| /openbsd/src/sys/dev/pci/drm/amd/display/dc/dml/dcn30/ |
| D | dcn30_fpu.c | 334 dc->current_state->bw_ctx.dml.ip.writeback_line_buffer_buffer_size); in dcn30_fpu_populate_dml_writeback_from_context()
371 if (!context->bw_ctx.bw.dcn.clk.fw_based_mclk_switching || in dcn30_fpu_update_soc_for_wm_a()
372 context->bw_ctx.dml.soc.dram_clock_change_latency_us == 0) in dcn30_fpu_update_soc_for_wm_a()
373 …context->bw_ctx.dml.soc.dram_clock_change_latency_us = dc->clk_mgr->bw_params->wm_table.nv_entries… in dcn30_fpu_update_soc_for_wm_a()
374 …context->bw_ctx.dml.soc.sr_enter_plus_exit_time_us = dc->clk_mgr->bw_params->wm_table.nv_entries[W… in dcn30_fpu_update_soc_for_wm_a()
375 …context->bw_ctx.dml.soc.sr_exit_time_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_A].dml_in… in dcn30_fpu_update_soc_for_wm_a()
385 int maxMpcComb = context->bw_ctx.dml.vba.maxMpcComb; in dcn30_fpu_calculate_wm_and_dlg()
387 double dcfclk = context->bw_ctx.dml.vba.DCFCLKState[vlevel][maxMpcComb]; in dcn30_fpu_calculate_wm_and_dlg()
388 …bool pstate_en = context->bw_ctx.dml.vba.DRAMClockChangeSupport[vlevel][maxMpcComb] != dm_dram_clo… in dcn30_fpu_calculate_wm_and_dlg()
394 context->bw_ctx.bw.dcn.clk.fw_based_mclk_switching = false; in dcn30_fpu_calculate_wm_and_dlg()
[all …]
|
| /openbsd/src/sys/dev/pci/drm/amd/display/dc/dml/dcn20/ |
| D | dcn20_fpu.c | 1040 …wb_arb_params->cli_watermark[k] = get_wm_writeback_urgent(&context->bw_ctx.dml, pipes, pipe_cnt) *… in dcn20_fpu_set_wb_arb_params()
1041 …wb_arb_params->pstate_watermark[k] = get_wm_writeback_dram_clock_change(&context->bw_ctx.dml, pipe… in dcn20_fpu_set_wb_arb_params()
1086 bool allow_z8 = context->bw_ctx.dml.vba.StutterPeriod > (double)minmum_z8_residency; in decide_zstate_support()
1096 if (is_pwrseq0 && context->bw_ctx.dml.vba.StutterPeriod > 5000.0) in decide_zstate_support()
1154 context->bw_ctx.bw.dcn.clk.dispclk_khz = context->bw_ctx.dml.vba.DISPCLK * 1000; in dcn20_calculate_dlg_params()
1155 context->bw_ctx.bw.dcn.clk.dcfclk_khz = context->bw_ctx.dml.vba.DCFCLK * 1000; in dcn20_calculate_dlg_params()
1156 context->bw_ctx.bw.dcn.clk.socclk_khz = context->bw_ctx.dml.vba.SOCCLK * 1000; in dcn20_calculate_dlg_params()
1157 context->bw_ctx.bw.dcn.clk.dramclk_khz = context->bw_ctx.dml.vba.DRAMSpeed * 1000 / 16; in dcn20_calculate_dlg_params()
1159 if (dc->debug.min_dram_clk_khz > context->bw_ctx.bw.dcn.clk.dramclk_khz) in dcn20_calculate_dlg_params()
1160 context->bw_ctx.bw.dcn.clk.dramclk_khz = dc->debug.min_dram_clk_khz; in dcn20_calculate_dlg_params()
[all …]
|
| /openbsd/src/sys/dev/pci/drm/amd/display/dc/core/ |
| D | dc_state.c | 189 memcpy(&state->bw_ctx.dml, &dc->dml, sizeof(struct display_mode_lib)); in init_state()
214 if (!dml2_create(dc, dml2_opt, &state->bw_ctx.dml2)) { in dc_state_create()
220 if (!dml2_create(dc, dml2_opt, &state->bw_ctx.dml2_dc_power_source)) { in dc_state_create()
236 struct dml2_context *dst_dml2 = dst_state->bw_ctx.dml2; in dc_state_copy()
237 struct dml2_context *dst_dml2_dc_power_source = dst_state->bw_ctx.dml2_dc_power_source; in dc_state_copy()
243 dst_state->bw_ctx.dml2 = dst_dml2; in dc_state_copy()
244 if (src_state->bw_ctx.dml2) in dc_state_copy()
245 dml2_copy(dst_state->bw_ctx.dml2, src_state->bw_ctx.dml2); in dc_state_copy()
247 dst_state->bw_ctx.dml2_dc_power_source = dst_dml2_dc_power_source; in dc_state_copy()
248 if (src_state->bw_ctx.dml2_dc_power_source) in dc_state_copy()
[all …]
|
| D | dc_debug.c | 353 context->bw_ctx.bw.dcn.clk.dispclk_khz, in context_clock_trace()
354 context->bw_ctx.bw.dcn.clk.dppclk_khz, in context_clock_trace()
355 context->bw_ctx.bw.dcn.clk.dcfclk_khz, in context_clock_trace()
356 context->bw_ctx.bw.dcn.clk.dcfclk_deep_sleep_khz, in context_clock_trace()
357 context->bw_ctx.bw.dcn.clk.fclk_khz, in context_clock_trace()
358 context->bw_ctx.bw.dcn.clk.socclk_khz); in context_clock_trace()
361 context->bw_ctx.bw.dcn.clk.dispclk_khz, in context_clock_trace()
362 context->bw_ctx.bw.dcn.clk.dppclk_khz, in context_clock_trace()
363 context->bw_ctx.bw.dcn.clk.dcfclk_khz, in context_clock_trace()
364 context->bw_ctx.bw.dcn.clk.dcfclk_deep_sleep_khz, in context_clock_trace()
[all …]
|
| D | amdgpu_dc.c | 2056 TRACE_DCN_CLOCK_STATE(&context->bw_ctx.bw.dcn.clk); in dc_commit_state_no_check()
2058 TRACE_DCE_CLOCK_STATE(&context->bw_ctx.bw.dce); in dc_commit_state_no_check()
2287 TRACE_DCE_CLOCK_STATE(&context->bw_ctx.bw.dce); in dc_post_update_surfaces_to_stream()
2289 TRACE_DCN_CLOCK_STATE(&context->bw_ctx.bw.dcn.clk); in dc_post_update_surfaces_to_stream()
2759 …if (!dc->clk_mgr->funcs->are_clock_states_equal(&dc->clk_mgr->clks, &dc->current_state->bw_ctx.bw.… in dc_check_update_surfaces_for_stream()
2762 …} else if (memcmp(&dc->current_state->bw_ctx.bw.dcn.clk, &dc->clk_mgr->clks, offsetof(struct dc_cl… in dc_check_update_surfaces_for_stream()
4875 TRACE_DCE_CLOCK_STATE(&context->bw_ctx.bw.dce); in update_planes_and_stream_v1()
5248 info->displayClock = (unsigned int)state->bw_ctx.bw.dcn.clk.dispclk_khz; in get_clock_requirements_for_state()
5249 info->engineClock = (unsigned int)state->bw_ctx.bw.dcn.clk.dcfclk_khz; in get_clock_requirements_for_state()
5250 info->memoryClock = (unsigned int)state->bw_ctx.bw.dcn.clk.dramclk_khz; in get_clock_requirements_for_state()
[all …]
|
| D | dc_hw_sequencer.c | 505 struct vba_vars_st *vba = &context->bw_ctx.dml.vba; in set_p_state_switch_method()
518 if (context->bw_ctx.bw.dcn.clk.fw_based_mclk_switching) { in set_p_state_switch_method()
|
| /openbsd/src/sys/dev/pci/drm/amd/display/dc/clk_mgr/dce110/ |
| D | dce110_clk_mgr.c | 183 context->bw_ctx.bw.dce.all_displays_in_sync; in dce11_pplib_apply_display_requirements()
185 context->bw_ctx.bw.dce.nbp_state_change_enable == false; in dce11_pplib_apply_display_requirements()
187 context->bw_ctx.bw.dce.cpuc_state_change_enable == false; in dce11_pplib_apply_display_requirements()
189 context->bw_ctx.bw.dce.cpup_state_change_enable == false; in dce11_pplib_apply_display_requirements()
191 context->bw_ctx.bw.dce.blackout_recovery_time_us; in dce11_pplib_apply_display_requirements()
205 pp_display_cfg->min_memory_clock_khz = context->bw_ctx.bw.dce.yclk_khz in dce11_pplib_apply_display_requirements()
211 context->bw_ctx.bw.dce.sclk_khz); in dce11_pplib_apply_display_requirements()
224 = context->bw_ctx.bw.dce.sclk_deep_sleep_khz; in dce11_pplib_apply_display_requirements()
255 int patched_disp_clk = context->bw_ctx.bw.dce.dispclk_khz; in dce11_update_clocks()
270 context->bw_ctx.bw.dce.dispclk_khz = dce_set_clock(clk_mgr_base, patched_disp_clk); in dce11_update_clocks()
|
| /openbsd/src/sys/dev/pci/drm/amd/display/dc/dce/ |
| D | dce_clk_mgr.c | 227 if (context->bw_ctx.bw.dce.dispclk_khz > in dce_get_required_clocks_state()
237 < context->bw_ctx.bw.dce.dispclk_khz) in dce_get_required_clocks_state()
619 context->bw_ctx.bw.dce.all_displays_in_sync; in dce11_pplib_apply_display_requirements()
621 context->bw_ctx.bw.dce.nbp_state_change_enable == false; in dce11_pplib_apply_display_requirements()
623 context->bw_ctx.bw.dce.cpuc_state_change_enable == false; in dce11_pplib_apply_display_requirements()
625 context->bw_ctx.bw.dce.cpup_state_change_enable == false; in dce11_pplib_apply_display_requirements()
627 context->bw_ctx.bw.dce.blackout_recovery_time_us; in dce11_pplib_apply_display_requirements()
629 pp_display_cfg->min_memory_clock_khz = context->bw_ctx.bw.dce.yclk_khz in dce11_pplib_apply_display_requirements()
634 context->bw_ctx.bw.dce.sclk_khz); in dce11_pplib_apply_display_requirements()
647 = context->bw_ctx.bw.dce.sclk_deep_sleep_khz; in dce11_pplib_apply_display_requirements()
[all …]
|
| /openbsd/src/sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn20/ |
| D | dcn20_clk_mgr.c | 221 struct dc_clocks *new_clocks = &context->bw_ctx.bw.dcn.clk; in dcn2_update_clocks()
349 struct dc_clocks *new_clocks = &context->bw_ctx.bw.dcn.clk; in dcn2_update_clocks_fpga()
456 clock_cfg->max_clock_khz = context->bw_ctx.bw.dcn.clk.max_supported_dispclk_khz; in dcn2_get_clock()
459 clock_cfg->bw_requirequired_clock_khz = context->bw_ctx.bw.dcn.clk.bw_dispclk_khz; in dcn2_get_clock()
462 clock_cfg->max_clock_khz = context->bw_ctx.bw.dcn.clk.max_supported_dppclk_khz; in dcn2_get_clock()
465 clock_cfg->bw_requirequired_clock_khz = context->bw_ctx.bw.dcn.clk.bw_dppclk_khz; in dcn2_get_clock()
|
| /openbsd/src/sys/dev/pci/drm/amd/display/dc/dcn10/ |
| D | dcn10_hw_sequencer_debug.c | 476 dc->current_state->bw_ctx.bw.dcn.clk.dcfclk_khz, in dcn10_get_clock_states()
477 dc->current_state->bw_ctx.bw.dcn.clk.dcfclk_deep_sleep_khz, in dcn10_get_clock_states()
478 dc->current_state->bw_ctx.bw.dcn.clk.dispclk_khz, in dcn10_get_clock_states()
479 dc->current_state->bw_ctx.bw.dcn.clk.dppclk_khz, in dcn10_get_clock_states()
480 dc->current_state->bw_ctx.bw.dcn.clk.fclk_khz, in dcn10_get_clock_states()
481 dc->current_state->bw_ctx.bw.dcn.clk.socclk_khz); in dcn10_get_clock_states()
|
| /openbsd/src/sys/dev/pci/drm/amd/display/dc/clk_mgr/dce100/ |
| D | dce_clk_mgr.c | 208 if (context->bw_ctx.bw.dce.dispclk_khz > in dce_get_required_clocks_state()
218 < context->bw_ctx.bw.dce.dispclk_khz) in dce_get_required_clocks_state()
403 int patched_disp_clk = context->bw_ctx.bw.dce.dispclk_khz; in dce_update_clocks()
|
| /openbsd/src/sys/dev/pci/drm/amd/display/dc/clk_mgr/dce120/ |
| D | dce120_clk_mgr.c | 91 int patched_disp_clk = context->bw_ctx.bw.dce.dispclk_khz; in dce12_update_clocks()
|
| /openbsd/src/sys/dev/pci/drm/amd/display/dc/clk_mgr/dce60/ |
| D | dce60_clk_mgr.c | 126 int patched_disp_clk = context->bw_ctx.bw.dce.dispclk_khz; in dce60_update_clocks()
|
| /openbsd/src/sys/dev/pci/drm/amd/display/amdgpu_dm/ |
| D | amdgpu_dm_helpers.c | 1219 dc_state->bw_ctx.bw.dcn.clk.p_state_change_support = false; in dm_helpers_dp_handle_test_pattern_request()
1220 dc_state->bw_ctx.bw.dcn.clk.dramclk_khz = clk_mgr->dc_mode_softmax_enabled ? in dm_helpers_dp_handle_test_pattern_request()
1222 dc_state->bw_ctx.bw.dcn.clk.idle_dramclk_khz = dc_state->bw_ctx.bw.dcn.clk.dramclk_khz; in dm_helpers_dp_handle_test_pattern_request()
|
| /openbsd/src/sys/dev/pci/drm/amd/display/dc/ |
| D | dc_dmub_srv.c | 920 wm_val_refclk = context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.pstate_change_ns * in dc_dmub_setup_subvp_dmub_command()
1708 …memcpy(&global_cmd->config.global, &context->bw_ctx.bw.dcn.fams2_global_config, sizeof(struct dmub… in dc_dmub_srv_fams2_update_config()
1716 for (i = 0; i < context->bw_ctx.bw.dcn.fams2_global_config.num_streams; i++) { in dc_dmub_srv_fams2_update_config()
1726 &context->bw_ctx.bw.dcn.fams2_stream_params[i], in dc_dmub_srv_fams2_update_config()
1735 if (enable && context->bw_ctx.bw.dcn.fams2_global_config.features.bits.enable) { in dc_dmub_srv_fams2_update_config()
1738 …cmd[context->bw_ctx.bw.dcn.fams2_global_config.num_streams].fams2_config.header.multi_cmd_pending … in dc_dmub_srv_fams2_update_config()
1739 num_cmds += context->bw_ctx.bw.dcn.fams2_global_config.num_streams; in dc_dmub_srv_fams2_update_config()
|
| /openbsd/src/sys/dev/pci/drm/amd/display/dc/dce60/ |
| D | dce60_resource.c | 881 context->bw_ctx.bw.dce.dispclk_khz = 681000; in dce60_validate_bandwidth()
882 context->bw_ctx.bw.dce.yclk_khz = 250000 * MEMORY_TYPE_MULTIPLIER_CZ; in dce60_validate_bandwidth()
884 context->bw_ctx.bw.dce.dispclk_khz = 0; in dce60_validate_bandwidth()
885 context->bw_ctx.bw.dce.yclk_khz = 0; in dce60_validate_bandwidth()
|
| /openbsd/src/sys/dev/pci/drm/amd/display/dc/clk_mgr/dce112/ |
| D | dce112_clk_mgr.c | 197 int patched_disp_clk = context->bw_ctx.bw.dce.dispclk_khz; in dce112_update_clocks()
|
| /openbsd/src/sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn10/ |
| D | rv1_clk_mgr.c | 194 struct dc_clocks *new_clocks = &context->bw_ctx.bw.dcn.clk; in rv1_update_clocks()
|
| /openbsd/src/sys/dev/pci/drm/amd/display/dc/inc/ |
| D | core_types.h | 622 struct bw_context bw_ctx; member
|
| /openbsd/src/sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn30/ |
| D | dcn30_clk_mgr.c | 197 struct dc_clocks *new_clocks = &context->bw_ctx.bw.dcn.clk; in dcn3_update_clocks()
|
| /openbsd/src/sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn21/ |
| D | rn_clk_mgr.c | 136 struct dc_clocks *new_clocks = &context->bw_ctx.bw.dcn.clk; in rn_update_clocks()
|