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Searched refs:mclk (Results 1 – 25 of 53) sorted by relevance

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/openbsd/src/sys/dev/pci/drm/radeon/
Dbtc_dpm.c1214 u32 *sclk, u32 *mclk) in btc_skip_blacklist_clocks() argument
1218 if ((sclk == NULL) || (mclk == NULL)) in btc_skip_blacklist_clocks()
1225 (btc_blacklist_clocks[i].mclk == *mclk)) in btc_skip_blacklist_clocks()
1234 btc_skip_blacklist_clocks(rdev, max_sclk, max_mclk, sclk, mclk); in btc_skip_blacklist_clocks()
1244 if ((pl->mclk == 0) || (pl->sclk == 0)) in btc_adjust_clock_combinations()
1247 if (pl->mclk == pl->sclk) in btc_adjust_clock_combinations()
1250 if (pl->mclk > pl->sclk) { in btc_adjust_clock_combinations()
1251 if (((pl->mclk + (pl->sclk - 1)) / pl->sclk) > rdev->pm.dpm.dyn_state.mclk_sclk_ratio) in btc_adjust_clock_combinations()
1254 (pl->mclk + in btc_adjust_clock_combinations()
1258 if ((pl->sclk - pl->mclk) > rdev->pm.dpm.dyn_state.sclk_mclk_delta) in btc_adjust_clock_combinations()
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Drv730_dpm.c118 LPRV7XX_SMC_MCLK_VALUE mclk) in rv730_populate_mclk_value() argument
183 mclk->mclk730.vMCLK_PWRMGT_CNTL = cpu_to_be32(mclk_pwrmgt_cntl); in rv730_populate_mclk_value()
184 mclk->mclk730.vDLL_CNTL = cpu_to_be32(dll_cntl); in rv730_populate_mclk_value()
185 mclk->mclk730.mclk_value = cpu_to_be32(memory_clock); in rv730_populate_mclk_value()
186 mclk->mclk730.vMPLL_FUNC_CNTL = cpu_to_be32(mpll_func_cntl); in rv730_populate_mclk_value()
187 mclk->mclk730.vMPLL_FUNC_CNTL2 = cpu_to_be32(mpll_func_cntl_2); in rv730_populate_mclk_value()
188 mclk->mclk730.vMPLL_FUNC_CNTL3 = cpu_to_be32(mpll_func_cntl_3); in rv730_populate_mclk_value()
189 mclk->mclk730.vMPLL_SS = cpu_to_be32(mpll_ss); in rv730_populate_mclk_value()
190 mclk->mclk730.vMPLL_SS2 = cpu_to_be32(mpll_ss2); in rv730_populate_mclk_value()
294 table->ACPIState.levels[0].mclk.mclk730.vMPLL_FUNC_CNTL = cpu_to_be32(mpll_func_cntl); in rv730_populate_smc_acpi_state()
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Drv740_dpm.c187 RV7XX_SMC_MCLK_VALUE *mclk) in rv740_populate_mclk_value() argument
274 mclk->mclk770.mclk_value = cpu_to_be32(memory_clock); in rv740_populate_mclk_value()
275 mclk->mclk770.vMPLL_AD_FUNC_CNTL = cpu_to_be32(mpll_ad_func_cntl); in rv740_populate_mclk_value()
276 mclk->mclk770.vMPLL_AD_FUNC_CNTL_2 = cpu_to_be32(mpll_ad_func_cntl_2); in rv740_populate_mclk_value()
277 mclk->mclk770.vMPLL_DQ_FUNC_CNTL = cpu_to_be32(mpll_dq_func_cntl); in rv740_populate_mclk_value()
278 mclk->mclk770.vMPLL_DQ_FUNC_CNTL_2 = cpu_to_be32(mpll_dq_func_cntl_2); in rv740_populate_mclk_value()
279 mclk->mclk770.vMCLK_PWRMGT_CNTL = cpu_to_be32(mclk_pwrmgt_cntl); in rv740_populate_mclk_value()
280 mclk->mclk770.vDLL_CNTL = cpu_to_be32(dll_cntl); in rv740_populate_mclk_value()
281 mclk->mclk770.vMPLL_SS = cpu_to_be32(mpll_ss1); in rv740_populate_mclk_value()
282 mclk->mclk770.vMPLL_SS2 = cpu_to_be32(mpll_ss2); in rv740_populate_mclk_value()
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Drv770_dpm.c389 RV7XX_SMC_MCLK_VALUE *mclk) in rv770_populate_mclk_value() argument
474 mclk->mclk770.mclk_value = cpu_to_be32(memory_clock); in rv770_populate_mclk_value()
475 mclk->mclk770.vMPLL_AD_FUNC_CNTL = cpu_to_be32(mpll_ad_func_cntl); in rv770_populate_mclk_value()
476 mclk->mclk770.vMPLL_AD_FUNC_CNTL_2 = cpu_to_be32(mpll_ad_func_cntl_2); in rv770_populate_mclk_value()
477 mclk->mclk770.vMPLL_DQ_FUNC_CNTL = cpu_to_be32(mpll_dq_func_cntl); in rv770_populate_mclk_value()
478 mclk->mclk770.vMPLL_DQ_FUNC_CNTL_2 = cpu_to_be32(mpll_dq_func_cntl_2); in rv770_populate_mclk_value()
479 mclk->mclk770.vMCLK_PWRMGT_CNTL = cpu_to_be32(mclk_pwrmgt_cntl); in rv770_populate_mclk_value()
480 mclk->mclk770.vDLL_CNTL = cpu_to_be32(dll_cntl); in rv770_populate_mclk_value()
593 int rv770_populate_mvdd_value(struct radeon_device *rdev, u32 mclk, in rv770_populate_mvdd_value() argument
604 if (mclk <= pi->mvdd_split_frequency) { in rv770_populate_mvdd_value()
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Dcypress_dpm.c422 u8 cypress_get_strobe_mode_settings(struct radeon_device *rdev, u32 mclk) in cypress_get_strobe_mode_settings() argument
429 if (mclk <= pi->mclk_strobe_mode_threshold) in cypress_get_strobe_mode_settings()
431 result = cypress_get_mclk_frequency_ratio(rdev, mclk, strobe_mode); in cypress_get_strobe_mode_settings()
474 RV7XX_SMC_MCLK_VALUE *mclk, in cypress_populate_mclk_value() argument
600 mclk->mclk770.mclk_value = cpu_to_be32(memory_clock); in cypress_populate_mclk_value()
601 mclk->mclk770.vMPLL_AD_FUNC_CNTL = cpu_to_be32(mpll_ad_func_cntl); in cypress_populate_mclk_value()
602 mclk->mclk770.vMPLL_AD_FUNC_CNTL_2 = cpu_to_be32(mpll_ad_func_cntl_2); in cypress_populate_mclk_value()
603 mclk->mclk770.vMPLL_DQ_FUNC_CNTL = cpu_to_be32(mpll_dq_func_cntl); in cypress_populate_mclk_value()
604 mclk->mclk770.vMPLL_DQ_FUNC_CNTL_2 = cpu_to_be32(mpll_dq_func_cntl_2); in cypress_populate_mclk_value()
605 mclk->mclk770.vMCLK_PWRMGT_CNTL = cpu_to_be32(mclk_pwrmgt_cntl); in cypress_populate_mclk_value()
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Dni_dpm.c791 u32 mclk; in ni_apply_state_adjust_rules() local
808 if (ps->performance_levels[i].mclk > max_limits->mclk) in ni_apply_state_adjust_rules()
809 ps->performance_levels[i].mclk = max_limits->mclk; in ni_apply_state_adjust_rules()
823 ps->performance_levels[0].mclk = in ni_apply_state_adjust_rules()
824 ps->performance_levels[ps->performance_level_count - 1].mclk; in ni_apply_state_adjust_rules()
829 btc_skip_blacklist_clocks(rdev, max_limits->sclk, max_limits->mclk, in ni_apply_state_adjust_rules()
831 &ps->performance_levels[0].mclk); in ni_apply_state_adjust_rules()
842 mclk = ps->performance_levels[0].mclk; in ni_apply_state_adjust_rules()
845 if (mclk < ps->performance_levels[i].mclk) in ni_apply_state_adjust_rules()
846 mclk = ps->performance_levels[i].mclk; in ni_apply_state_adjust_rules()
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Dsi_dpm.c2909 u32 mclk, sclk; in si_apply_state_adjust_rules() local
2973 if (ps->performance_levels[i].mclk > max_limits->mclk) in si_apply_state_adjust_rules()
2974 ps->performance_levels[i].mclk = max_limits->mclk; in si_apply_state_adjust_rules()
2998 if (ps->performance_levels[i].mclk > max_mclk_vddci) in si_apply_state_adjust_rules()
2999 ps->performance_levels[i].mclk = max_mclk_vddci; in si_apply_state_adjust_rules()
3002 if (ps->performance_levels[i].mclk > max_mclk_vddc) in si_apply_state_adjust_rules()
3003 ps->performance_levels[i].mclk = max_mclk_vddc; in si_apply_state_adjust_rules()
3006 if (ps->performance_levels[i].mclk > max_mclk) in si_apply_state_adjust_rules()
3007 ps->performance_levels[i].mclk = max_mclk; in si_apply_state_adjust_rules()
3018 mclk = ps->performance_levels[ps->performance_level_count - 1].mclk; in si_apply_state_adjust_rules()
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Dci_dpm.c772 u32 sclk, mclk; in ci_apply_state_adjust_rules() local
801 if (ps->performance_levels[i].mclk > max_limits->mclk) in ci_apply_state_adjust_rules()
802 ps->performance_levels[i].mclk = max_limits->mclk; in ci_apply_state_adjust_rules()
811 mclk = ps->performance_levels[ps->performance_level_count - 1].mclk; in ci_apply_state_adjust_rules()
814 mclk = ps->performance_levels[0].mclk; in ci_apply_state_adjust_rules()
821 if (mclk < rdev->pm.dpm.vce_states[rdev->pm.dpm.vce_level].mclk) in ci_apply_state_adjust_rules()
822 mclk = rdev->pm.dpm.vce_states[rdev->pm.dpm.vce_level].mclk; in ci_apply_state_adjust_rules()
826 ps->performance_levels[0].mclk = mclk; in ci_apply_state_adjust_rules()
832 if (ps->performance_levels[0].mclk < ps->performance_levels[1].mclk) in ci_apply_state_adjust_rules()
833 ps->performance_levels[0].mclk = ps->performance_levels[1].mclk; in ci_apply_state_adjust_rules()
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Drv770_dpm.h144 u32 mclk; member
185 LPRV7XX_SMC_MCLK_VALUE mclk);
206 RV7XX_SMC_MCLK_VALUE *mclk);
220 int rv770_populate_mvdd_value(struct radeon_device *rdev, u32 mclk,
Drv6xx_dpm.c456 state->high.mclk; in rv6xx_calculate_memory_clock_stepping_parameters()
458 state->high.mclk; in rv6xx_calculate_memory_clock_stepping_parameters()
460 state->medium.mclk; in rv6xx_calculate_memory_clock_stepping_parameters()
462 state->low.mclk; in rv6xx_calculate_memory_clock_stepping_parameters()
466 if (state->high.mclk == state->medium.mclk) in rv6xx_calculate_memory_clock_stepping_parameters()
473 if (state->medium.mclk == state->low.mclk) in rv6xx_calculate_memory_clock_stepping_parameters()
1821 u32 sclk, mclk; in rv6xx_parse_pplib_clock_info() local
1840 mclk = le16_to_cpu(clock_info->r600.usMemoryClockLow); in rv6xx_parse_pplib_clock_info()
1841 mclk |= clock_info->r600.ucMemoryClockHigh << 16; in rv6xx_parse_pplib_clock_info()
1843 pl->mclk = mclk; in rv6xx_parse_pplib_clock_info()
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Dradeon_clocks.c77 uint32_t fb_div, ref_div, post_div, mclk; in radeon_legacy_get_memory_clock() local
90 mclk = fb_div / ref_div; in radeon_legacy_get_memory_clock()
94 mclk >>= 1; in radeon_legacy_get_memory_clock()
96 mclk >>= 2; in radeon_legacy_get_memory_clock()
98 mclk >>= 3; in radeon_legacy_get_memory_clock()
100 return mclk; in radeon_legacy_get_memory_clock()
Dradeon_atombios.c2145 rdev->pm.power_state[state_index].clock_info[0].mclk = in radeon_atombios_parse_power_table_1_3()
2150 if ((rdev->pm.power_state[state_index].clock_info[0].mclk == 0) || in radeon_atombios_parse_power_table_1_3()
2180 rdev->pm.power_state[state_index].clock_info[0].mclk = in radeon_atombios_parse_power_table_1_3()
2185 if ((rdev->pm.power_state[state_index].clock_info[0].mclk == 0) || in radeon_atombios_parse_power_table_1_3()
2216 rdev->pm.power_state[state_index].clock_info[0].mclk = in radeon_atombios_parse_power_table_1_3()
2221 if ((rdev->pm.power_state[state_index].clock_info[0].mclk == 0) || in radeon_atombios_parse_power_table_1_3()
2456 rdev->pm.default_mclk = rdev->pm.power_state[state_index].clock_info[0].mclk; in radeon_atombios_parse_pplib_non_clock_info()
2468 rdev->pm.power_state[state_index].clock_info[j].mclk = in radeon_atombios_parse_pplib_non_clock_info()
2487 u32 sclk, mclk; in radeon_atombios_parse_pplib_clock_info() local
2503 mclk = le16_to_cpu(clock_info->ci.usMemoryClockLow); in radeon_atombios_parse_pplib_clock_info()
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Dradeon_pm.c175 u32 sclk, mclk; in radeon_set_power_state() local
197 mclk = rdev->pm.power_state[rdev->pm.requested_power_state_index]. in radeon_set_power_state()
198 clock_info[rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx].mclk; in radeon_set_power_state()
200 mclk = rdev->pm.power_state[rdev->pm.requested_power_state_index]. in radeon_set_power_state()
201 clock_info[rdev->pm.requested_clock_mode_index].mclk; in radeon_set_power_state()
203 if (mclk > rdev->pm.default_mclk) in radeon_set_power_state()
204 mclk = rdev->pm.default_mclk; in radeon_set_power_state()
233 if (rdev->asic->pm.set_memory_clock && (mclk != rdev->pm.current_mclk)) { in radeon_set_power_state()
235 radeon_set_memory_clock(rdev, mclk); in radeon_set_power_state()
237 rdev->pm.current_mclk = mclk; in radeon_set_power_state()
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Dbtc_dpm.h46 u32 *sclk, u32 *mclk);
Drv6xx_dpm.h80 u32 mclk; member
Dcypress_dpm.h158 u8 cypress_get_strobe_mode_settings(struct radeon_device *rdev, u32 mclk);
Dradeon_device.c741 u32 mclk = rdev->pm.current_mclk; in radeon_update_bandwidth_info() local
747 rdev->pm.mclk.full = dfixed_const(mclk); in radeon_update_bandwidth_info()
748 rdev->pm.mclk.full = dfixed_div(rdev->pm.mclk, a); in radeon_update_bandwidth_info()
Drv770_smc.h103 RV7XX_SMC_MCLK_VALUE mclk; member
/openbsd/src/sys/dev/pci/drm/amd/pm/powerplay/smumgr/
Diceland_smumgr.c1047 SMU71_Discrete_MemoryLevel *mclk, in iceland_calculate_mclk_params() argument
1155 mclk->MclkFrequency = memory_clock; in iceland_calculate_mclk_params()
1156 mclk->MpllFuncCntl = mpll_func_cntl; in iceland_calculate_mclk_params()
1157 mclk->MpllFuncCntl_1 = mpll_func_cntl_1; in iceland_calculate_mclk_params()
1158 mclk->MpllFuncCntl_2 = mpll_func_cntl_2; in iceland_calculate_mclk_params()
1159 mclk->MpllAdFuncCntl = mpll_ad_func_cntl; in iceland_calculate_mclk_params()
1160 mclk->MpllDqFuncCntl = mpll_dq_func_cntl; in iceland_calculate_mclk_params()
1161 mclk->MclkPwrmgtCntl = mclk_pwrmgt_cntl; in iceland_calculate_mclk_params()
1162 mclk->DllCntl = dll_cntl; in iceland_calculate_mclk_params()
1163 mclk->MpllSs1 = mpll_ss1; in iceland_calculate_mclk_params()
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Dci_smumgr.c1026 SMU7_Discrete_MemoryLevel *mclk, in ci_calculate_mclk_params() argument
1105 mclk->MclkFrequency = memory_clock; in ci_calculate_mclk_params()
1106 mclk->MpllFuncCntl = mpll_func_cntl; in ci_calculate_mclk_params()
1107 mclk->MpllFuncCntl_1 = mpll_func_cntl_1; in ci_calculate_mclk_params()
1108 mclk->MpllFuncCntl_2 = mpll_func_cntl_2; in ci_calculate_mclk_params()
1109 mclk->MpllAdFuncCntl = mpll_ad_func_cntl; in ci_calculate_mclk_params()
1110 mclk->MpllDqFuncCntl = mpll_dq_func_cntl; in ci_calculate_mclk_params()
1111 mclk->MclkPwrmgtCntl = mclk_pwrmgt_cntl; in ci_calculate_mclk_params()
1112 mclk->DllCntl = dll_cntl; in ci_calculate_mclk_params()
1113 mclk->MpllSs1 = mpll_ss1; in ci_calculate_mclk_params()
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Dtonga_smumgr.c790 SMU72_Discrete_MemoryLevel *mclk, in tonga_calculate_mclk_params() argument
906 mclk->MclkFrequency = memory_clock; in tonga_calculate_mclk_params()
907 mclk->MpllFuncCntl = mpll_func_cntl; in tonga_calculate_mclk_params()
908 mclk->MpllFuncCntl_1 = mpll_func_cntl_1; in tonga_calculate_mclk_params()
909 mclk->MpllFuncCntl_2 = mpll_func_cntl_2; in tonga_calculate_mclk_params()
910 mclk->MpllAdFuncCntl = mpll_ad_func_cntl; in tonga_calculate_mclk_params()
911 mclk->MpllDqFuncCntl = mpll_dq_func_cntl; in tonga_calculate_mclk_params()
912 mclk->MclkPwrmgtCntl = mclk_pwrmgt_cntl; in tonga_calculate_mclk_params()
913 mclk->DllCntl = dll_cntl; in tonga_calculate_mclk_params()
914 mclk->MpllSs1 = mpll_ss1; in tonga_calculate_mclk_params()
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/openbsd/src/sys/dev/pci/drm/amd/pm/powerplay/hwmgr/
Dsmu7_hwmgr.c2472 table_info->max_clock_voltage_on_ac.mclk = in smu7_set_private_data_based_on_pptable_v1()
2484 hwmgr->dyn_state.max_clock_voltage_on_ac.mclk = table_info->max_clock_voltage_on_ac.mclk; in smu7_set_private_data_based_on_pptable_v1()
2868 hwmgr->dyn_state.max_clock_voltage_on_ac.mclk = in smu7_set_private_data_based_on_pptable_v0()
3319 uint32_t mclk; in smu7_apply_state_adjust_rules() local
3349 if (smu7_ps->performance_levels[i].memory_clock > max_limits->mclk) in smu7_apply_state_adjust_rules()
3350 smu7_ps->performance_levels[i].memory_clock = max_limits->mclk; in smu7_apply_state_adjust_rules()
3377 stable_pstate_mclk = max_limits->mclk; in smu7_apply_state_adjust_rules()
3403 mclk = smu7_ps->performance_levels[0].memory_clock; in smu7_apply_state_adjust_rules()
3408 mclk = smu7_ps->performance_levels in smu7_apply_state_adjust_rules()
3415 if (mclk < minimum_clocks.memoryClock) in smu7_apply_state_adjust_rules()
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Dvega10_hwmgr.c796 table_info->max_clock_voltage_on_ac.mclk = in vega10_set_private_data_based_on_pptable()
805 hwmgr->dyn_state.max_clock_voltage_on_ac.mclk = in vega10_set_private_data_based_on_pptable()
806 table_info->max_clock_voltage_on_ac.mclk; in vega10_set_private_data_based_on_pptable()
3283 uint32_t mclk; in vega10_apply_state_adjust_rules() local
3317 max_limits->mclk) in vega10_apply_state_adjust_rules()
3319 max_limits->mclk; in vega10_apply_state_adjust_rules()
3357 stable_pstate_mclk = max_limits->mclk; in vega10_apply_state_adjust_rules()
3379 mclk = vega10_ps->performance_levels[0].mem_clock; in vega10_apply_state_adjust_rules()
3385 if (mclk < minimum_clocks.memoryClock) in vega10_apply_state_adjust_rules()
3386 mclk = (minimum_clocks.memoryClock > max_limits->mclk) ? in vega10_apply_state_adjust_rules()
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/openbsd/src/sys/dev/pci/drm/amd/display/dc/
Ddm_services_types.h64 struct dm_pp_clock_range mclk; member
/openbsd/src/sys/dev/pci/drm/amd/amdgpu/
Damdgpu_atombios.h95 u32 mclk[MAX_AC_TIMING_ENTRIES]; member

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