1 /*-
2 * Copyright 2015 John Wehle <john@feith.com>
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 *
14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
24 * SUCH DAMAGE.
25 */
26
27 /*
28 * Amlogic aml8726-m8 (and later) SDXC host controller driver.
29 */
30
31 #include <sys/cdefs.h>
32 __FBSDID("$FreeBSD$");
33
34 #include <sys/param.h>
35 #include <sys/systm.h>
36 #include <sys/conf.h>
37 #include <sys/bus.h>
38 #include <sys/kernel.h>
39 #include <sys/module.h>
40 #include <sys/lock.h>
41 #include <sys/mutex.h>
42 #include <sys/resource.h>
43 #include <sys/rman.h>
44
45 #include <sys/gpio.h>
46
47 #include <machine/bus.h>
48 #include <machine/cpu.h>
49
50 #include <dev/fdt/fdt_common.h>
51 #include <dev/ofw/ofw_bus.h>
52 #include <dev/ofw/ofw_bus_subr.h>
53
54 #include <dev/mmc/bridge.h>
55 #include <dev/mmc/mmcreg.h>
56 #include <dev/mmc/mmcbrvar.h>
57
58 #include <arm/amlogic/aml8726/aml8726_soc.h>
59 #include <arm/amlogic/aml8726/aml8726_sdxc-m8.h>
60
61 #include "gpio_if.h"
62 #include "mmcbr_if.h"
63
64 /*
65 * The table is sorted from highest to lowest and
66 * last entry in the table is mark by freq == 0.
67 */
68 struct {
69 uint32_t voltage;
70 uint32_t freq;
71 uint32_t rx_phase;
72 } aml8726_sdxc_clk_phases[] = {
73 {
74 MMC_OCR_LOW_VOLTAGE | MMC_OCR_320_330 | MMC_OCR_330_340,
75 100000000,
76 1
77 },
78 {
79 MMC_OCR_320_330 | MMC_OCR_330_340,
80 45000000,
81 15
82 },
83 {
84 MMC_OCR_LOW_VOLTAGE,
85 45000000,
86 11
87 },
88 {
89 MMC_OCR_LOW_VOLTAGE | MMC_OCR_320_330 | MMC_OCR_330_340,
90 24999999,
91 15
92 },
93 {
94 MMC_OCR_LOW_VOLTAGE | MMC_OCR_320_330 | MMC_OCR_330_340,
95 5000000,
96 23
97 },
98 {
99 MMC_OCR_LOW_VOLTAGE | MMC_OCR_320_330 | MMC_OCR_330_340,
100 1000000,
101 55
102 },
103 {
104 MMC_OCR_LOW_VOLTAGE | MMC_OCR_320_330 | MMC_OCR_330_340,
105 0,
106 1061
107 },
108 };
109
110 struct aml8726_sdxc_gpio {
111 device_t dev;
112 uint32_t pin;
113 uint32_t pol;
114 };
115
116 struct aml8726_sdxc_softc {
117 device_t dev;
118 boolean_t auto_fill_flush;
119 struct resource *res[2];
120 struct mtx mtx;
121 struct callout ch;
122 unsigned int ref_freq;
123 struct aml8726_sdxc_gpio pwr_en;
124 int voltages[2];
125 struct aml8726_sdxc_gpio vselect;
126 struct aml8726_sdxc_gpio card_rst;
127 bus_dma_tag_t dmatag;
128 bus_dmamap_t dmamap;
129 void *ih_cookie;
130 struct mmc_host host;
131 int bus_busy;
132 struct {
133 uint32_t time;
134 uint32_t error;
135 } busy;
136 struct mmc_command *cmd;
137 };
138
139 static struct resource_spec aml8726_sdxc_spec[] = {
140 { SYS_RES_MEMORY, 0, RF_ACTIVE },
141 { SYS_RES_IRQ, 0, RF_ACTIVE },
142 { -1, 0 }
143 };
144
145 #define AML_SDXC_LOCK(sc) mtx_lock(&(sc)->mtx)
146 #define AML_SDXC_UNLOCK(sc) mtx_unlock(&(sc)->mtx)
147 #define AML_SDXC_LOCK_ASSERT(sc) mtx_assert(&(sc)->mtx, MA_OWNED)
148 #define AML_SDXC_LOCK_INIT(sc) \
149 mtx_init(&(sc)->mtx, device_get_nameunit((sc)->dev), \
150 "sdxc", MTX_DEF)
151 #define AML_SDXC_LOCK_DESTROY(sc) mtx_destroy(&(sc)->mtx);
152
153 #define CSR_WRITE_4(sc, reg, val) bus_write_4((sc)->res[0], reg, (val))
154 #define CSR_READ_4(sc, reg) bus_read_4((sc)->res[0], reg)
155 #define CSR_BARRIER(sc, reg) bus_barrier((sc)->res[0], reg, 4, \
156 (BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE))
157
158 #define PIN_ON_FLAG(pol) ((pol) == 0 ? \
159 GPIO_PIN_LOW : GPIO_PIN_HIGH)
160 #define PIN_OFF_FLAG(pol) ((pol) == 0 ? \
161 GPIO_PIN_HIGH : GPIO_PIN_LOW)
162
163 #define msecs_to_ticks(ms) (((ms)*hz)/1000 + 1)
164
165 static void aml8726_sdxc_timeout(void *arg);
166
167 static void
aml8726_sdxc_mapmem(void * arg,bus_dma_segment_t * segs,int nseg,int error)168 aml8726_sdxc_mapmem(void *arg, bus_dma_segment_t *segs, int nseg, int error)
169 {
170 bus_addr_t *busaddrp;
171
172 /*
173 * There should only be one bus space address since
174 * bus_dma_tag_create was called with nsegments = 1.
175 */
176
177 busaddrp = (bus_addr_t *)arg;
178 *busaddrp = segs->ds_addr;
179 }
180
181 static int
aml8726_sdxc_power_off(struct aml8726_sdxc_softc * sc)182 aml8726_sdxc_power_off(struct aml8726_sdxc_softc *sc)
183 {
184
185 if (sc->pwr_en.dev == NULL)
186 return (0);
187
188 return (GPIO_PIN_SET(sc->pwr_en.dev, sc->pwr_en.pin,
189 PIN_OFF_FLAG(sc->pwr_en.pol)));
190 }
191
192 static int
aml8726_sdxc_power_on(struct aml8726_sdxc_softc * sc)193 aml8726_sdxc_power_on(struct aml8726_sdxc_softc *sc)
194 {
195
196 if (sc->pwr_en.dev == NULL)
197 return (0);
198
199 return (GPIO_PIN_SET(sc->pwr_en.dev, sc->pwr_en.pin,
200 PIN_ON_FLAG(sc->pwr_en.pol)));
201 }
202
203 static void
aml8726_sdxc_soft_reset(struct aml8726_sdxc_softc * sc)204 aml8726_sdxc_soft_reset(struct aml8726_sdxc_softc *sc)
205 {
206
207 CSR_WRITE_4(sc, AML_SDXC_SOFT_RESET_REG, AML_SDXC_SOFT_RESET);
208 CSR_BARRIER(sc, AML_SDXC_SOFT_RESET_REG);
209 DELAY(5);
210 }
211
212 static void
aml8726_sdxc_engage_dma(struct aml8726_sdxc_softc * sc)213 aml8726_sdxc_engage_dma(struct aml8726_sdxc_softc *sc)
214 {
215 int i;
216 uint32_t pdmar;
217 uint32_t sr;
218 struct mmc_data *data;
219
220 data = sc->cmd->data;
221
222 if (data == NULL || data->len == 0)
223 return;
224
225 /*
226 * Engaging the DMA hardware is recommended before writing
227 * to AML_SDXC_SEND_REG so that the FIFOs are ready to go.
228 *
229 * Presumably AML_SDXC_CNTRL_REG and AML_SDXC_DMA_ADDR_REG
230 * must be set up prior to this happening.
231 */
232
233 pdmar = CSR_READ_4(sc, AML_SDXC_PDMA_REG);
234
235 pdmar &= ~AML_SDXC_PDMA_RX_FLUSH_MODE_SW;
236 pdmar |= AML_SDXC_PDMA_DMA_EN;
237
238 if (sc->auto_fill_flush == true) {
239 CSR_WRITE_4(sc, AML_SDXC_PDMA_REG, pdmar);
240 CSR_BARRIER(sc, AML_SDXC_PDMA_REG);
241 return;
242 }
243
244 if ((data->flags & MMC_DATA_READ) != 0) {
245 pdmar |= AML_SDXC_PDMA_RX_FLUSH_MODE_SW;
246 CSR_WRITE_4(sc, AML_SDXC_PDMA_REG, pdmar);
247 CSR_BARRIER(sc, AML_SDXC_PDMA_REG);
248 } else {
249 pdmar |= AML_SDXC_PDMA_TX_FILL;
250 CSR_WRITE_4(sc, AML_SDXC_PDMA_REG, pdmar);
251 CSR_BARRIER(sc, AML_SDXC_PDMA_REG);
252
253 /*
254 * Wait up to 100us for data to show up.
255 */
256 for (i = 0; i < 100; i++) {
257 sr = CSR_READ_4(sc, AML_SDXC_STATUS_REG);
258 if ((sr & AML_SDXC_STATUS_TX_CNT_MASK) != 0)
259 break;
260 DELAY(1);
261 }
262 if (i >= 100)
263 device_printf(sc->dev, "TX FIFO fill timeout\n");
264 }
265 }
266
267 static void
aml8726_sdxc_disengage_dma(struct aml8726_sdxc_softc * sc)268 aml8726_sdxc_disengage_dma(struct aml8726_sdxc_softc *sc)
269 {
270 int i;
271 uint32_t pdmar;
272 uint32_t sr;
273 struct mmc_data *data;
274
275 data = sc->cmd->data;
276
277 if (data == NULL || data->len == 0)
278 return;
279
280 pdmar = CSR_READ_4(sc, AML_SDXC_PDMA_REG);
281
282 if (sc->auto_fill_flush == true) {
283 pdmar &= ~AML_SDXC_PDMA_DMA_EN;
284 CSR_WRITE_4(sc, AML_SDXC_PDMA_REG, pdmar);
285 CSR_BARRIER(sc, AML_SDXC_PDMA_REG);
286 return;
287 }
288
289 if ((data->flags & MMC_DATA_READ) != 0) {
290 pdmar |= AML_SDXC_PDMA_RX_FLUSH_NOW;
291 CSR_WRITE_4(sc, AML_SDXC_PDMA_REG, pdmar);
292 CSR_BARRIER(sc, AML_SDXC_PDMA_REG);
293
294 /*
295 * Wait up to 100us for data to drain.
296 */
297 for (i = 0; i < 100; i++) {
298 sr = CSR_READ_4(sc, AML_SDXC_STATUS_REG);
299 if ((sr & AML_SDXC_STATUS_RX_CNT_MASK) == 0)
300 break;
301 DELAY(1);
302 }
303 if (i >= 100)
304 device_printf(sc->dev, "RX FIFO drain timeout\n");
305 }
306
307 pdmar &= ~(AML_SDXC_PDMA_DMA_EN | AML_SDXC_PDMA_RX_FLUSH_MODE_SW);
308
309 CSR_WRITE_4(sc, AML_SDXC_PDMA_REG, pdmar);
310 CSR_BARRIER(sc, AML_SDXC_PDMA_REG);
311 }
312
313 static int
aml8726_sdxc_start_command(struct aml8726_sdxc_softc * sc,struct mmc_command * cmd)314 aml8726_sdxc_start_command(struct aml8726_sdxc_softc *sc,
315 struct mmc_command *cmd)
316 {
317 bus_addr_t baddr;
318 uint32_t block_size;
319 uint32_t ctlr;
320 uint32_t ier;
321 uint32_t sndr;
322 uint32_t timeout;
323 int error;
324 struct mmc_data *data;
325
326 AML_SDXC_LOCK_ASSERT(sc);
327
328 if (cmd->opcode > 0x3f)
329 return (MMC_ERR_INVALID);
330
331 /*
332 * Ensure the hardware state machine is in a known state.
333 */
334 aml8726_sdxc_soft_reset(sc);
335
336 sndr = cmd->opcode;
337
338 if ((cmd->flags & MMC_RSP_136) != 0) {
339 sndr |= AML_SDXC_SEND_CMD_HAS_RESP;
340 sndr |= AML_SDXC_SEND_RESP_136;
341 /*
342 * According to the SD spec the 136 bit response is
343 * used for getting the CID or CSD in which case the
344 * CRC7 is embedded in the contents rather than being
345 * calculated over the entire response (the controller
346 * always checks the CRC7 over the entire response).
347 */
348 sndr |= AML_SDXC_SEND_RESP_NO_CRC7_CHECK;
349 } else if ((cmd->flags & MMC_RSP_PRESENT) != 0)
350 sndr |= AML_SDXC_SEND_CMD_HAS_RESP;
351
352 if ((cmd->flags & MMC_RSP_CRC) == 0)
353 sndr |= AML_SDXC_SEND_RESP_NO_CRC7_CHECK;
354
355 if (cmd->opcode == MMC_STOP_TRANSMISSION)
356 sndr |= AML_SDXC_SEND_DATA_STOP;
357
358 data = cmd->data;
359
360 baddr = 0;
361 ctlr = CSR_READ_4(sc, AML_SDXC_CNTRL_REG);
362 ier = AML_SDXC_IRQ_ENABLE_STANDARD;
363 timeout = AML_SDXC_CMD_TIMEOUT;
364
365 ctlr &= ~AML_SDXC_CNTRL_PKG_LEN_MASK;
366
367 if (data && data->len &&
368 (data->flags & (MMC_DATA_READ | MMC_DATA_WRITE)) != 0) {
369 block_size = data->len;
370
371 if ((data->flags & MMC_DATA_MULTI) != 0) {
372 block_size = MMC_SECTOR_SIZE;
373 if ((data->len % block_size) != 0)
374 return (MMC_ERR_INVALID);
375 }
376
377 if (block_size > 512)
378 return (MMC_ERR_INVALID);
379
380 sndr |= AML_SDXC_SEND_CMD_HAS_DATA;
381 sndr |= ((data->flags & MMC_DATA_WRITE) != 0) ?
382 AML_SDXC_SEND_DATA_WRITE : 0;
383 sndr |= (((data->len / block_size) - 1) <<
384 AML_SDXC_SEND_REP_PKG_CNT_SHIFT);
385
386 ctlr |= ((block_size < 512) ? block_size : 0) <<
387 AML_SDXC_CNTRL_PKG_LEN_SHIFT;
388
389 ier &= ~AML_SDXC_IRQ_ENABLE_RESP_OK;
390 ier |= (sc->auto_fill_flush == true ||
391 (data->flags & MMC_DATA_WRITE) != 0) ?
392 AML_SDXC_IRQ_ENABLE_DMA_DONE :
393 AML_SDXC_IRQ_ENABLE_TRANSFER_DONE_OK;
394
395 error = bus_dmamap_load(sc->dmatag, sc->dmamap,
396 data->data, data->len, aml8726_sdxc_mapmem, &baddr,
397 BUS_DMA_NOWAIT);
398 if (error)
399 return (MMC_ERR_NO_MEMORY);
400
401 if ((data->flags & MMC_DATA_READ) != 0) {
402 bus_dmamap_sync(sc->dmatag, sc->dmamap,
403 BUS_DMASYNC_PREREAD);
404 timeout = AML_SDXC_READ_TIMEOUT *
405 (data->len / block_size);
406 } else {
407 bus_dmamap_sync(sc->dmatag, sc->dmamap,
408 BUS_DMASYNC_PREWRITE);
409 timeout = AML_SDXC_WRITE_TIMEOUT *
410 (data->len / block_size);
411 }
412 }
413
414 sc->cmd = cmd;
415
416 cmd->error = MMC_ERR_NONE;
417
418 sc->busy.time = 0;
419 sc->busy.error = MMC_ERR_NONE;
420
421 if (timeout > AML_SDXC_MAX_TIMEOUT)
422 timeout = AML_SDXC_MAX_TIMEOUT;
423
424 callout_reset(&sc->ch, msecs_to_ticks(timeout),
425 aml8726_sdxc_timeout, sc);
426
427 CSR_WRITE_4(sc, AML_SDXC_IRQ_ENABLE_REG, ier);
428
429 CSR_WRITE_4(sc, AML_SDXC_CNTRL_REG, ctlr);
430 CSR_WRITE_4(sc, AML_SDXC_DMA_ADDR_REG, (uint32_t)baddr);
431 CSR_WRITE_4(sc, AML_SDXC_CMD_ARGUMENT_REG, cmd->arg);
432
433 aml8726_sdxc_engage_dma(sc);
434
435 CSR_WRITE_4(sc, AML_SDXC_SEND_REG, sndr);
436 CSR_BARRIER(sc, AML_SDXC_SEND_REG);
437
438 return (MMC_ERR_NONE);
439 }
440
441 static void
aml8726_sdxc_finish_command(struct aml8726_sdxc_softc * sc,int mmc_error)442 aml8726_sdxc_finish_command(struct aml8726_sdxc_softc *sc, int mmc_error)
443 {
444 int mmc_stop_error;
445 struct mmc_command *cmd;
446 struct mmc_command *stop_cmd;
447 struct mmc_data *data;
448
449 AML_SDXC_LOCK_ASSERT(sc);
450
451 /* Clear all interrupts since the request is no longer in flight. */
452 CSR_WRITE_4(sc, AML_SDXC_IRQ_STATUS_REG, AML_SDXC_IRQ_STATUS_CLEAR);
453 CSR_BARRIER(sc, AML_SDXC_IRQ_STATUS_REG);
454
455 /* In some cases (e.g. finish called via timeout) this is a NOP. */
456 callout_stop(&sc->ch);
457
458 cmd = sc->cmd;
459 sc->cmd = NULL;
460
461 cmd->error = mmc_error;
462
463 data = cmd->data;
464
465 if (data && data->len
466 && (data->flags & (MMC_DATA_READ | MMC_DATA_WRITE)) != 0) {
467 if ((data->flags & MMC_DATA_READ) != 0)
468 bus_dmamap_sync(sc->dmatag, sc->dmamap,
469 BUS_DMASYNC_POSTREAD);
470 else
471 bus_dmamap_sync(sc->dmatag, sc->dmamap,
472 BUS_DMASYNC_POSTWRITE);
473 bus_dmamap_unload(sc->dmatag, sc->dmamap);
474 }
475
476 /*
477 * If there's a linked stop command, then start the stop command.
478 * In order to establish a known state attempt the stop command
479 * even if the original request encountered an error.
480 */
481
482 stop_cmd = (cmd->mrq->stop != cmd) ? cmd->mrq->stop : NULL;
483
484 if (stop_cmd != NULL) {
485
486 /*
487 * If the original command executed successfuly, then
488 * the hardware will also have automatically executed
489 * a stop command so don't bother with the one supplied
490 * with the original request.
491 */
492
493 if (mmc_error == MMC_ERR_NONE) {
494 stop_cmd->error = MMC_ERR_NONE;
495 stop_cmd->resp[0] = cmd->resp[0];
496 stop_cmd->resp[1] = cmd->resp[1];
497 stop_cmd->resp[2] = cmd->resp[2];
498 stop_cmd->resp[3] = cmd->resp[3];
499 } else {
500 mmc_stop_error = aml8726_sdxc_start_command(sc,
501 stop_cmd);
502 if (mmc_stop_error == MMC_ERR_NONE) {
503 AML_SDXC_UNLOCK(sc);
504 return;
505 }
506 stop_cmd->error = mmc_stop_error;
507 }
508 }
509
510 AML_SDXC_UNLOCK(sc);
511
512 /* Execute the callback after dropping the lock. */
513 if (cmd->mrq != NULL)
514 cmd->mrq->done(cmd->mrq);
515 }
516
517 static void
aml8726_sdxc_timeout(void * arg)518 aml8726_sdxc_timeout(void *arg)
519 {
520 struct aml8726_sdxc_softc *sc = (struct aml8726_sdxc_softc *)arg;
521
522 /*
523 * The command failed to complete in time so forcefully
524 * terminate it.
525 */
526 aml8726_sdxc_soft_reset(sc);
527
528 /*
529 * Ensure the command has terminated before continuing on
530 * to things such as bus_dmamap_sync / bus_dmamap_unload.
531 */
532 while ((CSR_READ_4(sc, AML_SDXC_STATUS_REG) &
533 AML_SDXC_STATUS_BUSY) != 0)
534 cpu_spinwait();
535
536 aml8726_sdxc_finish_command(sc, MMC_ERR_TIMEOUT);
537 }
538
539 static void
aml8726_sdxc_busy_check(void * arg)540 aml8726_sdxc_busy_check(void *arg)
541 {
542 struct aml8726_sdxc_softc *sc = (struct aml8726_sdxc_softc *)arg;
543 uint32_t sr;
544
545 sc->busy.time += AML_SDXC_BUSY_POLL_INTVL;
546
547 sr = CSR_READ_4(sc, AML_SDXC_STATUS_REG);
548
549 if ((sr & AML_SDXC_STATUS_DAT0) == 0) {
550 if (sc->busy.time < AML_SDXC_BUSY_TIMEOUT) {
551 callout_reset(&sc->ch,
552 msecs_to_ticks(AML_SDXC_BUSY_POLL_INTVL),
553 aml8726_sdxc_busy_check, sc);
554 AML_SDXC_UNLOCK(sc);
555 return;
556 }
557 if (sc->busy.error == MMC_ERR_NONE)
558 sc->busy.error = MMC_ERR_TIMEOUT;
559 }
560
561 aml8726_sdxc_finish_command(sc, sc->busy.error);
562 }
563
564 static void
aml8726_sdxc_intr(void * arg)565 aml8726_sdxc_intr(void *arg)
566 {
567 struct aml8726_sdxc_softc *sc = (struct aml8726_sdxc_softc *)arg;
568 uint32_t isr;
569 uint32_t pdmar;
570 uint32_t sndr;
571 uint32_t sr;
572 int i;
573 int mmc_error;
574 int start;
575 int stop;
576
577 AML_SDXC_LOCK(sc);
578
579 isr = CSR_READ_4(sc, AML_SDXC_IRQ_STATUS_REG);
580 sndr = CSR_READ_4(sc, AML_SDXC_SEND_REG);
581 sr = CSR_READ_4(sc, AML_SDXC_STATUS_REG);
582
583 if (sc->cmd == NULL)
584 goto spurious;
585
586 mmc_error = MMC_ERR_NONE;
587
588 if ((isr & (AML_SDXC_IRQ_STATUS_TX_FIFO_EMPTY |
589 AML_SDXC_IRQ_STATUS_RX_FIFO_FULL)) != 0)
590 mmc_error = MMC_ERR_FIFO;
591 else if ((isr & (AML_SDXC_IRQ_ENABLE_A_PKG_CRC_ERR |
592 AML_SDXC_IRQ_ENABLE_RESP_CRC_ERR)) != 0)
593 mmc_error = MMC_ERR_BADCRC;
594 else if ((isr & (AML_SDXC_IRQ_ENABLE_A_PKG_TIMEOUT_ERR |
595 AML_SDXC_IRQ_ENABLE_RESP_TIMEOUT_ERR)) != 0)
596 mmc_error = MMC_ERR_TIMEOUT;
597 else if ((isr & (AML_SDXC_IRQ_STATUS_RESP_OK |
598 AML_SDXC_IRQ_STATUS_DMA_DONE |
599 AML_SDXC_IRQ_STATUS_TRANSFER_DONE_OK)) != 0) {
600 ;
601 }
602 else {
603 spurious:
604 /*
605 * Clear spurious interrupts while leaving intacted any
606 * interrupts that may have occurred after we read the
607 * interrupt status register.
608 */
609
610 CSR_WRITE_4(sc, AML_SDXC_IRQ_STATUS_REG,
611 (AML_SDXC_IRQ_STATUS_CLEAR & isr));
612 CSR_BARRIER(sc, AML_SDXC_IRQ_STATUS_REG);
613 AML_SDXC_UNLOCK(sc);
614 return;
615 }
616
617 aml8726_sdxc_disengage_dma(sc);
618
619 if ((sndr & AML_SDXC_SEND_CMD_HAS_RESP) != 0) {
620 start = 0;
621 stop = 1;
622 if ((sndr & AML_SDXC_SEND_RESP_136) != 0) {
623 start = 1;
624 stop = start + 4;;
625 }
626 for (i = start; i < stop; i++) {
627 pdmar = CSR_READ_4(sc, AML_SDXC_PDMA_REG);
628 pdmar &= ~(AML_SDXC_PDMA_DMA_EN |
629 AML_SDXC_PDMA_RESP_INDEX_MASK);
630 pdmar |= i << AML_SDXC_PDMA_RESP_INDEX_SHIFT;
631 CSR_WRITE_4(sc, AML_SDXC_PDMA_REG, pdmar);
632 sc->cmd->resp[(stop - 1) - i] = CSR_READ_4(sc,
633 AML_SDXC_CMD_ARGUMENT_REG);
634 }
635 }
636
637 if ((sr & AML_SDXC_STATUS_BUSY) != 0 &&
638 /*
639 * A multiblock operation may keep the hardware
640 * busy until stop transmission is executed.
641 */
642 (isr & (AML_SDXC_IRQ_STATUS_DMA_DONE |
643 AML_SDXC_IRQ_STATUS_TRANSFER_DONE_OK)) == 0) {
644 if (mmc_error == MMC_ERR_NONE)
645 mmc_error = MMC_ERR_FAILED;
646
647 /*
648 * Issue a soft reset to terminate the command.
649 *
650 * Ensure the command has terminated before continuing on
651 * to things such as bus_dmamap_sync / bus_dmamap_unload.
652 */
653
654 aml8726_sdxc_soft_reset(sc);
655
656 while ((CSR_READ_4(sc, AML_SDXC_STATUS_REG) &
657 AML_SDXC_STATUS_BUSY) != 0)
658 cpu_spinwait();
659 }
660
661 /*
662 * The stop command can be generated either manually or
663 * automatically by the hardware if MISC_MANUAL_STOP_MODE
664 * has not been set. In either case check for busy.
665 */
666
667 if (((sc->cmd->flags & MMC_RSP_BUSY) != 0 ||
668 (sndr & AML_SDXC_SEND_INDEX_MASK) == MMC_STOP_TRANSMISSION) &&
669 (sr & AML_SDXC_STATUS_DAT0) == 0) {
670 sc->busy.error = mmc_error;
671 callout_reset(&sc->ch,
672 msecs_to_ticks(AML_SDXC_BUSY_POLL_INTVL),
673 aml8726_sdxc_busy_check, sc);
674 CSR_WRITE_4(sc, AML_SDXC_IRQ_STATUS_REG,
675 (AML_SDXC_IRQ_STATUS_CLEAR & isr));
676 CSR_BARRIER(sc, AML_SDXC_IRQ_STATUS_REG);
677 AML_SDXC_UNLOCK(sc);
678 return;
679 }
680
681 aml8726_sdxc_finish_command(sc, mmc_error);
682 }
683
684 static int
aml8726_sdxc_probe(device_t dev)685 aml8726_sdxc_probe(device_t dev)
686 {
687
688 if (!ofw_bus_status_okay(dev))
689 return (ENXIO);
690
691 if (!ofw_bus_is_compatible(dev, "amlogic,aml8726-sdxc-m8"))
692 return (ENXIO);
693
694 device_set_desc(dev, "Amlogic aml8726-m8 SDXC");
695
696 return (BUS_PROBE_DEFAULT);
697 }
698
699 static int
aml8726_sdxc_attach(device_t dev)700 aml8726_sdxc_attach(device_t dev)
701 {
702 struct aml8726_sdxc_softc *sc = device_get_softc(dev);
703 char *voltages;
704 char *voltage;
705 int error;
706 int nvoltages;
707 pcell_t prop[3];
708 phandle_t node;
709 ssize_t len;
710 device_t child;
711 uint32_t ectlr;
712 uint32_t miscr;
713 uint32_t pdmar;
714
715 sc->dev = dev;
716
717 sc->auto_fill_flush = false;
718
719 pdmar = AML_SDXC_PDMA_DMA_URGENT |
720 (49 << AML_SDXC_PDMA_TX_THOLD_SHIFT) |
721 (7 << AML_SDXC_PDMA_RX_THOLD_SHIFT) |
722 (15 << AML_SDXC_PDMA_RD_BURST_SHIFT) |
723 (7 << AML_SDXC_PDMA_WR_BURST_SHIFT);
724
725 miscr = (2 << AML_SDXC_MISC_WCRC_OK_PAT_SHIFT) |
726 (5 << AML_SDXC_MISC_WCRC_ERR_PAT_SHIFT);
727
728 ectlr = (12 << AML_SDXC_ENH_CNTRL_SDIO_IRQ_PERIOD_SHIFT);
729
730 /*
731 * Certain bitfields are dependent on the hardware revision.
732 */
733 switch (aml8726_soc_hw_rev) {
734 case AML_SOC_HW_REV_M8:
735 switch (aml8726_soc_metal_rev) {
736 case AML_SOC_M8_METAL_REV_M2_A:
737 sc->auto_fill_flush = true;
738 miscr |= (6 << AML_SDXC_MISC_TXSTART_THOLD_SHIFT);
739 ectlr |= (64 << AML_SDXC_ENH_CNTRL_RX_FULL_THOLD_SHIFT) |
740 AML_SDXC_ENH_CNTRL_WR_RESP_MODE_SKIP_M8M2;
741 break;
742 default:
743 miscr |= (7 << AML_SDXC_MISC_TXSTART_THOLD_SHIFT);
744 ectlr |= (63 << AML_SDXC_ENH_CNTRL_RX_FULL_THOLD_SHIFT) |
745 AML_SDXC_ENH_CNTRL_DMA_NO_WR_RESP_CHECK_M8 |
746 (255 << AML_SDXC_ENH_CNTRL_RX_TIMEOUT_SHIFT_M8);
747
748 break;
749 }
750 break;
751 case AML_SOC_HW_REV_M8B:
752 miscr |= (7 << AML_SDXC_MISC_TXSTART_THOLD_SHIFT);
753 ectlr |= (63 << AML_SDXC_ENH_CNTRL_RX_FULL_THOLD_SHIFT) |
754 AML_SDXC_ENH_CNTRL_DMA_NO_WR_RESP_CHECK_M8 |
755 (255 << AML_SDXC_ENH_CNTRL_RX_TIMEOUT_SHIFT_M8);
756 break;
757 default:
758 device_printf(dev, "unsupported SoC\n");
759 return (ENXIO);
760 /* NOTREACHED */
761 }
762
763 node = ofw_bus_get_node(dev);
764
765 len = OF_getencprop(node, "clock-frequency", prop, sizeof(prop));
766 if ((len / sizeof(prop[0])) != 1 || prop[0] == 0) {
767 device_printf(dev,
768 "missing clock-frequency attribute in FDT\n");
769 return (ENXIO);
770 }
771
772 sc->ref_freq = prop[0];
773
774 sc->pwr_en.dev = NULL;
775
776 len = OF_getencprop(node, "mmc-pwr-en", prop, sizeof(prop));
777 if (len > 0) {
778 if ((len / sizeof(prop[0])) == 3) {
779 sc->pwr_en.dev = OF_device_from_xref(prop[0]);
780 sc->pwr_en.pin = prop[1];
781 sc->pwr_en.pol = prop[2];
782 }
783
784 if (sc->pwr_en.dev == NULL) {
785 device_printf(dev,
786 "unable to process mmc-pwr-en attribute in FDT\n");
787 return (ENXIO);
788 }
789
790 /* Turn off power and then configure the output driver. */
791 if (aml8726_sdxc_power_off(sc) != 0 ||
792 GPIO_PIN_SETFLAGS(sc->pwr_en.dev, sc->pwr_en.pin,
793 GPIO_PIN_OUTPUT) != 0) {
794 device_printf(dev,
795 "could not use gpio to control power\n");
796 return (ENXIO);
797 }
798 }
799
800 len = OF_getprop_alloc(node, "mmc-voltages",
801 sizeof(char), (void **)&voltages);
802
803 if (len < 0) {
804 device_printf(dev, "missing mmc-voltages attribute in FDT\n");
805 return (ENXIO);
806 }
807
808 sc->voltages[0] = 0;
809 sc->voltages[1] = 0;
810
811 voltage = voltages;
812 nvoltages = 0;
813
814 while (len && nvoltages < 2) {
815 if (strncmp("1.8", voltage, len) == 0)
816 sc->voltages[nvoltages] = MMC_OCR_LOW_VOLTAGE;
817 else if (strncmp("3.3", voltage, len) == 0)
818 sc->voltages[nvoltages] = MMC_OCR_320_330 |
819 MMC_OCR_330_340;
820 else {
821 device_printf(dev,
822 "unknown voltage attribute %.*s in FDT\n",
823 len, voltage);
824 free(voltages, M_OFWPROP);
825 return (ENXIO);
826 }
827
828 nvoltages++;
829
830 /* queue up next string */
831 while (*voltage && len) {
832 voltage++;
833 len--;
834 }
835 if (len) {
836 voltage++;
837 len--;
838 }
839 }
840
841 free(voltages, M_OFWPROP);
842
843 sc->vselect.dev = NULL;
844
845 len = OF_getencprop(node, "mmc-vselect", prop, sizeof(prop));
846 if (len > 0) {
847 if ((len / sizeof(prop[0])) == 2) {
848 sc->vselect.dev = OF_device_from_xref(prop[0]);
849 sc->vselect.pin = prop[1];
850 sc->vselect.pol = 1;
851 }
852
853 if (sc->vselect.dev == NULL) {
854 device_printf(dev,
855 "unable to process mmc-vselect attribute in FDT\n");
856 return (ENXIO);
857 }
858
859 /*
860 * With the power off select voltage 0 and then
861 * configure the output driver.
862 */
863 if (GPIO_PIN_SET(sc->vselect.dev, sc->vselect.pin, 0) != 0 ||
864 GPIO_PIN_SETFLAGS(sc->vselect.dev, sc->vselect.pin,
865 GPIO_PIN_OUTPUT) != 0) {
866 device_printf(dev,
867 "could not use gpio to set voltage\n");
868 return (ENXIO);
869 }
870 }
871
872 if (nvoltages == 0) {
873 device_printf(dev, "no voltages in FDT\n");
874 return (ENXIO);
875 } else if (nvoltages == 1 && sc->vselect.dev != NULL) {
876 device_printf(dev, "only one voltage in FDT\n");
877 return (ENXIO);
878 } else if (nvoltages == 2 && sc->vselect.dev == NULL) {
879 device_printf(dev, "too many voltages in FDT\n");
880 return (ENXIO);
881 }
882
883 sc->card_rst.dev = NULL;
884
885 len = OF_getencprop(node, "mmc-rst", prop, sizeof(prop));
886 if (len > 0) {
887 if ((len / sizeof(prop[0])) == 3) {
888 sc->card_rst.dev = OF_device_from_xref(prop[0]);
889 sc->card_rst.pin = prop[1];
890 sc->card_rst.pol = prop[2];
891 }
892
893 if (sc->card_rst.dev == NULL) {
894 device_printf(dev,
895 "unable to process mmc-rst attribute in FDT\n");
896 return (ENXIO);
897 }
898 }
899
900 if (bus_alloc_resources(dev, aml8726_sdxc_spec, sc->res)) {
901 device_printf(dev, "could not allocate resources for device\n");
902 return (ENXIO);
903 }
904
905 AML_SDXC_LOCK_INIT(sc);
906
907 error = bus_dma_tag_create(bus_get_dma_tag(dev), AML_SDXC_ALIGN_DMA, 0,
908 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL,
909 AML_SDXC_MAX_DMA, 1, AML_SDXC_MAX_DMA, 0, NULL, NULL, &sc->dmatag);
910 if (error)
911 goto fail;
912
913 error = bus_dmamap_create(sc->dmatag, 0, &sc->dmamap);
914
915 if (error)
916 goto fail;
917
918 error = bus_setup_intr(dev, sc->res[1], INTR_TYPE_MISC | INTR_MPSAFE,
919 NULL, aml8726_sdxc_intr, sc, &sc->ih_cookie);
920 if (error) {
921 device_printf(dev, "could not setup interrupt handler\n");
922 goto fail;
923 }
924
925 callout_init_mtx(&sc->ch, &sc->mtx, CALLOUT_RETURNUNLOCKED);
926
927 sc->host.f_min = 200000;
928 sc->host.f_max = 100000000;
929 sc->host.host_ocr = sc->voltages[0] | sc->voltages[1];
930 sc->host.caps = MMC_CAP_8_BIT_DATA | MMC_CAP_4_BIT_DATA |
931 MMC_CAP_HSPEED;
932
933 aml8726_sdxc_soft_reset(sc);
934
935 CSR_WRITE_4(sc, AML_SDXC_PDMA_REG, pdmar);
936
937 CSR_WRITE_4(sc, AML_SDXC_MISC_REG, miscr);
938
939 CSR_WRITE_4(sc, AML_SDXC_ENH_CNTRL_REG, ectlr);
940
941 child = device_add_child(dev, "mmc", -1);
942
943 if (!child) {
944 device_printf(dev, "could not add mmc\n");
945 error = ENXIO;
946 goto fail;
947 }
948
949 error = device_probe_and_attach(child);
950
951 if (error) {
952 device_printf(dev, "could not attach mmc\n");
953 goto fail;
954 }
955
956 return (0);
957
958 fail:
959 if (sc->ih_cookie)
960 bus_teardown_intr(dev, sc->res[1], sc->ih_cookie);
961
962 if (sc->dmamap)
963 bus_dmamap_destroy(sc->dmatag, sc->dmamap);
964
965 if (sc->dmatag)
966 bus_dma_tag_destroy(sc->dmatag);
967
968 AML_SDXC_LOCK_DESTROY(sc);
969
970 (void)aml8726_sdxc_power_off(sc);
971
972 bus_release_resources(dev, aml8726_sdxc_spec, sc->res);
973
974 return (error);
975 }
976
977 static int
aml8726_sdxc_detach(device_t dev)978 aml8726_sdxc_detach(device_t dev)
979 {
980 struct aml8726_sdxc_softc *sc = device_get_softc(dev);
981
982 AML_SDXC_LOCK(sc);
983
984 if (sc->cmd != NULL) {
985 AML_SDXC_UNLOCK(sc);
986 return (EBUSY);
987 }
988
989 /*
990 * Turn off the power, reset the hardware state machine,
991 * and disable the interrupts.
992 */
993 aml8726_sdxc_power_off(sc);
994 aml8726_sdxc_soft_reset(sc);
995 CSR_WRITE_4(sc, AML_SDXC_IRQ_ENABLE_REG, 0);
996
997 AML_SDXC_UNLOCK(sc);
998
999 bus_generic_detach(dev);
1000
1001 bus_teardown_intr(dev, sc->res[1], sc->ih_cookie);
1002
1003 bus_dmamap_destroy(sc->dmatag, sc->dmamap);
1004
1005 bus_dma_tag_destroy(sc->dmatag);
1006
1007 AML_SDXC_LOCK_DESTROY(sc);
1008
1009 bus_release_resources(dev, aml8726_sdxc_spec, sc->res);
1010
1011 return (0);
1012 }
1013
1014 static int
aml8726_sdxc_shutdown(device_t dev)1015 aml8726_sdxc_shutdown(device_t dev)
1016 {
1017 struct aml8726_sdxc_softc *sc = device_get_softc(dev);
1018
1019 /*
1020 * Turn off the power, reset the hardware state machine,
1021 * and disable the interrupts.
1022 */
1023 aml8726_sdxc_power_off(sc);
1024 aml8726_sdxc_soft_reset(sc);
1025 CSR_WRITE_4(sc, AML_SDXC_IRQ_ENABLE_REG, 0);
1026
1027 return (0);
1028 }
1029
1030 static int
aml8726_sdxc_update_ios(device_t bus,device_t child)1031 aml8726_sdxc_update_ios(device_t bus, device_t child)
1032 {
1033 struct aml8726_sdxc_softc *sc = device_get_softc(bus);
1034 struct mmc_ios *ios = &sc->host.ios;
1035 unsigned int divisor;
1036 int error;
1037 int i;
1038 uint32_t cctlr;
1039 uint32_t clk2r;
1040 uint32_t ctlr;
1041 uint32_t freq;
1042
1043 ctlr = (7 << AML_SDXC_CNTRL_TX_ENDIAN_SHIFT) |
1044 (7 << AML_SDXC_CNTRL_RX_ENDIAN_SHIFT) |
1045 (0xf << AML_SDXC_CNTRL_RX_PERIOD_SHIFT) |
1046 (0x7f << AML_SDXC_CNTRL_RX_TIMEOUT_SHIFT);
1047
1048 switch (ios->bus_width) {
1049 case bus_width_8:
1050 ctlr |= AML_SDXC_CNTRL_BUS_WIDTH_8;
1051 break;
1052 case bus_width_4:
1053 ctlr |= AML_SDXC_CNTRL_BUS_WIDTH_4;
1054 break;
1055 case bus_width_1:
1056 ctlr |= AML_SDXC_CNTRL_BUS_WIDTH_1;
1057 break;
1058 default:
1059 return (EINVAL);
1060 }
1061
1062 CSR_WRITE_4(sc, AML_SDXC_CNTRL_REG, ctlr);
1063
1064 /*
1065 * Disable clocks and then clock module prior to setting desired values.
1066 */
1067 cctlr = CSR_READ_4(sc, AML_SDXC_CLK_CNTRL_REG);
1068 cctlr &= ~(AML_SDXC_CLK_CNTRL_TX_CLK_EN | AML_SDXC_CLK_CNTRL_RX_CLK_EN |
1069 AML_SDXC_CLK_CNTRL_SD_CLK_EN);
1070 CSR_WRITE_4(sc, AML_SDXC_CLK_CNTRL_REG, cctlr);
1071 CSR_BARRIER(sc, AML_SDXC_CLK_CNTRL_REG);
1072 cctlr &= ~AML_SDXC_CLK_CNTRL_CLK_MODULE_EN;
1073 CSR_WRITE_4(sc, AML_SDXC_CLK_CNTRL_REG, cctlr);
1074 CSR_BARRIER(sc, AML_SDXC_CLK_CNTRL_REG);
1075
1076 /*
1077 * aml8726-m8
1078 *
1079 * Clock select 1 fclk_div2 (1.275 GHz)
1080 */
1081 cctlr &= ~AML_SDXC_CLK_CNTRL_CLK_SEL_MASK;
1082 cctlr |= (1 << AML_SDXC_CLK_CNTRL_CLK_SEL_SHIFT);
1083
1084 divisor = sc->ref_freq / ios->clock - 1;
1085 if (divisor == 0 || divisor == -1)
1086 divisor = 1;
1087 if ((sc->ref_freq / (divisor + 1)) > ios->clock)
1088 divisor += 1;
1089 if (divisor > (AML_SDXC_CLK_CNTRL_CLK_DIV_MASK >>
1090 AML_SDXC_CLK_CNTRL_CLK_DIV_SHIFT))
1091 divisor = AML_SDXC_CLK_CNTRL_CLK_DIV_MASK >>
1092 AML_SDXC_CLK_CNTRL_CLK_DIV_SHIFT;
1093
1094 cctlr &= ~AML_SDXC_CLK_CNTRL_CLK_DIV_MASK;
1095 cctlr |= divisor << AML_SDXC_CLK_CNTRL_CLK_DIV_SHIFT;
1096
1097 cctlr &= ~AML_SDXC_CLK_CNTRL_MEM_PWR_MASK;
1098 cctlr |= AML_SDXC_CLK_CNTRL_MEM_PWR_ON;
1099
1100 CSR_WRITE_4(sc, AML_SDXC_CLK_CNTRL_REG, cctlr);
1101 CSR_BARRIER(sc, AML_SDXC_CLK_CNTRL_REG);
1102
1103 /*
1104 * Enable clock module and then clocks after setting desired values.
1105 */
1106 cctlr |= AML_SDXC_CLK_CNTRL_CLK_MODULE_EN;
1107 CSR_WRITE_4(sc, AML_SDXC_CLK_CNTRL_REG, cctlr);
1108 CSR_BARRIER(sc, AML_SDXC_CLK_CNTRL_REG);
1109 cctlr |= AML_SDXC_CLK_CNTRL_TX_CLK_EN | AML_SDXC_CLK_CNTRL_RX_CLK_EN |
1110 AML_SDXC_CLK_CNTRL_SD_CLK_EN;
1111 CSR_WRITE_4(sc, AML_SDXC_CLK_CNTRL_REG, cctlr);
1112 CSR_BARRIER(sc, AML_SDXC_CLK_CNTRL_REG);
1113
1114 freq = sc->ref_freq / divisor;
1115
1116 for (i = 0; aml8726_sdxc_clk_phases[i].voltage; i++) {
1117 if ((aml8726_sdxc_clk_phases[i].voltage &
1118 (1 << ios->vdd)) != 0 &&
1119 freq > aml8726_sdxc_clk_phases[i].freq)
1120 break;
1121 if (aml8726_sdxc_clk_phases[i].freq == 0)
1122 break;
1123 }
1124
1125 clk2r = (1 << AML_SDXC_CLK2_SD_PHASE_SHIFT) |
1126 (aml8726_sdxc_clk_phases[i].rx_phase <<
1127 AML_SDXC_CLK2_RX_PHASE_SHIFT);
1128 CSR_WRITE_4(sc, AML_SDXC_CLK2_REG, clk2r);
1129 CSR_BARRIER(sc, AML_SDXC_CLK2_REG);
1130
1131 error = 0;
1132
1133 switch (ios->power_mode) {
1134 case power_up:
1135 /*
1136 * Configure and power on the regulator so that the
1137 * voltage stabilizes prior to powering on the card.
1138 */
1139 if (sc->vselect.dev != NULL) {
1140 for (i = 0; i < 2; i++)
1141 if ((sc->voltages[i] & (1 << ios->vdd)) != 0)
1142 break;
1143 if (i >= 2)
1144 return (EINVAL);
1145 error = GPIO_PIN_SET(sc->vselect.dev,
1146 sc->vselect.pin, i);
1147 }
1148 break;
1149 case power_on:
1150 error = aml8726_sdxc_power_on(sc);
1151 if (error)
1152 break;
1153
1154 if (sc->card_rst.dev != NULL) {
1155 if (GPIO_PIN_SET(sc->card_rst.dev, sc->card_rst.pin,
1156 PIN_ON_FLAG(sc->card_rst.pol)) != 0 ||
1157 GPIO_PIN_SETFLAGS(sc->card_rst.dev,
1158 sc->card_rst.pin,
1159 GPIO_PIN_OUTPUT) != 0)
1160 error = ENXIO;
1161
1162 DELAY(5);
1163
1164 if (GPIO_PIN_SET(sc->card_rst.dev, sc->card_rst.pin,
1165 PIN_OFF_FLAG(sc->card_rst.pol)) != 0)
1166 error = ENXIO;
1167
1168 DELAY(5);
1169
1170 if (error) {
1171 device_printf(sc->dev,
1172 "could not use gpio to reset card\n");
1173 break;
1174 }
1175 }
1176 break;
1177 case power_off:
1178 error = aml8726_sdxc_power_off(sc);
1179 break;
1180 default:
1181 return (EINVAL);
1182 }
1183
1184 return (error);
1185 }
1186
1187 static int
aml8726_sdxc_request(device_t bus,device_t child,struct mmc_request * req)1188 aml8726_sdxc_request(device_t bus, device_t child, struct mmc_request *req)
1189 {
1190 struct aml8726_sdxc_softc *sc = device_get_softc(bus);
1191 int mmc_error;
1192
1193 AML_SDXC_LOCK(sc);
1194
1195 if (sc->cmd != NULL) {
1196 AML_SDXC_UNLOCK(sc);
1197 return (EBUSY);
1198 }
1199
1200 mmc_error = aml8726_sdxc_start_command(sc, req->cmd);
1201
1202 AML_SDXC_UNLOCK(sc);
1203
1204 /* Execute the callback after dropping the lock. */
1205 if (mmc_error != MMC_ERR_NONE) {
1206 req->cmd->error = mmc_error;
1207 req->done(req);
1208 }
1209
1210 return (0);
1211 }
1212
1213 static int
aml8726_sdxc_read_ivar(device_t bus,device_t child,int which,uintptr_t * result)1214 aml8726_sdxc_read_ivar(device_t bus, device_t child,
1215 int which, uintptr_t *result)
1216 {
1217 struct aml8726_sdxc_softc *sc = device_get_softc(bus);
1218
1219 switch (which) {
1220 case MMCBR_IVAR_BUS_MODE:
1221 *(int *)result = sc->host.ios.bus_mode;
1222 break;
1223 case MMCBR_IVAR_BUS_WIDTH:
1224 *(int *)result = sc->host.ios.bus_width;
1225 break;
1226 case MMCBR_IVAR_CHIP_SELECT:
1227 *(int *)result = sc->host.ios.chip_select;
1228 break;
1229 case MMCBR_IVAR_CLOCK:
1230 *(int *)result = sc->host.ios.clock;
1231 break;
1232 case MMCBR_IVAR_F_MIN:
1233 *(int *)result = sc->host.f_min;
1234 break;
1235 case MMCBR_IVAR_F_MAX:
1236 *(int *)result = sc->host.f_max;
1237 break;
1238 case MMCBR_IVAR_HOST_OCR:
1239 *(int *)result = sc->host.host_ocr;
1240 break;
1241 case MMCBR_IVAR_MODE:
1242 *(int *)result = sc->host.mode;
1243 break;
1244 case MMCBR_IVAR_OCR:
1245 *(int *)result = sc->host.ocr;
1246 break;
1247 case MMCBR_IVAR_POWER_MODE:
1248 *(int *)result = sc->host.ios.power_mode;
1249 break;
1250 case MMCBR_IVAR_VDD:
1251 *(int *)result = sc->host.ios.vdd;
1252 break;
1253 case MMCBR_IVAR_CAPS:
1254 *(int *)result = sc->host.caps;
1255 break;
1256 case MMCBR_IVAR_MAX_DATA:
1257 *(int *)result = AML_SDXC_MAX_DMA / MMC_SECTOR_SIZE;
1258 break;
1259 default:
1260 return (EINVAL);
1261 }
1262
1263 return (0);
1264 }
1265
1266 static int
aml8726_sdxc_write_ivar(device_t bus,device_t child,int which,uintptr_t value)1267 aml8726_sdxc_write_ivar(device_t bus, device_t child,
1268 int which, uintptr_t value)
1269 {
1270 struct aml8726_sdxc_softc *sc = device_get_softc(bus);
1271
1272 switch (which) {
1273 case MMCBR_IVAR_BUS_MODE:
1274 sc->host.ios.bus_mode = value;
1275 break;
1276 case MMCBR_IVAR_BUS_WIDTH:
1277 sc->host.ios.bus_width = value;
1278 break;
1279 case MMCBR_IVAR_CHIP_SELECT:
1280 sc->host.ios.chip_select = value;
1281 break;
1282 case MMCBR_IVAR_CLOCK:
1283 sc->host.ios.clock = value;
1284 break;
1285 case MMCBR_IVAR_MODE:
1286 sc->host.mode = value;
1287 break;
1288 case MMCBR_IVAR_OCR:
1289 sc->host.ocr = value;
1290 break;
1291 case MMCBR_IVAR_POWER_MODE:
1292 sc->host.ios.power_mode = value;
1293 break;
1294 case MMCBR_IVAR_VDD:
1295 sc->host.ios.vdd = value;
1296 break;
1297 /* These are read-only */
1298 case MMCBR_IVAR_CAPS:
1299 case MMCBR_IVAR_HOST_OCR:
1300 case MMCBR_IVAR_F_MIN:
1301 case MMCBR_IVAR_F_MAX:
1302 case MMCBR_IVAR_MAX_DATA:
1303 default:
1304 return (EINVAL);
1305 }
1306
1307 return (0);
1308 }
1309
1310 static int
aml8726_sdxc_get_ro(device_t bus,device_t child)1311 aml8726_sdxc_get_ro(device_t bus, device_t child)
1312 {
1313
1314 return (0);
1315 }
1316
1317 static int
aml8726_sdxc_acquire_host(device_t bus,device_t child)1318 aml8726_sdxc_acquire_host(device_t bus, device_t child)
1319 {
1320 struct aml8726_sdxc_softc *sc = device_get_softc(bus);
1321
1322 AML_SDXC_LOCK(sc);
1323
1324 while (sc->bus_busy)
1325 mtx_sleep(sc, &sc->mtx, PZERO, "sdxc", hz / 5);
1326 sc->bus_busy++;
1327
1328 AML_SDXC_UNLOCK(sc);
1329
1330 return (0);
1331 }
1332
1333 static int
aml8726_sdxc_release_host(device_t bus,device_t child)1334 aml8726_sdxc_release_host(device_t bus, device_t child)
1335 {
1336 struct aml8726_sdxc_softc *sc = device_get_softc(bus);
1337
1338 AML_SDXC_LOCK(sc);
1339
1340 sc->bus_busy--;
1341 wakeup(sc);
1342
1343 AML_SDXC_UNLOCK(sc);
1344
1345 return (0);
1346 }
1347
1348 static device_method_t aml8726_sdxc_methods[] = {
1349 /* Device interface */
1350 DEVMETHOD(device_probe, aml8726_sdxc_probe),
1351 DEVMETHOD(device_attach, aml8726_sdxc_attach),
1352 DEVMETHOD(device_detach, aml8726_sdxc_detach),
1353 DEVMETHOD(device_shutdown, aml8726_sdxc_shutdown),
1354
1355 /* Bus interface */
1356 DEVMETHOD(bus_read_ivar, aml8726_sdxc_read_ivar),
1357 DEVMETHOD(bus_write_ivar, aml8726_sdxc_write_ivar),
1358
1359 /* MMC bridge interface */
1360 DEVMETHOD(mmcbr_update_ios, aml8726_sdxc_update_ios),
1361 DEVMETHOD(mmcbr_request, aml8726_sdxc_request),
1362 DEVMETHOD(mmcbr_get_ro, aml8726_sdxc_get_ro),
1363 DEVMETHOD(mmcbr_acquire_host, aml8726_sdxc_acquire_host),
1364 DEVMETHOD(mmcbr_release_host, aml8726_sdxc_release_host),
1365
1366 DEVMETHOD_END
1367 };
1368
1369 static driver_t aml8726_sdxc_driver = {
1370 "aml8726_sdxc",
1371 aml8726_sdxc_methods,
1372 sizeof(struct aml8726_sdxc_softc),
1373 };
1374
1375 static devclass_t aml8726_sdxc_devclass;
1376
1377 DRIVER_MODULE(aml8726_sdxc, simplebus, aml8726_sdxc_driver,
1378 aml8726_sdxc_devclass, 0, 0);
1379 MODULE_DEPEND(aml8726_sdxc, aml8726_gpio, 1, 1, 1);
1380 DRIVER_MODULE(mmc, aml8726_sdxc, mmc_driver, mmc_devclass, NULL, NULL);
1381