1 /* Subroutines for the gcc driver.
2 Copyright (C) 2006, 2007, 2008, 2010 Free Software Foundation, Inc.
3
4 This file is part of GCC.
5
6 GCC is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 3, or (at your option)
9 any later version.
10
11 GCC is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
15
16 You should have received a copy of the GNU General Public License
17 along with GCC; see the file COPYING3. If not see
18 <http://www.gnu.org/licenses/>. */
19
20 #include "config.h"
21 #include "system.h"
22 #include "coretypes.h"
23 #include "tm.h"
24
25 const char *host_detect_local_cpu (int argc, const char **argv);
26
27 #ifdef __GNUC__
28 #include "cpuid.h"
29
30 struct cache_desc
31 {
32 unsigned sizekb;
33 unsigned assoc;
34 unsigned line;
35 };
36
37 /* Returns command line parameters that describe size and
38 cache line size of the processor caches. */
39
40 static char *
describe_cache(struct cache_desc level1,struct cache_desc level2)41 describe_cache (struct cache_desc level1, struct cache_desc level2)
42 {
43 char size[100], line[100], size2[100];
44
45 /* At the moment, gcc does not use the information
46 about the associativity of the cache. */
47
48 snprintf (size, sizeof (size),
49 "--param l1-cache-size=%u ", level1.sizekb);
50 snprintf (line, sizeof (line),
51 "--param l1-cache-line-size=%u ", level1.line);
52
53 snprintf (size2, sizeof (size2),
54 "--param l2-cache-size=%u ", level2.sizekb);
55
56 return concat (size, line, size2, NULL);
57 }
58
59 /* Detect L2 cache parameters using CPUID extended function 0x80000006. */
60
61 static void
detect_l2_cache(struct cache_desc * level2)62 detect_l2_cache (struct cache_desc *level2)
63 {
64 unsigned eax, ebx, ecx, edx;
65 unsigned assoc;
66
67 __cpuid (0x80000006, eax, ebx, ecx, edx);
68
69 level2->sizekb = (ecx >> 16) & 0xffff;
70 level2->line = ecx & 0xff;
71
72 assoc = (ecx >> 12) & 0xf;
73 if (assoc == 6)
74 assoc = 8;
75 else if (assoc == 8)
76 assoc = 16;
77 else if (assoc >= 0xa && assoc <= 0xc)
78 assoc = 32 + (assoc - 0xa) * 16;
79 else if (assoc >= 0xd && assoc <= 0xe)
80 assoc = 96 + (assoc - 0xd) * 32;
81
82 level2->assoc = assoc;
83 }
84
85 /* Returns the description of caches for an AMD processor. */
86
87 static const char *
detect_caches_amd(unsigned max_ext_level)88 detect_caches_amd (unsigned max_ext_level)
89 {
90 unsigned eax, ebx, ecx, edx;
91
92 struct cache_desc level1, level2 = {0, 0, 0};
93
94 if (max_ext_level < 0x80000005)
95 return "";
96
97 __cpuid (0x80000005, eax, ebx, ecx, edx);
98
99 level1.sizekb = (ecx >> 24) & 0xff;
100 level1.assoc = (ecx >> 16) & 0xff;
101 level1.line = ecx & 0xff;
102
103 if (max_ext_level >= 0x80000006)
104 detect_l2_cache (&level2);
105
106 return describe_cache (level1, level2);
107 }
108
109 /* Decodes the size, the associativity and the cache line size of
110 L1/L2 caches of an Intel processor. Values are based on
111 "Intel Processor Identification and the CPUID Instruction"
112 [Application Note 485], revision -032, December 2007. */
113
114 static void
decode_caches_intel(unsigned reg,bool xeon_mp,struct cache_desc * level1,struct cache_desc * level2)115 decode_caches_intel (unsigned reg, bool xeon_mp,
116 struct cache_desc *level1, struct cache_desc *level2)
117 {
118 int i;
119
120 for (i = 24; i >= 0; i -= 8)
121 switch ((reg >> i) & 0xff)
122 {
123 case 0x0a:
124 level1->sizekb = 8; level1->assoc = 2; level1->line = 32;
125 break;
126 case 0x0c:
127 level1->sizekb = 16; level1->assoc = 4; level1->line = 32;
128 break;
129 case 0x2c:
130 level1->sizekb = 32; level1->assoc = 8; level1->line = 64;
131 break;
132 case 0x39:
133 level2->sizekb = 128; level2->assoc = 4; level2->line = 64;
134 break;
135 case 0x3a:
136 level2->sizekb = 192; level2->assoc = 6; level2->line = 64;
137 break;
138 case 0x3b:
139 level2->sizekb = 128; level2->assoc = 2; level2->line = 64;
140 break;
141 case 0x3c:
142 level2->sizekb = 256; level2->assoc = 4; level2->line = 64;
143 break;
144 case 0x3d:
145 level2->sizekb = 384; level2->assoc = 6; level2->line = 64;
146 break;
147 case 0x3e:
148 level2->sizekb = 512; level2->assoc = 4; level2->line = 64;
149 break;
150 case 0x41:
151 level2->sizekb = 128; level2->assoc = 4; level2->line = 32;
152 break;
153 case 0x42:
154 level2->sizekb = 256; level2->assoc = 4; level2->line = 32;
155 break;
156 case 0x43:
157 level2->sizekb = 512; level2->assoc = 4; level2->line = 32;
158 break;
159 case 0x44:
160 level2->sizekb = 1024; level2->assoc = 4; level2->line = 32;
161 break;
162 case 0x45:
163 level2->sizekb = 2048; level2->assoc = 4; level2->line = 32;
164 break;
165 case 0x49:
166 if (xeon_mp)
167 break;
168 level2->sizekb = 4096; level2->assoc = 16; level2->line = 64;
169 break;
170 case 0x4e:
171 level2->sizekb = 6144; level2->assoc = 24; level2->line = 64;
172 break;
173 case 0x60:
174 level1->sizekb = 16; level1->assoc = 8; level1->line = 64;
175 break;
176 case 0x66:
177 level1->sizekb = 8; level1->assoc = 4; level1->line = 64;
178 break;
179 case 0x67:
180 level1->sizekb = 16; level1->assoc = 4; level1->line = 64;
181 break;
182 case 0x68:
183 level1->sizekb = 32; level1->assoc = 4; level1->line = 64;
184 break;
185 case 0x78:
186 level2->sizekb = 1024; level2->assoc = 4; level2->line = 64;
187 break;
188 case 0x79:
189 level2->sizekb = 128; level2->assoc = 8; level2->line = 64;
190 break;
191 case 0x7a:
192 level2->sizekb = 256; level2->assoc = 8; level2->line = 64;
193 break;
194 case 0x7b:
195 level2->sizekb = 512; level2->assoc = 8; level2->line = 64;
196 break;
197 case 0x7c:
198 level2->sizekb = 1024; level2->assoc = 8; level2->line = 64;
199 break;
200 case 0x7d:
201 level2->sizekb = 2048; level2->assoc = 8; level2->line = 64;
202 break;
203 case 0x7f:
204 level2->sizekb = 512; level2->assoc = 2; level2->line = 64;
205 break;
206 case 0x82:
207 level2->sizekb = 256; level2->assoc = 8; level2->line = 32;
208 break;
209 case 0x83:
210 level2->sizekb = 512; level2->assoc = 8; level2->line = 32;
211 break;
212 case 0x84:
213 level2->sizekb = 1024; level2->assoc = 8; level2->line = 32;
214 break;
215 case 0x85:
216 level2->sizekb = 2048; level2->assoc = 8; level2->line = 32;
217 break;
218 case 0x86:
219 level2->sizekb = 512; level2->assoc = 4; level2->line = 64;
220 break;
221 case 0x87:
222 level2->sizekb = 1024; level2->assoc = 8; level2->line = 64;
223
224 default:
225 break;
226 }
227 }
228
229 /* Detect cache parameters using CPUID function 2. */
230
231 static void
detect_caches_cpuid2(bool xeon_mp,struct cache_desc * level1,struct cache_desc * level2)232 detect_caches_cpuid2 (bool xeon_mp,
233 struct cache_desc *level1, struct cache_desc *level2)
234 {
235 unsigned regs[4];
236 int nreps, i;
237
238 __cpuid (2, regs[0], regs[1], regs[2], regs[3]);
239
240 nreps = regs[0] & 0x0f;
241 regs[0] &= ~0x0f;
242
243 while (--nreps >= 0)
244 {
245 for (i = 0; i < 4; i++)
246 if (regs[i] && !((regs[i] >> 31) & 1))
247 decode_caches_intel (regs[i], xeon_mp, level1, level2);
248
249 if (nreps)
250 __cpuid (2, regs[0], regs[1], regs[2], regs[3]);
251 }
252 }
253
254 /* Detect cache parameters using CPUID function 4. This
255 method doesn't require hardcoded tables. */
256
257 enum cache_type
258 {
259 CACHE_END = 0,
260 CACHE_DATA = 1,
261 CACHE_INST = 2,
262 CACHE_UNIFIED = 3
263 };
264
265 static void
detect_caches_cpuid4(struct cache_desc * level1,struct cache_desc * level2,struct cache_desc * level3)266 detect_caches_cpuid4 (struct cache_desc *level1, struct cache_desc *level2,
267 struct cache_desc *level3)
268 {
269 struct cache_desc *cache;
270
271 unsigned eax, ebx, ecx, edx;
272 int count;
273
274 for (count = 0;; count++)
275 {
276 __cpuid_count(4, count, eax, ebx, ecx, edx);
277 switch (eax & 0x1f)
278 {
279 case CACHE_END:
280 return;
281 case CACHE_DATA:
282 case CACHE_UNIFIED:
283 {
284 switch ((eax >> 5) & 0x07)
285 {
286 case 1:
287 cache = level1;
288 break;
289 case 2:
290 cache = level2;
291 break;
292 case 3:
293 cache = level3;
294 break;
295 default:
296 cache = NULL;
297 }
298
299 if (cache)
300 {
301 unsigned sets = ecx + 1;
302 unsigned part = ((ebx >> 12) & 0x03ff) + 1;
303
304 cache->assoc = ((ebx >> 22) & 0x03ff) + 1;
305 cache->line = (ebx & 0x0fff) + 1;
306
307 cache->sizekb = (cache->assoc * part
308 * cache->line * sets) / 1024;
309 }
310 }
311 default:
312 break;
313 }
314 }
315 }
316
317 /* Returns the description of caches for an Intel processor. */
318
319 static const char *
detect_caches_intel(bool xeon_mp,unsigned max_level,unsigned max_ext_level,unsigned * l2sizekb)320 detect_caches_intel (bool xeon_mp, unsigned max_level,
321 unsigned max_ext_level, unsigned *l2sizekb)
322 {
323 struct cache_desc level1 = {0, 0, 0}, level2 = {0, 0, 0}, level3 = {0, 0, 0};
324
325 if (max_level >= 4)
326 detect_caches_cpuid4 (&level1, &level2, &level3);
327 else if (max_level >= 2)
328 detect_caches_cpuid2 (xeon_mp, &level1, &level2);
329 else
330 return "";
331
332 if (level1.sizekb == 0)
333 return "";
334
335 /* Let the L3 replace the L2. This assumes inclusive caches
336 and single threaded program for now. */
337 if (level3.sizekb)
338 level2 = level3;
339
340 /* Intel CPUs are equipped with AMD style L2 cache info. Try this
341 method if other methods fail to provide L2 cache parameters. */
342 if (level2.sizekb == 0 && max_ext_level >= 0x80000006)
343 detect_l2_cache (&level2);
344
345 *l2sizekb = level2.sizekb;
346
347 return describe_cache (level1, level2);
348 }
349
350 enum vendor_signatures
351 {
352 SIG_INTEL = 0x756e6547 /* Genu */,
353 SIG_AMD = 0x68747541 /* Auth */,
354 SIG_CENTAUR = 0x746e6543 /* Cent */,
355 SIG_CYRIX = 0x69727943 /* Cyri */,
356 SIG_NSC = 0x646f6547 /* Geod */
357 };
358
359 enum processor_signatures
360 {
361 SIG_GEODE = 0x646f6547 /* Geod */
362 };
363
364 /* This will be called by the spec parser in gcc.c when it sees
365 a %:local_cpu_detect(args) construct. Currently it will be called
366 with either "arch" or "tune" as argument depending on if -march=native
367 or -mtune=native is to be substituted.
368
369 It returns a string containing new command line parameters to be
370 put at the place of the above two options, depending on what CPU
371 this is executed. E.g. "-march=k8" on an AMD64 machine
372 for -march=native.
373
374 ARGC and ARGV are set depending on the actual arguments given
375 in the spec. */
376
host_detect_local_cpu(int argc,const char ** argv)377 const char *host_detect_local_cpu (int argc, const char **argv)
378 {
379 enum processor_type processor = PROCESSOR_I386;
380 const char *cpu = "i386";
381
382 const char *cache = "";
383 const char *options = "";
384
385 unsigned int eax, ebx, ecx, edx;
386
387 unsigned int max_level, ext_level;
388
389 unsigned int vendor;
390 unsigned int model, family;
391
392 unsigned int has_sse3, has_ssse3, has_cmpxchg16b;
393 unsigned int has_cmpxchg8b, has_cmov, has_mmx, has_sse, has_sse2;
394
395 /* Extended features */
396 unsigned int has_lahf_lm = 0, has_sse4a = 0;
397 unsigned int has_longmode = 0, has_3dnowp = 0, has_3dnow = 0;
398 unsigned int has_movbe = 0, has_sse4_1 = 0, has_sse4_2 = 0;
399 unsigned int has_popcnt = 0, has_aes = 0, has_avx = 0, has_avx2 = 0;
400 unsigned int has_pclmul = 0, has_abm = 0, has_lwp = 0;
401 unsigned int has_fma = 0, has_fma4 = 0, has_xop = 0;
402 unsigned int has_bmi = 0, has_bmi2 = 0, has_tbm = 0, has_lzcnt = 0;
403 unsigned int has_rdrnd = 0, has_f16c = 0, has_fsgsbase = 0;
404 unsigned int has_osxsave = 0;
405
406 bool arch;
407
408 unsigned int l2sizekb = 0;
409
410 if (argc < 1)
411 return NULL;
412
413 arch = !strcmp (argv[0], "arch");
414
415 if (!arch && strcmp (argv[0], "tune"))
416 return NULL;
417
418 max_level = __get_cpuid_max (0, &vendor);
419 if (max_level < 1)
420 goto done;
421
422 __cpuid (1, eax, ebx, ecx, edx);
423
424 model = (eax >> 4) & 0x0f;
425 family = (eax >> 8) & 0x0f;
426 if (vendor == SIG_INTEL)
427 {
428 unsigned int extended_model, extended_family;
429
430 extended_model = (eax >> 12) & 0xf0;
431 extended_family = (eax >> 20) & 0xff;
432 if (family == 0x0f)
433 {
434 family += extended_family;
435 model += extended_model;
436 }
437 else if (family == 0x06)
438 model += extended_model;
439 }
440
441 has_sse3 = ecx & bit_SSE3;
442 has_ssse3 = ecx & bit_SSSE3;
443 has_sse4_1 = ecx & bit_SSE4_1;
444 has_sse4_2 = ecx & bit_SSE4_2;
445 has_avx = ecx & bit_AVX;
446 has_osxsave = ecx & bit_OSXSAVE;
447 has_cmpxchg16b = ecx & bit_CMPXCHG16B;
448 has_movbe = ecx & bit_MOVBE;
449 has_popcnt = ecx & bit_POPCNT;
450 has_aes = ecx & bit_AES;
451 has_pclmul = ecx & bit_PCLMUL;
452 has_fma = ecx & bit_FMA;
453 has_f16c = ecx & bit_F16C;
454 has_rdrnd = ecx & bit_RDRND;
455
456 has_cmpxchg8b = edx & bit_CMPXCHG8B;
457 has_cmov = edx & bit_CMOV;
458 has_mmx = edx & bit_MMX;
459 has_sse = edx & bit_SSE;
460 has_sse2 = edx & bit_SSE2;
461
462 if (max_level >= 7)
463 {
464 __cpuid_count (7, 0, eax, ebx, ecx, edx);
465
466 has_bmi = ebx & bit_BMI;
467 has_avx2 = ebx & bit_AVX2;
468 has_bmi2 = ebx & bit_BMI2;
469 has_fsgsbase = ebx & bit_FSGSBASE;
470 }
471
472 /* Check cpuid level of extended features. */
473 __cpuid (0x80000000, ext_level, ebx, ecx, edx);
474
475 if (ext_level > 0x80000000)
476 {
477 __cpuid (0x80000001, eax, ebx, ecx, edx);
478
479 has_lahf_lm = ecx & bit_LAHF_LM;
480 has_sse4a = ecx & bit_SSE4a;
481 has_abm = ecx & bit_ABM;
482 has_lwp = ecx & bit_LWP;
483 has_fma4 = ecx & bit_FMA4;
484 has_xop = ecx & bit_XOP;
485 has_tbm = ecx & bit_TBM;
486 has_lzcnt = ecx & bit_LZCNT;
487
488 has_longmode = edx & bit_LM;
489 has_3dnowp = edx & bit_3DNOWP;
490 has_3dnow = edx & bit_3DNOW;
491 }
492
493 /* Get XCR_XFEATURE_ENABLED_MASK register with xgetbv. */
494 #define XCR_XFEATURE_ENABLED_MASK 0x0
495 #define XSTATE_FP 0x1
496 #define XSTATE_SSE 0x2
497 #define XSTATE_YMM 0x4
498 if (has_osxsave)
499 asm (".byte 0x0f; .byte 0x01; .byte 0xd0"
500 : "=a" (eax), "=d" (edx)
501 : "c" (XCR_XFEATURE_ENABLED_MASK));
502
503 /* Check if SSE and YMM states are supported. */
504 if (!has_osxsave
505 || (eax & (XSTATE_SSE | XSTATE_YMM)) != (XSTATE_SSE | XSTATE_YMM))
506 {
507 has_avx = 0;
508 has_avx2 = 0;
509 has_fma = 0;
510 has_fma4 = 0;
511 has_f16c = 0;
512 has_xop = 0;
513 }
514
515 if (!arch)
516 {
517 if (vendor == SIG_AMD
518 || vendor == SIG_CENTAUR
519 || vendor == SIG_CYRIX
520 || vendor == SIG_NSC)
521 cache = detect_caches_amd (ext_level);
522 else if (vendor == SIG_INTEL)
523 {
524 bool xeon_mp = (family == 15 && model == 6);
525 cache = detect_caches_intel (xeon_mp, max_level,
526 ext_level, &l2sizekb);
527 }
528 }
529
530 if (vendor == SIG_AMD)
531 {
532 unsigned int name;
533
534 /* Detect geode processor by its processor signature. */
535 if (ext_level > 0x80000001)
536 __cpuid (0x80000002, name, ebx, ecx, edx);
537 else
538 name = 0;
539
540 if (name == SIG_GEODE)
541 processor = PROCESSOR_GEODE;
542 else if (has_bmi)
543 processor = PROCESSOR_BDVER2;
544 else if (has_xop)
545 processor = PROCESSOR_BDVER1;
546 else if (has_sse4a && has_ssse3)
547 processor = PROCESSOR_BTVER1;
548 else if (has_sse4a)
549 processor = PROCESSOR_AMDFAM10;
550 else if (has_sse2 || has_longmode)
551 processor = PROCESSOR_K8;
552 else if (has_3dnowp && family == 6)
553 processor = PROCESSOR_ATHLON;
554 else if (has_mmx)
555 processor = PROCESSOR_K6;
556 else
557 processor = PROCESSOR_PENTIUM;
558 }
559 else if (vendor == SIG_CENTAUR)
560 {
561 if (arch)
562 {
563 switch (family)
564 {
565 case 6:
566 if (model > 9)
567 /* Use the default detection procedure. */
568 processor = PROCESSOR_GENERIC32;
569 else if (model == 9)
570 cpu = "c3-2";
571 else if (model >= 6)
572 cpu = "c3";
573 else
574 processor = PROCESSOR_GENERIC32;
575 break;
576 case 5:
577 if (has_3dnow)
578 cpu = "winchip2";
579 else if (has_mmx)
580 cpu = "winchip2-c6";
581 else
582 processor = PROCESSOR_GENERIC32;
583 break;
584 default:
585 /* We have no idea. */
586 processor = PROCESSOR_GENERIC32;
587 }
588 }
589 }
590 else
591 {
592 switch (family)
593 {
594 case 4:
595 processor = PROCESSOR_I486;
596 break;
597 case 5:
598 processor = PROCESSOR_PENTIUM;
599 break;
600 case 6:
601 processor = PROCESSOR_PENTIUMPRO;
602 break;
603 case 15:
604 processor = PROCESSOR_PENTIUM4;
605 break;
606 default:
607 /* We have no idea. */
608 processor = PROCESSOR_GENERIC32;
609 }
610 }
611
612 switch (processor)
613 {
614 case PROCESSOR_I386:
615 /* Default. */
616 break;
617 case PROCESSOR_I486:
618 cpu = "i486";
619 break;
620 case PROCESSOR_PENTIUM:
621 if (arch && has_mmx)
622 cpu = "pentium-mmx";
623 else
624 cpu = "pentium";
625 break;
626 case PROCESSOR_PENTIUMPRO:
627 switch (model)
628 {
629 case 0x1c:
630 case 0x26:
631 /* Atom. */
632 cpu = "atom";
633 break;
634 case 0x0f:
635 /* Merom. */
636 case 0x17:
637 case 0x1d:
638 /* Penryn. */
639 cpu = "core2";
640 break;
641 case 0x1a:
642 case 0x1e:
643 case 0x1f:
644 case 0x2e:
645 /* Nehalem. */
646 case 0x25:
647 case 0x2c:
648 case 0x2f:
649 /* Westmere. */
650 cpu = "corei7";
651 break;
652 case 0x2a:
653 case 0x2d:
654 /* Sandy Bridge. */
655 cpu = "corei7-avx";
656 break;
657 case 0x3a:
658 case 0x3e:
659 /* Ivy Bridge. */
660 cpu = "core-avx-i";
661 break;
662 default:
663 if (arch)
664 {
665 /* This is unknown family 0x6 CPU. */
666 if (has_avx)
667 /* Assume Sandy Bridge. */
668 cpu = "corei7-avx";
669 else if (has_sse4_2)
670 /* Assume Core i7. */
671 cpu = "corei7";
672 else if (has_ssse3)
673 {
674 if (has_movbe)
675 /* Assume Atom. */
676 cpu = "atom";
677 else
678 /* Assume Core 2. */
679 cpu = "core2";
680 }
681 else if (has_sse3)
682 /* It is Core Duo. */
683 cpu = "pentium-m";
684 else if (has_sse2)
685 /* It is Pentium M. */
686 cpu = "pentium-m";
687 else if (has_sse)
688 /* It is Pentium III. */
689 cpu = "pentium3";
690 else if (has_mmx)
691 /* It is Pentium II. */
692 cpu = "pentium2";
693 else
694 /* Default to Pentium Pro. */
695 cpu = "pentiumpro";
696 }
697 else
698 /* For -mtune, we default to -mtune=generic. */
699 cpu = "generic";
700 break;
701 }
702 break;
703 case PROCESSOR_PENTIUM4:
704 if (has_sse3)
705 {
706 if (has_longmode)
707 cpu = "nocona";
708 else
709 cpu = "prescott";
710 }
711 else
712 cpu = "pentium4";
713 break;
714 case PROCESSOR_GEODE:
715 cpu = "geode";
716 break;
717 case PROCESSOR_K6:
718 if (arch && has_3dnow)
719 cpu = "k6-3";
720 else
721 cpu = "k6";
722 break;
723 case PROCESSOR_ATHLON:
724 if (arch && has_sse)
725 cpu = "athlon-4";
726 else
727 cpu = "athlon";
728 break;
729 case PROCESSOR_K8:
730 if (arch && has_sse3)
731 cpu = "k8-sse3";
732 else
733 cpu = "k8";
734 break;
735 case PROCESSOR_AMDFAM10:
736 cpu = "amdfam10";
737 break;
738 case PROCESSOR_BDVER1:
739 cpu = "bdver1";
740 break;
741 case PROCESSOR_BDVER2:
742 cpu = "bdver2";
743 break;
744 case PROCESSOR_BTVER1:
745 cpu = "btver1";
746 break;
747
748 default:
749 /* Use something reasonable. */
750 if (arch)
751 {
752 if (has_ssse3)
753 cpu = "core2";
754 else if (has_sse3)
755 {
756 if (has_longmode)
757 cpu = "nocona";
758 else
759 cpu = "prescott";
760 }
761 else if (has_sse2)
762 cpu = "pentium4";
763 else if (has_cmov)
764 cpu = "pentiumpro";
765 else if (has_mmx)
766 cpu = "pentium-mmx";
767 else if (has_cmpxchg8b)
768 cpu = "pentium";
769 }
770 else
771 cpu = "generic";
772 }
773
774 if (arch)
775 {
776 const char *cx16 = has_cmpxchg16b ? " -mcx16" : " -mno-cx16";
777 const char *sahf = has_lahf_lm ? " -msahf" : " -mno-sahf";
778 const char *movbe = has_movbe ? " -mmovbe" : " -mno-movbe";
779 const char *ase = has_aes ? " -maes" : " -mno-aes";
780 const char *pclmul = has_pclmul ? " -mpclmul" : " -mno-pclmul";
781 const char *popcnt = has_popcnt ? " -mpopcnt" : " -mno-popcnt";
782 const char *abm = has_abm ? " -mabm" : " -mno-abm";
783 const char *lwp = has_lwp ? " -mlwp" : " -mno-lwp";
784 const char *fma = has_fma ? " -mfma" : " -mno-fma";
785 const char *fma4 = has_fma4 ? " -mfma4" : " -mno-fma4";
786 const char *xop = has_xop ? " -mxop" : " -mno-xop";
787 const char *bmi = has_bmi ? " -mbmi" : " -mno-bmi";
788 const char *bmi2 = has_bmi2 ? " -mbmi2" : " -mno-bmi2";
789 const char *tbm = has_tbm ? " -mtbm" : " -mno-tbm";
790 const char *avx = has_avx ? " -mavx" : " -mno-avx";
791 const char *avx2 = has_avx2 ? " -mavx2" : " -mno-avx2";
792 const char *sse4_2 = has_sse4_2 ? " -msse4.2" : " -mno-sse4.2";
793 const char *sse4_1 = has_sse4_1 ? " -msse4.1" : " -mno-sse4.1";
794 const char *lzcnt = has_lzcnt ? " -mlzcnt" : " -mno-lzcnt";
795 const char *rdrnd = has_rdrnd ? " -mrdrnd" : " -mno-rdrnd";
796 const char *f16c = has_f16c ? " -mf16c" : " -mno-f16c";
797 const char *fsgsbase = has_fsgsbase ? " -mfsgsbase" : " -mno-fsgsbase";
798
799 options = concat (options, cx16, sahf, movbe, ase, pclmul,
800 popcnt, abm, lwp, fma, fma4, xop, bmi, bmi2,
801 tbm, avx, avx2, sse4_2, sse4_1, lzcnt, rdrnd,
802 f16c, fsgsbase, NULL);
803 }
804
805 done:
806 return concat (cache, "-m", argv[0], "=", cpu, options, NULL);
807 }
808 #else
809
810 /* If we aren't compiling with GCC then the driver will just ignore
811 -march and -mtune "native" target and will leave to the newly
812 built compiler to generate code for its default target. */
813
host_detect_local_cpu(int argc ATTRIBUTE_UNUSED,const char ** argv ATTRIBUTE_UNUSED)814 const char *host_detect_local_cpu (int argc ATTRIBUTE_UNUSED,
815 const char **argv ATTRIBUTE_UNUSED)
816 {
817 return NULL;
818 }
819 #endif /* __GNUC__ */
820