1;; Copyright (C) 2012-2018 Free Software Foundation, Inc. 2;; 3;; This file is part of GCC. 4;; 5;; GCC is free software; you can redistribute it and/or modify 6;; it under the terms of the GNU General Public License as published by 7;; the Free Software Foundation; either version 3, or (at your option) 8;; any later version. 9;; 10;; GCC is distributed in the hope that it will be useful, 11;; but WITHOUT ANY WARRANTY; without even the implied warranty of 12;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 13;; GNU General Public License for more details. 14;; 15;; You should have received a copy of the GNU General Public License 16;; along with GCC; see the file COPYING3. If not see 17;; <http://www.gnu.org/licenses/>. 18;; 19 20(define_attr "znver1_decode" "direct,vector,double" 21 (const_string "direct")) 22 23;; AMD znver1 Scheduling 24;; Modeling automatons for zen decoders, integer execution pipes, 25;; AGU pipes and floating point execution units. 26(define_automaton "znver1, znver1_ieu, znver1_fp, znver1_agu") 27 28;; Decoders unit has 4 decoders and all of them can decode fast path 29;; and vector type instructions. 30(define_cpu_unit "znver1-decode0" "znver1") 31(define_cpu_unit "znver1-decode1" "znver1") 32(define_cpu_unit "znver1-decode2" "znver1") 33(define_cpu_unit "znver1-decode3" "znver1") 34 35;; Currently blocking all decoders for vector path instructions as 36;; they are dispatched separetely as microcode sequence. 37;; Fix me: Need to revisit this. 38(define_reservation "znver1-vector" "znver1-decode0+znver1-decode1+znver1-decode2+znver1-decode3") 39 40;; Direct instructions can be issued to any of the four decoders. 41(define_reservation "znver1-direct" "znver1-decode0|znver1-decode1|znver1-decode2|znver1-decode3") 42 43;; Fix me: Need to revisit this later to simulate fast path double behavior. 44(define_reservation "znver1-double" "znver1-direct") 45 46 47;; Integer unit 4 ALU pipes. 48(define_cpu_unit "znver1-ieu0" "znver1_ieu") 49(define_cpu_unit "znver1-ieu1" "znver1_ieu") 50(define_cpu_unit "znver1-ieu2" "znver1_ieu") 51(define_cpu_unit "znver1-ieu3" "znver1_ieu") 52(define_reservation "znver1-ieu" "znver1-ieu0|znver1-ieu1|znver1-ieu2|znver1-ieu3") 53 54;; 2 AGU pipes. 55(define_cpu_unit "znver1-agu0" "znver1_agu") 56(define_cpu_unit "znver1-agu1" "znver1_agu") 57(define_reservation "znver1-agu-reserve" "znver1-agu0|znver1-agu1") 58 59(define_reservation "znver1-load" "znver1-agu-reserve") 60(define_reservation "znver1-store" "znver1-agu-reserve") 61 62;; vectorpath (microcoded) instructions are single issue instructions. 63;; So, they occupy all the integer units. 64(define_reservation "znver1-ivector" "znver1-ieu0+znver1-ieu1 65 +znver1-ieu2+znver1-ieu3 66 +znver1-agu0+znver1-agu1") 67 68;; Floating point unit 4 FP pipes. 69(define_cpu_unit "znver1-fp0" "znver1_fp") 70(define_cpu_unit "znver1-fp1" "znver1_fp") 71(define_cpu_unit "znver1-fp2" "znver1_fp") 72(define_cpu_unit "znver1-fp3" "znver1_fp") 73 74(define_reservation "znver1-fpu" "znver1-fp0|znver1-fp1|znver1-fp2|znver1-fp3") 75 76(define_reservation "znver1-fvector" "znver1-fp0+znver1-fp1 77 +znver1-fp2+znver1-fp3 78 +znver1-agu0+znver1-agu1") 79 80;; Call instruction 81(define_insn_reservation "znver1_call" 1 82 (and (eq_attr "cpu" "znver1") 83 (eq_attr "type" "call,callv")) 84 "znver1-double,znver1-store,znver1-ieu0|znver1-ieu3") 85 86;; General instructions 87(define_insn_reservation "znver1_push" 1 88 (and (eq_attr "cpu" "znver1") 89 (and (eq_attr "type" "push") 90 (eq_attr "memory" "none,unknown"))) 91 "znver1-direct,znver1-store") 92 93(define_insn_reservation "znver1_push_store" 1 94 (and (eq_attr "cpu" "znver1") 95 (and (eq_attr "type" "push") 96 (eq_attr "memory" "store"))) 97 "znver1-direct,znver1-store") 98 99(define_insn_reservation "znver1_push_both" 5 100 (and (eq_attr "cpu" "znver1") 101 (and (eq_attr "type" "push") 102 (eq_attr "memory" "both"))) 103 "znver1-direct,znver1-load,znver1-store") 104 105(define_insn_reservation "znver1_pop" 4 106 (and (eq_attr "cpu" "znver1") 107 (and (eq_attr "type" "pop") 108 (eq_attr "memory" "load"))) 109 "znver1-direct,znver1-load") 110 111(define_insn_reservation "znver1_pop_mem" 4 112 (and (eq_attr "cpu" "znver1") 113 (and (eq_attr "type" "pop") 114 (eq_attr "memory" "both"))) 115 "znver1-direct,znver1-load,znver1-store") 116 117;; Leave 118(define_insn_reservation "znver1_leave" 1 119 (and (eq_attr "cpu" "znver1") 120 (eq_attr "type" "leave")) 121 "znver1-double,znver1-ieu, znver1-store") 122 123;; Integer Instructions or General instructions 124;; Multiplications 125;; Reg operands 126(define_insn_reservation "znver1_imul" 3 127 (and (eq_attr "cpu" "znver1") 128 (and (eq_attr "type" "imul") 129 (eq_attr "memory" "none"))) 130 "znver1-direct,znver1-ieu1") 131 132(define_insn_reservation "znver1_imul_mem" 7 133 (and (eq_attr "cpu" "znver1") 134 (and (eq_attr "type" "imul") 135 (eq_attr "memory" "!none"))) 136 "znver1-direct,znver1-load, znver1-ieu1") 137 138;; Divisions 139;; Reg operands 140(define_insn_reservation "znver1_idiv_DI" 41 141 (and (eq_attr "cpu" "znver1") 142 (and (eq_attr "type" "idiv") 143 (and (eq_attr "mode" "DI") 144 (eq_attr "memory" "none")))) 145 "znver1-double,znver1-ieu2*41") 146 147(define_insn_reservation "znver1_idiv_SI" 25 148 (and (eq_attr "cpu" "znver1") 149 (and (eq_attr "type" "idiv") 150 (and (eq_attr "mode" "SI") 151 (eq_attr "memory" "none")))) 152 "znver1-double,znver1-ieu2*25") 153 154(define_insn_reservation "znver1_idiv_HI" 17 155 (and (eq_attr "cpu" "znver1") 156 (and (eq_attr "type" "idiv") 157 (and (eq_attr "mode" "HI") 158 (eq_attr "memory" "none")))) 159 "znver1-double,znver1-ieu2*17") 160 161(define_insn_reservation "znver1_idiv_QI" 12 162 (and (eq_attr "cpu" "znver1") 163 (and (eq_attr "type" "idiv") 164 (and (eq_attr "mode" "QI") 165 (eq_attr "memory" "none")))) 166 "znver1-direct,znver1-ieu2*12") 167 168;; Mem operands 169(define_insn_reservation "znver1_idiv_mem_DI" 45 170 (and (eq_attr "cpu" "znver1") 171 (and (eq_attr "type" "idiv") 172 (and (eq_attr "mode" "DI") 173 (eq_attr "memory" "none")))) 174 "znver1-double,znver1-load,znver1-ieu2*41") 175 176(define_insn_reservation "znver1_idiv_mem_SI" 29 177 (and (eq_attr "cpu" "znver1") 178 (and (eq_attr "type" "idiv") 179 (and (eq_attr "mode" "SI") 180 (eq_attr "memory" "none")))) 181 "znver1-double,znver1-load,znver1-ieu2*25") 182 183(define_insn_reservation "znver1_idiv_mem_HI" 21 184 (and (eq_attr "cpu" "znver1") 185 (and (eq_attr "type" "idiv") 186 (and (eq_attr "mode" "HI") 187 (eq_attr "memory" "none")))) 188 "znver1-double,znver1-load,znver1-ieu2*17") 189 190(define_insn_reservation "znver1_idiv_mem_QI" 16 191 (and (eq_attr "cpu" "znver1") 192 (and (eq_attr "type" "idiv") 193 (and (eq_attr "mode" "QI") 194 (eq_attr "memory" "none")))) 195 "znver1-direct,znver1-load,znver1-ieu2*12") 196 197;; STR ISHIFT which are micro coded. 198;; Fix me: Latency need to be rechecked. 199(define_insn_reservation "znver1_str_ishift" 6 200 (and (eq_attr "cpu" "znver1") 201 (and (eq_attr "type" "str,ishift") 202 (eq_attr "memory" "both,store"))) 203 "znver1-vector,znver1-ivector") 204;; MOV - integer moves 205(define_insn_reservation "znver1_load_imov_double" 2 206 (and (eq_attr "cpu" "znver1") 207 (and (eq_attr "znver1_decode" "double") 208 (and (eq_attr "type" "imovx") 209 (eq_attr "memory" "none")))) 210 "znver1-double,znver1-ieu") 211 212(define_insn_reservation "znver1_load_imov_direct" 1 213 (and (eq_attr "cpu" "znver1") 214 (and (eq_attr "type" "imov,imovx") 215 (eq_attr "memory" "none"))) 216 "znver1-direct,znver1-ieu") 217 218(define_insn_reservation "znver1_load_imov_double_store" 2 219 (and (eq_attr "cpu" "znver1") 220 (and (eq_attr "znver1_decode" "double") 221 (and (eq_attr "type" "imovx") 222 (eq_attr "memory" "store")))) 223 "znver1-double,znver1-ieu,znver1-store") 224 225(define_insn_reservation "znver1_load_imov_direct_store" 1 226 (and (eq_attr "cpu" "znver1") 227 (and (eq_attr "type" "imov,imovx") 228 (eq_attr "memory" "store"))) 229 "znver1-direct,znver1-ieu,znver1-store") 230 231(define_insn_reservation "znver1_load_imov_double_load" 5 232 (and (eq_attr "cpu" "znver1") 233 (and (eq_attr "znver1_decode" "double") 234 (and (eq_attr "type" "imovx") 235 (eq_attr "memory" "load")))) 236 "znver1-double,znver1-load") 237 238(define_insn_reservation "znver1_load_imov_direct_load" 4 239 (and (eq_attr "cpu" "znver1") 240 (and (eq_attr "type" "imov,imovx") 241 (eq_attr "memory" "load"))) 242 "znver1-direct,znver1-load") 243 244;; INTEGER/GENERAL instructions 245;; register/imm operands only: ALU, ICMP, NEG, NOT, ROTATE, ISHIFT, TEST 246(define_insn_reservation "znver1_insn" 1 247 (and (eq_attr "cpu" "znver1") 248 (and (eq_attr "type" "alu,icmp,negnot,rotate,rotate1,ishift,ishift1,test,setcc,incdec,icmov") 249 (eq_attr "memory" "none,unknown"))) 250 "znver1-direct,znver1-ieu") 251 252(define_insn_reservation "znver1_insn_load" 5 253 (and (eq_attr "cpu" "znver1") 254 (and (eq_attr "type" "alu,icmp,negnot,rotate,rotate1,ishift,ishift1,test,setcc,incdec,icmov") 255 (eq_attr "memory" "load"))) 256 "znver1-direct,znver1-load,znver1-ieu") 257 258(define_insn_reservation "znver1_insn_store" 1 259 (and (eq_attr "cpu" "znver1") 260 (and (eq_attr "type" "alu,icmp,negnot,rotate,rotate1,ishift1,test,setcc,incdec") 261 (eq_attr "memory" "store"))) 262 "znver1-direct,znver1-ieu,znver1-store") 263 264(define_insn_reservation "znver1_insn_both" 5 265 (and (eq_attr "cpu" "znver1") 266 (and (eq_attr "type" "alu,icmp,negnot,rotate,rotate1,ishift1,test,setcc,incdec") 267 (eq_attr "memory" "both"))) 268 "znver1-direct,znver1-load,znver1-ieu,znver1-store") 269 270;; Fix me: Other vector type insns keeping latency 6 as of now. 271(define_insn_reservation "znver1_ieu_vector" 6 272 (and (eq_attr "cpu" "znver1") 273 (eq_attr "type" "other,str,multi")) 274 "znver1-vector,znver1-ivector") 275 276;; ALU1 register operands. 277(define_insn_reservation "znver1_alu1_vector" 3 278 (and (eq_attr "cpu" "znver1") 279 (and (eq_attr "znver1_decode" "vector") 280 (and (eq_attr "type" "alu1") 281 (eq_attr "memory" "none,unknown")))) 282 "znver1-vector,znver1-ivector") 283 284(define_insn_reservation "znver1_alu1_double" 2 285 (and (eq_attr "cpu" "znver1") 286 (and (eq_attr "znver1_decode" "double") 287 (and (eq_attr "type" "alu1") 288 (eq_attr "memory" "none,unknown")))) 289 "znver1-double,znver1-ieu") 290 291(define_insn_reservation "znver1_alu1_direct" 1 292 (and (eq_attr "cpu" "znver1") 293 (and (eq_attr "znver1_decode" "direct") 294 (and (eq_attr "type" "alu1") 295 (eq_attr "memory" "none,unknown")))) 296 "znver1-direct,znver1-ieu") 297 298;; Branches : Fix me need to model conditional branches. 299(define_insn_reservation "znver1_branch" 1 300 (and (eq_attr "cpu" "znver1") 301 (and (eq_attr "type" "ibr") 302 (eq_attr "memory" "none"))) 303 "znver1-direct") 304 305;; Indirect branches check latencies. 306(define_insn_reservation "znver1_indirect_branch_mem" 6 307 (and (eq_attr "cpu" "znver1") 308 (and (eq_attr "type" "ibr") 309 (eq_attr "memory" "load"))) 310 "znver1-vector,znver1-ivector") 311 312;; LEA executes in ALU units with 1 cycle latency. 313(define_insn_reservation "znver1_lea" 1 314 (and (eq_attr "cpu" "znver1") 315 (eq_attr "type" "lea")) 316 "znver1-direct,znver1-ieu") 317 318;; Other integer instrucions 319(define_insn_reservation "znver1_idirect" 1 320 (and (eq_attr "cpu" "znver1") 321 (and (eq_attr "unit" "integer,unknown") 322 (eq_attr "memory" "none,unknown"))) 323 "znver1-direct,znver1-ieu") 324 325;; Floating point 326(define_insn_reservation "znver1_fp_cmov" 6 327 (and (eq_attr "cpu" "znver1") 328 (eq_attr "type" "fcmov")) 329 "znver1-vector,znver1-fvector") 330 331(define_insn_reservation "znver1_fp_mov_direct_load" 8 332 (and (eq_attr "cpu" "znver1") 333 (and (eq_attr "znver1_decode" "direct") 334 (and (eq_attr "type" "fmov") 335 (eq_attr "memory" "load")))) 336 "znver1-direct,znver1-load,znver1-fp3|znver1-fp1") 337 338(define_insn_reservation "znver1_fp_mov_direct_store" 5 339 (and (eq_attr "cpu" "znver1") 340 (and (eq_attr "znver1_decode" "direct") 341 (and (eq_attr "type" "fmov") 342 (eq_attr "memory" "store")))) 343 "znver1-direct,znver1-fp2|znver1-fp3,znver1-store") 344 345(define_insn_reservation "znver1_fp_mov_double" 4 346 (and (eq_attr "cpu" "znver1") 347 (and (eq_attr "znver1_decode" "double") 348 (and (eq_attr "type" "fmov") 349 (eq_attr "memory" "none")))) 350 "znver1-double,znver1-fp3") 351 352(define_insn_reservation "znver1_fp_mov_double_load" 12 353 (and (eq_attr "cpu" "znver1") 354 (and (eq_attr "znver1_decode" "double") 355 (and (eq_attr "type" "fmov") 356 (eq_attr "memory" "load")))) 357 "znver1-double,znver1-load,znver1-fp3") 358 359(define_insn_reservation "znver1_fp_mov_direct" 1 360 (and (eq_attr "cpu" "znver1") 361 (eq_attr "type" "fmov")) 362 "znver1-direct,znver1-fp3") 363 364(define_insn_reservation "znver1_fp_spc_direct" 5 365 (and (eq_attr "cpu" "znver1") 366 (and (eq_attr "type" "fpspc") 367 (eq_attr "memory" "store"))) 368 "znver1-direct,znver1-fp3,znver1-fp2") 369 370(define_insn_reservation "znver1_fp_insn_vector" 6 371 (and (eq_attr "cpu" "znver1") 372 (and (eq_attr "znver1_decode" "vector") 373 (eq_attr "type" "fpspc,mmxcvt,sselog1,ssemul,ssemov"))) 374 "znver1-vector,znver1-fvector") 375 376;; FABS 377(define_insn_reservation "znver1_fp_fsgn" 1 378 (and (eq_attr "cpu" "znver1") 379 (eq_attr "type" "fsgn")) 380 "znver1-direct,znver1-fp3") 381 382(define_insn_reservation "znver1_fp_fcmp" 2 383 (and (eq_attr "cpu" "znver1") 384 (and (eq_attr "memory" "none") 385 (and (eq_attr "znver1_decode" "double") 386 (eq_attr "type" "fcmp")))) 387 "znver1-double,znver1-fp0,znver1-fp2") 388 389(define_insn_reservation "znver1_fp_fcmp_load" 9 390 (and (eq_attr "cpu" "znver1") 391 (and (eq_attr "memory" "none") 392 (and (eq_attr "znver1_decode" "double") 393 (eq_attr "type" "fcmp")))) 394 "znver1-double,znver1-load, znver1-fp0,znver1-fp2") 395 396;;FADD FSUB FMUL 397(define_insn_reservation "znver1_fp_op_mul" 5 398 (and (eq_attr "cpu" "znver1") 399 (and (eq_attr "type" "fop,fmul") 400 (eq_attr "memory" "none"))) 401 "znver1-direct,znver1-fp0*5") 402 403(define_insn_reservation "znver1_fp_op_mul_load" 12 404 (and (eq_attr "cpu" "znver1") 405 (and (eq_attr "type" "fop,fmul") 406 (eq_attr "memory" "load"))) 407 "znver1-direct,znver1-load,znver1-fp0*5") 408 409(define_insn_reservation "znver1_fp_op_imul_load" 16 410 (and (eq_attr "cpu" "znver1") 411 (and (eq_attr "type" "fop,fmul") 412 (and (eq_attr "fp_int_src" "true") 413 (eq_attr "memory" "load")))) 414 "znver1-double,znver1-load,znver1-fp3,znver1-fp0") 415 416(define_insn_reservation "znver1_fp_op_div" 15 417 (and (eq_attr "cpu" "znver1") 418 (and (eq_attr "type" "fdiv") 419 (eq_attr "memory" "none"))) 420 "znver1-direct,znver1-fp3*15") 421 422(define_insn_reservation "znver1_fp_op_div_load" 22 423 (and (eq_attr "cpu" "znver1") 424 (and (eq_attr "type" "fdiv") 425 (eq_attr "memory" "load"))) 426 "znver1-direct,znver1-load,znver1-fp3*15") 427 428(define_insn_reservation "znver1_fp_op_idiv_load" 27 429 (and (eq_attr "cpu" "znver1") 430 (and (eq_attr "type" "fdiv") 431 (and (eq_attr "fp_int_src" "true") 432 (eq_attr "memory" "load")))) 433 "znver1-double,znver1-load,znver1-fp3*19") 434 435;; MMX, SSE, SSEn.n, AVX, AVX2 instructions 436(define_insn_reservation "znver1_fp_insn" 1 437 (and (eq_attr "cpu" "znver1") 438 (eq_attr "type" "mmx")) 439 "znver1-direct,znver1-fpu") 440 441(define_insn_reservation "znver1_mmx_add" 1 442 (and (eq_attr "cpu" "znver1") 443 (and (eq_attr "type" "mmxadd") 444 (eq_attr "memory" "none"))) 445 "znver1-direct,znver1-fp0|znver1-fp1|znver1-fp3") 446 447(define_insn_reservation "znver1_mmx_add_load" 8 448 (and (eq_attr "cpu" "znver1") 449 (and (eq_attr "type" "mmxadd") 450 (eq_attr "memory" "load"))) 451 "znver1-direct,znver1-load,znver1-fp0|znver1-fp1|znver1-fp3") 452 453(define_insn_reservation "znver1_mmx_cmp" 1 454 (and (eq_attr "cpu" "znver1") 455 (and (eq_attr "type" "mmxcmp") 456 (eq_attr "memory" "none"))) 457 "znver1-direct,znver1-fp0|znver1-fp3") 458 459(define_insn_reservation "znver1_mmx_cmp_load" 8 460 (and (eq_attr "cpu" "znver1") 461 (and (eq_attr "type" "mmxcmp") 462 (eq_attr "memory" "load"))) 463 "znver1-direct,znver1-load,znver1-fp0|znver1-fp3") 464 465(define_insn_reservation "znver1_mmx_cvt_pck_shuf" 1 466 (and (eq_attr "cpu" "znver1") 467 (and (eq_attr "type" "mmxcvt,sseshuf,sseshuf1") 468 (eq_attr "memory" "none"))) 469 "znver1-direct,znver1-fp1|znver1-fp2") 470 471(define_insn_reservation "znver1_mmx_cvt_pck_shuf_load" 8 472 (and (eq_attr "cpu" "znver1") 473 (and (eq_attr "type" "mmxcvt,sseshuf,sseshuf1") 474 (eq_attr "memory" "load"))) 475 "znver1-direct,znver1-load,znver1-fp1|znver1-fp2") 476 477(define_insn_reservation "znver1_mmx_shift_move" 1 478 (and (eq_attr "cpu" "znver1") 479 (and (eq_attr "type" "mmxshft,mmxmov") 480 (eq_attr "memory" "none"))) 481 "znver1-direct,znver1-fp2") 482 483(define_insn_reservation "znver1_mmx_shift_move_load" 8 484 (and (eq_attr "cpu" "znver1") 485 (and (eq_attr "type" "mmxshft,mmxmov") 486 (eq_attr "memory" "load"))) 487 "znver1-direct,znver1-load,znver1-fp2") 488 489(define_insn_reservation "znver1_mmx_move_store" 1 490 (and (eq_attr "cpu" "znver1") 491 (and (eq_attr "type" "mmxshft,mmxmov") 492 (eq_attr "memory" "store,both"))) 493 "znver1-direct,znver1-fp2,znver1-store") 494 495(define_insn_reservation "znver1_mmx_mul" 3 496 (and (eq_attr "cpu" "znver1") 497 (and (eq_attr "type" "mmxmul") 498 (eq_attr "memory" "none"))) 499 "znver1-direct,znver1-fp0*3") 500 501(define_insn_reservation "znver1_mmx_load" 10 502 (and (eq_attr "cpu" "znver1") 503 (and (eq_attr "type" "mmxmul") 504 (eq_attr "memory" "load"))) 505 "znver1-direct,znver1-load,znver1-fp0*3") 506 507(define_insn_reservation "znver1_avx256_log" 1 508 (and (eq_attr "cpu" "znver1") 509 (and (eq_attr "mode" "V8SF,V4DF,OI") 510 (and (eq_attr "type" "sselog") 511 (eq_attr "memory" "none")))) 512 "znver1-double,znver1-fpu") 513 514(define_insn_reservation "znver1_avx256_log_load" 8 515 (and (eq_attr "cpu" "znver1") 516 (and (eq_attr "mode" "V8SF,V4DF,OI") 517 (and (eq_attr "type" "sselog") 518 (eq_attr "memory" "load")))) 519 "znver1-double,znver1-load,znver1-fpu") 520 521(define_insn_reservation "znver1_sse_log" 1 522 (and (eq_attr "cpu" "znver1") 523 (and (eq_attr "type" "sselog") 524 (eq_attr "memory" "none"))) 525 "znver1-direct,znver1-fpu") 526 527(define_insn_reservation "znver1_sse_log_load" 8 528 (and (eq_attr "cpu" "znver1") 529 (and (eq_attr "type" "sselog") 530 (eq_attr "memory" "load"))) 531 "znver1-direct,znver1-load,znver1-fpu") 532 533(define_insn_reservation "znver1_avx256_log1" 1 534 (and (eq_attr "cpu" "znver1") 535 (and (eq_attr "mode" "V8SF,V4DF,OI") 536 (and (eq_attr "type" "sselog1") 537 (eq_attr "memory" "none")))) 538 "znver1-double,znver1-fp1|znver1-fp2") 539 540(define_insn_reservation "znver1_avx256_log1_load" 8 541 (and (eq_attr "cpu" "znver1") 542 (and (eq_attr "mode" "V8SF,V4DF,OI") 543 (and (eq_attr "type" "sselog1") 544 (eq_attr "memory" "!none")))) 545 "znver1-double,znver1-load,znver1-fp1|znver1-fp2") 546 547(define_insn_reservation "znver1_sse_log1" 1 548 (and (eq_attr "cpu" "znver1") 549 (and (eq_attr "type" "sselog1") 550 (eq_attr "memory" "none"))) 551 "znver1-direct,znver1-fp1|znver1-fp2") 552 553(define_insn_reservation "znver1_sse_log1_load" 8 554 (and (eq_attr "cpu" "znver1") 555 (and (eq_attr "type" "sselog1") 556 (eq_attr "memory" "!none"))) 557 "znver1-direct,znver1-load,znver1-fp1|znver1-fp2") 558 559(define_insn_reservation "znver1_sse_comi" 1 560 (and (eq_attr "cpu" "znver1") 561 (and (eq_attr "mode" "SF,DF,V4SF,V2DF") 562 (and (eq_attr "prefix" "!vex") 563 (and (eq_attr "prefix_extra" "0") 564 (and (eq_attr "type" "ssecomi") 565 (eq_attr "memory" "none")))))) 566 "znver1-direct,znver1-fp0|znver1-fp1") 567 568(define_insn_reservation "znver1_sse_comi_load" 8 569 (and (eq_attr "cpu" "znver1") 570 (and (eq_attr "mode" "SF,DF,V4SF,V2DF") 571 (and (eq_attr "prefix" "!vex") 572 (and (eq_attr "prefix_extra" "0") 573 (and (eq_attr "type" "ssecomi") 574 (eq_attr "memory" "load")))))) 575 "znver1-direct,znver1-load,znver1-fp0|znver1-fp1") 576 577(define_insn_reservation "znver1_sse_comi_double" 2 578 (and (eq_attr "cpu" "znver1") 579 (and (eq_attr "mode" "V4SF,V2DF,TI") 580 (and (eq_attr "prefix" "vex") 581 (and (eq_attr "prefix_extra" "0") 582 (and (eq_attr "type" "ssecomi") 583 (eq_attr "memory" "none")))))) 584 "znver1-double,znver1-fp0|znver1-fp1") 585 586(define_insn_reservation "znver1_sse_comi_double_load" 10 587 (and (eq_attr "cpu" "znver1") 588 (and (eq_attr "mode" "V4SF,V2DF,TI") 589 (and (eq_attr "prefix" "vex") 590 (and (eq_attr "prefix_extra" "0") 591 (and (eq_attr "type" "ssecomi") 592 (eq_attr "memory" "load")))))) 593 "znver1-double,znver1-load,znver1-fp0|znver1-fp1") 594 595(define_insn_reservation "znver1_sse_test" 1 596 (and (eq_attr "cpu" "znver1") 597 (and (eq_attr "mode" "SF,DF,V4SF,V2DF,TI") 598 (and (eq_attr "prefix_extra" "1") 599 (and (eq_attr "type" "ssecomi") 600 (eq_attr "memory" "none"))))) 601 "znver1-direct,znver1-fp1|znver1-fp2") 602 603(define_insn_reservation "znver1_sse_test_load" 8 604 (and (eq_attr "cpu" "znver1") 605 (and (eq_attr "mode" "SF,DF,V4SF,V2DF,TI") 606 (and (eq_attr "prefix_extra" "1") 607 (and (eq_attr "type" "ssecomi") 608 (eq_attr "memory" "load"))))) 609 "znver1-direct,znver1-load,znver1-fp1|znver1-fp2") 610 611;; SSE moves 612;; Fix me: Need to revist this again some of the moves may be restricted 613;; to some fpu pipes. 614(define_insn_reservation "znver1_sse_mov" 2 615 (and (eq_attr "cpu" "znver1") 616 (and (eq_attr "mode" "SI") 617 (and (eq_attr "isa" "avx") 618 (and (eq_attr "type" "ssemov") 619 (eq_attr "memory" "none"))))) 620 "znver1-direct,znver1-ieu0") 621 622(define_insn_reservation "znver1_avx_mov" 2 623 (and (eq_attr "cpu" "znver1") 624 (and (eq_attr "mode" "TI") 625 (and (eq_attr "isa" "avx") 626 (and (eq_attr "type" "ssemov") 627 (and (match_operand:SI 1 "register_operand") 628 (eq_attr "memory" "none")))))) 629 "znver1-direct,znver1-ieu2") 630 631(define_insn_reservation "znver1_sseavx_mov" 1 632 (and (eq_attr "cpu" "znver1") 633 (and (eq_attr "mode" "SF,DF,V4SF,V2DF,TI") 634 (and (eq_attr "type" "ssemov") 635 (eq_attr "memory" "none")))) 636 "znver1-direct,znver1-fpu") 637 638(define_insn_reservation "znver1_sseavx_mov_store" 1 639 (and (eq_attr "cpu" "znver1") 640 (and (eq_attr "mode" "SF,DF,V4SF,V2DF,TI") 641 (and (eq_attr "type" "ssemov") 642 (eq_attr "memory" "store")))) 643 "znver1-direct,znver1-fpu,znver1-store") 644 645(define_insn_reservation "znver1_sseavx_mov_load" 8 646 (and (eq_attr "cpu" "znver1") 647 (and (eq_attr "mode" "SF,DF,V4SF,V2DF,TI") 648 (and (eq_attr "type" "ssemov") 649 (eq_attr "memory" "load")))) 650 "znver1-direct,znver1-load,znver1-fpu") 651 652(define_insn_reservation "znver1_avx256_mov" 1 653 (and (eq_attr "cpu" "znver1") 654 (and (eq_attr "mode" "V8SF,V4DF,OI") 655 (and (eq_attr "type" "ssemov") 656 (eq_attr "memory" "none")))) 657 "znver1-double,znver1-fpu") 658 659(define_insn_reservation "znver1_avx256_mov_store" 1 660 (and (eq_attr "cpu" "znver1") 661 (and (eq_attr "mode" "V8SF,V4DF,OI") 662 (and (eq_attr "type" "ssemov") 663 (eq_attr "memory" "store")))) 664 "znver1-double,znver1-fpu,znver1-store") 665 666(define_insn_reservation "znver1_avx256_mov_load" 8 667 (and (eq_attr "cpu" "znver1") 668 (and (eq_attr "mode" "V8SF,V4DF,OI") 669 (and (eq_attr "type" "ssemov") 670 (eq_attr "memory" "load")))) 671 "znver1-double,znver1-load,znver1-fpu") 672 673;; SSE add 674(define_insn_reservation "znver1_sseavx_add" 3 675 (and (eq_attr "cpu" "znver1") 676 (and (eq_attr "mode" "SF,DF,V4SF,V2DF,TI") 677 (and (eq_attr "type" "sseadd") 678 (eq_attr "memory" "none")))) 679 "znver1-direct,znver1-fp2|znver1-fp3") 680 681(define_insn_reservation "znver1_sseavx_add_load" 10 682 (and (eq_attr "cpu" "znver1") 683 (and (eq_attr "mode" "SF,DF,V4SF,V2DF,TI") 684 (and (eq_attr "type" "sseadd") 685 (eq_attr "memory" "load")))) 686 "znver1-direct,znver1-load,znver1-fp2|znver1-fp3") 687 688(define_insn_reservation "znver1_avx256_add" 3 689 (and (eq_attr "cpu" "znver1") 690 (and (eq_attr "mode" "V8SF,V4DF,OI") 691 (and (eq_attr "type" "sseadd") 692 (eq_attr "memory" "none")))) 693 "znver1-double,znver1-fp2|znver1-fp3") 694 695(define_insn_reservation "znver1_avx256_add_load" 10 696 (and (eq_attr "cpu" "znver1") 697 (and (eq_attr "mode" "V8SF,V4DF,OI") 698 (and (eq_attr "type" "sseadd") 699 (eq_attr "memory" "load")))) 700 "znver1-double,znver1-load,znver1-fp2|znver1-fp3") 701 702(define_insn_reservation "znver1_sseavx_fma" 5 703 (and (eq_attr "cpu" "znver1") 704 (and (eq_attr "mode" "SF,DF,V4SF,V2DF") 705 (and (eq_attr "type" "ssemuladd") 706 (eq_attr "memory" "none")))) 707 "znver1-direct,znver1-fp0|znver1-fp1") 708 709(define_insn_reservation "znver1_sseavx_fma_load" 12 710 (and (eq_attr "cpu" "znver1") 711 (and (eq_attr "mode" "SF,DF,V4SF,V2DF") 712 (and (eq_attr "type" "ssemuladd") 713 (eq_attr "memory" "load")))) 714 "znver1-direct,znver1-load,znver1-fp0|znver1-fp1") 715 716(define_insn_reservation "znver1_avx256_fma" 5 717 (and (eq_attr "cpu" "znver1") 718 (and (eq_attr "mode" "V8SF,V4DF") 719 (and (eq_attr "type" "ssemuladd") 720 (eq_attr "memory" "none")))) 721 "znver1-double,znver1-fp0|znver1-fp1") 722 723(define_insn_reservation "znver1_avx256_fma_load" 12 724 (and (eq_attr "cpu" "znver1") 725 (and (eq_attr "mode" "V8SF,V4DF") 726 (and (eq_attr "type" "ssemuladd") 727 (eq_attr "memory" "load")))) 728 "znver1-double,znver1-load,znver1-fp0|znver1-fp1") 729 730(define_insn_reservation "znver1_sseavx_iadd" 1 731 (and (eq_attr "cpu" "znver1") 732 (and (eq_attr "mode" "DI,TI") 733 (and (eq_attr "type" "sseiadd") 734 (eq_attr "memory" "none")))) 735 "znver1-direct,znver1-fp0|znver1-fp1|znver1-fp3") 736 737(define_insn_reservation "znver1_sseavx_iadd_load" 8 738 (and (eq_attr "cpu" "znver1") 739 (and (eq_attr "mode" "DI,TI") 740 (and (eq_attr "type" "sseiadd") 741 (eq_attr "memory" "load")))) 742 "znver1-direct,znver1-load,znver1-fp0|znver1-fp1|znver1-fp3") 743 744(define_insn_reservation "znver1_avx256_iadd" 1 745 (and (eq_attr "cpu" "znver1") 746 (and (eq_attr "mode" "OI") 747 (and (eq_attr "type" "sseiadd") 748 (eq_attr "memory" "none")))) 749 "znver1-double,znver1-fp0|znver1-fp1|znver1-fp3") 750 751(define_insn_reservation "znver1_avx256_iadd_load" 8 752 (and (eq_attr "cpu" "znver1") 753 (and (eq_attr "mode" "OI") 754 (and (eq_attr "type" "sseiadd") 755 (eq_attr "memory" "load")))) 756 "znver1-double,znver1-load,znver1-fp0|znver1-fp1|znver1-fp3") 757 758;; SSE conversions. 759(define_insn_reservation "znver1_ssecvtsf_si_load" 12 760 (and (eq_attr "cpu" "znver1") 761 (and (eq_attr "mode" "SI") 762 (and (eq_attr "type" "sseicvt") 763 (and (match_operand:SF 1 "memory_operand") 764 (eq_attr "memory" "load"))))) 765 "znver1-double,znver1-load,znver1-fp3,znver1-ieu0") 766 767(define_insn_reservation "znver1_ssecvtdf_si" 5 768 (and (eq_attr "cpu" "znver1") 769 (and (eq_attr "mode" "SI") 770 (and (match_operand:DF 1 "register_operand") 771 (and (eq_attr "type" "sseicvt") 772 (eq_attr "memory" "none"))))) 773 "znver1-double,znver1-fp3,znver1-ieu0") 774 775(define_insn_reservation "znver1_ssecvtdf_si_load" 12 776 (and (eq_attr "cpu" "znver1") 777 (and (eq_attr "mode" "SI") 778 (and (eq_attr "type" "sseicvt") 779 (and (match_operand:DF 1 "memory_operand") 780 (eq_attr "memory" "load"))))) 781 "znver1-double,znver1-load,znver1-fp3,znver1-ieu0") 782 783;; All other used ssecvt fp3 pipes 784;; Check: Need to revisit this again. 785;; Some SSE converts may use different pipe combinations. 786(define_insn_reservation "znver1_ssecvt" 4 787 (and (eq_attr "cpu" "znver1") 788 (and (eq_attr "type" "ssecvt") 789 (eq_attr "memory" "none"))) 790 "znver1-direct,znver1-fp3") 791 792(define_insn_reservation "znver1_ssecvt_load" 11 793 (and (eq_attr "cpu" "znver1") 794 (and (eq_attr "type" "ssecvt") 795 (eq_attr "memory" "load"))) 796 "znver1-direct,znver1-load,znver1-fp3") 797 798;; SSE div 799(define_insn_reservation "znver1_ssediv_ss_ps" 10 800 (and (eq_attr "cpu" "znver1") 801 (and (eq_attr "mode" "V4SF,SF") 802 (and (eq_attr "type" "ssediv") 803 (eq_attr "memory" "none")))) 804 "znver1-direct,znver1-fp3*10") 805 806(define_insn_reservation "znver1_ssediv_ss_ps_load" 17 807 (and (eq_attr "cpu" "znver1") 808 (and (eq_attr "mode" "V4SF,SF") 809 (and (eq_attr "type" "ssediv") 810 (eq_attr "memory" "load")))) 811 "znver1-direct,znver1-load,znver1-fp3*10") 812 813(define_insn_reservation "znver1_ssediv_sd_pd" 13 814 (and (eq_attr "cpu" "znver1") 815 (and (eq_attr "mode" "V2DF,DF") 816 (and (eq_attr "type" "ssediv") 817 (eq_attr "memory" "none")))) 818 "znver1-direct,znver1-fp3*13") 819 820(define_insn_reservation "znver1_ssediv_sd_pd_load" 20 821 (and (eq_attr "cpu" "znver1") 822 (and (eq_attr "mode" "V2DF,DF") 823 (and (eq_attr "type" "ssediv") 824 (eq_attr "memory" "load")))) 825 "znver1-direct,znver1-load,znver1-fp3*13") 826 827(define_insn_reservation "znver1_ssediv_avx256_ps" 12 828 (and (eq_attr "cpu" "znver1") 829 (and (eq_attr "mode" "V8SF") 830 (and (eq_attr "memory" "none") 831 (eq_attr "type" "ssediv")))) 832 "znver1-double,znver1-fp3*12") 833 834(define_insn_reservation "znver1_ssediv_avx256_ps_load" 19 835 (and (eq_attr "cpu" "znver1") 836 (and (eq_attr "mode" "V8SF") 837 (and (eq_attr "type" "ssediv") 838 (eq_attr "memory" "load")))) 839 "znver1-double,znver1-load,znver1-fp3*12") 840 841(define_insn_reservation "znver1_ssediv_avx256_pd" 15 842 (and (eq_attr "cpu" "znver1") 843 (and (eq_attr "mode" "V4DF") 844 (and (eq_attr "type" "ssediv") 845 (eq_attr "memory" "none")))) 846 "znver1-double,znver1-fp3*15") 847 848(define_insn_reservation "znver1_ssediv_avx256_pd_load" 22 849 (and (eq_attr "cpu" "znver1") 850 (and (eq_attr "mode" "V4DF") 851 (and (eq_attr "type" "ssediv") 852 (eq_attr "memory" "load")))) 853 "znver1-double,znver1-load,znver1-fp3*15") 854;; SSE MUL 855(define_insn_reservation "znver1_ssemul_ss_ps" 3 856 (and (eq_attr "cpu" "znver1") 857 (and (eq_attr "mode" "V4SF,SF") 858 (and (eq_attr "type" "ssemul") 859 (eq_attr "memory" "none")))) 860 "znver1-direct,(znver1-fp0|znver1-fp1)*3") 861 862(define_insn_reservation "znver1_ssemul_ss_ps_load" 10 863 (and (eq_attr "cpu" "znver1") 864 (and (eq_attr "mode" "V4SF,SF") 865 (and (eq_attr "type" "ssemul") 866 (eq_attr "memory" "load")))) 867 "znver1-direct,znver1-load,(znver1-fp0|znver1-fp1)*3") 868 869(define_insn_reservation "znver1_ssemul_avx256_ps" 3 870 (and (eq_attr "cpu" "znver1") 871 (and (eq_attr "mode" "V8SF") 872 (and (eq_attr "type" "ssemul") 873 (eq_attr "memory" "none")))) 874 "znver1-double,(znver1-fp0|znver1-fp1)*3") 875 876(define_insn_reservation "znver1_ssemul_avx256_ps_load" 10 877 (and (eq_attr "cpu" "znver1") 878 (and (eq_attr "mode" "V8SF") 879 (and (eq_attr "type" "ssemul") 880 (eq_attr "memory" "load")))) 881 "znver1-double,znver1-load,(znver1-fp0|znver1-fp1)*3") 882 883(define_insn_reservation "znver1_ssemul_sd_pd" 4 884 (and (eq_attr "cpu" "znver1") 885 (and (eq_attr "mode" "V2DF,DF") 886 (and (eq_attr "type" "ssemul") 887 (eq_attr "memory" "none")))) 888 "znver1-direct,(znver1-fp0|znver1-fp1)*4") 889 890(define_insn_reservation "znver1_ssemul_sd_pd_load" 11 891 (and (eq_attr "cpu" "znver1") 892 (and (eq_attr "mode" "V2DF,DF") 893 (and (eq_attr "type" "ssemul") 894 (eq_attr "memory" "load")))) 895 "znver1-direct,znver1-load,(znver1-fp0|znver1-fp1)*4") 896 897(define_insn_reservation "znver1_ssemul_avx256_pd" 5 898 (and (eq_attr "cpu" "znver1") 899 (and (eq_attr "mode" "V4DF") 900 (and (eq_attr "mode" "V4DF") 901 (and (eq_attr "type" "ssemul") 902 (eq_attr "memory" "none"))))) 903 "znver1-double,(znver1-fp0|znver1-fp1)*4") 904 905(define_insn_reservation "znver1_ssemul_avx256_pd_load" 12 906 (and (eq_attr "cpu" "znver1") 907 (and (eq_attr "mode" "V4DF") 908 (and (eq_attr "type" "ssemul") 909 (eq_attr "memory" "load")))) 910 "znver1-double,znver1-load,(znver1-fp0|znver1-fp1)*4") 911 912;;SSE imul 913(define_insn_reservation "znver1_sseimul" 3 914 (and (eq_attr "cpu" "znver1") 915 (and (eq_attr "mode" "TI") 916 (and (eq_attr "type" "sseimul") 917 (eq_attr "memory" "none")))) 918 "znver1-direct,znver1-fp0*3") 919 920(define_insn_reservation "znver1_sseimul_avx256" 4 921 (and (eq_attr "cpu" "znver1") 922 (and (eq_attr "mode" "OI") 923 (and (eq_attr "type" "sseimul") 924 (eq_attr "memory" "none")))) 925 "znver1-double,znver1-fp0*4") 926 927(define_insn_reservation "znver1_sseimul_load" 10 928 (and (eq_attr "cpu" "znver1") 929 (and (eq_attr "mode" "TI") 930 (and (eq_attr "type" "sseimul") 931 (eq_attr "memory" "load")))) 932 "znver1-direct,znver1-load,znver1-fp0*3") 933 934(define_insn_reservation "znver1_sseimul_avx256_load" 11 935 (and (eq_attr "cpu" "znver1") 936 (and (eq_attr "mode" "OI") 937 (and (eq_attr "type" "sseimul") 938 (eq_attr "memory" "load")))) 939 "znver1-double,znver1-load,znver1-fp0*4") 940 941(define_insn_reservation "znver1_sseimul_di" 3 942 (and (eq_attr "cpu" "znver1") 943 (and (eq_attr "mode" "DI") 944 (and (eq_attr "memory" "none") 945 (eq_attr "type" "sseimul")))) 946 "znver1-direct,znver1-fp0*3") 947 948(define_insn_reservation "znver1_sseimul_load_di" 10 949 (and (eq_attr "cpu" "znver1") 950 (and (eq_attr "mode" "DI") 951 (and (eq_attr "type" "sseimul") 952 (eq_attr "memory" "load")))) 953 "znver1-direct,znver1-load,znver1-fp0*3") 954 955;; SSE compares 956(define_insn_reservation "znver1_sse_cmp" 1 957 (and (eq_attr "cpu" "znver1") 958 (and (eq_attr "mode" "SF,DF,V4SF,V2DF") 959 (and (eq_attr "type" "ssecmp") 960 (eq_attr "memory" "none")))) 961 "znver1-direct,znver1-fp0|znver1-fp1") 962 963(define_insn_reservation "znver1_sse_cmp_load" 8 964 (and (eq_attr "cpu" "znver1") 965 (and (eq_attr "mode" "SF,DF,V4SF,V2DF") 966 (and (eq_attr "type" "ssecmp") 967 (eq_attr "memory" "load")))) 968 "znver1-direct,znver1-load,znver1-fp0|znver1-fp1") 969 970(define_insn_reservation "znver1_sse_cmp_avx256" 1 971 (and (eq_attr "cpu" "znver1") 972 (and (eq_attr "mode" "V8SF,V4DF") 973 (and (eq_attr "type" "ssecmp") 974 (eq_attr "memory" "none")))) 975 "znver1-double,znver1-fp0|znver1-fp1") 976 977(define_insn_reservation "znver1_sse_cmp_avx256_load" 8 978 (and (eq_attr "cpu" "znver1") 979 (and (eq_attr "mode" "V8SF,V4DF") 980 (and (eq_attr "type" "ssecmp") 981 (eq_attr "memory" "load")))) 982 "znver1-double,znver1-load,znver1-fp0|znver1-fp1") 983 984(define_insn_reservation "znver1_sse_icmp" 1 985 (and (eq_attr "cpu" "znver1") 986 (and (eq_attr "mode" "QI,HI,SI,DI,TI") 987 (and (eq_attr "type" "ssecmp") 988 (eq_attr "memory" "none")))) 989 "znver1-direct,znver1-fp0|znver1-fp3") 990 991(define_insn_reservation "znver1_sse_icmp_load" 8 992 (and (eq_attr "cpu" "znver1") 993 (and (eq_attr "mode" "QI,HI,SI,DI,TI") 994 (and (eq_attr "type" "ssecmp") 995 (eq_attr "memory" "load")))) 996 "znver1-direct,znver1-load,znver1-fp0|znver1-fp3") 997 998(define_insn_reservation "znver1_sse_icmp_avx256" 1 999 (and (eq_attr "cpu" "znver1") 1000 (and (eq_attr "mode" "OI") 1001 (and (eq_attr "type" "ssecmp") 1002 (eq_attr "memory" "none")))) 1003 "znver1-double,znver1-fp0|znver1-fp3") 1004 1005(define_insn_reservation "znver1_sse_icmp_avx256_load" 8 1006 (and (eq_attr "cpu" "znver1") 1007 (and (eq_attr "mode" "OI") 1008 (and (eq_attr "type" "ssecmp") 1009 (eq_attr "memory" "load")))) 1010 "znver1-double,znver1-load,znver1-fp0|znver1-fp3") 1011