1 /*-
2 * SPDX-License-Identifier: BSD-3-Clause
3 *
4 * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/
5 * Copyright (c) 2012 Damjan Marion <dmarion@Freebsd.org>
6 * All rights reserved.
7 *
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions
10 * are met:
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
16 * 3. Neither the name of authors nor the names of its contributors may be
17 * used to endorse or promote products derived from this software without
18 * specific prior written permission.
19 *
20 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
24 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
25 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
26 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
27 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
28 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
29 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
30 * SUCH DAMAGE.
31 */
32
33 #include <sys/cdefs.h>
34 #include <sys/param.h>
35 #include <sys/systm.h>
36 #include <sys/endian.h>
37 #include <sys/mbuf.h>
38 #include <sys/lock.h>
39 #include <sys/mutex.h>
40 #include <sys/kernel.h>
41 #include <sys/module.h>
42 #include <sys/socket.h>
43 #include <sys/sysctl.h>
44
45 #include <sys/sockio.h>
46 #include <sys/bus.h>
47 #include <machine/bus.h>
48 #include <sys/rman.h>
49 #include <machine/resource.h>
50
51 #include <dev/ofw/ofw_bus.h>
52 #include <dev/ofw/ofw_bus_subr.h>
53
54 #include <arm/ti/ti_scm.h>
55 #include <arm/ti/ti_sysc.h>
56
57 #include <arm/ti/ti_edma3.h>
58
59 #define TI_EDMA3_NUM_TCS 3
60 #define TI_EDMA3_NUM_IRQS 3
61 #define TI_EDMA3_NUM_DMA_CHS 64
62 #define TI_EDMA3_NUM_QDMA_CHS 8
63
64 #define TI_EDMA3CC_PID 0x000
65 #define TI_EDMA3CC_DCHMAP(p) (0x100 + ((p)*4))
66 #define TI_EDMA3CC_DMAQNUM(n) (0x240 + ((n)*4))
67 #define TI_EDMA3CC_QDMAQNUM 0x260
68 #define TI_EDMA3CC_EMCR 0x308
69 #define TI_EDMA3CC_EMCRH 0x30C
70 #define TI_EDMA3CC_QEMCR 0x314
71 #define TI_EDMA3CC_CCERR 0x318
72 #define TI_EDMA3CC_CCERRCLR 0x31C
73 #define TI_EDMA3CC_DRAE(p) (0x340 + ((p)*8))
74 #define TI_EDMA3CC_DRAEH(p) (0x344 + ((p)*8))
75 #define TI_EDMA3CC_QRAE(p) (0x380 + ((p)*4))
76 #define TI_EDMA3CC_S_ESR(p) (0x2010 + ((p)*0x200))
77 #define TI_EDMA3CC_S_ESRH(p) (0x2014 + ((p)*0x200))
78 #define TI_EDMA3CC_S_SECR(p) (0x2040 + ((p)*0x200))
79 #define TI_EDMA3CC_S_SECRH(p) (0x2044 + ((p)*0x200))
80 #define TI_EDMA3CC_S_EESR(p) (0x2030 + ((p)*0x200))
81 #define TI_EDMA3CC_S_EESRH(p) (0x2034 + ((p)*0x200))
82 #define TI_EDMA3CC_S_IESR(p) (0x2060 + ((p)*0x200))
83 #define TI_EDMA3CC_S_IESRH(p) (0x2064 + ((p)*0x200))
84 #define TI_EDMA3CC_S_IPR(p) (0x2068 + ((p)*0x200))
85 #define TI_EDMA3CC_S_IPRH(p) (0x206C + ((p)*0x200))
86 #define TI_EDMA3CC_S_QEESR(p) (0x208C + ((p)*0x200))
87
88 #define TI_EDMA3CC_PARAM_OFFSET 0x4000
89 #define TI_EDMA3CC_OPT(p) (TI_EDMA3CC_PARAM_OFFSET + 0x0 + ((p)*0x20))
90
91 #define TI_EDMA3CC_DMAQNUM_SET(c,q) ((0x7 & (q)) << (((c) % 8) * 4))
92 #define TI_EDMA3CC_DMAQNUM_CLR(c) (~(0x7 << (((c) % 8) * 4)))
93 #define TI_EDMA3CC_QDMAQNUM_SET(c,q) ((0x7 & (q)) << ((c) * 4))
94 #define TI_EDMA3CC_QDMAQNUM_CLR(c) (~(0x7 << ((c) * 4)))
95
96 #define TI_EDMA3CC_OPT_TCC_CLR (~(0x3F000))
97 #define TI_EDMA3CC_OPT_TCC_SET(p) (((0x3F000 >> 12) & (p)) << 12)
98
99 struct ti_edma3_softc {
100 device_t sc_dev;
101 /*
102 * We use one-element array in case if we need to add
103 * mem resources for transfer control windows
104 */
105 struct resource * mem_res[1];
106 struct resource * irq_res[TI_EDMA3_NUM_IRQS];
107 void *ih_cookie[TI_EDMA3_NUM_IRQS];
108 };
109
110 static struct ti_edma3_softc *ti_edma3_sc = NULL;
111
112 static struct resource_spec ti_edma3_mem_spec[] = {
113 { SYS_RES_MEMORY, 0, RF_ACTIVE },
114 { -1, 0, 0 }
115 };
116 static struct resource_spec ti_edma3_irq_spec[] = {
117 { SYS_RES_IRQ, 0, RF_ACTIVE },
118 { SYS_RES_IRQ, 1, RF_ACTIVE },
119 { SYS_RES_IRQ, 2, RF_ACTIVE },
120 { -1, 0, 0 }
121 };
122
123 /* Read/Write macros */
124 #define ti_edma3_cc_rd_4(reg) bus_read_4(ti_edma3_sc->mem_res[0], reg)
125 #define ti_edma3_cc_wr_4(reg, val) bus_write_4(ti_edma3_sc->mem_res[0], reg, val)
126
127 static void ti_edma3_intr_comp(void *arg);
128 static void ti_edma3_intr_mperr(void *arg);
129 static void ti_edma3_intr_err(void *arg);
130
131 static struct {
132 driver_intr_t *handler;
133 char * description;
134 } ti_edma3_intrs[TI_EDMA3_NUM_IRQS] = {
135 { ti_edma3_intr_comp, "EDMA Completion Interrupt" },
136 { ti_edma3_intr_mperr, "EDMA Memory Protection Error Interrupt" },
137 { ti_edma3_intr_err, "EDMA Error Interrupt" },
138 };
139
140 static int
ti_edma3_probe(device_t dev)141 ti_edma3_probe(device_t dev)
142 {
143
144 if (!ofw_bus_status_okay(dev))
145 return (ENXIO);
146
147 if (!ofw_bus_is_compatible(dev, "ti,edma3"))
148 return (ENXIO);
149
150 device_set_desc(dev, "TI EDMA Controller");
151 return (0);
152 }
153
154 static int
ti_edma3_attach(device_t dev)155 ti_edma3_attach(device_t dev)
156 {
157 struct ti_edma3_softc *sc = device_get_softc(dev);
158 uint32_t reg;
159 int err;
160 int i;
161
162 if (ti_edma3_sc)
163 return (ENXIO);
164
165 ti_edma3_sc = sc;
166 sc->sc_dev = dev;
167
168 /* Request the memory resources */
169 err = bus_alloc_resources(dev, ti_edma3_mem_spec, sc->mem_res);
170 if (err) {
171 device_printf(dev, "Error: could not allocate mem resources\n");
172 return (ENXIO);
173 }
174
175 /* Request the IRQ resources */
176 err = bus_alloc_resources(dev, ti_edma3_irq_spec, sc->irq_res);
177 if (err) {
178 device_printf(dev, "Error: could not allocate irq resources\n");
179 return (ENXIO);
180 }
181
182 /* FIXME: Require DTS from Linux kernel 5.7 */
183 /* FIXME: OK to enable clkctrl here? */
184 /* Enable Channel Controller */
185 ti_sysc_clock_enable(device_get_parent(dev));
186
187 reg = ti_edma3_cc_rd_4(TI_EDMA3CC_PID);
188
189 device_printf(dev, "EDMA revision %08x\n", reg);
190
191 /* Attach interrupt handlers */
192 for (i = 0; i < TI_EDMA3_NUM_IRQS; ++i) {
193 err = bus_setup_intr(dev, sc->irq_res[i], INTR_TYPE_MISC |
194 INTR_MPSAFE, NULL, *ti_edma3_intrs[i].handler,
195 sc, &sc->ih_cookie[i]);
196 if (err) {
197 device_printf(dev, "could not setup %s\n",
198 ti_edma3_intrs[i].description);
199 return (err);
200 }
201 }
202
203 return (0);
204 }
205
206 static device_method_t ti_edma3_methods[] = {
207 DEVMETHOD(device_probe, ti_edma3_probe),
208 DEVMETHOD(device_attach, ti_edma3_attach),
209 {0, 0},
210 };
211
212 static driver_t ti_edma3_driver = {
213 "ti_edma3",
214 ti_edma3_methods,
215 sizeof(struct ti_edma3_softc),
216 };
217 static devclass_t ti_edma3_devclass;
218
219 DRIVER_MODULE(ti_edma3, simplebus, ti_edma3_driver, ti_edma3_devclass, 0, 0);
220 MODULE_DEPEND(ti_edma3, ti_sysc, 1, 1, 1);
221
222 static void
ti_edma3_intr_comp(void * arg)223 ti_edma3_intr_comp(void *arg)
224 {
225 printf("%s: unimplemented\n", __func__);
226 }
227
228 static void
ti_edma3_intr_mperr(void * arg)229 ti_edma3_intr_mperr(void *arg)
230 {
231 printf("%s: unimplemented\n", __func__);
232 }
233
234 static void
ti_edma3_intr_err(void * arg)235 ti_edma3_intr_err(void *arg)
236 {
237 printf("%s: unimplemented\n", __func__);
238 }
239
240 void
ti_edma3_init(unsigned int eqn)241 ti_edma3_init(unsigned int eqn)
242 {
243 uint32_t reg;
244 int i;
245
246 /* Clear Event Missed Regs */
247 ti_edma3_cc_wr_4(TI_EDMA3CC_EMCR, 0xFFFFFFFF);
248 ti_edma3_cc_wr_4(TI_EDMA3CC_EMCRH, 0xFFFFFFFF);
249 ti_edma3_cc_wr_4(TI_EDMA3CC_QEMCR, 0xFFFFFFFF);
250
251 /* Clear Error Reg */
252 ti_edma3_cc_wr_4(TI_EDMA3CC_CCERRCLR, 0xFFFFFFFF);
253
254 /* Enable DMA channels 0-63 */
255 ti_edma3_cc_wr_4(TI_EDMA3CC_DRAE(0), 0xFFFFFFFF);
256 ti_edma3_cc_wr_4(TI_EDMA3CC_DRAEH(0), 0xFFFFFFFF);
257
258 for (i = 0; i < 64; i++) {
259 ti_edma3_cc_wr_4(TI_EDMA3CC_DCHMAP(i), i<<5);
260 }
261
262 /* Initialize the DMA Queue Number Registers */
263 for (i = 0; i < TI_EDMA3_NUM_DMA_CHS; i++) {
264 reg = ti_edma3_cc_rd_4(TI_EDMA3CC_DMAQNUM(i>>3));
265 reg &= TI_EDMA3CC_DMAQNUM_CLR(i);
266 reg |= TI_EDMA3CC_DMAQNUM_SET(i, eqn);
267 ti_edma3_cc_wr_4(TI_EDMA3CC_DMAQNUM(i>>3), reg);
268 }
269
270 /* Enable the QDMA Region access for all channels */
271 ti_edma3_cc_wr_4(TI_EDMA3CC_QRAE(0), (1 << TI_EDMA3_NUM_QDMA_CHS) - 1);
272
273 /*Initialize QDMA Queue Number Registers */
274 for (i = 0; i < TI_EDMA3_NUM_QDMA_CHS; i++) {
275 reg = ti_edma3_cc_rd_4(TI_EDMA3CC_QDMAQNUM);
276 reg &= TI_EDMA3CC_QDMAQNUM_CLR(i);
277 reg |= TI_EDMA3CC_QDMAQNUM_SET(i, eqn);
278 ti_edma3_cc_wr_4(TI_EDMA3CC_QDMAQNUM, reg);
279 }
280 }
281
282 #ifdef notyet
283 int
ti_edma3_enable_event_intr(unsigned int ch)284 ti_edma3_enable_event_intr(unsigned int ch)
285 {
286 uint32_t reg;
287
288 if (ch >= TI_EDMA3_NUM_DMA_CHS)
289 return (EINVAL);
290
291 if (ch < 32) {
292 ti_edma3_cc_wr_4(TI_EDMA3CC_S_IESR(0), 1 << ch);
293 } else {
294 ti_edma3_cc_wr_4(TI_EDMA3CC_S_IESRH(0), 1 << (ch - 32));
295 }
296 return 0;
297 }
298 #endif
299
300 int
ti_edma3_request_dma_ch(unsigned int ch,unsigned int tccn,unsigned int eqn)301 ti_edma3_request_dma_ch(unsigned int ch, unsigned int tccn, unsigned int eqn)
302 {
303 uint32_t reg;
304
305 if (ch >= TI_EDMA3_NUM_DMA_CHS)
306 return (EINVAL);
307
308 /* Enable the DMA channel in the DRAE/DRAEH registers */
309 if (ch < 32) {
310 reg = ti_edma3_cc_rd_4(TI_EDMA3CC_DRAE(0));
311 reg |= (0x01 << ch);
312 ti_edma3_cc_wr_4(TI_EDMA3CC_DRAE(0), reg);
313 } else {
314 reg = ti_edma3_cc_rd_4(TI_EDMA3CC_DRAEH(0));
315 reg |= (0x01 << (ch - 32));
316 ti_edma3_cc_wr_4(TI_EDMA3CC_DRAEH(0), reg);
317 }
318
319 /* Associate DMA Channel to Event Queue */
320 reg = ti_edma3_cc_rd_4(TI_EDMA3CC_DMAQNUM(ch >> 3));
321 reg &= TI_EDMA3CC_DMAQNUM_CLR(ch);
322 reg |= TI_EDMA3CC_DMAQNUM_SET((ch), eqn);
323 ti_edma3_cc_wr_4(TI_EDMA3CC_DMAQNUM(ch >> 3), reg);
324
325 /* Set TCC in corresponding PaRAM Entry */
326 reg = ti_edma3_cc_rd_4(TI_EDMA3CC_OPT(ch));
327 reg &= TI_EDMA3CC_OPT_TCC_CLR;
328 reg |= TI_EDMA3CC_OPT_TCC_SET(ch);
329 ti_edma3_cc_wr_4(TI_EDMA3CC_OPT(ch), reg);
330
331 return 0;
332 }
333
334 int
ti_edma3_request_qdma_ch(unsigned int ch,unsigned int tccn,unsigned int eqn)335 ti_edma3_request_qdma_ch(unsigned int ch, unsigned int tccn, unsigned int eqn)
336 {
337 uint32_t reg;
338
339 if (ch >= TI_EDMA3_NUM_DMA_CHS)
340 return (EINVAL);
341
342 /* Enable the QDMA channel in the QRAE registers */
343 reg = ti_edma3_cc_rd_4(TI_EDMA3CC_QRAE(0));
344 reg |= (0x01 << ch);
345 ti_edma3_cc_wr_4(TI_EDMA3CC_QRAE(0), reg);
346
347 /* Associate QDMA Channel to Event Queue */
348 reg = ti_edma3_cc_rd_4(TI_EDMA3CC_QDMAQNUM);
349 reg |= TI_EDMA3CC_QDMAQNUM_SET(ch, eqn);
350 ti_edma3_cc_wr_4(TI_EDMA3CC_QDMAQNUM, reg);
351
352 /* Set TCC in corresponding PaRAM Entry */
353 reg = ti_edma3_cc_rd_4(TI_EDMA3CC_OPT(ch));
354 reg &= TI_EDMA3CC_OPT_TCC_CLR;
355 reg |= TI_EDMA3CC_OPT_TCC_SET(ch);
356 ti_edma3_cc_wr_4(TI_EDMA3CC_OPT(ch), reg);
357
358 return 0;
359 }
360
361 int
ti_edma3_enable_transfer_manual(unsigned int ch)362 ti_edma3_enable_transfer_manual(unsigned int ch)
363 {
364 if (ch >= TI_EDMA3_NUM_DMA_CHS)
365 return (EINVAL);
366
367 /* set corresponding bit in ESR/ESRH to set a event */
368 if (ch < 32) {
369 ti_edma3_cc_wr_4(TI_EDMA3CC_S_ESR(0), 1 << ch);
370 } else {
371 ti_edma3_cc_wr_4(TI_EDMA3CC_S_ESRH(0), 1 << (ch - 32));
372 }
373
374 return 0;
375 }
376
377 int
ti_edma3_enable_transfer_qdma(unsigned int ch)378 ti_edma3_enable_transfer_qdma(unsigned int ch)
379 {
380 if (ch >= TI_EDMA3_NUM_QDMA_CHS)
381 return (EINVAL);
382
383 /* set corresponding bit in QEESR to enable QDMA event */
384 ti_edma3_cc_wr_4(TI_EDMA3CC_S_QEESR(0), (1 << ch));
385
386 return 0;
387 }
388
389 int
ti_edma3_enable_transfer_event(unsigned int ch)390 ti_edma3_enable_transfer_event(unsigned int ch)
391 {
392 if (ch >= TI_EDMA3_NUM_DMA_CHS)
393 return (EINVAL);
394
395 /* Clear SECR(H) & EMCR(H) to clean any previous NULL request
396 * and set corresponding bit in EESR to enable DMA event */
397 if(ch < 32) {
398 ti_edma3_cc_wr_4(TI_EDMA3CC_S_SECR(0), (1 << ch));
399 ti_edma3_cc_wr_4(TI_EDMA3CC_EMCR, (1 << ch));
400 ti_edma3_cc_wr_4(TI_EDMA3CC_S_EESR(0), (1 << ch));
401 } else {
402 ti_edma3_cc_wr_4(TI_EDMA3CC_S_SECRH(0), 1 << (ch - 32));
403 ti_edma3_cc_wr_4(TI_EDMA3CC_EMCRH, 1 << (ch - 32));
404 ti_edma3_cc_wr_4(TI_EDMA3CC_S_EESRH(0), 1 << (ch - 32));
405 }
406
407 return 0;
408 }
409
410 void
ti_edma3_param_write(unsigned int ch,struct ti_edma3cc_param_set * prs)411 ti_edma3_param_write(unsigned int ch, struct ti_edma3cc_param_set *prs)
412 {
413 bus_write_region_4(ti_edma3_sc->mem_res[0], TI_EDMA3CC_OPT(ch),
414 (uint32_t *) prs, 8);
415 }
416
417 void
ti_edma3_param_read(unsigned int ch,struct ti_edma3cc_param_set * prs)418 ti_edma3_param_read(unsigned int ch, struct ti_edma3cc_param_set *prs)
419 {
420 bus_read_region_4(ti_edma3_sc->mem_res[0], TI_EDMA3CC_OPT(ch),
421 (uint32_t *) prs, 8);
422 }
423