1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
3 *
4 * Copyright (c) 2008 Hans Petter Selasky. All rights reserved.
5 * Copyright (c) 1998 The NetBSD Foundation, Inc. All rights reserved.
6 * Copyright (c) 1998 Lennart Augustsson. All rights reserved.
7 *
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions
10 * are met:
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
27 * SUCH DAMAGE.
28 */
29
30 /*
31 * USB Universal Host Controller driver.
32 * Handles e.g. PIIX3 and PIIX4.
33 *
34 * UHCI spec: http://developer.intel.com/design/USB/UHCI11D.htm
35 * USB spec: http://www.usb.org/developers/docs/usbspec.zip
36 * PIIXn spec: ftp://download.intel.com/design/intarch/datashts/29055002.pdf
37 * ftp://download.intel.com/design/intarch/datashts/29056201.pdf
38 */
39
40 #ifdef USB_GLOBAL_INCLUDE_FILE
41 #include USB_GLOBAL_INCLUDE_FILE
42 #else
43 #include <sys/stdint.h>
44 #include <sys/stddef.h>
45 #include <sys/param.h>
46 #include <sys/queue.h>
47 #include <sys/types.h>
48 #include <sys/systm.h>
49 #include <sys/kernel.h>
50 #include <sys/bus.h>
51 #include <sys/module.h>
52 #include <sys/lock.h>
53 #include <sys/mutex.h>
54 #include <sys/condvar.h>
55 #include <sys/sysctl.h>
56 #include <sys/sx.h>
57 #include <sys/unistd.h>
58 #include <sys/callout.h>
59 #include <sys/malloc.h>
60 #include <sys/priv.h>
61
62 #include <dev/usb/usb.h>
63 #include <dev/usb/usbdi.h>
64
65 #define USB_DEBUG_VAR uhcidebug
66
67 #include <dev/usb/usb_core.h>
68 #include <dev/usb/usb_debug.h>
69 #include <dev/usb/usb_busdma.h>
70 #include <dev/usb/usb_process.h>
71 #include <dev/usb/usb_transfer.h>
72 #include <dev/usb/usb_device.h>
73 #include <dev/usb/usb_hub.h>
74 #include <dev/usb/usb_util.h>
75
76 #include <dev/usb/usb_controller.h>
77 #include <dev/usb/usb_bus.h>
78 #endif /* USB_GLOBAL_INCLUDE_FILE */
79
80 #include <dev/usb/controller/uhci.h>
81 #include <dev/usb/controller/uhcireg.h>
82
83 #define alt_next next
84 #define UHCI_BUS2SC(bus) \
85 __containerof(bus, uhci_softc_t, sc_bus)
86
87 #ifdef USB_DEBUG
88 static int uhcidebug = 0;
89 static int uhcinoloop = 0;
90
91 static SYSCTL_NODE(_hw_usb, OID_AUTO, uhci, CTLFLAG_RW | CTLFLAG_MPSAFE, 0,
92 "USB uhci");
93 SYSCTL_INT(_hw_usb_uhci, OID_AUTO, debug, CTLFLAG_RWTUN,
94 &uhcidebug, 0, "uhci debug level");
95 SYSCTL_INT(_hw_usb_uhci, OID_AUTO, loop, CTLFLAG_RWTUN,
96 &uhcinoloop, 0, "uhci noloop");
97
98 static void uhci_dumpregs(uhci_softc_t *sc);
99 static void uhci_dump_tds(uhci_td_t *td);
100
101 #endif
102
103 #define UBARR(sc) bus_space_barrier((sc)->sc_io_tag, (sc)->sc_io_hdl, 0, (sc)->sc_io_size, \
104 BUS_SPACE_BARRIER_READ|BUS_SPACE_BARRIER_WRITE)
105 #define UWRITE1(sc, r, x) \
106 do { UBARR(sc); bus_space_write_1((sc)->sc_io_tag, (sc)->sc_io_hdl, (r), (x)); \
107 } while (/*CONSTCOND*/0)
108 #define UWRITE2(sc, r, x) \
109 do { UBARR(sc); bus_space_write_2((sc)->sc_io_tag, (sc)->sc_io_hdl, (r), (x)); \
110 } while (/*CONSTCOND*/0)
111 #define UWRITE4(sc, r, x) \
112 do { UBARR(sc); bus_space_write_4((sc)->sc_io_tag, (sc)->sc_io_hdl, (r), (x)); \
113 } while (/*CONSTCOND*/0)
114 #define UREAD1(sc, r) (UBARR(sc), bus_space_read_1((sc)->sc_io_tag, (sc)->sc_io_hdl, (r)))
115 #define UREAD2(sc, r) (UBARR(sc), bus_space_read_2((sc)->sc_io_tag, (sc)->sc_io_hdl, (r)))
116 #define UREAD4(sc, r) (UBARR(sc), bus_space_read_4((sc)->sc_io_tag, (sc)->sc_io_hdl, (r)))
117
118 #define UHCICMD(sc, cmd) UWRITE2(sc, UHCI_CMD, cmd)
119 #define UHCISTS(sc) UREAD2(sc, UHCI_STS)
120
121 #define UHCI_RESET_TIMEOUT 100 /* ms, reset timeout */
122
123 #define UHCI_INTR_ENDPT 1
124
125 struct uhci_mem_layout {
126 struct usb_page_search buf_res;
127 struct usb_page_search fix_res;
128
129 struct usb_page_cache *buf_pc;
130 struct usb_page_cache *fix_pc;
131
132 uint32_t buf_offset;
133
134 uint16_t max_frame_size;
135 };
136
137 struct uhci_std_temp {
138 struct uhci_mem_layout ml;
139 uhci_td_t *td;
140 uhci_td_t *td_next;
141 uint32_t average;
142 uint32_t td_status;
143 uint32_t td_token;
144 uint32_t len;
145 uint16_t max_frame_size;
146 uint8_t shortpkt;
147 uint8_t setup_alt_next;
148 uint8_t last_frame;
149 };
150
151 static const struct usb_bus_methods uhci_bus_methods;
152 static const struct usb_pipe_methods uhci_device_bulk_methods;
153 static const struct usb_pipe_methods uhci_device_ctrl_methods;
154 static const struct usb_pipe_methods uhci_device_intr_methods;
155 static const struct usb_pipe_methods uhci_device_isoc_methods;
156
157 static uint8_t uhci_restart(uhci_softc_t *sc);
158 static void uhci_do_poll(struct usb_bus *);
159 static void uhci_device_done(struct usb_xfer *, usb_error_t);
160 static void uhci_transfer_intr_enqueue(struct usb_xfer *);
161 static void uhci_timeout(void *);
162 static uint8_t uhci_check_transfer(struct usb_xfer *);
163 static void uhci_root_intr(uhci_softc_t *sc);
164
165 void
uhci_iterate_hw_softc(struct usb_bus * bus,usb_bus_mem_sub_cb_t * cb)166 uhci_iterate_hw_softc(struct usb_bus *bus, usb_bus_mem_sub_cb_t *cb)
167 {
168 struct uhci_softc *sc = UHCI_BUS2SC(bus);
169 uint32_t i;
170
171 cb(bus, &sc->sc_hw.pframes_pc, &sc->sc_hw.pframes_pg,
172 sizeof(uint32_t) * UHCI_FRAMELIST_COUNT, UHCI_FRAMELIST_ALIGN);
173
174 cb(bus, &sc->sc_hw.ls_ctl_start_pc, &sc->sc_hw.ls_ctl_start_pg,
175 sizeof(uhci_qh_t), UHCI_QH_ALIGN);
176
177 cb(bus, &sc->sc_hw.fs_ctl_start_pc, &sc->sc_hw.fs_ctl_start_pg,
178 sizeof(uhci_qh_t), UHCI_QH_ALIGN);
179
180 cb(bus, &sc->sc_hw.bulk_start_pc, &sc->sc_hw.bulk_start_pg,
181 sizeof(uhci_qh_t), UHCI_QH_ALIGN);
182
183 cb(bus, &sc->sc_hw.last_qh_pc, &sc->sc_hw.last_qh_pg,
184 sizeof(uhci_qh_t), UHCI_QH_ALIGN);
185
186 cb(bus, &sc->sc_hw.last_td_pc, &sc->sc_hw.last_td_pg,
187 sizeof(uhci_td_t), UHCI_TD_ALIGN);
188
189 for (i = 0; i != UHCI_VFRAMELIST_COUNT; i++) {
190 cb(bus, sc->sc_hw.isoc_start_pc + i,
191 sc->sc_hw.isoc_start_pg + i,
192 sizeof(uhci_td_t), UHCI_TD_ALIGN);
193 }
194
195 for (i = 0; i != UHCI_IFRAMELIST_COUNT; i++) {
196 cb(bus, sc->sc_hw.intr_start_pc + i,
197 sc->sc_hw.intr_start_pg + i,
198 sizeof(uhci_qh_t), UHCI_QH_ALIGN);
199 }
200 }
201
202 static void
uhci_mem_layout_init(struct uhci_mem_layout * ml,struct usb_xfer * xfer)203 uhci_mem_layout_init(struct uhci_mem_layout *ml, struct usb_xfer *xfer)
204 {
205 ml->buf_pc = xfer->frbuffers + 0;
206 ml->fix_pc = xfer->buf_fixup;
207
208 ml->buf_offset = 0;
209
210 ml->max_frame_size = xfer->max_frame_size;
211 }
212
213 static void
uhci_mem_layout_fixup(struct uhci_mem_layout * ml,struct uhci_td * td)214 uhci_mem_layout_fixup(struct uhci_mem_layout *ml, struct uhci_td *td)
215 {
216 usbd_get_page(ml->buf_pc, ml->buf_offset, &ml->buf_res);
217
218 if (ml->buf_res.length < td->len) {
219 /* need to do a fixup */
220
221 usbd_get_page(ml->fix_pc, 0, &ml->fix_res);
222
223 td->td_buffer = htole32(ml->fix_res.physaddr);
224
225 /*
226 * The UHCI driver cannot handle
227 * page crossings, so a fixup is
228 * needed:
229 *
230 * +----+----+ - - -
231 * | YYY|Y |
232 * +----+----+ - - -
233 * \ \
234 * \ \
235 * +----+
236 * |YYYY| (fixup)
237 * +----+
238 */
239
240 if ((td->td_token & htole32(UHCI_TD_PID)) ==
241 htole32(UHCI_TD_PID_IN)) {
242 td->fix_pc = ml->fix_pc;
243 usb_pc_cpu_invalidate(ml->fix_pc);
244
245 } else {
246 td->fix_pc = NULL;
247
248 /* copy data to fixup location */
249
250 usbd_copy_out(ml->buf_pc, ml->buf_offset,
251 ml->fix_res.buffer, td->len);
252
253 usb_pc_cpu_flush(ml->fix_pc);
254 }
255
256 /* prepare next fixup */
257
258 ml->fix_pc++;
259
260 } else {
261 td->td_buffer = htole32(ml->buf_res.physaddr);
262 td->fix_pc = NULL;
263 }
264
265 /* prepare next data location */
266
267 ml->buf_offset += td->len;
268 }
269
270 /*
271 * Return values:
272 * 0: Success
273 * Else: Failure
274 */
275 static uint8_t
uhci_restart(uhci_softc_t * sc)276 uhci_restart(uhci_softc_t *sc)
277 {
278 struct usb_page_search buf_res;
279
280 USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED);
281
282 if (UREAD2(sc, UHCI_CMD) & UHCI_CMD_RS) {
283 DPRINTFN(2, "Already started\n");
284 return (0);
285 }
286
287 DPRINTFN(2, "Restarting\n");
288
289 usbd_get_page(&sc->sc_hw.pframes_pc, 0, &buf_res);
290
291 /* Reload fresh base address */
292 UWRITE4(sc, UHCI_FLBASEADDR, buf_res.physaddr);
293
294 /*
295 * Assume 64 byte packets at frame end and start HC controller:
296 */
297 UHCICMD(sc, (UHCI_CMD_MAXP | UHCI_CMD_RS));
298
299 /* wait 10 milliseconds */
300
301 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 100);
302
303 /* check that controller has started */
304
305 if (UREAD2(sc, UHCI_STS) & UHCI_STS_HCH) {
306 DPRINTFN(2, "Failed\n");
307 return (1);
308 }
309 return (0);
310 }
311
312 void
uhci_reset(uhci_softc_t * sc)313 uhci_reset(uhci_softc_t *sc)
314 {
315 uint16_t n;
316
317 USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED);
318
319 DPRINTF("resetting the HC\n");
320
321 /* disable interrupts */
322
323 UWRITE2(sc, UHCI_INTR, 0);
324
325 /* global reset */
326
327 UHCICMD(sc, UHCI_CMD_GRESET);
328
329 /* wait */
330
331 usb_pause_mtx(&sc->sc_bus.bus_mtx,
332 USB_MS_TO_TICKS(USB_BUS_RESET_DELAY));
333
334 /* terminate all transfers */
335
336 UHCICMD(sc, UHCI_CMD_HCRESET);
337
338 /* the reset bit goes low when the controller is done */
339
340 n = UHCI_RESET_TIMEOUT;
341 while (n--) {
342 /* wait one millisecond */
343
344 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 1000);
345
346 if (!(UREAD2(sc, UHCI_CMD) & UHCI_CMD_HCRESET)) {
347 goto done_1;
348 }
349 }
350
351 device_printf(sc->sc_bus.bdev,
352 "controller did not reset\n");
353
354 done_1:
355
356 n = 10;
357 while (n--) {
358 /* wait one millisecond */
359
360 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 1000);
361
362 /* check if HC is stopped */
363 if (UREAD2(sc, UHCI_STS) & UHCI_STS_HCH) {
364 goto done_2;
365 }
366 }
367
368 device_printf(sc->sc_bus.bdev,
369 "controller did not stop\n");
370
371 done_2:
372
373 /* reset frame number */
374 UWRITE2(sc, UHCI_FRNUM, 0);
375 /* set default SOF value */
376 UWRITE1(sc, UHCI_SOF, 0x40);
377
378 USB_BUS_UNLOCK(&sc->sc_bus);
379
380 /* stop root interrupt */
381 usb_callout_drain(&sc->sc_root_intr);
382
383 USB_BUS_LOCK(&sc->sc_bus);
384 }
385
386 static void
uhci_start(uhci_softc_t * sc)387 uhci_start(uhci_softc_t *sc)
388 {
389 USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED);
390
391 DPRINTFN(2, "enabling\n");
392
393 /* enable interrupts */
394
395 UWRITE2(sc, UHCI_INTR,
396 (UHCI_INTR_TOCRCIE |
397 UHCI_INTR_RIE |
398 UHCI_INTR_IOCE |
399 UHCI_INTR_SPIE));
400
401 if (uhci_restart(sc)) {
402 device_printf(sc->sc_bus.bdev,
403 "cannot start HC controller\n");
404 }
405
406 /* start root interrupt */
407 uhci_root_intr(sc);
408 }
409
410 static struct uhci_qh *
uhci_init_qh(struct usb_page_cache * pc)411 uhci_init_qh(struct usb_page_cache *pc)
412 {
413 struct usb_page_search buf_res;
414 struct uhci_qh *qh;
415
416 usbd_get_page(pc, 0, &buf_res);
417
418 qh = buf_res.buffer;
419
420 qh->qh_self =
421 htole32(buf_res.physaddr) |
422 htole32(UHCI_PTR_QH);
423
424 qh->page_cache = pc;
425
426 return (qh);
427 }
428
429 static struct uhci_td *
uhci_init_td(struct usb_page_cache * pc)430 uhci_init_td(struct usb_page_cache *pc)
431 {
432 struct usb_page_search buf_res;
433 struct uhci_td *td;
434
435 usbd_get_page(pc, 0, &buf_res);
436
437 td = buf_res.buffer;
438
439 td->td_self =
440 htole32(buf_res.physaddr) |
441 htole32(UHCI_PTR_TD);
442
443 td->page_cache = pc;
444
445 return (td);
446 }
447
448 usb_error_t
uhci_init(uhci_softc_t * sc)449 uhci_init(uhci_softc_t *sc)
450 {
451 uint16_t bit;
452 uint16_t x;
453 uint16_t y;
454
455 DPRINTF("start\n");
456
457 usb_callout_init_mtx(&sc->sc_root_intr, &sc->sc_bus.bus_mtx, 0);
458
459 #ifdef USB_DEBUG
460 if (uhcidebug > 2) {
461 uhci_dumpregs(sc);
462 }
463 #endif
464 /*
465 * Setup QH's
466 */
467 sc->sc_ls_ctl_p_last =
468 uhci_init_qh(&sc->sc_hw.ls_ctl_start_pc);
469
470 sc->sc_fs_ctl_p_last =
471 uhci_init_qh(&sc->sc_hw.fs_ctl_start_pc);
472
473 sc->sc_bulk_p_last =
474 uhci_init_qh(&sc->sc_hw.bulk_start_pc);
475 #if 0
476 sc->sc_reclaim_qh_p =
477 sc->sc_fs_ctl_p_last;
478 #else
479 /* setup reclaim looping point */
480 sc->sc_reclaim_qh_p =
481 sc->sc_bulk_p_last;
482 #endif
483
484 sc->sc_last_qh_p =
485 uhci_init_qh(&sc->sc_hw.last_qh_pc);
486
487 sc->sc_last_td_p =
488 uhci_init_td(&sc->sc_hw.last_td_pc);
489
490 for (x = 0; x != UHCI_VFRAMELIST_COUNT; x++) {
491 sc->sc_isoc_p_last[x] =
492 uhci_init_td(sc->sc_hw.isoc_start_pc + x);
493 }
494
495 for (x = 0; x != UHCI_IFRAMELIST_COUNT; x++) {
496 sc->sc_intr_p_last[x] =
497 uhci_init_qh(sc->sc_hw.intr_start_pc + x);
498 }
499
500 /*
501 * the QHs are arranged to give poll intervals that are
502 * powers of 2 times 1ms
503 */
504 bit = UHCI_IFRAMELIST_COUNT / 2;
505 while (bit) {
506 x = bit;
507 while (x & bit) {
508 uhci_qh_t *qh_x;
509 uhci_qh_t *qh_y;
510
511 y = (x ^ bit) | (bit / 2);
512
513 /*
514 * the next QH has half the poll interval
515 */
516 qh_x = sc->sc_intr_p_last[x];
517 qh_y = sc->sc_intr_p_last[y];
518
519 qh_x->h_next = NULL;
520 qh_x->qh_h_next = qh_y->qh_self;
521 qh_x->e_next = NULL;
522 qh_x->qh_e_next = htole32(UHCI_PTR_T);
523 x++;
524 }
525 bit >>= 1;
526 }
527
528 if (1) {
529 uhci_qh_t *qh_ls;
530 uhci_qh_t *qh_intr;
531
532 qh_ls = sc->sc_ls_ctl_p_last;
533 qh_intr = sc->sc_intr_p_last[0];
534
535 /* start QH for interrupt traffic */
536 qh_intr->h_next = qh_ls;
537 qh_intr->qh_h_next = qh_ls->qh_self;
538 qh_intr->e_next = 0;
539 qh_intr->qh_e_next = htole32(UHCI_PTR_T);
540 }
541 for (x = 0; x != UHCI_VFRAMELIST_COUNT; x++) {
542 uhci_td_t *td_x;
543 uhci_qh_t *qh_intr;
544
545 td_x = sc->sc_isoc_p_last[x];
546 qh_intr = sc->sc_intr_p_last[x | (UHCI_IFRAMELIST_COUNT / 2)];
547
548 /* start TD for isochronous traffic */
549 td_x->next = NULL;
550 td_x->td_next = qh_intr->qh_self;
551 td_x->td_status = htole32(UHCI_TD_IOS);
552 td_x->td_token = htole32(0);
553 td_x->td_buffer = htole32(0);
554 }
555
556 if (1) {
557 uhci_qh_t *qh_ls;
558 uhci_qh_t *qh_fs;
559
560 qh_ls = sc->sc_ls_ctl_p_last;
561 qh_fs = sc->sc_fs_ctl_p_last;
562
563 /* start QH where low speed control traffic will be queued */
564 qh_ls->h_next = qh_fs;
565 qh_ls->qh_h_next = qh_fs->qh_self;
566 qh_ls->e_next = 0;
567 qh_ls->qh_e_next = htole32(UHCI_PTR_T);
568 }
569 if (1) {
570 uhci_qh_t *qh_ctl;
571 uhci_qh_t *qh_blk;
572 uhci_qh_t *qh_lst;
573 uhci_td_t *td_lst;
574
575 qh_ctl = sc->sc_fs_ctl_p_last;
576 qh_blk = sc->sc_bulk_p_last;
577
578 /* start QH where full speed control traffic will be queued */
579 qh_ctl->h_next = qh_blk;
580 qh_ctl->qh_h_next = qh_blk->qh_self;
581 qh_ctl->e_next = 0;
582 qh_ctl->qh_e_next = htole32(UHCI_PTR_T);
583
584 qh_lst = sc->sc_last_qh_p;
585
586 /* start QH where bulk traffic will be queued */
587 qh_blk->h_next = qh_lst;
588 qh_blk->qh_h_next = qh_lst->qh_self;
589 qh_blk->e_next = 0;
590 qh_blk->qh_e_next = htole32(UHCI_PTR_T);
591
592 td_lst = sc->sc_last_td_p;
593
594 /* end QH which is used for looping the QHs */
595 qh_lst->h_next = 0;
596 qh_lst->qh_h_next = htole32(UHCI_PTR_T); /* end of QH chain */
597 qh_lst->e_next = td_lst;
598 qh_lst->qh_e_next = td_lst->td_self;
599
600 /*
601 * end TD which hangs from the last QH, to avoid a bug in the PIIX
602 * that makes it run berserk otherwise
603 */
604 td_lst->next = 0;
605 td_lst->td_next = htole32(UHCI_PTR_T);
606 td_lst->td_status = htole32(0); /* inactive */
607 td_lst->td_token = htole32(0);
608 td_lst->td_buffer = htole32(0);
609 }
610 if (1) {
611 struct usb_page_search buf_res;
612 uint32_t *pframes;
613
614 usbd_get_page(&sc->sc_hw.pframes_pc, 0, &buf_res);
615
616 pframes = buf_res.buffer;
617
618 /*
619 * Setup UHCI framelist
620 *
621 * Execution order:
622 *
623 * pframes -> full speed isochronous -> interrupt QH's -> low
624 * speed control -> full speed control -> bulk transfers
625 *
626 */
627
628 for (x = 0; x != UHCI_FRAMELIST_COUNT; x++) {
629 pframes[x] =
630 sc->sc_isoc_p_last[x % UHCI_VFRAMELIST_COUNT]->td_self;
631 }
632 }
633 /* flush all cache into memory */
634
635 usb_bus_mem_flush_all(&sc->sc_bus, &uhci_iterate_hw_softc);
636
637 /* set up the bus struct */
638 sc->sc_bus.methods = &uhci_bus_methods;
639
640 USB_BUS_LOCK(&sc->sc_bus);
641 /* reset the controller */
642 uhci_reset(sc);
643
644 /* start the controller */
645 uhci_start(sc);
646 USB_BUS_UNLOCK(&sc->sc_bus);
647
648 /* catch lost interrupts */
649 uhci_do_poll(&sc->sc_bus);
650
651 return (0);
652 }
653
654 static void
uhci_suspend(uhci_softc_t * sc)655 uhci_suspend(uhci_softc_t *sc)
656 {
657 #ifdef USB_DEBUG
658 if (uhcidebug > 2) {
659 uhci_dumpregs(sc);
660 }
661 #endif
662
663 USB_BUS_LOCK(&sc->sc_bus);
664
665 /* stop the controller */
666
667 uhci_reset(sc);
668
669 /* enter global suspend */
670
671 UHCICMD(sc, UHCI_CMD_EGSM);
672
673 USB_BUS_UNLOCK(&sc->sc_bus);
674 }
675
676 static void
uhci_resume(uhci_softc_t * sc)677 uhci_resume(uhci_softc_t *sc)
678 {
679 USB_BUS_LOCK(&sc->sc_bus);
680
681 /* reset the controller */
682
683 uhci_reset(sc);
684
685 /* force global resume */
686
687 UHCICMD(sc, UHCI_CMD_FGR);
688
689 /* and start traffic again */
690
691 uhci_start(sc);
692
693 USB_BUS_UNLOCK(&sc->sc_bus);
694
695 #ifdef USB_DEBUG
696 if (uhcidebug > 2)
697 uhci_dumpregs(sc);
698 #endif
699
700 /* catch lost interrupts */
701 uhci_do_poll(&sc->sc_bus);
702 }
703
704 #ifdef USB_DEBUG
705 static void
uhci_dumpregs(uhci_softc_t * sc)706 uhci_dumpregs(uhci_softc_t *sc)
707 {
708 DPRINTFN(0, "%s regs: cmd=%04x, sts=%04x, intr=%04x, frnum=%04x, "
709 "flbase=%08x, sof=%04x, portsc1=%04x, portsc2=%04x\n",
710 device_get_nameunit(sc->sc_bus.bdev),
711 UREAD2(sc, UHCI_CMD),
712 UREAD2(sc, UHCI_STS),
713 UREAD2(sc, UHCI_INTR),
714 UREAD2(sc, UHCI_FRNUM),
715 UREAD4(sc, UHCI_FLBASEADDR),
716 UREAD1(sc, UHCI_SOF),
717 UREAD2(sc, UHCI_PORTSC1),
718 UREAD2(sc, UHCI_PORTSC2));
719 }
720
721 static uint8_t
uhci_dump_td(uhci_td_t * p)722 uhci_dump_td(uhci_td_t *p)
723 {
724 uint32_t td_next;
725 uint32_t td_status;
726 uint32_t td_token;
727 uint8_t temp;
728
729 usb_pc_cpu_invalidate(p->page_cache);
730
731 td_next = le32toh(p->td_next);
732 td_status = le32toh(p->td_status);
733 td_token = le32toh(p->td_token);
734
735 /*
736 * Check whether the link pointer in this TD marks the link pointer
737 * as end of queue:
738 */
739 temp = ((td_next & UHCI_PTR_T) || (td_next == 0));
740
741 printf("TD(%p) at 0x%08x = link=0x%08x status=0x%08x "
742 "token=0x%08x buffer=0x%08x\n",
743 p,
744 le32toh(p->td_self),
745 td_next,
746 td_status,
747 td_token,
748 le32toh(p->td_buffer));
749
750 printf("TD(%p) td_next=%s%s%s td_status=%s%s%s%s%s%s%s%s%s%s%s, errcnt=%d, actlen=%d pid=%02x,"
751 "addr=%d,endpt=%d,D=%d,maxlen=%d\n",
752 p,
753 (td_next & 1) ? "-T" : "",
754 (td_next & 2) ? "-Q" : "",
755 (td_next & 4) ? "-VF" : "",
756 (td_status & UHCI_TD_BITSTUFF) ? "-BITSTUFF" : "",
757 (td_status & UHCI_TD_CRCTO) ? "-CRCTO" : "",
758 (td_status & UHCI_TD_NAK) ? "-NAK" : "",
759 (td_status & UHCI_TD_BABBLE) ? "-BABBLE" : "",
760 (td_status & UHCI_TD_DBUFFER) ? "-DBUFFER" : "",
761 (td_status & UHCI_TD_STALLED) ? "-STALLED" : "",
762 (td_status & UHCI_TD_ACTIVE) ? "-ACTIVE" : "",
763 (td_status & UHCI_TD_IOC) ? "-IOC" : "",
764 (td_status & UHCI_TD_IOS) ? "-IOS" : "",
765 (td_status & UHCI_TD_LS) ? "-LS" : "",
766 (td_status & UHCI_TD_SPD) ? "-SPD" : "",
767 UHCI_TD_GET_ERRCNT(td_status),
768 UHCI_TD_GET_ACTLEN(td_status),
769 UHCI_TD_GET_PID(td_token),
770 UHCI_TD_GET_DEVADDR(td_token),
771 UHCI_TD_GET_ENDPT(td_token),
772 UHCI_TD_GET_DT(td_token),
773 UHCI_TD_GET_MAXLEN(td_token));
774
775 return (temp);
776 }
777
778 static uint8_t
uhci_dump_qh(uhci_qh_t * sqh)779 uhci_dump_qh(uhci_qh_t *sqh)
780 {
781 uint8_t temp;
782 uint32_t qh_h_next;
783 uint32_t qh_e_next;
784
785 usb_pc_cpu_invalidate(sqh->page_cache);
786
787 qh_h_next = le32toh(sqh->qh_h_next);
788 qh_e_next = le32toh(sqh->qh_e_next);
789
790 DPRINTFN(0, "QH(%p) at 0x%08x: h_next=0x%08x e_next=0x%08x\n", sqh,
791 le32toh(sqh->qh_self), qh_h_next, qh_e_next);
792
793 temp = ((((sqh->h_next != NULL) && !(qh_h_next & UHCI_PTR_T)) ? 1 : 0) |
794 (((sqh->e_next != NULL) && !(qh_e_next & UHCI_PTR_T)) ? 2 : 0));
795
796 return (temp);
797 }
798
799 static void
uhci_dump_all(uhci_softc_t * sc)800 uhci_dump_all(uhci_softc_t *sc)
801 {
802 uhci_dumpregs(sc);
803 uhci_dump_qh(sc->sc_ls_ctl_p_last);
804 uhci_dump_qh(sc->sc_fs_ctl_p_last);
805 uhci_dump_qh(sc->sc_bulk_p_last);
806 uhci_dump_qh(sc->sc_last_qh_p);
807 }
808
809 static void
uhci_dump_tds(uhci_td_t * td)810 uhci_dump_tds(uhci_td_t *td)
811 {
812 for (;
813 td != NULL;
814 td = td->obj_next) {
815 if (uhci_dump_td(td)) {
816 break;
817 }
818 }
819 }
820
821 #endif
822
823 /*
824 * Let the last QH loop back to the full speed control transfer QH.
825 * This is what intel calls "bandwidth reclamation" and improves
826 * USB performance a lot for some devices.
827 * If we are already looping, just count it.
828 */
829 static void
uhci_add_loop(uhci_softc_t * sc)830 uhci_add_loop(uhci_softc_t *sc)
831 {
832 struct uhci_qh *qh_lst;
833 struct uhci_qh *qh_rec;
834
835 #ifdef USB_DEBUG
836 if (uhcinoloop) {
837 return;
838 }
839 #endif
840 if (++(sc->sc_loops) == 1) {
841 DPRINTFN(6, "add\n");
842
843 qh_lst = sc->sc_last_qh_p;
844 qh_rec = sc->sc_reclaim_qh_p;
845
846 /* NOTE: we don't loop back the soft pointer */
847
848 qh_lst->qh_h_next = qh_rec->qh_self;
849 usb_pc_cpu_flush(qh_lst->page_cache);
850 }
851 }
852
853 static void
uhci_rem_loop(uhci_softc_t * sc)854 uhci_rem_loop(uhci_softc_t *sc)
855 {
856 struct uhci_qh *qh_lst;
857
858 #ifdef USB_DEBUG
859 if (uhcinoloop) {
860 return;
861 }
862 #endif
863 if (--(sc->sc_loops) == 0) {
864 DPRINTFN(6, "remove\n");
865
866 qh_lst = sc->sc_last_qh_p;
867 qh_lst->qh_h_next = htole32(UHCI_PTR_T);
868 usb_pc_cpu_flush(qh_lst->page_cache);
869 }
870 }
871
872 static void
uhci_transfer_intr_enqueue(struct usb_xfer * xfer)873 uhci_transfer_intr_enqueue(struct usb_xfer *xfer)
874 {
875 /* check for early completion */
876 if (uhci_check_transfer(xfer)) {
877 return;
878 }
879 /* put transfer on interrupt queue */
880 usbd_transfer_enqueue(&xfer->xroot->bus->intr_q, xfer);
881
882 /* start timeout, if any */
883 if (xfer->timeout != 0) {
884 usbd_transfer_timeout_ms(xfer, &uhci_timeout, xfer->timeout);
885 }
886 }
887
888 #define UHCI_APPEND_TD(std,last) (last) = _uhci_append_td(std,last)
889 static uhci_td_t *
_uhci_append_td(uhci_td_t * std,uhci_td_t * last)890 _uhci_append_td(uhci_td_t *std, uhci_td_t *last)
891 {
892 DPRINTFN(11, "%p to %p\n", std, last);
893
894 /* (sc->sc_bus.mtx) must be locked */
895
896 std->next = last->next;
897 std->td_next = last->td_next;
898
899 std->prev = last;
900
901 usb_pc_cpu_flush(std->page_cache);
902
903 /*
904 * the last->next->prev is never followed: std->next->prev = std;
905 */
906 last->next = std;
907 last->td_next = std->td_self;
908
909 usb_pc_cpu_flush(last->page_cache);
910
911 return (std);
912 }
913
914 #define UHCI_APPEND_QH(sqh,last) (last) = _uhci_append_qh(sqh,last)
915 static uhci_qh_t *
_uhci_append_qh(uhci_qh_t * sqh,uhci_qh_t * last)916 _uhci_append_qh(uhci_qh_t *sqh, uhci_qh_t *last)
917 {
918 DPRINTFN(11, "%p to %p\n", sqh, last);
919
920 if (sqh->h_prev != NULL) {
921 /* should not happen */
922 DPRINTFN(0, "QH already linked!\n");
923 return (last);
924 }
925 /* (sc->sc_bus.mtx) must be locked */
926
927 sqh->h_next = last->h_next;
928 sqh->qh_h_next = last->qh_h_next;
929
930 sqh->h_prev = last;
931
932 usb_pc_cpu_flush(sqh->page_cache);
933
934 /*
935 * The "last->h_next->h_prev" is never followed:
936 *
937 * "sqh->h_next->h_prev" = sqh;
938 */
939
940 last->h_next = sqh;
941 last->qh_h_next = sqh->qh_self;
942
943 usb_pc_cpu_flush(last->page_cache);
944
945 return (sqh);
946 }
947
948 /**/
949
950 #define UHCI_REMOVE_TD(std,last) (last) = _uhci_remove_td(std,last)
951 static uhci_td_t *
_uhci_remove_td(uhci_td_t * std,uhci_td_t * last)952 _uhci_remove_td(uhci_td_t *std, uhci_td_t *last)
953 {
954 DPRINTFN(11, "%p from %p\n", std, last);
955
956 /* (sc->sc_bus.mtx) must be locked */
957
958 std->prev->next = std->next;
959 std->prev->td_next = std->td_next;
960
961 usb_pc_cpu_flush(std->prev->page_cache);
962
963 if (std->next) {
964 std->next->prev = std->prev;
965 usb_pc_cpu_flush(std->next->page_cache);
966 }
967 return ((last == std) ? std->prev : last);
968 }
969
970 #define UHCI_REMOVE_QH(sqh,last) (last) = _uhci_remove_qh(sqh,last)
971 static uhci_qh_t *
_uhci_remove_qh(uhci_qh_t * sqh,uhci_qh_t * last)972 _uhci_remove_qh(uhci_qh_t *sqh, uhci_qh_t *last)
973 {
974 DPRINTFN(11, "%p from %p\n", sqh, last);
975
976 /* (sc->sc_bus.mtx) must be locked */
977
978 /* only remove if not removed from a queue */
979 if (sqh->h_prev) {
980 sqh->h_prev->h_next = sqh->h_next;
981 sqh->h_prev->qh_h_next = sqh->qh_h_next;
982
983 usb_pc_cpu_flush(sqh->h_prev->page_cache);
984
985 if (sqh->h_next) {
986 sqh->h_next->h_prev = sqh->h_prev;
987 usb_pc_cpu_flush(sqh->h_next->page_cache);
988 }
989 last = ((last == sqh) ? sqh->h_prev : last);
990
991 sqh->h_prev = 0;
992
993 usb_pc_cpu_flush(sqh->page_cache);
994 }
995 return (last);
996 }
997
998 static void
uhci_isoc_done(uhci_softc_t * sc,struct usb_xfer * xfer)999 uhci_isoc_done(uhci_softc_t *sc, struct usb_xfer *xfer)
1000 {
1001 struct usb_page_search res;
1002 uint32_t nframes = xfer->nframes;
1003 uint32_t status;
1004 uint32_t offset = 0;
1005 uint32_t *plen = xfer->frlengths;
1006 uint16_t len = 0;
1007 uhci_td_t *td = xfer->td_transfer_first;
1008 uhci_td_t **pp_last = &sc->sc_isoc_p_last[xfer->qh_pos];
1009
1010 DPRINTFN(13, "xfer=%p endpoint=%p transfer done\n",
1011 xfer, xfer->endpoint);
1012
1013 /* sync any DMA memory before doing fixups */
1014
1015 usb_bdma_post_sync(xfer);
1016
1017 while (nframes--) {
1018 if (td == NULL) {
1019 panic("%s:%d: out of TD's\n",
1020 __FUNCTION__, __LINE__);
1021 }
1022 if (pp_last >= &sc->sc_isoc_p_last[UHCI_VFRAMELIST_COUNT]) {
1023 pp_last = &sc->sc_isoc_p_last[0];
1024 }
1025 #ifdef USB_DEBUG
1026 if (uhcidebug > 5) {
1027 DPRINTF("isoc TD\n");
1028 uhci_dump_td(td);
1029 }
1030 #endif
1031 usb_pc_cpu_invalidate(td->page_cache);
1032 status = le32toh(td->td_status);
1033
1034 len = UHCI_TD_GET_ACTLEN(status);
1035
1036 if (len > *plen) {
1037 len = *plen;
1038 }
1039 if (td->fix_pc) {
1040 usbd_get_page(td->fix_pc, 0, &res);
1041
1042 /* copy data from fixup location to real location */
1043
1044 usb_pc_cpu_invalidate(td->fix_pc);
1045
1046 usbd_copy_in(xfer->frbuffers, offset,
1047 res.buffer, len);
1048 }
1049 offset += *plen;
1050
1051 *plen = len;
1052
1053 /* remove TD from schedule */
1054 UHCI_REMOVE_TD(td, *pp_last);
1055
1056 pp_last++;
1057 plen++;
1058 td = td->obj_next;
1059 }
1060
1061 xfer->aframes = xfer->nframes;
1062 }
1063
1064 static usb_error_t
uhci_non_isoc_done_sub(struct usb_xfer * xfer)1065 uhci_non_isoc_done_sub(struct usb_xfer *xfer)
1066 {
1067 struct usb_page_search res;
1068 uhci_td_t *td;
1069 uhci_td_t *td_alt_next;
1070 uint32_t status;
1071 uint32_t token;
1072 uint16_t len;
1073
1074 td = xfer->td_transfer_cache;
1075 td_alt_next = td->alt_next;
1076
1077 if (xfer->aframes != xfer->nframes) {
1078 usbd_xfer_set_frame_len(xfer, xfer->aframes, 0);
1079 }
1080 while (1) {
1081 usb_pc_cpu_invalidate(td->page_cache);
1082 status = le32toh(td->td_status);
1083 token = le32toh(td->td_token);
1084
1085 /*
1086 * Verify the status and add
1087 * up the actual length:
1088 */
1089
1090 len = UHCI_TD_GET_ACTLEN(status);
1091 if (len > td->len) {
1092 /* should not happen */
1093 DPRINTF("Invalid status length, "
1094 "0x%04x/0x%04x bytes\n", len, td->len);
1095 status |= UHCI_TD_STALLED;
1096
1097 } else if ((xfer->aframes != xfer->nframes) && (len > 0)) {
1098 if (td->fix_pc) {
1099 usbd_get_page(td->fix_pc, 0, &res);
1100
1101 /*
1102 * copy data from fixup location to real
1103 * location
1104 */
1105
1106 usb_pc_cpu_invalidate(td->fix_pc);
1107
1108 usbd_copy_in(xfer->frbuffers + xfer->aframes,
1109 xfer->frlengths[xfer->aframes], res.buffer, len);
1110 }
1111 /* update actual length */
1112
1113 xfer->frlengths[xfer->aframes] += len;
1114 }
1115 /* Check for last transfer */
1116 if (((void *)td) == xfer->td_transfer_last) {
1117 td = NULL;
1118 break;
1119 }
1120 if (status & UHCI_TD_STALLED) {
1121 /* the transfer is finished */
1122 td = NULL;
1123 break;
1124 }
1125 /* Check for short transfer */
1126 if (len != td->len) {
1127 if (xfer->flags_int.short_frames_ok) {
1128 /* follow alt next */
1129 td = td->alt_next;
1130 } else {
1131 /* the transfer is finished */
1132 td = NULL;
1133 }
1134 break;
1135 }
1136 td = td->obj_next;
1137
1138 if (td->alt_next != td_alt_next) {
1139 /* this USB frame is complete */
1140 break;
1141 }
1142 }
1143
1144 /* update transfer cache */
1145
1146 xfer->td_transfer_cache = td;
1147
1148 /* update data toggle */
1149
1150 xfer->endpoint->toggle_next = (token & UHCI_TD_SET_DT(1)) ? 0 : 1;
1151
1152 #ifdef USB_DEBUG
1153 if (status & UHCI_TD_ERROR) {
1154 DPRINTFN(11, "error, addr=%d, endpt=0x%02x, frame=0x%02x "
1155 "status=%s%s%s%s%s%s%s%s%s%s%s\n",
1156 xfer->address, xfer->endpointno, xfer->aframes,
1157 (status & UHCI_TD_BITSTUFF) ? "[BITSTUFF]" : "",
1158 (status & UHCI_TD_CRCTO) ? "[CRCTO]" : "",
1159 (status & UHCI_TD_NAK) ? "[NAK]" : "",
1160 (status & UHCI_TD_BABBLE) ? "[BABBLE]" : "",
1161 (status & UHCI_TD_DBUFFER) ? "[DBUFFER]" : "",
1162 (status & UHCI_TD_STALLED) ? "[STALLED]" : "",
1163 (status & UHCI_TD_ACTIVE) ? "[ACTIVE]" : "[NOT_ACTIVE]",
1164 (status & UHCI_TD_IOC) ? "[IOC]" : "",
1165 (status & UHCI_TD_IOS) ? "[IOS]" : "",
1166 (status & UHCI_TD_LS) ? "[LS]" : "",
1167 (status & UHCI_TD_SPD) ? "[SPD]" : "");
1168 }
1169 #endif
1170 if (status & UHCI_TD_STALLED) {
1171 /* try to separate I/O errors from STALL */
1172 if (UHCI_TD_GET_ERRCNT(status) == 0)
1173 return (USB_ERR_IOERROR);
1174 return (USB_ERR_STALLED);
1175 }
1176 return (USB_ERR_NORMAL_COMPLETION);
1177 }
1178
1179 static void
uhci_non_isoc_done(struct usb_xfer * xfer)1180 uhci_non_isoc_done(struct usb_xfer *xfer)
1181 {
1182 usb_error_t err = 0;
1183
1184 DPRINTFN(13, "xfer=%p endpoint=%p transfer done\n",
1185 xfer, xfer->endpoint);
1186
1187 #ifdef USB_DEBUG
1188 if (uhcidebug > 10) {
1189 uhci_dump_tds(xfer->td_transfer_first);
1190 }
1191 #endif
1192
1193 /* sync any DMA memory before doing fixups */
1194
1195 usb_bdma_post_sync(xfer);
1196
1197 /* reset scanner */
1198
1199 xfer->td_transfer_cache = xfer->td_transfer_first;
1200
1201 if (xfer->flags_int.control_xfr) {
1202 if (xfer->flags_int.control_hdr) {
1203 err = uhci_non_isoc_done_sub(xfer);
1204 }
1205 xfer->aframes = 1;
1206
1207 if (xfer->td_transfer_cache == NULL) {
1208 goto done;
1209 }
1210 }
1211 while (xfer->aframes != xfer->nframes) {
1212 err = uhci_non_isoc_done_sub(xfer);
1213 xfer->aframes++;
1214
1215 if (xfer->td_transfer_cache == NULL) {
1216 goto done;
1217 }
1218 }
1219
1220 if (xfer->flags_int.control_xfr &&
1221 !xfer->flags_int.control_act) {
1222 err = uhci_non_isoc_done_sub(xfer);
1223 }
1224 done:
1225 uhci_device_done(xfer, err);
1226 }
1227
1228 /*------------------------------------------------------------------------*
1229 * uhci_check_transfer_sub
1230 *
1231 * The main purpose of this function is to update the data-toggle
1232 * in case it is wrong.
1233 *------------------------------------------------------------------------*/
1234 static void
uhci_check_transfer_sub(struct usb_xfer * xfer)1235 uhci_check_transfer_sub(struct usb_xfer *xfer)
1236 {
1237 uhci_qh_t *qh;
1238 uhci_td_t *td;
1239 uhci_td_t *td_alt_next;
1240
1241 uint32_t td_token;
1242 uint32_t td_self;
1243
1244 td = xfer->td_transfer_cache;
1245 qh = xfer->qh_start[xfer->flags_int.curr_dma_set];
1246
1247 td_token = td->obj_next->td_token;
1248 td = td->alt_next;
1249 xfer->td_transfer_cache = td;
1250 td_self = td->td_self;
1251 td_alt_next = td->alt_next;
1252
1253 if (xfer->flags_int.control_xfr)
1254 goto skip; /* don't touch the DT value! */
1255
1256 if (!((td->td_token ^ td_token) & htole32(UHCI_TD_SET_DT(1))))
1257 goto skip; /* data toggle has correct value */
1258
1259 /*
1260 * The data toggle is wrong and we need to toggle it !
1261 */
1262 while (1) {
1263 td->td_token ^= htole32(UHCI_TD_SET_DT(1));
1264 usb_pc_cpu_flush(td->page_cache);
1265
1266 if (td == xfer->td_transfer_last) {
1267 /* last transfer */
1268 break;
1269 }
1270 td = td->obj_next;
1271
1272 if (td->alt_next != td_alt_next) {
1273 /* next frame */
1274 break;
1275 }
1276 }
1277 skip:
1278
1279 /* update the QH */
1280 qh->qh_e_next = td_self;
1281 usb_pc_cpu_flush(qh->page_cache);
1282
1283 DPRINTFN(13, "xfer=%p following alt next\n", xfer);
1284 }
1285
1286 /*------------------------------------------------------------------------*
1287 * uhci_check_transfer
1288 *
1289 * Return values:
1290 * 0: USB transfer is not finished
1291 * Else: USB transfer is finished
1292 *------------------------------------------------------------------------*/
1293 static uint8_t
uhci_check_transfer(struct usb_xfer * xfer)1294 uhci_check_transfer(struct usb_xfer *xfer)
1295 {
1296 uint32_t status;
1297 uint32_t token;
1298 uhci_td_t *td;
1299
1300 DPRINTFN(16, "xfer=%p checking transfer\n", xfer);
1301
1302 if (xfer->endpoint->methods == &uhci_device_isoc_methods) {
1303 /* isochronous transfer */
1304
1305 td = xfer->td_transfer_last;
1306
1307 usb_pc_cpu_invalidate(td->page_cache);
1308 status = le32toh(td->td_status);
1309
1310 /* check also if the first is complete */
1311
1312 td = xfer->td_transfer_first;
1313
1314 usb_pc_cpu_invalidate(td->page_cache);
1315 status |= le32toh(td->td_status);
1316
1317 if (!(status & UHCI_TD_ACTIVE)) {
1318 uhci_device_done(xfer, USB_ERR_NORMAL_COMPLETION);
1319 goto transferred;
1320 }
1321 } else {
1322 /* non-isochronous transfer */
1323
1324 /*
1325 * check whether there is an error somewhere
1326 * in the middle, or whether there was a short
1327 * packet (SPD and not ACTIVE)
1328 */
1329 td = xfer->td_transfer_cache;
1330
1331 while (1) {
1332 usb_pc_cpu_invalidate(td->page_cache);
1333 status = le32toh(td->td_status);
1334 token = le32toh(td->td_token);
1335
1336 /*
1337 * if there is an active TD the transfer isn't done
1338 */
1339 if (status & UHCI_TD_ACTIVE) {
1340 /* update cache */
1341 xfer->td_transfer_cache = td;
1342 goto done;
1343 }
1344 /*
1345 * last transfer descriptor makes the transfer done
1346 */
1347 if (((void *)td) == xfer->td_transfer_last) {
1348 break;
1349 }
1350 /*
1351 * any kind of error makes the transfer done
1352 */
1353 if (status & UHCI_TD_STALLED) {
1354 break;
1355 }
1356 /*
1357 * check if we reached the last packet
1358 * or if there is a short packet:
1359 */
1360 if ((td->td_next == htole32(UHCI_PTR_T)) ||
1361 (UHCI_TD_GET_ACTLEN(status) < td->len)) {
1362 if (xfer->flags_int.short_frames_ok) {
1363 /* follow alt next */
1364 if (td->alt_next) {
1365 /* update cache */
1366 xfer->td_transfer_cache = td;
1367 uhci_check_transfer_sub(xfer);
1368 goto done;
1369 }
1370 }
1371 /* transfer is done */
1372 break;
1373 }
1374 td = td->obj_next;
1375 }
1376 uhci_non_isoc_done(xfer);
1377 goto transferred;
1378 }
1379
1380 done:
1381 DPRINTFN(13, "xfer=%p is still active\n", xfer);
1382 return (0);
1383
1384 transferred:
1385 return (1);
1386 }
1387
1388 static void
uhci_interrupt_poll(uhci_softc_t * sc)1389 uhci_interrupt_poll(uhci_softc_t *sc)
1390 {
1391 struct usb_xfer *xfer;
1392
1393 repeat:
1394 TAILQ_FOREACH(xfer, &sc->sc_bus.intr_q.head, wait_entry) {
1395 /*
1396 * check if transfer is transferred
1397 */
1398 if (uhci_check_transfer(xfer)) {
1399 /* queue has been modified */
1400 goto repeat;
1401 }
1402 }
1403 }
1404
1405 /*------------------------------------------------------------------------*
1406 * uhci_interrupt - UHCI interrupt handler
1407 *
1408 * NOTE: Do not access "sc->sc_bus.bdev" inside the interrupt handler,
1409 * hence the interrupt handler will be setup before "sc->sc_bus.bdev"
1410 * is present !
1411 *------------------------------------------------------------------------*/
1412 void
uhci_interrupt(uhci_softc_t * sc)1413 uhci_interrupt(uhci_softc_t *sc)
1414 {
1415 uint32_t status;
1416
1417 USB_BUS_LOCK(&sc->sc_bus);
1418
1419 DPRINTFN(16, "real interrupt\n");
1420
1421 #ifdef USB_DEBUG
1422 if (uhcidebug > 15) {
1423 uhci_dumpregs(sc);
1424 }
1425 #endif
1426 status = UREAD2(sc, UHCI_STS) & UHCI_STS_ALLINTRS;
1427 if (status == 0) {
1428 /* the interrupt was not for us */
1429 goto done;
1430 }
1431 if (status & (UHCI_STS_RD | UHCI_STS_HSE |
1432 UHCI_STS_HCPE | UHCI_STS_HCH)) {
1433 if (status & UHCI_STS_RD) {
1434 #ifdef USB_DEBUG
1435 printf("%s: resume detect\n",
1436 __FUNCTION__);
1437 #endif
1438 }
1439 if (status & UHCI_STS_HSE) {
1440 printf("%s: host system error\n",
1441 __FUNCTION__);
1442 }
1443 if (status & UHCI_STS_HCPE) {
1444 printf("%s: host controller process error\n",
1445 __FUNCTION__);
1446 }
1447 if (status & UHCI_STS_HCH) {
1448 /* no acknowledge needed */
1449 DPRINTF("%s: host controller halted\n",
1450 __FUNCTION__);
1451 #ifdef USB_DEBUG
1452 if (uhcidebug > 0) {
1453 uhci_dump_all(sc);
1454 }
1455 #endif
1456 }
1457 }
1458 /* get acknowledge bits */
1459 status &= (UHCI_STS_USBINT |
1460 UHCI_STS_USBEI |
1461 UHCI_STS_RD |
1462 UHCI_STS_HSE |
1463 UHCI_STS_HCPE |
1464 UHCI_STS_HCH);
1465
1466 if (status == 0) {
1467 /* nothing to acknowledge */
1468 goto done;
1469 }
1470 /* acknowledge interrupts */
1471 UWRITE2(sc, UHCI_STS, status);
1472
1473 /* poll all the USB transfers */
1474 uhci_interrupt_poll(sc);
1475
1476 done:
1477 USB_BUS_UNLOCK(&sc->sc_bus);
1478 }
1479
1480 /*
1481 * called when a request does not complete
1482 */
1483 static void
uhci_timeout(void * arg)1484 uhci_timeout(void *arg)
1485 {
1486 struct usb_xfer *xfer = arg;
1487
1488 DPRINTF("xfer=%p\n", xfer);
1489
1490 USB_BUS_LOCK_ASSERT(xfer->xroot->bus, MA_OWNED);
1491
1492 /* transfer is transferred */
1493 uhci_device_done(xfer, USB_ERR_TIMEOUT);
1494 }
1495
1496 static void
uhci_do_poll(struct usb_bus * bus)1497 uhci_do_poll(struct usb_bus *bus)
1498 {
1499 struct uhci_softc *sc = UHCI_BUS2SC(bus);
1500
1501 USB_BUS_LOCK(&sc->sc_bus);
1502 uhci_interrupt_poll(sc);
1503 USB_BUS_UNLOCK(&sc->sc_bus);
1504 }
1505
1506 static void
uhci_setup_standard_chain_sub(struct uhci_std_temp * temp)1507 uhci_setup_standard_chain_sub(struct uhci_std_temp *temp)
1508 {
1509 uhci_td_t *td;
1510 uhci_td_t *td_next;
1511 uhci_td_t *td_alt_next;
1512 uint32_t average;
1513 uint32_t len_old;
1514 uint8_t shortpkt_old;
1515 uint8_t precompute;
1516
1517 td_alt_next = NULL;
1518 shortpkt_old = temp->shortpkt;
1519 len_old = temp->len;
1520 precompute = 1;
1521
1522 /* software is used to detect short incoming transfers */
1523
1524 if ((temp->td_token & htole32(UHCI_TD_PID)) == htole32(UHCI_TD_PID_IN)) {
1525 temp->td_status |= htole32(UHCI_TD_SPD);
1526 } else {
1527 temp->td_status &= ~htole32(UHCI_TD_SPD);
1528 }
1529
1530 temp->ml.buf_offset = 0;
1531
1532 restart:
1533
1534 temp->td_token &= ~htole32(UHCI_TD_SET_MAXLEN(0));
1535 temp->td_token |= htole32(UHCI_TD_SET_MAXLEN(temp->average));
1536
1537 td = temp->td;
1538 td_next = temp->td_next;
1539
1540 while (1) {
1541 if (temp->len == 0) {
1542 if (temp->shortpkt) {
1543 break;
1544 }
1545 /* send a Zero Length Packet, ZLP, last */
1546
1547 temp->shortpkt = 1;
1548 temp->td_token |= htole32(UHCI_TD_SET_MAXLEN(0));
1549 average = 0;
1550
1551 } else {
1552 average = temp->average;
1553
1554 if (temp->len < average) {
1555 temp->shortpkt = 1;
1556 temp->td_token &= ~htole32(UHCI_TD_SET_MAXLEN(0));
1557 temp->td_token |= htole32(UHCI_TD_SET_MAXLEN(temp->len));
1558 average = temp->len;
1559 }
1560 }
1561
1562 if (td_next == NULL) {
1563 panic("%s: out of UHCI transfer descriptors!", __FUNCTION__);
1564 }
1565 /* get next TD */
1566
1567 td = td_next;
1568 td_next = td->obj_next;
1569
1570 /* check if we are pre-computing */
1571
1572 if (precompute) {
1573 /* update remaining length */
1574
1575 temp->len -= average;
1576
1577 continue;
1578 }
1579 /* fill out current TD */
1580
1581 td->td_status = temp->td_status;
1582 td->td_token = temp->td_token;
1583
1584 /* update data toggle */
1585
1586 temp->td_token ^= htole32(UHCI_TD_SET_DT(1));
1587
1588 if (average == 0) {
1589 td->len = 0;
1590 td->td_buffer = 0;
1591 td->fix_pc = NULL;
1592
1593 } else {
1594 /* update remaining length */
1595
1596 temp->len -= average;
1597
1598 td->len = average;
1599
1600 /* fill out buffer pointer and do fixup, if any */
1601
1602 uhci_mem_layout_fixup(&temp->ml, td);
1603 }
1604
1605 td->alt_next = td_alt_next;
1606
1607 if ((td_next == td_alt_next) && temp->setup_alt_next) {
1608 /* we need to receive these frames one by one ! */
1609 td->td_status |= htole32(UHCI_TD_IOC);
1610 td->td_next = htole32(UHCI_PTR_T);
1611 } else {
1612 if (td_next) {
1613 /* link the current TD with the next one */
1614 td->td_next = td_next->td_self;
1615 }
1616 }
1617
1618 usb_pc_cpu_flush(td->page_cache);
1619 }
1620
1621 if (precompute) {
1622 precompute = 0;
1623
1624 /* setup alt next pointer, if any */
1625 if (temp->last_frame) {
1626 td_alt_next = NULL;
1627 } else {
1628 /* we use this field internally */
1629 td_alt_next = td_next;
1630 }
1631
1632 /* restore */
1633 temp->shortpkt = shortpkt_old;
1634 temp->len = len_old;
1635 goto restart;
1636 }
1637 temp->td = td;
1638 temp->td_next = td_next;
1639 }
1640
1641 static uhci_td_t *
uhci_setup_standard_chain(struct usb_xfer * xfer)1642 uhci_setup_standard_chain(struct usb_xfer *xfer)
1643 {
1644 struct uhci_std_temp temp;
1645 uhci_td_t *td;
1646 uint32_t x;
1647
1648 DPRINTFN(9, "addr=%d endpt=%d sumlen=%d speed=%d\n",
1649 xfer->address, UE_GET_ADDR(xfer->endpointno),
1650 xfer->sumlen, usbd_get_speed(xfer->xroot->udev));
1651
1652 temp.average = xfer->max_frame_size;
1653 temp.max_frame_size = xfer->max_frame_size;
1654
1655 /* toggle the DMA set we are using */
1656 xfer->flags_int.curr_dma_set ^= 1;
1657
1658 /* get next DMA set */
1659 td = xfer->td_start[xfer->flags_int.curr_dma_set];
1660 xfer->td_transfer_first = td;
1661 xfer->td_transfer_cache = td;
1662
1663 temp.td = NULL;
1664 temp.td_next = td;
1665 temp.last_frame = 0;
1666 temp.setup_alt_next = xfer->flags_int.short_frames_ok;
1667
1668 uhci_mem_layout_init(&temp.ml, xfer);
1669
1670 temp.td_status =
1671 htole32(UHCI_TD_ZERO_ACTLEN(UHCI_TD_SET_ERRCNT(3) |
1672 UHCI_TD_ACTIVE));
1673
1674 if (xfer->xroot->udev->speed == USB_SPEED_LOW) {
1675 temp.td_status |= htole32(UHCI_TD_LS);
1676 }
1677 temp.td_token =
1678 htole32(UHCI_TD_SET_ENDPT(xfer->endpointno) |
1679 UHCI_TD_SET_DEVADDR(xfer->address));
1680
1681 if (xfer->endpoint->toggle_next) {
1682 /* DATA1 is next */
1683 temp.td_token |= htole32(UHCI_TD_SET_DT(1));
1684 }
1685 /* check if we should prepend a setup message */
1686
1687 if (xfer->flags_int.control_xfr) {
1688 if (xfer->flags_int.control_hdr) {
1689 temp.td_token &= htole32(UHCI_TD_SET_DEVADDR(0x7F) |
1690 UHCI_TD_SET_ENDPT(0xF));
1691 temp.td_token |= htole32(UHCI_TD_PID_SETUP |
1692 UHCI_TD_SET_DT(0));
1693
1694 temp.len = xfer->frlengths[0];
1695 temp.ml.buf_pc = xfer->frbuffers + 0;
1696 temp.shortpkt = temp.len ? 1 : 0;
1697 /* check for last frame */
1698 if (xfer->nframes == 1) {
1699 /* no STATUS stage yet, SETUP is last */
1700 if (xfer->flags_int.control_act) {
1701 temp.last_frame = 1;
1702 temp.setup_alt_next = 0;
1703 }
1704 }
1705 uhci_setup_standard_chain_sub(&temp);
1706 }
1707 x = 1;
1708 } else {
1709 x = 0;
1710 }
1711
1712 while (x != xfer->nframes) {
1713 /* DATA0 / DATA1 message */
1714
1715 temp.len = xfer->frlengths[x];
1716 temp.ml.buf_pc = xfer->frbuffers + x;
1717
1718 x++;
1719
1720 if (x == xfer->nframes) {
1721 if (xfer->flags_int.control_xfr) {
1722 /* no STATUS stage yet, DATA is last */
1723 if (xfer->flags_int.control_act) {
1724 temp.last_frame = 1;
1725 temp.setup_alt_next = 0;
1726 }
1727 } else {
1728 temp.last_frame = 1;
1729 temp.setup_alt_next = 0;
1730 }
1731 }
1732 /*
1733 * Keep previous data toggle,
1734 * device address and endpoint number:
1735 */
1736
1737 temp.td_token &= htole32(UHCI_TD_SET_DEVADDR(0x7F) |
1738 UHCI_TD_SET_ENDPT(0xF) |
1739 UHCI_TD_SET_DT(1));
1740
1741 if (temp.len == 0) {
1742 /* make sure that we send an USB packet */
1743
1744 temp.shortpkt = 0;
1745
1746 } else {
1747 /* regular data transfer */
1748
1749 temp.shortpkt = (xfer->flags.force_short_xfer) ? 0 : 1;
1750 }
1751
1752 /* set endpoint direction */
1753
1754 temp.td_token |=
1755 (UE_GET_DIR(xfer->endpointno) == UE_DIR_IN) ?
1756 htole32(UHCI_TD_PID_IN) :
1757 htole32(UHCI_TD_PID_OUT);
1758
1759 uhci_setup_standard_chain_sub(&temp);
1760 }
1761
1762 /* check if we should append a status stage */
1763
1764 if (xfer->flags_int.control_xfr &&
1765 !xfer->flags_int.control_act) {
1766 /*
1767 * send a DATA1 message and reverse the current endpoint
1768 * direction
1769 */
1770
1771 temp.td_token &= htole32(UHCI_TD_SET_DEVADDR(0x7F) |
1772 UHCI_TD_SET_ENDPT(0xF) |
1773 UHCI_TD_SET_DT(1));
1774 temp.td_token |=
1775 (UE_GET_DIR(xfer->endpointno) == UE_DIR_OUT) ?
1776 htole32(UHCI_TD_PID_IN | UHCI_TD_SET_DT(1)) :
1777 htole32(UHCI_TD_PID_OUT | UHCI_TD_SET_DT(1));
1778
1779 temp.len = 0;
1780 temp.ml.buf_pc = NULL;
1781 temp.shortpkt = 0;
1782 temp.last_frame = 1;
1783 temp.setup_alt_next = 0;
1784
1785 uhci_setup_standard_chain_sub(&temp);
1786 }
1787 td = temp.td;
1788
1789 /* Ensure that last TD is terminating: */
1790 td->td_next = htole32(UHCI_PTR_T);
1791
1792 /* set interrupt bit */
1793
1794 td->td_status |= htole32(UHCI_TD_IOC);
1795
1796 usb_pc_cpu_flush(td->page_cache);
1797
1798 /* must have at least one frame! */
1799
1800 xfer->td_transfer_last = td;
1801
1802 #ifdef USB_DEBUG
1803 if (uhcidebug > 8) {
1804 DPRINTF("nexttog=%d; data before transfer:\n",
1805 xfer->endpoint->toggle_next);
1806 uhci_dump_tds(xfer->td_transfer_first);
1807 }
1808 #endif
1809 return (xfer->td_transfer_first);
1810 }
1811
1812 /* NOTE: "done" can be run two times in a row,
1813 * from close and from interrupt
1814 */
1815
1816 static void
uhci_device_done(struct usb_xfer * xfer,usb_error_t error)1817 uhci_device_done(struct usb_xfer *xfer, usb_error_t error)
1818 {
1819 const struct usb_pipe_methods *methods = xfer->endpoint->methods;
1820 uhci_softc_t *sc = UHCI_BUS2SC(xfer->xroot->bus);
1821 uhci_qh_t *qh;
1822
1823 USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED);
1824
1825 DPRINTFN(2, "xfer=%p, endpoint=%p, error=%d\n",
1826 xfer, xfer->endpoint, error);
1827
1828 qh = xfer->qh_start[xfer->flags_int.curr_dma_set];
1829 if (qh) {
1830 usb_pc_cpu_invalidate(qh->page_cache);
1831 }
1832 if (xfer->flags_int.bandwidth_reclaimed) {
1833 xfer->flags_int.bandwidth_reclaimed = 0;
1834 uhci_rem_loop(sc);
1835 }
1836 if (methods == &uhci_device_bulk_methods) {
1837 UHCI_REMOVE_QH(qh, sc->sc_bulk_p_last);
1838 }
1839 if (methods == &uhci_device_ctrl_methods) {
1840 if (xfer->xroot->udev->speed == USB_SPEED_LOW) {
1841 UHCI_REMOVE_QH(qh, sc->sc_ls_ctl_p_last);
1842 } else {
1843 UHCI_REMOVE_QH(qh, sc->sc_fs_ctl_p_last);
1844 }
1845 }
1846 if (methods == &uhci_device_intr_methods) {
1847 UHCI_REMOVE_QH(qh, sc->sc_intr_p_last[xfer->qh_pos]);
1848 }
1849 /*
1850 * Only finish isochronous transfers once
1851 * which will update "xfer->frlengths".
1852 */
1853 if (xfer->td_transfer_first &&
1854 xfer->td_transfer_last) {
1855 if (methods == &uhci_device_isoc_methods) {
1856 uhci_isoc_done(sc, xfer);
1857 }
1858 xfer->td_transfer_first = NULL;
1859 xfer->td_transfer_last = NULL;
1860 }
1861 /* dequeue transfer and start next transfer */
1862 usbd_transfer_done(xfer, error);
1863 }
1864
1865 /*------------------------------------------------------------------------*
1866 * uhci bulk support
1867 *------------------------------------------------------------------------*/
1868 static void
uhci_device_bulk_open(struct usb_xfer * xfer)1869 uhci_device_bulk_open(struct usb_xfer *xfer)
1870 {
1871 return;
1872 }
1873
1874 static void
uhci_device_bulk_close(struct usb_xfer * xfer)1875 uhci_device_bulk_close(struct usb_xfer *xfer)
1876 {
1877 uhci_device_done(xfer, USB_ERR_CANCELLED);
1878 }
1879
1880 static void
uhci_device_bulk_enter(struct usb_xfer * xfer)1881 uhci_device_bulk_enter(struct usb_xfer *xfer)
1882 {
1883 return;
1884 }
1885
1886 static void
uhci_device_bulk_start(struct usb_xfer * xfer)1887 uhci_device_bulk_start(struct usb_xfer *xfer)
1888 {
1889 uhci_softc_t *sc = UHCI_BUS2SC(xfer->xroot->bus);
1890 uhci_td_t *td;
1891 uhci_qh_t *qh;
1892
1893 /* setup TD's */
1894 td = uhci_setup_standard_chain(xfer);
1895
1896 /* setup QH */
1897 qh = xfer->qh_start[xfer->flags_int.curr_dma_set];
1898
1899 qh->e_next = td;
1900 qh->qh_e_next = td->td_self;
1901
1902 if (xfer->xroot->udev->flags.self_suspended == 0) {
1903 UHCI_APPEND_QH(qh, sc->sc_bulk_p_last);
1904 uhci_add_loop(sc);
1905 xfer->flags_int.bandwidth_reclaimed = 1;
1906 } else {
1907 usb_pc_cpu_flush(qh->page_cache);
1908 }
1909
1910 /* put transfer on interrupt queue */
1911 uhci_transfer_intr_enqueue(xfer);
1912 }
1913
1914 static const struct usb_pipe_methods uhci_device_bulk_methods =
1915 {
1916 .open = uhci_device_bulk_open,
1917 .close = uhci_device_bulk_close,
1918 .enter = uhci_device_bulk_enter,
1919 .start = uhci_device_bulk_start,
1920 };
1921
1922 /*------------------------------------------------------------------------*
1923 * uhci control support
1924 *------------------------------------------------------------------------*/
1925 static void
uhci_device_ctrl_open(struct usb_xfer * xfer)1926 uhci_device_ctrl_open(struct usb_xfer *xfer)
1927 {
1928 return;
1929 }
1930
1931 static void
uhci_device_ctrl_close(struct usb_xfer * xfer)1932 uhci_device_ctrl_close(struct usb_xfer *xfer)
1933 {
1934 uhci_device_done(xfer, USB_ERR_CANCELLED);
1935 }
1936
1937 static void
uhci_device_ctrl_enter(struct usb_xfer * xfer)1938 uhci_device_ctrl_enter(struct usb_xfer *xfer)
1939 {
1940 return;
1941 }
1942
1943 static void
uhci_device_ctrl_start(struct usb_xfer * xfer)1944 uhci_device_ctrl_start(struct usb_xfer *xfer)
1945 {
1946 uhci_softc_t *sc = UHCI_BUS2SC(xfer->xroot->bus);
1947 uhci_qh_t *qh;
1948 uhci_td_t *td;
1949
1950 /* setup TD's */
1951 td = uhci_setup_standard_chain(xfer);
1952
1953 /* setup QH */
1954 qh = xfer->qh_start[xfer->flags_int.curr_dma_set];
1955
1956 qh->e_next = td;
1957 qh->qh_e_next = td->td_self;
1958
1959 /*
1960 * NOTE: some devices choke on bandwidth- reclamation for control
1961 * transfers
1962 */
1963 if (xfer->xroot->udev->flags.self_suspended == 0) {
1964 if (xfer->xroot->udev->speed == USB_SPEED_LOW) {
1965 UHCI_APPEND_QH(qh, sc->sc_ls_ctl_p_last);
1966 } else {
1967 UHCI_APPEND_QH(qh, sc->sc_fs_ctl_p_last);
1968 }
1969 } else {
1970 usb_pc_cpu_flush(qh->page_cache);
1971 }
1972 /* put transfer on interrupt queue */
1973 uhci_transfer_intr_enqueue(xfer);
1974 }
1975
1976 static const struct usb_pipe_methods uhci_device_ctrl_methods =
1977 {
1978 .open = uhci_device_ctrl_open,
1979 .close = uhci_device_ctrl_close,
1980 .enter = uhci_device_ctrl_enter,
1981 .start = uhci_device_ctrl_start,
1982 };
1983
1984 /*------------------------------------------------------------------------*
1985 * uhci interrupt support
1986 *------------------------------------------------------------------------*/
1987 static void
uhci_device_intr_open(struct usb_xfer * xfer)1988 uhci_device_intr_open(struct usb_xfer *xfer)
1989 {
1990 uhci_softc_t *sc = UHCI_BUS2SC(xfer->xroot->bus);
1991 uint16_t best;
1992 uint16_t bit;
1993 uint16_t x;
1994
1995 best = 0;
1996 bit = UHCI_IFRAMELIST_COUNT / 2;
1997 while (bit) {
1998 if (xfer->interval >= bit) {
1999 x = bit;
2000 best = bit;
2001 while (x & bit) {
2002 if (sc->sc_intr_stat[x] <
2003 sc->sc_intr_stat[best]) {
2004 best = x;
2005 }
2006 x++;
2007 }
2008 break;
2009 }
2010 bit >>= 1;
2011 }
2012
2013 sc->sc_intr_stat[best]++;
2014 xfer->qh_pos = best;
2015
2016 DPRINTFN(3, "best=%d interval=%d\n",
2017 best, xfer->interval);
2018 }
2019
2020 static void
uhci_device_intr_close(struct usb_xfer * xfer)2021 uhci_device_intr_close(struct usb_xfer *xfer)
2022 {
2023 uhci_softc_t *sc = UHCI_BUS2SC(xfer->xroot->bus);
2024
2025 sc->sc_intr_stat[xfer->qh_pos]--;
2026
2027 uhci_device_done(xfer, USB_ERR_CANCELLED);
2028 }
2029
2030 static void
uhci_device_intr_enter(struct usb_xfer * xfer)2031 uhci_device_intr_enter(struct usb_xfer *xfer)
2032 {
2033 return;
2034 }
2035
2036 static void
uhci_device_intr_start(struct usb_xfer * xfer)2037 uhci_device_intr_start(struct usb_xfer *xfer)
2038 {
2039 uhci_softc_t *sc = UHCI_BUS2SC(xfer->xroot->bus);
2040 uhci_qh_t *qh;
2041 uhci_td_t *td;
2042
2043 /* setup TD's */
2044 td = uhci_setup_standard_chain(xfer);
2045
2046 /* setup QH */
2047 qh = xfer->qh_start[xfer->flags_int.curr_dma_set];
2048
2049 qh->e_next = td;
2050 qh->qh_e_next = td->td_self;
2051
2052 if (xfer->xroot->udev->flags.self_suspended == 0) {
2053 /* enter QHs into the controller data structures */
2054 UHCI_APPEND_QH(qh, sc->sc_intr_p_last[xfer->qh_pos]);
2055 } else {
2056 usb_pc_cpu_flush(qh->page_cache);
2057 }
2058
2059 /* put transfer on interrupt queue */
2060 uhci_transfer_intr_enqueue(xfer);
2061 }
2062
2063 static const struct usb_pipe_methods uhci_device_intr_methods =
2064 {
2065 .open = uhci_device_intr_open,
2066 .close = uhci_device_intr_close,
2067 .enter = uhci_device_intr_enter,
2068 .start = uhci_device_intr_start,
2069 };
2070
2071 /*------------------------------------------------------------------------*
2072 * uhci isochronous support
2073 *------------------------------------------------------------------------*/
2074 static void
uhci_device_isoc_open(struct usb_xfer * xfer)2075 uhci_device_isoc_open(struct usb_xfer *xfer)
2076 {
2077 uhci_td_t *td;
2078 uint32_t td_token;
2079 uint8_t ds;
2080
2081 td_token =
2082 (UE_GET_DIR(xfer->endpointno) == UE_DIR_IN) ?
2083 UHCI_TD_IN(0, xfer->endpointno, xfer->address, 0) :
2084 UHCI_TD_OUT(0, xfer->endpointno, xfer->address, 0);
2085
2086 td_token = htole32(td_token);
2087
2088 /* initialize all TD's */
2089
2090 for (ds = 0; ds != 2; ds++) {
2091 for (td = xfer->td_start[ds]; td; td = td->obj_next) {
2092 /* mark TD as inactive */
2093 td->td_status = htole32(UHCI_TD_IOS);
2094 td->td_token = td_token;
2095
2096 usb_pc_cpu_flush(td->page_cache);
2097 }
2098 }
2099 }
2100
2101 static void
uhci_device_isoc_close(struct usb_xfer * xfer)2102 uhci_device_isoc_close(struct usb_xfer *xfer)
2103 {
2104 uhci_device_done(xfer, USB_ERR_CANCELLED);
2105 }
2106
2107 static void
uhci_device_isoc_enter(struct usb_xfer * xfer)2108 uhci_device_isoc_enter(struct usb_xfer *xfer)
2109 {
2110 struct uhci_mem_layout ml;
2111 uhci_softc_t *sc = UHCI_BUS2SC(xfer->xroot->bus);
2112 uint32_t nframes;
2113 uint32_t startframe;
2114 uint32_t *plen;
2115
2116 #ifdef USB_DEBUG
2117 uint8_t once = 1;
2118
2119 #endif
2120 uhci_td_t *td;
2121 uhci_td_t *td_last = NULL;
2122 uhci_td_t **pp_last;
2123
2124 DPRINTFN(6, "xfer=%p next=%d nframes=%d\n",
2125 xfer, xfer->endpoint->isoc_next, xfer->nframes);
2126
2127 nframes = UREAD2(sc, UHCI_FRNUM);
2128
2129 if (usbd_xfer_get_isochronous_start_frame(
2130 xfer, nframes, 0, 1, UHCI_VFRAMELIST_COUNT - 1, &startframe))
2131 DPRINTFN(3, "start next=%d\n", startframe);
2132
2133 /* get the real number of frames */
2134
2135 nframes = xfer->nframes;
2136
2137 uhci_mem_layout_init(&ml, xfer);
2138
2139 plen = xfer->frlengths;
2140
2141 /* toggle the DMA set we are using */
2142 xfer->flags_int.curr_dma_set ^= 1;
2143
2144 /* get next DMA set */
2145 td = xfer->td_start[xfer->flags_int.curr_dma_set];
2146 xfer->td_transfer_first = td;
2147
2148 pp_last = &sc->sc_isoc_p_last[startframe];
2149
2150 /* store starting position */
2151
2152 xfer->qh_pos = startframe;
2153
2154 while (nframes--) {
2155 if (td == NULL) {
2156 panic("%s:%d: out of TD's\n",
2157 __FUNCTION__, __LINE__);
2158 }
2159 if (pp_last >= &sc->sc_isoc_p_last[UHCI_VFRAMELIST_COUNT]) {
2160 pp_last = &sc->sc_isoc_p_last[0];
2161 }
2162 if (*plen > xfer->max_frame_size) {
2163 #ifdef USB_DEBUG
2164 if (once) {
2165 once = 0;
2166 printf("%s: frame length(%d) exceeds %d "
2167 "bytes (frame truncated)\n",
2168 __FUNCTION__, *plen,
2169 xfer->max_frame_size);
2170 }
2171 #endif
2172 *plen = xfer->max_frame_size;
2173 }
2174 /* reuse td_token from last transfer */
2175
2176 td->td_token &= htole32(~UHCI_TD_MAXLEN_MASK);
2177 td->td_token |= htole32(UHCI_TD_SET_MAXLEN(*plen));
2178
2179 td->len = *plen;
2180
2181 if (td->len == 0) {
2182 /*
2183 * Do not call "uhci_mem_layout_fixup()" when the
2184 * length is zero!
2185 */
2186 td->td_buffer = 0;
2187 td->fix_pc = NULL;
2188
2189 } else {
2190 /* fill out buffer pointer and do fixup, if any */
2191
2192 uhci_mem_layout_fixup(&ml, td);
2193 }
2194
2195 /* update status */
2196 if (nframes == 0) {
2197 td->td_status = htole32
2198 (UHCI_TD_ZERO_ACTLEN
2199 (UHCI_TD_SET_ERRCNT(0) |
2200 UHCI_TD_ACTIVE |
2201 UHCI_TD_IOS |
2202 UHCI_TD_IOC));
2203 } else {
2204 td->td_status = htole32
2205 (UHCI_TD_ZERO_ACTLEN
2206 (UHCI_TD_SET_ERRCNT(0) |
2207 UHCI_TD_ACTIVE |
2208 UHCI_TD_IOS));
2209 }
2210
2211 usb_pc_cpu_flush(td->page_cache);
2212
2213 #ifdef USB_DEBUG
2214 if (uhcidebug > 5) {
2215 DPRINTF("TD %d\n", nframes);
2216 uhci_dump_td(td);
2217 }
2218 #endif
2219 /* insert TD into schedule */
2220 UHCI_APPEND_TD(td, *pp_last);
2221 pp_last++;
2222
2223 plen++;
2224 td_last = td;
2225 td = td->obj_next;
2226 }
2227
2228 xfer->td_transfer_last = td_last;
2229 }
2230
2231 static void
uhci_device_isoc_start(struct usb_xfer * xfer)2232 uhci_device_isoc_start(struct usb_xfer *xfer)
2233 {
2234 /* put transfer on interrupt queue */
2235 uhci_transfer_intr_enqueue(xfer);
2236 }
2237
2238 static const struct usb_pipe_methods uhci_device_isoc_methods =
2239 {
2240 .open = uhci_device_isoc_open,
2241 .close = uhci_device_isoc_close,
2242 .enter = uhci_device_isoc_enter,
2243 .start = uhci_device_isoc_start,
2244 };
2245
2246 /*------------------------------------------------------------------------*
2247 * uhci root control support
2248 *------------------------------------------------------------------------*
2249 * Simulate a hardware hub by handling all the necessary requests.
2250 *------------------------------------------------------------------------*/
2251
2252 static const
2253 struct usb_device_descriptor uhci_devd =
2254 {
2255 sizeof(struct usb_device_descriptor),
2256 UDESC_DEVICE, /* type */
2257 {0x00, 0x01}, /* USB version */
2258 UDCLASS_HUB, /* class */
2259 UDSUBCLASS_HUB, /* subclass */
2260 UDPROTO_FSHUB, /* protocol */
2261 64, /* max packet */
2262 {0}, {0}, {0x00, 0x01}, /* device id */
2263 1, 2, 0, /* string indexes */
2264 1 /* # of configurations */
2265 };
2266
2267 static const struct uhci_config_desc uhci_confd = {
2268 .confd = {
2269 .bLength = sizeof(struct usb_config_descriptor),
2270 .bDescriptorType = UDESC_CONFIG,
2271 .wTotalLength[0] = sizeof(uhci_confd),
2272 .bNumInterface = 1,
2273 .bConfigurationValue = 1,
2274 .iConfiguration = 0,
2275 .bmAttributes = UC_SELF_POWERED,
2276 .bMaxPower = 0 /* max power */
2277 },
2278 .ifcd = {
2279 .bLength = sizeof(struct usb_interface_descriptor),
2280 .bDescriptorType = UDESC_INTERFACE,
2281 .bNumEndpoints = 1,
2282 .bInterfaceClass = UICLASS_HUB,
2283 .bInterfaceSubClass = UISUBCLASS_HUB,
2284 .bInterfaceProtocol = UIPROTO_FSHUB,
2285 },
2286 .endpd = {
2287 .bLength = sizeof(struct usb_endpoint_descriptor),
2288 .bDescriptorType = UDESC_ENDPOINT,
2289 .bEndpointAddress = UE_DIR_IN | UHCI_INTR_ENDPT,
2290 .bmAttributes = UE_INTERRUPT,
2291 .wMaxPacketSize[0] = 8, /* max packet (63 ports) */
2292 .bInterval = 255,
2293 },
2294 };
2295
2296 static const
2297 struct usb_hub_descriptor_min uhci_hubd_piix =
2298 {
2299 .bDescLength = sizeof(uhci_hubd_piix),
2300 .bDescriptorType = UDESC_HUB,
2301 .bNbrPorts = 2,
2302 .wHubCharacteristics = {UHD_PWR_NO_SWITCH | UHD_OC_INDIVIDUAL, 0},
2303 .bPwrOn2PwrGood = 50,
2304 };
2305
2306 /*
2307 * The USB hub protocol requires that SET_FEATURE(PORT_RESET) also
2308 * enables the port, and also states that SET_FEATURE(PORT_ENABLE)
2309 * should not be used by the USB subsystem. As we cannot issue a
2310 * SET_FEATURE(PORT_ENABLE) externally, we must ensure that the port
2311 * will be enabled as part of the reset.
2312 *
2313 * On the VT83C572, the port cannot be successfully enabled until the
2314 * outstanding "port enable change" and "connection status change"
2315 * events have been reset.
2316 */
2317 static usb_error_t
uhci_portreset(uhci_softc_t * sc,uint16_t index)2318 uhci_portreset(uhci_softc_t *sc, uint16_t index)
2319 {
2320 uint16_t port;
2321 uint16_t x;
2322 uint8_t lim;
2323
2324 if (index == 1)
2325 port = UHCI_PORTSC1;
2326 else if (index == 2)
2327 port = UHCI_PORTSC2;
2328 else
2329 return (USB_ERR_IOERROR);
2330
2331 /*
2332 * Before we do anything, turn on SOF messages on the USB
2333 * BUS. Some USB devices do not cope without them!
2334 */
2335 uhci_restart(sc);
2336
2337 x = URWMASK(UREAD2(sc, port));
2338 UWRITE2(sc, port, x | UHCI_PORTSC_PR);
2339
2340 usb_pause_mtx(&sc->sc_bus.bus_mtx,
2341 USB_MS_TO_TICKS(usb_port_root_reset_delay));
2342
2343 DPRINTFN(4, "uhci port %d reset, status0 = 0x%04x\n",
2344 index, UREAD2(sc, port));
2345
2346 x = URWMASK(UREAD2(sc, port));
2347 UWRITE2(sc, port, x & ~UHCI_PORTSC_PR);
2348
2349 mtx_unlock(&sc->sc_bus.bus_mtx);
2350
2351 /*
2352 * This delay needs to be exactly 100us, else some USB devices
2353 * fail to attach!
2354 */
2355 DELAY(100);
2356
2357 mtx_lock(&sc->sc_bus.bus_mtx);
2358
2359 DPRINTFN(4, "uhci port %d reset, status1 = 0x%04x\n",
2360 index, UREAD2(sc, port));
2361
2362 x = URWMASK(UREAD2(sc, port));
2363 UWRITE2(sc, port, x | UHCI_PORTSC_PE);
2364
2365 for (lim = 0; lim < 12; lim++) {
2366 usb_pause_mtx(&sc->sc_bus.bus_mtx,
2367 USB_MS_TO_TICKS(usb_port_reset_delay));
2368
2369 x = UREAD2(sc, port);
2370
2371 DPRINTFN(4, "uhci port %d iteration %u, status = 0x%04x\n",
2372 index, lim, x);
2373
2374 if (!(x & UHCI_PORTSC_CCS)) {
2375 /*
2376 * No device is connected (or was disconnected
2377 * during reset). Consider the port reset.
2378 * The delay must be long enough to ensure on
2379 * the initial iteration that the device
2380 * connection will have been registered. 50ms
2381 * appears to be sufficient, but 20ms is not.
2382 */
2383 DPRINTFN(4, "uhci port %d loop %u, device detached\n",
2384 index, lim);
2385 goto done;
2386 }
2387 if (x & (UHCI_PORTSC_POEDC | UHCI_PORTSC_CSC)) {
2388 /*
2389 * Port enabled changed and/or connection
2390 * status changed were set. Reset either or
2391 * both raised flags (by writing a 1 to that
2392 * bit), and wait again for state to settle.
2393 */
2394 UWRITE2(sc, port, URWMASK(x) |
2395 (x & (UHCI_PORTSC_POEDC | UHCI_PORTSC_CSC)));
2396 continue;
2397 }
2398 if (x & UHCI_PORTSC_PE) {
2399 /* port is enabled */
2400 goto done;
2401 }
2402 UWRITE2(sc, port, URWMASK(x) | UHCI_PORTSC_PE);
2403 }
2404
2405 DPRINTFN(2, "uhci port %d reset timed out\n", index);
2406 return (USB_ERR_TIMEOUT);
2407
2408 done:
2409 DPRINTFN(4, "uhci port %d reset, status2 = 0x%04x\n",
2410 index, UREAD2(sc, port));
2411
2412 sc->sc_isreset = 1;
2413 return (USB_ERR_NORMAL_COMPLETION);
2414 }
2415
2416 static usb_error_t
uhci_roothub_exec(struct usb_device * udev,struct usb_device_request * req,const void ** pptr,uint16_t * plength)2417 uhci_roothub_exec(struct usb_device *udev,
2418 struct usb_device_request *req, const void **pptr, uint16_t *plength)
2419 {
2420 uhci_softc_t *sc = UHCI_BUS2SC(udev->bus);
2421 const void *ptr;
2422 const char *str_ptr;
2423 uint16_t x;
2424 uint16_t port;
2425 uint16_t value;
2426 uint16_t index;
2427 uint16_t status;
2428 uint16_t change;
2429 uint16_t len;
2430 usb_error_t err;
2431
2432 USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED);
2433
2434 /* buffer reset */
2435 ptr = (const void *)&sc->sc_hub_desc.temp;
2436 len = 0;
2437 err = 0;
2438
2439 value = UGETW(req->wValue);
2440 index = UGETW(req->wIndex);
2441
2442 DPRINTFN(3, "type=0x%02x request=0x%02x wLen=0x%04x "
2443 "wValue=0x%04x wIndex=0x%04x\n",
2444 req->bmRequestType, req->bRequest,
2445 UGETW(req->wLength), value, index);
2446
2447 #define C(x,y) ((x) | ((y) << 8))
2448 switch (C(req->bRequest, req->bmRequestType)) {
2449 case C(UR_CLEAR_FEATURE, UT_WRITE_DEVICE):
2450 case C(UR_CLEAR_FEATURE, UT_WRITE_INTERFACE):
2451 case C(UR_CLEAR_FEATURE, UT_WRITE_ENDPOINT):
2452 /*
2453 * DEVICE_REMOTE_WAKEUP and ENDPOINT_HALT are no-ops
2454 * for the integrated root hub.
2455 */
2456 break;
2457 case C(UR_GET_CONFIG, UT_READ_DEVICE):
2458 len = 1;
2459 sc->sc_hub_desc.temp[0] = sc->sc_conf;
2460 break;
2461 case C(UR_GET_DESCRIPTOR, UT_READ_DEVICE):
2462 switch (value >> 8) {
2463 case UDESC_DEVICE:
2464 if ((value & 0xff) != 0) {
2465 err = USB_ERR_IOERROR;
2466 goto done;
2467 }
2468 len = sizeof(uhci_devd);
2469 ptr = (const void *)&uhci_devd;
2470 break;
2471
2472 case UDESC_CONFIG:
2473 if ((value & 0xff) != 0) {
2474 err = USB_ERR_IOERROR;
2475 goto done;
2476 }
2477 len = sizeof(uhci_confd);
2478 ptr = (const void *)&uhci_confd;
2479 break;
2480
2481 case UDESC_STRING:
2482 switch (value & 0xff) {
2483 case 0: /* Language table */
2484 str_ptr = "\001";
2485 break;
2486
2487 case 1: /* Vendor */
2488 str_ptr = sc->sc_vendor;
2489 break;
2490
2491 case 2: /* Product */
2492 str_ptr = "UHCI root HUB";
2493 break;
2494
2495 default:
2496 str_ptr = "";
2497 break;
2498 }
2499
2500 len = usb_make_str_desc
2501 (sc->sc_hub_desc.temp,
2502 sizeof(sc->sc_hub_desc.temp),
2503 str_ptr);
2504 break;
2505
2506 default:
2507 err = USB_ERR_IOERROR;
2508 goto done;
2509 }
2510 break;
2511 case C(UR_GET_INTERFACE, UT_READ_INTERFACE):
2512 len = 1;
2513 sc->sc_hub_desc.temp[0] = 0;
2514 break;
2515 case C(UR_GET_STATUS, UT_READ_DEVICE):
2516 len = 2;
2517 USETW(sc->sc_hub_desc.stat.wStatus, UDS_SELF_POWERED);
2518 break;
2519 case C(UR_GET_STATUS, UT_READ_INTERFACE):
2520 case C(UR_GET_STATUS, UT_READ_ENDPOINT):
2521 len = 2;
2522 USETW(sc->sc_hub_desc.stat.wStatus, 0);
2523 break;
2524 case C(UR_SET_ADDRESS, UT_WRITE_DEVICE):
2525 if (value >= UHCI_MAX_DEVICES) {
2526 err = USB_ERR_IOERROR;
2527 goto done;
2528 }
2529 sc->sc_addr = value;
2530 break;
2531 case C(UR_SET_CONFIG, UT_WRITE_DEVICE):
2532 if ((value != 0) && (value != 1)) {
2533 err = USB_ERR_IOERROR;
2534 goto done;
2535 }
2536 sc->sc_conf = value;
2537 break;
2538 case C(UR_SET_DESCRIPTOR, UT_WRITE_DEVICE):
2539 break;
2540 case C(UR_SET_FEATURE, UT_WRITE_DEVICE):
2541 case C(UR_SET_FEATURE, UT_WRITE_INTERFACE):
2542 case C(UR_SET_FEATURE, UT_WRITE_ENDPOINT):
2543 err = USB_ERR_IOERROR;
2544 goto done;
2545 case C(UR_SET_INTERFACE, UT_WRITE_INTERFACE):
2546 break;
2547 case C(UR_SYNCH_FRAME, UT_WRITE_ENDPOINT):
2548 break;
2549 /* Hub requests */
2550 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_DEVICE):
2551 break;
2552 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_OTHER):
2553 DPRINTFN(4, "UR_CLEAR_PORT_FEATURE "
2554 "port=%d feature=%d\n",
2555 index, value);
2556 if (index == 1)
2557 port = UHCI_PORTSC1;
2558 else if (index == 2)
2559 port = UHCI_PORTSC2;
2560 else {
2561 err = USB_ERR_IOERROR;
2562 goto done;
2563 }
2564 switch (value) {
2565 case UHF_PORT_ENABLE:
2566 x = URWMASK(UREAD2(sc, port));
2567 UWRITE2(sc, port, x & ~UHCI_PORTSC_PE);
2568 break;
2569 case UHF_PORT_SUSPEND:
2570 x = URWMASK(UREAD2(sc, port));
2571 UWRITE2(sc, port, x & ~(UHCI_PORTSC_SUSP));
2572 break;
2573 case UHF_PORT_RESET:
2574 x = URWMASK(UREAD2(sc, port));
2575 UWRITE2(sc, port, x & ~UHCI_PORTSC_PR);
2576 break;
2577 case UHF_C_PORT_CONNECTION:
2578 x = URWMASK(UREAD2(sc, port));
2579 UWRITE2(sc, port, x | UHCI_PORTSC_CSC);
2580 break;
2581 case UHF_C_PORT_ENABLE:
2582 x = URWMASK(UREAD2(sc, port));
2583 UWRITE2(sc, port, x | UHCI_PORTSC_POEDC);
2584 break;
2585 case UHF_C_PORT_OVER_CURRENT:
2586 x = URWMASK(UREAD2(sc, port));
2587 UWRITE2(sc, port, x | UHCI_PORTSC_OCIC);
2588 break;
2589 case UHF_C_PORT_RESET:
2590 sc->sc_isreset = 0;
2591 err = USB_ERR_NORMAL_COMPLETION;
2592 goto done;
2593 case UHF_C_PORT_SUSPEND:
2594 sc->sc_isresumed &= ~(1 << index);
2595 break;
2596 case UHF_PORT_CONNECTION:
2597 case UHF_PORT_OVER_CURRENT:
2598 case UHF_PORT_POWER:
2599 case UHF_PORT_LOW_SPEED:
2600 default:
2601 err = USB_ERR_IOERROR;
2602 goto done;
2603 }
2604 break;
2605 case C(UR_GET_BUS_STATE, UT_READ_CLASS_OTHER):
2606 if (index == 1)
2607 port = UHCI_PORTSC1;
2608 else if (index == 2)
2609 port = UHCI_PORTSC2;
2610 else {
2611 err = USB_ERR_IOERROR;
2612 goto done;
2613 }
2614 len = 1;
2615 sc->sc_hub_desc.temp[0] =
2616 ((UREAD2(sc, port) & UHCI_PORTSC_LS) >>
2617 UHCI_PORTSC_LS_SHIFT);
2618 break;
2619 case C(UR_GET_DESCRIPTOR, UT_READ_CLASS_DEVICE):
2620 if ((value & 0xff) != 0) {
2621 err = USB_ERR_IOERROR;
2622 goto done;
2623 }
2624 len = sizeof(uhci_hubd_piix);
2625 ptr = (const void *)&uhci_hubd_piix;
2626 break;
2627 case C(UR_GET_STATUS, UT_READ_CLASS_DEVICE):
2628 len = 16;
2629 memset(sc->sc_hub_desc.temp, 0, 16);
2630 break;
2631 case C(UR_GET_STATUS, UT_READ_CLASS_OTHER):
2632 if (index == 1)
2633 port = UHCI_PORTSC1;
2634 else if (index == 2)
2635 port = UHCI_PORTSC2;
2636 else {
2637 err = USB_ERR_IOERROR;
2638 goto done;
2639 }
2640 x = UREAD2(sc, port);
2641 status = change = 0;
2642 if (x & UHCI_PORTSC_CCS)
2643 status |= UPS_CURRENT_CONNECT_STATUS;
2644 if (x & UHCI_PORTSC_CSC)
2645 change |= UPS_C_CONNECT_STATUS;
2646 if (x & UHCI_PORTSC_PE)
2647 status |= UPS_PORT_ENABLED;
2648 if (x & UHCI_PORTSC_POEDC)
2649 change |= UPS_C_PORT_ENABLED;
2650 if (x & UHCI_PORTSC_OCI)
2651 status |= UPS_OVERCURRENT_INDICATOR;
2652 if (x & UHCI_PORTSC_OCIC)
2653 change |= UPS_C_OVERCURRENT_INDICATOR;
2654 if (x & UHCI_PORTSC_LSDA)
2655 status |= UPS_LOW_SPEED;
2656 if ((x & UHCI_PORTSC_PE) && (x & UHCI_PORTSC_RD)) {
2657 /* need to do a write back */
2658 UWRITE2(sc, port, URWMASK(x));
2659
2660 /* wait 20ms for resume sequence to complete */
2661 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 50);
2662
2663 /* clear suspend and resume detect */
2664 UWRITE2(sc, port, URWMASK(x) & ~(UHCI_PORTSC_RD |
2665 UHCI_PORTSC_SUSP));
2666
2667 /* wait a little bit */
2668 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 500);
2669
2670 sc->sc_isresumed |= (1 << index);
2671
2672 } else if (x & UHCI_PORTSC_SUSP) {
2673 status |= UPS_SUSPEND;
2674 }
2675 status |= UPS_PORT_POWER;
2676 if (sc->sc_isresumed & (1 << index))
2677 change |= UPS_C_SUSPEND;
2678 if (sc->sc_isreset)
2679 change |= UPS_C_PORT_RESET;
2680 USETW(sc->sc_hub_desc.ps.wPortStatus, status);
2681 USETW(sc->sc_hub_desc.ps.wPortChange, change);
2682 len = sizeof(sc->sc_hub_desc.ps);
2683 break;
2684 case C(UR_SET_DESCRIPTOR, UT_WRITE_CLASS_DEVICE):
2685 err = USB_ERR_IOERROR;
2686 goto done;
2687 case C(UR_SET_FEATURE, UT_WRITE_CLASS_DEVICE):
2688 break;
2689 case C(UR_SET_FEATURE, UT_WRITE_CLASS_OTHER):
2690 if (index == 1)
2691 port = UHCI_PORTSC1;
2692 else if (index == 2)
2693 port = UHCI_PORTSC2;
2694 else {
2695 err = USB_ERR_IOERROR;
2696 goto done;
2697 }
2698 switch (value) {
2699 case UHF_PORT_ENABLE:
2700 x = URWMASK(UREAD2(sc, port));
2701 UWRITE2(sc, port, x | UHCI_PORTSC_PE);
2702 break;
2703 case UHF_PORT_SUSPEND:
2704 x = URWMASK(UREAD2(sc, port));
2705 UWRITE2(sc, port, x | UHCI_PORTSC_SUSP);
2706 break;
2707 case UHF_PORT_RESET:
2708 err = uhci_portreset(sc, index);
2709 goto done;
2710 case UHF_PORT_POWER:
2711 /* pretend we turned on power */
2712 err = USB_ERR_NORMAL_COMPLETION;
2713 goto done;
2714 case UHF_C_PORT_CONNECTION:
2715 case UHF_C_PORT_ENABLE:
2716 case UHF_C_PORT_OVER_CURRENT:
2717 case UHF_PORT_CONNECTION:
2718 case UHF_PORT_OVER_CURRENT:
2719 case UHF_PORT_LOW_SPEED:
2720 case UHF_C_PORT_SUSPEND:
2721 case UHF_C_PORT_RESET:
2722 default:
2723 err = USB_ERR_IOERROR;
2724 goto done;
2725 }
2726 break;
2727 default:
2728 err = USB_ERR_IOERROR;
2729 goto done;
2730 }
2731 done:
2732 *plength = len;
2733 *pptr = ptr;
2734 return (err);
2735 }
2736
2737 /*
2738 * This routine is executed periodically and simulates interrupts from
2739 * the root controller interrupt pipe for port status change:
2740 */
2741 static void
uhci_root_intr(uhci_softc_t * sc)2742 uhci_root_intr(uhci_softc_t *sc)
2743 {
2744 DPRINTFN(21, "\n");
2745
2746 USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED);
2747
2748 sc->sc_hub_idata[0] = 0;
2749
2750 if (UREAD2(sc, UHCI_PORTSC1) & (UHCI_PORTSC_CSC |
2751 UHCI_PORTSC_OCIC | UHCI_PORTSC_RD)) {
2752 sc->sc_hub_idata[0] |= 1 << 1;
2753 }
2754 if (UREAD2(sc, UHCI_PORTSC2) & (UHCI_PORTSC_CSC |
2755 UHCI_PORTSC_OCIC | UHCI_PORTSC_RD)) {
2756 sc->sc_hub_idata[0] |= 1 << 2;
2757 }
2758
2759 /* restart timer */
2760 usb_callout_reset(&sc->sc_root_intr, hz,
2761 (void *)&uhci_root_intr, sc);
2762
2763 if (sc->sc_hub_idata[0] != 0) {
2764 uhub_root_intr(&sc->sc_bus, sc->sc_hub_idata,
2765 sizeof(sc->sc_hub_idata));
2766 }
2767 }
2768
2769 static void
uhci_xfer_setup(struct usb_setup_params * parm)2770 uhci_xfer_setup(struct usb_setup_params *parm)
2771 {
2772 struct usb_page_search page_info;
2773 struct usb_page_cache *pc;
2774 struct usb_xfer *xfer;
2775 void *last_obj;
2776 uint32_t ntd;
2777 uint32_t nqh;
2778 uint32_t nfixup;
2779 uint32_t n;
2780 uint16_t align;
2781
2782 xfer = parm->curr_xfer;
2783
2784 parm->hc_max_packet_size = 0x500;
2785 parm->hc_max_packet_count = 1;
2786 parm->hc_max_frame_size = 0x500;
2787
2788 /*
2789 * compute ntd and nqh
2790 */
2791 if (parm->methods == &uhci_device_ctrl_methods) {
2792 xfer->flags_int.bdma_enable = 1;
2793 xfer->flags_int.bdma_no_post_sync = 1;
2794
2795 usbd_transfer_setup_sub(parm);
2796
2797 /* see EHCI HC driver for proof of "ntd" formula */
2798
2799 nqh = 1;
2800 ntd = ((2 * xfer->nframes) + 1 /* STATUS */
2801 + (xfer->max_data_length / xfer->max_frame_size));
2802
2803 } else if (parm->methods == &uhci_device_bulk_methods) {
2804 xfer->flags_int.bdma_enable = 1;
2805 xfer->flags_int.bdma_no_post_sync = 1;
2806
2807 usbd_transfer_setup_sub(parm);
2808
2809 nqh = 1;
2810 ntd = ((2 * xfer->nframes)
2811 + (xfer->max_data_length / xfer->max_frame_size));
2812
2813 } else if (parm->methods == &uhci_device_intr_methods) {
2814 xfer->flags_int.bdma_enable = 1;
2815 xfer->flags_int.bdma_no_post_sync = 1;
2816
2817 usbd_transfer_setup_sub(parm);
2818
2819 nqh = 1;
2820 ntd = ((2 * xfer->nframes)
2821 + (xfer->max_data_length / xfer->max_frame_size));
2822
2823 } else if (parm->methods == &uhci_device_isoc_methods) {
2824 xfer->flags_int.bdma_enable = 1;
2825 xfer->flags_int.bdma_no_post_sync = 1;
2826
2827 usbd_transfer_setup_sub(parm);
2828
2829 nqh = 0;
2830 ntd = xfer->nframes;
2831
2832 } else {
2833 usbd_transfer_setup_sub(parm);
2834
2835 nqh = 0;
2836 ntd = 0;
2837 }
2838
2839 if (parm->err) {
2840 return;
2841 }
2842 /*
2843 * NOTE: the UHCI controller requires that
2844 * every packet must be contiguous on
2845 * the same USB memory page !
2846 */
2847 nfixup = (parm->bufsize / USB_PAGE_SIZE) + 1;
2848
2849 /*
2850 * Compute a suitable power of two alignment
2851 * for our "max_frame_size" fixup buffer(s):
2852 */
2853 align = xfer->max_frame_size;
2854 n = 0;
2855 while (align) {
2856 align >>= 1;
2857 n++;
2858 }
2859
2860 /* check for power of two */
2861 if (!(xfer->max_frame_size &
2862 (xfer->max_frame_size - 1))) {
2863 n--;
2864 }
2865 /*
2866 * We don't allow alignments of
2867 * less than 8 bytes:
2868 *
2869 * NOTE: Allocating using an alignment
2870 * of 1 byte has special meaning!
2871 */
2872 if (n < 3) {
2873 n = 3;
2874 }
2875 align = (1 << n);
2876
2877 if (usbd_transfer_setup_sub_malloc(
2878 parm, &pc, xfer->max_frame_size,
2879 align, nfixup)) {
2880 parm->err = USB_ERR_NOMEM;
2881 return;
2882 }
2883 xfer->buf_fixup = pc;
2884
2885 alloc_dma_set:
2886
2887 if (parm->err) {
2888 return;
2889 }
2890 last_obj = NULL;
2891
2892 if (usbd_transfer_setup_sub_malloc(
2893 parm, &pc, sizeof(uhci_td_t),
2894 UHCI_TD_ALIGN, ntd)) {
2895 parm->err = USB_ERR_NOMEM;
2896 return;
2897 }
2898 if (parm->buf) {
2899 for (n = 0; n != ntd; n++) {
2900 uhci_td_t *td;
2901
2902 usbd_get_page(pc + n, 0, &page_info);
2903
2904 td = page_info.buffer;
2905
2906 /* init TD */
2907 if ((parm->methods == &uhci_device_bulk_methods) ||
2908 (parm->methods == &uhci_device_ctrl_methods) ||
2909 (parm->methods == &uhci_device_intr_methods)) {
2910 /* set depth first bit */
2911 td->td_self = htole32(page_info.physaddr |
2912 UHCI_PTR_TD | UHCI_PTR_VF);
2913 } else {
2914 td->td_self = htole32(page_info.physaddr |
2915 UHCI_PTR_TD);
2916 }
2917
2918 td->obj_next = last_obj;
2919 td->page_cache = pc + n;
2920
2921 last_obj = td;
2922
2923 usb_pc_cpu_flush(pc + n);
2924 }
2925 }
2926 xfer->td_start[xfer->flags_int.curr_dma_set] = last_obj;
2927
2928 last_obj = NULL;
2929
2930 if (usbd_transfer_setup_sub_malloc(
2931 parm, &pc, sizeof(uhci_qh_t),
2932 UHCI_QH_ALIGN, nqh)) {
2933 parm->err = USB_ERR_NOMEM;
2934 return;
2935 }
2936 if (parm->buf) {
2937 for (n = 0; n != nqh; n++) {
2938 uhci_qh_t *qh;
2939
2940 usbd_get_page(pc + n, 0, &page_info);
2941
2942 qh = page_info.buffer;
2943
2944 /* init QH */
2945 qh->qh_self = htole32(page_info.physaddr | UHCI_PTR_QH);
2946 qh->obj_next = last_obj;
2947 qh->page_cache = pc + n;
2948
2949 last_obj = qh;
2950
2951 usb_pc_cpu_flush(pc + n);
2952 }
2953 }
2954 xfer->qh_start[xfer->flags_int.curr_dma_set] = last_obj;
2955
2956 if (!xfer->flags_int.curr_dma_set) {
2957 xfer->flags_int.curr_dma_set = 1;
2958 goto alloc_dma_set;
2959 }
2960 }
2961
2962 static void
uhci_ep_init(struct usb_device * udev,struct usb_endpoint_descriptor * edesc,struct usb_endpoint * ep)2963 uhci_ep_init(struct usb_device *udev, struct usb_endpoint_descriptor *edesc,
2964 struct usb_endpoint *ep)
2965 {
2966 uhci_softc_t *sc = UHCI_BUS2SC(udev->bus);
2967
2968 DPRINTFN(2, "endpoint=%p, addr=%d, endpt=%d, mode=%d (%d)\n",
2969 ep, udev->address,
2970 edesc->bEndpointAddress, udev->flags.usb_mode,
2971 sc->sc_addr);
2972
2973 if (udev->device_index != sc->sc_addr) {
2974 switch (edesc->bmAttributes & UE_XFERTYPE) {
2975 case UE_CONTROL:
2976 ep->methods = &uhci_device_ctrl_methods;
2977 break;
2978 case UE_INTERRUPT:
2979 ep->methods = &uhci_device_intr_methods;
2980 break;
2981 case UE_ISOCHRONOUS:
2982 if (udev->speed == USB_SPEED_FULL) {
2983 ep->methods = &uhci_device_isoc_methods;
2984 }
2985 break;
2986 case UE_BULK:
2987 ep->methods = &uhci_device_bulk_methods;
2988 break;
2989 default:
2990 /* do nothing */
2991 break;
2992 }
2993 }
2994 }
2995
2996 static void
uhci_xfer_unsetup(struct usb_xfer * xfer)2997 uhci_xfer_unsetup(struct usb_xfer *xfer)
2998 {
2999 return;
3000 }
3001
3002 static void
uhci_get_dma_delay(struct usb_device * udev,uint32_t * pus)3003 uhci_get_dma_delay(struct usb_device *udev, uint32_t *pus)
3004 {
3005 /*
3006 * Wait until hardware has finished any possible use of the
3007 * transfer descriptor(s) and QH
3008 */
3009 *pus = (1125); /* microseconds */
3010 }
3011
3012 static void
uhci_device_resume(struct usb_device * udev)3013 uhci_device_resume(struct usb_device *udev)
3014 {
3015 struct uhci_softc *sc = UHCI_BUS2SC(udev->bus);
3016 struct usb_xfer *xfer;
3017 const struct usb_pipe_methods *methods;
3018 uhci_qh_t *qh;
3019
3020 DPRINTF("\n");
3021
3022 USB_BUS_LOCK(udev->bus);
3023
3024 TAILQ_FOREACH(xfer, &sc->sc_bus.intr_q.head, wait_entry) {
3025 if (xfer->xroot->udev == udev) {
3026 methods = xfer->endpoint->methods;
3027 qh = xfer->qh_start[xfer->flags_int.curr_dma_set];
3028
3029 if (methods == &uhci_device_bulk_methods) {
3030 UHCI_APPEND_QH(qh, sc->sc_bulk_p_last);
3031 uhci_add_loop(sc);
3032 xfer->flags_int.bandwidth_reclaimed = 1;
3033 }
3034 if (methods == &uhci_device_ctrl_methods) {
3035 if (xfer->xroot->udev->speed == USB_SPEED_LOW) {
3036 UHCI_APPEND_QH(qh, sc->sc_ls_ctl_p_last);
3037 } else {
3038 UHCI_APPEND_QH(qh, sc->sc_fs_ctl_p_last);
3039 }
3040 }
3041 if (methods == &uhci_device_intr_methods) {
3042 UHCI_APPEND_QH(qh, sc->sc_intr_p_last[xfer->qh_pos]);
3043 }
3044 }
3045 }
3046
3047 USB_BUS_UNLOCK(udev->bus);
3048
3049 return;
3050 }
3051
3052 static void
uhci_device_suspend(struct usb_device * udev)3053 uhci_device_suspend(struct usb_device *udev)
3054 {
3055 struct uhci_softc *sc = UHCI_BUS2SC(udev->bus);
3056 struct usb_xfer *xfer;
3057 const struct usb_pipe_methods *methods;
3058 uhci_qh_t *qh;
3059
3060 DPRINTF("\n");
3061
3062 USB_BUS_LOCK(udev->bus);
3063
3064 TAILQ_FOREACH(xfer, &sc->sc_bus.intr_q.head, wait_entry) {
3065 if (xfer->xroot->udev == udev) {
3066 methods = xfer->endpoint->methods;
3067 qh = xfer->qh_start[xfer->flags_int.curr_dma_set];
3068
3069 if (xfer->flags_int.bandwidth_reclaimed) {
3070 xfer->flags_int.bandwidth_reclaimed = 0;
3071 uhci_rem_loop(sc);
3072 }
3073 if (methods == &uhci_device_bulk_methods) {
3074 UHCI_REMOVE_QH(qh, sc->sc_bulk_p_last);
3075 }
3076 if (methods == &uhci_device_ctrl_methods) {
3077 if (xfer->xroot->udev->speed == USB_SPEED_LOW) {
3078 UHCI_REMOVE_QH(qh, sc->sc_ls_ctl_p_last);
3079 } else {
3080 UHCI_REMOVE_QH(qh, sc->sc_fs_ctl_p_last);
3081 }
3082 }
3083 if (methods == &uhci_device_intr_methods) {
3084 UHCI_REMOVE_QH(qh, sc->sc_intr_p_last[xfer->qh_pos]);
3085 }
3086 }
3087 }
3088
3089 USB_BUS_UNLOCK(udev->bus);
3090
3091 return;
3092 }
3093
3094 static void
uhci_set_hw_power_sleep(struct usb_bus * bus,uint32_t state)3095 uhci_set_hw_power_sleep(struct usb_bus *bus, uint32_t state)
3096 {
3097 struct uhci_softc *sc = UHCI_BUS2SC(bus);
3098
3099 switch (state) {
3100 case USB_HW_POWER_SUSPEND:
3101 case USB_HW_POWER_SHUTDOWN:
3102 uhci_suspend(sc);
3103 break;
3104 case USB_HW_POWER_RESUME:
3105 uhci_resume(sc);
3106 break;
3107 default:
3108 break;
3109 }
3110 }
3111
3112 static void
uhci_set_hw_power(struct usb_bus * bus)3113 uhci_set_hw_power(struct usb_bus *bus)
3114 {
3115 struct uhci_softc *sc = UHCI_BUS2SC(bus);
3116 uint32_t flags;
3117
3118 DPRINTF("\n");
3119
3120 USB_BUS_LOCK(bus);
3121
3122 flags = bus->hw_power_state;
3123
3124 /*
3125 * WARNING: Some FULL speed USB devices require periodic SOF
3126 * messages! If any USB devices are connected through the
3127 * UHCI, power save will be disabled!
3128 */
3129 if (flags & (USB_HW_POWER_CONTROL |
3130 USB_HW_POWER_NON_ROOT_HUB |
3131 USB_HW_POWER_BULK |
3132 USB_HW_POWER_INTERRUPT |
3133 USB_HW_POWER_ISOC)) {
3134 DPRINTF("Some USB transfer is "
3135 "active on unit %u.\n",
3136 device_get_unit(sc->sc_bus.bdev));
3137 uhci_restart(sc);
3138 } else {
3139 DPRINTF("Power save on unit %u.\n",
3140 device_get_unit(sc->sc_bus.bdev));
3141 UHCICMD(sc, UHCI_CMD_MAXP);
3142 }
3143
3144 USB_BUS_UNLOCK(bus);
3145
3146 return;
3147 }
3148
3149 static const struct usb_bus_methods uhci_bus_methods =
3150 {
3151 .endpoint_init = uhci_ep_init,
3152 .xfer_setup = uhci_xfer_setup,
3153 .xfer_unsetup = uhci_xfer_unsetup,
3154 .get_dma_delay = uhci_get_dma_delay,
3155 .device_resume = uhci_device_resume,
3156 .device_suspend = uhci_device_suspend,
3157 .set_hw_power = uhci_set_hw_power,
3158 .set_hw_power_sleep = uhci_set_hw_power_sleep,
3159 .roothub_exec = uhci_roothub_exec,
3160 .xfer_poll = uhci_do_poll,
3161 };
3162