1 /*
2 * Copyright 2015 Alexander Kabaev <kan@FreeBSD.org>.
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met:
8 *
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 *
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
18 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
19 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
20 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
21 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
22 * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
23 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
24 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
25 * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
26 */
27
28 #include <sys/cdefs.h>
29 #include <sys/param.h>
30 #include <sys/kernel.h>
31 #include <sys/bus.h>
32 #include <sys/callout.h>
33 #include <sys/condvar.h>
34 #include <sys/module.h>
35
36 #include <dev/extres/clk/clk.h>
37
38 #include <dev/ofw/ofw_bus_subr.h>
39
40 #include <dev/usb/usb.h>
41 #include <dev/usb/usbdi.h>
42
43 #include <dev/usb/usb_busdma.h>
44 #include <dev/usb/usb_process.h>
45
46 #include <dev/usb/usb_controller.h>
47 #include <dev/usb/usb_bus.h>
48
49 #include <dev/usb/controller/dwc_otg.h>
50 #include <dev/usb/controller/dwc_otg_fdt.h>
51
52 #include <mips/ingenic/jz4780_clock.h>
53 #include <mips/ingenic/jz4780_regs.h>
54
55 static device_probe_t jz4780_dwc_otg_probe;
56 static device_attach_t jz4780_dwc_otg_attach;
57 static device_detach_t jz4780_dwc_otg_detach;
58
59 struct jz4780_dwc_otg_softc {
60 struct dwc_otg_fdt_softc base; /* storage for DWC OTG code */
61 clk_t phy_clk;
62 clk_t otg_clk;
63 };
64
65 static int
jz4780_dwc_otg_clk_enable(device_t dev)66 jz4780_dwc_otg_clk_enable(device_t dev)
67 {
68 struct jz4780_dwc_otg_softc *sc;
69 int err;
70
71 sc = device_get_softc(dev);
72
73 /* Configure and enable phy clock */
74 err = clk_get_by_ofw_name(dev, 0, "otg_phy", &sc->phy_clk);
75 if (err != 0) {
76 device_printf(dev, "unable to lookup %s clock\n", "otg_phy");
77 return (err);
78 }
79 err = clk_set_freq(sc->phy_clk, 48000000, 0);
80 if (err != 0) {
81 device_printf(dev, "unable to set %s clock to 48 kHZ\n",
82 "otg_phy");
83 return (err);
84 }
85 err = clk_enable(sc->phy_clk);
86 if (err != 0) {
87 device_printf(dev, "unable to enable %s clock\n", "otg_phy");
88 return (err);
89 }
90
91 /* Configure and enable otg1 clock */
92 err = clk_get_by_ofw_name(dev, 0, "otg1", &sc->otg_clk);
93 if (err != 0) {
94 device_printf(dev, "unable to lookup %s clock\n", "otg1");
95 return (err);
96 }
97 err = clk_enable(sc->phy_clk);
98 if (err != 0) {
99 device_printf(dev, "unable to enable %s clock\n", "otg1");
100 return (err);
101 }
102
103 return (0);
104 }
105
106 static int
jz4780_dwc_otg_probe(device_t dev)107 jz4780_dwc_otg_probe(device_t dev)
108 {
109
110 if (!ofw_bus_status_okay(dev))
111 return (ENXIO);
112
113 if (!ofw_bus_is_compatible(dev, "ingenic,jz4780-otg"))
114 return (ENXIO);
115
116 device_set_desc(dev, "DWC OTG 2.0 integrated USB controller (jz4780)");
117
118 return (BUS_PROBE_VENDOR);
119 }
120
121 static int
jz4780_dwc_otg_attach(device_t dev)122 jz4780_dwc_otg_attach(device_t dev)
123 {
124 struct jz4780_dwc_otg_softc *sc;
125 struct resource *res;
126 int err, rid;
127
128 sc = device_get_softc(dev);
129
130 err = jz4780_dwc_otg_clk_enable(dev);
131 if (err != 0)
132 goto fail;
133
134 err = jz4780_otg_enable();
135 if (err != 0) {
136 device_printf(dev, "CGU failed to enable OTG\n");
137 goto fail;
138 }
139
140 /* Voodoo: Switch off VBUS overcurrent detection in OTG PHY */
141 res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, RF_ACTIVE);
142 if (res != NULL) {
143 uint32_t reg;
144
145 reg = bus_read_4(res, JZ_DWC2_GUSBCFG);
146 reg |= 0xc;
147 bus_write_4(res, JZ_DWC2_GUSBCFG, reg);
148 bus_release_resource(dev, SYS_RES_MEMORY, rid, res);
149 }
150
151 sc->base.sc_otg.sc_phy_type = DWC_OTG_PHY_UTMI;
152 sc->base.sc_otg.sc_phy_bits = 16;
153
154 err = dwc_otg_attach(dev);
155 if (err != 0)
156 goto fail;
157
158 return (0);
159 fail:
160 if (sc->otg_clk)
161 clk_release(sc->otg_clk);
162 if (sc->phy_clk)
163 clk_release(sc->phy_clk);
164 return (err);
165 }
166
167 static int
jz4780_dwc_otg_detach(device_t dev)168 jz4780_dwc_otg_detach(device_t dev)
169 {
170 struct jz4780_dwc_otg_softc *sc;
171 int err;
172
173 err = dwc_otg_detach(dev);
174 if (err != 0)
175 return (err);
176
177 sc = device_get_softc(dev);
178 if (sc->otg_clk)
179 clk_release(sc->otg_clk);
180 if (sc->phy_clk)
181 clk_release(sc->phy_clk);
182 return (0);
183 }
184
185 static device_method_t jz4780_dwc_otg_methods[] = {
186 /* bus interface */
187 DEVMETHOD(device_probe, jz4780_dwc_otg_probe),
188 DEVMETHOD(device_attach, jz4780_dwc_otg_attach),
189 DEVMETHOD(device_detach, jz4780_dwc_otg_detach),
190
191 DEVMETHOD_END
192 };
193
194 static devclass_t jz4780_dwc_otg_devclass;
195
196 DEFINE_CLASS_1(jzotg, jz4780_dwc_otg_driver, jz4780_dwc_otg_methods,
197 sizeof(struct jz4780_dwc_otg_softc), dwc_otg_driver);
198 DRIVER_MODULE(jzotg, simplebus, jz4780_dwc_otg_driver,
199 jz4780_dwc_otg_devclass, 0, 0);
200 MODULE_DEPEND(jzotg, usb, 1, 1, 1);
201