1 /*-
2 * Copyright (c) 2016 Stanislav Galabov.
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 *
14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
24 * SUCH DAMAGE.
25 */
26
27 #include <sys/cdefs.h>
28 #include <sys/param.h>
29 #include <sys/systm.h>
30 #include <sys/bus.h>
31 #include <sys/kernel.h>
32 #include <sys/module.h>
33 #include <sys/rman.h>
34
35 #include <machine/fdt.h>
36
37 #include <dev/ofw/openfirm.h>
38 #include <dev/ofw/ofw_bus.h>
39 #include <dev/ofw/ofw_bus_subr.h>
40
41 #include <dev/fdt/fdt_common.h>
42 #include <dev/fdt/fdt_clock.h>
43
44 #include <mips/mediatek/fdt_reset.h>
45 #include <mips/mediatek/mtk_sysctl.h>
46 #include <mips/mediatek/mtk_soc.h>
47
48 static uint32_t mtk_soc_socid = MTK_SOC_UNKNOWN;
49 static uint32_t mtk_soc_uartclk = 0;
50 static uint32_t mtk_soc_cpuclk = MTK_CPU_CLK_880MHZ;
51 static uint32_t mtk_soc_timerclk = MTK_CPU_CLK_880MHZ / 2;
52
53 static uint32_t mtk_soc_chipid0_3 = MTK_UNKNOWN_CHIPID0_3;
54 static uint32_t mtk_soc_chipid4_7 = MTK_UNKNOWN_CHIPID4_7;
55
56 static const struct ofw_compat_data compat_data[] = {
57 { "ralink,rt2880-soc", MTK_SOC_RT2880 },
58 { "ralink,rt3050-soc", MTK_SOC_RT3050 },
59 { "ralink,rt3052-soc", MTK_SOC_RT3052 },
60 { "ralink,rt3350-soc", MTK_SOC_RT3350 },
61 { "ralink,rt3352-soc", MTK_SOC_RT3352 },
62 { "ralink,rt3662-soc", MTK_SOC_RT3662 },
63 { "ralink,rt3883-soc", MTK_SOC_RT3883 },
64 { "ralink,rt5350-soc", MTK_SOC_RT5350 },
65 { "ralink,mtk7620a-soc", MTK_SOC_MT7620A },
66 { "ralink,mt7620a-soc", MTK_SOC_MT7620A },
67 { "ralink,mtk7620n-soc", MTK_SOC_MT7620N },
68 { "ralink,mt7620n-soc", MTK_SOC_MT7620N },
69 { "mediatek,mtk7621-soc", MTK_SOC_MT7621 },
70 { "mediatek,mt7621-soc", MTK_SOC_MT7621 },
71 { "ralink,mt7621-soc", MTK_SOC_MT7621 },
72 { "ralink,mtk7621-soc", MTK_SOC_MT7621 },
73 { "ralink,mtk7628an-soc", MTK_SOC_MT7628 },
74 { "mediatek,mt7628an-soc", MTK_SOC_MT7628 },
75 { "ralink,mtk7688-soc", MTK_SOC_MT7688 },
76
77 /* Sentinel */
78 { NULL, MTK_SOC_UNKNOWN },
79 };
80
81 static uint32_t
mtk_detect_cpuclk_rt2880(bus_space_tag_t bst,bus_space_handle_t bsh)82 mtk_detect_cpuclk_rt2880(bus_space_tag_t bst, bus_space_handle_t bsh)
83 {
84 uint32_t val;
85
86 val = bus_space_read_4(bst, bsh, SYSCTL_SYSCFG);
87 val >>= RT2880_CPU_CLKSEL_OFF;
88 val &= RT2880_CPU_CLKSEL_MSK;
89
90 switch (val) {
91 case 0:
92 return (MTK_CPU_CLK_250MHZ);
93 case 1:
94 return (MTK_CPU_CLK_266MHZ);
95 case 2:
96 return (MTK_CPU_CLK_280MHZ);
97 case 3:
98 return (MTK_CPU_CLK_300MHZ);
99 }
100
101 /* Never reached */
102 return (0);
103 }
104
105 static uint32_t
mtk_detect_cpuclk_rt305x(bus_space_tag_t bst,bus_space_handle_t bsh)106 mtk_detect_cpuclk_rt305x(bus_space_tag_t bst, bus_space_handle_t bsh)
107 {
108 uint32_t val;
109
110 val = bus_space_read_4(bst, bsh, SYSCTL_CHIPID0_3);
111 if (val == RT3350_CHIPID0_3)
112 return (MTK_CPU_CLK_320MHZ);
113
114 val = bus_space_read_4(bst, bsh, SYSCTL_SYSCFG);
115 val >>= RT305X_CPU_CLKSEL_OFF;
116 val &= RT305X_CPU_CLKSEL_MSK;
117
118 return ((val == 0) ? MTK_CPU_CLK_320MHZ : MTK_CPU_CLK_384MHZ);
119 }
120
121 static uint32_t
mtk_detect_cpuclk_rt3352(bus_space_tag_t bst,bus_space_handle_t bsh)122 mtk_detect_cpuclk_rt3352(bus_space_tag_t bst, bus_space_handle_t bsh)
123 {
124 uint32_t val;
125
126 val = bus_space_read_4(bst, bsh, SYSCTL_SYSCFG);
127 val >>= RT3352_CPU_CLKSEL_OFF;
128 val &= RT3352_CPU_CLKSEL_MSK;
129
130 if (val)
131 return (MTK_CPU_CLK_400MHZ);
132
133 return (MTK_CPU_CLK_384MHZ);
134 }
135
136 static uint32_t
mtk_detect_cpuclk_rt3883(bus_space_tag_t bst,bus_space_handle_t bsh)137 mtk_detect_cpuclk_rt3883(bus_space_tag_t bst, bus_space_handle_t bsh)
138 {
139 uint32_t val;
140
141 val = bus_space_read_4(bst, bsh, SYSCTL_SYSCFG);
142 val >>= RT3883_CPU_CLKSEL_OFF;
143 val &= RT3883_CPU_CLKSEL_MSK;
144
145 switch (val) {
146 case 0:
147 return (MTK_CPU_CLK_250MHZ);
148 case 1:
149 return (MTK_CPU_CLK_384MHZ);
150 case 2:
151 return (MTK_CPU_CLK_480MHZ);
152 case 3:
153 return (MTK_CPU_CLK_500MHZ);
154 }
155
156 /* Never reached */
157 return (0);
158 }
159
160 static uint32_t
mtk_detect_cpuclk_rt5350(bus_space_tag_t bst,bus_space_handle_t bsh)161 mtk_detect_cpuclk_rt5350(bus_space_tag_t bst, bus_space_handle_t bsh)
162 {
163 uint32_t val1, val2;
164
165 val1 = val2 = bus_space_read_4(bst, bsh, SYSCTL_SYSCFG);
166
167 val1 >>= RT5350_CPU_CLKSEL_OFF1;
168 val2 >>= RT5350_CPU_CLKSEL_OFF2;
169 val1 &= RT5350_CPU_CLKSEL_MSK;
170 val2 &= RT5350_CPU_CLKSEL_MSK;
171 val1 |= (val2 << 1);
172
173 switch (val1) {
174 case 0:
175 return (MTK_CPU_CLK_360MHZ);
176 case 1:
177 /* Reserved value, but we return UNKNOWN */
178 return (MTK_CPU_CLK_UNKNOWN);
179 case 2:
180 return (MTK_CPU_CLK_320MHZ);
181 case 3:
182 return (MTK_CPU_CLK_300MHZ);
183 }
184
185 /* Never reached */
186 return (0);
187 }
188
189 static uint32_t
mtk_detect_cpuclk_mt7620(bus_space_tag_t bst,bus_space_handle_t bsh)190 mtk_detect_cpuclk_mt7620(bus_space_tag_t bst, bus_space_handle_t bsh)
191 {
192 uint32_t val, mul, div, res;
193
194 val = bus_space_read_4(bst, bsh, SYSCTL_MT7620_CPLL_CFG1);
195 if (val & MT7620_CPU_CLK_AUX0)
196 return (MTK_CPU_CLK_480MHZ);
197
198 val = bus_space_read_4(bst, bsh, SYSCTL_MT7620_CPLL_CFG0);
199 if (!(val & MT7620_CPLL_SW_CFG))
200 return (MTK_CPU_CLK_600MHZ);
201
202 mul = MT7620_PLL_MULT_RATIO_BASE + ((val >> MT7620_PLL_MULT_RATIO_OFF) &
203 MT7620_PLL_MULT_RATIO_MSK);
204 div = (val >> MT7620_PLL_DIV_RATIO_OFF) & MT7620_PLL_DIV_RATIO_MSK;
205
206 if (div != MT7620_PLL_DIV_RATIO_MSK)
207 div += MT7620_PLL_DIV_RATIO_BASE;
208 else
209 div = MT7620_PLL_DIV_RATIO_MAX;
210
211 res = (MT7620_XTAL_40 * mul) / div;
212
213 return (MTK_MHZ(res));
214 }
215
216 static uint32_t
mtk_detect_cpuclk_mt7621(bus_space_tag_t bst,bus_space_handle_t bsh)217 mtk_detect_cpuclk_mt7621(bus_space_tag_t bst, bus_space_handle_t bsh)
218 {
219 uint32_t val, div, res;
220
221 val = bus_space_read_4(bst, bsh, SYSCTL_CLKCFG0);
222 if (val & MT7621_USES_MEMDIV) {
223 div = bus_space_read_4(bst, bsh, MTK_MT7621_CLKDIV_REG);
224 div >>= MT7621_MEMDIV_OFF;
225 div &= MT7621_MEMDIV_MSK;
226 div += MT7621_MEMDIV_BASE;
227
228 val = bus_space_read_4(bst, bsh, SYSCTL_SYSCFG);
229 val >>= MT7621_CLKSEL_OFF;
230 val &= MT7621_CLKSEL_MSK;
231
232 if (val >= MT7621_CLKSEL_25MHZ_VAL)
233 res = div * MT7621_CLKSEL_25MHZ;
234 else if (val >= MT7621_CLKSEL_20MHZ_VAL)
235 res = div * MT7621_CLKSEL_20MHZ;
236 else
237 res = div * 0; /* XXX: not sure about this */
238 } else {
239 val = bus_space_read_4(bst, bsh, SYSCTL_CUR_CLK_STS);
240 div = (val >> MT7621_CLK_STS_DIV_OFF) & MT7621_CLK_STS_MSK;
241 val &= MT7621_CLK_STS_MSK;
242
243 res = (MT7621_CLK_STS_BASE * val) / div;
244 }
245
246 return (MTK_MHZ(res));
247 }
248
249 static uint32_t
mtk_detect_cpuclk_mt7628(bus_space_tag_t bst,bus_space_handle_t bsh)250 mtk_detect_cpuclk_mt7628(bus_space_tag_t bst, bus_space_handle_t bsh)
251 {
252 uint32_t val;
253
254 val = bus_space_read_4(bst, bsh, SYSCTL_SYSCFG);
255 val >>= MT7628_CPU_CLKSEL_OFF;
256 val &= MT7628_CPU_CLKSEL_MSK;
257
258 if (val)
259 return (MTK_CPU_CLK_580MHZ);
260
261 return (MTK_CPU_CLK_575MHZ);
262 }
263
264 void
mtk_soc_try_early_detect(void)265 mtk_soc_try_early_detect(void)
266 {
267 bus_space_tag_t bst;
268 bus_space_handle_t bsh;
269 uint32_t base;
270 phandle_t node;
271 int i;
272
273 if ((node = OF_finddevice("/")) == -1)
274 return;
275
276 for (i = 0; compat_data[i].ocd_str != NULL; i++) {
277 if (ofw_bus_node_is_compatible(node, compat_data[i].ocd_str)) {
278 mtk_soc_socid = compat_data[i].ocd_data;
279 break;
280 }
281 }
282
283 if (mtk_soc_socid == MTK_SOC_UNKNOWN) {
284 /* We don't know the SoC, so we don't know how to get clocks */
285 return;
286 }
287
288 bst = fdtbus_bs_tag;
289 if (mtk_soc_socid == MTK_SOC_RT2880)
290 base = MTK_RT2880_BASE;
291 else if (mtk_soc_socid == MTK_SOC_MT7621)
292 base = MTK_MT7621_BASE;
293 else
294 base = MTK_DEFAULT_BASE;
295
296 if (bus_space_map(bst, base, MTK_DEFAULT_SIZE, 0, &bsh))
297 return;
298
299 /* Get our CHIP ID */
300 mtk_soc_chipid0_3 = bus_space_read_4(bst, bsh, SYSCTL_CHIPID0_3);
301 mtk_soc_chipid4_7 = bus_space_read_4(bst, bsh, SYSCTL_CHIPID4_7);
302
303 /* First, figure out the CPU clock */
304 switch (mtk_soc_socid) {
305 case MTK_SOC_RT2880:
306 mtk_soc_cpuclk = mtk_detect_cpuclk_rt2880(bst, bsh);
307 break;
308 case MTK_SOC_RT3050: /* fallthrough */
309 case MTK_SOC_RT3052:
310 case MTK_SOC_RT3350:
311 mtk_soc_cpuclk = mtk_detect_cpuclk_rt305x(bst, bsh);
312 break;
313 case MTK_SOC_RT3352:
314 mtk_soc_cpuclk = mtk_detect_cpuclk_rt3352(bst, bsh);
315 break;
316 case MTK_SOC_RT3662: /* fallthrough */
317 case MTK_SOC_RT3883:
318 mtk_soc_cpuclk = mtk_detect_cpuclk_rt3883(bst, bsh);
319 break;
320 case MTK_SOC_RT5350:
321 mtk_soc_cpuclk = mtk_detect_cpuclk_rt5350(bst, bsh);
322 break;
323 case MTK_SOC_MT7620A: /* fallthrough */
324 case MTK_SOC_MT7620N:
325 mtk_soc_cpuclk = mtk_detect_cpuclk_mt7620(bst, bsh);
326 break;
327 case MTK_SOC_MT7621:
328 mtk_soc_cpuclk = mtk_detect_cpuclk_mt7621(bst, bsh);
329 break;
330 case MTK_SOC_MT7628: /* fallthrough */
331 case MTK_SOC_MT7688:
332 mtk_soc_cpuclk = mtk_detect_cpuclk_mt7628(bst, bsh);
333 break;
334 default:
335 /* We don't know the SoC, so we can't find the CPU clock */
336 break;
337 }
338
339 /* Now figure out the timer clock */
340 if (mtk_soc_socid == MTK_SOC_MT7621) {
341 #ifdef notyet
342 /*
343 * We use the GIC timer for timing source and its clock freq is
344 * the same as the CPU's clock freq
345 */
346 mtk_soc_timerclk = mtk_soc_cpuclk;
347 #else
348 /*
349 * When GIC timer and MIPS timer are ready to co-exist and
350 * GIC timer is actually implemented, we need to switch to it.
351 * Until then we use a fake GIC timer, which is actually a
352 * normal MIPS ticker, so the timer clock is half the CPU clock
353 */
354 mtk_soc_timerclk = mtk_soc_cpuclk / 2;
355 #endif
356 } else {
357 /*
358 * We use the MIPS ticker for the rest for now, so
359 * the CPU clock is divided by 2
360 */
361 mtk_soc_timerclk = mtk_soc_cpuclk / 2;
362 }
363
364 switch (mtk_soc_socid) {
365 case MTK_SOC_RT2880:
366 mtk_soc_uartclk = mtk_soc_cpuclk / MTK_UARTDIV_2;
367 break;
368 case MTK_SOC_RT3350: /* fallthrough */
369 case MTK_SOC_RT3050: /* fallthrough */
370 case MTK_SOC_RT3052:
371 /* UART clock is CPU clock / 3 */
372 mtk_soc_uartclk = mtk_soc_cpuclk / MTK_UARTDIV_3;
373 break;
374 case MTK_SOC_RT3352: /* fallthrough */
375 case MTK_SOC_RT3662: /* fallthrough */
376 case MTK_SOC_RT3883: /* fallthrough */
377 case MTK_SOC_RT5350: /* fallthrough */
378 case MTK_SOC_MT7620A: /* fallthrough */
379 case MTK_SOC_MT7620N: /* fallthrough */
380 case MTK_SOC_MT7628: /* fallthrough */
381 case MTK_SOC_MT7688:
382 /* UART clock is always 40MHz */
383 mtk_soc_uartclk = MTK_UART_CLK_40MHZ;
384 break;
385 case MTK_SOC_MT7621:
386 /* UART clock is always 50MHz */
387 mtk_soc_uartclk = MTK_UART_CLK_50MHZ;
388 break;
389 default:
390 /* We don't know the SoC, so we don't know the UART clock */
391 break;
392 }
393
394 bus_space_unmap(bst, bsh, MTK_DEFAULT_SIZE);
395 }
396
397 void
mtk_soc_set_cpu_model(void)398 mtk_soc_set_cpu_model(void)
399 {
400 int idx, offset = sizeof(mtk_soc_chipid0_3);
401 char *chipid0_3 = (char *)(&mtk_soc_chipid0_3);
402 char *chipid4_7 = (char *)(&mtk_soc_chipid4_7);
403
404 /*
405 * CHIPID is always 2x32 bit registers, containing the ASCII
406 * representation of the chip, so use that directly.
407 *
408 * The info is either pre-populated in mtk_soc_try_early_detect() or
409 * it is left at its default value of "unknown " if it could not be
410 * obtained for some reason.
411 */
412 for (idx = 0; idx < offset; idx++) {
413 cpu_model[idx] = chipid0_3[idx];
414 cpu_model[idx + offset] = chipid4_7[idx];
415 }
416
417 /* Null-terminate the string */
418 cpu_model[2 * offset] = 0;
419 }
420
421 uint32_t
mtk_soc_get_uartclk(void)422 mtk_soc_get_uartclk(void)
423 {
424
425 return mtk_soc_uartclk;
426 }
427
428 uint32_t
mtk_soc_get_cpuclk(void)429 mtk_soc_get_cpuclk(void)
430 {
431
432 return mtk_soc_cpuclk;
433 }
434
435 uint32_t
mtk_soc_get_timerclk(void)436 mtk_soc_get_timerclk(void)
437 {
438
439 return mtk_soc_timerclk;
440 }
441
442 uint32_t
mtk_soc_get_socid(void)443 mtk_soc_get_socid(void)
444 {
445
446 return mtk_soc_socid;
447 }
448
449 /*
450 * The following are generic reset and clock functions
451 */
452
453 /* Default reset time is 100ms */
454 #define DEFAULT_RESET_TIME 100000
455
456 int
mtk_soc_reset_device(device_t dev)457 mtk_soc_reset_device(device_t dev)
458 {
459 int res;
460
461 res = fdt_reset_assert_all(dev);
462 if (res == 0) {
463 DELAY(DEFAULT_RESET_TIME);
464 res = fdt_reset_deassert_all(dev);
465 if (res == 0)
466 DELAY(DEFAULT_RESET_TIME);
467 }
468
469 return (res);
470 }
471
472 int
mtk_soc_stop_clock(device_t dev)473 mtk_soc_stop_clock(device_t dev)
474 {
475
476 return (fdt_clock_disable_all(dev));
477 }
478
479 int
mtk_soc_start_clock(device_t dev)480 mtk_soc_start_clock(device_t dev)
481 {
482
483 return (fdt_clock_enable_all(dev));
484 }
485
486 int
mtk_soc_assert_reset(device_t dev)487 mtk_soc_assert_reset(device_t dev)
488 {
489
490 return (fdt_reset_assert_all(dev));
491 }
492
493 int
mtk_soc_deassert_reset(device_t dev)494 mtk_soc_deassert_reset(device_t dev)
495 {
496
497 return (fdt_reset_deassert_all(dev));
498 }
499
500 void
mtk_soc_reset(void)501 mtk_soc_reset(void)
502 {
503
504 mtk_sysctl_clr_set(SYSCTL_RSTCTRL, 0, 1);
505 mtk_sysctl_clr_set(SYSCTL_RSTCTRL, 1, 0);
506 }
507