1 /* $NetBSD: sxreg.h,v 1.22 2024/05/12 13:43:27 macallan Exp $ */ 2 3 /*- 4 * Copyright (c) 2013 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Michael Lorenz. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 /* register definitions for Sun's SX / SPAM rendering engine */ 33 34 #ifndef SXREG_H 35 #define SXREG_H 36 37 /* SX control registers */ 38 #define SX_CONTROL_STATUS 0x00000000 39 #define SX_ERROR 0x00000004 40 #define SX_PAGE_BOUND_LOWER 0x00000008 41 #define SX_PAGE_BOUND_UPPER 0x0000000c 42 #define SX_PLANEMASK 0x00000010 43 #define SX_ROP_CONTROL 0x00000014 /* 8 bit ROP */ 44 #define SX_IQ_OVERFLOW_COUNTER 0x00000018 45 #define SX_DIAGNOSTICS 0x0000001c 46 #define SX_INSTRUCTIONS 0x00000020 47 #define SX_ID 0x00000028 48 #define SX_R0_INIT 0x0000002c 49 #define SX_SOFTRESET 0x00000030 50 #define SX_SYNC 0x00000034 /* write will stall CPU until */ 51 /* SX is idle */ 52 /* write registers directly, only when processor is stopped */ 53 #define SX_DIRECT_R0 0x00000100 54 #define SX_DIRECT_R1 0x00000104 /* and so on until R127 */ 55 /* write registers via pseudo instructions */ 56 #define SX_QUEUED_R0 0x00000300 57 #define SX_QUEUED_R1 0x00000304 /* and so on until R127 */ 58 #define SX_QUEUED(r) (0x300 + ((r) << 2)) 59 60 /* special purpose registers */ 61 #define R_ZERO 0 62 #define R_SCAM 1 63 #define R_MASK 2 /* bitmask for SX_STORE_SELECT */ 64 65 /* 66 * registers are repeated at 0x1000 with certain parts read only 67 * ( like the PAGE_BOUND registers ) which userland has no business writing to 68 */ 69 70 /* SX_CONTROL_STATUS */ 71 #define SX_EE1 0x00000001 /* illegal instruction */ 72 #define SX_EE2 0x00000002 /* page bound error */ 73 #define SX_EE3 0x00000004 /* illegal memory access */ 74 #define SX_EE4 0x00000008 /* illegal register access */ 75 #define SX_EE5 0x00000010 /* alignment violation */ 76 #define SX_EE6 0x00000020 /* illegal instruction queue write */ 77 #define SX_EI 0x00000080 /* interrupt on error */ 78 /* 79 * XXX 80 * the following bit definitions are from the SX manual. They're defined in a 81 * different way in SunOS's sxreg.h, the hardware seems to follow the latter. 82 */ 83 #if 0 84 #define SX_PB 0x00001000 /* enable page bound checking */ 85 #define SX_WO 0x00002000 /* write occurred ( by SX ) */ 86 #define SX_GO 0x00004000 /* start/stop the processor */ 87 #define SX_MT 0x00008000 /* instruction queue is empty */ 88 #endif 89 90 #define SX_PB 0x00000400 /* enable page bound checking */ 91 #define SX_WO 0x00000800 /* write occurred ( by SX ) */ 92 #define SX_GO 0x00001000 /* start/stop the processor */ 93 #define SX_JB 0x00002000 /* Jammed/Busy specifies the type of events */ 94 /* which increment the SX timer */ 95 #define SX_MT 0x00004000 /* instruction queue is empty */ 96 #define SX_BZ 0x00008000 /* Busy bit. When set it indicates that SX */ 97 /* is processing an instruction or an */ 98 /* instruction is pending in the Q */ 99 #define SX_B0MOD 0x00010000 /* When set by SX it indicates that a write */ 100 /* to bank zero of the SX registers (0-31) */ 101 /* occurred */ 102 #define SX_B1MOD 0x00020000 /* When set by SX it indicates that a write */ 103 /* to bank 1 of the SX registers (32-63) */ 104 /* occurred */ 105 #define SX_B2MOD 0x00040000 /* When set by SX it indicates that a write */ 106 /* to bank 2 of the SX registers (64-95) */ 107 /* occurred */ 108 #define SX_B3MOD 0x00080000 /* When set by SX it indicates that a write */ 109 /* to bank 3 of the SX registers (96-127) */ 110 /* occurred */ 111 112 /* SX_ERROR */ 113 #define SX_SE1 0x00000001 /* illegal instruction */ 114 #define SX_SE2 0x00000002 /* page bound error */ 115 #define SX_SE3 0x00000004 /* illegal memory access */ 116 #define SX_SE4 0x00000008 /* illegal register access */ 117 #define SX_SE5 0x00000010 /* alignment violation */ 118 #define SX_SE6 0x00000020 /* illegal instruction queue write */ 119 #define SX_SI 0x00000080 /* interrupt on error */ 120 121 /* SX_ID from the manual */ 122 #if 0 123 #define SX_ARCHITECTURE_MASK 0x000000ff 124 #define SX_CHIP_REVISION 0x0000ff00 125 #endif 126 127 #define SX_ARCHITECTURE_MASK 0x00000003 128 #define SX_CHIP_REVISION 0x000000f8 129 130 /* SX_DIAGNOSTICS */ 131 #define SX_IQ_FIFO_ACCESS 0x00000001 /* allow memory instructions 132 * in SX_INSTRUCTIONS */ 133 #define SX_SERIAL_INSTRUCTIONS 0x00000002 /* force inst. serializing */ 134 #define SX_RAM_PAGE_CROSS 0x00000004 /* indicates page crossing */ 135 #define SX_ARRAY_CONSTRAINING 0x00000008 /* When set constrains VRAM */ 136 /* array offset effective */ 137 /* address calculation */ 138 #define SX_UPG_MPG_DISABLE 0x00000010 /* When set, disables page */ 139 /* cross input into ld/st */ 140 /* state machines */ 141 #define SX_DIAG_INIT 0x4804 /* Setting of the diag reg */ 142 /* upon reset */ 143 144 145 /* 146 * memory referencing instructions are written to 0x800000000 + PA 147 * so we have to go through ASI 0x28 ( ASI_BYPASS + 8 ) 148 */ 149 #define ASI_SX 0x28 150 151 /* load / store instructions */ 152 #define SX_STORE_COND (0x4 << 19) /* conditional write with mask */ 153 #define SX_STORE_CLAMP (0x2 << 19) 154 #define SX_STORE_MASK (0x1 << 19) /* apply plane mask */ 155 #define SX_STORE_SELECT (0x8 << 19) /* expand with plane reg dest[0]/dest[1] */ 156 #define SX_LOAD (0xa << 19) 157 #define SX_STORE (0x0 << 19) 158 159 /* data type */ 160 #define SX_UBYTE_0 (0x00 << 14) 161 #define SX_UBYTE_8 (0x01 << 14) 162 #define SX_UBYTE_16 (0x02 << 14) 163 #define SX_UBYTE_24 (0x03 << 14) 164 #define SX_SBYTE_0 (0x04 << 14) 165 #define SX_SBYTE_8 (0x05 << 14) 166 #define SX_SBYTE_16 (0x06 << 14) 167 #define SX_SBYTE_24 (0x07 << 14) 168 #define SX_UQUAD_0 (0x08 << 14) 169 #define SX_UQUAD_8 (0x09 << 14) 170 #define SX_UQUAD_16 (0x0a << 14) 171 #define SX_UQUAD_24 (0x0b << 14) 172 #define SX_SQUAD_0 (0x0c << 14) 173 #define SX_SQUAD_8 (0x0d << 14) 174 #define SX_SQUAD_16 (0x0e << 14) 175 #define SX_SQUAD_24 (0x0f << 14) 176 #define SX_UCHAN_0 (0x10 << 14) 177 #define SX_UCHAN_8 (0x11 << 14) 178 #define SX_UCHAN_16 (0x12 << 14) 179 #define SX_UCHAN_24 (0x13 << 14) 180 #define SX_SCHAN_0 (0x14 << 14) 181 #define SX_SCHAN_8 (0x15 << 14) 182 #define SX_SCHAN_16 (0x16 << 14) 183 #define SX_SCHAN_24 (0x17 << 14) 184 #define SX_USHORT_0 (0x18 << 14) 185 #define SX_USHORT_8 (0x19 << 14) 186 #define SX_USHORT_16 (0x1a << 14) 187 #define SX_SSHORT_0 (0x1c << 14) 188 #define SX_SSHORT_8 (0x1d << 14) 189 #define SX_SSHORT_16 (0x1e << 14) 190 #define SX_LONG (0x1b << 14) 191 #define SX_PACKED (0x1f << 14) 192 193 194 #define SX_LD(dreg, cnt, o) (0x80000000 | ((cnt) << 23) | SX_LOAD | \ 195 SX_LONG | (dreg << 7) | (o)) 196 #define SX_LDB(dreg, cnt, o) (0x80000000 | ((cnt) << 23) | SX_LOAD | \ 197 SX_UBYTE_0 | (dreg << 7) | (o)) 198 #define SX_LDW(dreg, cnt, o) (0x80000000 | ((cnt) << 23) | SX_LOAD | \ 199 SX_USHORT_0 | (dreg << 7) | (o)) 200 #define SX_LDP(dreg, cnt, o) (0x80000000 | ((cnt) << 23) | SX_LOAD | \ 201 SX_PACKED | (dreg << 7) | (o)) 202 #define SX_LDUQ0(dreg, cnt, o) (0x80000000 | ((cnt) << 23) | SX_LOAD | \ 203 SX_UQUAD_0 | (dreg << 7) | (o)) 204 #define SX_LDUQ8(dreg, cnt, o) (0x80000000 | ((cnt) << 23) | SX_LOAD | \ 205 SX_UQUAD_8 | (dreg << 7) | (o)) 206 #define SX_LDUQ16(dreg, cnt, o) (0x80000000 | ((cnt) << 23) | SX_LOAD | \ 207 SX_UQUAD_16 | (dreg << 7) | (o)) 208 #define SX_LDUQ24(dreg, cnt, o) (0x80000000 | ((cnt) << 23) | SX_LOAD | \ 209 SX_UQUAD_24 | (dreg << 7) | (o)) 210 #define SX_LDUC0(dreg, cnt, o) (0x80000000 | ((cnt) << 23) | SX_LOAD | \ 211 SX_UCHAN_0 | (dreg << 7) | (o)) 212 #define SX_LDUC8(dreg, cnt, o) (0x80000000 | ((cnt) << 23) | SX_LOAD | \ 213 SX_UCHAN_8 | (dreg << 7) | (o)) 214 #define SX_LDUC16(dreg, cnt, o) (0x80000000 | ((cnt) << 23) | SX_LOAD | \ 215 SX_UCHAN_16 | (dreg << 7) | (o)) 216 #define SX_LDUC24(dreg, cnt, o) (0x80000000 | ((cnt) << 23) | SX_LOAD | \ 217 SX_UCHAN_24 | (dreg << 7) | (o)) 218 #define SX_ST(sreg, cnt, o) (0x80000000 | ((cnt) << 23) | SX_STORE | \ 219 SX_LONG | (sreg << 7) | (o)) 220 #define SX_STM(sreg, cnt, o) (0x80000000 | ((cnt) << 23) | SX_STORE_MASK | \ 221 SX_LONG | (sreg << 7) | (o)) 222 #define SX_STB(sreg, cnt, o) (0x80000000 | ((cnt) << 23) | SX_STORE | \ 223 SX_UBYTE_0 | (sreg << 7) | (o)) 224 #define SX_STBM(sreg, cnt, o) (0x80000000 | ((cnt) << 23) | SX_STORE_MASK | \ 225 SX_UBYTE_0 | (sreg << 7) | (o)) 226 #define SX_STBC(sreg, cnt, o) (0x80000000 | ((cnt) << 23) | SX_STORE_CLAMP | \ 227 SX_UBYTE_0 | (sreg << 7) | (o)) 228 #define SX_STW(sreg, cnt, o) (0x80000000 | ((cnt) << 23) | SX_STORE | \ 229 SX_USHORT_0 | (sreg << 7) | (o)) 230 #define SX_STP(sreg, cnt, o) (0x80000000 | ((cnt) << 23) | SX_STORE | \ 231 SX_PACKED | (sreg << 7) | (o)) 232 #define SX_STPS(sreg, cnt, o) (0x80000000 | ((cnt) << 23) | SX_STORE_SELECT | \ 233 SX_PACKED | (sreg << 7) | (o)) 234 #define SX_STS(sreg, cnt, o) (0x80000000 | ((cnt) << 23) | SX_STORE_SELECT \ 235 | SX_LONG | (sreg << 7) | (o)) 236 #define SX_STBS(reg, cnt, o) (0x80000000 | ((cnt) << 23) | SX_STORE_SELECT \ 237 | SX_UBYTE_0 | (reg << 7) | (o)) 238 #define SX_STUQ0(sreg, cnt, o) (0x80000000 | ((cnt) << 23) | SX_STORE | \ 239 SX_UQUAD_0 | (sreg << 7) | (o)) 240 #define SX_STUQ0C(sreg, cnt, o) (0x80000000 | ((cnt) << 23) | SX_STORE_CLAMP | \ 241 SX_UQUAD_0 | (sreg << 7) | (o)) 242 #define SX_STUQ8(sreg, cnt, o) (0x80000000 | ((cnt) << 23) | SX_STORE | \ 243 SX_UQUAD_8 | (sreg << 7) | (o)) 244 #define SX_STUQ16(sreg, cnt, o) (0x80000000 | ((cnt) << 23) | SX_STORE | \ 245 SX_UQUAD_16 | (sreg << 7) | (o)) 246 #define SX_STUQ24(sreg, cnt, o) (0x80000000 | ((cnt) << 23) | SX_STORE | \ 247 SX_UQUAD_24 | (sreg << 7) | (o)) 248 #define SX_STUC0(sreg, cnt, o) (0x80000000 | ((cnt) << 23) | SX_STORE | \ 249 SX_UCHAN_0 | (sreg << 7) | (o)) 250 #define SX_STUC0C(sreg, cnt, o) (0x80000000 | ((cnt) << 23) | SX_STORE_CLAMP | \ 251 SX_UCHAN_0 | (sreg << 7) | (o)) 252 #define SX_STUC8(sreg, cnt, o) (0x80000000 | ((cnt) << 23) | SX_STORE | \ 253 SX_UCHAN_8 | (sreg << 7) | (o)) 254 #define SX_STUC16(sreg, cnt, o) (0x80000000 | ((cnt) << 23) | SX_STORE | \ 255 SX_UCHAN_16 | (sreg << 7) | (o)) 256 #define SX_STUC24(sreg, cnt, o) (0x80000000 | ((cnt) << 23) | SX_STORE | \ 257 SX_UCHAN_24 | (sreg << 7) | (o)) 258 259 /* ROP and SELECT instructions */ 260 #define SX_ROP_B (0x0 << 21) /* mask bits apply to bytes */ 261 #define SX_ROP_M (0x1 << 21) /* mask bits apply to each bit */ 262 #define SX_ROP_L (0x2 << 21) /* mask bits apply per register */ 263 #define SX_SEL_B (0x4 << 21) /* byte select scalar */ 264 #define SX_SEL_V (0x6 << 21) /* register select vector */ 265 #define SX_SEL_S (0x7 << 21) /* register select scalar */ 266 267 #define SX_ROP(sa, sb, d, cnt) (0x90000000 | ((cnt) << 24) | SX_ROP_L | \ 268 ((sa) << 14) | (sb) | ((d) << 7)) 269 #define SX_ROPB(sa, sb, d, cnt) (0x90000000 | ((cnt) << 24) | SX_ROP_B | \ 270 ((sa) << 14) | (sb) | ((d) << 7)) 271 #define SX_SELECT_S(sa, sb, d, cnt) (0x90000000 | ((cnt) << 24) | SX_SEL_S | \ 272 ((sa) << 14) | (sb) | ((d) << 7)) 273 274 /* multiply group */ 275 #define SX_M16X16SR0 (0x0 << 28) /* 16bit multiply, no shift */ 276 #define SX_M16X16SR8 (0x1 << 28) /* 16bit multiply, shift right 8 */ 277 #define SX_M16X16SR16 (0x2 << 28) /* 16bit multiply, shift right 16 */ 278 #define SX_M32X16SR0 (0x4 << 28) /* 32x16bit multiply, no shift */ 279 #define SX_M32X16SR8 (0x5 << 28) /* 32x16bit multiply, shift right 8 */ 280 #define SX_M32X16SR16 (0x6 << 28) /* 32x16bit multiply, shift right 16 */ 281 282 #define SX_MULTIPLY (0x0 << 21) /* normal multiplication */ 283 #define SX_DOT (0x1 << 21) /* dot product of A and B */ 284 #define SX_SAXP (0x2 << 21) /* A * SCAM + B */ 285 286 #define SX_ROUND (0x1 << 23) /* round results */ 287 288 #define SX_MUL16X16(sa, sb, d, cnt) (SX_M16X16SR0 | ((cnt) << 24) | \ 289 SX_MULTIPLY | ((sa) << 14) | ((d) << 7) | (sb)) 290 #define SX_MUL16X16R(sa, sb, d, cnt) (SX_M16X16SR0 | ((cnt) << 24) | \ 291 SX_MULTIPLY | ((sa) << 14) | ((d) << 7) | (sb) | SX_ROUND) 292 #define SX_MUL16X16SR8(sa, sb, d, cnt) (SX_M16X16SR8 | ((cnt) << 24) | \ 293 SX_MULTIPLY | ((sa) << 14) | ((d) << 7) | (sb)) 294 #define SX_MUL16X16SR8R(sa, sb, d, cnt) (SX_M16X16SR8 | ((cnt) << 24) | \ 295 SX_MULTIPLY | ((sa) << 14) | ((d) << 7) | (sb) | SX_ROUND) 296 297 #define SX_SAXP16X16(sa, sb, d, cnt) (SX_M16X16SR0 | ((cnt) << 24) | \ 298 SX_SAXP | ((sa) << 14) | ((d) << 7) | (sb)) 299 #define SX_SAXP16X16R(sa, sb, d, cnt) (SX_M16X16SR0 | ((cnt) << 24) | \ 300 SX_SAXP | ((sa) << 14) | ((d) << 7) | (sb) | SX_ROUND) 301 #define SX_SAXP16X16SR8(sa, sb, d, cnt) (SX_M16X16SR8 | ((cnt) << 24) | \ 302 SX_SAXP | ((sa) << 14) | ((d) << 7) | (sb)) 303 #define SX_SAXP16X16SR8R(sa, sb, d, cnt) (SX_M16X16SR8 | ((cnt) << 24) | \ 304 SX_SAXP | ((sa) << 14) | ((d) << 7) | (sb) | SX_ROUND) 305 306 /* logic group */ 307 #define SX_AND_V (0x0 << 21) /* vector AND vector */ 308 #define SX_AND_S (0x1 << 21) /* vector AND scalar */ 309 #define SX_AND_I (0x2 << 21) /* vector AND immediate */ 310 #define SX_XOR_V (0x3 << 21) /* vector XOR vector */ 311 #define SX_XOR_S (0x4 << 21) /* vector XOR scalar */ 312 #define SX_XOR_I (0x5 << 21) /* vector XOR immediate */ 313 #define SX_OR_V (0x6 << 21) /* vector OR vector */ 314 #define SX_OR_S (0x7 << 21) /* vector OR scalar */ 315 /* immediates are 7bit sign extended to 32bit */ 316 317 #define SX_ANDV(sa, sb, d, cnt) (0xb0000000 | ((cnt) << 24) | SX_AND_V | \ 318 ((sa) << 14) | ((d) << 7) | (sb)) 319 #define SX_ANDS(sa, sb, d, cnt) (0xb0000000 | ((cnt) << 24) | SX_AND_S | \ 320 ((sa) << 14) | ((d) << 7) | (sb)) 321 #define SX_ANDI(sa, sb, d, cnt) (0xb0000000 | ((cnt) << 24) | SX_AND_I | \ 322 ((sa) << 14) | ((d) << 7) | (sb)) 323 #define SX_XORV(sa, sb, d, cnt) (0xb0000000 | ((cnt) << 24) | SX_XOR_V | \ 324 ((sa) << 14) | ((d) << 7) | (sb)) 325 #define SX_XORS(sa, sb, d, cnt) (0xb0000000 | ((cnt) << 24) | SX_XOR_S | \ 326 ((sa) << 14) | ((d) << 7) | (sb)) 327 #define SX_XORI(sa, sb, d, cnt) (0xb0000000 | ((cnt) << 24) | SX_XOR_I | \ 328 ((sa) << 14) | ((d) << 7) | (sb)) 329 #define SX_ORV(sa, sb, d, cnt) (0xb0000000 | ((cnt) << 24) | SX_OR_V | \ 330 ((sa) << 14) | ((d) << 7) | (sb)) 331 #define SX_ORS(sa, sb, d, cnt) (0xb0000000 | ((cnt) << 24) | SX_OR_S | \ 332 ((sa) << 14) | ((d) << 7) | (sb)) 333 334 /* arithmetic group */ 335 #define SX_ADD_V (0x00 << 21) /* vector + vector */ 336 #define SX_ADD_S (0x01 << 21) /* vector + scalar */ 337 #define SX_ADD_I (0x02 << 21) /* vector + immediate */ 338 #define SX_SUM (0x03 << 21) /* sum of vector and scalar */ 339 #define SX_SUB_V (0x04 << 21) /* vector - vector */ 340 #define SX_SUB_S (0x05 << 21) /* vector - scalar */ 341 #define SX_SUB_I (0x06 << 21) /* vector - immediate */ 342 #define SX_ABS (0x07 << 21) /* abs(sb) with sa=R0 */ 343 /* hardware does sa - sb for sb < 0 and sa + sb if sb > 0 */ 344 345 #define SX_ADDV(sa, sb, d, cnt) (0xa0000000 | ((cnt) << 24) | SX_ADD_V | \ 346 ((sa) << 14) | ((d) << 7) | (sb)) 347 348 /* MISC group */ 349 #define SX_GTHR (3 << 21) /* sa with spacing sb -> d */ 350 #define SX_SCTR (2 << 21) /* sa -> d with spacing sb */ 351 #define SX_GATHER(sa, sb, d, cnt) (0xe0000000 | ((cnt) << 24) | SX_GTHR | \ 352 ((sa) << 14) | ((d) << 7) | (sb)) 353 #define SX_SCATTER(sa, sb, d, cnt) (0xe0000000 | ((cnt) << 24) | SX_SCTR | \ 354 ((sa) << 14) | ((d) << 7) | (sb)) 355 356 /* shift group */ 357 #define SX_SRL_V (0 << 21) /* shift right logical, by vector */ 358 #define SX_SRL_I (1 << 21) /* shift right logical, by immediate */ 359 #define SX_SRA_V (2 << 21) /* shift right arithmetic, by vector */ 360 #define SX_SRA_I (3 << 21) /* shift right arithmetic, by immediate */ 361 #define SX_SLL_V (4 << 21) /* shift left logical, by vector */ 362 #define SX_SLL_I (5 << 21) /* shift left logical, by immediate */ 363 #define SX_SLF_S (6 << 21) /* shift left funnel, by SRCB */ 364 #define SX_SLF_I (7 << 21) /* shift left funnel, by immediate */ 365 366 #define SX_SRLV(sa, sb, d, cnt) (0xc0000000 | ((cnt) << 24) | SX_SRL_V | \ 367 ((sa) << 14) | ((d) << 7) | (sb)) 368 #define SX_SRLI(sa, sb, d, cnt) (0xc0000000 | ((cnt) << 24) | SX_SRL_I | \ 369 ((sa) << 14) | ((d) << 7) | (sb)) 370 #define SX_SRAV(sa, sb, d, cnt) (0xc0000000 | ((cnt) << 24) | SX_SRA_V | \ 371 ((sa) << 14) | ((d) << 7) | (sb)) 372 #define SX_SRAI(sa, sb, d, cnt) (0xc0000000 | ((cnt) << 24) | SX_SRA_I | \ 373 ((sa) << 14) | ((d) << 7) | (sb)) 374 #define SX_SLLV(sa, sb, d, cnt) (0xc0000000 | ((cnt) << 24) | SX_SLL_V | \ 375 ((sa) << 14) | ((d) << 7) | (sb)) 376 #define SX_SLLI(sa, sb, d, cnt) (0xc0000000 | ((cnt) << 24) | SX_SLL_I | \ 377 ((sa) << 14) | ((d) << 7) | (sb)) 378 #define SX_FUNNEL_S(sa, sb, d, cnt) (0xc0000000 | ((cnt) << 24) | SX_SLF_S | \ 379 ((sa) << 14) | ((d) << 7) | (sb)) 380 #define SX_FUNNEL_I(sa, sb, d, cnt) (0xc0000000 | ((cnt) << 24) | SX_SLF_I | \ 381 ((sa) << 14) | ((d) << 7) | (sb)) 382 383 #endif /* SXREG_H */ 384