[Midnightbsd-cvs] src: dev/bge: merge
laffer1 at midnightbsd.org
laffer1 at midnightbsd.org
Tue Nov 25 11:38:46 EST 2008
Log Message:
-----------
merge
Modified Files:
--------------
src/sys/dev/bge:
if_bge.c (r1.2 -> r1.3)
if_bgereg.h (r1.1.1.2 -> r1.2)
-------------- next part --------------
Index: if_bgereg.h
===================================================================
RCS file: /home/cvs/src/sys/dev/bge/if_bgereg.h,v
retrieving revision 1.1.1.2
retrieving revision 1.2
diff -L sys/dev/bge/if_bgereg.h -L sys/dev/bge/if_bgereg.h -u -r1.1.1.2 -r1.2
--- sys/dev/bge/if_bgereg.h
+++ sys/dev/bge/if_bgereg.h
@@ -30,7 +30,7 @@
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
* THE POSSIBILITY OF SUCH DAMAGE.
*
- * $FreeBSD: src/sys/dev/bge/if_bgereg.h,v 1.36.2.4 2006/02/05 18:07:15 oleg Exp $
+ * $FreeBSD: src/sys/dev/bge/if_bgereg.h,v 1.73 2007/05/22 19:22:58 jkim Exp $
*/
/*
@@ -61,58 +61,65 @@
* Flat mode consumes so much host address space that it is not
* recommended.
*/
-#define BGE_PAGE_ZERO 0x00000000
-#define BGE_PAGE_ZERO_END 0x000000FF
-#define BGE_SEND_RING_RCB 0x00000100
-#define BGE_SEND_RING_RCB_END 0x000001FF
-#define BGE_RX_RETURN_RING_RCB 0x00000200
-#define BGE_RX_RETURN_RING_RCB_END 0x000002FF
-#define BGE_STATS_BLOCK 0x00000300
-#define BGE_STATS_BLOCK_END 0x00000AFF
-#define BGE_STATUS_BLOCK 0x00000B00
-#define BGE_STATUS_BLOCK_END 0x00000B4F
-#define BGE_SOFTWARE_GENCOMM 0x00000B50
-#define BGE_SOFTWARE_GENCOMM_SIG 0x00000B54
-#define BGE_SOFTWARE_GENCOMM_NICCFG 0x00000B58
-#define BGE_SOFTWARE_GENCOMM_END 0x00000FFF
-#define BGE_UNMAPPED 0x00001000
-#define BGE_UNMAPPED_END 0x00001FFF
-#define BGE_DMA_DESCRIPTORS 0x00002000
-#define BGE_DMA_DESCRIPTORS_END 0x00003FFF
-#define BGE_SEND_RING_1_TO_4 0x00004000
-#define BGE_SEND_RING_1_TO_4_END 0x00005FFF
+#define BGE_PAGE_ZERO 0x00000000
+#define BGE_PAGE_ZERO_END 0x000000FF
+#define BGE_SEND_RING_RCB 0x00000100
+#define BGE_SEND_RING_RCB_END 0x000001FF
+#define BGE_RX_RETURN_RING_RCB 0x00000200
+#define BGE_RX_RETURN_RING_RCB_END 0x000002FF
+#define BGE_STATS_BLOCK 0x00000300
+#define BGE_STATS_BLOCK_END 0x00000AFF
+#define BGE_STATUS_BLOCK 0x00000B00
+#define BGE_STATUS_BLOCK_END 0x00000B4F
+#define BGE_SOFTWARE_GENCOMM 0x00000B50
+#define BGE_SOFTWARE_GENCOMM_SIG 0x00000B54
+#define BGE_SOFTWARE_GENCOMM_NICCFG 0x00000B58
+#define BGE_SOFTWARE_GENCOMM_FW 0x00000B78
+#define BGE_SOFTWARE_GENNCOMM_FW_LEN 0x00000B7C
+#define BGE_SOFTWARE_GENNCOMM_FW_DATA 0x00000B80
+#define BGE_SOFTWARE_GENCOMM_END 0x00000FFF
+#define BGE_UNMAPPED 0x00001000
+#define BGE_UNMAPPED_END 0x00001FFF
+#define BGE_DMA_DESCRIPTORS 0x00002000
+#define BGE_DMA_DESCRIPTORS_END 0x00003FFF
+#define BGE_SEND_RING_1_TO_4 0x00004000
+#define BGE_SEND_RING_1_TO_4_END 0x00005FFF
+
+/* Firmware interface */
+#define BGE_FW_DRV_ALIVE 0x00000001
+#define BGE_FW_PAUSE 0x00000002
/* Mappings for internal memory configuration */
-#define BGE_STD_RX_RINGS 0x00006000
-#define BGE_STD_RX_RINGS_END 0x00006FFF
-#define BGE_JUMBO_RX_RINGS 0x00007000
-#define BGE_JUMBO_RX_RINGS_END 0x00007FFF
-#define BGE_BUFFPOOL_1 0x00008000
-#define BGE_BUFFPOOL_1_END 0x0000FFFF
-#define BGE_BUFFPOOL_2 0x00010000 /* or expansion ROM */
-#define BGE_BUFFPOOL_2_END 0x00017FFF
-#define BGE_BUFFPOOL_3 0x00018000 /* or expansion ROM */
-#define BGE_BUFFPOOL_3_END 0x0001FFFF
+#define BGE_STD_RX_RINGS 0x00006000
+#define BGE_STD_RX_RINGS_END 0x00006FFF
+#define BGE_JUMBO_RX_RINGS 0x00007000
+#define BGE_JUMBO_RX_RINGS_END 0x00007FFF
+#define BGE_BUFFPOOL_1 0x00008000
+#define BGE_BUFFPOOL_1_END 0x0000FFFF
+#define BGE_BUFFPOOL_2 0x00010000 /* or expansion ROM */
+#define BGE_BUFFPOOL_2_END 0x00017FFF
+#define BGE_BUFFPOOL_3 0x00018000 /* or expansion ROM */
+#define BGE_BUFFPOOL_3_END 0x0001FFFF
/* Mappings for external SSRAM configurations */
-#define BGE_SEND_RING_5_TO_6 0x00006000
-#define BGE_SEND_RING_5_TO_6_END 0x00006FFF
-#define BGE_SEND_RING_7_TO_8 0x00007000
-#define BGE_SEND_RING_7_TO_8_END 0x00007FFF
-#define BGE_SEND_RING_9_TO_16 0x00008000
-#define BGE_SEND_RING_9_TO_16_END 0x0000BFFF
-#define BGE_EXT_STD_RX_RINGS 0x0000C000
-#define BGE_EXT_STD_RX_RINGS_END 0x0000CFFF
-#define BGE_EXT_JUMBO_RX_RINGS 0x0000D000
-#define BGE_EXT_JUMBO_RX_RINGS_END 0x0000DFFF
-#define BGE_MINI_RX_RINGS 0x0000E000
-#define BGE_MINI_RX_RINGS_END 0x0000FFFF
-#define BGE_AVAIL_REGION1 0x00010000 /* or expansion ROM */
-#define BGE_AVAIL_REGION1_END 0x00017FFF
-#define BGE_AVAIL_REGION2 0x00018000 /* or expansion ROM */
-#define BGE_AVAIL_REGION2_END 0x0001FFFF
-#define BGE_EXT_SSRAM 0x00020000
-#define BGE_EXT_SSRAM_END 0x000FFFFF
+#define BGE_SEND_RING_5_TO_6 0x00006000
+#define BGE_SEND_RING_5_TO_6_END 0x00006FFF
+#define BGE_SEND_RING_7_TO_8 0x00007000
+#define BGE_SEND_RING_7_TO_8_END 0x00007FFF
+#define BGE_SEND_RING_9_TO_16 0x00008000
+#define BGE_SEND_RING_9_TO_16_END 0x0000BFFF
+#define BGE_EXT_STD_RX_RINGS 0x0000C000
+#define BGE_EXT_STD_RX_RINGS_END 0x0000CFFF
+#define BGE_EXT_JUMBO_RX_RINGS 0x0000D000
+#define BGE_EXT_JUMBO_RX_RINGS_END 0x0000DFFF
+#define BGE_MINI_RX_RINGS 0x0000E000
+#define BGE_MINI_RX_RINGS_END 0x0000FFFF
+#define BGE_AVAIL_REGION1 0x00010000 /* or expansion ROM */
+#define BGE_AVAIL_REGION1_END 0x00017FFF
+#define BGE_AVAIL_REGION2 0x00018000 /* or expansion ROM */
+#define BGE_AVAIL_REGION2_END 0x0001FFFF
+#define BGE_EXT_SSRAM 0x00020000
+#define BGE_EXT_SSRAM_END 0x000FFFFF
/*
@@ -128,211 +135,254 @@
/*
* PCI registers defined in the PCI 2.2 spec.
*/
-#define BGE_PCI_VID 0x00
-#define BGE_PCI_DID 0x02
-#define BGE_PCI_CMD 0x04
-#define BGE_PCI_STS 0x06
-#define BGE_PCI_REV 0x08
-#define BGE_PCI_CLASS 0x09
-#define BGE_PCI_CACHESZ 0x0C
-#define BGE_PCI_LATTIMER 0x0D
-#define BGE_PCI_HDRTYPE 0x0E
-#define BGE_PCI_BIST 0x0F
-#define BGE_PCI_BAR0 0x10
-#define BGE_PCI_BAR1 0x14
-#define BGE_PCI_SUBSYS 0x2C
-#define BGE_PCI_SUBVID 0x2E
-#define BGE_PCI_ROMBASE 0x30
-#define BGE_PCI_CAPPTR 0x34
-#define BGE_PCI_INTLINE 0x3C
-#define BGE_PCI_INTPIN 0x3D
-#define BGE_PCI_MINGNT 0x3E
-#define BGE_PCI_MAXLAT 0x3F
-#define BGE_PCI_PCIXCAP 0x40
-#define BGE_PCI_NEXTPTR_PM 0x41
-#define BGE_PCI_PCIX_CMD 0x42
-#define BGE_PCI_PCIX_STS 0x44
-#define BGE_PCI_PWRMGMT_CAPID 0x48
-#define BGE_PCI_NEXTPTR_VPD 0x49
-#define BGE_PCI_PWRMGMT_CAPS 0x4A
-#define BGE_PCI_PWRMGMT_CMD 0x4C
-#define BGE_PCI_PWRMGMT_STS 0x4D
-#define BGE_PCI_PWRMGMT_DATA 0x4F
-#define BGE_PCI_VPD_CAPID 0x50
-#define BGE_PCI_NEXTPTR_MSI 0x51
-#define BGE_PCI_VPD_ADDR 0x52
-#define BGE_PCI_VPD_DATA 0x54
-#define BGE_PCI_MSI_CAPID 0x58
-#define BGE_PCI_NEXTPTR_NONE 0x59
-#define BGE_PCI_MSI_CTL 0x5A
-#define BGE_PCI_MSI_ADDR_HI 0x5C
-#define BGE_PCI_MSI_ADDR_LO 0x60
-#define BGE_PCI_MSI_DATA 0x64
+#define BGE_PCI_VID 0x00
+#define BGE_PCI_DID 0x02
+#define BGE_PCI_CMD 0x04
+#define BGE_PCI_STS 0x06
+#define BGE_PCI_REV 0x08
+#define BGE_PCI_CLASS 0x09
+#define BGE_PCI_CACHESZ 0x0C
+#define BGE_PCI_LATTIMER 0x0D
+#define BGE_PCI_HDRTYPE 0x0E
+#define BGE_PCI_BIST 0x0F
+#define BGE_PCI_BAR0 0x10
+#define BGE_PCI_BAR1 0x14
+#define BGE_PCI_SUBSYS 0x2C
+#define BGE_PCI_SUBVID 0x2E
+#define BGE_PCI_ROMBASE 0x30
+#define BGE_PCI_CAPPTR 0x34
+#define BGE_PCI_INTLINE 0x3C
+#define BGE_PCI_INTPIN 0x3D
+#define BGE_PCI_MINGNT 0x3E
+#define BGE_PCI_MAXLAT 0x3F
+#define BGE_PCI_PCIXCAP 0x40
+#define BGE_PCI_NEXTPTR_PM 0x41
+#define BGE_PCI_PCIX_CMD 0x42
+#define BGE_PCI_PCIX_STS 0x44
+#define BGE_PCI_PWRMGMT_CAPID 0x48
+#define BGE_PCI_NEXTPTR_VPD 0x49
+#define BGE_PCI_PWRMGMT_CAPS 0x4A
+#define BGE_PCI_PWRMGMT_CMD 0x4C
+#define BGE_PCI_PWRMGMT_STS 0x4D
+#define BGE_PCI_PWRMGMT_DATA 0x4F
+#define BGE_PCI_VPD_CAPID 0x50
+#define BGE_PCI_NEXTPTR_MSI 0x51
+#define BGE_PCI_VPD_ADDR 0x52
+#define BGE_PCI_VPD_DATA 0x54
+#define BGE_PCI_MSI_CAPID 0x58
+#define BGE_PCI_NEXTPTR_NONE 0x59
+#define BGE_PCI_MSI_CTL 0x5A
+#define BGE_PCI_MSI_ADDR_HI 0x5C
+#define BGE_PCI_MSI_ADDR_LO 0x60
+#define BGE_PCI_MSI_DATA 0x64
/* PCI MSI. ??? */
-#define BGE_PCIE_CAPID_REG 0xD0
-#define BGE_PCIE_CAPID 0x10
+#define BGE_PCIE_CAPID_REG 0xD0
+#define BGE_PCIE_CAPID 0x10
/*
* PCI registers specific to the BCM570x family.
*/
-#define BGE_PCI_MISC_CTL 0x68
-#define BGE_PCI_DMA_RW_CTL 0x6C
-#define BGE_PCI_PCISTATE 0x70
-#define BGE_PCI_CLKCTL 0x74
-#define BGE_PCI_REG_BASEADDR 0x78
-#define BGE_PCI_MEMWIN_BASEADDR 0x7C
-#define BGE_PCI_REG_DATA 0x80
-#define BGE_PCI_MEMWIN_DATA 0x84
-#define BGE_PCI_MODECTL 0x88
-#define BGE_PCI_MISC_CFG 0x8C
-#define BGE_PCI_MISC_LOCALCTL 0x90
-#define BGE_PCI_UNDI_RX_STD_PRODIDX_HI 0x98
-#define BGE_PCI_UNDI_RX_STD_PRODIDX_LO 0x9C
-#define BGE_PCI_UNDI_RX_RTN_CONSIDX_HI 0xA0
-#define BGE_PCI_UNDI_RX_RTN_CONSIDX_LO 0xA4
-#define BGE_PCI_UNDI_TX_BD_PRODIDX_HI 0xA8
-#define BGE_PCI_UNDI_TX_BD_PRODIDX_LO 0xAC
-#define BGE_PCI_ISR_MBX_HI 0xB0
-#define BGE_PCI_ISR_MBX_LO 0xB4
+#define BGE_PCI_MISC_CTL 0x68
+#define BGE_PCI_DMA_RW_CTL 0x6C
+#define BGE_PCI_PCISTATE 0x70
+#define BGE_PCI_CLKCTL 0x74
+#define BGE_PCI_REG_BASEADDR 0x78
+#define BGE_PCI_MEMWIN_BASEADDR 0x7C
+#define BGE_PCI_REG_DATA 0x80
+#define BGE_PCI_MEMWIN_DATA 0x84
+#define BGE_PCI_MODECTL 0x88
+#define BGE_PCI_MISC_CFG 0x8C
+#define BGE_PCI_MISC_LOCALCTL 0x90
+#define BGE_PCI_UNDI_RX_STD_PRODIDX_HI 0x98
+#define BGE_PCI_UNDI_RX_STD_PRODIDX_LO 0x9C
+#define BGE_PCI_UNDI_RX_RTN_CONSIDX_HI 0xA0
+#define BGE_PCI_UNDI_RX_RTN_CONSIDX_LO 0xA4
+#define BGE_PCI_UNDI_TX_BD_PRODIDX_HI 0xA8
+#define BGE_PCI_UNDI_TX_BD_PRODIDX_LO 0xAC
+#define BGE_PCI_ISR_MBX_HI 0xB0
+#define BGE_PCI_ISR_MBX_LO 0xB4
/* PCI Misc. Host control register */
-#define BGE_PCIMISCCTL_CLEAR_INTA 0x00000001
-#define BGE_PCIMISCCTL_MASK_PCI_INTR 0x00000002
-#define BGE_PCIMISCCTL_ENDIAN_BYTESWAP 0x00000004
-#define BGE_PCIMISCCTL_ENDIAN_WORDSWAP 0x00000008
-#define BGE_PCIMISCCTL_PCISTATE_RW 0x00000010
-#define BGE_PCIMISCCTL_CLOCKCTL_RW 0x00000020
-#define BGE_PCIMISCCTL_REG_WORDSWAP 0x00000040
-#define BGE_PCIMISCCTL_INDIRECT_ACCESS 0x00000080
-#define BGE_PCIMISCCTL_ASICREV 0xFFFF0000
+#define BGE_PCIMISCCTL_CLEAR_INTA 0x00000001
+#define BGE_PCIMISCCTL_MASK_PCI_INTR 0x00000002
+#define BGE_PCIMISCCTL_ENDIAN_BYTESWAP 0x00000004
+#define BGE_PCIMISCCTL_ENDIAN_WORDSWAP 0x00000008
+#define BGE_PCIMISCCTL_PCISTATE_RW 0x00000010
+#define BGE_PCIMISCCTL_CLOCKCTL_RW 0x00000020
+#define BGE_PCIMISCCTL_REG_WORDSWAP 0x00000040
+#define BGE_PCIMISCCTL_INDIRECT_ACCESS 0x00000080
+#define BGE_PCIMISCCTL_ASICREV 0xFFFF0000
-#define BGE_HIF_SWAP_OPTIONS (BGE_PCIMISCCTL_ENDIAN_WORDSWAP)
+#define BGE_HIF_SWAP_OPTIONS (BGE_PCIMISCCTL_ENDIAN_WORDSWAP)
#if BYTE_ORDER == LITTLE_ENDIAN
-#define BGE_DMA_SWAP_OPTIONS \
+#define BGE_DMA_SWAP_OPTIONS \
BGE_MODECTL_WORDSWAP_NONFRAME| \
BGE_MODECTL_BYTESWAP_DATA|BGE_MODECTL_WORDSWAP_DATA
#else
-#define BGE_DMA_SWAP_OPTIONS \
+#define BGE_DMA_SWAP_OPTIONS \
BGE_MODECTL_WORDSWAP_NONFRAME|BGE_MODECTL_BYTESWAP_NONFRAME| \
BGE_MODECTL_BYTESWAP_DATA|BGE_MODECTL_WORDSWAP_DATA
#endif
-#define BGE_INIT \
+#define BGE_INIT \
(BGE_HIF_SWAP_OPTIONS|BGE_PCIMISCCTL_CLEAR_INTA| \
BGE_PCIMISCCTL_MASK_PCI_INTR|BGE_PCIMISCCTL_INDIRECT_ACCESS)
-#define BGE_CHIPID_TIGON_I 0x40000000
-#define BGE_CHIPID_TIGON_II 0x60000000
-#define BGE_CHIPID_BCM5700_B0 0x71000000
-#define BGE_CHIPID_BCM5700_B1 0x71020000
-#define BGE_CHIPID_BCM5700_B2 0x71030000
-#define BGE_CHIPID_BCM5700_ALTIMA 0x71040000
-#define BGE_CHIPID_BCM5700_C0 0x72000000
-#define BGE_CHIPID_BCM5701_A0 0x00000000 /* grrrr */
-#define BGE_CHIPID_BCM5701_B0 0x01000000
-#define BGE_CHIPID_BCM5701_B2 0x01020000
-#define BGE_CHIPID_BCM5701_B5 0x01050000
-#define BGE_CHIPID_BCM5703_A0 0x10000000
-#define BGE_CHIPID_BCM5703_A1 0x10010000
-#define BGE_CHIPID_BCM5703_A2 0x10020000
-#define BGE_CHIPID_BCM5704_A0 0x20000000
-#define BGE_CHIPID_BCM5704_A1 0x20010000
-#define BGE_CHIPID_BCM5704_A2 0x20020000
-#define BGE_CHIPID_BCM5705_A0 0x30000000
-#define BGE_CHIPID_BCM5705_A1 0x30010000
-#define BGE_CHIPID_BCM5705_A2 0x30020000
-#define BGE_CHIPID_BCM5705_A3 0x30030000
-#define BGE_CHIPID_BCM5750_A0 0x40000000
-#define BGE_CHIPID_BCM5750_A1 0x40010000
-#define BGE_CHIPID_BCM5714_A0 0x50000000
+#define BGE_CHIPID_TIGON_I 0x40000000
+#define BGE_CHIPID_TIGON_II 0x60000000
+#define BGE_CHIPID_BCM5700_A0 0x70000000
+#define BGE_CHIPID_BCM5700_A1 0x70010000
+#define BGE_CHIPID_BCM5700_B0 0x71000000
+#define BGE_CHIPID_BCM5700_B1 0x71010000
+#define BGE_CHIPID_BCM5700_B2 0x71020000
+#define BGE_CHIPID_BCM5700_B3 0x71030000
+#define BGE_CHIPID_BCM5700_ALTIMA 0x71040000
+#define BGE_CHIPID_BCM5700_C0 0x72000000
+#define BGE_CHIPID_BCM5701_A0 0x00000000 /* grrrr */
+#define BGE_CHIPID_BCM5701_B0 0x01000000
+#define BGE_CHIPID_BCM5701_B2 0x01020000
+#define BGE_CHIPID_BCM5701_B5 0x01050000
+#define BGE_CHIPID_BCM5703_A0 0x10000000
+#define BGE_CHIPID_BCM5703_A1 0x10010000
+#define BGE_CHIPID_BCM5703_A2 0x10020000
+#define BGE_CHIPID_BCM5703_A3 0x10030000
+#define BGE_CHIPID_BCM5703_B0 0x11000000
+#define BGE_CHIPID_BCM5704_A0 0x20000000
+#define BGE_CHIPID_BCM5704_A1 0x20010000
+#define BGE_CHIPID_BCM5704_A2 0x20020000
+#define BGE_CHIPID_BCM5704_A3 0x20030000
+#define BGE_CHIPID_BCM5704_B0 0x21000000
+#define BGE_CHIPID_BCM5705_A0 0x30000000
+#define BGE_CHIPID_BCM5705_A1 0x30010000
+#define BGE_CHIPID_BCM5705_A2 0x30020000
+#define BGE_CHIPID_BCM5705_A3 0x30030000
+#define BGE_CHIPID_BCM5750_A0 0x40000000
+#define BGE_CHIPID_BCM5750_A1 0x40010000
+#define BGE_CHIPID_BCM5750_A3 0x40030000
+#define BGE_CHIPID_BCM5750_B0 0x41000000
+#define BGE_CHIPID_BCM5750_B1 0x41010000
+#define BGE_CHIPID_BCM5750_C0 0x42000000
+#define BGE_CHIPID_BCM5750_C1 0x42010000
+#define BGE_CHIPID_BCM5750_C2 0x42020000
+#define BGE_CHIPID_BCM5714_A0 0x50000000
+#define BGE_CHIPID_BCM5752_A0 0x60000000
+#define BGE_CHIPID_BCM5752_A1 0x60010000
+#define BGE_CHIPID_BCM5752_A2 0x60020000
+#define BGE_CHIPID_BCM5714_B0 0x80000000
+#define BGE_CHIPID_BCM5714_B3 0x80030000
+#define BGE_CHIPID_BCM5715_A0 0x90000000
+#define BGE_CHIPID_BCM5715_A1 0x90010000
+#define BGE_CHIPID_BCM5715_A3 0x90030000
+#define BGE_CHIPID_BCM5755_A0 0xa0000000
+#define BGE_CHIPID_BCM5755_A1 0xa0010000
+#define BGE_CHIPID_BCM5755_A2 0xa0020000
+#define BGE_CHIPID_BCM5754_A0 0xb0000000
+#define BGE_CHIPID_BCM5754_A1 0xb0010000
+#define BGE_CHIPID_BCM5754_A2 0xb0020000
+#define BGE_CHIPID_BCM5787_A0 0xb0000000
+#define BGE_CHIPID_BCM5787_A1 0xb0010000
+#define BGE_CHIPID_BCM5787_A2 0xb0020000
/* shorthand one */
-#define BGE_ASICREV(x) ((x) >> 28)
-#define BGE_ASICREV_BCM5700 0x07
-#define BGE_ASICREV_BCM5701 0x00
-#define BGE_ASICREV_BCM5703 0x01
-#define BGE_ASICREV_BCM5704 0x02
-#define BGE_ASICREV_BCM5705 0x03
-#define BGE_ASICREV_BCM5750 0x04
-#define BGE_ASICREV_BCM5714 0x05
-#define BGE_ASICREV_BCM5752 0x06
+#define BGE_ASICREV(x) ((x) >> 28)
+#define BGE_ASICREV_BCM5701 0x00
+#define BGE_ASICREV_BCM5703 0x01
+#define BGE_ASICREV_BCM5704 0x02
+#define BGE_ASICREV_BCM5705 0x03
+#define BGE_ASICREV_BCM5750 0x04
+#define BGE_ASICREV_BCM5714_A0 0x05
+#define BGE_ASICREV_BCM5752 0x06
+#define BGE_ASICREV_BCM5700 0x07
+#define BGE_ASICREV_BCM5780 0x08
+#define BGE_ASICREV_BCM5714 0x09
+#define BGE_ASICREV_BCM5755 0x0a
+#define BGE_ASICREV_BCM5754 0x0b
+#define BGE_ASICREV_BCM5787 0x0b
/* chip revisions */
-#define BGE_CHIPREV(x) ((x) >> 24)
-#define BGE_CHIPREV_5700_AX 0x70
-#define BGE_CHIPREV_5700_BX 0x71
-#define BGE_CHIPREV_5700_CX 0x72
-#define BGE_CHIPREV_5701_AX 0x00
+#define BGE_CHIPREV(x) ((x) >> 24)
+#define BGE_CHIPREV_5700_AX 0x70
+#define BGE_CHIPREV_5700_BX 0x71
+#define BGE_CHIPREV_5700_CX 0x72
+#define BGE_CHIPREV_5701_AX 0x00
+#define BGE_CHIPREV_5703_AX 0x10
+#define BGE_CHIPREV_5704_AX 0x20
+#define BGE_CHIPREV_5704_BX 0x21
+#define BGE_CHIPREV_5750_AX 0x40
+#define BGE_CHIPREV_5750_BX 0x41
/* PCI DMA Read/Write Control register */
-#define BGE_PCIDMARWCTL_MINDMA 0x000000FF
-#define BGE_PCIDMARWCTL_RDADRR_BNDRY 0x00000700
-#define BGE_PCIDMARWCTL_WRADDR_BNDRY 0x00003800
-#define BGE_PCIDMARWCTL_ONEDMA_ATONCE 0x00004000
-#define BGE_PCIDMARWCTL_RD_WAT 0x00070000
-# define BGE_PCIDMARWCTL_RD_WAT_SHIFT 16
-#define BGE_PCIDMARWCTL_WR_WAT 0x00380000
-# define BGE_PCIDMARWCTL_WR_WAT_SHIFT 19
-#define BGE_PCIDMARWCTL_USE_MRM 0x00400000
-#define BGE_PCIDMARWCTL_ASRT_ALL_BE 0x00800000
-#define BGE_PCIDMARWCTL_DFLT_PCI_RD_CMD 0x0F000000
-# define BGE_PCIDMA_RWCTL_PCI_RD_CMD_SHIFT 24
-#define BGE_PCIDMARWCTL_DFLT_PCI_WR_CMD 0xF0000000
-# define BGE_PCIDMA_RWCTL_PCI_WR_CMD_SHIFT 28
-
-#define BGE_PCI_READ_BNDRY_DISABLE 0x00000000
-#define BGE_PCI_READ_BNDRY_16BYTES 0x00000100
-#define BGE_PCI_READ_BNDRY_32BYTES 0x00000200
-#define BGE_PCI_READ_BNDRY_64BYTES 0x00000300
-#define BGE_PCI_READ_BNDRY_128BYTES 0x00000400
-#define BGE_PCI_READ_BNDRY_256BYTES 0x00000500
-#define BGE_PCI_READ_BNDRY_512BYTES 0x00000600
-#define BGE_PCI_READ_BNDRY_1024BYTES 0x00000700
-
-#define BGE_PCI_WRITE_BNDRY_DISABLE 0x00000000
-#define BGE_PCI_WRITE_BNDRY_16BYTES 0x00000800
-#define BGE_PCI_WRITE_BNDRY_32BYTES 0x00001000
-#define BGE_PCI_WRITE_BNDRY_64BYTES 0x00001800
-#define BGE_PCI_WRITE_BNDRY_128BYTES 0x00002000
-#define BGE_PCI_WRITE_BNDRY_256BYTES 0x00002800
-#define BGE_PCI_WRITE_BNDRY_512BYTES 0x00003000
-#define BGE_PCI_WRITE_BNDRY_1024BYTES 0x00003800
+#define BGE_PCIDMARWCTL_MINDMA 0x000000FF
+#define BGE_PCIDMARWCTL_RDADRR_BNDRY 0x00000700
+#define BGE_PCIDMARWCTL_WRADDR_BNDRY 0x00003800
+#define BGE_PCIDMARWCTL_ONEDMA_ATONCE 0x0000C000
+#define BGE_PCIDMARWCTL_ONEDMA_ATONCE_GLOBAL 0x00004000
+#define BGE_PCIDMARWCTL_ONEDMA_ATONCE_LOCAL 0x00008000
+#define BGE_PCIDMARWCTL_RD_WAT 0x00070000
+#define BGE_PCIDMARWCTL_WR_WAT 0x00380000
+#define BGE_PCIDMARWCTL_USE_MRM 0x00400000
+#define BGE_PCIDMARWCTL_ASRT_ALL_BE 0x00800000
+#define BGE_PCIDMARWCTL_DFLT_PCI_RD_CMD 0x0F000000
+#define BGE_PCIDMARWCTL_DFLT_PCI_WR_CMD 0xF0000000
+
+#define BGE_PCIDMARWCTL_RD_WAT_SHIFT(x) ((x) << 16)
+#define BGE_PCIDMARWCTL_WR_WAT_SHIFT(x) ((x) << 19)
+#define BGE_PCIDMARWCTL_RD_CMD_SHIFT(x) ((x) << 24)
+#define BGE_PCIDMARWCTL_WR_CMD_SHIFT(x) ((x) << 28)
+
+#define BGE_PCI_READ_BNDRY_DISABLE 0x00000000
+#define BGE_PCI_READ_BNDRY_16BYTES 0x00000100
+#define BGE_PCI_READ_BNDRY_32BYTES 0x00000200
+#define BGE_PCI_READ_BNDRY_64BYTES 0x00000300
+#define BGE_PCI_READ_BNDRY_128BYTES 0x00000400
+#define BGE_PCI_READ_BNDRY_256BYTES 0x00000500
+#define BGE_PCI_READ_BNDRY_512BYTES 0x00000600
+#define BGE_PCI_READ_BNDRY_1024BYTES 0x00000700
+
+#define BGE_PCI_WRITE_BNDRY_DISABLE 0x00000000
+#define BGE_PCI_WRITE_BNDRY_16BYTES 0x00000800
+#define BGE_PCI_WRITE_BNDRY_32BYTES 0x00001000
+#define BGE_PCI_WRITE_BNDRY_64BYTES 0x00001800
+#define BGE_PCI_WRITE_BNDRY_128BYTES 0x00002000
+#define BGE_PCI_WRITE_BNDRY_256BYTES 0x00002800
+#define BGE_PCI_WRITE_BNDRY_512BYTES 0x00003000
+#define BGE_PCI_WRITE_BNDRY_1024BYTES 0x00003800
/*
* PCI state register -- note, this register is read only
* unless the PCISTATE_WR bit of the PCI Misc. Host Control
* register is set.
*/
-#define BGE_PCISTATE_FORCE_RESET 0x00000001
-#define BGE_PCISTATE_INTR_STATE 0x00000002
-#define BGE_PCISTATE_PCI_BUSMODE 0x00000004 /* 1 = PCI, 0 = PCI-X */
-#define BGE_PCISTATE_PCI_BUSSPEED 0x00000008 /* 1 = 33/66, 0 = 66/133 */
-#define BGE_PCISTATE_32BIT_BUS 0x00000010 /* 1 = 32bit, 0 = 64bit */
-#define BGE_PCISTATE_WANT_EXPROM 0x00000020
-#define BGE_PCISTATE_EXPROM_RETRY 0x00000040
-#define BGE_PCISTATE_FLATVIEW_MODE 0x00000100
-#define BGE_PCISTATE_PCI_TGT_RETRY_MAX 0x00000E00
+#define BGE_PCISTATE_FORCE_RESET 0x00000001
+#define BGE_PCISTATE_INTR_STATE 0x00000002
+#define BGE_PCISTATE_PCI_BUSMODE 0x00000004 /* 1 = PCI, 0 = PCI-X */
+#define BGE_PCISTATE_PCI_BUSSPEED 0x00000008 /* 1 = 66/133, 0 = 33/66 */
+#define BGE_PCISTATE_32BIT_BUS 0x00000010 /* 1 = 32bit, 0 = 64bit */
+#define BGE_PCISTATE_WANT_EXPROM 0x00000020
+#define BGE_PCISTATE_EXPROM_RETRY 0x00000040
+#define BGE_PCISTATE_FLATVIEW_MODE 0x00000100
+#define BGE_PCISTATE_PCI_TGT_RETRY_MAX 0x00000E00
/*
* PCI Clock Control register -- note, this register is read only
* unless the CLOCKCTL_RW bit of the PCI Misc. Host Control
* register is set.
*/
-#define BGE_PCICLOCKCTL_DETECTED_SPEED 0x0000000F
-#define BGE_PCICLOCKCTL_M66EN 0x00000080
-#define BGE_PCICLOCKCTL_LOWPWR_CLKMODE 0x00000200
-#define BGE_PCICLOCKCTL_RXCPU_CLK_DIS 0x00000400
-#define BGE_PCICLOCKCTL_TXCPU_CLK_DIS 0x00000800
-#define BGE_PCICLOCKCTL_ALTCLK 0x00001000
-#define BGE_PCICLOCKCTL_ALTCLK_SRC 0x00002000
-#define BGE_PCICLOCKCTL_PCIPLL_DISABLE 0x00004000
-#define BGE_PCICLOCKCTL_SYSPLL_DISABLE 0x00008000
-#define BGE_PCICLOCKCTL_BIST_ENABLE 0x00010000
+#define BGE_PCICLOCKCTL_DETECTED_SPEED 0x0000000F
+#define BGE_PCICLOCKCTL_M66EN 0x00000080
+#define BGE_PCICLOCKCTL_LOWPWR_CLKMODE 0x00000200
+#define BGE_PCICLOCKCTL_RXCPU_CLK_DIS 0x00000400
+#define BGE_PCICLOCKCTL_TXCPU_CLK_DIS 0x00000800
+#define BGE_PCICLOCKCTL_ALTCLK 0x00001000
+#define BGE_PCICLOCKCTL_ALTCLK_SRC 0x00002000
+#define BGE_PCICLOCKCTL_PCIPLL_DISABLE 0x00004000
+#define BGE_PCICLOCKCTL_SYSPLL_DISABLE 0x00008000
+#define BGE_PCICLOCKCTL_BIST_ENABLE 0x00010000
#ifndef PCIM_CMD_MWIEN
-#define PCIM_CMD_MWIEN 0x0010
+#define PCIM_CMD_MWIEN 0x0010
#endif
/*
@@ -342,1401 +392,1402 @@
* first. The NIC will load the mailbox after the lower 32 bit word
* has been updated.
*/
-#define BGE_MBX_IRQ0_HI 0x0200
-#define BGE_MBX_IRQ0_LO 0x0204
-#define BGE_MBX_IRQ1_HI 0x0208
-#define BGE_MBX_IRQ1_LO 0x020C
-#define BGE_MBX_IRQ2_HI 0x0210
-#define BGE_MBX_IRQ2_LO 0x0214
-#define BGE_MBX_IRQ3_HI 0x0218
-#define BGE_MBX_IRQ3_LO 0x021C
-#define BGE_MBX_GEN0_HI 0x0220
-#define BGE_MBX_GEN0_LO 0x0224
-#define BGE_MBX_GEN1_HI 0x0228
-#define BGE_MBX_GEN1_LO 0x022C
-#define BGE_MBX_GEN2_HI 0x0230
-#define BGE_MBX_GEN2_LO 0x0234
-#define BGE_MBX_GEN3_HI 0x0228
-#define BGE_MBX_GEN3_LO 0x022C
-#define BGE_MBX_GEN4_HI 0x0240
-#define BGE_MBX_GEN4_LO 0x0244
-#define BGE_MBX_GEN5_HI 0x0248
-#define BGE_MBX_GEN5_LO 0x024C
-#define BGE_MBX_GEN6_HI 0x0250
-#define BGE_MBX_GEN6_LO 0x0254
-#define BGE_MBX_GEN7_HI 0x0258
-#define BGE_MBX_GEN7_LO 0x025C
-#define BGE_MBX_RELOAD_STATS_HI 0x0260
-#define BGE_MBX_RELOAD_STATS_LO 0x0264
-#define BGE_MBX_RX_STD_PROD_HI 0x0268
-#define BGE_MBX_RX_STD_PROD_LO 0x026C
-#define BGE_MBX_RX_JUMBO_PROD_HI 0x0270
-#define BGE_MBX_RX_JUMBO_PROD_LO 0x0274
-#define BGE_MBX_RX_MINI_PROD_HI 0x0278
-#define BGE_MBX_RX_MINI_PROD_LO 0x027C
-#define BGE_MBX_RX_CONS0_HI 0x0280
-#define BGE_MBX_RX_CONS0_LO 0x0284
-#define BGE_MBX_RX_CONS1_HI 0x0288
-#define BGE_MBX_RX_CONS1_LO 0x028C
-#define BGE_MBX_RX_CONS2_HI 0x0290
-#define BGE_MBX_RX_CONS2_LO 0x0294
-#define BGE_MBX_RX_CONS3_HI 0x0298
-#define BGE_MBX_RX_CONS3_LO 0x029C
-#define BGE_MBX_RX_CONS4_HI 0x02A0
-#define BGE_MBX_RX_CONS4_LO 0x02A4
-#define BGE_MBX_RX_CONS5_HI 0x02A8
-#define BGE_MBX_RX_CONS5_LO 0x02AC
-#define BGE_MBX_RX_CONS6_HI 0x02B0
-#define BGE_MBX_RX_CONS6_LO 0x02B4
-#define BGE_MBX_RX_CONS7_HI 0x02B8
-#define BGE_MBX_RX_CONS7_LO 0x02BC
-#define BGE_MBX_RX_CONS8_HI 0x02C0
-#define BGE_MBX_RX_CONS8_LO 0x02C4
-#define BGE_MBX_RX_CONS9_HI 0x02C8
-#define BGE_MBX_RX_CONS9_LO 0x02CC
-#define BGE_MBX_RX_CONS10_HI 0x02D0
-#define BGE_MBX_RX_CONS10_LO 0x02D4
-#define BGE_MBX_RX_CONS11_HI 0x02D8
-#define BGE_MBX_RX_CONS11_LO 0x02DC
-#define BGE_MBX_RX_CONS12_HI 0x02E0
-#define BGE_MBX_RX_CONS12_LO 0x02E4
-#define BGE_MBX_RX_CONS13_HI 0x02E8
-#define BGE_MBX_RX_CONS13_LO 0x02EC
-#define BGE_MBX_RX_CONS14_HI 0x02F0
-#define BGE_MBX_RX_CONS14_LO 0x02F4
-#define BGE_MBX_RX_CONS15_HI 0x02F8
-#define BGE_MBX_RX_CONS15_LO 0x02FC
-#define BGE_MBX_TX_HOST_PROD0_HI 0x0300
-#define BGE_MBX_TX_HOST_PROD0_LO 0x0304
-#define BGE_MBX_TX_HOST_PROD1_HI 0x0308
-#define BGE_MBX_TX_HOST_PROD1_LO 0x030C
-#define BGE_MBX_TX_HOST_PROD2_HI 0x0310
-#define BGE_MBX_TX_HOST_PROD2_LO 0x0314
-#define BGE_MBX_TX_HOST_PROD3_HI 0x0318
-#define BGE_MBX_TX_HOST_PROD3_LO 0x031C
-#define BGE_MBX_TX_HOST_PROD4_HI 0x0320
-#define BGE_MBX_TX_HOST_PROD4_LO 0x0324
-#define BGE_MBX_TX_HOST_PROD5_HI 0x0328
-#define BGE_MBX_TX_HOST_PROD5_LO 0x032C
-#define BGE_MBX_TX_HOST_PROD6_HI 0x0330
-#define BGE_MBX_TX_HOST_PROD6_LO 0x0334
-#define BGE_MBX_TX_HOST_PROD7_HI 0x0338
-#define BGE_MBX_TX_HOST_PROD7_LO 0x033C
-#define BGE_MBX_TX_HOST_PROD8_HI 0x0340
-#define BGE_MBX_TX_HOST_PROD8_LO 0x0344
-#define BGE_MBX_TX_HOST_PROD9_HI 0x0348
-#define BGE_MBX_TX_HOST_PROD9_LO 0x034C
-#define BGE_MBX_TX_HOST_PROD10_HI 0x0350
-#define BGE_MBX_TX_HOST_PROD10_LO 0x0354
-#define BGE_MBX_TX_HOST_PROD11_HI 0x0358
-#define BGE_MBX_TX_HOST_PROD11_LO 0x035C
-#define BGE_MBX_TX_HOST_PROD12_HI 0x0360
-#define BGE_MBX_TX_HOST_PROD12_LO 0x0364
-#define BGE_MBX_TX_HOST_PROD13_HI 0x0368
-#define BGE_MBX_TX_HOST_PROD13_LO 0x036C
-#define BGE_MBX_TX_HOST_PROD14_HI 0x0370
-#define BGE_MBX_TX_HOST_PROD14_LO 0x0374
-#define BGE_MBX_TX_HOST_PROD15_HI 0x0378
-#define BGE_MBX_TX_HOST_PROD15_LO 0x037C
-#define BGE_MBX_TX_NIC_PROD0_HI 0x0380
-#define BGE_MBX_TX_NIC_PROD0_LO 0x0384
-#define BGE_MBX_TX_NIC_PROD1_HI 0x0388
-#define BGE_MBX_TX_NIC_PROD1_LO 0x038C
-#define BGE_MBX_TX_NIC_PROD2_HI 0x0390
-#define BGE_MBX_TX_NIC_PROD2_LO 0x0394
-#define BGE_MBX_TX_NIC_PROD3_HI 0x0398
-#define BGE_MBX_TX_NIC_PROD3_LO 0x039C
-#define BGE_MBX_TX_NIC_PROD4_HI 0x03A0
-#define BGE_MBX_TX_NIC_PROD4_LO 0x03A4
-#define BGE_MBX_TX_NIC_PROD5_HI 0x03A8
-#define BGE_MBX_TX_NIC_PROD5_LO 0x03AC
-#define BGE_MBX_TX_NIC_PROD6_HI 0x03B0
-#define BGE_MBX_TX_NIC_PROD6_LO 0x03B4
-#define BGE_MBX_TX_NIC_PROD7_HI 0x03B8
-#define BGE_MBX_TX_NIC_PROD7_LO 0x03BC
-#define BGE_MBX_TX_NIC_PROD8_HI 0x03C0
-#define BGE_MBX_TX_NIC_PROD8_LO 0x03C4
-#define BGE_MBX_TX_NIC_PROD9_HI 0x03C8
-#define BGE_MBX_TX_NIC_PROD9_LO 0x03CC
-#define BGE_MBX_TX_NIC_PROD10_HI 0x03D0
-#define BGE_MBX_TX_NIC_PROD10_LO 0x03D4
-#define BGE_MBX_TX_NIC_PROD11_HI 0x03D8
-#define BGE_MBX_TX_NIC_PROD11_LO 0x03DC
-#define BGE_MBX_TX_NIC_PROD12_HI 0x03E0
-#define BGE_MBX_TX_NIC_PROD12_LO 0x03E4
-#define BGE_MBX_TX_NIC_PROD13_HI 0x03E8
-#define BGE_MBX_TX_NIC_PROD13_LO 0x03EC
-#define BGE_MBX_TX_NIC_PROD14_HI 0x03F0
-#define BGE_MBX_TX_NIC_PROD14_LO 0x03F4
-#define BGE_MBX_TX_NIC_PROD15_HI 0x03F8
-#define BGE_MBX_TX_NIC_PROD15_LO 0x03FC
-
-#define BGE_TX_RINGS_MAX 4
-#define BGE_TX_RINGS_EXTSSRAM_MAX 16
-#define BGE_RX_RINGS_MAX 16
+#define BGE_MBX_IRQ0_HI 0x0200
+#define BGE_MBX_IRQ0_LO 0x0204
+#define BGE_MBX_IRQ1_HI 0x0208
+#define BGE_MBX_IRQ1_LO 0x020C
+#define BGE_MBX_IRQ2_HI 0x0210
+#define BGE_MBX_IRQ2_LO 0x0214
+#define BGE_MBX_IRQ3_HI 0x0218
+#define BGE_MBX_IRQ3_LO 0x021C
+#define BGE_MBX_GEN0_HI 0x0220
+#define BGE_MBX_GEN0_LO 0x0224
+#define BGE_MBX_GEN1_HI 0x0228
+#define BGE_MBX_GEN1_LO 0x022C
+#define BGE_MBX_GEN2_HI 0x0230
+#define BGE_MBX_GEN2_LO 0x0234
+#define BGE_MBX_GEN3_HI 0x0228
+#define BGE_MBX_GEN3_LO 0x022C
+#define BGE_MBX_GEN4_HI 0x0240
+#define BGE_MBX_GEN4_LO 0x0244
+#define BGE_MBX_GEN5_HI 0x0248
+#define BGE_MBX_GEN5_LO 0x024C
+#define BGE_MBX_GEN6_HI 0x0250
+#define BGE_MBX_GEN6_LO 0x0254
+#define BGE_MBX_GEN7_HI 0x0258
+#define BGE_MBX_GEN7_LO 0x025C
+#define BGE_MBX_RELOAD_STATS_HI 0x0260
+#define BGE_MBX_RELOAD_STATS_LO 0x0264
+#define BGE_MBX_RX_STD_PROD_HI 0x0268
+#define BGE_MBX_RX_STD_PROD_LO 0x026C
+#define BGE_MBX_RX_JUMBO_PROD_HI 0x0270
+#define BGE_MBX_RX_JUMBO_PROD_LO 0x0274
+#define BGE_MBX_RX_MINI_PROD_HI 0x0278
+#define BGE_MBX_RX_MINI_PROD_LO 0x027C
+#define BGE_MBX_RX_CONS0_HI 0x0280
+#define BGE_MBX_RX_CONS0_LO 0x0284
+#define BGE_MBX_RX_CONS1_HI 0x0288
+#define BGE_MBX_RX_CONS1_LO 0x028C
+#define BGE_MBX_RX_CONS2_HI 0x0290
+#define BGE_MBX_RX_CONS2_LO 0x0294
+#define BGE_MBX_RX_CONS3_HI 0x0298
+#define BGE_MBX_RX_CONS3_LO 0x029C
+#define BGE_MBX_RX_CONS4_HI 0x02A0
+#define BGE_MBX_RX_CONS4_LO 0x02A4
+#define BGE_MBX_RX_CONS5_HI 0x02A8
+#define BGE_MBX_RX_CONS5_LO 0x02AC
+#define BGE_MBX_RX_CONS6_HI 0x02B0
+#define BGE_MBX_RX_CONS6_LO 0x02B4
+#define BGE_MBX_RX_CONS7_HI 0x02B8
+#define BGE_MBX_RX_CONS7_LO 0x02BC
+#define BGE_MBX_RX_CONS8_HI 0x02C0
+#define BGE_MBX_RX_CONS8_LO 0x02C4
+#define BGE_MBX_RX_CONS9_HI 0x02C8
+#define BGE_MBX_RX_CONS9_LO 0x02CC
+#define BGE_MBX_RX_CONS10_HI 0x02D0
+#define BGE_MBX_RX_CONS10_LO 0x02D4
+#define BGE_MBX_RX_CONS11_HI 0x02D8
+#define BGE_MBX_RX_CONS11_LO 0x02DC
+#define BGE_MBX_RX_CONS12_HI 0x02E0
+#define BGE_MBX_RX_CONS12_LO 0x02E4
+#define BGE_MBX_RX_CONS13_HI 0x02E8
+#define BGE_MBX_RX_CONS13_LO 0x02EC
+#define BGE_MBX_RX_CONS14_HI 0x02F0
+#define BGE_MBX_RX_CONS14_LO 0x02F4
+#define BGE_MBX_RX_CONS15_HI 0x02F8
+#define BGE_MBX_RX_CONS15_LO 0x02FC
+#define BGE_MBX_TX_HOST_PROD0_HI 0x0300
+#define BGE_MBX_TX_HOST_PROD0_LO 0x0304
+#define BGE_MBX_TX_HOST_PROD1_HI 0x0308
+#define BGE_MBX_TX_HOST_PROD1_LO 0x030C
+#define BGE_MBX_TX_HOST_PROD2_HI 0x0310
+#define BGE_MBX_TX_HOST_PROD2_LO 0x0314
+#define BGE_MBX_TX_HOST_PROD3_HI 0x0318
+#define BGE_MBX_TX_HOST_PROD3_LO 0x031C
+#define BGE_MBX_TX_HOST_PROD4_HI 0x0320
+#define BGE_MBX_TX_HOST_PROD4_LO 0x0324
+#define BGE_MBX_TX_HOST_PROD5_HI 0x0328
+#define BGE_MBX_TX_HOST_PROD5_LO 0x032C
+#define BGE_MBX_TX_HOST_PROD6_HI 0x0330
+#define BGE_MBX_TX_HOST_PROD6_LO 0x0334
+#define BGE_MBX_TX_HOST_PROD7_HI 0x0338
+#define BGE_MBX_TX_HOST_PROD7_LO 0x033C
+#define BGE_MBX_TX_HOST_PROD8_HI 0x0340
+#define BGE_MBX_TX_HOST_PROD8_LO 0x0344
+#define BGE_MBX_TX_HOST_PROD9_HI 0x0348
+#define BGE_MBX_TX_HOST_PROD9_LO 0x034C
+#define BGE_MBX_TX_HOST_PROD10_HI 0x0350
+#define BGE_MBX_TX_HOST_PROD10_LO 0x0354
+#define BGE_MBX_TX_HOST_PROD11_HI 0x0358
+#define BGE_MBX_TX_HOST_PROD11_LO 0x035C
+#define BGE_MBX_TX_HOST_PROD12_HI 0x0360
+#define BGE_MBX_TX_HOST_PROD12_LO 0x0364
+#define BGE_MBX_TX_HOST_PROD13_HI 0x0368
+#define BGE_MBX_TX_HOST_PROD13_LO 0x036C
+#define BGE_MBX_TX_HOST_PROD14_HI 0x0370
+#define BGE_MBX_TX_HOST_PROD14_LO 0x0374
+#define BGE_MBX_TX_HOST_PROD15_HI 0x0378
+#define BGE_MBX_TX_HOST_PROD15_LO 0x037C
+#define BGE_MBX_TX_NIC_PROD0_HI 0x0380
+#define BGE_MBX_TX_NIC_PROD0_LO 0x0384
+#define BGE_MBX_TX_NIC_PROD1_HI 0x0388
+#define BGE_MBX_TX_NIC_PROD1_LO 0x038C
+#define BGE_MBX_TX_NIC_PROD2_HI 0x0390
+#define BGE_MBX_TX_NIC_PROD2_LO 0x0394
+#define BGE_MBX_TX_NIC_PROD3_HI 0x0398
+#define BGE_MBX_TX_NIC_PROD3_LO 0x039C
+#define BGE_MBX_TX_NIC_PROD4_HI 0x03A0
+#define BGE_MBX_TX_NIC_PROD4_LO 0x03A4
+#define BGE_MBX_TX_NIC_PROD5_HI 0x03A8
+#define BGE_MBX_TX_NIC_PROD5_LO 0x03AC
+#define BGE_MBX_TX_NIC_PROD6_HI 0x03B0
+#define BGE_MBX_TX_NIC_PROD6_LO 0x03B4
+#define BGE_MBX_TX_NIC_PROD7_HI 0x03B8
+#define BGE_MBX_TX_NIC_PROD7_LO 0x03BC
+#define BGE_MBX_TX_NIC_PROD8_HI 0x03C0
+#define BGE_MBX_TX_NIC_PROD8_LO 0x03C4
+#define BGE_MBX_TX_NIC_PROD9_HI 0x03C8
+#define BGE_MBX_TX_NIC_PROD9_LO 0x03CC
+#define BGE_MBX_TX_NIC_PROD10_HI 0x03D0
+#define BGE_MBX_TX_NIC_PROD10_LO 0x03D4
+#define BGE_MBX_TX_NIC_PROD11_HI 0x03D8
+#define BGE_MBX_TX_NIC_PROD11_LO 0x03DC
+#define BGE_MBX_TX_NIC_PROD12_HI 0x03E0
+#define BGE_MBX_TX_NIC_PROD12_LO 0x03E4
+#define BGE_MBX_TX_NIC_PROD13_HI 0x03E8
+#define BGE_MBX_TX_NIC_PROD13_LO 0x03EC
+#define BGE_MBX_TX_NIC_PROD14_HI 0x03F0
+#define BGE_MBX_TX_NIC_PROD14_LO 0x03F4
+#define BGE_MBX_TX_NIC_PROD15_HI 0x03F8
+#define BGE_MBX_TX_NIC_PROD15_LO 0x03FC
+
+#define BGE_TX_RINGS_MAX 4
+#define BGE_TX_RINGS_EXTSSRAM_MAX 16
+#define BGE_RX_RINGS_MAX 16
/* Ethernet MAC control registers */
-#define BGE_MAC_MODE 0x0400
-#define BGE_MAC_STS 0x0404
-#define BGE_MAC_EVT_ENB 0x0408
-#define BGE_MAC_LED_CTL 0x040C
-#define BGE_MAC_ADDR1_LO 0x0410
-#define BGE_MAC_ADDR1_HI 0x0414
-#define BGE_MAC_ADDR2_LO 0x0418
-#define BGE_MAC_ADDR2_HI 0x041C
-#define BGE_MAC_ADDR3_LO 0x0420
-#define BGE_MAC_ADDR3_HI 0x0424
-#define BGE_MAC_ADDR4_LO 0x0428
-#define BGE_MAC_ADDR4_HI 0x042C
-#define BGE_WOL_PATPTR 0x0430
-#define BGE_WOL_PATCFG 0x0434
-#define BGE_TX_RANDOM_BACKOFF 0x0438
-#define BGE_RX_MTU 0x043C
-#define BGE_GBIT_PCS_TEST 0x0440
-#define BGE_TX_TBI_AUTONEG 0x0444
-#define BGE_RX_TBI_AUTONEG 0x0448
-#define BGE_MI_COMM 0x044C
-#define BGE_MI_STS 0x0450
-#define BGE_MI_MODE 0x0454
-#define BGE_AUTOPOLL_STS 0x0458
-#define BGE_TX_MODE 0x045C
-#define BGE_TX_STS 0x0460
-#define BGE_TX_LENGTHS 0x0464
-#define BGE_RX_MODE 0x0468
-#define BGE_RX_STS 0x046C
-#define BGE_MAR0 0x0470
-#define BGE_MAR1 0x0474
-#define BGE_MAR2 0x0478
-#define BGE_MAR3 0x047C
-#define BGE_RX_BD_RULES_CTL0 0x0480
-#define BGE_RX_BD_RULES_MASKVAL0 0x0484
-#define BGE_RX_BD_RULES_CTL1 0x0488
-#define BGE_RX_BD_RULES_MASKVAL1 0x048C
-#define BGE_RX_BD_RULES_CTL2 0x0490
-#define BGE_RX_BD_RULES_MASKVAL2 0x0494
-#define BGE_RX_BD_RULES_CTL3 0x0498
-#define BGE_RX_BD_RULES_MASKVAL3 0x049C
-#define BGE_RX_BD_RULES_CTL4 0x04A0
-#define BGE_RX_BD_RULES_MASKVAL4 0x04A4
-#define BGE_RX_BD_RULES_CTL5 0x04A8
-#define BGE_RX_BD_RULES_MASKVAL5 0x04AC
-#define BGE_RX_BD_RULES_CTL6 0x04B0
-#define BGE_RX_BD_RULES_MASKVAL6 0x04B4
-#define BGE_RX_BD_RULES_CTL7 0x04B8
-#define BGE_RX_BD_RULES_MASKVAL7 0x04BC
-#define BGE_RX_BD_RULES_CTL8 0x04C0
-#define BGE_RX_BD_RULES_MASKVAL8 0x04C4
-#define BGE_RX_BD_RULES_CTL9 0x04C8
-#define BGE_RX_BD_RULES_MASKVAL9 0x04CC
-#define BGE_RX_BD_RULES_CTL10 0x04D0
-#define BGE_RX_BD_RULES_MASKVAL10 0x04D4
-#define BGE_RX_BD_RULES_CTL11 0x04D8
-#define BGE_RX_BD_RULES_MASKVAL11 0x04DC
-#define BGE_RX_BD_RULES_CTL12 0x04E0
-#define BGE_RX_BD_RULES_MASKVAL12 0x04E4
-#define BGE_RX_BD_RULES_CTL13 0x04E8
-#define BGE_RX_BD_RULES_MASKVAL13 0x04EC
-#define BGE_RX_BD_RULES_CTL14 0x04F0
-#define BGE_RX_BD_RULES_MASKVAL14 0x04F4
-#define BGE_RX_BD_RULES_CTL15 0x04F8
-#define BGE_RX_BD_RULES_MASKVAL15 0x04FC
-#define BGE_RX_RULES_CFG 0x0500
-#define BGE_SERDES_CFG 0x0590
-#define BGE_SERDES_STS 0x0594
-#define BGE_SGDIG_CFG 0x05B0
-#define BGE_SGDIG_STS 0x05B4
-#define BGE_RX_STATS 0x0800
-#define BGE_TX_STATS 0x0880
+#define BGE_MAC_MODE 0x0400
+#define BGE_MAC_STS 0x0404
+#define BGE_MAC_EVT_ENB 0x0408
+#define BGE_MAC_LED_CTL 0x040C
+#define BGE_MAC_ADDR1_LO 0x0410
+#define BGE_MAC_ADDR1_HI 0x0414
+#define BGE_MAC_ADDR2_LO 0x0418
+#define BGE_MAC_ADDR2_HI 0x041C
+#define BGE_MAC_ADDR3_LO 0x0420
+#define BGE_MAC_ADDR3_HI 0x0424
+#define BGE_MAC_ADDR4_LO 0x0428
+#define BGE_MAC_ADDR4_HI 0x042C
+#define BGE_WOL_PATPTR 0x0430
+#define BGE_WOL_PATCFG 0x0434
+#define BGE_TX_RANDOM_BACKOFF 0x0438
+#define BGE_RX_MTU 0x043C
+#define BGE_GBIT_PCS_TEST 0x0440
+#define BGE_TX_TBI_AUTONEG 0x0444
+#define BGE_RX_TBI_AUTONEG 0x0448
+#define BGE_MI_COMM 0x044C
+#define BGE_MI_STS 0x0450
+#define BGE_MI_MODE 0x0454
+#define BGE_AUTOPOLL_STS 0x0458
+#define BGE_TX_MODE 0x045C
+#define BGE_TX_STS 0x0460
+#define BGE_TX_LENGTHS 0x0464
+#define BGE_RX_MODE 0x0468
+#define BGE_RX_STS 0x046C
+#define BGE_MAR0 0x0470
+#define BGE_MAR1 0x0474
+#define BGE_MAR2 0x0478
+#define BGE_MAR3 0x047C
+#define BGE_RX_BD_RULES_CTL0 0x0480
+#define BGE_RX_BD_RULES_MASKVAL0 0x0484
+#define BGE_RX_BD_RULES_CTL1 0x0488
+#define BGE_RX_BD_RULES_MASKVAL1 0x048C
+#define BGE_RX_BD_RULES_CTL2 0x0490
+#define BGE_RX_BD_RULES_MASKVAL2 0x0494
+#define BGE_RX_BD_RULES_CTL3 0x0498
+#define BGE_RX_BD_RULES_MASKVAL3 0x049C
+#define BGE_RX_BD_RULES_CTL4 0x04A0
+#define BGE_RX_BD_RULES_MASKVAL4 0x04A4
+#define BGE_RX_BD_RULES_CTL5 0x04A8
+#define BGE_RX_BD_RULES_MASKVAL5 0x04AC
+#define BGE_RX_BD_RULES_CTL6 0x04B0
+#define BGE_RX_BD_RULES_MASKVAL6 0x04B4
+#define BGE_RX_BD_RULES_CTL7 0x04B8
+#define BGE_RX_BD_RULES_MASKVAL7 0x04BC
+#define BGE_RX_BD_RULES_CTL8 0x04C0
+#define BGE_RX_BD_RULES_MASKVAL8 0x04C4
+#define BGE_RX_BD_RULES_CTL9 0x04C8
+#define BGE_RX_BD_RULES_MASKVAL9 0x04CC
+#define BGE_RX_BD_RULES_CTL10 0x04D0
+#define BGE_RX_BD_RULES_MASKVAL10 0x04D4
+#define BGE_RX_BD_RULES_CTL11 0x04D8
+#define BGE_RX_BD_RULES_MASKVAL11 0x04DC
+#define BGE_RX_BD_RULES_CTL12 0x04E0
+#define BGE_RX_BD_RULES_MASKVAL12 0x04E4
+#define BGE_RX_BD_RULES_CTL13 0x04E8
+#define BGE_RX_BD_RULES_MASKVAL13 0x04EC
+#define BGE_RX_BD_RULES_CTL14 0x04F0
+#define BGE_RX_BD_RULES_MASKVAL14 0x04F4
+#define BGE_RX_BD_RULES_CTL15 0x04F8
+#define BGE_RX_BD_RULES_MASKVAL15 0x04FC
+#define BGE_RX_RULES_CFG 0x0500
+#define BGE_SERDES_CFG 0x0590
+#define BGE_SERDES_STS 0x0594
+#define BGE_SGDIG_CFG 0x05B0
+#define BGE_SGDIG_STS 0x05B4
+#define BGE_MAC_STATS 0x0800
/* Ethernet MAC Mode register */
-#define BGE_MACMODE_RESET 0x00000001
-#define BGE_MACMODE_HALF_DUPLEX 0x00000002
-#define BGE_MACMODE_PORTMODE 0x0000000C
-#define BGE_MACMODE_LOOPBACK 0x00000010
-#define BGE_MACMODE_RX_TAGGEDPKT 0x00000080
-#define BGE_MACMODE_TX_BURST_ENB 0x00000100
-#define BGE_MACMODE_MAX_DEFER 0x00000200
-#define BGE_MACMODE_LINK_POLARITY 0x00000400
-#define BGE_MACMODE_RX_STATS_ENB 0x00000800
-#define BGE_MACMODE_RX_STATS_CLEAR 0x00001000
-#define BGE_MACMODE_RX_STATS_FLUSH 0x00002000
-#define BGE_MACMODE_TX_STATS_ENB 0x00004000
-#define BGE_MACMODE_TX_STATS_CLEAR 0x00008000
-#define BGE_MACMODE_TX_STATS_FLUSH 0x00010000
-#define BGE_MACMODE_TBI_SEND_CFGS 0x00020000
-#define BGE_MACMODE_MAGIC_PKT_ENB 0x00040000
-#define BGE_MACMODE_ACPI_PWRON_ENB 0x00080000
-#define BGE_MACMODE_MIP_ENB 0x00100000
-#define BGE_MACMODE_TXDMA_ENB 0x00200000
-#define BGE_MACMODE_RXDMA_ENB 0x00400000
-#define BGE_MACMODE_FRMHDR_DMA_ENB 0x00800000
-
-#define BGE_PORTMODE_NONE 0x00000000
-#define BGE_PORTMODE_MII 0x00000004
-#define BGE_PORTMODE_GMII 0x00000008
-#define BGE_PORTMODE_TBI 0x0000000C
+#define BGE_MACMODE_RESET 0x00000001
+#define BGE_MACMODE_HALF_DUPLEX 0x00000002
+#define BGE_MACMODE_PORTMODE 0x0000000C
+#define BGE_MACMODE_LOOPBACK 0x00000010
+#define BGE_MACMODE_RX_TAGGEDPKT 0x00000080
+#define BGE_MACMODE_TX_BURST_ENB 0x00000100
+#define BGE_MACMODE_MAX_DEFER 0x00000200
+#define BGE_MACMODE_LINK_POLARITY 0x00000400
+#define BGE_MACMODE_RX_STATS_ENB 0x00000800
+#define BGE_MACMODE_RX_STATS_CLEAR 0x00001000
+#define BGE_MACMODE_RX_STATS_FLUSH 0x00002000
+#define BGE_MACMODE_TX_STATS_ENB 0x00004000
+#define BGE_MACMODE_TX_STATS_CLEAR 0x00008000
+#define BGE_MACMODE_TX_STATS_FLUSH 0x00010000
+#define BGE_MACMODE_TBI_SEND_CFGS 0x00020000
+#define BGE_MACMODE_MAGIC_PKT_ENB 0x00040000
+#define BGE_MACMODE_ACPI_PWRON_ENB 0x00080000
+#define BGE_MACMODE_MIP_ENB 0x00100000
+#define BGE_MACMODE_TXDMA_ENB 0x00200000
+#define BGE_MACMODE_RXDMA_ENB 0x00400000
+#define BGE_MACMODE_FRMHDR_DMA_ENB 0x00800000
+
+#define BGE_PORTMODE_NONE 0x00000000
+#define BGE_PORTMODE_MII 0x00000004
+#define BGE_PORTMODE_GMII 0x00000008
+#define BGE_PORTMODE_TBI 0x0000000C
/* MAC Status register */
-#define BGE_MACSTAT_TBI_PCS_SYNCHED 0x00000001
-#define BGE_MACSTAT_TBI_SIGNAL_DETECT 0x00000002
-#define BGE_MACSTAT_RX_CFG 0x00000004
-#define BGE_MACSTAT_CFG_CHANGED 0x00000008
-#define BGE_MACSTAT_SYNC_CHANGED 0x00000010
-#define BGE_MACSTAT_PORT_DECODE_ERROR 0x00000400
-#define BGE_MACSTAT_LINK_CHANGED 0x00001000
-#define BGE_MACSTAT_MI_COMPLETE 0x00400000
-#define BGE_MACSTAT_MI_INTERRUPT 0x00800000
-#define BGE_MACSTAT_AUTOPOLL_ERROR 0x01000000
-#define BGE_MACSTAT_ODI_ERROR 0x02000000
-#define BGE_MACSTAT_RXSTAT_OFLOW 0x04000000
-#define BGE_MACSTAT_TXSTAT_OFLOW 0x08000000
+#define BGE_MACSTAT_TBI_PCS_SYNCHED 0x00000001
+#define BGE_MACSTAT_TBI_SIGNAL_DETECT 0x00000002
+#define BGE_MACSTAT_RX_CFG 0x00000004
+#define BGE_MACSTAT_CFG_CHANGED 0x00000008
+#define BGE_MACSTAT_SYNC_CHANGED 0x00000010
+#define BGE_MACSTAT_PORT_DECODE_ERROR 0x00000400
+#define BGE_MACSTAT_LINK_CHANGED 0x00001000
+#define BGE_MACSTAT_MI_COMPLETE 0x00400000
+#define BGE_MACSTAT_MI_INTERRUPT 0x00800000
+#define BGE_MACSTAT_AUTOPOLL_ERROR 0x01000000
+#define BGE_MACSTAT_ODI_ERROR 0x02000000
+#define BGE_MACSTAT_RXSTAT_OFLOW 0x04000000
+#define BGE_MACSTAT_TXSTAT_OFLOW 0x08000000
/* MAC Event Enable Register */
-#define BGE_EVTENB_PORT_DECODE_ERROR 0x00000400
-#define BGE_EVTENB_LINK_CHANGED 0x00001000
-#define BGE_EVTENB_MI_COMPLETE 0x00400000
-#define BGE_EVTENB_MI_INTERRUPT 0x00800000
-#define BGE_EVTENB_AUTOPOLL_ERROR 0x01000000
-#define BGE_EVTENB_ODI_ERROR 0x02000000
-#define BGE_EVTENB_RXSTAT_OFLOW 0x04000000
-#define BGE_EVTENB_TXSTAT_OFLOW 0x08000000
+#define BGE_EVTENB_PORT_DECODE_ERROR 0x00000400
+#define BGE_EVTENB_LINK_CHANGED 0x00001000
+#define BGE_EVTENB_MI_COMPLETE 0x00400000
+#define BGE_EVTENB_MI_INTERRUPT 0x00800000
+#define BGE_EVTENB_AUTOPOLL_ERROR 0x01000000
+#define BGE_EVTENB_ODI_ERROR 0x02000000
+#define BGE_EVTENB_RXSTAT_OFLOW 0x04000000
+#define BGE_EVTENB_TXSTAT_OFLOW 0x08000000
/* LED Control Register */
-#define BGE_LEDCTL_LINKLED_OVERRIDE 0x00000001
-#define BGE_LEDCTL_1000MBPS_LED 0x00000002
-#define BGE_LEDCTL_100MBPS_LED 0x00000004
-#define BGE_LEDCTL_10MBPS_LED 0x00000008
-#define BGE_LEDCTL_TRAFLED_OVERRIDE 0x00000010
-#define BGE_LEDCTL_TRAFLED_BLINK 0x00000020
-#define BGE_LEDCTL_TREFLED_BLINK_2 0x00000040
-#define BGE_LEDCTL_1000MBPS_STS 0x00000080
-#define BGE_LEDCTL_100MBPS_STS 0x00000100
-#define BGE_LEDCTL_10MBPS_STS 0x00000200
-#define BGE_LEDCTL_TRADLED_STS 0x00000400
-#define BGE_LEDCTL_BLINKPERIOD 0x7FF80000
-#define BGE_LEDCTL_BLINKPERIOD_OVERRIDE 0x80000000
+#define BGE_LEDCTL_LINKLED_OVERRIDE 0x00000001
+#define BGE_LEDCTL_1000MBPS_LED 0x00000002
+#define BGE_LEDCTL_100MBPS_LED 0x00000004
+#define BGE_LEDCTL_10MBPS_LED 0x00000008
+#define BGE_LEDCTL_TRAFLED_OVERRIDE 0x00000010
+#define BGE_LEDCTL_TRAFLED_BLINK 0x00000020
+#define BGE_LEDCTL_TREFLED_BLINK_2 0x00000040
+#define BGE_LEDCTL_1000MBPS_STS 0x00000080
+#define BGE_LEDCTL_100MBPS_STS 0x00000100
+#define BGE_LEDCTL_10MBPS_STS 0x00000200
+#define BGE_LEDCTL_TRADLED_STS 0x00000400
+#define BGE_LEDCTL_BLINKPERIOD 0x7FF80000
+#define BGE_LEDCTL_BLINKPERIOD_OVERRIDE 0x80000000
/* TX backoff seed register */
-#define BGE_TX_BACKOFF_SEED_MASK 0x3F
+#define BGE_TX_BACKOFF_SEED_MASK 0x3F
/* Autopoll status register */
-#define BGE_AUTOPOLLSTS_ERROR 0x00000001
+#define BGE_AUTOPOLLSTS_ERROR 0x00000001
/* Transmit MAC mode register */
-#define BGE_TXMODE_RESET 0x00000001
-#define BGE_TXMODE_ENABLE 0x00000002
-#define BGE_TXMODE_FLOWCTL_ENABLE 0x00000010
-#define BGE_TXMODE_BIGBACKOFF_ENABLE 0x00000020
-#define BGE_TXMODE_LONGPAUSE_ENABLE 0x00000040
+#define BGE_TXMODE_RESET 0x00000001
+#define BGE_TXMODE_ENABLE 0x00000002
+#define BGE_TXMODE_FLOWCTL_ENABLE 0x00000010
+#define BGE_TXMODE_BIGBACKOFF_ENABLE 0x00000020
+#define BGE_TXMODE_LONGPAUSE_ENABLE 0x00000040
/* Transmit MAC status register */
-#define BGE_TXSTAT_RX_XOFFED 0x00000001
-#define BGE_TXSTAT_SENT_XOFF 0x00000002
-#define BGE_TXSTAT_SENT_XON 0x00000004
-#define BGE_TXSTAT_LINK_UP 0x00000008
-#define BGE_TXSTAT_ODI_UFLOW 0x00000010
-#define BGE_TXSTAT_ODI_OFLOW 0x00000020
+#define BGE_TXSTAT_RX_XOFFED 0x00000001
+#define BGE_TXSTAT_SENT_XOFF 0x00000002
+#define BGE_TXSTAT_SENT_XON 0x00000004
+#define BGE_TXSTAT_LINK_UP 0x00000008
+#define BGE_TXSTAT_ODI_UFLOW 0x00000010
+#define BGE_TXSTAT_ODI_OFLOW 0x00000020
/* Transmit MAC lengths register */
-#define BGE_TXLEN_SLOTTIME 0x000000FF
-#define BGE_TXLEN_IPG 0x00000F00
-#define BGE_TXLEN_CRS 0x00003000
+#define BGE_TXLEN_SLOTTIME 0x000000FF
+#define BGE_TXLEN_IPG 0x00000F00
+#define BGE_TXLEN_CRS 0x00003000
/* Receive MAC mode register */
-#define BGE_RXMODE_RESET 0x00000001
-#define BGE_RXMODE_ENABLE 0x00000002
-#define BGE_RXMODE_FLOWCTL_ENABLE 0x00000004
-#define BGE_RXMODE_RX_GIANTS 0x00000020
-#define BGE_RXMODE_RX_RUNTS 0x00000040
-#define BGE_RXMODE_8022_LENCHECK 0x00000080
-#define BGE_RXMODE_RX_PROMISC 0x00000100
-#define BGE_RXMODE_RX_NO_CRC_CHECK 0x00000200
-#define BGE_RXMODE_RX_KEEP_VLAN_DIAG 0x00000400
+#define BGE_RXMODE_RESET 0x00000001
+#define BGE_RXMODE_ENABLE 0x00000002
+#define BGE_RXMODE_FLOWCTL_ENABLE 0x00000004
+#define BGE_RXMODE_RX_GIANTS 0x00000020
+#define BGE_RXMODE_RX_RUNTS 0x00000040
+#define BGE_RXMODE_8022_LENCHECK 0x00000080
+#define BGE_RXMODE_RX_PROMISC 0x00000100
+#define BGE_RXMODE_RX_NO_CRC_CHECK 0x00000200
+#define BGE_RXMODE_RX_KEEP_VLAN_DIAG 0x00000400
/* Receive MAC status register */
-#define BGE_RXSTAT_REMOTE_XOFFED 0x00000001
-#define BGE_RXSTAT_RCVD_XOFF 0x00000002
-#define BGE_RXSTAT_RCVD_XON 0x00000004
+#define BGE_RXSTAT_REMOTE_XOFFED 0x00000001
+#define BGE_RXSTAT_RCVD_XOFF 0x00000002
+#define BGE_RXSTAT_RCVD_XON 0x00000004
/* Receive Rules Control register */
-#define BGE_RXRULECTL_OFFSET 0x000000FF
-#define BGE_RXRULECTL_CLASS 0x00001F00
-#define BGE_RXRULECTL_HDRTYPE 0x0000E000
-#define BGE_RXRULECTL_COMPARE_OP 0x00030000
-#define BGE_RXRULECTL_MAP 0x01000000
-#define BGE_RXRULECTL_DISCARD 0x02000000
-#define BGE_RXRULECTL_MASK 0x04000000
-#define BGE_RXRULECTL_ACTIVATE_PROC3 0x08000000
-#define BGE_RXRULECTL_ACTIVATE_PROC2 0x10000000
-#define BGE_RXRULECTL_ACTIVATE_PROC1 0x20000000
-#define BGE_RXRULECTL_ANDWITHNEXT 0x40000000
+#define BGE_RXRULECTL_OFFSET 0x000000FF
+#define BGE_RXRULECTL_CLASS 0x00001F00
+#define BGE_RXRULECTL_HDRTYPE 0x0000E000
+#define BGE_RXRULECTL_COMPARE_OP 0x00030000
+#define BGE_RXRULECTL_MAP 0x01000000
+#define BGE_RXRULECTL_DISCARD 0x02000000
+#define BGE_RXRULECTL_MASK 0x04000000
+#define BGE_RXRULECTL_ACTIVATE_PROC3 0x08000000
+#define BGE_RXRULECTL_ACTIVATE_PROC2 0x10000000
+#define BGE_RXRULECTL_ACTIVATE_PROC1 0x20000000
+#define BGE_RXRULECTL_ANDWITHNEXT 0x40000000
/* Receive Rules Mask register */
-#define BGE_RXRULEMASK_VALUE 0x0000FFFF
-#define BGE_RXRULEMASK_MASKVAL 0xFFFF0000
+#define BGE_RXRULEMASK_VALUE 0x0000FFFF
+#define BGE_RXRULEMASK_MASKVAL 0xFFFF0000
/* SERDES configuration register */
-#define BGE_SERDESCFG_RXR 0x00000007 /* phase interpolator */
-#define BGE_SERDESCFG_RXG 0x00000018 /* rx gain setting */
-#define BGE_SERDESCFG_RXEDGESEL 0x00000040 /* rising/falling egde */
-#define BGE_SERDESCFG_TX_BIAS 0x00000380 /* TXDAC bias setting */
-#define BGE_SERDESCFG_IBMAX 0x00000400 /* bias current +25% */
-#define BGE_SERDESCFG_IBMIN 0x00000800 /* bias current -25% */
-#define BGE_SERDESCFG_TXMODE 0x00001000
-#define BGE_SERDESCFG_TXEDGESEL 0x00002000 /* rising/falling edge */
-#define BGE_SERDESCFG_MODE 0x00004000 /* TXCP/TXCN disabled */
-#define BGE_SERDESCFG_PLLTEST 0x00008000 /* PLL test mode */
-#define BGE_SERDESCFG_CDET 0x00010000 /* comma detect enable */
-#define BGE_SERDESCFG_TBILOOP 0x00020000 /* local loopback */
-#define BGE_SERDESCFG_REMLOOP 0x00040000 /* remote loopback */
-#define BGE_SERDESCFG_INVPHASE 0x00080000 /* Reverse 125Mhz clock */
-#define BGE_SERDESCFG_12REGCTL 0x00300000 /* 1.2v regulator ctl */
-#define BGE_SERDESCFG_REGCTL 0x00C00000 /* regulator ctl (2.5v) */
+#define BGE_SERDESCFG_RXR 0x00000007 /* phase interpolator */
+#define BGE_SERDESCFG_RXG 0x00000018 /* rx gain setting */
+#define BGE_SERDESCFG_RXEDGESEL 0x00000040 /* rising/falling egde */
+#define BGE_SERDESCFG_TX_BIAS 0x00000380 /* TXDAC bias setting */
+#define BGE_SERDESCFG_IBMAX 0x00000400 /* bias current +25% */
+#define BGE_SERDESCFG_IBMIN 0x00000800 /* bias current -25% */
+#define BGE_SERDESCFG_TXMODE 0x00001000
+#define BGE_SERDESCFG_TXEDGESEL 0x00002000 /* rising/falling edge */
+#define BGE_SERDESCFG_MODE 0x00004000 /* TXCP/TXCN disabled */
+#define BGE_SERDESCFG_PLLTEST 0x00008000 /* PLL test mode */
+#define BGE_SERDESCFG_CDET 0x00010000 /* comma detect enable */
+#define BGE_SERDESCFG_TBILOOP 0x00020000 /* local loopback */
+#define BGE_SERDESCFG_REMLOOP 0x00040000 /* remote loopback */
+#define BGE_SERDESCFG_INVPHASE 0x00080000 /* Reverse 125Mhz clock */
+#define BGE_SERDESCFG_12REGCTL 0x00300000 /* 1.2v regulator ctl */
+#define BGE_SERDESCFG_REGCTL 0x00C00000 /* regulator ctl (2.5v) */
/* SERDES status register */
-#define BGE_SERDESSTS_RXSTAT 0x0000000F /* receive status bits */
-#define BGE_SERDESSTS_CDET 0x00000010 /* comma code detected */
+#define BGE_SERDESSTS_RXSTAT 0x0000000F /* receive status bits */
+#define BGE_SERDESSTS_CDET 0x00000010 /* comma code detected */
/* SGDIG config (not documented) */
-#define BGE_SGDIGCFG_PAUSE_CAP 0x00000800
-#define BGE_SGDIGCFG_ASYM_PAUSE 0x00001000
-#define BGE_SGDIGCFG_SEND 0x40000000
-#define BGE_SGDIGCFG_AUTO 0x80000000
+#define BGE_SGDIGCFG_PAUSE_CAP 0x00000800
+#define BGE_SGDIGCFG_ASYM_PAUSE 0x00001000
+#define BGE_SGDIGCFG_SEND 0x40000000
+#define BGE_SGDIGCFG_AUTO 0x80000000
/* SGDIG status (not documented) */
-#define BGE_SGDIGSTS_PAUSE_CAP 0x00080000
-#define BGE_SGDIGSTS_ASYM_PAUSE 0x00100000
-#define BGE_SGDIGSTS_DONE 0x00000002
+#define BGE_SGDIGSTS_PAUSE_CAP 0x00080000
+#define BGE_SGDIGSTS_ASYM_PAUSE 0x00100000
+#define BGE_SGDIGSTS_DONE 0x00000002
/* MI communication register */
-#define BGE_MICOMM_DATA 0x0000FFFF
-#define BGE_MICOMM_REG 0x001F0000
-#define BGE_MICOMM_PHY 0x03E00000
-#define BGE_MICOMM_CMD 0x0C000000
-#define BGE_MICOMM_READFAIL 0x10000000
-#define BGE_MICOMM_BUSY 0x20000000
-
-#define BGE_MIREG(x) ((x & 0x1F) << 16)
-#define BGE_MIPHY(x) ((x & 0x1F) << 21)
-#define BGE_MICMD_WRITE 0x04000000
-#define BGE_MICMD_READ 0x08000000
+#define BGE_MICOMM_DATA 0x0000FFFF
+#define BGE_MICOMM_REG 0x001F0000
+#define BGE_MICOMM_PHY 0x03E00000
+#define BGE_MICOMM_CMD 0x0C000000
+#define BGE_MICOMM_READFAIL 0x10000000
+#define BGE_MICOMM_BUSY 0x20000000
+
+#define BGE_MIREG(x) ((x & 0x1F) << 16)
+#define BGE_MIPHY(x) ((x & 0x1F) << 21)
+#define BGE_MICMD_WRITE 0x04000000
+#define BGE_MICMD_READ 0x08000000
/* MI status register */
-#define BGE_MISTS_LINK 0x00000001
-#define BGE_MISTS_10MBPS 0x00000002
+#define BGE_MISTS_LINK 0x00000001
+#define BGE_MISTS_10MBPS 0x00000002
-#define BGE_MIMODE_SHORTPREAMBLE 0x00000002
-#define BGE_MIMODE_AUTOPOLL 0x00000010
-#define BGE_MIMODE_CLKCNT 0x001F0000
+#define BGE_MIMODE_SHORTPREAMBLE 0x00000002
+#define BGE_MIMODE_AUTOPOLL 0x00000010
+#define BGE_MIMODE_CLKCNT 0x001F0000
/*
* Send data initiator control registers.
*/
-#define BGE_SDI_MODE 0x0C00
-#define BGE_SDI_STATUS 0x0C04
-#define BGE_SDI_STATS_CTL 0x0C08
-#define BGE_SDI_STATS_ENABLE_MASK 0x0C0C
-#define BGE_SDI_STATS_INCREMENT_MASK 0x0C10
-#define BGE_LOCSTATS_COS0 0x0C80
-#define BGE_LOCSTATS_COS1 0x0C84
-#define BGE_LOCSTATS_COS2 0x0C88
-#define BGE_LOCSTATS_COS3 0x0C8C
-#define BGE_LOCSTATS_COS4 0x0C90
-#define BGE_LOCSTATS_COS5 0x0C84
-#define BGE_LOCSTATS_COS6 0x0C98
-#define BGE_LOCSTATS_COS7 0x0C9C
-#define BGE_LOCSTATS_COS8 0x0CA0
-#define BGE_LOCSTATS_COS9 0x0CA4
-#define BGE_LOCSTATS_COS10 0x0CA8
-#define BGE_LOCSTATS_COS11 0x0CAC
-#define BGE_LOCSTATS_COS12 0x0CB0
-#define BGE_LOCSTATS_COS13 0x0CB4
-#define BGE_LOCSTATS_COS14 0x0CB8
-#define BGE_LOCSTATS_COS15 0x0CBC
-#define BGE_LOCSTATS_DMA_RQ_FULL 0x0CC0
-#define BGE_LOCSTATS_DMA_HIPRIO_RQ_FULL 0x0CC4
-#define BGE_LOCSTATS_SDC_QUEUE_FULL 0x0CC8
-#define BGE_LOCSTATS_NIC_SENDPROD_SET 0x0CCC
-#define BGE_LOCSTATS_STATS_UPDATED 0x0CD0
-#define BGE_LOCSTATS_IRQS 0x0CD4
-#define BGE_LOCSTATS_AVOIDED_IRQS 0x0CD8
-#define BGE_LOCSTATS_TX_THRESH_HIT 0x0CDC
+#define BGE_SDI_MODE 0x0C00
+#define BGE_SDI_STATUS 0x0C04
+#define BGE_SDI_STATS_CTL 0x0C08
+#define BGE_SDI_STATS_ENABLE_MASK 0x0C0C
+#define BGE_SDI_STATS_INCREMENT_MASK 0x0C10
+#define BGE_LOCSTATS_COS0 0x0C80
+#define BGE_LOCSTATS_COS1 0x0C84
+#define BGE_LOCSTATS_COS2 0x0C88
+#define BGE_LOCSTATS_COS3 0x0C8C
+#define BGE_LOCSTATS_COS4 0x0C90
+#define BGE_LOCSTATS_COS5 0x0C84
+#define BGE_LOCSTATS_COS6 0x0C98
+#define BGE_LOCSTATS_COS7 0x0C9C
+#define BGE_LOCSTATS_COS8 0x0CA0
+#define BGE_LOCSTATS_COS9 0x0CA4
+#define BGE_LOCSTATS_COS10 0x0CA8
+#define BGE_LOCSTATS_COS11 0x0CAC
+#define BGE_LOCSTATS_COS12 0x0CB0
+#define BGE_LOCSTATS_COS13 0x0CB4
+#define BGE_LOCSTATS_COS14 0x0CB8
+#define BGE_LOCSTATS_COS15 0x0CBC
+#define BGE_LOCSTATS_DMA_RQ_FULL 0x0CC0
+#define BGE_LOCSTATS_DMA_HIPRIO_RQ_FULL 0x0CC4
+#define BGE_LOCSTATS_SDC_QUEUE_FULL 0x0CC8
+#define BGE_LOCSTATS_NIC_SENDPROD_SET 0x0CCC
+#define BGE_LOCSTATS_STATS_UPDATED 0x0CD0
+#define BGE_LOCSTATS_IRQS 0x0CD4
+#define BGE_LOCSTATS_AVOIDED_IRQS 0x0CD8
+#define BGE_LOCSTATS_TX_THRESH_HIT 0x0CDC
/* Send Data Initiator mode register */
-#define BGE_SDIMODE_RESET 0x00000001
-#define BGE_SDIMODE_ENABLE 0x00000002
-#define BGE_SDIMODE_STATS_OFLOW_ATTN 0x00000004
+#define BGE_SDIMODE_RESET 0x00000001
+#define BGE_SDIMODE_ENABLE 0x00000002
+#define BGE_SDIMODE_STATS_OFLOW_ATTN 0x00000004
/* Send Data Initiator stats register */
-#define BGE_SDISTAT_STATS_OFLOW_ATTN 0x00000004
+#define BGE_SDISTAT_STATS_OFLOW_ATTN 0x00000004
/* Send Data Initiator stats control register */
-#define BGE_SDISTATSCTL_ENABLE 0x00000001
-#define BGE_SDISTATSCTL_FASTER 0x00000002
-#define BGE_SDISTATSCTL_CLEAR 0x00000004
-#define BGE_SDISTATSCTL_FORCEFLUSH 0x00000008
-#define BGE_SDISTATSCTL_FORCEZERO 0x00000010
+#define BGE_SDISTATSCTL_ENABLE 0x00000001
+#define BGE_SDISTATSCTL_FASTER 0x00000002
+#define BGE_SDISTATSCTL_CLEAR 0x00000004
+#define BGE_SDISTATSCTL_FORCEFLUSH 0x00000008
+#define BGE_SDISTATSCTL_FORCEZERO 0x00000010
/*
* Send Data Completion Control registers
*/
-#define BGE_SDC_MODE 0x1000
-#define BGE_SDC_STATUS 0x1004
+#define BGE_SDC_MODE 0x1000
+#define BGE_SDC_STATUS 0x1004
/* Send Data completion mode register */
-#define BGE_SDCMODE_RESET 0x00000001
-#define BGE_SDCMODE_ENABLE 0x00000002
-#define BGE_SDCMODE_ATTN 0x00000004
+#define BGE_SDCMODE_RESET 0x00000001
+#define BGE_SDCMODE_ENABLE 0x00000002
+#define BGE_SDCMODE_ATTN 0x00000004
/* Send Data completion status register */
-#define BGE_SDCSTAT_ATTN 0x00000004
+#define BGE_SDCSTAT_ATTN 0x00000004
/*
* Send BD Ring Selector Control registers
*/
-#define BGE_SRS_MODE 0x1400
-#define BGE_SRS_STATUS 0x1404
-#define BGE_SRS_HWDIAG 0x1408
-#define BGE_SRS_LOC_NIC_CONS0 0x1440
-#define BGE_SRS_LOC_NIC_CONS1 0x1444
-#define BGE_SRS_LOC_NIC_CONS2 0x1448
-#define BGE_SRS_LOC_NIC_CONS3 0x144C
-#define BGE_SRS_LOC_NIC_CONS4 0x1450
-#define BGE_SRS_LOC_NIC_CONS5 0x1454
-#define BGE_SRS_LOC_NIC_CONS6 0x1458
-#define BGE_SRS_LOC_NIC_CONS7 0x145C
-#define BGE_SRS_LOC_NIC_CONS8 0x1460
-#define BGE_SRS_LOC_NIC_CONS9 0x1464
-#define BGE_SRS_LOC_NIC_CONS10 0x1468
-#define BGE_SRS_LOC_NIC_CONS11 0x146C
-#define BGE_SRS_LOC_NIC_CONS12 0x1470
-#define BGE_SRS_LOC_NIC_CONS13 0x1474
-#define BGE_SRS_LOC_NIC_CONS14 0x1478
-#define BGE_SRS_LOC_NIC_CONS15 0x147C
+#define BGE_SRS_MODE 0x1400
+#define BGE_SRS_STATUS 0x1404
+#define BGE_SRS_HWDIAG 0x1408
+#define BGE_SRS_LOC_NIC_CONS0 0x1440
+#define BGE_SRS_LOC_NIC_CONS1 0x1444
+#define BGE_SRS_LOC_NIC_CONS2 0x1448
+#define BGE_SRS_LOC_NIC_CONS3 0x144C
+#define BGE_SRS_LOC_NIC_CONS4 0x1450
+#define BGE_SRS_LOC_NIC_CONS5 0x1454
+#define BGE_SRS_LOC_NIC_CONS6 0x1458
+#define BGE_SRS_LOC_NIC_CONS7 0x145C
+#define BGE_SRS_LOC_NIC_CONS8 0x1460
+#define BGE_SRS_LOC_NIC_CONS9 0x1464
+#define BGE_SRS_LOC_NIC_CONS10 0x1468
+#define BGE_SRS_LOC_NIC_CONS11 0x146C
+#define BGE_SRS_LOC_NIC_CONS12 0x1470
+#define BGE_SRS_LOC_NIC_CONS13 0x1474
+#define BGE_SRS_LOC_NIC_CONS14 0x1478
+#define BGE_SRS_LOC_NIC_CONS15 0x147C
/* Send BD Ring Selector Mode register */
-#define BGE_SRSMODE_RESET 0x00000001
-#define BGE_SRSMODE_ENABLE 0x00000002
-#define BGE_SRSMODE_ATTN 0x00000004
+#define BGE_SRSMODE_RESET 0x00000001
+#define BGE_SRSMODE_ENABLE 0x00000002
+#define BGE_SRSMODE_ATTN 0x00000004
/* Send BD Ring Selector Status register */
-#define BGE_SRSSTAT_ERROR 0x00000004
+#define BGE_SRSSTAT_ERROR 0x00000004
/* Send BD Ring Selector HW Diagnostics register */
-#define BGE_SRSHWDIAG_STATE 0x0000000F
-#define BGE_SRSHWDIAG_CURRINGNUM 0x000000F0
-#define BGE_SRSHWDIAG_STAGEDRINGNUM 0x00000F00
-#define BGE_SRSHWDIAG_RINGNUM_IN_MBX 0x0000F000
+#define BGE_SRSHWDIAG_STATE 0x0000000F
+#define BGE_SRSHWDIAG_CURRINGNUM 0x000000F0
+#define BGE_SRSHWDIAG_STAGEDRINGNUM 0x00000F00
+#define BGE_SRSHWDIAG_RINGNUM_IN_MBX 0x0000F000
/*
* Send BD Initiator Selector Control registers
*/
-#define BGE_SBDI_MODE 0x1800
-#define BGE_SBDI_STATUS 0x1804
-#define BGE_SBDI_LOC_NIC_PROD0 0x1808
-#define BGE_SBDI_LOC_NIC_PROD1 0x180C
-#define BGE_SBDI_LOC_NIC_PROD2 0x1810
-#define BGE_SBDI_LOC_NIC_PROD3 0x1814
-#define BGE_SBDI_LOC_NIC_PROD4 0x1818
-#define BGE_SBDI_LOC_NIC_PROD5 0x181C
-#define BGE_SBDI_LOC_NIC_PROD6 0x1820
-#define BGE_SBDI_LOC_NIC_PROD7 0x1824
-#define BGE_SBDI_LOC_NIC_PROD8 0x1828
-#define BGE_SBDI_LOC_NIC_PROD9 0x182C
-#define BGE_SBDI_LOC_NIC_PROD10 0x1830
-#define BGE_SBDI_LOC_NIC_PROD11 0x1834
-#define BGE_SBDI_LOC_NIC_PROD12 0x1838
-#define BGE_SBDI_LOC_NIC_PROD13 0x183C
-#define BGE_SBDI_LOC_NIC_PROD14 0x1840
-#define BGE_SBDI_LOC_NIC_PROD15 0x1844
+#define BGE_SBDI_MODE 0x1800
+#define BGE_SBDI_STATUS 0x1804
+#define BGE_SBDI_LOC_NIC_PROD0 0x1808
+#define BGE_SBDI_LOC_NIC_PROD1 0x180C
+#define BGE_SBDI_LOC_NIC_PROD2 0x1810
+#define BGE_SBDI_LOC_NIC_PROD3 0x1814
+#define BGE_SBDI_LOC_NIC_PROD4 0x1818
+#define BGE_SBDI_LOC_NIC_PROD5 0x181C
+#define BGE_SBDI_LOC_NIC_PROD6 0x1820
+#define BGE_SBDI_LOC_NIC_PROD7 0x1824
+#define BGE_SBDI_LOC_NIC_PROD8 0x1828
+#define BGE_SBDI_LOC_NIC_PROD9 0x182C
+#define BGE_SBDI_LOC_NIC_PROD10 0x1830
+#define BGE_SBDI_LOC_NIC_PROD11 0x1834
+#define BGE_SBDI_LOC_NIC_PROD12 0x1838
+#define BGE_SBDI_LOC_NIC_PROD13 0x183C
+#define BGE_SBDI_LOC_NIC_PROD14 0x1840
+#define BGE_SBDI_LOC_NIC_PROD15 0x1844
/* Send BD Initiator Mode register */
-#define BGE_SBDIMODE_RESET 0x00000001
-#define BGE_SBDIMODE_ENABLE 0x00000002
-#define BGE_SBDIMODE_ATTN 0x00000004
+#define BGE_SBDIMODE_RESET 0x00000001
+#define BGE_SBDIMODE_ENABLE 0x00000002
+#define BGE_SBDIMODE_ATTN 0x00000004
/* Send BD Initiator Status register */
-#define BGE_SBDISTAT_ERROR 0x00000004
+#define BGE_SBDISTAT_ERROR 0x00000004
/*
* Send BD Completion Control registers
*/
-#define BGE_SBDC_MODE 0x1C00
-#define BGE_SBDC_STATUS 0x1C04
+#define BGE_SBDC_MODE 0x1C00
+#define BGE_SBDC_STATUS 0x1C04
/* Send BD Completion Control Mode register */
-#define BGE_SBDCMODE_RESET 0x00000001
-#define BGE_SBDCMODE_ENABLE 0x00000002
-#define BGE_SBDCMODE_ATTN 0x00000004
+#define BGE_SBDCMODE_RESET 0x00000001
+#define BGE_SBDCMODE_ENABLE 0x00000002
+#define BGE_SBDCMODE_ATTN 0x00000004
/* Send BD Completion Control Status register */
-#define BGE_SBDCSTAT_ATTN 0x00000004
+#define BGE_SBDCSTAT_ATTN 0x00000004
/*
* Receive List Placement Control registers
*/
-#define BGE_RXLP_MODE 0x2000
-#define BGE_RXLP_STATUS 0x2004
-#define BGE_RXLP_SEL_LIST_LOCK 0x2008
-#define BGE_RXLP_SEL_NON_EMPTY_BITS 0x200C
-#define BGE_RXLP_CFG 0x2010
-#define BGE_RXLP_STATS_CTL 0x2014
-#define BGE_RXLP_STATS_ENABLE_MASK 0x2018
-#define BGE_RXLP_STATS_INCREMENT_MASK 0x201C
-#define BGE_RXLP_HEAD0 0x2100
-#define BGE_RXLP_TAIL0 0x2104
-#define BGE_RXLP_COUNT0 0x2108
-#define BGE_RXLP_HEAD1 0x2110
-#define BGE_RXLP_TAIL1 0x2114
-#define BGE_RXLP_COUNT1 0x2118
-#define BGE_RXLP_HEAD2 0x2120
-#define BGE_RXLP_TAIL2 0x2124
-#define BGE_RXLP_COUNT2 0x2128
-#define BGE_RXLP_HEAD3 0x2130
-#define BGE_RXLP_TAIL3 0x2134
-#define BGE_RXLP_COUNT3 0x2138
-#define BGE_RXLP_HEAD4 0x2140
-#define BGE_RXLP_TAIL4 0x2144
-#define BGE_RXLP_COUNT4 0x2148
-#define BGE_RXLP_HEAD5 0x2150
-#define BGE_RXLP_TAIL5 0x2154
-#define BGE_RXLP_COUNT5 0x2158
-#define BGE_RXLP_HEAD6 0x2160
-#define BGE_RXLP_TAIL6 0x2164
-#define BGE_RXLP_COUNT6 0x2168
-#define BGE_RXLP_HEAD7 0x2170
-#define BGE_RXLP_TAIL7 0x2174
-#define BGE_RXLP_COUNT7 0x2178
-#define BGE_RXLP_HEAD8 0x2180
-#define BGE_RXLP_TAIL8 0x2184
-#define BGE_RXLP_COUNT8 0x2188
-#define BGE_RXLP_HEAD9 0x2190
-#define BGE_RXLP_TAIL9 0x2194
-#define BGE_RXLP_COUNT9 0x2198
-#define BGE_RXLP_HEAD10 0x21A0
-#define BGE_RXLP_TAIL10 0x21A4
-#define BGE_RXLP_COUNT10 0x21A8
-#define BGE_RXLP_HEAD11 0x21B0
-#define BGE_RXLP_TAIL11 0x21B4
-#define BGE_RXLP_COUNT11 0x21B8
-#define BGE_RXLP_HEAD12 0x21C0
-#define BGE_RXLP_TAIL12 0x21C4
-#define BGE_RXLP_COUNT12 0x21C8
-#define BGE_RXLP_HEAD13 0x21D0
-#define BGE_RXLP_TAIL13 0x21D4
-#define BGE_RXLP_COUNT13 0x21D8
-#define BGE_RXLP_HEAD14 0x21E0
-#define BGE_RXLP_TAIL14 0x21E4
-#define BGE_RXLP_COUNT14 0x21E8
-#define BGE_RXLP_HEAD15 0x21F0
-#define BGE_RXLP_TAIL15 0x21F4
-#define BGE_RXLP_COUNT15 0x21F8
-#define BGE_RXLP_LOCSTAT_COS0 0x2200
-#define BGE_RXLP_LOCSTAT_COS1 0x2204
-#define BGE_RXLP_LOCSTAT_COS2 0x2208
-#define BGE_RXLP_LOCSTAT_COS3 0x220C
-#define BGE_RXLP_LOCSTAT_COS4 0x2210
-#define BGE_RXLP_LOCSTAT_COS5 0x2214
-#define BGE_RXLP_LOCSTAT_COS6 0x2218
-#define BGE_RXLP_LOCSTAT_COS7 0x221C
-#define BGE_RXLP_LOCSTAT_COS8 0x2220
-#define BGE_RXLP_LOCSTAT_COS9 0x2224
-#define BGE_RXLP_LOCSTAT_COS10 0x2228
-#define BGE_RXLP_LOCSTAT_COS11 0x222C
-#define BGE_RXLP_LOCSTAT_COS12 0x2230
-#define BGE_RXLP_LOCSTAT_COS13 0x2234
-#define BGE_RXLP_LOCSTAT_COS14 0x2238
-#define BGE_RXLP_LOCSTAT_COS15 0x223C
-#define BGE_RXLP_LOCSTAT_FILTDROP 0x2240
-#define BGE_RXLP_LOCSTAT_DMA_WRQ_FULL 0x2244
-#define BGE_RXLP_LOCSTAT_DMA_HPWRQ_FULL 0x2248
-#define BGE_RXLP_LOCSTAT_OUT_OF_BDS 0x224C
-#define BGE_RXLP_LOCSTAT_IFIN_DROPS 0x2250
-#define BGE_RXLP_LOCSTAT_IFIN_ERRORS 0x2254
-#define BGE_RXLP_LOCSTAT_RXTHRESH_HIT 0x2258
+#define BGE_RXLP_MODE 0x2000
+#define BGE_RXLP_STATUS 0x2004
+#define BGE_RXLP_SEL_LIST_LOCK 0x2008
+#define BGE_RXLP_SEL_NON_EMPTY_BITS 0x200C
+#define BGE_RXLP_CFG 0x2010
+#define BGE_RXLP_STATS_CTL 0x2014
+#define BGE_RXLP_STATS_ENABLE_MASK 0x2018
+#define BGE_RXLP_STATS_INCREMENT_MASK 0x201C
+#define BGE_RXLP_HEAD0 0x2100
+#define BGE_RXLP_TAIL0 0x2104
+#define BGE_RXLP_COUNT0 0x2108
+#define BGE_RXLP_HEAD1 0x2110
+#define BGE_RXLP_TAIL1 0x2114
+#define BGE_RXLP_COUNT1 0x2118
+#define BGE_RXLP_HEAD2 0x2120
+#define BGE_RXLP_TAIL2 0x2124
+#define BGE_RXLP_COUNT2 0x2128
+#define BGE_RXLP_HEAD3 0x2130
+#define BGE_RXLP_TAIL3 0x2134
+#define BGE_RXLP_COUNT3 0x2138
+#define BGE_RXLP_HEAD4 0x2140
+#define BGE_RXLP_TAIL4 0x2144
+#define BGE_RXLP_COUNT4 0x2148
+#define BGE_RXLP_HEAD5 0x2150
+#define BGE_RXLP_TAIL5 0x2154
+#define BGE_RXLP_COUNT5 0x2158
+#define BGE_RXLP_HEAD6 0x2160
+#define BGE_RXLP_TAIL6 0x2164
+#define BGE_RXLP_COUNT6 0x2168
+#define BGE_RXLP_HEAD7 0x2170
+#define BGE_RXLP_TAIL7 0x2174
+#define BGE_RXLP_COUNT7 0x2178
+#define BGE_RXLP_HEAD8 0x2180
+#define BGE_RXLP_TAIL8 0x2184
+#define BGE_RXLP_COUNT8 0x2188
+#define BGE_RXLP_HEAD9 0x2190
+#define BGE_RXLP_TAIL9 0x2194
+#define BGE_RXLP_COUNT9 0x2198
+#define BGE_RXLP_HEAD10 0x21A0
+#define BGE_RXLP_TAIL10 0x21A4
+#define BGE_RXLP_COUNT10 0x21A8
+#define BGE_RXLP_HEAD11 0x21B0
+#define BGE_RXLP_TAIL11 0x21B4
+#define BGE_RXLP_COUNT11 0x21B8
+#define BGE_RXLP_HEAD12 0x21C0
+#define BGE_RXLP_TAIL12 0x21C4
+#define BGE_RXLP_COUNT12 0x21C8
+#define BGE_RXLP_HEAD13 0x21D0
+#define BGE_RXLP_TAIL13 0x21D4
+#define BGE_RXLP_COUNT13 0x21D8
+#define BGE_RXLP_HEAD14 0x21E0
+#define BGE_RXLP_TAIL14 0x21E4
+#define BGE_RXLP_COUNT14 0x21E8
+#define BGE_RXLP_HEAD15 0x21F0
+#define BGE_RXLP_TAIL15 0x21F4
+#define BGE_RXLP_COUNT15 0x21F8
+#define BGE_RXLP_LOCSTAT_COS0 0x2200
+#define BGE_RXLP_LOCSTAT_COS1 0x2204
+#define BGE_RXLP_LOCSTAT_COS2 0x2208
+#define BGE_RXLP_LOCSTAT_COS3 0x220C
+#define BGE_RXLP_LOCSTAT_COS4 0x2210
+#define BGE_RXLP_LOCSTAT_COS5 0x2214
+#define BGE_RXLP_LOCSTAT_COS6 0x2218
+#define BGE_RXLP_LOCSTAT_COS7 0x221C
+#define BGE_RXLP_LOCSTAT_COS8 0x2220
+#define BGE_RXLP_LOCSTAT_COS9 0x2224
+#define BGE_RXLP_LOCSTAT_COS10 0x2228
+#define BGE_RXLP_LOCSTAT_COS11 0x222C
+#define BGE_RXLP_LOCSTAT_COS12 0x2230
+#define BGE_RXLP_LOCSTAT_COS13 0x2234
+#define BGE_RXLP_LOCSTAT_COS14 0x2238
+#define BGE_RXLP_LOCSTAT_COS15 0x223C
+#define BGE_RXLP_LOCSTAT_FILTDROP 0x2240
+#define BGE_RXLP_LOCSTAT_DMA_WRQ_FULL 0x2244
+#define BGE_RXLP_LOCSTAT_DMA_HPWRQ_FULL 0x2248
+#define BGE_RXLP_LOCSTAT_OUT_OF_BDS 0x224C
+#define BGE_RXLP_LOCSTAT_IFIN_DROPS 0x2250
+#define BGE_RXLP_LOCSTAT_IFIN_ERRORS 0x2254
+#define BGE_RXLP_LOCSTAT_RXTHRESH_HIT 0x2258
/* Receive List Placement mode register */
-#define BGE_RXLPMODE_RESET 0x00000001
-#define BGE_RXLPMODE_ENABLE 0x00000002
-#define BGE_RXLPMODE_CLASS0_ATTN 0x00000004
-#define BGE_RXLPMODE_MAPOUTRANGE_ATTN 0x00000008
-#define BGE_RXLPMODE_STATSOFLOW_ATTN 0x00000010
+#define BGE_RXLPMODE_RESET 0x00000001
+#define BGE_RXLPMODE_ENABLE 0x00000002
+#define BGE_RXLPMODE_CLASS0_ATTN 0x00000004
+#define BGE_RXLPMODE_MAPOUTRANGE_ATTN 0x00000008
+#define BGE_RXLPMODE_STATSOFLOW_ATTN 0x00000010
/* Receive List Placement Status register */
-#define BGE_RXLPSTAT_CLASS0_ATTN 0x00000004
-#define BGE_RXLPSTAT_MAPOUTRANGE_ATTN 0x00000008
-#define BGE_RXLPSTAT_STATSOFLOW_ATTN 0x00000010
+#define BGE_RXLPSTAT_CLASS0_ATTN 0x00000004
+#define BGE_RXLPSTAT_MAPOUTRANGE_ATTN 0x00000008
+#define BGE_RXLPSTAT_STATSOFLOW_ATTN 0x00000010
/*
* Receive Data and Receive BD Initiator Control Registers
*/
-#define BGE_RDBDI_MODE 0x2400
-#define BGE_RDBDI_STATUS 0x2404
-#define BGE_RX_JUMBO_RCB_HADDR_HI 0x2440
-#define BGE_RX_JUMBO_RCB_HADDR_LO 0x2444
-#define BGE_RX_JUMBO_RCB_MAXLEN_FLAGS 0x2448
-#define BGE_RX_JUMBO_RCB_NICADDR 0x244C
-#define BGE_RX_STD_RCB_HADDR_HI 0x2450
-#define BGE_RX_STD_RCB_HADDR_LO 0x2454
-#define BGE_RX_STD_RCB_MAXLEN_FLAGS 0x2458
-#define BGE_RX_STD_RCB_NICADDR 0x245C
-#define BGE_RX_MINI_RCB_HADDR_HI 0x2460
-#define BGE_RX_MINI_RCB_HADDR_LO 0x2464
-#define BGE_RX_MINI_RCB_MAXLEN_FLAGS 0x2468
-#define BGE_RX_MINI_RCB_NICADDR 0x246C
-#define BGE_RDBDI_JUMBO_RX_CONS 0x2470
-#define BGE_RDBDI_STD_RX_CONS 0x2474
-#define BGE_RDBDI_MINI_RX_CONS 0x2478
-#define BGE_RDBDI_RETURN_PROD0 0x2480
-#define BGE_RDBDI_RETURN_PROD1 0x2484
-#define BGE_RDBDI_RETURN_PROD2 0x2488
-#define BGE_RDBDI_RETURN_PROD3 0x248C
-#define BGE_RDBDI_RETURN_PROD4 0x2490
-#define BGE_RDBDI_RETURN_PROD5 0x2494
-#define BGE_RDBDI_RETURN_PROD6 0x2498
-#define BGE_RDBDI_RETURN_PROD7 0x249C
-#define BGE_RDBDI_RETURN_PROD8 0x24A0
-#define BGE_RDBDI_RETURN_PROD9 0x24A4
-#define BGE_RDBDI_RETURN_PROD10 0x24A8
-#define BGE_RDBDI_RETURN_PROD11 0x24AC
-#define BGE_RDBDI_RETURN_PROD12 0x24B0
-#define BGE_RDBDI_RETURN_PROD13 0x24B4
-#define BGE_RDBDI_RETURN_PROD14 0x24B8
-#define BGE_RDBDI_RETURN_PROD15 0x24BC
-#define BGE_RDBDI_HWDIAG 0x24C0
+#define BGE_RDBDI_MODE 0x2400
+#define BGE_RDBDI_STATUS 0x2404
+#define BGE_RX_JUMBO_RCB_HADDR_HI 0x2440
+#define BGE_RX_JUMBO_RCB_HADDR_LO 0x2444
+#define BGE_RX_JUMBO_RCB_MAXLEN_FLAGS 0x2448
+#define BGE_RX_JUMBO_RCB_NICADDR 0x244C
+#define BGE_RX_STD_RCB_HADDR_HI 0x2450
+#define BGE_RX_STD_RCB_HADDR_LO 0x2454
+#define BGE_RX_STD_RCB_MAXLEN_FLAGS 0x2458
+#define BGE_RX_STD_RCB_NICADDR 0x245C
+#define BGE_RX_MINI_RCB_HADDR_HI 0x2460
+#define BGE_RX_MINI_RCB_HADDR_LO 0x2464
+#define BGE_RX_MINI_RCB_MAXLEN_FLAGS 0x2468
+#define BGE_RX_MINI_RCB_NICADDR 0x246C
+#define BGE_RDBDI_JUMBO_RX_CONS 0x2470
+#define BGE_RDBDI_STD_RX_CONS 0x2474
+#define BGE_RDBDI_MINI_RX_CONS 0x2478
+#define BGE_RDBDI_RETURN_PROD0 0x2480
+#define BGE_RDBDI_RETURN_PROD1 0x2484
+#define BGE_RDBDI_RETURN_PROD2 0x2488
+#define BGE_RDBDI_RETURN_PROD3 0x248C
+#define BGE_RDBDI_RETURN_PROD4 0x2490
+#define BGE_RDBDI_RETURN_PROD5 0x2494
+#define BGE_RDBDI_RETURN_PROD6 0x2498
+#define BGE_RDBDI_RETURN_PROD7 0x249C
+#define BGE_RDBDI_RETURN_PROD8 0x24A0
+#define BGE_RDBDI_RETURN_PROD9 0x24A4
+#define BGE_RDBDI_RETURN_PROD10 0x24A8
+#define BGE_RDBDI_RETURN_PROD11 0x24AC
+#define BGE_RDBDI_RETURN_PROD12 0x24B0
+#define BGE_RDBDI_RETURN_PROD13 0x24B4
+#define BGE_RDBDI_RETURN_PROD14 0x24B8
+#define BGE_RDBDI_RETURN_PROD15 0x24BC
+#define BGE_RDBDI_HWDIAG 0x24C0
/* Receive Data and Receive BD Initiator Mode register */
-#define BGE_RDBDIMODE_RESET 0x00000001
-#define BGE_RDBDIMODE_ENABLE 0x00000002
-#define BGE_RDBDIMODE_JUMBO_ATTN 0x00000004
-#define BGE_RDBDIMODE_GIANT_ATTN 0x00000008
-#define BGE_RDBDIMODE_BADRINGSZ_ATTN 0x00000010
+#define BGE_RDBDIMODE_RESET 0x00000001
+#define BGE_RDBDIMODE_ENABLE 0x00000002
+#define BGE_RDBDIMODE_JUMBO_ATTN 0x00000004
+#define BGE_RDBDIMODE_GIANT_ATTN 0x00000008
+#define BGE_RDBDIMODE_BADRINGSZ_ATTN 0x00000010
/* Receive Data and Receive BD Initiator Status register */
-#define BGE_RDBDISTAT_JUMBO_ATTN 0x00000004
-#define BGE_RDBDISTAT_GIANT_ATTN 0x00000008
-#define BGE_RDBDISTAT_BADRINGSZ_ATTN 0x00000010
+#define BGE_RDBDISTAT_JUMBO_ATTN 0x00000004
+#define BGE_RDBDISTAT_GIANT_ATTN 0x00000008
+#define BGE_RDBDISTAT_BADRINGSZ_ATTN 0x00000010
/*
* Receive Data Completion Control registers
*/
-#define BGE_RDC_MODE 0x2800
+#define BGE_RDC_MODE 0x2800
/* Receive Data Completion Mode register */
-#define BGE_RDCMODE_RESET 0x00000001
-#define BGE_RDCMODE_ENABLE 0x00000002
-#define BGE_RDCMODE_ATTN 0x00000004
+#define BGE_RDCMODE_RESET 0x00000001
+#define BGE_RDCMODE_ENABLE 0x00000002
+#define BGE_RDCMODE_ATTN 0x00000004
/*
* Receive BD Initiator Control registers
*/
-#define BGE_RBDI_MODE 0x2C00
-#define BGE_RBDI_STATUS 0x2C04
-#define BGE_RBDI_NIC_JUMBO_BD_PROD 0x2C08
-#define BGE_RBDI_NIC_STD_BD_PROD 0x2C0C
-#define BGE_RBDI_NIC_MINI_BD_PROD 0x2C10
-#define BGE_RBDI_MINI_REPL_THRESH 0x2C14
-#define BGE_RBDI_STD_REPL_THRESH 0x2C18
-#define BGE_RBDI_JUMBO_REPL_THRESH 0x2C1C
+#define BGE_RBDI_MODE 0x2C00
+#define BGE_RBDI_STATUS 0x2C04
+#define BGE_RBDI_NIC_JUMBO_BD_PROD 0x2C08
+#define BGE_RBDI_NIC_STD_BD_PROD 0x2C0C
+#define BGE_RBDI_NIC_MINI_BD_PROD 0x2C10
+#define BGE_RBDI_MINI_REPL_THRESH 0x2C14
+#define BGE_RBDI_STD_REPL_THRESH 0x2C18
+#define BGE_RBDI_JUMBO_REPL_THRESH 0x2C1C
/* Receive BD Initiator Mode register */
-#define BGE_RBDIMODE_RESET 0x00000001
-#define BGE_RBDIMODE_ENABLE 0x00000002
-#define BGE_RBDIMODE_ATTN 0x00000004
+#define BGE_RBDIMODE_RESET 0x00000001
+#define BGE_RBDIMODE_ENABLE 0x00000002
+#define BGE_RBDIMODE_ATTN 0x00000004
/* Receive BD Initiator Status register */
-#define BGE_RBDISTAT_ATTN 0x00000004
+#define BGE_RBDISTAT_ATTN 0x00000004
/*
* Receive BD Completion Control registers
*/
-#define BGE_RBDC_MODE 0x3000
-#define BGE_RBDC_STATUS 0x3004
-#define BGE_RBDC_JUMBO_BD_PROD 0x3008
-#define BGE_RBDC_STD_BD_PROD 0x300C
-#define BGE_RBDC_MINI_BD_PROD 0x3010
+#define BGE_RBDC_MODE 0x3000
+#define BGE_RBDC_STATUS 0x3004
+#define BGE_RBDC_JUMBO_BD_PROD 0x3008
+#define BGE_RBDC_STD_BD_PROD 0x300C
+#define BGE_RBDC_MINI_BD_PROD 0x3010
/* Receive BD completion mode register */
-#define BGE_RBDCMODE_RESET 0x00000001
-#define BGE_RBDCMODE_ENABLE 0x00000002
-#define BGE_RBDCMODE_ATTN 0x00000004
+#define BGE_RBDCMODE_RESET 0x00000001
+#define BGE_RBDCMODE_ENABLE 0x00000002
+#define BGE_RBDCMODE_ATTN 0x00000004
/* Receive BD completion status register */
-#define BGE_RBDCSTAT_ERROR 0x00000004
+#define BGE_RBDCSTAT_ERROR 0x00000004
/*
* Receive List Selector Control registers
*/
-#define BGE_RXLS_MODE 0x3400
-#define BGE_RXLS_STATUS 0x3404
+#define BGE_RXLS_MODE 0x3400
+#define BGE_RXLS_STATUS 0x3404
/* Receive List Selector Mode register */
-#define BGE_RXLSMODE_RESET 0x00000001
-#define BGE_RXLSMODE_ENABLE 0x00000002
-#define BGE_RXLSMODE_ATTN 0x00000004
+#define BGE_RXLSMODE_RESET 0x00000001
+#define BGE_RXLSMODE_ENABLE 0x00000002
+#define BGE_RXLSMODE_ATTN 0x00000004
/* Receive List Selector Status register */
-#define BGE_RXLSSTAT_ERROR 0x00000004
+#define BGE_RXLSSTAT_ERROR 0x00000004
/*
* Mbuf Cluster Free registers (has nothing to do with BSD mbufs)
*/
-#define BGE_MBCF_MODE 0x3800
-#define BGE_MBCF_STATUS 0x3804
+#define BGE_MBCF_MODE 0x3800
+#define BGE_MBCF_STATUS 0x3804
/* Mbuf Cluster Free mode register */
-#define BGE_MBCFMODE_RESET 0x00000001
-#define BGE_MBCFMODE_ENABLE 0x00000002
-#define BGE_MBCFMODE_ATTN 0x00000004
+#define BGE_MBCFMODE_RESET 0x00000001
+#define BGE_MBCFMODE_ENABLE 0x00000002
+#define BGE_MBCFMODE_ATTN 0x00000004
/* Mbuf Cluster Free status register */
-#define BGE_MBCFSTAT_ERROR 0x00000004
+#define BGE_MBCFSTAT_ERROR 0x00000004
/*
* Host Coalescing Control registers
*/
-#define BGE_HCC_MODE 0x3C00
-#define BGE_HCC_STATUS 0x3C04
-#define BGE_HCC_RX_COAL_TICKS 0x3C08
-#define BGE_HCC_TX_COAL_TICKS 0x3C0C
-#define BGE_HCC_RX_MAX_COAL_BDS 0x3C10
-#define BGE_HCC_TX_MAX_COAL_BDS 0x3C14
-#define BGE_HCC_RX_COAL_TICKS_INT 0x3C18 /* ticks during interrupt */
-#define BGE_HCC_TX_COAL_TICKS_INT 0x3C1C /* ticks during interrupt */
-#define BGE_HCC_RX_MAX_COAL_BDS_INT 0x3C20 /* BDs during interrupt */
-#define BGE_HCC_TX_MAX_COAL_BDS_INT 0x3C24 /* BDs during interrupt */
-#define BGE_HCC_STATS_TICKS 0x3C28
-#define BGE_HCC_STATS_ADDR_HI 0x3C30
-#define BGE_HCC_STATS_ADDR_LO 0x3C34
-#define BGE_HCC_STATUSBLK_ADDR_HI 0x3C38
-#define BGE_HCC_STATUSBLK_ADDR_LO 0x3C3C
-#define BGE_HCC_STATS_BASEADDR 0x3C40 /* address in NIC memory */
-#define BGE_HCC_STATUSBLK_BASEADDR 0x3C44 /* address in NIC memory */
-#define BGE_FLOW_ATTN 0x3C48
-#define BGE_HCC_JUMBO_BD_CONS 0x3C50
-#define BGE_HCC_STD_BD_CONS 0x3C54
-#define BGE_HCC_MINI_BD_CONS 0x3C58
-#define BGE_HCC_RX_RETURN_PROD0 0x3C80
-#define BGE_HCC_RX_RETURN_PROD1 0x3C84
-#define BGE_HCC_RX_RETURN_PROD2 0x3C88
-#define BGE_HCC_RX_RETURN_PROD3 0x3C8C
-#define BGE_HCC_RX_RETURN_PROD4 0x3C90
-#define BGE_HCC_RX_RETURN_PROD5 0x3C94
-#define BGE_HCC_RX_RETURN_PROD6 0x3C98
-#define BGE_HCC_RX_RETURN_PROD7 0x3C9C
-#define BGE_HCC_RX_RETURN_PROD8 0x3CA0
-#define BGE_HCC_RX_RETURN_PROD9 0x3CA4
-#define BGE_HCC_RX_RETURN_PROD10 0x3CA8
-#define BGE_HCC_RX_RETURN_PROD11 0x3CAC
-#define BGE_HCC_RX_RETURN_PROD12 0x3CB0
-#define BGE_HCC_RX_RETURN_PROD13 0x3CB4
-#define BGE_HCC_RX_RETURN_PROD14 0x3CB8
-#define BGE_HCC_RX_RETURN_PROD15 0x3CBC
-#define BGE_HCC_TX_BD_CONS0 0x3CC0
-#define BGE_HCC_TX_BD_CONS1 0x3CC4
-#define BGE_HCC_TX_BD_CONS2 0x3CC8
-#define BGE_HCC_TX_BD_CONS3 0x3CCC
-#define BGE_HCC_TX_BD_CONS4 0x3CD0
-#define BGE_HCC_TX_BD_CONS5 0x3CD4
-#define BGE_HCC_TX_BD_CONS6 0x3CD8
-#define BGE_HCC_TX_BD_CONS7 0x3CDC
-#define BGE_HCC_TX_BD_CONS8 0x3CE0
-#define BGE_HCC_TX_BD_CONS9 0x3CE4
-#define BGE_HCC_TX_BD_CONS10 0x3CE8
-#define BGE_HCC_TX_BD_CONS11 0x3CEC
-#define BGE_HCC_TX_BD_CONS12 0x3CF0
-#define BGE_HCC_TX_BD_CONS13 0x3CF4
-#define BGE_HCC_TX_BD_CONS14 0x3CF8
-#define BGE_HCC_TX_BD_CONS15 0x3CFC
+#define BGE_HCC_MODE 0x3C00
+#define BGE_HCC_STATUS 0x3C04
+#define BGE_HCC_RX_COAL_TICKS 0x3C08
+#define BGE_HCC_TX_COAL_TICKS 0x3C0C
+#define BGE_HCC_RX_MAX_COAL_BDS 0x3C10
+#define BGE_HCC_TX_MAX_COAL_BDS 0x3C14
+#define BGE_HCC_RX_COAL_TICKS_INT 0x3C18 /* ticks during interrupt */
+#define BGE_HCC_TX_COAL_TICKS_INT 0x3C1C /* ticks during interrupt */
+#define BGE_HCC_RX_MAX_COAL_BDS_INT 0x3C20 /* BDs during interrupt */
+#define BGE_HCC_TX_MAX_COAL_BDS_INT 0x3C24 /* BDs during interrupt */
+#define BGE_HCC_STATS_TICKS 0x3C28
+#define BGE_HCC_STATS_ADDR_HI 0x3C30
+#define BGE_HCC_STATS_ADDR_LO 0x3C34
+#define BGE_HCC_STATUSBLK_ADDR_HI 0x3C38
+#define BGE_HCC_STATUSBLK_ADDR_LO 0x3C3C
+#define BGE_HCC_STATS_BASEADDR 0x3C40 /* address in NIC memory */
+#define BGE_HCC_STATUSBLK_BASEADDR 0x3C44 /* address in NIC memory */
+#define BGE_FLOW_ATTN 0x3C48
+#define BGE_HCC_JUMBO_BD_CONS 0x3C50
+#define BGE_HCC_STD_BD_CONS 0x3C54
+#define BGE_HCC_MINI_BD_CONS 0x3C58
+#define BGE_HCC_RX_RETURN_PROD0 0x3C80
+#define BGE_HCC_RX_RETURN_PROD1 0x3C84
+#define BGE_HCC_RX_RETURN_PROD2 0x3C88
+#define BGE_HCC_RX_RETURN_PROD3 0x3C8C
+#define BGE_HCC_RX_RETURN_PROD4 0x3C90
+#define BGE_HCC_RX_RETURN_PROD5 0x3C94
+#define BGE_HCC_RX_RETURN_PROD6 0x3C98
+#define BGE_HCC_RX_RETURN_PROD7 0x3C9C
+#define BGE_HCC_RX_RETURN_PROD8 0x3CA0
+#define BGE_HCC_RX_RETURN_PROD9 0x3CA4
+#define BGE_HCC_RX_RETURN_PROD10 0x3CA8
+#define BGE_HCC_RX_RETURN_PROD11 0x3CAC
+#define BGE_HCC_RX_RETURN_PROD12 0x3CB0
+#define BGE_HCC_RX_RETURN_PROD13 0x3CB4
+#define BGE_HCC_RX_RETURN_PROD14 0x3CB8
+#define BGE_HCC_RX_RETURN_PROD15 0x3CBC
+#define BGE_HCC_TX_BD_CONS0 0x3CC0
+#define BGE_HCC_TX_BD_CONS1 0x3CC4
+#define BGE_HCC_TX_BD_CONS2 0x3CC8
+#define BGE_HCC_TX_BD_CONS3 0x3CCC
+#define BGE_HCC_TX_BD_CONS4 0x3CD0
+#define BGE_HCC_TX_BD_CONS5 0x3CD4
+#define BGE_HCC_TX_BD_CONS6 0x3CD8
+#define BGE_HCC_TX_BD_CONS7 0x3CDC
+#define BGE_HCC_TX_BD_CONS8 0x3CE0
+#define BGE_HCC_TX_BD_CONS9 0x3CE4
+#define BGE_HCC_TX_BD_CONS10 0x3CE8
+#define BGE_HCC_TX_BD_CONS11 0x3CEC
+#define BGE_HCC_TX_BD_CONS12 0x3CF0
+#define BGE_HCC_TX_BD_CONS13 0x3CF4
+#define BGE_HCC_TX_BD_CONS14 0x3CF8
+#define BGE_HCC_TX_BD_CONS15 0x3CFC
/* Host coalescing mode register */
-#define BGE_HCCMODE_RESET 0x00000001
-#define BGE_HCCMODE_ENABLE 0x00000002
-#define BGE_HCCMODE_ATTN 0x00000004
-#define BGE_HCCMODE_COAL_NOW 0x00000008
-#define BGE_HCCMODE_MSI_BITS 0x0x000070
-#define BGE_HCCMODE_STATBLK_SIZE 0x00000180
-
-#define BGE_STATBLKSZ_FULL 0x00000000
-#define BGE_STATBLKSZ_64BYTE 0x00000080
-#define BGE_STATBLKSZ_32BYTE 0x00000100
+#define BGE_HCCMODE_RESET 0x00000001
+#define BGE_HCCMODE_ENABLE 0x00000002
+#define BGE_HCCMODE_ATTN 0x00000004
+#define BGE_HCCMODE_COAL_NOW 0x00000008
+#define BGE_HCCMODE_MSI_BITS 0x00000070
+#define BGE_HCCMODE_STATBLK_SIZE 0x00000180
+
+#define BGE_STATBLKSZ_FULL 0x00000000
+#define BGE_STATBLKSZ_64BYTE 0x00000080
+#define BGE_STATBLKSZ_32BYTE 0x00000100
/* Host coalescing status register */
-#define BGE_HCCSTAT_ERROR 0x00000004
+#define BGE_HCCSTAT_ERROR 0x00000004
/* Flow attention register */
-#define BGE_FLOWATTN_MB_LOWAT 0x00000040
-#define BGE_FLOWATTN_MEMARB 0x00000080
-#define BGE_FLOWATTN_HOSTCOAL 0x00008000
-#define BGE_FLOWATTN_DMADONE_DISCARD 0x00010000
-#define BGE_FLOWATTN_RCB_INVAL 0x00020000
-#define BGE_FLOWATTN_RXDATA_CORRUPT 0x00040000
-#define BGE_FLOWATTN_RDBDI 0x00080000
-#define BGE_FLOWATTN_RXLS 0x00100000
-#define BGE_FLOWATTN_RXLP 0x00200000
-#define BGE_FLOWATTN_RBDC 0x00400000
-#define BGE_FLOWATTN_RBDI 0x00800000
-#define BGE_FLOWATTN_SDC 0x08000000
-#define BGE_FLOWATTN_SDI 0x10000000
-#define BGE_FLOWATTN_SRS 0x20000000
-#define BGE_FLOWATTN_SBDC 0x40000000
-#define BGE_FLOWATTN_SBDI 0x80000000
+#define BGE_FLOWATTN_MB_LOWAT 0x00000040
+#define BGE_FLOWATTN_MEMARB 0x00000080
+#define BGE_FLOWATTN_HOSTCOAL 0x00008000
+#define BGE_FLOWATTN_DMADONE_DISCARD 0x00010000
+#define BGE_FLOWATTN_RCB_INVAL 0x00020000
+#define BGE_FLOWATTN_RXDATA_CORRUPT 0x00040000
+#define BGE_FLOWATTN_RDBDI 0x00080000
+#define BGE_FLOWATTN_RXLS 0x00100000
+#define BGE_FLOWATTN_RXLP 0x00200000
+#define BGE_FLOWATTN_RBDC 0x00400000
+#define BGE_FLOWATTN_RBDI 0x00800000
+#define BGE_FLOWATTN_SDC 0x08000000
+#define BGE_FLOWATTN_SDI 0x10000000
+#define BGE_FLOWATTN_SRS 0x20000000
+#define BGE_FLOWATTN_SBDC 0x40000000
+#define BGE_FLOWATTN_SBDI 0x80000000
/*
* Memory arbiter registers
*/
-#define BGE_MARB_MODE 0x4000
-#define BGE_MARB_STATUS 0x4004
-#define BGE_MARB_TRAPADDR_HI 0x4008
-#define BGE_MARB_TRAPADDR_LO 0x400C
+#define BGE_MARB_MODE 0x4000
+#define BGE_MARB_STATUS 0x4004
+#define BGE_MARB_TRAPADDR_HI 0x4008
+#define BGE_MARB_TRAPADDR_LO 0x400C
/* Memory arbiter mode register */
-#define BGE_MARBMODE_RESET 0x00000001
-#define BGE_MARBMODE_ENABLE 0x00000002
-#define BGE_MARBMODE_TX_ADDR_TRAP 0x00000004
-#define BGE_MARBMODE_RX_ADDR_TRAP 0x00000008
-#define BGE_MARBMODE_DMAW1_TRAP 0x00000010
-#define BGE_MARBMODE_DMAR1_TRAP 0x00000020
-#define BGE_MARBMODE_RXRISC_TRAP 0x00000040
-#define BGE_MARBMODE_TXRISC_TRAP 0x00000080
-#define BGE_MARBMODE_PCI_TRAP 0x00000100
-#define BGE_MARBMODE_DMAR2_TRAP 0x00000200
-#define BGE_MARBMODE_RXQ_TRAP 0x00000400
-#define BGE_MARBMODE_RXDI1_TRAP 0x00000800
-#define BGE_MARBMODE_RXDI2_TRAP 0x00001000
-#define BGE_MARBMODE_DC_GRPMEM_TRAP 0x00002000
-#define BGE_MARBMODE_HCOAL_TRAP 0x00004000
-#define BGE_MARBMODE_MBUF_TRAP 0x00008000
-#define BGE_MARBMODE_TXDI_TRAP 0x00010000
-#define BGE_MARBMODE_SDC_DMAC_TRAP 0x00020000
-#define BGE_MARBMODE_TXBD_TRAP 0x00040000
-#define BGE_MARBMODE_BUFFMAN_TRAP 0x00080000
-#define BGE_MARBMODE_DMAW2_TRAP 0x00100000
-#define BGE_MARBMODE_XTSSRAM_ROFLO_TRAP 0x00200000
-#define BGE_MARBMODE_XTSSRAM_RUFLO_TRAP 0x00400000
-#define BGE_MARBMODE_XTSSRAM_WOFLO_TRAP 0x00800000
-#define BGE_MARBMODE_XTSSRAM_WUFLO_TRAP 0x01000000
-#define BGE_MARBMODE_XTSSRAM_PERR_TRAP 0x02000000
+#define BGE_MARBMODE_RESET 0x00000001
+#define BGE_MARBMODE_ENABLE 0x00000002
+#define BGE_MARBMODE_TX_ADDR_TRAP 0x00000004
+#define BGE_MARBMODE_RX_ADDR_TRAP 0x00000008
+#define BGE_MARBMODE_DMAW1_TRAP 0x00000010
+#define BGE_MARBMODE_DMAR1_TRAP 0x00000020
+#define BGE_MARBMODE_RXRISC_TRAP 0x00000040
+#define BGE_MARBMODE_TXRISC_TRAP 0x00000080
+#define BGE_MARBMODE_PCI_TRAP 0x00000100
+#define BGE_MARBMODE_DMAR2_TRAP 0x00000200
+#define BGE_MARBMODE_RXQ_TRAP 0x00000400
+#define BGE_MARBMODE_RXDI1_TRAP 0x00000800
+#define BGE_MARBMODE_RXDI2_TRAP 0x00001000
+#define BGE_MARBMODE_DC_GRPMEM_TRAP 0x00002000
+#define BGE_MARBMODE_HCOAL_TRAP 0x00004000
+#define BGE_MARBMODE_MBUF_TRAP 0x00008000
+#define BGE_MARBMODE_TXDI_TRAP 0x00010000
+#define BGE_MARBMODE_SDC_DMAC_TRAP 0x00020000
+#define BGE_MARBMODE_TXBD_TRAP 0x00040000
+#define BGE_MARBMODE_BUFFMAN_TRAP 0x00080000
+#define BGE_MARBMODE_DMAW2_TRAP 0x00100000
+#define BGE_MARBMODE_XTSSRAM_ROFLO_TRAP 0x00200000
+#define BGE_MARBMODE_XTSSRAM_RUFLO_TRAP 0x00400000
+#define BGE_MARBMODE_XTSSRAM_WOFLO_TRAP 0x00800000
+#define BGE_MARBMODE_XTSSRAM_WUFLO_TRAP 0x01000000
+#define BGE_MARBMODE_XTSSRAM_PERR_TRAP 0x02000000
/* Memory arbiter status register */
-#define BGE_MARBSTAT_TX_ADDR_TRAP 0x00000004
-#define BGE_MARBSTAT_RX_ADDR_TRAP 0x00000008
-#define BGE_MARBSTAT_DMAW1_TRAP 0x00000010
-#define BGE_MARBSTAT_DMAR1_TRAP 0x00000020
-#define BGE_MARBSTAT_RXRISC_TRAP 0x00000040
-#define BGE_MARBSTAT_TXRISC_TRAP 0x00000080
-#define BGE_MARBSTAT_PCI_TRAP 0x00000100
-#define BGE_MARBSTAT_DMAR2_TRAP 0x00000200
-#define BGE_MARBSTAT_RXQ_TRAP 0x00000400
-#define BGE_MARBSTAT_RXDI1_TRAP 0x00000800
-#define BGE_MARBSTAT_RXDI2_TRAP 0x00001000
-#define BGE_MARBSTAT_DC_GRPMEM_TRAP 0x00002000
-#define BGE_MARBSTAT_HCOAL_TRAP 0x00004000
-#define BGE_MARBSTAT_MBUF_TRAP 0x00008000
-#define BGE_MARBSTAT_TXDI_TRAP 0x00010000
-#define BGE_MARBSTAT_SDC_DMAC_TRAP 0x00020000
-#define BGE_MARBSTAT_TXBD_TRAP 0x00040000
-#define BGE_MARBSTAT_BUFFMAN_TRAP 0x00080000
-#define BGE_MARBSTAT_DMAW2_TRAP 0x00100000
-#define BGE_MARBSTAT_XTSSRAM_ROFLO_TRAP 0x00200000
-#define BGE_MARBSTAT_XTSSRAM_RUFLO_TRAP 0x00400000
-#define BGE_MARBSTAT_XTSSRAM_WOFLO_TRAP 0x00800000
-#define BGE_MARBSTAT_XTSSRAM_WUFLO_TRAP 0x01000000
-#define BGE_MARBSTAT_XTSSRAM_PERR_TRAP 0x02000000
+#define BGE_MARBSTAT_TX_ADDR_TRAP 0x00000004
+#define BGE_MARBSTAT_RX_ADDR_TRAP 0x00000008
+#define BGE_MARBSTAT_DMAW1_TRAP 0x00000010
+#define BGE_MARBSTAT_DMAR1_TRAP 0x00000020
+#define BGE_MARBSTAT_RXRISC_TRAP 0x00000040
+#define BGE_MARBSTAT_TXRISC_TRAP 0x00000080
+#define BGE_MARBSTAT_PCI_TRAP 0x00000100
+#define BGE_MARBSTAT_DMAR2_TRAP 0x00000200
+#define BGE_MARBSTAT_RXQ_TRAP 0x00000400
+#define BGE_MARBSTAT_RXDI1_TRAP 0x00000800
+#define BGE_MARBSTAT_RXDI2_TRAP 0x00001000
+#define BGE_MARBSTAT_DC_GRPMEM_TRAP 0x00002000
+#define BGE_MARBSTAT_HCOAL_TRAP 0x00004000
+#define BGE_MARBSTAT_MBUF_TRAP 0x00008000
+#define BGE_MARBSTAT_TXDI_TRAP 0x00010000
+#define BGE_MARBSTAT_SDC_DMAC_TRAP 0x00020000
+#define BGE_MARBSTAT_TXBD_TRAP 0x00040000
+#define BGE_MARBSTAT_BUFFMAN_TRAP 0x00080000
+#define BGE_MARBSTAT_DMAW2_TRAP 0x00100000
+#define BGE_MARBSTAT_XTSSRAM_ROFLO_TRAP 0x00200000
+#define BGE_MARBSTAT_XTSSRAM_RUFLO_TRAP 0x00400000
+#define BGE_MARBSTAT_XTSSRAM_WOFLO_TRAP 0x00800000
+#define BGE_MARBSTAT_XTSSRAM_WUFLO_TRAP 0x01000000
+#define BGE_MARBSTAT_XTSSRAM_PERR_TRAP 0x02000000
/*
* Buffer manager control registers
*/
-#define BGE_BMAN_MODE 0x4400
-#define BGE_BMAN_STATUS 0x4404
-#define BGE_BMAN_MBUFPOOL_BASEADDR 0x4408
-#define BGE_BMAN_MBUFPOOL_LEN 0x440C
-#define BGE_BMAN_MBUFPOOL_READDMA_LOWAT 0x4410
-#define BGE_BMAN_MBUFPOOL_MACRX_LOWAT 0x4414
-#define BGE_BMAN_MBUFPOOL_HIWAT 0x4418
-#define BGE_BMAN_RXCPU_MBALLOC_REQ 0x441C
-#define BGE_BMAN_RXCPU_MBALLOC_RESP 0x4420
-#define BGE_BMAN_TXCPU_MBALLOC_REQ 0x4424
-#define BGE_BMAN_TXCPU_MBALLOC_RESP 0x4428
-#define BGE_BMAN_DMA_DESCPOOL_BASEADDR 0x442C
-#define BGE_BMAN_DMA_DESCPOOL_LEN 0x4430
-#define BGE_BMAN_DMA_DESCPOOL_LOWAT 0x4434
-#define BGE_BMAN_DMA_DESCPOOL_HIWAT 0x4438
-#define BGE_BMAN_RXCPU_DMAALLOC_REQ 0x443C
-#define BGE_BMAN_RXCPU_DMAALLOC_RESP 0x4440
-#define BGE_BMAN_TXCPU_DMAALLOC_REQ 0x4444
-#define BGE_BMAN_TXCPU_DMALLLOC_RESP 0x4448
-#define BGE_BMAN_HWDIAG_1 0x444C
-#define BGE_BMAN_HWDIAG_2 0x4450
-#define BGE_BMAN_HWDIAG_3 0x4454
+#define BGE_BMAN_MODE 0x4400
+#define BGE_BMAN_STATUS 0x4404
+#define BGE_BMAN_MBUFPOOL_BASEADDR 0x4408
+#define BGE_BMAN_MBUFPOOL_LEN 0x440C
+#define BGE_BMAN_MBUFPOOL_READDMA_LOWAT 0x4410
+#define BGE_BMAN_MBUFPOOL_MACRX_LOWAT 0x4414
+#define BGE_BMAN_MBUFPOOL_HIWAT 0x4418
+#define BGE_BMAN_RXCPU_MBALLOC_REQ 0x441C
+#define BGE_BMAN_RXCPU_MBALLOC_RESP 0x4420
+#define BGE_BMAN_TXCPU_MBALLOC_REQ 0x4424
+#define BGE_BMAN_TXCPU_MBALLOC_RESP 0x4428
+#define BGE_BMAN_DMA_DESCPOOL_BASEADDR 0x442C
+#define BGE_BMAN_DMA_DESCPOOL_LEN 0x4430
+#define BGE_BMAN_DMA_DESCPOOL_LOWAT 0x4434
+#define BGE_BMAN_DMA_DESCPOOL_HIWAT 0x4438
+#define BGE_BMAN_RXCPU_DMAALLOC_REQ 0x443C
+#define BGE_BMAN_RXCPU_DMAALLOC_RESP 0x4440
+#define BGE_BMAN_TXCPU_DMAALLOC_REQ 0x4444
+#define BGE_BMAN_TXCPU_DMALLLOC_RESP 0x4448
+#define BGE_BMAN_HWDIAG_1 0x444C
+#define BGE_BMAN_HWDIAG_2 0x4450
+#define BGE_BMAN_HWDIAG_3 0x4454
/* Buffer manager mode register */
-#define BGE_BMANMODE_RESET 0x00000001
-#define BGE_BMANMODE_ENABLE 0x00000002
-#define BGE_BMANMODE_ATTN 0x00000004
-#define BGE_BMANMODE_TESTMODE 0x00000008
-#define BGE_BMANMODE_LOMBUF_ATTN 0x00000010
+#define BGE_BMANMODE_RESET 0x00000001
+#define BGE_BMANMODE_ENABLE 0x00000002
+#define BGE_BMANMODE_ATTN 0x00000004
+#define BGE_BMANMODE_TESTMODE 0x00000008
+#define BGE_BMANMODE_LOMBUF_ATTN 0x00000010
/* Buffer manager status register */
-#define BGE_BMANSTAT_ERRO 0x00000004
-#define BGE_BMANSTAT_LOWMBUF_ERROR 0x00000010
+#define BGE_BMANSTAT_ERRO 0x00000004
+#define BGE_BMANSTAT_LOWMBUF_ERROR 0x00000010
/*
* Read DMA Control registers
*/
-#define BGE_RDMA_MODE 0x4800
-#define BGE_RDMA_STATUS 0x4804
+#define BGE_RDMA_MODE 0x4800
+#define BGE_RDMA_STATUS 0x4804
/* Read DMA mode register */
-#define BGE_RDMAMODE_RESET 0x00000001
-#define BGE_RDMAMODE_ENABLE 0x00000002
-#define BGE_RDMAMODE_PCI_TGT_ABRT_ATTN 0x00000004
-#define BGE_RDMAMODE_PCI_MSTR_ABRT_ATTN 0x00000008
-#define BGE_RDMAMODE_PCI_PERR_ATTN 0x00000010
-#define BGE_RDMAMODE_PCI_ADDROFLOW_ATTN 0x00000020
-#define BGE_RDMAMODE_PCI_FIFOOFLOW_ATTN 0x00000040
-#define BGE_RDMAMODE_PCI_FIFOUFLOW_ATTN 0x00000080
-#define BGE_RDMAMODE_PCI_FIFOOREAD_ATTN 0x00000100
-#define BGE_RDMAMODE_LOCWRITE_TOOBIG 0x00000200
-#define BGE_RDMAMODE_ALL_ATTNS 0x000003FC
+#define BGE_RDMAMODE_RESET 0x00000001
+#define BGE_RDMAMODE_ENABLE 0x00000002
+#define BGE_RDMAMODE_PCI_TGT_ABRT_ATTN 0x00000004
+#define BGE_RDMAMODE_PCI_MSTR_ABRT_ATTN 0x00000008
+#define BGE_RDMAMODE_PCI_PERR_ATTN 0x00000010
+#define BGE_RDMAMODE_PCI_ADDROFLOW_ATTN 0x00000020
+#define BGE_RDMAMODE_PCI_FIFOOFLOW_ATTN 0x00000040
+#define BGE_RDMAMODE_PCI_FIFOUFLOW_ATTN 0x00000080
+#define BGE_RDMAMODE_PCI_FIFOOREAD_ATTN 0x00000100
+#define BGE_RDMAMODE_LOCWRITE_TOOBIG 0x00000200
+#define BGE_RDMAMODE_ALL_ATTNS 0x000003FC
/* Read DMA status register */
-#define BGE_RDMASTAT_PCI_TGT_ABRT_ATTN 0x00000004
-#define BGE_RDMASTAT_PCI_MSTR_ABRT_ATTN 0x00000008
-#define BGE_RDMASTAT_PCI_PERR_ATTN 0x00000010
-#define BGE_RDMASTAT_PCI_ADDROFLOW_ATTN 0x00000020
-#define BGE_RDMASTAT_PCI_FIFOOFLOW_ATTN 0x00000040
-#define BGE_RDMASTAT_PCI_FIFOUFLOW_ATTN 0x00000080
-#define BGE_RDMASTAT_PCI_FIFOOREAD_ATTN 0x00000100
-#define BGE_RDMASTAT_LOCWRITE_TOOBIG 0x00000200
+#define BGE_RDMASTAT_PCI_TGT_ABRT_ATTN 0x00000004
+#define BGE_RDMASTAT_PCI_MSTR_ABRT_ATTN 0x00000008
+#define BGE_RDMASTAT_PCI_PERR_ATTN 0x00000010
+#define BGE_RDMASTAT_PCI_ADDROFLOW_ATTN 0x00000020
+#define BGE_RDMASTAT_PCI_FIFOOFLOW_ATTN 0x00000040
+#define BGE_RDMASTAT_PCI_FIFOUFLOW_ATTN 0x00000080
+#define BGE_RDMASTAT_PCI_FIFOOREAD_ATTN 0x00000100
+#define BGE_RDMASTAT_LOCWRITE_TOOBIG 0x00000200
/*
* Write DMA control registers
*/
-#define BGE_WDMA_MODE 0x4C00
-#define BGE_WDMA_STATUS 0x4C04
+#define BGE_WDMA_MODE 0x4C00
+#define BGE_WDMA_STATUS 0x4C04
/* Write DMA mode register */
-#define BGE_WDMAMODE_RESET 0x00000001
-#define BGE_WDMAMODE_ENABLE 0x00000002
-#define BGE_WDMAMODE_PCI_TGT_ABRT_ATTN 0x00000004
-#define BGE_WDMAMODE_PCI_MSTR_ABRT_ATTN 0x00000008
-#define BGE_WDMAMODE_PCI_PERR_ATTN 0x00000010
-#define BGE_WDMAMODE_PCI_ADDROFLOW_ATTN 0x00000020
-#define BGE_WDMAMODE_PCI_FIFOOFLOW_ATTN 0x00000040
-#define BGE_WDMAMODE_PCI_FIFOUFLOW_ATTN 0x00000080
-#define BGE_WDMAMODE_PCI_FIFOOREAD_ATTN 0x00000100
-#define BGE_WDMAMODE_LOCREAD_TOOBIG 0x00000200
-#define BGE_WDMAMODE_ALL_ATTNS 0x000003FC
+#define BGE_WDMAMODE_RESET 0x00000001
+#define BGE_WDMAMODE_ENABLE 0x00000002
+#define BGE_WDMAMODE_PCI_TGT_ABRT_ATTN 0x00000004
+#define BGE_WDMAMODE_PCI_MSTR_ABRT_ATTN 0x00000008
+#define BGE_WDMAMODE_PCI_PERR_ATTN 0x00000010
+#define BGE_WDMAMODE_PCI_ADDROFLOW_ATTN 0x00000020
+#define BGE_WDMAMODE_PCI_FIFOOFLOW_ATTN 0x00000040
+#define BGE_WDMAMODE_PCI_FIFOUFLOW_ATTN 0x00000080
+#define BGE_WDMAMODE_PCI_FIFOOREAD_ATTN 0x00000100
+#define BGE_WDMAMODE_LOCREAD_TOOBIG 0x00000200
+#define BGE_WDMAMODE_ALL_ATTNS 0x000003FC
/* Write DMA status register */
-#define BGE_WDMASTAT_PCI_TGT_ABRT_ATTN 0x00000004
-#define BGE_WDMASTAT_PCI_MSTR_ABRT_ATTN 0x00000008
-#define BGE_WDMASTAT_PCI_PERR_ATTN 0x00000010
-#define BGE_WDMASTAT_PCI_ADDROFLOW_ATTN 0x00000020
-#define BGE_WDMASTAT_PCI_FIFOOFLOW_ATTN 0x00000040
-#define BGE_WDMASTAT_PCI_FIFOUFLOW_ATTN 0x00000080
-#define BGE_WDMASTAT_PCI_FIFOOREAD_ATTN 0x00000100
-#define BGE_WDMASTAT_LOCREAD_TOOBIG 0x00000200
+#define BGE_WDMASTAT_PCI_TGT_ABRT_ATTN 0x00000004
+#define BGE_WDMASTAT_PCI_MSTR_ABRT_ATTN 0x00000008
+#define BGE_WDMASTAT_PCI_PERR_ATTN 0x00000010
+#define BGE_WDMASTAT_PCI_ADDROFLOW_ATTN 0x00000020
+#define BGE_WDMASTAT_PCI_FIFOOFLOW_ATTN 0x00000040
+#define BGE_WDMASTAT_PCI_FIFOUFLOW_ATTN 0x00000080
+#define BGE_WDMASTAT_PCI_FIFOOREAD_ATTN 0x00000100
+#define BGE_WDMASTAT_LOCREAD_TOOBIG 0x00000200
/*
* RX CPU registers
*/
-#define BGE_RXCPU_MODE 0x5000
-#define BGE_RXCPU_STATUS 0x5004
-#define BGE_RXCPU_PC 0x501C
+#define BGE_RXCPU_MODE 0x5000
+#define BGE_RXCPU_STATUS 0x5004
+#define BGE_RXCPU_PC 0x501C
/* RX CPU mode register */
-#define BGE_RXCPUMODE_RESET 0x00000001
-#define BGE_RXCPUMODE_SINGLESTEP 0x00000002
-#define BGE_RXCPUMODE_P0_DATAHLT_ENB 0x00000004
-#define BGE_RXCPUMODE_P0_INSTRHLT_ENB 0x00000008
-#define BGE_RXCPUMODE_WR_POSTBUF_ENB 0x00000010
-#define BGE_RXCPUMODE_DATACACHE_ENB 0x00000020
-#define BGE_RXCPUMODE_ROMFAIL 0x00000040
-#define BGE_RXCPUMODE_WATCHDOG_ENB 0x00000080
-#define BGE_RXCPUMODE_INSTRCACHE_PRF 0x00000100
-#define BGE_RXCPUMODE_INSTRCACHE_FLUSH 0x00000200
-#define BGE_RXCPUMODE_HALTCPU 0x00000400
-#define BGE_RXCPUMODE_INVDATAHLT_ENB 0x00000800
-#define BGE_RXCPUMODE_MADDRTRAPHLT_ENB 0x00001000
-#define BGE_RXCPUMODE_RADDRTRAPHLT_ENB 0x00002000
+#define BGE_RXCPUMODE_RESET 0x00000001
+#define BGE_RXCPUMODE_SINGLESTEP 0x00000002
+#define BGE_RXCPUMODE_P0_DATAHLT_ENB 0x00000004
+#define BGE_RXCPUMODE_P0_INSTRHLT_ENB 0x00000008
+#define BGE_RXCPUMODE_WR_POSTBUF_ENB 0x00000010
+#define BGE_RXCPUMODE_DATACACHE_ENB 0x00000020
+#define BGE_RXCPUMODE_ROMFAIL 0x00000040
+#define BGE_RXCPUMODE_WATCHDOG_ENB 0x00000080
+#define BGE_RXCPUMODE_INSTRCACHE_PRF 0x00000100
+#define BGE_RXCPUMODE_INSTRCACHE_FLUSH 0x00000200
+#define BGE_RXCPUMODE_HALTCPU 0x00000400
+#define BGE_RXCPUMODE_INVDATAHLT_ENB 0x00000800
+#define BGE_RXCPUMODE_MADDRTRAPHLT_ENB 0x00001000
+#define BGE_RXCPUMODE_RADDRTRAPHLT_ENB 0x00002000
/* RX CPU status register */
-#define BGE_RXCPUSTAT_HW_BREAKPOINT 0x00000001
-#define BGE_RXCPUSTAT_HLTINSTR_EXECUTED 0x00000002
-#define BGE_RXCPUSTAT_INVALID_INSTR 0x00000004
-#define BGE_RXCPUSTAT_P0_DATAREF 0x00000008
-#define BGE_RXCPUSTAT_P0_INSTRREF 0x00000010
-#define BGE_RXCPUSTAT_INVALID_DATAACC 0x00000020
-#define BGE_RXCPUSTAT_INVALID_INSTRFTCH 0x00000040
-#define BGE_RXCPUSTAT_BAD_MEMALIGN 0x00000080
-#define BGE_RXCPUSTAT_MADDR_TRAP 0x00000100
-#define BGE_RXCPUSTAT_REGADDR_TRAP 0x00000200
-#define BGE_RXCPUSTAT_DATAACC_STALL 0x00001000
-#define BGE_RXCPUSTAT_INSTRFETCH_STALL 0x00002000
-#define BGE_RXCPUSTAT_MA_WR_FIFOOFLOW 0x08000000
-#define BGE_RXCPUSTAT_MA_RD_FIFOOFLOW 0x10000000
-#define BGE_RXCPUSTAT_MA_DATAMASK_OFLOW 0x20000000
-#define BGE_RXCPUSTAT_MA_REQ_FIFOOFLOW 0x40000000
-#define BGE_RXCPUSTAT_BLOCKING_READ 0x80000000
+#define BGE_RXCPUSTAT_HW_BREAKPOINT 0x00000001
+#define BGE_RXCPUSTAT_HLTINSTR_EXECUTED 0x00000002
+#define BGE_RXCPUSTAT_INVALID_INSTR 0x00000004
+#define BGE_RXCPUSTAT_P0_DATAREF 0x00000008
+#define BGE_RXCPUSTAT_P0_INSTRREF 0x00000010
+#define BGE_RXCPUSTAT_INVALID_DATAACC 0x00000020
+#define BGE_RXCPUSTAT_INVALID_INSTRFTCH 0x00000040
+#define BGE_RXCPUSTAT_BAD_MEMALIGN 0x00000080
+#define BGE_RXCPUSTAT_MADDR_TRAP 0x00000100
+#define BGE_RXCPUSTAT_REGADDR_TRAP 0x00000200
+#define BGE_RXCPUSTAT_DATAACC_STALL 0x00001000
+#define BGE_RXCPUSTAT_INSTRFETCH_STALL 0x00002000
+#define BGE_RXCPUSTAT_MA_WR_FIFOOFLOW 0x08000000
+#define BGE_RXCPUSTAT_MA_RD_FIFOOFLOW 0x10000000
+#define BGE_RXCPUSTAT_MA_DATAMASK_OFLOW 0x20000000
+#define BGE_RXCPUSTAT_MA_REQ_FIFOOFLOW 0x40000000
+#define BGE_RXCPUSTAT_BLOCKING_READ 0x80000000
/*
* TX CPU registers
*/
-#define BGE_TXCPU_MODE 0x5400
-#define BGE_TXCPU_STATUS 0x5404
-#define BGE_TXCPU_PC 0x541C
+#define BGE_TXCPU_MODE 0x5400
+#define BGE_TXCPU_STATUS 0x5404
+#define BGE_TXCPU_PC 0x541C
/* TX CPU mode register */
-#define BGE_TXCPUMODE_RESET 0x00000001
-#define BGE_TXCPUMODE_SINGLESTEP 0x00000002
-#define BGE_TXCPUMODE_P0_DATAHLT_ENB 0x00000004
-#define BGE_TXCPUMODE_P0_INSTRHLT_ENB 0x00000008
-#define BGE_TXCPUMODE_WR_POSTBUF_ENB 0x00000010
-#define BGE_TXCPUMODE_DATACACHE_ENB 0x00000020
-#define BGE_TXCPUMODE_ROMFAIL 0x00000040
-#define BGE_TXCPUMODE_WATCHDOG_ENB 0x00000080
-#define BGE_TXCPUMODE_INSTRCACHE_PRF 0x00000100
-#define BGE_TXCPUMODE_INSTRCACHE_FLUSH 0x00000200
-#define BGE_TXCPUMODE_HALTCPU 0x00000400
-#define BGE_TXCPUMODE_INVDATAHLT_ENB 0x00000800
-#define BGE_TXCPUMODE_MADDRTRAPHLT_ENB 0x00001000
+#define BGE_TXCPUMODE_RESET 0x00000001
+#define BGE_TXCPUMODE_SINGLESTEP 0x00000002
+#define BGE_TXCPUMODE_P0_DATAHLT_ENB 0x00000004
+#define BGE_TXCPUMODE_P0_INSTRHLT_ENB 0x00000008
+#define BGE_TXCPUMODE_WR_POSTBUF_ENB 0x00000010
+#define BGE_TXCPUMODE_DATACACHE_ENB 0x00000020
+#define BGE_TXCPUMODE_ROMFAIL 0x00000040
+#define BGE_TXCPUMODE_WATCHDOG_ENB 0x00000080
+#define BGE_TXCPUMODE_INSTRCACHE_PRF 0x00000100
+#define BGE_TXCPUMODE_INSTRCACHE_FLUSH 0x00000200
+#define BGE_TXCPUMODE_HALTCPU 0x00000400
+#define BGE_TXCPUMODE_INVDATAHLT_ENB 0x00000800
+#define BGE_TXCPUMODE_MADDRTRAPHLT_ENB 0x00001000
/* TX CPU status register */
-#define BGE_TXCPUSTAT_HW_BREAKPOINT 0x00000001
-#define BGE_TXCPUSTAT_HLTINSTR_EXECUTED 0x00000002
-#define BGE_TXCPUSTAT_INVALID_INSTR 0x00000004
-#define BGE_TXCPUSTAT_P0_DATAREF 0x00000008
-#define BGE_TXCPUSTAT_P0_INSTRREF 0x00000010
-#define BGE_TXCPUSTAT_INVALID_DATAACC 0x00000020
-#define BGE_TXCPUSTAT_INVALID_INSTRFTCH 0x00000040
-#define BGE_TXCPUSTAT_BAD_MEMALIGN 0x00000080
-#define BGE_TXCPUSTAT_MADDR_TRAP 0x00000100
-#define BGE_TXCPUSTAT_REGADDR_TRAP 0x00000200
-#define BGE_TXCPUSTAT_DATAACC_STALL 0x00001000
-#define BGE_TXCPUSTAT_INSTRFETCH_STALL 0x00002000
-#define BGE_TXCPUSTAT_MA_WR_FIFOOFLOW 0x08000000
-#define BGE_TXCPUSTAT_MA_RD_FIFOOFLOW 0x10000000
-#define BGE_TXCPUSTAT_MA_DATAMASK_OFLOW 0x20000000
-#define BGE_TXCPUSTAT_MA_REQ_FIFOOFLOW 0x40000000
-#define BGE_TXCPUSTAT_BLOCKING_READ 0x80000000
+#define BGE_TXCPUSTAT_HW_BREAKPOINT 0x00000001
+#define BGE_TXCPUSTAT_HLTINSTR_EXECUTED 0x00000002
+#define BGE_TXCPUSTAT_INVALID_INSTR 0x00000004
+#define BGE_TXCPUSTAT_P0_DATAREF 0x00000008
+#define BGE_TXCPUSTAT_P0_INSTRREF 0x00000010
+#define BGE_TXCPUSTAT_INVALID_DATAACC 0x00000020
+#define BGE_TXCPUSTAT_INVALID_INSTRFTCH 0x00000040
+#define BGE_TXCPUSTAT_BAD_MEMALIGN 0x00000080
+#define BGE_TXCPUSTAT_MADDR_TRAP 0x00000100
+#define BGE_TXCPUSTAT_REGADDR_TRAP 0x00000200
+#define BGE_TXCPUSTAT_DATAACC_STALL 0x00001000
+#define BGE_TXCPUSTAT_INSTRFETCH_STALL 0x00002000
+#define BGE_TXCPUSTAT_MA_WR_FIFOOFLOW 0x08000000
+#define BGE_TXCPUSTAT_MA_RD_FIFOOFLOW 0x10000000
+#define BGE_TXCPUSTAT_MA_DATAMASK_OFLOW 0x20000000
+#define BGE_TXCPUSTAT_MA_REQ_FIFOOFLOW 0x40000000
+#define BGE_TXCPUSTAT_BLOCKING_READ 0x80000000
/*
* Low priority mailbox registers
*/
-#define BGE_LPMBX_IRQ0_HI 0x5800
-#define BGE_LPMBX_IRQ0_LO 0x5804
-#define BGE_LPMBX_IRQ1_HI 0x5808
-#define BGE_LPMBX_IRQ1_LO 0x580C
-#define BGE_LPMBX_IRQ2_HI 0x5810
-#define BGE_LPMBX_IRQ2_LO 0x5814
-#define BGE_LPMBX_IRQ3_HI 0x5818
-#define BGE_LPMBX_IRQ3_LO 0x581C
-#define BGE_LPMBX_GEN0_HI 0x5820
-#define BGE_LPMBX_GEN0_LO 0x5824
-#define BGE_LPMBX_GEN1_HI 0x5828
-#define BGE_LPMBX_GEN1_LO 0x582C
-#define BGE_LPMBX_GEN2_HI 0x5830
-#define BGE_LPMBX_GEN2_LO 0x5834
-#define BGE_LPMBX_GEN3_HI 0x5828
-#define BGE_LPMBX_GEN3_LO 0x582C
-#define BGE_LPMBX_GEN4_HI 0x5840
-#define BGE_LPMBX_GEN4_LO 0x5844
-#define BGE_LPMBX_GEN5_HI 0x5848
-#define BGE_LPMBX_GEN5_LO 0x584C
-#define BGE_LPMBX_GEN6_HI 0x5850
-#define BGE_LPMBX_GEN6_LO 0x5854
-#define BGE_LPMBX_GEN7_HI 0x5858
-#define BGE_LPMBX_GEN7_LO 0x585C
-#define BGE_LPMBX_RELOAD_STATS_HI 0x5860
-#define BGE_LPMBX_RELOAD_STATS_LO 0x5864
-#define BGE_LPMBX_RX_STD_PROD_HI 0x5868
-#define BGE_LPMBX_RX_STD_PROD_LO 0x586C
-#define BGE_LPMBX_RX_JUMBO_PROD_HI 0x5870
-#define BGE_LPMBX_RX_JUMBO_PROD_LO 0x5874
-#define BGE_LPMBX_RX_MINI_PROD_HI 0x5878
-#define BGE_LPMBX_RX_MINI_PROD_LO 0x587C
-#define BGE_LPMBX_RX_CONS0_HI 0x5880
-#define BGE_LPMBX_RX_CONS0_LO 0x5884
-#define BGE_LPMBX_RX_CONS1_HI 0x5888
-#define BGE_LPMBX_RX_CONS1_LO 0x588C
-#define BGE_LPMBX_RX_CONS2_HI 0x5890
-#define BGE_LPMBX_RX_CONS2_LO 0x5894
-#define BGE_LPMBX_RX_CONS3_HI 0x5898
-#define BGE_LPMBX_RX_CONS3_LO 0x589C
-#define BGE_LPMBX_RX_CONS4_HI 0x58A0
-#define BGE_LPMBX_RX_CONS4_LO 0x58A4
-#define BGE_LPMBX_RX_CONS5_HI 0x58A8
-#define BGE_LPMBX_RX_CONS5_LO 0x58AC
-#define BGE_LPMBX_RX_CONS6_HI 0x58B0
-#define BGE_LPMBX_RX_CONS6_LO 0x58B4
-#define BGE_LPMBX_RX_CONS7_HI 0x58B8
-#define BGE_LPMBX_RX_CONS7_LO 0x58BC
-#define BGE_LPMBX_RX_CONS8_HI 0x58C0
-#define BGE_LPMBX_RX_CONS8_LO 0x58C4
-#define BGE_LPMBX_RX_CONS9_HI 0x58C8
-#define BGE_LPMBX_RX_CONS9_LO 0x58CC
-#define BGE_LPMBX_RX_CONS10_HI 0x58D0
-#define BGE_LPMBX_RX_CONS10_LO 0x58D4
-#define BGE_LPMBX_RX_CONS11_HI 0x58D8
-#define BGE_LPMBX_RX_CONS11_LO 0x58DC
-#define BGE_LPMBX_RX_CONS12_HI 0x58E0
-#define BGE_LPMBX_RX_CONS12_LO 0x58E4
-#define BGE_LPMBX_RX_CONS13_HI 0x58E8
-#define BGE_LPMBX_RX_CONS13_LO 0x58EC
-#define BGE_LPMBX_RX_CONS14_HI 0x58F0
-#define BGE_LPMBX_RX_CONS14_LO 0x58F4
-#define BGE_LPMBX_RX_CONS15_HI 0x58F8
-#define BGE_LPMBX_RX_CONS15_LO 0x58FC
-#define BGE_LPMBX_TX_HOST_PROD0_HI 0x5900
-#define BGE_LPMBX_TX_HOST_PROD0_LO 0x5904
-#define BGE_LPMBX_TX_HOST_PROD1_HI 0x5908
-#define BGE_LPMBX_TX_HOST_PROD1_LO 0x590C
-#define BGE_LPMBX_TX_HOST_PROD2_HI 0x5910
-#define BGE_LPMBX_TX_HOST_PROD2_LO 0x5914
-#define BGE_LPMBX_TX_HOST_PROD3_HI 0x5918
-#define BGE_LPMBX_TX_HOST_PROD3_LO 0x591C
-#define BGE_LPMBX_TX_HOST_PROD4_HI 0x5920
-#define BGE_LPMBX_TX_HOST_PROD4_LO 0x5924
-#define BGE_LPMBX_TX_HOST_PROD5_HI 0x5928
-#define BGE_LPMBX_TX_HOST_PROD5_LO 0x592C
-#define BGE_LPMBX_TX_HOST_PROD6_HI 0x5930
-#define BGE_LPMBX_TX_HOST_PROD6_LO 0x5934
-#define BGE_LPMBX_TX_HOST_PROD7_HI 0x5938
-#define BGE_LPMBX_TX_HOST_PROD7_LO 0x593C
-#define BGE_LPMBX_TX_HOST_PROD8_HI 0x5940
-#define BGE_LPMBX_TX_HOST_PROD8_LO 0x5944
-#define BGE_LPMBX_TX_HOST_PROD9_HI 0x5948
-#define BGE_LPMBX_TX_HOST_PROD9_LO 0x594C
-#define BGE_LPMBX_TX_HOST_PROD10_HI 0x5950
-#define BGE_LPMBX_TX_HOST_PROD10_LO 0x5954
-#define BGE_LPMBX_TX_HOST_PROD11_HI 0x5958
-#define BGE_LPMBX_TX_HOST_PROD11_LO 0x595C
-#define BGE_LPMBX_TX_HOST_PROD12_HI 0x5960
-#define BGE_LPMBX_TX_HOST_PROD12_LO 0x5964
-#define BGE_LPMBX_TX_HOST_PROD13_HI 0x5968
-#define BGE_LPMBX_TX_HOST_PROD13_LO 0x596C
-#define BGE_LPMBX_TX_HOST_PROD14_HI 0x5970
-#define BGE_LPMBX_TX_HOST_PROD14_LO 0x5974
-#define BGE_LPMBX_TX_HOST_PROD15_HI 0x5978
-#define BGE_LPMBX_TX_HOST_PROD15_LO 0x597C
-#define BGE_LPMBX_TX_NIC_PROD0_HI 0x5980
-#define BGE_LPMBX_TX_NIC_PROD0_LO 0x5984
-#define BGE_LPMBX_TX_NIC_PROD1_HI 0x5988
-#define BGE_LPMBX_TX_NIC_PROD1_LO 0x598C
-#define BGE_LPMBX_TX_NIC_PROD2_HI 0x5990
-#define BGE_LPMBX_TX_NIC_PROD2_LO 0x5994
-#define BGE_LPMBX_TX_NIC_PROD3_HI 0x5998
-#define BGE_LPMBX_TX_NIC_PROD3_LO 0x599C
-#define BGE_LPMBX_TX_NIC_PROD4_HI 0x59A0
-#define BGE_LPMBX_TX_NIC_PROD4_LO 0x59A4
-#define BGE_LPMBX_TX_NIC_PROD5_HI 0x59A8
-#define BGE_LPMBX_TX_NIC_PROD5_LO 0x59AC
-#define BGE_LPMBX_TX_NIC_PROD6_HI 0x59B0
-#define BGE_LPMBX_TX_NIC_PROD6_LO 0x59B4
-#define BGE_LPMBX_TX_NIC_PROD7_HI 0x59B8
-#define BGE_LPMBX_TX_NIC_PROD7_LO 0x59BC
-#define BGE_LPMBX_TX_NIC_PROD8_HI 0x59C0
-#define BGE_LPMBX_TX_NIC_PROD8_LO 0x59C4
-#define BGE_LPMBX_TX_NIC_PROD9_HI 0x59C8
-#define BGE_LPMBX_TX_NIC_PROD9_LO 0x59CC
-#define BGE_LPMBX_TX_NIC_PROD10_HI 0x59D0
-#define BGE_LPMBX_TX_NIC_PROD10_LO 0x59D4
-#define BGE_LPMBX_TX_NIC_PROD11_HI 0x59D8
-#define BGE_LPMBX_TX_NIC_PROD11_LO 0x59DC
-#define BGE_LPMBX_TX_NIC_PROD12_HI 0x59E0
-#define BGE_LPMBX_TX_NIC_PROD12_LO 0x59E4
-#define BGE_LPMBX_TX_NIC_PROD13_HI 0x59E8
-#define BGE_LPMBX_TX_NIC_PROD13_LO 0x59EC
-#define BGE_LPMBX_TX_NIC_PROD14_HI 0x59F0
-#define BGE_LPMBX_TX_NIC_PROD14_LO 0x59F4
-#define BGE_LPMBX_TX_NIC_PROD15_HI 0x59F8
-#define BGE_LPMBX_TX_NIC_PROD15_LO 0x59FC
+#define BGE_LPMBX_IRQ0_HI 0x5800
+#define BGE_LPMBX_IRQ0_LO 0x5804
+#define BGE_LPMBX_IRQ1_HI 0x5808
+#define BGE_LPMBX_IRQ1_LO 0x580C
+#define BGE_LPMBX_IRQ2_HI 0x5810
+#define BGE_LPMBX_IRQ2_LO 0x5814
+#define BGE_LPMBX_IRQ3_HI 0x5818
+#define BGE_LPMBX_IRQ3_LO 0x581C
+#define BGE_LPMBX_GEN0_HI 0x5820
+#define BGE_LPMBX_GEN0_LO 0x5824
+#define BGE_LPMBX_GEN1_HI 0x5828
+#define BGE_LPMBX_GEN1_LO 0x582C
+#define BGE_LPMBX_GEN2_HI 0x5830
+#define BGE_LPMBX_GEN2_LO 0x5834
+#define BGE_LPMBX_GEN3_HI 0x5828
+#define BGE_LPMBX_GEN3_LO 0x582C
+#define BGE_LPMBX_GEN4_HI 0x5840
+#define BGE_LPMBX_GEN4_LO 0x5844
+#define BGE_LPMBX_GEN5_HI 0x5848
+#define BGE_LPMBX_GEN5_LO 0x584C
+#define BGE_LPMBX_GEN6_HI 0x5850
+#define BGE_LPMBX_GEN6_LO 0x5854
+#define BGE_LPMBX_GEN7_HI 0x5858
+#define BGE_LPMBX_GEN7_LO 0x585C
+#define BGE_LPMBX_RELOAD_STATS_HI 0x5860
+#define BGE_LPMBX_RELOAD_STATS_LO 0x5864
+#define BGE_LPMBX_RX_STD_PROD_HI 0x5868
+#define BGE_LPMBX_RX_STD_PROD_LO 0x586C
+#define BGE_LPMBX_RX_JUMBO_PROD_HI 0x5870
+#define BGE_LPMBX_RX_JUMBO_PROD_LO 0x5874
+#define BGE_LPMBX_RX_MINI_PROD_HI 0x5878
+#define BGE_LPMBX_RX_MINI_PROD_LO 0x587C
+#define BGE_LPMBX_RX_CONS0_HI 0x5880
+#define BGE_LPMBX_RX_CONS0_LO 0x5884
+#define BGE_LPMBX_RX_CONS1_HI 0x5888
+#define BGE_LPMBX_RX_CONS1_LO 0x588C
+#define BGE_LPMBX_RX_CONS2_HI 0x5890
+#define BGE_LPMBX_RX_CONS2_LO 0x5894
+#define BGE_LPMBX_RX_CONS3_HI 0x5898
+#define BGE_LPMBX_RX_CONS3_LO 0x589C
+#define BGE_LPMBX_RX_CONS4_HI 0x58A0
+#define BGE_LPMBX_RX_CONS4_LO 0x58A4
+#define BGE_LPMBX_RX_CONS5_HI 0x58A8
+#define BGE_LPMBX_RX_CONS5_LO 0x58AC
+#define BGE_LPMBX_RX_CONS6_HI 0x58B0
+#define BGE_LPMBX_RX_CONS6_LO 0x58B4
+#define BGE_LPMBX_RX_CONS7_HI 0x58B8
+#define BGE_LPMBX_RX_CONS7_LO 0x58BC
+#define BGE_LPMBX_RX_CONS8_HI 0x58C0
+#define BGE_LPMBX_RX_CONS8_LO 0x58C4
+#define BGE_LPMBX_RX_CONS9_HI 0x58C8
+#define BGE_LPMBX_RX_CONS9_LO 0x58CC
+#define BGE_LPMBX_RX_CONS10_HI 0x58D0
+#define BGE_LPMBX_RX_CONS10_LO 0x58D4
+#define BGE_LPMBX_RX_CONS11_HI 0x58D8
+#define BGE_LPMBX_RX_CONS11_LO 0x58DC
+#define BGE_LPMBX_RX_CONS12_HI 0x58E0
+#define BGE_LPMBX_RX_CONS12_LO 0x58E4
+#define BGE_LPMBX_RX_CONS13_HI 0x58E8
+#define BGE_LPMBX_RX_CONS13_LO 0x58EC
+#define BGE_LPMBX_RX_CONS14_HI 0x58F0
+#define BGE_LPMBX_RX_CONS14_LO 0x58F4
+#define BGE_LPMBX_RX_CONS15_HI 0x58F8
+#define BGE_LPMBX_RX_CONS15_LO 0x58FC
+#define BGE_LPMBX_TX_HOST_PROD0_HI 0x5900
+#define BGE_LPMBX_TX_HOST_PROD0_LO 0x5904
+#define BGE_LPMBX_TX_HOST_PROD1_HI 0x5908
+#define BGE_LPMBX_TX_HOST_PROD1_LO 0x590C
+#define BGE_LPMBX_TX_HOST_PROD2_HI 0x5910
+#define BGE_LPMBX_TX_HOST_PROD2_LO 0x5914
+#define BGE_LPMBX_TX_HOST_PROD3_HI 0x5918
+#define BGE_LPMBX_TX_HOST_PROD3_LO 0x591C
+#define BGE_LPMBX_TX_HOST_PROD4_HI 0x5920
+#define BGE_LPMBX_TX_HOST_PROD4_LO 0x5924
+#define BGE_LPMBX_TX_HOST_PROD5_HI 0x5928
+#define BGE_LPMBX_TX_HOST_PROD5_LO 0x592C
+#define BGE_LPMBX_TX_HOST_PROD6_HI 0x5930
+#define BGE_LPMBX_TX_HOST_PROD6_LO 0x5934
+#define BGE_LPMBX_TX_HOST_PROD7_HI 0x5938
+#define BGE_LPMBX_TX_HOST_PROD7_LO 0x593C
+#define BGE_LPMBX_TX_HOST_PROD8_HI 0x5940
+#define BGE_LPMBX_TX_HOST_PROD8_LO 0x5944
+#define BGE_LPMBX_TX_HOST_PROD9_HI 0x5948
+#define BGE_LPMBX_TX_HOST_PROD9_LO 0x594C
+#define BGE_LPMBX_TX_HOST_PROD10_HI 0x5950
+#define BGE_LPMBX_TX_HOST_PROD10_LO 0x5954
+#define BGE_LPMBX_TX_HOST_PROD11_HI 0x5958
+#define BGE_LPMBX_TX_HOST_PROD11_LO 0x595C
+#define BGE_LPMBX_TX_HOST_PROD12_HI 0x5960
+#define BGE_LPMBX_TX_HOST_PROD12_LO 0x5964
+#define BGE_LPMBX_TX_HOST_PROD13_HI 0x5968
+#define BGE_LPMBX_TX_HOST_PROD13_LO 0x596C
+#define BGE_LPMBX_TX_HOST_PROD14_HI 0x5970
+#define BGE_LPMBX_TX_HOST_PROD14_LO 0x5974
+#define BGE_LPMBX_TX_HOST_PROD15_HI 0x5978
+#define BGE_LPMBX_TX_HOST_PROD15_LO 0x597C
+#define BGE_LPMBX_TX_NIC_PROD0_HI 0x5980
+#define BGE_LPMBX_TX_NIC_PROD0_LO 0x5984
+#define BGE_LPMBX_TX_NIC_PROD1_HI 0x5988
+#define BGE_LPMBX_TX_NIC_PROD1_LO 0x598C
+#define BGE_LPMBX_TX_NIC_PROD2_HI 0x5990
+#define BGE_LPMBX_TX_NIC_PROD2_LO 0x5994
+#define BGE_LPMBX_TX_NIC_PROD3_HI 0x5998
+#define BGE_LPMBX_TX_NIC_PROD3_LO 0x599C
+#define BGE_LPMBX_TX_NIC_PROD4_HI 0x59A0
+#define BGE_LPMBX_TX_NIC_PROD4_LO 0x59A4
+#define BGE_LPMBX_TX_NIC_PROD5_HI 0x59A8
+#define BGE_LPMBX_TX_NIC_PROD5_LO 0x59AC
+#define BGE_LPMBX_TX_NIC_PROD6_HI 0x59B0
+#define BGE_LPMBX_TX_NIC_PROD6_LO 0x59B4
+#define BGE_LPMBX_TX_NIC_PROD7_HI 0x59B8
+#define BGE_LPMBX_TX_NIC_PROD7_LO 0x59BC
+#define BGE_LPMBX_TX_NIC_PROD8_HI 0x59C0
+#define BGE_LPMBX_TX_NIC_PROD8_LO 0x59C4
+#define BGE_LPMBX_TX_NIC_PROD9_HI 0x59C8
+#define BGE_LPMBX_TX_NIC_PROD9_LO 0x59CC
+#define BGE_LPMBX_TX_NIC_PROD10_HI 0x59D0
+#define BGE_LPMBX_TX_NIC_PROD10_LO 0x59D4
+#define BGE_LPMBX_TX_NIC_PROD11_HI 0x59D8
+#define BGE_LPMBX_TX_NIC_PROD11_LO 0x59DC
+#define BGE_LPMBX_TX_NIC_PROD12_HI 0x59E0
+#define BGE_LPMBX_TX_NIC_PROD12_LO 0x59E4
+#define BGE_LPMBX_TX_NIC_PROD13_HI 0x59E8
+#define BGE_LPMBX_TX_NIC_PROD13_LO 0x59EC
+#define BGE_LPMBX_TX_NIC_PROD14_HI 0x59F0
+#define BGE_LPMBX_TX_NIC_PROD14_LO 0x59F4
+#define BGE_LPMBX_TX_NIC_PROD15_HI 0x59F8
+#define BGE_LPMBX_TX_NIC_PROD15_LO 0x59FC
/*
* Flow throw Queue reset register
*/
-#define BGE_FTQ_RESET 0x5C00
+#define BGE_FTQ_RESET 0x5C00
-#define BGE_FTQRESET_DMAREAD 0x00000002
-#define BGE_FTQRESET_DMAHIPRIO_RD 0x00000004
-#define BGE_FTQRESET_DMADONE 0x00000010
-#define BGE_FTQRESET_SBDC 0x00000020
-#define BGE_FTQRESET_SDI 0x00000040
-#define BGE_FTQRESET_WDMA 0x00000080
-#define BGE_FTQRESET_DMAHIPRIO_WR 0x00000100
-#define BGE_FTQRESET_TYPE1_SOFTWARE 0x00000200
-#define BGE_FTQRESET_SDC 0x00000400
-#define BGE_FTQRESET_HCC 0x00000800
-#define BGE_FTQRESET_TXFIFO 0x00001000
-#define BGE_FTQRESET_MBC 0x00002000
-#define BGE_FTQRESET_RBDC 0x00004000
-#define BGE_FTQRESET_RXLP 0x00008000
-#define BGE_FTQRESET_RDBDI 0x00010000
-#define BGE_FTQRESET_RDC 0x00020000
-#define BGE_FTQRESET_TYPE2_SOFTWARE 0x00040000
+#define BGE_FTQRESET_DMAREAD 0x00000002
+#define BGE_FTQRESET_DMAHIPRIO_RD 0x00000004
+#define BGE_FTQRESET_DMADONE 0x00000010
+#define BGE_FTQRESET_SBDC 0x00000020
+#define BGE_FTQRESET_SDI 0x00000040
+#define BGE_FTQRESET_WDMA 0x00000080
+#define BGE_FTQRESET_DMAHIPRIO_WR 0x00000100
+#define BGE_FTQRESET_TYPE1_SOFTWARE 0x00000200
+#define BGE_FTQRESET_SDC 0x00000400
+#define BGE_FTQRESET_HCC 0x00000800
+#define BGE_FTQRESET_TXFIFO 0x00001000
+#define BGE_FTQRESET_MBC 0x00002000
+#define BGE_FTQRESET_RBDC 0x00004000
+#define BGE_FTQRESET_RXLP 0x00008000
+#define BGE_FTQRESET_RDBDI 0x00010000
+#define BGE_FTQRESET_RDC 0x00020000
+#define BGE_FTQRESET_TYPE2_SOFTWARE 0x00040000
/*
* Message Signaled Interrupt registers
*/
-#define BGE_MSI_MODE 0x6000
-#define BGE_MSI_STATUS 0x6004
-#define BGE_MSI_FIFOACCESS 0x6008
+#define BGE_MSI_MODE 0x6000
+#define BGE_MSI_STATUS 0x6004
+#define BGE_MSI_FIFOACCESS 0x6008
/* MSI mode register */
-#define BGE_MSIMODE_RESET 0x00000001
-#define BGE_MSIMODE_ENABLE 0x00000002
-#define BGE_MSIMODE_PCI_TGT_ABRT_ATTN 0x00000004
-#define BGE_MSIMODE_PCI_MSTR_ABRT_ATTN 0x00000008
-#define BGE_MSIMODE_PCI_PERR_ATTN 0x00000010
-#define BGE_MSIMODE_MSI_FIFOUFLOW_ATTN 0x00000020
-#define BGE_MSIMODE_MSI_FIFOOFLOW_ATTN 0x00000040
+#define BGE_MSIMODE_RESET 0x00000001
+#define BGE_MSIMODE_ENABLE 0x00000002
+#define BGE_MSIMODE_PCI_TGT_ABRT_ATTN 0x00000004
+#define BGE_MSIMODE_PCI_MSTR_ABRT_ATTN 0x00000008
+#define BGE_MSIMODE_PCI_PERR_ATTN 0x00000010
+#define BGE_MSIMODE_MSI_FIFOUFLOW_ATTN 0x00000020
+#define BGE_MSIMODE_MSI_FIFOOFLOW_ATTN 0x00000040
/* MSI status register */
-#define BGE_MSISTAT_PCI_TGT_ABRT_ATTN 0x00000004
-#define BGE_MSISTAT_PCI_MSTR_ABRT_ATTN 0x00000008
-#define BGE_MSISTAT_PCI_PERR_ATTN 0x00000010
-#define BGE_MSISTAT_MSI_FIFOUFLOW_ATTN 0x00000020
-#define BGE_MSISTAT_MSI_FIFOOFLOW_ATTN 0x00000040
+#define BGE_MSISTAT_PCI_TGT_ABRT_ATTN 0x00000004
+#define BGE_MSISTAT_PCI_MSTR_ABRT_ATTN 0x00000008
+#define BGE_MSISTAT_PCI_PERR_ATTN 0x00000010
+#define BGE_MSISTAT_MSI_FIFOUFLOW_ATTN 0x00000020
+#define BGE_MSISTAT_MSI_FIFOOFLOW_ATTN 0x00000040
/*
* DMA Completion registers
*/
-#define BGE_DMAC_MODE 0x6400
+#define BGE_DMAC_MODE 0x6400
/* DMA Completion mode register */
-#define BGE_DMACMODE_RESET 0x00000001
-#define BGE_DMACMODE_ENABLE 0x00000002
+#define BGE_DMACMODE_RESET 0x00000001
+#define BGE_DMACMODE_ENABLE 0x00000002
/*
* General control registers.
*/
-#define BGE_MODE_CTL 0x6800
-#define BGE_MISC_CFG 0x6804
-#define BGE_MISC_LOCAL_CTL 0x6808
-#define BGE_EE_ADDR 0x6838
-#define BGE_EE_DATA 0x683C
-#define BGE_EE_CTL 0x6840
-#define BGE_MDI_CTL 0x6844
-#define BGE_EE_DELAY 0x6848
+#define BGE_MODE_CTL 0x6800
+#define BGE_MISC_CFG 0x6804
+#define BGE_MISC_LOCAL_CTL 0x6808
+#define BGE_CPU_EVENT 0x6810
+#define BGE_EE_ADDR 0x6838
+#define BGE_EE_DATA 0x683C
+#define BGE_EE_CTL 0x6840
+#define BGE_MDI_CTL 0x6844
+#define BGE_EE_DELAY 0x6848
+#define BGE_FASTBOOT_PC 0x6894
/* Mode control register */
-#define BGE_MODECTL_INT_SNDCOAL_ONLY 0x00000001
-#define BGE_MODECTL_BYTESWAP_NONFRAME 0x00000002
-#define BGE_MODECTL_WORDSWAP_NONFRAME 0x00000004
-#define BGE_MODECTL_BYTESWAP_DATA 0x00000010
-#define BGE_MODECTL_WORDSWAP_DATA 0x00000020
-#define BGE_MODECTL_NO_FRAME_CRACKING 0x00000200
-#define BGE_MODECTL_NO_RX_CRC 0x00000400
-#define BGE_MODECTL_RX_BADFRAMES 0x00000800
-#define BGE_MODECTL_NO_TX_INTR 0x00002000
-#define BGE_MODECTL_NO_RX_INTR 0x00004000
-#define BGE_MODECTL_FORCE_PCI32 0x00008000
-#define BGE_MODECTL_STACKUP 0x00010000
-#define BGE_MODECTL_HOST_SEND_BDS 0x00020000
-#define BGE_MODECTL_TX_NO_PHDR_CSUM 0x00100000
-#define BGE_MODECTL_RX_NO_PHDR_CSUM 0x00800000
-#define BGE_MODECTL_TX_ATTN_INTR 0x01000000
-#define BGE_MODECTL_RX_ATTN_INTR 0x02000000
-#define BGE_MODECTL_MAC_ATTN_INTR 0x04000000
-#define BGE_MODECTL_DMA_ATTN_INTR 0x08000000
-#define BGE_MODECTL_FLOWCTL_ATTN_INTR 0x10000000
-#define BGE_MODECTL_4X_SENDRING_SZ 0x20000000
-#define BGE_MODECTL_FW_PROCESS_MCASTS 0x40000000
+#define BGE_MODECTL_INT_SNDCOAL_ONLY 0x00000001
+#define BGE_MODECTL_BYTESWAP_NONFRAME 0x00000002
+#define BGE_MODECTL_WORDSWAP_NONFRAME 0x00000004
+#define BGE_MODECTL_BYTESWAP_DATA 0x00000010
+#define BGE_MODECTL_WORDSWAP_DATA 0x00000020
+#define BGE_MODECTL_NO_FRAME_CRACKING 0x00000200
+#define BGE_MODECTL_NO_RX_CRC 0x00000400
+#define BGE_MODECTL_RX_BADFRAMES 0x00000800
+#define BGE_MODECTL_NO_TX_INTR 0x00002000
+#define BGE_MODECTL_NO_RX_INTR 0x00004000
+#define BGE_MODECTL_FORCE_PCI32 0x00008000
+#define BGE_MODECTL_STACKUP 0x00010000
+#define BGE_MODECTL_HOST_SEND_BDS 0x00020000
+#define BGE_MODECTL_TX_NO_PHDR_CSUM 0x00100000
+#define BGE_MODECTL_RX_NO_PHDR_CSUM 0x00800000
+#define BGE_MODECTL_TX_ATTN_INTR 0x01000000
+#define BGE_MODECTL_RX_ATTN_INTR 0x02000000
+#define BGE_MODECTL_MAC_ATTN_INTR 0x04000000
+#define BGE_MODECTL_DMA_ATTN_INTR 0x08000000
+#define BGE_MODECTL_FLOWCTL_ATTN_INTR 0x10000000
+#define BGE_MODECTL_4X_SENDRING_SZ 0x20000000
+#define BGE_MODECTL_FW_PROCESS_MCASTS 0x40000000
/* Misc. config register */
-#define BGE_MISCCFG_RESET_CORE_CLOCKS 0x00000001
-#define BGE_MISCCFG_TIMER_PRESCALER 0x000000FE
+#define BGE_MISCCFG_RESET_CORE_CLOCKS 0x00000001
+#define BGE_MISCCFG_TIMER_PRESCALER 0x000000FE
-#define BGE_32BITTIME_66MHZ (0x41 << 1)
+#define BGE_32BITTIME_66MHZ (0x41 << 1)
/* Misc. Local Control */
-#define BGE_MLC_INTR_STATE 0x00000001
-#define BGE_MLC_INTR_CLR 0x00000002
-#define BGE_MLC_INTR_SET 0x00000004
-#define BGE_MLC_INTR_ONATTN 0x00000008
-#define BGE_MLC_MISCIO_IN0 0x00000100
-#define BGE_MLC_MISCIO_IN1 0x00000200
-#define BGE_MLC_MISCIO_IN2 0x00000400
-#define BGE_MLC_MISCIO_OUTEN0 0x00000800
-#define BGE_MLC_MISCIO_OUTEN1 0x00001000
-#define BGE_MLC_MISCIO_OUTEN2 0x00002000
-#define BGE_MLC_MISCIO_OUT0 0x00004000
-#define BGE_MLC_MISCIO_OUT1 0x00008000
-#define BGE_MLC_MISCIO_OUT2 0x00010000
-#define BGE_MLC_EXTRAM_ENB 0x00020000
-#define BGE_MLC_SRAM_SIZE 0x001C0000
-#define BGE_MLC_BANK_SEL 0x00200000 /* 0 = 2 banks, 1 == 1 */
-#define BGE_MLC_SSRAM_TYPE 0x00400000 /* 1 = ZBT, 0 = standard */
-#define BGE_MLC_SSRAM_CYC_DESEL 0x00800000
-#define BGE_MLC_AUTO_EEPROM 0x01000000
-
-#define BGE_SSRAMSIZE_256KB 0x00000000
-#define BGE_SSRAMSIZE_512KB 0x00040000
-#define BGE_SSRAMSIZE_1MB 0x00080000
-#define BGE_SSRAMSIZE_2MB 0x000C0000
-#define BGE_SSRAMSIZE_4MB 0x00100000
-#define BGE_SSRAMSIZE_8MB 0x00140000
-#define BGE_SSRAMSIZE_16M 0x00180000
+#define BGE_MLC_INTR_STATE 0x00000001
+#define BGE_MLC_INTR_CLR 0x00000002
+#define BGE_MLC_INTR_SET 0x00000004
+#define BGE_MLC_INTR_ONATTN 0x00000008
+#define BGE_MLC_MISCIO_IN0 0x00000100
+#define BGE_MLC_MISCIO_IN1 0x00000200
+#define BGE_MLC_MISCIO_IN2 0x00000400
+#define BGE_MLC_MISCIO_OUTEN0 0x00000800
+#define BGE_MLC_MISCIO_OUTEN1 0x00001000
+#define BGE_MLC_MISCIO_OUTEN2 0x00002000
+#define BGE_MLC_MISCIO_OUT0 0x00004000
+#define BGE_MLC_MISCIO_OUT1 0x00008000
+#define BGE_MLC_MISCIO_OUT2 0x00010000
+#define BGE_MLC_EXTRAM_ENB 0x00020000
+#define BGE_MLC_SRAM_SIZE 0x001C0000
+#define BGE_MLC_BANK_SEL 0x00200000 /* 0 = 2 banks, 1 == 1 */
+#define BGE_MLC_SSRAM_TYPE 0x00400000 /* 1 = ZBT, 0 = standard */
+#define BGE_MLC_SSRAM_CYC_DESEL 0x00800000
+#define BGE_MLC_AUTO_EEPROM 0x01000000
+
+#define BGE_SSRAMSIZE_256KB 0x00000000
+#define BGE_SSRAMSIZE_512KB 0x00040000
+#define BGE_SSRAMSIZE_1MB 0x00080000
+#define BGE_SSRAMSIZE_2MB 0x000C0000
+#define BGE_SSRAMSIZE_4MB 0x00100000
+#define BGE_SSRAMSIZE_8MB 0x00140000
+#define BGE_SSRAMSIZE_16M 0x00180000
/* EEPROM address register */
-#define BGE_EEADDR_ADDRESS 0x0000FFFC
-#define BGE_EEADDR_HALFCLK 0x01FF0000
-#define BGE_EEADDR_START 0x02000000
-#define BGE_EEADDR_DEVID 0x1C000000
-#define BGE_EEADDR_RESET 0x20000000
-#define BGE_EEADDR_DONE 0x40000000
-#define BGE_EEADDR_RW 0x80000000 /* 1 = rd, 0 = wr */
-
-#define BGE_EEDEVID(x) ((x & 7) << 26)
-#define BGE_EEHALFCLK(x) ((x & 0x1FF) << 16)
-#define BGE_HALFCLK_384SCL 0x60
-#define BGE_EE_READCMD \
+#define BGE_EEADDR_ADDRESS 0x0000FFFC
+#define BGE_EEADDR_HALFCLK 0x01FF0000
+#define BGE_EEADDR_START 0x02000000
+#define BGE_EEADDR_DEVID 0x1C000000
+#define BGE_EEADDR_RESET 0x20000000
+#define BGE_EEADDR_DONE 0x40000000
+#define BGE_EEADDR_RW 0x80000000 /* 1 = rd, 0 = wr */
+
+#define BGE_EEDEVID(x) ((x & 7) << 26)
+#define BGE_EEHALFCLK(x) ((x & 0x1FF) << 16)
+#define BGE_HALFCLK_384SCL 0x60
+#define BGE_EE_READCMD \
(BGE_EEHALFCLK(BGE_HALFCLK_384SCL)|BGE_EEDEVID(0)| \
BGE_EEADDR_START|BGE_EEADDR_RW|BGE_EEADDR_DONE)
-#define BGE_EE_WRCMD \
+#define BGE_EE_WRCMD \
(BGE_EEHALFCLK(BGE_HALFCLK_384SCL)|BGE_EEDEVID(0)| \
BGE_EEADDR_START|BGE_EEADDR_DONE)
/* EEPROM Control register */
-#define BGE_EECTL_CLKOUT_TRISTATE 0x00000001
-#define BGE_EECTL_CLKOUT 0x00000002
-#define BGE_EECTL_CLKIN 0x00000004
-#define BGE_EECTL_DATAOUT_TRISTATE 0x00000008
-#define BGE_EECTL_DATAOUT 0x00000010
-#define BGE_EECTL_DATAIN 0x00000020
+#define BGE_EECTL_CLKOUT_TRISTATE 0x00000001
+#define BGE_EECTL_CLKOUT 0x00000002
+#define BGE_EECTL_CLKIN 0x00000004
+#define BGE_EECTL_DATAOUT_TRISTATE 0x00000008
+#define BGE_EECTL_DATAOUT 0x00000010
+#define BGE_EECTL_DATAIN 0x00000020
/* MDI (MII/GMII) access register */
-#define BGE_MDI_DATA 0x00000001
-#define BGE_MDI_DIR 0x00000002
-#define BGE_MDI_SEL 0x00000004
-#define BGE_MDI_CLK 0x00000008
+#define BGE_MDI_DATA 0x00000001
+#define BGE_MDI_DIR 0x00000002
+#define BGE_MDI_SEL 0x00000004
+#define BGE_MDI_CLK 0x00000008
-#define BGE_MEMWIN_START 0x00008000
-#define BGE_MEMWIN_END 0x0000FFFF
+#define BGE_MEMWIN_START 0x00008000
+#define BGE_MEMWIN_END 0x0000FFFF
-#define BGE_MEMWIN_READ(sc, x, val) \
+#define BGE_MEMWIN_READ(sc, x, val) \
do { \
pci_write_config(sc->bge_dev, BGE_PCI_MEMWIN_BASEADDR, \
(0xFFFF0000 & x), 4); \
val = CSR_READ_4(sc, BGE_MEMWIN_START + (x & 0xFFFF)); \
} while(0)
-#define BGE_MEMWIN_WRITE(sc, x, val) \
+#define BGE_MEMWIN_WRITE(sc, x, val) \
do { \
pci_write_config(sc->bge_dev, BGE_PCI_MEMWIN_BASEADDR, \
(0xFFFF0000 & x), 4); \
@@ -1744,99 +1795,100 @@
} while(0)
/*
- * This magic number is used to prevent PXE restart when we
- * issue a software reset. We write this magic number to the
- * firmware mailbox at 0xB50 in order to prevent the PXE boot
- * code from running.
+ * This magic number is written to the firmware mailbox at 0xb50
+ * before a software reset is issued. After the internal firmware
+ * has completed its initialization it will write the opposite of
+ * this value, ~BGE_MAGIC_NUMBER, to the same location, allowing the
+ * driver to synchronize with the firmware.
*/
-#define BGE_MAGIC_NUMBER 0x4B657654
+#define BGE_MAGIC_NUMBER 0x4B657654
typedef struct {
- u_int32_t bge_addr_hi;
- u_int32_t bge_addr_lo;
+ uint32_t bge_addr_hi;
+ uint32_t bge_addr_lo;
} bge_hostaddr;
-#define BGE_HOSTADDR(x, y) \
+#define BGE_HOSTADDR(x, y) \
do { \
- (x).bge_addr_lo = ((u_int64_t) (y) & 0xffffffff); \
- (x).bge_addr_hi = ((u_int64_t) (y) >> 32); \
+ (x).bge_addr_lo = ((uint64_t) (y) & 0xffffffff); \
+ (x).bge_addr_hi = ((uint64_t) (y) >> 32); \
} while(0)
-#define BGE_ADDR_LO(y) \
- ((u_int64_t) (y) & 0xFFFFFFFF)
-#define BGE_ADDR_HI(y) \
- ((u_int64_t) (y) >> 32)
+#define BGE_ADDR_LO(y) \
+ ((uint64_t) (y) & 0xFFFFFFFF)
+#define BGE_ADDR_HI(y) \
+ ((uint64_t) (y) >> 32)
/* Ring control block structure */
struct bge_rcb {
bge_hostaddr bge_hostaddr;
- u_int32_t bge_maxlen_flags;
- u_int32_t bge_nicaddr;
+ uint32_t bge_maxlen_flags;
+ uint32_t bge_nicaddr;
};
#define RCB_WRITE_4(sc, rcb, offset, val) \
bus_space_write_4(sc->bge_btag, sc->bge_bhandle, \
rcb + offsetof(struct bge_rcb, offset), val)
-#define BGE_RCB_MAXLEN_FLAGS(maxlen, flags) ((maxlen) << 16 | (flags))
+#define BGE_RCB_MAXLEN_FLAGS(maxlen, flags) ((maxlen) << 16 | (flags))
-#define BGE_RCB_FLAG_USE_EXT_RX_BD 0x0001
-#define BGE_RCB_FLAG_RING_DISABLED 0x0002
+#define BGE_RCB_FLAG_USE_EXT_RX_BD 0x0001
+#define BGE_RCB_FLAG_RING_DISABLED 0x0002
struct bge_tx_bd {
bge_hostaddr bge_addr;
#if BYTE_ORDER == LITTLE_ENDIAN
- u_int16_t bge_flags;
- u_int16_t bge_len;
- u_int16_t bge_vlan_tag;
- u_int16_t bge_rsvd;
+ uint16_t bge_flags;
+ uint16_t bge_len;
+ uint16_t bge_vlan_tag;
+ uint16_t bge_rsvd;
#else
- u_int16_t bge_len;
- u_int16_t bge_flags;
- u_int16_t bge_rsvd;
- u_int16_t bge_vlan_tag;
+ uint16_t bge_len;
+ uint16_t bge_flags;
+ uint16_t bge_rsvd;
+ uint16_t bge_vlan_tag;
#endif
};
-#define BGE_TXBDFLAG_TCP_UDP_CSUM 0x0001
-#define BGE_TXBDFLAG_IP_CSUM 0x0002
-#define BGE_TXBDFLAG_END 0x0004
-#define BGE_TXBDFLAG_IP_FRAG 0x0008
-#define BGE_TXBDFLAG_IP_FRAG_END 0x0010
-#define BGE_TXBDFLAG_VLAN_TAG 0x0040
-#define BGE_TXBDFLAG_COAL_NOW 0x0080
-#define BGE_TXBDFLAG_CPU_PRE_DMA 0x0100
-#define BGE_TXBDFLAG_CPU_POST_DMA 0x0200
-#define BGE_TXBDFLAG_INSERT_SRC_ADDR 0x1000
-#define BGE_TXBDFLAG_CHOOSE_SRC_ADDR 0x6000
-#define BGE_TXBDFLAG_NO_CRC 0x8000
+#define BGE_TXBDFLAG_TCP_UDP_CSUM 0x0001
+#define BGE_TXBDFLAG_IP_CSUM 0x0002
+#define BGE_TXBDFLAG_END 0x0004
+#define BGE_TXBDFLAG_IP_FRAG 0x0008
+#define BGE_TXBDFLAG_IP_FRAG_END 0x0010
+#define BGE_TXBDFLAG_VLAN_TAG 0x0040
+#define BGE_TXBDFLAG_COAL_NOW 0x0080
+#define BGE_TXBDFLAG_CPU_PRE_DMA 0x0100
+#define BGE_TXBDFLAG_CPU_POST_DMA 0x0200
+#define BGE_TXBDFLAG_INSERT_SRC_ADDR 0x1000
+#define BGE_TXBDFLAG_CHOOSE_SRC_ADDR 0x6000
+#define BGE_TXBDFLAG_NO_CRC 0x8000
-#define BGE_NIC_TXRING_ADDR(ringno, size) \
+#define BGE_NIC_TXRING_ADDR(ringno, size) \
BGE_SEND_RING_1_TO_4 + \
((ringno * sizeof(struct bge_tx_bd) * size) / 4)
struct bge_rx_bd {
bge_hostaddr bge_addr;
#if BYTE_ORDER == LITTLE_ENDIAN
- u_int16_t bge_len;
- u_int16_t bge_idx;
- u_int16_t bge_flags;
- u_int16_t bge_type;
- u_int16_t bge_tcp_udp_csum;
- u_int16_t bge_ip_csum;
- u_int16_t bge_vlan_tag;
- u_int16_t bge_error_flag;
+ uint16_t bge_len;
+ uint16_t bge_idx;
+ uint16_t bge_flags;
+ uint16_t bge_type;
+ uint16_t bge_tcp_udp_csum;
+ uint16_t bge_ip_csum;
+ uint16_t bge_vlan_tag;
+ uint16_t bge_error_flag;
#else
- u_int16_t bge_idx;
- u_int16_t bge_len;
- u_int16_t bge_type;
- u_int16_t bge_flags;
- u_int16_t bge_ip_csum;
- u_int16_t bge_tcp_udp_csum;
- u_int16_t bge_error_flag;
- u_int16_t bge_vlan_tag;
+ uint16_t bge_idx;
+ uint16_t bge_len;
+ uint16_t bge_type;
+ uint16_t bge_flags;
+ uint16_t bge_ip_csum;
+ uint16_t bge_tcp_udp_csum;
+ uint16_t bge_error_flag;
+ uint16_t bge_vlan_tag;
#endif
- u_int32_t bge_rsvd;
- u_int32_t bge_opaque;
+ uint32_t bge_rsvd;
+ uint32_t bge_opaque;
};
struct bge_extrx_bd {
@@ -1844,91 +1896,91 @@
bge_hostaddr bge_addr2;
bge_hostaddr bge_addr3;
#if BYTE_ORDER == LITTLE_ENDIAN
- u_int16_t bge_len2;
- u_int16_t bge_len1;
- u_int16_t bge_rsvd1;
- u_int16_t bge_len3;
+ uint16_t bge_len2;
+ uint16_t bge_len1;
+ uint16_t bge_rsvd1;
+ uint16_t bge_len3;
#else
- u_int16_t bge_len1;
- u_int16_t bge_len2;
- u_int16_t bge_len3;
- u_int16_t bge_rsvd1;
+ uint16_t bge_len1;
+ uint16_t bge_len2;
+ uint16_t bge_len3;
+ uint16_t bge_rsvd1;
#endif
bge_hostaddr bge_addr0;
#if BYTE_ORDER == LITTLE_ENDIAN
- u_int16_t bge_len0;
- u_int16_t bge_idx;
- u_int16_t bge_flags;
- u_int16_t bge_type;
- u_int16_t bge_tcp_udp_csum;
- u_int16_t bge_ip_csum;
- u_int16_t bge_vlan_tag;
- u_int16_t bge_error_flag;
+ uint16_t bge_len0;
+ uint16_t bge_idx;
+ uint16_t bge_flags;
+ uint16_t bge_type;
+ uint16_t bge_tcp_udp_csum;
+ uint16_t bge_ip_csum;
+ uint16_t bge_vlan_tag;
+ uint16_t bge_error_flag;
#else
- u_int16_t bge_idx;
- u_int16_t bge_len0;
- u_int16_t bge_type;
- u_int16_t bge_flags;
- u_int16_t bge_ip_csum;
- u_int16_t bge_tcp_udp_csum;
- u_int16_t bge_error_flag;
- u_int16_t bge_vlan_tag;
+ uint16_t bge_idx;
+ uint16_t bge_len0;
+ uint16_t bge_type;
+ uint16_t bge_flags;
+ uint16_t bge_ip_csum;
+ uint16_t bge_tcp_udp_csum;
+ uint16_t bge_error_flag;
+ uint16_t bge_vlan_tag;
#endif
- u_int32_t bge_rsvd0;
- u_int32_t bge_opaque;
+ uint32_t bge_rsvd0;
+ uint32_t bge_opaque;
};
-#define BGE_RXBDFLAG_END 0x0004
-#define BGE_RXBDFLAG_JUMBO_RING 0x0020
-#define BGE_RXBDFLAG_VLAN_TAG 0x0040
-#define BGE_RXBDFLAG_ERROR 0x0400
-#define BGE_RXBDFLAG_MINI_RING 0x0800
-#define BGE_RXBDFLAG_IP_CSUM 0x1000
-#define BGE_RXBDFLAG_TCP_UDP_CSUM 0x2000
-#define BGE_RXBDFLAG_TCP_UDP_IS_TCP 0x4000
-
-#define BGE_RXERRFLAG_BAD_CRC 0x0001
-#define BGE_RXERRFLAG_COLL_DETECT 0x0002
-#define BGE_RXERRFLAG_LINK_LOST 0x0004
-#define BGE_RXERRFLAG_PHY_DECODE_ERR 0x0008
-#define BGE_RXERRFLAG_MAC_ABORT 0x0010
-#define BGE_RXERRFLAG_RUNT 0x0020
-#define BGE_RXERRFLAG_TRUNC_NO_RSRCS 0x0040
-#define BGE_RXERRFLAG_GIANT 0x0080
+#define BGE_RXBDFLAG_END 0x0004
+#define BGE_RXBDFLAG_JUMBO_RING 0x0020
+#define BGE_RXBDFLAG_VLAN_TAG 0x0040
+#define BGE_RXBDFLAG_ERROR 0x0400
+#define BGE_RXBDFLAG_MINI_RING 0x0800
+#define BGE_RXBDFLAG_IP_CSUM 0x1000
+#define BGE_RXBDFLAG_TCP_UDP_CSUM 0x2000
+#define BGE_RXBDFLAG_TCP_UDP_IS_TCP 0x4000
+
+#define BGE_RXERRFLAG_BAD_CRC 0x0001
+#define BGE_RXERRFLAG_COLL_DETECT 0x0002
+#define BGE_RXERRFLAG_LINK_LOST 0x0004
+#define BGE_RXERRFLAG_PHY_DECODE_ERR 0x0008
+#define BGE_RXERRFLAG_MAC_ABORT 0x0010
+#define BGE_RXERRFLAG_RUNT 0x0020
+#define BGE_RXERRFLAG_TRUNC_NO_RSRCS 0x0040
+#define BGE_RXERRFLAG_GIANT 0x0080
struct bge_sts_idx {
#if BYTE_ORDER == LITTLE_ENDIAN
- u_int16_t bge_rx_prod_idx;
- u_int16_t bge_tx_cons_idx;
+ uint16_t bge_rx_prod_idx;
+ uint16_t bge_tx_cons_idx;
#else
- u_int16_t bge_tx_cons_idx;
- u_int16_t bge_rx_prod_idx;
+ uint16_t bge_tx_cons_idx;
+ uint16_t bge_rx_prod_idx;
#endif
};
struct bge_status_block {
- u_int32_t bge_status;
- u_int32_t bge_rsvd0;
+ uint32_t bge_status;
+ uint32_t bge_rsvd0;
#if BYTE_ORDER == LITTLE_ENDIAN
- u_int16_t bge_rx_jumbo_cons_idx;
- u_int16_t bge_rx_std_cons_idx;
- u_int16_t bge_rx_mini_cons_idx;
- u_int16_t bge_rsvd1;
+ uint16_t bge_rx_jumbo_cons_idx;
+ uint16_t bge_rx_std_cons_idx;
+ uint16_t bge_rx_mini_cons_idx;
+ uint16_t bge_rsvd1;
#else
- u_int16_t bge_rx_std_cons_idx;
- u_int16_t bge_rx_jumbo_cons_idx;
- u_int16_t bge_rsvd1;
- u_int16_t bge_rx_mini_cons_idx;
+ uint16_t bge_rx_std_cons_idx;
+ uint16_t bge_rx_jumbo_cons_idx;
+ uint16_t bge_rsvd1;
+ uint16_t bge_rx_mini_cons_idx;
#endif
struct bge_sts_idx bge_idx[16];
};
-#define BGE_TX_CONSIDX(x, i) x->bge_idx[i].bge_tx_considx
-#define BGE_RX_PRODIDX(x, i) x->bge_idx[i].bge_rx_prodidx
+#define BGE_TX_CONSIDX(x, i) x->bge_idx[i].bge_tx_considx
+#define BGE_RX_PRODIDX(x, i) x->bge_idx[i].bge_rx_prodidx
-#define BGE_STATFLAG_UPDATED 0x00000001
-#define BGE_STATFLAG_LINKSTATE_CHANGED 0x00000002
-#define BGE_STATFLAG_ERROR 0x00000004
+#define BGE_STATFLAG_UPDATED 0x00000001
+#define BGE_STATFLAG_LINKSTATE_CHANGED 0x00000002
+#define BGE_STATFLAG_ERROR 0x00000004
/*
@@ -1936,124 +1988,156 @@
* (Note: the BCM570x still defaults to the Alteon PCI vendor ID
* even though they're now manufactured by Broadcom)
*/
-#define BCOM_VENDORID 0x14E4
-#define BCOM_DEVICEID_BCM5700 0x1644
-#define BCOM_DEVICEID_BCM5701 0x1645
-#define BCOM_DEVICEID_BCM5702 0x16A6
-#define BCOM_DEVICEID_BCM5702X 0x16C6
-#define BCOM_DEVICEID_BCM5703 0x16A7
-#define BCOM_DEVICEID_BCM5703X 0x16C7
-#define BCOM_DEVICEID_BCM5704C 0x1648
-#define BCOM_DEVICEID_BCM5704S 0x16A8
-#define BCOM_DEVICEID_BCM5705 0x1653
-#define BCOM_DEVICEID_BCM5705K 0x1654
-#define BCOM_DEVICEID_BCM5721 0x1659
-#define BCOM_DEVICEID_BCM5705M 0x165D
-#define BCOM_DEVICEID_BCM5705M_ALT 0x165E
-#define BCOM_DEVICEID_BCM5714C 0x1668
-#define BCOM_DEVICEID_BCM5750 0x1676
-#define BCOM_DEVICEID_BCM5750M 0x167C
-#define BCOM_DEVICEID_BCM5751 0x1677
-#define BCOM_DEVICEID_BCM5751M 0x167D
-#define BCOM_DEVICEID_BCM5752 0x1600
-#define BCOM_DEVICEID_BCM5782 0x1696
-#define BCOM_DEVICEID_BCM5788 0x169C
-#define BCOM_DEVICEID_BCM5789 0x169D
-#define BCOM_DEVICEID_BCM5901 0x170D
-#define BCOM_DEVICEID_BCM5901A2 0x170E
+#define BCOM_VENDORID 0x14E4
+#define BCOM_DEVICEID_BCM5700 0x1644
+#define BCOM_DEVICEID_BCM5701 0x1645
+#define BCOM_DEVICEID_BCM5702 0x1646
+#define BCOM_DEVICEID_BCM5702X 0x16A6
+#define BCOM_DEVICEID_BCM5702_ALT 0x16C6
+#define BCOM_DEVICEID_BCM5703 0x1647
+#define BCOM_DEVICEID_BCM5703X 0x16A7
+#define BCOM_DEVICEID_BCM5703_ALT 0x16C7
+#define BCOM_DEVICEID_BCM5704C 0x1648
+#define BCOM_DEVICEID_BCM5704S 0x16A8
+#define BCOM_DEVICEID_BCM5704S_ALT 0x1649
+#define BCOM_DEVICEID_BCM5705 0x1653
+#define BCOM_DEVICEID_BCM5705K 0x1654
+#define BCOM_DEVICEID_BCM5705F 0x166E
+#define BCOM_DEVICEID_BCM5705M 0x165D
+#define BCOM_DEVICEID_BCM5705M_ALT 0x165E
+#define BCOM_DEVICEID_BCM5714C 0x1668
+#define BCOM_DEVICEID_BCM5714S 0x1669
+#define BCOM_DEVICEID_BCM5715 0x1678
+#define BCOM_DEVICEID_BCM5715S 0x1679
+#define BCOM_DEVICEID_BCM5720 0x1658
+#define BCOM_DEVICEID_BCM5721 0x1659
+#define BCOM_DEVICEID_BCM5750 0x1676
+#define BCOM_DEVICEID_BCM5750M 0x167C
+#define BCOM_DEVICEID_BCM5751 0x1677
+#define BCOM_DEVICEID_BCM5751F 0x167E
+#define BCOM_DEVICEID_BCM5751M 0x167D
+#define BCOM_DEVICEID_BCM5752 0x1600
+#define BCOM_DEVICEID_BCM5752M 0x1601
+#define BCOM_DEVICEID_BCM5753 0x16F7
+#define BCOM_DEVICEID_BCM5753F 0x16FE
+#define BCOM_DEVICEID_BCM5753M 0x16FD
+#define BCOM_DEVICEID_BCM5754 0x167A
+#define BCOM_DEVICEID_BCM5754M 0x1672
+#define BCOM_DEVICEID_BCM5755 0x167B
+#define BCOM_DEVICEID_BCM5755M 0x1673
+#define BCOM_DEVICEID_BCM5780 0x166A
+#define BCOM_DEVICEID_BCM5780S 0x166B
+#define BCOM_DEVICEID_BCM5781 0x16DD
+#define BCOM_DEVICEID_BCM5782 0x1696
+#define BCOM_DEVICEID_BCM5786 0x169A
+#define BCOM_DEVICEID_BCM5787 0x169B
+#define BCOM_DEVICEID_BCM5787M 0x1693
+#define BCOM_DEVICEID_BCM5788 0x169C
+#define BCOM_DEVICEID_BCM5789 0x169D
+#define BCOM_DEVICEID_BCM5901 0x170D
+#define BCOM_DEVICEID_BCM5901A2 0x170E
+#define BCOM_DEVICEID_BCM5903M 0x16FF
/*
* Alteon AceNIC PCI vendor/device ID.
*/
-#define ALT_VENDORID 0x12AE
-#define ALT_DEVICEID_ACENIC 0x0001
-#define ALT_DEVICEID_ACENIC_COPPER 0x0002
-#define ALT_DEVICEID_BCM5700 0x0003
-#define ALT_DEVICEID_BCM5701 0x0004
+#define ALTEON_VENDORID 0x12AE
+#define ALTEON_DEVICEID_ACENIC 0x0001
+#define ALTEON_DEVICEID_ACENIC_COPPER 0x0002
+#define ALTEON_DEVICEID_BCM5700 0x0003
+#define ALTEON_DEVICEID_BCM5701 0x0004
/*
- * 3Com 3c985 PCI vendor/device ID.
- */
-#define TC_VENDORID 0x10B7
-#define TC_DEVICEID_3C985 0x0001
-#define TC_DEVICEID_3C996 0x0003
+ * 3Com 3c996 PCI vendor/device ID.
+ */
+#define TC_VENDORID 0x10B7
+#define TC_DEVICEID_3C996 0x0003
/*
* SysKonnect PCI vendor ID
*/
-#define SK_VENDORID 0x1148
-#define SK_DEVICEID_ALTIMA 0x4400
-#define SK_SUBSYSID_9D21 0x4421
-#define SK_SUBSYSID_9D41 0x4441
+#define SK_VENDORID 0x1148
+#define SK_DEVICEID_ALTIMA 0x4400
+#define SK_SUBSYSID_9D21 0x4421
+#define SK_SUBSYSID_9D41 0x4441
/*
* Altima PCI vendor/device ID.
*/
-#define ALTIMA_VENDORID 0x173b
-#define ALTIMA_DEVICE_AC1000 0x03e8
-#define ALTIMA_DEVICE_AC1002 0x03e9
-#define ALTIMA_DEVICE_AC9100 0x03ea
+#define ALTIMA_VENDORID 0x173b
+#define ALTIMA_DEVICE_AC1000 0x03e8
+#define ALTIMA_DEVICE_AC1002 0x03e9
+#define ALTIMA_DEVICE_AC9100 0x03ea
/*
* Dell PCI vendor ID
*/
-#define DELL_VENDORID 0x1028
+#define DELL_VENDORID 0x1028
/*
- * Offset of MAC address inside EEPROM.
+ * Apple PCI vendor ID.
*/
-#define BGE_EE_MAC_OFFSET 0x7C
-#define BGE_EE_HWCFG_OFFSET 0xC8
-
-#define BGE_HWCFG_VOLTAGE 0x00000003
-#define BGE_HWCFG_PHYLED_MODE 0x0000000C
-#define BGE_HWCFG_MEDIA 0x00000030
+#define APPLE_VENDORID 0x106b
+#define APPLE_DEVICE_BCM5701 0x1645
-#define BGE_VOLTAGE_1POINT3 0x00000000
-#define BGE_VOLTAGE_1POINT8 0x00000001
-
-#define BGE_PHYLEDMODE_UNSPEC 0x00000000
-#define BGE_PHYLEDMODE_TRIPLELED 0x00000004
-#define BGE_PHYLEDMODE_SINGLELED 0x00000008
+/*
+ * Sun PCI vendor ID
+ */
+#define SUN_VENDORID 0x108e
-#define BGE_MEDIA_UNSPEC 0x00000000
-#define BGE_MEDIA_COPPER 0x00000010
-#define BGE_MEDIA_FIBER 0x00000020
+/*
+ * Offset of MAC address inside EEPROM.
+ */
+#define BGE_EE_MAC_OFFSET 0x7C
+#define BGE_EE_HWCFG_OFFSET 0xC8
-#define BGE_PCI_READ_CMD 0x06000000
-#define BGE_PCI_WRITE_CMD 0x70000000
+#define BGE_HWCFG_VOLTAGE 0x00000003
+#define BGE_HWCFG_PHYLED_MODE 0x0000000C
+#define BGE_HWCFG_MEDIA 0x00000030
+#define BGE_HWCFG_ASF 0x00000080
+
+#define BGE_VOLTAGE_1POINT3 0x00000000
+#define BGE_VOLTAGE_1POINT8 0x00000001
+
+#define BGE_PHYLEDMODE_UNSPEC 0x00000000
+#define BGE_PHYLEDMODE_TRIPLELED 0x00000004
+#define BGE_PHYLEDMODE_SINGLELED 0x00000008
+
+#define BGE_MEDIA_UNSPEC 0x00000000
+#define BGE_MEDIA_COPPER 0x00000010
+#define BGE_MEDIA_FIBER 0x00000020
-#define BGE_TICKS_PER_SEC 1000000
+#define BGE_TICKS_PER_SEC 1000000
/*
* Ring size constants.
*/
-#define BGE_EVENT_RING_CNT 256
-#define BGE_CMD_RING_CNT 64
-#define BGE_STD_RX_RING_CNT 512
-#define BGE_JUMBO_RX_RING_CNT 256
-#define BGE_MINI_RX_RING_CNT 1024
-#define BGE_RETURN_RING_CNT 1024
+#define BGE_EVENT_RING_CNT 256
+#define BGE_CMD_RING_CNT 64
+#define BGE_STD_RX_RING_CNT 512
+#define BGE_JUMBO_RX_RING_CNT 256
+#define BGE_MINI_RX_RING_CNT 1024
+#define BGE_RETURN_RING_CNT 1024
/* 5705 has smaller return ring size */
-#define BGE_RETURN_RING_CNT_5705 512
+#define BGE_RETURN_RING_CNT_5705 512
/*
* Possible TX ring sizes.
*/
-#define BGE_TX_RING_CNT_128 128
-#define BGE_TX_RING_BASE_128 0x3800
+#define BGE_TX_RING_CNT_128 128
+#define BGE_TX_RING_BASE_128 0x3800
-#define BGE_TX_RING_CNT_256 256
-#define BGE_TX_RING_BASE_256 0x3000
+#define BGE_TX_RING_CNT_256 256
+#define BGE_TX_RING_BASE_256 0x3000
-#define BGE_TX_RING_CNT_512 512
-#define BGE_TX_RING_BASE_512 0x2000
+#define BGE_TX_RING_CNT_512 512
+#define BGE_TX_RING_BASE_512 0x2000
-#define BGE_TX_RING_CNT BGE_TX_RING_CNT_512
-#define BGE_TX_RING_BASE BGE_TX_RING_BASE_512
+#define BGE_TX_RING_CNT BGE_TX_RING_CNT_512
+#define BGE_TX_RING_BASE BGE_TX_RING_BASE_512
/*
* Tigon III statistics counters.
@@ -2129,43 +2213,43 @@
/* Stats counters access through registers */
struct bge_mac_stats_regs {
- u_int32_t ifHCOutOctets;
- u_int32_t Reserved0;
- u_int32_t etherStatsCollisions;
- u_int32_t outXonSent;
- u_int32_t outXoffSent;
- u_int32_t Reserved1;
- u_int32_t dot3StatsInternalMacTransmitErrors;
- u_int32_t dot3StatsSingleCollisionFrames;
- u_int32_t dot3StatsMultipleCollisionFrames;
- u_int32_t dot3StatsDeferredTransmissions;
- u_int32_t Reserved2;
- u_int32_t dot3StatsExcessiveCollisions;
- u_int32_t dot3StatsLateCollisions;
- u_int32_t Reserved3[14];
- u_int32_t ifHCOutUcastPkts;
- u_int32_t ifHCOutMulticastPkts;
- u_int32_t ifHCOutBroadcastPkts;
- u_int32_t Reserved4[2];
- u_int32_t ifHCInOctets;
- u_int32_t Reserved5;
- u_int32_t etherStatsFragments;
- u_int32_t ifHCInUcastPkts;
- u_int32_t ifHCInMulticastPkts;
- u_int32_t ifHCInBroadcastPkts;
- u_int32_t dot3StatsFCSErrors;
- u_int32_t dot3StatsAlignmentErrors;
- u_int32_t xonPauseFramesReceived;
- u_int32_t xoffPauseFramesReceived;
- u_int32_t macControlFramesReceived;
- u_int32_t xoffStateEntered;
- u_int32_t dot3StatsFramesTooLong;
- u_int32_t etherStatsJabbers;
- u_int32_t etherStatsUndersizePkts;
+ uint32_t ifHCOutOctets;
+ uint32_t Reserved0;
+ uint32_t etherStatsCollisions;
+ uint32_t outXonSent;
+ uint32_t outXoffSent;
+ uint32_t Reserved1;
+ uint32_t dot3StatsInternalMacTransmitErrors;
+ uint32_t dot3StatsSingleCollisionFrames;
+ uint32_t dot3StatsMultipleCollisionFrames;
+ uint32_t dot3StatsDeferredTransmissions;
+ uint32_t Reserved2;
+ uint32_t dot3StatsExcessiveCollisions;
+ uint32_t dot3StatsLateCollisions;
+ uint32_t Reserved3[14];
+ uint32_t ifHCOutUcastPkts;
+ uint32_t ifHCOutMulticastPkts;
+ uint32_t ifHCOutBroadcastPkts;
+ uint32_t Reserved4[2];
+ uint32_t ifHCInOctets;
+ uint32_t Reserved5;
+ uint32_t etherStatsFragments;
+ uint32_t ifHCInUcastPkts;
+ uint32_t ifHCInMulticastPkts;
+ uint32_t ifHCInBroadcastPkts;
+ uint32_t dot3StatsFCSErrors;
+ uint32_t dot3StatsAlignmentErrors;
+ uint32_t xonPauseFramesReceived;
+ uint32_t xoffPauseFramesReceived;
+ uint32_t macControlFramesReceived;
+ uint32_t xoffStateEntered;
+ uint32_t dot3StatsFramesTooLong;
+ uint32_t etherStatsJabbers;
+ uint32_t etherStatsUndersizePkts;
};
struct bge_stats {
- u_int8_t Reserved0[256];
+ uint8_t Reserved0[256];
/* Statistics maintained by Receive MAC. */
struct bge_rx_mac_stats rxstats;
@@ -2202,7 +2286,7 @@
bge_hostaddr nicAvoidedInterrupts;
bge_hostaddr nicSendThresholdHit;
- u_int8_t Reserved4[320];
+ uint8_t Reserved4[320];
};
/*
@@ -2220,59 +2304,36 @@
struct bge_rcb bge_return_rcb;
};
-#define BGE_FRAMELEN 1518
-#define BGE_MAX_FRAMELEN 1536
-#define BGE_JUMBO_FRAMELEN 9018
-#define BGE_JUMBO_MTU (BGE_JUMBO_FRAMELEN-ETHER_HDR_LEN-ETHER_CRC_LEN)
-#define BGE_MIN_FRAMELEN 60
+#define BGE_FRAMELEN 1518
+#define BGE_MAX_FRAMELEN 1536
+#define BGE_JUMBO_FRAMELEN 9018
+#define BGE_JUMBO_MTU (BGE_JUMBO_FRAMELEN-ETHER_HDR_LEN-ETHER_CRC_LEN)
+#define BGE_MIN_FRAMELEN 60
/*
* Other utility macros.
*/
-#define BGE_INC(x, y) (x) = (x + 1) % y
-
-/*
- * Vital product data and structures.
- */
-#define BGE_VPD_FLAG 0x8000
-
-/* VPD structures */
-struct vpd_res {
- u_int8_t vr_id;
- u_int8_t vr_len;
- u_int8_t vr_pad;
-};
-
-struct vpd_key {
- char vk_key[2];
- u_int8_t vk_len;
-};
-
-#define VPD_RES_ID 0x82 /* ID string */
-#define VPD_RES_READ 0x90 /* start of read only area */
-#define VPD_RES_WRITE 0x81 /* start of read/write area */
-#define VPD_RES_END 0x78 /* end tag */
-
+#define BGE_INC(x, y) (x) = (x + 1) % y
/*
* Register access macros. The Tigon always uses memory mapped register
* accesses and all registers must be accessed with 32 bit operations.
*/
-#define CSR_WRITE_4(sc, reg, val) \
+#define CSR_WRITE_4(sc, reg, val) \
bus_space_write_4(sc->bge_btag, sc->bge_bhandle, reg, val)
-#define CSR_READ_4(sc, reg) \
+#define CSR_READ_4(sc, reg) \
bus_space_read_4(sc->bge_btag, sc->bge_bhandle, reg)
-#define BGE_SETBIT(sc, reg, x) \
+#define BGE_SETBIT(sc, reg, x) \
CSR_WRITE_4(sc, reg, (CSR_READ_4(sc, reg) | (x)))
-#define BGE_CLRBIT(sc, reg, x) \
+#define BGE_CLRBIT(sc, reg, x) \
CSR_WRITE_4(sc, reg, (CSR_READ_4(sc, reg) & ~(x)))
-#define PCI_SETBIT(dev, reg, x, s) \
+#define PCI_SETBIT(dev, reg, x, s) \
pci_write_config(dev, reg, (pci_read_config(dev, reg, s) | (x)), s)
-#define PCI_CLRBIT(dev, reg, x, s) \
+#define PCI_CLRBIT(dev, reg, x, s) \
pci_write_config(dev, reg, (pci_read_config(dev, reg, s) & ~(x)), s)
/*
@@ -2281,19 +2342,19 @@
* allocated for the standard, mini and jumbo receive rings.
*/
-#define BGE_SSLOTS 256
-#define BGE_MSLOTS 256
-#define BGE_JSLOTS 384
-
-#define BGE_JRAWLEN (BGE_JUMBO_FRAMELEN + ETHER_ALIGN)
-#define BGE_JLEN (BGE_JRAWLEN + (sizeof(u_int64_t) - \
- (BGE_JRAWLEN % sizeof(u_int64_t))))
-#define BGE_JPAGESZ PAGE_SIZE
-#define BGE_RESID (BGE_JPAGESZ - (BGE_JLEN * BGE_JSLOTS) % BGE_JPAGESZ)
-#define BGE_JMEM ((BGE_JLEN * BGE_JSLOTS) + BGE_RESID)
+#define BGE_SSLOTS 256
+#define BGE_MSLOTS 256
+#define BGE_JSLOTS 384
+
+#define BGE_JRAWLEN (BGE_JUMBO_FRAMELEN + ETHER_ALIGN)
+#define BGE_JLEN (BGE_JRAWLEN + (sizeof(uint64_t) - \
+ (BGE_JRAWLEN % sizeof(uint64_t))))
+#define BGE_JPAGESZ PAGE_SIZE
+#define BGE_RESID (BGE_JPAGESZ - (BGE_JLEN * BGE_JSLOTS) % BGE_JPAGESZ)
+#define BGE_JMEM ((BGE_JLEN * BGE_JSLOTS) + BGE_RESID)
-#define BGE_NSEG_JUMBO 4
-#define BGE_NSEG_NEW 32
+#define BGE_NSEG_JUMBO 4
+#define BGE_NSEG_NEW 32
/*
* Ring structures. Most of these reside in host memory and we tell
@@ -2318,18 +2379,18 @@
struct bge_gib bge_info;
};
-#define BGE_STD_RX_RING_SZ \
+#define BGE_STD_RX_RING_SZ \
(sizeof(struct bge_rx_bd) * BGE_STD_RX_RING_CNT)
-#define BGE_JUMBO_RX_RING_SZ \
+#define BGE_JUMBO_RX_RING_SZ \
(sizeof(struct bge_extrx_bd) * BGE_JUMBO_RX_RING_CNT)
-#define BGE_TX_RING_SZ \
+#define BGE_TX_RING_SZ \
(sizeof(struct bge_tx_bd) * BGE_TX_RING_CNT)
-#define BGE_RX_RTN_RING_SZ(x) \
+#define BGE_RX_RTN_RING_SZ(x) \
(sizeof(struct bge_rx_bd) * x->bge_return_ring_cnt)
-#define BGE_STATUS_BLK_SZ sizeof (struct bge_status_block)
+#define BGE_STATUS_BLK_SZ sizeof (struct bge_status_block)
-#define BGE_STATS_SZ sizeof (struct bge_stats)
+#define BGE_STATS_SZ sizeof (struct bge_stats)
/*
* Mbuf pointers. We need these to keep track of the virtual addresses
@@ -2363,28 +2424,26 @@
struct bge_dmamap_arg {
struct bge_softc *sc;
bus_addr_t bge_busaddr;
- u_int16_t bge_flags;
+ uint16_t bge_flags;
int bge_idx;
int bge_maxsegs;
struct bge_tx_bd *bge_ring;
};
-struct bge_type {
- u_int16_t bge_vid;
- u_int16_t bge_did;
- char *bge_name;
-};
-
-#define BGE_HWREV_TIGON 0x01
-#define BGE_HWREV_TIGON_II 0x02
-#define BGE_TIMEOUT 100000
-#define BGE_TXCONS_UNSET 0xFFFF /* impossible value */
+#define BGE_HWREV_TIGON 0x01
+#define BGE_HWREV_TIGON_II 0x02
+#define BGE_TIMEOUT 100000
+#define BGE_TXCONS_UNSET 0xFFFF /* impossible value */
struct bge_bcom_hack {
int reg;
int val;
};
+#define ASF_ENABLE 1
+#define ASF_NEW_HANDSHAKE 2
+#define ASF_STACKUP 4
+
struct bge_softc {
struct ifnet *bge_ifp; /* interface info */
device_t bge_dev;
@@ -2396,39 +2455,54 @@
struct resource *bge_irq;
struct resource *bge_res;
struct ifmedia bge_ifmedia; /* TBI media info */
- u_int8_t bge_extram; /* has external SSRAM */
- u_int8_t bge_tbi;
- u_int8_t bge_rx_alignment_bug;
- u_int32_t bge_chipid;
- u_int8_t bge_asicrev;
- u_int8_t bge_chiprev;
- u_int8_t bge_no_3_led;
- u_int8_t bge_pcie;
+ uint32_t bge_flags;
+#define BGE_FLAG_TBI 0x00000001
+#define BGE_FLAG_JUMBO 0x00000002
+#define BGE_FLAG_EEPROM 0x00000004
+#define BGE_FLAG_MSI 0x00000100
+#define BGE_FLAG_PCIX 0x00000200
+#define BGE_FLAG_PCIE 0x00000400
+#define BGE_FLAG_5700_FAMILY 0x00001000
+#define BGE_FLAG_5705_PLUS 0x00002000
+#define BGE_FLAG_5714_FAMILY 0x00004000
+#define BGE_FLAG_575X_PLUS 0x00008000
+#define BGE_FLAG_RX_ALIGNBUG 0x00100000
+#define BGE_FLAG_NO_3LED 0x00200000
+#define BGE_FLAG_ADC_BUG 0x00400000
+#define BGE_FLAG_5704_A0_BUG 0x00800000
+#define BGE_FLAG_JITTER_BUG 0x01000000
+#define BGE_FLAG_BER_BUG 0x02000000
+#define BGE_FLAG_ADJUST_TRIM 0x04000000
+#define BGE_FLAG_CRC_BUG 0x08000000
+ uint32_t bge_chipid;
+ uint8_t bge_asicrev;
+ uint8_t bge_chiprev;
+ uint8_t bge_asf_mode;
+ uint8_t bge_asf_count;
struct bge_ring_data bge_ldata; /* rings */
struct bge_chain_data bge_cdata; /* mbufs */
- u_int16_t bge_tx_saved_considx;
- u_int16_t bge_rx_saved_considx;
- u_int16_t bge_ev_saved_considx;
- u_int16_t bge_return_ring_cnt;
- u_int16_t bge_std; /* current std ring head */
- u_int16_t bge_jumbo; /* current jumo ring head */
- u_int32_t bge_stat_ticks;
- u_int32_t bge_rx_coal_ticks;
- u_int32_t bge_tx_coal_ticks;
- u_int32_t bge_tx_prodidx;
- u_int32_t bge_rx_max_coal_bds;
- u_int32_t bge_tx_max_coal_bds;
- u_int32_t bge_tx_buf_ratio;
+ uint16_t bge_tx_saved_considx;
+ uint16_t bge_rx_saved_considx;
+ uint16_t bge_ev_saved_considx;
+ uint16_t bge_return_ring_cnt;
+ uint16_t bge_std; /* current std ring head */
+ uint16_t bge_jumbo; /* current jumo ring head */
+ uint32_t bge_stat_ticks;
+ uint32_t bge_rx_coal_ticks;
+ uint32_t bge_tx_coal_ticks;
+ uint32_t bge_tx_prodidx;
+ uint32_t bge_rx_max_coal_bds;
+ uint32_t bge_tx_max_coal_bds;
+ uint32_t bge_tx_buf_ratio;
int bge_if_flags;
int bge_txcnt;
int bge_link; /* link state */
int bge_link_evt; /* pending link event */
+ int bge_timer;
struct callout bge_stat_ch;
- char *bge_vpd_prodname;
- char *bge_vpd_readonly;
- u_long bge_rx_discards;
- u_long bge_tx_discards;
- u_long bge_tx_collisions;
+ uint32_t bge_rx_discards;
+ uint32_t bge_tx_discards;
+ uint32_t bge_tx_collisions;
#ifdef DEVICE_POLLING
int rxcycles;
#endif /* DEVICE_POLLING */
Index: if_bge.c
===================================================================
RCS file: /home/cvs/src/sys/dev/bge/if_bge.c,v
retrieving revision 1.2
retrieving revision 1.3
diff -L sys/dev/bge/if_bge.c -L sys/dev/bge/if_bge.c -u -r1.2 -r1.3
--- sys/dev/bge/if_bge.c
+++ sys/dev/bge/if_bge.c
@@ -32,7 +32,7 @@
*/
#include <sys/cdefs.h>
-__FBSDID("$FreeBSD: src/sys/dev/bge/if_bge.c,v 1.91.2.13 2006/03/04 09:34:48 oleg Exp $");
+__FBSDID("$FreeBSD: src/sys/dev/bge/if_bge.c,v 1.198.2.2.2.1 2008/01/22 17:30:13 jkim Exp $");
/*
* Broadcom BCM570x family gigabit ethernet driver for FreeBSD.
@@ -79,6 +79,7 @@
#include <sys/kernel.h>
#include <sys/module.h>
#include <sys/socket.h>
+#include <sys/sysctl.h>
#include <net/if.h>
#include <net/if_arp.h>
@@ -95,7 +96,6 @@
#include <netinet/in.h>
#include <netinet/ip.h>
-#include <machine/clock.h> /* for DELAY */
#include <machine/bus.h>
#include <machine/resource.h>
#include <sys/bus.h>
@@ -106,15 +106,20 @@
#include "miidevs.h"
#include <dev/mii/brgphyreg.h>
+#ifdef __sparc64__
+#include <dev/ofw/ofw_bus.h>
+#include <dev/ofw/openfirm.h>
+#include <machine/ofw_machdep.h>
+#include <machine/ver.h>
+#endif
+
#include <dev/pci/pcireg.h>
#include <dev/pci/pcivar.h>
#include <dev/bge/if_bgereg.h>
-#include "opt_bge.h"
-
-#define BGE_CSUM_FEATURES (CSUM_IP | CSUM_TCP | CSUM_UDP)
-#define ETHER_MIN_NOPAD (ETHER_MIN_LEN - ETHER_CRC_LEN) /* i.e., 60 */
+#define BGE_CSUM_FEATURES (CSUM_IP | CSUM_TCP | CSUM_UDP)
+#define ETHER_MIN_NOPAD (ETHER_MIN_LEN - ETHER_CRC_LEN) /* i.e., 60 */
MODULE_DEPEND(bge, pci, 1, 1, 1);
MODULE_DEPEND(bge, ether, 1, 1, 1);
@@ -129,150 +134,264 @@
* ID burned into it, though it will always be overriden by the vendor
* ID in the EEPROM. Just to be safe, we cover all possibilities.
*/
-#define BGE_DEVDESC_MAX 64 /* Maximum device description length */
+static struct bge_type {
+ uint16_t bge_vid;
+ uint16_t bge_did;
+} bge_devs[] = {
+ { ALTEON_VENDORID, ALTEON_DEVICEID_BCM5700 },
+ { ALTEON_VENDORID, ALTEON_DEVICEID_BCM5701 },
+
+ { ALTIMA_VENDORID, ALTIMA_DEVICE_AC1000 },
+ { ALTIMA_VENDORID, ALTIMA_DEVICE_AC1002 },
+ { ALTIMA_VENDORID, ALTIMA_DEVICE_AC9100 },
+
+ { APPLE_VENDORID, APPLE_DEVICE_BCM5701 },
+
+ { BCOM_VENDORID, BCOM_DEVICEID_BCM5700 },
+ { BCOM_VENDORID, BCOM_DEVICEID_BCM5701 },
+ { BCOM_VENDORID, BCOM_DEVICEID_BCM5702 },
+ { BCOM_VENDORID, BCOM_DEVICEID_BCM5702_ALT },
+ { BCOM_VENDORID, BCOM_DEVICEID_BCM5702X },
+ { BCOM_VENDORID, BCOM_DEVICEID_BCM5703 },
+ { BCOM_VENDORID, BCOM_DEVICEID_BCM5703_ALT },
+ { BCOM_VENDORID, BCOM_DEVICEID_BCM5703X },
+ { BCOM_VENDORID, BCOM_DEVICEID_BCM5704C },
+ { BCOM_VENDORID, BCOM_DEVICEID_BCM5704S },
+ { BCOM_VENDORID, BCOM_DEVICEID_BCM5704S_ALT },
+ { BCOM_VENDORID, BCOM_DEVICEID_BCM5705 },
+ { BCOM_VENDORID, BCOM_DEVICEID_BCM5705F },
+ { BCOM_VENDORID, BCOM_DEVICEID_BCM5705K },
+ { BCOM_VENDORID, BCOM_DEVICEID_BCM5705M },
+ { BCOM_VENDORID, BCOM_DEVICEID_BCM5705M_ALT },
+ { BCOM_VENDORID, BCOM_DEVICEID_BCM5714C },
+ { BCOM_VENDORID, BCOM_DEVICEID_BCM5714S },
+ { BCOM_VENDORID, BCOM_DEVICEID_BCM5715 },
+ { BCOM_VENDORID, BCOM_DEVICEID_BCM5715S },
+ { BCOM_VENDORID, BCOM_DEVICEID_BCM5720 },
+ { BCOM_VENDORID, BCOM_DEVICEID_BCM5721 },
+ { BCOM_VENDORID, BCOM_DEVICEID_BCM5750 },
+ { BCOM_VENDORID, BCOM_DEVICEID_BCM5750M },
+ { BCOM_VENDORID, BCOM_DEVICEID_BCM5751 },
+ { BCOM_VENDORID, BCOM_DEVICEID_BCM5751F },
+ { BCOM_VENDORID, BCOM_DEVICEID_BCM5751M },
+ { BCOM_VENDORID, BCOM_DEVICEID_BCM5752 },
+ { BCOM_VENDORID, BCOM_DEVICEID_BCM5752M },
+ { BCOM_VENDORID, BCOM_DEVICEID_BCM5753 },
+ { BCOM_VENDORID, BCOM_DEVICEID_BCM5753F },
+ { BCOM_VENDORID, BCOM_DEVICEID_BCM5753M },
+ { BCOM_VENDORID, BCOM_DEVICEID_BCM5754 },
+ { BCOM_VENDORID, BCOM_DEVICEID_BCM5754M },
+ { BCOM_VENDORID, BCOM_DEVICEID_BCM5755 },
+ { BCOM_VENDORID, BCOM_DEVICEID_BCM5755M },
+ { BCOM_VENDORID, BCOM_DEVICEID_BCM5780 },
+ { BCOM_VENDORID, BCOM_DEVICEID_BCM5780S },
+ { BCOM_VENDORID, BCOM_DEVICEID_BCM5781 },
+ { BCOM_VENDORID, BCOM_DEVICEID_BCM5782 },
+ { BCOM_VENDORID, BCOM_DEVICEID_BCM5786 },
+ { BCOM_VENDORID, BCOM_DEVICEID_BCM5787 },
+ { BCOM_VENDORID, BCOM_DEVICEID_BCM5787M },
+ { BCOM_VENDORID, BCOM_DEVICEID_BCM5788 },
+ { BCOM_VENDORID, BCOM_DEVICEID_BCM5789 },
+ { BCOM_VENDORID, BCOM_DEVICEID_BCM5901 },
+ { BCOM_VENDORID, BCOM_DEVICEID_BCM5901A2 },
+ { BCOM_VENDORID, BCOM_DEVICEID_BCM5903M },
+
+ { SK_VENDORID, SK_DEVICEID_ALTIMA },
-static struct bge_type bge_devs[] = {
- { ALT_VENDORID, ALT_DEVICEID_BCM5700,
- "Broadcom BCM5700 Gigabit Ethernet" },
- { ALT_VENDORID, ALT_DEVICEID_BCM5701,
- "Broadcom BCM5701 Gigabit Ethernet" },
- { BCOM_VENDORID, BCOM_DEVICEID_BCM5700,
- "Broadcom BCM5700 Gigabit Ethernet" },
- { BCOM_VENDORID, BCOM_DEVICEID_BCM5701,
- "Broadcom BCM5701 Gigabit Ethernet" },
- { BCOM_VENDORID, BCOM_DEVICEID_BCM5702,
- "Broadcom BCM5702 Gigabit Ethernet" },
- { BCOM_VENDORID, BCOM_DEVICEID_BCM5702X,
- "Broadcom BCM5702X Gigabit Ethernet" },
- { BCOM_VENDORID, BCOM_DEVICEID_BCM5703,
- "Broadcom BCM5703 Gigabit Ethernet" },
- { BCOM_VENDORID, BCOM_DEVICEID_BCM5703X,
- "Broadcom BCM5703X Gigabit Ethernet" },
- { BCOM_VENDORID, BCOM_DEVICEID_BCM5704C,
- "Broadcom BCM5704C Dual Gigabit Ethernet" },
- { BCOM_VENDORID, BCOM_DEVICEID_BCM5704S,
- "Broadcom BCM5704S Dual Gigabit Ethernet" },
- { BCOM_VENDORID, BCOM_DEVICEID_BCM5705,
- "Broadcom BCM5705 Gigabit Ethernet" },
- { BCOM_VENDORID, BCOM_DEVICEID_BCM5705K,
- "Broadcom BCM5705K Gigabit Ethernet" },
- { BCOM_VENDORID, BCOM_DEVICEID_BCM5705M,
- "Broadcom BCM5705M Gigabit Ethernet" },
- { BCOM_VENDORID, BCOM_DEVICEID_BCM5705M_ALT,
- "Broadcom BCM5705M Gigabit Ethernet" },
- { BCOM_VENDORID, BCOM_DEVICEID_BCM5714C,
- "Broadcom BCM5714C Gigabit Ethernet" },
- { BCOM_VENDORID, BCOM_DEVICEID_BCM5721,
- "Broadcom BCM5721 Gigabit Ethernet" },
- { BCOM_VENDORID, BCOM_DEVICEID_BCM5750,
- "Broadcom BCM5750 Gigabit Ethernet" },
- { BCOM_VENDORID, BCOM_DEVICEID_BCM5750M,
- "Broadcom BCM5750M Gigabit Ethernet" },
- { BCOM_VENDORID, BCOM_DEVICEID_BCM5751,
- "Broadcom BCM5751 Gigabit Ethernet" },
- { BCOM_VENDORID, BCOM_DEVICEID_BCM5751M,
- "Broadcom BCM5751M Gigabit Ethernet" },
- { BCOM_VENDORID, BCOM_DEVICEID_BCM5752,
- "Broadcom BCM5752 Gigabit Ethernet" },
- { BCOM_VENDORID, BCOM_DEVICEID_BCM5782,
- "Broadcom BCM5782 Gigabit Ethernet" },
- { BCOM_VENDORID, BCOM_DEVICEID_BCM5788,
- "Broadcom BCM5788 Gigabit Ethernet" },
- { BCOM_VENDORID, BCOM_DEVICEID_BCM5789,
- "Broadcom BCM5789 Gigabit Ethernet" },
- { BCOM_VENDORID, BCOM_DEVICEID_BCM5901,
- "Broadcom BCM5901 Fast Ethernet" },
- { BCOM_VENDORID, BCOM_DEVICEID_BCM5901A2,
- "Broadcom BCM5901A2 Fast Ethernet" },
- { SK_VENDORID, SK_DEVICEID_ALTIMA,
- "SysKonnect Gigabit Ethernet" },
- { ALTIMA_VENDORID, ALTIMA_DEVICE_AC1000,
- "Altima AC1000 Gigabit Ethernet" },
- { ALTIMA_VENDORID, ALTIMA_DEVICE_AC1002,
- "Altima AC1002 Gigabit Ethernet" },
- { ALTIMA_VENDORID, ALTIMA_DEVICE_AC9100,
- "Altima AC9100 Gigabit Ethernet" },
- { 0, 0, NULL }
+ { TC_VENDORID, TC_DEVICEID_3C996 },
+
+ { 0, 0 }
};
-static int bge_probe (device_t);
-static int bge_attach (device_t);
-static int bge_detach (device_t);
-static int bge_suspend (device_t);
-static int bge_resume (device_t);
-static void bge_release_resources
- (struct bge_softc *);
-static void bge_dma_map_addr (void *, bus_dma_segment_t *, int, int);
-static int bge_dma_alloc (device_t);
-static void bge_dma_free (struct bge_softc *);
-
-static void bge_txeof (struct bge_softc *);
-static void bge_rxeof (struct bge_softc *);
-
-static void bge_tick_locked (struct bge_softc *);
-static void bge_tick (void *);
-static void bge_stats_update (struct bge_softc *);
-static void bge_stats_update_regs
- (struct bge_softc *);
-static int bge_encap (struct bge_softc *, struct mbuf *,
- u_int32_t *);
-
-static void bge_intr (void *);
-static void bge_start_locked (struct ifnet *);
-static void bge_start (struct ifnet *);
-static int bge_ioctl (struct ifnet *, u_long, caddr_t);
-static void bge_init_locked (struct bge_softc *);
-static void bge_init (void *);
-static void bge_stop (struct bge_softc *);
-static void bge_watchdog (struct ifnet *);
-static void bge_shutdown (device_t);
-static int bge_ifmedia_upd (struct ifnet *);
-static void bge_ifmedia_sts (struct ifnet *, struct ifmediareq *);
-
-static u_int8_t bge_eeprom_getbyte (struct bge_softc *, int, u_int8_t *);
-static int bge_read_eeprom (struct bge_softc *, caddr_t, int, int);
-
-static void bge_setmulti (struct bge_softc *);
-
-static int bge_newbuf_std (struct bge_softc *, int, struct mbuf *);
-static int bge_newbuf_jumbo (struct bge_softc *, int, struct mbuf *);
-static int bge_init_rx_ring_std (struct bge_softc *);
-static void bge_free_rx_ring_std (struct bge_softc *);
-static int bge_init_rx_ring_jumbo (struct bge_softc *);
-static void bge_free_rx_ring_jumbo (struct bge_softc *);
-static void bge_free_tx_ring (struct bge_softc *);
-static int bge_init_tx_ring (struct bge_softc *);
+static const struct bge_vendor {
+ uint16_t v_id;
+ const char *v_name;
+} bge_vendors[] = {
+ { ALTEON_VENDORID, "Alteon" },
+ { ALTIMA_VENDORID, "Altima" },
+ { APPLE_VENDORID, "Apple" },
+ { BCOM_VENDORID, "Broadcom" },
+ { SK_VENDORID, "SysKonnect" },
+ { TC_VENDORID, "3Com" },
+
+ { 0, NULL }
+};
+
+static const struct bge_revision {
+ uint32_t br_chipid;
+ const char *br_name;
+} bge_revisions[] = {
+ { BGE_CHIPID_BCM5700_A0, "BCM5700 A0" },
+ { BGE_CHIPID_BCM5700_A1, "BCM5700 A1" },
+ { BGE_CHIPID_BCM5700_B0, "BCM5700 B0" },
+ { BGE_CHIPID_BCM5700_B1, "BCM5700 B1" },
+ { BGE_CHIPID_BCM5700_B2, "BCM5700 B2" },
+ { BGE_CHIPID_BCM5700_B3, "BCM5700 B3" },
+ { BGE_CHIPID_BCM5700_ALTIMA, "BCM5700 Altima" },
+ { BGE_CHIPID_BCM5700_C0, "BCM5700 C0" },
+ { BGE_CHIPID_BCM5701_A0, "BCM5701 A0" },
+ { BGE_CHIPID_BCM5701_B0, "BCM5701 B0" },
+ { BGE_CHIPID_BCM5701_B2, "BCM5701 B2" },
+ { BGE_CHIPID_BCM5701_B5, "BCM5701 B5" },
+ { BGE_CHIPID_BCM5703_A0, "BCM5703 A0" },
+ { BGE_CHIPID_BCM5703_A1, "BCM5703 A1" },
+ { BGE_CHIPID_BCM5703_A2, "BCM5703 A2" },
+ { BGE_CHIPID_BCM5703_A3, "BCM5703 A3" },
+ { BGE_CHIPID_BCM5703_B0, "BCM5703 B0" },
+ { BGE_CHIPID_BCM5704_A0, "BCM5704 A0" },
+ { BGE_CHIPID_BCM5704_A1, "BCM5704 A1" },
+ { BGE_CHIPID_BCM5704_A2, "BCM5704 A2" },
+ { BGE_CHIPID_BCM5704_A3, "BCM5704 A3" },
+ { BGE_CHIPID_BCM5704_B0, "BCM5704 B0" },
+ { BGE_CHIPID_BCM5705_A0, "BCM5705 A0" },
+ { BGE_CHIPID_BCM5705_A1, "BCM5705 A1" },
+ { BGE_CHIPID_BCM5705_A2, "BCM5705 A2" },
+ { BGE_CHIPID_BCM5705_A3, "BCM5705 A3" },
+ { BGE_CHIPID_BCM5750_A0, "BCM5750 A0" },
+ { BGE_CHIPID_BCM5750_A1, "BCM5750 A1" },
+ { BGE_CHIPID_BCM5750_A3, "BCM5750 A3" },
+ { BGE_CHIPID_BCM5750_B0, "BCM5750 B0" },
+ { BGE_CHIPID_BCM5750_B1, "BCM5750 B1" },
+ { BGE_CHIPID_BCM5750_C0, "BCM5750 C0" },
+ { BGE_CHIPID_BCM5750_C1, "BCM5750 C1" },
+ { BGE_CHIPID_BCM5750_C2, "BCM5750 C2" },
+ { BGE_CHIPID_BCM5714_A0, "BCM5714 A0" },
+ { BGE_CHIPID_BCM5752_A0, "BCM5752 A0" },
+ { BGE_CHIPID_BCM5752_A1, "BCM5752 A1" },
+ { BGE_CHIPID_BCM5752_A2, "BCM5752 A2" },
+ { BGE_CHIPID_BCM5714_B0, "BCM5714 B0" },
+ { BGE_CHIPID_BCM5714_B3, "BCM5714 B3" },
+ { BGE_CHIPID_BCM5715_A0, "BCM5715 A0" },
+ { BGE_CHIPID_BCM5715_A1, "BCM5715 A1" },
+ { BGE_CHIPID_BCM5715_A3, "BCM5715 A3" },
+ { BGE_CHIPID_BCM5755_A0, "BCM5755 A0" },
+ { BGE_CHIPID_BCM5755_A1, "BCM5755 A1" },
+ { BGE_CHIPID_BCM5755_A2, "BCM5755 A2" },
+ /* 5754 and 5787 share the same ASIC ID */
+ { BGE_CHIPID_BCM5787_A0, "BCM5754/5787 A0" },
+ { BGE_CHIPID_BCM5787_A1, "BCM5754/5787 A1" },
+ { BGE_CHIPID_BCM5787_A2, "BCM5754/5787 A2" },
-static int bge_chipinit (struct bge_softc *);
-static int bge_blockinit (struct bge_softc *);
+ { 0, NULL }
+};
-#ifdef notdef
-static u_int8_t bge_vpd_readbyte(struct bge_softc *, int);
-static void bge_vpd_read_res (struct bge_softc *, struct vpd_res *, int);
-static void bge_vpd_read (struct bge_softc *);
-#endif
+/*
+ * Some defaults for major revisions, so that newer steppings
+ * that we don't know about have a shot at working.
+ */
+static const struct bge_revision bge_majorrevs[] = {
+ { BGE_ASICREV_BCM5700, "unknown BCM5700" },
+ { BGE_ASICREV_BCM5701, "unknown BCM5701" },
+ { BGE_ASICREV_BCM5703, "unknown BCM5703" },
+ { BGE_ASICREV_BCM5704, "unknown BCM5704" },
+ { BGE_ASICREV_BCM5705, "unknown BCM5705" },
+ { BGE_ASICREV_BCM5750, "unknown BCM5750" },
+ { BGE_ASICREV_BCM5714_A0, "unknown BCM5714" },
+ { BGE_ASICREV_BCM5752, "unknown BCM5752" },
+ { BGE_ASICREV_BCM5780, "unknown BCM5780" },
+ { BGE_ASICREV_BCM5714, "unknown BCM5714" },
+ { BGE_ASICREV_BCM5755, "unknown BCM5755" },
+ /* 5754 and 5787 share the same ASIC ID */
+ { BGE_ASICREV_BCM5787, "unknown BCM5754/5787" },
-static u_int32_t bge_readmem_ind
- (struct bge_softc *, int);
-static void bge_writemem_ind (struct bge_softc *, int, int);
+ { 0, NULL }
+};
+
+#define BGE_IS_JUMBO_CAPABLE(sc) ((sc)->bge_flags & BGE_FLAG_JUMBO)
+#define BGE_IS_5700_FAMILY(sc) ((sc)->bge_flags & BGE_FLAG_5700_FAMILY)
+#define BGE_IS_5705_PLUS(sc) ((sc)->bge_flags & BGE_FLAG_5705_PLUS)
+#define BGE_IS_5714_FAMILY(sc) ((sc)->bge_flags & BGE_FLAG_5714_FAMILY)
+#define BGE_IS_575X_PLUS(sc) ((sc)->bge_flags & BGE_FLAG_575X_PLUS)
+
+const struct bge_revision * bge_lookup_rev(uint32_t);
+const struct bge_vendor * bge_lookup_vendor(uint16_t);
+static int bge_probe(device_t);
+static int bge_attach(device_t);
+static int bge_detach(device_t);
+static int bge_suspend(device_t);
+static int bge_resume(device_t);
+static void bge_release_resources(struct bge_softc *);
+static void bge_dma_map_addr(void *, bus_dma_segment_t *, int, int);
+static int bge_dma_alloc(device_t);
+static void bge_dma_free(struct bge_softc *);
+
+static void bge_txeof(struct bge_softc *);
+static void bge_rxeof(struct bge_softc *);
+
+static void bge_asf_driver_up (struct bge_softc *);
+static void bge_tick(void *);
+static void bge_stats_update(struct bge_softc *);
+static void bge_stats_update_regs(struct bge_softc *);
+static int bge_encap(struct bge_softc *, struct mbuf **, uint32_t *);
+
+static void bge_intr(void *);
+static void bge_start_locked(struct ifnet *);
+static void bge_start(struct ifnet *);
+static int bge_ioctl(struct ifnet *, u_long, caddr_t);
+static void bge_init_locked(struct bge_softc *);
+static void bge_init(void *);
+static void bge_stop(struct bge_softc *);
+static void bge_watchdog(struct bge_softc *);
+static void bge_shutdown(device_t);
+static int bge_ifmedia_upd_locked(struct ifnet *);
+static int bge_ifmedia_upd(struct ifnet *);
+static void bge_ifmedia_sts(struct ifnet *, struct ifmediareq *);
+
+static uint8_t bge_eeprom_getbyte(struct bge_softc *, int, uint8_t *);
+static int bge_read_eeprom(struct bge_softc *, caddr_t, int, int);
+
+static void bge_setpromisc(struct bge_softc *);
+static void bge_setmulti(struct bge_softc *);
+static void bge_setvlan(struct bge_softc *);
+
+static int bge_newbuf_std(struct bge_softc *, int, struct mbuf *);
+static int bge_newbuf_jumbo(struct bge_softc *, int, struct mbuf *);
+static int bge_init_rx_ring_std(struct bge_softc *);
+static void bge_free_rx_ring_std(struct bge_softc *);
+static int bge_init_rx_ring_jumbo(struct bge_softc *);
+static void bge_free_rx_ring_jumbo(struct bge_softc *);
+static void bge_free_tx_ring(struct bge_softc *);
+static int bge_init_tx_ring(struct bge_softc *);
+
+static int bge_chipinit(struct bge_softc *);
+static int bge_blockinit(struct bge_softc *);
+
+static int bge_has_eeprom(struct bge_softc *);
+static uint32_t bge_readmem_ind(struct bge_softc *, int);
+static void bge_writemem_ind(struct bge_softc *, int, int);
#ifdef notdef
-static u_int32_t bge_readreg_ind
- (struct bge_softc *, int);
+static uint32_t bge_readreg_ind(struct bge_softc *, int);
#endif
-static void bge_writereg_ind (struct bge_softc *, int, int);
+static void bge_writemem_direct(struct bge_softc *, int, int);
+static void bge_writereg_ind(struct bge_softc *, int, int);
-static int bge_miibus_readreg (device_t, int, int);
-static int bge_miibus_writereg (device_t, int, int, int);
-static void bge_miibus_statchg (device_t);
+static int bge_miibus_readreg(device_t, int, int);
+static int bge_miibus_writereg(device_t, int, int, int);
+static void bge_miibus_statchg(device_t);
#ifdef DEVICE_POLLING
-static void bge_poll (struct ifnet *ifp, enum poll_cmd cmd,
- int count);
-static void bge_poll_locked (struct ifnet *ifp, enum poll_cmd cmd,
- int count);
+static void bge_poll(struct ifnet *ifp, enum poll_cmd cmd, int count);
#endif
-static void bge_reset (struct bge_softc *);
-static void bge_link_upd (struct bge_softc *);
+#define BGE_RESET_START 1
+#define BGE_RESET_STOP 2
+static void bge_sig_post_reset(struct bge_softc *, int);
+static void bge_sig_legacy(struct bge_softc *, int);
+static void bge_sig_pre_reset(struct bge_softc *, int);
+static int bge_reset(struct bge_softc *);
+static void bge_link_upd(struct bge_softc *);
+
+/*
+ * The BGE_REGISTER_DEBUG option is only for low-level debugging. It may
+ * leak information to untrusted users. It is also known to cause alignment
+ * traps on certain architectures.
+ */
+#ifdef BGE_REGISTER_DEBUG
+static int bge_sysctl_debug_info(SYSCTL_HANDLER_ARGS);
+static int bge_sysctl_reg_read(SYSCTL_HANDLER_ARGS);
+static int bge_sysctl_mem_read(SYSCTL_HANDLER_ARGS);
+#endif
+static void bge_add_sysctls(struct bge_softc *);
+static int bge_sysctl_stats(SYSCTL_HANDLER_ARGS);
static device_method_t bge_methods[] = {
/* Device interface */
@@ -306,23 +425,74 @@
DRIVER_MODULE(bge, pci, bge_driver, bge_devclass, 0, 0);
DRIVER_MODULE(miibus, bge, miibus_driver, miibus_devclass, 0, 0);
-static u_int32_t
-bge_readmem_ind(sc, off)
- struct bge_softc *sc;
- int off;
+static int bge_allow_asf = 0;
+
+TUNABLE_INT("hw.bge.allow_asf", &bge_allow_asf);
+
+SYSCTL_NODE(_hw, OID_AUTO, bge, CTLFLAG_RD, 0, "BGE driver parameters");
+SYSCTL_INT(_hw_bge, OID_AUTO, allow_asf, CTLFLAG_RD, &bge_allow_asf, 0,
+ "Allow ASF mode if available");
+
+#define SPARC64_BLADE_1500_MODEL "SUNW,Sun-Blade-1500"
+#define SPARC64_BLADE_1500_PATH_BGE "/pci at 1f,700000/network at 2"
+#define SPARC64_BLADE_2500_MODEL "SUNW,Sun-Blade-2500"
+#define SPARC64_BLADE_2500_PATH_BGE "/pci at 1c,600000/network at 3"
+#define SPARC64_OFW_SUBVENDOR "subsystem-vendor-id"
+
+static int
+bge_has_eeprom(struct bge_softc *sc)
{
+#ifdef __sparc64__
+ char buf[sizeof(SPARC64_BLADE_1500_PATH_BGE)];
device_t dev;
+ uint32_t subvendor;
+
+ dev = sc->bge_dev;
+
+ /*
+ * The on-board BGEs found in sun4u machines aren't fitted with
+ * an EEPROM which means that we have to obtain the MAC address
+ * via OFW and that some tests will always fail. We distinguish
+ * such BGEs by the subvendor ID, which also has to be obtained
+ * from OFW instead of the PCI configuration space as the latter
+ * indicates Broadcom as the subvendor of the netboot interface.
+ * For early Blade 1500 and 2500 we even have to check the OFW
+ * device path as the subvendor ID always defaults to Broadcom
+ * there.
+ */
+ if (OF_getprop(ofw_bus_get_node(dev), SPARC64_OFW_SUBVENDOR,
+ &subvendor, sizeof(subvendor)) == sizeof(subvendor) &&
+ subvendor == SUN_VENDORID)
+ return (0);
+ memset(buf, 0, sizeof(buf));
+ if (OF_package_to_path(ofw_bus_get_node(dev), buf, sizeof(buf)) > 0) {
+ if (strcmp(sparc64_model, SPARC64_BLADE_1500_MODEL) == 0 &&
+ strcmp(buf, SPARC64_BLADE_1500_PATH_BGE) == 0)
+ return (0);
+ if (strcmp(sparc64_model, SPARC64_BLADE_2500_MODEL) == 0 &&
+ strcmp(buf, SPARC64_BLADE_2500_PATH_BGE) == 0)
+ return (0);
+ }
+#endif
+ return (1);
+}
+
+static uint32_t
+bge_readmem_ind(struct bge_softc *sc, int off)
+{
+ device_t dev;
+ uint32_t val;
dev = sc->bge_dev;
pci_write_config(dev, BGE_PCI_MEMWIN_BASEADDR, off, 4);
- return(pci_read_config(dev, BGE_PCI_MEMWIN_DATA, 4));
+ val = pci_read_config(dev, BGE_PCI_MEMWIN_DATA, 4);
+ pci_write_config(dev, BGE_PCI_MEMWIN_BASEADDR, 0, 4);
+ return (val);
}
static void
-bge_writemem_ind(sc, off, val)
- struct bge_softc *sc;
- int off, val;
+bge_writemem_ind(struct bge_softc *sc, int off, int val)
{
device_t dev;
@@ -330,29 +500,24 @@
pci_write_config(dev, BGE_PCI_MEMWIN_BASEADDR, off, 4);
pci_write_config(dev, BGE_PCI_MEMWIN_DATA, val, 4);
-
- return;
+ pci_write_config(dev, BGE_PCI_MEMWIN_BASEADDR, 0, 4);
}
#ifdef notdef
-static u_int32_t
-bge_readreg_ind(sc, off)
- struct bge_softc *sc;
- int off;
+static uint32_t
+bge_readreg_ind(struct bge_softc *sc, int off)
{
device_t dev;
dev = sc->bge_dev;
pci_write_config(dev, BGE_PCI_REG_BASEADDR, off, 4);
- return(pci_read_config(dev, BGE_PCI_REG_DATA, 4));
+ return (pci_read_config(dev, BGE_PCI_REG_DATA, 4));
}
#endif
static void
-bge_writereg_ind(sc, off, val)
- struct bge_softc *sc;
- int off, val;
+bge_writereg_ind(struct bge_softc *sc, int off, int val)
{
device_t dev;
@@ -360,8 +525,12 @@
pci_write_config(dev, BGE_PCI_REG_BASEADDR, off, 4);
pci_write_config(dev, BGE_PCI_REG_DATA, val, 4);
+}
- return;
+static void
+bge_writemem_direct(struct bge_softc *sc, int off, int val)
+{
+ CSR_WRITE_4(sc, off, val);
}
/*
@@ -369,11 +538,7 @@
*/
static void
-bge_dma_map_addr(arg, segs, nseg, error)
- void *arg;
- bus_dma_segment_t *segs;
- int nseg;
- int error;
+bge_dma_map_addr(void *arg, bus_dma_segment_t *segs, int nseg, int error)
{
struct bge_dmamap_arg *ctx;
@@ -388,116 +553,19 @@
}
ctx->bge_busaddr = segs->ds_addr;
-
- return;
}
-#ifdef notdef
-static u_int8_t
-bge_vpd_readbyte(sc, addr)
- struct bge_softc *sc;
- int addr;
-{
- int i;
- device_t dev;
- u_int32_t val;
-
- dev = sc->bge_dev;
- pci_write_config(dev, BGE_PCI_VPD_ADDR, addr, 2);
- for (i = 0; i < BGE_TIMEOUT * 10; i++) {
- DELAY(10);
- if (pci_read_config(dev, BGE_PCI_VPD_ADDR, 2) & BGE_VPD_FLAG)
- break;
- }
-
- if (i == BGE_TIMEOUT) {
- device_printf(sc->bge_dev, "VPD read timed out\n");
- return(0);
- }
-
- val = pci_read_config(dev, BGE_PCI_VPD_DATA, 4);
-
- return((val >> ((addr % 4) * 8)) & 0xFF);
-}
-
-static void
-bge_vpd_read_res(sc, res, addr)
- struct bge_softc *sc;
- struct vpd_res *res;
- int addr;
-{
- int i;
- u_int8_t *ptr;
-
- ptr = (u_int8_t *)res;
- for (i = 0; i < sizeof(struct vpd_res); i++)
- ptr[i] = bge_vpd_readbyte(sc, i + addr);
-
- return;
-}
-
-static void
-bge_vpd_read(sc)
- struct bge_softc *sc;
-{
- int pos = 0, i;
- struct vpd_res res;
-
- if (sc->bge_vpd_prodname != NULL)
- free(sc->bge_vpd_prodname, M_DEVBUF);
- if (sc->bge_vpd_readonly != NULL)
- free(sc->bge_vpd_readonly, M_DEVBUF);
- sc->bge_vpd_prodname = NULL;
- sc->bge_vpd_readonly = NULL;
-
- bge_vpd_read_res(sc, &res, pos);
-
- if (res.vr_id != VPD_RES_ID) {
- device_printf(sc->bge_dev,
- "bad VPD resource id: expected %x got %x\n", VPD_RES_ID,
- res.vr_id);
- return;
- }
-
- pos += sizeof(res);
- sc->bge_vpd_prodname = malloc(res.vr_len + 1, M_DEVBUF, M_NOWAIT);
- for (i = 0; i < res.vr_len; i++)
- sc->bge_vpd_prodname[i] = bge_vpd_readbyte(sc, i + pos);
- sc->bge_vpd_prodname[i] = '\0';
- pos += i;
-
- bge_vpd_read_res(sc, &res, pos);
-
- if (res.vr_id != VPD_RES_READ) {
- device_printf(sc->bge_dev,
- "bad VPD resource id: expected %x got %x\n", VPD_RES_READ,
- res.vr_id);
- return;
- }
-
- pos += sizeof(res);
- sc->bge_vpd_readonly = malloc(res.vr_len, M_DEVBUF, M_NOWAIT);
- for (i = 0; i < res.vr_len + 1; i++)
- sc->bge_vpd_readonly[i] = bge_vpd_readbyte(sc, i + pos);
-
- return;
-}
-#endif
-
/*
* Read a byte of data stored in the EEPROM at address 'addr.' The
* BCM570x supports both the traditional bitbang interface and an
* auto access interface for reading the EEPROM. We use the auto
* access method.
*/
-static u_int8_t
-bge_eeprom_getbyte(sc, addr, dest)
- struct bge_softc *sc;
- int addr;
- u_int8_t *dest;
+static uint8_t
+bge_eeprom_getbyte(struct bge_softc *sc, int addr, uint8_t *dest)
{
int i;
- u_int32_t byte = 0;
+ uint32_t byte = 0;
/*
* Enable use of auto EEPROM access so we can avoid
@@ -507,7 +575,7 @@
/* Reset the EEPROM, load the clock period. */
CSR_WRITE_4(sc, BGE_EE_ADDR,
- BGE_EEADDR_RESET|BGE_EEHALFCLK(BGE_HALFCLK_384SCL));
+ BGE_EEADDR_RESET | BGE_EEHALFCLK(BGE_HALFCLK_384SCL));
DELAY(20);
/* Issue the read EEPROM command. */
@@ -520,9 +588,9 @@
break;
}
- if (i == BGE_TIMEOUT) {
+ if (i == BGE_TIMEOUT * 10) {
device_printf(sc->bge_dev, "EEPROM read timed out\n");
- return(1);
+ return (1);
}
/* Get result. */
@@ -530,39 +598,33 @@
*dest = (byte >> ((addr % 4) * 8)) & 0xFF;
- return(0);
+ return (0);
}
/*
* Read a sequence of bytes from the EEPROM.
*/
static int
-bge_read_eeprom(sc, dest, off, cnt)
- struct bge_softc *sc;
- caddr_t dest;
- int off;
- int cnt;
+bge_read_eeprom(struct bge_softc *sc, caddr_t dest, int off, int cnt)
{
- int err = 0, i;
- u_int8_t byte = 0;
+ int i, error = 0;
+ uint8_t byte = 0;
for (i = 0; i < cnt; i++) {
- err = bge_eeprom_getbyte(sc, off + i, &byte);
- if (err)
+ error = bge_eeprom_getbyte(sc, off + i, &byte);
+ if (error)
break;
*(dest + i) = byte;
}
- return(err ? 1 : 0);
+ return (error ? 1 : 0);
}
static int
-bge_miibus_readreg(dev, phy, reg)
- device_t dev;
- int phy, reg;
+bge_miibus_readreg(device_t dev, int phy, int reg)
{
struct bge_softc *sc;
- u_int32_t val, autopoll;
+ uint32_t val, autopoll;
int i;
sc = device_get_softc(dev);
@@ -577,7 +639,7 @@
* special-cased.
*/
if (phy != 1)
- return(0);
+ return (0);
/* Reading with autopolling on may trigger PCI errors */
autopoll = CSR_READ_4(sc, BGE_MI_MODE);
@@ -586,17 +648,18 @@
DELAY(40);
}
- CSR_WRITE_4(sc, BGE_MI_COMM, BGE_MICMD_READ|BGE_MICOMM_BUSY|
- BGE_MIPHY(phy)|BGE_MIREG(reg));
+ CSR_WRITE_4(sc, BGE_MI_COMM, BGE_MICMD_READ | BGE_MICOMM_BUSY |
+ BGE_MIPHY(phy) | BGE_MIREG(reg));
for (i = 0; i < BGE_TIMEOUT; i++) {
+ DELAY(10);
val = CSR_READ_4(sc, BGE_MI_COMM);
if (!(val & BGE_MICOMM_BUSY))
break;
}
if (i == BGE_TIMEOUT) {
- if_printf(sc->bge_ifp, "PHY read timed out\n");
+ device_printf(sc->bge_dev, "PHY read timed out\n");
val = 0;
goto done;
}
@@ -610,18 +673,16 @@
}
if (val & BGE_MICOMM_READFAIL)
- return(0);
+ return (0);
- return(val & 0xFFFF);
+ return (val & 0xFFFF);
}
static int
-bge_miibus_writereg(dev, phy, reg, val)
- device_t dev;
- int phy, reg, val;
+bge_miibus_writereg(device_t dev, int phy, int reg, int val)
{
struct bge_softc *sc;
- u_int32_t autopoll;
+ uint32_t autopoll;
int i;
sc = device_get_softc(dev);
@@ -633,71 +694,63 @@
DELAY(40);
}
- CSR_WRITE_4(sc, BGE_MI_COMM, BGE_MICMD_WRITE|BGE_MICOMM_BUSY|
- BGE_MIPHY(phy)|BGE_MIREG(reg)|val);
+ CSR_WRITE_4(sc, BGE_MI_COMM, BGE_MICMD_WRITE | BGE_MICOMM_BUSY |
+ BGE_MIPHY(phy) | BGE_MIREG(reg) | val);
for (i = 0; i < BGE_TIMEOUT; i++) {
+ DELAY(10);
if (!(CSR_READ_4(sc, BGE_MI_COMM) & BGE_MICOMM_BUSY))
break;
}
+ if (i == BGE_TIMEOUT) {
+ device_printf(sc->bge_dev, "PHY write timed out\n");
+ return (0);
+ }
+
if (autopoll & BGE_MIMODE_AUTOPOLL) {
BGE_SETBIT(sc, BGE_MI_MODE, BGE_MIMODE_AUTOPOLL);
DELAY(40);
}
- if (i == BGE_TIMEOUT) {
- if_printf(sc->bge_ifp, "PHY read timed out\n");
- return(0);
- }
-
- return(0);
+ return (0);
}
static void
-bge_miibus_statchg(dev)
- device_t dev;
+bge_miibus_statchg(device_t dev)
{
struct bge_softc *sc;
struct mii_data *mii;
-
sc = device_get_softc(dev);
mii = device_get_softc(sc->bge_miibus);
BGE_CLRBIT(sc, BGE_MAC_MODE, BGE_MACMODE_PORTMODE);
- if (IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_T) {
+ if (IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_T)
BGE_SETBIT(sc, BGE_MAC_MODE, BGE_PORTMODE_GMII);
- } else {
+ else
BGE_SETBIT(sc, BGE_MAC_MODE, BGE_PORTMODE_MII);
- }
- if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) {
+ if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX)
BGE_CLRBIT(sc, BGE_MAC_MODE, BGE_MACMODE_HALF_DUPLEX);
- } else {
+ else
BGE_SETBIT(sc, BGE_MAC_MODE, BGE_MACMODE_HALF_DUPLEX);
- }
-
- return;
}
/*
* Intialize a standard receive ring descriptor.
*/
static int
-bge_newbuf_std(sc, i, m)
- struct bge_softc *sc;
- int i;
- struct mbuf *m;
-{
- struct mbuf *m_new = NULL;
- struct bge_rx_bd *r;
- struct bge_dmamap_arg ctx;
- int error;
+bge_newbuf_std(struct bge_softc *sc, int i, struct mbuf *m)
+{
+ struct mbuf *m_new = NULL;
+ struct bge_rx_bd *r;
+ struct bge_dmamap_arg ctx;
+ int error;
if (m == NULL) {
m_new = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR);
if (m_new == NULL)
- return(ENOBUFS);
+ return (ENOBUFS);
m_new->m_len = m_new->m_pkthdr.len = MCLBYTES;
} else {
m_new = m;
@@ -705,7 +758,7 @@
m_new->m_data = m_new->m_ext.ext_buf;
}
- if (!sc->bge_rx_alignment_bug)
+ if ((sc->bge_flags & BGE_FLAG_RX_ALIGNBUG) == 0)
m_adj(m_new, ETHER_ALIGN);
sc->bge_cdata.bge_rx_std_chain[i] = m_new;
r = &sc->bge_ldata.bge_rx_std_ring[i];
@@ -719,7 +772,7 @@
sc->bge_cdata.bge_rx_std_chain[i] = NULL;
m_freem(m_new);
}
- return(ENOMEM);
+ return (ENOMEM);
}
r->bge_addr.bge_addr_lo = BGE_ADDR_LO(ctx.bge_busaddr);
r->bge_addr.bge_addr_hi = BGE_ADDR_HI(ctx.bge_busaddr);
@@ -731,7 +784,7 @@
sc->bge_cdata.bge_rx_std_dmamap[i],
BUS_DMASYNC_PREREAD);
- return(0);
+ return (0);
}
/*
@@ -739,10 +792,7 @@
* a jumbo buffer from the pool managed internally by the driver.
*/
static int
-bge_newbuf_jumbo(sc, i, m)
- struct bge_softc *sc;
- int i;
- struct mbuf *m;
+bge_newbuf_jumbo(struct bge_softc *sc, int i, struct mbuf *m)
{
bus_dma_segment_t segs[BGE_NSEG_JUMBO];
struct bge_extrx_bd *r;
@@ -753,12 +803,12 @@
if (m == NULL) {
MGETHDR(m_new, M_DONTWAIT, MT_DATA);
if (m_new == NULL)
- return(ENOBUFS);
+ return (ENOBUFS);
m_cljget(m_new, M_DONTWAIT, MJUM9BYTES);
if (!(m_new->m_flags & M_EXT)) {
m_freem(m_new);
- return(ENOBUFS);
+ return (ENOBUFS);
}
m_new->m_len = m_new->m_pkthdr.len = MJUM9BYTES;
} else {
@@ -767,7 +817,7 @@
m_new->m_data = m_new->m_ext.ext_buf;
}
- if (!sc->bge_rx_alignment_bug)
+ if ((sc->bge_flags & BGE_FLAG_RX_ALIGNBUG) == 0)
m_adj(m_new, ETHER_ALIGN);
error = bus_dmamap_load_mbuf_sg(sc->bge_cdata.bge_mtag_jumbo,
@@ -776,7 +826,7 @@
if (error) {
if (m == NULL)
m_freem(m_new);
- return(error);
+ return (error);
}
sc->bge_cdata.bge_rx_jumbo_chain[i] = m_new;
@@ -784,7 +834,7 @@
* Fill in the extended RX buffer descriptor.
*/
r = &sc->bge_ldata.bge_rx_jumbo_ring[i];
- r->bge_flags = BGE_RXBDFLAG_JUMBO_RING|BGE_RXBDFLAG_END;
+ r->bge_flags = BGE_RXBDFLAG_JUMBO_RING | BGE_RXBDFLAG_END;
r->bge_idx = i;
r->bge_len3 = r->bge_len2 = r->bge_len1 = 0;
switch (nsegs) {
@@ -823,29 +873,27 @@
* the NIC.
*/
static int
-bge_init_rx_ring_std(sc)
- struct bge_softc *sc;
+bge_init_rx_ring_std(struct bge_softc *sc)
{
int i;
for (i = 0; i < BGE_SSLOTS; i++) {
if (bge_newbuf_std(sc, i, NULL) == ENOBUFS)
- return(ENOBUFS);
+ return (ENOBUFS);
};
bus_dmamap_sync(sc->bge_cdata.bge_rx_std_ring_tag,
sc->bge_cdata.bge_rx_std_ring_map,
- BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE);
+ BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
sc->bge_std = i - 1;
CSR_WRITE_4(sc, BGE_MBX_RX_STD_PROD_LO, sc->bge_std);
- return(0);
+ return (0);
}
static void
-bge_free_rx_ring_std(sc)
- struct bge_softc *sc;
+bge_free_rx_ring_std(struct bge_softc *sc)
{
int i;
@@ -862,25 +910,22 @@
bzero((char *)&sc->bge_ldata.bge_rx_std_ring[i],
sizeof(struct bge_rx_bd));
}
-
- return;
}
static int
-bge_init_rx_ring_jumbo(sc)
- struct bge_softc *sc;
+bge_init_rx_ring_jumbo(struct bge_softc *sc)
{
struct bge_rcb *rcb;
int i;
for (i = 0; i < BGE_JUMBO_RX_RING_CNT; i++) {
if (bge_newbuf_jumbo(sc, i, NULL) == ENOBUFS)
- return(ENOBUFS);
+ return (ENOBUFS);
};
bus_dmamap_sync(sc->bge_cdata.bge_rx_jumbo_ring_tag,
sc->bge_cdata.bge_rx_jumbo_ring_map,
- BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE);
+ BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
sc->bge_jumbo = i - 1;
@@ -891,12 +936,11 @@
CSR_WRITE_4(sc, BGE_MBX_RX_JUMBO_PROD_LO, sc->bge_jumbo);
- return(0);
+ return (0);
}
static void
-bge_free_rx_ring_jumbo(sc)
- struct bge_softc *sc;
+bge_free_rx_ring_jumbo(struct bge_softc *sc)
{
int i;
@@ -913,13 +957,10 @@
bzero((char *)&sc->bge_ldata.bge_rx_jumbo_ring[i],
sizeof(struct bge_extrx_bd));
}
-
- return;
}
static void
-bge_free_tx_ring(sc)
- struct bge_softc *sc;
+bge_free_tx_ring(struct bge_softc *sc)
{
int i;
@@ -939,13 +980,10 @@
bzero((char *)&sc->bge_ldata.bge_tx_ring[i],
sizeof(struct bge_tx_bd));
}
-
- return;
}
static int
-bge_init_tx_ring(sc)
- struct bge_softc *sc;
+bge_init_tx_ring(struct bge_softc *sc)
{
sc->bge_txcnt = 0;
sc->bge_tx_saved_considx = 0;
@@ -964,16 +1002,31 @@
if (sc->bge_chiprev == BGE_CHIPREV_5700_BX)
CSR_WRITE_4(sc, BGE_MBX_TX_NIC_PROD0_LO, 0);
- return(0);
+ return (0);
}
static void
-bge_setmulti(sc)
- struct bge_softc *sc;
+bge_setpromisc(struct bge_softc *sc)
+{
+ struct ifnet *ifp;
+
+ BGE_LOCK_ASSERT(sc);
+
+ ifp = sc->bge_ifp;
+
+ /* Enable or disable promiscuous mode as needed. */
+ if (ifp->if_flags & IFF_PROMISC)
+ BGE_SETBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_PROMISC);
+ else
+ BGE_CLRBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_PROMISC);
+}
+
+static void
+bge_setmulti(struct bge_softc *sc)
{
struct ifnet *ifp;
struct ifmultiaddr *ifma;
- u_int32_t hashes[4] = { 0, 0, 0, 0 };
+ uint32_t hashes[4] = { 0, 0, 0, 0 };
int h, i;
BGE_LOCK_ASSERT(sc);
@@ -1003,8 +1056,100 @@
for (i = 0; i < 4; i++)
CSR_WRITE_4(sc, BGE_MAR0 + (i * 4), hashes[i]);
+}
+
+static void
+bge_setvlan(struct bge_softc *sc)
+{
+ struct ifnet *ifp;
+
+ BGE_LOCK_ASSERT(sc);
+
+ ifp = sc->bge_ifp;
+
+ /* Enable or disable VLAN tag stripping as needed. */
+ if (ifp->if_capenable & IFCAP_VLAN_HWTAGGING)
+ BGE_CLRBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_KEEP_VLAN_DIAG);
+ else
+ BGE_SETBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_KEEP_VLAN_DIAG);
+}
+
+static void
+bge_sig_pre_reset(sc, type)
+ struct bge_softc *sc;
+ int type;
+{
+ /*
+ * Some chips don't like this so only do this if ASF is enabled
+ */
+ if (sc->bge_asf_mode)
+ bge_writemem_ind(sc, BGE_SOFTWARE_GENCOMM, BGE_MAGIC_NUMBER);
+
+ if (sc->bge_asf_mode & ASF_NEW_HANDSHAKE) {
+ switch (type) {
+ case BGE_RESET_START:
+ bge_writemem_ind(sc, BGE_SDI_STATUS, 0x1); /* START */
+ break;
+ case BGE_RESET_STOP:
+ bge_writemem_ind(sc, BGE_SDI_STATUS, 0x2); /* UNLOAD */
+ break;
+ }
+ }
+}
+
+static void
+bge_sig_post_reset(sc, type)
+ struct bge_softc *sc;
+ int type;
+{
+ if (sc->bge_asf_mode & ASF_NEW_HANDSHAKE) {
+ switch (type) {
+ case BGE_RESET_START:
+ bge_writemem_ind(sc, BGE_SDI_STATUS, 0x80000001);
+ /* START DONE */
+ break;
+ case BGE_RESET_STOP:
+ bge_writemem_ind(sc, BGE_SDI_STATUS, 0x80000002);
+ break;
+ }
+ }
+}
+
+static void
+bge_sig_legacy(sc, type)
+ struct bge_softc *sc;
+ int type;
+{
+ if (sc->bge_asf_mode) {
+ switch (type) {
+ case BGE_RESET_START:
+ bge_writemem_ind(sc, BGE_SDI_STATUS, 0x1); /* START */
+ break;
+ case BGE_RESET_STOP:
+ bge_writemem_ind(sc, BGE_SDI_STATUS, 0x2); /* UNLOAD */
+ break;
+ }
+ }
+}
- return;
+void bge_stop_fw(struct bge_softc *);
+void
+bge_stop_fw(sc)
+ struct bge_softc *sc;
+{
+ int i;
+
+ if (sc->bge_asf_mode) {
+ bge_writemem_ind(sc, BGE_SOFTWARE_GENCOMM_FW, BGE_FW_PAUSE);
+ CSR_WRITE_4(sc, BGE_CPU_EVENT,
+ CSR_READ_4(sc, BGE_CPU_EVENT) | (1 << 14));
+
+ for (i = 0; i < 100; i++ ) {
+ if (!(CSR_READ_4(sc, BGE_CPU_EVENT) & (1 << 14)))
+ break;
+ DELAY(10);
+ }
+ }
}
/*
@@ -1012,22 +1157,24 @@
* self-test results.
*/
static int
-bge_chipinit(sc)
- struct bge_softc *sc;
+bge_chipinit(struct bge_softc *sc)
{
- int i;
- u_int32_t dma_rw_ctl;
+ uint32_t dma_rw_ctl;
+ int i;
- /* Set endian type before we access any non-PCI registers. */
+ /* Set endianness before we access any non-PCI registers. */
pci_write_config(sc->bge_dev, BGE_PCI_MISC_CTL, BGE_INIT, 4);
/*
* Check the 'ROM failed' bit on the RX CPU to see if
- * self-tests passed.
+ * self-tests passed. Skip this check when there's no
+ * EEPROM fitted, since in that case it will always
+ * fail.
*/
- if (CSR_READ_4(sc, BGE_RXCPU_MODE) & BGE_RXCPUMODE_ROMFAIL) {
+ if ((sc->bge_flags & BGE_FLAG_EEPROM) &&
+ CSR_READ_4(sc, BGE_RXCPU_MODE) & BGE_RXCPUMODE_ROMFAIL) {
device_printf(sc->bge_dev, "RX CPU self-diagnostics failed!\n");
- return(ENODEV);
+ return (ENODEV);
}
/* Clear the MAC control register */
@@ -1038,99 +1185,102 @@
* internal memory.
*/
for (i = BGE_STATS_BLOCK;
- i < BGE_STATS_BLOCK_END + 1; i += sizeof(u_int32_t))
+ i < BGE_STATS_BLOCK_END + 1; i += sizeof(uint32_t))
BGE_MEMWIN_WRITE(sc, i, 0);
for (i = BGE_STATUS_BLOCK;
- i < BGE_STATUS_BLOCK_END + 1; i += sizeof(u_int32_t))
+ i < BGE_STATUS_BLOCK_END + 1; i += sizeof(uint32_t))
BGE_MEMWIN_WRITE(sc, i, 0);
- /* Set up the PCI DMA control register. */
- if (sc->bge_pcie) {
- dma_rw_ctl = BGE_PCI_READ_CMD|BGE_PCI_WRITE_CMD |
- (0xf << BGE_PCIDMARWCTL_RD_WAT_SHIFT) |
- (0x2 << BGE_PCIDMARWCTL_WR_WAT_SHIFT);
- } else if (pci_read_config(sc->bge_dev, BGE_PCI_PCISTATE, 4) &
- BGE_PCISTATE_PCI_BUSMODE) {
- /* Conventional PCI bus */
- dma_rw_ctl = BGE_PCI_READ_CMD|BGE_PCI_WRITE_CMD |
- (0x7 << BGE_PCIDMARWCTL_RD_WAT_SHIFT) |
- (0x7 << BGE_PCIDMARWCTL_WR_WAT_SHIFT) |
- (0x0F);
- } else {
- /* PCI-X bus */
- /*
- * The 5704 uses a different encoding of read/write
- * watermarks.
- */
- if (sc->bge_asicrev == BGE_ASICREV_BCM5704)
- dma_rw_ctl = BGE_PCI_READ_CMD|BGE_PCI_WRITE_CMD |
- (0x7 << BGE_PCIDMARWCTL_RD_WAT_SHIFT) |
- (0x3 << BGE_PCIDMARWCTL_WR_WAT_SHIFT);
- else
- dma_rw_ctl = BGE_PCI_READ_CMD|BGE_PCI_WRITE_CMD |
- (0x3 << BGE_PCIDMARWCTL_RD_WAT_SHIFT) |
- (0x3 << BGE_PCIDMARWCTL_WR_WAT_SHIFT) |
- (0x0F);
-
- /*
- * 5703 and 5704 need ONEDMA_AT_ONCE as a workaround
- * for hardware bugs.
- */
+ /*
+ * Set up the PCI DMA control register.
+ */
+ dma_rw_ctl = BGE_PCIDMARWCTL_RD_CMD_SHIFT(6) |
+ BGE_PCIDMARWCTL_WR_CMD_SHIFT(7);
+ if (sc->bge_flags & BGE_FLAG_PCIE) {
+ /* Read watermark not used, 128 bytes for write. */
+ dma_rw_ctl |= BGE_PCIDMARWCTL_WR_WAT_SHIFT(3);
+ } else if (sc->bge_flags & BGE_FLAG_PCIX) {
+ if (BGE_IS_5714_FAMILY(sc)) {
+ /* 256 bytes for read and write. */
+ dma_rw_ctl |= BGE_PCIDMARWCTL_RD_WAT_SHIFT(2) |
+ BGE_PCIDMARWCTL_WR_WAT_SHIFT(2);
+ dma_rw_ctl |= (sc->bge_asicrev == BGE_ASICREV_BCM5780) ?
+ BGE_PCIDMARWCTL_ONEDMA_ATONCE_GLOBAL :
+ BGE_PCIDMARWCTL_ONEDMA_ATONCE_LOCAL;
+ } else if (sc->bge_asicrev == BGE_ASICREV_BCM5704) {
+ /* 1536 bytes for read, 384 bytes for write. */
+ dma_rw_ctl |= BGE_PCIDMARWCTL_RD_WAT_SHIFT(7) |
+ BGE_PCIDMARWCTL_WR_WAT_SHIFT(3);
+ } else {
+ /* 384 bytes for read and write. */
+ dma_rw_ctl |= BGE_PCIDMARWCTL_RD_WAT_SHIFT(3) |
+ BGE_PCIDMARWCTL_WR_WAT_SHIFT(3) |
+ 0x0F;
+ }
if (sc->bge_asicrev == BGE_ASICREV_BCM5703 ||
sc->bge_asicrev == BGE_ASICREV_BCM5704) {
- u_int32_t tmp;
+ uint32_t tmp;
- tmp = CSR_READ_4(sc, BGE_PCI_CLKCTL) & 0x1f;
- if (tmp == 0x6 || tmp == 0x7)
- dma_rw_ctl |= BGE_PCIDMARWCTL_ONEDMA_ATONCE;
- }
- }
+ /* Set ONE_DMA_AT_ONCE for hardware workaround. */
+ tmp = CSR_READ_4(sc, BGE_PCI_CLKCTL) & 0x1F;
+ if (tmp == 6 || tmp == 7)
+ dma_rw_ctl |=
+ BGE_PCIDMARWCTL_ONEDMA_ATONCE_GLOBAL;
+ /* Set PCI-X DMA write workaround. */
+ dma_rw_ctl |= BGE_PCIDMARWCTL_ASRT_ALL_BE;
+ }
+ } else {
+ /* Conventional PCI bus: 256 bytes for read and write. */
+ dma_rw_ctl |= BGE_PCIDMARWCTL_RD_WAT_SHIFT(7) |
+ BGE_PCIDMARWCTL_WR_WAT_SHIFT(7);
+
+ if (sc->bge_asicrev != BGE_ASICREV_BCM5705 &&
+ sc->bge_asicrev != BGE_ASICREV_BCM5750)
+ dma_rw_ctl |= 0x0F;
+ }
+ if (sc->bge_asicrev == BGE_ASICREV_BCM5700 ||
+ sc->bge_asicrev == BGE_ASICREV_BCM5701)
+ dma_rw_ctl |= BGE_PCIDMARWCTL_USE_MRM |
+ BGE_PCIDMARWCTL_ASRT_ALL_BE;
if (sc->bge_asicrev == BGE_ASICREV_BCM5703 ||
- sc->bge_asicrev == BGE_ASICREV_BCM5704 ||
- sc->bge_asicrev == BGE_ASICREV_BCM5705 ||
- sc->bge_asicrev == BGE_ASICREV_BCM5750)
+ sc->bge_asicrev == BGE_ASICREV_BCM5704)
dma_rw_ctl &= ~BGE_PCIDMARWCTL_MINDMA;
pci_write_config(sc->bge_dev, BGE_PCI_DMA_RW_CTL, dma_rw_ctl, 4);
/*
* Set up general mode register.
*/
- CSR_WRITE_4(sc, BGE_MODE_CTL, BGE_DMA_SWAP_OPTIONS|
- BGE_MODECTL_MAC_ATTN_INTR|BGE_MODECTL_HOST_SEND_BDS|
+ CSR_WRITE_4(sc, BGE_MODE_CTL, BGE_DMA_SWAP_OPTIONS |
+ BGE_MODECTL_MAC_ATTN_INTR | BGE_MODECTL_HOST_SEND_BDS |
BGE_MODECTL_TX_NO_PHDR_CSUM);
/*
- * Disable memory write invalidate. Apparently it is not supported
- * properly by these devices.
+ * Tell the firmware the driver is running
*/
- PCI_CLRBIT(sc->bge_dev, BGE_PCI_CMD, PCIM_CMD_MWIEN, 4);
+ if (sc->bge_asf_mode & ASF_STACKUP)
+ BGE_SETBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP);
-#ifdef __brokenalpha__
/*
- * Must insure that we do not cross an 8K (bytes) boundary
- * for DMA reads. Our highest limit is 1K bytes. This is a
- * restriction on some ALPHA platforms with early revision
- * 21174 PCI chipsets, such as the AlphaPC 164lx
+ * Disable memory write invalidate. Apparently it is not supported
+ * properly by these devices.
*/
- PCI_SETBIT(sc->bge_dev, BGE_PCI_DMA_RW_CTL,
- BGE_PCI_READ_BNDRY_1024BYTES, 4);
-#endif
+ PCI_CLRBIT(sc->bge_dev, BGE_PCI_CMD, PCIM_CMD_MWIEN, 4);
/* Set the timer prescaler (always 66Mhz) */
- CSR_WRITE_4(sc, BGE_MISC_CFG, 65 << 1/*BGE_32BITTIME_66MHZ*/);
+ CSR_WRITE_4(sc, BGE_MISC_CFG, BGE_32BITTIME_66MHZ);
- return(0);
+ return (0);
}
static int
-bge_blockinit(sc)
- struct bge_softc *sc;
+bge_blockinit(struct bge_softc *sc)
{
struct bge_rcb *rcb;
bus_size_t vrcb;
bge_hostaddr taddr;
+ uint32_t val;
int i;
/*
@@ -1143,24 +1293,13 @@
/* Note: the BCM5704 has a smaller mbuf space than other chips. */
- if (sc->bge_asicrev != BGE_ASICREV_BCM5705 &&
- sc->bge_asicrev != BGE_ASICREV_BCM5750) {
+ if (!(BGE_IS_5705_PLUS(sc))) {
/* Configure mbuf memory pool */
- if (sc->bge_extram) {
- CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_BASEADDR,
- BGE_EXT_SSRAM);
- if (sc->bge_asicrev == BGE_ASICREV_BCM5704)
- CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_LEN, 0x10000);
- else
- CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_LEN, 0x18000);
- } else {
- CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_BASEADDR,
- BGE_BUFFPOOL_1);
- if (sc->bge_asicrev == BGE_ASICREV_BCM5704)
- CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_LEN, 0x10000);
- else
- CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_LEN, 0x18000);
- }
+ CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_BASEADDR, BGE_BUFFPOOL_1);
+ if (sc->bge_asicrev == BGE_ASICREV_BCM5704)
+ CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_LEN, 0x10000);
+ else
+ CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_LEN, 0x18000);
/* Configure DMA resource pool */
CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_BASEADDR,
@@ -1169,8 +1308,7 @@
}
/* Configure mbuf pool watermarks */
- if (sc->bge_asicrev == BGE_ASICREV_BCM5705 ||
- sc->bge_asicrev == BGE_ASICREV_BCM5750) {
+ if (BGE_IS_5705_PLUS(sc)) {
CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 0x0);
CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x10);
} else {
@@ -1184,22 +1322,21 @@
CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_HIWAT, 10);
/* Enable buffer manager */
- if (sc->bge_asicrev != BGE_ASICREV_BCM5705 &&
- sc->bge_asicrev != BGE_ASICREV_BCM5750) {
+ if (!(BGE_IS_5705_PLUS(sc))) {
CSR_WRITE_4(sc, BGE_BMAN_MODE,
- BGE_BMANMODE_ENABLE|BGE_BMANMODE_LOMBUF_ATTN);
+ BGE_BMANMODE_ENABLE | BGE_BMANMODE_LOMBUF_ATTN);
/* Poll for buffer manager start indication */
for (i = 0; i < BGE_TIMEOUT; i++) {
+ DELAY(10);
if (CSR_READ_4(sc, BGE_BMAN_MODE) & BGE_BMANMODE_ENABLE)
break;
- DELAY(10);
}
if (i == BGE_TIMEOUT) {
device_printf(sc->bge_dev,
"buffer manager failed to start\n");
- return(ENXIO);
+ return (ENXIO);
}
}
@@ -1209,14 +1346,14 @@
/* Wait until queue initialization is complete */
for (i = 0; i < BGE_TIMEOUT; i++) {
+ DELAY(10);
if (CSR_READ_4(sc, BGE_FTQ_RESET) == 0)
break;
- DELAY(10);
}
if (i == BGE_TIMEOUT) {
device_printf(sc->bge_dev, "flow-through queue init failed\n");
- return(ENXIO);
+ return (ENXIO);
}
/* Initialize the standard RX ring control block */
@@ -1227,16 +1364,12 @@
BGE_ADDR_HI(sc->bge_ldata.bge_rx_std_ring_paddr);
bus_dmamap_sync(sc->bge_cdata.bge_rx_std_ring_tag,
sc->bge_cdata.bge_rx_std_ring_map, BUS_DMASYNC_PREREAD);
- if (sc->bge_asicrev == BGE_ASICREV_BCM5705 ||
- sc->bge_asicrev == BGE_ASICREV_BCM5750)
+ if (BGE_IS_5705_PLUS(sc))
rcb->bge_maxlen_flags = BGE_RCB_MAXLEN_FLAGS(512, 0);
else
rcb->bge_maxlen_flags =
BGE_RCB_MAXLEN_FLAGS(BGE_MAX_FRAMELEN, 0);
- if (sc->bge_extram)
- rcb->bge_nicaddr = BGE_EXT_STD_RX_RINGS;
- else
- rcb->bge_nicaddr = BGE_STD_RX_RINGS;
+ rcb->bge_nicaddr = BGE_STD_RX_RINGS;
CSR_WRITE_4(sc, BGE_RX_STD_RCB_HADDR_HI, rcb->bge_hostaddr.bge_addr_hi);
CSR_WRITE_4(sc, BGE_RX_STD_RCB_HADDR_LO, rcb->bge_hostaddr.bge_addr_lo);
@@ -1250,8 +1383,7 @@
* using this ring (i.e. once we set the MTU
* high enough to require it).
*/
- if (sc->bge_asicrev != BGE_ASICREV_BCM5705 &&
- sc->bge_asicrev != BGE_ASICREV_BCM5750) {
+ if (BGE_IS_JUMBO_CAPABLE(sc)) {
rcb = &sc->bge_ldata.bge_info.bge_jumbo_rx_rcb;
rcb->bge_hostaddr.bge_addr_lo =
@@ -1262,11 +1394,8 @@
sc->bge_cdata.bge_rx_jumbo_ring_map,
BUS_DMASYNC_PREREAD);
rcb->bge_maxlen_flags = BGE_RCB_MAXLEN_FLAGS(0,
- BGE_RCB_FLAG_USE_EXT_RX_BD|BGE_RCB_FLAG_RING_DISABLED);
- if (sc->bge_extram)
- rcb->bge_nicaddr = BGE_EXT_JUMBO_RX_RINGS;
- else
- rcb->bge_nicaddr = BGE_JUMBO_RX_RINGS;
+ BGE_RCB_FLAG_USE_EXT_RX_BD | BGE_RCB_FLAG_RING_DISABLED);
+ rcb->bge_nicaddr = BGE_JUMBO_RX_RINGS;
CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_HADDR_HI,
rcb->bge_hostaddr.bge_addr_hi);
CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_HADDR_LO,
@@ -1288,8 +1417,16 @@
* Set the BD ring replentish thresholds. The recommended
* values are 1/8th the number of descriptors allocated to
* each ring.
+ * XXX The 5754 requires a lower threshold, so it might be a
+ * requirement of all 575x family chips. The Linux driver sets
+ * the lower threshold for all 5705 family chips as well, but there
+ * are reports that it might not need to be so strict.
*/
- CSR_WRITE_4(sc, BGE_RBDI_STD_REPL_THRESH, BGE_STD_RX_RING_CNT/8);
+ if (BGE_IS_5705_PLUS(sc))
+ val = 8;
+ else
+ val = BGE_STD_RX_RING_CNT / 8;
+ CSR_WRITE_4(sc, BGE_RBDI_STD_REPL_THRESH, val);
CSR_WRITE_4(sc, BGE_RBDI_JUMBO_REPL_THRESH, BGE_JUMBO_RX_RING_CNT/8);
/*
@@ -1312,8 +1449,7 @@
RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_lo, taddr.bge_addr_lo);
RCB_WRITE_4(sc, vrcb, bge_nicaddr,
BGE_NIC_TXRING_ADDR(0, BGE_TX_RING_CNT));
- if (sc->bge_asicrev != BGE_ASICREV_BCM5705 &&
- sc->bge_asicrev != BGE_ASICREV_BCM5750)
+ if (!(BGE_IS_5705_PLUS(sc)))
RCB_WRITE_4(sc, vrcb, bge_maxlen_flags,
BGE_RCB_MAXLEN_FLAGS(BGE_TX_RING_CNT, 0));
@@ -1327,7 +1463,7 @@
BGE_RCB_FLAG_RING_DISABLED));
RCB_WRITE_4(sc, vrcb, bge_nicaddr, 0);
CSR_WRITE_4(sc, BGE_MBX_RX_CONS0_LO +
- (i * (sizeof(u_int64_t))), 0);
+ (i * (sizeof(uint64_t))), 0);
vrcb += sizeof(struct bge_rcb);
}
@@ -1352,9 +1488,9 @@
/* Set random backoff seed for TX */
CSR_WRITE_4(sc, BGE_TX_RANDOM_BACKOFF,
- IFP2ENADDR(sc->bge_ifp)[0] + IFP2ENADDR(sc->bge_ifp)[1] +
- IFP2ENADDR(sc->bge_ifp)[2] + IFP2ENADDR(sc->bge_ifp)[3] +
- IFP2ENADDR(sc->bge_ifp)[4] + IFP2ENADDR(sc->bge_ifp)[5] +
+ IF_LLADDR(sc->bge_ifp)[0] + IF_LLADDR(sc->bge_ifp)[1] +
+ IF_LLADDR(sc->bge_ifp)[2] + IF_LLADDR(sc->bge_ifp)[3] +
+ IF_LLADDR(sc->bge_ifp)[4] + IF_LLADDR(sc->bge_ifp)[5] +
BGE_TX_BACKOFF_SEED_MASK);
/* Set inter-packet gap */
@@ -1381,15 +1517,15 @@
/* Poll to make sure it's shut down. */
for (i = 0; i < BGE_TIMEOUT; i++) {
+ DELAY(10);
if (!(CSR_READ_4(sc, BGE_HCC_MODE) & BGE_HCCMODE_ENABLE))
break;
- DELAY(10);
}
if (i == BGE_TIMEOUT) {
device_printf(sc->bge_dev,
"host coalescing engine failed to idle\n");
- return(ENXIO);
+ return (ENXIO);
}
/* Set up host coalescing defaults */
@@ -1397,17 +1533,15 @@
CSR_WRITE_4(sc, BGE_HCC_TX_COAL_TICKS, sc->bge_tx_coal_ticks);
CSR_WRITE_4(sc, BGE_HCC_RX_MAX_COAL_BDS, sc->bge_rx_max_coal_bds);
CSR_WRITE_4(sc, BGE_HCC_TX_MAX_COAL_BDS, sc->bge_tx_max_coal_bds);
- if (sc->bge_asicrev != BGE_ASICREV_BCM5705 &&
- sc->bge_asicrev != BGE_ASICREV_BCM5750) {
+ if (!(BGE_IS_5705_PLUS(sc))) {
CSR_WRITE_4(sc, BGE_HCC_RX_COAL_TICKS_INT, 0);
CSR_WRITE_4(sc, BGE_HCC_TX_COAL_TICKS_INT, 0);
}
- CSR_WRITE_4(sc, BGE_HCC_RX_MAX_COAL_BDS_INT, 0);
- CSR_WRITE_4(sc, BGE_HCC_TX_MAX_COAL_BDS_INT, 0);
+ CSR_WRITE_4(sc, BGE_HCC_RX_MAX_COAL_BDS_INT, 1);
+ CSR_WRITE_4(sc, BGE_HCC_TX_MAX_COAL_BDS_INT, 1);
/* Set up address of statistics block */
- if (sc->bge_asicrev != BGE_ASICREV_BCM5705 &&
- sc->bge_asicrev != BGE_ASICREV_BCM5750) {
+ if (!(BGE_IS_5705_PLUS(sc))) {
CSR_WRITE_4(sc, BGE_HCC_STATS_ADDR_HI,
BGE_ADDR_HI(sc->bge_ldata.bge_stats_paddr));
CSR_WRITE_4(sc, BGE_HCC_STATS_ADDR_LO,
@@ -1430,46 +1564,51 @@
/* Turn on RX BD completion state machine and enable attentions */
CSR_WRITE_4(sc, BGE_RBDC_MODE,
- BGE_RBDCMODE_ENABLE|BGE_RBDCMODE_ATTN);
+ BGE_RBDCMODE_ENABLE | BGE_RBDCMODE_ATTN);
/* Turn on RX list placement state machine */
CSR_WRITE_4(sc, BGE_RXLP_MODE, BGE_RXLPMODE_ENABLE);
/* Turn on RX list selector state machine. */
- if (sc->bge_asicrev != BGE_ASICREV_BCM5705 &&
- sc->bge_asicrev != BGE_ASICREV_BCM5750)
+ if (!(BGE_IS_5705_PLUS(sc)))
CSR_WRITE_4(sc, BGE_RXLS_MODE, BGE_RXLSMODE_ENABLE);
/* Turn on DMA, clear stats */
- CSR_WRITE_4(sc, BGE_MAC_MODE, BGE_MACMODE_TXDMA_ENB|
- BGE_MACMODE_RXDMA_ENB|BGE_MACMODE_RX_STATS_CLEAR|
- BGE_MACMODE_TX_STATS_CLEAR|BGE_MACMODE_RX_STATS_ENB|
- BGE_MACMODE_TX_STATS_ENB|BGE_MACMODE_FRMHDR_DMA_ENB|
- (sc->bge_tbi ? BGE_PORTMODE_TBI : BGE_PORTMODE_MII));
+ CSR_WRITE_4(sc, BGE_MAC_MODE, BGE_MACMODE_TXDMA_ENB |
+ BGE_MACMODE_RXDMA_ENB | BGE_MACMODE_RX_STATS_CLEAR |
+ BGE_MACMODE_TX_STATS_CLEAR | BGE_MACMODE_RX_STATS_ENB |
+ BGE_MACMODE_TX_STATS_ENB | BGE_MACMODE_FRMHDR_DMA_ENB |
+ ((sc->bge_flags & BGE_FLAG_TBI) ?
+ BGE_PORTMODE_TBI : BGE_PORTMODE_MII));
/* Set misc. local control, enable interrupts on attentions */
CSR_WRITE_4(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_INTR_ONATTN);
#ifdef notdef
/* Assert GPIO pins for PHY reset */
- BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_MISCIO_OUT0|
- BGE_MLC_MISCIO_OUT1|BGE_MLC_MISCIO_OUT2);
- BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_MISCIO_OUTEN0|
- BGE_MLC_MISCIO_OUTEN1|BGE_MLC_MISCIO_OUTEN2);
+ BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_MISCIO_OUT0 |
+ BGE_MLC_MISCIO_OUT1 | BGE_MLC_MISCIO_OUT2);
+ BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_MISCIO_OUTEN0 |
+ BGE_MLC_MISCIO_OUTEN1 | BGE_MLC_MISCIO_OUTEN2);
#endif
/* Turn on DMA completion state machine */
- if (sc->bge_asicrev != BGE_ASICREV_BCM5705 &&
- sc->bge_asicrev != BGE_ASICREV_BCM5750)
+ if (!(BGE_IS_5705_PLUS(sc)))
CSR_WRITE_4(sc, BGE_DMAC_MODE, BGE_DMACMODE_ENABLE);
+ val = BGE_WDMAMODE_ENABLE | BGE_WDMAMODE_ALL_ATTNS;
+
+ /* Enable host coalescing bug fix. */
+ if (sc->bge_asicrev == BGE_ASICREV_BCM5755 ||
+ sc->bge_asicrev == BGE_ASICREV_BCM5787)
+ val |= 1 << 29;
+
/* Turn on write DMA state machine */
- CSR_WRITE_4(sc, BGE_WDMA_MODE,
- BGE_WDMAMODE_ENABLE|BGE_WDMAMODE_ALL_ATTNS);
+ CSR_WRITE_4(sc, BGE_WDMA_MODE, val);
/* Turn on read DMA state machine */
CSR_WRITE_4(sc, BGE_RDMA_MODE,
- BGE_RDMAMODE_ENABLE|BGE_RDMAMODE_ALL_ATTNS);
+ BGE_RDMAMODE_ENABLE | BGE_RDMAMODE_ALL_ATTNS);
/* Turn on RX data completion state machine */
CSR_WRITE_4(sc, BGE_RDC_MODE, BGE_RDCMODE_ENABLE);
@@ -1481,8 +1620,7 @@
CSR_WRITE_4(sc, BGE_RDBDI_MODE, BGE_RDBDIMODE_ENABLE);
/* Turn on Mbuf cluster free state machine */
- if (sc->bge_asicrev != BGE_ASICREV_BCM5705 &&
- sc->bge_asicrev != BGE_ASICREV_BCM5750)
+ if (!(BGE_IS_5705_PLUS(sc)))
CSR_WRITE_4(sc, BGE_MBCF_MODE, BGE_MBCFMODE_ENABLE);
/* Turn on send BD completion state machine */
@@ -1502,21 +1640,21 @@
CSR_WRITE_4(sc, BGE_SDI_STATS_ENABLE_MASK, 0x007FFFFF);
CSR_WRITE_4(sc, BGE_SDI_STATS_CTL,
- BGE_SDISTATSCTL_ENABLE|BGE_SDISTATSCTL_FASTER);
+ BGE_SDISTATSCTL_ENABLE | BGE_SDISTATSCTL_FASTER);
/* ack/clear link change events */
- CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED|
- BGE_MACSTAT_CFG_CHANGED|BGE_MACSTAT_MI_COMPLETE|
+ CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED |
+ BGE_MACSTAT_CFG_CHANGED | BGE_MACSTAT_MI_COMPLETE |
BGE_MACSTAT_LINK_CHANGED);
CSR_WRITE_4(sc, BGE_MI_STS, 0);
/* Enable PHY auto polling (for MII/GMII only) */
- if (sc->bge_tbi) {
+ if (sc->bge_flags & BGE_FLAG_TBI) {
CSR_WRITE_4(sc, BGE_MI_STS, BGE_MISTS_LINK);
} else {
- BGE_SETBIT(sc, BGE_MI_MODE, BGE_MIMODE_AUTOPOLL|10<<16);
+ BGE_SETBIT(sc, BGE_MI_MODE, BGE_MIMODE_AUTOPOLL | (10 << 16));
if (sc->bge_asicrev == BGE_ASICREV_BCM5700 &&
- sc->bge_chipid != BGE_CHIPID_BCM5700_B1)
+ sc->bge_chipid != BGE_CHIPID_BCM5700_B2)
CSR_WRITE_4(sc, BGE_MAC_EVT_ENB,
BGE_EVTENB_MI_INTERRUPT);
}
@@ -1528,88 +1666,126 @@
* It's not necessary on newer BCM chips - perhaps enabling link
* state change attentions implies clearing pending attention.
*/
- CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED|
- BGE_MACSTAT_CFG_CHANGED|BGE_MACSTAT_MI_COMPLETE|
+ CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED |
+ BGE_MACSTAT_CFG_CHANGED | BGE_MACSTAT_MI_COMPLETE |
BGE_MACSTAT_LINK_CHANGED);
/* Enable link state change attentions. */
BGE_SETBIT(sc, BGE_MAC_EVT_ENB, BGE_EVTENB_LINK_CHANGED);
- return(0);
+ return (0);
+}
+
+const struct bge_revision *
+bge_lookup_rev(uint32_t chipid)
+{
+ const struct bge_revision *br;
+
+ for (br = bge_revisions; br->br_name != NULL; br++) {
+ if (br->br_chipid == chipid)
+ return (br);
+ }
+
+ for (br = bge_majorrevs; br->br_name != NULL; br++) {
+ if (br->br_chipid == BGE_ASICREV(chipid))
+ return (br);
+ }
+
+ return (NULL);
+}
+
+const struct bge_vendor *
+bge_lookup_vendor(uint16_t vid)
+{
+ const struct bge_vendor *v;
+
+ for (v = bge_vendors; v->v_name != NULL; v++)
+ if (v->v_id == vid)
+ return (v);
+
+ panic("%s: unknown vendor %d", __func__, vid);
+ return (NULL);
}
/*
* Probe for a Broadcom chip. Check the PCI vendor and device IDs
- * against our list and return its name if we find a match. Note
- * that since the Broadcom controller contains VPD support, we
- * can get the device name string from the controller itself instead
- * of the compiled-in string. This is a little slow, but it guarantees
- * we'll always announce the right product name.
+ * against our list and return its name if we find a match.
+ *
+ * Note that since the Broadcom controller contains VPD support, we
+ * try to get the device name string from the controller itself instead
+ * of the compiled-in string. It guarantees we'll always announce the
+ * right product name. We fall back to the compiled-in string when
+ * VPD is unavailable or corrupt.
*/
static int
-bge_probe(dev)
- device_t dev;
+bge_probe(device_t dev)
{
- struct bge_type *t;
- struct bge_softc *sc;
- char *descbuf;
-
- t = bge_devs;
+ struct bge_type *t = bge_devs;
+ struct bge_softc *sc = device_get_softc(dev);
+ uint16_t vid, did;
- sc = device_get_softc(dev);
- bzero(sc, sizeof(struct bge_softc));
sc->bge_dev = dev;
-
- while(t->bge_name != NULL) {
- if ((pci_get_vendor(dev) == t->bge_vid) &&
- (pci_get_device(dev) == t->bge_did)) {
-#ifdef notdef
- bge_vpd_read(sc);
- device_set_desc(dev, sc->bge_vpd_prodname);
+ vid = pci_get_vendor(dev);
+ did = pci_get_device(dev);
+ while(t->bge_vid != 0) {
+ if ((vid == t->bge_vid) && (did == t->bge_did)) {
+ char model[64], buf[96];
+ const struct bge_revision *br;
+ const struct bge_vendor *v;
+ uint32_t id;
+
+ id = pci_read_config(dev, BGE_PCI_MISC_CTL, 4) &
+ BGE_PCIMISCCTL_ASICREV;
+ br = bge_lookup_rev(id);
+ v = bge_lookup_vendor(vid);
+ {
+#if __FreeBSD_version > 700024
+ const char *pname;
+
+ if (pci_get_vpd_ident(dev, &pname) == 0)
+ snprintf(model, 64, "%s", pname);
+ else
#endif
- descbuf = malloc(BGE_DEVDESC_MAX, M_TEMP, M_NOWAIT);
- if (descbuf == NULL)
- return(ENOMEM);
- snprintf(descbuf, BGE_DEVDESC_MAX,
- "%s, ASIC rev. %#04x", t->bge_name,
- pci_read_config(dev, BGE_PCI_MISC_CTL, 4) >> 16);
- device_set_desc_copy(dev, descbuf);
+ snprintf(model, 64, "%s %s",
+ v->v_name,
+ br != NULL ? br->br_name :
+ "NetXtreme Ethernet Controller");
+ }
+ snprintf(buf, 96, "%s, %sASIC rev. %#04x", model,
+ br != NULL ? "" : "unknown ", id >> 16);
+ device_set_desc_copy(dev, buf);
if (pci_get_subvendor(dev) == DELL_VENDORID)
- sc->bge_no_3_led = 1;
- free(descbuf, M_TEMP);
- return(0);
+ sc->bge_flags |= BGE_FLAG_NO_3LED;
+ if (did == BCOM_DEVICEID_BCM5755M)
+ sc->bge_flags |= BGE_FLAG_ADJUST_TRIM;
+ return (0);
}
t++;
}
- return(ENXIO);
+ return (ENXIO);
}
static void
-bge_dma_free(sc)
- struct bge_softc *sc;
+bge_dma_free(struct bge_softc *sc)
{
int i;
-
- /* Destroy DMA maps for RX buffers */
-
+ /* Destroy DMA maps for RX buffers. */
for (i = 0; i < BGE_STD_RX_RING_CNT; i++) {
if (sc->bge_cdata.bge_rx_std_dmamap[i])
bus_dmamap_destroy(sc->bge_cdata.bge_mtag,
sc->bge_cdata.bge_rx_std_dmamap[i]);
}
- /* Destroy DMA maps for jumbo RX buffers */
-
+ /* Destroy DMA maps for jumbo RX buffers. */
for (i = 0; i < BGE_JUMBO_RX_RING_CNT; i++) {
if (sc->bge_cdata.bge_rx_jumbo_dmamap[i])
bus_dmamap_destroy(sc->bge_cdata.bge_mtag_jumbo,
sc->bge_cdata.bge_rx_jumbo_dmamap[i]);
}
- /* Destroy DMA maps for TX buffers */
-
+ /* Destroy DMA maps for TX buffers. */
for (i = 0; i < BGE_TX_RING_CNT; i++) {
if (sc->bge_cdata.bge_tx_dmamap[i])
bus_dmamap_destroy(sc->bge_cdata.bge_mtag,
@@ -1620,8 +1796,7 @@
bus_dma_tag_destroy(sc->bge_cdata.bge_mtag);
- /* Destroy standard RX ring */
-
+ /* Destroy standard RX ring. */
if (sc->bge_cdata.bge_rx_std_ring_map)
bus_dmamap_unload(sc->bge_cdata.bge_rx_std_ring_tag,
sc->bge_cdata.bge_rx_std_ring_map);
@@ -1633,8 +1808,7 @@
if (sc->bge_cdata.bge_rx_std_ring_tag)
bus_dma_tag_destroy(sc->bge_cdata.bge_rx_std_ring_tag);
- /* Destroy jumbo RX ring */
-
+ /* Destroy jumbo RX ring. */
if (sc->bge_cdata.bge_rx_jumbo_ring_map)
bus_dmamap_unload(sc->bge_cdata.bge_rx_jumbo_ring_tag,
sc->bge_cdata.bge_rx_jumbo_ring_map);
@@ -1648,8 +1822,7 @@
if (sc->bge_cdata.bge_rx_jumbo_ring_tag)
bus_dma_tag_destroy(sc->bge_cdata.bge_rx_jumbo_ring_tag);
- /* Destroy RX return ring */
-
+ /* Destroy RX return ring. */
if (sc->bge_cdata.bge_rx_return_ring_map)
bus_dmamap_unload(sc->bge_cdata.bge_rx_return_ring_tag,
sc->bge_cdata.bge_rx_return_ring_map);
@@ -1663,8 +1836,7 @@
if (sc->bge_cdata.bge_rx_return_ring_tag)
bus_dma_tag_destroy(sc->bge_cdata.bge_rx_return_ring_tag);
- /* Destroy TX ring */
-
+ /* Destroy TX ring. */
if (sc->bge_cdata.bge_tx_ring_map)
bus_dmamap_unload(sc->bge_cdata.bge_tx_ring_tag,
sc->bge_cdata.bge_tx_ring_map);
@@ -1677,8 +1849,7 @@
if (sc->bge_cdata.bge_tx_ring_tag)
bus_dma_tag_destroy(sc->bge_cdata.bge_tx_ring_tag);
- /* Destroy status block */
-
+ /* Destroy status block. */
if (sc->bge_cdata.bge_status_map)
bus_dmamap_unload(sc->bge_cdata.bge_status_tag,
sc->bge_cdata.bge_status_map);
@@ -1691,8 +1862,7 @@
if (sc->bge_cdata.bge_status_tag)
bus_dma_tag_destroy(sc->bge_cdata.bge_status_tag);
- /* Destroy statistics block */
-
+ /* Destroy statistics block. */
if (sc->bge_cdata.bge_stats_map)
bus_dmamap_unload(sc->bge_cdata.bge_stats_tag,
sc->bge_cdata.bge_stats_map);
@@ -1705,34 +1875,30 @@
if (sc->bge_cdata.bge_stats_tag)
bus_dma_tag_destroy(sc->bge_cdata.bge_stats_tag);
- /* Destroy the parent tag */
-
+ /* Destroy the parent tag. */
if (sc->bge_cdata.bge_parent_tag)
bus_dma_tag_destroy(sc->bge_cdata.bge_parent_tag);
-
- return;
}
static int
-bge_dma_alloc(dev)
- device_t dev;
+bge_dma_alloc(device_t dev)
{
+ struct bge_dmamap_arg ctx;
struct bge_softc *sc;
int i, error;
- struct bge_dmamap_arg ctx;
sc = device_get_softc(dev);
/*
* Allocate the parent bus DMA tag appropriate for PCI.
*/
- error = bus_dma_tag_create(NULL, /* parent */
- PAGE_SIZE, 0, /* alignment, boundary */
+ error = bus_dma_tag_create(bus_get_dma_tag(sc->bge_dev), /* parent */
+ 1, 0, /* alignment, boundary */
BUS_SPACE_MAXADDR, /* lowaddr */
BUS_SPACE_MAXADDR, /* highaddr */
NULL, NULL, /* filter, filterarg */
MAXBSIZE, BGE_NSEG_NEW, /* maxsize, nsegments */
- BUS_SPACE_MAXSIZE_32BIT,/* maxsegsize */
+ BUS_SPACE_MAXSIZE_32BIT, /* maxsegsize */
0, /* flags */
NULL, NULL, /* lockfunc, lockarg */
&sc->bge_cdata.bge_parent_tag);
@@ -1756,32 +1922,29 @@
return (ENOMEM);
}
- /* Create DMA maps for RX buffers */
-
+ /* Create DMA maps for RX buffers. */
for (i = 0; i < BGE_STD_RX_RING_CNT; i++) {
error = bus_dmamap_create(sc->bge_cdata.bge_mtag, 0,
&sc->bge_cdata.bge_rx_std_dmamap[i]);
if (error) {
device_printf(sc->bge_dev,
"can't create DMA map for RX\n");
- return(ENOMEM);
+ return (ENOMEM);
}
}
- /* Create DMA maps for TX buffers */
-
+ /* Create DMA maps for TX buffers. */
for (i = 0; i < BGE_TX_RING_CNT; i++) {
error = bus_dmamap_create(sc->bge_cdata.bge_mtag, 0,
&sc->bge_cdata.bge_tx_dmamap[i]);
if (error) {
device_printf(sc->bge_dev,
"can't create DMA map for RX\n");
- return(ENOMEM);
+ return (ENOMEM);
}
}
- /* Create tag for standard RX ring */
-
+ /* Create tag for standard RX ring. */
error = bus_dma_tag_create(sc->bge_cdata.bge_parent_tag,
PAGE_SIZE, 0, BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL,
NULL, BGE_STD_RX_RING_SZ, 1, BGE_STD_RX_RING_SZ, 0,
@@ -1792,8 +1955,7 @@
return (ENOMEM);
}
- /* Allocate DMA'able memory for standard RX ring */
-
+ /* Allocate DMA'able memory for standard RX ring. */
error = bus_dmamem_alloc(sc->bge_cdata.bge_rx_std_ring_tag,
(void **)&sc->bge_ldata.bge_rx_std_ring, BUS_DMA_NOWAIT,
&sc->bge_cdata.bge_rx_std_ring_map);
@@ -1802,8 +1964,7 @@
bzero((char *)sc->bge_ldata.bge_rx_std_ring, BGE_STD_RX_RING_SZ);
- /* Load the address of the standard RX ring */
-
+ /* Load the address of the standard RX ring. */
ctx.bge_maxsegs = 1;
ctx.sc = sc;
@@ -1816,38 +1977,19 @@
sc->bge_ldata.bge_rx_std_ring_paddr = ctx.bge_busaddr;
- if (sc->bge_asicrev != BGE_ASICREV_BCM5705 &&
- sc->bge_asicrev != BGE_ASICREV_BCM5750) {
-
- /*
- * Create tag for jumbo mbufs.
- * This is really a bit of a kludge. We allocate a special
- * jumbo buffer pool which (thanks to the way our DMA
- * memory allocation works) will consist of contiguous
- * pages. This means that even though a jumbo buffer might
- * be larger than a page size, we don't really need to
- * map it into more than one DMA segment. However, the
- * default mbuf tag will result in multi-segment mappings,
- * so we have to create a special jumbo mbuf tag that
- * lets us get away with mapping the jumbo buffers as
- * a single segment. I think eventually the driver should
- * be changed so that it uses ordinary mbufs and cluster
- * buffers, i.e. jumbo frames can span multiple DMA
- * descriptors. But that's a project for another day.
- */
-
+ /* Create tags for jumbo mbufs. */
+ if (BGE_IS_JUMBO_CAPABLE(sc)) {
error = bus_dma_tag_create(sc->bge_cdata.bge_parent_tag,
1, 0, BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL,
NULL, MJUM9BYTES, BGE_NSEG_JUMBO, PAGE_SIZE,
0, NULL, NULL, &sc->bge_cdata.bge_mtag_jumbo);
-
if (error) {
device_printf(sc->bge_dev,
- "could not allocate dma tag\n");
+ "could not allocate jumbo dma tag\n");
return (ENOMEM);
}
- /* Create tag for jumbo RX ring */
+ /* Create tag for jumbo RX ring. */
error = bus_dma_tag_create(sc->bge_cdata.bge_parent_tag,
PAGE_SIZE, 0, BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL,
NULL, BGE_JUMBO_RX_RING_SZ, 1, BGE_JUMBO_RX_RING_SZ, 0,
@@ -1855,11 +1997,11 @@
if (error) {
device_printf(sc->bge_dev,
- "could not allocate dma tag\n");
+ "could not allocate jumbo ring dma tag\n");
return (ENOMEM);
}
- /* Allocate DMA'able memory for jumbo RX ring */
+ /* Allocate DMA'able memory for jumbo RX ring. */
error = bus_dmamem_alloc(sc->bge_cdata.bge_rx_jumbo_ring_tag,
(void **)&sc->bge_ldata.bge_rx_jumbo_ring,
BUS_DMA_NOWAIT | BUS_DMA_ZERO,
@@ -1867,7 +2009,7 @@
if (error)
return (ENOMEM);
- /* Load the address of the jumbo RX ring */
+ /* Load the address of the jumbo RX ring. */
ctx.bge_maxsegs = 1;
ctx.sc = sc;
@@ -1881,22 +2023,20 @@
sc->bge_ldata.bge_rx_jumbo_ring_paddr = ctx.bge_busaddr;
- /* Create DMA maps for jumbo RX buffers */
-
+ /* Create DMA maps for jumbo RX buffers. */
for (i = 0; i < BGE_JUMBO_RX_RING_CNT; i++) {
error = bus_dmamap_create(sc->bge_cdata.bge_mtag_jumbo,
0, &sc->bge_cdata.bge_rx_jumbo_dmamap[i]);
if (error) {
device_printf(sc->bge_dev,
- "can't create DMA map for RX\n");
- return(ENOMEM);
+ "can't create DMA map for jumbo RX\n");
+ return (ENOMEM);
}
}
}
- /* Create tag for RX return ring */
-
+ /* Create tag for RX return ring. */
error = bus_dma_tag_create(sc->bge_cdata.bge_parent_tag,
PAGE_SIZE, 0, BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL,
NULL, BGE_RX_RTN_RING_SZ(sc), 1, BGE_RX_RTN_RING_SZ(sc), 0,
@@ -1907,8 +2047,7 @@
return (ENOMEM);
}
- /* Allocate DMA'able memory for RX return ring */
-
+ /* Allocate DMA'able memory for RX return ring. */
error = bus_dmamem_alloc(sc->bge_cdata.bge_rx_return_ring_tag,
(void **)&sc->bge_ldata.bge_rx_return_ring, BUS_DMA_NOWAIT,
&sc->bge_cdata.bge_rx_return_ring_map);
@@ -1918,8 +2057,7 @@
bzero((char *)sc->bge_ldata.bge_rx_return_ring,
BGE_RX_RTN_RING_SZ(sc));
- /* Load the address of the RX return ring */
-
+ /* Load the address of the RX return ring. */
ctx.bge_maxsegs = 1;
ctx.sc = sc;
@@ -1933,8 +2071,7 @@
sc->bge_ldata.bge_rx_return_ring_paddr = ctx.bge_busaddr;
- /* Create tag for TX ring */
-
+ /* Create tag for TX ring. */
error = bus_dma_tag_create(sc->bge_cdata.bge_parent_tag,
PAGE_SIZE, 0, BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL,
NULL, BGE_TX_RING_SZ, 1, BGE_TX_RING_SZ, 0, NULL, NULL,
@@ -1945,8 +2082,7 @@
return (ENOMEM);
}
- /* Allocate DMA'able memory for TX ring */
-
+ /* Allocate DMA'able memory for TX ring. */
error = bus_dmamem_alloc(sc->bge_cdata.bge_tx_ring_tag,
(void **)&sc->bge_ldata.bge_tx_ring, BUS_DMA_NOWAIT,
&sc->bge_cdata.bge_tx_ring_map);
@@ -1955,8 +2091,7 @@
bzero((char *)sc->bge_ldata.bge_tx_ring, BGE_TX_RING_SZ);
- /* Load the address of the TX ring */
-
+ /* Load the address of the TX ring. */
ctx.bge_maxsegs = 1;
ctx.sc = sc;
@@ -1969,8 +2104,7 @@
sc->bge_ldata.bge_tx_ring_paddr = ctx.bge_busaddr;
- /* Create tag for status block */
-
+ /* Create tag for status block. */
error = bus_dma_tag_create(sc->bge_cdata.bge_parent_tag,
PAGE_SIZE, 0, BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL,
NULL, BGE_STATUS_BLK_SZ, 1, BGE_STATUS_BLK_SZ, 0,
@@ -1981,8 +2115,7 @@
return (ENOMEM);
}
- /* Allocate DMA'able memory for status block */
-
+ /* Allocate DMA'able memory for status block. */
error = bus_dmamem_alloc(sc->bge_cdata.bge_status_tag,
(void **)&sc->bge_ldata.bge_status_block, BUS_DMA_NOWAIT,
&sc->bge_cdata.bge_status_map);
@@ -1991,8 +2124,7 @@
bzero((char *)sc->bge_ldata.bge_status_block, BGE_STATUS_BLK_SZ);
- /* Load the address of the status block */
-
+ /* Load the address of the status block. */
ctx.sc = sc;
ctx.bge_maxsegs = 1;
@@ -2005,8 +2137,7 @@
sc->bge_ldata.bge_status_block_paddr = ctx.bge_busaddr;
- /* Create tag for statistics block */
-
+ /* Create tag for statistics block. */
error = bus_dma_tag_create(sc->bge_cdata.bge_parent_tag,
PAGE_SIZE, 0, BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL,
NULL, BGE_STATS_SZ, 1, BGE_STATS_SZ, 0, NULL, NULL,
@@ -2017,8 +2148,7 @@
return (ENOMEM);
}
- /* Allocate DMA'able memory for statistics block */
-
+ /* Allocate DMA'able memory for statistics block. */
error = bus_dmamem_alloc(sc->bge_cdata.bge_stats_tag,
(void **)&sc->bge_ldata.bge_stats, BUS_DMA_NOWAIT,
&sc->bge_cdata.bge_stats_map);
@@ -2027,8 +2157,7 @@
bzero((char *)sc->bge_ldata.bge_stats, BGE_STATS_SZ);
- /* Load the address of the statstics block */
-
+ /* Load the address of the statstics block. */
ctx.sc = sc;
ctx.bge_maxsegs = 1;
@@ -2041,19 +2170,69 @@
sc->bge_ldata.bge_stats_paddr = ctx.bge_busaddr;
- return(0);
+ return (0);
}
+#if __FreeBSD_version > 602105
+/*
+ * Return true if this device has more than one port.
+ */
static int
-bge_attach(dev)
- device_t dev;
+bge_has_multiple_ports(struct bge_softc *sc)
+{
+ device_t dev = sc->bge_dev;
+ u_int b, d, f, fscan, s;
+
+ d = pci_get_domain(dev);
+ b = pci_get_bus(dev);
+ s = pci_get_slot(dev);
+ f = pci_get_function(dev);
+ for (fscan = 0; fscan <= PCI_FUNCMAX; fscan++)
+ if (fscan != f && pci_find_dbsf(d, b, s, fscan) != NULL)
+ return (1);
+ return (0);
+}
+
+/*
+ * Return true if MSI can be used with this device.
+ */
+static int
+bge_can_use_msi(struct bge_softc *sc)
+{
+ int can_use_msi = 0;
+
+ switch (sc->bge_asicrev) {
+ case BGE_ASICREV_BCM5714:
+ /*
+ * Apparently, MSI doesn't work when this chip is configured
+ * in single-port mode.
+ */
+ if (bge_has_multiple_ports(sc))
+ can_use_msi = 1;
+ break;
+ case BGE_ASICREV_BCM5750:
+ if (sc->bge_chiprev != BGE_CHIPREV_5750_AX &&
+ sc->bge_chiprev != BGE_CHIPREV_5750_BX)
+ can_use_msi = 1;
+ break;
+ case BGE_ASICREV_BCM5752:
+ case BGE_ASICREV_BCM5780:
+ can_use_msi = 1;
+ break;
+ }
+ return (can_use_msi);
+}
+#endif
+
+static int
+bge_attach(device_t dev)
{
struct ifnet *ifp;
struct bge_softc *sc;
- u_int32_t hwcfg = 0;
- u_int32_t mac_tmp = 0;
- u_char eaddr[6];
- int error = 0, rid;
+ uint32_t hwcfg = 0;
+ uint32_t mac_tmp = 0;
+ u_char eaddr[ETHER_ADDR_LEN];
+ int error, reg, rid, trys;
sc = device_get_softc(dev);
sc->bge_dev = dev;
@@ -2065,7 +2244,7 @@
rid = BGE_PCI_BAR0;
sc->bge_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid,
- RF_ACTIVE|PCI_RF_DENSE);
+ RF_ACTIVE | PCI_RF_DENSE);
if (sc->bge_res == NULL) {
device_printf (sc->bge_dev, "couldn't map memory\n");
@@ -2076,8 +2255,115 @@
sc->bge_btag = rman_get_bustag(sc->bge_res);
sc->bge_bhandle = rman_get_bushandle(sc->bge_res);
- /* Allocate interrupt */
+ /* Save ASIC rev. */
+
+ sc->bge_chipid =
+ pci_read_config(dev, BGE_PCI_MISC_CTL, 4) &
+ BGE_PCIMISCCTL_ASICREV;
+ sc->bge_asicrev = BGE_ASICREV(sc->bge_chipid);
+ sc->bge_chiprev = BGE_CHIPREV(sc->bge_chipid);
+
+ if (bge_has_eeprom(sc))
+ sc->bge_flags |= BGE_FLAG_EEPROM;
+
+ /* Save chipset family. */
+ switch (sc->bge_asicrev) {
+ case BGE_ASICREV_BCM5700:
+ case BGE_ASICREV_BCM5701:
+ case BGE_ASICREV_BCM5703:
+ case BGE_ASICREV_BCM5704:
+ sc->bge_flags |= BGE_FLAG_5700_FAMILY | BGE_FLAG_JUMBO;
+ break;
+ case BGE_ASICREV_BCM5714_A0:
+ case BGE_ASICREV_BCM5780:
+ case BGE_ASICREV_BCM5714:
+ sc->bge_flags |= BGE_FLAG_5714_FAMILY /* | BGE_FLAG_JUMBO */;
+ /* FALLTHRU */
+ case BGE_ASICREV_BCM5750:
+ case BGE_ASICREV_BCM5752:
+ case BGE_ASICREV_BCM5755:
+ case BGE_ASICREV_BCM5787:
+ sc->bge_flags |= BGE_FLAG_575X_PLUS;
+ /* FALLTHRU */
+ case BGE_ASICREV_BCM5705:
+ sc->bge_flags |= BGE_FLAG_5705_PLUS;
+ break;
+ }
+
+ /* Set various bug flags. */
+ if (sc->bge_chipid == BGE_CHIPID_BCM5701_A0 ||
+ sc->bge_chipid == BGE_CHIPID_BCM5701_B0)
+ sc->bge_flags |= BGE_FLAG_CRC_BUG;
+ if (sc->bge_chiprev == BGE_CHIPREV_5703_AX ||
+ sc->bge_chiprev == BGE_CHIPREV_5704_AX)
+ sc->bge_flags |= BGE_FLAG_ADC_BUG;
+ if (sc->bge_chipid == BGE_CHIPID_BCM5704_A0)
+ sc->bge_flags |= BGE_FLAG_5704_A0_BUG;
+ if (BGE_IS_5705_PLUS(sc) &&
+ !(sc->bge_flags & BGE_FLAG_ADJUST_TRIM)) {
+ if (sc->bge_asicrev == BGE_ASICREV_BCM5755 ||
+ sc->bge_asicrev == BGE_ASICREV_BCM5787)
+ sc->bge_flags |= BGE_FLAG_JITTER_BUG;
+ else
+ sc->bge_flags |= BGE_FLAG_BER_BUG;
+ }
+
+ /*
+ * Check if this is a PCI-X or PCI Express device.
+ */
+#if __FreeBSD_version > 602101
+ if (pci_find_extcap(dev, PCIY_EXPRESS, ®) == 0) {
+ /*
+ * Found a PCI Express capabilities register, this
+ * must be a PCI Express device.
+ */
+ if (reg != 0)
+ sc->bge_flags |= BGE_FLAG_PCIE;
+ } else if (pci_find_extcap(dev, PCIY_PCIX, ®) == 0) {
+ if (reg != 0)
+ sc->bge_flags |= BGE_FLAG_PCIX;
+ }
+
+#else
+ if (BGE_IS_5705_PLUS(sc)) {
+ reg = pci_read_config(dev, BGE_PCIE_CAPID_REG, 4);
+ if ((reg & 0xFF) == BGE_PCIE_CAPID)
+ sc->bge_flags |= BGE_FLAG_PCIE;
+ } else {
+ /*
+ * Check if the device is in PCI-X Mode.
+ * (This bit is not valid on PCI Express controllers.)
+ */
+ if ((pci_read_config(sc->bge_dev, BGE_PCI_PCISTATE, 4) &
+ BGE_PCISTATE_PCI_BUSMODE) == 0)
+ sc->bge_flags |= BGE_FLAG_PCIX;
+ }
+#endif
+
+#if __FreeBSD_version > 602105
+ {
+ int msicount;
+
+ /*
+ * Allocate the interrupt, using MSI if possible. These devices
+ * support 8 MSI messages, but only the first one is used in
+ * normal operation.
+ */
+ if (bge_can_use_msi(sc)) {
+ msicount = pci_msi_count(dev);
+ if (msicount > 1)
+ msicount = 1;
+ } else
+ msicount = 0;
+ if (msicount == 1 && pci_alloc_msi(dev, &msicount) == 0) {
+ rid = 1;
+ sc->bge_flags |= BGE_FLAG_MSI;
+ } else
+ rid = 0;
+ }
+#else
rid = 0;
+#endif
sc->bge_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
RF_SHAREABLE | RF_ACTIVE);
@@ -2090,70 +2376,70 @@
BGE_LOCK_INIT(sc, device_get_nameunit(dev));
- /* Save ASIC rev. */
-
- sc->bge_chipid =
- pci_read_config(dev, BGE_PCI_MISC_CTL, 4) &
- BGE_PCIMISCCTL_ASICREV;
- sc->bge_asicrev = BGE_ASICREV(sc->bge_chipid);
- sc->bge_chiprev = BGE_CHIPREV(sc->bge_chipid);
-
- /*
- * Treat the 5714 and the 5752 like the 5750 until we have more info
- * on this chip.
- */
- if (sc->bge_asicrev == BGE_ASICREV_BCM5714 ||
- sc->bge_asicrev == BGE_ASICREV_BCM5752)
- sc->bge_asicrev = BGE_ASICREV_BCM5750;
-
- /*
- * XXX: Broadcom Linux driver. Not in specs or eratta.
- * PCI-Express?
- */
- if (sc->bge_asicrev == BGE_ASICREV_BCM5750) {
- u_int32_t v;
+ /* Try to reset the chip. */
+ if (bge_reset(sc)) {
+ device_printf(sc->bge_dev, "chip reset failed\n");
+ error = ENXIO;
+ goto fail;
+ }
- v = pci_read_config(dev, BGE_PCI_MSI_CAPID, 4);
- if (((v >> 8) & 0xff) == BGE_PCIE_CAPID_REG) {
- v = pci_read_config(dev, BGE_PCIE_CAPID_REG, 4);
- if ((v & 0xff) == BGE_PCIE_CAPID)
- sc->bge_pcie = 1;
+ sc->bge_asf_mode = 0;
+ if (bge_allow_asf && (bge_readmem_ind(sc, BGE_SOFTWARE_GENCOMM_SIG)
+ == BGE_MAGIC_NUMBER)) {
+ if (bge_readmem_ind(sc, BGE_SOFTWARE_GENCOMM_NICCFG)
+ & BGE_HWCFG_ASF) {
+ sc->bge_asf_mode |= ASF_ENABLE;
+ sc->bge_asf_mode |= ASF_STACKUP;
+ if (sc->bge_asicrev == BGE_ASICREV_BCM5750) {
+ sc->bge_asf_mode |= ASF_NEW_HANDSHAKE;
+ }
}
}
- /* Try to reset the chip. */
- bge_reset(sc);
+ /* Try to reset the chip again the nice way. */
+ bge_stop_fw(sc);
+ bge_sig_pre_reset(sc, BGE_RESET_STOP);
+ if (bge_reset(sc)) {
+ device_printf(sc->bge_dev, "chip reset failed\n");
+ error = ENXIO;
+ goto fail;
+ }
+
+ bge_sig_legacy(sc, BGE_RESET_STOP);
+ bge_sig_post_reset(sc, BGE_RESET_STOP);
if (bge_chipinit(sc)) {
device_printf(sc->bge_dev, "chip initialization failed\n");
- bge_release_resources(sc);
error = ENXIO;
goto fail;
}
- /*
- * Get station address from the EEPROM.
- */
- mac_tmp = bge_readmem_ind(sc, 0x0c14);
- if ((mac_tmp >> 16) == 0x484b) {
- eaddr[0] = (u_char)(mac_tmp >> 8);
- eaddr[1] = (u_char)mac_tmp;
- mac_tmp = bge_readmem_ind(sc, 0x0c18);
- eaddr[2] = (u_char)(mac_tmp >> 24);
- eaddr[3] = (u_char)(mac_tmp >> 16);
- eaddr[4] = (u_char)(mac_tmp >> 8);
- eaddr[5] = (u_char)mac_tmp;
- } else if (bge_read_eeprom(sc, eaddr,
- BGE_EE_MAC_OFFSET + 2, ETHER_ADDR_LEN)) {
- device_printf(sc->bge_dev, "failed to read station address\n");
- bge_release_resources(sc);
- error = ENXIO;
- goto fail;
+#ifdef __sparc64__
+ if ((sc->bge_flags & BGE_FLAG_EEPROM) == 0)
+ OF_getetheraddr(dev, eaddr);
+ else
+#endif
+ {
+ mac_tmp = bge_readmem_ind(sc, 0x0C14);
+ if ((mac_tmp >> 16) == 0x484B) {
+ eaddr[0] = (u_char)(mac_tmp >> 8);
+ eaddr[1] = (u_char)mac_tmp;
+ mac_tmp = bge_readmem_ind(sc, 0x0C18);
+ eaddr[2] = (u_char)(mac_tmp >> 24);
+ eaddr[3] = (u_char)(mac_tmp >> 16);
+ eaddr[4] = (u_char)(mac_tmp >> 8);
+ eaddr[5] = (u_char)mac_tmp;
+ } else if (bge_read_eeprom(sc, eaddr,
+ BGE_EE_MAC_OFFSET + 2, ETHER_ADDR_LEN)) {
+ device_printf(sc->bge_dev,
+ "failed to read station address\n");
+ error = ENXIO;
+ goto fail;
+ }
}
/* 5705 limits RX return ring to 512 entries. */
- if (sc->bge_asicrev == BGE_ASICREV_BCM5705 ||
- sc->bge_asicrev == BGE_ASICREV_BCM5750)
+ if (BGE_IS_5705_PLUS(sc))
sc->bge_return_ring_cnt = BGE_RETURN_RING_CNT_5705;
else
sc->bge_return_ring_cnt = BGE_RETURN_RING_CNT;
@@ -2161,7 +2447,6 @@
if (bge_dma_alloc(dev)) {
device_printf(sc->bge_dev,
"failed to allocate DMA resources\n");
- bge_release_resources(sc);
error = ENXIO;
goto fail;
}
@@ -2170,14 +2455,13 @@
sc->bge_stat_ticks = BGE_TICKS_PER_SEC;
sc->bge_rx_coal_ticks = 150;
sc->bge_tx_coal_ticks = 150;
- sc->bge_rx_max_coal_bds = 64;
- sc->bge_tx_max_coal_bds = 128;
+ sc->bge_rx_max_coal_bds = 10;
+ sc->bge_tx_max_coal_bds = 10;
/* Set up ifnet structure */
ifp = sc->bge_ifp = if_alloc(IFT_ETHER);
if (ifp == NULL) {
device_printf(sc->bge_dev, "failed to if_alloc()\n");
- bge_release_resources(sc);
error = ENXIO;
goto fail;
}
@@ -2186,7 +2470,6 @@
ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
ifp->if_ioctl = bge_ioctl;
ifp->if_start = bge_start;
- ifp->if_watchdog = bge_watchdog;
ifp->if_init = bge_init;
ifp->if_mtu = ETHERMTU;
ifp->if_snd.ifq_drv_maxlen = BGE_TX_RING_CNT - 1;
@@ -2195,12 +2478,15 @@
ifp->if_hwassist = BGE_CSUM_FEATURES;
ifp->if_capabilities = IFCAP_HWCSUM | IFCAP_VLAN_HWTAGGING |
IFCAP_VLAN_MTU;
+#ifdef IFCAP_VLAN_HWCSUM
+ ifp->if_capabilities |= IFCAP_VLAN_HWCSUM;
+#endif
ifp->if_capenable = ifp->if_capabilities;
#ifdef DEVICE_POLLING
ifp->if_capabilities |= IFCAP_POLLING;
#endif
- /*
+ /*
* 5700 B0 chips do not support checksumming correctly due
* to hardware bugs.
*/
@@ -2221,11 +2507,10 @@
*/
if (bge_readmem_ind(sc, BGE_SOFTWARE_GENCOMM_SIG) == BGE_MAGIC_NUMBER)
hwcfg = bge_readmem_ind(sc, BGE_SOFTWARE_GENCOMM_NICCFG);
- else {
+ else if (sc->bge_flags & BGE_FLAG_EEPROM) {
if (bge_read_eeprom(sc, (caddr_t)&hwcfg, BGE_EE_HWCFG_OFFSET,
sizeof(hwcfg))) {
device_printf(sc->bge_dev, "failed to read EEPROM\n");
- bge_release_resources(sc);
error = ENXIO;
goto fail;
}
@@ -2233,32 +2518,53 @@
}
if ((hwcfg & BGE_HWCFG_MEDIA) == BGE_MEDIA_FIBER)
- sc->bge_tbi = 1;
+ sc->bge_flags |= BGE_FLAG_TBI;
/* The SysKonnect SK-9D41 is a 1000baseSX card. */
if ((pci_read_config(dev, BGE_PCI_SUBSYS, 4) >> 16) == SK_SUBSYSID_9D41)
- sc->bge_tbi = 1;
+ sc->bge_flags |= BGE_FLAG_TBI;
- if (sc->bge_tbi) {
- ifmedia_init(&sc->bge_ifmedia, IFM_IMASK,
- bge_ifmedia_upd, bge_ifmedia_sts);
- ifmedia_add(&sc->bge_ifmedia, IFM_ETHER|IFM_1000_SX, 0, NULL);
- ifmedia_add(&sc->bge_ifmedia,
- IFM_ETHER|IFM_1000_SX|IFM_FDX, 0, NULL);
- ifmedia_add(&sc->bge_ifmedia, IFM_ETHER|IFM_AUTO, 0, NULL);
- ifmedia_set(&sc->bge_ifmedia, IFM_ETHER|IFM_AUTO);
+ if (sc->bge_flags & BGE_FLAG_TBI) {
+ ifmedia_init(&sc->bge_ifmedia, IFM_IMASK, bge_ifmedia_upd,
+ bge_ifmedia_sts);
+ ifmedia_add(&sc->bge_ifmedia, IFM_ETHER | IFM_1000_SX, 0, NULL);
+ ifmedia_add(&sc->bge_ifmedia, IFM_ETHER | IFM_1000_SX | IFM_FDX,
+ 0, NULL);
+ ifmedia_add(&sc->bge_ifmedia, IFM_ETHER | IFM_AUTO, 0, NULL);
+ ifmedia_set(&sc->bge_ifmedia, IFM_ETHER | IFM_AUTO);
sc->bge_ifmedia.ifm_media = sc->bge_ifmedia.ifm_cur->ifm_media;
} else {
/*
- * Do transceiver setup.
+ * Do transceiver setup and tell the firmware the
+ * driver is down so we can try to get access the
+ * probe if ASF is running. Retry a couple of times
+ * if we get a conflict with the ASF firmware accessing
+ * the PHY.
*/
+ BGE_CLRBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP);
+again:
+ bge_asf_driver_up(sc);
+
+ trys = 0;
if (mii_phy_probe(dev, &sc->bge_miibus,
bge_ifmedia_upd, bge_ifmedia_sts)) {
+ if (trys++ < 4) {
+ device_printf(sc->bge_dev, "Try again\n");
+ bge_miibus_writereg(sc->bge_dev, 1, MII_BMCR,
+ BMCR_RESET);
+ goto again;
+ }
+
device_printf(sc->bge_dev, "MII without any PHY!\n");
- bge_release_resources(sc);
error = ENXIO;
goto fail;
}
+
+ /*
+ * Now tell the firmware we are going up after probing the PHY
+ */
+ if (sc->bge_asf_mode & ASF_STACKUP)
+ BGE_SETBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP);
}
/*
@@ -2269,43 +2575,44 @@
* which do not support unaligned accesses, we will realign the
* payloads by copying the received packets.
*/
- switch (sc->bge_chipid) {
- case BGE_CHIPID_BCM5701_A0:
- case BGE_CHIPID_BCM5701_B0:
- case BGE_CHIPID_BCM5701_B2:
- case BGE_CHIPID_BCM5701_B5:
- /* If in PCI-X mode, work around the alignment bug. */
- if ((pci_read_config(dev, BGE_PCI_PCISTATE, 4) &
- (BGE_PCISTATE_PCI_BUSMODE | BGE_PCISTATE_PCI_BUSSPEED)) ==
- BGE_PCISTATE_PCI_BUSSPEED)
- sc->bge_rx_alignment_bug = 1;
- break;
- }
+ if (sc->bge_asicrev == BGE_ASICREV_BCM5701 &&
+ sc->bge_flags & BGE_FLAG_PCIX)
+ sc->bge_flags |= BGE_FLAG_RX_ALIGNBUG;
/*
* Call MI attach routine.
*/
ether_ifattach(ifp, eaddr);
- callout_init(&sc->bge_stat_ch, CALLOUT_MPSAFE);
+ callout_init_mtx(&sc->bge_stat_ch, &sc->bge_mtx, 0);
/*
* Hookup IRQ last.
*/
+#if __FreeBSD_version > 700030
+ error = bus_setup_intr(dev, sc->bge_irq, INTR_TYPE_NET | INTR_MPSAFE,
+ NULL, bge_intr, sc, &sc->bge_intrhand);
+#else
error = bus_setup_intr(dev, sc->bge_irq, INTR_TYPE_NET | INTR_MPSAFE,
bge_intr, sc, &sc->bge_intrhand);
+#endif
if (error) {
bge_detach(dev);
device_printf(sc->bge_dev, "couldn't set up irq\n");
}
+ bge_add_sysctls(sc);
+
+ return (0);
+
fail:
- return(error);
+ bge_release_resources(sc);
+
+ return (error);
}
static int
-bge_detach(dev)
- device_t dev;
+bge_detach(device_t dev)
{
struct bge_softc *sc;
struct ifnet *ifp;
@@ -2323,9 +2630,11 @@
bge_reset(sc);
BGE_UNLOCK(sc);
+ callout_drain(&sc->bge_stat_ch);
+
ether_ifdetach(ifp);
- if (sc->bge_tbi) {
+ if (sc->bge_flags & BGE_FLAG_TBI) {
ifmedia_removeall(&sc->bge_ifmedia);
} else {
bus_generic_detach(dev);
@@ -2334,28 +2643,27 @@
bge_release_resources(sc);
- return(0);
+ return (0);
}
static void
-bge_release_resources(sc)
- struct bge_softc *sc;
+bge_release_resources(struct bge_softc *sc)
{
device_t dev;
dev = sc->bge_dev;
- if (sc->bge_vpd_prodname != NULL)
- free(sc->bge_vpd_prodname, M_DEVBUF);
-
- if (sc->bge_vpd_readonly != NULL)
- free(sc->bge_vpd_readonly, M_DEVBUF);
-
if (sc->bge_intrhand != NULL)
bus_teardown_intr(dev, sc->bge_irq, sc->bge_intrhand);
if (sc->bge_irq != NULL)
- bus_release_resource(dev, SYS_RES_IRQ, 0, sc->bge_irq);
+ bus_release_resource(dev, SYS_RES_IRQ,
+ sc->bge_flags & BGE_FLAG_MSI ? 1 : 0, sc->bge_irq);
+
+#if __FreeBSD_version > 602105
+ if (sc->bge_flags & BGE_FLAG_MSI)
+ pci_release_msi(dev);
+#endif
if (sc->bge_res != NULL)
bus_release_resource(dev, SYS_RES_MEMORY,
@@ -2368,95 +2676,133 @@
if (mtx_initialized(&sc->bge_mtx)) /* XXX */
BGE_LOCK_DESTROY(sc);
-
- return;
}
-
-static void
-bge_reset(sc)
- struct bge_softc *sc;
+
+static int
+bge_reset(struct bge_softc *sc)
{
device_t dev;
- u_int32_t cachesize, command, pcistate, reset;
+ uint32_t cachesize, command, pcistate, reset;
+ void (*write_op)(struct bge_softc *, int, int);
int i, val = 0;
dev = sc->bge_dev;
+ if (BGE_IS_575X_PLUS(sc) && !BGE_IS_5714_FAMILY(sc)) {
+ if (sc->bge_flags & BGE_FLAG_PCIE)
+ write_op = bge_writemem_direct;
+ else
+ write_op = bge_writemem_ind;
+ } else
+ write_op = bge_writereg_ind;
+
/* Save some important PCI state. */
cachesize = pci_read_config(dev, BGE_PCI_CACHESZ, 4);
command = pci_read_config(dev, BGE_PCI_CMD, 4);
pcistate = pci_read_config(dev, BGE_PCI_PCISTATE, 4);
pci_write_config(dev, BGE_PCI_MISC_CTL,
- BGE_PCIMISCCTL_INDIRECT_ACCESS|BGE_PCIMISCCTL_MASK_PCI_INTR|
- BGE_HIF_SWAP_OPTIONS|BGE_PCIMISCCTL_PCISTATE_RW, 4);
+ BGE_PCIMISCCTL_INDIRECT_ACCESS | BGE_PCIMISCCTL_MASK_PCI_INTR |
+ BGE_HIF_SWAP_OPTIONS | BGE_PCIMISCCTL_PCISTATE_RW, 4);
+
+ /* Disable fastboot on controllers that support it. */
+ if (sc->bge_asicrev == BGE_ASICREV_BCM5752 ||
+ sc->bge_asicrev == BGE_ASICREV_BCM5755 ||
+ sc->bge_asicrev == BGE_ASICREV_BCM5787) {
+ if (bootverbose)
+ device_printf(sc->bge_dev, "Disabling fastboot\n");
+ CSR_WRITE_4(sc, BGE_FASTBOOT_PC, 0x0);
+ }
+
+ /*
+ * Write the magic number to SRAM at offset 0xB50.
+ * When firmware finishes its initialization it will
+ * write ~BGE_MAGIC_NUMBER to the same location.
+ */
+ bge_writemem_ind(sc, BGE_SOFTWARE_GENCOMM, BGE_MAGIC_NUMBER);
- reset = BGE_MISCCFG_RESET_CORE_CLOCKS|(65<<1);
+ reset = BGE_MISCCFG_RESET_CORE_CLOCKS | BGE_32BITTIME_66MHZ;
/* XXX: Broadcom Linux driver. */
- if (sc->bge_pcie) {
- if (CSR_READ_4(sc, 0x7e2c) == 0x60) /* PCIE 1.0 */
- CSR_WRITE_4(sc, 0x7e2c, 0x20);
+ if (sc->bge_flags & BGE_FLAG_PCIE) {
+ if (CSR_READ_4(sc, 0x7E2C) == 0x60) /* PCIE 1.0 */
+ CSR_WRITE_4(sc, 0x7E2C, 0x20);
if (sc->bge_chipid != BGE_CHIPID_BCM5750_A0) {
/* Prevent PCIE link training during global reset */
- CSR_WRITE_4(sc, BGE_MISC_CFG, (1<<29));
- reset |= (1<<29);
+ CSR_WRITE_4(sc, BGE_MISC_CFG, 1 << 29);
+ reset |= 1 << 29;
}
}
+ /*
+ * Set GPHY Power Down Override to leave GPHY
+ * powered up in D0 uninitialized.
+ */
+ if (BGE_IS_5705_PLUS(sc))
+ reset |= 0x04000000;
+
/* Issue global reset */
- bge_writereg_ind(sc, BGE_MISC_CFG, reset);
+ write_op(sc, BGE_MISC_CFG, reset);
DELAY(1000);
/* XXX: Broadcom Linux driver. */
- if (sc->bge_pcie) {
+ if (sc->bge_flags & BGE_FLAG_PCIE) {
if (sc->bge_chipid == BGE_CHIPID_BCM5750_A0) {
uint32_t v;
DELAY(500000); /* wait for link training to complete */
- v = pci_read_config(dev, 0xc4, 4);
- pci_write_config(dev, 0xc4, v | (1<<15), 4);
+ v = pci_read_config(dev, 0xC4, 4);
+ pci_write_config(dev, 0xC4, v | (1 << 15), 4);
}
- /* Set PCIE max payload size and clear error status. */
- pci_write_config(dev, 0xd8, 0xf5000, 4);
+ /*
+ * Set PCIE max payload size to 128 bytes and clear error
+ * status.
+ */
+ pci_write_config(dev, 0xD8, 0xF5000, 4);
}
- /* Reset some of the PCI state that got zapped by reset */
+ /* Reset some of the PCI state that got zapped by reset. */
pci_write_config(dev, BGE_PCI_MISC_CTL,
- BGE_PCIMISCCTL_INDIRECT_ACCESS|BGE_PCIMISCCTL_MASK_PCI_INTR|
- BGE_HIF_SWAP_OPTIONS|BGE_PCIMISCCTL_PCISTATE_RW, 4);
+ BGE_PCIMISCCTL_INDIRECT_ACCESS | BGE_PCIMISCCTL_MASK_PCI_INTR |
+ BGE_HIF_SWAP_OPTIONS | BGE_PCIMISCCTL_PCISTATE_RW, 4);
pci_write_config(dev, BGE_PCI_CACHESZ, cachesize, 4);
pci_write_config(dev, BGE_PCI_CMD, command, 4);
- bge_writereg_ind(sc, BGE_MISC_CFG, (65 << 1));
+ write_op(sc, BGE_MISC_CFG, BGE_32BITTIME_66MHZ);
- /* Enable memory arbiter. */
- if (sc->bge_asicrev != BGE_ASICREV_BCM5705 &&
- sc->bge_asicrev != BGE_ASICREV_BCM5750)
+ /* Re-enable MSI, if neccesary, and enable the memory arbiter. */
+ if (BGE_IS_5714_FAMILY(sc)) {
+ uint32_t val;
+
+ /* This chip disables MSI on reset. */
+ if (sc->bge_flags & BGE_FLAG_MSI) {
+ val = pci_read_config(dev, BGE_PCI_MSI_CTL, 2);
+ pci_write_config(dev, BGE_PCI_MSI_CTL,
+ val | PCIM_MSICTRL_MSI_ENABLE, 2);
+ val = CSR_READ_4(sc, BGE_MSI_MODE);
+ CSR_WRITE_4(sc, BGE_MSI_MODE,
+ val | BGE_MSIMODE_ENABLE);
+ }
+ val = CSR_READ_4(sc, BGE_MARB_MODE);
+ CSR_WRITE_4(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE | val);
+ } else
CSR_WRITE_4(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE);
/*
- * Prevent PXE restart: write a magic number to the
- * general communications memory at 0xB50.
- */
- bge_writemem_ind(sc, BGE_SOFTWARE_GENCOMM, BGE_MAGIC_NUMBER);
- /*
- * Poll the value location we just wrote until
- * we see the 1's complement of the magic number.
- * This indicates that the firmware initialization
- * is complete.
+ * Poll until we see the 1's complement of the magic number.
+ * This indicates that the firmware initialization is complete.
+ * We expect this to fail if no EEPROM is fitted though.
*/
for (i = 0; i < BGE_TIMEOUT; i++) {
+ DELAY(10);
val = bge_readmem_ind(sc, BGE_SOFTWARE_GENCOMM);
if (val == ~BGE_MAGIC_NUMBER)
break;
- DELAY(10);
}
- if (i == BGE_TIMEOUT) {
- device_printf(sc->bge_dev, "firmware handshake timed out\n");
- return;
- }
+ if ((sc->bge_flags & BGE_FLAG_EEPROM) && i == BGE_TIMEOUT)
+ device_printf(sc->bge_dev, "firmware handshake timed out, "
+ "found 0x%08x\n", val);
/*
* XXX Wait for the value of the PCISTATE register to
@@ -2472,10 +2818,19 @@
DELAY(10);
}
- /* Fix up byte swapping */
- CSR_WRITE_4(sc, BGE_MODE_CTL, BGE_DMA_SWAP_OPTIONS|
+ if (sc->bge_flags & BGE_FLAG_PCIE) {
+ reset = bge_readmem_ind(sc, 0x7C00);
+ bge_writemem_ind(sc, 0x7C00, reset | (1 << 25));
+ }
+
+ /* Fix up byte swapping. */
+ CSR_WRITE_4(sc, BGE_MODE_CTL, BGE_DMA_SWAP_OPTIONS |
BGE_MODECTL_BYTESWAP_DATA);
+ /* Tell the ASF firmware we are up */
+ if (sc->bge_asf_mode & ASF_STACKUP)
+ BGE_SETBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP);
+
CSR_WRITE_4(sc, BGE_MAC_MODE, 0);
/*
@@ -2483,23 +2838,26 @@
* adjustment to insure the SERDES drive level is set
* to 1.2V.
*/
- if (sc->bge_asicrev == BGE_ASICREV_BCM5704 && sc->bge_tbi) {
+ if (sc->bge_asicrev == BGE_ASICREV_BCM5704 &&
+ sc->bge_flags & BGE_FLAG_TBI) {
uint32_t serdescfg;
+
serdescfg = CSR_READ_4(sc, BGE_SERDES_CFG);
serdescfg = (serdescfg & ~0xFFF) | 0x880;
CSR_WRITE_4(sc, BGE_SERDES_CFG, serdescfg);
}
/* XXX: Broadcom Linux driver. */
- if (sc->bge_pcie && sc->bge_chipid != BGE_CHIPID_BCM5750_A0) {
+ if (sc->bge_flags & BGE_FLAG_PCIE &&
+ sc->bge_chipid != BGE_CHIPID_BCM5750_A0) {
uint32_t v;
- v = CSR_READ_4(sc, 0x7c00);
- CSR_WRITE_4(sc, 0x7c00, v | (1<<25));
+ v = CSR_READ_4(sc, 0x7C00);
+ CSR_WRITE_4(sc, 0x7C00, v | (1 << 25));
}
DELAY(10000);
- return;
+ return(0);
}
/*
@@ -2512,15 +2870,14 @@
*/
static void
-bge_rxeof(sc)
- struct bge_softc *sc;
+bge_rxeof(struct bge_softc *sc)
{
struct ifnet *ifp;
int stdcnt = 0, jumbocnt = 0;
BGE_LOCK_ASSERT(sc);
- /* Nothing to do */
+ /* Nothing to do. */
if (sc->bge_rx_saved_considx ==
sc->bge_ldata.bge_status_block->bge_idx[0].bge_rx_prod_idx)
return;
@@ -2531,20 +2888,16 @@
sc->bge_cdata.bge_rx_return_ring_map, BUS_DMASYNC_POSTREAD);
bus_dmamap_sync(sc->bge_cdata.bge_rx_std_ring_tag,
sc->bge_cdata.bge_rx_std_ring_map, BUS_DMASYNC_POSTREAD);
- if (sc->bge_asicrev != BGE_ASICREV_BCM5705 &&
- sc->bge_asicrev != BGE_ASICREV_BCM5750) {
+ if (BGE_IS_JUMBO_CAPABLE(sc))
bus_dmamap_sync(sc->bge_cdata.bge_rx_jumbo_ring_tag,
- sc->bge_cdata.bge_rx_jumbo_ring_map,
- BUS_DMASYNC_POSTREAD);
- }
+ sc->bge_cdata.bge_rx_jumbo_ring_map, BUS_DMASYNC_POSTREAD);
while(sc->bge_rx_saved_considx !=
sc->bge_ldata.bge_status_block->bge_idx[0].bge_rx_prod_idx) {
struct bge_rx_bd *cur_rx;
- u_int32_t rxidx;
- struct ether_header *eh;
+ uint32_t rxidx;
struct mbuf *m = NULL;
- u_int16_t vlan_tag = 0;
+ uint16_t vlan_tag = 0;
int have_tag = 0;
#ifdef DEVICE_POLLING
@@ -2561,7 +2914,8 @@
rxidx = cur_rx->bge_idx;
BGE_INC(sc->bge_rx_saved_considx, sc->bge_return_ring_cnt);
- if (cur_rx->bge_flags & BGE_RXBDFLAG_VLAN_TAG) {
+ if (ifp->if_capenable & IFCAP_VLAN_HWTAGGING &&
+ cur_rx->bge_flags & BGE_RXBDFLAG_VLAN_TAG) {
have_tag = 1;
vlan_tag = cur_rx->bge_vlan_tag;
}
@@ -2616,20 +2970,19 @@
* For architectures with strict alignment we must make sure
* the payload is aligned.
*/
- if (sc->bge_rx_alignment_bug) {
+ if (sc->bge_flags & BGE_FLAG_RX_ALIGNBUG) {
bcopy(m->m_data, m->m_data + ETHER_ALIGN,
cur_rx->bge_len);
m->m_data += ETHER_ALIGN;
}
#endif
- eh = mtod(m, struct ether_header *);
m->m_pkthdr.len = m->m_len = cur_rx->bge_len - ETHER_CRC_LEN;
m->m_pkthdr.rcvif = ifp;
if (ifp->if_capenable & IFCAP_RXCSUM) {
if (cur_rx->bge_flags & BGE_RXBDFLAG_IP_CSUM) {
m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED;
- if ((cur_rx->bge_ip_csum ^ 0xffff) == 0)
+ if ((cur_rx->bge_ip_csum ^ 0xFFFF) == 0)
m->m_pkthdr.csum_flags |= CSUM_IP_VALID;
}
if (cur_rx->bge_flags & BGE_RXBDFLAG_TCP_UDP_CSUM &&
@@ -2646,9 +2999,14 @@
* attach that information to the packet.
*/
if (have_tag) {
+#if __FreeBSD_version > 700022
+ m->m_pkthdr.ether_vtag = vlan_tag;
+ m->m_flags |= M_VLANTAG;
+#else
VLAN_INPUT_TAG_NEW(ifp, m, vlan_tag);
if (m == NULL)
continue;
+#endif
}
BGE_UNLOCK(sc);
@@ -2659,31 +3017,35 @@
if (stdcnt > 0)
bus_dmamap_sync(sc->bge_cdata.bge_rx_std_ring_tag,
sc->bge_cdata.bge_rx_std_ring_map, BUS_DMASYNC_PREWRITE);
- if (sc->bge_asicrev != BGE_ASICREV_BCM5705 &&
- sc->bge_asicrev != BGE_ASICREV_BCM5750) {
- if (jumbocnt > 0)
- bus_dmamap_sync(sc->bge_cdata.bge_rx_jumbo_ring_tag,
- sc->bge_cdata.bge_rx_jumbo_ring_map,
- BUS_DMASYNC_PREWRITE);
- }
+
+ if (BGE_IS_JUMBO_CAPABLE(sc) && jumbocnt > 0)
+ bus_dmamap_sync(sc->bge_cdata.bge_rx_jumbo_ring_tag,
+ sc->bge_cdata.bge_rx_jumbo_ring_map, BUS_DMASYNC_PREWRITE);
CSR_WRITE_4(sc, BGE_MBX_RX_CONS0_LO, sc->bge_rx_saved_considx);
if (stdcnt)
CSR_WRITE_4(sc, BGE_MBX_RX_STD_PROD_LO, sc->bge_std);
if (jumbocnt)
CSR_WRITE_4(sc, BGE_MBX_RX_JUMBO_PROD_LO, sc->bge_jumbo);
+#ifdef notyet
+ /*
+ * This register wraps very quickly under heavy packet drops.
+ * If you need correct statistics, you can enable this check.
+ */
+ if (BGE_IS_5705_PLUS(sc))
+ ifp->if_ierrors += CSR_READ_4(sc, BGE_RXLP_LOCSTAT_IFIN_DROPS);
+#endif
}
static void
-bge_txeof(sc)
- struct bge_softc *sc;
+bge_txeof(struct bge_softc *sc)
{
struct bge_tx_bd *cur_tx = NULL;
struct ifnet *ifp;
BGE_LOCK_ASSERT(sc);
- /* Nothing to do */
+ /* Nothing to do. */
if (sc->bge_tx_saved_considx ==
sc->bge_ldata.bge_status_block->bge_idx[0].bge_tx_cons_idx)
return;
@@ -2692,14 +3054,14 @@
bus_dmamap_sync(sc->bge_cdata.bge_tx_ring_tag,
sc->bge_cdata.bge_tx_ring_map,
- BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE);
+ BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
/*
* Go through our tx ring and free mbufs for those
* frames that have been sent.
*/
while (sc->bge_tx_saved_considx !=
sc->bge_ldata.bge_status_block->bge_idx[0].bge_tx_cons_idx) {
- u_int32_t idx = 0;
+ uint32_t idx = 0;
idx = sc->bge_tx_saved_considx;
cur_tx = &sc->bge_ldata.bge_tx_ring[idx];
@@ -2716,11 +3078,12 @@
}
sc->bge_txcnt--;
BGE_INC(sc->bge_tx_saved_considx, BGE_TX_RING_CNT);
- ifp->if_timer = 0;
}
if (cur_tx != NULL)
ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
+ if (sc->bge_txcnt == 0)
+ sc->bge_timer = 0;
}
#ifdef DEVICE_POLLING
@@ -2728,37 +3091,31 @@
bge_poll(struct ifnet *ifp, enum poll_cmd cmd, int count)
{
struct bge_softc *sc = ifp->if_softc;
+ uint32_t statusword;
BGE_LOCK(sc);
- if (ifp->if_drv_flags & IFF_DRV_RUNNING)
- bge_poll_locked(ifp, cmd, count);
- BGE_UNLOCK(sc);
-}
-
-static void
-bge_poll_locked(struct ifnet *ifp, enum poll_cmd cmd, int count)
-{
- struct bge_softc *sc = ifp->if_softc;
- uint32_t statusword;
-
- BGE_LOCK_ASSERT(sc);
+ if (!(ifp->if_drv_flags & IFF_DRV_RUNNING)) {
+ BGE_UNLOCK(sc);
+ return;
+ }
bus_dmamap_sync(sc->bge_cdata.bge_status_tag,
sc->bge_cdata.bge_status_map, BUS_DMASYNC_POSTREAD);
- statusword = atomic_readandclear_32(&sc->bge_ldata.bge_status_block->bge_status);
+ statusword = atomic_readandclear_32(
+ &sc->bge_ldata.bge_status_block->bge_status);
bus_dmamap_sync(sc->bge_cdata.bge_status_tag,
sc->bge_cdata.bge_status_map, BUS_DMASYNC_PREREAD);
- /* Note link event. It will be processed by POLL_AND_CHECK_STATUS cmd */
+ /* Note link event. It will be processed by POLL_AND_CHECK_STATUS. */
if (statusword & BGE_STATFLAG_LINKSTATE_CHANGED)
sc->bge_link_evt++;
if (cmd == POLL_AND_CHECK_STATUS)
if ((sc->bge_asicrev == BGE_ASICREV_BCM5700 &&
- sc->bge_chipid != BGE_CHIPID_BCM5700_B1) ||
- sc->bge_link_evt || sc->bge_tbi)
+ sc->bge_chipid != BGE_CHIPID_BCM5700_B2) ||
+ sc->bge_link_evt || (sc->bge_flags & BGE_FLAG_TBI))
bge_link_upd(sc);
sc->rxcycles = count;
@@ -2766,12 +3123,13 @@
bge_txeof(sc);
if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd))
bge_start_locked(ifp);
+
+ BGE_UNLOCK(sc);
}
#endif /* DEVICE_POLLING */
static void
-bge_intr(xsc)
- void *xsc;
+bge_intr(void *xsc)
{
struct bge_softc *sc;
struct ifnet *ifp;
@@ -2790,66 +3148,101 @@
}
#endif
- bus_dmamap_sync(sc->bge_cdata.bge_status_tag,
- sc->bge_cdata.bge_status_map, BUS_DMASYNC_POSTREAD);
+ /*
+ * Ack the interrupt by writing something to BGE_MBX_IRQ0_LO. Don't
+ * disable interrupts by writing nonzero like we used to, since with
+ * our current organization this just gives complications and
+ * pessimizations for re-enabling interrupts. We used to have races
+ * instead of the necessary complications. Disabling interrupts
+ * would just reduce the chance of a status update while we are
+ * running (by switching to the interrupt-mode coalescence
+ * parameters), but this chance is already very low so it is more
+ * efficient to get another interrupt than prevent it.
+ *
+ * We do the ack first to ensure another interrupt if there is a
+ * status update after the ack. We don't check for the status
+ * changing later because it is more efficient to get another
+ * interrupt than prevent it, not quite as above (not checking is
+ * a smaller optimization than not toggling the interrupt enable,
+ * since checking doesn't involve PCI accesses and toggling require
+ * the status check). So toggling would probably be a pessimization
+ * even with MSI. It would only be needed for using a task queue.
+ */
+ CSR_WRITE_4(sc, BGE_MBX_IRQ0_LO, 0);
- statusword =
- atomic_readandclear_32(&sc->bge_ldata.bge_status_block->bge_status);
+ /*
+ * Do the mandatory PCI flush as well as get the link status.
+ */
+ statusword = CSR_READ_4(sc, BGE_MAC_STS) & BGE_MACSTAT_LINK_CHANGED;
+ /* Make sure the descriptor ring indexes are coherent. */
+ bus_dmamap_sync(sc->bge_cdata.bge_status_tag,
+ sc->bge_cdata.bge_status_map, BUS_DMASYNC_POSTREAD);
bus_dmamap_sync(sc->bge_cdata.bge_status_tag,
sc->bge_cdata.bge_status_map, BUS_DMASYNC_PREREAD);
-#ifdef notdef
- /* Avoid this for now -- checking this register is expensive. */
- /* Make sure this is really our interrupt. */
- if (!(CSR_READ_4(sc, BGE_MISC_LOCAL_CTL) & BGE_MLC_INTR_STATE))
- return;
-#endif
- /* Ack interrupt and stop others from occuring. */
- CSR_WRITE_4(sc, BGE_MBX_IRQ0_LO, 1);
-
if ((sc->bge_asicrev == BGE_ASICREV_BCM5700 &&
- sc->bge_chipid != BGE_CHIPID_BCM5700_B1) ||
- statusword & BGE_STATFLAG_LINKSTATE_CHANGED || sc->bge_link_evt)
+ sc->bge_chipid != BGE_CHIPID_BCM5700_B2) ||
+ statusword || sc->bge_link_evt)
bge_link_upd(sc);
if (ifp->if_drv_flags & IFF_DRV_RUNNING) {
- /* Check RX return ring producer/consumer */
+ /* Check RX return ring producer/consumer. */
bge_rxeof(sc);
- /* Check TX ring producer/consumer */
+ /* Check TX ring producer/consumer. */
bge_txeof(sc);
}
- /* Re-enable interrupts. */
- CSR_WRITE_4(sc, BGE_MBX_IRQ0_LO, 0);
-
if (ifp->if_drv_flags & IFF_DRV_RUNNING &&
!IFQ_DRV_IS_EMPTY(&ifp->if_snd))
bge_start_locked(ifp);
BGE_UNLOCK(sc);
+}
- return;
+static void
+bge_asf_driver_up(struct bge_softc *sc)
+{
+ if (sc->bge_asf_mode & ASF_STACKUP) {
+ /* Send ASF heartbeat aprox. every 2s */
+ if (sc->bge_asf_count)
+ sc->bge_asf_count --;
+ else {
+ sc->bge_asf_count = 5;
+ bge_writemem_ind(sc, BGE_SOFTWARE_GENCOMM_FW,
+ BGE_FW_DRV_ALIVE);
+ bge_writemem_ind(sc, BGE_SOFTWARE_GENNCOMM_FW_LEN, 4);
+ bge_writemem_ind(sc, BGE_SOFTWARE_GENNCOMM_FW_DATA, 3);
+ CSR_WRITE_4(sc, BGE_CPU_EVENT,
+ CSR_READ_4(sc, BGE_CPU_EVENT) | (1 << 14));
+ }
+ }
}
static void
-bge_tick_locked(sc)
- struct bge_softc *sc;
+bge_tick(void *xsc)
{
+ struct bge_softc *sc = xsc;
struct mii_data *mii = NULL;
BGE_LOCK_ASSERT(sc);
- if (sc->bge_asicrev == BGE_ASICREV_BCM5705 ||
- sc->bge_asicrev == BGE_ASICREV_BCM5750)
+ /* Synchronize with possible callout reset/stop. */
+ if (callout_pending(&sc->bge_stat_ch) ||
+ !callout_active(&sc->bge_stat_ch))
+ return;
+
+ if (BGE_IS_5705_PLUS(sc))
bge_stats_update_regs(sc);
else
bge_stats_update(sc);
- if (!sc->bge_tbi) {
+ if ((sc->bge_flags & BGE_FLAG_TBI) == 0) {
mii = device_get_softc(sc->bge_miibus);
- mii_tick(mii);
+ /* Don't mess with the PHY in IPMI/ASF mode */
+ if (!((sc->bge_asf_mode & ASF_STACKUP) && (sc->bge_link)))
+ mii_tick(mii);
} else {
/*
* Since in TBI mode auto-polling can't be used we should poll
@@ -2857,7 +3250,7 @@
* and trigger interrupt.
*/
#ifdef DEVICE_POLLING
- /* In polling mode we poll link state in bge_poll_locked() */
+ /* In polling mode we poll link state in bge_poll(). */
if (!(sc->bge_ifp->if_capenable & IFCAP_POLLING))
#endif
{
@@ -2866,87 +3259,52 @@
}
}
- callout_reset(&sc->bge_stat_ch, hz, bge_tick, sc);
-}
-
-static void
-bge_tick(xsc)
- void *xsc;
-{
- struct bge_softc *sc;
-
- sc = xsc;
+ bge_asf_driver_up(sc);
+ bge_watchdog(sc);
- BGE_LOCK(sc);
- bge_tick_locked(sc);
- BGE_UNLOCK(sc);
+ callout_reset(&sc->bge_stat_ch, hz, bge_tick, sc);
}
static void
-bge_stats_update_regs(sc)
- struct bge_softc *sc;
+bge_stats_update_regs(struct bge_softc *sc)
{
struct ifnet *ifp;
- struct bge_mac_stats_regs stats;
- u_int32_t *s;
- u_long cnt; /* current register value */
- int i;
ifp = sc->bge_ifp;
- s = (u_int32_t *)&stats;
- for (i = 0; i < sizeof(struct bge_mac_stats_regs); i += 4) {
- *s = CSR_READ_4(sc, BGE_RX_STATS + i);
- s++;
- }
+ ifp->if_collisions += CSR_READ_4(sc, BGE_MAC_STATS +
+ offsetof(struct bge_mac_stats_regs, etherStatsCollisions));
- cnt = stats.dot3StatsSingleCollisionFrames +
- stats.dot3StatsMultipleCollisionFrames +
- stats.dot3StatsExcessiveCollisions +
- stats.dot3StatsLateCollisions;
- ifp->if_collisions += cnt >= sc->bge_tx_collisions ?
- cnt - sc->bge_tx_collisions : cnt;
- sc->bge_tx_collisions = cnt;
+ ifp->if_ierrors += CSR_READ_4(sc, BGE_RXLP_LOCSTAT_IFIN_DROPS);
}
static void
-bge_stats_update(sc)
- struct bge_softc *sc;
+bge_stats_update(struct bge_softc *sc)
{
struct ifnet *ifp;
bus_size_t stats;
- u_long cnt; /* current register value */
+ uint32_t cnt; /* current register value */
ifp = sc->bge_ifp;
stats = BGE_MEMWIN_START + BGE_STATS_BLOCK;
-#define READ_STAT(sc, stats, stat) \
+#define READ_STAT(sc, stats, stat) \
CSR_READ_4(sc, stats + offsetof(struct bge_stats, stat))
- cnt = READ_STAT(sc, stats,
- txstats.dot3StatsSingleCollisionFrames.bge_addr_lo);
- cnt += READ_STAT(sc, stats,
- txstats.dot3StatsMultipleCollisionFrames.bge_addr_lo);
- cnt += READ_STAT(sc, stats,
- txstats.dot3StatsExcessiveCollisions.bge_addr_lo);
- cnt += READ_STAT(sc, stats,
- txstats.dot3StatsLateCollisions.bge_addr_lo);
- ifp->if_collisions += cnt >= sc->bge_tx_collisions ?
- cnt - sc->bge_tx_collisions : cnt;
+ cnt = READ_STAT(sc, stats, txstats.etherStatsCollisions.bge_addr_lo);
+ ifp->if_collisions += (uint32_t)(cnt - sc->bge_tx_collisions);
sc->bge_tx_collisions = cnt;
cnt = READ_STAT(sc, stats, ifInDiscards.bge_addr_lo);
- ifp->if_ierrors += cnt >= sc->bge_rx_discards ?
- cnt - sc->bge_rx_discards : cnt;
+ ifp->if_ierrors += (uint32_t)(cnt - sc->bge_rx_discards);
sc->bge_rx_discards = cnt;
cnt = READ_STAT(sc, stats, txstats.ifOutDiscards.bge_addr_lo);
- ifp->if_oerrors += cnt >= sc->bge_tx_discards ?
- cnt - sc->bge_tx_discards : cnt;
+ ifp->if_oerrors += (uint32_t)(cnt - sc->bge_tx_discards);
sc->bge_tx_discards = cnt;
-#undef READ_STAT
+#undef READ_STAT
}
/*
@@ -2999,53 +3357,55 @@
* pointers to descriptors.
*/
static int
-bge_encap(sc, m_head, txidx)
- struct bge_softc *sc;
- struct mbuf *m_head;
- uint32_t *txidx;
+bge_encap(struct bge_softc *sc, struct mbuf **m_head, uint32_t *txidx)
{
bus_dma_segment_t segs[BGE_NSEG_NEW];
bus_dmamap_t map;
- struct bge_tx_bd *d = NULL;
- struct m_tag *mtag;
+ struct bge_tx_bd *d;
+ struct mbuf *m = *m_head;
uint32_t idx = *txidx;
- uint16_t csum_flags = 0;
+ uint16_t csum_flags;
int nsegs, i, error;
- if (m_head->m_pkthdr.csum_flags) {
- if (m_head->m_pkthdr.csum_flags & CSUM_IP)
+ csum_flags = 0;
+ if (m->m_pkthdr.csum_flags) {
+ if (m->m_pkthdr.csum_flags & CSUM_IP)
csum_flags |= BGE_TXBDFLAG_IP_CSUM;
- if (m_head->m_pkthdr.csum_flags & (CSUM_TCP | CSUM_UDP)) {
+ if (m->m_pkthdr.csum_flags & (CSUM_TCP | CSUM_UDP)) {
csum_flags |= BGE_TXBDFLAG_TCP_UDP_CSUM;
- if (m_head->m_pkthdr.len < ETHER_MIN_NOPAD &&
- bge_cksum_pad(m_head) != 0)
- return (ENOBUFS);
+ if (m->m_pkthdr.len < ETHER_MIN_NOPAD &&
+ (error = bge_cksum_pad(m)) != 0) {
+ m_freem(m);
+ *m_head = NULL;
+ return (error);
+ }
}
- if (m_head->m_flags & M_LASTFRAG)
+ if (m->m_flags & M_LASTFRAG)
csum_flags |= BGE_TXBDFLAG_IP_FRAG_END;
- else if (m_head->m_flags & M_FRAG)
+ else if (m->m_flags & M_FRAG)
csum_flags |= BGE_TXBDFLAG_IP_FRAG;
}
- mtag = VLAN_OUTPUT_TAG(sc->bge_ifp, m_head);
-
map = sc->bge_cdata.bge_tx_dmamap[idx];
- error = bus_dmamap_load_mbuf_sg(sc->bge_cdata.bge_mtag, map,
- m_head, segs, &nsegs, BUS_DMA_NOWAIT);
- if (error) {
- if (error == EFBIG) {
- struct mbuf *m0;
-
- m0 = m_defrag(m_head, M_DONTWAIT);
- if (m0 == NULL)
- return (ENOBUFS);
- m_head = m0;
- error = bus_dmamap_load_mbuf_sg(sc->bge_cdata.bge_mtag,
- map, m_head, segs, &nsegs, BUS_DMA_NOWAIT);
+ error = bus_dmamap_load_mbuf_sg(sc->bge_cdata.bge_mtag, map, m, segs,
+ &nsegs, BUS_DMA_NOWAIT);
+ if (error == EFBIG) {
+ m = m_defrag(m, M_DONTWAIT);
+ if (m == NULL) {
+ m_freem(*m_head);
+ *m_head = NULL;
+ return (ENOBUFS);
+ }
+ *m_head = m;
+ error = bus_dmamap_load_mbuf_sg(sc->bge_cdata.bge_mtag, map, m,
+ segs, &nsegs, BUS_DMA_NOWAIT);
+ if (error) {
+ m_freem(m);
+ *m_head = NULL;
+ return (error);
}
- if (error)
- return (error);
- }
+ } else if (error != 0)
+ return (error);
/*
* Sanity check: avoid coming within 16 descriptors
@@ -3071,13 +3431,26 @@
/* Mark the last segment as end of packet... */
d->bge_flags |= BGE_TXBDFLAG_END;
+
/* ... and put VLAN tag into first segment. */
d = &sc->bge_ldata.bge_tx_ring[*txidx];
- if (mtag != NULL) {
+#if __FreeBSD_version > 700022
+ if (m->m_flags & M_VLANTAG) {
d->bge_flags |= BGE_TXBDFLAG_VLAN_TAG;
- d->bge_vlan_tag = VLAN_TAG_VALUE(mtag);
+ d->bge_vlan_tag = m->m_pkthdr.ether_vtag;
} else
d->bge_vlan_tag = 0;
+#else
+ {
+ struct m_tag *mtag;
+
+ if ((mtag = VLAN_OUTPUT_TAG(sc->bge_ifp, m)) != NULL) {
+ d->bge_flags |= BGE_TXBDFLAG_VLAN_TAG;
+ d->bge_vlan_tag = VLAN_TAG_VALUE(mtag);
+ } else
+ d->bge_vlan_tag = 0;
+ }
+#endif
/*
* Insure that the map for this transmission
@@ -3086,7 +3459,7 @@
*/
sc->bge_cdata.bge_tx_dmamap[*txidx] = sc->bge_cdata.bge_tx_dmamap[idx];
sc->bge_cdata.bge_tx_dmamap[idx] = map;
- sc->bge_cdata.bge_tx_chain[idx] = m_head;
+ sc->bge_cdata.bge_tx_chain[idx] = m;
sc->bge_txcnt += nsegs;
BGE_INC(idx, BGE_TX_RING_CNT);
@@ -3100,8 +3473,7 @@
* to the mbuf data regions directly in the transmit descriptors.
*/
static void
-bge_start_locked(ifp)
- struct ifnet *ifp;
+bge_start_locked(struct ifnet *ifp)
{
struct bge_softc *sc;
struct mbuf *m_head = NULL;
@@ -3148,7 +3520,9 @@
* don't have room, set the OACTIVE flag and wait
* for the NIC to drain the ring.
*/
- if (bge_encap(sc, m_head, &prodidx)) {
+ if (bge_encap(sc, &m_head, &prodidx)) {
+ if (m_head == NULL)
+ break;
IFQ_DRV_PREPEND(&ifp->if_snd, m_head);
ifp->if_drv_flags |= IFF_DRV_OACTIVE;
break;
@@ -3159,15 +3533,18 @@
* If there's a BPF listener, bounce a copy of this frame
* to him.
*/
+#ifdef ETHER_BPF_MTAP
+ ETHER_BPF_MTAP(ifp, m_head);
+#else
BPF_MTAP(ifp, m_head);
+#endif
}
- if (count == 0) {
- /* no packets were dequeued */
+ if (count == 0)
+ /* No packets were dequeued. */
return;
- }
- /* Transmit */
+ /* Transmit. */
CSR_WRITE_4(sc, BGE_MBX_TX_HOST_PROD0_LO, prodidx);
/* 5700 b2 errata */
if (sc->bge_chiprev == BGE_CHIPREV_5700_BX)
@@ -3178,9 +3555,7 @@
/*
* Set a timeout in case the chip goes out to lunch.
*/
- ifp->if_timer = 5;
-
- return;
+ sc->bge_timer = 5;
}
/*
@@ -3188,8 +3563,7 @@
* to the mbuf data regions directly in the transmit descriptors.
*/
static void
-bge_start(ifp)
- struct ifnet *ifp;
+bge_start(struct ifnet *ifp)
{
struct bge_softc *sc;
@@ -3200,11 +3574,10 @@
}
static void
-bge_init_locked(sc)
- struct bge_softc *sc;
+bge_init_locked(struct bge_softc *sc)
{
struct ifnet *ifp;
- u_int16_t *m;
+ uint16_t *m;
BGE_LOCK_ASSERT(sc);
@@ -3215,7 +3588,13 @@
/* Cancel pending I/O and flush buffers. */
bge_stop(sc);
+
+ bge_stop_fw(sc);
+ bge_sig_pre_reset(sc, BGE_RESET_START);
bge_reset(sc);
+ bge_sig_legacy(sc, BGE_RESET_START);
+ bge_sig_post_reset(sc, BGE_RESET_START);
+
bge_chipinit(sc);
/*
@@ -3231,23 +3610,23 @@
/* Specify MTU. */
CSR_WRITE_4(sc, BGE_RX_MTU, ifp->if_mtu +
- ETHER_HDR_LEN + ETHER_CRC_LEN + ETHER_VLAN_ENCAP_LEN);
+ ETHER_HDR_LEN + ETHER_CRC_LEN +
+ (ifp->if_capenable & IFCAP_VLAN_MTU ? ETHER_VLAN_ENCAP_LEN : 0));
/* Load our MAC address. */
- m = (u_int16_t *)&IFP2ENADDR(sc->bge_ifp)[0];
+ m = (uint16_t *)IF_LLADDR(sc->bge_ifp);
CSR_WRITE_4(sc, BGE_MAC_ADDR1_LO, htons(m[0]));
CSR_WRITE_4(sc, BGE_MAC_ADDR1_HI, (htons(m[1]) << 16) | htons(m[2]));
- /* Enable or disable promiscuous mode as needed. */
- if (ifp->if_flags & IFF_PROMISC) {
- BGE_SETBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_PROMISC);
- } else {
- BGE_CLRBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_PROMISC);
- }
+ /* Program promiscuous mode. */
+ bge_setpromisc(sc);
/* Program multicast filter. */
bge_setmulti(sc);
+ /* Program VLAN tag stripping. */
+ bge_setvlan(sc);
+
/* Init RX ring. */
bge_init_rx_ring_std(sc);
@@ -3257,7 +3636,7 @@
* entry of the ring.
*/
if (sc->bge_chipid == BGE_CHIPID_BCM5705_A0) {
- u_int32_t v, i;
+ uint32_t v, i;
for (i = 0; i < 10; i++) {
DELAY(20);
v = bge_readmem_ind(sc, BGE_STD_RX_RINGS + 8);
@@ -3273,16 +3652,19 @@
if (ifp->if_mtu > (ETHERMTU + ETHER_HDR_LEN + ETHER_CRC_LEN))
bge_init_rx_ring_jumbo(sc);
- /* Init our RX return ring index */
+ /* Init our RX return ring index. */
sc->bge_rx_saved_considx = 0;
+ /* Init our RX/TX stat counters. */
+ sc->bge_rx_discards = sc->bge_tx_discards = sc->bge_tx_collisions = 0;
+
/* Init TX ring. */
bge_init_tx_ring(sc);
- /* Turn on transmitter */
+ /* Turn on transmitter. */
BGE_SETBIT(sc, BGE_TX_MODE, BGE_TXMODE_ENABLE);
- /* Turn on receiver */
+ /* Turn on receiver. */
BGE_SETBIT(sc, BGE_RX_MODE, BGE_RXMODE_ENABLE);
/* Tell firmware we're alive. */
@@ -3294,11 +3676,9 @@
BGE_SETBIT(sc, BGE_PCI_MISC_CTL,
BGE_PCIMISCCTL_MASK_PCI_INTR);
CSR_WRITE_4(sc, BGE_MBX_IRQ0_LO, 1);
- CSR_WRITE_4(sc, BGE_HCC_RX_MAX_COAL_BDS_INT, 1);
- CSR_WRITE_4(sc, BGE_HCC_TX_MAX_COAL_BDS_INT, 1);
} else
#endif
-
+
/* Enable host interrupts. */
{
BGE_SETBIT(sc, BGE_PCI_MISC_CTL, BGE_PCIMISCCTL_CLEAR_INTA);
@@ -3306,7 +3686,7 @@
CSR_WRITE_4(sc, BGE_MBX_IRQ0_LO, 0);
}
- bge_ifmedia_upd(ifp);
+ bge_ifmedia_upd_locked(ifp);
ifp->if_drv_flags |= IFF_DRV_RUNNING;
ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
@@ -3315,39 +3695,48 @@
}
static void
-bge_init(xsc)
- void *xsc;
+bge_init(void *xsc)
{
struct bge_softc *sc = xsc;
BGE_LOCK(sc);
bge_init_locked(sc);
BGE_UNLOCK(sc);
-
- return;
}
/*
* Set media options.
*/
static int
-bge_ifmedia_upd(ifp)
- struct ifnet *ifp;
+bge_ifmedia_upd(struct ifnet *ifp)
{
- struct bge_softc *sc;
+ struct bge_softc *sc = ifp->if_softc;
+ int res;
+
+ BGE_LOCK(sc);
+ res = bge_ifmedia_upd_locked(ifp);
+ BGE_UNLOCK(sc);
+
+ return (res);
+}
+
+static int
+bge_ifmedia_upd_locked(struct ifnet *ifp)
+{
+ struct bge_softc *sc = ifp->if_softc;
struct mii_data *mii;
struct ifmedia *ifm;
- sc = ifp->if_softc;
+ BGE_LOCK_ASSERT(sc);
+
ifm = &sc->bge_ifmedia;
/* If this is a 1000baseX NIC, enable the TBI port. */
- if (sc->bge_tbi) {
+ if (sc->bge_flags & BGE_FLAG_TBI) {
if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER)
- return(EINVAL);
+ return (EINVAL);
switch(IFM_SUBTYPE(ifm->ifm_media)) {
case IFM_AUTO:
-#ifndef BGE_FAKE_AUTONEG
/*
* The BCM5704 ASIC appears to have a special
* mechanism for programming the autoneg
@@ -3355,17 +3744,19 @@
*/
if (sc->bge_asicrev == BGE_ASICREV_BCM5704) {
uint32_t sgdig;
- CSR_WRITE_4(sc, BGE_TX_TBI_AUTONEG, 0);
- sgdig = CSR_READ_4(sc, BGE_SGDIG_CFG);
- sgdig |= BGE_SGDIGCFG_AUTO|
- BGE_SGDIGCFG_PAUSE_CAP|
- BGE_SGDIGCFG_ASYM_PAUSE;
- CSR_WRITE_4(sc, BGE_SGDIG_CFG,
- sgdig|BGE_SGDIGCFG_SEND);
- DELAY(5);
- CSR_WRITE_4(sc, BGE_SGDIG_CFG, sgdig);
+ sgdig = CSR_READ_4(sc, BGE_SGDIG_STS);
+ if (sgdig & BGE_SGDIGSTS_DONE) {
+ CSR_WRITE_4(sc, BGE_TX_TBI_AUTONEG, 0);
+ sgdig = CSR_READ_4(sc, BGE_SGDIG_CFG);
+ sgdig |= BGE_SGDIGCFG_AUTO |
+ BGE_SGDIGCFG_PAUSE_CAP |
+ BGE_SGDIGCFG_ASYM_PAUSE;
+ CSR_WRITE_4(sc, BGE_SGDIG_CFG,
+ sgdig | BGE_SGDIGCFG_SEND);
+ DELAY(5);
+ CSR_WRITE_4(sc, BGE_SGDIG_CFG, sgdig);
+ }
}
-#endif
break;
case IFM_1000_SX:
if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) {
@@ -3377,9 +3768,9 @@
}
break;
default:
- return(EINVAL);
+ return (EINVAL);
}
- return(0);
+ return (0);
}
sc->bge_link_evt++;
@@ -3392,33 +3783,37 @@
}
mii_mediachg(mii);
- return(0);
+ return (0);
}
/*
* Report current media status.
*/
static void
-bge_ifmedia_sts(ifp, ifmr)
- struct ifnet *ifp;
- struct ifmediareq *ifmr;
+bge_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr)
{
- struct bge_softc *sc;
+ struct bge_softc *sc = ifp->if_softc;
struct mii_data *mii;
- sc = ifp->if_softc;
+ BGE_LOCK(sc);
- if (sc->bge_tbi) {
+ if (sc->bge_flags & BGE_FLAG_TBI) {
ifmr->ifm_status = IFM_AVALID;
ifmr->ifm_active = IFM_ETHER;
if (CSR_READ_4(sc, BGE_MAC_STS) &
BGE_MACSTAT_TBI_PCS_SYNCHED)
ifmr->ifm_status |= IFM_ACTIVE;
+ else {
+ ifmr->ifm_active |= IFM_NONE;
+ BGE_UNLOCK(sc);
+ return;
+ }
ifmr->ifm_active |= IFM_1000_SX;
if (CSR_READ_4(sc, BGE_MAC_MODE) & BGE_MACMODE_HALF_DUPLEX)
ifmr->ifm_active |= IFM_HDX;
else
ifmr->ifm_active |= IFM_FDX;
+ BGE_UNLOCK(sc);
return;
}
@@ -3427,28 +3822,26 @@
ifmr->ifm_active = mii->mii_media_active;
ifmr->ifm_status = mii->mii_media_status;
- return;
+ BGE_UNLOCK(sc);
}
static int
-bge_ioctl(ifp, command, data)
- struct ifnet *ifp;
- u_long command;
- caddr_t data;
+bge_ioctl(struct ifnet *ifp, u_long command, caddr_t data)
{
struct bge_softc *sc = ifp->if_softc;
struct ifreq *ifr = (struct ifreq *) data;
- int mask, error = 0;
struct mii_data *mii;
+ int flags, mask, error = 0;
- switch(command) {
+ switch (command) {
case SIOCSIFMTU:
- /* Disallow jumbo frames on 5705. */
- if (((sc->bge_asicrev == BGE_ASICREV_BCM5705 ||
- sc->bge_asicrev == BGE_ASICREV_BCM5750) &&
- ifr->ifr_mtu > ETHERMTU) || ifr->ifr_mtu > BGE_JUMBO_MTU)
+ if (ifr->ifr_mtu < ETHERMIN ||
+ ((BGE_IS_JUMBO_CAPABLE(sc)) &&
+ ifr->ifr_mtu > BGE_JUMBO_MTU) ||
+ ((!BGE_IS_JUMBO_CAPABLE(sc)) &&
+ ifr->ifr_mtu > ETHERMTU))
error = EINVAL;
- else {
+ else if (ifp->if_mtu != ifr->ifr_mtu) {
ifp->if_mtu = ifr->ifr_mtu;
ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
bge_init(sc);
@@ -3465,19 +3858,12 @@
* waiting for it to start up, which may take a
* second or two. Similarly for ALLMULTI.
*/
- if (ifp->if_drv_flags & IFF_DRV_RUNNING &&
- ifp->if_flags & IFF_PROMISC &&
- !(sc->bge_if_flags & IFF_PROMISC)) {
- BGE_SETBIT(sc, BGE_RX_MODE,
- BGE_RXMODE_RX_PROMISC);
- } else if (ifp->if_drv_flags & IFF_DRV_RUNNING &&
- !(ifp->if_flags & IFF_PROMISC) &&
- sc->bge_if_flags & IFF_PROMISC) {
- BGE_CLRBIT(sc, BGE_RX_MODE,
- BGE_RXMODE_RX_PROMISC);
- } else if (ifp->if_drv_flags & IFF_DRV_RUNNING &&
- (ifp->if_flags ^ sc->bge_if_flags) & IFF_ALLMULTI) {
- bge_setmulti(sc);
+ if (ifp->if_drv_flags & IFF_DRV_RUNNING) {
+ flags = ifp->if_flags ^ sc->bge_if_flags;
+ if (flags & IFF_PROMISC)
+ bge_setpromisc(sc);
+ if (flags & IFF_ALLMULTI)
+ bge_setmulti(sc);
} else
bge_init_locked(sc);
} else {
@@ -3500,7 +3886,7 @@
break;
case SIOCSIFMEDIA:
case SIOCGIFMEDIA:
- if (sc->bge_tbi) {
+ if (sc->bge_flags & BGE_FLAG_TBI) {
error = ifmedia_ioctl(ifp, ifr,
&sc->bge_ifmedia, command);
} else {
@@ -3516,21 +3902,17 @@
if (ifr->ifr_reqcap & IFCAP_POLLING) {
error = ether_poll_register(bge_poll, ifp);
if (error)
- return(error);
+ return (error);
BGE_LOCK(sc);
BGE_SETBIT(sc, BGE_PCI_MISC_CTL,
BGE_PCIMISCCTL_MASK_PCI_INTR);
CSR_WRITE_4(sc, BGE_MBX_IRQ0_LO, 1);
- CSR_WRITE_4(sc, BGE_HCC_RX_MAX_COAL_BDS_INT, 1);
- CSR_WRITE_4(sc, BGE_HCC_TX_MAX_COAL_BDS_INT, 1);
- ifp->if_capenable |= IFCAP_POLLING;
+ ifp->if_capenable |= IFCAP_POLLING;
BGE_UNLOCK(sc);
} else {
error = ether_poll_deregister(ifp);
/* Enable interrupt even in error case */
BGE_LOCK(sc);
- CSR_WRITE_4(sc, BGE_HCC_RX_MAX_COAL_BDS_INT, 0);
- CSR_WRITE_4(sc, BGE_HCC_TX_MAX_COAL_BDS_INT, 0);
BGE_CLRBIT(sc, BGE_PCI_MISC_CTL,
BGE_PCIMISCCTL_MASK_PCI_INTR);
CSR_WRITE_4(sc, BGE_MBX_IRQ0_LO, 0);
@@ -3546,32 +3928,54 @@
ifp->if_hwassist = BGE_CSUM_FEATURES;
else
ifp->if_hwassist = 0;
+#ifdef VLAN_CAPABILITIES
+ VLAN_CAPABILITIES(ifp);
+#endif
+ }
+
+ if (mask & IFCAP_VLAN_MTU) {
+ ifp->if_capenable ^= IFCAP_VLAN_MTU;
+ ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
+ bge_init(sc);
+ }
+
+ if (mask & IFCAP_VLAN_HWTAGGING) {
+ ifp->if_capenable ^= IFCAP_VLAN_HWTAGGING;
+ BGE_LOCK(sc);
+ bge_setvlan(sc);
+ BGE_UNLOCK(sc);
+#ifdef VLAN_CAPABILITIES
+ VLAN_CAPABILITIES(ifp);
+#endif
}
+
break;
default:
error = ether_ioctl(ifp, command, data);
break;
}
- return(error);
+ return (error);
}
static void
-bge_watchdog(ifp)
- struct ifnet *ifp;
+bge_watchdog(struct bge_softc *sc)
{
- struct bge_softc *sc;
+ struct ifnet *ifp;
- sc = ifp->if_softc;
+ BGE_LOCK_ASSERT(sc);
+
+ if (sc->bge_timer == 0 || --sc->bge_timer)
+ return;
+
+ ifp = sc->bge_ifp;
if_printf(ifp, "watchdog timeout -- resetting\n");
ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
- bge_init(sc);
+ bge_init_locked(sc);
ifp->if_oerrors++;
-
- return;
}
/*
@@ -3579,8 +3983,7 @@
* RX and TX lists.
*/
static void
-bge_stop(sc)
- struct bge_softc *sc;
+bge_stop(struct bge_softc *sc)
{
struct ifnet *ifp;
struct ifmedia_entry *ifm;
@@ -3591,34 +3994,32 @@
ifp = sc->bge_ifp;
- if (!sc->bge_tbi)
+ if ((sc->bge_flags & BGE_FLAG_TBI) == 0)
mii = device_get_softc(sc->bge_miibus);
callout_stop(&sc->bge_stat_ch);
/*
- * Disable all of the receiver blocks
+ * Disable all of the receiver blocks.
*/
BGE_CLRBIT(sc, BGE_RX_MODE, BGE_RXMODE_ENABLE);
BGE_CLRBIT(sc, BGE_RBDI_MODE, BGE_RBDIMODE_ENABLE);
BGE_CLRBIT(sc, BGE_RXLP_MODE, BGE_RXLPMODE_ENABLE);
- if (sc->bge_asicrev != BGE_ASICREV_BCM5705 &&
- sc->bge_asicrev != BGE_ASICREV_BCM5750)
+ if (!(BGE_IS_5705_PLUS(sc)))
BGE_CLRBIT(sc, BGE_RXLS_MODE, BGE_RXLSMODE_ENABLE);
BGE_CLRBIT(sc, BGE_RDBDI_MODE, BGE_RBDIMODE_ENABLE);
BGE_CLRBIT(sc, BGE_RDC_MODE, BGE_RDCMODE_ENABLE);
BGE_CLRBIT(sc, BGE_RBDC_MODE, BGE_RBDCMODE_ENABLE);
/*
- * Disable all of the transmit blocks
+ * Disable all of the transmit blocks.
*/
BGE_CLRBIT(sc, BGE_SRS_MODE, BGE_SRSMODE_ENABLE);
BGE_CLRBIT(sc, BGE_SBDI_MODE, BGE_SBDIMODE_ENABLE);
BGE_CLRBIT(sc, BGE_SDI_MODE, BGE_SDIMODE_ENABLE);
BGE_CLRBIT(sc, BGE_RDMA_MODE, BGE_RDMAMODE_ENABLE);
BGE_CLRBIT(sc, BGE_SDC_MODE, BGE_SDCMODE_ENABLE);
- if (sc->bge_asicrev != BGE_ASICREV_BCM5705 &&
- sc->bge_asicrev != BGE_ASICREV_BCM5750)
+ if (!(BGE_IS_5705_PLUS(sc)))
BGE_CLRBIT(sc, BGE_DMAC_MODE, BGE_DMACMODE_ENABLE);
BGE_CLRBIT(sc, BGE_SBDC_MODE, BGE_SBDCMODE_ENABLE);
@@ -3628,13 +4029,11 @@
*/
BGE_CLRBIT(sc, BGE_HCC_MODE, BGE_HCCMODE_ENABLE);
BGE_CLRBIT(sc, BGE_WDMA_MODE, BGE_WDMAMODE_ENABLE);
- if (sc->bge_asicrev != BGE_ASICREV_BCM5705 &&
- sc->bge_asicrev != BGE_ASICREV_BCM5750)
+ if (!(BGE_IS_5705_PLUS(sc)))
BGE_CLRBIT(sc, BGE_MBCF_MODE, BGE_MBCFMODE_ENABLE);
CSR_WRITE_4(sc, BGE_FTQ_RESET, 0xFFFFFFFF);
CSR_WRITE_4(sc, BGE_FTQ_RESET, 0);
- if (sc->bge_asicrev != BGE_ASICREV_BCM5705 &&
- sc->bge_asicrev != BGE_ASICREV_BCM5750) {
+ if (!(BGE_IS_5705_PLUS(sc))) {
BGE_CLRBIT(sc, BGE_BMAN_MODE, BGE_BMANMODE_ENABLE);
BGE_CLRBIT(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE);
}
@@ -3646,14 +4045,26 @@
/*
* Tell firmware we're shutting down.
*/
- BGE_CLRBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP);
+
+ bge_stop_fw(sc);
+ bge_sig_pre_reset(sc, BGE_RESET_STOP);
+ bge_reset(sc);
+ bge_sig_legacy(sc, BGE_RESET_STOP);
+ bge_sig_post_reset(sc, BGE_RESET_STOP);
+
+ /*
+ * Keep the ASF firmware running if up.
+ */
+ if (sc->bge_asf_mode & ASF_STACKUP)
+ BGE_SETBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP);
+ else
+ BGE_CLRBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP);
/* Free the RX lists. */
bge_free_rx_ring_std(sc);
/* Free jumbo RX list. */
- if (sc->bge_asicrev != BGE_ASICREV_BCM5705 &&
- sc->bge_asicrev != BGE_ASICREV_BCM5750)
+ if (BGE_IS_JUMBO_CAPABLE(sc))
bge_free_rx_ring_jumbo(sc);
/* Free TX buffers. */
@@ -3664,7 +4075,7 @@
* unchanged so that things will be put back to normal when
* we bring the interface back up.
*/
- if (!sc->bge_tbi) {
+ if ((sc->bge_flags & BGE_FLAG_TBI) == 0) {
itmp = ifp->if_flags;
ifp->if_flags |= IFF_UP;
/*
@@ -3673,7 +4084,7 @@
if (mii != NULL) {
ifm = mii->mii_media.ifm_cur;
mtmp = ifm->ifm_media;
- ifm->ifm_media = IFM_ETHER|IFM_NONE;
+ ifm->ifm_media = IFM_ETHER | IFM_NONE;
mii_mediachg(mii);
ifm->ifm_media = mtmp;
}
@@ -3682,12 +4093,7 @@
sc->bge_tx_saved_considx = BGE_TXCONS_UNSET;
- /*
- * We can't just call bge_link_upd() cause chip is almost stopped so
- * bge_link_upd -> bge_tick_locked -> bge_stats_update sequence may
- * lead to hardware deadlock. So we just clearing MAC's link state
- * (PHY may still have link UP).
- */
+ /* Clear MAC's link state (PHY may still have link UP). */
if (bootverbose && sc->bge_link)
if_printf(sc->bge_ifp, "link DOWN\n");
sc->bge_link = 0;
@@ -3700,8 +4106,7 @@
* get confused by errant DMAs when rebooting.
*/
static void
-bge_shutdown(dev)
- device_t dev;
+bge_shutdown(device_t dev)
{
struct bge_softc *sc;
@@ -3711,8 +4116,6 @@
bge_stop(sc);
bge_reset(sc);
BGE_UNLOCK(sc);
-
- return;
}
static int
@@ -3748,15 +4151,14 @@
}
static void
-bge_link_upd(sc)
- struct bge_softc *sc;
+bge_link_upd(struct bge_softc *sc)
{
struct mii_data *mii;
uint32_t link, status;
BGE_LOCK_ASSERT(sc);
- /* Clear 'pending link event' flag */
+ /* Clear 'pending link event' flag. */
sc->bge_link_evt = 0;
/*
@@ -3771,17 +4173,15 @@
* the interrupt handler.
*
* XXX: perhaps link state detection procedure used for
- * BGE_CHIPID_BCM5700_B1 can be used for others BCM5700 revisions.
+ * BGE_CHIPID_BCM5700_B2 can be used for others BCM5700 revisions.
*/
if (sc->bge_asicrev == BGE_ASICREV_BCM5700 &&
- sc->bge_chipid != BGE_CHIPID_BCM5700_B1) {
+ sc->bge_chipid != BGE_CHIPID_BCM5700_B2) {
status = CSR_READ_4(sc, BGE_MAC_STS);
if (status & BGE_MACSTAT_MI_INTERRUPT) {
- callout_stop(&sc->bge_stat_ch);
- bge_tick_locked(sc);
-
mii = device_get_softc(sc->bge_miibus);
+ mii_pollstat(mii);
if (!sc->bge_link &&
mii->mii_media_status & IFM_ACTIVE &&
IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) {
@@ -3796,7 +4196,7 @@
if_printf(sc->bge_ifp, "link DOWN\n");
}
- /* Clear the interrupt */
+ /* Clear the interrupt. */
CSR_WRITE_4(sc, BGE_MAC_EVT_ENB,
BGE_EVTENB_MI_INTERRUPT);
bge_miibus_readreg(sc->bge_dev, 1, BRGPHY_MII_ISR);
@@ -3804,9 +4204,9 @@
BRGPHY_INTRS);
}
return;
- }
+ }
- if (sc->bge_tbi) {
+ if (sc->bge_flags & BGE_FLAG_TBI) {
status = CSR_READ_4(sc, BGE_MAC_STS);
if (status & BGE_MACSTAT_TBI_PCS_SYNCHED) {
if (!sc->bge_link) {
@@ -3817,7 +4217,8 @@
CSR_WRITE_4(sc, BGE_MAC_STS, 0xFFFFFFFF);
if (bootverbose)
if_printf(sc->bge_ifp, "link UP\n");
- if_link_state_change(sc->bge_ifp, LINK_STATE_UP);
+ if_link_state_change(sc->bge_ifp,
+ LINK_STATE_UP);
}
} else if (sc->bge_link) {
sc->bge_link = 0;
@@ -3825,9 +4226,8 @@
if_printf(sc->bge_ifp, "link DOWN\n");
if_link_state_change(sc->bge_ifp, LINK_STATE_DOWN);
}
- /* Discard link events for MII/GMII cards if MI auto-polling disabled */
} else if (CSR_READ_4(sc, BGE_MI_MODE) & BGE_MIMODE_AUTOPOLL) {
- /*
+ /*
* Some broken BCM chips have BGE_STATFLAG_LINKSTATE_CHANGED bit
* in status word always set. Workaround this bug by reading
* PHY link status directly.
@@ -3836,10 +4236,8 @@
if (link != sc->bge_link ||
sc->bge_asicrev == BGE_ASICREV_BCM5700) {
- callout_stop(&sc->bge_stat_ch);
- bge_tick_locked(sc);
-
mii = device_get_softc(sc->bge_miibus);
+ mii_pollstat(mii);
if (!sc->bge_link &&
mii->mii_media_status & IFM_ACTIVE &&
IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) {
@@ -3854,10 +4252,287 @@
if_printf(sc->bge_ifp, "link DOWN\n");
}
}
+ } else {
+ /*
+ * Discard link events for MII/GMII controllers
+ * if MI auto-polling is disabled.
+ */
}
- /* Clear the attention */
- CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED|
- BGE_MACSTAT_CFG_CHANGED|BGE_MACSTAT_MI_COMPLETE|
+ /* Clear the attention. */
+ CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED |
+ BGE_MACSTAT_CFG_CHANGED | BGE_MACSTAT_MI_COMPLETE |
BGE_MACSTAT_LINK_CHANGED);
}
+
+#define BGE_SYSCTL_STAT(sc, ctx, desc, parent, node, oid) \
+ SYSCTL_ADD_PROC(ctx, parent, OID_AUTO, oid, CTLTYPE_UINT|CTLFLAG_RD, \
+ sc, offsetof(struct bge_stats, node), bge_sysctl_stats, "IU", \
+ desc)
+
+static void
+bge_add_sysctls(struct bge_softc *sc)
+{
+ struct sysctl_ctx_list *ctx;
+ struct sysctl_oid_list *children, *schildren;
+ struct sysctl_oid *tree;
+
+ ctx = device_get_sysctl_ctx(sc->bge_dev);
+ children = SYSCTL_CHILDREN(device_get_sysctl_tree(sc->bge_dev));
+
+#ifdef BGE_REGISTER_DEBUG
+ SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "debug_info",
+ CTLTYPE_INT | CTLFLAG_RW, sc, 0, bge_sysctl_debug_info, "I",
+ "Debug Information");
+
+ SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "reg_read",
+ CTLTYPE_INT | CTLFLAG_RW, sc, 0, bge_sysctl_reg_read, "I",
+ "Register Read");
+
+ SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "mem_read",
+ CTLTYPE_INT | CTLFLAG_RW, sc, 0, bge_sysctl_mem_read, "I",
+ "Memory Read");
+
+#endif
+
+ if (BGE_IS_5705_PLUS(sc))
+ return;
+
+ tree = SYSCTL_ADD_NODE(ctx, children, OID_AUTO, "stats", CTLFLAG_RD,
+ NULL, "BGE Statistics");
+ schildren = children = SYSCTL_CHILDREN(tree);
+ BGE_SYSCTL_STAT(sc, ctx, "Frames Dropped Due To Filters",
+ children, COSFramesDroppedDueToFilters,
+ "FramesDroppedDueToFilters");
+ BGE_SYSCTL_STAT(sc, ctx, "NIC DMA Write Queue Full",
+ children, nicDmaWriteQueueFull, "DmaWriteQueueFull");
+ BGE_SYSCTL_STAT(sc, ctx, "NIC DMA Write High Priority Queue Full",
+ children, nicDmaWriteHighPriQueueFull, "DmaWriteHighPriQueueFull");
+ BGE_SYSCTL_STAT(sc, ctx, "NIC No More RX Buffer Descriptors",
+ children, nicNoMoreRxBDs, "NoMoreRxBDs");
+ BGE_SYSCTL_STAT(sc, ctx, "Discarded Input Frames",
+ children, ifInDiscards, "InputDiscards");
+ BGE_SYSCTL_STAT(sc, ctx, "Input Errors",
+ children, ifInErrors, "InputErrors");
+ BGE_SYSCTL_STAT(sc, ctx, "NIC Recv Threshold Hit",
+ children, nicRecvThresholdHit, "RecvThresholdHit");
+ BGE_SYSCTL_STAT(sc, ctx, "NIC DMA Read Queue Full",
+ children, nicDmaReadQueueFull, "DmaReadQueueFull");
+ BGE_SYSCTL_STAT(sc, ctx, "NIC DMA Read High Priority Queue Full",
+ children, nicDmaReadHighPriQueueFull, "DmaReadHighPriQueueFull");
+ BGE_SYSCTL_STAT(sc, ctx, "NIC Send Data Complete Queue Full",
+ children, nicSendDataCompQueueFull, "SendDataCompQueueFull");
+ BGE_SYSCTL_STAT(sc, ctx, "NIC Ring Set Send Producer Index",
+ children, nicRingSetSendProdIndex, "RingSetSendProdIndex");
+ BGE_SYSCTL_STAT(sc, ctx, "NIC Ring Status Update",
+ children, nicRingStatusUpdate, "RingStatusUpdate");
+ BGE_SYSCTL_STAT(sc, ctx, "NIC Interrupts",
+ children, nicInterrupts, "Interrupts");
+ BGE_SYSCTL_STAT(sc, ctx, "NIC Avoided Interrupts",
+ children, nicAvoidedInterrupts, "AvoidedInterrupts");
+ BGE_SYSCTL_STAT(sc, ctx, "NIC Send Threshold Hit",
+ children, nicSendThresholdHit, "SendThresholdHit");
+
+ tree = SYSCTL_ADD_NODE(ctx, schildren, OID_AUTO, "rx", CTLFLAG_RD,
+ NULL, "BGE RX Statistics");
+ children = SYSCTL_CHILDREN(tree);
+ BGE_SYSCTL_STAT(sc, ctx, "Inbound Octets",
+ children, rxstats.ifHCInOctets, "Octets");
+ BGE_SYSCTL_STAT(sc, ctx, "Fragments",
+ children, rxstats.etherStatsFragments, "Fragments");
+ BGE_SYSCTL_STAT(sc, ctx, "Inbound Unicast Packets",
+ children, rxstats.ifHCInUcastPkts, "UcastPkts");
+ BGE_SYSCTL_STAT(sc, ctx, "Inbound Multicast Packets",
+ children, rxstats.ifHCInMulticastPkts, "MulticastPkts");
+ BGE_SYSCTL_STAT(sc, ctx, "FCS Errors",
+ children, rxstats.dot3StatsFCSErrors, "FCSErrors");
+ BGE_SYSCTL_STAT(sc, ctx, "Alignment Errors",
+ children, rxstats.dot3StatsAlignmentErrors, "AlignmentErrors");
+ BGE_SYSCTL_STAT(sc, ctx, "XON Pause Frames Received",
+ children, rxstats.xonPauseFramesReceived, "xonPauseFramesReceived");
+ BGE_SYSCTL_STAT(sc, ctx, "XOFF Pause Frames Received",
+ children, rxstats.xoffPauseFramesReceived,
+ "xoffPauseFramesReceived");
+ BGE_SYSCTL_STAT(sc, ctx, "MAC Control Frames Received",
+ children, rxstats.macControlFramesReceived,
+ "ControlFramesReceived");
+ BGE_SYSCTL_STAT(sc, ctx, "XOFF State Entered",
+ children, rxstats.xoffStateEntered, "xoffStateEntered");
+ BGE_SYSCTL_STAT(sc, ctx, "Frames Too Long",
+ children, rxstats.dot3StatsFramesTooLong, "FramesTooLong");
+ BGE_SYSCTL_STAT(sc, ctx, "Jabbers",
+ children, rxstats.etherStatsJabbers, "Jabbers");
+ BGE_SYSCTL_STAT(sc, ctx, "Undersized Packets",
+ children, rxstats.etherStatsUndersizePkts, "UndersizePkts");
+ BGE_SYSCTL_STAT(sc, ctx, "Inbound Range Length Errors",
+ children, rxstats.inRangeLengthError, "inRangeLengthError");
+ BGE_SYSCTL_STAT(sc, ctx, "Outbound Range Length Errors",
+ children, rxstats.outRangeLengthError, "outRangeLengthError");
+
+ tree = SYSCTL_ADD_NODE(ctx, schildren, OID_AUTO, "tx", CTLFLAG_RD,
+ NULL, "BGE TX Statistics");
+ children = SYSCTL_CHILDREN(tree);
+ BGE_SYSCTL_STAT(sc, ctx, "Outbound Octets",
+ children, txstats.ifHCOutOctets, "Octets");
+ BGE_SYSCTL_STAT(sc, ctx, "TX Collisions",
+ children, txstats.etherStatsCollisions, "Collisions");
+ BGE_SYSCTL_STAT(sc, ctx, "XON Sent",
+ children, txstats.outXonSent, "XonSent");
+ BGE_SYSCTL_STAT(sc, ctx, "XOFF Sent",
+ children, txstats.outXoffSent, "XoffSent");
+ BGE_SYSCTL_STAT(sc, ctx, "Flow Control Done",
+ children, txstats.flowControlDone, "flowControlDone");
+ BGE_SYSCTL_STAT(sc, ctx, "Internal MAC TX errors",
+ children, txstats.dot3StatsInternalMacTransmitErrors,
+ "InternalMacTransmitErrors");
+ BGE_SYSCTL_STAT(sc, ctx, "Single Collision Frames",
+ children, txstats.dot3StatsSingleCollisionFrames,
+ "SingleCollisionFrames");
+ BGE_SYSCTL_STAT(sc, ctx, "Multiple Collision Frames",
+ children, txstats.dot3StatsMultipleCollisionFrames,
+ "MultipleCollisionFrames");
+ BGE_SYSCTL_STAT(sc, ctx, "Deferred Transmissions",
+ children, txstats.dot3StatsDeferredTransmissions,
+ "DeferredTransmissions");
+ BGE_SYSCTL_STAT(sc, ctx, "Excessive Collisions",
+ children, txstats.dot3StatsExcessiveCollisions,
+ "ExcessiveCollisions");
+ BGE_SYSCTL_STAT(sc, ctx, "Late Collisions",
+ children, txstats.dot3StatsLateCollisions,
+ "LateCollisions");
+ BGE_SYSCTL_STAT(sc, ctx, "Outbound Unicast Packets",
+ children, txstats.ifHCOutUcastPkts, "UcastPkts");
+ BGE_SYSCTL_STAT(sc, ctx, "Outbound Multicast Packets",
+ children, txstats.ifHCOutMulticastPkts, "MulticastPkts");
+ BGE_SYSCTL_STAT(sc, ctx, "Outbound Broadcast Packets",
+ children, txstats.ifHCOutBroadcastPkts, "BroadcastPkts");
+ BGE_SYSCTL_STAT(sc, ctx, "Carrier Sense Errors",
+ children, txstats.dot3StatsCarrierSenseErrors,
+ "CarrierSenseErrors");
+ BGE_SYSCTL_STAT(sc, ctx, "Outbound Discards",
+ children, txstats.ifOutDiscards, "Discards");
+ BGE_SYSCTL_STAT(sc, ctx, "Outbound Errors",
+ children, txstats.ifOutErrors, "Errors");
+}
+
+static int
+bge_sysctl_stats(SYSCTL_HANDLER_ARGS)
+{
+ struct bge_softc *sc;
+ uint32_t result;
+ int offset;
+
+ sc = (struct bge_softc *)arg1;
+ offset = arg2;
+ result = CSR_READ_4(sc, BGE_MEMWIN_START + BGE_STATS_BLOCK + offset +
+ offsetof(bge_hostaddr, bge_addr_lo));
+ return (sysctl_handle_int(oidp, &result, 0, req));
+}
+
+#ifdef BGE_REGISTER_DEBUG
+static int
+bge_sysctl_debug_info(SYSCTL_HANDLER_ARGS)
+{
+ struct bge_softc *sc;
+ uint16_t *sbdata;
+ int error;
+ int result;
+ int i, j;
+
+ result = -1;
+ error = sysctl_handle_int(oidp, &result, 0, req);
+ if (error || (req->newptr == NULL))
+ return (error);
+
+ if (result == 1) {
+ sc = (struct bge_softc *)arg1;
+
+ sbdata = (uint16_t *)sc->bge_ldata.bge_status_block;
+ printf("Status Block:\n");
+ for (i = 0x0; i < (BGE_STATUS_BLK_SZ / 4); ) {
+ printf("%06x:", i);
+ for (j = 0; j < 8; j++) {
+ printf(" %04x", sbdata[i]);
+ i += 4;
+ }
+ printf("\n");
+ }
+
+ printf("Registers:\n");
+ for (i = 0x800; i < 0xA00; ) {
+ printf("%06x:", i);
+ for (j = 0; j < 8; j++) {
+ printf(" %08x", CSR_READ_4(sc, i));
+ i += 4;
+ }
+ printf("\n");
+ }
+
+ printf("Hardware Flags:\n");
+ if (BGE_IS_575X_PLUS(sc))
+ printf(" - 575X Plus\n");
+ if (BGE_IS_5705_PLUS(sc))
+ printf(" - 5705 Plus\n");
+ if (BGE_IS_5714_FAMILY(sc))
+ printf(" - 5714 Family\n");
+ if (BGE_IS_5700_FAMILY(sc))
+ printf(" - 5700 Family\n");
+ if (sc->bge_flags & BGE_FLAG_JUMBO)
+ printf(" - Supports Jumbo Frames\n");
+ if (sc->bge_flags & BGE_FLAG_PCIX)
+ printf(" - PCI-X Bus\n");
+ if (sc->bge_flags & BGE_FLAG_PCIE)
+ printf(" - PCI Express Bus\n");
+ if (sc->bge_flags & BGE_FLAG_NO_3LED)
+ printf(" - No 3 LEDs\n");
+ if (sc->bge_flags & BGE_FLAG_RX_ALIGNBUG)
+ printf(" - RX Alignment Bug\n");
+ }
+
+ return (error);
+}
+
+static int
+bge_sysctl_reg_read(SYSCTL_HANDLER_ARGS)
+{
+ struct bge_softc *sc;
+ int error;
+ uint16_t result;
+ uint32_t val;
+
+ result = -1;
+ error = sysctl_handle_int(oidp, &result, 0, req);
+ if (error || (req->newptr == NULL))
+ return (error);
+
+ if (result < 0x8000) {
+ sc = (struct bge_softc *)arg1;
+ val = CSR_READ_4(sc, result);
+ printf("reg 0x%06X = 0x%08X\n", result, val);
+ }
+
+ return (error);
+}
+
+static int
+bge_sysctl_mem_read(SYSCTL_HANDLER_ARGS)
+{
+ struct bge_softc *sc;
+ int error;
+ uint16_t result;
+ uint32_t val;
+
+ result = -1;
+ error = sysctl_handle_int(oidp, &result, 0, req);
+ if (error || (req->newptr == NULL))
+ return (error);
+
+ if (result < 0x8000) {
+ sc = (struct bge_softc *)arg1;
+ val = bge_readmem_ind(sc, result);
+ printf("mem 0x%06X = 0x%08X\n", result, val);
+ }
+
+ return (error);
+}
+#endif
More information about the Midnightbsd-cvs
mailing list