[Midnightbsd-cvs] src [8361] trunk/sys/dev/usb/controller: update const

[laffer1 at midnightbsd.org]

Revision: 8361
          http://svnweb.midnightbsd.org/src/?rev=8361
Author:   laffer1
Date:     2016-09-18 14:49:55 -0400 (Sun, 18 Sep 2016)
Log Message:
-----------
update const

Modified Paths:
--------------
    trunk/sys/dev/usb/controller/xhci.h
    trunk/sys/dev/usb/controller/xhcireg.h

Modified: trunk/sys/dev/usb/controller/xhci.h
===================================================================
--- trunk/sys/dev/usb/controller/xhci.h	2016-09-18 18:39:56 UTC (rev 8360)
+++ trunk/sys/dev/usb/controller/xhci.h	2016-09-18 18:49:55 UTC (rev 8361)
@@ -30,7 +30,7 @@
 
 #define	XHCI_MAX_DEVICES	MIN(USB_MAX_DEVICES, 128)
 #define	XHCI_MAX_ENDPOINTS	32	/* hardcoded - do not change */
-#define	XHCI_MAX_SCRATCHPADS	32
+#define	XHCI_MAX_SCRATCHPADS	256
 #define	XHCI_MAX_EVENTS		(16 * 13)
 #define	XHCI_MAX_COMMANDS	(16 * 1)
 #define	XHCI_MAX_RSEG		1

Modified: trunk/sys/dev/usb/controller/xhcireg.h
===================================================================
--- trunk/sys/dev/usb/controller/xhcireg.h	2016-09-18 18:39:56 UTC (rev 8360)
+++ trunk/sys/dev/usb/controller/xhcireg.h	2016-09-18 18:49:55 UTC (rev 8361)
@@ -35,7 +35,9 @@
 #define	PCI_XHCI_FLADJ		0x61	/* RW frame length adjust */
 
 #define	PCI_XHCI_INTEL_XUSB2PR	0xD0	/* Intel USB2 Port Routing */
+#define	PCI_XHCI_INTEL_USB2PRM	0xD4	/* Intel USB2 Port Routing Mask */
 #define	PCI_XHCI_INTEL_USB3_PSSEN 0xD8	/* Intel USB3 Port SuperSpeed Enable */
+#define	PCI_XHCI_INTEL_USB3PRM	0xDC	/* Intel USB3 Port Routing Mask */
 
 /* XHCI capability registers */
 #define	XHCI_CAPLENGTH		0x00	/* RO capability */
@@ -50,8 +52,8 @@
 #define	XHCI_HCSPARAMS2		0x08	/* RO structual parameters 2 */
 #define	XHCI_HCS2_IST(x)	((x) & 0xF)
 #define	XHCI_HCS2_ERST_MAX(x)	(((x) >> 4) & 0xF)
-#define	XHCI_HCS2_SPR(x)	(((x) >> 24) & 0x1)
-#define	XHCI_HCS2_SPB_MAX(x)	(((x) >> 27) & 0x7F)
+#define	XHCI_HCS2_SPR(x)	(((x) >> 26) & 0x1)
+#define	XHCI_HCS2_SPB_MAX(x)	((((x) >> 16) & 0x3E0) | (((x) >> 27) & 0x1F))
 #define	XHCI_HCSPARAMS3		0x0C	/* RO structual parameters 3 */
 #define	XHCI_HCS3_U1_DEL(x)	((x) & 0xFF)
 #define	XHCI_HCS3_U2_DEL(x)	(((x) >> 16) & 0xFFFF)
@@ -166,7 +168,8 @@
 #define	XHCI_IMOD_IVAL_SET(x)	(((x) & 0xFFFF) << 0)	/* 250ns unit */
 #define	XHCI_IMOD_ICNT_GET(x)	(((x) >> 16) & 0xFFFF)	/* 250ns unit */
 #define	XHCI_IMOD_ICNT_SET(x)	(((x) & 0xFFFF) << 16)	/* 250ns unit */
-#define	XHCI_IMOD_DEFAULT	0x000003E8U	/* 8000 IRQ/second */
+#define	XHCI_IMOD_DEFAULT	0x000001F4U	/* 8000 IRQs/second */
+#define	XHCI_IMOD_DEFAULT_LP 	0x000003F8U	/* 4000 IRQs/second - LynxPoint */
 #define	XHCI_ERSTSZ(n)		(0x0028 + (0x20 * (n)))	/* XHCI event ring segment table size */
 #define	XHCI_ERSTS_GET(x)	((x) & 0xFFFF)
 #define	XHCI_ERSTS_SET(x)	((x) & 0xFFFF)