cad/surelog
SystemVerilog 2017 Pre-processor, Parser, Elaborator, etc
| Flavor | Version | Run | OSVersion | Arch | License | Restricted | Build | Fetch | Test | Scan | |
|---|---|---|---|---|---|---|---|---|---|---|---|
| 1.84_1 | 641 | 4.0 | i386 | Apache-2.0 | 0 | skip | skip | skip | skip | Reset Port |
License Permissions: dist-mirror dist-sell pkg-mirror pkg-sell auto-accept
Events
| Machine | Phase | Type | Time | Message |
|---|---|---|---|---|
| master | build | skip | 2026-06-02 16:41:54.573598 | is marked as broken on i386: compilation fails: conversion function cannot be redeclared, see https://github.com/chipsalliance/Surelog/issues/3206 |
Links
Depends On
- devel/cmake-core (build)
- devel/googletest (build)
- devel/ninja (build)
- devel/py-orderedmultidict (build)
- devel/swig (build)
- devel/utf8cpp (build)
- java/openjdk17-bin (build)
- lang/python311 (build)
- lang/tcl86 (build)
- cad/uhdm (lib)
- devel/capnproto (lib)
- devel/google-perftools (lib)
- lang/python311 (run)
- lang/python311 (test)
Depend Of
NothingCategories
CVEs
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