MidnightBSD Maguscad/verilator
Synthesizable Verilog to C++ compiler
| Flavor | Version | Run | OSVersion | Arch | License | Restricted | Build | Fetch | Test | Scan | |
|---|---|---|---|---|---|---|---|---|---|---|---|
| 5.026_1 | 642 | 4.1 | amd64 | gpl3 | 0 | warn | pass | pass | warn |
License Permissions: dist-mirror dist-sell pkg-mirror pkg-sell auto-accept
Events
| Machine | Phase | Type | Time | Message |
|---|---|---|---|---|
| m4164b | fetch | info | 2026-07-06 06:14:17.610073 | Fetch Started |
| m4164b | fetch | pass | 2026-07-06 06:14:23.811341 | Fetch complete. |
| m4164b | build | info | 2026-07-08 07:45:42.041557 | Build Started |
| m4164b | build | warn | 2026-07-08 08:09:51.071111 | fake-qa reported: you might not need LIB_DEPENDS on libsystemc.so |
| m4164b | build | warn | 2026-07-08 08:11:03.316564 | Build complete. |
| m4164b | scan | info | 2026-07-12 12:20:42.69852 | Scan Started |
| m4164b | scan | fail | 2026-07-12 12:20:42.728863 | Virus scan found a problem. |
| m4164b | scan | internal | 2026-07-12 12:20:42.758222 | Exception thrown: open3: exec of yara /usr/magus/slave-data/mports/Tools/magus/yara/mports-shell.yar /usr/mports/cad/verilator/Makefile /usr/mports/cad/verilator/files/patch-src-verilog.y failed: No such file or directory at /usr/magus/slave-data/mports/Tools/magus/slave/../../lib/Magus/App/Slave/Worker.pm line 931. |
| m4164b | scan | info | 2026-07-20 05:51:14.118866 | Scan Started |
| m4164b | scan | info | 2026-07-20 05:51:33.775774 | Virus scan passed. |
| m4164b | scan | warn | 2026-07-20 05:51:33.80757 | YARA found suspicious port shell content. |
| m4164b | scan | warn | 2026-07-20 05:51:39.374464 | USE_GITHUB resolves to non-immutable-looking GH_TAGNAME: v5.026 |
| m4164b | scan | warn | 2026-07-20 05:51:39.40027 | Scan complete. |
| m4164b | test | info | 2026-07-21 11:42:37.901203 | Test Started |
| m4164b | test | pass | 2026-07-21 12:10:13.539759 | Test complete. |
scan Log
== ClamAV package scan == /mnt/magus/packages/642/verilator-5.026_1.mport: OK == YARA port-file scan == /usr/mports/cad/verilator/Makefile(1): error: syntax error, unexpected identifier /usr/mports/cad/verilator/Makefile(13): error: unterminated regular expression == Source integrity scan == Compared cad/verilator between df708ba31ff0dac565750f8e8ea7d2b702ae7963 and 028f5c35b717a0aa8460c3c4b96c7495cad12dee. Changed files: cad/verilator/Makefile Warnings: SourceIntegrityMutableGithubTag: USE_GITHUB resolves to non-immutable-looking GH_TAGNAME: v5.026
Links
Depends On
- devel/autoconf (build)
- devel/binutils (build)
- devel/bison (build)
- devel/gmake (build)
- lang/perl5.40 (build)
- lang/python312 (build)
- misc/help2man (build)
- shells/bash (build)
- devel/systemc (lib)
- devel/binutils (run)
- devel/gmake (run)
- lang/perl5.40 (run)
- lang/python312 (run)
- lang/python312 (test)
Depend Of
Categories
CVEs
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