MidnightBSD Magus

cad/gplcver

Verilog HDL simulator

Flavor Version Run OSVersion Arch License Restricted Build Fetch Test Scan
2.12.a 643 4.1 i386 gpl2 0 warn pass untested warn Reset Port

License Permissions: dist-mirror dist-sell pkg-mirror pkg-sell auto-accept

Events

Machine Phase Type Time Message
m4132 fetch info 2026-07-19 02:37:03.859788 Fetch Started
m4132 fetch pass 2026-07-19 02:37:07.940169 Fetch complete.
m4132 build info 2026-07-20 00:08:54.043073 Build Started
m4132 build warn 2026-07-20 00:09:04.432858 MASTER_SITES contains non-HTTPS URLs: http://downloads.sourceforge.net/project/gplcver/gplcver/2.12a/, http://cfhcable.dl.sourceforge.net/project/gplcver/gplcver/2.12a/, http://cytranet.dl.sourceforge.net/project/gplcver/gplcver/2.12a/, http://deac-ams.dl.sourceforge.net/project/gplcver/gplcver/2.12a/, http://deac-fra.dl.sourceforge.net/project/gplcver/gplcver/2.12a/ and 19 more
m4132 build warn 2026-07-20 00:09:04.714509 Build complete.
m4132 scan info 2026-07-21 03:29:20.430861 Scan Started
m4132 scan info 2026-07-21 03:29:38.22683 Virus scan passed.
m4132 scan warn 2026-07-21 03:29:38.270825 YARA found suspicious port shell content.
m4132 scan info 2026-07-21 03:29:38.56181 Source integrity scan passed.
m4132 scan warn 2026-07-21 03:29:38.587548 Scan complete.

scan Log

== ClamAV package scan ==
/mnt/magus/packages/643/gplcver-2.12.a.mport: OK

== YARA port-file scan ==
/usr/mports/cad/gplcver/Makefile(1): error: syntax error, unexpected identifier
/usr/mports/cad/gplcver/Makefile(16): error: unterminated regular expression

== Source integrity scan ==
Compared cad/gplcver between 70edcb85ec50f0f11f83cbb7af2b1a051439152a and 177ae033a7ad8459e5e20760b547a2b46a0c1e79.
Changed files:
  cad/gplcver/Makefile
No source integrity warnings.

Links

Depends On

Depend Of

Nothing

Categories

CVEs

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LLM Analysis