MidnightBSD Magus

cad/iverilog

Verilog simulation and synthesis tool

Flavor Version Run OSVersion Arch License Restricted Build Fetch Test Scan
12.0_1 646 4.1 amd64 gpl2 0 pass pass untested warn Reset Port

License Permissions: dist-mirror dist-sell pkg-mirror pkg-sell auto-accept

Events

Machine Phase Type Time Message
m4164 fetch info 2026-08-07 19:03:10.015211 Fetch Started
m4164 fetch pass 2026-08-07 19:03:14.292361 Fetch complete.
m4164b build info 2026-08-10 00:57:26.346955 Build Started
m4164b build pass 2026-08-10 00:59:26.313309 Build complete.
m4164b scan info 2026-08-15 14:35:03.276673 Scan Started
m4164b scan info 2026-08-15 14:35:20.432911 Virus scan passed.
m4164b scan info 2026-08-15 14:35:20.470789 YARA scan passed.
m4164b scan warn 2026-08-15 14:35:25.265481 USE_GITHUB resolves to non-immutable-looking GH_TAGNAME: v12_0
m4164b scan warn 2026-08-15 14:35:25.290425 Scan complete.

scan Log

== ClamAV package scan ==
/mnt/magus/packages/646/iverilog-12.0_1.mport: OK

== YARA port-file scan ==
No YARA matches.

== Source integrity scan ==
Compared cad/iverilog between 60b86f7714364c0e1a4411b214735dc6df5c236a and c8f81094d01e568b4d50d0898787ca34889bbdb7.
Changed files:
  cad/iverilog/Makefile
  cad/iverilog/distinfo
  cad/iverilog/pkg-descr
  cad/iverilog/pkg-plist
Warnings:
  SourceIntegrityMutableGithubTag: USE_GITHUB resolves to non-immutable-looking GH_TAGNAME: v12_0

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LLM Analysis