[Midnightbsd-cvs] src: sys/netinet: Syncronize the cpu detection code on i386 and amd64

laffer1 at midnightbsd.org laffer1 at midnightbsd.org
Sat May 17 01:36:07 EDT 2008


Log Message:
-----------
Syncronize the cpu detection code on i386 and amd64 with FreeBSD 6.2.

Add better SMP detection including multicore cpus.  Detect features on newer processors and initialize them properly.  Add support for some newer via c7 cpus.

Also make a subtle adjustment to tcp_syncache.c (unrelated)

Modified Files:
--------------
    src/sys/amd64/amd64:
        identcpu.c (r1.1.1.2 -> r1.2)
        initcpu.c (r1.1.1.1 -> r1.2)
    src/sys/amd64/include:
        md_var.h (r1.1.1.1 -> r1.2)
        specialreg.h (r1.1.1.1 -> r1.2)
    src/sys/i386/i386:
        identcpu.c (r1.2 -> r1.3)
        initcpu.c (r1.2 -> r1.3)
    src/sys/i386/include:
        md_var.h (r1.2 -> r1.3)
        specialreg.h (r1.1.1.1 -> r1.2)
    src/sys/netinet:
        tcp_syncache.c (r1.7 -> r1.8)

-------------- next part --------------
Index: specialreg.h
===================================================================
RCS file: /home/cvs/src/sys/amd64/include/specialreg.h,v
retrieving revision 1.1.1.1
retrieving revision 1.2
diff -L sys/amd64/include/specialreg.h -L sys/amd64/include/specialreg.h -u -r1.1.1.1 -r1.2
--- sys/amd64/include/specialreg.h
+++ sys/amd64/include/specialreg.h
@@ -27,7 +27,7 @@
  * SUCH DAMAGE.
  *
  *	from: @(#)specialreg.h	7.1 (Berkeley) 5/9/91
- * $FreeBSD: src/sys/amd64/include/specialreg.h,v 1.30 2004/06/08 01:02:52 peter Exp $
+ * $FreeBSD: src/sys/amd64/include/specialreg.h,v 1.30.8.1 2006/04/24 18:21:54 jkim Exp $
  */
 
 #ifndef _MACHINE_SPECIALREG_H_
@@ -126,7 +126,16 @@
 #define AMDID_SYSCALL	0x00000800
 #define AMDID_MP	0x00080000
 #define AMDID_NX	0x00100000
+#define AMDID_EXT_MMX	0x00400000
+#define AMDID_FFXSR	0x01000000
+#define AMDID_RDTSCP	0x08000000
 #define AMDID_LM	0x20000000
+#define AMDID_EXT_3DNOW	0x40000000
+#define AMDID_3DNOW	0x80000000
+
+#define AMDID2_LAHF	0x00000001
+#define AMDID2_CMP	0x00000002
+#define AMDID2_CR8	0x00000010
 
 /*
  * CPUID instruction 1 ebx info
@@ -137,6 +146,11 @@
 #define	CPUID_LOCAL_APIC_ID	0xff000000
 
 /*
+ * AMD extended function 8000_0008h ecx info
+ */
+#define AMDID_CMP_CORES		0x000000ff
+
+/*
  * Model-specific registers for the i386 family
  */
 #define MSR_P5_MC_ADDR		0x000
@@ -198,14 +212,14 @@
 #define MSR_MC2_STATUS		0x409
 #define MSR_MC2_ADDR		0x40a
 #define MSR_MC2_MISC		0x40b
-#define MSR_MC4_CTL		0x40c
-#define MSR_MC4_STATUS		0x40d
-#define MSR_MC4_ADDR		0x40e
-#define MSR_MC4_MISC		0x40f
-#define MSR_MC3_CTL		0x410
-#define MSR_MC3_STATUS		0x411
-#define MSR_MC3_ADDR		0x412
-#define MSR_MC3_MISC		0x413
+#define MSR_MC3_CTL		0x40c
+#define MSR_MC3_STATUS		0x40d
+#define MSR_MC3_ADDR		0x40e
+#define MSR_MC3_MISC		0x40f
+#define MSR_MC4_CTL		0x410
+#define MSR_MC4_STATUS		0x411
+#define MSR_MC4_ADDR		0x412
+#define MSR_MC4_MISC		0x413
 
 /*
  * Constants related to MSR's.
Index: md_var.h
===================================================================
RCS file: /home/cvs/src/sys/amd64/include/md_var.h,v
retrieving revision 1.1.1.1
retrieving revision 1.2
diff -L sys/amd64/include/md_var.h -L sys/amd64/include/md_var.h -u -r1.1.1.1 -r1.2
--- sys/amd64/include/md_var.h
+++ sys/amd64/include/md_var.h
@@ -26,7 +26,7 @@
  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  * SUCH DAMAGE.
  *
- * $FreeBSD: src/sys/amd64/include/md_var.h,v 1.75 2004/06/10 20:30:55 jhb Exp $
+ * $FreeBSD: src/sys/amd64/include/md_var.h,v 1.75.8.3 2006/07/24 23:28:08 peter Exp $
  */
 
 #ifndef _MACHINE_MD_VAR_H_
@@ -43,14 +43,19 @@
 extern	u_int	cpu_feature;
 extern	u_int	cpu_feature2;
 extern	u_int	amd_feature;
+extern	u_int	amd_feature2;
 extern	u_int	cpu_fxsr;
 extern	u_int	cpu_high;
 extern	u_int	cpu_id;
+extern	u_int	cpu_mxcsr_mask;
 extern	u_int	cpu_procinfo;
+extern	u_int	cpu_procinfo2;
 extern	char	cpu_vendor[];
 extern	char	kstack[];
 extern	char	sigcode[];
 extern	int	szsigcode;
+extern	uint64_t *vm_page_dump;
+extern	int	vm_page_dump_size;
 
 extern	struct pcpu __pcpu[];
 
@@ -59,11 +64,14 @@
 struct	reg;
 struct	fpreg;
 struct  dbreg;
+struct	dumperinfo;
 
 void	busdma_swi(void);
 void	cpu_setregs(void);
 void	doreti_iret(void) __asm(__STRING(doreti_iret));
 void	doreti_iret_fault(void) __asm(__STRING(doreti_iret_fault));
+void	dump_add_page(vm_paddr_t);
+void	dump_drop_page(vm_paddr_t);
 void	initializecpu(void);
 void	fillw(int /*u_short*/ pat, void *base, size_t cnt);
 void	fpstate_drop(struct thread *td);
@@ -73,5 +81,6 @@
 void	pagezero(void *addr);
 void	setidt(int idx, alias_for_inthand_t *func, int typ, int dpl, int ist);
 int	user_dbreg_trap(void);
+void	minidumpsys(struct dumperinfo *);
 
 #endif /* !_MACHINE_MD_VAR_H_ */
Index: initcpu.c
===================================================================
RCS file: /home/cvs/src/sys/i386/i386/initcpu.c,v
retrieving revision 1.2
retrieving revision 1.3
diff -L sys/i386/i386/initcpu.c -L sys/i386/i386/initcpu.c -u -r1.2 -r1.3
--- sys/i386/i386/initcpu.c
+++ sys/i386/i386/initcpu.c
@@ -28,7 +28,7 @@
  */
 
 #include <sys/cdefs.h>
-__FBSDID("$FreeBSD: src/sys/i386/i386/initcpu.c,v 1.52 2005/07/02 20:06:43 delphij Exp $");
+__FBSDID("$FreeBSD: src/sys/i386/i386/initcpu.c,v 1.52.2.3 2006/07/21 15:12:02 mr Exp $");
 
 #include "opt_cpu.h"
 
@@ -77,12 +77,21 @@
 int	cpu = 0;		/* Are we 386, 386sx, 486, etc? */
 u_int	cpu_feature = 0;	/* Feature flags */
 u_int	cpu_feature2 = 0;	/* Feature flags */
-u_int	amd_feature = 0;	/* Feature flags */
+u_int	amd_feature = 0;	/* AMD feature flags */
+u_int	amd_feature2 = 0;	/* AMD feature flags */
+u_int	via_feature_rng = 0;	/* VIA RNG features */
+u_int	via_feature_xcrypt = 0;	/* VIA ACE features */
 u_int	cpu_high = 0;		/* Highest arg to CPUID */
 u_int	cpu_id = 0;		/* Stepping ID */
 u_int	cpu_procinfo = 0;	/* HyperThreading Info / Brand Index / CLFUSH */
+u_int	cpu_procinfo2 = 0;	/* Multicore info */
 char	cpu_vendor[20] = "";	/* CPU Origin code */
 
+SYSCTL_UINT(_hw, OID_AUTO, via_feature_rng, CTLFLAG_RD,
+	&via_feature_rng, 0, "VIA C3/C7 RNG feature available in CPU");
+SYSCTL_UINT(_hw, OID_AUTO, via_feature_xcrypt, CTLFLAG_RD,
+	&via_feature_xcrypt, 0, "VIA C3/C7 xcrypt feature available in CPU");
+
 #ifdef CPU_ENABLE_SSE
 u_int	cpu_fxsr;		/* SSE enabled */
 u_int	cpu_mxcsr_mask;		/* valid bits in mxcsr */
@@ -524,6 +533,70 @@
 #endif /* CPU_PPRO2CELERON */
 }
 
+/*
+ * Initialize special VIA C3/C7 features
+ */
+static void
+init_via(void)
+{
+	u_int regs[4], val;
+	u_int64_t msreg;
+
+	do_cpuid(0xc0000000, regs);
+	val = regs[0];
+	if (val >= 0xc0000001) {
+		do_cpuid(0xc0000001, regs);
+		val = regs[3];
+	} else
+		val = 0;
+
+	/* Enable RNG if present and disabled */
+	if (val & VIA_CPUID_HAS_RNG) {
+		if (!(val & VIA_CPUID_DO_RNG)) {
+			msreg = rdmsr(0x110B);
+			msreg |= 0x40;
+			wrmsr(0x110B, msreg);
+		}
+		via_feature_rng = VIA_HAS_RNG;
+	}
+	/* Enable AES engine if present and disabled */
+	if (val & VIA_CPUID_HAS_ACE) {
+		if (!(val & VIA_CPUID_DO_ACE)) {
+			msreg = rdmsr(0x1107);
+			msreg |= (0x01 << 28);
+			wrmsr(0x1107, msreg);
+		}
+		via_feature_xcrypt |= VIA_HAS_AES;
+	}
+	/* Enable ACE2 engine if present and disabled */
+	if (val & VIA_CPUID_HAS_ACE2) {
+		if (!(val & VIA_CPUID_DO_ACE2)) {
+			msreg = rdmsr(0x1107);
+			msreg |= (0x01 << 28);
+			wrmsr(0x1107, msreg);
+		}
+		via_feature_xcrypt |= VIA_HAS_AESCTR;
+	}
+	/* Enable SHA engine if present and disabled */
+	if (val & VIA_CPUID_HAS_PHE) {
+		if (!(val & VIA_CPUID_DO_PHE)) {
+			msreg = rdmsr(0x1107);
+			msreg |= (0x01 << 28/**/);
+			wrmsr(0x1107, msreg);
+		}
+		via_feature_xcrypt |= VIA_HAS_SHA;
+	}
+	/* Enable MM engine if present and disabled */
+	if (val & VIA_CPUID_HAS_PMM) {
+		if (!(val & VIA_CPUID_DO_PMM)) {
+			msreg = rdmsr(0x1107);
+			msreg |= (0x01 << 28/**/);
+			wrmsr(0x1107, msreg);
+		}
+		via_feature_xcrypt |= VIA_HAS_MM;
+	}
+}
+
 #endif /* I686_CPU */
 
 /*
@@ -600,6 +673,18 @@
 				cpu_feature = regs[3];
 			}
 #endif
+		} else if (strcmp(cpu_vendor, "CentaurHauls") == 0) {
+			switch (cpu_id & 0xff0) {
+			case 0x690:
+				if ((cpu_id & 0xf) < 3)
+					break;
+				/* fall through. */
+			case 0x6a0:
+				init_via();
+				break;
+			default:
+				break;
+			}
 		}
 		break;
 #endif
Index: identcpu.c
===================================================================
RCS file: /home/cvs/src/sys/i386/i386/identcpu.c,v
retrieving revision 1.2
retrieving revision 1.3
diff -L sys/i386/i386/identcpu.c -L sys/i386/i386/identcpu.c -u -r1.2 -r1.3
--- sys/i386/i386/identcpu.c
+++ sys/i386/i386/identcpu.c
@@ -39,8 +39,8 @@
  */
 
 #include <sys/cdefs.h>
-/*$FreeBSD: src/sys/i386/i386/identcpu.c,v 1.145.2.2 2006/02/23 15:03:42 dwmalone Exp $ */
-__MBSDID("$MIdnightBSD$");
+/*$FreeBSD: src/sys/i386/i386/identcpu.c,v 1.145.2.5 2006/08/08 08:41:34 mr Exp $ */
+__MBSDID("$MidnightBSD$");
 
 #include "opt_cpu.h"
 
@@ -174,11 +174,17 @@
 	}
 
 	/* Detect AMD features (PTE no-execute bit, 3dnow, 64 bit mode etc) */
-	if (cpu_exthigh >= 0x80000001 &&
-	    (strcmp(cpu_vendor, "GenuineIntel") == 0 ||
-	     strcmp(cpu_vendor, "AuthenticAMD") == 0)) {
-		do_cpuid(0x80000001, regs);
-		amd_feature = regs[3] & ~(cpu_feature & 0x0183f3ff);
+	if (strcmp(cpu_vendor, "GenuineIntel") == 0 ||
+	    strcmp(cpu_vendor, "AuthenticAMD") == 0) {
+		if (cpu_exthigh >= 0x80000001) {
+			do_cpuid(0x80000001, regs);
+			amd_feature = regs[3] & ~(cpu_feature & 0x0183f3ff);
+			amd_feature2 = regs[2];
+		}
+		if (cpu_exthigh >= 0x80000008) {
+			do_cpuid(0x80000008, regs);
+			cpu_procinfo2 = regs[2];
+		}
 	}
 
 	if (strcmp(cpu_vendor, "GenuineIntel") == 0) {
@@ -554,16 +560,33 @@
 			break;
 		case 0x690:
 			strcpy(cpu_model, "VIA C3 Nehemiah");
+			if ((cpu_id & 0xf) < 3)
+				break;
+			goto via_common;
+		case 0x6a0:
+			strcpy(cpu_model, "VIA C7 Esther");
+via_common:
 			do_cpuid(0xc0000000, regs);
-			if (regs[0] == 0xc0000001) {
+			i = regs[0];
+			if (i >= 0xC0000001) {
 				do_cpuid(0xc0000001, regs);
-				if ((cpu_id & 0xf) >= 3)
-					if ((regs[3] & 0x0c) == 0x0c)
-						strcat(cpu_model, "+RNG");
-				if ((cpu_id & 0xf) >= 8)
-					if ((regs[3] & 0xc0) == 0xc0)
-						strcat(cpu_model, "+ACE");
-			}
+				i = regs[3];
+			} else
+				i = 0;
+			if (i & VIA_CPUID_HAS_RNG)
+				strcat(cpu_model, "+RNG");
+
+			if (i & VIA_CPUID_HAS_ACE)
+				strcat(cpu_model, "+AES");
+
+			if (i & VIA_CPUID_HAS_ACE2)
+				strcat(cpu_model, "+AES-CTR");
+
+			if (i & VIA_CPUID_HAS_PHE)
+				strcat(cpu_model, "+SHA1+SHA256");
+
+			if (i & VIA_CPUID_HAS_PMM)
+				strcat(cpu_model, "+RSA");
 			break;
 		default:
 			strcpy(cpu_model, "VIA/IDT Unknown");
@@ -612,18 +635,18 @@
 #if defined(I586_CPU)
 	case CPUCLASS_586:
 		hw_clockrate = (tsc_freq + 5000) / 1000000;
-		printf("%lld.%02lld-MHz ",
-		       (tsc_freq + 4999LL) / 1000000LL,
-		       ((tsc_freq + 4999LL) / 10000LL) % 100LL);
+		printf("%jd.%02d-MHz ",
+		       (intmax_t)(tsc_freq + 4999) / 1000000,
+		       (u_int)((tsc_freq + 4999) / 10000) % 100);
 		printf("586");
 		break;
 #endif
 #if defined(I686_CPU)
 	case CPUCLASS_686:
 		hw_clockrate = (tsc_freq + 5000) / 1000000;
-		printf("%lld.%02lld-MHz ",
-		       (tsc_freq + 4999LL) / 1000000LL,
-		       ((tsc_freq + 4999LL) / 10000LL) % 100LL);
+		printf("%jd.%02d-MHz ",
+		       (intmax_t)(tsc_freq + 4999) / 1000000,
+		       (u_int)((tsc_freq + 4999) / 10000) % 100);
 		printf("686");
 		break;
 #endif
@@ -650,6 +673,8 @@
 		if (strcmp(cpu_vendor, "CyrixInstead") == 0)
 			printf("  DIR=0x%04x", cyrix_did);
 		if (cpu_high > 0) {
+			u_int cmp = 1, htt = 1;
+
 			/*
 			 * Here we should probably set up flags indicating
 			 * whether or not various features are available.
@@ -731,6 +756,16 @@
 				"\040<b31>"
 				);
 			}
+
+			/*
+			 * AMD64 Architecture Programmer's Manual Volume 3:
+			 * General-Purpose and System Instructions
+			 * http://www.amd.com/us-en/assets/content_type/white_papers_and_tech_docs/24594.pdf
+			 *
+			 * IA-32 Intel Architecture Software Developer's Manual,
+			 * Volume 2A: Instruction Set Reference, A-M
+			 * ftp://download.intel.com/design/Pentium4/manuals/25366617.pdf
+			 */
 			if (amd_feature != 0) {
 				printf("\n  AMD Features=0x%b", amd_feature,
 				"\020"		/* in hex */
@@ -759,9 +794,9 @@
 				"\027MMX+"	/* AMD MMX Extensions */
 				"\030<s23>"	/* Same */
 				"\031<s24>"	/* Same */
-				"\032<b25>"	/* Undefined */
+				"\032FFXSR"	/* Fast FXSAVE/FXRSTOR */
 				"\033<b26>"	/* Undefined */
-				"\034<b27>"	/* Undefined */
+				"\034RDTSCP"	/* RDTSCP */
 				"\035<b28>"	/* Undefined */
 				"\036LM"	/* 64 bit long mode */
 				"\0373DNow+"	/* AMD 3DNow! Extensions */
@@ -769,23 +804,72 @@
 				);
 			}
 
+			if (amd_feature2 != 0) {
+				printf("\n  AMD Features2=0x%b", amd_feature2,
+				"\020"
+				"\001LAHF"	/* LAHF/SAHF in long mode */
+				"\002CMP"	/* CMP legacy */
+				"\003<b2>"
+				"\004<b3>"
+				"\005CR8"	/* CR8 in legacy mode */
+				"\006<b5>"
+				"\007<b6>"
+				"\010<b7>"
+				"\011<b8>"
+				"\012<b9>"
+				"\013<b10>"
+				"\014<b11>"
+				"\015<b12>"
+				"\016<b13>"
+				"\017<b14>"
+				"\020<b15>"
+				"\021<b16>"
+				"\022<b17>"
+				"\023<b18>"
+				"\024<b19>"
+				"\025<b20>"
+				"\026<b21>"
+				"\027<b22>"
+				"\030<b23>"
+				"\031<b24>"
+				"\032<b25>"
+				"\033<b26>"
+				"\034<b27>"
+				"\035<b28>"
+				"\036<b29>"
+				"\037<b30>"
+				"\040<b31>"
+				);
+			}
+
 			if (cpu_feature & CPUID_HTT && strcmp(cpu_vendor,
 			    "AuthenticAMD") == 0) {
 				cpu_feature &= ~CPUID_HTT;
 				if (bootverbose)
 	    				printf("\n    HTT bit cleared - FreeBSD"
-					    " does not have licenseing issues"
+					    " does not have licensing issues"
 					    " requiring it.\n");
 			}
 
 			/*
-			 * If this CPU supports hyperthreading then mention
-			 * the number of logical CPU's it contains.
+			 * If this CPU supports HTT or CMP then mention the
+			 * number of physical/logical cores it contains.
 			 */
-			if (cpu_feature & CPUID_HTT &&
-			    (cpu_procinfo & CPUID_HTT_CORES) >> 16 > 1)
-				printf("\n  Hyperthreading: %d logical CPUs",
-				    (cpu_procinfo & CPUID_HTT_CORES) >> 16);
+			if (cpu_feature & CPUID_HTT)
+				htt = (cpu_procinfo & CPUID_HTT_CORES) >> 16;
+			if (strcmp(cpu_vendor, "AuthenticAMD") == 0 &&
+			    (amd_feature2 & AMDID2_CMP))
+				cmp = (cpu_procinfo2 & AMDID_CMP_CORES) + 1;
+			else if (strcmp(cpu_vendor, "GenuineIntel") == 0 &&
+			    (cpu_high >= 4)) {
+				cpuid_count(4, 0, regs);
+				cmp = ((regs[0] & 0xfc000000) >> 26) + 1;
+			}
+			if (cmp > 1)
+				printf("\n  Cores per package: %d", cmp);
+			if ((htt / cmp) > 1)
+				printf("\n  Logical CPUs per core: %d",
+				    htt / cmp);
 		}
 	} else if (strcmp(cpu_vendor, "CyrixInstead") == 0) {
 		printf("  DIR=0x%04x", cyrix_did);
Index: specialreg.h
===================================================================
RCS file: /home/cvs/src/sys/i386/include/specialreg.h,v
retrieving revision 1.1.1.1
retrieving revision 1.2
diff -L sys/i386/include/specialreg.h -L sys/i386/include/specialreg.h -u -r1.1.1.1 -r1.2
--- sys/i386/include/specialreg.h
+++ sys/i386/include/specialreg.h
@@ -27,7 +27,7 @@
  * SUCH DAMAGE.
  *
  *	from: @(#)specialreg.h	7.1 (Berkeley) 5/9/91
- * $FreeBSD: src/sys/i386/include/specialreg.h,v 1.27 2004/04/07 20:46:05 imp Exp $
+ * $FreeBSD: src/sys/i386/include/specialreg.h,v 1.27.8.2 2006/07/21 15:12:03 mr Exp $
  */
 
 #ifndef _MACHINE_SPECIALREG_H_
@@ -108,6 +108,23 @@
 #define	CPUID_PBE	0x80000000
 
 /*
+ * Important bits in the AMD extended cpuid flags
+ */
+#define AMDID_SYSCALL	0x00000800
+#define AMDID_MP	0x00080000
+#define AMDID_NX	0x00100000
+#define AMDID_EXT_MMX	0x00400000
+#define AMDID_FFXSR	0x01000000
+#define AMDID_RDTSCP	0x08000000
+#define AMDID_LM	0x20000000
+#define AMDID_EXT_3DNOW	0x40000000
+#define AMDID_3DNOW	0x80000000
+
+#define AMDID2_LAHF	0x00000001
+#define AMDID2_CMP	0x00000002
+#define AMDID2_CR8	0x00000010
+
+/*
  * CPUID instruction 1 ebx info
  */
 #define	CPUID_BRAND_INDEX	0x000000ff
@@ -116,6 +133,11 @@
 #define	CPUID_LOCAL_APIC_ID	0xff000000
 
 /*
+ * AMD extended function 8000_0008h ecx info
+ */
+#define AMDID_CMP_CORES		0x000000ff
+
+/*
  * Model-specific registers for the i386 family
  */
 #define MSR_P5_MC_ADDR		0x000
@@ -371,6 +393,41 @@
 #define	AMD_WT_ALLOC_PRE	0x20000	/* programmable range enable */
 #define	AMD_WT_ALLOC_FRE	0x10000	/* fixed (A0000-FFFFF) range enable */
 
+/* VIA ACE crypto featureset: for via_feature_rng */
+#define	VIA_HAS_RNG		1	/* cpu has RNG */
+
+/* VIA ACE crypto featureset: for via_has_xcrypt */
+#define VIA_HAS_AES		1	/* cpu has AES */
+#define VIA_HAS_SHA		2	/* cpu has SHA1 & SHA256 */
+#define VIA_HAS_MM		4	/* cpu has RSA instructions */
+#define VIA_HAS_AESCTR		8	/* cpu has AES-CTR instructions */
+
+/* Centaur Extended Feature flags */
+#define VIA_CPUID_HAS_RNG	0x000004
+#define VIA_CPUID_DO_RNG	0x000008
+#define VIA_CPUID_HAS_ACE	0x000040
+#define VIA_CPUID_DO_ACE	0x000080
+#define VIA_CPUID_HAS_ACE2	0x000100
+#define VIA_CPUID_DO_ACE2	0x000200
+#define VIA_CPUID_HAS_PHE	0x000400
+#define VIA_CPUID_DO_PHE	0x000800
+#define VIA_CPUID_HAS_PMM	0x001000
+#define VIA_CPUID_DO_PMM	0x002000
+
+/* VIA ACE xcrypt-* instruction context control options */
+#define VIA_CRYPT_CWLO_ROUND_M		0x0000000f
+#define VIA_CRYPT_CWLO_ALG_M		0x00000070
+#define VIA_CRYPT_CWLO_ALG_AES		0x00000000
+#define VIA_CRYPT_CWLO_KEYGEN_M		0x00000080
+#define VIA_CRYPT_CWLO_KEYGEN_HW	0x00000000
+#define VIA_CRYPT_CWLO_KEYGEN_SW	0x00000080
+#define VIA_CRYPT_CWLO_NORMAL		0x00000000
+#define VIA_CRYPT_CWLO_INTERMEDIATE	0x00000100
+#define VIA_CRYPT_CWLO_ENCRYPT		0x00000000
+#define VIA_CRYPT_CWLO_DECRYPT		0x00000200
+#define VIA_CRYPT_CWLO_KEY128		0x0000000a	/* 128bit, 10 rds */
+#define VIA_CRYPT_CWLO_KEY192		0x0000040c	/* 192bit, 12 rds */
+#define VIA_CRYPT_CWLO_KEY256		0x0000080e	/* 256bit, 15 rds */
 
 #ifndef LOCORE
 static __inline u_char
Index: md_var.h
===================================================================
RCS file: /home/cvs/src/sys/i386/include/md_var.h,v
retrieving revision 1.2
retrieving revision 1.3
diff -L sys/i386/include/md_var.h -L sys/i386/include/md_var.h -u -r1.2 -r1.3
--- sys/i386/include/md_var.h
+++ sys/i386/include/md_var.h
@@ -26,7 +26,7 @@
  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  * SUCH DAMAGE.
  *
- * $FreeBSD: src/sys/i386/include/md_var.h,v 1.72 2005/06/30 06:44:34 peter Exp $
+ * $FreeBSD: src/sys/i386/include/md_var.h,v 1.72.2.4 2006/07/24 23:28:09 peter Exp $
  */
 
 #ifndef _MACHINE_MD_VAR_H_
@@ -48,11 +48,15 @@
 extern	u_int	cpu_feature;
 extern	u_int	cpu_feature2;
 extern	u_int	amd_feature;
+extern	u_int	amd_feature2;
+extern	u_int	via_feature_rng;
+extern	u_int	via_feature_xcrypt;
 extern	u_int	cpu_fxsr;
 extern	u_int	cpu_high;
 extern	u_int	cpu_id;
 extern	u_int	cpu_mxcsr_mask;
 extern	u_int	cpu_procinfo;
+extern	u_int	cpu_procinfo2;
 extern	char	cpu_vendor[];
 extern	u_int	cyrix_did;
 extern	char	kstack[];
@@ -64,12 +68,15 @@
 #ifdef COMPAT_43
 extern	int	szosigcode;
 #endif
+extern	uint32_t *vm_page_dump;
+extern	int	vm_page_dump_size;
 
 typedef void alias_for_inthand_t(u_int cs, u_int ef, u_int esp, u_int ss);
 struct	thread;
 struct	reg;
 struct	fpreg;
 struct  dbreg;
+struct	dumperinfo;
 
 void	bcopyb(const void *from, void *to, size_t len);
 void	busdma_swi(void);
@@ -83,6 +90,8 @@
 void	doreti_popl_es_fault(void) __asm(__STRING(doreti_popl_es_fault));
 void	doreti_popl_fs(void) __asm(__STRING(doreti_popl_fs));
 void	doreti_popl_fs_fault(void) __asm(__STRING(doreti_popl_fs_fault));
+void	dump_add_page(vm_paddr_t);
+void	dump_drop_page(vm_paddr_t);
 void	enable_sse(void);
 void	fillw(int /*u_short*/ pat, void *base, size_t cnt);
 void	i486_bzero(void *buf, size_t len);
@@ -98,5 +107,6 @@
 vm_paddr_t kvtop(void *addr);
 void	setidt(int idx, alias_for_inthand_t *func, int typ, int dpl, int selec);
 int     user_dbreg_trap(void);
+void	minidumpsys(struct dumperinfo *);
 
 #endif /* !_MACHINE_MD_VAR_H_ */
Index: initcpu.c
===================================================================
RCS file: /home/cvs/src/sys/amd64/amd64/initcpu.c,v
retrieving revision 1.1.1.1
retrieving revision 1.2
diff -L sys/amd64/amd64/initcpu.c -L sys/amd64/amd64/initcpu.c -u -r1.1.1.1 -r1.2
--- sys/amd64/amd64/initcpu.c
+++ sys/amd64/amd64/initcpu.c
@@ -28,7 +28,7 @@
  */
 
 #include <sys/cdefs.h>
-__FBSDID("$FreeBSD: src/sys/amd64/amd64/initcpu.c,v 1.48 2004/06/08 01:02:51 peter Exp $");
+__FBSDID("$FreeBSD: src/sys/amd64/amd64/initcpu.c,v 1.48.8.2 2006/07/01 09:06:40 davidxu Exp $");
 
 #include "opt_cpu.h"
 
@@ -51,13 +51,16 @@
 int	cpu;			/* Are we 386, 386sx, 486, etc? */
 u_int	cpu_feature;		/* Feature flags */
 u_int	cpu_feature2;		/* Feature flags */
-u_int	amd_feature;		/* Feature flags */
+u_int	amd_feature;		/* AMD feature flags */
+u_int	amd_feature2;		/* AMD feature flags */
 u_int	cpu_high;		/* Highest arg to CPUID */
 u_int	cpu_exthigh;		/* Highest arg to extended CPUID */
 u_int	cpu_id;			/* Stepping ID */
 u_int	cpu_procinfo;		/* HyperThreading Info / Brand Index / CLFUSH */
+u_int	cpu_procinfo2;		/* Multicore info */
 char	cpu_vendor[20];		/* CPU Origin code */
 u_int	cpu_fxsr;		/* SSE enabled */
+u_int	cpu_mxcsr_mask;		/* Valid bits in mxcsr */
 
 /*
  * Initialize CPU control registers
Index: identcpu.c
===================================================================
RCS file: /home/cvs/src/sys/amd64/amd64/identcpu.c,v
retrieving revision 1.1.1.2
retrieving revision 1.2
diff -L sys/amd64/amd64/identcpu.c -L sys/amd64/amd64/identcpu.c -u -r1.1.1.2 -r1.2
--- sys/amd64/amd64/identcpu.c
+++ sys/amd64/amd64/identcpu.c
@@ -39,7 +39,7 @@
  */
 
 #include <sys/cdefs.h>
-__FBSDID("$FreeBSD: src/sys/amd64/amd64/identcpu.c,v 1.136.2.2 2006/02/23 15:03:42 dwmalone Exp $");
+__FBSDID("$FreeBSD: src/sys/amd64/amd64/identcpu.c,v 1.136.2.3 2006/04/24 18:21:54 jkim Exp $");
 
 #include "opt_cpu.h"
 
@@ -165,6 +165,8 @@
 	    strcmp(cpu_vendor, "AuthenticAMD") == 0) {
 		printf("  Stepping = %u", cpu_id & 0xf);
 		if (cpu_high > 0) {
+			u_int cmp = 1, htt = 1;
+
 			/*
 			 * Here we should probably set up flags indicating
 			 * whether or not various features are available.
@@ -246,6 +248,16 @@
 				"\040<b31>"
 				);
 			}
+
+			/*
+			 * AMD64 Architecture Programmer's Manual Volume 3:
+			 * General-Purpose and System Instructions
+			 * http://www.amd.com/us-en/assets/content_type/white_papers_and_tech_docs/24594.pdf
+			 *
+			 * IA-32 Intel Architecture Software Developer's Manual,
+			 * Volume 2A: Instruction Set Reference, A-M
+			 * ftp://download.intel.com/design/Pentium4/manuals/25366617.pdf
+			 */
 			if (amd_feature != 0) {
 				printf("\n  AMD Features=0x%b", amd_feature,
 				"\020"		/* in hex */
@@ -274,9 +286,9 @@
 				"\027MMX+"	/* AMD MMX Extensions */
 				"\030<s23>"	/* Same */
 				"\031<s24>"	/* Same */
-				"\032<b25>"	/* Undefined */
+				"\032FFXSR"	/* Fast FXSAVE/FXRSTOR */
 				"\033<b26>"	/* Undefined */
-				"\034<b27>"	/* Undefined */
+				"\034RDTSCP"	/* RDTSCP */
 				"\035<b28>"	/* Undefined */
 				"\036LM"	/* 64 bit long mode */
 				"\0373DNow+"	/* AMD 3DNow! Extensions */
@@ -284,23 +296,72 @@
 				);
 			}
 
+			if (amd_feature2 != 0) {
+				printf("\n  AMD Features2=0x%b", amd_feature2,
+				"\020"
+				"\001LAHF"	/* LAHF/SAHF in long mode */
+				"\002CMP"	/* CMP legacy */
+				"\003<b2>"
+				"\004<b3>"
+				"\005CR8"	/* CR8 in legacy mode */
+				"\006<b5>"
+				"\007<b6>"
+				"\010<b7>"
+				"\011<b8>"
+				"\012<b9>"
+				"\013<b10>"
+				"\014<b11>"
+				"\015<b12>"
+				"\016<b13>"
+				"\017<b14>"
+				"\020<b15>"
+				"\021<b16>"
+				"\022<b17>"
+				"\023<b18>"
+				"\024<b19>"
+				"\025<b20>"
+				"\026<b21>"
+				"\027<b22>"
+				"\030<b23>"
+				"\031<b24>"
+				"\032<b25>"
+				"\033<b26>"
+				"\034<b27>"
+				"\035<b28>"
+				"\036<b29>"
+				"\037<b30>"
+				"\040<b31>"
+				);
+			}
+
 			if (cpu_feature & CPUID_HTT && strcmp(cpu_vendor,
 			    "AuthenticAMD") == 0) {
 				cpu_feature &= ~CPUID_HTT;
 				if (bootverbose)
 	    				printf("\n    HTT bit cleared - FreeBSD"
-					    " does not have licenseing issues"
+					    " does not have licensing issues"
 					    " requiring it.\n");
 			}
 
 			/*
-			 * If this CPU supports hyperthreading then mention
-			 * the number of logical CPU's it contains.
+			 * If this CPU supports HTT or CMP then mention the
+			 * number of physical/logical cores it contains.
 			 */
-			if (cpu_feature & CPUID_HTT &&
-			    (cpu_procinfo & CPUID_HTT_CORES) >> 16 > 1)
-				printf("\n  Hyperthreading: %d logical CPUs",
-				    (cpu_procinfo & CPUID_HTT_CORES) >> 16);
+			if (cpu_feature & CPUID_HTT)
+				htt = (cpu_procinfo & CPUID_HTT_CORES) >> 16;
+			if (strcmp(cpu_vendor, "AuthenticAMD") == 0 &&
+			    (amd_feature2 & AMDID2_CMP))
+				cmp = (cpu_procinfo2 & AMDID_CMP_CORES) + 1;
+			else if (strcmp(cpu_vendor, "GenuineIntel") == 0 &&
+			    (cpu_high >= 4)) {
+				cpuid_count(4, 0, regs);
+				cmp = ((regs[0] & 0xfc000000) >> 26) + 1;
+			}
+			if (cmp > 1)
+				printf("\n  Cores per package: %d", cmp);
+			if ((htt / cmp) > 1)
+				printf("\n  Logical CPUs per core: %d",
+				    htt / cmp);
 		}
 	}
 	/* Avoid ugly blank lines: only print newline when we have to. */
@@ -366,6 +427,11 @@
 	if (cpu_exthigh >= 0x80000001) {
 		do_cpuid(0x80000001, regs);
 		amd_feature = regs[3] & ~(cpu_feature & 0x0183f3ff);
+		amd_feature2 = regs[2];
+	}
+	if (cpu_exthigh >= 0x80000008) {
+		do_cpuid(0x80000008, regs);
+		cpu_procinfo2 = regs[2];
 	}
 
 	/* XXX */
Index: tcp_syncache.c
===================================================================
RCS file: /home/cvs/src/sys/netinet/tcp_syncache.c,v
retrieving revision 1.7
retrieving revision 1.8
diff -L sys/netinet/tcp_syncache.c -L sys/netinet/tcp_syncache.c -u -r1.7 -r1.8
--- sys/netinet/tcp_syncache.c
+++ sys/netinet/tcp_syncache.c
@@ -734,11 +734,7 @@
  * the SYN-RECEIVED state.
  */
 int
-syncache_expand(inc, th, sop, m)
-	struct in_conninfo *inc;
-	struct tcphdr *th;
-	struct socket **sop;
-	struct mbuf *m;
+syncache_expand(struct in_conninfo *inc, struct tcphdr *th, struct socket **sop, struct mbuf *m)
 {
 	struct syncache *sc;
 	struct syncache_head *sch;


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