[Midnightbsd-cvs] src: libkern/arm: remove arm/ia64 cruft
laffer1 at midnightbsd.org
laffer1 at midnightbsd.org
Sun Mar 15 10:28:22 EDT 2009
Log Message:
-----------
remove arm/ia64 cruft
Removed Files:
-------------
src/sys/libkern/arm:
divsi3.S
ffs.S
muldi3.c
src/sys/libkern/ia64:
__divdi3.S
__divsi3.S
__moddi3.S
__modsi3.S
__udivdi3.S
__udivsi3.S
__umoddi3.S
__umodsi3.S
bswap16.S
bswap32.S
byte_swap_2.S
byte_swap_4.S
-------------- next part --------------
--- sys/libkern/arm/ffs.S
+++ /dev/null
@@ -1,84 +0,0 @@
-/* $NetBSD: ffs.S,v 1.3 2003/04/05 23:27:15 bjh21 Exp $ */
-/*-
- * Copyright (c) 2001 Christopher Gilbert
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * 3. The name of the company nor the name of the author may be used to
- * endorse or promote products derived from this software without specific
- * prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
- * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
- * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
- * IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
- * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- * SUCH DAMAGE.
- */
-
-#include <machine/asm.h>
-__FBSDID("$FreeBSD: src/sys/libkern/arm/ffs.S,v 1.4 2005/01/07 00:24:33 imp Exp $");
-
-
-/*
- * ffs - find first set bit, this algorithm isolates the first set
- * bit, then multiplies the number by 0x0450fbaf which leaves the top
- * 6 bits as an index into the table. This algorithm should be a win
- * over the checking each bit in turn as per the C compiled version.
- *
- * under ARMv5 there's an instruction called CLZ (count leading Zero's) that
- * could be used
- *
- * This is the ffs algorithm devised by d.seal and posted to comp.sys.arm on
- * 16 Feb 1994.
- */
-
-ENTRY(ffs)
-
- /* Standard trick to isolate bottom bit in r0 or 0 if r0 = 0 on entry */
- rsb r1, r0, #0
- ands r0, r0, r1
-#ifndef __XSCALE__
-
- /*
- * now r0 has at most one set bit, call this X
- * if X = 0, all further instructions are skipped
- */
- adrne r2, .L_ffs_table
- orrne r0, r0, r0, lsl #4 /* r0 = X * 0x11 */
- orrne r0, r0, r0, lsl #6 /* r0 = X * 0x451 */
- rsbne r0, r0, r0, lsl #16 /* r0 = X * 0x0450fbaf */
-
- /* now lookup in table indexed on top 6 bits of r0 */
- ldrneb r0, [ r2, r0, lsr #26 ]
-
- RET
-.text;
-.type .L_ffs_table, _ASM_TYPE_OBJECT;
-.L_ffs_table:
-/* 0 1 2 3 4 5 6 7 */
- .byte 0, 1, 2, 13, 3, 7, 0, 14 /* 0- 7 */
- .byte 4, 0, 8, 0, 0, 0, 0, 15 /* 8-15 */
- .byte 11, 5, 0, 0, 9, 0, 0, 26 /* 16-23 */
- .byte 0, 0, 0, 0, 0, 22, 28, 16 /* 24-31 */
- .byte 32, 12, 6, 0, 0, 0, 0, 0 /* 32-39 */
- .byte 10, 0, 0, 25, 0, 0, 21, 27 /* 40-47 */
- .byte 31, 0, 0, 0, 0, 24, 0, 20 /* 48-55 */
- .byte 30, 0, 23, 19, 29, 18, 17, 0 /* 56-63 */
-#else
- clzne r0, r0
- rsbne r0, r0, #32
- RET
-#endif
--- sys/libkern/arm/divsi3.S
+++ /dev/null
@@ -1,387 +0,0 @@
-/* $NetBSD: divsi3.S,v 1.4 2003/04/05 23:27:15 bjh21 Exp $ */
-
-/*-
- * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- * SUCH DAMAGE.
- */
-
-#include <machine/asm.h>
-__FBSDID("$FreeBSD: src/sys/libkern/arm/divsi3.S,v 1.4 2005/01/07 00:24:33 imp Exp $");
-
-/*
- * stack is aligned as there's a possibility of branching to L_overflow
- * which makes a C call
- */
-
-ENTRY_NP(__umodsi3)
- stmfd sp!, {lr}
- sub sp, sp, #4 /* align stack */
- bl .L_udivide
- add sp, sp, #4 /* unalign stack */
- mov r0, r1
- ldmfd sp!, {pc}
-
-ENTRY_NP(__modsi3)
- stmfd sp!, {lr}
- sub sp, sp, #4 /* align stack */
- bl .L_divide
- add sp, sp, #4 /* unalign stack */
- mov r0, r1
- ldmfd sp!, {pc}
-
-.L_overflow:
-#if !defined(_KERNEL) && !defined(_STANDALONE)
- mov r0, #8 /* SIGFPE */
- bl PIC_SYM(_C_LABEL(raise), PLT) /* raise it */
- mov r0, #0
-#else
- /* XXX should cause a fatal error */
- mvn r0, #0
-#endif
- RET
-
-ENTRY_NP(__udivsi3)
-.L_udivide: /* r0 = r0 / r1; r1 = r0 % r1 */
- eor r0, r1, r0
- eor r1, r0, r1
- eor r0, r1, r0
- /* r0 = r1 / r0; r1 = r1 % r0 */
- cmp r0, #1
- bcc .L_overflow
- beq .L_divide_l0
- mov ip, #0
- movs r1, r1
- bpl .L_divide_l1
- orr ip, ip, #0x20000000 /* ip bit 0x20000000 = -ve r1 */
- movs r1, r1, lsr #1
- orrcs ip, ip, #0x10000000 /* ip bit 0x10000000 = bit 0 of r1 */
- b .L_divide_l1
-
-.L_divide_l0: /* r0 == 1 */
- mov r0, r1
- mov r1, #0
- RET
-
-ENTRY_NP(__divsi3)
-.L_divide: /* r0 = r0 / r1; r1 = r0 % r1 */
- eor r0, r1, r0
- eor r1, r0, r1
- eor r0, r1, r0
- /* r0 = r1 / r0; r1 = r1 % r0 */
- cmp r0, #1
- bcc .L_overflow
- beq .L_divide_l0
- ands ip, r0, #0x80000000
- rsbmi r0, r0, #0
- ands r2, r1, #0x80000000
- eor ip, ip, r2
- rsbmi r1, r1, #0
- orr ip, r2, ip, lsr #1 /* ip bit 0x40000000 = -ve division */
- /* ip bit 0x80000000 = -ve remainder */
-
-.L_divide_l1:
- mov r2, #1
- mov r3, #0
-
- /*
- * If the highest bit of the dividend is set, we have to be
- * careful when shifting the divisor. Test this.
- */
- movs r1,r1
- bpl .L_old_code
-
- /*
- * At this point, the highest bit of r1 is known to be set.
- * We abuse this below in the tst instructions.
- */
- tst r1, r0 /*, lsl #0 */
- bmi .L_divide_b1
- tst r1, r0, lsl #1
- bmi .L_divide_b2
- tst r1, r0, lsl #2
- bmi .L_divide_b3
- tst r1, r0, lsl #3
- bmi .L_divide_b4
- tst r1, r0, lsl #4
- bmi .L_divide_b5
- tst r1, r0, lsl #5
- bmi .L_divide_b6
- tst r1, r0, lsl #6
- bmi .L_divide_b7
- tst r1, r0, lsl #7
- bmi .L_divide_b8
- tst r1, r0, lsl #8
- bmi .L_divide_b9
- tst r1, r0, lsl #9
- bmi .L_divide_b10
- tst r1, r0, lsl #10
- bmi .L_divide_b11
- tst r1, r0, lsl #11
- bmi .L_divide_b12
- tst r1, r0, lsl #12
- bmi .L_divide_b13
- tst r1, r0, lsl #13
- bmi .L_divide_b14
- tst r1, r0, lsl #14
- bmi .L_divide_b15
- tst r1, r0, lsl #15
- bmi .L_divide_b16
- tst r1, r0, lsl #16
- bmi .L_divide_b17
- tst r1, r0, lsl #17
- bmi .L_divide_b18
- tst r1, r0, lsl #18
- bmi .L_divide_b19
- tst r1, r0, lsl #19
- bmi .L_divide_b20
- tst r1, r0, lsl #20
- bmi .L_divide_b21
- tst r1, r0, lsl #21
- bmi .L_divide_b22
- tst r1, r0, lsl #22
- bmi .L_divide_b23
- tst r1, r0, lsl #23
- bmi .L_divide_b24
- tst r1, r0, lsl #24
- bmi .L_divide_b25
- tst r1, r0, lsl #25
- bmi .L_divide_b26
- tst r1, r0, lsl #26
- bmi .L_divide_b27
- tst r1, r0, lsl #27
- bmi .L_divide_b28
- tst r1, r0, lsl #28
- bmi .L_divide_b29
- tst r1, r0, lsl #29
- bmi .L_divide_b30
- tst r1, r0, lsl #30
- bmi .L_divide_b31
-/*
- * instead of:
- * tst r1, r0, lsl #31
- * bmi .L_divide_b32
- */
- b .L_divide_b32
-
-.L_old_code:
- cmp r1, r0
- bcc .L_divide_b0
- cmp r1, r0, lsl #1
- bcc .L_divide_b1
- cmp r1, r0, lsl #2
- bcc .L_divide_b2
- cmp r1, r0, lsl #3
- bcc .L_divide_b3
- cmp r1, r0, lsl #4
- bcc .L_divide_b4
- cmp r1, r0, lsl #5
- bcc .L_divide_b5
- cmp r1, r0, lsl #6
- bcc .L_divide_b6
- cmp r1, r0, lsl #7
- bcc .L_divide_b7
- cmp r1, r0, lsl #8
- bcc .L_divide_b8
- cmp r1, r0, lsl #9
- bcc .L_divide_b9
- cmp r1, r0, lsl #10
- bcc .L_divide_b10
- cmp r1, r0, lsl #11
- bcc .L_divide_b11
- cmp r1, r0, lsl #12
- bcc .L_divide_b12
- cmp r1, r0, lsl #13
- bcc .L_divide_b13
- cmp r1, r0, lsl #14
- bcc .L_divide_b14
- cmp r1, r0, lsl #15
- bcc .L_divide_b15
- cmp r1, r0, lsl #16
- bcc .L_divide_b16
- cmp r1, r0, lsl #17
- bcc .L_divide_b17
- cmp r1, r0, lsl #18
- bcc .L_divide_b18
- cmp r1, r0, lsl #19
- bcc .L_divide_b19
- cmp r1, r0, lsl #20
- bcc .L_divide_b20
- cmp r1, r0, lsl #21
- bcc .L_divide_b21
- cmp r1, r0, lsl #22
- bcc .L_divide_b22
- cmp r1, r0, lsl #23
- bcc .L_divide_b23
- cmp r1, r0, lsl #24
- bcc .L_divide_b24
- cmp r1, r0, lsl #25
- bcc .L_divide_b25
- cmp r1, r0, lsl #26
- bcc .L_divide_b26
- cmp r1, r0, lsl #27
- bcc .L_divide_b27
- cmp r1, r0, lsl #28
- bcc .L_divide_b28
- cmp r1, r0, lsl #29
- bcc .L_divide_b29
- cmp r1, r0, lsl #30
- bcc .L_divide_b30
-.L_divide_b32:
- cmp r1, r0, lsl #31
- subhs r1, r1,r0, lsl #31
- addhs r3, r3,r2, lsl #31
-.L_divide_b31:
- cmp r1, r0, lsl #30
- subhs r1, r1,r0, lsl #30
- addhs r3, r3,r2, lsl #30
-.L_divide_b30:
- cmp r1, r0, lsl #29
- subhs r1, r1,r0, lsl #29
- addhs r3, r3,r2, lsl #29
-.L_divide_b29:
- cmp r1, r0, lsl #28
- subhs r1, r1,r0, lsl #28
- addhs r3, r3,r2, lsl #28
-.L_divide_b28:
- cmp r1, r0, lsl #27
- subhs r1, r1,r0, lsl #27
- addhs r3, r3,r2, lsl #27
-.L_divide_b27:
- cmp r1, r0, lsl #26
- subhs r1, r1,r0, lsl #26
- addhs r3, r3,r2, lsl #26
-.L_divide_b26:
- cmp r1, r0, lsl #25
- subhs r1, r1,r0, lsl #25
- addhs r3, r3,r2, lsl #25
-.L_divide_b25:
- cmp r1, r0, lsl #24
- subhs r1, r1,r0, lsl #24
- addhs r3, r3,r2, lsl #24
-.L_divide_b24:
- cmp r1, r0, lsl #23
- subhs r1, r1,r0, lsl #23
- addhs r3, r3,r2, lsl #23
-.L_divide_b23:
- cmp r1, r0, lsl #22
- subhs r1, r1,r0, lsl #22
- addhs r3, r3,r2, lsl #22
-.L_divide_b22:
- cmp r1, r0, lsl #21
- subhs r1, r1,r0, lsl #21
- addhs r3, r3,r2, lsl #21
-.L_divide_b21:
- cmp r1, r0, lsl #20
- subhs r1, r1,r0, lsl #20
- addhs r3, r3,r2, lsl #20
-.L_divide_b20:
- cmp r1, r0, lsl #19
- subhs r1, r1,r0, lsl #19
- addhs r3, r3,r2, lsl #19
-.L_divide_b19:
- cmp r1, r0, lsl #18
- subhs r1, r1,r0, lsl #18
- addhs r3, r3,r2, lsl #18
-.L_divide_b18:
- cmp r1, r0, lsl #17
- subhs r1, r1,r0, lsl #17
- addhs r3, r3,r2, lsl #17
-.L_divide_b17:
- cmp r1, r0, lsl #16
- subhs r1, r1,r0, lsl #16
- addhs r3, r3,r2, lsl #16
-.L_divide_b16:
- cmp r1, r0, lsl #15
- subhs r1, r1,r0, lsl #15
- addhs r3, r3,r2, lsl #15
-.L_divide_b15:
- cmp r1, r0, lsl #14
- subhs r1, r1,r0, lsl #14
- addhs r3, r3,r2, lsl #14
-.L_divide_b14:
- cmp r1, r0, lsl #13
- subhs r1, r1,r0, lsl #13
- addhs r3, r3,r2, lsl #13
-.L_divide_b13:
- cmp r1, r0, lsl #12
- subhs r1, r1,r0, lsl #12
- addhs r3, r3,r2, lsl #12
-.L_divide_b12:
- cmp r1, r0, lsl #11
- subhs r1, r1,r0, lsl #11
- addhs r3, r3,r2, lsl #11
-.L_divide_b11:
- cmp r1, r0, lsl #10
- subhs r1, r1,r0, lsl #10
- addhs r3, r3,r2, lsl #10
-.L_divide_b10:
- cmp r1, r0, lsl #9
- subhs r1, r1,r0, lsl #9
- addhs r3, r3,r2, lsl #9
-.L_divide_b9:
- cmp r1, r0, lsl #8
- subhs r1, r1,r0, lsl #8
- addhs r3, r3,r2, lsl #8
-.L_divide_b8:
- cmp r1, r0, lsl #7
- subhs r1, r1,r0, lsl #7
- addhs r3, r3,r2, lsl #7
-.L_divide_b7:
- cmp r1, r0, lsl #6
- subhs r1, r1,r0, lsl #6
- addhs r3, r3,r2, lsl #6
-.L_divide_b6:
- cmp r1, r0, lsl #5
- subhs r1, r1,r0, lsl #5
- addhs r3, r3,r2, lsl #5
-.L_divide_b5:
- cmp r1, r0, lsl #4
- subhs r1, r1,r0, lsl #4
- addhs r3, r3,r2, lsl #4
-.L_divide_b4:
- cmp r1, r0, lsl #3
- subhs r1, r1,r0, lsl #3
- addhs r3, r3,r2, lsl #3
-.L_divide_b3:
- cmp r1, r0, lsl #2
- subhs r1, r1,r0, lsl #2
- addhs r3, r3,r2, lsl #2
-.L_divide_b2:
- cmp r1, r0, lsl #1
- subhs r1, r1,r0, lsl #1
- addhs r3, r3,r2, lsl #1
-.L_divide_b1:
- cmp r1, r0
- subhs r1, r1, r0
- addhs r3, r3, r2
-.L_divide_b0:
-
- tst ip, #0x20000000
- bne .L_udivide_l1
- mov r0, r3
- cmp ip, #0
- rsbmi r1, r1, #0
- movs ip, ip, lsl #1
- bicmi r0, r0, #0x80000000 /* Fix incase we divided 0x80000000 */
- rsbmi r0, r0, #0
- RET
-
-.L_udivide_l1:
- tst ip, #0x10000000
- mov r1, r1, lsl #1
- orrne r1, r1, #1
- mov r3, r3, lsl #1
- cmp r1, r0
- subhs r1, r1, r0
- addhs r3, r3, r2
- mov r0, r3
- RET
--- sys/libkern/arm/muldi3.c
+++ /dev/null
@@ -1,249 +0,0 @@
-/* $NetBSD: muldi3.c,v 1.8 2003/08/07 16:32:09 agc Exp $ */
-
-/*-
- * Copyright (c) 1992, 1993
- * The Regents of the University of California. All rights reserved.
- *
- * This software was developed by the Computer Systems Engineering group
- * at Lawrence Berkeley Laboratory under DARPA contract BG 91-66 and
- * contributed to Berkeley.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * 3. Neither the name of the University nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- * SUCH DAMAGE.
- */
-
-#include <sys/cdefs.h>
-#if defined(LIBC_SCCS) && !defined(lint)
-#if 0
-static char sccsid[] = "@(#)muldi3.c 8.1 (Berkeley) 6/4/93";
-#else
-__FBSDID("$FreeBSD: src/sys/libkern/arm/muldi3.c,v 1.1 2004/05/14 12:28:31 cognet Exp $");
-#endif
-#endif /* LIBC_SCCS and not lint */
-
-#include <libkern/quad.h>
-
-/*
- * Multiply two quads.
- *
- * Our algorithm is based on the following. Split incoming quad values
- * u and v (where u,v >= 0) into
- *
- * u = 2^n u1 * u0 (n = number of bits in `u_int', usu. 32)
- *
- * and
- *
- * v = 2^n v1 * v0
- *
- * Then
- *
- * uv = 2^2n u1 v1 + 2^n u1 v0 + 2^n v1 u0 + u0 v0
- * = 2^2n u1 v1 + 2^n (u1 v0 + v1 u0) + u0 v0
- *
- * Now add 2^n u1 v1 to the first term and subtract it from the middle,
- * and add 2^n u0 v0 to the last term and subtract it from the middle.
- * This gives:
- *
- * uv = (2^2n + 2^n) (u1 v1) +
- * (2^n) (u1 v0 - u1 v1 + u0 v1 - u0 v0) +
- * (2^n + 1) (u0 v0)
- *
- * Factoring the middle a bit gives us:
- *
- * uv = (2^2n + 2^n) (u1 v1) + [u1v1 = high]
- * (2^n) (u1 - u0) (v0 - v1) + [(u1-u0)... = mid]
- * (2^n + 1) (u0 v0) [u0v0 = low]
- *
- * The terms (u1 v1), (u1 - u0) (v0 - v1), and (u0 v0) can all be done
- * in just half the precision of the original. (Note that either or both
- * of (u1 - u0) or (v0 - v1) may be negative.)
- *
- * This algorithm is from Knuth vol. 2 (2nd ed), section 4.3.3, p. 278.
- *
- * Since C does not give us a `int * int = quad' operator, we split
- * our input quads into two ints, then split the two ints into two
- * shorts. We can then calculate `short * short = int' in native
- * arithmetic.
- *
- * Our product should, strictly speaking, be a `long quad', with 128
- * bits, but we are going to discard the upper 64. In other words,
- * we are not interested in uv, but rather in (uv mod 2^2n). This
- * makes some of the terms above vanish, and we get:
- *
- * (2^n)(high) + (2^n)(mid) + (2^n + 1)(low)
- *
- * or
- *
- * (2^n)(high + mid + low) + low
- *
- * Furthermore, `high' and `mid' can be computed mod 2^n, as any factor
- * of 2^n in either one will also vanish. Only `low' need be computed
- * mod 2^2n, and only because of the final term above.
- */
-static quad_t __lmulq(u_int, u_int);
-
-quad_t __muldi3(quad_t, quad_t);
-quad_t
-__muldi3(quad_t a, quad_t b)
-{
- union uu u, v, low, prod;
- u_int high, mid, udiff, vdiff;
- int negall, negmid;
-#define u1 u.ul[H]
-#define u0 u.ul[L]
-#define v1 v.ul[H]
-#define v0 v.ul[L]
-
- /*
- * Get u and v such that u, v >= 0. When this is finished,
- * u1, u0, v1, and v0 will be directly accessible through the
- * int fields.
- */
- if (a >= 0)
- u.q = a, negall = 0;
- else
- u.q = -a, negall = 1;
- if (b >= 0)
- v.q = b;
- else
- v.q = -b, negall ^= 1;
-
- if (u1 == 0 && v1 == 0) {
- /*
- * An (I hope) important optimization occurs when u1 and v1
- * are both 0. This should be common since most numbers
- * are small. Here the product is just u0*v0.
- */
- prod.q = __lmulq(u0, v0);
- } else {
- /*
- * Compute the three intermediate products, remembering
- * whether the middle term is negative. We can discard
- * any upper bits in high and mid, so we can use native
- * u_int * u_int => u_int arithmetic.
- */
- low.q = __lmulq(u0, v0);
-
- if (u1 >= u0)
- negmid = 0, udiff = u1 - u0;
- else
- negmid = 1, udiff = u0 - u1;
- if (v0 >= v1)
- vdiff = v0 - v1;
- else
- vdiff = v1 - v0, negmid ^= 1;
- mid = udiff * vdiff;
-
- high = u1 * v1;
-
- /*
- * Assemble the final product.
- */
- prod.ul[H] = high + (negmid ? -mid : mid) + low.ul[L] +
- low.ul[H];
- prod.ul[L] = low.ul[L];
- }
- return (negall ? -prod.q : prod.q);
-#undef u1
-#undef u0
-#undef v1
-#undef v0
-}
-
-/*
- * Multiply two 2N-bit ints to produce a 4N-bit quad, where N is half
- * the number of bits in an int (whatever that is---the code below
- * does not care as long as quad.h does its part of the bargain---but
- * typically N==16).
- *
- * We use the same algorithm from Knuth, but this time the modulo refinement
- * does not apply. On the other hand, since N is half the size of an int,
- * we can get away with native multiplication---none of our input terms
- * exceeds (UINT_MAX >> 1).
- *
- * Note that, for u_int l, the quad-precision result
- *
- * l << N
- *
- * splits into high and low ints as HHALF(l) and LHUP(l) respectively.
- */
-static quad_t
-__lmulq(u_int u, u_int v)
-{
- u_int u1, u0, v1, v0, udiff, vdiff, high, mid, low;
- u_int prodh, prodl, was;
- union uu prod;
- int neg;
-
- u1 = HHALF(u);
- u0 = LHALF(u);
- v1 = HHALF(v);
- v0 = LHALF(v);
-
- low = u0 * v0;
-
- /* This is the same small-number optimization as before. */
- if (u1 == 0 && v1 == 0)
- return (low);
-
- if (u1 >= u0)
- udiff = u1 - u0, neg = 0;
- else
- udiff = u0 - u1, neg = 1;
- if (v0 >= v1)
- vdiff = v0 - v1;
- else
- vdiff = v1 - v0, neg ^= 1;
- mid = udiff * vdiff;
-
- high = u1 * v1;
-
- /* prod = (high << 2N) + (high << N); */
- prodh = high + HHALF(high);
- prodl = LHUP(high);
-
- /* if (neg) prod -= mid << N; else prod += mid << N; */
- if (neg) {
- was = prodl;
- prodl -= LHUP(mid);
- prodh -= HHALF(mid) + (prodl > was);
- } else {
- was = prodl;
- prodl += LHUP(mid);
- prodh += HHALF(mid) + (prodl < was);
- }
-
- /* prod += low << N */
- was = prodl;
- prodl += LHUP(low);
- prodh += HHALF(low) + (prodl < was);
- /* ... + low; */
- if ((prodl += low) < low)
- prodh++;
-
- /* return 4N-bit product */
- prod.ul[H] = prodh;
- prod.ul[L] = prodl;
- return (prod.q);
-}
--- sys/libkern/ia64/__umodsi3.S
+++ /dev/null
@@ -1,131 +0,0 @@
-.file "__umodsi3.s"
-
-// $FreeBSD: src/sys/libkern/ia64/__umodsi3.S,v 1.2 2005/01/07 00:24:33 imp Exp $
-
-//-
-// Copyright (c) 2000, Intel Corporation
-// All rights reserved.
-//
-// Contributed 2/15/2000 by Marius Cornea, John Harrison, Cristina Iordache,
-// Ted Kubaska, Bob Norin, and Shane Story of the Computational Software Lab,
-// Intel Corporation.
-//
-// WARRANTY DISCLAIMER
-//
-// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
-// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL INTEL OR ITS
-// CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
-// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
-// PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
-// PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
-// OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY OR TORT (INCLUDING
-// NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
-// SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-//
-// Intel Corporation is the author of this code, and requests that all
-// problem reports or change requests be submitted to it directly at
-// http://developer.intel.com/opensource.
-//
-
-.section .text
-
-// 32-bit unsigned integer remainder
-
-.proc __umodsi3#
-.align 32
-.global __umodsi3#
-.align 32
-
-__umodsi3:
-
-{ .mii
- alloc r31=ar.pfs,2,0,0,0
- nop.i 0
- nop.i 0;;
-} { .mii
- nop.m 0
-
- // 32-BIT UNSIGNED INTEGER REMAINDER BEGINS HERE
-
- // general register used:
- // r32 - 32-bit unsigned integer dividend
- // r33 - 32-bit unsigned integer divisor
- // r8 - 32-bit unsigned integer result
- // r2 - scratch register
- // floating-point registers used: f6, f7, f8, f9, f10, f11
- // predicate registers used: p6
-
- zxt4 r32=r32
- zxt4 r33=r33;;
-} { .mmb
- setf.sig f11=r32
- setf.sig f7=r33
- nop.b 0;;
-} { .mfi
- nop.m 0
- fcvt.xf f6=f11
- nop.i 0
-} { .mfi
- // get 2's complement of b
- sub r33=r0,r33
- fcvt.xf f7=f7
- mov r2 = 0x0ffdd;;
-} { .mfi
- setf.exp f9 = r2
- // (1) y0
- frcpa.s1 f8,p6=f6,f7
- nop.i 0;;
-} { .mfi
- nop.m 0
- // (2) q0 = a * y0
- (p6) fma.s1 f10=f6,f8,f0
- nop.i 0
-} { .mfi
- nop.m 0
- // (3) e0 = 1 - b * y0
- (p6) fnma.s1 f8=f7,f8,f1
- nop.i 0;;
-} { .mfi
- nop.m 0
- // (4) q1 = q0 + e0 * q0
- (p6) fma.s1 f10=f8,f10,f10
- nop.i 0
-} { .mfi
- // get 2's complement of b
- setf.sig f7=r33
- // (5) e1 = e0 * e0 + 2^-34
- (p6) fma.s1 f8=f8,f8,f9
- nop.i 0;;
-} { .mfi
- nop.m 0
- // (6) q2 = q1 + e1 * q1
- (p6) fma.s1 f8=f8,f10,f10
- nop.i 0;;
-} { .mfi
- nop.m 0
- // (7) q = trunc(q2)
- fcvt.fxu.trunc.s1 f8=f8
- nop.i 0;;
-} { .mfi
- nop.m 0
- // (8) r = a + (-b) * q
- xma.l f8=f8,f7,f11
- nop.i 0;;
-} { .mmi
- // remainder will be in the least significant 32 bits of r8 (if b != 0)
- getf.sig r8=f8
- nop.m 0
- nop.i 0;;
-}
-
- // 32-BIT UNSIGNED INTEGER REMAINDER ENDS HERE
-
-{ .mmb
- nop.m 0
- nop.m 0
- br.ret.sptk b0;;
-}
-
-.endp __umodsi3
--- sys/libkern/ia64/byte_swap_4.S
+++ /dev/null
@@ -1,47 +0,0 @@
-/* $FreeBSD: src/sys/libkern/ia64/byte_swap_4.S,v 1.5 2005/01/07 00:24:33 imp Exp $ */
-/* $NetBSD: byte_swap_4.S,v 1.2 1996/10/17 03:08:09 cgd Exp $ */
-
-/*-
- * Copyright (c) 1996 Carnegie-Mellon University.
- * All rights reserved.
- *
- * Author: Chris G. Demetriou
- *
- * Permission to use, copy, modify and distribute this software and
- * its documentation is hereby granted, provided that both the copyright
- * notice and this permission notice appear in all copies of the
- * software, derivative works or modified versions, and any portions
- * thereof, and that both notices appear in supporting documentation.
- *
- * CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS"
- * CONDITION. CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND
- * FOR ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE.
- *
- * Carnegie Mellon requests users of this software to return to
- *
- * Software Distribution Coordinator or Software.Distribution at CS.CMU.EDU
- * School of Computer Science
- * Carnegie Mellon University
- * Pittsburgh PA 15213-3890
- *
- * any improvements or extensions that they make and grant Carnegie the
- * rights to redistribute these changes.
- */
-
-#include <machine/asm.h>
-
-#ifndef NAME
-#error NAME not defined
-#endif
-
-/*
- * Byte-swap a 4-byte quantity. (Convert 0x01234567 to 0x67452301.)
- *
- * Argument is an unsigned 4-byte integer (u_int32_t).
- */
-ENTRY(NAME, 1)
- mux1 r16=in0, at rev
- ;;
- extr.u r8=r16,32,32
- br.ret.sptk.few rp
-END(NAME)
--- sys/libkern/ia64/__divsi3.S
+++ /dev/null
@@ -1,124 +0,0 @@
-.file "__divsi3.s"
-
-// $FreeBSD: src/sys/libkern/ia64/__divsi3.S,v 1.2 2005/01/07 00:24:33 imp Exp $
-
-//-
-// Copyright (c) 2000, Intel Corporation
-// All rights reserved.
-//
-// Contributed 2/15/2000 by Marius Cornea, John Harrison, Cristina Iordache,
-// Ted Kubaska, Bob Norin, and Shane Story of the Computational Software Lab,
-// Intel Corporation.
-//
-// WARRANTY DISCLAIMER
-//
-// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
-// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL INTEL OR ITS
-// CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
-// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
-// PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
-// PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
-// OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY OR TORT (INCLUDING
-// NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
-// SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-//
-// Intel Corporation is the author of this code, and requests that all
-// problem reports or change requests be submitted to it directly at
-// http://developer.intel.com/opensource.
-//
-
-.section .text
-
-// 32-bit signed integer divide
-
-.proc __divsi3#
-.align 32
-.global __divsi3#
-.align 32
-
-__divsi3:
-
-{ .mii
- alloc r31=ar.pfs,2,0,0,0
- nop.i 0
- nop.i 0;;
-} { .mii
- nop.m 0
-
- // 32-BIT SIGNED INTEGER DIVIDE BEGINS HERE
-
- // general register used:
- // r32 - 32-bit signed integer dividend
- // r33 - 32-bit signed integer divisor
- // r8 - 32-bit signed integer result
- // r2 - scratch register
- // floating-point registers used: f6, f7, f8, f9
- // predicate registers used: p6
-
- sxt4 r32=r32
- sxt4 r33=r33;;
-} { .mmb
- setf.sig f6=r32
- setf.sig f7=r33
- nop.b 0;;
-} { .mfi
- nop.m 0
- fcvt.xf f6=f6
- nop.i 0
-} { .mfi
- nop.m 0
- fcvt.xf f7=f7
- mov r2 = 0x0ffdd;;
-} { .mfi
- setf.exp f9 = r2
- // (1) y0
- frcpa.s1 f8,p6=f6,f7
- nop.i 0;;
-} { .mfi
- nop.m 0
- // (2) q0 = a * y0
- (p6) fma.s1 f6=f6,f8,f0
- nop.i 0
-} { .mfi
- nop.m 0
- // (3) e0 = 1 - b * y0
- (p6) fnma.s1 f7=f7,f8,f1
- nop.i 0;;
-} { .mfi
- nop.m 0
- // (4) q1 = q0 + e0 * q0
- (p6) fma.s1 f6=f7,f6,f6
- nop.i 0
-} { .mfi
- nop.m 0
- // (5) e1 = e0 * e0 + 2^-34
- (p6) fma.s1 f7=f7,f7,f9
- nop.i 0;;
-} { .mfi
- nop.m 0
- // (6) q2 = q1 + e1 * q1
- (p6) fma.s1 f8=f7,f6,f6
- nop.i 0;;
-} { .mfi
- nop.m 0
- // (7) q = trunc(q2)
- fcvt.fx.trunc.s1 f8=f8
- nop.i 0;;
-} { .mmi
- // quotient will be in the least significant 32 bits of r8 (if b != 0)
- getf.sig r8=f8
- nop.m 0
- nop.i 0;;
-}
-
- // 32-BIT SIGNED INTEGER DIVIDE ENDS HERE
-
-{ .mmb
- nop.m 0
- nop.m 0
- br.ret.sptk b0;;
-}
-
-.endp __divsi3
--- sys/libkern/ia64/byte_swap_2.S
+++ /dev/null
@@ -1,47 +0,0 @@
-/* $FreeBSD: src/sys/libkern/ia64/byte_swap_2.S,v 1.5 2005/01/07 00:24:33 imp Exp $ */
-/* $NetBSD: byte_swap_2.S,v 1.2 1996/10/17 03:08:08 cgd Exp $ */
-
-/*-
- * Copyright (c) 1996 Carnegie-Mellon University.
- * All rights reserved.
- *
- * Author: Chris G. Demetriou
- *
- * Permission to use, copy, modify and distribute this software and
- * its documentation is hereby granted, provided that both the copyright
- * notice and this permission notice appear in all copies of the
- * software, derivative works or modified versions, and any portions
- * thereof, and that both notices appear in supporting documentation.
- *
- * CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS"
- * CONDITION. CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND
- * FOR ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE.
- *
- * Carnegie Mellon requests users of this software to return to
- *
- * Software Distribution Coordinator or Software.Distribution at CS.CMU.EDU
- * School of Computer Science
- * Carnegie Mellon University
- * Pittsburgh PA 15213-3890
- *
- * any improvements or extensions that they make and grant Carnegie the
- * rights to redistribute these changes.
- */
-
-#include <machine/asm.h>
-
-#ifndef NAME
-#error NAME not defined
-#endif
-
-/*
- * Byte-swap a 2-byte quantity. (Convert 0x0123 to 0x2301.)
- *
- * Argument is an unsigned 2-byte integer (u_int16_t).
- */
-ENTRY(NAME, 1)
- mux1 r16=in0, at rev
- ;;
- extr.u r8=r16,48,16
- br.ret.sptk.few rp
-END(NAME)
--- sys/libkern/ia64/bswap16.S
+++ /dev/null
@@ -1,35 +0,0 @@
-/*-
- * Copyright (c) 1996 Carnegie-Mellon University.
- * All rights reserved.
- *
- * Author: Chris G. Demetriou
- *
- * Permission to use, copy, modify and distribute this software and
- * its documentation is hereby granted, provided that both the copyright
- * notice and this permission notice appear in all copies of the
- * software, derivative works or modified versions, and any portions
- * thereof, and that both notices appear in supporting documentation.
- *
- * CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS"
- * CONDITION. CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND
- * FOR ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE.
- *
- * Carnegie Mellon requests users of this software to return to
- *
- * Software Distribution Coordinator or Software.Distribution at CS.CMU.EDU
- * School of Computer Science
- * Carnegie Mellon University
- * Pittsburgh PA 15213-3890
- *
- * any improvements or extensions that they make and grant Carnegie the
- * rights to redistribute these changes.
- *
- * from: NetBSD: htons.S,v 1.1 1996/04/17 22:36:54 cgd
- * from: src/sys/libkern/ia64/htons.S,v 1.2 2002/02/18 20:35:21
- *
- * $FreeBSD: src/sys/libkern/ia64/bswap16.S,v 1.2 2005/01/07 00:24:33 imp Exp $
- */
-
-#define NAME __bswap16
-
-#include <libkern/ia64/byte_swap_2.S>
--- sys/libkern/ia64/__moddi3.S
+++ /dev/null
@@ -1,159 +0,0 @@
-.file "__moddi3.s"
-
-// $FreeBSD: src/sys/libkern/ia64/__moddi3.S,v 1.4 2005/01/07 00:24:33 imp Exp $
-
-//-
-// Copyright (c) 2000, Intel Corporation
-// All rights reserved.
-//
-// Contributed 2/15/2000 by Marius Cornea, John Harrison, Cristina Iordache,
-// Ted Kubaska, Bob Norin, and Shane Story of the Computational Software Lab,
-// Intel Corporation.
-//
-// WARRANTY DISCLAIMER
-//
-// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
-// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL INTEL OR ITS
-// CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
-// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
-// PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
-// PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
-// OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY OR TORT (INCLUDING
-// NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
-// SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-//
-// Intel Corporation is the author of this code, and requests that all
-// problem reports or change requests be submitted to it directly at
-// http://developer.intel.com/opensource.
-//
-
-.section .text
-
-// 64-bit signed integer remainder
-
-.proc __moddi3#
-.align 32
-.global __moddi3#
-.align 32
-
-__moddi3:
-
-{ .mii
- alloc r31=ar.pfs,3,0,0,0
- nop.i 0
- nop.i 0
-} { .mmb
-
- // 64-BIT SIGNED INTEGER REMAINDER BEGINS HERE
-
- // general register used:
- // r32 - 64-bit signed integer dividend, called a below
- // r33 - 64-bit signed integer divisor, called b below
- // r8 - 64-bit signed integer result
- // r2 - scratch register
- // floating-point registers used: f6, f7, f8, f9, f10, f11, f12
- // predicate registers used: p6
-
- setf.sig f12=r32 // holds a in integer form
- setf.sig f7=r33
- nop.b 0
-} { .mlx
- nop.m 0
- //movl r2=0x8000000000000000;;
- movl r2=0xffffffffffffffff;;
-} { .mfi
- // get the 2's complement of b
- sub r33=r0,r33
- fcvt.xf f6=f12
- nop.i 0
-} { .mfi
- nop.m 0
- fcvt.xf f7=f7
- nop.i 0;;
-} { .mfi
- nop.m 0
- // Step (1)
- // y0 = 1 / b in f8
- frcpa.s1 f8,p6=f6,f7
- nop.i 0;;
-} { .mfi
- nop.m 0
- // Step (2)
- // q0 = a * y0 in f10
- (p6) fma.s1 f10=f6,f8,f0
- nop.i 0
-} { .mfi
- nop.m 0
- // Step (3)
- // e0 = 1 - b * y0 in f9
- (p6) fnma.s1 f9=f7,f8,f1
- nop.i 0;;
-} { .mfi
- nop.m 0
- // Step (4)
- // q1 = q0 + e0 * q0 in f10
- (p6) fma.s1 f10=f9,f10,f10
- nop.i 0
-} { .mfi
- nop.m 0
- // Step (5)
- // e1 = e0 * e0 in f11
- (p6) fma.s1 f11=f9,f9,f0
- nop.i 0;;
-} { .mfi
- nop.m 0
- // Step (6)
- // y1 = y0 + e0 * y0 in f8
- (p6) fma.s1 f8=f9,f8,f8
- nop.i 0;;
-} { .mfi
- nop.m 0
- // Step (7)
- // q2 = q1 + e1 * q1 in f9
- (p6) fma.s1 f9=f11,f10,f10
- nop.i 0;;
-} { .mfi
- nop.m 0
- // Step (8)
- // y2 = y1 + e1 * y1 in f8
- (p6) fma.s1 f8=f11,f8,f8
- nop.i 0;;
-} { .mfi
- nop.m 0
- // Step (9)
- // r2 = a - b * q2 in f10
- (p6) fnma.s1 f10=f7,f9,f6
- nop.i 0;;
-} { .mfi
- setf.sig f7=r33
- // Step (10)
- // q3 = q2 + r2 * y2 in f8
- (p6) fma.s1 f8=f10,f8,f9
- nop.i 0;;
-} { .mfi
- nop.m 0
- // (11) q = trunc(q3)
- fcvt.fx.trunc.s1 f8=f8
- nop.i 0;;
-} { .mfi
- nop.m 0
- // (12) r = a + (-b) * q
- xma.l f8=f8,f7,f12
- nop.i 0;;
-} { .mib
- getf.sig r8=f8
- nop.i 0
- nop.b 0
-}
-
- // 64-BIT SIGNED INTEGER REMAINDER ENDS HERE
-
-{ .mib
- nop.m 0
- nop.i 0
- br.ret.sptk b0;;
-}
-
-.endp __moddi3
--- sys/libkern/ia64/bswap32.S
+++ /dev/null
@@ -1,35 +0,0 @@
-/*-
- * Copyright (c) 1996 Carnegie-Mellon University.
- * All rights reserved.
- *
- * Author: Chris G. Demetriou
- *
- * Permission to use, copy, modify and distribute this software and
- * its documentation is hereby granted, provided that both the copyright
- * notice and this permission notice appear in all copies of the
- * software, derivative works or modified versions, and any portions
- * thereof, and that both notices appear in supporting documentation.
- *
- * CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS"
- * CONDITION. CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND
- * FOR ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE.
- *
- * Carnegie Mellon requests users of this software to return to
- *
- * Software Distribution Coordinator or Software.Distribution at CS.CMU.EDU
- * School of Computer Science
- * Carnegie Mellon University
- * Pittsburgh PA 15213-3890
- *
- * any improvements or extensions that they make and grant Carnegie the
- * rights to redistribute these changes.
- *
- * from: NetBSD: htonl.S,v 1.1 1996/04/17 22:36:52 cgd
- * from: src/sys/libkern/ia64/htonl.S,v 1.2 2002/02/18 20:35:21
- *
- * $FreeBSD: src/sys/libkern/ia64/bswap32.S,v 1.2 2005/01/07 00:24:33 imp Exp $
- */
-
-#define NAME __bswap32
-
-#include <libkern/ia64/byte_swap_4.S>
--- sys/libkern/ia64/__divdi3.S
+++ /dev/null
@@ -1,142 +0,0 @@
-.file "__divdi3.s"
-
-// $FreeBSD: src/sys/libkern/ia64/__divdi3.S,v 1.2 2005/01/07 00:24:33 imp Exp $
-
-//-
-// Copyright (c) 2000, Intel Corporation
-// All rights reserved.
-//
-// Contributed 2/15/2000 by Marius Cornea, John Harrison, Cristina Iordache,
-// Ted Kubaska, Bob Norin, and Shane Story of the Computational Software Lab,
-// Intel Corporation.
-//
-// WARRANTY DISCLAIMER
-//
-// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
-// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL INTEL OR ITS
-// CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
-// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
-// PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
-// PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
-// OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY OR TORT (INCLUDING
-// NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
-// SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-//
-// Intel Corporation is the author of this code, and requests that all
-// problem reports or change requests be submitted to it directly at
-// http://developer.intel.com/opensource.
-//
-
-.section .text
-.proc __divdi3#
-.align 32
-.global __divdi3#
-.align 32
-
-// 64-bit signed integer divide
-
-__divdi3:
-
-{ .mii
- alloc r31=ar.pfs,2,0,0,0
- nop.i 0
- nop.i 0;;
-} { .mmi
-
- // 64-BIT SIGNED INTEGER DIVIDE BEGINS HERE
-
- setf.sig f8=r32
- setf.sig f9=r33
- nop.i 0;;
-} { .mfb
- nop.m 0
- fcvt.xf f6=f8
- nop.b 0
-} { .mfb
- nop.m 0
- fcvt.xf f7=f9
- nop.b 0;;
-} { .mfi
- nop.m 0
- // Step (1)
- // y0 = 1 / b in f8
- frcpa.s1 f8,p6=f6,f7
- nop.i 0;;
-} { .mfi
- nop.m 0
- // Step (2)
- // e0 = 1 - b * y0 in f9
- (p6) fnma.s1 f9=f7,f8,f1
- nop.i 0
-} { .mfi
- nop.m 0
- // Step (3)
- // q0 = a * y0 in f10
- (p6) fma.s1 f10=f6,f8,f0
- nop.i 0;;
-} { .mfi
- nop.m 0
- // Step (4)
- // e1 = e0 * e0 in f11
- (p6) fma.s1 f11=f9,f9,f0
- nop.i 0
-} { .mfi
- nop.m 0
- // Step (5)
- // q1 = q0 + e0 * q0 in f10
- (p6) fma.s1 f10=f9,f10,f10
- nop.i 0;;
-} { .mfi
- nop.m 0
- // Step (6)
- // y1 = y0 + e0 * y0 in f8
- (p6) fma.s1 f8=f9,f8,f8
- nop.i 0;;
-} { .mfi
- nop.m 0
- // Step (7)
- // q2 = q1 + e1 * q1 in f9
- (p6) fma.s1 f9=f11,f10,f10
- nop.i 0;;
-} { .mfi
- nop.m 0
- // Step (8)
- // y2 = y1 + e1 * y1 in f8
- (p6) fma.s1 f8=f11,f8,f8
- nop.i 0;;
-} { .mfi
- nop.m 0
- // Step (9)
- // r2 = a - b * q2 in f10
- (p6) fnma.s1 f10=f7,f9,f6
- nop.i 0;;
-} { .mfi
- nop.m 0
- // Step (10)
- // q3 = q2 + r2 * y2 in f8
- (p6) fma.s1 f8=f10,f8,f9
- nop.i 0;;
-} { .mfb
- nop.m 0
- // Step (11)
- // q = trunc (q3)
- fcvt.fx.trunc.s1 f8=f8
- nop.b 0;;
-} { .mmi
- // quotient will be in r8 (if b != 0)
- getf.sig r8=f8
- nop.m 0
- nop.i 0;;
-}
-
- // 64-BIT SIGNED INTEGER DIVIDE ENDS HERE
-
-{ .mmb
- nop.m 0
- nop.m 0
- br.ret.sptk b0;;
-}
-
-.endp __divdi3
--- sys/libkern/ia64/__udivdi3.S
+++ /dev/null
@@ -1,143 +0,0 @@
-.file "__udivdi3.s"
-
-// $FreeBSD: src/sys/libkern/ia64/__udivdi3.S,v 1.2 2005/01/07 00:24:33 imp Exp $
-
-//-
-// Copyright (c) 2000, Intel Corporation
-// All rights reserved.
-//
-// Contributed 2/15/2000 by Marius Cornea, John Harrison, Cristina Iordache,
-// Ted Kubaska, Bob Norin, and Shane Story of the Computational Software Lab,
-// Intel Corporation.
-//
-// WARRANTY DISCLAIMER
-//
-// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
-// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL INTEL OR ITS
-// CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
-// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
-// PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
-// PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
-// OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY OR TORT (INCLUDING
-// NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
-// SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-//
-// Intel Corporation is the author of this code, and requests that all
-// problem reports or change requests be submitted to it directly at
-// http://developer.intel.com/opensource.
-//
-
-.section .text
-.proc __udivdi3#
-.align 32
-.global __udivdi3#
-.align 32
-
-// 64-bit unsigned integer divide
-
-__udivdi3:
-
-{ .mii
- alloc r31=ar.pfs,2,0,0,0
- nop.i 0
- nop.i 0;;
-}
-
-{ .mmi
-
- // 64-BIT UNSIGNED INTEGER DIVIDE BEGINS HERE
-
- setf.sig f8=r32
- setf.sig f9=r33
- nop.i 0;;
-} { .mfb
- nop.m 0
- fma.s1 f6=f8,f1,f0
- nop.b 0
-} { .mfb
- nop.m 0
- fma.s1 f7=f9,f1,f0
- nop.b 0;;
-} { .mfi
- nop.m 0
- // Step (1)
- // y0 = 1 / b in f8
- frcpa.s1 f8,p6=f6,f7
- nop.i 0;;
-} { .mfi
- nop.m 0
- // Step (2)
- // e0 = 1 - b * y0 in f9
- (p6) fnma.s1 f9=f7,f8,f1
- nop.i 0
-} { .mfi
- nop.m 0
- // Step (3)
- // q0 = a * y0 in f10
- (p6) fma.s1 f10=f6,f8,f0
- nop.i 0;;
-} { .mfi
- nop.m 0
- // Step (4)
- // e1 = e0 * e0 in f11
- (p6) fma.s1 f11=f9,f9,f0
- nop.i 0
-} { .mfi
- nop.m 0
- // Step (5)
- // q1 = q0 + e0 * q0 in f10
- (p6) fma.s1 f10=f9,f10,f10
- nop.i 0;;
-} { .mfi
- nop.m 0
- // Step (6)
- // y1 = y0 + e0 * y0 in f8
- (p6) fma.s1 f8=f9,f8,f8
- nop.i 0;;
-} { .mfi
- nop.m 0
- // Step (7)
- // q2 = q1 + e1 * q1 in f9
- (p6) fma.s1 f9=f11,f10,f10
- nop.i 0;;
-} { .mfi
- nop.m 0
- // Step (8)
- // y2 = y1 + e1 * y1 in f8
- (p6) fma.s1 f8=f11,f8,f8
- nop.i 0;;
-} { .mfi
- nop.m 0
- // Step (9)
- // r2 = a - b * q2 in f10
- (p6) fnma.s1 f10=f7,f9,f6
- nop.i 0;;
-} { .mfi
- nop.m 0
- // Step (10)
- // q3 = q2 + r2 * y2 in f8
- (p6) fma.s1 f8=f10,f8,f9
- nop.i 0;;
-} { .mfb
- nop.m 0
- // (11) q = trunc(q3)
- fcvt.fxu.trunc.s1 f8=f8
- nop.b 0;;
-} { .mmi
- // quotient will be in r8 (if b != 0)
- getf.sig r8=f8
- nop.m 0
- nop.i 0;;
-}
-
- // 64-BIT UNSIGNED INTEGER DIVIDE ENDS HERE
-
-{ .mmb
- nop.m 0
- nop.m 0
- br.ret.sptk b0;;
-}
-
-.endp __udivdi3
--- sys/libkern/ia64/__umoddi3.S
+++ /dev/null
@@ -1,155 +0,0 @@
-.file "__umoddi3.s"
-
-// $FreeBSD: src/sys/libkern/ia64/__umoddi3.S,v 1.4 2005/01/07 00:24:33 imp Exp $
-
-//-
-// Copyright (c) 2000, Intel Corporation
-// All rights reserved.
-//
-// Contributed 2/15/2000 by Marius Cornea, John Harrison, Cristina Iordache,
-// Ted Kubaska, Bob Norin, and Shane Story of the Computational Software Lab,
-// Intel Corporation.
-//
-// WARRANTY DISCLAIMER
-//
-// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
-// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL INTEL OR ITS
-// CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
-// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
-// PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
-// PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
-// OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY OR TORT (INCLUDING
-// NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
-// SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-//
-// Intel Corporation is the author of this code, and requests that all
-// problem reports or change requests be submitted to it directly at
-// http://developer.intel.com/opensource.
-//
-
-.section .text
-
- // 64-bit unsigned integer remainder
-
-.proc __umoddi3#
-.align 32
-.global __umoddi3#
-.align 32
-
-__umoddi3:
-
-{ .mii
- alloc r31=ar.pfs,3,0,0,0
- nop.i 0
- nop.i 0
-} { .mmb
-
- // 64-BIT UNSIGNED INTEGER REMAINDER BEGINS HERE
-
- // general register used:
- // r32 - 64-bit unsigned integer dividend, called a below
- // r33 - 64-bit unsigned integer divisor, called b below
- // r8 - 64-bit unsigned integer result
- // floating-point registers used: f6, f7, f8, f9, f10, f11, f12
- // predicate registers used: p6
-
- setf.sig f12=r32 // holds a in integer form
- setf.sig f7=r33
- nop.b 0;;
-} { .mfi
- // get 2's complement of b
- sub r33=r0,r33
- fcvt.xuf.s1 f6=f12
- nop.i 0
-} { .mfi
- nop.m 0
- fcvt.xuf.s1 f7=f7
- nop.i 0;;
-} { .mfi
- nop.m 0
- // Step (1)
- // y0 = 1 / b in f8
- frcpa.s1 f8,p6=f6,f7
- nop.i 0;;
-} { .mfi
- nop.m 0
- // Step (2)
- // q0 = a * y0 in f10
- (p6) fma.s1 f10=f6,f8,f0
- nop.i 0
-} { .mfi
- nop.m 0
- // Step (3)
- // e0 = 1 - b * y0 in f9
- (p6) fnma.s1 f9=f7,f8,f1
- nop.i 0;;
-} { .mfi
- nop.m 0
- // Step (4)
- // q1 = q0 + e0 * q0 in f10
- (p6) fma.s1 f10=f9,f10,f10
- nop.i 0
-} { .mfi
- nop.m 0
- // Step (5)
- // e1 = e0 * e0 in f11
- (p6) fma.s1 f11=f9,f9,f0
- nop.i 0;;
-} { .mfi
- nop.m 0
- // Step (6)
- // y1 = y0 + e0 * y0 in f8
- (p6) fma.s1 f8=f9,f8,f8
- nop.i 0;;
-} { .mfi
- nop.m 0
- // Step (7)
- // q2 = q1 + e1 * q1 in f9
- (p6) fma.s1 f9=f11,f10,f10
- nop.i 0;;
-} { .mfi
- nop.m 0
- // Step (8)
- // y2 = y1 + e1 * y1 in f8
- (p6) fma.s1 f8=f11,f8,f8
- nop.i 0;;
-} { .mfi
- nop.m 0
- // Step (9)
- // r2 = a - b * q2 in f10
- (p6) fnma.s1 f10=f7,f9,f6
- nop.i 0;;
-} { .mfi
- // f7=-b
- setf.sig f7=r33
- // Step (10)
- // q3 = q2 + r2 * y2 in f8
- (p6) fma.s1 f8=f10,f8,f9
- nop.i 0;;
-} { .mfi
- nop.m 0
- // (11) q = trunc(q3)
- fcvt.fxu.trunc.s1 f8=f8
- nop.i 0;;
-} { .mfi
- nop.m 0
- // (12) r = a + (-b) * q
- xma.l f8=f8,f7,f12
- nop.i 0;;
-} { .mib
- getf.sig r8=f8
- nop.i 0
- nop.b 0
-}
-
- // 64-BIT UNSIGNED INTEGER REMAINDER ENDS HERE
-
-{ .mib
- nop.m 0
- nop.i 0
- br.ret.sptk b0;;
-}
-
-.endp __umoddi3
--- sys/libkern/ia64/__modsi3.S
+++ /dev/null
@@ -1,131 +0,0 @@
-.file "__modsi3.s"
-
-// $FreeBSD: src/sys/libkern/ia64/__modsi3.S,v 1.2 2005/01/07 00:24:33 imp Exp $
-
-//-
-// Copyright (c) 2000, Intel Corporation
-// All rights reserved.
-//
-// Contributed 2/15/2000 by Marius Cornea, John Harrison, Cristina Iordache,
-// Ted Kubaska, Bob Norin, and Shane Story of the Computational Software Lab,
-// Intel Corporation.
-//
-// WARRANTY DISCLAIMER
-//
-// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
-// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL INTEL OR ITS
-// CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
-// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
-// PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
-// PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
-// OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY OR TORT (INCLUDING
-// NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
-// SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-//
-// Intel Corporation is the author of this code, and requests that all
-// problem reports or change requests be submitted to it directly at
-// http://developer.intel.com/opensource.
-//
-
-.section .text
-
-// 32-bit signed integer remainder
-
-.proc __modsi3#
-.align 32
-.global __modsi3#
-.align 32
-
-__modsi3:
-
-{ .mii
- alloc r31=ar.pfs,2,0,0,0
- nop.i 0
- nop.i 0;;
-} { .mii
- nop.m 0
-
- // 32-BIT SIGNED INTEGER REMAINDER BEGINS HERE
-
- // general register used:
- // r32 - 32-bit signed integer dividend
- // r33 - 32-bit signed integer divisor
- // r8 - 32-bit signed integer result
- // r2 - scratch register
- // floating-point registers used: f6, f7, f8, f9, f10, f11
- // predicate registers used: p6
-
- sxt4 r32=r32
- sxt4 r33=r33;;
-} { .mmb
- setf.sig f11=r32
- setf.sig f7=r33
- nop.b 0;;
-} { .mfi
- // get 2's complement of b
- sub r33=r0,r33
- fcvt.xf f6=f11
- nop.i 0
-} { .mfi
- nop.m 0
- fcvt.xf f7=f7
- mov r2 = 0x0ffdd;;
-} { .mfi
- setf.exp f9 = r2
- // (1) y0
- frcpa.s1 f8,p6=f6,f7
- nop.i 0;;
-} { .mfi
- nop.m 0
- // (2) q0 = a * y0
- (p6) fma.s1 f10=f6,f8,f0
- nop.i 0
-} { .mfi
- nop.m 0
- // (3) e0 = 1 - b * y0
- (p6) fnma.s1 f8=f7,f8,f1
- nop.i 0;;
-} { .mfi
- // 2's complement of b
- setf.sig f7=r33
- // (4) q1 = q0 + e0 * q0
- (p6) fma.s1 f10=f8,f10,f10
- nop.i 0
-} { .mfi
- nop.m 0
- // (5) e1 = e0 * e0 + 2^-34
- (p6) fma.s1 f8=f8,f8,f9
- nop.i 0;;
-} { .mfi
- nop.m 0
- // (6) q2 = q1 + e1 * q1
- (p6) fma.s1 f8=f8,f10,f10
- nop.i 0;;
-} { .mfi
- nop.m 0
- // (7) q = trunc(q2)
- fcvt.fx.trunc.s1 f8=f8
- nop.i 0;;
-} { .mfi
- nop.m 0
- // (8) r = a + (-b) * q
- xma.l f8=f8,f7,f11
- nop.i 0;;
-} { .mmi
- // remainder will be in the least significant 32 bits of r8 (if b != 0)
- getf.sig r8=f8
- nop.m 0
- nop.i 0;;
-}
-
- // 32-BIT SIGNED INTEGER REMAINDER ENDS HERE
-
-{ .mmb
- nop.m 0
- nop.m 0
- br.ret.sptk b0;;
-}
-
-.endp __modsi3
--- sys/libkern/ia64/__udivsi3.S
+++ /dev/null
@@ -1,124 +0,0 @@
-.file "__udivsi3.s"
-
-// $FreeBSD: src/sys/libkern/ia64/__udivsi3.S,v 1.2 2005/01/07 00:24:33 imp Exp $
-
-//-
-// Copyright (c) 2000, Intel Corporation
-// All rights reserved.
-//
-// Contributed 2/15/2000 by Marius Cornea, John Harrison, Cristina Iordache,
-// Ted Kubaska, Bob Norin, and Shane Story of the Computational Software Lab,
-// Intel Corporation.
-//
-// WARRANTY DISCLAIMER
-//
-// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
-// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL INTEL OR ITS
-// CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
-// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
-// PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
-// PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
-// OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY OR TORT (INCLUDING
-// NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
-// SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-//
-// Intel Corporation is the author of this code, and requests that all
-// problem reports or change requests be submitted to it directly at
-// http://developer.intel.com/opensource.
-//
-
-.section .text
-
-// 32-bit unsigned integer divide
-
-.proc __udivsi3#
-.align 32
-.global __udivsi3#
-.align 32
-
-__udivsi3:
-
-{ .mii
- alloc r31=ar.pfs,2,0,0,0
- nop.i 0
- nop.i 0;;
-} { .mii
- nop.m 0
-
- // 32-BIT UNSIGNED INTEGER DIVIDE BEGINS HERE
-
- // general register used:
- // r32 - 32-bit unsigned integer dividend
- // r33 - 32-bit unsigned integer divisor
- // r8 - 32-bit unsigned integer result
- // r2 - scratch register
- // floating-point registers used: f6, f7, f8, f9
- // predicate registers used: p6
-
- zxt4 r32=r32
- zxt4 r33=r33;;
-} { .mmb
- setf.sig f6=r32
- setf.sig f7=r33
- nop.b 0;;
-} { .mfi
- nop.m 0
- fcvt.xf f6=f6
- nop.i 0
-} { .mfi
- nop.m 0
- fcvt.xf f7=f7
- mov r2 = 0x0ffdd;;
-} { .mfi
- setf.exp f9 = r2
- // (1) y0
- frcpa.s1 f8,p6=f6,f7
- nop.i 0;;
-} { .mfi
- nop.m 0
- // (2) q0 = a * y0
- (p6) fma.s1 f6=f6,f8,f0
- nop.i 0
-} { .mfi
- nop.m 0
- // (3) e0 = 1 - b * y0
- (p6) fnma.s1 f7=f7,f8,f1
- nop.i 0;;
-} { .mfi
- nop.m 0
- // (4) q1 = q0 + e0 * q0
- (p6) fma.s1 f6=f7,f6,f6
- nop.i 0
-} { .mfi
- nop.m 0
- // (5) e1 = e0 * e0 + 2^-34
- (p6) fma.s1 f7=f7,f7,f9
- nop.i 0;;
-} { .mfi
- nop.m 0
- // (6) q2 = q1 + e1 * q1
- (p6) fma.s1 f8=f7,f6,f6
- nop.i 0;;
-} { .mfi
- nop.m 0
- // (7) q = trunc(q2)
- fcvt.fxu.trunc.s1 f8=f8
- nop.i 0;;
-} { .mmi
- // quotient will be in the least significant 32 bits of r8 (if b != 0)
- getf.sig r8=f8
- nop.m 0
- nop.i 0;;
-}
-
- // 32-BIT UNSIGNED INTEGER DIVIDE ENDS HERE
-
-{ .mmb
- nop.m 0
- nop.m 0
- br.ret.sptk b0;;
-}
-
-.endp __udivsi3
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