[Midnightbsd-cvs] src [6560] U trunk/sys/dev/e1000: Update em(4) and igb(4) based on FreeBSD 9.2 driver
laffer1 at midnightbsd.org
laffer1 at midnightbsd.org
Sat Dec 28 09:30:48 EST 2013
Revision: 6560
http://svnweb.midnightbsd.org/src/?rev=6560
Author: laffer1
Date: 2013-12-28 09:30:47 -0500 (Sat, 28 Dec 2013)
Log Message:
-----------
Update em(4) and igb(4) based on FreeBSD 9.2 driver
Modified Paths:
--------------
trunk/sys/dev/e1000/LICENSE
trunk/sys/dev/e1000/README
trunk/sys/dev/e1000/e1000_80003es2lan.c
trunk/sys/dev/e1000/e1000_80003es2lan.h
trunk/sys/dev/e1000/e1000_82540.c
trunk/sys/dev/e1000/e1000_82541.c
trunk/sys/dev/e1000/e1000_82541.h
trunk/sys/dev/e1000/e1000_82542.c
trunk/sys/dev/e1000/e1000_82543.c
trunk/sys/dev/e1000/e1000_82543.h
trunk/sys/dev/e1000/e1000_82571.c
trunk/sys/dev/e1000/e1000_82571.h
trunk/sys/dev/e1000/e1000_82575.c
trunk/sys/dev/e1000/e1000_82575.h
trunk/sys/dev/e1000/e1000_api.c
trunk/sys/dev/e1000/e1000_api.h
trunk/sys/dev/e1000/e1000_defines.h
trunk/sys/dev/e1000/e1000_hw.h
trunk/sys/dev/e1000/e1000_i210.c
trunk/sys/dev/e1000/e1000_i210.h
trunk/sys/dev/e1000/e1000_ich8lan.c
trunk/sys/dev/e1000/e1000_ich8lan.h
trunk/sys/dev/e1000/e1000_mac.c
trunk/sys/dev/e1000/e1000_mac.h
trunk/sys/dev/e1000/e1000_manage.c
trunk/sys/dev/e1000/e1000_manage.h
trunk/sys/dev/e1000/e1000_mbx.c
trunk/sys/dev/e1000/e1000_mbx.h
trunk/sys/dev/e1000/e1000_nvm.c
trunk/sys/dev/e1000/e1000_nvm.h
trunk/sys/dev/e1000/e1000_osdep.c
trunk/sys/dev/e1000/e1000_osdep.h
trunk/sys/dev/e1000/e1000_phy.c
trunk/sys/dev/e1000/e1000_phy.h
trunk/sys/dev/e1000/e1000_regs.h
trunk/sys/dev/e1000/e1000_vf.c
trunk/sys/dev/e1000/e1000_vf.h
trunk/sys/dev/e1000/if_em.c
trunk/sys/dev/e1000/if_em.h
trunk/sys/dev/e1000/if_igb.c
trunk/sys/dev/e1000/if_igb.h
trunk/sys/dev/e1000/if_lem.c
trunk/sys/dev/e1000/if_lem.h
Property Changed:
----------------
trunk/sys/dev/e1000/LICENSE
trunk/sys/dev/e1000/README
trunk/sys/dev/e1000/e1000_80003es2lan.c
trunk/sys/dev/e1000/e1000_80003es2lan.h
trunk/sys/dev/e1000/e1000_82540.c
trunk/sys/dev/e1000/e1000_82541.c
trunk/sys/dev/e1000/e1000_82541.h
trunk/sys/dev/e1000/e1000_82542.c
trunk/sys/dev/e1000/e1000_82543.c
trunk/sys/dev/e1000/e1000_82543.h
trunk/sys/dev/e1000/e1000_82571.c
trunk/sys/dev/e1000/e1000_82571.h
trunk/sys/dev/e1000/e1000_82575.c
trunk/sys/dev/e1000/e1000_82575.h
trunk/sys/dev/e1000/e1000_api.c
trunk/sys/dev/e1000/e1000_api.h
trunk/sys/dev/e1000/e1000_defines.h
trunk/sys/dev/e1000/e1000_hw.h
trunk/sys/dev/e1000/e1000_i210.c
trunk/sys/dev/e1000/e1000_i210.h
trunk/sys/dev/e1000/e1000_ich8lan.c
trunk/sys/dev/e1000/e1000_ich8lan.h
trunk/sys/dev/e1000/e1000_mac.c
trunk/sys/dev/e1000/e1000_mac.h
trunk/sys/dev/e1000/e1000_manage.c
trunk/sys/dev/e1000/e1000_manage.h
trunk/sys/dev/e1000/e1000_mbx.c
trunk/sys/dev/e1000/e1000_mbx.h
trunk/sys/dev/e1000/e1000_nvm.c
trunk/sys/dev/e1000/e1000_nvm.h
trunk/sys/dev/e1000/e1000_osdep.c
trunk/sys/dev/e1000/e1000_osdep.h
trunk/sys/dev/e1000/e1000_phy.c
trunk/sys/dev/e1000/e1000_phy.h
trunk/sys/dev/e1000/e1000_regs.h
trunk/sys/dev/e1000/e1000_vf.c
trunk/sys/dev/e1000/e1000_vf.h
trunk/sys/dev/e1000/if_em.c
trunk/sys/dev/e1000/if_em.h
trunk/sys/dev/e1000/if_igb.c
trunk/sys/dev/e1000/if_igb.h
trunk/sys/dev/e1000/if_lem.c
trunk/sys/dev/e1000/if_lem.h
Modified: trunk/sys/dev/e1000/LICENSE
===================================================================
--- trunk/sys/dev/e1000/LICENSE 2013-12-28 14:30:04 UTC (rev 6559)
+++ trunk/sys/dev/e1000/LICENSE 2013-12-28 14:30:47 UTC (rev 6560)
@@ -1,4 +1,4 @@
-$MidnightBSD$
+$FreeBSD: release/9.2.0/sys/dev/e1000/LICENSE 203049 2010-01-26 22:32:22Z jfv $
Copyright (c) 2001-2010, Intel Corporation
All rights reserved.
Property changes on: trunk/sys/dev/e1000/LICENSE
___________________________________________________________________
Deleted: cvs2svn:cvs-rev
## -1 +0,0 ##
-1.4
\ No newline at end of property
Modified: trunk/sys/dev/e1000/README
===================================================================
--- trunk/sys/dev/e1000/README 2013-12-28 14:30:04 UTC (rev 6559)
+++ trunk/sys/dev/e1000/README 2013-12-28 14:30:47 UTC (rev 6560)
@@ -1,4 +1,4 @@
-$MidnightBSD$
+$FreeBSD: release/9.2.0/sys/dev/e1000/README 252899 2013-07-06 22:34:42Z jfv $
FreeBSD* Driver for Intel Network Connection
=============================================
@@ -389,7 +389,7 @@
http://support.intel.com
If an issue is identified, support is through email only at:
-freebsdnic at mailbox.intel.com
+freebsd at intel.com
License
Property changes on: trunk/sys/dev/e1000/README
___________________________________________________________________
Deleted: cvs2svn:cvs-rev
## -1 +0,0 ##
-1.4
\ No newline at end of property
Modified: trunk/sys/dev/e1000/e1000_80003es2lan.c
===================================================================
--- trunk/sys/dev/e1000/e1000_80003es2lan.c 2013-12-28 14:30:04 UTC (rev 6559)
+++ trunk/sys/dev/e1000/e1000_80003es2lan.c 2013-12-28 14:30:47 UTC (rev 6560)
@@ -1,3 +1,4 @@
+/* $MidnightBSD$ */
/******************************************************************************
Copyright (c) 2001-2011, Intel Corporation
@@ -30,7 +31,7 @@
POSSIBILITY OF SUCH DAMAGE.
******************************************************************************/
-/*$MidnightBSD$*/
+/*$FreeBSD: release/9.2.0/sys/dev/e1000/e1000_80003es2lan.c 235527 2012-05-16 22:22:52Z jfv $*/
/*
* 80003ES2LAN Gigabit Ethernet Controller (Copper)
Property changes on: trunk/sys/dev/e1000/e1000_80003es2lan.c
___________________________________________________________________
Deleted: cvs2svn:cvs-rev
## -1 +0,0 ##
-1.4
\ No newline at end of property
Modified: trunk/sys/dev/e1000/e1000_80003es2lan.h
===================================================================
--- trunk/sys/dev/e1000/e1000_80003es2lan.h 2013-12-28 14:30:04 UTC (rev 6559)
+++ trunk/sys/dev/e1000/e1000_80003es2lan.h 2013-12-28 14:30:47 UTC (rev 6560)
@@ -1,3 +1,4 @@
+/* $MidnightBSD$ */
/******************************************************************************
Copyright (c) 2001-2011, Intel Corporation
@@ -30,7 +31,7 @@
POSSIBILITY OF SUCH DAMAGE.
******************************************************************************/
-/*$MidnightBSD$*/
+/*$FreeBSD: release/9.2.0/sys/dev/e1000/e1000_80003es2lan.h 235527 2012-05-16 22:22:52Z jfv $*/
#ifndef _E1000_80003ES2LAN_H_
#define _E1000_80003ES2LAN_H_
Property changes on: trunk/sys/dev/e1000/e1000_80003es2lan.h
___________________________________________________________________
Deleted: cvs2svn:cvs-rev
## -1 +0,0 ##
-1.4
\ No newline at end of property
Modified: trunk/sys/dev/e1000/e1000_82540.c
===================================================================
--- trunk/sys/dev/e1000/e1000_82540.c 2013-12-28 14:30:04 UTC (rev 6559)
+++ trunk/sys/dev/e1000/e1000_82540.c 2013-12-28 14:30:47 UTC (rev 6560)
@@ -1,3 +1,4 @@
+/* $MidnightBSD$ */
/******************************************************************************
Copyright (c) 2001-2011, Intel Corporation
@@ -30,7 +31,7 @@
POSSIBILITY OF SUCH DAMAGE.
******************************************************************************/
-/*$MidnightBSD$*/
+/*$FreeBSD: release/9.2.0/sys/dev/e1000/e1000_82540.c 235527 2012-05-16 22:22:52Z jfv $*/
/*
* 82540EM Gigabit Ethernet Controller
Property changes on: trunk/sys/dev/e1000/e1000_82540.c
___________________________________________________________________
Deleted: cvs2svn:cvs-rev
## -1 +0,0 ##
-1.4
\ No newline at end of property
Modified: trunk/sys/dev/e1000/e1000_82541.c
===================================================================
--- trunk/sys/dev/e1000/e1000_82541.c 2013-12-28 14:30:04 UTC (rev 6559)
+++ trunk/sys/dev/e1000/e1000_82541.c 2013-12-28 14:30:47 UTC (rev 6560)
@@ -1,3 +1,4 @@
+/* $MidnightBSD$ */
/******************************************************************************
Copyright (c) 2001-2011, Intel Corporation
@@ -30,7 +31,7 @@
POSSIBILITY OF SUCH DAMAGE.
******************************************************************************/
-/*$MidnightBSD$*/
+/*$FreeBSD: release/9.2.0/sys/dev/e1000/e1000_82541.c 238262 2012-07-08 20:35:56Z jfv $*/
/*
* 82541EI Gigabit Ethernet Controller
Property changes on: trunk/sys/dev/e1000/e1000_82541.c
___________________________________________________________________
Deleted: cvs2svn:cvs-rev
## -1 +0,0 ##
-1.4
\ No newline at end of property
Modified: trunk/sys/dev/e1000/e1000_82541.h
===================================================================
--- trunk/sys/dev/e1000/e1000_82541.h 2013-12-28 14:30:04 UTC (rev 6559)
+++ trunk/sys/dev/e1000/e1000_82541.h 2013-12-28 14:30:47 UTC (rev 6560)
@@ -1,3 +1,4 @@
+/* $MidnightBSD$ */
/******************************************************************************
Copyright (c) 2001-2008, Intel Corporation
@@ -30,7 +31,7 @@
POSSIBILITY OF SUCH DAMAGE.
******************************************************************************/
-/*$MidnightBSD$*/
+/*$FreeBSD: release/9.2.0/sys/dev/e1000/e1000_82541.h 181027 2008-07-30 21:56:53Z jfv $*/
#ifndef _E1000_82541_H_
#define _E1000_82541_H_
Property changes on: trunk/sys/dev/e1000/e1000_82541.h
___________________________________________________________________
Deleted: cvs2svn:cvs-rev
## -1 +0,0 ##
-1.4
\ No newline at end of property
Modified: trunk/sys/dev/e1000/e1000_82542.c
===================================================================
--- trunk/sys/dev/e1000/e1000_82542.c 2013-12-28 14:30:04 UTC (rev 6559)
+++ trunk/sys/dev/e1000/e1000_82542.c 2013-12-28 14:30:47 UTC (rev 6560)
@@ -1,3 +1,4 @@
+/* $MidnightBSD$ */
/******************************************************************************
Copyright (c) 2001-2010, Intel Corporation
@@ -30,7 +31,7 @@
POSSIBILITY OF SUCH DAMAGE.
******************************************************************************/
-/*$MidnightBSD$*/
+/*$FreeBSD: release/9.2.0/sys/dev/e1000/e1000_82542.c 218581 2011-02-11 17:18:42Z jfv $*/
/*
* 82542 Gigabit Ethernet Controller
Property changes on: trunk/sys/dev/e1000/e1000_82542.c
___________________________________________________________________
Deleted: cvs2svn:cvs-rev
## -1 +0,0 ##
-1.4
\ No newline at end of property
Modified: trunk/sys/dev/e1000/e1000_82543.c
===================================================================
--- trunk/sys/dev/e1000/e1000_82543.c 2013-12-28 14:30:04 UTC (rev 6559)
+++ trunk/sys/dev/e1000/e1000_82543.c 2013-12-28 14:30:47 UTC (rev 6560)
@@ -1,3 +1,4 @@
+/* $MidnightBSD$ */
/******************************************************************************
Copyright (c) 2001-2011, Intel Corporation
@@ -30,7 +31,7 @@
POSSIBILITY OF SUCH DAMAGE.
******************************************************************************/
-/*$MidnightBSD$*/
+/*$FreeBSD: release/9.2.0/sys/dev/e1000/e1000_82543.c 238262 2012-07-08 20:35:56Z jfv $*/
/*
* 82543GC Gigabit Ethernet Controller (Fiber)
Property changes on: trunk/sys/dev/e1000/e1000_82543.c
___________________________________________________________________
Deleted: cvs2svn:cvs-rev
## -1 +0,0 ##
-1.4
\ No newline at end of property
Modified: trunk/sys/dev/e1000/e1000_82543.h
===================================================================
--- trunk/sys/dev/e1000/e1000_82543.h 2013-12-28 14:30:04 UTC (rev 6559)
+++ trunk/sys/dev/e1000/e1000_82543.h 2013-12-28 14:30:47 UTC (rev 6560)
@@ -1,3 +1,4 @@
+/* $MidnightBSD$ */
/******************************************************************************
Copyright (c) 2001-2008, Intel Corporation
@@ -30,7 +31,7 @@
POSSIBILITY OF SUCH DAMAGE.
******************************************************************************/
-/*$MidnightBSD$*/
+/*$FreeBSD: release/9.2.0/sys/dev/e1000/e1000_82543.h 181027 2008-07-30 21:56:53Z jfv $*/
#ifndef _E1000_82543_H_
#define _E1000_82543_H_
Property changes on: trunk/sys/dev/e1000/e1000_82543.h
___________________________________________________________________
Deleted: cvs2svn:cvs-rev
## -1 +0,0 ##
-1.4
\ No newline at end of property
Modified: trunk/sys/dev/e1000/e1000_82571.c
===================================================================
--- trunk/sys/dev/e1000/e1000_82571.c 2013-12-28 14:30:04 UTC (rev 6559)
+++ trunk/sys/dev/e1000/e1000_82571.c 2013-12-28 14:30:47 UTC (rev 6560)
@@ -1,6 +1,7 @@
+/* $MidnightBSD$ */
/******************************************************************************
- Copyright (c) 2001-2011, Intel Corporation
+ Copyright (c) 2001-2013, Intel Corporation
All rights reserved.
Redistribution and use in source and binary forms, with or without
@@ -30,10 +31,9 @@
POSSIBILITY OF SUCH DAMAGE.
******************************************************************************/
-/*$MidnightBSD$*/
+/*$FreeBSD: release/9.2.0/sys/dev/e1000/e1000_82571.c 248292 2013-03-14 22:55:59Z jfv $*/
-/*
- * 82571EB Gigabit Ethernet Controller
+/* 82571EB Gigabit Ethernet Controller
* 82571EB Gigabit Ethernet Controller (Copper)
* 82571EB Gigabit Ethernet Controller (Fiber)
* 82571EB Dual Port Gigabit Mezzanine Adapter
@@ -51,9 +51,6 @@
#include "e1000_api.h"
-static s32 e1000_init_phy_params_82571(struct e1000_hw *hw);
-static s32 e1000_init_nvm_params_82571(struct e1000_hw *hw);
-static s32 e1000_init_mac_params_82571(struct e1000_hw *hw);
static s32 e1000_acquire_nvm_82571(struct e1000_hw *hw);
static void e1000_release_nvm_82571(struct e1000_hw *hw);
static s32 e1000_write_nvm_82571(struct e1000_hw *hw, u16 offset,
@@ -78,7 +75,6 @@
static s32 e1000_fix_nvm_checksum_82571(struct e1000_hw *hw);
static s32 e1000_get_phy_id_82571(struct e1000_hw *hw);
static void e1000_put_hw_semaphore_82571(struct e1000_hw *hw);
-static s32 e1000_get_hw_semaphore_82573(struct e1000_hw *hw);
static void e1000_put_hw_semaphore_82573(struct e1000_hw *hw);
static s32 e1000_get_hw_semaphore_82574(struct e1000_hw *hw);
static void e1000_put_hw_semaphore_82574(struct e1000_hw *hw);
@@ -99,13 +95,13 @@
static s32 e1000_init_phy_params_82571(struct e1000_hw *hw)
{
struct e1000_phy_info *phy = &hw->phy;
- s32 ret_val = E1000_SUCCESS;
+ s32 ret_val;
DEBUGFUNC("e1000_init_phy_params_82571");
if (hw->phy.media_type != e1000_media_type_copper) {
phy->type = e1000_phy_none;
- goto out;
+ return E1000_SUCCESS;
}
phy->addr = 1;
@@ -165,8 +161,7 @@
phy->ops.set_d3_lplu_state = e1000_set_d3_lplu_state_82574;
break;
default:
- ret_val = -E1000_ERR_PHY;
- goto out;
+ return -E1000_ERR_PHY;
break;
}
@@ -174,7 +169,7 @@
ret_val = e1000_get_phy_id_82571(hw);
if (ret_val) {
DEBUGOUT("Error getting PHY ID\n");
- goto out;
+ return ret_val;
}
/* Verify phy id */
@@ -201,7 +196,6 @@
if (ret_val)
DEBUGOUT1("PHY ID unknown: type = 0x%08x\n", phy->id);
-out:
return ret_val;
}
@@ -241,8 +235,7 @@
if (((eecd >> 15) & 0x3) == 0x3) {
nvm->type = e1000_nvm_flash_hw;
nvm->word_size = 2048;
- /*
- * Autonomous Flash update bit must be cleared due
+ /* Autonomous Flash update bit must be cleared due
* to Flash update issue.
*/
eecd &= ~E1000_EECD_AUPDEN;
@@ -254,8 +247,7 @@
nvm->type = e1000_nvm_eeprom_spi;
size = (u16)((eecd & E1000_EECD_SIZE_EX_MASK) >>
E1000_EECD_SIZE_EX_SHIFT);
- /*
- * Added to a constant, "size" becomes the left-shift value
+ /* Added to a constant, "size" becomes the left-shift value
* for setting word_size.
*/
size += NVM_WORD_SIZE_BASE_SHIFT;
@@ -382,12 +374,11 @@
/* FWSM register */
mac->has_fwsm = TRUE;
- /*
- * ARC supported; valid only if manageability features are
+ /* ARC supported; valid only if manageability features are
* enabled.
*/
- mac->arc_subsystem_valid = (E1000_READ_REG(hw, E1000_FWSM) &
- E1000_FWSM_MODE_MASK) ? TRUE : FALSE;
+ mac->arc_subsystem_valid = !!(E1000_READ_REG(hw, E1000_FWSM) &
+ E1000_FWSM_MODE_MASK);
break;
case e1000_82574:
case e1000_82583:
@@ -405,8 +396,7 @@
break;
}
- /*
- * Ensure that the inter-port SWSM.SMBI lock bit is clear before
+ /* Ensure that the inter-port SWSM.SMBI lock bit is clear before
* first NVM or PHY acess. This should be done for single-port
* devices, and for one port only on dual-port devices so that
* for those devices we can still use the SMBI lock to synchronize
@@ -422,8 +412,9 @@
E1000_WRITE_REG(hw, E1000_SWSM2, swsm2 |
E1000_SWSM2_LOCK);
force_clear_smbi = TRUE;
- } else
+ } else {
force_clear_smbi = FALSE;
+ }
break;
default:
force_clear_smbi = TRUE;
@@ -443,10 +434,7 @@
E1000_WRITE_REG(hw, E1000_SWSM, swsm & ~E1000_SWSM_SMBI);
}
- /*
- * Initialze device specific counter of SMBI acquisition
- * timeouts.
- */
+ /* Initialze device specific counter of SMBI acquisition timeouts. */
hw->dev_spec._82571.smb_counter = 0;
return E1000_SUCCESS;
@@ -477,7 +465,7 @@
static s32 e1000_get_phy_id_82571(struct e1000_hw *hw)
{
struct e1000_phy_info *phy = &hw->phy;
- s32 ret_val = E1000_SUCCESS;
+ s32 ret_val;
u16 phy_id = 0;
DEBUGFUNC("e1000_get_phy_id_82571");
@@ -485,8 +473,7 @@
switch (hw->mac.type) {
case e1000_82571:
case e1000_82572:
- /*
- * The 82571 firmware may still be configuring the PHY.
+ /* The 82571 firmware may still be configuring the PHY.
* In this case, we cannot access the PHY until the
* configuration is done. So we explicitly set the
* PHY ID.
@@ -494,29 +481,29 @@
phy->id = IGP01E1000_I_PHY_ID;
break;
case e1000_82573:
- ret_val = e1000_get_phy_id(hw);
+ return e1000_get_phy_id(hw);
break;
case e1000_82574:
case e1000_82583:
ret_val = phy->ops.read_reg(hw, PHY_ID1, &phy_id);
if (ret_val)
- goto out;
+ return ret_val;
phy->id = (u32)(phy_id << 16);
usec_delay(20);
ret_val = phy->ops.read_reg(hw, PHY_ID2, &phy_id);
if (ret_val)
- goto out;
+ return ret_val;
phy->id |= (u32)(phy_id);
phy->revision = (u32)(phy_id & ~PHY_REVISION_MASK);
break;
default:
- ret_val = -E1000_ERR_PHY;
+ return -E1000_ERR_PHY;
break;
}
-out:
- return ret_val;
+
+ return E1000_SUCCESS;
}
/**
@@ -528,7 +515,6 @@
static s32 e1000_get_hw_semaphore_82571(struct e1000_hw *hw)
{
u32 swsm;
- s32 ret_val = E1000_SUCCESS;
s32 sw_timeout = hw->nvm.word_size + 1;
s32 fw_timeout = hw->nvm.word_size + 1;
s32 i = 0;
@@ -535,8 +521,7 @@
DEBUGFUNC("e1000_get_hw_semaphore_82571");
- /*
- * If we have timedout 3 times on trying to acquire
+ /* If we have timedout 3 times on trying to acquire
* the inter-port SMBI semaphore, there is old code
* operating on the other port, and it is not
* releasing SMBI. Modify the number of times that
@@ -576,12 +561,10 @@
/* Release semaphores */
e1000_put_hw_semaphore_82571(hw);
DEBUGOUT("Driver can't access the NVM\n");
- ret_val = -E1000_ERR_NVM;
- goto out;
+ return -E1000_ERR_NVM;
}
-out:
- return ret_val;
+ return E1000_SUCCESS;
}
/**
@@ -613,14 +596,13 @@
static s32 e1000_get_hw_semaphore_82573(struct e1000_hw *hw)
{
u32 extcnf_ctrl;
- s32 ret_val = E1000_SUCCESS;
s32 i = 0;
DEBUGFUNC("e1000_get_hw_semaphore_82573");
extcnf_ctrl = E1000_READ_REG(hw, E1000_EXTCNF_CTRL);
- extcnf_ctrl |= E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP;
do {
+ extcnf_ctrl |= E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP;
E1000_WRITE_REG(hw, E1000_EXTCNF_CTRL, extcnf_ctrl);
extcnf_ctrl = E1000_READ_REG(hw, E1000_EXTCNF_CTRL);
@@ -627,8 +609,6 @@
if (extcnf_ctrl & E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP)
break;
- extcnf_ctrl |= E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP;
-
msec_delay(2);
i++;
} while (i < MDIO_OWNERSHIP_TIMEOUT);
@@ -637,12 +617,10 @@
/* Release semaphores */
e1000_put_hw_semaphore_82573(hw);
DEBUGOUT("Driver can't access the PHY\n");
- ret_val = -E1000_ERR_PHY;
- goto out;
+ return -E1000_ERR_PHY;
}
-out:
- return ret_val;
+ return E1000_SUCCESS;
}
/**
@@ -712,7 +690,7 @@
**/
static s32 e1000_set_d0_lplu_state_82574(struct e1000_hw *hw, bool active)
{
- u16 data = E1000_READ_REG(hw, E1000_POEMB);
+ u32 data = E1000_READ_REG(hw, E1000_POEMB);
DEBUGFUNC("e1000_set_d0_lplu_state_82574");
@@ -738,7 +716,7 @@
**/
static s32 e1000_set_d3_lplu_state_82574(struct e1000_hw *hw, bool active)
{
- u16 data = E1000_READ_REG(hw, E1000_POEMB);
+ u32 data = E1000_READ_REG(hw, E1000_POEMB);
DEBUGFUNC("e1000_set_d3_lplu_state_82574");
@@ -771,7 +749,7 @@
ret_val = e1000_get_hw_semaphore_82571(hw);
if (ret_val)
- goto out;
+ return ret_val;
switch (hw->mac.type) {
case e1000_82573:
@@ -784,7 +762,6 @@
if (ret_val)
e1000_put_hw_semaphore_82571(hw);
-out:
return ret_val;
}
@@ -817,7 +794,7 @@
static s32 e1000_write_nvm_82571(struct e1000_hw *hw, u16 offset, u16 words,
u16 *data)
{
- s32 ret_val = E1000_SUCCESS;
+ s32 ret_val;
DEBUGFUNC("e1000_write_nvm_82571");
@@ -857,31 +834,27 @@
ret_val = e1000_update_nvm_checksum_generic(hw);
if (ret_val)
- goto out;
+ return ret_val;
- /*
- * If our nvm is an EEPROM, then we're done
+ /* If our nvm is an EEPROM, then we're done
* otherwise, commit the checksum to the flash NVM.
*/
if (hw->nvm.type != e1000_nvm_flash_hw)
- goto out;
+ return E1000_SUCCESS;
/* Check for pending operations. */
for (i = 0; i < E1000_FLASH_UPDATES; i++) {
msec_delay(1);
- if ((E1000_READ_REG(hw, E1000_EECD) & E1000_EECD_FLUPD) == 0)
+ if (!(E1000_READ_REG(hw, E1000_EECD) & E1000_EECD_FLUPD))
break;
}
- if (i == E1000_FLASH_UPDATES) {
- ret_val = -E1000_ERR_NVM;
- goto out;
- }
+ if (i == E1000_FLASH_UPDATES)
+ return -E1000_ERR_NVM;
/* Reset the firmware if using STM opcode. */
if ((E1000_READ_REG(hw, E1000_FLOP) & 0xFF00) == E1000_STM_OPCODE) {
- /*
- * The enabling of and the actual reset must be done
+ /* The enabling of and the actual reset must be done
* in two write cycles.
*/
E1000_WRITE_REG(hw, E1000_HICR, E1000_HICR_FW_RESET_ENABLE);
@@ -895,17 +868,14 @@
for (i = 0; i < E1000_FLASH_UPDATES; i++) {
msec_delay(1);
- if ((E1000_READ_REG(hw, E1000_EECD) & E1000_EECD_FLUPD) == 0)
+ if (!(E1000_READ_REG(hw, E1000_EECD) & E1000_EECD_FLUPD))
break;
}
- if (i == E1000_FLASH_UPDATES) {
- ret_val = -E1000_ERR_NVM;
- goto out;
- }
+ if (i == E1000_FLASH_UPDATES)
+ return -E1000_ERR_NVM;
-out:
- return ret_val;
+ return E1000_SUCCESS;
}
/**
@@ -944,19 +914,17 @@
{
struct e1000_nvm_info *nvm = &hw->nvm;
u32 i, eewr = 0;
- s32 ret_val = 0;
+ s32 ret_val = E1000_SUCCESS;
DEBUGFUNC("e1000_write_nvm_eewr_82571");
- /*
- * A check for invalid values: offset too large, too many words,
+ /* A check for invalid values: offset too large, too many words,
* and not enough words.
*/
if ((offset >= nvm->word_size) || (words > (nvm->word_size - offset)) ||
(words == 0)) {
DEBUGOUT("nvm parameter(s) out of bounds\n");
- ret_val = -E1000_ERR_NVM;
- goto out;
+ return -E1000_ERR_NVM;
}
for (i = 0; i < words; i++) {
@@ -975,7 +943,6 @@
break;
}
-out:
return ret_val;
}
@@ -988,7 +955,6 @@
static s32 e1000_get_cfg_done_82571(struct e1000_hw *hw)
{
s32 timeout = PHY_CFG_TIMEOUT;
- s32 ret_val = E1000_SUCCESS;
DEBUGFUNC("e1000_get_cfg_done_82571");
@@ -1001,12 +967,10 @@
}
if (!timeout) {
DEBUGOUT("MNG configuration cycle has not completed.\n");
- ret_val = -E1000_ERR_RESET;
- goto out;
+ return -E1000_ERR_RESET;
}
-out:
- return ret_val;
+ return E1000_SUCCESS;
}
/**
@@ -1023,17 +987,17 @@
static s32 e1000_set_d0_lplu_state_82571(struct e1000_hw *hw, bool active)
{
struct e1000_phy_info *phy = &hw->phy;
- s32 ret_val = E1000_SUCCESS;
+ s32 ret_val;
u16 data;
DEBUGFUNC("e1000_set_d0_lplu_state_82571");
if (!(phy->ops.read_reg))
- goto out;
+ return E1000_SUCCESS;
ret_val = phy->ops.read_reg(hw, IGP02E1000_PHY_POWER_MGMT, &data);
if (ret_val)
- goto out;
+ return ret_val;
if (active) {
data |= IGP02E1000_PM_D0_LPLU;
@@ -1040,22 +1004,23 @@
ret_val = phy->ops.write_reg(hw, IGP02E1000_PHY_POWER_MGMT,
data);
if (ret_val)
- goto out;
+ return ret_val;
/* When LPLU is enabled, we should disable SmartSpeed */
ret_val = phy->ops.read_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
&data);
+ if (ret_val)
+ return ret_val;
data &= ~IGP01E1000_PSCFR_SMART_SPEED;
ret_val = phy->ops.write_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
data);
if (ret_val)
- goto out;
+ return ret_val;
} else {
data &= ~IGP02E1000_PM_D0_LPLU;
ret_val = phy->ops.write_reg(hw, IGP02E1000_PHY_POWER_MGMT,
data);
- /*
- * LPLU and SmartSpeed are mutually exclusive. LPLU is used
+ /* LPLU and SmartSpeed are mutually exclusive. LPLU is used
* during Dx states where the power conservation is most
* important. During driver activity we should enable
* SmartSpeed, so performance is maintained.
@@ -1065,7 +1030,7 @@
IGP01E1000_PHY_PORT_CONFIG,
&data);
if (ret_val)
- goto out;
+ return ret_val;
data |= IGP01E1000_PSCFR_SMART_SPEED;
ret_val = phy->ops.write_reg(hw,
@@ -1072,13 +1037,13 @@
IGP01E1000_PHY_PORT_CONFIG,
data);
if (ret_val)
- goto out;
+ return ret_val;
} else if (phy->smart_speed == e1000_smart_speed_off) {
ret_val = phy->ops.read_reg(hw,
IGP01E1000_PHY_PORT_CONFIG,
&data);
if (ret_val)
- goto out;
+ return ret_val;
data &= ~IGP01E1000_PSCFR_SMART_SPEED;
ret_val = phy->ops.write_reg(hw,
@@ -1085,12 +1050,11 @@
IGP01E1000_PHY_PORT_CONFIG,
data);
if (ret_val)
- goto out;
+ return ret_val;
}
}
-out:
- return ret_val;
+ return E1000_SUCCESS;
}
/**
@@ -1101,13 +1065,12 @@
**/
static s32 e1000_reset_hw_82571(struct e1000_hw *hw)
{
- u32 ctrl, ctrl_ext;
+ u32 ctrl, ctrl_ext, eecd, tctl;
s32 ret_val;
DEBUGFUNC("e1000_reset_hw_82571");
- /*
- * Prevent the PCI-E bus from sticking if there is no TLP connection
+ /* Prevent the PCI-E bus from sticking if there is no TLP connection
* on the last TLP read/write transaction when MAC is reset.
*/
ret_val = e1000_disable_pcie_master_generic(hw);
@@ -1118,13 +1081,14 @@
E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff);
E1000_WRITE_REG(hw, E1000_RCTL, 0);
- E1000_WRITE_REG(hw, E1000_TCTL, E1000_TCTL_PSP);
+ tctl = E1000_READ_REG(hw, E1000_TCTL);
+ tctl &= ~E1000_TCTL_EN;
+ E1000_WRITE_REG(hw, E1000_TCTL, tctl);
E1000_WRITE_FLUSH(hw);
msec_delay(10);
- /*
- * Must acquire the MDIO ownership before MAC reset.
+ /* Must acquire the MDIO ownership before MAC reset.
* Ownership defaults to firmware after a reset.
*/
switch (hw->mac.type) {
@@ -1167,15 +1131,23 @@
ret_val = e1000_get_auto_rd_done_generic(hw);
if (ret_val)
/* We don't want to continue accessing MAC registers. */
- goto out;
+ return ret_val;
- /*
- * Phy configuration from NVM just starts after EECD_AUTO_RD is set.
+ /* Phy configuration from NVM just starts after EECD_AUTO_RD is set.
* Need to wait for Phy configuration completion before accessing
* NVM and Phy.
*/
switch (hw->mac.type) {
+ case e1000_82571:
+ case e1000_82572:
+ /* REQ and GNT bits need to be cleared when using AUTO_RD
+ * to access the EEPROM.
+ */
+ eecd = E1000_READ_REG(hw, E1000_EECD);
+ eecd &= ~(E1000_EECD_REQ | E1000_EECD_GNT);
+ E1000_WRITE_REG(hw, E1000_EECD, eecd);
+ break;
case e1000_82573:
case e1000_82574:
case e1000_82583:
@@ -1193,7 +1165,7 @@
/* Install any alternate MAC address into RAR0 */
ret_val = e1000_check_alt_mac_addr_generic(hw);
if (ret_val)
- goto out;
+ return ret_val;
e1000_set_laa_state_82571(hw, TRUE);
}
@@ -1202,8 +1174,7 @@
if (hw->phy.media_type == e1000_media_type_internal_serdes)
hw->mac.serdes_link_state = e1000_serdes_link_down;
-out:
- return ret_val;
+ return E1000_SUCCESS;
}
/**
@@ -1225,16 +1196,15 @@
/* Initialize identification LED */
ret_val = mac->ops.id_led_init(hw);
+ /* An error is not fatal and we should not stop init due to this */
if (ret_val)
DEBUGOUT("Error initializing identification LED\n");
- /* This is not fatal and we should not stop init due to this */
/* Disabling VLAN filtering */
DEBUGOUT("Initializing the IEEE VLAN\n");
mac->ops.clear_vfta(hw);
- /* Setup the receive address. */
- /*
+ /* Setup the receive address.
* If, however, a locally administered address was assigned to the
* 82571, we must reserve a RAR for it to work around an issue where
* resetting one port will reload the MAC on the other port.
@@ -1277,8 +1247,7 @@
break;
}
- /*
- * Clear all of the statistics registers (clear on read). It is
+ /* Clear all of the statistics registers (clear on read). It is
* important that we do this after we have tried to establish link
* because the symbol error count will increment wildly if there
* is no link.
@@ -1377,8 +1346,7 @@
E1000_WRITE_REG(hw, E1000_PBA_ECC, reg);
}
- /*
- * Workaround for hardware errata.
+ /* Workaround for hardware errata.
* Ensure that DMA Dynamic Clock gating is disabled on 82571 and 82572
*/
if ((hw->mac.type == e1000_82571) ||
@@ -1388,6 +1356,15 @@
E1000_WRITE_REG(hw, E1000_CTRL_EXT, reg);
}
+ /* Disable IPv6 extension header parsing because some malformed
+ * IPv6 headers can hang the Rx.
+ */
+ if (hw->mac.type <= e1000_82573) {
+ reg = E1000_READ_REG(hw, E1000_RFCTL);
+ reg |= (E1000_RFCTL_IPV6_EX_DIS | E1000_RFCTL_NEW_IPV6_EXT_DIS);
+ E1000_WRITE_REG(hw, E1000_RFCTL, reg);
+ }
+
/* PCI-Ex Control Registers */
switch (hw->mac.type) {
case e1000_82574:
@@ -1396,8 +1373,7 @@
reg |= (1 << 22);
E1000_WRITE_REG(hw, E1000_GCR, reg);
- /*
- * Workaround for hardware errata.
+ /* Workaround for hardware errata.
* apply workaround for hardware errata documented in errata
* docs Fixes issue where some error prone or unreliable PCIe
* completions are occurring, particularly with ASPM enabled.
@@ -1435,8 +1411,7 @@
case e1000_82574:
case e1000_82583:
if (hw->mng_cookie.vlan_id != 0) {
- /*
- * The VFTA is a 4096b bit-field, each identifying
+ /* The VFTA is a 4096b bit-field, each identifying
* a single VLAN ID. The following operations
* determine which 32b entry (i.e. offset) into the
* array we want to set the VLAN ID (i.e. bit) of
@@ -1443,9 +1418,11 @@
* the manageability unit.
*/
vfta_offset = (hw->mng_cookie.vlan_id >>
- E1000_VFTA_ENTRY_SHIFT) & E1000_VFTA_ENTRY_MASK;
- vfta_bit_in_reg = 1 << (hw->mng_cookie.vlan_id &
- E1000_VFTA_ENTRY_BIT_SHIFT_MASK);
+ E1000_VFTA_ENTRY_SHIFT) &
+ E1000_VFTA_ENTRY_MASK;
+ vfta_bit_in_reg =
+ 1 << (hw->mng_cookie.vlan_id &
+ E1000_VFTA_ENTRY_BIT_SHIFT_MASK);
}
break;
default:
@@ -1452,8 +1429,7 @@
break;
}
for (offset = 0; offset < E1000_VLAN_FILTER_TBL_SIZE; offset++) {
- /*
- * If the offset we want to clear is the same offset of the
+ /* If the offset we want to clear is the same offset of the
* manageability VLAN ID, then clear all bits except that of
* the manageability unit.
*/
@@ -1495,8 +1471,7 @@
ctrl = hw->mac.ledctl_mode2;
if (!(E1000_STATUS_LU & E1000_READ_REG(hw, E1000_STATUS))) {
- /*
- * If no link, then turn LED on by setting the invert bit
+ /* If no link, then turn LED on by setting the invert bit
* for each LED that's "on" (0x0E) in ledctl_mode2.
*/
for (i = 0; i < 4; i++)
@@ -1519,30 +1494,28 @@
{
u16 status_1kbt = 0;
u16 receive_errors = 0;
- bool phy_hung = FALSE;
- s32 ret_val = E1000_SUCCESS;
+ s32 ret_val;
DEBUGFUNC("e1000_check_phy_82574");
- /*
- * Read PHY Receive Error counter first, if its is max - all F's then
+ /* Read PHY Receive Error counter first, if its is max - all F's then
* read the Base1000T status register If both are max then PHY is hung.
*/
ret_val = hw->phy.ops.read_reg(hw, E1000_RECEIVE_ERROR_COUNTER,
&receive_errors);
if (ret_val)
- goto out;
+ return FALSE;
if (receive_errors == E1000_RECEIVE_ERROR_MAX) {
ret_val = hw->phy.ops.read_reg(hw, E1000_BASE1000T_STATUS,
&status_1kbt);
if (ret_val)
- goto out;
+ return FALSE;
if ((status_1kbt & E1000_IDLE_ERROR_COUNT_MASK) ==
E1000_IDLE_ERROR_COUNT_MASK)
- phy_hung = TRUE;
+ return TRUE;
}
-out:
- return phy_hung;
+
+ return FALSE;
}
@@ -1560,8 +1533,7 @@
{
DEBUGFUNC("e1000_setup_link_82571");
- /*
- * 82573 does not have a word in the NVM to determine
+ /* 82573 does not have a word in the NVM to determine
* the default flow control setting, so we explicitly
* set it to full.
*/
@@ -1608,17 +1580,14 @@
ret_val = e1000_copper_link_setup_igp(hw);
break;
default:
- ret_val = -E1000_ERR_PHY;
+ return -E1000_ERR_PHY;
break;
}
if (ret_val)
- goto out;
+ return ret_val;
- ret_val = e1000_setup_copper_link_generic(hw);
-
-out:
- return ret_val;
+ return e1000_setup_copper_link_generic(hw);
}
/**
@@ -1635,8 +1604,7 @@
switch (hw->mac.type) {
case e1000_82571:
case e1000_82572:
- /*
- * If SerDes loopback mode is entered, there is no form
+ /* If SerDes loopback mode is entered, there is no form
* of reset to take the adapter out of that mode. So we
* have to explicitly take the adapter out of loopback
* mode. This prevents drivers from twiddling their thumbs
@@ -1685,16 +1653,17 @@
ctrl = E1000_READ_REG(hw, E1000_CTRL);
status = E1000_READ_REG(hw, E1000_STATUS);
+ E1000_READ_REG(hw, E1000_RXCW);
+ /* SYNCH bit and IV bit are sticky */
+ usec_delay(10);
rxcw = E1000_READ_REG(hw, E1000_RXCW);
if ((rxcw & E1000_RXCW_SYNCH) && !(rxcw & E1000_RXCW_IV)) {
-
/* Receiver is synchronized with no invalid bits. */
switch (mac->serdes_link_state) {
case e1000_serdes_link_autoneg_complete:
if (!(status & E1000_STATUS_LU)) {
- /*
- * We have lost link, retry autoneg before
+ /* We have lost link, retry autoneg before
* reporting link failure
*/
mac->serdes_link_state =
@@ -1707,15 +1676,12 @@
break;
case e1000_serdes_link_forced_up:
- /*
- * If we are receiving /C/ ordered sets, re-enable
+ /* If we are receiving /C/ ordered sets, re-enable
* auto-negotiation in the TXCW register and disable
* forced link in the Device Control register in an
* attempt to auto-negotiate with our link partner.
- * If the partner code word is null, stop forcing
- * and restart auto negotiation.
*/
- if ((rxcw & E1000_RXCW_C) || !(rxcw & E1000_RXCW_CW)) {
+ if (rxcw & E1000_RXCW_C) {
/* Enable autoneg, and unforce link up */
E1000_WRITE_REG(hw, E1000_TXCW, mac->txcw);
E1000_WRITE_REG(hw, E1000_CTRL,
@@ -1731,8 +1697,7 @@
case e1000_serdes_link_autoneg_progress:
if (rxcw & E1000_RXCW_C) {
- /*
- * We received /C/ ordered sets, meaning the
+ /* We received /C/ ordered sets, meaning the
* link partner has autonegotiated, and we can
* trust the Link Up (LU) status bit.
*/
@@ -1748,8 +1713,7 @@
DEBUGOUT("AN_PROG -> DOWN\n");
}
} else {
- /*
- * The link partner did not autoneg.
+ /* The link partner did not autoneg.
* Force link up and full duplex, and change
* state to forced.
*/
@@ -1774,8 +1738,7 @@
case e1000_serdes_link_down:
default:
- /*
- * The link was down but the receiver has now gained
+ /* The link was down but the receiver has now gained
* valid sync, so lets see if we can bring the link
* up.
*/
@@ -1794,17 +1757,18 @@
mac->serdes_link_state = e1000_serdes_link_down;
DEBUGOUT("ANYSTATE -> DOWN\n");
} else {
- /*
- * Check several times, if Sync and Config
- * both are consistently 1 then simply ignore
- * the Invalid bit and restart Autoneg
+ /* Check several times, if SYNCH bit and CONFIG
+ * bit both are consistently 1 then simply ignore
+ * the IV bit and restart Autoneg
*/
for (i = 0; i < AN_RETRY_COUNT; i++) {
usec_delay(10);
rxcw = E1000_READ_REG(hw, E1000_RXCW);
- if ((rxcw & E1000_RXCW_IV) &&
- !((rxcw & E1000_RXCW_SYNCH) &&
- (rxcw & E1000_RXCW_C))) {
+ if ((rxcw & E1000_RXCW_SYNCH) &&
+ (rxcw & E1000_RXCW_C))
+ continue;
+
+ if (rxcw & E1000_RXCW_IV) {
mac->serdes_has_link = FALSE;
mac->serdes_link_state =
e1000_serdes_link_down;
@@ -1845,7 +1809,7 @@
ret_val = hw->nvm.ops.read(hw, NVM_ID_LED_SETTINGS, 1, data);
if (ret_val) {
DEBUGOUT("NVM Read Error\n");
- goto out;
+ return ret_val;
}
switch (hw->mac.type) {
@@ -1862,8 +1826,7 @@
break;
}
-out:
- return ret_val;
+ return E1000_SUCCESS;
}
/**
@@ -1900,8 +1863,7 @@
/* If workaround is activated... */
if (state)
- /*
- * Hold a copy of the LAA in RAR[14] This is done so that
+ /* Hold a copy of the LAA in RAR[14] This is done so that
* between the time RAR[0] gets clobbered and the time it
* gets fixed, the actual LAA is in one of the RARs and no
* incoming packets directed to this port are dropped.
@@ -1908,7 +1870,7 @@
* Eventually the LAA will be in RAR[0] and RAR[14].
*/
hw->mac.ops.rar_set(hw, hw->mac.addr,
- hw->mac.rar_entry_count - 1);
+ hw->mac.rar_entry_count - 1);
return;
}
@@ -1925,25 +1887,23 @@
static s32 e1000_fix_nvm_checksum_82571(struct e1000_hw *hw)
{
struct e1000_nvm_info *nvm = &hw->nvm;
- s32 ret_val = E1000_SUCCESS;
+ s32 ret_val;
u16 data;
DEBUGFUNC("e1000_fix_nvm_checksum_82571");
if (nvm->type != e1000_nvm_flash_hw)
- goto out;
+ return E1000_SUCCESS;
- /*
- * Check bit 4 of word 10h. If it is 0, firmware is done updating
+ /* Check bit 4 of word 10h. If it is 0, firmware is done updating
* 10h-12h. Checksum may need to be fixed.
*/
ret_val = nvm->ops.read(hw, 0x10, 1, &data);
if (ret_val)
- goto out;
+ return ret_val;
if (!(data & 0x10)) {
- /*
- * Read 0x23 and check bit 15. This bit is a 1
+ /* Read 0x23 and check bit 15. This bit is a 1
* when the checksum has already been fixed. If
* the checksum is still wrong and this bit is a
* 1, we need to return bad checksum. Otherwise,
@@ -1952,19 +1912,20 @@
*/
ret_val = nvm->ops.read(hw, 0x23, 1, &data);
if (ret_val)
- goto out;
+ return ret_val;
if (!(data & 0x8000)) {
data |= 0x8000;
ret_val = nvm->ops.write(hw, 0x23, 1, &data);
if (ret_val)
- goto out;
+ return ret_val;
ret_val = nvm->ops.update(hw);
+ if (ret_val)
+ return ret_val;
}
}
-out:
- return ret_val;
+ return E1000_SUCCESS;
}
@@ -1974,25 +1935,21 @@
**/
static s32 e1000_read_mac_addr_82571(struct e1000_hw *hw)
{
- s32 ret_val = E1000_SUCCESS;
-
DEBUGFUNC("e1000_read_mac_addr_82571");
if (hw->mac.type == e1000_82571) {
- /*
- * If there's an alternate MAC address place it in RAR0
+ s32 ret_val;
+
+ /* If there's an alternate MAC address place it in RAR0
* so that it will override the Si installed default perm
* address.
*/
ret_val = e1000_check_alt_mac_addr_generic(hw);
if (ret_val)
- goto out;
+ return ret_val;
}
- ret_val = e1000_read_mac_addr_generic(hw);
-
-out:
- return ret_val;
+ return e1000_read_mac_addr_generic(hw);
}
/**
@@ -2007,7 +1964,7 @@
struct e1000_phy_info *phy = &hw->phy;
struct e1000_mac_info *mac = &hw->mac;
- if (!(phy->ops.check_reset_block))
+ if (!phy->ops.check_reset_block)
return;
/* If the management interface is not enabled, then power down */
Property changes on: trunk/sys/dev/e1000/e1000_82571.c
___________________________________________________________________
Deleted: cvs2svn:cvs-rev
## -1 +0,0 ##
-1.4
\ No newline at end of property
Modified: trunk/sys/dev/e1000/e1000_82571.h
===================================================================
--- trunk/sys/dev/e1000/e1000_82571.h 2013-12-28 14:30:04 UTC (rev 6559)
+++ trunk/sys/dev/e1000/e1000_82571.h 2013-12-28 14:30:47 UTC (rev 6560)
@@ -1,3 +1,4 @@
+/* $MidnightBSD$ */
/******************************************************************************
Copyright (c) 2001-2010, Intel Corporation
@@ -30,7 +31,7 @@
POSSIBILITY OF SUCH DAMAGE.
******************************************************************************/
-/*$MidnightBSD$*/
+/*$FreeBSD: release/9.2.0/sys/dev/e1000/e1000_82571.h 213234 2010-09-28 00:13:15Z jfv $*/
#ifndef _E1000_82571_H_
#define _E1000_82571_H_
Property changes on: trunk/sys/dev/e1000/e1000_82571.h
___________________________________________________________________
Deleted: cvs2svn:cvs-rev
## -1 +0,0 ##
-1.4
\ No newline at end of property
Modified: trunk/sys/dev/e1000/e1000_82575.c
===================================================================
--- trunk/sys/dev/e1000/e1000_82575.c 2013-12-28 14:30:04 UTC (rev 6559)
+++ trunk/sys/dev/e1000/e1000_82575.c 2013-12-28 14:30:47 UTC (rev 6560)
@@ -1,6 +1,7 @@
+/* $MidnightBSD$ */
/******************************************************************************
- Copyright (c) 2001-2012, Intel Corporation
+ Copyright (c) 2001-2013, Intel Corporation
All rights reserved.
Redistribution and use in source and binary forms, with or without
@@ -30,7 +31,7 @@
POSSIBILITY OF SUCH DAMAGE.
******************************************************************************/
-/*$MidnightBSD$*/
+/*$FreeBSD: release/9.2.0/sys/dev/e1000/e1000_82575.c 248292 2013-03-14 22:55:59Z jfv $*/
/*
* 82575EB Gigabit Network Connection
@@ -144,6 +145,8 @@
break;
case e1000_82580:
case e1000_i350:
+ case e1000_i210:
+ case e1000_i211:
reg = E1000_READ_REG(hw, E1000_MDICNFG);
ext_mdio = !!(reg & E1000_MDICNFG_EXT_MDIO);
break;
@@ -332,6 +335,7 @@
} else {
nvm->type = e1000_nvm_flash_hw;
}
+
/* Function Pointers */
nvm->ops.acquire = e1000_acquire_nvm_82575;
nvm->ops.release = e1000_release_nvm_82575;
@@ -385,12 +389,17 @@
mac->rar_entry_count = E1000_RAR_ENTRIES_82576;
if (mac->type == e1000_82580)
mac->rar_entry_count = E1000_RAR_ENTRIES_82580;
- if (mac->type == e1000_i350) {
+ if (mac->type == e1000_i350)
mac->rar_entry_count = E1000_RAR_ENTRIES_I350;
- /* Enable EEE default settings for i350 */
+
+ /* Enable EEE default settings for EEE supported devices */
+ if (mac->type >= e1000_i350)
dev_spec->eee_disable = FALSE;
- }
+ /* Allow a single clear of the SW semaphore on I210 and newer */
+ if (mac->type >= e1000_i210)
+ dev_spec->clear_semaphore_once = TRUE;
+
/* Set if part includes ASF firmware */
mac->asf_firmware_present = TRUE;
/* FWSM register */
@@ -428,7 +437,7 @@
mac->ops.config_collision_dist = e1000_config_collision_dist_82575;
/* multicast address update */
mac->ops.update_mc_addr_list = e1000_update_mc_addr_list_generic;
- if (hw->mac.type == e1000_i350) {
+ if (mac->type == e1000_i350) {
/* writing VFTA */
mac->ops.write_vfta = e1000_write_vfta_i350;
/* clearing VFTA */
@@ -439,6 +448,9 @@
/* clearing VFTA */
mac->ops.clear_vfta = e1000_clear_vfta_generic;
}
+ if (hw->mac.type >= e1000_82580)
+ mac->ops.validate_mdi_setting =
+ e1000_validate_mdi_setting_crossover_generic;
/* ID LED init */
mac->ops.id_led_init = e1000_id_led_init_generic;
/* blink LED */
@@ -634,6 +646,8 @@
break;
case e1000_82580:
case e1000_i350:
+ case e1000_i210:
+ case e1000_i211:
mdic = E1000_READ_REG(hw, E1000_MDICNFG);
mdic &= E1000_MDICNFG_PHY_MASK;
phy->addr = mdic >> E1000_MDICNFG_PHY_SHIFT;
@@ -1143,6 +1157,15 @@
*/
hw->mac.get_link_status = !hw->mac.serdes_has_link;
+ /*
+ * Configure Flow Control now that Auto-Neg has completed.
+ * First, we need to restore the desired flow control
+ * settings because we may have had to re-autoneg with a
+ * different link partner.
+ */
+ ret_val = e1000_config_fc_after_link_up_generic(hw);
+ if (ret_val)
+ DEBUGOUT("Error configuring flow control\n");
} else {
ret_val = e1000_check_for_copper_link_generic(hw);
}
@@ -1222,6 +1245,7 @@
*duplex = FULL_DUPLEX;
else
*duplex = HALF_DUPLEX;
+
} else {
mac->serdes_has_link = FALSE;
*speed = 0;
@@ -1397,7 +1421,8 @@
static s32 e1000_setup_copper_link_82575(struct e1000_hw *hw)
{
u32 ctrl;
- s32 ret_val;
+ s32 ret_val;
+ u32 phpm_reg;
DEBUGFUNC("e1000_setup_copper_link_82575");
@@ -1406,6 +1431,13 @@
ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
+ /* Clear Go Link Disconnect bit */
+ if (hw->mac.type >= e1000_82580) {
+ phpm_reg = E1000_READ_REG(hw, E1000_82580_PHY_POWER_MGMT);
+ phpm_reg &= ~E1000_82580_PM_GO_LINKD;
+ E1000_WRITE_REG(hw, E1000_82580_PHY_POWER_MGMT, phpm_reg);
+ }
+
ret_val = e1000_setup_serdes_link_82575(hw);
if (ret_val)
goto out;
@@ -1423,12 +1455,17 @@
switch (hw->phy.type) {
case e1000_phy_i210:
case e1000_phy_m88:
- if (hw->phy.id == I347AT4_E_PHY_ID ||
- hw->phy.id == M88E1112_E_PHY_ID ||
- hw->phy.id == M88E1340M_E_PHY_ID)
+ switch (hw->phy.id) {
+ case I347AT4_E_PHY_ID:
+ case M88E1112_E_PHY_ID:
+ case M88E1340M_E_PHY_ID:
+ case I210_I_PHY_ID:
ret_val = e1000_copper_link_setup_m88_gen2(hw);
- else
+ break;
+ default:
ret_val = e1000_copper_link_setup_m88(hw);
+ break;
+ }
break;
case e1000_phy_igp_3:
ret_val = e1000_copper_link_setup_igp(hw);
@@ -1460,7 +1497,7 @@
**/
static s32 e1000_setup_serdes_link_82575(struct e1000_hw *hw)
{
- u32 ctrl_ext, ctrl_reg, reg;
+ u32 ctrl_ext, ctrl_reg, reg, anadv_reg;
bool pcs_autoneg;
s32 ret_val = E1000_SUCCESS;
u16 data;
@@ -1544,26 +1581,47 @@
reg &= ~(E1000_PCS_LCTL_AN_ENABLE | E1000_PCS_LCTL_FLV_LINK_UP |
E1000_PCS_LCTL_FSD | E1000_PCS_LCTL_FORCE_LINK);
- /*
- * We force flow control to prevent the CTRL register values from being
- * overwritten by the autonegotiated flow control values
- */
- reg |= E1000_PCS_LCTL_FORCE_FCTRL;
-
if (pcs_autoneg) {
/* Set PCS register for autoneg */
reg |= E1000_PCS_LCTL_AN_ENABLE | /* Enable Autoneg */
E1000_PCS_LCTL_AN_RESTART; /* Restart autoneg */
+
+ /* Disable force flow control for autoneg */
+ reg &= ~E1000_PCS_LCTL_FORCE_FCTRL;
+
+ /* Configure flow control advertisement for autoneg */
+ anadv_reg = E1000_READ_REG(hw, E1000_PCS_ANADV);
+ anadv_reg &= ~(E1000_TXCW_ASM_DIR | E1000_TXCW_PAUSE);
+
+ switch (hw->fc.requested_mode) {
+ case e1000_fc_full:
+ case e1000_fc_rx_pause:
+ anadv_reg |= E1000_TXCW_ASM_DIR;
+ anadv_reg |= E1000_TXCW_PAUSE;
+ break;
+ case e1000_fc_tx_pause:
+ anadv_reg |= E1000_TXCW_ASM_DIR;
+ break;
+ default:
+ break;
+ }
+
+ E1000_WRITE_REG(hw, E1000_PCS_ANADV, anadv_reg);
+
DEBUGOUT1("Configuring Autoneg:PCS_LCTL=0x%08X\n", reg);
} else {
/* Set PCS register for forced link */
reg |= E1000_PCS_LCTL_FSD; /* Force Speed */
+
+ /* Force flow control for forced link */
+ reg |= E1000_PCS_LCTL_FORCE_FCTRL;
+
DEBUGOUT1("Configuring Forced Link:PCS_LCTL=0x%08X\n", reg);
}
E1000_WRITE_REG(hw, E1000_PCS_LCTL, reg);
- if (!e1000_sgmii_active_82575(hw))
+ if (!pcs_autoneg && !e1000_sgmii_active_82575(hw))
e1000_force_mac_fc_generic(hw);
return ret_val;
@@ -1582,137 +1640,70 @@
**/
static s32 e1000_get_media_type_82575(struct e1000_hw *hw)
{
- u32 lan_id = 0;
- s32 ret_val = E1000_ERR_CONFIG;
struct e1000_dev_spec_82575 *dev_spec = &hw->dev_spec._82575;
+ s32 ret_val = E1000_SUCCESS;
u32 ctrl_ext = 0;
- u32 current_link_mode = 0;
- u16 init_ctrl_wd_3 = 0;
- u8 init_ctrl_wd_3_offset = 0;
- u8 init_ctrl_wd_3_bit_offset = 0;
+ u32 link_mode = 0;
/* Set internal phy as default */
dev_spec->sgmii_active = FALSE;
dev_spec->module_plugged = FALSE;
- /*
- * Check if NVM access method is attached already.
- * If it is then Init Control Word #3 is considered
- * otherwise runtime CSR register content is taken.
- */
-
/* Get CSR setting */
ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
- /* Get link mode setting */
- if ((hw->nvm.ops.read) && (hw->nvm.ops.read != e1000_null_read_nvm)) {
- /* Take link mode from EEPROM */
+ /* extract link mode setting */
+ link_mode = ctrl_ext & E1000_CTRL_EXT_LINK_MODE_MASK;
- /*
- * Get LAN port ID to derive its
- * adequate Init Control Word #3
- */
- lan_id = ((E1000_READ_REG(hw, E1000_STATUS) &
- E1000_STATUS_LAN_ID_MASK) >> E1000_STATUS_LAN_ID_OFFSET);
- /*
- * Derive Init Control Word #3 offset
- * and mask to pick up link mode setting.
- */
- if (hw->mac.type < e1000_82580) {
- init_ctrl_wd_3_offset = lan_id ?
- NVM_INIT_CONTROL3_PORT_A : NVM_INIT_CONTROL3_PORT_B;
- init_ctrl_wd_3_bit_offset = NVM_WORD24_LNK_MODE_OFFSET;
- } else {
- init_ctrl_wd_3_offset =
- NVM_82580_LAN_FUNC_OFFSET(lan_id) +
- NVM_INIT_CONTROL3_PORT_A;
- init_ctrl_wd_3_bit_offset =
- NVM_WORD24_82580_LNK_MODE_OFFSET;
- }
- /* Read Init Control Word #3*/
- hw->nvm.ops.read(hw, init_ctrl_wd_3_offset, 1, &init_ctrl_wd_3);
-
- /*
- * Align link mode bits to
- * their CTRL_EXT location.
- */
- current_link_mode = init_ctrl_wd_3;
- current_link_mode <<= (E1000_CTRL_EXT_LINK_MODE_OFFSET -
- init_ctrl_wd_3_bit_offset);
- current_link_mode &= E1000_CTRL_EXT_LINK_MODE_MASK;
-
- /*
- * Switch to CSR for all but internal PHY.
- */
- if (current_link_mode != E1000_CTRL_EXT_LINK_MODE_GMII)
- /* Take link mode from CSR */
- current_link_mode = ctrl_ext &
- E1000_CTRL_EXT_LINK_MODE_MASK;
- } else {
- /* Take link mode from CSR */
- current_link_mode = ctrl_ext & E1000_CTRL_EXT_LINK_MODE_MASK;
- }
-
- switch (current_link_mode) {
-
+ switch (link_mode) {
case E1000_CTRL_EXT_LINK_MODE_1000BASE_KX:
hw->phy.media_type = e1000_media_type_internal_serdes;
- current_link_mode = E1000_CTRL_EXT_LINK_MODE_1000BASE_KX;
break;
case E1000_CTRL_EXT_LINK_MODE_GMII:
hw->phy.media_type = e1000_media_type_copper;
- current_link_mode = E1000_CTRL_EXT_LINK_MODE_GMII;
break;
case E1000_CTRL_EXT_LINK_MODE_SGMII:
- case E1000_CTRL_EXT_LINK_MODE_PCIE_SERDES:
/* Get phy control interface type set (MDIO vs. I2C)*/
if (e1000_sgmii_uses_mdio_82575(hw)) {
hw->phy.media_type = e1000_media_type_copper;
dev_spec->sgmii_active = TRUE;
- current_link_mode = E1000_CTRL_EXT_LINK_MODE_SGMII;
- } else {
- ret_val = e1000_set_sfp_media_type_82575(hw);
- if (ret_val != E1000_SUCCESS)
- goto out;
- if (hw->phy.media_type ==
- e1000_media_type_internal_serdes) {
- current_link_mode =
- E1000_CTRL_EXT_LINK_MODE_PCIE_SERDES;
- } else if (hw->phy.media_type ==
- e1000_media_type_copper) {
- current_link_mode =
- E1000_CTRL_EXT_LINK_MODE_SGMII;
+ break;
+ }
+ /* fall through for I2C based SGMII */
+ case E1000_CTRL_EXT_LINK_MODE_PCIE_SERDES:
+ /* read media type from SFP EEPROM */
+ ret_val = e1000_set_sfp_media_type_82575(hw);
+ if ((ret_val != E1000_SUCCESS) ||
+ (hw->phy.media_type == e1000_media_type_unknown)) {
+ /*
+ * If media type was not identified then return media
+ * type defined by the CTRL_EXT settings.
+ */
+ hw->phy.media_type = e1000_media_type_internal_serdes;
+
+ if (link_mode == E1000_CTRL_EXT_LINK_MODE_SGMII) {
+ hw->phy.media_type = e1000_media_type_copper;
+ dev_spec->sgmii_active = TRUE;
}
+
+ break;
}
- break;
- default:
- DEBUGOUT("Link mode mask doesn't fit bit field size\n");
- goto out;
- }
- /*
- * Do not change current link mode setting
- * if media type is fibre or has not been
- * recognized.
- */
- if ((hw->phy.media_type != e1000_media_type_unknown) &&
- (hw->phy.media_type != e1000_media_type_fiber)) {
- /* Update link mode */
+
+ /* do not change link mode for 100BaseFX */
+ if (dev_spec->eth_flags.e100_base_fx)
+ break;
+
+ /* change current link mode setting */
ctrl_ext &= ~E1000_CTRL_EXT_LINK_MODE_MASK;
- E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext |
- current_link_mode);
- }
- ret_val = E1000_SUCCESS;
-out:
- /*
- * If media type was not identified then return media type
- * defined by the CTRL_EXT settings.
- */
- if (hw->phy.media_type == e1000_media_type_unknown) {
- if (current_link_mode == E1000_CTRL_EXT_LINK_MODE_SGMII)
- hw->phy.media_type = e1000_media_type_copper;
+ if (hw->phy.media_type == e1000_media_type_copper)
+ ctrl_ext |= E1000_CTRL_EXT_LINK_MODE_SGMII;
else
- hw->phy.media_type = e1000_media_type_internal_serdes;
+ ctrl_ext |= E1000_CTRL_EXT_LINK_MODE_PCIE_SERDES;
+
+ E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
+
+ break;
}
return ret_val;
@@ -1730,40 +1721,52 @@
s32 ret_val = E1000_ERR_CONFIG;
u32 ctrl_ext = 0;
struct e1000_dev_spec_82575 *dev_spec = &hw->dev_spec._82575;
- struct sfp_e1000_flags eth_flags = {0};
+ struct sfp_e1000_flags *eth_flags = &dev_spec->eth_flags;
u8 tranceiver_type = 0;
+ s32 timeout = 3;
- /* Turn I2C interface ON */
+ /* Turn I2C interface ON and power on sfp cage */
ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
+ ctrl_ext &= ~E1000_CTRL_EXT_SDP3_DATA;
E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext | E1000_CTRL_I2C_ENA);
+ E1000_WRITE_FLUSH(hw);
+
/* Read SFP module data */
- ret_val = e1000_read_sfp_data_byte(hw,
+ while (timeout) {
+ ret_val = e1000_read_sfp_data_byte(hw,
E1000_I2CCMD_SFP_DATA_ADDR(E1000_SFF_IDENTIFIER_OFFSET),
&tranceiver_type);
+ if (ret_val == E1000_SUCCESS)
+ break;
+ msec_delay(100);
+ timeout--;
+ }
if (ret_val != E1000_SUCCESS)
goto out;
+
ret_val = e1000_read_sfp_data_byte(hw,
E1000_I2CCMD_SFP_DATA_ADDR(E1000_SFF_ETH_FLAGS_OFFSET),
- (u8 *)ð_flags);
+ (u8 *)eth_flags);
if (ret_val != E1000_SUCCESS)
goto out;
- /*
- * Check if there is some SFP
- * module plugged and powered
- */
+
+ /* Check if there is some SFP module plugged and powered */
if ((tranceiver_type == E1000_SFF_IDENTIFIER_SFP) ||
(tranceiver_type == E1000_SFF_IDENTIFIER_SFF)) {
dev_spec->module_plugged = TRUE;
- if (eth_flags.e1000_base_lx || eth_flags.e1000_base_sx) {
+ if (eth_flags->e1000_base_lx || eth_flags->e1000_base_sx) {
hw->phy.media_type = e1000_media_type_internal_serdes;
- } else if (eth_flags.e1000_base_t) {
+ } else if (eth_flags->e100_base_fx) {
dev_spec->sgmii_active = TRUE;
+ hw->phy.media_type = e1000_media_type_internal_serdes;
+ } else if (eth_flags->e1000_base_t) {
+ dev_spec->sgmii_active = TRUE;
hw->phy.media_type = e1000_media_type_copper;
} else {
- hw->phy.media_type = e1000_media_type_unknown;
- DEBUGOUT("PHY module has not been recognized\n");
- goto out;
+ hw->phy.media_type = e1000_media_type_unknown;
+ DEBUGOUT("PHY module has not been recognized\n");
+ goto out;
}
} else {
hw->phy.media_type = e1000_media_type_unknown;
@@ -2334,6 +2337,10 @@
hw->dev_spec._82575.global_device_reset = FALSE;
+ /* 82580 does not reliably do global_device_reset due to hw errata */
+ if (hw->mac.type == e1000_82580)
+ global_device_reset = FALSE;
+
/* Get current control state. */
ctrl = E1000_READ_REG(hw, E1000_CTRL);
@@ -2660,10 +2667,15 @@
/* enable or disable per user setting */
if (!(hw->dev_spec._82575.eee_disable)) {
+ u32 eee_su = E1000_READ_REG(hw, E1000_EEE_SU);
+
ipcnfg |= (E1000_IPCNFG_EEE_1G_AN | E1000_IPCNFG_EEE_100M_AN);
eeer |= (E1000_EEER_TX_LPI_EN | E1000_EEER_RX_LPI_EN |
E1000_EEER_LPI_FC);
+ /* This bit should not be set in normal operation. */
+ if (eee_su & E1000_EEE_SU_LPI_CLK_STP)
+ DEBUGOUT("LPI Clock Stop Bit should not be set!\n");
} else {
ipcnfg &= ~(E1000_IPCNFG_EEE_1G_AN | E1000_IPCNFG_EEE_100M_AN);
eeer &= ~(E1000_EEER_TX_LPI_EN | E1000_EEER_RX_LPI_EN |
@@ -3275,3 +3287,4 @@
e1000_i2c_stop(hw);
}
+
Property changes on: trunk/sys/dev/e1000/e1000_82575.c
___________________________________________________________________
Deleted: cvs2svn:cvs-rev
## -1 +0,0 ##
-1.4
\ No newline at end of property
Modified: trunk/sys/dev/e1000/e1000_82575.h
===================================================================
--- trunk/sys/dev/e1000/e1000_82575.h 2013-12-28 14:30:04 UTC (rev 6559)
+++ trunk/sys/dev/e1000/e1000_82575.h 2013-12-28 14:30:47 UTC (rev 6560)
@@ -1,6 +1,7 @@
+/* $MidnightBSD$ */
/******************************************************************************
- Copyright (c) 2001-2011, Intel Corporation
+ Copyright (c) 2001-2013, Intel Corporation
All rights reserved.
Redistribution and use in source and binary forms, with or without
@@ -30,7 +31,7 @@
POSSIBILITY OF SUCH DAMAGE.
******************************************************************************/
-/*$MidnightBSD$*/
+/*$FreeBSD: release/9.2.0/sys/dev/e1000/e1000_82575.h 248292 2013-03-14 22:55:59Z jfv $*/
#ifndef _E1000_82575_H_
#define _E1000_82575_H_
@@ -360,10 +361,13 @@
#define E1000_DCA_RXCTRL_DESC_DCA_EN (1 << 5) /* DCA Rx Desc enable */
#define E1000_DCA_RXCTRL_HEAD_DCA_EN (1 << 6) /* DCA Rx Desc header ena */
#define E1000_DCA_RXCTRL_DATA_DCA_EN (1 << 7) /* DCA Rx Desc payload ena */
+#define E1000_DCA_RXCTRL_DESC_RRO_EN (1 << 9) /* DCA Rx Desc Relax Order */
#define E1000_DCA_TXCTRL_CPUID_MASK 0x0000001F /* Tx CPUID Mask */
#define E1000_DCA_TXCTRL_DESC_DCA_EN (1 << 5) /* DCA Tx Desc enable */
+#define E1000_DCA_TXCTRL_DESC_RRO_EN (1 << 9) /* Tx rd Desc Relax Order */
#define E1000_DCA_TXCTRL_TX_WB_RO_EN (1 << 11) /* Tx Desc writeback RO bit */
+#define E1000_DCA_TXCTRL_DATA_RRO_EN (1 << 13) /* Tx rd data Relax Order */
#define E1000_DCA_TXCTRL_CPUID_MASK_82576 0xFF000000 /* Tx CPUID Mask */
#define E1000_DCA_RXCTRL_CPUID_MASK_82576 0xFF000000 /* Rx CPUID Mask */
Property changes on: trunk/sys/dev/e1000/e1000_82575.h
___________________________________________________________________
Deleted: cvs2svn:cvs-rev
## -1 +0,0 ##
-1.4
\ No newline at end of property
Modified: trunk/sys/dev/e1000/e1000_api.c
===================================================================
--- trunk/sys/dev/e1000/e1000_api.c 2013-12-28 14:30:04 UTC (rev 6559)
+++ trunk/sys/dev/e1000/e1000_api.c 2013-12-28 14:30:47 UTC (rev 6560)
@@ -1,6 +1,7 @@
+/* $MidnightBSD$ */
/******************************************************************************
- Copyright (c) 2001-2012, Intel Corporation
+ Copyright (c) 2001-2013, Intel Corporation
All rights reserved.
Redistribution and use in source and binary forms, with or without
@@ -30,7 +31,7 @@
POSSIBILITY OF SUCH DAMAGE.
******************************************************************************/
-/*$MidnightBSD$*/
+/*$FreeBSD: release/9.2.0/sys/dev/e1000/e1000_api.c 248292 2013-03-14 22:55:59Z jfv $*/
#include "e1000_api.h"
@@ -289,6 +290,12 @@
case E1000_DEV_ID_PCH2_LV_V:
mac->type = e1000_pch2lan;
break;
+ case E1000_DEV_ID_PCH_LPT_I217_LM:
+ case E1000_DEV_ID_PCH_LPT_I217_V:
+ case E1000_DEV_ID_PCH_LPTLP_I218_LM:
+ case E1000_DEV_ID_PCH_LPTLP_I218_V:
+ mac->type = e1000_pch_lpt;
+ break;
case E1000_DEV_ID_82575EB_COPPER:
case E1000_DEV_ID_82575EB_FIBER_SERDES:
case E1000_DEV_ID_82575GB_QUAD_COPPER:
@@ -323,6 +330,9 @@
case E1000_DEV_ID_I350_DA4:
mac->type = e1000_i350;
break;
+#if defined(QV_RELEASE) && defined(SPRINGVILLE_FLASHLESS_HW)
+ case E1000_DEV_ID_I210_NVMLESS:
+#endif /* QV_RELEASE && SPRINGVILLE_FLASHLESS_HW */
case E1000_DEV_ID_I210_COPPER:
case E1000_DEV_ID_I210_COPPER_OEM1:
case E1000_DEV_ID_I210_COPPER_IT:
@@ -332,14 +342,17 @@
mac->type = e1000_i210;
break;
case E1000_DEV_ID_I211_COPPER:
- mac->type = e1000_i211;
- break;
+ mac->type = e1000_i211;
+ break;
case E1000_DEV_ID_82576_VF:
+ case E1000_DEV_ID_82576_VF_HV:
mac->type = e1000_vfadapt;
break;
case E1000_DEV_ID_I350_VF:
+ case E1000_DEV_ID_I350_VF_HV:
mac->type = e1000_vfadapt_i350;
break;
+
default:
/* Should never have loaded on this device */
ret_val = -E1000_ERR_MAC_INIT;
@@ -428,6 +441,7 @@
case e1000_ich10lan:
case e1000_pchlan:
case e1000_pch2lan:
+ case e1000_pch_lpt:
e1000_init_function_pointers_ich8lan(hw);
break;
case e1000_82575:
@@ -873,11 +887,7 @@
s32 e1000_mng_host_if_write(struct e1000_hw *hw, u8 *buffer, u16 length,
u16 offset, u8 *sum)
{
- if (hw->mac.ops.mng_host_if_write)
- return hw->mac.ops.mng_host_if_write(hw, buffer, length,
- offset, sum);
-
- return E1000_NOT_IMPLEMENTED;
+ return e1000_mng_host_if_write_generic(hw, buffer, length, offset, sum);
}
/**
@@ -890,10 +900,7 @@
s32 e1000_mng_write_cmd_header(struct e1000_hw *hw,
struct e1000_host_mng_command_header *hdr)
{
- if (hw->mac.ops.mng_write_cmd_header)
- return hw->mac.ops.mng_write_cmd_header(hw, hdr);
-
- return E1000_NOT_IMPLEMENTED;
+ return e1000_mng_write_cmd_header_generic(hw, hdr);
}
/**
@@ -908,23 +915,20 @@
**/
s32 e1000_mng_enable_host_if(struct e1000_hw *hw)
{
- if (hw->mac.ops.mng_enable_host_if)
- return hw->mac.ops.mng_enable_host_if(hw);
-
- return E1000_NOT_IMPLEMENTED;
+ return e1000_mng_enable_host_if_generic(hw);
}
/**
- * e1000_wait_autoneg - Waits for autonegotiation completion
+ * e1000_set_obff_timer - Set Optimized Buffer Flush/Fill timer
* @hw: pointer to the HW structure
+ * @itr: u32 indicating itr value
*
- * Waits for autoneg to complete. Currently no func pointer exists and all
- * implementations are handled in the generic version of this function.
+ * Set the OBFF timer based on the given interrupt rate.
**/
-s32 e1000_wait_autoneg(struct e1000_hw *hw)
+s32 e1000_set_obff_timer(struct e1000_hw *hw, u32 itr)
{
- if (hw->mac.ops.wait_autoneg)
- return hw->mac.ops.wait_autoneg(hw);
+ if (hw->mac.ops.set_obff_timer)
+ return hw->mac.ops.set_obff_timer(hw, itr);
return E1000_SUCCESS;
}
Property changes on: trunk/sys/dev/e1000/e1000_api.c
___________________________________________________________________
Deleted: cvs2svn:cvs-rev
## -1 +0,0 ##
-1.4
\ No newline at end of property
Modified: trunk/sys/dev/e1000/e1000_api.h
===================================================================
--- trunk/sys/dev/e1000/e1000_api.h 2013-12-28 14:30:04 UTC (rev 6559)
+++ trunk/sys/dev/e1000/e1000_api.h 2013-12-28 14:30:47 UTC (rev 6560)
@@ -1,6 +1,7 @@
+/* $MidnightBSD$ */
/******************************************************************************
- Copyright (c) 2001-2012, Intel Corporation
+ Copyright (c) 2001-2013, Intel Corporation
All rights reserved.
Redistribution and use in source and binary forms, with or without
@@ -30,7 +31,7 @@
POSSIBILITY OF SUCH DAMAGE.
******************************************************************************/
-/*$MidnightBSD$*/
+/*$FreeBSD: release/9.2.0/sys/dev/e1000/e1000_api.h 248292 2013-03-14 22:55:59Z jfv $*/
#ifndef _E1000_API_H_
#define _E1000_API_H_
@@ -51,6 +52,7 @@
extern void e1000_shutdown_fiber_serdes_link(struct e1000_hw *hw);
extern void e1000_init_function_pointers_i210(struct e1000_hw *hw);
+s32 e1000_set_obff_timer(struct e1000_hw *hw, u32 itr);
s32 e1000_set_mac_type(struct e1000_hw *hw);
s32 e1000_setup_init_funcs(struct e1000_hw *hw, bool init_device);
s32 e1000_init_mac_params(struct e1000_hw *hw);
@@ -105,7 +107,6 @@
s32 e1000_read_kmrn_reg(struct e1000_hw *hw, u32 offset, u16 *data);
s32 e1000_write_kmrn_reg(struct e1000_hw *hw, u32 offset, u16 data);
s32 e1000_write_nvm(struct e1000_hw *hw, u16 offset, u16 words, u16 *data);
-s32 e1000_wait_autoneg(struct e1000_hw *hw);
s32 e1000_set_d3_lplu_state(struct e1000_hw *hw, bool active);
s32 e1000_set_d0_lplu_state(struct e1000_hw *hw, bool active);
bool e1000_check_mng_mode(struct e1000_hw *hw);
@@ -162,4 +163,6 @@
(((length) > min_frame_size) && \
((length) <= (max_frame_size + VLAN_TAG_SIZE + 1)))))
-#endif
+#define E1000_MAX(a, b) ((a) > (b) ? (a) : (b))
+#define E1000_DIVIDE_ROUND_UP(a, b) (((a) + (b) - 1) / (b)) /* ceil(a/b) */
+#endif /* _E1000_API_H_ */
Property changes on: trunk/sys/dev/e1000/e1000_api.h
___________________________________________________________________
Deleted: cvs2svn:cvs-rev
## -1 +0,0 ##
-1.4
\ No newline at end of property
Modified: trunk/sys/dev/e1000/e1000_defines.h
===================================================================
--- trunk/sys/dev/e1000/e1000_defines.h 2013-12-28 14:30:04 UTC (rev 6559)
+++ trunk/sys/dev/e1000/e1000_defines.h 2013-12-28 14:30:47 UTC (rev 6560)
@@ -1,6 +1,7 @@
+/* $MidnightBSD$ */
/******************************************************************************
- Copyright (c) 2001-2012, Intel Corporation
+ Copyright (c) 2001-2013, Intel Corporation
All rights reserved.
Redistribution and use in source and binary forms, with or without
@@ -30,7 +31,7 @@
POSSIBILITY OF SUCH DAMAGE.
******************************************************************************/
-/*$MidnightBSD$*/
+/*$FreeBSD: release/9.2.0/sys/dev/e1000/e1000_defines.h 248292 2013-03-14 22:55:59Z jfv $*/
#ifndef _E1000_DEFINES_H_
#define _E1000_DEFINES_H_
@@ -43,15 +44,7 @@
/* Wake Up Control */
#define E1000_WUC_APME 0x00000001 /* APM Enable */
#define E1000_WUC_PME_EN 0x00000002 /* PME Enable */
-#define E1000_WUC_PME_STATUS 0x00000004 /* PME Status */
-#define E1000_WUC_APMPME 0x00000008 /* Assert PME on APM Wakeup */
-#define E1000_WUC_LSCWE 0x00000010 /* Link Status wake up enable */
-#define E1000_WUC_PPROXYE 0x00000010 /* Protocol Proxy Enable */
-#define E1000_WUC_LSCWO 0x00000020 /* Link Status wake up override */
-#define E1000_WUC_SPM 0x80000000 /* Enable SPM */
#define E1000_WUC_PHY_WAKE 0x00000100 /* if PHY supports wakeup */
-#define E1000_WUC_FLX6_PHY 0x4000 /* Flexible Filter 6 Enable */
-#define E1000_WUC_FLX7_PHY 0x8000 /* Flexible Filter 7 Enable */
/* Wake Up Filter Control */
#define E1000_WUFC_LNKC 0x00000001 /* Link Status Change Wakeup Enable */
@@ -61,41 +54,7 @@
#define E1000_WUFC_BC 0x00000010 /* Broadcast Wakeup Enable */
#define E1000_WUFC_ARP 0x00000020 /* ARP Request Packet Wakeup Enable */
#define E1000_WUFC_IPV4 0x00000040 /* Directed IPv4 Packet Wakeup Enable */
-#define E1000_WUFC_IPV6 0x00000080 /* Directed IPv6 Packet Wakeup Enable */
-#define E1000_WUFC_IGNORE_TCO_PHY 0x00000800 /* Ignore WakeOn TCO packets */
-#define E1000_WUFC_FLX0_PHY 0x00001000 /* Flexible Filter 0 Enable */
-#define E1000_WUFC_FLX1_PHY 0x00002000 /* Flexible Filter 1 Enable */
-#define E1000_WUFC_FLX2_PHY 0x00004000 /* Flexible Filter 2 Enable */
-#define E1000_WUFC_FLX3_PHY 0x00008000 /* Flexible Filter 3 Enable */
-#define E1000_WUFC_FLX4_PHY 0x00000200 /* Flexible Filter 4 Enable */
-#define E1000_WUFC_FLX5_PHY 0x00000400 /* Flexible Filter 5 Enable */
-#define E1000_WUFC_IGNORE_TCO 0x00008000 /* Ignore WakeOn TCO packets */
#define E1000_WUFC_FLX0 0x00010000 /* Flexible Filter 0 Enable */
-#define E1000_WUFC_FLX1 0x00020000 /* Flexible Filter 1 Enable */
-#define E1000_WUFC_FLX2 0x00040000 /* Flexible Filter 2 Enable */
-#define E1000_WUFC_FLX3 0x00080000 /* Flexible Filter 3 Enable */
-#define E1000_WUFC_FLX4 0x00100000 /* Flexible Filter 4 Enable */
-#define E1000_WUFC_FLX5 0x00200000 /* Flexible Filter 5 Enable */
-#define E1000_WUFC_FLX6 0x00400000 /* Flexible Filter 6 Enable */
-#define E1000_WUFC_FLX7 0x00800000 /* Flexible Filter 7 Enable */
-#define E1000_WUFC_FW_RST 0x80000000 /* Wake on FW Reset Enable */
-#define E1000_WUFC_ALL_FILTERS_PHY_4 0x0000F0FF /* wakeup filters mask */
-#define E1000_WUFC_FLX_OFFSET_PHY 12 /* Flexible Filters bits offset */
-#define E1000_WUFC_FLX_FILTERS_PHY_4 0x0000F000 /* 4 flexible filters mask */
-#define E1000_WUFC_ALL_FILTERS_PHY_6 0x0000F6FF /* 6 wakeup filters mask */
-#define E1000_WUFC_FLX_FILTERS_PHY_6 0x0000F600 /* 6 flexible filters mask */
-#define E1000_WUFC_ALL_FILTERS 0x000F00FF /* all wakeup filters mask */
-#define E1000_WUFC_ALL_FILTERS_6 0x003F00FF /* Mask all 6 wu filters */
-#define E1000_WUFC_ALL_FILTERS_8 0x00FF00FF /* Mask all 8 wu filters */
-#define E1000_WUFC_FLX_OFFSET 16 /* Flexible Filters bits offset */
-#define E1000_WUFC_FLX_FILTERS 0x000F0000 /* 4 flexible filters mask */
-#define E1000_WUFC_FLX_FILTERS_6 0x003F0000 /* 6 flexible filters mask */
-#define E1000_WUFC_FLX_FILTERS_8 0x00FF0000 /* 8 flexible filters mask */
-/*
- * For 82576 to utilize Extended filter masks in addition to
- * existing (filter) masks
- */
-#define E1000_WUFC_EXT_FLX_FILTERS 0x00300000 /* Ext. FLX filter mask */
/* Wake Up Status */
#define E1000_WUS_LNKC E1000_WUFC_LNKC
@@ -103,74 +62,18 @@
#define E1000_WUS_EX E1000_WUFC_EX
#define E1000_WUS_MC E1000_WUFC_MC
#define E1000_WUS_BC E1000_WUFC_BC
-#define E1000_WUS_ARP E1000_WUFC_ARP
-#define E1000_WUS_IPV4 E1000_WUFC_IPV4
-#define E1000_WUS_IPV6 E1000_WUFC_IPV6
-#define E1000_WUS_FLX0_PHY E1000_WUFC_FLX0_PHY
-#define E1000_WUS_FLX1_PHY E1000_WUFC_FLX1_PHY
-#define E1000_WUS_FLX2_PHY E1000_WUFC_FLX2_PHY
-#define E1000_WUS_FLX3_PHY E1000_WUFC_FLX3_PHY
-#define E1000_WUS_FLX_FILTERS_PHY_4 E1000_WUFC_FLX_FILTERS_PHY_4
-#define E1000_WUS_FLX0 E1000_WUFC_FLX0
-#define E1000_WUS_FLX1 E1000_WUFC_FLX1
-#define E1000_WUS_FLX2 E1000_WUFC_FLX2
-#define E1000_WUS_FLX3 E1000_WUFC_FLX3
-#define E1000_WUS_FLX4 E1000_WUFC_FLX4
-#define E1000_WUS_FLX5 E1000_WUFC_FLX5
-#define E1000_WUS_FLX6 E1000_WUFC_FLX6
-#define E1000_WUS_FLX7 E1000_WUFC_FLX7
-#define E1000_WUS_FLX4_PHY E1000_WUFC_FLX4_PHY
-#define E1000_WUS_FLX5_PHY E1000_WUFC_FLX5_PHY
-#define E1000_WUS_FLX6_PHY 0x0400
-#define E1000_WUS_FLX7_PHY 0x0800
-#define E1000_WUS_FLX_FILTERS E1000_WUFC_FLX_FILTERS
-#define E1000_WUS_FLX_FILTERS_6 E1000_WUFC_FLX_FILTERS_6
-#define E1000_WUS_FLX_FILTERS_8 E1000_WUFC_FLX_FILTERS_8
-#define E1000_WUS_FLX_FILTERS_PHY_6 E1000_WUFC_FLX_FILTERS_PHY_6
-/* Wake Up Packet Length */
-#define E1000_WUPL_LENGTH_MASK 0x0FFF /* Only the lower 12 bits are valid */
-
-/* Four Flexible Filters are supported */
-#define E1000_FLEXIBLE_FILTER_COUNT_MAX 4
-/* Six Flexible Filters are supported */
-#define E1000_FLEXIBLE_FILTER_COUNT_MAX_6 6
-/* Eight Flexible Filters are supported */
-#define E1000_FLEXIBLE_FILTER_COUNT_MAX_8 8
-/* Two Extended Flexible Filters are supported (82576) */
-#define E1000_EXT_FLEXIBLE_FILTER_COUNT_MAX 2
-#define E1000_FHFT_LENGTH_OFFSET 0xFC /* Length byte in FHFT */
-#define E1000_FHFT_LENGTH_MASK 0x0FF /* Length in lower byte */
-
-/* Each Flexible Filter is at most 128 (0x80) bytes in length */
-#define E1000_FLEXIBLE_FILTER_SIZE_MAX 128
-
-#define E1000_FFLT_SIZE E1000_FLEXIBLE_FILTER_COUNT_MAX
-#define E1000_FFLT_SIZE_6 E1000_FLEXIBLE_FILTER_COUNT_MAX_6
-#define E1000_FFLT_SIZE_8 E1000_FLEXIBLE_FILTER_COUNT_MAX_8
-#define E1000_FFMT_SIZE E1000_FLEXIBLE_FILTER_SIZE_MAX
-#define E1000_FFVT_SIZE E1000_FLEXIBLE_FILTER_SIZE_MAX
-
/* Extended Device Control */
-#define E1000_CTRL_EXT_GPI0_EN 0x00000001 /* Maps SDP4 to GPI0 */
-#define E1000_CTRL_EXT_GPI1_EN 0x00000002 /* Maps SDP5 to GPI1 */
-#define E1000_CTRL_EXT_PHYINT_EN E1000_CTRL_EXT_GPI1_EN
-#define E1000_CTRL_EXT_GPI2_EN 0x00000004 /* Maps SDP6 to GPI2 */
-#define E1000_CTRL_EXT_GPI3_EN 0x00000008 /* Maps SDP7 to GPI3 */
-/* Reserved (bits 4,5) in >= 82575 */
+#define E1000_CTRL_EXT_LPCD 0x00000004 /* LCD Power Cycle Done */
#define E1000_CTRL_EXT_SDP4_DATA 0x00000010 /* SW Definable Pin 4 data */
-#define E1000_CTRL_EXT_SDP5_DATA 0x00000020 /* SW Definable Pin 5 data */
-#define E1000_CTRL_EXT_PHY_INT E1000_CTRL_EXT_SDP5_DATA
#define E1000_CTRL_EXT_SDP6_DATA 0x00000040 /* SW Definable Pin 6 data */
#define E1000_CTRL_EXT_SDP3_DATA 0x00000080 /* SW Definable Pin 3 data */
/* SDP 4/5 (bits 8,9) are reserved in >= 82575 */
#define E1000_CTRL_EXT_SDP4_DIR 0x00000100 /* Direction of SDP4 0=in 1=out */
-#define E1000_CTRL_EXT_SDP5_DIR 0x00000200 /* Direction of SDP5 0=in 1=out */
#define E1000_CTRL_EXT_SDP6_DIR 0x00000400 /* Direction of SDP6 0=in 1=out */
#define E1000_CTRL_EXT_SDP3_DIR 0x00000800 /* Direction of SDP3 0=in 1=out */
-#define E1000_CTRL_EXT_ASDCHK 0x00001000 /* Initiate an ASD sequence */
+#define E1000_CTRL_EXT_FORCE_SMBUS 0x00000800 /* Force SMBus mode */
#define E1000_CTRL_EXT_EE_RST 0x00002000 /* Reinitialize from EEPROM */
-#define E1000_CTRL_EXT_IPS 0x00004000 /* Invert Power State */
/* Physical Func Reset Done Indication */
#define E1000_CTRL_EXT_PFRSTD 0x00004000
#define E1000_CTRL_EXT_SPD_BYPS 0x00008000 /* Speed Select Bypass */
@@ -179,42 +82,22 @@
#define E1000_CTRL_EXT_LINK_MODE_MASK 0x00C00000
/* Offset of the link mode field in Ctrl Ext register */
#define E1000_CTRL_EXT_LINK_MODE_OFFSET 22
-#define E1000_CTRL_EXT_LINK_MODE_82580_MASK 0x01C00000 /*82580 bit 24:22*/
#define E1000_CTRL_EXT_LINK_MODE_1000BASE_KX 0x00400000
#define E1000_CTRL_EXT_LINK_MODE_GMII 0x00000000
-#define E1000_CTRL_EXT_LINK_MODE_TBI 0x00C00000
-#define E1000_CTRL_EXT_LINK_MODE_KMRN 0x00000000
#define E1000_CTRL_EXT_LINK_MODE_PCIE_SERDES 0x00C00000
-#define E1000_CTRL_EXT_LINK_MODE_PCIX_SERDES 0x00800000
#define E1000_CTRL_EXT_LINK_MODE_SGMII 0x00800000
#define E1000_CTRL_EXT_EIAME 0x01000000
#define E1000_CTRL_EXT_IRCA 0x00000001
-#define E1000_CTRL_EXT_WR_WMARK_MASK 0x03000000
-#define E1000_CTRL_EXT_WR_WMARK_256 0x00000000
-#define E1000_CTRL_EXT_WR_WMARK_320 0x01000000
-#define E1000_CTRL_EXT_WR_WMARK_384 0x02000000
-#define E1000_CTRL_EXT_WR_WMARK_448 0x03000000
-#define E1000_CTRL_EXT_CANC 0x04000000 /* Int delay cancellation */
#define E1000_CTRL_EXT_DRV_LOAD 0x10000000 /* Drv loaded bit for FW */
-/* IAME enable bit (27) was removed in >= 82575 */
#define E1000_CTRL_EXT_IAME 0x08000000 /* Int ACK Auto-mask */
-/* packet buffer parity error detection enabled */
-#define E1000_CRTL_EXT_PB_PAREN 0x01000000
-/* descriptor FIFO parity error detection enable */
-#define E1000_CTRL_EXT_DF_PAREN 0x02000000
-#define E1000_CTRL_EXT_GHOST_PAREN 0x40000000
#define E1000_CTRL_EXT_PBA_CLR 0x80000000 /* PBA Clear */
#define E1000_CTRL_EXT_LSECCK 0x00001000
#define E1000_CTRL_EXT_PHYPDEN 0x00100000
#define E1000_I2CCMD_REG_ADDR_SHIFT 16
-#define E1000_I2CCMD_REG_ADDR 0x00FF0000
#define E1000_I2CCMD_PHY_ADDR_SHIFT 24
-#define E1000_I2CCMD_PHY_ADDR 0x07000000
#define E1000_I2CCMD_OPCODE_READ 0x08000000
#define E1000_I2CCMD_OPCODE_WRITE 0x00000000
-#define E1000_I2CCMD_RESET 0x10000000
#define E1000_I2CCMD_READY 0x20000000
-#define E1000_I2CCMD_INTERRUPT_ENA 0x40000000
#define E1000_I2CCMD_ERROR 0x80000000
#define E1000_I2CCMD_SFP_DATA_ADDR(a) (0x0000 + (a))
#define E1000_I2CCMD_SFP_DIAG_ADDR(a) (0x0100 + (a))
@@ -235,11 +118,9 @@
#define E1000_RXD_STAT_TCPCS 0x20 /* TCP xsum calculated */
#define E1000_RXD_STAT_IPCS 0x40 /* IP xsum calculated */
#define E1000_RXD_STAT_PIF 0x80 /* passed in-exact filter */
-#define E1000_RXD_STAT_CRCV 0x100 /* Speculative CRC Valid */
#define E1000_RXD_STAT_IPIDV 0x200 /* IP identification valid */
#define E1000_RXD_STAT_UDPV 0x400 /* Valid UDP checksum */
#define E1000_RXD_STAT_DYNINT 0x800 /* Pkt caused INT via DYNINT */
-#define E1000_RXD_STAT_ACK 0x8000 /* ACK Packet indication */
#define E1000_RXD_ERR_CE 0x01 /* CRC Error */
#define E1000_RXD_ERR_SE 0x02 /* Symbol Error */
#define E1000_RXD_ERR_SEQ 0x04 /* Sequence Error */
@@ -248,11 +129,8 @@
#define E1000_RXD_ERR_IPE 0x40 /* IP Checksum Error */
#define E1000_RXD_ERR_RXE 0x80 /* Rx Data Error */
#define E1000_RXD_SPC_VLAN_MASK 0x0FFF /* VLAN ID is in lower 12 bits */
-#define E1000_RXD_SPC_PRI_MASK 0xE000 /* Priority is in upper 3 bits */
-#define E1000_RXD_SPC_PRI_SHIFT 13
-#define E1000_RXD_SPC_CFI_MASK 0x1000 /* CFI is bit 12 */
-#define E1000_RXD_SPC_CFI_SHIFT 12
+#define E1000_RXDEXT_STATERR_TST 0x00000100 /* Time Stamp taken */
#define E1000_RXDEXT_STATERR_LB 0x00040000
#define E1000_RXDEXT_STATERR_CE 0x01000000
#define E1000_RXDEXT_STATERR_SE 0x02000000
@@ -262,13 +140,6 @@
#define E1000_RXDEXT_STATERR_IPE 0x40000000
#define E1000_RXDEXT_STATERR_RXE 0x80000000
-#define E1000_RXDEXT_LSECH 0x01000000
-#define E1000_RXDEXT_LSECE_MASK 0x60000000
-#define E1000_RXDEXT_LSECE_NO_ERROR 0x00000000
-#define E1000_RXDEXT_LSECE_NO_SA_MATCH 0x20000000
-#define E1000_RXDEXT_LSECE_REPLAY_DETECT 0x40000000
-#define E1000_RXDEXT_LSECE_BAD_SIG 0x60000000
-
/* mask to determine if packets should be dropped due to frame errors */
#define E1000_RXD_ERR_FRAME_ERR_MASK ( \
E1000_RXD_ERR_CE | \
@@ -285,58 +156,26 @@
E1000_RXDEXT_STATERR_CXE | \
E1000_RXDEXT_STATERR_RXE)
-#define E1000_MRQC_ENABLE_MASK 0x00000007
-#define E1000_MRQC_ENABLE_RSS_2Q 0x00000001
-#define E1000_MRQC_ENABLE_RSS_INT 0x00000004
#define E1000_MRQC_RSS_FIELD_MASK 0xFFFF0000
#define E1000_MRQC_RSS_FIELD_IPV4_TCP 0x00010000
#define E1000_MRQC_RSS_FIELD_IPV4 0x00020000
#define E1000_MRQC_RSS_FIELD_IPV6_TCP_EX 0x00040000
-#define E1000_MRQC_RSS_FIELD_IPV6_EX 0x00080000
#define E1000_MRQC_RSS_FIELD_IPV6 0x00100000
#define E1000_MRQC_RSS_FIELD_IPV6_TCP 0x00200000
#define E1000_RXDPS_HDRSTAT_HDRSP 0x00008000
-#define E1000_RXDPS_HDRSTAT_HDRLEN_MASK 0x000003FF
/* Management Control */
#define E1000_MANC_SMBUS_EN 0x00000001 /* SMBus Enabled - RO */
#define E1000_MANC_ASF_EN 0x00000002 /* ASF Enabled - RO */
-#define E1000_MANC_R_ON_FORCE 0x00000004 /* Reset on Force TCO - RO */
-#define E1000_MANC_RMCP_EN 0x00000100 /* Enable RCMP 026Fh Filtering */
-#define E1000_MANC_0298_EN 0x00000200 /* Enable RCMP 0298h Filtering */
-#define E1000_MANC_IPV4_EN 0x00000400 /* Enable IPv4 */
-#define E1000_MANC_IPV6_EN 0x00000800 /* Enable IPv6 */
-#define E1000_MANC_SNAP_EN 0x00001000 /* Accept LLC/SNAP */
#define E1000_MANC_ARP_EN 0x00002000 /* Enable ARP Request Filtering */
-/* Enable Neighbor Discovery Filtering */
-#define E1000_MANC_NEIGHBOR_EN 0x00004000
-#define E1000_MANC_ARP_RES_EN 0x00008000 /* Enable ARP response Filtering */
-#define E1000_MANC_TCO_RESET 0x00010000 /* TCO Reset Occurred */
#define E1000_MANC_RCV_TCO_EN 0x00020000 /* Receive TCO Packets Enabled */
-#define E1000_MANC_REPORT_STATUS 0x00040000 /* Status Reporting Enabled */
-#define E1000_MANC_RCV_ALL 0x00080000 /* Receive All Enabled */
#define E1000_MANC_BLK_PHY_RST_ON_IDE 0x00040000 /* Block phy resets */
/* Enable MAC address filtering */
#define E1000_MANC_EN_MAC_ADDR_FILTER 0x00100000
/* Enable MNG packets to host memory */
#define E1000_MANC_EN_MNG2HOST 0x00200000
-/* Enable IP address filtering */
-#define E1000_MANC_EN_IP_ADDR_FILTER 0x00400000
-#define E1000_MANC_EN_XSUM_FILTER 0x00800000 /* Ena checksum filtering */
-#define E1000_MANC_BR_EN 0x01000000 /* Ena broadcast filtering */
-#define E1000_MANC_SMB_REQ 0x01000000 /* SMBus Request */
-#define E1000_MANC_SMB_GNT 0x02000000 /* SMBus Grant */
-#define E1000_MANC_SMB_CLK_IN 0x04000000 /* SMBus Clock In */
-#define E1000_MANC_SMB_DATA_IN 0x08000000 /* SMBus Data In */
-#define E1000_MANC_SMB_DATA_OUT 0x10000000 /* SMBus Data Out */
-#define E1000_MANC_SMB_CLK_OUT 0x20000000 /* SMBus Clock Out */
-#define E1000_MANC_MPROXYE 0x40000000 /* Mngment Proxy Enable */
-#define E1000_MANC_EN_BMC2OS 0x10000000 /* OS2BMC is enabld or not */
-#define E1000_MANC_SMB_DATA_OUT_SHIFT 28 /* SMBus Data Out Shift */
-#define E1000_MANC_SMB_CLK_OUT_SHIFT 29 /* SMBus Clock Out Shift */
-
#define E1000_MANC2H_PORT_623 0x00000020 /* Port 0x26f */
#define E1000_MANC2H_PORT_664 0x00000040 /* Port 0x298 */
#define E1000_MDEF_PORT_623 0x00000800 /* Port 0x26f */
@@ -351,19 +190,11 @@
#define E1000_RCTL_LPE 0x00000020 /* long packet enable */
#define E1000_RCTL_LBM_NO 0x00000000 /* no loopback mode */
#define E1000_RCTL_LBM_MAC 0x00000040 /* MAC loopback mode */
-#define E1000_RCTL_LBM_SLP 0x00000080 /* serial link loopback mode */
#define E1000_RCTL_LBM_TCVR 0x000000C0 /* tcvr loopback mode */
-#define E1000_RCTL_DTYP_MASK 0x00000C00 /* Descriptor type mask */
#define E1000_RCTL_DTYP_PS 0x00000400 /* Packet Split descriptor */
#define E1000_RCTL_RDMTS_HALF 0x00000000 /* Rx desc min thresh size */
-#define E1000_RCTL_RDMTS_QUAT 0x00000100 /* Rx desc min thresh size */
-#define E1000_RCTL_RDMTS_EIGTH 0x00000200 /* Rx desc min thresh size */
#define E1000_RCTL_MO_SHIFT 12 /* multicast offset shift */
-#define E1000_RCTL_MO_0 0x00000000 /* multicast offset 11:0 */
-#define E1000_RCTL_MO_1 0x00001000 /* multicast offset 12:1 */
-#define E1000_RCTL_MO_2 0x00002000 /* multicast offset 13:2 */
#define E1000_RCTL_MO_3 0x00003000 /* multicast offset 15:4 */
-#define E1000_RCTL_MDR 0x00004000 /* multicast desc ring 0 */
#define E1000_RCTL_BAM 0x00008000 /* broadcast enable */
/* these buffer sizes are valid if E1000_RCTL_BSEX is 0 */
#define E1000_RCTL_SZ_2048 0x00000000 /* Rx buffer size 2048 */
@@ -381,11 +212,8 @@
#define E1000_RCTL_PMCF 0x00800000 /* pass MAC control frames */
#define E1000_RCTL_BSEX 0x02000000 /* Buffer size extension */
#define E1000_RCTL_SECRC 0x04000000 /* Strip Ethernet CRC */
-#define E1000_RCTL_FLXBUF_MASK 0x78000000 /* Flexible buffer size */
-#define E1000_RCTL_FLXBUF_SHIFT 27 /* Flexible buffer shift */
-/*
- * Use byte values for the following shift parameters
+/* Use byte values for the following shift parameters
* Usage:
* psrctl |= (((ROUNDUP(value0, 128) >> E1000_PSRCTL_BSIZE0_SHIFT) &
* E1000_PSRCTL_BSIZE0_MASK) |
@@ -420,16 +248,11 @@
#define E1000_SWFW_PHY3_SM 0x40
#define E1000_SWFW_SW_MNG_SM 0x400
-/* FACTPS Definitions */
-#define E1000_FACTPS_LFS 0x40000000 /* LAN Function Select */
/* Device Control */
#define E1000_CTRL_FD 0x00000001 /* Full duplex.0=half; 1=full */
-#define E1000_CTRL_BEM 0x00000002 /* Endian Mode.0=little,1=big */
#define E1000_CTRL_PRIOR 0x00000004 /* Priority on PCI. 0=rx,1=fair */
#define E1000_CTRL_GIO_MASTER_DISABLE 0x00000004 /*Blocks new Master reqs */
#define E1000_CTRL_LRST 0x00000008 /* Link reset. 0=normal,1=reset */
-#define E1000_CTRL_TME 0x00000010 /* Test mode. 0=normal,1=test */
-#define E1000_CTRL_SLE 0x00000020 /* Serial Link on 0=dis,1=en */
#define E1000_CTRL_ASDE 0x00000020 /* Auto-speed detect enable */
#define E1000_CTRL_SLU 0x00000040 /* Set link up (Force Link) */
#define E1000_CTRL_ILOS 0x00000080 /* Invert Loss-Of Signal */
@@ -437,50 +260,35 @@
#define E1000_CTRL_SPD_10 0x00000000 /* Force 10Mb */
#define E1000_CTRL_SPD_100 0x00000100 /* Force 100Mb */
#define E1000_CTRL_SPD_1000 0x00000200 /* Force 1Gb */
-#define E1000_CTRL_BEM32 0x00000400 /* Big Endian 32 mode */
#define E1000_CTRL_FRCSPD 0x00000800 /* Force Speed */
#define E1000_CTRL_FRCDPX 0x00001000 /* Force Duplex */
-#define E1000_CTRL_D_UD_EN 0x00002000 /* Dock/Undock enable */
-/* Defined polarity of Dock/Undock indication in SDP[0] */
-#define E1000_CTRL_D_UD_POLARITY 0x00004000
-/* Reset both PHY ports, through PHYRST_N pin */
-#define E1000_CTRL_FORCE_PHY_RESET 0x00008000
-/* enable link status from external LINK_0 and LINK_1 pins */
-#define E1000_CTRL_EXT_LINK_EN 0x00010000
#define E1000_CTRL_LANPHYPC_OVERRIDE 0x00010000 /* SW control of LANPHYPC */
#define E1000_CTRL_LANPHYPC_VALUE 0x00020000 /* SW value of LANPHYPC */
+#define E1000_CTRL_MEHE 0x00080000 /* Memory Error Handling Enable */
#define E1000_CTRL_SWDPIN0 0x00040000 /* SWDPIN 0 value */
#define E1000_CTRL_SWDPIN1 0x00080000 /* SWDPIN 1 value */
#define E1000_CTRL_SWDPIN2 0x00100000 /* SWDPIN 2 value */
#define E1000_CTRL_ADVD3WUC 0x00100000 /* D3 WUC */
+#define E1000_CTRL_EN_PHY_PWR_MGMT 0x00200000 /* PHY PM enable */
#define E1000_CTRL_SWDPIN3 0x00200000 /* SWDPIN 3 value */
#define E1000_CTRL_SWDPIO0 0x00400000 /* SWDPIN 0 Input or output */
-#define E1000_CTRL_SWDPIO1 0x00800000 /* SWDPIN 1 input or output */
#define E1000_CTRL_SWDPIO2 0x01000000 /* SWDPIN 2 input or output */
#define E1000_CTRL_SWDPIO3 0x02000000 /* SWDPIN 3 input or output */
#define E1000_CTRL_RST 0x04000000 /* Global reset */
#define E1000_CTRL_RFCE 0x08000000 /* Receive Flow Control enable */
#define E1000_CTRL_TFCE 0x10000000 /* Transmit flow control enable */
-#define E1000_CTRL_RTE 0x20000000 /* Routing tag enable */
#define E1000_CTRL_VME 0x40000000 /* IEEE VLAN mode enable */
#define E1000_CTRL_PHY_RST 0x80000000 /* PHY Reset */
-#define E1000_CTRL_SW2FW_INT 0x02000000 /* Initiate an interrupt to ME */
#define E1000_CTRL_I2C_ENA 0x02000000 /* I2C enable */
-/*
- * Bit definitions for the Management Data IO (MDIO) and Management Data
- * Clock (MDC) pins in the Device Control Register.
- */
-#define E1000_CTRL_PHY_RESET_DIR E1000_CTRL_SWDPIO0
-#define E1000_CTRL_PHY_RESET E1000_CTRL_SWDPIN0
#define E1000_CTRL_MDIO_DIR E1000_CTRL_SWDPIO2
#define E1000_CTRL_MDIO E1000_CTRL_SWDPIN2
#define E1000_CTRL_MDC_DIR E1000_CTRL_SWDPIO3
#define E1000_CTRL_MDC E1000_CTRL_SWDPIN3
-#define E1000_CTRL_PHY_RESET_DIR4 E1000_CTRL_EXT_SDP4_DIR
-#define E1000_CTRL_PHY_RESET4 E1000_CTRL_EXT_SDP4_DATA
#define E1000_CONNSW_ENRGSRC 0x4
+#define E1000_CONNSW_PHYSD 0x400
+#define E1000_CONNSW_SERDESD 0x200
#define E1000_PCS_CFG_PCS_EN 8
#define E1000_PCS_LCTL_FLV_LINK_UP 1
#define E1000_PCS_LCTL_FSV_10 0
@@ -489,29 +297,18 @@
#define E1000_PCS_LCTL_FDV_FULL 8
#define E1000_PCS_LCTL_FSD 0x10
#define E1000_PCS_LCTL_FORCE_LINK 0x20
-#define E1000_PCS_LCTL_LOW_LINK_LATCH 0x40
#define E1000_PCS_LCTL_FORCE_FCTRL 0x80
#define E1000_PCS_LCTL_AN_ENABLE 0x10000
#define E1000_PCS_LCTL_AN_RESTART 0x20000
#define E1000_PCS_LCTL_AN_TIMEOUT 0x40000
-#define E1000_PCS_LCTL_AN_SGMII_BYPASS 0x80000
-#define E1000_PCS_LCTL_AN_SGMII_TRIGGER 0x100000
-#define E1000_PCS_LCTL_FAST_LINK_TIMER 0x1000000
-#define E1000_PCS_LCTL_LINK_OK_FIX 0x2000000
-#define E1000_PCS_LCTL_CRS_ON_NI 0x4000000
#define E1000_ENABLE_SERDES_LOOPBACK 0x0410
#define E1000_PCS_LSTS_LINK_OK 1
-#define E1000_PCS_LSTS_SPEED_10 0
#define E1000_PCS_LSTS_SPEED_100 2
#define E1000_PCS_LSTS_SPEED_1000 4
#define E1000_PCS_LSTS_DUPLEX_FULL 8
#define E1000_PCS_LSTS_SYNK_OK 0x10
#define E1000_PCS_LSTS_AN_COMPLETE 0x10000
-#define E1000_PCS_LSTS_AN_PAGE_RX 0x20000
-#define E1000_PCS_LSTS_AN_TIMED_OUT 0x40000
-#define E1000_PCS_LSTS_AN_REMOTE_FAULT 0x80000
-#define E1000_PCS_LSTS_AN_ERROR_RWS 0x100000
/* Device Status */
#define E1000_STATUS_FD 0x00000001 /* Duplex 0=half 1=full */
@@ -518,36 +315,19 @@
#define E1000_STATUS_LU 0x00000002 /* Link up.0=no,1=link */
#define E1000_STATUS_FUNC_MASK 0x0000000C /* PCI Function Mask */
#define E1000_STATUS_FUNC_SHIFT 2
-#define E1000_STATUS_FUNC_0 0x00000000 /* Function 0 */
#define E1000_STATUS_FUNC_1 0x00000004 /* Function 1 */
#define E1000_STATUS_TXOFF 0x00000010 /* transmission paused */
-#define E1000_STATUS_TBIMODE 0x00000020 /* TBI mode */
-#define E1000_STATUS_SPEED_MASK 0x000000C0
+#define E1000_STATUS_SPEED_MASK 0x000000C0
#define E1000_STATUS_SPEED_10 0x00000000 /* Speed 10Mb/s */
#define E1000_STATUS_SPEED_100 0x00000040 /* Speed 100Mb/s */
#define E1000_STATUS_SPEED_1000 0x00000080 /* Speed 1000Mb/s */
#define E1000_STATUS_LAN_INIT_DONE 0x00000200 /* Lan Init Compltn by NVM */
-#define E1000_STATUS_ASDV 0x00000300 /* Auto speed detect value */
#define E1000_STATUS_PHYRA 0x00000400 /* PHY Reset Asserted */
-/* Change in Dock/Undock state clear on write '0'. */
-#define E1000_STATUS_DOCK_CI 0x00000800
#define E1000_STATUS_GIO_MASTER_ENABLE 0x00080000 /* Master request status */
-#define E1000_STATUS_MTXCKOK 0x00000400 /* MTX clock running OK */
#define E1000_STATUS_PCI66 0x00000800 /* In 66Mhz slot */
#define E1000_STATUS_BUS64 0x00001000 /* In 64 bit slot */
#define E1000_STATUS_PCIX_MODE 0x00002000 /* PCI-X mode */
#define E1000_STATUS_PCIX_SPEED 0x0000C000 /* PCI-X bus speed */
-#define E1000_STATUS_BMC_SKU_0 0x00100000 /* BMC USB redirect disbld */
-#define E1000_STATUS_BMC_SKU_1 0x00200000 /* BMC SRAM disabled */
-#define E1000_STATUS_BMC_SKU_2 0x00400000 /* BMC SDRAM disabled */
-#define E1000_STATUS_BMC_CRYPTO 0x00800000 /* BMC crypto disabled */
-/* BMC external code execution disabled */
-#define E1000_STATUS_BMC_LITE 0x01000000
-#define E1000_STATUS_RGMII_ENABLE 0x02000000 /* RGMII disabled */
-#define E1000_STATUS_FUSE_8 0x04000000
-#define E1000_STATUS_FUSE_9 0x08000000
-#define E1000_STATUS_SERDES0_DIS 0x10000000 /* SERDES disbld on port 0 */
-#define E1000_STATUS_SERDES1_DIS 0x20000000 /* SERDES disbld on port 1 */
/* Constants used to interpret the masked PCI-X bus speed. */
#define E1000_STATUS_PCIX_SPEED_66 0x00000000 /* PCI-X bus spd 50-66MHz */
@@ -578,8 +358,6 @@
ADVERTISE_100_FULL)
#define E1000_ALL_100_SPEED (ADVERTISE_100_HALF | ADVERTISE_100_FULL)
#define E1000_ALL_10_SPEED (ADVERTISE_10_HALF | ADVERTISE_10_FULL)
-#define E1000_ALL_FULL_DUPLEX ( \
- ADVERTISE_10_FULL | ADVERTISE_100_FULL | ADVERTISE_1000_FULL)
#define E1000_ALL_HALF_DUPLEX (ADVERTISE_10_HALF | ADVERTISE_100_HALF)
#define AUTONEG_ADVERTISE_SPEED_DEFAULT E1000_ALL_SPEED_DUPLEX
@@ -587,44 +365,14 @@
/* LED Control */
#define E1000_PHY_LED0_MODE_MASK 0x00000007
#define E1000_PHY_LED0_IVRT 0x00000008
-#define E1000_PHY_LED0_BLINK 0x00000010
#define E1000_PHY_LED0_MASK 0x0000001F
#define E1000_LEDCTL_LED0_MODE_MASK 0x0000000F
#define E1000_LEDCTL_LED0_MODE_SHIFT 0
-#define E1000_LEDCTL_LED0_BLINK_RATE 0x00000020
#define E1000_LEDCTL_LED0_IVRT 0x00000040
#define E1000_LEDCTL_LED0_BLINK 0x00000080
-#define E1000_LEDCTL_LED1_MODE_MASK 0x00000F00
-#define E1000_LEDCTL_LED1_MODE_SHIFT 8
-#define E1000_LEDCTL_LED1_BLINK_RATE 0x00002000
-#define E1000_LEDCTL_LED1_IVRT 0x00004000
-#define E1000_LEDCTL_LED1_BLINK 0x00008000
-#define E1000_LEDCTL_LED2_MODE_MASK 0x000F0000
-#define E1000_LEDCTL_LED2_MODE_SHIFT 16
-#define E1000_LEDCTL_LED2_BLINK_RATE 0x00200000
-#define E1000_LEDCTL_LED2_IVRT 0x00400000
-#define E1000_LEDCTL_LED2_BLINK 0x00800000
-#define E1000_LEDCTL_LED3_MODE_MASK 0x0F000000
-#define E1000_LEDCTL_LED3_MODE_SHIFT 24
-#define E1000_LEDCTL_LED3_BLINK_RATE 0x20000000
-#define E1000_LEDCTL_LED3_IVRT 0x40000000
-#define E1000_LEDCTL_LED3_BLINK 0x80000000
-#define E1000_LEDCTL_MODE_LINK_10_1000 0x0
-#define E1000_LEDCTL_MODE_LINK_100_1000 0x1
#define E1000_LEDCTL_MODE_LINK_UP 0x2
-#define E1000_LEDCTL_MODE_ACTIVITY 0x3
-#define E1000_LEDCTL_MODE_LINK_ACTIVITY 0x4
-#define E1000_LEDCTL_MODE_LINK_10 0x5
-#define E1000_LEDCTL_MODE_LINK_100 0x6
-#define E1000_LEDCTL_MODE_LINK_1000 0x7
-#define E1000_LEDCTL_MODE_PCIX_MODE 0x8
-#define E1000_LEDCTL_MODE_FULL_DUPLEX 0x9
-#define E1000_LEDCTL_MODE_COLLISION 0xA
-#define E1000_LEDCTL_MODE_BUS_SPEED 0xB
-#define E1000_LEDCTL_MODE_BUS_SIZE 0xC
-#define E1000_LEDCTL_MODE_PAUSED 0xD
#define E1000_LEDCTL_MODE_LED_ON 0xE
#define E1000_LEDCTL_MODE_LED_OFF 0xF
@@ -631,7 +379,6 @@
/* Transmit Descriptor bit definitions */
#define E1000_TXD_DTYP_D 0x00100000 /* Data Descriptor */
#define E1000_TXD_DTYP_C 0x00000000 /* Context Descriptor */
-#define E1000_TXD_POPTS_SHIFT 8 /* POPTS shift */
#define E1000_TXD_POPTS_IXSM 0x01 /* Insert IP checksum */
#define E1000_TXD_POPTS_TXSM 0x02 /* Insert TCP/UDP checksum */
#define E1000_TXD_CMD_EOP 0x01000000 /* End of Packet */
@@ -650,21 +397,14 @@
#define E1000_TXD_CMD_IP 0x02000000 /* IP packet */
#define E1000_TXD_CMD_TSE 0x04000000 /* TCP Seg enable */
#define E1000_TXD_STAT_TC 0x00000004 /* Tx Underrun */
-/* Extended desc bits for Linksec and timesync */
-#define E1000_TXD_CMD_LINKSEC 0x10000000 /* Apply LinkSec on packet */
#define E1000_TXD_EXTCMD_TSTAMP 0x00000010 /* IEEE1588 Timestamp packet */
/* Transmit Control */
-#define E1000_TCTL_RST 0x00000001 /* software reset */
#define E1000_TCTL_EN 0x00000002 /* enable Tx */
-#define E1000_TCTL_BCE 0x00000004 /* busy check enable */
#define E1000_TCTL_PSP 0x00000008 /* pad short packets */
#define E1000_TCTL_CT 0x00000ff0 /* collision threshold */
#define E1000_TCTL_COLD 0x003ff000 /* collision distance */
-#define E1000_TCTL_SWXOFF 0x00400000 /* SW Xoff transmission */
-#define E1000_TCTL_PBE 0x00800000 /* Packet Burst Enable */
#define E1000_TCTL_RTLC 0x01000000 /* Re-transmit on late collision */
-#define E1000_TCTL_NRTU 0x02000000 /* No Re-transmit on underrun */
#define E1000_TCTL_MULR 0x10000000 /* Multiple request support */
/* Transmit Arbitration Count */
@@ -672,29 +412,19 @@
/* SerDes Control */
#define E1000_SCTL_DISABLE_SERDES_LOOPBACK 0x0400
+#define E1000_SCTL_ENABLE_SERDES_LOOPBACK 0x0410
/* Receive Checksum Control */
-#define E1000_RXCSUM_PCSS_MASK 0x000000FF /* Packet Checksum Start */
#define E1000_RXCSUM_IPOFL 0x00000100 /* IPv4 checksum offload */
#define E1000_RXCSUM_TUOFL 0x00000200 /* TCP / UDP checksum offload */
-#define E1000_RXCSUM_IPV6OFL 0x00000400 /* IPv6 checksum offload */
#define E1000_RXCSUM_CRCOFL 0x00000800 /* CRC32 offload enable */
#define E1000_RXCSUM_IPPCSE 0x00001000 /* IP payload checksum enable */
#define E1000_RXCSUM_PCSD 0x00002000 /* packet checksum disabled */
/* Header split receive */
-#define E1000_RFCTL_ISCSI_DIS 0x00000001
-#define E1000_RFCTL_ISCSI_DWC_MASK 0x0000003E
-#define E1000_RFCTL_ISCSI_DWC_SHIFT 1
#define E1000_RFCTL_NFSW_DIS 0x00000040
#define E1000_RFCTL_NFSR_DIS 0x00000080
-#define E1000_RFCTL_NFS_VER_MASK 0x00000300
-#define E1000_RFCTL_NFS_VER_SHIFT 8
-#define E1000_RFCTL_IPV6_DIS 0x00000400
-#define E1000_RFCTL_IPV6_XSUM_DIS 0x00000800
#define E1000_RFCTL_ACK_DIS 0x00001000
-#define E1000_RFCTL_ACKD_DIS 0x00002000
-#define E1000_RFCTL_IPFRSP_DIS 0x00004000
#define E1000_RFCTL_EXTEN 0x00008000
#define E1000_RFCTL_IPV6_EX_DIS 0x00010000
#define E1000_RFCTL_NEW_IPV6_EXT_DIS 0x00020000
@@ -712,8 +442,6 @@
#define DEFAULT_82543_TIPG_IPGT_COPPER 8
#define E1000_TIPG_IPGT_MASK 0x000003FF
-#define E1000_TIPG_IPGR1_MASK 0x000FFC00
-#define E1000_TIPG_IPGR2_MASK 0x3FF00000
#define DEFAULT_82542_TIPG_IPGR1 2
#define DEFAULT_82543_TIPG_IPGR1 8
@@ -741,7 +469,6 @@
#define E1000_EXTCNF_CTRL_EXT_CNF_POINTER_MASK 0x0FFF0000
#define E1000_EXTCNF_CTRL_EXT_CNF_POINTER_SHIFT 16
-#define E1000_PHY_CTRL_SPD_EN 0x00000001
#define E1000_PHY_CTRL_D0A_LPLU 0x00000002
#define E1000_PHY_CTRL_NOND0A_LPLU 0x00000004
#define E1000_PHY_CTRL_NOND0A_GBE_DISABLE 0x00000008
@@ -749,8 +476,10 @@
#define E1000_KABGTXD_BGSQLBIAS 0x00050000
+/* Low Power IDLE Control */
+#define E1000_LPIC_LPIET_SHIFT 24 /* Low Power Idle Entry Time */
+
/* PBA constants */
-#define E1000_PBA_6K 0x0006 /* 6KB */
#define E1000_PBA_8K 0x0008 /* 8KB */
#define E1000_PBA_10K 0x000A /* 10KB */
#define E1000_PBA_12K 0x000C /* 12KB */
@@ -770,11 +499,16 @@
#define E1000_PBA_48K 0x0030 /* 48KB */
#define E1000_PBA_64K 0x0040 /* 64KB */
-#define E1000_PBA_RXA_MASK 0xFFFF;
+#define E1000_PBA_RXA_MASK 0xFFFF
#define E1000_PBS_16K E1000_PBA_16K
-#define E1000_PBS_24K E1000_PBA_24K
+/* Uncorrectable/correctable ECC Error counts and enable bits */
+#define E1000_PBECCSTS_CORR_ERR_CNT_MASK 0x000000FF
+#define E1000_PBECCSTS_UNCORR_ERR_CNT_MASK 0x0000FF00
+#define E1000_PBECCSTS_UNCORR_ERR_CNT_SHIFT 8
+#define E1000_PBECCSTS_ECC_ENABLE 0x00010000
+
#define IFS_MAX 80
#define IFS_MIN 40
#define IFS_RATIO 4
@@ -784,7 +518,6 @@
/* SW Semaphore Register */
#define E1000_SWSM_SMBI 0x00000001 /* Driver Semaphore bit */
#define E1000_SWSM_SWESMBI 0x00000002 /* FW Semaphore bit */
-#define E1000_SWSM_WMNG 0x00000004 /* Wake MNG Clock */
#define E1000_SWSM_DRV_LOAD 0x00000008 /* Driver Loaded Bit */
#define E1000_SWSM2_LOCK 0x00000002 /* Secondary driver semaphore bit */
@@ -798,7 +531,6 @@
#define E1000_ICR_RXO 0x00000040 /* Rx overrun */
#define E1000_ICR_RXT0 0x00000080 /* Rx timer intr (ring 0) */
#define E1000_ICR_VMMB 0x00000100 /* VM MB event */
-#define E1000_ICR_MDAC 0x00000200 /* MDIO access complete */
#define E1000_ICR_RXCFG 0x00000400 /* Rx /c/ ordered set */
#define E1000_ICR_GPI_EN0 0x00000800 /* GP Int 0 */
#define E1000_ICR_GPI_EN1 0x00001000 /* GP Int 1 */
@@ -805,26 +537,13 @@
#define E1000_ICR_GPI_EN2 0x00002000 /* GP Int 2 */
#define E1000_ICR_GPI_EN3 0x00004000 /* GP Int 3 */
#define E1000_ICR_TXD_LOW 0x00008000
-#define E1000_ICR_SRPD 0x00010000
-#define E1000_ICR_ACK 0x00020000 /* Receive Ack frame */
#define E1000_ICR_MNG 0x00040000 /* Manageability event */
-#define E1000_ICR_DOCK 0x00080000 /* Dock/Undock */
+#define E1000_ICR_ECCER 0x00400000 /* Uncorrectable ECC Error */
+#define E1000_ICR_TS 0x00080000 /* Time Sync Interrupt */
#define E1000_ICR_DRSTA 0x40000000 /* Device Reset Asserted */
/* If this bit asserted, the driver should claim the interrupt */
#define E1000_ICR_INT_ASSERTED 0x80000000
-#define E1000_ICR_RXD_FIFO_PAR0 0x00100000 /* Q0 Rx desc FIFO parity error */
-#define E1000_ICR_TXD_FIFO_PAR0 0x00200000 /* Q0 Tx desc FIFO parity error */
-#define E1000_ICR_HOST_ARB_PAR 0x00400000 /* host arb read buffer parity err */
-#define E1000_ICR_PB_PAR 0x00800000 /* packet buffer parity error */
-#define E1000_ICR_RXD_FIFO_PAR1 0x01000000 /* Q1 Rx desc FIFO parity error */
-#define E1000_ICR_TXD_FIFO_PAR1 0x02000000 /* Q1 Tx desc FIFO parity error */
-#define E1000_ICR_ALL_PARITY 0x03F00000 /* all parity error bits */
-/* FW changed the status of DISSW bit in the FWSM */
-#define E1000_ICR_DSW 0x00000020
-/* LAN connected device generates an interrupt */
-#define E1000_ICR_PHYINT 0x00001000
#define E1000_ICR_DOUTSYNC 0x10000000 /* NIC DMA out of sync */
-#define E1000_ICR_EPRST 0x00100000 /* ME hardware reset occurs */
#define E1000_ICR_RXQ0 0x00100000 /* Rx Queue 0 Interrupt */
#define E1000_ICR_RXQ1 0x00200000 /* Rx Queue 1 Interrupt */
#define E1000_ICR_TXQ0 0x00400000 /* Tx Queue 0 Interrupt */
@@ -862,19 +581,8 @@
#define E1000_TCPTIMER_COUNT_FINISH 0x00000400 /* Count finish */
#define E1000_TCPTIMER_LOOP 0x00000800 /* Loop */
-/*
- * This defines the bits that are set in the Interrupt Mask
+/* This defines the bits that are set in the Interrupt Mask
* Set/Read Register. Each bit is documented below:
- * o RXDMT0 = Receive Descriptor Minimum Threshold hit (ring 0)
- * o RXSEQ = Receive Sequence Error
- */
-#define POLL_IMS_ENABLE_MASK ( \
- E1000_IMS_RXDMT0 | \
- E1000_IMS_RXSEQ)
-
-/*
- * This defines the bits that are set in the Interrupt Mask
- * Set/Read Register. Each bit is documented below:
* o RXT0 = Receiver Timer Interrupt (ring 0)
* o TXDW = Transmit Descriptor Written Back
* o RXDMT0 = Receive Descriptor Minimum Threshold hit (ring 0)
@@ -897,34 +605,11 @@
#define E1000_IMS_RXDMT0 E1000_ICR_RXDMT0 /* Rx desc min. threshold */
#define E1000_IMS_RXO E1000_ICR_RXO /* Rx overrun */
#define E1000_IMS_RXT0 E1000_ICR_RXT0 /* Rx timer intr */
-#define E1000_IMS_MDAC E1000_ICR_MDAC /* MDIO access complete */
-#define E1000_IMS_RXCFG E1000_ICR_RXCFG /* Rx /c/ ordered set */
-#define E1000_IMS_GPI_EN0 E1000_ICR_GPI_EN0 /* GP Int 0 */
-#define E1000_IMS_GPI_EN1 E1000_ICR_GPI_EN1 /* GP Int 1 */
-#define E1000_IMS_GPI_EN2 E1000_ICR_GPI_EN2 /* GP Int 2 */
-#define E1000_IMS_GPI_EN3 E1000_ICR_GPI_EN3 /* GP Int 3 */
#define E1000_IMS_TXD_LOW E1000_ICR_TXD_LOW
-#define E1000_IMS_SRPD E1000_ICR_SRPD
-#define E1000_IMS_ACK E1000_ICR_ACK /* Receive Ack frame */
-#define E1000_IMS_MNG E1000_ICR_MNG /* Manageability event */
-#define E1000_IMS_DOCK E1000_ICR_DOCK /* Dock/Undock */
+#define E1000_IMS_ECCER E1000_ICR_ECCER /* Uncorrectable ECC Error */
+#define E1000_IMS_TS E1000_ICR_TS /* Time Sync Interrupt */
#define E1000_IMS_DRSTA E1000_ICR_DRSTA /* Device Reset Asserted */
-/* Q0 Rx desc FIFO parity error */
-#define E1000_IMS_RXD_FIFO_PAR0 E1000_ICR_RXD_FIFO_PAR0
-/* Q0 Tx desc FIFO parity error */
-#define E1000_IMS_TXD_FIFO_PAR0 E1000_ICR_TXD_FIFO_PAR0
-/* host arb read buffer parity error */
-#define E1000_IMS_HOST_ARB_PAR E1000_ICR_HOST_ARB_PAR
-/* packet buffer parity error */
-#define E1000_IMS_PB_PAR E1000_ICR_PB_PAR
-/* Q1 Rx desc FIFO parity error */
-#define E1000_IMS_RXD_FIFO_PAR1 E1000_ICR_RXD_FIFO_PAR1
-/* Q1 Tx desc FIFO parity error */
-#define E1000_IMS_TXD_FIFO_PAR1 E1000_ICR_TXD_FIFO_PAR1
-#define E1000_IMS_DSW E1000_ICR_DSW
-#define E1000_IMS_PHYINT E1000_ICR_PHYINT
#define E1000_IMS_DOUTSYNC E1000_ICR_DOUTSYNC /* NIC DMA out of sync */
-#define E1000_IMS_EPRST E1000_ICR_EPRST
#define E1000_IMS_RXQ0 E1000_ICR_RXQ0 /* Rx Queue 0 Interrupt */
#define E1000_IMS_RXQ1 E1000_ICR_RXQ1 /* Rx Queue 1 Interrupt */
#define E1000_IMS_TXQ0 E1000_ICR_TXQ0 /* Tx Queue 0 Interrupt */
@@ -947,41 +632,9 @@
#define E1000_EIMS_OTHER E1000_EICR_OTHER /* Interrupt Cause Active */
/* Interrupt Cause Set */
-#define E1000_ICS_TXDW E1000_ICR_TXDW /* Tx desc written back */
-#define E1000_ICS_TXQE E1000_ICR_TXQE /* Transmit Queue empty */
#define E1000_ICS_LSC E1000_ICR_LSC /* Link Status Change */
#define E1000_ICS_RXSEQ E1000_ICR_RXSEQ /* Rx sequence error */
#define E1000_ICS_RXDMT0 E1000_ICR_RXDMT0 /* Rx desc min. threshold */
-#define E1000_ICS_RXO E1000_ICR_RXO /* Rx overrun */
-#define E1000_ICS_RXT0 E1000_ICR_RXT0 /* Rx timer intr */
-#define E1000_ICS_MDAC E1000_ICR_MDAC /* MDIO access complete */
-#define E1000_ICS_RXCFG E1000_ICR_RXCFG /* Rx /c/ ordered set */
-#define E1000_ICS_GPI_EN0 E1000_ICR_GPI_EN0 /* GP Int 0 */
-#define E1000_ICS_GPI_EN1 E1000_ICR_GPI_EN1 /* GP Int 1 */
-#define E1000_ICS_GPI_EN2 E1000_ICR_GPI_EN2 /* GP Int 2 */
-#define E1000_ICS_GPI_EN3 E1000_ICR_GPI_EN3 /* GP Int 3 */
-#define E1000_ICS_TXD_LOW E1000_ICR_TXD_LOW
-#define E1000_ICS_SRPD E1000_ICR_SRPD
-#define E1000_ICS_ACK E1000_ICR_ACK /* Receive Ack frame */
-#define E1000_ICS_MNG E1000_ICR_MNG /* Manageability event */
-#define E1000_ICS_DOCK E1000_ICR_DOCK /* Dock/Undock */
-#define E1000_ICS_DRSTA E1000_ICR_DRSTA /* Device Reset Aserted */
-/* Q0 Rx desc FIFO parity error */
-#define E1000_ICS_RXD_FIFO_PAR0 E1000_ICR_RXD_FIFO_PAR0
-/* Q0 Tx desc FIFO parity error */
-#define E1000_ICS_TXD_FIFO_PAR0 E1000_ICR_TXD_FIFO_PAR0
-/* host arb read buffer parity error */
-#define E1000_ICS_HOST_ARB_PAR E1000_ICR_HOST_ARB_PAR
-/* packet buffer parity error */
-#define E1000_ICS_PB_PAR E1000_ICR_PB_PAR
-/* Q1 Rx desc FIFO parity error */
-#define E1000_ICS_RXD_FIFO_PAR1 E1000_ICR_RXD_FIFO_PAR1
-/* Q1 Tx desc FIFO parity error */
-#define E1000_ICS_TXD_FIFO_PAR1 E1000_ICR_TXD_FIFO_PAR1
-#define E1000_ICS_DSW E1000_ICR_DSW
-#define E1000_ICS_DOUTSYNC E1000_ICR_DOUTSYNC /* NIC DMA out of sync */
-#define E1000_ICS_PHYINT E1000_ICR_PHYINT
-#define E1000_ICS_EPRST E1000_ICR_EPRST
/* Extended Interrupt Cause Set */
#define E1000_EICS_RX_QUEUE0 E1000_EICR_RX_QUEUE0 /* Rx Queue 0 Interrupt */
@@ -1004,7 +657,6 @@
#define E1000_TXDCTL_HTHRESH 0x00003F00 /* TXDCTL Host Threshold */
#define E1000_TXDCTL_WTHRESH 0x003F0000 /* TXDCTL Writeback Threshold */
#define E1000_TXDCTL_GRAN 0x01000000 /* TXDCTL Granularity */
-#define E1000_TXDCTL_LWTHRESH 0xFE000000 /* TXDCTL Low Threshold */
#define E1000_TXDCTL_FULL_TX_DESC_WB 0x01010000 /* GRAN=1, WTHRESH=1 */
#define E1000_TXDCTL_MAX_TX_DESC_PREFETCH 0x0100001F /* GRAN=1, PTHRESH=31 */
/* Enable the counting of descriptors still to be processed. */
@@ -1019,8 +671,7 @@
#define VLAN_TAG_SIZE 4 /* 802.3ac tag (not DMA'd) */
#define E1000_VLAN_FILTER_TBL_SIZE 128 /* VLAN Filter Table (4096 bits) */
-/* Receive Address */
-/*
+/* Receive Address
* Number of high/low register pairs in the RAR. The RAR (Receive Address
* Registers) holds the directed and multicast addresses that we monitor.
* Technically, we have 16 spots. However, we reserve one of these spots
@@ -1032,8 +683,6 @@
#define E1000_RAL_MAC_ADDR_LEN 4
#define E1000_RAH_MAC_ADDR_LEN 2
#define E1000_RAH_QUEUE_MASK_82575 0x000C0000
-#define E1000_RAH_POOL_MASK 0x03FC0000
-#define E1000_RAH_POOL_SHIFT 18
#define E1000_RAH_POOL_1 0x00040000
/* Error Codes */
@@ -1073,30 +722,21 @@
/* Flow Control */
#define E1000_FCRTH_RTH 0x0000FFF8 /* Mask Bits[15:3] for RTH */
-#define E1000_FCRTH_XFCE 0x80000000 /* External Flow Control Enable */
#define E1000_FCRTL_RTL 0x0000FFF8 /* Mask Bits[15:3] for RTL */
#define E1000_FCRTL_XONE 0x80000000 /* Enable XON frame transmission */
/* Transmit Configuration Word */
#define E1000_TXCW_FD 0x00000020 /* TXCW full duplex */
-#define E1000_TXCW_HD 0x00000040 /* TXCW half duplex */
#define E1000_TXCW_PAUSE 0x00000080 /* TXCW sym pause request */
#define E1000_TXCW_ASM_DIR 0x00000100 /* TXCW astm pause direction */
#define E1000_TXCW_PAUSE_MASK 0x00000180 /* TXCW pause request mask */
-#define E1000_TXCW_RF 0x00003000 /* TXCW remote fault */
-#define E1000_TXCW_NP 0x00008000 /* TXCW next page */
-#define E1000_TXCW_CW 0x0000ffff /* TxConfigWord mask */
-#define E1000_TXCW_TXC 0x40000000 /* Transmit Config control */
#define E1000_TXCW_ANE 0x80000000 /* Auto-neg enable */
/* Receive Configuration Word */
#define E1000_RXCW_CW 0x0000ffff /* RxConfigWord mask */
-#define E1000_RXCW_NC 0x04000000 /* Receive config no carrier */
#define E1000_RXCW_IV 0x08000000 /* Receive config invalid */
-#define E1000_RXCW_CC 0x10000000 /* Receive config change */
#define E1000_RXCW_C 0x20000000 /* Receive config */
#define E1000_RXCW_SYNCH 0x40000000 /* Receive config synch */
-#define E1000_RXCW_ANC 0x80000000 /* Auto-neg complete */
#define E1000_TSYNCTXCTL_VALID 0x00000001 /* Tx timestamp valid */
#define E1000_TSYNCTXCTL_ENABLED 0x00000010 /* enable Tx timestamping */
@@ -1109,7 +749,14 @@
#define E1000_TSYNCRXCTL_TYPE_ALL 0x08
#define E1000_TSYNCRXCTL_TYPE_EVENT_V2 0x0A
#define E1000_TSYNCRXCTL_ENABLED 0x00000010 /* enable Rx timestamping */
+#define E1000_TSYNCRXCTL_SYSCFI 0x00000020 /* Sys clock frequency */
+#define E1000_RXMTRL_PTP_V1_SYNC_MESSAGE 0x00000000
+#define E1000_RXMTRL_PTP_V1_DELAY_REQ_MESSAGE 0x00010000
+
+#define E1000_RXMTRL_PTP_V2_SYNC_MESSAGE 0x00000000
+#define E1000_RXMTRL_PTP_V2_DELAY_REQ_MESSAGE 0x01000000
+
#define E1000_TSYNCRXCFG_PTP_V1_CTRLT_MASK 0x000000FF
#define E1000_TSYNCRXCFG_PTP_V1_SYNC_MESSAGE 0x00
#define E1000_TSYNCRXCFG_PTP_V1_DELAY_REQ_MESSAGE 0x01
@@ -1130,6 +777,11 @@
#define E1000_TSYNCRXCFG_PTP_V2_MANAGEMENT_MESSAGE 0x0D00
#define E1000_TIMINCA_16NS_SHIFT 24
+#define E1000_TIMINCA_INCPERIOD_SHIFT 24
+#define E1000_TIMINCA_INCVALUE_MASK 0x00FFFFFF
+
+#define E1000_TSICR_TXTS 0x00000002
+#define E1000_TSIM_TXTS 0x00000002
/* TUPLE Filtering Configuration */
#define E1000_TTQF_DISABLE_MASK 0xF0008000 /* TTQF Disable Mask */
#define E1000_TTQF_QUEUE_ENABLE 0x100 /* TTQF Queue Enable Bit */
@@ -1170,7 +822,7 @@
#define E1000_EEER_EEE_NEG 0x20000000 /* EEE capability nego */
#define E1000_EEER_RX_LPI_STATUS 0x40000000 /* Rx in LPI state */
#define E1000_EEER_TX_LPI_STATUS 0x80000000 /* Tx in LPI state */
-
+#define E1000_EEE_SU_LPI_CLK_STP 0x00800000 /* EEE LPI Clock Stop */
/* PCI Express Control */
#define E1000_GCR_RXD_NO_SNOOP 0x00000001
#define E1000_GCR_RXDSCW_NO_SNOOP 0x00000002
@@ -1314,10 +966,6 @@
#define E1000_EECD_CS 0x00000002 /* NVM Chip Select */
#define E1000_EECD_DI 0x00000004 /* NVM Data In */
#define E1000_EECD_DO 0x00000008 /* NVM Data Out */
-#define E1000_EECD_FWE_MASK 0x00000030
-#define E1000_EECD_FWE_DIS 0x00000010 /* Disable FLASH writes */
-#define E1000_EECD_FWE_EN 0x00000020 /* Enable FLASH writes */
-#define E1000_EECD_FWE_SHIFT 4
#define E1000_EECD_REQ 0x00000040 /* NVM Access Request */
#define E1000_EECD_GNT 0x00000080 /* NVM Access Grant */
#define E1000_EECD_PRES 0x00000100 /* NVM Present */
@@ -1335,28 +983,28 @@
#define E1000_EECD_AUTO_RD 0x00000200 /* NVM Auto Read done */
#define E1000_EECD_SIZE_EX_MASK 0x00007800 /* NVM Size */
#define E1000_EECD_SIZE_EX_SHIFT 11
-#define E1000_EECD_NVADDS 0x00018000 /* NVM Address Size */
-#define E1000_EECD_SELSHAD 0x00020000 /* Select Shadow RAM */
-#define E1000_EECD_INITSRAM 0x00040000 /* Initialize Shadow RAM */
#define E1000_EECD_FLUPD 0x00080000 /* Update FLASH */
#define E1000_EECD_AUPDEN 0x00100000 /* Ena Auto FLASH update */
-#define E1000_EECD_SHADV 0x00200000 /* Shadow RAM Data Valid */
#define E1000_EECD_SEC1VAL 0x00400000 /* Sector One Valid */
-#define E1000_EECD_SECVAL_SHIFT 22
#define E1000_EECD_SEC1VAL_VALID_MASK (E1000_EECD_AUTO_RD | E1000_EECD_PRES)
#define E1000_EECD_FLUPD_I210 0x00800000 /* Update FLASH */
#define E1000_EECD_FLUDONE_I210 0x04000000 /* Update FLASH done */
#define E1000_EECD_FLASH_DETECTED_I210 0x00080000 /* FLASH detected */
+#define E1000_EECD_SEC1VAL_I210 0x02000000 /* Sector One Valid */
#define E1000_FLUDONE_ATTEMPTS 20000
#define E1000_EERD_EEWR_MAX_COUNT 512 /* buffered EEPROM words rw */
-#define E1000_I210_FIFO_SEL_RX 0x00
+#define E1000_I210_FIFO_SEL_RX 0x00
#define E1000_I210_FIFO_SEL_TX_QAV(_i) (0x02 + (_i))
#define E1000_I210_FIFO_SEL_TX_LEGACY E1000_I210_FIFO_SEL_TX_QAV(0)
#define E1000_I210_FIFO_SEL_BMC2OS_TX 0x06
#define E1000_I210_FIFO_SEL_BMC2OS_RX 0x01
-#define E1000_NVM_SWDPIN0 0x0001 /* SWDPIN 0 NVM Value */
-#define E1000_NVM_LED_LOGIC 0x0020 /* Led Logic Word */
+#define E1000_I210_FLASH_SECTOR_SIZE 0x1000 /* 4KB FLASH sector unit size */
+/* Secure FLASH mode requires removing MSb */
+#define E1000_I210_FW_PTR_MASK 0x7FFF
+/* Firmware code revision field word offset*/
+#define E1000_I210_FW_VER_OFFSET 328
+
#define E1000_NVM_RW_REG_DATA 16 /* Offset to data in NVM read/write regs */
#define E1000_NVM_RW_REG_DONE 2 /* Offset to READ/WRITE done bit */
#define E1000_NVM_RW_REG_START 1 /* Start operation */
@@ -1368,13 +1016,11 @@
/* NVM Word Offsets */
#define NVM_COMPAT 0x0003
#define NVM_ID_LED_SETTINGS 0x0004
-#define NVM_VERSION 0x0005
#define NVM_SERDES_AMPLITUDE 0x0006 /* SERDES output amplitude */
#define NVM_PHY_CLASS_WORD 0x0007
-#define NVM_ETRACK_WORD 0x0042
-#define NVM_COMB_VER_OFF 0x0083
-#define NVM_COMB_VER_PTR 0x003d
-
+#define E1000_I210_NVM_FW_MODULE_PTR 0x0010
+#define E1000_I350_NVM_FW_MODULE_PTR 0x0051
+#define NVM_FUTURE_INIT_WORD1 0x0019
#define NVM_MAC_ADDR 0x0000
#define NVM_SUB_DEV_ID 0x000B
#define NVM_SUB_VEN_ID 0x000C
@@ -1385,15 +1031,15 @@
#define NVM_LED_1_CFG 0x001C
#define NVM_LED_0_2_CFG 0x001F
-#define NVM_INIT_CONTROL1_REG 0x000A
+#define NVM_COMPAT_VALID_CSUM 0x0001
+#define NVM_FUTURE_INIT_WORD1_VALID_CSUM 0x0040
+
#define NVM_INIT_CONTROL2_REG 0x000F
-#define NVM_SWDEF_PINS_CTRL_PORT_1 0x0010
#define NVM_INIT_CONTROL3_PORT_B 0x0014
#define NVM_INIT_3GIO_3 0x001A
#define NVM_SWDEF_PINS_CTRL_PORT_0 0x0020
#define NVM_INIT_CONTROL3_PORT_A 0x0024
#define NVM_CFG 0x0012
-#define NVM_FLASH_VERSION 0x0032
#define NVM_ALT_MAC_ADDR_PTR 0x0037
#define NVM_CHECKSUM_REG 0x003F
#define NVM_COMPATIBILITY_REG_3 0x0003
@@ -1419,9 +1065,7 @@
#define NVM_WORD0F_PAUSE_MASK 0x3000
#define NVM_WORD0F_PAUSE 0x1000
#define NVM_WORD0F_ASM_DIR 0x2000
-#define NVM_WORD0F_ANE 0x0800
#define NVM_WORD0F_SWPDIO_EXT_MASK 0x00F0
-#define NVM_WORD0F_LPLU 0x0001
/* Mask bits for fields in Word 0x1a of the NVM */
#define NVM_WORD1A_ASPM_MASK 0x000C
@@ -1435,7 +1079,7 @@
/* For checksumming, the sum of all words in the NVM should equal 0xBABA. */
#define NVM_SUM 0xBABA
-#define NVM_MAC_ADDR_OFFSET 0
+/* PBA (printed board assembly) number words */
#define NVM_PBA_OFFSET_0 8
#define NVM_PBA_OFFSET_1 9
#define NVM_PBA_PTR_GUARD 0xFAFA
@@ -1460,16 +1104,10 @@
#define NVM_WRITE_OPCODE_SPI 0x02 /* NVM write opcode */
#define NVM_A8_OPCODE_SPI 0x08 /* opcode bit-3 = address bit-8 */
#define NVM_WREN_OPCODE_SPI 0x06 /* NVM set Write Enable latch */
-#define NVM_WRDI_OPCODE_SPI 0x04 /* NVM reset Write Enable latch */
#define NVM_RDSR_OPCODE_SPI 0x05 /* NVM read Status register */
-#define NVM_WRSR_OPCODE_SPI 0x01 /* NVM write Status register */
/* SPI NVM Status Register */
#define NVM_STATUS_RDY_SPI 0x01
-#define NVM_STATUS_WEN_SPI 0x02
-#define NVM_STATUS_BP0_SPI 0x04
-#define NVM_STATUS_BP1_SPI 0x08
-#define NVM_STATUS_WPEN_SPI 0x80
/* Word definitions for ID LED Settings */
#define ID_LED_RESERVED_0000 0x0000
@@ -1523,8 +1161,7 @@
#define MAX_PHY_REG_ADDRESS 0x1F /* 5 bit address bus (0-0x1F) */
#define MAX_PHY_MULTI_PAGE_REG 0xF
-/* Bit definitions for valid PHY IDs. */
-/*
+/* Bit definitions for valid PHY IDs.
* I = Integrated
* E = External
*/
@@ -1532,7 +1169,6 @@
#define M88E1000_I_PHY_ID 0x01410C30
#define M88E1011_I_PHY_ID 0x01410C20
#define IGP01E1000_I_PHY_ID 0x02A80380
-#define M88E1011_I_REV_4 0x04
#define M88E1111_I_PHY_ID 0x01410CC0
#define M88E1112_E_PHY_ID 0x01410C90
#define I347AT4_E_PHY_ID 0x01410DC0
@@ -1547,6 +1183,7 @@
#define I82577_E_PHY_ID 0x01540050
#define I82578_E_PHY_ID 0x004DD040
#define I82579_E_PHY_ID 0x01540090
+#define I217_E_PHY_ID 0x015400A0
#define I82580_I_PHY_ID 0x015403A0
#define I350_I_PHY_ID 0x015403B0
#define I210_I_PHY_ID 0x01410C00
@@ -1556,8 +1193,6 @@
/* M88E1000 Specific Registers */
#define M88E1000_PHY_SPEC_CTRL 0x10 /* PHY Specific Control Reg */
#define M88E1000_PHY_SPEC_STATUS 0x11 /* PHY Specific Status Reg */
-#define M88E1000_INT_ENABLE 0x12 /* Interrupt Enable Reg */
-#define M88E1000_INT_STATUS 0x13 /* Interrupt Status Reg */
#define M88E1000_EXT_PHY_SPEC_CTRL 0x14 /* Extended PHY Specific Cntrl */
#define M88E1000_RX_ERR_CNTR 0x15 /* Receive Error Counter */
@@ -1568,11 +1203,7 @@
#define M88E1000_PHY_VCO_REG_BIT11 0x800 /* improved BER performance */
/* M88E1000 PHY Specific Control Register */
-#define M88E1000_PSCR_JABBER_DISABLE 0x0001 /* 1=Jabber Function disabled */
#define M88E1000_PSCR_POLARITY_REVERSAL 0x0002 /* 1=Polarity Reverse enabled */
-#define M88E1000_PSCR_SQE_TEST 0x0004 /* 1=SQE Test enabled */
-/* 1=CLK125 low, 0=CLK125 toggling */
-#define M88E1000_PSCR_CLK125_DISABLE 0x0010
/* MDI Crossover Mode bits 6:5 Manual MDI configuration */
#define M88E1000_PSCR_MDI_MANUAL_MODE 0x0000
#define M88E1000_PSCR_MDIX_MANUAL_MODE 0x0020 /* Manual MDIX configuration */
@@ -1580,24 +1211,13 @@
#define M88E1000_PSCR_AUTO_X_1000T 0x0040
/* Auto crossover enabled all speeds */
#define M88E1000_PSCR_AUTO_X_MODE 0x0060
-/*
- * 1=Enable Extended 10BASE-T distance (Lower 10BASE-T Rx Threshold
- * 0=Normal 10BASE-T Rx Threshold
- */
-#define M88E1000_PSCR_EN_10BT_EXT_DIST 0x0080
-/* 1=5-bit interface in 100BASE-TX, 0=MII interface in 100BASE-TX */
-#define M88E1000_PSCR_MII_5BIT_ENABLE 0x0100
-#define M88E1000_PSCR_SCRAMBLER_DISABLE 0x0200 /* 1=Scrambler disable */
-#define M88E1000_PSCR_FORCE_LINK_GOOD 0x0400 /* 1=Force link good */
#define M88E1000_PSCR_ASSERT_CRS_ON_TX 0x0800 /* 1=Assert CRS on Tx */
/* M88E1000 PHY Specific Status Register */
-#define M88E1000_PSSR_JABBER 0x0001 /* 1=Jabber */
#define M88E1000_PSSR_REV_POLARITY 0x0002 /* 1=Polarity reversed */
#define M88E1000_PSSR_DOWNSHIFT 0x0020 /* 1=Downshifted */
#define M88E1000_PSSR_MDIX 0x0040 /* 1=MDIX; 0=MDI */
-/*
- * 0 = <50M
+/* 0 = <50M
* 1 = 50-80M
* 2 = 80-110M
* 3 = 110-140M
@@ -1606,56 +1226,26 @@
#define M88E1000_PSSR_CABLE_LENGTH 0x0380
#define M88E1000_PSSR_LINK 0x0400 /* 1=Link up, 0=Link down */
#define M88E1000_PSSR_SPD_DPLX_RESOLVED 0x0800 /* 1=Speed & Duplex resolved */
-#define M88E1000_PSSR_PAGE_RCVD 0x1000 /* 1=Page received */
#define M88E1000_PSSR_DPLX 0x2000 /* 1=Duplex 0=Half Duplex */
#define M88E1000_PSSR_SPEED 0xC000 /* Speed, bits 14:15 */
-#define M88E1000_PSSR_10MBS 0x0000 /* 00=10Mbs */
#define M88E1000_PSSR_100MBS 0x4000 /* 01=100Mbs */
#define M88E1000_PSSR_1000MBS 0x8000 /* 10=1000Mbs */
#define M88E1000_PSSR_CABLE_LENGTH_SHIFT 7
-/* M88E1000 Extended PHY Specific Control Register */
-#define M88E1000_EPSCR_FIBER_LOOPBACK 0x4000 /* 1=Fiber loopback */
-/*
- * 1 = Lost lock detect enabled.
- * Will assert lost lock and bring
- * link down if idle not seen
- * within 1ms in 1000BASE-T
- */
-#define M88E1000_EPSCR_DOWN_NO_IDLE 0x8000
-/*
- * Number of times we will attempt to autonegotiate before downshifting if we
+/* Number of times we will attempt to autonegotiate before downshifting if we
* are the master
*/
#define M88E1000_EPSCR_MASTER_DOWNSHIFT_MASK 0x0C00
#define M88E1000_EPSCR_MASTER_DOWNSHIFT_1X 0x0000
-#define M88E1000_EPSCR_MASTER_DOWNSHIFT_2X 0x0400
-#define M88E1000_EPSCR_MASTER_DOWNSHIFT_3X 0x0800
-#define M88E1000_EPSCR_MASTER_DOWNSHIFT_4X 0x0C00
-/*
- * Number of times we will attempt to autonegotiate before downshifting if we
+/* Number of times we will attempt to autonegotiate before downshifting if we
* are the slave
*/
#define M88E1000_EPSCR_SLAVE_DOWNSHIFT_MASK 0x0300
-#define M88E1000_EPSCR_SLAVE_DOWNSHIFT_DIS 0x0000
#define M88E1000_EPSCR_SLAVE_DOWNSHIFT_1X 0x0100
-#define M88E1000_EPSCR_SLAVE_DOWNSHIFT_2X 0x0200
-#define M88E1000_EPSCR_SLAVE_DOWNSHIFT_3X 0x0300
-#define M88E1000_EPSCR_TX_CLK_2_5 0x0060 /* 2.5 MHz TX_CLK */
#define M88E1000_EPSCR_TX_CLK_25 0x0070 /* 25 MHz TX_CLK */
-#define M88E1000_EPSCR_TX_CLK_0 0x0000 /* NO TX_CLK */
-/* M88E1111 Specific Registers */
-#define M88E1111_PHY_PAGE_SELECT1 0x16 /* for registers 0-28 */
-#define M88E1111_PHY_PAGE_SELECT2 0x1D /* for registers 30-31 */
-
-/* M88E1111 page select register mask */
-#define M88E1111_PHY_PAGE_SELECT_MASK1 0xFF
-#define M88E1111_PHY_PAGE_SELECT_MASK2 0x3F
-
/* Intel I347AT4 Registers */
-
#define I347AT4_PCDL 0x10 /* PHY Cable Diagnostics Length */
#define I347AT4_PCDC 0x15 /* PHY Cable Diagnostics Control */
#define I347AT4_PAGE_SELECT 0x16
@@ -1662,8 +1252,7 @@
/* I347AT4 Extended PHY Specific Control Register */
-/*
- * Number of times we will attempt to autonegotiate before downshifting if we
+/* Number of times we will attempt to autonegotiate before downshifting if we
* are the master
*/
#define I347AT4_PSCR_DOWNSHIFT_ENABLE 0x0800
@@ -1685,14 +1274,7 @@
/* M88EC018 Rev 2 specific DownShift settings */
#define M88EC018_EPSCR_DOWNSHIFT_COUNTER_MASK 0x0E00
-#define M88EC018_EPSCR_DOWNSHIFT_COUNTER_1X 0x0000
-#define M88EC018_EPSCR_DOWNSHIFT_COUNTER_2X 0x0200
-#define M88EC018_EPSCR_DOWNSHIFT_COUNTER_3X 0x0400
-#define M88EC018_EPSCR_DOWNSHIFT_COUNTER_4X 0x0600
#define M88EC018_EPSCR_DOWNSHIFT_COUNTER_5X 0x0800
-#define M88EC018_EPSCR_DOWNSHIFT_COUNTER_6X 0x0A00
-#define M88EC018_EPSCR_DOWNSHIFT_COUNTER_7X 0x0C00
-#define M88EC018_EPSCR_DOWNSHIFT_COUNTER_8X 0x0E00
#define I82578_EPSCR_DOWNSHIFT_ENABLE 0x0020
#define I82578_EPSCR_DOWNSHIFT_COUNTER_MASK 0x001C
@@ -1700,8 +1282,7 @@
/* BME1000 PHY Specific Control Register */
#define BME1000_PSCR_ENABLE_DOWNSHIFT 0x0800 /* 1 = enable downshift */
-/*
- * Bits...
+/* Bits...
* 15-5: page
* 4-0: register offset
*/
@@ -1712,19 +1293,12 @@
/* GG82563 Specific Registers */
#define GG82563_PHY_SPEC_CTRL GG82563_REG(0, 16) /* PHY Spec Cntrl */
-#define GG82563_PHY_SPEC_STATUS GG82563_REG(0, 17) /* PHY Spec Status */
-#define GG82563_PHY_INT_ENABLE GG82563_REG(0, 18) /* Interrupt Ena */
-#define GG82563_PHY_SPEC_STATUS_2 GG82563_REG(0, 19) /* PHY Spec Stat2 */
-#define GG82563_PHY_RX_ERR_CNTR GG82563_REG(0, 21) /* Rx Err Counter */
#define GG82563_PHY_PAGE_SELECT GG82563_REG(0, 22) /* Page Select */
#define GG82563_PHY_SPEC_CTRL_2 GG82563_REG(0, 26) /* PHY Spec Cntrl2 */
#define GG82563_PHY_PAGE_SELECT_ALT GG82563_REG(0, 29) /* Alt Page Select */
-/* Test Clock Control (use reg. 29 to select) */
-#define GG82563_PHY_TEST_CLK_CTRL GG82563_REG(0, 30)
/* MAC Specific Control Register */
#define GG82563_PHY_MAC_SPEC_CTRL GG82563_REG(2, 21)
-#define GG82563_PHY_MAC_SPEC_CTRL_2 GG82563_REG(2, 26) /* MAC Spec Ctrl 2 */
#define GG82563_PHY_DSP_DISTANCE GG82563_REG(5, 26) /* DSP Distance */
@@ -1731,30 +1305,12 @@
/* Page 193 - Port Control Registers */
/* Kumeran Mode Control */
#define GG82563_PHY_KMRN_MODE_CTRL GG82563_REG(193, 16)
-#define GG82563_PHY_PORT_RESET GG82563_REG(193, 17) /* Port Reset */
-#define GG82563_PHY_REVISION_ID GG82563_REG(193, 18) /* Revision ID */
-#define GG82563_PHY_DEVICE_ID GG82563_REG(193, 19) /* Device ID */
#define GG82563_PHY_PWR_MGMT_CTRL GG82563_REG(193, 20) /* Pwr Mgt Ctrl */
-/* Rate Adaptation Control */
-#define GG82563_PHY_RATE_ADAPT_CTRL GG82563_REG(193, 25)
/* Page 194 - KMRN Registers */
-/* FIFO's Control/Status */
-#define GG82563_PHY_KMRN_FIFO_CTRL_STAT GG82563_REG(194, 16)
-#define GG82563_PHY_KMRN_CTRL GG82563_REG(194, 17) /* Control */
#define GG82563_PHY_INBAND_CTRL GG82563_REG(194, 18) /* Inband Ctrl */
-#define GG82563_PHY_KMRN_DIAGNOSTIC GG82563_REG(194, 19) /* Diagnostic */
-#define GG82563_PHY_ACK_TIMEOUTS GG82563_REG(194, 20) /* Ack Timeouts */
-#define GG82563_PHY_ADV_ABILITY GG82563_REG(194, 21) /* Adver Ability */
-/* Link Partner Advertised Ability */
-#define GG82563_PHY_LINK_PARTNER_ADV_ABILITY GG82563_REG(194, 23)
-#define GG82563_PHY_ADV_NEXT_PAGE GG82563_REG(194, 24) /* Adver Next Pg */
-/* Link Partner Advertised Next page */
-#define GG82563_PHY_LINK_PARTNER_ADV_NEXT_PAGE GG82563_REG(194, 25)
-#define GG82563_PHY_KMRN_MISC GG82563_REG(194, 26) /* Misc. */
/* MDI Control */
-#define E1000_MDIC_DATA_MASK 0x0000FFFF
#define E1000_MDIC_REG_MASK 0x001F0000
#define E1000_MDIC_REG_SHIFT 16
#define E1000_MDIC_PHY_MASK 0x03E00000
@@ -1762,7 +1318,6 @@
#define E1000_MDIC_OP_WRITE 0x04000000
#define E1000_MDIC_OP_READ 0x08000000
#define E1000_MDIC_READY 0x10000000
-#define E1000_MDIC_INT_EN 0x20000000
#define E1000_MDIC_ERROR 0x40000000
#define E1000_MDIC_DEST 0x80000000
@@ -1834,38 +1389,13 @@
/* Lx power decision based on DMA coal */
#define E1000_PCIEMISC_LX_DECISION 0x00000080
+#define E1000_RXPBS_CFG_TS_EN 0x80000000 /* Timestamp in Rx buffer */
#define E1000_RXPBS_SIZE_I210_MASK 0x0000003F /* Rx packet buffer size */
#define E1000_TXPB0S_SIZE_I210_MASK 0x0000003F /* Tx packet buffer 0 size */
-#define E1000_LTRC_EEEMS_EN 0x00000020 /* Enable EEE LTR max send */
-/* Minimum time for 1000BASE-T where no data will be transmit following move out
- * of EEE LPI Tx state
- */
-#define E1000_TW_SYSTEM_1000_MASK 0x000000FF
-/* Minimum time for 100BASE-T where no data will be transmit following move out
- * of EEE LPI Tx state
- */
-#define E1000_TW_SYSTEM_100_MASK 0x0000FF00
-#define E1000_TW_SYSTEM_100_SHIFT 8
-#define E1000_LTRMINV_LTRV_MASK 0x000003FF /* LTR minimum value */
-#define E1000_LTRMAXV_LTRV_MASK 0x000003FF /* LTR maximum value */
-#define E1000_LTRMINV_SCALE_MASK 0x00001C00 /* LTR minimum scale */
-#define E1000_LTRMINV_SCALE_SHIFT 10
-/* Reg val to set scale to 1024 nsec */
-#define E1000_LTRMINV_SCALE_1024 2
-/* Reg val to set scale to 32768 nsec */
-#define E1000_LTRMINV_SCALE_32768 3
-#define E1000_LTRMINV_LSNP_REQ 0x00008000 /* LTR Snoop Requirement */
-#define E1000_LTRMAXV_SCALE_MASK 0x00001C00 /* LTR maximum scale */
-#define E1000_LTRMAXV_SCALE_SHIFT 10
-/* Reg val to set scale to 1024 nsec */
-#define E1000_LTRMAXV_SCALE_1024 2
-/* Reg val to set scale to 32768 nsec */
-#define E1000_LTRMAXV_SCALE_32768 3
-#define E1000_LTRMAXV_LSNP_REQ 0x00008000 /* LTR Snoop Requirement */
#define E1000_DOBFFCTL_OBFFTHR_MASK 0x000000FF /* OBFF threshold */
#define E1000_DOBFFCTL_EXIT_ACT_MASK 0x01000000 /* Exit active CB */
-/* Proxy Filer Control */
+/* Proxy Filter Control */
#define E1000_PROXYFC_D0 0x00000001 /* Enable offload in D0 */
#define E1000_PROXYFC_EX 0x00000004 /* Directed exact proxy */
#define E1000_PROXYFC_MC 0x00000008 /* Directed MC Proxy */
@@ -1873,7 +1403,7 @@
#define E1000_PROXYFC_ARP_DIRECTED 0x00000020 /* Directed ARP Proxy Ena */
#define E1000_PROXYFC_IPV4 0x00000040 /* Directed IPv4 Enable */
#define E1000_PROXYFC_IPV6 0x00000080 /* Directed IPv6 Enable */
-#define E1000_PROXYFC_NS 0x00000200 /* IPv4 NBRHD Solicitation */
+#define E1000_PROXYFC_NS 0x00000200 /* IPv6 Neighbor Solicitation */
#define E1000_PROXYFC_ARP 0x00000800 /* ARP Request Proxy Ena */
/* Proxy Status */
#define E1000_PROXYS_CLEAR 0xFFFFFFFF /* Clear */
Property changes on: trunk/sys/dev/e1000/e1000_defines.h
___________________________________________________________________
Deleted: cvs2svn:cvs-rev
## -1 +0,0 ##
-1.4
\ No newline at end of property
Modified: trunk/sys/dev/e1000/e1000_hw.h
===================================================================
--- trunk/sys/dev/e1000/e1000_hw.h 2013-12-28 14:30:04 UTC (rev 6559)
+++ trunk/sys/dev/e1000/e1000_hw.h 2013-12-28 14:30:47 UTC (rev 6560)
@@ -1,6 +1,7 @@
+/* $MidnightBSD$ */
/******************************************************************************
- Copyright (c) 2001-2012, Intel Corporation
+ Copyright (c) 2001-2013, Intel Corporation
All rights reserved.
Redistribution and use in source and binary forms, with or without
@@ -30,7 +31,7 @@
POSSIBILITY OF SUCH DAMAGE.
******************************************************************************/
-/*$MidnightBSD$*/
+/*$FreeBSD: release/9.2.0/sys/dev/e1000/e1000_hw.h 248292 2013-03-14 22:55:59Z jfv $*/
#ifndef _E1000_HW_H_
#define _E1000_HW_H_
@@ -123,7 +124,6 @@
#define E1000_DEV_ID_ICH10_D_BM_LM 0x10DE
#define E1000_DEV_ID_ICH10_D_BM_LF 0x10DF
#define E1000_DEV_ID_ICH10_D_BM_V 0x1525
-
#define E1000_DEV_ID_PCH_M_HV_LM 0x10EA
#define E1000_DEV_ID_PCH_M_HV_LC 0x10EB
#define E1000_DEV_ID_PCH_D_HV_DM 0x10EF
@@ -130,6 +130,10 @@
#define E1000_DEV_ID_PCH_D_HV_DC 0x10F0
#define E1000_DEV_ID_PCH2_LV_LM 0x1502
#define E1000_DEV_ID_PCH2_LV_V 0x1503
+#define E1000_DEV_ID_PCH_LPT_I217_LM 0x153A
+#define E1000_DEV_ID_PCH_LPT_I217_V 0x153B
+#define E1000_DEV_ID_PCH_LPTLP_I218_LM 0x155A
+#define E1000_DEV_ID_PCH_LPTLP_I218_V 0x1559
#define E1000_DEV_ID_82576 0x10C9
#define E1000_DEV_ID_82576_FIBER 0x10E6
#define E1000_DEV_ID_82576_SERDES 0x10E7
@@ -139,7 +143,9 @@
#define E1000_DEV_ID_82576_NS_SERDES 0x1518
#define E1000_DEV_ID_82576_SERDES_QUAD 0x150D
#define E1000_DEV_ID_82576_VF 0x10CA
+#define E1000_DEV_ID_82576_VF_HV 0x152D
#define E1000_DEV_ID_I350_VF 0x1520
+#define E1000_DEV_ID_I350_VF_HV 0x152F
#define E1000_DEV_ID_82575EB_COPPER 0x10A7
#define E1000_DEV_ID_82575EB_FIBER_SERDES 0x10A9
#define E1000_DEV_ID_82575GB_QUAD_COPPER 0x10D6
@@ -165,6 +171,7 @@
#define E1000_DEV_ID_DH89XXCC_SERDES 0x043A
#define E1000_DEV_ID_DH89XXCC_BACKPLANE 0x043C
#define E1000_DEV_ID_DH89XXCC_SFP 0x0440
+
#define E1000_REVISION_0 0
#define E1000_REVISION_1 1
#define E1000_REVISION_2 2
@@ -206,6 +213,7 @@
e1000_ich10lan,
e1000_pchlan,
e1000_pch2lan,
+ e1000_pch_lpt,
e1000_82575,
e1000_82576,
e1000_82580,
@@ -255,6 +263,7 @@
e1000_phy_82578,
e1000_phy_82577,
e1000_phy_82579,
+ e1000_phy_i217,
e1000_phy_82580,
e1000_phy_vf,
e1000_phy_i210,
@@ -651,13 +660,13 @@
#include "e1000_manage.h"
#include "e1000_mbx.h"
+/* Function pointers for the MAC. */
struct e1000_mac_operations {
- /* Function pointers for the MAC. */
s32 (*init_params)(struct e1000_hw *);
s32 (*id_led_init)(struct e1000_hw *);
s32 (*blink_led)(struct e1000_hw *);
+ bool (*check_mng_mode)(struct e1000_hw *);
s32 (*check_for_link)(struct e1000_hw *);
- bool (*check_mng_mode)(struct e1000_hw *hw);
s32 (*cleanup_led)(struct e1000_hw *);
void (*clear_hw_cntrs)(struct e1000_hw *);
void (*clear_vfta)(struct e1000_hw *);
@@ -679,17 +688,12 @@
void (*rar_set)(struct e1000_hw *, u8*, u32);
s32 (*read_mac_addr)(struct e1000_hw *);
s32 (*validate_mdi_setting)(struct e1000_hw *);
- s32 (*mng_host_if_write)(struct e1000_hw *, u8*, u16, u16, u8*);
- s32 (*mng_write_cmd_header)(struct e1000_hw *hw,
- struct e1000_host_mng_command_header*);
- s32 (*mng_enable_host_if)(struct e1000_hw *);
- s32 (*wait_autoneg)(struct e1000_hw *);
+ s32 (*set_obff_timer)(struct e1000_hw *, u32);
s32 (*acquire_swfw_sync)(struct e1000_hw *, u16);
void (*release_swfw_sync)(struct e1000_hw *, u16);
};
-/*
- * When to use various PHY register access functions:
+/* When to use various PHY register access functions:
*
* Func Caller
* Function Does Does When to use
@@ -731,6 +735,7 @@
s32 (*write_i2c_byte)(struct e1000_hw *, u8, u8, u8);
};
+/* Function pointers for the NVM. */
struct e1000_nvm_operations {
s32 (*init_params)(struct e1000_hw *);
s32 (*acquire)(struct e1000_hw *);
@@ -785,6 +790,7 @@
enum e1000_serdes_link_state serdes_link_state;
bool serdes_has_link;
bool tx_pkt_filtering;
+ u32 max_frame_size;
};
struct e1000_phy_info {
@@ -915,7 +921,7 @@
bool modified;
};
-#define E1000_SHADOW_RAM_WORDS 2048
+#define E1000_SHADOW_RAM_WORDS 2048
struct e1000_dev_spec_ich8lan {
bool kmrn_lock_loss_workaround_enabled;
@@ -924,6 +930,7 @@
E1000_MUTEX swflag_mutex;
bool nvm_k1_enabled;
bool eee_disable;
+ u16 eee_lp_ability;
};
struct e1000_dev_spec_82575 {
@@ -931,7 +938,9 @@
bool global_device_reset;
bool eee_disable;
bool module_plugged;
+ bool clear_semaphore_once;
u32 mtu;
+ struct sfp_e1000_flags eth_flags;
};
struct e1000_dev_spec_vf {
Property changes on: trunk/sys/dev/e1000/e1000_hw.h
___________________________________________________________________
Deleted: cvs2svn:cvs-rev
## -1 +0,0 ##
-1.4
\ No newline at end of property
Modified: trunk/sys/dev/e1000/e1000_i210.c
===================================================================
--- trunk/sys/dev/e1000/e1000_i210.c 2013-12-28 14:30:04 UTC (rev 6559)
+++ trunk/sys/dev/e1000/e1000_i210.c 2013-12-28 14:30:47 UTC (rev 6560)
@@ -1,6 +1,7 @@
+/* $MidnightBSD$ */
/******************************************************************************
- Copyright (c) 2001-2012, Intel Corporation
+ Copyright (c) 2001-2013, Intel Corporation
All rights reserved.
Redistribution and use in source and binary forms, with or without
@@ -30,7 +31,7 @@
POSSIBILITY OF SUCH DAMAGE.
******************************************************************************/
-/*$MidnightBSD$*/
+/*$FreeBSD: release/9.2.0/sys/dev/e1000/e1000_i210.c 248292 2013-03-14 22:55:59Z jfv $*/
#include "e1000_api.h"
@@ -38,7 +39,6 @@
static s32 e1000_acquire_nvm_i210(struct e1000_hw *hw);
static void e1000_release_nvm_i210(struct e1000_hw *hw);
static s32 e1000_get_hw_semaphore_i210(struct e1000_hw *hw);
-static void e1000_put_hw_semaphore_i210(struct e1000_hw *hw);
static s32 e1000_write_nvm_srwr(struct e1000_hw *hw, u16 offset, u16 words,
u16 *data);
static s32 e1000_pool_flash_update_done_i210(struct e1000_hw *hw);
@@ -105,13 +105,14 @@
}
swfw_sync = E1000_READ_REG(hw, E1000_SW_FW_SYNC);
- if (!(swfw_sync & fwmask))
+ if (!(swfw_sync & (fwmask | swmask)))
break;
/*
* Firmware currently using resource (fwmask)
+ * or other software thread using resource (swmask)
*/
- e1000_put_hw_semaphore_i210(hw);
+ e1000_put_hw_semaphore_generic(hw);
msec_delay_irq(5);
i++;
}
@@ -125,7 +126,7 @@
swfw_sync |= swmask;
E1000_WRITE_REG(hw, E1000_SW_FW_SYNC, swfw_sync);
- e1000_put_hw_semaphore_i210(hw);
+ e1000_put_hw_semaphore_generic(hw);
out:
return ret_val;
@@ -152,7 +153,7 @@
swfw_sync &= ~mask;
E1000_WRITE_REG(hw, E1000_SW_FW_SYNC, swfw_sync);
- e1000_put_hw_semaphore_i210(hw);
+ e1000_put_hw_semaphore_generic(hw);
}
/**
@@ -164,12 +165,45 @@
static s32 e1000_get_hw_semaphore_i210(struct e1000_hw *hw)
{
u32 swsm;
- s32 ret_val = E1000_SUCCESS;
s32 timeout = hw->nvm.word_size + 1;
s32 i = 0;
DEBUGFUNC("e1000_get_hw_semaphore_i210");
+ /* Get the SW semaphore */
+ while (i < timeout) {
+ swsm = E1000_READ_REG(hw, E1000_SWSM);
+ if (!(swsm & E1000_SWSM_SMBI))
+ break;
+
+ usec_delay(50);
+ i++;
+ }
+
+ if (i == timeout) {
+ /*
+ * In rare circumstances, the driver may not have released the
+ * SW semaphore. Clear the semaphore once before giving up.
+ */
+ if (hw->dev_spec._82575.clear_semaphore_once) {
+ hw->dev_spec._82575.clear_semaphore_once = FALSE;
+ e1000_put_hw_semaphore_generic(hw);
+ for (i = 0; i < timeout; i++) {
+ swsm = E1000_READ_REG(hw, E1000_SWSM);
+ if (!(swsm & E1000_SWSM_SMBI))
+ break;
+
+ usec_delay(50);
+ }
+ }
+
+ /* If we do not have the semaphore here, we have to give up. */
+ if (i == timeout) {
+ DEBUGOUT("Driver can't access device - SMBI bit is set.\n");
+ return -E1000_ERR_NVM;
+ }
+ }
+
/* Get the FW semaphore. */
for (i = 0; i < timeout; i++) {
swsm = E1000_READ_REG(hw, E1000_SWSM);
@@ -186,34 +220,13 @@
/* Release semaphores */
e1000_put_hw_semaphore_generic(hw);
DEBUGOUT("Driver can't access the NVM\n");
- ret_val = -E1000_ERR_NVM;
- goto out;
+ return -E1000_ERR_NVM;
}
-out:
- return ret_val;
+ return E1000_SUCCESS;
}
/**
- * e1000_put_hw_semaphore_i210 - Release hardware semaphore
- * @hw: pointer to the HW structure
- *
- * Release hardware semaphore used to access the PHY or NVM
- **/
-static void e1000_put_hw_semaphore_i210(struct e1000_hw *hw)
-{
- u32 swsm;
-
- DEBUGFUNC("e1000_put_hw_semaphore_i210");
-
- swsm = E1000_READ_REG(hw, E1000_SWSM);
-
- swsm &= ~E1000_SWSM_SWESMBI;
-
- E1000_WRITE_REG(hw, E1000_SWSM, swsm);
-}
-
-/**
* e1000_read_nvm_srrd_i210 - Reads Shadow Ram using EERD register
* @hw: pointer to the HW structure
* @offset: offset of word in the Shadow Ram to read
@@ -364,8 +377,8 @@
*
* Wrapper function to return data formerly found in the NVM.
**/
-static s32 e1000_read_nvm_i211(struct e1000_hw *hw, u16 offset, u16 words,
- u16 *data)
+static s32 e1000_read_nvm_i211(struct e1000_hw *hw, u16 offset,
+ u16 words, u16 *data)
{
s32 ret_val = E1000_SUCCESS;
@@ -380,15 +393,40 @@
if (ret_val != E1000_SUCCESS)
DEBUGOUT("MAC Addr not found in iNVM\n");
break;
- case NVM_ID_LED_SETTINGS:
case NVM_INIT_CTRL_2:
+ ret_val = e1000_read_invm_i211(hw, (u8)offset, data);
+ if (ret_val != E1000_SUCCESS) {
+ *data = NVM_INIT_CTRL_2_DEFAULT_I211;
+ ret_val = E1000_SUCCESS;
+ }
+ break;
case NVM_INIT_CTRL_4:
+ ret_val = e1000_read_invm_i211(hw, (u8)offset, data);
+ if (ret_val != E1000_SUCCESS) {
+ *data = NVM_INIT_CTRL_4_DEFAULT_I211;
+ ret_val = E1000_SUCCESS;
+ }
+ break;
case NVM_LED_1_CFG:
+ ret_val = e1000_read_invm_i211(hw, (u8)offset, data);
+ if (ret_val != E1000_SUCCESS) {
+ *data = NVM_LED_1_CFG_DEFAULT_I211;
+ ret_val = E1000_SUCCESS;
+ }
+ break;
case NVM_LED_0_2_CFG:
- e1000_read_invm_i211(hw, (u8)offset, data);
+ ret_val = e1000_read_invm_i211(hw, (u8)offset, data);
+ if (ret_val != E1000_SUCCESS) {
+ *data = NVM_LED_0_2_CFG_DEFAULT_I211;
+ ret_val = E1000_SUCCESS;
+ }
break;
- case NVM_COMPAT:
- *data = ID_LED_DEFAULT_I210;
+ case NVM_ID_LED_SETTINGS:
+ ret_val = e1000_read_invm_i211(hw, (u8)offset, data);
+ if (ret_val != E1000_SUCCESS) {
+ *data = ID_LED_RESERVED_FFFF;
+ ret_val = E1000_SUCCESS;
+ }
break;
case NVM_SUB_DEV_ID:
*data = hw->subsystem_device_id;
@@ -555,26 +593,6 @@
}
/**
- * e1000_get_flash_presence_i210 - Check if flash device is detected.
- * @hw: pointer to the HW structure
- *
- **/
-static bool e1000_get_flash_presence_i210(struct e1000_hw *hw)
-{
- u32 eec = 0;
- bool ret_val = FALSE;
-
- DEBUGFUNC("e1000_get_flash_presence_i210");
-
- eec = E1000_READ_REG(hw, E1000_EECD);
-
- if (eec & E1000_EECD_FLASH_DETECTED_I210)
- ret_val = TRUE;
-
- return ret_val;
-}
-
-/**
* e1000_update_flash_i210 - Commit EEPROM to the flash
* @hw: pointer to the HW structure
*
@@ -690,10 +708,7 @@
switch (hw->mac.type) {
case e1000_i210:
- if (e1000_get_flash_presence_i210(hw))
- hw->nvm.ops.init_params = e1000_init_nvm_params_i210;
- else
- hw->nvm.ops.init_params = e1000_init_nvm_params_i211;
+ hw->nvm.ops.init_params = e1000_init_nvm_params_i210;
break;
case e1000_i211:
hw->nvm.ops.init_params = e1000_init_nvm_params_i211;
Property changes on: trunk/sys/dev/e1000/e1000_i210.c
___________________________________________________________________
Deleted: cvs2svn:cvs-rev
## -1 +0,0 ##
-1.2
\ No newline at end of property
Modified: trunk/sys/dev/e1000/e1000_i210.h
===================================================================
--- trunk/sys/dev/e1000/e1000_i210.h 2013-12-28 14:30:04 UTC (rev 6559)
+++ trunk/sys/dev/e1000/e1000_i210.h 2013-12-28 14:30:47 UTC (rev 6560)
@@ -1,6 +1,7 @@
+/* $MidnightBSD$ */
/******************************************************************************
- Copyright (c) 2001-2012, Intel Corporation
+ Copyright (c) 2001-2013, Intel Corporation
All rights reserved.
Redistribution and use in source and binary forms, with or without
@@ -30,7 +31,7 @@
POSSIBILITY OF SUCH DAMAGE.
******************************************************************************/
-/*$MidnightBSD$*/
+/*$FreeBSD: release/9.2.0/sys/dev/e1000/e1000_i210.h 248292 2013-03-14 22:55:59Z jfv $*/
#ifndef _E1000_I210_H_
#define _E1000_I210_H_
@@ -43,8 +44,6 @@
s32 e1000_read_nvm_srrd_i210(struct e1000_hw *hw, u16 offset,
u16 words, u16 *data);
s32 e1000_read_invm_i211(struct e1000_hw *hw, u8 address, u16 *data);
-s32 e1000_check_for_copper_link_i210(struct e1000_hw *hw);
-s32 e1000_set_ltr_i210(struct e1000_hw *hw, bool link);
s32 e1000_acquire_swfw_sync_i210(struct e1000_hw *hw, u16 mask);
void e1000_release_swfw_sync_i210(struct e1000_hw *hw, u16 mask);
@@ -69,7 +68,16 @@
#define E1000_INVM_RSA_KEY_SHA256_DATA_SIZE_IN_DWORDS 8
#define E1000_INVM_CSR_AUTOLOAD_DATA_SIZE_IN_DWORDS 1
+#define E1000_INVM_ULT_BYTES_SIZE 8
+#define E1000_INVM_RECORD_SIZE_IN_BYTES 4
+#define E1000_INVM_VER_FIELD_ONE 0x1FF8
+#define E1000_INVM_VER_FIELD_TWO 0x7FE000
+#define E1000_INVM_IMGTYPE_FIELD 0x1F800000
+#define E1000_INVM_MAJOR_MASK 0x3F0
+#define E1000_INVM_MINOR_MASK 0xF
+#define E1000_INVM_MAJOR_SHIFT 4
+
#define ID_LED_DEFAULT_I210 ((ID_LED_OFF1_ON2 << 8) | \
(ID_LED_DEF1_DEF2 << 4) | \
(ID_LED_OFF1_OFF2))
@@ -77,4 +85,9 @@
(ID_LED_DEF1_DEF2 << 4) | \
(ID_LED_DEF1_DEF2))
+/* NVM offset defaults for I211 devices */
+#define NVM_INIT_CTRL_2_DEFAULT_I211 0X7243
+#define NVM_INIT_CTRL_4_DEFAULT_I211 0x00C1
+#define NVM_LED_1_CFG_DEFAULT_I211 0x0184
+#define NVM_LED_0_2_CFG_DEFAULT_I211 0x200C
#endif
Property changes on: trunk/sys/dev/e1000/e1000_i210.h
___________________________________________________________________
Deleted: cvs2svn:cvs-rev
## -1 +0,0 ##
-1.2
\ No newline at end of property
Modified: trunk/sys/dev/e1000/e1000_ich8lan.c
===================================================================
--- trunk/sys/dev/e1000/e1000_ich8lan.c 2013-12-28 14:30:04 UTC (rev 6559)
+++ trunk/sys/dev/e1000/e1000_ich8lan.c 2013-12-28 14:30:47 UTC (rev 6560)
@@ -1,6 +1,7 @@
+/* $MidnightBSD$ */
/******************************************************************************
- Copyright (c) 2001-2011, Intel Corporation
+ Copyright (c) 2001-2013, Intel Corporation
All rights reserved.
Redistribution and use in source and binary forms, with or without
@@ -30,10 +31,9 @@
POSSIBILITY OF SUCH DAMAGE.
******************************************************************************/
-/*$MidnightBSD$*/
+/*$FreeBSD: release/9.2.0/sys/dev/e1000/e1000_ich8lan.c 248292 2013-03-14 22:55:59Z jfv $*/
-/*
- * 82562G 10/100 Network Connection
+/* 82562G 10/100 Network Connection
* 82562G-2 10/100 Network Connection
* 82562GT 10/100 Network Connection
* 82562GT-2 10/100 Network Connection
@@ -64,10 +64,6 @@
#include "e1000_api.h"
-static s32 e1000_init_phy_params_ich8lan(struct e1000_hw *hw);
-static s32 e1000_init_phy_params_pchlan(struct e1000_hw *hw);
-static s32 e1000_init_nvm_params_ich8lan(struct e1000_hw *hw);
-static s32 e1000_init_mac_params_ich8lan(struct e1000_hw *hw);
static s32 e1000_acquire_swflag_ich8lan(struct e1000_hw *hw);
static void e1000_release_swflag_ich8lan(struct e1000_hw *hw);
static s32 e1000_acquire_nvm_ich8lan(struct e1000_hw *hw);
@@ -75,6 +71,7 @@
static bool e1000_check_mng_mode_ich8lan(struct e1000_hw *hw);
static bool e1000_check_mng_mode_pchlan(struct e1000_hw *hw);
static void e1000_rar_set_pch2lan(struct e1000_hw *hw, u8 *addr, u32 index);
+static void e1000_rar_set_pch_lpt(struct e1000_hw *hw, u8 *addr, u32 index);
static void e1000_update_mc_addr_list_pch2lan(struct e1000_hw *hw,
u8 *mc_addr_list,
u32 mc_addr_count);
@@ -99,6 +96,7 @@
static s32 e1000_init_hw_ich8lan(struct e1000_hw *hw);
static s32 e1000_setup_link_ich8lan(struct e1000_hw *hw);
static s32 e1000_setup_copper_link_ich8lan(struct e1000_hw *hw);
+static s32 e1000_setup_copper_link_pch_lpt(struct e1000_hw *hw);
static s32 e1000_get_link_up_info_ich8lan(struct e1000_hw *hw,
u16 *speed, u16 *duplex);
static s32 e1000_cleanup_led_ich8lan(struct e1000_hw *hw);
@@ -111,8 +109,6 @@
static s32 e1000_led_off_pchlan(struct e1000_hw *hw);
static void e1000_clear_hw_cntrs_ich8lan(struct e1000_hw *hw);
static s32 e1000_erase_flash_bank_ich8lan(struct e1000_hw *hw, u32 bank);
-static s32 e1000_flash_cycle_ich8lan(struct e1000_hw *hw, u32 timeout);
-static s32 e1000_flash_cycle_init_ich8lan(struct e1000_hw *hw);
static void e1000_initialize_hw_bits_ich8lan(struct e1000_hw *hw);
static s32 e1000_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw);
static s32 e1000_read_flash_byte_ich8lan(struct e1000_hw *hw,
@@ -123,22 +119,14 @@
u32 offset, u16 *data);
static s32 e1000_retry_write_flash_byte_ich8lan(struct e1000_hw *hw,
u32 offset, u8 byte);
-static s32 e1000_write_flash_byte_ich8lan(struct e1000_hw *hw,
- u32 offset, u8 data);
-static s32 e1000_write_flash_data_ich8lan(struct e1000_hw *hw, u32 offset,
- u8 size, u16 data);
static s32 e1000_get_cfg_done_ich8lan(struct e1000_hw *hw);
static void e1000_power_down_phy_copper_ich8lan(struct e1000_hw *hw);
static s32 e1000_check_for_copper_link_ich8lan(struct e1000_hw *hw);
-static void e1000_lan_init_done_ich8lan(struct e1000_hw *hw);
-static s32 e1000_sw_lcd_config_ich8lan(struct e1000_hw *hw);
static s32 e1000_set_mdio_slow_mode_hv(struct e1000_hw *hw);
static s32 e1000_k1_workaround_lv(struct e1000_hw *hw);
static void e1000_gate_hw_phy_config_ich8lan(struct e1000_hw *hw, bool gate);
-#if defined(NAHUM6_HW) && (defined(LTR_SUPPORT) || defined(OBFF_SUPPORT))
+static s32 e1000_set_obff_timer_pch_lpt(struct e1000_hw *hw, u32 itr);
-#endif /* NAHUM6_HW && (LTR_SUPPORT || OBFF_SUPPORT) */
-
/* ICH GbE Flash Hardware Sequencing Flash Status Register bit breakdown */
/* Offset 04h HSFSTS */
union ich8_hws_flash_status {
@@ -180,23 +168,193 @@
u16 regval;
};
-static void e1000_toggle_lanphypc_value_ich8lan(struct e1000_hw *hw)
+/**
+ * e1000_phy_is_accessible_pchlan - Check if able to access PHY registers
+ * @hw: pointer to the HW structure
+ *
+ * Test access to the PHY registers by reading the PHY ID registers. If
+ * the PHY ID is already known (e.g. resume path) compare it with known ID,
+ * otherwise assume the read PHY ID is correct if it is valid.
+ *
+ * Assumes the sw/fw/hw semaphore is already acquired.
+ **/
+static bool e1000_phy_is_accessible_pchlan(struct e1000_hw *hw)
{
- u32 ctrl;
+ u16 phy_reg = 0;
+ u32 phy_id = 0;
+ s32 ret_val;
+ u16 retry_count;
- DEBUGFUNC("e1000_toggle_lanphypc_value_ich8lan");
+ for (retry_count = 0; retry_count < 2; retry_count++) {
+ ret_val = hw->phy.ops.read_reg_locked(hw, PHY_ID1, &phy_reg);
+ if (ret_val || (phy_reg == 0xFFFF))
+ continue;
+ phy_id = (u32)(phy_reg << 16);
- ctrl = E1000_READ_REG(hw, E1000_CTRL);
- ctrl |= E1000_CTRL_LANPHYPC_OVERRIDE;
- ctrl &= ~E1000_CTRL_LANPHYPC_VALUE;
- E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
- E1000_WRITE_FLUSH(hw);
- usec_delay(10);
- ctrl &= ~E1000_CTRL_LANPHYPC_OVERRIDE;
- E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
+ ret_val = hw->phy.ops.read_reg_locked(hw, PHY_ID2, &phy_reg);
+ if (ret_val || (phy_reg == 0xFFFF)) {
+ phy_id = 0;
+ continue;
+ }
+ phy_id |= (u32)(phy_reg & PHY_REVISION_MASK);
+ break;
+ }
+
+ if (hw->phy.id) {
+ if (hw->phy.id == phy_id)
+ return TRUE;
+ } else if (phy_id) {
+ hw->phy.id = phy_id;
+ hw->phy.revision = (u32)(phy_reg & ~PHY_REVISION_MASK);
+ return TRUE;
+ }
+
+ /* In case the PHY needs to be in mdio slow mode,
+ * set slow mode and try to get the PHY id again.
+ */
+ hw->phy.ops.release(hw);
+ ret_val = e1000_set_mdio_slow_mode_hv(hw);
+ if (!ret_val)
+ ret_val = e1000_get_phy_id(hw);
+ hw->phy.ops.acquire(hw);
+
+ return !ret_val;
}
/**
+ * e1000_init_phy_workarounds_pchlan - PHY initialization workarounds
+ * @hw: pointer to the HW structure
+ *
+ * Workarounds/flow necessary for PHY initialization during driver load
+ * and resume paths.
+ **/
+static s32 e1000_init_phy_workarounds_pchlan(struct e1000_hw *hw)
+{
+ u32 mac_reg, fwsm = E1000_READ_REG(hw, E1000_FWSM);
+ s32 ret_val;
+ u16 phy_reg;
+
+ DEBUGFUNC("e1000_init_phy_workarounds_pchlan");
+
+ /* Gate automatic PHY configuration by hardware on managed and
+ * non-managed 82579 and newer adapters.
+ */
+ e1000_gate_hw_phy_config_ich8lan(hw, TRUE);
+
+ ret_val = hw->phy.ops.acquire(hw);
+ if (ret_val) {
+ DEBUGOUT("Failed to initialize PHY flow\n");
+ goto out;
+ }
+
+ /* The MAC-PHY interconnect may be in SMBus mode. If the PHY is
+ * inaccessible and resetting the PHY is not blocked, toggle the
+ * LANPHYPC Value bit to force the interconnect to PCIe mode.
+ */
+ switch (hw->mac.type) {
+ case e1000_pch_lpt:
+ if (e1000_phy_is_accessible_pchlan(hw))
+ break;
+
+ /* Before toggling LANPHYPC, see if PHY is accessible by
+ * forcing MAC to SMBus mode first.
+ */
+ mac_reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
+ mac_reg |= E1000_CTRL_EXT_FORCE_SMBUS;
+ E1000_WRITE_REG(hw, E1000_CTRL_EXT, mac_reg);
+
+ /* fall-through */
+ case e1000_pch2lan:
+ if (e1000_phy_is_accessible_pchlan(hw)) {
+ if (hw->mac.type == e1000_pch_lpt) {
+ /* Unforce SMBus mode in PHY */
+ hw->phy.ops.read_reg_locked(hw, CV_SMB_CTRL,
+ &phy_reg);
+ phy_reg &= ~CV_SMB_CTRL_FORCE_SMBUS;
+ hw->phy.ops.write_reg_locked(hw, CV_SMB_CTRL,
+ phy_reg);
+
+ /* Unforce SMBus mode in MAC */
+ mac_reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
+ mac_reg &= ~E1000_CTRL_EXT_FORCE_SMBUS;
+ E1000_WRITE_REG(hw, E1000_CTRL_EXT, mac_reg);
+ }
+ break;
+ }
+
+ /* fall-through */
+ case e1000_pchlan:
+ if ((hw->mac.type == e1000_pchlan) &&
+ (fwsm & E1000_ICH_FWSM_FW_VALID))
+ break;
+
+ if (hw->phy.ops.check_reset_block(hw)) {
+ DEBUGOUT("Required LANPHYPC toggle blocked by ME\n");
+ break;
+ }
+
+ DEBUGOUT("Toggling LANPHYPC\n");
+
+ /* Set Phy Config Counter to 50msec */
+ mac_reg = E1000_READ_REG(hw, E1000_FEXTNVM3);
+ mac_reg &= ~E1000_FEXTNVM3_PHY_CFG_COUNTER_MASK;
+ mac_reg |= E1000_FEXTNVM3_PHY_CFG_COUNTER_50MSEC;
+ E1000_WRITE_REG(hw, E1000_FEXTNVM3, mac_reg);
+
+ if (hw->mac.type == e1000_pch_lpt) {
+ /* Toggling LANPHYPC brings the PHY out of SMBus mode
+ * So ensure that the MAC is also out of SMBus mode
+ */
+ mac_reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
+ mac_reg &= ~E1000_CTRL_EXT_FORCE_SMBUS;
+ E1000_WRITE_REG(hw, E1000_CTRL_EXT, mac_reg);
+ }
+
+ /* Toggle LANPHYPC Value bit */
+ mac_reg = E1000_READ_REG(hw, E1000_CTRL);
+ mac_reg |= E1000_CTRL_LANPHYPC_OVERRIDE;
+ mac_reg &= ~E1000_CTRL_LANPHYPC_VALUE;
+ E1000_WRITE_REG(hw, E1000_CTRL, mac_reg);
+ E1000_WRITE_FLUSH(hw);
+ usec_delay(10);
+ mac_reg &= ~E1000_CTRL_LANPHYPC_OVERRIDE;
+ E1000_WRITE_REG(hw, E1000_CTRL, mac_reg);
+ E1000_WRITE_FLUSH(hw);
+ if (hw->mac.type < e1000_pch_lpt) {
+ msec_delay(50);
+ } else {
+ u16 count = 20;
+ do {
+ msec_delay(5);
+ } while (!(E1000_READ_REG(hw, E1000_CTRL_EXT) &
+ E1000_CTRL_EXT_LPCD) && count--);
+ }
+ break;
+ default:
+ break;
+ }
+
+ hw->phy.ops.release(hw);
+
+ /* Reset the PHY before any access to it. Doing so, ensures
+ * that the PHY is in a known good state before we read/write
+ * PHY registers. The generic reset is sufficient here,
+ * because we haven't determined the PHY type yet.
+ */
+ ret_val = e1000_phy_hw_reset_generic(hw);
+
+out:
+ /* Ungate automatic PHY configuration on non-managed 82579 */
+ if ((hw->mac.type == e1000_pch2lan) &&
+ !(fwsm & E1000_ICH_FWSM_FW_VALID)) {
+ msec_delay(10);
+ e1000_gate_hw_phy_config_ich8lan(hw, FALSE);
+ }
+
+ return ret_val;
+}
+
+/**
* e1000_init_phy_params_pchlan - Initialize PHY function pointers
* @hw: pointer to the HW structure
*
@@ -205,7 +363,7 @@
static s32 e1000_init_phy_params_pchlan(struct e1000_hw *hw)
{
struct e1000_phy_info *phy = &hw->phy;
- s32 ret_val = E1000_SUCCESS;
+ s32 ret_val;
DEBUGFUNC("e1000_init_phy_params_pchlan");
@@ -230,70 +388,40 @@
phy->ops.power_down = e1000_power_down_phy_copper_ich8lan;
phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT;
- if (!hw->phy.ops.check_reset_block(hw)) {
- u32 fwsm = E1000_READ_REG(hw, E1000_FWSM);
+ phy->id = e1000_phy_unknown;
- /*
- * The MAC-PHY interconnect may still be in SMBus mode after
- * Sx->S0. If resetting the PHY is not blocked, toggle the
- * LANPHYPC Value bit to force the interconnect to PCIe mode.
- */
- e1000_toggle_lanphypc_value_ich8lan(hw);
- msec_delay(50);
+ ret_val = e1000_init_phy_workarounds_pchlan(hw);
+ if (ret_val)
+ return ret_val;
- /*
- * Gate automatic PHY configuration by hardware on
- * non-managed 82579
- */
- if ((hw->mac.type == e1000_pch2lan) &&
- !(fwsm & E1000_ICH_FWSM_FW_VALID))
- e1000_gate_hw_phy_config_ich8lan(hw, TRUE);
-
- /*
- * Reset the PHY before any access to it. Doing so, ensures
- * that the PHY is in a known good state before we read/write
- * PHY registers. The generic reset is sufficient here,
- * because we haven't determined the PHY type yet.
- */
- ret_val = e1000_phy_hw_reset_generic(hw);
- if (ret_val)
- goto out;
-
- /* Ungate automatic PHY configuration on non-managed 82579 */
- if ((hw->mac.type == e1000_pch2lan) &&
- !(fwsm & E1000_ICH_FWSM_FW_VALID)) {
- msec_delay(10);
- e1000_gate_hw_phy_config_ich8lan(hw, FALSE);
+ if (phy->id == e1000_phy_unknown)
+ switch (hw->mac.type) {
+ default:
+ ret_val = e1000_get_phy_id(hw);
+ if (ret_val)
+ return ret_val;
+ if ((phy->id != 0) && (phy->id != PHY_REVISION_MASK))
+ break;
+ /* fall-through */
+ case e1000_pch2lan:
+ case e1000_pch_lpt:
+ /* In case the PHY needs to be in mdio slow mode,
+ * set slow mode and try to get the PHY id again.
+ */
+ ret_val = e1000_set_mdio_slow_mode_hv(hw);
+ if (ret_val)
+ return ret_val;
+ ret_val = e1000_get_phy_id(hw);
+ if (ret_val)
+ return ret_val;
+ break;
}
- }
-
- phy->id = e1000_phy_unknown;
- switch (hw->mac.type) {
- default:
- ret_val = e1000_get_phy_id(hw);
- if (ret_val)
- goto out;
- if ((phy->id != 0) && (phy->id != PHY_REVISION_MASK))
- break;
- /* fall-through */
- case e1000_pch2lan:
- /*
- * In case the PHY needs to be in mdio slow mode,
- * set slow mode and try to get the PHY id again.
- */
- ret_val = e1000_set_mdio_slow_mode_hv(hw);
- if (ret_val)
- goto out;
- ret_val = e1000_get_phy_id(hw);
- if (ret_val)
- goto out;
- break;
- }
phy->type = e1000_get_phy_type_from_id(phy->id);
switch (phy->type) {
case e1000_phy_82577:
case e1000_phy_82579:
+ case e1000_phy_i217:
phy->ops.check_polarity = e1000_check_polarity_82577;
phy->ops.force_speed_duplex =
e1000_phy_force_speed_duplex_82577;
@@ -312,7 +440,6 @@
break;
}
-out:
return ret_val;
}
@@ -325,7 +452,7 @@
static s32 e1000_init_phy_params_ich8lan(struct e1000_hw *hw)
{
struct e1000_phy_info *phy = &hw->phy;
- s32 ret_val = E1000_SUCCESS;
+ s32 ret_val;
u16 i = 0;
DEBUGFUNC("e1000_init_phy_params_ich8lan");
@@ -346,8 +473,7 @@
phy->ops.power_up = e1000_power_up_phy_copper;
phy->ops.power_down = e1000_power_down_phy_copper_ich8lan;
- /*
- * We may need to do this twice - once for IGP and if that fails,
+ /* We may need to do this twice - once for IGP and if that fails,
* we'll set BM func pointers and try again
*/
ret_val = e1000_determine_phy_address(hw);
@@ -357,7 +483,7 @@
ret_val = e1000_determine_phy_address(hw);
if (ret_val) {
DEBUGOUT("Cannot determine PHY addr. Erroring out\n");
- goto out;
+ return ret_val;
}
}
@@ -367,7 +493,7 @@
msec_delay(1);
ret_val = e1000_get_phy_id(hw);
if (ret_val)
- goto out;
+ return ret_val;
}
/* Verify phy id */
@@ -401,12 +527,11 @@
phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_m88;
break;
default:
- ret_val = -E1000_ERR_PHY;
- goto out;
+ return -E1000_ERR_PHY;
+ break;
}
-out:
- return ret_val;
+ return E1000_SUCCESS;
}
/**
@@ -421,7 +546,6 @@
struct e1000_nvm_info *nvm = &hw->nvm;
struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
u32 gfpreg, sector_base_addr, sector_end_addr;
- s32 ret_val = E1000_SUCCESS;
u16 i;
DEBUGFUNC("e1000_init_nvm_params_ich8lan");
@@ -429,8 +553,7 @@
/* Can't read flash registers if the register set isn't mapped. */
if (!hw->flash_address) {
DEBUGOUT("ERROR: Flash registers not mapped\n");
- ret_val = -E1000_ERR_CONFIG;
- goto out;
+ return -E1000_ERR_CONFIG;
}
nvm->type = e1000_nvm_flash_sw;
@@ -437,8 +560,7 @@
gfpreg = E1000_READ_FLASH_REG(hw, ICH_FLASH_GFPREG);
- /*
- * sector_X_addr is a "sector"-aligned address (4096 bytes)
+ /* sector_X_addr is a "sector"-aligned address (4096 bytes)
* Add 1 to sector_end_addr since this sector is included in
* the overall size.
*/
@@ -448,8 +570,7 @@
/* flash_base_addr is byte-aligned */
nvm->flash_base_addr = sector_base_addr << FLASH_SECTOR_ADDR_SHIFT;
- /*
- * find total size of the NVM, then cut in half since the total
+ /* find total size of the NVM, then cut in half since the total
* size represents two separate NVM banks.
*/
nvm->flash_bank_size = (sector_end_addr - sector_base_addr)
@@ -478,8 +599,7 @@
nvm->ops.validate = e1000_validate_nvm_checksum_ich8lan;
nvm->ops.write = e1000_write_nvm_ich8lan;
-out:
- return ret_val;
+ return E1000_SUCCESS;
}
/**
@@ -536,7 +656,7 @@
/* clear hardware counters */
mac->ops.clear_hw_cntrs = e1000_clear_hw_cntrs_ich8lan;
- /* LED operations */
+ /* LED and other operations */
switch (mac->type) {
case e1000_ich8lan:
case e1000_ich9lan:
@@ -558,10 +678,11 @@
case e1000_pch2lan:
mac->rar_entry_count = E1000_PCH2_RAR_ENTRIES;
mac->ops.rar_set = e1000_rar_set_pch2lan;
+ /* fall-through */
+ case e1000_pch_lpt:
/* multicast address update for pch2 */
mac->ops.update_mc_addr_list =
e1000_update_mc_addr_list_pch2lan;
- /* fall-through */
case e1000_pchlan:
/* check management mode */
mac->ops.check_mng_mode = e1000_check_mng_mode_pchlan;
@@ -579,56 +700,386 @@
break;
}
-#if defined(NAHUM6_HW) && (defined(LTR_SUPPORT) || defined(OBFF_SUPPORT))
if (mac->type == e1000_pch_lpt) {
+ mac->rar_entry_count = E1000_PCH_LPT_RAR_ENTRIES;
+ mac->ops.rar_set = e1000_rar_set_pch_lpt;
+ mac->ops.setup_physical_interface = e1000_setup_copper_link_pch_lpt;
+ mac->ops.set_obff_timer = e1000_set_obff_timer_pch_lpt;
}
-#endif /* NAHUM6_HW && (LTR_SUPPORT || OBFF_SUPPORT) */
/* Enable PCS Lock-loss workaround for ICH8 */
if (mac->type == e1000_ich8lan)
e1000_set_kmrn_lock_loss_workaround_ich8lan(hw, TRUE);
- /* Gate automatic PHY configuration by hardware on managed 82579 */
- if ((mac->type == e1000_pch2lan) &&
- (E1000_READ_REG(hw, E1000_FWSM) & E1000_ICH_FWSM_FW_VALID))
- e1000_gate_hw_phy_config_ich8lan(hw, TRUE);
-
return E1000_SUCCESS;
}
/**
+ * __e1000_access_emi_reg_locked - Read/write EMI register
+ * @hw: pointer to the HW structure
+ * @addr: EMI address to program
+ * @data: pointer to value to read/write from/to the EMI address
+ * @read: boolean flag to indicate read or write
+ *
+ * This helper function assumes the SW/FW/HW Semaphore is already acquired.
+ **/
+static s32 __e1000_access_emi_reg_locked(struct e1000_hw *hw, u16 address,
+ u16 *data, bool read)
+{
+ s32 ret_val;
+
+ DEBUGFUNC("__e1000_access_emi_reg_locked");
+
+ ret_val = hw->phy.ops.write_reg_locked(hw, I82579_EMI_ADDR, address);
+ if (ret_val)
+ return ret_val;
+
+ if (read)
+ ret_val = hw->phy.ops.read_reg_locked(hw, I82579_EMI_DATA,
+ data);
+ else
+ ret_val = hw->phy.ops.write_reg_locked(hw, I82579_EMI_DATA,
+ *data);
+
+ return ret_val;
+}
+
+/**
+ * e1000_read_emi_reg_locked - Read Extended Management Interface register
+ * @hw: pointer to the HW structure
+ * @addr: EMI address to program
+ * @data: value to be read from the EMI address
+ *
+ * Assumes the SW/FW/HW Semaphore is already acquired.
+ **/
+s32 e1000_read_emi_reg_locked(struct e1000_hw *hw, u16 addr, u16 *data)
+{
+ DEBUGFUNC("e1000_read_emi_reg_locked");
+
+ return __e1000_access_emi_reg_locked(hw, addr, data, TRUE);
+}
+
+/**
+ * e1000_write_emi_reg_locked - Write Extended Management Interface register
+ * @hw: pointer to the HW structure
+ * @addr: EMI address to program
+ * @data: value to be written to the EMI address
+ *
+ * Assumes the SW/FW/HW Semaphore is already acquired.
+ **/
+static s32 e1000_write_emi_reg_locked(struct e1000_hw *hw, u16 addr, u16 data)
+{
+ DEBUGFUNC("e1000_read_emi_reg_locked");
+
+ return __e1000_access_emi_reg_locked(hw, addr, &data, FALSE);
+}
+
+/**
* e1000_set_eee_pchlan - Enable/disable EEE support
* @hw: pointer to the HW structure
*
- * Enable/disable EEE based on setting in dev_spec structure. The bits in
- * the LPI Control register will remain set only if/when link is up.
+ * Enable/disable EEE based on setting in dev_spec structure, the duplex of
+ * the link and the EEE capabilities of the link partner. The LPI Control
+ * register bits will remain set only if/when link is up.
**/
static s32 e1000_set_eee_pchlan(struct e1000_hw *hw)
{
struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
- s32 ret_val = E1000_SUCCESS;
- u16 phy_reg;
+ s32 ret_val;
+ u16 lpi_ctrl;
DEBUGFUNC("e1000_set_eee_pchlan");
- if (hw->phy.type != e1000_phy_82579)
- goto out;
+ if ((hw->phy.type != e1000_phy_82579) &&
+ (hw->phy.type != e1000_phy_i217))
+ return E1000_SUCCESS;
- ret_val = hw->phy.ops.read_reg(hw, I82579_LPI_CTRL, &phy_reg);
+ ret_val = hw->phy.ops.acquire(hw);
if (ret_val)
- goto out;
+ return ret_val;
- if (dev_spec->eee_disable)
- phy_reg &= ~I82579_LPI_CTRL_ENABLE_MASK;
- else
- phy_reg |= I82579_LPI_CTRL_ENABLE_MASK;
+ ret_val = hw->phy.ops.read_reg_locked(hw, I82579_LPI_CTRL, &lpi_ctrl);
+ if (ret_val)
+ goto release;
- ret_val = hw->phy.ops.write_reg(hw, I82579_LPI_CTRL, phy_reg);
-out:
+ /* Clear bits that enable EEE in various speeds */
+ lpi_ctrl &= ~I82579_LPI_CTRL_ENABLE_MASK;
+
+ /* Enable EEE if not disabled by user */
+ if (!dev_spec->eee_disable) {
+ u16 lpa, pcs_status, data;
+
+ /* Save off link partner's EEE ability */
+ switch (hw->phy.type) {
+ case e1000_phy_82579:
+ lpa = I82579_EEE_LP_ABILITY;
+ pcs_status = I82579_EEE_PCS_STATUS;
+ break;
+ case e1000_phy_i217:
+ lpa = I217_EEE_LP_ABILITY;
+ pcs_status = I217_EEE_PCS_STATUS;
+ break;
+ default:
+ ret_val = -E1000_ERR_PHY;
+ goto release;
+ }
+ ret_val = e1000_read_emi_reg_locked(hw, lpa,
+ &dev_spec->eee_lp_ability);
+ if (ret_val)
+ goto release;
+
+ /* Enable EEE only for speeds in which the link partner is
+ * EEE capable.
+ */
+ if (dev_spec->eee_lp_ability & I82579_EEE_1000_SUPPORTED)
+ lpi_ctrl |= I82579_LPI_CTRL_1000_ENABLE;
+
+ if (dev_spec->eee_lp_ability & I82579_EEE_100_SUPPORTED) {
+ hw->phy.ops.read_reg_locked(hw, PHY_LP_ABILITY, &data);
+ if (data & NWAY_LPAR_100TX_FD_CAPS)
+ lpi_ctrl |= I82579_LPI_CTRL_100_ENABLE;
+ else
+ /* EEE is not supported in 100Half, so ignore
+ * partner's EEE in 100 ability if full-duplex
+ * is not advertised.
+ */
+ dev_spec->eee_lp_ability &=
+ ~I82579_EEE_100_SUPPORTED;
+ }
+
+ /* R/Clr IEEE MMD 3.1 bits 11:10 - Tx/Rx LPI Received */
+ ret_val = e1000_read_emi_reg_locked(hw, pcs_status, &data);
+ if (ret_val)
+ goto release;
+ }
+
+ ret_val = hw->phy.ops.write_reg_locked(hw, I82579_LPI_CTRL, lpi_ctrl);
+release:
+ hw->phy.ops.release(hw);
+
return ret_val;
}
/**
+ * e1000_k1_workaround_lpt_lp - K1 workaround on Lynxpoint-LP
+ * @hw: pointer to the HW structure
+ * @link: link up bool flag
+ *
+ * When K1 is enabled for 1Gbps, the MAC can miss 2 DMA completion indications
+ * preventing further DMA write requests. Workaround the issue by disabling
+ * the de-assertion of the clock request when in 1Gpbs mode.
+ **/
+static s32 e1000_k1_workaround_lpt_lp(struct e1000_hw *hw, bool link)
+{
+ u32 fextnvm6 = E1000_READ_REG(hw, E1000_FEXTNVM6);
+ s32 ret_val = E1000_SUCCESS;
+
+ if (link && (E1000_READ_REG(hw, E1000_STATUS) &
+ E1000_STATUS_SPEED_1000)) {
+ u16 kmrn_reg;
+
+ ret_val = hw->phy.ops.acquire(hw);
+ if (ret_val)
+ return ret_val;
+
+ ret_val =
+ e1000_read_kmrn_reg_locked(hw, E1000_KMRNCTRLSTA_K1_CONFIG,
+ &kmrn_reg);
+ if (ret_val)
+ goto release;
+
+ ret_val =
+ e1000_write_kmrn_reg_locked(hw,
+ E1000_KMRNCTRLSTA_K1_CONFIG,
+ kmrn_reg &
+ ~E1000_KMRNCTRLSTA_K1_ENABLE);
+ if (ret_val)
+ goto release;
+
+ usec_delay(10);
+
+ E1000_WRITE_REG(hw, E1000_FEXTNVM6,
+ fextnvm6 | E1000_FEXTNVM6_REQ_PLL_CLK);
+
+ ret_val =
+ e1000_write_kmrn_reg_locked(hw,
+ E1000_KMRNCTRLSTA_K1_CONFIG,
+ kmrn_reg);
+release:
+ hw->phy.ops.release(hw);
+ } else {
+ /* clear FEXTNVM6 bit 8 on link down or 10/100 */
+ E1000_WRITE_REG(hw, E1000_FEXTNVM6,
+ fextnvm6 & ~E1000_FEXTNVM6_REQ_PLL_CLK);
+ }
+
+ return ret_val;
+}
+
+static u64 e1000_ltr2ns(u16 ltr)
+{
+ u32 value, scale;
+
+ /* Determine the latency in nsec based on the LTR value & scale */
+ value = ltr & E1000_LTRV_VALUE_MASK;
+ scale = (ltr & E1000_LTRV_SCALE_MASK) >> E1000_LTRV_SCALE_SHIFT;
+
+ return value * (1 << (scale * E1000_LTRV_SCALE_FACTOR));
+}
+
+/**
+ * e1000_platform_pm_pch_lpt - Set platform power management values
+ * @hw: pointer to the HW structure
+ * @link: bool indicating link status
+ *
+ * Set the Latency Tolerance Reporting (LTR) values for the "PCIe-like"
+ * GbE MAC in the Lynx Point PCH based on Rx buffer size and link speed
+ * when link is up (which must not exceed the maximum latency supported
+ * by the platform), otherwise specify there is no LTR requirement.
+ * Unlike TRUE-PCIe devices which set the LTR maximum snoop/no-snoop
+ * latencies in the LTR Extended Capability Structure in the PCIe Extended
+ * Capability register set, on this device LTR is set by writing the
+ * equivalent snoop/no-snoop latencies in the LTRV register in the MAC and
+ * set the SEND bit to send an Intel On-chip System Fabric sideband (IOSF-SB)
+ * message to the PMC.
+ *
+ * Use the LTR value to calculate the Optimized Buffer Flush/Fill (OBFF)
+ * high-water mark.
+ **/
+static s32 e1000_platform_pm_pch_lpt(struct e1000_hw *hw, bool link)
+{
+ u32 reg = link << (E1000_LTRV_REQ_SHIFT + E1000_LTRV_NOSNOOP_SHIFT) |
+ link << E1000_LTRV_REQ_SHIFT | E1000_LTRV_SEND;
+ u16 lat_enc = 0; /* latency encoded */
+ s32 obff_hwm = 0;
+
+ DEBUGFUNC("e1000_platform_pm_pch_lpt");
+
+ if (link) {
+ u16 speed, duplex, scale = 0;
+ u16 max_snoop, max_nosnoop;
+ u16 max_ltr_enc; /* max LTR latency encoded */
+ s64 lat_ns; /* latency (ns) */
+ s64 value;
+ u32 rxa;
+
+ if (!hw->mac.max_frame_size) {
+ DEBUGOUT("max_frame_size not set.\n");
+ return -E1000_ERR_CONFIG;
+ }
+
+ hw->mac.ops.get_link_up_info(hw, &speed, &duplex);
+ if (!speed) {
+ DEBUGOUT("Speed not set.\n");
+ return -E1000_ERR_CONFIG;
+ }
+
+ /* Rx Packet Buffer Allocation size (KB) */
+ rxa = E1000_READ_REG(hw, E1000_PBA) & E1000_PBA_RXA_MASK;
+
+ /* Determine the maximum latency tolerated by the device.
+ *
+ * Per the PCIe spec, the tolerated latencies are encoded as
+ * a 3-bit encoded scale (only 0-5 are valid) multiplied by
+ * a 10-bit value (0-1023) to provide a range from 1 ns to
+ * 2^25*(2^10-1) ns. The scale is encoded as 0=2^0ns,
+ * 1=2^5ns, 2=2^10ns,...5=2^25ns.
+ */
+ lat_ns = ((s64)rxa * 1024 -
+ (2 * (s64)hw->mac.max_frame_size)) * 8 * 1000;
+ if (lat_ns < 0)
+ lat_ns = 0;
+ else
+ lat_ns /= speed;
+
+ value = lat_ns;
+ while (value > E1000_LTRV_VALUE_MASK) {
+ scale++;
+ value = E1000_DIVIDE_ROUND_UP(value, (1 << 5));
+ }
+ if (scale > E1000_LTRV_SCALE_MAX) {
+ DEBUGOUT1("Invalid LTR latency scale %d\n", scale);
+ return -E1000_ERR_CONFIG;
+ }
+ lat_enc = (u16)((scale << E1000_LTRV_SCALE_SHIFT) | value);
+
+ /* Determine the maximum latency tolerated by the platform */
+ e1000_read_pci_cfg(hw, E1000_PCI_LTR_CAP_LPT, &max_snoop);
+ e1000_read_pci_cfg(hw, E1000_PCI_LTR_CAP_LPT + 2, &max_nosnoop);
+ max_ltr_enc = E1000_MAX(max_snoop, max_nosnoop);
+
+ if (lat_enc > max_ltr_enc) {
+ lat_enc = max_ltr_enc;
+ lat_ns = e1000_ltr2ns(max_ltr_enc);
+ }
+
+ if (lat_ns) {
+ lat_ns *= speed * 1000;
+ lat_ns /= 8;
+ lat_ns /= 1000000000;
+ obff_hwm = (s32)(rxa - lat_ns);
+ }
+
+ if ((obff_hwm < 0) || (obff_hwm > E1000_SVT_OFF_HWM_MASK)) {
+ DEBUGOUT1("Invalid high water mark %d\n", obff_hwm);
+ return -E1000_ERR_CONFIG;
+ }
+ }
+
+ /* Set Snoop and No-Snoop latencies the same */
+ reg |= lat_enc | (lat_enc << E1000_LTRV_NOSNOOP_SHIFT);
+ E1000_WRITE_REG(hw, E1000_LTRV, reg);
+
+ /* Set OBFF high water mark */
+ reg = E1000_READ_REG(hw, E1000_SVT) & ~E1000_SVT_OFF_HWM_MASK;
+ reg |= obff_hwm;
+ E1000_WRITE_REG(hw, E1000_SVT, reg);
+
+ /* Enable OBFF */
+ reg = E1000_READ_REG(hw, E1000_SVCR);
+ reg |= E1000_SVCR_OFF_EN;
+ /* Always unblock interrupts to the CPU even when the system is
+ * in OBFF mode. This ensures that small round-robin traffic
+ * (like ping) does not get dropped or experience long latency.
+ */
+ reg |= E1000_SVCR_OFF_MASKINT;
+ E1000_WRITE_REG(hw, E1000_SVCR, reg);
+
+ return E1000_SUCCESS;
+}
+
+/**
+ * e1000_set_obff_timer_pch_lpt - Update Optimized Buffer Flush/Fill timer
+ * @hw: pointer to the HW structure
+ * @itr: interrupt throttling rate
+ *
+ * Configure OBFF with the updated interrupt rate.
+ **/
+static s32 e1000_set_obff_timer_pch_lpt(struct e1000_hw *hw, u32 itr)
+{
+ u32 svcr;
+ s32 timer;
+
+ DEBUGFUNC("e1000_set_obff_timer_pch_lpt");
+
+ /* Convert ITR value into microseconds for OBFF timer */
+ timer = itr & E1000_ITR_MASK;
+ timer = (timer * E1000_ITR_MULT) / 1000;
+
+ if ((timer < 0) || (timer > E1000_ITR_MASK)) {
+ DEBUGOUT1("Invalid OBFF timer %d\n", timer);
+ return -E1000_ERR_CONFIG;
+ }
+
+ svcr = E1000_READ_REG(hw, E1000_SVCR);
+ svcr &= ~E1000_SVCR_OFF_TIMER_MASK;
+ svcr |= timer << E1000_SVCR_OFF_TIMER_SHIFT;
+ E1000_WRITE_REG(hw, E1000_SVCR, svcr);
+
+ return E1000_SUCCESS;
+}
+
+/**
* e1000_check_for_copper_link_ich8lan - Check for link (Copper)
* @hw: pointer to the HW structure
*
@@ -645,39 +1096,77 @@
DEBUGFUNC("e1000_check_for_copper_link_ich8lan");
- /*
- * We only want to go out to the PHY registers to see if Auto-Neg
+ /* We only want to go out to the PHY registers to see if Auto-Neg
* has completed and/or if our link status has changed. The
* get_link_status flag is set upon receiving a Link Status
* Change or Rx Sequence Error interrupt.
*/
- if (!mac->get_link_status) {
- ret_val = E1000_SUCCESS;
- goto out;
- }
+ if (!mac->get_link_status)
+ return E1000_SUCCESS;
- /*
- * First we want to see if the MII Status Register reports
+ /* First we want to see if the MII Status Register reports
* link. If so, then we want to get the current speed/duplex
* of the PHY.
*/
ret_val = e1000_phy_has_link_generic(hw, 1, 0, &link);
if (ret_val)
- goto out;
+ return ret_val;
if (hw->mac.type == e1000_pchlan) {
ret_val = e1000_k1_gig_workaround_hv(hw, link);
if (ret_val)
- goto out;
+ return ret_val;
}
-#if defined(NAHUM6_HW) && (defined(LTR_SUPPORT) || defined(OBFF_SUPPORT))
+ /* When connected at 10Mbps half-duplex, 82579 parts are excessively
+ * aggressive resulting in many collisions. To avoid this, increase
+ * the IPG and reduce Rx latency in the PHY.
+ */
+ if ((hw->mac.type == e1000_pch2lan) && link) {
+ u32 reg;
+ reg = E1000_READ_REG(hw, E1000_STATUS);
+ if (!(reg & (E1000_STATUS_FD | E1000_STATUS_SPEED_MASK))) {
+ reg = E1000_READ_REG(hw, E1000_TIPG);
+ reg &= ~E1000_TIPG_IPGT_MASK;
+ reg |= 0xFF;
+ E1000_WRITE_REG(hw, E1000_TIPG, reg);
+
+ /* Reduce Rx latency in analog PHY */
+ ret_val = hw->phy.ops.acquire(hw);
+ if (ret_val)
+ return ret_val;
+
+ ret_val = e1000_write_emi_reg_locked(hw, I82579_RX_CONFIG, 0);
+
+ hw->phy.ops.release(hw);
+
+ if (ret_val)
+ return ret_val;
+ }
+ }
+
+ /* Work-around I218 hang issue */
+ if ((hw->device_id == E1000_DEV_ID_PCH_LPTLP_I218_LM) ||
+ (hw->device_id == E1000_DEV_ID_PCH_LPTLP_I218_V)) {
+ ret_val = e1000_k1_workaround_lpt_lp(hw, link);
+ if (ret_val)
+ return ret_val;
+ }
+
if (hw->mac.type == e1000_pch_lpt) {
+ /* Set platform power management values for Latency Tolerance
+ * Reporting (LTR) and Optimized Buffer Flush/Fill (OBFF).
+ */
+ ret_val = e1000_platform_pm_pch_lpt(hw, link);
+ if (ret_val)
+ return ret_val;
}
-#endif /* NAHUM6_HW && (LTR_SUPPORT || OBFF_SUPPORT) */
+ /* Clear link partner's EEE ability */
+ hw->dev_spec.ich8lan.eee_lp_ability = 0;
+
if (!link)
- goto out; /* No link detected */
+ return E1000_SUCCESS; /* No link detected */
mac->get_link_status = FALSE;
@@ -685,17 +1174,16 @@
case e1000_pch2lan:
ret_val = e1000_k1_workaround_lv(hw);
if (ret_val)
- goto out;
+ return ret_val;
/* fall-thru */
case e1000_pchlan:
if (hw->phy.type == e1000_phy_82578) {
ret_val = e1000_link_stall_workaround_hv(hw);
if (ret_val)
- goto out;
+ return ret_val;
}
- /*
- * Workaround for PCHx parts in half-duplex:
+ /* Workaround for PCHx parts in half-duplex:
* Set the number of preambles removed from the packet
* when it is passed from the PHY to the MAC to prevent
* the MAC from misinterpreting the packet type.
@@ -713,8 +1201,7 @@
break;
}
- /*
- * Check if there was DownShift, must be checked
+ /* Check if there was DownShift, must be checked
* immediately after link-up
*/
e1000_check_downshift_generic(hw);
@@ -722,26 +1209,21 @@
/* Enable/Disable EEE after link up */
ret_val = e1000_set_eee_pchlan(hw);
if (ret_val)
- goto out;
+ return ret_val;
- /*
- * If we are forcing speed/duplex, then we simply return since
+ /* If we are forcing speed/duplex, then we simply return since
* we have already determined whether we have link or not.
*/
- if (!mac->autoneg) {
- ret_val = -E1000_ERR_CONFIG;
- goto out;
- }
+ if (!mac->autoneg)
+ return -E1000_ERR_CONFIG;
- /*
- * Auto-Neg is enabled. Auto Speed Detection takes care
+ /* Auto-Neg is enabled. Auto Speed Detection takes care
* of MAC speed/duplex configuration. So we only need to
* configure Collision Distance in the MAC.
*/
- hw->mac.ops.config_collision_dist(hw);
+ mac->ops.config_collision_dist(hw);
- /*
- * Configure Flow Control now that Auto-Neg has completed.
+ /* Configure Flow Control now that Auto-Neg has completed.
* First, we need to restore the desired flow control
* settings because we may have had to re-autoneg with a
* different link partner.
@@ -750,7 +1232,6 @@
if (ret_val)
DEBUGOUT("Error configuring flow control\n");
-out:
return ret_val;
}
@@ -774,6 +1255,7 @@
break;
case e1000_pchlan:
case e1000_pch2lan:
+ case e1000_pch_lpt:
hw->phy.ops.init_params = e1000_init_phy_params_pchlan;
break;
default:
@@ -957,8 +1439,7 @@
DEBUGFUNC("e1000_rar_set_pch2lan");
- /*
- * HW expects these in little endian so we reverse the byte order
+ /* HW expects these in little endian so we reverse the byte order
* from network order (big endian) to little endian
*/
rar_low = ((u32) addr[0] |
@@ -980,11 +1461,19 @@
}
if (index < hw->mac.rar_entry_count) {
+ s32 ret_val;
+
+ ret_val = e1000_acquire_swflag_ich8lan(hw);
+ if (ret_val)
+ goto out;
+
E1000_WRITE_REG(hw, E1000_SHRAL(index - 1), rar_low);
E1000_WRITE_FLUSH(hw);
E1000_WRITE_REG(hw, E1000_SHRAH(index - 1), rar_high);
E1000_WRITE_FLUSH(hw);
+ e1000_release_swflag_ich8lan(hw);
+
/* verify the register updates */
if ((E1000_READ_REG(hw, E1000_SHRAL(index - 1)) == rar_low) &&
(E1000_READ_REG(hw, E1000_SHRAH(index - 1)) == rar_high))
@@ -994,10 +1483,89 @@
(index - 1), E1000_READ_REG(hw, E1000_FWSM));
}
+out:
DEBUGOUT1("Failed to write receive address at index %d\n", index);
}
/**
+ * e1000_rar_set_pch_lpt - Set receive address registers
+ * @hw: pointer to the HW structure
+ * @addr: pointer to the receive address
+ * @index: receive address array register
+ *
+ * Sets the receive address register array at index to the address passed
+ * in by addr. For LPT, RAR[0] is the base address register that is to
+ * contain the MAC address. SHRA[0-10] are the shared receive address
+ * registers that are shared between the Host and manageability engine (ME).
+ **/
+static void e1000_rar_set_pch_lpt(struct e1000_hw *hw, u8 *addr, u32 index)
+{
+ u32 rar_low, rar_high;
+ u32 wlock_mac;
+
+ DEBUGFUNC("e1000_rar_set_pch_lpt");
+
+ /* HW expects these in little endian so we reverse the byte order
+ * from network order (big endian) to little endian
+ */
+ rar_low = ((u32) addr[0] | ((u32) addr[1] << 8) |
+ ((u32) addr[2] << 16) | ((u32) addr[3] << 24));
+
+ rar_high = ((u32) addr[4] | ((u32) addr[5] << 8));
+
+ /* If MAC address zero, no need to set the AV bit */
+ if (rar_low || rar_high)
+ rar_high |= E1000_RAH_AV;
+
+ if (index == 0) {
+ E1000_WRITE_REG(hw, E1000_RAL(index), rar_low);
+ E1000_WRITE_FLUSH(hw);
+ E1000_WRITE_REG(hw, E1000_RAH(index), rar_high);
+ E1000_WRITE_FLUSH(hw);
+ return;
+ }
+
+ /* The manageability engine (ME) can lock certain SHRAR registers that
+ * it is using - those registers are unavailable for use.
+ */
+ if (index < hw->mac.rar_entry_count) {
+ wlock_mac = E1000_READ_REG(hw, E1000_FWSM) &
+ E1000_FWSM_WLOCK_MAC_MASK;
+ wlock_mac >>= E1000_FWSM_WLOCK_MAC_SHIFT;
+
+ /* Check if all SHRAR registers are locked */
+ if (wlock_mac == 1)
+ goto out;
+
+ if ((wlock_mac == 0) || (index <= wlock_mac)) {
+ s32 ret_val;
+
+ ret_val = e1000_acquire_swflag_ich8lan(hw);
+
+ if (ret_val)
+ goto out;
+
+ E1000_WRITE_REG(hw, E1000_SHRAL_PCH_LPT(index - 1),
+ rar_low);
+ E1000_WRITE_FLUSH(hw);
+ E1000_WRITE_REG(hw, E1000_SHRAH_PCH_LPT(index - 1),
+ rar_high);
+ E1000_WRITE_FLUSH(hw);
+
+ e1000_release_swflag_ich8lan(hw);
+
+ /* verify the register updates */
+ if ((E1000_READ_REG(hw, E1000_SHRAL_PCH_LPT(index - 1)) == rar_low) &&
+ (E1000_READ_REG(hw, E1000_SHRAH_PCH_LPT(index - 1)) == rar_high))
+ return;
+ }
+ }
+
+out:
+ DEBUGOUT1("Failed to write receive address at index %d\n", index);
+}
+
+/**
* e1000_update_mc_addr_list_pch2lan - Update Multicast addresses
* @hw: pointer to the HW structure
* @mc_addr_list: array of multicast addresses to program
@@ -1072,21 +1640,34 @@
{
u16 phy_data;
u32 strap = E1000_READ_REG(hw, E1000_STRAP);
- s32 ret_val = E1000_SUCCESS;
+ u32 freq = (strap & E1000_STRAP_SMT_FREQ_MASK) >>
+ E1000_STRAP_SMT_FREQ_SHIFT;
+ s32 ret_val;
strap &= E1000_STRAP_SMBUS_ADDRESS_MASK;
ret_val = e1000_read_phy_reg_hv_locked(hw, HV_SMB_ADDR, &phy_data);
if (ret_val)
- goto out;
+ return ret_val;
phy_data &= ~HV_SMB_ADDR_MASK;
phy_data |= (strap >> E1000_STRAP_SMBUS_ADDRESS_SHIFT);
phy_data |= HV_SMB_ADDR_PEC_EN | HV_SMB_ADDR_VALID;
- ret_val = e1000_write_phy_reg_hv_locked(hw, HV_SMB_ADDR, phy_data);
-out:
- return ret_val;
+ if (hw->phy.type == e1000_phy_i217) {
+ /* Restore SMBus frequency */
+ if (freq--) {
+ phy_data &= ~HV_SMB_ADDR_FREQ_MASK;
+ phy_data |= (freq & (1 << 0)) <<
+ HV_SMB_ADDR_FREQ_LOW_SHIFT;
+ phy_data |= (freq & (1 << 1)) <<
+ (HV_SMB_ADDR_FREQ_HIGH_SHIFT - 1);
+ } else {
+ DEBUGOUT("Unsupported SMB frequency in PHY\n");
+ }
+ }
+
+ return e1000_write_phy_reg_hv_locked(hw, HV_SMB_ADDR, phy_data);
}
/**
@@ -1105,8 +1686,7 @@
DEBUGFUNC("e1000_sw_lcd_config_ich8lan");
- /*
- * Initialize the PHY from the NVM on ICH platforms. This
+ /* Initialize the PHY from the NVM on ICH platforms. This
* is needed due to an issue where the NVM configuration is
* not properly autoloaded after power transitions.
* Therefore, after each PHY reset, we will load the
@@ -1125,6 +1705,7 @@
/* Fall-thru */
case e1000_pchlan:
case e1000_pch2lan:
+ case e1000_pch_lpt:
sw_cfg_mask = E1000_FEXTNVM_SW_CONFIG_ICH8M;
break;
default:
@@ -1137,32 +1718,29 @@
data = E1000_READ_REG(hw, E1000_FEXTNVM);
if (!(data & sw_cfg_mask))
- goto out;
+ goto release;
- /*
- * Make sure HW does not configure LCD from PHY
+ /* Make sure HW does not configure LCD from PHY
* extended configuration before SW configuration
*/
data = E1000_READ_REG(hw, E1000_EXTCNF_CTRL);
- if (!(hw->mac.type == e1000_pch2lan)) {
- if (data & E1000_EXTCNF_CTRL_LCD_WRITE_ENABLE)
- goto out;
- }
+ if ((hw->mac.type < e1000_pch2lan) &&
+ (data & E1000_EXTCNF_CTRL_LCD_WRITE_ENABLE))
+ goto release;
cnf_size = E1000_READ_REG(hw, E1000_EXTCNF_SIZE);
cnf_size &= E1000_EXTCNF_SIZE_EXT_PCIE_LENGTH_MASK;
cnf_size >>= E1000_EXTCNF_SIZE_EXT_PCIE_LENGTH_SHIFT;
if (!cnf_size)
- goto out;
+ goto release;
cnf_base_addr = data & E1000_EXTCNF_CTRL_EXT_CNF_POINTER_MASK;
cnf_base_addr >>= E1000_EXTCNF_CTRL_EXT_CNF_POINTER_SHIFT;
- if ((!(data & E1000_EXTCNF_CTRL_OEM_WRITE_ENABLE) &&
- (hw->mac.type == e1000_pchlan)) ||
- (hw->mac.type == e1000_pch2lan)) {
- /*
- * HW configures the SMBus address and LEDs when the
+ if (((hw->mac.type == e1000_pchlan) &&
+ !(data & E1000_EXTCNF_CTRL_OEM_WRITE_ENABLE)) ||
+ (hw->mac.type > e1000_pchlan)) {
+ /* HW configures the SMBus address and LEDs when the
* OEM and LCD Write Enable bits are set in the NVM.
* When both NVM bits are cleared, SW will configure
* them instead.
@@ -1169,13 +1747,13 @@
*/
ret_val = e1000_write_smbus_addr(hw);
if (ret_val)
- goto out;
+ goto release;
data = E1000_READ_REG(hw, E1000_LEDCTL);
ret_val = e1000_write_phy_reg_hv_locked(hw, HV_LED_CONFIG,
(u16)data);
if (ret_val)
- goto out;
+ goto release;
}
/* Configure LCD from extended configuration region. */
@@ -1187,12 +1765,12 @@
ret_val = hw->nvm.ops.read(hw, (word_addr + i * 2), 1,
®_data);
if (ret_val)
- goto out;
+ goto release;
ret_val = hw->nvm.ops.read(hw, (word_addr + i * 2 + 1),
1, ®_addr);
if (ret_val)
- goto out;
+ goto release;
/* Save off the PHY page for future writes. */
if (reg_addr == IGP01E1000_PHY_PAGE_SELECT) {
@@ -1206,10 +1784,10 @@
ret_val = phy->ops.write_reg_locked(hw, (u32)reg_addr,
reg_data);
if (ret_val)
- goto out;
+ goto release;
}
-out:
+release:
hw->phy.ops.release(hw);
return ret_val;
}
@@ -1233,12 +1811,12 @@
DEBUGFUNC("e1000_k1_gig_workaround_hv");
if (hw->mac.type != e1000_pchlan)
- goto out;
+ return E1000_SUCCESS;
/* Wrap the whole flow with the sw flag */
ret_val = hw->phy.ops.acquire(hw);
if (ret_val)
- goto out;
+ return ret_val;
/* Disable K1 when link is 1Gbps, otherwise use the NVM setting */
if (link) {
@@ -1292,7 +1870,7 @@
release:
hw->phy.ops.release(hw);
-out:
+
return ret_val;
}
@@ -1308,7 +1886,7 @@
**/
s32 e1000_configure_k1_ich8lan(struct e1000_hw *hw, bool k1_enable)
{
- s32 ret_val = E1000_SUCCESS;
+ s32 ret_val;
u32 ctrl_reg = 0;
u32 ctrl_ext = 0;
u32 reg = 0;
@@ -1319,7 +1897,7 @@
ret_val = e1000_read_kmrn_reg_locked(hw, E1000_KMRNCTRLSTA_K1_CONFIG,
&kmrn_reg);
if (ret_val)
- goto out;
+ return ret_val;
if (k1_enable)
kmrn_reg |= E1000_KMRNCTRLSTA_K1_ENABLE;
@@ -1329,7 +1907,7 @@
ret_val = e1000_write_kmrn_reg_locked(hw, E1000_KMRNCTRLSTA_K1_CONFIG,
kmrn_reg);
if (ret_val)
- goto out;
+ return ret_val;
usec_delay(20);
ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
@@ -1347,8 +1925,7 @@
E1000_WRITE_FLUSH(hw);
usec_delay(20);
-out:
- return ret_val;
+ return E1000_SUCCESS;
}
/**
@@ -1368,7 +1945,7 @@
DEBUGFUNC("e1000_oem_bits_config_ich8lan");
- if ((hw->mac.type != e1000_pch2lan) && (hw->mac.type != e1000_pchlan))
+ if (hw->mac.type < e1000_pchlan)
return ret_val;
ret_val = hw->phy.ops.acquire(hw);
@@ -1375,21 +1952,21 @@
if (ret_val)
return ret_val;
- if (!(hw->mac.type == e1000_pch2lan)) {
+ if (hw->mac.type == e1000_pchlan) {
mac_reg = E1000_READ_REG(hw, E1000_EXTCNF_CTRL);
if (mac_reg & E1000_EXTCNF_CTRL_OEM_WRITE_ENABLE)
- goto out;
+ goto release;
}
mac_reg = E1000_READ_REG(hw, E1000_FEXTNVM);
if (!(mac_reg & E1000_FEXTNVM_SW_CONFIG_ICH8M))
- goto out;
+ goto release;
mac_reg = E1000_READ_REG(hw, E1000_PHY_CTRL);
ret_val = hw->phy.ops.read_reg_locked(hw, HV_OEM_BITS, &oem_reg);
if (ret_val)
- goto out;
+ goto release;
oem_reg &= ~(HV_OEM_BITS_GBE_DIS | HV_OEM_BITS_LPLU);
@@ -1399,10 +1976,6 @@
if (mac_reg & E1000_PHY_CTRL_D0A_LPLU)
oem_reg |= HV_OEM_BITS_LPLU;
-
- /* Set Restart auto-neg to activate the bits */
- if (!hw->phy.ops.check_reset_block(hw))
- oem_reg |= HV_OEM_BITS_RESTART_AN;
} else {
if (mac_reg & (E1000_PHY_CTRL_GBE_DISABLE |
E1000_PHY_CTRL_NOND0A_GBE_DISABLE))
@@ -1413,9 +1986,14 @@
oem_reg |= HV_OEM_BITS_LPLU;
}
+ /* Set Restart auto-neg to activate the bits */
+ if ((d0_state || (hw->mac.type != e1000_pchlan)) &&
+ !hw->phy.ops.check_reset_block(hw))
+ oem_reg |= HV_OEM_BITS_RESTART_AN;
+
ret_val = hw->phy.ops.write_reg_locked(hw, HV_OEM_BITS, oem_reg);
-out:
+release:
hw->phy.ops.release(hw);
return ret_val;
@@ -1456,13 +2034,13 @@
DEBUGFUNC("e1000_hv_phy_workarounds_ich8lan");
if (hw->mac.type != e1000_pchlan)
- goto out;
+ return E1000_SUCCESS;
/* Set MDIO slow mode before any other MDIO access */
if (hw->phy.type == e1000_phy_82577) {
ret_val = e1000_set_mdio_slow_mode_hv(hw);
if (ret_val)
- goto out;
+ return ret_val;
}
if (((hw->phy.type == e1000_phy_82577) &&
@@ -1471,18 +2049,17 @@
/* Disable generation of early preamble */
ret_val = hw->phy.ops.write_reg(hw, PHY_REG(769, 25), 0x4431);
if (ret_val)
- goto out;
+ return ret_val;
/* Preamble tuning for SSC */
ret_val = hw->phy.ops.write_reg(hw, HV_KMRN_FIFO_CTRLSTA,
0xA204);
if (ret_val)
- goto out;
+ return ret_val;
}
if (hw->phy.type == e1000_phy_82578) {
- /*
- * Return registers to default by doing a soft reset then
+ /* Return registers to default by doing a soft reset then
* writing 0x3140 to the control register.
*/
if (hw->phy.revision < 2) {
@@ -1495,34 +2072,38 @@
/* Select page 0 */
ret_val = hw->phy.ops.acquire(hw);
if (ret_val)
- goto out;
+ return ret_val;
hw->phy.addr = 1;
ret_val = e1000_write_phy_reg_mdic(hw, IGP01E1000_PHY_PAGE_SELECT, 0);
hw->phy.ops.release(hw);
if (ret_val)
- goto out;
+ return ret_val;
- /*
- * Configure the K1 Si workaround during phy reset assuming there is
+ /* Configure the K1 Si workaround during phy reset assuming there is
* link so that it disables K1 if link is in 1Gbps.
*/
ret_val = e1000_k1_gig_workaround_hv(hw, TRUE);
if (ret_val)
- goto out;
+ return ret_val;
/* Workaround for link disconnects on a busy hub in half duplex */
ret_val = hw->phy.ops.acquire(hw);
if (ret_val)
- goto out;
+ return ret_val;
ret_val = hw->phy.ops.read_reg_locked(hw, BM_PORT_GEN_CFG, &phy_data);
if (ret_val)
goto release;
ret_val = hw->phy.ops.write_reg_locked(hw, BM_PORT_GEN_CFG,
phy_data & 0x00FF);
+ if (ret_val)
+ goto release;
+
+ /* set MSE higher to enable link to stay up when noise is high */
+ ret_val = e1000_write_emi_reg_locked(hw, I82577_MSE_THRESHOLD, 0x0034);
release:
hw->phy.ops.release(hw);
-out:
+
return ret_val;
}
@@ -1600,8 +2181,8 @@
DEBUGFUNC("e1000_lv_jumbo_workaround_ich8lan");
- if (hw->mac.type != e1000_pch2lan)
- goto out;
+ if (hw->mac.type < e1000_pch2lan)
+ return E1000_SUCCESS;
/* disable Rx path while enabling/disabling workaround */
hw->phy.ops.read_reg(hw, PHY_REG(769, 20), &phy_reg);
@@ -1608,11 +2189,10 @@
ret_val = hw->phy.ops.write_reg(hw, PHY_REG(769, 20),
phy_reg | (1 << 14));
if (ret_val)
- goto out;
+ return ret_val;
if (enable) {
- /*
- * Write Rx addresses (rar_entry_count for RAL/H, +4 for
+ /* Write Rx addresses (rar_entry_count for RAL/H, +4 for
* SHRAL/H) and initial CRC values to the MAC
*/
for (i = 0; i < (hw->mac.rar_entry_count + 4); i++) {
@@ -1651,17 +2231,17 @@
E1000_KMRNCTRLSTA_CTRL_OFFSET,
&data);
if (ret_val)
- goto out;
+ return ret_val;
ret_val = e1000_write_kmrn_reg_generic(hw,
E1000_KMRNCTRLSTA_CTRL_OFFSET,
data | (1 << 0));
if (ret_val)
- goto out;
+ return ret_val;
ret_val = e1000_read_kmrn_reg_generic(hw,
E1000_KMRNCTRLSTA_HD_CTRL,
&data);
if (ret_val)
- goto out;
+ return ret_val;
data &= ~(0xF << 8);
data |= (0xB << 8);
ret_val = e1000_write_kmrn_reg_generic(hw,
@@ -1668,7 +2248,7 @@
E1000_KMRNCTRLSTA_HD_CTRL,
data);
if (ret_val)
- goto out;
+ return ret_val;
/* Enable jumbo frame workaround in the PHY */
hw->phy.ops.read_reg(hw, PHY_REG(769, 23), &data);
@@ -1676,26 +2256,26 @@
data |= (0x37 << 5);
ret_val = hw->phy.ops.write_reg(hw, PHY_REG(769, 23), data);
if (ret_val)
- goto out;
+ return ret_val;
hw->phy.ops.read_reg(hw, PHY_REG(769, 16), &data);
data &= ~(1 << 13);
ret_val = hw->phy.ops.write_reg(hw, PHY_REG(769, 16), data);
if (ret_val)
- goto out;
+ return ret_val;
hw->phy.ops.read_reg(hw, PHY_REG(776, 20), &data);
data &= ~(0x3FF << 2);
data |= (0x1A << 2);
ret_val = hw->phy.ops.write_reg(hw, PHY_REG(776, 20), data);
if (ret_val)
- goto out;
+ return ret_val;
ret_val = hw->phy.ops.write_reg(hw, PHY_REG(776, 23), 0xF100);
if (ret_val)
- goto out;
+ return ret_val;
hw->phy.ops.read_reg(hw, HV_PM_CTRL, &data);
ret_val = hw->phy.ops.write_reg(hw, HV_PM_CTRL, data |
(1 << 10));
if (ret_val)
- goto out;
+ return ret_val;
} else {
/* Write MAC register values back to h/w defaults */
mac_reg = E1000_READ_REG(hw, E1000_FFLT_DBG);
@@ -1710,17 +2290,17 @@
E1000_KMRNCTRLSTA_CTRL_OFFSET,
&data);
if (ret_val)
- goto out;
+ return ret_val;
ret_val = e1000_write_kmrn_reg_generic(hw,
E1000_KMRNCTRLSTA_CTRL_OFFSET,
data & ~(1 << 0));
if (ret_val)
- goto out;
+ return ret_val;
ret_val = e1000_read_kmrn_reg_generic(hw,
E1000_KMRNCTRLSTA_HD_CTRL,
&data);
if (ret_val)
- goto out;
+ return ret_val;
data &= ~(0xF << 8);
data |= (0xB << 8);
ret_val = e1000_write_kmrn_reg_generic(hw,
@@ -1727,7 +2307,7 @@
E1000_KMRNCTRLSTA_HD_CTRL,
data);
if (ret_val)
- goto out;
+ return ret_val;
/* Write PHY register values back to h/w defaults */
hw->phy.ops.read_reg(hw, PHY_REG(769, 23), &data);
@@ -1734,34 +2314,31 @@
data &= ~(0x7F << 5);
ret_val = hw->phy.ops.write_reg(hw, PHY_REG(769, 23), data);
if (ret_val)
- goto out;
+ return ret_val;
hw->phy.ops.read_reg(hw, PHY_REG(769, 16), &data);
data |= (1 << 13);
ret_val = hw->phy.ops.write_reg(hw, PHY_REG(769, 16), data);
if (ret_val)
- goto out;
+ return ret_val;
hw->phy.ops.read_reg(hw, PHY_REG(776, 20), &data);
data &= ~(0x3FF << 2);
data |= (0x8 << 2);
ret_val = hw->phy.ops.write_reg(hw, PHY_REG(776, 20), data);
if (ret_val)
- goto out;
+ return ret_val;
ret_val = hw->phy.ops.write_reg(hw, PHY_REG(776, 23), 0x7E00);
if (ret_val)
- goto out;
+ return ret_val;
hw->phy.ops.read_reg(hw, HV_PM_CTRL, &data);
ret_val = hw->phy.ops.write_reg(hw, HV_PM_CTRL, data &
~(1 << 10));
if (ret_val)
- goto out;
+ return ret_val;
}
/* re-enable Rx path after enabling/disabling workaround */
- ret_val = hw->phy.ops.write_reg(hw, PHY_REG(769, 20), phy_reg &
- ~(1 << 14));
-
-out:
- return ret_val;
+ return hw->phy.ops.write_reg(hw, PHY_REG(769, 20), phy_reg &
+ ~(1 << 14));
}
/**
@@ -1775,34 +2352,25 @@
DEBUGFUNC("e1000_lv_phy_workarounds_ich8lan");
if (hw->mac.type != e1000_pch2lan)
- goto out;
+ return E1000_SUCCESS;
/* Set MDIO slow mode before any other MDIO access */
ret_val = e1000_set_mdio_slow_mode_hv(hw);
+ if (ret_val)
+ return ret_val;
ret_val = hw->phy.ops.acquire(hw);
if (ret_val)
- goto out;
- ret_val = hw->phy.ops.write_reg_locked(hw, I82579_EMI_ADDR,
- I82579_MSE_THRESHOLD);
- if (ret_val)
- goto release;
+ return ret_val;
/* set MSE higher to enable link to stay up when noise is high */
- ret_val = hw->phy.ops.write_reg_locked(hw, I82579_EMI_DATA,
- 0x0034);
+ ret_val = e1000_write_emi_reg_locked(hw, I82579_MSE_THRESHOLD, 0x0034);
if (ret_val)
goto release;
- ret_val = hw->phy.ops.write_reg_locked(hw, I82579_EMI_ADDR,
- I82579_MSE_LINK_DOWN);
- if (ret_val)
- goto release;
/* drop link after 5 times MSE threshold was reached */
- ret_val = hw->phy.ops.write_reg_locked(hw, I82579_EMI_DATA,
- 0x0005);
+ ret_val = e1000_write_emi_reg_locked(hw, I82579_MSE_LINK_DOWN, 0x0005);
release:
hw->phy.ops.release(hw);
-out:
return ret_val;
}
@@ -1822,12 +2390,12 @@
DEBUGFUNC("e1000_k1_workaround_lv");
if (hw->mac.type != e1000_pch2lan)
- goto out;
+ return E1000_SUCCESS;
/* Set K1 beacon duration based on 1Gbps speed or otherwise */
ret_val = hw->phy.ops.read_reg(hw, HV_M_STATUS, &status_reg);
if (ret_val)
- goto out;
+ return ret_val;
if ((status_reg & (HV_M_STATUS_LINK_UP | HV_M_STATUS_AUTONEG_COMPLETE))
== (HV_M_STATUS_LINK_UP | HV_M_STATUS_AUTONEG_COMPLETE)) {
@@ -1836,11 +2404,23 @@
ret_val = hw->phy.ops.read_reg(hw, I82579_LPI_CTRL, &phy_reg);
if (ret_val)
- goto out;
+ return ret_val;
if (status_reg & HV_M_STATUS_SPEED_1000) {
+ u16 pm_phy_reg;
+
mac_reg |= E1000_FEXTNVM4_BEACON_DURATION_8USEC;
phy_reg &= ~I82579_LPI_CTRL_FORCE_PLL_LOCK_COUNT;
+ /* LV 1G Packet drop issue wa */
+ ret_val = hw->phy.ops.read_reg(hw, HV_PM_CTRL,
+ &pm_phy_reg);
+ if (ret_val)
+ return ret_val;
+ pm_phy_reg &= ~HV_PM_CTRL_PLL_STOP_IN_K1_GIGA;
+ ret_val = hw->phy.ops.write_reg(hw, HV_PM_CTRL,
+ pm_phy_reg);
+ if (ret_val)
+ return ret_val;
} else {
mac_reg |= E1000_FEXTNVM4_BEACON_DURATION_16USEC;
phy_reg |= I82579_LPI_CTRL_FORCE_PLL_LOCK_COUNT;
@@ -1849,7 +2429,6 @@
ret_val = hw->phy.ops.write_reg(hw, I82579_LPI_CTRL, phy_reg);
}
-out:
return ret_val;
}
@@ -1867,7 +2446,7 @@
DEBUGFUNC("e1000_gate_hw_phy_config_ich8lan");
- if (hw->mac.type != e1000_pch2lan)
+ if (hw->mac.type < e1000_pch2lan)
return;
extcnf_ctrl = E1000_READ_REG(hw, E1000_EXTCNF_CTRL);
@@ -1878,7 +2457,6 @@
extcnf_ctrl &= ~E1000_EXTCNF_CTRL_GATE_PHY_CFG;
E1000_WRITE_REG(hw, E1000_EXTCNF_CTRL, extcnf_ctrl);
- return;
}
/**
@@ -1901,8 +2479,7 @@
usec_delay(100);
} while ((!data) && --loop);
- /*
- * If basic configuration is incomplete before the above loop
+ /* If basic configuration is incomplete before the above loop
* count reaches 0, loading the configuration from NVM will
* leave the PHY in a bad state possibly resulting in no link.
*/
@@ -1927,7 +2504,7 @@
DEBUGFUNC("e1000_post_phy_reset_ich8lan");
if (hw->phy.ops.check_reset_block(hw))
- goto out;
+ return E1000_SUCCESS;
/* Allow time for h/w to get to quiescent state after reset */
msec_delay(10);
@@ -1937,12 +2514,12 @@
case e1000_pchlan:
ret_val = e1000_hv_phy_workarounds_ich8lan(hw);
if (ret_val)
- goto out;
+ return ret_val;
break;
case e1000_pch2lan:
ret_val = e1000_lv_phy_workarounds_ich8lan(hw);
if (ret_val)
- goto out;
+ return ret_val;
break;
default:
break;
@@ -1958,7 +2535,7 @@
/* Configure the LCD with the extended configuration region in NVM */
ret_val = e1000_sw_lcd_config_ich8lan(hw);
if (ret_val)
- goto out;
+ return ret_val;
/* Configure the LCD with the OEM bits in NVM */
ret_val = e1000_oem_bits_config_ich8lan(hw, TRUE);
@@ -1974,18 +2551,13 @@
/* Set EEE LPI Update Timer to 200usec */
ret_val = hw->phy.ops.acquire(hw);
if (ret_val)
- goto out;
- ret_val = hw->phy.ops.write_reg_locked(hw, I82579_EMI_ADDR,
- I82579_LPI_UPDATE_TIMER);
- if (ret_val)
- goto release;
- ret_val = hw->phy.ops.write_reg_locked(hw, I82579_EMI_DATA,
- 0x1387);
-release:
+ return ret_val;
+ ret_val = e1000_write_emi_reg_locked(hw,
+ I82579_LPI_UPDATE_TIMER,
+ 0x1387);
hw->phy.ops.release(hw);
}
-out:
return ret_val;
}
@@ -2010,12 +2582,9 @@
ret_val = e1000_phy_hw_reset_generic(hw);
if (ret_val)
- goto out;
+ return ret_val;
- ret_val = e1000_post_phy_reset_ich8lan(hw);
-
-out:
- return ret_val;
+ return e1000_post_phy_reset_ich8lan(hw);
}
/**
@@ -2031,7 +2600,7 @@
**/
static s32 e1000_set_lplu_state_pchlan(struct e1000_hw *hw, bool active)
{
- s32 ret_val = E1000_SUCCESS;
+ s32 ret_val;
u16 oem_reg;
DEBUGFUNC("e1000_set_lplu_state_pchlan");
@@ -2038,7 +2607,7 @@
ret_val = hw->phy.ops.read_reg(hw, HV_OEM_BITS, &oem_reg);
if (ret_val)
- goto out;
+ return ret_val;
if (active)
oem_reg |= HV_OEM_BITS_LPLU;
@@ -2048,10 +2617,7 @@
if (!hw->phy.ops.check_reset_block(hw))
oem_reg |= HV_OEM_BITS_RESTART_AN;
- ret_val = hw->phy.ops.write_reg(hw, HV_OEM_BITS, oem_reg);
-
-out:
- return ret_val;
+ return hw->phy.ops.write_reg(hw, HV_OEM_BITS, oem_reg);
}
/**
@@ -2077,7 +2643,7 @@
DEBUGFUNC("e1000_set_d0_lplu_state_ich8lan");
if (phy->type == e1000_phy_ife)
- goto out;
+ return E1000_SUCCESS;
phy_ctrl = E1000_READ_REG(hw, E1000_PHY_CTRL);
@@ -2086,10 +2652,9 @@
E1000_WRITE_REG(hw, E1000_PHY_CTRL, phy_ctrl);
if (phy->type != e1000_phy_igp_3)
- goto out;
+ return E1000_SUCCESS;
- /*
- * Call gig speed drop workaround on LPLU before accessing
+ /* Call gig speed drop workaround on LPLU before accessing
* any PHY registers
*/
if (hw->mac.type == e1000_ich8lan)
@@ -2099,21 +2664,22 @@
ret_val = phy->ops.read_reg(hw,
IGP01E1000_PHY_PORT_CONFIG,
&data);
+ if (ret_val)
+ return ret_val;
data &= ~IGP01E1000_PSCFR_SMART_SPEED;
ret_val = phy->ops.write_reg(hw,
IGP01E1000_PHY_PORT_CONFIG,
data);
if (ret_val)
- goto out;
+ return ret_val;
} else {
phy_ctrl &= ~E1000_PHY_CTRL_D0A_LPLU;
E1000_WRITE_REG(hw, E1000_PHY_CTRL, phy_ctrl);
if (phy->type != e1000_phy_igp_3)
- goto out;
+ return E1000_SUCCESS;
- /*
- * LPLU and SmartSpeed are mutually exclusive. LPLU is used
+ /* LPLU and SmartSpeed are mutually exclusive. LPLU is used
* during Dx states where the power conservation is most
* important. During driver activity we should enable
* SmartSpeed, so performance is maintained.
@@ -2123,7 +2689,7 @@
IGP01E1000_PHY_PORT_CONFIG,
&data);
if (ret_val)
- goto out;
+ return ret_val;
data |= IGP01E1000_PSCFR_SMART_SPEED;
ret_val = phy->ops.write_reg(hw,
@@ -2130,13 +2696,13 @@
IGP01E1000_PHY_PORT_CONFIG,
data);
if (ret_val)
- goto out;
+ return ret_val;
} else if (phy->smart_speed == e1000_smart_speed_off) {
ret_val = phy->ops.read_reg(hw,
IGP01E1000_PHY_PORT_CONFIG,
&data);
if (ret_val)
- goto out;
+ return ret_val;
data &= ~IGP01E1000_PSCFR_SMART_SPEED;
ret_val = phy->ops.write_reg(hw,
@@ -2143,12 +2709,11 @@
IGP01E1000_PHY_PORT_CONFIG,
data);
if (ret_val)
- goto out;
+ return ret_val;
}
}
-out:
- return ret_val;
+ return E1000_SUCCESS;
}
/**
@@ -2180,10 +2745,9 @@
E1000_WRITE_REG(hw, E1000_PHY_CTRL, phy_ctrl);
if (phy->type != e1000_phy_igp_3)
- goto out;
+ return E1000_SUCCESS;
- /*
- * LPLU and SmartSpeed are mutually exclusive. LPLU is used
+ /* LPLU and SmartSpeed are mutually exclusive. LPLU is used
* during Dx states where the power conservation is most
* important. During driver activity we should enable
* SmartSpeed, so performance is maintained.
@@ -2193,7 +2757,7 @@
IGP01E1000_PHY_PORT_CONFIG,
&data);
if (ret_val)
- goto out;
+ return ret_val;
data |= IGP01E1000_PSCFR_SMART_SPEED;
ret_val = phy->ops.write_reg(hw,
@@ -2200,13 +2764,13 @@
IGP01E1000_PHY_PORT_CONFIG,
data);
if (ret_val)
- goto out;
+ return ret_val;
} else if (phy->smart_speed == e1000_smart_speed_off) {
ret_val = phy->ops.read_reg(hw,
IGP01E1000_PHY_PORT_CONFIG,
&data);
if (ret_val)
- goto out;
+ return ret_val;
data &= ~IGP01E1000_PSCFR_SMART_SPEED;
ret_val = phy->ops.write_reg(hw,
@@ -2213,7 +2777,7 @@
IGP01E1000_PHY_PORT_CONFIG,
data);
if (ret_val)
- goto out;
+ return ret_val;
}
} else if ((phy->autoneg_advertised == E1000_ALL_SPEED_DUPLEX) ||
(phy->autoneg_advertised == E1000_ALL_NOT_GIG) ||
@@ -2222,10 +2786,9 @@
E1000_WRITE_REG(hw, E1000_PHY_CTRL, phy_ctrl);
if (phy->type != e1000_phy_igp_3)
- goto out;
+ return E1000_SUCCESS;
- /*
- * Call gig speed drop workaround on LPLU before accessing
+ /* Call gig speed drop workaround on LPLU before accessing
* any PHY registers
*/
if (hw->mac.type == e1000_ich8lan)
@@ -2236,7 +2799,7 @@
IGP01E1000_PHY_PORT_CONFIG,
&data);
if (ret_val)
- goto out;
+ return ret_val;
data &= ~IGP01E1000_PSCFR_SMART_SPEED;
ret_val = phy->ops.write_reg(hw,
@@ -2244,7 +2807,6 @@
data);
}
-out:
return ret_val;
}
@@ -2263,7 +2825,7 @@
u32 bank1_offset = nvm->flash_bank_size * sizeof(u16);
u32 act_offset = E1000_ICH_NVM_SIG_WORD * 2 + 1;
u8 sig_byte = 0;
- s32 ret_val = E1000_SUCCESS;
+ s32 ret_val;
DEBUGFUNC("e1000_valid_nvm_bank_detect_ich8lan");
@@ -2278,7 +2840,7 @@
else
*bank = 0;
- goto out;
+ return E1000_SUCCESS;
}
DEBUGOUT("Unable to determine valid NVM bank via EEC - reading flash signature\n");
/* fall-thru */
@@ -2290,11 +2852,11 @@
ret_val = e1000_read_flash_byte_ich8lan(hw, act_offset,
&sig_byte);
if (ret_val)
- goto out;
+ return ret_val;
if ((sig_byte & E1000_ICH_NVM_VALID_SIG_MASK) ==
E1000_ICH_NVM_SIG_VALUE) {
*bank = 0;
- goto out;
+ return E1000_SUCCESS;
}
/* Check bank 1 */
@@ -2302,19 +2864,16 @@
bank1_offset,
&sig_byte);
if (ret_val)
- goto out;
+ return ret_val;
if ((sig_byte & E1000_ICH_NVM_VALID_SIG_MASK) ==
E1000_ICH_NVM_SIG_VALUE) {
*bank = 1;
- goto out;
+ return E1000_SUCCESS;
}
DEBUGOUT("ERROR: No valid NVM bank present\n");
- ret_val = -E1000_ERR_NVM;
- break;
+ return -E1000_ERR_NVM;
}
-out:
- return ret_val;
}
/**
@@ -2396,9 +2955,9 @@
hsfsts.regval = E1000_READ_FLASH_REG16(hw, ICH_FLASH_HSFSTS);
/* Check if the flash descriptor is valid */
- if (hsfsts.hsf_status.fldesvalid == 0) {
+ if (!hsfsts.hsf_status.fldesvalid) {
DEBUGOUT("Flash descriptor invalid. SW Sequencing must be used.\n");
- goto out;
+ return -E1000_ERR_NVM;
}
/* Clear FCERR and DAEL in hw status by writing 1 */
@@ -2407,8 +2966,7 @@
E1000_WRITE_FLASH_REG16(hw, ICH_FLASH_HSFSTS, hsfsts.regval);
- /*
- * Either we should have a hardware SPI cycle in progress
+ /* Either we should have a hardware SPI cycle in progress
* bit to check against, in order to start a new cycle or
* FDONE bit should be changed in the hardware so that it
* is 1 after hardware reset, which can then be used as an
@@ -2416,9 +2974,8 @@
* completed.
*/
- if (hsfsts.hsf_status.flcinprog == 0) {
- /*
- * There is no cycle running at present,
+ if (!hsfsts.hsf_status.flcinprog) {
+ /* There is no cycle running at present,
* so we can start a cycle.
* Begin by setting Flash Cycle Done.
*/
@@ -2428,14 +2985,13 @@
} else {
s32 i;
- /*
- * Otherwise poll for sometime so the current
+ /* Otherwise poll for sometime so the current
* cycle has a chance to end before giving up.
*/
for (i = 0; i < ICH_FLASH_READ_COMMAND_TIMEOUT; i++) {
hsfsts.regval = E1000_READ_FLASH_REG16(hw,
ICH_FLASH_HSFSTS);
- if (hsfsts.hsf_status.flcinprog == 0) {
+ if (!hsfsts.hsf_status.flcinprog) {
ret_val = E1000_SUCCESS;
break;
}
@@ -2442,8 +2998,7 @@
usec_delay(1);
}
if (ret_val == E1000_SUCCESS) {
- /*
- * Successful in waiting for previous cycle to timeout,
+ /* Successful in waiting for previous cycle to timeout,
* now set the Flash Cycle Done.
*/
hsfsts.hsf_status.flcdone = 1;
@@ -2454,7 +3009,6 @@
}
}
-out:
return ret_val;
}
@@ -2469,7 +3023,6 @@
{
union ich8_hws_flash_ctrl hsflctl;
union ich8_hws_flash_status hsfsts;
- s32 ret_val = -E1000_ERR_NVM;
u32 i = 0;
DEBUGFUNC("e1000_flash_cycle_ich8lan");
@@ -2482,15 +3035,15 @@
/* wait till FDONE bit is set to 1 */
do {
hsfsts.regval = E1000_READ_FLASH_REG16(hw, ICH_FLASH_HSFSTS);
- if (hsfsts.hsf_status.flcdone == 1)
+ if (hsfsts.hsf_status.flcdone)
break;
usec_delay(1);
} while (i++ < timeout);
- if (hsfsts.hsf_status.flcdone == 1 && hsfsts.hsf_status.flcerr == 0)
- ret_val = E1000_SUCCESS;
+ if (hsfsts.hsf_status.flcdone && !hsfsts.hsf_status.flcerr)
+ return E1000_SUCCESS;
- return ret_val;
+ return -E1000_ERR_NVM;
}
/**
@@ -2505,22 +3058,15 @@
static s32 e1000_read_flash_word_ich8lan(struct e1000_hw *hw, u32 offset,
u16 *data)
{
- s32 ret_val;
-
DEBUGFUNC("e1000_read_flash_word_ich8lan");
- if (!data) {
- ret_val = -E1000_ERR_NVM;
- goto out;
- }
+ if (!data)
+ return -E1000_ERR_NVM;
/* Must convert offset into bytes. */
offset <<= 1;
- ret_val = e1000_read_flash_data_ich8lan(hw, offset, 2, data);
-
-out:
- return ret_val;
+ return e1000_read_flash_data_ich8lan(hw, offset, 2, data);
}
/**
@@ -2534,17 +3080,16 @@
static s32 e1000_read_flash_byte_ich8lan(struct e1000_hw *hw, u32 offset,
u8 *data)
{
- s32 ret_val = E1000_SUCCESS;
+ s32 ret_val;
u16 word = 0;
ret_val = e1000_read_flash_data_ich8lan(hw, offset, 1, &word);
if (ret_val)
- goto out;
+ return ret_val;
*data = (u8)word;
-out:
- return ret_val;
+ return E1000_SUCCESS;
}
/**
@@ -2569,7 +3114,7 @@
DEBUGFUNC("e1000_read_flash_data_ich8lan");
if (size < 1 || size > 2 || offset > ICH_FLASH_LINEAR_ADDR_MASK)
- goto out;
+ return -E1000_ERR_NVM;
flash_linear_addr = (ICH_FLASH_LINEAR_ADDR_MASK & offset) +
hw->nvm.flash_base_addr;
@@ -2592,8 +3137,7 @@
ret_val = e1000_flash_cycle_ich8lan(hw,
ICH_FLASH_READ_COMMAND_TIMEOUT);
- /*
- * Check if FCERR is set to 1, if set to 1, clear it
+ /* Check if FCERR is set to 1, if set to 1, clear it
* and try the whole sequence a few more times, else
* read in (shift in) the Flash Data0, the order is
* least significant byte first msb to lsb
@@ -2606,8 +3150,7 @@
*data = (u16)(flash_data & 0x0000FFFF);
break;
} else {
- /*
- * If we've gotten here, then things are probably
+ /* If we've gotten here, then things are probably
* completely hosed, but if the error condition is
* detected, it won't hurt to give it another try...
* ICH_FLASH_CYCLE_REPEAT_COUNT times.
@@ -2614,10 +3157,10 @@
*/
hsfsts.regval = E1000_READ_FLASH_REG16(hw,
ICH_FLASH_HSFSTS);
- if (hsfsts.hsf_status.flcerr == 1) {
+ if (hsfsts.hsf_status.flcerr) {
/* Repeat for some time before giving up. */
continue;
- } else if (hsfsts.hsf_status.flcdone == 0) {
+ } else if (!hsfsts.hsf_status.flcdone) {
DEBUGOUT("Timeout error - flash cycle did not complete.\n");
break;
}
@@ -2624,7 +3167,6 @@
}
} while (count++ < ICH_FLASH_CYCLE_REPEAT_COUNT);
-out:
return ret_val;
}
@@ -2642,7 +3184,6 @@
{
struct e1000_nvm_info *nvm = &hw->nvm;
struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
- s32 ret_val = E1000_SUCCESS;
u16 i;
DEBUGFUNC("e1000_write_nvm_ich8lan");
@@ -2650,8 +3191,7 @@
if ((offset >= nvm->word_size) || (words > nvm->word_size - offset) ||
(words == 0)) {
DEBUGOUT("nvm parameter(s) out of bounds\n");
- ret_val = -E1000_ERR_NVM;
- goto out;
+ return -E1000_ERR_NVM;
}
nvm->ops.acquire(hw);
@@ -2663,8 +3203,7 @@
nvm->ops.release(hw);
-out:
- return ret_val;
+ return E1000_SUCCESS;
}
/**
@@ -2697,8 +3236,7 @@
nvm->ops.acquire(hw);
- /*
- * We're writing to the opposite bank so if we're on bank 1,
+ /* We're writing to the opposite bank so if we're on bank 1,
* write to bank 0 etc. We also need to erase the segment that
* is going to be written
*/
@@ -2723,8 +3261,7 @@
}
for (i = 0; i < E1000_SHADOW_RAM_WORDS; i++) {
- /*
- * Determine whether to write the value stored
+ /* Determine whether to write the value stored
* in the other NVM bank or a modified value stored
* in the shadow RAM
*/
@@ -2738,8 +3275,7 @@
break;
}
- /*
- * If the word is 0x13, then make sure the signature bits
+ /* If the word is 0x13, then make sure the signature bits
* (15:14) are 11b until the commit has completed.
* This will allow us to write 10b which indicates the
* signature is valid. We want to do this after the write
@@ -2768,8 +3304,7 @@
break;
}
- /*
- * Don't bother writing the segment valid bits if sector
+ /* Don't bother writing the segment valid bits if sector
* programming failed.
*/
if (ret_val) {
@@ -2777,8 +3312,7 @@
goto release;
}
- /*
- * Finally validate the new segment by setting bit 15:14
+ /* Finally validate the new segment by setting bit 15:14
* to 10b in word 0x13 , this can be done without an
* erase as well since these bits are 11 to start with
* and we need to change bit 14 to 0b
@@ -2795,8 +3329,7 @@
if (ret_val)
goto release;
- /*
- * And invalidate the previously valid segment by setting
+ /* And invalidate the previously valid segment by setting
* its signature word (0x13) high_byte to 0b. This can be
* done without an erase because flash erase sets all bits
* to 1's. We can write 1's to 0's without an erase
@@ -2815,8 +3348,7 @@
release:
nvm->ops.release(hw);
- /*
- * Reload the EEPROM, or else modifications will not appear
+ /* Reload the EEPROM, or else modifications will not appear
* until after the next adapter reset.
*/
if (!ret_val) {
@@ -2841,35 +3373,44 @@
**/
static s32 e1000_validate_nvm_checksum_ich8lan(struct e1000_hw *hw)
{
- s32 ret_val = E1000_SUCCESS;
+ s32 ret_val;
u16 data;
+ u16 word;
+ u16 valid_csum_mask;
DEBUGFUNC("e1000_validate_nvm_checksum_ich8lan");
- /*
- * Read 0x19 and check bit 6. If this bit is 0, the checksum
- * needs to be fixed. This bit is an indication that the NVM
- * was prepared by OEM software and did not calculate the
- * checksum...a likely scenario.
+ /* Read NVM and check Invalid Image CSUM bit. If this bit is 0,
+ * the checksum needs to be fixed. This bit is an indication that
+ * the NVM was prepared by OEM software and did not calculate
+ * the checksum...a likely scenario.
*/
- ret_val = hw->nvm.ops.read(hw, 0x19, 1, &data);
+ switch (hw->mac.type) {
+ case e1000_pch_lpt:
+ word = NVM_COMPAT;
+ valid_csum_mask = NVM_COMPAT_VALID_CSUM;
+ break;
+ default:
+ word = NVM_FUTURE_INIT_WORD1;
+ valid_csum_mask = NVM_FUTURE_INIT_WORD1_VALID_CSUM;
+ break;
+ }
+
+ ret_val = hw->nvm.ops.read(hw, word, 1, &data);
if (ret_val)
- goto out;
+ return ret_val;
- if ((data & 0x40) == 0) {
- data |= 0x40;
- ret_val = hw->nvm.ops.write(hw, 0x19, 1, &data);
+ if (!(data & valid_csum_mask)) {
+ data |= valid_csum_mask;
+ ret_val = hw->nvm.ops.write(hw, word, 1, &data);
if (ret_val)
- goto out;
+ return ret_val;
ret_val = hw->nvm.ops.update(hw);
if (ret_val)
- goto out;
+ return ret_val;
}
- ret_val = e1000_validate_nvm_checksum_generic(hw);
-
-out:
- return ret_val;
+ return e1000_validate_nvm_checksum_generic(hw);
}
/**
@@ -2888,7 +3429,7 @@
union ich8_hws_flash_ctrl hsflctl;
u32 flash_linear_addr;
u32 flash_data = 0;
- s32 ret_val = -E1000_ERR_NVM;
+ s32 ret_val;
u8 count = 0;
DEBUGFUNC("e1000_write_ich8_data");
@@ -2895,7 +3436,7 @@
if (size < 1 || size > 2 || data > size * 0xff ||
offset > ICH_FLASH_LINEAR_ADDR_MASK)
- goto out;
+ return -E1000_ERR_NVM;
flash_linear_addr = (ICH_FLASH_LINEAR_ADDR_MASK & offset) +
hw->nvm.flash_base_addr;
@@ -2922,8 +3463,7 @@
E1000_WRITE_FLASH_REG(hw, ICH_FLASH_FDATA0, flash_data);
- /*
- * check if FCERR is set to 1 , if set to 1, clear it
+ /* check if FCERR is set to 1 , if set to 1, clear it
* and try the whole sequence a few more times else done
*/
ret_val = e1000_flash_cycle_ich8lan(hw,
@@ -2931,23 +3471,21 @@
if (ret_val == E1000_SUCCESS)
break;
- /*
- * If we're here, then things are most likely
+ /* If we're here, then things are most likely
* completely hosed, but if the error condition
* is detected, it won't hurt to give it another
* try...ICH_FLASH_CYCLE_REPEAT_COUNT times.
*/
hsfsts.regval = E1000_READ_FLASH_REG16(hw, ICH_FLASH_HSFSTS);
- if (hsfsts.hsf_status.flcerr == 1)
+ if (hsfsts.hsf_status.flcerr)
/* Repeat for some time before giving up. */
continue;
- if (hsfsts.hsf_status.flcdone == 0) {
+ if (!hsfsts.hsf_status.flcdone) {
DEBUGOUT("Timeout error - flash cycle did not complete.\n");
break;
}
} while (count++ < ICH_FLASH_CYCLE_REPEAT_COUNT);
-out:
return ret_val;
}
@@ -2987,8 +3525,8 @@
DEBUGFUNC("e1000_retry_write_flash_byte_ich8lan");
ret_val = e1000_write_flash_byte_ich8lan(hw, offset, byte);
- if (ret_val == E1000_SUCCESS)
- goto out;
+ if (!ret_val)
+ return ret_val;
for (program_retries = 0; program_retries < 100; program_retries++) {
DEBUGOUT2("Retrying Byte %2.2X at offset %u\n", byte, offset);
@@ -2997,13 +3535,10 @@
if (ret_val == E1000_SUCCESS)
break;
}
- if (program_retries == 100) {
- ret_val = -E1000_ERR_NVM;
- goto out;
- }
+ if (program_retries == 100)
+ return -E1000_ERR_NVM;
-out:
- return ret_val;
+ return E1000_SUCCESS;
}
/**
@@ -3022,7 +3557,7 @@
u32 flash_linear_addr;
/* bank size is in 16bit words - adjust to bytes */
u32 flash_bank_size = nvm->flash_bank_size * 2;
- s32 ret_val = E1000_SUCCESS;
+ s32 ret_val;
s32 count = 0;
s32 j, iteration, sector_size;
@@ -3030,8 +3565,7 @@
hsfsts.regval = E1000_READ_FLASH_REG16(hw, ICH_FLASH_HSFSTS);
- /*
- * Determine HW Sector size: Read BERASE bits of hw flash status
+ /* Determine HW Sector size: Read BERASE bits of hw flash status
* register
* 00: The Hw sector is 256 bytes, hence we need to erase 16
* consecutive sectors. The start index for the nth Hw sector
@@ -3062,8 +3596,7 @@
iteration = 1;
break;
default:
- ret_val = -E1000_ERR_NVM;
- goto out;
+ return -E1000_ERR_NVM;
}
/* Start with the base address, then add the sector offset. */
@@ -3075,10 +3608,9 @@
/* Steps */
ret_val = e1000_flash_cycle_init_ich8lan(hw);
if (ret_val)
- goto out;
+ return ret_val;
- /*
- * Write a value 11 (block Erase) in Flash
+ /* Write a value 11 (block Erase) in Flash
* Cycle field in hw flash control
*/
hsflctl.regval = E1000_READ_FLASH_REG16(hw,
@@ -3087,8 +3619,7 @@
E1000_WRITE_FLASH_REG16(hw, ICH_FLASH_HSFCTL,
hsflctl.regval);
- /*
- * Write the last 24 bits of an index within the
+ /* Write the last 24 bits of an index within the
* block into Flash Linear address field in Flash
* Address.
*/
@@ -3101,23 +3632,21 @@
if (ret_val == E1000_SUCCESS)
break;
- /*
- * Check if FCERR is set to 1. If 1,
+ /* Check if FCERR is set to 1. If 1,
* clear it and try the whole sequence
* a few more times else Done
*/
hsfsts.regval = E1000_READ_FLASH_REG16(hw,
ICH_FLASH_HSFSTS);
- if (hsfsts.hsf_status.flcerr == 1)
+ if (hsfsts.hsf_status.flcerr)
/* repeat for some time before giving up */
continue;
- else if (hsfsts.hsf_status.flcdone == 0)
- goto out;
+ else if (!hsfsts.hsf_status.flcdone)
+ return ret_val;
} while (++count < ICH_FLASH_CYCLE_REPEAT_COUNT);
}
-out:
- return ret_val;
+ return E1000_SUCCESS;
}
/**
@@ -3138,14 +3667,13 @@
ret_val = hw->nvm.ops.read(hw, NVM_ID_LED_SETTINGS, 1, data);
if (ret_val) {
DEBUGOUT("NVM Read Error\n");
- goto out;
+ return ret_val;
}
if (*data == ID_LED_RESERVED_0000 || *data == ID_LED_RESERVED_FFFF)
*data = ID_LED_DEFAULT_ICH8LAN;
-out:
- return ret_val;
+ return E1000_SUCCESS;
}
/**
@@ -3174,7 +3702,7 @@
/* Get default ID LED modes */
ret_val = hw->nvm.ops.valid_led_default(hw, &data);
if (ret_val)
- goto out;
+ return ret_val;
mac->ledctl_default = E1000_READ_REG(hw, E1000_LEDCTL);
mac->ledctl_mode1 = mac->ledctl_default;
@@ -3219,8 +3747,7 @@
}
}
-out:
- return ret_val;
+ return E1000_SUCCESS;
}
/**
@@ -3239,8 +3766,7 @@
ret_val = e1000_get_bus_info_pcie_generic(hw);
- /*
- * ICH devices are "PCI Express"-ish. They have
+ /* ICH devices are "PCI Express"-ish. They have
* a configuration space, but do not contain
* PCI Express Capability registers, so bus width
* must be hardcoded.
@@ -3261,14 +3787,13 @@
static s32 e1000_reset_hw_ich8lan(struct e1000_hw *hw)
{
struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
- u16 reg;
- u32 ctrl, kab;
+ u16 kum_cfg;
+ u32 ctrl, reg;
s32 ret_val;
DEBUGFUNC("e1000_reset_hw_ich8lan");
- /*
- * Prevent the PCI-E bus from sticking if there is no TLP connection
+ /* Prevent the PCI-E bus from sticking if there is no TLP connection
* on the last TLP read/write transaction when MAC is reset.
*/
ret_val = e1000_disable_pcie_master_generic(hw);
@@ -3278,8 +3803,7 @@
DEBUGOUT("Masking off all interrupts\n");
E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff);
- /*
- * Disable the Transmit and Receive units. Then delay to allow
+ /* Disable the Transmit and Receive units. Then delay to allow
* any pending transactions to complete before we hit the MAC
* with the global reset.
*/
@@ -3299,11 +3823,11 @@
if (hw->mac.type == e1000_pchlan) {
/* Save the NVM K1 bit setting*/
- ret_val = e1000_read_nvm(hw, E1000_NVM_K1_CONFIG, 1, ®);
+ ret_val = e1000_read_nvm(hw, E1000_NVM_K1_CONFIG, 1, &kum_cfg);
if (ret_val)
return ret_val;
- if (reg & E1000_NVM_K1_ENABLE)
+ if (kum_cfg & E1000_NVM_K1_ENABLE)
dev_spec->nvm_k1_enabled = TRUE;
else
dev_spec->nvm_k1_enabled = FALSE;
@@ -3312,15 +3836,13 @@
ctrl = E1000_READ_REG(hw, E1000_CTRL);
if (!hw->phy.ops.check_reset_block(hw)) {
- /*
- * Full-chip reset requires MAC and PHY reset at the same
+ /* Full-chip reset requires MAC and PHY reset at the same
* time to make sure the interface between MAC and the
* external PHY is reset.
*/
ctrl |= E1000_CTRL_PHY_RST;
- /*
- * Gate automatic PHY configuration by hardware on
+ /* Gate automatic PHY configuration by hardware on
* non-managed 82579
*/
if ((hw->mac.type == e1000_pch2lan) &&
@@ -3333,6 +3855,14 @@
/* cannot issue a flush here because it hangs the hardware */
msec_delay(20);
+ /* Set Phy Config Counter to 50msec */
+ if (hw->mac.type == e1000_pch2lan) {
+ reg = E1000_READ_REG(hw, E1000_FEXTNVM3);
+ reg &= ~E1000_FEXTNVM3_PHY_CFG_COUNTER_MASK;
+ reg |= E1000_FEXTNVM3_PHY_CFG_COUNTER_50MSEC;
+ E1000_WRITE_REG(hw, E1000_FEXTNVM3, reg);
+ }
+
if (!ret_val)
E1000_MUTEX_UNLOCK(&hw->dev_spec.ich8lan.swflag_mutex);
@@ -3339,15 +3869,14 @@
if (ctrl & E1000_CTRL_PHY_RST) {
ret_val = hw->phy.ops.get_cfg_done(hw);
if (ret_val)
- goto out;
+ return ret_val;
ret_val = e1000_post_phy_reset_ich8lan(hw);
if (ret_val)
- goto out;
+ return ret_val;
}
- /*
- * For PCH, this write will make sure that any noise
+ /* For PCH, this write will make sure that any noise
* will be detected as a CRC error and be dropped rather than show up
* as a bad packet to the DMA engine.
*/
@@ -3357,12 +3886,11 @@
E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff);
E1000_READ_REG(hw, E1000_ICR);
- kab = E1000_READ_REG(hw, E1000_KABGTXD);
- kab |= E1000_KABGTXD_BGSQLBIAS;
- E1000_WRITE_REG(hw, E1000_KABGTXD, kab);
+ reg = E1000_READ_REG(hw, E1000_KABGTXD);
+ reg |= E1000_KABGTXD_BGSQLBIAS;
+ E1000_WRITE_REG(hw, E1000_KABGTXD, reg);
-out:
- return ret_val;
+ return E1000_SUCCESS;
}
/**
@@ -3390,9 +3918,9 @@
/* Initialize identification LED */
ret_val = mac->ops.id_led_init(hw);
+ /* An error is not fatal and we should not stop init due to this */
if (ret_val)
DEBUGOUT("Error initializing identification LED\n");
- /* This is not fatal and we should not stop init due to this */
/* Setup the receive address. */
e1000_init_rx_addrs_generic(hw, mac->rar_entry_count);
@@ -3402,8 +3930,7 @@
for (i = 0; i < mac->mta_reg_count; i++)
E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, 0);
- /*
- * The 82578 Rx buffer will stall if wakeup is enabled in host and
+ /* The 82578 Rx buffer will stall if wakeup is enabled in host and
* the ME. Disable wakeup by clearing the host wakeup bit.
* Reset the phy after disabling host wakeup to reset the Rx buffer.
*/
@@ -3433,8 +3960,7 @@
E1000_TXDCTL_MAX_TX_DESC_PREFETCH;
E1000_WRITE_REG(hw, E1000_TXDCTL(1), txdctl);
- /*
- * ICH8 has opposite polarity of no_snoop bits.
+ /* ICH8 has opposite polarity of no_snoop bits.
* By default, we should use snoop behavior.
*/
if (mac->type == e1000_ich8lan)
@@ -3447,8 +3973,7 @@
ctrl_ext |= E1000_CTRL_EXT_RO_DIS;
E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
- /*
- * Clear all of the statistics registers (clear on read). It is
+ /* Clear all of the statistics registers (clear on read). It is
* important that we do this after we have tried to establish link
* because the symbol error count will increment wildly if there
* is no link.
@@ -3457,6 +3982,7 @@
return ret_val;
}
+
/**
* e1000_initialize_hw_bits_ich8lan - Initialize required hardware bits
* @hw: pointer to the HW structure
@@ -3511,14 +4037,29 @@
E1000_WRITE_REG(hw, E1000_STATUS, reg);
}
- /*
- * work-around descriptor data corruption issue during nfs v2 udp
+ /* work-around descriptor data corruption issue during nfs v2 udp
* traffic, just disable the nfs filtering capability
*/
reg = E1000_READ_REG(hw, E1000_RFCTL);
reg |= (E1000_RFCTL_NFSW_DIS | E1000_RFCTL_NFSR_DIS);
+ /* Disable IPv6 extension header parsing because some malformed
+ * IPv6 headers can hang the Rx.
+ */
+ if (hw->mac.type == e1000_ich8lan)
+ reg |= (E1000_RFCTL_IPV6_EX_DIS | E1000_RFCTL_NEW_IPV6_EXT_DIS);
E1000_WRITE_REG(hw, E1000_RFCTL, reg);
+ /* Enable ECC on Lynxpoint */
+ if (hw->mac.type == e1000_pch_lpt) {
+ reg = E1000_READ_REG(hw, E1000_PBECCSTS);
+ reg |= E1000_PBECCSTS_ECC_ENABLE;
+ E1000_WRITE_REG(hw, E1000_PBECCSTS, reg);
+
+ reg = E1000_READ_REG(hw, E1000_CTRL);
+ reg |= E1000_CTRL_MEHE;
+ E1000_WRITE_REG(hw, E1000_CTRL, reg);
+ }
+
return;
}
@@ -3534,15 +4075,14 @@
**/
static s32 e1000_setup_link_ich8lan(struct e1000_hw *hw)
{
- s32 ret_val = E1000_SUCCESS;
+ s32 ret_val;
DEBUGFUNC("e1000_setup_link_ich8lan");
if (hw->phy.ops.check_reset_block(hw))
- goto out;
+ return E1000_SUCCESS;
- /*
- * ICH parts do not have a word in the NVM to determine
+ /* ICH parts do not have a word in the NVM to determine
* the default flow control setting, so we explicitly
* set it to full.
*/
@@ -3549,8 +4089,7 @@
if (hw->fc.requested_mode == e1000_fc_default)
hw->fc.requested_mode = e1000_fc_full;
- /*
- * Save off the requested flow control mode for use later. Depending
+ /* Save off the requested flow control mode for use later. Depending
* on the link partner's capabilities, we may or may not use this mode.
*/
hw->fc.current_mode = hw->fc.requested_mode;
@@ -3561,11 +4100,12 @@
/* Continue to configure the copper link. */
ret_val = hw->mac.ops.setup_physical_interface(hw);
if (ret_val)
- goto out;
+ return ret_val;
E1000_WRITE_REG(hw, E1000_FCTTV, hw->fc.pause_time);
if ((hw->phy.type == e1000_phy_82578) ||
(hw->phy.type == e1000_phy_82579) ||
+ (hw->phy.type == e1000_phy_i217) ||
(hw->phy.type == e1000_phy_82577)) {
E1000_WRITE_REG(hw, E1000_FCRTV_PCH, hw->fc.refresh_time);
@@ -3573,13 +4113,10 @@
PHY_REG(BM_PORT_CTRL_PAGE, 27),
hw->fc.pause_time);
if (ret_val)
- goto out;
+ return ret_val;
}
- ret_val = e1000_set_fc_watermarks_generic(hw);
-
-out:
- return ret_val;
+ return e1000_set_fc_watermarks_generic(hw);
}
/**
@@ -3603,8 +4140,7 @@
ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
- /*
- * Set the mac to wait the maximum time between each iteration
+ /* Set the mac to wait the maximum time between each iteration
* and increase the max iterations when polling the phy;
* this fixes erroneous timeouts at 10Mbps.
*/
@@ -3611,42 +4147,42 @@
ret_val = e1000_write_kmrn_reg_generic(hw, E1000_KMRNCTRLSTA_TIMEOUTS,
0xFFFF);
if (ret_val)
- goto out;
+ return ret_val;
ret_val = e1000_read_kmrn_reg_generic(hw,
E1000_KMRNCTRLSTA_INBAND_PARAM,
®_data);
if (ret_val)
- goto out;
+ return ret_val;
reg_data |= 0x3F;
ret_val = e1000_write_kmrn_reg_generic(hw,
E1000_KMRNCTRLSTA_INBAND_PARAM,
reg_data);
if (ret_val)
- goto out;
+ return ret_val;
switch (hw->phy.type) {
case e1000_phy_igp_3:
ret_val = e1000_copper_link_setup_igp(hw);
if (ret_val)
- goto out;
+ return ret_val;
break;
case e1000_phy_bm:
case e1000_phy_82578:
ret_val = e1000_copper_link_setup_m88(hw);
if (ret_val)
- goto out;
+ return ret_val;
break;
case e1000_phy_82577:
case e1000_phy_82579:
ret_val = e1000_copper_link_setup_82577(hw);
if (ret_val)
- goto out;
+ return ret_val;
break;
case e1000_phy_ife:
ret_val = hw->phy.ops.read_reg(hw, IFE_PHY_MDIX_CONTROL,
®_data);
if (ret_val)
- goto out;
+ return ret_val;
reg_data &= ~IFE_PMC_AUTO_MDIX;
@@ -3665,18 +4201,43 @@
ret_val = hw->phy.ops.write_reg(hw, IFE_PHY_MDIX_CONTROL,
reg_data);
if (ret_val)
- goto out;
+ return ret_val;
break;
default:
break;
}
- ret_val = e1000_setup_copper_link_generic(hw);
-out:
- return ret_val;
+ return e1000_setup_copper_link_generic(hw);
}
/**
+ * e1000_setup_copper_link_pch_lpt - Configure MAC/PHY interface
+ * @hw: pointer to the HW structure
+ *
+ * Calls the PHY specific link setup function and then calls the
+ * generic setup_copper_link to finish configuring the link for
+ * Lynxpoint PCH devices
+ **/
+static s32 e1000_setup_copper_link_pch_lpt(struct e1000_hw *hw)
+{
+ u32 ctrl;
+ s32 ret_val;
+
+ DEBUGFUNC("e1000_setup_copper_link_pch_lpt");
+
+ ctrl = E1000_READ_REG(hw, E1000_CTRL);
+ ctrl |= E1000_CTRL_SLU;
+ ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
+ E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
+
+ ret_val = e1000_copper_link_setup_82577(hw);
+ if (ret_val)
+ return ret_val;
+
+ return e1000_setup_copper_link_generic(hw);
+}
+
+/**
* e1000_get_link_up_info_ich8lan - Get current link speed and duplex
* @hw: pointer to the HW structure
* @speed: pointer to store current link speed
@@ -3695,7 +4256,7 @@
ret_val = e1000_get_speed_and_duplex_copper_generic(hw, speed, duplex);
if (ret_val)
- goto out;
+ return ret_val;
if ((hw->mac.type == e1000_ich8lan) &&
(hw->phy.type == e1000_phy_igp_3) &&
@@ -3703,7 +4264,6 @@
ret_val = e1000_kmrn_lock_loss_workaround_ich8lan(hw);
}
-out:
return ret_val;
}
@@ -3726,7 +4286,7 @@
{
struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
u32 phy_ctrl;
- s32 ret_val = E1000_SUCCESS;
+ s32 ret_val;
u16 i, data;
bool link;
@@ -3733,34 +4293,29 @@
DEBUGFUNC("e1000_kmrn_lock_loss_workaround_ich8lan");
if (!dev_spec->kmrn_lock_loss_workaround_enabled)
- goto out;
+ return E1000_SUCCESS;
- /*
- * Make sure link is up before proceeding. If not just return.
+ /* Make sure link is up before proceeding. If not just return.
* Attempting this while link is negotiating fouled up link
* stability
*/
ret_val = e1000_phy_has_link_generic(hw, 1, 0, &link);
- if (!link) {
- ret_val = E1000_SUCCESS;
- goto out;
- }
+ if (!link)
+ return E1000_SUCCESS;
for (i = 0; i < 10; i++) {
/* read once to clear */
ret_val = hw->phy.ops.read_reg(hw, IGP3_KMRN_DIAG, &data);
if (ret_val)
- goto out;
+ return ret_val;
/* and again to get new status */
ret_val = hw->phy.ops.read_reg(hw, IGP3_KMRN_DIAG, &data);
if (ret_val)
- goto out;
+ return ret_val;
/* check for PCS lock */
- if (!(data & IGP3_KMRN_DIAG_PCS_LOCK_LOSS)) {
- ret_val = E1000_SUCCESS;
- goto out;
- }
+ if (!(data & IGP3_KMRN_DIAG_PCS_LOCK_LOSS))
+ return E1000_SUCCESS;
/* Issue PHY reset */
hw->phy.ops.reset(hw);
@@ -3772,17 +4327,13 @@
E1000_PHY_CTRL_NOND0A_GBE_DISABLE);
E1000_WRITE_REG(hw, E1000_PHY_CTRL, phy_ctrl);
- /*
- * Call gig speed drop workaround on Gig disable before accessing
+ /* Call gig speed drop workaround on Gig disable before accessing
* any PHY registers
*/
e1000_gig_downshift_workaround_ich8lan(hw);
/* unable to acquire PCS lock */
- ret_val = -E1000_ERR_PHY;
-
-out:
- return ret_val;
+ return -E1000_ERR_PHY;
}
/**
@@ -3829,7 +4380,7 @@
DEBUGFUNC("e1000_igp3_phy_powerdown_workaround_ich8lan");
if (hw->phy.type != e1000_phy_igp_3)
- goto out;
+ return;
/* Try the workaround twice (if needed) */
do {
@@ -3839,8 +4390,7 @@
E1000_PHY_CTRL_NOND0A_GBE_DISABLE);
E1000_WRITE_REG(hw, E1000_PHY_CTRL, reg);
- /*
- * Call gig speed drop workaround on Gig disable before
+ /* Call gig speed drop workaround on Gig disable before
* accessing any PHY registers
*/
if (hw->mac.type == e1000_ich8lan)
@@ -3863,9 +4413,6 @@
E1000_WRITE_REG(hw, E1000_CTRL, reg | E1000_CTRL_PHY_RST);
retry++;
} while (retry);
-
-out:
- return;
}
/**
@@ -3880,7 +4427,7 @@
**/
void e1000_gig_downshift_workaround_ich8lan(struct e1000_hw *hw)
{
- s32 ret_val = E1000_SUCCESS;
+ s32 ret_val;
u16 reg_data;
DEBUGFUNC("e1000_gig_downshift_workaround_ich8lan");
@@ -3887,24 +4434,21 @@
if ((hw->mac.type != e1000_ich8lan) ||
(hw->phy.type == e1000_phy_ife))
- goto out;
+ return;
ret_val = e1000_read_kmrn_reg_generic(hw, E1000_KMRNCTRLSTA_DIAG_OFFSET,
®_data);
if (ret_val)
- goto out;
+ return;
reg_data |= E1000_KMRNCTRLSTA_DIAG_NELPBK;
ret_val = e1000_write_kmrn_reg_generic(hw,
E1000_KMRNCTRLSTA_DIAG_OFFSET,
reg_data);
if (ret_val)
- goto out;
+ return;
reg_data &= ~E1000_KMRNCTRLSTA_DIAG_NELPBK;
- ret_val = e1000_write_kmrn_reg_generic(hw,
- E1000_KMRNCTRLSTA_DIAG_OFFSET,
- reg_data);
-out:
- return;
+ e1000_write_kmrn_reg_generic(hw, E1000_KMRNCTRLSTA_DIAG_OFFSET,
+ reg_data);
}
/**
@@ -3917,9 +4461,13 @@
* the LPLU setting in the NVM or custom setting. For PCH and newer parts,
* the OEM bits PHY register (LED, GbE disable and LPLU configurations) also
* needs to be written.
+ * Parts that support (and are linked to a partner which support) EEE in
+ * 100Mbps should disable LPLU since 100Mbps w/ EEE requires less power
+ * than 10Mbps w/o EEE.
**/
void e1000_suspend_workarounds_ich8lan(struct e1000_hw *hw)
{
+ struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
u32 phy_ctrl;
s32 ret_val;
@@ -3927,13 +4475,96 @@
phy_ctrl = E1000_READ_REG(hw, E1000_PHY_CTRL);
phy_ctrl |= E1000_PHY_CTRL_GBE_DISABLE;
+
+ if (hw->phy.type == e1000_phy_i217) {
+ u16 phy_reg, device_id = hw->device_id;
+
+ if ((device_id == E1000_DEV_ID_PCH_LPTLP_I218_LM) ||
+ (device_id == E1000_DEV_ID_PCH_LPTLP_I218_V)) {
+ u32 fextnvm6 = E1000_READ_REG(hw, E1000_FEXTNVM6);
+
+ E1000_WRITE_REG(hw, E1000_FEXTNVM6,
+ fextnvm6 & ~E1000_FEXTNVM6_REQ_PLL_CLK);
+ }
+
+ ret_val = hw->phy.ops.acquire(hw);
+ if (ret_val)
+ goto out;
+
+ if (!dev_spec->eee_disable) {
+ u16 eee_advert;
+
+ ret_val =
+ e1000_read_emi_reg_locked(hw,
+ I217_EEE_ADVERTISEMENT,
+ &eee_advert);
+ if (ret_val)
+ goto release;
+
+ /* Disable LPLU if both link partners support 100BaseT
+ * EEE and 100Full is advertised on both ends of the
+ * link.
+ */
+ if ((eee_advert & I82579_EEE_100_SUPPORTED) &&
+ (dev_spec->eee_lp_ability &
+ I82579_EEE_100_SUPPORTED) &&
+ (hw->phy.autoneg_advertised & ADVERTISE_100_FULL))
+ phy_ctrl &= ~(E1000_PHY_CTRL_D0A_LPLU |
+ E1000_PHY_CTRL_NOND0A_LPLU);
+ }
+
+ /* For i217 Intel Rapid Start Technology support,
+ * when the system is going into Sx and no manageability engine
+ * is present, the driver must configure proxy to reset only on
+ * power good. LPI (Low Power Idle) state must also reset only
+ * on power good, as well as the MTA (Multicast table array).
+ * The SMBus release must also be disabled on LCD reset.
+ */
+ if (!(E1000_READ_REG(hw, E1000_FWSM) &
+ E1000_ICH_FWSM_FW_VALID)) {
+ /* Enable proxy to reset only on power good. */
+ hw->phy.ops.read_reg_locked(hw, I217_PROXY_CTRL,
+ &phy_reg);
+ phy_reg |= I217_PROXY_CTRL_AUTO_DISABLE;
+ hw->phy.ops.write_reg_locked(hw, I217_PROXY_CTRL,
+ phy_reg);
+
+ /* Set bit enable LPI (EEE) to reset only on
+ * power good.
+ */
+ hw->phy.ops.read_reg_locked(hw, I217_SxCTRL, &phy_reg);
+ phy_reg |= I217_SxCTRL_ENABLE_LPI_RESET;
+ hw->phy.ops.write_reg_locked(hw, I217_SxCTRL, phy_reg);
+
+ /* Disable the SMB release on LCD reset. */
+ hw->phy.ops.read_reg_locked(hw, I217_MEMPWR, &phy_reg);
+ phy_reg &= ~I217_MEMPWR_DISABLE_SMB_RELEASE;
+ hw->phy.ops.write_reg_locked(hw, I217_MEMPWR, phy_reg);
+ }
+
+ /* Enable MTA to reset for Intel Rapid Start Technology
+ * Support
+ */
+ hw->phy.ops.read_reg_locked(hw, I217_CGFREG, &phy_reg);
+ phy_reg |= I217_CGFREG_ENABLE_MTA_RESET;
+ hw->phy.ops.write_reg_locked(hw, I217_CGFREG, phy_reg);
+
+release:
+ hw->phy.ops.release(hw);
+ }
+out:
E1000_WRITE_REG(hw, E1000_PHY_CTRL, phy_ctrl);
+
if (hw->mac.type == e1000_ich8lan)
e1000_gig_downshift_workaround_ich8lan(hw);
if (hw->mac.type >= e1000_pchlan) {
e1000_oem_bits_config_ich8lan(hw, FALSE);
- e1000_phy_hw_reset_ich8lan(hw);
+
+ /* Reset PHY to activate OEM bits on 82577/8 */
+ if (hw->mac.type == e1000_pchlan)
+ e1000_phy_hw_reset_generic(hw);
+
ret_val = hw->phy.ops.acquire(hw);
if (ret_val)
return;
@@ -3952,48 +4583,64 @@
* on which PHY resets are not blocked, if the PHY registers cannot be
* accessed properly by the s/w toggle the LANPHYPC value to power cycle
* the PHY.
+ * On i217, setup Intel Rapid Start Technology.
**/
void e1000_resume_workarounds_pchlan(struct e1000_hw *hw)
{
- u16 phy_id1, phy_id2;
s32 ret_val;
DEBUGFUNC("e1000_resume_workarounds_pchlan");
- if ((hw->mac.type != e1000_pch2lan) ||
- hw->phy.ops.check_reset_block(hw))
+ if (hw->mac.type < e1000_pch2lan)
return;
- ret_val = hw->phy.ops.acquire(hw);
+ ret_val = e1000_init_phy_workarounds_pchlan(hw);
if (ret_val) {
- DEBUGOUT("Failed to acquire PHY semaphore in resume\n");
+ DEBUGOUT1("Failed to init PHY flow ret_val=%d\n", ret_val);
return;
}
- /* Test access to the PHY registers by reading the ID regs */
- ret_val = hw->phy.ops.read_reg_locked(hw, PHY_ID1, &phy_id1);
- if (ret_val)
- goto release;
- ret_val = hw->phy.ops.read_reg_locked(hw, PHY_ID2, &phy_id2);
- if (ret_val)
- goto release;
+ /* For i217 Intel Rapid Start Technology support when the system
+ * is transitioning from Sx and no manageability engine is present
+ * configure SMBus to restore on reset, disable proxy, and enable
+ * the reset on MTA (Multicast table array).
+ */
+ if (hw->phy.type == e1000_phy_i217) {
+ u16 phy_reg;
- if (hw->phy.id == ((u32)(phy_id1 << 16) |
- (u32)(phy_id2 & PHY_REVISION_MASK)))
- goto release;
+ ret_val = hw->phy.ops.acquire(hw);
+ if (ret_val) {
+ DEBUGOUT("Failed to setup iRST\n");
+ return;
+ }
- e1000_toggle_lanphypc_value_ich8lan(hw);
+ if (!(E1000_READ_REG(hw, E1000_FWSM) &
+ E1000_ICH_FWSM_FW_VALID)) {
+ /* Restore clear on SMB if no manageability engine
+ * is present
+ */
+ ret_val = hw->phy.ops.read_reg_locked(hw, I217_MEMPWR,
+ &phy_reg);
+ if (ret_val)
+ goto release;
+ phy_reg |= I217_MEMPWR_DISABLE_SMB_RELEASE;
+ hw->phy.ops.write_reg_locked(hw, I217_MEMPWR, phy_reg);
- hw->phy.ops.release(hw);
- msec_delay(50);
- hw->phy.ops.reset(hw);
- msec_delay(50);
- return;
-
+ /* Disable Proxy */
+ hw->phy.ops.write_reg_locked(hw, I217_PROXY_CTRL, 0);
+ }
+ /* Enable reset on MTA */
+ ret_val = hw->phy.ops.read_reg_locked(hw, I217_CGFREG,
+ &phy_reg);
+ if (ret_val)
+ goto release;
+ phy_reg &= ~I217_CGFREG_ENABLE_MTA_RESET;
+ hw->phy.ops.write_reg_locked(hw, I217_CGFREG, phy_reg);
release:
- hw->phy.ops.release(hw);
-
- return;
+ if (ret_val)
+ DEBUGOUT1("Error %d in resume workarounds\n", ret_val);
+ hw->phy.ops.release(hw);
+ }
}
/**
@@ -4091,8 +4738,7 @@
DEBUGFUNC("e1000_led_on_pchlan");
- /*
- * If no link, then turn LED on by setting the invert bit
+ /* If no link, then turn LED on by setting the invert bit
* for each LED that's mode is "link_up" in ledctl_mode2.
*/
if (!(E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU)) {
@@ -4124,8 +4770,7 @@
DEBUGFUNC("e1000_led_off_pchlan");
- /*
- * If no link, then turn LED off by clearing the invert bit
+ /* If no link, then turn LED off by clearing the invert bit
* for each LED that's mode is "link_up" in ledctl_mode1.
*/
if (!(E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU)) {
@@ -4172,8 +4817,7 @@
} else {
ret_val = e1000_get_auto_rd_done_generic(hw);
if (ret_val) {
- /*
- * When auto config read does not complete, do not
+ /* When auto config read does not complete, do not
* return with an error. This can happen in situations
* where there is no eeprom and prevents getting link.
*/
@@ -4191,7 +4835,7 @@
/* If EEPROM is not marked present, init the IGP 3 PHY manually */
if (hw->mac.type <= e1000_ich9lan) {
- if (((E1000_READ_REG(hw, E1000_EECD) & E1000_EECD_PRES) == 0) &&
+ if (!(E1000_READ_REG(hw, E1000_EECD) & E1000_EECD_PRES) &&
(hw->phy.type == e1000_phy_igp_3)) {
e1000_phy_init_script_igp3(hw);
}
@@ -4256,6 +4900,7 @@
/* Clear PHY statistics registers */
if ((hw->phy.type == e1000_phy_82578) ||
(hw->phy.type == e1000_phy_82579) ||
+ (hw->phy.type == e1000_phy_i217) ||
(hw->phy.type == e1000_phy_82577)) {
ret_val = hw->phy.ops.acquire(hw);
if (ret_val)
Property changes on: trunk/sys/dev/e1000/e1000_ich8lan.c
___________________________________________________________________
Deleted: cvs2svn:cvs-rev
## -1 +0,0 ##
-1.4
\ No newline at end of property
Modified: trunk/sys/dev/e1000/e1000_ich8lan.h
===================================================================
--- trunk/sys/dev/e1000/e1000_ich8lan.h 2013-12-28 14:30:04 UTC (rev 6559)
+++ trunk/sys/dev/e1000/e1000_ich8lan.h 2013-12-28 14:30:47 UTC (rev 6560)
@@ -1,6 +1,7 @@
+/* $MidnightBSD$ */
/******************************************************************************
- Copyright (c) 2001-2011, Intel Corporation
+ Copyright (c) 2001-2013, Intel Corporation
All rights reserved.
Redistribution and use in source and binary forms, with or without
@@ -30,7 +31,7 @@
POSSIBILITY OF SUCH DAMAGE.
******************************************************************************/
-/*$MidnightBSD$*/
+/*$FreeBSD: release/9.2.0/sys/dev/e1000/e1000_ich8lan.h 248292 2013-03-14 22:55:59Z jfv $*/
#ifndef _E1000_ICH8LAN_H_
#define _E1000_ICH8LAN_H_
@@ -59,12 +60,8 @@
#define ICH_FLASH_SEG_SIZE_4K 4096
#define ICH_FLASH_SEG_SIZE_8K 8192
#define ICH_FLASH_SEG_SIZE_64K 65536
-#define ICH_FLASH_SECTOR_SIZE 4096
-#define ICH_FLASH_REG_MAPSIZE 0x00A0
-
#define E1000_ICH_FWSM_RSPCIPHY 0x00000040 /* Reset PHY on PCI Reset */
-#define E1000_ICH_FWSM_DISSW 0x10000000 /* FW Disables SW Writes */
/* FW established a valid mode */
#define E1000_ICH_FWSM_FW_VALID 0x00008000
#define E1000_ICH_FWSM_PCIM2PCI 0x01000000 /* ME PCIm-to-PCI active */
@@ -72,24 +69,13 @@
#define E1000_ICH_MNG_IAMT_MODE 0x2
-#define E1000_FWSM_PROXY_MODE 0x00000008 /* FW is in proxy mode */
-#define E1000_FWSM_MEMC 0x00000010 /* ME Messaging capable */
+#define E1000_FWSM_WLOCK_MAC_MASK 0x0380
+#define E1000_FWSM_WLOCK_MAC_SHIFT 7
/* Shared Receive Address Registers */
-#define E1000_SHRAL(_i) (0x05438 + ((_i) * 8))
-#define E1000_SHRAH(_i) (0x0543C + ((_i) * 8))
-#define E1000_SHRAH_AV 0x80000000 /* Addr Valid bit */
-#define E1000_SHRAH_MAV 0x40000000 /* Multicast Addr Valid bit */
+#define E1000_SHRAL_PCH_LPT(_i) (0x05408 + ((_i) * 8))
+#define E1000_SHRAH_PCH_LPT(_i) (0x0540C + ((_i) * 8))
-#define E1000_H2ME 0x05B50 /* Host to ME */
-#define E1000_H2ME_LSECREQ 0x00000001 /* Linksec Request */
-#define E1000_H2ME_LSECA 0x00000002 /* Linksec Active */
-#define E1000_H2ME_LSECSF 0x00000004 /* Linksec Failed */
-#define E1000_H2ME_LSECD 0x00000008 /* Linksec Disabled */
-#define E1000_H2ME_SLCAPD 0x00000010 /* Start LCAPD */
-#define E1000_H2ME_IPV4_ARP_EN 0x00000020 /* Arp Offload enable bit */
-#define E1000_H2ME_IPV6_NS_EN 0x00000040 /* NS Offload enable bit */
-
#define ID_LED_DEFAULT_ICH8LAN ((ID_LED_DEF1_DEF2 << 12) | \
(ID_LED_OFF1_OFF2 << 8) | \
(ID_LED_OFF1_ON2 << 4) | \
@@ -105,14 +91,20 @@
#define E1000_FEXTNVM_SW_CONFIG 1
#define E1000_FEXTNVM_SW_CONFIG_ICH8M (1 << 27) /* Bit redefined for ICH8M */
+#define E1000_FEXTNVM3_PHY_CFG_COUNTER_MASK 0x0C000000
+#define E1000_FEXTNVM3_PHY_CFG_COUNTER_50MSEC 0x08000000
+
#define E1000_FEXTNVM4_BEACON_DURATION_MASK 0x7
#define E1000_FEXTNVM4_BEACON_DURATION_8USEC 0x7
#define E1000_FEXTNVM4_BEACON_DURATION_16USEC 0x3
+#define E1000_FEXTNVM6_REQ_PLL_CLK 0x00000100
+
#define PCIE_ICH8_SNOOP_ALL PCIE_NO_SNOOP_ALL
#define E1000_ICH_RAR_ENTRIES 7
#define E1000_PCH2_RAR_ENTRIES 5 /* RAR[0], SHRA[0-3] */
+#define E1000_PCH_LPT_RAR_ENTRIES 12 /* RAR[0], SHRA[0-10] */
#define PHY_PAGE_SHIFT 5
#define PHY_REG(page, reg) (((page) << PHY_PAGE_SHIFT) | \
@@ -119,13 +111,10 @@
((reg) & MAX_PHY_REG_ADDRESS))
#define IGP3_KMRN_DIAG PHY_REG(770, 19) /* KMRN Diagnostic */
#define IGP3_VR_CTRL PHY_REG(776, 18) /* Voltage Regulator Control */
-#define IGP3_CAPABILITY PHY_REG(776, 19) /* Capability */
-#define IGP3_PM_CTRL PHY_REG(769, 20) /* Power Management Control */
#define IGP3_KMRN_DIAG_PCS_LOCK_LOSS 0x0002
#define IGP3_VR_CTRL_DEV_POWERDOWN_MODE_MASK 0x0300
#define IGP3_VR_CTRL_MODE_SHUTDOWN 0x0200
-#define IGP3_PM_CTRL_FORCE_PWR_DOWN 0x0020
/* PHY Wakeup Registers and defines */
#define BM_PORT_GEN_CFG PHY_REG(BM_PORT_CTRL_PAGE, 17)
@@ -138,15 +127,7 @@
#define BM_RAR_H(_i) (BM_PHY_REG(BM_WUC_PAGE, 18 + ((_i) << 2)))
#define BM_RAR_CTRL(_i) (BM_PHY_REG(BM_WUC_PAGE, 19 + ((_i) << 2)))
#define BM_MTA(_i) (BM_PHY_REG(BM_WUC_PAGE, 128 + ((_i) << 1)))
-#define BM_IPAV (BM_PHY_REG(BM_WUC_PAGE, 64))
-#define BM_IP4AT_L(_i) (BM_PHY_REG(BM_WUC_PAGE, 82 + ((_i) * 2)))
-#define BM_IP4AT_H(_i) (BM_PHY_REG(BM_WUC_PAGE, 83 + ((_i) * 2)))
-#define BM_SHRAL_LOWER(_i) (BM_PHY_REG(BM_WUC_PAGE, 44 + ((_i) * 4)))
-#define BM_SHRAL_UPPER(_i) (BM_PHY_REG(BM_WUC_PAGE, 45 + ((_i) * 4)))
-#define BM_SHRAH_LOWER(_i) (BM_PHY_REG(BM_WUC_PAGE, 46 + ((_i) * 4)))
-#define BM_SHRAH_UPPER(_i) (BM_PHY_REG(BM_WUC_PAGE, 47 + ((_i) * 4)))
-
#define BM_RCTL_UPE 0x0001 /* Unicast Promiscuous Mode */
#define BM_RCTL_MPE 0x0002 /* Multicast Promiscuous Mode */
#define BM_RCTL_MO_SHIFT 3 /* Multicast Offset Shift */
@@ -177,28 +158,28 @@
#define E1000_FCRTV_PCH 0x05F40 /* PCH Flow Control Refresh Timer Value */
-/*
- * For ICH, the name used for NVM word 17h is LED1 Config.
- * For PCH, the word was re-named to OEM Config.
- */
-#define E1000_NVM_LED1_CONFIG 0x17 /* NVM LED1/LPLU Config Word */
-#define E1000_NVM_LED1_CONFIG_LPLU_NONDOA 0x0400 /* NVM LPLU in non-D0a Bit */
-#define E1000_NVM_OEM_CONFIG E1000_NVM_LED1_CONFIG
-#define E1000_NVM_OEM_CONFIG_LPLU_NONDOA E1000_NVM_LED1_CONFIG_LPLU_NONDOA
-
#define E1000_NVM_K1_CONFIG 0x1B /* NVM K1 Config Word */
#define E1000_NVM_K1_ENABLE 0x1 /* NVM Enable K1 bit */
+/* SMBus Control Phy Register */
+#define CV_SMB_CTRL PHY_REG(769, 23)
+#define CV_SMB_CTRL_FORCE_SMBUS 0x0001
+
/* SMBus Address Phy Register */
#define HV_SMB_ADDR PHY_REG(768, 26)
#define HV_SMB_ADDR_MASK 0x007F
#define HV_SMB_ADDR_PEC_EN 0x0200
#define HV_SMB_ADDR_VALID 0x0080
+#define HV_SMB_ADDR_FREQ_MASK 0x1100
+#define HV_SMB_ADDR_FREQ_LOW_SHIFT 8
+#define HV_SMB_ADDR_FREQ_HIGH_SHIFT 12
/* Strapping Option Register - RO */
#define E1000_STRAP 0x0000C
#define E1000_STRAP_SMBUS_ADDRESS_MASK 0x00FE0000
#define E1000_STRAP_SMBUS_ADDRESS_SHIFT 17
+#define E1000_STRAP_SMT_FREQ_MASK 0x00003000
+#define E1000_STRAP_SMT_FREQ_SHIFT 12
/* OEM Bits Phy Register */
#define HV_OEM_BITS PHY_REG(768, 25)
@@ -206,8 +187,6 @@
#define HV_OEM_BITS_GBE_DIS 0x0040 /* Gigabit Disable */
#define HV_OEM_BITS_RESTART_AN 0x0400 /* Restart Auto-negotiation */
-#define LCD_CFG_PHY_ADDR_BIT 0x0020 /* Phy addr bit from LCD Config word */
-
/* KMRN Mode Control */
#define HV_KMRN_MODE_CTRL PHY_REG(769, 16)
#define HV_KMRN_MDIO_SLOW 0x0400
@@ -219,47 +198,73 @@
/* PHY Power Management Control */
#define HV_PM_CTRL PHY_REG(770, 17)
+#define HV_PM_CTRL_PLL_STOP_IN_K1_GIGA 0x100
#define SW_FLAG_TIMEOUT 1000 /* SW Semaphore flag timeout in ms */
/* PHY Low Power Idle Control */
#define I82579_LPI_CTRL PHY_REG(772, 20)
+#define I82579_LPI_CTRL_100_ENABLE 0x2000
+#define I82579_LPI_CTRL_1000_ENABLE 0x4000
#define I82579_LPI_CTRL_ENABLE_MASK 0x6000
#define I82579_LPI_CTRL_FORCE_PLL_LOCK_COUNT 0x80
-/* EMI Registers */
+/* Extended Management Interface (EMI) Registers */
#define I82579_EMI_ADDR 0x10
#define I82579_EMI_DATA 0x11
#define I82579_LPI_UPDATE_TIMER 0x4805 /* in 40ns units + 40 ns base value */
-#define I82579_MSE_THRESHOLD 0x084F /* Mean Square Error Threshold */
+#define I82579_MSE_THRESHOLD 0x084F /* 82579 Mean Square Error Threshold */
+#define I82577_MSE_THRESHOLD 0x0887 /* 82577 Mean Square Error Threshold */
#define I82579_MSE_LINK_DOWN 0x2411 /* MSE count before dropping link */
+#define I82579_RX_CONFIG 0x3412 /* Receive configuration */
+#define I82579_EEE_PCS_STATUS 0x182D /* IEEE MMD Register 3.1 >> 8 */
+#define I82579_EEE_CAPABILITY 0x0410 /* IEEE MMD Register 3.20 */
+#define I82579_EEE_ADVERTISEMENT 0x040E /* IEEE MMD Register 7.60 */
+#define I82579_EEE_LP_ABILITY 0x040F /* IEEE MMD Register 7.61 */
+#define I82579_EEE_100_SUPPORTED (1 << 1) /* 100BaseTx EEE supported */
+#define I82579_EEE_1000_SUPPORTED (1 << 2) /* 1000BaseTx EEE supported */
+#define I217_EEE_PCS_STATUS 0x9401 /* IEEE MMD Register 3.1 */
+#define I217_EEE_CAPABILITY 0x8000 /* IEEE MMD Register 3.20 */
+#define I217_EEE_ADVERTISEMENT 0x8001 /* IEEE MMD Register 7.60 */
+#define I217_EEE_LP_ABILITY 0x8002 /* IEEE MMD Register 7.61 */
-/*
- * Additional interrupts need to be handled for ICH family:
- * DSW = The FW changed the status of the DISSW bit in FWSM
- * PHYINT = The LAN connected device generates an interrupt
- * EPRST = Manageability reset event
- */
-#define IMS_ICH_ENABLE_MASK (\
- E1000_IMS_DSW | \
- E1000_IMS_PHYINT | \
- E1000_IMS_EPRST)
+#define E1000_EEE_RX_LPI_RCVD 0x0400 /* Tx LP idle received */
+#define E1000_EEE_TX_LPI_RCVD 0x0800 /* Rx LP idle received */
-/* Additional interrupt register bit definitions */
-#define E1000_ICR_LSECPNC 0x00004000 /* PN threshold - client */
-#define E1000_IMS_LSECPNC E1000_ICR_LSECPNC /* PN threshold - client */
-#define E1000_ICS_LSECPNC E1000_ICR_LSECPNC /* PN threshold - client */
+/* Intel Rapid Start Technology Support */
+#define I217_PROXY_CTRL BM_PHY_REG(BM_WUC_PAGE, 70)
+#define I217_PROXY_CTRL_AUTO_DISABLE 0x0080
+#define I217_SxCTRL PHY_REG(BM_PORT_CTRL_PAGE, 28)
+#define I217_SxCTRL_ENABLE_LPI_RESET 0x1000
+#define I217_CGFREG PHY_REG(772, 29)
+#define I217_CGFREG_ENABLE_MTA_RESET 0x0002
+#define I217_MEMPWR PHY_REG(772, 26)
+#define I217_MEMPWR_DISABLE_SMB_RELEASE 0x0010
-/* Security Processing bit Indication */
-#define E1000_RXDEXT_LINKSEC_STATUS_LSECH 0x01000000
-#define E1000_RXDEXT_LINKSEC_ERROR_BIT_MASK 0x60000000
-#define E1000_RXDEXT_LINKSEC_ERROR_NO_SA_MATCH 0x20000000
-#define E1000_RXDEXT_LINKSEC_ERROR_REPLAY_ERROR 0x40000000
-#define E1000_RXDEXT_LINKSEC_ERROR_BAD_SIG 0x60000000
-
/* Receive Address Initial CRC Calculation */
#define E1000_PCH_RAICC(_n) (0x05F50 + ((_n) * 4))
+/* Latency Tolerance Reporting */
+#define E1000_LTRV 0x000F8
+#define E1000_LTRV_VALUE_MASK 0x000003FF
+#define E1000_LTRV_SCALE_MAX 5
+#define E1000_LTRV_SCALE_FACTOR 5
+#define E1000_LTRV_SCALE_SHIFT 10
+#define E1000_LTRV_SCALE_MASK 0x00001C00
+#define E1000_LTRV_REQ_SHIFT 15
+#define E1000_LTRV_NOSNOOP_SHIFT 16
+#define E1000_LTRV_SEND (1 << 30)
+
+/* Proprietary Latency Tolerance Reporting PCI Capability */
+#define E1000_PCI_LTR_CAP_LPT 0xA8
+
+/* OBFF Control & Threshold Defines */
+#define E1000_SVCR_OFF_EN 0x00000001
+#define E1000_SVCR_OFF_MASKINT 0x00001000
+#define E1000_SVCR_OFF_TIMER_MASK 0xFFFF0000
+#define E1000_SVCR_OFF_TIMER_SHIFT 16
+#define E1000_SVT_OFF_HWM_MASK 0x0000001F
+
void e1000_set_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw,
bool state);
void e1000_igp3_phy_powerdown_workaround_ich8lan(struct e1000_hw *hw);
@@ -269,4 +274,5 @@
s32 e1000_configure_k1_ich8lan(struct e1000_hw *hw, bool k1_enable);
void e1000_copy_rx_addrs_to_phy_ich8lan(struct e1000_hw *hw);
s32 e1000_lv_jumbo_workaround_ich8lan(struct e1000_hw *hw, bool enable);
-#endif
+s32 e1000_read_emi_reg_locked(struct e1000_hw *hw, u16 addr, u16 *data);
+#endif /* _E1000_ICH8LAN_H_ */
Property changes on: trunk/sys/dev/e1000/e1000_ich8lan.h
___________________________________________________________________
Deleted: cvs2svn:cvs-rev
## -1 +0,0 ##
-1.4
\ No newline at end of property
Modified: trunk/sys/dev/e1000/e1000_mac.c
===================================================================
--- trunk/sys/dev/e1000/e1000_mac.c 2013-12-28 14:30:04 UTC (rev 6559)
+++ trunk/sys/dev/e1000/e1000_mac.c 2013-12-28 14:30:47 UTC (rev 6560)
@@ -1,6 +1,7 @@
+/* $MidnightBSD$ */
/******************************************************************************
- Copyright (c) 2001-2012, Intel Corporation
+ Copyright (c) 2001-2013, Intel Corporation
All rights reserved.
Redistribution and use in source and binary forms, with or without
@@ -30,7 +31,7 @@
POSSIBILITY OF SUCH DAMAGE.
******************************************************************************/
-/*$MidnightBSD$*/
+/*$FreeBSD: release/9.2.0/sys/dev/e1000/e1000_mac.c 248292 2013-03-14 22:55:59Z jfv $*/
#include "e1000_api.h"
@@ -70,12 +71,9 @@
mac->ops.setup_link = e1000_null_ops_generic;
mac->ops.get_link_up_info = e1000_null_link_info;
mac->ops.check_for_link = e1000_null_ops_generic;
- mac->ops.wait_autoneg = e1000_wait_autoneg_generic;
+ mac->ops.set_obff_timer = e1000_null_set_obff_timer;
/* Management */
mac->ops.check_mng_mode = e1000_null_mng_mode;
- mac->ops.mng_host_if_write = e1000_mng_host_if_write_generic;
- mac->ops.mng_write_cmd_header = e1000_mng_write_cmd_header_generic;
- mac->ops.mng_enable_host_if = e1000_mng_enable_host_if_generic;
/* VLAN, MC, etc. */
mac->ops.update_mc_addr_list = e1000_null_update_mc;
mac->ops.clear_vfta = e1000_null_mac_generic;
@@ -118,8 +116,7 @@
* e1000_null_mng_mode - No-op function, return FALSE
* @hw: pointer to the HW structure
**/
-bool e1000_null_mng_mode(struct e1000_hw *hw)
-{
+bool e1000_null_mng_mode(struct e1000_hw *hw) {
DEBUGFUNC("e1000_null_mng_mode");
return FALSE;
}
@@ -155,6 +152,16 @@
}
/**
+ * e1000_null_set_obff_timer - No-op function, return 0
+ * @hw: pointer to the HW structure
+ **/
+s32 e1000_null_set_obff_timer(struct e1000_hw *hw, u32 a)
+{
+ DEBUGFUNC("e1000_null_set_obff_timer");
+ return E1000_SUCCESS;
+}
+
+/**
* e1000_get_bus_info_pci_generic - Get PCI(x) bus information
* @hw: pointer to the HW structure
*
@@ -268,8 +275,7 @@
struct e1000_bus_info *bus = &hw->bus;
u32 reg;
- /*
- * The status register reports the correct function number
+ /* The status register reports the correct function number
* for the device regardless of function swap state.
*/
reg = E1000_READ_REG(hw, E1000_STATUS);
@@ -389,7 +395,7 @@
s32 e1000_check_alt_mac_addr_generic(struct e1000_hw *hw)
{
u32 i;
- s32 ret_val = E1000_SUCCESS;
+ s32 ret_val;
u16 offset, nvm_alt_mac_addr_offset, nvm_data;
u8 alt_mac_addr[ETH_ADDR_LEN];
@@ -403,8 +409,7 @@
if ((hw->mac.type < e1000_82571) || (hw->mac.type == e1000_82573))
return E1000_SUCCESS;
- /*
- * Alternate MAC address is handled by the option ROM for 82580
+ /* Alternate MAC address is handled by the option ROM for 82580
* and newer. SW support not required.
*/
if (hw->mac.type >= e1000_82580)
@@ -447,8 +452,7 @@
return E1000_SUCCESS;
}
- /*
- * We have a valid alternate MAC address, and we want to treat it the
+ /* We have a valid alternate MAC address, and we want to treat it the
* same as the normal permanent MAC address stored by the HW into the
* RAR. Do this by mapping this address into RAR0.
*/
@@ -472,8 +476,7 @@
DEBUGFUNC("e1000_rar_set_generic");
- /*
- * HW expects these in little endian so we reverse the byte order
+ /* HW expects these in little endian so we reverse the byte order
* from network order (big endian) to little endian
*/
rar_low = ((u32) addr[0] | ((u32) addr[1] << 8) |
@@ -485,8 +488,7 @@
if (rar_low || rar_high)
rar_high |= E1000_RAH_AV;
- /*
- * Some bridges will combine consecutive 32-bit writes into
+ /* Some bridges will combine consecutive 32-bit writes into
* a single burst write, which will malfunction on some parts.
* The flushes avoid this.
*/
@@ -514,15 +516,13 @@
/* Register count multiplied by bits per register */
hash_mask = (hw->mac.mta_reg_count * 32) - 1;
- /*
- * For a mc_filter_type of 0, bit_shift is the number of left-shifts
+ /* For a mc_filter_type of 0, bit_shift is the number of left-shifts
* where 0xFF would still fall within the hash mask.
*/
while (hash_mask >> bit_shift != 0xFF)
bit_shift++;
- /*
- * The portion of the address that is used for the hash table
+ /* The portion of the address that is used for the hash table
* is determined by the mc_filter_type setting.
* The algorithm is such that there is a total of 8 bits of shifting.
* The bit_shift for a mc_filter_type of 0 represents the number of
@@ -707,8 +707,7 @@
DEBUGFUNC("e1000_check_for_copper_link");
- /*
- * We only want to go out to the PHY registers to see if Auto-Neg
+ /* We only want to go out to the PHY registers to see if Auto-Neg
* has completed and/or if our link status has changed. The
* get_link_status flag is set upon receiving a Link Status
* Change or Rx Sequence Error interrupt.
@@ -716,8 +715,7 @@
if (!mac->get_link_status)
return E1000_SUCCESS;
- /*
- * First we want to see if the MII Status Register reports
+ /* First we want to see if the MII Status Register reports
* link. If so, then we want to get the current speed/duplex
* of the PHY.
*/
@@ -730,28 +728,24 @@
mac->get_link_status = FALSE;
- /*
- * Check if there was DownShift, must be checked
+ /* Check if there was DownShift, must be checked
* immediately after link-up
*/
e1000_check_downshift_generic(hw);
- /*
- * If we are forcing speed/duplex, then we simply return since
+ /* If we are forcing speed/duplex, then we simply return since
* we have already determined whether we have link or not.
*/
if (!mac->autoneg)
return -E1000_ERR_CONFIG;
- /*
- * Auto-Neg is enabled. Auto Speed Detection takes care
+ /* Auto-Neg is enabled. Auto Speed Detection takes care
* of MAC speed/duplex configuration. So we only need to
* configure Collision Distance in the MAC.
*/
mac->ops.config_collision_dist(hw);
- /*
- * Configure Flow Control now that Auto-Neg has completed.
+ /* Configure Flow Control now that Auto-Neg has completed.
* First, we need to restore the desired flow control
* settings because we may have had to re-autoneg with a
* different link partner.
@@ -784,8 +778,7 @@
status = E1000_READ_REG(hw, E1000_STATUS);
rxcw = E1000_READ_REG(hw, E1000_RXCW);
- /*
- * If we don't have link (auto-negotiation failed or link partner
+ /* If we don't have link (auto-negotiation failed or link partner
* cannot auto-negotiate), the cable is plugged in (we have signal),
* and our link partner is not trying to auto-negotiate with us (we
* are receiving idles or data), we need to force link up. We also
@@ -816,8 +809,7 @@
return ret_val;
}
} else if ((ctrl & E1000_CTRL_SLU) && (rxcw & E1000_RXCW_C)) {
- /*
- * If we are forcing link and we are receiving /C/ ordered
+ /* If we are forcing link and we are receiving /C/ ordered
* sets, re-enable auto-negotiation in the TXCW register
* and disable forced link in the Device Control register
* in an attempt to auto-negotiate with our link partner.
@@ -853,8 +845,7 @@
status = E1000_READ_REG(hw, E1000_STATUS);
rxcw = E1000_READ_REG(hw, E1000_RXCW);
- /*
- * If we don't have link (auto-negotiation failed or link partner
+ /* If we don't have link (auto-negotiation failed or link partner
* cannot auto-negotiate), and our link partner is not trying to
* auto-negotiate with us (we are receiving idles or data),
* we need to force link up. We also need to give auto-negotiation
@@ -883,8 +874,7 @@
return ret_val;
}
} else if ((ctrl & E1000_CTRL_SLU) && (rxcw & E1000_RXCW_C)) {
- /*
- * If we are forcing link and we are receiving /C/ ordered
+ /* If we are forcing link and we are receiving /C/ ordered
* sets, re-enable auto-negotiation in the TXCW register
* and disable forced link in the Device Control register
* in an attempt to auto-negotiate with our link partner.
@@ -895,8 +885,7 @@
mac->serdes_has_link = TRUE;
} else if (!(E1000_TXCW_ANE & E1000_READ_REG(hw, E1000_TXCW))) {
- /*
- * If we force link for non-auto-negotiation switch, check
+ /* If we force link for non-auto-negotiation switch, check
* link status based on MAC synchronization for internal
* serdes media type.
*/
@@ -955,8 +944,7 @@
DEBUGFUNC("e1000_set_default_fc_generic");
- /*
- * Read and store word 0x0F of the EEPROM. This word contains bits
+ /* Read and store word 0x0F of the EEPROM. This word contains bits
* that determine the hardware's default PAUSE (flow control) mode,
* a bit that determines whether the HW defaults to enabling or
* disabling auto-negotiation, and the direction of the
@@ -998,15 +986,13 @@
DEBUGFUNC("e1000_setup_link_generic");
- /*
- * In the case of the phy reset being blocked, we already have a link.
+ /* In the case of the phy reset being blocked, we already have a link.
* We do not need to set it up again.
*/
if (hw->phy.ops.check_reset_block && hw->phy.ops.check_reset_block(hw))
return E1000_SUCCESS;
- /*
- * If requested flow control is set to default, set flow control
+ /* If requested flow control is set to default, set flow control
* based on the EEPROM flow control settings.
*/
if (hw->fc.requested_mode == e1000_fc_default) {
@@ -1015,8 +1001,7 @@
return ret_val;
}
- /*
- * Save off the requested flow control mode for use later. Depending
+ /* Save off the requested flow control mode for use later. Depending
* on the link partner's capabilities, we may or may not use this mode.
*/
hw->fc.current_mode = hw->fc.requested_mode;
@@ -1029,8 +1014,7 @@
if (ret_val)
return ret_val;
- /*
- * Initialize the flow control address, type, and PAUSE timer
+ /* Initialize the flow control address, type, and PAUSE timer
* registers to their default values. This is done even if flow
* control is disabled, because it does not hurt anything to
* initialize these registers.
@@ -1059,8 +1043,7 @@
DEBUGFUNC("e1000_commit_fc_settings_generic");
- /*
- * Check for a software override of the flow control settings, and
+ /* Check for a software override of the flow control settings, and
* setup the device accordingly. If auto-negotiation is enabled, then
* software will have to set the "PAUSE" bits to the correct value in
* the Transmit Config Word Register (TXCW) and re-start auto-
@@ -1082,8 +1065,7 @@
txcw = (E1000_TXCW_ANE | E1000_TXCW_FD);
break;
case e1000_fc_rx_pause:
- /*
- * Rx Flow control is enabled and Tx Flow control is disabled
+ /* Rx Flow control is enabled and Tx Flow control is disabled
* by a software over-ride. Since there really isn't a way to
* advertise that we are capable of Rx Pause ONLY, we will
* advertise that we support both symmetric and asymmetric Rx
@@ -1093,15 +1075,13 @@
txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_PAUSE_MASK);
break;
case e1000_fc_tx_pause:
- /*
- * Tx Flow control is enabled, and Rx Flow control is disabled,
+ /* Tx Flow control is enabled, and Rx Flow control is disabled,
* by a software over-ride.
*/
txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_ASM_DIR);
break;
case e1000_fc_full:
- /*
- * Flow control (both Rx and Tx) is enabled by a software
+ /* Flow control (both Rx and Tx) is enabled by a software
* over-ride.
*/
txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_PAUSE_MASK);
@@ -1133,8 +1113,7 @@
DEBUGFUNC("e1000_poll_fiber_serdes_link_generic");
- /*
- * If we have a signal (the cable is plugged in, or assumed TRUE for
+ /* If we have a signal (the cable is plugged in, or assumed TRUE for
* serdes media) then poll for a "Link-Up" indication in the Device
* Status Register. Time-out if a link isn't seen in 500 milliseconds
* seconds (Auto-negotiation should complete in less than 500
@@ -1149,8 +1128,7 @@
if (i == FIBER_LINK_UP_LIMIT) {
DEBUGOUT("Never got a valid link from auto-neg!!!\n");
mac->autoneg_failed = TRUE;
- /*
- * AutoNeg failed to achieve a link, so we'll call
+ /* AutoNeg failed to achieve a link, so we'll call
* mac->check_for_link. This routine will force the
* link up if we detect a signal. This will allow us to
* communicate with non-autonegotiating link partners.
@@ -1194,8 +1172,7 @@
if (ret_val)
return ret_val;
- /*
- * Since auto-negotiation is enabled, take the link out of reset (the
+ /* Since auto-negotiation is enabled, take the link out of reset (the
* link will be in reset, because we previously reset the chip). This
* will restart auto-negotiation. If auto-negotiation is successful
* then the link-up status bit will be set and the flow control enable
@@ -1207,8 +1184,7 @@
E1000_WRITE_FLUSH(hw);
msec_delay(1);
- /*
- * For these adapters, the SW definable pin 1 is set when the optics
+ /* For these adapters, the SW definable pin 1 is set when the optics
* detect a signal. If we have a signal, then poll for a "Link-Up"
* indication.
*/
@@ -1258,8 +1234,7 @@
DEBUGFUNC("e1000_set_fc_watermarks_generic");
- /*
- * Set the flow control receive threshold registers. Normally,
+ /* Set the flow control receive threshold registers. Normally,
* these registers will be set to a default threshold that may be
* adjusted later by the driver's runtime code. However, if the
* ability to transmit pause frames is not enabled, then these
@@ -1266,8 +1241,7 @@
* registers will be set to 0.
*/
if (hw->fc.current_mode & e1000_fc_tx_pause) {
- /*
- * We need to set up the Receive Threshold high and low water
+ /* We need to set up the Receive Threshold high and low water
* marks as well as (optionally) enabling the transmission of
* XON frames.
*/
@@ -1301,8 +1275,7 @@
ctrl = E1000_READ_REG(hw, E1000_CTRL);
- /*
- * Because we didn't get link via the internal auto-negotiation
+ /* Because we didn't get link via the internal auto-negotiation
* mechanism (we either forced link or we got link via PHY
* auto-neg), we have to manually enable/disable transmit an
* receive flow control.
@@ -1360,13 +1333,13 @@
{
struct e1000_mac_info *mac = &hw->mac;
s32 ret_val = E1000_SUCCESS;
+ u32 pcs_status_reg, pcs_adv_reg, pcs_lp_ability_reg, pcs_ctrl_reg;
u16 mii_status_reg, mii_nway_adv_reg, mii_nway_lp_ability_reg;
u16 speed, duplex;
DEBUGFUNC("e1000_config_fc_after_link_up_generic");
- /*
- * Check for the case where we have fiber media and auto-neg failed
+ /* Check for the case where we have fiber media and auto-neg failed
* so we had to force link. In this case, we need to force the
* configuration of the MAC to match the "fc" parameter.
*/
@@ -1384,15 +1357,13 @@
return ret_val;
}
- /*
- * Check for the case where we have copper media and auto-neg is
+ /* Check for the case where we have copper media and auto-neg is
* enabled. In this case, we need to check and see if Auto-Neg
* has completed, and if so, how the PHY and link partner has
* flow control configured.
*/
if ((hw->phy.media_type == e1000_media_type_copper) && mac->autoneg) {
- /*
- * Read the MII Status Register and check to see if AutoNeg
+ /* Read the MII Status Register and check to see if AutoNeg
* has completed. We read this twice because this reg has
* some "sticky" (latched) bits.
*/
@@ -1408,8 +1379,7 @@
return ret_val;
}
- /*
- * The AutoNeg process has completed, so we now need to
+ /* The AutoNeg process has completed, so we now need to
* read both the Auto Negotiation Advertisement
* Register (Address 4) and the Auto_Negotiation Base
* Page Ability Register (Address 5) to determine how
@@ -1424,8 +1394,7 @@
if (ret_val)
return ret_val;
- /*
- * Two bits in the Auto Negotiation Advertisement Register
+ /* Two bits in the Auto Negotiation Advertisement Register
* (Address 4) and two bits in the Auto Negotiation Base
* Page Ability Register (Address 5) determine flow control
* for both the PHY and the link partner. The following
@@ -1460,8 +1429,7 @@
*/
if ((mii_nway_adv_reg & NWAY_AR_PAUSE) &&
(mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE)) {
- /*
- * Now we need to check if the user selected Rx ONLY
+ /* Now we need to check if the user selected Rx ONLY
* of pause frames. In this case, we had to advertise
* FULL flow control because we could not advertise Rx
* ONLY. Hence, we must now check to see if we need to
@@ -1475,8 +1443,7 @@
DEBUGOUT("Flow Control = Rx PAUSE frames only.\n");
}
}
- /*
- * For receiving PAUSE frames ONLY.
+ /* For receiving PAUSE frames ONLY.
*
* LOCAL DEVICE | LINK PARTNER
* PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result
@@ -1490,8 +1457,7 @@
hw->fc.current_mode = e1000_fc_tx_pause;
DEBUGOUT("Flow Control = Tx PAUSE frames only.\n");
}
- /*
- * For transmitting PAUSE frames ONLY.
+ /* For transmitting PAUSE frames ONLY.
*
* LOCAL DEVICE | LINK PARTNER
* PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result
@@ -1505,8 +1471,7 @@
hw->fc.current_mode = e1000_fc_rx_pause;
DEBUGOUT("Flow Control = Rx PAUSE frames only.\n");
} else {
- /*
- * Per the IEEE spec, at this point flow control
+ /* Per the IEEE spec, at this point flow control
* should be disabled.
*/
hw->fc.current_mode = e1000_fc_none;
@@ -1513,8 +1478,7 @@
DEBUGOUT("Flow Control = NONE.\n");
}
- /*
- * Now we need to do one last check... If we auto-
+ /* Now we need to do one last check... If we auto-
* negotiated to HALF DUPLEX, flow control should not be
* enabled per IEEE 802.3 spec.
*/
@@ -1527,8 +1491,7 @@
if (duplex == HALF_DUPLEX)
hw->fc.current_mode = e1000_fc_none;
- /*
- * Now we call a subroutine to actually force the MAC
+ /* Now we call a subroutine to actually force the MAC
* controller to use the correct flow control settings.
*/
ret_val = e1000_force_mac_fc_generic(hw);
@@ -1538,6 +1501,130 @@
}
}
+ /* Check for the case where we have SerDes media and auto-neg is
+ * enabled. In this case, we need to check and see if Auto-Neg
+ * has completed, and if so, how the PHY and link partner has
+ * flow control configured.
+ */
+ if ((hw->phy.media_type == e1000_media_type_internal_serdes) &&
+ mac->autoneg) {
+ /* Read the PCS_LSTS and check to see if AutoNeg
+ * has completed.
+ */
+ pcs_status_reg = E1000_READ_REG(hw, E1000_PCS_LSTAT);
+
+ if (!(pcs_status_reg & E1000_PCS_LSTS_AN_COMPLETE)) {
+ DEBUGOUT("PCS Auto Neg has not completed.\n");
+ return ret_val;
+ }
+
+ /* The AutoNeg process has completed, so we now need to
+ * read both the Auto Negotiation Advertisement
+ * Register (PCS_ANADV) and the Auto_Negotiation Base
+ * Page Ability Register (PCS_LPAB) to determine how
+ * flow control was negotiated.
+ */
+ pcs_adv_reg = E1000_READ_REG(hw, E1000_PCS_ANADV);
+ pcs_lp_ability_reg = E1000_READ_REG(hw, E1000_PCS_LPAB);
+
+ /* Two bits in the Auto Negotiation Advertisement Register
+ * (PCS_ANADV) and two bits in the Auto Negotiation Base
+ * Page Ability Register (PCS_LPAB) determine flow control
+ * for both the PHY and the link partner. The following
+ * table, taken out of the IEEE 802.3ab/D6.0 dated March 25,
+ * 1999, describes these PAUSE resolution bits and how flow
+ * control is determined based upon these settings.
+ * NOTE: DC = Don't Care
+ *
+ * LOCAL DEVICE | LINK PARTNER
+ * PAUSE | ASM_DIR | PAUSE | ASM_DIR | NIC Resolution
+ *-------|---------|-------|---------|--------------------
+ * 0 | 0 | DC | DC | e1000_fc_none
+ * 0 | 1 | 0 | DC | e1000_fc_none
+ * 0 | 1 | 1 | 0 | e1000_fc_none
+ * 0 | 1 | 1 | 1 | e1000_fc_tx_pause
+ * 1 | 0 | 0 | DC | e1000_fc_none
+ * 1 | DC | 1 | DC | e1000_fc_full
+ * 1 | 1 | 0 | 0 | e1000_fc_none
+ * 1 | 1 | 0 | 1 | e1000_fc_rx_pause
+ *
+ * Are both PAUSE bits set to 1? If so, this implies
+ * Symmetric Flow Control is enabled at both ends. The
+ * ASM_DIR bits are irrelevant per the spec.
+ *
+ * For Symmetric Flow Control:
+ *
+ * LOCAL DEVICE | LINK PARTNER
+ * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result
+ *-------|---------|-------|---------|--------------------
+ * 1 | DC | 1 | DC | e1000_fc_full
+ *
+ */
+ if ((pcs_adv_reg & E1000_TXCW_PAUSE) &&
+ (pcs_lp_ability_reg & E1000_TXCW_PAUSE)) {
+ /* Now we need to check if the user selected Rx ONLY
+ * of pause frames. In this case, we had to advertise
+ * FULL flow control because we could not advertise Rx
+ * ONLY. Hence, we must now check to see if we need to
+ * turn OFF the TRANSMISSION of PAUSE frames.
+ */
+ if (hw->fc.requested_mode == e1000_fc_full) {
+ hw->fc.current_mode = e1000_fc_full;
+ DEBUGOUT("Flow Control = FULL.\n");
+ } else {
+ hw->fc.current_mode = e1000_fc_rx_pause;
+ DEBUGOUT("Flow Control = Rx PAUSE frames only.\n");
+ }
+ }
+ /* For receiving PAUSE frames ONLY.
+ *
+ * LOCAL DEVICE | LINK PARTNER
+ * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result
+ *-------|---------|-------|---------|--------------------
+ * 0 | 1 | 1 | 1 | e1000_fc_tx_pause
+ */
+ else if (!(pcs_adv_reg & E1000_TXCW_PAUSE) &&
+ (pcs_adv_reg & E1000_TXCW_ASM_DIR) &&
+ (pcs_lp_ability_reg & E1000_TXCW_PAUSE) &&
+ (pcs_lp_ability_reg & E1000_TXCW_ASM_DIR)) {
+ hw->fc.current_mode = e1000_fc_tx_pause;
+ DEBUGOUT("Flow Control = Tx PAUSE frames only.\n");
+ }
+ /* For transmitting PAUSE frames ONLY.
+ *
+ * LOCAL DEVICE | LINK PARTNER
+ * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result
+ *-------|---------|-------|---------|--------------------
+ * 1 | 1 | 0 | 1 | e1000_fc_rx_pause
+ */
+ else if ((pcs_adv_reg & E1000_TXCW_PAUSE) &&
+ (pcs_adv_reg & E1000_TXCW_ASM_DIR) &&
+ !(pcs_lp_ability_reg & E1000_TXCW_PAUSE) &&
+ (pcs_lp_ability_reg & E1000_TXCW_ASM_DIR)) {
+ hw->fc.current_mode = e1000_fc_rx_pause;
+ DEBUGOUT("Flow Control = Rx PAUSE frames only.\n");
+ } else {
+ /* Per the IEEE spec, at this point flow control
+ * should be disabled.
+ */
+ hw->fc.current_mode = e1000_fc_none;
+ DEBUGOUT("Flow Control = NONE.\n");
+ }
+
+ /* Now we call a subroutine to actually force the MAC
+ * controller to use the correct flow control settings.
+ */
+ pcs_ctrl_reg = E1000_READ_REG(hw, E1000_PCS_LCTL);
+ pcs_ctrl_reg |= E1000_PCS_LCTL_FORCE_FCTRL;
+ E1000_WRITE_REG(hw, E1000_PCS_LCTL, pcs_ctrl_reg);
+
+ ret_val = e1000_force_mac_fc_generic(hw);
+ if (ret_val) {
+ DEBUGOUT("Error forcing flow control settings\n");
+ return ret_val;
+ }
+ }
+
return E1000_SUCCESS;
}
@@ -1854,16 +1941,28 @@
ledctl_blink = E1000_LEDCTL_LED0_BLINK |
(E1000_LEDCTL_MODE_LED_ON << E1000_LEDCTL_LED0_MODE_SHIFT);
} else {
- /*
- * set the blink bit for each LED that's "on" (0x0E)
- * in ledctl_mode2
+ /* Set the blink bit for each LED that's "on" (0x0E)
+ * (or "off" if inverted) in ledctl_mode2. The blink
+ * logic in hardware only works when mode is set to "on"
+ * so it must be changed accordingly when the mode is
+ * "off" and inverted.
*/
ledctl_blink = hw->mac.ledctl_mode2;
- for (i = 0; i < 4; i++)
- if (((hw->mac.ledctl_mode2 >> (i * 8)) & 0xFF) ==
- E1000_LEDCTL_MODE_LED_ON)
- ledctl_blink |= (E1000_LEDCTL_LED0_BLINK <<
- (i * 8));
+ for (i = 0; i < 32; i += 8) {
+ u32 mode = (hw->mac.ledctl_mode2 >> i) &
+ E1000_LEDCTL_LED0_MODE_MASK;
+ u32 led_default = hw->mac.ledctl_default >> i;
+
+ if ((!(led_default & E1000_LEDCTL_LED0_IVRT) &&
+ (mode == E1000_LEDCTL_MODE_LED_ON)) ||
+ ((led_default & E1000_LEDCTL_LED0_IVRT) &&
+ (mode == E1000_LEDCTL_MODE_LED_OFF))) {
+ ledctl_blink &=
+ ~(E1000_LEDCTL_LED0_MODE_MASK << i);
+ ledctl_blink |= (E1000_LEDCTL_LED0_BLINK |
+ E1000_LEDCTL_MODE_LED_ON) << i;
+ }
+ }
}
E1000_WRITE_REG(hw, E1000_LEDCTL, ledctl_blink);
@@ -2083,6 +2182,20 @@
}
/**
+ * e1000_validate_mdi_setting_crossover_generic - Verify MDI/MDIx settings
+ * @hw: pointer to the HW structure
+ *
+ * Validate the MDI/MDIx setting, allowing for auto-crossover during forced
+ * operation.
+ **/
+s32 e1000_validate_mdi_setting_crossover_generic(struct e1000_hw *hw)
+{
+ DEBUGFUNC("e1000_validate_mdi_setting_crossover_generic");
+
+ return E1000_SUCCESS;
+}
+
+/**
* e1000_write_8bit_ctrl_reg_generic - Write a 8bit CTRL register
* @hw: pointer to the HW structure
* @reg: 32bit register offset such as E1000_SCTL
Property changes on: trunk/sys/dev/e1000/e1000_mac.c
___________________________________________________________________
Deleted: cvs2svn:cvs-rev
## -1 +0,0 ##
-1.4
\ No newline at end of property
Modified: trunk/sys/dev/e1000/e1000_mac.h
===================================================================
--- trunk/sys/dev/e1000/e1000_mac.h 2013-12-28 14:30:04 UTC (rev 6559)
+++ trunk/sys/dev/e1000/e1000_mac.h 2013-12-28 14:30:47 UTC (rev 6560)
@@ -1,6 +1,7 @@
+/* $MidnightBSD$ */
/******************************************************************************
- Copyright (c) 2001-2012, Intel Corporation
+ Copyright (c) 2001-2013, Intel Corporation
All rights reserved.
Redistribution and use in source and binary forms, with or without
@@ -30,15 +31,11 @@
POSSIBILITY OF SUCH DAMAGE.
******************************************************************************/
-/*$MidnightBSD$*/
+/*$FreeBSD: release/9.2.0/sys/dev/e1000/e1000_mac.h 248292 2013-03-14 22:55:59Z jfv $*/
#ifndef _E1000_MAC_H_
#define _E1000_MAC_H_
-/*
- * Functions that should not be called directly from drivers but can be used
- * by other files in this 'shared code'
- */
void e1000_init_mac_ops_generic(struct e1000_hw *hw);
void e1000_null_mac_generic(struct e1000_hw *hw);
s32 e1000_null_ops_generic(struct e1000_hw *hw);
@@ -47,6 +44,7 @@
void e1000_null_update_mc(struct e1000_hw *hw, u8 *h, u32 a);
void e1000_null_write_vfta(struct e1000_hw *hw, u32 a, u32 b);
void e1000_null_rar_set(struct e1000_hw *hw, u8 *h, u32 a);
+s32 e1000_null_set_obff_timer(struct e1000_hw *hw, u32 a);
s32 e1000_blink_led_generic(struct e1000_hw *hw);
s32 e1000_check_for_copper_link_generic(struct e1000_hw *hw);
s32 e1000_check_for_fiber_link_generic(struct e1000_hw *hw);
@@ -77,6 +75,7 @@
s32 e1000_setup_fiber_serdes_link_generic(struct e1000_hw *hw);
s32 e1000_setup_led_generic(struct e1000_hw *hw);
s32 e1000_setup_link_generic(struct e1000_hw *hw);
+s32 e1000_validate_mdi_setting_crossover_generic(struct e1000_hw *hw);
s32 e1000_write_8bit_ctrl_reg_generic(struct e1000_hw *hw, u32 reg,
u32 offset, u8 data);
Property changes on: trunk/sys/dev/e1000/e1000_mac.h
___________________________________________________________________
Deleted: cvs2svn:cvs-rev
## -1 +0,0 ##
-1.4
\ No newline at end of property
Modified: trunk/sys/dev/e1000/e1000_manage.c
===================================================================
--- trunk/sys/dev/e1000/e1000_manage.c 2013-12-28 14:30:04 UTC (rev 6559)
+++ trunk/sys/dev/e1000/e1000_manage.c 2013-12-28 14:30:47 UTC (rev 6560)
@@ -1,6 +1,7 @@
+/* $MidnightBSD$ */
/******************************************************************************
- Copyright (c) 2001-2012, Intel Corporation
+ Copyright (c) 2001-2013, Intel Corporation
All rights reserved.
Redistribution and use in source and binary forms, with or without
@@ -30,7 +31,7 @@
POSSIBILITY OF SUCH DAMAGE.
******************************************************************************/
-/*$MidnightBSD$*/
+/*$FreeBSD: release/9.2.0/sys/dev/e1000/e1000_manage.c 248292 2013-03-14 22:55:59Z jfv $*/
#include "e1000_api.h"
@@ -145,11 +146,10 @@
return hw->mac.tx_pkt_filtering;
}
- /*
- * If we can't read from the host interface for whatever
+ /* If we can't read from the host interface for whatever
* reason, disable filtering.
*/
- ret_val = hw->mac.ops.mng_enable_host_if(hw);
+ ret_val = e1000_mng_enable_host_if_generic(hw);
if (ret_val != E1000_SUCCESS) {
hw->mac.tx_pkt_filtering = FALSE;
return hw->mac.tx_pkt_filtering;
@@ -165,8 +165,7 @@
hdr->checksum = 0;
csum = e1000_calculate_checksum((u8 *)hdr,
E1000_MNG_DHCP_COOKIE_LENGTH);
- /*
- * If either the checksums or signature don't match, then
+ /* If either the checksums or signature don't match, then
* the cookie area isn't considered valid, in which case we
* take the safe route of assuming Tx filtering is enabled.
*/
@@ -259,8 +258,7 @@
/* Calculate length in DWORDs */
length >>= 2;
- /*
- * The device driver writes the relevant command block into the
+ /* The device driver writes the relevant command block into the
* ram area.
*/
for (i = 0; i < length; i++) {
@@ -312,18 +310,18 @@
hdr.checksum = 0;
/* Enable the host interface */
- ret_val = hw->mac.ops.mng_enable_host_if(hw);
+ ret_val = e1000_mng_enable_host_if_generic(hw);
if (ret_val)
return ret_val;
/* Populate the host interface with the contents of "buffer". */
- ret_val = hw->mac.ops.mng_host_if_write(hw, buffer, length,
- sizeof(hdr), &(hdr.checksum));
+ ret_val = e1000_mng_host_if_write_generic(hw, buffer, length,
+ sizeof(hdr), &(hdr.checksum));
if (ret_val)
return ret_val;
/* Write the manageability command header */
- ret_val = hw->mac.ops.mng_write_cmd_header(hw, &hdr);
+ ret_val = e1000_mng_write_cmd_header_generic(hw, &hdr);
if (ret_val)
return ret_val;
@@ -424,8 +422,7 @@
/* Calculate length in DWORDs */
length >>= 2;
- /*
- * The device driver writes the relevant command block
+ /* The device driver writes the relevant command block
* into the ram area.
*/
for (i = 0; i < length; i++)
@@ -537,8 +534,7 @@
/* Calculate length in DWORDs */
length >>= 2;
- /*
- * The device driver writes the relevant FW code block
+ /* The device driver writes the relevant FW code block
* into the ram area in DWORDs via 1kB ram addressing window.
*/
for (i = 0; i < length; i++) {
Property changes on: trunk/sys/dev/e1000/e1000_manage.c
___________________________________________________________________
Deleted: cvs2svn:cvs-rev
## -1 +0,0 ##
-1.4
\ No newline at end of property
Modified: trunk/sys/dev/e1000/e1000_manage.h
===================================================================
--- trunk/sys/dev/e1000/e1000_manage.h 2013-12-28 14:30:04 UTC (rev 6559)
+++ trunk/sys/dev/e1000/e1000_manage.h 2013-12-28 14:30:47 UTC (rev 6560)
@@ -1,3 +1,4 @@
+/* $MidnightBSD$ */
/******************************************************************************
Copyright (c) 2001-2012, Intel Corporation
@@ -30,7 +31,7 @@
POSSIBILITY OF SUCH DAMAGE.
******************************************************************************/
-/*$MidnightBSD$*/
+/*$FreeBSD: release/9.2.0/sys/dev/e1000/e1000_manage.h 238262 2012-07-08 20:35:56Z jfv $*/
#ifndef _E1000_MANAGE_H_
#define _E1000_MANAGE_H_
Property changes on: trunk/sys/dev/e1000/e1000_manage.h
___________________________________________________________________
Deleted: cvs2svn:cvs-rev
## -1 +0,0 ##
-1.4
\ No newline at end of property
Modified: trunk/sys/dev/e1000/e1000_mbx.c
===================================================================
--- trunk/sys/dev/e1000/e1000_mbx.c 2013-12-28 14:30:04 UTC (rev 6559)
+++ trunk/sys/dev/e1000/e1000_mbx.c 2013-12-28 14:30:47 UTC (rev 6560)
@@ -1,3 +1,4 @@
+/* $MidnightBSD$ */
/******************************************************************************
Copyright (c) 2001-2010, Intel Corporation
@@ -30,7 +31,7 @@
POSSIBILITY OF SUCH DAMAGE.
******************************************************************************/
-/*$MidnightBSD$*/
+/*$FreeBSD: release/9.2.0/sys/dev/e1000/e1000_mbx.c 218530 2011-02-11 01:00:26Z jfv $*/
#include "e1000_mbx.h"
Property changes on: trunk/sys/dev/e1000/e1000_mbx.c
___________________________________________________________________
Deleted: cvs2svn:cvs-rev
## -1 +0,0 ##
-1.3
\ No newline at end of property
Modified: trunk/sys/dev/e1000/e1000_mbx.h
===================================================================
--- trunk/sys/dev/e1000/e1000_mbx.h 2013-12-28 14:30:04 UTC (rev 6559)
+++ trunk/sys/dev/e1000/e1000_mbx.h 2013-12-28 14:30:47 UTC (rev 6560)
@@ -1,3 +1,4 @@
+/* $MidnightBSD$ */
/******************************************************************************
Copyright (c) 2001-2010, Intel Corporation
@@ -30,7 +31,7 @@
POSSIBILITY OF SUCH DAMAGE.
******************************************************************************/
-/*$MidnightBSD$*/
+/*$FreeBSD: release/9.2.0/sys/dev/e1000/e1000_mbx.h 209616 2010-06-30 21:05:51Z jfv $*/
#ifndef _E1000_MBX_H_
#define _E1000_MBX_H_
Property changes on: trunk/sys/dev/e1000/e1000_mbx.h
___________________________________________________________________
Deleted: cvs2svn:cvs-rev
## -1 +0,0 ##
-1.3
\ No newline at end of property
Modified: trunk/sys/dev/e1000/e1000_nvm.c
===================================================================
--- trunk/sys/dev/e1000/e1000_nvm.c 2013-12-28 14:30:04 UTC (rev 6559)
+++ trunk/sys/dev/e1000/e1000_nvm.c 2013-12-28 14:30:47 UTC (rev 6560)
@@ -1,6 +1,7 @@
+/* $MidnightBSD$ */
/******************************************************************************
- Copyright (c) 2001-2011, Intel Corporation
+ Copyright (c) 2001-2013, Intel Corporation
All rights reserved.
Redistribution and use in source and binary forms, with or without
@@ -30,7 +31,7 @@
POSSIBILITY OF SUCH DAMAGE.
******************************************************************************/
-/*$MidnightBSD$*/
+/*$FreeBSD: release/9.2.0/sys/dev/e1000/e1000_nvm.c 248292 2013-03-14 22:55:59Z jfv $*/
#include "e1000_api.h"
@@ -227,7 +228,6 @@
{
u32 attempts = 100000;
u32 i, reg = 0;
- s32 ret_val = -E1000_ERR_NVM;
DEBUGFUNC("e1000_poll_eerd_eewr_done");
@@ -237,15 +237,13 @@
else
reg = E1000_READ_REG(hw, E1000_EEWR);
- if (reg & E1000_NVM_RW_REG_DONE) {
- ret_val = E1000_SUCCESS;
- break;
- }
+ if (reg & E1000_NVM_RW_REG_DONE)
+ return E1000_SUCCESS;
usec_delay(5);
}
- return ret_val;
+ return -E1000_ERR_NVM;
}
/**
@@ -260,7 +258,6 @@
{
u32 eecd = E1000_READ_REG(hw, E1000_EECD);
s32 timeout = E1000_NVM_GRANT_ATTEMPTS;
- s32 ret_val = E1000_SUCCESS;
DEBUGFUNC("e1000_acquire_nvm_generic");
@@ -279,10 +276,10 @@
eecd &= ~E1000_EECD_REQ;
E1000_WRITE_REG(hw, E1000_EECD, eecd);
DEBUGOUT("Could not acquire NVM grant\n");
- ret_val = -E1000_ERR_NVM;
+ return -E1000_ERR_NVM;
}
- return ret_val;
+ return E1000_SUCCESS;
}
/**
@@ -381,7 +378,6 @@
{
struct e1000_nvm_info *nvm = &hw->nvm;
u32 eecd = E1000_READ_REG(hw, E1000_EECD);
- s32 ret_val = E1000_SUCCESS;
u8 spi_stat_reg;
DEBUGFUNC("e1000_ready_nvm_eeprom");
@@ -402,8 +398,7 @@
E1000_WRITE_FLUSH(hw);
usec_delay(1);
- /*
- * Read "Status Register" repeatedly until the LSB is cleared.
+ /* Read "Status Register" repeatedly until the LSB is cleared.
* The EEPROM will signal that the command has been completed
* by clearing bit 0 of the internal status register. If it's
* not cleared within 'timeout', then error out.
@@ -422,13 +417,11 @@
if (!timeout) {
DEBUGOUT("SPI NVM Status error\n");
- ret_val = -E1000_ERR_NVM;
- goto out;
+ return -E1000_ERR_NVM;
}
}
-out:
- return ret_val;
+ return E1000_SUCCESS;
}
/**
@@ -450,20 +443,18 @@
DEBUGFUNC("e1000_read_nvm_spi");
- /*
- * A check for invalid values: offset too large, too many words,
+ /* A check for invalid values: offset too large, too many words,
* and not enough words.
*/
if ((offset >= nvm->word_size) || (words > (nvm->word_size - offset)) ||
(words == 0)) {
DEBUGOUT("nvm parameter(s) out of bounds\n");
- ret_val = -E1000_ERR_NVM;
- goto out;
+ return -E1000_ERR_NVM;
}
ret_val = nvm->ops.acquire(hw);
if (ret_val)
- goto out;
+ return ret_val;
ret_val = e1000_ready_nvm_eeprom(hw);
if (ret_val)
@@ -478,8 +469,7 @@
e1000_shift_out_eec_bits(hw, read_opcode, nvm->opcode_bits);
e1000_shift_out_eec_bits(hw, (u16)(offset*2), nvm->address_bits);
- /*
- * Read the data. SPI NVMs increment the address with each byte
+ /* Read the data. SPI NVMs increment the address with each byte
* read and will roll over if reading beyond the end. This allows
* us to read the whole NVM from any offset
*/
@@ -491,7 +481,6 @@
release:
nvm->ops.release(hw);
-out:
return ret_val;
}
@@ -514,20 +503,18 @@
DEBUGFUNC("e1000_read_nvm_microwire");
- /*
- * A check for invalid values: offset too large, too many words,
+ /* A check for invalid values: offset too large, too many words,
* and not enough words.
*/
if ((offset >= nvm->word_size) || (words > (nvm->word_size - offset)) ||
(words == 0)) {
DEBUGOUT("nvm parameter(s) out of bounds\n");
- ret_val = -E1000_ERR_NVM;
- goto out;
+ return -E1000_ERR_NVM;
}
ret_val = nvm->ops.acquire(hw);
if (ret_val)
- goto out;
+ return ret_val;
ret_val = e1000_ready_nvm_eeprom(hw);
if (ret_val)
@@ -539,8 +526,7 @@
e1000_shift_out_eec_bits(hw, (u16)(offset + i),
nvm->address_bits);
- /*
- * Read the data. For microwire, each word requires the
+ /* Read the data. For microwire, each word requires the
* overhead of setup and tear-down.
*/
data[i] = e1000_shift_in_eec_bits(hw, 16);
@@ -550,7 +536,6 @@
release:
nvm->ops.release(hw);
-out:
return ret_val;
}
@@ -571,15 +556,13 @@
DEBUGFUNC("e1000_read_nvm_eerd");
- /*
- * A check for invalid values: offset too large, too many words,
+ /* A check for invalid values: offset too large, too many words,
* too many words for the offset, and not enough words.
*/
if ((offset >= nvm->word_size) || (words > (nvm->word_size - offset)) ||
(words == 0)) {
DEBUGOUT("nvm parameter(s) out of bounds\n");
- ret_val = -E1000_ERR_NVM;
- goto out;
+ return -E1000_ERR_NVM;
}
for (i = 0; i < words; i++) {
@@ -595,7 +578,6 @@
E1000_NVM_RW_REG_DATA);
}
-out:
return ret_val;
}
@@ -614,33 +596,33 @@
s32 e1000_write_nvm_spi(struct e1000_hw *hw, u16 offset, u16 words, u16 *data)
{
struct e1000_nvm_info *nvm = &hw->nvm;
- s32 ret_val;
+ s32 ret_val = -E1000_ERR_NVM;
u16 widx = 0;
DEBUGFUNC("e1000_write_nvm_spi");
- /*
- * A check for invalid values: offset too large, too many words,
+ /* A check for invalid values: offset too large, too many words,
* and not enough words.
*/
if ((offset >= nvm->word_size) || (words > (nvm->word_size - offset)) ||
(words == 0)) {
DEBUGOUT("nvm parameter(s) out of bounds\n");
- ret_val = -E1000_ERR_NVM;
- goto out;
+ return -E1000_ERR_NVM;
}
- ret_val = nvm->ops.acquire(hw);
- if (ret_val)
- goto out;
-
while (widx < words) {
u8 write_opcode = NVM_WRITE_OPCODE_SPI;
- ret_val = e1000_ready_nvm_eeprom(hw);
+ ret_val = nvm->ops.acquire(hw);
if (ret_val)
- goto release;
+ return ret_val;
+ ret_val = e1000_ready_nvm_eeprom(hw);
+ if (ret_val) {
+ nvm->ops.release(hw);
+ return ret_val;
+ }
+
e1000_standby_nvm(hw);
/* Send the WRITE ENABLE command (8 bit opcode) */
@@ -649,8 +631,7 @@
e1000_standby_nvm(hw);
- /*
- * Some SPI eeproms use the 8th address bit embedded in the
+ /* Some SPI eeproms use the 8th address bit embedded in the
* opcode
*/
if ((nvm->address_bits == 8) && (offset >= 128))
@@ -673,13 +654,10 @@
break;
}
}
+ msec_delay(10);
+ nvm->ops.release(hw);
}
- msec_delay(10);
-release:
- nvm->ops.release(hw);
-
-out:
return ret_val;
}
@@ -706,20 +684,18 @@
DEBUGFUNC("e1000_write_nvm_microwire");
- /*
- * A check for invalid values: offset too large, too many words,
+ /* A check for invalid values: offset too large, too many words,
* and not enough words.
*/
if ((offset >= nvm->word_size) || (words > (nvm->word_size - offset)) ||
(words == 0)) {
DEBUGOUT("nvm parameter(s) out of bounds\n");
- ret_val = -E1000_ERR_NVM;
- goto out;
+ return -E1000_ERR_NVM;
}
ret_val = nvm->ops.acquire(hw);
if (ret_val)
- goto out;
+ return ret_val;
ret_val = e1000_ready_nvm_eeprom(hw);
if (ret_val)
@@ -769,7 +745,6 @@
release:
nvm->ops.release(hw);
-out:
return ret_val;
}
@@ -795,24 +770,22 @@
if (pba_num == NULL) {
DEBUGOUT("PBA string buffer was null\n");
- ret_val = E1000_ERR_INVALID_ARGUMENT;
- goto out;
+ return -E1000_ERR_INVALID_ARGUMENT;
}
ret_val = hw->nvm.ops.read(hw, NVM_PBA_OFFSET_0, 1, &nvm_data);
if (ret_val) {
DEBUGOUT("NVM Read Error\n");
- goto out;
+ return ret_val;
}
ret_val = hw->nvm.ops.read(hw, NVM_PBA_OFFSET_1, 1, &pba_ptr);
if (ret_val) {
DEBUGOUT("NVM Read Error\n");
- goto out;
+ return ret_val;
}
- /*
- * if nvm_data is not ptr guard the PBA must be in legacy format which
+ /* if nvm_data is not ptr guard the PBA must be in legacy format which
* means pba_ptr is actually our second data word for the PBA number
* and we can decode it into an ascii string
*/
@@ -819,8 +792,8 @@
if (nvm_data != NVM_PBA_PTR_GUARD) {
DEBUGOUT("NVM PBA number is not stored as string\n");
- /* we will need 11 characters to store the PBA */
- if (pba_num_size < 11) {
+ /* make sure callers buffer is big enough to store the PBA */
+ if (pba_num_size < E1000_PBANUM_LENGTH) {
DEBUGOUT("PBA string buffer too small\n");
return E1000_ERR_NO_SPACE;
}
@@ -848,25 +821,23 @@
pba_num[offset] += 'A' - 0xA;
}
- goto out;
+ return E1000_SUCCESS;
}
ret_val = hw->nvm.ops.read(hw, pba_ptr, 1, &length);
if (ret_val) {
DEBUGOUT("NVM Read Error\n");
- goto out;
+ return ret_val;
}
if (length == 0xFFFF || length == 0) {
DEBUGOUT("NVM PBA number section invalid length\n");
- ret_val = E1000_ERR_NVM_PBA_SECTION;
- goto out;
+ return -E1000_ERR_NVM_PBA_SECTION;
}
/* check if pba_num buffer is big enough */
if (pba_num_size < (((u32)length * 2) - 1)) {
DEBUGOUT("PBA string buffer too small\n");
- ret_val = E1000_ERR_NO_SPACE;
- goto out;
+ return -E1000_ERR_NO_SPACE;
}
/* trim pba length from start of string */
@@ -877,7 +848,7 @@
ret_val = hw->nvm.ops.read(hw, pba_ptr + offset, 1, &nvm_data);
if (ret_val) {
DEBUGOUT("NVM Read Error\n");
- goto out;
+ return ret_val;
}
pba_num[offset * 2] = (u8)(nvm_data >> 8);
pba_num[(offset * 2) + 1] = (u8)(nvm_data & 0xFF);
@@ -884,8 +855,7 @@
}
pba_num[offset * 2] = '\0';
-out:
- return ret_val;
+ return E1000_SUCCESS;
}
/**
@@ -907,51 +877,236 @@
if (pba_num_size == NULL) {
DEBUGOUT("PBA buffer size was null\n");
- ret_val = E1000_ERR_INVALID_ARGUMENT;
- goto out;
+ return -E1000_ERR_INVALID_ARGUMENT;
}
ret_val = hw->nvm.ops.read(hw, NVM_PBA_OFFSET_0, 1, &nvm_data);
if (ret_val) {
DEBUGOUT("NVM Read Error\n");
- goto out;
+ return ret_val;
}
ret_val = hw->nvm.ops.read(hw, NVM_PBA_OFFSET_1, 1, &pba_ptr);
if (ret_val) {
DEBUGOUT("NVM Read Error\n");
- goto out;
+ return ret_val;
}
/* if data is not ptr guard the PBA must be in legacy format */
if (nvm_data != NVM_PBA_PTR_GUARD) {
- *pba_num_size = 11;
- goto out;
+ *pba_num_size = E1000_PBANUM_LENGTH;
+ return E1000_SUCCESS;
}
ret_val = hw->nvm.ops.read(hw, pba_ptr, 1, &length);
if (ret_val) {
DEBUGOUT("NVM Read Error\n");
- goto out;
+ return ret_val;
}
if (length == 0xFFFF || length == 0) {
DEBUGOUT("NVM PBA number section invalid length\n");
- ret_val = E1000_ERR_NVM_PBA_SECTION;
- goto out;
+ return -E1000_ERR_NVM_PBA_SECTION;
}
- /*
- * Convert from length in u16 values to u8 chars, add 1 for NULL,
+ /* Convert from length in u16 values to u8 chars, add 1 for NULL,
* and subtract 2 because length field is included in length.
*/
*pba_num_size = ((u32)length * 2) - 1;
-out:
- return ret_val;
+ return E1000_SUCCESS;
}
+
/**
+ * e1000_read_pba_raw
+ * @hw: pointer to the HW structure
+ * @eeprom_buf: optional pointer to EEPROM image
+ * @eeprom_buf_size: size of EEPROM image in words
+ * @max_pba_block_size: PBA block size limit
+ * @pba: pointer to output PBA structure
+ *
+ * Reads PBA from EEPROM image when eeprom_buf is not NULL.
+ * Reads PBA from physical EEPROM device when eeprom_buf is NULL.
+ *
+ **/
+s32 e1000_read_pba_raw(struct e1000_hw *hw, u16 *eeprom_buf,
+ u32 eeprom_buf_size, u16 max_pba_block_size,
+ struct e1000_pba *pba)
+{
+ s32 ret_val;
+ u16 pba_block_size;
+
+ if (pba == NULL)
+ return -E1000_ERR_PARAM;
+
+ if (eeprom_buf == NULL) {
+ ret_val = e1000_read_nvm(hw, NVM_PBA_OFFSET_0, 2,
+ &pba->word[0]);
+ if (ret_val)
+ return ret_val;
+ } else {
+ if (eeprom_buf_size > NVM_PBA_OFFSET_1) {
+ pba->word[0] = eeprom_buf[NVM_PBA_OFFSET_0];
+ pba->word[1] = eeprom_buf[NVM_PBA_OFFSET_1];
+ } else {
+ return -E1000_ERR_PARAM;
+ }
+ }
+
+ if (pba->word[0] == NVM_PBA_PTR_GUARD) {
+ if (pba->pba_block == NULL)
+ return -E1000_ERR_PARAM;
+
+ ret_val = e1000_get_pba_block_size(hw, eeprom_buf,
+ eeprom_buf_size,
+ &pba_block_size);
+ if (ret_val)
+ return ret_val;
+
+ if (pba_block_size > max_pba_block_size)
+ return -E1000_ERR_PARAM;
+
+ if (eeprom_buf == NULL) {
+ ret_val = e1000_read_nvm(hw, pba->word[1],
+ pba_block_size,
+ pba->pba_block);
+ if (ret_val)
+ return ret_val;
+ } else {
+ if (eeprom_buf_size > (u32)(pba->word[1] +
+ pba->pba_block[0])) {
+ memcpy(pba->pba_block,
+ &eeprom_buf[pba->word[1]],
+ pba_block_size * sizeof(u16));
+ } else {
+ return -E1000_ERR_PARAM;
+ }
+ }
+ }
+
+ return E1000_SUCCESS;
+}
+
+/**
+ * e1000_write_pba_raw
+ * @hw: pointer to the HW structure
+ * @eeprom_buf: optional pointer to EEPROM image
+ * @eeprom_buf_size: size of EEPROM image in words
+ * @pba: pointer to PBA structure
+ *
+ * Writes PBA to EEPROM image when eeprom_buf is not NULL.
+ * Writes PBA to physical EEPROM device when eeprom_buf is NULL.
+ *
+ **/
+s32 e1000_write_pba_raw(struct e1000_hw *hw, u16 *eeprom_buf,
+ u32 eeprom_buf_size, struct e1000_pba *pba)
+{
+ s32 ret_val;
+
+ if (pba == NULL)
+ return -E1000_ERR_PARAM;
+
+ if (eeprom_buf == NULL) {
+ ret_val = e1000_write_nvm(hw, NVM_PBA_OFFSET_0, 2,
+ &pba->word[0]);
+ if (ret_val)
+ return ret_val;
+ } else {
+ if (eeprom_buf_size > NVM_PBA_OFFSET_1) {
+ eeprom_buf[NVM_PBA_OFFSET_0] = pba->word[0];
+ eeprom_buf[NVM_PBA_OFFSET_1] = pba->word[1];
+ } else {
+ return -E1000_ERR_PARAM;
+ }
+ }
+
+ if (pba->word[0] == NVM_PBA_PTR_GUARD) {
+ if (pba->pba_block == NULL)
+ return -E1000_ERR_PARAM;
+
+ if (eeprom_buf == NULL) {
+ ret_val = e1000_write_nvm(hw, pba->word[1],
+ pba->pba_block[0],
+ pba->pba_block);
+ if (ret_val)
+ return ret_val;
+ } else {
+ if (eeprom_buf_size > (u32)(pba->word[1] +
+ pba->pba_block[0])) {
+ memcpy(&eeprom_buf[pba->word[1]],
+ pba->pba_block,
+ pba->pba_block[0] * sizeof(u16));
+ } else {
+ return -E1000_ERR_PARAM;
+ }
+ }
+ }
+
+ return E1000_SUCCESS;
+}
+
+/**
+ * e1000_get_pba_block_size
+ * @hw: pointer to the HW structure
+ * @eeprom_buf: optional pointer to EEPROM image
+ * @eeprom_buf_size: size of EEPROM image in words
+ * @pba_data_size: pointer to output variable
+ *
+ * Returns the size of the PBA block in words. Function operates on EEPROM
+ * image if the eeprom_buf pointer is not NULL otherwise it accesses physical
+ * EEPROM device.
+ *
+ **/
+s32 e1000_get_pba_block_size(struct e1000_hw *hw, u16 *eeprom_buf,
+ u32 eeprom_buf_size, u16 *pba_block_size)
+{
+ s32 ret_val;
+ u16 pba_word[2];
+ u16 length;
+
+ DEBUGFUNC("e1000_get_pba_block_size");
+
+ if (eeprom_buf == NULL) {
+ ret_val = e1000_read_nvm(hw, NVM_PBA_OFFSET_0, 2, &pba_word[0]);
+ if (ret_val)
+ return ret_val;
+ } else {
+ if (eeprom_buf_size > NVM_PBA_OFFSET_1) {
+ pba_word[0] = eeprom_buf[NVM_PBA_OFFSET_0];
+ pba_word[1] = eeprom_buf[NVM_PBA_OFFSET_1];
+ } else {
+ return -E1000_ERR_PARAM;
+ }
+ }
+
+ if (pba_word[0] == NVM_PBA_PTR_GUARD) {
+ if (eeprom_buf == NULL) {
+ ret_val = e1000_read_nvm(hw, pba_word[1] + 0, 1,
+ &length);
+ if (ret_val)
+ return ret_val;
+ } else {
+ if (eeprom_buf_size > pba_word[1])
+ length = eeprom_buf[pba_word[1] + 0];
+ else
+ return -E1000_ERR_PARAM;
+ }
+
+ if (length == 0xFFFF || length == 0)
+ return -E1000_ERR_NVM_PBA_SECTION;
+ } else {
+ /* PBA number in legacy format, there is no PBA Block. */
+ length = 0;
+ }
+
+ if (pba_block_size != NULL)
+ *pba_block_size = length;
+
+ return E1000_SUCCESS;
+}
+
+/**
* e1000_read_mac_addr_generic - Read device MAC address
* @hw: pointer to the HW structure
*
@@ -989,7 +1144,7 @@
**/
s32 e1000_validate_nvm_checksum_generic(struct e1000_hw *hw)
{
- s32 ret_val = E1000_SUCCESS;
+ s32 ret_val;
u16 checksum = 0;
u16 i, nvm_data;
@@ -999,7 +1154,7 @@
ret_val = hw->nvm.ops.read(hw, i, 1, &nvm_data);
if (ret_val) {
DEBUGOUT("NVM Read Error\n");
- goto out;
+ return ret_val;
}
checksum += nvm_data;
}
@@ -1006,12 +1161,10 @@
if (checksum != (u16) NVM_SUM) {
DEBUGOUT("NVM Checksum Invalid\n");
- ret_val = -E1000_ERR_NVM;
- goto out;
+ return -E1000_ERR_NVM;
}
-out:
- return ret_val;
+ return E1000_SUCCESS;
}
/**
@@ -1034,7 +1187,7 @@
ret_val = hw->nvm.ops.read(hw, i, 1, &nvm_data);
if (ret_val) {
DEBUGOUT("NVM Read Error while updating checksum.\n");
- goto out;
+ return ret_val;
}
checksum += nvm_data;
}
@@ -1043,7 +1196,6 @@
if (ret_val)
DEBUGOUT("NVM Write Error while updating checksum.\n");
-out:
return ret_val;
}
@@ -1067,3 +1219,4 @@
E1000_WRITE_FLUSH(hw);
}
+
Property changes on: trunk/sys/dev/e1000/e1000_nvm.c
___________________________________________________________________
Deleted: cvs2svn:cvs-rev
## -1 +0,0 ##
-1.4
\ No newline at end of property
Modified: trunk/sys/dev/e1000/e1000_nvm.h
===================================================================
--- trunk/sys/dev/e1000/e1000_nvm.h 2013-12-28 14:30:04 UTC (rev 6559)
+++ trunk/sys/dev/e1000/e1000_nvm.h 2013-12-28 14:30:47 UTC (rev 6560)
@@ -1,6 +1,7 @@
+/* $MidnightBSD$ */
/******************************************************************************
- Copyright (c) 2001-2011, Intel Corporation
+ Copyright (c) 2001-2013, Intel Corporation
All rights reserved.
Redistribution and use in source and binary forms, with or without
@@ -30,11 +31,19 @@
POSSIBILITY OF SUCH DAMAGE.
******************************************************************************/
-/*$MidnightBSD$*/
+/*$FreeBSD: release/9.2.0/sys/dev/e1000/e1000_nvm.h 248292 2013-03-14 22:55:59Z jfv $*/
#ifndef _E1000_NVM_H_
#define _E1000_NVM_H_
+#if !defined(NO_READ_PBA_RAW) || !defined(NO_WRITE_PBA_RAW)
+struct e1000_pba {
+ u16 word[2];
+ u16 *pba_block;
+};
+#endif
+
+
void e1000_init_nvm_ops_generic(struct e1000_hw *hw);
s32 e1000_null_read_nvm(struct e1000_hw *hw, u16 a, u16 b, u16 *c);
void e1000_null_nvm_generic(struct e1000_hw *hw);
@@ -47,6 +56,13 @@
s32 e1000_read_pba_string_generic(struct e1000_hw *hw, u8 *pba_num,
u32 pba_num_size);
s32 e1000_read_pba_length_generic(struct e1000_hw *hw, u32 *pba_num_size);
+s32 e1000_read_pba_raw(struct e1000_hw *hw, u16 *eeprom_buf,
+ u32 eeprom_buf_size, u16 max_pba_block_size,
+ struct e1000_pba *pba);
+s32 e1000_write_pba_raw(struct e1000_hw *hw, u16 *eeprom_buf,
+ u32 eeprom_buf_size, struct e1000_pba *pba);
+s32 e1000_get_pba_block_size(struct e1000_hw *hw, u16 *eeprom_buf,
+ u32 eeprom_buf_size, u16 *pba_block_size);
s32 e1000_read_nvm_spi(struct e1000_hw *hw, u16 offset, u16 words, u16 *data);
s32 e1000_read_nvm_microwire(struct e1000_hw *hw, u16 offset,
u16 words, u16 *data);
Property changes on: trunk/sys/dev/e1000/e1000_nvm.h
___________________________________________________________________
Deleted: cvs2svn:cvs-rev
## -1 +0,0 ##
-1.4
\ No newline at end of property
Modified: trunk/sys/dev/e1000/e1000_osdep.c
===================================================================
--- trunk/sys/dev/e1000/e1000_osdep.c 2013-12-28 14:30:04 UTC (rev 6559)
+++ trunk/sys/dev/e1000/e1000_osdep.c 2013-12-28 14:30:47 UTC (rev 6560)
@@ -1,3 +1,4 @@
+/* $MidnightBSD$ */
/******************************************************************************
Copyright (c) 2001-2010, Intel Corporation
@@ -30,7 +31,7 @@
POSSIBILITY OF SUCH DAMAGE.
******************************************************************************/
-/*$MidnightBSD$*/
+/*$FreeBSD: release/9.2.0/sys/dev/e1000/e1000_osdep.c 219902 2011-03-23 13:10:15Z jhb $*/
#include "e1000_api.h"
Property changes on: trunk/sys/dev/e1000/e1000_osdep.c
___________________________________________________________________
Deleted: cvs2svn:cvs-rev
## -1 +0,0 ##
-1.4
\ No newline at end of property
Modified: trunk/sys/dev/e1000/e1000_osdep.h
===================================================================
--- trunk/sys/dev/e1000/e1000_osdep.h 2013-12-28 14:30:04 UTC (rev 6559)
+++ trunk/sys/dev/e1000/e1000_osdep.h 2013-12-28 14:30:47 UTC (rev 6560)
@@ -1,6 +1,7 @@
+/* $MidnightBSD$ */
/******************************************************************************
- Copyright (c) 2001-2010, Intel Corporation
+ Copyright (c) 2001-2013, Intel Corporation
All rights reserved.
Redistribution and use in source and binary forms, with or without
@@ -30,7 +31,7 @@
POSSIBILITY OF SUCH DAMAGE.
******************************************************************************/
-/*$MidnightBSD$*/
+/*$FreeBSD: release/9.2.0/sys/dev/e1000/e1000_osdep.h 248292 2013-03-14 22:55:59Z jfv $*/
#ifndef _FREEBSD_OS_H_
@@ -66,7 +67,8 @@
#define MSGOUT(S, A, B) printf(S "\n", A, B)
#define DEBUGFUNC(F) DEBUGOUT(F);
#define DEBUGOUT(S) do {} while (0)
-#define DEBUGOUT1(S,A) do {} while (0)
+/* This define is needed or shared code will not build */
+#define DEBUGOUT1(S,A) if (0) printf(S,A);
#define DEBUGOUT2(S,A,B) do {} while (0)
#define DEBUGOUT3(S,A,B,C) do {} while (0)
#define DEBUGOUT7(S,A,B,C,D,E,F,G) do {} while (0)
Property changes on: trunk/sys/dev/e1000/e1000_osdep.h
___________________________________________________________________
Deleted: cvs2svn:cvs-rev
## -1 +0,0 ##
-1.4
\ No newline at end of property
Modified: trunk/sys/dev/e1000/e1000_phy.c
===================================================================
--- trunk/sys/dev/e1000/e1000_phy.c 2013-12-28 14:30:04 UTC (rev 6559)
+++ trunk/sys/dev/e1000/e1000_phy.c 2013-12-28 14:30:47 UTC (rev 6560)
@@ -1,6 +1,7 @@
+/* $MidnightBSD$ */
/******************************************************************************
- Copyright (c) 2001-2012, Intel Corporation
+ Copyright (c) 2001-2013, Intel Corporation
All rights reserved.
Redistribution and use in source and binary forms, with or without
@@ -30,11 +31,11 @@
POSSIBILITY OF SUCH DAMAGE.
******************************************************************************/
-/*$MidnightBSD$*/
+/*$FreeBSD: release/9.2.0/sys/dev/e1000/e1000_phy.c 248292 2013-03-14 22:55:59Z jfv $*/
#include "e1000_api.h"
-static u32 e1000_get_phy_addr_for_bm_page(u32 page, u32 reg);
+static s32 e1000_wait_autoneg(struct e1000_hw *hw);
static s32 e1000_access_phy_wakeup_reg_bm(struct e1000_hw *hw, u32 offset,
u16 *data, bool read, bool page_set);
static u32 e1000_get_phy_addr_for_hv_page(u32 page);
@@ -173,8 +174,10 @@
* @data: data value to write
*
**/
-s32 e1000_write_i2c_byte_null(struct e1000_hw *hw, u8 byte_offset,
- u8 dev_addr, u8 data)
+s32 e1000_write_i2c_byte_null(struct e1000_hw *hw,
+ u8 byte_offset,
+ u8 dev_addr,
+ u8 data)
{
DEBUGFUNC("e1000_write_i2c_byte_null");
return E1000_SUCCESS;
@@ -285,8 +288,7 @@
return -E1000_ERR_PARAM;
}
- /*
- * Set up Op-code, Phy Address, and register offset in the MDI
+ /* Set up Op-code, Phy Address, and register offset in the MDI
* Control register. The MAC will take care of interfacing with the
* PHY to retrieve the desired data.
*/
@@ -296,8 +298,7 @@
E1000_WRITE_REG(hw, E1000_MDIC, mdic);
- /*
- * Poll the ready bit to see if the MDI read completed
+ /* Poll the ready bit to see if the MDI read completed
* Increasing the time out as testing showed failures with
* the lower time out
*/
@@ -315,10 +316,15 @@
DEBUGOUT("MDI Error\n");
return -E1000_ERR_PHY;
}
+ if (((mdic & E1000_MDIC_REG_MASK) >> E1000_MDIC_REG_SHIFT) != offset) {
+ DEBUGOUT2("MDI Read offset error - requested %d, returned %d\n",
+ offset,
+ (mdic & E1000_MDIC_REG_MASK) >> E1000_MDIC_REG_SHIFT);
+ return -E1000_ERR_PHY;
+ }
*data = (u16) mdic;
- /*
- * Allow some time after each MDIC transaction to avoid
+ /* Allow some time after each MDIC transaction to avoid
* reading duplicate data in the next MDIC transaction.
*/
if (hw->mac.type == e1000_pch2lan)
@@ -347,8 +353,7 @@
return -E1000_ERR_PARAM;
}
- /*
- * Set up Op-code, Phy Address, and register offset in the MDI
+ /* Set up Op-code, Phy Address, and register offset in the MDI
* Control register. The MAC will take care of interfacing with the
* PHY to retrieve the desired data.
*/
@@ -359,8 +364,7 @@
E1000_WRITE_REG(hw, E1000_MDIC, mdic);
- /*
- * Poll the ready bit to see if the MDI read completed
+ /* Poll the ready bit to see if the MDI read completed
* Increasing the time out as testing showed failures with
* the lower time out
*/
@@ -378,9 +382,14 @@
DEBUGOUT("MDI Error\n");
return -E1000_ERR_PHY;
}
+ if (((mdic & E1000_MDIC_REG_MASK) >> E1000_MDIC_REG_SHIFT) != offset) {
+ DEBUGOUT2("MDI Write offset error - requested %d, returned %d\n",
+ offset,
+ (mdic & E1000_MDIC_REG_MASK) >> E1000_MDIC_REG_SHIFT);
+ return -E1000_ERR_PHY;
+ }
- /*
- * Allow some time after each MDIC transaction to avoid
+ /* Allow some time after each MDIC transaction to avoid
* reading duplicate data in the next MDIC transaction.
*/
if (hw->mac.type == e1000_pch2lan)
@@ -405,8 +414,7 @@
DEBUGFUNC("e1000_read_phy_reg_i2c");
- /*
- * Set up Op-code, Phy Address, and register address in the I2CCMD
+ /* Set up Op-code, Phy Address, and register address in the I2CCMD
* register. The MAC will take care of interfacing with the
* PHY to retrieve the desired data.
*/
@@ -464,8 +472,7 @@
/* Swap the data bytes for the I2C interface */
phy_data_swapped = ((data >> 8) & 0x00FF) | ((data << 8) & 0xFF00);
- /*
- * Set up Op-code, Phy Address, and register address in the I2CCMD
+ /* Set up Op-code, Phy Address, and register address in the I2CCMD
* register. The MAC will take care of interfacing with the
* PHY to retrieve the desired data.
*/
@@ -521,8 +528,7 @@
return -E1000_ERR_PHY;
}
- /*
- * Set up Op-code, EEPROM Address,in the I2CCMD
+ /* Set up Op-code, EEPROM Address,in the I2CCMD
* register. The MAC will take care of interfacing with the
* EEPROM to retrieve the desired data.
*/
@@ -576,14 +582,12 @@
DEBUGOUT("I2CCMD command address exceeds upper limit\n");
return -E1000_ERR_PHY;
}
- /*
- * The programming interface is 16 bits wide
+ /* The programming interface is 16 bits wide
* so we need to read the whole word first
* then update appropriate byte lane and write
* the updated word back.
*/
- /*
- * Set up Op-code, EEPROM Address,in the I2CCMD
+ /* Set up Op-code, EEPROM Address,in the I2CCMD
* register. The MAC will take care of interfacing
* with an EEPROM to write the data given.
*/
@@ -593,8 +597,7 @@
E1000_WRITE_REG(hw, E1000_I2CCMD, i2ccmd);
for (i = 0; i < E1000_I2CCMD_PHY_TIMEOUT; i++) {
usec_delay(50);
- /*
- * Poll the ready bit to see if lastly
+ /* Poll the ready bit to see if lastly
* launched I2C operation completed
*/
i2ccmd = E1000_READ_REG(hw, E1000_I2CCMD);
@@ -602,8 +605,7 @@
/* Check if this is READ or WRITE phase */
if ((i2ccmd & E1000_I2CCMD_OPCODE_READ) ==
E1000_I2CCMD_OPCODE_READ) {
- /*
- * Write the selected byte
+ /* Write the selected byte
* lane and update whole word
*/
data_local = i2ccmd & 0xFF00;
@@ -1053,12 +1055,16 @@
}
}
- /* Enable CRS on Tx. This must be set for half-duplex operation. */
+ /* Enable CRS on Tx. This must be set for half-duplex operation.
+ * Not required on some PHYs.
+ */
ret_val = hw->phy.ops.read_reg(hw, I82577_CFG_REG, &phy_data);
if (ret_val)
return ret_val;
- phy_data |= I82577_CFG_ASSERT_CRS_ON_TX;
+ if ((hw->phy.type != e1000_phy_82579) &&
+ (hw->phy.type != e1000_phy_i217))
+ phy_data |= I82577_CFG_ASSERT_CRS_ON_TX;
/* Enable downshift */
phy_data |= I82577_CFG_ENABLE_DOWNSHIFT;
@@ -1072,8 +1078,7 @@
if (ret_val)
return ret_val;
phy_data &= ~I82577_PHY_CTRL2_MDIX_CFG_MASK;
- /*
- * Options:
+ /* Options:
* 0 - Auto (default)
* 1 - MDI mode
* 2 - MDI-X mode
@@ -1121,8 +1126,7 @@
if (phy->type != e1000_phy_bm)
phy_data |= M88E1000_PSCR_ASSERT_CRS_ON_TX;
- /*
- * Options:
+ /* Options:
* MDI/MDI-X = 0 (default)
* 0 - Auto for all speeds
* 1 - MDI mode
@@ -1147,8 +1151,7 @@
break;
}
- /*
- * Options:
+ /* Options:
* disable_polarity_correction = 0 (default)
* Automatic Correction for Reversed Cable Polarity
* 0 - Disabled
@@ -1185,8 +1188,7 @@
if ((phy->type == e1000_phy_m88) &&
(phy->revision < E1000_REVISION_4) &&
(phy->id != BME1000_E_PHY_ID_R2)) {
- /*
- * Force TX_CLK in the Extended PHY Specific Control Register
+ /* Force TX_CLK in the Extended PHY Specific Control Register
* to 25MHz clock.
*/
ret_val = phy->ops.read_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL,
@@ -1278,8 +1280,7 @@
if (ret_val)
return ret_val;
- /*
- * Options:
+ /* Options:
* MDI/MDI-X = 0 (default)
* 0 - Auto for all speeds
* 1 - MDI mode
@@ -1307,8 +1308,7 @@
break;
}
- /*
- * Options:
+ /* Options:
* disable_polarity_correction = 0 (default)
* Automatic Correction for Reversed Cable Polarity
* 0 - Disabled
@@ -1359,14 +1359,12 @@
return ret_val;
}
- /*
- * Wait 100ms for MAC to configure PHY from NVM settings, to avoid
+ /* Wait 100ms for MAC to configure PHY from NVM settings, to avoid
* timeout issues when LFS is enabled.
*/
msec_delay(100);
- /*
- * The NVM settings will configure LPLU in D3 for
+ /* The NVM settings will configure LPLU in D3 for
* non-IGP1 PHYs.
*/
if (phy->type == e1000_phy_igp) {
@@ -1411,8 +1409,7 @@
/* set auto-master slave resolution settings */
if (hw->mac.autoneg) {
- /*
- * when autonegotiation advertisement is only 1000Mbps then we
+ /* when autonegotiation advertisement is only 1000Mbps then we
* should disable SmartSpeed and enable Auto MasterSlave
* resolution as hardware default.
*/
@@ -1481,8 +1478,7 @@
return ret_val;
}
- /*
- * Need to parse both autoneg_advertised and fc and set up
+ /* Need to parse both autoneg_advertised and fc and set up
* the appropriate PHY registers. First we will parse for
* autoneg_advertised software override. Since we can advertise
* a plethora of combinations, we need to check each bit
@@ -1489,8 +1485,7 @@
* individually.
*/
- /*
- * First we clear all the 10/100 mb speed bits in the Auto-Neg
+ /* First we clear all the 10/100 mb speed bits in the Auto-Neg
* Advertisement Register (Address 4) and the 1000 mb speed bits in
* the 1000Base-T Control Register (Address 9).
*/
@@ -1536,8 +1531,7 @@
mii_1000t_ctrl_reg |= CR_1000T_FD_CAPS;
}
- /*
- * Check for a software override of the flow control settings, and
+ /* Check for a software override of the flow control settings, and
* setup the PHY advertisement registers accordingly. If
* auto-negotiation is enabled, then software will have to set the
* "PAUSE" bits to the correct value in the Auto-Negotiation
@@ -1556,15 +1550,13 @@
*/
switch (hw->fc.current_mode) {
case e1000_fc_none:
- /*
- * Flow control (Rx & Tx) is completely disabled by a
+ /* Flow control (Rx & Tx) is completely disabled by a
* software over-ride.
*/
mii_autoneg_adv_reg &= ~(NWAY_AR_ASM_DIR | NWAY_AR_PAUSE);
break;
case e1000_fc_rx_pause:
- /*
- * Rx Flow control is enabled, and Tx Flow control is
+ /* Rx Flow control is enabled, and Tx Flow control is
* disabled, by a software over-ride.
*
* Since there really isn't a way to advertise that we are
@@ -1576,8 +1568,7 @@
mii_autoneg_adv_reg |= (NWAY_AR_ASM_DIR | NWAY_AR_PAUSE);
break;
case e1000_fc_tx_pause:
- /*
- * Tx Flow control is enabled, and Rx Flow control is
+ /* Tx Flow control is enabled, and Rx Flow control is
* disabled, by a software over-ride.
*/
mii_autoneg_adv_reg |= NWAY_AR_ASM_DIR;
@@ -1584,8 +1575,7 @@
mii_autoneg_adv_reg &= ~NWAY_AR_PAUSE;
break;
case e1000_fc_full:
- /*
- * Flow control (both Rx and Tx) is enabled by a software
+ /* Flow control (both Rx and Tx) is enabled by a software
* over-ride.
*/
mii_autoneg_adv_reg |= (NWAY_AR_ASM_DIR | NWAY_AR_PAUSE);
@@ -1625,14 +1615,12 @@
DEBUGFUNC("e1000_copper_link_autoneg");
- /*
- * Perform some bounds checking on the autoneg advertisement
+ /* Perform some bounds checking on the autoneg advertisement
* parameter.
*/
phy->autoneg_advertised &= phy->autoneg_mask;
- /*
- * If autoneg_advertised is zero, we assume it was not defaulted
+ /* If autoneg_advertised is zero, we assume it was not defaulted
* by the calling code so we set to advertise full capability.
*/
if (!phy->autoneg_advertised)
@@ -1646,8 +1634,7 @@
}
DEBUGOUT("Restarting Auto-Neg\n");
- /*
- * Restart auto-negotiation by setting the Auto Neg Enable bit and
+ /* Restart auto-negotiation by setting the Auto Neg Enable bit and
* the Auto Neg Restart bit in the PHY control register.
*/
ret_val = phy->ops.read_reg(hw, PHY_CONTROL, &phy_ctrl);
@@ -1659,12 +1646,11 @@
if (ret_val)
return ret_val;
- /*
- * Does the user want to wait for Auto-Neg to complete here, or
+ /* Does the user want to wait for Auto-Neg to complete here, or
* check at a later time (for example, callback routine).
*/
if (phy->autoneg_wait_to_complete) {
- ret_val = hw->mac.ops.wait_autoneg(hw);
+ ret_val = e1000_wait_autoneg(hw);
if (ret_val) {
DEBUGOUT("Error while waiting for autoneg to complete\n");
return ret_val;
@@ -1693,8 +1679,7 @@
DEBUGFUNC("e1000_setup_copper_link_generic");
if (hw->mac.autoneg) {
- /*
- * Setup autoneg and flow control advertisement and perform
+ /* Setup autoneg and flow control advertisement and perform
* autonegotiation.
*/
ret_val = e1000_copper_link_autoneg(hw);
@@ -1701,8 +1686,7 @@
if (ret_val)
return ret_val;
} else {
- /*
- * PHY will be set to 10H, 10F, 100H or 100F
+ /* PHY will be set to 10H, 10F, 100H or 100F
* depending on user settings.
*/
DEBUGOUT("Forcing Speed and Duplex\n");
@@ -1713,8 +1697,7 @@
}
}
- /*
- * Check link status. Wait up to 100 microseconds for link to become
+ /* Check link status. Wait up to 100 microseconds for link to become
* valid.
*/
ret_val = e1000_phy_has_link_generic(hw, COPPER_LINK_UP_LIMIT, 10,
@@ -1760,8 +1743,7 @@
if (ret_val)
return ret_val;
- /*
- * Clear Auto-Crossover to force MDI manually. IGP requires MDI
+ /* Clear Auto-Crossover to force MDI manually. IGP requires MDI
* forced whenever speed and duplex are forced.
*/
ret_val = phy->ops.read_reg(hw, IGP01E1000_PHY_PORT_CTRL, &phy_data);
@@ -1817,18 +1799,22 @@
DEBUGFUNC("e1000_phy_force_speed_duplex_m88");
- /*
- * Clear Auto-Crossover to force MDI manually. M88E1000 requires MDI
- * forced whenever speed and duplex are forced.
- */
- ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
- if (ret_val)
- return ret_val;
+ /* I210 and I211 devices support Auto-Crossover in forced operation. */
+ if (phy->type != e1000_phy_i210) {
+ /* Clear Auto-Crossover to force MDI manually. M88E1000
+ * requires MDI forced whenever speed and duplex are forced.
+ */
+ ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_CTRL,
+ &phy_data);
+ if (ret_val)
+ return ret_val;
- phy_data &= ~M88E1000_PSCR_AUTO_X_MODE;
- ret_val = phy->ops.write_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data);
- if (ret_val)
- return ret_val;
+ phy_data &= ~M88E1000_PSCR_AUTO_X_MODE;
+ ret_val = phy->ops.write_reg(hw, M88E1000_PHY_SPEC_CTRL,
+ phy_data);
+ if (ret_val)
+ return ret_val;
+ }
DEBUGOUT1("M88E1000 PSCR: %X\n", phy_data);
@@ -1874,8 +1860,7 @@
if (!reset_dsp) {
DEBUGOUT("Link taking longer than expected.\n");
} else {
- /*
- * We didn't get link.
+ /* We didn't get link.
* Reset the DSP and cross our fingers.
*/
ret_val = phy->ops.write_reg(hw,
@@ -1909,8 +1894,7 @@
if (ret_val)
return ret_val;
- /*
- * Resetting the phy means we need to re-force TX_CLK in the
+ /* Resetting the phy means we need to re-force TX_CLK in the
* Extended PHY Specific Control Register to 25MHz clock from
* the reset value of 2.5MHz.
*/
@@ -1919,8 +1903,7 @@
if (ret_val)
return ret_val;
- /*
- * In addition, we must re-enable CRS on Tx for both half and full
+ /* In addition, we must re-enable CRS on Tx for both half and full
* duplex.
*/
ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
@@ -2045,11 +2028,10 @@
if (mac->forced_speed_duplex & E1000_ALL_100_SPEED) {
ctrl |= E1000_CTRL_SPD_100;
*phy_ctrl |= MII_CR_SPEED_100;
- *phy_ctrl &= ~(MII_CR_SPEED_1000 | MII_CR_SPEED_10);
+ *phy_ctrl &= ~MII_CR_SPEED_1000;
DEBUGOUT("Forcing 100mb\n");
} else {
ctrl &= ~(E1000_CTRL_SPD_1000 | E1000_CTRL_SPD_100);
- *phy_ctrl |= MII_CR_SPEED_10;
*phy_ctrl &= ~(MII_CR_SPEED_1000 | MII_CR_SPEED_100);
DEBUGOUT("Forcing 10mb\n");
}
@@ -2094,8 +2076,7 @@
data);
if (ret_val)
return ret_val;
- /*
- * LPLU and SmartSpeed are mutually exclusive. LPLU is used
+ /* LPLU and SmartSpeed are mutually exclusive. LPLU is used
* during Dx states where the power conservation is most
* important. During driver activity we should enable
* SmartSpeed, so performance is maintained.
@@ -2238,8 +2219,7 @@
DEBUGFUNC("e1000_check_polarity_igp");
- /*
- * Polarity is determined based on the speed of
+ /* Polarity is determined based on the speed of
* our connection.
*/
ret_val = phy->ops.read_reg(hw, IGP01E1000_PHY_PORT_STATUS, &data);
@@ -2251,8 +2231,7 @@
offset = IGP01E1000_PHY_PCS_INIT_REG;
mask = IGP01E1000_PHY_POLARITY_MASK;
} else {
- /*
- * This really only applies to 10Mbps since
+ /* This really only applies to 10Mbps since
* there is no polarity for 100Mbps (always 0).
*/
offset = IGP01E1000_PHY_PORT_STATUS;
@@ -2283,8 +2262,7 @@
DEBUGFUNC("e1000_check_polarity_ife");
- /*
- * Polarity is determined based on the reversal feature being enabled.
+ /* Polarity is determined based on the reversal feature being enabled.
*/
if (phy->polarity_correction) {
offset = IFE_PHY_EXTENDED_STATUS_CONTROL;
@@ -2305,18 +2283,18 @@
}
/**
- * e1000_wait_autoneg_generic - Wait for auto-neg completion
+ * e1000_wait_autoneg - Wait for auto-neg completion
* @hw: pointer to the HW structure
*
* Waits for auto-negotiation to complete or for the auto-negotiation time
* limit to expire, which ever happens first.
**/
-s32 e1000_wait_autoneg_generic(struct e1000_hw *hw)
+static s32 e1000_wait_autoneg(struct e1000_hw *hw)
{
s32 ret_val = E1000_SUCCESS;
u16 i, phy_status;
- DEBUGFUNC("e1000_wait_autoneg_generic");
+ DEBUGFUNC("e1000_wait_autoneg");
if (!hw->phy.ops.read_reg)
return E1000_SUCCESS;
@@ -2334,8 +2312,7 @@
msec_delay(100);
}
- /*
- * PHY_AUTO_NEG_TIME expiration doesn't guarantee auto-negotiation
+ /* PHY_AUTO_NEG_TIME expiration doesn't guarantee auto-negotiation
* has completed.
*/
return ret_val;
@@ -2362,15 +2339,13 @@
return E1000_SUCCESS;
for (i = 0; i < iterations; i++) {
- /*
- * Some PHYs require the PHY_STATUS register to be read
+ /* Some PHYs require the PHY_STATUS register to be read
* twice due to the link bit being sticky. No harm doing
* it across the board.
*/
ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, &phy_status);
if (ret_val)
- /*
- * If the first read fails, another entity may have
+ /* If the first read fails, another entity may have
* ownership of the resources, wait and try again to
* see if they have relinquished the resources yet.
*/
@@ -2436,7 +2411,8 @@
{
struct e1000_phy_info *phy = &hw->phy;
s32 ret_val;
- u16 phy_data, phy_data2, index, default_page, is_cm;
+ u16 phy_data, phy_data2, is_cm;
+ u16 index, default_page;
DEBUGFUNC("e1000_get_cable_length_m88_gen2");
@@ -2574,8 +2550,7 @@
if (ret_val)
return ret_val;
- /*
- * Getting bits 15:9, which represent the combination of
+ /* Getting bits 15:9, which represent the combination of
* coarse and fine gain values. The result is a number
* that can be put into the lookup table to obtain the
* approximate cable length.
@@ -2961,15 +2936,13 @@
hw->phy.ops.write_reg(hw, 0x1796, 0x0008);
/* Change cg_icount + enable integbp for channels BCD */
hw->phy.ops.write_reg(hw, 0x1798, 0xD008);
- /*
- * Change cg_icount + enable integbp + change prop_factor_master
+ /* Change cg_icount + enable integbp + change prop_factor_master
* to 8 for channel A
*/
hw->phy.ops.write_reg(hw, 0x1898, 0xD918);
/* Disable AHT in Slave mode on channel A */
hw->phy.ops.write_reg(hw, 0x187A, 0x0800);
- /*
- * Enable LPLU and disable AN to 1000 in non-D0a states,
+ /* Enable LPLU and disable AN to 1000 in non-D0a states,
* Enable SPD+B2B
*/
hw->phy.ops.write_reg(hw, 0x0019, 0x008D);
@@ -3030,6 +3003,9 @@
case I82579_E_PHY_ID:
phy_type = e1000_phy_82579;
break;
+ case I217_E_PHY_ID:
+ phy_type = e1000_phy_i217;
+ break;
case I82580_I_PHY_ID:
phy_type = e1000_phy_82580;
break;
@@ -3067,8 +3043,7 @@
e1000_get_phy_id(hw);
phy_type = e1000_get_phy_type_from_id(hw->phy.id);
- /*
- * If phy_type is valid, break - we found our
+ /* If phy_type is valid, break - we found our
* PHY address
*/
if (phy_type != e1000_phy_unknown)
@@ -3130,8 +3105,7 @@
if (offset > MAX_PHY_MULTI_PAGE_REG) {
u32 page_shift, page_select;
- /*
- * Page select is register 31 for phy address 1 and 22 for
+ /* Page select is register 31 for phy address 1 and 22 for
* phy address 2 and 3. Page select is shifted only for
* phy address 1.
*/
@@ -3191,8 +3165,7 @@
if (offset > MAX_PHY_MULTI_PAGE_REG) {
u32 page_shift, page_select;
- /*
- * Page select is register 31 for phy address 1 and 22 for
+ /* Page select is register 31 for phy address 1 and 22 for
* phy address 2 and 3. Page select is shifted only for
* phy address 1.
*/
@@ -3249,7 +3222,6 @@
hw->phy.addr = 1;
if (offset > MAX_PHY_MULTI_PAGE_REG) {
-
/* Page is shifted left, PHY expects (page x 32) */
ret_val = e1000_write_phy_reg_mdic(hw, BM_PHY_PAGE_SELECT,
page);
@@ -3346,8 +3318,7 @@
return ret_val;
}
- /*
- * Enable both PHY wakeup mode and Wakeup register page writes.
+ /* Enable both PHY wakeup mode and Wakeup register page writes.
* Prevent a power state change by disabling ME and Host PHY wakeup.
*/
temp = *phy_reg;
@@ -3361,8 +3332,7 @@
return ret_val;
}
- /*
- * Select Host Wakeup Registers page - caller now able to write
+ /* Select Host Wakeup Registers page - caller now able to write
* registers on the Wakeup registers page
*/
return e1000_set_page_igp(hw, (BM_WUC_PAGE << IGP_PAGE_SHIFT));
@@ -3381,7 +3351,7 @@
**/
s32 e1000_disable_phy_wakeup_reg_access_bm(struct e1000_hw *hw, u16 *phy_reg)
{
- s32 ret_val = E1000_SUCCESS;
+ s32 ret_val;
DEBUGFUNC("e1000_disable_phy_wakeup_reg_access_bm");
@@ -3434,6 +3404,7 @@
{
s32 ret_val;
u16 reg = BM_PHY_REG_NUM(offset);
+ u16 page = BM_PHY_REG_PAGE(offset);
u16 phy_reg = 0;
DEBUGFUNC("e1000_access_phy_wakeup_reg_bm");
@@ -3687,8 +3658,7 @@
if (page == HV_INTC_FC_PAGE_START)
page = 0;
- /*
- * Workaround MDIO accesses being disabled after entering IEEE
+ /* Workaround MDIO accesses being disabled after entering IEEE
* Power Down (when bit 11 of the PHY Control register is set)
*/
if ((hw->phy.type == e1000_phy_82578) &&
@@ -3801,8 +3771,8 @@
u16 *data, bool read)
{
s32 ret_val;
- u32 addr_reg = 0;
- u32 data_reg = 0;
+ u32 addr_reg;
+ u32 data_reg;
DEBUGFUNC("e1000_access_phy_debug_regs_hv");
@@ -3875,8 +3845,8 @@
/* flush the packets in the fifo buffer */
ret_val = hw->phy.ops.write_reg(hw, HV_MUX_DATA_CTRL,
- HV_MUX_DATA_CTRL_GEN_TO_MAC |
- HV_MUX_DATA_CTRL_FORCE_SPEED);
+ (HV_MUX_DATA_CTRL_GEN_TO_MAC |
+ HV_MUX_DATA_CTRL_FORCE_SPEED));
if (ret_val)
return ret_val;
@@ -4044,7 +4014,7 @@
I82577_DSTATUS_CABLE_LENGTH_SHIFT;
if (length == E1000_CABLE_LENGTH_UNDEFINED)
- ret_val = -E1000_ERR_PHY;
+ return -E1000_ERR_PHY;
phy->cable_length = length;
@@ -4113,3 +4083,4 @@
hw->phy.ops.release(hw);
return ret_val;
}
+
Property changes on: trunk/sys/dev/e1000/e1000_phy.c
___________________________________________________________________
Deleted: cvs2svn:cvs-rev
## -1 +0,0 ##
-1.4
\ No newline at end of property
Modified: trunk/sys/dev/e1000/e1000_phy.h
===================================================================
--- trunk/sys/dev/e1000/e1000_phy.h 2013-12-28 14:30:04 UTC (rev 6559)
+++ trunk/sys/dev/e1000/e1000_phy.h 2013-12-28 14:30:47 UTC (rev 6560)
@@ -1,6 +1,7 @@
+/* $MidnightBSD$ */
/******************************************************************************
- Copyright (c) 2001-2012, Intel Corporation
+ Copyright (c) 2001-2013, Intel Corporation
All rights reserved.
Redistribution and use in source and binary forms, with or without
@@ -30,7 +31,7 @@
POSSIBILITY OF SUCH DAMAGE.
******************************************************************************/
-/*$MidnightBSD$*/
+/*$FreeBSD: release/9.2.0/sys/dev/e1000/e1000_phy.h 248292 2013-03-14 22:55:59Z jfv $*/
#ifndef _E1000_PHY_H_
#define _E1000_PHY_H_
@@ -78,13 +79,11 @@
s32 e1000_read_phy_reg_m88(struct e1000_hw *hw, u32 offset, u16 *data);
s32 e1000_set_d3_lplu_state_generic(struct e1000_hw *hw, bool active);
s32 e1000_setup_copper_link_generic(struct e1000_hw *hw);
-s32 e1000_wait_autoneg_generic(struct e1000_hw *hw);
s32 e1000_write_kmrn_reg_generic(struct e1000_hw *hw, u32 offset, u16 data);
s32 e1000_write_kmrn_reg_locked(struct e1000_hw *hw, u32 offset, u16 data);
s32 e1000_write_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 data);
s32 e1000_write_phy_reg_igp_locked(struct e1000_hw *hw, u32 offset, u16 data);
s32 e1000_write_phy_reg_m88(struct e1000_hw *hw, u32 offset, u16 data);
-s32 e1000_phy_reset_dsp(struct e1000_hw *hw);
s32 e1000_phy_has_link_generic(struct e1000_hw *hw, u32 iterations,
u32 usec_interval, bool *success);
s32 e1000_phy_init_script_igp3(struct e1000_hw *hw);
@@ -127,7 +126,6 @@
#define IGP01E1000_PHY_PORT_CTRL 0x12 /* Control */
#define IGP01E1000_PHY_LINK_HEALTH 0x13 /* PHY Link Health */
#define IGP01E1000_GMII_FIFO 0x14 /* GMII FIFO */
-#define IGP01E1000_PHY_CHANNEL_QUALITY 0x15 /* PHY Channel Quality */
#define IGP02E1000_PHY_POWER_MGMT 0x19 /* Power Management */
#define IGP01E1000_PHY_PAGE_SELECT 0x1F /* Page Select */
#define BM_PHY_PAGE_SELECT 22 /* Page Select for BM */
@@ -147,7 +145,6 @@
/* BM/HV Specific Registers */
#define BM_PORT_CTRL_PAGE 769
-#define BM_PCIE_PAGE 770
#define BM_WUC_PAGE 800
#define BM_WUC_ADDRESS_OPCODE 0x11
#define BM_WUC_DATA_OPCODE 0x12
@@ -188,7 +185,6 @@
#define I82577_PHY_STATUS2_MDIX 0x0800
#define I82577_PHY_STATUS2_SPEED_MASK 0x0300
#define I82577_PHY_STATUS2_SPEED_1000MBPS 0x0200
-#define I82577_PHY_STATUS2_SPEED_100MBPS 0x0100
/* I82577 PHY Control 2 */
#define I82577_PHY_CTRL2_MANUAL_MDIX 0x0200
@@ -204,14 +200,13 @@
#define E1000_82580_PM_SPD 0x0001 /* Smart Power Down */
#define E1000_82580_PM_D0_LPLU 0x0002 /* For D0a states */
#define E1000_82580_PM_D3_LPLU 0x0004 /* For all other states */
+#define E1000_82580_PM_GO_LINKD 0x0020 /* Go Link Disconnect */
/* BM PHY Copper Specific Control 1 */
#define BM_CS_CTRL1 16
-#define BM_CS_CTRL1_ENERGY_DETECT 0x0300 /* Enable Energy Detect */
/* BM PHY Copper Specific Status */
#define BM_CS_STATUS 17
-#define BM_CS_STATUS_ENERGY_DETECT 0x0010 /* Energy Detect Status */
#define BM_CS_STATUS_LINK_UP 0x0400
#define BM_CS_STATUS_RESOLVED 0x0800
#define BM_CS_STATUS_SPEED_MASK 0xC000
@@ -257,9 +252,6 @@
#define IGP02E1000_AGC_LENGTH_MASK 0x7F
#define IGP02E1000_AGC_RANGE 15
-#define IGP03E1000_PHY_MISC_CTRL 0x1B
-#define IGP03E1000_PHY_MISC_DUPLEX_MANUAL_SET 0x1000 /* Manually Set Duplex */
-
#define E1000_CABLE_LENGTH_UNDEFINED 0xFF
#define E1000_KMRNCTRLSTA_OFFSET 0x001F0000
@@ -272,7 +264,7 @@
#define E1000_KMRNCTRLSTA_IBIST_DISABLE 0x0200 /* Kumeran IBIST Disable */
#define E1000_KMRNCTRLSTA_DIAG_NELPBK 0x1000 /* Nearend Loopback mode */
#define E1000_KMRNCTRLSTA_K1_CONFIG 0x7
-#define E1000_KMRNCTRLSTA_K1_ENABLE 0x0002
+#define E1000_KMRNCTRLSTA_K1_ENABLE 0x0002 /* enable K1 */
#define E1000_KMRNCTRLSTA_HD_CTRL 0x10 /* Kumeran HD Control */
#define IFE_PHY_EXTENDED_STATUS_CONTROL 0x10
@@ -286,7 +278,6 @@
/* IFE PHY Special Control */
#define IFE_PSC_AUTO_POLARITY_DISABLE 0x0010
#define IFE_PSC_FORCE_POLARITY 0x0020
-#define IFE_PSC_DISABLE_DYNAMIC_POWER_DOWN 0x0100
/* IFE PHY Special Control and LED Control */
#define IFE_PSCL_PROBE_MODE 0x0020
Property changes on: trunk/sys/dev/e1000/e1000_phy.h
___________________________________________________________________
Deleted: cvs2svn:cvs-rev
## -1 +0,0 ##
-1.4
\ No newline at end of property
Modified: trunk/sys/dev/e1000/e1000_regs.h
===================================================================
--- trunk/sys/dev/e1000/e1000_regs.h 2013-12-28 14:30:04 UTC (rev 6559)
+++ trunk/sys/dev/e1000/e1000_regs.h 2013-12-28 14:30:47 UTC (rev 6560)
@@ -1,6 +1,7 @@
+/* $MidnightBSD$ */
/******************************************************************************
- Copyright (c) 2001-2012, Intel Corporation
+ Copyright (c) 2001-2013, Intel Corporation
All rights reserved.
Redistribution and use in source and binary forms, with or without
@@ -30,7 +31,7 @@
POSSIBILITY OF SUCH DAMAGE.
******************************************************************************/
-/*$MidnightBSD$*/
+/*$FreeBSD: release/9.2.0/sys/dev/e1000/e1000_regs.h 248292 2013-03-14 22:55:59Z jfv $*/
#ifndef _E1000_REGS_H_
#define _E1000_REGS_H_
@@ -55,9 +56,11 @@
#define E1000_SCTL 0x00024 /* SerDes Control - RW */
#define E1000_FCAL 0x00028 /* Flow Control Address Low - RW */
#define E1000_FCAH 0x0002C /* Flow Control Address High -RW */
-#define E1000_FEXT 0x0002C /* Future Extended - RW */
+#define E1000_FEXTNVM 0x00028 /* Future Extended NVM - RW */
+#define E1000_FEXTNVM3 0x0003C /* Future Extended NVM 3 - RW */
#define E1000_FEXTNVM4 0x00024 /* Future Extended NVM 4 - RW */
-#define E1000_FEXTNVM 0x00028 /* Future Extended NVM - RW */
+#define E1000_FEXTNVM6 0x00010 /* Future Extended NVM 6 - RW */
+#define E1000_FEXTNVM7 0x000E4 /* Future Extended NVM 7 - RW */
#define E1000_FCT 0x00030 /* Flow Control Type - RW */
#define E1000_CONNSW 0x00034 /* Copper/Fiber switch control - RW */
#define E1000_VET 0x00038 /* VLAN Ether Type - RW */
@@ -70,6 +73,7 @@
#define E1000_IVAR 0x000E4 /* Interrupt Vector Allocation Register - RW */
#define E1000_SVCR 0x000F0
#define E1000_SVT 0x000F4
+#define E1000_LPIC 0x000FC /* Low Power IDLE control */
#define E1000_RCTL 0x00100 /* Rx Control - RW */
#define E1000_FCTTV 0x00170 /* Flow Control Transmit Timer Value - RW */
#define E1000_TXCW 0x00178 /* Tx Configuration Word - RW */
@@ -97,6 +101,7 @@
#define E1000_POEMB E1000_PHY_CTRL /* PHY OEM Bits */
#define E1000_PBA 0x01000 /* Packet Buffer Allocation - RW */
#define E1000_PBS 0x01008 /* Packet Buffer Size */
+#define E1000_PBECCSTS 0x0100C /* Packet Buffer ECC Status - RW */
#define E1000_EEMNGCTL 0x01010 /* MNG EEprom Control */
#define E1000_EEARBC 0x01024 /* EEPROM Auto Read Bus Control */
#define E1000_FLASHT 0x01028 /* FLASH Timer Register */
@@ -129,7 +134,11 @@
#define E1000_FCRTL 0x02160 /* Flow Control Receive Threshold Low - RW */
#define E1000_FCRTH 0x02168 /* Flow Control Receive Threshold High - RW */
#define E1000_PSRCTL 0x02170 /* Packet Split Receive Control - RW */
-#define E1000_RDFPCQ(_n) (0x02430 + (0x4 * (_n)))
+#define E1000_RDFH 0x02410 /* Rx Data FIFO Head - RW */
+#define E1000_RDFT 0x02418 /* Rx Data FIFO Tail - RW */
+#define E1000_RDFHS 0x02420 /* Rx Data FIFO Head Saved - RW */
+#define E1000_RDFTS 0x02428 /* Rx Data FIFO Tail Saved - RW */
+#define E1000_RDFPC 0x02430 /* Rx Data FIFO Packet Count - RW */
#define E1000_PBRTH 0x02458 /* PB Rx Arbitration Threshold - RW */
#define E1000_FCRTV 0x02460 /* Flow Control Refresh Timer Value - RW */
/* Split and Replication Rx Control - RW */
@@ -200,8 +209,7 @@
/* Queues packet buffer size masks where _n can be 0-3 and _s 0-63 [kB] */
#define E1000_I210_TXPBS_SIZE(_n, _s) ((_s) << (6 * _n))
-/*
- * Convenience macros
+/* Convenience macros
*
* Note: "_n" is the queue number of the register to be written to.
*
@@ -413,8 +421,7 @@
#define E1000_LSECTXKEY1(_n) (0x0B030 + (0x04 * (_n)))
#define E1000_LSECRXSA(_n) (0x0B310 + (0x04 * (_n))) /* Rx SAs - RW */
#define E1000_LSECRXPN(_n) (0x0B330 + (0x04 * (_n))) /* Rx SAs - RW */
-/*
- * LinkSec Rx Keys - where _n is the SA no. and _m the 4 dwords of the 128 bit
+/* LinkSec Rx Keys - where _n is the SA no. and _m the 4 dwords of the 128 bit
* key - RW.
*/
#define E1000_LSECRXKEY(_n, _m) (0x0B350 + (0x10 * (_n)) + (0x04 * (_m)))
@@ -454,7 +461,6 @@
#define E1000_PCS_LPAB 0x0421C /* Link Partner Ability - RW */
#define E1000_PCS_NPTX 0x04220 /* AN Next Page Transmit - RW */
#define E1000_PCS_LPABNP 0x04224 /* Link Partner Ability Next Pg - RW */
-#define E1000_1GSTAT_RCV 0x04228 /* 1GSTAT Code Violation Pkt Cnt - RW */
#define E1000_RXCSUM 0x05000 /* Rx Checksum Control - RW */
#define E1000_RLPML 0x05004 /* Rx Long Packet Max Length */
#define E1000_RFCTL 0x05008 /* Receive Filter Control*/
@@ -489,7 +495,6 @@
#define E1000_KMRNCTRLSTA 0x00034 /* MAC-PHY interface - RW */
-#define E1000_MDPHYA 0x0003C /* PHY address - RW */
#define E1000_MANC2H 0x05860 /* Management Control To Host - RW */
/* Management Decision Filters */
#define E1000_MDEF(_n) (0x05890 + (4 * (_n)))
@@ -522,15 +527,6 @@
#define E1000_IMIREXT(_i) (0x05AA0 + ((_i) * 4)) /* Immediate INTR Ext*/
#define E1000_IMIRVP 0x05AC0 /* Immediate INT Rx VLAN Priority -RW */
#define E1000_MSIXBM(_i) (0x01600 + ((_i) * 4)) /* MSI-X Alloc Reg -RW */
-/* MSI-X Table entry addr low reg - RW */
-#define E1000_MSIXTADD(_i) (0x0C000 + ((_i) * 0x10))
-/* MSI-X Table entry addr upper reg - RW */
-#define E1000_MSIXTUADD(_i) (0x0C004 + ((_i) * 0x10))
-/* MSI-X Table entry message reg - RW */
-#define E1000_MSIXTMSG(_i) (0x0C008 + ((_i) * 0x10))
-/* MSI-X Table entry vector ctrl reg - RW */
-#define E1000_MSIXVCTRL(_i) (0x0C00C + ((_i) * 0x10))
-#define E1000_MSIXPBA 0x0E000 /* MSI-X Pending bit array */
#define E1000_RETA(_i) (0x05C00 + ((_i) * 4)) /* Redirection Table - RW */
#define E1000_RSSRK(_i) (0x05C80 + ((_i) * 4)) /* RSS Random Key - RW */
#define E1000_RSSIM 0x05864 /* RSS Interrupt Mask */
@@ -580,8 +576,12 @@
#define E1000_SYSTIML 0x0B600 /* System time register Low - RO */
#define E1000_SYSTIMH 0x0B604 /* System time register High - RO */
#define E1000_TIMINCA 0x0B608 /* Increment attributes register - RW */
+#define E1000_TIMADJL 0x0B60C /* Time sync time adjustment offset Low - RW */
+#define E1000_TIMADJH 0x0B610 /* Time sync time adjustment offset High - RW */
#define E1000_TSAUXC 0x0B640 /* Timesync Auxiliary Control register */
#define E1000_SYSTIMR 0x0B6F8 /* System time register Residue */
+#define E1000_TSICR 0x0B66C /* Interrupt Cause Register */
+#define E1000_TSIM 0x0B674 /* Interrupt Mask Register */
#define E1000_RXMTRL 0x0B634 /* Time sync Rx EtherType and Msg Type - RW */
#define E1000_RXUDP 0x0B638 /* Time Sync Rx UDP Port - RW */
@@ -671,8 +671,6 @@
#define E1000_O2BGPTC 0x08FE4 /* OS2BMC packets received by BMC */
#define E1000_O2BSPC 0x0415C /* OS2BMC packets transmitted by host */
-#define E1000_LTRMINV 0x5BB0 /* LTR Minimum Value */
-#define E1000_LTRMAXV 0x5BB4 /* LTR Maximum Value */
#define E1000_DOBFFCTL 0x3F24 /* DMA OBFF Control Register */
Property changes on: trunk/sys/dev/e1000/e1000_regs.h
___________________________________________________________________
Deleted: cvs2svn:cvs-rev
## -1 +0,0 ##
-1.4
\ No newline at end of property
Modified: trunk/sys/dev/e1000/e1000_vf.c
===================================================================
--- trunk/sys/dev/e1000/e1000_vf.c 2013-12-28 14:30:04 UTC (rev 6559)
+++ trunk/sys/dev/e1000/e1000_vf.c 2013-12-28 14:30:47 UTC (rev 6560)
@@ -1,3 +1,4 @@
+/* $MidnightBSD$ */
/******************************************************************************
Copyright (c) 2001-2011, Intel Corporation
@@ -30,7 +31,7 @@
POSSIBILITY OF SUCH DAMAGE.
******************************************************************************/
-/*$MidnightBSD$*/
+/*$FreeBSD: release/9.2.0/sys/dev/e1000/e1000_vf.c 235527 2012-05-16 22:22:52Z jfv $*/
#include "e1000_api.h"
Property changes on: trunk/sys/dev/e1000/e1000_vf.c
___________________________________________________________________
Deleted: cvs2svn:cvs-rev
## -1 +0,0 ##
-1.3
\ No newline at end of property
Modified: trunk/sys/dev/e1000/e1000_vf.h
===================================================================
--- trunk/sys/dev/e1000/e1000_vf.h 2013-12-28 14:30:04 UTC (rev 6559)
+++ trunk/sys/dev/e1000/e1000_vf.h 2013-12-28 14:30:47 UTC (rev 6560)
@@ -1,3 +1,4 @@
+/* $MidnightBSD$ */
/******************************************************************************
Copyright (c) 2001-2010, Intel Corporation
@@ -30,7 +31,7 @@
POSSIBILITY OF SUCH DAMAGE.
******************************************************************************/
-/*$MidnightBSD$*/
+/*$FreeBSD: release/9.2.0/sys/dev/e1000/e1000_vf.h 218530 2011-02-11 01:00:26Z jfv $*/
#ifndef _E1000_VF_H_
#define _E1000_VF_H_
Property changes on: trunk/sys/dev/e1000/e1000_vf.h
___________________________________________________________________
Deleted: cvs2svn:cvs-rev
## -1 +0,0 ##
-1.3
\ No newline at end of property
Modified: trunk/sys/dev/e1000/if_em.c
===================================================================
--- trunk/sys/dev/e1000/if_em.c 2013-12-28 14:30:04 UTC (rev 6559)
+++ trunk/sys/dev/e1000/if_em.c 2013-12-28 14:30:47 UTC (rev 6560)
@@ -1,6 +1,7 @@
+/* $MidnightBSD$ */
/******************************************************************************
- Copyright (c) 2001-2011, Intel Corporation
+ Copyright (c) 2001-2013, Intel Corporation
All rights reserved.
Redistribution and use in source and binary forms, with or without
@@ -30,12 +31,13 @@
POSSIBILITY OF SUCH DAMAGE.
******************************************************************************/
-/*$MidnightBSD$*/
+/*$FreeBSD: release/9.2.0/sys/dev/e1000/if_em.c 254573 2013-08-20 17:50:30Z jfv $*/
+#include "opt_inet.h"
+#include "opt_inet6.h"
+
#ifdef HAVE_KERNEL_OPTION_HEADERS
#include "opt_device_polling.h"
-#include "opt_inet.h"
-#include "opt_inet6.h"
#endif
#include <sys/param.h>
@@ -94,7 +96,7 @@
/*********************************************************************
* Driver version:
*********************************************************************/
-char em_driver_version[] = "7.3.2";
+char em_driver_version[] = "7.3.8";
/*********************************************************************
* PCI Device ID Table
@@ -172,6 +174,12 @@
{ 0x8086, E1000_DEV_ID_PCH_D_HV_DC, PCI_ANY_ID, PCI_ANY_ID, 0},
{ 0x8086, E1000_DEV_ID_PCH2_LV_LM, PCI_ANY_ID, PCI_ANY_ID, 0},
{ 0x8086, E1000_DEV_ID_PCH2_LV_V, PCI_ANY_ID, PCI_ANY_ID, 0},
+ { 0x8086, E1000_DEV_ID_PCH_LPT_I217_LM, PCI_ANY_ID, PCI_ANY_ID, 0},
+ { 0x8086, E1000_DEV_ID_PCH_LPT_I217_V, PCI_ANY_ID, PCI_ANY_ID, 0},
+ { 0x8086, E1000_DEV_ID_PCH_LPTLP_I218_LM,
+ PCI_ANY_ID, PCI_ANY_ID, 0},
+ { 0x8086, E1000_DEV_ID_PCH_LPTLP_I218_V,
+ PCI_ANY_ID, PCI_ANY_ID, 0},
/* required last entry */
{ 0, 0, 0, 0, 0}
};
@@ -309,7 +317,7 @@
DEVMETHOD(device_shutdown, em_shutdown),
DEVMETHOD(device_suspend, em_suspend),
DEVMETHOD(device_resume, em_resume),
- {0, 0}
+ DEVMETHOD_END
};
static driver_t em_driver = {
@@ -329,6 +337,9 @@
#define EM_USECS_TO_TICKS(usecs) ((1000 * (usecs) + 512) / 1024)
#define M_TSO_LEN 66
+#define MAX_INTS_PER_SEC 8000
+#define DEFAULT_ITR (1000000000/(MAX_INTS_PER_SEC * 256))
+
/* Allow common code without TSO */
#ifndef CSUM_TSO
#define CSUM_TSO 0
@@ -520,7 +531,8 @@
(hw->mac.type == e1000_ich9lan) ||
(hw->mac.type == e1000_ich10lan) ||
(hw->mac.type == e1000_pchlan) ||
- (hw->mac.type == e1000_pch2lan)) {
+ (hw->mac.type == e1000_pch2lan) ||
+ (hw->mac.type == e1000_pch_lpt)) {
int rid = EM_BAR_TYPE_FLASH;
adapter->flash = bus_alloc_resource_any(dev,
SYS_RES_MEMORY, &rid, RF_ACTIVE);
@@ -563,6 +575,11 @@
&adapter->tx_abs_int_delay,
E1000_REGISTER(hw, E1000_TADV),
em_tx_abs_int_delay_dflt);
+ em_add_int_delay_sysctl(adapter, "itr",
+ "interrupt delay limit in usecs/4",
+ &adapter->tx_itr,
+ E1000_REGISTER(hw, E1000_ITR),
+ DEFAULT_ITR);
/* Sysctl for limiting the amount of work done in the taskqueue */
em_set_sysctl_value(adapter, "rx_processing_limit",
@@ -605,8 +622,8 @@
* Set the frame limits assuming
* standard ethernet sized frames.
*/
- adapter->max_frame_size = ETHERMTU + ETHER_HDR_LEN + ETHERNET_FCS_SIZE;
- adapter->min_frame_size = ETH_ZLEN + ETHERNET_FCS_SIZE;
+ adapter->hw.mac.max_frame_size =
+ ETHERMTU + ETHER_HDR_LEN + ETHERNET_FCS_SIZE;
/*
* This controls when hardware reports transmit completion
@@ -905,28 +922,29 @@
}
enq = 0;
- if (m == NULL) {
- next = drbr_dequeue(ifp, txr->br);
- } else if (drbr_needs_enqueue(ifp, txr->br)) {
- if ((err = drbr_enqueue(ifp, txr->br, m)) != 0)
+ if (m != NULL) {
+ err = drbr_enqueue(ifp, txr->br, m);
+ if (err)
return (err);
- next = drbr_dequeue(ifp, txr->br);
- } else
- next = m;
+ }
/* Process the queue */
- while (next != NULL) {
+ while ((next = drbr_peek(ifp, txr->br)) != NULL) {
if ((err = em_xmit(txr, &next)) != 0) {
- if (next != NULL)
- err = drbr_enqueue(ifp, txr->br, next);
- break;
+ if (next == NULL)
+ drbr_advance(ifp, txr->br);
+ else
+ drbr_putback(ifp, txr->br, next);
+ break;
}
+ drbr_advance(ifp, txr->br);
enq++;
- drbr_stats_update(ifp, next->m_pkthdr.len, next->m_flags);
+ ifp->if_obytes += next->m_pkthdr.len;
+ if (next->m_flags & M_MCAST)
+ ifp->if_omcasts++;
ETHER_BPF_MTAP(ifp, next);
if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0)
break;
- next = drbr_dequeue(ifp, txr->br);
}
if (enq > 0) {
@@ -1105,6 +1123,7 @@
case e1000_ich9lan:
case e1000_ich10lan:
case e1000_pch2lan:
+ case e1000_pch_lpt:
case e1000_82574:
case e1000_82583:
case e1000_80003es2lan: /* 9K Jumbo Frame size */
@@ -1128,7 +1147,7 @@
}
ifp->if_mtu = ifr->ifr_mtu;
- adapter->max_frame_size =
+ adapter->hw.mac.max_frame_size =
ifp->if_mtu + ETHER_HDR_LEN + ETHER_CRC_LEN;
em_init_locked(adapter);
EM_CORE_UNLOCK(adapter);
@@ -1323,9 +1342,9 @@
** Figure out the desired mbuf
** pool for doing jumbos
*/
- if (adapter->max_frame_size <= 2048)
+ if (adapter->hw.mac.max_frame_size <= 2048)
adapter->rx_mbuf_sz = MCLBYTES;
- else if (adapter->max_frame_size <= 4096)
+ else if (adapter->hw.mac.max_frame_size <= 4096)
adapter->rx_mbuf_sz = MJUMPAGESIZE;
else
adapter->rx_mbuf_sz = MJUM9BYTES;
@@ -1570,6 +1589,8 @@
bool more;
++rxr->rx_irq;
+ if (!(adapter->ifp->if_drv_flags & IFF_DRV_RUNNING))
+ return;
more = em_rxeof(rxr, adapter->rx_process_limit, NULL);
if (more)
taskqueue_enqueue(rxr->tq, &rxr->rx_task);
@@ -1827,7 +1848,7 @@
if (do_tso || (m_head->m_next != NULL &&
m_head->m_pkthdr.csum_flags & CSUM_OFFLOAD)) {
if (M_WRITABLE(*m_headp) == 0) {
- m_head = m_dup(*m_headp, M_DONTWAIT);
+ m_head = m_dup(*m_headp, M_NOWAIT);
m_freem(*m_headp);
if (m_head == NULL) {
*m_headp = NULL;
@@ -1944,7 +1965,7 @@
if (error == EFBIG && remap) {
struct mbuf *m;
- m = m_defrag(*m_headp, M_DONTWAIT);
+ m = m_defrag(*m_headp, M_NOWAIT);
if (m == NULL) {
adapter->mbuf_alloc_failed++;
m_freem(*m_headp);
@@ -2122,12 +2143,37 @@
static void
em_disable_promisc(struct adapter *adapter)
{
- u32 reg_rctl;
+ struct ifnet *ifp = adapter->ifp;
+ u32 reg_rctl;
+ int mcnt = 0;
reg_rctl = E1000_READ_REG(&adapter->hw, E1000_RCTL);
-
reg_rctl &= (~E1000_RCTL_UPE);
- reg_rctl &= (~E1000_RCTL_MPE);
+ if (ifp->if_flags & IFF_ALLMULTI)
+ mcnt = MAX_NUM_MULTICAST_ADDRESSES;
+ else {
+ struct ifmultiaddr *ifma;
+#if __FreeBSD_version < 800000
+ IF_ADDR_LOCK(ifp);
+#else
+ if_maddr_rlock(ifp);
+#endif
+ TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
+ if (ifma->ifma_addr->sa_family != AF_LINK)
+ continue;
+ if (mcnt == MAX_NUM_MULTICAST_ADDRESSES)
+ break;
+ mcnt++;
+ }
+#if __FreeBSD_version < 800000
+ IF_ADDR_UNLOCK(ifp);
+#else
+ if_maddr_runlock(ifp);
+#endif
+ }
+ /* Don't disable if in MAX groups */
+ if (mcnt < MAX_NUM_MULTICAST_ADDRESSES)
+ reg_rctl &= (~E1000_RCTL_MPE);
reg_rctl &= (~E1000_RCTL_SBP);
E1000_WRITE_REG(&adapter->hw, E1000_RCTL, reg_rctl);
}
@@ -2232,7 +2278,7 @@
/* Mask to use in the irq trigger */
if (adapter->msix_mem)
- trigger = rxr->ims; /* RX for 82574 */
+ trigger = rxr->ims;
else
trigger = E1000_ICS_RXDMT0;
@@ -2397,16 +2443,8 @@
device_t dev = adapter->dev;
/* Make sure our PCI config space has the necessary stuff set */
+ pci_enable_busmaster(dev);
adapter->hw.bus.pci_cmd_word = pci_read_config(dev, PCIR_COMMAND, 2);
- if (!((adapter->hw.bus.pci_cmd_word & PCIM_CMD_BUSMASTEREN) &&
- (adapter->hw.bus.pci_cmd_word & PCIM_CMD_MEMEN))) {
- device_printf(dev, "Memory Access and/or Bus Master bits "
- "were not set!\n");
- adapter->hw.bus.pci_cmd_word |=
- (PCIM_CMD_BUSMASTEREN | PCIM_CMD_MEMEN);
- pci_write_config(dev, PCIR_COMMAND,
- adapter->hw.bus.pci_cmd_word, 2);
- }
/* Save off the information about this board */
adapter->hw.vendor_id = pci_get_vendor(dev);
@@ -2705,7 +2743,7 @@
em_setup_msix(struct adapter *adapter)
{
device_t dev = adapter->dev;
- int val = 0;
+ int val;
/*
** Setup MSI/X for Hartwell: tests have shown
@@ -2719,7 +2757,7 @@
int rid = PCIR_BAR(EM_MSIX_BAR);
adapter->msix_mem = bus_alloc_resource_any(dev,
SYS_RES_MEMORY, &rid, RF_ACTIVE);
- if (!adapter->msix_mem) {
+ if (adapter->msix_mem == NULL) {
/* May not be enabled */
device_printf(adapter->dev,
"Unable to map MSIX table \n");
@@ -2726,30 +2764,36 @@
goto msi;
}
val = pci_msix_count(dev);
- /* We only need 3 vectors */
- if (val > 3)
+ /* We only need/want 3 vectors */
+ if (val >= 3)
val = 3;
- if ((val != 3) && (val != 5)) {
- bus_release_resource(dev, SYS_RES_MEMORY,
- PCIR_BAR(EM_MSIX_BAR), adapter->msix_mem);
- adapter->msix_mem = NULL;
+ else {
device_printf(adapter->dev,
- "MSIX: incorrect vectors, using MSI\n");
+ "MSIX: insufficient vectors, using MSI\n");
goto msi;
}
- if (pci_alloc_msix(dev, &val) == 0) {
+ if ((pci_alloc_msix(dev, &val) == 0) && (val == 3)) {
device_printf(adapter->dev,
"Using MSIX interrupts "
"with %d vectors\n", val);
+ return (val);
}
- return (val);
+ /*
+ ** If MSIX alloc failed or provided us with
+ ** less than needed, free and fall through to MSI
+ */
+ pci_release_msi(dev);
}
msi:
- val = pci_msi_count(dev);
- if (val == 1 && pci_alloc_msi(dev, &val) == 0) {
- adapter->msix = 1;
+ if (adapter->msix_mem != NULL) {
+ bus_release_resource(dev, SYS_RES_MEMORY,
+ PCIR_BAR(EM_MSIX_BAR), adapter->msix_mem);
+ adapter->msix_mem = NULL;
+ }
+ val = 1;
+ if (pci_alloc_msi(dev, &val) == 0) {
device_printf(adapter->dev,"Using an MSI interrupt\n");
return (val);
}
@@ -2812,7 +2856,7 @@
case e1000_ich9lan:
case e1000_ich10lan:
/* Boost Receive side for jumbo frames */
- if (adapter->max_frame_size > 4096)
+ if (adapter->hw.mac.max_frame_size > 4096)
pba = E1000_PBA_14K;
else
pba = E1000_PBA_10K;
@@ -2819,10 +2863,11 @@
break;
case e1000_pchlan:
case e1000_pch2lan:
+ case e1000_pch_lpt:
pba = E1000_PBA_26K;
break;
default:
- if (adapter->max_frame_size > 8192)
+ if (adapter->hw.mac.max_frame_size > 8192)
pba = E1000_PBA_40K; /* 40K for Rx, 24K for Tx */
else
pba = E1000_PBA_48K; /* 48K for Rx, 16K for Tx */
@@ -2845,7 +2890,7 @@
*/
rx_buffer_size = ((E1000_READ_REG(hw, E1000_PBA) & 0xffff) << 10 );
hw->fc.high_water = rx_buffer_size -
- roundup2(adapter->max_frame_size, 1024);
+ roundup2(adapter->hw.mac.max_frame_size, 1024);
hw->fc.low_water = hw->fc.high_water - 1500;
if (adapter->fc) /* locally set flow control value? */
@@ -2876,6 +2921,7 @@
hw->fc.refresh_time = 0x1000;
break;
case e1000_pch2lan:
+ case e1000_pch_lpt:
hw->fc.high_water = 0x5C20;
hw->fc.low_water = 0x5048;
hw->fc.pause_time = 0x0650;
@@ -3790,17 +3836,9 @@
EM_TX_LOCK_ASSERT(txr);
#ifdef DEV_NETMAP
- if (ifp->if_capenable & IFCAP_NETMAP) {
- struct netmap_adapter *na = NA(ifp);
-
- selwakeuppri(&na->tx_rings[txr->me].si, PI_NET);
- EM_TX_UNLOCK(txr);
- EM_CORE_LOCK(adapter);
- selwakeuppri(&na->tx_si, PI_NET);
- EM_CORE_UNLOCK(adapter);
- EM_TX_LOCK(txr);
+ if (netmap_tx_irq(ifp, txr->me |
+ (NETMAP_LOCKED_ENTER | NETMAP_LOCKED_EXIT)))
return;
- }
#endif /* DEV_NETMAP */
/* No work, make sure watchdog is off */
@@ -3926,7 +3964,7 @@
while (j != limit) {
rxbuf = &rxr->rx_buffers[i];
if (rxbuf->m_head == NULL) {
- m = m_getjcl(M_DONTWAIT, MT_DATA,
+ m = m_getjcl(M_NOWAIT, MT_DATA,
M_PKTHDR, adapter->rx_mbuf_sz);
/*
** If we have a temporary resource shortage
@@ -4096,7 +4134,7 @@
continue;
}
#endif /* DEV_NETMAP */
- rxbuf->m_head = m_getjcl(M_DONTWAIT, MT_DATA,
+ rxbuf->m_head = m_getjcl(M_NOWAIT, MT_DATA,
M_PKTHDR, adapter->rx_mbuf_sz);
if (rxbuf->m_head == NULL) {
error = ENOBUFS;
@@ -4241,8 +4279,6 @@
* Enable receive unit.
*
**********************************************************************/
-#define MAX_INTS_PER_SEC 8000
-#define DEFAULT_ITR 1000000000/(MAX_INTS_PER_SEC * 256)
static void
em_initialize_receive_unit(struct adapter *adapter)
@@ -4284,11 +4320,12 @@
E1000_WRITE_REG(hw, E1000_RFCTL, E1000_RFCTL_ACK_DIS);
}
- if (ifp->if_capenable & IFCAP_RXCSUM) {
- rxcsum = E1000_READ_REG(hw, E1000_RXCSUM);
- rxcsum |= (E1000_RXCSUM_IPOFL | E1000_RXCSUM_TUOFL);
- E1000_WRITE_REG(hw, E1000_RXCSUM, rxcsum);
- }
+ rxcsum = E1000_READ_REG(hw, E1000_RXCSUM);
+ if (ifp->if_capenable & IFCAP_RXCSUM)
+ rxcsum |= E1000_RXCSUM_TUOFL;
+ else
+ rxcsum &= ~E1000_RXCSUM_TUOFL;
+ E1000_WRITE_REG(hw, E1000_RXCSUM, rxcsum);
/*
** XXX TEMPORARY WORKAROUND: on some systems with 82573
@@ -4302,6 +4339,8 @@
for (int i = 0; i < adapter->num_queues; i++, rxr++) {
/* Setup the Base and Length of the Rx Descriptor Ring */
+ u32 rdt = adapter->num_rx_desc - 1; /* default */
+
bus_addr = rxr->rxdma.dma_paddr;
E1000_WRITE_REG(hw, E1000_RDLEN(i),
adapter->num_rx_desc * sizeof(struct e1000_rx_desc));
@@ -4313,18 +4352,11 @@
/*
* an init() while a netmap client is active must
* preserve the rx buffers passed to userspace.
- * In this driver it means we adjust RDT to
- * something different from na->num_rx_desc - 1.
*/
- if (ifp->if_capenable & IFCAP_NETMAP) {
- struct netmap_adapter *na = NA(adapter->ifp);
- struct netmap_kring *kring = &na->rx_rings[i];
- int t = na->num_rx_desc - 1 - kring->nr_hwavail;
-
- E1000_WRITE_REG(hw, E1000_RDT(i), t);
- } else
+ if (ifp->if_capenable & IFCAP_NETMAP)
+ rdt -= NA(adapter->ifp)->rx_rings[i].nr_hwavail;
#endif /* DEV_NETMAP */
- E1000_WRITE_REG(hw, E1000_RDT(i), adapter->num_rx_desc - 1);
+ E1000_WRITE_REG(hw, E1000_RDT(i), rdt);
}
/* Set PTHRESH for improved jumbo performance */
@@ -4336,7 +4368,7 @@
E1000_WRITE_REG(hw, E1000_RXDCTL(0), rxdctl | 3);
}
- if (adapter->hw.mac.type == e1000_pch2lan) {
+ if (adapter->hw.mac.type >= e1000_pch2lan) {
if (ifp->if_mtu > ETHERMTU)
e1000_lv_jumbo_workaround_ich8lan(hw, TRUE);
else
@@ -4401,17 +4433,8 @@
EM_RX_LOCK(rxr);
#ifdef DEV_NETMAP
- if (ifp->if_capenable & IFCAP_NETMAP) {
- struct netmap_adapter *na = NA(ifp);
-
- na->rx_rings[rxr->me].nr_kflags |= NKR_PENDINTR;
- selwakeuppri(&na->rx_rings[rxr->me].si, PI_NET);
- EM_RX_UNLOCK(rxr);
- EM_CORE_LOCK(adapter);
- selwakeuppri(&na->rx_si, PI_NET);
- EM_CORE_UNLOCK(adapter);
- return (0);
- }
+ if (netmap_rx_irq(ifp, rxr->me | NETMAP_LOCKED_ENTER, &processed))
+ return (FALSE);
#endif /* DEV_NETMAP */
for (i = rxr->next_to_check, processed = 0; count != 0;) {
@@ -4434,7 +4457,7 @@
if ((cur->errors & E1000_RXD_ERR_FRAME_ERR_MASK) ||
(rxr->discard == TRUE)) {
- ifp->if_ierrors++;
+ adapter->dropped_pkts++;
++rxr->rx_discarded;
if (!eop) /* Catch subsequent segs */
rxr->discard = TRUE;
@@ -4470,7 +4493,7 @@
ifp->if_ipackets++;
em_receive_checksum(cur, sendmp);
#ifndef __NO_STRICT_ALIGNMENT
- if (adapter->max_frame_size >
+ if (adapter->hw.mac.max_frame_size >
(MCLBYTES - ETHER_ALIGN) &&
em_fixup_rx(rxr) != 0)
goto skip;
@@ -4575,7 +4598,7 @@
bcopy(m->m_data, m->m_data + ETHER_HDR_LEN, m->m_len);
m->m_data += ETHER_HDR_LEN;
} else {
- MGETHDR(n, M_DONTWAIT, MT_DATA);
+ MGETHDR(n, M_NOWAIT, MT_DATA);
if (n != NULL) {
bcopy(m->m_data, n->m_data, ETHER_HDR_LEN);
m->m_data += ETHER_HDR_LEN;
@@ -4606,31 +4629,23 @@
static void
em_receive_checksum(struct e1000_rx_desc *rx_desc, struct mbuf *mp)
{
+ mp->m_pkthdr.csum_flags = 0;
+
/* Ignore Checksum bit is set */
- if (rx_desc->status & E1000_RXD_STAT_IXSM) {
- mp->m_pkthdr.csum_flags = 0;
+ if (rx_desc->status & E1000_RXD_STAT_IXSM)
return;
- }
- if (rx_desc->status & E1000_RXD_STAT_IPCS) {
- /* Did it pass? */
- if (!(rx_desc->errors & E1000_RXD_ERR_IPE)) {
- /* IP Checksum Good */
- mp->m_pkthdr.csum_flags = CSUM_IP_CHECKED;
- mp->m_pkthdr.csum_flags |= CSUM_IP_VALID;
+ if (rx_desc->errors & (E1000_RXD_ERR_TCPE | E1000_RXD_ERR_IPE))
+ return;
- } else {
- mp->m_pkthdr.csum_flags = 0;
- }
- }
+ /* IP Checksum Good? */
+ if (rx_desc->status & E1000_RXD_STAT_IPCS)
+ mp->m_pkthdr.csum_flags = (CSUM_IP_CHECKED | CSUM_IP_VALID);
- if (rx_desc->status & E1000_RXD_STAT_TCPCS) {
- /* Did it pass? */
- if (!(rx_desc->errors & E1000_RXD_ERR_TCPE)) {
- mp->m_pkthdr.csum_flags |=
- (CSUM_DATA_VALID | CSUM_PSEUDO_HDR);
- mp->m_pkthdr.csum_data = htons(0xffff);
- }
+ /* TCP or UDP checksum */
+ if (rx_desc->status & (E1000_RXD_STAT_TCPCS | E1000_RXD_STAT_UDPCS)) {
+ mp->m_pkthdr.csum_flags |= (CSUM_DATA_VALID | CSUM_PSEUDO_HDR);
+ mp->m_pkthdr.csum_data = htons(0xffff);
}
}
@@ -5117,7 +5132,7 @@
return;
reg = base + PCIR_EXPRESS_LINK_CTL;
link_ctrl = pci_read_config(dev, reg, 2);
- link_ctrl &= 0xFFFC; /* turn off bit 1 and 2 */
+ link_ctrl &= ~PCIEM_LINK_CTL_ASPMC;
pci_write_config(dev, reg, link_ctrl, 2);
return;
}
@@ -5609,6 +5624,8 @@
return (EINVAL);
info->value = usecs;
ticks = EM_USECS_TO_TICKS(usecs);
+ if (info->offset == E1000_ITR) /* units are 256ns here */
+ ticks *= 4;
adapter = info->adapter;
Property changes on: trunk/sys/dev/e1000/if_em.c
___________________________________________________________________
Deleted: cvs2svn:cvs-rev
## -1 +0,0 ##
-1.4
\ No newline at end of property
Modified: trunk/sys/dev/e1000/if_em.h
===================================================================
--- trunk/sys/dev/e1000/if_em.h 2013-12-28 14:30:04 UTC (rev 6559)
+++ trunk/sys/dev/e1000/if_em.h 2013-12-28 14:30:47 UTC (rev 6560)
@@ -1,3 +1,4 @@
+/* $MidnightBSD$ */
/******************************************************************************
Copyright (c) 2001-2011, Intel Corporation
@@ -30,7 +31,7 @@
POSSIBILITY OF SUCH DAMAGE.
******************************************************************************/
-/*$MidnightBSD$*/
+/*$FreeBSD: release/9.2.0/sys/dev/e1000/if_em.h 250458 2013-05-10 16:16:33Z luigi $*/
#ifndef _EM_H_DEFINED_
@@ -429,6 +430,7 @@
struct em_int_delay_info tx_abs_int_delay;
struct em_int_delay_info rx_int_delay;
struct em_int_delay_info rx_abs_int_delay;
+ struct em_int_delay_info tx_itr;
/* Misc stats maintained by the driver */
unsigned long dropped_pkts;
Property changes on: trunk/sys/dev/e1000/if_em.h
___________________________________________________________________
Deleted: cvs2svn:cvs-rev
## -1 +0,0 ##
-1.4
\ No newline at end of property
Modified: trunk/sys/dev/e1000/if_igb.c
===================================================================
--- trunk/sys/dev/e1000/if_igb.c 2013-12-28 14:30:04 UTC (rev 6559)
+++ trunk/sys/dev/e1000/if_igb.c 2013-12-28 14:30:47 UTC (rev 6560)
@@ -1,6 +1,7 @@
+/* $MidnightBSD$ */
/******************************************************************************
- Copyright (c) 2001-2012, Intel Corporation
+ Copyright (c) 2001-2013, Intel Corporation
All rights reserved.
Redistribution and use in source and binary forms, with or without
@@ -30,19 +31,20 @@
POSSIBILITY OF SUCH DAMAGE.
******************************************************************************/
-/*$MidnightBSD$*/
+/*$FreeBSD: release/9.2.0/sys/dev/e1000/if_igb.c 254573 2013-08-20 17:50:30Z jfv $*/
+#include "opt_inet.h"
+#include "opt_inet6.h"
+
#ifdef HAVE_KERNEL_OPTION_HEADERS
#include "opt_device_polling.h"
-#include "opt_inet.h"
-#include "opt_inet6.h"
#include "opt_altq.h"
#endif
#include <sys/param.h>
#include <sys/systm.h>
-#if __FreeBSD_version >= 800000
+#ifndef IGB_LEGACY_TX
#include <sys/buf_ring.h>
#endif
#include <sys/bus.h>
@@ -100,7 +102,7 @@
/*********************************************************************
* Driver version:
*********************************************************************/
-char igb_driver_version[] = "version - 2.3.4";
+char igb_driver_version[] = "version - 2.3.10";
/*********************************************************************
@@ -179,10 +181,9 @@
static int igb_shutdown(device_t);
static int igb_suspend(device_t);
static int igb_resume(device_t);
-#if __FreeBSD_version >= 800000
+#ifndef IGB_LEGACY_TX
static int igb_mq_start(struct ifnet *, struct mbuf *);
-static int igb_mq_start_locked(struct ifnet *,
- struct tx_ring *, struct mbuf *);
+static int igb_mq_start_locked(struct ifnet *, struct tx_ring *);
static void igb_qflush(struct ifnet *);
static void igb_deferred_mq_start(void *, int);
#else
@@ -295,7 +296,7 @@
DEVMETHOD(device_shutdown, igb_shutdown),
DEVMETHOD(device_suspend, igb_suspend),
DEVMETHOD(device_resume, igb_resume),
- {0, 0}
+ DEVMETHOD_END
};
static driver_t igb_driver = {
@@ -351,7 +352,17 @@
SYSCTL_INT(_hw_igb, OID_AUTO, max_interrupt_rate, CTLFLAG_RDTUN,
&igb_max_interrupt_rate, 0, "Maximum interrupts per second");
+#if __FreeBSD_version >= 800000
/*
+** Tuneable number of buffers in the buf-ring (drbr_xxx)
+*/
+static int igb_buf_ring_size = IGB_BR_SIZE;
+TUNABLE_INT("hw.igb.buf_ring_size", &igb_buf_ring_size);
+SYSCTL_INT(_hw_igb, OID_AUTO, buf_ring_size, CTLFLAG_RDTUN,
+ &igb_buf_ring_size, 0, "Size of the bufring");
+#endif
+
+/*
** Header split causes the packet header to
** be dma'd to a seperate mbuf from the payload.
** this can have memory alignment benefits. But
@@ -365,8 +376,9 @@
"Enable receive mbuf header split");
/*
-** This will autoconfigure based on
-** the number of CPUs if left at 0.
+** This will autoconfigure based on the
+** number of CPUs and max supported
+** MSIX messages if left at 0.
*/
static int igb_num_queues = 0;
TUNABLE_INT("hw.igb.num_queues", &igb_num_queues);
@@ -841,11 +853,11 @@
(ifp->if_drv_flags & IFF_DRV_RUNNING) && adapter->link_active) {
for (int i = 0; i < adapter->num_queues; i++, txr++) {
IGB_TX_LOCK(txr);
-#if __FreeBSD_version >= 800000
+#ifndef IGB_LEGACY_TX
/* Process the stack queue only if not depleted */
if (((txr->queue_status & IGB_QUEUE_DEPLETED) == 0) &&
!drbr_empty(ifp, txr->br))
- igb_mq_start_locked(ifp, txr, NULL);
+ igb_mq_start_locked(ifp, txr);
#else
if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd))
igb_start_locked(txr, ifp);
@@ -859,7 +871,7 @@
}
-#if __FreeBSD_version < 800000
+#ifdef IGB_LEGACY_TX
/*********************************************************************
* Transmit entry point
@@ -937,10 +949,11 @@
return;
}
-#else /* __FreeBSD_version >= 800000 */
+#else /* ~IGB_LEGACY_TX */
/*
-** Multiqueue Transmit driver
+** Multiqueue Transmit Entry:
+** quick turnaround to the stack
**
*/
static int
@@ -956,23 +969,23 @@
i = m->m_pkthdr.flowid % adapter->num_queues;
else
i = curcpu % adapter->num_queues;
-
txr = &adapter->tx_rings[i];
que = &adapter->queues[i];
- if (((txr->queue_status & IGB_QUEUE_DEPLETED) == 0) &&
- IGB_TX_TRYLOCK(txr)) {
- err = igb_mq_start_locked(ifp, txr, m);
+
+ err = drbr_enqueue(ifp, txr->br, m);
+ if (err)
+ return (err);
+ if (IGB_TX_TRYLOCK(txr)) {
+ err = igb_mq_start_locked(ifp, txr);
IGB_TX_UNLOCK(txr);
- } else {
- err = drbr_enqueue(ifp, txr->br, m);
+ } else
taskqueue_enqueue(que->tq, &txr->txq_task);
- }
return (err);
}
static int
-igb_mq_start_locked(struct ifnet *ifp, struct tx_ring *txr, struct mbuf *m)
+igb_mq_start_locked(struct ifnet *ifp, struct tx_ring *txr)
{
struct adapter *adapter = txr->adapter;
struct mbuf *next;
@@ -981,36 +994,35 @@
IGB_TX_LOCK_ASSERT(txr);
if (((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) ||
- (txr->queue_status == IGB_QUEUE_DEPLETED) ||
- adapter->link_active == 0) {
- if (m != NULL)
- err = drbr_enqueue(ifp, txr->br, m);
- return (err);
- }
+ adapter->link_active == 0)
+ return (ENETDOWN);
enq = 0;
- if (m == NULL) {
- next = drbr_dequeue(ifp, txr->br);
- } else if (drbr_needs_enqueue(ifp, txr->br)) {
- if ((err = drbr_enqueue(ifp, txr->br, m)) != 0)
- return (err);
- next = drbr_dequeue(ifp, txr->br);
- } else
- next = m;
/* Process the queue */
- while (next != NULL) {
+ while ((next = drbr_peek(ifp, txr->br)) != NULL) {
if ((err = igb_xmit(txr, &next)) != 0) {
- if (next != NULL)
- err = drbr_enqueue(ifp, txr->br, next);
+ if (next == NULL) {
+ /* It was freed, move forward */
+ drbr_advance(ifp, txr->br);
+ } else {
+ /*
+ * Still have one left, it may not be
+ * the same since the transmit function
+ * may have changed it.
+ */
+ drbr_putback(ifp, txr->br, next);
+ }
break;
}
+ drbr_advance(ifp, txr->br);
enq++;
- drbr_stats_update(ifp, next->m_pkthdr.len, next->m_flags);
+ ifp->if_obytes += next->m_pkthdr.len;
+ if (next->m_flags & M_MCAST)
+ ifp->if_omcasts++;
ETHER_BPF_MTAP(ifp, next);
if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0)
break;
- next = drbr_dequeue(ifp, txr->br);
}
if (enq > 0) {
/* Set the watchdog */
@@ -1036,7 +1048,7 @@
IGB_TX_LOCK(txr);
if (!drbr_empty(ifp, txr->br))
- igb_mq_start_locked(ifp, txr, NULL);
+ igb_mq_start_locked(ifp, txr);
IGB_TX_UNLOCK(txr);
}
@@ -1058,7 +1070,7 @@
}
if_qflush(ifp);
}
-#endif /* __FreeBSD_version >= 800000 */
+#endif /* ~IGB_LEGACY_TX */
/*********************************************************************
* Ioctl entry point
@@ -1384,11 +1396,11 @@
IGB_TX_LOCK(txr);
igb_txeof(txr);
-#if __FreeBSD_version >= 800000
+#ifndef IGB_LEGACY_TX
/* Process the stack queue only if not depleted */
if (((txr->queue_status & IGB_QUEUE_DEPLETED) == 0) &&
!drbr_empty(ifp, txr->br))
- igb_mq_start_locked(ifp, txr, NULL);
+ igb_mq_start_locked(ifp, txr);
#else
if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd))
igb_start_locked(txr, ifp);
@@ -1435,11 +1447,11 @@
if ((ifp->if_drv_flags & IFF_DRV_RUNNING) && adapter->link_active) {
for (int i = 0; i < adapter->num_queues; i++, txr++) {
IGB_TX_LOCK(txr);
-#if __FreeBSD_version >= 800000
+#ifndef IGB_LEGACY_TX
/* Process the stack queue only if not depleted */
if (((txr->queue_status & IGB_QUEUE_DEPLETED) == 0) &&
!drbr_empty(ifp, txr->br))
- igb_mq_start_locked(ifp, txr, NULL);
+ igb_mq_start_locked(ifp, txr);
#else
if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd))
igb_start_locked(txr, ifp);
@@ -1494,12 +1506,6 @@
}
#ifdef DEVICE_POLLING
-/*********************************************************************
- *
- * Legacy polling routine : if using this code you MUST be sure that
- * multiqueue is not defined, ie, set igb_num_queues to 1.
- *
- *********************************************************************/
#if __FreeBSD_version >= 800000
#define POLL_RETURN_COUNT(a) (a)
static int
@@ -1510,8 +1516,8 @@
igb_poll(struct ifnet *ifp, enum poll_cmd cmd, int count)
{
struct adapter *adapter = ifp->if_softc;
- struct igb_queue *que = adapter->queues;
- struct tx_ring *txr = adapter->tx_rings;
+ struct igb_queue *que;
+ struct tx_ring *txr;
u32 reg_icr, rx_done = 0;
u32 loop = IGB_MAX_LOOP;
bool more;
@@ -1533,20 +1539,26 @@
}
IGB_CORE_UNLOCK(adapter);
- igb_rxeof(que, count, &rx_done);
+ for (int i = 0; i < adapter->num_queues; i++) {
+ que = &adapter->queues[i];
+ txr = que->txr;
- IGB_TX_LOCK(txr);
- do {
- more = igb_txeof(txr);
- } while (loop-- && more);
-#if __FreeBSD_version >= 800000
- if (!drbr_empty(ifp, txr->br))
- igb_mq_start_locked(ifp, txr, NULL);
+ igb_rxeof(que, count, &rx_done);
+
+ IGB_TX_LOCK(txr);
+ do {
+ more = igb_txeof(txr);
+ } while (loop-- && more);
+#ifndef IGB_LEGACY_TX
+ if (!drbr_empty(ifp, txr->br))
+ igb_mq_start_locked(ifp, txr);
#else
- if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd))
- igb_start_locked(txr, ifp);
+ if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd))
+ igb_start_locked(txr, ifp);
#endif
- IGB_TX_UNLOCK(txr);
+ IGB_TX_UNLOCK(txr);
+ }
+
return POLL_RETURN_COUNT(rx_done);
}
#endif /* DEVICE_POLLING */
@@ -1567,16 +1579,20 @@
u32 newitr = 0;
bool more_rx;
+ /* Ignore spurious interrupts */
+ if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0)
+ return;
+
E1000_WRITE_REG(&adapter->hw, E1000_EIMC, que->eims);
++que->irqs;
IGB_TX_LOCK(txr);
igb_txeof(txr);
-#if __FreeBSD_version >= 800000
+#ifndef IGB_LEGACY_TX
/* Process the stack queue only if not depleted */
if (((txr->queue_status & IGB_QUEUE_DEPLETED) == 0) &&
!drbr_empty(ifp, txr->br))
- igb_mq_start_locked(ifp, txr, NULL);
+ igb_mq_start_locked(ifp, txr);
#else
if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd))
igb_start_locked(txr, ifp);
@@ -1685,7 +1701,6 @@
igb_media_status(struct ifnet *ifp, struct ifmediareq *ifmr)
{
struct adapter *adapter = ifp->if_softc;
- u_char fiber_type = IFM_1000_SX;
INIT_DEBUGOUT("igb_media_status: begin");
@@ -1702,26 +1717,31 @@
ifmr->ifm_status |= IFM_ACTIVE;
- if ((adapter->hw.phy.media_type == e1000_media_type_fiber) ||
- (adapter->hw.phy.media_type == e1000_media_type_internal_serdes))
- ifmr->ifm_active |= fiber_type | IFM_FDX;
- else {
- switch (adapter->link_speed) {
- case 10:
- ifmr->ifm_active |= IFM_10_T;
- break;
- case 100:
+ switch (adapter->link_speed) {
+ case 10:
+ ifmr->ifm_active |= IFM_10_T;
+ break;
+ case 100:
+ /*
+ ** Support for 100Mb SFP - these are Fiber
+ ** but the media type appears as serdes
+ */
+ if (adapter->hw.phy.media_type ==
+ e1000_media_type_internal_serdes)
+ ifmr->ifm_active |= IFM_100_FX;
+ else
ifmr->ifm_active |= IFM_100_TX;
- break;
- case 1000:
- ifmr->ifm_active |= IFM_1000_T;
- break;
- }
- if (adapter->link_duplex == FULL_DUPLEX)
- ifmr->ifm_active |= IFM_FDX;
- else
- ifmr->ifm_active |= IFM_HDX;
+ break;
+ case 1000:
+ ifmr->ifm_active |= IFM_1000_T;
+ break;
}
+
+ if (adapter->link_duplex == FULL_DUPLEX)
+ ifmr->ifm_active |= IFM_FDX;
+ else
+ ifmr->ifm_active |= IFM_HDX;
+
IGB_CORE_UNLOCK(adapter);
}
@@ -1834,7 +1854,7 @@
if (do_tso || (m_head->m_next != NULL &&
m_head->m_pkthdr.csum_flags & CSUM_OFFLOAD)) {
if (M_WRITABLE(*m_headp) == 0) {
- m_head = m_dup(*m_headp, M_DONTWAIT);
+ m_head = m_dup(*m_headp, M_NOWAIT);
m_freem(*m_headp);
if (m_head == NULL) {
*m_headp = NULL;
@@ -1939,7 +1959,7 @@
if (error == EFBIG && remap) {
struct mbuf *m;
- m = m_defrag(*m_headp, M_DONTWAIT);
+ m = m_defrag(*m_headp, M_NOWAIT);
if (m == NULL) {
adapter->mbuf_defrag_failed++;
m_freem(*m_headp);
@@ -2088,7 +2108,9 @@
igb_disable_promisc(struct adapter *adapter)
{
struct e1000_hw *hw = &adapter->hw;
+ struct ifnet *ifp = adapter->ifp;
u32 reg;
+ int mcnt = 0;
if (adapter->vf_ifp) {
e1000_promisc_set_vf(hw, e1000_promisc_disabled);
@@ -2096,7 +2118,31 @@
}
reg = E1000_READ_REG(hw, E1000_RCTL);
reg &= (~E1000_RCTL_UPE);
- reg &= (~E1000_RCTL_MPE);
+ if (ifp->if_flags & IFF_ALLMULTI)
+ mcnt = MAX_NUM_MULTICAST_ADDRESSES;
+ else {
+ struct ifmultiaddr *ifma;
+#if __FreeBSD_version < 800000
+ IF_ADDR_LOCK(ifp);
+#else
+ if_maddr_rlock(ifp);
+#endif
+ TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
+ if (ifma->ifma_addr->sa_family != AF_LINK)
+ continue;
+ if (mcnt == MAX_NUM_MULTICAST_ADDRESSES)
+ break;
+ mcnt++;
+ }
+#if __FreeBSD_version < 800000
+ IF_ADDR_UNLOCK(ifp);
+#else
+ if_maddr_runlock(ifp);
+#endif
+ }
+ /* Don't disable if in MAX groups */
+ if (mcnt < MAX_NUM_MULTICAST_ADDRESSES)
+ reg &= (~E1000_RCTL_MPE);
E1000_WRITE_REG(hw, E1000_RCTL, reg);
}
@@ -2224,11 +2270,13 @@
static void
igb_update_link_status(struct adapter *adapter)
{
- struct e1000_hw *hw = &adapter->hw;
- struct ifnet *ifp = adapter->ifp;
- device_t dev = adapter->dev;
- struct tx_ring *txr = adapter->tx_rings;
- u32 link_check, thstat, ctrl;
+ struct e1000_hw *hw = &adapter->hw;
+ struct e1000_fc_info *fc = &hw->fc;
+ struct ifnet *ifp = adapter->ifp;
+ device_t dev = adapter->dev;
+ struct tx_ring *txr = adapter->tx_rings;
+ u32 link_check, thstat, ctrl;
+ char *flowctl = NULL;
link_check = thstat = ctrl = 0;
@@ -2266,15 +2314,33 @@
ctrl = E1000_READ_REG(hw, E1000_CTRL_EXT);
}
+ /* Get the flow control for display */
+ switch (fc->current_mode) {
+ case e1000_fc_rx_pause:
+ flowctl = "RX";
+ break;
+ case e1000_fc_tx_pause:
+ flowctl = "TX";
+ break;
+ case e1000_fc_full:
+ flowctl = "Full";
+ break;
+ case e1000_fc_none:
+ default:
+ flowctl = "None";
+ break;
+ }
+
/* Now we check if a transition has happened */
if (link_check && (adapter->link_active == 0)) {
e1000_get_speed_and_duplex(&adapter->hw,
&adapter->link_speed, &adapter->link_duplex);
if (bootverbose)
- device_printf(dev, "Link is up %d Mbps %s\n",
+ device_printf(dev, "Link is up %d Mbps %s,"
+ " Flow Control: %s\n",
adapter->link_speed,
((adapter->link_duplex == FULL_DUPLEX) ?
- "Full Duplex" : "Half Duplex"));
+ "Full Duplex" : "Half Duplex"), flowctl);
adapter->link_active = 1;
ifp->if_baudrate = adapter->link_speed * 1000000;
if ((ctrl & E1000_CTRL_EXT_LINK_MODE_GMII) &&
@@ -2351,16 +2417,8 @@
device_t dev = adapter->dev;
/* Make sure our PCI config space has the necessary stuff set */
+ pci_enable_busmaster(dev);
adapter->hw.bus.pci_cmd_word = pci_read_config(dev, PCIR_COMMAND, 2);
- if (!((adapter->hw.bus.pci_cmd_word & PCIM_CMD_BUSMASTEREN) &&
- (adapter->hw.bus.pci_cmd_word & PCIM_CMD_MEMEN))) {
- INIT_DEBUGOUT("Memory Access and/or Bus Master "
- "bits were not set!\n");
- adapter->hw.bus.pci_cmd_word |=
- (PCIM_CMD_BUSMASTEREN | PCIM_CMD_MEMEN);
- pci_write_config(dev, PCIR_COMMAND,
- adapter->hw.bus.pci_cmd_word, 2);
- }
/* Save off the information about this board */
adapter->hw.vendor_id = pci_get_vendor(dev);
@@ -2420,7 +2478,6 @@
{
device_t dev = adapter->dev;
struct igb_queue *que = adapter->queues;
- struct tx_ring *txr = adapter->tx_rings;
int error, rid = 0;
/* Turn off all interrupts */
@@ -2439,8 +2496,8 @@
return (ENXIO);
}
-#if __FreeBSD_version >= 800000
- TASK_INIT(&txr->txq_task, 0, igb_deferred_mq_start, txr);
+#ifndef IGB_LEGACY_TX
+ TASK_INIT(&que->txr->txq_task, 0, igb_deferred_mq_start, que->txr);
#endif
/*
@@ -2522,9 +2579,8 @@
"Bound queue %d to cpu %d\n",
i,igb_last_bind_cpu);
igb_last_bind_cpu = CPU_NEXT(igb_last_bind_cpu);
- igb_last_bind_cpu = igb_last_bind_cpu % mp_ncpus;
}
-#if __FreeBSD_version >= 800000
+#ifndef IGB_LEGACY_TX
TASK_INIT(&que->txr->txq_task, 0, igb_deferred_mq_start,
que->txr);
#endif
@@ -2750,7 +2806,7 @@
for (int i = 0; i < adapter->num_queues; i++, que++) {
if (que->tq != NULL) {
-#if __FreeBSD_version >= 800000
+#ifndef IGB_LEGACY_TX
taskqueue_drain(que->tq, &que->txr->txq_task);
#endif
taskqueue_drain(que->tq, &que->que_task);
@@ -2785,10 +2841,13 @@
goto msi;
/* First try MSI/X */
+ msgs = pci_msix_count(dev);
+ if (msgs == 0)
+ goto msi;
rid = PCIR_BAR(IGB_MSIX_BAR);
adapter->msix_mem = bus_alloc_resource_any(dev,
SYS_RES_MEMORY, &rid, RF_ACTIVE);
- if (!adapter->msix_mem) {
+ if (adapter->msix_mem == NULL) {
/* May not be enabled */
device_printf(adapter->dev,
"Unable to map MSIX table \n");
@@ -2795,14 +2854,6 @@
goto msi;
}
- msgs = pci_msix_count(dev);
- if (msgs == 0) { /* system has msix disabled */
- bus_release_resource(dev, SYS_RES_MEMORY,
- PCIR_BAR(IGB_MSIX_BAR), adapter->msix_mem);
- adapter->msix_mem = NULL;
- goto msi;
- }
-
/* Figure out a reasonable auto config value */
queues = (mp_ncpus > (msgs-1)) ? (msgs-1) : mp_ncpus;
@@ -2845,20 +2896,32 @@
"MSIX Configuration Problem, "
"%d vectors configured, but %d queues wanted!\n",
msgs, want);
- return (0);
+ goto msi;
}
- if ((msgs) && pci_alloc_msix(dev, &msgs) == 0) {
+ if ((pci_alloc_msix(dev, &msgs) == 0) && (msgs == want)) {
device_printf(adapter->dev,
"Using MSIX interrupts with %d vectors\n", msgs);
adapter->num_queues = queues;
return (msgs);
}
+ /*
+ ** If MSIX alloc failed or provided us with
+ ** less than needed, free and fall through to MSI
+ */
+ pci_release_msi(dev);
+
msi:
- msgs = pci_msi_count(dev);
- if (msgs == 1 && pci_alloc_msi(dev, &msgs) == 0) {
- device_printf(adapter->dev," Using MSI interrupt\n");
+ if (adapter->msix_mem != NULL) {
+ bus_release_resource(dev, SYS_RES_MEMORY,
+ PCIR_BAR(IGB_MSIX_BAR), adapter->msix_mem);
+ adapter->msix_mem = NULL;
+ }
+ msgs = 1;
+ if (pci_alloc_msi(dev, &msgs) == 0) {
+ device_printf(adapter->dev," Using an MSI interrupt\n");
return (msgs);
}
+ device_printf(adapter->dev," Using a Legacy interrupt\n");
return (0);
}
@@ -3060,7 +3123,7 @@
ifp->if_softc = adapter;
ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
ifp->if_ioctl = igb_ioctl;
-#if __FreeBSD_version >= 800000
+#ifndef IGB_LEGACY_TX
ifp->if_transmit = igb_mq_start;
ifp->if_qflush = igb_qflush;
#else
@@ -3304,9 +3367,9 @@
error = ENOMEM;
goto err_tx_desc;
}
-#if __FreeBSD_version >= 800000
+#ifndef IGB_LEGACY_TX
/* Allocate a buf ring */
- txr->br = buf_ring_alloc(IGB_BR_SIZE, M_DEVBUF,
+ txr->br = buf_ring_alloc(igb_buf_ring_size, M_DEVBUF,
M_WAITOK, &txr->tx_mtx);
#endif
}
@@ -3365,7 +3428,7 @@
igb_dma_free(adapter, &txr->txdma);
free(adapter->rx_rings, M_DEVBUF);
rx_fail:
-#if __FreeBSD_version >= 800000
+#ifndef IGB_LEGACY_TX
buf_ring_free(txr->br, M_DEVBUF);
#endif
free(adapter->tx_rings, M_DEVBUF);
@@ -3623,7 +3686,7 @@
tx_buffer->map = NULL;
}
}
-#if __FreeBSD_version >= 800000
+#ifndef IGB_LEGACY_TX
if (txr->br != NULL)
buf_ring_free(txr->br, M_DEVBUF);
#endif
@@ -3845,17 +3908,9 @@
IGB_TX_LOCK_ASSERT(txr);
#ifdef DEV_NETMAP
- if (ifp->if_capenable & IFCAP_NETMAP) {
- struct netmap_adapter *na = NA(ifp);
-
- selwakeuppri(&na->tx_rings[txr->me].si, PI_NET);
- IGB_TX_UNLOCK(txr);
- IGB_CORE_LOCK(adapter);
- selwakeuppri(&na->tx_si, PI_NET);
- IGB_CORE_UNLOCK(adapter);
- IGB_TX_LOCK(txr);
- return FALSE;
- }
+ if (netmap_tx_irq(ifp, txr->me |
+ (NETMAP_LOCKED_ENTER|NETMAP_LOCKED_EXIT)))
+ return (FALSE);
#endif /* DEV_NETMAP */
if (txr->tx_avail == adapter->num_tx_desc) {
txr->queue_status = IGB_QUEUE_IDLE;
@@ -3988,7 +4043,7 @@
if (rxr->hdr_split == FALSE)
goto no_split;
if (rxbuf->m_head == NULL) {
- mh = m_gethdr(M_DONTWAIT, MT_DATA);
+ mh = m_gethdr(M_NOWAIT, MT_DATA);
if (mh == NULL)
goto update;
} else
@@ -4014,7 +4069,7 @@
htole64(hseg[0].ds_addr);
no_split:
if (rxbuf->m_pack == NULL) {
- mp = m_getjcl(M_DONTWAIT, MT_DATA,
+ mp = m_getjcl(M_NOWAIT, MT_DATA,
M_PKTHDR, adapter->rx_mbuf_sz);
if (mp == NULL)
goto update;
@@ -4230,7 +4285,7 @@
goto skip_head;
/* First the header */
- rxbuf->m_head = m_gethdr(M_DONTWAIT, MT_DATA);
+ rxbuf->m_head = m_gethdr(M_NOWAIT, MT_DATA);
if (rxbuf->m_head == NULL) {
error = ENOBUFS;
goto fail;
@@ -4252,7 +4307,7 @@
skip_head:
/* Now the payload cluster */
- rxbuf->m_pack = m_getjcl(M_DONTWAIT, MT_DATA,
+ rxbuf->m_pack = m_getjcl(M_NOWAIT, MT_DATA,
M_PKTHDR, adapter->rx_mbuf_sz);
if (rxbuf->m_pack == NULL) {
error = ENOBUFS;
@@ -4335,8 +4390,8 @@
* the rings that completed, the failing case will have
* cleaned up for itself. 'i' is the endpoint.
*/
- for (int j = 0; j > i; ++j) {
- rxr = &adapter->rx_rings[i];
+ for (int j = 0; j < i; ++j) {
+ rxr = &adapter->rx_rings[j];
IGB_RX_LOCK(rxr);
igb_free_receive_ring(rxr);
IGB_RX_UNLOCK(rxr);
@@ -4709,17 +4764,8 @@
BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
#ifdef DEV_NETMAP
- if (ifp->if_capenable & IFCAP_NETMAP) {
- struct netmap_adapter *na = NA(ifp);
-
- na->rx_rings[rxr->me].nr_kflags |= NKR_PENDINTR;
- selwakeuppri(&na->rx_rings[rxr->me].si, PI_NET);
- IGB_RX_UNLOCK(rxr);
- IGB_CORE_LOCK(adapter);
- selwakeuppri(&na->rx_si, PI_NET);
- IGB_CORE_UNLOCK(adapter);
- return (0);
- }
+ if (netmap_rx_irq(ifp, rxr->me | NETMAP_LOCKED_ENTER, &processed))
+ return (FALSE);
#endif /* DEV_NETMAP */
/* Main clean loop */
@@ -4752,7 +4798,7 @@
/* Make sure all segments of a bad packet are discarded */
if (((staterr & E1000_RXDEXT_ERR_FRAME_ERR_MASK) != 0) ||
(rxr->discard)) {
- ifp->if_ierrors++;
+ adapter->dropped_pkts++;
++rxr->rx_discarded;
if (!eop) /* Catch subsequent segs */
rxr->discard = TRUE;
@@ -4844,7 +4890,7 @@
rxr->fmp->m_pkthdr.ether_vtag = vtag;
rxr->fmp->m_flags |= M_VLANTAG;
}
-#if __FreeBSD_version >= 800000
+#ifndef IGB_LEGACY_TX
rxr->fmp->m_pkthdr.flowid = que->msix;
rxr->fmp->m_flags |= M_FLOWID;
#endif
@@ -4894,7 +4940,7 @@
}
if (done != NULL)
- *done = rxdone;
+ *done += rxdone;
IGB_RX_UNLOCK(rxr);
return ((staterr & E1000_RXD_STAT_DD) ? TRUE : FALSE);
Property changes on: trunk/sys/dev/e1000/if_igb.c
___________________________________________________________________
Deleted: cvs2svn:cvs-rev
## -1 +0,0 ##
-1.4
\ No newline at end of property
Modified: trunk/sys/dev/e1000/if_igb.h
===================================================================
--- trunk/sys/dev/e1000/if_igb.h 2013-12-28 14:30:04 UTC (rev 6559)
+++ trunk/sys/dev/e1000/if_igb.h 2013-12-28 14:30:47 UTC (rev 6560)
@@ -1,3 +1,4 @@
+/* $MidnightBSD$ */
/******************************************************************************
Copyright (c) 2001-2011, Intel Corporation
@@ -30,7 +31,7 @@
POSSIBILITY OF SUCH DAMAGE.
******************************************************************************/
-/*$MidnightBSD$*/
+/*$FreeBSD: release/9.2.0/sys/dev/e1000/if_igb.h 252899 2013-07-06 22:34:42Z jfv $*/
#ifndef _IGB_H_DEFINED_
#define _IGB_H_DEFINED_
@@ -297,11 +298,11 @@
u32 next_to_clean;
volatile u16 tx_avail;
struct igb_tx_buffer *tx_buffers;
-#if __FreeBSD_version >= 800000
+#ifndef IGB_LEGACY_TX
struct buf_ring *br;
+ struct task txq_task;
#endif
bus_dma_tag_t txtag;
- struct task txq_task;
u32 bytes;
u32 packets;
Property changes on: trunk/sys/dev/e1000/if_igb.h
___________________________________________________________________
Deleted: cvs2svn:cvs-rev
## -1 +0,0 ##
-1.4
\ No newline at end of property
Modified: trunk/sys/dev/e1000/if_lem.c
===================================================================
--- trunk/sys/dev/e1000/if_lem.c 2013-12-28 14:30:04 UTC (rev 6559)
+++ trunk/sys/dev/e1000/if_lem.c 2013-12-28 14:30:47 UTC (rev 6560)
@@ -1,6 +1,7 @@
+/* $MidnightBSD$ */
/******************************************************************************
- Copyright (c) 2001-2011, Intel Corporation
+ Copyright (c) 2001-2012, Intel Corporation
All rights reserved.
Redistribution and use in source and binary forms, with or without
@@ -30,12 +31,13 @@
POSSIBILITY OF SUCH DAMAGE.
******************************************************************************/
-/*$MidnightBSD$*/
+/*$FreeBSD: release/9.2.0/sys/dev/e1000/if_lem.c 254364 2013-08-15 12:19:16Z scottl $*/
+#include "opt_inet.h"
+#include "opt_inet6.h"
+
#ifdef HAVE_KERNEL_OPTION_HEADERS
#include "opt_device_polling.h"
-#include "opt_inet.h"
-#include "opt_inet6.h"
#endif
#include <sys/param.h>
@@ -85,7 +87,7 @@
/*********************************************************************
* Legacy Em Driver version:
*********************************************************************/
-char lem_driver_version[] = "1.0.4";
+char lem_driver_version[] = "1.0.6";
/*********************************************************************
* PCI Device ID Table
@@ -239,15 +241,12 @@
static int lem_enable_phy_wakeup(struct adapter *);
static void lem_led_func(void *, int);
-#ifdef EM_LEGACY_IRQ
static void lem_intr(void *);
-#else /* FAST IRQ */
static int lem_irq_fast(void *);
static void lem_handle_rxtx(void *context, int pending);
static void lem_handle_link(void *context, int pending);
static void lem_add_rx_process_limit(struct adapter *, const char *,
const char *, int *, int);
-#endif /* ~EM_LEGACY_IRQ */
#ifdef DEVICE_POLLING
static poll_handler_t lem_poll;
@@ -265,7 +264,7 @@
DEVMETHOD(device_shutdown, lem_shutdown),
DEVMETHOD(device_suspend, lem_suspend),
DEVMETHOD(device_resume, lem_resume),
- {0, 0}
+ DEVMETHOD_END
};
static driver_t lem_driver = {
@@ -284,6 +283,9 @@
#define EM_TICKS_TO_USECS(ticks) ((1024 * (ticks) + 500) / 1000)
#define EM_USECS_TO_TICKS(usecs) ((1000 * (usecs) + 512) / 1024)
+#define MAX_INTS_PER_SEC 8000
+#define DEFAULT_ITR (1000000000/(MAX_INTS_PER_SEC * 256))
+
static int lem_tx_int_delay_dflt = EM_TICKS_TO_USECS(EM_TIDV);
static int lem_rx_int_delay_dflt = EM_TICKS_TO_USECS(EM_RDTR);
static int lem_tx_abs_int_delay_dflt = EM_TICKS_TO_USECS(EM_TADV);
@@ -304,11 +306,13 @@
TUNABLE_INT("hw.em.smart_pwr_down", &lem_smart_pwr_down);
TUNABLE_INT("hw.em.sbp", &lem_debug_sbp);
-#ifndef EM_LEGACY_IRQ
+/* Interrupt style - default to fast */
+static int lem_use_legacy_irq = 0;
+TUNABLE_INT("hw.em.use_legacy_irq", &lem_use_legacy_irq);
+
/* How many packets rxeof tries to clean at a time */
static int lem_rx_process_limit = 100;
TUNABLE_INT("hw.em.rx_process_limit", &lem_rx_process_limit);
-#endif
/* Flow control setting - default to FULL */
static int lem_fc_setting = e1000_fc_full;
@@ -391,11 +395,6 @@
INIT_DEBUGOUT("lem_attach: begin");
- if (resource_disabled("lem", device_get_unit(dev))) {
- device_printf(dev, "Disabled by device hint\n");
- return (ENXIO);
- }
-
adapter = device_get_softc(dev);
adapter->dev = adapter->osdep.dev = dev;
EM_CORE_LOCK_INIT(adapter, device_get_nameunit(dev));
@@ -448,14 +447,17 @@
&adapter->tx_abs_int_delay,
E1000_REGISTER(&adapter->hw, E1000_TADV),
lem_tx_abs_int_delay_dflt);
+ lem_add_int_delay_sysctl(adapter, "itr",
+ "interrupt delay limit in usecs/4",
+ &adapter->tx_itr,
+ E1000_REGISTER(&adapter->hw, E1000_ITR),
+ DEFAULT_ITR);
}
-#ifndef EM_LEGACY_IRQ
/* Sysctls for limiting the amount of work done in the taskqueue */
lem_add_rx_process_limit(adapter, "rx_processing_limit",
"max number of rx packets to process", &adapter->rx_process_limit,
lem_rx_process_limit);
-#endif
/* Sysctl for setting the interface flow control */
lem_set_flow_cntrl(adapter, "flow_control",
@@ -1197,22 +1199,6 @@
callout_reset(&adapter->timer, hz, lem_local_timer, adapter);
e1000_clear_hw_cntrs_base_generic(&adapter->hw);
- /* MSI/X configuration for 82574 */
- if (adapter->hw.mac.type == e1000_82574) {
- int tmp;
- tmp = E1000_READ_REG(&adapter->hw, E1000_CTRL_EXT);
- tmp |= E1000_CTRL_EXT_PBA_CLR;
- E1000_WRITE_REG(&adapter->hw, E1000_CTRL_EXT, tmp);
- /*
- ** Set the IVAR - interrupt vector routing.
- ** Each nibble represents a vector, high bit
- ** is enable, other 3 bits are the MSIX table
- ** entry, we map RXQ0 to 0, TXQ0 to 1, and
- ** Link (other) to 2, hence the magic number.
- */
- E1000_WRITE_REG(&adapter->hw, E1000_IVAR, 0x800A0908);
- }
-
#ifdef DEVICE_POLLING
/*
* Only enable interrupts if we are not polling, make sure
@@ -1281,7 +1267,6 @@
}
#endif /* DEVICE_POLLING */
-#ifdef EM_LEGACY_IRQ
/*********************************************************************
*
* Legacy Interrupt Service routine
@@ -1295,7 +1280,8 @@
u32 reg_icr;
- if (ifp->if_capenable & IFCAP_POLLING)
+ if ((ifp->if_capenable & IFCAP_POLLING) ||
+ ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0))
return;
EM_CORE_LOCK(adapter);
@@ -1303,12 +1289,11 @@
if (reg_icr & E1000_ICR_RXO)
adapter->rx_overruns++;
- if ((reg_icr == 0xffffffff) || (reg_icr == 0))
- goto out;
+ if ((reg_icr == 0xffffffff) || (reg_icr == 0)) {
+ EM_CORE_UNLOCK(adapter);
+ return;
+ }
- if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0)
- goto out;
-
if (reg_icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) {
callout_stop(&adapter->timer);
adapter->hw.mac.get_link_status = 1;
@@ -1317,23 +1302,22 @@
lem_tx_purge(adapter);
callout_reset(&adapter->timer, hz,
lem_local_timer, adapter);
- goto out;
+ EM_CORE_UNLOCK(adapter);
+ return;
}
+ EM_CORE_UNLOCK(adapter);
+ lem_rxeof(adapter, -1, NULL);
+
EM_TX_LOCK(adapter);
- lem_rxeof(adapter, -1, NULL);
lem_txeof(adapter);
if (ifp->if_drv_flags & IFF_DRV_RUNNING &&
!IFQ_DRV_IS_EMPTY(&ifp->if_snd))
lem_start_locked(ifp);
EM_TX_UNLOCK(adapter);
-
-out:
- EM_CORE_UNLOCK(adapter);
return;
}
-#else /* EM_FAST_IRQ, then fast interrupt routines only */
static void
lem_handle_link(void *context, int pending)
@@ -1363,12 +1347,16 @@
if (ifp->if_drv_flags & IFF_DRV_RUNNING) {
- lem_rxeof(adapter, adapter->rx_process_limit, NULL);
+ bool more = lem_rxeof(adapter, adapter->rx_process_limit, NULL);
EM_TX_LOCK(adapter);
lem_txeof(adapter);
if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd))
lem_start_locked(ifp);
EM_TX_UNLOCK(adapter);
+ if (more) {
+ taskqueue_enqueue(adapter->tq, &adapter->rxtx_task);
+ return;
+ }
}
if (ifp->if_drv_flags & IFF_DRV_RUNNING)
@@ -1417,7 +1405,6 @@
adapter->rx_overruns++;
return FILTER_HANDLED;
}
-#endif /* ~EM_LEGACY_IRQ */
/*********************************************************************
@@ -1593,7 +1580,7 @@
if (error == EFBIG) {
struct mbuf *m;
- m = m_defrag(*m_headp, M_DONTWAIT);
+ m = m_defrag(*m_headp, M_NOWAIT);
if (m == NULL) {
adapter->mbuf_alloc_failed++;
m_freem(*m_headp);
@@ -1883,12 +1870,37 @@
static void
lem_disable_promisc(struct adapter *adapter)
{
- u32 reg_rctl;
+ struct ifnet *ifp = adapter->ifp;
+ u32 reg_rctl;
+ int mcnt = 0;
reg_rctl = E1000_READ_REG(&adapter->hw, E1000_RCTL);
-
reg_rctl &= (~E1000_RCTL_UPE);
- reg_rctl &= (~E1000_RCTL_MPE);
+ if (ifp->if_flags & IFF_ALLMULTI)
+ mcnt = MAX_NUM_MULTICAST_ADDRESSES;
+ else {
+ struct ifmultiaddr *ifma;
+#if __FreeBSD_version < 800000
+ IF_ADDR_LOCK(ifp);
+#else
+ if_maddr_rlock(ifp);
+#endif
+ TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
+ if (ifma->ifma_addr->sa_family != AF_LINK)
+ continue;
+ if (mcnt == MAX_NUM_MULTICAST_ADDRESSES)
+ break;
+ mcnt++;
+ }
+#if __FreeBSD_version < 800000
+ IF_ADDR_UNLOCK(ifp);
+#else
+ if_maddr_runlock(ifp);
+#endif
+ }
+ /* Don't disable if in MAX groups */
+ if (mcnt < MAX_NUM_MULTICAST_ADDRESSES)
+ reg_rctl &= (~E1000_RCTL_MPE);
reg_rctl &= (~E1000_RCTL_SBP);
E1000_WRITE_REG(&adapter->hw, E1000_RCTL, reg_rctl);
}
@@ -2108,16 +2120,8 @@
device_t dev = adapter->dev;
/* Make sure our PCI config space has the necessary stuff set */
+ pci_enable_busmaster(dev);
adapter->hw.bus.pci_cmd_word = pci_read_config(dev, PCIR_COMMAND, 2);
- if (!((adapter->hw.bus.pci_cmd_word & PCIM_CMD_BUSMASTEREN) &&
- (adapter->hw.bus.pci_cmd_word & PCIM_CMD_MEMEN))) {
- device_printf(dev, "Memory Access and/or Bus Master bits "
- "were not set!\n");
- adapter->hw.bus.pci_cmd_word |=
- (PCIM_CMD_BUSMASTEREN | PCIM_CMD_MEMEN);
- pci_write_config(dev, PCIR_COMMAND,
- adapter->hw.bus.pci_cmd_word, 2);
- }
/* Save off the information about this board */
adapter->hw.vendor_id = pci_get_vendor(dev);
@@ -2214,19 +2218,21 @@
return (ENXIO);
}
-#ifdef EM_LEGACY_IRQ
- /* We do Legacy setup */
- if ((error = bus_setup_intr(dev, adapter->res[0],
- INTR_TYPE_NET | INTR_MPSAFE, NULL, lem_intr, adapter,
- &adapter->tag[0])) != 0) {
- device_printf(dev, "Failed to register interrupt handler");
- return (error);
+ /* Do Legacy setup? */
+ if (lem_use_legacy_irq) {
+ if ((error = bus_setup_intr(dev, adapter->res[0],
+ INTR_TYPE_NET | INTR_MPSAFE, NULL, lem_intr, adapter,
+ &adapter->tag[0])) != 0) {
+ device_printf(dev,
+ "Failed to register interrupt handler");
+ return (error);
+ }
+ return (0);
}
-#else /* FAST_IRQ */
/*
- * Try allocating a fast interrupt and the associated deferred
- * processing contexts.
+ * Use a Fast interrupt and the associated
+ * deferred processing contexts.
*/
TASK_INIT(&adapter->rxtx_task, 0, lem_handle_rxtx, adapter);
TASK_INIT(&adapter->link_task, 0, lem_handle_link, adapter);
@@ -2243,7 +2249,6 @@
adapter->tq = NULL;
return (error);
}
-#endif /* EM_LEGACY_IRQ */
return (0);
}
@@ -2981,10 +2986,8 @@
EM_TX_LOCK_ASSERT(adapter);
#ifdef DEV_NETMAP
- if (ifp->if_capenable & IFCAP_NETMAP) {
- selwakeuppri(&NA(ifp)->tx_rings[0].si, PI_NET);
+ if (netmap_tx_irq(ifp, 0 | (NETMAP_LOCKED_ENTER|NETMAP_LOCKED_EXIT)))
return;
- }
#endif /* DEV_NETMAP */
if (adapter->num_tx_desc_avail == adapter->num_tx_desc)
return;
@@ -3101,7 +3104,7 @@
struct em_buffer *rx_buffer;
int error, nsegs;
- m = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR);
+ m = m_getcl(M_NOWAIT, MT_DATA, M_PKTHDR);
if (m == NULL) {
adapter->mbuf_cluster_failed++;
return (ENOBUFS);
@@ -3272,8 +3275,6 @@
* Enable receive unit.
*
**********************************************************************/
-#define MAX_INTS_PER_SEC 8000
-#define DEFAULT_ITR 1000000000/(MAX_INTS_PER_SEC * 256)
static void
lem_initialize_receive_unit(struct adapter *adapter)
@@ -3301,20 +3302,6 @@
E1000_WRITE_REG(&adapter->hw, E1000_ITR, DEFAULT_ITR);
}
- /*
- ** When using MSIX interrupts we need to throttle
- ** using the EITR register (82574 only)
- */
- if (adapter->msix)
- for (int i = 0; i < 4; i++)
- E1000_WRITE_REG(&adapter->hw,
- E1000_EITR_82574(i), DEFAULT_ITR);
-
- /* Disable accelerated ackknowledge */
- if (adapter->hw.mac.type == e1000_82574)
- E1000_WRITE_REG(&adapter->hw,
- E1000_RFCTL, E1000_RFCTL_ACK_DIS);
-
/* Setup the Base and Length of the Rx Descriptor Ring */
bus_addr = adapter->rxdma.dma_paddr;
E1000_WRITE_REG(&adapter->hw, E1000_RDLEN(0),
@@ -3378,19 +3365,13 @@
* Tail Descriptor Pointers
*/
E1000_WRITE_REG(&adapter->hw, E1000_RDH(0), 0);
+ rctl = adapter->num_rx_desc - 1; /* default RDT value */
#ifdef DEV_NETMAP
/* preserve buffers already made available to clients */
- if (ifp->if_capenable & IFCAP_NETMAP) {
- struct netmap_adapter *na = NA(adapter->ifp);
- struct netmap_kring *kring = &na->rx_rings[0];
- int t = na->num_rx_desc - 1 - kring->nr_hwavail;
-
- if (t >= na->num_rx_desc)
- t -= na->num_rx_desc;
- E1000_WRITE_REG(&adapter->hw, E1000_RDT(0), t);
- } else
+ if (ifp->if_capenable & IFCAP_NETMAP)
+ rctl -= NA(adapter->ifp)->rx_rings[0].nr_hwavail;
#endif /* DEV_NETMAP */
- E1000_WRITE_REG(&adapter->hw, E1000_RDT(0), adapter->num_rx_desc - 1);
+ E1000_WRITE_REG(&adapter->hw, E1000_RDT(0), rctl);
return;
}
@@ -3460,7 +3441,7 @@
static bool
lem_rxeof(struct adapter *adapter, int count, int *done)
{
- struct ifnet *ifp = adapter->ifp;;
+ struct ifnet *ifp = adapter->ifp;
struct mbuf *mp;
u8 status = 0, accept_frame = 0, eop = 0;
u16 len, desc_len, prev_len_adj;
@@ -3474,13 +3455,8 @@
BUS_DMASYNC_POSTREAD);
#ifdef DEV_NETMAP
- if (ifp->if_capenable & IFCAP_NETMAP) {
- struct netmap_adapter *na = NA(ifp);
- na->rx_rings[0].nr_kflags |= NKR_PENDINTR;
- selwakeuppri(&na->rx_rings[0].si, PI_NET);
- EM_RX_UNLOCK(adapter);
- return (0);
- }
+ if (netmap_rx_irq(ifp, 0 | NETMAP_LOCKED_ENTER, &rx_sent))
+ return (FALSE);
#endif /* DEV_NETMAP */
if (!((current_desc->status) & E1000_RXD_STAT_DD)) {
@@ -3597,7 +3573,7 @@
adapter->lmp = NULL;
}
} else {
- ifp->if_ierrors++;
+ adapter->dropped_pkts++;
discard:
/* Reuse loaded DMA map and just update mbuf chain */
mp = adapter->rx_buffer_area[i].m_head;
@@ -3673,7 +3649,7 @@
bcopy(m->m_data, m->m_data + ETHER_HDR_LEN, m->m_len);
m->m_data += ETHER_HDR_LEN;
} else {
- MGETHDR(n, M_DONTWAIT, MT_DATA);
+ MGETHDR(n, M_NOWAIT, MT_DATA);
if (n != NULL) {
bcopy(m->m_data, n->m_data, ETHER_HDR_LEN);
m->m_data += ETHER_HDR_LEN;
@@ -3822,10 +3798,6 @@
reg &= ~E1000_RCTL_CFIEN;
reg |= E1000_RCTL_VFE;
E1000_WRITE_REG(hw, E1000_RCTL, reg);
-
- /* Update the frame size */
- E1000_WRITE_REG(&adapter->hw, E1000_RLPML,
- adapter->max_frame_size + VLAN_TAG_SIZE);
}
static void
@@ -3834,10 +3806,6 @@
struct e1000_hw *hw = &adapter->hw;
u32 ims_mask = IMS_ENABLE_MASK;
- if (adapter->msix) {
- E1000_WRITE_REG(hw, EM_EIAC, EM_MSIX_MASK);
- ims_mask |= EM_MSIX_MASK;
- }
E1000_WRITE_REG(hw, E1000_IMS, ims_mask);
}
@@ -3846,9 +3814,7 @@
{
struct e1000_hw *hw = &adapter->hw;
- if (adapter->msix)
- E1000_WRITE_REG(hw, EM_EIAC, 0);
- E1000_WRITE_REG(&adapter->hw, E1000_IMC, 0xffffffff);
+ E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff);
}
/*
@@ -4634,6 +4600,8 @@
return (EINVAL);
info->value = usecs;
ticks = EM_USECS_TO_TICKS(usecs);
+ if (info->offset == E1000_ITR) /* units are 256ns here */
+ ticks *= 4;
adapter = info->adapter;
@@ -4682,7 +4650,6 @@
OID_AUTO, name, CTLTYPE_INT|CTLFLAG_RW, limit, value, description);
}
-#ifndef EM_LEGACY_IRQ
static void
lem_add_rx_process_limit(struct adapter *adapter, const char *name,
const char *description, int *limit, int value)
@@ -4692,4 +4659,3 @@
SYSCTL_CHILDREN(device_get_sysctl_tree(adapter->dev)),
OID_AUTO, name, CTLTYPE_INT|CTLFLAG_RW, limit, value, description);
}
-#endif
Property changes on: trunk/sys/dev/e1000/if_lem.c
___________________________________________________________________
Deleted: cvs2svn:cvs-rev
## -1 +0,0 ##
-1.3
\ No newline at end of property
Modified: trunk/sys/dev/e1000/if_lem.h
===================================================================
--- trunk/sys/dev/e1000/if_lem.h 2013-12-28 14:30:04 UTC (rev 6559)
+++ trunk/sys/dev/e1000/if_lem.h 2013-12-28 14:30:47 UTC (rev 6560)
@@ -1,3 +1,4 @@
+/* $MidnightBSD$ */
/******************************************************************************
Copyright (c) 2001-2011, Intel Corporation
@@ -30,7 +31,7 @@
POSSIBILITY OF SUCH DAMAGE.
******************************************************************************/
-/*$MidnightBSD$*/
+/*$FreeBSD: release/9.2.0/sys/dev/e1000/if_lem.h 250458 2013-05-10 16:16:33Z luigi $*/
#ifndef _LEM_H_DEFINED_
@@ -363,6 +364,7 @@
struct em_int_delay_info tx_abs_int_delay;
struct em_int_delay_info rx_int_delay;
struct em_int_delay_info rx_abs_int_delay;
+ struct em_int_delay_info tx_itr;
/*
* Transmit definitions
Property changes on: trunk/sys/dev/e1000/if_lem.h
___________________________________________________________________
Deleted: cvs2svn:cvs-rev
## -1 +0,0 ##
-1.3
\ No newline at end of property
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