[Midnightbsd-cvs] src [7234] trunk/sys/dev: sync cas with freebsd 9-stable and fix another const warning in bge
laffer1 at midnightbsd.org
laffer1 at midnightbsd.org
Tue Aug 11 21:20:39 EDT 2015
Revision: 7234
http://svnweb.midnightbsd.org/src/?rev=7234
Author: laffer1
Date: 2015-08-11 21:20:39 -0400 (Tue, 11 Aug 2015)
Log Message:
-----------
sync cas with freebsd 9-stable and fix another const warning in bge
Modified Paths:
--------------
trunk/sys/dev/bge/if_bge.c
trunk/sys/dev/cas/if_cas.c
Modified: trunk/sys/dev/bge/if_bge.c
===================================================================
--- trunk/sys/dev/bge/if_bge.c 2015-08-12 01:15:18 UTC (rev 7233)
+++ trunk/sys/dev/bge/if_bge.c 2015-08-12 01:20:39 UTC (rev 7234)
@@ -328,7 +328,7 @@
* Some defaults for major revisions, so that newer steppings
* that we don't know about have a shot at working.
*/
-static const struct bge_revision const bge_majorrevs[] = {
+static const struct bge_revision bge_majorrevs[] = {
{ BGE_ASICREV_BCM5700, "unknown BCM5700" },
{ BGE_ASICREV_BCM5701, "unknown BCM5701" },
{ BGE_ASICREV_BCM5703, "unknown BCM5703" },
Modified: trunk/sys/dev/cas/if_cas.c
===================================================================
--- trunk/sys/dev/cas/if_cas.c 2015-08-12 01:15:18 UTC (rev 7233)
+++ trunk/sys/dev/cas/if_cas.c 2015-08-12 01:20:39 UTC (rev 7234)
@@ -214,8 +214,12 @@
error = ENXIO;
goto fail_ifnet;
}
- taskqueue_start_threads(&sc->sc_tq, 1, PI_NET, "%s taskq",
+ error = taskqueue_start_threads(&sc->sc_tq, 1, PI_NET, "%s taskq",
device_get_nameunit(sc->sc_dev));
+ if (error != 0) {
+ device_printf(sc->sc_dev, "could not start threads\n");
+ goto fail_taskq;
+ }
/* Make sure the chip is stopped. */
cas_reset(sc);
@@ -339,10 +343,13 @@
BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE);
/* Enable/unfreeze the GMII pins of Saturn. */
if (sc->sc_variant == CAS_SATURN) {
- CAS_WRITE_4(sc, CAS_SATURN_PCFG, 0);
+ CAS_WRITE_4(sc, CAS_SATURN_PCFG,
+ CAS_READ_4(sc, CAS_SATURN_PCFG) &
+ ~CAS_SATURN_PCFG_FSI);
CAS_BARRIER(sc, CAS_SATURN_PCFG, 4,
BUS_SPACE_BARRIER_READ |
BUS_SPACE_BARRIER_WRITE);
+ DELAY(10000);
}
error = mii_attach(sc->sc_dev, &sc->sc_miibus, ifp,
cas_mediachange, cas_mediastatus, BMSR_DEFCAPMASK,
@@ -359,10 +366,12 @@
/* Freeze the GMII pins of Saturn for saving power. */
if (sc->sc_variant == CAS_SATURN) {
CAS_WRITE_4(sc, CAS_SATURN_PCFG,
+ CAS_READ_4(sc, CAS_SATURN_PCFG) |
CAS_SATURN_PCFG_FSI);
CAS_BARRIER(sc, CAS_SATURN_PCFG, 4,
BUS_SPACE_BARRIER_READ |
BUS_SPACE_BARRIER_WRITE);
+ DELAY(10000);
}
error = mii_attach(sc->sc_dev, &sc->sc_miibus, ifp,
cas_mediachange, cas_mediastatus, BMSR_DEFCAPMASK,
@@ -815,7 +824,8 @@
BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE);
if (cas_bitwait(sc, CAS_MAC_RX_CONF, CAS_MAC_RX_CONF_EN, 0))
return (1);
- device_printf(sc->sc_dev, "cannot disable RX MAC\n");
+ if (bootverbose)
+ device_printf(sc->sc_dev, "cannot disable RX MAC\n");
return (0);
}
@@ -829,7 +839,8 @@
BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE);
if (cas_bitwait(sc, CAS_MAC_TX_CONF, CAS_MAC_TX_CONF_EN, 0))
return (1);
- device_printf(sc->sc_dev, "cannot disable TX MAC\n");
+ if (bootverbose)
+ device_printf(sc->sc_dev, "cannot disable TX MAC\n");
return (0);
}
@@ -1032,7 +1043,8 @@
/*
* Enable infinite bursts for revisions without PCI issues if
* applicable. Doing so greatly improves the TX performance on
- * !__sparc64__.
+ * !__sparc64__ (on sparc64, setting CAS_INF_BURST improves TX
+ * performance only marginally but hurts RX throughput quite a bit).
*/
CAS_WRITE_4(sc, CAS_INF_BURST,
#if !defined(__sparc64__)
@@ -1192,7 +1204,7 @@
cflags = 0;
if (((*m_head)->m_pkthdr.csum_flags & CAS_CSUM_FEATURES) != 0) {
if (M_WRITABLE(*m_head) == 0) {
- m = m_dup(*m_head, M_DONTWAIT);
+ m = m_dup(*m_head, M_NOWAIT);
m_freem(*m_head);
*m_head = m;
if (m == NULL)
@@ -1215,7 +1227,7 @@
error = bus_dmamap_load_mbuf_sg(sc->sc_tdmatag, txs->txs_dmamap,
*m_head, txsegs, &nsegs, BUS_DMA_NOWAIT);
if (error == EFBIG) {
- m = m_collapse(*m_head, M_DONTWAIT, CAS_NTXSEGS);
+ m = m_collapse(*m_head, M_NOWAIT, CAS_NTXSEGS);
if (m == NULL) {
m_freem(*m_head);
*m_head = NULL;
@@ -1714,7 +1726,7 @@
__func__, idx, off, len);
#endif
rxds = &sc->sc_rxdsoft[idx];
- MGETHDR(m, M_DONTWAIT, MT_DATA);
+ MGETHDR(m, M_NOWAIT, MT_DATA);
if (m != NULL) {
refcount_acquire(&rxds->rxds_refcount);
bus_dmamap_sync(sc->sc_rdmatag,
@@ -1759,7 +1771,7 @@
__func__, idx, off, len);
#endif
rxds = &sc->sc_rxdsoft[idx];
- MGETHDR(m, M_DONTWAIT, MT_DATA);
+ MGETHDR(m, M_NOWAIT, MT_DATA);
if (m != NULL) {
refcount_acquire(&rxds->rxds_refcount);
off += ETHER_ALIGN;
@@ -1796,7 +1808,7 @@
#endif
rxds2 = &sc->sc_rxdsoft[idx2];
if (m != NULL) {
- MGET(m2, M_DONTWAIT, MT_DATA);
+ MGET(m2, M_NOWAIT, MT_DATA);
if (m2 != NULL) {
refcount_acquire(
&rxds2->rxds_refcount);
@@ -2623,7 +2635,7 @@
uint8_t cpd_revid;
int cpd_variant;
const char *cpd_desc;
-} const cas_pci_devlist[] = {
+} cas_pci_devlist[] = {
{ 0x0035100b, 0x0, CAS_SATURN, "NS DP83065 Saturn Gigabit Ethernet" },
{ 0xabba108e, 0x10, CAS_CASPLUS, "Sun Cassini+ Gigabit Ethernet" },
{ 0xabba108e, 0x0, CAS_CAS, "Sun Cassini Gigabit Ethernet" },
@@ -2682,7 +2694,10 @@
return (ENXIO);
}
- pci_enable_busmaster(dev);
+ /* PCI configuration */
+ pci_write_config(dev, PCIR_COMMAND,
+ pci_read_config(dev, PCIR_COMMAND, 2) | PCIM_CMD_BUSMASTEREN |
+ PCIM_CMD_MWRICEN | PCIM_CMD_PERRESPEN | PCIM_CMD_SERRESPEN, 2);
sc->sc_dev = dev;
if (sc->sc_variant == CAS_CAS && pci_get_devid(dev) < 0x02)
@@ -2865,7 +2880,7 @@
goto fail;
}
i = 0;
- if (lma > 1 && pci_get_slot(dev) < sizeof(enaddr) / sizeof(*enaddr))
+ if (lma > 1 && pci_get_slot(dev) < nitems(enaddr))
i = pci_get_slot(dev);
memcpy(sc->sc_enaddr, enaddr[i], ETHER_ADDR_LEN);
@@ -2874,7 +2889,7 @@
goto fail;
}
i = 0;
- if (phy > 1 && pci_get_slot(dev) < sizeof(pcs) / sizeof(*pcs))
+ if (phy > 1 && pci_get_slot(dev) < nitems(pcs))
i = pci_get_slot(dev);
if (pcs[i] != 0)
sc->sc_flags |= CAS_SERDES;
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