[Midnightbsd-cvs] src [7303] trunk/sys: add support for the Realtek 8168/ 8111 G and the 8106E
laffer1 at midnightbsd.org
laffer1 at midnightbsd.org
Sat Sep 5 08:03:18 EDT 2015
Revision: 7303
http://svnweb.midnightbsd.org/src/?rev=7303
Author: laffer1
Date: 2015-09-05 08:03:17 -0400 (Sat, 05 Sep 2015)
Log Message:
-----------
add support for the Realtek 8168/8111 G and the 8106E
Modified Paths:
--------------
trunk/sys/dev/re/if_re.c
trunk/sys/pci/if_rlreg.h
Modified: trunk/sys/dev/re/if_re.c
===================================================================
--- trunk/sys/dev/re/if_re.c 2015-09-05 11:47:59 UTC (rev 7302)
+++ trunk/sys/dev/re/if_re.c 2015-09-05 12:03:17 UTC (rev 7303)
@@ -181,7 +181,7 @@
{ RT_VENDORID, RT_DEVICEID_8101E, 0,
"RealTek 810xE PCIe 10/100baseTX" },
{ RT_VENDORID, RT_DEVICEID_8168, 0,
- "RealTek 8168/8111 B/C/CP/D/DP/E/F PCIe Gigabit Ethernet" },
+ "RealTek 8168/8111 B/C/CP/D/DP/E/F/G PCIe Gigabit Ethernet" },
{ RT_VENDORID, RT_DEVICEID_8169, 0,
"RealTek 8169/8169S/8169SB(L)/8110S/8110SB(L) Gigabit Ethernet" },
{ RT_VENDORID, RT_DEVICEID_8169SC, 0,
@@ -223,6 +223,7 @@
{ RL_HWREV_8402, RL_8169, "8402", RL_MTU },
{ RL_HWREV_8105E, RL_8169, "8105E", RL_MTU },
{ RL_HWREV_8105E_SPIN1, RL_8169, "8105E", RL_MTU },
+ { RL_HWREV_8106E, RL_8169, "8106E", RL_MTU },
{ RL_HWREV_8168B_SPIN2, RL_8169, "8168", RL_JUMBO_MTU },
{ RL_HWREV_8168B_SPIN3, RL_8169, "8168", RL_JUMBO_MTU },
{ RL_HWREV_8168C, RL_8169, "8168C/8111C", RL_JUMBO_MTU_6K },
@@ -232,8 +233,12 @@
{ RL_HWREV_8168DP, RL_8169, "8168DP/8111DP", RL_JUMBO_MTU_9K },
{ RL_HWREV_8168E, RL_8169, "8168E/8111E", RL_JUMBO_MTU_9K},
{ RL_HWREV_8168E_VL, RL_8169, "8168E/8111E-VL", RL_JUMBO_MTU_6K},
+ { RL_HWREV_8168EP, RL_8169, "8168EP/8111EP", RL_JUMBO_MTU_9K},
{ RL_HWREV_8168F, RL_8169, "8168F/8111F", RL_JUMBO_MTU_9K},
+ { RL_HWREV_8168G, RL_8169, "8168G/8111G", RL_JUMBO_MTU_9K},
+ { RL_HWREV_8168GU, RL_8169, "8168GU/8111GU", RL_JUMBO_MTU_9K},
{ RL_HWREV_8411, RL_8169, "8411", RL_JUMBO_MTU_9K},
+ { RL_HWREV_8411B, RL_8169, "8411B", RL_JUMBO_MTU_9K},
{ 0, 0, NULL, 0 }
};
@@ -650,6 +655,10 @@
ifp = sc->rl_ifp;
rxfilt = RL_RXCFG_CONFIG | RL_RXCFG_RX_INDIV | RL_RXCFG_RX_BROAD;
+ if ((sc->rl_flags & RL_FLAG_EARLYOFF) != 0)
+ rxfilt |= RL_RXCFG_EARLYOFF;
+ else if ((sc->rl_flags & RL_FLAG_EARLYOFFV2) != 0)
+ rxfilt |= RL_RXCFG_EARLYOFFV2;
if (ifp->if_flags & (IFF_ALLMULTI | IFF_PROMISC)) {
if (ifp->if_flags & IFF_PROMISC)
@@ -693,6 +702,12 @@
rxfilt |= RL_RXCFG_RX_MULTI;
}
+ if (sc->rl_hwrev->rl_rev == RL_HWREV_8168F) {
+ /* Disable multicast filtering due to silicon bug. */
+ hashes[0] = 0xffffffff;
+ hashes[1] = 0xffffffff;
+ }
+
done:
CSR_WRITE_4(sc, RL_MAR0, hashes[0]);
CSR_WRITE_4(sc, RL_MAR4, hashes[1]);
@@ -758,7 +773,7 @@
u_int8_t src[] = { 0x00, 'w', 'o', 'r', 'l', 'd' };
/* Allocate a single mbuf */
- MGETHDR(m0, M_DONTWAIT, MT_DATA);
+ MGETHDR(m0, M_NOWAIT, MT_DATA);
if (m0 == NULL)
return (ENOBUFS);
@@ -1259,7 +1274,7 @@
msic = 0;
/* Prefer MSI-X to MSI. */
if (msixc > 0) {
- msixc = 1;
+ msixc = RL_MSI_MESSAGES;
rid = PCIR_BAR(4);
sc->rl_res_pba = bus_alloc_resource_any(dev, SYS_RES_MEMORY,
&rid, RF_ACTIVE);
@@ -1269,7 +1284,7 @@
}
if (sc->rl_res_pba != NULL &&
pci_alloc_msix(dev, &msixc) == 0) {
- if (msixc == 1) {
+ if (msixc == RL_MSI_MESSAGES) {
device_printf(dev, "Using %d MSI-X message\n",
msixc);
sc->rl_flags |= RL_FLAG_MSIX;
@@ -1286,7 +1301,7 @@
}
/* Prefer MSI to INTx. */
if (msixc == 0 && msic > 0) {
- msic = 1;
+ msic = RL_MSI_MESSAGES;
if (pci_alloc_msi(dev, &msic) == 0) {
if (msic == RL_MSI_MESSAGES) {
device_printf(dev, "Using %d MSI message\n",
@@ -1346,11 +1361,11 @@
PCIR_EXPRESS_LINK_CAP, 2);
if ((cap & PCIM_LINK_CAP_ASPM) != 0) {
ctl = pci_read_config(dev, sc->rl_expcap +
- PCIR_EXPRESS_LINK_CTL, 2);
+ PCIER_LINK_CTL, 2);
if ((ctl & 0x0003) != 0) {
ctl &= ~0x0003;
pci_write_config(dev, sc->rl_expcap +
- PCIR_EXPRESS_LINK_CTL, ctl, 2);
+ PCIER_LINK_CTL, ctl, 2);
device_printf(dev, "ASPM disabled\n");
}
} else
@@ -1367,10 +1382,11 @@
break;
default:
device_printf(dev, "Chip rev. 0x%08x\n", hwrev & 0x7c800000);
+ sc->rl_macrev = hwrev & 0x00700000;
hwrev &= RL_TXCFG_HWREV;
break;
}
- device_printf(dev, "MAC rev. 0x%08x\n", hwrev & 0x00700000);
+ device_printf(dev, "MAC rev. 0x%08x\n", sc->rl_macrev);
while (hw_rev->rl_desc != NULL) {
if (hw_rev->rl_rev == hwrev) {
sc->rl_type = hw_rev->rl_type;
@@ -1408,6 +1424,7 @@
case RL_HWREV_8401E:
case RL_HWREV_8105E:
case RL_HWREV_8105E_SPIN1:
+ case RL_HWREV_8106E:
sc->rl_flags |= RL_FLAG_PHYWAKE | RL_FLAG_PHYWAKE_PM |
RL_FLAG_PAR | RL_FLAG_DESCV2 | RL_FLAG_MACSTAT |
RL_FLAG_FASTETHER | RL_FLAG_CMDSTOP | RL_FLAG_AUTOPAD;
@@ -1429,7 +1446,7 @@
sc->rl_flags |= RL_FLAG_MACSLEEP;
/* FALLTHROUGH */
case RL_HWREV_8168C:
- if ((hwrev & 0x00700000) == 0x00200000)
+ if (sc->rl_macrev == 0x00200000)
sc->rl_flags |= RL_FLAG_MACSLEEP;
/* FALLTHROUGH */
case RL_HWREV_8168CP:
@@ -1456,6 +1473,8 @@
break;
case RL_HWREV_8168E_VL:
case RL_HWREV_8168F:
+ sc->rl_flags |= RL_FLAG_EARLYOFF;
+ /* FALLTHROUGH */
case RL_HWREV_8411:
sc->rl_flags |= RL_FLAG_PHYWAKE | RL_FLAG_PAR |
RL_FLAG_DESCV2 | RL_FLAG_MACSTAT | RL_FLAG_CMDSTOP |
@@ -1462,6 +1481,27 @@
RL_FLAG_AUTOPAD | RL_FLAG_JUMBOV2 |
RL_FLAG_CMDSTOP_WAIT_TXQ | RL_FLAG_WOL_MANLINK;
break;
+ case RL_HWREV_8168EP:
+ case RL_HWREV_8168G:
+ case RL_HWREV_8411B:
+ sc->rl_flags |= RL_FLAG_PHYWAKE | RL_FLAG_PAR |
+ RL_FLAG_DESCV2 | RL_FLAG_MACSTAT | RL_FLAG_CMDSTOP |
+ RL_FLAG_AUTOPAD | RL_FLAG_JUMBOV2 |
+ RL_FLAG_CMDSTOP_WAIT_TXQ | RL_FLAG_WOL_MANLINK |
+ RL_FLAG_EARLYOFFV2 | RL_FLAG_RXDV_GATED;
+ break;
+ case RL_HWREV_8168GU:
+ if (pci_get_device(dev) == RT_DEVICEID_8101E) {
+ /* RTL8106EUS */
+ sc->rl_flags |= RL_FLAG_FASTETHER;
+ } else
+ sc->rl_flags |= RL_FLAG_JUMBOV2 | RL_FLAG_WOL_MANLINK;
+
+ sc->rl_flags |= RL_FLAG_PHYWAKE | RL_FLAG_PAR |
+ RL_FLAG_DESCV2 | RL_FLAG_MACSTAT | RL_FLAG_CMDSTOP |
+ RL_FLAG_AUTOPAD | RL_FLAG_CMDSTOP_WAIT_TXQ |
+ RL_FLAG_EARLYOFFV2 | RL_FLAG_RXDV_GATED;
+ break;
case RL_HWREV_8169_8110SB:
case RL_HWREV_8169_8110SBL:
case RL_HWREV_8169_8110SC:
@@ -1584,15 +1624,18 @@
ifp->if_start = re_start;
/*
* RTL8168/8111C generates wrong IP checksummed frame if the
- * packet has IP options so disable TX IP checksum offloading.
+ * packet has IP options so disable TX checksum offloading.
*/
if (sc->rl_hwrev->rl_rev == RL_HWREV_8168C ||
- sc->rl_hwrev->rl_rev == RL_HWREV_8168C_SPIN2)
- ifp->if_hwassist = CSUM_TCP | CSUM_UDP;
- else
+ sc->rl_hwrev->rl_rev == RL_HWREV_8168C_SPIN2 ||
+ sc->rl_hwrev->rl_rev == RL_HWREV_8168CP) {
+ ifp->if_hwassist = 0;
+ ifp->if_capabilities = IFCAP_RXCSUM | IFCAP_TSO4;
+ } else {
ifp->if_hwassist = CSUM_IP | CSUM_TCP | CSUM_UDP;
+ ifp->if_capabilities = IFCAP_HWCSUM | IFCAP_TSO4;
+ }
ifp->if_hwassist |= CSUM_TSO;
- ifp->if_capabilities = IFCAP_HWCSUM | IFCAP_TSO4;
ifp->if_capenable = ifp->if_capabilities;
ifp->if_init = re_init;
IFQ_SET_MAXLEN(&ifp->if_snd, RL_IFQ_MAXLEN);
@@ -1753,8 +1796,12 @@
bus_teardown_intr(dev, sc->rl_irq[0], sc->rl_intrhand[0]);
sc->rl_intrhand[0] = NULL;
}
- if (ifp != NULL)
+ if (ifp != NULL) {
+#ifdef DEV_NETMAP
+ netmap_detach(ifp);
+#endif /* DEV_NETMAP */
if_free(ifp);
+ }
if ((sc->rl_flags & (RL_FLAG_MSI | RL_FLAG_MSIX)) == 0)
rid = 0;
else
@@ -1843,9 +1890,6 @@
bus_dma_tag_destroy(sc->rl_ldata.rl_stag);
}
-#ifdef DEV_NETMAP
- netmap_detach(ifp);
-#endif /* DEV_NETMAP */
if (sc->rl_parent_tag)
bus_dma_tag_destroy(sc->rl_parent_tag);
@@ -1885,7 +1929,7 @@
uint32_t cmdstat;
int error, nsegs;
- m = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR);
+ m = m_getcl(M_NOWAIT, MT_DATA, M_PKTHDR);
if (m == NULL)
return (ENOBUFS);
@@ -1949,7 +1993,7 @@
uint32_t cmdstat;
int error, nsegs;
- m = m_getjcl(M_DONTWAIT, MT_DATA, M_PKTHDR, MJUM9BYTES);
+ m = m_getjcl(M_NOWAIT, MT_DATA, M_PKTHDR, MJUM9BYTES);
if (m == NULL)
return (ENOBUFS);
m->m_len = m->m_pkthdr.len = MJUM9BYTES;
@@ -2110,11 +2154,8 @@
ifp = sc->rl_ifp;
#ifdef DEV_NETMAP
- if (ifp->if_capenable & IFCAP_NETMAP) {
- NA(ifp)->rx_rings->nr_kflags |= NKR_PENDINTR;
- selwakeuppri(&NA(ifp)->rx_rings->si, PI_NET);
+ if (netmap_rx_irq(ifp, 0, &rx_npkts))
return 0;
- }
#endif /* DEV_NETMAP */
if (ifp->if_mtu > RL_MTU && (sc->rl_flags & RL_FLAG_JUMBOV2) != 0)
jumbo = 1;
@@ -2358,10 +2399,8 @@
ifp = sc->rl_ifp;
#ifdef DEV_NETMAP
- if (ifp->if_capenable & IFCAP_NETMAP) {
- selwakeuppri(&NA(ifp)->tx_rings[0].si, PI_NET);
+ if (netmap_tx_irq(ifp, 0))
return;
- }
#endif /* DEV_NETMAP */
/* Invalidate the TX descriptor list */
bus_dmamap_sync(sc->rl_ldata.rl_tx_list_tag,
@@ -2699,7 +2738,7 @@
padlen = RL_MIN_FRAMELEN - (*m_head)->m_pkthdr.len;
if (M_WRITABLE(*m_head) == 0) {
/* Get a writable copy. */
- m_new = m_dup(*m_head, M_DONTWAIT);
+ m_new = m_dup(*m_head, M_NOWAIT);
m_freem(*m_head);
if (m_new == NULL) {
*m_head = NULL;
@@ -2709,7 +2748,7 @@
}
if ((*m_head)->m_next != NULL ||
M_TRAILINGSPACE(*m_head) < padlen) {
- m_new = m_defrag(*m_head, M_DONTWAIT);
+ m_new = m_defrag(*m_head, M_NOWAIT);
if (m_new == NULL) {
m_freem(*m_head);
*m_head = NULL;
@@ -2733,7 +2772,7 @@
error = bus_dmamap_load_mbuf_sg(sc->rl_ldata.rl_tx_mtag, txd->tx_dmamap,
*m_head, segs, &nsegs, BUS_DMA_NOWAIT);
if (error == EFBIG) {
- m_new = m_collapse(*m_head, M_DONTWAIT, RL_NTXSEGS);
+ m_new = m_collapse(*m_head, M_NOWAIT, RL_NTXSEGS);
if (m_new == NULL) {
m_freem(*m_head);
*m_head = NULL;
@@ -3151,10 +3190,9 @@
CSR_WRITE_4(sc, RL_TXLIST_ADDR_LO,
RL_ADDR_LO(sc->rl_ldata.rl_tx_list_addr));
- /*
- * Enable transmit and receive.
- */
- CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_TX_ENB|RL_CMD_RX_ENB);
+ if ((sc->rl_flags & RL_FLAG_RXDV_GATED) != 0)
+ CSR_WRITE_4(sc, RL_MISC, CSR_READ_4(sc, RL_MISC) &
+ ~0x00080000);
/*
* Set the initial TX configuration.
@@ -3182,6 +3220,11 @@
CSR_WRITE_2(sc, RL_INTRMOD, 0x5100);
}
+ /*
+ * Enable transmit and receive.
+ */
+ CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_TX_ENB | RL_CMD_RX_ENB);
+
#ifdef DEVICE_POLLING
/*
* Disable interrupts if we are polling.
@@ -3205,10 +3248,6 @@
/* Start RX/TX process. */
CSR_WRITE_4(sc, RL_MISSEDPKT, 0);
-#ifdef notdef
- /* Enable receiver and transmitter. */
- CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_TX_ENB|RL_CMD_RX_ENB);
-#endif
/*
* Initialize the timer interrupt register so that
@@ -3328,13 +3367,14 @@
struct rl_softc *sc = ifp->if_softc;
struct ifreq *ifr = (struct ifreq *) data;
struct mii_data *mii;
- uint32_t rev;
int error = 0;
switch (command) {
case SIOCSIFMTU:
if (ifr->ifr_mtu < ETHERMIN ||
- ifr->ifr_mtu > sc->rl_hwrev->rl_max_mtu) {
+ ifr->ifr_mtu > sc->rl_hwrev->rl_max_mtu ||
+ ((sc->rl_flags & RL_FLAG_FASTETHER) != 0 &&
+ ifr->ifr_mtu > RL_MTU)) {
error = EINVAL;
break;
}
@@ -3415,14 +3455,9 @@
if ((mask & IFCAP_TXCSUM) != 0 &&
(ifp->if_capabilities & IFCAP_TXCSUM) != 0) {
ifp->if_capenable ^= IFCAP_TXCSUM;
- if ((ifp->if_capenable & IFCAP_TXCSUM) != 0) {
- rev = sc->rl_hwrev->rl_rev;
- if (rev == RL_HWREV_8168C ||
- rev == RL_HWREV_8168C_SPIN2)
- ifp->if_hwassist |= CSUM_TCP | CSUM_UDP;
- else
- ifp->if_hwassist |= RE_CSUM_FEATURES;
- } else
+ if ((ifp->if_capenable & IFCAP_TXCSUM) != 0)
+ ifp->if_hwassist |= RE_CSUM_FEATURES;
+ else
ifp->if_hwassist &= ~RE_CSUM_FEATURES;
reinit = 1;
}
Modified: trunk/sys/pci/if_rlreg.h
===================================================================
--- trunk/sys/pci/if_rlreg.h 2015-09-05 11:47:59 UTC (rev 7302)
+++ trunk/sys/pci/if_rlreg.h 2015-09-05 12:03:17 UTC (rev 7303)
@@ -29,7 +29,7 @@
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
* THE POSSIBILITY OF SUCH DAMAGE.
*
- * $MidnightBSD: src/sys/pci/if_rlreg.h,v 1.12 2013/01/17 23:29:42 laffer1 Exp $
+ * $MidnightBSD$
*/
/*
@@ -145,6 +145,7 @@
#define RL_PMCH 0x006F /* 8 bits */
#define RL_MAXRXPKTLEN 0x00DA /* 16 bits, chip multiplies by 8 */
#define RL_INTRMOD 0x00E2 /* 16 bits */
+#define RL_MISC 0x00F0
/*
* TX config register bits
@@ -163,7 +164,6 @@
#define RL_LOOPTEST_ON_CPLUS 0x00060000
/* Known revision codes. */
-
#define RL_HWREV_8169 0x00000000
#define RL_HWREV_8169S 0x00800000
#define RL_HWREV_8110S 0x04000000
@@ -189,8 +189,13 @@
#define RL_HWREV_8105E 0x40800000
#define RL_HWREV_8105E_SPIN1 0x40C00000
#define RL_HWREV_8402 0x44000000
+#define RL_HWREV_8106E 0x44800000
#define RL_HWREV_8168F 0x48000000
#define RL_HWREV_8411 0x48800000
+#define RL_HWREV_8168G 0x4C000000
+#define RL_HWREV_8168EP 0x50000000
+#define RL_HWREV_8168GU 0x50800000
+#define RL_HWREV_8411B 0x5C800000
#define RL_HWREV_8139 0x60000000
#define RL_HWREV_8139A 0x70000000
#define RL_HWREV_8139AG 0x70800000
@@ -282,8 +287,10 @@
#define RL_RXCFG_RX_RUNT 0x00000010
#define RL_RXCFG_RX_ERRPKT 0x00000020
#define RL_RXCFG_WRAP 0x00000080
+#define RL_RXCFG_EARLYOFFV2 0x00000800
#define RL_RXCFG_MAXDMA 0x00000700
#define RL_RXCFG_BUFSZ 0x00001800
+#define RL_RXCFG_EARLYOFF 0x00003800
#define RL_RXCFG_FIFOTHRESH 0x0000E000
#define RL_RXCFG_EARLYTHRESH 0x07000000
@@ -324,8 +331,8 @@
#define RL_RXSTAT_INDIV 0x00004000
#define RL_RXSTAT_MULTI 0x00008000
#define RL_RXSTAT_LENMASK 0xFFFF0000
+#define RL_RXSTAT_UNFINISHED 0x0000FFF0 /* DMA still in progress */
-#define RL_RXSTAT_UNFINISHED 0xFFF0 /* DMA still in progress */
/*
* Command register.
*/
@@ -356,6 +363,7 @@
#define RL_PARA7C 0x7C
#define RL_PARA7C_DEF 0xcb38de43
#define RL_PARA7C_RETUNE 0xfb38de03
+
/*
* EEPROM control register
*/
@@ -468,11 +476,9 @@
*/
/* RL_DUMPSTATS_LO register */
-
#define RL_DUMPSTATS_START 0x00000008
/* Transmit start register */
-
#define RL_TXSTART_SWI 0x01 /* generate TX interrupt */
#define RL_TXSTART_START 0x40 /* start normal queue transmit */
#define RL_TXSTART_HPRIO_START 0x80 /* start hi prio queue transmit */
@@ -491,7 +497,6 @@
#define RL_BUSWIDTH_64BITS 0x08
/* C+ mode command register */
-
#define RL_CPLUSCMD_TXENB 0x0001 /* enable C+ transmit mode */
#define RL_CPLUSCMD_RXENB 0x0002 /* enable C+ receive mode */
#define RL_CPLUSCMD_PCI_MRW 0x0008 /* enable PCI multi-read/write */
@@ -509,7 +514,6 @@
#define RL_CPLUSCMD_BIST_ENB 0x8000 /* 8168C/CP */
/* C+ early transmit threshold */
-
#define RL_EARLYTXTHRESH_CNT 0x003F /* byte count times 8 */
/* Timer interrupt register */
@@ -523,7 +527,6 @@
/*
* Gigabit PHY access register (8169 only)
*/
-
#define RL_PHYAR_PHYDATA 0x0000FFFF
#define RL_PHYAR_PHYREG 0x001F0000
#define RL_PHYAR_BUSY 0x80000000
@@ -554,7 +557,6 @@
* For reception, there's just one large buffer where the chip stores
* all received packets.
*/
-
#define RL_RX_BUF_SZ RL_RXBUF_64
#define RL_RXBUFLEN (1 << ((RL_RX_BUF_SZ >> 11) + 13))
#define RL_TX_LIST_CNT 4
@@ -637,11 +639,10 @@
/*
* RX/TX descriptor definition. When large send mode is enabled, the
- * lower 11 bits of the TX rl_cmd word are used to hold the MSS, and
+ * lower 11 bits of the TX rl_cmdstat word are used to hold the MSS, and
* the checksum offload bits are disabled. The structure layout is
* the same for RX and TX descriptors
*/
-
struct rl_desc {
uint32_t rl_cmdstat;
uint32_t rl_vlanctl;
@@ -674,7 +675,6 @@
* Error bits are valid only on the last descriptor of a frame
* (i.e. RL_TDESC_CMD_EOF == 1)
*/
-
#define RL_TDESC_STAT_COLCNT 0x000F0000 /* collision count */
#define RL_TDESC_STAT_EXCESSCOL 0x00100000 /* excessive collisions */
#define RL_TDESC_STAT_LINKFAIL 0x00200000 /* link faulure */
@@ -686,7 +686,6 @@
/*
* RX descriptor cmd/vlan definitions
*/
-
#define RL_RDESC_CMD_EOR 0x40000000
#define RL_RDESC_CMD_OWN 0x80000000
#define RL_RDESC_CMD_BUFLEN 0x00001FFF
@@ -777,7 +776,7 @@
#define RL_TX_DESC_CNT RL_8169_TX_DESC_CNT
#define RL_RX_DESC_CNT RL_8169_RX_DESC_CNT
#define RL_RX_JUMBO_DESC_CNT RL_RX_DESC_CNT
-#define RL_NTXSEGS 32
+#define RL_NTXSEGS 35
#define RL_RING_ALIGN 256
#define RL_DUMP_ALIGN 64
@@ -877,6 +876,7 @@
bus_dma_tag_t rl_parent_tag;
uint8_t rl_type;
const struct rl_hwrev *rl_hwrev;
+ uint32_t rl_macrev;
int rl_eecmd_read;
int rl_eewidth;
int rl_expcap;
@@ -929,6 +929,9 @@
#define RL_FLAG_WAIT_TXPOLL 0x00004000
#define RL_FLAG_CMDSTOP_WAIT_TXQ 0x00008000
#define RL_FLAG_WOL_MANLINK 0x00010000
+#define RL_FLAG_EARLYOFF 0x00020000
+#define RL_FLAG_EARLYOFFV2 0x00040000
+#define RL_FLAG_RXDV_GATED 0x00080000
#define RL_FLAG_PCIE 0x40000000
#define RL_FLAG_LINK 0x80000000
};
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