[Midnightbsd-cvs] src [7755] trunk/sys/dev/coretemp/coretemp.c: Catch known CPUs before using IA32_TEMPERATURE_TARGET.

[laffer1 at midnightbsd.org]

Revision: 7755
          http://svnweb.midnightbsd.org/src/?rev=7755
Author:   laffer1
Date:     2016-08-21 00:33:53 -0400 (Sun, 21 Aug 2016)
Log Message:
-----------
Catch known CPUs before using IA32_TEMPERATURE_TARGET.
This way we would have an opportunity to hide the
Tj(target) value doesn't seem right stuff if we know
it's not working there.

Obtained from: FreeBSD

Modified Paths:
--------------
    trunk/sys/dev/coretemp/coretemp.c

Modified: trunk/sys/dev/coretemp/coretemp.c
===================================================================
--- trunk/sys/dev/coretemp/coretemp.c	2016-08-21 04:32:09 UTC (rev 7754)
+++ trunk/sys/dev/coretemp/coretemp.c	2016-08-21 04:33:53 UTC (rev 7755)
@@ -180,34 +180,6 @@
 	 */
 	sc->sc_tjmax = 100;
 
-	/*
-	 * Attempt to get Tj(max) from MSR IA32_TEMPERATURE_TARGET.
-	 *
-	 * This method is described in Intel white paper
-	 * "CPU Monitoring With DTS/PECI". (#322683)
-	 */
-	ret = rdmsr_safe(MSR_IA32_TEMPERATURE_TARGET, &msr);
-	if (ret == 0) {
-		tjtarget = (msr >> 16) & 0xff;
-		/*
-		 * On earlier generation of processors, the value obtained
-		 * from IA32_TEMPERATURE_TARGET register is an offset that
-		 * needs to be summed with a model specific base.  It is
-		 * however not clear what these numbers are, with the
-		 * publicly available documents from Intel.
-		 *
-		 * For now, we consider [70, 100]C range, as described in
-		 * #322683, as "reasonable" and accept these values
-		 * whenever the MSR is available for read, regardless the
-		 * CPU model.
-		 */
-		if (tjtarget >= 70 && tjtarget <= 100)
-			sc->sc_tjmax = tjtarget;
-		else
-			device_printf(dev, "Tj(target) value %d does "
-				    "not seem right.\n", tjtarget);
-	}
-
 	if ((cpu_model == 0xf && cpu_stepping >= 2) || cpu_model == 0xe) {
 		/*
 		 * On some Core 2 CPUs, there's an undocumented MSR that
@@ -219,6 +191,46 @@
 		msr = rdmsr(MSR_IA32_EXT_CONFIG);
 		if (msr & (1 << 30))
 			sc->sc_tjmax = 85;
+	} else if (cpu_model == 0x17) {
+		switch (cpu_stepping) {
+		case 0x6:	/* Mobile Core 2 Duo */
+			sc->sc_tjmax = 104;
+			break;
+		default:	/* Unknown stepping */
+			break;
+		}
+	} else {
+		/*
+		 * Attempt to get Tj(max) from MSR IA32_TEMPERATURE_TARGET.
+		 *
+		 * This method is described in Intel white paper "CPU
+		 * Monitoring With DTS/PECI". (#322683)
+		 */
+		ret = rdmsr_safe(MSR_IA32_TEMPERATURE_TARGET, &msr);
+		if (ret == 0) {
+			tjtarget = (msr >> 16) & 0xff;
+			
+			/*
+			 * On earlier generation of processors, the value
+			 * obtained from IA32_TEMPERATURE_TARGET register is
+			 * an offset that needs to be summed with a model
+			 * specific base.  It is however not clear what
+			 * these numbers are, with the publicly available
+			 * documents from Intel.
+			 *
+			 * For now, we consider [70, 100]C range, as
+			 * described in #322683, as "reasonable" and accept
+			 * these values whenever the MSR is available for
+			 * read, regardless the CPU model.
+			 */
+			if (tjtarget >= 70 && tjtarget <= 100)
+				sc->sc_tjmax = tjtarget;
+			else
+				device_printf(dev, "Tj(target) value %d "
+				    "does not seem right.\n", tjtarget);
+		} else
+			device_printf(dev, "Can not get Tj(target) "
+			    "from your CPU, using 100C.\n");
 	}
 
 	if (bootverbose)