[Midnightbsd-cvs] src [7760] stable/0.8/sys/dev/coretemp/coretemp.c: switch over to freebsd implementation until sensors framework issue is sorted.
laffer1 at midnightbsd.org
laffer1 at midnightbsd.org
Sun Aug 21 11:08:55 EDT 2016
Revision: 7760
http://svnweb.midnightbsd.org/src/?rev=7760
Author: laffer1
Date: 2016-08-21 11:08:55 -0400 (Sun, 21 Aug 2016)
Log Message:
-----------
switch over to freebsd implementation until sensors framework issue is sorted.
Modified Paths:
--------------
stable/0.8/sys/dev/coretemp/coretemp.c
Modified: stable/0.8/sys/dev/coretemp/coretemp.c
===================================================================
--- stable/0.8/sys/dev/coretemp/coretemp.c 2016-08-21 15:05:28 UTC (rev 7759)
+++ stable/0.8/sys/dev/coretemp/coretemp.c 2016-08-21 15:08:55 UTC (rev 7760)
@@ -1,4 +1,3 @@
-/* $MidnightBSD: src/sys/dev/coretemp/coretemp.c,v 1.5 2010/03/05 03:40:43 laffer1 Exp $ */
/*-
* Copyright (c) 2007, 2008 Rui Paulo <rpaulo at FreeBSD.org>
* All rights reserved.
@@ -31,7 +30,7 @@
*/
#include <sys/cdefs.h>
-__FBSDID("$FreeBSD: src/sys/dev/coretemp/coretemp.c,v 1.2.4.3.2.1 2008/11/25 02:59:29 kensmith Exp $");
+__FBSDID("$FreeBSD$");
#include <sys/param.h>
#include <sys/bus.h>
@@ -40,21 +39,30 @@
#include <sys/module.h>
#include <sys/conf.h>
#include <sys/kernel.h>
-#include <sys/sensors.h>
+#include <sys/sysctl.h>
#include <sys/proc.h> /* for curthread */
#include <sys/sched.h>
#include <machine/specialreg.h>
#include <machine/cpufunc.h>
+#include <machine/cputypes.h>
#include <machine/md_var.h>
-extern int smp_cpus;
+#define TZ_ZEROC 2732
+#define THERM_STATUS_LOG 0x02
+#define THERM_STATUS 0x01
+#define THERM_STATUS_TEMP_SHIFT 16
+#define THERM_STATUS_TEMP_MASK 0x7f
+#define THERM_STATUS_RES_SHIFT 27
+#define THERM_STATUS_RES_MASK 0x0f
+#define THERM_STATUS_VALID_SHIFT 31
+#define THERM_STATUS_VALID_MASK 0x01
+
struct coretemp_softc {
- struct ksensordev sc_sensordev;
- struct ksensor sc_sensor;
- device_t sc_dev;
- int sc_tjmax;
+ device_t sc_dev;
+ int sc_tjmax;
+ unsigned int sc_throttle_log;
};
/*
@@ -65,8 +73,10 @@
static int coretemp_attach(device_t dev);
static int coretemp_detach(device_t dev);
-static int coretemp_get_temp(device_t dev);
-static void coretemp_refresh(void *arg);
+static uint64_t coretemp_get_thermal_msr(int cpu);
+static void coretemp_clear_thermal_msr(int cpu);
+static int coretemp_get_val_sysctl(SYSCTL_HANDLER_ARGS);
+static int coretemp_throttle_log_sysctl(SYSCTL_HANDLER_ARGS);
static device_method_t coretemp_methods[] = {
/* Device interface */
@@ -84,8 +94,16 @@
sizeof(struct coretemp_softc),
};
+enum therm_info {
+ CORETEMP_TEMP,
+ CORETEMP_DELTA,
+ CORETEMP_RESOLUTION,
+ CORETEMP_TJMAX,
+};
+
static devclass_t coretemp_devclass;
-DRIVER_MODULE(coretemp, cpu, coretemp_driver, coretemp_devclass, NULL, NULL);
+DRIVER_MODULE(coretemp, cpu, coretemp_driver, coretemp_devclass, NULL,
+ NULL);
static void
coretemp_identify(driver_t *driver, device_t parent)
@@ -98,7 +116,7 @@
return;
/* Check that CPUID 0x06 is supported and the vendor is Intel.*/
- if (cpu_high < 6 || strcmp(cpu_vendor, "GenuineIntel"))
+ if (cpu_high < 6 || cpu_vendor_id != CPU_VENDOR_INTEL)
return;
/*
* CPUID 0x06 returns 1 if the processor has on-die thermal
@@ -134,21 +152,16 @@
struct coretemp_softc *sc = device_get_softc(dev);
device_t pdev;
uint64_t msr;
- int cpu_model;
- int cpu_mask;
+ int cpu_model, cpu_stepping;
+ int ret, tjtarget;
+ struct sysctl_oid *oid;
+ struct sysctl_ctx_list *ctx;
sc->sc_dev = dev;
pdev = device_get_parent(dev);
- cpu_model = (cpu_id >> 4) & 15;
- /* extended model */
- cpu_model += ((cpu_id >> 16) & 0xf) << 4;
- cpu_mask = cpu_id & 15;
+ cpu_model = CPUID_TO_MODEL(cpu_id);
+ cpu_stepping = cpu_id & CPUID_STEPPING;
-#if 0 /*
- * XXXrpaulo: I have this CPU model and when it returns from C3
- * coretemp continues to function properly.
- */
-
/*
* Some CPUs, namely the PIII, don't have thermal sensors, but
* report them when the CPUID check is performed in
@@ -158,6 +171,11 @@
if (cpu_model < 0xe)
return (ENXIO);
+#if 0 /*
+ * XXXrpaulo: I have this CPU model and when it returns from C3
+ * coretemp continues to function properly.
+ */
+
/*
* Check for errata AE18.
* "Processor Digital Thermal Sensor (DTS) Readout stops
@@ -165,7 +183,7 @@
*
* Adapted from the Linux coretemp driver.
*/
- if (cpu_model == 0xe && cpu_mask < 0xc) {
+ if (cpu_model == 0xe && cpu_stepping < 0xc) {
msr = rdmsr(MSR_BIOS_SIGN);
msr = msr >> 32;
if (msr < 0x39) {
@@ -175,32 +193,106 @@
}
}
#endif
+
/*
- * On some Core 2 CPUs, there's an undocumented MSR that
- * can tell us if Tj(max) is 100 or 85.
- *
- * The if-clause for CPUs having the MSR_IA32_EXT_CONFIG was adapted
- * from the Linux coretemp driver.
+ * Use 100C as the initial value.
*/
sc->sc_tjmax = 100;
- if ((cpu_model == 0xf && cpu_mask >= 2) || cpu_model == 0xe) {
+
+ if ((cpu_model == 0xf && cpu_stepping >= 2) || cpu_model == 0xe) {
+ /*
+ * On some Core 2 CPUs, there's an undocumented MSR that
+ * can tell us if Tj(max) is 100 or 85.
+ *
+ * The if-clause for CPUs having the MSR_IA32_EXT_CONFIG was adapted
+ * from the Linux coretemp driver.
+ */
msr = rdmsr(MSR_IA32_EXT_CONFIG);
if (msr & (1 << 30))
sc->sc_tjmax = 85;
+ } else if (cpu_model == 0x17) {
+ switch (cpu_stepping) {
+ case 0x6: /* Mobile Core 2 Duo */
+ sc->sc_tjmax = 105;
+ break;
+ default: /* Unknown stepping */
+ break;
+ }
+ } else if (cpu_model == 0x1c) {
+ switch (cpu_stepping) {
+ case 0xa: /* 45nm Atom D400, N400 and D500 series */
+ sc->sc_tjmax = 100;
+ break;
+ default:
+ sc->sc_tjmax = 90;
+ break;
+ }
+ } else {
+ /*
+ * Attempt to get Tj(max) from MSR IA32_TEMPERATURE_TARGET.
+ *
+ * This method is described in Intel white paper "CPU
+ * Monitoring With DTS/PECI". (#322683)
+ */
+ ret = rdmsr_safe(MSR_IA32_TEMPERATURE_TARGET, &msr);
+ if (ret == 0) {
+ tjtarget = (msr >> 16) & 0xff;
+
+ /*
+ * On earlier generation of processors, the value
+ * obtained from IA32_TEMPERATURE_TARGET register is
+ * an offset that needs to be summed with a model
+ * specific base. It is however not clear what
+ * these numbers are, with the publicly available
+ * documents from Intel.
+ *
+ * For now, we consider [70, 110]C range, as
+ * described in #322683, as "reasonable" and accept
+ * these values whenever the MSR is available for
+ * read, regardless the CPU model.
+ */
+ if (tjtarget >= 70 && tjtarget <= 110)
+ sc->sc_tjmax = tjtarget;
+ else
+ device_printf(dev, "Tj(target) value %d "
+ "does not seem right.\n", tjtarget);
+ } else
+ device_printf(dev, "Can not get Tj(target) "
+ "from your CPU, using 100C.\n");
}
+ if (bootverbose)
+ device_printf(dev, "Setting TjMax=%d\n", sc->sc_tjmax);
+
+ ctx = device_get_sysctl_ctx(dev);
+
+ oid = SYSCTL_ADD_NODE(ctx,
+ SYSCTL_CHILDREN(device_get_sysctl_tree(pdev)), OID_AUTO,
+ "coretemp", CTLFLAG_RD, NULL, "Per-CPU thermal information");
+
/*
- * Add hw.sensors.cpuN.temp0 MIB.
+ * Add the MIBs to dev.cpu.N and dev.cpu.N.coretemp.
*/
- strlcpy(sc->sc_sensordev.xname, device_get_nameunit(pdev),
- sizeof(sc->sc_sensordev.xname));
- sc->sc_sensor.type = SENSOR_TEMP;
- sensor_attach(&sc->sc_sensordev, &sc->sc_sensor);
- if (sensor_task_register(sc, coretemp_refresh, 2)) {
- device_printf(dev, "unable to register update task\n");
- return (ENXIO);
- }
- sensordev_install(&sc->sc_sensordev);
+ SYSCTL_ADD_PROC(ctx, SYSCTL_CHILDREN(device_get_sysctl_tree(pdev)),
+ OID_AUTO, "temperature", CTLTYPE_INT | CTLFLAG_RD | CTLFLAG_MPSAFE,
+ dev, CORETEMP_TEMP, coretemp_get_val_sysctl, "IK",
+ "Current temperature");
+ SYSCTL_ADD_PROC(ctx, SYSCTL_CHILDREN(oid), OID_AUTO, "delta",
+ CTLTYPE_INT | CTLFLAG_RD | CTLFLAG_MPSAFE, dev, CORETEMP_DELTA,
+ coretemp_get_val_sysctl, "I",
+ "Delta between TCC activation and current temperature");
+ SYSCTL_ADD_PROC(ctx, SYSCTL_CHILDREN(oid), OID_AUTO, "resolution",
+ CTLTYPE_INT | CTLFLAG_RD | CTLFLAG_MPSAFE, dev, CORETEMP_RESOLUTION,
+ coretemp_get_val_sysctl, "I",
+ "Resolution of CPU thermal sensor");
+ SYSCTL_ADD_PROC(ctx, SYSCTL_CHILDREN(oid), OID_AUTO, "tjmax",
+ CTLTYPE_INT | CTLFLAG_RD | CTLFLAG_MPSAFE, dev, CORETEMP_TJMAX,
+ coretemp_get_val_sysctl, "IK",
+ "TCC activation temperature");
+ SYSCTL_ADD_PROC(ctx, SYSCTL_CHILDREN(oid), OID_AUTO,
+ "throttle_log", CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_MPSAFE, dev, 0,
+ coretemp_throttle_log_sysctl, "I",
+ "Set to 1 if the thermal sensor has tripped");
return (0);
}
@@ -208,93 +300,147 @@
static int
coretemp_detach(device_t dev)
{
- struct coretemp_softc *sc = device_get_softc(dev);
+ return (0);
+}
- sensordev_deinstall(&sc->sc_sensordev);
- sensor_task_unregister(sc);
+static uint64_t
+coretemp_get_thermal_msr(int cpu)
+{
+ uint64_t msr;
- return (0);
+ thread_lock(curthread);
+ sched_bind(curthread, cpu);
+ thread_unlock(curthread);
+
+ /*
+ * The digital temperature reading is located at bit 16
+ * of MSR_THERM_STATUS.
+ *
+ * There is a bit on that MSR that indicates whether the
+ * temperature is valid or not.
+ *
+ * The temperature is computed by subtracting the temperature
+ * reading by Tj(max).
+ */
+ msr = rdmsr(MSR_THERM_STATUS);
+
+ thread_lock(curthread);
+ sched_unbind(curthread);
+ thread_unlock(curthread);
+
+ return (msr);
}
+static void
+coretemp_clear_thermal_msr(int cpu)
+{
+ thread_lock(curthread);
+ sched_bind(curthread, cpu);
+ thread_unlock(curthread);
+ wrmsr(MSR_THERM_STATUS, 0);
+
+ thread_lock(curthread);
+ sched_unbind(curthread);
+ thread_unlock(curthread);
+}
+
static int
-coretemp_get_temp(device_t dev)
+coretemp_get_val_sysctl(SYSCTL_HANDLER_ARGS)
{
+ device_t dev;
uint64_t msr;
- int temp;
- int cpu = device_get_unit(dev);
- struct coretemp_softc *sc = device_get_softc(dev);
+ int val, tmp;
+ struct coretemp_softc *sc;
+ enum therm_info type;
char stemp[16];
- /*
- * Bind to specific CPU to read the correct temperature.
- * If not all CPUs are initialised, then only read from
- * cpu0, returning -1 on all other CPUs.
- */
- if (smp_cpus > 1) {
- thread_lock(curthread);
- sched_bind(curthread, cpu);
- msr = rdmsr(MSR_THERM_STATUS);
- sched_unbind(curthread);
- thread_unlock(curthread);
- } else if (cpu != 0)
- return (-1);
- else
- msr = rdmsr(MSR_THERM_STATUS);
+ dev = (device_t) arg1;
+ msr = coretemp_get_thermal_msr(device_get_unit(dev));
+ sc = device_get_softc(dev);
+ type = arg2;
- /*
- * Check for Thermal Status and Thermal Status Log.
- */
- if ((msr & 0x3) == 0x3)
- device_printf(dev, "PROCHOT asserted\n");
+ if (((msr >> THERM_STATUS_VALID_SHIFT) & THERM_STATUS_VALID_MASK) != 1) {
+ val = -1;
+ } else {
+ switch (type) {
+ case CORETEMP_TEMP:
+ tmp = (msr >> THERM_STATUS_TEMP_SHIFT) &
+ THERM_STATUS_TEMP_MASK;
+ val = (sc->sc_tjmax - tmp) * 10 + TZ_ZEROC;
+ break;
+ case CORETEMP_DELTA:
+ val = (msr >> THERM_STATUS_TEMP_SHIFT) &
+ THERM_STATUS_TEMP_MASK;
+ break;
+ case CORETEMP_RESOLUTION:
+ val = (msr >> THERM_STATUS_RES_SHIFT) &
+ THERM_STATUS_RES_MASK;
+ break;
+ case CORETEMP_TJMAX:
+ val = sc->sc_tjmax * 10 + TZ_ZEROC;
+ break;
+ }
+ }
- /*
- * Bit 31 contains "Reading valid"
- */
- if (((msr >> 31) & 0x1) == 1) {
+ if (msr & THERM_STATUS_LOG) {
+ coretemp_clear_thermal_msr(device_get_unit(dev));
+ sc->sc_throttle_log = 1;
+
/*
- * Starting on bit 16 and ending on bit 22.
+ * Check for Critical Temperature Status and Critical
+ * Temperature Log. It doesn't really matter if the
+ * current temperature is invalid because the "Critical
+ * Temperature Log" bit will tell us if the Critical
+ * Temperature has * been reached in past. It's not
+ * directly related to the current temperature.
+ *
+ * If we reach a critical level, allow devctl(4)
+ * to catch this and shutdown the system.
*/
- temp = sc->sc_tjmax - ((msr >> 16) & 0x7f);
- } else
- temp = -1;
-
- /*
- * Check for Critical Temperature Status and Critical
- * Temperature Log.
- * It doesn't really matter if the current temperature is
- * invalid because the "Critical Temperature Log" bit will
- * tell us if the Critical Temperature has been reached in
- * past. It's not directly related to the current temperature.
- *
- * If we reach a critical level, allow devctl(4) to catch this
- * and shutdown the system.
- */
- if (((msr >> 4) & 0x3) == 0x3) {
- device_printf(dev, "critical temperature detected, "
- "suggest system shutdown\n");
- snprintf(stemp, sizeof(stemp), "%d", temp);
- devctl_notify("coretemp", "Thermal", stemp, "notify=0xcc");
+ if (msr & THERM_STATUS) {
+ tmp = (msr >> THERM_STATUS_TEMP_SHIFT) &
+ THERM_STATUS_TEMP_MASK;
+ tmp = (sc->sc_tjmax - tmp) * 10 + TZ_ZEROC;
+ device_printf(dev, "critical temperature detected, "
+ "suggest system shutdown\n");
+ snprintf(stemp, sizeof(stemp), "%d", tmp);
+ devctl_notify("coretemp", "Thermal", stemp,
+ "notify=0xcc");
+ }
}
- return (temp);
+ return (sysctl_handle_int(oidp, &val, 0, req));
}
-static void
-coretemp_refresh(void *arg)
+static int
+coretemp_throttle_log_sysctl(SYSCTL_HANDLER_ARGS)
{
- struct coretemp_softc *sc = arg;
- device_t dev = sc->sc_dev;
- struct ksensor *s = &sc->sc_sensor;
- int temp;
+ device_t dev;
+ uint64_t msr;
+ int error, val;
+ struct coretemp_softc *sc;
- temp = coretemp_get_temp(dev);
+ dev = (device_t) arg1;
+ msr = coretemp_get_thermal_msr(device_get_unit(dev));
+ sc = device_get_softc(dev);
- if (temp == -1) {
- s->flags |= SENSOR_FINVALID;
- s->value = 0;
- } else {
- s->flags &= ~SENSOR_FINVALID;
- s->value = temp * 1000000 + 273150000;
+ if (msr & THERM_STATUS_LOG) {
+ coretemp_clear_thermal_msr(device_get_unit(dev));
+ sc->sc_throttle_log = 1;
}
+
+ val = sc->sc_throttle_log;
+
+ error = sysctl_handle_int(oidp, &val, 0, req);
+
+ if (error || !req->newptr)
+ return (error);
+ else if (val != 0)
+ return (EINVAL);
+
+ coretemp_clear_thermal_msr(device_get_unit(dev));
+ sc->sc_throttle_log = 0;
+
+ return (0);
}
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