[Midnightbsd-cvs] src [8454] trunk/sys/dev/bge: rework controller reset feature
laffer1 at midnightbsd.org
laffer1 at midnightbsd.org
Sun Sep 18 17:55:10 EDT 2016
Revision: 8454
http://svnweb.midnightbsd.org/src/?rev=8454
Author: laffer1
Date: 2016-09-18 17:55:10 -0400 (Sun, 18 Sep 2016)
Log Message:
-----------
rework controller reset feature
Modified Paths:
--------------
trunk/sys/dev/bge/if_bge.c
trunk/sys/dev/bge/if_bgereg.h
Modified: trunk/sys/dev/bge/if_bge.c
===================================================================
--- trunk/sys/dev/bge/if_bge.c 2016-09-18 21:54:55 UTC (rev 8453)
+++ trunk/sys/dev/bge/if_bge.c 2016-09-18 21:55:10 UTC (rev 8454)
@@ -1433,10 +1433,6 @@
misc_ctl |= BGE_PCIMISCCTL_TAGGED_STATUS;
pci_write_config(sc->bge_dev, BGE_PCI_MISC_CTL, misc_ctl, 4);
- /* Clear the MAC control register */
- CSR_WRITE_4(sc, BGE_MAC_MODE, 0);
- DELAY(40);
-
/*
* Clear the MAC statistics block in the NIC's
* internal memory.
@@ -3585,7 +3581,7 @@
bge_reset(struct bge_softc *sc)
{
device_t dev;
- uint32_t cachesize, command, pcistate, reset, val;
+ uint32_t cachesize, command, mac_mode, mac_mode_mask, reset, val;
void (*write_op)(struct bge_softc *, int, int);
uint16_t devctl;
int i;
@@ -3592,6 +3588,9 @@
dev = sc->bge_dev;
+ mac_mode_mask = BGE_MACMODE_HALF_DUPLEX | BGE_MACMODE_PORTMODE;
+ mac_mode = CSR_READ_4(sc, BGE_MAC_MODE) & mac_mode_mask;
+
if (BGE_IS_575X_PLUS(sc) && !BGE_IS_5714_FAMILY(sc) &&
(sc->bge_asicrev != BGE_ASICREV_BCM5906)) {
if (sc->bge_flags & BGE_FLAG_PCIE)
@@ -3604,7 +3603,6 @@
/* Save some important PCI state. */
cachesize = pci_read_config(dev, BGE_PCI_CACHESZ, 4);
command = pci_read_config(dev, BGE_PCI_CMD, 4);
- pcistate = pci_read_config(dev, BGE_PCI_PCISTATE, 4);
pci_write_config(dev, BGE_PCI_MISC_CTL,
BGE_PCIMISCCTL_INDIRECT_ACCESS | BGE_PCIMISCCTL_MASK_PCI_INTR |
@@ -3661,7 +3659,10 @@
/* Issue global reset */
write_op(sc, BGE_MISC_CFG, reset);
- DELAY(1000);
+ if (sc->bge_flags & BGE_FLAG_PCIE)
+ DELAY(100 * 1000);
+ else
+ DELAY(1000);
/* XXX: Broadcom Linux driver. */
if (sc->bge_flags & BGE_FLAG_PCIE) {
@@ -3689,9 +3690,13 @@
pci_write_config(dev, BGE_PCI_MISC_CTL,
BGE_PCIMISCCTL_INDIRECT_ACCESS | BGE_PCIMISCCTL_MASK_PCI_INTR |
BGE_HIF_SWAP_OPTIONS | BGE_PCIMISCCTL_PCISTATE_RW, 4);
+ val = BGE_PCISTATE_ROM_ENABLE | BGE_PCISTATE_ROM_RETRY_ENABLE;
+ if (sc->bge_chipid == BGE_CHIPID_BCM5704_A0 &&
+ (sc->bge_flags & BGE_FLAG_PCIX) != 0)
+ val |= BGE_PCISTATE_RETRY_SAME_DMA;
+ pci_write_config(dev, BGE_PCI_PCISTATE, val, 4);
pci_write_config(dev, BGE_PCI_CACHESZ, cachesize, 4);
pci_write_config(dev, BGE_PCI_CMD, command, 4);
- write_op(sc, BGE_MISC_CFG, BGE_32BITTIME_66MHZ);
/*
* Disable PCI-X relaxed ordering to ensure status block update
* comes first then packet buffer DMA. Otherwise driver may
@@ -3730,6 +3735,14 @@
} else
CSR_WRITE_4(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE);
+ /* Fix up byte swapping. */
+ CSR_WRITE_4(sc, BGE_MODE_CTL, bge_dma_swap_options(sc));
+
+ val = CSR_READ_4(sc, BGE_MAC_MODE);
+ val = (val & ~mac_mode_mask) | mac_mode;
+ CSR_WRITE_4(sc, BGE_MAC_MODE, val);
+ DELAY(40);
+
if (sc->bge_asicrev == BGE_ASICREV_BCM5906) {
for (i = 0; i < BGE_TIMEOUT; i++) {
val = CSR_READ_4(sc, BGE_VCPU_STATUS);
@@ -3765,30 +3778,6 @@
}
/*
- * XXX Wait for the value of the PCISTATE register to
- * return to its original pre-reset state. This is a
- * fairly good indicator of reset completion. If we don't
- * wait for the reset to fully complete, trying to read
- * from the device's non-PCI registers may yield garbage
- * results.
- */
- for (i = 0; i < BGE_TIMEOUT; i++) {
- if (pci_read_config(dev, BGE_PCI_PCISTATE, 4) == pcistate)
- break;
- DELAY(10);
- }
-
- /* Fix up byte swapping. */
- CSR_WRITE_4(sc, BGE_MODE_CTL, bge_dma_swap_options(sc));
-
- /* Tell the ASF firmware we are up */
- if (sc->bge_asf_mode & ASF_STACKUP)
- BGE_SETBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP);
-
- CSR_WRITE_4(sc, BGE_MAC_MODE, 0);
- DELAY(40);
-
- /*
* The 5704 in TBI mode apparently needs some special
* adjustment to insure the SERDES drive level is set
* to 1.2V.
Modified: trunk/sys/dev/bge/if_bgereg.h
===================================================================
--- trunk/sys/dev/bge/if_bgereg.h 2016-09-18 21:54:55 UTC (rev 8453)
+++ trunk/sys/dev/bge/if_bgereg.h 2016-09-18 21:55:10 UTC (rev 8454)
@@ -430,10 +430,11 @@
#define BGE_PCISTATE_PCI_BUSMODE 0x00000004 /* 1 = PCI, 0 = PCI-X */
#define BGE_PCISTATE_PCI_BUSSPEED 0x00000008 /* 1 = 66/133, 0 = 33/66 */
#define BGE_PCISTATE_32BIT_BUS 0x00000010 /* 1 = 32bit, 0 = 64bit */
-#define BGE_PCISTATE_WANT_EXPROM 0x00000020
-#define BGE_PCISTATE_EXPROM_RETRY 0x00000040
+#define BGE_PCISTATE_ROM_ENABLE 0x00000020
+#define BGE_PCISTATE_ROM_RETRY_ENABLE 0x00000040
#define BGE_PCISTATE_FLATVIEW_MODE 0x00000100
#define BGE_PCISTATE_PCI_TGT_RETRY_MAX 0x00000E00
+#define BGE_PCISTATE_RETRY_SAME_DMA 0x00002000
/*
* PCI Clock Control register -- note, this register is read only
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