[Midnightbsd-cvs] src [8956] trunk/sys/dev/usb/controller: revert usb changes to allow USB to work on intel controllers again.

[laffer1 at midnightbsd.org]

Revision: 8956
          http://svnweb.midnightbsd.org/src/?rev=8956
Author:   laffer1
Date:     2016-09-27 12:26:07 -0400 (Tue, 27 Sep 2016)
Log Message:
-----------
revert usb changes to allow USB to work on intel controllers again.

Modified Paths:
--------------
    trunk/sys/dev/usb/controller/ehci_pci.c
    trunk/sys/dev/usb/controller/xhci.h
    trunk/sys/dev/usb/controller/xhcireg.h

Modified: trunk/sys/dev/usb/controller/ehci_pci.c
===================================================================
--- trunk/sys/dev/usb/controller/ehci_pci.c	2016-09-27 16:24:33 UTC (rev 8955)
+++ trunk/sys/dev/usb/controller/ehci_pci.c	2016-09-27 16:26:07 UTC (rev 8956)
@@ -29,7 +29,7 @@
  */
 
 #include <sys/cdefs.h>
-__FBSDID("$FreeBSD: stable/9/sys/dev/usb/controller/ehci_pci.c 278279 2015-02-05 20:15:42Z hselasky $");
+__MBSDID("$MidnightBSD$");
 
 /*
  * USB Enhanced Host Controller Driver, a.k.a. USB 2.0 controller.
@@ -120,16 +120,10 @@
 	case 0x43961002:
 		return ("AMD SB7x0/SB8x0/SB9x0 USB 2.0 controller");
 
-	case 0x1d268086:
-		return ("Intel Patsburg USB 2.0 controller");
-	case 0x1d2d8086:
-		return ("Intel Patsburg USB 2.0 controller");
 	case 0x1e268086:
 		return ("Intel Panther Point USB 2.0 controller");
 	case 0x1e2d8086:
 		return ("Intel Panther Point USB 2.0 controller");
-	case 0x1f2c8086:
-		return ("Intel Avoton USB 2.0 controller");
 	case 0x25ad8086:
 		return "Intel 6300ESB USB 2.0 controller";
 	case 0x24cd8086:
@@ -158,14 +152,6 @@
 		return ("Intel PCH USB 2.0 controller USB-A");
 	case 0x3b3c8086:
 		return ("Intel PCH USB 2.0 controller USB-B");
-	case 0x8c268086:
-		return ("Intel Lynx Point USB 2.0 controller USB-A");
-	case 0x8c2d8086:
-		return ("Intel Lynx Point USB 2.0 controller USB-B");
-	case 0x8ca68086:
-		return ("Intel Wildcat Point USB 2.0 controller USB-A");
-	case 0x8cad8086:
-		return ("Intel Wildcat Point USB 2.0 controller USB-B");
 
 	case 0x00e01033:
 		return ("NEC uPD 720100 USB 2.0 controller");
@@ -179,7 +165,7 @@
 	case 0x00e810de:
 		return "NVIDIA nForce3 250 USB 2.0 controller";
 	case 0x005b10de:
-		return "NVIDIA nForce CK804 USB 2.0 controller";
+		return "NVIDIA nForce4 USB 2.0 controller";
 	case 0x036d10de:
 		return "NVIDIA nForce MCP55 USB 2.0 controller";
 	case 0x03f210de:

Modified: trunk/sys/dev/usb/controller/xhci.h
===================================================================
--- trunk/sys/dev/usb/controller/xhci.h	2016-09-27 16:24:33 UTC (rev 8955)
+++ trunk/sys/dev/usb/controller/xhci.h	2016-09-27 16:26:07 UTC (rev 8956)
@@ -30,7 +30,7 @@
 
 #define	XHCI_MAX_DEVICES	MIN(USB_MAX_DEVICES, 128)
 #define	XHCI_MAX_ENDPOINTS	32	/* hardcoded - do not change */
-#define	XHCI_MAX_SCRATCHPADS	256
+#define	XHCI_MAX_SCRATCHPADS	32
 #define	XHCI_MAX_EVENTS		(16 * 13)
 #define	XHCI_MAX_COMMANDS	(16 * 1)
 #define	XHCI_MAX_RSEG		1

Modified: trunk/sys/dev/usb/controller/xhcireg.h
===================================================================
--- trunk/sys/dev/usb/controller/xhcireg.h	2016-09-27 16:24:33 UTC (rev 8955)
+++ trunk/sys/dev/usb/controller/xhcireg.h	2016-09-27 16:26:07 UTC (rev 8956)
@@ -35,9 +35,7 @@
 #define	PCI_XHCI_FLADJ		0x61	/* RW frame length adjust */
 
 #define	PCI_XHCI_INTEL_XUSB2PR	0xD0	/* Intel USB2 Port Routing */
-#define	PCI_XHCI_INTEL_USB2PRM	0xD4	/* Intel USB2 Port Routing Mask */
 #define	PCI_XHCI_INTEL_USB3_PSSEN 0xD8	/* Intel USB3 Port SuperSpeed Enable */
-#define	PCI_XHCI_INTEL_USB3PRM	0xDC	/* Intel USB3 Port Routing Mask */
 
 /* XHCI capability registers */
 #define	XHCI_CAPLENGTH		0x00	/* RO capability */
@@ -52,8 +50,8 @@
 #define	XHCI_HCSPARAMS2		0x08	/* RO structual parameters 2 */
 #define	XHCI_HCS2_IST(x)	((x) & 0xF)
 #define	XHCI_HCS2_ERST_MAX(x)	(((x) >> 4) & 0xF)
-#define	XHCI_HCS2_SPR(x)	(((x) >> 26) & 0x1)
-#define	XHCI_HCS2_SPB_MAX(x)	((((x) >> 16) & 0x3E0) | (((x) >> 27) & 0x1F))
+#define	XHCI_HCS2_SPR(x)	(((x) >> 24) & 0x1)
+#define	XHCI_HCS2_SPB_MAX(x)	(((x) >> 27) & 0x7F)
 #define	XHCI_HCSPARAMS3		0x0C	/* RO structual parameters 3 */
 #define	XHCI_HCS3_U1_DEL(x)	((x) & 0xFF)
 #define	XHCI_HCS3_U2_DEL(x)	(((x) >> 16) & 0xFFFF)
@@ -168,8 +166,7 @@
 #define	XHCI_IMOD_IVAL_SET(x)	(((x) & 0xFFFF) << 0)	/* 250ns unit */
 #define	XHCI_IMOD_ICNT_GET(x)	(((x) >> 16) & 0xFFFF)	/* 250ns unit */
 #define	XHCI_IMOD_ICNT_SET(x)	(((x) & 0xFFFF) << 16)	/* 250ns unit */
-#define	XHCI_IMOD_DEFAULT	0x000001F4U	/* 8000 IRQs/second */
-#define	XHCI_IMOD_DEFAULT_LP 	0x000003F8U	/* 4000 IRQs/second - LynxPoint */
+#define	XHCI_IMOD_DEFAULT	0x000003E8U	/* 8000 IRQ/second */
 #define	XHCI_ERSTSZ(n)		(0x0028 + (0x20 * (n)))	/* XHCI event ring segment table size */
 #define	XHCI_ERSTS_GET(x)	((x) & 0xFFFF)
 #define	XHCI_ERSTS_SET(x)	((x) & 0xFFFF)