[Midnightbsd-cvs] src [9987] trunk/sys/mips: mips support
laffer1 at midnightbsd.org
laffer1 at midnightbsd.org
Sat May 26 17:55:03 EDT 2018
Revision: 9987
http://svnweb.midnightbsd.org/src/?rev=9987
Author: laffer1
Date: 2018-05-26 17:55:02 -0400 (Sat, 26 May 2018)
Log Message:
-----------
mips support
Added Paths:
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trunk/sys/mips/
trunk/sys/mips/adm5120/
trunk/sys/mips/adm5120/adm5120_machdep.c
trunk/sys/mips/adm5120/adm5120reg.h
trunk/sys/mips/adm5120/admpci.c
trunk/sys/mips/adm5120/console.c
trunk/sys/mips/adm5120/files.adm5120
trunk/sys/mips/adm5120/if_admsw.c
trunk/sys/mips/adm5120/if_admswreg.h
trunk/sys/mips/adm5120/if_admswvar.h
trunk/sys/mips/adm5120/obio.c
trunk/sys/mips/adm5120/obiovar.h
trunk/sys/mips/adm5120/std.adm5120
trunk/sys/mips/adm5120/uart_bus_adm5120.c
trunk/sys/mips/adm5120/uart_cpu_adm5120.c
trunk/sys/mips/adm5120/uart_dev_adm5120.c
trunk/sys/mips/adm5120/uart_dev_adm5120.h
trunk/sys/mips/alchemy/
trunk/sys/mips/alchemy/alchemy_machdep.c
trunk/sys/mips/alchemy/aureg.h
trunk/sys/mips/alchemy/files.alchemy
trunk/sys/mips/alchemy/obio.c
trunk/sys/mips/alchemy/std.alchemy
trunk/sys/mips/alchemy/uart_bus_alchemy.c
trunk/sys/mips/alchemy/uart_cpu_alchemy.c
trunk/sys/mips/atheros/
trunk/sys/mips/atheros/apb.c
trunk/sys/mips/atheros/apbvar.h
trunk/sys/mips/atheros/ar71xx_bus_space_reversed.c
trunk/sys/mips/atheros/ar71xx_bus_space_reversed.h
trunk/sys/mips/atheros/ar71xx_chip.c
trunk/sys/mips/atheros/ar71xx_chip.h
trunk/sys/mips/atheros/ar71xx_cpudef.h
trunk/sys/mips/atheros/ar71xx_ehci.c
trunk/sys/mips/atheros/ar71xx_fixup.c
trunk/sys/mips/atheros/ar71xx_fixup.h
trunk/sys/mips/atheros/ar71xx_gpio.c
trunk/sys/mips/atheros/ar71xx_gpiovar.h
trunk/sys/mips/atheros/ar71xx_machdep.c
trunk/sys/mips/atheros/ar71xx_ohci.c
trunk/sys/mips/atheros/ar71xx_pci.c
trunk/sys/mips/atheros/ar71xx_pci_bus_space.c
trunk/sys/mips/atheros/ar71xx_pci_bus_space.h
trunk/sys/mips/atheros/ar71xx_setup.c
trunk/sys/mips/atheros/ar71xx_setup.h
trunk/sys/mips/atheros/ar71xx_spi.c
trunk/sys/mips/atheros/ar71xx_wdog.c
trunk/sys/mips/atheros/ar71xxreg.h
trunk/sys/mips/atheros/ar724x_chip.c
trunk/sys/mips/atheros/ar724x_chip.h
trunk/sys/mips/atheros/ar724x_pci.c
trunk/sys/mips/atheros/ar724xreg.h
trunk/sys/mips/atheros/ar91xx_chip.c
trunk/sys/mips/atheros/ar91xx_chip.h
trunk/sys/mips/atheros/ar91xxreg.h
trunk/sys/mips/atheros/ar933x_chip.c
trunk/sys/mips/atheros/ar933x_chip.h
trunk/sys/mips/atheros/ar933x_uart.h
trunk/sys/mips/atheros/ar933xreg.h
trunk/sys/mips/atheros/ar934x_chip.c
trunk/sys/mips/atheros/ar934x_chip.h
trunk/sys/mips/atheros/ar934xreg.h
trunk/sys/mips/atheros/files.ar71xx
trunk/sys/mips/atheros/if_arge.c
trunk/sys/mips/atheros/if_argevar.h
trunk/sys/mips/atheros/pcf2123_rtc.c
trunk/sys/mips/atheros/pcf2123reg.h
trunk/sys/mips/atheros/std.ar71xx
trunk/sys/mips/atheros/uart_bus_ar71xx.c
trunk/sys/mips/atheros/uart_bus_ar933x.c
trunk/sys/mips/atheros/uart_cpu_ar71xx.c
trunk/sys/mips/atheros/uart_cpu_ar933x.c
trunk/sys/mips/atheros/uart_dev_ar933x.c
trunk/sys/mips/atheros/uart_dev_ar933x.h
trunk/sys/mips/beri/
trunk/sys/mips/beri/beri_machdep.c
trunk/sys/mips/beri/beri_pic.c
trunk/sys/mips/beri/beri_simplebus.c
trunk/sys/mips/beri/fdt_ic_if.m
trunk/sys/mips/beri/files.beri
trunk/sys/mips/beri/std.beri
trunk/sys/mips/cavium/
trunk/sys/mips/cavium/asm_octeon.S
trunk/sys/mips/cavium/ciu.c
trunk/sys/mips/cavium/cryptocteon/
trunk/sys/mips/cavium/cryptocteon/cavium_crypto.c
trunk/sys/mips/cavium/cryptocteon/cryptocteon.c
trunk/sys/mips/cavium/cryptocteon/cryptocteonvar.h
trunk/sys/mips/cavium/cvmx_config.h
trunk/sys/mips/cavium/files.octeon1
trunk/sys/mips/cavium/if_octm.c
trunk/sys/mips/cavium/obio.c
trunk/sys/mips/cavium/obiovar.h
trunk/sys/mips/cavium/octe/
trunk/sys/mips/cavium/octe/cavium-ethernet.h
trunk/sys/mips/cavium/octe/ethernet-common.c
trunk/sys/mips/cavium/octe/ethernet-common.h
trunk/sys/mips/cavium/octe/ethernet-defines.h
trunk/sys/mips/cavium/octe/ethernet-headers.h
trunk/sys/mips/cavium/octe/ethernet-mdio.c
trunk/sys/mips/cavium/octe/ethernet-mdio.h
trunk/sys/mips/cavium/octe/ethernet-mem.c
trunk/sys/mips/cavium/octe/ethernet-mem.h
trunk/sys/mips/cavium/octe/ethernet-mv88e61xx.c
trunk/sys/mips/cavium/octe/ethernet-mv88e61xx.h
trunk/sys/mips/cavium/octe/ethernet-rgmii.c
trunk/sys/mips/cavium/octe/ethernet-rx.c
trunk/sys/mips/cavium/octe/ethernet-rx.h
trunk/sys/mips/cavium/octe/ethernet-sgmii.c
trunk/sys/mips/cavium/octe/ethernet-spi.c
trunk/sys/mips/cavium/octe/ethernet-tx.c
trunk/sys/mips/cavium/octe/ethernet-tx.h
trunk/sys/mips/cavium/octe/ethernet-util.h
trunk/sys/mips/cavium/octe/ethernet-xaui.c
trunk/sys/mips/cavium/octe/ethernet.c
trunk/sys/mips/cavium/octe/mv88e61xxphy.c
trunk/sys/mips/cavium/octe/mv88e61xxphyreg.h
trunk/sys/mips/cavium/octe/octe.c
trunk/sys/mips/cavium/octe/octebus.c
trunk/sys/mips/cavium/octe/octebusvar.h
trunk/sys/mips/cavium/octe/wrapper-cvmx-includes.h
trunk/sys/mips/cavium/octeon_cop2.S
trunk/sys/mips/cavium/octeon_cop2.h
trunk/sys/mips/cavium/octeon_ds1337.c
trunk/sys/mips/cavium/octeon_ebt3000_cf.c
trunk/sys/mips/cavium/octeon_gpio.c
trunk/sys/mips/cavium/octeon_gpiovar.h
trunk/sys/mips/cavium/octeon_irq.h
trunk/sys/mips/cavium/octeon_machdep.c
trunk/sys/mips/cavium/octeon_mp.c
trunk/sys/mips/cavium/octeon_nmi.S
trunk/sys/mips/cavium/octeon_pci_console.c
trunk/sys/mips/cavium/octeon_pcmap_regs.h
trunk/sys/mips/cavium/octeon_pmc.c
trunk/sys/mips/cavium/octeon_rnd.c
trunk/sys/mips/cavium/octeon_rtc.c
trunk/sys/mips/cavium/octeon_wdog.c
trunk/sys/mips/cavium/octopci.c
trunk/sys/mips/cavium/octopci_bus_space.c
trunk/sys/mips/cavium/octopcireg.h
trunk/sys/mips/cavium/octopcivar.h
trunk/sys/mips/cavium/std.octeon1
trunk/sys/mips/cavium/uart_bus_octeonusart.c
trunk/sys/mips/cavium/uart_cpu_octeonusart.c
trunk/sys/mips/cavium/uart_dev_oct16550.c
trunk/sys/mips/cavium/usb/
trunk/sys/mips/cavium/usb/octusb.c
trunk/sys/mips/cavium/usb/octusb.h
trunk/sys/mips/cavium/usb/octusb_octeon.c
trunk/sys/mips/compile/
trunk/sys/mips/conf/
trunk/sys/mips/conf/ADM5120
trunk/sys/mips/conf/ADM5120.hints
trunk/sys/mips/conf/ALCHEMY
trunk/sys/mips/conf/AP121
trunk/sys/mips/conf/AP121.hints
trunk/sys/mips/conf/AP91
trunk/sys/mips/conf/AP91.hints
trunk/sys/mips/conf/AP93
trunk/sys/mips/conf/AP93.hints
trunk/sys/mips/conf/AP94
trunk/sys/mips/conf/AP94.hints
trunk/sys/mips/conf/AP96
trunk/sys/mips/conf/AP96.hints
trunk/sys/mips/conf/AR71XX_BASE
trunk/sys/mips/conf/AR71XX_BASE.hints
trunk/sys/mips/conf/AR724X_BASE
trunk/sys/mips/conf/AR724X_BASE.hints
trunk/sys/mips/conf/AR91XX_BASE
trunk/sys/mips/conf/AR91XX_BASE.hints
trunk/sys/mips/conf/AR933X_BASE
trunk/sys/mips/conf/AR933X_BASE.hints
trunk/sys/mips/conf/AR934X_BASE
trunk/sys/mips/conf/AR934X_BASE.hints
trunk/sys/mips/conf/BERI_DE4.hints
trunk/sys/mips/conf/BERI_DE4_BASE
trunk/sys/mips/conf/BERI_DE4_MDROOT
trunk/sys/mips/conf/BERI_DE4_SDROOT
trunk/sys/mips/conf/BERI_NETFPGA_MDROOT
trunk/sys/mips/conf/BERI_SIM_BASE
trunk/sys/mips/conf/BERI_SIM_MDROOT
trunk/sys/mips/conf/BERI_SIM_SDROOT
trunk/sys/mips/conf/BERI_TEMPLATE
trunk/sys/mips/conf/BERI_TPAD.hints
trunk/sys/mips/conf/CARAMBOLA2
trunk/sys/mips/conf/CARAMBOLA2.hints
trunk/sys/mips/conf/DB120
trunk/sys/mips/conf/DB120.hints
trunk/sys/mips/conf/DEFAULTS
trunk/sys/mips/conf/DIR-825
trunk/sys/mips/conf/DIR-825.hints
trunk/sys/mips/conf/ENH200
trunk/sys/mips/conf/ENH200.hints
trunk/sys/mips/conf/GXEMUL
trunk/sys/mips/conf/GXEMUL.hints
trunk/sys/mips/conf/GXEMUL32
trunk/sys/mips/conf/IDT
trunk/sys/mips/conf/IDT.hints
trunk/sys/mips/conf/MALTA
trunk/sys/mips/conf/MALTA.hints
trunk/sys/mips/conf/MALTA64
trunk/sys/mips/conf/OCTEON1
trunk/sys/mips/conf/OCTEON1.hints
trunk/sys/mips/conf/PB47
trunk/sys/mips/conf/PB47.hints
trunk/sys/mips/conf/PB92
trunk/sys/mips/conf/PB92.hints
trunk/sys/mips/conf/PICOSTATION_M2HP
trunk/sys/mips/conf/PICOSTATION_M2HP.hints
trunk/sys/mips/conf/QEMU
trunk/sys/mips/conf/ROUTERSTATION
trunk/sys/mips/conf/ROUTERSTATION.hints
trunk/sys/mips/conf/ROUTERSTATION_MFS
trunk/sys/mips/conf/RSPRO
trunk/sys/mips/conf/RSPRO.hints
trunk/sys/mips/conf/RSPRO_MFS
trunk/sys/mips/conf/RSPRO_STANDALONE
trunk/sys/mips/conf/RT305X
trunk/sys/mips/conf/RT305X.hints
trunk/sys/mips/conf/SENTRY5
trunk/sys/mips/conf/SENTRY5.hints
trunk/sys/mips/conf/SWARM
trunk/sys/mips/conf/SWARM.hints
trunk/sys/mips/conf/SWARM64
trunk/sys/mips/conf/SWARM64_SMP
trunk/sys/mips/conf/SWARM_SMP
trunk/sys/mips/conf/TP-WN1043ND
trunk/sys/mips/conf/TP-WN1043ND.hints
trunk/sys/mips/conf/WZR-300HP
trunk/sys/mips/conf/WZR-300HP.hints
trunk/sys/mips/conf/XLP
trunk/sys/mips/conf/XLP.hints
trunk/sys/mips/conf/XLP64
trunk/sys/mips/conf/XLPN32
trunk/sys/mips/conf/XLR
trunk/sys/mips/conf/XLR64
trunk/sys/mips/conf/XLRN32
trunk/sys/mips/conf/std.SWARM
trunk/sys/mips/conf/std.XLP
trunk/sys/mips/gxemul/
trunk/sys/mips/gxemul/files.gxemul
trunk/sys/mips/gxemul/gxemul_machdep.c
trunk/sys/mips/gxemul/mpreg.h
trunk/sys/mips/gxemul/std.gxemul
trunk/sys/mips/idt/
trunk/sys/mips/idt/files.idt
trunk/sys/mips/idt/idt_machdep.c
trunk/sys/mips/idt/idtpci.c
trunk/sys/mips/idt/idtreg.h
trunk/sys/mips/idt/if_kr.c
trunk/sys/mips/idt/if_krreg.h
trunk/sys/mips/idt/obio.c
trunk/sys/mips/idt/obiovar.h
trunk/sys/mips/idt/std.idt
trunk/sys/mips/idt/uart_bus_rc32434.c
trunk/sys/mips/idt/uart_cpu_rc32434.c
trunk/sys/mips/include/
trunk/sys/mips/include/_align.h
trunk/sys/mips/include/_bus.h
trunk/sys/mips/include/_inttypes.h
trunk/sys/mips/include/_limits.h
trunk/sys/mips/include/_stdint.h
trunk/sys/mips/include/_types.h
trunk/sys/mips/include/asm.h
trunk/sys/mips/include/atomic.h
trunk/sys/mips/include/bootinfo.h
trunk/sys/mips/include/bus.h
trunk/sys/mips/include/bus_dma.h
trunk/sys/mips/include/cache.h
trunk/sys/mips/include/cache_mipsNN.h
trunk/sys/mips/include/cache_r4k.h
trunk/sys/mips/include/cdefs.h
trunk/sys/mips/include/clock.h
trunk/sys/mips/include/counter.h
trunk/sys/mips/include/cpu.h
trunk/sys/mips/include/cpufunc.h
trunk/sys/mips/include/cpuinfo.h
trunk/sys/mips/include/cpuregs.h
trunk/sys/mips/include/db_machdep.h
trunk/sys/mips/include/elf.h
trunk/sys/mips/include/endian.h
trunk/sys/mips/include/exec.h
trunk/sys/mips/include/fdt.h
trunk/sys/mips/include/float.h
trunk/sys/mips/include/floatingpoint.h
trunk/sys/mips/include/fls64.h
trunk/sys/mips/include/fpu.h
trunk/sys/mips/include/frame.h
trunk/sys/mips/include/gdb_machdep.h
trunk/sys/mips/include/hwfunc.h
trunk/sys/mips/include/ieee.h
trunk/sys/mips/include/ieeefp.h
trunk/sys/mips/include/in_cksum.h
trunk/sys/mips/include/intr_machdep.h
trunk/sys/mips/include/kdb.h
trunk/sys/mips/include/limits.h
trunk/sys/mips/include/locore.h
trunk/sys/mips/include/md_var.h
trunk/sys/mips/include/memdev.h
trunk/sys/mips/include/metadata.h
trunk/sys/mips/include/minidump.h
trunk/sys/mips/include/mips_opcode.h
trunk/sys/mips/include/octeon_cop2.h
trunk/sys/mips/include/ofw_machdep.h
trunk/sys/mips/include/param.h
trunk/sys/mips/include/pcb.h
trunk/sys/mips/include/pcpu.h
trunk/sys/mips/include/pmap.h
trunk/sys/mips/include/pmc_mdep.h
trunk/sys/mips/include/proc.h
trunk/sys/mips/include/profile.h
trunk/sys/mips/include/pte.h
trunk/sys/mips/include/ptrace.h
trunk/sys/mips/include/reg.h
trunk/sys/mips/include/regdef.h
trunk/sys/mips/include/regnum.h
trunk/sys/mips/include/reloc.h
trunk/sys/mips/include/resource.h
trunk/sys/mips/include/runq.h
trunk/sys/mips/include/sc_machdep.h
trunk/sys/mips/include/setjmp.h
trunk/sys/mips/include/sf_buf.h
trunk/sys/mips/include/sigframe.h
trunk/sys/mips/include/signal.h
trunk/sys/mips/include/smp.h
trunk/sys/mips/include/stdarg.h
trunk/sys/mips/include/sysarch.h
trunk/sys/mips/include/tlb.h
trunk/sys/mips/include/tls.h
trunk/sys/mips/include/trap.h
trunk/sys/mips/include/ucontext.h
trunk/sys/mips/include/varargs.h
trunk/sys/mips/include/vdso.h
trunk/sys/mips/include/vm.h
trunk/sys/mips/include/vmparam.h
trunk/sys/mips/malta/
trunk/sys/mips/malta/files.malta
trunk/sys/mips/malta/gt.c
trunk/sys/mips/malta/gt_pci.c
trunk/sys/mips/malta/gt_pci_bus_space.c
trunk/sys/mips/malta/gt_pci_bus_space.h
trunk/sys/mips/malta/gtreg.h
trunk/sys/mips/malta/gtvar.h
trunk/sys/mips/malta/malta_machdep.c
trunk/sys/mips/malta/maltareg.h
trunk/sys/mips/malta/obio.c
trunk/sys/mips/malta/obiovar.h
trunk/sys/mips/malta/std.malta
trunk/sys/mips/malta/uart_bus_maltausart.c
trunk/sys/mips/malta/uart_cpu_maltausart.c
trunk/sys/mips/malta/yamon.c
trunk/sys/mips/malta/yamon.h
trunk/sys/mips/mips/
trunk/sys/mips/mips/autoconf.c
trunk/sys/mips/mips/bcopy.S
trunk/sys/mips/mips/bus_space_fdt.c
trunk/sys/mips/mips/bus_space_generic.c
trunk/sys/mips/mips/busdma_machdep.c
trunk/sys/mips/mips/cache.c
trunk/sys/mips/mips/cache_mipsNN.c
trunk/sys/mips/mips/cpu.c
trunk/sys/mips/mips/db_disasm.c
trunk/sys/mips/mips/db_interface.c
trunk/sys/mips/mips/db_trace.c
trunk/sys/mips/mips/dump_machdep.c
trunk/sys/mips/mips/elf_machdep.c
trunk/sys/mips/mips/elf_trampoline.c
trunk/sys/mips/mips/exception.S
trunk/sys/mips/mips/fp.S
trunk/sys/mips/mips/freebsd32_machdep.c
trunk/sys/mips/mips/gdb_machdep.c
trunk/sys/mips/mips/genassym.c
trunk/sys/mips/mips/in_cksum.c
trunk/sys/mips/mips/inckern.S
trunk/sys/mips/mips/intr_machdep.c
trunk/sys/mips/mips/libkern_machdep.c
trunk/sys/mips/mips/locore.S
trunk/sys/mips/mips/machdep.c
trunk/sys/mips/mips/mem.c
trunk/sys/mips/mips/minidump_machdep.c
trunk/sys/mips/mips/mp_machdep.c
trunk/sys/mips/mips/mpboot.S
trunk/sys/mips/mips/nexus.c
trunk/sys/mips/mips/octeon_cop2.c
trunk/sys/mips/mips/octeon_cop2_swtch.S
trunk/sys/mips/mips/pm_machdep.c
trunk/sys/mips/mips/pmap.c
trunk/sys/mips/mips/ptrace_machdep.c
trunk/sys/mips/mips/sc_machdep.c
trunk/sys/mips/mips/stack_machdep.c
trunk/sys/mips/mips/stdatomic.c
trunk/sys/mips/mips/support.S
trunk/sys/mips/mips/swtch.S
trunk/sys/mips/mips/sys_machdep.c
trunk/sys/mips/mips/tick.c
trunk/sys/mips/mips/tlb.c
trunk/sys/mips/mips/trap.c
trunk/sys/mips/mips/uio_machdep.c
trunk/sys/mips/mips/uma_machdep.c
trunk/sys/mips/mips/vm_machdep.c
trunk/sys/mips/nlm/
trunk/sys/mips/nlm/board.c
trunk/sys/mips/nlm/board.h
trunk/sys/mips/nlm/board_cpld.c
trunk/sys/mips/nlm/board_eeprom.c
trunk/sys/mips/nlm/bus_space_rmi.c
trunk/sys/mips/nlm/bus_space_rmi_pci.c
trunk/sys/mips/nlm/clock.h
trunk/sys/mips/nlm/cms.c
trunk/sys/mips/nlm/dev/
trunk/sys/mips/nlm/dev/cfi_pci_xlp.c
trunk/sys/mips/nlm/dev/net/
trunk/sys/mips/nlm/dev/net/mdio.c
trunk/sys/mips/nlm/dev/net/nae.c
trunk/sys/mips/nlm/dev/net/sgmii.c
trunk/sys/mips/nlm/dev/net/ucore/
trunk/sys/mips/nlm/dev/net/ucore/crt0_basic.S
trunk/sys/mips/nlm/dev/net/ucore/ld.ucore.S
trunk/sys/mips/nlm/dev/net/ucore/ucore.h
trunk/sys/mips/nlm/dev/net/ucore/ucore_app.c
trunk/sys/mips/nlm/dev/net/xaui.c
trunk/sys/mips/nlm/dev/net/xlpge.c
trunk/sys/mips/nlm/dev/net/xlpge.h
trunk/sys/mips/nlm/dev/sec/
trunk/sys/mips/nlm/dev/sec/nlmrsa.c
trunk/sys/mips/nlm/dev/sec/nlmrsalib.h
trunk/sys/mips/nlm/dev/sec/nlmsec.c
trunk/sys/mips/nlm/dev/sec/nlmseclib.c
trunk/sys/mips/nlm/dev/sec/nlmseclib.h
trunk/sys/mips/nlm/dev/sec/rsa_ucode.h
trunk/sys/mips/nlm/dev/uart_pci_xlp.c
trunk/sys/mips/nlm/files.xlp
trunk/sys/mips/nlm/hal/
trunk/sys/mips/nlm/hal/bridge.h
trunk/sys/mips/nlm/hal/cop2.h
trunk/sys/mips/nlm/hal/cpucontrol.h
trunk/sys/mips/nlm/hal/fmn.c
trunk/sys/mips/nlm/hal/fmn.h
trunk/sys/mips/nlm/hal/gbu.h
trunk/sys/mips/nlm/hal/haldefs.h
trunk/sys/mips/nlm/hal/interlaken.h
trunk/sys/mips/nlm/hal/iomap.h
trunk/sys/mips/nlm/hal/mdio.h
trunk/sys/mips/nlm/hal/mips-extns.h
trunk/sys/mips/nlm/hal/mmu.h
trunk/sys/mips/nlm/hal/nae.h
trunk/sys/mips/nlm/hal/nlm_hal.c
trunk/sys/mips/nlm/hal/nlmsaelib.h
trunk/sys/mips/nlm/hal/pcibus.h
trunk/sys/mips/nlm/hal/pic.h
trunk/sys/mips/nlm/hal/poe.h
trunk/sys/mips/nlm/hal/sgmii.h
trunk/sys/mips/nlm/hal/sys.h
trunk/sys/mips/nlm/hal/uart.h
trunk/sys/mips/nlm/hal/ucore_loader.h
trunk/sys/mips/nlm/hal/usb.h
trunk/sys/mips/nlm/hal/xaui.h
trunk/sys/mips/nlm/interrupt.h
trunk/sys/mips/nlm/intr_machdep.c
trunk/sys/mips/nlm/mpreset.S
trunk/sys/mips/nlm/msgring.h
trunk/sys/mips/nlm/std.xlp
trunk/sys/mips/nlm/tick.c
trunk/sys/mips/nlm/uart_cpu_xlp.c
trunk/sys/mips/nlm/usb_init.c
trunk/sys/mips/nlm/xlp.h
trunk/sys/mips/nlm/xlp_machdep.c
trunk/sys/mips/nlm/xlp_pci.c
trunk/sys/mips/rmi/
trunk/sys/mips/rmi/Makefile.msgring
trunk/sys/mips/rmi/board.c
trunk/sys/mips/rmi/board.h
trunk/sys/mips/rmi/bus_space_rmi.c
trunk/sys/mips/rmi/bus_space_rmi_pci.c
trunk/sys/mips/rmi/dev/
trunk/sys/mips/rmi/dev/iic/
trunk/sys/mips/rmi/dev/iic/at24co2n.c
trunk/sys/mips/rmi/dev/iic/ds1374u.c
trunk/sys/mips/rmi/dev/iic/max6657.c
trunk/sys/mips/rmi/dev/nlge/
trunk/sys/mips/rmi/dev/nlge/if_nlge.c
trunk/sys/mips/rmi/dev/nlge/if_nlge.h
trunk/sys/mips/rmi/dev/sec/
trunk/sys/mips/rmi/dev/sec/desc.h
trunk/sys/mips/rmi/dev/sec/rmilib.c
trunk/sys/mips/rmi/dev/sec/rmilib.h
trunk/sys/mips/rmi/dev/sec/rmisec.c
trunk/sys/mips/rmi/dev/xlr/
trunk/sys/mips/rmi/dev/xlr/atx_cpld.h
trunk/sys/mips/rmi/dev/xlr/debug.h
trunk/sys/mips/rmi/dev/xlr/rge.c
trunk/sys/mips/rmi/dev/xlr/rge.h
trunk/sys/mips/rmi/dev/xlr/xgmac_mdio.h
trunk/sys/mips/rmi/files.xlr
trunk/sys/mips/rmi/fmn.c
trunk/sys/mips/rmi/interrupt.h
trunk/sys/mips/rmi/intr_machdep.c
trunk/sys/mips/rmi/iodi.c
trunk/sys/mips/rmi/iomap.h
trunk/sys/mips/rmi/mpwait.S
trunk/sys/mips/rmi/msgring.c
trunk/sys/mips/rmi/msgring.cfg
trunk/sys/mips/rmi/msgring.h
trunk/sys/mips/rmi/msgring_xls.c
trunk/sys/mips/rmi/msgring_xls.cfg
trunk/sys/mips/rmi/pcibus.h
trunk/sys/mips/rmi/pic.h
trunk/sys/mips/rmi/rmi_boot_info.h
trunk/sys/mips/rmi/rmi_mips_exts.h
trunk/sys/mips/rmi/rootfs_list.txt
trunk/sys/mips/rmi/std.xlr
trunk/sys/mips/rmi/tick.c
trunk/sys/mips/rmi/uart_bus_xlr_iodi.c
trunk/sys/mips/rmi/uart_cpu_mips_xlr.c
trunk/sys/mips/rmi/xlr_csum_nocopy.S
trunk/sys/mips/rmi/xlr_i2c.c
trunk/sys/mips/rmi/xlr_machdep.c
trunk/sys/mips/rmi/xlr_pci.c
trunk/sys/mips/rmi/xlr_pcmcia.c
trunk/sys/mips/rmi/xls_ehci.c
trunk/sys/mips/rt305x/
trunk/sys/mips/rt305x/files.rt305x
trunk/sys/mips/rt305x/obio.c
trunk/sys/mips/rt305x/obiovar.h
trunk/sys/mips/rt305x/rt305x_dotg.c
trunk/sys/mips/rt305x/rt305x_gpio.c
trunk/sys/mips/rt305x/rt305x_gpio.h
trunk/sys/mips/rt305x/rt305x_gpiovar.h
trunk/sys/mips/rt305x/rt305x_ic.c
trunk/sys/mips/rt305x/rt305x_icvar.h
trunk/sys/mips/rt305x/rt305x_machdep.c
trunk/sys/mips/rt305x/rt305x_sysctl.c
trunk/sys/mips/rt305x/rt305x_sysctlvar.h
trunk/sys/mips/rt305x/rt305xreg.h
trunk/sys/mips/rt305x/rt_swreg.h
trunk/sys/mips/rt305x/std.rt305x
trunk/sys/mips/rt305x/uart_bus_rt305x.c
trunk/sys/mips/rt305x/uart_cpu_rt305x.c
trunk/sys/mips/rt305x/uart_dev_rt305x.c
trunk/sys/mips/rt305x/uart_dev_rt305x.h
trunk/sys/mips/sentry5/
trunk/sys/mips/sentry5/files.sentry5
trunk/sys/mips/sentry5/obio.c
trunk/sys/mips/sentry5/obiovar.h
trunk/sys/mips/sentry5/s5_machdep.c
trunk/sys/mips/sentry5/s5reg.h
trunk/sys/mips/sentry5/std.sentry5
trunk/sys/mips/sentry5/uart_bus_sbusart.c
trunk/sys/mips/sentry5/uart_cpu_sbusart.c
trunk/sys/mips/sibyte/
trunk/sys/mips/sibyte/ata_zbbus.c
trunk/sys/mips/sibyte/files.sibyte
trunk/sys/mips/sibyte/sb_asm.S
trunk/sys/mips/sibyte/sb_bus_space.h
trunk/sys/mips/sibyte/sb_machdep.c
trunk/sys/mips/sibyte/sb_scd.c
trunk/sys/mips/sibyte/sb_scd.h
trunk/sys/mips/sibyte/sb_zbbus.c
trunk/sys/mips/sibyte/sb_zbpci.c
trunk/sys/mips/sibyte/std.sibyte
Added: trunk/sys/mips/adm5120/adm5120_machdep.c
===================================================================
--- trunk/sys/mips/adm5120/adm5120_machdep.c (rev 0)
+++ trunk/sys/mips/adm5120/adm5120_machdep.c 2018-05-26 21:55:02 UTC (rev 9987)
@@ -0,0 +1,145 @@
+/* $MidnightBSD$ */
+/*-
+ * Copyright (C) 2007 by Oleksandr Tymoshenko. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+ * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+ * IN NO EVENT SHALL THE AUTHOR OR HIS RELATIVES BE LIABLE FOR ANY DIRECT,
+ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF MIND, USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
+ * THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+#include <sys/cdefs.h>
+__FBSDID("$FreeBSD: stable/10/sys/mips/adm5120/adm5120_machdep.c 247297 2013-02-26 01:00:11Z attilio $");
+
+#include "opt_ddb.h"
+
+#include <sys/param.h>
+#include <sys/conf.h>
+#include <sys/kernel.h>
+#include <sys/systm.h>
+#include <sys/imgact.h>
+#include <sys/bio.h>
+#include <sys/buf.h>
+#include <sys/bus.h>
+#include <sys/cpu.h>
+#include <sys/cons.h>
+#include <sys/exec.h>
+#include <sys/ucontext.h>
+#include <sys/proc.h>
+#include <sys/kdb.h>
+#include <sys/ptrace.h>
+#include <sys/reboot.h>
+#include <sys/signalvar.h>
+#include <sys/sysent.h>
+#include <sys/sysproto.h>
+#include <sys/user.h>
+
+#include <vm/vm.h>
+#include <vm/vm_object.h>
+#include <vm/vm_page.h>
+
+#include <machine/cache.h>
+#include <machine/clock.h>
+#include <machine/cpu.h>
+#include <machine/cpuinfo.h>
+#include <machine/cpufunc.h>
+#include <machine/cpuregs.h>
+#include <machine/hwfunc.h>
+#include <machine/intr_machdep.h>
+#include <machine/locore.h>
+#include <machine/md_var.h>
+#include <machine/pte.h>
+#include <machine/sigframe.h>
+#include <machine/trap.h>
+#include <machine/vmparam.h>
+
+extern int *edata;
+extern int *end;
+
+void
+platform_cpu_init()
+{
+ /* Nothing special */
+}
+
+static void
+mips_init(void)
+{
+ int i;
+
+ printf("entry: mips_init()\n");
+
+ bootverbose = 1;
+ realmem = btoc(16 << 20);
+
+ for (i = 0; i < 10; i++) {
+ phys_avail[i] = 0;
+ }
+
+ /* phys_avail regions are in bytes */
+ phys_avail[0] = MIPS_KSEG0_TO_PHYS(kernel_kseg0_end);
+ phys_avail[1] = ctob(realmem);
+
+ dump_avail[0] = phys_avail[0];
+ dump_avail[1] = phys_avail[1];
+
+ physmem = realmem;
+
+ init_param1();
+ init_param2(physmem);
+ mips_cpu_init();
+ pmap_bootstrap();
+ mips_proc0_init();
+ mutex_init();
+ kdb_init();
+#ifdef KDB
+ if (boothowto & RB_KDB)
+ kdb_enter(KDB_WHY_BOOTFLAGS, "Boot flags requested debugger");
+#endif
+}
+
+void
+platform_reset(void)
+{
+
+ __asm __volatile("li $25, 0xbfc00000");
+ __asm __volatile("j $25");
+}
+
+void
+platform_start(__register_t a0 __unused, __register_t a1 __unused,
+ __register_t a2 __unused, __register_t a3 __unused)
+{
+ vm_offset_t kernend;
+ uint64_t platform_counter_freq = 175 * 1000 * 1000;
+
+ /* clear the BSS and SBSS segments */
+ kernend = (vm_offset_t)&end;
+ memset(&edata, 0, kernend - (vm_offset_t)(&edata));
+
+ mips_postboot_fixup();
+
+ /* Initialize pcpu stuff */
+ mips_pcpu0_init();
+
+ cninit();
+ mips_init();
+ mips_timer_init_params(platform_counter_freq, 0);
+}
Property changes on: trunk/sys/mips/adm5120/adm5120_machdep.c
___________________________________________________________________
Added: svn:eol-style
## -0,0 +1 ##
+native
\ No newline at end of property
Added: svn:keywords
## -0,0 +1 ##
+MidnightBSD=%H
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+text/plain
\ No newline at end of property
Added: trunk/sys/mips/adm5120/adm5120reg.h
===================================================================
--- trunk/sys/mips/adm5120/adm5120reg.h (rev 0)
+++ trunk/sys/mips/adm5120/adm5120reg.h 2018-05-26 21:55:02 UTC (rev 9987)
@@ -0,0 +1,295 @@
+/* $MidnightBSD$ */
+/* $NetBSD: adm5120reg.h,v 1.1 2007/03/20 08:52:03 dyoung Exp $ */
+
+/*-
+ * Copyright (c) 2007 Ruslan Ermilov and Vsevolod Lobko.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or
+ * without modification, are permitted provided that the following
+ * conditions are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above
+ * copyright notice, this list of conditions and the following
+ * disclaimer in the documentation and/or other materials provided
+ * with the distribution.
+ * 3. The names of the authors may not be used to endorse or promote
+ * products derived from this software without specific prior
+ * written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHORS ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
+ * PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHORS
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY,
+ * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
+ * TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
+ * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ *
+ * $FreeBSD: stable/10/sys/mips/adm5120/adm5120reg.h 202175 2010-01-12 21:36:08Z imp $
+ */
+
+#ifndef _ADM5120REG_H_
+#define _ADM5120REG_H_
+
+/* Helpers from NetBSD */
+/* __BIT(n): nth bit, where __BIT(0) == 0x1. */
+#define __BIT(__n) \
+ (((__n) >= NBBY * sizeof(uintmax_t)) ? 0 : ((uintmax_t)1 << (__n)))
+
+/* __BITS(m, n): bits m through n, m < n. */
+#define __BITS(__m, __n) \
+ ((__BIT(MAX((__m), (__n)) + 1) - 1) ^ (__BIT(MIN((__m), (__n))) - 1))
+
+/* Last byte of physical address space. */
+#define ADM5120_TOP 0x1fffffff
+#define ADM5120_BOTTOM 0x0
+
+/* Flash addresses */
+#define ADM5120_BASE_SRAM0 0x1fc00000
+
+/* UARTs */
+#define ADM5120_BASE_UART1 0x12800000
+#define ADM5120_BASE_UART0 0x12600000
+
+/* ICU */
+#define ADM5120_BASE_ICU 0x12200000
+#define ICU_STATUS_REG 0x00
+#define ICU_RAW_STATUS_REG 0x04
+#define ICU_ENABLE_REG 0x08
+#define ICU_DISABLE_REG 0x0c
+#define ICU_SOFT_REG 0x10
+#define ICU_MODE_REG 0x14
+#define ICU_FIQ_STATUS_REG 0x18
+#define ICU_TESTSRC_REG 0x1c
+#define ICU_SRCSEL_REG 0x20
+#define ICU_LEVEL_REG 0x24
+#define ICU_INT_MASK 0x3ff
+
+/* Switch */
+#define ADM5120_BASE_SWITCH 0x12000000
+#define SW_CODE_REG 0x00
+#define CLKS_MASK 0x00300000
+#define CLKS_175MHZ 0x00000000
+#define CLKS_200MHZ 0x00100000
+#define SW_SFTRES_REG 0x04
+#define SW_MEMCONT_REG 0x1c
+#define SDRAM_SIZE_4MBYTES 0x0001
+#define SDRAM_SIZE_8MBYTES 0x0002
+#define SDRAM_SIZE_16MBYTES 0x0003
+#define SDRAM_SIZE_64MBYTES 0x0004
+#define SDRAM_SIZE_128MBYTES 0x0005
+#define SDRAM_SIZE_MASK 0x0007
+#define SRAM0_SIZE_SHIFT 8
+#define SRAM1_SIZE_SHIFT 16
+#define SRAM_MASK 0x0007
+#define SRAM_SSIZE 0x40000
+
+#define ADM5120_BASE_PCI_CONFDATA 0x115ffff8
+#define ADM5120_BASE_PCI_CONFADDR 0x115ffff0
+#define ADM5120_BASE_PCI_IO 0x11500000
+#define ADM5120_BASE_PCI_MEM 0x11400000
+#define ADM5120_BASE_USB 0x11200000
+#define ADM5120_BASE_MPMC 0x11000000
+#define ADM5120_BASE_EXTIO1 0x10e00000
+#define ADM5120_BASE_EXTIO0 0x10c00000
+#define ADM5120_BASE_RSVD0 0x10800000
+#define ADM5120_BASE_SRAM1 0x10000000
+
+#define _REG_READ(b, o) *((volatile uint32_t *)MIPS_PHYS_TO_KSEG1((b) + (o)))
+#define SW_READ(o) _REG_READ(ADM5120_BASE_SWITCH, o)
+
+#define _REG_WRITE(b, o, v) (_REG_READ(b, o)) = (v)
+#define SW_WRITE(o, v) _REG_WRITE(ADM5120_BASE_SWITCH,o, v)
+
+/* USB */
+
+/* Watchdog Timers: base address is switch controller */
+
+#define ADM5120_WDOG0 0x00c0
+#define ADM5120_WDOG1 0x00c4
+
+#define ADM5120_WDOG0_WTTR __BIT(31) /* 0: do not reset,
+ * 1: reset on wdog expiration
+ */
+#define ADM5120_WDOG1_WDE __BIT(31) /* 0: deactivate,
+ * 1: drop all CPU-bound
+ * packets, disable flow
+ * control on all ports.
+ */
+#define ADM5120_WDOG_WTS_MASK __BITS(30, 16) /* Watchdog Timer Set:
+ * timer expires when it
+ * reaches WTS. Units of
+ * 10ms.
+ */
+#define ADM5120_WDOG_RSVD __BIT(15)
+#define ADM5120_WDOG_WT_MASK __BITS(14, 0) /* Watchdog Timer:
+ * counts up, write to clear.
+ */
+
+/* GPIO: base address is switch controller */
+#define ADM5120_GPIO0 0x00b8
+
+#define ADM5120_GPIO0_OV __BITS(31, 24) /* rw: output value */
+#define ADM5120_GPIO0_OE __BITS(23, 16) /* rw: output enable,
+ * bit[n] = 0 -> input
+ * bit[n] = 1 -> output
+ */
+#define ADM5120_GPIO0_IV __BITS(15, 8) /* ro: input value */
+#define ADM5120_GPIO0_RSVD __BITS(7, 0) /* rw: reserved */
+
+#define ADM5120_GPIO2 0x00bc
+#define ADM5120_GPIO2_EW __BIT(6) /* 1: enable wait state pin,
+ * pin GPIO[0], for GPIO[1]
+ * or GPIO[3] Chip Select:
+ * memory controller waits for
+ * WAIT# inactive (high).
+ */
+#define ADM5120_GPIO2_CSX1 __BIT(5) /* 1: GPIO[3:4] act as
+ * Chip Select for
+ * External I/O 1 (CSX1)
+ * and External Interrupt 1
+ * (INTX1), respectively.
+ * 0: CSX1/INTX1 disabled
+ */
+#define ADM5120_GPIO2_CSX0 __BIT(4) /* 1: GPIO[1:2] act as
+ * Chip Select for
+ * External I/O 0 (CSX0)
+ * and External Interrupt 0
+ * (INTX0), respectively.
+ * 0: CSX0/INTX0 disabled
+ */
+
+/* MultiPort Memory Controller (MPMC) */
+
+#define ADM5120_MPMC_CONTROL 0x000
+#define ADM5120_MPMC_CONTROL_DWB __BIT(3) /* write 1 to
+ * drain write
+ * buffers. write 0
+ * for normal buffer
+ * operation.
+ */
+#define ADM5120_MPMC_CONTROL_LPM __BIT(2) /* 1: activate low-power
+ * mode. SDRAM is
+ * still refreshed.
+ */
+#define ADM5120_MPMC_CONTROL_AM __BIT(1) /* 1: address mirror:
+ * static memory
+ * chip select 0
+ * is mapped to chip
+ * select 1.
+ */
+#define ADM5120_MPMC_CONTROL_ME __BIT(0) /* 0: disable MPMC.
+ * DRAM is not
+ * refreshed.
+ * 1: enable MPMC.
+ */
+
+#define ADM5120_MPMC_STATUS 0x004
+#define ADM5120_MPMC_STATUS_SRA __BIT(2) /* read-only
+ * MPMC operating mode
+ * indication,
+ * 1: self-refresh
+ * acknowledge
+ * 0: normal mode
+ */
+#define ADM5120_MPMC_STATUS_WBS __BIT(1) /* read-only
+ * write-buffer status,
+ * 0: buffers empty
+ * 1: contain data
+ */
+#define ADM5120_MPMC_STATUS_BU __BIT(0) /* read-only MPMC
+ * "busy" indication,
+ * 0: MPMC idle
+ * 1: MPMC is performing
+ * memory transactions
+ */
+
+#define ADM5120_MPMC_SEW 0x080
+#define ADM5120_MPMC_SEW_RSVD __BITS(31, 10)
+#define ADM5120_MPMC_SEW_EWTO __BITS(9, 0) /* timeout access after
+ * 16 * (n + 1) clock cycles
+ * (XXX which clock?)
+ */
+
+#define ADM5120_MPMC_SC(__i) (0x200 + 0x020 * (__i))
+#define ADM5120_MPMC_SC_RSVD0 __BITS(31, 21)
+#define ADM5120_MPMC_SC_WP __BIT(20) /* 1: write protect */
+#define ADM5120_MPMC_SC_BE __BIT(20) /* 1: enable write buffer */
+#define ADM5120_MPMC_SC_RSVD1 __BITS(18, 9)
+#define ADM5120_MPMC_SC_EW __BIT(8) /* 1: enable extended wait;
+ */
+#define ADM5120_MPMC_SC_BLS __BIT(7) /* 0: byte line state pins
+ * are active high on read,
+ * active low on write.
+ *
+ * 1: byte line state pins
+ * are active low on read and
+ * on write.
+ */
+#define ADM5120_MPMC_SC_CCP __BIT(6) /* 0: chip select is active low,
+ * 1: active high
+ */
+#define ADM5120_MPMC_SC_RSVD2 __BITS(5, 4)
+#define ADM5120_MPMC_SC_PM __BIT(3) /* 0: page mode disabled,
+ * 1: enable asynchronous
+ * page mode four
+ */
+#define ADM5120_MPMC_SC_RSVD3 __BIT(2)
+#define ADM5120_MPMC_SC_MW_MASK __BITS(1, 0) /* memory width, bits */
+#define ADM5120_MPMC_SC_MW_8B __SHIFTIN(0, ADM5120_MPMC_SC_MW_MASK)
+#define ADM5120_MPMC_SC_MW_16B __SHIFTIN(1, ADM5120_MPMC_SC_MW_MASK)
+#define ADM5120_MPMC_SC_MW_32B __SHIFTIN(2, ADM5120_MPMC_SC_MW_MASK)
+#define ADM5120_MPMC_SC_MW_RSVD __SHIFTIN(3, ADM5120_MPMC_SC_MW_MASK)
+
+#define ADM5120_MPMC_SWW(__i) (0x204 + 0x020 * (__i))
+#define ADM5120_MPMC_SWW_RSVD __BITS(31, 4)
+#define ADM5120_MPMC_SWW_WWE __BITS(3, 0) /* delay (n + 1) * HCLK cycles
+ * after asserting chip select
+ * (CS) before asserting write
+ * enable (WE)
+ */
+
+#define ADM5120_MPMC_SWO(__i) (0x208 + 0x020 * (__i))
+#define ADM5120_MPMC_SWO_RSVD __BITS(31, 4)
+#define ADM5120_MPMC_SWO_WOE __BITS(3, 0) /* delay n * HCLK cycles
+ * after asserting chip select
+ * before asserting output
+ * enable (OE)
+ */
+
+#define ADM5120_MPMC_SWR(__i) (0x20c + 0x020 * (__i))
+#define ADM5120_MPMC_SWR_RSVD __BITS(31, 5)
+#define ADM5120_MPMC_SWR_NMRW __BITS(4, 0) /* read wait states for
+ * either first page-mode
+ * access or for non-page mode
+ * read, (n + 1) * HCLK cycles
+ */
+
+#define ADM5120_MPMC_SWP(__i) (0x210 + 0x020 * (__i))
+#define ADM5120_MPMC_SWP_RSVD __BITS(31, 5)
+#define ADM5120_MPMC_SWP_WPS __BITS(4, 0) /* read wait states for
+ * second and subsequent
+ * page-mode read,
+ * (n + 1) * HCLK cycles
+ */
+
+#define ADM5120_MPMC_SWWR(__i) (0x214 + 0x020 * (__i))
+#define ADM5120_MPMC_SWWR_RSVD __BITS(31, 5)
+#define ADM5120_MPMC_SWWR_WWS __BITS(4, 0) /* write wait states after
+ * the first read (??),
+ * (n + 2) * HCLK cycles
+ */
+
+#define ADM5120_MPMC_SWT(__i) (0x218 + 0x020 * (__i))
+#define ADM5120_MPMC_SWT_RSVD __BITS(31, 4)
+#define ADM5120_MPMC_SWT_WAITTURN __BITS(3, 0) /* bus turnaround time,
+ * (n + 1) * HCLK cycles
+ */
+
+#endif /* _ADM5120REG_H_ */
Property changes on: trunk/sys/mips/adm5120/adm5120reg.h
___________________________________________________________________
Added: svn:eol-style
## -0,0 +1 ##
+native
\ No newline at end of property
Added: svn:keywords
## -0,0 +1 ##
+MidnightBSD=%H
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+text/plain
\ No newline at end of property
Added: trunk/sys/mips/adm5120/admpci.c
===================================================================
--- trunk/sys/mips/adm5120/admpci.c (rev 0)
+++ trunk/sys/mips/adm5120/admpci.c 2018-05-26 21:55:02 UTC (rev 9987)
@@ -0,0 +1,503 @@
+/* $MidnightBSD$ */
+/* $NetBSD: admpci.c,v 1.1 2007/03/20 08:52:02 dyoung Exp $ */
+
+/*-
+ * Copyright (c) 2007 David Young. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or
+ * without modification, are permitted provided that the following
+ * conditions are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above
+ * copyright notice, this list of conditions and the following
+ * disclaimer in the documentation and/or other materials provided
+ * with the distribution.
+ * 3. The name of the author may not be used to endorse or promote
+ * products derived from this software without specific prior
+ * written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
+ * PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY,
+ * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
+ * TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
+ * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ */
+/*-
+ * Copyright (c) 2006 Itronix Inc.
+ * All rights reserved.
+ *
+ * Written by Garrett D'Amore for Itronix Inc.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * 3. The name of Itronix Inc. may not be used to endorse
+ * or promote products derived from this software without specific
+ * prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ITRONIX INC. ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL ITRONIX INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <sys/cdefs.h>
+__FBSDID("$FreeBSD: stable/10/sys/mips/adm5120/admpci.c 227843 2011-11-22 21:28:20Z marius $");
+
+#include <sys/param.h>
+#include <sys/systm.h>
+
+#include <sys/bus.h>
+#include <sys/interrupt.h>
+#include <sys/malloc.h>
+#include <sys/kernel.h>
+#include <sys/module.h>
+#include <sys/rman.h>
+
+#include <vm/vm.h>
+#include <vm/pmap.h>
+#include <vm/vm_extern.h>
+
+#include <machine/bus.h>
+#include <machine/cpu.h>
+#include <machine/pmap.h>
+
+#include <dev/pci/pcivar.h>
+#include <dev/pci/pcireg.h>
+
+#include <dev/pci/pcib_private.h>
+#include "pcib_if.h"
+
+#include <mips/adm5120/adm5120reg.h>
+
+#ifdef ADMPCI_DEBUG
+int admpci_debug = 1;
+#define ADMPCI_DPRINTF(__fmt, ...) \
+do { \
+ if (admpci_debug) \
+ printf((__fmt), __VA_ARGS__); \
+} while (/*CONSTCOND*/0)
+#else /* !ADMPCI_DEBUG */
+#define ADMPCI_DPRINTF(__fmt, ...) do { } while (/*CONSTCOND*/0)
+#endif /* ADMPCI_DEBUG */
+
+#define ADMPCI_TAG_BUS_MASK __BITS(23, 16)
+/* Bit 11 is reserved. It selects the AHB-PCI bridge. Let device 0
+ * be the bridge. For all other device numbers, let bit[11] == 0.
+ */
+#define ADMPCI_TAG_DEVICE_MASK __BITS(15, 11)
+#define ADMPCI_TAG_DEVICE_SUBMASK __BITS(15, 12)
+#define ADMPCI_TAG_DEVICE_BRIDGE __BIT(11)
+#define ADMPCI_TAG_FUNCTION_MASK __BITS(10, 8)
+#define ADMPCI_TAG_REGISTER_MASK __BITS(7, 0)
+
+#define ADMPCI_MAX_DEVICE
+
+struct admpci_softc {
+ device_t sc_dev;
+ bus_space_tag_t sc_st;
+
+ /* Access to PCI config registers */
+ bus_space_handle_t sc_addrh;
+ bus_space_handle_t sc_datah;
+
+ int sc_busno;
+ struct rman sc_mem_rman;
+ struct rman sc_io_rman;
+ struct rman sc_irq_rman;
+ uint32_t sc_mem;
+ uint32_t sc_io;
+};
+
+static int
+admpci_probe(device_t dev)
+{
+
+ return (0);
+}
+
+static int
+admpci_attach(device_t dev)
+{
+ int busno = 0;
+ struct admpci_softc *sc = device_get_softc(dev);
+
+ sc->sc_dev = dev;
+ sc->sc_busno = busno;
+
+ /* Use KSEG1 to access IO ports for it is uncached */
+ sc->sc_io = MIPS_PHYS_TO_KSEG1(ADM5120_BASE_PCI_IO);
+ sc->sc_io_rman.rm_type = RMAN_ARRAY;
+ sc->sc_io_rman.rm_descr = "ADMPCI I/O Ports";
+ if (rman_init(&sc->sc_io_rman) != 0 ||
+ rman_manage_region(&sc->sc_io_rman, 0, 0xffff) != 0) {
+ panic("admpci_attach: failed to set up I/O rman");
+ }
+
+ /* Use KSEG1 to access PCI memory for it is uncached */
+ sc->sc_mem = MIPS_PHYS_TO_KSEG1(ADM5120_BASE_PCI_MEM);
+ sc->sc_mem_rman.rm_type = RMAN_ARRAY;
+ sc->sc_mem_rman.rm_descr = "ADMPCI PCI Memory";
+ if (rman_init(&sc->sc_mem_rman) != 0 ||
+ rman_manage_region(&sc->sc_mem_rman,
+ sc->sc_mem, sc->sc_mem + 0x100000) != 0) {
+ panic("admpci_attach: failed to set up memory rman");
+ }
+
+ sc->sc_irq_rman.rm_type = RMAN_ARRAY;
+ sc->sc_irq_rman.rm_descr = "ADMPCI PCI IRQs";
+ if (rman_init(&sc->sc_irq_rman) != 0 ||
+ rman_manage_region(&sc->sc_irq_rman, 1, 31) != 0)
+ panic("admpci_attach: failed to set up IRQ rman");
+
+ if (bus_space_map(sc->sc_st, ADM5120_BASE_PCI_CONFADDR, 4, 0,
+ &sc->sc_addrh) != 0) {
+ device_printf(sc->sc_dev, "unable to address space\n");
+ panic("bus_space_map failed");
+ }
+
+ if (bus_space_map(sc->sc_st, ADM5120_BASE_PCI_CONFDATA, 4, 0,
+ &sc->sc_datah) != 0) {
+ device_printf(sc->sc_dev, "unable to address space\n");
+ panic("bus_space_map failed");
+ }
+
+ device_add_child(dev, "pci", busno);
+ return (bus_generic_attach(dev));
+}
+
+static int
+admpci_maxslots(device_t dev)
+{
+
+ return (PCI_SLOTMAX);
+}
+
+static uint32_t
+admpci_make_addr(int bus, int slot, int func, int reg)
+{
+
+ return (0x80000000 | (bus << 16) | (slot << 11) | (func << 8) | reg);
+}
+
+static uint32_t
+admpci_read_config(device_t dev, int bus, int slot, int func, int reg,
+ int bytes)
+{
+ struct admpci_softc *sc = device_get_softc(dev);
+ uint32_t data;
+ uint32_t shift, mask;
+ bus_addr_t addr;
+
+ ADMPCI_DPRINTF("%s: sc %p tag (%x, %x, %x) reg %d\n", __func__,
+ (void *)sc, bus, slot, func, reg);
+
+ addr = admpci_make_addr(bus, slot, func, reg);
+
+ ADMPCI_DPRINTF("%s: sc_addrh %p sc_datah %p addr %p\n", __func__,
+ (void *)sc->sc_addrh, (void *)sc->sc_datah, (void *)addr);
+
+ bus_space_write_4(sc->sc_io, sc->sc_addrh, 0, addr);
+ data = bus_space_read_4(sc->sc_io, sc->sc_datah, 0);
+
+ switch (reg % 4) {
+ case 3:
+ shift = 24;
+ break;
+ case 2:
+ shift = 16;
+ break;
+ case 1:
+ shift = 8;
+ break;
+ default:
+ shift = 0;
+ break;
+ }
+
+ switch (bytes) {
+ case 1:
+ mask = 0xff;
+ data = (data >> shift) & mask;
+ break;
+ case 2:
+ mask = 0xffff;
+ if (reg % 4 == 0)
+ data = data & mask;
+ else
+ data = (data >> 16) & mask;
+ break;
+ case 4:
+ break;
+ default:
+ panic("%s: wrong bytes count", __func__);
+ break;
+ }
+
+ ADMPCI_DPRINTF("%s: read 0x%x\n", __func__, data);
+ return (data);
+}
+
+static void
+admpci_write_config(device_t dev, int bus, int slot, int func, int reg,
+ uint32_t data, int bytes)
+{
+ struct admpci_softc *sc = device_get_softc(dev);
+ bus_addr_t addr;
+ uint32_t reg_data;
+ uint32_t shift, mask;
+
+ ADMPCI_DPRINTF("%s: sc %p tag (%x, %x, %x) reg %d\n", __func__,
+ (void *)sc, bus, slot, func, reg);
+
+ if (bytes != 4) {
+ reg_data = admpci_read_config(dev, bus, slot, func, reg, 4);
+
+ switch (reg % 4) {
+ case 3:
+ shift = 24;
+ break;
+ case 2:
+ shift = 16;
+ break;
+ case 1:
+ shift = 8;
+ break;
+ default:
+ shift = 0;
+ break;
+ }
+
+ switch (bytes) {
+ case 1:
+ mask = 0xff;
+ data = (reg_data & ~ (mask << shift)) | (data << shift);
+ break;
+ case 2:
+ mask = 0xffff;
+ if (reg % 4 == 0)
+ data = (reg_data & ~mask) | data;
+ else
+ data = (reg_data & ~ (mask << shift)) |
+ (data << shift);
+ break;
+ case 4:
+ break;
+ default:
+ panic("%s: wrong bytes count", __func__);
+ break;
+ }
+ }
+
+ addr = admpci_make_addr(bus, slot, func, reg);
+
+ ADMPCI_DPRINTF("%s: sc_addrh %p sc_datah %p addr %p\n", __func__,
+ (void *)sc->sc_addrh, (void *)sc->sc_datah, (void *)addr);
+
+ bus_space_write_4(sc->sc_io, sc->sc_addrh, 0, addr);
+ bus_space_write_4(sc->sc_io, sc->sc_datah, 0, data);
+}
+
+static int
+admpci_route_interrupt(device_t pcib, device_t dev, int pin)
+{
+ /* TODO: implement */
+ return (0);
+}
+
+static int
+admpci_read_ivar(device_t dev, device_t child, int which, uintptr_t *result)
+{
+ struct admpci_softc *sc = device_get_softc(dev);
+
+ switch (which) {
+ case PCIB_IVAR_DOMAIN:
+ *result = 0;
+ return (0);
+ case PCIB_IVAR_BUS:
+ *result = sc->sc_busno;
+ return (0);
+ }
+
+ return (ENOENT);
+}
+
+static int
+admpci_write_ivar(device_t dev, device_t child, int which, uintptr_t result)
+{
+ struct admpci_softc * sc = device_get_softc(dev);
+
+ switch (which) {
+ case PCIB_IVAR_BUS:
+ sc->sc_busno = result;
+ return (0);
+ }
+ return (ENOENT);
+}
+
+static struct resource *
+admpci_alloc_resource(device_t bus, device_t child, int type, int *rid,
+ u_long start, u_long end, u_long count, u_int flags)
+{
+
+ return (NULL);
+#if 0
+ struct admpci_softc *sc = device_get_softc(bus);
+ struct resource *rv = NULL;
+ struct rman *rm;
+ bus_space_handle_t bh = 0;
+
+ switch (type) {
+ case SYS_RES_IRQ:
+ rm = &sc->sc_irq_rman;
+ break;
+ case SYS_RES_MEMORY:
+ rm = &sc->sc_mem_rman;
+ bh = sc->sc_mem;
+ break;
+ case SYS_RES_IOPORT:
+ rm = &sc->sc_io_rman;
+ bh = sc->sc_io;
+ break;
+ default:
+ return (NULL);
+ }
+
+ rv = rman_reserve_resource(rm, start, end, count, flags, child);
+ if (rv == NULL)
+ return (NULL);
+ rman_set_rid(rv, *rid);
+ if (type != SYS_RES_IRQ) {
+ bh += (rman_get_start(rv));
+
+ rman_set_bustag(rv, sc->sc_st);
+ rman_set_bushandle(rv, bh);
+ if (flags & RF_ACTIVE) {
+ if (bus_activate_resource(child, type, *rid, rv)) {
+ rman_release_resource(rv);
+ return (NULL);
+ }
+ }
+ }
+ return (rv);
+#endif
+}
+
+static int
+admpci_activate_resource(device_t bus, device_t child, int type, int rid,
+ struct resource *r)
+{
+ bus_space_handle_t p;
+ int error;
+
+ if ((type == SYS_RES_MEMORY) || (type == SYS_RES_IOPORT)) {
+ error = bus_space_map(rman_get_bustag(r),
+ rman_get_bushandle(r), rman_get_size(r), 0, &p);
+ if (error)
+ return (error);
+ rman_set_bushandle(r, p);
+ }
+ return (rman_activate_resource(r));
+}
+
+static int
+admpci_setup_intr(device_t dev, device_t child, struct resource *ires,
+ int flags, driver_filter_t *filt, driver_intr_t *handler,
+ void *arg, void **cookiep)
+{
+
+#if 0
+ struct admpci_softc *sc = device_get_softc(dev);
+ struct intr_event *event;
+ int irq, error;
+
+ irq = rman_get_start(ires);
+ if (irq >= ICU_LEN || irq == 2)
+ panic("%s: bad irq or type", __func__);
+
+ event = sc->sc_eventstab[irq];
+ if (event == NULL) {
+ error = intr_event_create(&event, (void *)irq, 0,
+ (void (*)(void *))NULL, "admpci intr%d:", irq);
+ if (error)
+ return 0;
+ sc->sc_eventstab[irq] = event;
+ }
+
+ intr_event_add_handler(event, device_get_nameunit(child), filt,
+ handler, arg, intr_priority(flags), flags, cookiep);
+
+ /* Enable it, set trigger mode. */
+ sc->sc_imask &= ~(1 << irq);
+ sc->sc_elcr &= ~(1 << irq);
+
+ admpci_set_icus(sc);
+#endif
+
+ return (0);
+}
+
+static int
+admpci_teardown_intr(device_t dev, device_t child, struct resource *res,
+ void *cookie)
+{
+
+ return (intr_event_remove_handler(cookie));
+}
+
+static device_method_t admpci_methods[] = {
+ /* Device interface */
+ DEVMETHOD(device_probe, admpci_probe),
+ DEVMETHOD(device_attach, admpci_attach),
+ DEVMETHOD(device_shutdown, bus_generic_shutdown),
+ DEVMETHOD(device_suspend, bus_generic_suspend),
+ DEVMETHOD(device_resume, bus_generic_resume),
+
+ /* Bus interface */
+ DEVMETHOD(bus_read_ivar, admpci_read_ivar),
+ DEVMETHOD(bus_write_ivar, admpci_write_ivar),
+ DEVMETHOD(bus_alloc_resource, admpci_alloc_resource),
+ DEVMETHOD(bus_release_resource, bus_generic_release_resource),
+ DEVMETHOD(bus_activate_resource, admpci_activate_resource),
+ DEVMETHOD(bus_deactivate_resource, bus_generic_deactivate_resource),
+ DEVMETHOD(bus_setup_intr, admpci_setup_intr),
+ DEVMETHOD(bus_teardown_intr, admpci_teardown_intr),
+
+ /* pcib interface */
+ DEVMETHOD(pcib_maxslots, admpci_maxslots),
+ DEVMETHOD(pcib_read_config, admpci_read_config),
+ DEVMETHOD(pcib_write_config, admpci_write_config),
+ DEVMETHOD(pcib_route_interrupt, admpci_route_interrupt),
+
+ DEVMETHOD_END
+};
+
+static driver_t admpci_driver = {
+ "pcib",
+ admpci_methods,
+ sizeof(struct admpci_softc),
+};
+
+static devclass_t admpci_devclass;
+
+DRIVER_MODULE(admpci, obio, admpci_driver, admpci_devclass, 0, 0);
Property changes on: trunk/sys/mips/adm5120/admpci.c
___________________________________________________________________
Added: svn:eol-style
## -0,0 +1 ##
+native
\ No newline at end of property
Added: svn:keywords
## -0,0 +1 ##
+MidnightBSD=%H
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+text/plain
\ No newline at end of property
Added: trunk/sys/mips/adm5120/console.c
===================================================================
--- trunk/sys/mips/adm5120/console.c (rev 0)
+++ trunk/sys/mips/adm5120/console.c 2018-05-26 21:55:02 UTC (rev 9987)
@@ -0,0 +1,108 @@
+/* $MidnightBSD$ */
+/* $NetBSD: uart.c,v 1.2 2007/03/23 20:05:47 dogcow Exp $ */
+
+/*-
+ * Copyright (c) 2007 Ruslan Ermilov and Vsevolod Lobko.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or
+ * without modification, are permitted provided that the following
+ * conditions are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above
+ * copyright notice, this list of conditions and the following
+ * disclaimer in the documentation and/or other materials provided
+ * with the distribution.
+ * 3. The names of the authors may not be used to endorse or promote
+ * products derived from this software without specific prior
+ * written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHORS ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
+ * PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHORS
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY,
+ * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
+ * TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
+ * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ *
+ */
+
+#include <sys/cdefs.h>
+__FBSDID("$FreeBSD: stable/10/sys/mips/adm5120/console.c 228631 2011-12-17 15:08:43Z avg $");
+
+#include <sys/types.h>
+#include <sys/param.h>
+#include <sys/systm.h>
+#include <sys/kernel.h>
+#include <sys/time.h>
+
+#include <sys/cons.h>
+#include <sys/consio.h>
+
+static cn_probe_t uart_cnprobe;
+static cn_init_t uart_cninit;
+static cn_term_t uart_cnterm;
+static cn_getc_t uart_cngetc;
+static cn_putc_t uart_cnputc;
+static cn_grab_t uart_cngrab;
+static cn_ungrab_t uart_cnungrab;
+
+static void
+uart_cnprobe(struct consdev *cp)
+{
+
+ sprintf(cp->cn_name, "uart");
+ cp->cn_pri = CN_NORMAL;
+}
+
+static void
+uart_cninit(struct consdev *cp)
+{
+
+}
+
+
+void
+uart_cnputc(struct consdev *cp, int c)
+{
+ char chr;
+
+ chr = c;
+ while ((*((volatile unsigned long *)0xb2600018)) & 0x20) ;
+ (*((volatile unsigned long *)0xb2600000)) = c;
+ while ((*((volatile unsigned long *)0xb2600018)) & 0x20) ;
+}
+
+int
+uart_cngetc(struct consdev * cp)
+{
+
+ while ((*((volatile unsigned long *)0xb2600018)) & 0x10) ;
+ return (*((volatile unsigned long *)0xb2600000)) & 0xff;
+}
+
+static void
+uart_cnterm(struct consdev * cp)
+{
+
+}
+
+static void
+uart_cngrab(struct consdev *cp)
+{
+
+}
+
+static void
+uart_cnungrab(struct consdev *cp)
+{
+
+}
+
+CONSOLE_DRIVER(uart);
Property changes on: trunk/sys/mips/adm5120/console.c
___________________________________________________________________
Added: svn:eol-style
## -0,0 +1 ##
+native
\ No newline at end of property
Added: svn:keywords
## -0,0 +1 ##
+MidnightBSD=%H
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+text/plain
\ No newline at end of property
Added: trunk/sys/mips/adm5120/files.adm5120
===================================================================
--- trunk/sys/mips/adm5120/files.adm5120 (rev 0)
+++ trunk/sys/mips/adm5120/files.adm5120 2018-05-26 21:55:02 UTC (rev 9987)
@@ -0,0 +1,13 @@
+# $FreeBSD: stable/10/sys/mips/adm5120/files.adm5120 202175 2010-01-12 21:36:08Z imp $
+
+# ADM5120 on-board devices
+# mips/adm5120/console.c standard
+mips/adm5120/adm5120_machdep.c standard
+mips/adm5120/admpci.c optional admpci
+mips/adm5120/if_admsw.c optional admsw
+mips/adm5120/obio.c standard
+mips/adm5120/uart_bus_adm5120.c optional uart
+mips/adm5120/uart_cpu_adm5120.c optional uart
+mips/adm5120/uart_dev_adm5120.c optional uart
+mips/mips/intr_machdep.c standard
+mips/mips/tick.c standard
Property changes on: trunk/sys/mips/adm5120/files.adm5120
___________________________________________________________________
Added: mnbsd:nokeywords
## -0,0 +1 ##
+MidnightBSD=%H
\ No newline at end of property
Added: trunk/sys/mips/adm5120/if_admsw.c
===================================================================
--- trunk/sys/mips/adm5120/if_admsw.c (rev 0)
+++ trunk/sys/mips/adm5120/if_admsw.c 2018-05-26 21:55:02 UTC (rev 9987)
@@ -0,0 +1,1354 @@
+/* $MidnightBSD$ */
+/* $NetBSD: if_admsw.c,v 1.3 2007/04/22 19:26:25 dyoung Exp $ */
+
+/*-
+ * Copyright (c) 2007 Ruslan Ermilov and Vsevolod Lobko.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or
+ * without modification, are permitted provided that the following
+ * conditions are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above
+ * copyright notice, this list of conditions and the following
+ * disclaimer in the documentation and/or other materials provided
+ * with the distribution.
+ * 3. The names of the authors may not be used to endorse or promote
+ * products derived from this software without specific prior
+ * written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHORS ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
+ * PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHORS
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY,
+ * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
+ * TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
+ * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ */
+/*
+ * Copyright (c) 2001 Wasabi Systems, Inc.
+ * All rights reserved.
+ *
+ * Written by Jason R. Thorpe for Wasabi Systems, Inc.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * 3. All advertising materials mentioning features or use of this software
+ * must display the following acknowledgement:
+ * This product includes software developed for the NetBSD Project by
+ * Wasabi Systems, Inc.
+ * 4. The name of Wasabi Systems, Inc. may not be used to endorse
+ * or promote products derived from this software without specific prior
+ * written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/*
+ * Device driver for Alchemy Semiconductor Au1x00 Ethernet Media
+ * Access Controller.
+ *
+ * TODO:
+ *
+ * Better Rx buffer management; we want to get new Rx buffers
+ * to the chip more quickly than we currently do.
+ */
+
+#include <sys/cdefs.h>
+__FBSDID("$FreeBSD: stable/10/sys/mips/adm5120/if_admsw.c 243882 2012-12-05 08:04:20Z glebius $");
+
+#include <sys/param.h>
+#include <sys/systm.h>
+#include <sys/bus.h>
+#include <sys/kernel.h>
+#include <sys/mbuf.h>
+#include <sys/malloc.h>
+#include <sys/module.h>
+#include <sys/rman.h>
+#include <sys/socket.h>
+#include <sys/sockio.h>
+#include <sys/sysctl.h>
+#include <machine/bus.h>
+
+#include <net/ethernet.h>
+#include <net/if.h>
+#include <net/if_arp.h>
+#include <net/if_dl.h>
+#include <net/if_media.h>
+#include <net/if_mib.h>
+#include <net/if_types.h>
+
+#ifdef INET
+#include <netinet/in.h>
+#include <netinet/in_systm.h>
+#include <netinet/in_var.h>
+#include <netinet/ip.h>
+#endif
+
+#include <net/bpf.h>
+#include <net/bpfdesc.h>
+
+#include <mips/adm5120/adm5120reg.h>
+#include <mips/adm5120/if_admswreg.h>
+#include <mips/adm5120/if_admswvar.h>
+
+/* TODO: add locking */
+#define ADMSW_LOCK(sc) do {} while(0);
+#define ADMSW_UNLOCK(sc) do {} while(0);
+
+static uint8_t vlan_matrix[SW_DEVS] = {
+ (1 << 6) | (1 << 0), /* CPU + port0 */
+ (1 << 6) | (1 << 1), /* CPU + port1 */
+ (1 << 6) | (1 << 2), /* CPU + port2 */
+ (1 << 6) | (1 << 3), /* CPU + port3 */
+ (1 << 6) | (1 << 4), /* CPU + port4 */
+ (1 << 6) | (1 << 5), /* CPU + port5 */
+};
+
+/* ifnet entry points */
+static void admsw_start(struct ifnet *);
+static void admsw_watchdog(void *);
+static int admsw_ioctl(struct ifnet *, u_long, caddr_t);
+static void admsw_init(void *);
+static void admsw_stop(struct ifnet *, int);
+
+static void admsw_reset(struct admsw_softc *);
+static void admsw_set_filter(struct admsw_softc *);
+
+static void admsw_txintr(struct admsw_softc *, int);
+static void admsw_rxintr(struct admsw_softc *, int);
+static int admsw_add_rxbuf(struct admsw_softc *, int, int);
+#define admsw_add_rxhbuf(sc, idx) admsw_add_rxbuf(sc, idx, 1)
+#define admsw_add_rxlbuf(sc, idx) admsw_add_rxbuf(sc, idx, 0)
+
+static int admsw_mediachange(struct ifnet *);
+static void admsw_mediastatus(struct ifnet *, struct ifmediareq *);
+
+static int admsw_intr(void *);
+
+/* bus entry points */
+static int admsw_probe(device_t dev);
+static int admsw_attach(device_t dev);
+static int admsw_detach(device_t dev);
+static int admsw_shutdown(device_t dev);
+
+static void
+admsw_dma_map_addr(void *arg, bus_dma_segment_t *segs, int nseg, int error)
+{
+ uint32_t *addr;
+
+ if (error)
+ return;
+
+ KASSERT(nseg == 1, ("too many DMA segments, %d should be 1", nseg));
+ addr = arg;
+ *addr = segs->ds_addr;
+}
+
+static void
+admsw_rxbuf_map_addr(void *arg, bus_dma_segment_t *segs, int nseg, int error)
+{
+ struct admsw_descsoft *ds;
+
+ if (error)
+ return;
+
+ KASSERT(nseg == 1, ("too many DMA segments, %d should be 1", nseg));
+
+ ds = arg;
+ ds->ds_nsegs = nseg;
+ ds->ds_addr[0] = segs[0].ds_addr;
+ ds->ds_len[0] = segs[0].ds_len;
+
+}
+
+static void
+admsw_mbuf_map_addr(void *arg, bus_dma_segment_t *segs, int nseg,
+ bus_size_t mapsize, int error)
+{
+ struct admsw_descsoft *ds;
+
+ if (error)
+ return;
+
+ ds = arg;
+
+ if((nseg != 1) && (nseg != 2))
+ panic("%s: nseg == %d\n", __func__, nseg);
+
+ ds->ds_nsegs = nseg;
+ ds->ds_addr[0] = segs[0].ds_addr;
+ ds->ds_len[0] = segs[0].ds_len;
+
+ if(nseg > 1) {
+ ds->ds_addr[1] = segs[1].ds_addr;
+ ds->ds_len[1] = segs[1].ds_len;
+ }
+}
+
+
+
+static int
+admsw_probe(device_t dev)
+{
+
+ device_set_desc(dev, "ADM5120 Switch Engine");
+ return (0);
+}
+
+#define REG_READ(o) bus_read_4((sc)->mem_res, (o))
+#define REG_WRITE(o,v) bus_write_4((sc)->mem_res, (o),(v))
+
+static void
+admsw_init_bufs(struct admsw_softc *sc)
+{
+ int i;
+ struct admsw_desc *desc;
+
+ for (i = 0; i < ADMSW_NTXHDESC; i++) {
+ if (sc->sc_txhsoft[i].ds_mbuf != NULL) {
+ m_freem(sc->sc_txhsoft[i].ds_mbuf);
+ sc->sc_txhsoft[i].ds_mbuf = NULL;
+ }
+ desc = &sc->sc_txhdescs[i];
+ desc->data = 0;
+ desc->cntl = 0;
+ desc->len = MAC_BUFLEN;
+ desc->status = 0;
+ ADMSW_CDTXHSYNC(sc, i,
+ BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE);
+ }
+ sc->sc_txhdescs[ADMSW_NTXHDESC - 1].data |= ADM5120_DMA_RINGEND;
+ ADMSW_CDTXHSYNC(sc, ADMSW_NTXHDESC - 1,
+ BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE);
+
+ for (i = 0; i < ADMSW_NRXHDESC; i++) {
+ if (sc->sc_rxhsoft[i].ds_mbuf == NULL) {
+ if (admsw_add_rxhbuf(sc, i) != 0)
+ panic("admsw_init_bufs\n");
+ } else
+ ADMSW_INIT_RXHDESC(sc, i);
+ }
+
+ for (i = 0; i < ADMSW_NTXLDESC; i++) {
+ if (sc->sc_txlsoft[i].ds_mbuf != NULL) {
+ m_freem(sc->sc_txlsoft[i].ds_mbuf);
+ sc->sc_txlsoft[i].ds_mbuf = NULL;
+ }
+ desc = &sc->sc_txldescs[i];
+ desc->data = 0;
+ desc->cntl = 0;
+ desc->len = MAC_BUFLEN;
+ desc->status = 0;
+ ADMSW_CDTXLSYNC(sc, i,
+ BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE);
+ }
+ sc->sc_txldescs[ADMSW_NTXLDESC - 1].data |= ADM5120_DMA_RINGEND;
+ ADMSW_CDTXLSYNC(sc, ADMSW_NTXLDESC - 1,
+ BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE);
+
+ for (i = 0; i < ADMSW_NRXLDESC; i++) {
+ if (sc->sc_rxlsoft[i].ds_mbuf == NULL) {
+ if (admsw_add_rxlbuf(sc, i) != 0)
+ panic("admsw_init_bufs\n");
+ } else
+ ADMSW_INIT_RXLDESC(sc, i);
+ }
+
+ REG_WRITE(SEND_HBADDR_REG, ADMSW_CDTXHADDR(sc, 0));
+ REG_WRITE(SEND_LBADDR_REG, ADMSW_CDTXLADDR(sc, 0));
+ REG_WRITE(RECV_HBADDR_REG, ADMSW_CDRXHADDR(sc, 0));
+ REG_WRITE(RECV_LBADDR_REG, ADMSW_CDRXLADDR(sc, 0));
+
+ sc->sc_txfree = ADMSW_NTXLDESC;
+ sc->sc_txnext = 0;
+ sc->sc_txdirty = 0;
+ sc->sc_rxptr = 0;
+}
+
+static void
+admsw_setvlan(struct admsw_softc *sc, char matrix[6])
+{
+ uint32_t i;
+
+ i = matrix[0] + (matrix[1] << 8) + (matrix[2] << 16) + (matrix[3] << 24);
+ REG_WRITE(VLAN_G1_REG, i);
+ i = matrix[4] + (matrix[5] << 8);
+ REG_WRITE(VLAN_G2_REG, i);
+}
+
+static void
+admsw_reset(struct admsw_softc *sc)
+{
+ uint32_t wdog1;
+ int i;
+
+ REG_WRITE(PORT_CONF0_REG,
+ REG_READ(PORT_CONF0_REG) | PORT_CONF0_DP_MASK);
+ REG_WRITE(CPUP_CONF_REG,
+ REG_READ(CPUP_CONF_REG) | CPUP_CONF_DCPUP);
+
+ /* Wait for DMA to complete. Overkill. In 3ms, we can
+ * send at least two entire 1500-byte packets at 10 Mb/s.
+ */
+ DELAY(3000);
+
+ /* The datasheet recommends that we move all PHYs to reset
+ * state prior to software reset.
+ */
+ REG_WRITE(PHY_CNTL2_REG,
+ REG_READ(PHY_CNTL2_REG) & ~PHY_CNTL2_PHYR_MASK);
+
+ /* Reset the switch. */
+ REG_WRITE(ADMSW_SW_RES, 0x1);
+
+ DELAY(100 * 1000);
+
+ REG_WRITE(ADMSW_BOOT_DONE, ADMSW_BOOT_DONE_BO);
+
+ /* begin old code */
+ REG_WRITE(CPUP_CONF_REG,
+ CPUP_CONF_DCPUP | CPUP_CONF_CRCP | CPUP_CONF_DUNP_MASK |
+ CPUP_CONF_DMCP_MASK);
+
+ REG_WRITE(PORT_CONF0_REG, PORT_CONF0_EMCP_MASK | PORT_CONF0_EMBP_MASK);
+
+ REG_WRITE(PHY_CNTL2_REG,
+ REG_READ(PHY_CNTL2_REG) | PHY_CNTL2_ANE_MASK | PHY_CNTL2_PHYR_MASK |
+ PHY_CNTL2_AMDIX_MASK);
+
+ REG_WRITE(PHY_CNTL3_REG, REG_READ(PHY_CNTL3_REG) | PHY_CNTL3_RNT);
+
+ REG_WRITE(ADMSW_INT_MASK, INT_MASK);
+ REG_WRITE(ADMSW_INT_ST, INT_MASK);
+
+ /*
+ * While in DDB, we stop servicing interrupts, RX ring
+ * fills up and when free block counter falls behind FC
+ * threshold, the switch starts to emit 802.3x PAUSE
+ * frames. This can upset peer switches.
+ *
+ * Stop this from happening by disabling FC and D2
+ * thresholds.
+ */
+ REG_WRITE(FC_TH_REG,
+ REG_READ(FC_TH_REG) & ~(FC_TH_FCS_MASK | FC_TH_D2S_MASK));
+
+ admsw_setvlan(sc, vlan_matrix);
+
+ for (i = 0; i < SW_DEVS; i++) {
+ REG_WRITE(MAC_WT1_REG,
+ sc->sc_enaddr[2] |
+ (sc->sc_enaddr[3]<<8) |
+ (sc->sc_enaddr[4]<<16) |
+ ((sc->sc_enaddr[5]+i)<<24));
+ REG_WRITE(MAC_WT0_REG, (i<<MAC_WT0_VLANID_SHIFT) |
+ (sc->sc_enaddr[0]<<16) | (sc->sc_enaddr[1]<<24) |
+ MAC_WT0_WRITE | MAC_WT0_VLANID_EN);
+
+ while (!(REG_READ(MAC_WT0_REG) & MAC_WT0_WRITE_DONE));
+ }
+
+ wdog1 = REG_READ(ADM5120_WDOG1);
+ REG_WRITE(ADM5120_WDOG1, wdog1 & ~ADM5120_WDOG1_WDE);
+}
+
+static int
+admsw_attach(device_t dev)
+{
+ uint8_t enaddr[ETHER_ADDR_LEN];
+ struct admsw_softc *sc = (struct admsw_softc *) device_get_softc(dev);
+ struct ifnet *ifp;
+ int error, i, rid;
+
+ sc->sc_dev = dev;
+ device_printf(dev, "ADM5120 Switch Engine, %d ports\n", SW_DEVS);
+ sc->ndevs = 0;
+
+ /* XXXMIPS: fix it */
+ enaddr[0] = 0x00;
+ enaddr[1] = 0x0C;
+ enaddr[2] = 0x42;
+ enaddr[3] = 0x07;
+ enaddr[4] = 0xB2;
+ enaddr[5] = 0x4E;
+
+ memcpy(sc->sc_enaddr, enaddr, sizeof(sc->sc_enaddr));
+
+ device_printf(sc->sc_dev, "base Ethernet address %s\n",
+ ether_sprintf(enaddr));
+ callout_init(&sc->sc_watchdog, 1);
+
+ rid = 0;
+ if ((sc->mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid,
+ RF_ACTIVE)) == NULL) {
+ device_printf(dev, "unable to allocate memory resource\n");
+ return (ENXIO);
+ }
+
+ /* Hook up the interrupt handler. */
+ rid = 0;
+ if ((sc->irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
+ RF_SHAREABLE | RF_ACTIVE)) == NULL) {
+ device_printf(dev, "unable to allocate IRQ resource\n");
+ return (ENXIO);
+ }
+
+ if ((error = bus_setup_intr(dev, sc->irq_res, INTR_TYPE_NET,
+ admsw_intr, NULL, sc, &sc->sc_ih)) != 0) {
+ device_printf(dev,
+ "WARNING: unable to register interrupt handler\n");
+ return (error);
+ }
+
+ /*
+ * Allocate the control data structures, and create and load the
+ * DMA map for it.
+ */
+ if ((error = bus_dma_tag_create(NULL, 4, 0,
+ BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR,
+ NULL, NULL, sizeof(struct admsw_control_data), 1,
+ sizeof(struct admsw_control_data), 0, NULL, NULL,
+ &sc->sc_control_dmat)) != 0) {
+ device_printf(sc->sc_dev,
+ "unable to create control data DMA map, error = %d\n",
+ error);
+ return (error);
+ }
+
+ if ((error = bus_dmamem_alloc(sc->sc_control_dmat,
+ (void **)&sc->sc_control_data, BUS_DMA_NOWAIT,
+ &sc->sc_cddmamap)) != 0) {
+ device_printf(sc->sc_dev,
+ "unable to allocate control data, error = %d\n", error);
+ return (error);
+ }
+
+ if ((error = bus_dmamap_load(sc->sc_control_dmat, sc->sc_cddmamap,
+ sc->sc_control_data, sizeof(struct admsw_control_data),
+ admsw_dma_map_addr, &sc->sc_cddma, 0)) != 0) {
+ device_printf(sc->sc_dev,
+ "unable to load control data DMA map, error = %d\n", error);
+ return (error);
+ }
+
+ /*
+ * Create the transmit buffer DMA maps.
+ */
+ if ((error = bus_dma_tag_create(NULL, 1, 0,
+ BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR,
+ NULL, NULL, MCLBYTES, 1, MCLBYTES, 0, NULL, NULL,
+ &sc->sc_bufs_dmat)) != 0) {
+ device_printf(sc->sc_dev,
+ "unable to create control data DMA map, error = %d\n",
+ error);
+ return (error);
+ }
+
+ for (i = 0; i < ADMSW_NTXHDESC; i++) {
+ if ((error = bus_dmamap_create(sc->sc_bufs_dmat, 0,
+ &sc->sc_txhsoft[i].ds_dmamap)) != 0) {
+ device_printf(sc->sc_dev,
+ "unable to create txh DMA map %d, error = %d\n",
+ i, error);
+ return (error);
+ }
+ sc->sc_txhsoft[i].ds_mbuf = NULL;
+ }
+
+ for (i = 0; i < ADMSW_NTXLDESC; i++) {
+ if ((error = bus_dmamap_create(sc->sc_bufs_dmat, 0,
+ &sc->sc_txlsoft[i].ds_dmamap)) != 0) {
+ device_printf(sc->sc_dev,
+ "unable to create txl DMA map %d, error = %d\n",
+ i, error);
+ return (error);
+ }
+ sc->sc_txlsoft[i].ds_mbuf = NULL;
+ }
+
+ /*
+ * Create the receive buffer DMA maps.
+ */
+ for (i = 0; i < ADMSW_NRXHDESC; i++) {
+ if ((error = bus_dmamap_create(sc->sc_bufs_dmat, 0,
+ &sc->sc_rxhsoft[i].ds_dmamap)) != 0) {
+ device_printf(sc->sc_dev,
+ "unable to create rxh DMA map %d, error = %d\n",
+ i, error);
+ return (error);
+ }
+ sc->sc_rxhsoft[i].ds_mbuf = NULL;
+ }
+
+ for (i = 0; i < ADMSW_NRXLDESC; i++) {
+ if ((error = bus_dmamap_create(sc->sc_bufs_dmat, 0,
+ &sc->sc_rxlsoft[i].ds_dmamap)) != 0) {
+ device_printf(sc->sc_dev,
+ "unable to create rxl DMA map %d, error = %d\n",
+ i, error);
+ return (error);
+ }
+ sc->sc_rxlsoft[i].ds_mbuf = NULL;
+ }
+
+ admsw_init_bufs(sc);
+ admsw_reset(sc);
+
+ for (i = 0; i < SW_DEVS; i++) {
+ ifmedia_init(&sc->sc_ifmedia[i], 0, admsw_mediachange,
+ admsw_mediastatus);
+ ifmedia_add(&sc->sc_ifmedia[i], IFM_ETHER|IFM_10_T, 0, NULL);
+ ifmedia_add(&sc->sc_ifmedia[i],
+ IFM_ETHER|IFM_10_T|IFM_FDX, 0, NULL);
+ ifmedia_add(&sc->sc_ifmedia[i], IFM_ETHER|IFM_100_TX, 0, NULL);
+ ifmedia_add(&sc->sc_ifmedia[i],
+ IFM_ETHER|IFM_100_TX|IFM_FDX, 0, NULL);
+ ifmedia_add(&sc->sc_ifmedia[i], IFM_ETHER|IFM_AUTO, 0, NULL);
+ ifmedia_set(&sc->sc_ifmedia[i], IFM_ETHER|IFM_AUTO);
+
+ ifp = sc->sc_ifnet[i] = if_alloc(IFT_ETHER);
+
+ /* Setup interface parameters */
+ ifp->if_softc = sc;
+ if_initname(ifp, device_get_name(dev), i);
+ ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
+ ifp->if_ioctl = admsw_ioctl;
+ ifp->if_output = ether_output;
+ ifp->if_start = admsw_start;
+ ifp->if_init = admsw_init;
+ ifp->if_mtu = ETHERMTU;
+ ifp->if_baudrate = IF_Mbps(100);
+ IFQ_SET_MAXLEN(&ifp->if_snd, max(ADMSW_NTXLDESC, ifqmaxlen));
+ ifp->if_snd.ifq_drv_maxlen = max(ADMSW_NTXLDESC, ifqmaxlen);
+ IFQ_SET_READY(&ifp->if_snd);
+ ifp->if_capabilities |= IFCAP_VLAN_MTU;
+
+ /* Attach the interface. */
+ ether_ifattach(ifp, enaddr);
+ enaddr[5]++;
+ }
+
+ /* XXX: admwdog_attach(sc); */
+
+ /* leave interrupts and cpu port disabled */
+ return (0);
+}
+
+static int
+admsw_detach(device_t dev)
+{
+
+ printf("TODO: DETACH\n");
+ return (0);
+}
+
+/*
+ * admsw_shutdown:
+ *
+ * Make sure the interface is stopped at reboot time.
+ */
+static int
+admsw_shutdown(device_t dev)
+{
+ struct admsw_softc *sc;
+ int i;
+
+ sc = device_get_softc(dev);
+ for (i = 0; i < SW_DEVS; i++)
+ admsw_stop(sc->sc_ifnet[i], 1);
+
+ return (0);
+}
+
+/*
+ * admsw_start: [ifnet interface function]
+ *
+ * Start packet transmission on the interface.
+ */
+static void
+admsw_start(struct ifnet *ifp)
+{
+ struct admsw_softc *sc = ifp->if_softc;
+ struct mbuf *m0, *m;
+ struct admsw_descsoft *ds;
+ struct admsw_desc *desc;
+ bus_dmamap_t dmamap;
+ struct ether_header *eh;
+ int error, nexttx, len, i;
+ static int vlan = 0;
+
+ /*
+ * Loop through the send queues, setting up transmit descriptors
+ * unitl we drain the queues, or use up all available transmit
+ * descriptors.
+ */
+ for (;;) {
+ vlan++;
+ if (vlan == SW_DEVS)
+ vlan = 0;
+ i = vlan;
+ for (;;) {
+ ifp = sc->sc_ifnet[i];
+ if ((ifp->if_drv_flags & (IFF_DRV_RUNNING|IFF_DRV_OACTIVE))
+ == IFF_DRV_RUNNING) {
+ /* Grab a packet off the queue. */
+ IF_DEQUEUE(&ifp->if_snd, m0);
+ if (m0 != NULL)
+ break;
+ }
+ i++;
+ if (i == SW_DEVS)
+ i = 0;
+ if (i == vlan)
+ return;
+ }
+ vlan = i;
+ m = NULL;
+
+ /* Get a spare descriptor. */
+ if (sc->sc_txfree == 0) {
+ /* No more slots left; notify upper layer. */
+ ifp->if_drv_flags |= IFF_DRV_OACTIVE;
+ break;
+ }
+ nexttx = sc->sc_txnext;
+ desc = &sc->sc_txldescs[nexttx];
+ ds = &sc->sc_txlsoft[nexttx];
+ dmamap = ds->ds_dmamap;
+
+ /*
+ * Load the DMA map. If this fails, the packet either
+ * didn't fit in the alloted number of segments, or we
+ * were short on resources. In this case, we'll copy
+ * and try again.
+ */
+ if (m0->m_pkthdr.len < ETHER_MIN_LEN ||
+ bus_dmamap_load_mbuf(sc->sc_bufs_dmat, dmamap, m0,
+ admsw_mbuf_map_addr, ds, BUS_DMA_NOWAIT) != 0) {
+ MGETHDR(m, M_NOWAIT, MT_DATA);
+ if (m == NULL) {
+ device_printf(sc->sc_dev,
+ "unable to allocate Tx mbuf\n");
+ break;
+ }
+ if (m0->m_pkthdr.len > MHLEN) {
+ MCLGET(m, M_NOWAIT);
+ if ((m->m_flags & M_EXT) == 0) {
+ device_printf(sc->sc_dev,
+ "unable to allocate Tx cluster\n");
+ m_freem(m);
+ break;
+ }
+ }
+ m->m_pkthdr.csum_flags = m0->m_pkthdr.csum_flags;
+ m_copydata(m0, 0, m0->m_pkthdr.len, mtod(m, void *));
+ m->m_pkthdr.len = m->m_len = m0->m_pkthdr.len;
+ if (m->m_pkthdr.len < ETHER_MIN_LEN) {
+ if (M_TRAILINGSPACE(m) < ETHER_MIN_LEN - m->m_pkthdr.len)
+ panic("admsw_start: M_TRAILINGSPACE\n");
+ memset(mtod(m, uint8_t *) + m->m_pkthdr.len, 0,
+ ETHER_MIN_LEN - ETHER_CRC_LEN - m->m_pkthdr.len);
+ m->m_pkthdr.len = m->m_len = ETHER_MIN_LEN;
+ }
+ error = bus_dmamap_load_mbuf(sc->sc_bufs_dmat,
+ dmamap, m, admsw_mbuf_map_addr, ds, BUS_DMA_NOWAIT);
+ if (error) {
+ device_printf(sc->sc_dev,
+ "unable to load Tx buffer, error = %d\n",
+ error);
+ break;
+ }
+ }
+
+ if (m != NULL) {
+ m_freem(m0);
+ m0 = m;
+ }
+
+ /*
+ * WE ARE NOW COMMITTED TO TRANSMITTING THE PACKET.
+ */
+
+ /* Sync the DMA map. */
+ bus_dmamap_sync(sc->sc_bufs_dmat, dmamap, BUS_DMASYNC_PREWRITE);
+
+ if (ds->ds_nsegs != 1 && ds->ds_nsegs != 2)
+ panic("admsw_start: nsegs == %d\n", ds->ds_nsegs);
+ desc->data = ds->ds_addr[0];
+ desc->len = len = ds->ds_len[0];
+ if (ds->ds_nsegs > 1) {
+ len += ds->ds_len[1];
+ desc->cntl = ds->ds_addr[1] | ADM5120_DMA_BUF2ENABLE;
+ } else
+ desc->cntl = 0;
+ desc->status = (len << ADM5120_DMA_LENSHIFT) | (1 << vlan);
+ eh = mtod(m0, struct ether_header *);
+ if (ntohs(eh->ether_type) == ETHERTYPE_IP &&
+ m0->m_pkthdr.csum_flags & CSUM_IP)
+ desc->status |= ADM5120_DMA_CSUM;
+ if (nexttx == ADMSW_NTXLDESC - 1)
+ desc->data |= ADM5120_DMA_RINGEND;
+ desc->data |= ADM5120_DMA_OWN;
+
+ /* Sync the descriptor. */
+ ADMSW_CDTXLSYNC(sc, nexttx,
+ BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE);
+
+ REG_WRITE(SEND_TRIG_REG, 1);
+ /* printf("send slot %d\n",nexttx); */
+
+ /*
+ * Store a pointer to the packet so we can free it later.
+ */
+ ds->ds_mbuf = m0;
+
+ /* Advance the Tx pointer. */
+ sc->sc_txfree--;
+ sc->sc_txnext = ADMSW_NEXTTXL(nexttx);
+
+ /* Pass the packet to any BPF listeners. */
+ BPF_MTAP(ifp, m0);
+
+ /* Set a watchdog timer in case the chip flakes out. */
+ sc->sc_timer = 5;
+ }
+}
+
+/*
+ * admsw_watchdog: [ifnet interface function]
+ *
+ * Watchdog timer handler.
+ */
+static void
+admsw_watchdog(void *arg)
+{
+ struct admsw_softc *sc = arg;
+ struct ifnet *ifp;
+ int vlan;
+
+ callout_reset(&sc->sc_watchdog, hz, admsw_watchdog, sc);
+ if (sc->sc_timer == 0 || --sc->sc_timer > 0)
+ return;
+
+ /* Check if an interrupt was lost. */
+ if (sc->sc_txfree == ADMSW_NTXLDESC) {
+ device_printf(sc->sc_dev, "watchdog false alarm\n");
+ return;
+ }
+ if (sc->sc_timer != 0)
+ device_printf(sc->sc_dev, "watchdog timer is %d!\n",
+ sc->sc_timer);
+ admsw_txintr(sc, 0);
+ if (sc->sc_txfree == ADMSW_NTXLDESC) {
+ device_printf(sc->sc_dev, "tx IRQ lost (queue empty)\n");
+ return;
+ }
+ if (sc->sc_timer != 0) {
+ device_printf(sc->sc_dev, "tx IRQ lost (timer recharged)\n");
+ return;
+ }
+
+ device_printf(sc->sc_dev, "device timeout, txfree = %d\n",
+ sc->sc_txfree);
+ for (vlan = 0; vlan < SW_DEVS; vlan++)
+ admsw_stop(sc->sc_ifnet[vlan], 0);
+ admsw_init(sc);
+
+ ifp = sc->sc_ifnet[0];
+
+ /* Try to get more packets going. */
+ admsw_start(ifp);
+}
+
+/*
+ * admsw_ioctl: [ifnet interface function]
+ *
+ * Handle control requests from the operator.
+ */
+static int
+admsw_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data)
+{
+ struct admsw_softc *sc = ifp->if_softc;
+ struct ifdrv *ifd;
+ int error, port;
+
+ ADMSW_LOCK(sc);
+
+ switch (cmd) {
+ case SIOCSIFMEDIA:
+ case SIOCGIFMEDIA:
+ port = 0;
+ while(port < SW_DEVS)
+ if(ifp == sc->sc_ifnet[port])
+ break;
+ else
+ port++;
+ if (port >= SW_DEVS)
+ error = EOPNOTSUPP;
+ else
+ error = ifmedia_ioctl(ifp, (struct ifreq *)data,
+ &sc->sc_ifmedia[port], cmd);
+ break;
+
+ case SIOCGDRVSPEC:
+ case SIOCSDRVSPEC:
+ ifd = (struct ifdrv *) data;
+ if (ifd->ifd_cmd != 0 || ifd->ifd_len != sizeof(vlan_matrix)) {
+ error = EINVAL;
+ break;
+ }
+ if (cmd == SIOCGDRVSPEC) {
+ error = copyout(vlan_matrix, ifd->ifd_data,
+ sizeof(vlan_matrix));
+ } else {
+ error = copyin(ifd->ifd_data, vlan_matrix,
+ sizeof(vlan_matrix));
+ admsw_setvlan(sc, vlan_matrix);
+ }
+ break;
+
+ default:
+ error = ether_ioctl(ifp, cmd, data);
+ if (error == ENETRESET) {
+ /*
+ * Multicast list has changed; set the hardware filter
+ * accordingly.
+ */
+ admsw_set_filter(sc);
+ error = 0;
+ }
+ break;
+ }
+
+ /* Try to get more packets going. */
+ admsw_start(ifp);
+
+ ADMSW_UNLOCK(sc);
+ return (error);
+}
+
+
+/*
+ * admsw_intr:
+ *
+ * Interrupt service routine.
+ */
+static int
+admsw_intr(void *arg)
+{
+ struct admsw_softc *sc = arg;
+ uint32_t pending;
+
+ pending = REG_READ(ADMSW_INT_ST);
+ REG_WRITE(ADMSW_INT_ST, pending);
+
+ if (sc->ndevs == 0)
+ return (FILTER_STRAY);
+
+ if ((pending & ADMSW_INTR_RHD) != 0)
+ admsw_rxintr(sc, 1);
+
+ if ((pending & ADMSW_INTR_RLD) != 0)
+ admsw_rxintr(sc, 0);
+
+ if ((pending & ADMSW_INTR_SHD) != 0)
+ admsw_txintr(sc, 1);
+
+ if ((pending & ADMSW_INTR_SLD) != 0)
+ admsw_txintr(sc, 0);
+
+ return (FILTER_HANDLED);
+}
+
+/*
+ * admsw_txintr:
+ *
+ * Helper; handle transmit interrupts.
+ */
+static void
+admsw_txintr(struct admsw_softc *sc, int prio)
+{
+ struct ifnet *ifp;
+ struct admsw_desc *desc;
+ struct admsw_descsoft *ds;
+ int i, vlan;
+ int gotone = 0;
+
+ /* printf("txintr: txdirty: %d, txfree: %d\n",sc->sc_txdirty, sc->sc_txfree); */
+ for (i = sc->sc_txdirty; sc->sc_txfree != ADMSW_NTXLDESC;
+ i = ADMSW_NEXTTXL(i)) {
+
+ ADMSW_CDTXLSYNC(sc, i,
+ BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE);
+
+ desc = &sc->sc_txldescs[i];
+ ds = &sc->sc_txlsoft[i];
+ if (desc->data & ADM5120_DMA_OWN) {
+ ADMSW_CDTXLSYNC(sc, i,
+ BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE);
+ break;
+ }
+
+ bus_dmamap_sync(sc->sc_bufs_dmat, ds->ds_dmamap,
+ BUS_DMASYNC_POSTWRITE);
+ bus_dmamap_unload(sc->sc_bufs_dmat, ds->ds_dmamap);
+ m_freem(ds->ds_mbuf);
+ ds->ds_mbuf = NULL;
+
+ vlan = ffs(desc->status & 0x3f) - 1;
+ if (vlan < 0 || vlan >= SW_DEVS)
+ panic("admsw_txintr: bad vlan\n");
+ ifp = sc->sc_ifnet[vlan];
+ gotone = 1;
+ /* printf("clear tx slot %d\n",i); */
+
+ ifp->if_opackets++;
+
+ sc->sc_txfree++;
+ }
+
+ if (gotone) {
+ sc->sc_txdirty = i;
+ for (vlan = 0; vlan < SW_DEVS; vlan++)
+ sc->sc_ifnet[vlan]->if_drv_flags &= ~IFF_DRV_OACTIVE;
+
+ ifp = sc->sc_ifnet[0];
+
+ /* Try to queue more packets. */
+ admsw_start(ifp);
+
+ /*
+ * If there are no more pending transmissions,
+ * cancel the watchdog timer.
+ */
+ if (sc->sc_txfree == ADMSW_NTXLDESC)
+ sc->sc_timer = 0;
+
+ }
+
+ /* printf("txintr end: txdirty: %d, txfree: %d\n",sc->sc_txdirty, sc->sc_txfree); */
+}
+
+/*
+ * admsw_rxintr:
+ *
+ * Helper; handle receive interrupts.
+ */
+static void
+admsw_rxintr(struct admsw_softc *sc, int high)
+{
+ struct ifnet *ifp;
+ struct admsw_descsoft *ds;
+ struct mbuf *m;
+ uint32_t stat;
+ int i, len, port, vlan;
+
+ /* printf("rxintr\n"); */
+
+ if (high)
+ panic("admsw_rxintr: high priority packet\n");
+
+#if 1
+ ADMSW_CDRXLSYNC(sc, sc->sc_rxptr,
+ BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE);
+ if ((sc->sc_rxldescs[sc->sc_rxptr].data & ADM5120_DMA_OWN) == 0)
+ ADMSW_CDRXLSYNC(sc, sc->sc_rxptr,
+ BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE);
+ else {
+ i = sc->sc_rxptr;
+ do {
+ ADMSW_CDRXLSYNC(sc, i,
+ BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE);
+ i = ADMSW_NEXTRXL(i);
+ /* the ring is empty, just return. */
+ if (i == sc->sc_rxptr)
+ return;
+ ADMSW_CDRXLSYNC(sc, i,
+ BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE);
+ } while (sc->sc_rxldescs[i].data & ADM5120_DMA_OWN);
+
+ ADMSW_CDRXLSYNC(sc, i,
+ BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE);
+
+ ADMSW_CDRXLSYNC(sc, sc->sc_rxptr,
+ BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE);
+
+ if ((sc->sc_rxldescs[sc->sc_rxptr].data & ADM5120_DMA_OWN) == 0)
+ ADMSW_CDRXLSYNC(sc, sc->sc_rxptr,
+ BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE);
+ else {
+ ADMSW_CDRXLSYNC(sc, sc->sc_rxptr,
+ BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE);
+ /* We've fallen behind the chip: catch it. */
+#if 0
+ device_printf(sc->sc_dev,
+ "RX ring resync, base=%x, work=%x, %d -> %d\n",
+ REG_READ(RECV_LBADDR_REG),
+ REG_READ(RECV_LWADDR_REG), sc->sc_rxptr, i);
+#endif
+ sc->sc_rxptr = i;
+ /* ADMSW_EVCNT_INCR(&sc->sc_ev_rxsync); */
+ }
+ }
+#endif
+ for (i = sc->sc_rxptr;; i = ADMSW_NEXTRXL(i)) {
+ ds = &sc->sc_rxlsoft[i];
+
+ ADMSW_CDRXLSYNC(sc, i,
+ BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE);
+
+ if (sc->sc_rxldescs[i].data & ADM5120_DMA_OWN) {
+ ADMSW_CDRXLSYNC(sc, i,
+ BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE);
+ break;
+ }
+
+ /* printf("process slot %d\n",i); */
+
+ bus_dmamap_sync(sc->sc_bufs_dmat, ds->ds_dmamap,
+ BUS_DMASYNC_POSTREAD);
+
+ stat = sc->sc_rxldescs[i].status;
+ len = (stat & ADM5120_DMA_LEN) >> ADM5120_DMA_LENSHIFT;
+ len -= ETHER_CRC_LEN;
+ port = (stat & ADM5120_DMA_PORTID) >> ADM5120_DMA_PORTSHIFT;
+
+ for (vlan = 0; vlan < SW_DEVS; vlan++)
+ if ((1 << port) & vlan_matrix[vlan])
+ break;
+
+ if (vlan == SW_DEVS)
+ vlan = 0;
+
+ ifp = sc->sc_ifnet[vlan];
+
+ m = ds->ds_mbuf;
+ if (admsw_add_rxlbuf(sc, i) != 0) {
+ ifp->if_ierrors++;
+ ADMSW_INIT_RXLDESC(sc, i);
+ bus_dmamap_sync(sc->sc_bufs_dmat, ds->ds_dmamap,
+ BUS_DMASYNC_PREREAD);
+ continue;
+ }
+
+ m->m_pkthdr.rcvif = ifp;
+ m->m_pkthdr.len = m->m_len = len;
+ if ((stat & ADM5120_DMA_TYPE) == ADM5120_DMA_TYPE_IP) {
+ m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED;
+ if (!(stat & ADM5120_DMA_CSUMFAIL))
+ m->m_pkthdr.csum_flags |= CSUM_IP_VALID;
+ }
+
+ BPF_MTAP(ifp, m);
+
+ /* Pass it on. */
+ (*ifp->if_input)(ifp, m);
+ ifp->if_ipackets++;
+ }
+
+ /* Update the receive pointer. */
+ sc->sc_rxptr = i;
+}
+
+/*
+ * admsw_init: [ifnet interface function]
+ *
+ * Initialize the interface.
+ */
+static void
+admsw_init(void *xsc)
+{
+ struct admsw_softc *sc = xsc;
+ struct ifnet *ifp;
+ int i;
+
+ for (i = 0; i < SW_DEVS; i++) {
+ ifp = sc->sc_ifnet[i];
+ if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) {
+ if (sc->ndevs == 0) {
+ admsw_init_bufs(sc);
+ admsw_reset(sc);
+ REG_WRITE(CPUP_CONF_REG,
+ CPUP_CONF_CRCP | CPUP_CONF_DUNP_MASK |
+ CPUP_CONF_DMCP_MASK);
+ /* clear all pending interrupts */
+ REG_WRITE(ADMSW_INT_ST, INT_MASK);
+
+ /* enable needed interrupts */
+ REG_WRITE(ADMSW_INT_MASK,
+ REG_READ(ADMSW_INT_MASK) &
+ ~(ADMSW_INTR_SHD | ADMSW_INTR_SLD |
+ ADMSW_INTR_RHD | ADMSW_INTR_RLD |
+ ADMSW_INTR_HDF | ADMSW_INTR_LDF));
+
+ callout_reset(&sc->sc_watchdog, hz,
+ admsw_watchdog, sc);
+ }
+ sc->ndevs++;
+ }
+
+
+ /* mark iface as running */
+ ifp->if_drv_flags |= IFF_DRV_RUNNING;
+ ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
+ }
+
+ /* Set the receive filter. */
+ admsw_set_filter(sc);
+}
+
+/*
+ * admsw_stop: [ifnet interface function]
+ *
+ * Stop transmission on the interface.
+ */
+static void
+admsw_stop(struct ifnet *ifp, int disable)
+{
+ struct admsw_softc *sc = ifp->if_softc;
+
+ if (!(ifp->if_drv_flags & IFF_DRV_RUNNING))
+ return;
+
+ if (--sc->ndevs == 0) {
+ /* printf("debug: de-initializing hardware\n"); */
+
+ /* disable cpu port */
+ REG_WRITE(CPUP_CONF_REG,
+ CPUP_CONF_DCPUP | CPUP_CONF_CRCP |
+ CPUP_CONF_DUNP_MASK | CPUP_CONF_DMCP_MASK);
+
+ /* XXX We should disable, then clear? --dyoung */
+ /* clear all pending interrupts */
+ REG_WRITE(ADMSW_INT_ST, INT_MASK);
+
+ /* disable interrupts */
+ REG_WRITE(ADMSW_INT_MASK, INT_MASK);
+
+ /* Cancel the watchdog timer. */
+ sc->sc_timer = 0;
+ callout_stop(&sc->sc_watchdog);
+ }
+
+ /* Mark the interface as down. */
+ ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE);
+
+ return;
+}
+
+/*
+ * admsw_set_filter:
+ *
+ * Set up the receive filter.
+ */
+static void
+admsw_set_filter(struct admsw_softc *sc)
+{
+ int i;
+ uint32_t allmc, anymc, conf, promisc;
+ struct ifnet *ifp;
+ struct ifmultiaddr *ifma;
+
+ /* Find which ports should be operated in promisc mode. */
+ allmc = anymc = promisc = 0;
+ for (i = 0; i < SW_DEVS; i++) {
+ ifp = sc->sc_ifnet[i];
+ if (ifp->if_flags & IFF_PROMISC)
+ promisc |= vlan_matrix[i];
+
+ ifp->if_flags &= ~IFF_ALLMULTI;
+
+ if_maddr_rlock(ifp);
+ TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link)
+ {
+ if (ifma->ifma_addr->sa_family != AF_LINK)
+ continue;
+
+ anymc |= vlan_matrix[i];
+ }
+ if_maddr_runlock(ifp);
+ }
+
+ conf = REG_READ(CPUP_CONF_REG);
+ /* 1 Disable forwarding of unknown & multicast packets to
+ * CPU on all ports.
+ * 2 Enable forwarding of unknown & multicast packets to
+ * CPU on ports where IFF_PROMISC or IFF_ALLMULTI is set.
+ */
+ conf |= CPUP_CONF_DUNP_MASK | CPUP_CONF_DMCP_MASK;
+ /* Enable forwarding of unknown packets to CPU on selected ports. */
+ conf ^= ((promisc << CPUP_CONF_DUNP_SHIFT) & CPUP_CONF_DUNP_MASK);
+ conf ^= ((allmc << CPUP_CONF_DMCP_SHIFT) & CPUP_CONF_DMCP_MASK);
+ conf ^= ((anymc << CPUP_CONF_DMCP_SHIFT) & CPUP_CONF_DMCP_MASK);
+ REG_WRITE(CPUP_CONF_REG, conf);
+}
+
+/*
+ * admsw_add_rxbuf:
+ *
+ * Add a receive buffer to the indicated descriptor.
+ */
+int
+admsw_add_rxbuf(struct admsw_softc *sc, int idx, int high)
+{
+ struct admsw_descsoft *ds;
+ struct mbuf *m;
+ int error;
+
+ if (high)
+ ds = &sc->sc_rxhsoft[idx];
+ else
+ ds = &sc->sc_rxlsoft[idx];
+
+ MGETHDR(m, M_NOWAIT, MT_DATA);
+ if (m == NULL)
+ return (ENOBUFS);
+
+ MCLGET(m, M_NOWAIT);
+ if ((m->m_flags & M_EXT) == 0) {
+ m_freem(m);
+ return (ENOBUFS);
+ }
+
+ if (ds->ds_mbuf != NULL)
+ bus_dmamap_unload(sc->sc_bufs_dmat, ds->ds_dmamap);
+
+ ds->ds_mbuf = m;
+
+ error = bus_dmamap_load(sc->sc_bufs_dmat, ds->ds_dmamap,
+ m->m_ext.ext_buf, m->m_ext.ext_size, admsw_rxbuf_map_addr,
+ ds, BUS_DMA_NOWAIT);
+ if (error) {
+ device_printf(sc->sc_dev,
+ "can't load rx DMA map %d, error = %d\n", idx, error);
+ panic("admsw_add_rxbuf"); /* XXX */
+ }
+
+ bus_dmamap_sync(sc->sc_bufs_dmat, ds->ds_dmamap, BUS_DMASYNC_PREREAD);
+
+ if (high)
+ ADMSW_INIT_RXHDESC(sc, idx);
+ else
+ ADMSW_INIT_RXLDESC(sc, idx);
+
+ return (0);
+}
+
+int
+admsw_mediachange(struct ifnet *ifp)
+{
+ struct admsw_softc *sc = ifp->if_softc;
+ int port = 0;
+ struct ifmedia *ifm;
+ int old, new, val;
+
+ while(port < SW_DEVS) {
+ if(ifp == sc->sc_ifnet[port])
+ break;
+ else
+ port++;
+ }
+
+ ifm = &sc->sc_ifmedia[port];
+
+ if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER)
+ return (EINVAL);
+
+ if (IFM_SUBTYPE(ifm->ifm_media) == IFM_AUTO) {
+ val = PHY_CNTL2_AUTONEG|PHY_CNTL2_100M|PHY_CNTL2_FDX;
+ } else if (IFM_SUBTYPE(ifm->ifm_media) == IFM_100_TX) {
+ if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX)
+ val = PHY_CNTL2_100M|PHY_CNTL2_FDX;
+ else
+ val = PHY_CNTL2_100M;
+ } else if (IFM_SUBTYPE(ifm->ifm_media) == IFM_10_T) {
+ if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX)
+ val = PHY_CNTL2_FDX;
+ else
+ val = 0;
+ } else
+ return (EINVAL);
+
+ old = REG_READ(PHY_CNTL2_REG);
+ new = old & ~((PHY_CNTL2_AUTONEG|PHY_CNTL2_100M|PHY_CNTL2_FDX) << port);
+ new |= (val << port);
+
+ if (new != old)
+ REG_WRITE(PHY_CNTL2_REG, new);
+
+ return (0);
+}
+
+void
+admsw_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr)
+{
+ struct admsw_softc *sc = ifp->if_softc;
+ int port = 0;
+ int status;
+
+ while(port < SW_DEVS) {
+ if(ifp == sc->sc_ifnet[port])
+ break;
+ else
+ port++;
+ }
+
+ ifmr->ifm_status = IFM_AVALID;
+ ifmr->ifm_active = IFM_ETHER;
+
+ status = REG_READ(PHY_ST_REG) >> port;
+
+ if ((status & PHY_ST_LINKUP) == 0) {
+ ifmr->ifm_active |= IFM_NONE;
+ return;
+ }
+
+ ifmr->ifm_status |= IFM_ACTIVE;
+ ifmr->ifm_active |= (status & PHY_ST_100M) ? IFM_100_TX : IFM_10_T;
+ if (status & PHY_ST_FDX)
+ ifmr->ifm_active |= IFM_FDX;
+}
+
+static device_method_t admsw_methods[] = {
+ /* Device interface */
+ DEVMETHOD(device_probe, admsw_probe),
+ DEVMETHOD(device_attach, admsw_attach),
+ DEVMETHOD(device_detach, admsw_detach),
+ DEVMETHOD(device_shutdown, admsw_shutdown),
+
+ { 0, 0 }
+};
+
+static devclass_t admsw_devclass;
+
+static driver_t admsw_driver = {
+ "admsw",
+ admsw_methods,
+ sizeof(struct admsw_softc),
+};
+
+DRIVER_MODULE(admsw, obio, admsw_driver, admsw_devclass, 0, 0);
+MODULE_DEPEND(admsw, ether, 1, 1, 1);
Property changes on: trunk/sys/mips/adm5120/if_admsw.c
___________________________________________________________________
Added: svn:eol-style
## -0,0 +1 ##
+native
\ No newline at end of property
Added: svn:keywords
## -0,0 +1 ##
+MidnightBSD=%H
\ No newline at end of property
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## -0,0 +1 ##
+text/plain
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Added: trunk/sys/mips/adm5120/if_admswreg.h
===================================================================
--- trunk/sys/mips/adm5120/if_admswreg.h (rev 0)
+++ trunk/sys/mips/adm5120/if_admswreg.h 2018-05-26 21:55:02 UTC (rev 9987)
@@ -0,0 +1,679 @@
+/* $MidnightBSD$ */
+/* $NetBSD: if_admswreg.h,v 1.1 2007/03/20 08:52:02 dyoung Exp $ */
+
+/*-
+ * Copyright (c) 2007 Ruslan Ermilov and Vsevolod Lobko.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or
+ * without modification, are permitted provided that the following
+ * conditions are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above
+ * copyright notice, this list of conditions and the following
+ * disclaimer in the documentation and/or other materials provided
+ * with the distribution.
+ * 3. The names of the authors may not be used to endorse or promote
+ * products derived from this software without specific prior
+ * written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHORS ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
+ * PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHORS
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY,
+ * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
+ * TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
+ * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ *
+ * $FreeBSD: stable/10/sys/mips/adm5120/if_admswreg.h 202175 2010-01-12 21:36:08Z imp $
+ */
+#ifndef _IF_ADMSWREG_H_
+#define _IF_ADMSWREG_H_
+
+#define ADMSW_BOOT_DONE 0x0008
+#define ADMSW_BOOT_DONE_BO __BIT(0)
+#define ADMSW_SW_RES 0x000c
+#define ADMSW_SW_RES_SWR __BITS(31, 0)
+#define ADMSW_INT_ST 0x00b0
+#define ADMSW_INT_MASK 0x00b4
+
+#define ADMSW_INTR_RSVD __BITS(31, 25)
+#define ADMSW_INTR_CPUH __BIT(24)
+#define ADMSW_INTR_SDE __BIT(23)
+#define ADMSW_INTR_RDE __BIT(22)
+#define ADMSW_INTR_W1TE __BIT(21)
+#define ADMSW_INTR_W0TE __BIT(20)
+#define ADMSW_INTR_MI __BIT(19)
+#define ADMSW_INTR_PSC __BIT(18)
+#define ADMSW_INTR_BCS __BIT(16)
+#define ADMSW_INTR_MD __BIT(15)
+#define ADMSW_INTR_GQF __BIT(14)
+#define ADMSW_INTR_CPQ __BIT(13)
+#define ADMSW_INTR_P5QF __BIT(11)
+#define ADMSW_INTR_P4QF __BIT(10)
+#define ADMSW_INTR_P3QF __BIT(9)
+#define ADMSW_INTR_P2QF __BIT(8)
+#define ADMSW_INTR_P1QF __BIT(7)
+#define ADMSW_INTR_P0QF __BIT(6)
+#define ADMSW_INTR_LDF __BIT(5)
+#define ADMSW_INTR_HDF __BIT(4)
+#define ADMSW_INTR_RLD __BIT(3)
+#define ADMSW_INTR_RHD __BIT(2)
+#define ADMSW_INTR_SLD __BIT(1)
+#define ADMSW_INTR_SHD __BIT(0)
+
+#define ADMSW_INT_FMT \
+ "\x10"\
+ "\x01SHD"\
+ "\x02SLD"\
+ "\x03RHD"\
+ "\x04RLD"\
+ "\x05HDF"\
+ "\x06LDF"\
+ "\x07P0QF"\
+ "\x08P1QF"\
+ "\x09P2QF"\
+ "\x0aP3QF"\
+ "\x0bP4QF"\
+ "\x0cP5QF"\
+ "\x0e"\
+ "CPQ"\
+ "\x0fGQF"\
+ "\x10MD"\
+ "\x11"\
+ "BCS"\
+ "\x13PSC"\
+ "\x14MI"\
+ "\x15W0TE"\
+ "\x16W1TE"\
+ "\x17RDE"\
+ "\x18SDE"\
+ "\x19"\
+ "CPUH"
+
+#define CODE_REG 0x0000
+#define SFTREST_REG 0x0004
+#define BOOT_DONE_REG 0x0008
+#define GLOBAL_ST_REG 0x0010
+#define PHY_ST_REG 0x0014
+#define PHY_ST_LINKUP (1 << 0)
+#define PHY_ST_100M (1 << 8)
+#define PHY_ST_FDX (1 << 16)
+#define PORT_ST_REG 0x0018
+#define MEM_CONTROL_REG 0x001C
+#define SW_CONF_REG 0x0020
+
+#define CPUP_CONF_REG 0x0024
+#define CPUP_CONF_DCPUP 0x00000001
+#define CPUP_CONF_CRCP 0x00000002
+#define CPUP_CONF_BTM 0x00000004
+#define CPUP_CONF_DUNP_SHIFT 9
+#define CPUP_CONF_DUNP_MASK (0x3F << CPUP_CONF_DUNP_SHIFT)
+#define CPUP_CONF_DMCP_SHIFT 16
+#define CPUP_CONF_DMCP_MASK (0x3F << CPUP_CONF_DMCP_SHIFT)
+#define CPUP_CONF_DBCP_SHIFT 24
+#define CPUP_CONF_DBCP_MASK (0x3F << CPUP_CONF_DBCP_SHIFT)
+
+#define PORT_CONF0_REG 0x0028
+#define PORT_CONF0_DP_MASK 0x0000003F
+#define PORT_CONF0_EMCP_MASK 0x00003F00
+#define PORT_CONF0_EMCP_SHIFT 8
+#define PORT_CONF0_EMBP_MASK 0x003F0000
+#define PORT_CONF0_EMBP_SHIFT 16
+#define PORT_CONF1_REG 0x002C
+#define PORT_CONF2_REG 0x0030
+
+#define VLAN_G1_REG 0x0040
+#define VLAN_G2_REG 0x0044
+#define SEND_TRIG_REG 0x0048
+#define SRCH_CMD_REG 0x004C
+#define ADDR_ST0_REG 0x0050
+#define ADDR_ST1_REG 0x0054
+#define MAC_WT0_REG 0x0058
+#define MAC_WT0_WRITE 0x00000001
+#define MAC_WT0_WRITE_DONE 0x00000002
+#define MAC_WT0_FILTER_EN 0x00000004
+#define MAC_WT0_VLANID_SHIFT 3
+#define MAC_WT0_VLANID_MASK 0x00000038
+#define MAC_WT0_VLANID_EN 0x00000040
+#define MAC_WT0_PORTMAP_MASK 0x00001F80
+#define MAC_WT0_PORTMAP_SHIFT 7
+#define MAC_WT0_AGE_MASK (0x7 << 13)
+#define MAC_WT0_AGE_STATIC (0x7 << 13)
+#define MAC_WT0_AGE_VALID (0x1 << 13)
+#define MAC_WT0_AGE_EMPTY 0
+#define MAC_WT1_REG 0x005C
+#define BW_CNTL0_REG 0x0060
+#define BW_CNTL1_REG 0x0064
+#define PHY_CNTL0_REG 0x0068
+#define PHY_CNTL1_REG 0x006C
+#define FC_TH_REG 0x0070
+#define FC_TH_FCS_MASK 0x01FF0000
+#define FC_TH_D2R_MASK 0x0000FF00
+#define FC_TH_D2S_MASK 0x000000FF
+#define ADJ_PORT_TH_REG 0x0074
+#define PORT_TH_REG 0x0078
+#define PHY_CNTL2_REG 0x007C
+#define PHY_CNTL2_AUTONEG (1 << 0)
+#define PHY_CNTL2_ANE_MASK 0x0000001F
+#define PHY_CNTL2_SC_MASK 0x000003E0
+#define PHY_CNTL2_SC_SHIFT 5
+#define PHY_CNTL2_100M (1 << PHY_CNTL2_SC_SHIFT)
+#define PHY_CNTL2_DC_MASK 0x00007C00
+#define PHY_CNTL2_DC_SHIFT 10
+#define PHY_CNTL2_FDX (1 << PHY_CNTL2_DC_SHIFT)
+#define PHY_CNTL2_RFCV_MASK 0x000F8000
+#define PHY_CNTL2_RFCV_SHIFT 15
+#define PHY_CNTL2_PHYR_MASK 0x01F00000
+#define PHY_CNTL2_PHYR_SHIFT 20
+#define PHY_CNTL2_AMDIX_MASK 0x3E000000
+#define PHY_CNTL2_AMDIX_SHIFT 25
+#define PHY_CNTL2_RMAE 0x40000000
+#define PHY_CNTL3_REG 0x0080
+#define PHY_CNTL3_RNT 0x00000400
+
+#define PRI_CNTL_REG 0x0084
+#define VLAN_PRI_REG 0x0088
+#define TOS_EN_REG 0x008C
+#define TOS_MAP0_REG 0x0090
+#define TOS_MAP1_REG 0x0094
+#define CUSTOM_PRI1_REG 0x0098
+#define CUSTOM_PRI2_REG 0x009C
+
+#define EMPTY_CNT_REG 0x00A4
+#define PORT_CNT_SEL_REG 0x00A8
+#define PORT_CNT_REG 0x00AC
+
+#define INT_MASK 0x1FDEFFF
+
+#define GPIO_CONF0_REG 0x00B8
+#define GPIO_CONF2_REG 0x00BC
+
+#define SWAP_IN_REG 0x00C8
+#define SWAP_OUT_REG 0x00CC
+
+#define SEND_HBADDR_REG 0x00D0
+#define SEND_LBADDR_REG 0x00D4
+#define RECV_HBADDR_REG 0x00D8
+#define RECV_LBADDR_REG 0x00DC
+#define SEND_HWADDR_REG 0x00E0
+#define SEND_LWADDR_REG 0x00E4
+#define RECV_HWADDR_REG 0x00E8
+#define RECV_LWADDR_REG 0x00EC
+
+#define TIMER_INT_REG 0x00F0
+#define TIMER_REG 0x00F4
+
+#define PORT0_LED_REG 0x0100
+#define PORT1_LED_REG 0x0104
+#define PORT2_LED_REG 0x0108
+#define PORT3_LED_REG 0x010c
+#define PORT4_LED_REG 0x0110
+
+/* Hardware descriptor format */
+struct admsw_desc {
+ volatile uint32_t data;
+ volatile uint32_t cntl;
+ volatile uint32_t len;
+ volatile uint32_t status;
+} __attribute__((__packed__, __aligned__(4)));
+
+#define ADM5120_DMA_MASK 0x01ffffff
+#define ADM5120_DMA_OWN 0x80000000 /* buffer owner */
+#define ADM5120_DMA_RINGEND 0x10000000 /* Last in DMA ring */
+#define ADM5120_DMA_BUF2ENABLE 0x80000000
+
+#define ADM5120_DMA_PORTID 0x00007000
+#define ADM5120_DMA_PORTSHIFT 12
+#define ADM5120_DMA_LEN 0x07ff0000
+#define ADM5120_DMA_LENSHIFT 16
+#define ADM5120_DMA_TYPE 0x00000003
+#define ADM5120_DMA_TYPE_IP 0x00000000
+#define ADM5120_DMA_TYPE_PPPOE 0x00000001
+#define ADM5120_DMA_CSUM 0x80000000
+#define ADM5120_DMA_CSUMFAIL 0x00000008
+
+#define SW_DEVS 6
+
+#if 0
+/* CODE_REG */
+#define CODE_ID_MASK 0x00FFFF
+#define CODE_ADM5120_ID 0x5120
+
+#define CODE_REV_MASK 0x0F0000
+#define CODE_REV_SHIFT 16
+#define CODE_REV_ADM5120_0 0x8
+
+#define CODE_CLK_MASK 0x300000
+#define CODE_CLK_SHIFT 20
+
+#define CPU_CLK_175MHZ 0x0
+#define CPU_CLK_200MHZ 0x1
+#define CPU_CLK_225MHZ 0x2
+#define CPU_CLK_250MHZ 0x3
+
+#define CPU_SPEED_175M (175000000/2)
+#define CPU_SPEED_200M (200000000/2)
+#define CPU_SPEED_225M (225000000/2)
+#define CPU_SPEED_250M (250000000/2)
+
+#define CPU_NAND_BOOT 0x01000000
+#define CPU_DCACHE_2K_WAY (0x1 << 25)
+#define CPU_DCACHE_2WAY (0x1 << 26)
+#define CPU_ICACHE_2K_WAY (0x1 << 27)
+#define CPU_ICACHE_2WAY (0x1 << 28)
+
+#define CPU_GMII_SUPPORT 0x20000000
+
+#define CPU_PQFP_MODE (0x1 << 29)
+
+#define CPU_CACHE_LINE_SIZE 16
+
+/* SftRest_REG */
+#define SOFTWARE_RESET 0x1
+
+/* Boot_done_REG */
+#define BOOT_DONE 0x1
+
+/* SWReset_REG */
+#define SWITCH_RESET 0x1
+
+/* Global_St_REG */
+#define DATA_BUF_BIST_FAILED (0x1 << 0)
+#define LINK_TAB_BIST_FAILED (0x1 << 1)
+#define MC_TAB_BIST_FAILED (0x1 << 2)
+#define ADDR_TAB_BIST_FAILED (0x1 << 3)
+#define DCACHE_D_FAILED (0x3 << 4)
+#define DCACHE_T_FAILED (0x1 << 6)
+#define ICACHE_D_FAILED (0x3 << 7)
+#define ICACHE_T_FAILED (0x1 << 9)
+#define BIST_FAILED_MASK 0x03FF
+
+#define ALLMEM_TEST_DONE (0x1 << 10)
+
+#define SKIP_BLK_CNT_MASK 0x1FF000
+#define SKIP_BLK_CNT_SHIFT 12
+
+
+/* PHY_st_REG */
+#define PORT_LINK_MASK 0x0000001F
+#define PORT_MII_LINKFAIL 0x00000020
+#define PORT_SPEED_MASK 0x00001F00
+
+#define PORT_GMII_SPD_MASK 0x00006000
+#define PORT_GMII_SPD_10M 0
+#define PORT_GMII_SPD_100M 0x00002000
+#define PORT_GMII_SPD_1000M 0x00004000
+
+#define PORT_DUPLEX_MASK 0x003F0000
+#define PORT_FLOWCTRL_MASK 0x1F000000
+
+#define PORT_GMII_FLOWCTRL_MASK 0x60000000
+#define PORT_GMII_FC_ON 0x20000000
+#define PORT_GMII_RXFC_ON 0x20000000
+#define PORT_GMII_TXFC_ON 0x40000000
+
+/* Port_st_REG */
+#define PORT_SECURE_ST_MASK 0x001F
+#define MII_PORT_TXC_ERR 0x0080
+
+/* Mem_control_REG */
+#define SDRAM_SIZE_4MBYTES 0x0001
+#define SDRAM_SIZE_8MBYTES 0x0002
+#define SDRAM_SIZE_16MBYTES 0x0003
+#define SDRAM_SIZE_64MBYTES 0x0004
+#define SDRAM_SIZE_128MBYTES 0x0005
+#define SDRAM_SIZE_MASK 0x0007
+
+#define MEMCNTL_SDRAM1_EN (0x1 << 5)
+
+#define ROM_SIZE_DISABLE 0x0000
+#define ROM_SIZE_512KBYTES 0x0001
+#define ROM_SIZE_1MBYTES 0x0002
+#define ROM_SIZE_2MBYTES 0x0003
+#define ROM_SIZE_4MBYTES 0x0004
+#define ROM_SIZE_8MBYTES 0x0005
+#define ROM_SIZE_MASK 0x0007
+
+#define ROM0_SIZE_SHIFT 8
+#define ROM1_SIZE_SHIFT 16
+
+
+/* SW_conf_REG */
+#define SW_AGE_TIMER_MASK 0x000000F0
+#define SW_AGE_TIMER_DISABLE 0x0
+#define SW_AGE_TIMER_FAST 0x00000080
+#define SW_AGE_TIMER_300SEC 0x00000010
+#define SW_AGE_TIMER_600SEC 0x00000020
+#define SW_AGE_TIMER_1200SEC 0x00000030
+#define SW_AGE_TIMER_2400SEC 0x00000040
+#define SW_AGE_TIMER_4800SEC 0x00000050
+#define SW_AGE_TIMER_9600SEC 0x00000060
+#define SW_AGE_TIMER_19200SEC 0x00000070
+//#define SW_AGE_TIMER_38400SEC 0x00000070
+
+#define SW_BC_PREV_MASK 0x00000300
+#define SW_BC_PREV_DISABLE 0
+#define SW_BC_PREV_64BC 0x00000100
+#define SW_BC_PREV_48BC 0x00000200
+#define SW_BC_PREV_32BC 0x00000300
+
+#define SW_MAX_LEN_MASK 0x00000C00
+#define SW_MAX_LEN_1536 0
+#define SW_MAX_LEN_1522 0x00000800
+#define SW_MAX_LEN_1518 0x00000400
+
+#define SW_DIS_COLABT 0x00001000
+
+#define SW_HASH_ALG_MASK 0x00006000
+#define SW_HASH_ALG_DIRECT 0
+#define SW_HASH_ALG_XOR48 0x00002000
+#define SW_HASH_ALG_XOR32 0x00004000
+
+#define SW_DISABLE_BACKOFF_TIMER 0x00008000
+
+#define SW_BP_NUM_MASK 0x000F0000
+#define SW_BP_NUM_SHIFT 16
+#define SW_BP_MODE_MASK 0x00300000
+#define SW_BP_MODE_DISABLE 0
+#define SW_BP_MODE_JAM 0x00100000
+#define SW_BP_MODE_JAMALL 0x00200000
+#define SW_BP_MODE_CARRIER 0x00300000
+#define SW_RESRV_MC_FILTER 0x00400000
+#define SW_BISR_DISABLE 0x00800000
+
+#define SW_DIS_MII_WAS_TX 0x01000000
+#define SW_BISS_EN 0x02000000
+#define SW_BISS_TH_MASK 0x0C000000
+#define SW_BISS_TH_SHIFT 26
+#define SW_REQ_LATENCY_MASK 0xF0000000
+#define SW_REQ_LATENCY_SHIFT 28
+
+
+/* CPUp_conf_REG */
+#define SW_CPU_PORT_DISABLE 0x00000001
+#define SW_PADING_CRC 0x00000002
+#define SW_BRIDGE_MODE 0x00000004
+
+#define SW_DIS_UN_SHIFT 9
+#define SW_DIS_UN_MASK (0x3F << SW_DIS_UN_SHIFT)
+#define SW_DIS_MC_SHIFT 16
+#define SW_DIS_MC_MASK (0x3F << SW_DIS_MC_SHIFT)
+#define SW_DIS_BC_SHIFT 24
+#define SW_DIS_BC_MASK (0x3F << SW_DIS_BC_SHIFT)
+
+
+/* Port_conf0_REG */
+#define SW_DISABLE_PORT_MASK 0x0000003F
+#define SW_EN_MC_MASK 0x00003F00
+#define SW_EN_MC_SHIFT 8
+#define SW_EN_BP_MASK 0x003F0000
+#define SW_EN_BP_SHIFT 16
+#define SW_EN_FC_MASK 0x3F000000
+#define SW_EN_FC_SHIFT 24
+
+
+/* Port_conf1_REG */
+#define SW_DIS_SA_LEARN_MASK 0x0000003F
+#define SW_PORT_BLOCKING_MASK 0x00000FC0
+#define SW_PORT_BLOCKING_SHIFT 6
+#define SW_PORT_BLOCKING_ON 0x1
+
+#define SW_PORT_BLOCKING_MODE_MASK 0x0003F000
+#define SW_PORT_BLOCKING_MODE_SHIFT 12
+#define SW_PORT_BLOCKING_CTRLONLY 0x1
+
+#define SW_EN_PORT_AGE_MASK 0x03F00000
+#define SW_EN_PORT_AGE_SHIFT 20
+#define SW_EN_SA_SECURED_MASK 0xFC000000
+#define SW_EN_SA_SECURED_SHIFT 26
+
+
+/* Port_conf2_REG */
+#define SW_GMII_AN_EN 0x00000001
+#define SW_GMII_FORCE_SPD_MASK 0x00000006
+#define SW_GMII_FORCE_SPD_10M 0
+#define SW_GMII_FORCE_SPD_100M 0x2
+#define SW_GMII_FORCE_SPD_1000M 0x4
+
+#define SW_GMII_FORCE_FULL_DUPLEX 0x00000008
+
+#define SW_GMII_FORCE_RXFC 0x00000010
+#define SW_GMII_FORCE_TXFC 0x00000020
+
+#define SW_GMII_EN 0x00000040
+#define SW_GMII_REVERSE 0x00000080
+
+#define SW_GMII_TXC_CHECK_EN 0x00000100
+
+#define SW_LED_FLASH_TIME_MASK 0x00030000
+#define SW_LED_FLASH_TIME_30MS 0
+#define SW_LED_FLASH_TIME_60MS 0x00010000
+#define SW_LED_FLASH_TIME_240MS 0x00020000
+#define SW_LED_FLASH_TIME_480MS 0x00030000
+
+
+/* Send_trig_REG */
+#define SEND_TRIG_LOW 0x0001
+#define SEND_TRIG_HIGH 0x0002
+
+
+/* Srch_cmd_REG */
+#define SW_MAC_SEARCH_START 0x000001
+#define SW_MAX_SEARCH_AGAIN 0x000002
+
+
+/* MAC_wt0_REG */
+#define SW_MAC_WRITE 0x00000001
+#define SW_MAC_WRITE_DONE 0x00000002
+#define SW_MAC_FILTER_EN 0x00000004
+#define SW_MAC_VLANID_SHIFT 3
+#define SW_MAC_VLANID_MASK 0x00000038
+#define SW_MAC_VLANID_EN 0x00000040
+#define SW_MAC_PORTMAP_MASK 0x00001F80
+#define SW_MAC_PORTMAP_SHIFT 7
+#define SW_MAC_AGE_MASK (0x7 << 13)
+#define SW_MAC_AGE_STATIC (0x7 << 13)
+#define SW_MAC_AGE_VALID (0x1 << 13)
+#define SW_MAC_AGE_EMPTY 0
+
+/* BW_cntl0_REG */
+#define SW_PORT_TX_NOLIMIT 0
+#define SW_PORT_TX_64K 1
+#define SW_PORT_TX_128K 2
+#define SW_PORT_TX_256K 3
+#define SW_PORT_TX_512K 4
+#define SW_PORT_TX_1M 5
+#define SW_PORT_TX_4M 6
+#define SW_PORT_TX_10MK 7
+
+/* BW_cntl1_REG */
+#define SW_TRAFFIC_SHAPE_IPG (0x1 << 31)
+
+/* PHY_cntl0_REG */
+#define SW_PHY_ADDR_MASK 0x0000001F
+#define PHY_ADDR_MAX 0x1f
+#define SW_PHY_REG_ADDR_MASK 0x00001F00
+#define SW_PHY_REG_ADDR_SHIFT 8
+#define PHY_REG_ADDR_MAX 0x1f
+#define SW_PHY_WRITE 0x00002000
+#define SW_PHY_READ 0x00004000
+#define SW_PHY_WDATA_MASK 0xFFFF0000
+#define SW_PHY_WDATA_SHIFT 16
+
+
+/* PHY_cntl1_REG */
+#define SW_PHY_WRITE_DONE 0x00000001
+#define SW_PHY_READ_DONE 0x00000002
+#define SW_PHY_RDATA_MASK 0xFFFF0000
+#define SW_PHY_RDATA_SHIFT 16
+
+/* FC_th_REG */
+/* Adj_port_th_REG */
+/* Port_th_REG */
+
+/* PHY_cntl2_REG */
+#define SW_PHY_AN_MASK 0x0000001F
+#define SW_PHY_SPD_MASK 0x000003E0
+#define SW_PHY_SPD_SHIFT 5
+#define SW_PHY_DPX_MASK 0x00007C00
+#define SW_PHY_DPX_SHIFT 10
+#define SW_FORCE_FC_MASK 0x000F8000
+#define SW_FORCE_FC_SHIFT 15
+#define SW_PHY_NORMAL_MASK 0x01F00000
+#define SW_PHY_NORMAL_SHIFT 20
+#define SW_PHY_AUTOMDIX_MASK 0x3E000000
+#define SW_PHY_AUTOMDIX_SHIFT 25
+#define SW_PHY_REC_MCCAVERAGE 0x40000000
+
+
+/* PHY_cntl3_REG */
+/* Pri_cntl_REG */
+/* VLAN_pri_REG */
+/* TOS_en_REG */
+/* TOS_map0_REG */
+/* TOS_map1_REG */
+/* Custom_pri1_REG */
+/* Custom_pri2_REG */
+/* Empty_cnt_REG */
+/* Port_cnt_sel_REG */
+/* Port_cnt_REG */
+
+
+/* SW_Int_st_REG & SW_Int_mask_REG */
+#define SEND_H_DONE_INT 0x0000001
+#define SEND_L_DONE_INT 0x0000002
+#define RX_H_DONE_INT 0x0000004
+#define RX_L_DONE_INT 0x0000008
+#define RX_H_DESC_FULL_INT 0x0000010
+#define RX_L_DESC_FULL_INT 0x0000020
+#define PORT0_QUE_FULL_INT 0x0000040
+#define PORT1_QUE_FULL_INT 0x0000080
+#define PORT2_QUE_FULL_INT 0x0000100
+#define PORT3_QUE_FULL_INT 0x0000200
+#define PORT4_QUE_FULL_INT 0x0000400
+#define PORT5_QUE_FULL_INT 0x0000800
+
+#define CPU_QUE_FULL_INT 0x0002000
+#define GLOBAL_QUE_FULL_INT 0x0004000
+#define MUST_DROP_INT 0x0008000
+#define BC_STORM_INT 0x0010000
+
+#define PORT_STATUS_CHANGE_INT 0x0040000
+#define INTRUDER_INT 0x0080000
+#define WATCHDOG0_EXPR_INT 0x0100000
+#define WATCHDOG1_EXPR_INT 0x0200000
+#define RX_DESC_ERR_INT 0x0400000
+#define SEND_DESC_ERR_INT 0x0800000
+#define CPU_HOLD_INT 0x1000000
+#define SWITCH_INT_MASK 0x1FDEFFF
+
+
+/* GPIO_conf0_REG */
+#define GPIO0_INPUT_MODE 0x00000001
+#define GPIO1_INPUT_MODE 0x00000002
+#define GPIO2_INPUT_MODE 0x00000004
+#define GPIO3_INPUT_MODE 0x00000008
+#define GPIO4_INPUT_MODE 0x00000010
+#define GPIO5_INPUT_MODE 0x00000020
+#define GPIO6_INPUT_MODE 0x00000040
+#define GPIO7_INPUT_MODE 0x00000080
+
+#define GPIO0_OUTPUT_MODE 0
+#define GPIO1_OUTPUT_MODE 0
+#define GPIO2_OUTPUT_MODE 0
+#define GPIO3_OUTPUT_MODE 0
+#define GPIO4_OUTPUT_MODE 0
+#define GPIO5_OUTPUT_MODE 0
+#define GPIO6_OUTPUT_MODE 0
+#define GPIO7_OUTPUT_MODE 0
+
+#define GPIO0_INPUT_MASK 0x00000100
+#define GPIO1_INPUT_MASK 0x00000200
+#define GPIO2_INPUT_MASK 0x00000400
+#define GPIO3_INPUT_MASK 0x00000800
+#define GPIO4_INPUT_MASK 0x00001000
+#define GPIO5_INPUT_MASK 0x00002000
+#define GPIO6_INPUT_MASK 0x00004000
+#define GPIO7_INPUT_MASK 0x00008000
+
+#define GPIO0_OUTPUT_EN 0x00010000
+#define GPIO1_OUTPUT_EN 0x00020000
+#define GPIO2_OUTPUT_EN 0x00040000
+#define GPIO3_OUTPUT_EN 0x00080000
+#define GPIO4_OUTPUT_EN 0x00100000
+#define GPIO5_OUTPUT_EN 0x00200000
+#define GPIO6_OUTPUT_EN 0x00400000
+#define GPIO7_OUTPUT_EN 0x00800000
+
+#define GPIO_CONF0_OUTEN_MASK 0x00ff0000
+
+#define GPIO0_OUTPUT_HI 0x01000000
+#define GPIO1_OUTPUT_HI 0x02000000
+#define GPIO2_OUTPUT_HI 0x04000000
+#define GPIO3_OUTPUT_HI 0x08000000
+#define GPIO4_OUTPUT_HI 0x10000000
+#define GPIO5_OUTPUT_HI 0x20000000
+#define GPIO6_OUTPUT_HI 0x40000000
+#define GPIO7_OUTPUT_HI 0x80000000
+
+#define GPIO0_OUTPUT_LOW 0
+#define GPIO1_OUTPUT_LOW 0
+#define GPIO2_OUTPUT_LOW 0
+#define GPIO3_OUTPUT_LOW 0
+#define GPIO4_OUTPUT_LOW 0
+#define GPIO5_OUTPUT_LOW 0
+#define GPIO6_OUTPUT_LOW 0
+#define GPIO7_OUTPUT_LOW 0
+
+
+/* GPIO_conf2_REG */
+#define EXTIO_WAIT_EN (0x1 << 6)
+#define EXTIO_CS1_INT1_EN (0x1 << 5)
+#define EXTIO_CS0_INT0_EN (0x1 << 4)
+
+/* Timer_int_REG */
+#define SW_TIMER_INT_DISABLE 0x10000
+#define SW_TIMER_INT 0x1
+
+/* Timer_REG */
+#define SW_TIMER_EN 0x10000
+#define SW_TIMER_MASK 0xffff
+#define SW_TIMER_10MS_TICKS 0x3D09
+#define SW_TIMER_1MS_TICKS 0x61A
+#define SW_TIMER_100US_TICKS 0x9D
+
+
+/* Port0_LED_REG, Port1_LED_REG, Port2_LED_REG, Port3_LED_REG, Port4_LED_REG*/
+#define GPIOL_INPUT_MODE 0x00
+#define GPIOL_OUTPUT_FLASH 0x01
+#define GPIOL_OUTPUT_LOW 0x02
+#define GPIOL_OUTPUT_HIGH 0x03
+#define GPIOL_LINK_LED 0x04
+#define GPIOL_SPEED_LED 0x05
+#define GPIOL_DUPLEX_LED 0x06
+#define GPIOL_ACT_LED 0x07
+#define GPIOL_COL_LED 0x08
+#define GPIOL_LINK_ACT_LED 0x09
+#define GPIOL_DUPLEX_COL_LED 0x0A
+#define GPIOL_10MLINK_ACT_LED 0x0B
+#define GPIOL_100MLINK_ACT_LED 0x0C
+#define GPIOL_CTRL_MASK 0x0F
+
+#define GPIOL_INPUT_MASK 0x7000
+#define GPIOL_INPUT_0_MASK 0x1000
+#define GPIOL_INPUT_1_MASK 0x2000
+#define GPIOL_INPUT_2_MASK 0x4000
+
+#define PORT_LED0_SHIFT 0
+#define PORT_LED1_SHIFT 4
+#define PORT_LED2_SHIFT 8
+#endif
+
+#endif /* _IF_ADMSWREG_H_ */
Property changes on: trunk/sys/mips/adm5120/if_admswreg.h
___________________________________________________________________
Added: svn:eol-style
## -0,0 +1 ##
+native
\ No newline at end of property
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## -0,0 +1 ##
+MidnightBSD=%H
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## -0,0 +1 ##
+text/plain
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Added: trunk/sys/mips/adm5120/if_admswvar.h
===================================================================
--- trunk/sys/mips/adm5120/if_admswvar.h (rev 0)
+++ trunk/sys/mips/adm5120/if_admswvar.h 2018-05-26 21:55:02 UTC (rev 9987)
@@ -0,0 +1,215 @@
+/* $MidnightBSD$ */
+/* $NetBSD: if_admswvar.h,v 1.1 2007/03/20 08:52:02 dyoung Exp $ */
+
+/*-
+ * Copyright (c) 2007 Ruslan Ermilov and Vsevolod Lobko.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or
+ * without modification, are permitted provided that the following
+ * conditions are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above
+ * copyright notice, this list of conditions and the following
+ * disclaimer in the documentation and/or other materials provided
+ * with the distribution.
+ * 3. The names of the authors may not be used to endorse or promote
+ * products derived from this software without specific prior
+ * written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHORS ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
+ * PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHORS
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY,
+ * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
+ * TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
+ * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ */
+#ifndef _IF_ADMSWVAR_H_
+#define _IF_ADMSWVAR_H_
+
+#include <sys/cdefs.h>
+__FBSDID("$FreeBSD: stable/10/sys/mips/adm5120/if_admswvar.h 202175 2010-01-12 21:36:08Z imp $");
+
+#include <sys/param.h>
+#include <sys/systm.h>
+#include <sys/bus.h>
+#include <sys/kernel.h>
+#include <sys/mbuf.h>
+#include <sys/malloc.h>
+#include <sys/module.h>
+#include <sys/rman.h>
+#include <sys/socket.h>
+#include <sys/sockio.h>
+#include <sys/sysctl.h>
+#include <machine/bus.h>
+
+#include <net/ethernet.h>
+#include <net/if.h>
+#include <net/if_arp.h>
+#include <net/if_dl.h>
+#include <net/if_media.h>
+#include <net/if_mib.h>
+#include <net/if_types.h>
+
+#ifdef INET
+#include <netinet/in.h>
+#include <netinet/in_systm.h>
+#include <netinet/in_var.h>
+#include <netinet/ip.h>
+#endif
+
+#include <net/bpf.h>
+#include <net/bpfdesc.h>
+
+#include <dev/mii/mii.h>
+#include <dev/mii/miivar.h>
+
+#include <mips/adm5120/adm5120reg.h>
+#include <mips/adm5120/if_admswreg.h>
+
+#define MAC_BUFLEN 0x07ff
+
+#define ADMSW_NTXHDESC 4
+#define ADMSW_NRXHDESC 32
+#define ADMSW_NTXLDESC 32
+#define ADMSW_NRXLDESC 32
+
+#define ADMSW_NTXHDESC_MASK (ADMSW_NTXHDESC - 1)
+#define ADMSW_NRXHDESC_MASK (ADMSW_NRXHDESC - 1)
+#define ADMSW_NTXLDESC_MASK (ADMSW_NTXLDESC - 1)
+#define ADMSW_NRXLDESC_MASK (ADMSW_NRXLDESC - 1)
+
+#define ADMSW_NEXTTXH(x) (((x) + 1) & ADMSW_NTXHDESC_MASK)
+#define ADMSW_NEXTRXH(x) (((x) + 1) & ADMSW_NRXHDESC_MASK)
+#define ADMSW_NEXTTXL(x) (((x) + 1) & ADMSW_NTXLDESC_MASK)
+#define ADMSW_NEXTRXL(x) (((x) + 1) & ADMSW_NRXLDESC_MASK)
+
+#define ADMSW_IRQ 9
+
+struct admsw_control_data {
+ /* The transmit descriptors. */
+ struct admsw_desc acd_txhdescs[ADMSW_NTXHDESC];
+
+ /* The receive descriptors. */
+ struct admsw_desc acd_rxhdescs[ADMSW_NRXHDESC];
+
+ /* The transmit descriptors. */
+ struct admsw_desc acd_txldescs[ADMSW_NTXLDESC];
+
+ /* The receive descriptors. */
+ struct admsw_desc acd_rxldescs[ADMSW_NRXLDESC];
+};
+
+#define ADMSW_CDOFF(x) offsetof(struct admsw_control_data, x)
+#define ADMSW_CDTXHOFF(x) ADMSW_CDOFF(acd_txhdescs[(x)])
+#define ADMSW_CDTXLOFF(x) ADMSW_CDOFF(acd_txldescs[(x)])
+#define ADMSW_CDRXHOFF(x) ADMSW_CDOFF(acd_rxhdescs[(x)])
+#define ADMSW_CDRXLOFF(x) ADMSW_CDOFF(acd_rxldescs[(x)])
+
+struct admsw_descsoft {
+ struct mbuf *ds_mbuf;
+ bus_dmamap_t ds_dmamap;
+ /* Up to 2 segments */
+ uint32_t ds_addr[2];
+ uint32_t ds_len[2];
+ uint32_t ds_nsegs;
+};
+
+/*
+ * Software state per device.
+ */
+struct admsw_softc {
+ device_t sc_dev; /* generic device information */
+ uint8_t sc_enaddr[ETHER_ADDR_LEN];
+ bus_dma_tag_t sc_control_dmat;
+ /* bus DMA tag for control structs*/
+ bus_dma_tag_t sc_bufs_dmat; /* bus DMA tag for buffers */
+ struct ifmedia sc_ifmedia[SW_DEVS];
+ int ndevs; /* number of IFF_RUNNING interfaces */
+ struct ifnet *sc_ifnet[SW_DEVS];
+ struct callout sc_watchdog;
+ int sc_timer;
+ /* Ethernet common data */
+ void *sc_ih; /* interrupt cookie */
+ struct resource *irq_res;
+ struct resource *mem_res;
+ bus_dmamap_t sc_cddmamap; /* control data DMA map */
+ uint32_t sc_cddma;
+ struct admsw_control_data *sc_control_data;
+
+ struct admsw_descsoft sc_txhsoft[ADMSW_NTXHDESC];
+ struct admsw_descsoft sc_rxhsoft[ADMSW_NRXHDESC];
+ struct admsw_descsoft sc_txlsoft[ADMSW_NTXLDESC];
+ struct admsw_descsoft sc_rxlsoft[ADMSW_NRXLDESC];
+#define sc_txhdescs sc_control_data->acd_txhdescs
+#define sc_rxhdescs sc_control_data->acd_rxhdescs
+#define sc_txldescs sc_control_data->acd_txldescs
+#define sc_rxldescs sc_control_data->acd_rxldescs
+
+ int sc_txfree; /* number of free Tx descriptors */
+ int sc_txnext; /* next Tx descriptor to use */
+ int sc_txdirty; /* first dirty Tx descriptor */
+ int sc_rxptr; /* next ready Rx descriptor */
+};
+
+#define ADMSW_CDTXHADDR(sc, x) ((sc)->sc_cddma + ADMSW_CDTXHOFF((x)))
+#define ADMSW_CDTXLADDR(sc, x) ((sc)->sc_cddma + ADMSW_CDTXLOFF((x)))
+#define ADMSW_CDRXHADDR(sc, x) ((sc)->sc_cddma + ADMSW_CDRXHOFF((x)))
+#define ADMSW_CDRXLADDR(sc, x) ((sc)->sc_cddma + ADMSW_CDRXLOFF((x)))
+
+#define ADMSW_CDTXHSYNC(sc, x, ops) \
+ bus_dmamap_sync((sc)->sc_control_dmat, (sc)->sc_cddmamap, (ops))
+
+#define ADMSW_CDTXLSYNC(sc, x, ops) \
+ bus_dmamap_sync((sc)->sc_control_dmat, (sc)->sc_cddmamap, (ops))
+
+#define ADMSW_CDRXHSYNC(sc, x, ops) \
+ bus_dmamap_sync((sc)->sc_control_dmat, (sc)->sc_cddmamap, (ops))
+
+#define ADMSW_CDRXLSYNC(sc, x, ops) \
+ bus_dmamap_sync((sc)->sc_control_dmat, (sc)->sc_cddmamap, (ops))
+
+#define ADMSW_INIT_RXHDESC(sc, x) \
+do { \
+ struct admsw_descsoft *__ds = &(sc)->sc_rxhsoft[(x)]; \
+ struct admsw_desc *__desc = &(sc)->sc_rxhdescs[(x)]; \
+ struct mbuf *__m = __ds->ds_mbuf; \
+ \
+ __m->m_data = __m->m_ext.ext_buf + 2; \
+ __desc->data = __ds->ds_addr[0] + 2; \
+ __desc->cntl = 0; \
+ __desc->len = min(MCLBYTES - 2, MAC_BUFLEN - 2); \
+ __desc->status = 0; \
+ if ((x) == ADMSW_NRXHDESC - 1) \
+ __desc->data |= ADM5120_DMA_RINGEND; \
+ __desc->data |= ADM5120_DMA_OWN; \
+ ADMSW_CDRXHSYNC((sc), (x), BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); \
+} while (0)
+
+#define ADMSW_INIT_RXLDESC(sc, x) \
+do { \
+ struct admsw_descsoft *__ds = &(sc)->sc_rxlsoft[(x)]; \
+ struct admsw_desc *__desc = &(sc)->sc_rxldescs[(x)]; \
+ struct mbuf *__m = __ds->ds_mbuf; \
+ \
+ __m->m_data = __m->m_ext.ext_buf + 2; \
+ __desc->data = __ds->ds_addr[0] + 2; \
+ __desc->cntl = 0; \
+ __desc->len = min(MCLBYTES - 2, MAC_BUFLEN - 2); \
+ __desc->status = 0; \
+ if ((x) == ADMSW_NRXLDESC - 1) \
+ __desc->data |= ADM5120_DMA_RINGEND; \
+ __desc->data |= ADM5120_DMA_OWN; \
+ ADMSW_CDRXLSYNC((sc), (x), BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); \
+} while (0)
+
+void admwdog_attach(struct admsw_softc *);
+
+#endif /* _IF_ADMSWVAR_H_ */
Property changes on: trunk/sys/mips/adm5120/if_admswvar.h
___________________________________________________________________
Added: svn:eol-style
## -0,0 +1 ##
+native
\ No newline at end of property
Added: svn:keywords
## -0,0 +1 ##
+MidnightBSD=%H
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+text/plain
\ No newline at end of property
Added: trunk/sys/mips/adm5120/obio.c
===================================================================
--- trunk/sys/mips/adm5120/obio.c (rev 0)
+++ trunk/sys/mips/adm5120/obio.c 2018-05-26 21:55:02 UTC (rev 9987)
@@ -0,0 +1,545 @@
+/* $MidnightBSD$ */
+/* $NetBSD: obio.c,v 1.11 2003/07/15 00:25:05 lukem Exp $ */
+
+/*-
+ * Copyright (c) 2001, 2002, 2003 Wasabi Systems, Inc.
+ * All rights reserved.
+ *
+ * Written by Jason R. Thorpe for Wasabi Systems, Inc.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * 3. All advertising materials mentioning features or use of this software
+ * must display the following acknowledgement:
+ * This product includes software developed for the NetBSD Project by
+ * Wasabi Systems, Inc.
+ * 4. The name of Wasabi Systems, Inc. may not be used to endorse
+ * or promote products derived from this software without specific prior
+ * written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <sys/cdefs.h>
+__FBSDID("$FreeBSD: stable/10/sys/mips/adm5120/obio.c 265999 2014-05-14 01:35:43Z ian $");
+
+#include <sys/param.h>
+#include <sys/systm.h>
+#include <sys/bus.h>
+#include <sys/interrupt.h>
+#include <sys/kernel.h>
+#include <sys/module.h>
+#include <sys/rman.h>
+#include <sys/malloc.h>
+
+#include <machine/bus.h>
+
+#include <mips/adm5120/adm5120reg.h>
+#include <mips/adm5120/obiovar.h>
+
+/* MIPS HW interrupts of IRQ/FIQ respectively */
+#define ADM5120_INTR 0
+#define ADM5120_FAST_INTR 1
+
+/* Interrupt levels */
+#define INTR_IRQ 0
+#define INTR_FIQ 1
+
+int irq_priorities[NIRQS] = {
+ INTR_IRQ, /* flash */
+ INTR_FIQ, /* uart0 */
+ INTR_FIQ, /* uart1 */
+ INTR_IRQ, /* ahci */
+ INTR_IRQ, /* unknown */
+ INTR_IRQ, /* unknown */
+ INTR_IRQ, /* unknown */
+ INTR_IRQ, /* unknown */
+ INTR_IRQ, /* unknown */
+ INTR_IRQ, /* admsw */
+ INTR_IRQ, /* unknown */
+ INTR_IRQ, /* unknown */
+ INTR_IRQ, /* unknown */
+ INTR_IRQ, /* unknown */
+ INTR_IRQ, /* unknown */
+ INTR_IRQ, /* unknown */
+ INTR_IRQ, /* unknown */
+ INTR_IRQ, /* unknown */
+ INTR_IRQ, /* unknown */
+ INTR_IRQ, /* unknown */
+ INTR_IRQ, /* unknown */
+ INTR_IRQ, /* unknown */
+ INTR_IRQ, /* unknown */
+ INTR_IRQ, /* unknown */
+ INTR_IRQ, /* unknown */
+ INTR_IRQ, /* unknown */
+ INTR_IRQ, /* unknown */
+ INTR_IRQ, /* unknown */
+ INTR_IRQ, /* unknown */
+ INTR_IRQ, /* unknown */
+ INTR_IRQ, /* unknown */
+ INTR_IRQ, /* unknown */
+};
+
+
+#define REG_READ(o) *((volatile uint32_t *)MIPS_PHYS_TO_KSEG1(ADM5120_BASE_ICU + (o)))
+#define REG_WRITE(o,v) (REG_READ(o)) = (v)
+
+static int obio_activate_resource(device_t, device_t, int, int,
+ struct resource *);
+static device_t obio_add_child(device_t, u_int, const char *, int);
+static struct resource *
+ obio_alloc_resource(device_t, device_t, int, int *, u_long,
+ u_long, u_long, u_int);
+static int obio_attach(device_t);
+static int obio_deactivate_resource(device_t, device_t, int, int,
+ struct resource *);
+static struct resource_list *
+ obio_get_resource_list(device_t, device_t);
+static void obio_hinted_child(device_t, const char *, int);
+static int obio_intr(void *);
+static int obio_probe(device_t);
+static int obio_release_resource(device_t, device_t, int, int,
+ struct resource *);
+static int obio_setup_intr(device_t, device_t, struct resource *, int,
+ driver_filter_t *, driver_intr_t *, void *, void **);
+static int obio_teardown_intr(device_t, device_t, struct resource *,
+ void *);
+
+
+static void
+obio_mask_irq(void *source)
+{
+ int irq;
+ uint32_t irqmask;
+ uint32_t reg;
+
+ irq = (int)source;
+ irqmask = 1 << irq;
+
+ /* disable IRQ */
+ reg = REG_READ(ICU_DISABLE_REG);
+ REG_WRITE(ICU_DISABLE_REG, (reg | irqmask));
+}
+
+static void
+obio_unmask_irq(void *source)
+{
+ int irq;
+ uint32_t irqmask;
+ uint32_t reg;
+
+ irq = (int)source;
+ irqmask = 1 << irq;
+
+ /* disable IRQ */
+ reg = REG_READ(ICU_DISABLE_REG);
+ REG_WRITE(ICU_DISABLE_REG, (reg & ~irqmask));
+
+}
+
+
+static int
+obio_probe(device_t dev)
+{
+
+ return (BUS_PROBE_NOWILDCARD);
+}
+
+static int
+obio_attach(device_t dev)
+{
+ struct obio_softc *sc = device_get_softc(dev);
+ int rid;
+
+ sc->oba_mem_rman.rm_type = RMAN_ARRAY;
+ sc->oba_mem_rman.rm_descr = "OBIO memeory";
+ if (rman_init(&sc->oba_mem_rman) != 0 ||
+ rman_manage_region(&sc->oba_mem_rman, OBIO_MEM_START,
+ OBIO_MEM_START + OBIO_MEM_SIZE) != 0)
+ panic("obio_attach: failed to set up I/O rman");
+
+ sc->oba_irq_rman.rm_type = RMAN_ARRAY;
+ sc->oba_irq_rman.rm_descr = "OBIO IRQ";
+
+ if (rman_init(&sc->oba_irq_rman) != 0 ||
+ rman_manage_region(&sc->oba_irq_rman, 0, NIRQS-1) != 0)
+ panic("obio_attach: failed to set up IRQ rman");
+
+ /* Hook up our interrupt handler. */
+ if ((sc->sc_irq = bus_alloc_resource(dev, SYS_RES_IRQ, &rid,
+ ADM5120_INTR, ADM5120_INTR, 1,
+ RF_SHAREABLE | RF_ACTIVE)) == NULL) {
+ device_printf(dev, "unable to allocate IRQ resource\n");
+ return (ENXIO);
+ }
+
+ if ((bus_setup_intr(dev, sc->sc_irq, INTR_TYPE_MISC, obio_intr, NULL,
+ sc, &sc->sc_ih))) {
+ device_printf(dev,
+ "WARNING: unable to register interrupt handler\n");
+ return (ENXIO);
+ }
+
+ /* Hook up our FAST interrupt handler. */
+ if ((sc->sc_fast_irq = bus_alloc_resource(dev, SYS_RES_IRQ, &rid,
+ ADM5120_FAST_INTR, ADM5120_FAST_INTR, 1,
+ RF_SHAREABLE | RF_ACTIVE)) == NULL) {
+ device_printf(dev, "unable to allocate IRQ resource\n");
+ return (ENXIO);
+ }
+
+ if ((bus_setup_intr(dev, sc->sc_fast_irq, INTR_TYPE_MISC, obio_intr,
+ NULL, sc, &sc->sc_fast_ih))) {
+ device_printf(dev,
+ "WARNING: unable to register interrupt handler\n");
+ return (ENXIO);
+ }
+
+ /* disable all interrupts */
+ REG_WRITE(ICU_ENABLE_REG, ICU_INT_MASK);
+
+ bus_generic_probe(dev);
+ bus_enumerate_hinted_children(dev);
+ bus_generic_attach(dev);
+
+ return (0);
+}
+
+static struct resource *
+obio_alloc_resource(device_t bus, device_t child, int type, int *rid,
+ u_long start, u_long end, u_long count, u_int flags)
+{
+ struct obio_softc *sc = device_get_softc(bus);
+ struct obio_ivar *ivar = device_get_ivars(child);
+ struct resource *rv;
+ struct resource_list_entry *rle;
+ struct rman *rm;
+ int isdefault, needactivate, passthrough;
+
+ isdefault = (start == 0UL && end == ~0UL && count == 1);
+ needactivate = flags & RF_ACTIVE;
+ passthrough = (device_get_parent(child) != bus);
+ rle = NULL;
+
+ if (passthrough)
+ return (BUS_ALLOC_RESOURCE(device_get_parent(bus), child, type,
+ rid, start, end, count, flags));
+
+ /*
+ * If this is an allocation of the "default" range for a given RID,
+ * and we know what the resources for this device are (ie. they aren't
+ * maintained by a child bus), then work out the start/end values.
+ */
+ if (isdefault) {
+ rle = resource_list_find(&ivar->resources, type, *rid);
+ if (rle == NULL)
+ return (NULL);
+ if (rle->res != NULL) {
+ panic("%s: resource entry is busy", __func__);
+ }
+ start = rle->start;
+ end = rle->end;
+ count = rle->count;
+ }
+
+ switch (type) {
+ case SYS_RES_IRQ:
+ rm = &sc->oba_irq_rman;
+ break;
+ case SYS_RES_MEMORY:
+ rm = &sc->oba_mem_rman;
+ break;
+ default:
+ printf("%s: unknown resource type %d\n", __func__, type);
+ return (0);
+ }
+
+ rv = rman_reserve_resource(rm, start, end, count, flags, child);
+ if (rv == 0) {
+ printf("%s: could not reserve resource\n", __func__);
+ return (0);
+ }
+
+ rman_set_rid(rv, *rid);
+
+ if (needactivate) {
+ if (bus_activate_resource(child, type, *rid, rv)) {
+ printf("%s: could not activate resource\n", __func__);
+ rman_release_resource(rv);
+ return (0);
+ }
+ }
+
+ return (rv);
+}
+
+static int
+obio_activate_resource(device_t bus, device_t child, int type, int rid,
+ struct resource *r)
+{
+
+ /*
+ * If this is a memory resource, track the direct mapping
+ * in the uncached MIPS KSEG1 segment.
+ */
+ if (type == SYS_RES_MEMORY) {
+ void *vaddr;
+
+ vaddr = (void *)MIPS_PHYS_TO_KSEG1((intptr_t)rman_get_start(r));
+ rman_set_virtual(r, vaddr);
+ rman_set_bustag(r, mips_bus_space_generic);
+ rman_set_bushandle(r, (bus_space_handle_t)vaddr);
+ }
+
+ return (rman_activate_resource(r));
+}
+
+static int
+obio_deactivate_resource(device_t bus, device_t child, int type, int rid,
+ struct resource *r)
+{
+
+ return (rman_deactivate_resource(r));
+}
+
+static int
+obio_release_resource(device_t dev, device_t child, int type,
+ int rid, struct resource *r)
+{
+ struct resource_list *rl;
+ struct resource_list_entry *rle;
+
+ rl = obio_get_resource_list(dev, child);
+ if (rl == NULL)
+ return (EINVAL);
+ rle = resource_list_find(rl, type, rid);
+ if (rle == NULL)
+ return (EINVAL);
+ rman_release_resource(r);
+ rle->res = NULL;
+
+ return (0);
+}
+
+static int
+obio_setup_intr(device_t dev, device_t child, struct resource *ires,
+ int flags, driver_filter_t *filt, driver_intr_t *handler,
+ void *arg, void **cookiep)
+{
+ struct obio_softc *sc = device_get_softc(dev);
+ struct intr_event *event;
+ int irq, error, priority;
+ uint32_t irqmask;
+
+ irq = rman_get_start(ires);
+
+ if (irq >= NIRQS)
+ panic("%s: bad irq %d", __func__, irq);
+
+ event = sc->sc_eventstab[irq];
+ if (event == NULL) {
+ error = intr_event_create(&event, (void *)irq, 0, irq,
+ obio_mask_irq, obio_unmask_irq,
+ NULL, NULL, "obio intr%d:", irq);
+
+ sc->sc_eventstab[irq] = event;
+ }
+ else
+ panic("obio: Can't share IRQs");
+
+ intr_event_add_handler(event, device_get_nameunit(child), filt,
+ handler, arg, intr_priority(flags), flags, cookiep);
+
+ irqmask = 1 << irq;
+ priority = irq_priorities[irq];
+
+ if (priority == INTR_FIQ)
+ REG_WRITE(ICU_MODE_REG, REG_READ(ICU_MODE_REG) | irqmask);
+ else
+ REG_WRITE(ICU_MODE_REG, REG_READ(ICU_MODE_REG) & ~irqmask);
+
+ /* enable */
+ REG_WRITE(ICU_ENABLE_REG, irqmask);
+
+ obio_unmask_irq((void*)irq);
+
+ return (0);
+}
+
+static int
+obio_teardown_intr(device_t dev, device_t child, struct resource *ires,
+ void *cookie)
+{
+ struct obio_softc *sc = device_get_softc(dev);
+ int irq, result, priority;
+ uint32_t irqmask;
+
+ irq = rman_get_start(ires);
+ if (irq >= NIRQS)
+ panic("%s: bad irq %d", __func__, irq);
+
+ if (sc->sc_eventstab[irq] == NULL)
+ panic("Trying to teardown unoccupied IRQ");
+
+ irqmask = (1 << irq);
+ priority = irq_priorities[irq];
+
+ if (priority == INTR_FIQ)
+ REG_WRITE(ICU_MODE_REG, REG_READ(ICU_MODE_REG) & ~irqmask);
+ else
+ REG_WRITE(ICU_MODE_REG, REG_READ(ICU_MODE_REG) | irqmask);
+
+ /* disable */
+ irqmask = REG_READ(ICU_ENABLE_REG);
+ irqmask &= ~(1 << irq);
+ REG_WRITE(ICU_ENABLE_REG, irqmask);
+
+ result = intr_event_remove_handler(cookie);
+ if (!result) {
+ sc->sc_eventstab[irq] = NULL;
+ }
+
+ return (result);
+}
+
+static int
+obio_intr(void *arg)
+{
+ struct obio_softc *sc = arg;
+ struct intr_event *event;
+ uint32_t irqstat;
+ int irq;
+
+ irqstat = REG_READ(ICU_FIQ_STATUS_REG);
+ irqstat |= REG_READ(ICU_STATUS_REG);
+
+ irq = 0;
+ while (irqstat != 0) {
+ if ((irqstat & 1) == 1) {
+ event = sc->sc_eventstab[irq];
+ if (!event || TAILQ_EMPTY(&event->ie_handlers))
+ continue;
+
+ /* TODO: pass frame as an argument*/
+ /* TODO: log stray interrupt */
+ intr_event_handle(event, NULL);
+ }
+
+ irq++;
+ irqstat >>= 1;
+ }
+
+ return (FILTER_HANDLED);
+}
+
+static void
+obio_hinted_child(device_t bus, const char *dname, int dunit)
+{
+ device_t child;
+ long maddr;
+ int msize;
+ int irq;
+ int result;
+
+ child = BUS_ADD_CHILD(bus, 0, dname, dunit);
+
+ /*
+ * Set hard-wired resources for hinted child using
+ * specific RIDs.
+ */
+ resource_long_value(dname, dunit, "maddr", &maddr);
+ resource_int_value(dname, dunit, "msize", &msize);
+
+
+ result = bus_set_resource(child, SYS_RES_MEMORY, 0,
+ maddr, msize);
+ if (result != 0)
+ device_printf(bus, "warning: bus_set_resource() failed\n");
+
+ if (resource_int_value(dname, dunit, "irq", &irq) == 0) {
+ result = bus_set_resource(child, SYS_RES_IRQ, 0, irq, 1);
+ if (result != 0)
+ device_printf(bus,
+ "warning: bus_set_resource() failed\n");
+ }
+}
+
+static device_t
+obio_add_child(device_t bus, u_int order, const char *name, int unit)
+{
+ device_t child;
+ struct obio_ivar *ivar;
+
+ ivar = malloc(sizeof(struct obio_ivar), M_DEVBUF, M_WAITOK | M_ZERO);
+ if (ivar == NULL) {
+ printf("Failed to allocate ivar\n");
+ return (0);
+ }
+ resource_list_init(&ivar->resources);
+
+ child = device_add_child_ordered(bus, order, name, unit);
+ if (child == NULL) {
+ printf("Can't add child %s%d ordered\n", name, unit);
+ return (0);
+ }
+
+ device_set_ivars(child, ivar);
+
+ return (child);
+}
+
+/*
+ * Helper routine for bus_generic_rl_get_resource/bus_generic_rl_set_resource
+ * Provides pointer to resource_list for these routines
+ */
+static struct resource_list *
+obio_get_resource_list(device_t dev, device_t child)
+{
+ struct obio_ivar *ivar;
+
+ ivar = device_get_ivars(child);
+ return (&(ivar->resources));
+}
+
+static device_method_t obio_methods[] = {
+ DEVMETHOD(bus_activate_resource, obio_activate_resource),
+ DEVMETHOD(bus_add_child, obio_add_child),
+ DEVMETHOD(bus_alloc_resource, obio_alloc_resource),
+ DEVMETHOD(bus_deactivate_resource, obio_deactivate_resource),
+ DEVMETHOD(bus_get_resource_list, obio_get_resource_list),
+ DEVMETHOD(bus_hinted_child, obio_hinted_child),
+ DEVMETHOD(bus_release_resource, obio_release_resource),
+ DEVMETHOD(bus_setup_intr, obio_setup_intr),
+ DEVMETHOD(bus_teardown_intr, obio_teardown_intr),
+ DEVMETHOD(device_attach, obio_attach),
+ DEVMETHOD(device_probe, obio_probe),
+ DEVMETHOD(bus_get_resource, bus_generic_rl_get_resource),
+ DEVMETHOD(bus_set_resource, bus_generic_rl_set_resource),
+
+ {0, 0},
+};
+
+static driver_t obio_driver = {
+ "obio",
+ obio_methods,
+ sizeof(struct obio_softc),
+};
+static devclass_t obio_devclass;
+
+DRIVER_MODULE(obio, nexus, obio_driver, obio_devclass, 0, 0);
Property changes on: trunk/sys/mips/adm5120/obio.c
___________________________________________________________________
Added: svn:eol-style
## -0,0 +1 ##
+native
\ No newline at end of property
Added: svn:keywords
## -0,0 +1 ##
+MidnightBSD=%H
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+text/plain
\ No newline at end of property
Added: trunk/sys/mips/adm5120/obiovar.h
===================================================================
--- trunk/sys/mips/adm5120/obiovar.h (rev 0)
+++ trunk/sys/mips/adm5120/obiovar.h 2018-05-26 21:55:02 UTC (rev 9987)
@@ -0,0 +1,67 @@
+/* $MidnightBSD$ */
+/* $NetBSD: obiovar.h,v 1.4 2003/06/16 17:40:53 thorpej Exp $ */
+
+/*-
+ * Copyright (c) 2002, 2003 Wasabi Systems, Inc.
+ * All rights reserved.
+ *
+ * Written by Jason R. Thorpe for Wasabi Systems, Inc.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * 3. All advertising materials mentioning features or use of this software
+ * must display the following acknowledgement:
+ * This product includes software developed for the NetBSD Project by
+ * Wasabi Systems, Inc.
+ * 4. The name of Wasabi Systems, Inc. may not be used to endorse
+ * or promote products derived from this software without specific prior
+ * written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * $FreeBSD: stable/10/sys/mips/adm5120/obiovar.h 202175 2010-01-12 21:36:08Z imp $
+ *
+ */
+
+#ifndef _ADM5120_OBIOVAR_H_
+#define _ADM5120_OBIOVAR_H_
+
+#include <sys/rman.h>
+
+/* Number of IRQs */
+#define NIRQS 32
+
+#define OBIO_MEM_START 0x10C00000L
+#define OBIO_MEM_SIZE 0x1e00000
+
+struct obio_softc {
+ struct rman oba_mem_rman;
+ struct rman oba_irq_rman;
+ struct intr_event *sc_eventstab[NIRQS]; /* IRQ events structs */
+ struct resource *sc_irq; /* IRQ resource */
+ void *sc_ih; /* interrupt cookie */
+ struct resource *sc_fast_irq; /* IRQ resource */
+ void *sc_fast_ih; /* interrupt cookie */
+};
+
+struct obio_ivar {
+ struct resource_list resources;
+};
+
+#endif /* _ADM5120_OBIOVAR_H_ */
Property changes on: trunk/sys/mips/adm5120/obiovar.h
___________________________________________________________________
Added: svn:eol-style
## -0,0 +1 ##
+native
\ No newline at end of property
Added: svn:keywords
## -0,0 +1 ##
+MidnightBSD=%H
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+text/plain
\ No newline at end of property
Added: trunk/sys/mips/adm5120/std.adm5120
===================================================================
--- trunk/sys/mips/adm5120/std.adm5120 (rev 0)
+++ trunk/sys/mips/adm5120/std.adm5120 2018-05-26 21:55:02 UTC (rev 9987)
@@ -0,0 +1,12 @@
+# $FreeBSD: stable/10/sys/mips/adm5120/std.adm5120 232896 2012-03-12 21:25:32Z jmallett $
+#
+# Standard include file for ADM5120
+
+files "../adm5120/files.adm5120"
+
+machine mips mipsel
+cpu CPU_MIPS4KC
+
+# device admpci
+device admsw
+device pci
Property changes on: trunk/sys/mips/adm5120/std.adm5120
___________________________________________________________________
Added: mnbsd:nokeywords
## -0,0 +1 ##
+MidnightBSD=%H
\ No newline at end of property
Added: trunk/sys/mips/adm5120/uart_bus_adm5120.c
===================================================================
--- trunk/sys/mips/adm5120/uart_bus_adm5120.c (rev 0)
+++ trunk/sys/mips/adm5120/uart_bus_adm5120.c 2018-05-26 21:55:02 UTC (rev 9987)
@@ -0,0 +1,94 @@
+/* $MidnightBSD$ */
+/*-
+ * Copyright (c) 2007 Bruce M. Simpson.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * $Id$
+ */
+/*
+ * Skeleton of this file was based on respective code for ARM
+ * code written by Olivier Houchard.
+ */
+
+/*
+ * XXXMIPS: This file is hacked from arm/... . XXXMIPS here means this file is
+ * experimental and was written for MIPS32 port.
+ */
+#include "opt_uart.h"
+
+#include <sys/cdefs.h>
+__FBSDID("$FreeBSD: stable/10/sys/mips/adm5120/uart_bus_adm5120.c 202175 2010-01-12 21:36:08Z imp $");
+
+#include <sys/param.h>
+#include <sys/systm.h>
+#include <sys/bus.h>
+#include <sys/conf.h>
+#include <sys/kernel.h>
+#include <sys/module.h>
+#include <machine/bus.h>
+#include <sys/rman.h>
+#include <machine/resource.h>
+
+#include <dev/pci/pcivar.h>
+
+#include <dev/uart/uart.h>
+#include <dev/uart/uart_bus.h>
+#include <dev/uart/uart_cpu.h>
+
+#include <mips/adm5120/adm5120reg.h>
+
+#include "uart_if.h"
+
+static int uart_adm5120_probe(device_t dev);
+
+extern struct uart_class uart_adm5120_uart_class;
+
+static device_method_t uart_adm5120_methods[] = {
+ /* Device interface */
+ DEVMETHOD(device_probe, uart_adm5120_probe),
+ DEVMETHOD(device_attach, uart_bus_attach),
+ DEVMETHOD(device_detach, uart_bus_detach),
+ { 0, 0 }
+};
+
+static driver_t uart_adm5120_driver = {
+ uart_driver_name,
+ uart_adm5120_methods,
+ sizeof(struct uart_softc),
+};
+
+extern SLIST_HEAD(uart_devinfo_list, uart_devinfo) uart_sysdevs;
+
+static int
+uart_adm5120_probe(device_t dev)
+{
+ struct uart_softc *sc;
+
+ sc = device_get_softc(dev);
+ sc->sc_sysdev = SLIST_FIRST(&uart_sysdevs);
+ sc->sc_class = &uart_adm5120_uart_class;
+ bcopy(&sc->sc_sysdev->bas, &sc->sc_bas, sizeof(sc->sc_bas));
+
+ return (uart_bus_probe(dev, 0, 0, 0, 0));
+}
+
+DRIVER_MODULE(uart, obio, uart_adm5120_driver, uart_devclass, 0, 0);
Property changes on: trunk/sys/mips/adm5120/uart_bus_adm5120.c
___________________________________________________________________
Added: svn:eol-style
## -0,0 +1 ##
+native
\ No newline at end of property
Added: svn:keywords
## -0,0 +1 ##
+MidnightBSD=%H
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+text/plain
\ No newline at end of property
Added: trunk/sys/mips/adm5120/uart_cpu_adm5120.c
===================================================================
--- trunk/sys/mips/adm5120/uart_cpu_adm5120.c (rev 0)
+++ trunk/sys/mips/adm5120/uart_cpu_adm5120.c 2018-05-26 21:55:02 UTC (rev 9987)
@@ -0,0 +1,84 @@
+/* $MidnightBSD$ */
+/*-
+ * Copyright (c) 2006 Wojciech A. Koszek <wkoszek at FreeBSD.org>
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ * $Id$
+ */
+/*
+ * Skeleton of this file was based on respective code for ARM
+ * code written by Olivier Houchard.
+ */
+/*
+ * XXXMIPS: This file is hacked from arm/... . XXXMIPS here means this file is
+ * experimental and was written for MIPS32 port.
+ */
+#include "opt_uart.h"
+
+#include <sys/cdefs.h>
+__FBSDID("$FreeBSD: stable/10/sys/mips/adm5120/uart_cpu_adm5120.c 202175 2010-01-12 21:36:08Z imp $");
+
+#include <sys/param.h>
+#include <sys/systm.h>
+#include <sys/bus.h>
+#include <sys/cons.h>
+
+#include <machine/bus.h>
+
+#include <dev/uart/uart.h>
+#include <dev/uart/uart_cpu.h>
+
+#include <mips/adm5120/adm5120reg.h>
+
+extern struct uart_class uart_adm5120_uart_class;
+bus_space_tag_t uart_bus_space_io;
+bus_space_tag_t uart_bus_space_mem;
+
+int
+uart_cpu_eqres(struct uart_bas *b1, struct uart_bas *b2)
+{
+
+ return ((b1->bsh == b2->bsh && b1->bst == b2->bst) ? 1 : 0);
+}
+
+int
+uart_cpu_getdev(int devtype, struct uart_devinfo *di)
+{
+
+ di->ops = uart_getops(&uart_adm5120_uart_class);
+ di->bas.chan = 0;
+ di->bas.bst = mips_bus_space_generic;
+ di->bas.regshft = 0;
+ di->bas.rclk = 0;
+ di->baudrate = 115200;
+ di->databits = 8;
+ di->stopbits = 1;
+ di->parity = UART_PARITY_NONE;
+
+ uart_bus_space_io = 0;
+ uart_bus_space_mem = mips_bus_space_generic;
+ di->bas.bsh = MIPS_PHYS_TO_KSEG1(ADM5120_BASE_UART0);
+
+ return (0);
+}
Property changes on: trunk/sys/mips/adm5120/uart_cpu_adm5120.c
___________________________________________________________________
Added: svn:eol-style
## -0,0 +1 ##
+native
\ No newline at end of property
Added: svn:keywords
## -0,0 +1 ##
+MidnightBSD=%H
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+text/plain
\ No newline at end of property
Added: trunk/sys/mips/adm5120/uart_dev_adm5120.c
===================================================================
--- trunk/sys/mips/adm5120/uart_dev_adm5120.c (rev 0)
+++ trunk/sys/mips/adm5120/uart_dev_adm5120.c 2018-05-26 21:55:02 UTC (rev 9987)
@@ -0,0 +1,480 @@
+/* $MidnightBSD$ */
+/* $NetBSD: uart.c,v 1.2 2007/03/23 20:05:47 dogcow Exp $ */
+
+/*-
+ * Copyright (c) 2007 Ruslan Ermilov and Vsevolod Lobko.
+ * Copyright (c) 2007 Oleksandr Tymoshenko.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or
+ * without modification, are permitted provided that the following
+ * conditions are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above
+ * copyright notice, this list of conditions and the following
+ * disclaimer in the documentation and/or other materials provided
+ * with the distribution.
+ * 3. The names of the authors may not be used to endorse or promote
+ * products derived from this software without specific prior
+ * written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHORS ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
+ * PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHORS
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY,
+ * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
+ * TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
+ * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ */
+
+#include <sys/cdefs.h>
+__FBSDID("$FreeBSD: stable/10/sys/mips/adm5120/uart_dev_adm5120.c 262649 2014-03-01 04:16:54Z imp $");
+
+#include <sys/param.h>
+#include <sys/systm.h>
+#include <sys/bus.h>
+#include <sys/conf.h>
+#include <machine/bus.h>
+
+#include <dev/uart/uart.h>
+#include <dev/uart/uart_cpu.h>
+#include <dev/uart/uart_bus.h>
+
+#include <mips/adm5120/uart_dev_adm5120.h>
+
+#include "uart_if.h"
+
+/*
+ * Low-level UART interface.
+ */
+static int adm5120_uart_probe(struct uart_bas *bas);
+static void adm5120_uart_init(struct uart_bas *bas, int, int, int, int);
+static void adm5120_uart_term(struct uart_bas *bas);
+static void adm5120_uart_putc(struct uart_bas *bas, int);
+static int adm5120_uart_rxready(struct uart_bas *bas);
+static int adm5120_uart_getc(struct uart_bas *bas, struct mtx *);
+
+static struct uart_ops uart_adm5120_uart_ops = {
+ .probe = adm5120_uart_probe,
+ .init = adm5120_uart_init,
+ .term = adm5120_uart_term,
+ .putc = adm5120_uart_putc,
+ .rxready = adm5120_uart_rxready,
+ .getc = adm5120_uart_getc,
+};
+
+static int
+adm5120_uart_probe(struct uart_bas *bas)
+{
+
+ return (0);
+}
+
+static void
+adm5120_uart_init(struct uart_bas *bas, int baudrate, int databits,
+ int stopbits, int parity)
+{
+
+ /* TODO: Set parameters for uart, meanwhile stick with 115200N1 */
+}
+
+static void
+adm5120_uart_term(struct uart_bas *bas)
+{
+
+}
+
+static void
+adm5120_uart_putc(struct uart_bas *bas, int c)
+{
+ char chr;
+ chr = c;
+ while (uart_getreg(bas, UART_FR_REG) & UART_FR_TX_FIFO_FULL)
+ ;
+ uart_setreg(bas, UART_DR_REG, c);
+ while (uart_getreg(bas, UART_FR_REG) & UART_FR_BUSY)
+ ;
+ uart_barrier(bas);
+}
+
+static int
+adm5120_uart_rxready(struct uart_bas *bas)
+{
+ if (uart_getreg(bas, UART_FR_REG) & UART_FR_RX_FIFO_EMPTY)
+ return (0);
+
+ return (1);
+}
+
+static int
+adm5120_uart_getc(struct uart_bas *bas, struct mtx *hwmtx)
+{
+ int c;
+
+ uart_lock(hwmtx);
+
+ while (uart_getreg(bas, UART_FR_REG) & UART_FR_RX_FIFO_EMPTY) {
+ uart_unlock(hwmtx);
+ DELAY(10);
+ uart_lock(hwmtx);
+ }
+
+ c = uart_getreg(bas, UART_DR_REG);
+
+ uart_unlock(hwmtx);
+
+ return (c);
+}
+
+/*
+ * High-level UART interface.
+ */
+struct adm5120_uart_softc {
+ struct uart_softc base;
+};
+
+static int adm5120_uart_bus_attach(struct uart_softc *);
+static int adm5120_uart_bus_detach(struct uart_softc *);
+static int adm5120_uart_bus_flush(struct uart_softc *, int);
+static int adm5120_uart_bus_getsig(struct uart_softc *);
+static int adm5120_uart_bus_ioctl(struct uart_softc *, int, intptr_t);
+static int adm5120_uart_bus_ipend(struct uart_softc *);
+static int adm5120_uart_bus_param(struct uart_softc *, int, int, int, int);
+static int adm5120_uart_bus_probe(struct uart_softc *);
+static int adm5120_uart_bus_receive(struct uart_softc *);
+static int adm5120_uart_bus_setsig(struct uart_softc *, int);
+static int adm5120_uart_bus_transmit(struct uart_softc *);
+static void adm5120_uart_bus_grab(struct uart_softc *);
+static void adm5120_uart_bus_ungrab(struct uart_softc *);
+
+static kobj_method_t adm5120_uart_methods[] = {
+ KOBJMETHOD(uart_attach, adm5120_uart_bus_attach),
+ KOBJMETHOD(uart_detach, adm5120_uart_bus_detach),
+ KOBJMETHOD(uart_flush, adm5120_uart_bus_flush),
+ KOBJMETHOD(uart_getsig, adm5120_uart_bus_getsig),
+ KOBJMETHOD(uart_ioctl, adm5120_uart_bus_ioctl),
+ KOBJMETHOD(uart_ipend, adm5120_uart_bus_ipend),
+ KOBJMETHOD(uart_param, adm5120_uart_bus_param),
+ KOBJMETHOD(uart_probe, adm5120_uart_bus_probe),
+ KOBJMETHOD(uart_receive, adm5120_uart_bus_receive),
+ KOBJMETHOD(uart_setsig, adm5120_uart_bus_setsig),
+ KOBJMETHOD(uart_transmit, adm5120_uart_bus_transmit),
+ KOBJMETHOD(uart_grab, adm5120_uart_bus_grab),
+ KOBJMETHOD(uart_ungrab, adm5120_uart_bus_ungrab),
+ { 0, 0 }
+};
+
+struct uart_class uart_adm5120_uart_class = {
+ "adm5120",
+ adm5120_uart_methods,
+ sizeof(struct adm5120_uart_softc),
+ .uc_ops = &uart_adm5120_uart_ops,
+ .uc_range = 1, /* use hinted range */
+ .uc_rclk = 62500000
+};
+
+#define SIGCHG(c, i, s, d) \
+ if (c) { \
+ i |= (i & s) ? s : s | d; \
+ } else { \
+ i = (i & s) ? (i & ~s) | d : i; \
+ }
+
+/*
+ * Disable TX interrupt. uart should be locked
+ */
+static __inline void
+adm5120_uart_disable_txintr(struct uart_softc *sc)
+{
+ uint8_t cr;
+
+ cr = uart_getreg(&sc->sc_bas, UART_CR_REG);
+ cr &= ~UART_CR_TX_INT_EN;
+ uart_setreg(&sc->sc_bas, UART_CR_REG, cr);
+}
+
+/*
+ * Enable TX interrupt. uart should be locked
+ */
+static __inline void
+adm5120_uart_enable_txintr(struct uart_softc *sc)
+{
+ uint8_t cr;
+
+ cr = uart_getreg(&sc->sc_bas, UART_CR_REG);
+ cr |= UART_CR_TX_INT_EN;
+ uart_setreg(&sc->sc_bas, UART_CR_REG, cr);
+}
+
+static int
+adm5120_uart_bus_attach(struct uart_softc *sc)
+{
+ struct uart_bas *bas;
+ struct uart_devinfo *di;
+
+ bas = &sc->sc_bas;
+ if (sc->sc_sysdev != NULL) {
+ di = sc->sc_sysdev;
+ /* TODO: set parameters from di */
+ } else {
+ /* TODO: set parameters 115200, 8N1 */
+ }
+
+ (void)adm5120_uart_bus_getsig(sc);
+
+#if 1
+ /* Enable FIFO */
+ uart_setreg(bas, UART_LCR_H_REG,
+ uart_getreg(bas, UART_LCR_H_REG) | UART_LCR_H_FEN);
+#endif
+ /* Enable interrupts */
+ uart_setreg(bas, UART_CR_REG,
+ UART_CR_PORT_EN|UART_CR_RX_INT_EN|UART_CR_RX_TIMEOUT_INT_EN|
+ UART_CR_MODEM_STATUS_INT_EN);
+
+ return (0);
+}
+
+static int
+adm5120_uart_bus_detach(struct uart_softc *sc)
+{
+
+ return (0);
+}
+
+static int
+adm5120_uart_bus_flush(struct uart_softc *sc, int what)
+{
+
+ return (0);
+}
+
+static int
+adm5120_uart_bus_getsig(struct uart_softc *sc)
+{
+ uint32_t new, old, sig;
+ uint8_t bes;
+
+ do {
+ old = sc->sc_hwsig;
+ sig = old;
+ uart_lock(sc->sc_hwmtx);
+ bes = uart_getreg(&sc->sc_bas, UART_FR_REG);
+ uart_unlock(sc->sc_hwmtx);
+ SIGCHG(bes & UART_FR_CTS, sig, SER_CTS, SER_DCTS);
+ SIGCHG(bes & UART_FR_DCD, sig, SER_DCD, SER_DDCD);
+ SIGCHG(bes & UART_FR_DSR, sig, SER_DSR, SER_DDSR);
+ new = sig & ~SER_MASK_DELTA;
+ } while (!atomic_cmpset_32(&sc->sc_hwsig, old, new));
+
+ return (sig);
+}
+
+static int
+adm5120_uart_bus_ioctl(struct uart_softc *sc, int request, intptr_t data)
+{
+ struct uart_bas *bas;
+ int baudrate, divisor, error;
+
+ bas = &sc->sc_bas;
+ error = 0;
+ uart_lock(sc->sc_hwmtx);
+ switch (request) {
+ case UART_IOCTL_BREAK:
+ /* TODO: Send BREAK */
+ break;
+ case UART_IOCTL_BAUD:
+ divisor = uart_getreg(bas, UART_LCR_M_REG);
+ divisor = (divisor << 8) |
+ uart_getreg(bas, UART_LCR_L_REG);
+ baudrate = bas->rclk / 2 / (divisor + 2);
+ *(int*)data = baudrate;
+ break;
+ default:
+ error = EINVAL;
+ break;
+ }
+ uart_unlock(sc->sc_hwmtx);
+ return (error);
+}
+
+static int
+adm5120_uart_bus_ipend(struct uart_softc *sc)
+{
+ struct uart_bas *bas;
+ int ipend;
+ uint8_t ir, fr, rsr;
+
+ bas = &sc->sc_bas;
+ ipend = 0;
+
+ uart_lock(sc->sc_hwmtx);
+ ir = uart_getreg(&sc->sc_bas, UART_IR_REG);
+ fr = uart_getreg(&sc->sc_bas, UART_FR_REG);
+ rsr = uart_getreg(&sc->sc_bas, UART_RSR_REG);
+
+ if (ir & UART_IR_RX_INT)
+ ipend |= SER_INT_RXREADY;
+
+ if (ir & UART_IR_RX_TIMEOUT_INT)
+ ipend |= SER_INT_RXREADY;
+
+ if (ir & UART_IR_MODEM_STATUS_INT)
+ ipend |= SER_INT_SIGCHG;
+
+ if (rsr & UART_RSR_BE)
+ ipend |= SER_INT_BREAK;
+
+ if (rsr & UART_RSR_OE)
+ ipend |= SER_INT_OVERRUN;
+
+ if (fr & UART_FR_TX_FIFO_EMPTY) {
+ if (ir & UART_IR_TX_INT) {
+ adm5120_uart_disable_txintr(sc);
+ ipend |= SER_INT_TXIDLE;
+ }
+ }
+
+ if (ipend)
+ uart_setreg(bas, UART_IR_REG, ir | UART_IR_UICR);
+
+ uart_unlock(sc->sc_hwmtx);
+
+ return (ipend);
+}
+
+static int
+adm5120_uart_bus_param(struct uart_softc *sc, int baudrate, int databits,
+ int stopbits, int parity)
+{
+
+ /* TODO: Set parameters for uart, meanwhile stick with 115200 8N1 */
+ return (0);
+}
+
+static int
+adm5120_uart_bus_probe(struct uart_softc *sc)
+{
+ char buf[80];
+ int error;
+ char ch;
+
+ error = adm5120_uart_probe(&sc->sc_bas);
+ if (error)
+ return (error);
+
+ sc->sc_rxfifosz = 16;
+ sc->sc_txfifosz = 16;
+
+ ch = sc->sc_bas.chan + 'A';
+
+ snprintf(buf, sizeof(buf), "adm5120_uart, channel %c", ch);
+ device_set_desc_copy(sc->sc_dev, buf);
+
+ return (0);
+}
+
+static int
+adm5120_uart_bus_receive(struct uart_softc *sc)
+{
+ struct uart_bas *bas;
+ int xc;
+ uint8_t fr, rsr;
+
+ bas = &sc->sc_bas;
+ uart_lock(sc->sc_hwmtx);
+ fr = uart_getreg(bas, UART_FR_REG);
+ while (!(fr & UART_FR_RX_FIFO_EMPTY)) {
+ if (uart_rx_full(sc)) {
+ sc->sc_rxbuf[sc->sc_rxput] = UART_STAT_OVERRUN;
+ break;
+ }
+ xc = 0;
+ rsr = uart_getreg(bas, UART_RSR_REG);
+ if (rsr & UART_RSR_FE)
+ xc |= UART_STAT_FRAMERR;
+ if (rsr & UART_RSR_PE)
+ xc |= UART_STAT_PARERR;
+ if (rsr & UART_RSR_OE)
+ xc |= UART_STAT_OVERRUN;
+ xc |= uart_getreg(bas, UART_DR_REG);
+ uart_barrier(bas);
+ uart_rx_put(sc, xc);
+ if (rsr & (UART_RSR_FE | UART_RSR_PE | UART_RSR_OE)) {
+ uart_setreg(bas, UART_ECR_REG, UART_ECR_RSR);
+ uart_barrier(bas);
+ }
+ fr = uart_getreg(bas, UART_FR_REG);
+ }
+
+ /* Discard everything left in the Rx FIFO. */
+ while (!(fr & UART_FR_RX_FIFO_EMPTY)) {
+ ( void)uart_getreg(bas, UART_DR_REG);
+ uart_barrier(bas);
+ rsr = uart_getreg(bas, UART_RSR_REG);
+ if (rsr & (UART_RSR_FE | UART_RSR_PE | UART_RSR_OE)) {
+ uart_setreg(bas, UART_ECR_REG, UART_ECR_RSR);
+ uart_barrier(bas);
+ }
+ fr = uart_getreg(bas, UART_FR_REG);
+ }
+ uart_unlock(sc->sc_hwmtx);
+ return (0);
+}
+
+static int
+adm5120_uart_bus_setsig(struct uart_softc *sc, int sig)
+{
+
+ /* TODO: implement (?) */
+ return (0);
+}
+
+static int
+adm5120_uart_bus_transmit(struct uart_softc *sc)
+{
+ struct uart_bas *bas;
+
+ bas = &sc->sc_bas;
+ uart_lock(sc->sc_hwmtx);
+ sc->sc_txbusy = 1;
+ for (int i = 0; i < sc->sc_txdatasz; i++) {
+ if (uart_getreg(bas, UART_FR_REG) & UART_FR_TX_FIFO_FULL)
+ break;
+ uart_setreg(bas, UART_DR_REG, sc->sc_txbuf[i]);
+ }
+
+ /* Enable TX interrupt */
+ adm5120_uart_enable_txintr(sc);
+ uart_unlock(sc->sc_hwmtx);
+ return (0);
+}
+
+static void
+adm5120_uart_bus_grab(struct uart_softc *sc)
+{
+
+ /* Enable interrupts - no RX_INT or RX_TIMEOUT */
+ uart_lock(sc->sc_hwmtx);
+ uart_setreg(&sc->sc_bas, UART_CR_REG,
+ UART_CR_PORT_EN | UART_CR_MODEM_STATUS_INT_EN);
+ uart_unlock(sc->sc_hwmtx);
+}
+
+static void
+adm5120_uart_bus_ungrab(struct uart_softc *sc)
+{
+
+ /* Enable interrupts */
+ uart_lock(sc->sc_hwmtx);
+ uart_setreg(&sc->sc_bas, UART_CR_REG,
+ UART_CR_PORT_EN|UART_CR_RX_INT_EN|UART_CR_RX_TIMEOUT_INT_EN|
+ UART_CR_MODEM_STATUS_INT_EN);
+ uart_unlock(sc->sc_hwmtx);
+}
Property changes on: trunk/sys/mips/adm5120/uart_dev_adm5120.c
___________________________________________________________________
Added: svn:eol-style
## -0,0 +1 ##
+native
\ No newline at end of property
Added: svn:keywords
## -0,0 +1 ##
+MidnightBSD=%H
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+text/plain
\ No newline at end of property
Added: trunk/sys/mips/adm5120/uart_dev_adm5120.h
===================================================================
--- trunk/sys/mips/adm5120/uart_dev_adm5120.h (rev 0)
+++ trunk/sys/mips/adm5120/uart_dev_adm5120.h 2018-05-26 21:55:02 UTC (rev 9987)
@@ -0,0 +1,81 @@
+/* $MidnightBSD$ */
+/* $NetBSD: uart.h,v 1.1 2007/03/20 08:52:02 dyoung Exp $ */
+
+/*-
+ * Copyright (c) 2007 Ruslan Ermilov and Vsevolod Lobko.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or
+ * without modification, are permitted provided that the following
+ * conditions are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above
+ * copyright notice, this list of conditions and the following
+ * disclaimer in the documentation and/or other materials provided
+ * with the distribution.
+ * 3. The names of the authors may not be used to endorse or promote
+ * products derived from this software without specific prior
+ * written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHORS ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
+ * PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHORS
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY,
+ * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
+ * TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
+ * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ *
+ * $FreeBSD: stable/10/sys/mips/adm5120/uart_dev_adm5120.h 202175 2010-01-12 21:36:08Z imp $
+ */
+#ifndef _ADMUART_H
+#define _ADMUART_H
+/* UART registers */
+#define UART_DR_REG 0x00
+#define UART_RSR_REG 0x04
+#define UART_RSR_FE 0x01
+#define UART_RSR_PE 0x02
+#define UART_RSR_BE 0x04
+#define UART_RSR_OE 0x08
+#define UART_ECR_REG 0x04
+#define UART_ECR_RSR 0x80
+#define UART_LCR_H_REG 0x08
+#define UART_LCR_H_FEN 0x10
+#define UART_LCR_M_REG 0x0c
+#define UART_LCR_L_REG 0x10
+#define UART_CR_REG 0x14
+#define UART_CR_PORT_EN 0x01
+#define UART_CR_SIREN 0x02
+#define UART_CR_SIRLP 0x04
+#define UART_CR_MODEM_STATUS_INT_EN 0x08
+#define UART_CR_RX_INT_EN 0x10
+#define UART_CR_TX_INT_EN 0x20
+#define UART_CR_RX_TIMEOUT_INT_EN 0x40
+#define UART_CR_LOOPBACK_EN 0x80
+#define UART_FR_REG 0x18
+#define UART_FR_CTS 0x01
+#define UART_FR_DSR 0x02
+#define UART_FR_DCD 0x04
+#define UART_FR_BUSY 0x08
+#define UART_FR_RX_FIFO_EMPTY 0x10
+#define UART_FR_TX_FIFO_FULL 0x20
+#define UART_FR_RX_FIFO_FULL 0x40
+#define UART_FR_TX_FIFO_EMPTY 0x80
+#define UART_IR_REG 0x1c
+#define UART_IR_MODEM_STATUS_INT 0x01
+#define UART_IR_RX_INT 0x02
+#define UART_IR_TX_INT 0x04
+#define UART_IR_RX_TIMEOUT_INT 0x08
+#define UART_IR_INT_MASK 0x0f
+#define UART_IR_UICR 0x80
+#define UART_ILPR_REG 0x20
+
+/* UART interrupts */
+
+int uart_cnattach(void);
+#endif /* _ADMUART_H */
Property changes on: trunk/sys/mips/adm5120/uart_dev_adm5120.h
___________________________________________________________________
Added: svn:eol-style
## -0,0 +1 ##
+native
\ No newline at end of property
Added: svn:keywords
## -0,0 +1 ##
+MidnightBSD=%H
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+text/plain
\ No newline at end of property
Added: trunk/sys/mips/alchemy/alchemy_machdep.c
===================================================================
--- trunk/sys/mips/alchemy/alchemy_machdep.c (rev 0)
+++ trunk/sys/mips/alchemy/alchemy_machdep.c 2018-05-26 21:55:02 UTC (rev 9987)
@@ -0,0 +1,149 @@
+/* $MidnightBSD$ */
+/*-
+ * Copyright (C) 2007 by Oleksandr Tymoshenko. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+ * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+ * IN NO EVENT SHALL THE AUTHOR OR HIS RELATIVES BE LIABLE FOR ANY DIRECT,
+ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF MIND, USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
+ * THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+#include <sys/cdefs.h>
+__FBSDID("$FreeBSD: stable/10/sys/mips/alchemy/alchemy_machdep.c 247297 2013-02-26 01:00:11Z attilio $");
+
+#include "opt_ddb.h"
+
+#include <sys/param.h>
+#include <sys/conf.h>
+#include <sys/kernel.h>
+#include <sys/systm.h>
+#include <sys/imgact.h>
+#include <sys/bio.h>
+#include <sys/buf.h>
+#include <sys/bus.h>
+#include <sys/cpu.h>
+#include <sys/cons.h>
+#include <sys/exec.h>
+#include <sys/ucontext.h>
+#include <sys/proc.h>
+#include <sys/kdb.h>
+#include <sys/ptrace.h>
+#include <sys/reboot.h>
+#include <sys/signalvar.h>
+#include <sys/sysent.h>
+#include <sys/sysproto.h>
+#include <sys/user.h>
+
+#include <vm/vm.h>
+#include <vm/vm_object.h>
+#include <vm/vm_page.h>
+
+#include <machine/cache.h>
+#include <machine/clock.h>
+#include <machine/cpu.h>
+#include <machine/cpuinfo.h>
+#include <machine/cpufunc.h>
+#include <machine/cpuregs.h>
+#include <machine/hwfunc.h>
+#include <machine/intr_machdep.h>
+#include <machine/locore.h>
+#include <machine/md_var.h>
+#include <machine/pte.h>
+#include <machine/sigframe.h>
+#include <machine/trap.h>
+#include <machine/vmparam.h>
+
+extern int *edata;
+extern int *end;
+
+void
+platform_cpu_init()
+{
+ /* Nothing special */
+}
+
+static void
+mips_init(void)
+{
+ int i;
+
+ printf("entry: mips_init()\n");
+
+ bootverbose = 1;
+ realmem = btoc(16 << 20);
+
+ for (i = 0; i < 10; i++) {
+ phys_avail[i] = 0;
+ }
+
+ /* phys_avail regions are in bytes */
+ phys_avail[0] = MIPS_KSEG0_TO_PHYS(kernel_kseg0_end);
+ phys_avail[1] = ctob(realmem);
+
+ dump_avail[0] = phys_avail[0];
+ dump_avail[1] = phys_avail[1];
+
+ physmem = realmem;
+
+ init_param1();
+ init_param2(physmem);
+ mips_cpu_init();
+ pmap_bootstrap();
+ mips_proc0_init();
+ mutex_init();
+
+ kdb_init();
+#ifdef KDB
+ if (boothowto & RB_KDB)
+ kdb_enter(KDB_WHY_BOOTFLAGS, "Boot flags requested debugger");
+#endif
+}
+
+void
+platform_reset(void)
+{
+
+ __asm __volatile("li $25, 0xbfc00000");
+ __asm __volatile("j $25");
+}
+
+void
+platform_start(__register_t a0 __unused, __register_t a1 __unused,
+ __register_t a2 __unused, __register_t a3 __unused)
+{
+ vm_offset_t kernend;
+ uint64_t platform_counter_freq = 175 * 1000 * 1000;
+
+ /* clear the BSS and SBSS segments */
+ kernend = (vm_offset_t)&end;
+ memset(&edata, 0, kernend - (vm_offset_t)(&edata));
+
+ mips_postboot_fixup();
+
+ /* Initialize pcpu stuff */
+ mips_pcpu0_init();
+
+ cninit();
+ mips_init();
+ /* Set counter_freq for tick_init_params() */
+ platform_counter_freq = 175 * 1000 * 1000;
+
+ mips_timer_init_params(platform_counter_freq, 0);
+}
Property changes on: trunk/sys/mips/alchemy/alchemy_machdep.c
___________________________________________________________________
Added: svn:eol-style
## -0,0 +1 ##
+native
\ No newline at end of property
Added: svn:keywords
## -0,0 +1 ##
+MidnightBSD=%H
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+text/plain
\ No newline at end of property
Added: trunk/sys/mips/alchemy/aureg.h
===================================================================
--- trunk/sys/mips/alchemy/aureg.h (rev 0)
+++ trunk/sys/mips/alchemy/aureg.h 2018-05-26 21:55:02 UTC (rev 9987)
@@ -0,0 +1,374 @@
+/* $MidnightBSD$ */
+/* $NetBSD: aureg.h,v 1.18 2006/10/02 06:44:00 gdamore Exp $ */
+
+/*
+ * Copyright 2002 Wasabi Systems, Inc.
+ * All rights reserved.
+ *
+ * Written by Simon Burge for Wasabi Systems, Inc.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * 3. All advertising materials mentioning features or use of this software
+ * must display the following acknowledgement:
+ * This product includes software developed for the NetBSD Project by
+ * Wasabi Systems, Inc.
+ * 4. The name of Wasabi Systems, Inc. may not be used to endorse
+ * or promote products derived from this software without specific prior
+ * written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef _MIPS_ALCHEMY_AUREG_H
+#define _MIPS_ALCHEMY_AUREG_H
+
+/************************************************************************/
+/******************** AC97 Controller registers *********************/
+/************************************************************************/
+#define AC97_BASE 0x10000000
+
+/************************************************************************/
+/*********************** USB Host registers *************************/
+/************************************************************************/
+#define USBH_BASE 0x10100000
+#define AU1550_USBH_BASE 0x14020000
+
+#define USBH_ENABLE 0x7fffc
+#define USBH_SIZE 0x100000
+
+#define AU1550_USBH_ENABLE 0x7ffc
+#define AU1550_USBH_SIZE 0x60000
+
+/************************************************************************/
+/********************** USB Device registers ************************/
+/************************************************************************/
+#define USBD_BASE 0x10200000
+
+/************************************************************************/
+/************************* IRDA registers ***************************/
+/************************************************************************/
+#define IRDA_BASE 0x10300000
+
+/************************************************************************/
+/****************** Interrupt Controller registers ******************/
+/************************************************************************/
+
+#define IC0_BASE 0x10400000
+#define IC1_BASE 0x11800000
+
+/*
+ * The *_READ registers read the current value of the register
+ * The *_SET registers set to 1 all bits that are written 1
+ * The *_CLEAR registers clear to zero all bits that are written as 1
+ */
+#define IC_CONFIG0_READ 0x40 /* See table below */
+#define IC_CONFIG0_SET 0x40
+#define IC_CONFIG0_CLEAR 0x44
+
+#define IC_CONFIG1_READ 0x48 /* See table below */
+#define IC_CONFIG1_SET 0x48
+#define IC_CONFIG1_CLEAR 0x4c
+
+#define IC_CONFIG2_READ 0x50 /* See table below */
+#define IC_CONFIG2_SET 0x50
+#define IC_CONFIG2_CLEAR 0x54
+
+#define IC_REQUEST0_INT 0x54 /* Show active interrupts on request 0 */
+
+#define IC_SOURCE_READ 0x58 /* Interrupt source */
+#define IC_SOURCE_SET 0x58 /* 0 - test bit used as source */
+#define IC_SOURCE_CLEAR 0x5c /* 1 - peripheral/GPIO used as source */
+
+#define IC_REQUEST1_INT 0x5c /* Show active interrupts on request 1 */
+
+#define IC_ASSIGN_REQUEST_READ 0x60 /* Assigns the interrupt to one of the */
+#define IC_ASSIGN_REQUEST_SET 0x60 /* CPU requests (0 - assign to request 1, */
+#define IC_ASSIGN_REQUEST_CLEAR 0x64 /* 1 - assign to request 0) */
+
+#define IC_WAKEUP_READ 0x68 /* Controls whether the interrupt can */
+#define IC_WAKEUP_SET 0x68 /* cause a wakeup from IDLE */
+#define IC_WAKEUP_CLEAR 0x6c
+
+#define IC_MASK_READ 0x70 /* Enables/Disables the interrupt */
+#define IC_MASK_SET 0x70
+#define IC_MASK_CLEAR 0x74
+
+#define IC_RISING_EDGE 0x78 /* Check/clear rising edge */
+
+#define IC_FALLING_EDGE 0x7c /* Check/clear falling edge */
+
+#define IC_TEST_BIT 0x80 /* single bit source select */
+
+/*
+ * Interrupt Configuration Register Functions
+ *
+ * Cfg2[n] Cfg1[n] Cfg0[n] Function
+ * 0 0 0 Interrupts Disabled
+ * 0 0 1 Rising Edge Enabled
+ * 0 1 0 Falling Edge Enabled
+ * 0 1 1 Rising and Falling Edge Enabled
+ * 1 0 0 Interrupts Disabled
+ * 1 0 1 High Level Enabled
+ * 1 1 0 Low Level Enabled
+ * 1 1 1 Both Levels and Both Edges Enabled
+ */
+
+/************************************************************************/
+/************* Programable Serial Controller registers **************/
+/************************************************************************/
+
+#define PSC0_BASE 0x11A00000
+#define PSC1_BASE 0x11B00000
+#define PSC2_BASE 0x10A00000
+#define PSC3_BASE 0x10B00000
+
+
+/************************************************************************/
+/********************** Ethernet MAC registers **********************/
+/************************************************************************/
+
+#define MAC0_BASE 0x10500000
+#define MAC1_BASE 0x10510000
+#define MACx_SIZE 0x28
+
+#define AU1500_MAC0_BASE 0x11500000 /* Grr, different on Au1500 */
+#define AU1500_MAC1_BASE 0x11510000 /* Grr, different on Au1500 */
+
+#define MAC0_ENABLE 0x10520000
+#define MAC1_ENABLE 0x10520004
+#define MACENx_SIZE 0x04
+
+#define AU1500_MAC0_ENABLE 0x11520000 /* Grr, different on Au1500 */
+#define AU1500_MAC1_ENABLE 0x11520004 /* Grr, different on Au1500 */
+
+#define MAC0_DMA_BASE 0x14004000
+#define MAC1_DMA_BASE 0x14004200
+#define MACx_DMA_SIZE 0x140
+
+/************************************************************************/
+/********************** Static Bus registers ************************/
+/************************************************************************/
+#define STATIC_BUS_BASE 0x14001000
+
+/************************************************************************/
+/******************** Secure Digital registers **********************/
+/************************************************************************/
+#define SD0_BASE 0x10600000
+#define SD1_BASE 0x10680000
+
+/************************************************************************/
+/************************* I^2S registers ***************************/
+/************************************************************************/
+#define I2S_BASE 0x11000000
+
+/************************************************************************/
+/************************** UART registers **************************/
+/************************************************************************/
+
+#define UART0_BASE 0x11100000
+#define UART1_BASE 0x11200000
+#define UART2_BASE 0x11300000
+#define UART3_BASE 0x11400000
+
+/************************************************************************/
+/************************* SSI registers ****************************/
+/************************************************************************/
+#define SSI0_BASE 0x11600000
+#define SSI1_BASE 0x11680000
+
+/************************************************************************/
+/************************ GPIO2 registers ***************************/
+/************************************************************************/
+#define GPIO_BASE 0x11900100
+
+/************************************************************************/
+/************************ GPIO2 registers ***************************/
+/************************************************************************/
+#define GPIO2_BASE 0x11700000
+
+/************************************************************************/
+/************************* PCI registers ****************************/
+/************************************************************************/
+#define PCI_BASE 0x14005000
+#define PCI_HEADER 0x14005100
+#define PCI_MEM_BASE 0x400000000ULL
+#define PCI_IO_BASE 0x500000000ULL
+#define PCI_CONFIG_BASE 0x600000000ULL
+
+/************************************************************************/
+/*********************** PCMCIA registers ***************************/
+/************************************************************************/
+#define PCMCIA_BASE 0xF00000000ULL
+
+/************************************************************************/
+/****************** Programmable Counter registers ******************/
+/************************************************************************/
+
+#define SYS_BASE 0x11900000
+
+#define PC_BASE SYS_BASE
+
+#define PC_TRIM0 0x00 /* PC0 Divide (16 bits) */
+#define PC_COUNTER_WRITE0 0x04 /* set PC0 */
+#define PC_MATCH0_0 0x08 /* match counter & interrupt */
+#define PC_MATCH1_0 0x0c /* match counter & interrupt */
+#define PC_MATCH2_0 0x10 /* match counter & interrupt */
+#define PC_COUNTER_CONTROL 0x14 /* Programmable Counter Control */
+#define CC_E1S 0x00800000 /* Enable PC1 write status */
+#define CC_T1S 0x00100000 /* Trim PC1 write status */
+#define CC_M21 0x00080000 /* Match 2 of PC1 write status */
+#define CC_M11 0x00040000 /* Match 1 of PC1 write status */
+#define CC_M01 0x00020000 /* Match 0 of PC1 write status */
+#define CC_C1S 0x00010000 /* PC1 write status */
+#define CC_BP 0x00004000 /* Bypass OSC (use GPIO1) */
+#define CC_EN1 0x00002000 /* Enable PC1 */
+#define CC_BT1 0x00001000 /* Bypass Trim on PC1 */
+#define CC_EN0 0x00000800 /* Enable PC0 */
+#define CC_BT0 0x00000400 /* Bypass Trim on PC0 */
+#define CC_EO 0x00000100 /* Enable Oscillator */
+#define CC_E0S 0x00000080 /* Enable PC0 write status */
+#define CC_32S 0x00000020 /* 32.768kHz OSC status */
+#define CC_T0S 0x00000010 /* Trim PC0 write status */
+#define CC_M20 0x00000008 /* Match 2 of PC0 write status */
+#define CC_M10 0x00000004 /* Match 1 of PC0 write status */
+#define CC_M00 0x00000002 /* Match 0 of PC0 write status */
+#define CC_C0S 0x00000001 /* PC0 write status */
+#define PC_COUNTER_READ_0 0x40 /* get PC0 */
+#define PC_TRIM1 0x44 /* PC1 Divide (16 bits) */
+#define PC_COUNTER_WRITE1 0x48 /* set PC1 */
+#define PC_MATCH0_1 0x4c /* match counter & interrupt */
+#define PC_MATCH1_1 0x50 /* match counter & interrupt */
+#define PC_MATCH2_1 0x54 /* match counter & interrupt */
+#define PC_COUNTER_READ_1 0x58 /* get PC1 */
+
+#define PC_SIZE 0x5c /* size of register set */
+#define PC_RATE 32768 /* counter rate is 32.768kHz */
+
+/************************************************************************/
+/******************* Frequency Generator Registers ******************/
+/************************************************************************/
+
+#define SYS_FREQCTRL0 (SYS_BASE + 0x20)
+#define SFC_FRDIV2(f) (f<<22) /* 29:22. Freq Divider 2 */
+#define SFC_FE2 (1<<21) /* Freq generator output enable 2 */
+#define SFC_FS2 (1<<20) /* Freq generator source 2 */
+#define SFC_FRDIV1(f) (f<<12) /* 19:12. Freq Divider 1 */
+#define SFC_FE1 (1<<11) /* Freq generator output enable 1 */
+#define SFC_FS1 (1<<10) /* Freq generator source 1 */
+#define SFC_FRDIV0(f) (f<<2) /* 9:2. Freq Divider 0 */
+#define SFC_FE0 2 /* Freq generator output enable 0 */
+#define SFC_FS0 1 /* Freq generator source 0 */
+
+#define SYS_FREQCTRL1 (SYS_BASE + 0x24)
+#define SFC_FRDIV5(f) (f<<22) /* 29:22. Freq Divider 5 */
+#define SFC_FE5 (1<<21) /* Freq generator output enable 5 */
+#define SFC_FS5 (1<<20) /* Freq generator source 5 */
+#define SFC_FRDIV4(f) (f<<12) /* 19:12. Freq Divider 4 */
+#define SFC_FE4 (1<<11) /* Freq generator output enable 4 */
+#define SFC_FS4 (1<<10) /* Freq generator source 4 */
+#define SFC_FRDIV3(f) (f<<2) /* 9:2. Freq Divider 3 */
+#define SFC_FE3 2 /* Freq generator output enable 3 */
+#define SFC_FS3 1 /* Freq generator source 3 */
+
+/************************************************************************/
+/****************** Clock Source Control Registers ******************/
+/************************************************************************/
+
+#define SYS_CLKSRC (SYS_BASE + 0x28)
+#define SCS_ME1(n) (n<<27) /* EXTCLK1 Clock Mux input select */
+#define SCS_ME0(n) (n<<22) /* EXTCLK0 Clock Mux input select */
+#define SCS_MPC(n) (n<<17) /* PCI clock mux input select */
+#define SCS_MUH(n) (n<<12) /* USB Host clock mux input select */
+#define SCS_MUD(n) (n<<7) /* USB Device clock mux input select */
+#define SCS_MEx_AUX 0x1 /* Aux clock */
+#define SCS_MEx_FREQ0 0x2 /* FREQ0 */
+#define SCS_MEx_FREQ1 0x3 /* FREQ1 */
+#define SCS_MEx_FREQ2 0x4 /* FREQ2 */
+#define SCS_MEx_FREQ3 0x5 /* FREQ3 */
+#define SCS_MEx_FREQ4 0x6 /* FREQ4 */
+#define SCS_MEx_FREQ5 0x7 /* FREQ5 */
+#define SCS_DE1 (1<<26) /* EXTCLK1 clock divider select */
+#define SCS_CE1 (1<<25) /* EXTCLK1 clock select */
+#define SCS_DE0 (1<<21) /* EXTCLK0 clock divider select */
+#define SCS_CE0 (1<<20) /* EXTCLK0 clock select */
+#define SCS_DPC (1<<16) /* PCI clock divider select */
+#define SCS_CPC (1<<15) /* PCI clock select */
+#define SCS_DUH (1<<11) /* USB Host clock divider select */
+#define SCS_CUH (1<<10) /* USB Host clock select */
+#define SCS_DUD (1<<6) /* USB Device clock divider select */
+#define SCS_CUD (1<<5) /* USB Device clock select */
+/*
+ * Au1550 bits, needed for PSCs. Note that some bits collide with
+ * earlier parts. On Au1550, USB clocks (both device and host) are
+ * shared with PSC2, and must be configured for 48MHz. DBAU1550 YAMON
+ * does this by default. Also, EXTCLK0 is shared with PSC3. DBAU1550
+ * YAMON does not configure any clocks besides PSC2.
+ */
+#define SCS_MP3(n) (n<<22) /* psc3_intclock mux */
+#define SCS_DP3 (1<<21) /* psc3_intclock divider */
+#define SCS_CP3 (1<<20) /* psc3_intclock select */
+#define SCS_MP1(n) (n<<12) /* psc1_intclock mux */
+#define SCS_DP1 (1<<11) /* psc1_intclock divider */
+#define SCS_CP1 (1<<10) /* psc1_intclock select */
+#define SCS_MP0(n) (n<<7) /* psc0_intclock mux */
+#define SCS_DP0 (1<<6) /* psc0_intclock divider */
+#define SCS_CP0 (1<<5) /* psc0_intclock seelct */
+#define SCS_MP2(n) (n<<2) /* psc2_intclock mux */
+#define SCS_DP2 (1<<1) /* psc2_intclock divider */
+#define SCS_CP2 (1<<0) /* psc2_intclock select */
+
+/************************************************************************/
+/*************************** PIN Function *****************************/
+/************************************************************************/
+
+#define SYS_PINFUNC (SYS_BASE + 0x2c)
+#define SPF_PSC3_MASK (7<<20)
+#define SPF_PSC3_AC97 (0<<17) /* select AC97/SPI */
+#define SPF_PSC3_I2S (1<<17) /* select I2S */
+#define SPF_PSC3_SMBUS (3<<17) /* select SMbus */
+#define SPF_PSC3_GPIO (7<<17) /* select gpio215:211 */
+#define SPF_PSC2_MASK (7<<17)
+#define SPF_PSC2_AC97 (0<<17) /* select AC97/SPI */
+#define SPF_PSC2_I2S (1<<17) /* select I2S */
+#define SPF_PSC2_SMBUS (3<<17) /* select SMbus */
+#define SPF_PSC2_GPIO (7<<17) /* select gpio210:206*/
+#define SPF_CS (1<<16) /* extclk0 or 32kHz osc */
+#define SPF_USB (1<<15) /* host or device usb otg */
+#define SPF_U3T (1<<14) /* uart3 tx or gpio23 */
+#define SPF_U1R (1<<13) /* uart1 rx or gpio22 */
+#define SPF_U1T (1<<12) /* uart1 tx or gpio21 */
+#define SPF_EX1 (1<<10) /* gpio3 or extclk1 */
+#define SPF_EX0 (1<<9) /* gpio2 or extclk0/32kHz osc*/
+#define SPF_U3 (1<<7) /* gpio14:9 or uart3 */
+#define SPF_MBSa (1<<5) /* must be set */
+#define SPF_NI2 (1<<4) /* enet1 or gpio28:24 */
+#define SPF_U0 (1<<3) /* uart0 or gpio20 */
+#define SPF_MBSb (1<<2) /* must be set */
+#define SPF_S1 (1<<1) /* gpio17 or psc1_sync1 */
+#define SPF_S0 (1<<0) /* gpio16 or psc0_sync1 */
+
+/************************************************************************/
+/*************************** PLL Control *****************************/
+/************************************************************************/
+
+#define SYS_CPUPLL (SYS_BASE + 0x60)
+#define SYS_AUXPLL (SYS_BASE + 0x64)
+
+#endif /* _MIPS_ALCHEMY_AUREG_H */
Property changes on: trunk/sys/mips/alchemy/aureg.h
___________________________________________________________________
Added: svn:eol-style
## -0,0 +1 ##
+native
\ No newline at end of property
Added: svn:keywords
## -0,0 +1 ##
+MidnightBSD=%H
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+text/plain
\ No newline at end of property
Added: trunk/sys/mips/alchemy/files.alchemy
===================================================================
--- trunk/sys/mips/alchemy/files.alchemy (rev 0)
+++ trunk/sys/mips/alchemy/files.alchemy 2018-05-26 21:55:02 UTC (rev 9987)
@@ -0,0 +1,9 @@
+# $FreeBSD: stable/10/sys/mips/alchemy/files.alchemy 202175 2010-01-12 21:36:08Z imp $
+# Alchmy on-board devices
+# mips/alchemy/console.c standard
+mips/alchemy/alchemy_machdep.c standard
+mips/alchemy/obio.c standard
+mips/alchemy/uart_bus_alchemy.c optional uart
+mips/alchemy/uart_cpu_alchemy.c optional uart
+mips/mips/intr_machdep.c standard
+mips/mips/tick.c standard
Property changes on: trunk/sys/mips/alchemy/files.alchemy
___________________________________________________________________
Added: mnbsd:nokeywords
## -0,0 +1 ##
+MidnightBSD=%H
\ No newline at end of property
Added: trunk/sys/mips/alchemy/obio.c
===================================================================
--- trunk/sys/mips/alchemy/obio.c (rev 0)
+++ trunk/sys/mips/alchemy/obio.c 2018-05-26 21:55:02 UTC (rev 9987)
@@ -0,0 +1,537 @@
+/* $MidnightBSD$ */
+/* $NetBSD: obio.c,v 1.11 2003/07/15 00:25:05 lukem Exp $ */
+
+/*-
+ * Copyright (c) 2001, 2002, 2003 Wasabi Systems, Inc.
+ * All rights reserved.
+ *
+ * Written by Jason R. Thorpe for Wasabi Systems, Inc.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * 3. All advertising materials mentioning features or use of this software
+ * must display the following acknowledgement:
+ * This product includes software developed for the NetBSD Project by
+ * Wasabi Systems, Inc.
+ * 4. The name of Wasabi Systems, Inc. may not be used to endorse
+ * or promote products derived from this software without specific prior
+ * written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <sys/cdefs.h>
+__FBSDID("$FreeBSD: stable/10/sys/mips/alchemy/obio.c 265999 2014-05-14 01:35:43Z ian $");
+
+#include <sys/param.h>
+#include <sys/systm.h>
+#include <sys/bus.h>
+#include <sys/interrupt.h>
+#include <sys/kernel.h>
+#include <sys/module.h>
+#include <sys/rman.h>
+#include <sys/malloc.h>
+
+#include <machine/bus.h>
+
+#include <mips/adm5120/adm5120reg.h>
+#include <mips/adm5120/obiovar.h>
+
+/* MIPS HW interrupts of IRQ/FIQ respectively */
+#define ADM5120_INTR 0
+#define ADM5120_FAST_INTR 1
+
+/* Interrupt levels */
+#define INTR_IRQ 0
+#define INTR_FIQ 1
+
+int irq_priorities[NIRQS] = {
+ INTR_IRQ, /* flash */
+ INTR_FIQ, /* uart0 */
+ INTR_FIQ, /* uart1 */
+ INTR_IRQ, /* ahci */
+ INTR_IRQ, /* unknown */
+ INTR_IRQ, /* unknown */
+ INTR_IRQ, /* unknown */
+ INTR_IRQ, /* unknown */
+ INTR_IRQ, /* unknown */
+ INTR_IRQ, /* admsw */
+ INTR_IRQ, /* unknown */
+ INTR_IRQ, /* unknown */
+ INTR_IRQ, /* unknown */
+ INTR_IRQ, /* unknown */
+ INTR_IRQ, /* unknown */
+ INTR_IRQ, /* unknown */
+ INTR_IRQ, /* unknown */
+ INTR_IRQ, /* unknown */
+ INTR_IRQ, /* unknown */
+ INTR_IRQ, /* unknown */
+ INTR_IRQ, /* unknown */
+ INTR_IRQ, /* unknown */
+ INTR_IRQ, /* unknown */
+ INTR_IRQ, /* unknown */
+ INTR_IRQ, /* unknown */
+ INTR_IRQ, /* unknown */
+ INTR_IRQ, /* unknown */
+ INTR_IRQ, /* unknown */
+ INTR_IRQ, /* unknown */
+ INTR_IRQ, /* unknown */
+ INTR_IRQ, /* unknown */
+ INTR_IRQ, /* unknown */
+};
+
+
+#define REG_READ(o) *((volatile uint32_t *)MIPS_PHYS_TO_KSEG1(ADM5120_BASE_ICU + (o)))
+#define REG_WRITE(o,v) (REG_READ(o)) = (v)
+
+static int obio_activate_resource(device_t, device_t, int, int,
+ struct resource *);
+static device_t obio_add_child(device_t, u_int, const char *, int);
+static struct resource *
+ obio_alloc_resource(device_t, device_t, int, int *, u_long,
+ u_long, u_long, u_int);
+static int obio_attach(device_t);
+static int obio_deactivate_resource(device_t, device_t, int, int,
+ struct resource *);
+static struct resource_list *
+ obio_get_resource_list(device_t, device_t);
+static void obio_hinted_child(device_t, const char *, int);
+static int obio_intr(void *);
+static int obio_probe(device_t);
+static int obio_release_resource(device_t, device_t, int, int,
+ struct resource *);
+static int obio_setup_intr(device_t, device_t, struct resource *, int,
+ driver_filter_t *, driver_intr_t *, void *, void **);
+static int obio_teardown_intr(device_t, device_t, struct resource *,
+ void *);
+
+static void
+obio_mask_irq(void *arg)
+{
+ /* XXX need to write */
+#if 0
+ unsigned int irq = (unsigned int)arg;
+ int ip_bit, mask, mask_register;
+
+ /* mask IRQ */
+ mask_register = ICU_IRQ_MASK_REG(irq);
+ ip_bit = ICU_IP_BIT(irq);
+
+ mask = ICU_REG_READ(mask_register);
+ ICU_REG_WRITE(mask_register, mask | ip_bit);
+#endif
+}
+
+static void
+obio_unmask_irq(void *arg)
+{
+ /* XXX need to write */
+#if 0
+ unsigned int irq = (unsigned int)arg;
+ int ip_bit, mask, mask_register;
+
+ /* unmask IRQ */
+ mask_register = ICU_IRQ_MASK_REG(irq);
+ ip_bit = ICU_IP_BIT(irq);
+
+ mask = ICU_REG_READ(mask_register);
+ ICU_REG_WRITE(mask_register, mask & ~ip_bit);
+#endif
+}
+
+static int
+obio_probe(device_t dev)
+{
+
+ return (BUS_PROBE_NOWILDCARD);
+}
+
+static int
+obio_attach(device_t dev)
+{
+ struct obio_softc *sc = device_get_softc(dev);
+ int rid;
+
+ sc->oba_mem_rman.rm_type = RMAN_ARRAY;
+ sc->oba_mem_rman.rm_descr = "OBIO memeory";
+ if (rman_init(&sc->oba_mem_rman) != 0 ||
+ rman_manage_region(&sc->oba_mem_rman, OBIO_MEM_START,
+ OBIO_MEM_START + OBIO_MEM_SIZE) != 0)
+ panic("obio_attach: failed to set up I/O rman");
+
+ sc->oba_irq_rman.rm_type = RMAN_ARRAY;
+ sc->oba_irq_rman.rm_descr = "OBIO IRQ";
+
+ if (rman_init(&sc->oba_irq_rman) != 0 ||
+ rman_manage_region(&sc->oba_irq_rman, 0, NIRQS-1) != 0)
+ panic("obio_attach: failed to set up IRQ rman");
+
+ /* Hook up our interrupt handler. */
+ if ((sc->sc_irq = bus_alloc_resource(dev, SYS_RES_IRQ, &rid,
+ ADM5120_INTR, ADM5120_INTR, 1,
+ RF_SHAREABLE | RF_ACTIVE)) == NULL) {
+ device_printf(dev, "unable to allocate IRQ resource\n");
+ return (ENXIO);
+ }
+
+ if ((bus_setup_intr(dev, sc->sc_irq, INTR_TYPE_MISC, obio_intr, NULL,
+ sc, &sc->sc_ih))) {
+ device_printf(dev,
+ "WARNING: unable to register interrupt handler\n");
+ return (ENXIO);
+ }
+
+ /* Hook up our FAST interrupt handler. */
+ if ((sc->sc_fast_irq = bus_alloc_resource(dev, SYS_RES_IRQ, &rid,
+ ADM5120_FAST_INTR, ADM5120_FAST_INTR, 1,
+ RF_SHAREABLE | RF_ACTIVE)) == NULL) {
+ device_printf(dev, "unable to allocate IRQ resource\n");
+ return (ENXIO);
+ }
+
+ if ((bus_setup_intr(dev, sc->sc_fast_irq, INTR_TYPE_MISC, obio_intr,
+ NULL, sc, &sc->sc_fast_ih))) {
+ device_printf(dev,
+ "WARNING: unable to register interrupt handler\n");
+ return (ENXIO);
+ }
+
+ /* disable all interrupts */
+ REG_WRITE(ICU_ENABLE_REG, ICU_INT_MASK);
+
+ bus_generic_probe(dev);
+ bus_enumerate_hinted_children(dev);
+ bus_generic_attach(dev);
+
+ return (0);
+}
+
+static struct resource *
+obio_alloc_resource(device_t bus, device_t child, int type, int *rid,
+ u_long start, u_long end, u_long count, u_int flags)
+{
+ struct obio_softc *sc = device_get_softc(bus);
+ struct obio_ivar *ivar = device_get_ivars(child);
+ struct resource *rv;
+ struct resource_list_entry *rle;
+ struct rman *rm;
+ int isdefault, needactivate, passthrough;
+
+ isdefault = (start == 0UL && end == ~0UL && count == 1);
+ needactivate = flags & RF_ACTIVE;
+ passthrough = (device_get_parent(child) != bus);
+ rle = NULL;
+
+ if (passthrough)
+ return (BUS_ALLOC_RESOURCE(device_get_parent(bus), child, type,
+ rid, start, end, count, flags));
+
+ /*
+ * If this is an allocation of the "default" range for a given RID,
+ * and we know what the resources for this device are (ie. they aren't
+ * maintained by a child bus), then work out the start/end values.
+ */
+ if (isdefault) {
+ rle = resource_list_find(&ivar->resources, type, *rid);
+ if (rle == NULL)
+ return (NULL);
+ if (rle->res != NULL) {
+ panic("%s: resource entry is busy", __func__);
+ }
+ start = rle->start;
+ end = rle->end;
+ count = rle->count;
+ }
+
+ switch (type) {
+ case SYS_RES_IRQ:
+ rm = &sc->oba_irq_rman;
+ break;
+ case SYS_RES_MEMORY:
+ rm = &sc->oba_mem_rman;
+ break;
+ default:
+ printf("%s: unknown resource type %d\n", __func__, type);
+ return (0);
+ }
+
+ rv = rman_reserve_resource(rm, start, end, count, flags, child);
+ if (rv == 0) {
+ printf("%s: could not reserve resource\n", __func__);
+ return (0);
+ }
+
+ rman_set_rid(rv, *rid);
+
+ if (needactivate) {
+ if (bus_activate_resource(child, type, *rid, rv)) {
+ printf("%s: could not activate resource\n", __func__);
+ rman_release_resource(rv);
+ return (0);
+ }
+ }
+
+ return (rv);
+}
+
+static int
+obio_activate_resource(device_t bus, device_t child, int type, int rid,
+ struct resource *r)
+{
+
+ /*
+ * If this is a memory resource, track the direct mapping
+ * in the uncached MIPS KSEG1 segment.
+ */
+ if (type == SYS_RES_MEMORY) {
+ void *vaddr;
+
+ vaddr = (void *)MIPS_PHYS_TO_KSEG1((intptr_t)rman_get_start(r));
+ rman_set_virtual(r, vaddr);
+ rman_set_bustag(r, mips_bus_space_generic);
+ rman_set_bushandle(r, (bus_space_handle_t)vaddr);
+ }
+
+ return (rman_activate_resource(r));
+}
+
+static int
+obio_deactivate_resource(device_t bus, device_t child, int type, int rid,
+ struct resource *r)
+{
+
+ return (rman_deactivate_resource(r));
+}
+
+static int
+obio_release_resource(device_t dev, device_t child, int type,
+ int rid, struct resource *r)
+{
+ struct resource_list *rl;
+ struct resource_list_entry *rle;
+
+ rl = obio_get_resource_list(dev, child);
+ if (rl == NULL)
+ return (EINVAL);
+ rle = resource_list_find(rl, type, rid);
+ if (rle == NULL)
+ return (EINVAL);
+ rman_release_resource(r);
+ rle->res = NULL;
+
+ return (0);
+}
+
+static int
+obio_setup_intr(device_t dev, device_t child, struct resource *ires,
+ int flags, driver_filter_t *filt, driver_intr_t *handler,
+ void *arg, void **cookiep)
+{
+ struct obio_softc *sc = device_get_softc(dev);
+ struct intr_event *event;
+ int irq, error, priority;
+ uint32_t irqmask;
+
+ irq = rman_get_start(ires);
+
+ if (irq >= NIRQS)
+ panic("%s: bad irq %d", __func__, irq);
+
+ event = sc->sc_eventstab[irq];
+ if (event == NULL) {
+ error = intr_event_create(&event, (void *)irq, 0, irq,
+ obio_mask_irq, obio_unmask_irq,
+ NULL, NULL,
+ "obio intr%d:", irq);
+
+ sc->sc_eventstab[irq] = event;
+ }
+ else
+ panic("obio: Can't share IRQs");
+
+ intr_event_add_handler(event, device_get_nameunit(child), filt,
+ handler, arg, intr_priority(flags), flags, cookiep);
+
+ irqmask = 1 << irq;
+ priority = irq_priorities[irq];
+
+ if (priority == INTR_FIQ)
+ REG_WRITE(ICU_MODE_REG, REG_READ(ICU_MODE_REG) | irqmask);
+ else
+ REG_WRITE(ICU_MODE_REG, REG_READ(ICU_MODE_REG) & ~irqmask);
+
+ /* enable */
+ REG_WRITE(ICU_ENABLE_REG, irqmask);
+
+ return (0);
+}
+
+static int
+obio_teardown_intr(device_t dev, device_t child, struct resource *ires,
+ void *cookie)
+{
+ struct obio_softc *sc = device_get_softc(dev);
+ int irq, result;
+ uint32_t irqmask;
+
+ irq = rman_get_start(ires);
+ if (irq >= NIRQS)
+ panic("%s: bad irq %d", __func__, irq);
+
+ if (sc->sc_eventstab[irq] == NULL)
+ panic("Trying to teardown unoccupied IRQ");
+
+ irqmask = 1 << irq; /* only used as a mask from here on */
+
+ /* disable this irq in HW */
+ REG_WRITE(ICU_DISABLE_REG, irqmask);
+
+ result = intr_event_remove_handler(cookie);
+ if (!result) {
+ sc->sc_eventstab[irq] = NULL;
+ }
+
+ return (result);
+}
+
+static int
+obio_intr(void *arg)
+{
+ struct obio_softc *sc = arg;
+ struct intr_event *event;
+ uint32_t irqstat;
+ int irq;
+
+ irqstat = REG_READ(ICU_FIQ_STATUS_REG);
+ irqstat |= REG_READ(ICU_STATUS_REG);
+
+ irq = 0;
+ while (irqstat != 0) {
+ if ((irqstat & 1) == 1) {
+ event = sc->sc_eventstab[irq];
+ if (!event || TAILQ_EMPTY(&event->ie_handlers))
+ continue;
+
+ /* TODO: pass frame as an argument*/
+ /* TODO: log stray interrupt */
+ intr_event_handle(event, NULL);
+ }
+
+ irq++;
+ irqstat >>= 1;
+ }
+
+ return (FILTER_HANDLED);
+}
+
+static void
+obio_hinted_child(device_t bus, const char *dname, int dunit)
+{
+ device_t child;
+ long maddr;
+ int msize;
+ int irq;
+ int result;
+
+ child = BUS_ADD_CHILD(bus, 0, dname, dunit);
+
+ /*
+ * Set hard-wired resources for hinted child using
+ * specific RIDs.
+ */
+ resource_long_value(dname, dunit, "maddr", &maddr);
+ resource_int_value(dname, dunit, "msize", &msize);
+
+
+ result = bus_set_resource(child, SYS_RES_MEMORY, 0,
+ maddr, msize);
+ if (result != 0)
+ device_printf(bus, "warning: bus_set_resource() failed\n");
+
+ if (resource_int_value(dname, dunit, "irq", &irq) == 0) {
+ result = bus_set_resource(child, SYS_RES_IRQ, 0, irq, 1);
+ if (result != 0)
+ device_printf(bus,
+ "warning: bus_set_resource() failed\n");
+ }
+}
+
+static device_t
+obio_add_child(device_t bus, u_int order, const char *name, int unit)
+{
+ device_t child;
+ struct obio_ivar *ivar;
+
+ ivar = malloc(sizeof(struct obio_ivar), M_DEVBUF, M_WAITOK | M_ZERO);
+ if (ivar == NULL) {
+ printf("Failed to allocate ivar\n");
+ return (0);
+ }
+ resource_list_init(&ivar->resources);
+
+ child = device_add_child_ordered(bus, order, name, unit);
+ if (child == NULL) {
+ printf("Can't add child %s%d ordered\n", name, unit);
+ return (0);
+ }
+
+ device_set_ivars(child, ivar);
+
+ return (child);
+}
+
+/*
+ * Helper routine for bus_generic_rl_get_resource/bus_generic_rl_set_resource
+ * Provides pointer to resource_list for these routines
+ */
+static struct resource_list *
+obio_get_resource_list(device_t dev, device_t child)
+{
+ struct obio_ivar *ivar;
+
+ ivar = device_get_ivars(child);
+ return (&(ivar->resources));
+}
+
+static device_method_t obio_methods[] = {
+ DEVMETHOD(bus_activate_resource, obio_activate_resource),
+ DEVMETHOD(bus_add_child, obio_add_child),
+ DEVMETHOD(bus_alloc_resource, obio_alloc_resource),
+ DEVMETHOD(bus_deactivate_resource, obio_deactivate_resource),
+ DEVMETHOD(bus_get_resource_list, obio_get_resource_list),
+ DEVMETHOD(bus_hinted_child, obio_hinted_child),
+ DEVMETHOD(bus_release_resource, obio_release_resource),
+ DEVMETHOD(bus_setup_intr, obio_setup_intr),
+ DEVMETHOD(bus_teardown_intr, obio_teardown_intr),
+ DEVMETHOD(device_attach, obio_attach),
+ DEVMETHOD(device_probe, obio_probe),
+ DEVMETHOD(bus_get_resource, bus_generic_rl_get_resource),
+ DEVMETHOD(bus_set_resource, bus_generic_rl_set_resource),
+
+ {0, 0},
+};
+
+static driver_t obio_driver = {
+ "obio",
+ obio_methods,
+ sizeof(struct obio_softc),
+};
+static devclass_t obio_devclass;
+
+DRIVER_MODULE(obio, nexus, obio_driver, obio_devclass, 0, 0);
Property changes on: trunk/sys/mips/alchemy/obio.c
___________________________________________________________________
Added: svn:eol-style
## -0,0 +1 ##
+native
\ No newline at end of property
Added: svn:keywords
## -0,0 +1 ##
+MidnightBSD=%H
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+text/plain
\ No newline at end of property
Added: trunk/sys/mips/alchemy/std.alchemy
===================================================================
--- trunk/sys/mips/alchemy/std.alchemy (rev 0)
+++ trunk/sys/mips/alchemy/std.alchemy 2018-05-26 21:55:02 UTC (rev 9987)
@@ -0,0 +1,8 @@
+# $FreeBSD: stable/10/sys/mips/alchemy/std.alchemy 232896 2012-03-12 21:25:32Z jmallett $
+# Standard include file for Alchemy Au1xxx CPUs:
+# Au1000, Au1200, Au1250, Au1500 and Au1550
+
+files "../alchemy/files.alchemy"
+
+machine mips mipsel
+cpu CPU_MIPS4KC
Property changes on: trunk/sys/mips/alchemy/std.alchemy
___________________________________________________________________
Added: mnbsd:nokeywords
## -0,0 +1 ##
+MidnightBSD=%H
\ No newline at end of property
Added: trunk/sys/mips/alchemy/uart_bus_alchemy.c
===================================================================
--- trunk/sys/mips/alchemy/uart_bus_alchemy.c (rev 0)
+++ trunk/sys/mips/alchemy/uart_bus_alchemy.c 2018-05-26 21:55:02 UTC (rev 9987)
@@ -0,0 +1,88 @@
+/* $MidnightBSD$ */
+/*-
+ * Copyright (c) 2007 Bruce M. Simpson.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * $Id$
+ */
+/*
+ * Skeleton of this file was based on respective code for ARM
+ * code written by Olivier Houchard.
+ */
+
+#include "opt_uart.h"
+
+#include <sys/cdefs.h>
+__FBSDID("$FreeBSD: stable/10/sys/mips/alchemy/uart_bus_alchemy.c 187498 2009-01-20 22:42:37Z imp $");
+
+#include <sys/param.h>
+#include <sys/systm.h>
+#include <sys/bus.h>
+#include <sys/conf.h>
+#include <sys/kernel.h>
+#include <sys/module.h>
+#include <machine/bus.h>
+#include <sys/rman.h>
+#include <machine/resource.h>
+
+#include <dev/pci/pcivar.h>
+
+#include <dev/uart/uart.h>
+#include <dev/uart/uart_bus.h>
+#include <dev/uart/uart_cpu.h>
+
+#include <mips/alchemy/aureg.h>
+
+#include "uart_if.h"
+
+static int uart_alchemy_probe(device_t dev);
+
+static device_method_t uart_alchemy_methods[] = {
+ /* Device interface */
+ DEVMETHOD(device_probe, uart_alchemy_probe),
+ DEVMETHOD(device_attach, uart_bus_attach),
+ DEVMETHOD(device_detach, uart_bus_detach),
+ { 0, 0 }
+};
+
+static driver_t uart_alchemy_driver = {
+ uart_driver_name,
+ uart_alchemy_methods,
+ sizeof(struct uart_softc),
+};
+
+extern SLIST_HEAD(uart_devinfo_list, uart_devinfo) uart_sysdevs;
+
+static int
+uart_alchemy_probe(device_t dev)
+{
+ struct uart_softc *sc;
+
+ sc = device_get_softc(dev);
+ sc->sc_sysdev = SLIST_FIRST(&uart_sysdevs);
+ sc->sc_class = &uart_ns8250_class;
+ bcopy(&sc->sc_sysdev->bas, &sc->sc_bas, sizeof(sc->sc_bas));
+
+ return (uart_bus_probe(dev, 0, 0, 0, 0));
+}
+
+DRIVER_MODULE(uart, obio, uart_alchemy_driver, uart_devclass, 0, 0);
Property changes on: trunk/sys/mips/alchemy/uart_bus_alchemy.c
___________________________________________________________________
Added: svn:eol-style
## -0,0 +1 ##
+native
\ No newline at end of property
Added: svn:keywords
## -0,0 +1 ##
+MidnightBSD=%H
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+text/plain
\ No newline at end of property
Added: trunk/sys/mips/alchemy/uart_cpu_alchemy.c
===================================================================
--- trunk/sys/mips/alchemy/uart_cpu_alchemy.c (rev 0)
+++ trunk/sys/mips/alchemy/uart_cpu_alchemy.c 2018-05-26 21:55:02 UTC (rev 9987)
@@ -0,0 +1,80 @@
+/* $MidnightBSD$ */
+/*-
+ * Copyright (c) 2006 Wojciech A. Koszek <wkoszek at FreeBSD.org>
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ * $Id$
+ */
+/*
+ * Skeleton of this file was based on respective code for ARM
+ * code written by Olivier Houchard.
+ */
+
+#include "opt_uart.h"
+
+#include <sys/cdefs.h>
+__FBSDID("$FreeBSD: stable/10/sys/mips/alchemy/uart_cpu_alchemy.c 191282 2009-04-19 22:02:14Z gonzo $");
+
+#include <sys/param.h>
+#include <sys/systm.h>
+#include <sys/bus.h>
+#include <sys/cons.h>
+
+#include <machine/bus.h>
+
+#include <dev/uart/uart.h>
+#include <dev/uart/uart_cpu.h>
+
+#include <mips/alchemy/aureg.h>
+
+bus_space_tag_t uart_bus_space_io;
+bus_space_tag_t uart_bus_space_mem;
+
+int
+uart_cpu_eqres(struct uart_bas *b1, struct uart_bas *b2)
+{
+
+ return ((b1->bsh == b2->bsh && b1->bst == b2->bst) ? 1 : 0);
+}
+
+int
+uart_cpu_getdev(int devtype, struct uart_devinfo *di)
+{
+
+ di->ops = uart_getops(&uart_ns8250_class);
+ di->bas.chan = 0;
+ di->bas.bst = mips_bus_space_generic;
+ di->bas.regshft = 0;
+ di->bas.rclk = 0;
+ di->baudrate = 115200;
+ di->databits = 8;
+ di->stopbits = 1;
+ di->parity = UART_PARITY_NONE;
+
+ uart_bus_space_io = 0;
+ uart_bus_space_mem = mips_bus_space_generic;
+ di->bas.bsh = MIPS_PHYS_TO_KSEG1(UART0_BASE);
+
+ return (0);
+}
Property changes on: trunk/sys/mips/alchemy/uart_cpu_alchemy.c
___________________________________________________________________
Added: svn:eol-style
## -0,0 +1 ##
+native
\ No newline at end of property
Added: svn:keywords
## -0,0 +1 ##
+MidnightBSD=%H
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+text/plain
\ No newline at end of property
Added: trunk/sys/mips/atheros/apb.c
===================================================================
--- trunk/sys/mips/atheros/apb.c (rev 0)
+++ trunk/sys/mips/atheros/apb.c 2018-05-26 21:55:02 UTC (rev 9987)
@@ -0,0 +1,506 @@
+/* $MidnightBSD$ */
+/*-
+ * Copyright (c) 2009, Oleksandr Tymoshenko <gonzo at FreeBSD.org>
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice unmodified, this list of conditions, and the following
+ * disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ */
+
+#include <sys/cdefs.h>
+__FBSDID("$FreeBSD: stable/10/sys/mips/atheros/apb.c 265999 2014-05-14 01:35:43Z ian $");
+
+#include <sys/param.h>
+#include <sys/systm.h>
+#include <sys/bus.h>
+#include <sys/interrupt.h>
+#include <sys/kernel.h>
+#include <sys/module.h>
+#include <sys/rman.h>
+#include <sys/malloc.h>
+#include <sys/pcpu.h>
+#include <sys/proc.h>
+#include <sys/pmc.h>
+#include <sys/pmckern.h>
+
+#include <machine/bus.h>
+#include <machine/intr_machdep.h>
+
+#include <mips/atheros/apbvar.h>
+#include <mips/atheros/ar71xxreg.h>
+#include <mips/atheros/ar71xx_setup.h>
+
+#define APB_INTR_PMC 5
+
+#undef APB_DEBUG
+#ifdef APB_DEBUG
+#define dprintf printf
+#else
+#define dprintf(x, arg...)
+#endif /* APB_DEBUG */
+
+static int apb_activate_resource(device_t, device_t, int, int,
+ struct resource *);
+static device_t apb_add_child(device_t, u_int, const char *, int);
+static struct resource *
+ apb_alloc_resource(device_t, device_t, int, int *, u_long,
+ u_long, u_long, u_int);
+static int apb_attach(device_t);
+static int apb_deactivate_resource(device_t, device_t, int, int,
+ struct resource *);
+static struct resource_list *
+ apb_get_resource_list(device_t, device_t);
+static void apb_hinted_child(device_t, const char *, int);
+static int apb_filter(void *);
+static int apb_probe(device_t);
+static int apb_release_resource(device_t, device_t, int, int,
+ struct resource *);
+static int apb_setup_intr(device_t, device_t, struct resource *, int,
+ driver_filter_t *, driver_intr_t *, void *, void **);
+static int apb_teardown_intr(device_t, device_t, struct resource *,
+ void *);
+
+static void
+apb_mask_irq(void *source)
+{
+ unsigned int irq = (unsigned int)source;
+ uint32_t reg;
+
+ reg = ATH_READ_REG(AR71XX_MISC_INTR_MASK);
+ ATH_WRITE_REG(AR71XX_MISC_INTR_MASK, reg & ~(1 << irq));
+
+}
+
+static void
+apb_unmask_irq(void *source)
+{
+ uint32_t reg;
+ unsigned int irq = (unsigned int)source;
+
+ reg = ATH_READ_REG(AR71XX_MISC_INTR_MASK);
+ ATH_WRITE_REG(AR71XX_MISC_INTR_MASK, reg | (1 << irq));
+}
+
+static int
+apb_probe(device_t dev)
+{
+
+ return (BUS_PROBE_NOWILDCARD);
+}
+
+static int
+apb_attach(device_t dev)
+{
+ struct apb_softc *sc = device_get_softc(dev);
+ int rid = 0;
+
+ device_set_desc(dev, "APB Bus bridge");
+
+ sc->apb_mem_rman.rm_type = RMAN_ARRAY;
+ sc->apb_mem_rman.rm_descr = "APB memory window";
+
+ if (rman_init(&sc->apb_mem_rman) != 0 ||
+ rman_manage_region(&sc->apb_mem_rman,
+ AR71XX_APB_BASE,
+ AR71XX_APB_BASE + AR71XX_APB_SIZE - 1) != 0)
+ panic("apb_attach: failed to set up memory rman");
+
+ sc->apb_irq_rman.rm_type = RMAN_ARRAY;
+ sc->apb_irq_rman.rm_descr = "APB IRQ";
+
+ if (rman_init(&sc->apb_irq_rman) != 0 ||
+ rman_manage_region(&sc->apb_irq_rman,
+ APB_IRQ_BASE, APB_IRQ_END) != 0)
+ panic("apb_attach: failed to set up IRQ rman");
+
+ if ((sc->sc_misc_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
+ RF_SHAREABLE | RF_ACTIVE)) == NULL) {
+ device_printf(dev, "unable to allocate IRQ resource\n");
+ return (ENXIO);
+ }
+
+ if ((bus_setup_intr(dev, sc->sc_misc_irq, INTR_TYPE_MISC,
+ apb_filter, NULL, sc, &sc->sc_misc_ih))) {
+ device_printf(dev,
+ "WARNING: unable to register interrupt handler\n");
+ return (ENXIO);
+ }
+
+ bus_generic_probe(dev);
+ bus_enumerate_hinted_children(dev);
+ bus_generic_attach(dev);
+
+ /*
+ * Unmask performance counter IRQ
+ */
+ apb_unmask_irq((void*)APB_INTR_PMC);
+ sc->sc_intr_counter[APB_INTR_PMC] = mips_intrcnt_create("apb irq5: pmc");
+
+ return (0);
+}
+
+static struct resource *
+apb_alloc_resource(device_t bus, device_t child, int type, int *rid,
+ u_long start, u_long end, u_long count, u_int flags)
+{
+ struct apb_softc *sc = device_get_softc(bus);
+ struct apb_ivar *ivar = device_get_ivars(child);
+ struct resource *rv;
+ struct resource_list_entry *rle;
+ struct rman *rm;
+ int isdefault, needactivate, passthrough;
+
+ isdefault = (start == 0UL && end == ~0UL);
+ needactivate = flags & RF_ACTIVE;
+ /*
+ * Pass memory requests to nexus device
+ */
+ passthrough = (device_get_parent(child) != bus);
+ rle = NULL;
+
+ dprintf("%s: entry (%p, %p, %d, %d, %p, %p, %ld, %d)\n",
+ __func__, bus, child, type, *rid, (void *)(intptr_t)start,
+ (void *)(intptr_t)end, count, flags);
+
+ if (passthrough)
+ return (BUS_ALLOC_RESOURCE(device_get_parent(bus), child, type,
+ rid, start, end, count, flags));
+
+ /*
+ * If this is an allocation of the "default" range for a given RID,
+ * and we know what the resources for this device are (ie. they aren't
+ * maintained by a child bus), then work out the start/end values.
+ */
+
+ if (isdefault) {
+ rle = resource_list_find(&ivar->resources, type, *rid);
+ if (rle == NULL) {
+ return (NULL);
+ }
+
+ if (rle->res != NULL) {
+ panic("%s: resource entry is busy", __func__);
+ }
+ start = rle->start;
+ end = rle->end;
+ count = rle->count;
+
+ dprintf("%s: default resource (%p, %p, %ld)\n",
+ __func__, (void *)(intptr_t)start,
+ (void *)(intptr_t)end, count);
+ }
+
+ switch (type) {
+ case SYS_RES_IRQ:
+ rm = &sc->apb_irq_rman;
+ break;
+ case SYS_RES_MEMORY:
+ rm = &sc->apb_mem_rman;
+ break;
+ default:
+ printf("%s: unknown resource type %d\n", __func__, type);
+ return (0);
+ }
+
+ rv = rman_reserve_resource(rm, start, end, count, flags, child);
+ if (rv == 0) {
+ printf("%s: could not reserve resource\n", __func__);
+ return (0);
+ }
+
+ rman_set_rid(rv, *rid);
+
+ if (needactivate) {
+ if (bus_activate_resource(child, type, *rid, rv)) {
+ printf("%s: could not activate resource\n", __func__);
+ rman_release_resource(rv);
+ return (0);
+ }
+ }
+
+ return (rv);
+}
+
+static int
+apb_activate_resource(device_t bus, device_t child, int type, int rid,
+ struct resource *r)
+{
+
+ /* XXX: should we mask/unmask IRQ here? */
+ return (BUS_ACTIVATE_RESOURCE(device_get_parent(bus), child,
+ type, rid, r));
+}
+
+static int
+apb_deactivate_resource(device_t bus, device_t child, int type, int rid,
+ struct resource *r)
+{
+
+ /* XXX: should we mask/unmask IRQ here? */
+ return (BUS_DEACTIVATE_RESOURCE(device_get_parent(bus), child,
+ type, rid, r));
+}
+
+static int
+apb_release_resource(device_t dev, device_t child, int type,
+ int rid, struct resource *r)
+{
+ struct resource_list *rl;
+ struct resource_list_entry *rle;
+
+ rl = apb_get_resource_list(dev, child);
+ if (rl == NULL)
+ return (EINVAL);
+ rle = resource_list_find(rl, type, rid);
+ if (rle == NULL)
+ return (EINVAL);
+ rman_release_resource(r);
+ rle->res = NULL;
+
+ return (0);
+}
+
+static int
+apb_setup_intr(device_t bus, device_t child, struct resource *ires,
+ int flags, driver_filter_t *filt, driver_intr_t *handler,
+ void *arg, void **cookiep)
+{
+ struct apb_softc *sc = device_get_softc(bus);
+ struct intr_event *event;
+ int irq, error;
+
+ irq = rman_get_start(ires);
+
+ if (irq > APB_IRQ_END)
+ panic("%s: bad irq %d", __func__, irq);
+
+ event = sc->sc_eventstab[irq];
+ if (event == NULL) {
+ error = intr_event_create(&event, (void *)irq, 0, irq,
+ apb_mask_irq, apb_unmask_irq,
+ NULL, NULL,
+ "apb intr%d:", irq);
+
+ if (error == 0) {
+ sc->sc_eventstab[irq] = event;
+ sc->sc_intr_counter[irq] =
+ mips_intrcnt_create(event->ie_name);
+ }
+ else
+ return (error);
+ }
+
+ intr_event_add_handler(event, device_get_nameunit(child), filt,
+ handler, arg, intr_priority(flags), flags, cookiep);
+ mips_intrcnt_setname(sc->sc_intr_counter[irq], event->ie_fullname);
+
+ apb_unmask_irq((void*)irq);
+
+ return (0);
+}
+
+static int
+apb_teardown_intr(device_t dev, device_t child, struct resource *ires,
+ void *cookie)
+{
+ struct apb_softc *sc = device_get_softc(dev);
+ int irq, result;
+
+ irq = rman_get_start(ires);
+ if (irq > APB_IRQ_END)
+ panic("%s: bad irq %d", __func__, irq);
+
+ if (sc->sc_eventstab[irq] == NULL)
+ panic("Trying to teardown unoccupied IRQ");
+
+ apb_mask_irq((void*)irq);
+
+ result = intr_event_remove_handler(cookie);
+ if (!result)
+ sc->sc_eventstab[irq] = NULL;
+
+ return (result);
+}
+
+static int
+apb_filter(void *arg)
+{
+ struct apb_softc *sc = arg;
+ struct intr_event *event;
+ uint32_t reg, irq;
+ struct thread *td;
+ struct trapframe *tf;
+
+ reg = ATH_READ_REG(AR71XX_MISC_INTR_STATUS);
+ for (irq = 0; irq < APB_NIRQS; irq++) {
+ if (reg & (1 << irq)) {
+
+ switch (ar71xx_soc) {
+ case AR71XX_SOC_AR7240:
+ case AR71XX_SOC_AR7241:
+ case AR71XX_SOC_AR7242:
+ case AR71XX_SOC_AR9330:
+ case AR71XX_SOC_AR9331:
+ case AR71XX_SOC_AR9341:
+ case AR71XX_SOC_AR9342:
+ case AR71XX_SOC_AR9344:
+ /* Ack/clear the irq on status register for AR724x */
+ ATH_WRITE_REG(AR71XX_MISC_INTR_STATUS,
+ reg & ~(1 << irq));
+ break;
+ default:
+ /* fallthrough */
+ break;
+ }
+
+ event = sc->sc_eventstab[irq];
+ if (!event || TAILQ_EMPTY(&event->ie_handlers)) {
+ if (irq == APB_INTR_PMC) {
+ td = PCPU_GET(curthread);
+ tf = td->td_intr_frame;
+
+ if (pmc_intr)
+ (*pmc_intr)(PCPU_GET(cpuid), tf);
+
+ mips_intrcnt_inc(sc->sc_intr_counter[irq]);
+
+ continue;
+ }
+ /* Ignore timer interrupts */
+ if (irq != 0)
+ printf("Stray APB IRQ %d\n", irq);
+ continue;
+ }
+
+ intr_event_handle(event, PCPU_GET(curthread)->td_intr_frame);
+ mips_intrcnt_inc(sc->sc_intr_counter[irq]);
+ }
+ }
+
+ return (FILTER_HANDLED);
+}
+
+static void
+apb_hinted_child(device_t bus, const char *dname, int dunit)
+{
+ device_t child;
+ long maddr;
+ int msize;
+ int irq;
+ int result;
+ int mem_hints_count;
+
+ child = BUS_ADD_CHILD(bus, 0, dname, dunit);
+
+ /*
+ * Set hard-wired resources for hinted child using
+ * specific RIDs.
+ */
+ mem_hints_count = 0;
+ if (resource_long_value(dname, dunit, "maddr", &maddr) == 0)
+ mem_hints_count++;
+ if (resource_int_value(dname, dunit, "msize", &msize) == 0)
+ mem_hints_count++;
+
+ /* check if all info for mem resource has been provided */
+ if ((mem_hints_count > 0) && (mem_hints_count < 2)) {
+ printf("Either maddr or msize hint is missing for %s%d\n",
+ dname, dunit);
+ } else if (mem_hints_count) {
+ result = bus_set_resource(child, SYS_RES_MEMORY, 0,
+ maddr, msize);
+ if (result != 0)
+ device_printf(bus,
+ "warning: bus_set_resource() failed\n");
+ }
+
+ if (resource_int_value(dname, dunit, "irq", &irq) == 0) {
+ result = bus_set_resource(child, SYS_RES_IRQ, 0, irq, 1);
+ if (result != 0)
+ device_printf(bus,
+ "warning: bus_set_resource() failed\n");
+ }
+}
+
+static device_t
+apb_add_child(device_t bus, u_int order, const char *name, int unit)
+{
+ device_t child;
+ struct apb_ivar *ivar;
+
+ ivar = malloc(sizeof(struct apb_ivar), M_DEVBUF, M_WAITOK | M_ZERO);
+ if (ivar == NULL) {
+ printf("Failed to allocate ivar\n");
+ return (0);
+ }
+ resource_list_init(&ivar->resources);
+
+ child = device_add_child_ordered(bus, order, name, unit);
+ if (child == NULL) {
+ printf("Can't add child %s%d ordered\n", name, unit);
+ return (0);
+ }
+
+ device_set_ivars(child, ivar);
+
+ return (child);
+}
+
+/*
+ * Helper routine for bus_generic_rl_get_resource/bus_generic_rl_set_resource
+ * Provides pointer to resource_list for these routines
+ */
+static struct resource_list *
+apb_get_resource_list(device_t dev, device_t child)
+{
+ struct apb_ivar *ivar;
+
+ ivar = device_get_ivars(child);
+ return (&(ivar->resources));
+}
+
+static device_method_t apb_methods[] = {
+ DEVMETHOD(bus_activate_resource, apb_activate_resource),
+ DEVMETHOD(bus_add_child, apb_add_child),
+ DEVMETHOD(bus_alloc_resource, apb_alloc_resource),
+ DEVMETHOD(bus_deactivate_resource, apb_deactivate_resource),
+ DEVMETHOD(bus_get_resource_list, apb_get_resource_list),
+ DEVMETHOD(bus_hinted_child, apb_hinted_child),
+ DEVMETHOD(bus_release_resource, apb_release_resource),
+ DEVMETHOD(bus_setup_intr, apb_setup_intr),
+ DEVMETHOD(bus_teardown_intr, apb_teardown_intr),
+ DEVMETHOD(device_attach, apb_attach),
+ DEVMETHOD(device_probe, apb_probe),
+ DEVMETHOD(bus_get_resource, bus_generic_rl_get_resource),
+ DEVMETHOD(bus_set_resource, bus_generic_rl_set_resource),
+
+ DEVMETHOD_END
+};
+
+static driver_t apb_driver = {
+ "apb",
+ apb_methods,
+ sizeof(struct apb_softc),
+};
+static devclass_t apb_devclass;
+
+DRIVER_MODULE(apb, nexus, apb_driver, apb_devclass, 0, 0);
Property changes on: trunk/sys/mips/atheros/apb.c
___________________________________________________________________
Added: svn:eol-style
## -0,0 +1 ##
+native
\ No newline at end of property
Added: svn:keywords
## -0,0 +1 ##
+MidnightBSD=%H
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+text/plain
\ No newline at end of property
Added: trunk/sys/mips/atheros/apbvar.h
===================================================================
--- trunk/sys/mips/atheros/apbvar.h (rev 0)
+++ trunk/sys/mips/atheros/apbvar.h 2018-05-26 21:55:02 UTC (rev 9987)
@@ -0,0 +1,51 @@
+/* $MidnightBSD$ */
+/*-
+ * Copyright (c) 2009, Oleksandr Tymoshenko <gonzo at FreeBSD.org>
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice unmodified, this list of conditions, and the following
+ * disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ */
+
+#ifndef _APBVAR_H_
+#define _APBVAR_H_
+
+#define APB_IRQ_BASE 0
+#define APB_IRQ_END 7
+#define APB_NIRQS 8
+
+struct apb_softc {
+ struct rman apb_irq_rman;
+ struct rman apb_mem_rman;
+ /* IRQ events structs for child devices */
+ struct intr_event *sc_eventstab[APB_NIRQS];
+ mips_intrcnt_t sc_intr_counter[APB_NIRQS];
+ /* Resources and cookies for MIPS CPU INTs */
+ struct resource *sc_misc_irq;
+ void *sc_misc_ih;
+};
+
+struct apb_ivar {
+ struct resource_list resources;
+};
+
+#endif /* _APBVAR_H_ */
Property changes on: trunk/sys/mips/atheros/apbvar.h
___________________________________________________________________
Added: svn:eol-style
## -0,0 +1 ##
+native
\ No newline at end of property
Added: svn:keywords
## -0,0 +1 ##
+MidnightBSD=%H
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+text/plain
\ No newline at end of property
Added: trunk/sys/mips/atheros/ar71xx_bus_space_reversed.c
===================================================================
--- trunk/sys/mips/atheros/ar71xx_bus_space_reversed.c (rev 0)
+++ trunk/sys/mips/atheros/ar71xx_bus_space_reversed.c 2018-05-26 21:55:02 UTC (rev 9987)
@@ -0,0 +1,182 @@
+/* $MidnightBSD$ */
+/*-
+ * Copyright (c) 2009, Oleksandr Tymoshenko <gonzo at FreeBSD.org>
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice unmodified, this list of conditions, and the following
+ * disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ */
+#include <sys/cdefs.h>
+__FBSDID("$FreeBSD: stable/10/sys/mips/atheros/ar71xx_bus_space_reversed.c 202175 2010-01-12 21:36:08Z imp $");
+
+#include <sys/param.h>
+#include <sys/systm.h>
+#include <sys/bus.h>
+
+#include <machine/bus.h>
+#include <mips/atheros/ar71xx_bus_space_reversed.h>
+
+static bs_r_1_proto(reversed);
+static bs_r_2_proto(reversed);
+static bs_w_1_proto(reversed);
+static bs_w_2_proto(reversed);
+
+/*
+ * Bus space that handles offsets in word for 1/2 bytes read/write access.
+ * Byte order of values is handled by device drivers itself.
+ */
+static struct bus_space bus_space_reversed = {
+ /* cookie */
+ (void *) 0,
+
+ /* mapping/unmapping */
+ generic_bs_map,
+ generic_bs_unmap,
+ generic_bs_subregion,
+
+ /* allocation/deallocation */
+ NULL,
+ NULL,
+
+ /* barrier */
+ generic_bs_barrier,
+
+ /* read (single) */
+ reversed_bs_r_1,
+ reversed_bs_r_2,
+ generic_bs_r_4,
+ NULL,
+
+ /* read multiple */
+ generic_bs_rm_1,
+ generic_bs_rm_2,
+ generic_bs_rm_4,
+ NULL,
+
+ /* read region */
+ generic_bs_rr_1,
+ generic_bs_rr_2,
+ generic_bs_rr_4,
+ NULL,
+
+ /* write (single) */
+ reversed_bs_w_1,
+ reversed_bs_w_2,
+ generic_bs_w_4,
+ NULL,
+
+ /* write multiple */
+ generic_bs_wm_1,
+ generic_bs_wm_2,
+ generic_bs_wm_4,
+ NULL,
+
+ /* write region */
+ NULL,
+ generic_bs_wr_2,
+ generic_bs_wr_4,
+ NULL,
+
+ /* set multiple */
+ NULL,
+ NULL,
+ NULL,
+ NULL,
+
+ /* set region */
+ NULL,
+ generic_bs_sr_2,
+ generic_bs_sr_4,
+ NULL,
+
+ /* copy */
+ NULL,
+ generic_bs_c_2,
+ NULL,
+ NULL,
+
+ /* read (single) stream */
+ generic_bs_r_1,
+ generic_bs_r_2,
+ generic_bs_r_4,
+ NULL,
+
+ /* read multiple stream */
+ generic_bs_rm_1,
+ generic_bs_rm_2,
+ generic_bs_rm_4,
+ NULL,
+
+ /* read region stream */
+ generic_bs_rr_1,
+ generic_bs_rr_2,
+ generic_bs_rr_4,
+ NULL,
+
+ /* write (single) stream */
+ generic_bs_w_1,
+ generic_bs_w_2,
+ generic_bs_w_4,
+ NULL,
+
+ /* write multiple stream */
+ generic_bs_wm_1,
+ generic_bs_wm_2,
+ generic_bs_wm_4,
+ NULL,
+
+ /* write region stream */
+ NULL,
+ generic_bs_wr_2,
+ generic_bs_wr_4,
+ NULL,
+};
+
+bus_space_tag_t ar71xx_bus_space_reversed = &bus_space_reversed;
+
+static uint8_t
+reversed_bs_r_1(void *t, bus_space_handle_t h, bus_size_t o)
+{
+
+ return readb(h + (o &~ 3) + (3 - (o & 3)));
+}
+
+static void
+reversed_bs_w_1(void *t, bus_space_handle_t h, bus_size_t o, u_int8_t v)
+{
+
+ writeb(h + (o &~ 3) + (3 - (o & 3)), v);
+}
+
+static uint16_t
+reversed_bs_r_2(void *t, bus_space_handle_t h, bus_size_t o)
+{
+
+ return readw(h + (o &~ 3) + (2 - (o & 3)));
+}
+
+static void
+reversed_bs_w_2(void *t, bus_space_handle_t h, bus_size_t o, uint16_t v)
+{
+
+ writew(h + (o &~ 3) + (2 - (o & 3)), v);
+}
Property changes on: trunk/sys/mips/atheros/ar71xx_bus_space_reversed.c
___________________________________________________________________
Added: svn:eol-style
## -0,0 +1 ##
+native
\ No newline at end of property
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## -0,0 +1 ##
+MidnightBSD=%H
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## -0,0 +1 ##
+text/plain
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Added: trunk/sys/mips/atheros/ar71xx_bus_space_reversed.h
===================================================================
--- trunk/sys/mips/atheros/ar71xx_bus_space_reversed.h (rev 0)
+++ trunk/sys/mips/atheros/ar71xx_bus_space_reversed.h 2018-05-26 21:55:02 UTC (rev 9987)
@@ -0,0 +1,34 @@
+/* $MidnightBSD$ */
+/*-
+ * Copyright (c) 2009, Oleksandr Tymoshenko <gonzo at FreeBSD.org>
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice unmodified, this list of conditions, and the following
+ * disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ */
+
+#ifndef __AR71XX_BUS_SPACE_REVERSEDH__
+#define __AR71XX_BUS_SPACE_REVERSEDH__
+
+extern bus_space_tag_t ar71xx_bus_space_reversed;
+
+#endif /* __AR71XX_BUS_SPACE_REVERSEDH__ */
Property changes on: trunk/sys/mips/atheros/ar71xx_bus_space_reversed.h
___________________________________________________________________
Added: svn:eol-style
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+native
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+MidnightBSD=%H
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## -0,0 +1 ##
+text/plain
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Added: trunk/sys/mips/atheros/ar71xx_chip.c
===================================================================
--- trunk/sys/mips/atheros/ar71xx_chip.c (rev 0)
+++ trunk/sys/mips/atheros/ar71xx_chip.c 2018-05-26 21:55:02 UTC (rev 9987)
@@ -0,0 +1,341 @@
+/* $MidnightBSD$ */
+/*-
+ * Copyright (c) 2010 Adrian Chadd
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ */
+
+#include <sys/cdefs.h>
+__FBSDID("$FreeBSD: stable/10/sys/mips/atheros/ar71xx_chip.c 253508 2013-07-21 03:52:52Z adrian $");
+
+#include "opt_ddb.h"
+
+#include <sys/param.h>
+#include <sys/conf.h>
+#include <sys/kernel.h>
+#include <sys/systm.h>
+#include <sys/bus.h>
+#include <sys/cons.h>
+#include <sys/kdb.h>
+#include <sys/reboot.h>
+
+#include <vm/vm.h>
+#include <vm/vm_page.h>
+
+#include <net/ethernet.h>
+
+#include <machine/clock.h>
+#include <machine/cpu.h>
+#include <machine/cpuregs.h>
+#include <machine/hwfunc.h>
+#include <machine/md_var.h>
+#include <machine/trap.h>
+#include <machine/vmparam.h>
+
+#include <mips/atheros/ar71xxreg.h>
+#include <mips/atheros/ar71xx_chip.h>
+#include <mips/atheros/ar71xx_cpudef.h>
+
+#include <mips/sentry5/s5reg.h>
+
+/* XXX these should replace the current definitions in ar71xxreg.h */
+/* XXX perhaps an ar71xx_chip.h header file? */
+#define AR71XX_PLL_REG_CPU_CONFIG AR71XX_PLL_CPU_BASE + 0x00
+#define AR71XX_PLL_REG_SEC_CONFIG AR71XX_PLL_CPU_BASE + 0x04
+#define AR71XX_PLL_REG_ETH0_INT_CLOCK AR71XX_PLL_CPU_BASE + 0x10
+#define AR71XX_PLL_REG_ETH1_INT_CLOCK AR71XX_PLL_CPU_BASE + 0x14
+
+#define AR71XX_PLL_DIV_SHIFT 3
+#define AR71XX_PLL_DIV_MASK 0x1f
+#define AR71XX_CPU_DIV_SHIFT 16
+#define AR71XX_CPU_DIV_MASK 0x3
+#define AR71XX_DDR_DIV_SHIFT 18
+#define AR71XX_DDR_DIV_MASK 0x3
+#define AR71XX_AHB_DIV_SHIFT 20
+#define AR71XX_AHB_DIV_MASK 0x7
+
+/* XXX these shouldn't be in here - this file is a per-chip file */
+/* XXX these should be in the top-level ar71xx type, not ar71xx -chip */
+uint32_t u_ar71xx_cpu_freq;
+uint32_t u_ar71xx_ahb_freq;
+uint32_t u_ar71xx_ddr_freq;
+uint32_t u_ar71xx_uart_freq;
+uint32_t u_ar71xx_wdt_freq;
+uint32_t u_ar71xx_refclk;
+
+static void
+ar71xx_chip_detect_mem_size(void)
+{
+}
+
+static void
+ar71xx_chip_detect_sys_frequency(void)
+{
+ uint32_t pll;
+ uint32_t freq;
+ uint32_t div;
+
+ u_ar71xx_refclk = AR71XX_BASE_FREQ;
+
+ pll = ATH_READ_REG(AR71XX_PLL_REG_CPU_CONFIG);
+
+ div = ((pll >> AR71XX_PLL_DIV_SHIFT) & AR71XX_PLL_DIV_MASK) + 1;
+ freq = div * AR71XX_BASE_FREQ;
+
+ div = ((pll >> AR71XX_CPU_DIV_SHIFT) & AR71XX_CPU_DIV_MASK) + 1;
+ u_ar71xx_cpu_freq = freq / div;
+
+ div = ((pll >> AR71XX_DDR_DIV_SHIFT) & AR71XX_DDR_DIV_MASK) + 1;
+ u_ar71xx_ddr_freq = freq / div;
+
+ div = (((pll >> AR71XX_AHB_DIV_SHIFT) & AR71XX_AHB_DIV_MASK) + 1) * 2;
+ u_ar71xx_ahb_freq = u_ar71xx_cpu_freq / div;
+ u_ar71xx_wdt_freq = u_ar71xx_cpu_freq / div;
+ u_ar71xx_uart_freq = u_ar71xx_cpu_freq / div;
+}
+
+/*
+ * This does not lock the CPU whilst doing the work!
+ */
+static void
+ar71xx_chip_device_stop(uint32_t mask)
+{
+ uint32_t reg;
+
+ reg = ATH_READ_REG(AR71XX_RST_RESET);
+ ATH_WRITE_REG(AR71XX_RST_RESET, reg | mask);
+}
+
+static void
+ar71xx_chip_device_start(uint32_t mask)
+{
+ uint32_t reg;
+
+ reg = ATH_READ_REG(AR71XX_RST_RESET);
+ ATH_WRITE_REG(AR71XX_RST_RESET, reg & ~mask);
+}
+
+static int
+ar71xx_chip_device_stopped(uint32_t mask)
+{
+ uint32_t reg;
+
+ reg = ATH_READ_REG(AR71XX_RST_RESET);
+ return ((reg & mask) == mask);
+}
+
+void
+ar71xx_chip_set_mii_speed(uint32_t unit, uint32_t speed)
+{
+ uint32_t val, reg, ctrl;
+
+ switch (unit) {
+ case 0:
+ reg = AR71XX_MII0_CTRL;
+ break;
+ case 1:
+ reg = AR71XX_MII1_CTRL;
+ break;
+ default:
+ printf("%s: invalid MII unit set for arge unit: %d\n",
+ __func__, unit);
+ return;
+ }
+
+ switch (speed) {
+ case 10:
+ ctrl = MII_CTRL_SPEED_10;
+ break;
+ case 100:
+ ctrl = MII_CTRL_SPEED_100;
+ break;
+ case 1000:
+ ctrl = MII_CTRL_SPEED_1000;
+ break;
+ default:
+ printf("%s: invalid MII speed (%d) set for arge unit: %d\n",
+ __func__, speed, unit);
+ return;
+ }
+
+ val = ATH_READ_REG(reg);
+ val &= ~(MII_CTRL_SPEED_MASK << MII_CTRL_SPEED_SHIFT);
+ val |= (ctrl & MII_CTRL_SPEED_MASK) << MII_CTRL_SPEED_SHIFT;
+ ATH_WRITE_REG(reg, val);
+}
+
+void
+ar71xx_chip_set_mii_if(uint32_t unit, uint32_t mii_mode)
+{
+ uint32_t val, reg, mii_if;
+
+ switch (unit) {
+ case 0:
+ reg = AR71XX_MII0_CTRL;
+ if (mii_mode == AR71XX_MII_MODE_GMII)
+ mii_if = MII0_CTRL_IF_GMII;
+ else if (mii_mode == AR71XX_MII_MODE_MII)
+ mii_if = MII0_CTRL_IF_MII;
+ else if (mii_mode == AR71XX_MII_MODE_RGMII)
+ mii_if = MII0_CTRL_IF_RGMII;
+ else if (mii_mode == AR71XX_MII_MODE_RMII)
+ mii_if = MII0_CTRL_IF_RMII;
+ else {
+ printf("%s: invalid MII mode (%d) for unit %d\n",
+ __func__, mii_mode, unit);
+ return;
+ }
+ break;
+ case 1:
+ reg = AR71XX_MII1_CTRL;
+ if (mii_mode == AR71XX_MII_MODE_RGMII)
+ mii_if = MII1_CTRL_IF_RGMII;
+ else if (mii_mode == AR71XX_MII_MODE_RMII)
+ mii_if = MII1_CTRL_IF_RMII;
+ else {
+ printf("%s: invalid MII mode (%d) for unit %d\n",
+ __func__, mii_mode, unit);
+ return;
+ }
+ break;
+ default:
+ printf("%s: invalid MII unit set for arge unit: %d\n",
+ __func__, unit);
+ return;
+ }
+
+ val = ATH_READ_REG(reg);
+ val &= ~(MII_CTRL_IF_MASK << MII_CTRL_IF_SHIFT);
+ val |= (mii_if & MII_CTRL_IF_MASK) << MII_CTRL_IF_SHIFT;
+ ATH_WRITE_REG(reg, val);
+}
+
+/* Speed is either 10, 100 or 1000 */
+static void
+ar71xx_chip_set_pll_ge(int unit, int speed, uint32_t pll)
+{
+
+ switch (unit) {
+ case 0:
+ ar71xx_write_pll(AR71XX_PLL_SEC_CONFIG,
+ AR71XX_PLL_ETH_INT0_CLK, pll,
+ AR71XX_PLL_ETH0_SHIFT);
+ break;
+ case 1:
+ ar71xx_write_pll(AR71XX_PLL_SEC_CONFIG,
+ AR71XX_PLL_ETH_INT1_CLK, pll,
+ AR71XX_PLL_ETH1_SHIFT);
+ break;
+ default:
+ printf("%s: invalid PLL set for arge unit: %d\n",
+ __func__, unit);
+ return;
+ }
+}
+
+static void
+ar71xx_chip_ddr_flush_ge(int unit)
+{
+
+ switch (unit) {
+ case 0:
+ ar71xx_ddr_flush(AR71XX_WB_FLUSH_GE0);
+ break;
+ case 1:
+ ar71xx_ddr_flush(AR71XX_WB_FLUSH_GE1);
+ break;
+ default:
+ printf("%s: invalid DDR flush for arge unit: %d\n",
+ __func__, unit);
+ return;
+ }
+}
+
+static void
+ar71xx_chip_ddr_flush_ip2(void)
+{
+ ar71xx_ddr_flush(AR71XX_WB_FLUSH_PCI);
+}
+
+static uint32_t
+ar71xx_chip_get_eth_pll(unsigned int mac, int speed)
+{
+ uint32_t pll;
+
+ switch (speed) {
+ case 10:
+ pll = PLL_ETH_INT_CLK_10;
+ break;
+ case 100:
+ pll = PLL_ETH_INT_CLK_100;
+ break;
+ case 1000:
+ pll = PLL_ETH_INT_CLK_1000;
+ break;
+ default:
+ printf("%s%d: invalid speed %d\n", __func__, mac, speed);
+ pll = 0;
+ }
+
+ return (pll);
+}
+
+static void
+ar71xx_chip_init_usb_peripheral(void)
+{
+
+ ar71xx_device_stop(RST_RESET_USB_OHCI_DLL |
+ RST_RESET_USB_HOST | RST_RESET_USB_PHY);
+ DELAY(1000);
+
+ ar71xx_device_start(RST_RESET_USB_OHCI_DLL |
+ RST_RESET_USB_HOST | RST_RESET_USB_PHY);
+ DELAY(1000);
+
+ ATH_WRITE_REG(AR71XX_USB_CTRL_CONFIG,
+ USB_CTRL_CONFIG_OHCI_DES_SWAP |
+ USB_CTRL_CONFIG_OHCI_BUF_SWAP |
+ USB_CTRL_CONFIG_EHCI_DES_SWAP |
+ USB_CTRL_CONFIG_EHCI_BUF_SWAP);
+
+ ATH_WRITE_REG(AR71XX_USB_CTRL_FLADJ,
+ (32 << USB_CTRL_FLADJ_HOST_SHIFT) |
+ (3 << USB_CTRL_FLADJ_A5_SHIFT));
+
+ DELAY(1000);
+}
+
+struct ar71xx_cpu_def ar71xx_chip_def = {
+ &ar71xx_chip_detect_mem_size,
+ &ar71xx_chip_detect_sys_frequency,
+ &ar71xx_chip_device_stop,
+ &ar71xx_chip_device_start,
+ &ar71xx_chip_device_stopped,
+ &ar71xx_chip_set_pll_ge,
+ &ar71xx_chip_set_mii_speed,
+ &ar71xx_chip_set_mii_if,
+ &ar71xx_chip_ddr_flush_ge,
+ &ar71xx_chip_get_eth_pll,
+ &ar71xx_chip_ddr_flush_ip2,
+ &ar71xx_chip_init_usb_peripheral,
+};
Property changes on: trunk/sys/mips/atheros/ar71xx_chip.c
___________________________________________________________________
Added: svn:eol-style
## -0,0 +1 ##
+native
\ No newline at end of property
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## -0,0 +1 ##
+MidnightBSD=%H
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+text/plain
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Added: trunk/sys/mips/atheros/ar71xx_chip.h
===================================================================
--- trunk/sys/mips/atheros/ar71xx_chip.h (rev 0)
+++ trunk/sys/mips/atheros/ar71xx_chip.h 2018-05-26 21:55:02 UTC (rev 9987)
@@ -0,0 +1,37 @@
+/* $MidnightBSD$ */
+/*-
+ * Copyright (c) 2010 Adrian Chadd
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ */
+
+/* $FreeBSD: stable/10/sys/mips/atheros/ar71xx_chip.h 234906 2012-05-02 01:21:57Z adrian $ */
+
+#ifndef __AR71XX_CHIP_H__
+#define __AR71XX_CHIP_H__
+
+extern struct ar71xx_cpu_def ar71xx_chip_def;
+extern void ar71xx_chip_set_mii_speed(uint32_t unit, uint32_t speed);
+extern void ar71xx_chip_set_mii_if(uint32_t unit, uint32_t mii_if);
+
+#endif
Property changes on: trunk/sys/mips/atheros/ar71xx_chip.h
___________________________________________________________________
Added: svn:eol-style
## -0,0 +1 ##
+native
\ No newline at end of property
Added: svn:keywords
## -0,0 +1 ##
+MidnightBSD=%H
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## -0,0 +1 ##
+text/plain
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Added: trunk/sys/mips/atheros/ar71xx_cpudef.h
===================================================================
--- trunk/sys/mips/atheros/ar71xx_cpudef.h (rev 0)
+++ trunk/sys/mips/atheros/ar71xx_cpudef.h 2018-05-26 21:55:02 UTC (rev 9987)
@@ -0,0 +1,135 @@
+/* $MidnightBSD$ */
+/*-
+ * Copyright (c) 2010 Adrian Chadd
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ */
+
+/* $FreeBSD: stable/10/sys/mips/atheros/ar71xx_cpudef.h 253507 2013-07-21 03:51:24Z adrian $ */
+
+#ifndef __AR71XX_CPUDEF_H__
+#define __AR71XX_CPUDEF_H__
+
+struct ar71xx_cpu_def {
+ void (* detect_mem_size) (void);
+ void (* detect_sys_frequency) (void);
+ void (* ar71xx_chip_device_stop) (uint32_t);
+ void (* ar71xx_chip_device_start) (uint32_t);
+ int (* ar71xx_chip_device_stopped) (uint32_t);
+ void (* ar71xx_chip_set_pll_ge) (int, int, uint32_t);
+ void (* ar71xx_chip_set_mii_speed) (uint32_t, uint32_t);
+ void (* ar71xx_chip_set_mii_if) (uint32_t, ar71xx_mii_mode);
+ void (* ar71xx_chip_ddr_flush_ge) (int);
+ uint32_t (* ar71xx_chip_get_eth_pll) (unsigned int, int);
+
+ /*
+ * From Linux - Handling this IRQ is a bit special.
+ * AR71xx - AR71XX_DDR_REG_FLUSH_PCI
+ * AR724x - AR724X_DDR_REG_FLUSH_PCIE
+ * AR91xx - AR91XX_DDR_REG_FLUSH_WMAC
+ *
+ * These are set when STATUSF_IP2 is set in regiser c0.
+ * This flush is done before the IRQ is handled to make
+ * sure the driver correctly sees any memory updates.
+ */
+ void (* ar71xx_chip_ddr_flush_ip2) (void);
+ /*
+ * The USB peripheral init code is subtly different for
+ * each chip.
+ */
+ void (* ar71xx_chip_init_usb_peripheral) (void);
+};
+
+extern struct ar71xx_cpu_def * ar71xx_cpu_ops;
+
+static inline void ar71xx_detect_sys_frequency(void)
+{
+ ar71xx_cpu_ops->detect_sys_frequency();
+}
+
+static inline void ar71xx_device_stop(uint32_t mask)
+{
+ ar71xx_cpu_ops->ar71xx_chip_device_stop(mask);
+}
+
+static inline void ar71xx_device_start(uint32_t mask)
+{
+ ar71xx_cpu_ops->ar71xx_chip_device_start(mask);
+}
+
+static inline int ar71xx_device_stopped(uint32_t mask)
+{
+ return ar71xx_cpu_ops->ar71xx_chip_device_stopped(mask);
+}
+
+static inline void ar71xx_device_set_pll_ge(int unit, int speed, uint32_t pll)
+{
+ ar71xx_cpu_ops->ar71xx_chip_set_pll_ge(unit, speed, pll);
+}
+
+static inline void ar71xx_device_set_mii_speed(int unit, int speed)
+{
+ ar71xx_cpu_ops->ar71xx_chip_set_mii_speed(unit, speed);
+}
+
+static inline void ar71xx_device_set_mii_if(int unit, ar71xx_mii_mode mii_cfg)
+{
+ ar71xx_cpu_ops->ar71xx_chip_set_mii_if(unit, mii_cfg);
+}
+
+static inline void ar71xx_device_flush_ddr_ge(int unit)
+{
+ ar71xx_cpu_ops->ar71xx_chip_ddr_flush_ge(unit);
+}
+
+static inline uint32_t ar71xx_device_get_eth_pll(unsigned int unit, int speed)
+{
+ return (ar71xx_cpu_ops->ar71xx_chip_get_eth_pll(unit, speed));
+}
+
+static inline void ar71xx_init_usb_peripheral(void)
+{
+ ar71xx_cpu_ops->ar71xx_chip_init_usb_peripheral();
+}
+
+static inline void ar71xx_device_ddr_flush_ip2(void)
+{
+ ar71xx_cpu_ops->ar71xx_chip_ddr_flush_ip2();
+}
+
+/* XXX shouldn't be here! */
+extern uint32_t u_ar71xx_refclk;
+extern uint32_t u_ar71xx_cpu_freq;
+extern uint32_t u_ar71xx_ahb_freq;
+extern uint32_t u_ar71xx_ddr_freq;
+extern uint32_t u_ar71xx_uart_freq;
+extern uint32_t u_ar71xx_wdt_freq;
+
+static inline uint64_t ar71xx_refclk(void) { return u_ar71xx_refclk; }
+static inline uint64_t ar71xx_cpu_freq(void) { return u_ar71xx_cpu_freq; }
+static inline uint64_t ar71xx_ahb_freq(void) { return u_ar71xx_ahb_freq; }
+static inline uint64_t ar71xx_ddr_freq(void) { return u_ar71xx_ddr_freq; }
+static inline uint64_t ar71xx_uart_freq(void) { return u_ar71xx_uart_freq; }
+static inline uint64_t ar71xx_wdt_freq(void) { return u_ar71xx_wdt_freq; }
+
+#endif
Property changes on: trunk/sys/mips/atheros/ar71xx_cpudef.h
___________________________________________________________________
Added: svn:eol-style
## -0,0 +1 ##
+native
\ No newline at end of property
Added: svn:keywords
## -0,0 +1 ##
+MidnightBSD=%H
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+text/plain
\ No newline at end of property
Added: trunk/sys/mips/atheros/ar71xx_ehci.c
===================================================================
--- trunk/sys/mips/atheros/ar71xx_ehci.c (rev 0)
+++ trunk/sys/mips/atheros/ar71xx_ehci.c 2018-05-26 21:55:02 UTC (rev 9987)
@@ -0,0 +1,255 @@
+/* $MidnightBSD$ */
+/*-
+ * Copyright (c) 2008 Sam Leffler. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+ * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+ * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/*
+ * AR71XX attachment driver for the USB Enhanced Host Controller.
+ */
+
+#include <sys/cdefs.h>
+__FBSDID("$FreeBSD: stable/10/sys/mips/atheros/ar71xx_ehci.c 308402 2016-11-07 09:19:04Z hselasky $");
+
+#include "opt_bus.h"
+
+#include <sys/param.h>
+#include <sys/systm.h>
+#include <sys/bus.h>
+#include <sys/rman.h>
+#include <sys/condvar.h>
+#include <sys/kernel.h>
+#include <sys/module.h>
+
+#include <machine/bus.h>
+
+#include <dev/usb/usb.h>
+#include <dev/usb/usbdi.h>
+
+#include <dev/usb/usb_core.h>
+#include <dev/usb/usb_busdma.h>
+#include <dev/usb/usb_process.h>
+#include <dev/usb/usb_util.h>
+
+#include <dev/usb/usb_controller.h>
+#include <dev/usb/usb_bus.h>
+#include <dev/usb/controller/ehci.h>
+#include <dev/usb/controller/ehcireg.h>
+
+#include <mips/atheros/ar71xx_setup.h>
+#include <mips/atheros/ar71xx_bus_space_reversed.h>
+
+#define EHCI_HC_DEVSTR "AR71XX Integrated USB 2.0 controller"
+
+struct ar71xx_ehci_softc {
+ ehci_softc_t base; /* storage for EHCI code */
+};
+
+static device_attach_t ar71xx_ehci_attach;
+static device_detach_t ar71xx_ehci_detach;
+
+bs_r_1_proto(reversed);
+bs_w_1_proto(reversed);
+
+static int
+ar71xx_ehci_probe(device_t self)
+{
+
+ device_set_desc(self, EHCI_HC_DEVSTR);
+
+ return (BUS_PROBE_NOWILDCARD);
+}
+
+static int
+ar71xx_ehci_attach(device_t self)
+{
+ struct ar71xx_ehci_softc *isc = device_get_softc(self);
+ ehci_softc_t *sc = &isc->base;
+ int err;
+ int rid;
+
+ /* initialise some bus fields */
+ sc->sc_bus.parent = self;
+ sc->sc_bus.devices = sc->sc_devices;
+ sc->sc_bus.devices_max = EHCI_MAX_DEVICES;
+ sc->sc_bus.dma_bits = 32;
+
+ /* get all DMA memory */
+ if (usb_bus_mem_alloc_all(&sc->sc_bus,
+ USB_GET_DMA_TAG(self), &ehci_iterate_hw_softc)) {
+ return (ENOMEM);
+ }
+
+ sc->sc_bus.usbrev = USB_REV_2_0;
+
+ /* NB: hints fix the memory location and irq */
+
+ rid = 0;
+ sc->sc_io_res = bus_alloc_resource_any(self, SYS_RES_MEMORY, &rid, RF_ACTIVE);
+ if (!sc->sc_io_res) {
+ device_printf(self, "Could not map memory\n");
+ goto error;
+ }
+
+ /*
+ * Craft special resource for bus space ops that handle
+ * byte-alignment of non-word addresses.
+ */
+ sc->sc_io_tag = ar71xx_bus_space_reversed;
+ sc->sc_io_hdl = rman_get_bushandle(sc->sc_io_res);
+ sc->sc_io_size = rman_get_size(sc->sc_io_res);
+
+ rid = 0;
+ sc->sc_irq_res = bus_alloc_resource_any(self, SYS_RES_IRQ, &rid,
+ RF_ACTIVE);
+ if (sc->sc_irq_res == NULL) {
+ device_printf(self, "Could not allocate irq\n");
+ goto error;
+ }
+ sc->sc_bus.bdev = device_add_child(self, "usbus", -1);
+ if (!sc->sc_bus.bdev) {
+ device_printf(self, "Could not add USB device\n");
+ goto error;
+ }
+ device_set_ivars(sc->sc_bus.bdev, &sc->sc_bus);
+ device_set_desc(sc->sc_bus.bdev, EHCI_HC_DEVSTR);
+
+ sprintf(sc->sc_vendor, "Atheros");
+
+
+ err = bus_setup_intr(self, sc->sc_irq_res, INTR_TYPE_BIO | INTR_MPSAFE,
+ NULL, (driver_intr_t *)ehci_interrupt, sc, &sc->sc_intr_hdl);
+ if (err) {
+ device_printf(self, "Could not setup irq, %d\n", err);
+ sc->sc_intr_hdl = NULL;
+ goto error;
+ }
+
+ /*
+ * Arrange to force Host mode, select big-endian byte alignment,
+ * and arrange to not terminate reset operations (the adapter
+ * will ignore it if we do but might as well save a reg write).
+ * Also, the controller has an embedded Transaction Translator
+ * which means port speed must be read from the Port Status
+ * register following a port enable.
+ */
+ sc->sc_flags = EHCI_SCFLG_SETMODE;
+
+ switch (ar71xx_soc) {
+ case AR71XX_SOC_AR7241:
+ case AR71XX_SOC_AR7242:
+ case AR71XX_SOC_AR9130:
+ case AR71XX_SOC_AR9132:
+ case AR71XX_SOC_AR9330:
+ case AR71XX_SOC_AR9331:
+ sc->sc_flags |= EHCI_SCFLG_TT | EHCI_SCFLG_NORESTERM;
+ break;
+ default:
+ /* fallthrough */
+ break;
+ }
+
+ /*
+ * ehci_reset() needs the correct offset to access the host controller
+ * registers. The AR724x/AR913x offsets aren't 0.
+ */
+ sc->sc_offs = EHCI_CAPLENGTH(EREAD4(sc, EHCI_CAPLEN_HCIVERSION));
+
+
+ (void) ehci_reset(sc);
+
+ err = ehci_init(sc);
+ if (!err) {
+ err = device_probe_and_attach(sc->sc_bus.bdev);
+ }
+ if (err) {
+ device_printf(self, "USB init failed err=%d\n", err);
+ goto error;
+ }
+ return (0);
+
+error:
+ ar71xx_ehci_detach(self);
+ return (ENXIO);
+}
+
+static int
+ar71xx_ehci_detach(device_t self)
+{
+ struct ar71xx_ehci_softc *isc = device_get_softc(self);
+ ehci_softc_t *sc = &isc->base;
+ int err;
+
+ /* during module unload there are lots of children leftover */
+ device_delete_children(self);
+
+ if (sc->sc_irq_res && sc->sc_intr_hdl) {
+ /*
+ * only call ehci_detach() after ehci_init()
+ */
+ ehci_detach(sc);
+
+ err = bus_teardown_intr(self, sc->sc_irq_res, sc->sc_intr_hdl);
+
+ if (err)
+ /* XXX or should we panic? */
+ device_printf(self, "Could not tear down irq, %d\n",
+ err);
+ sc->sc_intr_hdl = NULL;
+ }
+
+ if (sc->sc_irq_res) {
+ bus_release_resource(self, SYS_RES_IRQ, 0, sc->sc_irq_res);
+ sc->sc_irq_res = NULL;
+ }
+ if (sc->sc_io_res) {
+ bus_release_resource(self, SYS_RES_MEMORY, 0,
+ sc->sc_io_res);
+ sc->sc_io_res = NULL;
+ }
+ usb_bus_mem_free_all(&sc->sc_bus, &ehci_iterate_hw_softc);
+
+ return (0);
+}
+
+static device_method_t ehci_methods[] = {
+ /* Device interface */
+ DEVMETHOD(device_probe, ar71xx_ehci_probe),
+ DEVMETHOD(device_attach, ar71xx_ehci_attach),
+ DEVMETHOD(device_detach, ar71xx_ehci_detach),
+ DEVMETHOD(device_suspend, bus_generic_suspend),
+ DEVMETHOD(device_resume, bus_generic_resume),
+ DEVMETHOD(device_shutdown, bus_generic_shutdown),
+
+ DEVMETHOD_END
+};
+
+static driver_t ehci_driver = {
+ .name = "ehci",
+ .methods = ehci_methods,
+ .size = sizeof(struct ar71xx_ehci_softc),
+};
+
+static devclass_t ehci_devclass;
+
+DRIVER_MODULE(ehci, nexus, ehci_driver, ehci_devclass, 0, 0);
+MODULE_DEPEND(ehci, usb, 1, 1, 1);
Property changes on: trunk/sys/mips/atheros/ar71xx_ehci.c
___________________________________________________________________
Added: svn:eol-style
## -0,0 +1 ##
+native
\ No newline at end of property
Added: svn:keywords
## -0,0 +1 ##
+MidnightBSD=%H
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+text/plain
\ No newline at end of property
Added: trunk/sys/mips/atheros/ar71xx_fixup.c
===================================================================
--- trunk/sys/mips/atheros/ar71xx_fixup.c (rev 0)
+++ trunk/sys/mips/atheros/ar71xx_fixup.c 2018-05-26 21:55:02 UTC (rev 9987)
@@ -0,0 +1,154 @@
+/* $MidnightBSD$ */
+/*-
+ * Copyright (c) 2009, Oleksandr Tymoshenko <gonzo at FreeBSD.org>
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice unmodified, this list of conditions, and the following
+ * disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ */
+
+#include <sys/cdefs.h>
+__FBSDID("$FreeBSD: stable/10/sys/mips/atheros/ar71xx_fixup.c 234485 2012-04-20 08:26:05Z adrian $");
+
+#include "opt_ar71xx.h"
+
+#include <sys/param.h>
+#include <sys/systm.h>
+
+#include <sys/bus.h>
+#include <sys/interrupt.h>
+#include <sys/malloc.h>
+#include <sys/kernel.h>
+#include <sys/module.h>
+#include <sys/rman.h>
+#include <sys/lock.h>
+#include <sys/mutex.h>
+
+#include <vm/vm.h>
+#include <vm/pmap.h>
+#include <vm/vm_extern.h>
+
+#include <machine/bus.h>
+#include <machine/cpu.h>
+#include <machine/intr_machdep.h>
+#include <machine/pmap.h>
+
+#include <dev/pci/pcivar.h>
+#include <dev/pci/pcireg.h>
+
+#include <dev/pci/pcib_private.h>
+#include "pcib_if.h"
+
+#include <mips/atheros/ar71xxreg.h>
+#include <mips/atheros/ar71xx_pci_bus_space.h>
+
+#include <mips/atheros/ar71xx_cpudef.h>
+
+#include <sys/linker.h>
+#include <sys/firmware.h>
+
+#include <mips/atheros/ar71xx_fixup.h>
+
+/*
+ * Take a copy of the EEPROM contents and squirrel it away in a firmware.
+ * The SPI flash will eventually cease to be memory-mapped, so we need
+ * to take a copy of this before the SPI driver initialises.
+ */
+void
+ar71xx_pci_slot_create_eeprom_firmware(device_t dev, u_int bus, u_int slot,
+ u_int func, long int flash_addr, int size)
+{
+ char buf[64];
+ uint16_t *cal_data = (uint16_t *) MIPS_PHYS_TO_KSEG1(flash_addr);
+ void *eeprom = NULL;
+ const struct firmware *fw = NULL;
+
+ device_printf(dev, "EEPROM firmware: 0x%lx @ %d bytes\n",
+ flash_addr, size);
+
+ eeprom = malloc(size, M_DEVBUF, M_WAITOK | M_ZERO);
+ if (! eeprom) {
+ device_printf(dev,
+ "%s: malloc failed for '%s', aborting EEPROM\n",
+ __func__, buf);
+ return;
+ }
+
+ memcpy(eeprom, cal_data, size);
+
+ /*
+ * Generate a flash EEPROM 'firmware' from the given memory
+ * region. Since the SPI controller will eventually
+ * go into port-IO mode instead of memory-mapped IO
+ * mode, a copy of the EEPROM contents is required.
+ */
+ snprintf(buf, sizeof(buf), "%s.%d.bus.%d.%d.%d.eeprom_firmware",
+ device_get_name(dev), device_get_unit(dev), bus, slot, func);
+ fw = firmware_register(buf, eeprom, size, 1, NULL);
+ if (fw == NULL) {
+ device_printf(dev, "%s: firmware_register (%s) failed\n",
+ __func__, buf);
+ free(eeprom, M_DEVBUF);
+ return;
+ }
+ device_printf(dev, "device EEPROM '%s' registered\n", buf);
+}
+
+#if 0
+static void
+ar71xx_pci_slot_fixup(device_t dev, u_int bus, u_int slot, u_int func)
+{
+ long int flash_addr;
+ char buf[64];
+ int size;
+
+ /*
+ * Check whether the given slot has a hint to poke.
+ */
+ if (bootverbose)
+ device_printf(dev, "%s: checking dev %s, %d/%d/%d\n",
+ __func__, device_get_nameunit(dev), bus, slot, func);
+
+ snprintf(buf, sizeof(buf), "bus.%d.%d.%d.ath_fixup_addr",
+ bus, slot, func);
+
+ if (resource_long_value(device_get_name(dev), device_get_unit(dev),
+ buf, &flash_addr) == 0) {
+ snprintf(buf, sizeof(buf), "bus.%d.%d.%d.ath_fixup_size",
+ bus, slot, func);
+ if (resource_int_value(device_get_name(dev),
+ device_get_unit(dev), buf, &size) != 0) {
+ device_printf(dev,
+ "%s: missing hint '%s', aborting EEPROM\n",
+ __func__, buf);
+ return;
+ }
+
+
+ device_printf(dev, "found EEPROM at 0x%lx on %d.%d.%d\n",
+ flash_addr, bus, slot, func);
+ ar71xx_pci_fixup(dev, bus, slot, func, flash_addr, size);
+ ar71xx_pci_slot_create_eeprom_firmware(dev, bus, slot, func,
+ flash_addr, size);
+ }
+}
+#endif /* 0 */
Property changes on: trunk/sys/mips/atheros/ar71xx_fixup.c
___________________________________________________________________
Added: svn:eol-style
## -0,0 +1 ##
+native
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## -0,0 +1 ##
+MidnightBSD=%H
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Added: svn:mime-type
## -0,0 +1 ##
+text/plain
\ No newline at end of property
Added: trunk/sys/mips/atheros/ar71xx_fixup.h
===================================================================
--- trunk/sys/mips/atheros/ar71xx_fixup.h (rev 0)
+++ trunk/sys/mips/atheros/ar71xx_fixup.h 2018-05-26 21:55:02 UTC (rev 9987)
@@ -0,0 +1,37 @@
+/* $MidnightBSD$ */
+/*-
+ * Copyright (c) 2012, Adrian Chadd <adrian at FreeBSD.org>
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice unmodified, this list of conditions, and the following
+ * disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ * $FreeBSD: stable/10/sys/mips/atheros/ar71xx_fixup.h 234485 2012-04-20 08:26:05Z adrian $
+ */
+
+#ifndef __ATHEROS_AR71XX_FIXUP_H__
+#define __ATHEROS_AR71XX_FIXUP_H__
+
+extern void ar71xx_pci_slot_create_eeprom_firmware(device_t dev,
+ u_int bus, u_int slot, u_int func, long int flash_addr, int size);
+
+#endif /* __ATHEROS_AR71XX_FIXUP_H__ */
Property changes on: trunk/sys/mips/atheros/ar71xx_fixup.h
___________________________________________________________________
Added: svn:eol-style
## -0,0 +1 ##
+native
\ No newline at end of property
Added: svn:keywords
## -0,0 +1 ##
+MidnightBSD=%H
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+text/plain
\ No newline at end of property
Added: trunk/sys/mips/atheros/ar71xx_gpio.c
===================================================================
--- trunk/sys/mips/atheros/ar71xx_gpio.c (rev 0)
+++ trunk/sys/mips/atheros/ar71xx_gpio.c 2018-05-26 21:55:02 UTC (rev 9987)
@@ -0,0 +1,489 @@
+/* $MidnightBSD$ */
+/*-
+ * Copyright (c) 2009, Oleksandr Tymoshenko <gonzo at FreeBSD.org>
+ * Copyright (c) 2009, Luiz Otavio O Souza.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice unmodified, this list of conditions, and the following
+ * disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ */
+
+/*
+ * GPIO driver for AR71xx
+ */
+
+#include <sys/cdefs.h>
+__FBSDID("$FreeBSD: stable/10/sys/mips/atheros/ar71xx_gpio.c 278786 2015-02-14 21:16:19Z loos $");
+
+#include <sys/param.h>
+#include <sys/systm.h>
+#include <sys/bus.h>
+
+#include <sys/kernel.h>
+#include <sys/module.h>
+#include <sys/rman.h>
+#include <sys/lock.h>
+#include <sys/malloc.h>
+#include <sys/mutex.h>
+#include <sys/gpio.h>
+
+#include <machine/bus.h>
+#include <machine/resource.h>
+#include <mips/atheros/ar71xxreg.h>
+#include <mips/atheros/ar71xx_setup.h>
+#include <mips/atheros/ar71xx_gpiovar.h>
+#include <mips/atheros/ar933xreg.h>
+#include <mips/atheros/ar934xreg.h>
+
+#include "gpio_if.h"
+
+#define DEFAULT_CAPS (GPIO_PIN_INPUT | GPIO_PIN_OUTPUT)
+
+/*
+ * Helpers
+ */
+static void ar71xx_gpio_function_enable(struct ar71xx_gpio_softc *sc,
+ uint32_t mask);
+static void ar71xx_gpio_function_disable(struct ar71xx_gpio_softc *sc,
+ uint32_t mask);
+static void ar71xx_gpio_pin_configure(struct ar71xx_gpio_softc *sc,
+ struct gpio_pin *pin, uint32_t flags);
+
+/*
+ * Driver stuff
+ */
+static int ar71xx_gpio_probe(device_t dev);
+static int ar71xx_gpio_attach(device_t dev);
+static int ar71xx_gpio_detach(device_t dev);
+static int ar71xx_gpio_filter(void *arg);
+static void ar71xx_gpio_intr(void *arg);
+
+/*
+ * GPIO interface
+ */
+static int ar71xx_gpio_pin_max(device_t dev, int *maxpin);
+static int ar71xx_gpio_pin_getcaps(device_t dev, uint32_t pin, uint32_t *caps);
+static int ar71xx_gpio_pin_getflags(device_t dev, uint32_t pin, uint32_t
+ *flags);
+static int ar71xx_gpio_pin_getname(device_t dev, uint32_t pin, char *name);
+static int ar71xx_gpio_pin_setflags(device_t dev, uint32_t pin, uint32_t flags);
+static int ar71xx_gpio_pin_set(device_t dev, uint32_t pin, unsigned int value);
+static int ar71xx_gpio_pin_get(device_t dev, uint32_t pin, unsigned int *val);
+static int ar71xx_gpio_pin_toggle(device_t dev, uint32_t pin);
+
+static void
+ar71xx_gpio_function_enable(struct ar71xx_gpio_softc *sc, uint32_t mask)
+{
+ if (ar71xx_soc == AR71XX_SOC_AR9341 ||
+ ar71xx_soc == AR71XX_SOC_AR9342 ||
+ ar71xx_soc == AR71XX_SOC_AR9344)
+ GPIO_SET_BITS(sc, AR934X_GPIO_REG_FUNC, mask);
+ else
+ GPIO_SET_BITS(sc, AR71XX_GPIO_FUNCTION, mask);
+}
+
+static void
+ar71xx_gpio_function_disable(struct ar71xx_gpio_softc *sc, uint32_t mask)
+{
+ if (ar71xx_soc == AR71XX_SOC_AR9341 ||
+ ar71xx_soc == AR71XX_SOC_AR9342 ||
+ ar71xx_soc == AR71XX_SOC_AR9344)
+ GPIO_CLEAR_BITS(sc, AR934X_GPIO_REG_FUNC, mask);
+ else
+ GPIO_CLEAR_BITS(sc, AR71XX_GPIO_FUNCTION, mask);
+}
+
+static void
+ar71xx_gpio_pin_configure(struct ar71xx_gpio_softc *sc, struct gpio_pin *pin,
+ unsigned int flags)
+{
+ uint32_t mask;
+
+ mask = 1 << pin->gp_pin;
+
+ /*
+ * Manage input/output
+ */
+ if (flags & (GPIO_PIN_INPUT|GPIO_PIN_OUTPUT)) {
+ pin->gp_flags &= ~(GPIO_PIN_INPUT|GPIO_PIN_OUTPUT);
+ if (flags & GPIO_PIN_OUTPUT) {
+ pin->gp_flags |= GPIO_PIN_OUTPUT;
+ GPIO_SET_BITS(sc, AR71XX_GPIO_OE, mask);
+ }
+ else {
+ pin->gp_flags |= GPIO_PIN_INPUT;
+ GPIO_CLEAR_BITS(sc, AR71XX_GPIO_OE, mask);
+ }
+ }
+}
+
+static int
+ar71xx_gpio_pin_max(device_t dev, int *maxpin)
+{
+
+ switch (ar71xx_soc) {
+ case AR71XX_SOC_AR9130:
+ case AR71XX_SOC_AR9132:
+ *maxpin = AR91XX_GPIO_PINS - 1;
+ break;
+ case AR71XX_SOC_AR7240:
+ case AR71XX_SOC_AR7241:
+ case AR71XX_SOC_AR7242:
+ *maxpin = AR724X_GPIO_PINS - 1;
+ break;
+ case AR71XX_SOC_AR9330:
+ case AR71XX_SOC_AR9331:
+ *maxpin = AR933X_GPIO_COUNT - 1;
+ break;
+ case AR71XX_SOC_AR9341:
+ case AR71XX_SOC_AR9342:
+ case AR71XX_SOC_AR9344:
+ *maxpin = AR934X_GPIO_COUNT - 1;
+ break;
+ default:
+ *maxpin = AR71XX_GPIO_PINS - 1;
+ }
+ return (0);
+}
+
+static int
+ar71xx_gpio_pin_getcaps(device_t dev, uint32_t pin, uint32_t *caps)
+{
+ struct ar71xx_gpio_softc *sc = device_get_softc(dev);
+ int i;
+
+ for (i = 0; i < sc->gpio_npins; i++) {
+ if (sc->gpio_pins[i].gp_pin == pin)
+ break;
+ }
+
+ if (i >= sc->gpio_npins)
+ return (EINVAL);
+
+ GPIO_LOCK(sc);
+ *caps = sc->gpio_pins[i].gp_caps;
+ GPIO_UNLOCK(sc);
+
+ return (0);
+}
+
+static int
+ar71xx_gpio_pin_getflags(device_t dev, uint32_t pin, uint32_t *flags)
+{
+ struct ar71xx_gpio_softc *sc = device_get_softc(dev);
+ int i;
+
+ for (i = 0; i < sc->gpio_npins; i++) {
+ if (sc->gpio_pins[i].gp_pin == pin)
+ break;
+ }
+
+ if (i >= sc->gpio_npins)
+ return (EINVAL);
+
+ GPIO_LOCK(sc);
+ *flags = sc->gpio_pins[i].gp_flags;
+ GPIO_UNLOCK(sc);
+
+ return (0);
+}
+
+static int
+ar71xx_gpio_pin_getname(device_t dev, uint32_t pin, char *name)
+{
+ struct ar71xx_gpio_softc *sc = device_get_softc(dev);
+ int i;
+
+ for (i = 0; i < sc->gpio_npins; i++) {
+ if (sc->gpio_pins[i].gp_pin == pin)
+ break;
+ }
+
+ if (i >= sc->gpio_npins)
+ return (EINVAL);
+
+ GPIO_LOCK(sc);
+ memcpy(name, sc->gpio_pins[i].gp_name, GPIOMAXNAME);
+ GPIO_UNLOCK(sc);
+
+ return (0);
+}
+
+static int
+ar71xx_gpio_pin_setflags(device_t dev, uint32_t pin, uint32_t flags)
+{
+ int i;
+ struct ar71xx_gpio_softc *sc = device_get_softc(dev);
+
+ for (i = 0; i < sc->gpio_npins; i++) {
+ if (sc->gpio_pins[i].gp_pin == pin)
+ break;
+ }
+
+ if (i >= sc->gpio_npins)
+ return (EINVAL);
+
+ ar71xx_gpio_pin_configure(sc, &sc->gpio_pins[i], flags);
+
+ return (0);
+}
+
+static int
+ar71xx_gpio_pin_set(device_t dev, uint32_t pin, unsigned int value)
+{
+ struct ar71xx_gpio_softc *sc = device_get_softc(dev);
+ int i;
+
+ for (i = 0; i < sc->gpio_npins; i++) {
+ if (sc->gpio_pins[i].gp_pin == pin)
+ break;
+ }
+
+ if (i >= sc->gpio_npins)
+ return (EINVAL);
+
+ if (value)
+ GPIO_WRITE(sc, AR71XX_GPIO_SET, (1 << pin));
+ else
+ GPIO_WRITE(sc, AR71XX_GPIO_CLEAR, (1 << pin));
+
+ return (0);
+}
+
+static int
+ar71xx_gpio_pin_get(device_t dev, uint32_t pin, unsigned int *val)
+{
+ struct ar71xx_gpio_softc *sc = device_get_softc(dev);
+ int i;
+
+ for (i = 0; i < sc->gpio_npins; i++) {
+ if (sc->gpio_pins[i].gp_pin == pin)
+ break;
+ }
+
+ if (i >= sc->gpio_npins)
+ return (EINVAL);
+
+ *val = (GPIO_READ(sc, AR71XX_GPIO_IN) & (1 << pin)) ? 1 : 0;
+
+ return (0);
+}
+
+static int
+ar71xx_gpio_pin_toggle(device_t dev, uint32_t pin)
+{
+ int res, i;
+ struct ar71xx_gpio_softc *sc = device_get_softc(dev);
+
+ for (i = 0; i < sc->gpio_npins; i++) {
+ if (sc->gpio_pins[i].gp_pin == pin)
+ break;
+ }
+
+ if (i >= sc->gpio_npins)
+ return (EINVAL);
+
+ res = (GPIO_READ(sc, AR71XX_GPIO_IN) & (1 << pin)) ? 1 : 0;
+ if (res)
+ GPIO_WRITE(sc, AR71XX_GPIO_CLEAR, (1 << pin));
+ else
+ GPIO_WRITE(sc, AR71XX_GPIO_SET, (1 << pin));
+
+ return (0);
+}
+
+static int
+ar71xx_gpio_filter(void *arg)
+{
+
+ /* TODO: something useful */
+ return (FILTER_STRAY);
+}
+
+
+
+static void
+ar71xx_gpio_intr(void *arg)
+{
+ struct ar71xx_gpio_softc *sc = arg;
+ GPIO_LOCK(sc);
+ /* TODO: something useful */
+ GPIO_UNLOCK(sc);
+}
+
+static int
+ar71xx_gpio_probe(device_t dev)
+{
+
+ device_set_desc(dev, "Atheros AR71XX GPIO driver");
+ return (0);
+}
+
+static int
+ar71xx_gpio_attach(device_t dev)
+{
+ struct ar71xx_gpio_softc *sc = device_get_softc(dev);
+ int error = 0;
+ int i, j, maxpin;
+ int mask, pinon;
+ int old = 0;
+
+ KASSERT((device_get_unit(dev) == 0),
+ ("ar71xx_gpio: Only one gpio module supported"));
+
+ mtx_init(&sc->gpio_mtx, device_get_nameunit(dev), NULL, MTX_DEF);
+
+ /* Map control/status registers. */
+ sc->gpio_mem_rid = 0;
+ sc->gpio_mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY,
+ &sc->gpio_mem_rid, RF_ACTIVE);
+
+ if (sc->gpio_mem_res == NULL) {
+ device_printf(dev, "couldn't map memory\n");
+ error = ENXIO;
+ ar71xx_gpio_detach(dev);
+ return(error);
+ }
+
+ if ((sc->gpio_irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ,
+ &sc->gpio_irq_rid, RF_SHAREABLE | RF_ACTIVE)) == NULL) {
+ device_printf(dev, "unable to allocate IRQ resource\n");
+ return (ENXIO);
+ }
+
+ if ((bus_setup_intr(dev, sc->gpio_irq_res, INTR_TYPE_MISC,
+ ar71xx_gpio_filter, ar71xx_gpio_intr, sc, &sc->gpio_ih))) {
+ device_printf(dev,
+ "WARNING: unable to register interrupt handler\n");
+ return (ENXIO);
+ }
+
+ sc->dev = dev;
+
+ /* Enable function bits that are required */
+ if (resource_int_value(device_get_name(dev), device_get_unit(dev),
+ "function_set", &mask) == 0) {
+ device_printf(dev, "function_set: 0x%x\n", mask);
+ ar71xx_gpio_function_enable(sc, mask);
+ old = 1;
+ }
+ /* Disable function bits that are required */
+ if (resource_int_value(device_get_name(dev), device_get_unit(dev),
+ "function_clear", &mask) == 0) {
+ device_printf(dev, "function_clear: 0x%x\n", mask);
+ ar71xx_gpio_function_disable(sc, mask);
+ old = 1;
+ }
+ /* Handle previous behaviour */
+ if (old == 0) {
+ ar71xx_gpio_function_enable(sc, GPIO_FUNC_SPI_CS1_EN);
+ ar71xx_gpio_function_enable(sc, GPIO_FUNC_SPI_CS2_EN);
+ }
+
+ /* Configure all pins as input */
+ /* disable interrupts for all pins */
+ GPIO_WRITE(sc, AR71XX_GPIO_INT_MASK, 0);
+
+ /* Initialise all pins specified in the mask, up to the pin count */
+ (void) ar71xx_gpio_pin_max(dev, &maxpin);
+ if (resource_int_value(device_get_name(dev), device_get_unit(dev),
+ "pinmask", &mask) != 0)
+ mask = 0;
+ if (resource_int_value(device_get_name(dev), device_get_unit(dev),
+ "pinon", &pinon) != 0)
+ pinon = 0;
+ device_printf(dev, "gpio pinmask=0x%x\n", mask);
+ for (j = 0; j <= maxpin; j++) {
+ if ((mask & (1 << j)) == 0)
+ continue;
+ sc->gpio_npins++;
+ }
+ sc->gpio_pins = malloc(sizeof(*sc->gpio_pins) * sc->gpio_npins,
+ M_DEVBUF, M_WAITOK | M_ZERO);
+ for (i = 0, j = 0; j <= maxpin; j++) {
+ if ((mask & (1 << j)) == 0)
+ continue;
+ snprintf(sc->gpio_pins[i].gp_name, GPIOMAXNAME,
+ "pin %d", j);
+ sc->gpio_pins[i].gp_pin = j;
+ sc->gpio_pins[i].gp_caps = DEFAULT_CAPS;
+ sc->gpio_pins[i].gp_flags = 0;
+ ar71xx_gpio_pin_configure(sc, &sc->gpio_pins[i], DEFAULT_CAPS);
+ i++;
+ }
+ for (i = 0; i < sc->gpio_npins; i++) {
+ j = sc->gpio_pins[i].gp_pin;
+ if ((pinon & (1 << j)) != 0)
+ ar71xx_gpio_pin_set(dev, j, 1);
+ }
+ device_add_child(dev, "gpioc", -1);
+ device_add_child(dev, "gpiobus", -1);
+
+ return (bus_generic_attach(dev));
+}
+
+static int
+ar71xx_gpio_detach(device_t dev)
+{
+ struct ar71xx_gpio_softc *sc = device_get_softc(dev);
+
+ KASSERT(mtx_initialized(&sc->gpio_mtx), ("gpio mutex not initialized"));
+
+ ar71xx_gpio_function_disable(sc, GPIO_FUNC_SPI_CS1_EN);
+ ar71xx_gpio_function_disable(sc, GPIO_FUNC_SPI_CS2_EN);
+ bus_generic_detach(dev);
+
+ if (sc->gpio_mem_res)
+ bus_release_resource(dev, SYS_RES_MEMORY, sc->gpio_mem_rid,
+ sc->gpio_mem_res);
+
+ free(sc->gpio_pins, M_DEVBUF);
+ mtx_destroy(&sc->gpio_mtx);
+
+ return(0);
+}
+
+static device_method_t ar71xx_gpio_methods[] = {
+ DEVMETHOD(device_probe, ar71xx_gpio_probe),
+ DEVMETHOD(device_attach, ar71xx_gpio_attach),
+ DEVMETHOD(device_detach, ar71xx_gpio_detach),
+
+ /* GPIO protocol */
+ DEVMETHOD(gpio_pin_max, ar71xx_gpio_pin_max),
+ DEVMETHOD(gpio_pin_getname, ar71xx_gpio_pin_getname),
+ DEVMETHOD(gpio_pin_getflags, ar71xx_gpio_pin_getflags),
+ DEVMETHOD(gpio_pin_getcaps, ar71xx_gpio_pin_getcaps),
+ DEVMETHOD(gpio_pin_setflags, ar71xx_gpio_pin_setflags),
+ DEVMETHOD(gpio_pin_get, ar71xx_gpio_pin_get),
+ DEVMETHOD(gpio_pin_set, ar71xx_gpio_pin_set),
+ DEVMETHOD(gpio_pin_toggle, ar71xx_gpio_pin_toggle),
+ {0, 0},
+};
+
+static driver_t ar71xx_gpio_driver = {
+ "gpio",
+ ar71xx_gpio_methods,
+ sizeof(struct ar71xx_gpio_softc),
+};
+static devclass_t ar71xx_gpio_devclass;
+
+DRIVER_MODULE(ar71xx_gpio, apb, ar71xx_gpio_driver, ar71xx_gpio_devclass, 0, 0);
Property changes on: trunk/sys/mips/atheros/ar71xx_gpio.c
___________________________________________________________________
Added: svn:eol-style
## -0,0 +1 ##
+native
\ No newline at end of property
Added: svn:keywords
## -0,0 +1 ##
+MidnightBSD=%H
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+text/plain
\ No newline at end of property
Added: trunk/sys/mips/atheros/ar71xx_gpiovar.h
===================================================================
--- trunk/sys/mips/atheros/ar71xx_gpiovar.h (rev 0)
+++ trunk/sys/mips/atheros/ar71xx_gpiovar.h 2018-05-26 21:55:02 UTC (rev 9987)
@@ -0,0 +1,71 @@
+/* $MidnightBSD$ */
+/*-
+ * Copyright (c) 2009, Oleksandr Tymoshenko <gonzo at FreeBSD.org>
+ * Copyright (c) 2009, Luiz Otavio O Souza.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice unmodified, this list of conditions, and the following
+ * disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ * $FreeBSD: stable/10/sys/mips/atheros/ar71xx_gpiovar.h 255335 2013-09-06 23:47:50Z loos $
+ *
+ */
+
+#ifndef __AR71XX_GPIOVAR_H__
+#define __AR71XX_GPIOVAR_H__
+
+#define GPIO_LOCK(_sc) mtx_lock(&(_sc)->gpio_mtx)
+#define GPIO_UNLOCK(_sc) mtx_unlock(&(_sc)->gpio_mtx)
+#define GPIO_LOCK_ASSERT(_sc) mtx_assert(&(_sc)->gpio_mtx, MA_OWNED)
+
+/*
+ * register space access macros
+ */
+#define GPIO_WRITE(sc, reg, val) do { \
+ bus_write_4(sc->gpio_mem_res, (reg), (val)); \
+ } while (0)
+
+#define GPIO_READ(sc, reg) bus_read_4(sc->gpio_mem_res, (reg))
+
+#define GPIO_SET_BITS(sc, reg, bits) \
+ GPIO_WRITE(sc, reg, GPIO_READ(sc, (reg)) | (bits))
+
+#define GPIO_CLEAR_BITS(sc, reg, bits) \
+ GPIO_WRITE(sc, reg, GPIO_READ(sc, (reg)) & ~(bits))
+
+#define AR71XX_GPIO_PINS 12
+#define AR724X_GPIO_PINS 18
+#define AR91XX_GPIO_PINS 22
+
+struct ar71xx_gpio_softc {
+ device_t dev;
+ struct mtx gpio_mtx;
+ struct resource *gpio_mem_res;
+ int gpio_mem_rid;
+ struct resource *gpio_irq_res;
+ int gpio_irq_rid;
+ void *gpio_ih;
+ int gpio_npins;
+ struct gpio_pin *gpio_pins;
+};
+
+#endif /* __AR71XX_GPIOVAR_H__ */
Property changes on: trunk/sys/mips/atheros/ar71xx_gpiovar.h
___________________________________________________________________
Added: svn:eol-style
## -0,0 +1 ##
+native
\ No newline at end of property
Added: svn:keywords
## -0,0 +1 ##
+MidnightBSD=%H
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+text/plain
\ No newline at end of property
Added: trunk/sys/mips/atheros/ar71xx_machdep.c
===================================================================
--- trunk/sys/mips/atheros/ar71xx_machdep.c (rev 0)
+++ trunk/sys/mips/atheros/ar71xx_machdep.c 2018-05-26 21:55:02 UTC (rev 9987)
@@ -0,0 +1,288 @@
+/* $MidnightBSD$ */
+/*-
+ * Copyright (c) 2009 Oleksandr Tymoshenko
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ */
+
+#include <sys/cdefs.h>
+__FBSDID("$FreeBSD: stable/10/sys/mips/atheros/ar71xx_machdep.c 248865 2013-03-29 06:31:31Z adrian $");
+
+#include "opt_ddb.h"
+#include "opt_ar71xx.h"
+
+#include <sys/param.h>
+#include <sys/conf.h>
+#include <sys/kernel.h>
+#include <sys/systm.h>
+#include <sys/bus.h>
+#include <sys/cons.h>
+#include <sys/kdb.h>
+#include <sys/reboot.h>
+
+#include <vm/vm.h>
+#include <vm/vm_page.h>
+
+#include <net/ethernet.h>
+
+#include <machine/clock.h>
+#include <machine/cpu.h>
+#include <machine/cpuregs.h>
+#include <machine/hwfunc.h>
+#include <machine/md_var.h>
+#include <machine/trap.h>
+#include <machine/vmparam.h>
+
+#include <mips/atheros/ar71xxreg.h>
+
+#include <mips/atheros/ar71xx_setup.h>
+#include <mips/atheros/ar71xx_cpudef.h>
+
+#include <mips/sentry5/s5reg.h>
+
+extern char edata[], end[];
+
+uint32_t ar711_base_mac[ETHER_ADDR_LEN];
+/* 4KB static data aread to keep a copy of the bootload env until
+ the dynamic kenv is setup */
+char boot1_env[4096];
+
+/*
+ * We get a string in from Redboot with the all the arguments together,
+ * "foo=bar bar=baz". Split them up and save in kenv.
+ */
+static void
+parse_argv(char *str)
+{
+ char *n, *v;
+
+ while ((v = strsep(&str, " ")) != NULL) {
+ if (*v == '\0')
+ continue;
+ if (*v == '-') {
+ while (*v != '\0') {
+ v++;
+ switch (*v) {
+ case 'a': boothowto |= RB_ASKNAME; break;
+ case 'd': boothowto |= RB_KDB; break;
+ case 'g': boothowto |= RB_GDB; break;
+ case 's': boothowto |= RB_SINGLE; break;
+ case 'v': boothowto |= RB_VERBOSE; break;
+ }
+ }
+ } else {
+ n = strsep(&v, "=");
+ if (v == NULL)
+ setenv(n, "1");
+ else
+ setenv(n, v);
+ }
+ }
+}
+
+void
+platform_cpu_init()
+{
+ /* Nothing special */
+}
+
+void
+platform_reset(void)
+{
+ ar71xx_device_stop(RST_RESET_FULL_CHIP);
+ /* Wait for reset */
+ while(1)
+ ;
+}
+
+/*
+ * Obtain the MAC address via the Redboot environment.
+ */
+static void
+ar71xx_redboot_get_macaddr(void)
+{
+ char *var;
+ int count = 0;
+
+ /*
+ * "ethaddr" is passed via envp on RedBoot platforms
+ * "kmac" is passed via argv on RouterBOOT platforms
+ */
+ if ((var = getenv("ethaddr")) != NULL ||
+ (var = getenv("kmac")) != NULL) {
+ count = sscanf(var, "%x%*c%x%*c%x%*c%x%*c%x%*c%x",
+ &ar711_base_mac[0], &ar711_base_mac[1],
+ &ar711_base_mac[2], &ar711_base_mac[3],
+ &ar711_base_mac[4], &ar711_base_mac[5]);
+ if (count < 6)
+ memset(ar711_base_mac, 0,
+ sizeof(ar711_base_mac));
+ freeenv(var);
+ }
+}
+
+void
+platform_start(__register_t a0 __unused, __register_t a1 __unused,
+ __register_t a2 __unused, __register_t a3 __unused)
+{
+ uint64_t platform_counter_freq;
+ int argc = 0, i;
+ char **argv = NULL, **envp = NULL;
+ vm_offset_t kernend;
+
+ /*
+ * clear the BSS and SBSS segments, this should be first call in
+ * the function
+ */
+ kernend = (vm_offset_t)&end;
+ memset(&edata, 0, kernend - (vm_offset_t)(&edata));
+
+ mips_postboot_fixup();
+
+ /* Initialize pcpu stuff */
+ mips_pcpu0_init();
+
+ /*
+ * Until some more sensible abstractions for uboot/redboot
+ * environment handling, we have to make this a compile-time
+ * hack. The existing code handles the uboot environment
+ * very incorrectly so we should just ignore initialising
+ * the relevant pointers.
+ */
+#ifndef AR71XX_ENV_UBOOT
+ argc = a0;
+ argv = (char**)a1;
+ envp = (char**)a2;
+#endif
+ /*
+ * Protect ourselves from garbage in registers
+ */
+ if (MIPS_IS_VALID_PTR(envp)) {
+ for (i = 0; envp[i]; i += 2) {
+ if (strcmp(envp[i], "memsize") == 0)
+ realmem = btoc(strtoul(envp[i+1], NULL, 16));
+ }
+ }
+
+ /*
+ * Just wild guess. RedBoot let us down and didn't reported
+ * memory size
+ */
+ if (realmem == 0)
+ realmem = btoc(32*1024*1024);
+
+ /*
+ * Allow build-time override in case Redboot lies
+ * or in other situations (eg where there's u-boot)
+ * where there isn't (yet) a convienent method of
+ * being told how much RAM is available.
+ *
+ * This happens on at least the Ubiquiti LS-SR71A
+ * board, where redboot says there's 16mb of RAM
+ * but in fact there's 32mb.
+ */
+#if defined(AR71XX_REALMEM)
+ realmem = btoc(AR71XX_REALMEM);
+#endif
+
+ /* phys_avail regions are in bytes */
+ phys_avail[0] = MIPS_KSEG0_TO_PHYS(kernel_kseg0_end);
+ phys_avail[1] = ctob(realmem);
+
+ dump_avail[0] = phys_avail[0];
+ dump_avail[1] = phys_avail[1] - phys_avail[0];
+
+ physmem = realmem;
+
+ /*
+ * ns8250 uart code uses DELAY so ticker should be inititalized
+ * before cninit. And tick_init_params refers to hz, so * init_param1
+ * should be called first.
+ */
+ init_param1();
+
+ /* Detect the system type - this is needed for subsequent chipset-specific calls */
+ ar71xx_detect_sys_type();
+ ar71xx_detect_sys_frequency();
+
+ platform_counter_freq = ar71xx_cpu_freq();
+ mips_timer_init_params(platform_counter_freq, 1);
+ cninit();
+ init_static_kenv(boot1_env, sizeof(boot1_env));
+
+ printf("CPU platform: %s\n", ar71xx_get_system_type());
+ printf("CPU Frequency=%d MHz\n", u_ar71xx_cpu_freq / 1000000);
+ printf("CPU DDR Frequency=%d MHz\n", u_ar71xx_ddr_freq / 1000000);
+ printf("CPU AHB Frequency=%d MHz\n", u_ar71xx_ahb_freq / 1000000);
+ printf("platform frequency: %lld\n", platform_counter_freq);
+ printf("CPU reference clock: %d MHz\n", u_ar71xx_refclk / 1000000);
+ printf("arguments: \n");
+ printf(" a0 = %08x\n", a0);
+ printf(" a1 = %08x\n", a1);
+ printf(" a2 = %08x\n", a2);
+ printf(" a3 = %08x\n", a3);
+
+ /*
+ * XXX this code is very redboot specific.
+ */
+ printf("Cmd line:");
+ if (MIPS_IS_VALID_PTR(argv)) {
+ for (i = 0; i < argc; i++) {
+ printf(" %s", argv[i]);
+ parse_argv(argv[i]);
+ }
+ }
+ else
+ printf ("argv is invalid");
+ printf("\n");
+
+ printf("Environment:\n");
+ if (MIPS_IS_VALID_PTR(envp)) {
+ for (i = 0; envp[i]; i+=2) {
+ printf(" %s = %s\n", envp[i], envp[i+1]);
+ setenv(envp[i], envp[i+1]);
+ }
+ }
+ else
+ printf ("envp is invalid\n");
+
+ /* Redboot if_arge MAC address is in the environment */
+ ar71xx_redboot_get_macaddr();
+
+ init_param2(physmem);
+ mips_cpu_init();
+ pmap_bootstrap();
+ mips_proc0_init();
+ mutex_init();
+
+ /*
+ * Reset USB devices
+ */
+ ar71xx_init_usb_peripheral();
+
+ kdb_init();
+#ifdef KDB
+ if (boothowto & RB_KDB)
+ kdb_enter(KDB_WHY_BOOTFLAGS, "Boot flags requested debugger");
+#endif
+}
Property changes on: trunk/sys/mips/atheros/ar71xx_machdep.c
___________________________________________________________________
Added: svn:eol-style
## -0,0 +1 ##
+native
\ No newline at end of property
Added: svn:keywords
## -0,0 +1 ##
+MidnightBSD=%H
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+text/plain
\ No newline at end of property
Added: trunk/sys/mips/atheros/ar71xx_ohci.c
===================================================================
--- trunk/sys/mips/atheros/ar71xx_ohci.c (rev 0)
+++ trunk/sys/mips/atheros/ar71xx_ohci.c 2018-05-26 21:55:02 UTC (rev 9987)
@@ -0,0 +1,208 @@
+/* $MidnightBSD$ */
+/*-
+ * Copyright (c) 2009, Oleksandr Tymoshenko <gonzo at FreeBSD.org>
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice unmodified, this list of conditions, and the following
+ * disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ */
+
+#include <sys/cdefs.h>
+__FBSDID("$FreeBSD: stable/10/sys/mips/atheros/ar71xx_ohci.c 308402 2016-11-07 09:19:04Z hselasky $");
+
+#include <sys/param.h>
+#include <sys/systm.h>
+#include <sys/bus.h>
+#include <sys/rman.h>
+#include <sys/condvar.h>
+#include <sys/kernel.h>
+#include <sys/module.h>
+
+#include <dev/usb/usb.h>
+#include <dev/usb/usbdi.h>
+
+#include <dev/usb/usb_core.h>
+#include <dev/usb/usb_busdma.h>
+#include <dev/usb/usb_process.h>
+#include <dev/usb/usb_util.h>
+
+#include <dev/usb/usb_controller.h>
+#include <dev/usb/usb_bus.h>
+#include <dev/usb/controller/ohci.h>
+#include <dev/usb/controller/ohcireg.h>
+
+static int ar71xx_ohci_attach(device_t dev);
+static int ar71xx_ohci_detach(device_t dev);
+static int ar71xx_ohci_probe(device_t dev);
+
+struct ar71xx_ohci_softc
+{
+ struct ohci_softc sc_ohci;
+};
+
+static int
+ar71xx_ohci_probe(device_t dev)
+{
+ device_set_desc(dev, "AR71XX integrated OHCI controller");
+ return (BUS_PROBE_DEFAULT);
+}
+
+static int
+ar71xx_ohci_attach(device_t dev)
+{
+ struct ar71xx_ohci_softc *sc = device_get_softc(dev);
+ int err;
+ int rid;
+
+ /* initialise some bus fields */
+ sc->sc_ohci.sc_bus.parent = dev;
+ sc->sc_ohci.sc_bus.devices = sc->sc_ohci.sc_devices;
+ sc->sc_ohci.sc_bus.devices_max = OHCI_MAX_DEVICES;
+ sc->sc_ohci.sc_bus.dma_bits = 32;
+
+ /* get all DMA memory */
+ if (usb_bus_mem_alloc_all(&sc->sc_ohci.sc_bus,
+ USB_GET_DMA_TAG(dev), &ohci_iterate_hw_softc)) {
+ return (ENOMEM);
+ }
+
+ sc->sc_ohci.sc_dev = dev;
+
+ rid = 0;
+ sc->sc_ohci.sc_io_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid,
+ RF_ACTIVE);
+ if (sc->sc_ohci.sc_io_res == NULL) {
+ err = ENOMEM;
+ goto error;
+ }
+ sc->sc_ohci.sc_io_tag = rman_get_bustag(sc->sc_ohci.sc_io_res);
+ sc->sc_ohci.sc_io_hdl = rman_get_bushandle(sc->sc_ohci.sc_io_res);
+ sc->sc_ohci.sc_io_size = rman_get_size(sc->sc_ohci.sc_io_res);
+
+ rid = 0;
+ sc->sc_ohci.sc_irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
+ RF_ACTIVE);
+ if (sc->sc_ohci.sc_irq_res == NULL) {
+ err = ENOMEM;
+ goto error;
+ }
+ sc->sc_ohci.sc_bus.bdev = device_add_child(dev, "usbus", -1);
+ if (sc->sc_ohci.sc_bus.bdev == NULL) {
+ err = ENOMEM;
+ goto error;
+ }
+ device_set_ivars(sc->sc_ohci.sc_bus.bdev, &sc->sc_ohci.sc_bus);
+
+ err = bus_setup_intr(dev, sc->sc_ohci.sc_irq_res,
+ INTR_TYPE_BIO | INTR_MPSAFE, NULL,
+ (driver_intr_t *)ohci_interrupt, sc, &sc->sc_ohci.sc_intr_hdl);
+ if (err) {
+ err = ENXIO;
+ goto error;
+ }
+
+ strlcpy(sc->sc_ohci.sc_vendor, "Atheros", sizeof(sc->sc_ohci.sc_vendor));
+
+ bus_space_write_4(sc->sc_ohci.sc_io_tag, sc->sc_ohci.sc_io_hdl, OHCI_CONTROL, 0);
+
+ err = ohci_init(&sc->sc_ohci);
+ if (!err)
+ err = device_probe_and_attach(sc->sc_ohci.sc_bus.bdev);
+
+ if (err)
+ goto error;
+ return (0);
+
+error:
+ if (err) {
+ ar71xx_ohci_detach(dev);
+ return (err);
+ }
+ return (err);
+}
+
+static int
+ar71xx_ohci_detach(device_t dev)
+{
+ struct ar71xx_ohci_softc *sc = device_get_softc(dev);
+
+ /* during module unload there are lots of children leftover */
+ device_delete_children(dev);
+
+ /*
+ * Put the controller into reset, then disable clocks and do
+ * the MI tear down. We have to disable the clocks/hardware
+ * after we do the rest of the teardown. We also disable the
+ * clocks in the opposite order we acquire them, but that
+ * doesn't seem to be absolutely necessary. We free up the
+ * clocks after we disable them, so the system could, in
+ * theory, reuse them.
+ */
+ bus_space_write_4(sc->sc_ohci.sc_io_tag, sc->sc_ohci.sc_io_hdl,
+ OHCI_CONTROL, 0);
+
+ if (sc->sc_ohci.sc_intr_hdl) {
+ bus_teardown_intr(dev, sc->sc_ohci.sc_irq_res, sc->sc_ohci.sc_intr_hdl);
+ sc->sc_ohci.sc_intr_hdl = NULL;
+ }
+
+ if (sc->sc_ohci.sc_irq_res && sc->sc_ohci.sc_intr_hdl) {
+ /*
+ * only call ohci_detach() after ohci_init()
+ */
+ ohci_detach(&sc->sc_ohci);
+
+ bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sc_ohci.sc_irq_res);
+ sc->sc_ohci.sc_irq_res = NULL;
+ }
+ if (sc->sc_ohci.sc_io_res) {
+ bus_release_resource(dev, SYS_RES_MEMORY, 0, sc->sc_ohci.sc_io_res);
+ sc->sc_ohci.sc_io_res = NULL;
+ sc->sc_ohci.sc_io_tag = 0;
+ sc->sc_ohci.sc_io_hdl = 0;
+ }
+ usb_bus_mem_free_all(&sc->sc_ohci.sc_bus, &ohci_iterate_hw_softc);
+
+ return (0);
+}
+
+static device_method_t ohci_methods[] = {
+ /* Device interface */
+ DEVMETHOD(device_probe, ar71xx_ohci_probe),
+ DEVMETHOD(device_attach, ar71xx_ohci_attach),
+ DEVMETHOD(device_detach, ar71xx_ohci_detach),
+ DEVMETHOD(device_suspend, bus_generic_suspend),
+ DEVMETHOD(device_resume, bus_generic_resume),
+ DEVMETHOD(device_shutdown, bus_generic_shutdown),
+
+ DEVMETHOD_END
+};
+
+static driver_t ohci_driver = {
+ .name = "ohci",
+ .methods = ohci_methods,
+ .size = sizeof(struct ar71xx_ohci_softc),
+};
+
+static devclass_t ohci_devclass;
+
+DRIVER_MODULE(ohci, apb, ohci_driver, ohci_devclass, 0, 0);
Property changes on: trunk/sys/mips/atheros/ar71xx_ohci.c
___________________________________________________________________
Added: svn:eol-style
## -0,0 +1 ##
+native
\ No newline at end of property
Added: svn:keywords
## -0,0 +1 ##
+MidnightBSD=%H
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+text/plain
\ No newline at end of property
Added: trunk/sys/mips/atheros/ar71xx_pci.c
===================================================================
--- trunk/sys/mips/atheros/ar71xx_pci.c (rev 0)
+++ trunk/sys/mips/atheros/ar71xx_pci.c 2018-05-26 21:55:02 UTC (rev 9987)
@@ -0,0 +1,707 @@
+/* $MidnightBSD$ */
+/*-
+ * Copyright (c) 2009, Oleksandr Tymoshenko <gonzo at FreeBSD.org>
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice unmodified, this list of conditions, and the following
+ * disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ */
+
+#include <sys/cdefs.h>
+__FBSDID("$FreeBSD: stable/10/sys/mips/atheros/ar71xx_pci.c 265999 2014-05-14 01:35:43Z ian $");
+
+#include "opt_ar71xx.h"
+
+#include <sys/param.h>
+#include <sys/systm.h>
+
+#include <sys/bus.h>
+#include <sys/interrupt.h>
+#include <sys/malloc.h>
+#include <sys/kernel.h>
+#include <sys/module.h>
+#include <sys/rman.h>
+#include <sys/lock.h>
+#include <sys/mutex.h>
+
+#include <vm/vm.h>
+#include <vm/pmap.h>
+#include <vm/vm_extern.h>
+
+#include <machine/bus.h>
+#include <machine/cpu.h>
+#include <machine/intr_machdep.h>
+#include <machine/pmap.h>
+
+#include <dev/pci/pcivar.h>
+#include <dev/pci/pcireg.h>
+
+#include <dev/pci/pcib_private.h>
+#include "pcib_if.h"
+
+#include <mips/atheros/ar71xxreg.h>
+#include <mips/atheros/ar71xx_pci_bus_space.h>
+
+#include <mips/atheros/ar71xx_cpudef.h>
+
+#ifdef AR71XX_ATH_EEPROM
+#include <mips/atheros/ar71xx_fixup.h>
+#endif /* AR71XX_ATH_EEPROM */
+
+#undef AR71XX_PCI_DEBUG
+#ifdef AR71XX_PCI_DEBUG
+#define dprintf printf
+#else
+#define dprintf(x, arg...)
+#endif
+
+struct mtx ar71xx_pci_mtx;
+MTX_SYSINIT(ar71xx_pci_mtx, &ar71xx_pci_mtx, "ar71xx PCI space mutex",
+ MTX_SPIN);
+
+struct ar71xx_pci_softc {
+ device_t sc_dev;
+
+ int sc_busno;
+ int sc_baseslot;
+ struct rman sc_mem_rman;
+ struct rman sc_irq_rman;
+
+ struct intr_event *sc_eventstab[AR71XX_PCI_NIRQS];
+ mips_intrcnt_t sc_intr_counter[AR71XX_PCI_NIRQS];
+ struct resource *sc_irq;
+ void *sc_ih;
+};
+
+static int ar71xx_pci_setup_intr(device_t, device_t, struct resource *, int,
+ driver_filter_t *, driver_intr_t *, void *, void **);
+static int ar71xx_pci_teardown_intr(device_t, device_t, struct resource *,
+ void *);
+static int ar71xx_pci_intr(void *);
+
+static void
+ar71xx_pci_mask_irq(void *source)
+{
+ uint32_t reg;
+ unsigned int irq = (unsigned int)source;
+
+ /* XXX is the PCI lock required here? */
+ reg = ATH_READ_REG(AR71XX_PCI_INTR_MASK);
+ /* flush */
+ reg = ATH_READ_REG(AR71XX_PCI_INTR_MASK);
+ ATH_WRITE_REG(AR71XX_PCI_INTR_MASK, reg & ~(1 << irq));
+}
+
+static void
+ar71xx_pci_unmask_irq(void *source)
+{
+ uint32_t reg;
+ unsigned int irq = (unsigned int)source;
+
+ /* XXX is the PCI lock required here? */
+ reg = ATH_READ_REG(AR71XX_PCI_INTR_MASK);
+ ATH_WRITE_REG(AR71XX_PCI_INTR_MASK, reg | (1 << irq));
+ /* flush */
+ reg = ATH_READ_REG(AR71XX_PCI_INTR_MASK);
+}
+
+/*
+ * get bitmask for bytes of interest:
+ * 0 - we want this byte, 1 - ignore it. e.g: we read 1 byte
+ * from register 7. Bitmask would be: 0111
+ */
+static uint32_t
+ar71xx_get_bytes_to_read(int reg, int bytes)
+{
+ uint32_t bytes_to_read = 0;
+
+ if ((bytes % 4) == 0)
+ bytes_to_read = 0;
+ else if ((bytes % 4) == 1)
+ bytes_to_read = (~(1 << (reg % 4))) & 0xf;
+ else if ((bytes % 4) == 2)
+ bytes_to_read = (~(3 << (reg % 4))) & 0xf;
+ else
+ panic("%s: wrong combination", __func__);
+
+ return (bytes_to_read);
+}
+
+static int
+ar71xx_pci_check_bus_error(void)
+{
+ uint32_t error, addr, has_errors = 0;
+
+ mtx_assert(&ar71xx_pci_mtx, MA_OWNED);
+
+ error = ATH_READ_REG(AR71XX_PCI_ERROR) & 0x3;
+ dprintf("%s: PCI error = %02x\n", __func__, error);
+ if (error) {
+ addr = ATH_READ_REG(AR71XX_PCI_ERROR_ADDR);
+
+ /* Do not report it yet */
+#if 0
+ printf("PCI bus error %d at addr 0x%08x\n", error, addr);
+#endif
+ ATH_WRITE_REG(AR71XX_PCI_ERROR, error);
+ has_errors = 1;
+ }
+
+ error = ATH_READ_REG(AR71XX_PCI_AHB_ERROR) & 0x1;
+ dprintf("%s: AHB error = %02x\n", __func__, error);
+ if (error) {
+ addr = ATH_READ_REG(AR71XX_PCI_AHB_ERROR_ADDR);
+ /* Do not report it yet */
+#if 0
+ printf("AHB bus error %d at addr 0x%08x\n", error, addr);
+#endif
+ ATH_WRITE_REG(AR71XX_PCI_AHB_ERROR, error);
+ has_errors = 1;
+ }
+
+ return (has_errors);
+}
+
+static uint32_t
+ar71xx_pci_make_addr(int bus, int slot, int func, int reg)
+{
+ if (bus == 0) {
+ return ((1 << slot) | (func << 8) | (reg & ~3));
+ } else {
+ return ((bus << 16) | (slot << 11) | (func << 8)
+ | (reg & ~3) | 1);
+ }
+}
+
+static int
+ar71xx_pci_conf_setup(int bus, int slot, int func, int reg, int bytes,
+ uint32_t cmd)
+{
+ uint32_t addr = ar71xx_pci_make_addr(bus, slot, func, (reg & ~3));
+
+ mtx_assert(&ar71xx_pci_mtx, MA_OWNED);
+
+ cmd |= (ar71xx_get_bytes_to_read(reg, bytes) << 4);
+ ATH_WRITE_REG(AR71XX_PCI_CONF_ADDR, addr);
+ ATH_WRITE_REG(AR71XX_PCI_CONF_CMD, cmd);
+
+ dprintf("%s: tag (%x, %x, %x) %d/%d addr=%08x, cmd=%08x\n", __func__,
+ bus, slot, func, reg, bytes, addr, cmd);
+
+ return ar71xx_pci_check_bus_error();
+}
+
+static uint32_t
+ar71xx_pci_read_config(device_t dev, u_int bus, u_int slot, u_int func,
+ u_int reg, int bytes)
+{
+ uint32_t data;
+ uint32_t shift, mask;
+
+ /* register access is 32-bit aligned */
+ shift = (reg & 3) * 8;
+
+ /* Create a mask based on the width, post-shift */
+ if (bytes == 2)
+ mask = 0xffff;
+ else if (bytes == 1)
+ mask = 0xff;
+ else
+ mask = 0xffffffff;
+
+ dprintf("%s: tag (%x, %x, %x) reg %d(%d)\n", __func__, bus, slot,
+ func, reg, bytes);
+
+ mtx_lock_spin(&ar71xx_pci_mtx);
+ if (ar71xx_pci_conf_setup(bus, slot, func, reg, bytes,
+ PCI_CONF_CMD_READ) == 0)
+ data = ATH_READ_REG(AR71XX_PCI_CONF_READ_DATA);
+ else
+ data = -1;
+ mtx_unlock_spin(&ar71xx_pci_mtx);
+
+ /* get request bytes from 32-bit word */
+ data = (data >> shift) & mask;
+
+ dprintf("%s: read 0x%x\n", __func__, data);
+
+ return (data);
+}
+
+static void
+ar71xx_pci_local_write(device_t dev, uint32_t reg, uint32_t data, int bytes)
+{
+ uint32_t cmd;
+
+ dprintf("%s: local write reg %d(%d)\n", __func__, reg, bytes);
+
+ data = data << (8*(reg % 4));
+ cmd = PCI_LCONF_CMD_WRITE | (reg & ~3);
+ cmd |= (ar71xx_get_bytes_to_read(reg, bytes) << 20);
+ mtx_lock_spin(&ar71xx_pci_mtx);
+ ATH_WRITE_REG(AR71XX_PCI_LCONF_CMD, cmd);
+ ATH_WRITE_REG(AR71XX_PCI_LCONF_WRITE_DATA, data);
+ mtx_unlock_spin(&ar71xx_pci_mtx);
+}
+
+static void
+ar71xx_pci_write_config(device_t dev, u_int bus, u_int slot, u_int func,
+ u_int reg, uint32_t data, int bytes)
+{
+
+ dprintf("%s: tag (%x, %x, %x) reg %d(%d)\n", __func__, bus, slot,
+ func, reg, bytes);
+
+ data = data << (8*(reg % 4));
+ mtx_lock_spin(&ar71xx_pci_mtx);
+ if (ar71xx_pci_conf_setup(bus, slot, func, reg, bytes,
+ PCI_CONF_CMD_WRITE) == 0)
+ ATH_WRITE_REG(AR71XX_PCI_CONF_WRITE_DATA, data);
+ mtx_unlock_spin(&ar71xx_pci_mtx);
+}
+
+#ifdef AR71XX_ATH_EEPROM
+/*
+ * Some embedded boards (eg AP94) have the MAC attached via PCI but they
+ * don't have the MAC-attached EEPROM. The register initialisation
+ * values and calibration data are stored in the on-board flash.
+ * This routine initialises the NIC via the EEPROM register contents
+ * before the probe/attach routines get a go at things.
+ */
+static void
+ar71xx_pci_fixup(device_t dev, u_int bus, u_int slot, u_int func,
+ long flash_addr, int len)
+{
+ uint16_t *cal_data = (uint16_t *) MIPS_PHYS_TO_KSEG1(flash_addr);
+ uint32_t reg, val, bar0;
+
+ if (bootverbose)
+ device_printf(dev, "%s: flash_addr=%lx, cal_data=%p\n",
+ __func__, flash_addr, cal_data);
+
+ /* XXX check 0xa55a */
+ /* Save bar(0) address - just to flush bar(0) (SoC WAR) ? */
+ bar0 = ar71xx_pci_read_config(dev, bus, slot, func, PCIR_BAR(0), 4);
+ ar71xx_pci_write_config(dev, bus, slot, func, PCIR_BAR(0),
+ AR71XX_PCI_MEM_BASE, 4);
+
+ val = ar71xx_pci_read_config(dev, bus, slot, func, PCIR_COMMAND, 2);
+ val |= (PCIM_CMD_BUSMASTEREN | PCIM_CMD_MEMEN);
+ ar71xx_pci_write_config(dev, bus, slot, func, PCIR_COMMAND, val, 2);
+
+ cal_data += 3;
+ while (*cal_data != 0xffff) {
+ reg = *cal_data++;
+ val = *cal_data++;
+ val |= (*cal_data++) << 16;
+ if (bootverbose)
+ printf(" reg: %x, val=%x\n", reg, val);
+
+ /* Write eeprom fixup data to device memory */
+ ATH_WRITE_REG(AR71XX_PCI_MEM_BASE + reg, val);
+ DELAY(100);
+ }
+
+ val = ar71xx_pci_read_config(dev, bus, slot, func, PCIR_COMMAND, 2);
+ val &= ~(PCIM_CMD_BUSMASTEREN | PCIM_CMD_MEMEN);
+ ar71xx_pci_write_config(dev, bus, slot, func, PCIR_COMMAND, val, 2);
+
+ /* Write the saved bar(0) address */
+ ar71xx_pci_write_config(dev, bus, slot, func, PCIR_BAR(0), bar0, 4);
+}
+
+static void
+ar71xx_pci_slot_fixup(device_t dev, u_int bus, u_int slot, u_int func)
+{
+ long int flash_addr;
+ char buf[64];
+ int size;
+
+ /*
+ * Check whether the given slot has a hint to poke.
+ */
+ if (bootverbose)
+ device_printf(dev, "%s: checking dev %s, %d/%d/%d\n",
+ __func__, device_get_nameunit(dev), bus, slot, func);
+
+ snprintf(buf, sizeof(buf), "bus.%d.%d.%d.ath_fixup_addr",
+ bus, slot, func);
+
+ if (resource_long_value(device_get_name(dev), device_get_unit(dev),
+ buf, &flash_addr) == 0) {
+ snprintf(buf, sizeof(buf), "bus.%d.%d.%d.ath_fixup_size",
+ bus, slot, func);
+ if (resource_int_value(device_get_name(dev),
+ device_get_unit(dev), buf, &size) != 0) {
+ device_printf(dev,
+ "%s: missing hint '%s', aborting EEPROM\n",
+ __func__, buf);
+ return;
+ }
+
+
+ device_printf(dev, "found EEPROM at 0x%lx on %d.%d.%d\n",
+ flash_addr, bus, slot, func);
+ ar71xx_pci_fixup(dev, bus, slot, func, flash_addr, size);
+ ar71xx_pci_slot_create_eeprom_firmware(dev, bus, slot, func,
+ flash_addr, size);
+ }
+}
+#endif /* AR71XX_ATH_EEPROM */
+
+static int
+ar71xx_pci_probe(device_t dev)
+{
+
+ return (BUS_PROBE_NOWILDCARD);
+}
+
+static int
+ar71xx_pci_attach(device_t dev)
+{
+ int busno = 0;
+ int rid = 0;
+ struct ar71xx_pci_softc *sc = device_get_softc(dev);
+
+ sc->sc_mem_rman.rm_type = RMAN_ARRAY;
+ sc->sc_mem_rman.rm_descr = "ar71xx PCI memory window";
+ if (rman_init(&sc->sc_mem_rman) != 0 ||
+ rman_manage_region(&sc->sc_mem_rman, AR71XX_PCI_MEM_BASE,
+ AR71XX_PCI_MEM_BASE + AR71XX_PCI_MEM_SIZE - 1) != 0) {
+ panic("ar71xx_pci_attach: failed to set up I/O rman");
+ }
+
+ sc->sc_irq_rman.rm_type = RMAN_ARRAY;
+ sc->sc_irq_rman.rm_descr = "ar71xx PCI IRQs";
+ if (rman_init(&sc->sc_irq_rman) != 0 ||
+ rman_manage_region(&sc->sc_irq_rman, AR71XX_PCI_IRQ_START,
+ AR71XX_PCI_IRQ_END) != 0)
+ panic("ar71xx_pci_attach: failed to set up IRQ rman");
+
+ /*
+ * Check if there is a base slot hint. Otherwise use default value.
+ */
+ if (resource_int_value(device_get_name(dev),
+ device_get_unit(dev), "baseslot", &sc->sc_baseslot) != 0) {
+ device_printf(dev,
+ "%s: missing hint '%s', default to AR71XX_PCI_BASE_SLOT\n",
+ __func__, "baseslot");
+ sc->sc_baseslot = AR71XX_PCI_BASE_SLOT;
+ }
+
+ ATH_WRITE_REG(AR71XX_PCI_INTR_STATUS, 0);
+ ATH_WRITE_REG(AR71XX_PCI_INTR_MASK, 0);
+
+ /* Hook up our interrupt handler. */
+ if ((sc->sc_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
+ RF_SHAREABLE | RF_ACTIVE)) == NULL) {
+ device_printf(dev, "unable to allocate IRQ resource\n");
+ return ENXIO;
+ }
+
+ if ((bus_setup_intr(dev, sc->sc_irq, INTR_TYPE_MISC,
+ ar71xx_pci_intr, NULL, sc, &sc->sc_ih))) {
+ device_printf(dev,
+ "WARNING: unable to register interrupt handler\n");
+ return ENXIO;
+ }
+
+ /* reset PCI core and PCI bus */
+ ar71xx_device_stop(RST_RESET_PCI_CORE | RST_RESET_PCI_BUS);
+ DELAY(100000);
+
+ ar71xx_device_start(RST_RESET_PCI_CORE | RST_RESET_PCI_BUS);
+ DELAY(100000);
+
+ /* Init PCI windows */
+ ATH_WRITE_REG(AR71XX_PCI_WINDOW0, PCI_WINDOW0_ADDR);
+ ATH_WRITE_REG(AR71XX_PCI_WINDOW1, PCI_WINDOW1_ADDR);
+ ATH_WRITE_REG(AR71XX_PCI_WINDOW2, PCI_WINDOW2_ADDR);
+ ATH_WRITE_REG(AR71XX_PCI_WINDOW3, PCI_WINDOW3_ADDR);
+ ATH_WRITE_REG(AR71XX_PCI_WINDOW4, PCI_WINDOW4_ADDR);
+ ATH_WRITE_REG(AR71XX_PCI_WINDOW5, PCI_WINDOW5_ADDR);
+ ATH_WRITE_REG(AR71XX_PCI_WINDOW6, PCI_WINDOW6_ADDR);
+ ATH_WRITE_REG(AR71XX_PCI_WINDOW7, PCI_WINDOW7_CONF_ADDR);
+ DELAY(100000);
+
+ mtx_lock_spin(&ar71xx_pci_mtx);
+ ar71xx_pci_check_bus_error();
+ mtx_unlock_spin(&ar71xx_pci_mtx);
+
+ /* Fixup internal PCI bridge */
+ ar71xx_pci_local_write(dev, PCIR_COMMAND,
+ PCIM_CMD_BUSMASTEREN | PCIM_CMD_MEMEN
+ | PCIM_CMD_SERRESPEN | PCIM_CMD_BACKTOBACK
+ | PCIM_CMD_PERRESPEN | PCIM_CMD_MWRICEN, 4);
+
+#ifdef AR71XX_ATH_EEPROM
+ /*
+ * Hard-code a check for slot 17 and 18 - these are
+ * the two PCI slots which may have a PCI device that
+ * requires "fixing".
+ */
+ ar71xx_pci_slot_fixup(dev, 0, 17, 0);
+ ar71xx_pci_slot_fixup(dev, 0, 18, 0);
+#endif /* AR71XX_ATH_EEPROM */
+
+ device_add_child(dev, "pci", busno);
+ return (bus_generic_attach(dev));
+}
+
+static int
+ar71xx_pci_read_ivar(device_t dev, device_t child, int which,
+ uintptr_t *result)
+{
+ struct ar71xx_pci_softc *sc = device_get_softc(dev);
+
+ switch (which) {
+ case PCIB_IVAR_DOMAIN:
+ *result = 0;
+ return (0);
+ case PCIB_IVAR_BUS:
+ *result = sc->sc_busno;
+ return (0);
+ }
+
+ return (ENOENT);
+}
+
+static int
+ar71xx_pci_write_ivar(device_t dev, device_t child, int which,
+ uintptr_t result)
+{
+ struct ar71xx_pci_softc * sc = device_get_softc(dev);
+
+ switch (which) {
+ case PCIB_IVAR_BUS:
+ sc->sc_busno = result;
+ return (0);
+ }
+
+ return (ENOENT);
+}
+
+static struct resource *
+ar71xx_pci_alloc_resource(device_t bus, device_t child, int type, int *rid,
+ u_long start, u_long end, u_long count, u_int flags)
+{
+
+ struct ar71xx_pci_softc *sc = device_get_softc(bus);
+ struct resource *rv;
+ struct rman *rm;
+
+ switch (type) {
+ case SYS_RES_IRQ:
+ rm = &sc->sc_irq_rman;
+ break;
+ case SYS_RES_MEMORY:
+ rm = &sc->sc_mem_rman;
+ break;
+ default:
+ return (NULL);
+ }
+
+ rv = rman_reserve_resource(rm, start, end, count, flags, child);
+
+ if (rv == NULL)
+ return (NULL);
+
+ rman_set_rid(rv, *rid);
+
+ if (flags & RF_ACTIVE) {
+ if (bus_activate_resource(child, type, *rid, rv)) {
+ rman_release_resource(rv);
+ return (NULL);
+ }
+ }
+ return (rv);
+}
+
+static int
+ar71xx_pci_activate_resource(device_t bus, device_t child, int type, int rid,
+ struct resource *r)
+{
+ int res = (BUS_ACTIVATE_RESOURCE(device_get_parent(bus),
+ child, type, rid, r));
+
+ if (!res) {
+ switch(type) {
+ case SYS_RES_MEMORY:
+ case SYS_RES_IOPORT:
+ rman_set_bustag(r, ar71xx_bus_space_pcimem);
+ break;
+ }
+ }
+ return (res);
+}
+
+static int
+ar71xx_pci_setup_intr(device_t bus, device_t child, struct resource *ires,
+ int flags, driver_filter_t *filt, driver_intr_t *handler,
+ void *arg, void **cookiep)
+{
+ struct ar71xx_pci_softc *sc = device_get_softc(bus);
+ struct intr_event *event;
+ int irq, error;
+
+ irq = rman_get_start(ires);
+
+ if (irq > AR71XX_PCI_IRQ_END)
+ panic("%s: bad irq %d", __func__, irq);
+
+ event = sc->sc_eventstab[irq];
+ if (event == NULL) {
+ error = intr_event_create(&event, (void *)irq, 0, irq,
+ ar71xx_pci_mask_irq, ar71xx_pci_unmask_irq, NULL, NULL,
+ "pci intr%d:", irq);
+
+ if (error == 0) {
+ sc->sc_eventstab[irq] = event;
+ sc->sc_intr_counter[irq] =
+ mips_intrcnt_create(event->ie_name);
+ }
+ else
+ return (error);
+ }
+
+ intr_event_add_handler(event, device_get_nameunit(child), filt,
+ handler, arg, intr_priority(flags), flags, cookiep);
+ mips_intrcnt_setname(sc->sc_intr_counter[irq], event->ie_fullname);
+
+ ar71xx_pci_unmask_irq((void*)irq);
+
+ return (0);
+}
+
+static int
+ar71xx_pci_teardown_intr(device_t dev, device_t child, struct resource *ires,
+ void *cookie)
+{
+ struct ar71xx_pci_softc *sc = device_get_softc(dev);
+ int irq, result;
+
+ irq = rman_get_start(ires);
+ if (irq > AR71XX_PCI_IRQ_END)
+ panic("%s: bad irq %d", __func__, irq);
+
+ if (sc->sc_eventstab[irq] == NULL)
+ panic("Trying to teardown unoccupied IRQ");
+
+ ar71xx_pci_mask_irq((void*)irq);
+
+ result = intr_event_remove_handler(cookie);
+ if (!result)
+ sc->sc_eventstab[irq] = NULL;
+
+ return (result);
+}
+
+static int
+ar71xx_pci_intr(void *arg)
+{
+ struct ar71xx_pci_softc *sc = arg;
+ struct intr_event *event;
+ uint32_t reg, irq, mask;
+
+ reg = ATH_READ_REG(AR71XX_PCI_INTR_STATUS);
+ mask = ATH_READ_REG(AR71XX_PCI_INTR_MASK);
+ /*
+ * Handle only unmasked interrupts
+ */
+ reg &= mask;
+ for (irq = AR71XX_PCI_IRQ_START; irq <= AR71XX_PCI_IRQ_END; irq++) {
+ if (reg & (1 << irq)) {
+ event = sc->sc_eventstab[irq];
+ if (!event || TAILQ_EMPTY(&event->ie_handlers)) {
+ /* Ignore timer interrupts */
+ if (irq != 0)
+ printf("Stray IRQ %d\n", irq);
+ continue;
+ }
+
+ /* Flush DDR FIFO for IP2 */
+ ar71xx_device_ddr_flush_ip2();
+
+ /* TODO: frame instead of NULL? */
+ intr_event_handle(event, NULL);
+ mips_intrcnt_inc(sc->sc_intr_counter[irq]);
+ }
+ }
+
+ return (FILTER_HANDLED);
+}
+
+static int
+ar71xx_pci_maxslots(device_t dev)
+{
+
+ return (PCI_SLOTMAX);
+}
+
+static int
+ar71xx_pci_route_interrupt(device_t pcib, device_t device, int pin)
+{
+ struct ar71xx_pci_softc *sc = device_get_softc(pcib);
+
+ if (pci_get_slot(device) < sc->sc_baseslot)
+ panic("%s: PCI slot %d is less then AR71XX_PCI_BASE_SLOT",
+ __func__, pci_get_slot(device));
+
+ return (pci_get_slot(device) - sc->sc_baseslot);
+}
+
+static device_method_t ar71xx_pci_methods[] = {
+ /* Device interface */
+ DEVMETHOD(device_probe, ar71xx_pci_probe),
+ DEVMETHOD(device_attach, ar71xx_pci_attach),
+ DEVMETHOD(device_shutdown, bus_generic_shutdown),
+ DEVMETHOD(device_suspend, bus_generic_suspend),
+ DEVMETHOD(device_resume, bus_generic_resume),
+
+ /* Bus interface */
+ DEVMETHOD(bus_read_ivar, ar71xx_pci_read_ivar),
+ DEVMETHOD(bus_write_ivar, ar71xx_pci_write_ivar),
+ DEVMETHOD(bus_alloc_resource, ar71xx_pci_alloc_resource),
+ DEVMETHOD(bus_release_resource, bus_generic_release_resource),
+ DEVMETHOD(bus_activate_resource, ar71xx_pci_activate_resource),
+ DEVMETHOD(bus_deactivate_resource, bus_generic_deactivate_resource),
+ DEVMETHOD(bus_setup_intr, ar71xx_pci_setup_intr),
+ DEVMETHOD(bus_teardown_intr, ar71xx_pci_teardown_intr),
+
+ /* pcib interface */
+ DEVMETHOD(pcib_maxslots, ar71xx_pci_maxslots),
+ DEVMETHOD(pcib_read_config, ar71xx_pci_read_config),
+ DEVMETHOD(pcib_write_config, ar71xx_pci_write_config),
+ DEVMETHOD(pcib_route_interrupt, ar71xx_pci_route_interrupt),
+
+ DEVMETHOD_END
+};
+
+static driver_t ar71xx_pci_driver = {
+ "pcib",
+ ar71xx_pci_methods,
+ sizeof(struct ar71xx_pci_softc),
+};
+
+static devclass_t ar71xx_pci_devclass;
+
+DRIVER_MODULE(ar71xx_pci, nexus, ar71xx_pci_driver, ar71xx_pci_devclass, 0, 0);
Property changes on: trunk/sys/mips/atheros/ar71xx_pci.c
___________________________________________________________________
Added: svn:eol-style
## -0,0 +1 ##
+native
\ No newline at end of property
Added: svn:keywords
## -0,0 +1 ##
+MidnightBSD=%H
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+text/plain
\ No newline at end of property
Added: trunk/sys/mips/atheros/ar71xx_pci_bus_space.c
===================================================================
--- trunk/sys/mips/atheros/ar71xx_pci_bus_space.c (rev 0)
+++ trunk/sys/mips/atheros/ar71xx_pci_bus_space.c 2018-05-26 21:55:02 UTC (rev 9987)
@@ -0,0 +1,199 @@
+/* $MidnightBSD$ */
+/*-
+ * Copyright (c) 2009, Oleksandr Tymoshenko <gonzo at FreeBSD.org>
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice unmodified, this list of conditions, and the following
+ * disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ */
+#include <sys/cdefs.h>
+__FBSDID("$FreeBSD: stable/10/sys/mips/atheros/ar71xx_pci_bus_space.c 202175 2010-01-12 21:36:08Z imp $");
+
+#include <sys/param.h>
+#include <sys/systm.h>
+#include <sys/bus.h>
+#include <sys/endian.h>
+
+#include <machine/bus.h>
+#include <mips/atheros/ar71xx_pci_bus_space.h>
+
+static bs_r_1_s_proto(pcimem);
+static bs_r_2_s_proto(pcimem);
+static bs_r_4_s_proto(pcimem);
+static bs_w_1_s_proto(pcimem);
+static bs_w_2_s_proto(pcimem);
+static bs_w_4_s_proto(pcimem);
+
+/*
+ * Bus space that handles offsets in word for 1/2 bytes read/write access.
+ * Byte order of values is handled by device drivers itself.
+ */
+static struct bus_space bus_space_pcimem = {
+ /* cookie */
+ (void *) 0,
+
+ /* mapping/unmapping */
+ generic_bs_map,
+ generic_bs_unmap,
+ generic_bs_subregion,
+
+ /* allocation/deallocation */
+ NULL,
+ NULL,
+
+ /* barrier */
+ generic_bs_barrier,
+
+ /* read (single) */
+ generic_bs_r_1,
+ generic_bs_r_2,
+ generic_bs_r_4,
+ NULL,
+
+ /* read multiple */
+ generic_bs_rm_1,
+ generic_bs_rm_2,
+ generic_bs_rm_4,
+ NULL,
+
+ /* read region */
+ generic_bs_rr_1,
+ generic_bs_rr_2,
+ generic_bs_rr_4,
+ NULL,
+
+ /* write (single) */
+ generic_bs_w_1,
+ generic_bs_w_2,
+ generic_bs_w_4,
+ NULL,
+
+ /* write multiple */
+ generic_bs_wm_1,
+ generic_bs_wm_2,
+ generic_bs_wm_4,
+ NULL,
+
+ /* write region */
+ NULL,
+ generic_bs_wr_2,
+ generic_bs_wr_4,
+ NULL,
+
+ /* set multiple */
+ NULL,
+ NULL,
+ NULL,
+ NULL,
+
+ /* set region */
+ NULL,
+ generic_bs_sr_2,
+ generic_bs_sr_4,
+ NULL,
+
+ /* copy */
+ NULL,
+ generic_bs_c_2,
+ NULL,
+ NULL,
+
+ /* read (single) stream */
+ pcimem_bs_r_1_s,
+ pcimem_bs_r_2_s,
+ pcimem_bs_r_4_s,
+ NULL,
+
+ /* read multiple stream */
+ generic_bs_rm_1,
+ generic_bs_rm_2,
+ generic_bs_rm_4,
+ NULL,
+
+ /* read region stream */
+ generic_bs_rr_1,
+ generic_bs_rr_2,
+ generic_bs_rr_4,
+ NULL,
+
+ /* write (single) stream */
+ pcimem_bs_w_1_s,
+ pcimem_bs_w_2_s,
+ pcimem_bs_w_4_s,
+ NULL,
+
+ /* write multiple stream */
+ generic_bs_wm_1,
+ generic_bs_wm_2,
+ generic_bs_wm_4,
+ NULL,
+
+ /* write region stream */
+ NULL,
+ generic_bs_wr_2,
+ generic_bs_wr_4,
+ NULL,
+};
+
+bus_space_tag_t ar71xx_bus_space_pcimem = &bus_space_pcimem;
+
+static uint8_t
+pcimem_bs_r_1_s(void *t, bus_space_handle_t h, bus_size_t o)
+{
+
+ return readb(h + (o &~ 3) + (3 - (o & 3)));
+}
+
+static void
+pcimem_bs_w_1_s(void *t, bus_space_handle_t h, bus_size_t o, u_int8_t v)
+{
+
+ writeb(h + (o &~ 3) + (3 - (o & 3)), v);
+}
+
+static uint16_t
+pcimem_bs_r_2_s(void *t, bus_space_handle_t h, bus_size_t o)
+{
+
+ return readw(h + (o &~ 3) + (2 - (o & 3)));
+}
+
+static void
+pcimem_bs_w_2_s(void *t, bus_space_handle_t h, bus_size_t o, uint16_t v)
+{
+
+ writew(h + (o &~ 3) + (2 - (o & 3)), v);
+}
+
+static uint32_t
+pcimem_bs_r_4_s(void *t, bus_space_handle_t h, bus_size_t o)
+{
+
+ return le32toh(readl(h + o));
+}
+
+static void
+pcimem_bs_w_4_s(void *t, bus_space_handle_t h, bus_size_t o, uint32_t v)
+{
+
+ writel(h + o, htole32(v));
+}
Property changes on: trunk/sys/mips/atheros/ar71xx_pci_bus_space.c
___________________________________________________________________
Added: svn:eol-style
## -0,0 +1 ##
+native
\ No newline at end of property
Added: svn:keywords
## -0,0 +1 ##
+MidnightBSD=%H
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+text/plain
\ No newline at end of property
Added: trunk/sys/mips/atheros/ar71xx_pci_bus_space.h
===================================================================
--- trunk/sys/mips/atheros/ar71xx_pci_bus_space.h (rev 0)
+++ trunk/sys/mips/atheros/ar71xx_pci_bus_space.h 2018-05-26 21:55:02 UTC (rev 9987)
@@ -0,0 +1,34 @@
+/* $MidnightBSD$ */
+/*-
+ * Copyright (c) 2009, Oleksandr Tymoshenko <gonzo at FreeBSD.org>
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice unmodified, this list of conditions, and the following
+ * disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ */
+
+#ifndef __AR71XX_PCI_BUS_SPACEH__
+#define __AR71XX_PCI_BUS_SPACEH__
+
+extern bus_space_tag_t ar71xx_bus_space_pcimem;
+
+#endif /* __AR71XX_PCI_BUS_SPACEH__ */
Property changes on: trunk/sys/mips/atheros/ar71xx_pci_bus_space.h
___________________________________________________________________
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Added: trunk/sys/mips/atheros/ar71xx_setup.c
===================================================================
--- trunk/sys/mips/atheros/ar71xx_setup.c (rev 0)
+++ trunk/sys/mips/atheros/ar71xx_setup.c 2018-05-26 21:55:02 UTC (rev 9987)
@@ -0,0 +1,200 @@
+/* $MidnightBSD$ */
+/*-
+ * Copyright (c) 2010 Adrian Chadd
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ */
+
+#include <sys/cdefs.h>
+__FBSDID("$FreeBSD: stable/10/sys/mips/atheros/ar71xx_setup.c 253511 2013-07-21 03:56:57Z adrian $");
+
+#include "opt_ddb.h"
+
+#include <sys/param.h>
+#include <sys/conf.h>
+#include <sys/kernel.h>
+#include <sys/systm.h>
+#include <sys/bus.h>
+#include <sys/cons.h>
+#include <sys/kdb.h>
+#include <sys/reboot.h>
+
+#include <vm/vm.h>
+#include <vm/vm_page.h>
+
+#include <net/ethernet.h>
+
+#include <machine/clock.h>
+#include <machine/cpu.h>
+#include <machine/cpuregs.h>
+#include <machine/hwfunc.h>
+#include <machine/md_var.h>
+#include <machine/trap.h>
+#include <machine/vmparam.h>
+
+#include <mips/atheros/ar71xxreg.h>
+#include <mips/atheros/ar933xreg.h>
+#include <mips/atheros/ar934xreg.h>
+
+#include <mips/atheros/ar71xx_setup.h>
+
+#include <mips/atheros/ar71xx_cpudef.h>
+
+#include <mips/atheros/ar71xx_chip.h>
+#include <mips/atheros/ar724x_chip.h>
+#include <mips/atheros/ar91xx_chip.h>
+#include <mips/atheros/ar933x_chip.h>
+#include <mips/atheros/ar934x_chip.h>
+
+#define AR71XX_SYS_TYPE_LEN 128
+
+static char ar71xx_sys_type[AR71XX_SYS_TYPE_LEN];
+enum ar71xx_soc_type ar71xx_soc;
+struct ar71xx_cpu_def * ar71xx_cpu_ops = NULL;
+
+void
+ar71xx_detect_sys_type(void)
+{
+ char *chip = "????";
+ uint32_t id;
+ uint32_t major;
+ uint32_t minor;
+ uint32_t rev = 0;
+
+ id = ATH_READ_REG(AR71XX_RST_RESET_REG_REV_ID);
+ major = id & REV_ID_MAJOR_MASK;
+
+ switch (major) {
+ case REV_ID_MAJOR_AR71XX:
+ minor = id & AR71XX_REV_ID_MINOR_MASK;
+ rev = id >> AR71XX_REV_ID_REVISION_SHIFT;
+ rev &= AR71XX_REV_ID_REVISION_MASK;
+ ar71xx_cpu_ops = &ar71xx_chip_def;
+ switch (minor) {
+ case AR71XX_REV_ID_MINOR_AR7130:
+ ar71xx_soc = AR71XX_SOC_AR7130;
+ chip = "7130";
+ break;
+
+ case AR71XX_REV_ID_MINOR_AR7141:
+ ar71xx_soc = AR71XX_SOC_AR7141;
+ chip = "7141";
+ break;
+
+ case AR71XX_REV_ID_MINOR_AR7161:
+ ar71xx_soc = AR71XX_SOC_AR7161;
+ chip = "7161";
+ break;
+ }
+ break;
+
+ case REV_ID_MAJOR_AR7240:
+ ar71xx_soc = AR71XX_SOC_AR7240;
+ chip = "7240";
+ ar71xx_cpu_ops = &ar724x_chip_def;
+ rev = (id & AR724X_REV_ID_REVISION_MASK);
+ break;
+
+ case REV_ID_MAJOR_AR7241:
+ ar71xx_soc = AR71XX_SOC_AR7241;
+ chip = "7241";
+ ar71xx_cpu_ops = &ar724x_chip_def;
+ rev = (id & AR724X_REV_ID_REVISION_MASK);
+ break;
+
+ case REV_ID_MAJOR_AR7242:
+ ar71xx_soc = AR71XX_SOC_AR7242;
+ chip = "7242";
+ ar71xx_cpu_ops = &ar724x_chip_def;
+ rev = (id & AR724X_REV_ID_REVISION_MASK);
+ break;
+
+ case REV_ID_MAJOR_AR913X:
+ minor = id & AR91XX_REV_ID_MINOR_MASK;
+ rev = id >> AR91XX_REV_ID_REVISION_SHIFT;
+ rev &= AR91XX_REV_ID_REVISION_MASK;
+ ar71xx_cpu_ops = &ar91xx_chip_def;
+ switch (minor) {
+ case AR91XX_REV_ID_MINOR_AR9130:
+ ar71xx_soc = AR71XX_SOC_AR9130;
+ chip = "9130";
+ break;
+
+ case AR91XX_REV_ID_MINOR_AR9132:
+ ar71xx_soc = AR71XX_SOC_AR9132;
+ chip = "9132";
+ break;
+ }
+ break;
+ case REV_ID_MAJOR_AR9330:
+ minor = 0;
+ rev = (id & AR933X_REV_ID_REVISION_MASK);
+ chip = "9330";
+ ar71xx_cpu_ops = &ar933x_chip_def;
+ ar71xx_soc = AR71XX_SOC_AR9330;
+ break;
+ case REV_ID_MAJOR_AR9331:
+ minor = 1;
+ rev = (id & AR933X_REV_ID_REVISION_MASK);
+ chip = "9331";
+ ar71xx_soc = AR71XX_SOC_AR9331;
+ ar71xx_cpu_ops = &ar933x_chip_def;
+ break;
+
+ case REV_ID_MAJOR_AR9341:
+ minor = 0;
+ rev = (id & AR934X_REV_ID_REVISION_MASK);
+ chip = "9341";
+ ar71xx_soc = AR71XX_SOC_AR9341;
+ ar71xx_cpu_ops = &ar934x_chip_def;
+ break;
+
+ case REV_ID_MAJOR_AR9342:
+ minor = 0;
+ rev = (id & AR934X_REV_ID_REVISION_MASK);
+ chip = "9342";
+ ar71xx_soc = AR71XX_SOC_AR9342;
+ ar71xx_cpu_ops = &ar934x_chip_def;
+ break;
+
+ case REV_ID_MAJOR_AR9344:
+ minor = 0;
+ rev = (id & AR934X_REV_ID_REVISION_MASK);
+ chip = "9344";
+ ar71xx_soc = AR71XX_SOC_AR9344;
+ ar71xx_cpu_ops = &ar934x_chip_def;
+ break;
+
+ default:
+ panic("ar71xx: unknown chip id:0x%08x\n", id);
+ }
+
+ sprintf(ar71xx_sys_type, "Atheros AR%s rev %u", chip, rev);
+}
+
+const char *
+ar71xx_get_system_type(void)
+{
+ return ar71xx_sys_type;
+}
+
Property changes on: trunk/sys/mips/atheros/ar71xx_setup.c
___________________________________________________________________
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Added: trunk/sys/mips/atheros/ar71xx_setup.h
===================================================================
--- trunk/sys/mips/atheros/ar71xx_setup.h (rev 0)
+++ trunk/sys/mips/atheros/ar71xx_setup.h 2018-05-26 21:55:02 UTC (rev 9987)
@@ -0,0 +1,54 @@
+/* $MidnightBSD$ */
+/*-
+ * Copyright (c) 2010 Adrian Chadd
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ */
+
+/* $FreeBSD: stable/10/sys/mips/atheros/ar71xx_setup.h 253027 2013-07-08 06:10:29Z adrian $ */
+
+#ifndef __AR71XX_SETUP_H__
+#define __AR71XX_SETUP_H__
+
+enum ar71xx_soc_type {
+ AR71XX_SOC_UNKNOWN,
+ AR71XX_SOC_AR7130,
+ AR71XX_SOC_AR7141,
+ AR71XX_SOC_AR7161,
+ AR71XX_SOC_AR7240,
+ AR71XX_SOC_AR7241,
+ AR71XX_SOC_AR7242,
+ AR71XX_SOC_AR9130,
+ AR71XX_SOC_AR9132,
+ AR71XX_SOC_AR9330,
+ AR71XX_SOC_AR9331,
+ AR71XX_SOC_AR9341,
+ AR71XX_SOC_AR9342,
+ AR71XX_SOC_AR9344,
+};
+extern enum ar71xx_soc_type ar71xx_soc;
+
+extern void ar71xx_detect_sys_type(void);
+extern const char *ar71xx_get_system_type(void);
+
+#endif
Property changes on: trunk/sys/mips/atheros/ar71xx_setup.h
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Added: trunk/sys/mips/atheros/ar71xx_spi.c
===================================================================
--- trunk/sys/mips/atheros/ar71xx_spi.c (rev 0)
+++ trunk/sys/mips/atheros/ar71xx_spi.c 2018-05-26 21:55:02 UTC (rev 9987)
@@ -0,0 +1,238 @@
+/* $MidnightBSD$ */
+/*-
+ * Copyright (c) 2009, Oleksandr Tymoshenko <gonzo at FreeBSD.org>
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice unmodified, this list of conditions, and the following
+ * disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ */
+
+#include <sys/cdefs.h>
+__FBSDID("$FreeBSD: stable/10/sys/mips/atheros/ar71xx_spi.c 265999 2014-05-14 01:35:43Z ian $");
+
+#include <sys/param.h>
+#include <sys/systm.h>
+
+#include <sys/bus.h>
+#include <sys/interrupt.h>
+#include <sys/malloc.h>
+#include <sys/kernel.h>
+#include <sys/module.h>
+#include <sys/rman.h>
+
+#include <vm/vm.h>
+#include <vm/pmap.h>
+#include <vm/vm_extern.h>
+
+#include <machine/bus.h>
+#include <machine/cpu.h>
+#include <machine/pmap.h>
+
+#include <dev/spibus/spi.h>
+#include <dev/spibus/spibusvar.h>
+#include "spibus_if.h"
+
+#include <mips/atheros/ar71xxreg.h>
+
+#undef AR71XX_SPI_DEBUG
+#ifdef AR71XX_SPI_DEBUG
+#define dprintf printf
+#else
+#define dprintf(x, arg...)
+#endif
+
+/*
+ * register space access macros
+ */
+#define SPI_WRITE(sc, reg, val) do { \
+ bus_write_4(sc->sc_mem_res, (reg), (val)); \
+ } while (0)
+
+#define SPI_READ(sc, reg) bus_read_4(sc->sc_mem_res, (reg))
+
+#define SPI_SET_BITS(sc, reg, bits) \
+ SPI_WRITE(sc, reg, SPI_READ(sc, (reg)) | (bits))
+
+#define SPI_CLEAR_BITS(sc, reg, bits) \
+ SPI_WRITE(sc, reg, SPI_READ(sc, (reg)) & ~(bits))
+
+struct ar71xx_spi_softc {
+ device_t sc_dev;
+ struct resource *sc_mem_res;
+ uint32_t sc_reg_ctrl;
+};
+
+static int
+ar71xx_spi_probe(device_t dev)
+{
+ device_set_desc(dev, "AR71XX SPI");
+ return (BUS_PROBE_NOWILDCARD);
+}
+
+static int
+ar71xx_spi_attach(device_t dev)
+{
+ struct ar71xx_spi_softc *sc = device_get_softc(dev);
+ int rid;
+
+ sc->sc_dev = dev;
+ rid = 0;
+ sc->sc_mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid,
+ RF_ACTIVE);
+ if (!sc->sc_mem_res) {
+ device_printf(dev, "Could not map memory\n");
+ return (ENXIO);
+ }
+
+
+ SPI_WRITE(sc, AR71XX_SPI_FS, 1);
+ sc->sc_reg_ctrl = SPI_READ(sc, AR71XX_SPI_CTRL);
+ SPI_WRITE(sc, AR71XX_SPI_CTRL, 0x43);
+ SPI_WRITE(sc, AR71XX_SPI_IO_CTRL, SPI_IO_CTRL_CSMASK);
+
+ device_add_child(dev, "spibus", -1);
+ return (bus_generic_attach(dev));
+}
+
+static void
+ar71xx_spi_chip_activate(struct ar71xx_spi_softc *sc, int cs)
+{
+ uint32_t ioctrl = SPI_IO_CTRL_CSMASK;
+ /*
+ * Put respective CSx to low
+ */
+ ioctrl &= ~(SPI_IO_CTRL_CS0 << cs);
+
+ SPI_WRITE(sc, AR71XX_SPI_IO_CTRL, ioctrl);
+}
+
+static void
+ar71xx_spi_chip_deactivate(struct ar71xx_spi_softc *sc, int cs)
+{
+ /*
+ * Put all CSx to high
+ */
+ SPI_WRITE(sc, AR71XX_SPI_IO_CTRL, SPI_IO_CTRL_CSMASK);
+}
+
+static uint8_t
+ar71xx_spi_txrx(struct ar71xx_spi_softc *sc, int cs, uint8_t data)
+{
+ int bit;
+ /* CS0 */
+ uint32_t ioctrl = SPI_IO_CTRL_CSMASK;
+ /*
+ * low-level for selected CS
+ */
+ ioctrl &= ~(SPI_IO_CTRL_CS0 << cs);
+
+ uint32_t iod, rds;
+ for (bit = 7; bit >=0; bit--) {
+ if (data & (1 << bit))
+ iod = ioctrl | SPI_IO_CTRL_DO;
+ else
+ iod = ioctrl & ~SPI_IO_CTRL_DO;
+ SPI_WRITE(sc, AR71XX_SPI_IO_CTRL, iod);
+ SPI_WRITE(sc, AR71XX_SPI_IO_CTRL, iod | SPI_IO_CTRL_CLK);
+ }
+
+ /*
+ * Provide falling edge for connected device by clear clock bit.
+ */
+ SPI_WRITE(sc, AR71XX_SPI_IO_CTRL, iod);
+ rds = SPI_READ(sc, AR71XX_SPI_RDS);
+
+ return (rds & 0xff);
+}
+
+static int
+ar71xx_spi_transfer(device_t dev, device_t child, struct spi_command *cmd)
+{
+ struct ar71xx_spi_softc *sc;
+ uint8_t *buf_in, *buf_out;
+ struct spibus_ivar *devi = SPIBUS_IVAR(child);
+ int i;
+
+ sc = device_get_softc(dev);
+
+ ar71xx_spi_chip_activate(sc, devi->cs);
+
+ KASSERT(cmd->tx_cmd_sz == cmd->rx_cmd_sz,
+ ("TX/RX command sizes should be equal"));
+ KASSERT(cmd->tx_data_sz == cmd->rx_data_sz,
+ ("TX/RX data sizes should be equal"));
+
+ /*
+ * Transfer command
+ */
+ buf_out = (uint8_t *)cmd->tx_cmd;
+ buf_in = (uint8_t *)cmd->rx_cmd;
+ for (i = 0; i < cmd->tx_cmd_sz; i++)
+ buf_in[i] = ar71xx_spi_txrx(sc, devi->cs, buf_out[i]);
+
+ /*
+ * Receive/transmit data (depends on command)
+ */
+ buf_out = (uint8_t *)cmd->tx_data;
+ buf_in = (uint8_t *)cmd->rx_data;
+ for (i = 0; i < cmd->tx_data_sz; i++)
+ buf_in[i] = ar71xx_spi_txrx(sc, devi->cs, buf_out[i]);
+
+ ar71xx_spi_chip_deactivate(sc, devi->cs);
+
+ return (0);
+}
+
+static int
+ar71xx_spi_detach(device_t dev)
+{
+ struct ar71xx_spi_softc *sc = device_get_softc(dev);
+
+ SPI_WRITE(sc, AR71XX_SPI_CTRL, sc->sc_reg_ctrl);
+ SPI_WRITE(sc, AR71XX_SPI_FS, 0);
+
+ if (sc->sc_mem_res)
+ bus_release_resource(dev, SYS_RES_MEMORY, 0, sc->sc_mem_res);
+
+ return (0);
+}
+
+static device_method_t ar71xx_spi_methods[] = {
+ /* Device interface */
+ DEVMETHOD(device_probe, ar71xx_spi_probe),
+ DEVMETHOD(device_attach, ar71xx_spi_attach),
+ DEVMETHOD(device_detach, ar71xx_spi_detach),
+
+ DEVMETHOD(spibus_transfer, ar71xx_spi_transfer),
+
+ {0, 0}
+};
+
+static driver_t ar71xx_spi_driver = {
+ "spi",
+ ar71xx_spi_methods,
+ sizeof(struct ar71xx_spi_softc),
+};
+
+static devclass_t ar71xx_spi_devclass;
+
+DRIVER_MODULE(ar71xx_spi, nexus, ar71xx_spi_driver, ar71xx_spi_devclass, 0, 0);
Property changes on: trunk/sys/mips/atheros/ar71xx_spi.c
___________________________________________________________________
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Added: trunk/sys/mips/atheros/ar71xx_wdog.c
===================================================================
--- trunk/sys/mips/atheros/ar71xx_wdog.c (rev 0)
+++ trunk/sys/mips/atheros/ar71xx_wdog.c 2018-05-26 21:55:02 UTC (rev 9987)
@@ -0,0 +1,157 @@
+/* $MidnightBSD$ */
+/*-
+ * Copyright (c) 2009, Oleksandr Tymoshenko <gonzo at FreeBSD.org>
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice unmodified, this list of conditions, and the following
+ * disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ */
+
+/*
+ * Watchdog driver for AR71xx
+ */
+
+#include <sys/cdefs.h>
+__FBSDID("$FreeBSD: stable/10/sys/mips/atheros/ar71xx_wdog.c 265999 2014-05-14 01:35:43Z ian $");
+
+#include <sys/param.h>
+#include <sys/systm.h>
+#include <sys/watchdog.h>
+#include <sys/bus.h>
+#include <sys/kernel.h>
+#include <sys/module.h>
+#include <sys/sysctl.h>
+
+#include <mips/atheros/ar71xxreg.h>
+#include <mips/atheros/ar71xx_cpudef.h>
+
+struct ar71xx_wdog_softc {
+ device_t dev;
+ int armed;
+ int reboot_from_watchdog;
+ int debug;
+};
+
+static void
+ar71xx_wdog_watchdog_fn(void *private, u_int cmd, int *error)
+{
+ struct ar71xx_wdog_softc *sc = private;
+ uint64_t timer_val;
+
+ cmd &= WD_INTERVAL;
+ if (sc->debug)
+ device_printf(sc->dev, "ar71xx_wdog_watchdog_fn: cmd: %x\n", cmd);
+ if (cmd > 0) {
+ timer_val = (uint64_t)(1ULL << cmd) * ar71xx_ahb_freq() /
+ 1000000000;
+ if (sc->debug)
+ device_printf(sc->dev, "ar71xx_wdog_watchdog_fn: programming timer: %jx\n", (uintmax_t) timer_val);
+ /*
+ * Load timer with large enough value to prevent spurious
+ * reset
+ */
+ ATH_WRITE_REG(AR71XX_RST_WDOG_TIMER,
+ ar71xx_ahb_freq() * 10);
+ ATH_WRITE_REG(AR71XX_RST_WDOG_CONTROL,
+ RST_WDOG_ACTION_RESET);
+ ATH_WRITE_REG(AR71XX_RST_WDOG_TIMER,
+ (timer_val & 0xffffffff));
+ sc->armed = 1;
+ *error = 0;
+ } else {
+ if (sc->debug)
+ device_printf(sc->dev, "ar71xx_wdog_watchdog_fn: disarming\n");
+ if (sc->armed) {
+ ATH_WRITE_REG(AR71XX_RST_WDOG_CONTROL,
+ RST_WDOG_ACTION_NOACTION);
+ sc->armed = 0;
+ }
+ }
+}
+
+static int
+ar71xx_wdog_probe(device_t dev)
+{
+
+ device_set_desc(dev, "Atheros AR71XX watchdog timer");
+ return (BUS_PROBE_NOWILDCARD);
+}
+
+static void
+ar71xx_wdog_sysctl(device_t dev)
+{
+ struct ar71xx_wdog_softc *sc = device_get_softc(dev);
+
+ struct sysctl_ctx_list *ctx = device_get_sysctl_ctx(sc->dev);
+ struct sysctl_oid *tree = device_get_sysctl_tree(sc->dev);
+
+ SYSCTL_ADD_INT(ctx, SYSCTL_CHILDREN(tree), OID_AUTO,
+ "debug", CTLFLAG_RW, &sc->debug, 0,
+ "enable watchdog debugging");
+ SYSCTL_ADD_INT(ctx, SYSCTL_CHILDREN(tree), OID_AUTO,
+ "armed", CTLFLAG_RD, &sc->armed, 0,
+ "whether the watchdog is armed");
+ SYSCTL_ADD_INT(ctx, SYSCTL_CHILDREN(tree), OID_AUTO,
+ "reboot_from_watchdog", CTLFLAG_RD, &sc->reboot_from_watchdog, 0,
+ "whether the system rebooted from the watchdog");
+}
+
+
+static int
+ar71xx_wdog_attach(device_t dev)
+{
+ struct ar71xx_wdog_softc *sc = device_get_softc(dev);
+
+ /* Initialise */
+ sc->reboot_from_watchdog = 0;
+ sc->armed = 0;
+ sc->debug = 0;
+
+ if (ATH_READ_REG(AR71XX_RST_WDOG_CONTROL) & RST_WDOG_LAST) {
+ device_printf (dev,
+ "Previous reset was due to watchdog timeout\n");
+ sc->reboot_from_watchdog = 1;
+ }
+
+ ATH_WRITE_REG(AR71XX_RST_WDOG_CONTROL, RST_WDOG_ACTION_NOACTION);
+
+ sc->dev = dev;
+ EVENTHANDLER_REGISTER(watchdog_list, ar71xx_wdog_watchdog_fn, sc, 0);
+ ar71xx_wdog_sysctl(dev);
+
+ return (0);
+}
+
+static device_method_t ar71xx_wdog_methods[] = {
+ DEVMETHOD(device_probe, ar71xx_wdog_probe),
+ DEVMETHOD(device_attach, ar71xx_wdog_attach),
+ {0, 0},
+};
+
+static driver_t ar71xx_wdog_driver = {
+ "ar71xx_wdog",
+ ar71xx_wdog_methods,
+ sizeof(struct ar71xx_wdog_softc),
+};
+static devclass_t ar71xx_wdog_devclass;
+
+DRIVER_MODULE(ar71xx_wdog, nexus, ar71xx_wdog_driver, ar71xx_wdog_devclass, 0, 0);
Property changes on: trunk/sys/mips/atheros/ar71xx_wdog.c
___________________________________________________________________
Added: svn:eol-style
## -0,0 +1 ##
+native
\ No newline at end of property
Added: svn:keywords
## -0,0 +1 ##
+MidnightBSD=%H
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Added: trunk/sys/mips/atheros/ar71xxreg.h
===================================================================
--- trunk/sys/mips/atheros/ar71xxreg.h (rev 0)
+++ trunk/sys/mips/atheros/ar71xxreg.h 2018-05-26 21:55:02 UTC (rev 9987)
@@ -0,0 +1,566 @@
+/* $MidnightBSD$ */
+/*-
+ * Copyright (c) 2009 Oleksandr Tymoshenko
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ */
+
+/* $FreeBSD: stable/10/sys/mips/atheros/ar71xxreg.h 261455 2014-02-04 03:36:42Z eadler $ */
+
+#ifndef _AR71XX_REG_H_
+#define _AR71XX_REG_H_
+
+/* PCI region */
+#define AR71XX_PCI_MEM_BASE 0x10000000
+/*
+ * PCI mem windows is 0x08000000 bytes long but we exclude control
+ * region from the resource manager
+ */
+#define AR71XX_PCI_MEM_SIZE 0x07000000
+#define AR71XX_PCI_IRQ_START 0
+#define AR71XX_PCI_IRQ_END 2
+#define AR71XX_PCI_NIRQS 3
+/*
+ * PCI devices slots are starting from this number
+ */
+#define AR71XX_PCI_BASE_SLOT 17
+
+/* PCI config registers */
+#define AR71XX_PCI_LCONF_CMD 0x17010000
+#define PCI_LCONF_CMD_READ 0x00000000
+#define PCI_LCONF_CMD_WRITE 0x00010000
+#define AR71XX_PCI_LCONF_WRITE_DATA 0x17010004
+#define AR71XX_PCI_LCONF_READ_DATA 0x17010008
+#define AR71XX_PCI_CONF_ADDR 0x1701000C
+#define AR71XX_PCI_CONF_CMD 0x17010010
+#define PCI_CONF_CMD_READ 0x0000000A
+#define PCI_CONF_CMD_WRITE 0x0000000B
+#define AR71XX_PCI_CONF_WRITE_DATA 0x17010014
+#define AR71XX_PCI_CONF_READ_DATA 0x17010018
+#define AR71XX_PCI_ERROR 0x1701001C
+#define AR71XX_PCI_ERROR_ADDR 0x17010020
+#define AR71XX_PCI_AHB_ERROR 0x17010024
+#define AR71XX_PCI_AHB_ERROR_ADDR 0x17010028
+
+/* APB region */
+/*
+ * Size is not really true actual APB window size is
+ * 0x01000000 but it should handle OHCI memory as well
+ * because this controller's interrupt is routed through
+ * APB.
+ */
+#define AR71XX_APB_BASE 0x18000000
+#define AR71XX_APB_SIZE 0x06000000
+
+/* DDR registers */
+#define AR71XX_DDR_CONFIG 0x18000000
+#define AR71XX_DDR_CONFIG2 0x18000004
+#define AR71XX_DDR_MODE_REGISTER 0x18000008
+#define AR71XX_DDR_EXT_MODE_REGISTER 0x1800000C
+#define AR71XX_DDR_CONTROL 0x18000010
+#define AR71XX_DDR_REFRESH 0x18000014
+#define AR71XX_DDR_RD_DATA_THIS_CYCLE 0x18000018
+#define AR71XX_TAP_CONTROL0 0x1800001C
+#define AR71XX_TAP_CONTROL1 0x18000020
+#define AR71XX_TAP_CONTROL2 0x18000024
+#define AR71XX_TAP_CONTROL3 0x18000028
+#define AR71XX_PCI_WINDOW0 0x1800007C
+#define AR71XX_PCI_WINDOW1 0x18000080
+#define AR71XX_PCI_WINDOW2 0x18000084
+#define AR71XX_PCI_WINDOW3 0x18000088
+#define AR71XX_PCI_WINDOW4 0x1800008C
+#define AR71XX_PCI_WINDOW5 0x18000090
+#define AR71XX_PCI_WINDOW6 0x18000094
+#define AR71XX_PCI_WINDOW7 0x18000098
+#define AR71XX_WB_FLUSH_GE0 0x1800009C
+#define AR71XX_WB_FLUSH_GE1 0x180000A0
+#define AR71XX_WB_FLUSH_USB 0x180000A4
+#define AR71XX_WB_FLUSH_PCI 0x180000A8
+
+/*
+ * Values for PCI_WINDOW_X registers
+ */
+#define PCI_WINDOW0_ADDR 0x10000000
+#define PCI_WINDOW1_ADDR 0x11000000
+#define PCI_WINDOW2_ADDR 0x12000000
+#define PCI_WINDOW3_ADDR 0x13000000
+#define PCI_WINDOW4_ADDR 0x14000000
+#define PCI_WINDOW5_ADDR 0x15000000
+#define PCI_WINDOW6_ADDR 0x16000000
+#define PCI_WINDOW7_ADDR 0x17000000
+/* This value enables acces to PCI config registers */
+#define PCI_WINDOW7_CONF_ADDR 0x07000000
+
+#define AR71XX_UART_ADDR 0x18020000
+
+#define AR71XX_USB_CTRL_FLADJ 0x18030000
+#define USB_CTRL_FLADJ_HOST_SHIFT 12
+#define USB_CTRL_FLADJ_A5_SHIFT 10
+#define USB_CTRL_FLADJ_A4_SHIFT 8
+#define USB_CTRL_FLADJ_A3_SHIFT 6
+#define USB_CTRL_FLADJ_A2_SHIFT 4
+#define USB_CTRL_FLADJ_A1_SHIFT 2
+#define USB_CTRL_FLADJ_A0_SHIFT 0
+#define AR71XX_USB_CTRL_CONFIG 0x18030004
+#define USB_CTRL_CONFIG_OHCI_DES_SWAP (1 << 19)
+#define USB_CTRL_CONFIG_OHCI_BUF_SWAP (1 << 18)
+#define USB_CTRL_CONFIG_EHCI_DES_SWAP (1 << 17)
+#define USB_CTRL_CONFIG_EHCI_BUF_SWAP (1 << 16)
+#define USB_CTRL_CONFIG_DISABLE_XTL (1 << 13)
+#define USB_CTRL_CONFIG_OVERRIDE_XTL (1 << 12)
+#define USB_CTRL_CONFIG_CLK_SEL_SHIFT 4
+#define USB_CTRL_CONFIG_CLK_SEL_MASK 3
+#define USB_CTRL_CONFIG_CLK_SEL_12 0
+#define USB_CTRL_CONFIG_CLK_SEL_24 1
+#define USB_CTRL_CONFIG_CLK_SEL_48 2
+#define USB_CTRL_CONFIG_OVER_CURRENT_AS_GPIO (1 << 8)
+#define USB_CTRL_CONFIG_SS_SIMULATION_MODE (1 << 2)
+#define USB_CTRL_CONFIG_RESUME_UTMI_PLS_DIS (1 << 1)
+#define USB_CTRL_CONFIG_UTMI_BACKWARD_ENB (1 << 0)
+
+#define AR71XX_GPIO_BASE 0x18040000
+#define AR71XX_GPIO_OE 0x00
+#define AR71XX_GPIO_IN 0x04
+#define AR71XX_GPIO_OUT 0x08
+#define AR71XX_GPIO_SET 0x0c
+#define AR71XX_GPIO_CLEAR 0x10
+#define AR71XX_GPIO_INT 0x14
+#define AR71XX_GPIO_INT_TYPE 0x18
+#define AR71XX_GPIO_INT_POLARITY 0x1c
+#define AR71XX_GPIO_INT_PENDING 0x20
+#define AR71XX_GPIO_INT_MASK 0x24
+#define AR71XX_GPIO_FUNCTION 0x28
+#define GPIO_FUNC_STEREO_EN (1 << 17)
+#define GPIO_FUNC_SLIC_EN (1 << 16)
+#define GPIO_FUNC_SPI_CS2_EN (1 << 13)
+ /* CS2 is shared with GPIO_1 */
+#define GPIO_FUNC_SPI_CS1_EN (1 << 12)
+ /* CS1 is shared with GPIO_0 */
+#define GPIO_FUNC_UART_EN (1 << 8)
+#define GPIO_FUNC_USB_OC_EN (1 << 4)
+#define GPIO_FUNC_USB_CLK_EN (0)
+
+#define AR71XX_BASE_FREQ 40000000
+#define AR71XX_PLL_CPU_BASE 0x18050000
+#define AR71XX_PLL_CPU_CONFIG 0x18050000
+#define PLL_SW_UPDATE (1U << 31)
+#define PLL_LOCKED (1 << 30)
+#define PLL_AHB_DIV_SHIFT 20
+#define PLL_AHB_DIV_MASK 7
+#define PLL_DDR_DIV_SEL_SHIFT 18
+#define PLL_DDR_DIV_SEL_MASK 3
+#define PLL_CPU_DIV_SEL_SHIFT 16
+#define PLL_CPU_DIV_SEL_MASK 3
+#define PLL_LOOP_BW_SHIFT 12
+#define PLL_LOOP_BW_MASK 0xf
+#define PLL_DIV_IN_SHIFT 10
+#define PLL_DIV_IN_MASK 3
+#define PLL_DIV_OUT_SHIFT 8
+#define PLL_DIV_OUT_MASK 3
+#define PLL_FB_SHIFT 3
+#define PLL_FB_MASK 0x1f
+#define PLL_BYPASS (1 << 1)
+#define PLL_POWER_DOWN (1 << 0)
+#define AR71XX_PLL_SEC_CONFIG 0x18050004
+#define AR71XX_PLL_ETH0_SHIFT 17
+#define AR71XX_PLL_ETH1_SHIFT 19
+#define AR71XX_PLL_CPU_CLK_CTRL 0x18050008
+#define AR71XX_PLL_ETH_INT0_CLK 0x18050010
+#define AR71XX_PLL_ETH_INT1_CLK 0x18050014
+#define XPLL_ETH_INT_CLK_10 0x00991099
+#define XPLL_ETH_INT_CLK_100 0x00441011
+#define XPLL_ETH_INT_CLK_1000 0x13110000
+#define XPLL_ETH_INT_CLK_1000_GMII 0x14110000
+#define PLL_ETH_INT_CLK_10 0x00991099
+#define PLL_ETH_INT_CLK_100 0x00001099
+#define PLL_ETH_INT_CLK_1000 0x00110000
+#define AR71XX_PLL_ETH_EXT_CLK 0x18050018
+#define AR71XX_PLL_PCI_CLK 0x1805001C
+
+/* Reset block */
+#define AR71XX_RST_BLOCK_BASE 0x18060000
+
+#define AR71XX_RST_WDOG_CONTROL 0x18060008
+#define RST_WDOG_LAST (1U << 31)
+#define RST_WDOG_ACTION_MASK 3
+#define RST_WDOG_ACTION_RESET 3
+#define RST_WDOG_ACTION_NMI 2
+#define RST_WDOG_ACTION_GP_INTR 1
+#define RST_WDOG_ACTION_NOACTION 0
+
+#define AR71XX_RST_WDOG_TIMER 0x1806000C
+/*
+ * APB interrupt status and mask register and interrupt bit numbers for
+ */
+#define AR71XX_MISC_INTR_STATUS 0x18060010
+#define AR71XX_MISC_INTR_MASK 0x18060014
+#define MISC_INTR_TIMER 0
+#define MISC_INTR_ERROR 1
+#define MISC_INTR_GPIO 2
+#define MISC_INTR_UART 3
+#define MISC_INTR_WATCHDOG 4
+#define MISC_INTR_PERF 5
+#define MISC_INTR_OHCI 6
+#define MISC_INTR_DMA 7
+
+#define AR71XX_PCI_INTR_STATUS 0x18060018
+#define AR71XX_PCI_INTR_MASK 0x1806001C
+#define PCI_INTR_CORE (1 << 4)
+
+#define AR71XX_RST_RESET 0x18060024
+#define RST_RESET_FULL_CHIP (1 << 24) /* Same as pulling
+ the reset pin */
+#define RST_RESET_CPU_COLD (1 << 20) /* Cold reset */
+#define RST_RESET_GE1_MAC (1 << 13)
+#define RST_RESET_GE1_PHY (1 << 12)
+#define RST_RESET_GE0_MAC (1 << 9)
+#define RST_RESET_GE0_PHY (1 << 8)
+#define RST_RESET_USB_OHCI_DLL (1 << 6)
+#define RST_RESET_USB_HOST (1 << 5)
+#define RST_RESET_USB_PHY (1 << 4)
+#define RST_RESET_PCI_BUS (1 << 1)
+#define RST_RESET_PCI_CORE (1 << 0)
+
+/* Chipset revision details */
+#define AR71XX_RST_RESET_REG_REV_ID 0x18060090
+#define REV_ID_MAJOR_MASK 0xfff0
+#define REV_ID_MAJOR_AR71XX 0x00a0
+#define REV_ID_MAJOR_AR913X 0x00b0
+#define REV_ID_MAJOR_AR7240 0x00c0
+#define REV_ID_MAJOR_AR7241 0x0100
+#define REV_ID_MAJOR_AR7242 0x1100
+
+/* AR71XX chipset revision details */
+#define AR71XX_REV_ID_MINOR_MASK 0x3
+#define AR71XX_REV_ID_MINOR_AR7130 0x0
+#define AR71XX_REV_ID_MINOR_AR7141 0x1
+#define AR71XX_REV_ID_MINOR_AR7161 0x2
+#define AR71XX_REV_ID_REVISION_MASK 0x3
+#define AR71XX_REV_ID_REVISION_SHIFT 2
+
+/* AR724X chipset revision details */
+#define AR724X_REV_ID_REVISION_MASK 0x3
+
+/* AR91XX chipset revision details */
+#define AR91XX_REV_ID_MINOR_MASK 0x3
+#define AR91XX_REV_ID_MINOR_AR9130 0x0
+#define AR91XX_REV_ID_MINOR_AR9132 0x1
+#define AR91XX_REV_ID_REVISION_MASK 0x3
+#define AR91XX_REV_ID_REVISION_SHIFT 2
+
+typedef enum {
+ AR71XX_MII_MODE_NONE = 0,
+ AR71XX_MII_MODE_GMII,
+ AR71XX_MII_MODE_MII,
+ AR71XX_MII_MODE_RGMII,
+ AR71XX_MII_MODE_RMII,
+} ar71xx_mii_mode;
+
+/*
+ * AR71xx MII control region
+ */
+#define AR71XX_MII0_CTRL 0x18070000
+#define MII_CTRL_SPEED_SHIFT 4
+#define MII_CTRL_SPEED_MASK 3
+#define MII_CTRL_SPEED_10 0
+#define MII_CTRL_SPEED_100 1
+#define MII_CTRL_SPEED_1000 2
+#define MII_CTRL_IF_MASK 3
+#define MII_CTRL_IF_SHIFT 0
+#define MII0_CTRL_IF_GMII 0
+#define MII0_CTRL_IF_MII 1
+#define MII0_CTRL_IF_RGMII 2
+#define MII0_CTRL_IF_RMII 3
+
+#define AR71XX_MII1_CTRL 0x18070004
+
+#define MII1_CTRL_IF_RGMII 0
+#define MII1_CTRL_IF_RMII 1
+
+/*
+ * GigE adapters region
+ */
+#define AR71XX_MAC0_BASE 0x19000000
+#define AR71XX_MAC1_BASE 0x1A000000
+
+#define AR71XX_MAC_CFG1 0x00
+#define MAC_CFG1_SOFT_RESET (1U << 31)
+#define MAC_CFG1_SIMUL_RESET (1 << 30)
+#define MAC_CFG1_MAC_RX_BLOCK_RESET (1 << 19)
+#define MAC_CFG1_MAC_TX_BLOCK_RESET (1 << 18)
+#define MAC_CFG1_RX_FUNC_RESET (1 << 17)
+#define MAC_CFG1_TX_FUNC_RESET (1 << 16)
+#define MAC_CFG1_LOOPBACK (1 << 8)
+#define MAC_CFG1_RXFLOW_CTRL (1 << 5)
+#define MAC_CFG1_TXFLOW_CTRL (1 << 4)
+#define MAC_CFG1_SYNC_RX (1 << 3)
+#define MAC_CFG1_RX_ENABLE (1 << 2)
+#define MAC_CFG1_SYNC_TX (1 << 1)
+#define MAC_CFG1_TX_ENABLE (1 << 0)
+#define AR71XX_MAC_CFG2 0x04
+#define MAC_CFG2_PREAMBLE_LEN_MASK 0xf
+#define MAC_CFG2_PREAMBLE_LEN_SHIFT 12
+#define MAC_CFG2_IFACE_MODE_1000 (2 << 8)
+#define MAC_CFG2_IFACE_MODE_10_100 (1 << 8)
+#define MAC_CFG2_IFACE_MODE_SHIFT 8
+#define MAC_CFG2_IFACE_MODE_MASK 3
+#define MAC_CFG2_HUGE_FRAME (1 << 5)
+#define MAC_CFG2_LENGTH_FIELD (1 << 4)
+#define MAC_CFG2_ENABLE_PADCRC (1 << 2)
+#define MAC_CFG2_ENABLE_CRC (1 << 1)
+#define MAC_CFG2_FULL_DUPLEX (1 << 0)
+#define AR71XX_MAC_IFG 0x08
+#define AR71XX_MAC_HDUPLEX 0x0C
+#define AR71XX_MAC_MAX_FRAME_LEN 0x10
+#define AR71XX_MAC_MII_CFG 0x20
+#define MAC_MII_CFG_RESET (1U << 31)
+#define MAC_MII_CFG_SCAN_AUTO_INC (1 << 5)
+#define MAC_MII_CFG_PREAMBLE_SUP (1 << 4)
+#define MAC_MII_CFG_CLOCK_SELECT_MASK 0x7
+#define MAC_MII_CFG_CLOCK_SELECT_MASK_AR933X 0xf
+#define MAC_MII_CFG_CLOCK_DIV_4 0
+#define MAC_MII_CFG_CLOCK_DIV_6 2
+#define MAC_MII_CFG_CLOCK_DIV_8 3
+#define MAC_MII_CFG_CLOCK_DIV_10 4
+#define MAC_MII_CFG_CLOCK_DIV_14 5
+#define MAC_MII_CFG_CLOCK_DIV_20 6
+#define MAC_MII_CFG_CLOCK_DIV_28 7
+
+/* .. and the AR933x/AR934x extensions */
+#define MAC_MII_CFG_CLOCK_DIV_34 8
+#define MAC_MII_CFG_CLOCK_DIV_42 9
+#define MAC_MII_CFG_CLOCK_DIV_50 10
+#define MAC_MII_CFG_CLOCK_DIV_58 11
+#define MAC_MII_CFG_CLOCK_DIV_66 12
+#define MAC_MII_CFG_CLOCK_DIV_74 13
+#define MAC_MII_CFG_CLOCK_DIV_82 14
+#define MAC_MII_CFG_CLOCK_DIV_98 15
+
+#define AR71XX_MAC_MII_CMD 0x24
+#define MAC_MII_CMD_SCAN_CYCLE (1 << 1)
+#define MAC_MII_CMD_READ 1
+#define MAC_MII_CMD_WRITE 0
+#define AR71XX_MAC_MII_ADDR 0x28
+#define MAC_MII_PHY_ADDR_SHIFT 8
+#define MAC_MII_PHY_ADDR_MASK 0xff
+#define MAC_MII_REG_MASK 0x1f
+#define AR71XX_MAC_MII_CONTROL 0x2C
+#define MAC_MII_CONTROL_MASK 0xffff
+#define AR71XX_MAC_MII_STATUS 0x30
+#define MAC_MII_STATUS_MASK 0xffff
+#define AR71XX_MAC_MII_INDICATOR 0x34
+#define MAC_MII_INDICATOR_NOT_VALID (1 << 2)
+#define MAC_MII_INDICATOR_SCANNING (1 << 1)
+#define MAC_MII_INDICATOR_BUSY (1 << 0)
+#define AR71XX_MAC_IFCONTROL 0x38
+#define MAC_IFCONTROL_SPEED (1 << 16)
+#define AR71XX_MAC_STA_ADDR1 0x40
+#define AR71XX_MAC_STA_ADDR2 0x44
+#define AR71XX_MAC_FIFO_CFG0 0x48
+#define FIFO_CFG0_TX_FABRIC (1 << 4)
+#define FIFO_CFG0_TX_SYSTEM (1 << 3)
+#define FIFO_CFG0_RX_FABRIC (1 << 2)
+#define FIFO_CFG0_RX_SYSTEM (1 << 1)
+#define FIFO_CFG0_WATERMARK (1 << 0)
+#define FIFO_CFG0_ALL ((1 << 5) - 1)
+#define FIFO_CFG0_ENABLE_SHIFT 8
+#define AR71XX_MAC_FIFO_CFG1 0x4C
+#define AR71XX_MAC_FIFO_CFG2 0x50
+#define AR71XX_MAC_FIFO_TX_THRESHOLD 0x54
+#define AR71XX_MAC_FIFO_RX_FILTMATCH 0x58
+/*
+ * These flags applicable both to AR71XX_MAC_FIFO_RX_FILTMASK and
+ * to AR71XX_MAC_FIFO_RX_FILTMATCH
+ */
+#define FIFO_RX_MATCH_UNICAST (1 << 17)
+#define FIFO_RX_MATCH_TRUNC_FRAME (1 << 16)
+#define FIFO_RX_MATCH_VLAN_TAG (1 << 15)
+#define FIFO_RX_MATCH_UNSUP_OPCODE (1 << 14)
+#define FIFO_RX_MATCH_PAUSE_FRAME (1 << 13)
+#define FIFO_RX_MATCH_CTRL_FRAME (1 << 12)
+#define FIFO_RX_MATCH_LONG_EVENT (1 << 11)
+#define FIFO_RX_MATCH_DRIBBLE_NIBBLE (1 << 10)
+#define FIFO_RX_MATCH_BCAST (1 << 9)
+#define FIFO_RX_MATCH_MCAST (1 << 8)
+#define FIFO_RX_MATCH_OK (1 << 7)
+#define FIFO_RX_MATCH_OORANGE (1 << 6)
+#define FIFO_RX_MATCH_LEN_MSMTCH (1 << 5)
+#define FIFO_RX_MATCH_CRC_ERROR (1 << 4)
+#define FIFO_RX_MATCH_CODE_ERROR (1 << 3)
+#define FIFO_RX_MATCH_FALSE_CARRIER (1 << 2)
+#define FIFO_RX_MATCH_RX_DV_EVENT (1 << 1)
+#define FIFO_RX_MATCH_DROP_EVENT (1 << 0)
+/*
+ * Exclude unicast and truncated frames from matching
+ */
+#define FIFO_RX_FILTMATCH_DEFAULT \
+ (FIFO_RX_MATCH_VLAN_TAG | \
+ FIFO_RX_MATCH_UNSUP_OPCODE | \
+ FIFO_RX_MATCH_PAUSE_FRAME | \
+ FIFO_RX_MATCH_CTRL_FRAME | \
+ FIFO_RX_MATCH_LONG_EVENT | \
+ FIFO_RX_MATCH_DRIBBLE_NIBBLE | \
+ FIFO_RX_MATCH_BCAST | \
+ FIFO_RX_MATCH_MCAST | \
+ FIFO_RX_MATCH_OK | \
+ FIFO_RX_MATCH_OORANGE | \
+ FIFO_RX_MATCH_LEN_MSMTCH | \
+ FIFO_RX_MATCH_CRC_ERROR | \
+ FIFO_RX_MATCH_CODE_ERROR | \
+ FIFO_RX_MATCH_FALSE_CARRIER | \
+ FIFO_RX_MATCH_RX_DV_EVENT | \
+ FIFO_RX_MATCH_DROP_EVENT)
+#define AR71XX_MAC_FIFO_RX_FILTMASK 0x5C
+#define FIFO_RX_MASK_BYTE_MODE (1 << 19)
+#define FIFO_RX_MASK_NO_SHORT_FRAME (1 << 18)
+#define FIFO_RX_MASK_BIT17 (1 << 17)
+#define FIFO_RX_MASK_BIT16 (1 << 16)
+#define FIFO_RX_MASK_TRUNC_FRAME (1 << 15)
+#define FIFO_RX_MASK_LONG_EVENT (1 << 14)
+#define FIFO_RX_MASK_VLAN_TAG (1 << 13)
+#define FIFO_RX_MASK_UNSUP_OPCODE (1 << 12)
+#define FIFO_RX_MASK_PAUSE_FRAME (1 << 11)
+#define FIFO_RX_MASK_CTRL_FRAME (1 << 10)
+#define FIFO_RX_MASK_DRIBBLE_NIBBLE (1 << 9)
+#define FIFO_RX_MASK_BCAST (1 << 8)
+#define FIFO_RX_MASK_MCAST (1 << 7)
+#define FIFO_RX_MASK_OK (1 << 6)
+#define FIFO_RX_MASK_OORANGE (1 << 5)
+#define FIFO_RX_MASK_LEN_MSMTCH (1 << 4)
+#define FIFO_RX_MASK_CODE_ERROR (1 << 3)
+#define FIFO_RX_MASK_FALSE_CARRIER (1 << 2)
+#define FIFO_RX_MASK_RX_DV_EVENT (1 << 1)
+#define FIFO_RX_MASK_DROP_EVENT (1 << 0)
+
+/*
+ * Len. mismatch, unsup. opcode and short frmae bits excluded
+ */
+#define FIFO_RX_FILTMASK_DEFAULT \
+ (FIFO_RX_MASK_NO_SHORT_FRAME | \
+ FIFO_RX_MASK_BIT17 | \
+ FIFO_RX_MASK_BIT16 | \
+ FIFO_RX_MASK_TRUNC_FRAME | \
+ FIFO_RX_MASK_LONG_EVENT | \
+ FIFO_RX_MASK_VLAN_TAG | \
+ FIFO_RX_MASK_PAUSE_FRAME | \
+ FIFO_RX_MASK_CTRL_FRAME | \
+ FIFO_RX_MASK_DRIBBLE_NIBBLE | \
+ FIFO_RX_MASK_BCAST | \
+ FIFO_RX_MASK_MCAST | \
+ FIFO_RX_MASK_OK | \
+ FIFO_RX_MASK_OORANGE | \
+ FIFO_RX_MASK_CODE_ERROR | \
+ FIFO_RX_MASK_FALSE_CARRIER | \
+ FIFO_RX_MASK_RX_DV_EVENT | \
+ FIFO_RX_MASK_DROP_EVENT)
+
+#define AR71XX_MAC_FIFO_RAM0 0x60
+#define AR71XX_MAC_FIFO_RAM1 0x64
+#define AR71XX_MAC_FIFO_RAM2 0x68
+#define AR71XX_MAC_FIFO_RAM3 0x6C
+#define AR71XX_MAC_FIFO_RAM4 0x70
+#define AR71XX_MAC_FIFO_RAM5 0x74
+#define AR71XX_MAC_FIFO_RAM6 0x78
+#define AR71XX_DMA_TX_CONTROL 0x180
+#define DMA_TX_CONTROL_EN (1 << 0)
+#define AR71XX_DMA_TX_DESC 0x184
+#define AR71XX_DMA_TX_STATUS 0x188
+#define DMA_TX_STATUS_PCOUNT_MASK 0xff
+#define DMA_TX_STATUS_PCOUNT_SHIFT 16
+#define DMA_TX_STATUS_BUS_ERROR (1 << 3)
+#define DMA_TX_STATUS_UNDERRUN (1 << 1)
+#define DMA_TX_STATUS_PKT_SENT (1 << 0)
+#define AR71XX_DMA_RX_CONTROL 0x18C
+#define DMA_RX_CONTROL_EN (1 << 0)
+#define AR71XX_DMA_RX_DESC 0x190
+#define AR71XX_DMA_RX_STATUS 0x194
+#define DMA_RX_STATUS_PCOUNT_MASK 0xff
+#define DMA_RX_STATUS_PCOUNT_SHIFT 16
+#define DMA_RX_STATUS_BUS_ERROR (1 << 3)
+#define DMA_RX_STATUS_OVERFLOW (1 << 2)
+#define DMA_RX_STATUS_PKT_RECVD (1 << 0)
+#define AR71XX_DMA_INTR 0x198
+#define AR71XX_DMA_INTR_STATUS 0x19C
+#define DMA_INTR_ALL ((1 << 8) - 1)
+#define DMA_INTR_RX_BUS_ERROR (1 << 7)
+#define DMA_INTR_RX_OVERFLOW (1 << 6)
+#define DMA_INTR_RX_PKT_RCVD (1 << 4)
+#define DMA_INTR_TX_BUS_ERROR (1 << 3)
+#define DMA_INTR_TX_UNDERRUN (1 << 1)
+#define DMA_INTR_TX_PKT_SENT (1 << 0)
+
+#define AR71XX_SPI_BASE 0x1f000000
+#define AR71XX_SPI_FS 0x00
+#define AR71XX_SPI_CTRL 0x04
+#define SPI_CTRL_REMAP_DISABLE (1 << 6)
+#define SPI_CTRL_CLOCK_DIVIDER_MASK ((1 << 6) - 1)
+#define AR71XX_SPI_IO_CTRL 0x08
+#define SPI_IO_CTRL_CS2 (1 << 18)
+#define SPI_IO_CTRL_CS1 (1 << 17)
+#define SPI_IO_CTRL_CS0 (1 << 16)
+#define SPI_IO_CTRL_CSMASK (7 << 16)
+#define SPI_IO_CTRL_CLK (1 << 8)
+#define SPI_IO_CTRL_DO 1
+#define AR71XX_SPI_RDS 0x0C
+
+#define ATH_READ_REG(reg) \
+ *((volatile uint32_t *)MIPS_PHYS_TO_KSEG1((reg)))
+
+#define ATH_WRITE_REG(reg, val) \
+ *((volatile uint32_t *)MIPS_PHYS_TO_KSEG1((reg))) = (val)
+
+static inline void
+ar71xx_ddr_flush(uint32_t reg)
+{
+ ATH_WRITE_REG(reg, 1);
+ while ((ATH_READ_REG(reg) & 0x1))
+ ;
+ ATH_WRITE_REG(reg, 1);
+ while ((ATH_READ_REG(reg) & 0x1))
+ ;
+}
+
+static inline void
+ar71xx_write_pll(uint32_t cfg_reg, uint32_t pll_reg, uint32_t pll, uint32_t pll_reg_shift)
+{
+ uint32_t sec_cfg;
+
+ /* set PLL registers */
+ sec_cfg = ATH_READ_REG(cfg_reg);
+ sec_cfg &= ~(3 << pll_reg_shift);
+ sec_cfg |= (2 << pll_reg_shift);
+
+ ATH_WRITE_REG(cfg_reg, sec_cfg);
+ DELAY(100);
+
+ ATH_WRITE_REG(pll_reg, pll);
+ sec_cfg |= (3 << pll_reg_shift);
+ ATH_WRITE_REG(cfg_reg, sec_cfg);
+ DELAY(100);
+
+ sec_cfg &= ~(3 << pll_reg_shift);
+ ATH_WRITE_REG(cfg_reg, sec_cfg);
+ DELAY(100);
+}
+
+#endif /* _AR71XX_REG_H_ */
Property changes on: trunk/sys/mips/atheros/ar71xxreg.h
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Added: trunk/sys/mips/atheros/ar724x_chip.c
===================================================================
--- trunk/sys/mips/atheros/ar724x_chip.c (rev 0)
+++ trunk/sys/mips/atheros/ar724x_chip.c 2018-05-26 21:55:02 UTC (rev 9987)
@@ -0,0 +1,250 @@
+/* $MidnightBSD$ */
+/*-
+ * Copyright (c) 2010 Adrian Chadd
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ */
+
+#include <sys/cdefs.h>
+__FBSDID("$FreeBSD: stable/10/sys/mips/atheros/ar724x_chip.c 253508 2013-07-21 03:52:52Z adrian $");
+
+#include "opt_ddb.h"
+
+#include <sys/param.h>
+#include <sys/conf.h>
+#include <sys/kernel.h>
+#include <sys/systm.h>
+#include <sys/bus.h>
+#include <sys/cons.h>
+#include <sys/kdb.h>
+#include <sys/reboot.h>
+
+#include <vm/vm.h>
+#include <vm/vm_page.h>
+
+#include <net/ethernet.h>
+
+#include <machine/clock.h>
+#include <machine/cpu.h>
+#include <machine/cpuregs.h>
+#include <machine/hwfunc.h>
+#include <machine/md_var.h>
+#include <machine/trap.h>
+#include <machine/vmparam.h>
+
+#include <mips/atheros/ar71xxreg.h>
+#include <mips/atheros/ar724xreg.h>
+
+#include <mips/atheros/ar71xx_cpudef.h>
+#include <mips/atheros/ar71xx_setup.h>
+#include <mips/atheros/ar71xx_chip.h>
+#include <mips/atheros/ar724x_chip.h>
+
+#include <mips/sentry5/s5reg.h>
+
+static void
+ar724x_chip_detect_mem_size(void)
+{
+}
+
+static void
+ar724x_chip_detect_sys_frequency(void)
+{
+ uint32_t pll;
+ uint32_t freq;
+ uint32_t div;
+
+ u_ar71xx_refclk = AR724X_BASE_FREQ;
+
+ pll = ATH_READ_REG(AR724X_PLL_REG_CPU_CONFIG);
+
+ div = ((pll >> AR724X_PLL_DIV_SHIFT) & AR724X_PLL_DIV_MASK);
+ freq = div * AR724X_BASE_FREQ;
+
+ div = ((pll >> AR724X_PLL_REF_DIV_SHIFT) & AR724X_PLL_REF_DIV_MASK);
+ freq *= div;
+
+ u_ar71xx_cpu_freq = freq;
+
+ div = ((pll >> AR724X_DDR_DIV_SHIFT) & AR724X_DDR_DIV_MASK) + 1;
+ u_ar71xx_ddr_freq = freq / div;
+
+ div = (((pll >> AR724X_AHB_DIV_SHIFT) & AR724X_AHB_DIV_MASK) + 1) * 2;
+ u_ar71xx_ahb_freq = u_ar71xx_cpu_freq / div;
+ u_ar71xx_wdt_freq = u_ar71xx_cpu_freq / div;
+ u_ar71xx_uart_freq = u_ar71xx_cpu_freq / div;
+}
+
+static void
+ar724x_chip_device_stop(uint32_t mask)
+{
+ uint32_t mask_inv, reg;
+
+ mask_inv = mask & AR724X_RESET_MODULE_USB_OHCI_DLL;
+ reg = ATH_READ_REG(AR724X_RESET_REG_RESET_MODULE);
+ reg |= mask;
+ reg &= ~mask_inv;
+ ATH_WRITE_REG(AR724X_RESET_REG_RESET_MODULE, reg);
+}
+
+static void
+ar724x_chip_device_start(uint32_t mask)
+{
+ uint32_t mask_inv, reg;
+
+ mask_inv = mask & AR724X_RESET_MODULE_USB_OHCI_DLL;
+ reg = ATH_READ_REG(AR724X_RESET_REG_RESET_MODULE);
+ reg &= ~mask;
+ reg |= mask_inv;
+ ATH_WRITE_REG(AR724X_RESET_REG_RESET_MODULE, reg);
+}
+
+static int
+ar724x_chip_device_stopped(uint32_t mask)
+{
+ uint32_t reg;
+
+ reg = ATH_READ_REG(AR724X_RESET_REG_RESET_MODULE);
+ return ((reg & mask) == mask);
+}
+
+static void
+ar724x_chip_set_mii_speed(uint32_t unit, uint32_t speed)
+{
+
+ /* XXX TODO */
+ return;
+}
+
+/*
+ * XXX TODO: set the PLL for arge0 only on AR7242.
+ * The PLL/clock requirements are different.
+ *
+ * Otherwise, it's a NULL function for AR7240, AR7241 and
+ * AR7242 arge1.
+ */
+static void
+ar724x_chip_set_pll_ge(int unit, int speed, uint32_t pll)
+{
+
+ switch (unit) {
+ case 0:
+ /* XXX TODO */
+ break;
+ case 1:
+ /* XXX TODO */
+ break;
+ default:
+ printf("%s: invalid PLL set for arge unit: %d\n",
+ __func__, unit);
+ return;
+ }
+}
+
+static void
+ar724x_chip_ddr_flush_ge(int unit)
+{
+
+ switch (unit) {
+ case 0:
+ ar71xx_ddr_flush(AR724X_DDR_REG_FLUSH_GE0);
+ break;
+ case 1:
+ ar71xx_ddr_flush(AR724X_DDR_REG_FLUSH_GE1);
+ break;
+ default:
+ printf("%s: invalid DDR flush for arge unit: %d\n",
+ __func__, unit);
+ return;
+ }
+}
+
+static void
+ar724x_chip_ddr_flush_ip2(void)
+{
+
+ ar71xx_ddr_flush(AR724X_DDR_REG_FLUSH_PCIE);
+}
+
+static uint32_t
+ar724x_chip_get_eth_pll(unsigned int mac, int speed)
+{
+
+ return (0);
+}
+
+static void
+ar724x_chip_init_usb_peripheral(void)
+{
+
+ switch (ar71xx_soc) {
+ case AR71XX_SOC_AR7240:
+ ar71xx_device_stop(AR724X_RESET_MODULE_USB_OHCI_DLL |
+ AR724X_RESET_USB_HOST);
+ DELAY(1000);
+
+ ar71xx_device_start(AR724X_RESET_MODULE_USB_OHCI_DLL |
+ AR724X_RESET_USB_HOST);
+ DELAY(1000);
+
+ /*
+ * WAR for HW bug. Here it adjusts the duration
+ * between two SOFS.
+ */
+ ATH_WRITE_REG(AR71XX_USB_CTRL_FLADJ,
+ (3 << USB_CTRL_FLADJ_A0_SHIFT));
+
+ break;
+
+ case AR71XX_SOC_AR7241:
+ case AR71XX_SOC_AR7242:
+ ar71xx_device_start(AR724X_RESET_MODULE_USB_OHCI_DLL);
+ DELAY(100);
+
+ ar71xx_device_start(AR724X_RESET_USB_HOST);
+ DELAY(100);
+
+ ar71xx_device_start(AR724X_RESET_USB_PHY);
+ DELAY(100);
+
+ break;
+
+ default:
+ break;
+ }
+}
+
+struct ar71xx_cpu_def ar724x_chip_def = {
+ &ar724x_chip_detect_mem_size,
+ &ar724x_chip_detect_sys_frequency,
+ &ar724x_chip_device_stop,
+ &ar724x_chip_device_start,
+ &ar724x_chip_device_stopped,
+ &ar724x_chip_set_pll_ge,
+ &ar724x_chip_set_mii_speed,
+ &ar71xx_chip_set_mii_if,
+ &ar724x_chip_ddr_flush_ge,
+ &ar724x_chip_get_eth_pll,
+ &ar724x_chip_ddr_flush_ip2,
+ &ar724x_chip_init_usb_peripheral
+};
Property changes on: trunk/sys/mips/atheros/ar724x_chip.c
___________________________________________________________________
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+text/plain
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Added: trunk/sys/mips/atheros/ar724x_chip.h
===================================================================
--- trunk/sys/mips/atheros/ar724x_chip.h (rev 0)
+++ trunk/sys/mips/atheros/ar724x_chip.h 2018-05-26 21:55:02 UTC (rev 9987)
@@ -0,0 +1,35 @@
+/* $MidnightBSD$ */
+/*-
+ * Copyright (c) 2010 Adrian Chadd
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ */
+
+/* $FreeBSD: stable/10/sys/mips/atheros/ar724x_chip.h 211503 2010-08-19 11:53:55Z adrian $ */
+
+#ifndef __AR724X_CHIP_H__
+#define __AR724X_CHIP_H__
+
+extern struct ar71xx_cpu_def ar724x_chip_def;
+
+#endif
Property changes on: trunk/sys/mips/atheros/ar724x_chip.h
___________________________________________________________________
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+native
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+MidnightBSD=%H
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+text/plain
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Added: trunk/sys/mips/atheros/ar724x_pci.c
===================================================================
--- trunk/sys/mips/atheros/ar724x_pci.c (rev 0)
+++ trunk/sys/mips/atheros/ar724x_pci.c 2018-05-26 21:55:02 UTC (rev 9987)
@@ -0,0 +1,653 @@
+/* $MidnightBSD$ */
+/*-
+ * Copyright (c) 2009, Oleksandr Tymoshenko <gonzo at FreeBSD.org>
+ * Copyright (c) 2011, Luiz Otavio O Souza.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice unmodified, this list of conditions, and the following
+ * disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ */
+
+#include <sys/cdefs.h>
+__FBSDID("$FreeBSD: stable/10/sys/mips/atheros/ar724x_pci.c 265999 2014-05-14 01:35:43Z ian $");
+
+#include "opt_ar71xx.h"
+
+#include <sys/param.h>
+#include <sys/systm.h>
+
+#include <sys/bus.h>
+#include <sys/interrupt.h>
+#include <sys/malloc.h>
+#include <sys/kernel.h>
+#include <sys/module.h>
+#include <sys/rman.h>
+
+#include <vm/vm.h>
+#include <vm/pmap.h>
+#include <vm/vm_extern.h>
+
+#include <machine/bus.h>
+#include <machine/cpu.h>
+#include <machine/intr_machdep.h>
+#include <machine/pmap.h>
+
+#include <dev/pci/pcivar.h>
+#include <dev/pci/pcireg.h>
+
+#include <dev/pci/pcib_private.h>
+#include "pcib_if.h"
+
+#include <mips/atheros/ar71xxreg.h>
+#include <mips/atheros/ar724xreg.h>
+#include <mips/atheros/ar71xx_setup.h>
+#include <mips/atheros/ar71xx_pci_bus_space.h>
+
+#include <mips/atheros/ar71xx_cpudef.h>
+
+#ifdef AR71XX_ATH_EEPROM
+#include <mips/atheros/ar71xx_fixup.h>
+#endif /* AR71XX_ATH_EEPROM */
+
+#undef AR724X_PCI_DEBUG
+#ifdef AR724X_PCI_DEBUG
+#define dprintf printf
+#else
+#define dprintf(x, arg...)
+#endif
+
+struct ar71xx_pci_softc {
+ device_t sc_dev;
+
+ int sc_busno;
+ struct rman sc_mem_rman;
+ struct rman sc_irq_rman;
+
+ struct intr_event *sc_eventstab[AR71XX_PCI_NIRQS];
+ mips_intrcnt_t sc_intr_counter[AR71XX_PCI_NIRQS];
+ struct resource *sc_irq;
+ void *sc_ih;
+};
+
+static int ar724x_pci_setup_intr(device_t, device_t, struct resource *, int,
+ driver_filter_t *, driver_intr_t *, void *, void **);
+static int ar724x_pci_teardown_intr(device_t, device_t, struct resource *,
+ void *);
+static int ar724x_pci_intr(void *);
+
+static void
+ar724x_pci_write(uint32_t reg, uint32_t offset, uint32_t data, int bytes)
+{
+ uint32_t val, mask, shift;
+
+ /* Register access is 32-bit aligned */
+ shift = (offset & 3) * 8;
+ if (bytes % 4)
+ mask = (1 << (bytes * 8)) - 1;
+ else
+ mask = 0xffffffff;
+
+ val = ATH_READ_REG(reg + (offset & ~3));
+ val &= ~(mask << shift);
+ val |= ((data & mask) << shift);
+ ATH_WRITE_REG(reg + (offset & ~3), val);
+
+ dprintf("%s: %#x/%#x addr=%#x, data=%#x(%#x), bytes=%d\n", __func__,
+ reg, reg + (offset & ~3), offset, data, val, bytes);
+}
+
+static uint32_t
+ar724x_pci_read_config(device_t dev, u_int bus, u_int slot, u_int func,
+ u_int reg, int bytes)
+{
+ uint32_t data, shift, mask;
+
+ /* Register access is 32-bit aligned */
+ shift = (reg & 3) * 8;
+ if (shift)
+ mask = (1 << shift) - 1;
+ else
+ mask = 0xffffffff;
+
+ dprintf("%s: tag (%x, %x, %x) reg %d(%d)\n", __func__, bus, slot,
+ func, reg, bytes);
+
+ if ((bus == 0) && (slot == 0) && (func == 0))
+ data = ATH_READ_REG(AR724X_PCI_CFG_BASE + (reg & ~3));
+ else
+ data = -1;
+
+ /* Get request bytes from 32-bit word */
+ data = (data >> shift) & mask;
+
+ dprintf("%s: read 0x%x\n", __func__, data);
+
+ return (data);
+}
+
+static void
+ar724x_pci_write_config(device_t dev, u_int bus, u_int slot, u_int func,
+ u_int reg, uint32_t data, int bytes)
+{
+
+ dprintf("%s: tag (%x, %x, %x) reg %d(%d): %x\n", __func__, bus, slot,
+ func, reg, bytes, data);
+
+ if ((bus != 0) || (slot != 0) || (func != 0))
+ return;
+
+ /*
+ * WAR for BAR issue on AR7240 - We are unable to access the PCI device
+ * space if we set the BAR with proper base address.
+ */
+ if (reg == PCIR_BAR(0) && bytes == 4 && ar71xx_soc == AR71XX_SOC_AR7240)
+ ar724x_pci_write(AR724X_PCI_CFG_BASE, reg, 0xffff, bytes);
+ else
+ ar724x_pci_write(AR724X_PCI_CFG_BASE, reg, data, bytes);
+}
+
+static void
+ar724x_pci_mask_irq(void *source)
+{
+ uint32_t reg;
+ unsigned int irq = (unsigned int)source;
+
+ /* XXX - Only one interrupt ? Only one device ? */
+ if (irq != AR71XX_PCI_IRQ_START)
+ return;
+
+ /* Update the interrupt mask reg */
+ reg = ATH_READ_REG(AR724X_PCI_INTR_MASK);
+ ATH_WRITE_REG(AR724X_PCI_INTR_MASK,
+ reg & ~AR724X_PCI_INTR_DEV0);
+
+ /* Clear any pending interrupt */
+ reg = ATH_READ_REG(AR724X_PCI_INTR_STATUS);
+ ATH_WRITE_REG(AR724X_PCI_INTR_STATUS,
+ reg | AR724X_PCI_INTR_DEV0);
+}
+
+static void
+ar724x_pci_unmask_irq(void *source)
+{
+ uint32_t reg;
+ unsigned int irq = (unsigned int)source;
+
+ /* XXX */
+ if (irq != AR71XX_PCI_IRQ_START)
+ return;
+
+ /* Update the interrupt mask reg */
+ reg = ATH_READ_REG(AR724X_PCI_INTR_MASK);
+ ATH_WRITE_REG(AR724X_PCI_INTR_MASK,
+ reg | AR724X_PCI_INTR_DEV0);
+}
+
+static int
+ar724x_pci_setup(device_t dev)
+{
+ uint32_t reg;
+
+ /* setup COMMAND register */
+ reg = PCIM_CMD_BUSMASTEREN | PCIM_CMD_MEMEN | PCIM_CMD_SERRESPEN |
+ PCIM_CMD_BACKTOBACK | PCIM_CMD_PERRESPEN | PCIM_CMD_MWRICEN;
+
+ ar724x_pci_write(AR724X_PCI_CRP_BASE, PCIR_COMMAND, reg, 2);
+ ar724x_pci_write(AR724X_PCI_CRP_BASE, 0x20, 0x1ff01000, 4);
+ ar724x_pci_write(AR724X_PCI_CRP_BASE, 0x24, 0x1ff01000, 4);
+
+ reg = ATH_READ_REG(AR724X_PCI_RESET);
+ if (reg != 0x7) {
+ DELAY(100000);
+ ATH_WRITE_REG(AR724X_PCI_RESET, 0);
+ DELAY(100);
+ ATH_WRITE_REG(AR724X_PCI_RESET, 4);
+ DELAY(100000);
+ }
+
+ if (ar71xx_soc == AR71XX_SOC_AR7240)
+ reg = AR724X_PCI_APP_LTSSM_ENABLE;
+ else
+ reg = 0x1ffc1;
+ ATH_WRITE_REG(AR724X_PCI_APP, reg);
+ /* Flush write */
+ (void) ATH_READ_REG(AR724X_PCI_APP);
+
+ DELAY(1000);
+
+ reg = ATH_READ_REG(AR724X_PCI_RESET);
+ if ((reg & AR724X_PCI_RESET_LINK_UP) == 0) {
+ device_printf(dev, "no PCIe controller found\n");
+ return (ENXIO);
+ }
+
+ if (ar71xx_soc == AR71XX_SOC_AR7241 ||
+ ar71xx_soc == AR71XX_SOC_AR7242) {
+ reg = ATH_READ_REG(AR724X_PCI_APP);
+ reg |= (1 << 16);
+ ATH_WRITE_REG(AR724X_PCI_APP, reg);
+ }
+
+ return (0);
+}
+
+#ifdef AR71XX_ATH_EEPROM
+#define AR5416_EEPROM_MAGIC 0xa55a
+
+/*
+ * XXX - This should not be here ! And this looks like Atheros (if_ath) only.
+ */
+static void
+ar724x_pci_fixup(device_t dev, long flash_addr, int len)
+{
+ uint32_t bar0, reg, val;
+ uint16_t *cal_data = (uint16_t *) MIPS_PHYS_TO_KSEG1(flash_addr);
+
+ if (cal_data[0] != AR5416_EEPROM_MAGIC) {
+ device_printf(dev, "%s: Invalid calibration data from 0x%x\n",
+ __func__, (uintptr_t) flash_addr);
+ return;
+ }
+
+ /* Save bar(0) address - just to flush bar(0) (SoC WAR) ? */
+ bar0 = ar724x_pci_read_config(dev, 0, 0, 0, PCIR_BAR(0), 4);
+
+ /* Write temporary BAR0 to map the NIC into a fixed location */
+ ar724x_pci_write_config(dev, 0, 0, 0, PCIR_BAR(0),
+ AR71XX_PCI_MEM_BASE, 4);
+
+ val = ar724x_pci_read_config(dev, 0, 0, 0, PCIR_COMMAND, 2);
+ val |= (PCIM_CMD_BUSMASTEREN | PCIM_CMD_MEMEN);
+ ar724x_pci_write_config(dev, 0, 0, 0, PCIR_COMMAND, val, 2);
+
+ /* set pointer to first reg address */
+ cal_data += 3;
+ while (*cal_data != 0xffff) {
+ reg = *cal_data++;
+ val = *cal_data++;
+ val |= (*cal_data++) << 16;
+
+ if (bootverbose)
+ printf(" 0x%08x=0x%04x\n", reg, val);
+
+ /* Write eeprom fixup data to device memory */
+ ATH_WRITE_REG(AR71XX_PCI_MEM_BASE + reg, val);
+ DELAY(100);
+ }
+
+ val = ar724x_pci_read_config(dev, 0, 0, 0, PCIR_COMMAND, 2);
+ val &= ~(PCIM_CMD_BUSMASTEREN | PCIM_CMD_MEMEN);
+ ar724x_pci_write_config(dev, 0, 0, 0, PCIR_COMMAND, val, 2);
+
+ /* Write the saved bar(0) address */
+ ar724x_pci_write_config(dev, 0, 0, 0, PCIR_BAR(0), bar0, 4);
+}
+#undef AR5416_EEPROM_MAGIC
+
+/*
+ * XXX This is (mostly) duplicated with ar71xx_pci.c.
+ * It should at some point be fixed.
+ */
+static void
+ar724x_pci_slot_fixup(device_t dev)
+{
+ long int flash_addr;
+ char buf[64];
+ int size;
+
+ /*
+ * Check whether the given slot has a hint to poke.
+ */
+ if (bootverbose)
+ device_printf(dev, "%s: checking dev %s, %d/%d/%d\n",
+ __func__, device_get_nameunit(dev), 0, 0, 0);
+
+ snprintf(buf, sizeof(buf), "bus.%d.%d.%d.ath_fixup_addr",
+ 0, 0, 0);
+
+ if (resource_long_value(device_get_name(dev), device_get_unit(dev),
+ buf, &flash_addr) == 0) {
+ snprintf(buf, sizeof(buf), "bus.%d.%d.%d.ath_fixup_size",
+ 0, 0, 0);
+ if (resource_int_value(device_get_name(dev),
+ device_get_unit(dev), buf, &size) != 0) {
+ device_printf(dev,
+ "%s: missing hint '%s', aborting EEPROM\n",
+ __func__, buf);
+ return;
+ }
+
+
+ device_printf(dev, "found EEPROM at 0x%lx on %d.%d.%d\n",
+ flash_addr, 0, 0, 0);
+ ar724x_pci_fixup(dev, flash_addr, size);
+ ar71xx_pci_slot_create_eeprom_firmware(dev, 0, 0, 0,
+ flash_addr, size);
+ }
+}
+#endif /* AR71XX_ATH_EEPROM */
+
+static int
+ar724x_pci_probe(device_t dev)
+{
+
+ return (BUS_PROBE_NOWILDCARD);
+}
+
+static int
+ar724x_pci_attach(device_t dev)
+{
+ struct ar71xx_pci_softc *sc = device_get_softc(dev);
+ int busno = 0;
+ int rid = 0;
+
+ sc->sc_mem_rman.rm_type = RMAN_ARRAY;
+ sc->sc_mem_rman.rm_descr = "ar724x PCI memory window";
+ if (rman_init(&sc->sc_mem_rman) != 0 ||
+ rman_manage_region(&sc->sc_mem_rman, AR71XX_PCI_MEM_BASE,
+ AR71XX_PCI_MEM_BASE + AR71XX_PCI_MEM_SIZE - 1) != 0) {
+ panic("ar724x_pci_attach: failed to set up I/O rman");
+ }
+
+ sc->sc_irq_rman.rm_type = RMAN_ARRAY;
+ sc->sc_irq_rman.rm_descr = "ar724x PCI IRQs";
+ if (rman_init(&sc->sc_irq_rman) != 0 ||
+ rman_manage_region(&sc->sc_irq_rman, AR71XX_PCI_IRQ_START,
+ AR71XX_PCI_IRQ_END) != 0)
+ panic("ar724x_pci_attach: failed to set up IRQ rman");
+
+ /* Disable interrupts */
+ ATH_WRITE_REG(AR724X_PCI_INTR_STATUS, 0);
+ ATH_WRITE_REG(AR724X_PCI_INTR_MASK, 0);
+
+ /* Hook up our interrupt handler. */
+ if ((sc->sc_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
+ RF_SHAREABLE | RF_ACTIVE)) == NULL) {
+ device_printf(dev, "unable to allocate IRQ resource\n");
+ return (ENXIO);
+ }
+
+ if ((bus_setup_intr(dev, sc->sc_irq, INTR_TYPE_MISC,
+ ar724x_pci_intr, NULL, sc, &sc->sc_ih))) {
+ device_printf(dev,
+ "WARNING: unable to register interrupt handler\n");
+ return (ENXIO);
+ }
+
+ /* Reset PCIe core and PCIe PHY */
+ ar71xx_device_stop(AR724X_RESET_PCIE);
+ ar71xx_device_stop(AR724X_RESET_PCIE_PHY);
+ ar71xx_device_stop(AR724X_RESET_PCIE_PHY_SERIAL);
+ DELAY(100);
+
+ ar71xx_device_start(AR724X_RESET_PCIE_PHY_SERIAL);
+ DELAY(100);
+ ar71xx_device_start(AR724X_RESET_PCIE_PHY);
+ ar71xx_device_start(AR724X_RESET_PCIE);
+
+ if (ar724x_pci_setup(dev))
+ return (ENXIO);
+
+#ifdef AR71XX_ATH_EEPROM
+ ar724x_pci_slot_fixup(dev);
+#endif /* AR71XX_ATH_EEPROM */
+
+ /* Fixup internal PCI bridge */
+ ar724x_pci_write_config(dev, 0, 0, 0, PCIR_COMMAND,
+ PCIM_CMD_BUSMASTEREN | PCIM_CMD_MEMEN
+ | PCIM_CMD_SERRESPEN | PCIM_CMD_BACKTOBACK
+ | PCIM_CMD_PERRESPEN | PCIM_CMD_MWRICEN, 2);
+
+ device_add_child(dev, "pci", busno);
+ return (bus_generic_attach(dev));
+}
+
+static int
+ar724x_pci_read_ivar(device_t dev, device_t child, int which, uintptr_t *result)
+{
+ struct ar71xx_pci_softc *sc = device_get_softc(dev);
+
+ switch (which) {
+ case PCIB_IVAR_DOMAIN:
+ *result = 0;
+ return (0);
+ case PCIB_IVAR_BUS:
+ *result = sc->sc_busno;
+ return (0);
+ }
+
+ return (ENOENT);
+}
+
+static int
+ar724x_pci_write_ivar(device_t dev, device_t child, int which, uintptr_t result)
+{
+ struct ar71xx_pci_softc * sc = device_get_softc(dev);
+
+ switch (which) {
+ case PCIB_IVAR_BUS:
+ sc->sc_busno = result;
+ return (0);
+ }
+
+ return (ENOENT);
+}
+
+static struct resource *
+ar724x_pci_alloc_resource(device_t bus, device_t child, int type, int *rid,
+ u_long start, u_long end, u_long count, u_int flags)
+{
+ struct ar71xx_pci_softc *sc = device_get_softc(bus);
+ struct resource *rv;
+ struct rman *rm;
+
+ switch (type) {
+ case SYS_RES_IRQ:
+ rm = &sc->sc_irq_rman;
+ break;
+ case SYS_RES_MEMORY:
+ rm = &sc->sc_mem_rman;
+ break;
+ default:
+ return (NULL);
+ }
+
+ rv = rman_reserve_resource(rm, start, end, count, flags, child);
+
+ if (rv == NULL)
+ return (NULL);
+
+ rman_set_rid(rv, *rid);
+
+ if (flags & RF_ACTIVE) {
+ if (bus_activate_resource(child, type, *rid, rv)) {
+ rman_release_resource(rv);
+ return (NULL);
+ }
+ }
+
+
+ return (rv);
+}
+
+static int
+ar724x_pci_activate_resource(device_t bus, device_t child, int type, int rid,
+ struct resource *r)
+{
+ int res = (BUS_ACTIVATE_RESOURCE(device_get_parent(bus),
+ child, type, rid, r));
+
+ if (!res) {
+ switch(type) {
+ case SYS_RES_MEMORY:
+ case SYS_RES_IOPORT:
+
+ rman_set_bustag(r, ar71xx_bus_space_pcimem);
+ break;
+ }
+ }
+
+ return (res);
+}
+
+static int
+ar724x_pci_setup_intr(device_t bus, device_t child, struct resource *ires,
+ int flags, driver_filter_t *filt, driver_intr_t *handler,
+ void *arg, void **cookiep)
+{
+ struct ar71xx_pci_softc *sc = device_get_softc(bus);
+ struct intr_event *event;
+ int irq, error;
+
+ irq = rman_get_start(ires);
+ if (irq > AR71XX_PCI_IRQ_END)
+ panic("%s: bad irq %d", __func__, irq);
+
+ event = sc->sc_eventstab[irq];
+ if (event == NULL) {
+ error = intr_event_create(&event, (void *)irq, 0, irq,
+ ar724x_pci_mask_irq, ar724x_pci_unmask_irq, NULL, NULL,
+ "pci intr%d:", irq);
+
+ if (error == 0) {
+ sc->sc_eventstab[irq] = event;
+ sc->sc_intr_counter[irq] =
+ mips_intrcnt_create(event->ie_name);
+ }
+ else
+ return error;
+ }
+
+ intr_event_add_handler(event, device_get_nameunit(child), filt,
+ handler, arg, intr_priority(flags), flags, cookiep);
+ mips_intrcnt_setname(sc->sc_intr_counter[irq], event->ie_fullname);
+
+ ar724x_pci_unmask_irq((void*)irq);
+
+ return (0);
+}
+
+static int
+ar724x_pci_teardown_intr(device_t dev, device_t child, struct resource *ires,
+ void *cookie)
+{
+ struct ar71xx_pci_softc *sc = device_get_softc(dev);
+ int irq, result;
+
+ irq = rman_get_start(ires);
+ if (irq > AR71XX_PCI_IRQ_END)
+ panic("%s: bad irq %d", __func__, irq);
+
+ if (sc->sc_eventstab[irq] == NULL)
+ panic("Trying to teardown unoccupied IRQ");
+
+ ar724x_pci_mask_irq((void*)irq);
+
+ result = intr_event_remove_handler(cookie);
+ if (!result)
+ sc->sc_eventstab[irq] = NULL;
+
+ return (result);
+}
+
+static int
+ar724x_pci_intr(void *arg)
+{
+ struct ar71xx_pci_softc *sc = arg;
+ struct intr_event *event;
+ uint32_t reg, irq, mask;
+
+ ar71xx_device_ddr_flush_ip2();
+
+ reg = ATH_READ_REG(AR724X_PCI_INTR_STATUS);
+ mask = ATH_READ_REG(AR724X_PCI_INTR_MASK);
+ /*
+ * Handle only unmasked interrupts
+ */
+ reg &= mask;
+ if (reg & AR724X_PCI_INTR_DEV0) {
+
+ irq = AR71XX_PCI_IRQ_START;
+ event = sc->sc_eventstab[irq];
+ if (!event || TAILQ_EMPTY(&event->ie_handlers)) {
+ printf("Stray IRQ %d\n", irq);
+ return (FILTER_STRAY);
+ }
+
+ /* TODO: frame instead of NULL? */
+ intr_event_handle(event, NULL);
+ mips_intrcnt_inc(sc->sc_intr_counter[irq]);
+ }
+
+ return (FILTER_HANDLED);
+}
+
+static int
+ar724x_pci_maxslots(device_t dev)
+{
+
+ return (PCI_SLOTMAX);
+}
+
+static int
+ar724x_pci_route_interrupt(device_t pcib, device_t device, int pin)
+{
+
+ return (pci_get_slot(device));
+}
+
+static device_method_t ar724x_pci_methods[] = {
+ /* Device interface */
+ DEVMETHOD(device_probe, ar724x_pci_probe),
+ DEVMETHOD(device_attach, ar724x_pci_attach),
+ DEVMETHOD(device_shutdown, bus_generic_shutdown),
+ DEVMETHOD(device_suspend, bus_generic_suspend),
+ DEVMETHOD(device_resume, bus_generic_resume),
+
+ /* Bus interface */
+ DEVMETHOD(bus_read_ivar, ar724x_pci_read_ivar),
+ DEVMETHOD(bus_write_ivar, ar724x_pci_write_ivar),
+ DEVMETHOD(bus_alloc_resource, ar724x_pci_alloc_resource),
+ DEVMETHOD(bus_release_resource, bus_generic_release_resource),
+ DEVMETHOD(bus_activate_resource, ar724x_pci_activate_resource),
+ DEVMETHOD(bus_deactivate_resource, bus_generic_deactivate_resource),
+ DEVMETHOD(bus_setup_intr, ar724x_pci_setup_intr),
+ DEVMETHOD(bus_teardown_intr, ar724x_pci_teardown_intr),
+
+ /* pcib interface */
+ DEVMETHOD(pcib_maxslots, ar724x_pci_maxslots),
+ DEVMETHOD(pcib_read_config, ar724x_pci_read_config),
+ DEVMETHOD(pcib_write_config, ar724x_pci_write_config),
+ DEVMETHOD(pcib_route_interrupt, ar724x_pci_route_interrupt),
+
+ DEVMETHOD_END
+};
+
+static driver_t ar724x_pci_driver = {
+ "pcib",
+ ar724x_pci_methods,
+ sizeof(struct ar71xx_pci_softc),
+};
+
+static devclass_t ar724x_pci_devclass;
+
+DRIVER_MODULE(ar724x_pci, nexus, ar724x_pci_driver, ar724x_pci_devclass, 0, 0);
Property changes on: trunk/sys/mips/atheros/ar724x_pci.c
___________________________________________________________________
Added: svn:eol-style
## -0,0 +1 ##
+native
\ No newline at end of property
Added: svn:keywords
## -0,0 +1 ##
+MidnightBSD=%H
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+text/plain
\ No newline at end of property
Added: trunk/sys/mips/atheros/ar724xreg.h
===================================================================
--- trunk/sys/mips/atheros/ar724xreg.h (rev 0)
+++ trunk/sys/mips/atheros/ar724xreg.h 2018-05-26 21:55:02 UTC (rev 9987)
@@ -0,0 +1,109 @@
+/* $MidnightBSD$ */
+/*-
+ * Copyright (c) 2010 Adrian Chadd
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ */
+
+/* $FreeBSD: stable/10/sys/mips/atheros/ar724xreg.h 221518 2011-05-06 02:45:02Z adrian $ */
+
+#ifndef __AR72XX_REG_H__
+#define __AR72XX_REG_H__
+
+#define AR724X_PLL_REG_CPU_CONFIG AR71XX_PLL_CPU_BASE + 0x00
+#define AR724X_PLL_REG_PCIE_CONFIG AR71XX_PLL_CPU_BASE + 0x18
+
+#define AR724X_PLL_DIV_SHIFT 0
+#define AR724X_PLL_DIV_MASK 0x3ff
+#define AR724X_PLL_REF_DIV_SHIFT 10
+#define AR724X_PLL_REF_DIV_MASK 0xf
+#define AR724X_AHB_DIV_SHIFT 19
+#define AR724X_AHB_DIV_MASK 0x1
+#define AR724X_DDR_DIV_SHIFT 22
+#define AR724X_DDR_DIV_MASK 0x3
+
+#define AR724X_PLL_VAL_1000 0x00110000
+#define AR724X_PLL_VAL_100 0x00001099
+#define AR724X_PLL_VAL_10 0x00991099
+
+#define AR724X_BASE_FREQ 5000000
+
+#define AR724X_DDR_REG_FLUSH_GE0 (AR71XX_DDR_CONFIG + 0x7c)
+#define AR724X_DDR_REG_FLUSH_GE1 (AR71XX_DDR_CONFIG + 0x80)
+#define AR724X_DDR_REG_FLUSH_USB (AR71XX_DDR_CONFIG + 0x84)
+#define AR724X_DDR_REG_FLUSH_PCIE (AR71XX_DDR_CONFIG + 0x88)
+
+#define AR724X_RESET_REG_RESET_MODULE AR71XX_RST_BLOCK_BASE + 0x1c
+#define AR724X_RESET_USB_HOST (1 << 5)
+#define AR724X_RESET_USB_PHY (1 << 4)
+#define AR724X_RESET_MODULE_USB_OHCI_DLL (1 << 3)
+
+#define AR724X_RESET_GE1_MDIO (1 << 23)
+#define AR724X_RESET_GE0_MDIO (1 << 22)
+#define AR724X_RESET_PCIE_PHY_SERIAL (1 << 10)
+#define AR724X_RESET_PCIE_PHY (1 << 7)
+#define AR724X_RESET_PCIE (1 << 6)
+#define AR724X_RESET_USB_HOST (1 << 5)
+#define AR724X_RESET_USB_PHY (1 << 4)
+#define AR724X_RESET_USBSUS_OVERRIDE (1 << 3)
+
+/* XXX so USB requires different init code? -adrian */
+#define AR7240_OHCI_BASE 0x1b000000
+#define AR7240_OHCI_SIZE 0x01000000
+
+#define AR724X_PCI_CRP_BASE (AR71XX_APB_BASE + 0x000C0000)
+#define AR724X_PCI_CRP_SIZE 0x100
+#define AR724X_PCI_CFG_BASE 0x14000000
+#define AR724X_PCI_CFG_SIZE 0x1000
+
+#define AR724X_PCI_CTRL_BASE (AR71XX_APB_BASE + 0x000F0000)
+#define AR724X_PCI_CTRL_SIZE 0x100
+
+/* PCI config registers */
+#define AR724X_PCI_APP 0x180f0000
+#define AR724X_PCI_APP_LTSSM_ENABLE (1 << 0)
+#define AR724X_PCI_RESET 0x180f0018
+#define AR724X_PCI_RESET_LINK_UP (1 << 0)
+#define AR724X_PCI_INTR_STATUS 0x180f004c
+#define AR724X_PCI_INTR_MASK 0x180f0050
+#define AR724X_PCI_INTR_DEV0 (1 << 14)
+
+#define AR724X_GPIO_FUNC_GE0_MII_CLK_EN (1 >> 19)
+#define AR724X_GPIO_FUNC_SPI_EN (1 >> 18)
+#define AR724X_GPIO_FUNC_SPI_CS_EN2 (1 >> 14)
+#define AR724X_GPIO_FUNC_SPI_CS_EN1 (1 >> 13)
+#define AR724X_GPIO_FUNC_CLK_OBS5_EN (1 >> 12)
+#define AR724X_GPIO_FUNC_CLK_OBS4_EN (1 >> 11)
+#define AR724X_GPIO_FUNC_CLK_OBS3_EN (1 >> 10)
+#define AR724X_GPIO_FUNC_CLK_OBS2_EN (1 >> 9)
+#define AR724X_GPIO_FUNC_CLK_OBS1_EN (1 >> 8)
+#define AR724X_GPIO_FUNC_ETH_SWITCH_LED4_EN (1 >> 7)
+#define AR724X_GPIO_FUNC_ETH_SWITCH_LED3_EN (1 >> 6)
+#define AR724X_GPIO_FUNC_ETH_SWITCH_LED2_EN (1 >> 5)
+#define AR724X_GPIO_FUNC_ETH_SWITCH_LED1_EN (1 >> 4)
+#define AR724X_GPIO_FUNC_ETH_SWITCH_LED0_EN (1 >> 3)
+#define AR724X_GPIO_FUNC_UART_RTS_CTS_EN (1 >> 2)
+#define AR724X_GPIO_FUNC_UART_EN (1 >> 1)
+#define AR724X_GPIO_FUNC_JTAG_DISABLE (1 >> 0)
+
+#endif
Property changes on: trunk/sys/mips/atheros/ar724xreg.h
___________________________________________________________________
Added: svn:eol-style
## -0,0 +1 ##
+native
\ No newline at end of property
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## -0,0 +1 ##
+MidnightBSD=%H
\ No newline at end of property
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## -0,0 +1 ##
+text/plain
\ No newline at end of property
Added: trunk/sys/mips/atheros/ar91xx_chip.c
===================================================================
--- trunk/sys/mips/atheros/ar91xx_chip.c (rev 0)
+++ trunk/sys/mips/atheros/ar91xx_chip.c 2018-05-26 21:55:02 UTC (rev 9987)
@@ -0,0 +1,224 @@
+/* $MidnightBSD$ */
+/*-
+ * Copyright (c) 2010 Adrian Chadd
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ */
+
+#include <sys/cdefs.h>
+__FBSDID("$FreeBSD: stable/10/sys/mips/atheros/ar91xx_chip.c 253508 2013-07-21 03:52:52Z adrian $");
+
+#include "opt_ddb.h"
+
+#include <sys/param.h>
+#include <sys/conf.h>
+#include <sys/kernel.h>
+#include <sys/systm.h>
+#include <sys/bus.h>
+#include <sys/cons.h>
+#include <sys/kdb.h>
+#include <sys/reboot.h>
+
+#include <vm/vm.h>
+#include <vm/vm_page.h>
+
+#include <net/ethernet.h>
+
+#include <machine/clock.h>
+#include <machine/cpu.h>
+#include <machine/cpuregs.h>
+#include <machine/hwfunc.h>
+#include <machine/md_var.h>
+#include <machine/trap.h>
+#include <machine/vmparam.h>
+
+#include <mips/atheros/ar71xxreg.h>
+#include <mips/atheros/ar71xx_cpudef.h>
+#include <mips/atheros/ar71xx_chip.h>
+#include <mips/atheros/ar91xxreg.h>
+#include <mips/atheros/ar91xx_chip.h>
+
+#include <mips/sentry5/s5reg.h>
+
+static void
+ar91xx_chip_detect_mem_size(void)
+{
+}
+
+static void
+ar91xx_chip_detect_sys_frequency(void)
+{
+ uint32_t pll;
+ uint32_t freq;
+ uint32_t div;
+
+ u_ar71xx_refclk = AR91XX_BASE_FREQ;
+
+ pll = ATH_READ_REG(AR91XX_PLL_REG_CPU_CONFIG);
+
+ div = ((pll >> AR91XX_PLL_DIV_SHIFT) & AR91XX_PLL_DIV_MASK);
+ freq = div * AR91XX_BASE_FREQ;
+ u_ar71xx_cpu_freq = freq;
+
+ div = ((pll >> AR91XX_DDR_DIV_SHIFT) & AR91XX_DDR_DIV_MASK) + 1;
+ u_ar71xx_ddr_freq = freq / div;
+
+ div = (((pll >> AR91XX_AHB_DIV_SHIFT) & AR91XX_AHB_DIV_MASK) + 1) * 2;
+ u_ar71xx_ahb_freq = u_ar71xx_cpu_freq / div;
+ u_ar71xx_uart_freq = u_ar71xx_cpu_freq / div;
+ u_ar71xx_wdt_freq = u_ar71xx_cpu_freq / div;
+}
+
+static void
+ar91xx_chip_device_stop(uint32_t mask)
+{
+ uint32_t reg;
+
+ reg = ATH_READ_REG(AR91XX_RESET_REG_RESET_MODULE);
+ ATH_WRITE_REG(AR91XX_RESET_REG_RESET_MODULE, reg | mask);
+}
+
+static void
+ar91xx_chip_device_start(uint32_t mask)
+{
+ uint32_t reg;
+
+ reg = ATH_READ_REG(AR91XX_RESET_REG_RESET_MODULE);
+ ATH_WRITE_REG(AR91XX_RESET_REG_RESET_MODULE, reg & ~mask);
+}
+
+static int
+ar91xx_chip_device_stopped(uint32_t mask)
+{
+ uint32_t reg;
+
+ reg = ATH_READ_REG(AR91XX_RESET_REG_RESET_MODULE);
+ return ((reg & mask) == mask);
+}
+
+static void
+ar91xx_chip_set_pll_ge(int unit, int speed, uint32_t pll)
+{
+
+ switch (unit) {
+ case 0:
+ ar71xx_write_pll(AR91XX_PLL_REG_ETH_CONFIG,
+ AR91XX_PLL_REG_ETH0_INT_CLOCK, pll,
+ AR91XX_ETH0_PLL_SHIFT);
+ break;
+ case 1:
+ ar71xx_write_pll(AR91XX_PLL_REG_ETH_CONFIG,
+ AR91XX_PLL_REG_ETH1_INT_CLOCK, pll,
+ AR91XX_ETH1_PLL_SHIFT);
+ break;
+ default:
+ printf("%s: invalid PLL set for arge unit: %d\n",
+ __func__, unit);
+ return;
+ }
+}
+
+static void
+ar91xx_chip_ddr_flush_ge(int unit)
+{
+
+ switch (unit) {
+ case 0:
+ ar71xx_ddr_flush(AR91XX_DDR_REG_FLUSH_GE0);
+ break;
+ case 1:
+ ar71xx_ddr_flush(AR91XX_DDR_REG_FLUSH_GE1);
+ break;
+ default:
+ printf("%s: invalid DDR flush for arge unit: %d\n",
+ __func__, unit);
+ return;
+ }
+}
+
+static void
+ar91xx_chip_ddr_flush_ip2(void)
+{
+
+ ar71xx_ddr_flush(AR91XX_DDR_REG_FLUSH_WMAC);
+}
+
+
+static uint32_t
+ar91xx_chip_get_eth_pll(unsigned int mac, int speed)
+{
+ uint32_t pll;
+
+ switch(speed) {
+ case 10:
+ pll = AR91XX_PLL_VAL_10;
+ break;
+ case 100:
+ pll = AR91XX_PLL_VAL_100;
+ break;
+ case 1000:
+ pll = AR91XX_PLL_VAL_1000;
+ break;
+ default:
+ printf("%s%d: invalid speed %d\n", __func__, mac, speed);
+ pll = 0;
+ }
+
+ return (pll);
+}
+
+static void
+ar91xx_chip_init_usb_peripheral(void)
+{
+
+ ar71xx_device_stop(AR91XX_RST_RESET_MODULE_USBSUS_OVERRIDE);
+ DELAY(100);
+
+ ar71xx_device_start(RST_RESET_USB_HOST);
+ DELAY(100);
+
+ ar71xx_device_start(RST_RESET_USB_PHY);
+ DELAY(100);
+
+ /* Wireless */
+ ar71xx_device_stop(AR91XX_RST_RESET_MODULE_AMBA2WMAC);
+ DELAY(1000);
+
+ ar71xx_device_start(AR91XX_RST_RESET_MODULE_AMBA2WMAC);
+ DELAY(1000);
+}
+
+struct ar71xx_cpu_def ar91xx_chip_def = {
+ &ar91xx_chip_detect_mem_size,
+ &ar91xx_chip_detect_sys_frequency,
+ &ar91xx_chip_device_stop,
+ &ar91xx_chip_device_start,
+ &ar91xx_chip_device_stopped,
+ &ar91xx_chip_set_pll_ge,
+ &ar71xx_chip_set_mii_speed,
+ &ar71xx_chip_set_mii_if,
+ &ar91xx_chip_ddr_flush_ge,
+ &ar91xx_chip_get_eth_pll,
+ &ar91xx_chip_ddr_flush_ip2,
+ &ar91xx_chip_init_usb_peripheral,
+};
Property changes on: trunk/sys/mips/atheros/ar91xx_chip.c
___________________________________________________________________
Added: svn:eol-style
## -0,0 +1 ##
+native
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+MidnightBSD=%H
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+text/plain
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Added: trunk/sys/mips/atheros/ar91xx_chip.h
===================================================================
--- trunk/sys/mips/atheros/ar91xx_chip.h (rev 0)
+++ trunk/sys/mips/atheros/ar91xx_chip.h 2018-05-26 21:55:02 UTC (rev 9987)
@@ -0,0 +1,35 @@
+/* $MidnightBSD$ */
+/*-
+ * Copyright (c) 2010 Adrian Chadd
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ */
+
+/* $FreeBSD: stable/10/sys/mips/atheros/ar91xx_chip.h 211502 2010-08-19 11:40:10Z adrian $ */
+
+#ifndef __AR91XX_CHIP_H__
+#define __AR91XX_CHIP_H__
+
+extern struct ar71xx_cpu_def ar91xx_chip_def;
+
+#endif
Property changes on: trunk/sys/mips/atheros/ar91xx_chip.h
___________________________________________________________________
Added: svn:eol-style
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+native
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+MidnightBSD=%H
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+text/plain
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Added: trunk/sys/mips/atheros/ar91xxreg.h
===================================================================
--- trunk/sys/mips/atheros/ar91xxreg.h (rev 0)
+++ trunk/sys/mips/atheros/ar91xxreg.h 2018-05-26 21:55:02 UTC (rev 9987)
@@ -0,0 +1,85 @@
+/* $MidnightBSD$ */
+/*-
+ * Copyright (c) 2010 Adrian Chadd
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ */
+
+/* $FreeBSD: stable/10/sys/mips/atheros/ar91xxreg.h 221518 2011-05-06 02:45:02Z adrian $ */
+
+#ifndef __AR91XX_REG_H__
+#define __AR91XX_REG_H__
+
+#define AR91XX_BASE_FREQ 5000000
+
+/* reset block */
+#define AR91XX_RESET_REG_RESET_MODULE AR71XX_RST_BLOCK_BASE + 0x1c
+
+#define AR91XX_RST_RESET_MODULE_USBSUS_OVERRIDE (1 << 10)
+#define AR91XX_RST_RESET_MODULE_AMBA2WMAC (1 << 22)
+
+/* PLL block */
+#define AR91XX_PLL_REG_CPU_CONFIG AR71XX_PLL_CPU_BASE + 0x00
+#define AR91XX_PLL_REG_ETH_CONFIG AR71XX_PLL_CPU_BASE + 0x04
+#define AR91XX_PLL_REG_ETH0_INT_CLOCK AR71XX_PLL_CPU_BASE + 0x14
+#define AR91XX_PLL_REG_ETH1_INT_CLOCK AR71XX_PLL_CPU_BASE + 0x18
+
+#define AR91XX_PLL_DIV_SHIFT 0
+#define AR91XX_PLL_DIV_MASK 0x3ff
+#define AR91XX_DDR_DIV_SHIFT 22
+#define AR91XX_DDR_DIV_MASK 0x3
+#define AR91XX_AHB_DIV_SHIFT 19
+#define AR91XX_AHB_DIV_MASK 0x1
+
+#define AR91XX_ETH0_PLL_SHIFT 20
+#define AR91XX_ETH1_PLL_SHIFT 22
+
+#define AR91XX_PLL_VAL_1000 0x1a000000
+#define AR91XX_PLL_VAL_100 0x13000a44
+#define AR91XX_PLL_VAL_10 0x00441099
+
+/* DDR block */
+#define AR91XX_DDR_CTRLBASE (AR71XX_APB_BASE + 0)
+#define AR91XX_DDR_CTRL_SIZE 0x10000
+#define AR91XX_DDR_REG_FLUSH_GE0 AR91XX_DDR_CTRLBASE + 0x7c
+#define AR91XX_DDR_REG_FLUSH_GE1 AR91XX_DDR_CTRLBASE + 0x80
+#define AR91XX_DDR_REG_FLUSH_USB AR91XX_DDR_CTRLBASE + 0x84
+#define AR91XX_DDR_REG_FLUSH_WMAC AR91XX_DDR_CTRLBASE + 0x88
+
+/* WMAC stuff */
+#define AR91XX_WMAC_BASE (AR71XX_APB_BASE + 0x000C0000)
+#define AR91XX_WMAC_SIZE 0x30000
+
+/* GPIO stuff */
+#define AR91XX_GPIO_FUNC_WMAC_LED_EN (1 << 22)
+#define AR91XX_GPIO_FUNC_EXP_PORT_CS_EN (1 << 21)
+#define AR91XX_GPIO_FUNC_I2S_REFCLKEN (1 << 20)
+#define AR91XX_GPIO_FUNC_I2S_MCKEN (1 << 19)
+#define AR91XX_GPIO_FUNC_I2S1_EN (1 << 18)
+#define AR91XX_GPIO_FUNC_I2S0_EN (1 << 17)
+#define AR91XX_GPIO_FUNC_SLIC_EN (1 << 16)
+#define AR91XX_GPIO_FUNC_UART_RTSCTS_EN (1 << 9)
+#define AR91XX_GPIO_FUNC_UART_EN (1 << 8)
+#define AR91XX_GPIO_FUNC_USB_CLK_EN (1 << 4)
+
+#endif
Property changes on: trunk/sys/mips/atheros/ar91xxreg.h
___________________________________________________________________
Added: svn:eol-style
## -0,0 +1 ##
+native
\ No newline at end of property
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+MidnightBSD=%H
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+text/plain
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Added: trunk/sys/mips/atheros/ar933x_chip.c
===================================================================
--- trunk/sys/mips/atheros/ar933x_chip.c (rev 0)
+++ trunk/sys/mips/atheros/ar933x_chip.c 2018-05-26 21:55:02 UTC (rev 9987)
@@ -0,0 +1,259 @@
+/* $MidnightBSD$ */
+/*-
+ * Copyright (c) 2012 Adrian Chadd <adrian at FreeBSD.org>
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ */
+
+#include <sys/cdefs.h>
+__FBSDID("$FreeBSD: stable/10/sys/mips/atheros/ar933x_chip.c 255764 2013-09-21 19:42:37Z adrian $");
+
+#include "opt_ddb.h"
+
+#include <sys/param.h>
+#include <sys/conf.h>
+#include <sys/kernel.h>
+#include <sys/systm.h>
+#include <sys/bus.h>
+#include <sys/cons.h>
+#include <sys/kdb.h>
+#include <sys/reboot.h>
+
+#include <vm/vm.h>
+#include <vm/vm_page.h>
+
+#include <net/ethernet.h>
+
+#include <machine/clock.h>
+#include <machine/cpu.h>
+#include <machine/cpuregs.h>
+#include <machine/hwfunc.h>
+#include <machine/md_var.h>
+#include <machine/trap.h>
+#include <machine/vmparam.h>
+
+#include <mips/atheros/ar71xxreg.h>
+#include <mips/atheros/ar933xreg.h>
+
+#include <mips/atheros/ar71xx_cpudef.h>
+#include <mips/atheros/ar71xx_setup.h>
+
+#include <mips/atheros/ar71xx_chip.h>
+#include <mips/atheros/ar933x_chip.h>
+
+static void
+ar933x_chip_detect_mem_size(void)
+{
+}
+
+static void
+ar933x_chip_detect_sys_frequency(void)
+{
+ uint32_t clock_ctrl;
+ uint32_t cpu_config;
+ uint32_t freq;
+ uint32_t t;
+
+ t = ATH_READ_REG(AR933X_RESET_REG_BOOTSTRAP);
+ if (t & AR933X_BOOTSTRAP_REF_CLK_40)
+ u_ar71xx_refclk = (40 * 1000 * 1000);
+ else
+ u_ar71xx_refclk = (25 * 1000 * 1000);
+
+ clock_ctrl = ATH_READ_REG(AR933X_PLL_CLOCK_CTRL_REG);
+ if (clock_ctrl & AR933X_PLL_CLOCK_CTRL_BYPASS) {
+ u_ar71xx_cpu_freq = u_ar71xx_refclk;
+ u_ar71xx_ahb_freq = u_ar71xx_refclk;
+ u_ar71xx_ddr_freq = u_ar71xx_refclk;
+ } else {
+ cpu_config = ATH_READ_REG(AR933X_PLL_CPU_CONFIG_REG);
+
+ t = (cpu_config >> AR933X_PLL_CPU_CONFIG_REFDIV_SHIFT) &
+ AR933X_PLL_CPU_CONFIG_REFDIV_MASK;
+ freq = u_ar71xx_refclk / t;
+
+ t = (cpu_config >> AR933X_PLL_CPU_CONFIG_NINT_SHIFT) &
+ AR933X_PLL_CPU_CONFIG_NINT_MASK;
+ freq *= t;
+
+ t = (cpu_config >> AR933X_PLL_CPU_CONFIG_OUTDIV_SHIFT) &
+ AR933X_PLL_CPU_CONFIG_OUTDIV_MASK;
+ if (t == 0)
+ t = 1;
+
+ freq >>= t;
+
+ t = ((clock_ctrl >> AR933X_PLL_CLOCK_CTRL_CPU_DIV_SHIFT) &
+ AR933X_PLL_CLOCK_CTRL_CPU_DIV_MASK) + 1;
+ u_ar71xx_cpu_freq = freq / t;
+
+ t = ((clock_ctrl >> AR933X_PLL_CLOCK_CTRL_DDR_DIV_SHIFT) &
+ AR933X_PLL_CLOCK_CTRL_DDR_DIV_MASK) + 1;
+ u_ar71xx_ddr_freq = freq / t;
+
+ t = ((clock_ctrl >> AR933X_PLL_CLOCK_CTRL_AHB_DIV_SHIFT) &
+ AR933X_PLL_CLOCK_CTRL_AHB_DIV_MASK) + 1;
+ u_ar71xx_ahb_freq = freq / t;
+ }
+
+ /* On the AR933x, the UART frequency is the reference clock,
+ * not the AHB bus clock.
+ */
+ u_ar71xx_uart_freq = u_ar71xx_refclk;
+
+ /*
+ * XXX check what the watchdog frequency should be?
+ */
+ u_ar71xx_wdt_freq = u_ar71xx_ahb_freq;
+}
+
+static void
+ar933x_chip_device_stop(uint32_t mask)
+{
+ uint32_t reg;
+
+ reg = ATH_READ_REG(AR933X_RESET_REG_RESET_MODULE);
+ ATH_WRITE_REG(AR933X_RESET_REG_RESET_MODULE, reg | mask);
+}
+
+static void
+ar933x_chip_device_start(uint32_t mask)
+{
+ uint32_t reg;
+
+ reg = ATH_READ_REG(AR933X_RESET_REG_RESET_MODULE);
+ ATH_WRITE_REG(AR933X_RESET_REG_RESET_MODULE, reg & ~mask);
+}
+
+static int
+ar933x_chip_device_stopped(uint32_t mask)
+{
+ uint32_t reg;
+
+ reg = ATH_READ_REG(AR933X_RESET_REG_RESET_MODULE);
+ return ((reg & mask) == mask);
+}
+
+static void
+ar933x_chip_set_mii_speed(uint32_t unit, uint32_t speed)
+{
+
+ /* XXX TODO */
+ return;
+}
+
+/*
+ * XXX TODO !!
+ */
+static void
+ar933x_chip_set_pll_ge(int unit, int speed, uint32_t pll)
+{
+
+ switch (unit) {
+ case 0:
+ /* XXX TODO */
+ break;
+ case 1:
+ /* XXX TODO */
+ break;
+ default:
+ printf("%s: invalid PLL set for arge unit: %d\n",
+ __func__, unit);
+ return;
+ }
+}
+
+static void
+ar933x_chip_ddr_flush_ge(int unit)
+{
+
+ switch (unit) {
+ case 0:
+ ar71xx_ddr_flush(AR933X_DDR_REG_FLUSH_GE0);
+ break;
+ case 1:
+ ar71xx_ddr_flush(AR933X_DDR_REG_FLUSH_GE1);
+ break;
+ default:
+ printf("%s: invalid DDR flush for arge unit: %d\n",
+ __func__, unit);
+ return;
+ }
+}
+
+static void
+ar933x_chip_ddr_flush_ip2(void)
+{
+
+ ar71xx_ddr_flush(AR933X_DDR_REG_FLUSH_WMAC);
+}
+
+static uint32_t
+ar933x_chip_get_eth_pll(unsigned int mac, int speed)
+{
+ uint32_t pll;
+
+ switch (speed) {
+ case 10:
+ pll = AR933X_PLL_VAL_10;
+ break;
+ case 100:
+ pll = AR933X_PLL_VAL_100;
+ break;
+ case 1000:
+ pll = AR933X_PLL_VAL_1000;
+ break;
+ default:
+ printf("%s%d: invalid speed %d\n", __func__, mac, speed);
+ pll = 0;
+ }
+ return (pll);
+}
+
+static void
+ar933x_chip_init_usb_peripheral(void)
+{
+ ar71xx_device_stop(AR933X_RESET_USBSUS_OVERRIDE);
+ DELAY(100);
+
+ ar71xx_device_start(AR933X_RESET_USB_HOST);
+ DELAY(100);
+
+ ar71xx_device_start(AR933X_RESET_USB_PHY);
+ DELAY(100);
+}
+
+struct ar71xx_cpu_def ar933x_chip_def = {
+ &ar933x_chip_detect_mem_size,
+ &ar933x_chip_detect_sys_frequency,
+ &ar933x_chip_device_stop,
+ &ar933x_chip_device_start,
+ &ar933x_chip_device_stopped,
+ &ar933x_chip_set_pll_ge,
+ &ar933x_chip_set_mii_speed,
+ &ar71xx_chip_set_mii_if,
+ &ar933x_chip_ddr_flush_ge,
+ &ar933x_chip_get_eth_pll,
+ &ar933x_chip_ddr_flush_ip2,
+ &ar933x_chip_init_usb_peripheral
+};
Property changes on: trunk/sys/mips/atheros/ar933x_chip.c
___________________________________________________________________
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+native
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+MidnightBSD=%H
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+text/plain
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Added: trunk/sys/mips/atheros/ar933x_chip.h
===================================================================
--- trunk/sys/mips/atheros/ar933x_chip.h (rev 0)
+++ trunk/sys/mips/atheros/ar933x_chip.h 2018-05-26 21:55:02 UTC (rev 9987)
@@ -0,0 +1,35 @@
+/* $MidnightBSD$ */
+/*-
+ * Copyright (c) 2012 Adrian Chadd <adrian at FreeBSD.org>
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ */
+
+/* $FreeBSD: stable/10/sys/mips/atheros/ar933x_chip.h 248782 2013-03-27 03:38:58Z adrian $ */
+
+#ifndef __AR933X_CHIP_H__
+#define __AR933X_CHIP_H__
+
+extern struct ar71xx_cpu_def ar933x_chip_def;
+
+#endif
Property changes on: trunk/sys/mips/atheros/ar933x_chip.h
___________________________________________________________________
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+native
\ No newline at end of property
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## -0,0 +1 ##
+MidnightBSD=%H
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## -0,0 +1 ##
+text/plain
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Added: trunk/sys/mips/atheros/ar933x_uart.h
===================================================================
--- trunk/sys/mips/atheros/ar933x_uart.h (rev 0)
+++ trunk/sys/mips/atheros/ar933x_uart.h 2018-05-26 21:55:02 UTC (rev 9987)
@@ -0,0 +1,92 @@
+/* $MidnightBSD$ */
+/*-
+ * Copyright (c) 2012 Adrian Chadd <adrian at FreeBSD.org>
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ * $FreeBSD: stable/10/sys/mips/atheros/ar933x_uart.h 248866 2013-03-29 06:32:02Z adrian $
+ */
+
+/*
+ * Atheros AR933x SoC UART registers
+ */
+#ifndef __AR933X_UART_H__
+#define __AR933X_UART_H__
+
+#define AR933X_UART_REGS_SIZE 20
+#define AR933X_UART_FIFO_SIZE 16
+
+#define AR933X_UART_DATA_REG 0x00
+#define AR933X_UART_CS_REG 0x04
+#define AR933X_UART_CLOCK_REG 0x08
+#define AR933X_UART_INT_REG 0x0c
+#define AR933X_UART_INT_EN_REG 0x10
+
+#define AR933X_UART_DATA_TX_RX_MASK 0xff
+#define AR933X_UART_DATA_RX_CSR (1 << 8)
+#define AR933X_UART_DATA_TX_CSR (1 << 9)
+
+#define AR933X_UART_CS_PARITY_S 0
+#define AR933X_UART_CS_PARITY_M 0x3
+#define AR933X_UART_CS_PARITY_NONE 0
+#define AR933X_UART_CS_PARITY_ODD 1
+#define AR933X_UART_CS_PARITY_EVEN 2
+#define AR933X_UART_CS_IF_MODE_S 2
+#define AR933X_UART_CS_IF_MODE_M 0x3
+#define AR933X_UART_CS_IF_MODE_NONE 0
+#define AR933X_UART_CS_IF_MODE_DTE 1
+#define AR933X_UART_CS_IF_MODE_DCE 2
+#define AR933X_UART_CS_FLOW_CTRL_S 4
+#define AR933X_UART_CS_FLOW_CTRL_M 0x3
+#define AR933X_UART_CS_DMA_EN (1 << 6)
+#define AR933X_UART_CS_TX_READY_ORIDE (1 << 7)
+#define AR933X_UART_CS_RX_READY_ORIDE (1 << 8)
+#define AR933X_UART_CS_TX_READY (1 << 9)
+#define AR933X_UART_CS_RX_BREAK (1 << 10)
+#define AR933X_UART_CS_TX_BREAK (1 << 11)
+#define AR933X_UART_CS_HOST_INT (1 << 12)
+#define AR933X_UART_CS_HOST_INT_EN (1 << 13)
+#define AR933X_UART_CS_TX_BUSY (1 << 14)
+#define AR933X_UART_CS_RX_BUSY (1 << 15)
+
+#define AR933X_UART_CLOCK_SCALE_M 0xff
+#define AR933X_UART_CLOCK_SCALE_S 16
+#define AR933X_UART_CLOCK_STEP_M 0xffff
+#define AR933X_UART_CLOCK_STEP_S 0
+
+#define AR933X_UART_MAX_SCALE 0xff
+#define AR933X_UART_MAX_STEP 0xffff
+
+#define AR933X_UART_INT_RX_VALID (1 << 0)
+#define AR933X_UART_INT_TX_READY (1 << 1)
+#define AR933X_UART_INT_RX_FRAMING_ERR (1 << 2)
+#define AR933X_UART_INT_RX_OFLOW_ERR (1 << 3)
+#define AR933X_UART_INT_TX_OFLOW_ERR (1 << 4)
+#define AR933X_UART_INT_RX_PARITY_ERR (1 << 5)
+#define AR933X_UART_INT_RX_BREAK_ON (1 << 6)
+#define AR933X_UART_INT_RX_BREAK_OFF (1 << 7)
+#define AR933X_UART_INT_RX_FULL (1 << 8)
+#define AR933X_UART_INT_TX_EMPTY (1 << 9)
+#define AR933X_UART_INT_ALLINTS 0x3ff
+
+#endif /* __AR933X_UART_H__ */
Property changes on: trunk/sys/mips/atheros/ar933x_uart.h
___________________________________________________________________
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+text/plain
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Added: trunk/sys/mips/atheros/ar933xreg.h
===================================================================
--- trunk/sys/mips/atheros/ar933xreg.h (rev 0)
+++ trunk/sys/mips/atheros/ar933xreg.h 2018-05-26 21:55:02 UTC (rev 9987)
@@ -0,0 +1,83 @@
+/* $MidnightBSD$ */
+/*-
+ * Copyright (c) 2012 Adrian Chadd <adrian at FreeBSD.org>
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ * $FreeBSD: stable/10/sys/mips/atheros/ar933xreg.h 249123 2013-04-05 01:35:59Z adrian $
+ */
+
+#ifndef __AR93XX_REG_H__
+#define __AR93XX_REG_H__
+
+#define REV_ID_MAJOR_AR9330 0x0110
+#define REV_ID_MAJOR_AR9331 0x1110
+
+#define AR933X_REV_ID_REVISION_MASK 0x3
+
+#define AR933X_GPIO_COUNT 30
+
+#define AR933X_UART_BASE (AR71XX_APB_BASE + 0x00020000)
+#define AR933X_UART_SIZE 0x14
+#define AR933X_WMAC_BASE (AR71XX_APB_BASE + 0x00100000)
+#define AR933X_WMAC_SIZE 0x20000
+#define AR933X_EHCI_BASE 0x1b000000
+#define AR933X_EHCI_SIZE 0x1000
+
+#define AR933X_DDR_REG_FLUSH_GE0 (AR71XX_APB_BASE + 0x7c)
+#define AR933X_DDR_REG_FLUSH_GE1 (AR71XX_APB_BASE + 0x80)
+#define AR933X_DDR_REG_FLUSH_USB (AR71XX_APB_BASE + 0x84)
+#define AR933X_DDR_REG_FLUSH_WMAC (AR71XX_APB_BASE + 0x88)
+
+#define AR933X_PLL_CPU_CONFIG_REG (AR71XX_PLL_CPU_BASE + 0x00)
+#define AR933X_PLL_CLOCK_CTRL_REG (AR71XX_PLL_CPU_BASE + 0x08)
+
+#define AR933X_PLL_CPU_CONFIG_NINT_SHIFT 10
+#define AR933X_PLL_CPU_CONFIG_NINT_MASK 0x3f
+#define AR933X_PLL_CPU_CONFIG_REFDIV_SHIFT 16
+#define AR933X_PLL_CPU_CONFIG_REFDIV_MASK 0x1f
+#define AR933X_PLL_CPU_CONFIG_OUTDIV_SHIFT 23
+#define AR933X_PLL_CPU_CONFIG_OUTDIV_MASK 0x7
+
+#define AR933X_PLL_CLOCK_CTRL_BYPASS (1 << 2)
+#define AR933X_PLL_CLOCK_CTRL_CPU_DIV_SHIFT 5
+#define AR933X_PLL_CLOCK_CTRL_CPU_DIV_MASK 0x3
+#define AR933X_PLL_CLOCK_CTRL_DDR_DIV_SHIFT 10
+#define AR933X_PLL_CLOCK_CTRL_DDR_DIV_MASK 0x3
+#define AR933X_PLL_CLOCK_CTRL_AHB_DIV_SHIFT 15
+#define AR933X_PLL_CLOCK_CTRL_AHB_DIV_MASK 0x7
+
+#define AR933X_RESET_REG_RESET_MODULE (AR71XX_RST_BLOCK_BASE + 0x1c)
+#define AR933X_RESET_REG_BOOTSTRAP (AR71XX_RST_BLOCK_BASE + 0xac)
+#define AR933X_RESET_WMAC (1 << 11)
+#define AR933X_RESET_USB_HOST (1 << 5)
+#define AR933X_RESET_USB_PHY (1 << 4)
+#define AR933X_RESET_USBSUS_OVERRIDE (1 << 3)
+
+#define AR933X_BOOTSTRAP_REF_CLK_40 (1 << 0)
+
+#define AR933X_PLL_VAL_1000 0x00110000
+#define AR933X_PLL_VAL_100 0x00001099
+#define AR933X_PLL_VAL_10 0x00991099
+
+#endif /* __AR93XX_REG_H__ */
Property changes on: trunk/sys/mips/atheros/ar933xreg.h
___________________________________________________________________
Added: svn:eol-style
## -0,0 +1 ##
+native
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+MidnightBSD=%H
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Added: trunk/sys/mips/atheros/ar934x_chip.c
===================================================================
--- trunk/sys/mips/atheros/ar934x_chip.c (rev 0)
+++ trunk/sys/mips/atheros/ar934x_chip.c 2018-05-26 21:55:02 UTC (rev 9987)
@@ -0,0 +1,334 @@
+/* $MidnightBSD$ */
+/*-
+ * Copyright (c) 2013 Adrian Chadd <adrian at FreeBSD.org>
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ */
+
+#include <sys/cdefs.h>
+__FBSDID("$FreeBSD: stable/10/sys/mips/atheros/ar934x_chip.c 253511 2013-07-21 03:56:57Z adrian $");
+
+#include "opt_ddb.h"
+
+#include <sys/param.h>
+#include <sys/conf.h>
+#include <sys/kernel.h>
+#include <sys/systm.h>
+#include <sys/bus.h>
+#include <sys/cons.h>
+#include <sys/kdb.h>
+#include <sys/reboot.h>
+
+#include <vm/vm.h>
+#include <vm/vm_page.h>
+
+#include <net/ethernet.h>
+
+#include <machine/clock.h>
+#include <machine/cpu.h>
+#include <machine/cpuregs.h>
+#include <machine/hwfunc.h>
+#include <machine/md_var.h>
+#include <machine/trap.h>
+#include <machine/vmparam.h>
+
+#include <mips/atheros/ar71xxreg.h>
+#include <mips/atheros/ar934xreg.h>
+
+#include <mips/atheros/ar71xx_cpudef.h>
+#include <mips/atheros/ar71xx_setup.h>
+
+#include <mips/atheros/ar71xx_chip.h>
+#include <mips/atheros/ar934x_chip.h>
+
+static void
+ar934x_chip_detect_mem_size(void)
+{
+}
+
+static uint32_t
+ar934x_get_pll_freq(uint32_t ref, uint32_t ref_div, uint32_t nint,
+ uint32_t nfrac, uint32_t frac, uint32_t out_div)
+{
+ uint64_t t;
+ uint32_t ret;
+
+ t = u_ar71xx_refclk;
+ t *= nint;
+ t = t / ref_div;
+ ret = t;
+
+ t = u_ar71xx_refclk;
+ t *= nfrac;
+ t = t / (ref_div * frac);
+ ret += t;
+
+ ret /= (1 << out_div);
+ return (ret);
+}
+
+static void
+ar934x_chip_detect_sys_frequency(void)
+{
+ uint32_t pll, out_div, ref_div, nint, nfrac, frac, clk_ctrl, postdiv;
+ uint32_t cpu_pll, ddr_pll;
+ uint32_t bootstrap;
+
+ bootstrap = ATH_READ_REG(AR934X_RESET_REG_BOOTSTRAP);
+ if (bootstrap & AR934X_BOOTSTRAP_REF_CLK_40)
+ u_ar71xx_refclk = 40 * 1000 * 1000;
+ else
+ u_ar71xx_refclk = 25 * 1000 * 1000;
+
+ pll = ATH_READ_REG(AR934X_SRIF_CPU_DPLL2_REG);
+ if (pll & AR934X_SRIF_DPLL2_LOCAL_PLL) {
+ out_div = (pll >> AR934X_SRIF_DPLL2_OUTDIV_SHIFT) &
+ AR934X_SRIF_DPLL2_OUTDIV_MASK;
+ pll = ATH_READ_REG(AR934X_SRIF_CPU_DPLL1_REG);
+ nint = (pll >> AR934X_SRIF_DPLL1_NINT_SHIFT) &
+ AR934X_SRIF_DPLL1_NINT_MASK;
+ nfrac = pll & AR934X_SRIF_DPLL1_NFRAC_MASK;
+ ref_div = (pll >> AR934X_SRIF_DPLL1_REFDIV_SHIFT) &
+ AR934X_SRIF_DPLL1_REFDIV_MASK;
+ frac = 1 << 18;
+ } else {
+ pll = ATH_READ_REG(AR934X_PLL_CPU_CONFIG_REG);
+ out_div = (pll >> AR934X_PLL_CPU_CONFIG_OUTDIV_SHIFT) &
+ AR934X_PLL_CPU_CONFIG_OUTDIV_MASK;
+ ref_div = (pll >> AR934X_PLL_CPU_CONFIG_REFDIV_SHIFT) &
+ AR934X_PLL_CPU_CONFIG_REFDIV_MASK;
+ nint = (pll >> AR934X_PLL_CPU_CONFIG_NINT_SHIFT) &
+ AR934X_PLL_CPU_CONFIG_NINT_MASK;
+ nfrac = (pll >> AR934X_PLL_CPU_CONFIG_NFRAC_SHIFT) &
+ AR934X_PLL_CPU_CONFIG_NFRAC_MASK;
+ frac = 1 << 6;
+ }
+
+ cpu_pll = ar934x_get_pll_freq(u_ar71xx_refclk, ref_div, nint,
+ nfrac, frac, out_div);
+
+ pll = ATH_READ_REG(AR934X_SRIF_DDR_DPLL2_REG);
+ if (pll & AR934X_SRIF_DPLL2_LOCAL_PLL) {
+ out_div = (pll >> AR934X_SRIF_DPLL2_OUTDIV_SHIFT) &
+ AR934X_SRIF_DPLL2_OUTDIV_MASK;
+ pll = ATH_READ_REG(AR934X_SRIF_DDR_DPLL1_REG);
+ nint = (pll >> AR934X_SRIF_DPLL1_NINT_SHIFT) &
+ AR934X_SRIF_DPLL1_NINT_MASK;
+ nfrac = pll & AR934X_SRIF_DPLL1_NFRAC_MASK;
+ ref_div = (pll >> AR934X_SRIF_DPLL1_REFDIV_SHIFT) &
+ AR934X_SRIF_DPLL1_REFDIV_MASK;
+ frac = 1 << 18;
+ } else {
+ pll = ATH_READ_REG(AR934X_PLL_DDR_CONFIG_REG);
+ out_div = (pll >> AR934X_PLL_DDR_CONFIG_OUTDIV_SHIFT) &
+ AR934X_PLL_DDR_CONFIG_OUTDIV_MASK;
+ ref_div = (pll >> AR934X_PLL_DDR_CONFIG_REFDIV_SHIFT) &
+ AR934X_PLL_DDR_CONFIG_REFDIV_MASK;
+ nint = (pll >> AR934X_PLL_DDR_CONFIG_NINT_SHIFT) &
+ AR934X_PLL_DDR_CONFIG_NINT_MASK;
+ nfrac = (pll >> AR934X_PLL_DDR_CONFIG_NFRAC_SHIFT) &
+ AR934X_PLL_DDR_CONFIG_NFRAC_MASK;
+ frac = 1 << 10;
+ }
+
+ ddr_pll = ar934x_get_pll_freq(u_ar71xx_refclk, ref_div, nint,
+ nfrac, frac, out_div);
+
+ clk_ctrl = ATH_READ_REG(AR934X_PLL_CPU_DDR_CLK_CTRL_REG);
+
+ postdiv = (clk_ctrl >> AR934X_PLL_CPU_DDR_CLK_CTRL_CPU_POST_DIV_SHIFT) &
+ AR934X_PLL_CPU_DDR_CLK_CTRL_CPU_POST_DIV_MASK;
+
+ if (clk_ctrl & AR934X_PLL_CPU_DDR_CLK_CTRL_CPU_PLL_BYPASS)
+ u_ar71xx_cpu_freq = u_ar71xx_refclk;
+ else if (clk_ctrl & AR934X_PLL_CPU_DDR_CLK_CTRL_CPUCLK_FROM_CPUPLL)
+ u_ar71xx_cpu_freq = cpu_pll / (postdiv + 1);
+ else
+ u_ar71xx_cpu_freq = ddr_pll / (postdiv + 1);
+
+ postdiv = (clk_ctrl >> AR934X_PLL_CPU_DDR_CLK_CTRL_DDR_POST_DIV_SHIFT) &
+ AR934X_PLL_CPU_DDR_CLK_CTRL_DDR_POST_DIV_MASK;
+
+ if (clk_ctrl & AR934X_PLL_CPU_DDR_CLK_CTRL_DDR_PLL_BYPASS)
+ u_ar71xx_ddr_freq = u_ar71xx_refclk;
+ else if (clk_ctrl & AR934X_PLL_CPU_DDR_CLK_CTRL_DDRCLK_FROM_DDRPLL)
+ u_ar71xx_ddr_freq = ddr_pll / (postdiv + 1);
+ else
+ u_ar71xx_ddr_freq = cpu_pll / (postdiv + 1);
+
+ postdiv = (clk_ctrl >> AR934X_PLL_CPU_DDR_CLK_CTRL_AHB_POST_DIV_SHIFT) &
+ AR934X_PLL_CPU_DDR_CLK_CTRL_AHB_POST_DIV_MASK;
+
+ if (clk_ctrl & AR934X_PLL_CPU_DDR_CLK_CTRL_AHB_PLL_BYPASS)
+ u_ar71xx_ahb_freq = u_ar71xx_refclk;
+ else if (clk_ctrl & AR934X_PLL_CPU_DDR_CLK_CTRL_AHBCLK_FROM_DDRPLL)
+ u_ar71xx_ahb_freq = ddr_pll / (postdiv + 1);
+ else
+ u_ar71xx_ahb_freq = cpu_pll / (postdiv + 1);
+
+ u_ar71xx_wdt_freq = u_ar71xx_refclk;
+ u_ar71xx_uart_freq = u_ar71xx_refclk;
+}
+
+static void
+ar934x_chip_device_stop(uint32_t mask)
+{
+ uint32_t reg;
+
+ reg = ATH_READ_REG(AR934X_RESET_REG_RESET_MODULE);
+ ATH_WRITE_REG(AR934X_RESET_REG_RESET_MODULE, reg | mask);
+}
+
+static void
+ar934x_chip_device_start(uint32_t mask)
+{
+ uint32_t reg;
+
+ reg = ATH_READ_REG(AR934X_RESET_REG_RESET_MODULE);
+ ATH_WRITE_REG(AR934X_RESET_REG_RESET_MODULE, reg & ~mask);
+}
+
+static int
+ar934x_chip_device_stopped(uint32_t mask)
+{
+ uint32_t reg;
+
+ reg = ATH_READ_REG(AR934X_RESET_REG_RESET_MODULE);
+ return ((reg & mask) == mask);
+}
+
+static void
+ar934x_chip_set_mii_speed(uint32_t unit, uint32_t speed)
+{
+
+ /* XXX TODO */
+ return;
+}
+
+/*
+ * XXX TODO !!
+ */
+static void
+ar934x_chip_set_pll_ge(int unit, int speed, uint32_t pll)
+{
+
+ switch (unit) {
+ case 0:
+ /* XXX TODO */
+ break;
+ case 1:
+ /* XXX TODO */
+ break;
+ default:
+ printf("%s: invalid PLL set for arge unit: %d\n",
+ __func__, unit);
+ return;
+ }
+}
+
+static void
+ar934x_chip_ddr_flush_ge(int unit)
+{
+
+ switch (unit) {
+ case 0:
+ ar71xx_ddr_flush(AR934X_DDR_REG_FLUSH_GE0);
+ break;
+ case 1:
+ ar71xx_ddr_flush(AR934X_DDR_REG_FLUSH_GE1);
+ break;
+ default:
+ printf("%s: invalid DDR flush for arge unit: %d\n",
+ __func__, unit);
+ return;
+ }
+}
+
+static void
+ar934x_chip_ddr_flush_ip2(void)
+{
+
+ ar71xx_ddr_flush(AR934X_DDR_REG_FLUSH_WMAC);
+}
+
+static uint32_t
+ar934x_chip_get_eth_pll(unsigned int mac, int speed)
+{
+#if 0
+ uint32_t pll;
+
+ switch (speed) {
+ case 10:
+ pll = AR933X_PLL_VAL_10;
+ break;
+ case 100:
+ pll = AR933X_PLL_VAL_100;
+ break;
+ case 1000:
+ pll = AR933X_PLL_VAL_1000;
+ break;
+ default:
+ printf("%s%d: invalid speed %d\n", __func__, mac, speed);
+ pll = 0;
+ }
+ return (pll);
+#endif
+ return (0);
+}
+
+static void
+ar934x_chip_init_usb_peripheral(void)
+{
+ uint32_t reg;
+
+ reg = ATH_READ_REG(AR934X_RESET_REG_BOOTSTRAP);
+ if (reg & AR934X_BOOTSTRAP_USB_MODE_DEVICE)
+ return;
+
+ ar71xx_device_stop(AR934X_RESET_USBSUS_OVERRIDE);
+ DELAY(100);
+
+ ar71xx_device_start(AR934X_RESET_USB_PHY);
+ DELAY(100);
+
+ ar71xx_device_start(AR934X_RESET_USB_PHY_ANALOG);
+ DELAY(100);
+
+ ar71xx_device_start(AR934X_RESET_USB_HOST);
+ DELAY(100);
+}
+
+struct ar71xx_cpu_def ar934x_chip_def = {
+ &ar934x_chip_detect_mem_size,
+ &ar934x_chip_detect_sys_frequency,
+ &ar934x_chip_device_stop,
+ &ar934x_chip_device_start,
+ &ar934x_chip_device_stopped,
+ &ar934x_chip_set_pll_ge,
+ &ar934x_chip_set_mii_speed,
+ &ar71xx_chip_set_mii_if,
+ &ar934x_chip_ddr_flush_ge,
+ &ar934x_chip_get_eth_pll,
+ &ar934x_chip_ddr_flush_ip2,
+ &ar934x_chip_init_usb_peripheral
+};
Property changes on: trunk/sys/mips/atheros/ar934x_chip.c
___________________________________________________________________
Added: svn:eol-style
## -0,0 +1 ##
+native
\ No newline at end of property
Added: svn:keywords
## -0,0 +1 ##
+MidnightBSD=%H
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+text/plain
\ No newline at end of property
Added: trunk/sys/mips/atheros/ar934x_chip.h
===================================================================
--- trunk/sys/mips/atheros/ar934x_chip.h (rev 0)
+++ trunk/sys/mips/atheros/ar934x_chip.h 2018-05-26 21:55:02 UTC (rev 9987)
@@ -0,0 +1,35 @@
+/* $MidnightBSD$ */
+/*-
+ * Copyright (c) 2013 Adrian Chadd <adrian at FreeBSD.org>
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ */
+
+/* $FreeBSD: stable/10/sys/mips/atheros/ar934x_chip.h 253511 2013-07-21 03:56:57Z adrian $ */
+
+#ifndef __AR934X_CHIP_H__
+#define __AR934X_CHIP_H__
+
+extern struct ar71xx_cpu_def ar934x_chip_def;
+
+#endif
Property changes on: trunk/sys/mips/atheros/ar934x_chip.h
___________________________________________________________________
Added: svn:eol-style
## -0,0 +1 ##
+native
\ No newline at end of property
Added: svn:keywords
## -0,0 +1 ##
+MidnightBSD=%H
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+text/plain
\ No newline at end of property
Added: trunk/sys/mips/atheros/ar934xreg.h
===================================================================
--- trunk/sys/mips/atheros/ar934xreg.h (rev 0)
+++ trunk/sys/mips/atheros/ar934xreg.h 2018-05-26 21:55:02 UTC (rev 9987)
@@ -0,0 +1,212 @@
+/* $MidnightBSD$ */
+/*-
+ * Copyright (c) 2013 Adrian Chadd <adrian at FreeBSD.org>
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ * $FreeBSD: stable/10/sys/mips/atheros/ar934xreg.h 261455 2014-02-04 03:36:42Z eadler $
+ */
+
+#ifndef __AR934X_REG_H__
+#define __AR934X_REG_H__
+
+#define AR934X_GMAC_BASE (AR71XX_APB_BASE + 0x00070000)
+#define AR934X_GMAC_SIZE 0x14
+#define AR934X_WMAC_BASE (AR71XX_APB_BASE + 0x00100000)
+#define AR934X_WMAC_SIZE 0x20000
+#define AR934X_EHCI_BASE 0x1b000000
+#define AR934X_EHCI_SIZE 0x200
+#define AR934X_SRIF_BASE (AR71XX_APB_BASE + 0x00116000)
+#define AR934X_SRIF_SIZE 0x1000
+
+/* AR934x GMAC configuration */
+#define AR934X_GMAC_REG_ETH_CFG (AR934X_GMAC_BASE + 0x00)
+
+#define AR934X_ETH_CFG_RGMII_GMAC0 (1 << 0)
+#define AR934X_ETH_CFG_MII_GMAC0 (1 << 1)
+#define AR934X_ETH_CFG_GMII_GMAC0 (1 << 2)
+#define AR934X_ETH_CFG_MII_GMAC0_MASTER (1 << 3)
+#define AR934X_ETH_CFG_MII_GMAC0_SLAVE (1 << 4)
+#define AR934X_ETH_CFG_MII_GMAC0_ERR_EN (1 << 5)
+#define AR934X_ETH_CFG_SW_ONLY_MODE (1 << 6)
+#define AR934X_ETH_CFG_SW_PHY_SWAP (1 << 7)
+#define AR934X_ETH_CFG_SW_APB_ACCESS (1 << 9)
+#define AR934X_ETH_CFG_RMII_GMAC0 (1 << 10)
+#define AR933X_ETH_CFG_MII_CNTL_SPEED (1 << 11)
+#define AR934X_ETH_CFG_RMII_GMAC0_MASTER (1 << 12)
+#define AR934X_ETH_CFG_SW_ACC_MSB_FIRST (1 << 13)
+
+#define AR934X_DDR_REG_FLUSH_GE0 (AR71XX_APB_BASE + 0x9c)
+#define AR934X_DDR_REG_FLUSH_GE1 (AR71XX_APB_BASE + 0xa0)
+#define AR934X_DDR_REG_FLUSH_USB (AR71XX_APB_BASE + 0xa4)
+#define AR934X_DDR_REG_FLUSH_PCIE (AR71XX_APB_BASE + 0xa8)
+#define AR934X_DDR_REG_FLUSH_WMAC (AR71XX_APB_BASE + 0xac)
+
+#define AR934X_PLL_CPU_CONFIG_REG (AR71XX_PLL_CPU_BASE + 0x00)
+#define AR934X_PLL_DDR_CONFIG_REG (AR71XX_PLL_CPU_BASE + 0x04)
+#define AR934X_PLL_CPU_DDR_CLK_CTRL_REG (AR71XX_PLL_CPU_BASE + 0x08)
+#define AR934X_PLL_SWITCH_CLOCK_CONTROL_REG (AR71XX_PLL_CPU_BASE + 0x24)
+#define AR934X_PLL_SWITCH_CLOCK_CONTROL_MDIO_CLK_SEL (1 << 6)
+#define AR934X_PLL_ETH_XMII_CONTROL_REG (AR71XX_PLL_CPU_BASE + 0x2c)
+
+#define AR934X_PLL_CPU_CONFIG_NFRAC_SHIFT 0
+#define AR934X_PLL_CPU_CONFIG_NFRAC_MASK 0x3f
+#define AR934X_PLL_CPU_CONFIG_NINT_SHIFT 6
+#define AR934X_PLL_CPU_CONFIG_NINT_MASK 0x3f
+#define AR934X_PLL_CPU_CONFIG_REFDIV_SHIFT 12
+#define AR934X_PLL_CPU_CONFIG_REFDIV_MASK 0x1f
+#define AR934X_PLL_CPU_CONFIG_OUTDIV_SHIFT 19
+#define AR934X_PLL_CPU_CONFIG_OUTDIV_MASK 0x3
+
+#define AR934X_PLL_DDR_CONFIG_NFRAC_SHIFT 0
+#define AR934X_PLL_DDR_CONFIG_NFRAC_MASK 0x3ff
+#define AR934X_PLL_DDR_CONFIG_NINT_SHIFT 10
+#define AR934X_PLL_DDR_CONFIG_NINT_MASK 0x3f
+#define AR934X_PLL_DDR_CONFIG_REFDIV_SHIFT 16
+#define AR934X_PLL_DDR_CONFIG_REFDIV_MASK 0x1f
+#define AR934X_PLL_DDR_CONFIG_OUTDIV_SHIFT 23
+#define AR934X_PLL_DDR_CONFIG_OUTDIV_MASK 0x7
+
+#define AR934X_PLL_CPU_DDR_CLK_CTRL_CPU_PLL_BYPASS (1 << 2)
+#define AR934X_PLL_CPU_DDR_CLK_CTRL_DDR_PLL_BYPASS (1 << 3)
+#define AR934X_PLL_CPU_DDR_CLK_CTRL_AHB_PLL_BYPASS (1 << 4)
+#define AR934X_PLL_CPU_DDR_CLK_CTRL_CPU_POST_DIV_SHIFT 5
+#define AR934X_PLL_CPU_DDR_CLK_CTRL_CPU_POST_DIV_MASK 0x1f
+#define AR934X_PLL_CPU_DDR_CLK_CTRL_DDR_POST_DIV_SHIFT 10
+#define AR934X_PLL_CPU_DDR_CLK_CTRL_DDR_POST_DIV_MASK 0x1f
+#define AR934X_PLL_CPU_DDR_CLK_CTRL_AHB_POST_DIV_SHIFT 15
+#define AR934X_PLL_CPU_DDR_CLK_CTRL_AHB_POST_DIV_MASK 0x1f
+#define AR934X_PLL_CPU_DDR_CLK_CTRL_CPUCLK_FROM_CPUPLL (1 << 20)
+#define AR934X_PLL_CPU_DDR_CLK_CTRL_DDRCLK_FROM_DDRPLL (1 << 21)
+#define AR934X_PLL_CPU_DDR_CLK_CTRL_AHBCLK_FROM_DDRPLL (1 << 24)
+
+#define AR934X_RESET_REG_RESET_MODULE (AR71XX_RST_BLOCK_BASE + 0x1c)
+#define AR934X_RESET_REG_BOOTSTRAP (AR71XX_RST_BLOCK_BASE + 0xb0)
+#define AR934X_RESET_REG_PCIE_WMAC_INT_STATUS (AR71XX_RST_BLOCK_BASE + 0xac)
+
+#define AR934X_RESET_HOST (1U << 31)
+#define AR934X_RESET_SLIC (1 << 30)
+#define AR934X_RESET_HDMA (1 << 29)
+#define AR934X_RESET_EXTERNAL (1 << 28)
+#define AR934X_RESET_RTC (1 << 27)
+#define AR934X_RESET_PCIE_EP_INT (1 << 26)
+#define AR934X_RESET_CHKSUM_ACC (1 << 25)
+#define AR934X_RESET_FULL_CHIP (1 << 24)
+#define AR934X_RESET_GE1_MDIO (1 << 23)
+#define AR934X_RESET_GE0_MDIO (1 << 22)
+#define AR934X_RESET_CPU_NMI (1 << 21)
+#define AR934X_RESET_CPU_COLD (1 << 20)
+#define AR934X_RESET_HOST_RESET_INT (1 << 19)
+#define AR934X_RESET_PCIE_EP (1 << 18)
+#define AR934X_RESET_UART1 (1 << 17)
+#define AR934X_RESET_DDR (1 << 16)
+#define AR934X_RESET_USB_PHY_PLL_PWD_EXT (1 << 15)
+#define AR934X_RESET_NANDF (1 << 14)
+#define AR934X_RESET_GE1_MAC (1 << 13)
+#define AR934X_RESET_ETH_SWITCH_ANALOG (1 << 12)
+#define AR934X_RESET_USB_PHY_ANALOG (1 << 11)
+#define AR934X_RESET_HOST_DMA_INT (1 << 10)
+#define AR934X_RESET_GE0_MAC (1 << 9)
+#define AR934X_RESET_ETH_SWITCH (1 << 8)
+#define AR934X_RESET_PCIE_PHY (1 << 7)
+#define AR934X_RESET_PCIE (1 << 6)
+#define AR934X_RESET_USB_HOST (1 << 5)
+#define AR934X_RESET_USB_PHY (1 << 4)
+#define AR934X_RESET_USBSUS_OVERRIDE (1 << 3)
+#define AR934X_RESET_LUT (1 << 2)
+#define AR934X_RESET_MBOX (1 << 1)
+#define AR934X_RESET_I2S (1 << 0)
+
+#define AR934X_BOOTSTRAP_SW_OPTION8 (1 << 23)
+#define AR934X_BOOTSTRAP_SW_OPTION7 (1 << 22)
+#define AR934X_BOOTSTRAP_SW_OPTION6 (1 << 21)
+#define AR934X_BOOTSTRAP_SW_OPTION5 (1 << 20)
+#define AR934X_BOOTSTRAP_SW_OPTION4 (1 << 19)
+#define AR934X_BOOTSTRAP_SW_OPTION3 (1 << 18)
+#define AR934X_BOOTSTRAP_SW_OPTION2 (1 << 17)
+#define AR934X_BOOTSTRAP_SW_OPTION1 (1 << 16)
+#define AR934X_BOOTSTRAP_USB_MODE_DEVICE (1 << 7)
+#define AR934X_BOOTSTRAP_PCIE_RC (1 << 6)
+#define AR934X_BOOTSTRAP_EJTAG_MODE (1 << 5)
+#define AR934X_BOOTSTRAP_REF_CLK_40 (1 << 4)
+#define AR934X_BOOTSTRAP_BOOT_FROM_SPI (1 << 2)
+#define AR934X_BOOTSTRAP_SDRAM_DISABLED (1 << 1)
+#define AR934X_BOOTSTRAP_DDR1 (1 << 0)
+
+#define AR934X_PCIE_WMAC_INT_WMAC_MISC (1 << 0)
+#define AR934X_PCIE_WMAC_INT_WMAC_TX (1 << 1)
+#define AR934X_PCIE_WMAC_INT_WMAC_RXLP (1 << 2)
+#define AR934X_PCIE_WMAC_INT_WMAC_RXHP (1 << 3)
+#define AR934X_PCIE_WMAC_INT_PCIE_RC (1 << 4)
+#define AR934X_PCIE_WMAC_INT_PCIE_RC0 (1 << 5)
+#define AR934X_PCIE_WMAC_INT_PCIE_RC1 (1 << 6)
+#define AR934X_PCIE_WMAC_INT_PCIE_RC2 (1 << 7)
+#define AR934X_PCIE_WMAC_INT_PCIE_RC3 (1 << 8)
+#define AR934X_PCIE_WMAC_INT_WMAC_ALL \
+ (AR934X_PCIE_WMAC_INT_WMAC_MISC | AR934X_PCIE_WMAC_INT_WMAC_TX | \
+ AR934X_PCIE_WMAC_INT_WMAC_RXLP | AR934X_PCIE_WMAC_INT_WMAC_RXHP)
+
+#define AR934X_PCIE_WMAC_INT_PCIE_ALL \
+ (AR934X_PCIE_WMAC_INT_PCIE_RC | AR934X_PCIE_WMAC_INT_PCIE_RC0 | \
+ AR934X_PCIE_WMAC_INT_PCIE_RC1 | AR934X_PCIE_WMAC_INT_PCIE_RC2 | \
+ AR934X_PCIE_WMAC_INT_PCIE_RC3)
+
+#define REV_ID_MAJOR_AR9341 0x0120
+#define REV_ID_MAJOR_AR9342 0x1120
+#define REV_ID_MAJOR_AR9344 0x2120
+
+#define AR934X_REV_ID_REVISION_MASK 0xf
+
+/*
+ * GPIO block
+ */
+#define AR934X_GPIO_REG_FUNC 0x6c
+#define AR934X_GPIO_COUNT 23
+
+/*
+ * SRIF block
+ */
+#define AR934X_SRIF_CPU_DPLL1_REG (AR934X_SRIF_BASE + 0x1c0)
+#define AR934X_SRIF_CPU_DPLL2_REG (AR934X_SRIF_BASE + 0x1c4)
+#define AR934X_SRIF_CPU_DPLL3_REG (AR934X_SRIF_BASE + 0x1c8)
+
+#define AR934X_SRIF_DDR_DPLL1_REG (AR934X_SRIF_BASE + 0x240)
+#define AR934X_SRIF_DDR_DPLL2_REG (AR934X_SRIF_BASE + 0x244)
+#define AR934X_SRIF_DDR_DPLL3_REG (AR934X_SRIF_BASE + 0x248)
+
+#define AR934X_SRIF_DPLL1_REFDIV_SHIFT 27
+#define AR934X_SRIF_DPLL1_REFDIV_MASK 0x1f
+#define AR934X_SRIF_DPLL1_NINT_SHIFT 18
+#define AR934X_SRIF_DPLL1_NINT_MASK 0x1ff
+#define AR934X_SRIF_DPLL1_NFRAC_MASK 0x0003ffff
+
+#define AR934X_SRIF_DPLL2_LOCAL_PLL (1 << 30)
+#define AR934X_SRIF_DPLL2_OUTDIV_SHIFT 13
+#define AR934X_SRIF_DPLL2_OUTDIV_MASK 0x7
+
+/* XXX verify! */
+#define AR934X_PLL_VAL_1000 0x16000000
+#define AR934X_PLL_VAL_100 0x00000101
+#define AR934X_PLL_VAL_10 0x00001616
+
+#endif /* __AR934X_REG_H__ */
Property changes on: trunk/sys/mips/atheros/ar934xreg.h
___________________________________________________________________
Added: svn:eol-style
## -0,0 +1 ##
+native
\ No newline at end of property
Added: svn:keywords
## -0,0 +1 ##
+MidnightBSD=%H
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+text/plain
\ No newline at end of property
Added: trunk/sys/mips/atheros/files.ar71xx
===================================================================
--- trunk/sys/mips/atheros/files.ar71xx (rev 0)
+++ trunk/sys/mips/atheros/files.ar71xx 2018-05-26 21:55:02 UTC (rev 9987)
@@ -0,0 +1,31 @@
+# $FreeBSD: stable/10/sys/mips/atheros/files.ar71xx 253511 2013-07-21 03:56:57Z adrian $
+
+mips/atheros/apb.c standard
+mips/atheros/ar71xx_gpio.c optional gpio
+mips/atheros/ar71xx_machdep.c standard
+mips/atheros/ar71xx_ehci.c optional ehci
+mips/atheros/ar71xx_ohci.c optional ohci
+mips/atheros/ar71xx_pci.c optional ar71xx_pci pci
+mips/atheros/ar724x_pci.c optional ar724x_pci pci
+mips/atheros/ar71xx_pci_bus_space.c optional pci
+mips/atheros/ar71xx_spi.c optional ar71xx_spi
+mips/atheros/pcf2123_rtc.c optional pcf2123_rtc ar71xx_spi
+mips/atheros/ar71xx_wdog.c optional ar71xx_wdog
+mips/atheros/if_arge.c optional arge
+mips/atheros/uart_bus_ar71xx.c optional uart_ar71xx
+mips/atheros/uart_cpu_ar71xx.c optional uart_ar71xx
+mips/atheros/uart_bus_ar933x.c optional uart_ar933x
+mips/atheros/uart_cpu_ar933x.c optional uart_ar933x
+mips/atheros/uart_dev_ar933x.c optional uart_ar933x
+mips/atheros/ar71xx_bus_space_reversed.c standard
+mips/mips/intr_machdep.c standard
+mips/mips/tick.c standard
+mips/atheros/ar71xx_setup.c standard
+mips/atheros/ar71xx_chip.c standard
+mips/atheros/ar724x_chip.c standard
+mips/atheros/ar91xx_chip.c standard
+mips/atheros/ar933x_chip.c standard
+mips/atheros/ar934x_chip.c standard
+mips/atheros/ar71xx_fixup.c optional ar71xx_ath_eeprom
+
+dev/hwpmc/hwpmc_mips24k.c optional hwpmc_mips24k
Property changes on: trunk/sys/mips/atheros/files.ar71xx
___________________________________________________________________
Added: mnbsd:nokeywords
## -0,0 +1 ##
+MidnightBSD=%H
\ No newline at end of property
Added: trunk/sys/mips/atheros/if_arge.c
===================================================================
--- trunk/sys/mips/atheros/if_arge.c (rev 0)
+++ trunk/sys/mips/atheros/if_arge.c 2018-05-26 21:55:02 UTC (rev 9987)
@@ -0,0 +1,2243 @@
+/* $MidnightBSD$ */
+/*-
+ * Copyright (c) 2009, Oleksandr Tymoshenko
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice unmodified, this list of conditions, and the following
+ * disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ */
+
+#include <sys/cdefs.h>
+__FBSDID("$FreeBSD: stable/10/sys/mips/atheros/if_arge.c 322725 2017-08-20 19:21:06Z delphij $");
+
+/*
+ * AR71XX gigabit ethernet driver
+ */
+#ifdef HAVE_KERNEL_OPTION_HEADERS
+#include "opt_device_polling.h"
+#endif
+
+#include "opt_arge.h"
+
+#include <sys/param.h>
+#include <sys/endian.h>
+#include <sys/systm.h>
+#include <sys/sockio.h>
+#include <sys/mbuf.h>
+#include <sys/malloc.h>
+#include <sys/kernel.h>
+#include <sys/module.h>
+#include <sys/socket.h>
+#include <sys/taskqueue.h>
+#include <sys/sysctl.h>
+
+#include <net/if.h>
+#include <net/if_arp.h>
+#include <net/ethernet.h>
+#include <net/if_dl.h>
+#include <net/if_media.h>
+#include <net/if_types.h>
+
+#include <net/bpf.h>
+
+#include <machine/bus.h>
+#include <machine/cache.h>
+#include <machine/resource.h>
+#include <vm/vm_param.h>
+#include <vm/vm.h>
+#include <vm/pmap.h>
+#include <machine/pmap.h>
+#include <sys/bus.h>
+#include <sys/rman.h>
+
+#include <dev/mii/mii.h>
+#include <dev/mii/miivar.h>
+
+#include <dev/pci/pcireg.h>
+#include <dev/pci/pcivar.h>
+
+#include "opt_arge.h"
+
+#if defined(ARGE_MDIO)
+#include <dev/etherswitch/mdio.h>
+#include <dev/etherswitch/miiproxy.h>
+#include "mdio_if.h"
+#endif
+
+
+MODULE_DEPEND(arge, ether, 1, 1, 1);
+MODULE_DEPEND(arge, miibus, 1, 1, 1);
+MODULE_VERSION(arge, 1);
+
+#include "miibus_if.h"
+
+#include <mips/atheros/ar71xxreg.h>
+#include <mips/atheros/if_argevar.h>
+#include <mips/atheros/ar71xx_setup.h>
+#include <mips/atheros/ar71xx_cpudef.h>
+
+typedef enum {
+ ARGE_DBG_MII = 0x00000001,
+ ARGE_DBG_INTR = 0x00000002,
+ ARGE_DBG_TX = 0x00000004,
+ ARGE_DBG_RX = 0x00000008,
+ ARGE_DBG_ERR = 0x00000010,
+ ARGE_DBG_RESET = 0x00000020,
+ ARGE_DBG_PLL = 0x00000040,
+} arge_debug_flags;
+
+static const char * arge_miicfg_str[] = {
+ "NONE",
+ "GMII",
+ "MII",
+ "RGMII",
+ "RMII"
+};
+
+#ifdef ARGE_DEBUG
+#define ARGEDEBUG(_sc, _m, ...) \
+ do { \
+ if ((_m) & (_sc)->arge_debug) \
+ device_printf((_sc)->arge_dev, __VA_ARGS__); \
+ } while (0)
+#else
+#define ARGEDEBUG(_sc, _m, ...)
+#endif
+
+static int arge_attach(device_t);
+static int arge_detach(device_t);
+static void arge_flush_ddr(struct arge_softc *);
+static int arge_ifmedia_upd(struct ifnet *);
+static void arge_ifmedia_sts(struct ifnet *, struct ifmediareq *);
+static int arge_ioctl(struct ifnet *, u_long, caddr_t);
+static void arge_init(void *);
+static void arge_init_locked(struct arge_softc *);
+static void arge_link_task(void *, int);
+static void arge_update_link_locked(struct arge_softc *sc);
+static void arge_set_pll(struct arge_softc *, int, int);
+static int arge_miibus_readreg(device_t, int, int);
+static void arge_miibus_statchg(device_t);
+static int arge_miibus_writereg(device_t, int, int, int);
+static int arge_probe(device_t);
+static void arge_reset_dma(struct arge_softc *);
+static int arge_resume(device_t);
+static int arge_rx_ring_init(struct arge_softc *);
+static void arge_rx_ring_free(struct arge_softc *sc);
+static int arge_tx_ring_init(struct arge_softc *);
+static void arge_tx_ring_free(struct arge_softc *);
+#ifdef DEVICE_POLLING
+static int arge_poll(struct ifnet *, enum poll_cmd, int);
+#endif
+static int arge_shutdown(device_t);
+static void arge_start(struct ifnet *);
+static void arge_start_locked(struct ifnet *);
+static void arge_stop(struct arge_softc *);
+static int arge_suspend(device_t);
+
+static int arge_rx_locked(struct arge_softc *);
+static void arge_tx_locked(struct arge_softc *);
+static void arge_intr(void *);
+static int arge_intr_filter(void *);
+static void arge_tick(void *);
+
+static void arge_hinted_child(device_t bus, const char *dname, int dunit);
+
+/*
+ * ifmedia callbacks for multiPHY MAC
+ */
+void arge_multiphy_mediastatus(struct ifnet *, struct ifmediareq *);
+int arge_multiphy_mediachange(struct ifnet *);
+
+static void arge_dmamap_cb(void *, bus_dma_segment_t *, int, int);
+static int arge_dma_alloc(struct arge_softc *);
+static void arge_dma_free(struct arge_softc *);
+static int arge_newbuf(struct arge_softc *, int);
+static __inline void arge_fixup_rx(struct mbuf *);
+
+static device_method_t arge_methods[] = {
+ /* Device interface */
+ DEVMETHOD(device_probe, arge_probe),
+ DEVMETHOD(device_attach, arge_attach),
+ DEVMETHOD(device_detach, arge_detach),
+ DEVMETHOD(device_suspend, arge_suspend),
+ DEVMETHOD(device_resume, arge_resume),
+ DEVMETHOD(device_shutdown, arge_shutdown),
+
+ /* MII interface */
+ DEVMETHOD(miibus_readreg, arge_miibus_readreg),
+ DEVMETHOD(miibus_writereg, arge_miibus_writereg),
+ DEVMETHOD(miibus_statchg, arge_miibus_statchg),
+
+ /* bus interface */
+ DEVMETHOD(bus_add_child, device_add_child_ordered),
+ DEVMETHOD(bus_hinted_child, arge_hinted_child),
+
+ DEVMETHOD_END
+};
+
+static driver_t arge_driver = {
+ "arge",
+ arge_methods,
+ sizeof(struct arge_softc)
+};
+
+static devclass_t arge_devclass;
+
+DRIVER_MODULE(arge, nexus, arge_driver, arge_devclass, 0, 0);
+DRIVER_MODULE(miibus, arge, miibus_driver, miibus_devclass, 0, 0);
+
+#if defined(ARGE_MDIO)
+static int argemdio_probe(device_t);
+static int argemdio_attach(device_t);
+static int argemdio_detach(device_t);
+
+/*
+ * Declare an additional, separate driver for accessing the MDIO bus.
+ */
+static device_method_t argemdio_methods[] = {
+ /* Device interface */
+ DEVMETHOD(device_probe, argemdio_probe),
+ DEVMETHOD(device_attach, argemdio_attach),
+ DEVMETHOD(device_detach, argemdio_detach),
+
+ /* bus interface */
+ DEVMETHOD(bus_add_child, device_add_child_ordered),
+
+ /* MDIO access */
+ DEVMETHOD(mdio_readreg, arge_miibus_readreg),
+ DEVMETHOD(mdio_writereg, arge_miibus_writereg),
+};
+
+DEFINE_CLASS_0(argemdio, argemdio_driver, argemdio_methods,
+ sizeof(struct arge_softc));
+static devclass_t argemdio_devclass;
+
+DRIVER_MODULE(miiproxy, arge, miiproxy_driver, miiproxy_devclass, 0, 0);
+DRIVER_MODULE(argemdio, nexus, argemdio_driver, argemdio_devclass, 0, 0);
+DRIVER_MODULE(mdio, argemdio, mdio_driver, mdio_devclass, 0, 0);
+#endif
+
+/*
+ * RedBoot passes MAC address to entry point as environment
+ * variable. platfrom_start parses it and stores in this variable
+ */
+extern uint32_t ar711_base_mac[ETHER_ADDR_LEN];
+
+static struct mtx miibus_mtx;
+
+MTX_SYSINIT(miibus_mtx, &miibus_mtx, "arge mii lock", MTX_DEF);
+
+/*
+ * Flushes all
+ */
+static void
+arge_flush_ddr(struct arge_softc *sc)
+{
+
+ ar71xx_device_flush_ddr_ge(sc->arge_mac_unit);
+}
+
+static int
+arge_probe(device_t dev)
+{
+
+ device_set_desc(dev, "Atheros AR71xx built-in ethernet interface");
+ return (BUS_PROBE_NOWILDCARD);
+}
+
+static void
+arge_attach_sysctl(device_t dev)
+{
+ struct arge_softc *sc = device_get_softc(dev);
+ struct sysctl_ctx_list *ctx = device_get_sysctl_ctx(dev);
+ struct sysctl_oid *tree = device_get_sysctl_tree(dev);
+
+#ifdef ARGE_DEBUG
+ SYSCTL_ADD_INT(ctx, SYSCTL_CHILDREN(tree), OID_AUTO,
+ "debug", CTLFLAG_RW, &sc->arge_debug, 0,
+ "arge interface debugging flags");
+#endif
+
+ SYSCTL_ADD_UINT(ctx, SYSCTL_CHILDREN(tree), OID_AUTO,
+ "tx_pkts_aligned", CTLFLAG_RW, &sc->stats.tx_pkts_aligned, 0,
+ "number of TX aligned packets");
+
+ SYSCTL_ADD_UINT(ctx, SYSCTL_CHILDREN(tree), OID_AUTO,
+ "tx_pkts_unaligned", CTLFLAG_RW, &sc->stats.tx_pkts_unaligned,
+ 0, "number of TX unaligned packets");
+
+#ifdef ARGE_DEBUG
+ SYSCTL_ADD_UINT(ctx, SYSCTL_CHILDREN(tree), OID_AUTO, "tx_prod",
+ CTLFLAG_RW, &sc->arge_cdata.arge_tx_prod, 0, "");
+ SYSCTL_ADD_UINT(ctx, SYSCTL_CHILDREN(tree), OID_AUTO, "tx_cons",
+ CTLFLAG_RW, &sc->arge_cdata.arge_tx_cons, 0, "");
+ SYSCTL_ADD_UINT(ctx, SYSCTL_CHILDREN(tree), OID_AUTO, "tx_cnt",
+ CTLFLAG_RW, &sc->arge_cdata.arge_tx_cnt, 0, "");
+#endif
+}
+
+static void
+arge_reset_mac(struct arge_softc *sc)
+{
+ uint32_t reg;
+
+ /* Step 1. Soft-reset MAC */
+ ARGE_SET_BITS(sc, AR71XX_MAC_CFG1, MAC_CFG1_SOFT_RESET);
+ DELAY(20);
+
+ /* Step 2. Punt the MAC core from the central reset register */
+ ar71xx_device_stop(sc->arge_mac_unit == 0 ? RST_RESET_GE0_MAC :
+ RST_RESET_GE1_MAC);
+ DELAY(100);
+ ar71xx_device_start(sc->arge_mac_unit == 0 ? RST_RESET_GE0_MAC :
+ RST_RESET_GE1_MAC);
+
+ /* Step 3. Reconfigure MAC block */
+ ARGE_WRITE(sc, AR71XX_MAC_CFG1,
+ MAC_CFG1_SYNC_RX | MAC_CFG1_RX_ENABLE |
+ MAC_CFG1_SYNC_TX | MAC_CFG1_TX_ENABLE);
+
+ reg = ARGE_READ(sc, AR71XX_MAC_CFG2);
+ reg |= MAC_CFG2_ENABLE_PADCRC | MAC_CFG2_LENGTH_FIELD ;
+ ARGE_WRITE(sc, AR71XX_MAC_CFG2, reg);
+
+ ARGE_WRITE(sc, AR71XX_MAC_MAX_FRAME_LEN, 1536);
+}
+
+static void
+arge_reset_miibus(struct arge_softc *sc)
+{
+
+ /* Reset MII bus */
+ ARGE_WRITE(sc, AR71XX_MAC_MII_CFG, MAC_MII_CFG_RESET);
+ DELAY(100);
+ ARGE_WRITE(sc, AR71XX_MAC_MII_CFG, MAC_MII_CFG_CLOCK_DIV_28);
+ DELAY(100);
+}
+
+static void
+arge_fetch_pll_config(struct arge_softc *sc)
+{
+ long int val;
+
+ if (resource_long_value(device_get_name(sc->arge_dev),
+ device_get_unit(sc->arge_dev),
+ "pll_10", &val) == 0) {
+ sc->arge_pllcfg.pll_10 = val;
+ device_printf(sc->arge_dev, "%s: pll_10 = 0x%x\n",
+ __func__, (int) val);
+ }
+ if (resource_long_value(device_get_name(sc->arge_dev),
+ device_get_unit(sc->arge_dev),
+ "pll_100", &val) == 0) {
+ sc->arge_pllcfg.pll_100 = val;
+ device_printf(sc->arge_dev, "%s: pll_100 = 0x%x\n",
+ __func__, (int) val);
+ }
+ if (resource_long_value(device_get_name(sc->arge_dev),
+ device_get_unit(sc->arge_dev),
+ "pll_1000", &val) == 0) {
+ sc->arge_pllcfg.pll_1000 = val;
+ device_printf(sc->arge_dev, "%s: pll_1000 = 0x%x\n",
+ __func__, (int) val);
+ }
+}
+
+static int
+arge_attach(device_t dev)
+{
+ struct ifnet *ifp;
+ struct arge_softc *sc;
+ int error = 0, rid;
+ uint32_t rnd;
+ int is_base_mac_empty, i;
+ uint32_t hint;
+ long eeprom_mac_addr = 0;
+ int miicfg = 0;
+ int readascii = 0;
+
+ sc = device_get_softc(dev);
+ sc->arge_dev = dev;
+ sc->arge_mac_unit = device_get_unit(dev);
+
+ /*
+ * Some units (eg the TP-Link WR-1043ND) do not have a convenient
+ * EEPROM location to read the ethernet MAC address from.
+ * OpenWRT simply snaffles it from a fixed location.
+ *
+ * Since multiple units seem to use this feature, include
+ * a method of setting the MAC address based on an flash location
+ * in CPU address space.
+ *
+ * Some vendors have decided to store the mac address as a literal
+ * string of 18 characters in xx:xx:xx:xx:xx:xx format instead of
+ * an array of numbers. Expose a hint to turn on this conversion
+ * feature via strtol()
+ */
+ if (resource_long_value(device_get_name(dev), device_get_unit(dev),
+ "eeprommac", &eeprom_mac_addr) == 0) {
+ int i;
+ const char *mac =
+ (const char *) MIPS_PHYS_TO_KSEG1(eeprom_mac_addr);
+ device_printf(dev, "Overriding MAC from EEPROM\n");
+ if (resource_int_value(device_get_name(dev), device_get_unit(dev),
+ "readascii", &readascii) == 0) {
+ device_printf(dev, "Vendor stores MAC in ASCII format\n");
+ for (i = 0; i < 6; i++) {
+ ar711_base_mac[i] = strtol(&(mac[i*3]), NULL, 16);
+ }
+ } else {
+ for (i = 0; i < 6; i++) {
+ ar711_base_mac[i] = mac[i];
+ }
+ }
+ }
+
+ KASSERT(((sc->arge_mac_unit == 0) || (sc->arge_mac_unit == 1)),
+ ("if_arge: Only MAC0 and MAC1 supported"));
+
+ /*
+ * Fetch the PLL configuration.
+ */
+ arge_fetch_pll_config(sc);
+
+ /*
+ * Get the MII configuration, if applicable.
+ */
+ if (resource_int_value(device_get_name(dev), device_get_unit(dev),
+ "miimode", &miicfg) == 0) {
+ /* XXX bounds check? */
+ device_printf(dev, "%s: overriding MII mode to '%s'\n",
+ __func__, arge_miicfg_str[miicfg]);
+ sc->arge_miicfg = miicfg;
+ }
+
+ /*
+ * Get which PHY of 5 available we should use for this unit
+ */
+ if (resource_int_value(device_get_name(dev), device_get_unit(dev),
+ "phymask", &sc->arge_phymask) != 0) {
+ /*
+ * Use port 4 (WAN) for GE0. For any other port use
+ * its PHY the same as its unit number
+ */
+ if (sc->arge_mac_unit == 0)
+ sc->arge_phymask = (1 << 4);
+ else
+ /* Use all phys up to 4 */
+ sc->arge_phymask = (1 << 4) - 1;
+
+ device_printf(dev, "No PHY specified, using mask %d\n", sc->arge_phymask);
+ }
+
+ /*
+ * Get default media & duplex mode, by default its Base100T
+ * and full duplex
+ */
+ if (resource_int_value(device_get_name(dev), device_get_unit(dev),
+ "media", &hint) != 0)
+ hint = 0;
+
+ if (hint == 1000)
+ sc->arge_media_type = IFM_1000_T;
+ else
+ sc->arge_media_type = IFM_100_TX;
+
+ if (resource_int_value(device_get_name(dev), device_get_unit(dev),
+ "fduplex", &hint) != 0)
+ hint = 1;
+
+ if (hint)
+ sc->arge_duplex_mode = IFM_FDX;
+ else
+ sc->arge_duplex_mode = 0;
+
+ mtx_init(&sc->arge_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK,
+ MTX_DEF);
+ callout_init_mtx(&sc->arge_stat_callout, &sc->arge_mtx, 0);
+ TASK_INIT(&sc->arge_link_task, 0, arge_link_task, sc);
+
+ /* Map control/status registers. */
+ sc->arge_rid = 0;
+ sc->arge_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY,
+ &sc->arge_rid, RF_ACTIVE | RF_SHAREABLE);
+
+ if (sc->arge_res == NULL) {
+ device_printf(dev, "couldn't map memory\n");
+ error = ENXIO;
+ goto fail;
+ }
+
+ /* Allocate interrupts */
+ rid = 0;
+ sc->arge_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
+ RF_SHAREABLE | RF_ACTIVE);
+
+ if (sc->arge_irq == NULL) {
+ device_printf(dev, "couldn't map interrupt\n");
+ error = ENXIO;
+ goto fail;
+ }
+
+ /* Allocate ifnet structure. */
+ ifp = sc->arge_ifp = if_alloc(IFT_ETHER);
+
+ if (ifp == NULL) {
+ device_printf(dev, "couldn't allocate ifnet structure\n");
+ error = ENOSPC;
+ goto fail;
+ }
+
+ ifp->if_softc = sc;
+ if_initname(ifp, device_get_name(dev), device_get_unit(dev));
+ ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
+ ifp->if_ioctl = arge_ioctl;
+ ifp->if_start = arge_start;
+ ifp->if_init = arge_init;
+ sc->arge_if_flags = ifp->if_flags;
+
+ /* XXX: add real size */
+ IFQ_SET_MAXLEN(&ifp->if_snd, ifqmaxlen);
+ ifp->if_snd.ifq_maxlen = ifqmaxlen;
+ IFQ_SET_READY(&ifp->if_snd);
+
+ ifp->if_capenable = ifp->if_capabilities;
+#ifdef DEVICE_POLLING
+ ifp->if_capabilities |= IFCAP_POLLING;
+#endif
+
+ is_base_mac_empty = 1;
+ for (i = 0; i < ETHER_ADDR_LEN; i++) {
+ sc->arge_eaddr[i] = ar711_base_mac[i] & 0xff;
+ if (sc->arge_eaddr[i] != 0)
+ is_base_mac_empty = 0;
+ }
+
+ if (is_base_mac_empty) {
+ /*
+ * No MAC address configured. Generate the random one.
+ */
+ if (bootverbose)
+ device_printf(dev,
+ "Generating random ethernet address.\n");
+
+ rnd = arc4random();
+ sc->arge_eaddr[0] = 'b';
+ sc->arge_eaddr[1] = 's';
+ sc->arge_eaddr[2] = 'd';
+ sc->arge_eaddr[3] = (rnd >> 24) & 0xff;
+ sc->arge_eaddr[4] = (rnd >> 16) & 0xff;
+ sc->arge_eaddr[5] = (rnd >> 8) & 0xff;
+ }
+ if (sc->arge_mac_unit != 0)
+ sc->arge_eaddr[5] += sc->arge_mac_unit;
+
+ if (arge_dma_alloc(sc) != 0) {
+ error = ENXIO;
+ goto fail;
+ }
+
+ /*
+ * Don't do this for the MDIO bus case - it's already done
+ * as part of the MDIO bus attachment.
+ */
+#if !defined(ARGE_MDIO)
+ /* Initialize the MAC block */
+ arge_reset_mac(sc);
+ arge_reset_miibus(sc);
+#endif
+
+ /* Configure MII mode, just for convienence */
+ if (sc->arge_miicfg != 0)
+ ar71xx_device_set_mii_if(sc->arge_mac_unit, sc->arge_miicfg);
+
+ /*
+ * Set all Ethernet address registers to the same initial values
+ * set all four addresses to 66-88-aa-cc-dd-ee
+ */
+ ARGE_WRITE(sc, AR71XX_MAC_STA_ADDR1, (sc->arge_eaddr[2] << 24)
+ | (sc->arge_eaddr[3] << 16) | (sc->arge_eaddr[4] << 8)
+ | sc->arge_eaddr[5]);
+ ARGE_WRITE(sc, AR71XX_MAC_STA_ADDR2, (sc->arge_eaddr[0] << 8)
+ | sc->arge_eaddr[1]);
+
+ ARGE_WRITE(sc, AR71XX_MAC_FIFO_CFG0,
+ FIFO_CFG0_ALL << FIFO_CFG0_ENABLE_SHIFT);
+
+ switch (ar71xx_soc) {
+ case AR71XX_SOC_AR7240:
+ case AR71XX_SOC_AR7241:
+ case AR71XX_SOC_AR7242:
+ case AR71XX_SOC_AR9330:
+ case AR71XX_SOC_AR9331:
+ ARGE_WRITE(sc, AR71XX_MAC_FIFO_CFG1, 0x0010ffff);
+ ARGE_WRITE(sc, AR71XX_MAC_FIFO_CFG2, 0x015500aa);
+ break;
+ default:
+ ARGE_WRITE(sc, AR71XX_MAC_FIFO_CFG1, 0x0fff0000);
+ ARGE_WRITE(sc, AR71XX_MAC_FIFO_CFG2, 0x00001fff);
+ }
+
+ ARGE_WRITE(sc, AR71XX_MAC_FIFO_RX_FILTMATCH,
+ FIFO_RX_FILTMATCH_DEFAULT);
+
+ ARGE_WRITE(sc, AR71XX_MAC_FIFO_RX_FILTMASK,
+ FIFO_RX_FILTMASK_DEFAULT);
+
+#if defined(ARGE_MDIO)
+ sc->arge_miiproxy = mii_attach_proxy(sc->arge_dev);
+#endif
+
+ device_printf(sc->arge_dev, "finishing attachment, phymask %04x"
+ ", proxy %s \n", sc->arge_phymask, sc->arge_miiproxy == NULL ?
+ "null" : "set");
+ for (i = 0; i < ARGE_NPHY; i++) {
+ if (((1 << i) & sc->arge_phymask) != 0) {
+ error = mii_attach(sc->arge_miiproxy != NULL ?
+ sc->arge_miiproxy : sc->arge_dev,
+ &sc->arge_miibus, sc->arge_ifp,
+ arge_ifmedia_upd, arge_ifmedia_sts,
+ BMSR_DEFCAPMASK, i, MII_OFFSET_ANY, 0);
+ if (error != 0) {
+ device_printf(sc->arge_dev, "unable to attach"
+ " PHY %d: %d\n", i, error);
+ goto fail;
+ }
+ }
+ }
+ if (sc->arge_miibus == NULL) {
+ /* no PHY, so use hard-coded values */
+ ifmedia_init(&sc->arge_ifmedia, 0,
+ arge_multiphy_mediachange,
+ arge_multiphy_mediastatus);
+ ifmedia_add(&sc->arge_ifmedia,
+ IFM_ETHER | sc->arge_media_type | sc->arge_duplex_mode,
+ 0, NULL);
+ ifmedia_set(&sc->arge_ifmedia,
+ IFM_ETHER | sc->arge_media_type | sc->arge_duplex_mode);
+ arge_set_pll(sc, sc->arge_media_type, sc->arge_duplex_mode);
+ }
+
+ /* Call MI attach routine. */
+ ether_ifattach(sc->arge_ifp, sc->arge_eaddr);
+
+ /* Hook interrupt last to avoid having to lock softc */
+ error = bus_setup_intr(sc->arge_dev, sc->arge_irq, INTR_TYPE_NET | INTR_MPSAFE,
+ arge_intr_filter, arge_intr, sc, &sc->arge_intrhand);
+
+ if (error) {
+ device_printf(sc->arge_dev, "couldn't set up irq\n");
+ ether_ifdetach(sc->arge_ifp);
+ goto fail;
+ }
+
+ /* setup sysctl variables */
+ arge_attach_sysctl(sc->arge_dev);
+
+fail:
+ if (error)
+ arge_detach(dev);
+
+ return (error);
+}
+
+static int
+arge_detach(device_t dev)
+{
+ struct arge_softc *sc = device_get_softc(dev);
+ struct ifnet *ifp = sc->arge_ifp;
+
+ KASSERT(mtx_initialized(&sc->arge_mtx),
+ ("arge mutex not initialized"));
+
+ /* These should only be active if attach succeeded */
+ if (device_is_attached(dev)) {
+ ARGE_LOCK(sc);
+ sc->arge_detach = 1;
+#ifdef DEVICE_POLLING
+ if (ifp->if_capenable & IFCAP_POLLING)
+ ether_poll_deregister(ifp);
+#endif
+
+ arge_stop(sc);
+ ARGE_UNLOCK(sc);
+ taskqueue_drain(taskqueue_swi, &sc->arge_link_task);
+ ether_ifdetach(ifp);
+ }
+
+ if (sc->arge_miibus)
+ device_delete_child(dev, sc->arge_miibus);
+
+ if (sc->arge_miiproxy)
+ device_delete_child(dev, sc->arge_miiproxy);
+
+ bus_generic_detach(dev);
+
+ if (sc->arge_intrhand)
+ bus_teardown_intr(dev, sc->arge_irq, sc->arge_intrhand);
+
+ if (sc->arge_res)
+ bus_release_resource(dev, SYS_RES_MEMORY, sc->arge_rid,
+ sc->arge_res);
+
+ if (ifp)
+ if_free(ifp);
+
+ arge_dma_free(sc);
+
+ mtx_destroy(&sc->arge_mtx);
+
+ return (0);
+
+}
+
+static int
+arge_suspend(device_t dev)
+{
+
+ panic("%s", __func__);
+ return 0;
+}
+
+static int
+arge_resume(device_t dev)
+{
+
+ panic("%s", __func__);
+ return 0;
+}
+
+static int
+arge_shutdown(device_t dev)
+{
+ struct arge_softc *sc;
+
+ sc = device_get_softc(dev);
+
+ ARGE_LOCK(sc);
+ arge_stop(sc);
+ ARGE_UNLOCK(sc);
+
+ return (0);
+}
+
+static void
+arge_hinted_child(device_t bus, const char *dname, int dunit)
+{
+ BUS_ADD_CHILD(bus, 0, dname, dunit);
+ device_printf(bus, "hinted child %s%d\n", dname, dunit);
+}
+
+static int
+arge_miibus_readreg(device_t dev, int phy, int reg)
+{
+ struct arge_softc * sc = device_get_softc(dev);
+ int i, result;
+ uint32_t addr = (phy << MAC_MII_PHY_ADDR_SHIFT)
+ | (reg & MAC_MII_REG_MASK);
+
+ mtx_lock(&miibus_mtx);
+ ARGE_MDIO_WRITE(sc, AR71XX_MAC_MII_CMD, MAC_MII_CMD_WRITE);
+ ARGE_MDIO_WRITE(sc, AR71XX_MAC_MII_ADDR, addr);
+ ARGE_MDIO_WRITE(sc, AR71XX_MAC_MII_CMD, MAC_MII_CMD_READ);
+
+ i = ARGE_MII_TIMEOUT;
+ while ((ARGE_MDIO_READ(sc, AR71XX_MAC_MII_INDICATOR) &
+ MAC_MII_INDICATOR_BUSY) && (i--))
+ DELAY(5);
+
+ if (i < 0) {
+ mtx_unlock(&miibus_mtx);
+ ARGEDEBUG(sc, ARGE_DBG_MII, "%s timedout\n", __func__);
+ /* XXX: return ERRNO istead? */
+ return (-1);
+ }
+
+ result = ARGE_MDIO_READ(sc, AR71XX_MAC_MII_STATUS) & MAC_MII_STATUS_MASK;
+ ARGE_MDIO_WRITE(sc, AR71XX_MAC_MII_CMD, MAC_MII_CMD_WRITE);
+ mtx_unlock(&miibus_mtx);
+
+ ARGEDEBUG(sc, ARGE_DBG_MII,
+ "%s: phy=%d, reg=%02x, value[%08x]=%04x\n",
+ __func__, phy, reg, addr, result);
+
+ return (result);
+}
+
+static int
+arge_miibus_writereg(device_t dev, int phy, int reg, int data)
+{
+ struct arge_softc * sc = device_get_softc(dev);
+ int i;
+ uint32_t addr =
+ (phy << MAC_MII_PHY_ADDR_SHIFT) | (reg & MAC_MII_REG_MASK);
+
+ ARGEDEBUG(sc, ARGE_DBG_MII, "%s: phy=%d, reg=%02x, value=%04x\n", __func__,
+ phy, reg, data);
+
+ mtx_lock(&miibus_mtx);
+ ARGE_MDIO_WRITE(sc, AR71XX_MAC_MII_ADDR, addr);
+ ARGE_MDIO_WRITE(sc, AR71XX_MAC_MII_CONTROL, data);
+
+ i = ARGE_MII_TIMEOUT;
+ while ((ARGE_MDIO_READ(sc, AR71XX_MAC_MII_INDICATOR) &
+ MAC_MII_INDICATOR_BUSY) && (i--))
+ DELAY(5);
+
+ mtx_unlock(&miibus_mtx);
+
+ if (i < 0) {
+ ARGEDEBUG(sc, ARGE_DBG_MII, "%s timedout\n", __func__);
+ /* XXX: return ERRNO istead? */
+ return (-1);
+ }
+
+ return (0);
+}
+
+static void
+arge_miibus_statchg(device_t dev)
+{
+ struct arge_softc *sc;
+
+ sc = device_get_softc(dev);
+ taskqueue_enqueue(taskqueue_swi, &sc->arge_link_task);
+}
+
+static void
+arge_link_task(void *arg, int pending)
+{
+ struct arge_softc *sc;
+ sc = (struct arge_softc *)arg;
+
+ ARGE_LOCK(sc);
+ arge_update_link_locked(sc);
+ ARGE_UNLOCK(sc);
+}
+
+static void
+arge_update_link_locked(struct arge_softc *sc)
+{
+ struct mii_data *mii;
+ struct ifnet *ifp;
+ uint32_t media, duplex;
+
+ mii = device_get_softc(sc->arge_miibus);
+ ifp = sc->arge_ifp;
+ if (mii == NULL || ifp == NULL ||
+ (ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) {
+ return;
+ }
+
+ if (mii->mii_media_status & IFM_ACTIVE) {
+
+ media = IFM_SUBTYPE(mii->mii_media_active);
+ if (media != IFM_NONE) {
+ sc->arge_link_status = 1;
+ duplex = mii->mii_media_active & IFM_GMASK;
+ ARGEDEBUG(sc, ARGE_DBG_MII, "%s: media=%d, duplex=%d\n",
+ __func__,
+ media,
+ duplex);
+ arge_set_pll(sc, media, duplex);
+ }
+ } else {
+ sc->arge_link_status = 0;
+ }
+}
+
+static void
+arge_set_pll(struct arge_softc *sc, int media, int duplex)
+{
+ uint32_t cfg, ifcontrol, rx_filtmask;
+ uint32_t fifo_tx, pll;
+ int if_speed;
+
+ ARGEDEBUG(sc, ARGE_DBG_PLL, "set_pll(%04x, %s)\n", media,
+ duplex == IFM_FDX ? "full" : "half");
+ cfg = ARGE_READ(sc, AR71XX_MAC_CFG2);
+ cfg &= ~(MAC_CFG2_IFACE_MODE_1000
+ | MAC_CFG2_IFACE_MODE_10_100
+ | MAC_CFG2_FULL_DUPLEX);
+
+ if (duplex == IFM_FDX)
+ cfg |= MAC_CFG2_FULL_DUPLEX;
+
+ ifcontrol = ARGE_READ(sc, AR71XX_MAC_IFCONTROL);
+ ifcontrol &= ~MAC_IFCONTROL_SPEED;
+ rx_filtmask =
+ ARGE_READ(sc, AR71XX_MAC_FIFO_RX_FILTMASK);
+ rx_filtmask &= ~FIFO_RX_MASK_BYTE_MODE;
+
+ switch(media) {
+ case IFM_10_T:
+ cfg |= MAC_CFG2_IFACE_MODE_10_100;
+ if_speed = 10;
+ break;
+ case IFM_100_TX:
+ cfg |= MAC_CFG2_IFACE_MODE_10_100;
+ ifcontrol |= MAC_IFCONTROL_SPEED;
+ if_speed = 100;
+ break;
+ case IFM_1000_T:
+ case IFM_1000_SX:
+ cfg |= MAC_CFG2_IFACE_MODE_1000;
+ rx_filtmask |= FIFO_RX_MASK_BYTE_MODE;
+ if_speed = 1000;
+ break;
+ default:
+ if_speed = 100;
+ device_printf(sc->arge_dev,
+ "Unknown media %d\n", media);
+ }
+
+ ARGEDEBUG(sc, ARGE_DBG_PLL, "%s: if_speed=%d\n", __func__, if_speed);
+
+ switch (ar71xx_soc) {
+ case AR71XX_SOC_AR7240:
+ case AR71XX_SOC_AR7241:
+ case AR71XX_SOC_AR7242:
+ case AR71XX_SOC_AR9330:
+ case AR71XX_SOC_AR9331:
+ fifo_tx = 0x01f00140;
+ break;
+ case AR71XX_SOC_AR9130:
+ case AR71XX_SOC_AR9132:
+ fifo_tx = 0x00780fff;
+ break;
+ default:
+ fifo_tx = 0x008001ff;
+ }
+
+ ARGE_WRITE(sc, AR71XX_MAC_CFG2, cfg);
+ ARGE_WRITE(sc, AR71XX_MAC_IFCONTROL, ifcontrol);
+ ARGE_WRITE(sc, AR71XX_MAC_FIFO_RX_FILTMASK,
+ rx_filtmask);
+ ARGE_WRITE(sc, AR71XX_MAC_FIFO_TX_THRESHOLD, fifo_tx);
+
+ /* fetch PLL registers */
+ pll = ar71xx_device_get_eth_pll(sc->arge_mac_unit, if_speed);
+ ARGEDEBUG(sc, ARGE_DBG_PLL, "%s: pll=0x%x\n", __func__, pll);
+
+ /* Override if required by platform data */
+ if (if_speed == 10 && sc->arge_pllcfg.pll_10 != 0)
+ pll = sc->arge_pllcfg.pll_10;
+ else if (if_speed == 100 && sc->arge_pllcfg.pll_100 != 0)
+ pll = sc->arge_pllcfg.pll_100;
+ else if (if_speed == 1000 && sc->arge_pllcfg.pll_1000 != 0)
+ pll = sc->arge_pllcfg.pll_1000;
+ ARGEDEBUG(sc, ARGE_DBG_PLL, "%s: final pll=0x%x\n", __func__, pll);
+
+ /* XXX ensure pll != 0 */
+ ar71xx_device_set_pll_ge(sc->arge_mac_unit, if_speed, pll);
+
+ /* set MII registers */
+ /*
+ * This was introduced to match what the Linux ag71xx ethernet
+ * driver does. For the AR71xx case, it does set the port
+ * MII speed. However, if this is done, non-gigabit speeds
+ * are not at all reliable when speaking via RGMII through
+ * 'bridge' PHY port that's pretending to be a local PHY.
+ *
+ * Until that gets root caused, and until an AR71xx + normal
+ * PHY board is tested, leave this disabled.
+ */
+#if 0
+ ar71xx_device_set_mii_speed(sc->arge_mac_unit, if_speed);
+#endif
+}
+
+
+static void
+arge_reset_dma(struct arge_softc *sc)
+{
+ ARGE_WRITE(sc, AR71XX_DMA_RX_CONTROL, 0);
+ ARGE_WRITE(sc, AR71XX_DMA_TX_CONTROL, 0);
+
+ ARGE_WRITE(sc, AR71XX_DMA_RX_DESC, 0);
+ ARGE_WRITE(sc, AR71XX_DMA_TX_DESC, 0);
+
+ /* Clear all possible RX interrupts */
+ while(ARGE_READ(sc, AR71XX_DMA_RX_STATUS) & DMA_RX_STATUS_PKT_RECVD)
+ ARGE_WRITE(sc, AR71XX_DMA_RX_STATUS, DMA_RX_STATUS_PKT_RECVD);
+
+ /*
+ * Clear all possible TX interrupts
+ */
+ while(ARGE_READ(sc, AR71XX_DMA_TX_STATUS) & DMA_TX_STATUS_PKT_SENT)
+ ARGE_WRITE(sc, AR71XX_DMA_TX_STATUS, DMA_TX_STATUS_PKT_SENT);
+
+ /*
+ * Now Rx/Tx errors
+ */
+ ARGE_WRITE(sc, AR71XX_DMA_RX_STATUS,
+ DMA_RX_STATUS_BUS_ERROR | DMA_RX_STATUS_OVERFLOW);
+ ARGE_WRITE(sc, AR71XX_DMA_TX_STATUS,
+ DMA_TX_STATUS_BUS_ERROR | DMA_TX_STATUS_UNDERRUN);
+
+ /*
+ * Force a DDR flush so any pending data is properly
+ * flushed to RAM before underlying buffers are freed.
+ */
+ arge_flush_ddr(sc);
+}
+
+
+
+static void
+arge_init(void *xsc)
+{
+ struct arge_softc *sc = xsc;
+
+ ARGE_LOCK(sc);
+ arge_init_locked(sc);
+ ARGE_UNLOCK(sc);
+}
+
+static void
+arge_init_locked(struct arge_softc *sc)
+{
+ struct ifnet *ifp = sc->arge_ifp;
+ struct mii_data *mii;
+
+ ARGE_LOCK_ASSERT(sc);
+
+ if ((ifp->if_flags & IFF_UP) && (ifp->if_drv_flags & IFF_DRV_RUNNING))
+ return;
+
+ /* Init circular RX list. */
+ if (arge_rx_ring_init(sc) != 0) {
+ device_printf(sc->arge_dev,
+ "initialization failed: no memory for rx buffers\n");
+ arge_stop(sc);
+ return;
+ }
+
+ /* Init tx descriptors. */
+ arge_tx_ring_init(sc);
+
+ arge_reset_dma(sc);
+
+ if (sc->arge_miibus) {
+ mii = device_get_softc(sc->arge_miibus);
+ mii_mediachg(mii);
+ }
+ else {
+ /*
+ * Sun always shines over multiPHY interface
+ */
+ sc->arge_link_status = 1;
+ }
+
+ ifp->if_drv_flags |= IFF_DRV_RUNNING;
+ ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
+
+ if (sc->arge_miibus) {
+ callout_reset(&sc->arge_stat_callout, hz, arge_tick, sc);
+ arge_update_link_locked(sc);
+ }
+
+ ARGE_WRITE(sc, AR71XX_DMA_TX_DESC, ARGE_TX_RING_ADDR(sc, 0));
+ ARGE_WRITE(sc, AR71XX_DMA_RX_DESC, ARGE_RX_RING_ADDR(sc, 0));
+
+ /* Start listening */
+ ARGE_WRITE(sc, AR71XX_DMA_RX_CONTROL, DMA_RX_CONTROL_EN);
+
+ /* Enable interrupts */
+ ARGE_WRITE(sc, AR71XX_DMA_INTR, DMA_INTR_ALL);
+}
+
+/*
+ * Return whether the mbuf chain is correctly aligned
+ * for the arge TX engine.
+ *
+ * The TX engine requires each fragment to be aligned to a
+ * 4 byte boundary and the size of each fragment except
+ * the last to be a multiple of 4 bytes.
+ */
+static int
+arge_mbuf_chain_is_tx_aligned(struct mbuf *m0)
+{
+ struct mbuf *m;
+
+ for (m = m0; m != NULL; m = m->m_next) {
+ if((mtod(m, intptr_t) & 3) != 0)
+ return 0;
+ if ((m->m_next != NULL) && ((m->m_len & 0x03) != 0))
+ return 0;
+ }
+ return 1;
+}
+
+/*
+ * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data
+ * pointers to the fragment pointers.
+ */
+static int
+arge_encap(struct arge_softc *sc, struct mbuf **m_head)
+{
+ struct arge_txdesc *txd;
+ struct arge_desc *desc, *prev_desc;
+ bus_dma_segment_t txsegs[ARGE_MAXFRAGS];
+ int error, i, nsegs, prod, prev_prod;
+ struct mbuf *m;
+
+ ARGE_LOCK_ASSERT(sc);
+
+ /*
+ * Fix mbuf chain, all fragments should be 4 bytes aligned and
+ * even 4 bytes
+ */
+ m = *m_head;
+ if (! arge_mbuf_chain_is_tx_aligned(m)) {
+ sc->stats.tx_pkts_unaligned++;
+ m = m_defrag(*m_head, M_NOWAIT);
+ if (m == NULL) {
+ m_freem(*m_head);
+ *m_head = NULL;
+ return (ENOBUFS);
+ }
+ *m_head = m;
+ } else
+ sc->stats.tx_pkts_aligned++;
+
+ prod = sc->arge_cdata.arge_tx_prod;
+ txd = &sc->arge_cdata.arge_txdesc[prod];
+ error = bus_dmamap_load_mbuf_sg(sc->arge_cdata.arge_tx_tag,
+ txd->tx_dmamap, *m_head, txsegs, &nsegs, BUS_DMA_NOWAIT);
+
+ if (error == EFBIG) {
+ panic("EFBIG");
+ } else if (error != 0)
+ return (error);
+
+ if (nsegs == 0) {
+ m_freem(*m_head);
+ *m_head = NULL;
+ return (EIO);
+ }
+
+ /* Check number of available descriptors. */
+ if (sc->arge_cdata.arge_tx_cnt + nsegs >= (ARGE_TX_RING_COUNT - 1)) {
+ bus_dmamap_unload(sc->arge_cdata.arge_tx_tag, txd->tx_dmamap);
+ return (ENOBUFS);
+ }
+
+ txd->tx_m = *m_head;
+ bus_dmamap_sync(sc->arge_cdata.arge_tx_tag, txd->tx_dmamap,
+ BUS_DMASYNC_PREWRITE);
+
+ /*
+ * Make a list of descriptors for this packet. DMA controller will
+ * walk through it while arge_link is not zero.
+ */
+ prev_prod = prod;
+ desc = prev_desc = NULL;
+ for (i = 0; i < nsegs; i++) {
+ desc = &sc->arge_rdata.arge_tx_ring[prod];
+ desc->packet_ctrl = ARGE_DMASIZE(txsegs[i].ds_len);
+
+ if (txsegs[i].ds_addr & 3)
+ panic("TX packet address unaligned\n");
+
+ desc->packet_addr = txsegs[i].ds_addr;
+
+ /* link with previous descriptor */
+ if (prev_desc)
+ prev_desc->packet_ctrl |= ARGE_DESC_MORE;
+
+ sc->arge_cdata.arge_tx_cnt++;
+ prev_desc = desc;
+ ARGE_INC(prod, ARGE_TX_RING_COUNT);
+ }
+
+ /* Update producer index. */
+ sc->arge_cdata.arge_tx_prod = prod;
+
+ /* Sync descriptors. */
+ bus_dmamap_sync(sc->arge_cdata.arge_tx_ring_tag,
+ sc->arge_cdata.arge_tx_ring_map,
+ BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
+
+ /* Start transmitting */
+ ARGEDEBUG(sc, ARGE_DBG_TX, "%s: setting DMA_TX_CONTROL_EN\n",
+ __func__);
+ ARGE_WRITE(sc, AR71XX_DMA_TX_CONTROL, DMA_TX_CONTROL_EN);
+ return (0);
+}
+
+static void
+arge_start(struct ifnet *ifp)
+{
+ struct arge_softc *sc;
+
+ sc = ifp->if_softc;
+
+ ARGE_LOCK(sc);
+ arge_start_locked(ifp);
+ ARGE_UNLOCK(sc);
+}
+
+static void
+arge_start_locked(struct ifnet *ifp)
+{
+ struct arge_softc *sc;
+ struct mbuf *m_head;
+ int enq = 0;
+
+ sc = ifp->if_softc;
+
+ ARGE_LOCK_ASSERT(sc);
+
+ ARGEDEBUG(sc, ARGE_DBG_TX, "%s: beginning\n", __func__);
+
+ if ((ifp->if_drv_flags & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) !=
+ IFF_DRV_RUNNING || sc->arge_link_status == 0 )
+ return;
+
+ /*
+ * Before we go any further, check whether we're already full.
+ * The below check errors out immediately if the ring is full
+ * and never gets a chance to set this flag. Although it's
+ * likely never needed, this at least avoids an unexpected
+ * situation.
+ */
+ if (sc->arge_cdata.arge_tx_cnt >= ARGE_TX_RING_COUNT - 2) {
+ ifp->if_drv_flags |= IFF_DRV_OACTIVE;
+ ARGEDEBUG(sc, ARGE_DBG_ERR,
+ "%s: tx_cnt %d >= max %d; setting IFF_DRV_OACTIVE\n",
+ __func__, sc->arge_cdata.arge_tx_cnt,
+ ARGE_TX_RING_COUNT - 2);
+ return;
+ }
+
+ arge_flush_ddr(sc);
+
+ for (enq = 0; !IFQ_DRV_IS_EMPTY(&ifp->if_snd) &&
+ sc->arge_cdata.arge_tx_cnt < ARGE_TX_RING_COUNT - 2; ) {
+ IFQ_DRV_DEQUEUE(&ifp->if_snd, m_head);
+ if (m_head == NULL)
+ break;
+
+
+ /*
+ * Pack the data into the transmit ring.
+ */
+ if (arge_encap(sc, &m_head)) {
+ if (m_head == NULL)
+ break;
+ IFQ_DRV_PREPEND(&ifp->if_snd, m_head);
+ ifp->if_drv_flags |= IFF_DRV_OACTIVE;
+ break;
+ }
+
+ enq++;
+ /*
+ * If there's a BPF listener, bounce a copy of this frame
+ * to him.
+ */
+ ETHER_BPF_MTAP(ifp, m_head);
+ }
+ ARGEDEBUG(sc, ARGE_DBG_TX, "%s: finished; queued %d packets\n",
+ __func__, enq);
+}
+
+static void
+arge_stop(struct arge_softc *sc)
+{
+ struct ifnet *ifp;
+
+ ARGE_LOCK_ASSERT(sc);
+
+ ifp = sc->arge_ifp;
+ ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE);
+ if (sc->arge_miibus)
+ callout_stop(&sc->arge_stat_callout);
+
+ /* mask out interrupts */
+ ARGE_WRITE(sc, AR71XX_DMA_INTR, 0);
+
+ arge_reset_dma(sc);
+
+ /* Flush FIFO and free any existing mbufs */
+ arge_flush_ddr(sc);
+ arge_rx_ring_free(sc);
+ arge_tx_ring_free(sc);
+}
+
+
+static int
+arge_ioctl(struct ifnet *ifp, u_long command, caddr_t data)
+{
+ struct arge_softc *sc = ifp->if_softc;
+ struct ifreq *ifr = (struct ifreq *) data;
+ struct mii_data *mii;
+ int error;
+#ifdef DEVICE_POLLING
+ int mask;
+#endif
+
+ switch (command) {
+ case SIOCSIFFLAGS:
+ ARGE_LOCK(sc);
+ if ((ifp->if_flags & IFF_UP) != 0) {
+ if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) {
+ if (((ifp->if_flags ^ sc->arge_if_flags)
+ & (IFF_PROMISC | IFF_ALLMULTI)) != 0) {
+ /* XXX: handle promisc & multi flags */
+ }
+
+ } else {
+ if (!sc->arge_detach)
+ arge_init_locked(sc);
+ }
+ } else if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) {
+ ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
+ arge_stop(sc);
+ }
+ sc->arge_if_flags = ifp->if_flags;
+ ARGE_UNLOCK(sc);
+ error = 0;
+ break;
+ case SIOCADDMULTI:
+ case SIOCDELMULTI:
+ /* XXX: implement SIOCDELMULTI */
+ error = 0;
+ break;
+ case SIOCGIFMEDIA:
+ case SIOCSIFMEDIA:
+ if (sc->arge_miibus) {
+ mii = device_get_softc(sc->arge_miibus);
+ error = ifmedia_ioctl(ifp, ifr, &mii->mii_media,
+ command);
+ }
+ else
+ error = ifmedia_ioctl(ifp, ifr, &sc->arge_ifmedia,
+ command);
+ break;
+ case SIOCSIFCAP:
+ /* XXX: Check other capabilities */
+#ifdef DEVICE_POLLING
+ mask = ifp->if_capenable ^ ifr->ifr_reqcap;
+ if (mask & IFCAP_POLLING) {
+ if (ifr->ifr_reqcap & IFCAP_POLLING) {
+ ARGE_WRITE(sc, AR71XX_DMA_INTR, 0);
+ error = ether_poll_register(arge_poll, ifp);
+ if (error)
+ return error;
+ ARGE_LOCK(sc);
+ ifp->if_capenable |= IFCAP_POLLING;
+ ARGE_UNLOCK(sc);
+ } else {
+ ARGE_WRITE(sc, AR71XX_DMA_INTR, DMA_INTR_ALL);
+ error = ether_poll_deregister(ifp);
+ ARGE_LOCK(sc);
+ ifp->if_capenable &= ~IFCAP_POLLING;
+ ARGE_UNLOCK(sc);
+ }
+ }
+ error = 0;
+ break;
+#endif
+ default:
+ error = ether_ioctl(ifp, command, data);
+ break;
+ }
+
+ return (error);
+}
+
+/*
+ * Set media options.
+ */
+static int
+arge_ifmedia_upd(struct ifnet *ifp)
+{
+ struct arge_softc *sc;
+ struct mii_data *mii;
+ struct mii_softc *miisc;
+ int error;
+
+ sc = ifp->if_softc;
+ ARGE_LOCK(sc);
+ mii = device_get_softc(sc->arge_miibus);
+ LIST_FOREACH(miisc, &mii->mii_phys, mii_list)
+ PHY_RESET(miisc);
+ error = mii_mediachg(mii);
+ ARGE_UNLOCK(sc);
+
+ return (error);
+}
+
+/*
+ * Report current media status.
+ */
+static void
+arge_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr)
+{
+ struct arge_softc *sc = ifp->if_softc;
+ struct mii_data *mii;
+
+ mii = device_get_softc(sc->arge_miibus);
+ ARGE_LOCK(sc);
+ mii_pollstat(mii);
+ ifmr->ifm_active = mii->mii_media_active;
+ ifmr->ifm_status = mii->mii_media_status;
+ ARGE_UNLOCK(sc);
+}
+
+struct arge_dmamap_arg {
+ bus_addr_t arge_busaddr;
+};
+
+static void
+arge_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nseg, int error)
+{
+ struct arge_dmamap_arg *ctx;
+
+ if (error != 0)
+ return;
+ ctx = arg;
+ ctx->arge_busaddr = segs[0].ds_addr;
+}
+
+static int
+arge_dma_alloc(struct arge_softc *sc)
+{
+ struct arge_dmamap_arg ctx;
+ struct arge_txdesc *txd;
+ struct arge_rxdesc *rxd;
+ int error, i;
+
+ /* Create parent DMA tag. */
+ error = bus_dma_tag_create(
+ bus_get_dma_tag(sc->arge_dev), /* parent */
+ 1, 0, /* alignment, boundary */
+ BUS_SPACE_MAXADDR_32BIT, /* lowaddr */
+ BUS_SPACE_MAXADDR, /* highaddr */
+ NULL, NULL, /* filter, filterarg */
+ BUS_SPACE_MAXSIZE_32BIT, /* maxsize */
+ 0, /* nsegments */
+ BUS_SPACE_MAXSIZE_32BIT, /* maxsegsize */
+ 0, /* flags */
+ NULL, NULL, /* lockfunc, lockarg */
+ &sc->arge_cdata.arge_parent_tag);
+ if (error != 0) {
+ device_printf(sc->arge_dev,
+ "failed to create parent DMA tag\n");
+ goto fail;
+ }
+ /* Create tag for Tx ring. */
+ error = bus_dma_tag_create(
+ sc->arge_cdata.arge_parent_tag, /* parent */
+ ARGE_RING_ALIGN, 0, /* alignment, boundary */
+ BUS_SPACE_MAXADDR, /* lowaddr */
+ BUS_SPACE_MAXADDR, /* highaddr */
+ NULL, NULL, /* filter, filterarg */
+ ARGE_TX_DMA_SIZE, /* maxsize */
+ 1, /* nsegments */
+ ARGE_TX_DMA_SIZE, /* maxsegsize */
+ 0, /* flags */
+ NULL, NULL, /* lockfunc, lockarg */
+ &sc->arge_cdata.arge_tx_ring_tag);
+ if (error != 0) {
+ device_printf(sc->arge_dev,
+ "failed to create Tx ring DMA tag\n");
+ goto fail;
+ }
+
+ /* Create tag for Rx ring. */
+ error = bus_dma_tag_create(
+ sc->arge_cdata.arge_parent_tag, /* parent */
+ ARGE_RING_ALIGN, 0, /* alignment, boundary */
+ BUS_SPACE_MAXADDR, /* lowaddr */
+ BUS_SPACE_MAXADDR, /* highaddr */
+ NULL, NULL, /* filter, filterarg */
+ ARGE_RX_DMA_SIZE, /* maxsize */
+ 1, /* nsegments */
+ ARGE_RX_DMA_SIZE, /* maxsegsize */
+ 0, /* flags */
+ NULL, NULL, /* lockfunc, lockarg */
+ &sc->arge_cdata.arge_rx_ring_tag);
+ if (error != 0) {
+ device_printf(sc->arge_dev,
+ "failed to create Rx ring DMA tag\n");
+ goto fail;
+ }
+
+ /* Create tag for Tx buffers. */
+ error = bus_dma_tag_create(
+ sc->arge_cdata.arge_parent_tag, /* parent */
+ sizeof(uint32_t), 0, /* alignment, boundary */
+ BUS_SPACE_MAXADDR, /* lowaddr */
+ BUS_SPACE_MAXADDR, /* highaddr */
+ NULL, NULL, /* filter, filterarg */
+ MCLBYTES * ARGE_MAXFRAGS, /* maxsize */
+ ARGE_MAXFRAGS, /* nsegments */
+ MCLBYTES, /* maxsegsize */
+ 0, /* flags */
+ NULL, NULL, /* lockfunc, lockarg */
+ &sc->arge_cdata.arge_tx_tag);
+ if (error != 0) {
+ device_printf(sc->arge_dev, "failed to create Tx DMA tag\n");
+ goto fail;
+ }
+
+ /* Create tag for Rx buffers. */
+ error = bus_dma_tag_create(
+ sc->arge_cdata.arge_parent_tag, /* parent */
+ ARGE_RX_ALIGN, 0, /* alignment, boundary */
+ BUS_SPACE_MAXADDR, /* lowaddr */
+ BUS_SPACE_MAXADDR, /* highaddr */
+ NULL, NULL, /* filter, filterarg */
+ MCLBYTES, /* maxsize */
+ ARGE_MAXFRAGS, /* nsegments */
+ MCLBYTES, /* maxsegsize */
+ 0, /* flags */
+ NULL, NULL, /* lockfunc, lockarg */
+ &sc->arge_cdata.arge_rx_tag);
+ if (error != 0) {
+ device_printf(sc->arge_dev, "failed to create Rx DMA tag\n");
+ goto fail;
+ }
+
+ /* Allocate DMA'able memory and load the DMA map for Tx ring. */
+ error = bus_dmamem_alloc(sc->arge_cdata.arge_tx_ring_tag,
+ (void **)&sc->arge_rdata.arge_tx_ring, BUS_DMA_WAITOK |
+ BUS_DMA_COHERENT | BUS_DMA_ZERO,
+ &sc->arge_cdata.arge_tx_ring_map);
+ if (error != 0) {
+ device_printf(sc->arge_dev,
+ "failed to allocate DMA'able memory for Tx ring\n");
+ goto fail;
+ }
+
+ ctx.arge_busaddr = 0;
+ error = bus_dmamap_load(sc->arge_cdata.arge_tx_ring_tag,
+ sc->arge_cdata.arge_tx_ring_map, sc->arge_rdata.arge_tx_ring,
+ ARGE_TX_DMA_SIZE, arge_dmamap_cb, &ctx, 0);
+ if (error != 0 || ctx.arge_busaddr == 0) {
+ device_printf(sc->arge_dev,
+ "failed to load DMA'able memory for Tx ring\n");
+ goto fail;
+ }
+ sc->arge_rdata.arge_tx_ring_paddr = ctx.arge_busaddr;
+
+ /* Allocate DMA'able memory and load the DMA map for Rx ring. */
+ error = bus_dmamem_alloc(sc->arge_cdata.arge_rx_ring_tag,
+ (void **)&sc->arge_rdata.arge_rx_ring, BUS_DMA_WAITOK |
+ BUS_DMA_COHERENT | BUS_DMA_ZERO,
+ &sc->arge_cdata.arge_rx_ring_map);
+ if (error != 0) {
+ device_printf(sc->arge_dev,
+ "failed to allocate DMA'able memory for Rx ring\n");
+ goto fail;
+ }
+
+ ctx.arge_busaddr = 0;
+ error = bus_dmamap_load(sc->arge_cdata.arge_rx_ring_tag,
+ sc->arge_cdata.arge_rx_ring_map, sc->arge_rdata.arge_rx_ring,
+ ARGE_RX_DMA_SIZE, arge_dmamap_cb, &ctx, 0);
+ if (error != 0 || ctx.arge_busaddr == 0) {
+ device_printf(sc->arge_dev,
+ "failed to load DMA'able memory for Rx ring\n");
+ goto fail;
+ }
+ sc->arge_rdata.arge_rx_ring_paddr = ctx.arge_busaddr;
+
+ /* Create DMA maps for Tx buffers. */
+ for (i = 0; i < ARGE_TX_RING_COUNT; i++) {
+ txd = &sc->arge_cdata.arge_txdesc[i];
+ txd->tx_m = NULL;
+ txd->tx_dmamap = NULL;
+ error = bus_dmamap_create(sc->arge_cdata.arge_tx_tag, 0,
+ &txd->tx_dmamap);
+ if (error != 0) {
+ device_printf(sc->arge_dev,
+ "failed to create Tx dmamap\n");
+ goto fail;
+ }
+ }
+ /* Create DMA maps for Rx buffers. */
+ if ((error = bus_dmamap_create(sc->arge_cdata.arge_rx_tag, 0,
+ &sc->arge_cdata.arge_rx_sparemap)) != 0) {
+ device_printf(sc->arge_dev,
+ "failed to create spare Rx dmamap\n");
+ goto fail;
+ }
+ for (i = 0; i < ARGE_RX_RING_COUNT; i++) {
+ rxd = &sc->arge_cdata.arge_rxdesc[i];
+ rxd->rx_m = NULL;
+ rxd->rx_dmamap = NULL;
+ error = bus_dmamap_create(sc->arge_cdata.arge_rx_tag, 0,
+ &rxd->rx_dmamap);
+ if (error != 0) {
+ device_printf(sc->arge_dev,
+ "failed to create Rx dmamap\n");
+ goto fail;
+ }
+ }
+
+fail:
+ return (error);
+}
+
+static void
+arge_dma_free(struct arge_softc *sc)
+{
+ struct arge_txdesc *txd;
+ struct arge_rxdesc *rxd;
+ int i;
+
+ /* Tx ring. */
+ if (sc->arge_cdata.arge_tx_ring_tag) {
+ if (sc->arge_cdata.arge_tx_ring_map)
+ bus_dmamap_unload(sc->arge_cdata.arge_tx_ring_tag,
+ sc->arge_cdata.arge_tx_ring_map);
+ if (sc->arge_cdata.arge_tx_ring_map &&
+ sc->arge_rdata.arge_tx_ring)
+ bus_dmamem_free(sc->arge_cdata.arge_tx_ring_tag,
+ sc->arge_rdata.arge_tx_ring,
+ sc->arge_cdata.arge_tx_ring_map);
+ sc->arge_rdata.arge_tx_ring = NULL;
+ sc->arge_cdata.arge_tx_ring_map = NULL;
+ bus_dma_tag_destroy(sc->arge_cdata.arge_tx_ring_tag);
+ sc->arge_cdata.arge_tx_ring_tag = NULL;
+ }
+ /* Rx ring. */
+ if (sc->arge_cdata.arge_rx_ring_tag) {
+ if (sc->arge_cdata.arge_rx_ring_map)
+ bus_dmamap_unload(sc->arge_cdata.arge_rx_ring_tag,
+ sc->arge_cdata.arge_rx_ring_map);
+ if (sc->arge_cdata.arge_rx_ring_map &&
+ sc->arge_rdata.arge_rx_ring)
+ bus_dmamem_free(sc->arge_cdata.arge_rx_ring_tag,
+ sc->arge_rdata.arge_rx_ring,
+ sc->arge_cdata.arge_rx_ring_map);
+ sc->arge_rdata.arge_rx_ring = NULL;
+ sc->arge_cdata.arge_rx_ring_map = NULL;
+ bus_dma_tag_destroy(sc->arge_cdata.arge_rx_ring_tag);
+ sc->arge_cdata.arge_rx_ring_tag = NULL;
+ }
+ /* Tx buffers. */
+ if (sc->arge_cdata.arge_tx_tag) {
+ for (i = 0; i < ARGE_TX_RING_COUNT; i++) {
+ txd = &sc->arge_cdata.arge_txdesc[i];
+ if (txd->tx_dmamap) {
+ bus_dmamap_destroy(sc->arge_cdata.arge_tx_tag,
+ txd->tx_dmamap);
+ txd->tx_dmamap = NULL;
+ }
+ }
+ bus_dma_tag_destroy(sc->arge_cdata.arge_tx_tag);
+ sc->arge_cdata.arge_tx_tag = NULL;
+ }
+ /* Rx buffers. */
+ if (sc->arge_cdata.arge_rx_tag) {
+ for (i = 0; i < ARGE_RX_RING_COUNT; i++) {
+ rxd = &sc->arge_cdata.arge_rxdesc[i];
+ if (rxd->rx_dmamap) {
+ bus_dmamap_destroy(sc->arge_cdata.arge_rx_tag,
+ rxd->rx_dmamap);
+ rxd->rx_dmamap = NULL;
+ }
+ }
+ if (sc->arge_cdata.arge_rx_sparemap) {
+ bus_dmamap_destroy(sc->arge_cdata.arge_rx_tag,
+ sc->arge_cdata.arge_rx_sparemap);
+ sc->arge_cdata.arge_rx_sparemap = 0;
+ }
+ bus_dma_tag_destroy(sc->arge_cdata.arge_rx_tag);
+ sc->arge_cdata.arge_rx_tag = NULL;
+ }
+
+ if (sc->arge_cdata.arge_parent_tag) {
+ bus_dma_tag_destroy(sc->arge_cdata.arge_parent_tag);
+ sc->arge_cdata.arge_parent_tag = NULL;
+ }
+}
+
+/*
+ * Initialize the transmit descriptors.
+ */
+static int
+arge_tx_ring_init(struct arge_softc *sc)
+{
+ struct arge_ring_data *rd;
+ struct arge_txdesc *txd;
+ bus_addr_t addr;
+ int i;
+
+ sc->arge_cdata.arge_tx_prod = 0;
+ sc->arge_cdata.arge_tx_cons = 0;
+ sc->arge_cdata.arge_tx_cnt = 0;
+
+ rd = &sc->arge_rdata;
+ bzero(rd->arge_tx_ring, sizeof(rd->arge_tx_ring));
+ for (i = 0; i < ARGE_TX_RING_COUNT; i++) {
+ if (i == ARGE_TX_RING_COUNT - 1)
+ addr = ARGE_TX_RING_ADDR(sc, 0);
+ else
+ addr = ARGE_TX_RING_ADDR(sc, i + 1);
+ rd->arge_tx_ring[i].packet_ctrl = ARGE_DESC_EMPTY;
+ rd->arge_tx_ring[i].next_desc = addr;
+ txd = &sc->arge_cdata.arge_txdesc[i];
+ txd->tx_m = NULL;
+ }
+
+ bus_dmamap_sync(sc->arge_cdata.arge_tx_ring_tag,
+ sc->arge_cdata.arge_tx_ring_map,
+ BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
+
+ return (0);
+}
+
+/*
+ * Free the Tx ring, unload any pending dma transaction and free the mbuf.
+ */
+static void
+arge_tx_ring_free(struct arge_softc *sc)
+{
+ struct arge_txdesc *txd;
+ int i;
+
+ /* Free the Tx buffers. */
+ for (i = 0; i < ARGE_TX_RING_COUNT; i++) {
+ txd = &sc->arge_cdata.arge_txdesc[i];
+ if (txd->tx_dmamap) {
+ bus_dmamap_sync(sc->arge_cdata.arge_tx_tag,
+ txd->tx_dmamap, BUS_DMASYNC_POSTWRITE);
+ bus_dmamap_unload(sc->arge_cdata.arge_tx_tag,
+ txd->tx_dmamap);
+ }
+ if (txd->tx_m)
+ m_freem(txd->tx_m);
+ txd->tx_m = NULL;
+ }
+}
+
+/*
+ * Initialize the RX descriptors and allocate mbufs for them. Note that
+ * we arrange the descriptors in a closed ring, so that the last descriptor
+ * points back to the first.
+ */
+static int
+arge_rx_ring_init(struct arge_softc *sc)
+{
+ struct arge_ring_data *rd;
+ struct arge_rxdesc *rxd;
+ bus_addr_t addr;
+ int i;
+
+ sc->arge_cdata.arge_rx_cons = 0;
+
+ rd = &sc->arge_rdata;
+ bzero(rd->arge_rx_ring, sizeof(rd->arge_rx_ring));
+ for (i = 0; i < ARGE_RX_RING_COUNT; i++) {
+ rxd = &sc->arge_cdata.arge_rxdesc[i];
+ if (rxd->rx_m != NULL) {
+ device_printf(sc->arge_dev,
+ "%s: ring[%d] rx_m wasn't free?\n",
+ __func__,
+ i);
+ }
+ rxd->rx_m = NULL;
+ rxd->desc = &rd->arge_rx_ring[i];
+ if (i == ARGE_RX_RING_COUNT - 1)
+ addr = ARGE_RX_RING_ADDR(sc, 0);
+ else
+ addr = ARGE_RX_RING_ADDR(sc, i + 1);
+ rd->arge_rx_ring[i].next_desc = addr;
+ if (arge_newbuf(sc, i) != 0) {
+ return (ENOBUFS);
+ }
+ }
+
+ bus_dmamap_sync(sc->arge_cdata.arge_rx_ring_tag,
+ sc->arge_cdata.arge_rx_ring_map,
+ BUS_DMASYNC_PREWRITE);
+
+ return (0);
+}
+
+/*
+ * Free all the buffers in the RX ring.
+ *
+ * TODO: ensure that DMA is disabled and no pending DMA
+ * is lurking in the FIFO.
+ */
+static void
+arge_rx_ring_free(struct arge_softc *sc)
+{
+ int i;
+ struct arge_rxdesc *rxd;
+
+ ARGE_LOCK_ASSERT(sc);
+
+ for (i = 0; i < ARGE_RX_RING_COUNT; i++) {
+ rxd = &sc->arge_cdata.arge_rxdesc[i];
+ /* Unmap the mbuf */
+ if (rxd->rx_m != NULL) {
+ bus_dmamap_unload(sc->arge_cdata.arge_rx_tag,
+ rxd->rx_dmamap);
+ m_free(rxd->rx_m);
+ rxd->rx_m = NULL;
+ }
+ }
+}
+
+/*
+ * Initialize an RX descriptor and attach an MBUF cluster.
+ */
+static int
+arge_newbuf(struct arge_softc *sc, int idx)
+{
+ struct arge_desc *desc;
+ struct arge_rxdesc *rxd;
+ struct mbuf *m;
+ bus_dma_segment_t segs[1];
+ bus_dmamap_t map;
+ int nsegs;
+
+ m = m_getcl(M_NOWAIT, MT_DATA, M_PKTHDR);
+ if (m == NULL)
+ return (ENOBUFS);
+ m->m_len = m->m_pkthdr.len = MCLBYTES;
+ m_adj(m, sizeof(uint64_t));
+
+ if (bus_dmamap_load_mbuf_sg(sc->arge_cdata.arge_rx_tag,
+ sc->arge_cdata.arge_rx_sparemap, m, segs, &nsegs, 0) != 0) {
+ m_freem(m);
+ return (ENOBUFS);
+ }
+ KASSERT(nsegs == 1, ("%s: %d segments returned!", __func__, nsegs));
+
+ rxd = &sc->arge_cdata.arge_rxdesc[idx];
+ if (rxd->rx_m != NULL) {
+ bus_dmamap_unload(sc->arge_cdata.arge_rx_tag, rxd->rx_dmamap);
+ }
+ map = rxd->rx_dmamap;
+ rxd->rx_dmamap = sc->arge_cdata.arge_rx_sparemap;
+ sc->arge_cdata.arge_rx_sparemap = map;
+ rxd->rx_m = m;
+ desc = rxd->desc;
+ if (segs[0].ds_addr & 3)
+ panic("RX packet address unaligned");
+ desc->packet_addr = segs[0].ds_addr;
+ desc->packet_ctrl = ARGE_DESC_EMPTY | ARGE_DMASIZE(segs[0].ds_len);
+
+ bus_dmamap_sync(sc->arge_cdata.arge_rx_ring_tag,
+ sc->arge_cdata.arge_rx_ring_map,
+ BUS_DMASYNC_PREWRITE);
+
+ return (0);
+}
+
+static __inline void
+arge_fixup_rx(struct mbuf *m)
+{
+ int i;
+ uint16_t *src, *dst;
+
+ src = mtod(m, uint16_t *);
+ dst = src - 1;
+
+ for (i = 0; i < m->m_len / sizeof(uint16_t); i++) {
+ *dst++ = *src++;
+ }
+
+ if (m->m_len % sizeof(uint16_t))
+ *(uint8_t *)dst = *(uint8_t *)src;
+
+ m->m_data -= ETHER_ALIGN;
+}
+
+#ifdef DEVICE_POLLING
+static int
+arge_poll(struct ifnet *ifp, enum poll_cmd cmd, int count)
+{
+ struct arge_softc *sc = ifp->if_softc;
+ int rx_npkts = 0;
+
+ if (ifp->if_drv_flags & IFF_DRV_RUNNING) {
+ ARGE_LOCK(sc);
+ arge_tx_locked(sc);
+ rx_npkts = arge_rx_locked(sc);
+ ARGE_UNLOCK(sc);
+ }
+
+ return (rx_npkts);
+}
+#endif /* DEVICE_POLLING */
+
+
+static void
+arge_tx_locked(struct arge_softc *sc)
+{
+ struct arge_txdesc *txd;
+ struct arge_desc *cur_tx;
+ struct ifnet *ifp;
+ uint32_t ctrl;
+ int cons, prod;
+
+ ARGE_LOCK_ASSERT(sc);
+
+ cons = sc->arge_cdata.arge_tx_cons;
+ prod = sc->arge_cdata.arge_tx_prod;
+
+ ARGEDEBUG(sc, ARGE_DBG_TX, "%s: cons=%d, prod=%d\n", __func__, cons,
+ prod);
+
+ if (cons == prod)
+ return;
+
+ bus_dmamap_sync(sc->arge_cdata.arge_tx_ring_tag,
+ sc->arge_cdata.arge_tx_ring_map,
+ BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
+
+ ifp = sc->arge_ifp;
+ /*
+ * Go through our tx list and free mbufs for those
+ * frames that have been transmitted.
+ */
+ for (; cons != prod; ARGE_INC(cons, ARGE_TX_RING_COUNT)) {
+ cur_tx = &sc->arge_rdata.arge_tx_ring[cons];
+ ctrl = cur_tx->packet_ctrl;
+ /* Check if descriptor has "finished" flag */
+ if ((ctrl & ARGE_DESC_EMPTY) == 0)
+ break;
+
+ ARGE_WRITE(sc, AR71XX_DMA_TX_STATUS, DMA_TX_STATUS_PKT_SENT);
+
+ sc->arge_cdata.arge_tx_cnt--;
+ ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
+
+ txd = &sc->arge_cdata.arge_txdesc[cons];
+
+ ifp->if_opackets++;
+
+ bus_dmamap_sync(sc->arge_cdata.arge_tx_tag, txd->tx_dmamap,
+ BUS_DMASYNC_POSTWRITE);
+ bus_dmamap_unload(sc->arge_cdata.arge_tx_tag, txd->tx_dmamap);
+
+ /* Free only if it's first descriptor in list */
+ if (txd->tx_m)
+ m_freem(txd->tx_m);
+ txd->tx_m = NULL;
+
+ /* reset descriptor */
+ cur_tx->packet_addr = 0;
+ }
+
+ sc->arge_cdata.arge_tx_cons = cons;
+
+ bus_dmamap_sync(sc->arge_cdata.arge_tx_ring_tag,
+ sc->arge_cdata.arge_tx_ring_map, BUS_DMASYNC_PREWRITE);
+}
+
+
+static int
+arge_rx_locked(struct arge_softc *sc)
+{
+ struct arge_rxdesc *rxd;
+ struct ifnet *ifp = sc->arge_ifp;
+ int cons, prog, packet_len, i;
+ struct arge_desc *cur_rx;
+ struct mbuf *m;
+ int rx_npkts = 0;
+
+ ARGE_LOCK_ASSERT(sc);
+
+ cons = sc->arge_cdata.arge_rx_cons;
+
+ bus_dmamap_sync(sc->arge_cdata.arge_rx_ring_tag,
+ sc->arge_cdata.arge_rx_ring_map,
+ BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
+
+ for (prog = 0; prog < ARGE_RX_RING_COUNT;
+ ARGE_INC(cons, ARGE_RX_RING_COUNT)) {
+ cur_rx = &sc->arge_rdata.arge_rx_ring[cons];
+ rxd = &sc->arge_cdata.arge_rxdesc[cons];
+ m = rxd->rx_m;
+
+ if ((cur_rx->packet_ctrl & ARGE_DESC_EMPTY) != 0)
+ break;
+
+ ARGE_WRITE(sc, AR71XX_DMA_RX_STATUS, DMA_RX_STATUS_PKT_RECVD);
+
+ prog++;
+
+ packet_len = ARGE_DMASIZE(cur_rx->packet_ctrl);
+ bus_dmamap_sync(sc->arge_cdata.arge_rx_tag, rxd->rx_dmamap,
+ BUS_DMASYNC_POSTREAD);
+ m = rxd->rx_m;
+
+ arge_fixup_rx(m);
+ m->m_pkthdr.rcvif = ifp;
+ /* Skip 4 bytes of CRC */
+ m->m_pkthdr.len = m->m_len = packet_len - ETHER_CRC_LEN;
+ ifp->if_ipackets++;
+ rx_npkts++;
+
+ ARGE_UNLOCK(sc);
+ (*ifp->if_input)(ifp, m);
+ ARGE_LOCK(sc);
+ cur_rx->packet_addr = 0;
+ }
+
+ if (prog > 0) {
+
+ i = sc->arge_cdata.arge_rx_cons;
+ for (; prog > 0 ; prog--) {
+ if (arge_newbuf(sc, i) != 0) {
+ device_printf(sc->arge_dev,
+ "Failed to allocate buffer\n");
+ break;
+ }
+ ARGE_INC(i, ARGE_RX_RING_COUNT);
+ }
+
+ bus_dmamap_sync(sc->arge_cdata.arge_rx_ring_tag,
+ sc->arge_cdata.arge_rx_ring_map,
+ BUS_DMASYNC_PREWRITE);
+
+ sc->arge_cdata.arge_rx_cons = cons;
+ }
+
+ return (rx_npkts);
+}
+
+static int
+arge_intr_filter(void *arg)
+{
+ struct arge_softc *sc = arg;
+ uint32_t status, ints;
+
+ status = ARGE_READ(sc, AR71XX_DMA_INTR_STATUS);
+ ints = ARGE_READ(sc, AR71XX_DMA_INTR);
+
+ ARGEDEBUG(sc, ARGE_DBG_INTR, "int mask(filter) = %b\n", ints,
+ "\20\10RX_BUS_ERROR\7RX_OVERFLOW\5RX_PKT_RCVD"
+ "\4TX_BUS_ERROR\2TX_UNDERRUN\1TX_PKT_SENT");
+ ARGEDEBUG(sc, ARGE_DBG_INTR, "status(filter) = %b\n", status,
+ "\20\10RX_BUS_ERROR\7RX_OVERFLOW\5RX_PKT_RCVD"
+ "\4TX_BUS_ERROR\2TX_UNDERRUN\1TX_PKT_SENT");
+
+ if (status & DMA_INTR_ALL) {
+ sc->arge_intr_status |= status;
+ ARGE_WRITE(sc, AR71XX_DMA_INTR, 0);
+ return (FILTER_SCHEDULE_THREAD);
+ }
+
+ sc->arge_intr_status = 0;
+ return (FILTER_STRAY);
+}
+
+static void
+arge_intr(void *arg)
+{
+ struct arge_softc *sc = arg;
+ uint32_t status;
+ struct ifnet *ifp = sc->arge_ifp;
+
+ status = ARGE_READ(sc, AR71XX_DMA_INTR_STATUS);
+ status |= sc->arge_intr_status;
+
+ ARGEDEBUG(sc, ARGE_DBG_INTR, "int status(intr) = %b\n", status,
+ "\20\10\7RX_OVERFLOW\5RX_PKT_RCVD"
+ "\4TX_BUS_ERROR\2TX_UNDERRUN\1TX_PKT_SENT");
+
+ /*
+ * Is it our interrupt at all?
+ */
+ if (status == 0)
+ return;
+
+ if (status & DMA_INTR_RX_BUS_ERROR) {
+ ARGE_WRITE(sc, AR71XX_DMA_RX_STATUS, DMA_RX_STATUS_BUS_ERROR);
+ device_printf(sc->arge_dev, "RX bus error");
+ return;
+ }
+
+ if (status & DMA_INTR_TX_BUS_ERROR) {
+ ARGE_WRITE(sc, AR71XX_DMA_TX_STATUS, DMA_TX_STATUS_BUS_ERROR);
+ device_printf(sc->arge_dev, "TX bus error");
+ return;
+ }
+
+ ARGE_LOCK(sc);
+
+ if (status & DMA_INTR_RX_PKT_RCVD)
+ arge_rx_locked(sc);
+
+ /*
+ * RX overrun disables the receiver.
+ * Clear indication and re-enable rx.
+ */
+ if ( status & DMA_INTR_RX_OVERFLOW) {
+ ARGE_WRITE(sc, AR71XX_DMA_RX_STATUS, DMA_RX_STATUS_OVERFLOW);
+ ARGE_WRITE(sc, AR71XX_DMA_RX_CONTROL, DMA_RX_CONTROL_EN);
+ sc->stats.rx_overflow++;
+ }
+
+ if (status & DMA_INTR_TX_PKT_SENT)
+ arge_tx_locked(sc);
+ /*
+ * Underrun turns off TX. Clear underrun indication.
+ * If there's anything left in the ring, reactivate the tx.
+ */
+ if (status & DMA_INTR_TX_UNDERRUN) {
+ ARGE_WRITE(sc, AR71XX_DMA_TX_STATUS, DMA_TX_STATUS_UNDERRUN);
+ sc->stats.tx_underflow++;
+ ARGEDEBUG(sc, ARGE_DBG_TX, "%s: TX underrun; tx_cnt=%d\n",
+ __func__, sc->arge_cdata.arge_tx_cnt);
+ if (sc->arge_cdata.arge_tx_cnt > 0 ) {
+ ARGE_WRITE(sc, AR71XX_DMA_TX_CONTROL,
+ DMA_TX_CONTROL_EN);
+ }
+ }
+
+ /*
+ * If we've finished TXing and there's space for more packets
+ * to be queued for TX, do so. Otherwise we may end up in a
+ * situation where the interface send queue was filled
+ * whilst the hardware queue was full, then the hardware
+ * queue was drained by the interface send queue wasn't,
+ * and thus if_start() is never called to kick-start
+ * the send process (and all subsequent packets are simply
+ * discarded.
+ *
+ * XXX TODO: make sure that the hardware deals nicely
+ * with the possibility of the queue being enabled above
+ * after a TX underrun, then having the hardware queue added
+ * to below.
+ */
+ if (status & (DMA_INTR_TX_PKT_SENT | DMA_INTR_TX_UNDERRUN) &&
+ (ifp->if_drv_flags & IFF_DRV_OACTIVE) == 0) {
+ if (!IFQ_IS_EMPTY(&ifp->if_snd))
+ arge_start_locked(ifp);
+ }
+
+ /*
+ * We handled all bits, clear status
+ */
+ sc->arge_intr_status = 0;
+ ARGE_UNLOCK(sc);
+ /*
+ * re-enable all interrupts
+ */
+ ARGE_WRITE(sc, AR71XX_DMA_INTR, DMA_INTR_ALL);
+}
+
+
+static void
+arge_tick(void *xsc)
+{
+ struct arge_softc *sc = xsc;
+ struct mii_data *mii;
+
+ ARGE_LOCK_ASSERT(sc);
+
+ if (sc->arge_miibus) {
+ mii = device_get_softc(sc->arge_miibus);
+ mii_tick(mii);
+ callout_reset(&sc->arge_stat_callout, hz, arge_tick, sc);
+ }
+}
+
+int
+arge_multiphy_mediachange(struct ifnet *ifp)
+{
+ struct arge_softc *sc = ifp->if_softc;
+ struct ifmedia *ifm = &sc->arge_ifmedia;
+ struct ifmedia_entry *ife = ifm->ifm_cur;
+
+ if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER)
+ return (EINVAL);
+
+ if (IFM_SUBTYPE(ife->ifm_media) == IFM_AUTO) {
+ device_printf(sc->arge_dev,
+ "AUTO is not supported for multiphy MAC");
+ return (EINVAL);
+ }
+
+ /*
+ * Ignore everything
+ */
+ return (0);
+}
+
+void
+arge_multiphy_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr)
+{
+ struct arge_softc *sc = ifp->if_softc;
+
+ ifmr->ifm_status = IFM_AVALID | IFM_ACTIVE;
+ ifmr->ifm_active = IFM_ETHER | sc->arge_media_type |
+ sc->arge_duplex_mode;
+}
+
+#if defined(ARGE_MDIO)
+static int
+argemdio_probe(device_t dev)
+{
+ device_set_desc(dev, "Atheros AR71xx built-in ethernet interface, MDIO controller");
+ return (0);
+}
+
+static int
+argemdio_attach(device_t dev)
+{
+ struct arge_softc *sc;
+ int error = 0;
+
+ sc = device_get_softc(dev);
+ sc->arge_dev = dev;
+ sc->arge_mac_unit = device_get_unit(dev);
+ sc->arge_rid = 0;
+ sc->arge_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY,
+ &sc->arge_rid, RF_ACTIVE | RF_SHAREABLE);
+ if (sc->arge_res == NULL) {
+ device_printf(dev, "couldn't map memory\n");
+ error = ENXIO;
+ goto fail;
+ }
+
+ /* Reset MAC - required for AR71xx MDIO to successfully occur */
+ arge_reset_mac(sc);
+ /* Reset MII bus */
+ arge_reset_miibus(sc);
+
+ bus_generic_probe(dev);
+ bus_enumerate_hinted_children(dev);
+ error = bus_generic_attach(dev);
+fail:
+ return (error);
+}
+
+static int
+argemdio_detach(device_t dev)
+{
+ return (0);
+}
+
+#endif
Property changes on: trunk/sys/mips/atheros/if_arge.c
___________________________________________________________________
Added: svn:eol-style
## -0,0 +1 ##
+native
\ No newline at end of property
Added: svn:keywords
## -0,0 +1 ##
+MidnightBSD=%H
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+text/plain
\ No newline at end of property
Added: trunk/sys/mips/atheros/if_argevar.h
===================================================================
--- trunk/sys/mips/atheros/if_argevar.h (rev 0)
+++ trunk/sys/mips/atheros/if_argevar.h 2018-05-26 21:55:02 UTC (rev 9987)
@@ -0,0 +1,171 @@
+/* $MidnightBSD$ */
+/*-
+ * Copyright (c) 2009, Oleksandr Tymoshenko
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice unmodified, this list of conditions, and the following
+ * disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ * $FreeBSD: stable/10/sys/mips/atheros/if_argevar.h 261455 2014-02-04 03:36:42Z eadler $
+ */
+
+#ifndef __IF_ARGEVAR_H__
+#define __IF_ARGEVAR_H__
+
+#define ARGE_NPHY 32
+#define ARGE_TX_RING_COUNT 128
+#define ARGE_RX_RING_COUNT 128
+#define ARGE_RX_DMA_SIZE ARGE_RX_RING_COUNT * sizeof(struct arge_desc)
+#define ARGE_TX_DMA_SIZE ARGE_TX_RING_COUNT * sizeof(struct arge_desc)
+#define ARGE_MAXFRAGS 8
+#define ARGE_RING_ALIGN sizeof(struct arge_desc)
+#define ARGE_RX_ALIGN sizeof(uint32_t)
+#define ARGE_MAXFRAGS 8
+#define ARGE_TX_RING_ADDR(sc, i) \
+ ((sc)->arge_rdata.arge_tx_ring_paddr + sizeof(struct arge_desc) * (i))
+#define ARGE_RX_RING_ADDR(sc, i) \
+ ((sc)->arge_rdata.arge_rx_ring_paddr + sizeof(struct arge_desc) * (i))
+#define ARGE_INC(x,y) (x) = (((x) + 1) % y)
+
+
+#define ARGE_MII_TIMEOUT 1000
+
+#define ARGE_LOCK(_sc) mtx_lock(&(_sc)->arge_mtx)
+#define ARGE_UNLOCK(_sc) mtx_unlock(&(_sc)->arge_mtx)
+#define ARGE_LOCK_ASSERT(_sc) mtx_assert(&(_sc)->arge_mtx, MA_OWNED)
+
+/*
+ * register space access macros
+ */
+#define ARGE_WRITE(sc, reg, val) do { \
+ bus_write_4(sc->arge_res, (reg), (val)); \
+ } while (0)
+
+#define ARGE_READ(sc, reg) bus_read_4(sc->arge_res, (reg))
+
+#define ARGE_SET_BITS(sc, reg, bits) \
+ ARGE_WRITE(sc, reg, ARGE_READ(sc, (reg)) | (bits))
+
+#define ARGE_CLEAR_BITS(sc, reg, bits) \
+ ARGE_WRITE(sc, reg, ARGE_READ(sc, (reg)) & ~(bits))
+
+#define ARGE_MDIO_WRITE(_sc, _reg, _val) \
+ ARGE_WRITE((_sc), (_reg), (_val))
+#define ARGE_MDIO_READ(_sc, _reg) \
+ ARGE_READ((_sc), (_reg))
+
+#define ARGE_DESC_EMPTY (1U << 31)
+#define ARGE_DESC_MORE (1 << 24)
+#define ARGE_DESC_SIZE_MASK ((1 << 12) - 1)
+#define ARGE_DMASIZE(len) ((len) & ARGE_DESC_SIZE_MASK)
+struct arge_desc {
+ uint32_t packet_addr;
+ uint32_t packet_ctrl;
+ uint32_t next_desc;
+ uint32_t padding;
+};
+
+struct arge_txdesc {
+ struct mbuf *tx_m;
+ bus_dmamap_t tx_dmamap;
+};
+
+struct arge_rxdesc {
+ struct mbuf *rx_m;
+ bus_dmamap_t rx_dmamap;
+ struct arge_desc *desc;
+};
+
+struct arge_chain_data {
+ bus_dma_tag_t arge_parent_tag;
+ bus_dma_tag_t arge_tx_tag;
+ struct arge_txdesc arge_txdesc[ARGE_TX_RING_COUNT];
+ bus_dma_tag_t arge_rx_tag;
+ struct arge_rxdesc arge_rxdesc[ARGE_RX_RING_COUNT];
+ bus_dma_tag_t arge_tx_ring_tag;
+ bus_dma_tag_t arge_rx_ring_tag;
+ bus_dmamap_t arge_tx_ring_map;
+ bus_dmamap_t arge_rx_ring_map;
+ bus_dmamap_t arge_rx_sparemap;
+ int arge_tx_prod;
+ int arge_tx_cons;
+ int arge_tx_cnt;
+ int arge_rx_cons;
+};
+
+struct arge_ring_data {
+ struct arge_desc *arge_rx_ring;
+ struct arge_desc *arge_tx_ring;
+ bus_addr_t arge_rx_ring_paddr;
+ bus_addr_t arge_tx_ring_paddr;
+};
+
+/*
+ * Allow PLL values to be overridden.
+ */
+struct arge_pll_data {
+ uint32_t pll_10;
+ uint32_t pll_100;
+ uint32_t pll_1000;
+};
+
+struct arge_softc {
+ struct ifnet *arge_ifp; /* interface info */
+ device_t arge_dev;
+ struct ifmedia arge_ifmedia;
+ /*
+ * Media & duples settings for multiPHY MAC
+ */
+ uint32_t arge_media_type;
+ uint32_t arge_duplex_mode;
+ uint32_t arge_phymask;
+ uint8_t arge_eaddr[ETHER_ADDR_LEN];
+ struct resource *arge_res;
+ int arge_rid;
+ struct resource *arge_irq;
+ void *arge_intrhand;
+ device_t arge_miibus;
+ device_t arge_miiproxy;
+ ar71xx_mii_mode arge_miicfg;
+ struct arge_pll_data arge_pllcfg;
+ bus_dma_tag_t arge_parent_tag;
+ bus_dma_tag_t arge_tag;
+ struct mtx arge_mtx;
+ struct callout arge_stat_callout;
+ struct task arge_link_task;
+ struct arge_chain_data arge_cdata;
+ struct arge_ring_data arge_rdata;
+ int arge_link_status;
+ int arge_detach;
+ uint32_t arge_intr_status;
+ int arge_mac_unit;
+ int arge_if_flags;
+ uint32_t arge_debug;
+ struct {
+ uint32_t tx_pkts_unaligned;
+ uint32_t tx_pkts_aligned;
+ uint32_t rx_overflow;
+ uint32_t tx_underflow;
+ } stats;
+};
+
+#endif /* __IF_ARGEVAR_H__ */
Property changes on: trunk/sys/mips/atheros/if_argevar.h
___________________________________________________________________
Added: svn:eol-style
## -0,0 +1 ##
+native
\ No newline at end of property
Added: svn:keywords
## -0,0 +1 ##
+MidnightBSD=%H
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+text/plain
\ No newline at end of property
Added: trunk/sys/mips/atheros/pcf2123_rtc.c
===================================================================
--- trunk/sys/mips/atheros/pcf2123_rtc.c (rev 0)
+++ trunk/sys/mips/atheros/pcf2123_rtc.c 2018-05-26 21:55:02 UTC (rev 9987)
@@ -0,0 +1,205 @@
+/* $MidnightBSD$ */
+/*-
+ * Copyright (c) 2010, Oleksandr Tymoshenko <gonzo at FreeBSD.org>
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice unmodified, this list of conditions, and the following
+ * disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ */
+
+#include <sys/cdefs.h>
+__FBSDID("$FreeBSD: stable/10/sys/mips/atheros/pcf2123_rtc.c 202839 2010-01-22 22:14:12Z gonzo $");
+
+#include <sys/param.h>
+#include <sys/bus.h>
+#include <sys/lock.h>
+#include <sys/time.h>
+#include <sys/clock.h>
+#include <sys/resource.h>
+#include <sys/systm.h>
+#include <sys/rman.h>
+#include <sys/kernel.h>
+#include <sys/module.h>
+
+#include <mips/atheros/pcf2123reg.h>
+
+#include <dev/spibus/spi.h>
+#include "spibus_if.h"
+
+#include "clock_if.h"
+
+#define YEAR_BASE 1970
+#define PCF2123_DELAY 50
+
+struct pcf2123_rtc_softc {
+ device_t dev;
+};
+
+static int pcf2123_rtc_probe(device_t dev);
+static int pcf2123_rtc_attach(device_t dev);
+
+static int pcf2123_rtc_gettime(device_t dev, struct timespec *ts);
+static int pcf2123_rtc_settime(device_t dev, struct timespec *ts);
+
+static int
+pcf2123_rtc_probe(device_t dev)
+{
+
+ device_set_desc(dev, "PCF2123 SPI RTC");
+ return (0);
+}
+
+static int
+pcf2123_rtc_attach(device_t dev)
+{
+ struct pcf2123_rtc_softc *sc;
+ struct spi_command cmd;
+ unsigned char rxBuf[3];
+ unsigned char txBuf[3];
+ int err;
+
+ sc = device_get_softc(dev);
+ sc->dev = dev;
+
+ clock_register(dev, 1000000);
+
+ memset(&cmd, 0, sizeof(cmd));
+ memset(rxBuf, 0, sizeof(rxBuf));
+ memset(txBuf, 0, sizeof(txBuf));
+
+ /* Make sure Ctrl1 and Ctrl2 are zeroes */
+ txBuf[0] = PCF2123_WRITE(PCF2123_REG_CTRL1);
+ cmd.rx_cmd = rxBuf;
+ cmd.tx_cmd = txBuf;
+ cmd.rx_cmd_sz = sizeof(rxBuf);
+ cmd.tx_cmd_sz = sizeof(txBuf);
+ err = SPIBUS_TRANSFER(device_get_parent(dev), dev, &cmd);
+ DELAY(PCF2123_DELAY);
+
+ return (0);
+}
+
+static int
+pcf2123_rtc_gettime(device_t dev, struct timespec *ts)
+{
+ struct clocktime ct;
+ struct spi_command cmd;
+ unsigned char rxTimedate[8];
+ unsigned char txTimedate[8];
+ int err;
+
+ memset(&cmd, 0, sizeof(cmd));
+ memset(rxTimedate, 0, sizeof(rxTimedate));
+ memset(txTimedate, 0, sizeof(txTimedate));
+
+ /*
+ * Counter is stopped when access to time registers is in progress
+ * So there is no need to stop/start counter
+ */
+ /* Start reading from seconds */
+ txTimedate[0] = PCF2123_READ(PCF2123_REG_SECONDS);
+ cmd.rx_cmd = rxTimedate;
+ cmd.tx_cmd = txTimedate;
+ cmd.rx_cmd_sz = sizeof(rxTimedate);
+ cmd.tx_cmd_sz = sizeof(txTimedate);
+ err = SPIBUS_TRANSFER(device_get_parent(dev), dev, &cmd);
+ DELAY(PCF2123_DELAY);
+
+ ct.nsec = 0;
+ ct.sec = FROMBCD(rxTimedate[1] & 0x7f);
+ ct.min = FROMBCD(rxTimedate[2] & 0x7f);
+ ct.hour = FROMBCD(rxTimedate[3] & 0x3f);
+
+ ct.dow = FROMBCD(rxTimedate[5] & 0x3f);
+
+ ct.day = FROMBCD(rxTimedate[4] & 0x3f);
+ ct.mon = FROMBCD(rxTimedate[6] & 0x1f);
+ ct.year = YEAR_BASE + FROMBCD(rxTimedate[7]);
+
+ return (clock_ct_to_ts(&ct, ts));
+}
+
+static int
+pcf2123_rtc_settime(device_t dev, struct timespec *ts)
+{
+ struct clocktime ct;
+ struct pcf2123_rtc_softc *sc;
+ struct spi_command cmd;
+ unsigned char rxTimedate[8];
+ unsigned char txTimedate[8];
+ int err;
+
+ sc = device_get_softc(dev);
+
+ /* Resolution: 1 sec */
+ if (ts->tv_nsec >= 500000000)
+ ts->tv_sec++;
+ ts->tv_nsec = 0;
+ clock_ts_to_ct(ts, &ct);
+
+ memset(&cmd, 0, sizeof(cmd));
+ memset(rxTimedate, 0, sizeof(rxTimedate));
+ memset(txTimedate, 0, sizeof(txTimedate));
+
+ /* Start reading from seconds */
+ cmd.rx_cmd = rxTimedate;
+ cmd.tx_cmd = txTimedate;
+ cmd.rx_cmd_sz = sizeof(rxTimedate);
+ cmd.tx_cmd_sz = sizeof(txTimedate);
+
+ /*
+ * Counter is stopped when access to time registers is in progress
+ * So there is no need to stop/start counter
+ */
+ txTimedate[0] = PCF2123_WRITE(PCF2123_REG_SECONDS);
+ txTimedate[1] = TOBCD(ct.sec);
+ txTimedate[2] = TOBCD(ct.min);
+ txTimedate[3] = TOBCD(ct.hour);
+ txTimedate[4] = TOBCD(ct.day);
+ txTimedate[5] = TOBCD(ct.dow);
+ txTimedate[6] = TOBCD(ct.mon);
+ txTimedate[7] = TOBCD(ct.year - YEAR_BASE);
+
+ err = SPIBUS_TRANSFER(device_get_parent(dev), dev, &cmd);
+ DELAY(PCF2123_DELAY);
+
+ return (err);
+}
+
+static device_method_t pcf2123_rtc_methods[] = {
+ DEVMETHOD(device_probe, pcf2123_rtc_probe),
+ DEVMETHOD(device_attach, pcf2123_rtc_attach),
+
+ DEVMETHOD(clock_gettime, pcf2123_rtc_gettime),
+ DEVMETHOD(clock_settime, pcf2123_rtc_settime),
+
+ { 0, 0 },
+};
+
+static driver_t pcf2123_rtc_driver = {
+ "rtc",
+ pcf2123_rtc_methods,
+ sizeof(struct pcf2123_rtc_softc),
+};
+static devclass_t pcf2123_rtc_devclass;
+
+DRIVER_MODULE(pcf2123_rtc, spibus, pcf2123_rtc_driver, pcf2123_rtc_devclass, 0, 0);
Property changes on: trunk/sys/mips/atheros/pcf2123_rtc.c
___________________________________________________________________
Added: svn:eol-style
## -0,0 +1 ##
+native
\ No newline at end of property
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## -0,0 +1 ##
+MidnightBSD=%H
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+text/plain
\ No newline at end of property
Added: trunk/sys/mips/atheros/pcf2123reg.h
===================================================================
--- trunk/sys/mips/atheros/pcf2123reg.h (rev 0)
+++ trunk/sys/mips/atheros/pcf2123reg.h 2018-05-26 21:55:02 UTC (rev 9987)
@@ -0,0 +1,68 @@
+/* $MidnightBSD$ */
+/*-
+ * Copyright (c) 2009, Oleksandr Tymoshenko <gonzo at FreeBSD.org>
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice unmodified, this list of conditions, and the following
+ * disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ */
+
+/* $FreeBSD: stable/10/sys/mips/atheros/pcf2123reg.h 202839 2010-01-22 22:14:12Z gonzo $ */
+
+#ifndef __PCF2123REG_H__
+#define __PCF2123REG_H__
+
+/* Control and status */
+#define PCF2123_REG_CTRL1 0x0
+#define PCF2123_REG_CTRL2 0x1
+
+/* Time and date */
+#define PCF2123_REG_SECONDS 0x2
+#define PCF2123_REG_MINUTES 0x3
+#define PCF2123_REG_HOURS 0x4
+#define PCF2123_REG_DAYS 0x5
+#define PCF2123_REG_WEEKDAYS 0x6
+#define PCF2123_REG_MONTHS 0x7
+#define PCF2123_REG_YEARS 0x8
+
+/* Alarm registers */
+#define PCF2123_REG_MINUTE_ALARM 0x9
+#define PCF2123_REG_HOUR_ALARM 0xA
+#define PCF2123_REG_DAY_ALARM 0xB
+#define PCF2123_REG_WEEKDAY_ALARM 0xC
+
+/* Offset */
+#define PCF2123_REG_OFFSET 0xD
+
+/* Timer */
+#define PCF2123_REG_TIMER_CLKOUT 0xE
+#define PCF2123_REG_COUNTDOWN_TIMER 0xF
+
+/* Commands */
+#define PCF2123_CMD_READ (1 << 7)
+#define PCF2123_CMD_WRITE (0 << 7)
+
+#define PCF2123_READ(reg) (PCF2123_CMD_READ | (1 << 4) | (reg))
+#define PCF2123_WRITE(reg) (PCF2123_CMD_WRITE | (1 << 4) | (reg))
+
+#endif /* __PCF2123REG_H__ */
+
Property changes on: trunk/sys/mips/atheros/pcf2123reg.h
___________________________________________________________________
Added: svn:eol-style
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+native
\ No newline at end of property
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## -0,0 +1 ##
+MidnightBSD=%H
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+text/plain
\ No newline at end of property
Added: trunk/sys/mips/atheros/std.ar71xx
===================================================================
--- trunk/sys/mips/atheros/std.ar71xx (rev 0)
+++ trunk/sys/mips/atheros/std.ar71xx 2018-05-26 21:55:02 UTC (rev 9987)
@@ -0,0 +1,8 @@
+# $FreeBSD: stable/10/sys/mips/atheros/std.ar71xx 233644 2012-03-29 02:54:35Z jmallett $
+#
+# standard config for all ar71xx based kernels.
+
+files "../atheros/files.ar71xx"
+
+machine mips mips
+cpu CPU_MIPS4KC
Property changes on: trunk/sys/mips/atheros/std.ar71xx
___________________________________________________________________
Added: mnbsd:nokeywords
## -0,0 +1 ##
+MidnightBSD=%H
\ No newline at end of property
Added: trunk/sys/mips/atheros/uart_bus_ar71xx.c
===================================================================
--- trunk/sys/mips/atheros/uart_bus_ar71xx.c (rev 0)
+++ trunk/sys/mips/atheros/uart_bus_ar71xx.c 2018-05-26 21:55:02 UTC (rev 9987)
@@ -0,0 +1,90 @@
+/* $MidnightBSD$ */
+/*-
+ * Copyright (c) 2009, Oleksandr Tymoshenko <gonzo at FreeBSD.org>
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ */
+#include "opt_uart.h"
+
+#include <sys/cdefs.h>
+__FBSDID("$FreeBSD: stable/10/sys/mips/atheros/uart_bus_ar71xx.c 253509 2013-07-21 03:54:39Z adrian $");
+
+#include <sys/param.h>
+#include <sys/systm.h>
+#include <sys/bus.h>
+#include <sys/conf.h>
+#include <sys/kernel.h>
+#include <sys/module.h>
+
+#include <machine/bus.h>
+
+#include <dev/uart/uart.h>
+#include <dev/uart/uart_cpu.h>
+#include <dev/uart/uart_bus.h>
+
+#include <mips/atheros/ar71xxreg.h>
+#include <mips/atheros/ar71xx_cpudef.h>
+
+#include "uart_if.h"
+
+static int uart_ar71xx_probe(device_t dev);
+extern struct uart_class uart_ar71xx_uart_class;
+
+static device_method_t uart_ar71xx_methods[] = {
+ /* Device interface */
+ DEVMETHOD(device_probe, uart_ar71xx_probe),
+ DEVMETHOD(device_attach, uart_bus_attach),
+ DEVMETHOD(device_detach, uart_bus_detach),
+ { 0, 0 }
+};
+
+static driver_t uart_ar71xx_driver = {
+ uart_driver_name,
+ uart_ar71xx_methods,
+ sizeof(struct uart_softc),
+};
+
+extern SLIST_HEAD(uart_devinfo_list, uart_devinfo) uart_sysdevs;
+
+static int
+uart_ar71xx_probe(device_t dev)
+{
+ struct uart_softc *sc;
+ uint64_t freq;
+
+ freq = ar71xx_uart_freq();
+
+ sc = device_get_softc(dev);
+ sc->sc_sysdev = SLIST_FIRST(&uart_sysdevs);
+ sc->sc_class = &uart_ns8250_class;
+ bcopy(&sc->sc_sysdev->bas, &sc->sc_bas, sizeof(sc->sc_bas));
+ sc->sc_sysdev->bas.regshft = 2;
+ sc->sc_sysdev->bas.bst = mips_bus_space_generic;
+ sc->sc_sysdev->bas.bsh = MIPS_PHYS_TO_KSEG1(AR71XX_UART_ADDR) + 3;
+ sc->sc_bas.regshft = 2;
+ sc->sc_bas.bst = mips_bus_space_generic;
+ sc->sc_bas.bsh = MIPS_PHYS_TO_KSEG1(AR71XX_UART_ADDR) + 3;
+
+ return (uart_bus_probe(dev, 2, freq, 0, 0));
+}
+
+DRIVER_MODULE(uart, apb, uart_ar71xx_driver, uart_devclass, 0, 0);
Property changes on: trunk/sys/mips/atheros/uart_bus_ar71xx.c
___________________________________________________________________
Added: svn:eol-style
## -0,0 +1 ##
+native
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## -0,0 +1 ##
+MidnightBSD=%H
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## -0,0 +1 ##
+text/plain
\ No newline at end of property
Added: trunk/sys/mips/atheros/uart_bus_ar933x.c
===================================================================
--- trunk/sys/mips/atheros/uart_bus_ar933x.c (rev 0)
+++ trunk/sys/mips/atheros/uart_bus_ar933x.c 2018-05-26 21:55:02 UTC (rev 9987)
@@ -0,0 +1,92 @@
+/* $MidnightBSD$ */
+/*-
+ * Copyright (c) 2012, Adrian Chadd <adrian at FreeBSD.org>
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ */
+#include "opt_uart.h"
+
+#include <sys/cdefs.h>
+__FBSDID("$FreeBSD: stable/10/sys/mips/atheros/uart_bus_ar933x.c 253509 2013-07-21 03:54:39Z adrian $");
+
+#include <sys/param.h>
+#include <sys/systm.h>
+#include <sys/bus.h>
+#include <sys/conf.h>
+#include <sys/kernel.h>
+#include <sys/module.h>
+
+#include <machine/bus.h>
+
+#include <dev/uart/uart.h>
+#include <dev/uart/uart_cpu.h>
+#include <dev/uart/uart_bus.h>
+
+#include <mips/atheros/ar71xxreg.h>
+#include <mips/atheros/ar71xx_cpudef.h>
+
+#include <mips/atheros/uart_dev_ar933x.h>
+
+#include "uart_if.h"
+
+static int uart_ar933x_probe(device_t dev);
+extern struct uart_class uart_ar933x_uart_class;
+
+static device_method_t uart_ar933x_methods[] = {
+ /* Device interface */
+ DEVMETHOD(device_probe, uart_ar933x_probe),
+ DEVMETHOD(device_attach, uart_bus_attach),
+ DEVMETHOD(device_detach, uart_bus_detach),
+ { 0, 0 }
+};
+
+static driver_t uart_ar933x_driver = {
+ uart_driver_name,
+ uart_ar933x_methods,
+ sizeof(struct uart_softc),
+};
+
+extern SLIST_HEAD(uart_devinfo_list, uart_devinfo) uart_sysdevs;
+
+static int
+uart_ar933x_probe(device_t dev)
+{
+ struct uart_softc *sc;
+ uint64_t freq;
+
+ freq = ar71xx_uart_freq();
+
+ sc = device_get_softc(dev);
+ sc->sc_sysdev = SLIST_FIRST(&uart_sysdevs);
+ sc->sc_class = &uart_ar933x_class;
+ bcopy(&sc->sc_sysdev->bas, &sc->sc_bas, sizeof(sc->sc_bas));
+ sc->sc_sysdev->bas.regshft = 0;
+ sc->sc_sysdev->bas.bst = mips_bus_space_generic;
+ sc->sc_sysdev->bas.bsh = MIPS_PHYS_TO_KSEG1(AR71XX_UART_ADDR);
+ sc->sc_bas.regshft = 0;
+ sc->sc_bas.bst = mips_bus_space_generic;
+ sc->sc_bas.bsh = MIPS_PHYS_TO_KSEG1(AR71XX_UART_ADDR);
+
+ return (uart_bus_probe(dev, 2, freq, 0, 0));
+}
+
+DRIVER_MODULE(uart, apb, uart_ar933x_driver, uart_devclass, 0, 0);
Property changes on: trunk/sys/mips/atheros/uart_bus_ar933x.c
___________________________________________________________________
Added: svn:eol-style
## -0,0 +1 ##
+native
\ No newline at end of property
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## -0,0 +1 ##
+MidnightBSD=%H
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## -0,0 +1 ##
+text/plain
\ No newline at end of property
Added: trunk/sys/mips/atheros/uart_cpu_ar71xx.c
===================================================================
--- trunk/sys/mips/atheros/uart_cpu_ar71xx.c (rev 0)
+++ trunk/sys/mips/atheros/uart_cpu_ar71xx.c 2018-05-26 21:55:02 UTC (rev 9987)
@@ -0,0 +1,77 @@
+/* $MidnightBSD$ */
+/*-
+ * Copyright (c) 2009 Oleksandr Tymoshenko
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ */
+#include "opt_uart.h"
+
+#include <sys/cdefs.h>
+__FBSDID("$FreeBSD: stable/10/sys/mips/atheros/uart_cpu_ar71xx.c 253509 2013-07-21 03:54:39Z adrian $");
+
+#include <sys/param.h>
+#include <sys/systm.h>
+#include <sys/bus.h>
+
+#include <machine/bus.h>
+
+#include <dev/uart/uart.h>
+#include <dev/uart/uart_cpu.h>
+
+#include <mips/atheros/ar71xxreg.h>
+#include <mips/atheros/ar71xx_cpudef.h>
+#include <mips/atheros/ar71xx_bus_space_reversed.h>
+
+bus_space_tag_t uart_bus_space_io;
+bus_space_tag_t uart_bus_space_mem;
+
+int
+uart_cpu_eqres(struct uart_bas *b1, struct uart_bas *b2)
+{
+ return ((b1->bsh == b2->bsh && b1->bst == b2->bst) ? 1 : 0);
+}
+
+int
+uart_cpu_getdev(int devtype, struct uart_devinfo *di)
+{
+ uint64_t freq;
+
+ freq = ar71xx_uart_freq();
+
+ di->ops = uart_getops(&uart_ns8250_class);
+ di->bas.chan = 0;
+ di->bas.bst = ar71xx_bus_space_reversed;
+ di->bas.regshft = 2;
+ di->bas.rclk = freq;
+ di->baudrate = 115200;
+ di->databits = 8;
+ di->stopbits = 1;
+
+ di->parity = UART_PARITY_NONE;
+
+ uart_bus_space_io = NULL;
+ uart_bus_space_mem = ar71xx_bus_space_reversed;
+ di->bas.bsh = MIPS_PHYS_TO_KSEG1(AR71XX_UART_ADDR);
+ return (0);
+}
Property changes on: trunk/sys/mips/atheros/uart_cpu_ar71xx.c
___________________________________________________________________
Added: svn:eol-style
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+native
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+MidnightBSD=%H
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## -0,0 +1 ##
+text/plain
\ No newline at end of property
Added: trunk/sys/mips/atheros/uart_cpu_ar933x.c
===================================================================
--- trunk/sys/mips/atheros/uart_cpu_ar933x.c (rev 0)
+++ trunk/sys/mips/atheros/uart_cpu_ar933x.c 2018-05-26 21:55:02 UTC (rev 9987)
@@ -0,0 +1,79 @@
+/* $MidnightBSD$ */
+/*-
+ * Copyright (c) 2012 Adrian Chadd <adrian at FreeBSD.org>
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ */
+#include "opt_uart.h"
+
+#include <sys/cdefs.h>
+__FBSDID("$FreeBSD: stable/10/sys/mips/atheros/uart_cpu_ar933x.c 253509 2013-07-21 03:54:39Z adrian $");
+
+#include <sys/param.h>
+#include <sys/systm.h>
+#include <sys/bus.h>
+
+#include <machine/bus.h>
+
+#include <dev/uart/uart.h>
+#include <dev/uart/uart_cpu.h>
+
+#include <mips/atheros/ar71xxreg.h>
+#include <mips/atheros/ar71xx_cpudef.h>
+#include <mips/atheros/ar71xx_bus_space_reversed.h>
+
+#include <mips/atheros/uart_dev_ar933x.h>
+
+bus_space_tag_t uart_bus_space_io;
+bus_space_tag_t uart_bus_space_mem;
+
+int
+uart_cpu_eqres(struct uart_bas *b1, struct uart_bas *b2)
+{
+ return ((b1->bsh == b2->bsh && b1->bst == b2->bst) ? 1 : 0);
+}
+
+int
+uart_cpu_getdev(int devtype, struct uart_devinfo *di)
+{
+ uint64_t freq;
+
+ freq = ar71xx_uart_freq();
+
+ di->ops = uart_getops(&uart_ar933x_class);
+ di->bas.chan = 0;
+ di->bas.bst = ar71xx_bus_space_reversed;
+ di->bas.regshft = 0; /* We'll do "correct" dword addressing here */
+ di->bas.rclk = freq;
+ di->baudrate = 115200;
+ di->databits = 8;
+ di->stopbits = 1;
+
+ di->parity = UART_PARITY_NONE;
+
+ uart_bus_space_io = NULL;
+ uart_bus_space_mem = ar71xx_bus_space_reversed;
+ di->bas.bsh = MIPS_PHYS_TO_KSEG1(AR71XX_UART_ADDR);
+ return (0);
+}
Property changes on: trunk/sys/mips/atheros/uart_cpu_ar933x.c
___________________________________________________________________
Added: svn:eol-style
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Added: trunk/sys/mips/atheros/uart_dev_ar933x.c
===================================================================
--- trunk/sys/mips/atheros/uart_dev_ar933x.c (rev 0)
+++ trunk/sys/mips/atheros/uart_dev_ar933x.c 2018-05-26 21:55:02 UTC (rev 9987)
@@ -0,0 +1,787 @@
+/* $MidnightBSD$ */
+/*-
+ * Copyright (c) 2013 Adrian Chadd <adrian at FreeBSD.org>
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+ * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+ * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <sys/cdefs.h>
+__FBSDID("$FreeBSD: stable/10/sys/mips/atheros/uart_dev_ar933x.c 262649 2014-03-01 04:16:54Z imp $");
+
+#include <sys/param.h>
+#include <sys/systm.h>
+#include <sys/bus.h>
+#include <sys/conf.h>
+#include <machine/bus.h>
+
+#include <dev/uart/uart.h>
+#include <dev/uart/uart_cpu.h>
+#include <dev/uart/uart_bus.h>
+
+#include <mips/atheros/ar933x_uart.h>
+
+#include "uart_if.h"
+
+/*
+ * Default system clock is 25MHz; see ar933x_chip.c for how
+ * the startup process determines whether it's 25MHz or 40MHz.
+ */
+#define DEFAULT_RCLK (25 * 1000 * 1000)
+
+#define ar933x_getreg(bas, reg) \
+ bus_space_read_4((bas)->bst, (bas)->bsh, reg)
+#define ar933x_setreg(bas, reg, value) \
+ bus_space_write_4((bas)->bst, (bas)->bsh, reg, value)
+
+
+
+static int
+ar933x_drain(struct uart_bas *bas, int what)
+{
+ int limit;
+
+ if (what & UART_DRAIN_TRANSMITTER) {
+ limit = 10*1024;
+
+ /* Loop over until the TX FIFO shows entirely clear */
+ while (--limit) {
+ if ((ar933x_getreg(bas, AR933X_UART_CS_REG)
+ & AR933X_UART_CS_TX_BUSY) == 0)
+ break;
+ }
+ if (limit == 0) {
+ return (EIO);
+ }
+ }
+
+ if (what & UART_DRAIN_RECEIVER) {
+ limit=10*4096;
+ while (--limit) {
+
+ /* XXX duplicated from ar933x_getc() */
+ /* XXX TODO: refactor! */
+
+ /* If there's nothing to read, stop! */
+ if ((ar933x_getreg(bas, AR933X_UART_DATA_REG) &
+ AR933X_UART_DATA_RX_CSR) == 0) {
+ break;
+ }
+
+ /* Read the top of the RX FIFO */
+ (void) ar933x_getreg(bas, AR933X_UART_DATA_REG);
+
+ /* Remove that entry from said RX FIFO */
+ ar933x_setreg(bas, AR933X_UART_DATA_REG,
+ AR933X_UART_DATA_RX_CSR);
+
+ uart_barrier(bas);
+ DELAY(2);
+ }
+ if (limit == 0) {
+ return (EIO);
+ }
+ }
+ return (0);
+}
+
+/*
+ * Calculate the baud from the given chip configuration parameters.
+ */
+static unsigned long
+ar933x_uart_get_baud(unsigned int clk, unsigned int scale,
+ unsigned int step)
+{
+ uint64_t t;
+ uint32_t div;
+
+ div = (2 << 16) * (scale + 1);
+ t = clk;
+ t *= step;
+ t += (div / 2);
+ t = t / div;
+
+ return (t);
+}
+
+/*
+ * Calculate the scale/step with the lowest possible deviation from
+ * the target baudrate.
+ */
+static void
+ar933x_uart_get_scale_step(struct uart_bas *bas, unsigned int baud,
+ unsigned int *scale, unsigned int *step)
+{
+ unsigned int tscale;
+ uint32_t clk;
+ long min_diff;
+
+ clk = bas->rclk;
+ *scale = 0;
+ *step = 0;
+
+ min_diff = baud;
+ for (tscale = 0; tscale < AR933X_UART_MAX_SCALE; tscale++) {
+ uint64_t tstep;
+ int diff;
+
+ tstep = baud * (tscale + 1);
+ tstep *= (2 << 16);
+ tstep = tstep / clk;
+
+ if (tstep > AR933X_UART_MAX_STEP)
+ break;
+
+ diff = abs(ar933x_uart_get_baud(clk, tscale, tstep) - baud);
+ if (diff < min_diff) {
+ min_diff = diff;
+ *scale = tscale;
+ *step = tstep;
+ }
+ }
+}
+
+static int
+ar933x_param(struct uart_bas *bas, int baudrate, int databits, int stopbits,
+ int parity)
+{
+ /* UART always 8 bits */
+
+ /* UART always 1 stop bit */
+
+ /* UART parity is controllable by bits 0:1, ignore for now */
+
+ /* Set baudrate if required. */
+ if (baudrate > 0) {
+ uint32_t clock_scale, clock_step;
+
+ /* Find the best fit for the given baud rate */
+ ar933x_uart_get_scale_step(bas, baudrate, &clock_scale,
+ &clock_step);
+
+ /*
+ * Program the clock register in its entirety - no need
+ * for Read-Modify-Write.
+ */
+ ar933x_setreg(bas, AR933X_UART_CLOCK_REG,
+ ((clock_scale & AR933X_UART_CLOCK_SCALE_M)
+ << AR933X_UART_CLOCK_SCALE_S) |
+ (clock_step & AR933X_UART_CLOCK_STEP_M));
+ }
+
+ uart_barrier(bas);
+ return (0);
+}
+
+
+/*
+ * Low-level UART interface.
+ */
+static int ar933x_probe(struct uart_bas *bas);
+static void ar933x_init(struct uart_bas *bas, int, int, int, int);
+static void ar933x_term(struct uart_bas *bas);
+static void ar933x_putc(struct uart_bas *bas, int);
+static int ar933x_rxready(struct uart_bas *bas);
+static int ar933x_getc(struct uart_bas *bas, struct mtx *);
+
+static struct uart_ops uart_ar933x_ops = {
+ .probe = ar933x_probe,
+ .init = ar933x_init,
+ .term = ar933x_term,
+ .putc = ar933x_putc,
+ .rxready = ar933x_rxready,
+ .getc = ar933x_getc,
+};
+
+static int
+ar933x_probe(struct uart_bas *bas)
+{
+
+ /* We always know this will be here */
+ return (0);
+}
+
+static void
+ar933x_init(struct uart_bas *bas, int baudrate, int databits, int stopbits,
+ int parity)
+{
+ uint32_t reg;
+
+ /* Setup default parameters */
+ ar933x_param(bas, baudrate, databits, stopbits, parity);
+
+ /* XXX Force enable UART in case it was disabled */
+
+ /* Disable all interrupts */
+ ar933x_setreg(bas, AR933X_UART_INT_EN_REG, 0x00000000);
+
+ /* Disable the host interrupt */
+ reg = ar933x_getreg(bas, AR933X_UART_CS_REG);
+ reg &= ~AR933X_UART_CS_HOST_INT_EN;
+ ar933x_setreg(bas, AR933X_UART_CS_REG, reg);
+
+ uart_barrier(bas);
+
+ /* XXX Set RTS/DTR? */
+}
+
+/*
+ * Detach from console.
+ */
+static void
+ar933x_term(struct uart_bas *bas)
+{
+
+ /* XXX TODO */
+}
+
+static void
+ar933x_putc(struct uart_bas *bas, int c)
+{
+ int limit;
+
+ limit = 250000;
+
+ /* Wait for space in the TX FIFO */
+ while ( ((ar933x_getreg(bas, AR933X_UART_DATA_REG) &
+ AR933X_UART_DATA_TX_CSR) == 0) && --limit)
+ DELAY(4);
+
+ /* Write the actual byte */
+ ar933x_setreg(bas, AR933X_UART_DATA_REG,
+ (c & 0xff) | AR933X_UART_DATA_TX_CSR);
+}
+
+static int
+ar933x_rxready(struct uart_bas *bas)
+{
+
+ /* Wait for a character to come ready */
+ return (!!(ar933x_getreg(bas, AR933X_UART_DATA_REG)
+ & AR933X_UART_DATA_RX_CSR));
+}
+
+static int
+ar933x_getc(struct uart_bas *bas, struct mtx *hwmtx)
+{
+ int c;
+
+ uart_lock(hwmtx);
+
+ /* Wait for a character to come ready */
+ while ((ar933x_getreg(bas, AR933X_UART_DATA_REG) &
+ AR933X_UART_DATA_RX_CSR) == 0) {
+ uart_unlock(hwmtx);
+ DELAY(4);
+ uart_lock(hwmtx);
+ }
+
+ /* Read the top of the RX FIFO */
+ c = ar933x_getreg(bas, AR933X_UART_DATA_REG) & 0xff;
+
+ /* Remove that entry from said RX FIFO */
+ ar933x_setreg(bas, AR933X_UART_DATA_REG, AR933X_UART_DATA_RX_CSR);
+
+ uart_unlock(hwmtx);
+
+ return (c);
+}
+
+/*
+ * High-level UART interface.
+ */
+struct ar933x_softc {
+ struct uart_softc base;
+
+ uint32_t u_ier;
+};
+
+static int ar933x_bus_attach(struct uart_softc *);
+static int ar933x_bus_detach(struct uart_softc *);
+static int ar933x_bus_flush(struct uart_softc *, int);
+static int ar933x_bus_getsig(struct uart_softc *);
+static int ar933x_bus_ioctl(struct uart_softc *, int, intptr_t);
+static int ar933x_bus_ipend(struct uart_softc *);
+static int ar933x_bus_param(struct uart_softc *, int, int, int, int);
+static int ar933x_bus_probe(struct uart_softc *);
+static int ar933x_bus_receive(struct uart_softc *);
+static int ar933x_bus_setsig(struct uart_softc *, int);
+static int ar933x_bus_transmit(struct uart_softc *);
+static void ar933x_bus_grab(struct uart_softc *);
+static void ar933x_bus_ungrab(struct uart_softc *);
+
+static kobj_method_t ar933x_methods[] = {
+ KOBJMETHOD(uart_attach, ar933x_bus_attach),
+ KOBJMETHOD(uart_detach, ar933x_bus_detach),
+ KOBJMETHOD(uart_flush, ar933x_bus_flush),
+ KOBJMETHOD(uart_getsig, ar933x_bus_getsig),
+ KOBJMETHOD(uart_ioctl, ar933x_bus_ioctl),
+ KOBJMETHOD(uart_ipend, ar933x_bus_ipend),
+ KOBJMETHOD(uart_param, ar933x_bus_param),
+ KOBJMETHOD(uart_probe, ar933x_bus_probe),
+ KOBJMETHOD(uart_receive, ar933x_bus_receive),
+ KOBJMETHOD(uart_setsig, ar933x_bus_setsig),
+ KOBJMETHOD(uart_transmit, ar933x_bus_transmit),
+ KOBJMETHOD(uart_grab, ar933x_bus_grab),
+ KOBJMETHOD(uart_ungrab, ar933x_bus_ungrab),
+ { 0, 0 }
+};
+
+struct uart_class uart_ar933x_class = {
+ "ar933x",
+ ar933x_methods,
+ sizeof(struct ar933x_softc),
+ .uc_ops = &uart_ar933x_ops,
+ .uc_range = 8,
+ .uc_rclk = DEFAULT_RCLK
+};
+
+#define SIGCHG(c, i, s, d) \
+ if (c) { \
+ i |= (i & s) ? s : s | d; \
+ } else { \
+ i = (i & s) ? (i & ~s) | d : i; \
+ }
+
+static int
+ar933x_bus_attach(struct uart_softc *sc)
+{
+ struct ar933x_softc *u = (struct ar933x_softc *)sc;
+ struct uart_bas *bas = &sc->sc_bas;
+ uint32_t reg;
+
+ /* XXX TODO: flush transmitter */
+
+ /*
+ * Setup initial interrupt notifications.
+ *
+ * XXX for now, just RX FIFO valid.
+ * Later on (when they're handled), also handle
+ * RX errors/overflow.
+ */
+ u->u_ier = AR933X_UART_INT_RX_VALID;
+
+ /* Enable RX interrupts to kick-start things */
+ ar933x_setreg(bas, AR933X_UART_INT_EN_REG, u->u_ier);
+
+ /* Enable the host interrupt now */
+ reg = ar933x_getreg(bas, AR933X_UART_CS_REG);
+ reg |= AR933X_UART_CS_HOST_INT_EN;
+ ar933x_setreg(bas, AR933X_UART_CS_REG, reg);
+
+ return (0);
+}
+
+static int
+ar933x_bus_detach(struct uart_softc *sc)
+{
+ struct uart_bas *bas = &sc->sc_bas;
+ uint32_t reg;
+
+ /* Disable all interrupts */
+ ar933x_setreg(bas, AR933X_UART_INT_EN_REG, 0x00000000);
+
+ /* Disable the host interrupt */
+ reg = ar933x_getreg(bas, AR933X_UART_CS_REG);
+ reg &= ~AR933X_UART_CS_HOST_INT_EN;
+ ar933x_setreg(bas, AR933X_UART_CS_REG, reg);
+ uart_barrier(bas);
+
+ return (0);
+}
+
+static int
+ar933x_bus_flush(struct uart_softc *sc, int what)
+{
+ struct uart_bas *bas;
+
+ bas = &sc->sc_bas;
+ uart_lock(sc->sc_hwmtx);
+ ar933x_drain(bas, what);
+ uart_unlock(sc->sc_hwmtx);
+
+ return (0);
+}
+
+static int
+ar933x_bus_getsig(struct uart_softc *sc)
+{
+ uint32_t sig = sc->sc_hwsig;
+
+ /*
+ * For now, let's just return that DSR/DCD/CTS is asserted.
+ *
+ * XXX TODO: actually verify whether this is correct!
+ */
+ SIGCHG(1, sig, SER_DSR, SER_DDSR);
+ SIGCHG(1, sig, SER_CTS, SER_DCTS);
+ SIGCHG(1, sig, SER_DCD, SER_DDCD);
+ SIGCHG(1, sig, SER_RI, SER_DRI);
+
+ sc->sc_hwsig = sig & ~SER_MASK_DELTA;
+
+ return (sig);
+}
+
+static int
+ar933x_bus_ioctl(struct uart_softc *sc, int request, intptr_t data)
+{
+#if 0
+ struct uart_bas *bas;
+ int baudrate, divisor, error;
+ uint8_t efr, lcr;
+
+ bas = &sc->sc_bas;
+ error = 0;
+ uart_lock(sc->sc_hwmtx);
+ switch (request) {
+ case UART_IOCTL_BREAK:
+ lcr = uart_getreg(bas, REG_LCR);
+ if (data)
+ lcr |= LCR_SBREAK;
+ else
+ lcr &= ~LCR_SBREAK;
+ uart_setreg(bas, REG_LCR, lcr);
+ uart_barrier(bas);
+ break;
+ case UART_IOCTL_IFLOW:
+ lcr = uart_getreg(bas, REG_LCR);
+ uart_barrier(bas);
+ uart_setreg(bas, REG_LCR, 0xbf);
+ uart_barrier(bas);
+ efr = uart_getreg(bas, REG_EFR);
+ if (data)
+ efr |= EFR_RTS;
+ else
+ efr &= ~EFR_RTS;
+ uart_setreg(bas, REG_EFR, efr);
+ uart_barrier(bas);
+ uart_setreg(bas, REG_LCR, lcr);
+ uart_barrier(bas);
+ break;
+ case UART_IOCTL_OFLOW:
+ lcr = uart_getreg(bas, REG_LCR);
+ uart_barrier(bas);
+ uart_setreg(bas, REG_LCR, 0xbf);
+ uart_barrier(bas);
+ efr = uart_getreg(bas, REG_EFR);
+ if (data)
+ efr |= EFR_CTS;
+ else
+ efr &= ~EFR_CTS;
+ uart_setreg(bas, REG_EFR, efr);
+ uart_barrier(bas);
+ uart_setreg(bas, REG_LCR, lcr);
+ uart_barrier(bas);
+ break;
+ case UART_IOCTL_BAUD:
+ lcr = uart_getreg(bas, REG_LCR);
+ uart_setreg(bas, REG_LCR, lcr | LCR_DLAB);
+ uart_barrier(bas);
+ divisor = uart_getreg(bas, REG_DLL) |
+ (uart_getreg(bas, REG_DLH) << 8);
+ uart_barrier(bas);
+ uart_setreg(bas, REG_LCR, lcr);
+ uart_barrier(bas);
+ baudrate = (divisor > 0) ? bas->rclk / divisor / 16 : 0;
+ if (baudrate > 0)
+ *(int*)data = baudrate;
+ else
+ error = ENXIO;
+ break;
+ default:
+ error = EINVAL;
+ break;
+ }
+ uart_unlock(sc->sc_hwmtx);
+ return (error);
+#endif
+ return (ENXIO);
+}
+
+/*
+ * Bus interrupt handler.
+ *
+ * For now, system interrupts are disabled.
+ * So this is just called from a callout in uart_core.c
+ * to poll various state.
+ */
+static int
+ar933x_bus_ipend(struct uart_softc *sc)
+{
+ struct ar933x_softc *u = (struct ar933x_softc *)sc;
+ struct uart_bas *bas = &sc->sc_bas;
+ int ipend = 0;
+ uint32_t isr;
+
+ uart_lock(sc->sc_hwmtx);
+
+ /*
+ * Fetch/ACK the ISR status.
+ */
+ isr = ar933x_getreg(bas, AR933X_UART_INT_REG);
+ ar933x_setreg(bas, AR933X_UART_INT_REG, isr);
+ uart_barrier(bas);
+
+ /*
+ * RX ready - notify upper layer.
+ */
+ if (isr & AR933X_UART_INT_RX_VALID) {
+ ipend |= SER_INT_RXREADY;
+ }
+
+ /*
+ * If we get this interrupt, we should disable
+ * it from the interrupt mask and inform the uart
+ * driver appropriately.
+ *
+ * We can't keep setting SER_INT_TXIDLE or SER_INT_SIGCHG
+ * all the time or IO stops working. So we will always
+ * clear this interrupt if we get it, then we only signal
+ * the upper layer if we were doing active TX in the
+ * first place.
+ *
+ * Also, the name is misleading. This actually means
+ * "the FIFO is almost empty." So if we just write some
+ * more data to the FIFO without checking whether it can
+ * take said data, we'll overflow the thing.
+ *
+ * Unfortunately the FreeBSD uart device has no concept of
+ * partial UART writes - it expects that the whole buffer
+ * is written to the hardware. Thus for now, ar933x_bus_transmit()
+ * will wait for the FIFO to finish draining before it pushes
+ * more frames into it.
+ */
+ if (isr & AR933X_UART_INT_TX_EMPTY) {
+ /*
+ * Update u_ier to disable TX notifications; update hardware
+ */
+ u->u_ier &= ~AR933X_UART_INT_TX_EMPTY;
+ ar933x_setreg(bas, AR933X_UART_INT_EN_REG, u->u_ier);
+ uart_barrier(bas);
+ }
+
+ /*
+ * Only signal TX idle if we're not busy transmitting.
+ */
+ if (sc->sc_txbusy) {
+ if (isr & AR933X_UART_INT_TX_EMPTY) {
+ ipend |= SER_INT_TXIDLE;
+ } else {
+ ipend |= SER_INT_SIGCHG;
+ }
+ }
+
+ uart_unlock(sc->sc_hwmtx);
+ return (ipend);
+}
+
+static int
+ar933x_bus_param(struct uart_softc *sc, int baudrate, int databits,
+ int stopbits, int parity)
+{
+ struct uart_bas *bas;
+ int error;
+
+ bas = &sc->sc_bas;
+ uart_lock(sc->sc_hwmtx);
+ error = ar933x_param(bas, baudrate, databits, stopbits, parity);
+ uart_unlock(sc->sc_hwmtx);
+ return (error);
+}
+
+static int
+ar933x_bus_probe(struct uart_softc *sc)
+{
+ struct uart_bas *bas;
+ int error;
+
+ bas = &sc->sc_bas;
+
+ error = ar933x_probe(bas);
+ if (error)
+ return (error);
+
+ /* Reset FIFOs. */
+ ar933x_drain(bas, UART_FLUSH_RECEIVER|UART_FLUSH_TRANSMITTER);
+
+ /* XXX TODO: actually find out what the FIFO depth is! */
+ sc->sc_rxfifosz = 16;
+ sc->sc_txfifosz = 16;
+
+ return (0);
+}
+
+static int
+ar933x_bus_receive(struct uart_softc *sc)
+{
+ struct uart_bas *bas = &sc->sc_bas;
+ int xc;
+
+ uart_lock(sc->sc_hwmtx);
+
+ /* Loop over until we are full, or no data is available */
+ while (ar933x_rxready(bas)) {
+ if (uart_rx_full(sc)) {
+ sc->sc_rxbuf[sc->sc_rxput] = UART_STAT_OVERRUN;
+ break;
+ }
+
+ /* Read the top of the RX FIFO */
+ xc = ar933x_getreg(bas, AR933X_UART_DATA_REG) & 0xff;
+
+ /* Remove that entry from said RX FIFO */
+ ar933x_setreg(bas, AR933X_UART_DATA_REG,
+ AR933X_UART_DATA_RX_CSR);
+ uart_barrier(bas);
+
+ /* XXX frame, parity error */
+ uart_rx_put(sc, xc);
+ }
+
+ /*
+ * XXX TODO: Discard everything left in the Rx FIFO?
+ * XXX only if we've hit an overrun condition?
+ */
+
+ uart_unlock(sc->sc_hwmtx);
+
+ return (0);
+}
+
+static int
+ar933x_bus_setsig(struct uart_softc *sc, int sig)
+{
+#if 0
+ struct ar933x_softc *ns8250 = (struct ar933x_softc*)sc;
+ struct uart_bas *bas;
+ uint32_t new, old;
+
+ bas = &sc->sc_bas;
+ do {
+ old = sc->sc_hwsig;
+ new = old;
+ if (sig & SER_DDTR) {
+ SIGCHG(sig & SER_DTR, new, SER_DTR,
+ SER_DDTR);
+ }
+ if (sig & SER_DRTS) {
+ SIGCHG(sig & SER_RTS, new, SER_RTS,
+ SER_DRTS);
+ }
+ } while (!atomic_cmpset_32(&sc->sc_hwsig, old, new));
+ uart_lock(sc->sc_hwmtx);
+ ns8250->mcr &= ~(MCR_DTR|MCR_RTS);
+ if (new & SER_DTR)
+ ns8250->mcr |= MCR_DTR;
+ if (new & SER_RTS)
+ ns8250->mcr |= MCR_RTS;
+ uart_setreg(bas, REG_MCR, ns8250->mcr);
+ uart_barrier(bas);
+ uart_unlock(sc->sc_hwmtx);
+#endif
+ return (0);
+}
+
+/*
+ * Write the current transmit buffer to the TX FIFO.
+ *
+ * Unfortunately the FreeBSD uart device has no concept of
+ * partial UART writes - it expects that the whole buffer
+ * is written to the hardware. Thus for now, this will wait for
+ * the FIFO to finish draining before it pushes more frames into it.
+ *
+ * If non-blocking operation is truely needed here, either
+ * the FreeBSD uart device will need to handle partial writes
+ * in xxx_bus_transmit(), or we'll need to do TX FIFO buffering
+ * of our own here.
+ */
+static int
+ar933x_bus_transmit(struct uart_softc *sc)
+{
+ struct uart_bas *bas = &sc->sc_bas;
+ struct ar933x_softc *u = (struct ar933x_softc *)sc;
+ int i;
+
+ uart_lock(sc->sc_hwmtx);
+
+ /* Wait for the FIFO to be clear - see above */
+ while (ar933x_getreg(bas, AR933X_UART_CS_REG) &
+ AR933X_UART_CS_TX_BUSY)
+ ;
+
+ /*
+ * Write some data!
+ */
+ for (i = 0; i < sc->sc_txdatasz; i++) {
+ /* Write the TX data */
+ ar933x_setreg(bas, AR933X_UART_DATA_REG,
+ (sc->sc_txbuf[i] & 0xff) | AR933X_UART_DATA_TX_CSR);
+ uart_barrier(bas);
+ }
+
+ /*
+ * Now that we're transmitting, get interrupt notification
+ * when the FIFO is (almost) empty - see above.
+ */
+ u->u_ier |= AR933X_UART_INT_TX_EMPTY;
+ ar933x_setreg(bas, AR933X_UART_INT_EN_REG, u->u_ier);
+ uart_barrier(bas);
+
+ /*
+ * Inform the upper layer that we are presently transmitting
+ * data to the hardware; this will be cleared when the
+ * TXIDLE interrupt occurs.
+ */
+ sc->sc_txbusy = 1;
+ uart_unlock(sc->sc_hwmtx);
+
+ return (0);
+}
+
+static void
+ar933x_bus_grab(struct uart_softc *sc)
+{
+ struct uart_bas *bas = &sc->sc_bas;
+ uint32_t reg;
+
+ /* Disable the host interrupt now */
+ uart_lock(sc->sc_hwmtx);
+ reg = ar933x_getreg(bas, AR933X_UART_CS_REG);
+ reg &= ~AR933X_UART_CS_HOST_INT_EN;
+ ar933x_setreg(bas, AR933X_UART_CS_REG, reg);
+ uart_unlock(sc->sc_hwmtx);
+}
+
+static void
+ar933x_bus_ungrab(struct uart_softc *sc)
+{
+ struct uart_bas *bas = &sc->sc_bas;
+ uint32_t reg;
+
+ /* Enable the host interrupt now */
+ uart_lock(sc->sc_hwmtx);
+ reg = ar933x_getreg(bas, AR933X_UART_CS_REG);
+ reg |= AR933X_UART_CS_HOST_INT_EN;
+ ar933x_setreg(bas, AR933X_UART_CS_REG, reg);
+ uart_unlock(sc->sc_hwmtx);
+}
Property changes on: trunk/sys/mips/atheros/uart_dev_ar933x.c
___________________________________________________________________
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+native
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+MidnightBSD=%H
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+text/plain
\ No newline at end of property
Added: trunk/sys/mips/atheros/uart_dev_ar933x.h
===================================================================
--- trunk/sys/mips/atheros/uart_dev_ar933x.h (rev 0)
+++ trunk/sys/mips/atheros/uart_dev_ar933x.h 2018-05-26 21:55:02 UTC (rev 9987)
@@ -0,0 +1,34 @@
+/* $MidnightBSD$ */
+/*-
+ * Copyright (c) 2013 Adrian Chadd <adrian at FreeBSD.org>
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+ * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+ * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * $FreeBSD: stable/10/sys/mips/atheros/uart_dev_ar933x.h 248843 2013-03-28 19:27:06Z adrian $
+ */
+#ifndef __UART_DEV_AR933X__
+#define __UART_DEV_AR933X__
+
+extern struct uart_class uart_ar933x_class;
+
+#endif
Property changes on: trunk/sys/mips/atheros/uart_dev_ar933x.h
___________________________________________________________________
Added: svn:eol-style
## -0,0 +1 ##
+native
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Added: svn:keywords
## -0,0 +1 ##
+MidnightBSD=%H
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## -0,0 +1 ##
+text/plain
\ No newline at end of property
Added: trunk/sys/mips/beri/beri_machdep.c
===================================================================
--- trunk/sys/mips/beri/beri_machdep.c (rev 0)
+++ trunk/sys/mips/beri/beri_machdep.c 2018-05-26 21:55:02 UTC (rev 9987)
@@ -0,0 +1,263 @@
+/* $MidnightBSD$ */
+/*-
+ * Copyright (c) 2006 Wojciech A. Koszek <wkoszek at FreeBSD.org>
+ * Copyright (c) 2012 Robert N. M. Watson
+ * All rights reserved.
+ *
+ * This software was developed by SRI International and the University of
+ * Cambridge Computer Laboratory under DARPA/AFRL contract (FA8750-10-C-0237)
+ * ("CTSRD"), as part of the DARPA CRASH research programme.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ */
+#include <sys/cdefs.h>
+__FBSDID("$FreeBSD: stable/10/sys/mips/beri/beri_machdep.c 270058 2014-08-16 14:14:29Z bz $");
+
+#include "opt_ddb.h"
+#include "opt_platform.h"
+
+#include <sys/param.h>
+#include <sys/conf.h>
+#include <sys/kernel.h>
+#include <sys/systm.h>
+#include <sys/imgact.h>
+#include <sys/bio.h>
+#include <sys/buf.h>
+#include <sys/bus.h>
+#include <sys/cpu.h>
+#include <sys/cons.h>
+#include <sys/exec.h>
+#include <sys/linker.h>
+#include <sys/ucontext.h>
+#include <sys/proc.h>
+#include <sys/kdb.h>
+#include <sys/ptrace.h>
+#include <sys/reboot.h>
+#include <sys/signalvar.h>
+#include <sys/sysent.h>
+#include <sys/sysproto.h>
+#include <sys/user.h>
+
+#ifdef FDT
+#include <dev/fdt/fdt_common.h>
+#include <dev/ofw/openfirm.h>
+#endif
+
+#include <vm/vm.h>
+#include <vm/vm_object.h>
+#include <vm/vm_page.h>
+
+#include <machine/clock.h>
+#include <machine/cpu.h>
+#include <machine/cpuregs.h>
+#include <machine/hwfunc.h>
+#include <machine/md_var.h>
+#include <machine/metadata.h>
+#include <machine/pmap.h>
+#include <machine/trap.h>
+
+extern int *edata;
+extern int *end;
+
+void
+platform_cpu_init()
+{
+ /* Nothing special */
+}
+
+static void
+mips_init(void)
+{
+ int i;
+
+ for (i = 0; i < 10; i++) {
+ phys_avail[i] = 0;
+ }
+
+ /* phys_avail regions are in bytes */
+ phys_avail[0] = MIPS_KSEG0_TO_PHYS(kernel_kseg0_end);
+ phys_avail[1] = ctob(realmem);
+
+ dump_avail[0] = phys_avail[0];
+ dump_avail[1] = phys_avail[1];
+
+ physmem = realmem;
+
+ init_param1();
+ init_param2(physmem);
+ mips_cpu_init();
+ pmap_bootstrap();
+ mips_proc0_init();
+ mutex_init();
+ kdb_init();
+#ifdef KDB
+ if (boothowto & RB_KDB)
+ kdb_enter(KDB_WHY_BOOTFLAGS, "Boot flags requested debugger");
+#endif
+}
+
+/*
+ * Perform a board-level soft-reset.
+ */
+void
+platform_reset(void)
+{
+
+ /* XXX SMP will likely require us to do more. */
+ __asm__ __volatile__(
+ "mfc0 $k0, $12\n\t"
+ "li $k1, 0x00100000\n\t"
+ "or $k0, $k0, $k1\n\t"
+ "mtc0 $k0, $12\n");
+ for( ; ; )
+ __asm__ __volatile("wait");
+}
+
+#ifdef FDT
+/* Parse cmd line args as env - copied from xlp_machdep. */
+/* XXX-BZ this should really be centrally provided for all (boot) code. */
+static void
+_parse_bootargs(char *cmdline)
+{
+ char *n, *v;
+
+ while ((v = strsep(&cmdline, " \n")) != NULL) {
+ if (*v == '\0')
+ continue;
+ if (*v == '-') {
+ while (*v != '\0') {
+ v++;
+ switch (*v) {
+ case 'a': boothowto |= RB_ASKNAME; break;
+ /* Someone should simulate that ;-) */
+ case 'C': boothowto |= RB_CDROM; break;
+ case 'd': boothowto |= RB_KDB; break;
+ case 'D': boothowto |= RB_MULTIPLE; break;
+ case 'm': boothowto |= RB_MUTE; break;
+ case 'g': boothowto |= RB_GDB; break;
+ case 'h': boothowto |= RB_SERIAL; break;
+ case 'p': boothowto |= RB_PAUSE; break;
+ case 'r': boothowto |= RB_DFLTROOT; break;
+ case 's': boothowto |= RB_SINGLE; break;
+ case 'v': boothowto |= RB_VERBOSE; break;
+ }
+ }
+ } else {
+ n = strsep(&v, "=");
+ if (v == NULL)
+ setenv(n, "1");
+ else
+ setenv(n, v);
+ }
+ }
+}
+#endif
+
+void
+platform_start(__register_t a0, __register_t a1, __register_t a2,
+ __register_t a3)
+{
+ vm_offset_t kernend;
+ uint64_t platform_counter_freq;
+ int argc = a0;
+ char **argv = (char **)a1;
+ char **envp = (char **)a2;
+ unsigned int memsize = a3;
+#ifdef FDT
+ char buf[2048]; /* early stack supposedly big enough */
+ vm_offset_t dtbp;
+ phandle_t chosen;
+ void *kmdp;
+#endif
+ int i;
+
+ /* clear the BSS and SBSS segments */
+ kernend = (vm_offset_t)&end;
+ memset(&edata, 0, kernend - (vm_offset_t)(&edata));
+
+ mips_postboot_fixup();
+
+ mips_pcpu0_init();
+
+#ifdef FDT
+ /*
+ * Find the dtb passed in by the boot loader (currently fictional).
+ */
+ kmdp = preload_search_by_type("elf kernel");
+ if (kmdp != NULL)
+ dtbp = MD_FETCH(kmdp, MODINFOMD_DTBP, vm_offset_t);
+ else
+ dtbp = (vm_offset_t)NULL;
+
+#if defined(FDT_DTB_STATIC)
+ /*
+ * In case the device tree blob was not retrieved (from metadata) try
+ * to use the statically embedded one.
+ */
+ if (dtbp == (vm_offset_t)NULL)
+ dtbp = (vm_offset_t)&fdt_static_dtb;
+#else
+#error "Non-static FDT not yet supported on BERI"
+#endif
+
+ if (OF_install(OFW_FDT, 0) == FALSE)
+ while (1);
+ if (OF_init((void *)dtbp) != 0)
+ while (1);
+
+ /*
+ * Get bootargs from FDT if specified.
+ */
+ chosen = OF_finddevice("/chosen");
+ if (OF_getprop(chosen, "bootargs", buf, sizeof(buf)) != -1)
+ _parse_bootargs(buf);
+#endif
+
+ /*
+ * XXXRW: We have no way to compare wallclock time to cycle rate on
+ * BERI, so for now assume we run at the MALTA default (100MHz).
+ */
+ platform_counter_freq = MIPS_DEFAULT_HZ;
+ mips_timer_early_init(platform_counter_freq);
+
+ cninit();
+ printf("entry: platform_start()\n");
+
+ bootverbose = 1;
+ if (bootverbose) {
+ printf("cmd line: ");
+ for (i = 0; i < argc; i++)
+ printf("%s ", argv[i]);
+ printf("\n");
+
+ printf("envp:\n");
+ for (i = 0; envp[i]; i += 2)
+ printf("\t%s = %s\n", envp[i], envp[i+1]);
+
+ printf("memsize = %08x\n", memsize);
+ }
+
+ realmem = btoc(memsize);
+ mips_init();
+
+ mips_timer_init_params(platform_counter_freq, 0);
+}
Property changes on: trunk/sys/mips/beri/beri_machdep.c
___________________________________________________________________
Added: svn:eol-style
## -0,0 +1 ##
+native
\ No newline at end of property
Added: svn:keywords
## -0,0 +1 ##
+MidnightBSD=%H
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+text/plain
\ No newline at end of property
Added: trunk/sys/mips/beri/beri_pic.c
===================================================================
--- trunk/sys/mips/beri/beri_pic.c (rev 0)
+++ trunk/sys/mips/beri/beri_pic.c 2018-05-26 21:55:02 UTC (rev 9987)
@@ -0,0 +1,704 @@
+/* $MidnightBSD$ */
+/*-
+ * Copyright (c) 2013 SRI International
+ * All rights reserved.
+ *
+ * This software was developed by SRI International and the University of
+ * Cambridge Computer Laboratory under DARPA/AFRL contract (FA8750-10-C-0237)
+ * ("CTSRD"), as part of the DARPA CRASH research programme.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ */
+
+#include <sys/cdefs.h>
+__FBSDID("$FreeBSD: stable/10/sys/mips/beri/beri_pic.c 266152 2014-05-15 16:11:06Z ian $");
+
+#include <sys/param.h>
+#include <sys/kernel.h>
+#include <sys/lock.h>
+#include <sys/malloc.h>
+#include <sys/module.h>
+#include <sys/mutex.h>
+#include <sys/systm.h>
+#include <sys/bus.h>
+
+#include <machine/bus.h>
+#include <machine/intr_machdep.h>
+
+#include <dev/ofw/ofw_bus.h>
+#include <dev/ofw/ofw_bus_subr.h>
+
+#include <dev/fdt/fdt_common.h>
+
+#include "fdt_ic_if.h"
+
+struct beripic_softc;
+
+static uint64_t bp_read_cfg(struct beripic_softc *, int);
+static void bp_write_cfg(struct beripic_softc *, int, uint64_t);
+static void bp_detach_resources(device_t);
+static char *bp_strconfig(uint64_t, char *, size_t);
+static void bp_config_source(device_t, int, int, u_long, u_long);
+#ifdef __mips__
+static void bp_set_counter_name(device_t, device_t, int);
+#endif
+
+static int beripic_fdt_probe(device_t);
+static int beripic_fdt_attach(device_t);
+
+static int beripic_activate_intr(device_t, struct resource *);
+static struct resource *
+ beripic_alloc_intr(device_t, device_t, int *, u_long, u_int);
+static int beripic_config_intr(device_t, int, enum intr_trigger,
+ enum intr_polarity);
+static int beripic_release_intr(device_t, struct resource *);
+static int beripic_setup_intr(device_t, device_t, struct resource *,
+ int, driver_filter_t *, driver_intr_t *, void *, void **);
+static int beripic_teardown_intr(device_t, device_t, struct resource *,
+ void *);
+
+static int beripic_filter(void *);
+static void beripic_intr(void *);
+
+#define BP_MAX_HARD_IRQS 6
+#define BP_FIRST_SOFT 64
+
+struct beripic_softc {
+ device_t bp_dev;
+ struct resource *bp_cfg_res;
+ struct resource *bp_read_res;
+ struct resource *bp_set_res;
+ struct resource *bp_clear_res;
+ int bp_cfg_rid;
+ int bp_read_rid;
+ int bp_set_rid;
+ int bp_clear_rid;
+ bus_space_tag_t bp_cfg_bst;
+ bus_space_tag_t bp_read_bst;
+ bus_space_tag_t bp_set_bst;
+ bus_space_tag_t bp_clear_bst;
+ bus_space_handle_t bp_cfg_bsh;
+ bus_space_handle_t bp_read_bsh;
+ bus_space_handle_t bp_set_bsh;
+ bus_space_handle_t bp_clear_bsh;
+
+ struct resource *bp_irqs[BP_MAX_HARD_IRQS];
+ int bp_irq_rids[BP_MAX_HARD_IRQS];
+ int bp_nirqs;
+ int bp_next_irq;
+ int bp_next_tid;
+
+ int bp_nthreads;
+
+ int bp_nhard;
+ int bp_nsoft;
+ int bp_nsrcs;
+ struct rman bp_src_rman;
+
+#ifdef __mips__
+ mips_intrcnt_t *bp_counters;
+#endif
+
+ struct mtx bp_cfgmtx;
+};
+
+struct beripic_intr_arg {
+ driver_filter_t *filter;
+ driver_intr_t *intr;
+ void *arg;
+ struct resource *irq;
+#ifdef __mips__
+ mips_intrcnt_t counter;
+#endif
+};
+
+struct beripic_cookie {
+ struct beripic_intr_arg *bpia;
+ struct resource *hirq;
+ void *cookie;
+};
+
+#define BP_CFG_MASK_E 0x80000000ull
+#define BP_CFG_SHIFT_E 31
+#define BP_CFG_MASK_TID 0x7FFFFF00ull /* Depends on CPU */
+#define BP_CFG_SHIFT_TID 8
+#define BP_CFG_MASK_IRQ 0x0000000Full
+#define BP_CFG_SHIFT_IRQ 0
+#define BP_CFG_VALID (BP_CFG_MASK_E|BP_CFG_MASK_TID|BP_CFG_MASK_IRQ)
+#define BP_CFG_RESERVED ~BP_CFG_VALID
+
+#define BP_CFG_ENABLED(cfg) (((cfg) & BP_CFG_MASK_E) >> BP_CFG_SHIFT_E)
+#define BP_CFG_TID(cfg) (((cfg) & BP_CFG_MASK_TID) >> BP_CFG_SHIFT_TID)
+#define BP_CFG_IRQ(cfg) (((cfg) & BP_CFG_MASK_IRQ) >> BP_CFG_SHIFT_IRQ)
+
+MALLOC_DEFINE(M_BERIPIC, "beripic", "beripic memory");
+
+static uint64_t
+bp_read_cfg(struct beripic_softc *sc, int irq)
+{
+
+ KASSERT((irq >= 0 && irq < sc->bp_nsrcs),
+ ("IRQ of of range %d (0-%d)", irq, sc->bp_nsrcs - 1));
+ return (bus_space_read_8(sc->bp_cfg_bst, sc->bp_cfg_bsh, irq * 8));
+}
+
+static void
+bp_write_cfg(struct beripic_softc *sc, int irq, uint64_t config)
+{
+
+ KASSERT((irq >= 0 && irq < sc->bp_nsrcs),
+ ("IRQ of of range %d (0-%d)", irq, sc->bp_nsrcs - 1));
+ bus_space_write_8(sc->bp_cfg_bst, sc->bp_cfg_bsh, irq * 8, config);
+}
+
+static void
+bp_detach_resources(device_t dev)
+{
+ struct beripic_softc *sc;
+ int i;
+
+ sc = device_get_softc(dev);
+
+ if (sc->bp_cfg_res != NULL) {
+ bus_release_resource(dev, SYS_RES_MEMORY, sc->bp_cfg_rid,
+ sc->bp_cfg_res);
+ sc->bp_cfg_res = NULL;
+ }
+ if (sc->bp_read_res != NULL) {
+ bus_release_resource(dev, SYS_RES_MEMORY, sc->bp_read_rid,
+ sc->bp_read_res);
+ sc->bp_read_res = NULL;
+ }
+ if (sc->bp_set_res != NULL) {
+ bus_release_resource(dev, SYS_RES_MEMORY, sc->bp_set_rid,
+ sc->bp_set_res);
+ sc->bp_set_res = NULL;
+ }
+ if (sc->bp_clear_res != NULL) {
+ bus_release_resource(dev, SYS_RES_MEMORY, sc->bp_clear_rid,
+ sc->bp_clear_res);
+ sc->bp_clear_res = NULL;
+ }
+ for (i = sc->bp_nirqs - 1; i >= 0; i--) {
+ bus_release_resource(dev, SYS_RES_IRQ, sc->bp_irq_rids[i],
+ sc->bp_irqs[i]);
+ }
+ sc->bp_nirqs = 0;
+}
+
+static char *
+bp_strconfig(uint64_t config, char *configstr, size_t len)
+{
+
+ if (snprintf(configstr, len, "%s tid: %llu hardintr %llu",
+ BP_CFG_ENABLED(config) ? "enabled" : "disabled",
+ BP_CFG_TID(config), BP_CFG_IRQ(config)) > len - 1)
+ return (NULL);
+ return (configstr);
+}
+
+static void
+bp_config_source(device_t ic, int src, int enable, u_long tid, u_long irq)
+{
+ struct beripic_softc *sc;
+ uint64_t config;
+
+ sc = device_get_softc(ic);
+
+ config = 0;
+ config |= enable << BP_CFG_SHIFT_E;
+ config |= tid << BP_CFG_SHIFT_TID;
+ config |= irq << BP_CFG_SHIFT_IRQ;
+
+ bp_write_cfg(sc, src, config);
+}
+
+#ifdef __mips__
+static void
+bp_set_counter_name(device_t ic, device_t child, int src)
+{
+ struct beripic_softc *sc;
+ char name[MAXCOMLEN + 1];
+
+ sc = device_get_softc(ic);
+
+ if (snprintf(name, sizeof(name), "bp%dsrc%d%s%s%s",
+ device_get_unit(ic), src, src < sc->bp_nhard ? "" : "s",
+ child == NULL ? "" : " ",
+ child == NULL ? " " : device_get_nameunit(child)) >= sizeof(name))
+ name[sizeof(name) - 2] = '+';
+
+ mips_intrcnt_setname(sc->bp_counters[src], name);
+}
+#endif
+
+static int
+beripic_fdt_probe(device_t dev)
+{
+
+ if (!ofw_bus_status_okay(dev))
+ return (ENXIO);
+
+ if (!ofw_bus_is_compatible(dev, "sri-cambridge,beri-pic"))
+ return (ENXIO);
+
+ device_set_desc(dev, "BERI Programmable Interrupt Controller");
+ return (BUS_PROBE_DEFAULT);
+}
+
+static int
+beripic_fdt_attach(device_t dev)
+{
+ char configstr[64];
+ struct beripic_softc *sc;
+ struct fdt_ic *fic;
+ pcell_t nhard, nsoft;
+ phandle_t ph;
+ int error, i, src;
+ uint64_t config;
+
+ sc = device_get_softc(dev);
+ sc->bp_dev = dev;
+
+ mtx_init(&sc->bp_cfgmtx, "beripic config lock", NULL, MTX_DEF);
+
+ /*
+ * FDT lists CONFIG, IP_READ, IP_SET, and IP_CLEAR registers as
+ * seperate memory regions in that order.
+ */
+ sc->bp_cfg_rid = 0;
+ sc->bp_cfg_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY,
+ &sc->bp_cfg_rid, RF_ACTIVE);
+ if (sc->bp_cfg_res == NULL) {
+ device_printf(dev, "failed to map config memory");
+ error = ENXIO;
+ goto err;
+ }
+ if (bootverbose)
+ device_printf(sc->bp_dev, "config region at mem %p-%p\n",
+ (void *)rman_get_start(sc->bp_cfg_res),
+ (void *)(rman_get_start(sc->bp_cfg_res) +
+ rman_get_size(sc->bp_cfg_res)));
+
+ sc->bp_read_rid = 1;
+ sc->bp_read_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY,
+ &sc->bp_read_rid, RF_ACTIVE);
+ if (sc->bp_read_res == NULL) {
+ device_printf(dev, "failed to map IP read memory");
+ error = ENXIO;
+ goto err;
+ }
+ if (bootverbose)
+ device_printf(sc->bp_dev, "IP read region at mem %p-%p\n",
+ (void *)rman_get_start(sc->bp_read_res),
+ (void *)(rman_get_start(sc->bp_read_res) +
+ rman_get_size(sc->bp_read_res)));
+
+ sc->bp_set_rid = 2;
+ sc->bp_set_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY,
+ &sc->bp_set_rid, RF_ACTIVE);
+ if (sc->bp_set_res == NULL) {
+ device_printf(dev, "failed to map IP read memory");
+ error = ENXIO;
+ goto err;
+ }
+ if (bootverbose)
+ device_printf(sc->bp_dev, "IP set region at mem %p-%p\n",
+ (void *)rman_get_start(sc->bp_set_res),
+ (void *)(rman_get_start(sc->bp_set_res) +
+ rman_get_size(sc->bp_set_res)));
+
+ sc->bp_clear_rid = 3;
+ sc->bp_clear_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY,
+ &sc->bp_clear_rid, RF_ACTIVE);
+ if (sc->bp_clear_res == NULL) {
+ device_printf(dev, "failed to map IP read memory");
+ error = ENXIO;
+ goto err;
+ }
+ if (bootverbose)
+ device_printf(sc->bp_dev, "IP clear region at mem %p-%p\n",
+ (void *)rman_get_start(sc->bp_clear_res),
+ (void *)(rman_get_start(sc->bp_clear_res) +
+ rman_get_size(sc->bp_clear_res)));
+
+ i = 0;
+ for (i = 0; i < BP_MAX_HARD_IRQS; i++) {
+ sc->bp_irq_rids[i] = i;
+ sc->bp_irqs[i] = bus_alloc_resource_any(dev, SYS_RES_IRQ,
+ &sc->bp_irq_rids[i], RF_ACTIVE | RF_SHAREABLE);
+ if (sc->bp_irqs[i] == NULL)
+ break;
+ }
+ if (i == 0) {
+ device_printf(dev, "failed to allocate any parent IRQs!");
+ error = ENXIO;
+ goto err;
+ }
+ sc->bp_nirqs = i;
+
+ ph = ofw_bus_gen_get_node(device_get_parent(dev), dev);
+
+#ifndef SMP
+ sc->bp_nthreads = 1;
+#else
+ sc->bp_nthreads = 1;
+ /* XXX: get nthreads from cpu(s) somehow */
+#endif
+
+ if (OF_getprop(ph, "hard-interrupt-sources", &nhard, sizeof(nhard))
+ <= 0) {
+ device_printf(dev, "failed to get number of hard sources");
+ error = ENXIO;
+ goto err;
+ }
+ if (OF_getprop(ph, "soft-interrupt-sources", &nsoft, sizeof(nsoft))
+ <= 0) {
+ device_printf(dev, "failed to get number of soft sources");
+ error = ENXIO;
+ goto err;
+ }
+
+ sc->bp_nhard = nhard;
+ sc->bp_nsoft = nsoft;
+ sc->bp_nsrcs = sc->bp_nhard + sc->bp_nsoft;
+ /* XXX: should deal with gap between hard and soft */
+ KASSERT(sc->bp_nhard <= BP_FIRST_SOFT,
+ ("too many hard sources"));
+ KASSERT(rman_get_size(sc->bp_cfg_res) / 8 == sc->bp_nsrcs,
+ ("config space size does not match sources"));
+ KASSERT(sc->bp_nhard % 64 == 0,
+ ("Non-multiple of 64 intr counts not supported"));
+ KASSERT(sc->bp_nsoft % 64 == 0,
+ ("Non-multiple of 64 intr counts not supported"));
+ if (bootverbose)
+ device_printf(dev, "%d hard and %d soft sources\n",
+ sc->bp_nhard, sc->bp_nsoft);
+
+#ifdef __mips__
+ sc->bp_counters = malloc(sizeof(*sc->bp_counters) * sc->bp_nsrcs,
+ M_BERIPIC, M_WAITOK|M_ZERO);
+ for (i = 0; i < sc->bp_nsrcs; i++) {
+ sc->bp_counters[i] = mips_intrcnt_create("");
+ bp_set_counter_name(dev, NULL, i);
+ }
+#endif
+
+ sc->bp_src_rman.rm_start = 0;
+ sc->bp_src_rman.rm_end = sc->bp_nsrcs - 1;
+ sc->bp_src_rman.rm_type = RMAN_ARRAY;
+ sc->bp_src_rman.rm_descr = "Interrupt source";
+ if (rman_init(&(sc->bp_src_rman)) != 0 ||
+ rman_manage_region(&(sc->bp_src_rman), 0, sc->bp_nsrcs - 1) != 0) {
+ device_printf(dev, "Failed to set up sources rman");
+ error = ENXIO;
+ goto err;
+ }
+
+ sc->bp_cfg_bst = rman_get_bustag(sc->bp_cfg_res);
+ sc->bp_cfg_bsh = rman_get_bushandle(sc->bp_cfg_res);
+ sc->bp_read_bst = rman_get_bustag(sc->bp_read_res);
+ sc->bp_read_bsh = rman_get_bushandle(sc->bp_read_res);
+ sc->bp_set_bst = rman_get_bustag(sc->bp_set_res);
+ sc->bp_set_bsh = rman_get_bushandle(sc->bp_set_res);
+ sc->bp_clear_bst = rman_get_bustag(sc->bp_clear_res);
+ sc->bp_clear_bsh = rman_get_bushandle(sc->bp_clear_res);
+
+ for (src = 0; src < sc->bp_nsrcs; src++) {
+ config = bp_read_cfg(sc, src);
+ if (config == 0)
+ continue;
+
+ if (bootverbose) {
+ device_printf(dev, "initial config: src %d: %s\n", src,
+ bp_strconfig(config, configstr, sizeof(configstr)));
+ if (config & BP_CFG_RESERVED)
+ device_printf(dev,
+ "reserved bits not 0: 0x%016jx\n",
+ (uintmax_t) config);
+ }
+
+ bp_config_source(dev, src, 0, 0, 0);
+ }
+
+ fic = malloc(sizeof(*fic), M_BERIPIC, M_WAITOK|M_ZERO);
+ fic->iph = ph;
+ fic->dev = dev;
+ SLIST_INSERT_HEAD(&fdt_ic_list_head, fic, fdt_ics);
+
+ return (0);
+err:
+ bp_detach_resources(dev);
+
+ return (error);
+}
+
+static struct resource *
+beripic_alloc_intr(device_t ic, device_t child, int *rid, u_long irq,
+ u_int flags)
+{
+ struct beripic_softc *sc;
+ struct resource *rv;
+
+ sc = device_get_softc(ic);
+
+ rv = rman_reserve_resource(&(sc->bp_src_rman), irq, irq, 1, flags,
+ child);
+ if (rv == NULL)
+ printf("%s: could not reserve source interrupt for %s\n",
+ __func__, device_get_nameunit(child));
+ rman_set_rid(rv, *rid);
+
+ if ((flags & RF_ACTIVE) &&
+ beripic_activate_intr(ic, rv) != 0) {
+ printf("%s: could not activate interrupt\n", __func__);
+ rman_release_resource(rv);
+ return (NULL);
+ }
+
+ return (rv);
+}
+
+static int
+beripic_release_intr(device_t ic, struct resource *r)
+{
+
+ return (rman_release_resource(r));
+}
+
+static int
+beripic_activate_intr(device_t ic, struct resource *r)
+{
+
+ return (rman_activate_resource(r));
+}
+
+static int
+beripic_deactivate_intr(device_t ic, struct resource *r)
+{
+
+ return (rman_deactivate_resource(r));
+}
+
+static int
+beripic_config_intr(device_t dev, int irq, enum intr_trigger trig,
+ enum intr_polarity pol)
+{
+
+ if (trig != INTR_TRIGGER_CONFORM || pol != INTR_POLARITY_CONFORM)
+ return (EINVAL);
+
+ return (0);
+}
+
+static int
+beripic_setup_intr(device_t ic, device_t child, struct resource *irq,
+ int flags, driver_filter_t *filter, driver_intr_t *intr, void *arg,
+ void **cookiep)
+{
+ struct beripic_softc *sc;
+ struct beripic_intr_arg *bpia;
+ struct beripic_cookie *bpc;
+ int error;
+ u_long hirq, src, tid;
+
+ sc = device_get_softc(ic);
+
+ src = rman_get_start(irq);
+
+ KASSERT(src < sc->bp_nsrcs, ("source (%lu) out of range 0-%d",
+ src, sc->bp_nsrcs - 1));
+
+ bpia = malloc(sizeof(*bpia), M_BERIPIC, M_WAITOK|M_ZERO);
+ bpia->filter = filter;
+ bpia->intr = intr;
+ bpia->arg = arg;
+ bpia->irq = irq;
+#ifdef __mips__
+ bpia->counter = sc->bp_counters[src];
+ bp_set_counter_name(ic, child, src);
+#endif
+
+ bpc = malloc(sizeof(*bpc), M_BERIPIC, M_WAITOK|M_ZERO);
+ bpc->bpia = bpia;
+
+ mtx_lock(&(sc->bp_cfgmtx));
+ bpc->hirq = sc->bp_irqs[sc->bp_next_irq];
+ hirq = rman_get_start(bpc->hirq);
+ tid = sc->bp_next_tid;
+
+ error = BUS_SETUP_INTR(device_get_parent(ic), ic, bpc->hirq, flags,
+ beripic_filter, intr == NULL ? NULL : beripic_intr, bpia,
+ &(bpc->cookie));
+ if (error != 0)
+ goto err;
+
+#ifdef NOTYET
+#ifdef SMP
+ /* XXX: bind ithread to cpu */
+ sc->bp_next_tid++;
+ if (sc->bp_next_tid >= sc->bp_nthreads)
+ sc->bp_next_tid = 0;
+#endif
+#endif
+ if (sc->bp_next_tid == 0) {
+ sc->bp_next_irq++;
+ if (sc->bp_next_irq >= sc->bp_nirqs)
+ sc->bp_next_irq = 0;
+ }
+ mtx_unlock(&(sc->bp_cfgmtx));
+
+ *cookiep = bpc;
+
+ bp_config_source(ic, rman_get_start(irq), 1, tid, hirq);
+
+ return (0);
+err:
+ free(bpc, M_BERIPIC);
+ free(bpia, M_BERIPIC);
+
+ return (error);
+}
+
+static int
+beripic_teardown_intr(device_t dev, device_t child, struct resource *irq,
+ void *cookie)
+{
+ struct beripic_cookie *bpc;
+ int error;
+
+ bpc = cookie;
+
+ bp_config_source(dev, rman_get_start(irq), 0, 0, 0);
+
+ free(bpc->bpia, M_BERIPIC);
+
+ error = BUS_TEARDOWN_INTR(device_get_parent(dev), dev, bpc->hirq,
+ bpc->cookie);
+
+ free(bpc, M_BERIPIC);
+
+ return (error);
+}
+
+static int
+beripic_filter(void *arg)
+{
+ struct beripic_intr_arg *bpic;
+
+ bpic = arg;
+
+#ifdef __mips__
+ mips_intrcnt_inc(bpic->counter);
+#endif
+
+ /* XXX: Add a check that our source is high */
+
+ if (bpic->filter == NULL)
+ return (FILTER_SCHEDULE_THREAD);
+
+ return (bpic->filter(bpic->arg));
+}
+
+static void
+beripic_intr(void *arg)
+{
+ struct beripic_intr_arg *bpic;
+
+ bpic = arg;
+
+ KASSERT(bpic->intr != NULL,
+ ("%s installed, but no child intr", __func__));
+
+ bpic->intr(bpic->arg);
+}
+
+#ifdef SMP
+static void
+beripic_setup_ipi(device_t ic, u_int tid, u_int ipi_irq)
+{
+
+ bp_config_source(ic, BP_FIRST_SOFT + tid, 1, tid, ipi_irq);
+}
+
+static void
+beripic_send_ipi(device_t ic, u_int tid)
+{
+ struct beripic_softc *sc;
+ uint64_t bit;
+
+ sc = device_get_softc(ic);
+
+ KASSERT(tid < sc->bp_nsoft, ("tid (%d) too large\n", tid));
+
+ bit = 1ULL << (tid % 64);
+ bus_space_write_8(sc->bp_set_bst, sc->bp_set_bsh,
+ (BP_FIRST_SOFT / 8) + (tid / 64), bit);
+}
+
+static void
+beripic_clear_ipi(device_t ic, u_int tid)
+{
+ struct beripic_softc *sc;
+ uint64_t bit;
+
+ sc = device_get_softc(ic);
+
+ KASSERT(tid < sc->bp_nsoft, ("tid (%d) to large\n", tid));
+
+ bit = 1ULL << (tid % 64);
+ bus_space_write_8(sc->bp_clear_bst, sc->bp_clear_bsh,
+ (BP_FIRST_SOFT / 8) + (tid / 64), bit);
+}
+#endif
+
+devclass_t beripic_devclass;
+
+static device_method_t beripic_fdt_methods[] = {
+ /* Device interface */
+ DEVMETHOD(device_probe, beripic_fdt_probe),
+ DEVMETHOD(device_attach, beripic_fdt_attach),
+
+ DEVMETHOD(fdt_ic_activate_intr, beripic_activate_intr),
+ DEVMETHOD(fdt_ic_alloc_intr, beripic_alloc_intr),
+ DEVMETHOD(fdt_ic_config_intr, beripic_config_intr),
+ DEVMETHOD(fdt_ic_deactivate_intr, beripic_deactivate_intr),
+ DEVMETHOD(fdt_ic_release_intr, beripic_release_intr),
+ DEVMETHOD(fdt_ic_setup_intr, beripic_setup_intr),
+ DEVMETHOD(fdt_ic_teardown_intr, beripic_teardown_intr),
+
+#ifdef SMP
+ DEVMETHOD(fdt_ic_setup_ipi, beripic_setup_ipi),
+ DEVMETHOD(fdt_ic_clear_ipi, beripic_clear_ipi),
+ DEVMETHOD(fdt_ic_send_ipi, beripic_send_ipi),
+#endif
+
+ { 0, 0 },
+};
+
+static driver_t beripic_fdt_driver = {
+ "beripic",
+ beripic_fdt_methods,
+ sizeof(struct beripic_softc)
+};
+
+DRIVER_MODULE(beripic, simplebus, beripic_fdt_driver, beripic_devclass, 0, 0);
Property changes on: trunk/sys/mips/beri/beri_pic.c
___________________________________________________________________
Added: svn:eol-style
## -0,0 +1 ##
+native
\ No newline at end of property
Added: svn:keywords
## -0,0 +1 ##
+MidnightBSD=%H
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+text/plain
\ No newline at end of property
Added: trunk/sys/mips/beri/beri_simplebus.c
===================================================================
--- trunk/sys/mips/beri/beri_simplebus.c (rev 0)
+++ trunk/sys/mips/beri/beri_simplebus.c 2018-05-26 21:55:02 UTC (rev 9987)
@@ -0,0 +1,429 @@
+/* $MidnightBSD$ */
+/*-
+ * Copyright (c) 2009-2010 The FreeBSD Foundation
+ * All rights reserved.
+ *
+ * This software was developed by Semihalf under sponsorship from
+ * the FreeBSD Foundation.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ */
+
+#include <sys/cdefs.h>
+__FBSDID("$FreeBSD: stable/10/sys/mips/beri/beri_simplebus.c 273675 2014-10-26 04:01:57Z ian $");
+
+#include "opt_platform.h"
+#include <sys/param.h>
+#include <sys/systm.h>
+#include <sys/ktr.h>
+#include <sys/kernel.h>
+#include <sys/module.h>
+#include <sys/bus.h>
+#include <sys/rman.h>
+#include <sys/malloc.h>
+
+#include <dev/ofw/ofw_bus.h>
+#include <dev/ofw/ofw_bus_subr.h>
+#include <dev/ofw/openfirm.h>
+
+#include <dev/fdt/fdt_common.h>
+#include "fdt_ic_if.h"
+#include "ofw_bus_if.h"
+
+#ifdef DEBUG
+#define debugf(fmt, args...) do { printf("%s(): ", __func__); \
+ printf(fmt,##args); } while (0)
+#else
+#define debugf(fmt, args...)
+#endif
+
+static MALLOC_DEFINE(M_SIMPLEBUS, "simplebus", "simplebus devices information");
+
+struct simplebus_softc {
+ int sc_addr_cells;
+ int sc_size_cells;
+};
+
+struct simplebus_devinfo {
+ struct ofw_bus_devinfo di_ofw;
+ struct resource_list di_res;
+
+ /* Interrupts sense-level info for this device */
+ struct fdt_sense_level di_intr_sl[DI_MAX_INTR_NUM];
+};
+
+/*
+ * Prototypes.
+ */
+static int simplebus_probe(device_t);
+static int simplebus_attach(device_t);
+
+static int simplebus_print_child(device_t, device_t);
+static int simplebus_setup_intr(device_t, device_t, struct resource *, int,
+ driver_filter_t *, driver_intr_t *, void *, void **);
+static int simplebus_teardown_intr(device_t, device_t, struct resource *,
+ void *);
+
+static int simplebus_activate_resource(device_t, device_t, int, int,
+ struct resource *);
+static struct resource *simplebus_alloc_resource(device_t, device_t, int,
+ int *, u_long, u_long, u_long, u_int);
+static int simplebus_deactivate_resource(device_t, device_t, int, int,
+ struct resource *);
+static int simplebus_release_resource(device_t, device_t, int, int,
+ struct resource *);
+static device_t simplebus_get_interrupt_parent(device_t);
+static struct resource_list *simplebus_get_resource_list(device_t, device_t);
+
+static ofw_bus_get_devinfo_t simplebus_get_devinfo;
+
+/*
+ * Bus interface definition.
+ */
+static device_method_t simplebus_methods[] = {
+ /* Device interface */
+ DEVMETHOD(device_probe, simplebus_probe),
+ DEVMETHOD(device_attach, simplebus_attach),
+ DEVMETHOD(device_detach, bus_generic_detach),
+ DEVMETHOD(device_shutdown, bus_generic_shutdown),
+ DEVMETHOD(device_suspend, bus_generic_suspend),
+ DEVMETHOD(device_resume, bus_generic_resume),
+
+ /* Bus interface */
+ DEVMETHOD(bus_print_child, simplebus_print_child),
+ DEVMETHOD(bus_alloc_resource, simplebus_alloc_resource),
+ DEVMETHOD(bus_release_resource, simplebus_release_resource),
+ DEVMETHOD(bus_activate_resource, simplebus_activate_resource),
+ DEVMETHOD(bus_deactivate_resource, simplebus_deactivate_resource),
+ DEVMETHOD(bus_setup_intr, simplebus_setup_intr),
+ DEVMETHOD(bus_teardown_intr, simplebus_teardown_intr),
+ DEVMETHOD(bus_get_resource_list, simplebus_get_resource_list),
+
+ /* OFW bus interface */
+ DEVMETHOD(ofw_bus_get_devinfo, simplebus_get_devinfo),
+ DEVMETHOD(ofw_bus_get_compat, ofw_bus_gen_get_compat),
+ DEVMETHOD(ofw_bus_get_model, ofw_bus_gen_get_model),
+ DEVMETHOD(ofw_bus_get_name, ofw_bus_gen_get_name),
+ DEVMETHOD(ofw_bus_get_node, ofw_bus_gen_get_node),
+ DEVMETHOD(ofw_bus_get_type, ofw_bus_gen_get_type),
+
+ { 0, 0 }
+};
+
+static driver_t simplebus_driver = {
+ "simplebus",
+ simplebus_methods,
+ sizeof(struct simplebus_softc)
+};
+
+devclass_t simplebus_devclass;
+
+DRIVER_MODULE(simplebus, ofwbus, simplebus_driver, simplebus_devclass, 0, 0);
+DRIVER_MODULE(simplebus, simplebus, simplebus_driver, simplebus_devclass, 0,
+ 0);
+
+static int
+simplebus_probe(device_t dev)
+{
+
+ if (!ofw_bus_status_okay(dev))
+ return (ENXIO);
+
+ if (!ofw_bus_is_compatible(dev, "simple-bus"))
+ return (ENXIO);
+
+ device_set_desc(dev, "Flattened device tree simple bus");
+
+ return (BUS_PROBE_SPECIFIC);
+}
+
+static int
+simplebus_attach(device_t dev)
+{
+ device_t dev_child;
+ struct simplebus_devinfo *di;
+ struct simplebus_softc *sc;
+ phandle_t dt_node, dt_child;
+
+ sc = device_get_softc(dev);
+
+ /*
+ * Walk simple-bus and add direct subordinates as our children.
+ */
+ dt_node = ofw_bus_get_node(dev);
+ for (dt_child = OF_child(dt_node); dt_child != 0;
+ dt_child = OF_peer(dt_child)) {
+
+ /* Check and process 'status' property. */
+ if (!(fdt_is_enabled(dt_child)))
+ continue;
+
+ if (!(fdt_pm_is_enabled(dt_child)))
+ continue;
+
+ di = malloc(sizeof(*di), M_SIMPLEBUS, M_WAITOK | M_ZERO);
+
+ if (ofw_bus_gen_setup_devinfo(&di->di_ofw, dt_child) != 0) {
+ free(di, M_SIMPLEBUS);
+ device_printf(dev, "could not set up devinfo\n");
+ continue;
+ }
+
+ resource_list_init(&di->di_res);
+ if (fdt_reg_to_rl(dt_child, &di->di_res)) {
+ device_printf(dev,
+ "%s: could not process 'reg' "
+ "property\n", di->di_ofw.obd_name);
+ ofw_bus_gen_destroy_devinfo(&di->di_ofw);
+ free(di, M_SIMPLEBUS);
+ continue;
+ }
+
+ if (ofw_bus_intr_to_rl(dev, dt_child, &di->di_res)) {
+ device_printf(dev, "%s: could not process "
+ "'interrupts' property\n", di->di_ofw.obd_name);
+ resource_list_free(&di->di_res);
+ ofw_bus_gen_destroy_devinfo(&di->di_ofw);
+ free(di, M_SIMPLEBUS);
+ continue;
+ }
+
+ /* Add newbus device for this FDT node */
+ dev_child = device_add_child(dev, NULL, -1);
+ if (dev_child == NULL) {
+ device_printf(dev, "could not add child: %s\n",
+ di->di_ofw.obd_name);
+ resource_list_free(&di->di_res);
+ ofw_bus_gen_destroy_devinfo(&di->di_ofw);
+ free(di, M_SIMPLEBUS);
+ continue;
+ }
+#ifdef DEBUG
+ device_printf(dev, "added child: %s\n\n", di->di_ofw.obd_name);
+#endif
+ device_set_ivars(dev_child, di);
+ }
+
+ return (bus_generic_attach(dev));
+}
+
+static int
+simplebus_print_child(device_t dev, device_t child)
+{
+ device_t ip;
+ struct simplebus_devinfo *di;
+ struct resource_list *rl;
+ int rv;
+
+ di = device_get_ivars(child);
+ rl = &di->di_res;
+
+ rv = 0;
+ rv += bus_print_child_header(dev, child);
+ rv += resource_list_print_type(rl, "mem", SYS_RES_MEMORY, "%#lx");
+ rv += resource_list_print_type(rl, "irq", SYS_RES_IRQ, "%ld");
+ if ((ip = simplebus_get_interrupt_parent(child)) != NULL)
+ rv += printf(" (%s)", device_get_nameunit(ip));
+ rv += bus_print_child_footer(dev, child);
+
+ return (rv);
+}
+
+static struct resource *
+simplebus_alloc_resource(device_t bus, device_t child, int type, int *rid,
+ u_long start, u_long end, u_long count, u_int flags)
+{
+ device_t ic;
+ struct simplebus_devinfo *di;
+ struct resource_list_entry *rle;
+
+ /*
+ * Request for the default allocation with a given rid: use resource
+ * list stored in the local device info.
+ */
+ if ((start == 0UL) && (end == ~0UL)) {
+ if ((di = device_get_ivars(child)) == NULL)
+ return (NULL);
+
+ if (type == SYS_RES_IOPORT)
+ type = SYS_RES_MEMORY;
+
+ rle = resource_list_find(&di->di_res, type, *rid);
+ if (rle == NULL) {
+ if (bootverbose)
+ device_printf(bus, "no default resources for "
+ "rid = %d, type = %d\n", *rid, type);
+ return (NULL);
+ }
+ start = rle->start;
+ end = rle->end;
+ count = rle->count;
+ }
+
+ if (type == SYS_RES_IRQ &&
+ (ic = simplebus_get_interrupt_parent(child)) != NULL)
+ return(FDT_IC_ALLOC_INTR(ic, child, rid, start, flags));
+
+ return (bus_generic_alloc_resource(bus, child, type, rid, start, end,
+ count, flags));
+}
+
+static int
+simplebus_activate_resource(device_t dev, device_t child, int type, int rid,
+ struct resource *r)
+{
+ device_t ic;
+
+ if (type == SYS_RES_IRQ &&
+ (ic = simplebus_get_interrupt_parent(child)) != NULL)
+ return (FDT_IC_ACTIVATE_INTR(ic, r));
+
+ return (bus_generic_activate_resource(dev, child, type, rid, r));
+}
+
+static int
+simplebus_deactivate_resource(device_t dev, device_t child, int type, int rid,
+ struct resource *r)
+{
+ device_t ic;
+
+ if (type == SYS_RES_IRQ &&
+ (ic = simplebus_get_interrupt_parent(child)) != NULL)
+ return (FDT_IC_DEACTIVATE_INTR(ic, r));
+
+ return (bus_generic_deactivate_resource(dev, child, type, rid, r));
+}
+
+static int
+simplebus_release_resource(device_t dev, device_t child, int type, int rid,
+ struct resource *r)
+{
+ device_t ic;
+
+ if (type == SYS_RES_IRQ &&
+ (ic = simplebus_get_interrupt_parent(child)) != NULL)
+ return (FDT_IC_RELEASE_INTR(ic, r));
+
+ return (bus_generic_release_resource(dev, child, type, rid, r));
+}
+
+static struct resource_list *
+simplebus_get_resource_list(device_t bus, device_t child)
+{
+ struct simplebus_devinfo *di;
+
+ di = device_get_ivars(child);
+ return (&di->di_res);
+}
+
+static device_t
+simplebus_get_interrupt_parent(device_t dev)
+{
+ struct simplebus_devinfo *di;
+ struct fdt_ic *ic;
+ device_t ip;
+ phandle_t ph, iph;
+
+ ip = NULL;
+
+ di = device_get_ivars(dev);
+ if (di == NULL)
+ return (NULL);
+
+ if (OF_getencprop(di->di_ofw.obd_node, "interrupt-parent", &iph,
+ sizeof(iph)) > 0) {
+ ph = OF_node_from_xref(iph);
+ SLIST_FOREACH(ic, &fdt_ic_list_head, fdt_ics) {
+ if (ic->iph == ph) {
+ ip = ic->dev;
+ break;
+ }
+ }
+ }
+ return (ip);
+}
+
+static int
+simplebus_setup_intr(device_t bus, device_t child, struct resource *res,
+ int flags, driver_filter_t *filter, driver_intr_t *ihand, void *arg,
+ void **cookiep)
+{
+ struct simplebus_devinfo *di;
+ device_t ic;
+ enum intr_trigger trig;
+ enum intr_polarity pol;
+ int error, irq, rid;
+
+ di = device_get_ivars(child);
+ if (di == NULL)
+ return (ENXIO);
+
+ if (res == NULL)
+ return (EINVAL);
+
+ rid = rman_get_rid(res);
+ if (rid >= DI_MAX_INTR_NUM)
+ return (ENOENT);
+
+ ic = simplebus_get_interrupt_parent(child);
+
+ trig = di->di_intr_sl[rid].trig;
+ pol = di->di_intr_sl[rid].pol;
+ if (trig != INTR_TRIGGER_CONFORM || pol != INTR_POLARITY_CONFORM) {
+ irq = rman_get_start(res);
+ if (ic != NULL)
+ error = FDT_IC_CONFIG_INTR(ic, irq, trig, pol);
+ else
+ error = bus_generic_config_intr(bus, irq, trig, pol);
+ if (error)
+ return (error);
+ }
+
+ if (ic != NULL)
+ error = FDT_IC_SETUP_INTR(ic, child, res, flags, filter,
+ ihand, arg, cookiep);
+ else
+ error = bus_generic_setup_intr(bus, child, res, flags, filter,
+ ihand, arg, cookiep);
+ return (error);
+}
+
+static int
+simplebus_teardown_intr(device_t bus, device_t child, struct resource *res,
+ void *cookie)
+{
+ device_t ic;
+
+ if ((ic = simplebus_get_interrupt_parent(child)) != NULL)
+ return (FDT_IC_TEARDOWN_INTR(ic, child, res, cookie));
+
+ return (bus_generic_teardown_intr(bus, child, res, cookie));
+}
+
+static const struct ofw_bus_devinfo *
+simplebus_get_devinfo(device_t bus, device_t child)
+{
+ struct simplebus_devinfo *di;
+
+ di = device_get_ivars(child);
+ return (&di->di_ofw);
+}
Property changes on: trunk/sys/mips/beri/beri_simplebus.c
___________________________________________________________________
Added: svn:eol-style
## -0,0 +1 ##
+native
\ No newline at end of property
Added: svn:keywords
## -0,0 +1 ##
+MidnightBSD=%H
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+text/plain
\ No newline at end of property
Added: trunk/sys/mips/beri/fdt_ic_if.m
===================================================================
--- trunk/sys/mips/beri/fdt_ic_if.m (rev 0)
+++ trunk/sys/mips/beri/fdt_ic_if.m 2018-05-26 21:55:02 UTC (rev 9987)
@@ -0,0 +1,266 @@
+#-
+# Copyright (c) 2013 SRI International
+# Copyright (c) 1998-2004 Doug Rabson
+# All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions
+# are met:
+# 1. Redistributions of source code must retain the above copyright
+# notice, this list of conditions and the following disclaimer.
+# 2. Redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in the
+# documentation and/or other materials provided with the distribution.
+#
+# THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+# ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+# IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+# ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+# FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+# DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+# OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+# HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+# LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+# OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+# SUCH DAMAGE.
+#
+# $FreeBSD: stable/10/sys/mips/beri/fdt_ic_if.m 266128 2014-05-15 14:26:11Z ian $
+#
+
+#include <sys/types.h>
+#include <sys/systm.h>
+#include <sys/bus.h>
+
+/**
+ * @defgroup FST_IC fdt_ic - KObj methods for interrupt controllers
+ * @brief A set of methods required device drivers that are interrupt
+ * controllers. Derived from sys/kern/bus_if.m.
+ * @{
+ */
+INTERFACE fdt_ic;
+
+/**
+ * @brief Allocate an interrupt resource
+ *
+ * This method is called by child devices of an interrupt controller to
+ * allocate an interrup. The meaning of the resource-ID field varies
+ * from bus to bus and is opaque to the interrupt controller. If a
+ * resource was allocated and the caller did not use the RF_ACTIVE
+ * to specify that it should be activated immediately, the caller is
+ * responsible for calling FDT_IC_ACTIVATE_INTR() when it actually uses
+ * the interupt.
+ *
+ * @param _dev the interrupt-parent device of @p _child
+ * @param _child the device which is requesting an allocation
+ * @param _rid a pointer to the resource identifier
+ * @param _irq interrupt source to allocate
+ * @param _flags any extra flags to control the resource
+ * allocation - see @c RF_XXX flags in
+ * <sys/rman.h> for details
+ *
+ * @returns the interrupt which was allocated or @c NULL if no
+ * resource could be allocated
+ */
+METHOD struct resource * alloc_intr {
+ device_t _dev;
+ device_t _child;
+ int *_rid;
+ u_long _irq;
+ u_int _flags;
+};
+
+/**
+ * @brief Activate an interrupt
+ *
+ * Activate an interrupt previously allocated with FDT_IC_ALLOC_INTR().
+ *
+ * @param _dev the parent device of @p _child
+ * @param _r interrupt to activate
+ */
+METHOD int activate_intr {
+ device_t _dev;
+ struct resource *_r;
+};
+
+/**
+ * @brief Deactivate an interrupt
+ *
+ * Deactivate a resource previously allocated with FDT_IC_ALLOC_INTR().
+ *
+ * @param _dev the parent device of @p _child
+ * @param _r the interrupt to deactivate
+ */
+METHOD int deactivate_intr {
+ device_t _dev;
+ struct resource *_r;
+};
+
+/**
+ * @brief Release an interrupt
+ *
+ * Free an interupt allocated by the FDT_IC_ALLOC_INTR.
+ *
+ * @param _dev the parent device of @p _child
+ * @param _r the resource to release
+ */
+METHOD int release_intr {
+ device_t _dev;
+ struct resource *_res;
+};
+
+/**
+ * @brief Install an interrupt handler
+ *
+ * This method is used to associate an interrupt handler function with
+ * an irq resource. When the interrupt triggers, the function @p _intr
+ * will be called with the value of @p _arg as its single
+ * argument. The value returned in @p *_cookiep is used to cancel the
+ * interrupt handler - the caller should save this value to use in a
+ * future call to FDT_IC_TEARDOWN_INTR().
+ *
+ * @param _dev the interrupt-parent device of @p _child
+ * @param _child the device which allocated the resource
+ * @param _irq the resource representing the interrupt
+ * @param _flags a set of bits from enum intr_type specifying
+ * the class of interrupt
+ * @param _intr the function to call when the interrupt
+ * triggers
+ * @param _arg a value to use as the single argument in calls
+ * to @p _intr
+ * @param _cookiep a pointer to a location to recieve a cookie
+ * value that may be used to remove the interrupt
+ * handler
+ */
+METHOD int setup_intr {
+ device_t _dev;
+ device_t _child;
+ struct resource *_irq;
+ int _flags;
+ driver_filter_t *_filter;
+ driver_intr_t *_intr;
+ void *_arg;
+ void **_cookiep;
+};
+
+/**
+ * @brief Uninstall an interrupt handler
+ *
+ * This method is used to disassociate an interrupt handler function
+ * with an irq resource. The value of @p _cookie must be the value
+ * returned from a previous call to FDT_IC_SETUP_INTR().
+ *
+ * @param _dev the interrupt-parent device of @p _child
+ * @param _child the device which allocated the resource
+ * @param _irq the resource representing the interrupt
+ * @param _cookie the cookie value returned when the interrupt
+ * was originally registered
+ */
+METHOD int teardown_intr {
+ device_t _dev;
+ device_t _child;
+ struct resource *_irq;
+ void *_cookie;
+};
+
+/**
+ * @brief Allow drivers to request that an interrupt be bound to a specific
+ * CPU.
+ *
+ * @param _dev the interrupt-parent device of @p _child
+ * @param _child the device which allocated the resource
+ * @param _irq the resource representing the interrupt
+ * @param _cpu the CPU to bind the interrupt to
+ */
+METHOD int bind_intr {
+ device_t _dev;
+ device_t _child;
+ struct resource *_irq;
+ int _cpu;
+};
+
+/**
+ * @brief Allow drivers to specify the trigger mode and polarity
+ * of the specified interrupt.
+ *
+ * @param _dev the interrupt-parent device
+ * @param _irq the interrupt number to modify
+ * @param _trig the trigger mode required
+ * @param _pol the interrupt polarity required
+ */
+METHOD int config_intr {
+ device_t _dev;
+ int _irq;
+ enum intr_trigger _trig;
+ enum intr_polarity _pol;
+};
+
+/**
+ * @brief Allow drivers to associate a description with an active
+ * interrupt handler.
+ *
+ * @param _dev the interrupt-parent device of @p _child
+ * @param _child the device which allocated the resource
+ * @param _irq the resource representing the interrupt
+ * @param _cookie the cookie value returned when the interrupt
+ * was originally registered
+ * @param _descr the description to associate with the interrupt
+ */
+METHOD int describe_intr {
+ device_t _dev;
+ device_t _child;
+ struct resource *_irq;
+ void *_cookie;
+ const char *_descr;
+};
+
+/**
+ * @brief Notify an ic that specified child's IRQ should be remapped.
+ *
+ * @param _dev the interrupt-parent device
+ * @param _child the child device
+ * @param _irq the irq number
+ */
+METHOD int remap_intr {
+ device_t _dev;
+ device_t _child;
+ u_int _irq;
+};
+
+/**
+ * @brief Enable an IPI source.
+ *
+ * @param _dev the interrupt controller
+ * @param _tid the thread ID (relative to the interrupt controller)
+ * to enable IPIs for
+ * @param _ipi_irq hardware IRQ to send IPIs to
+ */
+METHOD void setup_ipi {
+ device_t _dev;
+ u_int _tid;
+ u_int _irq;
+};
+
+/**
+ * @brief Send an IPI to the specified thread.
+ *
+ * @param _dev the interrupt controller
+ * @param _tid the thread ID (relative to the interrupt controller)
+ * to send IPIs to
+ */
+METHOD void send_ipi {
+ device_t _dev;
+ u_int _tid;
+};
+
+/**
+ * @brief Clear the IPI on the specfied thread. Only call with the
+ * local hardware thread or interrupts may be lost!
+ *
+ * @param _dev the interrupt controller
+ * @param _tid the thread ID (relative to the interrupt controller)
+ * to clear the IPI on
+ */
+METHOD void clear_ipi {
+ device_t _dev;
+ u_int _tid;
+};
Property changes on: trunk/sys/mips/beri/fdt_ic_if.m
___________________________________________________________________
Added: mnbsd:nokeywords
## -0,0 +1 ##
+MidnightBSD=%H
\ No newline at end of property
Added: trunk/sys/mips/beri/files.beri
===================================================================
--- trunk/sys/mips/beri/files.beri (rev 0)
+++ trunk/sys/mips/beri/files.beri 2018-05-26 21:55:02 UTC (rev 9987)
@@ -0,0 +1,26 @@
+# $FreeBSD: stable/10/sys/mips/beri/files.beri 270061 2014-08-16 14:30:46Z bz $
+dev/altera/atse/if_atse.c optional altera_atse
+dev/altera/atse/if_atse_fdt.c optional altera_atse fdt
+dev/altera/atse/if_atse_nexus.c optional altera_atse
+dev/altera/jtag_uart/altera_jtag_uart_cons.c optional altera_jtag_uart
+dev/altera/jtag_uart/altera_jtag_uart_tty.c optional altera_jtag_uart
+dev/altera/jtag_uart/altera_jtag_uart_fdt.c optional altera_jtag_uart fdt
+dev/altera/jtag_uart/altera_jtag_uart_nexus.c optional altera_jtag_uart
+dev/netfpga10g/nf10bmac/if_nf10bmac_fdt.c optional netfpga10g_nf10bmac fdt
+dev/netfpga10g/nf10bmac/if_nf10bmac.c optional netfpga10g_nf10bmac
+dev/terasic/de4led/terasic_de4led.c optional terasic_de4led
+dev/terasic/de4led/terasic_de4led_fdt.c optional terasic_de4led fdt
+dev/terasic/de4led/terasic_de4led_nexus.c optional terasic_de4led
+dev/terasic/mtl/terasic_mtl.c optional terasic_mtl
+dev/terasic/mtl/terasic_mtl_fdt.c optional terasic_mtl fdt
+dev/terasic/mtl/terasic_mtl_nexus.c optional terasic_mtl
+dev/terasic/mtl/terasic_mtl_pixel.c optional terasic_mtl
+dev/terasic/mtl/terasic_mtl_reg.c optional terasic_mtl
+dev/terasic/mtl/terasic_mtl_syscons.c optional terasic_mtl
+dev/terasic/mtl/terasic_mtl_text.c optional terasic_mtl
+mips/beri/beri_machdep.c standard
+mips/beri/beri_pic.c optional fdt
+mips/beri/beri_simplebus.c optional fdt
+mips/beri/fdt_ic_if.m optional fdt
+mips/mips/intr_machdep.c standard
+mips/mips/tick.c standard
Property changes on: trunk/sys/mips/beri/files.beri
___________________________________________________________________
Added: mnbsd:nokeywords
## -0,0 +1 ##
+MidnightBSD=%H
\ No newline at end of property
Added: trunk/sys/mips/beri/std.beri
===================================================================
--- trunk/sys/mips/beri/std.beri (rev 0)
+++ trunk/sys/mips/beri/std.beri 2018-05-26 21:55:02 UTC (rev 9987)
@@ -0,0 +1,6 @@
+# $FreeBSD: stable/10/sys/mips/beri/std.beri 257528 2013-11-01 21:17:45Z brooks $
+files "../beri/files.beri"
+
+cpu CPU_MIPS4KC
+
+options BERI_LARGE_TLB
Property changes on: trunk/sys/mips/beri/std.beri
___________________________________________________________________
Added: mnbsd:nokeywords
## -0,0 +1 ##
+MidnightBSD=%H
\ No newline at end of property
Added: trunk/sys/mips/cavium/asm_octeon.S
===================================================================
--- trunk/sys/mips/cavium/asm_octeon.S (rev 0)
+++ trunk/sys/mips/cavium/asm_octeon.S 2018-05-26 21:55:02 UTC (rev 9987)
@@ -0,0 +1,67 @@
+/* $MidnightBSD$ */
+/*-
+ * Copyright (c) 2004-2010 Juli Mallett <jmallett at FreeBSD.org>
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ * $FreeBSD: stable/10/sys/mips/cavium/asm_octeon.S 226018 2011-10-04 17:49:19Z marcel $
+ */
+
+#include <machine/asm.h>
+
+ .set noreorder
+
+#ifdef SMP
+/*
+ * This function must be implemented in assembly because it is called early
+ * in AP boot without a valid stack.
+ */
+LEAF(platform_processor_id)
+ .set push
+ .set mips32r2
+ jr ra
+ rdhwr v0, $0
+ .set pop
+END(platform_processor_id)
+
+/*
+ * Called on APs to wait until they are told to launch.
+ */
+LEAF(octeon_ap_wait)
+ jal platform_processor_id
+ nop
+
+1: ll t0, octeon_ap_boot
+ bne v0, t0, 1b
+ nop
+
+ move t0, zero
+ sc t0, octeon_ap_boot
+
+ beqz t0, 1b
+ nop
+
+ j mpentry
+ nop
+END(octeon_ap_wait)
+#endif
Property changes on: trunk/sys/mips/cavium/asm_octeon.S
___________________________________________________________________
Added: svn:eol-style
## -0,0 +1 ##
+native
\ No newline at end of property
Added: svn:keywords
## -0,0 +1 ##
+MidnightBSD=%H
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+text/plain
\ No newline at end of property
Added: trunk/sys/mips/cavium/ciu.c
===================================================================
--- trunk/sys/mips/cavium/ciu.c (rev 0)
+++ trunk/sys/mips/cavium/ciu.c 2018-05-26 21:55:02 UTC (rev 9987)
@@ -0,0 +1,489 @@
+/* $MidnightBSD$ */
+/*-
+ * Copyright (c) 2010 Juli Mallett <jmallett at FreeBSD.org>
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ * $FreeBSD: stable/10/sys/mips/cavium/ciu.c 265999 2014-05-14 01:35:43Z ian $
+ */
+
+#include <sys/cdefs.h>
+__FBSDID("$FreeBSD: stable/10/sys/mips/cavium/ciu.c 265999 2014-05-14 01:35:43Z ian $");
+
+#include <sys/param.h>
+#include <sys/systm.h>
+#include <sys/bus.h>
+#include <sys/interrupt.h>
+#include <sys/kernel.h>
+#include <sys/module.h>
+#include <sys/rman.h>
+#include <sys/malloc.h>
+#include <sys/smp.h>
+
+#include <machine/bus.h>
+#include <machine/intr_machdep.h>
+
+#include <contrib/octeon-sdk/cvmx.h>
+#include <mips/cavium/octeon_irq.h>
+
+/*
+ * This bus sits between devices/buses and nexus and handles CIU interrupts
+ * and passes everything else through. It should really be a nexus subclass
+ * or something, but for now this will be sufficient.
+ */
+
+#define CIU_IRQ_HARD (0)
+
+#define CIU_IRQ_EN0_BEGIN OCTEON_IRQ_WORKQ0
+#define CIU_IRQ_EN0_END OCTEON_IRQ_BOOTDMA
+#define CIU_IRQ_EN0_COUNT ((CIU_IRQ_EN0_END - CIU_IRQ_EN0_BEGIN) + 1)
+
+#define CIU_IRQ_EN1_BEGIN OCTEON_IRQ_WDOG0
+#define CIU_IRQ_EN1_END OCTEON_IRQ_DFM
+#define CIU_IRQ_EN1_COUNT ((CIU_IRQ_EN1_END - CIU_IRQ_EN1_BEGIN) + 1)
+
+struct ciu_softc {
+ struct rman irq_rman;
+ struct resource *ciu_irq;
+};
+
+static mips_intrcnt_t ciu_en0_intrcnt[CIU_IRQ_EN0_COUNT];
+static mips_intrcnt_t ciu_en1_intrcnt[CIU_IRQ_EN1_COUNT];
+
+static struct intr_event *ciu_en0_intr_events[CIU_IRQ_EN0_COUNT];
+static struct intr_event *ciu_en1_intr_events[CIU_IRQ_EN1_COUNT];
+
+static int ciu_probe(device_t);
+static int ciu_attach(device_t);
+static struct resource *ciu_alloc_resource(device_t, device_t, int, int *,
+ u_long, u_long, u_long, u_int);
+static int ciu_setup_intr(device_t, device_t, struct resource *,
+ int, driver_filter_t *, driver_intr_t *,
+ void *, void **);
+static int ciu_teardown_intr(device_t, device_t,
+ struct resource *, void *);
+static int ciu_bind_intr(device_t, device_t, struct resource *,
+ int);
+static int ciu_describe_intr(device_t, device_t,
+ struct resource *, void *,
+ const char *);
+static void ciu_hinted_child(device_t, const char *, int);
+
+static void ciu_en0_intr_mask(void *);
+static void ciu_en0_intr_unmask(void *);
+#ifdef SMP
+static int ciu_en0_intr_bind(void *, u_char);
+#endif
+
+static void ciu_en1_intr_mask(void *);
+static void ciu_en1_intr_unmask(void *);
+#ifdef SMP
+static int ciu_en1_intr_bind(void *, u_char);
+#endif
+
+static int ciu_intr(void *);
+
+static int
+ciu_probe(device_t dev)
+{
+ if (device_get_unit(dev) != 0)
+ return (ENXIO);
+
+ device_set_desc(dev, "Cavium Octeon Central Interrupt Unit");
+ return (BUS_PROBE_NOWILDCARD);
+}
+
+static int
+ciu_attach(device_t dev)
+{
+ char name[MAXCOMLEN + 1];
+ struct ciu_softc *sc;
+ unsigned i;
+ int error;
+ int rid;
+
+ sc = device_get_softc(dev);
+
+ rid = 0;
+ sc->ciu_irq = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, CIU_IRQ_HARD,
+ CIU_IRQ_HARD, 1, RF_ACTIVE);
+ if (sc->ciu_irq == NULL) {
+ device_printf(dev, "could not allocate irq%d\n", CIU_IRQ_HARD);
+ return (ENXIO);
+ }
+
+ error = bus_setup_intr(dev, sc->ciu_irq, INTR_TYPE_MISC, ciu_intr,
+ NULL, sc, NULL);
+ if (error != 0) {
+ device_printf(dev, "bus_setup_intr failed: %d\n", error);
+ return (error);
+ }
+
+ sc->irq_rman.rm_type = RMAN_ARRAY;
+ sc->irq_rman.rm_descr = "CIU IRQ";
+
+ error = rman_init(&sc->irq_rman);
+ if (error != 0)
+ return (error);
+
+ /*
+ * We have two contiguous IRQ regions, use a single rman.
+ */
+ error = rman_manage_region(&sc->irq_rman, CIU_IRQ_EN0_BEGIN,
+ CIU_IRQ_EN1_END);
+ if (error != 0)
+ return (error);
+
+ for (i = 0; i < CIU_IRQ_EN0_COUNT; i++) {
+ snprintf(name, sizeof name, "int%d:", i + CIU_IRQ_EN0_BEGIN);
+ ciu_en0_intrcnt[i] = mips_intrcnt_create(name);
+ }
+
+ for (i = 0; i < CIU_IRQ_EN1_COUNT; i++) {
+ snprintf(name, sizeof name, "int%d:", i + CIU_IRQ_EN1_BEGIN);
+ ciu_en1_intrcnt[i] = mips_intrcnt_create(name);
+ }
+
+ bus_generic_probe(dev);
+ bus_generic_attach(dev);
+
+ return (0);
+}
+
+static struct resource *
+ciu_alloc_resource(device_t bus, device_t child, int type, int *rid,
+ u_long start, u_long end, u_long count, u_int flags)
+{
+ struct resource *res;
+ struct ciu_softc *sc;
+
+ sc = device_get_softc(bus);
+
+ switch (type) {
+ case SYS_RES_IRQ:
+ break;
+ default:
+ return (bus_alloc_resource(device_get_parent(bus), type, rid,
+ start, end, count, flags));
+ }
+
+ /*
+ * One interrupt at a time for now.
+ */
+ if (start != end)
+ return (NULL);
+
+ res = rman_reserve_resource(&sc->irq_rman, start, end, count, flags,
+ child);
+ if (res != NULL)
+ return (res);
+
+ return (NULL);
+}
+
+static int
+ciu_setup_intr(device_t bus, device_t child, struct resource *res, int flags,
+ driver_filter_t *filter, driver_intr_t *intr, void *arg,
+ void **cookiep)
+{
+ struct intr_event *event, **eventp;
+ void (*mask_func)(void *);
+ void (*unmask_func)(void *);
+ int (*bind_func)(void *, u_char);
+ mips_intrcnt_t intrcnt;
+ int error;
+ int irq;
+
+ irq = rman_get_start(res);
+ if (irq <= CIU_IRQ_EN0_END) {
+ eventp = &ciu_en0_intr_events[irq - CIU_IRQ_EN0_BEGIN];
+ intrcnt = ciu_en0_intrcnt[irq - CIU_IRQ_EN0_BEGIN];
+ mask_func = ciu_en0_intr_mask;
+ unmask_func = ciu_en0_intr_unmask;
+#ifdef SMP
+ bind_func = ciu_en0_intr_bind;
+#endif
+ } else {
+ eventp = &ciu_en1_intr_events[irq - CIU_IRQ_EN1_BEGIN];
+ intrcnt = ciu_en1_intrcnt[irq - CIU_IRQ_EN1_BEGIN];
+ mask_func = ciu_en1_intr_mask;
+ unmask_func = ciu_en1_intr_unmask;
+#ifdef SMP
+ bind_func = ciu_en1_intr_bind;
+#endif
+ }
+#if !defined(SMP)
+ bind_func = NULL;
+#endif
+
+ if ((event = *eventp) == NULL) {
+ error = intr_event_create(eventp, (void *)(uintptr_t)irq, 0,
+ irq, mask_func, unmask_func, NULL, bind_func, "int%d", irq);
+ if (error != 0)
+ return (error);
+
+ event = *eventp;
+
+ unmask_func((void *)(uintptr_t)irq);
+ }
+
+ intr_event_add_handler(event, device_get_nameunit(child),
+ filter, intr, arg, intr_priority(flags), flags, cookiep);
+
+ mips_intrcnt_setname(intrcnt, event->ie_fullname);
+
+ return (0);
+}
+
+static int
+ciu_teardown_intr(device_t bus, device_t child, struct resource *res,
+ void *cookie)
+{
+ int error;
+
+ error = intr_event_remove_handler(cookie);
+ if (error != 0)
+ return (error);
+
+ return (0);
+}
+
+#ifdef SMP
+static int
+ciu_bind_intr(device_t bus, device_t child, struct resource *res, int cpu)
+{
+ struct intr_event *event;
+ int irq;
+
+ irq = rman_get_start(res);
+ if (irq <= CIU_IRQ_EN0_END)
+ event = ciu_en0_intr_events[irq - CIU_IRQ_EN0_BEGIN];
+ else
+ event = ciu_en1_intr_events[irq - CIU_IRQ_EN1_BEGIN];
+
+ return (intr_event_bind(event, cpu));
+}
+#endif
+
+static int
+ciu_describe_intr(device_t bus, device_t child, struct resource *res,
+ void *cookie, const char *descr)
+{
+ struct intr_event *event;
+ mips_intrcnt_t intrcnt;
+ int error;
+ int irq;
+
+ irq = rman_get_start(res);
+ if (irq <= CIU_IRQ_EN0_END) {
+ event = ciu_en0_intr_events[irq - CIU_IRQ_EN0_BEGIN];
+ intrcnt = ciu_en0_intrcnt[irq - CIU_IRQ_EN0_BEGIN];
+ } else {
+ event = ciu_en1_intr_events[irq - CIU_IRQ_EN1_BEGIN];
+ intrcnt = ciu_en1_intrcnt[irq - CIU_IRQ_EN1_BEGIN];
+ }
+
+ error = intr_event_describe_handler(event, cookie, descr);
+ if (error != 0)
+ return (error);
+
+ mips_intrcnt_setname(intrcnt, event->ie_fullname);
+
+ return (0);
+}
+
+static void
+ciu_hinted_child(device_t bus, const char *dname, int dunit)
+{
+ BUS_ADD_CHILD(bus, 0, dname, dunit);
+}
+
+static void
+ciu_en0_intr_mask(void *arg)
+{
+ uint64_t mask;
+ int irq;
+
+ irq = (uintptr_t)arg;
+ mask = cvmx_read_csr(CVMX_CIU_INTX_EN0(cvmx_get_core_num()*2));
+ mask &= ~(1ull << (irq - CIU_IRQ_EN0_BEGIN));
+ cvmx_write_csr(CVMX_CIU_INTX_EN0(cvmx_get_core_num()*2), mask);
+}
+
+static void
+ciu_en0_intr_unmask(void *arg)
+{
+ uint64_t mask;
+ int irq;
+
+ irq = (uintptr_t)arg;
+ mask = cvmx_read_csr(CVMX_CIU_INTX_EN0(cvmx_get_core_num()*2));
+ mask |= 1ull << (irq - CIU_IRQ_EN0_BEGIN);
+ cvmx_write_csr(CVMX_CIU_INTX_EN0(cvmx_get_core_num()*2), mask);
+}
+
+#ifdef SMP
+static int
+ciu_en0_intr_bind(void *arg, u_char target)
+{
+ uint64_t mask;
+ int core;
+ int irq;
+
+ irq = (uintptr_t)arg;
+ CPU_FOREACH(core) {
+ mask = cvmx_read_csr(CVMX_CIU_INTX_EN0(core*2));
+ if (core == target)
+ mask |= 1ull << (irq - CIU_IRQ_EN0_BEGIN);
+ else
+ mask &= ~(1ull << (irq - CIU_IRQ_EN0_BEGIN));
+ cvmx_write_csr(CVMX_CIU_INTX_EN0(core*2), mask);
+ }
+
+ return (0);
+}
+#endif
+
+static void
+ciu_en1_intr_mask(void *arg)
+{
+ uint64_t mask;
+ int irq;
+
+ irq = (uintptr_t)arg;
+ mask = cvmx_read_csr(CVMX_CIU_INTX_EN1(cvmx_get_core_num()*2));
+ mask &= ~(1ull << (irq - CIU_IRQ_EN1_BEGIN));
+ cvmx_write_csr(CVMX_CIU_INTX_EN1(cvmx_get_core_num()*2), mask);
+}
+
+static void
+ciu_en1_intr_unmask(void *arg)
+{
+ uint64_t mask;
+ int irq;
+
+ irq = (uintptr_t)arg;
+ mask = cvmx_read_csr(CVMX_CIU_INTX_EN1(cvmx_get_core_num()*2));
+ mask |= 1ull << (irq - CIU_IRQ_EN1_BEGIN);
+ cvmx_write_csr(CVMX_CIU_INTX_EN1(cvmx_get_core_num()*2), mask);
+}
+
+#ifdef SMP
+static int
+ciu_en1_intr_bind(void *arg, u_char target)
+{
+ uint64_t mask;
+ int core;
+ int irq;
+
+ irq = (uintptr_t)arg;
+ CPU_FOREACH(core) {
+ mask = cvmx_read_csr(CVMX_CIU_INTX_EN1(core*2));
+ if (core == target)
+ mask |= 1ull << (irq - CIU_IRQ_EN1_BEGIN);
+ else
+ mask &= ~(1ull << (irq - CIU_IRQ_EN1_BEGIN));
+ cvmx_write_csr(CVMX_CIU_INTX_EN1(core*2), mask);
+ }
+
+ return (0);
+}
+#endif
+
+static int
+ciu_intr(void *arg)
+{
+ struct ciu_softc *sc;
+ uint64_t en0_sum, en1_sum;
+ uint64_t en0_mask, en1_mask;
+ int irq_index;
+ int error;
+
+ sc = arg;
+ (void)sc;
+
+ en0_sum = cvmx_read_csr(CVMX_CIU_INTX_SUM0(cvmx_get_core_num()*2));
+ en1_sum = cvmx_read_csr(CVMX_CIU_INT_SUM1);
+
+ en0_mask = cvmx_read_csr(CVMX_CIU_INTX_EN0(cvmx_get_core_num()*2));
+ en1_mask = cvmx_read_csr(CVMX_CIU_INTX_EN1(cvmx_get_core_num()*2));
+
+ en0_sum &= en0_mask;
+ en1_sum &= en1_mask;
+
+ if (en0_sum == 0 && en1_sum == 0)
+ return (FILTER_STRAY);
+
+ irq_index = 0;
+ for (irq_index = 0; en0_sum != 0; irq_index++, en0_sum >>= 1) {
+ if ((en0_sum & 1) == 0)
+ continue;
+
+ mips_intrcnt_inc(ciu_en0_intrcnt[irq_index]);
+
+ error = intr_event_handle(ciu_en0_intr_events[irq_index], NULL);
+ if (error != 0)
+ printf("%s: stray en0 irq%d\n", __func__, irq_index);
+ }
+
+ irq_index = 0;
+ for (irq_index = 0; en1_sum != 0; irq_index++, en1_sum >>= 1) {
+ if ((en1_sum & 1) == 0)
+ continue;
+
+ mips_intrcnt_inc(ciu_en1_intrcnt[irq_index]);
+
+ error = intr_event_handle(ciu_en1_intr_events[irq_index], NULL);
+ if (error != 0)
+ printf("%s: stray en1 irq%d\n", __func__, irq_index);
+ }
+
+ return (FILTER_HANDLED);
+}
+
+static device_method_t ciu_methods[] = {
+ DEVMETHOD(device_probe, ciu_probe),
+ DEVMETHOD(device_attach, ciu_attach),
+
+ DEVMETHOD(bus_alloc_resource, ciu_alloc_resource),
+ DEVMETHOD(bus_activate_resource,bus_generic_activate_resource),
+ DEVMETHOD(bus_setup_intr, ciu_setup_intr),
+ DEVMETHOD(bus_teardown_intr, ciu_teardown_intr),
+#ifdef SMP
+ DEVMETHOD(bus_bind_intr, ciu_bind_intr),
+#endif
+ DEVMETHOD(bus_describe_intr, ciu_describe_intr),
+
+ DEVMETHOD(bus_add_child, bus_generic_add_child),
+ DEVMETHOD(bus_hinted_child, ciu_hinted_child),
+
+ { 0, 0 }
+};
+
+static driver_t ciu_driver = {
+ "ciu",
+ ciu_methods,
+ sizeof(struct ciu_softc),
+};
+static devclass_t ciu_devclass;
+DRIVER_MODULE(ciu, nexus, ciu_driver, ciu_devclass, 0, 0);
Property changes on: trunk/sys/mips/cavium/ciu.c
___________________________________________________________________
Added: svn:eol-style
## -0,0 +1 ##
+native
\ No newline at end of property
Added: svn:keywords
## -0,0 +1 ##
+MidnightBSD=%H
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+text/plain
\ No newline at end of property
Added: trunk/sys/mips/cavium/cryptocteon/cavium_crypto.c
===================================================================
--- trunk/sys/mips/cavium/cryptocteon/cavium_crypto.c (rev 0)
+++ trunk/sys/mips/cavium/cryptocteon/cavium_crypto.c 2018-05-26 21:55:02 UTC (rev 9987)
@@ -0,0 +1,2137 @@
+/* $MidnightBSD$ */
+/*
+ * vim:sw=4 ts=8
+ */
+/*
+ * Copyright (c) 2009 David McCullough <david.mccullough at securecomputing.com>
+ *
+ * Copyright (c) 2003-2007 Cavium Networks (support at cavium.com). All rights
+ * reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. All advertising materials mentioning features or use of this software
+ * must display the following acknowledgement:
+ * This product includes software developed by Cavium Networks
+ * 4. Cavium Networks' name may not be used to endorse or promote products
+ * derived from this software without specific prior written permission.
+ *
+ * This Software, including technical data, may be subject to U.S. export
+ * control laws, including the U.S. Export Administration Act and its
+ * associated regulations, and may be subject to export or import regulations
+ * in other countries. You warrant that You will comply strictly in all
+ * respects with all such regulations and acknowledge that you have the
+ * responsibility to obtain licenses to export, re-export or import the
+ * Software.
+ *
+ * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS" AND
+ * WITH ALL FAULTS AND CAVIUM MAKES NO PROMISES, REPRESENTATIONS OR WARRANTIES,
+ * EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO THE
+ * SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
+ * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
+ * SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES OF TITLE,
+ * MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR PURPOSE, LACK OF
+ * VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET POSSESSION OR
+ * CORRESPONDENCE TO DESCRIPTION. THE ENTIRE RISK ARISING OUT OF USE OR
+ * PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
+*/
+/****************************************************************************/
+
+#include <sys/cdefs.h>
+__FBSDID("$FreeBSD: stable/10/sys/mips/cavium/cryptocteon/cavium_crypto.c 229677 2012-01-06 01:23:26Z gonzo $");
+
+#include <sys/param.h>
+#include <sys/systm.h>
+#include <sys/kernel.h>
+#include <sys/module.h>
+#include <sys/malloc.h>
+#include <sys/uio.h>
+
+#include <opencrypto/cryptodev.h>
+
+#include <contrib/octeon-sdk/cvmx.h>
+
+#include <mips/cavium/cryptocteon/cryptocteonvar.h>
+
+/****************************************************************************/
+
+#define IOV_INIT(iov, ptr, idx, len) \
+ do { \
+ (idx) = 0; \
+ (ptr) = (iov)[(idx)].iov_base; \
+ (len) = (iov)[(idx)].iov_len; \
+ } while (0)
+
+/*
+ * XXX
+ * It would be better if this were an IOV_READ/IOV_WRITE macro instead so
+ * that we could detect overflow before it happens rather than right after,
+ * which is especially bad since there is usually no IOV_CONSUME after the
+ * final read or write.
+ */
+#define IOV_CONSUME(iov, ptr, idx, len) \
+ do { \
+ if ((len) > sizeof *(ptr)) { \
+ (len) -= sizeof *(ptr); \
+ (ptr)++; \
+ } else { \
+ if ((len) != sizeof *(ptr)) \
+ panic("%s: went past end of iovec.", __func__); \
+ (idx)++; \
+ (ptr) = (iov)[(idx)].iov_base; \
+ (len) = (iov)[(idx)].iov_len; \
+ } \
+ } while (0)
+
+#define ESP_HEADER_LENGTH 8
+#define DES_CBC_IV_LENGTH 8
+#define AES_CBC_IV_LENGTH 16
+#define ESP_HMAC_LEN 12
+
+#define ESP_HEADER_LENGTH 8
+#define DES_CBC_IV_LENGTH 8
+
+/****************************************************************************/
+
+#define CVM_LOAD_SHA_UNIT(dat, next) { \
+ if (next == 0) { \
+ next = 1; \
+ CVMX_MT_HSH_DAT (dat, 0); \
+ } else if (next == 1) { \
+ next = 2; \
+ CVMX_MT_HSH_DAT (dat, 1); \
+ } else if (next == 2) { \
+ next = 3; \
+ CVMX_MT_HSH_DAT (dat, 2); \
+ } else if (next == 3) { \
+ next = 4; \
+ CVMX_MT_HSH_DAT (dat, 3); \
+ } else if (next == 4) { \
+ next = 5; \
+ CVMX_MT_HSH_DAT (dat, 4); \
+ } else if (next == 5) { \
+ next = 6; \
+ CVMX_MT_HSH_DAT (dat, 5); \
+ } else if (next == 6) { \
+ next = 7; \
+ CVMX_MT_HSH_DAT (dat, 6); \
+ } else { \
+ CVMX_MT_HSH_STARTSHA (dat); \
+ next = 0; \
+ } \
+}
+
+#define CVM_LOAD2_SHA_UNIT(dat1, dat2, next) { \
+ if (next == 0) { \
+ CVMX_MT_HSH_DAT (dat1, 0); \
+ CVMX_MT_HSH_DAT (dat2, 1); \
+ next = 2; \
+ } else if (next == 1) { \
+ CVMX_MT_HSH_DAT (dat1, 1); \
+ CVMX_MT_HSH_DAT (dat2, 2); \
+ next = 3; \
+ } else if (next == 2) { \
+ CVMX_MT_HSH_DAT (dat1, 2); \
+ CVMX_MT_HSH_DAT (dat2, 3); \
+ next = 4; \
+ } else if (next == 3) { \
+ CVMX_MT_HSH_DAT (dat1, 3); \
+ CVMX_MT_HSH_DAT (dat2, 4); \
+ next = 5; \
+ } else if (next == 4) { \
+ CVMX_MT_HSH_DAT (dat1, 4); \
+ CVMX_MT_HSH_DAT (dat2, 5); \
+ next = 6; \
+ } else if (next == 5) { \
+ CVMX_MT_HSH_DAT (dat1, 5); \
+ CVMX_MT_HSH_DAT (dat2, 6); \
+ next = 7; \
+ } else if (next == 6) { \
+ CVMX_MT_HSH_DAT (dat1, 6); \
+ CVMX_MT_HSH_STARTSHA (dat2); \
+ next = 0; \
+ } else { \
+ CVMX_MT_HSH_STARTSHA (dat1); \
+ CVMX_MT_HSH_DAT (dat2, 0); \
+ next = 1; \
+ } \
+}
+
+/****************************************************************************/
+
+#define CVM_LOAD_MD5_UNIT(dat, next) { \
+ if (next == 0) { \
+ next = 1; \
+ CVMX_MT_HSH_DAT (dat, 0); \
+ } else if (next == 1) { \
+ next = 2; \
+ CVMX_MT_HSH_DAT (dat, 1); \
+ } else if (next == 2) { \
+ next = 3; \
+ CVMX_MT_HSH_DAT (dat, 2); \
+ } else if (next == 3) { \
+ next = 4; \
+ CVMX_MT_HSH_DAT (dat, 3); \
+ } else if (next == 4) { \
+ next = 5; \
+ CVMX_MT_HSH_DAT (dat, 4); \
+ } else if (next == 5) { \
+ next = 6; \
+ CVMX_MT_HSH_DAT (dat, 5); \
+ } else if (next == 6) { \
+ next = 7; \
+ CVMX_MT_HSH_DAT (dat, 6); \
+ } else { \
+ CVMX_MT_HSH_STARTMD5 (dat); \
+ next = 0; \
+ } \
+}
+
+#define CVM_LOAD2_MD5_UNIT(dat1, dat2, next) { \
+ if (next == 0) { \
+ CVMX_MT_HSH_DAT (dat1, 0); \
+ CVMX_MT_HSH_DAT (dat2, 1); \
+ next = 2; \
+ } else if (next == 1) { \
+ CVMX_MT_HSH_DAT (dat1, 1); \
+ CVMX_MT_HSH_DAT (dat2, 2); \
+ next = 3; \
+ } else if (next == 2) { \
+ CVMX_MT_HSH_DAT (dat1, 2); \
+ CVMX_MT_HSH_DAT (dat2, 3); \
+ next = 4; \
+ } else if (next == 3) { \
+ CVMX_MT_HSH_DAT (dat1, 3); \
+ CVMX_MT_HSH_DAT (dat2, 4); \
+ next = 5; \
+ } else if (next == 4) { \
+ CVMX_MT_HSH_DAT (dat1, 4); \
+ CVMX_MT_HSH_DAT (dat2, 5); \
+ next = 6; \
+ } else if (next == 5) { \
+ CVMX_MT_HSH_DAT (dat1, 5); \
+ CVMX_MT_HSH_DAT (dat2, 6); \
+ next = 7; \
+ } else if (next == 6) { \
+ CVMX_MT_HSH_DAT (dat1, 6); \
+ CVMX_MT_HSH_STARTMD5 (dat2); \
+ next = 0; \
+ } else { \
+ CVMX_MT_HSH_STARTMD5 (dat1); \
+ CVMX_MT_HSH_DAT (dat2, 0); \
+ next = 1; \
+ } \
+}
+
+/****************************************************************************/
+
+void
+octo_calc_hash(uint8_t auth, unsigned char *key, uint64_t *inner, uint64_t *outer)
+{
+ uint8_t hash_key[64];
+ uint64_t *key1;
+ register uint64_t xor1 = 0x3636363636363636ULL;
+ register uint64_t xor2 = 0x5c5c5c5c5c5c5c5cULL;
+
+ dprintf("%s()\n", __func__);
+
+ memset(hash_key, 0, sizeof(hash_key));
+ memcpy(hash_key, (uint8_t *) key, (auth ? 20 : 16));
+ key1 = (uint64_t *) hash_key;
+ if (auth) {
+ CVMX_MT_HSH_IV(0x67452301EFCDAB89ULL, 0);
+ CVMX_MT_HSH_IV(0x98BADCFE10325476ULL, 1);
+ CVMX_MT_HSH_IV(0xC3D2E1F000000000ULL, 2);
+ } else {
+ CVMX_MT_HSH_IV(0x0123456789ABCDEFULL, 0);
+ CVMX_MT_HSH_IV(0xFEDCBA9876543210ULL, 1);
+ }
+
+ CVMX_MT_HSH_DAT((*key1 ^ xor1), 0);
+ key1++;
+ CVMX_MT_HSH_DAT((*key1 ^ xor1), 1);
+ key1++;
+ CVMX_MT_HSH_DAT((*key1 ^ xor1), 2);
+ key1++;
+ CVMX_MT_HSH_DAT((*key1 ^ xor1), 3);
+ key1++;
+ CVMX_MT_HSH_DAT((*key1 ^ xor1), 4);
+ key1++;
+ CVMX_MT_HSH_DAT((*key1 ^ xor1), 5);
+ key1++;
+ CVMX_MT_HSH_DAT((*key1 ^ xor1), 6);
+ key1++;
+ if (auth)
+ CVMX_MT_HSH_STARTSHA((*key1 ^ xor1));
+ else
+ CVMX_MT_HSH_STARTMD5((*key1 ^ xor1));
+
+ CVMX_MF_HSH_IV(inner[0], 0);
+ CVMX_MF_HSH_IV(inner[1], 1);
+ if (auth) {
+ inner[2] = 0;
+ CVMX_MF_HSH_IV(((uint64_t *) inner)[2], 2);
+ }
+
+ memset(hash_key, 0, sizeof(hash_key));
+ memcpy(hash_key, (uint8_t *) key, (auth ? 20 : 16));
+ key1 = (uint64_t *) hash_key;
+ if (auth) {
+ CVMX_MT_HSH_IV(0x67452301EFCDAB89ULL, 0);
+ CVMX_MT_HSH_IV(0x98BADCFE10325476ULL, 1);
+ CVMX_MT_HSH_IV(0xC3D2E1F000000000ULL, 2);
+ } else {
+ CVMX_MT_HSH_IV(0x0123456789ABCDEFULL, 0);
+ CVMX_MT_HSH_IV(0xFEDCBA9876543210ULL, 1);
+ }
+
+ CVMX_MT_HSH_DAT((*key1 ^ xor2), 0);
+ key1++;
+ CVMX_MT_HSH_DAT((*key1 ^ xor2), 1);
+ key1++;
+ CVMX_MT_HSH_DAT((*key1 ^ xor2), 2);
+ key1++;
+ CVMX_MT_HSH_DAT((*key1 ^ xor2), 3);
+ key1++;
+ CVMX_MT_HSH_DAT((*key1 ^ xor2), 4);
+ key1++;
+ CVMX_MT_HSH_DAT((*key1 ^ xor2), 5);
+ key1++;
+ CVMX_MT_HSH_DAT((*key1 ^ xor2), 6);
+ key1++;
+ if (auth)
+ CVMX_MT_HSH_STARTSHA((*key1 ^ xor2));
+ else
+ CVMX_MT_HSH_STARTMD5((*key1 ^ xor2));
+
+ CVMX_MF_HSH_IV(outer[0], 0);
+ CVMX_MF_HSH_IV(outer[1], 1);
+ if (auth) {
+ outer[2] = 0;
+ CVMX_MF_HSH_IV(outer[2], 2);
+ }
+ return;
+}
+
+/****************************************************************************/
+/* DES functions */
+
+int
+octo_des_cbc_encrypt(
+ struct octo_sess *od,
+ struct iovec *iov, size_t iovcnt, size_t iovlen,
+ int auth_off, int auth_len,
+ int crypt_off, int crypt_len,
+ int icv_off, uint8_t *ivp)
+{
+ uint64_t *data;
+ int data_i, data_l;
+
+ dprintf("%s()\n", __func__);
+
+ if (__predict_false(od == NULL || iov==NULL || iovlen==0 || ivp==NULL ||
+ (crypt_off & 0x7) || (crypt_off + crypt_len > iovlen))) {
+ dprintf("%s: Bad parameters od=%p iov=%p iovlen=%jd "
+ "auth_off=%d auth_len=%d crypt_off=%d crypt_len=%d "
+ "icv_off=%d ivp=%p\n", __func__, od, iov, iovlen,
+ auth_off, auth_len, crypt_off, crypt_len, icv_off, ivp);
+ return -EINVAL;
+ }
+
+ IOV_INIT(iov, data, data_i, data_l);
+
+ CVMX_PREFETCH0(ivp);
+ CVMX_PREFETCH0(od->octo_enckey);
+
+
+ /* load 3DES Key */
+ CVMX_MT_3DES_KEY(((uint64_t *) od->octo_enckey)[0], 0);
+ if (od->octo_encklen == 24) {
+ CVMX_MT_3DES_KEY(((uint64_t *) od->octo_enckey)[1], 1);
+ CVMX_MT_3DES_KEY(((uint64_t *) od->octo_enckey)[2], 2);
+ } else if (od->octo_encklen == 8) {
+ CVMX_MT_3DES_KEY(((uint64_t *) od->octo_enckey)[0], 1);
+ CVMX_MT_3DES_KEY(((uint64_t *) od->octo_enckey)[0], 2);
+ } else {
+ dprintf("%s: Bad key length %d\n", __func__, od->octo_encklen);
+ return -EINVAL;
+ }
+
+ CVMX_MT_3DES_IV(* (uint64_t *) ivp);
+
+ while (crypt_off > 0) {
+ IOV_CONSUME(iov, data, data_i, data_l);
+ crypt_off -= 8;
+ }
+
+ while (crypt_len > 0) {
+ CVMX_MT_3DES_ENC_CBC(*data);
+ CVMX_MF_3DES_RESULT(*data);
+ IOV_CONSUME(iov, data, data_i, data_l);
+ crypt_len -= 8;
+ }
+
+ return 0;
+}
+
+
+int
+octo_des_cbc_decrypt(
+ struct octo_sess *od,
+ struct iovec *iov, size_t iovcnt, size_t iovlen,
+ int auth_off, int auth_len,
+ int crypt_off, int crypt_len,
+ int icv_off, uint8_t *ivp)
+{
+ uint64_t *data;
+ int data_i, data_l;
+
+ dprintf("%s()\n", __func__);
+
+ if (__predict_false(od == NULL || iov==NULL || iovlen==0 || ivp==NULL ||
+ (crypt_off & 0x7) || (crypt_off + crypt_len > iovlen))) {
+ dprintf("%s: Bad parameters od=%p iov=%p iovlen=%jd "
+ "auth_off=%d auth_len=%d crypt_off=%d crypt_len=%d "
+ "icv_off=%d ivp=%p\n", __func__, od, iov, iovlen,
+ auth_off, auth_len, crypt_off, crypt_len, icv_off, ivp);
+ return -EINVAL;
+ }
+
+ IOV_INIT(iov, data, data_i, data_l);
+
+ CVMX_PREFETCH0(ivp);
+ CVMX_PREFETCH0(od->octo_enckey);
+
+ /* load 3DES Key */
+ CVMX_MT_3DES_KEY(((uint64_t *) od->octo_enckey)[0], 0);
+ if (od->octo_encklen == 24) {
+ CVMX_MT_3DES_KEY(((uint64_t *) od->octo_enckey)[1], 1);
+ CVMX_MT_3DES_KEY(((uint64_t *) od->octo_enckey)[2], 2);
+ } else if (od->octo_encklen == 8) {
+ CVMX_MT_3DES_KEY(((uint64_t *) od->octo_enckey)[0], 1);
+ CVMX_MT_3DES_KEY(((uint64_t *) od->octo_enckey)[0], 2);
+ } else {
+ dprintf("%s: Bad key length %d\n", __func__, od->octo_encklen);
+ return -EINVAL;
+ }
+
+ CVMX_MT_3DES_IV(* (uint64_t *) ivp);
+
+ while (crypt_off > 0) {
+ IOV_CONSUME(iov, data, data_i, data_l);
+ crypt_off -= 8;
+ }
+
+ while (crypt_len > 0) {
+ CVMX_MT_3DES_DEC_CBC(*data);
+ CVMX_MF_3DES_RESULT(*data);
+ IOV_CONSUME(iov, data, data_i, data_l);
+ crypt_len -= 8;
+ }
+
+ return 0;
+}
+
+/****************************************************************************/
+/* AES functions */
+
+int
+octo_aes_cbc_encrypt(
+ struct octo_sess *od,
+ struct iovec *iov, size_t iovcnt, size_t iovlen,
+ int auth_off, int auth_len,
+ int crypt_off, int crypt_len,
+ int icv_off, uint8_t *ivp)
+{
+ uint64_t *data, *pdata;
+ int data_i, data_l;
+
+ dprintf("%s()\n", __func__);
+
+ if (__predict_false(od == NULL || iov==NULL || iovlen==0 || ivp==NULL ||
+ (crypt_off & 0x7) || (crypt_off + crypt_len > iovlen))) {
+ dprintf("%s: Bad parameters od=%p iov=%p iovlen=%jd "
+ "auth_off=%d auth_len=%d crypt_off=%d crypt_len=%d "
+ "icv_off=%d ivp=%p\n", __func__, od, iov, iovlen,
+ auth_off, auth_len, crypt_off, crypt_len, icv_off, ivp);
+ return -EINVAL;
+ }
+
+ IOV_INIT(iov, data, data_i, data_l);
+
+ CVMX_PREFETCH0(ivp);
+ CVMX_PREFETCH0(od->octo_enckey);
+
+ /* load AES Key */
+ CVMX_MT_AES_KEY(((uint64_t *) od->octo_enckey)[0], 0);
+ CVMX_MT_AES_KEY(((uint64_t *) od->octo_enckey)[1], 1);
+
+ if (od->octo_encklen == 16) {
+ CVMX_MT_AES_KEY(0x0, 2);
+ CVMX_MT_AES_KEY(0x0, 3);
+ } else if (od->octo_encklen == 24) {
+ CVMX_MT_AES_KEY(((uint64_t *) od->octo_enckey)[2], 2);
+ CVMX_MT_AES_KEY(0x0, 3);
+ } else if (od->octo_encklen == 32) {
+ CVMX_MT_AES_KEY(((uint64_t *) od->octo_enckey)[2], 2);
+ CVMX_MT_AES_KEY(((uint64_t *) od->octo_enckey)[3], 3);
+ } else {
+ dprintf("%s: Bad key length %d\n", __func__, od->octo_encklen);
+ return -EINVAL;
+ }
+ CVMX_MT_AES_KEYLENGTH(od->octo_encklen / 8 - 1);
+
+ CVMX_MT_AES_IV(((uint64_t *) ivp)[0], 0);
+ CVMX_MT_AES_IV(((uint64_t *) ivp)[1], 1);
+
+ while (crypt_off > 0) {
+ IOV_CONSUME(iov, data, data_i, data_l);
+ crypt_off -= 8;
+ }
+
+ while (crypt_len > 0) {
+ pdata = data;
+ CVMX_MT_AES_ENC_CBC0(*data);
+ IOV_CONSUME(iov, data, data_i, data_l);
+ CVMX_MT_AES_ENC_CBC1(*data);
+ CVMX_MF_AES_RESULT(*pdata, 0);
+ CVMX_MF_AES_RESULT(*data, 1);
+ IOV_CONSUME(iov, data, data_i, data_l);
+ crypt_len -= 16;
+ }
+
+ return 0;
+}
+
+
+int
+octo_aes_cbc_decrypt(
+ struct octo_sess *od,
+ struct iovec *iov, size_t iovcnt, size_t iovlen,
+ int auth_off, int auth_len,
+ int crypt_off, int crypt_len,
+ int icv_off, uint8_t *ivp)
+{
+ uint64_t *data, *pdata;
+ int data_i, data_l;
+
+ dprintf("%s()\n", __func__);
+
+ if (__predict_false(od == NULL || iov==NULL || iovlen==0 || ivp==NULL ||
+ (crypt_off & 0x7) || (crypt_off + crypt_len > iovlen))) {
+ dprintf("%s: Bad parameters od=%p iov=%p iovlen=%jd "
+ "auth_off=%d auth_len=%d crypt_off=%d crypt_len=%d "
+ "icv_off=%d ivp=%p\n", __func__, od, iov, iovlen,
+ auth_off, auth_len, crypt_off, crypt_len, icv_off, ivp);
+ return -EINVAL;
+ }
+
+ IOV_INIT(iov, data, data_i, data_l);
+
+ CVMX_PREFETCH0(ivp);
+ CVMX_PREFETCH0(od->octo_enckey);
+
+ /* load AES Key */
+ CVMX_MT_AES_KEY(((uint64_t *) od->octo_enckey)[0], 0);
+ CVMX_MT_AES_KEY(((uint64_t *) od->octo_enckey)[1], 1);
+
+ if (od->octo_encklen == 16) {
+ CVMX_MT_AES_KEY(0x0, 2);
+ CVMX_MT_AES_KEY(0x0, 3);
+ } else if (od->octo_encklen == 24) {
+ CVMX_MT_AES_KEY(((uint64_t *) od->octo_enckey)[2], 2);
+ CVMX_MT_AES_KEY(0x0, 3);
+ } else if (od->octo_encklen == 32) {
+ CVMX_MT_AES_KEY(((uint64_t *) od->octo_enckey)[2], 2);
+ CVMX_MT_AES_KEY(((uint64_t *) od->octo_enckey)[3], 3);
+ } else {
+ dprintf("%s: Bad key length %d\n", __func__, od->octo_encklen);
+ return -EINVAL;
+ }
+ CVMX_MT_AES_KEYLENGTH(od->octo_encklen / 8 - 1);
+
+ CVMX_MT_AES_IV(((uint64_t *) ivp)[0], 0);
+ CVMX_MT_AES_IV(((uint64_t *) ivp)[1], 1);
+
+ while (crypt_off > 0) {
+ IOV_CONSUME(iov, data, data_i, data_l);
+ crypt_off -= 8;
+ }
+
+ while (crypt_len > 0) {
+ pdata = data;
+ CVMX_MT_AES_DEC_CBC0(*data);
+ IOV_CONSUME(iov, data, data_i, data_l);
+ CVMX_MT_AES_DEC_CBC1(*data);
+ CVMX_MF_AES_RESULT(*pdata, 0);
+ CVMX_MF_AES_RESULT(*data, 1);
+ IOV_CONSUME(iov, data, data_i, data_l);
+ crypt_len -= 16;
+ }
+
+ return 0;
+}
+
+/****************************************************************************/
+/* MD5 */
+
+int
+octo_null_md5_encrypt(
+ struct octo_sess *od,
+ struct iovec *iov, size_t iovcnt, size_t iovlen,
+ int auth_off, int auth_len,
+ int crypt_off, int crypt_len,
+ int icv_off, uint8_t *ivp)
+{
+ register int next = 0;
+ uint64_t *data;
+ uint64_t tmp1, tmp2;
+ int data_i, data_l, alen = auth_len;
+
+ dprintf("%s()\n", __func__);
+
+ if (__predict_false(od == NULL || iov==NULL || iovlen==0 ||
+ (auth_off & 0x7) || (auth_off + auth_len > iovlen))) {
+ dprintf("%s: Bad parameters od=%p iov=%p iovlen=%jd "
+ "auth_off=%d auth_len=%d crypt_off=%d crypt_len=%d "
+ "icv_off=%d ivp=%p\n", __func__, od, iov, iovlen,
+ auth_off, auth_len, crypt_off, crypt_len, icv_off, ivp);
+ return -EINVAL;
+ }
+
+ IOV_INIT(iov, data, data_i, data_l);
+
+ /* Load MD5 IV */
+ CVMX_MT_HSH_IV(od->octo_hminner[0], 0);
+ CVMX_MT_HSH_IV(od->octo_hminner[1], 1);
+
+ while (auth_off > 0) {
+ IOV_CONSUME(iov, data, data_i, data_l);
+ auth_off -= 8;
+ }
+
+ while (auth_len > 0) {
+ CVM_LOAD_MD5_UNIT(*data, next);
+ auth_len -= 8;
+ IOV_CONSUME(iov, data, data_i, data_l);
+ }
+
+ /* finish the hash */
+ CVMX_PREFETCH0(od->octo_hmouter);
+#if 0
+ if (__predict_false(inplen)) {
+ uint64_t tmp = 0;
+ uint8_t *p = (uint8_t *) & tmp;
+ p[inplen] = 0x80;
+ do {
+ inplen--;
+ p[inplen] = ((uint8_t *) data)[inplen];
+ } while (inplen);
+ CVM_LOAD_MD5_UNIT(tmp, next);
+ } else {
+ CVM_LOAD_MD5_UNIT(0x8000000000000000ULL, next);
+ }
+#else
+ CVM_LOAD_MD5_UNIT(0x8000000000000000ULL, next);
+#endif
+
+ /* Finish Inner hash */
+ while (next != 7) {
+ CVM_LOAD_MD5_UNIT(((uint64_t) 0x0ULL), next);
+ }
+ CVMX_ES64(tmp1, ((alen + 64) << 3));
+ CVM_LOAD_MD5_UNIT(tmp1, next);
+
+ /* Get the inner hash of HMAC */
+ CVMX_MF_HSH_IV(tmp1, 0);
+ CVMX_MF_HSH_IV(tmp2, 1);
+
+ /* Initialize hash unit */
+ CVMX_MT_HSH_IV(od->octo_hmouter[0], 0);
+ CVMX_MT_HSH_IV(od->octo_hmouter[1], 1);
+
+ CVMX_MT_HSH_DAT(tmp1, 0);
+ CVMX_MT_HSH_DAT(tmp2, 1);
+ CVMX_MT_HSH_DAT(0x8000000000000000ULL, 2);
+ CVMX_MT_HSH_DATZ(3);
+ CVMX_MT_HSH_DATZ(4);
+ CVMX_MT_HSH_DATZ(5);
+ CVMX_MT_HSH_DATZ(6);
+ CVMX_ES64(tmp1, ((64 + 16) << 3));
+ CVMX_MT_HSH_STARTMD5(tmp1);
+
+ /* save the HMAC */
+ IOV_INIT(iov, data, data_i, data_l);
+ while (icv_off > 0) {
+ IOV_CONSUME(iov, data, data_i, data_l);
+ icv_off -= 8;
+ }
+ CVMX_MF_HSH_IV(*data, 0);
+ IOV_CONSUME(iov, data, data_i, data_l);
+ CVMX_MF_HSH_IV(tmp1, 1);
+ *(uint32_t *)data = (uint32_t) (tmp1 >> 32);
+
+ return 0;
+}
+
+/****************************************************************************/
+/* SHA1 */
+
+int
+octo_null_sha1_encrypt(
+ struct octo_sess *od,
+ struct iovec *iov, size_t iovcnt, size_t iovlen,
+ int auth_off, int auth_len,
+ int crypt_off, int crypt_len,
+ int icv_off, uint8_t *ivp)
+{
+ register int next = 0;
+ uint64_t *data;
+ uint64_t tmp1, tmp2, tmp3;
+ int data_i, data_l, alen = auth_len;
+
+ dprintf("%s()\n", __func__);
+
+ if (__predict_false(od == NULL || iov==NULL || iovlen==0 ||
+ (auth_off & 0x7) || (auth_off + auth_len > iovlen))) {
+ dprintf("%s: Bad parameters od=%p iov=%p iovlen=%jd "
+ "auth_off=%d auth_len=%d crypt_off=%d crypt_len=%d "
+ "icv_off=%d ivp=%p\n", __func__, od, iov, iovlen,
+ auth_off, auth_len, crypt_off, crypt_len, icv_off, ivp);
+ return -EINVAL;
+ }
+
+ IOV_INIT(iov, data, data_i, data_l);
+
+ /* Load SHA1 IV */
+ CVMX_MT_HSH_IV(od->octo_hminner[0], 0);
+ CVMX_MT_HSH_IV(od->octo_hminner[1], 1);
+ CVMX_MT_HSH_IV(od->octo_hminner[2], 2);
+
+ while (auth_off > 0) {
+ IOV_CONSUME(iov, data, data_i, data_l);
+ auth_off -= 8;
+ }
+
+ while (auth_len > 0) {
+ CVM_LOAD_SHA_UNIT(*data, next);
+ auth_len -= 8;
+ IOV_CONSUME(iov, data, data_i, data_l);
+ }
+
+ /* finish the hash */
+ CVMX_PREFETCH0(od->octo_hmouter);
+#if 0
+ if (__predict_false(inplen)) {
+ uint64_t tmp = 0;
+ uint8_t *p = (uint8_t *) & tmp;
+ p[inplen] = 0x80;
+ do {
+ inplen--;
+ p[inplen] = ((uint8_t *) data)[inplen];
+ } while (inplen);
+ CVM_LOAD_MD5_UNIT(tmp, next);
+ } else {
+ CVM_LOAD_MD5_UNIT(0x8000000000000000ULL, next);
+ }
+#else
+ CVM_LOAD_SHA_UNIT(0x8000000000000000ULL, next);
+#endif
+
+ /* Finish Inner hash */
+ while (next != 7) {
+ CVM_LOAD_SHA_UNIT(((uint64_t) 0x0ULL), next);
+ }
+ CVM_LOAD_SHA_UNIT((uint64_t) ((alen + 64) << 3), next);
+
+ /* Get the inner hash of HMAC */
+ CVMX_MF_HSH_IV(tmp1, 0);
+ CVMX_MF_HSH_IV(tmp2, 1);
+ tmp3 = 0;
+ CVMX_MF_HSH_IV(tmp3, 2);
+
+ /* Initialize hash unit */
+ CVMX_MT_HSH_IV(od->octo_hmouter[0], 0);
+ CVMX_MT_HSH_IV(od->octo_hmouter[1], 1);
+ CVMX_MT_HSH_IV(od->octo_hmouter[2], 2);
+
+ CVMX_MT_HSH_DAT(tmp1, 0);
+ CVMX_MT_HSH_DAT(tmp2, 1);
+ tmp3 |= 0x0000000080000000;
+ CVMX_MT_HSH_DAT(tmp3, 2);
+ CVMX_MT_HSH_DATZ(3);
+ CVMX_MT_HSH_DATZ(4);
+ CVMX_MT_HSH_DATZ(5);
+ CVMX_MT_HSH_DATZ(6);
+ CVMX_MT_HSH_STARTSHA((uint64_t) ((64 + 20) << 3));
+
+ /* save the HMAC */
+ IOV_INIT(iov, data, data_i, data_l);
+ while (icv_off > 0) {
+ IOV_CONSUME(iov, data, data_i, data_l);
+ icv_off -= 8;
+ }
+ CVMX_MF_HSH_IV(*data, 0);
+ IOV_CONSUME(iov, data, data_i, data_l);
+ CVMX_MF_HSH_IV(tmp1, 1);
+ *(uint32_t *)data = (uint32_t) (tmp1 >> 32);
+
+ return 0;
+}
+
+/****************************************************************************/
+/* DES MD5 */
+
+int
+octo_des_cbc_md5_encrypt(
+ struct octo_sess *od,
+ struct iovec *iov, size_t iovcnt, size_t iovlen,
+ int auth_off, int auth_len,
+ int crypt_off, int crypt_len,
+ int icv_off, uint8_t *ivp)
+{
+ register int next = 0;
+ union {
+ uint32_t data32[2];
+ uint64_t data64[1];
+ } mydata;
+ uint64_t *data = &mydata.data64[0];
+ uint32_t *data32;
+ uint64_t tmp1, tmp2;
+ int data_i, data_l, alen = auth_len;
+
+ dprintf("%s()\n", __func__);
+
+ if (__predict_false(od == NULL || iov==NULL || iovlen==0 || ivp==NULL ||
+ (crypt_off & 0x3) || (crypt_off + crypt_len > iovlen) ||
+ (crypt_len & 0x7) ||
+ (auth_len & 0x7) ||
+ (auth_off & 0x3) || (auth_off + auth_len > iovlen))) {
+ dprintf("%s: Bad parameters od=%p iov=%p iovlen=%jd "
+ "auth_off=%d auth_len=%d crypt_off=%d crypt_len=%d "
+ "icv_off=%d ivp=%p\n", __func__, od, iov, iovlen,
+ auth_off, auth_len, crypt_off, crypt_len, icv_off, ivp);
+ return -EINVAL;
+ }
+
+ IOV_INIT(iov, data32, data_i, data_l);
+
+ CVMX_PREFETCH0(ivp);
+ CVMX_PREFETCH0(od->octo_enckey);
+
+ /* load 3DES Key */
+ CVMX_MT_3DES_KEY(((uint64_t *) od->octo_enckey)[0], 0);
+ if (od->octo_encklen == 24) {
+ CVMX_MT_3DES_KEY(((uint64_t *) od->octo_enckey)[1], 1);
+ CVMX_MT_3DES_KEY(((uint64_t *) od->octo_enckey)[2], 2);
+ } else if (od->octo_encklen == 8) {
+ CVMX_MT_3DES_KEY(((uint64_t *) od->octo_enckey)[0], 1);
+ CVMX_MT_3DES_KEY(((uint64_t *) od->octo_enckey)[0], 2);
+ } else {
+ dprintf("%s: Bad key length %d\n", __func__, od->octo_encklen);
+ return -EINVAL;
+ }
+
+ CVMX_MT_3DES_IV(* (uint64_t *) ivp);
+
+ /* Load MD5 IV */
+ CVMX_MT_HSH_IV(od->octo_hminner[0], 0);
+ CVMX_MT_HSH_IV(od->octo_hminner[1], 1);
+
+ while (crypt_off > 0 && auth_off > 0) {
+ IOV_CONSUME(iov, data32, data_i, data_l);
+ crypt_off -= 4;
+ auth_off -= 4;
+ }
+
+ while (crypt_len > 0 || auth_len > 0) {
+ uint32_t *first = data32;
+ mydata.data32[0] = *first;
+ IOV_CONSUME(iov, data32, data_i, data_l);
+ mydata.data32[1] = *data32;
+ if (crypt_off <= 0) {
+ if (crypt_len > 0) {
+ CVMX_MT_3DES_ENC_CBC(*data);
+ CVMX_MF_3DES_RESULT(*data);
+ crypt_len -= 8;
+ }
+ } else
+ crypt_off -= 8;
+ if (auth_off <= 0) {
+ if (auth_len > 0) {
+ CVM_LOAD_MD5_UNIT(*data, next);
+ auth_len -= 8;
+ }
+ } else
+ auth_off -= 8;
+ *first = mydata.data32[0];
+ *data32 = mydata.data32[1];
+ IOV_CONSUME(iov, data32, data_i, data_l);
+ }
+
+ /* finish the hash */
+ CVMX_PREFETCH0(od->octo_hmouter);
+#if 0
+ if (__predict_false(inplen)) {
+ uint64_t tmp = 0;
+ uint8_t *p = (uint8_t *) & tmp;
+ p[inplen] = 0x80;
+ do {
+ inplen--;
+ p[inplen] = ((uint8_t *) data)[inplen];
+ } while (inplen);
+ CVM_LOAD_MD5_UNIT(tmp, next);
+ } else {
+ CVM_LOAD_MD5_UNIT(0x8000000000000000ULL, next);
+ }
+#else
+ CVM_LOAD_MD5_UNIT(0x8000000000000000ULL, next);
+#endif
+
+ /* Finish Inner hash */
+ while (next != 7) {
+ CVM_LOAD_MD5_UNIT(((uint64_t) 0x0ULL), next);
+ }
+ CVMX_ES64(tmp1, ((alen + 64) << 3));
+ CVM_LOAD_MD5_UNIT(tmp1, next);
+
+ /* Get the inner hash of HMAC */
+ CVMX_MF_HSH_IV(tmp1, 0);
+ CVMX_MF_HSH_IV(tmp2, 1);
+
+ /* Initialize hash unit */
+ CVMX_MT_HSH_IV(od->octo_hmouter[0], 0);
+ CVMX_MT_HSH_IV(od->octo_hmouter[1], 1);
+
+ CVMX_MT_HSH_DAT(tmp1, 0);
+ CVMX_MT_HSH_DAT(tmp2, 1);
+ CVMX_MT_HSH_DAT(0x8000000000000000ULL, 2);
+ CVMX_MT_HSH_DATZ(3);
+ CVMX_MT_HSH_DATZ(4);
+ CVMX_MT_HSH_DATZ(5);
+ CVMX_MT_HSH_DATZ(6);
+ CVMX_ES64(tmp1, ((64 + 16) << 3));
+ CVMX_MT_HSH_STARTMD5(tmp1);
+
+ /* save the HMAC */
+ IOV_INIT(iov, data32, data_i, data_l);
+ while (icv_off > 0) {
+ IOV_CONSUME(iov, data32, data_i, data_l);
+ icv_off -= 4;
+ }
+ CVMX_MF_HSH_IV(tmp1, 0);
+ *data32 = (uint32_t) (tmp1 >> 32);
+ IOV_CONSUME(iov, data32, data_i, data_l);
+ *data32 = (uint32_t) tmp1;
+ IOV_CONSUME(iov, data32, data_i, data_l);
+ CVMX_MF_HSH_IV(tmp1, 1);
+ *data32 = (uint32_t) (tmp1 >> 32);
+
+ return 0;
+}
+
+int
+octo_des_cbc_md5_decrypt(
+ struct octo_sess *od,
+ struct iovec *iov, size_t iovcnt, size_t iovlen,
+ int auth_off, int auth_len,
+ int crypt_off, int crypt_len,
+ int icv_off, uint8_t *ivp)
+{
+ register int next = 0;
+ union {
+ uint32_t data32[2];
+ uint64_t data64[1];
+ } mydata;
+ uint64_t *data = &mydata.data64[0];
+ uint32_t *data32;
+ uint64_t tmp1, tmp2;
+ int data_i, data_l, alen = auth_len;
+
+ dprintf("%s()\n", __func__);
+
+ if (__predict_false(od == NULL || iov==NULL || iovlen==0 || ivp==NULL ||
+ (crypt_off & 0x3) || (crypt_off + crypt_len > iovlen) ||
+ (crypt_len & 0x7) ||
+ (auth_len & 0x7) ||
+ (auth_off & 0x3) || (auth_off + auth_len > iovlen))) {
+ dprintf("%s: Bad parameters od=%p iov=%p iovlen=%jd "
+ "auth_off=%d auth_len=%d crypt_off=%d crypt_len=%d "
+ "icv_off=%d ivp=%p\n", __func__, od, iov, iovlen,
+ auth_off, auth_len, crypt_off, crypt_len, icv_off, ivp);
+ return -EINVAL;
+ }
+
+ IOV_INIT(iov, data32, data_i, data_l);
+
+ CVMX_PREFETCH0(ivp);
+ CVMX_PREFETCH0(od->octo_enckey);
+
+ /* load 3DES Key */
+ CVMX_MT_3DES_KEY(((uint64_t *) od->octo_enckey)[0], 0);
+ if (od->octo_encklen == 24) {
+ CVMX_MT_3DES_KEY(((uint64_t *) od->octo_enckey)[1], 1);
+ CVMX_MT_3DES_KEY(((uint64_t *) od->octo_enckey)[2], 2);
+ } else if (od->octo_encklen == 8) {
+ CVMX_MT_3DES_KEY(((uint64_t *) od->octo_enckey)[0], 1);
+ CVMX_MT_3DES_KEY(((uint64_t *) od->octo_enckey)[0], 2);
+ } else {
+ dprintf("%s: Bad key length %d\n", __func__, od->octo_encklen);
+ return -EINVAL;
+ }
+
+ CVMX_MT_3DES_IV(* (uint64_t *) ivp);
+
+ /* Load MD5 IV */
+ CVMX_MT_HSH_IV(od->octo_hminner[0], 0);
+ CVMX_MT_HSH_IV(od->octo_hminner[1], 1);
+
+ while (crypt_off > 0 && auth_off > 0) {
+ IOV_CONSUME(iov, data32, data_i, data_l);
+ crypt_off -= 4;
+ auth_off -= 4;
+ }
+
+ while (crypt_len > 0 || auth_len > 0) {
+ uint32_t *first = data32;
+ mydata.data32[0] = *first;
+ IOV_CONSUME(iov, data32, data_i, data_l);
+ mydata.data32[1] = *data32;
+ if (auth_off <= 0) {
+ if (auth_len > 0) {
+ CVM_LOAD_MD5_UNIT(*data, next);
+ auth_len -= 8;
+ }
+ } else
+ auth_off -= 8;
+ if (crypt_off <= 0) {
+ if (crypt_len > 0) {
+ CVMX_MT_3DES_DEC_CBC(*data);
+ CVMX_MF_3DES_RESULT(*data);
+ crypt_len -= 8;
+ }
+ } else
+ crypt_off -= 8;
+ *first = mydata.data32[0];
+ *data32 = mydata.data32[1];
+ IOV_CONSUME(iov, data32, data_i, data_l);
+ }
+
+ /* finish the hash */
+ CVMX_PREFETCH0(od->octo_hmouter);
+#if 0
+ if (__predict_false(inplen)) {
+ uint64_t tmp = 0;
+ uint8_t *p = (uint8_t *) & tmp;
+ p[inplen] = 0x80;
+ do {
+ inplen--;
+ p[inplen] = ((uint8_t *) data)[inplen];
+ } while (inplen);
+ CVM_LOAD_MD5_UNIT(tmp, next);
+ } else {
+ CVM_LOAD_MD5_UNIT(0x8000000000000000ULL, next);
+ }
+#else
+ CVM_LOAD_MD5_UNIT(0x8000000000000000ULL, next);
+#endif
+
+ /* Finish Inner hash */
+ while (next != 7) {
+ CVM_LOAD_MD5_UNIT(((uint64_t) 0x0ULL), next);
+ }
+ CVMX_ES64(tmp1, ((alen + 64) << 3));
+ CVM_LOAD_MD5_UNIT(tmp1, next);
+
+ /* Get the inner hash of HMAC */
+ CVMX_MF_HSH_IV(tmp1, 0);
+ CVMX_MF_HSH_IV(tmp2, 1);
+
+ /* Initialize hash unit */
+ CVMX_MT_HSH_IV(od->octo_hmouter[0], 0);
+ CVMX_MT_HSH_IV(od->octo_hmouter[1], 1);
+
+ CVMX_MT_HSH_DAT(tmp1, 0);
+ CVMX_MT_HSH_DAT(tmp2, 1);
+ CVMX_MT_HSH_DAT(0x8000000000000000ULL, 2);
+ CVMX_MT_HSH_DATZ(3);
+ CVMX_MT_HSH_DATZ(4);
+ CVMX_MT_HSH_DATZ(5);
+ CVMX_MT_HSH_DATZ(6);
+ CVMX_ES64(tmp1, ((64 + 16) << 3));
+ CVMX_MT_HSH_STARTMD5(tmp1);
+
+ /* save the HMAC */
+ IOV_INIT(iov, data32, data_i, data_l);
+ while (icv_off > 0) {
+ IOV_CONSUME(iov, data32, data_i, data_l);
+ icv_off -= 4;
+ }
+ CVMX_MF_HSH_IV(tmp1, 0);
+ *data32 = (uint32_t) (tmp1 >> 32);
+ IOV_CONSUME(iov, data32, data_i, data_l);
+ *data32 = (uint32_t) tmp1;
+ IOV_CONSUME(iov, data32, data_i, data_l);
+ CVMX_MF_HSH_IV(tmp1, 1);
+ *data32 = (uint32_t) (tmp1 >> 32);
+
+ return 0;
+}
+
+/****************************************************************************/
+/* DES SHA */
+
+int
+octo_des_cbc_sha1_encrypt(
+ struct octo_sess *od,
+ struct iovec *iov, size_t iovcnt, size_t iovlen,
+ int auth_off, int auth_len,
+ int crypt_off, int crypt_len,
+ int icv_off, uint8_t *ivp)
+{
+ register int next = 0;
+ union {
+ uint32_t data32[2];
+ uint64_t data64[1];
+ } mydata;
+ uint64_t *data = &mydata.data64[0];
+ uint32_t *data32;
+ uint64_t tmp1, tmp2, tmp3;
+ int data_i, data_l, alen = auth_len;
+
+ dprintf("%s()\n", __func__);
+
+ if (__predict_false(od == NULL || iov==NULL || iovlen==0 || ivp==NULL ||
+ (crypt_off & 0x3) || (crypt_off + crypt_len > iovlen) ||
+ (crypt_len & 0x7) ||
+ (auth_len & 0x7) ||
+ (auth_off & 0x3) || (auth_off + auth_len > iovlen))) {
+ dprintf("%s: Bad parameters od=%p iov=%p iovlen=%jd "
+ "auth_off=%d auth_len=%d crypt_off=%d crypt_len=%d "
+ "icv_off=%d ivp=%p\n", __func__, od, iov, iovlen,
+ auth_off, auth_len, crypt_off, crypt_len, icv_off, ivp);
+ return -EINVAL;
+ }
+
+ IOV_INIT(iov, data32, data_i, data_l);
+
+ CVMX_PREFETCH0(ivp);
+ CVMX_PREFETCH0(od->octo_enckey);
+
+ /* load 3DES Key */
+ CVMX_MT_3DES_KEY(((uint64_t *) od->octo_enckey)[0], 0);
+ if (od->octo_encklen == 24) {
+ CVMX_MT_3DES_KEY(((uint64_t *) od->octo_enckey)[1], 1);
+ CVMX_MT_3DES_KEY(((uint64_t *) od->octo_enckey)[2], 2);
+ } else if (od->octo_encklen == 8) {
+ CVMX_MT_3DES_KEY(((uint64_t *) od->octo_enckey)[0], 1);
+ CVMX_MT_3DES_KEY(((uint64_t *) od->octo_enckey)[0], 2);
+ } else {
+ dprintf("%s: Bad key length %d\n", __func__, od->octo_encklen);
+ return -EINVAL;
+ }
+
+ CVMX_MT_3DES_IV(* (uint64_t *) ivp);
+
+ /* Load SHA1 IV */
+ CVMX_MT_HSH_IV(od->octo_hminner[0], 0);
+ CVMX_MT_HSH_IV(od->octo_hminner[1], 1);
+ CVMX_MT_HSH_IV(od->octo_hminner[2], 2);
+
+ while (crypt_off > 0 && auth_off > 0) {
+ IOV_CONSUME(iov, data32, data_i, data_l);
+ crypt_off -= 4;
+ auth_off -= 4;
+ }
+
+ while (crypt_len > 0 || auth_len > 0) {
+ uint32_t *first = data32;
+ mydata.data32[0] = *first;
+ IOV_CONSUME(iov, data32, data_i, data_l);
+ mydata.data32[1] = *data32;
+ if (crypt_off <= 0) {
+ if (crypt_len > 0) {
+ CVMX_MT_3DES_ENC_CBC(*data);
+ CVMX_MF_3DES_RESULT(*data);
+ crypt_len -= 8;
+ }
+ } else
+ crypt_off -= 8;
+ if (auth_off <= 0) {
+ if (auth_len > 0) {
+ CVM_LOAD_SHA_UNIT(*data, next);
+ auth_len -= 8;
+ }
+ } else
+ auth_off -= 8;
+ *first = mydata.data32[0];
+ *data32 = mydata.data32[1];
+ IOV_CONSUME(iov, data32, data_i, data_l);
+ }
+
+ /* finish the hash */
+ CVMX_PREFETCH0(od->octo_hmouter);
+#if 0
+ if (__predict_false(inplen)) {
+ uint64_t tmp = 0;
+ uint8_t *p = (uint8_t *) & tmp;
+ p[inplen] = 0x80;
+ do {
+ inplen--;
+ p[inplen] = ((uint8_t *) data)[inplen];
+ } while (inplen);
+ CVM_LOAD_SHA_UNIT(tmp, next);
+ } else {
+ CVM_LOAD_SHA_UNIT(0x8000000000000000ULL, next);
+ }
+#else
+ CVM_LOAD_SHA_UNIT(0x8000000000000000ULL, next);
+#endif
+
+ /* Finish Inner hash */
+ while (next != 7) {
+ CVM_LOAD_SHA_UNIT(((uint64_t) 0x0ULL), next);
+ }
+ CVM_LOAD_SHA_UNIT((uint64_t) ((alen + 64) << 3), next);
+
+ /* Get the inner hash of HMAC */
+ CVMX_MF_HSH_IV(tmp1, 0);
+ CVMX_MF_HSH_IV(tmp2, 1);
+ tmp3 = 0;
+ CVMX_MF_HSH_IV(tmp3, 2);
+
+ /* Initialize hash unit */
+ CVMX_MT_HSH_IV(od->octo_hmouter[0], 0);
+ CVMX_MT_HSH_IV(od->octo_hmouter[1], 1);
+ CVMX_MT_HSH_IV(od->octo_hmouter[2], 2);
+
+ CVMX_MT_HSH_DAT(tmp1, 0);
+ CVMX_MT_HSH_DAT(tmp2, 1);
+ tmp3 |= 0x0000000080000000;
+ CVMX_MT_HSH_DAT(tmp3, 2);
+ CVMX_MT_HSH_DATZ(3);
+ CVMX_MT_HSH_DATZ(4);
+ CVMX_MT_HSH_DATZ(5);
+ CVMX_MT_HSH_DATZ(6);
+ CVMX_MT_HSH_STARTSHA((uint64_t) ((64 + 20) << 3));
+
+ /* save the HMAC */
+ IOV_INIT(iov, data32, data_i, data_l);
+ while (icv_off > 0) {
+ IOV_CONSUME(iov, data32, data_i, data_l);
+ icv_off -= 4;
+ }
+ CVMX_MF_HSH_IV(tmp1, 0);
+ *data32 = (uint32_t) (tmp1 >> 32);
+ IOV_CONSUME(iov, data32, data_i, data_l);
+ *data32 = (uint32_t) tmp1;
+ IOV_CONSUME(iov, data32, data_i, data_l);
+ CVMX_MF_HSH_IV(tmp1, 1);
+ *data32 = (uint32_t) (tmp1 >> 32);
+
+ return 0;
+}
+
+int
+octo_des_cbc_sha1_decrypt(
+ struct octo_sess *od,
+ struct iovec *iov, size_t iovcnt, size_t iovlen,
+ int auth_off, int auth_len,
+ int crypt_off, int crypt_len,
+ int icv_off, uint8_t *ivp)
+{
+ register int next = 0;
+ union {
+ uint32_t data32[2];
+ uint64_t data64[1];
+ } mydata;
+ uint64_t *data = &mydata.data64[0];
+ uint32_t *data32;
+ uint64_t tmp1, tmp2, tmp3;
+ int data_i, data_l, alen = auth_len;
+
+ dprintf("%s()\n", __func__);
+
+ if (__predict_false(od == NULL || iov==NULL || iovlen==0 || ivp==NULL ||
+ (crypt_off & 0x3) || (crypt_off + crypt_len > iovlen) ||
+ (crypt_len & 0x7) ||
+ (auth_len & 0x7) ||
+ (auth_off & 0x3) || (auth_off + auth_len > iovlen))) {
+ dprintf("%s: Bad parameters od=%p iov=%p iovlen=%jd "
+ "auth_off=%d auth_len=%d crypt_off=%d crypt_len=%d "
+ "icv_off=%d ivp=%p\n", __func__, od, iov, iovlen,
+ auth_off, auth_len, crypt_off, crypt_len, icv_off, ivp);
+ return -EINVAL;
+ }
+
+ IOV_INIT(iov, data32, data_i, data_l);
+
+ CVMX_PREFETCH0(ivp);
+ CVMX_PREFETCH0(od->octo_enckey);
+
+ /* load 3DES Key */
+ CVMX_MT_3DES_KEY(((uint64_t *) od->octo_enckey)[0], 0);
+ if (od->octo_encklen == 24) {
+ CVMX_MT_3DES_KEY(((uint64_t *) od->octo_enckey)[1], 1);
+ CVMX_MT_3DES_KEY(((uint64_t *) od->octo_enckey)[2], 2);
+ } else if (od->octo_encklen == 8) {
+ CVMX_MT_3DES_KEY(((uint64_t *) od->octo_enckey)[0], 1);
+ CVMX_MT_3DES_KEY(((uint64_t *) od->octo_enckey)[0], 2);
+ } else {
+ dprintf("%s: Bad key length %d\n", __func__, od->octo_encklen);
+ return -EINVAL;
+ }
+
+ CVMX_MT_3DES_IV(* (uint64_t *) ivp);
+
+ /* Load SHA1 IV */
+ CVMX_MT_HSH_IV(od->octo_hminner[0], 0);
+ CVMX_MT_HSH_IV(od->octo_hminner[1], 1);
+ CVMX_MT_HSH_IV(od->octo_hminner[2], 2);
+
+ while (crypt_off > 0 && auth_off > 0) {
+ IOV_CONSUME(iov, data32, data_i, data_l);
+ crypt_off -= 4;
+ auth_off -= 4;
+ }
+
+ while (crypt_len > 0 || auth_len > 0) {
+ uint32_t *first = data32;
+ mydata.data32[0] = *first;
+ IOV_CONSUME(iov, data32, data_i, data_l);
+ mydata.data32[1] = *data32;
+ if (auth_off <= 0) {
+ if (auth_len > 0) {
+ CVM_LOAD_SHA_UNIT(*data, next);
+ auth_len -= 8;
+ }
+ } else
+ auth_off -= 8;
+ if (crypt_off <= 0) {
+ if (crypt_len > 0) {
+ CVMX_MT_3DES_DEC_CBC(*data);
+ CVMX_MF_3DES_RESULT(*data);
+ crypt_len -= 8;
+ }
+ } else
+ crypt_off -= 8;
+ *first = mydata.data32[0];
+ *data32 = mydata.data32[1];
+ IOV_CONSUME(iov, data32, data_i, data_l);
+ }
+
+ /* finish the hash */
+ CVMX_PREFETCH0(od->octo_hmouter);
+#if 0
+ if (__predict_false(inplen)) {
+ uint64_t tmp = 0;
+ uint8_t *p = (uint8_t *) & tmp;
+ p[inplen] = 0x80;
+ do {
+ inplen--;
+ p[inplen] = ((uint8_t *) data)[inplen];
+ } while (inplen);
+ CVM_LOAD_SHA_UNIT(tmp, next);
+ } else {
+ CVM_LOAD_SHA_UNIT(0x8000000000000000ULL, next);
+ }
+#else
+ CVM_LOAD_SHA_UNIT(0x8000000000000000ULL, next);
+#endif
+
+ /* Finish Inner hash */
+ while (next != 7) {
+ CVM_LOAD_SHA_UNIT(((uint64_t) 0x0ULL), next);
+ }
+ CVM_LOAD_SHA_UNIT((uint64_t) ((alen + 64) << 3), next);
+
+ /* Get the inner hash of HMAC */
+ CVMX_MF_HSH_IV(tmp1, 0);
+ CVMX_MF_HSH_IV(tmp2, 1);
+ tmp3 = 0;
+ CVMX_MF_HSH_IV(tmp3, 2);
+
+ /* Initialize hash unit */
+ CVMX_MT_HSH_IV(od->octo_hmouter[0], 0);
+ CVMX_MT_HSH_IV(od->octo_hmouter[1], 1);
+ CVMX_MT_HSH_IV(od->octo_hmouter[2], 2);
+
+ CVMX_MT_HSH_DAT(tmp1, 0);
+ CVMX_MT_HSH_DAT(tmp2, 1);
+ tmp3 |= 0x0000000080000000;
+ CVMX_MT_HSH_DAT(tmp3, 2);
+ CVMX_MT_HSH_DATZ(3);
+ CVMX_MT_HSH_DATZ(4);
+ CVMX_MT_HSH_DATZ(5);
+ CVMX_MT_HSH_DATZ(6);
+ CVMX_MT_HSH_STARTSHA((uint64_t) ((64 + 20) << 3));
+ /* save the HMAC */
+ IOV_INIT(iov, data32, data_i, data_l);
+ while (icv_off > 0) {
+ IOV_CONSUME(iov, data32, data_i, data_l);
+ icv_off -= 4;
+ }
+ CVMX_MF_HSH_IV(tmp1, 0);
+ *data32 = (uint32_t) (tmp1 >> 32);
+ IOV_CONSUME(iov, data32, data_i, data_l);
+ *data32 = (uint32_t) tmp1;
+ IOV_CONSUME(iov, data32, data_i, data_l);
+ CVMX_MF_HSH_IV(tmp1, 1);
+ *data32 = (uint32_t) (tmp1 >> 32);
+
+ return 0;
+}
+
+/****************************************************************************/
+/* AES MD5 */
+
+int
+octo_aes_cbc_md5_encrypt(
+ struct octo_sess *od,
+ struct iovec *iov, size_t iovcnt, size_t iovlen,
+ int auth_off, int auth_len,
+ int crypt_off, int crypt_len,
+ int icv_off, uint8_t *ivp)
+{
+ register int next = 0;
+ union {
+ uint32_t data32[2];
+ uint64_t data64[1];
+ } mydata[2];
+ uint64_t *pdata = &mydata[0].data64[0];
+ uint64_t *data = &mydata[1].data64[0];
+ uint32_t *data32;
+ uint64_t tmp1, tmp2;
+ int data_i, data_l, alen = auth_len;
+
+ dprintf("%s()\n", __func__);
+
+ if (__predict_false(od == NULL || iov==NULL || iovlen==0 || ivp==NULL ||
+ (crypt_off & 0x3) || (crypt_off + crypt_len > iovlen) ||
+ (crypt_len & 0x7) ||
+ (auth_len & 0x7) ||
+ (auth_off & 0x3) || (auth_off + auth_len > iovlen))) {
+ dprintf("%s: Bad parameters od=%p iov=%p iovlen=%jd "
+ "auth_off=%d auth_len=%d crypt_off=%d crypt_len=%d "
+ "icv_off=%d ivp=%p\n", __func__, od, iov, iovlen,
+ auth_off, auth_len, crypt_off, crypt_len, icv_off, ivp);
+ return -EINVAL;
+ }
+
+ IOV_INIT(iov, data32, data_i, data_l);
+
+ CVMX_PREFETCH0(ivp);
+ CVMX_PREFETCH0(od->octo_enckey);
+
+ /* load AES Key */
+ CVMX_MT_AES_KEY(((uint64_t *) od->octo_enckey)[0], 0);
+ CVMX_MT_AES_KEY(((uint64_t *) od->octo_enckey)[1], 1);
+
+ if (od->octo_encklen == 16) {
+ CVMX_MT_AES_KEY(0x0, 2);
+ CVMX_MT_AES_KEY(0x0, 3);
+ } else if (od->octo_encklen == 24) {
+ CVMX_MT_AES_KEY(((uint64_t *) od->octo_enckey)[2], 2);
+ CVMX_MT_AES_KEY(0x0, 3);
+ } else if (od->octo_encklen == 32) {
+ CVMX_MT_AES_KEY(((uint64_t *) od->octo_enckey)[2], 2);
+ CVMX_MT_AES_KEY(((uint64_t *) od->octo_enckey)[3], 3);
+ } else {
+ dprintf("%s: Bad key length %d\n", __func__, od->octo_encklen);
+ return -EINVAL;
+ }
+ CVMX_MT_AES_KEYLENGTH(od->octo_encklen / 8 - 1);
+
+ CVMX_MT_AES_IV(((uint64_t *) ivp)[0], 0);
+ CVMX_MT_AES_IV(((uint64_t *) ivp)[1], 1);
+
+ /* Load MD5 IV */
+ CVMX_MT_HSH_IV(od->octo_hminner[0], 0);
+ CVMX_MT_HSH_IV(od->octo_hminner[1], 1);
+
+ while (crypt_off > 0 && auth_off > 0) {
+ IOV_CONSUME(iov, data32, data_i, data_l);
+ crypt_off -= 4;
+ auth_off -= 4;
+ }
+
+ while (crypt_len > 0 || auth_len > 0) {
+ uint32_t *pdata32[3];
+
+ pdata32[0] = data32;
+ mydata[0].data32[0] = *data32;
+ IOV_CONSUME(iov, data32, data_i, data_l);
+
+ pdata32[1] = data32;
+ mydata[0].data32[1] = *data32;
+ IOV_CONSUME(iov, data32, data_i, data_l);
+
+ pdata32[2] = data32;
+ mydata[1].data32[0] = *data32;
+ IOV_CONSUME(iov, data32, data_i, data_l);
+
+ mydata[1].data32[1] = *data32;
+
+
+ if (crypt_off <= 0) {
+ if (crypt_len > 0) {
+ CVMX_MT_AES_ENC_CBC0(*pdata);
+ CVMX_MT_AES_ENC_CBC1(*data);
+ CVMX_MF_AES_RESULT(*pdata, 0);
+ CVMX_MF_AES_RESULT(*data, 1);
+ crypt_len -= 16;
+ }
+ } else
+ crypt_off -= 16;
+
+ if (auth_off <= 0) {
+ if (auth_len > 0) {
+ CVM_LOAD_MD5_UNIT(*pdata, next);
+ CVM_LOAD_MD5_UNIT(*data, next);
+ auth_len -= 16;
+ }
+ } else
+ auth_off -= 16;
+
+ *pdata32[0] = mydata[0].data32[0];
+ *pdata32[1] = mydata[0].data32[1];
+ *pdata32[2] = mydata[1].data32[0];
+ *data32 = mydata[1].data32[1];
+
+ IOV_CONSUME(iov, data32, data_i, data_l);
+ }
+
+ /* finish the hash */
+ CVMX_PREFETCH0(od->octo_hmouter);
+#if 0
+ if (__predict_false(inplen)) {
+ uint64_t tmp = 0;
+ uint8_t *p = (uint8_t *) & tmp;
+ p[inplen] = 0x80;
+ do {
+ inplen--;
+ p[inplen] = ((uint8_t *) data)[inplen];
+ } while (inplen);
+ CVM_LOAD_MD5_UNIT(tmp, next);
+ } else {
+ CVM_LOAD_MD5_UNIT(0x8000000000000000ULL, next);
+ }
+#else
+ CVM_LOAD_MD5_UNIT(0x8000000000000000ULL, next);
+#endif
+
+ /* Finish Inner hash */
+ while (next != 7) {
+ CVM_LOAD_MD5_UNIT(((uint64_t) 0x0ULL), next);
+ }
+ CVMX_ES64(tmp1, ((alen + 64) << 3));
+ CVM_LOAD_MD5_UNIT(tmp1, next);
+
+ /* Get the inner hash of HMAC */
+ CVMX_MF_HSH_IV(tmp1, 0);
+ CVMX_MF_HSH_IV(tmp2, 1);
+
+ /* Initialize hash unit */
+ CVMX_MT_HSH_IV(od->octo_hmouter[0], 0);
+ CVMX_MT_HSH_IV(od->octo_hmouter[1], 1);
+
+ CVMX_MT_HSH_DAT(tmp1, 0);
+ CVMX_MT_HSH_DAT(tmp2, 1);
+ CVMX_MT_HSH_DAT(0x8000000000000000ULL, 2);
+ CVMX_MT_HSH_DATZ(3);
+ CVMX_MT_HSH_DATZ(4);
+ CVMX_MT_HSH_DATZ(5);
+ CVMX_MT_HSH_DATZ(6);
+ CVMX_ES64(tmp1, ((64 + 16) << 3));
+ CVMX_MT_HSH_STARTMD5(tmp1);
+
+ /* save the HMAC */
+ IOV_INIT(iov, data32, data_i, data_l);
+ while (icv_off > 0) {
+ IOV_CONSUME(iov, data32, data_i, data_l);
+ icv_off -= 4;
+ }
+ CVMX_MF_HSH_IV(tmp1, 0);
+ *data32 = (uint32_t) (tmp1 >> 32);
+ IOV_CONSUME(iov, data32, data_i, data_l);
+ *data32 = (uint32_t) tmp1;
+ IOV_CONSUME(iov, data32, data_i, data_l);
+ CVMX_MF_HSH_IV(tmp1, 1);
+ *data32 = (uint32_t) (tmp1 >> 32);
+
+ return 0;
+}
+
+int
+octo_aes_cbc_md5_decrypt(
+ struct octo_sess *od,
+ struct iovec *iov, size_t iovcnt, size_t iovlen,
+ int auth_off, int auth_len,
+ int crypt_off, int crypt_len,
+ int icv_off, uint8_t *ivp)
+{
+ register int next = 0;
+ union {
+ uint32_t data32[2];
+ uint64_t data64[1];
+ } mydata[2];
+ uint64_t *pdata = &mydata[0].data64[0];
+ uint64_t *data = &mydata[1].data64[0];
+ uint32_t *data32;
+ uint64_t tmp1, tmp2;
+ int data_i, data_l, alen = auth_len;
+
+ dprintf("%s()\n", __func__);
+
+ if (__predict_false(od == NULL || iov==NULL || iovlen==0 || ivp==NULL ||
+ (crypt_off & 0x3) || (crypt_off + crypt_len > iovlen) ||
+ (crypt_len & 0x7) ||
+ (auth_len & 0x7) ||
+ (auth_off & 0x3) || (auth_off + auth_len > iovlen))) {
+ dprintf("%s: Bad parameters od=%p iov=%p iovlen=%jd "
+ "auth_off=%d auth_len=%d crypt_off=%d crypt_len=%d "
+ "icv_off=%d ivp=%p\n", __func__, od, iov, iovlen,
+ auth_off, auth_len, crypt_off, crypt_len, icv_off, ivp);
+ return -EINVAL;
+ }
+
+ IOV_INIT(iov, data32, data_i, data_l);
+
+ CVMX_PREFETCH0(ivp);
+ CVMX_PREFETCH0(od->octo_enckey);
+
+ /* load AES Key */
+ CVMX_MT_AES_KEY(((uint64_t *) od->octo_enckey)[0], 0);
+ CVMX_MT_AES_KEY(((uint64_t *) od->octo_enckey)[1], 1);
+
+ if (od->octo_encklen == 16) {
+ CVMX_MT_AES_KEY(0x0, 2);
+ CVMX_MT_AES_KEY(0x0, 3);
+ } else if (od->octo_encklen == 24) {
+ CVMX_MT_AES_KEY(((uint64_t *) od->octo_enckey)[2], 2);
+ CVMX_MT_AES_KEY(0x0, 3);
+ } else if (od->octo_encklen == 32) {
+ CVMX_MT_AES_KEY(((uint64_t *) od->octo_enckey)[2], 2);
+ CVMX_MT_AES_KEY(((uint64_t *) od->octo_enckey)[3], 3);
+ } else {
+ dprintf("%s: Bad key length %d\n", __func__, od->octo_encklen);
+ return -EINVAL;
+ }
+ CVMX_MT_AES_KEYLENGTH(od->octo_encklen / 8 - 1);
+
+ CVMX_MT_AES_IV(((uint64_t *) ivp)[0], 0);
+ CVMX_MT_AES_IV(((uint64_t *) ivp)[1], 1);
+
+ /* Load MD5 IV */
+ CVMX_MT_HSH_IV(od->octo_hminner[0], 0);
+ CVMX_MT_HSH_IV(od->octo_hminner[1], 1);
+
+ while (crypt_off > 0 && auth_off > 0) {
+ IOV_CONSUME(iov, data32, data_i, data_l);
+ crypt_off -= 4;
+ auth_off -= 4;
+ }
+
+ while (crypt_len > 0 || auth_len > 0) {
+ uint32_t *pdata32[3];
+
+ pdata32[0] = data32;
+ mydata[0].data32[0] = *data32;
+ IOV_CONSUME(iov, data32, data_i, data_l);
+ pdata32[1] = data32;
+ mydata[0].data32[1] = *data32;
+ IOV_CONSUME(iov, data32, data_i, data_l);
+ pdata32[2] = data32;
+ mydata[1].data32[0] = *data32;
+ IOV_CONSUME(iov, data32, data_i, data_l);
+ mydata[1].data32[1] = *data32;
+
+ if (auth_off <= 0) {
+ if (auth_len > 0) {
+ CVM_LOAD_MD5_UNIT(*pdata, next);
+ CVM_LOAD_MD5_UNIT(*data, next);
+ auth_len -= 16;
+ }
+ } else
+ auth_off -= 16;
+
+ if (crypt_off <= 0) {
+ if (crypt_len > 0) {
+ CVMX_MT_AES_DEC_CBC0(*pdata);
+ CVMX_MT_AES_DEC_CBC1(*data);
+ CVMX_MF_AES_RESULT(*pdata, 0);
+ CVMX_MF_AES_RESULT(*data, 1);
+ crypt_len -= 16;
+ }
+ } else
+ crypt_off -= 16;
+
+ *pdata32[0] = mydata[0].data32[0];
+ *pdata32[1] = mydata[0].data32[1];
+ *pdata32[2] = mydata[1].data32[0];
+ *data32 = mydata[1].data32[1];
+
+ IOV_CONSUME(iov, data32, data_i, data_l);
+ }
+
+ /* finish the hash */
+ CVMX_PREFETCH0(od->octo_hmouter);
+#if 0
+ if (__predict_false(inplen)) {
+ uint64_t tmp = 0;
+ uint8_t *p = (uint8_t *) & tmp;
+ p[inplen] = 0x80;
+ do {
+ inplen--;
+ p[inplen] = ((uint8_t *) data)[inplen];
+ } while (inplen);
+ CVM_LOAD_MD5_UNIT(tmp, next);
+ } else {
+ CVM_LOAD_MD5_UNIT(0x8000000000000000ULL, next);
+ }
+#else
+ CVM_LOAD_MD5_UNIT(0x8000000000000000ULL, next);
+#endif
+
+ /* Finish Inner hash */
+ while (next != 7) {
+ CVM_LOAD_MD5_UNIT(((uint64_t) 0x0ULL), next);
+ }
+ CVMX_ES64(tmp1, ((alen + 64) << 3));
+ CVM_LOAD_MD5_UNIT(tmp1, next);
+
+ /* Get the inner hash of HMAC */
+ CVMX_MF_HSH_IV(tmp1, 0);
+ CVMX_MF_HSH_IV(tmp2, 1);
+
+ /* Initialize hash unit */
+ CVMX_MT_HSH_IV(od->octo_hmouter[0], 0);
+ CVMX_MT_HSH_IV(od->octo_hmouter[1], 1);
+
+ CVMX_MT_HSH_DAT(tmp1, 0);
+ CVMX_MT_HSH_DAT(tmp2, 1);
+ CVMX_MT_HSH_DAT(0x8000000000000000ULL, 2);
+ CVMX_MT_HSH_DATZ(3);
+ CVMX_MT_HSH_DATZ(4);
+ CVMX_MT_HSH_DATZ(5);
+ CVMX_MT_HSH_DATZ(6);
+ CVMX_ES64(tmp1, ((64 + 16) << 3));
+ CVMX_MT_HSH_STARTMD5(tmp1);
+
+ /* save the HMAC */
+ IOV_INIT(iov, data32, data_i, data_l);
+ while (icv_off > 0) {
+ IOV_CONSUME(iov, data32, data_i, data_l);
+ icv_off -= 4;
+ }
+ CVMX_MF_HSH_IV(tmp1, 0);
+ *data32 = (uint32_t) (tmp1 >> 32);
+ IOV_CONSUME(iov, data32, data_i, data_l);
+ *data32 = (uint32_t) tmp1;
+ IOV_CONSUME(iov, data32, data_i, data_l);
+ CVMX_MF_HSH_IV(tmp1, 1);
+ *data32 = (uint32_t) (tmp1 >> 32);
+
+ return 0;
+}
+
+/****************************************************************************/
+/* AES SHA1 */
+
+int
+octo_aes_cbc_sha1_encrypt(
+ struct octo_sess *od,
+ struct iovec *iov, size_t iovcnt, size_t iovlen,
+ int auth_off, int auth_len,
+ int crypt_off, int crypt_len,
+ int icv_off, uint8_t *ivp)
+{
+ register int next = 0;
+ union {
+ uint32_t data32[2];
+ uint64_t data64[1];
+ } mydata[2];
+ uint64_t *pdata = &mydata[0].data64[0];
+ uint64_t *data = &mydata[1].data64[0];
+ uint32_t *data32;
+ uint64_t tmp1, tmp2, tmp3;
+ int data_i, data_l, alen = auth_len;
+
+ dprintf("%s()\n", __func__);
+
+ if (__predict_false(od == NULL || iov==NULL || iovlen==0 || ivp==NULL ||
+ (crypt_off & 0x3) || (crypt_off + crypt_len > iovlen) ||
+ (crypt_len & 0x7) ||
+ (auth_len & 0x7) ||
+ (auth_off & 0x3) || (auth_off + auth_len > iovlen))) {
+ dprintf("%s: Bad parameters od=%p iov=%p iovlen=%jd "
+ "auth_off=%d auth_len=%d crypt_off=%d crypt_len=%d "
+ "icv_off=%d ivp=%p\n", __func__, od, iov, iovlen,
+ auth_off, auth_len, crypt_off, crypt_len, icv_off, ivp);
+ return -EINVAL;
+ }
+
+ IOV_INIT(iov, data32, data_i, data_l);
+
+ CVMX_PREFETCH0(ivp);
+ CVMX_PREFETCH0(od->octo_enckey);
+
+ /* load AES Key */
+ CVMX_MT_AES_KEY(((uint64_t *) od->octo_enckey)[0], 0);
+ CVMX_MT_AES_KEY(((uint64_t *) od->octo_enckey)[1], 1);
+
+ if (od->octo_encklen == 16) {
+ CVMX_MT_AES_KEY(0x0, 2);
+ CVMX_MT_AES_KEY(0x0, 3);
+ } else if (od->octo_encklen == 24) {
+ CVMX_MT_AES_KEY(((uint64_t *) od->octo_enckey)[2], 2);
+ CVMX_MT_AES_KEY(0x0, 3);
+ } else if (od->octo_encklen == 32) {
+ CVMX_MT_AES_KEY(((uint64_t *) od->octo_enckey)[2], 2);
+ CVMX_MT_AES_KEY(((uint64_t *) od->octo_enckey)[3], 3);
+ } else {
+ dprintf("%s: Bad key length %d\n", __func__, od->octo_encklen);
+ return -EINVAL;
+ }
+ CVMX_MT_AES_KEYLENGTH(od->octo_encklen / 8 - 1);
+
+ CVMX_MT_AES_IV(((uint64_t *) ivp)[0], 0);
+ CVMX_MT_AES_IV(((uint64_t *) ivp)[1], 1);
+
+ /* Load SHA IV */
+ CVMX_MT_HSH_IV(od->octo_hminner[0], 0);
+ CVMX_MT_HSH_IV(od->octo_hminner[1], 1);
+ CVMX_MT_HSH_IV(od->octo_hminner[2], 2);
+
+ while (crypt_off > 0 && auth_off > 0) {
+ IOV_CONSUME(iov, data32, data_i, data_l);
+ crypt_off -= 4;
+ auth_off -= 4;
+ }
+
+ while (crypt_len > 0 || auth_len > 0) {
+ uint32_t *pdata32[3];
+
+ pdata32[0] = data32;
+ mydata[0].data32[0] = *data32;
+ IOV_CONSUME(iov, data32, data_i, data_l);
+ pdata32[1] = data32;
+ mydata[0].data32[1] = *data32;
+ IOV_CONSUME(iov, data32, data_i, data_l);
+ pdata32[2] = data32;
+ mydata[1].data32[0] = *data32;
+ IOV_CONSUME(iov, data32, data_i, data_l);
+ mydata[1].data32[1] = *data32;
+
+
+ if (crypt_off <= 0) {
+ if (crypt_len > 0) {
+ CVMX_MT_AES_ENC_CBC0(*pdata);
+ CVMX_MT_AES_ENC_CBC1(*data);
+ CVMX_MF_AES_RESULT(*pdata, 0);
+ CVMX_MF_AES_RESULT(*data, 1);
+ crypt_len -= 16;
+ }
+ } else
+ crypt_off -= 16;
+
+ if (auth_off <= 0) {
+ if (auth_len > 0) {
+ CVM_LOAD_SHA_UNIT(*pdata, next);
+ CVM_LOAD_SHA_UNIT(*data, next);
+ auth_len -= 16;
+ }
+ } else
+ auth_off -= 16;
+
+ *pdata32[0] = mydata[0].data32[0];
+ *pdata32[1] = mydata[0].data32[1];
+ *pdata32[2] = mydata[1].data32[0];
+ *data32 = mydata[1].data32[1];
+
+ IOV_CONSUME(iov, data32, data_i, data_l);
+ }
+
+ /* finish the hash */
+ CVMX_PREFETCH0(od->octo_hmouter);
+#if 0
+ if (__predict_false(inplen)) {
+ uint64_t tmp = 0;
+ uint8_t *p = (uint8_t *) & tmp;
+ p[inplen] = 0x80;
+ do {
+ inplen--;
+ p[inplen] = ((uint8_t *) data)[inplen];
+ } while (inplen);
+ CVM_LOAD_SHA_UNIT(tmp, next);
+ } else {
+ CVM_LOAD_SHA_UNIT(0x8000000000000000ULL, next);
+ }
+#else
+ CVM_LOAD_SHA_UNIT(0x8000000000000000ULL, next);
+#endif
+
+ /* Finish Inner hash */
+ while (next != 7) {
+ CVM_LOAD_SHA_UNIT(((uint64_t) 0x0ULL), next);
+ }
+ CVM_LOAD_SHA_UNIT((uint64_t) ((alen + 64) << 3), next);
+
+ /* Get the inner hash of HMAC */
+ CVMX_MF_HSH_IV(tmp1, 0);
+ CVMX_MF_HSH_IV(tmp2, 1);
+ tmp3 = 0;
+ CVMX_MF_HSH_IV(tmp3, 2);
+
+ /* Initialize hash unit */
+ CVMX_MT_HSH_IV(od->octo_hmouter[0], 0);
+ CVMX_MT_HSH_IV(od->octo_hmouter[1], 1);
+ CVMX_MT_HSH_IV(od->octo_hmouter[2], 2);
+
+ CVMX_MT_HSH_DAT(tmp1, 0);
+ CVMX_MT_HSH_DAT(tmp2, 1);
+ tmp3 |= 0x0000000080000000;
+ CVMX_MT_HSH_DAT(tmp3, 2);
+ CVMX_MT_HSH_DATZ(3);
+ CVMX_MT_HSH_DATZ(4);
+ CVMX_MT_HSH_DATZ(5);
+ CVMX_MT_HSH_DATZ(6);
+ CVMX_MT_HSH_STARTSHA((uint64_t) ((64 + 20) << 3));
+
+ /* finish the hash */
+ CVMX_PREFETCH0(od->octo_hmouter);
+#if 0
+ if (__predict_false(inplen)) {
+ uint64_t tmp = 0;
+ uint8_t *p = (uint8_t *) & tmp;
+ p[inplen] = 0x80;
+ do {
+ inplen--;
+ p[inplen] = ((uint8_t *) data)[inplen];
+ } while (inplen);
+ CVM_LOAD_MD5_UNIT(tmp, next);
+ } else {
+ CVM_LOAD_MD5_UNIT(0x8000000000000000ULL, next);
+ }
+#else
+ CVM_LOAD_MD5_UNIT(0x8000000000000000ULL, next);
+#endif
+
+ /* save the HMAC */
+ IOV_INIT(iov, data32, data_i, data_l);
+ while (icv_off > 0) {
+ IOV_CONSUME(iov, data32, data_i, data_l);
+ icv_off -= 4;
+ }
+ CVMX_MF_HSH_IV(tmp1, 0);
+ *data32 = (uint32_t) (tmp1 >> 32);
+ IOV_CONSUME(iov, data32, data_i, data_l);
+ *data32 = (uint32_t) tmp1;
+ IOV_CONSUME(iov, data32, data_i, data_l);
+ CVMX_MF_HSH_IV(tmp1, 1);
+ *data32 = (uint32_t) (tmp1 >> 32);
+
+ return 0;
+}
+
+int
+octo_aes_cbc_sha1_decrypt(
+ struct octo_sess *od,
+ struct iovec *iov, size_t iovcnt, size_t iovlen,
+ int auth_off, int auth_len,
+ int crypt_off, int crypt_len,
+ int icv_off, uint8_t *ivp)
+{
+ register int next = 0;
+ union {
+ uint32_t data32[2];
+ uint64_t data64[1];
+ } mydata[2];
+ uint64_t *pdata = &mydata[0].data64[0];
+ uint64_t *data = &mydata[1].data64[0];
+ uint32_t *data32;
+ uint64_t tmp1, tmp2, tmp3;
+ int data_i, data_l, alen = auth_len;
+
+ dprintf("%s()\n", __func__);
+
+ if (__predict_false(od == NULL || iov==NULL || iovlen==0 || ivp==NULL ||
+ (crypt_off & 0x3) || (crypt_off + crypt_len > iovlen) ||
+ (crypt_len & 0x7) ||
+ (auth_len & 0x7) ||
+ (auth_off & 0x3) || (auth_off + auth_len > iovlen))) {
+ dprintf("%s: Bad parameters od=%p iov=%p iovlen=%jd "
+ "auth_off=%d auth_len=%d crypt_off=%d crypt_len=%d "
+ "icv_off=%d ivp=%p\n", __func__, od, iov, iovlen,
+ auth_off, auth_len, crypt_off, crypt_len, icv_off, ivp);
+ return -EINVAL;
+ }
+
+ IOV_INIT(iov, data32, data_i, data_l);
+
+ CVMX_PREFETCH0(ivp);
+ CVMX_PREFETCH0(od->octo_enckey);
+
+ /* load AES Key */
+ CVMX_MT_AES_KEY(((uint64_t *) od->octo_enckey)[0], 0);
+ CVMX_MT_AES_KEY(((uint64_t *) od->octo_enckey)[1], 1);
+
+ if (od->octo_encklen == 16) {
+ CVMX_MT_AES_KEY(0x0, 2);
+ CVMX_MT_AES_KEY(0x0, 3);
+ } else if (od->octo_encklen == 24) {
+ CVMX_MT_AES_KEY(((uint64_t *) od->octo_enckey)[2], 2);
+ CVMX_MT_AES_KEY(0x0, 3);
+ } else if (od->octo_encklen == 32) {
+ CVMX_MT_AES_KEY(((uint64_t *) od->octo_enckey)[2], 2);
+ CVMX_MT_AES_KEY(((uint64_t *) od->octo_enckey)[3], 3);
+ } else {
+ dprintf("%s: Bad key length %d\n", __func__, od->octo_encklen);
+ return -EINVAL;
+ }
+ CVMX_MT_AES_KEYLENGTH(od->octo_encklen / 8 - 1);
+
+ CVMX_MT_AES_IV(((uint64_t *) ivp)[0], 0);
+ CVMX_MT_AES_IV(((uint64_t *) ivp)[1], 1);
+
+ /* Load MD5 IV */
+ CVMX_MT_HSH_IV(od->octo_hminner[0], 0);
+ CVMX_MT_HSH_IV(od->octo_hminner[1], 1);
+ CVMX_MT_HSH_IV(od->octo_hminner[2], 2);
+
+ while (crypt_off > 0 && auth_off > 0) {
+ IOV_CONSUME(iov, data32, data_i, data_l);
+ crypt_off -= 4;
+ auth_off -= 4;
+ }
+
+ while (crypt_len > 0 || auth_len > 0) {
+ uint32_t *pdata32[3];
+
+ pdata32[0] = data32;
+ mydata[0].data32[0] = *data32;
+ IOV_CONSUME(iov, data32, data_i, data_l);
+ pdata32[1] = data32;
+ mydata[0].data32[1] = *data32;
+ IOV_CONSUME(iov, data32, data_i, data_l);
+ pdata32[2] = data32;
+ mydata[1].data32[0] = *data32;
+ IOV_CONSUME(iov, data32, data_i, data_l);
+ mydata[1].data32[1] = *data32;
+
+ if (auth_off <= 0) {
+ if (auth_len > 0) {
+ CVM_LOAD_SHA_UNIT(*pdata, next);
+ CVM_LOAD_SHA_UNIT(*data, next);
+ auth_len -= 16;
+ }
+ } else
+ auth_off -= 16;
+
+ if (crypt_off <= 0) {
+ if (crypt_len > 0) {
+ CVMX_MT_AES_DEC_CBC0(*pdata);
+ CVMX_MT_AES_DEC_CBC1(*data);
+ CVMX_MF_AES_RESULT(*pdata, 0);
+ CVMX_MF_AES_RESULT(*data, 1);
+ crypt_len -= 16;
+ }
+ } else
+ crypt_off -= 16;
+
+ *pdata32[0] = mydata[0].data32[0];
+ *pdata32[1] = mydata[0].data32[1];
+ *pdata32[2] = mydata[1].data32[0];
+ *data32 = mydata[1].data32[1];
+
+ IOV_CONSUME(iov, data32, data_i, data_l);
+ }
+
+ /* finish the hash */
+ CVMX_PREFETCH0(od->octo_hmouter);
+#if 0
+ if (__predict_false(inplen)) {
+ uint64_t tmp = 0;
+ uint8_t *p = (uint8_t *) & tmp;
+ p[inplen] = 0x80;
+ do {
+ inplen--;
+ p[inplen] = ((uint8_t *) data)[inplen];
+ } while (inplen);
+ CVM_LOAD_SHA_UNIT(tmp, next);
+ } else {
+ CVM_LOAD_SHA_UNIT(0x8000000000000000ULL, next);
+ }
+#else
+ CVM_LOAD_SHA_UNIT(0x8000000000000000ULL, next);
+#endif
+
+ /* Finish Inner hash */
+ while (next != 7) {
+ CVM_LOAD_SHA_UNIT(((uint64_t) 0x0ULL), next);
+ }
+ CVM_LOAD_SHA_UNIT((uint64_t) ((alen + 64) << 3), next);
+
+ /* Get the inner hash of HMAC */
+ CVMX_MF_HSH_IV(tmp1, 0);
+ CVMX_MF_HSH_IV(tmp2, 1);
+ tmp3 = 0;
+ CVMX_MF_HSH_IV(tmp3, 2);
+
+ /* Initialize hash unit */
+ CVMX_MT_HSH_IV(od->octo_hmouter[0], 0);
+ CVMX_MT_HSH_IV(od->octo_hmouter[1], 1);
+ CVMX_MT_HSH_IV(od->octo_hmouter[2], 2);
+
+ CVMX_MT_HSH_DAT(tmp1, 0);
+ CVMX_MT_HSH_DAT(tmp2, 1);
+ tmp3 |= 0x0000000080000000;
+ CVMX_MT_HSH_DAT(tmp3, 2);
+ CVMX_MT_HSH_DATZ(3);
+ CVMX_MT_HSH_DATZ(4);
+ CVMX_MT_HSH_DATZ(5);
+ CVMX_MT_HSH_DATZ(6);
+ CVMX_MT_HSH_STARTSHA((uint64_t) ((64 + 20) << 3));
+
+ /* finish the hash */
+ CVMX_PREFETCH0(od->octo_hmouter);
+#if 0
+ if (__predict_false(inplen)) {
+ uint64_t tmp = 0;
+ uint8_t *p = (uint8_t *) & tmp;
+ p[inplen] = 0x80;
+ do {
+ inplen--;
+ p[inplen] = ((uint8_t *) data)[inplen];
+ } while (inplen);
+ CVM_LOAD_MD5_UNIT(tmp, next);
+ } else {
+ CVM_LOAD_MD5_UNIT(0x8000000000000000ULL, next);
+ }
+#else
+ CVM_LOAD_MD5_UNIT(0x8000000000000000ULL, next);
+#endif
+
+ /* save the HMAC */
+ IOV_INIT(iov, data32, data_i, data_l);
+ while (icv_off > 0) {
+ IOV_CONSUME(iov, data32, data_i, data_l);
+ icv_off -= 4;
+ }
+ CVMX_MF_HSH_IV(tmp1, 0);
+ *data32 = (uint32_t) (tmp1 >> 32);
+ IOV_CONSUME(iov, data32, data_i, data_l);
+ *data32 = (uint32_t) tmp1;
+ IOV_CONSUME(iov, data32, data_i, data_l);
+ CVMX_MF_HSH_IV(tmp1, 1);
+ *data32 = (uint32_t) (tmp1 >> 32);
+
+ return 0;
+}
+
+/****************************************************************************/
Property changes on: trunk/sys/mips/cavium/cryptocteon/cavium_crypto.c
___________________________________________________________________
Added: svn:eol-style
## -0,0 +1 ##
+native
\ No newline at end of property
Added: svn:keywords
## -0,0 +1 ##
+MidnightBSD=%H
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+text/plain
\ No newline at end of property
Added: trunk/sys/mips/cavium/cryptocteon/cryptocteon.c
===================================================================
--- trunk/sys/mips/cavium/cryptocteon/cryptocteon.c (rev 0)
+++ trunk/sys/mips/cavium/cryptocteon/cryptocteon.c 2018-05-26 21:55:02 UTC (rev 9987)
@@ -0,0 +1,527 @@
+/* $MidnightBSD$ */
+/*
+ * Octeon Crypto for OCF
+ *
+ * Written by David McCullough <david_mccullough at securecomputing.com>
+ * Copyright (C) 2009 David McCullough
+ *
+ * LICENSE TERMS
+ *
+ * The free distribution and use of this software in both source and binary
+ * form is allowed (with or without changes) provided that:
+ *
+ * 1. distributions of this source code include the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ *
+ * 2. distributions in binary form include the above copyright
+ * notice, this list of conditions and the following disclaimer
+ * in the documentation and/or other associated materials;
+ *
+ * 3. the copyright holder's name is not used to endorse products
+ * built using this software without specific written permission.
+ *
+ * DISCLAIMER
+ *
+ * This software is provided 'as is' with no explicit or implied warranties
+ * in respect of its properties, including, but not limited to, correctness
+ * and/or fitness for purpose.
+ * ---------------------------------------------------------------------------
+ */
+
+#include <sys/cdefs.h>
+__FBSDID("$FreeBSD: stable/10/sys/mips/cavium/cryptocteon/cryptocteon.c 210312 2010-07-20 19:32:25Z jmallett $");
+
+#include <sys/param.h>
+#include <sys/systm.h>
+#include <sys/bus.h>
+#include <sys/kernel.h>
+#include <sys/module.h>
+#include <sys/malloc.h>
+#include <sys/mbuf.h>
+#include <sys/uio.h>
+
+#include <opencrypto/cryptodev.h>
+
+#include <contrib/octeon-sdk/cvmx.h>
+
+#include <mips/cavium/cryptocteon/cryptocteonvar.h>
+
+#include "cryptodev_if.h"
+
+struct cryptocteon_softc {
+ int32_t sc_cid; /* opencrypto id */
+ struct octo_sess **sc_sessions;
+ uint32_t sc_sesnum;
+};
+
+int cryptocteon_debug = 0;
+TUNABLE_INT("hw.cryptocteon.debug", &cryptocteon_debug);
+
+static void cryptocteon_identify(driver_t *, device_t);
+static int cryptocteon_probe(device_t);
+static int cryptocteon_attach(device_t);
+
+static int cryptocteon_process(device_t, struct cryptop *, int);
+static int cryptocteon_newsession(device_t, u_int32_t *, struct cryptoini *);
+static int cryptocteon_freesession(device_t, u_int64_t);
+
+static void
+cryptocteon_identify(driver_t *drv, device_t parent)
+{
+ if (octeon_has_feature(OCTEON_FEATURE_CRYPTO))
+ BUS_ADD_CHILD(parent, 0, "cryptocteon", 0);
+}
+
+static int
+cryptocteon_probe(device_t dev)
+{
+ device_set_desc(dev, "Octeon Secure Coprocessor");
+ return (0);
+}
+
+static int
+cryptocteon_attach(device_t dev)
+{
+ struct cryptocteon_softc *sc;
+
+ sc = device_get_softc(dev);
+
+ sc->sc_cid = crypto_get_driverid(dev, CRYPTOCAP_F_HARDWARE | CRYPTOCAP_F_SYNC);
+ if (sc->sc_cid < 0) {
+ device_printf(dev, "crypto_get_driverid ret %d\n", sc->sc_cid);
+ return (ENXIO);
+ }
+
+ crypto_register(sc->sc_cid, CRYPTO_MD5_HMAC, 0, 0);
+ crypto_register(sc->sc_cid, CRYPTO_SHA1_HMAC, 0, 0);
+ crypto_register(sc->sc_cid, CRYPTO_DES_CBC, 0, 0);
+ crypto_register(sc->sc_cid, CRYPTO_3DES_CBC, 0, 0);
+ crypto_register(sc->sc_cid, CRYPTO_AES_CBC, 0, 0);
+
+ return (0);
+}
+
+/*
+ * Generate a new octo session. We artifically limit it to a single
+ * hash/cipher or hash-cipher combo just to make it easier, most callers
+ * do not expect more than this anyway.
+ */
+static int
+cryptocteon_newsession(device_t dev, u_int32_t *sid, struct cryptoini *cri)
+{
+ struct cryptoini *c, *encini = NULL, *macini = NULL;
+ struct cryptocteon_softc *sc;
+ struct octo_sess **ocd;
+ int i;
+
+ sc = device_get_softc(dev);
+
+ if (sid == NULL || cri == NULL || sc == NULL)
+ return (EINVAL);
+
+ /*
+ * To keep it simple, we only handle hash, cipher or hash/cipher in a
+ * session, you cannot currently do multiple ciphers/hashes in one
+ * session even though it would be possibel to code this driver to
+ * handle it.
+ */
+ for (i = 0, c = cri; c && i < 2; i++) {
+ if (c->cri_alg == CRYPTO_MD5_HMAC ||
+ c->cri_alg == CRYPTO_SHA1_HMAC ||
+ c->cri_alg == CRYPTO_NULL_HMAC) {
+ if (macini) {
+ break;
+ }
+ macini = c;
+ }
+ if (c->cri_alg == CRYPTO_DES_CBC ||
+ c->cri_alg == CRYPTO_3DES_CBC ||
+ c->cri_alg == CRYPTO_AES_CBC ||
+ c->cri_alg == CRYPTO_NULL_CBC) {
+ if (encini) {
+ break;
+ }
+ encini = c;
+ }
+ c = c->cri_next;
+ }
+ if (!macini && !encini) {
+ dprintf("%s,%d - EINVAL bad cipher/hash or combination\n",
+ __FILE__, __LINE__);
+ return EINVAL;
+ }
+ if (c) {
+ dprintf("%s,%d - EINVAL cannot handle chained cipher/hash combos\n",
+ __FILE__, __LINE__);
+ return EINVAL;
+ }
+
+ /*
+ * So we have something we can do, lets setup the session
+ */
+
+ if (sc->sc_sessions) {
+ for (i = 1; i < sc->sc_sesnum; i++)
+ if (sc->sc_sessions[i] == NULL)
+ break;
+ } else
+ i = 1; /* NB: to silence compiler warning */
+
+ if (sc->sc_sessions == NULL || i == sc->sc_sesnum) {
+ if (sc->sc_sessions == NULL) {
+ i = 1; /* We leave sc->sc_sessions[0] empty */
+ sc->sc_sesnum = CRYPTO_SW_SESSIONS;
+ } else
+ sc->sc_sesnum *= 2;
+
+ ocd = malloc(sc->sc_sesnum * sizeof(struct octo_sess *),
+ M_DEVBUF, M_NOWAIT | M_ZERO);
+ if (ocd == NULL) {
+ /* Reset session number */
+ if (sc->sc_sesnum == CRYPTO_SW_SESSIONS)
+ sc->sc_sesnum = 0;
+ else
+ sc->sc_sesnum /= 2;
+ dprintf("%s,%d: ENOBUFS\n", __FILE__, __LINE__);
+ return ENOBUFS;
+ }
+
+ /* Copy existing sessions */
+ if (sc->sc_sessions) {
+ memcpy(ocd, sc->sc_sessions,
+ (sc->sc_sesnum / 2) * sizeof(struct octo_sess *));
+ free(sc->sc_sessions, M_DEVBUF);
+ }
+
+ sc->sc_sessions = ocd;
+ }
+
+ ocd = &sc->sc_sessions[i];
+ *sid = i;
+
+ *ocd = malloc(sizeof(struct octo_sess), M_DEVBUF, M_NOWAIT | M_ZERO);
+ if (*ocd == NULL) {
+ cryptocteon_freesession(NULL, i);
+ dprintf("%s,%d: ENOBUFS\n", __FILE__, __LINE__);
+ return ENOBUFS;
+ }
+
+ if (encini && encini->cri_key) {
+ (*ocd)->octo_encklen = (encini->cri_klen + 7) / 8;
+ memcpy((*ocd)->octo_enckey, encini->cri_key, (*ocd)->octo_encklen);
+ }
+
+ if (macini && macini->cri_key) {
+ (*ocd)->octo_macklen = (macini->cri_klen + 7) / 8;
+ memcpy((*ocd)->octo_mackey, macini->cri_key, (*ocd)->octo_macklen);
+ }
+
+ (*ocd)->octo_mlen = 0;
+ if (encini && encini->cri_mlen)
+ (*ocd)->octo_mlen = encini->cri_mlen;
+ else if (macini && macini->cri_mlen)
+ (*ocd)->octo_mlen = macini->cri_mlen;
+ else
+ (*ocd)->octo_mlen = 12;
+
+ /*
+ * point c at the enc if it exists, otherwise the mac
+ */
+ c = encini ? encini : macini;
+
+ switch (c->cri_alg) {
+ case CRYPTO_DES_CBC:
+ case CRYPTO_3DES_CBC:
+ (*ocd)->octo_ivsize = 8;
+ switch (macini ? macini->cri_alg : -1) {
+ case CRYPTO_MD5_HMAC:
+ (*ocd)->octo_encrypt = octo_des_cbc_md5_encrypt;
+ (*ocd)->octo_decrypt = octo_des_cbc_md5_decrypt;
+ octo_calc_hash(0, macini->cri_key, (*ocd)->octo_hminner,
+ (*ocd)->octo_hmouter);
+ break;
+ case CRYPTO_SHA1_HMAC:
+ (*ocd)->octo_encrypt = octo_des_cbc_sha1_encrypt;
+ (*ocd)->octo_decrypt = octo_des_cbc_sha1_encrypt;
+ octo_calc_hash(1, macini->cri_key, (*ocd)->octo_hminner,
+ (*ocd)->octo_hmouter);
+ break;
+ case -1:
+ (*ocd)->octo_encrypt = octo_des_cbc_encrypt;
+ (*ocd)->octo_decrypt = octo_des_cbc_decrypt;
+ break;
+ default:
+ cryptocteon_freesession(NULL, i);
+ dprintf("%s,%d: EINVALn", __FILE__, __LINE__);
+ return EINVAL;
+ }
+ break;
+ case CRYPTO_AES_CBC:
+ (*ocd)->octo_ivsize = 16;
+ switch (macini ? macini->cri_alg : -1) {
+ case CRYPTO_MD5_HMAC:
+ (*ocd)->octo_encrypt = octo_aes_cbc_md5_encrypt;
+ (*ocd)->octo_decrypt = octo_aes_cbc_md5_decrypt;
+ octo_calc_hash(0, macini->cri_key, (*ocd)->octo_hminner,
+ (*ocd)->octo_hmouter);
+ break;
+ case CRYPTO_SHA1_HMAC:
+ (*ocd)->octo_encrypt = octo_aes_cbc_sha1_encrypt;
+ (*ocd)->octo_decrypt = octo_aes_cbc_sha1_decrypt;
+ octo_calc_hash(1, macini->cri_key, (*ocd)->octo_hminner,
+ (*ocd)->octo_hmouter);
+ break;
+ case -1:
+ (*ocd)->octo_encrypt = octo_aes_cbc_encrypt;
+ (*ocd)->octo_decrypt = octo_aes_cbc_decrypt;
+ break;
+ default:
+ cryptocteon_freesession(NULL, i);
+ dprintf("%s,%d: EINVALn", __FILE__, __LINE__);
+ return EINVAL;
+ }
+ break;
+ case CRYPTO_MD5_HMAC:
+ (*ocd)->octo_encrypt = octo_null_md5_encrypt;
+ (*ocd)->octo_decrypt = octo_null_md5_encrypt;
+ octo_calc_hash(0, macini->cri_key, (*ocd)->octo_hminner,
+ (*ocd)->octo_hmouter);
+ break;
+ case CRYPTO_SHA1_HMAC:
+ (*ocd)->octo_encrypt = octo_null_sha1_encrypt;
+ (*ocd)->octo_decrypt = octo_null_sha1_encrypt;
+ octo_calc_hash(1, macini->cri_key, (*ocd)->octo_hminner,
+ (*ocd)->octo_hmouter);
+ break;
+ default:
+ cryptocteon_freesession(NULL, i);
+ dprintf("%s,%d: EINVALn", __FILE__, __LINE__);
+ return EINVAL;
+ }
+
+ (*ocd)->octo_encalg = encini ? encini->cri_alg : -1;
+ (*ocd)->octo_macalg = macini ? macini->cri_alg : -1;
+
+ return 0;
+}
+
+/*
+ * Free a session.
+ */
+static int
+cryptocteon_freesession(device_t dev, u_int64_t tid)
+{
+ struct cryptocteon_softc *sc;
+ u_int32_t sid = CRYPTO_SESID2LID(tid);
+
+ sc = device_get_softc(dev);
+
+ if (sc == NULL)
+ return (EINVAL);
+
+ if (sid > sc->sc_sesnum || sc->sc_sessions == NULL ||
+ sc->sc_sessions[sid] == NULL)
+ return (EINVAL);
+
+ /* Silently accept and return */
+ if (sid == 0)
+ return(0);
+
+ if (sc->sc_sessions[sid])
+ free(sc->sc_sessions[sid], M_DEVBUF);
+ sc->sc_sessions[sid] = NULL;
+ return 0;
+}
+
+/*
+ * Process a request.
+ */
+static int
+cryptocteon_process(device_t dev, struct cryptop *crp, int hint)
+{
+ struct cryptodesc *crd;
+ struct octo_sess *od;
+ u_int32_t lid;
+ size_t iovcnt, iovlen;
+ struct mbuf *m = NULL;
+ struct uio *uiop = NULL;
+ struct cryptodesc *enccrd = NULL, *maccrd = NULL;
+ unsigned char *ivp = NULL;
+ unsigned char iv_data[HASH_MAX_LEN];
+ int auth_off = 0, auth_len = 0, crypt_off = 0, crypt_len = 0, icv_off = 0;
+ struct cryptocteon_softc *sc;
+
+ sc = device_get_softc(dev);
+
+ if (sc == NULL || crp == NULL)
+ return EINVAL;
+
+ crp->crp_etype = 0;
+
+ if (crp->crp_desc == NULL || crp->crp_buf == NULL) {
+ dprintf("%s,%d: EINVAL\n", __FILE__, __LINE__);
+ crp->crp_etype = EINVAL;
+ goto done;
+ }
+
+ lid = crp->crp_sid & 0xffffffff;
+ if (lid >= sc->sc_sesnum || lid == 0 || sc->sc_sessions == NULL ||
+ sc->sc_sessions[lid] == NULL) {
+ crp->crp_etype = ENOENT;
+ dprintf("%s,%d: ENOENT\n", __FILE__, __LINE__);
+ goto done;
+ }
+ od = sc->sc_sessions[lid];
+
+ /*
+ * do some error checking outside of the loop for m and IOV processing
+ * this leaves us with valid m or uiop pointers for later
+ */
+ if (crp->crp_flags & CRYPTO_F_IMBUF) {
+ unsigned frags;
+
+ m = (struct mbuf *) crp->crp_buf;
+ for (frags = 0; m != NULL; frags++)
+ m = m->m_next;
+
+ if (frags >= UIO_MAXIOV) {
+ printf("%s,%d: %d frags > UIO_MAXIOV", __FILE__, __LINE__, frags);
+ goto done;
+ }
+
+ m = (struct mbuf *) crp->crp_buf;
+ } else if (crp->crp_flags & CRYPTO_F_IOV) {
+ uiop = (struct uio *) crp->crp_buf;
+ if (uiop->uio_iovcnt > UIO_MAXIOV) {
+ printf("%s,%d: %d uio_iovcnt > UIO_MAXIOV", __FILE__, __LINE__,
+ uiop->uio_iovcnt);
+ goto done;
+ }
+ }
+
+ /* point our enccrd and maccrd appropriately */
+ crd = crp->crp_desc;
+ if (crd->crd_alg == od->octo_encalg) enccrd = crd;
+ if (crd->crd_alg == od->octo_macalg) maccrd = crd;
+ crd = crd->crd_next;
+ if (crd) {
+ if (crd->crd_alg == od->octo_encalg) enccrd = crd;
+ if (crd->crd_alg == od->octo_macalg) maccrd = crd;
+ crd = crd->crd_next;
+ }
+ if (crd) {
+ crp->crp_etype = EINVAL;
+ dprintf("%s,%d: ENOENT - descriptors do not match session\n",
+ __FILE__, __LINE__);
+ goto done;
+ }
+
+ if (enccrd) {
+ if (enccrd->crd_flags & CRD_F_IV_EXPLICIT) {
+ ivp = enccrd->crd_iv;
+ } else {
+ ivp = iv_data;
+ crypto_copydata(crp->crp_flags, crp->crp_buf,
+ enccrd->crd_inject, od->octo_ivsize, (caddr_t) ivp);
+ }
+
+ if (maccrd) {
+ auth_off = maccrd->crd_skip;
+ auth_len = maccrd->crd_len;
+ icv_off = maccrd->crd_inject;
+ }
+
+ crypt_off = enccrd->crd_skip;
+ crypt_len = enccrd->crd_len;
+ } else { /* if (maccrd) */
+ auth_off = maccrd->crd_skip;
+ auth_len = maccrd->crd_len;
+ icv_off = maccrd->crd_inject;
+ }
+
+ /*
+ * setup the I/O vector to cover the buffer
+ */
+ if (crp->crp_flags & CRYPTO_F_IMBUF) {
+ iovcnt = 0;
+ iovlen = 0;
+
+ while (m != NULL) {
+ od->octo_iov[iovcnt].iov_base = mtod(m, void *);
+ od->octo_iov[iovcnt].iov_len = m->m_len;
+
+ m = m->m_next;
+ iovlen += od->octo_iov[iovcnt++].iov_len;
+ }
+ } else if (crp->crp_flags & CRYPTO_F_IOV) {
+ iovlen = 0;
+ for (iovcnt = 0; iovcnt < uiop->uio_iovcnt; iovcnt++) {
+ od->octo_iov[iovcnt].iov_base = uiop->uio_iov[iovcnt].iov_base;
+ od->octo_iov[iovcnt].iov_len = uiop->uio_iov[iovcnt].iov_len;
+
+ iovlen += od->octo_iov[iovcnt].iov_len;
+ }
+ } else {
+ iovlen = crp->crp_ilen;
+ od->octo_iov[0].iov_base = crp->crp_buf;
+ od->octo_iov[0].iov_len = crp->crp_ilen;
+ iovcnt = 1;
+ }
+
+
+ /*
+ * setup a new explicit key
+ */
+ if (enccrd) {
+ if (enccrd->crd_flags & CRD_F_KEY_EXPLICIT) {
+ od->octo_encklen = (enccrd->crd_klen + 7) / 8;
+ memcpy(od->octo_enckey, enccrd->crd_key, od->octo_encklen);
+ }
+ }
+ if (maccrd) {
+ if (maccrd->crd_flags & CRD_F_KEY_EXPLICIT) {
+ od->octo_macklen = (maccrd->crd_klen + 7) / 8;
+ memcpy(od->octo_mackey, maccrd->crd_key, od->octo_macklen);
+ od->octo_mackey_set = 0;
+ }
+ if (!od->octo_mackey_set) {
+ octo_calc_hash(maccrd->crd_alg == CRYPTO_MD5_HMAC ? 0 : 1,
+ maccrd->crd_key, od->octo_hminner, od->octo_hmouter);
+ od->octo_mackey_set = 1;
+ }
+ }
+
+
+ if (!enccrd || (enccrd->crd_flags & CRD_F_ENCRYPT))
+ (*od->octo_encrypt)(od, od->octo_iov, iovcnt, iovlen,
+ auth_off, auth_len, crypt_off, crypt_len, icv_off, ivp);
+ else
+ (*od->octo_decrypt)(od, od->octo_iov, iovcnt, iovlen,
+ auth_off, auth_len, crypt_off, crypt_len, icv_off, ivp);
+
+done:
+ crypto_done(crp);
+ return 0;
+}
+
+static device_method_t cryptocteon_methods[] = {
+ /* device methods */
+ DEVMETHOD(device_identify, cryptocteon_identify),
+ DEVMETHOD(device_probe, cryptocteon_probe),
+ DEVMETHOD(device_attach, cryptocteon_attach),
+
+ /* crypto device methods */
+ DEVMETHOD(cryptodev_newsession, cryptocteon_newsession),
+ DEVMETHOD(cryptodev_freesession,cryptocteon_freesession),
+ DEVMETHOD(cryptodev_process, cryptocteon_process),
+
+ { 0, 0 }
+};
+
+static driver_t cryptocteon_driver = {
+ "cryptocteon",
+ cryptocteon_methods,
+ sizeof (struct cryptocteon_softc),
+};
+static devclass_t cryptocteon_devclass;
+DRIVER_MODULE(cryptocteon, nexus, cryptocteon_driver, cryptocteon_devclass, 0, 0);
Property changes on: trunk/sys/mips/cavium/cryptocteon/cryptocteon.c
___________________________________________________________________
Added: svn:eol-style
## -0,0 +1 ##
+native
\ No newline at end of property
Added: svn:keywords
## -0,0 +1 ##
+MidnightBSD=%H
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+text/plain
\ No newline at end of property
Added: trunk/sys/mips/cavium/cryptocteon/cryptocteonvar.h
===================================================================
--- trunk/sys/mips/cavium/cryptocteon/cryptocteonvar.h (rev 0)
+++ trunk/sys/mips/cavium/cryptocteon/cryptocteonvar.h 2018-05-26 21:55:02 UTC (rev 9987)
@@ -0,0 +1,95 @@
+/* $MidnightBSD$ */
+/*
+ * Octeon Crypto for OCF
+ *
+ * Written by David McCullough <david_mccullough at securecomputing.com>
+ * Copyright (C) 2009 David McCullough
+ *
+ * LICENSE TERMS
+ *
+ * The free distribution and use of this software in both source and binary
+ * form is allowed (with or without changes) provided that:
+ *
+ * 1. distributions of this source code include the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ *
+ * 2. distributions in binary form include the above copyright
+ * notice, this list of conditions and the following disclaimer
+ * in the documentation and/or other associated materials;
+ *
+ * 3. the copyright holder's name is not used to endorse products
+ * built using this software without specific written permission.
+ *
+ * DISCLAIMER
+ *
+ * This software is provided 'as is' with no explicit or implied warranties
+ * in respect of its properties, including, but not limited to, correctness
+ * and/or fitness for purpose.
+ * ---------------------------------------------------------------------------
+ *
+ * $FreeBSD: stable/10/sys/mips/cavium/cryptocteon/cryptocteonvar.h 210312 2010-07-20 19:32:25Z jmallett $
+ */
+
+#ifndef _MIPS_CAVIUM_CRYPTOCTEON_CRYPTOCTEONVAR_H_
+#define _MIPS_CAVIUM_CRYPTOCTEON_CRYPTOCTEONVAR_H_
+
+struct octo_sess;
+
+typedef int octo_encrypt_t(struct octo_sess *od, struct iovec *iov, size_t iovcnt, size_t iovlen, int auth_off, int auth_len, int crypt_off, int crypt_len, int icv_off, uint8_t *ivp);
+typedef int octo_decrypt_t(struct octo_sess *od, struct iovec *iov, size_t iovcnt, size_t iovlen, int auth_off, int auth_len, int crypt_off, int crypt_len, int icv_off, uint8_t *ivp);
+
+struct octo_sess {
+ int octo_encalg;
+ #define MAX_CIPHER_KEYLEN 64
+ char octo_enckey[MAX_CIPHER_KEYLEN];
+ int octo_encklen;
+
+ int octo_macalg;
+ #define MAX_HASH_KEYLEN 64
+ char octo_mackey[MAX_HASH_KEYLEN];
+ int octo_macklen;
+ int octo_mackey_set;
+
+ int octo_mlen;
+ int octo_ivsize;
+
+ octo_encrypt_t *octo_encrypt;
+ octo_decrypt_t *octo_decrypt;
+
+ uint64_t octo_hminner[3];
+ uint64_t octo_hmouter[3];
+
+ struct iovec octo_iov[UIO_MAXIOV];
+};
+
+#define dprintf(fmt, ...) \
+ do { \
+ if (cryptocteon_debug) \
+ printf("%s: " fmt, __func__, ## __VA_ARGS__); \
+ } while (0)
+
+extern int cryptocteon_debug;
+
+void octo_calc_hash(uint8_t, unsigned char *, uint64_t *, uint64_t *);
+
+/* XXX Actually just hashing functions, not encryption. */
+octo_encrypt_t octo_null_md5_encrypt;
+octo_encrypt_t octo_null_sha1_encrypt;
+
+octo_encrypt_t octo_des_cbc_encrypt;
+octo_encrypt_t octo_des_cbc_md5_encrypt;
+octo_encrypt_t octo_des_cbc_sha1_encrypt;
+
+octo_decrypt_t octo_des_cbc_decrypt;
+octo_decrypt_t octo_des_cbc_md5_decrypt;
+octo_decrypt_t octo_des_cbc_sha1_decrypt;
+
+octo_encrypt_t octo_aes_cbc_encrypt;
+octo_encrypt_t octo_aes_cbc_md5_encrypt;
+octo_encrypt_t octo_aes_cbc_sha1_encrypt;
+
+octo_decrypt_t octo_aes_cbc_decrypt;
+octo_decrypt_t octo_aes_cbc_md5_decrypt;
+octo_decrypt_t octo_aes_cbc_sha1_decrypt;
+
+#endif /* !_MIPS_CAVIUM_CRYPTOCTEON_CRYPTOCTEONVAR_H_ */
Property changes on: trunk/sys/mips/cavium/cryptocteon/cryptocteonvar.h
___________________________________________________________________
Added: svn:eol-style
## -0,0 +1 ##
+native
\ No newline at end of property
Added: svn:keywords
## -0,0 +1 ##
+MidnightBSD=%H
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+text/plain
\ No newline at end of property
Added: trunk/sys/mips/cavium/cvmx_config.h
===================================================================
--- trunk/sys/mips/cavium/cvmx_config.h (rev 0)
+++ trunk/sys/mips/cavium/cvmx_config.h 2018-05-26 21:55:02 UTC (rev 9987)
@@ -0,0 +1,199 @@
+/* $MidnightBSD$ */
+/***********************license start***************
+ * Copyright (c) 2003-2008 Cavium Networks (support at cavium.com). All rights
+ * reserved.
+ *
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
+ *
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ *
+ * * Redistributions in binary form must reproduce the above
+ * copyright notice, this list of conditions and the following
+ * disclaimer in the documentation and/or other materials provided
+ * with the distribution.
+ *
+ * * Neither the name of Cavium Networks nor the names of
+ * its contributors may be used to endorse or promote products
+ * derived from this software without specific prior written
+ * permission.
+ *
+ * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
+ * AND WITH ALL FAULTS AND CAVIUM NETWORKS MAKES NO PROMISES, REPRESENTATIONS
+ * OR WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH
+ * RESPECT TO THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY
+ * REPRESENTATION OR DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT
+ * DEFECTS, AND CAVIUM SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES
+ * OF TITLE, MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR
+ * PURPOSE, LACK OF VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET
+ * POSSESSION OR CORRESPONDENCE TO DESCRIPTION. THE ENTIRE RISK ARISING OUT
+ * OF USE OR PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
+ *
+ *
+ * For any questions regarding licensing please contact marketing at caviumnetworks.com
+ *
+ ***********************license end**************************************/
+/* $FreeBSD: stable/10/sys/mips/cavium/cvmx_config.h 233639 2012-03-29 02:05:11Z jmallett $ */
+
+#ifndef _CVMX_CONFIG_H
+#define _CVMX_CONFIG_H
+
+#include "opt_cvmx.h"
+
+#include <sys/types.h>
+#include <sys/param.h>
+#include <sys/systm.h>
+#include <sys/mbuf.h>
+
+#include <vm/vm.h>
+#include <vm/pmap.h>
+
+#include <machine/pmap.h>
+#include <machine/stdarg.h>
+
+#define asm __asm
+
+#define CVMX_DONT_INCLUDE_CONFIG
+
+/* Define to enable the use of simple executive packet output functions.
+** For packet I/O setup enable the helper functions below.
+*/
+#define CVMX_ENABLE_PKO_FUNCTIONS
+
+/* Define to enable the use of simple executive helper functions. These
+** include many harware setup functions. See cvmx-helper.[ch] for
+** details.
+*/
+#define CVMX_ENABLE_HELPER_FUNCTIONS
+
+/* CVMX_HELPER_FIRST_MBUFF_SKIP is the number of bytes to reserve before
+** the beginning of the packet. If necessary, override the default
+** here. See the IPD section of the hardware manual for MBUFF SKIP
+** details.*/
+#define CVMX_HELPER_FIRST_MBUFF_SKIP 184
+
+/* CVMX_HELPER_NOT_FIRST_MBUFF_SKIP is the number of bytes to reserve in each
+** chained packet element. If necessary, override the default here */
+#define CVMX_HELPER_NOT_FIRST_MBUFF_SKIP 0
+
+/* CVMX_HELPER_ENABLE_BACK_PRESSURE controls whether back pressure is enabled
+** for all input ports. This controls if IPD sends backpressure to all ports if
+** Octeon's FPA pools don't have enough packet or work queue entries. Even when
+** this is off, it is still possible to get backpressure from individual
+** hardware ports. When configuring backpressure, also check
+** CVMX_HELPER_DISABLE_*_BACKPRESSURE below. If necessary, override the default
+** here */
+#define CVMX_HELPER_ENABLE_BACK_PRESSURE 1
+
+/* CVMX_HELPER_ENABLE_IPD controls if the IPD is enabled in the helper
+** function. Once it is enabled the hardware starts accepting packets. You
+** might want to skip the IPD enable if configuration changes are need
+** from the default helper setup. If necessary, override the default here */
+#define CVMX_HELPER_ENABLE_IPD 1
+
+/* CVMX_HELPER_INPUT_TAG_TYPE selects the type of tag that the IPD assigns
+** to incoming packets. */
+#define CVMX_HELPER_INPUT_TAG_TYPE CVMX_POW_TAG_TYPE_ORDERED
+
+/* The following select which fields are used by the PIP to generate
+** the tag on INPUT
+** 0: don't include
+** 1: include */
+#define CVMX_HELPER_INPUT_TAG_IPV6_SRC_IP 0
+#define CVMX_HELPER_INPUT_TAG_IPV6_DST_IP 0
+#define CVMX_HELPER_INPUT_TAG_IPV6_SRC_PORT 0
+#define CVMX_HELPER_INPUT_TAG_IPV6_DST_PORT 0
+#define CVMX_HELPER_INPUT_TAG_IPV6_NEXT_HEADER 0
+#define CVMX_HELPER_INPUT_TAG_IPV4_SRC_IP 0
+#define CVMX_HELPER_INPUT_TAG_IPV4_DST_IP 0
+#define CVMX_HELPER_INPUT_TAG_IPV4_SRC_PORT 0
+#define CVMX_HELPER_INPUT_TAG_IPV4_DST_PORT 0
+#define CVMX_HELPER_INPUT_TAG_IPV4_PROTOCOL 0
+#define CVMX_HELPER_INPUT_TAG_INPUT_PORT 1
+
+/* Select skip mode for input ports */
+#define CVMX_HELPER_INPUT_PORT_SKIP_MODE CVMX_PIP_PORT_CFG_MODE_SKIPL2
+
+/* Define the number of queues per output port */
+#define CVMX_HELPER_PKO_QUEUES_PER_PORT_INTERFACE0 1
+#define CVMX_HELPER_PKO_QUEUES_PER_PORT_INTERFACE1 1
+
+/* Configure PKO to use per-core queues (PKO lockless operation).
+** Please see the related SDK documentation for PKO that illustrates
+** how to enable and configure this option. */
+//#define CVMX_ENABLE_PKO_LOCKLESS_OPERATION 1
+//#define CVMX_HELPER_PKO_MAX_PORTS_INTERFACE0 8
+//#define CVMX_HELPER_PKO_MAX_PORTS_INTERFACE1 8
+
+/* Force backpressure to be disabled. This overrides all other
+** backpressure configuration */
+#define CVMX_HELPER_DISABLE_RGMII_BACKPRESSURE 1
+
+/* Disable the SPI4000's processing of backpressure packets and backpressure
+** generation. When this is 1, the SPI4000 will not stop sending packets when
+** receiving backpressure. It will also not generate backpressure packets when
+** its internal FIFOs are full. */
+#define CVMX_HELPER_DISABLE_SPI4000_BACKPRESSURE 1
+
+/* CVMX_HELPER_SPI_TIMEOUT is used to determine how long the SPI initialization
+** routines wait for SPI training. You can override the value using
+** executive-config.h if necessary */
+#define CVMX_HELPER_SPI_TIMEOUT 10
+
+/* Select the number of low latency memory ports (interfaces) that
+** will be configured. Valid values are 1 and 2.
+*/
+#define CVMX_LLM_CONFIG_NUM_PORTS 2
+
+/* Enable the fix for PKI-100 errata ("Size field is 8 too large in WQE and next
+** pointers"). If CVMX_ENABLE_LEN_M8_FIX is set to 0, the fix for this errata will
+** not be enabled.
+** 0: Fix is not enabled
+** 1: Fix is enabled, if supported by hardware
+*/
+#define CVMX_ENABLE_LEN_M8_FIX 1
+
+#if defined(CVMX_ENABLE_HELPER_FUNCTIONS) && !defined(CVMX_ENABLE_PKO_FUNCTIONS)
+#define CVMX_ENABLE_PKO_FUNCTIONS
+#endif
+
+/* Enable debug and informational printfs */
+#define CVMX_CONFIG_ENABLE_DEBUG_PRINTS 1
+
+/************************* Config Specific Defines ************************/
+#define CVMX_LLM_NUM_PORTS 1
+#define CVMX_PKO_QUEUES_PER_PORT_INTERFACE0 1 /**< PKO queues per port for interface 0 (ports 0-15) */
+#define CVMX_PKO_QUEUES_PER_PORT_INTERFACE1 1 /**< PKO queues per port for interface 1 (ports 16-31) */
+#define CVMX_PKO_MAX_PORTS_INTERFACE0 CVMX_HELPER_PKO_MAX_PORTS_INTERFACE0 /**< Limit on the number of PKO ports enabled for interface 0 */
+#define CVMX_PKO_MAX_PORTS_INTERFACE1 CVMX_HELPER_PKO_MAX_PORTS_INTERFACE1 /**< Limit on the number of PKO ports enabled for interface 1 */
+#define CVMX_PKO_QUEUES_PER_PORT_PCI 1 /**< PKO queues per port for PCI (ports 32-35) */
+#define CVMX_PKO_QUEUES_PER_PORT_LOOP 1 /**< PKO queues per port for Loop devices (ports 36-39) */
+
+/************************* FPA allocation *********************************/
+/* Pool sizes in bytes, must be multiple of a cache line */
+#define CVMX_FPA_POOL_0_SIZE (15 * CVMX_CACHE_LINE_SIZE)
+#define CVMX_FPA_POOL_1_SIZE (1 * CVMX_CACHE_LINE_SIZE)
+#define CVMX_FPA_POOL_2_SIZE (8 * CVMX_CACHE_LINE_SIZE)
+#define CVMX_FPA_POOL_3_SIZE (0 * CVMX_CACHE_LINE_SIZE)
+#define CVMX_FPA_POOL_4_SIZE (0 * CVMX_CACHE_LINE_SIZE)
+#define CVMX_FPA_POOL_5_SIZE (0 * CVMX_CACHE_LINE_SIZE)
+#define CVMX_FPA_POOL_6_SIZE (0 * CVMX_CACHE_LINE_SIZE)
+#define CVMX_FPA_POOL_7_SIZE (0 * CVMX_CACHE_LINE_SIZE)
+
+/* Pools in use */
+#define CVMX_FPA_PACKET_POOL (0) /**< Packet buffers */
+#define CVMX_FPA_PACKET_POOL_SIZE CVMX_FPA_POOL_0_SIZE
+#define CVMX_FPA_WQE_POOL (1) /**< Work queue entrys */
+#define CVMX_FPA_WQE_POOL_SIZE CVMX_FPA_POOL_1_SIZE
+#define CVMX_FPA_OUTPUT_BUFFER_POOL (2) /**< PKO queue command buffers */
+#define CVMX_FPA_OUTPUT_BUFFER_POOL_SIZE CVMX_FPA_POOL_2_SIZE
+
+/************************* FAU allocation ********************************/
+#define CVMX_FAU_REG_END 2048
+
+#define CVMX_SCR_SCRATCH 0
+
+#endif /* !_CVMX_CONFIG_H */
Property changes on: trunk/sys/mips/cavium/cvmx_config.h
___________________________________________________________________
Added: svn:eol-style
## -0,0 +1 ##
+native
\ No newline at end of property
Added: svn:keywords
## -0,0 +1 ##
+MidnightBSD=%H
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+text/plain
\ No newline at end of property
Added: trunk/sys/mips/cavium/files.octeon1
===================================================================
--- trunk/sys/mips/cavium/files.octeon1 (rev 0)
+++ trunk/sys/mips/cavium/files.octeon1 2018-05-26 21:55:02 UTC (rev 9987)
@@ -0,0 +1,99 @@
+# $FreeBSD: stable/10/sys/mips/cavium/files.octeon1 242955 2012-11-13 07:39:49Z jmallett $
+# Octeon Support Files
+#
+mips/cavium/asm_octeon.S optional smp
+mips/cavium/ciu.c standard
+mips/cavium/obio.c optional uart
+mips/cavium/octeon_ds1337.c standard
+mips/cavium/octeon_ebt3000_cf.c optional cf
+mips/cavium/octeon_machdep.c standard
+mips/cavium/octeon_mp.c optional smp
+mips/cavium/octeon_pmc.c optional hwpmc
+mips/cavium/octeon_rtc.c standard
+mips/cavium/uart_bus_octeonusart.c optional uart
+mips/cavium/uart_cpu_octeonusart.c optional uart
+mips/cavium/uart_dev_oct16550.c optional uart
+mips/mips/intr_machdep.c standard
+mips/mips/tick.c standard
+
+mips/cavium/octeon_rnd.c optional random
+mips/cavium/octeon_wdog.c optional octeon_wdog
+mips/cavium/octeon_nmi.S optional octeon_wdog
+
+mips/cavium/cryptocteon/cavium_crypto.c optional cryptocteon
+mips/cavium/cryptocteon/cryptocteon.c optional cryptocteon
+mips/mips/octeon_cop2_swtch.S standard
+mips/mips/octeon_cop2.c standard
+
+mips/cavium/if_octm.c optional octm
+contrib/octeon-sdk/cvmx-mgmt-port.c optional octm
+
+mips/cavium/octe/ethernet.c optional octe
+mips/cavium/octe/ethernet-mv88e61xx.c optional octe octeon_vendor_lanner
+mips/cavium/octe/ethernet-common.c optional octe
+mips/cavium/octe/ethernet-mdio.c optional octe
+mips/cavium/octe/ethernet-mem.c optional octe
+mips/cavium/octe/ethernet-rgmii.c optional octe
+mips/cavium/octe/ethernet-rx.c optional octe
+mips/cavium/octe/ethernet-sgmii.c optional octe
+mips/cavium/octe/ethernet-spi.c optional octe
+mips/cavium/octe/ethernet-tx.c optional octe
+mips/cavium/octe/ethernet-xaui.c optional octe
+mips/cavium/octe/mv88e61xxphy.c optional octe mv88e61xxphy
+mips/cavium/octe/octe.c optional octe
+mips/cavium/octe/octebus.c optional octe
+
+mips/cavium/octopci.c optional pci
+mips/cavium/octopci_bus_space.c optional pci
+mips/cavium/octeon_pci_console.c optional pci
+contrib/octeon-sdk/octeon-pci-console.c optional pci
+
+mips/cavium/usb/octusb.c optional usb octusb
+mips/cavium/usb/octusb_octeon.c optional usb octusb
+
+contrib/octeon-sdk/cvmx-usb.c optional octusb
+
+mips/cavium/octeon_gpio.c optional gpio
+
+# XXX Some files could be excluded in some configurations. Making them
+# optional but on in the default config would seem reasonable.
+contrib/octeon-sdk/cvmx-cmd-queue.c standard
+contrib/octeon-sdk/cvmx-bootmem.c standard
+contrib/octeon-sdk/cvmx-clock.c standard
+contrib/octeon-sdk/cvmx-ebt3000.c standard
+contrib/octeon-sdk/cvmx-fpa.c standard
+contrib/octeon-sdk/cvmx-helper.c standard
+contrib/octeon-sdk/cvmx-helper-cfg.c standard
+contrib/octeon-sdk/cvmx-helper-board.c standard
+contrib/octeon-sdk/cvmx-helper-cfg.c standard
+contrib/octeon-sdk/cvmx-helper-errata.c standard
+contrib/octeon-sdk/cvmx-helper-fpa.c standard
+contrib/octeon-sdk/cvmx-helper-ilk.c standard
+contrib/octeon-sdk/cvmx-helper-jtag.c standard
+contrib/octeon-sdk/cvmx-helper-loop.c standard
+contrib/octeon-sdk/cvmx-helper-npi.c standard
+contrib/octeon-sdk/cvmx-helper-rgmii.c standard
+contrib/octeon-sdk/cvmx-helper-sgmii.c standard
+contrib/octeon-sdk/cvmx-helper-spi.c standard
+contrib/octeon-sdk/cvmx-helper-srio.c standard
+contrib/octeon-sdk/cvmx-helper-util.c standard
+contrib/octeon-sdk/cvmx-helper-xaui.c standard
+contrib/octeon-sdk/cvmx-ilk.c standard
+contrib/octeon-sdk/cvmx-ipd.c standard
+contrib/octeon-sdk/cvmx-l2c.c standard
+contrib/octeon-sdk/cvmx-pcie.c standard
+contrib/octeon-sdk/cvmx-pko.c standard
+contrib/octeon-sdk/cvmx-qlm.c standard
+contrib/octeon-sdk/cvmx-qlm-tables.c standard
+contrib/octeon-sdk/cvmx-spi.c standard
+contrib/octeon-sdk/cvmx-spi4000.c standard
+contrib/octeon-sdk/cvmx-srio.c standard
+contrib/octeon-sdk/cvmx-sysinfo.c standard
+contrib/octeon-sdk/cvmx-thunder.c standard
+contrib/octeon-sdk/cvmx-twsi.c standard
+contrib/octeon-sdk/cvmx-warn.c standard
+contrib/octeon-sdk/octeon-feature.c standard
+contrib/octeon-sdk/octeon-model.c standard
+
+# HWPMC
+dev/hwpmc/hwpmc_octeon.c optional hwpmc
Property changes on: trunk/sys/mips/cavium/files.octeon1
___________________________________________________________________
Added: mnbsd:nokeywords
## -0,0 +1 ##
+MidnightBSD=%H
\ No newline at end of property
Added: trunk/sys/mips/cavium/if_octm.c
===================================================================
--- trunk/sys/mips/cavium/if_octm.c (rev 0)
+++ trunk/sys/mips/cavium/if_octm.c 2018-05-26 21:55:02 UTC (rev 9987)
@@ -0,0 +1,539 @@
+/* $MidnightBSD$ */
+/*-
+ * Copyright (c) 2010-2011 Juli Mallett <jmallett at FreeBSD.org>
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ * $FreeBSD: stable/10/sys/mips/cavium/if_octm.c 243882 2012-12-05 08:04:20Z glebius $
+ */
+
+/*
+ * Cavium Octeon management port Ethernet devices.
+ */
+
+#include "opt_inet.h"
+
+#include <sys/param.h>
+#include <sys/systm.h>
+#include <sys/bus.h>
+#include <sys/endian.h>
+#include <sys/kernel.h>
+#include <sys/mbuf.h>
+#include <sys/lock.h>
+#include <sys/module.h>
+#include <sys/mutex.h>
+#include <sys/rman.h>
+#include <sys/socket.h>
+#include <sys/sockio.h>
+#include <sys/sysctl.h>
+
+#include <net/bpf.h>
+#include <net/ethernet.h>
+#include <net/if.h>
+#include <net/if_dl.h>
+#include <net/if_media.h>
+#include <net/if_types.h>
+#include <net/if_var.h>
+#include <net/if_vlan_var.h>
+
+#ifdef INET
+#include <netinet/in.h>
+#include <netinet/if_ether.h>
+#endif
+
+#include <contrib/octeon-sdk/cvmx.h>
+#include <mips/cavium/octeon_irq.h>
+#include <contrib/octeon-sdk/cvmx-mgmt-port.h>
+
+struct octm_softc {
+ struct ifnet *sc_ifp;
+ device_t sc_dev;
+ unsigned sc_port;
+ int sc_flags;
+ struct ifmedia sc_ifmedia;
+ struct resource *sc_intr;
+ void *sc_intr_cookie;
+};
+
+static void octm_identify(driver_t *, device_t);
+static int octm_probe(device_t);
+static int octm_attach(device_t);
+static int octm_detach(device_t);
+static int octm_shutdown(device_t);
+
+static void octm_init(void *);
+static int octm_transmit(struct ifnet *, struct mbuf *);
+
+static int octm_medchange(struct ifnet *);
+static void octm_medstat(struct ifnet *, struct ifmediareq *);
+
+static int octm_ioctl(struct ifnet *, u_long, caddr_t);
+
+static void octm_rx_intr(void *);
+
+static device_method_t octm_methods[] = {
+ /* Device interface */
+ DEVMETHOD(device_identify, octm_identify),
+ DEVMETHOD(device_probe, octm_probe),
+ DEVMETHOD(device_attach, octm_attach),
+ DEVMETHOD(device_detach, octm_detach),
+ DEVMETHOD(device_shutdown, octm_shutdown),
+
+ { 0, 0 }
+};
+
+static driver_t octm_driver = {
+ "octm",
+ octm_methods,
+ sizeof (struct octm_softc),
+};
+
+static devclass_t octm_devclass;
+
+DRIVER_MODULE(octm, ciu, octm_driver, octm_devclass, 0, 0);
+
+static void
+octm_identify(driver_t *drv, device_t parent)
+{
+ unsigned i;
+
+ if (!octeon_has_feature(OCTEON_FEATURE_MGMT_PORT))
+ return;
+
+ for (i = 0; i < CVMX_MGMT_PORT_NUM_PORTS; i++)
+ BUS_ADD_CHILD(parent, 0, "octm", i);
+}
+
+static int
+octm_probe(device_t dev)
+{
+ cvmx_mgmt_port_result_t result;
+
+ result = cvmx_mgmt_port_initialize(device_get_unit(dev));
+ switch (result) {
+ case CVMX_MGMT_PORT_SUCCESS:
+ break;
+ case CVMX_MGMT_PORT_NO_MEMORY:
+ return (ENOBUFS);
+ case CVMX_MGMT_PORT_INVALID_PARAM:
+ return (ENXIO);
+ case CVMX_MGMT_PORT_INIT_ERROR:
+ return (EIO);
+ }
+
+ device_set_desc(dev, "Cavium Octeon Management Ethernet");
+
+ return (0);
+}
+
+static int
+octm_attach(device_t dev)
+{
+ struct ifnet *ifp;
+ struct octm_softc *sc;
+ cvmx_mixx_irhwm_t mixx_irhwm;
+ cvmx_mixx_intena_t mixx_intena;
+ uint64_t mac;
+ int error;
+ int irq;
+ int rid;
+
+ sc = device_get_softc(dev);
+ sc->sc_dev = dev;
+ sc->sc_port = device_get_unit(dev);
+
+ switch (sc->sc_port) {
+ case 0:
+ irq = OCTEON_IRQ_MII;
+ break;
+ case 1:
+ irq = OCTEON_IRQ_MII1;
+ break;
+ default:
+ device_printf(dev, "unsupported management port %u.\n", sc->sc_port);
+ return (ENXIO);
+ }
+
+ /*
+ * Set MAC address for this management port.
+ */
+ mac = 0;
+ memcpy((u_int8_t *)&mac + 2, cvmx_sysinfo_get()->mac_addr_base, 6);
+ mac += sc->sc_port;
+
+ cvmx_mgmt_port_set_mac(sc->sc_port, mac);
+
+ /* No watermark for input ring. */
+ mixx_irhwm.u64 = 0;
+ cvmx_write_csr(CVMX_MIXX_IRHWM(sc->sc_port), mixx_irhwm.u64);
+
+ /* Enable input ring interrupts. */
+ mixx_intena.u64 = 0;
+ mixx_intena.s.ithena = 1;
+ cvmx_write_csr(CVMX_MIXX_INTENA(sc->sc_port), mixx_intena.u64);
+
+ /* Allocate and establish interrupt. */
+ rid = 0;
+ sc->sc_intr = bus_alloc_resource(sc->sc_dev, SYS_RES_IRQ, &rid,
+ irq, irq, 1, RF_ACTIVE);
+ if (sc->sc_intr == NULL) {
+ device_printf(dev, "unable to allocate IRQ.\n");
+ return (ENXIO);
+ }
+
+ error = bus_setup_intr(sc->sc_dev, sc->sc_intr, INTR_TYPE_NET, NULL,
+ octm_rx_intr, sc, &sc->sc_intr_cookie);
+ if (error != 0) {
+ device_printf(dev, "unable to setup interrupt.\n");
+ bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sc_intr);
+ return (ENXIO);
+ }
+
+ bus_describe_intr(sc->sc_dev, sc->sc_intr, sc->sc_intr_cookie, "rx");
+
+ /* XXX Possibly should enable TX interrupts. */
+
+ ifp = if_alloc(IFT_ETHER);
+ if (ifp == NULL) {
+ device_printf(dev, "cannot allocate ifnet.\n");
+ bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sc_intr);
+ return (ENOMEM);
+ }
+
+ if_initname(ifp, device_get_name(dev), device_get_unit(dev));
+ ifp->if_mtu = ETHERMTU;
+ ifp->if_init = octm_init;
+ ifp->if_softc = sc;
+ ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST | IFF_ALLMULTI;
+ ifp->if_ioctl = octm_ioctl;
+
+ sc->sc_ifp = ifp;
+ sc->sc_flags = ifp->if_flags;
+
+ ifmedia_init(&sc->sc_ifmedia, 0, octm_medchange, octm_medstat);
+
+ ifmedia_add(&sc->sc_ifmedia, IFM_ETHER | IFM_AUTO, 0, NULL);
+ ifmedia_set(&sc->sc_ifmedia, IFM_ETHER | IFM_AUTO);
+
+ ether_ifattach(ifp, (const u_int8_t *)&mac + 2);
+
+ ifp->if_transmit = octm_transmit;
+
+ ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header);
+ ifp->if_capabilities = IFCAP_VLAN_MTU;
+ ifp->if_capenable = ifp->if_capabilities;
+
+ IFQ_SET_MAXLEN(&ifp->if_snd, CVMX_MGMT_PORT_NUM_TX_BUFFERS);
+ ifp->if_snd.ifq_drv_maxlen = CVMX_MGMT_PORT_NUM_TX_BUFFERS;
+ IFQ_SET_READY(&ifp->if_snd);
+
+ return (bus_generic_attach(dev));
+}
+
+static int
+octm_detach(device_t dev)
+{
+ struct octm_softc *sc;
+ cvmx_mgmt_port_result_t result;
+
+ sc = device_get_softc(dev);
+
+ result = cvmx_mgmt_port_initialize(sc->sc_port);
+ switch (result) {
+ case CVMX_MGMT_PORT_SUCCESS:
+ break;
+ case CVMX_MGMT_PORT_NO_MEMORY:
+ return (ENOBUFS);
+ case CVMX_MGMT_PORT_INVALID_PARAM:
+ return (ENXIO);
+ case CVMX_MGMT_PORT_INIT_ERROR:
+ return (EIO);
+ }
+
+ bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sc_intr);
+ /* XXX Incomplete. */
+
+ return (0);
+}
+
+static int
+octm_shutdown(device_t dev)
+{
+ return (octm_detach(dev));
+}
+
+static void
+octm_init(void *arg)
+{
+ struct ifnet *ifp;
+ struct octm_softc *sc;
+ cvmx_mgmt_port_netdevice_flags_t flags;
+ uint64_t mac;
+
+ sc = arg;
+ ifp = sc->sc_ifp;
+
+ if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) {
+ cvmx_mgmt_port_disable(sc->sc_port);
+
+ ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
+ }
+
+ /*
+ * NB:
+ * MAC must be set before allmulti and promisc below, as
+ * cvmx_mgmt_port_set_mac will always enable the CAM, and turning on
+ * promiscuous mode only works with the CAM disabled.
+ */
+ mac = 0;
+ memcpy((u_int8_t *)&mac + 2, IF_LLADDR(ifp), 6);
+ cvmx_mgmt_port_set_mac(sc->sc_port, mac);
+
+ /*
+ * This is done unconditionally, rather than only if sc_flags have
+ * changed because of set_mac's effect on the CAM noted above.
+ */
+ flags = 0;
+ if ((ifp->if_flags & IFF_ALLMULTI) != 0)
+ flags |= CVMX_IFF_ALLMULTI;
+ if ((ifp->if_flags & IFF_PROMISC) != 0)
+ flags |= CVMX_IFF_PROMISC;
+ cvmx_mgmt_port_set_multicast_list(sc->sc_port, flags);
+
+ /* XXX link state? */
+
+ if ((ifp->if_flags & IFF_UP) != 0)
+ cvmx_mgmt_port_enable(sc->sc_port);
+
+ ifp->if_drv_flags |= IFF_DRV_RUNNING;
+ ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
+}
+
+static int
+octm_transmit(struct ifnet *ifp, struct mbuf *m)
+{
+ struct octm_softc *sc;
+ cvmx_mgmt_port_result_t result;
+
+ sc = ifp->if_softc;
+
+ if ((ifp->if_drv_flags & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) !=
+ IFF_DRV_RUNNING) {
+ m_freem(m);
+ return (0);
+ }
+
+ result = cvmx_mgmt_port_sendm(sc->sc_port, m);
+
+ if (result == CVMX_MGMT_PORT_SUCCESS) {
+ ETHER_BPF_MTAP(ifp, m);
+
+ ifp->if_opackets++;
+ ifp->if_obytes += m->m_pkthdr.len;
+ } else
+ ifp->if_oerrors++;
+
+ m_freem(m);
+
+ switch (result) {
+ case CVMX_MGMT_PORT_SUCCESS:
+ return (0);
+ case CVMX_MGMT_PORT_NO_MEMORY:
+ return (ENOBUFS);
+ case CVMX_MGMT_PORT_INVALID_PARAM:
+ return (ENXIO);
+ case CVMX_MGMT_PORT_INIT_ERROR:
+ return (EIO);
+ default:
+ return (EDOOFUS);
+ }
+}
+
+static int
+octm_medchange(struct ifnet *ifp)
+{
+ return (ENOTSUP);
+}
+
+static void
+octm_medstat(struct ifnet *ifp, struct ifmediareq *ifm)
+{
+ struct octm_softc *sc;
+ cvmx_helper_link_info_t link_info;
+
+ sc = ifp->if_softc;
+
+ ifm->ifm_status = IFM_AVALID;
+ ifm->ifm_active = IFT_ETHER;
+
+ link_info = cvmx_mgmt_port_link_get(sc->sc_port);
+ if (!link_info.s.link_up)
+ return;
+
+ ifm->ifm_status |= IFM_ACTIVE;
+
+ switch (link_info.s.speed) {
+ case 10:
+ ifm->ifm_active |= IFM_10_T;
+ break;
+ case 100:
+ ifm->ifm_active |= IFM_100_TX;
+ break;
+ case 1000:
+ ifm->ifm_active |= IFM_1000_T;
+ break;
+ case 10000:
+ ifm->ifm_active |= IFM_10G_T;
+ break;
+ }
+
+ if (link_info.s.full_duplex)
+ ifm->ifm_active |= IFM_FDX;
+ else
+ ifm->ifm_active |= IFM_HDX;
+}
+
+static int
+octm_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data)
+{
+ struct octm_softc *sc;
+ struct ifreq *ifr;
+#ifdef INET
+ struct ifaddr *ifa;
+#endif
+ int error;
+
+ sc = ifp->if_softc;
+ ifr = (struct ifreq *)data;
+#ifdef INET
+ ifa = (struct ifaddr *)data;
+#endif
+
+ switch (cmd) {
+ case SIOCSIFADDR:
+#ifdef INET
+ /*
+ * Avoid reinitialization unless it's necessary.
+ */
+ if (ifa->ifa_addr->sa_family == AF_INET) {
+ ifp->if_flags |= IFF_UP;
+ if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0)
+ octm_init(sc);
+ arp_ifinit(ifp, ifa);
+
+ return (0);
+ }
+#endif
+ error = ether_ioctl(ifp, cmd, data);
+ if (error != 0)
+ return (error);
+ return (0);
+
+ case SIOCSIFFLAGS:
+ if (ifp->if_flags == sc->sc_flags)
+ return (0);
+ if ((ifp->if_flags & IFF_UP) != 0) {
+ octm_init(sc);
+ } else {
+ if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) {
+ cvmx_mgmt_port_disable(sc->sc_port);
+
+ ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
+ }
+ }
+ sc->sc_flags = ifp->if_flags;
+ return (0);
+
+ case SIOCSIFCAP:
+ /*
+ * Just change the capabilities in software, currently none
+ * require reprogramming hardware, they just toggle whether we
+ * make use of already-present facilities in software.
+ */
+ ifp->if_capenable = ifr->ifr_reqcap;
+ return (0);
+
+ case SIOCSIFMTU:
+ cvmx_mgmt_port_set_max_packet_size(sc->sc_port, ifr->ifr_mtu + ifp->if_data.ifi_hdrlen);
+ return (0);
+
+ case SIOCSIFMEDIA:
+ case SIOCGIFMEDIA:
+ error = ifmedia_ioctl(ifp, ifr, &sc->sc_ifmedia, cmd);
+ if (error != 0)
+ return (error);
+ return (0);
+
+ default:
+ error = ether_ioctl(ifp, cmd, data);
+ if (error != 0)
+ return (error);
+ return (0);
+ }
+}
+
+static void
+octm_rx_intr(void *arg)
+{
+ struct octm_softc *sc = arg;
+ cvmx_mixx_isr_t mixx_isr;
+ int len;
+
+ mixx_isr.u64 = cvmx_read_csr(CVMX_MIXX_ISR(sc->sc_port));
+ if (!mixx_isr.s.irthresh) {
+ device_printf(sc->sc_dev, "stray interrupt.\n");
+ return;
+ }
+
+ for (;;) {
+ struct mbuf *m = m_getcl(M_NOWAIT, MT_DATA, M_PKTHDR);
+ if (m == NULL) {
+ device_printf(sc->sc_dev, "no memory for receive mbuf.\n");
+ return;
+ }
+
+
+ len = cvmx_mgmt_port_receive(sc->sc_port, MCLBYTES, m->m_data);
+ if (len > 0) {
+ m->m_pkthdr.rcvif = sc->sc_ifp;
+ m->m_pkthdr.len = m->m_len = len;
+
+ sc->sc_ifp->if_ipackets++;
+
+ (*sc->sc_ifp->if_input)(sc->sc_ifp, m);
+
+ continue;
+ }
+
+ m_freem(m);
+
+ if (len == 0)
+ break;
+
+ sc->sc_ifp->if_ierrors++;
+ }
+
+ /* Acknowledge interrupts. */
+ cvmx_write_csr(CVMX_MIXX_ISR(sc->sc_port), mixx_isr.u64);
+ cvmx_read_csr(CVMX_MIXX_ISR(sc->sc_port));
+}
Property changes on: trunk/sys/mips/cavium/if_octm.c
___________________________________________________________________
Added: svn:eol-style
## -0,0 +1 ##
+native
\ No newline at end of property
Added: svn:keywords
## -0,0 +1 ##
+MidnightBSD=%H
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+text/plain
\ No newline at end of property
Added: trunk/sys/mips/cavium/obio.c
===================================================================
--- trunk/sys/mips/cavium/obio.c (rev 0)
+++ trunk/sys/mips/cavium/obio.c 2018-05-26 21:55:02 UTC (rev 9987)
@@ -0,0 +1,208 @@
+/* $MidnightBSD$ */
+/* $NetBSD: obio.c,v 1.11 2003/07/15 00:25:05 lukem Exp $ */
+
+/*-
+ * Copyright (c) 2001, 2002, 2003 Wasabi Systems, Inc.
+ * All rights reserved.
+ *
+ * Written by Jason R. Thorpe for Wasabi Systems, Inc.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * 3. All advertising materials mentioning features or use of this software
+ * must display the following acknowledgement:
+ * This product includes software developed for the NetBSD Project by
+ * Wasabi Systems, Inc.
+ * 4. The name of Wasabi Systems, Inc. may not be used to endorse
+ * or promote products derived from this software without specific prior
+ * written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/*
+ * On-board device autoconfiguration support for Cavium OCTEON 1 family of
+ * SoC devices.
+ */
+
+#include <sys/cdefs.h>
+__FBSDID("$FreeBSD: stable/10/sys/mips/cavium/obio.c 232812 2012-03-11 06:17:49Z jmallett $");
+
+#include <sys/param.h>
+#include <sys/systm.h>
+#include <sys/bus.h>
+#include <sys/kernel.h>
+#include <sys/module.h>
+#include <sys/rman.h>
+#include <sys/malloc.h>
+
+#include <machine/bus.h>
+
+#include <mips/cavium/octeon_pcmap_regs.h>
+#include <mips/cavium/obiovar.h>
+
+#include <contrib/octeon-sdk/cvmx.h>
+#include <mips/cavium/octeon_irq.h>
+
+extern struct bus_space octeon_uart_tag;
+
+static void obio_identify(driver_t *, device_t);
+static int obio_probe(device_t);
+static int obio_attach(device_t);
+
+static void
+obio_identify(driver_t *drv, device_t parent)
+{
+ BUS_ADD_CHILD(parent, 0, "obio", 0);
+}
+
+static int
+obio_probe(device_t dev)
+{
+ if (device_get_unit(dev) != 0)
+ return (ENXIO);
+ return (0);
+}
+
+static int
+obio_attach(device_t dev)
+{
+ struct obio_softc *sc = device_get_softc(dev);
+
+ sc->oba_st = mips_bus_space_generic;
+ /*
+ * XXX
+ * Here and elsewhere using RBR as a base address because it kind of
+ * is, but that feels pretty sloppy. Should consider adding a define
+ * that's more semantic, at least.
+ */
+ sc->oba_addr = CVMX_MIO_UARTX_RBR(0);
+ sc->oba_size = 0x10000;
+ sc->oba_rman.rm_type = RMAN_ARRAY;
+ sc->oba_rman.rm_descr = "OBIO I/O";
+ if (rman_init(&sc->oba_rman) != 0 ||
+ rman_manage_region(&sc->oba_rman,
+ sc->oba_addr, sc->oba_addr + sc->oba_size) != 0)
+ panic("obio_attach: failed to set up I/O rman");
+ sc->oba_irq_rman.rm_type = RMAN_ARRAY;
+ sc->oba_irq_rman.rm_descr = "OBIO IRQ";
+
+ /*
+ * This module is intended for UART purposes only and
+ * manages IRQs for UART0 and UART1.
+ */
+ if (rman_init(&sc->oba_irq_rman) != 0 ||
+ rman_manage_region(&sc->oba_irq_rman, OCTEON_IRQ_UART0, OCTEON_IRQ_UART1) != 0)
+ panic("obio_attach: failed to set up IRQ rman");
+
+ device_add_child(dev, "uart", 1); /* Setup Uart-1 first. */
+ device_add_child(dev, "uart", 0); /* Uart-0 next. So it is first in console list */
+ bus_generic_probe(dev);
+ bus_generic_attach(dev);
+ return (0);
+}
+
+static struct resource *
+obio_alloc_resource(device_t bus, device_t child, int type, int *rid,
+ u_long start, u_long end, u_long count, u_int flags)
+{
+ struct resource *rv;
+ struct rman *rm;
+ bus_space_tag_t bt = 0;
+ bus_space_handle_t bh = 0;
+ struct obio_softc *sc = device_get_softc(bus);
+
+ switch (type) {
+ case SYS_RES_IRQ:
+ switch (device_get_unit(child)) {
+ case 0:
+ start = end = OCTEON_IRQ_UART0;
+ break;
+ case 1:
+ start = end = OCTEON_IRQ_UART1;
+ break;
+ default:
+ return (NULL);
+ }
+ rm = &sc->oba_irq_rman;
+ break;
+ case SYS_RES_MEMORY:
+ return (NULL);
+ case SYS_RES_IOPORT:
+ rm = &sc->oba_rman;
+ bt = &octeon_uart_tag;
+ bh = CVMX_MIO_UARTX_RBR(device_get_unit(child));
+ start = bh;
+ break;
+ default:
+ return (NULL);
+ }
+
+ rv = rman_reserve_resource(rm, start, end, count, flags, child);
+ if (rv == NULL) {
+ return (NULL);
+ }
+ if (type == SYS_RES_IRQ) {
+ return (rv);
+ }
+ rman_set_rid(rv, *rid);
+ rman_set_bustag(rv, bt);
+ rman_set_bushandle(rv, bh);
+
+ if (0) {
+ if (bus_activate_resource(child, type, *rid, rv)) {
+ rman_release_resource(rv);
+ return (NULL);
+ }
+ }
+ return (rv);
+
+}
+
+static int
+obio_activate_resource(device_t bus, device_t child, int type, int rid,
+ struct resource *r)
+{
+ return (0);
+}
+static device_method_t obio_methods[] = {
+ /* Device methods */
+ DEVMETHOD(device_identify, obio_identify),
+ DEVMETHOD(device_probe, obio_probe),
+ DEVMETHOD(device_attach, obio_attach),
+
+ /* Bus methods */
+ DEVMETHOD(bus_alloc_resource, obio_alloc_resource),
+ DEVMETHOD(bus_activate_resource,obio_activate_resource),
+ DEVMETHOD(bus_setup_intr, bus_generic_setup_intr),
+ DEVMETHOD(bus_teardown_intr, bus_generic_teardown_intr),
+
+ DEVMETHOD(bus_add_child, bus_generic_add_child),
+
+ {0, 0},
+};
+
+static driver_t obio_driver = {
+ "obio",
+ obio_methods,
+ sizeof(struct obio_softc),
+};
+static devclass_t obio_devclass;
+
+DRIVER_MODULE(obio, ciu, obio_driver, obio_devclass, 0, 0);
Property changes on: trunk/sys/mips/cavium/obio.c
___________________________________________________________________
Added: svn:eol-style
## -0,0 +1 ##
+native
\ No newline at end of property
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## -0,0 +1 ##
+MidnightBSD=%H
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+text/plain
\ No newline at end of property
Added: trunk/sys/mips/cavium/obiovar.h
===================================================================
--- trunk/sys/mips/cavium/obiovar.h (rev 0)
+++ trunk/sys/mips/cavium/obiovar.h 2018-05-26 21:55:02 UTC (rev 9987)
@@ -0,0 +1,56 @@
+/* $MidnightBSD$ */
+/* $NetBSD: obiovar.h,v 1.4 2003/06/16 17:40:53 thorpej Exp $ */
+
+/*-
+ * Copyright (c) 2002, 2003 Wasabi Systems, Inc.
+ * All rights reserved.
+ *
+ * Written by Jason R. Thorpe for Wasabi Systems, Inc.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * 3. All advertising materials mentioning features or use of this software
+ * must display the following acknowledgement:
+ * This product includes software developed for the NetBSD Project by
+ * Wasabi Systems, Inc.
+ * 4. The name of Wasabi Systems, Inc. may not be used to endorse
+ * or promote products derived from this software without specific prior
+ * written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * $FreeBSD: stable/10/sys/mips/cavium/obiovar.h 203128 2010-01-28 20:38:52Z imp $
+ *
+ */
+
+#ifndef _OCTEON_OBIOVAR_H_
+#define _OCTEON_OBIOVAR_H_
+
+#include <sys/rman.h>
+
+struct obio_softc {
+ bus_space_tag_t oba_st; /* bus space tag */
+ bus_addr_t oba_addr; /* address of device */
+ bus_size_t oba_size; /* size of device */
+ struct rman oba_rman;
+ struct rman oba_irq_rman;
+
+};
+
+#endif /* _OCTEON_OBIOVAR_H_ */
Property changes on: trunk/sys/mips/cavium/obiovar.h
___________________________________________________________________
Added: svn:eol-style
## -0,0 +1 ##
+native
\ No newline at end of property
Added: svn:keywords
## -0,0 +1 ##
+MidnightBSD=%H
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+text/plain
\ No newline at end of property
Added: trunk/sys/mips/cavium/octe/cavium-ethernet.h
===================================================================
--- trunk/sys/mips/cavium/octe/cavium-ethernet.h (rev 0)
+++ trunk/sys/mips/cavium/octe/cavium-ethernet.h 2018-05-26 21:55:02 UTC (rev 9987)
@@ -0,0 +1,100 @@
+/* $MidnightBSD$ */
+/*************************************************************************
+Copyright (c) 2003-2007 Cavium Networks (support at cavium.com). All rights
+reserved.
+
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are
+met:
+
+ * Redistributions of source code must retain the above copyright
+ notice, this list of conditions and the following disclaimer.
+
+ * Redistributions in binary form must reproduce the above
+ copyright notice, this list of conditions and the following
+ disclaimer in the documentation and/or other materials provided
+ with the distribution.
+
+ * Neither the name of Cavium Networks nor the names of
+ its contributors may be used to endorse or promote products
+ derived from this software without specific prior written
+ permission.
+
+This Software, including technical data, may be subject to U.S. export control laws, including the U.S. Export Administration Act and its associated regulations, and may be subject to export or import regulations in other countries.
+
+TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
+AND WITH ALL FAULTS AND CAVIUM NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES OF TITLE, MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR PURPOSE, LACK OF VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET POSSESSION OR CORRESPONDENCE TO DESCRIPTION. THE ENTIRE RISK ARISING OUT OF USE OR PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
+
+*************************************************************************/
+/* $FreeBSD: stable/10/sys/mips/cavium/octe/cavium-ethernet.h 213762 2010-10-13 09:17:44Z jmallett $ */
+
+/**
+ * @file
+ * External interface for the Cavium Octeon ethernet driver.
+ *
+ * $Id: cavium-ethernet.h 41589 2009-03-19 19:58:58Z cchavva $
+ *
+ */
+#ifndef CAVIUM_ETHERNET_H
+#define CAVIUM_ETHERNET_H
+
+#include <net/if_media.h>
+
+/**
+ * This is the definition of the Ethernet driver's private
+ * driver state stored in ifp->if_softc.
+ */
+typedef struct {
+ /* XXX FreeBSD device softcs must start with an ifnet pointer. */
+ struct ifnet *ifp;
+
+ int port; /* PKO hardware output port */
+ int queue; /* PKO hardware queue for the port */
+ int fau; /* Hardware fetch and add to count outstanding tx buffers */
+ int imode; /* Type of port. This is one of the enums in cvmx_helper_interface_mode_t */
+#if 0
+ struct ifnet_stats stats; /* Device statistics */
+#endif
+ uint64_t link_info; /* Last negotiated link state */
+ void (*poll)(struct ifnet *ifp); /* Called periodically to check link status */
+
+ /*
+ * FreeBSD additions.
+ */
+ device_t dev;
+ device_t miibus;
+
+ int (*open)(struct ifnet *ifp);
+ int (*stop)(struct ifnet *ifp);
+
+ int (*init)(struct ifnet *ifp);
+ void (*uninit)(struct ifnet *ifp);
+
+ uint8_t mac[6];
+ int phy_id;
+ const char *phy_device;
+ int (*mdio_read)(struct ifnet *, int, int);
+ void (*mdio_write)(struct ifnet *, int, int, int);
+
+ struct ifqueue tx_free_queue[16];
+
+ int need_link_update;
+ struct task link_task;
+ struct ifmedia media;
+ int if_flags;
+
+ struct mtx tx_mtx;
+} cvm_oct_private_t;
+
+
+/**
+ * Free a work queue entry received in a intercept callback.
+ *
+ * @param work_queue_entry
+ * Work queue entry to free
+ * @return Zero on success, Negative on failure.
+ */
+int cvm_oct_free_work(void *work_queue_entry);
+
+#endif
Property changes on: trunk/sys/mips/cavium/octe/cavium-ethernet.h
___________________________________________________________________
Added: svn:eol-style
## -0,0 +1 ##
+native
\ No newline at end of property
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## -0,0 +1 ##
+MidnightBSD=%H
\ No newline at end of property
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## -0,0 +1 ##
+text/plain
\ No newline at end of property
Added: trunk/sys/mips/cavium/octe/ethernet-common.c
===================================================================
--- trunk/sys/mips/cavium/octe/ethernet-common.c (rev 0)
+++ trunk/sys/mips/cavium/octe/ethernet-common.c 2018-05-26 21:55:02 UTC (rev 9987)
@@ -0,0 +1,345 @@
+/* $MidnightBSD$ */
+/*************************************************************************
+Copyright (c) 2003-2007 Cavium Networks (support at cavium.com). All rights
+reserved.
+
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are
+met:
+
+ * Redistributions of source code must retain the above copyright
+ notice, this list of conditions and the following disclaimer.
+
+ * Redistributions in binary form must reproduce the above
+ copyright notice, this list of conditions and the following
+ disclaimer in the documentation and/or other materials provided
+ with the distribution.
+
+ * Neither the name of Cavium Networks nor the names of
+ its contributors may be used to endorse or promote products
+ derived from this software without specific prior written
+ permission.
+
+This Software, including technical data, may be subject to U.S. export control laws, including the U.S. Export Administration Act and its associated regulations, and may be subject to export or import regulations in other countries.
+
+TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
+AND WITH ALL FAULTS AND CAVIUM NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES OF TITLE, MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR PURPOSE, LACK OF VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET POSSESSION OR CORRESPONDENCE TO DESCRIPTION. THE ENTIRE RISK ARISING OUT OF USE OR PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
+
+*************************************************************************/
+
+#include <sys/cdefs.h>
+__FBSDID("$FreeBSD: stable/10/sys/mips/cavium/octe/ethernet-common.c 250192 2013-05-02 19:47:36Z imp $");
+
+#include <sys/param.h>
+#include <sys/systm.h>
+#include <sys/bus.h>
+#include <sys/endian.h>
+#include <sys/kernel.h>
+#include <sys/mbuf.h>
+#include <sys/socket.h>
+
+#include <net/ethernet.h>
+#include <net/if.h>
+
+#include "wrapper-cvmx-includes.h"
+#include "ethernet-headers.h"
+
+static uint64_t cvm_oct_mac_addr = 0;
+static uint32_t cvm_oct_mac_addr_offset = 0;
+
+/**
+ * Set the multicast list. Currently unimplemented.
+ *
+ * @param dev Device to work on
+ */
+void cvm_oct_common_set_multicast_list(struct ifnet *ifp)
+{
+ cvmx_gmxx_prtx_cfg_t gmx_cfg;
+ cvm_oct_private_t *priv = (cvm_oct_private_t *)ifp->if_softc;
+ int interface = INTERFACE(priv->port);
+ int index = INDEX(priv->port);
+
+ if ((interface < 2) && (cvmx_helper_interface_get_mode(interface) != CVMX_HELPER_INTERFACE_MODE_SPI)) {
+ cvmx_gmxx_rxx_adr_ctl_t control;
+ control.u64 = 0;
+ control.s.bcst = 1; /* Allow broadcast MAC addresses */
+
+ if (/*ifp->mc_list || */(ifp->if_flags&IFF_ALLMULTI) ||
+ (ifp->if_flags & IFF_PROMISC))
+ control.s.mcst = 2; /* Force accept multicast packets */
+ else
+ control.s.mcst = 1; /* Force reject multicat packets */
+
+ if (ifp->if_flags & IFF_PROMISC)
+ control.s.cam_mode = 0; /* Reject matches if promisc. Since CAM is shut off, should accept everything */
+ else
+ control.s.cam_mode = 1; /* Filter packets based on the CAM */
+
+ gmx_cfg.u64 = cvmx_read_csr(CVMX_GMXX_PRTX_CFG(index, interface));
+ cvmx_write_csr(CVMX_GMXX_PRTX_CFG(index, interface), gmx_cfg.u64 & ~1ull);
+
+ cvmx_write_csr(CVMX_GMXX_RXX_ADR_CTL(index, interface), control.u64);
+ if (ifp->if_flags&IFF_PROMISC)
+ cvmx_write_csr(CVMX_GMXX_RXX_ADR_CAM_EN(index, interface), 0);
+ else
+ cvmx_write_csr(CVMX_GMXX_RXX_ADR_CAM_EN(index, interface), 1);
+
+ cvmx_write_csr(CVMX_GMXX_PRTX_CFG(index, interface), gmx_cfg.u64);
+ }
+}
+
+
+/**
+ * Assign a MAC addres from the pool of available MAC addresses
+ * Can return as either a 64-bit value and/or 6 octets.
+ *
+ * @param macp Filled in with the assigned address if non-NULL
+ * @param octets Filled in with the assigned address if non-NULL
+ * @return Zero on success
+ */
+int cvm_assign_mac_address(uint64_t *macp, uint8_t *octets)
+{
+ /* Initialize from global MAC address base; fail if not set */
+ if (cvm_oct_mac_addr == 0) {
+ memcpy((uint8_t *)&cvm_oct_mac_addr + 2,
+ cvmx_sysinfo_get()->mac_addr_base, 6);
+
+ if (cvm_oct_mac_addr == 0)
+ return ENXIO;
+
+ cvm_oct_mac_addr_offset = cvmx_mgmt_port_num_ports();
+ cvm_oct_mac_addr += cvm_oct_mac_addr_offset;
+ }
+
+ if (cvm_oct_mac_addr_offset >= cvmx_sysinfo_get()->mac_addr_count)
+ return ENXIO; /* Out of addresses to assign */
+
+ if (macp)
+ *macp = cvm_oct_mac_addr;
+ if (octets)
+ memcpy(octets, (u_int8_t *)&cvm_oct_mac_addr + 2, 6);
+
+ cvm_oct_mac_addr++;
+ cvm_oct_mac_addr_offset++;
+
+ return 0;
+}
+
+/**
+ * Set the hardware MAC address for a device
+ *
+ * @param dev Device to change the MAC address for
+ * @param addr Address structure to change it too.
+ */
+void cvm_oct_common_set_mac_address(struct ifnet *ifp, const void *addr)
+{
+ cvm_oct_private_t *priv = (cvm_oct_private_t *)ifp->if_softc;
+ cvmx_gmxx_prtx_cfg_t gmx_cfg;
+ int interface = INTERFACE(priv->port);
+ int index = INDEX(priv->port);
+
+ memcpy(priv->mac, addr, 6);
+
+ if ((interface < 2) && (cvmx_helper_interface_get_mode(interface) != CVMX_HELPER_INTERFACE_MODE_SPI)) {
+ int i;
+ const uint8_t *ptr = addr;
+ uint64_t mac = 0;
+ for (i = 0; i < 6; i++)
+ mac = (mac<<8) | (uint64_t)(ptr[i]);
+
+ gmx_cfg.u64 = cvmx_read_csr(CVMX_GMXX_PRTX_CFG(index, interface));
+ cvmx_write_csr(CVMX_GMXX_PRTX_CFG(index, interface), gmx_cfg.u64 & ~1ull);
+
+ cvmx_write_csr(CVMX_GMXX_SMACX(index, interface), mac);
+ cvmx_write_csr(CVMX_GMXX_RXX_ADR_CAM0(index, interface), ptr[0]);
+ cvmx_write_csr(CVMX_GMXX_RXX_ADR_CAM1(index, interface), ptr[1]);
+ cvmx_write_csr(CVMX_GMXX_RXX_ADR_CAM2(index, interface), ptr[2]);
+ cvmx_write_csr(CVMX_GMXX_RXX_ADR_CAM3(index, interface), ptr[3]);
+ cvmx_write_csr(CVMX_GMXX_RXX_ADR_CAM4(index, interface), ptr[4]);
+ cvmx_write_csr(CVMX_GMXX_RXX_ADR_CAM5(index, interface), ptr[5]);
+ cvm_oct_common_set_multicast_list(ifp);
+ cvmx_write_csr(CVMX_GMXX_PRTX_CFG(index, interface), gmx_cfg.u64);
+ }
+}
+
+
+/**
+ * Change the link MTU. Unimplemented
+ *
+ * @param dev Device to change
+ * @param new_mtu The new MTU
+ * @return Zero on success
+ */
+int cvm_oct_common_change_mtu(struct ifnet *ifp, int new_mtu)
+{
+ cvm_oct_private_t *priv = (cvm_oct_private_t *)ifp->if_softc;
+ int interface = INTERFACE(priv->port);
+ int index = INDEX(priv->port);
+ int vlan_bytes = 4;
+
+ /* Limit the MTU to make sure the ethernet packets are between 64 bytes
+ and 65535 bytes */
+ if ((new_mtu + 14 + 4 + vlan_bytes < 64) || (new_mtu + 14 + 4 + vlan_bytes > 65392)) {
+ printf("MTU must be between %d and %d.\n", 64-14-4-vlan_bytes, 65392-14-4-vlan_bytes);
+ return -EINVAL;
+ }
+ ifp->if_mtu = new_mtu;
+
+ if ((interface < 2) && (cvmx_helper_interface_get_mode(interface) != CVMX_HELPER_INTERFACE_MODE_SPI)) {
+ int max_packet = new_mtu + 14 + 4 + vlan_bytes; /* Add ethernet header and FCS, and VLAN if configured. */
+
+ if (OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN58XX)) {
+ /* Signal errors on packets larger than the MTU */
+ cvmx_write_csr(CVMX_GMXX_RXX_FRM_MAX(index, interface), max_packet);
+ } else {
+ /* Set the hardware to truncate packets larger than the MTU and
+ smaller the 64 bytes */
+ cvmx_pip_frm_len_chkx_t frm_len_chk;
+ frm_len_chk.u64 = 0;
+ frm_len_chk.s.minlen = 64;
+ frm_len_chk.s.maxlen = max_packet;
+ cvmx_write_csr(CVMX_PIP_FRM_LEN_CHKX(interface), frm_len_chk.u64);
+ }
+ /* Set the hardware to truncate packets larger than the MTU. The
+ jabber register must be set to a multiple of 8 bytes, so round up */
+ cvmx_write_csr(CVMX_GMXX_RXX_JABBER(index, interface), (max_packet + 7) & ~7u);
+ }
+ return 0;
+}
+
+
+/**
+ * Enable port.
+ */
+int cvm_oct_common_open(struct ifnet *ifp)
+{
+ cvmx_gmxx_prtx_cfg_t gmx_cfg;
+ cvm_oct_private_t *priv = (cvm_oct_private_t *)ifp->if_softc;
+ int interface = INTERFACE(priv->port);
+ int index = INDEX(priv->port);
+ cvmx_helper_link_info_t link_info;
+
+ gmx_cfg.u64 = cvmx_read_csr(CVMX_GMXX_PRTX_CFG(index, interface));
+ gmx_cfg.s.en = 1;
+ cvmx_write_csr(CVMX_GMXX_PRTX_CFG(index, interface), gmx_cfg.u64);
+
+ /*
+ * Set the link state unless we are using MII.
+ */
+ if (cvmx_sysinfo_get()->board_type != CVMX_BOARD_TYPE_SIM && priv->miibus == NULL) {
+ link_info = cvmx_helper_link_get(priv->port);
+ if (!link_info.s.link_up)
+ if_link_state_change(ifp, LINK_STATE_DOWN);
+ else
+ if_link_state_change(ifp, LINK_STATE_UP);
+ }
+
+ return 0;
+}
+
+
+/**
+ * Disable port.
+ */
+int cvm_oct_common_stop(struct ifnet *ifp)
+{
+ cvmx_gmxx_prtx_cfg_t gmx_cfg;
+ cvm_oct_private_t *priv = (cvm_oct_private_t *)ifp->if_softc;
+ int interface = INTERFACE(priv->port);
+ int index = INDEX(priv->port);
+
+ gmx_cfg.u64 = cvmx_read_csr(CVMX_GMXX_PRTX_CFG(index, interface));
+ gmx_cfg.s.en = 0;
+ cvmx_write_csr(CVMX_GMXX_PRTX_CFG(index, interface), gmx_cfg.u64);
+ return 0;
+}
+
+/**
+ * Poll for link status change.
+ */
+void cvm_oct_common_poll(struct ifnet *ifp)
+{
+ cvm_oct_private_t *priv = (cvm_oct_private_t *)ifp->if_softc;
+ cvmx_helper_link_info_t link_info;
+
+ /*
+ * If this is a simulation, do nothing.
+ */
+ if (cvmx_sysinfo_get()->board_type == CVMX_BOARD_TYPE_SIM)
+ return;
+
+ /*
+ * If there is a device-specific poll method, use it.
+ */
+ if (priv->poll != NULL) {
+ priv->poll(ifp);
+ return;
+ }
+
+ /*
+ * If an MII bus is attached, don't use the Simple Executive's link
+ * state routines.
+ */
+ if (priv->miibus != NULL)
+ return;
+
+ /*
+ * Use the Simple Executive's link state routines.
+ */
+ link_info = cvmx_helper_link_get(priv->port);
+ if (link_info.u64 == priv->link_info)
+ return;
+
+ link_info = cvmx_helper_link_autoconf(priv->port);
+ priv->link_info = link_info.u64;
+ priv->need_link_update = 1;
+}
+
+
+/**
+ * Per network device initialization
+ *
+ * @param dev Device to initialize
+ * @return Zero on success
+ */
+int cvm_oct_common_init(struct ifnet *ifp)
+{
+ uint8_t mac[6];
+ cvm_oct_private_t *priv = (cvm_oct_private_t *)ifp->if_softc;
+
+ if (cvm_assign_mac_address(NULL, mac) != 0)
+ return ENXIO;
+
+ ifp->if_mtu = ETHERMTU;
+
+ cvm_oct_mdio_setup_device(ifp);
+
+ cvm_oct_common_set_mac_address(ifp, mac);
+ cvm_oct_common_change_mtu(ifp, ifp->if_mtu);
+
+ /*
+ * Do any last-minute board-specific initialization.
+ */
+ switch (cvmx_sysinfo_get()->board_type) {
+#if defined(OCTEON_VENDOR_LANNER)
+ case CVMX_BOARD_TYPE_CUST_LANNER_MR320:
+ case CVMX_BOARD_TYPE_CUST_LANNER_MR321X:
+ if (priv->phy_id == 16)
+ cvm_oct_mv88e61xx_setup_device(ifp);
+ break;
+#endif
+ default:
+ break;
+ }
+
+ device_attach(priv->dev);
+
+ return 0;
+}
+
+void cvm_oct_common_uninit(struct ifnet *ifp)
+{
+ /* Currently nothing to do */
+}
+
Property changes on: trunk/sys/mips/cavium/octe/ethernet-common.c
___________________________________________________________________
Added: svn:eol-style
## -0,0 +1 ##
+native
\ No newline at end of property
Added: svn:keywords
## -0,0 +1 ##
+MidnightBSD=%H
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+text/plain
\ No newline at end of property
Added: trunk/sys/mips/cavium/octe/ethernet-common.h
===================================================================
--- trunk/sys/mips/cavium/octe/ethernet-common.h (rev 0)
+++ trunk/sys/mips/cavium/octe/ethernet-common.h 2018-05-26 21:55:02 UTC (rev 9987)
@@ -0,0 +1,56 @@
+/* $MidnightBSD$ */
+/*************************************************************************
+Copyright (c) 2003-2007 Cavium Networks (support at cavium.com). All rights
+reserved.
+
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are
+met:
+
+ * Redistributions of source code must retain the above copyright
+ notice, this list of conditions and the following disclaimer.
+
+ * Redistributions in binary form must reproduce the above
+ copyright notice, this list of conditions and the following
+ disclaimer in the documentation and/or other materials provided
+ with the distribution.
+
+ * Neither the name of Cavium Networks nor the names of
+ its contributors may be used to endorse or promote products
+ derived from this software without specific prior written
+ permission.
+
+This Software, including technical data, may be subject to U.S. export control laws, including the U.S. Export Administration Act and its associated regulations, and may be subject to export or import regulations in other countries.
+
+TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
+AND WITH ALL FAULTS AND CAVIUM NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES OF TITLE, MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR PURPOSE, LACK OF VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET POSSESSION OR CORRESPONDENCE TO DESCRIPTION. THE ENTIRE RISK ARISING OUT OF USE OR PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
+
+*************************************************************************/
+/* $FreeBSD: stable/10/sys/mips/cavium/octe/ethernet-common.h 231987 2012-02-22 01:30:25Z gonzo $ */
+
+int cvm_oct_common_open(struct ifnet *ifp);
+int cvm_oct_common_stop(struct ifnet *ifp);
+void cvm_oct_common_poll(struct ifnet *ifp);
+int cvm_oct_common_init(struct ifnet *ifp);
+void cvm_oct_common_uninit(struct ifnet *ifp);
+
+int cvm_oct_common_change_mtu(struct ifnet *ifp, int new_mtu);
+void cvm_oct_common_set_multicast_list(struct ifnet *ifp);
+void cvm_oct_common_set_mac_address(struct ifnet *ifp, const void *);
+int cvm_assign_mac_address(uint64_t *, uint8_t *);
+
+int cvm_oct_init_module(device_t);
+void cvm_oct_cleanup_module(device_t);
+
+/*
+ * XXX/juli
+ * These belong elsewhere but we can't stomach the nested extern.
+ */
+int cvm_oct_rgmii_init(struct ifnet *ifp);
+void cvm_oct_rgmii_uninit(struct ifnet *ifp);
+int cvm_oct_sgmii_init(struct ifnet *ifp);
+int cvm_oct_spi_init(struct ifnet *ifp);
+void cvm_oct_spi_uninit(struct ifnet *ifp);
+int cvm_oct_xaui_init(struct ifnet *ifp);
+
Property changes on: trunk/sys/mips/cavium/octe/ethernet-common.h
___________________________________________________________________
Added: svn:eol-style
## -0,0 +1 ##
+native
\ No newline at end of property
Added: svn:keywords
## -0,0 +1 ##
+MidnightBSD=%H
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+text/plain
\ No newline at end of property
Added: trunk/sys/mips/cavium/octe/ethernet-defines.h
===================================================================
--- trunk/sys/mips/cavium/octe/ethernet-defines.h (rev 0)
+++ trunk/sys/mips/cavium/octe/ethernet-defines.h 2018-05-26 21:55:02 UTC (rev 9987)
@@ -0,0 +1,52 @@
+/* $MidnightBSD$ */
+/*************************************************************************
+Copyright (c) 2003-2007 Cavium Networks (support at cavium.com). All rights
+reserved.
+
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are
+met:
+
+ * Redistributions of source code must retain the above copyright
+ notice, this list of conditions and the following disclaimer.
+
+ * Redistributions in binary form must reproduce the above
+ copyright notice, this list of conditions and the following
+ disclaimer in the documentation and/or other materials provided
+ with the distribution.
+
+ * Neither the name of Cavium Networks nor the names of
+ its contributors may be used to endorse or promote products
+ derived from this software without specific prior written
+ permission.
+
+This Software, including technical data, may be subject to U.S. export control laws, including the U.S. Export Administration Act and its associated regulations, and may be subject to export or import regulations in other countries.
+
+TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
+AND WITH ALL FAULTS AND CAVIUM NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES OF TITLE, MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR PURPOSE, LACK OF VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET POSSESSION OR CORRESPONDENCE TO DESCRIPTION. THE ENTIRE RISK ARISING OUT OF USE OR PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
+
+*************************************************************************/
+/* $FreeBSD: stable/10/sys/mips/cavium/octe/ethernet-defines.h 217664 2011-01-20 23:34:59Z jmallett $ */
+
+/*
+ * A few defines are used to control the operation of this driver:
+ * CONFIG_CAVIUM_OCTEON_NUM_PACKET_BUFFERS
+ * This kernel config option allows the user to control the number of
+ * packet and work queue buffers allocated by the driver. If this is zero,
+ * the driver uses the default from below.
+ */
+
+#define INTERRUPT_LIMIT 10000 /* Max interrupts per second per core */
+/*#define INTERRUPT_LIMIT 0 *//* Don't limit the number of interrupts */
+#define USE_RED 1 /* Enable Random Early Dropping under load */
+#define USE_10MBPS_PREAMBLE_WORKAROUND 1 /* Allow SW based preamble removal at 10Mbps to workaround PHYs giving us bad preambles */
+#define DONT_WRITEBACK(x) (x) /* Use this to have all FPA frees also tell the L2 not to write data to memory */
+/*#define DONT_WRITEBACK(x) 0 *//* Use this to not have FPA frees control L2 */
+
+#define MAX_RX_PACKETS 120 /* Maximum number of packets to process per interrupt. */
+#define MAX_OUT_QUEUE_DEPTH 1000
+
+#define FAU_NUM_PACKET_BUFFERS_TO_FREE (CVMX_FAU_REG_END - sizeof(uint32_t))
+#define TOTAL_NUMBER_OF_PORTS (CVMX_PIP_NUM_INPUT_PORTS+1)
+
Property changes on: trunk/sys/mips/cavium/octe/ethernet-defines.h
___________________________________________________________________
Added: svn:eol-style
## -0,0 +1 ##
+native
\ No newline at end of property
Added: svn:keywords
## -0,0 +1 ##
+MidnightBSD=%H
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+text/plain
\ No newline at end of property
Added: trunk/sys/mips/cavium/octe/ethernet-headers.h
===================================================================
--- trunk/sys/mips/cavium/octe/ethernet-headers.h (rev 0)
+++ trunk/sys/mips/cavium/octe/ethernet-headers.h 2018-05-26 21:55:02 UTC (rev 9987)
@@ -0,0 +1,51 @@
+/* $MidnightBSD$ */
+/*************************************************************************
+Copyright (c) 2003-2007 Cavium Networks (support at cavium.com). All rights
+reserved.
+
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are
+met:
+
+ * Redistributions of source code must retain the above copyright
+ notice, this list of conditions and the following disclaimer.
+
+ * Redistributions in binary form must reproduce the above
+ copyright notice, this list of conditions and the following
+ disclaimer in the documentation and/or other materials provided
+ with the distribution.
+
+ * Neither the name of Cavium Networks nor the names of
+ its contributors may be used to endorse or promote products
+ derived from this software without specific prior written
+ permission.
+
+This Software, including technical data, may be subject to U.S. export control laws, including the U.S. Export Administration Act and its associated regulations, and may be subject to export or import regulations in other countries.
+
+TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
+AND WITH ALL FAULTS AND CAVIUM NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES OF TITLE, MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR PURPOSE, LACK OF VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET POSSESSION OR CORRESPONDENCE TO DESCRIPTION. THE ENTIRE RISK ARISING OUT OF USE OR PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
+
+*************************************************************************/
+/* $FreeBSD: stable/10/sys/mips/cavium/octe/ethernet-headers.h 213346 2010-10-02 05:43:17Z jmallett $ */
+
+#ifndef __ETHERNET_HEADERS_H__
+#define __ETHERNET_HEADERS_H__
+
+#include "cavium-ethernet.h"
+#include "ethernet-common.h"
+#include "ethernet-defines.h"
+#include "ethernet-mdio.h"
+#include "ethernet-mem.h"
+#include "ethernet-rx.h"
+#include "ethernet-tx.h"
+#include "ethernet-util.h"
+
+/*
+ * Any board- or vendor-specific includes.
+ */
+#ifdef OCTEON_VENDOR_LANNER
+#include "ethernet-mv88e61xx.h"
+#endif
+
+#endif
Property changes on: trunk/sys/mips/cavium/octe/ethernet-headers.h
___________________________________________________________________
Added: svn:eol-style
## -0,0 +1 ##
+native
\ No newline at end of property
Added: svn:keywords
## -0,0 +1 ##
+MidnightBSD=%H
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+text/plain
\ No newline at end of property
Added: trunk/sys/mips/cavium/octe/ethernet-mdio.c
===================================================================
--- trunk/sys/mips/cavium/octe/ethernet-mdio.c (rev 0)
+++ trunk/sys/mips/cavium/octe/ethernet-mdio.c 2018-05-26 21:55:02 UTC (rev 9987)
@@ -0,0 +1,134 @@
+/* $MidnightBSD$ */
+/*************************************************************************
+Copyright (c) 2003-2007 Cavium Networks (support at cavium.com). All rights
+reserved.
+
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are
+met:
+
+ * Redistributions of source code must retain the above copyright
+ notice, this list of conditions and the following disclaimer.
+
+ * Redistributions in binary form must reproduce the above
+ copyright notice, this list of conditions and the following
+ disclaimer in the documentation and/or other materials provided
+ with the distribution.
+
+ * Neither the name of Cavium Networks nor the names of
+ its contributors may be used to endorse or promote products
+ derived from this software without specific prior written
+ permission.
+
+This Software, including technical data, may be subject to U.S. export control laws, including the U.S. Export Administration Act and its associated regulations, and may be subject to export or import regulations in other countries.
+
+TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
+AND WITH ALL FAULTS AND CAVIUM NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES OF TITLE, MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR PURPOSE, LACK OF VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET POSSESSION OR CORRESPONDENCE TO DESCRIPTION. THE ENTIRE RISK ARISING OUT OF USE OR PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
+
+*************************************************************************/
+
+#include <sys/cdefs.h>
+__FBSDID("$FreeBSD: stable/10/sys/mips/cavium/octe/ethernet-mdio.c 215974 2010-11-28 05:57:24Z jmallett $");
+
+#include <sys/param.h>
+#include <sys/systm.h>
+#include <sys/bus.h>
+#include <sys/endian.h>
+#include <sys/kernel.h>
+#include <sys/mbuf.h>
+#include <sys/socket.h>
+#include <sys/lock.h>
+#include <sys/mutex.h>
+
+#include <net/ethernet.h>
+#include <net/if.h>
+
+#include "wrapper-cvmx-includes.h"
+#include "ethernet-headers.h"
+
+struct mtx cvm_oct_mdio_mtx;
+MTX_SYSINIT(cvm_oct_mdio, &cvm_oct_mdio_mtx, "MDIO", MTX_DEF);
+
+/**
+ * Perform an MII read. Called by the generic MII routines
+ *
+ * @param dev Device to perform read for
+ * @param phy_id The MII phy id
+ * @param location Register location to read
+ * @return Result from the read or zero on failure
+ */
+int cvm_oct_mdio_read(struct ifnet *ifp, int phy_id, int location)
+{
+ cvmx_smi_cmd_t smi_cmd;
+ cvmx_smi_rd_dat_t smi_rd;
+
+ MDIO_LOCK();
+ smi_cmd.u64 = 0;
+ smi_cmd.s.phy_op = 1;
+ smi_cmd.s.phy_adr = phy_id;
+ smi_cmd.s.reg_adr = location;
+ cvmx_write_csr(CVMX_SMI_CMD, smi_cmd.u64);
+
+ do {
+ smi_rd.u64 = cvmx_read_csr(CVMX_SMI_RD_DAT);
+ } while (smi_rd.s.pending);
+
+ MDIO_UNLOCK();
+
+ if (smi_rd.s.val)
+ return smi_rd.s.dat;
+ else
+ return 0;
+}
+
+
+/**
+ * Perform an MII write. Called by the generic MII routines
+ *
+ * @param dev Device to perform write for
+ * @param phy_id The MII phy id
+ * @param location Register location to write
+ * @param val Value to write
+ */
+void cvm_oct_mdio_write(struct ifnet *ifp, int phy_id, int location, int val)
+{
+ cvmx_smi_cmd_t smi_cmd;
+ cvmx_smi_wr_dat_t smi_wr;
+
+ MDIO_LOCK();
+ smi_wr.u64 = 0;
+ smi_wr.s.dat = val;
+ cvmx_write_csr(CVMX_SMI_WR_DAT, smi_wr.u64);
+
+ smi_cmd.u64 = 0;
+ smi_cmd.s.phy_op = 0;
+ smi_cmd.s.phy_adr = phy_id;
+ smi_cmd.s.reg_adr = location;
+ cvmx_write_csr(CVMX_SMI_CMD, smi_cmd.u64);
+
+ do {
+ smi_wr.u64 = cvmx_read_csr(CVMX_SMI_WR_DAT);
+ } while (smi_wr.s.pending);
+ MDIO_UNLOCK();
+}
+
+/**
+ * Setup the MDIO device structures
+ *
+ * @param dev Device to setup
+ *
+ * @return Zero on success, negative on failure
+ */
+int cvm_oct_mdio_setup_device(struct ifnet *ifp)
+{
+ cvm_oct_private_t *priv = (cvm_oct_private_t *)ifp->if_softc;
+
+ priv->phy_id = cvmx_helper_board_get_mii_address(priv->port);
+ priv->phy_device = NULL;
+ priv->mdio_read = NULL;
+ priv->mdio_write = NULL;
+
+ return 0;
+}
+
Property changes on: trunk/sys/mips/cavium/octe/ethernet-mdio.c
___________________________________________________________________
Added: svn:eol-style
## -0,0 +1 ##
+native
\ No newline at end of property
Added: svn:keywords
## -0,0 +1 ##
+MidnightBSD=%H
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+text/plain
\ No newline at end of property
Added: trunk/sys/mips/cavium/octe/ethernet-mdio.h
===================================================================
--- trunk/sys/mips/cavium/octe/ethernet-mdio.h (rev 0)
+++ trunk/sys/mips/cavium/octe/ethernet-mdio.h 2018-05-26 21:55:02 UTC (rev 9987)
@@ -0,0 +1,41 @@
+/* $MidnightBSD$ */
+/*************************************************************************
+Copyright (c) 2003-2007 Cavium Networks (support at cavium.com). All rights
+reserved.
+
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are
+met:
+
+ * Redistributions of source code must retain the above copyright
+ notice, this list of conditions and the following disclaimer.
+
+ * Redistributions in binary form must reproduce the above
+ copyright notice, this list of conditions and the following
+ disclaimer in the documentation and/or other materials provided
+ with the distribution.
+
+ * Neither the name of Cavium Networks nor the names of
+ its contributors may be used to endorse or promote products
+ derived from this software without specific prior written
+ permission.
+
+This Software, including technical data, may be subject to U.S. export control laws, including the U.S. Export Administration Act and its associated regulations, and may be subject to export or import regulations in other countries.
+
+TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
+AND WITH ALL FAULTS AND CAVIUM NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES OF TITLE, MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR PURPOSE, LACK OF VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET POSSESSION OR CORRESPONDENCE TO DESCRIPTION. THE ENTIRE RISK ARISING OUT OF USE OR PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
+
+*************************************************************************/
+/* $FreeBSD: stable/10/sys/mips/cavium/octe/ethernet-mdio.h 210311 2010-07-20 19:25:11Z jmallett $ */
+
+extern struct mtx cvm_oct_mdio_mtx;
+
+#define MDIO_LOCK() mtx_lock(&cvm_oct_mdio_mtx)
+#define MDIO_UNLOCK() mtx_unlock(&cvm_oct_mdio_mtx)
+#define MDIO_TRYLOCK() mtx_trylock(&cvm_oct_mdio_mtx)
+
+int cvm_oct_mdio_read(struct ifnet *ifp, int phy_id, int location);
+void cvm_oct_mdio_write(struct ifnet *ifp, int phy_id, int location, int val);
+int cvm_oct_mdio_setup_device(struct ifnet *ifp);
+
Property changes on: trunk/sys/mips/cavium/octe/ethernet-mdio.h
___________________________________________________________________
Added: svn:eol-style
## -0,0 +1 ##
+native
\ No newline at end of property
Added: svn:keywords
## -0,0 +1 ##
+MidnightBSD=%H
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+text/plain
\ No newline at end of property
Added: trunk/sys/mips/cavium/octe/ethernet-mem.c
===================================================================
--- trunk/sys/mips/cavium/octe/ethernet-mem.c (rev 0)
+++ trunk/sys/mips/cavium/octe/ethernet-mem.c 2018-05-26 21:55:02 UTC (rev 9987)
@@ -0,0 +1,100 @@
+/* $MidnightBSD$ */
+/*************************************************************************
+Copyright (c) 2003-2007 Cavium Networks (support at cavium.com). All rights
+reserved.
+
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are
+met:
+
+ * Redistributions of source code must retain the above copyright
+ notice, this list of conditions and the following disclaimer.
+
+ * Redistributions in binary form must reproduce the above
+ copyright notice, this list of conditions and the following
+ disclaimer in the documentation and/or other materials provided
+ with the distribution.
+
+ * Neither the name of Cavium Networks nor the names of
+ its contributors may be used to endorse or promote products
+ derived from this software without specific prior written
+ permission.
+
+This Software, including technical data, may be subject to U.S. export control laws, including the U.S. Export Administration Act and its associated regulations, and may be subject to export or import regulations in other countries.
+
+TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
+AND WITH ALL FAULTS AND CAVIUM NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES OF TITLE, MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR PURPOSE, LACK OF VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET POSSESSION OR CORRESPONDENCE TO DESCRIPTION. THE ENTIRE RISK ARISING OUT OF USE OR PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
+
+*************************************************************************/
+
+#include <sys/cdefs.h>
+__FBSDID("$FreeBSD: stable/10/sys/mips/cavium/octe/ethernet-mem.c 243882 2012-12-05 08:04:20Z glebius $");
+
+#include <sys/param.h>
+#include <sys/systm.h>
+#include <sys/bus.h>
+#include <sys/endian.h>
+#include <sys/kernel.h>
+#include <sys/mbuf.h>
+#include <sys/socket.h>
+
+#include <net/ethernet.h>
+#include <net/if.h>
+
+#include "wrapper-cvmx-includes.h"
+#include "ethernet-headers.h"
+
+/**
+ * Fill the supplied hardware pool with mbufs
+ *
+ * @param pool Pool to allocate an mbuf for
+ * @param size Size of the buffer needed for the pool
+ * @param elements Number of buffers to allocate
+ */
+int cvm_oct_mem_fill_fpa(int pool, int size, int elements)
+{
+ int freed = elements;
+ while (freed) {
+ KASSERT(size <= MCLBYTES - 128, ("mbuf clusters are too small"));
+
+ struct mbuf *m = m_getcl(M_NOWAIT, MT_DATA, M_PKTHDR);
+ if (__predict_false(m == NULL)) {
+ printf("Failed to allocate mbuf for hardware pool %d\n", pool);
+ break;
+ }
+
+ m->m_data += 128 - (((uintptr_t)m->m_data) & 0x7f);
+ *(struct mbuf **)(m->m_data - sizeof(void *)) = m;
+ cvmx_fpa_free(m->m_data, pool, DONT_WRITEBACK(size/128));
+ freed--;
+ }
+ return (elements - freed);
+}
+
+
+/**
+ * Free the supplied hardware pool of mbufs
+ *
+ * @param pool Pool to allocate an mbuf for
+ * @param size Size of the buffer needed for the pool
+ * @param elements Number of buffers to allocate
+ */
+void cvm_oct_mem_empty_fpa(int pool, int size, int elements)
+{
+ char *memory;
+
+ do {
+ memory = cvmx_fpa_alloc(pool);
+ if (memory) {
+ struct mbuf *m = *(struct mbuf **)(memory - sizeof(void *));
+ elements--;
+ m_freem(m);
+ }
+ } while (memory);
+
+ if (elements < 0)
+ printf("Warning: Freeing of pool %u had too many mbufs (%d)\n", pool, elements);
+ else if (elements > 0)
+ printf("Warning: Freeing of pool %u is missing %d mbufs\n", pool, elements);
+}
Property changes on: trunk/sys/mips/cavium/octe/ethernet-mem.c
___________________________________________________________________
Added: svn:eol-style
## -0,0 +1 ##
+native
\ No newline at end of property
Added: svn:keywords
## -0,0 +1 ##
+MidnightBSD=%H
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+text/plain
\ No newline at end of property
Added: trunk/sys/mips/cavium/octe/ethernet-mem.h
===================================================================
--- trunk/sys/mips/cavium/octe/ethernet-mem.h (rev 0)
+++ trunk/sys/mips/cavium/octe/ethernet-mem.h 2018-05-26 21:55:02 UTC (rev 9987)
@@ -0,0 +1,34 @@
+/* $MidnightBSD$ */
+/*************************************************************************
+Copyright (c) 2003-2007 Cavium Networks (support at cavium.com). All rights
+reserved.
+
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are
+met:
+
+ * Redistributions of source code must retain the above copyright
+ notice, this list of conditions and the following disclaimer.
+
+ * Redistributions in binary form must reproduce the above
+ copyright notice, this list of conditions and the following
+ disclaimer in the documentation and/or other materials provided
+ with the distribution.
+
+ * Neither the name of Cavium Networks nor the names of
+ its contributors may be used to endorse or promote products
+ derived from this software without specific prior written
+ permission.
+
+This Software, including technical data, may be subject to U.S. export control laws, including the U.S. Export Administration Act and its associated regulations, and may be subject to export or import regulations in other countries.
+
+TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
+AND WITH ALL FAULTS AND CAVIUM NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES OF TITLE, MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR PURPOSE, LACK OF VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET POSSESSION OR CORRESPONDENCE TO DESCRIPTION. THE ENTIRE RISK ARISING OUT OF USE OR PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
+
+*************************************************************************/
+/* $FreeBSD: stable/10/sys/mips/cavium/octe/ethernet-mem.h 210311 2010-07-20 19:25:11Z jmallett $ */
+
+int cvm_oct_mem_fill_fpa(int pool, int size, int elements);
+void cvm_oct_mem_empty_fpa(int pool, int size, int elements);
+
Property changes on: trunk/sys/mips/cavium/octe/ethernet-mem.h
___________________________________________________________________
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Added: trunk/sys/mips/cavium/octe/ethernet-mv88e61xx.c
===================================================================
--- trunk/sys/mips/cavium/octe/ethernet-mv88e61xx.c (rev 0)
+++ trunk/sys/mips/cavium/octe/ethernet-mv88e61xx.c 2018-05-26 21:55:02 UTC (rev 9987)
@@ -0,0 +1,128 @@
+/* $MidnightBSD$ */
+/*-
+ * Copyright (c) 2010 Juli Mallett <jmallett at FreeBSD.org>
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ * $FreeBSD: stable/10/sys/mips/cavium/octe/ethernet-mv88e61xx.c 213762 2010-10-13 09:17:44Z jmallett $
+ */
+
+/*
+ * Interface to the Marvell 88E61XX SMI/MDIO.
+ */
+
+#include <sys/cdefs.h>
+__FBSDID("$FreeBSD: stable/10/sys/mips/cavium/octe/ethernet-mv88e61xx.c 213762 2010-10-13 09:17:44Z jmallett $");
+
+#include <sys/param.h>
+#include <sys/systm.h>
+#include <sys/bus.h>
+#include <sys/endian.h>
+#include <sys/kernel.h>
+#include <sys/mbuf.h>
+#include <sys/socket.h>
+
+#include <dev/mii/mii.h>
+
+#include <net/ethernet.h>
+#include <net/if.h>
+
+#include "wrapper-cvmx-includes.h"
+#include "ethernet-headers.h"
+
+#define MV88E61XX_SMI_REG_CMD 0x00 /* Indirect command register. */
+#define MV88E61XX_SMI_CMD_BUSY 0x8000 /* Busy bit. */
+#define MV88E61XX_SMI_CMD_22 0x1000 /* Clause 22 (default 45.) */
+#define MV88E61XX_SMI_CMD_READ 0x0800 /* Read command. */
+#define MV88E61XX_SMI_CMD_WRITE 0x0400 /* Write command. */
+#define MV88E61XX_SMI_CMD_PHY(phy) (((phy) & 0x1f) << 5)
+#define MV88E61XX_SMI_CMD_REG(reg) ((reg) & 0x1f)
+
+#define MV88E61XX_SMI_REG_DAT 0x01 /* Indirect data register. */
+
+static int cvm_oct_mv88e61xx_smi_read(struct ifnet *, int, int);
+static void cvm_oct_mv88e61xx_smi_write(struct ifnet *, int, int, int);
+static int cvm_oct_mv88e61xx_smi_wait(struct ifnet *);
+
+int
+cvm_oct_mv88e61xx_setup_device(struct ifnet *ifp)
+{
+ cvm_oct_private_t *priv = (cvm_oct_private_t *)ifp->if_softc;
+
+ priv->mdio_read = cvm_oct_mv88e61xx_smi_read;
+ priv->mdio_write = cvm_oct_mv88e61xx_smi_write;
+ priv->phy_device = "mv88e61xxphy";
+
+ return (0);
+}
+
+static int
+cvm_oct_mv88e61xx_smi_read(struct ifnet *ifp, int phy_id, int location)
+{
+ cvm_oct_private_t *priv = (cvm_oct_private_t *)ifp->if_softc;
+ int error;
+
+ error = cvm_oct_mv88e61xx_smi_wait(ifp);
+ if (error != 0)
+ return (0);
+
+ cvm_oct_mdio_write(ifp, priv->phy_id, MV88E61XX_SMI_REG_CMD,
+ MV88E61XX_SMI_CMD_BUSY | MV88E61XX_SMI_CMD_22 |
+ MV88E61XX_SMI_CMD_READ | MV88E61XX_SMI_CMD_PHY(phy_id) |
+ MV88E61XX_SMI_CMD_REG(location));
+
+ error = cvm_oct_mv88e61xx_smi_wait(ifp);
+ if (error != 0)
+ return (0);
+
+ return (cvm_oct_mdio_read(ifp, priv->phy_id, MV88E61XX_SMI_REG_DAT));
+}
+
+static void
+cvm_oct_mv88e61xx_smi_write(struct ifnet *ifp, int phy_id, int location, int val)
+{
+ cvm_oct_private_t *priv = (cvm_oct_private_t *)ifp->if_softc;
+
+ cvm_oct_mv88e61xx_smi_wait(ifp);
+ cvm_oct_mdio_write(ifp, priv->phy_id, MV88E61XX_SMI_REG_DAT, val);
+ cvm_oct_mdio_write(ifp, priv->phy_id, MV88E61XX_SMI_REG_CMD,
+ MV88E61XX_SMI_CMD_BUSY | MV88E61XX_SMI_CMD_22 |
+ MV88E61XX_SMI_CMD_WRITE | MV88E61XX_SMI_CMD_PHY(phy_id) |
+ MV88E61XX_SMI_CMD_REG(location));
+ cvm_oct_mv88e61xx_smi_wait(ifp);
+}
+
+static int
+cvm_oct_mv88e61xx_smi_wait(struct ifnet *ifp)
+{
+ cvm_oct_private_t *priv = (cvm_oct_private_t *)ifp->if_softc;
+ uint16_t cmd;
+ unsigned i;
+
+ for (i = 0; i < 10000; i++) {
+ cmd = cvm_oct_mdio_read(ifp, priv->phy_id, MV88E61XX_SMI_REG_CMD);
+ if ((cmd & MV88E61XX_SMI_CMD_BUSY) == 0)
+ return (0);
+ }
+ return (ETIMEDOUT);
+}
Property changes on: trunk/sys/mips/cavium/octe/ethernet-mv88e61xx.c
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Added: trunk/sys/mips/cavium/octe/ethernet-mv88e61xx.h
===================================================================
--- trunk/sys/mips/cavium/octe/ethernet-mv88e61xx.h (rev 0)
+++ trunk/sys/mips/cavium/octe/ethernet-mv88e61xx.h 2018-05-26 21:55:02 UTC (rev 9987)
@@ -0,0 +1,35 @@
+/* $MidnightBSD$ */
+/*-
+ * Copyright (c) 2010 Juli Mallett <jmallett at FreeBSD.org>
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ * $FreeBSD: stable/10/sys/mips/cavium/octe/ethernet-mv88e61xx.h 213346 2010-10-02 05:43:17Z jmallett $
+ */
+
+#ifndef _CAVIUM_OCTE_ETHERNET_MV88E61XX_H_
+#define _CAVIUM_OCTE_ETHERNET_MV88E61XX_H_
+
+int cvm_oct_mv88e61xx_setup_device(struct ifnet *ifp);
+
+#endif /* !_CAVIUM_OCTE_ETHERNET_MV88E61XX_H_ */
Property changes on: trunk/sys/mips/cavium/octe/ethernet-mv88e61xx.h
___________________________________________________________________
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Added: trunk/sys/mips/cavium/octe/ethernet-rgmii.c
===================================================================
--- trunk/sys/mips/cavium/octe/ethernet-rgmii.c (rev 0)
+++ trunk/sys/mips/cavium/octe/ethernet-rgmii.c 2018-05-26 21:55:02 UTC (rev 9987)
@@ -0,0 +1,308 @@
+/* $MidnightBSD$ */
+/*************************************************************************
+Copyright (c) 2003-2007 Cavium Networks (support at cavium.com). All rights
+reserved.
+
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are
+met:
+
+ * Redistributions of source code must retain the above copyright
+ notice, this list of conditions and the following disclaimer.
+
+ * Redistributions in binary form must reproduce the above
+ copyright notice, this list of conditions and the following
+ disclaimer in the documentation and/or other materials provided
+ with the distribution.
+
+ * Neither the name of Cavium Networks nor the names of
+ its contributors may be used to endorse or promote products
+ derived from this software without specific prior written
+ permission.
+
+This Software, including technical data, may be subject to U.S. export control laws, including the U.S. Export Administration Act and its associated regulations, and may be subject to export or import regulations in other countries.
+
+TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
+AND WITH ALL FAULTS AND CAVIUM NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES OF TITLE, MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR PURPOSE, LACK OF VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET POSSESSION OR CORRESPONDENCE TO DESCRIPTION. THE ENTIRE RISK ARISING OUT OF USE OR PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
+
+*************************************************************************/
+
+#include <sys/cdefs.h>
+__FBSDID("$FreeBSD: stable/10/sys/mips/cavium/octe/ethernet-rgmii.c 242346 2012-10-30 06:36:14Z jmallett $");
+
+#include <sys/param.h>
+#include <sys/systm.h>
+#include <sys/bus.h>
+#include <sys/endian.h>
+#include <sys/kernel.h>
+#include <sys/mbuf.h>
+#include <sys/rman.h>
+#include <sys/socket.h>
+#include <sys/lock.h>
+#include <sys/mutex.h>
+
+#include <net/ethernet.h>
+#include <net/if.h>
+
+#include "wrapper-cvmx-includes.h"
+#include "ethernet-headers.h"
+
+#include "octebusvar.h"
+
+extern struct ifnet *cvm_oct_device[];
+
+static struct mtx global_register_lock;
+MTX_SYSINIT(global_register_lock, &global_register_lock,
+ "RGMII Global", MTX_SPIN);
+
+static int number_rgmii_ports;
+
+static void cvm_oct_rgmii_poll(struct ifnet *ifp)
+{
+ cvm_oct_private_t *priv = (cvm_oct_private_t *)ifp->if_softc;
+ cvmx_helper_link_info_t link_info;
+
+ /* Take the global register lock since we are going to touch
+ registers that affect more than one port */
+ mtx_lock_spin(&global_register_lock);
+
+ link_info = cvmx_helper_link_get(priv->port);
+ if (link_info.u64 == priv->link_info) {
+
+ /* If the 10Mbps preamble workaround is supported and we're
+ at 10Mbps we may need to do some special checking */
+ if (USE_10MBPS_PREAMBLE_WORKAROUND && (link_info.s.speed == 10)) {
+
+ /* Read the GMXX_RXX_INT_REG[PCTERR] bit and
+ see if we are getting preamble errors */
+ int interface = INTERFACE(priv->port);
+ int index = INDEX(priv->port);
+ cvmx_gmxx_rxx_int_reg_t gmxx_rxx_int_reg;
+ gmxx_rxx_int_reg.u64 = cvmx_read_csr(CVMX_GMXX_RXX_INT_REG(index, interface));
+ if (gmxx_rxx_int_reg.s.pcterr) {
+
+ /* We are getting preamble errors at 10Mbps.
+ Most likely the PHY is giving us packets
+ with mis aligned preambles. In order to get
+ these packets we need to disable preamble
+ checking and do it in software */
+ cvmx_gmxx_rxx_frm_ctl_t gmxx_rxx_frm_ctl;
+ cvmx_ipd_sub_port_fcs_t ipd_sub_port_fcs;
+
+ /* Disable preamble checking */
+ gmxx_rxx_frm_ctl.u64 = cvmx_read_csr(CVMX_GMXX_RXX_FRM_CTL(index, interface));
+ gmxx_rxx_frm_ctl.s.pre_chk = 0;
+ cvmx_write_csr(CVMX_GMXX_RXX_FRM_CTL(index, interface), gmxx_rxx_frm_ctl.u64);
+
+ /* Disable FCS stripping */
+ ipd_sub_port_fcs.u64 = cvmx_read_csr(CVMX_IPD_SUB_PORT_FCS);
+ ipd_sub_port_fcs.s.port_bit &= 0xffffffffull ^ (1ull<<priv->port);
+ cvmx_write_csr(CVMX_IPD_SUB_PORT_FCS, ipd_sub_port_fcs.u64);
+
+ /* Clear any error bits */
+ cvmx_write_csr(CVMX_GMXX_RXX_INT_REG(index, interface), gmxx_rxx_int_reg.u64);
+ DEBUGPRINT("%s: Using 10Mbps with software preamble removal\n", if_name(ifp));
+ }
+ }
+ mtx_unlock_spin(&global_register_lock);
+ return;
+ }
+
+ /* If the 10Mbps preamble workaround is allowed we need to on
+ preamble checking, FCS stripping, and clear error bits on
+ every speed change. If errors occur during 10Mbps operation
+ the above code will change this stuff */
+ if (USE_10MBPS_PREAMBLE_WORKAROUND) {
+
+ cvmx_gmxx_rxx_frm_ctl_t gmxx_rxx_frm_ctl;
+ cvmx_ipd_sub_port_fcs_t ipd_sub_port_fcs;
+ cvmx_gmxx_rxx_int_reg_t gmxx_rxx_int_reg;
+ int interface = INTERFACE(priv->port);
+ int index = INDEX(priv->port);
+
+ /* Enable preamble checking */
+ gmxx_rxx_frm_ctl.u64 = cvmx_read_csr(CVMX_GMXX_RXX_FRM_CTL(index, interface));
+ gmxx_rxx_frm_ctl.s.pre_chk = 1;
+ cvmx_write_csr(CVMX_GMXX_RXX_FRM_CTL(index, interface), gmxx_rxx_frm_ctl.u64);
+ /* Enable FCS stripping */
+ ipd_sub_port_fcs.u64 = cvmx_read_csr(CVMX_IPD_SUB_PORT_FCS);
+ ipd_sub_port_fcs.s.port_bit |= 1ull<<priv->port;
+ cvmx_write_csr(CVMX_IPD_SUB_PORT_FCS, ipd_sub_port_fcs.u64);
+ /* Clear any error bits */
+ gmxx_rxx_int_reg.u64 = cvmx_read_csr(CVMX_GMXX_RXX_INT_REG(index, interface));
+ cvmx_write_csr(CVMX_GMXX_RXX_INT_REG(index, interface), gmxx_rxx_int_reg.u64);
+ }
+
+ if (priv->miibus == NULL) {
+ link_info = cvmx_helper_link_autoconf(priv->port);
+ priv->link_info = link_info.u64;
+ priv->need_link_update = 1;
+ }
+ mtx_unlock_spin(&global_register_lock);
+}
+
+
+static int cvm_oct_rgmii_rml_interrupt(void *dev_id)
+{
+ cvmx_npi_rsl_int_blocks_t rsl_int_blocks;
+ int index;
+ int return_status = FILTER_STRAY;
+
+ rsl_int_blocks.u64 = cvmx_read_csr(CVMX_NPI_RSL_INT_BLOCKS);
+
+ /* Check and see if this interrupt was caused by the GMX0 block */
+ if (rsl_int_blocks.s.gmx0) {
+
+ int interface = 0;
+ /* Loop through every port of this interface */
+ for (index = 0; index < cvmx_helper_ports_on_interface(interface); index++) {
+
+ /* Read the GMX interrupt status bits */
+ cvmx_gmxx_rxx_int_reg_t gmx_rx_int_reg;
+ gmx_rx_int_reg.u64 = cvmx_read_csr(CVMX_GMXX_RXX_INT_REG(index, interface));
+ gmx_rx_int_reg.u64 &= cvmx_read_csr(CVMX_GMXX_RXX_INT_EN(index, interface));
+ /* Poll the port if inband status changed */
+ if (gmx_rx_int_reg.s.phy_dupx || gmx_rx_int_reg.s.phy_link || gmx_rx_int_reg.s.phy_spd) {
+
+ struct ifnet *ifp = cvm_oct_device[cvmx_helper_get_ipd_port(interface, index)];
+ if (ifp)
+ cvm_oct_rgmii_poll(ifp);
+ gmx_rx_int_reg.u64 = 0;
+ gmx_rx_int_reg.s.phy_dupx = 1;
+ gmx_rx_int_reg.s.phy_link = 1;
+ gmx_rx_int_reg.s.phy_spd = 1;
+ cvmx_write_csr(CVMX_GMXX_RXX_INT_REG(index, interface), gmx_rx_int_reg.u64);
+ return_status = FILTER_HANDLED;
+ }
+ }
+ }
+
+ /* Check and see if this interrupt was caused by the GMX1 block */
+ if (rsl_int_blocks.s.gmx1) {
+
+ int interface = 1;
+ /* Loop through every port of this interface */
+ for (index = 0; index < cvmx_helper_ports_on_interface(interface); index++) {
+
+ /* Read the GMX interrupt status bits */
+ cvmx_gmxx_rxx_int_reg_t gmx_rx_int_reg;
+ gmx_rx_int_reg.u64 = cvmx_read_csr(CVMX_GMXX_RXX_INT_REG(index, interface));
+ gmx_rx_int_reg.u64 &= cvmx_read_csr(CVMX_GMXX_RXX_INT_EN(index, interface));
+ /* Poll the port if inband status changed */
+ if (gmx_rx_int_reg.s.phy_dupx || gmx_rx_int_reg.s.phy_link || gmx_rx_int_reg.s.phy_spd) {
+
+ struct ifnet *ifp = cvm_oct_device[cvmx_helper_get_ipd_port(interface, index)];
+ if (ifp)
+ cvm_oct_rgmii_poll(ifp);
+ gmx_rx_int_reg.u64 = 0;
+ gmx_rx_int_reg.s.phy_dupx = 1;
+ gmx_rx_int_reg.s.phy_link = 1;
+ gmx_rx_int_reg.s.phy_spd = 1;
+ cvmx_write_csr(CVMX_GMXX_RXX_INT_REG(index, interface), gmx_rx_int_reg.u64);
+ return_status = FILTER_HANDLED;
+ }
+ }
+ }
+ return return_status;
+}
+
+
+int cvm_oct_rgmii_init(struct ifnet *ifp)
+{
+ struct octebus_softc *sc;
+ cvm_oct_private_t *priv = (cvm_oct_private_t *)ifp->if_softc;
+ int error;
+ int rid;
+
+ if (cvm_oct_common_init(ifp) != 0)
+ return ENXIO;
+
+ priv->open = cvm_oct_common_open;
+ priv->stop = cvm_oct_common_stop;
+ priv->stop(ifp);
+
+ /* Due to GMX errata in CN3XXX series chips, it is necessary to take the
+ link down immediately whne the PHY changes state. In order to do this
+ we call the poll function every time the RGMII inband status changes.
+ This may cause problems if the PHY doesn't implement inband status
+ properly */
+ if (number_rgmii_ports == 0) {
+ sc = device_get_softc(device_get_parent(priv->dev));
+
+ rid = 0;
+ sc->sc_rgmii_irq = bus_alloc_resource(sc->sc_dev, SYS_RES_IRQ,
+ &rid, OCTEON_IRQ_RML,
+ OCTEON_IRQ_RML, 1,
+ RF_ACTIVE);
+ if (sc->sc_rgmii_irq == NULL) {
+ device_printf(sc->sc_dev, "could not allocate RGMII irq");
+ return ENXIO;
+ }
+
+ error = bus_setup_intr(sc->sc_dev, sc->sc_rgmii_irq,
+ INTR_TYPE_NET | INTR_MPSAFE,
+ cvm_oct_rgmii_rml_interrupt, NULL,
+ &number_rgmii_ports, NULL);
+ if (error != 0) {
+ device_printf(sc->sc_dev, "could not setup RGMII irq");
+ return error;
+ }
+ }
+ number_rgmii_ports++;
+
+ /* Only true RGMII ports need to be polled. In GMII mode, port 0 is really
+ a RGMII port */
+ if (((priv->imode == CVMX_HELPER_INTERFACE_MODE_GMII) && (priv->port == 0)) ||
+ (priv->imode == CVMX_HELPER_INTERFACE_MODE_RGMII)) {
+
+ if (cvmx_sysinfo_get()->board_type != CVMX_BOARD_TYPE_SIM) {
+
+ cvmx_gmxx_rxx_int_en_t gmx_rx_int_en;
+ int interface = INTERFACE(priv->port);
+ int index = INDEX(priv->port);
+
+ /* Enable interrupts on inband status changes for this port */
+ gmx_rx_int_en.u64 = cvmx_read_csr(CVMX_GMXX_RXX_INT_EN(index, interface));
+ gmx_rx_int_en.s.phy_dupx = 1;
+ gmx_rx_int_en.s.phy_link = 1;
+ gmx_rx_int_en.s.phy_spd = 1;
+ cvmx_write_csr(CVMX_GMXX_RXX_INT_EN(index, interface), gmx_rx_int_en.u64);
+ priv->poll = cvm_oct_rgmii_poll;
+ }
+ }
+
+ return 0;
+}
+
+void cvm_oct_rgmii_uninit(struct ifnet *ifp)
+{
+ cvm_oct_private_t *priv = (cvm_oct_private_t *)ifp->if_softc;
+ cvm_oct_common_uninit(ifp);
+
+ /* Only true RGMII ports need to be polled. In GMII mode, port 0 is really
+ a RGMII port */
+ if (((priv->imode == CVMX_HELPER_INTERFACE_MODE_GMII) && (priv->port == 0)) ||
+ (priv->imode == CVMX_HELPER_INTERFACE_MODE_RGMII)) {
+
+ if (cvmx_sysinfo_get()->board_type != CVMX_BOARD_TYPE_SIM) {
+
+ cvmx_gmxx_rxx_int_en_t gmx_rx_int_en;
+ int interface = INTERFACE(priv->port);
+ int index = INDEX(priv->port);
+
+ /* Disable interrupts on inband status changes for this port */
+ gmx_rx_int_en.u64 = cvmx_read_csr(CVMX_GMXX_RXX_INT_EN(index, interface));
+ gmx_rx_int_en.s.phy_dupx = 0;
+ gmx_rx_int_en.s.phy_link = 0;
+ gmx_rx_int_en.s.phy_spd = 0;
+ cvmx_write_csr(CVMX_GMXX_RXX_INT_EN(index, interface), gmx_rx_int_en.u64);
+ }
+ }
+
+ /* Remove the interrupt handler when the last port is removed */
+ number_rgmii_ports--;
+ if (number_rgmii_ports == 0)
+ panic("%s: need to implement IRQ release.", __func__);
+}
+
Property changes on: trunk/sys/mips/cavium/octe/ethernet-rgmii.c
___________________________________________________________________
Added: svn:eol-style
## -0,0 +1 ##
+native
\ No newline at end of property
Added: svn:keywords
## -0,0 +1 ##
+MidnightBSD=%H
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+text/plain
\ No newline at end of property
Added: trunk/sys/mips/cavium/octe/ethernet-rx.c
===================================================================
--- trunk/sys/mips/cavium/octe/ethernet-rx.c (rev 0)
+++ trunk/sys/mips/cavium/octe/ethernet-rx.c 2018-05-26 21:55:02 UTC (rev 9987)
@@ -0,0 +1,391 @@
+/* $MidnightBSD$ */
+/*************************************************************************
+Copyright (c) 2003-2007 Cavium Networks (support at cavium.com). All rights
+reserved.
+
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are
+met:
+
+ * Redistributions of source code must retain the above copyright
+ notice, this list of conditions and the following disclaimer.
+
+ * Redistributions in binary form must reproduce the above
+ copyright notice, this list of conditions and the following
+ disclaimer in the documentation and/or other materials provided
+ with the distribution.
+
+ * Neither the name of Cavium Networks nor the names of
+ its contributors may be used to endorse or promote products
+ derived from this software without specific prior written
+ permission.
+
+This Software, including technical data, may be subject to U.S. export control laws, including the U.S. Export Administration Act and its associated regulations, and may be subject to export or import regulations in other countries.
+
+TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
+AND WITH ALL FAULTS AND CAVIUM NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES OF TITLE, MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR PURPOSE, LACK OF VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET POSSESSION OR CORRESPONDENCE TO DESCRIPTION. THE ENTIRE RISK ARISING OUT OF USE OR PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
+
+*************************************************************************/
+
+#include <sys/cdefs.h>
+__FBSDID("$FreeBSD: stable/10/sys/mips/cavium/octe/ethernet-rx.c 243882 2012-12-05 08:04:20Z glebius $");
+
+#include <sys/param.h>
+#include <sys/systm.h>
+#include <sys/bus.h>
+#include <sys/endian.h>
+#include <sys/kernel.h>
+#include <sys/mbuf.h>
+#include <sys/socket.h>
+#include <sys/proc.h>
+#include <sys/sched.h>
+#include <sys/smp.h>
+#include <sys/taskqueue.h>
+
+#include <net/ethernet.h>
+#include <net/if.h>
+
+#include "wrapper-cvmx-includes.h"
+#include "ethernet-headers.h"
+
+extern int pow_receive_group;
+extern struct ifnet *cvm_oct_device[];
+
+static struct task cvm_oct_task;
+static struct taskqueue *cvm_oct_taskq;
+
+static int cvm_oct_rx_active;
+
+/**
+ * Interrupt handler. The interrupt occurs whenever the POW
+ * transitions from 0->1 packets in our group.
+ *
+ * @param cpl
+ * @param dev_id
+ * @param regs
+ * @return
+ */
+int cvm_oct_do_interrupt(void *dev_id)
+{
+ /* Acknowledge the interrupt */
+ if (INTERRUPT_LIMIT)
+ cvmx_write_csr(CVMX_POW_WQ_INT, 1<<pow_receive_group);
+ else
+ cvmx_write_csr(CVMX_POW_WQ_INT, 0x10001<<pow_receive_group);
+
+ /*
+ * Schedule task if there isn't one running.
+ */
+ if (atomic_cmpset_int(&cvm_oct_rx_active, 0, 1))
+ taskqueue_enqueue(cvm_oct_taskq, &cvm_oct_task);
+
+ return FILTER_HANDLED;
+}
+
+
+/**
+ * This is called on receive errors, and determines if the packet
+ * can be dropped early-on in cvm_oct_tasklet_rx().
+ *
+ * @param work Work queue entry pointing to the packet.
+ * @return Non-zero if the packet can be dropped, zero otherwise.
+ */
+static inline int cvm_oct_check_rcv_error(cvmx_wqe_t *work)
+{
+ if ((work->word2.snoip.err_code == 10) && (work->word1.s.len <= 64)) {
+ /* Ignore length errors on min size packets. Some equipment
+ incorrectly pads packets to 64+4FCS instead of 60+4FCS.
+ Note these packets still get counted as frame errors. */
+ } else
+ if (USE_10MBPS_PREAMBLE_WORKAROUND && ((work->word2.snoip.err_code == 5) || (work->word2.snoip.err_code == 7))) {
+
+ /* We received a packet with either an alignment error or a
+ FCS error. This may be signalling that we are running
+ 10Mbps with GMXX_RXX_FRM_CTL[PRE_CHK} off. If this is the
+ case we need to parse the packet to determine if we can
+ remove a non spec preamble and generate a correct packet */
+ int interface = cvmx_helper_get_interface_num(work->word1.cn38xx.ipprt);
+ int index = cvmx_helper_get_interface_index_num(work->word1.cn38xx.ipprt);
+ cvmx_gmxx_rxx_frm_ctl_t gmxx_rxx_frm_ctl;
+ gmxx_rxx_frm_ctl.u64 = cvmx_read_csr(CVMX_GMXX_RXX_FRM_CTL(index, interface));
+ if (gmxx_rxx_frm_ctl.s.pre_chk == 0) {
+
+ uint8_t *ptr = cvmx_phys_to_ptr(work->packet_ptr.s.addr);
+ int i = 0;
+
+ while (i < work->word1.s.len-1) {
+ if (*ptr != 0x55)
+ break;
+ ptr++;
+ i++;
+ }
+
+ if (*ptr == 0xd5) {
+ /*
+ DEBUGPRINT("Port %d received 0xd5 preamble\n", work->word1.cn38xx.ipprt);
+ */
+ work->packet_ptr.s.addr += i+1;
+ work->word1.s.len -= i+5;
+ } else
+ if ((*ptr & 0xf) == 0xd) {
+ /*
+ DEBUGPRINT("Port %d received 0x?d preamble\n", work->word1.cn38xx.ipprt);
+ */
+ work->packet_ptr.s.addr += i;
+ work->word1.s.len -= i+4;
+ for (i = 0; i < work->word1.s.len; i++) {
+ *ptr = ((*ptr&0xf0)>>4) | ((*(ptr+1)&0xf)<<4);
+ ptr++;
+ }
+ } else {
+ DEBUGPRINT("Port %d unknown preamble, packet dropped\n", work->word1.cn38xx.ipprt);
+ /*
+ cvmx_helper_dump_packet(work);
+ */
+ cvm_oct_free_work(work);
+ return 1;
+ }
+ }
+ } else {
+ DEBUGPRINT("Port %d receive error code %d, packet dropped\n", work->word1.cn38xx.ipprt, work->word2.snoip.err_code);
+ cvm_oct_free_work(work);
+ return 1;
+ }
+
+ return 0;
+}
+
+/**
+ * Tasklet function that is scheduled on a core when an interrupt occurs.
+ *
+ * @param unused
+ */
+void cvm_oct_tasklet_rx(void *context, int pending)
+{
+ int coreid;
+ uint64_t old_group_mask;
+ int rx_count = 0;
+ int number_to_free;
+ int num_freed;
+ int packet_not_copied;
+
+ sched_pin();
+ coreid = cvmx_get_core_num();
+
+ /* Prefetch cvm_oct_device since we know we need it soon */
+ CVMX_PREFETCH(cvm_oct_device, 0);
+
+ /* Only allow work for our group (and preserve priorities) */
+ old_group_mask = cvmx_read_csr(CVMX_POW_PP_GRP_MSKX(coreid));
+ cvmx_write_csr(CVMX_POW_PP_GRP_MSKX(coreid),
+ (old_group_mask & ~0xFFFFull) | 1<<pow_receive_group);
+
+ while (1) {
+ struct mbuf *m = NULL;
+ int mbuf_in_hw;
+ cvmx_wqe_t *work;
+
+ if ((INTERRUPT_LIMIT == 0) || (rx_count < MAX_RX_PACKETS))
+ work = cvmx_pow_work_request_sync(CVMX_POW_NO_WAIT);
+ else
+ work = NULL;
+ CVMX_PREFETCH(work, 0);
+ if (work == NULL)
+ break;
+
+ mbuf_in_hw = work->word2.s.bufs == 1;
+ if ((mbuf_in_hw)) {
+ m = *(struct mbuf **)(cvm_oct_get_buffer_ptr(work->packet_ptr) - sizeof(void *));
+ CVMX_PREFETCH(m, offsetof(struct mbuf, m_data));
+ CVMX_PREFETCH(m, offsetof(struct mbuf, m_pkthdr));
+ }
+ CVMX_PREFETCH(cvm_oct_device[work->word1.cn38xx.ipprt], 0);
+ //CVMX_PREFETCH(m, 0);
+
+
+ rx_count++;
+ /* Immediately throw away all packets with receive errors */
+ if ((work->word2.snoip.rcv_error)) {
+ if (cvm_oct_check_rcv_error(work))
+ continue;
+ }
+
+ /* We can only use the zero copy path if mbufs are in the FPA pool
+ and the packet fits in a single buffer */
+ if ((mbuf_in_hw)) {
+ CVMX_PREFETCH(m->m_data, 0);
+
+ m->m_pkthdr.len = m->m_len = work->word1.s.len;
+
+ packet_not_copied = 1;
+
+ /*
+ * Adjust the data pointer based on the offset
+ * of the packet within the buffer.
+ */
+ m->m_data += (work->packet_ptr.s.back << 7) + (work->packet_ptr.s.addr & 0x7f);
+ } else {
+
+ /* We have to copy the packet. First allocate an
+ mbuf for it */
+ MGETHDR(m, M_NOWAIT, MT_DATA);
+ if (m == NULL) {
+ DEBUGPRINT("Port %d failed to allocate mbuf, packet dropped\n", work->word1.cn38xx.ipprt);
+ cvm_oct_free_work(work);
+ continue;
+ }
+
+ /* Check if we've received a packet that was entirely
+ stored in the work entry. This is untested */
+ if ((work->word2.s.bufs == 0)) {
+ uint8_t *ptr = work->packet_data;
+
+ if (cvmx_likely(!work->word2.s.not_IP)) {
+ /* The beginning of the packet moves
+ for IP packets */
+ if (work->word2.s.is_v6)
+ ptr += 2;
+ else
+ ptr += 6;
+ }
+ panic("%s: not yet implemented; copy in small packet.", __func__);
+ /* No packet buffers to free */
+ } else {
+ int segments = work->word2.s.bufs;
+ cvmx_buf_ptr_t segment_ptr = work->packet_ptr;
+ int len = work->word1.s.len;
+
+ while (segments--) {
+ cvmx_buf_ptr_t next_ptr = *(cvmx_buf_ptr_t *)cvmx_phys_to_ptr(segment_ptr.s.addr-8);
+ /* Octeon Errata PKI-100: The segment
+ size is wrong. Until it is fixed,
+ calculate the segment size based on
+ the packet pool buffer size. When
+ it is fixed, the following line
+ should be replaced with this one:
+ int segment_size = segment_ptr.s.size; */
+ int segment_size = CVMX_FPA_PACKET_POOL_SIZE - (segment_ptr.s.addr - (((segment_ptr.s.addr >> 7) - segment_ptr.s.back) << 7));
+ /* Don't copy more than what is left
+ in the packet */
+ if (segment_size > len)
+ segment_size = len;
+ /* Copy the data into the packet */
+ panic("%s: not yet implemented; copy in packet segments.", __func__);
+#if 0
+ memcpy(m_put(m, segment_size), cvmx_phys_to_ptr(segment_ptr.s.addr), segment_size);
+#endif
+ /* Reduce the amount of bytes left
+ to copy */
+ len -= segment_size;
+ segment_ptr = next_ptr;
+ }
+ }
+ packet_not_copied = 0;
+ }
+
+ if (((work->word1.cn38xx.ipprt < TOTAL_NUMBER_OF_PORTS) &&
+ cvm_oct_device[work->word1.cn38xx.ipprt])) {
+ struct ifnet *ifp = cvm_oct_device[work->word1.cn38xx.ipprt];
+
+ /* Only accept packets for devices
+ that are currently up */
+ if ((ifp->if_flags & IFF_UP)) {
+ m->m_pkthdr.rcvif = ifp;
+
+ if ((ifp->if_capenable & IFCAP_RXCSUM) != 0) {
+ if ((work->word2.s.not_IP || work->word2.s.IP_exc || work->word2.s.L4_error))
+ m->m_pkthdr.csum_flags = 0; /* XXX */
+ else {
+ m->m_pkthdr.csum_flags = CSUM_IP_CHECKED | CSUM_IP_VALID | CSUM_DATA_VALID | CSUM_PSEUDO_HDR;
+ m->m_pkthdr.csum_data = 0xffff;
+ }
+ } else {
+ m->m_pkthdr.csum_flags = 0; /* XXX */
+ }
+
+ ifp->if_ipackets++;
+
+ (*ifp->if_input)(ifp, m);
+ } else {
+ /* Drop any packet received for a device that isn't up */
+ /*
+ DEBUGPRINT("%s: Device not up, packet dropped\n",
+ if_name(ifp));
+ */
+ m_freem(m);
+ }
+ } else {
+ /* Drop any packet received for a device that
+ doesn't exist */
+ DEBUGPRINT("Port %d not controlled by FreeBSD, packet dropped\n", work->word1.cn38xx.ipprt);
+ m_freem(m);
+ }
+
+ /* Check to see if the mbuf and work share
+ the same packet buffer */
+ if ((packet_not_copied)) {
+ /* This buffer needs to be replaced, increment
+ the number of buffers we need to free by one */
+ cvmx_fau_atomic_add32(
+ FAU_NUM_PACKET_BUFFERS_TO_FREE, 1);
+
+ cvmx_fpa_free(work, CVMX_FPA_WQE_POOL,
+ DONT_WRITEBACK(1));
+ } else
+ cvm_oct_free_work(work);
+ }
+
+ /*
+ * If we hit our limit, schedule another task while we clean up.
+ */
+ if (INTERRUPT_LIMIT != 0 && rx_count == MAX_RX_PACKETS) {
+ taskqueue_enqueue(cvm_oct_taskq, &cvm_oct_task);
+ } else {
+ /*
+ * No more packets, all done.
+ */
+ if (!atomic_cmpset_int(&cvm_oct_rx_active, 1, 0))
+ panic("%s: inconsistent rx active state.", __func__);
+ }
+
+ /* Restore the original POW group mask */
+ cvmx_write_csr(CVMX_POW_PP_GRP_MSKX(coreid), old_group_mask);
+
+ /* Refill the packet buffer pool */
+ number_to_free =
+ cvmx_fau_fetch_and_add32(FAU_NUM_PACKET_BUFFERS_TO_FREE, 0);
+
+ if (number_to_free > 0) {
+ cvmx_fau_atomic_add32(FAU_NUM_PACKET_BUFFERS_TO_FREE,
+ -number_to_free);
+ num_freed =
+ cvm_oct_mem_fill_fpa(CVMX_FPA_PACKET_POOL,
+ CVMX_FPA_PACKET_POOL_SIZE,
+ number_to_free);
+ if (num_freed != number_to_free) {
+ cvmx_fau_atomic_add32(FAU_NUM_PACKET_BUFFERS_TO_FREE,
+ number_to_free - num_freed);
+ }
+ }
+ sched_unpin();
+}
+
+
+
+void cvm_oct_rx_initialize(void)
+{
+ TASK_INIT(&cvm_oct_task, 0, cvm_oct_tasklet_rx, NULL);
+
+ cvm_oct_taskq = taskqueue_create_fast("oct_rx", M_NOWAIT,
+ taskqueue_thread_enqueue,
+ &cvm_oct_taskq);
+ taskqueue_start_threads(&cvm_oct_taskq, min(mp_ncpus, MAXCPU),
+ PI_NET, "octe taskq");
+}
+
+void cvm_oct_rx_shutdown(void)
+{
+ panic("%s: not yet implemented.", __func__);
+}
+
Property changes on: trunk/sys/mips/cavium/octe/ethernet-rx.c
___________________________________________________________________
Added: svn:eol-style
## -0,0 +1 ##
+native
\ No newline at end of property
Added: svn:keywords
## -0,0 +1 ##
+MidnightBSD=%H
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+text/plain
\ No newline at end of property
Added: trunk/sys/mips/cavium/octe/ethernet-rx.h
===================================================================
--- trunk/sys/mips/cavium/octe/ethernet-rx.h (rev 0)
+++ trunk/sys/mips/cavium/octe/ethernet-rx.h 2018-05-26 21:55:02 UTC (rev 9987)
@@ -0,0 +1,38 @@
+/* $MidnightBSD$ */
+/*************************************************************************
+Copyright (c) 2003-2007 Cavium Networks (support at cavium.com). All rights
+reserved.
+
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are
+met:
+
+ * Redistributions of source code must retain the above copyright
+ notice, this list of conditions and the following disclaimer.
+
+ * Redistributions in binary form must reproduce the above
+ copyright notice, this list of conditions and the following
+ disclaimer in the documentation and/or other materials provided
+ with the distribution.
+
+ * Neither the name of Cavium Networks nor the names of
+ its contributors may be used to endorse or promote products
+ derived from this software without specific prior written
+ permission.
+
+This Software, including technical data, may be subject to U.S. export control laws, including the U.S. Export Administration Act and its associated regulations, and may be subject to export or import regulations in other countries.
+
+TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
+AND WITH ALL FAULTS AND CAVIUM NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES OF TITLE, MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR PURPOSE, LACK OF VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET POSSESSION OR CORRESPONDENCE TO DESCRIPTION. THE ENTIRE RISK ARISING OUT OF USE OR PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
+
+*************************************************************************/
+/* $FreeBSD: stable/10/sys/mips/cavium/octe/ethernet-rx.h 210311 2010-07-20 19:25:11Z jmallett $ */
+
+int cvm_oct_do_interrupt(void *dev_id);
+void cvm_oct_poll_controller(struct ifnet *ifp);
+void cvm_oct_tasklet_rx(void *context, int pending);
+
+void cvm_oct_rx_initialize(void);
+void cvm_oct_rx_shutdown(void);
+
Property changes on: trunk/sys/mips/cavium/octe/ethernet-rx.h
___________________________________________________________________
Added: svn:eol-style
## -0,0 +1 ##
+native
\ No newline at end of property
Added: svn:keywords
## -0,0 +1 ##
+MidnightBSD=%H
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+text/plain
\ No newline at end of property
Added: trunk/sys/mips/cavium/octe/ethernet-sgmii.c
===================================================================
--- trunk/sys/mips/cavium/octe/ethernet-sgmii.c (rev 0)
+++ trunk/sys/mips/cavium/octe/ethernet-sgmii.c 2018-05-26 21:55:02 UTC (rev 9987)
@@ -0,0 +1,61 @@
+/* $MidnightBSD$ */
+/*************************************************************************
+Copyright (c) 2003-2007 Cavium Networks (support at cavium.com). All rights
+reserved.
+
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are
+met:
+
+ * Redistributions of source code must retain the above copyright
+ notice, this list of conditions and the following disclaimer.
+
+ * Redistributions in binary form must reproduce the above
+ copyright notice, this list of conditions and the following
+ disclaimer in the documentation and/or other materials provided
+ with the distribution.
+
+ * Neither the name of Cavium Networks nor the names of
+ its contributors may be used to endorse or promote products
+ derived from this software without specific prior written
+ permission.
+
+This Software, including technical data, may be subject to U.S. export control laws, including the U.S. Export Administration Act and its associated regulations, and may be subject to export or import regulations in other countries.
+
+TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
+AND WITH ALL FAULTS AND CAVIUM NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES OF TITLE, MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR PURPOSE, LACK OF VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET POSSESSION OR CORRESPONDENCE TO DESCRIPTION. THE ENTIRE RISK ARISING OUT OF USE OR PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
+
+*************************************************************************/
+
+#include <sys/cdefs.h>
+__FBSDID("$FreeBSD: stable/10/sys/mips/cavium/octe/ethernet-sgmii.c 242346 2012-10-30 06:36:14Z jmallett $");
+
+#include <sys/param.h>
+#include <sys/systm.h>
+#include <sys/bus.h>
+#include <sys/endian.h>
+#include <sys/kernel.h>
+#include <sys/mbuf.h>
+#include <sys/socket.h>
+
+#include <net/ethernet.h>
+#include <net/if.h>
+
+#include "wrapper-cvmx-includes.h"
+#include "ethernet-headers.h"
+
+int cvm_oct_sgmii_init(struct ifnet *ifp)
+{
+ cvm_oct_private_t *priv = (cvm_oct_private_t *)ifp->if_softc;
+
+ if (cvm_oct_common_init(ifp) != 0)
+ return ENXIO;
+
+ priv->open = cvm_oct_common_open;
+ priv->stop = cvm_oct_common_stop;
+ priv->stop(ifp);
+
+ /* FIXME: Need autoneg logic */
+ return 0;
+}
Property changes on: trunk/sys/mips/cavium/octe/ethernet-sgmii.c
___________________________________________________________________
Added: svn:eol-style
## -0,0 +1 ##
+native
\ No newline at end of property
Added: svn:keywords
## -0,0 +1 ##
+MidnightBSD=%H
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+text/plain
\ No newline at end of property
Added: trunk/sys/mips/cavium/octe/ethernet-spi.c
===================================================================
--- trunk/sys/mips/cavium/octe/ethernet-spi.c (rev 0)
+++ trunk/sys/mips/cavium/octe/ethernet-spi.c 2018-05-26 21:55:02 UTC (rev 9987)
@@ -0,0 +1,311 @@
+/* $MidnightBSD$ */
+/*************************************************************************
+Copyright (c) 2003-2007 Cavium Networks (support at cavium.com). All rights
+reserved.
+
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are
+met:
+
+ * Redistributions of source code must retain the above copyright
+ notice, this list of conditions and the following disclaimer.
+
+ * Redistributions in binary form must reproduce the above
+ copyright notice, this list of conditions and the following
+ disclaimer in the documentation and/or other materials provided
+ with the distribution.
+
+ * Neither the name of Cavium Networks nor the names of
+ its contributors may be used to endorse or promote products
+ derived from this software without specific prior written
+ permission.
+
+This Software, including technical data, may be subject to U.S. export control laws, including the U.S. Export Administration Act and its associated regulations, and may be subject to export or import regulations in other countries.
+
+TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
+AND WITH ALL FAULTS AND CAVIUM NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES OF TITLE, MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR PURPOSE, LACK OF VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET POSSESSION OR CORRESPONDENCE TO DESCRIPTION. THE ENTIRE RISK ARISING OUT OF USE OR PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
+
+*************************************************************************/
+
+#include <sys/cdefs.h>
+__FBSDID("$FreeBSD: stable/10/sys/mips/cavium/octe/ethernet-spi.c 232812 2012-03-11 06:17:49Z jmallett $");
+
+#include <sys/param.h>
+#include <sys/systm.h>
+#include <sys/bus.h>
+#include <sys/endian.h>
+#include <sys/kernel.h>
+#include <sys/mbuf.h>
+#include <sys/rman.h>
+#include <sys/socket.h>
+
+#include <net/ethernet.h>
+#include <net/if.h>
+
+#include "wrapper-cvmx-includes.h"
+#include "ethernet-headers.h"
+
+#include "octebusvar.h"
+
+static int number_spi_ports;
+static int need_retrain[2] = {0, 0};
+
+static int cvm_oct_spi_rml_interrupt(void *dev_id)
+{
+ int return_status = FILTER_STRAY;
+ cvmx_npi_rsl_int_blocks_t rsl_int_blocks;
+
+ /* Check and see if this interrupt was caused by the GMX block */
+ rsl_int_blocks.u64 = cvmx_read_csr(CVMX_NPI_RSL_INT_BLOCKS);
+ if (rsl_int_blocks.s.spx1) { /* 19 - SPX1_INT_REG & STX1_INT_REG */
+
+ cvmx_spxx_int_reg_t spx_int_reg;
+ cvmx_stxx_int_reg_t stx_int_reg;
+
+ spx_int_reg.u64 = cvmx_read_csr(CVMX_SPXX_INT_REG(1));
+ cvmx_write_csr(CVMX_SPXX_INT_REG(1), spx_int_reg.u64);
+ if (!need_retrain[1]) {
+
+ spx_int_reg.u64 &= cvmx_read_csr(CVMX_SPXX_INT_MSK(1));
+ if (spx_int_reg.s.spf)
+ printf("SPI1: SRX Spi4 interface down\n");
+ if (spx_int_reg.s.calerr)
+ printf("SPI1: SRX Spi4 Calendar table parity error\n");
+ if (spx_int_reg.s.syncerr)
+ printf("SPI1: SRX Consecutive Spi4 DIP4 errors have exceeded SPX_ERR_CTL[ERRCNT]\n");
+ if (spx_int_reg.s.diperr)
+ printf("SPI1: SRX Spi4 DIP4 error\n");
+ if (spx_int_reg.s.tpaovr)
+ printf("SPI1: SRX Selected port has hit TPA overflow\n");
+ if (spx_int_reg.s.rsverr)
+ printf("SPI1: SRX Spi4 reserved control word detected\n");
+ if (spx_int_reg.s.drwnng)
+ printf("SPI1: SRX Spi4 receive FIFO drowning/overflow\n");
+ if (spx_int_reg.s.clserr)
+ printf("SPI1: SRX Spi4 packet closed on non-16B alignment without EOP\n");
+ if (spx_int_reg.s.spiovr)
+ printf("SPI1: SRX Spi4 async FIFO overflow\n");
+ if (spx_int_reg.s.abnorm)
+ printf("SPI1: SRX Abnormal packet termination (ERR bit)\n");
+ if (spx_int_reg.s.prtnxa)
+ printf("SPI1: SRX Port out of range\n");
+ }
+
+ stx_int_reg.u64 = cvmx_read_csr(CVMX_STXX_INT_REG(1));
+ cvmx_write_csr(CVMX_STXX_INT_REG(1), stx_int_reg.u64);
+ if (!need_retrain[1]) {
+
+ stx_int_reg.u64 &= cvmx_read_csr(CVMX_STXX_INT_MSK(1));
+ if (stx_int_reg.s.syncerr)
+ printf("SPI1: STX Interface encountered a fatal error\n");
+ if (stx_int_reg.s.frmerr)
+ printf("SPI1: STX FRMCNT has exceeded STX_DIP_CNT[MAXFRM]\n");
+ if (stx_int_reg.s.unxfrm)
+ printf("SPI1: STX Unexpected framing sequence\n");
+ if (stx_int_reg.s.nosync)
+ printf("SPI1: STX ERRCNT has exceeded STX_DIP_CNT[MAXDIP]\n");
+ if (stx_int_reg.s.diperr)
+ printf("SPI1: STX DIP2 error on the Spi4 Status channel\n");
+ if (stx_int_reg.s.datovr)
+ printf("SPI1: STX Spi4 FIFO overflow error\n");
+ if (stx_int_reg.s.ovrbst)
+ printf("SPI1: STX Transmit packet burst too big\n");
+ if (stx_int_reg.s.calpar1)
+ printf("SPI1: STX Calendar Table Parity Error Bank1\n");
+ if (stx_int_reg.s.calpar0)
+ printf("SPI1: STX Calendar Table Parity Error Bank0\n");
+ }
+
+ cvmx_write_csr(CVMX_SPXX_INT_MSK(1), 0);
+ cvmx_write_csr(CVMX_STXX_INT_MSK(1), 0);
+ need_retrain[1] = 1;
+ return_status = FILTER_HANDLED;
+ }
+
+ if (rsl_int_blocks.s.spx0) { /* 18 - SPX0_INT_REG & STX0_INT_REG */
+ cvmx_spxx_int_reg_t spx_int_reg;
+ cvmx_stxx_int_reg_t stx_int_reg;
+
+ spx_int_reg.u64 = cvmx_read_csr(CVMX_SPXX_INT_REG(0));
+ cvmx_write_csr(CVMX_SPXX_INT_REG(0), spx_int_reg.u64);
+ if (!need_retrain[0]) {
+
+ spx_int_reg.u64 &= cvmx_read_csr(CVMX_SPXX_INT_MSK(0));
+ if (spx_int_reg.s.spf)
+ printf("SPI0: SRX Spi4 interface down\n");
+ if (spx_int_reg.s.calerr)
+ printf("SPI0: SRX Spi4 Calendar table parity error\n");
+ if (spx_int_reg.s.syncerr)
+ printf("SPI0: SRX Consecutive Spi4 DIP4 errors have exceeded SPX_ERR_CTL[ERRCNT]\n");
+ if (spx_int_reg.s.diperr)
+ printf("SPI0: SRX Spi4 DIP4 error\n");
+ if (spx_int_reg.s.tpaovr)
+ printf("SPI0: SRX Selected port has hit TPA overflow\n");
+ if (spx_int_reg.s.rsverr)
+ printf("SPI0: SRX Spi4 reserved control word detected\n");
+ if (spx_int_reg.s.drwnng)
+ printf("SPI0: SRX Spi4 receive FIFO drowning/overflow\n");
+ if (spx_int_reg.s.clserr)
+ printf("SPI0: SRX Spi4 packet closed on non-16B alignment without EOP\n");
+ if (spx_int_reg.s.spiovr)
+ printf("SPI0: SRX Spi4 async FIFO overflow\n");
+ if (spx_int_reg.s.abnorm)
+ printf("SPI0: SRX Abnormal packet termination (ERR bit)\n");
+ if (spx_int_reg.s.prtnxa)
+ printf("SPI0: SRX Port out of range\n");
+ }
+
+ stx_int_reg.u64 = cvmx_read_csr(CVMX_STXX_INT_REG(0));
+ cvmx_write_csr(CVMX_STXX_INT_REG(0), stx_int_reg.u64);
+ if (!need_retrain[0]) {
+
+ stx_int_reg.u64 &= cvmx_read_csr(CVMX_STXX_INT_MSK(0));
+ if (stx_int_reg.s.syncerr)
+ printf("SPI0: STX Interface encountered a fatal error\n");
+ if (stx_int_reg.s.frmerr)
+ printf("SPI0: STX FRMCNT has exceeded STX_DIP_CNT[MAXFRM]\n");
+ if (stx_int_reg.s.unxfrm)
+ printf("SPI0: STX Unexpected framing sequence\n");
+ if (stx_int_reg.s.nosync)
+ printf("SPI0: STX ERRCNT has exceeded STX_DIP_CNT[MAXDIP]\n");
+ if (stx_int_reg.s.diperr)
+ printf("SPI0: STX DIP2 error on the Spi4 Status channel\n");
+ if (stx_int_reg.s.datovr)
+ printf("SPI0: STX Spi4 FIFO overflow error\n");
+ if (stx_int_reg.s.ovrbst)
+ printf("SPI0: STX Transmit packet burst too big\n");
+ if (stx_int_reg.s.calpar1)
+ printf("SPI0: STX Calendar Table Parity Error Bank1\n");
+ if (stx_int_reg.s.calpar0)
+ printf("SPI0: STX Calendar Table Parity Error Bank0\n");
+ }
+
+ cvmx_write_csr(CVMX_SPXX_INT_MSK(0), 0);
+ cvmx_write_csr(CVMX_STXX_INT_MSK(0), 0);
+ need_retrain[0] = 1;
+ return_status = FILTER_HANDLED;
+ }
+
+ return return_status;
+}
+
+static void cvm_oct_spi_enable_error_reporting(int interface)
+{
+ cvmx_spxx_int_msk_t spxx_int_msk;
+ cvmx_stxx_int_msk_t stxx_int_msk;
+
+ spxx_int_msk.u64 = cvmx_read_csr(CVMX_SPXX_INT_MSK(interface));
+ spxx_int_msk.s.calerr = 1;
+ spxx_int_msk.s.syncerr = 1;
+ spxx_int_msk.s.diperr = 1;
+ spxx_int_msk.s.tpaovr = 1;
+ spxx_int_msk.s.rsverr = 1;
+ spxx_int_msk.s.drwnng = 1;
+ spxx_int_msk.s.clserr = 1;
+ spxx_int_msk.s.spiovr = 1;
+ spxx_int_msk.s.abnorm = 1;
+ spxx_int_msk.s.prtnxa = 1;
+ cvmx_write_csr(CVMX_SPXX_INT_MSK(interface), spxx_int_msk.u64);
+
+ stxx_int_msk.u64 = cvmx_read_csr(CVMX_STXX_INT_MSK(interface));
+ stxx_int_msk.s.frmerr = 1;
+ stxx_int_msk.s.unxfrm = 1;
+ stxx_int_msk.s.nosync = 1;
+ stxx_int_msk.s.diperr = 1;
+ stxx_int_msk.s.datovr = 1;
+ stxx_int_msk.s.ovrbst = 1;
+ stxx_int_msk.s.calpar1 = 1;
+ stxx_int_msk.s.calpar0 = 1;
+ cvmx_write_csr(CVMX_STXX_INT_MSK(interface), stxx_int_msk.u64);
+}
+
+static void cvm_oct_spi_poll(struct ifnet *ifp)
+{
+ static int spi4000_port;
+ cvm_oct_private_t *priv = (cvm_oct_private_t *)ifp->if_softc;
+ int interface;
+
+ for (interface = 0; interface < 2; interface++) {
+
+ if ((priv->port == interface*16) && need_retrain[interface]) {
+
+ if (cvmx_spi_restart_interface(interface, CVMX_SPI_MODE_DUPLEX, 10) == 0) {
+ need_retrain[interface] = 0;
+ cvm_oct_spi_enable_error_reporting(interface);
+ }
+ }
+
+ /* The SPI4000 TWSI interface is very slow. In order not to
+ bring the system to a crawl, we only poll a single port
+ every second. This means negotiation speed changes
+ take up to 10 seconds, but at least we don't waste
+ absurd amounts of time waiting for TWSI */
+ if (priv->port == spi4000_port) {
+ /* This function does nothing if it is called on an
+ interface without a SPI4000 */
+ cvmx_spi4000_check_speed(interface, priv->port);
+ /* Normal ordering increments. By decrementing
+ we only match once per iteration */
+ spi4000_port--;
+ if (spi4000_port < 0)
+ spi4000_port = 10;
+ }
+ }
+}
+
+
+int cvm_oct_spi_init(struct ifnet *ifp)
+{
+ struct octebus_softc *sc;
+ cvm_oct_private_t *priv = (cvm_oct_private_t *)ifp->if_softc;
+ int error;
+ int rid;
+
+ if (number_spi_ports == 0) {
+ sc = device_get_softc(device_get_parent(priv->dev));
+
+ rid = 0;
+ sc->sc_spi_irq = bus_alloc_resource(sc->sc_dev, SYS_RES_IRQ,
+ &rid, OCTEON_IRQ_RML,
+ OCTEON_IRQ_RML, 1,
+ RF_ACTIVE);
+ if (sc->sc_spi_irq == NULL) {
+ device_printf(sc->sc_dev, "could not allocate SPI irq");
+ return ENXIO;
+ }
+
+ error = bus_setup_intr(sc->sc_dev, sc->sc_spi_irq,
+ INTR_TYPE_NET | INTR_MPSAFE,
+ cvm_oct_spi_rml_interrupt, NULL,
+ &number_spi_ports, NULL);
+ if (error != 0) {
+ device_printf(sc->sc_dev, "could not setup SPI irq");
+ return error;
+ }
+ }
+ number_spi_ports++;
+
+ if ((priv->port == 0) || (priv->port == 16)) {
+ cvm_oct_spi_enable_error_reporting(INTERFACE(priv->port));
+ priv->poll = cvm_oct_spi_poll;
+ }
+ if (cvm_oct_common_init(ifp) != 0)
+ return ENXIO;
+ return 0;
+}
+
+void cvm_oct_spi_uninit(struct ifnet *ifp)
+{
+ int interface;
+
+ cvm_oct_common_uninit(ifp);
+ number_spi_ports--;
+ if (number_spi_ports == 0) {
+ for (interface = 0; interface < 2; interface++) {
+ cvmx_write_csr(CVMX_SPXX_INT_MSK(interface), 0);
+ cvmx_write_csr(CVMX_STXX_INT_MSK(interface), 0);
+ }
+ panic("%s: IRQ release not yet implemented.", __func__);
+ }
+}
Property changes on: trunk/sys/mips/cavium/octe/ethernet-spi.c
___________________________________________________________________
Added: svn:eol-style
## -0,0 +1 ##
+native
\ No newline at end of property
Added: svn:keywords
## -0,0 +1 ##
+MidnightBSD=%H
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+text/plain
\ No newline at end of property
Added: trunk/sys/mips/cavium/octe/ethernet-tx.c
===================================================================
--- trunk/sys/mips/cavium/octe/ethernet-tx.c (rev 0)
+++ trunk/sys/mips/cavium/octe/ethernet-tx.c 2018-05-26 21:55:02 UTC (rev 9987)
@@ -0,0 +1,272 @@
+/* $MidnightBSD$ */
+/*************************************************************************
+Copyright (c) 2003-2007 Cavium Networks (support at cavium.com). All rights
+reserved.
+
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are
+met:
+
+ * Redistributions of source code must retain the above copyright
+ notice, this list of conditions and the following disclaimer.
+
+ * Redistributions in binary form must reproduce the above
+ copyright notice, this list of conditions and the following
+ disclaimer in the documentation and/or other materials provided
+ with the distribution.
+
+ * Neither the name of Cavium Networks nor the names of
+ its contributors may be used to endorse or promote products
+ derived from this software without specific prior written
+ permission.
+
+This Software, including technical data, may be subject to U.S. export control laws, including the U.S. Export Administration Act and its associated regulations, and may be subject to export or import regulations in other countries.
+
+TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
+AND WITH ALL FAULTS AND CAVIUM NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES OF TITLE, MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR PURPOSE, LACK OF VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET POSSESSION OR CORRESPONDENCE TO DESCRIPTION. THE ENTIRE RISK ARISING OUT OF USE OR PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
+
+*************************************************************************/
+
+#include <sys/cdefs.h>
+__FBSDID("$FreeBSD: stable/10/sys/mips/cavium/octe/ethernet-tx.c 243264 2012-11-19 08:30:29Z jmallett $");
+
+#include <sys/param.h>
+#include <sys/systm.h>
+#include <sys/bus.h>
+#include <sys/endian.h>
+#include <sys/kernel.h>
+#include <sys/mbuf.h>
+#include <sys/socket.h>
+
+#include <net/bpf.h>
+#include <net/ethernet.h>
+#include <net/if.h>
+
+#include "wrapper-cvmx-includes.h"
+#include "ethernet-headers.h"
+
+/* You can define GET_MBUF_QOS() to override how the mbuf output function
+ determines which output queue is used. The default implementation
+ always uses the base queue for the port. If, for example, you wanted
+ to use the m->priority fieid, define GET_MBUF_QOS as:
+ #define GET_MBUF_QOS(m) ((m)->priority) */
+#ifndef GET_MBUF_QOS
+ #define GET_MBUF_QOS(m) 0
+#endif
+
+
+/**
+ * Packet transmit
+ *
+ * @param m Packet to send
+ * @param dev Device info structure
+ * @return Always returns zero
+ */
+int cvm_oct_xmit(struct mbuf *m, struct ifnet *ifp)
+{
+ cvmx_pko_command_word0_t pko_command;
+ cvmx_buf_ptr_t hw_buffer;
+ int dropped;
+ int qos;
+ cvm_oct_private_t *priv = (cvm_oct_private_t *)ifp->if_softc;
+ int32_t in_use;
+ int32_t buffers_to_free;
+ cvmx_wqe_t *work;
+
+ /* Prefetch the private data structure.
+ It is larger that one cache line */
+ CVMX_PREFETCH(priv, 0);
+
+ /* Start off assuming no drop */
+ dropped = 0;
+
+ /* The check on CVMX_PKO_QUEUES_PER_PORT_* is designed to completely
+ remove "qos" in the event neither interface supports multiple queues
+ per port */
+ if ((CVMX_PKO_QUEUES_PER_PORT_INTERFACE0 > 1) ||
+ (CVMX_PKO_QUEUES_PER_PORT_INTERFACE1 > 1)) {
+ qos = GET_MBUF_QOS(m);
+ if (qos <= 0)
+ qos = 0;
+ else if (qos >= cvmx_pko_get_num_queues(priv->port))
+ qos = 0;
+ } else
+ qos = 0;
+
+ /* The CN3XXX series of parts has an errata (GMX-401) which causes the
+ GMX block to hang if a collision occurs towards the end of a
+ <68 byte packet. As a workaround for this, we pad packets to be
+ 68 bytes whenever we are in half duplex mode. We don't handle
+ the case of having a small packet but no room to add the padding.
+ The kernel should always give us at least a cache line */
+ if (__predict_false(m->m_pkthdr.len < 64) && OCTEON_IS_MODEL(OCTEON_CN3XXX)) {
+ cvmx_gmxx_prtx_cfg_t gmx_prt_cfg;
+ int interface = INTERFACE(priv->port);
+ int index = INDEX(priv->port);
+
+ if (interface < 2) {
+ /* We only need to pad packet in half duplex mode */
+ gmx_prt_cfg.u64 = cvmx_read_csr(CVMX_GMXX_PRTX_CFG(index, interface));
+ if (gmx_prt_cfg.s.duplex == 0) {
+ static uint8_t pad[64];
+
+ if (!m_append(m, sizeof pad - m->m_pkthdr.len, pad))
+ printf("%s: unable to padd small packet.", __func__);
+ }
+ }
+ }
+
+#ifdef OCTEON_VENDOR_RADISYS
+ /*
+ * The RSYS4GBE will hang if asked to transmit a packet less than 60 bytes.
+ */
+ if (__predict_false(m->m_pkthdr.len < 60) &&
+ cvmx_sysinfo_get()->board_type == CVMX_BOARD_TYPE_CUST_RADISYS_RSYS4GBE) {
+ static uint8_t pad[60];
+
+ if (!m_append(m, sizeof pad - m->m_pkthdr.len, pad))
+ printf("%s: unable to pad small packet.", __func__);
+ }
+#endif
+
+ /*
+ * If the packet is not fragmented.
+ */
+ if (m->m_pkthdr.len == m->m_len) {
+ /* Build the PKO buffer pointer */
+ hw_buffer.u64 = 0;
+ hw_buffer.s.addr = cvmx_ptr_to_phys(m->m_data);
+ hw_buffer.s.pool = 0;
+ hw_buffer.s.size = m->m_len;
+
+ /* Build the PKO command */
+ pko_command.u64 = 0;
+ pko_command.s.segs = 1;
+ pko_command.s.dontfree = 1; /* Do not put this buffer into the FPA. */
+
+ work = NULL;
+ } else {
+ struct mbuf *n;
+ unsigned segs;
+ uint64_t *gp;
+
+ /*
+ * The packet is fragmented, we need to send a list of segments
+ * in memory we borrow from the WQE pool.
+ */
+ work = cvmx_fpa_alloc(CVMX_FPA_WQE_POOL);
+ if (work == NULL) {
+ m_freem(m);
+ ifp->if_oerrors++;
+ return 1;
+ }
+
+ segs = 0;
+ gp = (uint64_t *)work;
+ for (n = m; n != NULL; n = n->m_next) {
+ if (segs == CVMX_FPA_WQE_POOL_SIZE / sizeof (uint64_t))
+ panic("%s: too many segments in packet; call m_collapse().", __func__);
+
+ /* Build the PKO buffer pointer */
+ hw_buffer.u64 = 0;
+ hw_buffer.s.i = 1; /* Do not put this buffer into the FPA. */
+ hw_buffer.s.addr = cvmx_ptr_to_phys(n->m_data);
+ hw_buffer.s.pool = 0;
+ hw_buffer.s.size = n->m_len;
+
+ *gp++ = hw_buffer.u64;
+ segs++;
+ }
+
+ /* Build the PKO buffer gather list pointer */
+ hw_buffer.u64 = 0;
+ hw_buffer.s.addr = cvmx_ptr_to_phys(work);
+ hw_buffer.s.pool = CVMX_FPA_WQE_POOL;
+ hw_buffer.s.size = segs;
+
+ /* Build the PKO command */
+ pko_command.u64 = 0;
+ pko_command.s.segs = segs;
+ pko_command.s.gather = 1;
+ pko_command.s.dontfree = 0; /* Put the WQE above back into the FPA. */
+ }
+
+ /* Finish building the PKO command */
+ pko_command.s.n2 = 1; /* Don't pollute L2 with the outgoing packet */
+ pko_command.s.reg0 = priv->fau+qos*4;
+ pko_command.s.total_bytes = m->m_pkthdr.len;
+ pko_command.s.size0 = CVMX_FAU_OP_SIZE_32;
+ pko_command.s.subone0 = 1;
+
+ /* Check if we can use the hardware checksumming */
+ if ((m->m_pkthdr.csum_flags & (CSUM_TCP | CSUM_UDP)) != 0) {
+ /* Use hardware checksum calc */
+ pko_command.s.ipoffp1 = ETHER_HDR_LEN + 1;
+ }
+
+ /*
+ * XXX
+ * Could use a different free queue (and different FAU address) per
+ * core instead of per QoS, to reduce contention here.
+ */
+ IF_LOCK(&priv->tx_free_queue[qos]);
+ /* Get the number of mbufs in use by the hardware */
+ in_use = cvmx_fau_fetch_and_add32(priv->fau+qos*4, 1);
+ buffers_to_free = cvmx_fau_fetch_and_add32(FAU_NUM_PACKET_BUFFERS_TO_FREE, 0);
+
+ cvmx_pko_send_packet_prepare(priv->port, priv->queue + qos, CVMX_PKO_LOCK_CMD_QUEUE);
+
+ /* Drop this packet if we have too many already queued to the HW */
+ if (_IF_QFULL(&priv->tx_free_queue[qos])) {
+ dropped = 1;
+ }
+ /* Send the packet to the output queue */
+ else
+ if (__predict_false(cvmx_pko_send_packet_finish(priv->port, priv->queue + qos, pko_command, hw_buffer, CVMX_PKO_LOCK_CMD_QUEUE))) {
+ DEBUGPRINT("%s: Failed to send the packet\n", if_name(ifp));
+ dropped = 1;
+ }
+
+ if (__predict_false(dropped)) {
+ m_freem(m);
+ cvmx_fau_atomic_add32(priv->fau+qos*4, -1);
+ ifp->if_oerrors++;
+ } else {
+ /* Put this packet on the queue to be freed later */
+ _IF_ENQUEUE(&priv->tx_free_queue[qos], m);
+
+ /* Pass it to any BPF listeners. */
+ ETHER_BPF_MTAP(ifp, m);
+
+ ifp->if_opackets++;
+ ifp->if_obytes += m->m_pkthdr.len;
+ }
+
+ /* Free mbufs not in use by the hardware */
+ if (_IF_QLEN(&priv->tx_free_queue[qos]) > in_use) {
+ while (_IF_QLEN(&priv->tx_free_queue[qos]) > in_use) {
+ _IF_DEQUEUE(&priv->tx_free_queue[qos], m);
+ m_freem(m);
+ }
+ }
+ IF_UNLOCK(&priv->tx_free_queue[qos]);
+
+ return dropped;
+}
+
+
+/**
+ * This function frees all mbufs that are currenty queued for TX.
+ *
+ * @param dev Device being shutdown
+ */
+void cvm_oct_tx_shutdown(struct ifnet *ifp)
+{
+ cvm_oct_private_t *priv = (cvm_oct_private_t *)ifp->if_softc;
+ int qos;
+
+ for (qos = 0; qos < 16; qos++) {
+ IF_DRAIN(&priv->tx_free_queue[qos]);
+ }
+}
Property changes on: trunk/sys/mips/cavium/octe/ethernet-tx.c
___________________________________________________________________
Added: svn:eol-style
## -0,0 +1 ##
+native
\ No newline at end of property
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## -0,0 +1 ##
+MidnightBSD=%H
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+text/plain
\ No newline at end of property
Added: trunk/sys/mips/cavium/octe/ethernet-tx.h
===================================================================
--- trunk/sys/mips/cavium/octe/ethernet-tx.h (rev 0)
+++ trunk/sys/mips/cavium/octe/ethernet-tx.h 2018-05-26 21:55:02 UTC (rev 9987)
@@ -0,0 +1,34 @@
+/* $MidnightBSD$ */
+/*************************************************************************
+Copyright (c) 2003-2007 Cavium Networks (support at cavium.com). All rights
+reserved.
+
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are
+met:
+
+ * Redistributions of source code must retain the above copyright
+ notice, this list of conditions and the following disclaimer.
+
+ * Redistributions in binary form must reproduce the above
+ copyright notice, this list of conditions and the following
+ disclaimer in the documentation and/or other materials provided
+ with the distribution.
+
+ * Neither the name of Cavium Networks nor the names of
+ its contributors may be used to endorse or promote products
+ derived from this software without specific prior written
+ permission.
+
+This Software, including technical data, may be subject to U.S. export control laws, including the U.S. Export Administration Act and its associated regulations, and may be subject to export or import regulations in other countries.
+
+TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
+AND WITH ALL FAULTS AND CAVIUM NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES OF TITLE, MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR PURPOSE, LACK OF VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET POSSESSION OR CORRESPONDENCE TO DESCRIPTION. THE ENTIRE RISK ARISING OUT OF USE OR PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
+
+*************************************************************************/
+/* $FreeBSD: stable/10/sys/mips/cavium/octe/ethernet-tx.h 215959 2010-11-28 00:26:08Z jmallett $ */
+
+int cvm_oct_xmit(struct mbuf *m, struct ifnet *ifp);
+void cvm_oct_tx_shutdown(struct ifnet *ifp);
+
Property changes on: trunk/sys/mips/cavium/octe/ethernet-tx.h
___________________________________________________________________
Added: svn:eol-style
## -0,0 +1 ##
+native
\ No newline at end of property
Added: svn:keywords
## -0,0 +1 ##
+MidnightBSD=%H
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+text/plain
\ No newline at end of property
Added: trunk/sys/mips/cavium/octe/ethernet-util.h
===================================================================
--- trunk/sys/mips/cavium/octe/ethernet-util.h (rev 0)
+++ trunk/sys/mips/cavium/octe/ethernet-util.h 2018-05-26 21:55:02 UTC (rev 9987)
@@ -0,0 +1,85 @@
+/* $MidnightBSD$ */
+/*************************************************************************
+Copyright (c) 2003-2007 Cavium Networks (support at cavium.com). All rights
+reserved.
+
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are
+met:
+
+ * Redistributions of source code must retain the above copyright
+ notice, this list of conditions and the following disclaimer.
+
+ * Redistributions in binary form must reproduce the above
+ copyright notice, this list of conditions and the following
+ disclaimer in the documentation and/or other materials provided
+ with the distribution.
+
+ * Neither the name of Cavium Networks nor the names of
+ its contributors may be used to endorse or promote products
+ derived from this software without specific prior written
+ permission.
+
+This Software, including technical data, may be subject to U.S. export control laws, including the U.S. Export Administration Act and its associated regulations, and may be subject to export or import regulations in other countries.
+
+TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
+AND WITH ALL FAULTS AND CAVIUM NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES OF TITLE, MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR PURPOSE, LACK OF VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET POSSESSION OR CORRESPONDENCE TO DESCRIPTION. THE ENTIRE RISK ARISING OUT OF USE OR PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
+
+*************************************************************************/
+/* $FreeBSD: stable/10/sys/mips/cavium/octe/ethernet-util.h 210311 2010-07-20 19:25:11Z jmallett $ */
+
+#define DEBUGPRINT(format, ...) printf(format, ##__VA_ARGS__)
+
+/**
+ * Given a packet data address, return a pointer to the
+ * beginning of the packet buffer.
+ *
+ * @param packet_ptr Packet data hardware address
+ * @return Packet buffer pointer
+ */
+static inline char *cvm_oct_get_buffer_ptr(cvmx_buf_ptr_t packet_ptr)
+{
+ return cvmx_phys_to_ptr(((packet_ptr.s.addr >> 7) - packet_ptr.s.back) << 7);
+}
+
+
+/**
+ * Given an IPD/PKO port number, return the logical interface it is
+ * on.
+ *
+ * @param ipd_port Port to check
+ *
+ * @return Logical interface
+ */
+static inline int INTERFACE(int ipd_port)
+{
+ if (ipd_port < 32) /* Interface 0 or 1 for RGMII,GMII,SPI, etc */
+ return ipd_port>>4;
+ else if (ipd_port < 36) /* Interface 2 for NPI */
+ return 2;
+ else if (ipd_port < 40) /* Interface 3 for loopback */
+ return 3;
+ else if (ipd_port == 40) /* Non existant interface for POW0 */
+ return 4;
+ else
+ panic("Illegal ipd_port %d passed to INTERFACE\n", ipd_port);
+}
+
+
+/**
+ * Given an IPD/PKO port number, return the port's index on a
+ * logical interface.
+ *
+ * @param ipd_port Port to check
+ *
+ * @return Index into interface port list
+ */
+static inline int INDEX(int ipd_port)
+{
+ if (ipd_port < 32)
+ return ipd_port & 15;
+ else
+ return ipd_port & 3;
+}
+
Property changes on: trunk/sys/mips/cavium/octe/ethernet-util.h
___________________________________________________________________
Added: svn:eol-style
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+native
\ No newline at end of property
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## -0,0 +1 ##
+MidnightBSD=%H
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Added: svn:mime-type
## -0,0 +1 ##
+text/plain
\ No newline at end of property
Added: trunk/sys/mips/cavium/octe/ethernet-xaui.c
===================================================================
--- trunk/sys/mips/cavium/octe/ethernet-xaui.c (rev 0)
+++ trunk/sys/mips/cavium/octe/ethernet-xaui.c 2018-05-26 21:55:02 UTC (rev 9987)
@@ -0,0 +1,60 @@
+/* $MidnightBSD$ */
+/*************************************************************************
+Copyright (c) 2003-2007 Cavium Networks (support at cavium.com). All rights
+reserved.
+
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are
+met:
+
+ * Redistributions of source code must retain the above copyright
+ notice, this list of conditions and the following disclaimer.
+
+ * Redistributions in binary form must reproduce the above
+ copyright notice, this list of conditions and the following
+ disclaimer in the documentation and/or other materials provided
+ with the distribution.
+
+ * Neither the name of Cavium Networks nor the names of
+ its contributors may be used to endorse or promote products
+ derived from this software without specific prior written
+ permission.
+
+This Software, including technical data, may be subject to U.S. export control laws, including the U.S. Export Administration Act and its associated regulations, and may be subject to export or import regulations in other countries.
+
+TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
+AND WITH ALL FAULTS AND CAVIUM NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES OF TITLE, MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR PURPOSE, LACK OF VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET POSSESSION OR CORRESPONDENCE TO DESCRIPTION. THE ENTIRE RISK ARISING OUT OF USE OR PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
+
+*************************************************************************/
+
+#include <sys/cdefs.h>
+__FBSDID("$FreeBSD: stable/10/sys/mips/cavium/octe/ethernet-xaui.c 242346 2012-10-30 06:36:14Z jmallett $");
+
+#include <sys/param.h>
+#include <sys/systm.h>
+#include <sys/bus.h>
+#include <sys/endian.h>
+#include <sys/kernel.h>
+#include <sys/mbuf.h>
+#include <sys/socket.h>
+
+#include <net/ethernet.h>
+#include <net/if.h>
+
+#include "wrapper-cvmx-includes.h"
+#include "ethernet-headers.h"
+
+int cvm_oct_xaui_init(struct ifnet *ifp)
+{
+ cvm_oct_private_t *priv = (cvm_oct_private_t *)ifp->if_softc;
+
+ if (cvm_oct_common_init(ifp) != 0)
+ return ENXIO;
+
+ priv->open = cvm_oct_common_open;
+ priv->stop = cvm_oct_common_stop;
+ priv->stop(ifp);
+
+ return 0;
+}
Property changes on: trunk/sys/mips/cavium/octe/ethernet-xaui.c
___________________________________________________________________
Added: svn:eol-style
## -0,0 +1 ##
+native
\ No newline at end of property
Added: svn:keywords
## -0,0 +1 ##
+MidnightBSD=%H
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+text/plain
\ No newline at end of property
Added: trunk/sys/mips/cavium/octe/ethernet.c
===================================================================
--- trunk/sys/mips/cavium/octe/ethernet.c (rev 0)
+++ trunk/sys/mips/cavium/octe/ethernet.c 2018-05-26 21:55:02 UTC (rev 9987)
@@ -0,0 +1,508 @@
+/* $MidnightBSD$ */
+/*************************************************************************
+Copyright (c) 2003-2007 Cavium Networks (support at cavium.com). All rights
+reserved.
+
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are
+met:
+
+ * Redistributions of source code must retain the above copyright
+ notice, this list of conditions and the following disclaimer.
+
+ * Redistributions in binary form must reproduce the above
+ copyright notice, this list of conditions and the following
+ disclaimer in the documentation and/or other materials provided
+ with the distribution.
+
+ * Neither the name of Cavium Networks nor the names of
+ its contributors may be used to endorse or promote products
+ derived from this software without specific prior written
+ permission.
+
+This Software, including technical data, may be subject to U.S. export control laws, including the U.S. Export Administration Act and its associated regulations, and may be subject to export or import regulations in other countries.
+
+TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
+AND WITH ALL FAULTS AND CAVIUM NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES OF TITLE, MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR PURPOSE, LACK OF VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET POSSESSION OR CORRESPONDENCE TO DESCRIPTION. THE ENTIRE RISK ARISING OUT OF USE OR PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
+*************************************************************************/
+
+#include <sys/cdefs.h>
+__FBSDID("$FreeBSD: stable/10/sys/mips/cavium/octe/ethernet.c 314667 2017-03-04 13:03:31Z avg $");
+
+#include <sys/param.h>
+#include <sys/systm.h>
+#include <sys/bus.h>
+#include <sys/conf.h>
+#include <sys/endian.h>
+#include <sys/kernel.h>
+#include <sys/rman.h>
+#include <sys/mbuf.h>
+#include <sys/socket.h>
+#include <sys/module.h>
+#include <sys/smp.h>
+#include <sys/taskqueue.h>
+
+#include <net/ethernet.h>
+#include <net/if.h>
+#include <net/if_types.h>
+
+#include "wrapper-cvmx-includes.h"
+#include "ethernet-headers.h"
+
+#include "octebusvar.h"
+
+/*
+ * XXX/juli
+ * Convert 0444 to tunables, 0644 to sysctls.
+ */
+#if defined(CONFIG_CAVIUM_OCTEON_NUM_PACKET_BUFFERS) && CONFIG_CAVIUM_OCTEON_NUM_PACKET_BUFFERS
+int num_packet_buffers = CONFIG_CAVIUM_OCTEON_NUM_PACKET_BUFFERS;
+#else
+int num_packet_buffers = 1024;
+#endif
+TUNABLE_INT("hw.octe.num_packet_buffers", &num_packet_buffers);
+/*
+ "\t\tNumber of packet buffers to allocate and store in the\n"
+ "\t\tFPA. By default, 1024 packet buffers are used unless\n"
+ "\t\tCONFIG_CAVIUM_OCTEON_NUM_PACKET_BUFFERS is defined." */
+
+int pow_receive_group = 15;
+TUNABLE_INT("hw.octe.pow_receive_group", &pow_receive_group);
+/*
+ "\t\tPOW group to receive packets from. All ethernet hardware\n"
+ "\t\twill be configured to send incomming packets to this POW\n"
+ "\t\tgroup. Also any other software can submit packets to this\n"
+ "\t\tgroup for the kernel to process." */
+
+/**
+ * Periodic timer to check auto negotiation
+ */
+static struct callout cvm_oct_poll_timer;
+
+/**
+ * Array of every ethernet device owned by this driver indexed by
+ * the ipd input port number.
+ */
+struct ifnet *cvm_oct_device[TOTAL_NUMBER_OF_PORTS];
+
+/**
+ * Task to handle link status changes.
+ */
+static struct taskqueue *cvm_oct_link_taskq;
+
+/*
+ * Number of buffers in output buffer pool.
+ */
+static int cvm_oct_num_output_buffers;
+
+/**
+ * Function to update link status.
+ */
+static void cvm_oct_update_link(void *context, int pending)
+{
+ cvm_oct_private_t *priv = (cvm_oct_private_t *)context;
+ struct ifnet *ifp = priv->ifp;
+ cvmx_helper_link_info_t link_info;
+
+ link_info.u64 = priv->link_info;
+
+ if (link_info.s.link_up) {
+ if_link_state_change(ifp, LINK_STATE_UP);
+ DEBUGPRINT("%s: %u Mbps %s duplex, port %2d, queue %2d\n",
+ if_name(ifp), link_info.s.speed,
+ (link_info.s.full_duplex) ? "Full" : "Half",
+ priv->port, priv->queue);
+ } else {
+ if_link_state_change(ifp, LINK_STATE_DOWN);
+ DEBUGPRINT("%s: Link down\n", if_name(ifp));
+ }
+ priv->need_link_update = 0;
+}
+
+/**
+ * Periodic timer tick for slow management operations
+ *
+ * @param arg Device to check
+ */
+static void cvm_do_timer(void *arg)
+{
+ static int port;
+ static int updated;
+ if (port < CVMX_PIP_NUM_INPUT_PORTS) {
+ if (cvm_oct_device[port]) {
+ int queues_per_port;
+ int qos;
+ cvm_oct_private_t *priv = (cvm_oct_private_t *)cvm_oct_device[port]->if_softc;
+
+ cvm_oct_common_poll(priv->ifp);
+ if (priv->need_link_update) {
+ updated++;
+ taskqueue_enqueue(cvm_oct_link_taskq, &priv->link_task);
+ }
+
+ queues_per_port = cvmx_pko_get_num_queues(port);
+ /* Drain any pending packets in the free list */
+ for (qos = 0; qos < queues_per_port; qos++) {
+ if (_IF_QLEN(&priv->tx_free_queue[qos]) > 0) {
+ IF_LOCK(&priv->tx_free_queue[qos]);
+ while (_IF_QLEN(&priv->tx_free_queue[qos]) > cvmx_fau_fetch_and_add32(priv->fau+qos*4, 0)) {
+ struct mbuf *m;
+
+ _IF_DEQUEUE(&priv->tx_free_queue[qos], m);
+ m_freem(m);
+ }
+ IF_UNLOCK(&priv->tx_free_queue[qos]);
+
+ /*
+ * XXX locking!
+ */
+ priv->ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
+ }
+ }
+ }
+ port++;
+ /* Poll the next port in a 50th of a second.
+ This spreads the polling of ports out a little bit */
+ callout_reset(&cvm_oct_poll_timer, hz / 50, cvm_do_timer, NULL);
+ } else {
+ port = 0;
+ /* If any updates were made in this run, continue iterating at
+ * 1/50th of a second, so that if a link has merely gone down
+ * temporarily (e.g. because of interface reinitialization) it
+ * will not be forced to stay down for an entire second.
+ */
+ if (updated > 0) {
+ updated = 0;
+ callout_reset(&cvm_oct_poll_timer, hz / 50, cvm_do_timer, NULL);
+ } else {
+ /* All ports have been polled. Start the next iteration through
+ the ports in one second */
+ callout_reset(&cvm_oct_poll_timer, hz, cvm_do_timer, NULL);
+ }
+ }
+}
+
+/**
+ * Configure common hardware for all interfaces
+ */
+static void cvm_oct_configure_common_hw(device_t bus)
+{
+ struct octebus_softc *sc;
+ int pko_queues;
+ int error;
+ int rid;
+
+ sc = device_get_softc(bus);
+
+ /* Setup the FPA */
+ cvmx_fpa_enable();
+ cvm_oct_mem_fill_fpa(CVMX_FPA_PACKET_POOL, CVMX_FPA_PACKET_POOL_SIZE,
+ num_packet_buffers);
+ cvm_oct_mem_fill_fpa(CVMX_FPA_WQE_POOL, CVMX_FPA_WQE_POOL_SIZE,
+ num_packet_buffers);
+ if (CVMX_FPA_OUTPUT_BUFFER_POOL != CVMX_FPA_PACKET_POOL) {
+ /*
+ * If the FPA uses different pools for output buffers and
+ * packets, size the output buffer pool based on the number
+ * of PKO queues.
+ */
+ if (OCTEON_IS_MODEL(OCTEON_CN38XX))
+ pko_queues = 128;
+ else if (OCTEON_IS_MODEL(OCTEON_CN3XXX))
+ pko_queues = 32;
+ else if (OCTEON_IS_MODEL(OCTEON_CN50XX))
+ pko_queues = 32;
+ else
+ pko_queues = 256;
+
+ cvm_oct_num_output_buffers = 4 * pko_queues;
+ cvm_oct_mem_fill_fpa(CVMX_FPA_OUTPUT_BUFFER_POOL,
+ CVMX_FPA_OUTPUT_BUFFER_POOL_SIZE,
+ cvm_oct_num_output_buffers);
+ }
+
+ if (USE_RED)
+ cvmx_helper_setup_red(num_packet_buffers/4,
+ num_packet_buffers/8);
+
+ /* Enable the MII interface */
+ if (cvmx_sysinfo_get()->board_type != CVMX_BOARD_TYPE_SIM)
+ cvmx_write_csr(CVMX_SMI_EN, 1);
+
+ /* Register an IRQ hander for to receive POW interrupts */
+ rid = 0;
+ sc->sc_rx_irq = bus_alloc_resource(bus, SYS_RES_IRQ, &rid,
+ OCTEON_IRQ_WORKQ0 + pow_receive_group,
+ OCTEON_IRQ_WORKQ0 + pow_receive_group,
+ 1, RF_ACTIVE);
+ if (sc->sc_rx_irq == NULL) {
+ device_printf(bus, "could not allocate workq irq");
+ return;
+ }
+
+ error = bus_setup_intr(bus, sc->sc_rx_irq, INTR_TYPE_NET | INTR_MPSAFE,
+ cvm_oct_do_interrupt, NULL, cvm_oct_device,
+ &sc->sc_rx_intr_cookie);
+ if (error != 0) {
+ device_printf(bus, "could not setup workq irq");
+ return;
+ }
+
+
+#ifdef SMP
+ {
+ cvmx_ciu_intx0_t en;
+ int core;
+
+ CPU_FOREACH(core) {
+ if (core == PCPU_GET(cpuid))
+ continue;
+
+ en.u64 = cvmx_read_csr(CVMX_CIU_INTX_EN0(core*2));
+ en.s.workq |= (1<<pow_receive_group);
+ cvmx_write_csr(CVMX_CIU_INTX_EN0(core*2), en.u64);
+ }
+ }
+#endif
+}
+
+
+/**
+ * Free a work queue entry received in a intercept callback.
+ *
+ * @param work_queue_entry
+ * Work queue entry to free
+ * @return Zero on success, Negative on failure.
+ */
+int cvm_oct_free_work(void *work_queue_entry)
+{
+ cvmx_wqe_t *work = work_queue_entry;
+
+ int segments = work->word2.s.bufs;
+ cvmx_buf_ptr_t segment_ptr = work->packet_ptr;
+
+ while (segments--) {
+ cvmx_buf_ptr_t next_ptr = *(cvmx_buf_ptr_t *)cvmx_phys_to_ptr(segment_ptr.s.addr-8);
+ if (__predict_false(!segment_ptr.s.i))
+ cvmx_fpa_free(cvm_oct_get_buffer_ptr(segment_ptr), segment_ptr.s.pool, DONT_WRITEBACK(CVMX_FPA_PACKET_POOL_SIZE/128));
+ segment_ptr = next_ptr;
+ }
+ cvmx_fpa_free(work, CVMX_FPA_WQE_POOL, DONT_WRITEBACK(1));
+
+ return 0;
+}
+
+
+/**
+ * Module/ driver initialization. Creates the linux network
+ * devices.
+ *
+ * @return Zero on success
+ */
+int cvm_oct_init_module(device_t bus)
+{
+ device_t dev;
+ int ifnum;
+ int num_interfaces;
+ int interface;
+ int fau = FAU_NUM_PACKET_BUFFERS_TO_FREE;
+ int qos;
+
+ cvm_oct_rx_initialize();
+ cvm_oct_configure_common_hw(bus);
+
+ cvmx_helper_initialize_packet_io_global();
+
+ /* Change the input group for all ports before input is enabled */
+ num_interfaces = cvmx_helper_get_number_of_interfaces();
+ for (interface = 0; interface < num_interfaces; interface++) {
+ int num_ports = cvmx_helper_ports_on_interface(interface);
+ int port;
+
+ for (port = 0; port < num_ports; port++) {
+ cvmx_pip_prt_tagx_t pip_prt_tagx;
+ int pkind = cvmx_helper_get_ipd_port(interface, port);
+
+ pip_prt_tagx.u64 = cvmx_read_csr(CVMX_PIP_PRT_TAGX(pkind));
+ pip_prt_tagx.s.grp = pow_receive_group;
+ cvmx_write_csr(CVMX_PIP_PRT_TAGX(pkind), pip_prt_tagx.u64);
+ }
+ }
+
+ cvmx_helper_ipd_and_packet_input_enable();
+
+ memset(cvm_oct_device, 0, sizeof(cvm_oct_device));
+
+ cvm_oct_link_taskq = taskqueue_create("octe link", M_NOWAIT,
+ taskqueue_thread_enqueue, &cvm_oct_link_taskq);
+ taskqueue_start_threads(&cvm_oct_link_taskq, 1, PI_NET,
+ "octe link taskq");
+
+ /* Initialize the FAU used for counting packet buffers that need to be freed */
+ cvmx_fau_atomic_write32(FAU_NUM_PACKET_BUFFERS_TO_FREE, 0);
+
+ ifnum = 0;
+ num_interfaces = cvmx_helper_get_number_of_interfaces();
+ for (interface = 0; interface < num_interfaces; interface++) {
+ cvmx_helper_interface_mode_t imode = cvmx_helper_interface_get_mode(interface);
+ int num_ports = cvmx_helper_ports_on_interface(interface);
+ int port;
+
+ for (port = cvmx_helper_get_ipd_port(interface, 0);
+ port < cvmx_helper_get_ipd_port(interface, num_ports);
+ ifnum++, port++) {
+ cvm_oct_private_t *priv;
+ struct ifnet *ifp;
+
+ dev = BUS_ADD_CHILD(bus, 0, "octe", ifnum);
+ if (dev != NULL)
+ ifp = if_alloc(IFT_ETHER);
+ if (dev == NULL || ifp == NULL) {
+ printf("Failed to allocate ethernet device for interface %d port %d\n", interface, port);
+ continue;
+ }
+
+ /* Initialize the device private structure. */
+ device_probe(dev);
+ priv = device_get_softc(dev);
+ priv->dev = dev;
+ priv->ifp = ifp;
+ priv->imode = imode;
+ priv->port = port;
+ priv->queue = cvmx_pko_get_base_queue(priv->port);
+ priv->fau = fau - cvmx_pko_get_num_queues(port) * 4;
+ for (qos = 0; qos < cvmx_pko_get_num_queues(port); qos++)
+ cvmx_fau_atomic_write32(priv->fau+qos*4, 0);
+ TASK_INIT(&priv->link_task, 0, cvm_oct_update_link, priv);
+
+ switch (priv->imode) {
+
+ /* These types don't support ports to IPD/PKO */
+ case CVMX_HELPER_INTERFACE_MODE_DISABLED:
+ case CVMX_HELPER_INTERFACE_MODE_PCIE:
+ case CVMX_HELPER_INTERFACE_MODE_PICMG:
+ break;
+
+ case CVMX_HELPER_INTERFACE_MODE_NPI:
+ priv->init = cvm_oct_common_init;
+ priv->uninit = cvm_oct_common_uninit;
+ device_set_desc(dev, "Cavium Octeon NPI Ethernet");
+ break;
+
+ case CVMX_HELPER_INTERFACE_MODE_XAUI:
+ priv->init = cvm_oct_xaui_init;
+ priv->uninit = cvm_oct_common_uninit;
+ device_set_desc(dev, "Cavium Octeon XAUI Ethernet");
+ break;
+
+ case CVMX_HELPER_INTERFACE_MODE_LOOP:
+ priv->init = cvm_oct_common_init;
+ priv->uninit = cvm_oct_common_uninit;
+ device_set_desc(dev, "Cavium Octeon LOOP Ethernet");
+ break;
+
+ case CVMX_HELPER_INTERFACE_MODE_SGMII:
+ priv->init = cvm_oct_sgmii_init;
+ priv->uninit = cvm_oct_common_uninit;
+ device_set_desc(dev, "Cavium Octeon SGMII Ethernet");
+ break;
+
+ case CVMX_HELPER_INTERFACE_MODE_SPI:
+ priv->init = cvm_oct_spi_init;
+ priv->uninit = cvm_oct_spi_uninit;
+ device_set_desc(dev, "Cavium Octeon SPI Ethernet");
+ break;
+
+ case CVMX_HELPER_INTERFACE_MODE_RGMII:
+ priv->init = cvm_oct_rgmii_init;
+ priv->uninit = cvm_oct_rgmii_uninit;
+ device_set_desc(dev, "Cavium Octeon RGMII Ethernet");
+ break;
+
+ case CVMX_HELPER_INTERFACE_MODE_GMII:
+ priv->init = cvm_oct_rgmii_init;
+ priv->uninit = cvm_oct_rgmii_uninit;
+ device_set_desc(dev, "Cavium Octeon GMII Ethernet");
+ break;
+ }
+
+ ifp->if_softc = priv;
+
+ if (!priv->init) {
+ printf("octe%d: unsupported device type interface %d, port %d\n",
+ ifnum, interface, priv->port);
+ if_free(ifp);
+ } else if (priv->init(ifp) != 0) {
+ printf("octe%d: failed to register device for interface %d, port %d\n",
+ ifnum, interface, priv->port);
+ if_free(ifp);
+ } else {
+ cvm_oct_device[priv->port] = ifp;
+ fau -= cvmx_pko_get_num_queues(priv->port) * sizeof(uint32_t);
+ }
+ }
+ }
+
+ if (INTERRUPT_LIMIT) {
+ /* Set the POW timer rate to give an interrupt at most INTERRUPT_LIMIT times per second */
+ cvmx_write_csr(CVMX_POW_WQ_INT_PC, cvmx_clock_get_rate(CVMX_CLOCK_CORE)/(INTERRUPT_LIMIT*16*256)<<8);
+
+ /* Enable POW timer interrupt. It will count when there are packets available */
+ cvmx_write_csr(CVMX_POW_WQ_INT_THRX(pow_receive_group), 0x1ful<<24);
+ } else {
+ /* Enable POW interrupt when our port has at least one packet */
+ cvmx_write_csr(CVMX_POW_WQ_INT_THRX(pow_receive_group), 0x1001);
+ }
+
+ callout_init(&cvm_oct_poll_timer, 1);
+ callout_reset(&cvm_oct_poll_timer, hz, cvm_do_timer, NULL);
+
+ return 0;
+}
+
+
+/**
+ * Module / driver shutdown
+ *
+ * @return Zero on success
+ */
+void cvm_oct_cleanup_module(device_t bus)
+{
+ int port;
+ struct octebus_softc *sc = device_get_softc(bus);
+
+ /* Disable POW interrupt */
+ cvmx_write_csr(CVMX_POW_WQ_INT_THRX(pow_receive_group), 0);
+
+ /* Free the interrupt handler */
+ bus_teardown_intr(bus, sc->sc_rx_irq, sc->sc_rx_intr_cookie);
+
+ callout_stop(&cvm_oct_poll_timer);
+ cvm_oct_rx_shutdown();
+
+ cvmx_helper_shutdown_packet_io_global();
+
+ /* Free the ethernet devices */
+ for (port = 0; port < TOTAL_NUMBER_OF_PORTS; port++) {
+ if (cvm_oct_device[port]) {
+ cvm_oct_tx_shutdown(cvm_oct_device[port]);
+#if 0
+ unregister_netdev(cvm_oct_device[port]);
+ kfree(cvm_oct_device[port]);
+#else
+ panic("%s: need to detach and free interface.", __func__);
+#endif
+ cvm_oct_device[port] = NULL;
+ }
+ }
+ /* Free the HW pools */
+ cvm_oct_mem_empty_fpa(CVMX_FPA_PACKET_POOL, CVMX_FPA_PACKET_POOL_SIZE, num_packet_buffers);
+ cvm_oct_mem_empty_fpa(CVMX_FPA_WQE_POOL, CVMX_FPA_WQE_POOL_SIZE, num_packet_buffers);
+
+ if (CVMX_FPA_OUTPUT_BUFFER_POOL != CVMX_FPA_PACKET_POOL)
+ cvm_oct_mem_empty_fpa(CVMX_FPA_OUTPUT_BUFFER_POOL, CVMX_FPA_OUTPUT_BUFFER_POOL_SIZE, cvm_oct_num_output_buffers);
+
+ /* Disable FPA, all buffers are free, not done by helper shutdown. */
+ cvmx_fpa_disable();
+}
Property changes on: trunk/sys/mips/cavium/octe/ethernet.c
___________________________________________________________________
Added: svn:eol-style
## -0,0 +1 ##
+native
\ No newline at end of property
Added: svn:keywords
## -0,0 +1 ##
+MidnightBSD=%H
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+text/plain
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Added: trunk/sys/mips/cavium/octe/mv88e61xxphy.c
===================================================================
--- trunk/sys/mips/cavium/octe/mv88e61xxphy.c (rev 0)
+++ trunk/sys/mips/cavium/octe/mv88e61xxphy.c 2018-05-26 21:55:02 UTC (rev 9987)
@@ -0,0 +1,631 @@
+/* $MidnightBSD$ */
+/*-
+ * Copyright (c) 2010 Juli Mallett <jmallett at FreeBSD.org>
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ * $FreeBSD: stable/10/sys/mips/cavium/octe/mv88e61xxphy.c 213762 2010-10-13 09:17:44Z jmallett $
+ */
+
+#include <sys/cdefs.h>
+__FBSDID("$FreeBSD: stable/10/sys/mips/cavium/octe/mv88e61xxphy.c 213762 2010-10-13 09:17:44Z jmallett $");
+
+/*
+ * Driver for the Marvell 88E61xx family of switch PHYs
+ */
+
+#include <sys/param.h>
+#include <sys/systm.h>
+#include <sys/kernel.h>
+#include <sys/socket.h>
+#include <sys/errno.h>
+#include <sys/module.h>
+#include <sys/bus.h>
+#include <sys/sysctl.h>
+
+#include <net/ethernet.h>
+#include <net/if.h>
+#include <net/if_media.h>
+
+#include "miibus_if.h"
+
+#include "mv88e61xxphyreg.h"
+
+struct mv88e61xxphy_softc;
+
+struct mv88e61xxphy_port_softc {
+ struct mv88e61xxphy_softc *sc_switch;
+ unsigned sc_port;
+ unsigned sc_domain;
+ unsigned sc_vlan;
+ unsigned sc_priority;
+ unsigned sc_flags;
+};
+
+#define MV88E61XXPHY_PORT_FLAG_VTU_UPDATE (0x0001)
+
+struct mv88e61xxphy_softc {
+ device_t sc_dev;
+ struct mv88e61xxphy_port_softc sc_ports[MV88E61XX_PORTS];
+};
+
+enum mv88e61xxphy_vtu_membership_type {
+ MV88E61XXPHY_VTU_UNMODIFIED,
+ MV88E61XXPHY_VTU_UNTAGGED,
+ MV88E61XXPHY_VTU_TAGGED,
+ MV88E61XXPHY_VTU_DISCARDED,
+};
+
+enum mv88e61xxphy_sysctl_link_type {
+ MV88E61XXPHY_LINK_SYSCTL_DUPLEX,
+ MV88E61XXPHY_LINK_SYSCTL_LINK,
+ MV88E61XXPHY_LINK_SYSCTL_MEDIA,
+};
+
+enum mv88e61xxphy_sysctl_port_type {
+ MV88E61XXPHY_PORT_SYSCTL_DOMAIN,
+ MV88E61XXPHY_PORT_SYSCTL_VLAN,
+ MV88E61XXPHY_PORT_SYSCTL_PRIORITY,
+};
+
+/*
+ * Register access macros.
+ */
+#define MV88E61XX_READ(sc, phy, reg) \
+ MIIBUS_READREG(device_get_parent((sc)->sc_dev), (phy), (reg))
+
+#define MV88E61XX_WRITE(sc, phy, reg, val) \
+ MIIBUS_WRITEREG(device_get_parent((sc)->sc_dev), (phy), (reg), (val))
+
+#define MV88E61XX_READ_PORT(psc, reg) \
+ MV88E61XX_READ((psc)->sc_switch, MV88E61XX_PORT((psc)->sc_port), (reg))
+
+#define MV88E61XX_WRITE_PORT(psc, reg, val) \
+ MV88E61XX_WRITE((psc)->sc_switch, MV88E61XX_PORT((psc)->sc_port), (reg), (val))
+
+static int mv88e61xxphy_probe(device_t);
+static int mv88e61xxphy_attach(device_t);
+
+static void mv88e61xxphy_init(struct mv88e61xxphy_softc *);
+static void mv88e61xxphy_init_port(struct mv88e61xxphy_port_softc *);
+static void mv88e61xxphy_init_vtu(struct mv88e61xxphy_softc *);
+static int mv88e61xxphy_sysctl_link_proc(SYSCTL_HANDLER_ARGS);
+static int mv88e61xxphy_sysctl_port_proc(SYSCTL_HANDLER_ARGS);
+static void mv88e61xxphy_vtu_load(struct mv88e61xxphy_softc *, uint16_t);
+static void mv88e61xxphy_vtu_set_membership(struct mv88e61xxphy_softc *, unsigned, enum mv88e61xxphy_vtu_membership_type);
+static void mv88e61xxphy_vtu_wait(struct mv88e61xxphy_softc *);
+
+static int
+mv88e61xxphy_probe(device_t dev)
+{
+ uint16_t val;
+
+ val = MIIBUS_READREG(device_get_parent(dev), MV88E61XX_PORT(0),
+ MV88E61XX_PORT_REVISION);
+ switch (val >> 4) {
+ case 0x121:
+ device_set_desc(dev, "Marvell Link Street 88E6123 3-Port Gigabit Switch");
+ return (0);
+ case 0x161:
+ device_set_desc(dev, "Marvell Link Street 88E6161 6-Port Gigabit Switch");
+ return (0);
+ case 0x165:
+ device_set_desc(dev, "Marvell Link Street 88E6161 6-Port Advanced Gigabit Switch");
+ return (0);
+ default:
+ return (ENXIO);
+ }
+}
+
+static int
+mv88e61xxphy_attach(device_t dev)
+{
+ char portbuf[] = "N";
+ struct sysctl_ctx_list *ctx = device_get_sysctl_ctx(dev);
+ struct sysctl_oid *tree = device_get_sysctl_tree(dev);
+ struct sysctl_oid_list *child = SYSCTL_CHILDREN(tree);
+ struct sysctl_oid *port_node, *portN_node;
+ struct sysctl_oid_list *port_tree, *portN_tree;
+ struct mv88e61xxphy_softc *sc;
+ unsigned port;
+
+ sc = device_get_softc(dev);
+ sc->sc_dev = dev;
+
+ /*
+ * Initialize port softcs.
+ */
+ for (port = 0; port < MV88E61XX_PORTS; port++) {
+ struct mv88e61xxphy_port_softc *psc;
+
+ psc = &sc->sc_ports[port];
+ psc->sc_switch = sc;
+ psc->sc_port = port;
+ psc->sc_domain = 0; /* One broadcast domain by default. */
+ psc->sc_vlan = port + 1; /* Tag VLANs by default. */
+ psc->sc_priority = 0; /* No default special priority. */
+ psc->sc_flags = 0;
+ }
+
+ /*
+ * Add per-port sysctl tree/handlers.
+ */
+ port_node = SYSCTL_ADD_NODE(ctx, child, OID_AUTO, "port",
+ CTLFLAG_RD, NULL, "Switch Ports");
+ port_tree = SYSCTL_CHILDREN(port_node);
+ for (port = 0; port < MV88E61XX_PORTS; port++) {
+ struct mv88e61xxphy_port_softc *psc;
+
+ psc = &sc->sc_ports[port];
+
+ portbuf[0] = '0' + port;
+ portN_node = SYSCTL_ADD_NODE(ctx, port_tree, OID_AUTO, portbuf,
+ CTLFLAG_RD, NULL, "Switch Port");
+ portN_tree = SYSCTL_CHILDREN(portN_node);
+
+ SYSCTL_ADD_PROC(ctx, portN_tree, OID_AUTO, "duplex",
+ CTLFLAG_RD | CTLTYPE_INT, psc,
+ MV88E61XXPHY_LINK_SYSCTL_DUPLEX,
+ mv88e61xxphy_sysctl_link_proc, "IU",
+ "Media duplex status (0 = half duplex; 1 = full duplex)");
+
+ SYSCTL_ADD_PROC(ctx, portN_tree, OID_AUTO, "link",
+ CTLFLAG_RD | CTLTYPE_INT, psc,
+ MV88E61XXPHY_LINK_SYSCTL_LINK,
+ mv88e61xxphy_sysctl_link_proc, "IU",
+ "Link status (0 = down; 1 = up)");
+
+ SYSCTL_ADD_PROC(ctx, portN_tree, OID_AUTO, "media",
+ CTLFLAG_RD | CTLTYPE_INT, psc,
+ MV88E61XXPHY_LINK_SYSCTL_MEDIA,
+ mv88e61xxphy_sysctl_link_proc, "IU",
+ "Media speed (0 = unknown; 10 = 10Mbps; 100 = 100Mbps; 1000 = 1Gbps)");
+
+ SYSCTL_ADD_PROC(ctx, portN_tree, OID_AUTO, "domain",
+ CTLFLAG_RW | CTLTYPE_INT, psc,
+ MV88E61XXPHY_PORT_SYSCTL_DOMAIN,
+ mv88e61xxphy_sysctl_port_proc, "IU",
+ "Broadcast domain (ports can only talk to other ports in the same domain)");
+
+ SYSCTL_ADD_PROC(ctx, portN_tree, OID_AUTO, "vlan",
+ CTLFLAG_RW | CTLTYPE_INT, psc,
+ MV88E61XXPHY_PORT_SYSCTL_VLAN,
+ mv88e61xxphy_sysctl_port_proc, "IU",
+ "Tag packets from/for this port with a given VLAN.");
+
+ SYSCTL_ADD_PROC(ctx, portN_tree, OID_AUTO, "priority",
+ CTLFLAG_RW | CTLTYPE_INT, psc,
+ MV88E61XXPHY_PORT_SYSCTL_PRIORITY,
+ mv88e61xxphy_sysctl_port_proc, "IU",
+ "Default packet priority for this port.");
+ }
+
+ mv88e61xxphy_init(sc);
+
+ return (0);
+}
+
+static void
+mv88e61xxphy_init(struct mv88e61xxphy_softc *sc)
+{
+ unsigned port;
+ uint16_t val;
+ unsigned i;
+
+ /* Disable all ports. */
+ for (port = 0; port < MV88E61XX_PORTS; port++) {
+ struct mv88e61xxphy_port_softc *psc;
+
+ psc = &sc->sc_ports[port];
+
+ val = MV88E61XX_READ_PORT(psc, MV88E61XX_PORT_CONTROL);
+ val &= ~0x3;
+ MV88E61XX_WRITE_PORT(psc, MV88E61XX_PORT_CONTROL, val);
+ }
+
+ DELAY(2000);
+
+ /* Reset the switch. */
+ MV88E61XX_WRITE(sc, MV88E61XX_GLOBAL, MV88E61XX_GLOBAL_CONTROL, 0xc400);
+ for (i = 0; i < 100; i++) {
+ val = MV88E61XX_READ(sc, MV88E61XX_GLOBAL, MV88E61XX_GLOBAL_STATUS);
+ if ((val & 0xc800) == 0xc800)
+ break;
+ DELAY(10);
+ }
+ if (i == 100) {
+ device_printf(sc->sc_dev, "%s: switch reset timed out.\n", __func__);
+ return;
+ }
+
+ /* Disable PPU. */
+ MV88E61XX_WRITE(sc, MV88E61XX_GLOBAL, MV88E61XX_GLOBAL_CONTROL, 0x0000);
+
+ /* Configure host port and send monitor frames to it. */
+ MV88E61XX_WRITE(sc, MV88E61XX_GLOBAL, MV88E61XX_GLOBAL_MONITOR,
+ (MV88E61XX_HOST_PORT << 12) | (MV88E61XX_HOST_PORT << 8) |
+ (MV88E61XX_HOST_PORT << 4));
+
+ /* Disable remote management. */
+ MV88E61XX_WRITE(sc, MV88E61XX_GLOBAL, MV88E61XX_GLOBAL_REMOTE_MGMT, 0x0000);
+
+ /* Send all specifically-addressed frames to the host port. */
+ MV88E61XX_WRITE(sc, MV88E61XX_GLOBAL2, MV88E61XX_GLOBAL2_MANAGE_2X, 0xffff);
+ MV88E61XX_WRITE(sc, MV88E61XX_GLOBAL2, MV88E61XX_GLOBAL2_MANAGE_0X, 0xffff);
+
+ /* Remove provider-supplied tag and use it for switching. */
+ MV88E61XX_WRITE(sc, MV88E61XX_GLOBAL2, MV88E61XX_GLOBAL2_CONTROL2,
+ MV88E61XX_GLOBAL2_CONTROL2_REMOVE_PTAG);
+
+ /* Configure all ports. */
+ for (port = 0; port < MV88E61XX_PORTS; port++) {
+ struct mv88e61xxphy_port_softc *psc;
+
+ psc = &sc->sc_ports[port];
+ mv88e61xxphy_init_port(psc);
+ }
+
+ /* Reprogram VLAN table (VTU.) */
+ mv88e61xxphy_init_vtu(sc);
+
+ /* Enable all ports. */
+ for (port = 0; port < MV88E61XX_PORTS; port++) {
+ struct mv88e61xxphy_port_softc *psc;
+
+ psc = &sc->sc_ports[port];
+
+ val = MV88E61XX_READ_PORT(psc, MV88E61XX_PORT_CONTROL);
+ val |= 0x3;
+ MV88E61XX_WRITE_PORT(psc, MV88E61XX_PORT_CONTROL, val);
+ }
+}
+
+static void
+mv88e61xxphy_init_port(struct mv88e61xxphy_port_softc *psc)
+{
+ struct mv88e61xxphy_softc *sc;
+ unsigned allow_mask;
+
+ sc = psc->sc_switch;
+
+ /* Set media type and flow control. */
+ if (psc->sc_port != MV88E61XX_HOST_PORT) {
+ /* Don't force any media type or flow control. */
+ MV88E61XX_WRITE_PORT(psc, MV88E61XX_PORT_FORCE_MAC, 0x0003);
+ } else {
+ /* Make CPU port 1G FDX. */
+ MV88E61XX_WRITE_PORT(psc, MV88E61XX_PORT_FORCE_MAC, 0x003e);
+ }
+
+ /* Don't limit flow control pauses. */
+ MV88E61XX_WRITE_PORT(psc, MV88E61XX_PORT_PAUSE_CONTROL, 0x0000);
+
+ /* Set various port functions per Linux. */
+ if (psc->sc_port != MV88E61XX_HOST_PORT) {
+ MV88E61XX_WRITE_PORT(psc, MV88E61XX_PORT_CONTROL, 0x04bc);
+ } else {
+ /*
+ * Send frames for unknown unicast and multicast groups to
+ * host, too.
+ */
+ MV88E61XX_WRITE_PORT(psc, MV88E61XX_PORT_CONTROL, 0x063f);
+ }
+
+ if (psc->sc_port != MV88E61XX_HOST_PORT) {
+ /* Disable trunking. */
+ MV88E61XX_WRITE_PORT(psc, MV88E61XX_PORT_CONTROL2, 0x0000);
+ } else {
+ /* Disable trunking and send learn messages to host. */
+ MV88E61XX_WRITE_PORT(psc, MV88E61XX_PORT_CONTROL2, 0x8000);
+ }
+
+ /*
+ * Port-based VLAN map; isolates MAC tables and forces ports to talk
+ * only to the host.
+ *
+ * Always allow the host to send to all ports and allow all ports to
+ * send to the host.
+ */
+ if (psc->sc_port != MV88E61XX_HOST_PORT) {
+ allow_mask = 1 << MV88E61XX_HOST_PORT;
+ } else {
+ allow_mask = (1 << MV88E61XX_PORTS) - 1;
+ allow_mask &= ~(1 << MV88E61XX_HOST_PORT);
+ }
+ MV88E61XX_WRITE_PORT(psc, MV88E61XX_PORT_VLAN_MAP,
+ (psc->sc_domain << 12) | allow_mask);
+
+ /* VLAN tagging. Set default priority and VLAN tag (or none.) */
+ MV88E61XX_WRITE_PORT(psc, MV88E61XX_PORT_VLAN,
+ (psc->sc_priority << 14) | psc->sc_vlan);
+
+ if (psc->sc_port == MV88E61XX_HOST_PORT) {
+ /* Set provider ingress tag. */
+ MV88E61XX_WRITE_PORT(psc, MV88E61XX_PORT_PROVIDER_PROTO,
+ ETHERTYPE_VLAN);
+
+ /* Set provider egress tag. */
+ MV88E61XX_WRITE_PORT(psc, MV88E61XX_PORT_ETHER_PROTO,
+ ETHERTYPE_VLAN);
+
+ /* Use secure 802.1q mode and accept only tagged frames. */
+ MV88E61XX_WRITE_PORT(psc, MV88E61XX_PORT_FILTER,
+ MV88E61XX_PORT_FILTER_MAP_DEST |
+ MV88E61XX_PORT_FILTER_8021Q_SECURE |
+ MV88E61XX_PORT_FILTER_DISCARD_UNTAGGED);
+ } else {
+ /* Don't allow tagged frames. */
+ MV88E61XX_WRITE_PORT(psc, MV88E61XX_PORT_FILTER,
+ MV88E61XX_PORT_FILTER_MAP_DEST |
+ MV88E61XX_PORT_FILTER_DISCARD_TAGGED);
+ }
+}
+
+static void
+mv88e61xxphy_init_vtu(struct mv88e61xxphy_softc *sc)
+{
+ unsigned port;
+
+ /*
+ * Start flush of the VTU.
+ */
+ mv88e61xxphy_vtu_wait(sc);
+ MV88E61XX_WRITE(sc, MV88E61XX_GLOBAL, MV88E61XX_GLOBAL_VTU_OP,
+ MV88E61XX_GLOBAL_VTU_OP_BUSY | MV88E61XX_GLOBAL_VTU_OP_OP_FLUSH);
+
+ /*
+ * Queue each port's VLAN to be programmed.
+ */
+ for (port = 0; port < MV88E61XX_PORTS; port++) {
+ struct mv88e61xxphy_port_softc *psc;
+
+ psc = &sc->sc_ports[port];
+ psc->sc_flags &= ~MV88E61XXPHY_PORT_FLAG_VTU_UPDATE;
+ if (psc->sc_vlan == 0)
+ continue;
+ psc->sc_flags |= MV88E61XXPHY_PORT_FLAG_VTU_UPDATE;
+ }
+
+ /*
+ * Program each VLAN that is in use.
+ */
+ for (port = 0; port < MV88E61XX_PORTS; port++) {
+ struct mv88e61xxphy_port_softc *psc;
+
+ psc = &sc->sc_ports[port];
+ if ((psc->sc_flags & MV88E61XXPHY_PORT_FLAG_VTU_UPDATE) == 0)
+ continue;
+ mv88e61xxphy_vtu_load(sc, psc->sc_vlan);
+ }
+
+ /*
+ * Wait for last pending VTU operation to complete.
+ */
+ mv88e61xxphy_vtu_wait(sc);
+}
+
+static int
+mv88e61xxphy_sysctl_link_proc(SYSCTL_HANDLER_ARGS)
+{
+ struct mv88e61xxphy_port_softc *psc = arg1;
+ enum mv88e61xxphy_sysctl_link_type type = arg2;
+ uint16_t val;
+ unsigned out;
+
+ val = MV88E61XX_READ_PORT(psc, MV88E61XX_PORT_STATUS);
+ switch (type) {
+ case MV88E61XXPHY_LINK_SYSCTL_DUPLEX:
+ if ((val & MV88E61XX_PORT_STATUS_DUPLEX) != 0)
+ out = 1;
+ else
+ out = 0;
+ break;
+ case MV88E61XXPHY_LINK_SYSCTL_LINK:
+ if ((val & MV88E61XX_PORT_STATUS_LINK) != 0)
+ out = 1;
+ else
+ out = 0;
+ break;
+ case MV88E61XXPHY_LINK_SYSCTL_MEDIA:
+ switch (val & MV88E61XX_PORT_STATUS_MEDIA) {
+ case MV88E61XX_PORT_STATUS_MEDIA_10M:
+ out = 10;
+ break;
+ case MV88E61XX_PORT_STATUS_MEDIA_100M:
+ out = 100;
+ break;
+ case MV88E61XX_PORT_STATUS_MEDIA_1G:
+ out = 1000;
+ break;
+ default:
+ out = 0;
+ break;
+ }
+ break;
+ default:
+ return (EINVAL);
+ }
+ return (sysctl_handle_int(oidp, NULL, out, req));
+}
+
+static int
+mv88e61xxphy_sysctl_port_proc(SYSCTL_HANDLER_ARGS)
+{
+ struct mv88e61xxphy_port_softc *psc = arg1;
+ enum mv88e61xxphy_sysctl_port_type type = arg2;
+ struct mv88e61xxphy_softc *sc = psc->sc_switch;
+ unsigned max, val, *valp;
+ int error;
+
+ switch (type) {
+ case MV88E61XXPHY_PORT_SYSCTL_DOMAIN:
+ valp = &psc->sc_domain;
+ max = 0xf;
+ break;
+ case MV88E61XXPHY_PORT_SYSCTL_VLAN:
+ valp = &psc->sc_vlan;
+ max = 0x1000;
+ break;
+ case MV88E61XXPHY_PORT_SYSCTL_PRIORITY:
+ valp = &psc->sc_priority;
+ max = 3;
+ break;
+ default:
+ return (EINVAL);
+ }
+
+ val = *valp;
+ error = sysctl_handle_int(oidp, &val, 0, req);
+ if (error != 0 || req->newptr == NULL)
+ return (error);
+
+ /* Bounds check value. */
+ if (val >= max)
+ return (EINVAL);
+
+ /* Reinitialize switch with new value. */
+ *valp = val;
+ mv88e61xxphy_init(sc);
+
+ return (0);
+}
+
+static void
+mv88e61xxphy_vtu_load(struct mv88e61xxphy_softc *sc, uint16_t vid)
+{
+ unsigned port;
+
+ /*
+ * Wait for previous operation to complete.
+ */
+ mv88e61xxphy_vtu_wait(sc);
+
+ /*
+ * Set VID.
+ */
+ MV88E61XX_WRITE(sc, MV88E61XX_GLOBAL, MV88E61XX_GLOBAL_VTU_VID,
+ MV88E61XX_GLOBAL_VTU_VID_VALID | vid);
+
+ /*
+ * Add ports to this VTU.
+ */
+ for (port = 0; port < MV88E61XX_PORTS; port++) {
+ struct mv88e61xxphy_port_softc *psc;
+
+ psc = &sc->sc_ports[port];
+ if (psc->sc_vlan == vid) {
+ /*
+ * Send this port its VLAN traffic untagged.
+ */
+ psc->sc_flags &= ~MV88E61XXPHY_PORT_FLAG_VTU_UPDATE;
+ mv88e61xxphy_vtu_set_membership(sc, port, MV88E61XXPHY_VTU_UNTAGGED);
+ } else if (psc->sc_port == MV88E61XX_HOST_PORT) {
+ /*
+ * The host sees all VLANs tagged.
+ */
+ mv88e61xxphy_vtu_set_membership(sc, port, MV88E61XXPHY_VTU_TAGGED);
+ } else {
+ /*
+ * This port isn't on this VLAN.
+ */
+ mv88e61xxphy_vtu_set_membership(sc, port, MV88E61XXPHY_VTU_DISCARDED);
+ }
+ }
+
+ /*
+ * Start adding this entry.
+ */
+ MV88E61XX_WRITE(sc, MV88E61XX_GLOBAL, MV88E61XX_GLOBAL_VTU_OP,
+ MV88E61XX_GLOBAL_VTU_OP_BUSY |
+ MV88E61XX_GLOBAL_VTU_OP_OP_VTU_LOAD);
+}
+
+static void
+mv88e61xxphy_vtu_set_membership(struct mv88e61xxphy_softc *sc, unsigned port,
+ enum mv88e61xxphy_vtu_membership_type type)
+{
+ unsigned shift, reg;
+ uint16_t bits;
+ uint16_t val;
+
+ switch (type) {
+ case MV88E61XXPHY_VTU_UNMODIFIED:
+ bits = 0;
+ break;
+ case MV88E61XXPHY_VTU_UNTAGGED:
+ bits = 1;
+ break;
+ case MV88E61XXPHY_VTU_TAGGED:
+ bits = 2;
+ break;
+ case MV88E61XXPHY_VTU_DISCARDED:
+ bits = 3;
+ break;
+ default:
+ return;
+ }
+
+ if (port < 4) {
+ reg = MV88E61XX_GLOBAL_VTU_DATA_P0P3;
+ shift = port * 4;
+ } else {
+ reg = MV88E61XX_GLOBAL_VTU_DATA_P4P5;
+ shift = (port - 4) * 4;
+ }
+
+ val = MV88E61XX_READ(sc, MV88E61XX_GLOBAL, reg);
+ val |= bits << shift;
+ MV88E61XX_WRITE(sc, MV88E61XX_GLOBAL, reg, val);
+}
+
+static void
+mv88e61xxphy_vtu_wait(struct mv88e61xxphy_softc *sc)
+{
+ uint16_t val;
+
+ for (;;) {
+ val = MV88E61XX_READ(sc, MV88E61XX_GLOBAL, MV88E61XX_GLOBAL_VTU_OP);
+ if ((val & MV88E61XX_GLOBAL_VTU_OP_BUSY) == 0)
+ return;
+ }
+}
+
+static device_method_t mv88e61xxphy_methods[] = {
+ /* device interface */
+ DEVMETHOD(device_probe, mv88e61xxphy_probe),
+ DEVMETHOD(device_attach, mv88e61xxphy_attach),
+ DEVMETHOD(device_detach, bus_generic_detach),
+ DEVMETHOD(device_shutdown, bus_generic_shutdown),
+
+ { 0, 0 }
+};
+
+static devclass_t mv88e61xxphy_devclass;
+
+static driver_t mv88e61xxphy_driver = {
+ "mv88e61xxphy",
+ mv88e61xxphy_methods,
+ sizeof(struct mv88e61xxphy_softc)
+};
+
+DRIVER_MODULE(mv88e61xxphy, octe, mv88e61xxphy_driver, mv88e61xxphy_devclass, 0, 0);
Property changes on: trunk/sys/mips/cavium/octe/mv88e61xxphy.c
___________________________________________________________________
Added: svn:eol-style
## -0,0 +1 ##
+native
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## -0,0 +1 ##
+MidnightBSD=%H
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Added: svn:mime-type
## -0,0 +1 ##
+text/plain
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Added: trunk/sys/mips/cavium/octe/mv88e61xxphyreg.h
===================================================================
--- trunk/sys/mips/cavium/octe/mv88e61xxphyreg.h (rev 0)
+++ trunk/sys/mips/cavium/octe/mv88e61xxphyreg.h 2018-05-26 21:55:02 UTC (rev 9987)
@@ -0,0 +1,150 @@
+/* $MidnightBSD$ */
+/*-
+ * Copyright (c) 2010 Juli Mallett <jmallett at FreeBSD.org>
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ * $FreeBSD: stable/10/sys/mips/cavium/octe/mv88e61xxphyreg.h 213762 2010-10-13 09:17:44Z jmallett $
+ */
+
+/*
+ * Register definitions for Marvell MV88E61XX
+ *
+ * Note that names and definitions were gleaned from Linux and U-Boot patches
+ * released by Marvell, often by looking at contextual use of the registers
+ * involved, and may not be representative of the full functionality of those
+ * registers and are certainly not an exhaustive enumeration of registers.
+ *
+ * For an exhaustive enumeration of registers, check out the QD-DSDT package
+ * included in the Marvell ARM Feroceon Board Support Package for Linux.
+ */
+
+#ifndef _MIPS_CAVIUM_OCTE_MV88E61XXPHYREG_H_
+#define _MIPS_CAVIUM_OCTE_MV88E61XXPHYREG_H_
+
+/*
+ * Port addresses & per-port registers.
+ */
+#define MV88E61XX_PORT(x) (0x10 + (x))
+#define MV88E61XX_HOST_PORT (5)
+#define MV88E61XX_PORTS (6)
+
+#define MV88E61XX_PORT_STATUS (0x00)
+#define MV88E61XX_PORT_FORCE_MAC (0x01)
+#define MV88E61XX_PORT_PAUSE_CONTROL (0x02)
+#define MV88E61XX_PORT_REVISION (0x03)
+#define MV88E61XX_PORT_CONTROL (0x04)
+#define MV88E61XX_PORT_CONTROL2 (0x05)
+#define MV88E61XX_PORT_VLAN_MAP (0x06)
+#define MV88E61XX_PORT_VLAN (0x07)
+#define MV88E61XX_PORT_FILTER (0x08)
+#define MV88E61XX_PORT_EGRESS_CONTROL (0x09)
+#define MV88E61XX_PORT_EGRESS_CONTROL2 (0x0a)
+#define MV88E61XX_PORT_PORT_LEARN (0x0b)
+#define MV88E61XX_PORT_ATU_CONTROL (0x0c)
+#define MV88E61XX_PORT_PRIORITY_CONTROL (0x0d)
+#define MV88E61XX_PORT_ETHER_PROTO (0x0f)
+#define MV88E61XX_PORT_PROVIDER_PROTO (0x1a)
+#define MV88E61XX_PORT_PRIORITY_MAP (0x18)
+#define MV88E61XX_PORT_PRIORITY_MAP2 (0x19)
+
+/*
+ * Fields and values in each register.
+ */
+#define MV88E61XX_PORT_STATUS_MEDIA (0x0300)
+#define MV88E61XX_PORT_STATUS_MEDIA_10M (0x0000)
+#define MV88E61XX_PORT_STATUS_MEDIA_100M (0x0100)
+#define MV88E61XX_PORT_STATUS_MEDIA_1G (0x0200)
+#define MV88E61XX_PORT_STATUS_DUPLEX (0x0400)
+#define MV88E61XX_PORT_STATUS_LINK (0x0800)
+#define MV88E61XX_PORT_STATUS_FC (0x8000)
+
+#define MV88E61XX_PORT_CONTROL_DOUBLE_TAG (0x0200)
+
+#define MV88E61XX_PORT_FILTER_MAP_DEST (0x0080)
+#define MV88E61XX_PORT_FILTER_DISCARD_UNTAGGED (0x0100)
+#define MV88E61XX_PORT_FILTER_DISCARD_TAGGED (0x0200)
+#define MV88E61XX_PORT_FILTER_8021Q_MODE (0x0c00)
+#define MV88E61XX_PORT_FILTER_8021Q_DISABLED (0x0000)
+#define MV88E61XX_PORT_FILTER_8021Q_FALLBACK (0x0400)
+#define MV88E61XX_PORT_FILTER_8021Q_CHECK (0x0800)
+#define MV88E61XX_PORT_FILTER_8021Q_SECURE (0x0c00)
+
+/*
+ * Global address & global registers.
+ */
+#define MV88E61XX_GLOBAL (0x1b)
+
+#define MV88E61XX_GLOBAL_STATUS (0x00)
+#define MV88E61XX_GLOBAL_CONTROL (0x04)
+#define MV88E61XX_GLOBAL_VTU_OP (0x05)
+#define MV88E61XX_GLOBAL_VTU_VID (0x06)
+#define MV88E61XX_GLOBAL_VTU_DATA_P0P3 (0x07)
+#define MV88E61XX_GLOBAL_VTU_DATA_P4P5 (0x08)
+#define MV88E61XX_GLOBAL_ATU_CONTROL (0x0a)
+#define MV88E61XX_GLOBAL_PRIORITY_MAP (0x18)
+#define MV88E61XX_GLOBAL_MONITOR (0x1a)
+#define MV88E61XX_GLOBAL_REMOTE_MGMT (0x1c)
+#define MV88E61XX_GLOBAL_STATS (0x1d)
+
+/*
+ * Fields and values in each register.
+ */
+#define MV88E61XX_GLOBAL_VTU_OP_BUSY (0x8000)
+#define MV88E61XX_GLOBAL_VTU_OP_OP (0x7000)
+#define MV88E61XX_GLOBAL_VTU_OP_OP_FLUSH (0x1000)
+#define MV88E61XX_GLOBAL_VTU_OP_OP_VTU_LOAD (0x3000)
+
+#define MV88E61XX_GLOBAL_VTU_VID_VALID (0x1000)
+
+/*
+ * Second global address & second global registers.
+ */
+#define MV88E61XX_GLOBAL2 (0x1c)
+
+#define MV88E61XX_GLOBAL2_MANAGE_2X (0x02)
+#define MV88E61XX_GLOBAL2_MANAGE_0X (0x03)
+#define MV88E61XX_GLOBAL2_CONTROL2 (0x05)
+#define MV88E61XX_GLOBAL2_TRUNK_MASK (0x07)
+#define MV88E61XX_GLOBAL2_TRUNK_MAP (0x08)
+#define MV88E61XX_GLOBAL2_RATELIMIT (0x09)
+#define MV88E61XX_GLOBAL2_VLAN_CONTROL (0x0b)
+#define MV88E61XX_GLOBAL2_MAC_ADDRESS (0x0d)
+
+/*
+ * Fields and values in each register.
+ */
+#define MV88E61XX_GLOBAL2_CONTROL2_DOUBLE_USE (0x8000)
+#define MV88E61XX_GLOBAL2_CONTROL2_LOOP_PREVENT (0x4000)
+#define MV88E61XX_GLOBAL2_CONTROL2_FLOW_MESSAGE (0x2000)
+#define MV88E61XX_GLOBAL2_CONTROL2_FLOOD_BC (0x1000)
+#define MV88E61XX_GLOBAL2_CONTROL2_REMOVE_PTAG (0x0800)
+#define MV88E61XX_GLOBAL2_CONTROL2_AGE_INT (0x0400)
+#define MV88E61XX_GLOBAL2_CONTROL2_FLOW_TAG (0x0200)
+#define MV88E61XX_GLOBAL2_CONTROL2_ALWAYS_VTU (0x0100)
+#define MV88E61XX_GLOBAL2_CONTROL2_FORCE_FC_PRI (0x0080)
+#define MV88E61XX_GLOBAL2_CONTROL2_FC_PRI (0x0070)
+#define MV88E61XX_GLOBAL2_CONTROL2_MGMT_TO_HOST (0x0008)
+#define MV88E61XX_GLOBAL2_CONTROL2_MGMT_PRI (0x0007)
+
+#endif /* !_MIPS_CAVIUM_OCTE_MV88E61XXPHYREG_H_ */
Property changes on: trunk/sys/mips/cavium/octe/mv88e61xxphyreg.h
___________________________________________________________________
Added: svn:eol-style
## -0,0 +1 ##
+native
\ No newline at end of property
Added: svn:keywords
## -0,0 +1 ##
+MidnightBSD=%H
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+text/plain
\ No newline at end of property
Added: trunk/sys/mips/cavium/octe/octe.c
===================================================================
--- trunk/sys/mips/cavium/octe/octe.c (rev 0)
+++ trunk/sys/mips/cavium/octe/octe.c 2018-05-26 21:55:02 UTC (rev 9987)
@@ -0,0 +1,492 @@
+/* $MidnightBSD$ */
+/*-
+ * Copyright (c) 2010 Juli Mallett <jmallett at FreeBSD.org>
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ * $FreeBSD: stable/10/sys/mips/cavium/octe/octe.c 221407 2011-05-03 19:51:29Z marius $
+ */
+
+/*
+ * Cavium Octeon Ethernet devices.
+ *
+ * XXX This file should be moved to if_octe.c
+ * XXX The driver may have sufficient locking but we need locking to protect
+ * the interfaces presented here, right?
+ */
+
+#include "opt_inet.h"
+
+#include <sys/param.h>
+#include <sys/systm.h>
+#include <sys/bus.h>
+#include <sys/endian.h>
+#include <sys/kernel.h>
+#include <sys/mbuf.h>
+#include <sys/lock.h>
+#include <sys/module.h>
+#include <sys/mutex.h>
+#include <sys/rman.h>
+#include <sys/socket.h>
+#include <sys/sockio.h>
+#include <sys/sysctl.h>
+
+#include <net/bpf.h>
+#include <net/ethernet.h>
+#include <net/if.h>
+#include <net/if_dl.h>
+#include <net/if_media.h>
+#include <net/if_types.h>
+#include <net/if_var.h>
+#include <net/if_vlan_var.h>
+
+#ifdef INET
+#include <netinet/in.h>
+#include <netinet/if_ether.h>
+#endif
+
+#include <dev/mii/mii.h>
+#include <dev/mii/miivar.h>
+
+#include "wrapper-cvmx-includes.h"
+#include "cavium-ethernet.h"
+
+#include "ethernet-common.h"
+#include "ethernet-defines.h"
+#include "ethernet-mdio.h"
+#include "ethernet-tx.h"
+
+#include "miibus_if.h"
+
+#define OCTE_TX_LOCK(priv) mtx_lock(&(priv)->tx_mtx)
+#define OCTE_TX_UNLOCK(priv) mtx_unlock(&(priv)->tx_mtx)
+
+static int octe_probe(device_t);
+static int octe_attach(device_t);
+static int octe_detach(device_t);
+static int octe_shutdown(device_t);
+
+static int octe_miibus_readreg(device_t, int, int);
+static int octe_miibus_writereg(device_t, int, int, int);
+
+static void octe_init(void *);
+static void octe_stop(void *);
+static int octe_transmit(struct ifnet *, struct mbuf *);
+
+static int octe_mii_medchange(struct ifnet *);
+static void octe_mii_medstat(struct ifnet *, struct ifmediareq *);
+
+static int octe_medchange(struct ifnet *);
+static void octe_medstat(struct ifnet *, struct ifmediareq *);
+
+static int octe_ioctl(struct ifnet *, u_long, caddr_t);
+
+static device_method_t octe_methods[] = {
+ /* Device interface */
+ DEVMETHOD(device_probe, octe_probe),
+ DEVMETHOD(device_attach, octe_attach),
+ DEVMETHOD(device_detach, octe_detach),
+ DEVMETHOD(device_shutdown, octe_shutdown),
+
+ /* MII interface */
+ DEVMETHOD(miibus_readreg, octe_miibus_readreg),
+ DEVMETHOD(miibus_writereg, octe_miibus_writereg),
+
+ { 0, 0 }
+};
+
+static driver_t octe_driver = {
+ "octe",
+ octe_methods,
+ sizeof (cvm_oct_private_t),
+};
+
+static devclass_t octe_devclass;
+
+DRIVER_MODULE(octe, octebus, octe_driver, octe_devclass, 0, 0);
+DRIVER_MODULE(miibus, octe, miibus_driver, miibus_devclass, 0, 0);
+
+static int
+octe_probe(device_t dev)
+{
+ return (0);
+}
+
+static int
+octe_attach(device_t dev)
+{
+ struct ifnet *ifp;
+ cvm_oct_private_t *priv;
+ device_t child;
+ unsigned qos;
+ int error;
+
+ priv = device_get_softc(dev);
+ ifp = priv->ifp;
+
+ if_initname(ifp, device_get_name(dev), device_get_unit(dev));
+
+ if (priv->phy_id != -1) {
+ if (priv->phy_device == NULL) {
+ error = mii_attach(dev, &priv->miibus, ifp,
+ octe_mii_medchange, octe_mii_medstat,
+ BMSR_DEFCAPMASK, priv->phy_id, MII_OFFSET_ANY, 0);
+ if (error != 0)
+ device_printf(dev, "attaching PHYs failed\n");
+ } else {
+ child = device_add_child(dev, priv->phy_device, -1);
+ if (child == NULL)
+ device_printf(dev, "missing phy %u device %s\n", priv->phy_id, priv->phy_device);
+ }
+ }
+
+ if (priv->miibus == NULL) {
+ ifmedia_init(&priv->media, 0, octe_medchange, octe_medstat);
+
+ ifmedia_add(&priv->media, IFM_ETHER | IFM_AUTO, 0, NULL);
+ ifmedia_set(&priv->media, IFM_ETHER | IFM_AUTO);
+ }
+
+ /*
+ * XXX
+ * We don't support programming the multicast filter right now, although it
+ * ought to be easy enough. (Presumably it's just a matter of putting
+ * multicast addresses in the CAM?)
+ */
+ ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST | IFF_ALLMULTI;
+ ifp->if_init = octe_init;
+ ifp->if_ioctl = octe_ioctl;
+
+ priv->if_flags = ifp->if_flags;
+
+ mtx_init(&priv->tx_mtx, ifp->if_xname, "octe tx send queue", MTX_DEF);
+
+ for (qos = 0; qos < 16; qos++) {
+ mtx_init(&priv->tx_free_queue[qos].ifq_mtx, ifp->if_xname, "octe tx free queue", MTX_DEF);
+ IFQ_SET_MAXLEN(&priv->tx_free_queue[qos], MAX_OUT_QUEUE_DEPTH);
+ }
+
+ ether_ifattach(ifp, priv->mac);
+
+ ifp->if_transmit = octe_transmit;
+
+ ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header);
+ ifp->if_capabilities = IFCAP_VLAN_MTU | IFCAP_HWCSUM;
+ ifp->if_capenable = ifp->if_capabilities;
+ ifp->if_hwassist = CSUM_TCP | CSUM_UDP;
+
+ OCTE_TX_LOCK(priv);
+ IFQ_SET_MAXLEN(&ifp->if_snd, MAX_OUT_QUEUE_DEPTH);
+ ifp->if_snd.ifq_drv_maxlen = MAX_OUT_QUEUE_DEPTH;
+ IFQ_SET_READY(&ifp->if_snd);
+ OCTE_TX_UNLOCK(priv);
+
+ return (bus_generic_attach(dev));
+}
+
+static int
+octe_detach(device_t dev)
+{
+ return (0);
+}
+
+static int
+octe_shutdown(device_t dev)
+{
+ return (octe_detach(dev));
+}
+
+static int
+octe_miibus_readreg(device_t dev, int phy, int reg)
+{
+ cvm_oct_private_t *priv;
+
+ priv = device_get_softc(dev);
+
+ /*
+ * Try interface-specific MII routine.
+ */
+ if (priv->mdio_read != NULL)
+ return (priv->mdio_read(priv->ifp, phy, reg));
+
+ /*
+ * Try generic MII routine.
+ */
+ KASSERT(phy == priv->phy_id,
+ ("read from phy %u but our phy is %u", phy, priv->phy_id));
+ return (cvm_oct_mdio_read(priv->ifp, phy, reg));
+}
+
+static int
+octe_miibus_writereg(device_t dev, int phy, int reg, int val)
+{
+ cvm_oct_private_t *priv;
+
+ priv = device_get_softc(dev);
+
+ /*
+ * Try interface-specific MII routine.
+ */
+ if (priv->mdio_write != NULL) {
+ priv->mdio_write(priv->ifp, phy, reg, val);
+ return (0);
+ }
+
+ /*
+ * Try generic MII routine.
+ */
+ KASSERT(phy == priv->phy_id,
+ ("write to phy %u but our phy is %u", phy, priv->phy_id));
+ cvm_oct_mdio_write(priv->ifp, phy, reg, val);
+
+ return (0);
+}
+
+static void
+octe_init(void *arg)
+{
+ struct ifnet *ifp;
+ cvm_oct_private_t *priv;
+
+ priv = arg;
+ ifp = priv->ifp;
+
+ if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0)
+ octe_stop(priv);
+
+ if (priv->open != NULL)
+ priv->open(ifp);
+
+ if (((ifp->if_flags ^ priv->if_flags) & (IFF_ALLMULTI | IFF_MULTICAST | IFF_PROMISC)) != 0)
+ cvm_oct_common_set_multicast_list(ifp);
+
+ cvm_oct_common_set_mac_address(ifp, IF_LLADDR(ifp));
+
+ cvm_oct_common_poll(ifp);
+
+ if (priv->miibus != NULL)
+ mii_mediachg(device_get_softc(priv->miibus));
+
+ ifp->if_drv_flags |= IFF_DRV_RUNNING;
+ ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
+}
+
+static void
+octe_stop(void *arg)
+{
+ struct ifnet *ifp;
+ cvm_oct_private_t *priv;
+
+ priv = arg;
+ ifp = priv->ifp;
+
+ if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0)
+ return;
+
+ if (priv->stop != NULL)
+ priv->stop(ifp);
+
+ ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
+}
+
+static int
+octe_transmit(struct ifnet *ifp, struct mbuf *m)
+{
+ cvm_oct_private_t *priv;
+
+ priv = ifp->if_softc;
+
+ if ((ifp->if_drv_flags & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) !=
+ IFF_DRV_RUNNING) {
+ m_freem(m);
+ return (0);
+ }
+
+ return (cvm_oct_xmit(m, ifp));
+}
+
+static int
+octe_mii_medchange(struct ifnet *ifp)
+{
+ cvm_oct_private_t *priv;
+ struct mii_data *mii;
+ struct mii_softc *miisc;
+
+ priv = ifp->if_softc;
+ mii = device_get_softc(priv->miibus);
+ LIST_FOREACH(miisc, &mii->mii_phys, mii_list)
+ PHY_RESET(miisc);
+ mii_mediachg(mii);
+
+ return (0);
+}
+
+static void
+octe_mii_medstat(struct ifnet *ifp, struct ifmediareq *ifm)
+{
+ cvm_oct_private_t *priv;
+ struct mii_data *mii;
+
+ priv = ifp->if_softc;
+ mii = device_get_softc(priv->miibus);
+
+ mii_pollstat(mii);
+ ifm->ifm_active = mii->mii_media_active;
+ ifm->ifm_status = mii->mii_media_status;
+}
+
+static int
+octe_medchange(struct ifnet *ifp)
+{
+ return (ENOTSUP);
+}
+
+static void
+octe_medstat(struct ifnet *ifp, struct ifmediareq *ifm)
+{
+ cvm_oct_private_t *priv;
+ cvmx_helper_link_info_t link_info;
+
+ priv = ifp->if_softc;
+
+ ifm->ifm_status = IFM_AVALID;
+ ifm->ifm_active = IFT_ETHER;
+
+ if (priv->poll == NULL)
+ return;
+ priv->poll(ifp);
+
+ link_info.u64 = priv->link_info;
+
+ if (!link_info.s.link_up)
+ return;
+
+ ifm->ifm_status |= IFM_ACTIVE;
+
+ switch (link_info.s.speed) {
+ case 10:
+ ifm->ifm_active |= IFM_10_T;
+ break;
+ case 100:
+ ifm->ifm_active |= IFM_100_TX;
+ break;
+ case 1000:
+ ifm->ifm_active |= IFM_1000_T;
+ break;
+ case 10000:
+ ifm->ifm_active |= IFM_10G_T;
+ break;
+ }
+
+ if (link_info.s.full_duplex)
+ ifm->ifm_active |= IFM_FDX;
+ else
+ ifm->ifm_active |= IFM_HDX;
+}
+
+static int
+octe_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data)
+{
+ cvm_oct_private_t *priv;
+ struct mii_data *mii;
+ struct ifreq *ifr;
+#ifdef INET
+ struct ifaddr *ifa;
+#endif
+ int error;
+
+ priv = ifp->if_softc;
+ ifr = (struct ifreq *)data;
+#ifdef INET
+ ifa = (struct ifaddr *)data;
+#endif
+
+ switch (cmd) {
+ case SIOCSIFADDR:
+#ifdef INET
+ /*
+ * Avoid reinitialization unless it's necessary.
+ */
+ if (ifa->ifa_addr->sa_family == AF_INET) {
+ ifp->if_flags |= IFF_UP;
+ if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0)
+ octe_init(priv);
+ arp_ifinit(ifp, ifa);
+
+ return (0);
+ }
+#endif
+ error = ether_ioctl(ifp, cmd, data);
+ if (error != 0)
+ return (error);
+ return (0);
+
+ case SIOCSIFFLAGS:
+ if (ifp->if_flags == priv->if_flags)
+ return (0);
+ if ((ifp->if_flags & IFF_UP) != 0) {
+ if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0)
+ octe_init(priv);
+ } else {
+ if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0)
+ octe_stop(priv);
+ }
+ priv->if_flags = ifp->if_flags;
+ return (0);
+
+ case SIOCSIFCAP:
+ /*
+ * Just change the capabilities in software, currently none
+ * require reprogramming hardware, they just toggle whether we
+ * make use of already-present facilities in software.
+ */
+ ifp->if_capenable = ifr->ifr_reqcap;
+ return (0);
+
+ case SIOCSIFMTU:
+ error = cvm_oct_common_change_mtu(ifp, ifr->ifr_mtu);
+ if (error != 0)
+ return (EINVAL);
+ return (0);
+
+ case SIOCSIFMEDIA:
+ case SIOCGIFMEDIA:
+ if (priv->miibus != NULL) {
+ mii = device_get_softc(priv->miibus);
+ error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, cmd);
+ if (error != 0)
+ return (error);
+ return (0);
+ }
+ error = ifmedia_ioctl(ifp, ifr, &priv->media, cmd);
+ if (error != 0)
+ return (error);
+ return (0);
+
+ default:
+ error = ether_ioctl(ifp, cmd, data);
+ if (error != 0)
+ return (error);
+ return (0);
+ }
+}
Property changes on: trunk/sys/mips/cavium/octe/octe.c
___________________________________________________________________
Added: svn:eol-style
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+native
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+MidnightBSD=%H
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## -0,0 +1 ##
+text/plain
\ No newline at end of property
Added: trunk/sys/mips/cavium/octe/octebus.c
===================================================================
--- trunk/sys/mips/cavium/octe/octebus.c (rev 0)
+++ trunk/sys/mips/cavium/octe/octebus.c 2018-05-26 21:55:02 UTC (rev 9987)
@@ -0,0 +1,124 @@
+/* $MidnightBSD$ */
+/*-
+ * Copyright (c) 2010 Juli Mallett <jmallett at FreeBSD.org>
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ * $FreeBSD: stable/10/sys/mips/cavium/octe/octebus.c 219695 2011-03-16 08:56:22Z jmallett $
+ */
+
+/*
+ * Cavium Octeon Ethernet pseudo-bus attachment.
+ */
+
+#include <sys/param.h>
+#include <sys/systm.h>
+#include <sys/bus.h>
+#include <sys/endian.h>
+#include <sys/kernel.h>
+#include <sys/mbuf.h>
+#include <sys/lock.h>
+#include <sys/module.h>
+#include <sys/mutex.h>
+#include <sys/rman.h>
+#include <sys/socket.h>
+#include <sys/sockio.h>
+#include <sys/sysctl.h>
+
+#include "ethernet-common.h"
+
+#include "octebusvar.h"
+
+static void octebus_identify(driver_t *drv, device_t parent);
+static int octebus_probe(device_t dev);
+static int octebus_attach(device_t dev);
+static int octebus_detach(device_t dev);
+static int octebus_shutdown(device_t dev);
+
+static device_method_t octebus_methods[] = {
+ /* Device interface */
+ DEVMETHOD(device_identify, octebus_identify),
+ DEVMETHOD(device_probe, octebus_probe),
+ DEVMETHOD(device_attach, octebus_attach),
+ DEVMETHOD(device_detach, octebus_detach),
+ DEVMETHOD(device_shutdown, octebus_shutdown),
+
+ /* Bus interface. */
+ DEVMETHOD(bus_add_child, bus_generic_add_child),
+
+ { 0, 0 }
+};
+
+static driver_t octebus_driver = {
+ "octebus",
+ octebus_methods,
+ sizeof (struct octebus_softc),
+};
+
+static devclass_t octebus_devclass;
+
+DRIVER_MODULE(octebus, ciu, octebus_driver, octebus_devclass, 0, 0);
+
+static void
+octebus_identify(driver_t *drv, device_t parent)
+{
+ BUS_ADD_CHILD(parent, 0, "octebus", 0);
+}
+
+static int
+octebus_probe(device_t dev)
+{
+ if (device_get_unit(dev) != 0)
+ return (ENXIO);
+ device_set_desc(dev, "Cavium Octeon Ethernet pseudo-bus");
+ return (0);
+}
+
+static int
+octebus_attach(device_t dev)
+{
+ struct octebus_softc *sc;
+ int rv;
+
+ sc = device_get_softc(dev);
+ sc->sc_dev = dev;
+
+ rv = cvm_oct_init_module(dev);
+ if (rv != 0)
+ return (ENXIO);
+
+ return (0);
+}
+
+static int
+octebus_detach(device_t dev)
+{
+ cvm_oct_cleanup_module(dev);
+ return (0);
+}
+
+static int
+octebus_shutdown(device_t dev)
+{
+ return (octebus_detach(dev));
+}
Property changes on: trunk/sys/mips/cavium/octe/octebus.c
___________________________________________________________________
Added: svn:eol-style
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+native
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+MidnightBSD=%H
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+text/plain
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Added: trunk/sys/mips/cavium/octe/octebusvar.h
===================================================================
--- trunk/sys/mips/cavium/octe/octebusvar.h (rev 0)
+++ trunk/sys/mips/cavium/octe/octebusvar.h 2018-05-26 21:55:02 UTC (rev 9987)
@@ -0,0 +1,43 @@
+/* $MidnightBSD$ */
+/*-
+ * Copyright (c) 2010 Juli Mallett <jmallett at FreeBSD.org>
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ * $FreeBSD: stable/10/sys/mips/cavium/octe/octebusvar.h 219695 2011-03-16 08:56:22Z jmallett $
+ */
+
+#ifndef _CAVIUM_OCTE_OCTEBUSVAR_H_
+#define _CAVIUM_OCTE_OCTEBUSVAR_H_
+
+struct octebus_softc {
+ device_t sc_dev;
+
+ struct resource *sc_rx_irq;
+ void *sc_rx_intr_cookie;
+
+ struct resource *sc_rgmii_irq;
+ struct resource *sc_spi_irq;
+};
+
+#endif /* !_CAVIUM_OCTE_OCTEBUSVAR_H_ */
Property changes on: trunk/sys/mips/cavium/octe/octebusvar.h
___________________________________________________________________
Added: svn:eol-style
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+MidnightBSD=%H
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+text/plain
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Added: trunk/sys/mips/cavium/octe/wrapper-cvmx-includes.h
===================================================================
--- trunk/sys/mips/cavium/octe/wrapper-cvmx-includes.h (rev 0)
+++ trunk/sys/mips/cavium/octe/wrapper-cvmx-includes.h 2018-05-26 21:55:02 UTC (rev 9987)
@@ -0,0 +1,52 @@
+/* $MidnightBSD$ */
+/*************************************************************************
+Copyright (c) 2003-2007 Cavium Networks (support at cavium.com). All rights
+reserved.
+
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are
+met:
+
+ * Redistributions of source code must retain the above copyright
+ notice, this list of conditions and the following disclaimer.
+
+ * Redistributions in binary form must reproduce the above
+ copyright notice, this list of conditions and the following
+ disclaimer in the documentation and/or other materials provided
+ with the distribution.
+
+ * Neither the name of Cavium Networks nor the names of
+ its contributors may be used to endorse or promote products
+ derived from this software without specific prior written
+ permission.
+
+This Software, including technical data, may be subject to U.S. export control laws, including the U.S. Export Administration Act and its associated regulations, and may be subject to export or import regulations in other countries.
+
+TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
+AND WITH ALL FAULTS AND CAVIUM NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES OF TITLE, MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR PURPOSE, LACK OF VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET POSSESSION OR CORRESPONDENCE TO DESCRIPTION. THE ENTIRE RISK ARISING OUT OF USE OR PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
+
+*************************************************************************/
+/* $FreeBSD: stable/10/sys/mips/cavium/octe/wrapper-cvmx-includes.h 250192 2013-05-02 19:47:36Z imp $ */
+
+#ifndef __WRAPPER_CVMX_INCLUDES_H__
+#define __WRAPPER_CVMX_INCLUDES_H__
+
+#include <contrib/octeon-sdk/cvmx.h>
+#include <contrib/octeon-sdk/cvmx-version.h>
+#include <contrib/octeon-sdk/cvmx-atomic.h>
+#include <contrib/octeon-sdk/cvmx-pip.h>
+#include <contrib/octeon-sdk/cvmx-ipd.h>
+#include <contrib/octeon-sdk/cvmx-pko.h>
+#include <contrib/octeon-sdk/cvmx-pow.h>
+#include <contrib/octeon-sdk/cvmx-gmx.h>
+#include <contrib/octeon-sdk/cvmx-spi.h>
+#include <contrib/octeon-sdk/cvmx-bootmem.h>
+#include <contrib/octeon-sdk/cvmx-app-init.h>
+#include <contrib/octeon-sdk/cvmx-helper.h>
+#include <contrib/octeon-sdk/cvmx-helper-board.h>
+#include <contrib/octeon-sdk/cvmx-mgmt-port.h>
+#include <mips/cavium/octeon_irq.h>
+#include <contrib/octeon-sdk/octeon-model.h>
+
+#endif
Property changes on: trunk/sys/mips/cavium/octe/wrapper-cvmx-includes.h
___________________________________________________________________
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Added: trunk/sys/mips/cavium/octeon_cop2.S
===================================================================
--- trunk/sys/mips/cavium/octeon_cop2.S (rev 0)
+++ trunk/sys/mips/cavium/octeon_cop2.S 2018-05-26 21:55:02 UTC (rev 9987)
@@ -0,0 +1,226 @@
+/* $MidnightBSD$ */
+/*-
+ * Copyright (c) 2011 Oleksandr Tymoshenko
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ * $FreeBSD: stable/10/sys/mips/cavium/octeon_cop2.S 229677 2012-01-06 01:23:26Z gonzo $
+ */
+
+#include <machine/asm.h>
+#include <mips/cavium/octeon_cop2.h>
+
+#include "assym.s"
+
+.set noreorder
+
+#define SAVE_COP2_REGISTER(reg) \
+ dmfc2 t1, reg; sd t1, reg##_OFFSET(a0)
+
+
+#define RESTORE_COP2_REGISTER(reg) \
+ ld t1, reg##_OFFSET(a0); dmtc2 t1, reg##_SET
+
+LEAF(octeon_cop2_save)
+ /* Get CvmCtl register */
+ dmfc0 t0, $9, 7
+
+ /* CRC state */
+ SAVE_COP2_REGISTER(COP2_CRC_IV)
+ SAVE_COP2_REGISTER(COP2_CRC_LENGTH)
+ SAVE_COP2_REGISTER(COP2_CRC_POLY)
+
+ /* if CvmCtl[NODFA_CP2] -> save_nodfa */
+ bbit1 t0, 28, save_nodfa
+ nop
+
+ /* LLM state */
+ SAVE_COP2_REGISTER(COP2_LLM_DAT0)
+ SAVE_COP2_REGISTER(COP2_LLM_DAT1)
+
+save_nodfa:
+ /* crypto stuff is irrelevant if CvmCtl[NOCRYPTO] */
+ bbit1 t0, 26, save_done
+ nop
+
+ SAVE_COP2_REGISTER(COP2_3DES_IV)
+ SAVE_COP2_REGISTER(COP2_3DES_KEY0)
+ SAVE_COP2_REGISTER(COP2_3DES_KEY1)
+ SAVE_COP2_REGISTER(COP2_3DES_KEY2)
+ SAVE_COP2_REGISTER(COP2_3DES_RESULT)
+
+ SAVE_COP2_REGISTER(COP2_AES_INP0)
+ SAVE_COP2_REGISTER(COP2_AES_IV0)
+ SAVE_COP2_REGISTER(COP2_AES_IV1)
+ SAVE_COP2_REGISTER(COP2_AES_KEY0)
+ SAVE_COP2_REGISTER(COP2_AES_KEY1)
+ SAVE_COP2_REGISTER(COP2_AES_KEY2)
+ SAVE_COP2_REGISTER(COP2_AES_KEY3)
+ SAVE_COP2_REGISTER(COP2_AES_KEYLEN)
+ SAVE_COP2_REGISTER(COP2_AES_RESULT0)
+ SAVE_COP2_REGISTER(COP2_AES_RESULT1)
+
+ dmfc0 t0, $15
+ li t1, 0x000d0000 /* Octeon Pass1 */
+ beq t0, t1, save_pass1
+ nop
+
+ SAVE_COP2_REGISTER(COP2_HSH_DATW0)
+ SAVE_COP2_REGISTER(COP2_HSH_DATW1)
+ SAVE_COP2_REGISTER(COP2_HSH_DATW2)
+ SAVE_COP2_REGISTER(COP2_HSH_DATW3)
+ SAVE_COP2_REGISTER(COP2_HSH_DATW4)
+ SAVE_COP2_REGISTER(COP2_HSH_DATW5)
+ SAVE_COP2_REGISTER(COP2_HSH_DATW6)
+ SAVE_COP2_REGISTER(COP2_HSH_DATW7)
+ SAVE_COP2_REGISTER(COP2_HSH_DATW8)
+ SAVE_COP2_REGISTER(COP2_HSH_DATW9)
+ SAVE_COP2_REGISTER(COP2_HSH_DATW10)
+ SAVE_COP2_REGISTER(COP2_HSH_DATW11)
+ SAVE_COP2_REGISTER(COP2_HSH_DATW12)
+ SAVE_COP2_REGISTER(COP2_HSH_DATW13)
+ SAVE_COP2_REGISTER(COP2_HSH_DATW14)
+ SAVE_COP2_REGISTER(COP2_HSH_IVW0)
+ SAVE_COP2_REGISTER(COP2_HSH_IVW1)
+ SAVE_COP2_REGISTER(COP2_HSH_IVW2)
+ SAVE_COP2_REGISTER(COP2_HSH_IVW3)
+ SAVE_COP2_REGISTER(COP2_HSH_IVW4)
+ SAVE_COP2_REGISTER(COP2_HSH_IVW5)
+ SAVE_COP2_REGISTER(COP2_HSH_IVW6)
+ SAVE_COP2_REGISTER(COP2_HSH_IVW7)
+ SAVE_COP2_REGISTER(COP2_GFM_MULT0)
+ SAVE_COP2_REGISTER(COP2_GFM_MULT1)
+ SAVE_COP2_REGISTER(COP2_GFM_POLY)
+ SAVE_COP2_REGISTER(COP2_GFM_RESULT0)
+ SAVE_COP2_REGISTER(COP2_GFM_RESULT1)
+ jr ra
+ nop
+
+save_pass1:
+ SAVE_COP2_REGISTER(COP2_HSH_DATW0_PASS1)
+ SAVE_COP2_REGISTER(COP2_HSH_DATW1_PASS1)
+ SAVE_COP2_REGISTER(COP2_HSH_DATW2_PASS1)
+ SAVE_COP2_REGISTER(COP2_HSH_DATW3_PASS1)
+ SAVE_COP2_REGISTER(COP2_HSH_DATW4_PASS1)
+ SAVE_COP2_REGISTER(COP2_HSH_DATW5_PASS1)
+ SAVE_COP2_REGISTER(COP2_HSH_DATW6_PASS1)
+ SAVE_COP2_REGISTER(COP2_HSH_IVW0_PASS1)
+ SAVE_COP2_REGISTER(COP2_HSH_IVW1_PASS1)
+ SAVE_COP2_REGISTER(COP2_HSH_IVW2_PASS1)
+
+save_done:
+ jr ra
+ nop
+END(octeon_cop2_save)
+
+LEAF(octeon_cop2_restore)
+ /* Get CvmCtl register */
+ dmfc0 t0, $9, 7
+
+ /* CRC state */
+ RESTORE_COP2_REGISTER(COP2_CRC_IV)
+ RESTORE_COP2_REGISTER(COP2_CRC_LENGTH)
+ RESTORE_COP2_REGISTER(COP2_CRC_POLY)
+
+ /* if CvmCtl[NODFA_CP2] -> save_nodfa */
+ bbit1 t0, 28, restore_nodfa
+ nop
+
+ /* LLM state */
+ RESTORE_COP2_REGISTER(COP2_LLM_DAT0)
+ RESTORE_COP2_REGISTER(COP2_LLM_DAT1)
+
+restore_nodfa:
+ /* crypto stuff is irrelevant if CvmCtl[NOCRYPTO] */
+ bbit1 t0, 26, restore_done
+ nop
+
+ RESTORE_COP2_REGISTER(COP2_3DES_IV)
+ RESTORE_COP2_REGISTER(COP2_3DES_KEY0)
+ RESTORE_COP2_REGISTER(COP2_3DES_KEY1)
+ RESTORE_COP2_REGISTER(COP2_3DES_KEY2)
+ RESTORE_COP2_REGISTER(COP2_3DES_RESULT)
+
+ RESTORE_COP2_REGISTER(COP2_AES_INP0)
+ RESTORE_COP2_REGISTER(COP2_AES_IV0)
+ RESTORE_COP2_REGISTER(COP2_AES_IV1)
+ RESTORE_COP2_REGISTER(COP2_AES_KEY0)
+ RESTORE_COP2_REGISTER(COP2_AES_KEY1)
+ RESTORE_COP2_REGISTER(COP2_AES_KEY2)
+ RESTORE_COP2_REGISTER(COP2_AES_KEY3)
+ RESTORE_COP2_REGISTER(COP2_AES_KEYLEN)
+ RESTORE_COP2_REGISTER(COP2_AES_RESULT0)
+ RESTORE_COP2_REGISTER(COP2_AES_RESULT1)
+
+ dmfc0 t0, $15
+ li t1, 0x000d0000 /* Octeon Pass1 */
+ beq t0, t1, restore_pass1
+ nop
+
+ RESTORE_COP2_REGISTER(COP2_HSH_DATW0)
+ RESTORE_COP2_REGISTER(COP2_HSH_DATW1)
+ RESTORE_COP2_REGISTER(COP2_HSH_DATW2)
+ RESTORE_COP2_REGISTER(COP2_HSH_DATW3)
+ RESTORE_COP2_REGISTER(COP2_HSH_DATW4)
+ RESTORE_COP2_REGISTER(COP2_HSH_DATW5)
+ RESTORE_COP2_REGISTER(COP2_HSH_DATW6)
+ RESTORE_COP2_REGISTER(COP2_HSH_DATW7)
+ RESTORE_COP2_REGISTER(COP2_HSH_DATW8)
+ RESTORE_COP2_REGISTER(COP2_HSH_DATW9)
+ RESTORE_COP2_REGISTER(COP2_HSH_DATW10)
+ RESTORE_COP2_REGISTER(COP2_HSH_DATW11)
+ RESTORE_COP2_REGISTER(COP2_HSH_DATW12)
+ RESTORE_COP2_REGISTER(COP2_HSH_DATW13)
+ RESTORE_COP2_REGISTER(COP2_HSH_DATW14)
+ RESTORE_COP2_REGISTER(COP2_HSH_IVW0)
+ RESTORE_COP2_REGISTER(COP2_HSH_IVW1)
+ RESTORE_COP2_REGISTER(COP2_HSH_IVW2)
+ RESTORE_COP2_REGISTER(COP2_HSH_IVW3)
+ RESTORE_COP2_REGISTER(COP2_HSH_IVW4)
+ RESTORE_COP2_REGISTER(COP2_HSH_IVW5)
+ RESTORE_COP2_REGISTER(COP2_HSH_IVW6)
+ RESTORE_COP2_REGISTER(COP2_HSH_IVW7)
+ RESTORE_COP2_REGISTER(COP2_GFM_MULT0)
+ RESTORE_COP2_REGISTER(COP2_GFM_MULT1)
+ RESTORE_COP2_REGISTER(COP2_GFM_POLY)
+ RESTORE_COP2_REGISTER(COP2_GFM_RESULT0)
+ RESTORE_COP2_REGISTER(COP2_GFM_RESULT1)
+ jr ra
+ nop
+
+restore_pass1:
+ RESTORE_COP2_REGISTER(COP2_HSH_DATW0_PASS1)
+ RESTORE_COP2_REGISTER(COP2_HSH_DATW1_PASS1)
+ RESTORE_COP2_REGISTER(COP2_HSH_DATW2_PASS1)
+ RESTORE_COP2_REGISTER(COP2_HSH_DATW3_PASS1)
+ RESTORE_COP2_REGISTER(COP2_HSH_DATW4_PASS1)
+ RESTORE_COP2_REGISTER(COP2_HSH_DATW5_PASS1)
+ RESTORE_COP2_REGISTER(COP2_HSH_DATW6_PASS1)
+ RESTORE_COP2_REGISTER(COP2_HSH_IVW0_PASS1)
+ RESTORE_COP2_REGISTER(COP2_HSH_IVW1_PASS1)
+ RESTORE_COP2_REGISTER(COP2_HSH_IVW2_PASS1)
+
+restore_done:
+ jr ra
+ nop
+END(octeon_cop2_restore)
Property changes on: trunk/sys/mips/cavium/octeon_cop2.S
___________________________________________________________________
Added: svn:eol-style
## -0,0 +1 ##
+native
\ No newline at end of property
Added: svn:keywords
## -0,0 +1 ##
+MidnightBSD=%H
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+text/plain
\ No newline at end of property
Added: trunk/sys/mips/cavium/octeon_cop2.h
===================================================================
--- trunk/sys/mips/cavium/octeon_cop2.h (rev 0)
+++ trunk/sys/mips/cavium/octeon_cop2.h 2018-05-26 21:55:02 UTC (rev 9987)
@@ -0,0 +1,211 @@
+/* $MidnightBSD$ */
+/*-
+ * Copyright (c) 2011, Oleksandr Tymoshenko <gonzo at FreeBSD.org>
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice unmodified, this list of conditions, and the following
+ * disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ * $FreeBSD: stable/10/sys/mips/cavium/octeon_cop2.h 229677 2012-01-06 01:23:26Z gonzo $
+ *
+ */
+
+#ifndef __OCTEON_COP2_H__
+#define __OCTEON_COP2_H__
+
+/*
+ * COP2 registers of interest
+ */
+#define COP2_CRC_IV 0x201
+#define COP2_CRC_IV_SET COP2_CRC_IV
+#define COP2_CRC_LENGTH 0x202
+#define COP2_CRC_LENGTH_SET 0x1202
+#define COP2_CRC_POLY 0x200
+#define COP2_CRC_POLY_SET 0x4200
+#define COP2_LLM_DAT0 0x402
+#define COP2_LLM_DAT0_SET COP2_LLM_DAT0
+#define COP2_LLM_DAT1 0x40A
+#define COP2_LLM_DAT1_SET COP2_LLM_DAT1
+#define COP2_3DES_IV 0x084
+#define COP2_3DES_IV_SET COP2_3DES_IV
+#define COP2_3DES_KEY0 0x080
+#define COP2_3DES_KEY0_SET COP2_3DES_KEY0
+#define COP2_3DES_KEY1 0x081
+#define COP2_3DES_KEY1_SET COP2_3DES_KEY1
+#define COP2_3DES_KEY2 0x082
+#define COP2_3DES_KEY2_SET COP2_3DES_KEY2
+#define COP2_3DES_RESULT 0x088
+#define COP2_3DES_RESULT_SET 0x098
+#define COP2_AES_INP0 0x111
+#define COP2_AES_INP0_SET COP2_AES_INP0
+#define COP2_AES_IV0 0x102
+#define COP2_AES_IV0_SET COP2_AES_IV0
+#define COP2_AES_IV1 0x103
+#define COP2_AES_IV1_SET COP2_AES_IV1
+#define COP2_AES_KEY0 0x104
+#define COP2_AES_KEY0_SET COP2_AES_KEY0
+#define COP2_AES_KEY1 0x105
+#define COP2_AES_KEY1_SET COP2_AES_KEY1
+#define COP2_AES_KEY2 0x106
+#define COP2_AES_KEY2_SET COP2_AES_KEY2
+#define COP2_AES_KEY3 0x107
+#define COP2_AES_KEY3_SET COP2_AES_KEY3
+#define COP2_AES_KEYLEN 0x110
+#define COP2_AES_KEYLEN_SET COP2_AES_KEYLEN
+#define COP2_AES_RESULT0 0x100
+#define COP2_AES_RESULT0_SET COP2_AES_RESULT0
+#define COP2_AES_RESULT1 0x101
+#define COP2_AES_RESULT1_SET COP2_AES_RESULT1
+#define COP2_HSH_DATW0 0x240
+#define COP2_HSH_DATW0_SET COP2_HSH_DATW0
+#define COP2_HSH_DATW1 0x241
+#define COP2_HSH_DATW1_SET COP2_HSH_DATW1
+#define COP2_HSH_DATW2 0x242
+#define COP2_HSH_DATW2_SET COP2_HSH_DATW2
+#define COP2_HSH_DATW3 0x243
+#define COP2_HSH_DATW3_SET COP2_HSH_DATW3
+#define COP2_HSH_DATW4 0x244
+#define COP2_HSH_DATW4_SET COP2_HSH_DATW4
+#define COP2_HSH_DATW5 0x245
+#define COP2_HSH_DATW5_SET COP2_HSH_DATW5
+#define COP2_HSH_DATW6 0x246
+#define COP2_HSH_DATW6_SET COP2_HSH_DATW6
+#define COP2_HSH_DATW7 0x247
+#define COP2_HSH_DATW7_SET COP2_HSH_DATW7
+#define COP2_HSH_DATW8 0x248
+#define COP2_HSH_DATW8_SET COP2_HSH_DATW8
+#define COP2_HSH_DATW9 0x249
+#define COP2_HSH_DATW9_SET COP2_HSH_DATW9
+#define COP2_HSH_DATW10 0x24A
+#define COP2_HSH_DATW10_SET COP2_HSH_DATW10
+#define COP2_HSH_DATW11 0x24B
+#define COP2_HSH_DATW11_SET COP2_HSH_DATW11
+#define COP2_HSH_DATW12 0x24C
+#define COP2_HSH_DATW12_SET COP2_HSH_DATW12
+#define COP2_HSH_DATW13 0x24D
+#define COP2_HSH_DATW13_SET COP2_HSH_DATW13
+#define COP2_HSH_DATW14 0x24E
+#define COP2_HSH_DATW14_SET COP2_HSH_DATW14
+#define COP2_HSH_IVW0 0x250
+#define COP2_HSH_IVW0_SET COP2_HSH_IVW0
+#define COP2_HSH_IVW1 0x251
+#define COP2_HSH_IVW1_SET COP2_HSH_IVW1
+#define COP2_HSH_IVW2 0x252
+#define COP2_HSH_IVW2_SET COP2_HSH_IVW2
+#define COP2_HSH_IVW3 0x253
+#define COP2_HSH_IVW3_SET COP2_HSH_IVW3
+#define COP2_HSH_IVW4 0x254
+#define COP2_HSH_IVW4_SET COP2_HSH_IVW4
+#define COP2_HSH_IVW5 0x255
+#define COP2_HSH_IVW5_SET COP2_HSH_IVW5
+#define COP2_HSH_IVW6 0x256
+#define COP2_HSH_IVW6_SET COP2_HSH_IVW6
+#define COP2_HSH_IVW7 0x257
+#define COP2_HSH_IVW7_SET COP2_HSH_IVW7
+#define COP2_GFM_MULT0 0x258
+#define COP2_GFM_MULT0_SET COP2_GFM_MULT0
+#define COP2_GFM_MULT1 0x259
+#define COP2_GFM_MULT1_SET COP2_GFM_MULT1
+#define COP2_GFM_POLY 0x25E
+#define COP2_GFM_POLY_SET COP2_GFM_POLY
+#define COP2_GFM_RESULT0 0x25A
+#define COP2_GFM_RESULT0_SET COP2_GFM_RESULT0
+#define COP2_GFM_RESULT1 0x25B
+#define COP2_GFM_RESULT1_SET COP2_GFM_RESULT1
+#define COP2_HSH_DATW0_PASS1 0x040
+#define COP2_HSH_DATW0_PASS1_SET COP2_HSH_DATW0_PASS1
+#define COP2_HSH_DATW1_PASS1 0x041
+#define COP2_HSH_DATW1_PASS1_SET COP2_HSH_DATW1_PASS1
+#define COP2_HSH_DATW2_PASS1 0x042
+#define COP2_HSH_DATW2_PASS1_SET COP2_HSH_DATW2_PASS1
+#define COP2_HSH_DATW3_PASS1 0x043
+#define COP2_HSH_DATW3_PASS1_SET COP2_HSH_DATW3_PASS1
+#define COP2_HSH_DATW4_PASS1 0x044
+#define COP2_HSH_DATW4_PASS1_SET COP2_HSH_DATW4_PASS1
+#define COP2_HSH_DATW5_PASS1 0x045
+#define COP2_HSH_DATW5_PASS1_SET COP2_HSH_DATW5_PASS1
+#define COP2_HSH_DATW6_PASS1 0x046
+#define COP2_HSH_DATW6_PASS1_SET COP2_HSH_DATW6_PASS1
+#define COP2_HSH_IVW0_PASS1 0x048
+#define COP2_HSH_IVW0_PASS1_SET COP2_HSH_IVW0_PASS1
+#define COP2_HSH_IVW1_PASS1 0x049
+#define COP2_HSH_IVW1_PASS1_SET COP2_HSH_IVW1_PASS1
+#define COP2_HSH_IVW2_PASS1 0x04A
+#define COP2_HSH_IVW2_PASS1_SET COP2_HSH_IVW2_PASS1
+
+#ifndef LOCORE
+
+struct octeon_cop2_state {
+ /* 3DES */
+ /* 0x0084 */
+ unsigned long _3des_iv;
+ /* 0x0080..0x0082 */
+ unsigned long _3des_key[3];
+ /* 0x0088, set: 0x0098 */
+ unsigned long _3des_result;
+
+ /* AES */
+ /* 0x0111 */
+ unsigned long aes_inp0;
+ /* 0x0102..0x0103 */
+ unsigned long aes_iv[2];
+ /* 0x0104..0x0107 */
+ unsigned long aes_key[4];
+ /* 0x0110 */
+ unsigned long aes_keylen;
+ /* 0x0100..0x0101 */
+ unsigned long aes_result[2];
+
+ /* CRC */
+ /* 0x0201 */
+ unsigned long crc_iv;
+ /* 0x0202, set: 0x1202 */
+ unsigned long crc_length;
+ /* 0x0200, set: 0x4200 */
+ unsigned long crc_poly;
+
+ /* Low-latency memory stuff */
+ /* 0x0402, 0x040A */
+ unsigned long llm_dat[2];
+
+ /* SHA & MD5 */
+ /* 0x0240..0x024E */
+ unsigned long hsh_datw[15];
+ /* 0x0250..0x0257 */
+ unsigned long hsh_ivw[8];
+
+ /* GFM */
+ /* 0x0258..0x0259 */
+ unsigned long gfm_mult[2];
+ /* 0x025E */
+ unsigned long gfm_poly;
+ /* 0x025A..0x025B */
+ unsigned long gfm_result[2];
+};
+
+/* Prototypes */
+
+void octeon_cop2_save(struct octeon_cop2_state *);
+void octeon_cop2_restore(struct octeon_cop2_state *);
+
+#endif /* LOCORE */
+#endif /* __OCTEON_COP2_H__ */
Property changes on: trunk/sys/mips/cavium/octeon_cop2.h
___________________________________________________________________
Added: svn:eol-style
## -0,0 +1 ##
+native
\ No newline at end of property
Added: svn:keywords
## -0,0 +1 ##
+MidnightBSD=%H
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+text/plain
\ No newline at end of property
Added: trunk/sys/mips/cavium/octeon_ds1337.c
===================================================================
--- trunk/sys/mips/cavium/octeon_ds1337.c (rev 0)
+++ trunk/sys/mips/cavium/octeon_ds1337.c 2018-05-26 21:55:02 UTC (rev 9987)
@@ -0,0 +1,221 @@
+/* $MidnightBSD$ */
+/***********************license start***************
+ * Copyright (c) 2003-2008 Cavium Networks (support at cavium.com). All rights
+ * reserved.
+ *
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
+ *
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ *
+ * * Redistributions in binary form must reproduce the above
+ * copyright notice, this list of conditions and the following
+ * disclaimer in the documentation and/or other materials provided
+ * with the distribution.
+ *
+ * * Neither the name of Cavium Networks nor the names of
+ * its contributors may be used to endorse or promote products
+ * derived from this software without specific prior written
+ * permission.
+ *
+ * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
+ * AND WITH ALL FAULTS AND CAVIUM NETWORKS MAKES NO PROMISES, REPRESENTATIONS
+ * OR WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH
+ * RESPECT TO THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY
+ * REPRESENTATION OR DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT
+ * DEFECTS, AND CAVIUM SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES
+ * OF TITLE, MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR
+ * PURPOSE, LACK OF VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET
+ * POSSESSION OR CORRESPONDENCE TO DESCRIPTION. THE ENTIRE RISK ARISING OUT
+ * OF USE OR PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
+ *
+ *
+ * For any questions regarding licensing please contact marketing at caviumnetworks.com
+ *
+ ***********************license end**************************************/
+
+
+
+
+
+
+/**
+ * @file
+ *
+ * Interface to the EBH-30xx specific devices
+ *
+ * <hr>$Revision: 41586 $<hr>
+ *
+ */
+
+#include <sys/cdefs.h>
+__FBSDID("$FreeBSD: stable/10/sys/mips/cavium/octeon_ds1337.c 229161 2011-12-31 23:21:36Z gonzo $");
+
+#include <sys/param.h>
+#include <sys/timespec.h>
+#include <sys/clock.h>
+#include <sys/libkern.h>
+
+#include <contrib/octeon-sdk/cvmx.h>
+#include <contrib/octeon-sdk/cvmx-cn3010-evb-hs5.h>
+#include <contrib/octeon-sdk/cvmx-twsi.h>
+
+#define CT_CHECK(_expr, _msg) \
+ do { \
+ if (_expr) { \
+ cvmx_dprintf("Warning: RTC has invalid %s field\n", (_msg)); \
+ rc = -1; \
+ } \
+ } while(0);
+
+static int validate_ct_struct(struct clocktime *ct)
+{
+ int rc = 0;
+
+ if (!ct)
+ return -1;
+
+ CT_CHECK(ct->sec < 0 || ct->sec > 60, "second"); /* + Leap sec */
+ CT_CHECK(ct->min < 0 || ct->min > 59, "minute");
+ CT_CHECK(ct->hour < 0 || ct->hour > 23, "hour");
+ CT_CHECK(ct->day < 1 || ct->day > 31, "day");
+ CT_CHECK(ct->dow < 1 || ct->dow > 7, "day of week");
+ CT_CHECK(ct->mon < 1 || ct->mon > 12, "month");
+ CT_CHECK(ct->year > 2037,"year");
+
+ return rc;
+}
+
+/*
+ * Board-specifc RTC read
+ * Time is expressed in seconds from epoch (Jan 1 1970 at 00:00:00 UTC)
+ * and converted internally to calendar format.
+ */
+uint32_t cvmx_rtc_ds1337_read(void)
+{
+ int i, retry;
+ uint8_t reg[8];
+ uint8_t sec;
+ struct clocktime ct;
+ struct timespec ts;
+
+
+ memset(®, 0, sizeof(reg));
+ memset(&ct, 0, sizeof(ct));
+
+ for(retry=0; retry<2; retry++)
+ {
+ /* Lockless read: detects the infrequent roll-over and retries */
+ reg[0] = cvmx_twsi_read8(CVMX_RTC_DS1337_ADDR, 0x0);
+ for(i=1; i<7; i++)
+ reg[i] = cvmx_twsi_read8_cur_addr(CVMX_RTC_DS1337_ADDR);
+
+ sec = cvmx_twsi_read8(CVMX_RTC_DS1337_ADDR, 0x0);
+ if ((sec & 0xf) == (reg[0] & 0xf))
+ break; /* Time did not roll-over, value is correct */
+ }
+
+ ct.sec = bcd2bin(reg[0] & 0x7f);
+ ct.min = bcd2bin(reg[1] & 0x7f);
+ ct.hour = bcd2bin(reg[2] & 0x3f);
+ if ((reg[2] & 0x40) && (reg[2] & 0x20)) /* AM/PM format and is PM time */
+ {
+ ct.hour = (ct.hour + 12) % 24;
+ }
+ ct.dow = (reg[3] & 0x7); /* Day of week field is 1..7 */
+ ct.day = bcd2bin(reg[4] & 0x3f);
+ ct.mon = bcd2bin(reg[5] & 0x1f); /* Month field is 1..12 */
+#if defined(OCTEON_BOARD_CAPK_0100ND)
+ /*
+ * CAPK-0100ND uses DS1307 that does not have century bit
+ */
+ ct.year = 2000 + bcd2bin(reg[6]);
+#else
+ ct.year = ((reg[5] & 0x80) ? 2000 : 1900) + bcd2bin(reg[6]);
+#endif
+
+
+ if (validate_ct_struct(&ct))
+ cvmx_dprintf("Warning: RTC calendar is not configured properly\n");
+
+ if (clock_ct_to_ts(&ct, &ts) != 0) {
+ cvmx_dprintf("Warning: RTC calendar is not configured properly\n");
+ return 0;
+ }
+
+ return ts.tv_sec;
+}
+
+/*
+ * Board-specific RTC write
+ * Time returned is in seconds from epoch (Jan 1 1970 at 00:00:00 UTC)
+ */
+int cvmx_rtc_ds1337_write(uint32_t time)
+{
+ struct clocktime ct;
+ struct timespec ts;
+ int i, rc, retry;
+ uint8_t reg[8];
+ uint8_t sec;
+
+ ts.tv_sec = time;
+ ts.tv_nsec = 0;
+
+ clock_ts_to_ct(&ts, &ct);
+
+ if (validate_ct_struct(&ct))
+ {
+ cvmx_dprintf("Error: RTC was passed wrong calendar values, write failed\n");
+ goto ct_invalid;
+ }
+
+ reg[0] = bin2bcd(ct.sec);
+ reg[1] = bin2bcd(ct.min);
+ reg[2] = bin2bcd(ct.hour); /* Force 0..23 format even if using AM/PM */
+ reg[3] = bin2bcd(ct.dow);
+ reg[4] = bin2bcd(ct.day);
+ reg[5] = bin2bcd(ct.mon);
+ if (ct.year >= 2000) /* Set century bit*/
+ {
+ reg[5] |= 0x80;
+ }
+ reg[6] = bin2bcd(ct.year % 100);
+
+ /* Lockless write: detects the infrequent roll-over and retries */
+ for(retry=0; retry<2; retry++)
+ {
+ rc = 0;
+ for(i=0; i<7; i++)
+ {
+ rc |= cvmx_twsi_write8(CVMX_RTC_DS1337_ADDR, i, reg[i]);
+ }
+
+ sec = cvmx_twsi_read8(CVMX_RTC_DS1337_ADDR, 0x0);
+ if ((sec & 0xf) == (reg[0] & 0xf))
+ break; /* Time did not roll-over, value is correct */
+ }
+
+ return (rc ? -1 : 0);
+
+ ct_invalid:
+ return -1;
+}
+
+#ifdef CVMX_RTC_DEBUG
+
+void cvmx_rtc_ds1337_dump_state(void)
+{
+ int i = 0;
+
+ printf("RTC:\n");
+ printf("%d : %02X ", i, cvmx_twsi_read8(CVMX_RTC_DS1337_ADDR, 0x0));
+ for(i=1; i<16; i++) {
+ printf("%02X ", cvmx_twsi_read8_cur_addr(CVMX_RTC_DS1337_ADDR));
+ }
+ printf("\n");
+}
+
+#endif /* CVMX_RTC_DEBUG */
Property changes on: trunk/sys/mips/cavium/octeon_ds1337.c
___________________________________________________________________
Added: svn:eol-style
## -0,0 +1 ##
+native
\ No newline at end of property
Added: svn:keywords
## -0,0 +1 ##
+MidnightBSD=%H
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+text/plain
\ No newline at end of property
Added: trunk/sys/mips/cavium/octeon_ebt3000_cf.c
===================================================================
--- trunk/sys/mips/cavium/octeon_ebt3000_cf.c (rev 0)
+++ trunk/sys/mips/cavium/octeon_ebt3000_cf.c 2018-05-26 21:55:02 UTC (rev 9987)
@@ -0,0 +1,738 @@
+/* $MidnightBSD$ */
+/***********************license start***************
+ * Copyright (c) 2003-2008 Cavium Networks (support at cavium.com). All rights
+ * reserved.
+ *
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
+ *
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ *
+ * * Redistributions in binary form must reproduce the above
+ * copyright notice, this list of conditions and the following
+ * disclaimer in the documentation and/or other materials provided
+ * with the distribution.
+ *
+ * * Neither the name of Cavium Networks nor the names of
+ * its contributors may be used to endorse or promote products
+ * derived from this software without specific prior written
+ * permission.
+ *
+ * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
+ * AND WITH ALL FAULTS AND CAVIUM NETWORKS MAKES NO PROMISES, REPRESENTATIONS
+ * OR WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH
+ * RESPECT TO THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY
+ * REPRESENTATION OR DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT
+ * DEFECTS, AND CAVIUM SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES
+ * OF TITLE, MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR
+ * PURPOSE, LACK OF VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET
+ * POSSESSION OR CORRESPONDENCE TO DESCRIPTION. THE ENTIRE RISK ARISING OUT
+ * OF USE OR PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
+ *
+ *
+ * For any questions regarding licensing please contact marketing at caviumnetworks.com
+ *
+ ***********************license end**************************************/
+
+/*
+ * octeon_ebt3000_cf.c
+ *
+ */
+
+#include <sys/cdefs.h>
+__FBSDID("$FreeBSD: stable/10/sys/mips/cavium/octeon_ebt3000_cf.c 265999 2014-05-14 01:35:43Z ian $");
+
+#include <sys/param.h>
+#include <sys/bio.h>
+#include <sys/systm.h>
+#include <sys/sysctl.h>
+#include <sys/ata.h>
+#include <sys/bus.h>
+#include <sys/kernel.h>
+#include <sys/module.h>
+#include <sys/rman.h>
+#include <sys/power.h>
+#include <sys/smp.h>
+#include <sys/time.h>
+#include <sys/timetc.h>
+#include <sys/malloc.h>
+
+#include <geom/geom.h>
+
+#include <machine/clock.h>
+#include <machine/locore.h>
+#include <machine/md_var.h>
+#include <machine/cpuregs.h>
+
+#include <mips/cavium/octeon_pcmap_regs.h>
+
+#include <contrib/octeon-sdk/cvmx.h>
+
+/* ATA Commands */
+#define CMD_READ_SECTOR 0x20
+#define CMD_WRITE_SECTOR 0x30
+#define CMD_IDENTIFY 0xEC
+
+/* The ATA Task File */
+#define TF_DATA 0x00
+#define TF_ERROR 0x01
+#define TF_PRECOMP 0x01
+#define TF_SECTOR_COUNT 0x02
+#define TF_SECTOR_NUMBER 0x03
+#define TF_CYL_LSB 0x04
+#define TF_CYL_MSB 0x05
+#define TF_DRV_HEAD 0x06
+#define TF_STATUS 0x07
+#define TF_COMMAND 0x07
+
+/* Status Register */
+#define STATUS_BSY 0x80 /* Drive is busy */
+#define STATUS_RDY 0x40 /* Drive is ready */
+#define STATUS_DF 0x20 /* Device fault */
+#define STATUS_DRQ 0x08 /* Data can be transferred */
+
+/* Miscelaneous */
+#define SECTOR_SIZE 512
+#define WAIT_DELAY 1000
+#define NR_TRIES 1000
+#define SWAP_SHORT(x) ((x << 8) | (x >> 8))
+#define MODEL_STR_SIZE 40
+
+/* Globals */
+/*
+ * There's three bus types supported by this driver.
+ *
+ * CF_8 -- Traditional PC Card IDE interface on an 8-bit wide bus. We assume
+ * the bool loader has configure attribute memory properly. We then access
+ * the device like old-school 8-bit IDE card (which is all a traditional PC Card
+ * interface really is).
+ * CF_16 -- Traditional PC Card IDE interface on a 16-bit wide bus. Registers on
+ * this bus are 16-bits wide too. When accessing registers in the task file, you
+ * have to do it in 16-bit chunks, and worry about masking out what you don't want
+ * or ORing together the traditional 8-bit values. We assume the bootloader does
+ * the right attribute memory initialization dance.
+ * CF_TRUE_IDE_8 - CF Card wired to True IDE mode. There's no Attribute memory
+ * space at all. Instead all the traditional 8-bit registers are there, but
+ * on a 16-bit bus where addr0 isn't wired. This means we need to read/write them
+ * 16-bit chunks, but only the lower 8 bits are valid. We do not (and can not)
+ * access this like CF_16 with the comingled registers. Yet we can't access
+ * this like CF_8 because of the register offset. Except the TF_DATA register
+ * appears to be full width?
+ */
+void *base_addr;
+int bus_type;
+#define CF_8 1 /* 8-bit bus, no offsets - PC Card */
+#define CF_16 2 /* 16-bit bus, registers shared - PC Card */
+#define CF_TRUE_IDE_8 3 /* 16-bit bus, only lower 8-bits, TrueIDE */
+const char *const cf_type[] = {
+ "impossible type",
+ "CF 8-bit",
+ "CF 16-bit",
+ "True IDE"
+};
+
+/* Device parameters */
+struct drive_param{
+ union {
+ char buf[SECTOR_SIZE];
+ struct ata_params driveid;
+ } u;
+
+ char model[MODEL_STR_SIZE];
+ uint32_t nr_sectors;
+ uint16_t sector_size;
+ uint16_t heads;
+ uint16_t tracks;
+ uint16_t sec_track;
+};
+
+/* Device softc */
+struct cf_priv {
+ device_t dev;
+ struct drive_param drive_param;
+
+ struct bio_queue_head cf_bq;
+ struct g_geom *cf_geom;
+ struct g_provider *cf_provider;
+
+};
+
+/* GEOM class implementation */
+static g_access_t cf_access;
+static g_start_t cf_start;
+static g_ioctl_t cf_ioctl;
+
+struct g_class g_cf_class = {
+ .name = "CF",
+ .version = G_VERSION,
+ .start = cf_start,
+ .access = cf_access,
+ .ioctl = cf_ioctl,
+};
+
+DECLARE_GEOM_CLASS(g_cf_class, g_cf);
+
+/* Device methods */
+static int cf_probe(device_t);
+static void cf_identify(driver_t *, device_t);
+static int cf_attach(device_t);
+static void cf_attach_geom(void *, int);
+
+/* ATA methods */
+static int cf_cmd_identify(struct cf_priv *);
+static int cf_cmd_write(uint32_t, uint32_t, void *);
+static int cf_cmd_read(uint32_t, uint32_t, void *);
+static int cf_wait_busy(void);
+static int cf_send_cmd(uint32_t, uint8_t);
+
+/* Miscelenous */
+static void cf_swap_ascii(unsigned char[], char[]);
+
+
+/* ------------------------------------------------------------------- *
+ * cf_access() *
+ * ------------------------------------------------------------------- */
+static int cf_access (struct g_provider *pp, int r, int w, int e)
+{
+ return (0);
+}
+
+
+/* ------------------------------------------------------------------- *
+ * cf_start() *
+ * ------------------------------------------------------------------- */
+static void cf_start (struct bio *bp)
+{
+ struct cf_priv *cf_priv;
+ int error;
+
+ cf_priv = bp->bio_to->geom->softc;
+
+ /*
+ * Handle actual I/O requests. The request is passed down through
+ * the bio struct.
+ */
+
+ if(bp->bio_cmd & BIO_GETATTR) {
+ if (g_handleattr_int(bp, "GEOM::fwsectors", cf_priv->drive_param.sec_track))
+ return;
+ if (g_handleattr_int(bp, "GEOM::fwheads", cf_priv->drive_param.heads))
+ return;
+ g_io_deliver(bp, ENOIOCTL);
+ return;
+ }
+
+ if ((bp->bio_cmd & (BIO_READ | BIO_WRITE))) {
+
+ if (bp->bio_cmd & BIO_READ) {
+ error = cf_cmd_read(bp->bio_length / cf_priv->drive_param.sector_size,
+ bp->bio_offset / cf_priv->drive_param.sector_size, bp->bio_data);
+ } else if (bp->bio_cmd & BIO_WRITE) {
+ error = cf_cmd_write(bp->bio_length / cf_priv->drive_param.sector_size,
+ bp->bio_offset/cf_priv->drive_param.sector_size, bp->bio_data);
+ } else {
+ printf("%s: unrecognized bio_cmd %x.\n", __func__, bp->bio_cmd);
+ error = ENOTSUP;
+ }
+
+ if (error != 0) {
+ g_io_deliver(bp, error);
+ return;
+ }
+
+ bp->bio_resid = 0;
+ bp->bio_completed = bp->bio_length;
+ g_io_deliver(bp, 0);
+ }
+}
+
+
+static int cf_ioctl (struct g_provider *pp, u_long cmd, void *data, int fflag, struct thread *td)
+{
+ return (0);
+}
+
+
+static uint8_t cf_inb_8(int port)
+{
+ /*
+ * Traditional 8-bit PC Card/CF bus access.
+ */
+ if (bus_type == CF_8) {
+ volatile uint8_t *task_file = (volatile uint8_t *)base_addr;
+ return task_file[port];
+ }
+
+ /*
+ * True IDE access. lower 8 bits on a 16-bit bus (see above).
+ */
+ volatile uint16_t *task_file = (volatile uint16_t *)base_addr;
+ return task_file[port] & 0xff;
+}
+
+static void cf_outb_8(int port, uint8_t val)
+{
+ /*
+ * Traditional 8-bit PC Card/CF bus access.
+ */
+ if (bus_type == CF_8) {
+ volatile uint8_t *task_file = (volatile uint8_t *)base_addr;
+ task_file[port] = val;
+ return;
+ }
+
+ /*
+ * True IDE access. lower 8 bits on a 16-bit bus (see above).
+ */
+ volatile uint16_t *task_file = (volatile uint16_t *)base_addr;
+ task_file[port] = val & 0xff;
+}
+
+static uint8_t cf_inb_16(int port)
+{
+ volatile uint16_t *task_file = (volatile uint16_t *)base_addr;
+ uint16_t val = task_file[port / 2];
+ if (port & 1)
+ return (val >> 8) & 0xff;
+ return val & 0xff;
+}
+
+static uint16_t cf_inw_16(int port)
+{
+ volatile uint16_t *task_file = (volatile uint16_t *)base_addr;
+ uint16_t val = task_file[port / 2];
+ return val;
+}
+
+static void cf_outw_16(int port, uint16_t val)
+{
+ volatile uint16_t *task_file = (volatile uint16_t *)base_addr;
+ task_file[port / 2] = val;
+}
+
+/* ------------------------------------------------------------------- *
+ * cf_cmd_read() *
+ * ------------------------------------------------------------------- *
+ *
+ * Read nr_sectors from the device starting from start_sector.
+ */
+static int cf_cmd_read (uint32_t nr_sectors, uint32_t start_sector, void *buf)
+{
+ unsigned long lba;
+ uint32_t count;
+ uint16_t *ptr_16;
+ uint8_t *ptr_8;
+ int error;
+
+ ptr_8 = (uint8_t*)buf;
+ ptr_16 = (uint16_t*)buf;
+ lba = start_sector;
+
+ while (nr_sectors--) {
+ error = cf_send_cmd(lba, CMD_READ_SECTOR);
+ if (error != 0) {
+ printf("%s: cf_send_cmd(CMD_READ_SECTOR) failed: %d\n", __func__, error);
+ return (error);
+ }
+
+ switch (bus_type)
+ {
+ case CF_8:
+ for (count = 0; count < SECTOR_SIZE; count++) {
+ *ptr_8++ = cf_inb_8(TF_DATA);
+ if ((count & 0xf) == 0)
+ (void)cf_inb_8(TF_STATUS);
+ }
+ break;
+ case CF_TRUE_IDE_8:
+ case CF_16:
+ default:
+ for (count = 0; count < SECTOR_SIZE; count+=2) {
+ uint16_t temp;
+ temp = cf_inw_16(TF_DATA);
+ *ptr_16++ = SWAP_SHORT(temp);
+ if ((count & 0xf) == 0)
+ (void)cf_inb_16(TF_STATUS);
+ }
+ break;
+ }
+
+ lba++;
+ }
+ return (0);
+}
+
+
+/* ------------------------------------------------------------------- *
+ * cf_cmd_write() *
+ * ------------------------------------------------------------------- *
+ *
+ * Write nr_sectors to the device starting from start_sector.
+ */
+static int cf_cmd_write (uint32_t nr_sectors, uint32_t start_sector, void *buf)
+{
+ uint32_t lba;
+ uint32_t count;
+ uint16_t *ptr_16;
+ uint8_t *ptr_8;
+ int error;
+
+ lba = start_sector;
+ ptr_8 = (uint8_t*)buf;
+ ptr_16 = (uint16_t*)buf;
+
+ while (nr_sectors--) {
+ error = cf_send_cmd(lba, CMD_WRITE_SECTOR);
+ if (error != 0) {
+ printf("%s: cf_send_cmd(CMD_WRITE_SECTOR) failed: %d\n", __func__, error);
+ return (error);
+ }
+
+ switch (bus_type)
+ {
+ case CF_8:
+ for (count = 0; count < SECTOR_SIZE; count++) {
+ cf_outb_8(TF_DATA, *ptr_8++);
+ if ((count & 0xf) == 0)
+ (void)cf_inb_8(TF_STATUS);
+ }
+ break;
+ case CF_TRUE_IDE_8:
+ case CF_16:
+ default:
+ for (count = 0; count < SECTOR_SIZE; count+=2) {
+ uint16_t temp = *ptr_16++;
+ cf_outw_16(TF_DATA, SWAP_SHORT(temp));
+ if ((count & 0xf) == 0)
+ (void)cf_inb_16(TF_STATUS);
+ }
+ break;
+ }
+
+ lba++;
+ }
+ return (0);
+}
+
+
+/* ------------------------------------------------------------------- *
+ * cf_cmd_identify() *
+ * ------------------------------------------------------------------- *
+ *
+ * Read parameters and other information from the drive and store
+ * it in the drive_param structure
+ *
+ */
+static int cf_cmd_identify(struct cf_priv *cf_priv)
+{
+ int count;
+ int error;
+
+ error = cf_send_cmd(0, CMD_IDENTIFY);
+ if (error != 0) {
+ printf("%s: identify failed: %d\n", __func__, error);
+ return (error);
+ }
+ switch (bus_type)
+ {
+ case CF_8:
+ for (count = 0; count < SECTOR_SIZE; count++)
+ cf_priv->drive_param.u.buf[count] = cf_inb_8(TF_DATA);
+ break;
+ case CF_TRUE_IDE_8:
+ case CF_16:
+ default:
+ for (count = 0; count < SECTOR_SIZE; count += 2) {
+ uint16_t temp;
+ temp = cf_inw_16(TF_DATA);
+
+ /* endianess will be swapped below */
+ cf_priv->drive_param.u.buf[count] = (temp & 0xff);
+ cf_priv->drive_param.u.buf[count + 1] = (temp & 0xff00) >> 8;
+ }
+ break;
+ }
+
+ cf_swap_ascii(cf_priv->drive_param.u.driveid.model, cf_priv->drive_param.model);
+
+ cf_priv->drive_param.sector_size = 512; //= SWAP_SHORT (cf_priv->drive_param.u.driveid.sector_bytes);
+ cf_priv->drive_param.heads = SWAP_SHORT (cf_priv->drive_param.u.driveid.current_heads);
+ cf_priv->drive_param.tracks = SWAP_SHORT (cf_priv->drive_param.u.driveid.current_cylinders);
+ cf_priv->drive_param.sec_track = SWAP_SHORT (cf_priv->drive_param.u.driveid.current_sectors);
+ cf_priv->drive_param.nr_sectors = (uint32_t)SWAP_SHORT (cf_priv->drive_param.u.driveid.lba_size_1) |
+ ((uint32_t)SWAP_SHORT (cf_priv->drive_param.u.driveid.lba_size_2));
+ if (bootverbose) {
+ printf(" model %s\n", cf_priv->drive_param.model);
+ printf(" heads %d tracks %d sec_tracks %d sectors %d\n",
+ cf_priv->drive_param.heads, cf_priv->drive_param.tracks,
+ cf_priv->drive_param.sec_track, cf_priv->drive_param.nr_sectors);
+ }
+
+ return (0);
+}
+
+
+/* ------------------------------------------------------------------- *
+ * cf_send_cmd() *
+ * ------------------------------------------------------------------- *
+ *
+ * Send command to read/write one sector specified by lba.
+ *
+ */
+static int cf_send_cmd (uint32_t lba, uint8_t cmd)
+{
+ switch (bus_type)
+ {
+ case CF_8:
+ case CF_TRUE_IDE_8:
+ while (cf_inb_8(TF_STATUS) & STATUS_BSY)
+ DELAY(WAIT_DELAY);
+ cf_outb_8(TF_SECTOR_COUNT, 1);
+ cf_outb_8(TF_SECTOR_NUMBER, lba & 0xff);
+ cf_outb_8(TF_CYL_LSB, (lba >> 8) & 0xff);
+ cf_outb_8(TF_CYL_MSB, (lba >> 16) & 0xff);
+ cf_outb_8(TF_DRV_HEAD, ((lba >> 24) & 0xff) | 0xe0);
+ cf_outb_8(TF_COMMAND, cmd);
+ break;
+ case CF_16:
+ default:
+ while (cf_inb_16(TF_STATUS) & STATUS_BSY)
+ DELAY(WAIT_DELAY);
+ cf_outw_16(TF_SECTOR_COUNT, 1 | ((lba & 0xff) << 8));
+ cf_outw_16(TF_CYL_LSB, ((lba >> 8) & 0xff) | (((lba >> 16) & 0xff) << 8));
+ cf_outw_16(TF_DRV_HEAD, (((lba >> 24) & 0xff) | 0xe0) | (cmd << 8));
+ break;
+ }
+
+ return (cf_wait_busy());
+}
+
+/* ------------------------------------------------------------------- *
+ * cf_wait_busy() *
+ * ------------------------------------------------------------------- *
+ *
+ * Wait until the drive finishes a given command and data is
+ * ready to be transferred. This is done by repeatedly checking
+ * the BSY bit of the status register. When the controller is ready for
+ * data transfer, it clears the BSY bit and sets the DRQ bit.
+ *
+ * If the DF bit is ever set, we return error.
+ *
+ * This code originally spun on DRQ. If that behavior turns out to be
+ * necessary, a flag can be added or this function can be called
+ * repeatedly as long as it is returning ENXIO.
+ */
+static int cf_wait_busy (void)
+{
+ uint8_t status;
+
+ switch (bus_type)
+ {
+ case CF_8:
+ case CF_TRUE_IDE_8:
+ status = cf_inb_8(TF_STATUS);
+ while ((status & STATUS_BSY) == STATUS_BSY) {
+ if ((status & STATUS_DF) != 0) {
+ printf("%s: device fault (status=%x)\n", __func__, status);
+ return (EIO);
+ }
+ DELAY(WAIT_DELAY);
+ status = cf_inb_8(TF_STATUS);
+ }
+ break;
+ case CF_16:
+ default:
+ status = cf_inb_16(TF_STATUS);
+ while ((status & STATUS_BSY) == STATUS_BSY) {
+ if ((status & STATUS_DF) != 0) {
+ printf("%s: device fault (status=%x)\n", __func__, status);
+ return (EIO);
+ }
+ DELAY(WAIT_DELAY);
+ status = cf_inb_16(TF_STATUS);
+ }
+ break;
+ }
+
+ /* DRQ is only for when read data is actually available; check BSY */
+ /* Some vendors do assert DRQ, but not all. Check BSY instead. */
+ if (status & STATUS_BSY) {
+ printf("%s: device not ready (status=%x)\n", __func__, status);
+ return (ENXIO);
+ }
+
+ return (0);
+}
+
+/* ------------------------------------------------------------------- *
+ * cf_swap_ascii() *
+ * ------------------------------------------------------------------- *
+ *
+ * The ascii string returned by the controller specifying
+ * the model of the drive is byte-swaped. This routine
+ * corrects the byte ordering.
+ *
+ */
+static void cf_swap_ascii (unsigned char str1[], char str2[])
+{
+ int i;
+
+ for(i = 0; i < MODEL_STR_SIZE; i++)
+ str2[i] = str1[i ^ 1];
+}
+
+
+/* ------------------------------------------------------------------- *
+ * cf_probe() *
+ * ------------------------------------------------------------------- */
+
+static int cf_probe (device_t dev)
+{
+ if (cvmx_sysinfo_get()->board_type == CVMX_BOARD_TYPE_SIM)
+ return (ENXIO);
+
+ if (device_get_unit(dev) != 0) {
+ panic("can't attach more devices\n");
+ }
+
+ device_set_desc(dev, "Octeon Compact Flash Driver");
+
+ return (BUS_PROBE_NOWILDCARD);
+}
+
+/* ------------------------------------------------------------------- *
+ * cf_identify() *
+ * ------------------------------------------------------------------- *
+ *
+ * Find the bootbus region for the CF to determine
+ * 16 or 8 bit and check to see if device is
+ * inserted.
+ *
+ */
+static void cf_identify (driver_t *drv, device_t parent)
+{
+ int bus_region;
+ int count = 0;
+ cvmx_mio_boot_reg_cfgx_t cfg;
+ uint64_t phys_base;
+
+ if (cvmx_sysinfo_get()->board_type == CVMX_BOARD_TYPE_SIM)
+ return;
+
+ phys_base = cvmx_sysinfo_get()->compact_flash_common_base_addr;
+ if (phys_base == 0)
+ return;
+ base_addr = cvmx_phys_to_ptr(phys_base);
+
+ for (bus_region = 0; bus_region < 8; bus_region++)
+ {
+ cfg.u64 = cvmx_read_csr(CVMX_MIO_BOOT_REG_CFGX(bus_region));
+ if (cfg.s.base == phys_base >> 16)
+ {
+ if (cvmx_sysinfo_get()->compact_flash_attribute_base_addr == 0)
+ bus_type = CF_TRUE_IDE_8;
+ else
+ bus_type = (cfg.s.width) ? CF_16 : CF_8;
+ printf("Compact flash found in bootbus region %d (%s).\n", bus_region, cf_type[bus_type]);
+ break;
+ }
+ }
+
+ switch (bus_type)
+ {
+ case CF_8:
+ case CF_TRUE_IDE_8:
+ /* Check if CF is inserted */
+ while (cf_inb_8(TF_STATUS) & STATUS_BSY) {
+ if ((count++) == NR_TRIES ) {
+ printf("Compact Flash not present\n");
+ return;
+ }
+ DELAY(WAIT_DELAY);
+ }
+ break;
+ case CF_16:
+ default:
+ /* Check if CF is inserted */
+ while (cf_inb_16(TF_STATUS) & STATUS_BSY) {
+ if ((count++) == NR_TRIES ) {
+ printf("Compact Flash not present\n");
+ return;
+ }
+ DELAY(WAIT_DELAY);
+ }
+ break;
+ }
+
+ BUS_ADD_CHILD(parent, 0, "cf", 0);
+}
+
+
+/* ------------------------------------------------------------------- *
+ * cf_attach_geom() *
+ * ------------------------------------------------------------------- */
+
+static void cf_attach_geom (void *arg, int flag)
+{
+ struct cf_priv *cf_priv;
+
+ cf_priv = (struct cf_priv *) arg;
+ cf_priv->cf_geom = g_new_geomf(&g_cf_class, "cf%d", device_get_unit(cf_priv->dev));
+ cf_priv->cf_geom->softc = cf_priv;
+ cf_priv->cf_provider = g_new_providerf(cf_priv->cf_geom, cf_priv->cf_geom->name);
+ cf_priv->cf_provider->sectorsize = cf_priv->drive_param.sector_size;
+ cf_priv->cf_provider->mediasize = cf_priv->drive_param.nr_sectors * cf_priv->cf_provider->sectorsize;
+ g_error_provider(cf_priv->cf_provider, 0);
+}
+
+/* ------------------------------------------------------------------- *
+ * cf_attach() *
+ * ------------------------------------------------------------------- */
+
+static int cf_attach (device_t dev)
+{
+ struct cf_priv *cf_priv;
+ int error;
+
+ if (cvmx_sysinfo_get()->board_type == CVMX_BOARD_TYPE_SIM)
+ return (ENXIO);
+
+ cf_priv = device_get_softc(dev);
+ cf_priv->dev = dev;
+
+ error = cf_cmd_identify(cf_priv);
+ if (error != 0) {
+ device_printf(dev, "cf_cmd_identify failed: %d\n", error);
+ return (error);
+ }
+
+ g_post_event(cf_attach_geom, cf_priv, M_WAITOK, NULL);
+ bioq_init(&cf_priv->cf_bq);
+
+ return 0;
+}
+
+
+static device_method_t cf_methods[] = {
+ /* Device interface */
+ DEVMETHOD(device_probe, cf_probe),
+ DEVMETHOD(device_identify, cf_identify),
+ DEVMETHOD(device_attach, cf_attach),
+ DEVMETHOD(device_detach, bus_generic_detach),
+ DEVMETHOD(device_shutdown, bus_generic_shutdown),
+
+ { 0, 0 }
+};
+
+static driver_t cf_driver = {
+ "cf",
+ cf_methods,
+ sizeof(struct cf_priv)
+};
+
+static devclass_t cf_devclass;
+
+DRIVER_MODULE(cf, nexus, cf_driver, cf_devclass, 0, 0);
Property changes on: trunk/sys/mips/cavium/octeon_ebt3000_cf.c
___________________________________________________________________
Added: svn:eol-style
## -0,0 +1 ##
+native
\ No newline at end of property
Added: svn:keywords
## -0,0 +1 ##
+MidnightBSD=%H
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+text/plain
\ No newline at end of property
Added: trunk/sys/mips/cavium/octeon_gpio.c
===================================================================
--- trunk/sys/mips/cavium/octeon_gpio.c (rev 0)
+++ trunk/sys/mips/cavium/octeon_gpio.c 2018-05-26 21:55:02 UTC (rev 9987)
@@ -0,0 +1,487 @@
+/* $MidnightBSD$ */
+/*-
+ * Copyright (c) 2011, Oleksandr Tymoshenko <gonzo at FreeBSD.org>
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice unmodified, this list of conditions, and the following
+ * disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ */
+
+/*
+ * GPIO driver for Cavium Octeon
+ */
+
+#include <sys/cdefs.h>
+__FBSDID("$FreeBSD: stable/10/sys/mips/cavium/octeon_gpio.c 278786 2015-02-14 21:16:19Z loos $");
+
+#include <sys/param.h>
+#include <sys/systm.h>
+#include <sys/bus.h>
+
+#include <sys/kernel.h>
+#include <sys/module.h>
+#include <sys/rman.h>
+#include <sys/lock.h>
+#include <sys/mutex.h>
+#include <sys/gpio.h>
+
+#include <machine/bus.h>
+#include <machine/resource.h>
+
+#include <contrib/octeon-sdk/cvmx.h>
+#include <contrib/octeon-sdk/cvmx-gpio.h>
+#include <mips/cavium/octeon_irq.h>
+
+#include <mips/cavium/octeon_gpiovar.h>
+
+#include "gpio_if.h"
+
+#define DEFAULT_CAPS (GPIO_PIN_INPUT | GPIO_PIN_OUTPUT)
+
+struct octeon_gpio_pin {
+ const char *name;
+ int pin;
+ int flags;
+};
+
+/*
+ * on CAP100 GPIO 7 is "Factory defaults" button
+ *
+ */
+static struct octeon_gpio_pin octeon_gpio_pins[] = {
+ { "F/D", 7, GPIO_PIN_INPUT},
+ { NULL, 0, 0},
+};
+
+/*
+ * Helpers
+ */
+static void octeon_gpio_pin_configure(struct octeon_gpio_softc *sc,
+ struct gpio_pin *pin, uint32_t flags);
+
+/*
+ * Driver stuff
+ */
+static void octeon_gpio_identify(driver_t *, device_t);
+static int octeon_gpio_probe(device_t dev);
+static int octeon_gpio_attach(device_t dev);
+static int octeon_gpio_detach(device_t dev);
+static int octeon_gpio_filter(void *arg);
+static void octeon_gpio_intr(void *arg);
+
+/*
+ * GPIO interface
+ */
+static int octeon_gpio_pin_max(device_t dev, int *maxpin);
+static int octeon_gpio_pin_getcaps(device_t dev, uint32_t pin, uint32_t *caps);
+static int octeon_gpio_pin_getflags(device_t dev, uint32_t pin, uint32_t
+ *flags);
+static int octeon_gpio_pin_getname(device_t dev, uint32_t pin, char *name);
+static int octeon_gpio_pin_setflags(device_t dev, uint32_t pin, uint32_t flags);
+static int octeon_gpio_pin_set(device_t dev, uint32_t pin, unsigned int value);
+static int octeon_gpio_pin_get(device_t dev, uint32_t pin, unsigned int *val);
+static int octeon_gpio_pin_toggle(device_t dev, uint32_t pin);
+
+static void
+octeon_gpio_pin_configure(struct octeon_gpio_softc *sc, struct gpio_pin *pin,
+ unsigned int flags)
+{
+ uint32_t mask;
+ cvmx_gpio_bit_cfgx_t gpio_cfgx;
+
+ mask = 1 << pin->gp_pin;
+ GPIO_LOCK(sc);
+
+ /*
+ * Manage input/output
+ */
+ if (flags & (GPIO_PIN_INPUT|GPIO_PIN_OUTPUT)) {
+ gpio_cfgx.u64 = cvmx_read_csr(CVMX_GPIO_BIT_CFGX(pin->gp_pin));
+ pin->gp_flags &= ~(GPIO_PIN_INPUT|GPIO_PIN_OUTPUT);
+ if (flags & GPIO_PIN_OUTPUT) {
+ pin->gp_flags |= GPIO_PIN_OUTPUT;
+ gpio_cfgx.s.tx_oe = 1;
+ }
+ else {
+ pin->gp_flags |= GPIO_PIN_INPUT;
+ gpio_cfgx.s.tx_oe = 0;
+ }
+ if (flags & GPIO_PIN_INVIN)
+ gpio_cfgx.s.rx_xor = 1;
+ else
+ gpio_cfgx.s.rx_xor = 0;
+ cvmx_write_csr(CVMX_GPIO_BIT_CFGX(pin->gp_pin), gpio_cfgx.u64);
+ }
+
+ GPIO_UNLOCK(sc);
+}
+
+static int
+octeon_gpio_pin_max(device_t dev, int *maxpin)
+{
+
+ *maxpin = OCTEON_GPIO_PINS - 1;
+ return (0);
+}
+
+static int
+octeon_gpio_pin_getcaps(device_t dev, uint32_t pin, uint32_t *caps)
+{
+ struct octeon_gpio_softc *sc = device_get_softc(dev);
+ int i;
+
+ for (i = 0; i < sc->gpio_npins; i++) {
+ if (sc->gpio_pins[i].gp_pin == pin)
+ break;
+ }
+
+ if (i >= sc->gpio_npins)
+ return (EINVAL);
+
+ GPIO_LOCK(sc);
+ *caps = sc->gpio_pins[i].gp_caps;
+ GPIO_UNLOCK(sc);
+
+ return (0);
+}
+
+static int
+octeon_gpio_pin_getflags(device_t dev, uint32_t pin, uint32_t *flags)
+{
+ struct octeon_gpio_softc *sc = device_get_softc(dev);
+ int i;
+
+ for (i = 0; i < sc->gpio_npins; i++) {
+ if (sc->gpio_pins[i].gp_pin == pin)
+ break;
+ }
+
+ if (i >= sc->gpio_npins)
+ return (EINVAL);
+
+ GPIO_LOCK(sc);
+ *flags = sc->gpio_pins[i].gp_flags;
+ GPIO_UNLOCK(sc);
+
+ return (0);
+}
+
+static int
+octeon_gpio_pin_getname(device_t dev, uint32_t pin, char *name)
+{
+ struct octeon_gpio_softc *sc = device_get_softc(dev);
+ int i;
+
+ for (i = 0; i < sc->gpio_npins; i++) {
+ if (sc->gpio_pins[i].gp_pin == pin)
+ break;
+ }
+
+ if (i >= sc->gpio_npins)
+ return (EINVAL);
+
+ GPIO_LOCK(sc);
+ memcpy(name, sc->gpio_pins[i].gp_name, GPIOMAXNAME);
+ GPIO_UNLOCK(sc);
+
+ return (0);
+}
+
+static int
+octeon_gpio_pin_setflags(device_t dev, uint32_t pin, uint32_t flags)
+{
+ int i;
+ struct octeon_gpio_softc *sc = device_get_softc(dev);
+
+ for (i = 0; i < sc->gpio_npins; i++) {
+ if (sc->gpio_pins[i].gp_pin == pin)
+ break;
+ }
+
+ if (i >= sc->gpio_npins)
+ return (EINVAL);
+
+ octeon_gpio_pin_configure(sc, &sc->gpio_pins[i], flags);
+
+ return (0);
+}
+
+static int
+octeon_gpio_pin_set(device_t dev, uint32_t pin, unsigned int value)
+{
+ struct octeon_gpio_softc *sc = device_get_softc(dev);
+ int i;
+
+ for (i = 0; i < sc->gpio_npins; i++) {
+ if (sc->gpio_pins[i].gp_pin == pin)
+ break;
+ }
+
+ if (i >= sc->gpio_npins)
+ return (EINVAL);
+
+ GPIO_LOCK(sc);
+ if (value)
+ cvmx_gpio_set(1 << pin);
+ else
+ cvmx_gpio_clear(1 << pin);
+ GPIO_UNLOCK(sc);
+
+ return (0);
+}
+
+static int
+octeon_gpio_pin_get(device_t dev, uint32_t pin, unsigned int *val)
+{
+ struct octeon_gpio_softc *sc = device_get_softc(dev);
+ int i;
+ uint64_t state;
+
+ for (i = 0; i < sc->gpio_npins; i++) {
+ if (sc->gpio_pins[i].gp_pin == pin)
+ break;
+ }
+
+ if (i >= sc->gpio_npins)
+ return (EINVAL);
+
+ GPIO_LOCK(sc);
+ state = cvmx_gpio_read();
+ *val = (state & (1 << pin)) ? 1 : 0;
+ GPIO_UNLOCK(sc);
+
+ return (0);
+}
+
+static int
+octeon_gpio_pin_toggle(device_t dev, uint32_t pin)
+{
+ int i;
+ uint64_t state;
+ struct octeon_gpio_softc *sc = device_get_softc(dev);
+
+ for (i = 0; i < sc->gpio_npins; i++) {
+ if (sc->gpio_pins[i].gp_pin == pin)
+ break;
+ }
+
+ if (i >= sc->gpio_npins)
+ return (EINVAL);
+
+ GPIO_LOCK(sc);
+ /*
+ * XXX: Need to check if read returns actual state of output
+ * pins or we need to keep this information by ourself
+ */
+ state = cvmx_gpio_read();
+ if (state & (1 << pin))
+ cvmx_gpio_clear(1 << pin);
+ else
+ cvmx_gpio_set(1 << pin);
+ GPIO_UNLOCK(sc);
+
+ return (0);
+}
+
+static int
+octeon_gpio_filter(void *arg)
+{
+ cvmx_gpio_bit_cfgx_t gpio_cfgx;
+ void **cookie = arg;
+ struct octeon_gpio_softc *sc = *cookie;
+ long int irq = (cookie - sc->gpio_intr_cookies);
+
+ if ((irq < 0) || (irq >= OCTEON_GPIO_IRQS))
+ return (FILTER_STRAY);
+
+ gpio_cfgx.u64 = cvmx_read_csr(CVMX_GPIO_BIT_CFGX(irq));
+ /* Clear rising edge detector */
+ if (gpio_cfgx.s.int_type == OCTEON_GPIO_IRQ_EDGE)
+ cvmx_gpio_interrupt_clear(1 << irq);
+ /* disable interrupt */
+ gpio_cfgx.s.int_en = 0;
+ cvmx_write_csr(CVMX_GPIO_BIT_CFGX(irq), gpio_cfgx.u64);
+
+ return (FILTER_SCHEDULE_THREAD);
+}
+
+static void
+octeon_gpio_intr(void *arg)
+{
+ cvmx_gpio_bit_cfgx_t gpio_cfgx;
+ void **cookie = arg;
+ struct octeon_gpio_softc *sc = *cookie;
+ long int irq = (cookie - sc->gpio_intr_cookies);
+
+ if ((irq < 0) || (irq >= OCTEON_GPIO_IRQS)) {
+ printf("%s: invalid GPIO IRQ: %ld\n",
+ __func__, irq);
+ return;
+ }
+
+ GPIO_LOCK(sc);
+ gpio_cfgx.u64 = cvmx_read_csr(CVMX_GPIO_BIT_CFGX(irq));
+ /* disable interrupt */
+ gpio_cfgx.s.int_en = 1;
+ cvmx_write_csr(CVMX_GPIO_BIT_CFGX(irq), gpio_cfgx.u64);
+
+ /* TODO: notify bus here or something */
+ printf("GPIO IRQ for pin %ld\n", irq);
+ GPIO_UNLOCK(sc);
+}
+
+static void
+octeon_gpio_identify(driver_t *drv, device_t parent)
+{
+
+ BUS_ADD_CHILD(parent, 0, "gpio", 0);
+}
+
+static int
+octeon_gpio_probe(device_t dev)
+{
+
+ device_set_desc(dev, "Cavium Octeon GPIO driver");
+ return (0);
+}
+
+static int
+octeon_gpio_attach(device_t dev)
+{
+ struct octeon_gpio_softc *sc = device_get_softc(dev);
+ struct octeon_gpio_pin *pinp;
+ cvmx_gpio_bit_cfgx_t gpio_cfgx;
+
+ int i;
+
+ KASSERT((device_get_unit(dev) == 0),
+ ("octeon_gpio: Only one gpio module supported"));
+
+ mtx_init(&sc->gpio_mtx, device_get_nameunit(dev), NULL, MTX_DEF);
+
+ for ( i = 0; i < OCTEON_GPIO_IRQS; i++) {
+ if ((sc->gpio_irq_res[i] = bus_alloc_resource(dev,
+ SYS_RES_IRQ, &sc->gpio_irq_rid[i],
+ OCTEON_IRQ_GPIO0 + i, OCTEON_IRQ_GPIO0 + i, 1,
+ RF_SHAREABLE | RF_ACTIVE)) == NULL) {
+ device_printf(dev, "unable to allocate IRQ resource\n");
+ return (ENXIO);
+ }
+
+ sc->gpio_intr_cookies[i] = sc;
+ if ((bus_setup_intr(dev, sc->gpio_irq_res[i], INTR_TYPE_MISC,
+ octeon_gpio_filter, octeon_gpio_intr,
+ &(sc->gpio_intr_cookies[i]), &sc->gpio_ih[i]))) {
+ device_printf(dev,
+ "WARNING: unable to register interrupt handler\n");
+ return (ENXIO);
+ }
+ }
+
+ sc->dev = dev;
+ /* Configure all pins as input */
+ /* disable interrupts for all pins */
+ pinp = octeon_gpio_pins;
+ i = 0;
+ while (pinp->name) {
+ strncpy(sc->gpio_pins[i].gp_name, pinp->name, GPIOMAXNAME);
+ sc->gpio_pins[i].gp_pin = pinp->pin;
+ sc->gpio_pins[i].gp_caps = DEFAULT_CAPS;
+ sc->gpio_pins[i].gp_flags = 0;
+ octeon_gpio_pin_configure(sc, &sc->gpio_pins[i], pinp->flags);
+ pinp++;
+ i++;
+ }
+
+ sc->gpio_npins = i;
+
+#if 0
+ /*
+ * Sample: how to enable edge-triggered interrupt
+ * for GPIO pin
+ */
+ gpio_cfgx.u64 = cvmx_read_csr(CVMX_GPIO_BIT_CFGX(7));
+ gpio_cfgx.s.int_en = 1;
+ gpio_cfgx.s.int_type = OCTEON_GPIO_IRQ_EDGE;
+ cvmx_write_csr(CVMX_GPIO_BIT_CFGX(7), gpio_cfgx.u64);
+#endif
+
+ if (bootverbose) {
+ for (i = 0; i < 16; i++) {
+ gpio_cfgx.u64 = cvmx_read_csr(CVMX_GPIO_BIT_CFGX(i));
+ device_printf(dev, "[pin%d] output=%d, invinput=%d, intr=%d, intr_type=%s\n",
+ i, gpio_cfgx.s.tx_oe, gpio_cfgx.s.rx_xor,
+ gpio_cfgx.s.int_en, gpio_cfgx.s.int_type ? "rising edge" : "level");
+ }
+ }
+
+ device_add_child(dev, "gpioc", -1);
+ device_add_child(dev, "gpiobus", -1);
+
+ return (bus_generic_attach(dev));
+}
+
+static int
+octeon_gpio_detach(device_t dev)
+{
+ struct octeon_gpio_softc *sc = device_get_softc(dev);
+ int i;
+
+ KASSERT(mtx_initialized(&sc->gpio_mtx), ("gpio mutex not initialized"));
+
+ for ( i = 0; i < OCTEON_GPIO_IRQS; i++) {
+ bus_release_resource(dev, SYS_RES_IRQ,
+ sc->gpio_irq_rid[i], sc->gpio_irq_res[i]);
+ }
+ bus_generic_detach(dev);
+
+ mtx_destroy(&sc->gpio_mtx);
+
+ return(0);
+}
+
+static device_method_t octeon_gpio_methods[] = {
+ DEVMETHOD(device_identify, octeon_gpio_identify),
+ DEVMETHOD(device_probe, octeon_gpio_probe),
+ DEVMETHOD(device_attach, octeon_gpio_attach),
+ DEVMETHOD(device_detach, octeon_gpio_detach),
+
+ /* GPIO protocol */
+ DEVMETHOD(gpio_pin_max, octeon_gpio_pin_max),
+ DEVMETHOD(gpio_pin_getname, octeon_gpio_pin_getname),
+ DEVMETHOD(gpio_pin_getflags, octeon_gpio_pin_getflags),
+ DEVMETHOD(gpio_pin_getcaps, octeon_gpio_pin_getcaps),
+ DEVMETHOD(gpio_pin_setflags, octeon_gpio_pin_setflags),
+ DEVMETHOD(gpio_pin_get, octeon_gpio_pin_get),
+ DEVMETHOD(gpio_pin_set, octeon_gpio_pin_set),
+ DEVMETHOD(gpio_pin_toggle, octeon_gpio_pin_toggle),
+ {0, 0},
+};
+
+static driver_t octeon_gpio_driver = {
+ "gpio",
+ octeon_gpio_methods,
+ sizeof(struct octeon_gpio_softc),
+};
+static devclass_t octeon_gpio_devclass;
+
+DRIVER_MODULE(octeon_gpio, ciu, octeon_gpio_driver, octeon_gpio_devclass, 0, 0);
Property changes on: trunk/sys/mips/cavium/octeon_gpio.c
___________________________________________________________________
Added: svn:eol-style
## -0,0 +1 ##
+native
\ No newline at end of property
Added: svn:keywords
## -0,0 +1 ##
+MidnightBSD=%H
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+text/plain
\ No newline at end of property
Added: trunk/sys/mips/cavium/octeon_gpiovar.h
===================================================================
--- trunk/sys/mips/cavium/octeon_gpiovar.h (rev 0)
+++ trunk/sys/mips/cavium/octeon_gpiovar.h 2018-05-26 21:55:02 UTC (rev 9987)
@@ -0,0 +1,56 @@
+/* $MidnightBSD$ */
+/*-
+ * Copyright (c) 2011, Oleksandr Tymoshenko <gonzo at FreeBSD.org>
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice unmodified, this list of conditions, and the following
+ * disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ * $FreeBSD: stable/10/sys/mips/cavium/octeon_gpiovar.h 228925 2011-12-28 05:57:03Z gonzo $
+ *
+ */
+
+#ifndef __OCTEON_GPIOVAR_H__
+#define __OCTEON_GPIOVAR_H__
+
+#define GPIO_LOCK(_sc) mtx_lock(&(_sc)->gpio_mtx)
+#define GPIO_UNLOCK(_sc) mtx_unlock(&(_sc)->gpio_mtx)
+#define GPIO_LOCK_ASSERT(_sc) mtx_assert(&(_sc)->gpio_mtx, MA_OWNED)
+
+#define OCTEON_GPIO_IRQ_LEVEL 0
+#define OCTEON_GPIO_IRQ_EDGE 1
+
+#define OCTEON_GPIO_PINS 24
+#define OCTEON_GPIO_IRQS 16
+
+struct octeon_gpio_softc {
+ device_t dev;
+ struct mtx gpio_mtx;
+ struct resource *gpio_irq_res[OCTEON_GPIO_IRQS];
+ int gpio_irq_rid[OCTEON_GPIO_IRQS];
+ void *gpio_ih[OCTEON_GPIO_IRQS];
+ void *gpio_intr_cookies[OCTEON_GPIO_IRQS];
+ int gpio_npins;
+ struct gpio_pin gpio_pins[OCTEON_GPIO_PINS];
+};
+
+#endif /* __OCTEON_GPIOVAR_H__ */
Property changes on: trunk/sys/mips/cavium/octeon_gpiovar.h
___________________________________________________________________
Added: svn:eol-style
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+native
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+MidnightBSD=%H
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+text/plain
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Added: trunk/sys/mips/cavium/octeon_irq.h
===================================================================
--- trunk/sys/mips/cavium/octeon_irq.h (rev 0)
+++ trunk/sys/mips/cavium/octeon_irq.h 2018-05-26 21:55:02 UTC (rev 9987)
@@ -0,0 +1,182 @@
+/* $MidnightBSD$ */
+/***********************license start***************
+ * Copyright (c) 2003-2010 Cavium Networks (support at cavium.com). All rights
+ * reserved.
+ *
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
+ *
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ *
+ * * Redistributions in binary form must reproduce the above
+ * copyright notice, this list of conditions and the following
+ * disclaimer in the documentation and/or other materials provided
+ * with the distribution.
+
+ * * Neither the name of Cavium Networks nor the names of
+ * its contributors may be used to endorse or promote products
+ * derived from this software without specific prior written
+ * permission.
+
+ * This Software, including technical data, may be subject to U.S. export control
+ * laws, including the U.S. Export Administration Act and its associated
+ * regulations, and may be subject to export or import regulations in other
+ * countries.
+
+ * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
+ * AND WITH ALL FAULTS AND CAVIUM NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR
+ * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
+ * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
+ * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
+ * SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES OF TITLE,
+ * MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR PURPOSE, LACK OF
+ * VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET POSSESSION OR
+ * CORRESPONDENCE TO DESCRIPTION. THE ENTIRE RISK ARISING OUT OF USE OR
+ * PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
+ ***********************license end**************************************/
+
+#ifndef __OCTEON_IRQ_H__
+#define __OCTEON_IRQ_H__
+
+/*
+ * $FreeBSD: stable/10/sys/mips/cavium/octeon_irq.h 233417 2012-03-24 06:28:15Z gonzo $
+ */
+
+/**
+ * Enumeration of Interrupt numbers
+ */
+typedef enum
+{
+ /* 0 - 7 represent the 8 MIPS standard interrupt sources */
+ OCTEON_IRQ_SW0 = 0,
+ OCTEON_IRQ_SW1 = 1,
+ OCTEON_IRQ_CIU0 = 2,
+ OCTEON_IRQ_CIU1 = 3,
+ OCTEON_IRQ_4 = 4,
+ OCTEON_IRQ_5 = 5,
+ OCTEON_IRQ_6 = 6,
+ OCTEON_IRQ_7 = 7,
+
+ /* 8 - 71 represent the sources in CIU_INTX_EN0 */
+ OCTEON_IRQ_WORKQ0 = 8,
+ OCTEON_IRQ_WORKQ1 = 9,
+ OCTEON_IRQ_WORKQ2 = 10,
+ OCTEON_IRQ_WORKQ3 = 11,
+ OCTEON_IRQ_WORKQ4 = 12,
+ OCTEON_IRQ_WORKQ5 = 13,
+ OCTEON_IRQ_WORKQ6 = 14,
+ OCTEON_IRQ_WORKQ7 = 15,
+ OCTEON_IRQ_WORKQ8 = 16,
+ OCTEON_IRQ_WORKQ9 = 17,
+ OCTEON_IRQ_WORKQ10 = 18,
+ OCTEON_IRQ_WORKQ11 = 19,
+ OCTEON_IRQ_WORKQ12 = 20,
+ OCTEON_IRQ_WORKQ13 = 21,
+ OCTEON_IRQ_WORKQ14 = 22,
+ OCTEON_IRQ_WORKQ15 = 23,
+ OCTEON_IRQ_GPIO0 = 24,
+ OCTEON_IRQ_GPIO1 = 25,
+ OCTEON_IRQ_GPIO2 = 26,
+ OCTEON_IRQ_GPIO3 = 27,
+ OCTEON_IRQ_GPIO4 = 28,
+ OCTEON_IRQ_GPIO5 = 29,
+ OCTEON_IRQ_GPIO6 = 30,
+ OCTEON_IRQ_GPIO7 = 31,
+ OCTEON_IRQ_GPIO8 = 32,
+ OCTEON_IRQ_GPIO9 = 33,
+ OCTEON_IRQ_GPIO10 = 34,
+ OCTEON_IRQ_GPIO11 = 35,
+ OCTEON_IRQ_GPIO12 = 36,
+ OCTEON_IRQ_GPIO13 = 37,
+ OCTEON_IRQ_GPIO14 = 38,
+ OCTEON_IRQ_GPIO15 = 39,
+ OCTEON_IRQ_MBOX0 = 40,
+ OCTEON_IRQ_MBOX1 = 41,
+ OCTEON_IRQ_UART0 = 42,
+ OCTEON_IRQ_UART1 = 43,
+ OCTEON_IRQ_PCI_INT0 = 44,
+ OCTEON_IRQ_PCI_INT1 = 45,
+ OCTEON_IRQ_PCI_INT2 = 46,
+ OCTEON_IRQ_PCI_INT3 = 47,
+ OCTEON_IRQ_PCI_MSI0 = 48,
+ OCTEON_IRQ_PCI_MSI1 = 49,
+ OCTEON_IRQ_PCI_MSI2 = 50,
+ OCTEON_IRQ_PCI_MSI3 = 51,
+ OCTEON_IRQ_RESERVED44 = 52,
+ OCTEON_IRQ_TWSI = 53,
+ OCTEON_IRQ_RML = 54,
+ OCTEON_IRQ_TRACE = 55,
+ OCTEON_IRQ_GMX_DRP0 = 56,
+ OCTEON_IRQ_GMX_DRP1 = 57, /* Doesn't apply on CN52XX or CN63XX */
+ OCTEON_IRQ_IPD_DRP = 58,
+ OCTEON_IRQ_KEY_ZERO = 59, /* Doesn't apply on CN52XX or CN63XX */
+ OCTEON_IRQ_TIMER0 = 60,
+ OCTEON_IRQ_TIMER1 = 61,
+ OCTEON_IRQ_TIMER2 = 62,
+ OCTEON_IRQ_TIMER3 = 63,
+ OCTEON_IRQ_USB0 = 64, /* Doesn't apply on CN38XX or CN58XX */
+ OCTEON_IRQ_PCM = 65, /* Doesn't apply on CN52XX or CN63XX */
+ OCTEON_IRQ_MPI = 66, /* Doesn't apply on CN52XX or CN63XX */
+ OCTEON_IRQ_TWSI2 = 67, /* Added in CN56XX */
+ OCTEON_IRQ_POWIQ = 68, /* Added in CN56XX */
+ OCTEON_IRQ_IPDPPTHR = 69, /* Added in CN56XX */
+ OCTEON_IRQ_MII = 70, /* Added in CN56XX */
+ OCTEON_IRQ_BOOTDMA = 71, /* Added in CN56XX */
+
+ /* 72 - 135 represent the sources in CIU_INTX_EN1 */
+ OCTEON_IRQ_WDOG0 = 72,
+ OCTEON_IRQ_WDOG1 = 73,
+ OCTEON_IRQ_WDOG2 = 74,
+ OCTEON_IRQ_WDOG3 = 75,
+ OCTEON_IRQ_WDOG4 = 76,
+ OCTEON_IRQ_WDOG5 = 77,
+ OCTEON_IRQ_WDOG6 = 78,
+ OCTEON_IRQ_WDOG7 = 79,
+ OCTEON_IRQ_WDOG8 = 80,
+ OCTEON_IRQ_WDOG9 = 81,
+ OCTEON_IRQ_WDOG10= 82,
+ OCTEON_IRQ_WDOG11= 83,
+ OCTEON_IRQ_WDOG12= 84,
+ OCTEON_IRQ_WDOG13= 85,
+ OCTEON_IRQ_WDOG14= 86,
+ OCTEON_IRQ_WDOG15= 87,
+ OCTEON_IRQ_UART2 = 88, /* Added in CN52XX */
+ OCTEON_IRQ_USB1 = 89, /* Added in CN52XX */
+ OCTEON_IRQ_MII1 = 90, /* Added in CN52XX */
+ OCTEON_IRQ_NAND = 91, /* Added in CN52XX */
+ OCTEON_IRQ_MIO = 92, /* Added in CN63XX */
+ OCTEON_IRQ_IOB = 93, /* Added in CN63XX */
+ OCTEON_IRQ_FPA = 94, /* Added in CN63XX */
+ OCTEON_IRQ_POW = 95, /* Added in CN63XX */
+ OCTEON_IRQ_L2C = 96, /* Added in CN63XX */
+ OCTEON_IRQ_IPD = 97, /* Added in CN63XX */
+ OCTEON_IRQ_PIP = 98, /* Added in CN63XX */
+ OCTEON_IRQ_PKO = 99, /* Added in CN63XX */
+ OCTEON_IRQ_ZIP = 100, /* Added in CN63XX */
+ OCTEON_IRQ_TIM = 101, /* Added in CN63XX */
+ OCTEON_IRQ_RAD = 102, /* Added in CN63XX */
+ OCTEON_IRQ_KEY = 103, /* Added in CN63XX */
+ OCTEON_IRQ_DFA = 104, /* Added in CN63XX */
+ OCTEON_IRQ_USB = 105, /* Added in CN63XX */
+ OCTEON_IRQ_SLI = 106, /* Added in CN63XX */
+ OCTEON_IRQ_DPI = 107, /* Added in CN63XX */
+ OCTEON_IRQ_AGX0 = 108, /* Added in CN63XX */
+ /* 109 - 117 are reserved */
+ OCTEON_IRQ_AGL = 118, /* Added in CN63XX */
+ OCTEON_IRQ_PTP = 119, /* Added in CN63XX */
+ OCTEON_IRQ_PEM0 = 120, /* Added in CN63XX */
+ OCTEON_IRQ_PEM1 = 121, /* Added in CN63XX */
+ OCTEON_IRQ_SRIO0 = 122, /* Added in CN63XX */
+ OCTEON_IRQ_SRIO1 = 123, /* Added in CN63XX */
+ OCTEON_IRQ_LMC0 = 124, /* Added in CN63XX */
+ /* Interrupts 125 - 127 are reserved */
+ OCTEON_IRQ_DFM = 128, /* Added in CN63XX */
+ /* Interrupts 129 - 135 are reserved */
+} octeon_irq_t;
+
+#define OCTEON_PMC_IRQ OCTEON_IRQ_4
+
+#endif
Property changes on: trunk/sys/mips/cavium/octeon_irq.h
___________________________________________________________________
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+MidnightBSD=%H
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## -0,0 +1 ##
+text/plain
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Added: trunk/sys/mips/cavium/octeon_machdep.c
===================================================================
--- trunk/sys/mips/cavium/octeon_machdep.c (rev 0)
+++ trunk/sys/mips/cavium/octeon_machdep.c 2018-05-26 21:55:02 UTC (rev 9987)
@@ -0,0 +1,663 @@
+/* $MidnightBSD$ */
+/*-
+ * Copyright (c) 2006 Wojciech A. Koszek <wkoszek at FreeBSD.org>
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ * $FreeBSD: stable/10/sys/mips/cavium/octeon_machdep.c 247297 2013-02-26 01:00:11Z attilio $
+ */
+#include <sys/cdefs.h>
+__FBSDID("$FreeBSD: stable/10/sys/mips/cavium/octeon_machdep.c 247297 2013-02-26 01:00:11Z attilio $");
+
+#include <sys/param.h>
+#include <sys/conf.h>
+#include <sys/kernel.h>
+#include <sys/systm.h>
+#include <sys/imgact.h>
+#include <sys/bio.h>
+#include <sys/buf.h>
+#include <sys/bus.h>
+#include <sys/cpu.h>
+#include <sys/cons.h>
+#include <sys/exec.h>
+#include <sys/ucontext.h>
+#include <sys/proc.h>
+#include <sys/kdb.h>
+#include <sys/ptrace.h>
+#include <sys/reboot.h>
+#include <sys/signalvar.h>
+#include <sys/sysctl.h>
+#include <sys/sysent.h>
+#include <sys/sysproto.h>
+#include <sys/time.h>
+#include <sys/timetc.h>
+#include <sys/user.h>
+
+#include <vm/vm.h>
+#include <vm/vm_object.h>
+#include <vm/vm_page.h>
+
+#include <machine/atomic.h>
+#include <machine/cache.h>
+#include <machine/clock.h>
+#include <machine/cpu.h>
+#include <machine/cpuregs.h>
+#include <machine/cpufunc.h>
+#include <mips/cavium/octeon_pcmap_regs.h>
+#include <machine/hwfunc.h>
+#include <machine/intr_machdep.h>
+#include <machine/locore.h>
+#include <machine/md_var.h>
+#include <machine/pcpu.h>
+#include <machine/pte.h>
+#include <machine/trap.h>
+#include <machine/vmparam.h>
+
+#include <contrib/octeon-sdk/cvmx.h>
+#include <contrib/octeon-sdk/cvmx-bootmem.h>
+#include <contrib/octeon-sdk/cvmx-ebt3000.h>
+#include <contrib/octeon-sdk/cvmx-helper-cfg.h>
+#include <contrib/octeon-sdk/cvmx-interrupt.h>
+#include <contrib/octeon-sdk/cvmx-version.h>
+
+#include <mips/cavium/octeon_irq.h>
+
+#if defined(__mips_n64)
+#define MAX_APP_DESC_ADDR 0xffffffffafffffff
+#else
+#define MAX_APP_DESC_ADDR 0xafffffff
+#endif
+
+struct octeon_feature_description {
+ octeon_feature_t ofd_feature;
+ const char *ofd_string;
+};
+
+extern int *end;
+extern char cpu_model[];
+extern char cpu_board[];
+
+static const struct octeon_feature_description octeon_feature_descriptions[] = {
+ { OCTEON_FEATURE_SAAD, "SAAD" },
+ { OCTEON_FEATURE_ZIP, "ZIP" },
+ { OCTEON_FEATURE_CRYPTO, "CRYPTO" },
+ { OCTEON_FEATURE_DORM_CRYPTO, "DORM_CRYPTO" },
+ { OCTEON_FEATURE_PCIE, "PCIE" },
+ { OCTEON_FEATURE_SRIO, "SRIO" },
+ { OCTEON_FEATURE_KEY_MEMORY, "KEY_MEMORY" },
+ { OCTEON_FEATURE_LED_CONTROLLER, "LED_CONTROLLER" },
+ { OCTEON_FEATURE_TRA, "TRA" },
+ { OCTEON_FEATURE_MGMT_PORT, "MGMT_PORT" },
+ { OCTEON_FEATURE_RAID, "RAID" },
+ { OCTEON_FEATURE_USB, "USB" },
+ { OCTEON_FEATURE_NO_WPTR, "NO_WPTR" },
+ { OCTEON_FEATURE_DFA, "DFA" },
+ { OCTEON_FEATURE_MDIO_CLAUSE_45, "MDIO_CLAUSE_45" },
+ { OCTEON_FEATURE_NPEI, "NPEI" },
+ { OCTEON_FEATURE_ILK, "ILK" },
+ { OCTEON_FEATURE_HFA, "HFA" },
+ { OCTEON_FEATURE_DFM, "DFM" },
+ { OCTEON_FEATURE_CIU2, "CIU2" },
+ { OCTEON_FEATURE_DICI_MODE, "DICI_MODE" },
+ { OCTEON_FEATURE_BIT_EXTRACTOR, "BIT_EXTRACTOR" },
+ { OCTEON_FEATURE_NAND, "NAND" },
+ { OCTEON_FEATURE_MMC, "MMC" },
+ { OCTEON_FEATURE_PKND, "PKND" },
+ { OCTEON_FEATURE_CN68XX_WQE, "CN68XX_WQE" },
+ { 0, NULL }
+};
+
+static uint64_t octeon_get_ticks(void);
+static unsigned octeon_get_timecount(struct timecounter *tc);
+
+static void octeon_boot_params_init(register_t ptr);
+
+static struct timecounter octeon_timecounter = {
+ octeon_get_timecount, /* get_timecount */
+ 0, /* no poll_pps */
+ 0xffffffffu, /* octeon_mask */
+ 0, /* frequency */
+ "Octeon", /* name */
+ 900, /* quality (adjusted in code) */
+};
+
+void
+platform_cpu_init()
+{
+ /* Nothing special yet */
+}
+
+/*
+ * Perform a board-level soft-reset.
+ */
+void
+platform_reset(void)
+{
+ cvmx_write_csr(CVMX_CIU_SOFT_RST, 1);
+}
+
+/*
+ * octeon_debug_symbol
+ *
+ * Does nothing.
+ * Used to mark the point for simulator to begin tracing
+ */
+void
+octeon_debug_symbol(void)
+{
+}
+
+/*
+ * octeon_ciu_reset
+ *
+ * Shutdown all CIU to IP2, IP3 mappings
+ */
+void
+octeon_ciu_reset(void)
+{
+ uint64_t cvmctl;
+
+ /* Disable all CIU interrupts by default */
+ cvmx_write_csr(CVMX_CIU_INTX_EN0(cvmx_get_core_num()*2), 0);
+ cvmx_write_csr(CVMX_CIU_INTX_EN0(cvmx_get_core_num()*2+1), 0);
+ cvmx_write_csr(CVMX_CIU_INTX_EN1(cvmx_get_core_num()*2), 0);
+ cvmx_write_csr(CVMX_CIU_INTX_EN1(cvmx_get_core_num()*2+1), 0);
+
+#ifdef SMP
+ /* Enable the MBOX interrupts. */
+ cvmx_write_csr(CVMX_CIU_INTX_EN0(cvmx_get_core_num()*2+1),
+ (1ull << (OCTEON_IRQ_MBOX0 - 8)) |
+ (1ull << (OCTEON_IRQ_MBOX1 - 8)));
+#endif
+
+ /*
+ * Move the Performance Counter interrupt to OCTEON_PMC_IRQ
+ */
+ cvmctl = mips_rd_cvmctl();
+ cvmctl &= ~(7 << 7);
+ cvmctl |= (OCTEON_PMC_IRQ + 2) << 7;
+ mips_wr_cvmctl(cvmctl);
+}
+
+static void
+octeon_memory_init(void)
+{
+ vm_paddr_t phys_end;
+ int64_t addr;
+ unsigned i, j;
+
+ phys_end = round_page(MIPS_KSEG0_TO_PHYS((vm_offset_t)&end));
+
+ if (cvmx_sysinfo_get()->board_type == CVMX_BOARD_TYPE_SIM) {
+ /* Simulator we limit to 96 meg */
+ phys_avail[0] = phys_end;
+ phys_avail[1] = 96 << 20;
+
+ dump_avail[0] = phys_avail[0];
+ dump_avail[1] = phys_avail[1];
+
+ realmem = physmem = btoc(phys_avail[1] - phys_avail[0]);
+ return;
+ }
+
+ /*
+ * Allocate memory from bootmem 1MB at a time and merge
+ * adjacent entries.
+ */
+ i = 0;
+ while (i < PHYS_AVAIL_ENTRIES) {
+ /*
+ * If there is less than 2MB of memory available in 128-byte
+ * blocks, do not steal any more memory. We need to leave some
+ * memory for the command queues to be allocated out of.
+ */
+ if (cvmx_bootmem_available_mem(128) < 2 << 20)
+ break;
+
+ addr = cvmx_bootmem_phy_alloc(1 << 20, phys_end,
+ ~(vm_paddr_t)0, PAGE_SIZE, 0);
+ if (addr == -1)
+ break;
+
+ /*
+ * The SDK needs to be able to easily map any memory that might
+ * come to it e.g. in the form of an mbuf. Because on !n64 we
+ * can't direct-map some addresses and we don't want to manage
+ * temporary mappings within the SDK, don't feed memory that
+ * can't be direct-mapped to the kernel.
+ */
+#if !defined(__mips_n64)
+ if (!MIPS_DIRECT_MAPPABLE(addr + (1 << 20) - 1))
+ continue;
+#endif
+
+ physmem += btoc(1 << 20);
+
+ if (i > 0 && phys_avail[i - 1] == addr) {
+ phys_avail[i - 1] += 1 << 20;
+ continue;
+ }
+
+ phys_avail[i + 0] = addr;
+ phys_avail[i + 1] = addr + (1 << 20);
+
+ i += 2;
+ }
+
+ for (j = 0; j < i; j++)
+ dump_avail[j] = phys_avail[j];
+
+ realmem = physmem;
+}
+
+void
+platform_start(__register_t a0, __register_t a1, __register_t a2 __unused,
+ __register_t a3)
+{
+ const struct octeon_feature_description *ofd;
+ uint64_t platform_counter_freq;
+ int rv;
+
+ mips_postboot_fixup();
+
+ /*
+ * Initialize boot parameters so that we can determine things like
+ * which console we shoud use, etc.
+ */
+ octeon_boot_params_init(a3);
+
+ /* Initialize pcpu stuff */
+ mips_pcpu0_init();
+ mips_timer_early_init(cvmx_sysinfo_get()->cpu_clock_hz);
+
+ /* Initialize console. */
+ cninit();
+
+ /*
+ * Display information about the CPU.
+ */
+#if !defined(OCTEON_MODEL)
+ printf("Using runtime CPU model checks.\n");
+#else
+ printf("Compiled for CPU model: " __XSTRING(OCTEON_MODEL) "\n");
+#endif
+ strcpy(cpu_model, octeon_model_get_string(cvmx_get_proc_id()));
+ printf("CPU Model: %s\n", cpu_model);
+ printf("CPU clock: %uMHz Core Mask: %#x\n",
+ cvmx_sysinfo_get()->cpu_clock_hz / 1000000,
+ cvmx_sysinfo_get()->core_mask);
+ rv = octeon_model_version_check(cvmx_get_proc_id());
+ if (rv == -1)
+ panic("%s: kernel not compatible with this processor.", __func__);
+
+ /*
+ * Display information about the board.
+ */
+#if defined(OCTEON_BOARD_CAPK_0100ND)
+ strcpy(cpu_board, "CAPK-0100ND");
+ if (cvmx_sysinfo_get()->board_type != CVMX_BOARD_TYPE_CN3010_EVB_HS5) {
+ panic("Compiled for %s, but board type is %s.", cpu_board,
+ cvmx_board_type_to_string(cvmx_sysinfo_get()->board_type));
+ }
+#else
+ strcpy(cpu_board,
+ cvmx_board_type_to_string(cvmx_sysinfo_get()->board_type));
+#endif
+ printf("Board: %s\n", cpu_board);
+ printf("Board Type: %u Revision: %u/%u\n",
+ cvmx_sysinfo_get()->board_type,
+ cvmx_sysinfo_get()->board_rev_major,
+ cvmx_sysinfo_get()->board_rev_minor);
+ printf("Serial number: %s\n", cvmx_sysinfo_get()->board_serial_number);
+
+ /*
+ * Additional on-chip hardware/settings.
+ *
+ * XXX Display PCI host/target? What else?
+ */
+ printf("MAC address base: %6D (%u configured)\n",
+ cvmx_sysinfo_get()->mac_addr_base, ":",
+ cvmx_sysinfo_get()->mac_addr_count);
+
+
+ octeon_ciu_reset();
+ /*
+ * XXX
+ * We can certainly parse command line arguments or U-Boot environment
+ * to determine whether to bootverbose / single user / ... I think
+ * stass has patches to add support for loader things to U-Boot even.
+ */
+ bootverbose = 1;
+
+ /*
+ * For some reason on the cn38xx simulator ebase register is set to
+ * 0x80001000 at bootup time. Move it back to the default, but
+ * when we move to having support for multiple executives, we need
+ * to rethink this.
+ */
+ mips_wr_ebase(0x80000000);
+
+ octeon_memory_init();
+ init_param1();
+ init_param2(physmem);
+ mips_cpu_init();
+ pmap_bootstrap();
+ mips_proc0_init();
+ mutex_init();
+ kdb_init();
+#ifdef KDB
+ if (boothowto & RB_KDB)
+ kdb_enter(KDB_WHY_BOOTFLAGS, "Boot flags requested debugger");
+#endif
+ cpu_clock = cvmx_sysinfo_get()->cpu_clock_hz;
+ platform_counter_freq = cpu_clock;
+ octeon_timecounter.tc_frequency = cpu_clock;
+ platform_timecounter = &octeon_timecounter;
+ mips_timer_init_params(platform_counter_freq, 0);
+ set_cputicker(octeon_get_ticks, cpu_clock, 0);
+
+#ifdef SMP
+ /*
+ * Clear any pending IPIs.
+ */
+ cvmx_write_csr(CVMX_CIU_MBOX_CLRX(0), 0xffffffff);
+#endif
+
+ printf("Octeon SDK: %s\n", OCTEON_SDK_VERSION_STRING);
+ printf("Available Octeon features:");
+ for (ofd = octeon_feature_descriptions; ofd->ofd_string != NULL; ofd++)
+ if (octeon_has_feature(ofd->ofd_feature))
+ printf(" %s", ofd->ofd_string);
+ printf("\n");
+}
+
+static uint64_t
+octeon_get_ticks(void)
+{
+ uint64_t cvmcount;
+
+ CVMX_MF_CYCLE(cvmcount);
+ return (cvmcount);
+}
+
+static unsigned
+octeon_get_timecount(struct timecounter *tc)
+{
+ return ((unsigned)octeon_get_ticks());
+}
+
+static int
+sysctl_machdep_led_display(SYSCTL_HANDLER_ARGS)
+{
+ size_t buflen;
+ char buf[9];
+ int error;
+
+ if (req->newptr == NULL)
+ return (EINVAL);
+
+ if (cvmx_sysinfo_get()->led_display_base_addr == 0)
+ return (ENODEV);
+
+ /*
+ * Revision 1.x of the EBT3000 only supports 4 characters, but
+ * other devices support 8.
+ */
+ if (cvmx_sysinfo_get()->board_type == CVMX_BOARD_TYPE_EBT3000 &&
+ cvmx_sysinfo_get()->board_rev_major == 1)
+ buflen = 4;
+ else
+ buflen = 8;
+
+ if (req->newlen > buflen)
+ return (E2BIG);
+
+ error = SYSCTL_IN(req, buf, req->newlen);
+ if (error != 0)
+ return (error);
+
+ buf[req->newlen] = '\0';
+ ebt3000_str_write(buf);
+
+ return (0);
+}
+
+SYSCTL_PROC(_machdep, OID_AUTO, led_display, CTLTYPE_STRING | CTLFLAG_WR,
+ NULL, 0, sysctl_machdep_led_display, "A",
+ "String to display on LED display");
+
+void
+cvmx_dvprintf(const char *fmt, va_list ap)
+{
+ if (!bootverbose)
+ return;
+ vprintf(fmt, ap);
+}
+
+void
+cvmx_dprintf(const char *fmt, ...)
+{
+ va_list ap;
+
+ va_start(ap, fmt);
+ cvmx_dvprintf(fmt, ap);
+ va_end(ap);
+}
+
+/**
+ * version of printf that works better in exception context.
+ *
+ * @param format
+ *
+ * XXX If this function weren't in cvmx-interrupt.c, we'd use the SDK version.
+ */
+void cvmx_safe_printf(const char *format, ...)
+{
+ char buffer[256];
+ char *ptr = buffer;
+ int count;
+ va_list args;
+
+ va_start(args, format);
+#ifndef __U_BOOT__
+ count = vsnprintf(buffer, sizeof(buffer), format, args);
+#else
+ count = vsprintf(buffer, format, args);
+#endif
+ va_end(args);
+
+ while (count-- > 0)
+ {
+ cvmx_uart_lsr_t lsrval;
+
+ /* Spin until there is room */
+ do
+ {
+ lsrval.u64 = cvmx_read_csr(CVMX_MIO_UARTX_LSR(0));
+#if !defined(CONFIG_OCTEON_SIM_SPEED)
+ if (lsrval.s.temt == 0)
+ cvmx_wait(10000); /* Just to reduce the load on the system */
+#endif
+ }
+ while (lsrval.s.temt == 0);
+
+ if (*ptr == '\n')
+ cvmx_write_csr(CVMX_MIO_UARTX_THR(0), '\r');
+ cvmx_write_csr(CVMX_MIO_UARTX_THR(0), *ptr++);
+ }
+}
+
+/* impSTART: This stuff should move back into the Cavium SDK */
+/*
+ ****************************************************************************************
+ *
+ * APP/BOOT DESCRIPTOR STUFF
+ *
+ ****************************************************************************************
+ */
+
+/* Define the struct that is initialized by the bootloader used by the
+ * startup code.
+ *
+ * Copyright (c) 2004, 2005, 2006 Cavium Networks.
+ *
+ * The authors hereby grant permission to use, copy, modify, distribute,
+ * and license this software and its documentation for any purpose, provided
+ * that existing copyright notices are retained in all copies and that this
+ * notice is included verbatim in any distributions. No written agreement,
+ * license, or royalty fee is required for any of the authorized uses.
+ * Modifications to this software may be copyrighted by their authors
+ * and need not follow the licensing terms described here, provided that
+ * the new terms are clearly indicated on the first page of each file where
+ * they apply.
+ */
+
+#define OCTEON_CURRENT_DESC_VERSION 6
+#define OCTEON_ARGV_MAX_ARGS (64)
+#define OCTOEN_SERIAL_LEN 20
+
+typedef struct {
+ /* Start of block referenced by assembly code - do not change! */
+ uint32_t desc_version;
+ uint32_t desc_size;
+
+ uint64_t stack_top;
+ uint64_t heap_base;
+ uint64_t heap_end;
+ uint64_t entry_point; /* Only used by bootloader */
+ uint64_t desc_vaddr;
+ /* End of This block referenced by assembly code - do not change! */
+
+ uint32_t exception_base_addr;
+ uint32_t stack_size;
+ uint32_t heap_size;
+ uint32_t argc; /* Argc count for application */
+ uint32_t argv[OCTEON_ARGV_MAX_ARGS];
+ uint32_t flags;
+ uint32_t core_mask;
+ uint32_t dram_size; /**< DRAM size in megabyes */
+ uint32_t phy_mem_desc_addr; /**< physical address of free memory descriptor block*/
+ uint32_t debugger_flags_base_addr; /**< used to pass flags from app to debugger */
+ uint32_t eclock_hz; /**< CPU clock speed, in hz */
+ uint32_t dclock_hz; /**< DRAM clock speed, in hz */
+ uint32_t spi_clock_hz; /**< SPI4 clock in hz */
+ uint16_t board_type;
+ uint8_t board_rev_major;
+ uint8_t board_rev_minor;
+ uint16_t chip_type;
+ uint8_t chip_rev_major;
+ uint8_t chip_rev_minor;
+ char board_serial_number[OCTOEN_SERIAL_LEN];
+ uint8_t mac_addr_base[6];
+ uint8_t mac_addr_count;
+ uint64_t cvmx_desc_vaddr;
+} octeon_boot_descriptor_t;
+
+static cvmx_bootinfo_t *
+octeon_process_app_desc_ver_6(octeon_boot_descriptor_t *app_desc_ptr)
+{
+ cvmx_bootinfo_t *octeon_bootinfo;
+
+ /* XXX Why is 0x00000000ffffffffULL a bad value? */
+ if (app_desc_ptr->cvmx_desc_vaddr == 0 ||
+ app_desc_ptr->cvmx_desc_vaddr == 0xfffffffful) {
+ cvmx_safe_printf("Bad octeon_bootinfo %#jx\n",
+ (uintmax_t)app_desc_ptr->cvmx_desc_vaddr);
+ return (NULL);
+ }
+
+ octeon_bootinfo = cvmx_phys_to_ptr(app_desc_ptr->cvmx_desc_vaddr);
+ if (octeon_bootinfo->major_version != 1) {
+ cvmx_safe_printf("Incompatible CVMX descriptor from bootloader: %d.%d %p\n",
+ (int) octeon_bootinfo->major_version,
+ (int) octeon_bootinfo->minor_version, octeon_bootinfo);
+ return (NULL);
+ }
+
+ cvmx_sysinfo_minimal_initialize(octeon_bootinfo->phy_mem_desc_addr,
+ octeon_bootinfo->board_type,
+ octeon_bootinfo->board_rev_major,
+ octeon_bootinfo->board_rev_minor,
+ octeon_bootinfo->eclock_hz);
+ memcpy(cvmx_sysinfo_get()->mac_addr_base,
+ octeon_bootinfo->mac_addr_base, 6);
+ cvmx_sysinfo_get()->mac_addr_count = octeon_bootinfo->mac_addr_count;
+ cvmx_sysinfo_get()->compact_flash_common_base_addr =
+ octeon_bootinfo->compact_flash_common_base_addr;
+ cvmx_sysinfo_get()->compact_flash_attribute_base_addr =
+ octeon_bootinfo->compact_flash_attribute_base_addr;
+ cvmx_sysinfo_get()->core_mask = octeon_bootinfo->core_mask;
+ cvmx_sysinfo_get()->led_display_base_addr =
+ octeon_bootinfo->led_display_base_addr;
+ memcpy(cvmx_sysinfo_get()->board_serial_number,
+ octeon_bootinfo->board_serial_number,
+ sizeof cvmx_sysinfo_get()->board_serial_number);
+ return (octeon_bootinfo);
+}
+
+static void
+octeon_boot_params_init(register_t ptr)
+{
+ octeon_boot_descriptor_t *app_desc_ptr;
+ cvmx_bootinfo_t *octeon_bootinfo;
+
+ if (ptr == 0 || ptr >= MAX_APP_DESC_ADDR) {
+ cvmx_safe_printf("app descriptor passed at invalid address %#jx\n",
+ (uintmax_t)ptr);
+ platform_reset();
+ }
+
+ app_desc_ptr = (octeon_boot_descriptor_t *)(intptr_t)ptr;
+ if (app_desc_ptr->desc_version < 6) {
+ cvmx_safe_printf("Your boot code is too old to be supported.\n");
+ platform_reset();
+ }
+ octeon_bootinfo = octeon_process_app_desc_ver_6(app_desc_ptr);
+ if (octeon_bootinfo == NULL) {
+ cvmx_safe_printf("Could not parse boot descriptor.\n");
+ platform_reset();
+ }
+
+ if (cvmx_sysinfo_get()->led_display_base_addr != 0) {
+ /*
+ * Revision 1.x of the EBT3000 only supports 4 characters, but
+ * other devices support 8.
+ */
+ if (cvmx_sysinfo_get()->board_type == CVMX_BOARD_TYPE_EBT3000 &&
+ cvmx_sysinfo_get()->board_rev_major == 1)
+ ebt3000_str_write("FBSD");
+ else
+ ebt3000_str_write("FreeBSD!");
+ }
+
+ if (cvmx_sysinfo_get()->phy_mem_desc_addr == (uint64_t)0) {
+ cvmx_safe_printf("Your boot loader did not supply a memory descriptor.\n");
+ platform_reset();
+ }
+ cvmx_bootmem_init(cvmx_sysinfo_get()->phy_mem_desc_addr);
+
+ octeon_feature_init();
+
+ __cvmx_helper_cfg_init();
+}
+/* impEND: This stuff should move back into the Cavium SDK */
Property changes on: trunk/sys/mips/cavium/octeon_machdep.c
___________________________________________________________________
Added: svn:eol-style
## -0,0 +1 ##
+native
\ No newline at end of property
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## -0,0 +1 ##
+MidnightBSD=%H
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## -0,0 +1 ##
+text/plain
\ No newline at end of property
Added: trunk/sys/mips/cavium/octeon_mp.c
===================================================================
--- trunk/sys/mips/cavium/octeon_mp.c (rev 0)
+++ trunk/sys/mips/cavium/octeon_mp.c 2018-05-26 21:55:02 UTC (rev 9987)
@@ -0,0 +1,147 @@
+/* $MidnightBSD$ */
+/*-
+ * Copyright (c) 2004-2010 Juli Mallett <jmallett at FreeBSD.org>
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ * $FreeBSD: stable/10/sys/mips/cavium/octeon_mp.c 232812 2012-03-11 06:17:49Z jmallett $
+ */
+#include <sys/cdefs.h>
+__FBSDID("$FreeBSD: stable/10/sys/mips/cavium/octeon_mp.c 232812 2012-03-11 06:17:49Z jmallett $");
+
+#include <sys/param.h>
+#include <sys/conf.h>
+#include <sys/kernel.h>
+#include <sys/smp.h>
+#include <sys/systm.h>
+
+#include <machine/hwfunc.h>
+#include <machine/md_var.h>
+#include <machine/smp.h>
+
+#include <mips/cavium/octeon_pcmap_regs.h>
+
+#include <contrib/octeon-sdk/cvmx.h>
+#include <mips/cavium/octeon_irq.h>
+
+unsigned octeon_ap_boot = ~0;
+
+void
+platform_ipi_send(int cpuid)
+{
+ cvmx_write_csr(CVMX_CIU_MBOX_SETX(cpuid), 1);
+ mips_wbflush();
+}
+
+void
+platform_ipi_clear(void)
+{
+ uint64_t action;
+
+ action = cvmx_read_csr(CVMX_CIU_MBOX_CLRX(PCPU_GET(cpuid)));
+ KASSERT(action == 1, ("unexpected IPIs: %#jx", (uintmax_t)action));
+ cvmx_write_csr(CVMX_CIU_MBOX_CLRX(PCPU_GET(cpuid)), action);
+}
+
+int
+platform_ipi_intrnum(void)
+{
+ return (1);
+}
+
+void
+platform_init_ap(int cpuid)
+{
+ unsigned ciu_int_mask, clock_int_mask, ipi_int_mask;
+
+ /*
+ * Set the exception base.
+ */
+ mips_wr_ebase(0x80000000);
+
+ /*
+ * Clear any pending IPIs.
+ */
+ cvmx_write_csr(CVMX_CIU_MBOX_CLRX(cpuid), 0xffffffff);
+
+ /*
+ * Set up interrupts.
+ */
+ octeon_ciu_reset();
+
+ /*
+ * Unmask the clock, ipi and ciu interrupts.
+ */
+ ciu_int_mask = hard_int_mask(0);
+ clock_int_mask = hard_int_mask(5);
+ ipi_int_mask = hard_int_mask(platform_ipi_intrnum());
+ set_intr_mask(ciu_int_mask | clock_int_mask | ipi_int_mask);
+
+ mips_wbflush();
+}
+
+void
+platform_cpu_mask(cpuset_t *mask)
+{
+ uint64_t core_mask = cvmx_sysinfo_get()->core_mask;
+ uint64_t i, m;
+
+ CPU_ZERO(mask);
+ for (i = 0, m = 1 ; i < MAXCPU; i++, m <<= 1)
+ if (core_mask & m)
+ CPU_SET(i, mask);
+}
+
+struct cpu_group *
+platform_smp_topo(void)
+{
+ return (smp_topo_none());
+}
+
+int
+platform_start_ap(int cpuid)
+{
+ uint64_t cores_in_reset;
+
+ /*
+ * Release the core if it is in reset, and let it rev up a bit.
+ * The real synchronization happens below via octeon_ap_boot.
+ */
+ cores_in_reset = cvmx_read_csr(CVMX_CIU_PP_RST);
+ if (cores_in_reset & (1ULL << cpuid)) {
+ if (bootverbose)
+ printf ("AP #%d still in reset\n", cpuid);
+ cores_in_reset &= ~(1ULL << cpuid);
+ cvmx_write_csr(CVMX_CIU_PP_RST, (uint64_t)(cores_in_reset));
+ DELAY(2000); /* Give it a moment to start */
+ }
+
+ if (atomic_cmpset_32(&octeon_ap_boot, ~0, cpuid) == 0)
+ return (-1);
+ for (;;) {
+ DELAY(1000);
+ if (atomic_cmpset_32(&octeon_ap_boot, 0, ~0) != 0)
+ return (0);
+ printf("Waiting for cpu%d to start\n", cpuid);
+ }
+}
Property changes on: trunk/sys/mips/cavium/octeon_mp.c
___________________________________________________________________
Added: svn:eol-style
## -0,0 +1 ##
+native
\ No newline at end of property
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## -0,0 +1 ##
+MidnightBSD=%H
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+text/plain
\ No newline at end of property
Added: trunk/sys/mips/cavium/octeon_nmi.S
===================================================================
--- trunk/sys/mips/cavium/octeon_nmi.S (rev 0)
+++ trunk/sys/mips/cavium/octeon_nmi.S 2018-05-26 21:55:02 UTC (rev 9987)
@@ -0,0 +1,48 @@
+/* $MidnightBSD$ */
+/*-
+ * Copyright (c) 2010 Oleksandr Tymoshenko
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ * $FreeBSD: stable/10/sys/mips/cavium/octeon_nmi.S 215989 2010-11-28 08:11:05Z gonzo $
+ */
+
+#include <machine/asm.h>
+
+.set noreorder
+
+/*
+ * Only first 128 bytes of handler is used
+ */
+NESTED_NOPROFILE(octeon_wdog_nmi_handler, 32, ra)
+ .set push
+ .set noat
+ PTR_LA k0, _C_LABEL(octeon_wdog_nmi)
+ jr k0
+ nop
+1:
+ nop
+ j 1b
+ nop
+ .set at
+END(octeon_wdog_nmi_handler)
Property changes on: trunk/sys/mips/cavium/octeon_nmi.S
___________________________________________________________________
Added: svn:eol-style
## -0,0 +1 ##
+native
\ No newline at end of property
Added: svn:keywords
## -0,0 +1 ##
+MidnightBSD=%H
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+text/plain
\ No newline at end of property
Added: trunk/sys/mips/cavium/octeon_pci_console.c
===================================================================
--- trunk/sys/mips/cavium/octeon_pci_console.c (rev 0)
+++ trunk/sys/mips/cavium/octeon_pci_console.c 2018-05-26 21:55:02 UTC (rev 9987)
@@ -0,0 +1,237 @@
+/* $MidnightBSD$ */
+/*-
+ * Copyright (c) 2012 Juli Mallett <jmallett at FreeBSD.org>
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ * $FreeBSD: stable/10/sys/mips/cavium/octeon_pci_console.c 243255 2012-11-19 01:58:20Z jmallett $
+ */
+
+#include <sys/cdefs.h>
+__FBSDID("$FreeBSD: stable/10/sys/mips/cavium/octeon_pci_console.c 243255 2012-11-19 01:58:20Z jmallett $");
+
+#include <sys/param.h>
+#include <sys/systm.h>
+#include <sys/bus.h>
+#include <sys/conf.h>
+#include <sys/cons.h>
+#include <sys/kernel.h>
+#include <sys/reboot.h>
+
+#include <contrib/octeon-sdk/cvmx.h>
+#include <contrib/octeon-sdk/cvmx-bootmem.h>
+#include <contrib/octeon-sdk/cvmx-interrupt.h>
+#include <contrib/octeon-sdk/octeon-pci-console.h>
+
+#ifdef OCTEON_VENDOR_RADISYS
+#define OPCIC_FLAG_RSYS (0x00000001)
+
+#define OPCIC_RSYS_FIFO_SIZE (0x2000)
+#endif
+
+struct opcic_softc {
+ unsigned sc_flags;
+ uint64_t sc_base_addr;
+};
+
+static struct opcic_softc opcic_instance;
+
+static cn_probe_t opcic_cnprobe;
+static cn_init_t opcic_cninit;
+static cn_term_t opcic_cnterm;
+static cn_getc_t opcic_cngetc;
+static cn_putc_t opcic_cnputc;
+static cn_grab_t opcic_cngrab;
+static cn_ungrab_t opcic_cnungrab;
+
+#ifdef OCTEON_VENDOR_RADISYS
+static int opcic_rsys_cngetc(struct opcic_softc *);
+static void opcic_rsys_cnputc(struct opcic_softc *, int);
+#endif
+
+CONSOLE_DRIVER(opcic);
+
+static void
+opcic_cnprobe(struct consdev *cp)
+{
+ const struct cvmx_bootmem_named_block_desc *pci_console_block;
+ struct opcic_softc *sc;
+
+ sc = &opcic_instance;
+ sc->sc_flags = 0;
+ sc->sc_base_addr = 0;
+
+ cp->cn_pri = CN_DEAD;
+
+ switch (cvmx_sysinfo_get()->board_type) {
+#ifdef OCTEON_VENDOR_RADISYS
+ case CVMX_BOARD_TYPE_CUST_RADISYS_RSYS4GBE:
+ pci_console_block =
+ cvmx_bootmem_find_named_block("rsys_gbl_memory");
+ if (pci_console_block != NULL) {
+ sc->sc_flags |= OPCIC_FLAG_RSYS;
+ sc->sc_base_addr = pci_console_block->base_addr;
+ break;
+ }
+#endif
+ default:
+ pci_console_block =
+ cvmx_bootmem_find_named_block(OCTEON_PCI_CONSOLE_BLOCK_NAME);
+ if (pci_console_block == NULL)
+ return;
+ sc->sc_base_addr = pci_console_block->base_addr;
+ break;
+ }
+
+ cp->cn_arg = sc;
+ snprintf(cp->cn_name, sizeof cp->cn_name, "opcic@%p", cp->cn_arg);
+ cp->cn_pri = (boothowto & RB_SERIAL) ? CN_REMOTE : CN_NORMAL;
+}
+
+static void
+opcic_cninit(struct consdev *cp)
+{
+ (void)cp;
+}
+
+static void
+opcic_cnterm(struct consdev *cp)
+{
+ (void)cp;
+}
+
+static int
+opcic_cngetc(struct consdev *cp)
+{
+ struct opcic_softc *sc;
+ char ch;
+ int rv;
+
+ sc = cp->cn_arg;
+
+#ifdef OCTEON_VENDOR_RADISYS
+ if ((sc->sc_flags & OPCIC_FLAG_RSYS) != 0)
+ return (opcic_rsys_cngetc(sc));
+#endif
+
+ rv = octeon_pci_console_read(sc->sc_base_addr, 0, &ch, 1,
+ OCT_PCI_CON_FLAG_NONBLOCK);
+ if (rv != 1)
+ return (-1);
+ return (ch);
+}
+
+static void
+opcic_cnputc(struct consdev *cp, int c)
+{
+ struct opcic_softc *sc;
+ char ch;
+ int rv;
+
+ sc = cp->cn_arg;
+ ch = c;
+
+#ifdef OCTEON_VENDOR_RADISYS
+ if ((sc->sc_flags & OPCIC_FLAG_RSYS) != 0) {
+ opcic_rsys_cnputc(sc, c);
+ return;
+ }
+#endif
+
+ rv = octeon_pci_console_write(sc->sc_base_addr, 0, &ch, 1, 0);
+ if (rv == -1)
+ panic("%s: octeon_pci_console_write failed.", __func__);
+}
+
+static void
+opcic_cngrab(struct consdev *cp)
+{
+ (void)cp;
+}
+
+static void
+opcic_cnungrab(struct consdev *cp)
+{
+ (void)cp;
+}
+
+#ifdef OCTEON_VENDOR_RADISYS
+static int
+opcic_rsys_cngetc(struct opcic_softc *sc)
+{
+ uint64_t gbl_base;
+ uint64_t console_base;
+ uint64_t console_rbuf;
+ uint64_t console_rcnt[2];
+ uint16_t rcnt[2];
+ uint16_t roff;
+ int c;
+
+ gbl_base = CVMX_ADD_IO_SEG(sc->sc_base_addr);
+ console_base = gbl_base + 0x10;
+
+ console_rbuf = console_base + 0x2018;
+ console_rcnt[0] = console_base + 0x08;
+ console_rcnt[1] = console_base + 0x0a;
+
+ /* Check if there is anything new in the FIFO. */
+ rcnt[0] = cvmx_read64_uint16(console_rcnt[0]);
+ rcnt[1] = cvmx_read64_uint16(console_rcnt[1]);
+ if (rcnt[0] == rcnt[1])
+ return (-1);
+
+ /* Get first new character in the FIFO. */
+ if (rcnt[0] != 0)
+ roff = rcnt[0] - 1;
+ else
+ roff = OPCIC_RSYS_FIFO_SIZE - 1;
+ c = cvmx_read64_uint8(console_rbuf + roff);
+
+ /* Advance FIFO. */
+ rcnt[1] = (rcnt[1] + 1) % OPCIC_RSYS_FIFO_SIZE;
+ cvmx_write64_uint16(console_rcnt[1], rcnt[1]);
+
+ return (c);
+}
+
+static void
+opcic_rsys_cnputc(struct opcic_softc *sc, int c)
+{
+ uint64_t gbl_base;
+ uint64_t console_base;
+ uint64_t console_wbuf;
+ uint64_t console_wcnt;
+ uint16_t wcnt;
+
+ gbl_base = CVMX_ADD_IO_SEG(sc->sc_base_addr);
+ console_base = gbl_base + 0x10;
+
+ console_wbuf = console_base + 0x0018;
+ console_wcnt = console_base + 0x0c;
+
+ /* Append character to FIFO. */
+ wcnt = cvmx_read64_uint16(console_wcnt) % OPCIC_RSYS_FIFO_SIZE;
+ cvmx_write64_uint8(console_wbuf + wcnt, (uint8_t)c);
+ cvmx_write64_uint16(console_wcnt, wcnt + 1);
+}
+#endif
Property changes on: trunk/sys/mips/cavium/octeon_pci_console.c
___________________________________________________________________
Added: svn:eol-style
## -0,0 +1 ##
+native
\ No newline at end of property
Added: svn:keywords
## -0,0 +1 ##
+MidnightBSD=%H
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+text/plain
\ No newline at end of property
Added: trunk/sys/mips/cavium/octeon_pcmap_regs.h
===================================================================
--- trunk/sys/mips/cavium/octeon_pcmap_regs.h (rev 0)
+++ trunk/sys/mips/cavium/octeon_pcmap_regs.h 2018-05-26 21:55:02 UTC (rev 9987)
@@ -0,0 +1,60 @@
+/* $MidnightBSD$ */
+/***********************license start***************
+ * Copyright (c) 2003-2008 Cavium Networks (support at cavium.com). All rights
+ * reserved.
+ *
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
+ *
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ *
+ * * Redistributions in binary form must reproduce the above
+ * copyright notice, this list of conditions and the following
+ * disclaimer in the documentation and/or other materials provided
+ * with the distribution.
+ *
+ * * Neither the name of Cavium Networks nor the names of
+ * its contributors may be used to endorse or promote products
+ * derived from this software without specific prior written
+ * permission.
+ *
+ * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
+ * AND WITH ALL FAULTS AND CAVIUM NETWORKS MAKES NO PROMISES, REPRESENTATIONS
+ * OR WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH
+ * RESPECT TO THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY
+ * REPRESENTATION OR DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT
+ * DEFECTS, AND CAVIUM SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES
+ * OF TITLE, MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR
+ * PURPOSE, LACK OF VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET
+ * POSSESSION OR CORRESPONDENCE TO DESCRIPTION. THE ENTIRE RISK ARISING OUT
+ * OF USE OR PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
+ *
+ *
+ * For any questions regarding licensing please contact marketing at caviumnetworks.com
+ *
+ ***********************license end**************************************/
+
+/*
+ * This product includes software developed by the University of
+ * California, Berkeley and its contributors."
+ */
+
+/* $FreeBSD: stable/10/sys/mips/cavium/octeon_pcmap_regs.h 242346 2012-10-30 06:36:14Z jmallett $ */
+
+#ifndef __OCTEON_PCMAP_REGS_H__
+#define __OCTEON_PCMAP_REGS_H__
+
+#ifndef LOCORE
+/*
+ * octeon_machdep.c
+ *
+ * Direct to Board Support level.
+ */
+void octeon_debug_symbol(void);
+void octeon_ciu_reset(void);
+#endif /* LOCORE */
+
+#endif /* !OCTEON_PCMAP_REGS_H__ */
Property changes on: trunk/sys/mips/cavium/octeon_pcmap_regs.h
___________________________________________________________________
Added: svn:eol-style
## -0,0 +1 ##
+native
\ No newline at end of property
Added: svn:keywords
## -0,0 +1 ##
+MidnightBSD=%H
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+text/plain
\ No newline at end of property
Added: trunk/sys/mips/cavium/octeon_pmc.c
===================================================================
--- trunk/sys/mips/cavium/octeon_pmc.c (rev 0)
+++ trunk/sys/mips/cavium/octeon_pmc.c 2018-05-26 21:55:02 UTC (rev 9987)
@@ -0,0 +1,131 @@
+/* $MidnightBSD$ */
+/*-
+ * Copyright (c) 2012 Oleksandr Tymoshenko <gonzo at freebsd.org>
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ * $FreeBSD: stable/10/sys/mips/cavium/octeon_pmc.c 265999 2014-05-14 01:35:43Z ian $
+ */
+
+#include <sys/cdefs.h>
+__FBSDID("$FreeBSD: stable/10/sys/mips/cavium/octeon_pmc.c 265999 2014-05-14 01:35:43Z ian $");
+
+#include <sys/param.h>
+#include <sys/systm.h>
+#include <sys/bus.h>
+#include <sys/interrupt.h>
+#include <sys/kernel.h>
+#include <sys/module.h>
+#include <sys/rman.h>
+#include <sys/malloc.h>
+#include <sys/smp.h>
+#include <sys/pmc.h>
+#include <sys/pmckern.h>
+
+#include <machine/bus.h>
+#include <machine/intr_machdep.h>
+
+#include <contrib/octeon-sdk/cvmx.h>
+#include <mips/cavium/octeon_irq.h>
+
+struct octeon_pmc_softc {
+ struct rman irq_rman;
+ struct resource *octeon_pmc_irq;
+};
+
+static void octeon_pmc_identify(driver_t *, device_t);
+static int octeon_pmc_probe(device_t);
+static int octeon_pmc_attach(device_t);
+static int octeon_pmc_intr(void *);
+
+static void
+octeon_pmc_identify(driver_t *drv, device_t parent)
+{
+ if (octeon_has_feature(OCTEON_FEATURE_USB))
+ BUS_ADD_CHILD(parent, 0, "pmc", 0);
+}
+
+static int
+octeon_pmc_probe(device_t dev)
+{
+ if (device_get_unit(dev) != 0)
+ return (ENXIO);
+
+ device_set_desc(dev, "Cavium Octeon Performance Counters");
+ return (BUS_PROBE_NOWILDCARD);
+}
+
+static int
+octeon_pmc_attach(device_t dev)
+{
+ struct octeon_pmc_softc *sc;
+ int error;
+ int rid;
+
+ sc = device_get_softc(dev);
+
+ rid = 0;
+ sc->octeon_pmc_irq = bus_alloc_resource(dev,
+ SYS_RES_IRQ, &rid, OCTEON_PMC_IRQ,
+ OCTEON_PMC_IRQ, 1, RF_ACTIVE);
+
+ if (sc->octeon_pmc_irq == NULL) {
+ device_printf(dev, "could not allocate irq%d\n", OCTEON_PMC_IRQ);
+ return (ENXIO);
+ }
+
+ error = bus_setup_intr(dev, sc->octeon_pmc_irq,
+ INTR_TYPE_MISC, octeon_pmc_intr, NULL, sc, NULL);
+ if (error != 0) {
+ device_printf(dev, "bus_setup_intr failed: %d\n", error);
+ return (error);
+ }
+
+ return (0);
+}
+
+static int
+octeon_pmc_intr(void *arg)
+{
+ struct trapframe *tf = PCPU_GET(curthread)->td_intr_frame;
+
+ if (pmc_intr)
+ (*pmc_intr)(PCPU_GET(cpuid), tf);
+
+ return (FILTER_HANDLED);
+}
+
+static device_method_t octeon_pmc_methods[] = {
+ DEVMETHOD(device_identify, octeon_pmc_identify),
+ DEVMETHOD(device_probe, octeon_pmc_probe),
+ DEVMETHOD(device_attach, octeon_pmc_attach),
+ { 0, 0 }
+};
+
+static driver_t octeon_pmc_driver = {
+ "pmc",
+ octeon_pmc_methods,
+ sizeof(struct octeon_pmc_softc),
+};
+static devclass_t octeon_pmc_devclass;
+DRIVER_MODULE(octeon_pmc, nexus, octeon_pmc_driver, octeon_pmc_devclass, 0, 0);
Property changes on: trunk/sys/mips/cavium/octeon_pmc.c
___________________________________________________________________
Added: svn:eol-style
## -0,0 +1 ##
+native
\ No newline at end of property
Added: svn:keywords
## -0,0 +1 ##
+MidnightBSD=%H
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+text/plain
\ No newline at end of property
Added: trunk/sys/mips/cavium/octeon_rnd.c
===================================================================
--- trunk/sys/mips/cavium/octeon_rnd.c (rev 0)
+++ trunk/sys/mips/cavium/octeon_rnd.c 2018-05-26 21:55:02 UTC (rev 9987)
@@ -0,0 +1,133 @@
+/* $MidnightBSD$ */
+/*-
+ * Copyright (c) 2010 Juli Mallett <jmallett at FreeBSD.org>
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ * $FreeBSD: stable/10/sys/mips/cavium/octeon_rnd.c 314667 2017-03-04 13:03:31Z avg $
+ */
+
+#include <sys/cdefs.h>
+__FBSDID("$FreeBSD: stable/10/sys/mips/cavium/octeon_rnd.c 314667 2017-03-04 13:03:31Z avg $");
+
+#include <sys/param.h>
+#include <sys/systm.h>
+#include <sys/bus.h>
+#include <sys/clock.h>
+#include <sys/kernel.h>
+#include <sys/lock.h>
+#include <sys/module.h>
+#include <sys/random.h>
+
+#include <contrib/octeon-sdk/cvmx.h>
+#include <contrib/octeon-sdk/cvmx-rng.h>
+
+#define OCTEON_RND_WORDS 2
+
+struct octeon_rnd_softc {
+ uint64_t sc_entropy[OCTEON_RND_WORDS];
+ struct callout sc_callout;
+};
+
+static void octeon_rnd_identify(driver_t *drv, device_t parent);
+static int octeon_rnd_attach(device_t dev);
+static int octeon_rnd_probe(device_t dev);
+static int octeon_rnd_detach(device_t dev);
+
+static void octeon_rnd_harvest(void *);
+
+static device_method_t octeon_rnd_methods[] = {
+ /* Device interface */
+ DEVMETHOD(device_identify, octeon_rnd_identify),
+ DEVMETHOD(device_probe, octeon_rnd_probe),
+ DEVMETHOD(device_attach, octeon_rnd_attach),
+ DEVMETHOD(device_detach, octeon_rnd_detach),
+
+ { 0, 0 }
+};
+
+static driver_t octeon_rnd_driver = {
+ "rnd",
+ octeon_rnd_methods,
+ sizeof (struct octeon_rnd_softc)
+};
+static devclass_t octeon_rnd_devclass;
+DRIVER_MODULE(rnd, nexus, octeon_rnd_driver, octeon_rnd_devclass, 0, 0);
+
+static void
+octeon_rnd_identify(driver_t *drv, device_t parent)
+{
+ BUS_ADD_CHILD(parent, 0, "rnd", 0);
+}
+
+static int
+octeon_rnd_probe(device_t dev)
+{
+ if (device_get_unit(dev) != 0)
+ return (ENXIO);
+
+ device_set_desc(dev, "Cavium Octeon Random Number Generator");
+ return (BUS_PROBE_NOWILDCARD);
+}
+
+static int
+octeon_rnd_attach(device_t dev)
+{
+ struct octeon_rnd_softc *sc;
+
+ sc = device_get_softc(dev);
+ callout_init(&sc->sc_callout, 1);
+ callout_reset(&sc->sc_callout, hz * 5, octeon_rnd_harvest, sc);
+
+ cvmx_rng_enable();
+
+ return (0);
+}
+
+static int
+octeon_rnd_detach(device_t dev)
+{
+ struct octeon_rnd_softc *sc;
+
+ sc = device_get_softc(dev);
+
+ callout_stop(&sc->sc_callout);
+
+ return (0);
+}
+
+static void
+octeon_rnd_harvest(void *arg)
+{
+ struct octeon_rnd_softc *sc;
+ unsigned i;
+
+ sc = arg;
+
+ for (i = 0; i < OCTEON_RND_WORDS; i++)
+ sc->sc_entropy[i] = cvmx_rng_get_random64();
+ random_harvest(sc->sc_entropy, sizeof sc->sc_entropy,
+ (sizeof(sc->sc_entropy)*8)/2, RANDOM_PURE_OCTEON);
+
+ callout_reset(&sc->sc_callout, hz * 5, octeon_rnd_harvest, sc);
+}
Property changes on: trunk/sys/mips/cavium/octeon_rnd.c
___________________________________________________________________
Added: svn:eol-style
## -0,0 +1 ##
+native
\ No newline at end of property
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## -0,0 +1 ##
+MidnightBSD=%H
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Added: svn:mime-type
## -0,0 +1 ##
+text/plain
\ No newline at end of property
Added: trunk/sys/mips/cavium/octeon_rtc.c
===================================================================
--- trunk/sys/mips/cavium/octeon_rtc.c (rev 0)
+++ trunk/sys/mips/cavium/octeon_rtc.c 2018-05-26 21:55:02 UTC (rev 9987)
@@ -0,0 +1,131 @@
+/* $MidnightBSD$ */
+/*-
+ * Copyright (c) 2010 Juli Mallett <jmallett at FreeBSD.org>
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ * $FreeBSD: stable/10/sys/mips/cavium/octeon_rtc.c 265999 2014-05-14 01:35:43Z ian $
+ */
+
+#include <sys/cdefs.h>
+__FBSDID("$FreeBSD: stable/10/sys/mips/cavium/octeon_rtc.c 265999 2014-05-14 01:35:43Z ian $");
+
+#include <sys/param.h>
+#include <sys/systm.h>
+#include <sys/bus.h>
+#include <sys/clock.h>
+#include <sys/kernel.h>
+#include <sys/lock.h>
+#include <sys/module.h>
+
+#include <contrib/octeon-sdk/cvmx.h>
+#include <contrib/octeon-sdk/cvmx-rtc.h>
+
+#include "clock_if.h"
+
+static int octeon_rtc_attach(device_t dev);
+static int octeon_rtc_probe(device_t dev);
+
+static int octeon_rtc_settime(device_t dev, struct timespec *ts);
+static int octeon_rtc_gettime(device_t dev, struct timespec *ts);
+
+static device_method_t octeon_rtc_methods[] = {
+ /* Device interface */
+ DEVMETHOD(device_probe, octeon_rtc_probe),
+ DEVMETHOD(device_attach, octeon_rtc_attach),
+
+ /* clock interface */
+ DEVMETHOD(clock_gettime, octeon_rtc_gettime),
+ DEVMETHOD(clock_settime, octeon_rtc_settime),
+
+ { 0, 0 }
+};
+
+static driver_t octeon_rtc_driver = {
+ "rtc",
+ octeon_rtc_methods,
+ 0
+};
+static devclass_t octeon_rtc_devclass;
+DRIVER_MODULE(rtc, nexus, octeon_rtc_driver, octeon_rtc_devclass, 0, 0);
+
+static int
+octeon_rtc_probe(device_t dev)
+{
+ cvmx_rtc_options_t supported;
+
+ if (device_get_unit(dev) != 0)
+ return (ENXIO);
+
+ supported = cvmx_rtc_supported();
+ if (supported == 0)
+ return (ENXIO);
+
+ device_set_desc(dev, "Cavium Octeon Realtime Clock");
+ return (BUS_PROBE_NOWILDCARD);
+}
+
+static int
+octeon_rtc_attach(device_t dev)
+{
+ cvmx_rtc_options_t supported;
+
+ supported = cvmx_rtc_supported();
+ if ((supported & CVMX_RTC_READ) == 0)
+ return (ENXIO);
+
+ clock_register(dev, 1000000);
+ return (0);
+}
+
+static int
+octeon_rtc_settime(device_t dev, struct timespec *ts)
+{
+ cvmx_rtc_options_t supported;
+ uint32_t status;
+
+ supported = cvmx_rtc_supported();
+ if ((supported & CVMX_RTC_WRITE) == 0)
+ return (ENOTSUP);
+
+ status = cvmx_rtc_write(ts->tv_sec);
+ if (status != 0)
+ return (EINVAL);
+
+ return (0);
+}
+
+static int
+octeon_rtc_gettime(device_t dev, struct timespec *ts)
+{
+ uint32_t secs;
+
+ secs = cvmx_rtc_read();
+ if (secs == 0)
+ return (ENOTSUP);
+
+ ts->tv_sec = secs;
+ ts->tv_nsec = 0;
+
+ return (0);
+}
Property changes on: trunk/sys/mips/cavium/octeon_rtc.c
___________________________________________________________________
Added: svn:eol-style
## -0,0 +1 ##
+native
\ No newline at end of property
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## -0,0 +1 ##
+MidnightBSD=%H
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+text/plain
\ No newline at end of property
Added: trunk/sys/mips/cavium/octeon_wdog.c
===================================================================
--- trunk/sys/mips/cavium/octeon_wdog.c (rev 0)
+++ trunk/sys/mips/cavium/octeon_wdog.c 2018-05-26 21:55:02 UTC (rev 9987)
@@ -0,0 +1,276 @@
+/* $MidnightBSD$ */
+/*-
+ * Copyright (c) 2009, Oleksandr Tymoshenko <gonzo at FreeBSD.org>
+ * Copyright (c) 2010-2011, Juli Mallett <jmallett at FreeBSD.org>
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice unmodified, this list of conditions, and the following
+ * disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ */
+
+/*
+ * Watchdog driver for Cavium Octeon
+ */
+
+#include <sys/cdefs.h>
+__FBSDID("$FreeBSD: stable/10/sys/mips/cavium/octeon_wdog.c 232812 2012-03-11 06:17:49Z jmallett $");
+
+#include <sys/param.h>
+#include <sys/systm.h>
+#include <sys/watchdog.h>
+#include <sys/bus.h>
+#include <sys/kernel.h>
+#include <sys/module.h>
+#include <sys/sysctl.h>
+#include <sys/rman.h>
+#include <sys/smp.h>
+
+#include <contrib/octeon-sdk/cvmx.h>
+#include <mips/cavium/octeon_irq.h>
+
+#define DEFAULT_TIMER_VAL 65535
+
+struct octeon_wdog_softc {
+ device_t sc_dev;
+ struct octeon_wdog_core_softc {
+ int csc_core;
+ struct resource *csc_intr;
+ void *csc_intr_cookie;
+ } sc_cores[MAXCPU];
+ int sc_armed;
+ int sc_debug;
+};
+
+extern void octeon_wdog_nmi_handler(void);
+void octeon_wdog_nmi(void);
+
+static void octeon_watchdog_arm_core(int);
+static void octeon_watchdog_disarm_core(int);
+static int octeon_wdog_attach(device_t);
+static void octeon_wdog_identify(driver_t *, device_t);
+static int octeon_wdog_intr(void *);
+static int octeon_wdog_probe(device_t);
+static void octeon_wdog_setup(struct octeon_wdog_softc *, int);
+static void octeon_wdog_sysctl(device_t);
+static void octeon_wdog_watchdog_fn(void *, u_int, int *);
+
+void
+octeon_wdog_nmi(void)
+{
+ int core;
+
+ core = cvmx_get_core_num();
+
+ printf("cpu%u: NMI detected\n", core);
+ printf("cpu%u: Exception PC: %p\n", core, (void *)mips_rd_excpc());
+ printf("cpu%u: status %#x cause %#x\n", core, mips_rd_status(), mips_rd_cause());
+
+ /*
+ * This is the end
+ * Beautiful friend
+ *
+ * Just wait for Soft Reset to come and take us
+ */
+ for (;;)
+ continue;
+}
+
+static void
+octeon_watchdog_arm_core(int core)
+{
+ cvmx_ciu_wdogx_t ciu_wdog;
+
+ /* Poke it! */
+ cvmx_write_csr(CVMX_CIU_PP_POKEX(core), 1);
+
+ /*
+ * XXX
+ * Perhaps if KDB is enabled, we should use mode=2 and drop into the
+ * debugger on NMI?
+ *
+ * XXX
+ * Timer should be calculated based on CPU frquency
+ */
+ ciu_wdog.u64 = 0;
+ ciu_wdog.s.len = DEFAULT_TIMER_VAL;
+ ciu_wdog.s.mode = 3;
+ cvmx_write_csr(CVMX_CIU_WDOGX(core), ciu_wdog.u64);
+}
+
+static void
+octeon_watchdog_disarm_core(int core)
+{
+
+ cvmx_write_csr(CVMX_CIU_WDOGX(core), 0);
+}
+
+static void
+octeon_wdog_watchdog_fn(void *private, u_int cmd, int *error)
+{
+ struct octeon_wdog_softc *sc = private;
+ int core;
+
+ cmd &= WD_INTERVAL;
+ if (sc->sc_debug)
+ device_printf(sc->sc_dev, "%s: cmd: %x\n", __func__, cmd);
+ if (cmd > 0) {
+ CPU_FOREACH(core)
+ octeon_watchdog_arm_core(core);
+ sc->sc_armed = 1;
+ *error = 0;
+ } else {
+ if (sc->sc_armed) {
+ CPU_FOREACH(core)
+ octeon_watchdog_disarm_core(core);
+ sc->sc_armed = 0;
+ }
+ }
+}
+
+static void
+octeon_wdog_sysctl(device_t dev)
+{
+ struct octeon_wdog_softc *sc = device_get_softc(dev);
+
+ struct sysctl_ctx_list *ctx = device_get_sysctl_ctx(sc->sc_dev);
+ struct sysctl_oid *tree = device_get_sysctl_tree(sc->sc_dev);
+
+ SYSCTL_ADD_INT(ctx, SYSCTL_CHILDREN(tree), OID_AUTO,
+ "debug", CTLFLAG_RW, &sc->sc_debug, 0,
+ "enable watchdog debugging");
+ SYSCTL_ADD_INT(ctx, SYSCTL_CHILDREN(tree), OID_AUTO,
+ "armed", CTLFLAG_RD, &sc->sc_armed, 0,
+ "whether the watchdog is armed");
+}
+
+static void
+octeon_wdog_setup(struct octeon_wdog_softc *sc, int core)
+{
+ struct octeon_wdog_core_softc *csc;
+ int rid, error;
+
+ csc = &sc->sc_cores[core];
+
+ csc->csc_core = core;
+
+ /* Interrupt part */
+ rid = 0;
+ csc->csc_intr = bus_alloc_resource(sc->sc_dev, SYS_RES_IRQ, &rid,
+ OCTEON_IRQ_WDOG0 + core, OCTEON_IRQ_WDOG0 + core, 1, RF_ACTIVE);
+ if (csc->csc_intr == NULL)
+ panic("%s: bus_alloc_resource for core %u failed",
+ __func__, core);
+
+ error = bus_setup_intr(sc->sc_dev, csc->csc_intr, INTR_TYPE_MISC,
+ octeon_wdog_intr, NULL, csc, &csc->csc_intr_cookie);
+ if (error != 0)
+ panic("%s: bus_setup_intr for core %u: %d", __func__, core,
+ error);
+
+ bus_bind_intr(sc->sc_dev, csc->csc_intr, core);
+ bus_describe_intr(sc->sc_dev, csc->csc_intr, csc->csc_intr_cookie,
+ "cpu%u", core);
+
+ if (sc->sc_armed) {
+ /* Armed by default. */
+ octeon_watchdog_arm_core(core);
+ } else {
+ /* Disarmed by default. */
+ octeon_watchdog_disarm_core(core);
+ }
+}
+
+static int
+octeon_wdog_intr(void *arg)
+{
+ struct octeon_wdog_core_softc *csc = arg;
+
+ KASSERT(csc->csc_core == cvmx_get_core_num(),
+ ("got watchdog interrupt for core %u on core %u.",
+ csc->csc_core, cvmx_get_core_num()));
+
+ (void)csc;
+
+ /* Poke it! */
+ cvmx_write_csr(CVMX_CIU_PP_POKEX(cvmx_get_core_num()), 1);
+
+ return (FILTER_HANDLED);
+}
+
+static int
+octeon_wdog_probe(device_t dev)
+{
+
+ device_set_desc(dev, "Cavium Octeon watchdog timer");
+ return (0);
+}
+
+static int
+octeon_wdog_attach(device_t dev)
+{
+ struct octeon_wdog_softc *sc = device_get_softc(dev);
+ uint64_t *nmi_handler = (uint64_t*)octeon_wdog_nmi_handler;
+ int core, i;
+
+ /* Initialise */
+ sc->sc_armed = 0; /* XXX Ought to be a tunable / config option. */
+ sc->sc_debug = 0;
+
+ sc->sc_dev = dev;
+ EVENTHANDLER_REGISTER(watchdog_list, octeon_wdog_watchdog_fn, sc, 0);
+ octeon_wdog_sysctl(dev);
+
+ for (i = 0; i < 16; i++) {
+ cvmx_write_csr(CVMX_MIO_BOOT_LOC_ADR, i * 8);
+ cvmx_write_csr(CVMX_MIO_BOOT_LOC_DAT, nmi_handler[i]);
+ }
+
+ cvmx_write_csr(CVMX_MIO_BOOT_LOC_CFGX(0), 0x81fc0000);
+
+ CPU_FOREACH(core)
+ octeon_wdog_setup(sc, core);
+ return (0);
+}
+
+static void
+octeon_wdog_identify(driver_t *drv, device_t parent)
+{
+
+ BUS_ADD_CHILD(parent, 0, "owdog", 0);
+}
+
+static device_method_t octeon_wdog_methods[] = {
+ DEVMETHOD(device_identify, octeon_wdog_identify),
+
+ DEVMETHOD(device_probe, octeon_wdog_probe),
+ DEVMETHOD(device_attach, octeon_wdog_attach),
+ {0, 0},
+};
+
+static driver_t octeon_wdog_driver = {
+ "owdog",
+ octeon_wdog_methods,
+ sizeof(struct octeon_wdog_softc),
+};
+static devclass_t octeon_wdog_devclass;
+
+DRIVER_MODULE(owdog, ciu, octeon_wdog_driver, octeon_wdog_devclass, 0, 0);
Property changes on: trunk/sys/mips/cavium/octeon_wdog.c
___________________________________________________________________
Added: svn:eol-style
## -0,0 +1 ##
+native
\ No newline at end of property
Added: svn:keywords
## -0,0 +1 ##
+MidnightBSD=%H
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+text/plain
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Added: trunk/sys/mips/cavium/octopci.c
===================================================================
--- trunk/sys/mips/cavium/octopci.c (rev 0)
+++ trunk/sys/mips/cavium/octopci.c 2018-05-26 21:55:02 UTC (rev 9987)
@@ -0,0 +1,992 @@
+/* $MidnightBSD$ */
+/*-
+ * Copyright (c) 2010-2011 Juli Mallett <jmallett at FreeBSD.org>
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ * $FreeBSD: stable/10/sys/mips/cavium/octopci.c 242454 2012-11-01 20:39:39Z jmallett $
+ */
+
+#include <sys/cdefs.h>
+__FBSDID("$FreeBSD: stable/10/sys/mips/cavium/octopci.c 242454 2012-11-01 20:39:39Z jmallett $");
+
+#include <sys/param.h>
+#include <sys/systm.h>
+
+#include <sys/bus.h>
+#include <sys/endian.h>
+#include <sys/interrupt.h>
+#include <sys/malloc.h>
+#include <sys/kernel.h>
+#include <sys/module.h>
+#include <sys/rman.h>
+
+#include <vm/vm.h>
+#include <vm/pmap.h>
+#include <vm/vm_extern.h>
+
+#include <machine/bus.h>
+#include <machine/cpu.h>
+#include <machine/pmap.h>
+
+#include <contrib/octeon-sdk/cvmx.h>
+#include <mips/cavium/octeon_irq.h>
+#include <contrib/octeon-sdk/cvmx-pcie.h>
+
+#include <dev/pci/pcireg.h>
+#include <dev/pci/pcivar.h>
+
+#include <dev/pci/pcib_private.h>
+
+#include <mips/cavium/octopcireg.h>
+#include <mips/cavium/octopcivar.h>
+
+#include "pcib_if.h"
+
+#define NPI_WRITE(addr, value) cvmx_write64_uint32((addr) ^ 4, (value))
+#define NPI_READ(addr) cvmx_read64_uint32((addr) ^ 4)
+
+struct octopci_softc {
+ device_t sc_dev;
+
+ unsigned sc_domain;
+ unsigned sc_bus;
+
+ bus_addr_t sc_io_base;
+ unsigned sc_io_next;
+ struct rman sc_io;
+
+ bus_addr_t sc_mem1_base;
+ unsigned sc_mem1_next;
+ struct rman sc_mem1;
+};
+
+static void octopci_identify(driver_t *, device_t);
+static int octopci_probe(device_t);
+static int octopci_attach(device_t);
+static int octopci_read_ivar(device_t, device_t, int,
+ uintptr_t *);
+static struct resource *octopci_alloc_resource(device_t, device_t, int, int *,
+ u_long, u_long, u_long, u_int);
+static int octopci_activate_resource(device_t, device_t, int, int,
+ struct resource *);
+static int octopci_maxslots(device_t);
+static uint32_t octopci_read_config(device_t, u_int, u_int, u_int, u_int, int);
+static void octopci_write_config(device_t, u_int, u_int, u_int, u_int,
+ uint32_t, int);
+static int octopci_route_interrupt(device_t, device_t, int);
+
+static unsigned octopci_init_bar(device_t, unsigned, unsigned, unsigned, unsigned, uint8_t *);
+static unsigned octopci_init_device(device_t, unsigned, unsigned, unsigned, unsigned);
+static unsigned octopci_init_bus(device_t, unsigned);
+static void octopci_init_pci(device_t);
+static uint64_t octopci_cs_addr(unsigned, unsigned, unsigned, unsigned);
+
+static void
+octopci_identify(driver_t *drv, device_t parent)
+{
+ BUS_ADD_CHILD(parent, 0, "pcib", 0);
+ if (octeon_has_feature(OCTEON_FEATURE_PCIE))
+ BUS_ADD_CHILD(parent, 0, "pcib", 1);
+}
+
+static int
+octopci_probe(device_t dev)
+{
+ if (octeon_has_feature(OCTEON_FEATURE_PCIE)) {
+ device_set_desc(dev, "Cavium Octeon PCIe bridge");
+ return (0);
+ }
+
+ /* Check whether we are a PCI host. */
+ if ((cvmx_sysinfo_get()->bootloader_config_flags & CVMX_BOOTINFO_CFG_FLAG_PCI_HOST) == 0)
+ return (ENXIO);
+
+ if (device_get_unit(dev) != 0)
+ return (ENXIO);
+
+ device_set_desc(dev, "Cavium Octeon PCI bridge");
+ return (0);
+}
+
+static int
+octopci_attach(device_t dev)
+{
+ struct octopci_softc *sc;
+ unsigned subbus;
+ int error;
+
+ sc = device_get_softc(dev);
+ sc->sc_dev = dev;
+
+ if (octeon_has_feature(OCTEON_FEATURE_PCIE)) {
+ sc->sc_domain = device_get_unit(dev);
+
+ error = cvmx_pcie_rc_initialize(sc->sc_domain);
+ if (error != 0) {
+ device_printf(dev, "Failed to put PCIe bus in host mode.\n");
+ return (ENXIO);
+ }
+
+ /*
+ * In RC mode, the Simple Executive programs the first bus to
+ * be numbered as bus 1, because some IDT bridges used in
+ * Octeon systems object to being attached to bus 0.
+ */
+ sc->sc_bus = 1;
+
+ sc->sc_io_base = CVMX_ADD_IO_SEG(cvmx_pcie_get_io_base_address(sc->sc_domain));
+ sc->sc_io.rm_descr = "Cavium Octeon PCIe I/O Ports";
+
+ sc->sc_mem1_base = CVMX_ADD_IO_SEG(cvmx_pcie_get_mem_base_address(sc->sc_domain));
+ sc->sc_mem1.rm_descr = "Cavium Octeon PCIe Memory";
+ } else {
+ octopci_init_pci(dev);
+
+ sc->sc_domain = 0;
+ sc->sc_bus = 0;
+
+ sc->sc_io_base = CVMX_ADDR_DID(CVMX_FULL_DID(CVMX_OCT_DID_PCI, CVMX_OCT_SUBDID_PCI_IO));
+ sc->sc_io.rm_descr = "Cavium Octeon PCI I/O Ports";
+
+ sc->sc_mem1_base = CVMX_ADDR_DID(CVMX_FULL_DID(CVMX_OCT_DID_PCI, CVMX_OCT_SUBDID_PCI_MEM1));
+ sc->sc_mem1.rm_descr = "Cavium Octeon PCI Memory";
+ }
+
+ sc->sc_io.rm_type = RMAN_ARRAY;
+ error = rman_init(&sc->sc_io);
+ if (error != 0)
+ return (error);
+
+ error = rman_manage_region(&sc->sc_io, CVMX_OCT_PCI_IO_BASE,
+ CVMX_OCT_PCI_IO_BASE + CVMX_OCT_PCI_IO_SIZE);
+ if (error != 0)
+ return (error);
+
+ sc->sc_mem1.rm_type = RMAN_ARRAY;
+ error = rman_init(&sc->sc_mem1);
+ if (error != 0)
+ return (error);
+
+ error = rman_manage_region(&sc->sc_mem1, CVMX_OCT_PCI_MEM1_BASE,
+ CVMX_OCT_PCI_MEM1_BASE + CVMX_OCT_PCI_MEM1_SIZE);
+ if (error != 0)
+ return (error);
+
+ /*
+ * Next offsets for resource allocation in octopci_init_bar.
+ */
+ sc->sc_io_next = 0;
+ sc->sc_mem1_next = 0;
+
+ /*
+ * Configure devices.
+ */
+ octopci_write_config(dev, sc->sc_bus, 0, 0, PCIR_SUBBUS_1, 0xff, 1);
+ subbus = octopci_init_bus(dev, sc->sc_bus);
+ octopci_write_config(dev, sc->sc_bus, 0, 0, PCIR_SUBBUS_1, subbus, 1);
+
+ device_add_child(dev, "pci", device_get_unit(dev));
+
+ return (bus_generic_attach(dev));
+}
+
+static int
+octopci_read_ivar(device_t dev, device_t child, int which, uintptr_t *result)
+{
+ struct octopci_softc *sc;
+
+ sc = device_get_softc(dev);
+
+ switch (which) {
+ case PCIB_IVAR_DOMAIN:
+ *result = sc->sc_domain;
+ return (0);
+ case PCIB_IVAR_BUS:
+ *result = sc->sc_bus;
+ return (0);
+
+ }
+ return (ENOENT);
+}
+
+static struct resource *
+octopci_alloc_resource(device_t bus, device_t child, int type, int *rid,
+ u_long start, u_long end, u_long count, u_int flags)
+{
+ struct octopci_softc *sc;
+ struct resource *res;
+ struct rman *rm;
+ int error;
+
+ sc = device_get_softc(bus);
+
+ switch (type) {
+ case SYS_RES_IRQ:
+ res = bus_generic_alloc_resource(bus, child, type, rid, start,
+ end, count, flags);
+ if (res != NULL)
+ return (res);
+ return (NULL);
+ case SYS_RES_MEMORY:
+ rm = &sc->sc_mem1;
+ break;
+ case SYS_RES_IOPORT:
+ rm = &sc->sc_io;
+ break;
+ default:
+ return (NULL);
+ }
+
+ res = rman_reserve_resource(rm, start, end, count, flags, child);
+ if (res == NULL)
+ return (NULL);
+
+ rman_set_rid(res, *rid);
+ rman_set_bustag(res, octopci_bus_space);
+
+ switch (type) {
+ case SYS_RES_MEMORY:
+ rman_set_bushandle(res, sc->sc_mem1_base + rman_get_start(res));
+ break;
+ case SYS_RES_IOPORT:
+ rman_set_bushandle(res, sc->sc_io_base + rman_get_start(res));
+#if __mips_n64
+ rman_set_virtual(res, (void *)rman_get_bushandle(res));
+#else
+ /*
+ * XXX
+ * We can't access ports via a 32-bit pointer.
+ */
+ rman_set_virtual(res, NULL);
+#endif
+ break;
+ }
+
+ if ((flags & RF_ACTIVE) != 0) {
+ error = bus_activate_resource(child, type, *rid, res);
+ if (error != 0) {
+ rman_release_resource(res);
+ return (NULL);
+ }
+ }
+
+ return (res);
+}
+
+static int
+octopci_activate_resource(device_t bus, device_t child, int type, int rid,
+ struct resource *res)
+{
+ bus_space_handle_t bh;
+ int error;
+
+ switch (type) {
+ case SYS_RES_IRQ:
+ error = bus_generic_activate_resource(bus, child, type, rid,
+ res);
+ if (error != 0)
+ return (error);
+ return (0);
+ case SYS_RES_MEMORY:
+ case SYS_RES_IOPORT:
+ error = bus_space_map(rman_get_bustag(res),
+ rman_get_bushandle(res), rman_get_size(res), 0, &bh);
+ if (error != 0)
+ return (error);
+ rman_set_bushandle(res, bh);
+ break;
+ default:
+ return (ENXIO);
+ }
+
+ error = rman_activate_resource(res);
+ if (error != 0)
+ return (error);
+ return (0);
+}
+
+static int
+octopci_maxslots(device_t dev)
+{
+ return (PCI_SLOTMAX);
+}
+
+static uint32_t
+octopci_read_config(device_t dev, u_int bus, u_int slot, u_int func, u_int reg,
+ int bytes)
+{
+ struct octopci_softc *sc;
+ uint64_t addr;
+ uint32_t data;
+
+ sc = device_get_softc(dev);
+
+ if (octeon_has_feature(OCTEON_FEATURE_PCIE)) {
+ if (bus == 0 && slot == 0 && func == 0)
+ return ((uint32_t)-1);
+
+ switch (bytes) {
+ case 4:
+ return (cvmx_pcie_config_read32(sc->sc_domain, bus, slot, func, reg));
+ case 2:
+ return (cvmx_pcie_config_read16(sc->sc_domain, bus, slot, func, reg));
+ case 1:
+ return (cvmx_pcie_config_read8(sc->sc_domain, bus, slot, func, reg));
+ default:
+ return ((uint32_t)-1);
+ }
+ }
+
+ addr = octopci_cs_addr(bus, slot, func, reg);
+
+ switch (bytes) {
+ case 4:
+ data = le32toh(cvmx_read64_uint32(addr));
+ return (data);
+ case 2:
+ data = le16toh(cvmx_read64_uint16(addr));
+ return (data);
+ case 1:
+ data = cvmx_read64_uint8(addr);
+ return (data);
+ default:
+ return ((uint32_t)-1);
+ }
+}
+
+static void
+octopci_write_config(device_t dev, u_int bus, u_int slot, u_int func,
+ u_int reg, uint32_t data, int bytes)
+{
+ struct octopci_softc *sc;
+ uint64_t addr;
+
+ sc = device_get_softc(dev);
+
+ if (octeon_has_feature(OCTEON_FEATURE_PCIE)) {
+ switch (bytes) {
+ case 4:
+ cvmx_pcie_config_write32(sc->sc_domain, bus, slot, func, reg, data);
+ return;
+ case 2:
+ cvmx_pcie_config_write16(sc->sc_domain, bus, slot, func, reg, data);
+ return;
+ case 1:
+ cvmx_pcie_config_write8(sc->sc_domain, bus, slot, func, reg, data);
+ return;
+ default:
+ return;
+ }
+ }
+
+ addr = octopci_cs_addr(bus, slot, func, reg);
+
+ switch (bytes) {
+ case 4:
+ cvmx_write64_uint32(addr, htole32(data));
+ return;
+ case 2:
+ cvmx_write64_uint16(addr, htole16(data));
+ return;
+ case 1:
+ cvmx_write64_uint8(addr, data);
+ return;
+ default:
+ return;
+ }
+}
+
+static int
+octopci_route_interrupt(device_t dev, device_t child, int pin)
+{
+ struct octopci_softc *sc;
+ unsigned bus, slot, func;
+ unsigned irq;
+
+ sc = device_get_softc(dev);
+
+ if (octeon_has_feature(OCTEON_FEATURE_PCIE))
+ return (OCTEON_IRQ_PCI_INT0 + pin - 1);
+
+ bus = pci_get_bus(child);
+ slot = pci_get_slot(child);
+ func = pci_get_function(child);
+
+ /*
+ * Board types we have to know at compile-time.
+ */
+#if defined(OCTEON_BOARD_CAPK_0100ND)
+ if (bus == 0 && slot == 12 && func == 0)
+ return (OCTEON_IRQ_PCI_INT2);
+#endif
+
+ /*
+ * For board types we can determine at runtime.
+ */
+ switch (cvmx_sysinfo_get()->board_type) {
+#if defined(OCTEON_VENDOR_LANNER)
+ case CVMX_BOARD_TYPE_CUST_LANNER_MR955:
+ return (OCTEON_IRQ_PCI_INT0 + pin - 1);
+ case CVMX_BOARD_TYPE_CUST_LANNER_MR320:
+ if (slot < 32) {
+ if (slot == 3 || slot == 9)
+ irq = pin;
+ else
+ irq = pin - 1;
+ return (OCTEON_IRQ_PCI_INT0 + (irq & 3));
+ }
+ break;
+#endif
+ default:
+ break;
+ }
+
+ irq = slot + pin - 3;
+
+ return (OCTEON_IRQ_PCI_INT0 + (irq & 3));
+}
+
+static unsigned
+octopci_init_bar(device_t dev, unsigned b, unsigned s, unsigned f, unsigned barnum, uint8_t *commandp)
+{
+ struct octopci_softc *sc;
+ uint64_t bar;
+ unsigned size;
+ int barsize;
+
+ sc = device_get_softc(dev);
+
+ octopci_write_config(dev, b, s, f, PCIR_BAR(barnum), 0xffffffff, 4);
+ bar = octopci_read_config(dev, b, s, f, PCIR_BAR(barnum), 4);
+
+ if (bar == 0) {
+ /* Bar not implemented; got to next bar. */
+ return (barnum + 1);
+ }
+
+ if (PCI_BAR_IO(bar)) {
+ size = ~(bar & PCIM_BAR_IO_BASE) + 1;
+
+ sc->sc_io_next = (sc->sc_io_next + size - 1) & ~(size - 1);
+ if (sc->sc_io_next + size > CVMX_OCT_PCI_IO_SIZE) {
+ device_printf(dev, "%02x.%02x:%02x: no ports for BAR%u.\n",
+ b, s, f, barnum);
+ return (barnum + 1);
+ }
+ octopci_write_config(dev, b, s, f, PCIR_BAR(barnum),
+ CVMX_OCT_PCI_IO_BASE + sc->sc_io_next, 4);
+ sc->sc_io_next += size;
+
+ /*
+ * Enable I/O ports.
+ */
+ *commandp |= PCIM_CMD_PORTEN;
+
+ return (barnum + 1);
+ } else {
+ if (PCIR_BAR(barnum) == PCIR_BIOS) {
+ /*
+ * ROM BAR is always 32-bit.
+ */
+ barsize = 1;
+ } else {
+ switch (bar & PCIM_BAR_MEM_TYPE) {
+ case PCIM_BAR_MEM_64:
+ /*
+ * XXX
+ * High 32 bits are all zeroes for now.
+ */
+ octopci_write_config(dev, b, s, f, PCIR_BAR(barnum + 1), 0, 4);
+ barsize = 2;
+ break;
+ default:
+ barsize = 1;
+ break;
+ }
+ }
+
+ size = ~(bar & (uint32_t)PCIM_BAR_MEM_BASE) + 1;
+
+ sc->sc_mem1_next = (sc->sc_mem1_next + size - 1) & ~(size - 1);
+ if (sc->sc_mem1_next + size > CVMX_OCT_PCI_MEM1_SIZE) {
+ device_printf(dev, "%02x.%02x:%02x: no memory for BAR%u.\n",
+ b, s, f, barnum);
+ return (barnum + barsize);
+ }
+ octopci_write_config(dev, b, s, f, PCIR_BAR(barnum),
+ CVMX_OCT_PCI_MEM1_BASE + sc->sc_mem1_next, 4);
+ sc->sc_mem1_next += size;
+
+ /*
+ * Enable memory access.
+ */
+ *commandp |= PCIM_CMD_MEMEN;
+
+ return (barnum + barsize);
+ }
+}
+
+static unsigned
+octopci_init_device(device_t dev, unsigned b, unsigned s, unsigned f, unsigned secbus)
+{
+ unsigned barnum, bars;
+ uint8_t brctl;
+ uint8_t class, subclass;
+ uint8_t command;
+ uint8_t hdrtype;
+
+ /* Read header type (again.) */
+ hdrtype = octopci_read_config(dev, b, s, f, PCIR_HDRTYPE, 1);
+
+ /*
+ * Disable memory and I/O while programming BARs.
+ */
+ command = octopci_read_config(dev, b, s, f, PCIR_COMMAND, 1);
+ command &= ~(PCIM_CMD_MEMEN | PCIM_CMD_PORTEN);
+ octopci_write_config(dev, b, s, f, PCIR_COMMAND, command, 1);
+
+ DELAY(10000);
+
+ /* Program BARs. */
+ switch (hdrtype & PCIM_HDRTYPE) {
+ case PCIM_HDRTYPE_NORMAL:
+ bars = 6;
+ break;
+ case PCIM_HDRTYPE_BRIDGE:
+ bars = 2;
+ break;
+ case PCIM_HDRTYPE_CARDBUS:
+ bars = 0;
+ break;
+ default:
+ device_printf(dev, "%02x.%02x:%02x: invalid header type %#x\n",
+ b, s, f, hdrtype);
+ return (secbus);
+ }
+
+ barnum = 0;
+ while (barnum < bars)
+ barnum = octopci_init_bar(dev, b, s, f, barnum, &command);
+
+ /* Enable bus mastering. */
+ command |= PCIM_CMD_BUSMASTEREN;
+
+ /* Enable whatever facilities the BARs require. */
+ octopci_write_config(dev, b, s, f, PCIR_COMMAND, command, 1);
+
+ DELAY(10000);
+
+ /*
+ * Set cache line size. On Octeon it should be 128 bytes,
+ * but according to Linux some Intel bridges have trouble
+ * with values over 64 bytes, so use 64 bytes.
+ */
+ octopci_write_config(dev, b, s, f, PCIR_CACHELNSZ, 16, 1);
+
+ /* Set latency timer. */
+ octopci_write_config(dev, b, s, f, PCIR_LATTIMER, 48, 1);
+
+ /* Board-specific or device-specific fixups and workarounds. */
+ switch (cvmx_sysinfo_get()->board_type) {
+#if defined(OCTEON_VENDOR_LANNER)
+ case CVMX_BOARD_TYPE_CUST_LANNER_MR955:
+ if (b == 1 && s == 7 && f == 0) {
+ bus_addr_t busaddr, unitbusaddr;
+ uint32_t bar;
+ uint32_t tmp;
+ unsigned unit;
+
+ /*
+ * Set Tx DMA power.
+ */
+ bar = octopci_read_config(dev, b, s, f,
+ PCIR_BAR(3), 4);
+ busaddr = CVMX_ADDR_DID(CVMX_FULL_DID(CVMX_OCT_DID_PCI,
+ CVMX_OCT_SUBDID_PCI_MEM1));
+ busaddr += (bar & (uint32_t)PCIM_BAR_MEM_BASE);
+ for (unit = 0; unit < 4; unit++) {
+ unitbusaddr = busaddr + 0x430 + (unit << 8);
+ tmp = le32toh(cvmx_read64_uint32(unitbusaddr));
+ tmp &= ~0x700;
+ tmp |= 0x300;
+ cvmx_write64_uint32(unitbusaddr, htole32(tmp));
+ }
+ }
+ break;
+#endif
+ default:
+ break;
+ }
+
+ /* Configure PCI-PCI bridges. */
+ class = octopci_read_config(dev, b, s, f, PCIR_CLASS, 1);
+ if (class != PCIC_BRIDGE)
+ return (secbus);
+
+ subclass = octopci_read_config(dev, b, s, f, PCIR_SUBCLASS, 1);
+ if (subclass != PCIS_BRIDGE_PCI)
+ return (secbus);
+
+ /* Enable memory and I/O access. */
+ command |= PCIM_CMD_MEMEN | PCIM_CMD_PORTEN;
+ octopci_write_config(dev, b, s, f, PCIR_COMMAND, command, 1);
+
+ /* Enable errors and parity checking. Do a bus reset. */
+ brctl = octopci_read_config(dev, b, s, f, PCIR_BRIDGECTL_1, 1);
+ brctl |= PCIB_BCR_PERR_ENABLE | PCIB_BCR_SERR_ENABLE;
+
+ /* Perform a secondary bus reset. */
+ brctl |= PCIB_BCR_SECBUS_RESET;
+ octopci_write_config(dev, b, s, f, PCIR_BRIDGECTL_1, brctl, 1);
+ DELAY(100000);
+ brctl &= ~PCIB_BCR_SECBUS_RESET;
+ octopci_write_config(dev, b, s, f, PCIR_BRIDGECTL_1, brctl, 1);
+
+ secbus++;
+
+ /* Program memory and I/O ranges. */
+ octopci_write_config(dev, b, s, f, PCIR_MEMBASE_1,
+ CVMX_OCT_PCI_MEM1_BASE >> 16, 2);
+ octopci_write_config(dev, b, s, f, PCIR_MEMLIMIT_1,
+ (CVMX_OCT_PCI_MEM1_BASE + CVMX_OCT_PCI_MEM1_SIZE - 1) >> 16, 2);
+
+ octopci_write_config(dev, b, s, f, PCIR_IOBASEL_1,
+ CVMX_OCT_PCI_IO_BASE >> 8, 1);
+ octopci_write_config(dev, b, s, f, PCIR_IOBASEH_1,
+ CVMX_OCT_PCI_IO_BASE >> 16, 2);
+
+ octopci_write_config(dev, b, s, f, PCIR_IOLIMITL_1,
+ (CVMX_OCT_PCI_IO_BASE + CVMX_OCT_PCI_IO_SIZE - 1) >> 8, 1);
+ octopci_write_config(dev, b, s, f, PCIR_IOLIMITH_1,
+ (CVMX_OCT_PCI_IO_BASE + CVMX_OCT_PCI_IO_SIZE - 1) >> 16, 2);
+
+ /* Program prefetchable memory decoder. */
+ /* XXX */
+
+ /* Probe secondary/subordinate buses. */
+ octopci_write_config(dev, b, s, f, PCIR_PRIBUS_1, b, 1);
+ octopci_write_config(dev, b, s, f, PCIR_SECBUS_1, secbus, 1);
+ octopci_write_config(dev, b, s, f, PCIR_SUBBUS_1, 0xff, 1);
+
+ /* Perform a secondary bus reset. */
+ brctl |= PCIB_BCR_SECBUS_RESET;
+ octopci_write_config(dev, b, s, f, PCIR_BRIDGECTL_1, brctl, 1);
+ DELAY(100000);
+ brctl &= ~PCIB_BCR_SECBUS_RESET;
+ octopci_write_config(dev, b, s, f, PCIR_BRIDGECTL_1, brctl, 1);
+
+ /* Give the bus time to settle now before reading configspace. */
+ DELAY(100000);
+
+ secbus = octopci_init_bus(dev, secbus);
+
+ octopci_write_config(dev, b, s, f, PCIR_SUBBUS_1, secbus, 1);
+
+ return (secbus);
+}
+
+static unsigned
+octopci_init_bus(device_t dev, unsigned b)
+{
+ unsigned s, f;
+ uint8_t hdrtype;
+ unsigned secbus;
+
+ secbus = b;
+
+ for (s = 0; s <= PCI_SLOTMAX; s++) {
+ for (f = 0; f <= PCI_FUNCMAX; f++) {
+ hdrtype = octopci_read_config(dev, b, s, f, PCIR_HDRTYPE, 1);
+
+ if (hdrtype == 0xff) {
+ if (f == 0)
+ break; /* Next slot. */
+ continue; /* Next function. */
+ }
+
+ secbus = octopci_init_device(dev, b, s, f, secbus);
+
+ if (f == 0 && (hdrtype & PCIM_MFDEV) == 0)
+ break; /* Next slot. */
+ }
+ }
+
+ return (secbus);
+}
+
+static uint64_t
+octopci_cs_addr(unsigned bus, unsigned slot, unsigned func, unsigned reg)
+{
+ octeon_pci_config_space_address_t pci_addr;
+
+ pci_addr.u64 = 0;
+ pci_addr.s.upper = 2;
+ pci_addr.s.io = 1;
+ pci_addr.s.did = 3;
+ pci_addr.s.subdid = CVMX_OCT_SUBDID_PCI_CFG;
+ pci_addr.s.endian_swap = 1;
+ pci_addr.s.bus = bus;
+ pci_addr.s.dev = slot;
+ pci_addr.s.func = func;
+ pci_addr.s.reg = reg;
+
+ return (pci_addr.u64);
+}
+
+static void
+octopci_init_pci(device_t dev)
+{
+ cvmx_npi_mem_access_subid_t npi_mem_access_subid;
+ cvmx_npi_pci_int_arb_cfg_t npi_pci_int_arb_cfg;
+ cvmx_npi_ctl_status_t npi_ctl_status;
+ cvmx_pci_ctl_status_2_t pci_ctl_status_2;
+ cvmx_pci_cfg56_t pci_cfg56;
+ cvmx_pci_cfg22_t pci_cfg22;
+ cvmx_pci_cfg16_t pci_cfg16;
+ cvmx_pci_cfg19_t pci_cfg19;
+ cvmx_pci_cfg01_t pci_cfg01;
+ unsigned i;
+
+ /*
+ * Reset the PCI bus.
+ */
+ cvmx_write_csr(CVMX_CIU_SOFT_PRST, 0x1);
+ cvmx_read_csr(CVMX_CIU_SOFT_PRST);
+
+ DELAY(2000);
+
+ npi_ctl_status.u64 = 0;
+ npi_ctl_status.s.max_word = 1;
+ npi_ctl_status.s.timer = 1;
+ cvmx_write_csr(CVMX_NPI_CTL_STATUS, npi_ctl_status.u64);
+
+ /*
+ * Set host mode.
+ */
+ switch (cvmx_sysinfo_get()->board_type) {
+#if defined(OCTEON_VENDOR_LANNER)
+ case CVMX_BOARD_TYPE_CUST_LANNER_MR320:
+ case CVMX_BOARD_TYPE_CUST_LANNER_MR955:
+ /* 32-bit PCI-X */
+ cvmx_write_csr(CVMX_CIU_SOFT_PRST, 0x0);
+ break;
+#endif
+ default:
+ /* 64-bit PCI-X */
+ cvmx_write_csr(CVMX_CIU_SOFT_PRST, 0x4);
+ break;
+ }
+ cvmx_read_csr(CVMX_CIU_SOFT_PRST);
+
+ DELAY(2000);
+
+ /*
+ * Enable BARs and configure big BAR mode.
+ */
+ pci_ctl_status_2.u32 = 0;
+ pci_ctl_status_2.s.bb1_hole = 5; /* 256MB hole in BAR1 */
+ pci_ctl_status_2.s.bb1_siz = 1; /* BAR1 is 2GB */
+ pci_ctl_status_2.s.bb_ca = 1; /* Bypass cache for big BAR */
+ pci_ctl_status_2.s.bb_es = 1; /* Do big BAR byte-swapping */
+ pci_ctl_status_2.s.bb1 = 1; /* BAR1 is big */
+ pci_ctl_status_2.s.bb0 = 1; /* BAR0 is big */
+ pci_ctl_status_2.s.bar2pres = 1; /* BAR2 present */
+ pci_ctl_status_2.s.pmo_amod = 1; /* Round-robin priority */
+ pci_ctl_status_2.s.tsr_hwm = 1;
+ pci_ctl_status_2.s.bar2_enb = 1; /* Enable BAR2 */
+ pci_ctl_status_2.s.bar2_esx = 1; /* Do BAR2 byte-swapping */
+ pci_ctl_status_2.s.bar2_cax = 1; /* Bypass cache for BAR2 */
+
+ NPI_WRITE(CVMX_NPI_PCI_CTL_STATUS_2, pci_ctl_status_2.u32);
+
+ DELAY(2000);
+
+ pci_ctl_status_2.u32 = NPI_READ(CVMX_NPI_PCI_CTL_STATUS_2);
+
+ device_printf(dev, "%u-bit PCI%s bus.\n",
+ pci_ctl_status_2.s.ap_64ad ? 64 : 32,
+ pci_ctl_status_2.s.ap_pcix ? "-X" : "");
+
+ /*
+ * Set up transaction splitting, etc., parameters.
+ */
+ pci_cfg19.u32 = 0;
+ pci_cfg19.s.mrbcm = 1;
+ if (pci_ctl_status_2.s.ap_pcix) {
+ pci_cfg19.s.mdrrmc = 0;
+ pci_cfg19.s.tdomc = 4;
+ } else {
+ pci_cfg19.s.mdrrmc = 2;
+ pci_cfg19.s.tdomc = 1;
+ }
+ NPI_WRITE(CVMX_NPI_PCI_CFG19, pci_cfg19.u32);
+ NPI_READ(CVMX_NPI_PCI_CFG19);
+
+ /*
+ * Set up PCI error handling and memory access.
+ */
+ pci_cfg01.u32 = 0;
+ pci_cfg01.s.fbbe = 1;
+ pci_cfg01.s.see = 1;
+ pci_cfg01.s.pee = 1;
+ pci_cfg01.s.me = 1;
+ pci_cfg01.s.msae = 1;
+ if (pci_ctl_status_2.s.ap_pcix) {
+ pci_cfg01.s.fbb = 0;
+ } else {
+ pci_cfg01.s.fbb = 1;
+ }
+ NPI_WRITE(CVMX_NPI_PCI_CFG01, pci_cfg01.u32);
+ NPI_READ(CVMX_NPI_PCI_CFG01);
+
+ /*
+ * Enable the Octeon bus arbiter.
+ */
+ npi_pci_int_arb_cfg.u64 = 0;
+ npi_pci_int_arb_cfg.s.en = 1;
+ cvmx_write_csr(CVMX_NPI_PCI_INT_ARB_CFG, npi_pci_int_arb_cfg.u64);
+
+ /*
+ * Disable master latency timer.
+ */
+ pci_cfg16.u32 = 0;
+ pci_cfg16.s.mltd = 1;
+ NPI_WRITE(CVMX_NPI_PCI_CFG16, pci_cfg16.u32);
+ NPI_READ(CVMX_NPI_PCI_CFG16);
+
+ /*
+ * Configure master arbiter.
+ */
+ pci_cfg22.u32 = 0;
+ pci_cfg22.s.flush = 1;
+ pci_cfg22.s.mrv = 255;
+ NPI_WRITE(CVMX_NPI_PCI_CFG22, pci_cfg22.u32);
+ NPI_READ(CVMX_NPI_PCI_CFG22);
+
+ /*
+ * Set up PCI-X capabilities.
+ */
+ if (pci_ctl_status_2.s.ap_pcix) {
+ pci_cfg56.u32 = 0;
+ pci_cfg56.s.most = 3;
+ pci_cfg56.s.roe = 1; /* Enable relaxed ordering */
+ pci_cfg56.s.dpere = 1;
+ pci_cfg56.s.ncp = 0xe8;
+ pci_cfg56.s.pxcid = 7;
+ NPI_WRITE(CVMX_NPI_PCI_CFG56, pci_cfg56.u32);
+ NPI_READ(CVMX_NPI_PCI_CFG56);
+ }
+
+ NPI_WRITE(CVMX_NPI_PCI_READ_CMD_6, 0x22);
+ NPI_READ(CVMX_NPI_PCI_READ_CMD_6);
+ NPI_WRITE(CVMX_NPI_PCI_READ_CMD_C, 0x33);
+ NPI_READ(CVMX_NPI_PCI_READ_CMD_C);
+ NPI_WRITE(CVMX_NPI_PCI_READ_CMD_E, 0x33);
+ NPI_READ(CVMX_NPI_PCI_READ_CMD_E);
+
+ /*
+ * Configure MEM1 sub-DID access.
+ */
+ npi_mem_access_subid.u64 = 0;
+ npi_mem_access_subid.s.esr = 1; /* Byte-swap on read */
+ npi_mem_access_subid.s.esw = 1; /* Byte-swap on write */
+ switch (cvmx_sysinfo_get()->board_type) {
+#if defined(OCTEON_VENDOR_LANNER)
+ case CVMX_BOARD_TYPE_CUST_LANNER_MR955:
+ npi_mem_access_subid.s.shortl = 1;
+ break;
+#endif
+ default:
+ break;
+ }
+ cvmx_write_csr(CVMX_NPI_MEM_ACCESS_SUBID3, npi_mem_access_subid.u64);
+
+ /*
+ * Configure BAR2. Linux says this has to come first.
+ */
+ NPI_WRITE(CVMX_NPI_PCI_CFG08, 0x00000000);
+ NPI_READ(CVMX_NPI_PCI_CFG08);
+ NPI_WRITE(CVMX_NPI_PCI_CFG09, 0x00000080);
+ NPI_READ(CVMX_NPI_PCI_CFG09);
+
+ /*
+ * Disable BAR1 IndexX.
+ */
+ for (i = 0; i < 32; i++) {
+ NPI_WRITE(CVMX_NPI_PCI_BAR1_INDEXX(i), 0);
+ NPI_READ(CVMX_NPI_PCI_BAR1_INDEXX(i));
+ }
+
+ /*
+ * Configure BAR0 and BAR1.
+ */
+ NPI_WRITE(CVMX_NPI_PCI_CFG04, 0x00000000);
+ NPI_READ(CVMX_NPI_PCI_CFG04);
+ NPI_WRITE(CVMX_NPI_PCI_CFG05, 0x00000000);
+ NPI_READ(CVMX_NPI_PCI_CFG05);
+
+ NPI_WRITE(CVMX_NPI_PCI_CFG06, 0x80000000);
+ NPI_READ(CVMX_NPI_PCI_CFG06);
+ NPI_WRITE(CVMX_NPI_PCI_CFG07, 0x00000000);
+ NPI_READ(CVMX_NPI_PCI_CFG07);
+
+ /*
+ * Clear PCI interrupts.
+ */
+ cvmx_write_csr(CVMX_NPI_PCI_INT_SUM2, 0xffffffffffffffffull);
+}
+
+static device_method_t octopci_methods[] = {
+ /* Device interface */
+ DEVMETHOD(device_identify, octopci_identify),
+ DEVMETHOD(device_probe, octopci_probe),
+ DEVMETHOD(device_attach, octopci_attach),
+
+ /* Bus interface */
+ DEVMETHOD(bus_read_ivar, octopci_read_ivar),
+ DEVMETHOD(bus_alloc_resource, octopci_alloc_resource),
+ DEVMETHOD(bus_release_resource, bus_generic_release_resource),
+ DEVMETHOD(bus_activate_resource,octopci_activate_resource),
+ DEVMETHOD(bus_deactivate_resource,bus_generic_deactivate_resource),
+ DEVMETHOD(bus_setup_intr, bus_generic_setup_intr),
+ DEVMETHOD(bus_teardown_intr, bus_generic_teardown_intr),
+
+ DEVMETHOD(bus_add_child, bus_generic_add_child),
+
+ /* pcib interface */
+ DEVMETHOD(pcib_maxslots, octopci_maxslots),
+ DEVMETHOD(pcib_read_config, octopci_read_config),
+ DEVMETHOD(pcib_write_config, octopci_write_config),
+ DEVMETHOD(pcib_route_interrupt, octopci_route_interrupt),
+
+ DEVMETHOD_END
+};
+
+static driver_t octopci_driver = {
+ "pcib",
+ octopci_methods,
+ sizeof(struct octopci_softc),
+};
+static devclass_t octopci_devclass;
+DRIVER_MODULE(octopci, ciu, octopci_driver, octopci_devclass, 0, 0);
Property changes on: trunk/sys/mips/cavium/octopci.c
___________________________________________________________________
Added: svn:eol-style
## -0,0 +1 ##
+native
\ No newline at end of property
Added: svn:keywords
## -0,0 +1 ##
+MidnightBSD=%H
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+text/plain
\ No newline at end of property
Added: trunk/sys/mips/cavium/octopci_bus_space.c
===================================================================
--- trunk/sys/mips/cavium/octopci_bus_space.c (rev 0)
+++ trunk/sys/mips/cavium/octopci_bus_space.c 2018-05-26 21:55:02 UTC (rev 9987)
@@ -0,0 +1,576 @@
+/* $MidnightBSD$ */
+/* $NetBSD: bus.h,v 1.12 1997/10/01 08:25:15 fvdl Exp $ */
+/*-
+ * $Id: bus.h,v 1.6 2007/08/09 11:23:32 katta Exp $
+ *
+ * Copyright (c) 1996, 1997 The NetBSD Foundation, Inc.
+ * All rights reserved.
+ *
+ * This code is derived from software contributed to The NetBSD Foundation
+ * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility,
+ * NASA Ames Research Center.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
+ * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/*
+ * Copyright (c) 1996 Charles M. Hannum. All rights reserved.
+ * Copyright (c) 1996 Christopher G. Demetriou. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * 3. All advertising materials mentioning features or use of this software
+ * must display the following acknowledgement:
+ * This product includes software developed by Christopher G. Demetriou
+ * for the NetBSD Project.
+ * 4. The name of the author may not be used to endorse or promote products
+ * derived from this software without specific prior written permission
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+ * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+ * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * from: src/sys/alpha/include/bus.h,v 1.5 1999/08/28 00:38:40 peter
+ * $FreeBSD: stable/10/sys/mips/cavium/octopci_bus_space.c 263687 2014-03-24 13:48:04Z emaste $
+ */
+#include <sys/cdefs.h>
+__FBSDID("$FreeBSD: stable/10/sys/mips/cavium/octopci_bus_space.c 263687 2014-03-24 13:48:04Z emaste $");
+
+#include <sys/param.h>
+#include <sys/systm.h>
+#include <sys/bus.h>
+#include <sys/kernel.h>
+#include <sys/malloc.h>
+#include <sys/ktr.h>
+#include <sys/endian.h>
+
+#include <vm/vm.h>
+#include <vm/pmap.h>
+#include <vm/vm_kern.h>
+#include <vm/vm_extern.h>
+
+#include <machine/bus.h>
+#include <machine/cache.h>
+
+#include <mips/cavium/octopcivar.h>
+
+#include <contrib/octeon-sdk/cvmx.h>
+
+static struct bus_space octopci_space = {
+ /* cookie */
+ (void *) 0,
+
+ /* mapping/unmapping */
+ octopci_bs_map,
+ octopci_bs_unmap,
+ octopci_bs_subregion,
+
+ /* allocation/deallocation */
+ NULL,
+ NULL,
+
+ /* barrier */
+ octopci_bs_barrier,
+
+ /* read (single) */
+ octopci_bs_r_1,
+ octopci_bs_r_2,
+ octopci_bs_r_4,
+ NULL,
+
+ /* read multiple */
+ octopci_bs_rm_1,
+ octopci_bs_rm_2,
+ octopci_bs_rm_4,
+ NULL,
+
+ /* read region */
+ octopci_bs_rr_1,
+ octopci_bs_rr_2,
+ octopci_bs_rr_4,
+ NULL,
+
+ /* write (single) */
+ octopci_bs_w_1,
+ octopci_bs_w_2,
+ octopci_bs_w_4,
+ NULL,
+
+ /* write multiple */
+ octopci_bs_wm_1,
+ octopci_bs_wm_2,
+ octopci_bs_wm_4,
+ NULL,
+
+ /* write region */
+ NULL,
+ octopci_bs_wr_2,
+ octopci_bs_wr_4,
+ NULL,
+
+ /* set multiple */
+ NULL,
+ NULL,
+ NULL,
+ NULL,
+
+ /* set region */
+ NULL,
+ octopci_bs_sr_2,
+ octopci_bs_sr_4,
+ NULL,
+
+ /* copy */
+ NULL,
+ octopci_bs_c_2,
+ NULL,
+ NULL,
+
+ /* read (single) stream */
+ octopci_bs_r_1,
+ octopci_bs_r_2,
+ octopci_bs_r_4,
+ NULL,
+
+ /* read multiple stream */
+ octopci_bs_rm_1,
+ octopci_bs_rm_2,
+ octopci_bs_rm_4,
+ NULL,
+
+ /* read region stream */
+ octopci_bs_rr_1,
+ octopci_bs_rr_2,
+ octopci_bs_rr_4,
+ NULL,
+
+ /* write (single) stream */
+ octopci_bs_w_1,
+ octopci_bs_w_2,
+ octopci_bs_w_4,
+ NULL,
+
+ /* write multiple stream */
+ octopci_bs_wm_1,
+ octopci_bs_wm_2,
+ octopci_bs_wm_4,
+ NULL,
+
+ /* write region stream */
+ NULL,
+ octopci_bs_wr_2,
+ octopci_bs_wr_4,
+ NULL,
+};
+
+#define rd8(a) cvmx_read64_uint8(a)
+#define rd16(a) le16toh(cvmx_read64_uint16(a))
+#define rd32(a) le32toh(cvmx_read64_uint32(a))
+#define wr8(a, v) cvmx_write64_uint8(a, v)
+#define wr16(a, v) cvmx_write64_uint16(a, htole16(v))
+#define wr32(a, v) cvmx_write64_uint32(a, htole32(v))
+
+/* octopci bus_space tag */
+bus_space_tag_t octopci_bus_space = &octopci_space;
+
+int
+octopci_bs_map(void *t __unused, bus_addr_t addr,
+ bus_size_t size __unused, int flags __unused,
+ bus_space_handle_t *bshp)
+{
+
+ *bshp = addr;
+ return (0);
+}
+
+void
+octopci_bs_unmap(void *t __unused, bus_space_handle_t bh __unused,
+ bus_size_t size __unused)
+{
+
+ /* Do nothing */
+}
+
+int
+octopci_bs_subregion(void *t __unused, bus_space_handle_t handle,
+ bus_size_t offset, bus_size_t size __unused,
+ bus_space_handle_t *bshp)
+{
+
+ *bshp = handle + offset;
+ return (0);
+}
+
+uint8_t
+octopci_bs_r_1(void *t, bus_space_handle_t handle,
+ bus_size_t offset)
+{
+
+ return (rd8(handle + offset));
+}
+
+uint16_t
+octopci_bs_r_2(void *t, bus_space_handle_t handle,
+ bus_size_t offset)
+{
+
+ return (rd16(handle + offset));
+}
+
+uint32_t
+octopci_bs_r_4(void *t, bus_space_handle_t handle,
+ bus_size_t offset)
+{
+
+ return (rd32(handle + offset));
+}
+
+
+void
+octopci_bs_rm_1(void *t, bus_space_handle_t bsh,
+ bus_size_t offset, uint8_t *addr, size_t count)
+{
+
+ while (count--)
+ *addr++ = rd8(bsh + offset);
+}
+
+void
+octopci_bs_rm_2(void *t, bus_space_handle_t bsh,
+ bus_size_t offset, uint16_t *addr, size_t count)
+{
+ bus_addr_t baddr = bsh + offset;
+
+ while (count--)
+ *addr++ = rd16(baddr);
+}
+
+void
+octopci_bs_rm_4(void *t, bus_space_handle_t bsh,
+ bus_size_t offset, uint32_t *addr, size_t count)
+{
+ bus_addr_t baddr = bsh + offset;
+
+ while (count--)
+ *addr++ = rd32(baddr);
+}
+
+
+/*
+ * Read `count' 1, 2, 4, or 8 byte quantities from bus space
+ * described by tag/handle and starting at `offset' and copy into
+ * buffer provided.
+ */
+void
+octopci_bs_rr_1(void *t, bus_space_handle_t bsh,
+ bus_size_t offset, uint8_t *addr, size_t count)
+{
+ bus_addr_t baddr = bsh + offset;
+
+ while (count--) {
+ *addr++ = rd8(baddr);
+ baddr += 1;
+ }
+}
+
+void
+octopci_bs_rr_2(void *t, bus_space_handle_t bsh,
+ bus_size_t offset, uint16_t *addr, size_t count)
+{
+ bus_addr_t baddr = bsh + offset;
+
+ while (count--) {
+ *addr++ = rd16(baddr);
+ baddr += 2;
+ }
+}
+
+void
+octopci_bs_rr_4(void *t, bus_space_handle_t bsh,
+ bus_size_t offset, uint32_t *addr, size_t count)
+{
+ bus_addr_t baddr = bsh + offset;
+
+ while (count--) {
+ *addr++ = rd32(baddr);
+ baddr += 4;
+ }
+}
+
+/*
+ * Write the 1, 2, 4, or 8 byte value `value' to bus space
+ * described by tag/handle/offset.
+ */
+void
+octopci_bs_w_1(void *t, bus_space_handle_t bsh,
+ bus_size_t offset, uint8_t value)
+{
+
+ wr8(bsh + offset, value);
+}
+
+void
+octopci_bs_w_2(void *t, bus_space_handle_t bsh,
+ bus_size_t offset, uint16_t value)
+{
+
+ wr16(bsh + offset, value);
+}
+
+void
+octopci_bs_w_4(void *t, bus_space_handle_t bsh,
+ bus_size_t offset, uint32_t value)
+{
+
+ wr32(bsh + offset, value);
+}
+
+/*
+ * Write `count' 1, 2, 4, or 8 byte quantities from the buffer
+ * provided to bus space described by tag/handle/offset.
+ */
+void
+octopci_bs_wm_1(void *t, bus_space_handle_t bsh,
+ bus_size_t offset, const uint8_t *addr, size_t count)
+{
+ bus_addr_t baddr = bsh + offset;
+
+ while (count--)
+ wr8(baddr, *addr++);
+}
+
+void
+octopci_bs_wm_2(void *t, bus_space_handle_t bsh,
+ bus_size_t offset, const uint16_t *addr, size_t count)
+{
+ bus_addr_t baddr = bsh + offset;
+
+ while (count--)
+ wr16(baddr, *addr++);
+}
+
+void
+octopci_bs_wm_4(void *t, bus_space_handle_t bsh,
+ bus_size_t offset, const uint32_t *addr, size_t count)
+{
+ bus_addr_t baddr = bsh + offset;
+
+ while (count--)
+ wr32(baddr, *addr++);
+}
+
+/*
+ * Write `count' 1, 2, 4, or 8 byte quantities from the buffer provided
+ * to bus space described by tag/handle starting at `offset'.
+ */
+void
+octopci_bs_wr_1(void *t, bus_space_handle_t bsh,
+ bus_size_t offset, const uint8_t *addr, size_t count)
+{
+ bus_addr_t baddr = bsh + offset;
+
+ while (count--) {
+ wr8(baddr, *addr++);
+ baddr += 1;
+ }
+}
+
+void
+octopci_bs_wr_2(void *t, bus_space_handle_t bsh,
+ bus_size_t offset, const uint16_t *addr, size_t count)
+{
+ bus_addr_t baddr = bsh + offset;
+
+ while (count--) {
+ wr16(baddr, *addr++);
+ baddr += 2;
+ }
+}
+
+void
+octopci_bs_wr_4(void *t, bus_space_handle_t bsh,
+ bus_size_t offset, const uint32_t *addr, size_t count)
+{
+ bus_addr_t baddr = bsh + offset;
+
+ while (count--) {
+ wr32(baddr, *addr++);
+ baddr += 4;
+ }
+}
+
+/*
+ * Write the 1, 2, 4, or 8 byte value `val' to bus space described
+ * by tag/handle/offset `count' times.
+ */
+void
+octopci_bs_sm_1(void *t, bus_space_handle_t bsh,
+ bus_size_t offset, uint8_t value, size_t count)
+{
+ bus_addr_t addr = bsh + offset;
+
+ while (count--)
+ wr8(addr, value);
+}
+
+void
+octopci_bs_sm_2(void *t, bus_space_handle_t bsh,
+ bus_size_t offset, uint16_t value, size_t count)
+{
+ bus_addr_t addr = bsh + offset;
+
+ while (count--)
+ wr16(addr, value);
+}
+
+void
+octopci_bs_sm_4(void *t, bus_space_handle_t bsh,
+ bus_size_t offset, uint32_t value, size_t count)
+{
+ bus_addr_t addr = bsh + offset;
+
+ while (count--)
+ wr32(addr, value);
+}
+
+/*
+ * Write `count' 1, 2, 4, or 8 byte value `val' to bus space described
+ * by tag/handle starting at `offset'.
+ */
+void
+octopci_bs_sr_1(void *t, bus_space_handle_t bsh,
+ bus_size_t offset, uint8_t value, size_t count)
+{
+ bus_addr_t addr = bsh + offset;
+
+ for (; count != 0; count--, addr++)
+ wr8(addr, value);
+}
+
+void
+octopci_bs_sr_2(void *t, bus_space_handle_t bsh,
+ bus_size_t offset, uint16_t value, size_t count)
+{
+ bus_addr_t addr = bsh + offset;
+
+ for (; count != 0; count--, addr += 2)
+ wr16(addr, value);
+}
+
+void
+octopci_bs_sr_4(void *t, bus_space_handle_t bsh,
+ bus_size_t offset, uint32_t value, size_t count)
+{
+ bus_addr_t addr = bsh + offset;
+
+ for (; count != 0; count--, addr += 4)
+ wr32(addr, value);
+}
+
+/*
+ * Copy `count' 1, 2, 4, or 8 byte values from bus space starting
+ * at tag/bsh1/off1 to bus space starting at tag/bsh2/off2.
+ */
+void
+octopci_bs_c_1(void *t, bus_space_handle_t bsh1,
+ bus_size_t off1, bus_space_handle_t bsh2,
+ bus_size_t off2, size_t count)
+{
+ bus_addr_t addr1 = bsh1 + off1;
+ bus_addr_t addr2 = bsh2 + off2;
+
+ if (addr1 >= addr2) {
+ /* src after dest: copy forward */
+ for (; count != 0; count--, addr1++, addr2++)
+ wr8(addr2, rd8(addr1));
+ } else {
+ /* dest after src: copy backwards */
+ for (addr1 += (count - 1), addr2 += (count - 1);
+ count != 0; count--, addr1--, addr2--)
+ wr8(addr2, rd8(addr1));
+ }
+}
+
+void
+octopci_bs_c_2(void *t, bus_space_handle_t bsh1,
+ bus_size_t off1, bus_space_handle_t bsh2,
+ bus_size_t off2, size_t count)
+{
+ bus_addr_t addr1 = bsh1 + off1;
+ bus_addr_t addr2 = bsh2 + off2;
+
+ if (addr1 >= addr2) {
+ /* src after dest: copy forward */
+ for (; count != 0; count--, addr1 += 2, addr2 += 2)
+ wr16(addr2, rd16(addr1));
+ } else {
+ /* dest after src: copy backwards */
+ for (addr1 += 2 * (count - 1), addr2 += 2 * (count - 1);
+ count != 0; count--, addr1 -= 2, addr2 -= 2)
+ wr16(addr2, rd16(addr1));
+ }
+}
+
+void
+octopci_bs_c_4(void *t, bus_space_handle_t bsh1,
+ bus_size_t off1, bus_space_handle_t bsh2,
+ bus_size_t off2, size_t count)
+{
+ bus_addr_t addr1 = bsh1 + off1;
+ bus_addr_t addr2 = bsh2 + off2;
+
+ if (addr1 >= addr2) {
+ /* src after dest: copy forward */
+ for (; count != 0; count--, addr1 += 4, addr2 += 4)
+ wr32(addr2, rd32(addr1));
+ } else {
+ /* dest after src: copy backwards */
+ for (addr1 += 4 * (count - 1), addr2 += 4 * (count - 1);
+ count != 0; count--, addr1 -= 4, addr2 -= 4)
+ wr32(addr2, rd32(addr1));
+ }
+}
+
+void
+octopci_bs_barrier(void *t __unused,
+ bus_space_handle_t bsh __unused,
+ bus_size_t offset __unused, bus_size_t len __unused,
+ int flags)
+{
+#if 0
+ if (flags & BUS_SPACE_BARRIER_WRITE)
+ mips_dcache_wbinv_all();
+#endif
+}
Property changes on: trunk/sys/mips/cavium/octopci_bus_space.c
___________________________________________________________________
Added: svn:eol-style
## -0,0 +1 ##
+native
\ No newline at end of property
Added: svn:keywords
## -0,0 +1 ##
+MidnightBSD=%H
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+text/plain
\ No newline at end of property
Added: trunk/sys/mips/cavium/octopcireg.h
===================================================================
--- trunk/sys/mips/cavium/octopcireg.h (rev 0)
+++ trunk/sys/mips/cavium/octopcireg.h 2018-05-26 21:55:02 UTC (rev 9987)
@@ -0,0 +1,106 @@
+/* $MidnightBSD$ */
+/***********************license start************************************
+ * Copyright (c) 2005-2007 Cavium Networks (support at cavium.com). All rights
+ * reserved.
+ *
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
+ *
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ *
+ * * Redistributions in binary form must reproduce the above
+ * copyright notice, this list of conditions and the following
+ * disclaimer in the documentation and/or other materials provided
+ * with the distribution.
+ *
+ * * Neither the name of Cavium Networks nor the names of
+ * its contributors may be used to endorse or promote products
+ * derived from this software without specific prior written
+ * permission.
+ *
+ * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
+ * AND WITH ALL FAULTS AND CAVIUM NETWORKS MAKES NO PROMISES, REPRESENTATIONS
+ * OR WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH
+ * RESPECT TO THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY
+ * REPRESENTATION OR DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT
+ * DEFECTS, AND CAVIUM SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES
+ * OF TITLE, MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR
+ * PURPOSE, LACK OF VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET
+ * POSSESSION OR CORRESPONDENCE TO DESCRIPTION. THE ENTIRE RISK ARISING OUT
+ * OF USE OR PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
+ *
+ *
+ * For any questions regarding licensing please contact marketing at caviumnetworks.com
+ *
+ ***********************license end**************************************/
+/* $FreeBSD: stable/10/sys/mips/cavium/octopcireg.h 213089 2010-09-24 00:14:24Z jmallett $ */
+
+#ifndef _CAVIUM_OCTOPCIREG_H_
+#define _CAVIUM_OCTOPCIREG_H_
+
+/**
+ * This is the bit decoding used for the Octeon PCI controller addresses for config space
+ */
+typedef union
+{
+ uint64_t u64;
+ uint64_t * u64_ptr;
+ uint32_t * u32_ptr;
+ uint16_t * u16_ptr;
+ uint8_t * u8_ptr;
+ struct
+ {
+ uint64_t upper : 2;
+ uint64_t reserved : 13;
+ uint64_t io : 1;
+ uint64_t did : 5;
+ uint64_t subdid : 3;
+ uint64_t reserved2 : 4;
+ uint64_t endian_swap : 2;
+ uint64_t reserved3 : 10;
+ uint64_t bus : 8;
+ uint64_t dev : 5;
+ uint64_t func : 3;
+ uint64_t reg : 8;
+ } s;
+} octeon_pci_config_space_address_t;
+
+typedef union
+{
+ uint64_t u64;
+ uint32_t * u32_ptr;
+ uint16_t * u16_ptr;
+ uint8_t * u8_ptr;
+ struct
+ {
+ uint64_t upper : 2;
+ uint64_t reserved : 13;
+ uint64_t io : 1;
+ uint64_t did : 5;
+ uint64_t subdid : 3;
+ uint64_t reserved2 : 4;
+ uint64_t endian_swap : 2;
+ uint64_t res1 : 1;
+ uint64_t port : 1;
+ uint64_t addr : 32;
+ } s;
+} octeon_pci_io_space_address_t;
+
+
+#define CVMX_OCT_SUBDID_PCI_CFG 1
+#define CVMX_OCT_SUBDID_PCI_IO 2
+#define CVMX_OCT_SUBDID_PCI_MEM1 3
+#define CVMX_OCT_SUBDID_PCI_MEM2 4
+#define CVMX_OCT_SUBDID_PCI_MEM3 5
+#define CVMX_OCT_SUBDID_PCI_MEM4 6
+
+#define CVMX_OCT_PCI_IO_BASE 0x00004000
+#define CVMX_OCT_PCI_IO_SIZE 0x08000000
+
+#define CVMX_OCT_PCI_MEM1_BASE 0xf0000000
+#define CVMX_OCT_PCI_MEM1_SIZE 0x0f000000
+
+#endif /* !_CAVIUM_OCTOPCIREG_H_ */
Property changes on: trunk/sys/mips/cavium/octopcireg.h
___________________________________________________________________
Added: svn:eol-style
## -0,0 +1 ##
+native
\ No newline at end of property
Added: svn:keywords
## -0,0 +1 ##
+MidnightBSD=%H
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+text/plain
\ No newline at end of property
Added: trunk/sys/mips/cavium/octopcivar.h
===================================================================
--- trunk/sys/mips/cavium/octopcivar.h (rev 0)
+++ trunk/sys/mips/cavium/octopcivar.h 2018-05-26 21:55:02 UTC (rev 9987)
@@ -0,0 +1,36 @@
+/* $MidnightBSD$ */
+/*-
+ * Copyright (c) 2010 Juli Mallett <jmallett at FreeBSD.org>
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ * $FreeBSD: stable/10/sys/mips/cavium/octopcivar.h 210311 2010-07-20 19:25:11Z jmallett $
+ */
+#ifndef _MIPS_CAVIUM_OCTOPCIVAR_H
+#define _MIPS_CAVIUM_OCTOPCIVAR_H
+
+DECLARE_BUS_SPACE_PROTOTYPES(octopci);
+
+extern bus_space_tag_t octopci_bus_space;
+
+#endif /* !_MIPS_CAVIUM_OCTOPCIVAR_H */
Property changes on: trunk/sys/mips/cavium/octopcivar.h
___________________________________________________________________
Added: svn:eol-style
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+native
\ No newline at end of property
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## -0,0 +1 ##
+MidnightBSD=%H
\ No newline at end of property
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## -0,0 +1 ##
+text/plain
\ No newline at end of property
Added: trunk/sys/mips/cavium/std.octeon1
===================================================================
--- trunk/sys/mips/cavium/std.octeon1 (rev 0)
+++ trunk/sys/mips/cavium/std.octeon1 2018-05-26 21:55:02 UTC (rev 9987)
@@ -0,0 +1,5 @@
+# $FreeBSD: stable/10/sys/mips/cavium/std.octeon1 253539 2013-07-22 03:55:15Z imp $
+#
+files "../cavium/files.octeon1"
+machine mips mips64
+cpu CPU_CNMIPS
Property changes on: trunk/sys/mips/cavium/std.octeon1
___________________________________________________________________
Added: mnbsd:nokeywords
## -0,0 +1 ##
+MidnightBSD=%H
\ No newline at end of property
Added: trunk/sys/mips/cavium/uart_bus_octeonusart.c
===================================================================
--- trunk/sys/mips/cavium/uart_bus_octeonusart.c (rev 0)
+++ trunk/sys/mips/cavium/uart_bus_octeonusart.c 2018-05-26 21:55:02 UTC (rev 9987)
@@ -0,0 +1,112 @@
+/* $MidnightBSD$ */
+/*-
+ * Copyright (c) 2006 Wojciech A. Koszek <wkoszek at FreeBSD.org>
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * $Id$
+ */
+/*
+ * Skeleton of this file was based on respective code for ARM
+ * code written by Olivier Houchard.
+ */
+
+/*
+ * XXXMIPS: This file is hacked from arm/... . XXXMIPS here means this file is
+ * experimental and was written for MIPS32 port.
+ */
+#include "opt_uart.h"
+
+#include <sys/cdefs.h>
+__FBSDID("$FreeBSD: stable/10/sys/mips/cavium/uart_bus_octeonusart.c 237687 2012-06-28 06:49:04Z imp $");
+
+#include <sys/param.h>
+#include <sys/systm.h>
+#include <sys/bus.h>
+#include <sys/conf.h>
+#include <sys/kernel.h>
+#include <sys/module.h>
+#include <machine/bus.h>
+#include <sys/rman.h>
+#include <machine/resource.h>
+
+#include <dev/pci/pcivar.h>
+
+#include <dev/uart/uart.h>
+#include <dev/uart/uart_bus.h>
+#include <dev/uart/uart_cpu.h>
+
+#include <mips/cavium/octeon_pcmap_regs.h>
+
+#include <contrib/octeon-sdk/cvmx.h>
+
+#include "uart_if.h"
+
+extern struct uart_class uart_oct16550_class;
+
+static int uart_octeon_probe(device_t dev);
+
+static device_method_t uart_octeon_methods[] = {
+ /* Device interface */
+ DEVMETHOD(device_probe, uart_octeon_probe),
+ DEVMETHOD(device_attach, uart_bus_attach),
+ DEVMETHOD(device_detach, uart_bus_detach),
+ {0, 0}
+};
+
+static driver_t uart_octeon_driver = {
+ uart_driver_name,
+ uart_octeon_methods,
+ sizeof(struct uart_softc),
+};
+
+extern
+SLIST_HEAD(uart_devinfo_list, uart_devinfo) uart_sysdevs;
+
+static int
+uart_octeon_probe(device_t dev)
+{
+ struct uart_softc *sc;
+ int unit;
+
+ unit = device_get_unit(dev);
+ sc = device_get_softc(dev);
+ sc->sc_class = &uart_oct16550_class;
+
+ /*
+ * We inherit the settings from the systme console. Note, the bst
+ * bad bus_space_map are bogus here, but obio doesn't yet support
+ * them, it seems.
+ */
+ sc->sc_sysdev = SLIST_FIRST(&uart_sysdevs);
+ bcopy(&sc->sc_sysdev->bas, &sc->sc_bas, sizeof(sc->sc_bas));
+ sc->sc_bas.bst = uart_bus_space_mem;
+ /*
+ * XXX
+ * RBR isn't really a great base address.
+ */
+ if (bus_space_map(sc->sc_bas.bst, CVMX_MIO_UARTX_RBR(0),
+ uart_getrange(sc->sc_class), 0, &sc->sc_bas.bsh) != 0)
+ return (ENXIO);
+ return (uart_bus_probe(dev, sc->sc_bas.regshft, 0, 0, unit));
+}
+
+DRIVER_MODULE(uart, obio, uart_octeon_driver, uart_devclass, 0, 0);
Property changes on: trunk/sys/mips/cavium/uart_bus_octeonusart.c
___________________________________________________________________
Added: svn:eol-style
## -0,0 +1 ##
+native
\ No newline at end of property
Added: svn:keywords
## -0,0 +1 ##
+MidnightBSD=%H
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+text/plain
\ No newline at end of property
Added: trunk/sys/mips/cavium/uart_cpu_octeonusart.c
===================================================================
--- trunk/sys/mips/cavium/uart_cpu_octeonusart.c (rev 0)
+++ trunk/sys/mips/cavium/uart_cpu_octeonusart.c 2018-05-26 21:55:02 UTC (rev 9987)
@@ -0,0 +1,175 @@
+/* $MidnightBSD$ */
+/*-
+ * Copyright (c) 2009 M. Warner Losh <imp at FreeBSD.org>
+ * Copyright (c) 2006 Wojciech A. Koszek <wkoszek at FreeBSD.org>
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ * $Id$
+ */
+#include "opt_uart.h"
+
+#include <sys/cdefs.h>
+__FBSDID("$FreeBSD: stable/10/sys/mips/cavium/uart_cpu_octeonusart.c 242345 2012-10-30 06:29:17Z jmallett $");
+
+#include <sys/param.h>
+#include <sys/systm.h>
+#include <sys/bus.h>
+#include <sys/cons.h>
+
+#include <machine/bus.h>
+
+#include <dev/uart/uart.h>
+#include <dev/uart/uart_cpu.h>
+
+#include <mips/cavium/octeon_pcmap_regs.h>
+
+#include <contrib/octeon-sdk/cvmx.h>
+
+bus_space_tag_t uart_bus_space_io;
+bus_space_tag_t uart_bus_space_mem;
+
+/*
+ * Specailized uart bus space. We present a 1 apart byte oriented
+ * bus to the outside world, but internally translate to/from the 8-apart
+ * 64-bit word bus that's on the octeon. We only support simple read/write
+ * in this space. Everything else is undefined.
+ */
+static uint8_t
+ou_bs_r_1(void *t, bus_space_handle_t handle, bus_size_t offset)
+{
+
+ return (cvmx_read64_uint64(handle + offset));
+}
+
+static uint16_t
+ou_bs_r_2(void *t, bus_space_handle_t handle, bus_size_t offset)
+{
+
+ return (cvmx_read64_uint64(handle + offset));
+}
+
+static uint32_t
+ou_bs_r_4(void *t, bus_space_handle_t handle, bus_size_t offset)
+{
+
+ return (cvmx_read64_uint64(handle + offset));
+}
+
+static uint64_t
+ou_bs_r_8(void *t, bus_space_handle_t handle, bus_size_t offset)
+{
+
+ return (cvmx_read64_uint64(handle + offset));
+}
+
+static void
+ou_bs_w_1(void *t, bus_space_handle_t bsh, bus_size_t offset, uint8_t value)
+{
+
+ cvmx_write64_uint64(bsh + offset, value);
+}
+
+static void
+ou_bs_w_2(void *t, bus_space_handle_t bsh, bus_size_t offset, uint16_t value)
+{
+
+ cvmx_write64_uint64(bsh + offset, value);
+}
+
+static void
+ou_bs_w_4(void *t, bus_space_handle_t bsh, bus_size_t offset, uint32_t value)
+{
+
+ cvmx_write64_uint64(bsh + offset, value);
+}
+
+static void
+ou_bs_w_8(void *t, bus_space_handle_t bsh, bus_size_t offset, uint64_t value)
+{
+
+ cvmx_write64_uint64(bsh + offset, value);
+}
+
+struct bus_space octeon_uart_tag = {
+ .bs_map = generic_bs_map,
+ .bs_unmap = generic_bs_unmap,
+ .bs_subregion = generic_bs_subregion,
+ .bs_barrier = generic_bs_barrier,
+ .bs_r_1 = ou_bs_r_1,
+ .bs_r_2 = ou_bs_r_2,
+ .bs_r_4 = ou_bs_r_4,
+ .bs_r_8 = ou_bs_r_8,
+ .bs_w_1 = ou_bs_w_1,
+ .bs_w_2 = ou_bs_w_2,
+ .bs_w_4 = ou_bs_w_4,
+ .bs_w_8 = ou_bs_w_8,
+};
+
+extern struct uart_class uart_oct16550_class;
+
+int
+uart_cpu_eqres(struct uart_bas *b1, struct uart_bas *b2)
+{
+
+ return ((b1->bsh == b2->bsh && b1->bst == b2->bst) ? 1 : 0);
+}
+
+int
+uart_cpu_getdev(int devtype, struct uart_devinfo *di)
+{
+ struct uart_class *class = &uart_oct16550_class;
+
+ /*
+ * These fields need to be setup corretly for uart_getenv to
+ * work in all cases.
+ */
+ uart_bus_space_io = NULL; /* No io map for this device */
+ uart_bus_space_mem = &octeon_uart_tag;
+ di->bas.bst = uart_bus_space_mem;
+
+ /*
+ * If env specification for UART exists it takes precedence:
+ * hw.uart.console="mm:0xf1012000" or similar
+ */
+ if (uart_getenv(devtype, di, class) == 0)
+ return (0);
+
+ /*
+ * Fallback to UART0 for console.
+ */
+ di->ops = uart_getops(class);
+ di->bas.chan = 0;
+ /* XXX */
+ if (bus_space_map(di->bas.bst, CVMX_MIO_UARTX_RBR(0),
+ uart_getrange(class), 0, &di->bas.bsh) != 0)
+ return (ENXIO);
+ di->bas.regshft = 3;
+ di->bas.rclk = 0;
+ di->baudrate = 115200;
+ di->databits = 8;
+ di->stopbits = 1;
+ di->parity = UART_PARITY_NONE;
+
+ return (0);
+}
Property changes on: trunk/sys/mips/cavium/uart_cpu_octeonusart.c
___________________________________________________________________
Added: svn:eol-style
## -0,0 +1 ##
+native
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## -0,0 +1 ##
+MidnightBSD=%H
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## -0,0 +1 ##
+text/plain
\ No newline at end of property
Added: trunk/sys/mips/cavium/uart_dev_oct16550.c
===================================================================
--- trunk/sys/mips/cavium/uart_dev_oct16550.c (rev 0)
+++ trunk/sys/mips/cavium/uart_dev_oct16550.c 2018-05-26 21:55:02 UTC (rev 9987)
@@ -0,0 +1,848 @@
+/* $MidnightBSD$ */
+/*-
+ * Copyright (c) 2003 Marcel Moolenaar
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+ * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+ * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/*
+ * uart_dev_oct16550.c
+ *
+ * Derived from uart_dev_ns8250.c
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+ * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+ * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ *
+ */
+
+
+#include <sys/cdefs.h>
+__FBSDID("$FreeBSD: stable/10/sys/mips/cavium/uart_dev_oct16550.c 262649 2014-03-01 04:16:54Z imp $");
+
+#include <sys/param.h>
+#include <sys/systm.h>
+#include <sys/bus.h>
+#include <sys/conf.h>
+#include <machine/bus.h>
+#include <machine/pcpu.h>
+
+#include <dev/uart/uart.h>
+#include <dev/uart/uart_cpu.h>
+#include <dev/uart/uart_bus.h>
+
+#include <dev/ic/ns16550.h>
+
+#include <mips/cavium/octeon_pcmap_regs.h>
+
+#include <contrib/octeon-sdk/cvmx.h>
+
+#include "uart_if.h"
+
+/*
+ * Clear pending interrupts. THRE is cleared by reading IIR. Data
+ * that may have been received gets lost here.
+ */
+static void
+oct16550_clrint (struct uart_bas *bas)
+{
+ uint8_t iir;
+
+ iir = uart_getreg(bas, REG_IIR);
+ while ((iir & IIR_NOPEND) == 0) {
+ iir &= IIR_IMASK;
+ if (iir == IIR_RLS)
+ (void)uart_getreg(bas, REG_LSR);
+ else if (iir == IIR_RXRDY || iir == IIR_RXTOUT)
+ (void)uart_getreg(bas, REG_DATA);
+ else if (iir == IIR_MLSC)
+ (void)uart_getreg(bas, REG_MSR);
+ else if (iir == IIR_BUSY)
+ (void) uart_getreg(bas, REG_USR);
+ uart_barrier(bas);
+ iir = uart_getreg(bas, REG_IIR);
+ }
+}
+
+static int delay_changed = 1;
+
+static int
+oct16550_delay (struct uart_bas *bas)
+{
+ int divisor;
+ u_char lcr;
+ static int delay = 0;
+
+ if (!delay_changed) return delay;
+ delay_changed = 0;
+ lcr = uart_getreg(bas, REG_LCR);
+ uart_setreg(bas, REG_LCR, lcr | LCR_DLAB);
+ uart_barrier(bas);
+ divisor = uart_getreg(bas, REG_DLL) | (uart_getreg(bas, REG_DLH) << 8);
+ uart_barrier(bas);
+ uart_setreg(bas, REG_LCR, lcr);
+ uart_barrier(bas);
+
+ if(!bas->rclk)
+ return 10; /* return an approx delay value */
+
+ /* 1/10th the time to transmit 1 character (estimate). */
+ if (divisor <= 134)
+ return (16000000 * divisor / bas->rclk);
+ return (16000 * divisor / (bas->rclk / 1000));
+
+}
+
+static int
+oct16550_divisor (int rclk, int baudrate)
+{
+ int actual_baud, divisor;
+ int error;
+
+ if (baudrate == 0)
+ return (0);
+
+ divisor = (rclk / (baudrate << 3) + 1) >> 1;
+ if (divisor == 0 || divisor >= 65536)
+ return (0);
+ actual_baud = rclk / (divisor << 4);
+
+ /* 10 times error in percent: */
+ error = ((actual_baud - baudrate) * 2000 / baudrate + 1) >> 1;
+
+ /* 3.0% maximum error tolerance: */
+ if (error < -30 || error > 30)
+ return (0);
+
+ return (divisor);
+}
+
+static int
+oct16550_drain (struct uart_bas *bas, int what)
+{
+ int delay, limit;
+
+ delay = oct16550_delay(bas);
+
+ if (what & UART_DRAIN_TRANSMITTER) {
+ /*
+ * Pick an arbitrary high limit to avoid getting stuck in
+ * an infinite loop when the hardware is broken. Make the
+ * limit high enough to handle large FIFOs.
+ */
+ limit = 10*10*10*1024;
+ while ((uart_getreg(bas, REG_LSR) & LSR_TEMT) == 0 && --limit)
+ DELAY(delay);
+ if (limit == 0) {
+ /* printf("oct16550: transmitter appears stuck... "); */
+ return (0);
+ }
+ }
+
+ if (what & UART_DRAIN_RECEIVER) {
+ /*
+ * Pick an arbitrary high limit to avoid getting stuck in
+ * an infinite loop when the hardware is broken. Make the
+ * limit high enough to handle large FIFOs and integrated
+ * UARTs. The HP rx2600 for example has 3 UARTs on the
+ * management board that tend to get a lot of data send
+ * to it when the UART is first activated.
+ */
+ limit=10*4096;
+ while ((uart_getreg(bas, REG_LSR) & LSR_RXRDY) && --limit) {
+ (void)uart_getreg(bas, REG_DATA);
+ uart_barrier(bas);
+ DELAY(delay << 2);
+ }
+ if (limit == 0) {
+ /* printf("oct16550: receiver appears broken... "); */
+ return (EIO);
+ }
+ }
+
+ return (0);
+}
+
+/*
+ * We can only flush UARTs with FIFOs. UARTs without FIFOs should be
+ * drained. WARNING: this function clobbers the FIFO setting!
+ */
+static void
+oct16550_flush (struct uart_bas *bas, int what)
+{
+ uint8_t fcr;
+
+ fcr = FCR_ENABLE;
+ if (what & UART_FLUSH_TRANSMITTER)
+ fcr |= FCR_XMT_RST;
+ if (what & UART_FLUSH_RECEIVER)
+ fcr |= FCR_RCV_RST;
+ uart_setreg(bas, REG_FCR, fcr);
+ uart_barrier(bas);
+}
+
+static int
+oct16550_param (struct uart_bas *bas, int baudrate, int databits, int stopbits,
+ int parity)
+{
+ int divisor;
+ uint8_t lcr;
+
+ lcr = 0;
+ if (databits >= 8)
+ lcr |= LCR_8BITS;
+ else if (databits == 7)
+ lcr |= LCR_7BITS;
+ else if (databits == 6)
+ lcr |= LCR_6BITS;
+ else
+ lcr |= LCR_5BITS;
+ if (stopbits > 1)
+ lcr |= LCR_STOPB;
+ lcr |= parity << 3;
+
+ /* Set baudrate. */
+ if (baudrate > 0) {
+ divisor = oct16550_divisor(bas->rclk, baudrate);
+ if (divisor == 0)
+ return (EINVAL);
+ uart_setreg(bas, REG_LCR, lcr | LCR_DLAB);
+ uart_barrier(bas);
+ uart_setreg(bas, REG_DLL, divisor & 0xff);
+ uart_setreg(bas, REG_DLH, (divisor >> 8) & 0xff);
+ uart_barrier(bas);
+ delay_changed = 1;
+ }
+
+ /* Set LCR and clear DLAB. */
+ uart_setreg(bas, REG_LCR, lcr);
+ uart_barrier(bas);
+ return (0);
+}
+
+/*
+ * Low-level UART interface.
+ */
+static int oct16550_probe(struct uart_bas *bas);
+static void oct16550_init(struct uart_bas *bas, int, int, int, int);
+static void oct16550_term(struct uart_bas *bas);
+static void oct16550_putc(struct uart_bas *bas, int);
+static int oct16550_rxready(struct uart_bas *bas);
+static int oct16550_getc(struct uart_bas *bas, struct mtx *);
+
+struct uart_ops uart_oct16550_ops = {
+ .probe = oct16550_probe,
+ .init = oct16550_init,
+ .term = oct16550_term,
+ .putc = oct16550_putc,
+ .rxready = oct16550_rxready,
+ .getc = oct16550_getc,
+};
+
+static int
+oct16550_probe (struct uart_bas *bas)
+{
+ u_char val;
+
+ /* Check known 0 bits that don't depend on DLAB. */
+ val = uart_getreg(bas, REG_IIR);
+ if (val & 0x30)
+ return (ENXIO);
+ val = uart_getreg(bas, REG_MCR);
+ if (val & 0xc0)
+ return (ENXIO);
+ val = uart_getreg(bas, REG_USR);
+ if (val & 0xe0)
+ return (ENXIO);
+ return (0);
+}
+
+static void
+oct16550_init (struct uart_bas *bas, int baudrate, int databits, int stopbits,
+ int parity)
+{
+ u_char ier;
+
+ oct16550_param(bas, baudrate, databits, stopbits, parity);
+
+ /* Disable all interrupt sources. */
+ ier = uart_getreg(bas, REG_IER) & 0x0;
+ uart_setreg(bas, REG_IER, ier);
+ uart_barrier(bas);
+
+ /* Disable the FIFO (if present). */
+// uart_setreg(bas, REG_FCR, 0);
+ uart_barrier(bas);
+
+ /* Set RTS & DTR. */
+ uart_setreg(bas, REG_MCR, MCR_RTS | MCR_DTR);
+ uart_barrier(bas);
+
+ oct16550_clrint(bas);
+}
+
+static void
+oct16550_term (struct uart_bas *bas)
+{
+
+ /* Clear RTS & DTR. */
+ uart_setreg(bas, REG_MCR, 0);
+ uart_barrier(bas);
+}
+
+static inline void oct16550_wait_txhr_empty (struct uart_bas *bas, int limit, int delay)
+{
+ while (((uart_getreg(bas, REG_LSR) & LSR_THRE) == 0) &&
+ ((uart_getreg(bas, REG_USR) & USR_TXFIFO_NOTFULL) == 0))
+ DELAY(delay);
+}
+
+static void
+oct16550_putc (struct uart_bas *bas, int c)
+{
+ int delay;
+
+ /* 1/10th the time to transmit 1 character (estimate). */
+ delay = oct16550_delay(bas);
+ oct16550_wait_txhr_empty(bas, 100, delay);
+ uart_setreg(bas, REG_DATA, c);
+ uart_barrier(bas);
+ oct16550_wait_txhr_empty(bas, 100, delay);
+}
+
+static int
+oct16550_rxready (struct uart_bas *bas)
+{
+
+ return ((uart_getreg(bas, REG_LSR) & LSR_RXRDY) != 0 ? 1 : 0);
+}
+
+static int
+oct16550_getc (struct uart_bas *bas, struct mtx *hwmtx)
+{
+ int c, delay;
+
+ uart_lock(hwmtx);
+
+ /* 1/10th the time to transmit 1 character (estimate). */
+ delay = oct16550_delay(bas);
+
+ while ((uart_getreg(bas, REG_LSR) & LSR_RXRDY) == 0) {
+ uart_unlock(hwmtx);
+ DELAY(delay);
+ uart_lock(hwmtx);
+ }
+
+ c = uart_getreg(bas, REG_DATA);
+
+ uart_unlock(hwmtx);
+
+ return (c);
+}
+
+/*
+ * High-level UART interface.
+ */
+struct oct16550_softc {
+ struct uart_softc base;
+ uint8_t fcr;
+ uint8_t ier;
+ uint8_t mcr;
+};
+
+static int oct16550_bus_attach(struct uart_softc *);
+static int oct16550_bus_detach(struct uart_softc *);
+static int oct16550_bus_flush(struct uart_softc *, int);
+static int oct16550_bus_getsig(struct uart_softc *);
+static int oct16550_bus_ioctl(struct uart_softc *, int, intptr_t);
+static int oct16550_bus_ipend(struct uart_softc *);
+static int oct16550_bus_param(struct uart_softc *, int, int, int, int);
+static int oct16550_bus_probe(struct uart_softc *);
+static int oct16550_bus_receive(struct uart_softc *);
+static int oct16550_bus_setsig(struct uart_softc *, int);
+static int oct16550_bus_transmit(struct uart_softc *);
+static void oct16550_bus_grab(struct uart_softc *);
+static void oct16550_bus_ungrab(struct uart_softc *);
+
+static kobj_method_t oct16550_methods[] = {
+ KOBJMETHOD(uart_attach, oct16550_bus_attach),
+ KOBJMETHOD(uart_detach, oct16550_bus_detach),
+ KOBJMETHOD(uart_flush, oct16550_bus_flush),
+ KOBJMETHOD(uart_getsig, oct16550_bus_getsig),
+ KOBJMETHOD(uart_ioctl, oct16550_bus_ioctl),
+ KOBJMETHOD(uart_ipend, oct16550_bus_ipend),
+ KOBJMETHOD(uart_param, oct16550_bus_param),
+ KOBJMETHOD(uart_probe, oct16550_bus_probe),
+ KOBJMETHOD(uart_receive, oct16550_bus_receive),
+ KOBJMETHOD(uart_setsig, oct16550_bus_setsig),
+ KOBJMETHOD(uart_transmit, oct16550_bus_transmit),
+ KOBJMETHOD(uart_grab, oct16550_bus_grab),
+ KOBJMETHOD(uart_ungrab, oct16550_bus_ungrab),
+ { 0, 0 }
+};
+
+struct uart_class uart_oct16550_class = {
+ "oct16550 class",
+ oct16550_methods,
+ sizeof(struct oct16550_softc),
+ .uc_ops = &uart_oct16550_ops,
+ .uc_range = 8 << 3,
+ .uc_rclk = 0
+};
+
+#define SIGCHG(c, i, s, d) \
+ if (c) { \
+ i |= (i & s) ? s : s | d; \
+ } else { \
+ i = (i & s) ? (i & ~s) | d : i; \
+ }
+
+static int
+oct16550_bus_attach (struct uart_softc *sc)
+{
+ struct oct16550_softc *oct16550 = (struct oct16550_softc*)sc;
+ struct uart_bas *bas;
+ int unit;
+
+ unit = device_get_unit(sc->sc_dev);
+ bas = &sc->sc_bas;
+
+ oct16550_drain(bas, UART_DRAIN_TRANSMITTER);
+ oct16550->mcr = uart_getreg(bas, REG_MCR);
+ oct16550->fcr = FCR_ENABLE | FCR_RX_HIGH;
+ uart_setreg(bas, REG_FCR, oct16550->fcr);
+ uart_barrier(bas);
+ oct16550_bus_flush(sc, UART_FLUSH_RECEIVER|UART_FLUSH_TRANSMITTER);
+
+ if (oct16550->mcr & MCR_DTR)
+ sc->sc_hwsig |= SER_DTR;
+ if (oct16550->mcr & MCR_RTS)
+ sc->sc_hwsig |= SER_RTS;
+ oct16550_bus_getsig(sc);
+
+ oct16550_clrint(bas);
+ oct16550->ier = uart_getreg(bas, REG_IER) & 0xf0;
+ oct16550->ier |= IER_EMSC | IER_ERLS | IER_ERXRDY;
+ uart_setreg(bas, REG_IER, oct16550->ier);
+ uart_barrier(bas);
+
+ return (0);
+}
+
+static int
+oct16550_bus_detach (struct uart_softc *sc)
+{
+ struct uart_bas *bas;
+ u_char ier;
+
+ bas = &sc->sc_bas;
+ ier = uart_getreg(bas, REG_IER) & 0xf0;
+ uart_setreg(bas, REG_IER, ier);
+ uart_barrier(bas);
+ oct16550_clrint(bas);
+ return (0);
+}
+
+static int
+oct16550_bus_flush (struct uart_softc *sc, int what)
+{
+ struct oct16550_softc *oct16550 = (struct oct16550_softc*)sc;
+ struct uart_bas *bas;
+ int error;
+
+ bas = &sc->sc_bas;
+ uart_lock(sc->sc_hwmtx);
+ if (sc->sc_rxfifosz > 1) {
+ oct16550_flush(bas, what);
+ uart_setreg(bas, REG_FCR, oct16550->fcr);
+ uart_barrier(bas);
+ error = 0;
+ } else
+ error = oct16550_drain(bas, what);
+ uart_unlock(sc->sc_hwmtx);
+ return (error);
+}
+
+static int
+oct16550_bus_getsig (struct uart_softc *sc)
+{
+ uint32_t new, old, sig;
+ uint8_t msr;
+
+ do {
+ old = sc->sc_hwsig;
+ sig = old;
+ uart_lock(sc->sc_hwmtx);
+ msr = uart_getreg(&sc->sc_bas, REG_MSR);
+ uart_unlock(sc->sc_hwmtx);
+ SIGCHG(msr & MSR_DSR, sig, SER_DSR, SER_DDSR);
+ SIGCHG(msr & MSR_CTS, sig, SER_CTS, SER_DCTS);
+ SIGCHG(msr & MSR_DCD, sig, SER_DCD, SER_DDCD);
+ SIGCHG(msr & MSR_RI, sig, SER_RI, SER_DRI);
+ new = sig & ~SER_MASK_DELTA;
+ } while (!atomic_cmpset_32(&sc->sc_hwsig, old, new));
+ return (sig);
+}
+
+static int
+oct16550_bus_ioctl (struct uart_softc *sc, int request, intptr_t data)
+{
+ struct uart_bas *bas;
+ int baudrate, divisor, error;
+ uint8_t efr, lcr;
+
+ bas = &sc->sc_bas;
+ error = 0;
+ uart_lock(sc->sc_hwmtx);
+ switch (request) {
+ case UART_IOCTL_BREAK:
+ lcr = uart_getreg(bas, REG_LCR);
+ if (data)
+ lcr |= LCR_SBREAK;
+ else
+ lcr &= ~LCR_SBREAK;
+ uart_setreg(bas, REG_LCR, lcr);
+ uart_barrier(bas);
+ break;
+ case UART_IOCTL_IFLOW:
+ lcr = uart_getreg(bas, REG_LCR);
+ uart_barrier(bas);
+ uart_setreg(bas, REG_LCR, 0xbf);
+ uart_barrier(bas);
+ efr = uart_getreg(bas, REG_EFR);
+ if (data)
+ efr |= EFR_RTS;
+ else
+ efr &= ~EFR_RTS;
+ uart_setreg(bas, REG_EFR, efr);
+ uart_barrier(bas);
+ uart_setreg(bas, REG_LCR, lcr);
+ uart_barrier(bas);
+ break;
+ case UART_IOCTL_OFLOW:
+ lcr = uart_getreg(bas, REG_LCR);
+ uart_barrier(bas);
+ uart_setreg(bas, REG_LCR, 0xbf);
+ uart_barrier(bas);
+ efr = uart_getreg(bas, REG_EFR);
+ if (data)
+ efr |= EFR_CTS;
+ else
+ efr &= ~EFR_CTS;
+ uart_setreg(bas, REG_EFR, efr);
+ uart_barrier(bas);
+ uart_setreg(bas, REG_LCR, lcr);
+ uart_barrier(bas);
+ break;
+ case UART_IOCTL_BAUD:
+ lcr = uart_getreg(bas, REG_LCR);
+ uart_setreg(bas, REG_LCR, lcr | LCR_DLAB);
+ uart_barrier(bas);
+ divisor = uart_getreg(bas, REG_DLL) |
+ (uart_getreg(bas, REG_DLH) << 8);
+ uart_barrier(bas);
+ uart_setreg(bas, REG_LCR, lcr);
+ uart_barrier(bas);
+ baudrate = (divisor > 0) ? bas->rclk / divisor / 16 : 0;
+ delay_changed = 1;
+ if (baudrate > 0)
+ *(int*)data = baudrate;
+ else
+ error = ENXIO;
+ break;
+ default:
+ error = EINVAL;
+ break;
+ }
+ uart_unlock(sc->sc_hwmtx);
+ return (error);
+}
+
+
+static int
+oct16550_bus_ipend(struct uart_softc *sc)
+{
+ struct uart_bas *bas;
+ int ipend = 0;
+ uint8_t iir, lsr;
+
+ bas = &sc->sc_bas;
+ uart_lock(sc->sc_hwmtx);
+
+ iir = uart_getreg(bas, REG_IIR) & IIR_IMASK;
+ if (iir != IIR_NOPEND) {
+
+ if (iir == IIR_RLS) {
+ lsr = uart_getreg(bas, REG_LSR);
+ if (lsr & LSR_OE)
+ ipend |= SER_INT_OVERRUN;
+ if (lsr & LSR_BI)
+ ipend |= SER_INT_BREAK;
+ if (lsr & LSR_RXRDY)
+ ipend |= SER_INT_RXREADY;
+
+ } else if (iir == IIR_RXRDY) {
+ ipend |= SER_INT_RXREADY;
+
+ } else if (iir == IIR_RXTOUT) {
+ ipend |= SER_INT_RXREADY;
+
+ } else if (iir == IIR_TXRDY) {
+ ipend |= SER_INT_TXIDLE;
+
+ } else if (iir == IIR_MLSC) {
+ ipend |= SER_INT_SIGCHG;
+
+ } else if (iir == IIR_BUSY) {
+ (void) uart_getreg(bas, REG_USR);
+ }
+ }
+ uart_unlock(sc->sc_hwmtx);
+
+ return (ipend);
+}
+
+static int
+oct16550_bus_param (struct uart_softc *sc, int baudrate, int databits,
+ int stopbits, int parity)
+{
+ struct uart_bas *bas;
+ int error;
+
+ bas = &sc->sc_bas;
+ uart_lock(sc->sc_hwmtx);
+ error = oct16550_param(bas, baudrate, databits, stopbits, parity);
+ uart_unlock(sc->sc_hwmtx);
+ return (error);
+}
+
+static int
+oct16550_bus_probe (struct uart_softc *sc)
+{
+ struct uart_bas *bas;
+ int error;
+
+ bas = &sc->sc_bas;
+ bas->rclk = uart_oct16550_class.uc_rclk = cvmx_clock_get_rate(CVMX_CLOCK_SCLK);
+
+ error = oct16550_probe(bas);
+ if (error) {
+ return (error);
+ }
+
+ uart_setreg(bas, REG_MCR, (MCR_DTR | MCR_RTS));
+
+ /*
+ * Enable FIFOs. And check that the UART has them. If not, we're
+ * done. Since this is the first time we enable the FIFOs, we reset
+ * them.
+ */
+ oct16550_drain(bas, UART_DRAIN_TRANSMITTER);
+#define ENABLE_OCTEON_FIFO 1
+#ifdef ENABLE_OCTEON_FIFO
+ uart_setreg(bas, REG_FCR, FCR_ENABLE | FCR_XMT_RST | FCR_RCV_RST);
+#endif
+ uart_barrier(bas);
+
+ oct16550_flush(bas, UART_FLUSH_RECEIVER|UART_FLUSH_TRANSMITTER);
+
+ if (device_get_unit(sc->sc_dev)) {
+ device_set_desc(sc->sc_dev, "Octeon-16550 channel 1");
+ } else {
+ device_set_desc(sc->sc_dev, "Octeon-16550 channel 0");
+ }
+#ifdef ENABLE_OCTEON_FIFO
+ sc->sc_rxfifosz = 64;
+ sc->sc_txfifosz = 64;
+#else
+ sc->sc_rxfifosz = 1;
+ sc->sc_txfifosz = 1;
+#endif
+
+
+#if 0
+ /*
+ * XXX there are some issues related to hardware flow control and
+ * it's likely that uart(4) is the cause. This basicly needs more
+ * investigation, but we avoid using for hardware flow control
+ * until then.
+ */
+ /* 16650s or higher have automatic flow control. */
+ if (sc->sc_rxfifosz > 16) {
+ sc->sc_hwiflow = 1;
+ sc->sc_hwoflow = 1;
+ }
+#endif
+
+ return (0);
+}
+
+static int
+oct16550_bus_receive (struct uart_softc *sc)
+{
+ struct uart_bas *bas;
+ int xc;
+ uint8_t lsr;
+
+ bas = &sc->sc_bas;
+ uart_lock(sc->sc_hwmtx);
+ lsr = uart_getreg(bas, REG_LSR);
+
+ while (lsr & LSR_RXRDY) {
+ if (uart_rx_full(sc)) {
+ sc->sc_rxbuf[sc->sc_rxput] = UART_STAT_OVERRUN;
+ break;
+ }
+ xc = uart_getreg(bas, REG_DATA);
+ if (lsr & LSR_FE)
+ xc |= UART_STAT_FRAMERR;
+ if (lsr & LSR_PE)
+ xc |= UART_STAT_PARERR;
+ uart_rx_put(sc, xc);
+ lsr = uart_getreg(bas, REG_LSR);
+ }
+ /* Discard everything left in the Rx FIFO. */
+ /*
+ * First do a dummy read/discard anyway, in case the UART was lying to us.
+ * This problem was seen on board, when IIR said RBR, but LSR said no RXRDY
+ * Results in a stuck ipend loop.
+ */
+ (void)uart_getreg(bas, REG_DATA);
+ while (lsr & LSR_RXRDY) {
+ (void)uart_getreg(bas, REG_DATA);
+ uart_barrier(bas);
+ lsr = uart_getreg(bas, REG_LSR);
+ }
+ uart_unlock(sc->sc_hwmtx);
+ return (0);
+}
+
+static int
+oct16550_bus_setsig (struct uart_softc *sc, int sig)
+{
+ struct oct16550_softc *oct16550 = (struct oct16550_softc*)sc;
+ struct uart_bas *bas;
+ uint32_t new, old;
+
+ bas = &sc->sc_bas;
+ do {
+ old = sc->sc_hwsig;
+ new = old;
+ if (sig & SER_DDTR) {
+ SIGCHG(sig & SER_DTR, new, SER_DTR,
+ SER_DDTR);
+ }
+ if (sig & SER_DRTS) {
+ SIGCHG(sig & SER_RTS, new, SER_RTS,
+ SER_DRTS);
+ }
+ } while (!atomic_cmpset_32(&sc->sc_hwsig, old, new));
+ uart_lock(sc->sc_hwmtx);
+ oct16550->mcr &= ~(MCR_DTR|MCR_RTS);
+ if (new & SER_DTR)
+ oct16550->mcr |= MCR_DTR;
+ if (new & SER_RTS)
+ oct16550->mcr |= MCR_RTS;
+ uart_setreg(bas, REG_MCR, oct16550->mcr);
+ uart_barrier(bas);
+ uart_unlock(sc->sc_hwmtx);
+ return (0);
+}
+
+static int
+oct16550_bus_transmit (struct uart_softc *sc)
+{
+ struct oct16550_softc *oct16550 = (struct oct16550_softc*)sc;
+ struct uart_bas *bas;
+ int i;
+
+ bas = &sc->sc_bas;
+ uart_lock(sc->sc_hwmtx);
+#ifdef NO_UART_INTERRUPTS
+ for (i = 0; i < sc->sc_txdatasz; i++) {
+ oct16550_putc(bas, sc->sc_txbuf[i]);
+ }
+#else
+
+ oct16550_wait_txhr_empty(bas, 100, oct16550_delay(bas));
+ uart_setreg(bas, REG_IER, oct16550->ier | IER_ETXRDY);
+ uart_barrier(bas);
+
+ for (i = 0; i < sc->sc_txdatasz; i++) {
+ uart_setreg(bas, REG_DATA, sc->sc_txbuf[i]);
+ uart_barrier(bas);
+ }
+ sc->sc_txbusy = 1;
+#endif
+ uart_unlock(sc->sc_hwmtx);
+ return (0);
+}
+
+static void
+oct16550_bus_grab(struct uart_softc *sc)
+{
+ struct uart_bas *bas = &sc->sc_bas;
+
+ /*
+ * turn off all interrupts to enter polling mode. Leave the
+ * saved mask alone. We'll restore whatever it was in ungrab.
+ * All pending interupt signals are reset when IER is set to 0.
+ */
+ uart_lock(sc->sc_hwmtx);
+ uart_setreg(bas, REG_IER, 0);
+ uart_barrier(bas);
+ uart_unlock(sc->sc_hwmtx);
+}
+
+static void
+oct16550_bus_ungrab(struct uart_softc *sc)
+{
+ struct oct16550_softc *oct16550 = (struct oct16550_softc*)sc;
+ struct uart_bas *bas = &sc->sc_bas;
+
+ /*
+ * Restore previous interrupt mask
+ */
+ uart_lock(sc->sc_hwmtx);
+ uart_setreg(bas, REG_IER, oct16550->ier);
+ uart_barrier(bas);
+ uart_unlock(sc->sc_hwmtx);
+}
Property changes on: trunk/sys/mips/cavium/uart_dev_oct16550.c
___________________________________________________________________
Added: svn:eol-style
## -0,0 +1 ##
+native
\ No newline at end of property
Added: svn:keywords
## -0,0 +1 ##
+MidnightBSD=%H
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+text/plain
\ No newline at end of property
Added: trunk/sys/mips/cavium/usb/octusb.c
===================================================================
--- trunk/sys/mips/cavium/usb/octusb.c (rev 0)
+++ trunk/sys/mips/cavium/usb/octusb.c 2018-05-26 21:55:02 UTC (rev 9987)
@@ -0,0 +1,1948 @@
+/* $MidnightBSD$ */
+#include <sys/cdefs.h>
+__FBSDID("$FreeBSD: stable/10/sys/mips/cavium/usb/octusb.c 241082 2012-10-01 05:42:43Z hselasky $");
+
+/*-
+ * Copyright (c) 2010 Hans Petter Selasky. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ */
+
+/*
+ * This file contains the driver for Octeon Executive Library USB
+ * Controller driver API.
+ */
+
+/* TODO: The root HUB port callback is not yet implemented. */
+
+#include <sys/stdint.h>
+#include <sys/stddef.h>
+#include <sys/param.h>
+#include <sys/queue.h>
+#include <sys/types.h>
+#include <sys/systm.h>
+#include <sys/kernel.h>
+#include <sys/bus.h>
+#include <sys/module.h>
+#include <sys/lock.h>
+#include <sys/mutex.h>
+#include <sys/condvar.h>
+#include <sys/sysctl.h>
+#include <sys/sx.h>
+#include <sys/unistd.h>
+#include <sys/callout.h>
+#include <sys/malloc.h>
+#include <sys/priv.h>
+
+#include <dev/usb/usb.h>
+#include <dev/usb/usbdi.h>
+
+#define USB_DEBUG_VAR octusbdebug
+
+#include <dev/usb/usb_core.h>
+#include <dev/usb/usb_debug.h>
+#include <dev/usb/usb_busdma.h>
+#include <dev/usb/usb_process.h>
+#include <dev/usb/usb_transfer.h>
+#include <dev/usb/usb_device.h>
+#include <dev/usb/usb_hub.h>
+#include <dev/usb/usb_util.h>
+
+#include <dev/usb/usb_controller.h>
+#include <dev/usb/usb_bus.h>
+
+#include <contrib/octeon-sdk/cvmx.h>
+#include <contrib/octeon-sdk/cvmx-usb.h>
+
+#include <mips/cavium/usb/octusb.h>
+
+#define OCTUSB_BUS2SC(bus) \
+ ((struct octusb_softc *)(((uint8_t *)(bus)) - \
+ ((uint8_t *)&(((struct octusb_softc *)0)->sc_bus))))
+
+#ifdef USB_DEBUG
+static int octusbdebug = 0;
+
+static SYSCTL_NODE(_hw_usb, OID_AUTO, octusb, CTLFLAG_RW, 0, "OCTUSB");
+SYSCTL_INT(_hw_usb_octusb, OID_AUTO, debug, CTLFLAG_RW,
+ &octusbdebug, 0, "OCTUSB debug level");
+
+TUNABLE_INT("hw.usb.octusb.debug", &octusbdebug);
+
+#endif
+
+struct octusb_std_temp {
+ octusb_cmd_t *func;
+ struct octusb_td *td;
+ struct octusb_td *td_next;
+ struct usb_page_cache *pc;
+ uint32_t offset;
+ uint32_t len;
+ uint8_t short_pkt;
+ uint8_t setup_alt_next;
+};
+
+extern struct usb_bus_methods octusb_bus_methods;
+extern struct usb_pipe_methods octusb_device_bulk_methods;
+extern struct usb_pipe_methods octusb_device_ctrl_methods;
+extern struct usb_pipe_methods octusb_device_intr_methods;
+extern struct usb_pipe_methods octusb_device_isoc_methods;
+
+static void octusb_standard_done(struct usb_xfer *);
+static void octusb_device_done(struct usb_xfer *, usb_error_t);
+static void octusb_timeout(void *);
+static void octusb_do_poll(struct usb_bus *);
+
+static cvmx_usb_speed_t
+octusb_convert_speed(enum usb_dev_speed speed)
+{
+ ; /* indent fix */
+ switch (speed) {
+ case USB_SPEED_HIGH:
+ return (CVMX_USB_SPEED_HIGH);
+ case USB_SPEED_FULL:
+ return (CVMX_USB_SPEED_FULL);
+ default:
+ return (CVMX_USB_SPEED_LOW);
+ }
+}
+
+static cvmx_usb_transfer_t
+octusb_convert_ep_type(uint8_t ep_type)
+{
+ ; /* indent fix */
+ switch (ep_type & UE_XFERTYPE) {
+ case UE_CONTROL:
+ return (CVMX_USB_TRANSFER_CONTROL);
+ case UE_INTERRUPT:
+ return (CVMX_USB_TRANSFER_INTERRUPT);
+ case UE_ISOCHRONOUS:
+ return (CVMX_USB_TRANSFER_ISOCHRONOUS);
+ case UE_BULK:
+ return (CVMX_USB_TRANSFER_BULK);
+ default:
+ return (0); /* should not happen */
+ }
+}
+
+static uint8_t
+octusb_host_alloc_endpoint(struct octusb_td *td)
+{
+ struct octusb_softc *sc;
+ int ep_handle;
+
+ if (td->qh->fixup_pending)
+ return (1); /* busy */
+
+ if (td->qh->ep_allocated)
+ return (0); /* success */
+
+ /* get softc */
+ sc = td->qh->sc;
+
+ ep_handle = cvmx_usb_open_pipe(
+ &sc->sc_port[td->qh->root_port_index].state,
+ 0,
+ td->qh->dev_addr,
+ td->qh->ep_num & UE_ADDR,
+ octusb_convert_speed(td->qh->dev_speed),
+ td->qh->max_packet_size,
+ octusb_convert_ep_type(td->qh->ep_type),
+ (td->qh->ep_num & UE_DIR_IN) ? CVMX_USB_DIRECTION_IN :
+ CVMX_USB_DIRECTION_OUT,
+ td->qh->ep_interval,
+ (td->qh->dev_speed == USB_SPEED_HIGH) ? td->qh->ep_mult : 0,
+ td->qh->hs_hub_addr,
+ td->qh->hs_hub_port);
+
+ if (ep_handle < 0) {
+ DPRINTFN(1, "cvmx_usb_open_pipe failed: %d\n", ep_handle);
+ return (1); /* busy */
+ }
+
+ cvmx_usb_set_toggle(
+ &sc->sc_port[td->qh->root_port_index].state,
+ ep_handle, td->qh->ep_toggle_next);
+
+ td->qh->fixup_handle = -1;
+ td->qh->fixup_complete = 0;
+ td->qh->fixup_len = 0;
+ td->qh->fixup_off = 0;
+ td->qh->fixup_pending = 0;
+ td->qh->fixup_actlen = 0;
+
+ td->qh->ep_handle = ep_handle;
+ td->qh->ep_allocated = 1;
+
+ return (0); /* success */
+}
+
+static void
+octusb_host_free_endpoint(struct octusb_td *td)
+{
+ struct octusb_softc *sc;
+
+ if (td->qh->ep_allocated == 0)
+ return;
+
+ /* get softc */
+ sc = td->qh->sc;
+
+ if (td->qh->fixup_handle >= 0) {
+ /* cancel, if any */
+ cvmx_usb_cancel(&sc->sc_port[td->qh->root_port_index].state,
+ td->qh->ep_handle, td->qh->fixup_handle);
+ }
+ cvmx_usb_close_pipe(&sc->sc_port[td->qh->root_port_index].state, td->qh->ep_handle);
+
+ td->qh->ep_allocated = 0;
+}
+
+static void
+octusb_complete_cb(cvmx_usb_state_t *state,
+ cvmx_usb_callback_t reason,
+ cvmx_usb_complete_t status,
+ int pipe_handle, int submit_handle,
+ int bytes_transferred, void *user_data)
+{
+ struct octusb_td *td;
+
+ if (reason != CVMX_USB_CALLBACK_TRANSFER_COMPLETE)
+ return;
+
+ td = user_data;
+
+ td->qh->fixup_complete = 1;
+ td->qh->fixup_pending = 0;
+ td->qh->fixup_actlen = bytes_transferred;
+ td->qh->fixup_handle = -1;
+
+ switch (status) {
+ case CVMX_USB_COMPLETE_SUCCESS:
+ case CVMX_USB_COMPLETE_SHORT:
+ td->error_any = 0;
+ td->error_stall = 0;
+ break;
+ case CVMX_USB_COMPLETE_STALL:
+ td->error_stall = 1;
+ td->error_any = 1;
+ break;
+ default:
+ td->error_any = 1;
+ break;
+ }
+}
+
+static uint8_t
+octusb_host_control_header_tx(struct octusb_td *td)
+{
+ int status;
+
+ /* allocate endpoint and check pending */
+ if (octusb_host_alloc_endpoint(td))
+ return (1); /* busy */
+
+ /* check error */
+ if (td->error_any)
+ return (0); /* done */
+
+ if (td->qh->fixup_complete != 0) {
+ /* clear complete flag */
+ td->qh->fixup_complete = 0;
+
+ /* flush data */
+ usb_pc_cpu_invalidate(td->qh->fixup_pc);
+ return (0); /* done */
+ }
+ /* verify length */
+ if (td->remainder != 8) {
+ td->error_any = 1;
+ return (0); /* done */
+ }
+ usbd_copy_out(td->pc, td->offset, td->qh->fixup_buf, 8);
+
+ /* update offset and remainder */
+ td->offset += 8;
+ td->remainder -= 8;
+
+ /* setup data length and offset */
+ td->qh->fixup_len = UGETW(td->qh->fixup_buf + 6);
+ td->qh->fixup_off = 0;
+
+ if (td->qh->fixup_len > (OCTUSB_MAX_FIXUP - 8)) {
+ td->error_any = 1;
+ return (0); /* done */
+ }
+ /* do control IN request */
+ if (td->qh->fixup_buf[0] & UE_DIR_IN) {
+
+ struct octusb_softc *sc;
+
+ /* get softc */
+ sc = td->qh->sc;
+
+ /* flush data */
+ usb_pc_cpu_flush(td->qh->fixup_pc);
+
+ status = cvmx_usb_submit_control(
+ &sc->sc_port[td->qh->root_port_index].state,
+ td->qh->ep_handle, td->qh->fixup_phys,
+ td->qh->fixup_phys + 8, td->qh->fixup_len,
+ &octusb_complete_cb, td);
+ /* check status */
+ if (status < 0) {
+ td->error_any = 1;
+ return (0); /* done */
+ }
+ td->qh->fixup_handle = status;
+ td->qh->fixup_pending = 1;
+ td->qh->fixup_complete = 0;
+
+ return (1); /* busy */
+ }
+ return (0); /* done */
+}
+
+static uint8_t
+octusb_host_control_data_tx(struct octusb_td *td)
+{
+ uint32_t rem;
+
+ /* allocate endpoint and check pending */
+ if (octusb_host_alloc_endpoint(td))
+ return (1); /* busy */
+
+ /* check error */
+ if (td->error_any)
+ return (0); /* done */
+
+ rem = td->qh->fixup_len - td->qh->fixup_off;
+
+ if (td->remainder > rem) {
+ td->error_any = 1;
+ DPRINTFN(1, "Excess setup transmit data\n");
+ return (0); /* done */
+ }
+ usbd_copy_out(td->pc, td->offset, td->qh->fixup_buf +
+ td->qh->fixup_off + 8, td->remainder);
+
+ td->offset += td->remainder;
+ td->qh->fixup_off += td->remainder;
+ td->remainder = 0;
+
+ return (0); /* done */
+}
+
+static uint8_t
+octusb_host_control_data_rx(struct octusb_td *td)
+{
+ uint32_t rem;
+
+ /* allocate endpoint and check pending */
+ if (octusb_host_alloc_endpoint(td))
+ return (1); /* busy */
+
+ /* check error */
+ if (td->error_any)
+ return (0); /* done */
+
+ /* copy data from buffer */
+ rem = td->qh->fixup_actlen - td->qh->fixup_off;
+
+ if (rem > td->remainder)
+ rem = td->remainder;
+
+ usbd_copy_in(td->pc, td->offset, td->qh->fixup_buf +
+ td->qh->fixup_off + 8, rem);
+
+ td->offset += rem;
+ td->remainder -= rem;
+ td->qh->fixup_off += rem;
+
+ return (0); /* done */
+}
+
+static uint8_t
+octusb_host_control_status_tx(struct octusb_td *td)
+{
+ int status;
+
+ /* allocate endpoint and check pending */
+ if (octusb_host_alloc_endpoint(td))
+ return (1); /* busy */
+
+ /* check error */
+ if (td->error_any)
+ return (0); /* done */
+
+ if (td->qh->fixup_complete != 0) {
+ /* clear complete flag */
+ td->qh->fixup_complete = 0;
+ /* done */
+ return (0);
+ }
+ /* do control IN request */
+ if (!(td->qh->fixup_buf[0] & UE_DIR_IN)) {
+
+ struct octusb_softc *sc;
+
+ /* get softc */
+ sc = td->qh->sc;
+
+ /* flush data */
+ usb_pc_cpu_flush(td->qh->fixup_pc);
+
+ /* start USB transfer */
+ status = cvmx_usb_submit_control(
+ &sc->sc_port[td->qh->root_port_index].state,
+ td->qh->ep_handle, td->qh->fixup_phys,
+ td->qh->fixup_phys + 8, td->qh->fixup_len,
+ &octusb_complete_cb, td);
+
+ /* check status */
+ if (status < 0) {
+ td->error_any = 1;
+ return (0); /* done */
+ }
+ td->qh->fixup_handle = status;
+ td->qh->fixup_pending = 1;
+ td->qh->fixup_complete = 0;
+
+ return (1); /* busy */
+ }
+ return (0); /* done */
+}
+
+static uint8_t
+octusb_non_control_data_tx(struct octusb_td *td)
+{
+ struct octusb_softc *sc;
+ uint32_t rem;
+ int status;
+
+ /* allocate endpoint and check pending */
+ if (octusb_host_alloc_endpoint(td))
+ return (1); /* busy */
+
+ /* check error */
+ if (td->error_any)
+ return (0); /* done */
+
+ if ((td->qh->fixup_complete != 0) &&
+ ((td->qh->ep_type & UE_XFERTYPE) == UE_ISOCHRONOUS)) {
+ td->qh->fixup_complete = 0;
+ return (0); /* done */
+ }
+ /* check complete */
+ if (td->remainder == 0) {
+ if (td->short_pkt)
+ return (0); /* complete */
+ /* else need to send a zero length packet */
+ rem = 0;
+ td->short_pkt = 1;
+ } else {
+ /* get maximum length */
+ rem = OCTUSB_MAX_FIXUP % td->qh->max_frame_size;
+ rem = OCTUSB_MAX_FIXUP - rem;
+
+ if (rem == 0) {
+ /* should not happen */
+ DPRINTFN(1, "Fixup buffer is too small\n");
+ td->error_any = 1;
+ return (0); /* done */
+ }
+ /* get minimum length */
+ if (rem > td->remainder) {
+ rem = td->remainder;
+ if ((rem == 0) || (rem % td->qh->max_frame_size))
+ td->short_pkt = 1;
+ }
+ /* copy data into fixup buffer */
+ usbd_copy_out(td->pc, td->offset, td->qh->fixup_buf, rem);
+
+ /* flush data */
+ usb_pc_cpu_flush(td->qh->fixup_pc);
+
+ /* pre-increment TX buffer offset */
+ td->offset += rem;
+ td->remainder -= rem;
+ }
+
+ /* get softc */
+ sc = td->qh->sc;
+
+ switch (td->qh->ep_type & UE_XFERTYPE) {
+ case UE_ISOCHRONOUS:
+ td->qh->iso_pkt.offset = 0;
+ td->qh->iso_pkt.length = rem;
+ td->qh->iso_pkt.status = 0;
+ /* start USB transfer */
+ status = cvmx_usb_submit_isochronous(&sc->sc_port[td->qh->root_port_index].state,
+ td->qh->ep_handle, 1, CVMX_USB_ISOCHRONOUS_FLAGS_ALLOW_SHORT |
+ CVMX_USB_ISOCHRONOUS_FLAGS_ASAP, 1, &td->qh->iso_pkt,
+ td->qh->fixup_phys, rem, &octusb_complete_cb, td);
+ break;
+ case UE_BULK:
+ /* start USB transfer */
+ status = cvmx_usb_submit_bulk(&sc->sc_port[td->qh->root_port_index].state,
+ td->qh->ep_handle, td->qh->fixup_phys, rem, &octusb_complete_cb, td);
+ break;
+ case UE_INTERRUPT:
+ /* start USB transfer (interrupt or interrupt) */
+ status = cvmx_usb_submit_interrupt(&sc->sc_port[td->qh->root_port_index].state,
+ td->qh->ep_handle, td->qh->fixup_phys, rem, &octusb_complete_cb, td);
+ break;
+ default:
+ status = -1;
+ break;
+ }
+
+ /* check status */
+ if (status < 0) {
+ td->error_any = 1;
+ return (0); /* done */
+ }
+ td->qh->fixup_handle = status;
+ td->qh->fixup_len = rem;
+ td->qh->fixup_pending = 1;
+ td->qh->fixup_complete = 0;
+
+ return (1); /* busy */
+}
+
+static uint8_t
+octusb_non_control_data_rx(struct octusb_td *td)
+{
+ struct octusb_softc *sc;
+ uint32_t rem;
+ int status;
+ uint8_t got_short;
+
+ /* allocate endpoint and check pending */
+ if (octusb_host_alloc_endpoint(td))
+ return (1); /* busy */
+
+ /* check error */
+ if (td->error_any)
+ return (0); /* done */
+
+ got_short = 0;
+
+ if (td->qh->fixup_complete != 0) {
+
+ /* invalidate data */
+ usb_pc_cpu_invalidate(td->qh->fixup_pc);
+
+ rem = td->qh->fixup_actlen;
+
+ /* verify transfer length */
+ if (rem != td->qh->fixup_len) {
+ if (rem < td->qh->fixup_len) {
+ /* we have a short packet */
+ td->short_pkt = 1;
+ got_short = 1;
+ } else {
+ /* invalid USB packet */
+ td->error_any = 1;
+ return (0); /* we are complete */
+ }
+ }
+ /* copy data into fixup buffer */
+ usbd_copy_in(td->pc, td->offset, td->qh->fixup_buf, rem);
+
+ /* post-increment RX buffer offset */
+ td->offset += rem;
+ td->remainder -= rem;
+
+ td->qh->fixup_complete = 0;
+
+ if ((td->qh->ep_type & UE_XFERTYPE) == UE_ISOCHRONOUS)
+ return (0); /* done */
+ }
+ /* check if we are complete */
+ if ((td->remainder == 0) || got_short) {
+ if (td->short_pkt) {
+ /* we are complete */
+ return (0);
+ }
+ /* else need to receive a zero length packet */
+ rem = 0;
+ td->short_pkt = 1;
+ } else {
+ /* get maximum length */
+ rem = OCTUSB_MAX_FIXUP % td->qh->max_frame_size;
+ rem = OCTUSB_MAX_FIXUP - rem;
+
+ if (rem == 0) {
+ /* should not happen */
+ DPRINTFN(1, "Fixup buffer is too small\n");
+ td->error_any = 1;
+ return (0); /* done */
+ }
+ /* get minimum length */
+ if (rem > td->remainder)
+ rem = td->remainder;
+ }
+
+ /* invalidate data */
+ usb_pc_cpu_invalidate(td->qh->fixup_pc);
+
+ /* get softc */
+ sc = td->qh->sc;
+
+ switch (td->qh->ep_type & UE_XFERTYPE) {
+ case UE_ISOCHRONOUS:
+ td->qh->iso_pkt.offset = 0;
+ td->qh->iso_pkt.length = rem;
+ td->qh->iso_pkt.status = 0;
+ /* start USB transfer */
+ status = cvmx_usb_submit_isochronous(&sc->sc_port[td->qh->root_port_index].state,
+ td->qh->ep_handle, 1, CVMX_USB_ISOCHRONOUS_FLAGS_ALLOW_SHORT |
+ CVMX_USB_ISOCHRONOUS_FLAGS_ASAP, 1, &td->qh->iso_pkt,
+ td->qh->fixup_phys, rem, &octusb_complete_cb, td);
+ break;
+ case UE_BULK:
+ /* start USB transfer */
+ status = cvmx_usb_submit_bulk(&sc->sc_port[td->qh->root_port_index].state,
+ td->qh->ep_handle, td->qh->fixup_phys, rem, &octusb_complete_cb, td);
+ break;
+ case UE_INTERRUPT:
+ /* start USB transfer */
+ status = cvmx_usb_submit_interrupt(&sc->sc_port[td->qh->root_port_index].state,
+ td->qh->ep_handle, td->qh->fixup_phys, rem, &octusb_complete_cb, td);
+ break;
+ default:
+ status = -1;
+ break;
+ }
+
+ /* check status */
+ if (status < 0) {
+ td->error_any = 1;
+ return (0); /* done */
+ }
+ td->qh->fixup_handle = status;
+ td->qh->fixup_len = rem;
+ td->qh->fixup_pending = 1;
+ td->qh->fixup_complete = 0;
+
+ return (1); /* busy */
+}
+
+static uint8_t
+octusb_xfer_do_fifo(struct usb_xfer *xfer)
+{
+ struct octusb_td *td;
+
+ DPRINTFN(8, "\n");
+
+ td = xfer->td_transfer_cache;
+
+ while (1) {
+ if ((td->func) (td)) {
+ /* operation in progress */
+ break;
+ }
+ if (((void *)td) == xfer->td_transfer_last) {
+ goto done;
+ }
+ if (td->error_any) {
+ goto done;
+ } else if (td->remainder > 0) {
+ /*
+ * We had a short transfer. If there is no
+ * alternate next, stop processing !
+ */
+ if (td->alt_next == 0)
+ goto done;
+ }
+ /*
+ * Fetch the next transfer descriptor and transfer
+ * some flags to the next transfer descriptor
+ */
+ td = td->obj_next;
+ xfer->td_transfer_cache = td;
+ }
+ return (1); /* not complete */
+
+done:
+ /* compute all actual lengths */
+
+ octusb_standard_done(xfer);
+
+ return (0); /* complete */
+}
+
+static usb_error_t
+octusb_standard_done_sub(struct usb_xfer *xfer)
+{
+ struct octusb_td *td;
+ uint32_t len;
+ usb_error_t error;
+
+ DPRINTFN(8, "\n");
+
+ td = xfer->td_transfer_cache;
+
+ do {
+ len = td->remainder;
+
+ if (xfer->aframes != xfer->nframes) {
+ /*
+ * Verify the length and subtract
+ * the remainder from "frlengths[]":
+ */
+ if (len > xfer->frlengths[xfer->aframes]) {
+ td->error_any = 1;
+ } else {
+ xfer->frlengths[xfer->aframes] -= len;
+ }
+ }
+ /* Check for transfer error */
+ if (td->error_any) {
+ /* the transfer is finished */
+ error = td->error_stall ? USB_ERR_STALLED : USB_ERR_IOERROR;
+ td = NULL;
+ break;
+ }
+ /* Check for short transfer */
+ if (len > 0) {
+ if (xfer->flags_int.short_frames_ok) {
+ /* follow alt next */
+ if (td->alt_next) {
+ td = td->obj_next;
+ } else {
+ td = NULL;
+ }
+ } else {
+ /* the transfer is finished */
+ td = NULL;
+ }
+ error = 0;
+ break;
+ }
+ td = td->obj_next;
+
+ /* this USB frame is complete */
+ error = 0;
+ break;
+
+ } while (0);
+
+ /* update transfer cache */
+
+ xfer->td_transfer_cache = td;
+
+ return (error);
+}
+
+static void
+octusb_standard_done(struct usb_xfer *xfer)
+{
+ struct octusb_softc *sc;
+ struct octusb_qh *qh;
+ usb_error_t error = 0;
+
+ DPRINTFN(12, "xfer=%p endpoint=%p transfer done\n",
+ xfer, xfer->endpoint);
+
+ /* reset scanner */
+
+ xfer->td_transfer_cache = xfer->td_transfer_first;
+
+ if (xfer->flags_int.control_xfr) {
+
+ if (xfer->flags_int.control_hdr)
+ error = octusb_standard_done_sub(xfer);
+
+ xfer->aframes = 1;
+
+ if (xfer->td_transfer_cache == NULL)
+ goto done;
+ }
+ while (xfer->aframes != xfer->nframes) {
+
+ error = octusb_standard_done_sub(xfer);
+
+ xfer->aframes++;
+
+ if (xfer->td_transfer_cache == NULL)
+ goto done;
+ }
+
+ if (xfer->flags_int.control_xfr &&
+ !xfer->flags_int.control_act)
+ error = octusb_standard_done_sub(xfer);
+
+done:
+ /* update data toggle */
+
+ qh = xfer->qh_start[0];
+ sc = qh->sc;
+
+ xfer->endpoint->toggle_next =
+ cvmx_usb_get_toggle(
+ &sc->sc_port[qh->root_port_index].state,
+ qh->ep_handle) ? 1 : 0;
+
+ octusb_device_done(xfer, error);
+}
+
+static void
+octusb_interrupt_poll(struct octusb_softc *sc)
+{
+ struct usb_xfer *xfer;
+ uint8_t x;
+
+ /* poll all ports */
+ for (x = 0; x != sc->sc_noport; x++)
+ cvmx_usb_poll(&sc->sc_port[x].state);
+
+repeat:
+ TAILQ_FOREACH(xfer, &sc->sc_bus.intr_q.head, wait_entry) {
+ if (!octusb_xfer_do_fifo(xfer)) {
+ /* queue has been modified */
+ goto repeat;
+ }
+ }
+}
+
+static void
+octusb_start_standard_chain(struct usb_xfer *xfer)
+{
+ DPRINTFN(8, "\n");
+
+ /* poll one time */
+ if (octusb_xfer_do_fifo(xfer)) {
+
+ /* put transfer on interrupt queue */
+ usbd_transfer_enqueue(&xfer->xroot->bus->intr_q, xfer);
+
+ /* start timeout, if any */
+ if (xfer->timeout != 0) {
+ usbd_transfer_timeout_ms(xfer,
+ &octusb_timeout, xfer->timeout);
+ }
+ }
+}
+
+void
+octusb_iterate_hw_softc(struct usb_bus *bus, usb_bus_mem_sub_cb_t *cb)
+{
+
+}
+
+usb_error_t
+octusb_init(struct octusb_softc *sc)
+{
+ cvmx_usb_initialize_flags_t flags;
+ int status;
+ uint8_t x;
+
+ /* flush all cache into memory */
+
+ usb_bus_mem_flush_all(&sc->sc_bus, &octusb_iterate_hw_softc);
+
+ /* set up the bus struct */
+ sc->sc_bus.methods = &octusb_bus_methods;
+
+ /* get number of ports */
+ sc->sc_noport = cvmx_usb_get_num_ports();
+
+ /* check number of ports */
+ if (sc->sc_noport > OCTUSB_MAX_PORTS)
+ sc->sc_noport = OCTUSB_MAX_PORTS;
+
+ /* set USB revision */
+ sc->sc_bus.usbrev = USB_REV_2_0;
+
+ /* flags for port initialization */
+ flags = CVMX_USB_INITIALIZE_FLAGS_CLOCK_AUTO;
+#ifdef USB_DEBUG
+ if (octusbdebug > 100)
+ flags |= CVMX_USB_INITIALIZE_FLAGS_DEBUG_ALL;
+#endif
+
+ USB_BUS_LOCK(&sc->sc_bus);
+
+ /* setup all ports */
+ for (x = 0; x != sc->sc_noport; x++) {
+ status = cvmx_usb_initialize(&sc->sc_port[x].state, x, flags);
+ if (status < 0)
+ sc->sc_port[x].disabled = 1;
+ }
+
+ USB_BUS_UNLOCK(&sc->sc_bus);
+
+ /* catch lost interrupts */
+ octusb_do_poll(&sc->sc_bus);
+
+ return (0);
+}
+
+usb_error_t
+octusb_uninit(struct octusb_softc *sc)
+{
+ uint8_t x;
+
+ USB_BUS_LOCK(&sc->sc_bus);
+
+ for (x = 0; x != sc->sc_noport; x++) {
+ if (sc->sc_port[x].disabled == 0)
+ cvmx_usb_shutdown(&sc->sc_port[x].state);
+ }
+ USB_BUS_UNLOCK(&sc->sc_bus);
+
+ return (0);
+
+}
+
+static void
+octusb_suspend(struct octusb_softc *sc)
+{
+ /* TODO */
+}
+
+static void
+octusb_resume(struct octusb_softc *sc)
+{
+ /* TODO */
+}
+
+/*------------------------------------------------------------------------*
+ * octusb_interrupt - OCTUSB interrupt handler
+ *------------------------------------------------------------------------*/
+void
+octusb_interrupt(struct octusb_softc *sc)
+{
+ USB_BUS_LOCK(&sc->sc_bus);
+
+ DPRINTFN(16, "real interrupt\n");
+
+ /* poll all the USB transfers */
+ octusb_interrupt_poll(sc);
+
+ USB_BUS_UNLOCK(&sc->sc_bus);
+}
+
+/*------------------------------------------------------------------------*
+ * octusb_timeout - OCTUSB transfer timeout handler
+ *------------------------------------------------------------------------*/
+static void
+octusb_timeout(void *arg)
+{
+ struct usb_xfer *xfer = arg;
+
+ DPRINTF("xfer=%p\n", xfer);
+
+ USB_BUS_LOCK_ASSERT(xfer->xroot->bus, MA_OWNED);
+
+ /* transfer is transferred */
+ octusb_device_done(xfer, USB_ERR_TIMEOUT);
+}
+
+/*------------------------------------------------------------------------*
+ * octusb_do_poll - OCTUSB poll transfers
+ *------------------------------------------------------------------------*/
+static void
+octusb_do_poll(struct usb_bus *bus)
+{
+ struct octusb_softc *sc = OCTUSB_BUS2SC(bus);
+
+ USB_BUS_LOCK(&sc->sc_bus);
+ octusb_interrupt_poll(sc);
+ USB_BUS_UNLOCK(&sc->sc_bus);
+}
+
+static void
+octusb_setup_standard_chain_sub(struct octusb_std_temp *temp)
+{
+ struct octusb_td *td;
+
+ /* get current Transfer Descriptor */
+ td = temp->td_next;
+ temp->td = td;
+
+ /* prepare for next TD */
+ temp->td_next = td->obj_next;
+
+ /* fill out the Transfer Descriptor */
+ td->func = temp->func;
+ td->pc = temp->pc;
+ td->offset = temp->offset;
+ td->remainder = temp->len;
+ td->error_any = 0;
+ td->error_stall = 0;
+ td->short_pkt = temp->short_pkt;
+ td->alt_next = temp->setup_alt_next;
+}
+
+static void
+octusb_setup_standard_chain(struct usb_xfer *xfer)
+{
+ struct octusb_std_temp temp;
+ struct octusb_td *td;
+ uint32_t x;
+
+ DPRINTFN(9, "addr=%d endpt=%d sumlen=%d speed=%d\n",
+ xfer->address, UE_GET_ADDR(xfer->endpointno),
+ xfer->sumlen, usbd_get_speed(xfer->xroot->udev));
+
+ /* setup starting point */
+ td = xfer->td_start[0];
+ xfer->td_transfer_first = td;
+ xfer->td_transfer_cache = td;
+
+ temp.td = NULL;
+ temp.td_next = td;
+ temp.setup_alt_next = xfer->flags_int.short_frames_ok;
+ temp.offset = 0;
+
+ /* check if we should prepend a setup message */
+
+ if (xfer->flags_int.control_xfr) {
+
+ if (xfer->flags_int.control_hdr) {
+
+ temp.func = &octusb_host_control_header_tx;
+ temp.len = xfer->frlengths[0];
+ temp.pc = xfer->frbuffers + 0;
+ temp.short_pkt = temp.len ? 1 : 0;
+
+ /* check for last frame */
+ if (xfer->nframes == 1) {
+ /*
+ * no STATUS stage yet, SETUP is
+ * last
+ */
+ if (xfer->flags_int.control_act)
+ temp.setup_alt_next = 0;
+ }
+ octusb_setup_standard_chain_sub(&temp);
+ }
+ x = 1;
+ } else {
+ x = 0;
+ }
+
+ if (x != xfer->nframes) {
+ if (xfer->endpointno & UE_DIR_IN) {
+ if (xfer->flags_int.control_xfr)
+ temp.func = &octusb_host_control_data_rx;
+ else
+ temp.func = &octusb_non_control_data_rx;
+ } else {
+ if (xfer->flags_int.control_xfr)
+ temp.func = &octusb_host_control_data_tx;
+ else
+ temp.func = &octusb_non_control_data_tx;
+ }
+
+ /* setup "pc" pointer */
+ temp.pc = xfer->frbuffers + x;
+ }
+ while (x != xfer->nframes) {
+
+ /* DATA0 or DATA1 message */
+
+ temp.len = xfer->frlengths[x];
+
+ x++;
+
+ if (x == xfer->nframes) {
+ if (xfer->flags_int.control_xfr) {
+ /* no STATUS stage yet, DATA is last */
+ if (xfer->flags_int.control_act)
+ temp.setup_alt_next = 0;
+ } else {
+ temp.setup_alt_next = 0;
+ }
+ }
+ if (temp.len == 0) {
+
+ /* make sure that we send an USB packet */
+
+ temp.short_pkt = 0;
+
+ } else {
+
+ /* regular data transfer */
+
+ temp.short_pkt = (xfer->flags.force_short_xfer) ? 0 : 1;
+ }
+
+ octusb_setup_standard_chain_sub(&temp);
+
+ if (xfer->flags_int.isochronous_xfr) {
+ /* get next data offset */
+ temp.offset += temp.len;
+ } else {
+ /* get next Page Cache pointer */
+ temp.pc = xfer->frbuffers + x;
+ }
+ }
+
+ /* check if we should append a status stage */
+
+ if (xfer->flags_int.control_xfr &&
+ !xfer->flags_int.control_act) {
+
+ temp.func = &octusb_host_control_status_tx;
+ temp.len = 0;
+ temp.pc = NULL;
+ temp.short_pkt = 0;
+ temp.setup_alt_next = 0;
+
+ octusb_setup_standard_chain_sub(&temp);
+ }
+ /* must have at least one frame! */
+ td = temp.td;
+ xfer->td_transfer_last = td;
+
+ /* properly setup QH */
+
+ td->qh->ep_allocated = 0;
+ td->qh->ep_toggle_next = xfer->endpoint->toggle_next ? 1 : 0;
+}
+
+/*------------------------------------------------------------------------*
+ * octusb_device_done - OCTUSB transfers done code
+ *
+ * NOTE: This function can be called more than one time in a row.
+ *------------------------------------------------------------------------*/
+static void
+octusb_device_done(struct usb_xfer *xfer, usb_error_t error)
+{
+ USB_BUS_LOCK_ASSERT(xfer->xroot->bus, MA_OWNED);
+
+ DPRINTFN(2, "xfer=%p, endpoint=%p, error=%d\n",
+ xfer, xfer->endpoint, error);
+
+ /*
+ * 1) Free any endpoints.
+ * 2) Control transfers can be split and we should not re-open
+ * the data pipe between transactions unless there is an error.
+ */
+ if ((xfer->flags_int.control_act == 0) || (error != 0)) {
+ struct octusb_td *td;
+
+ td = xfer->td_start[0];
+
+ octusb_host_free_endpoint(td);
+ }
+ /* dequeue transfer and start next transfer */
+ usbd_transfer_done(xfer, error);
+}
+
+/*------------------------------------------------------------------------*
+ * octusb bulk support
+ *------------------------------------------------------------------------*/
+static void
+octusb_device_bulk_open(struct usb_xfer *xfer)
+{
+ return;
+}
+
+static void
+octusb_device_bulk_close(struct usb_xfer *xfer)
+{
+ octusb_device_done(xfer, USB_ERR_CANCELLED);
+}
+
+static void
+octusb_device_bulk_enter(struct usb_xfer *xfer)
+{
+ return;
+}
+
+static void
+octusb_device_bulk_start(struct usb_xfer *xfer)
+{
+ /* setup TDs */
+ octusb_setup_standard_chain(xfer);
+ octusb_start_standard_chain(xfer);
+}
+
+struct usb_pipe_methods octusb_device_bulk_methods =
+{
+ .open = octusb_device_bulk_open,
+ .close = octusb_device_bulk_close,
+ .enter = octusb_device_bulk_enter,
+ .start = octusb_device_bulk_start,
+};
+
+/*------------------------------------------------------------------------*
+ * octusb control support
+ *------------------------------------------------------------------------*/
+static void
+octusb_device_ctrl_open(struct usb_xfer *xfer)
+{
+ return;
+}
+
+static void
+octusb_device_ctrl_close(struct usb_xfer *xfer)
+{
+ octusb_device_done(xfer, USB_ERR_CANCELLED);
+}
+
+static void
+octusb_device_ctrl_enter(struct usb_xfer *xfer)
+{
+ return;
+}
+
+static void
+octusb_device_ctrl_start(struct usb_xfer *xfer)
+{
+ /* setup TDs */
+ octusb_setup_standard_chain(xfer);
+ octusb_start_standard_chain(xfer);
+}
+
+struct usb_pipe_methods octusb_device_ctrl_methods =
+{
+ .open = octusb_device_ctrl_open,
+ .close = octusb_device_ctrl_close,
+ .enter = octusb_device_ctrl_enter,
+ .start = octusb_device_ctrl_start,
+};
+
+/*------------------------------------------------------------------------*
+ * octusb interrupt support
+ *------------------------------------------------------------------------*/
+static void
+octusb_device_intr_open(struct usb_xfer *xfer)
+{
+ return;
+}
+
+static void
+octusb_device_intr_close(struct usb_xfer *xfer)
+{
+ octusb_device_done(xfer, USB_ERR_CANCELLED);
+}
+
+static void
+octusb_device_intr_enter(struct usb_xfer *xfer)
+{
+ return;
+}
+
+static void
+octusb_device_intr_start(struct usb_xfer *xfer)
+{
+ /* setup TDs */
+ octusb_setup_standard_chain(xfer);
+ octusb_start_standard_chain(xfer);
+}
+
+struct usb_pipe_methods octusb_device_intr_methods =
+{
+ .open = octusb_device_intr_open,
+ .close = octusb_device_intr_close,
+ .enter = octusb_device_intr_enter,
+ .start = octusb_device_intr_start,
+};
+
+/*------------------------------------------------------------------------*
+ * octusb isochronous support
+ *------------------------------------------------------------------------*/
+static void
+octusb_device_isoc_open(struct usb_xfer *xfer)
+{
+ return;
+}
+
+static void
+octusb_device_isoc_close(struct usb_xfer *xfer)
+{
+ octusb_device_done(xfer, USB_ERR_CANCELLED);
+}
+
+static void
+octusb_device_isoc_enter(struct usb_xfer *xfer)
+{
+ struct octusb_softc *sc = OCTUSB_BUS2SC(xfer->xroot->bus);
+ uint32_t temp;
+ uint32_t frame_count;
+ uint32_t fs_frames;
+
+ DPRINTFN(5, "xfer=%p next=%d nframes=%d\n",
+ xfer, xfer->endpoint->isoc_next, xfer->nframes);
+
+ /* get the current frame index */
+
+ frame_count = cvmx_usb_get_frame_number(
+ &sc->sc_port[xfer->xroot->udev->port_index].state);
+
+ /*
+ * check if the frame index is within the window where the frames
+ * will be inserted
+ */
+ temp = (frame_count - xfer->endpoint->isoc_next) & 0x7FF;
+
+ if (usbd_get_speed(xfer->xroot->udev) == USB_SPEED_HIGH) {
+ fs_frames = (xfer->nframes + 7) / 8;
+ } else {
+ fs_frames = xfer->nframes;
+ }
+
+ if ((xfer->endpoint->is_synced == 0) || (temp < fs_frames)) {
+ /*
+ * If there is data underflow or the pipe queue is
+ * empty we schedule the transfer a few frames ahead
+ * of the current frame position. Else two isochronous
+ * transfers might overlap.
+ */
+ xfer->endpoint->isoc_next = (frame_count + 3) & 0x7FF;
+ xfer->endpoint->is_synced = 1;
+ DPRINTFN(2, "start next=%d\n", xfer->endpoint->isoc_next);
+ }
+ /*
+ * compute how many milliseconds the insertion is ahead of the
+ * current frame position:
+ */
+ temp = (xfer->endpoint->isoc_next - frame_count) & 0x7FF;
+
+ /*
+ * pre-compute when the isochronous transfer will be finished:
+ */
+ xfer->isoc_time_complete =
+ usb_isoc_time_expand(&sc->sc_bus, frame_count) + temp +
+ fs_frames;
+
+ /* compute frame number for next insertion */
+ xfer->endpoint->isoc_next += fs_frames;
+}
+
+static void
+octusb_device_isoc_start(struct usb_xfer *xfer)
+{
+ /* setup TDs */
+ octusb_setup_standard_chain(xfer);
+ octusb_start_standard_chain(xfer);
+}
+
+struct usb_pipe_methods octusb_device_isoc_methods =
+{
+ .open = octusb_device_isoc_open,
+ .close = octusb_device_isoc_close,
+ .enter = octusb_device_isoc_enter,
+ .start = octusb_device_isoc_start,
+};
+
+/*------------------------------------------------------------------------*
+ * OCTUSB root HUB support
+ *------------------------------------------------------------------------*
+ * Simulate a hardware HUB by handling all the necessary requests.
+ *------------------------------------------------------------------------*/
+static const
+struct usb_device_descriptor octusb_devd = {
+ .bLength = sizeof(octusb_devd),
+ .bDescriptorType = UDESC_DEVICE,
+ .bcdUSB = {0x00, 0x02},
+ .bDeviceClass = UDCLASS_HUB,
+ .bDeviceSubClass = UDSUBCLASS_HUB,
+ .bDeviceProtocol = UDPROTO_FSHUB,
+ .bMaxPacketSize = 64,
+ .idVendor = {0},
+ .idProduct = {0},
+ .bcdDevice = {0x00, 0x01},
+ .iManufacturer = 1,
+ .iProduct = 2,
+ .iSerialNumber = 0,
+ .bNumConfigurations = 1,
+};
+
+static const
+struct usb_device_qualifier octusb_odevd = {
+ .bLength = sizeof(octusb_odevd),
+ .bDescriptorType = UDESC_DEVICE_QUALIFIER,
+ .bcdUSB = {0x00, 0x02},
+ .bDeviceClass = UDCLASS_HUB,
+ .bDeviceSubClass = UDSUBCLASS_HUB,
+ .bDeviceProtocol = UDPROTO_FSHUB,
+ .bMaxPacketSize0 = 0,
+ .bNumConfigurations = 0,
+ .bReserved = 0,
+};
+
+static const
+struct octusb_config_desc octusb_confd = {
+ .confd = {
+ .bLength = sizeof(struct usb_config_descriptor),
+ .bDescriptorType = UDESC_CONFIG,
+ .wTotalLength[0] = sizeof(octusb_confd),
+ .bNumInterface = 1,
+ .bConfigurationValue = 1,
+ .iConfiguration = 0,
+ .bmAttributes = UC_SELF_POWERED,
+ .bMaxPower = 0 /* max power */
+ },
+ .ifcd = {
+ .bLength = sizeof(struct usb_interface_descriptor),
+ .bDescriptorType = UDESC_INTERFACE,
+ .bNumEndpoints = 1,
+ .bInterfaceClass = UICLASS_HUB,
+ .bInterfaceSubClass = UISUBCLASS_HUB,
+ .bInterfaceProtocol = UIPROTO_FSHUB,
+ },
+ .endpd = {
+ .bLength = sizeof(struct usb_endpoint_descriptor),
+ .bDescriptorType = UDESC_ENDPOINT,
+ .bEndpointAddress = UE_DIR_IN | OCTUSB_INTR_ENDPT,
+ .bmAttributes = UE_INTERRUPT,
+ .wMaxPacketSize[0] = 8, /* max packet (63 ports) */
+ .bInterval = 255,
+ },
+};
+
+static const
+struct usb_hub_descriptor_min octusb_hubd =
+{
+ .bDescLength = sizeof(octusb_hubd),
+ .bDescriptorType = UDESC_HUB,
+ .bNbrPorts = 2,
+ .wHubCharacteristics = {UHD_PWR_NO_SWITCH | UHD_OC_INDIVIDUAL, 0},
+ .bPwrOn2PwrGood = 50,
+ .bHubContrCurrent = 0,
+ .DeviceRemovable = {0x00}, /* all ports are removable */
+};
+
+static usb_error_t
+octusb_roothub_exec(struct usb_device *udev,
+ struct usb_device_request *req, const void **pptr, uint16_t *plength)
+{
+ struct octusb_softc *sc = OCTUSB_BUS2SC(udev->bus);
+ const void *ptr;
+ const char *str_ptr;
+ uint16_t value;
+ uint16_t index;
+ uint16_t status;
+ uint16_t change;
+ uint16_t len;
+ usb_error_t err;
+ cvmx_usb_port_status_t usb_port_status;
+
+ USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED);
+
+ /* XXX disable power save mode, hence it is not supported */
+ udev->power_mode = USB_POWER_MODE_ON;
+
+ /* buffer reset */
+ ptr = (const void *)&sc->sc_hub_desc.temp;
+ len = 0;
+ err = 0;
+
+ value = UGETW(req->wValue);
+ index = UGETW(req->wIndex);
+
+ DPRINTFN(3, "type=0x%02x request=0x%02x wLen=0x%04x "
+ "wValue=0x%04x wIndex=0x%04x\n",
+ req->bmRequestType, req->bRequest,
+ UGETW(req->wLength), value, index);
+
+#define C(x,y) ((x) | ((y) << 8))
+ switch (C(req->bRequest, req->bmRequestType)) {
+ case C(UR_CLEAR_FEATURE, UT_WRITE_DEVICE):
+ case C(UR_CLEAR_FEATURE, UT_WRITE_INTERFACE):
+ case C(UR_CLEAR_FEATURE, UT_WRITE_ENDPOINT):
+ break;
+ case C(UR_GET_CONFIG, UT_READ_DEVICE):
+ len = 1;
+ sc->sc_hub_desc.temp[0] = sc->sc_conf;
+ break;
+ case C(UR_GET_DESCRIPTOR, UT_READ_DEVICE):
+ switch (value >> 8) {
+ case UDESC_DEVICE:
+ if ((value & 0xff) != 0) {
+ err = USB_ERR_IOERROR;
+ goto done;
+ }
+ len = sizeof(octusb_devd);
+
+ ptr = (const void *)&octusb_devd;
+ break;
+
+ case UDESC_DEVICE_QUALIFIER:
+ if ((value & 0xff) != 0) {
+ err = USB_ERR_IOERROR;
+ goto done;
+ }
+ len = sizeof(octusb_odevd);
+ ptr = (const void *)&octusb_odevd;
+ break;
+
+ case UDESC_CONFIG:
+ if ((value & 0xff) != 0) {
+ err = USB_ERR_IOERROR;
+ goto done;
+ }
+ len = sizeof(octusb_confd);
+ ptr = (const void *)&octusb_confd;
+ break;
+
+ case UDESC_STRING:
+ switch (value & 0xff) {
+ case 0: /* Language table */
+ str_ptr = "\001";
+ break;
+
+ case 1: /* Vendor */
+ str_ptr = "Cavium Networks";
+ break;
+
+ case 2: /* Product */
+ str_ptr = "OCTUSB Root HUB";
+ break;
+
+ default:
+ str_ptr = "";
+ break;
+ }
+
+ len = usb_make_str_desc(sc->sc_hub_desc.temp,
+ sizeof(sc->sc_hub_desc.temp), str_ptr);
+ break;
+
+ default:
+ err = USB_ERR_IOERROR;
+ goto done;
+ }
+ break;
+ case C(UR_GET_INTERFACE, UT_READ_INTERFACE):
+ len = 1;
+ sc->sc_hub_desc.temp[0] = 0;
+ break;
+ case C(UR_GET_STATUS, UT_READ_DEVICE):
+ len = 2;
+ USETW(sc->sc_hub_desc.stat.wStatus, UDS_SELF_POWERED);
+ break;
+ case C(UR_GET_STATUS, UT_READ_INTERFACE):
+ case C(UR_GET_STATUS, UT_READ_ENDPOINT):
+ len = 2;
+ USETW(sc->sc_hub_desc.stat.wStatus, 0);
+ break;
+ case C(UR_SET_ADDRESS, UT_WRITE_DEVICE):
+ if (value >= OCTUSB_MAX_DEVICES) {
+ err = USB_ERR_IOERROR;
+ goto done;
+ }
+ sc->sc_addr = value;
+ break;
+ case C(UR_SET_CONFIG, UT_WRITE_DEVICE):
+ if ((value != 0) && (value != 1)) {
+ err = USB_ERR_IOERROR;
+ goto done;
+ }
+ sc->sc_conf = value;
+ break;
+ case C(UR_SET_DESCRIPTOR, UT_WRITE_DEVICE):
+ break;
+ case C(UR_SET_FEATURE, UT_WRITE_DEVICE):
+ case C(UR_SET_FEATURE, UT_WRITE_INTERFACE):
+ case C(UR_SET_FEATURE, UT_WRITE_ENDPOINT):
+ err = USB_ERR_IOERROR;
+ goto done;
+ case C(UR_SET_INTERFACE, UT_WRITE_INTERFACE):
+ break;
+ case C(UR_SYNCH_FRAME, UT_WRITE_ENDPOINT):
+ break;
+ /* Hub requests */
+ case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_DEVICE):
+ break;
+ case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_OTHER):
+ DPRINTFN(4, "UR_CLEAR_PORT_FEATURE "
+ "port=%d feature=%d\n",
+ index, value);
+ if ((index < 1) ||
+ (index > sc->sc_noport) ||
+ sc->sc_port[index - 1].disabled) {
+ err = USB_ERR_IOERROR;
+ goto done;
+ }
+ index--;
+
+ switch (value) {
+ case UHF_PORT_ENABLE:
+ cvmx_usb_disable(&sc->sc_port[index].state);
+ break;
+ case UHF_PORT_SUSPEND:
+ case UHF_PORT_RESET:
+ break;
+ case UHF_C_PORT_CONNECTION:
+ cvmx_usb_set_status(&sc->sc_port[index].state,
+ cvmx_usb_get_status(&sc->sc_port[index].state));
+ break;
+ case UHF_C_PORT_ENABLE:
+ cvmx_usb_set_status(&sc->sc_port[index].state,
+ cvmx_usb_get_status(&sc->sc_port[index].state));
+ break;
+ case UHF_C_PORT_OVER_CURRENT:
+ cvmx_usb_set_status(&sc->sc_port[index].state,
+ cvmx_usb_get_status(&sc->sc_port[index].state));
+ break;
+ case UHF_C_PORT_RESET:
+ sc->sc_isreset = 0;
+ goto done;
+ case UHF_C_PORT_SUSPEND:
+ break;
+ case UHF_PORT_CONNECTION:
+ case UHF_PORT_OVER_CURRENT:
+ case UHF_PORT_POWER:
+ case UHF_PORT_LOW_SPEED:
+ default:
+ err = USB_ERR_IOERROR;
+ goto done;
+ }
+ break;
+ case C(UR_GET_DESCRIPTOR, UT_READ_CLASS_DEVICE):
+ if ((value & 0xff) != 0) {
+ err = USB_ERR_IOERROR;
+ goto done;
+ }
+ sc->sc_hubd = octusb_hubd;
+ sc->sc_hubd.bNbrPorts = sc->sc_noport;
+ len = sizeof(sc->sc_hubd);
+ ptr = (const void *)&sc->sc_hubd;
+ break;
+ case C(UR_GET_STATUS, UT_READ_CLASS_DEVICE):
+ len = 16;
+ memset(sc->sc_hub_desc.temp, 0, 16);
+ break;
+ case C(UR_GET_STATUS, UT_READ_CLASS_OTHER):
+ if ((index < 1) ||
+ (index > sc->sc_noport) ||
+ sc->sc_port[index - 1].disabled) {
+ err = USB_ERR_IOERROR;
+ goto done;
+ }
+ index--;
+
+ usb_port_status = cvmx_usb_get_status(&sc->sc_port[index].state);
+
+ status = change = 0;
+ if (usb_port_status.connected)
+ status |= UPS_CURRENT_CONNECT_STATUS;
+ if (usb_port_status.port_enabled)
+ status |= UPS_PORT_ENABLED;
+ if (usb_port_status.port_over_current)
+ status |= UPS_OVERCURRENT_INDICATOR;
+ if (usb_port_status.port_powered)
+ status |= UPS_PORT_POWER;
+
+ switch (usb_port_status.port_speed) {
+ case CVMX_USB_SPEED_HIGH:
+ status |= UPS_HIGH_SPEED;
+ break;
+ case CVMX_USB_SPEED_FULL:
+ break;
+ default:
+ status |= UPS_LOW_SPEED;
+ break;
+ }
+
+ if (usb_port_status.connect_change)
+ change |= UPS_C_CONNECT_STATUS;
+ if (sc->sc_isreset)
+ change |= UPS_C_PORT_RESET;
+
+ USETW(sc->sc_hub_desc.ps.wPortStatus, status);
+ USETW(sc->sc_hub_desc.ps.wPortChange, change);
+
+ len = sizeof(sc->sc_hub_desc.ps);
+ break;
+ case C(UR_SET_DESCRIPTOR, UT_WRITE_CLASS_DEVICE):
+ err = USB_ERR_IOERROR;
+ goto done;
+ case C(UR_SET_FEATURE, UT_WRITE_CLASS_DEVICE):
+ break;
+ case C(UR_SET_FEATURE, UT_WRITE_CLASS_OTHER):
+ if ((index < 1) ||
+ (index > sc->sc_noport) ||
+ sc->sc_port[index - 1].disabled) {
+ err = USB_ERR_IOERROR;
+ goto done;
+ }
+ index--;
+
+ switch (value) {
+ case UHF_PORT_ENABLE:
+ break;
+ case UHF_PORT_RESET:
+ cvmx_usb_disable(&sc->sc_port[index].state);
+ if (cvmx_usb_enable(&sc->sc_port[index].state)) {
+ err = USB_ERR_IOERROR;
+ goto done;
+ }
+ sc->sc_isreset = 1;
+ goto done;
+ case UHF_PORT_POWER:
+ /* pretend we turned on power */
+ goto done;
+ case UHF_PORT_SUSPEND:
+ case UHF_C_PORT_CONNECTION:
+ case UHF_C_PORT_ENABLE:
+ case UHF_C_PORT_OVER_CURRENT:
+ case UHF_PORT_CONNECTION:
+ case UHF_PORT_OVER_CURRENT:
+ case UHF_PORT_LOW_SPEED:
+ case UHF_C_PORT_SUSPEND:
+ case UHF_C_PORT_RESET:
+ default:
+ err = USB_ERR_IOERROR;
+ goto done;
+ }
+ break;
+ default:
+ err = USB_ERR_IOERROR;
+ goto done;
+ }
+done:
+ *plength = len;
+ *pptr = ptr;
+ return (err);
+}
+
+static void
+octusb_xfer_setup(struct usb_setup_params *parm)
+{
+ struct usb_page_search page_info;
+ struct usb_page_cache *pc;
+ struct octusb_softc *sc;
+ struct octusb_qh *qh;
+ struct usb_xfer *xfer;
+ struct usb_device *hub;
+ void *last_obj;
+ uint32_t n;
+ uint32_t ntd;
+
+ sc = OCTUSB_BUS2SC(parm->udev->bus);
+ xfer = parm->curr_xfer;
+ qh = NULL;
+
+ /*
+ * NOTE: This driver does not use any of the parameters that
+ * are computed from the following values. Just set some
+ * reasonable dummies:
+ */
+
+ parm->hc_max_packet_size = 0x400;
+ parm->hc_max_packet_count = 3;
+ parm->hc_max_frame_size = 0xC00;
+
+ usbd_transfer_setup_sub(parm);
+
+ if (parm->err)
+ return;
+
+ /* Allocate a queue head */
+
+ if (usbd_transfer_setup_sub_malloc(
+ parm, &pc, sizeof(struct octusb_qh),
+ USB_HOST_ALIGN, 1)) {
+ parm->err = USB_ERR_NOMEM;
+ return;
+ }
+ if (parm->buf) {
+ usbd_get_page(pc, 0, &page_info);
+
+ qh = page_info.buffer;
+
+ /* fill out QH */
+
+ qh->sc = OCTUSB_BUS2SC(xfer->xroot->bus);
+ qh->max_frame_size = xfer->max_frame_size;
+ qh->max_packet_size = xfer->max_packet_size;
+ qh->ep_num = xfer->endpointno;
+ qh->ep_type = xfer->endpoint->edesc->bmAttributes;
+ qh->dev_addr = xfer->address;
+ qh->dev_speed = usbd_get_speed(xfer->xroot->udev);
+ qh->root_port_index = xfer->xroot->udev->port_index;
+ /* We need Octeon USB HUB's port index, not the local port */
+ hub = xfer->xroot->udev->parent_hub;
+ while(hub && hub->parent_hub) {
+ qh->root_port_index = hub->port_index;
+ hub = hub->parent_hub;
+ }
+
+ switch (xfer->endpoint->edesc->bmAttributes & UE_XFERTYPE) {
+ case UE_INTERRUPT:
+ if (usbd_get_speed(xfer->xroot->udev) == USB_SPEED_HIGH)
+ qh->ep_interval = xfer->interval * 8;
+ else
+ qh->ep_interval = xfer->interval * 1;
+ break;
+ case UE_ISOCHRONOUS:
+ qh->ep_interval = 1 << xfer->fps_shift;
+ break;
+ default:
+ qh->ep_interval = 0;
+ break;
+ }
+
+ qh->ep_mult = xfer->max_packet_count & 3;
+ qh->hs_hub_addr = xfer->xroot->udev->hs_hub_addr;
+ qh->hs_hub_port = xfer->xroot->udev->hs_port_no;
+ }
+ xfer->qh_start[0] = qh;
+
+ /* Allocate a fixup buffer */
+
+ if (usbd_transfer_setup_sub_malloc(
+ parm, &pc, OCTUSB_MAX_FIXUP,
+ OCTUSB_MAX_FIXUP, 1)) {
+ parm->err = USB_ERR_NOMEM;
+ return;
+ }
+ if (parm->buf) {
+ usbd_get_page(pc, 0, &page_info);
+
+ qh->fixup_phys = page_info.physaddr;
+ qh->fixup_pc = pc;
+ qh->fixup_buf = page_info.buffer;
+ }
+ /* Allocate transfer descriptors */
+
+ last_obj = NULL;
+
+ ntd = xfer->nframes + 1 /* STATUS */ + 1 /* SYNC */ ;
+
+ if (usbd_transfer_setup_sub_malloc(
+ parm, &pc, sizeof(struct octusb_td),
+ USB_HOST_ALIGN, ntd)) {
+ parm->err = USB_ERR_NOMEM;
+ return;
+ }
+ if (parm->buf) {
+ for (n = 0; n != ntd; n++) {
+ struct octusb_td *td;
+
+ usbd_get_page(pc + n, 0, &page_info);
+
+ td = page_info.buffer;
+
+ td->qh = qh;
+ td->obj_next = last_obj;
+
+ last_obj = td;
+ }
+ }
+ xfer->td_start[0] = last_obj;
+}
+
+static void
+octusb_ep_init(struct usb_device *udev, struct usb_endpoint_descriptor *edesc,
+ struct usb_endpoint *ep)
+{
+ struct octusb_softc *sc = OCTUSB_BUS2SC(udev->bus);
+
+ DPRINTFN(2, "endpoint=%p, addr=%d, endpt=%d, mode=%d (%d)\n",
+ ep, udev->address, edesc->bEndpointAddress,
+ udev->flags.usb_mode, sc->sc_addr);
+
+ if (udev->device_index != sc->sc_addr) {
+ switch (edesc->bmAttributes & UE_XFERTYPE) {
+ case UE_CONTROL:
+ ep->methods = &octusb_device_ctrl_methods;
+ break;
+ case UE_INTERRUPT:
+ ep->methods = &octusb_device_intr_methods;
+ break;
+ case UE_ISOCHRONOUS:
+ if (udev->speed != USB_SPEED_LOW)
+ ep->methods = &octusb_device_isoc_methods;
+ break;
+ case UE_BULK:
+ ep->methods = &octusb_device_bulk_methods;
+ break;
+ default:
+ /* do nothing */
+ break;
+ }
+ }
+}
+
+static void
+octusb_xfer_unsetup(struct usb_xfer *xfer)
+{
+ DPRINTF("Nothing to do.\n");
+}
+
+static void
+octusb_get_dma_delay(struct usb_device *udev, uint32_t *pus)
+{
+ /* DMA delay - wait until any use of memory is finished */
+ *pus = (2125); /* microseconds */
+}
+
+static void
+octusb_device_resume(struct usb_device *udev)
+{
+ DPRINTF("Nothing to do.\n");
+}
+
+static void
+octusb_device_suspend(struct usb_device *udev)
+{
+ DPRINTF("Nothing to do.\n");
+}
+
+static void
+octusb_set_hw_power(struct usb_bus *bus)
+{
+ DPRINTF("Nothing to do.\n");
+}
+
+static void
+octusb_set_hw_power_sleep(struct usb_bus *bus, uint32_t state)
+{
+ struct octusb_softc *sc = OCTUSB_BUS2SC(bus);
+
+ switch (state) {
+ case USB_HW_POWER_SUSPEND:
+ octusb_suspend(sc);
+ break;
+ case USB_HW_POWER_SHUTDOWN:
+ octusb_uninit(sc);
+ break;
+ case USB_HW_POWER_RESUME:
+ octusb_resume(sc);
+ break;
+ default:
+ break;
+ }
+}
+
+struct usb_bus_methods octusb_bus_methods = {
+ .endpoint_init = octusb_ep_init,
+ .xfer_setup = octusb_xfer_setup,
+ .xfer_unsetup = octusb_xfer_unsetup,
+ .get_dma_delay = octusb_get_dma_delay,
+ .device_resume = octusb_device_resume,
+ .device_suspend = octusb_device_suspend,
+ .set_hw_power = octusb_set_hw_power,
+ .set_hw_power_sleep = octusb_set_hw_power_sleep,
+ .roothub_exec = octusb_roothub_exec,
+ .xfer_poll = octusb_do_poll,
+};
Property changes on: trunk/sys/mips/cavium/usb/octusb.c
___________________________________________________________________
Added: svn:eol-style
## -0,0 +1 ##
+native
\ No newline at end of property
Added: svn:keywords
## -0,0 +1 ##
+MidnightBSD=%H
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+text/plain
\ No newline at end of property
Added: trunk/sys/mips/cavium/usb/octusb.h
===================================================================
--- trunk/sys/mips/cavium/usb/octusb.h (rev 0)
+++ trunk/sys/mips/cavium/usb/octusb.h 2018-05-26 21:55:02 UTC (rev 9987)
@@ -0,0 +1,139 @@
+/* $MidnightBSD$ */
+/* $FreeBSD: stable/10/sys/mips/cavium/usb/octusb.h 230405 2012-01-20 23:37:04Z gonzo $ */
+
+/*-
+ * Copyright (c) 2010 Hans Petter Selasky. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ */
+
+#ifndef _OCTUSB_H_
+#define _OCTUSB_H_
+
+#define OCTUSB_MAX_DEVICES MIN(USB_MAX_DEVICES, 64)
+#define OCTUSB_MAX_PORTS 2 /* hardcoded */
+#define OCTUSB_MAX_FIXUP 4096 /* bytes */
+#define OCTUSB_INTR_ENDPT 0x01
+
+struct octusb_qh;
+struct octusb_td;
+struct octusb_softc;
+
+typedef uint8_t (octusb_cmd_t)(struct octusb_td *td);
+
+struct octusb_td {
+ struct octusb_qh *qh;
+ struct octusb_td *obj_next;
+ struct usb_page_cache *pc;
+ octusb_cmd_t *func;
+
+ uint32_t remainder;
+ uint32_t offset;
+
+ uint8_t error_any:1;
+ uint8_t error_stall:1;
+ uint8_t short_pkt:1;
+ uint8_t alt_next:1;
+ uint8_t reserved:4;
+};
+
+struct octusb_qh {
+
+ uint64_t fixup_phys;
+
+ struct octusb_softc *sc;
+ struct usb_page_cache *fixup_pc;
+ uint8_t *fixup_buf;
+
+ cvmx_usb_iso_packet_t iso_pkt;
+
+ uint32_t fixup_off;
+
+ uint16_t max_frame_size;
+ uint16_t max_packet_size;
+ uint16_t fixup_actlen;
+ uint16_t fixup_len;
+ uint16_t ep_interval;
+
+ uint8_t dev_addr;
+ uint8_t dev_speed;
+ uint8_t ep_allocated;
+ uint8_t ep_mult;
+ uint8_t ep_num;
+ uint8_t ep_type;
+ uint8_t ep_toggle_next;
+ uint8_t root_port_index;
+ uint8_t fixup_complete;
+ uint8_t fixup_pending;
+ uint8_t hs_hub_addr;
+ uint8_t hs_hub_port;
+
+ int fixup_handle;
+ int ep_handle;
+};
+
+struct octusb_config_desc {
+ struct usb_config_descriptor confd;
+ struct usb_interface_descriptor ifcd;
+ struct usb_endpoint_descriptor endpd;
+} __packed;
+
+union octusb_hub_desc {
+ struct usb_status stat;
+ struct usb_port_status ps;
+ uint8_t temp[128];
+};
+
+struct octusb_port {
+ cvmx_usb_state_t state;
+ uint8_t disabled;
+};
+
+struct octusb_softc {
+
+ struct usb_bus sc_bus; /* base device */
+ union octusb_hub_desc sc_hub_desc;
+
+ struct usb_device *sc_devices[OCTUSB_MAX_DEVICES];
+
+ struct resource *sc_irq_res[OCTUSB_MAX_PORTS];
+ void *sc_intr_hdl[OCTUSB_MAX_PORTS];
+
+ struct octusb_port sc_port[OCTUSB_MAX_PORTS];
+ device_t sc_dev;
+
+ struct usb_hub_descriptor_min sc_hubd;
+
+ uint8_t sc_noport; /* number of ports */
+ uint8_t sc_addr; /* device address */
+ uint8_t sc_conf; /* device configuration */
+ uint8_t sc_isreset; /* set if current port is reset */
+
+ uint8_t sc_hub_idata[1];
+};
+
+usb_bus_mem_cb_t octusb_iterate_hw_softc;
+usb_error_t octusb_init(struct octusb_softc *);
+usb_error_t octusb_uninit(struct octusb_softc *);
+void octusb_interrupt(struct octusb_softc *);
+
+#endif /* _OCTUSB_H_ */
Property changes on: trunk/sys/mips/cavium/usb/octusb.h
___________________________________________________________________
Added: svn:eol-style
## -0,0 +1 ##
+native
\ No newline at end of property
Added: svn:keywords
## -0,0 +1 ##
+MidnightBSD=%H
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+text/plain
\ No newline at end of property
Added: trunk/sys/mips/cavium/usb/octusb_octeon.c
===================================================================
--- trunk/sys/mips/cavium/usb/octusb_octeon.c (rev 0)
+++ trunk/sys/mips/cavium/usb/octusb_octeon.c 2018-05-26 21:55:02 UTC (rev 9987)
@@ -0,0 +1,218 @@
+/* $MidnightBSD$ */
+#include <sys/cdefs.h>
+__FBSDID("$FreeBSD: stable/10/sys/mips/cavium/usb/octusb_octeon.c 308402 2016-11-07 09:19:04Z hselasky $");
+
+/*-
+ * Copyright (c) 2007-2008 Hans Petter Selasky. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ */
+
+#include <sys/stdint.h>
+#include <sys/stddef.h>
+#include <sys/param.h>
+#include <sys/queue.h>
+#include <sys/types.h>
+#include <sys/systm.h>
+#include <sys/kernel.h>
+#include <sys/bus.h>
+#include <sys/module.h>
+#include <sys/lock.h>
+#include <sys/mutex.h>
+#include <sys/condvar.h>
+#include <sys/sysctl.h>
+#include <sys/sx.h>
+#include <sys/unistd.h>
+#include <sys/callout.h>
+#include <sys/malloc.h>
+#include <sys/priv.h>
+#include <sys/rman.h>
+
+#include <dev/usb/usb.h>
+#include <dev/usb/usbdi.h>
+
+#include <dev/usb/usb_core.h>
+#include <dev/usb/usb_busdma.h>
+#include <dev/usb/usb_process.h>
+#include <dev/usb/usb_util.h>
+
+#include <dev/usb/usb_controller.h>
+#include <dev/usb/usb_bus.h>
+
+#include <contrib/octeon-sdk/cvmx.h>
+#include <mips/cavium/octeon_irq.h>
+#include <contrib/octeon-sdk/cvmx-usb.h>
+
+#include <mips/cavium/usb/octusb.h>
+
+#define MEM_RID 0
+
+static device_identify_t octusb_octeon_identify;
+static device_probe_t octusb_octeon_probe;
+static device_attach_t octusb_octeon_attach;
+static device_detach_t octusb_octeon_detach;
+
+struct octusb_octeon_softc {
+ struct octusb_softc sc_dci; /* must be first */
+};
+
+static void
+octusb_octeon_identify(driver_t *drv, device_t parent)
+{
+ if (octeon_has_feature(OCTEON_FEATURE_USB))
+ BUS_ADD_CHILD(parent, 0, "octusb", 0);
+}
+
+static int
+octusb_octeon_probe(device_t dev)
+{
+ device_set_desc(dev, "Cavium Octeon USB controller");
+ return (0);
+}
+
+static int
+octusb_octeon_attach(device_t dev)
+{
+ struct octusb_octeon_softc *sc = device_get_softc(dev);
+ int err;
+ int rid;
+ int nports;
+ int i;
+
+ /* setup controller interface softc */
+
+ /* initialise some bus fields */
+ sc->sc_dci.sc_bus.parent = dev;
+ sc->sc_dci.sc_bus.devices = sc->sc_dci.sc_devices;
+ sc->sc_dci.sc_bus.devices_max = OCTUSB_MAX_DEVICES;
+ sc->sc_dci.sc_bus.dma_bits = 32;
+
+ /* get all DMA memory */
+ if (usb_bus_mem_alloc_all(&sc->sc_dci.sc_bus,
+ USB_GET_DMA_TAG(dev), NULL)) {
+ return (ENOMEM);
+ }
+ nports = cvmx_usb_get_num_ports();
+ if (nports > OCTUSB_MAX_PORTS)
+ panic("octusb: too many USB ports %d", nports);
+ for (i = 0; i < nports; i++) {
+ rid = 0;
+ sc->sc_dci.sc_irq_res[i] =
+ bus_alloc_resource(dev, SYS_RES_IRQ, &rid,
+ OCTEON_IRQ_USB0 + i, OCTEON_IRQ_USB0 + i, 1, RF_ACTIVE);
+ if (!(sc->sc_dci.sc_irq_res[i])) {
+ goto error;
+ }
+
+#if (__FreeBSD_version >= 700031)
+ err = bus_setup_intr(dev, sc->sc_dci.sc_irq_res[i], INTR_TYPE_BIO | INTR_MPSAFE,
+ NULL, (driver_intr_t *)octusb_interrupt, sc, &sc->sc_dci.sc_intr_hdl[i]);
+#else
+ err = bus_setup_intr(dev, sc->sc_dci.sc_irq_res[i], INTR_TYPE_BIO | INTR_MPSAFE,
+ (driver_intr_t *)octusb_interrupt, sc, &sc->sc_dci.sc_intr_hdl[i]);
+#endif
+ if (err) {
+ sc->sc_dci.sc_intr_hdl[i] = NULL;
+ goto error;
+ }
+ }
+
+ sc->sc_dci.sc_bus.bdev = device_add_child(dev, "usbus", -1);
+ if (!(sc->sc_dci.sc_bus.bdev)) {
+ goto error;
+ }
+ device_set_ivars(sc->sc_dci.sc_bus.bdev, &sc->sc_dci.sc_bus);
+
+
+ err = octusb_init(&sc->sc_dci);
+ if (!err) {
+ err = device_probe_and_attach(sc->sc_dci.sc_bus.bdev);
+ }
+ if (err) {
+ goto error;
+ }
+ return (0);
+
+error:
+ octusb_octeon_detach(dev);
+ return (ENXIO);
+}
+
+static int
+octusb_octeon_detach(device_t dev)
+{
+ struct octusb_octeon_softc *sc = device_get_softc(dev);
+ int err;
+ int nports;
+ int i;
+
+ /* during module unload there are lots of children leftover */
+ device_delete_children(dev);
+
+ if (sc->sc_dci.sc_irq_res[0] && sc->sc_dci.sc_intr_hdl[0])
+ /*
+ * only call octusb_octeon_uninit() after octusb_octeon_init()
+ */
+ octusb_uninit(&sc->sc_dci);
+
+ nports = cvmx_usb_get_num_ports();
+ if (nports > OCTUSB_MAX_PORTS)
+ panic("octusb: too many USB ports %d", nports);
+ for (i = 0; i < nports; i++) {
+ if (sc->sc_dci.sc_irq_res[0] && sc->sc_dci.sc_intr_hdl[0]) {
+ err = bus_teardown_intr(dev, sc->sc_dci.sc_irq_res[i],
+ sc->sc_dci.sc_intr_hdl[i]);
+ sc->sc_dci.sc_intr_hdl[i] = NULL;
+ }
+ if (sc->sc_dci.sc_irq_res) {
+ bus_release_resource(dev, SYS_RES_IRQ, 0,
+ sc->sc_dci.sc_irq_res[i]);
+ sc->sc_dci.sc_irq_res[i] = NULL;
+ }
+ }
+ usb_bus_mem_free_all(&sc->sc_dci.sc_bus, NULL);
+
+ return (0);
+}
+
+static device_method_t octusb_octeon_methods[] = {
+ /* Device interface */
+ DEVMETHOD(device_identify, octusb_octeon_identify),
+ DEVMETHOD(device_probe, octusb_octeon_probe),
+ DEVMETHOD(device_attach, octusb_octeon_attach),
+ DEVMETHOD(device_detach, octusb_octeon_detach),
+ DEVMETHOD(device_resume, bus_generic_resume),
+ DEVMETHOD(device_suspend, bus_generic_suspend),
+ DEVMETHOD(device_shutdown, bus_generic_shutdown),
+
+ DEVMETHOD_END
+};
+
+static driver_t octusb_octeon_driver = {
+ .name = "octusb",
+ .methods = octusb_octeon_methods,
+ .size = sizeof(struct octusb_octeon_softc),
+};
+
+static devclass_t octusb_octeon_devclass;
+
+DRIVER_MODULE(octusb, ciu, octusb_octeon_driver, octusb_octeon_devclass, 0, 0);
Property changes on: trunk/sys/mips/cavium/usb/octusb_octeon.c
___________________________________________________________________
Added: svn:eol-style
## -0,0 +1 ##
+native
\ No newline at end of property
Added: svn:keywords
## -0,0 +1 ##
+MidnightBSD=%H
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+text/plain
\ No newline at end of property
Added: trunk/sys/mips/conf/ADM5120
===================================================================
--- trunk/sys/mips/conf/ADM5120 (rev 0)
+++ trunk/sys/mips/conf/ADM5120 2018-05-26 21:55:02 UTC (rev 9987)
@@ -0,0 +1,64 @@
+# ADM5120 -- Kernel configuration file for FreeBSD/mips for adm5120 systems
+#
+# For more information on this file, please read the handbook section on
+# Kernel Configuration Files:
+#
+# http://www.FreeBSD.org/doc/en_US.ISO8859-1/books/handbook/kernelconfig-config.html
+#
+# The handbook is also available locally in /usr/share/doc/handbook
+# if you've installed the doc distribution, otherwise always see the
+# FreeBSD World Wide Web server (http://www.FreeBSD.org/) for the
+# latest information.
+#
+# An exhaustive list of options and more detailed explanations of the
+# device lines is also present in the ../../conf/NOTES and NOTES files.
+# If you are in doubt as to the purpose or necessity of a line, check first
+# in NOTES.
+#
+# $FreeBSD: stable/10/sys/mips/conf/ADM5120 221753 2011-05-11 00:52:41Z gonzo $
+
+ident ADM5120
+
+# Don't build any modules yet.
+makeoptions MODULES_OVERRIDE=""
+
+include "../adm5120/std.adm5120"
+
+hints "ADM5120.hints" #Default places to look for devices.
+
+makeoptions DEBUG=-g #Build kernel with gdb(1) debug symbols
+
+options DDB
+options KDB
+
+options SCHED_4BSD #4BSD scheduler
+options INET #InterNETworking
+options NFSCL #Network Filesystem Client
+options NFS_ROOT #NFS usable as /, requires NFSCL
+options PSEUDOFS #Pseudo-filesystem framework
+#options _KPOSIX_PRIORITY_SCHEDULING #Posix P1003_1B real-time extensions
+
+options BOOTP
+options BOOTP_NFSROOT
+options BOOTP_NFSV3
+options BOOTP_WIRED_TO=admsw0
+options BOOTP_COMPAT
+
+#options FFS #Berkeley Fast Filesystem
+#options SOFTUPDATES #Enable FFS soft updates support
+#options UFS_ACL #Support for access control lists
+#options UFS_DIRHASH #Improve performance on big directories
+options ROOTDEVNAME=\"nfs:10.0.0.1:/mnt/bsd\"
+
+# Debugging for use in -current
+#options DEADLKRES #Enable the deadlock resolver
+options INVARIANTS #Enable calls of extra sanity checking
+options INVARIANT_SUPPORT #Extra sanity checks of internal structures, required by INVARIANTS
+#options WITNESS #Enable checks to detect deadlocks and cycles
+#options WITNESS_SKIPSPIN #Don't run witness on spinlocks for speed
+
+device loop
+device ether
+device uart
+nodevice uart_ns8250 # ADM5120's UART not 16550-like
+# device md
Property changes on: trunk/sys/mips/conf/ADM5120
___________________________________________________________________
Added: mnbsd:nokeywords
## -0,0 +1 ##
+MidnightBSD=%H
\ No newline at end of property
Added: trunk/sys/mips/conf/ADM5120.hints
===================================================================
--- trunk/sys/mips/conf/ADM5120.hints (rev 0)
+++ trunk/sys/mips/conf/ADM5120.hints 2018-05-26 21:55:02 UTC (rev 9987)
@@ -0,0 +1,24 @@
+# $FreeBSD: stable/10/sys/mips/conf/ADM5120.hints 202175 2010-01-12 21:36:08Z imp $
+# device.hints
+hint.obio.0.at="nexus0"
+hint.obio.0.maddr=0x0
+hint.obio.0.msize=0x1fffffff
+
+# host-to-pci bridge
+hint.pcib.0.at="obio0"
+hint.pcib.0.maddr=0x11400000
+hint.pcib.0.msize=0x100000
+hint.pcib.0.io=0x11500000
+hint.pcib.0.iosize=0x100000
+
+# on-board switch engine
+hint.admsw.0.at="obio0"
+hint.admsw.0.maddr=0x12000000
+hint.admsw.0.msize=0x200000
+hint.admsw.0.irq=9
+
+# uart0
+hint.uart.0.at="obio0"
+hint.uart.0.maddr=0x12600000
+hint.uart.0.msize=0x200000
+hint.uart.0.irq=1
Property changes on: trunk/sys/mips/conf/ADM5120.hints
___________________________________________________________________
Added: mnbsd:nokeywords
## -0,0 +1 ##
+MidnightBSD=%H
\ No newline at end of property
Added: trunk/sys/mips/conf/ALCHEMY
===================================================================
--- trunk/sys/mips/conf/ALCHEMY (rev 0)
+++ trunk/sys/mips/conf/ALCHEMY 2018-05-26 21:55:02 UTC (rev 9987)
@@ -0,0 +1,64 @@
+# ALCHEMY -- Generic kernel for Alchemy Au1xxx CPUs.
+#
+# For more information on this file, please read the handbook section on
+# Kernel Configuration Files:
+#
+# http://www.FreeBSD.org/doc/en_US.ISO8859-1/books/handbook/kernelconfig-config.html
+#
+# The handbook is also available locally in /usr/share/doc/handbook
+# if you've installed the doc distribution, otherwise always see the
+# FreeBSD World Wide Web server (http://www.FreeBSD.org/) for the
+# latest information.
+#
+# An exhaustive list of options and more detailed explanations of the
+# device lines is also present in the ../../conf/NOTES and NOTES files.
+# If you are in doubt as to the purpose or necessity of a line, check first
+# in NOTES.
+#
+# $FreeBSD: stable/10/sys/mips/conf/ALCHEMY 266331 2014-05-17 17:34:37Z ian $
+
+ident ALCHEMY
+
+# Don't build any modules yet.
+makeoptions MODULES_OVERRIDE=""
+
+include "../alchemy/std.alchemy"
+
+#hints "ALCHEMY.hints" #Default places to look for devices.
+
+makeoptions DEBUG=-g #Build kernel with gdb(1) debug symbols
+
+options DDB
+options KDB
+
+options SCHED_4BSD #4BSD scheduler
+options INET #InterNETworking
+options NFSCL #Network Filesystem Client
+options NFS_ROOT #NFS usable as /, requires NFSCL
+options PSEUDOFS #Pseudo-filesystem framework
+# options _KPOSIX_PRIORITY_SCHEDULING #Posix P1003_1B real-time extensions
+
+options BOOTP
+options BOOTP_NFSROOT
+options BOOTP_NFSV3
+options BOOTP_WIRED_TO=admsw0
+options BOOTP_COMPAT
+
+# options FFS #Berkeley Fast Filesystem
+# options SOFTUPDATES #Enable FFS soft updates support
+# options UFS_ACL #Support for access control lists
+# options UFS_DIRHASH #Improve performance on big directories
+options ROOTDEVNAME=\"nfs:10.0.0.1:/mnt/bsd\"
+
+
+# Debugging for use in -current
+#options DEADLKRES #Enable the deadlock resolver
+options INVARIANTS #Enable calls of extra sanity checking
+options INVARIANT_SUPPORT #Extra sanity checks of internal structures, required by INVARIANTS
+#options WITNESS #Enable checks to detect deadlocks and cycles
+#options WITNESS_SKIPSPIN #Don't run witness on spinlocks for speed
+
+device loop
+device ether
+device uart
+# device md
Property changes on: trunk/sys/mips/conf/ALCHEMY
___________________________________________________________________
Added: mnbsd:nokeywords
## -0,0 +1 ##
+MidnightBSD=%H
\ No newline at end of property
Added: trunk/sys/mips/conf/AP121
===================================================================
--- trunk/sys/mips/conf/AP121 (rev 0)
+++ trunk/sys/mips/conf/AP121 2018-05-26 21:55:02 UTC (rev 9987)
@@ -0,0 +1,51 @@
+#
+# AP121 - the AP121 reference board from Qualcomm Atheros includes:
+#
+# * AR9330 SoC
+# * 16MB RAM
+# * 4MB flash
+# * Integrated 1x1 2GHz wifi and 10/100 bridge
+#
+# $FreeBSD: stable/10/sys/mips/conf/AP121 266331 2014-05-17 17:34:37Z ian $
+#
+
+# Include the default AR933x parameters
+include "AR933X_BASE"
+
+ident AP121
+
+# Override hints with board values
+hints "AP121.hints"
+
+# Force the board memory - the base AP121 only has 16MB RAM
+options AR71XX_REALMEM=(16*1024*1024)
+
+# i2c GPIO bus
+#device gpioiic
+#device iicbb
+#device iicbus
+#device iic
+
+# Options required for miiproxy and mdiobus
+options ARGE_MDIO # Export an MDIO bus separate from arge
+device miiproxy # MDIO bus <-> MII PHY rendezvous
+
+device etherswitch
+device arswitch
+
+# read MSDOS formatted disks - USB
+#options MSDOSFS
+
+# Enable the uboot environment stuff rather then the
+# redboot stuff.
+options AR71XX_ENV_UBOOT
+
+# uzip - to boot natively from flash
+device geom_uncompress
+options GEOM_UNCOMPRESS
+
+# Used for the static uboot partition map
+device geom_map
+
+# Boot off of the rootfs, as defined in the geom_map setup.
+options ROOTDEVNAME=\"ufs:map/rootfs.uncompress\"
Property changes on: trunk/sys/mips/conf/AP121
___________________________________________________________________
Added: mnbsd:nokeywords
## -0,0 +1 ##
+MidnightBSD=%H
\ No newline at end of property
Added: trunk/sys/mips/conf/AP121.hints
===================================================================
--- trunk/sys/mips/conf/AP121.hints (rev 0)
+++ trunk/sys/mips/conf/AP121.hints 2018-05-26 21:55:02 UTC (rev 9987)
@@ -0,0 +1,107 @@
+#
+# This file adds to the values in AR91XX_BASE.hints.
+#
+# $FreeBSD: stable/10/sys/mips/conf/AP121.hints 249127 2013-04-05 02:15:10Z adrian $
+
+# mdiobus on arge1
+hint.argemdio.0.at="nexus0"
+hint.argemdio.0.maddr=0x1a000000
+hint.argemdio.0.msize=0x1000
+hint.argemdio.0.order=0
+
+# Embedded Atheros Switch
+hint.arswitch.0.at="mdio0"
+hint.arswitch.0.is_7240=1
+hint.arswitch.0.numphys=4
+hint.arswitch.0.phy4cpu=1 # phy 4 is a "CPU" separate PHY
+hint.arswitch.0.is_rgmii=0
+hint.arswitch.0.is_gmii=1 # arge1 <-> switch PHY is GMII
+
+# arge0 - MII, autoneg, phy(4)
+hint.arge.0.phymask=0x10 # PHY4
+hint.arge.0.mdio=mdioproxy1 # .. off of the switch mdiobus
+
+# arge1 - GMII, 1000/full
+hint.arge.1.phymask=0x0 # No directly mapped PHYs
+hint.arge.1.media=1000
+hint.arge.1.fduplex=1
+
+# The AP121 4MB flash layout:
+#
+# bootargs=console=ttyS0,115200 root=31:02 rootfstype=squashfs
+# init=/sbin/init mtdparts=ar7240-nor0:256k(u-boot),64k(u-boot-env),
+# 2752k(rootfs),896k(uImage),64k(NVRAM),64k(ART)
+#
+# So:
+# 256k: uboot
+# 64: uboot-env
+# 2752k: rootfs
+# 896k: kernel
+# 64k: config
+# 64k: ART
+
+hint.map.0.at="flash/spi0"
+hint.map.0.start=0x00000000
+hint.map.0.end=0x000040000
+hint.map.0.name="uboot"
+hint.map.0.readonly=1
+
+hint.map.1.at="flash/spi0"
+hint.map.1.start=0x00040000
+hint.map.1.end=0x00050000
+hint.map.1.name="uboot-env"
+hint.map.1.readonly=0
+
+hint.map.2.at="flash/spi0"
+hint.map.2.start=0x00050000
+hint.map.2.end=0x00300000
+hint.map.2.name="rootfs"
+hint.map.2.readonly=0
+
+hint.map.3.at="flash/spi0"
+hint.map.3.start=0x00300000
+hint.map.3.end=0x003e0000
+hint.map.3.name="kernel"
+hint.map.3.readonly=0
+
+hint.map.4.at="flash/spi0"
+hint.map.4.start=0x003e0000
+hint.map.4.end=0x003f0000
+hint.map.4.name="cfg"
+hint.map.4.readonly=0
+
+# This is radio calibration section. It is (or should be!) unique
+# for each board, to take into account thermal and electrical differences
+# as well as the regulatory compliance data.
+#
+hint.map.5.at="flash/spi0"
+hint.map.5.start=0x003f0000
+hint.map.5.end=0x00400000
+hint.map.5.name="art"
+hint.map.5.readonly=1
+
+# GPIO specific configuration block
+
+# Don't flip on anything that isn't already enabled.
+# This includes leaving the SPI CS1/CS2 pins as GPIO pins as they're
+# not used here.
+hint.gpio.0.function_set=0x00000000
+hint.gpio.0.function_clear=0x00000000
+
+# These are the GPIO LEDs and buttons which can be software controlled.
+#hint.gpio.0.pinmask=0x001c02ae
+hint.gpio.0.pinmask=0x00001803
+
+# gpio0 - WLAN LED
+# gpio1 - USB LED
+# gpio11 - Jumpstart button
+# gpio12 - Reset button
+
+# LEDs are configured separately and driven by the LED device
+hint.gpioled.0.at="gpiobus0"
+hint.gpioled.0.name="wlan"
+hint.gpioled.0.pins=0x0001
+
+hint.gpioled.1.at="gpiobus0"
+hint.gpioled.1.name="usb"
+hint.gpioled.1.pins=0x0002
Property changes on: trunk/sys/mips/conf/AP121.hints
___________________________________________________________________
Added: mnbsd:nokeywords
## -0,0 +1 ##
+MidnightBSD=%H
\ No newline at end of property
Added: trunk/sys/mips/conf/AP91
===================================================================
--- trunk/sys/mips/conf/AP91 (rev 0)
+++ trunk/sys/mips/conf/AP91 2018-05-26 21:55:02 UTC (rev 9987)
@@ -0,0 +1,64 @@
+#
+# Specific board setup for the Atheros AP91 reference board.
+#
+# The AP91 has the following hardware:
+#
+# + AR7241 CPU SoC
+# + AR9287 Wifi
+# + Integrated switch (XXX speed?)
+# + 4MB flash
+# + 16MB RAM
+# + uboot environment
+
+# $FreeBSD: stable/10/sys/mips/conf/AP91 266331 2014-05-17 17:34:37Z ian $
+
+include "AR724X_BASE"
+ident "AP91"
+hints "AP91.hints"
+
+options AR71XX_REALMEM=16*1024*1024
+
+options AR71XX_ENV_UBOOT
+
+# Limit inlines
+makeoptions INLINE_LIMIT=768
+
+# We bite the performance overhead for now; the kernel won't
+# fit if the mutexes are inlined.
+options MUTEX_NOINLINE
+options RWLOCK_NOINLINE
+options SX_NOINLINE
+
+# There's no need to enable swapping on this platform.
+options NO_SWAPPING
+
+# For DOS - enable if required
+# options MSDOSFS
+
+# uncompress - to boot read-only lzma natively from flash
+device geom_uncompress
+options GEOM_UNCOMPRESS
+options ROOTDEVNAME=\"ufs:/dev/map/rootfs.uncompress\"
+
+# Not enough space for these..
+nooptions INVARIANTS
+nooptions INVARIANT_SUPPORT
+nooptions WITNESS
+nooptions WITNESS_SKIPSPIN
+nooptions DEBUG_REDZONE
+nooptions DEBUG_MEMGUARD
+
+# Used for the static uboot partition map
+device geom_map
+
+# Options needed for the EEPROM based calibration/PCI configuration data.
+options AR71XX_ATH_EEPROM # Fetch EEPROM/PCI config from flash
+options ATH_EEPROM_FIRMWARE # Use EEPROM from flash
+device firmware # Used by the above
+
+# Options required for miiproxy and mdiobus
+options ARGE_MDIO # Export an MDIO bus separate from arge
+device miiproxy # MDIO bus <-> MII PHY rendezvous
+
+device etherswitch
+device arswitch
Property changes on: trunk/sys/mips/conf/AP91
___________________________________________________________________
Added: mnbsd:nokeywords
## -0,0 +1 ##
+MidnightBSD=%H
\ No newline at end of property
Added: trunk/sys/mips/conf/AP91.hints
===================================================================
--- trunk/sys/mips/conf/AP91.hints (rev 0)
+++ trunk/sys/mips/conf/AP91.hints 2018-05-26 21:55:02 UTC (rev 9987)
@@ -0,0 +1,104 @@
+# $FreeBSD: stable/10/sys/mips/conf/AP91.hints 242718 2012-11-07 22:46:30Z ray $
+
+# arge0 MDIO bus
+hint.argemdio.0.at="nexus0"
+hint.argemdio.0.maddr=0x19000000
+hint.argemdio.0.msize=0x1000
+hint.argemdio.0.order=0
+
+# arge1 MDIO bus doesn't exist on the AR7240
+
+# arge0: MII; dedicated PHY 4 on switch, connected via internal switch
+# MDIO bus.
+
+hint.arge.0.at="nexus0"
+hint.arge.0.maddr=0x19000000
+hint.arge.0.msize=0x1000
+hint.arge.0.irq=2
+# hint.arge.0.eeprommac=0x83fe9ff0
+hint.arge.0.phymask=0x10 # PHY 4
+# hint.arge.0.miimode=2 # MII
+hint.arge.0.mdio=mdioproxy1 # Hanging off the arswitch MDIO bus
+
+# arge1: connected to the LAN switch MAC, at 1000BaseTX / GMII.
+
+hint.arge.1.phymask=0x0
+# hint.arge.1.miimode=1 # GMII
+hint.arge.1.media=1000 # Force to 1000BaseTX/full
+hint.arge.1.fduplex=1
+
+#
+# AR7240 switch config
+#
+hint.arswitch.0.at="mdio0"
+hint.arswitch.0.is_7240=1 # We need to be explicitly told this
+hint.arswitch.0.numphys=4 # 4 active switch PHYs (PHY 0 -> 3)
+hint.arswitch.0.phy4cpu=1 # Yes, PHY 4 == dedicated PHY
+hint.arswitch.0.is_rgmii=0 # No, not RGMII
+hint.arswitch.0.is_gmii=0 # No, not GMII
+
+# ath0 hint - pcie slot 0
+hint.pcib.0.bus.0.0.0.ath_fixup_addr=0x1fff1000
+hint.pcib.0.bus.0.0.0.ath_fixup_size=4096
+
+# ath
+hint.ath.0.eeprom_firmware="pcib.0.bus.0.0.0.eeprom_firmware"
+
+# Signal leds
+hint.gpioled.0.at="gpiobus0"
+hint.gpioled.0.name="sig1"
+hint.gpioled.0.pins=0x0001 # pin 0
+hint.gpioled.1.at="gpiobus0"
+hint.gpioled.1.name="sig2"
+hint.gpioled.1.pins=0x0002 # pin 1
+hint.gpioled.2.at="gpiobus0"
+hint.gpioled.2.name="sig3"
+hint.gpioled.2.pins=0x0800 # pin 11
+hint.gpioled.3.at="gpiobus0"
+hint.gpioled.3.name="sig4"
+hint.gpioled.3.pins=0x0080 # pin 7
+
+# nvram mapping - XXX ?
+hint.nvram.0.base=0x1f030000
+hint.nvram.0.maxsize=0x2000
+hint.nvram.0.flags=3 # 1 = No check, 2 = Format Generic
+hint.nvram.1.base=0x1f032000
+hint.nvram.1.maxsize=0x4000
+hint.nvram.1.flags=3 # 1 = No check, 2 = Format Generic
+
+# GEOM_MAP
+#
+# From my AP91 environment:
+#
+# mtdparts=ar7240-nor0:256k(u-boot),64k(u-boot-env),2752k(rootfs),
+# 960k(uImage),64k(ART)
+
+hint.map.0.at="flash/spi0"
+hint.map.0.start=0x00000000
+hint.map.0.end=0x00040000 # 256k u-boot
+hint.map.0.name="u-boot"
+hint.map.0.readonly=1
+
+hint.map.1.at="flash/spi0"
+hint.map.1.start=0x00040000
+hint.map.1.end=0x00050000 # 64k u-boot-env
+hint.map.1.name="u-boot-env"
+hint.map.1.readonly=0
+
+hint.map.2.at="flash/spi0"
+hint.map.2.start=0x00050000
+hint.map.2.end=0x00300000 # 2752k rootfs
+hint.map.2.name="rootfs"
+hint.map.2.readonly=1
+
+hint.map.3.at="flash/spi0"
+hint.map.3.start=0x00300000
+hint.map.3.end=0x003f0000 # 896k uImage
+hint.map.3.name="uImage"
+hint.map.3.readonly=1
+
+hint.map.4.at="flash/spi0"
+hint.map.4.start=0x003f0000
+hint.map.4.end=0x00400000 # 64k ART
+hint.map.4.name="ART"
+hint.map.4.readonly=1
Property changes on: trunk/sys/mips/conf/AP91.hints
___________________________________________________________________
Added: mnbsd:nokeywords
## -0,0 +1 ##
+MidnightBSD=%H
\ No newline at end of property
Added: trunk/sys/mips/conf/AP93
===================================================================
--- trunk/sys/mips/conf/AP93 (rev 0)
+++ trunk/sys/mips/conf/AP93 2018-05-26 21:55:02 UTC (rev 9987)
@@ -0,0 +1,44 @@
+#
+# Specific board setup for the Atheros AP91 reference board.
+#
+# The AP93 has the following hardware:
+#
+# + AR7240 CPU SoC
+# + AR9280 Wifi
+# + Integrated switch (XXX speed?)
+# + 16MB flash
+# + 64MB RAM
+# + uboot environment
+
+# $FreeBSD: stable/10/sys/mips/conf/AP93 266331 2014-05-17 17:34:37Z ian $
+
+include "AR724X_BASE"
+ident "AP93"
+hints "AP93.hints"
+
+options AR71XX_REALMEM=64*1024*1024
+
+options AR71XX_ENV_UBOOT
+
+# For DOS - enable if required
+options MSDOSFS
+
+# uncompress - to boot read-only lzma natively from flash
+device geom_uncompress
+options GEOM_UNCOMPRESS
+options ROOTDEVNAME=\"ufs:/dev/map/rootfs.uncompress\"
+
+# Used for the static uboot partition map
+device geom_map
+
+# Options needed for the EEPROM based calibration/PCI configuration data.
+options AR71XX_ATH_EEPROM # Fetch EEPROM/PCI config from flash
+options ATH_EEPROM_FIRMWARE # Use EEPROM from flash
+device firmware # Used by the above
+
+# Options required for miiproxy and mdiobus
+options ARGE_MDIO # Export an MDIO bus separate from arge
+device miiproxy # MDIO bus <-> MII PHY rendezvous
+
+device etherswitch
+device arswitch
Property changes on: trunk/sys/mips/conf/AP93
___________________________________________________________________
Added: mnbsd:nokeywords
## -0,0 +1 ##
+MidnightBSD=%H
\ No newline at end of property
Added: trunk/sys/mips/conf/AP93.hints
===================================================================
--- trunk/sys/mips/conf/AP93.hints (rev 0)
+++ trunk/sys/mips/conf/AP93.hints 2018-05-26 21:55:02 UTC (rev 9987)
@@ -0,0 +1,150 @@
+# $FreeBSD: stable/10/sys/mips/conf/AP93.hints 252689 2013-07-04 08:09:54Z adrian $
+
+# arge0 MDIO bus
+hint.argemdio.0.at="nexus0"
+hint.argemdio.0.maddr=0x19000000
+hint.argemdio.0.msize=0x1000
+hint.argemdio.0.order=0
+
+# arge1 MDIO bus doesn't exist on the AR7240
+
+# arge0: MII; dedicated PHY 4 on switch, connected via internal switch
+# MDIO bus.
+
+# hint.arge.0.eeprommac=0x83fe9ff0
+hint.arge.0.phymask=0x10 # PHY 4
+# hint.arge.0.miimode=2 # MII
+hint.arge.0.mdio=mdioproxy1 # Hanging off the arswitch MDIO bus
+
+# arge1: connected to the LAN switch MAC, at 1000BaseTX / GMII.
+hint.arge.1.phymask=0x0
+# hint.arge.1.miimode=1 # GMII
+hint.arge.1.media=1000 # Force to 1000BaseTX/full
+hint.arge.1.fduplex=1
+
+#
+# AR7240 switch config
+#
+hint.arswitch.0.at="mdio0"
+hint.arswitch.0.is_7240=1 # We need to be explicitly told this
+hint.arswitch.0.numphys=4 # 4 active switch PHYs (PHY 0 -> 3)
+hint.arswitch.0.phy4cpu=1 # Yes, PHY 4 == dedicated PHY
+hint.arswitch.0.is_rgmii=0 # No, not RGMII
+hint.arswitch.0.is_gmii=0 # No, not GMII
+
+# ath0 hint - pcie slot 0
+hint.pcib.0.bus.0.0.0.ath_fixup_addr=0x1fff1000
+hint.pcib.0.bus.0.0.0.ath_fixup_size=4096
+
+# ath0 - eeprom comes from here
+hint.ath.0.eeprom_firmware="pcib.0.bus.0.0.0.eeprom_firmware"
+
+# Signal leds
+hint.gpioled.0.at="gpiobus0"
+hint.gpioled.0.name="sig1"
+hint.gpioled.0.pins=0x0001 # pin 0
+hint.gpioled.1.at="gpiobus0"
+hint.gpioled.1.name="sig2"
+hint.gpioled.1.pins=0x0002 # pin 1
+hint.gpioled.2.at="gpiobus0"
+hint.gpioled.2.name="sig3"
+hint.gpioled.2.pins=0x0800 # pin 11
+hint.gpioled.3.at="gpiobus0"
+hint.gpioled.3.name="sig4"
+hint.gpioled.3.pins=0x0080 # pin 7
+
+# nvram mapping - XXX ?
+hint.nvram.0.base=0x1f030000
+hint.nvram.0.maxsize=0x2000
+hint.nvram.0.flags=3 # 1 = No check, 2 = Format Generic
+hint.nvram.1.base=0x1f032000
+hint.nvram.1.maxsize=0x4000
+hint.nvram.1.flags=3 # 1 = No check, 2 = Format Generic
+
+# GEOM_MAP
+#
+# From my AP93 environment:
+#
+# 256k - uboot
+# 256k - uboot-env
+# 3072k - spare-rootfs
+# 1024k - spare-uImage
+# 3072k - rootfs
+# 1024k - uImage
+# 64k - mib0
+# 64k - mib1
+# 4096k - ct
+# 3392k - var
+# 64k - ART
+
+# To make it useful for FreeBSD for now, treat spare rootfs, spare
+# uimage and rootfs as 'rootfs'.
+
+hint.map.0.at="flash/spi0"
+hint.map.0.start=0x00000000
+hint.map.0.end=0x00040000
+hint.map.0.name="uboot"
+hint.map.0.readonly=1
+
+hint.map.1.at="flash/spi0"
+hint.map.1.start=0x00040000
+hint.map.1.end=0x00080000
+hint.map.1.name="uboot-env"
+hint.map.1.readonly=1
+
+hint.map.2.at="flash/spi0"
+hint.map.2.start=0x00080000
+# hint.map.2.end=0x00380000
+hint.map.2.end=0x00780000
+# hint.map.2.name="spare-rootfs"
+hint.map.2.name="rootfs"
+hint.map.2.readonly=1
+
+#hint.map.3.at="flash/spi0"
+#hint.map.3.start=0x00380000
+#hint.map.3.end=0x00480000
+#hint.map.3.name="spare-uImage"
+#hint.map.3.readonly=1
+
+#hint.map.4.at="flash/spi0"
+#hint.map.4.start=0x00480000
+#hint.map.4.end=0x00780000
+#hint.map.4.name="rootfs"
+#hint.map.4.readonly=1
+
+hint.map.3.at="flash/spi0"
+hint.map.3.start=0x00780000
+hint.map.3.end=0x00880000
+hint.map.3.name="uImage"
+hint.map.3.readonly=1
+
+hint.map.4.at="flash/spi0"
+hint.map.4.start=0x00880000
+hint.map.4.end=0x00890000
+hint.map.4.name="mib0"
+hint.map.4.readonly=1
+
+hint.map.5.at="flash/spi0"
+hint.map.5.start=0x00890000
+hint.map.5.end=0x008a0000
+hint.map.5.name="mib1"
+hint.map.5.readonly=1
+
+hint.map.6.at="flash/spi0"
+hint.map.6.start=0x008a0000
+hint.map.6.end=0x00ca0000
+hint.map.6.name="ct"
+hint.map.6.readonly=1
+
+hint.map.7.at="flash/spi0"
+hint.map.7.start=0x00ca0000
+hint.map.7.end=0x00ff0000
+hint.map.7.name="var"
+hint.map.7.readonly=1
+
+hint.map.8.at="flash/spi0"
+hint.map.8.start=0x00ff0000
+hint.map.8.end=0x01000000 # 64k ART
+hint.map.8.name="ART"
+hint.map.8.readonly=1
+
Property changes on: trunk/sys/mips/conf/AP93.hints
___________________________________________________________________
Added: mnbsd:nokeywords
## -0,0 +1 ##
+MidnightBSD=%H
\ No newline at end of property
Added: trunk/sys/mips/conf/AP94
===================================================================
--- trunk/sys/mips/conf/AP94 (rev 0)
+++ trunk/sys/mips/conf/AP94 2018-05-26 21:55:02 UTC (rev 9987)
@@ -0,0 +1,35 @@
+#
+# Specific board setup for the Atheros AP94 reference board.
+#
+# The AP94 has the following hardware:
+#
+# + AR7161 CPU SoC
+# + AR9223 2.4GHz 11n
+# + AR9220 5GHz 11n
+# + AR8216 10/100 switch
+# + m25p64 based 8MB flash
+# + 32mb RAM
+# + uboot environment
+
+# $FreeBSD: stable/10/sys/mips/conf/AP94 266331 2014-05-17 17:34:37Z ian $
+
+include "AR71XX_BASE"
+ident "AP94"
+hints "AP94.hints"
+
+# GEOM modules
+device geom_redboot # to get access to the SPI flash partitions
+device geom_uzip # compressed in-memory filesystem hackery!
+options GEOM_UZIP
+
+options ROOTDEVNAME=\"ufs:md0.uzip\"
+options AR71XX_REALMEM=32*1024*1024
+
+options AR71XX_ENV_UBOOT
+
+# options MD_ROOT
+# options MD_ROOT_SIZE="6144"
+
+options AR71XX_ATH_EEPROM # Fetch EEPROM/PCI config from flash
+options ATH_EEPROM_FIRMWARE # Use EEPROM from flash
+device firmware # Used by the above
Property changes on: trunk/sys/mips/conf/AP94
___________________________________________________________________
Added: mnbsd:nokeywords
## -0,0 +1 ##
+MidnightBSD=%H
\ No newline at end of property
Added: trunk/sys/mips/conf/AP94.hints
===================================================================
--- trunk/sys/mips/conf/AP94.hints (rev 0)
+++ trunk/sys/mips/conf/AP94.hints 2018-05-26 21:55:02 UTC (rev 9987)
@@ -0,0 +1,28 @@
+# $FreeBSD: stable/10/sys/mips/conf/AP94.hints 234219 2012-04-13 08:52:25Z adrian $
+
+hint.arge.0.phymask=0x000c
+hint.arge.0.media=100
+hint.arge.0.fduplex=1
+
+# XXX grab these from uboot?
+# hint.arge.0.eeprommac=0x1f01fc00
+
+# The ath NICs have calibration data in flash.
+# PCI slot 17
+# hint.ath.0.eepromaddr=0x1fff1000
+# PCI slot 18
+# hint.ath.1.eepromaddr=0x1fff5000
+
+# ath0 - slot 17
+hint.pcib.0.bus.0.17.0.ath_fixup_addr=0x1fff1000
+hint.pcib.0.bus.0.17.0.ath_fixup_size=4096
+
+# ath1 - slot 18
+hint.pcib.0.bus.0.18.0.ath_fixup_addr=0x1fff5000
+hint.pcib.0.bus.0.18.0.ath_fixup_size=4096
+
+# .. and now, telling each ath(4) NIC where to find the firmware
+# image.
+hint.ath.0.eeprom_firmware="pcib.0.bus.0.17.0.eeprom_firmware"
+hint.ath.1.eeprom_firmware="pcib.0.bus.0.18.0.eeprom_firmware"
+
Property changes on: trunk/sys/mips/conf/AP94.hints
___________________________________________________________________
Added: mnbsd:nokeywords
## -0,0 +1 ##
+MidnightBSD=%H
\ No newline at end of property
Added: trunk/sys/mips/conf/AP96
===================================================================
--- trunk/sys/mips/conf/AP96 (rev 0)
+++ trunk/sys/mips/conf/AP96 2018-05-26 21:55:02 UTC (rev 9987)
@@ -0,0 +1,45 @@
+#
+# Specific board setup for the Atheros AP96 reference board.
+#
+# The AP96 has the following hardware:
+#
+# + AR7161 CPU SoC
+# + AR9223 2.4GHz 11n
+# + AR9220 5GHz 11n
+# + AR8316 10/100/1000 switch
+# + m25p64 based 8MB flash
+# + 64mb RAM
+# + uboot environment
+
+# $FreeBSD: stable/10/sys/mips/conf/AP96 266331 2014-05-17 17:34:37Z ian $
+
+include "AR71XX_BASE"
+ident "AP96"
+hints "AP96.hints"
+
+options AR71XX_REALMEM=64*1024*1024
+
+options AR71XX_ENV_UBOOT
+
+# For DOS - enable if required
+options MSDOSFS
+
+# uncompress - to boot read-only lzma natively from flash
+device geom_uncompress
+options GEOM_UNCOMPRESS
+options ROOTDEVNAME=\"ufs:/dev/map/rootfs.uncompress\"
+
+# Used for the static uboot partition map
+device geom_map
+
+# Options needed for the EEPROM based calibration/PCI configuration data.
+options AR71XX_ATH_EEPROM # Fetch EEPROM/PCI config from flash
+options ATH_EEPROM_FIRMWARE # Use EEPROM from flash
+device firmware # Used by the above
+
+# Options required for miiproxy and mdiobus
+options ARGE_MDIO # Export an MDIO bus separate from arge
+device miiproxy # MDIO bus <-> MII PHY rendezvous
+
+device etherswitch
+device arswitch
Property changes on: trunk/sys/mips/conf/AP96
___________________________________________________________________
Added: mnbsd:nokeywords
## -0,0 +1 ##
+MidnightBSD=%H
\ No newline at end of property
Added: trunk/sys/mips/conf/AP96.hints
===================================================================
--- trunk/sys/mips/conf/AP96.hints (rev 0)
+++ trunk/sys/mips/conf/AP96.hints 2018-05-26 21:55:02 UTC (rev 9987)
@@ -0,0 +1,97 @@
+# $FreeBSD: stable/10/sys/mips/conf/AP96.hints 242724 2012-11-07 23:50:28Z adrian $
+
+# arge0 MDIO bus - there's no arge1 MDIO bus for AR71xx
+hint.argemdio.0.at="nexus0"
+hint.argemdio.0.maddr=0x19000000
+hint.argemdio.0.msize=0x1000
+hint.argemdio.0.order=0
+# This creates an automatic mdioproxy0!
+
+
+# The switch automatically probes off of mdio0, and will
+# create an mdioproxy1.
+
+# TODO: RGMII
+hint.arge.0.phymask=0x0 # Nothing attached here (XXX?)
+hint.arge.0.media=1000
+hint.arge.0.fduplex=1
+hint.arge.0.miimode=3 # RGMII
+
+# TODO: RGMII
+hint.arge.1.phymask=0x10
+# hint.arge.1.pll_1000 = 0x1f000000
+# For now, rendezouvs this on the arge0 mdiobus.
+# Later, this will rendezvous via the AR8316 switch.
+hint.arge.1.miimode=3 # RGMII
+hint.arge.1.mdio=mdioproxy1 # off the switch mdiobus
+
+# AR8316 switch on MDIO0
+hint.arswitch.0.at="mdio0"
+hint.arswitch.0.is_7240=0
+hint.arswitch.0.numphys=4
+hint.arswitch.0.phy4cpu=1
+hint.arswitch.0.is_rgmii=1
+hint.arswitch.0.is_gmii=0
+
+# ath0 - slot 17
+hint.pcib.0.bus.0.17.0.ath_fixup_addr=0x1fff1000
+hint.pcib.0.bus.0.17.0.ath_fixup_size=4096
+
+# ath1 - slot 18
+hint.pcib.0.bus.0.18.0.ath_fixup_addr=0x1fff5000
+hint.pcib.0.bus.0.18.0.ath_fixup_size=4096
+
+# .. and now, telling each ath(4) NIC where to find the firmware
+# image.
+hint.ath.0.eeprom_firmware="pcib.0.bus.0.17.0.eeprom_firmware"
+hint.ath.1.eeprom_firmware="pcib.0.bus.0.18.0.eeprom_firmware"
+
+# The default flash layout:
+# uboot: 192k
+# env: 64k
+# rootfs: 6144k
+# uimage (kernel): 1728k
+# caldata: 64k
+#
+# bootargs=console=ttyS0,115200 root=31:02 rootfstype=jffs2 init=/sbin/init
+# mtdparts=ar7100-nor0:192k(uboot),64k(env),6144k(rootfs),1728k(uImage),64k(caldata) mem=64M
+
+#
+# We steal 64k from the end of rootfs to store the local config.
+
+hint.map.0.at="flash/spi0"
+hint.map.0.start=0x00000000
+hint.map.0.end=0x000030000
+hint.map.0.name="uboot"
+hint.map.0.readonly=1
+
+hint.map.1.at="flash/spi0"
+hint.map.1.start=0x00030000
+hint.map.1.end=0x00040000
+hint.map.1.name="uboot-env"
+hint.map.1.readonly=1
+
+hint.map.2.at="flash/spi0"
+hint.map.2.start=0x00040000
+hint.map.2.end=0x00630000
+hint.map.2.name="rootfs"
+hint.map.2.readonly=1
+
+hint.map.3.at="flash/spi0"
+hint.map.3.start=0x00630000
+hint.map.3.end=0x00640000
+hint.map.3.name="cfg"
+hint.map.3.readonly=0
+
+hint.map.4.at="flash/spi0"
+hint.map.4.start=0x00640000
+hint.map.4.end=0x007f0000
+hint.map.4.name="kernel"
+hint.map.4.readonly=1
+
+hint.map.5.at="flash/spi0"
+hint.map.5.start=0x007f0000
+hint.map.5.end=0x00800000
+hint.map.5.name="art"
+hint.map.5.readonly=1
+
Property changes on: trunk/sys/mips/conf/AP96.hints
___________________________________________________________________
Added: mnbsd:nokeywords
## -0,0 +1 ##
+MidnightBSD=%H
\ No newline at end of property
Added: trunk/sys/mips/conf/AR71XX_BASE
===================================================================
--- trunk/sys/mips/conf/AR71XX_BASE (rev 0)
+++ trunk/sys/mips/conf/AR71XX_BASE 2018-05-26 21:55:02 UTC (rev 9987)
@@ -0,0 +1,126 @@
+#
+# AR71XX -- Kernel configuration file for FreeBSD/MIPS for Atheros 71xx systems
+#
+# This includes all the common drivers for the AR71XX boards along with
+# the usb, net80211 and atheros driver code.
+#
+# $FreeBSD: stable/10/sys/mips/conf/AR71XX_BASE 266331 2014-05-17 17:34:37Z ian $
+#
+
+machine mips mips
+ident AR71XX_BASE
+cpu CPU_MIPS4KC
+makeoptions KERNLOADADDR=0x80050000
+options HZ=1000
+options HWPMC_HOOKS
+
+files "../atheros/files.ar71xx"
+
+# For now, hints are per-board.
+
+hints "AR71XX_BASE.hints"
+
+makeoptions DEBUG=-g #Build kernel with gdb(1) debug symbols
+
+# Build these as modules so small platform builds will have the
+# modules already built.
+makeoptions MODULES_OVERRIDE="random gpio ar71xx if_gif if_gre if_bridge bridgestp usb wlan wlan_xauth wlan_acl wlan_wep wlan_tkip wlan_ccmp wlan_rssadapt wlan_amrr ath ath_pci"
+
+options DDB
+options KDB
+
+options SCHED_4BSD #4BSD scheduler
+options INET #InterNETworking
+options INET6 # IPv6
+
+# options NFSCL #Network Filesystem Client
+
+options PSEUDOFS #Pseudo-filesystem framework
+options _KPOSIX_PRIORITY_SCHEDULING #Posix P1003_1B real-time extensions
+
+# options NFS_LEGACYRPC
+# Debugging for use in -current
+options INVARIANTS
+options INVARIANT_SUPPORT
+options WITNESS
+options WITNESS_SKIPSPIN
+options DEBUG_REDZONE
+options DEBUG_MEMGUARD
+
+options FFS #Berkeley Fast Filesystem
+# options SOFTUPDATES #Enable FFS soft updates support
+# options UFS_ACL #Support for access control lists
+# options UFS_DIRHASH #Improve performance on big directories
+# options MSDOSFS # Read MSDOS filesystems; useful for USB/CF
+
+device pci
+device ar71xx_pci
+
+# 802.11 framework
+options IEEE80211_DEBUG
+options IEEE80211_ALQ
+options IEEE80211_SUPPORT_MESH
+# This option is currently broken for if_ath_tx.
+options IEEE80211_SUPPORT_TDMA
+options IEEE80211_AMPDU_AGE
+device wlan # 802.11 support
+device wlan_wep # 802.11 WEP support
+device wlan_ccmp # 802.11 CCMP support
+device wlan_tkip # 802.11 TKIP support
+device wlan_xauth # 802.11 hostap support
+
+# Atheros wireless NICs
+device ath # Atheros interface support
+device ath_pci # Atheros PCI/Cardbus bus
+options ATH_DEBUG
+options ATH_DIAGAPI
+options ATH_ENABLE_11N
+options AH_DEBUG
+options AH_DEBUG_ALQ
+options ALQ
+device ath_hal
+option AH_SUPPORT_AR5416
+device ath_rate_sample
+option AH_RXCFG_SDMAMW_4BYTES
+option AH_AR5416_INTERRUPT_MITIGATION
+# There's no DFS radar detection support yet so this won't actually
+# detect radars. It however does enable the rest of the channel change
+# machinery so DFS can be debugged.
+option ATH_ENABLE_DFS
+
+device mii
+device arge
+
+device usb
+options USB_EHCI_BIG_ENDIAN_DESC # handle big-endian byte order
+options USB_DEBUG
+options USB_HOST_ALIGN=32 # AR71XX (MIPS in general?) requires this
+device ehci
+
+device scbus
+device umass
+device da
+
+# On-board SPI flash
+device spibus
+device ar71xx_spi
+device mx25l
+device ar71xx_wdog
+
+device uart
+device uart_ar71xx
+
+device loop
+device ether
+device md
+device bpf
+device random
+device if_bridge
+device gif # ip[46] in ip[46] tunneling protocol
+device gre # generic encapsulation - only for IPv4 in IPv4 though atm
+
+options ARGE_DEBUG # Enable if_arge debugging for now
+
+# Enable GPIO
+device gpio
+device gpioled
Property changes on: trunk/sys/mips/conf/AR71XX_BASE
___________________________________________________________________
Added: mnbsd:nokeywords
## -0,0 +1 ##
+MidnightBSD=%H
\ No newline at end of property
Added: trunk/sys/mips/conf/AR71XX_BASE.hints
===================================================================
--- trunk/sys/mips/conf/AR71XX_BASE.hints (rev 0)
+++ trunk/sys/mips/conf/AR71XX_BASE.hints 2018-05-26 21:55:02 UTC (rev 9987)
@@ -0,0 +1,66 @@
+#
+# $FreeBSD: stable/10/sys/mips/conf/AR71XX_BASE.hints 228944 2011-12-29 05:51:48Z adrian $
+#
+hint.apb.0.at="nexus0"
+hint.apb.0.irq=4
+
+# uart0
+hint.uart.0.at="apb0"
+# see atheros/uart_cpu_ar71xx.c why +3
+hint.uart.0.maddr=0x18020003
+hint.uart.0.msize=0x18
+hint.uart.0.irq=3
+
+#ohci
+hint.ohci.0.at="apb0"
+hint.ohci.0.maddr=0x1c000000
+hint.ohci.0.msize=0x01000000
+hint.ohci.0.irq=6
+
+#ehci
+hint.ehci.0.at="nexus0"
+hint.ehci.0.maddr=0x1b000000
+hint.ehci.0.msize=0x01000000
+hint.ehci.0.irq=1
+
+# pci
+hint.pcib.0.at="nexus0"
+hint.pcib.0.irq=0
+
+hint.arge.0.at="nexus0"
+hint.arge.0.maddr=0x19000000
+hint.arge.0.msize=0x1000
+hint.arge.0.irq=2
+
+# phymask, media and fduplex depend upon the specific
+# board.
+# So each board will override the settings as needed.
+
+hint.arge.1.at="nexus0"
+hint.arge.1.maddr=0x1a000000
+hint.arge.1.msize=0x1000
+hint.arge.1.irq=3
+
+# SPI flash
+hint.spi.0.at="nexus0"
+hint.spi.0.maddr=0x1f000000
+hint.spi.0.msize=0x10
+
+hint.mx25l.0.at="spibus0"
+hint.mx25l.0.cs=0
+
+# Watchdog
+hint.ar71xx_wdog.0.at="nexus0"
+
+# GPIO
+hint.gpio.0.at="apb0"
+hint.gpio.0.maddr=0x18040000
+hint.gpio.0.msize=0x1000
+hint.gpio.0.irq=2
+
+# Each board should override the GPIO bus pins with the configuration
+# relevant to it. Thus no pins are defined here.
+
+# hwpmc device
+hint.ar71xx_pmc.0.at="apb0"
+hint.ar71xx_pmc.0.irq=5
Property changes on: trunk/sys/mips/conf/AR71XX_BASE.hints
___________________________________________________________________
Added: mnbsd:nokeywords
## -0,0 +1 ##
+MidnightBSD=%H
\ No newline at end of property
Added: trunk/sys/mips/conf/AR724X_BASE
===================================================================
--- trunk/sys/mips/conf/AR724X_BASE (rev 0)
+++ trunk/sys/mips/conf/AR724X_BASE 2018-05-26 21:55:02 UTC (rev 9987)
@@ -0,0 +1,133 @@
+#
+# AR724X -- Kernel configuration file for FreeBSD/MIPS for Atheros 724x systems
+#
+# This includes all the common drivers for the AR724x boards.
+# Since the AR724x boards tend to have minimal flash (sometimes 4MB!),
+# the majority of the kernel framework will be built as modules.
+#
+# $FreeBSD: stable/10/sys/mips/conf/AR724X_BASE 266331 2014-05-17 17:34:37Z ian $
+#
+
+machine mips mips
+ident AR724X_BASE
+cpu CPU_MIPS4KC
+makeoptions KERNLOADADDR=0x80050000
+options HZ=1000
+options HWPMC_HOOKS
+
+files "../atheros/files.ar71xx"
+
+# For now, hints are per-board.
+
+hints "AR724X_BASE.hints"
+
+makeoptions DEBUG=-g #Build kernel with gdb(1) debug symbols
+
+# Build these as modules so small platform builds will have the
+# modules already built.
+makeoptions MODULES_OVERRIDE="random gpio ar71xx if_gif if_gre if_bridge bridgestp usb wlan wlan_xauth wlan_acl wlan_wep wlan_tkip wlan_ccmp wlan_rssadapt wlan_amrr ath ath_pci hwpmc cam"
+
+options DDB
+options KDB
+
+options SCHED_4BSD #4BSD scheduler
+options INET #InterNETworking
+#options INET6 # IPv6
+#options NFSCL #Network Filesystem Client
+options PSEUDOFS #Pseudo-filesystem framework
+options _KPOSIX_PRIORITY_SCHEDULING #Posix P1003_1B real-time extensions
+
+#options NFS_LEGACYRPC
+# Debugging for use in -current
+options INVARIANTS
+options INVARIANT_SUPPORT
+options WITNESS
+options WITNESS_SKIPSPIN
+options DEBUG_REDZONE
+options DEBUG_MEMGUARD
+
+# Don't include the SCSI/CAM strings in the default build
+options SCSI_NO_SENSE_STRINGS
+options SCSI_NO_OP_STRINGS
+
+# .. And no sysctl strings
+options NO_SYSCTL_DESCR
+
+options FFS #Berkeley Fast Filesystem
+options NO_FFS_SNAPSHOT
+# options SOFTUPDATES #Enable FFS soft updates support
+# options UFS_ACL #Support for access control lists
+# options UFS_DIRHASH #Improve performance on big directories
+# options MSDOSFS # Read MSDOS filesystems; useful for USB/CF
+
+device pci
+device ar724x_pci
+
+# 802.11 framework
+options IEEE80211_DEBUG
+options IEEE80211_ALQ
+options IEEE80211_SUPPORT_MESH
+options IEEE80211_SUPPORT_SUPERG
+options IEEE80211_SUPPORT_TDMA
+options IEEE80211_AMPDU_AGE
+#device wlan # 802.11 support
+#device wlan_wep # 802.11 WEP support
+#device wlan_ccmp # 802.11 CCMP support
+#device wlan_tkip # 802.11 TKIP support
+#device wlan_xauth # 802.11 hostap support
+
+# Atheros wireless NICs
+#device ath # Atheros interface support
+#device ath_pci # Atheros PCI/Cardbus bus
+options ATH_DEBUG
+options ATH_DIAGAPI
+options ATH_ENABLE_11N
+options AH_DEBUG
+options AH_DEBUG_ALQ
+options ALQ
+#device ath_hal
+option AH_SUPPORT_AR5416
+#device ath_rate_sample
+option AH_RXCFG_SDMAMW_4BYTES
+option AH_AR5416_INTERRUPT_MITIGATION
+# There's no DFS radar detection support yet so this won't actually
+# detect radars. It however does enable the rest of the channel change
+# machinery so DFS can be debugged.
+option ATH_ENABLE_DFS
+
+device mii
+device arge
+options ARGE_DEBUG # Enable if_arge debugging for now
+
+#device usb
+options USB_EHCI_BIG_ENDIAN_DESC # handle big-endian byte order
+options USB_DEBUG
+options USB_HOST_ALIGN=32 # AR724X (MIPS in general?) requires this
+#device ehci
+
+#device umass
+
+device scbus
+device da
+
+# On-board SPI flash
+device spibus
+device ar71xx_spi
+device mx25l
+device ar71xx_wdog
+
+device uart
+device uart_ar71xx
+
+device loop
+device ether
+device md
+device bpf
+#device random
+#device if_bridge
+#device gif # ip[46] in ip[46] tunneling protocol
+#device gre # generic encapsulation - only for IPv4 in IPv4 though atm
+
+# Enable GPIO
+#device gpio
+#device gpioled
Property changes on: trunk/sys/mips/conf/AR724X_BASE
___________________________________________________________________
Added: mnbsd:nokeywords
## -0,0 +1 ##
+MidnightBSD=%H
\ No newline at end of property
Added: trunk/sys/mips/conf/AR724X_BASE.hints
===================================================================
--- trunk/sys/mips/conf/AR724X_BASE.hints (rev 0)
+++ trunk/sys/mips/conf/AR724X_BASE.hints 2018-05-26 21:55:02 UTC (rev 9987)
@@ -0,0 +1,66 @@
+#
+# $FreeBSD: stable/10/sys/mips/conf/AR724X_BASE.hints 239705 2012-08-26 04:36:59Z adrian $
+#
+hint.apb.0.at="nexus0"
+hint.apb.0.irq=4
+
+# uart0
+hint.uart.0.at="apb0"
+# see atheros/uart_cpu_ar71xx.c why +3
+hint.uart.0.maddr=0x18020003
+hint.uart.0.msize=0x18
+hint.uart.0.irq=3
+
+#ohci
+hint.ohci.0.at="apb0"
+hint.ohci.0.maddr=0x1c000000
+hint.ohci.0.msize=0x01000000
+hint.ohci.0.irq=6
+
+#ehci
+hint.ehci.0.at="nexus0"
+hint.ehci.0.maddr=0x1b000100
+hint.ehci.0.msize=0x01000000
+hint.ehci.0.irq=1
+
+# pci
+hint.pcib.0.at="nexus0"
+hint.pcib.0.irq=0
+
+hint.arge.0.at="nexus0"
+hint.arge.0.maddr=0x19000000
+hint.arge.0.msize=0x1000
+hint.arge.0.irq=2
+
+# phymask, media and fduplex depend upon the specific
+# board.
+# So each board will override the settings as needed.
+
+hint.arge.1.at="nexus0"
+hint.arge.1.maddr=0x1a000000
+hint.arge.1.msize=0x1000
+hint.arge.1.irq=3
+
+# SPI flash
+hint.spi.0.at="nexus0"
+hint.spi.0.maddr=0x1f000000
+hint.spi.0.msize=0x10
+
+hint.mx25l.0.at="spibus0"
+hint.mx25l.0.cs=0
+
+# Watchdog
+hint.ar71xx_wdog.0.at="nexus0"
+
+# GPIO
+hint.gpio.0.at="apb0"
+hint.gpio.0.maddr=0x18040000
+hint.gpio.0.msize=0x1000
+hint.gpio.0.irq=2
+
+# Each board should override the GPIO bus pins with the configuration
+# relevant to it. Thus no pins are defined here.
+
+# hwpmc device
+hint.ar71xx_pmc.0.at="apb0"
+hint.ar71xx_pmc.0.irq=5
Property changes on: trunk/sys/mips/conf/AR724X_BASE.hints
___________________________________________________________________
Added: mnbsd:nokeywords
## -0,0 +1 ##
+MidnightBSD=%H
\ No newline at end of property
Added: trunk/sys/mips/conf/AR91XX_BASE
===================================================================
--- trunk/sys/mips/conf/AR91XX_BASE (rev 0)
+++ trunk/sys/mips/conf/AR91XX_BASE 2018-05-26 21:55:02 UTC (rev 9987)
@@ -0,0 +1,118 @@
+#
+# AR91XX -- Kernel configuration base file for the Atheros AR913x SoC.
+#
+# This file (and the hints file accompanying it) are not designed to be
+# used by themselves. Instead, users of this file should create a kernel
+# config file which includes this file (which gets the basic hints), then
+# override the default options (adding devices as needed) and adding
+# hints as needed (for example, the GPIO and LAN PHY.)
+#
+# $FreeBSD: stable/10/sys/mips/conf/AR91XX_BASE 266331 2014-05-17 17:34:37Z ian $
+#
+
+machine mips mips
+ident AR91XX_BASE
+cpu CPU_MIPS4KC
+makeoptions KERNLOADADDR=0x80050000
+options HZ=1000
+
+files "../atheros/files.ar71xx"
+hints "AR91XX_BASE.hints"
+
+makeoptions DEBUG=-g #Build kernel with gdb(1) debug symbols
+makeoptions MODULES_OVERRIDE="random gpio ar71xx if_gif if_gre if_bridge bridgestp usb wlan wlan_xauth wlan_acl wlan_wep wlan_tkip wlan_ccmp wlan_rssadapt wlan_amrr ath ath_ahb hwpmc"
+
+options DDB
+options KDB
+options ALQ
+
+options SCHED_4BSD #4BSD scheduler
+options INET #InterNETworking
+options INET6 #InterNETworking
+#options NFSCL #Network Filesystem Client
+options PSEUDOFS #Pseudo-filesystem framework
+options _KPOSIX_PRIORITY_SCHEDULING #Posix P1003_1B real-time extensions
+
+# PMC
+options HWPMC_HOOKS
+device hwpmc
+device hwpmc_mips24k
+
+# options NFS_LEGACYRPC
+# Debugging for use in -current
+options INVARIANTS
+options INVARIANT_SUPPORT
+options WITNESS
+options WITNESS_SKIPSPIN
+options FFS #Berkeley Fast Filesystem
+#options SOFTUPDATES #Enable FFS soft updates support
+#options UFS_ACL #Support for access control lists
+#options UFS_DIRHASH #Improve performance on big directories
+options NO_FFS_SNAPSHOT # We don't require snapshot support
+
+# Wireless NIC cards
+options IEEE80211_DEBUG
+options IEEE80211_SUPPORT_MESH
+options IEEE80211_SUPPORT_TDMA
+options IEEE80211_ALQ # 802.11 ALQ logging support
+device wlan # 802.11 support
+device wlan_wep # 802.11 WEP support
+device wlan_ccmp # 802.11 CCMP support
+device wlan_tkip # 802.11 TKIP support
+device wlan_xauth # 802.11 hostap support
+
+# ath(4)
+device ath # Atheros network device
+device ath_rate_sample
+device ath_ahb # Atheros host bus glue
+options ATH_DEBUG
+options ATH_DIAGAPI
+option ATH_ENABLE_11N
+option AH_DEBUG_ALQ
+
+# Don't bother compiling the whole HAL - AH_SUPPORT_AR9130 breaks the
+# rest of the 11n chipset support at the moment and the pre-AR5212
+# HALs aren't required.
+# device ath_hal
+
+# The AR9130 code requires AR5416; and AR5416 requires the AR5212 code.
+device ath_ar5212
+device ath_ar5416
+device ath_ar9130
+
+options AH_DEBUG
+option AH_SUPPORT_AR5416
+option AH_SUPPORT_AR9130 # Makes other chipsets not function!
+option AH_DEBUG_ALQ
+# interrupt mitigation not possible on AR9130
+# option AH_AR5416_INTERRUPT_MITIGATION
+
+device mii
+device arge
+
+device usb
+options USB_EHCI_BIG_ENDIAN_DESC # handle big-endian byte order
+options USB_DEBUG
+options USB_HOST_ALIGN=32 # AR71XX (MIPS in general?) requires this
+device ehci
+
+device scbus
+device umass
+device da
+
+device spibus
+device ar71xx_spi
+device mx25l
+device ar71xx_wdog
+
+device uart
+device uart_ar71xx
+
+device loop
+device ether
+device md
+device bpf
+device random
+device if_bridge
+device gpio
+device gpioled
Property changes on: trunk/sys/mips/conf/AR91XX_BASE
___________________________________________________________________
Added: mnbsd:nokeywords
## -0,0 +1 ##
+MidnightBSD=%H
\ No newline at end of property
Added: trunk/sys/mips/conf/AR91XX_BASE.hints
===================================================================
--- trunk/sys/mips/conf/AR91XX_BASE.hints (rev 0)
+++ trunk/sys/mips/conf/AR91XX_BASE.hints 2018-05-26 21:55:02 UTC (rev 9987)
@@ -0,0 +1,59 @@
+# This file (and the kernel config file accompanying it) are not designed
+# to be used by themselves. Instead, users of this file should create a
+# kernel # config file which includes this file (which gets the basic hints),
+# then override the default options (adding devices as needed) and adding
+# hints as needed (for example, the GPIO and LAN PHY.)
+
+# $FreeBSD: stable/10/sys/mips/conf/AR91XX_BASE.hints 228519 2011-12-15 01:05:38Z adrian $
+
+hint.apb.0.at="nexus0"
+hint.apb.0.irq=4
+
+# uart0
+hint.uart.0.at="apb0"
+# see atheros/uart_cpu_ar71xx.c why +3
+hint.uart.0.maddr=0x18020003
+hint.uart.0.msize=0x18
+hint.uart.0.irq=3
+
+#ehci - note the 0x100 offset for the AR913x/AR724x
+hint.ehci.0.at="nexus0"
+hint.ehci.0.maddr=0x1b000100
+hint.ehci.0.msize=0x00ffff00
+hint.ehci.0.irq=1
+
+hint.arge.0.at="nexus0"
+hint.arge.0.maddr=0x19000000
+hint.arge.0.msize=0x1000
+hint.arge.0.irq=2
+
+hint.arge.1.at="nexus0"
+hint.arge.1.maddr=0x1a000000
+hint.arge.1.msize=0x1000
+hint.arge.1.irq=3
+
+# XXX The ath device hangs off of the AHB, rather than the Nexus.
+hint.ath.0.at="nexus0"
+hint.ath.0.maddr=0x180c0000
+hint.ath.0.msize=0x30000
+hint.ath.0.irq=0
+# Set this to define where the ath calibration data
+# should be fetched from in physical memory.
+# hint.ath.0.eepromaddr=0x1fff1000
+
+# SPI flash
+hint.spi.0.at="nexus0"
+hint.spi.0.maddr=0x1f000000
+hint.spi.0.msize=0x10
+
+hint.mx25l.0.at="spibus0"
+hint.mx25l.0.cs=0
+
+# Watchdog
+hint.ar71xx_wdog.0.at="nexus0"
+
+# The GPIO function and pin mask is configured per-board
+hint.gpio.0.at="apb0"
+hint.gpio.0.maddr=0x18040000
+hint.gpio.0.msize=0x1000
+hint.gpio.0.irq=2
Property changes on: trunk/sys/mips/conf/AR91XX_BASE.hints
___________________________________________________________________
Added: mnbsd:nokeywords
## -0,0 +1 ##
+MidnightBSD=%H
\ No newline at end of property
Added: trunk/sys/mips/conf/AR933X_BASE
===================================================================
--- trunk/sys/mips/conf/AR933X_BASE (rev 0)
+++ trunk/sys/mips/conf/AR933X_BASE 2018-05-26 21:55:02 UTC (rev 9987)
@@ -0,0 +1,124 @@
+#
+# AR91XX -- Kernel configuration base file for the Atheros AR913x SoC.
+#
+# This file (and the hints file accompanying it) are not designed to be
+# used by themselves. Instead, users of this file should create a kernel
+# config file which includes this file (which gets the basic hints), then
+# override the default options (adding devices as needed) and adding
+# hints as needed (for example, the GPIO and LAN PHY.)
+#
+# $FreeBSD: stable/10/sys/mips/conf/AR933X_BASE 266331 2014-05-17 17:34:37Z ian $
+#
+
+machine mips mips
+ident AR933X_BASE
+cpu CPU_MIPS4KC
+makeoptions KERNLOADADDR=0x80050000
+options HZ=1000
+
+files "../atheros/files.ar71xx"
+hints "AR933X_BASE.hints"
+
+makeoptions DEBUG=-g #Build kernel with gdb(1) debug symbols
+# makeoptions MODULES_OVERRIDE="random gpio ar71xx if_gif if_gre if_bridge bridgestp usb wlan wlan_xauth wlan_acl wlan_wep wlan_tkip wlan_ccmp wlan_rssadapt wlan_amrr ath ath_ahb hwpmc"
+makeoptions MODULES_OVERRIDE=""
+
+options DDB
+options KDB
+options ALQ
+
+options SCHED_4BSD #4BSD scheduler
+options INET #InterNETworking
+#options INET6 #InterNETworking
+#options NFSCL #Network Filesystem Client
+options PSEUDOFS #Pseudo-filesystem framework
+options _KPOSIX_PRIORITY_SCHEDULING #Posix P1003_1B real-time extensions
+
+# Don't include the SCSI/CAM strings in the default build
+options SCSI_NO_SENSE_STRINGS
+options SCSI_NO_OP_STRINGS
+
+# .. And no sysctl strings
+options NO_SYSCTL_DESCR
+
+# Limit IO size
+options NBUF=128
+
+# Limit UMTX hash size
+# options UMTX_NUM_CHAINS=64
+
+# PMC
+#options HWPMC_HOOKS
+#device hwpmc
+#device hwpmc_mips24k
+
+# options NFS_LEGACYRPC
+# Debugging for use in -current
+#options INVARIANTS
+#options INVARIANT_SUPPORT
+#options WITNESS
+#options WITNESS_SKIPSPIN
+options FFS #Berkeley Fast Filesystem
+#options SOFTUPDATES #Enable FFS soft updates support
+#options UFS_ACL #Support for access control lists
+#options UFS_DIRHASH #Improve performance on big directories
+options NO_FFS_SNAPSHOT # We don't require snapshot support
+
+# Wireless NIC cards
+options IEEE80211_DEBUG
+options IEEE80211_SUPPORT_MESH
+options IEEE80211_SUPPORT_TDMA
+options IEEE80211_SUPPORT_SUPERG
+options IEEE80211_ALQ # 802.11 ALQ logging support
+device wlan # 802.11 support
+device wlan_wep # 802.11 WEP support
+device wlan_ccmp # 802.11 CCMP support
+device wlan_tkip # 802.11 TKIP support
+device wlan_xauth # 802.11 hostap support
+
+# ath(4)
+device ath # Atheros network device
+device ath_rate_sample
+device ath_ahb # Atheros host bus glue
+options ATH_DEBUG
+options ATH_DIAGAPI
+option ATH_ENABLE_11N
+option AH_DEBUG_ALQ
+
+#device ath_hal
+device ath_ar9300 # AR9330 HAL; no need for the others
+option AH_DEBUG
+option AH_SUPPORT_AR5416 # 11n HAL support
+option AH_SUPPORT_AR9330 # Chipset support
+option AH_DEBUG_ALQ
+option AH_AR5416_INTERRUPT_MITIGATION
+
+device mii
+device arge
+
+device usb
+options USB_EHCI_BIG_ENDIAN_DESC # handle big-endian byte order
+options USB_DEBUG
+options USB_HOST_ALIGN=32 # AR71XX (MIPS in general?) requires this
+device ehci
+
+device scbus
+device umass
+device da
+
+device spibus
+device ar71xx_spi
+device mx25l
+device ar71xx_wdog
+
+device uart
+device uart_ar933x
+
+device loop
+device ether
+device md
+device bpf
+device random
+device if_bridge
+device gpio
+device gpioled
Property changes on: trunk/sys/mips/conf/AR933X_BASE
___________________________________________________________________
Added: mnbsd:nokeywords
## -0,0 +1 ##
+MidnightBSD=%H
\ No newline at end of property
Added: trunk/sys/mips/conf/AR933X_BASE.hints
===================================================================
--- trunk/sys/mips/conf/AR933X_BASE.hints (rev 0)
+++ trunk/sys/mips/conf/AR933X_BASE.hints 2018-05-26 21:55:02 UTC (rev 9987)
@@ -0,0 +1,61 @@
+# This file (and the kernel config file accompanying it) are not designed
+# to be used by themselves. Instead, users of this file should create a
+# kernel # config file which includes this file (which gets the basic hints),
+# then override the default options (adding devices as needed) and adding
+# hints as needed (for example, the GPIO and LAN PHY.)
+
+# $FreeBSD: stable/10/sys/mips/conf/AR933X_BASE.hints 252242 2013-06-26 05:02:47Z adrian $
+
+hint.apb.0.at="nexus0"
+hint.apb.0.irq=4
+
+# uart0
+hint.uart.0.at="apb0"
+# NB: This isn't an ns8250 UART
+hint.uart.0.maddr=0x18020000
+hint.uart.0.msize=0x18
+hint.uart.0.irq=3
+
+#ehci - note the 0x100 offset for the AR913x/AR724x
+hint.ehci.0.at="nexus0"
+hint.ehci.0.maddr=0x1b000100
+hint.ehci.0.msize=0x00ffff00
+hint.ehci.0.irq=1
+
+hint.arge.0.at="nexus0"
+hint.arge.0.maddr=0x19000000
+hint.arge.0.msize=0x1000
+hint.arge.0.irq=2
+
+hint.arge.1.at="nexus0"
+hint.arge.1.maddr=0x1a000000
+hint.arge.1.msize=0x1000
+hint.arge.1.irq=3
+
+# XXX The ath device hangs off of the AHB, rather than the Nexus.
+hint.ath.0.at="nexus0"
+hint.ath.0.maddr=0x18100000
+hint.ath.0.msize=0x20000
+hint.ath.0.irq=0
+hint.ath.0.vendor_id=0x168c
+hint.ath.0.device_id=0x0035
+# Set this to define where the ath calibration data
+# should be fetched from in physical memory.
+# hint.ath.0.eepromaddr=0x1fff1000
+
+# SPI flash
+hint.spi.0.at="nexus0"
+hint.spi.0.maddr=0x1f000000
+hint.spi.0.msize=0x10
+
+hint.mx25l.0.at="spibus0"
+hint.mx25l.0.cs=0
+
+# Watchdog
+hint.ar71xx_wdog.0.at="nexus0"
+
+# The GPIO function and pin mask is configured per-board
+hint.gpio.0.at="apb0"
+hint.gpio.0.maddr=0x18040000
+hint.gpio.0.msize=0x1000
+hint.gpio.0.irq=2
Property changes on: trunk/sys/mips/conf/AR933X_BASE.hints
___________________________________________________________________
Added: mnbsd:nokeywords
## -0,0 +1 ##
+MidnightBSD=%H
\ No newline at end of property
Added: trunk/sys/mips/conf/AR934X_BASE
===================================================================
--- trunk/sys/mips/conf/AR934X_BASE (rev 0)
+++ trunk/sys/mips/conf/AR934X_BASE 2018-05-26 21:55:02 UTC (rev 9987)
@@ -0,0 +1,124 @@
+#
+# AR91XX -- Kernel configuration base file for the Atheros AR913x SoC.
+#
+# This file (and the hints file accompanying it) are not designed to be
+# used by themselves. Instead, users of this file should create a kernel
+# config file which includes this file (which gets the basic hints), then
+# override the default options (adding devices as needed) and adding
+# hints as needed (for example, the GPIO and LAN PHY.)
+#
+# $FreeBSD: stable/10/sys/mips/conf/AR934X_BASE 266331 2014-05-17 17:34:37Z ian $
+#
+
+machine mips mips
+ident AR934X_BASE
+cpu CPU_MIPS74KC
+makeoptions KERNLOADADDR=0x80050000
+options HZ=1000
+
+files "../atheros/files.ar71xx"
+hints "AR934X_BASE.hints"
+
+makeoptions DEBUG=-g #Build kernel with gdb(1) debug symbols
+# makeoptions MODULES_OVERRIDE="random gpio ar71xx if_gif if_gre if_bridge bridgestp usb wlan wlan_xauth wlan_acl wlan_wep wlan_tkip wlan_ccmp wlan_rssadapt wlan_amrr ath ath_ahb hwpmc"
+makeoptions MODULES_OVERRIDE=""
+
+options DDB
+options KDB
+options ALQ
+
+options SCHED_4BSD #4BSD scheduler
+options INET #InterNETworking
+#options INET6 #InterNETworking
+#options NFSCL #Network Filesystem Client
+options PSEUDOFS #Pseudo-filesystem framework
+options _KPOSIX_PRIORITY_SCHEDULING #Posix P1003_1B real-time extensions
+
+# Don't include the SCSI/CAM strings in the default build
+options SCSI_NO_SENSE_STRINGS
+options SCSI_NO_OP_STRINGS
+
+# .. And no sysctl strings
+options NO_SYSCTL_DESCR
+
+# Limit IO size
+options NBUF=128
+
+# Limit UMTX hash size
+# options UMTX_NUM_CHAINS=64
+
+# PMC
+#options HWPMC_HOOKS
+#device hwpmc
+#device hwpmc_mips24k
+
+# options NFS_LEGACYRPC
+# Debugging for use in -current
+#options INVARIANTS
+#options INVARIANT_SUPPORT
+#options WITNESS
+#options WITNESS_SKIPSPIN
+options FFS #Berkeley Fast Filesystem
+#options SOFTUPDATES #Enable FFS soft updates support
+#options UFS_ACL #Support for access control lists
+#options UFS_DIRHASH #Improve performance on big directories
+options NO_FFS_SNAPSHOT # We don't require snapshot support
+
+# Wireless NIC cards
+options IEEE80211_DEBUG
+options IEEE80211_SUPPORT_MESH
+options IEEE80211_SUPPORT_TDMA
+options IEEE80211_SUPPORT_SUPERG
+options IEEE80211_ALQ # 802.11 ALQ logging support
+device wlan # 802.11 support
+device wlan_wep # 802.11 WEP support
+device wlan_ccmp # 802.11 CCMP support
+device wlan_tkip # 802.11 TKIP support
+device wlan_xauth # 802.11 hostap support
+
+# ath(4)
+device ath # Atheros network device
+device ath_rate_sample
+device ath_ahb # Atheros host bus glue
+options ATH_DEBUG
+options ATH_DIAGAPI
+option ATH_ENABLE_11N
+option AH_DEBUG_ALQ
+
+#device ath_hal
+device ath_ar9300 # AR9330 HAL; no need for the others
+option AH_DEBUG
+option AH_SUPPORT_AR5416 # 11n HAL support
+option AH_SUPPORT_AR9340 # Chipset support
+option AH_DEBUG_ALQ
+option AH_AR5416_INTERRUPT_MITIGATION
+
+device mii
+device arge
+
+device usb
+options USB_EHCI_BIG_ENDIAN_DESC # handle big-endian byte order
+options USB_DEBUG
+options USB_HOST_ALIGN=32 # AR71XX (MIPS in general?) requires this
+device ehci
+
+device scbus
+device umass
+device da
+
+device spibus
+device ar71xx_spi
+device mx25l
+device ar71xx_wdog
+
+device uart
+device uart_ar71xx
+
+device loop
+device ether
+device md
+device bpf
+device random
+device if_bridge
+device gpio
+device gpioled
Property changes on: trunk/sys/mips/conf/AR934X_BASE
___________________________________________________________________
Added: mnbsd:nokeywords
## -0,0 +1 ##
+MidnightBSD=%H
\ No newline at end of property
Added: trunk/sys/mips/conf/AR934X_BASE.hints
===================================================================
--- trunk/sys/mips/conf/AR934X_BASE.hints (rev 0)
+++ trunk/sys/mips/conf/AR934X_BASE.hints 2018-05-26 21:55:02 UTC (rev 9987)
@@ -0,0 +1,61 @@
+# This file (and the kernel config file accompanying it) are not designed
+# to be used by themselves. Instead, users of this file should create a
+# kernel # config file which includes this file (which gets the basic hints),
+# then override the default options (adding devices as needed) and adding
+# hints as needed (for example, the GPIO and LAN PHY.)
+
+# $FreeBSD: stable/10/sys/mips/conf/AR934X_BASE.hints 253512 2013-07-21 04:00:48Z adrian $
+
+hint.apb.0.at="nexus0"
+hint.apb.0.irq=4
+
+# uart0
+hint.uart.0.at="apb0"
+# NB: This isn't an ns8250 UART
+hint.uart.0.maddr=0x18020003
+hint.uart.0.msize=0x18
+hint.uart.0.irq=3
+
+#ehci - note the 0x100 offset for the AR913x/AR724x
+hint.ehci.0.at="nexus0"
+hint.ehci.0.maddr=0x1b000100
+hint.ehci.0.msize=0x00001000
+hint.ehci.0.irq=1
+
+hint.arge.0.at="nexus0"
+hint.arge.0.maddr=0x19000000
+hint.arge.0.msize=0x1000
+hint.arge.0.irq=2
+
+hint.arge.1.at="nexus0"
+hint.arge.1.maddr=0x1a000000
+hint.arge.1.msize=0x1000
+hint.arge.1.irq=3
+
+# XXX The ath device hangs off of the AHB, rather than the Nexus.
+hint.ath.0.at="nexus0"
+hint.ath.0.maddr=0x18100000
+hint.ath.0.msize=0x20000
+hint.ath.0.irq=0
+hint.ath.0.vendor_id=0x168c
+hint.ath.0.device_id=0x0031
+# Set this to define where the ath calibration data
+# should be fetched from in physical memory.
+# hint.ath.0.eepromaddr=0x1fff1000
+
+# SPI flash
+hint.spi.0.at="nexus0"
+hint.spi.0.maddr=0x1f000000
+hint.spi.0.msize=0x10
+
+hint.mx25l.0.at="spibus0"
+hint.mx25l.0.cs=0
+
+# Watchdog
+hint.ar71xx_wdog.0.at="nexus0"
+
+# The GPIO function and pin mask is configured per-board
+hint.gpio.0.at="apb0"
+hint.gpio.0.maddr=0x18040000
+hint.gpio.0.msize=0x1000
+hint.gpio.0.irq=2
Property changes on: trunk/sys/mips/conf/AR934X_BASE.hints
___________________________________________________________________
Added: mnbsd:nokeywords
## -0,0 +1 ##
+MidnightBSD=%H
\ No newline at end of property
Added: trunk/sys/mips/conf/BERI_DE4.hints
===================================================================
--- trunk/sys/mips/conf/BERI_DE4.hints (rev 0)
+++ trunk/sys/mips/conf/BERI_DE4.hints 2018-05-26 21:55:02 UTC (rev 9987)
@@ -0,0 +1,26 @@
+# $FreeBSD: stable/10/sys/mips/conf/BERI_DE4.hints 257527 2013-11-01 21:15:39Z brooks $
+
+# Hardwired location of bitfile
+hint.map.0.at="cfid0s.fpga0"
+hint.map.0.start=0x00000000
+hint.map.0.end=0x00c00000
+hint.map.0.name="fpga"
+
+# Kernel on the second chip
+hint.map.1.at="cfid0s.os"
+hint.map.1.start=0x007e0000
+hint.map.1.end=0x01fe0000
+hint.map.1.name="kernel"
+
+# Altera Triple-Speed Ethernet Mac, present in tPad and DE-4 configurations
+# configured from fdt(4) but PHYs are still described in here.
+# Currently configured for individual tse_mac cores.
+hint.e1000phy.0.at="miibus0"
+hint.e1000phy.0.phyno=0
+hint.e1000phy.1.at="miibus0"
+hint.e1000phy.1.phyno=0
+hint.e1000phy.2.at="miibus0"
+hint.e1000phy.2.phyno=0
+hint.e1000phy.3.at="miibus0"
+hint.e1000phy.3.phyno=0
+
Property changes on: trunk/sys/mips/conf/BERI_DE4.hints
___________________________________________________________________
Added: mnbsd:nokeywords
## -0,0 +1 ##
+MidnightBSD=%H
\ No newline at end of property
Added: trunk/sys/mips/conf/BERI_DE4_BASE
===================================================================
--- trunk/sys/mips/conf/BERI_DE4_BASE (rev 0)
+++ trunk/sys/mips/conf/BERI_DE4_BASE 2018-05-26 21:55:02 UTC (rev 9987)
@@ -0,0 +1,42 @@
+#
+# BERI_DE4_BASE -- Kernel for the SRI/Cambridge "BERI" (Bluespec Extensible RISC
+# Implementation) FPGA soft core, as configured in its Terasic DE-4 reference
+# configuration. This kernel configration must be further specialized to
+# to include a root filesystem specification.
+#
+# $FreeBSD: stable/10/sys/mips/conf/BERI_DE4_BASE 257527 2013-11-01 21:15:39Z brooks $
+#
+
+include "BERI_TEMPLATE"
+
+ident BERI_DE4_BASE
+
+options NFSCL # New Network Filesystem Client
+options NFSLOCKD # Network Lock Manager
+options NFS_ROOT # NFS usable as /, requires NFSCL
+
+options FDT
+options FDT_DTB_STATIC
+makeoptions FDT_DTS_FILE=beripad-de4.dts
+
+hints "BERI_DE4.hints" # Flash partitions still use hints.
+
+device altera_atse
+device altera_avgen
+device altera_jtag_uart
+device altera_sdcard
+device terasic_de4led
+device terasic_mtl
+
+device bpf
+device cfi
+device cfid
+options CFI_SUPPORT_STRATAFLASH
+options ATSE_CFI_HACK
+device sc
+
+device uart
+
+device miibus
+options DEVICE_POLLING
+
Property changes on: trunk/sys/mips/conf/BERI_DE4_BASE
___________________________________________________________________
Added: mnbsd:nokeywords
## -0,0 +1 ##
+MidnightBSD=%H
\ No newline at end of property
Added: trunk/sys/mips/conf/BERI_DE4_MDROOT
===================================================================
--- trunk/sys/mips/conf/BERI_DE4_MDROOT (rev 0)
+++ trunk/sys/mips/conf/BERI_DE4_MDROOT 2018-05-26 21:55:02 UTC (rev 9987)
@@ -0,0 +1,19 @@
+#
+# BERI_DE4_MDROOT -- Kernel for the SRI/Cambridge "BERI" (Bluespec Extensible
+# RISC # Implementation) FPGA soft core, as configured in its Terasic DE-4
+# reference configuration.
+#
+# $FreeBSD: stable/10/sys/mips/conf/BERI_DE4_MDROOT 257527 2013-11-01 21:15:39Z brooks $
+#
+
+include "BERI_DE4_BASE"
+
+ident BERI_DE4_MDROOT
+
+#
+# This kernel configuration uses an embedded 8MB memory root file system.
+# Adjust the following path based on local requirements.
+#
+options MD_ROOT # MD is a potential root device
+options MD_ROOT_SIZE=26112 # 25.5MB
+options ROOTDEVNAME=\"ufs:md0\"
Property changes on: trunk/sys/mips/conf/BERI_DE4_MDROOT
___________________________________________________________________
Added: mnbsd:nokeywords
## -0,0 +1 ##
+MidnightBSD=%H
\ No newline at end of property
Added: trunk/sys/mips/conf/BERI_DE4_SDROOT
===================================================================
--- trunk/sys/mips/conf/BERI_DE4_SDROOT (rev 0)
+++ trunk/sys/mips/conf/BERI_DE4_SDROOT 2018-05-26 21:55:02 UTC (rev 9987)
@@ -0,0 +1,16 @@
+#
+# BERI_DE4_SDROOT -- Kernel for the SRI/Cambridge "BERI" (Bluespec Extensible
+# RISC Implementation) FPGA soft core, as configured in its Terasic DE-4
+# reference configuration.
+#
+# $FreeBSD: stable/10/sys/mips/conf/BERI_DE4_SDROOT 257527 2013-11-01 21:15:39Z brooks $
+#
+
+include "BERI_DE4_BASE"
+
+ident BERI_DE4_SDROOT
+
+#
+# This kernel expects to find its root filesystem on the SD Card.
+#
+options ROOTDEVNAME=\"ufs:/dev/altera_sdcard0\"
Property changes on: trunk/sys/mips/conf/BERI_DE4_SDROOT
___________________________________________________________________
Added: mnbsd:nokeywords
## -0,0 +1 ##
+MidnightBSD=%H
\ No newline at end of property
Added: trunk/sys/mips/conf/BERI_NETFPGA_MDROOT
===================================================================
--- trunk/sys/mips/conf/BERI_NETFPGA_MDROOT (rev 0)
+++ trunk/sys/mips/conf/BERI_NETFPGA_MDROOT 2018-05-26 21:55:02 UTC (rev 9987)
@@ -0,0 +1,36 @@
+#
+# BERI_NETFPGA_MDROOT -- Kernel for the SRI/Cambridge "BERI" (Bluespec Extensible
+# RISC Implementation) FPGA soft core, as configured in its NetFPGA reference
+# configuration.
+#
+# $FreeBSD: stable/10/sys/mips/conf/BERI_NETFPGA_MDROOT 270061 2014-08-16 14:30:46Z bz $
+#
+
+include "BERI_TEMPLATE"
+
+ident BERI_NETFPGA_MDROOT
+
+options HZ=100
+
+options FDT
+options FDT_DTB_STATIC
+makeoptions FDT_DTS_FILE=beri-netfpga.dts
+
+#device uart
+device altera_jtag_uart
+
+device bpf
+
+options DEVICE_POLLING
+device netfpga10g_nf10bmac
+
+#
+# This kernel configuration uses an embedded memory root file system.
+# Adjust the following path and size based on local requirements.
+#
+options MD_ROOT # MD is a potential root device
+options MD_ROOT_SIZE=26112 # 25.5MB
+options ROOTDEVNAME=\"ufs:md0\"
+#makeoptions MFS_IMAGE=/foo/baz/baz/mdroot.img
+
+# end
Property changes on: trunk/sys/mips/conf/BERI_NETFPGA_MDROOT
___________________________________________________________________
Added: mnbsd:nokeywords
## -0,0 +1 ##
+MidnightBSD=%H
\ No newline at end of property
Added: trunk/sys/mips/conf/BERI_SIM_BASE
===================================================================
--- trunk/sys/mips/conf/BERI_SIM_BASE (rev 0)
+++ trunk/sys/mips/conf/BERI_SIM_BASE 2018-05-26 21:55:02 UTC (rev 9987)
@@ -0,0 +1,19 @@
+#
+# BERI_SIM_BASE -- Base kernel for the SRI/Cambridge "BERI" (Bluespec
+# Extensible RISC Implementation) FPGA soft core, as configured for
+# simulation.
+#
+# $FreeBSD: stable/10/sys/mips/conf/BERI_SIM_BASE 257527 2013-11-01 21:15:39Z brooks $
+#
+
+include "BERI_TEMPLATE"
+
+options FDT
+options FDT_DTB_STATIC
+makeoptions FDT_DTS_FILE=beri-sim.dts
+
+options ALTERA_SDCARD_FAST_SIM
+
+device altera_avgen
+device altera_jtag_uart
+device altera_sdcard
Property changes on: trunk/sys/mips/conf/BERI_SIM_BASE
___________________________________________________________________
Added: mnbsd:nokeywords
## -0,0 +1 ##
+MidnightBSD=%H
\ No newline at end of property
Added: trunk/sys/mips/conf/BERI_SIM_MDROOT
===================================================================
--- trunk/sys/mips/conf/BERI_SIM_MDROOT (rev 0)
+++ trunk/sys/mips/conf/BERI_SIM_MDROOT 2018-05-26 21:55:02 UTC (rev 9987)
@@ -0,0 +1,18 @@
+#
+# BERI_SIM_MDROOT -- Kernel for the SRI/Cambridge "BERI" (Bluespec Extensible
+# RISC Implementation) FPGA soft core, as configured for simulation.
+#
+# $FreeBSD: stable/10/sys/mips/conf/BERI_SIM_MDROOT 257527 2013-11-01 21:15:39Z brooks $
+#
+
+include "BERI_SIM_BASE"
+
+ident BERI_SIM_MDROOT
+
+#
+# This kernel configuration uses an embedded memory root file system.
+# Adjust the following path based on local requirements.
+#
+options MD_ROOT # MD is a potential root device
+options MD_ROOT_SIZE=26112 # 25.5MB
+options ROOTDEVNAME=\"ufs:md0\"
Property changes on: trunk/sys/mips/conf/BERI_SIM_MDROOT
___________________________________________________________________
Added: mnbsd:nokeywords
## -0,0 +1 ##
+MidnightBSD=%H
\ No newline at end of property
Added: trunk/sys/mips/conf/BERI_SIM_SDROOT
===================================================================
--- trunk/sys/mips/conf/BERI_SIM_SDROOT (rev 0)
+++ trunk/sys/mips/conf/BERI_SIM_SDROOT 2018-05-26 21:55:02 UTC (rev 9987)
@@ -0,0 +1,15 @@
+#
+# BERI_SIM_SDROOT -- Kernel for the SRI/Cambridge "BERI" (Bluespec Extensible
+# RISC Implementation) FPGA soft core, as configured for simulation.
+#
+# $FreeBSD: stable/10/sys/mips/conf/BERI_SIM_SDROOT 257527 2013-11-01 21:15:39Z brooks $
+#
+
+include "BERI_SIM_BASE"
+
+ident BERI_SIM_SDROOT
+
+#
+# This kernel expects to find its root filesystem on the SD Card.
+#
+options ROOTDEVNAME=\"ufs:/dev/altera_sdcard0\"
Property changes on: trunk/sys/mips/conf/BERI_SIM_SDROOT
___________________________________________________________________
Added: mnbsd:nokeywords
## -0,0 +1 ##
+MidnightBSD=%H
\ No newline at end of property
Added: trunk/sys/mips/conf/BERI_TEMPLATE
===================================================================
--- trunk/sys/mips/conf/BERI_TEMPLATE (rev 0)
+++ trunk/sys/mips/conf/BERI_TEMPLATE 2018-05-26 21:55:02 UTC (rev 9987)
@@ -0,0 +1,61 @@
+#
+# BERI_TEMPLATE -- a template kernel configuration for the SRI/Cambridge
+# "BERI" (Bluespec Extensible RISC Implementation) FPGA soft core CPU. This
+# kernel configuration file will be included by other board-specific files,
+# and so contains only BERI features common across all board targets.
+#
+# $FreeBSD: stable/10/sys/mips/conf/BERI_TEMPLATE 257527 2013-11-01 21:15:39Z brooks $
+#
+
+ident BERI_TEMPLATE
+
+machine mips mips64
+
+cpu CPU_BERI
+
+options HZ=200
+
+makeoptions ARCH_FLAGS="-march=mips64 -mabi=64"
+
+makeoptions KERNLOADADDR=0xffffffff80100000
+
+include "../beri/std.beri"
+
+makeoptions DEBUG=-g #Build kernel with gdb(1) debug symbols
+
+makeoptions MODULES_OVERRIDE=""
+
+options DDB
+options KDB
+options ALT_BREAK_TO_DEBUGGER
+options KTRACE
+
+options CAPABILITY_MODE
+options CAPABILITIES
+
+options SCHED_ULE
+
+options FFS #Berkeley Fast Filesystem
+
+options INET
+options INET6
+options KGSSAPI
+options NFSCL
+options NFSLOCKD
+options NFS_ROOT
+
+# Debugging for use in -current
+#options DEADLKRES #Enable the deadlock resolver
+options INVARIANTS #Enable calls of extra sanity checking
+options INVARIANT_SUPPORT #Extra sanity checks of internal structures, required by INVARIANTS
+#options WITNESS #Enable checks to detect deadlocks and cycles
+#options WITNESS_SKIPSPIN #Don't run witness on spinlocks for speed
+
+device crypto
+device cryptodev
+device ether
+device geom_map
+device loop
+device md
+device random
+device snp
Property changes on: trunk/sys/mips/conf/BERI_TEMPLATE
___________________________________________________________________
Added: mnbsd:nokeywords
## -0,0 +1 ##
+MidnightBSD=%H
\ No newline at end of property
Added: trunk/sys/mips/conf/BERI_TPAD.hints
===================================================================
--- trunk/sys/mips/conf/BERI_TPAD.hints (rev 0)
+++ trunk/sys/mips/conf/BERI_TPAD.hints 2018-05-26 21:55:02 UTC (rev 9987)
@@ -0,0 +1,51 @@
+# $FreeBSD: stable/10/sys/mips/conf/BERI_TPAD.hints 239679 2012-08-25 12:02:13Z rwatson $
+
+#
+# Altera JTAG UARTs configured for console, debugging, and data putput on the
+# Terasic tPad.
+#
+hint.altera_jtag_uart.0.at="nexus0"
+hint.altera_jtag_uart.0.maddr=0x7f000000
+hint.altera_jtag_uart.0.msize=0x40
+hint.altera_jtag_uart.0.irq=0
+
+hint.altera_jtag_uart.1.at="nexus0"
+hint.altera_jtag_uart.1.maddr=0x7f001000
+hint.altera_jtag_uart.1.msize=0x40
+
+hint.altera_jtag_uart.2.at="nexus0"
+hint.altera_jtag_uart.2.maddr=0x7f002000
+hint.altera_jtag_uart.2.msize=0x40
+
+#
+# Expose the tPad touchscreen device via an Avalon "generic" device. Observe
+# that this is a portion of DRAM, so some care may be required in how memory
+# is exposed to FreeBSD to avoid use of that DRAM for both the touch screen
+# and FreeBSD use.
+#
+# Two separate devices are used here because alignment/width requirements for
+# I/O differ: the frame buffer accepts 16-bit I/O, and the touch input device
+# requires 32-bit I/O.
+#
+hint.altera_avgen.0.at="nexus0"
+hint.altera_avgen.0.maddr=0x04000000
+hint.altera_avgen.0.msize=0x01000000
+hint.altera_avgen.0.width=2
+hint.altera_avgen.0.fileio="rw"
+hint.altera_avgen.0.mmapio="rw"
+hint.altera_avgen.0.devname="display"
+
+hint.altera_avgen.1.at="nexus0"
+hint.altera_avgen.1.maddr=0x05000000
+hint.altera_avgen.1.msize=0x00000020
+hint.altera_avgen.1.width=4
+hint.altera_avgen.1.fileio="rw"
+hint.altera_avgen.1.mmapio="rw"
+hint.altera_avgen.1.devname="touch"
+
+#
+# On-board DE4 and tPad SD Card IP core
+#
+hint.altera_sdcardc.0.at="nexus0"
+hint.altera_sdcardc.0.maddr=0x7f008000
+hint.altera_sdcardc.0.msize=0x400
Property changes on: trunk/sys/mips/conf/BERI_TPAD.hints
___________________________________________________________________
Added: mnbsd:nokeywords
## -0,0 +1 ##
+MidnightBSD=%H
\ No newline at end of property
Added: trunk/sys/mips/conf/CARAMBOLA2
===================================================================
--- trunk/sys/mips/conf/CARAMBOLA2 (rev 0)
+++ trunk/sys/mips/conf/CARAMBOLA2 2018-05-26 21:55:02 UTC (rev 9987)
@@ -0,0 +1,53 @@
+#
+# Carambola 2 - an AR933x based SoC wifi device.
+#
+# http://shop.8devices.com/wifi4things/carambola2
+#
+# * AR9330 SoC
+# * 64MB RAM
+# * 16MB flash
+# * Integrated 1x1 2GHz wifi and 10/100 bridge
+#
+# $FreeBSD: stable/10/sys/mips/conf/CARAMBOLA2 266331 2014-05-17 17:34:37Z ian $
+#
+
+# Include the default AR933x parameters
+include "AR933X_BASE"
+
+ident CARAMBOLA2
+
+# Override hints with board values
+hints "CARAMBOLA2.hints"
+
+# Board memory - 64MB
+options AR71XX_REALMEM=(64*1024*1024)
+
+# i2c GPIO bus
+#device gpioiic
+#device iicbb
+#device iicbus
+#device iic
+
+# Options required for miiproxy and mdiobus
+options ARGE_MDIO # Export an MDIO bus separate from arge
+device miiproxy # MDIO bus <-> MII PHY rendezvous
+
+device etherswitch
+device arswitch
+
+# read MSDOS formatted disks - USB
+#options MSDOSFS
+
+# Enable the uboot environment stuff rather then the
+# redboot stuff.
+options AR71XX_ENV_UBOOT
+
+# uzip - to boot natively from flash
+device geom_uncompress
+options GEOM_UNCOMPRESS
+
+# Used for the static uboot partition map
+device geom_map
+
+# Boot off of the rootfs, as defined in the geom_map setup.
+options ROOTDEVNAME=\"ufs:map/rootfs.uncompress\"
Property changes on: trunk/sys/mips/conf/CARAMBOLA2
___________________________________________________________________
Added: mnbsd:nokeywords
## -0,0 +1 ##
+MidnightBSD=%H
\ No newline at end of property
Added: trunk/sys/mips/conf/CARAMBOLA2.hints
===================================================================
--- trunk/sys/mips/conf/CARAMBOLA2.hints (rev 0)
+++ trunk/sys/mips/conf/CARAMBOLA2.hints 2018-05-26 21:55:02 UTC (rev 9987)
@@ -0,0 +1,114 @@
+#
+# This file adds to the values in AR91XX_BASE.hints.
+#
+# $FreeBSD: stable/10/sys/mips/conf/CARAMBOLA2.hints 252243 2013-06-26 05:03:47Z adrian $
+
+# mdiobus on arge1
+hint.argemdio.0.at="nexus0"
+hint.argemdio.0.maddr=0x1a000000
+hint.argemdio.0.msize=0x1000
+hint.argemdio.0.order=0
+
+# Embedded Atheros Switch
+hint.arswitch.0.at="mdio0"
+
+# XXX this should really say it's an AR933x switch, as there
+# are some vlan specific differences here!
+hint.arswitch.0.is_7240=1
+hint.arswitch.0.numphys=4
+hint.arswitch.0.phy4cpu=1 # phy 4 is a "CPU" separate PHY
+hint.arswitch.0.is_rgmii=0
+hint.arswitch.0.is_gmii=1 # arge1 <-> switch PHY is GMII
+
+# arge0 - MII, autoneg, phy(4)
+hint.arge.0.phymask=0x10 # PHY4
+hint.arge.0.mdio=mdioproxy1 # .. off of the switch mdiobus
+
+# arge1 - GMII, 1000/full
+hint.arge.1.phymask=0x0 # No directly mapped PHYs
+hint.arge.1.media=1000
+hint.arge.1.fduplex=1
+
+# Where the ART is - last 64k in the flash
+# 0x9fff1000 ?
+hint.ath.0.eepromaddr=0x1fff0000
+hint.ath.0.eepromsize=16384
+
+# The AP121 16MB flash layout:
+#
+# [ 0.700000] 0x000000000000-0x000000040000 : "u-boot"
+# [ 0.710000] 0x000000040000-0x000000050000 : "u-boot-env"
+# [ 0.710000] 0x000000050000-0x000000250000 : "kernel"
+# [ 0.720000] 0x000000250000-0x000000fe0000 : "rootfs"
+# [ 0.720000] mtd: partition "rootfs" set to be root filesystem
+# [ 0.730000] mtd: partition "rootfs_data" created automatically, ofs=480000, len=B60000
+# [ 0.740000] 0x000000480000-0x000000fe0000 : "rootfs_data"
+# [ 0.740000] 0x000000fe0000-0x000000ff0000 : "nvram"
+# [ 0.750000] 0x000000ff0000-0x000001000000 : "art"
+# [ 0.750000] 0x000000050000-0x000000fe0000 : "firmware"
+
+hint.map.0.at="flash/spi0"
+hint.map.0.start=0x00000000
+hint.map.0.end=0x000040000
+hint.map.0.name="uboot"
+hint.map.0.readonly=1
+
+hint.map.1.at="flash/spi0"
+hint.map.1.start=0x00040000
+hint.map.1.end=0x00050000
+hint.map.1.name="uboot-env"
+hint.map.1.readonly=0
+
+hint.map.2.at="flash/spi0"
+hint.map.2.start=0x00050000
+hint.map.2.end=0x00250000
+hint.map.2.name="kernel"
+hint.map.2.readonly=0
+
+hint.map.3.at="flash/spi0"
+hint.map.3.start=0x00250000
+hint.map.3.end=0x00fe0000
+hint.map.3.name="rootfs"
+hint.map.3.readonly=0
+
+hint.map.4.at="flash/spi0"
+hint.map.4.start=0x00fe0000
+hint.map.4.end=0x00ff0000
+hint.map.4.name="cfg"
+hint.map.4.readonly=0
+
+# This is radio calibration section. It is (or should be!) unique
+# for each board, to take into account thermal and electrical differences
+# as well as the regulatory compliance data.
+#
+hint.map.5.at="flash/spi0"
+hint.map.5.start=0x00ff0000
+hint.map.5.end=0x01000000
+hint.map.5.name="art"
+hint.map.5.readonly=1
+
+# GPIO specific configuration block
+
+# Don't flip on anything that isn't already enabled.
+# This includes leaving the SPI CS1/CS2 pins as GPIO pins as they're
+# not used here.
+hint.gpio.0.function_set=0x00000000
+hint.gpio.0.function_clear=0x00000000
+
+# These are the GPIO LEDs and buttons which can be software controlled.
+#hint.gpio.0.pinmask=0x001c02ae
+hint.gpio.0.pinmask=0x00001803
+
+# gpio0 - WLAN LED
+# gpio1 - USB LED
+# gpio11 - Jumpstart button
+# gpio12 - Reset button
+
+# LEDs are configured separately and driven by the LED device
+hint.gpioled.0.at="gpiobus0"
+hint.gpioled.0.name="wlan"
+hint.gpioled.0.pins=0x0001
+
+hint.gpioled.1.at="gpiobus0"
+hint.gpioled.1.name="usb"
+hint.gpioled.1.pins=0x0002
Property changes on: trunk/sys/mips/conf/CARAMBOLA2.hints
___________________________________________________________________
Added: mnbsd:nokeywords
## -0,0 +1 ##
+MidnightBSD=%H
\ No newline at end of property
Added: trunk/sys/mips/conf/DB120
===================================================================
--- trunk/sys/mips/conf/DB120 (rev 0)
+++ trunk/sys/mips/conf/DB120 2018-05-26 21:55:02 UTC (rev 9987)
@@ -0,0 +1,46 @@
+#
+# DB120 - the AR9344 SoC reference design
+#
+# $FreeBSD: stable/10/sys/mips/conf/DB120 253512 2013-07-21 04:00:48Z adrian $
+#
+
+# Include the default AR934x parameters
+include "AR934X_BASE"
+
+ident DB120
+
+# Override hints with board values
+hints "DB120.hints"
+
+# Force the board memory - the base DB120 has 128MB RAM
+options AR71XX_REALMEM=(32*1024*1024)
+
+# i2c GPIO bus
+#device gpioiic
+#device iicbb
+#device iicbus
+#device iic
+
+# Options required for miiproxy and mdiobus
+options ARGE_MDIO # Export an MDIO bus separate from arge
+device miiproxy # MDIO bus <-> MII PHY rendezvous
+
+device etherswitch
+device arswitch
+
+# read MSDOS formatted disks - USB
+#options MSDOSFS
+
+# Enable the uboot environment stuff rather then the
+# redboot stuff.
+options AR71XX_ENV_UBOOT
+
+# uzip - to boot natively from flash
+device geom_uncompress
+options GEOM_UNCOMPRESS
+
+# Used for the static uboot partition map
+device geom_map
+
+# Boot off of the rootfs, as defined in the geom_map setup.
+options ROOTDEVNAME=\"ufs:map/rootfs.uncompress\"
Property changes on: trunk/sys/mips/conf/DB120
___________________________________________________________________
Added: mnbsd:nokeywords
## -0,0 +1 ##
+MidnightBSD=%H
\ No newline at end of property
Added: trunk/sys/mips/conf/DB120.hints
===================================================================
--- trunk/sys/mips/conf/DB120.hints (rev 0)
+++ trunk/sys/mips/conf/DB120.hints 2018-05-26 21:55:02 UTC (rev 9987)
@@ -0,0 +1,3 @@
+# $FreeBSD: stable/10/sys/mips/conf/DB120.hints 253512 2013-07-21 04:00:48Z adrian $
+
+# This is a placeholder until the hardware support is complete.
Property changes on: trunk/sys/mips/conf/DB120.hints
___________________________________________________________________
Added: mnbsd:nokeywords
## -0,0 +1 ##
+MidnightBSD=%H
\ No newline at end of property
Added: trunk/sys/mips/conf/DEFAULTS
===================================================================
--- trunk/sys/mips/conf/DEFAULTS (rev 0)
+++ trunk/sys/mips/conf/DEFAULTS 2018-05-26 21:55:02 UTC (rev 9987)
@@ -0,0 +1,11 @@
+#
+# DEFAULTS -- Default kernel configuration file for FreeBSD/mips
+#
+# $FreeBSD: stable/10/sys/mips/conf/DEFAULTS 232619 2012-03-06 20:01:25Z attilio $
+
+device mem
+
+device uart_ns8250
+
+options GEOM_PART_BSD
+options GEOM_PART_MBR
Property changes on: trunk/sys/mips/conf/DEFAULTS
___________________________________________________________________
Added: mnbsd:nokeywords
## -0,0 +1 ##
+MidnightBSD=%H
\ No newline at end of property
Added: trunk/sys/mips/conf/DIR-825
===================================================================
--- trunk/sys/mips/conf/DIR-825 (rev 0)
+++ trunk/sys/mips/conf/DIR-825 2018-05-26 21:55:02 UTC (rev 9987)
@@ -0,0 +1,71 @@
+#
+# Specific board setup for the D-Link DIR-825 router.
+#
+# The DIR-825 has the following hardware:
+#
+# + AR7161 CPU SoC
+# + AR9223 2.4GHz 11n
+# + AR9220 5GHz 11n
+# + RealTek RTL8366S Gigabit switch
+# + m25p64 based 8MB flash
+# + 64MB RAM
+# + uboot environment
+
+# $FreeBSD: stable/10/sys/mips/conf/DIR-825 255195 2013-09-03 22:33:06Z sbruno $
+
+include "AR71XX_BASE"
+ident "DIR-825"
+hints "DIR-825.hints"
+
+# Since the kernel image must fit inside 1024KiB, we have to build almost
+# everything as modules.
+nodevice random
+nodevice gpio
+nodevice gpioled
+nodevice gif
+nodevice gre
+nodevice if_bridge
+nodevice usb
+nodevice ehci
+nodevice wlan
+nodevice wlan_xauth
+nodevice wlan_acl
+nodevice wlan_wep
+nodevice wlan_tkip
+nodevice wlan_ccmp
+nodevice wlan_rssadapt
+nodevice wlan_amrr
+nodevice ath
+nodevice ath_pci
+nodevice ath_hal
+nodevice umass
+nodevice ath_rate_sample
+
+nooptions INET6
+
+# Don't include the SCSI/CAM strings in the default build
+options SCSI_NO_SENSE_STRINGS
+options SCSI_NO_OP_STRINGS
+
+# .. And no sysctl strings
+options NO_SYSCTL_DESCR
+
+# GEOM modules
+device geom_map # to get access to the SPI flash partitions
+device geom_uncompress # compressed in-memory filesystem hackery!
+options GEOM_UNCOMPRESS
+options GEOM_PART_GPT
+
+options ROOTDEVNAME=\"ufs:/dev/map/rootfs.uncompress\"
+options AR71XX_REALMEM=64*1024*1024
+
+options AR71XX_ENV_UBOOT
+
+options MSDOSFS # Read MSDOS filesystems; useful for USB/CF
+
+# options MD_ROOT
+# options MD_ROOT_SIZE="6144"
+
+options AR71XX_ATH_EEPROM # Fetch EEPROM/PCI config from flash
+options ATH_EEPROM_FIRMWARE # Use EEPROM from flash
+device firmware # Used by the above
Property changes on: trunk/sys/mips/conf/DIR-825
___________________________________________________________________
Added: mnbsd:nokeywords
## -0,0 +1 ##
+MidnightBSD=%H
\ No newline at end of property
Added: trunk/sys/mips/conf/DIR-825.hints
===================================================================
--- trunk/sys/mips/conf/DIR-825.hints (rev 0)
+++ trunk/sys/mips/conf/DIR-825.hints 2018-05-26 21:55:02 UTC (rev 9987)
@@ -0,0 +1,71 @@
+# $FreeBSD: stable/10/sys/mips/conf/DIR-825.hints 254690 2013-08-23 13:14:18Z sbruno $
+
+# arge0 is connected to the LAN side of the switch PHY.
+# arge1 is connected to the single port WAN side of the switch PHY.
+
+hint.arge.0.phymask=0x0
+hint.arge.0.media=1000
+hint.arge.0.fduplex=1
+hint.arge.0.eeprommac=0x1f66ffa0
+hint.arge.0.readascii=1
+
+hint.arge.1.phymask=0x0
+hint.arge.1.media=1000
+hint.arge.1.fduplex=1
+hint.arge.1.eeprommac=0x1f66ffb4
+hint.arge.1.readascii=1
+
+# ath0 - slot 17
+hint.pcib.0.bus.0.17.0.ath_fixup_addr=0x1f661000
+hint.pcib.0.bus.0.17.0.ath_fixup_size=4096
+
+# ath1 - slot 18
+hint.pcib.0.bus.0.18.0.ath_fixup_addr=0x1f665000
+hint.pcib.0.bus.0.18.0.ath_fixup_size=4096
+
+# .. and now, telling each ath(4) NIC where to find the firmware
+# image.
+hint.ath.0.eeprom_firmware="pcib.0.bus.0.17.0.eeprom_firmware"
+hint.ath.1.eeprom_firmware="pcib.0.bus.0.18.0.eeprom_firmware"
+
+# TODO: gpio LEDs
+
+# Geom MAP
+
+# The DIR-825 has an 8MB flash part - HOWEVER, the 64k caldata isn't
+# at the end of the flash. It's ~ 6MB into the flash image.
+
+# mtdparts=ar7100-nor0:256k(uboot),64k(Config),1024k(vmlinux),5184k(rootfs),64k(caldata)
+
+hint.map.0.at="flash/spi0"
+hint.map.0.start=0x00000000
+hint.map.0.end=0x000040000
+hint.map.0.name="uboot"
+hint.map.0.readonly=1
+
+# This config partition is the D-Link specific configuration area.
+# I'm re-purposing it for FreeBSD.
+hint.map.1.at="flash/spi0"
+hint.map.1.start=0x00040000
+hint.map.1.end=0x00050000
+hint.map.1.name="cfg"
+hint.map.1.readonly=0
+
+hint.map.2.at="flash/spi0"
+hint.map.2.start=0x0050000
+hint.map.2.end=0x00150000
+hint.map.2.name="kernel"
+hint.map.2.readonly=1
+
+hint.map.3.at="flash/spi0"
+hint.map.3.start=0x00150000
+hint.map.3.end=0x00660000
+hint.map.3.name="rootfs"
+hint.map.3.readonly=0
+
+hint.map.4.at="flash/spi0"
+hint.map.4.start=0x00660000
+hint.map.4.end=0x00670000
+hint.map.4.name="art"
+hint.map.4.readonly=1
+
Property changes on: trunk/sys/mips/conf/DIR-825.hints
___________________________________________________________________
Added: mnbsd:nokeywords
## -0,0 +1 ##
+MidnightBSD=%H
\ No newline at end of property
Added: trunk/sys/mips/conf/ENH200
===================================================================
--- trunk/sys/mips/conf/ENH200 (rev 0)
+++ trunk/sys/mips/conf/ENH200 2018-05-26 21:55:02 UTC (rev 9987)
@@ -0,0 +1,44 @@
+#
+# Specific board setup for the Engenius ENH-200 802.11bgn mesh node.
+#
+# The Engenius ENH-200 has the following hardware:
+#
+# + AR7240 CPU SoC
+# + AR9285 Wifi
+# + Integrated switch
+# + 8MB flash
+# + 32MB RAM
+# + uboot environment
+
+# $FreeBSD: stable/10/sys/mips/conf/ENH200 266331 2014-05-17 17:34:37Z ian $
+
+include "AR724X_BASE"
+ident "ENH200"
+hints "ENH200.hints"
+
+options AR71XX_REALMEM=32*1024*1024
+
+options AR71XX_ENV_UBOOT
+
+# For DOS - enable if required
+options MSDOSFS
+
+# uncompress - to boot read-only lzma natively from flash
+device geom_uncompress
+options GEOM_UNCOMPRESS
+options ROOTDEVNAME=\"ufs:/dev/map/rootfs.uncompress\"
+
+# Used for the static uboot partition map
+device geom_map
+
+# Options needed for the EEPROM based calibration/PCI configuration data.
+options AR71XX_ATH_EEPROM # Fetch EEPROM/PCI config from flash
+options ATH_EEPROM_FIRMWARE # Use EEPROM from flash
+device firmware # Used by the above
+
+# Options required for miiproxy and mdiobus
+options ARGE_MDIO # Export an MDIO bus separate from arge
+device miiproxy # MDIO bus <-> MII PHY rendezvous
+
+device etherswitch
+device arswitch
Property changes on: trunk/sys/mips/conf/ENH200
___________________________________________________________________
Added: mnbsd:nokeywords
## -0,0 +1 ##
+MidnightBSD=%H
\ No newline at end of property
Added: trunk/sys/mips/conf/ENH200.hints
===================================================================
--- trunk/sys/mips/conf/ENH200.hints (rev 0)
+++ trunk/sys/mips/conf/ENH200.hints 2018-05-26 21:55:02 UTC (rev 9987)
@@ -0,0 +1,124 @@
+# $FreeBSD: stable/10/sys/mips/conf/ENH200.hints 252691 2013-07-04 08:42:20Z adrian $
+
+# arge0 MDIO bus
+hint.argemdio.0.at="nexus0"
+hint.argemdio.0.maddr=0x19000000
+hint.argemdio.0.msize=0x1000
+hint.argemdio.0.order=0
+
+# arge1 MDIO bus doesn't exist on the AR7240
+
+# arge0: MII; dedicated PHY 4 on switch, connected via internal switch
+# MDIO bus.
+
+# hint.arge.0.eeprommac=0x83fe9ff0
+hint.arge.0.phymask=0x10 # PHY 4
+# hint.arge.0.miimode=2 # MII
+hint.arge.0.mdio=mdioproxy1 # Hanging off the arswitch MDIO bus
+
+# arge1: connected to the LAN switch MAC, at 1000BaseTX / GMII.
+hint.arge.1.phymask=0x0
+# hint.arge.1.miimode=1 # GMII
+hint.arge.1.media=1000 # Force to 1000BaseTX/full
+hint.arge.1.fduplex=1
+
+#
+# AR7240 switch config
+#
+hint.arswitch.0.at="mdio0"
+hint.arswitch.0.is_7240=1 # We need to be explicitly told this
+hint.arswitch.0.numphys=4 # 4 active switch PHYs (PHY 0 -> 3)
+hint.arswitch.0.phy4cpu=1 # Yes, PHY 4 == dedicated PHY
+hint.arswitch.0.is_rgmii=0 # No, not RGMII
+hint.arswitch.0.is_gmii=0 # No, not GMII
+
+# ath0 hint - pcie slot 0
+hint.pcib.0.bus.0.0.0.ath_fixup_addr=0x1fff1000
+hint.pcib.0.bus.0.0.0.ath_fixup_size=4096
+
+# ath0 - eeprom comes from here
+hint.ath.0.eeprom_firmware="pcib.0.bus.0.0.0.eeprom_firmware"
+
+# Signal leds
+hint.gpioled.0.at="gpiobus0"
+hint.gpioled.0.name="sig1"
+hint.gpioled.0.pins=0x0001 # pin 0
+hint.gpioled.1.at="gpiobus0"
+hint.gpioled.1.name="sig2"
+hint.gpioled.1.pins=0x0002 # pin 1
+hint.gpioled.2.at="gpiobus0"
+hint.gpioled.2.name="sig3"
+hint.gpioled.2.pins=0x0800 # pin 11
+hint.gpioled.3.at="gpiobus0"
+hint.gpioled.3.name="sig4"
+hint.gpioled.3.pins=0x0080 # pin 7
+
+# nvram mapping - XXX ?
+#hint.nvram.0.base=0x1f030000
+#hint.nvram.0.maxsize=0x2000
+#hint.nvram.0.flags=3 # 1 = No check, 2 = Format Generic
+#hint.nvram.1.base=0x1f032000
+#hint.nvram.1.maxsize=0x4000
+#hint.nvram.1.flags=3 # 1 = No check, 2 = Format Generic
+
+# GEOM_MAP
+#
+# The default bootargs:
+#
+# bootargs=console=ttyS0,115200 root=31:04 rootfstype=squashfs init=/etc/preinit mtdparts=ar7240-nor0:256k(u-boot),64k(u-boot-env),320k(custom),1024k(kernel),4928k(rootfs),1536k(failsafe),64k(ART) board=ENH200
+#
+# However there's not a lot of space in this image layout.
+#
+# Thus, an alternate layout will be used, complete with reconfiguring
+# uboot to use the new base address.
+#
+# 256k - uboot (0x000000 -> 0x040000)
+# 64k - uboot-env (0x040000 -> 0x050000)
+# 1728k - kernel (0x050000 -> 0x200000)
+# 6016k - rootfs (0x200000 -> 0x7e0000)
+# 64k - config (0x7e0000 -> 0x7f0000)
+# 64k - ART (0x7f0000 -> 0x800000)
+#
+# For this, the 'bootcmd' environment variable needs to be
+# changed to point to the new location:
+#
+# ar7240> setenv bootcmd 'bootm 0x9f050000'
+
+# uboot (256k)
+hint.map.0.at="flash/spi0"
+hint.map.0.start=0x00000000
+hint.map.0.end=0x00040000
+hint.map.0.name="uboot"
+hint.map.0.readonly=1
+
+# uboot-env (64k)
+hint.map.1.at="flash/spi0"
+hint.map.1.start=0x00040000
+hint.map.1.end=0x00050000
+hint.map.1.name="uboot-env"
+hint.map.1.readonly=1
+
+# kernel (1728k)
+hint.map.2.at="flash/spi0"
+hint.map.2.start=0x00050000
+hint.map.2.end=0x00200000
+hint.map.2.name="kernel"
+
+# rootfs (6016k)
+hint.map.3.at="flash/spi0"
+hint.map.3.start=0x00200000
+hint.map.3.end=0x007e0000
+hint.map.3.name="rootfs"
+
+# config (64k)
+hint.map.4.at="flash/spi0"
+hint.map.4.start=0x007e0000
+hint.map.4.end=0x007f0000
+hint.map.4.name="cfg"
+
+# ART (64k)
+hint.map.5.at="flash/spi0"
+hint.map.5.start=0x007f0000
+hint.map.5.end=0x00800000
+hint.map.5.name="ART"
+hint.map.5.readonly=1
Property changes on: trunk/sys/mips/conf/ENH200.hints
___________________________________________________________________
Added: mnbsd:nokeywords
## -0,0 +1 ##
+MidnightBSD=%H
\ No newline at end of property
Added: trunk/sys/mips/conf/GXEMUL
===================================================================
--- trunk/sys/mips/conf/GXEMUL (rev 0)
+++ trunk/sys/mips/conf/GXEMUL 2018-05-26 21:55:02 UTC (rev 9987)
@@ -0,0 +1,63 @@
+#
+# GXEMUL "oldtestmips" sample kernel configuration.
+#
+# $FreeBSD: stable/10/sys/mips/conf/GXEMUL 253845 2013-07-31 17:21:18Z obrien $
+#
+
+ident GXEMUL
+
+machine mips mips64
+cpu CPU_MIPS4KC
+
+options HZ=100
+
+makeoptions ARCH_FLAGS="-march=mips64 -mabi=64"
+
+makeoptions KERNLOADADDR=0xffffffff80100000
+
+include "../gxemul/std.gxemul"
+
+hints "GXEMUL.hints" #Default places to look for devices.
+
+makeoptions DEBUG=-g #Build kernel with gdb(1) debug symbols
+
+makeoptions MODULES_OVERRIDE=""
+
+options DDB
+options KDB
+
+# Make an SMP-capable kernel by default
+options SMP # Symmetric MultiProcessor Kernel
+
+options SCHED_ULE
+options INET # InterNETworking
+options INET6 # IPv6 communications protocols
+
+options FFS #Berkeley Fast Filesystem
+
+# Debugging for use in -current
+#options DEADLKRES #Enable the deadlock resolver
+options INVARIANTS #Enable calls of extra sanity checking
+options INVARIANT_SUPPORT #Extra sanity checks of internal structures, required by INVARIANTS
+#options WITNESS #Enable checks to detect deadlocks and cycles
+#options WITNESS_SKIPSPIN #Don't run witness on spinlocks for speed
+
+options ROOTDEVNAME=\"ufs:gxemul_disk0\"
+
+device gxemul_cons
+device gxemul_disk
+device gxemul_ether
+
+# Pseudo devices.
+device loop # Network loopback
+device random # Entropy device
+device ether # Ethernet support
+device tun # Packet tunnel.
+device md # Memory "disks"
+device gif # IPv6 and IPv4 tunneling
+device faith # IPv6-to-IPv4 relaying (translation)
+
+# The `bpf' device enables the Berkeley Packet Filter.
+# Be aware of the administrative consequences of enabling this!
+# Note that 'bpf' is required for DHCP.
+device bpf # Berkeley packet filter
Property changes on: trunk/sys/mips/conf/GXEMUL
___________________________________________________________________
Added: mnbsd:nokeywords
## -0,0 +1 ##
+MidnightBSD=%H
\ No newline at end of property
Added: trunk/sys/mips/conf/GXEMUL.hints
===================================================================
--- trunk/sys/mips/conf/GXEMUL.hints (rev 0)
+++ trunk/sys/mips/conf/GXEMUL.hints 2018-05-26 21:55:02 UTC (rev 9987)
@@ -0,0 +1 @@
+# $FreeBSD: stable/10/sys/mips/conf/GXEMUL.hints 234920 2012-05-02 08:10:15Z rwatson $
Property changes on: trunk/sys/mips/conf/GXEMUL.hints
___________________________________________________________________
Added: mnbsd:nokeywords
## -0,0 +1 ##
+MidnightBSD=%H
\ No newline at end of property
Added: trunk/sys/mips/conf/GXEMUL32
===================================================================
--- trunk/sys/mips/conf/GXEMUL32 (rev 0)
+++ trunk/sys/mips/conf/GXEMUL32 2018-05-26 21:55:02 UTC (rev 9987)
@@ -0,0 +1,61 @@
+#
+# GXEMUL "oldtestmips" sample kernel configuration.
+#
+# $FreeBSD: stable/10/sys/mips/conf/GXEMUL32 255212 2013-09-04 20:34:36Z gonzo $
+#
+
+ident GXEMUL
+
+machine mips mips
+cpu CPU_MIPS4KC
+
+options HZ=100
+
+makeoptions KERNLOADADDR=0x80100000
+
+include "../gxemul/std.gxemul"
+
+hints "GXEMUL.hints" #Default places to look for devices.
+
+makeoptions DEBUG=-g #Build kernel with gdb(1) debug symbols
+
+makeoptions MODULES_OVERRIDE=""
+
+options DDB
+options KDB
+
+# Make an SMP-capable kernel by default
+options SMP # Symmetric MultiProcessor Kernel
+
+options SCHED_ULE
+options INET # InterNETworking
+options INET6 # IPv6 communications protocols
+
+options FFS #Berkeley Fast Filesystem
+
+# Debugging for use in -current
+#options DEADLKRES #Enable the deadlock resolver
+options INVARIANTS #Enable calls of extra sanity checking
+options INVARIANT_SUPPORT #Extra sanity checks of internal structures, required by INVARIANTS
+#options WITNESS #Enable checks to detect deadlocks and cycles
+#options WITNESS_SKIPSPIN #Don't run witness on spinlocks for speed
+
+options ROOTDEVNAME=\"ufs:gxemul_disk0\"
+
+device gxemul_cons
+device gxemul_disk
+device gxemul_ether
+
+# Pseudo devices.
+device loop # Network loopback
+device random # Entropy device
+device ether # Ethernet support
+device tun # Packet tunnel.
+device md # Memory "disks"
+device gif # IPv6 and IPv4 tunneling
+device faith # IPv6-to-IPv4 relaying (translation)
+
+# The `bpf' device enables the Berkeley Packet Filter.
+# Be aware of the administrative consequences of enabling this!
+# Note that 'bpf' is required for DHCP.
+device bpf # Berkeley packet filter
Property changes on: trunk/sys/mips/conf/GXEMUL32
___________________________________________________________________
Added: mnbsd:nokeywords
## -0,0 +1 ##
+MidnightBSD=%H
\ No newline at end of property
Added: trunk/sys/mips/conf/IDT
===================================================================
--- trunk/sys/mips/conf/IDT (rev 0)
+++ trunk/sys/mips/conf/IDT 2018-05-26 21:55:02 UTC (rev 9987)
@@ -0,0 +1,54 @@
+# $FreeBSD: stable/10/sys/mips/conf/IDT 221753 2011-05-11 00:52:41Z gonzo $
+
+cpu CPU_MIPS4KC
+ident RB532
+
+# Don't build any modules yet.
+makeoptions MODULES_OVERRIDE=""
+
+include "../idt/std.idt"
+hints "IDT.hints" #Default places to look for devices.
+
+makeoptions DEBUG=-g #Build kernel with gdb(1) debug symbols
+
+options DDB
+options KDB
+
+options SCHED_4BSD #4BSD scheduler
+options INET #InterNETworking
+options NFSCL #Network Filesystem Client
+options NFS_ROOT #NFS usable as /, requires NFSCL
+options PSEUDOFS #Pseudo-filesystem framework
+
+options BOOTP
+options BOOTP_NFSROOT
+options BOOTP_NFSV3
+options BOOTP_WIRED_TO=kr0
+options BOOTP_COMPAT
+
+# Debugging for use in -current
+#options DEADLKRES #Enable the deadlock resolver
+options INVARIANTS #Enable calls of extra sanity checking
+options INVARIANT_SUPPORT #Extra sanity checks of internal structures, required by INVARIANTS
+
+device loop
+device pci
+device ether
+device miibus
+device vr
+device kr
+device uart
+device md
+
+# Wireless NIC cards
+device wlan # 802.11 support
+device wlan_wep # 802.11 WEP support
+device wlan_tkip # 802.11 TKIP support
+device ath # Atheros NIC's
+device ath_pci # Atheros pci/cardbus glue
+device ath_hal # pci/cardbus chip support
+options AH_SUPPORT_AR5416 # enable AR5416 tx/rx descriptors
+device ath_rate_sample # SampleRate tx rate control for ath
+options ATH_DEBUG
+
+device bpf
Property changes on: trunk/sys/mips/conf/IDT
___________________________________________________________________
Added: mnbsd:nokeywords
## -0,0 +1 ##
+MidnightBSD=%H
\ No newline at end of property
Added: trunk/sys/mips/conf/IDT.hints
===================================================================
--- trunk/sys/mips/conf/IDT.hints (rev 0)
+++ trunk/sys/mips/conf/IDT.hints 2018-05-26 21:55:02 UTC (rev 9987)
@@ -0,0 +1,22 @@
+# $FreeBSD: stable/10/sys/mips/conf/IDT.hints 202175 2010-01-12 21:36:08Z imp $
+# device.hints
+hint.obio.0.at="nexus0"
+hint.obio.0.maddr=0x0
+hint.obio.0.msize=0x1fffffff
+
+# host-to-pci bridge
+hint.pcib.0.at="obio0"
+# hint.pcib.0.maddr=0x11400000
+# hint.pcib.0.msize=0x100000
+# hint.pcib.0.io=0x11500000
+# hint.pcib.0.iosize=0x100000
+
+# uart0
+hint.uart.0.at="obio0"
+hint.uart.0.maddr=0x18058000
+hint.uart.0.msize=0x1C
+hint.uart.0.irq=104
+
+hint.kr.0.at="obio0"
+hint.kr.0.maddr=0x18060000
+hint.kr.0.msize=0x10000
Property changes on: trunk/sys/mips/conf/IDT.hints
___________________________________________________________________
Added: mnbsd:nokeywords
## -0,0 +1 ##
+MidnightBSD=%H
\ No newline at end of property
Added: trunk/sys/mips/conf/MALTA
===================================================================
--- trunk/sys/mips/conf/MALTA (rev 0)
+++ trunk/sys/mips/conf/MALTA 2018-05-26 21:55:02 UTC (rev 9987)
@@ -0,0 +1,70 @@
+# MALTA -- Kernel config for MALTA boards
+#
+# For more information on this file, please read the handbook section on
+# Kernel Configuration Files:
+#
+# http://www.FreeBSD.org/doc/en_US.ISO8859-1/books/handbook/kernelconfig-config.html
+#
+# The handbook is also available locally in /usr/share/doc/handbook
+# if you've installed the doc distribution, otherwise always see the
+# FreeBSD World Wide Web server (http://www.FreeBSD.org/) for the
+# latest information.
+#
+# An exhaustive list of options and more detailed explanations of the
+# device lines is also present in the ../../conf/NOTES and NOTES files.
+# If you are in doubt as to the purpose or necessity of a line, check first
+# in NOTES.
+#
+# $FreeBSD: stable/10/sys/mips/conf/MALTA 255989 2013-10-02 14:43:17Z sbruno $
+
+ident MALTA
+
+machine mips mipsel # Malta supports both, so it isn't in std.malta
+
+makeoptions KERNLOADADDR=0x80100000
+
+options YAMON
+
+# Don't build any modules yet.
+makeoptions MODULES_OVERRIDE=""
+
+options TICK_USE_YAMON_FREQ=defined
+#options TICK_USE_MALTA_RTC=defined
+
+include "../malta/std.malta"
+
+hints "MALTA.hints" #Default places to look for devices.
+
+makeoptions DEBUG=-g #Build kernel with gdb(1) debug symbols
+
+options DDB
+options KDB
+
+options SCHED_4BSD #4BSD scheduler
+options INET #InterNETworking
+options NFSCL #Network Filesystem Client
+options NFS_ROOT #NFS usable as /, requires NFSCL
+options PSEUDOFS #Pseudo-filesystem framework
+options _KPOSIX_PRIORITY_SCHEDULING #Posix P1003_1B real-time extensions
+
+options FFS #Berkeley Fast Filesystem
+options SOFTUPDATES #Enable FFS soft updates support
+options UFS_ACL #Support for access control lists
+options UFS_DIRHASH #Improve performance on big directories
+options ROOTDEVNAME=\"ufs:ada0\"
+
+
+# Debugging for use in -current
+#options DEADLKRES #Enable the deadlock resolver
+options INVARIANTS #Enable calls of extra sanity checking
+options INVARIANT_SUPPORT #Extra sanity checks of internal structures, required by INVARIANTS
+#options WITNESS #Enable checks to detect deadlocks and cycles
+#options WITNESS_SKIPSPIN #Don't run witness on spinlocks for speed
+
+device loop
+device ether
+device le
+device miibus
+device bpf
+device md
+device uart
Property changes on: trunk/sys/mips/conf/MALTA
___________________________________________________________________
Added: mnbsd:nokeywords
## -0,0 +1 ##
+MidnightBSD=%H
\ No newline at end of property
Added: trunk/sys/mips/conf/MALTA.hints
===================================================================
--- trunk/sys/mips/conf/MALTA.hints (rev 0)
+++ trunk/sys/mips/conf/MALTA.hints 2018-05-26 21:55:02 UTC (rev 9987)
@@ -0,0 +1,5 @@
+# $FreeBSD: stable/10/sys/mips/conf/MALTA.hints 202175 2010-01-12 21:36:08Z imp $
+# device.hints
+# hint.uart.0.at="nexus"
+# hint.uart.0.maddr="0x180003f8"
+# hint.uart.0.flags="0x90"
Property changes on: trunk/sys/mips/conf/MALTA.hints
___________________________________________________________________
Added: mnbsd:nokeywords
## -0,0 +1 ##
+MidnightBSD=%H
\ No newline at end of property
Added: trunk/sys/mips/conf/MALTA64
===================================================================
--- trunk/sys/mips/conf/MALTA64 (rev 0)
+++ trunk/sys/mips/conf/MALTA64 2018-05-26 21:55:02 UTC (rev 9987)
@@ -0,0 +1,72 @@
+# MALTA -- Kernel config for MALTA boards
+#
+# For more information on this file, please read the handbook section on
+# Kernel Configuration Files:
+#
+# http://www.FreeBSD.org/doc/en_US.ISO8859-1/books/handbook/kernelconfig-config.html
+#
+# The handbook is also available locally in /usr/share/doc/handbook
+# if you've installed the doc distribution, otherwise always see the
+# FreeBSD World Wide Web server (http://www.FreeBSD.org/) for the
+# latest information.
+#
+# An exhaustive list of options and more detailed explanations of the
+# device lines is also present in the ../../conf/NOTES and NOTES files.
+# If you are in doubt as to the purpose or necessity of a line, check first
+# in NOTES.
+#
+# $FreeBSD: stable/10/sys/mips/conf/MALTA64 255089 2013-08-31 01:30:01Z gonzo $
+
+ident MALTA
+
+machine mips mips64el # Malta supports both, so it isn't in std.malta
+
+makeoptions ARCH_FLAGS="-march=mips64 -mabi=64"
+
+options YAMON
+
+# Don't build any modules yet.
+makeoptions MODULES_OVERRIDE=""
+
+options TICK_USE_YAMON_FREQ=defined
+#options TICK_USE_MALTA_RTC=defined
+
+makeoptions KERNLOADADDR=0xffffffff80100000
+
+include "../malta/std.malta"
+
+hints "MALTA.hints" #Default places to look for devices.
+
+makeoptions DEBUG=-g #Build kernel with gdb(1) debug symbols
+
+options DDB
+options KDB
+
+options SCHED_4BSD #4BSD scheduler
+options INET #InterNETworking
+options NFSCL #Network Filesystem Client
+options NFS_ROOT #NFS usable as /, requires NFSCL
+options PSEUDOFS #Pseudo-filesystem framework
+options _KPOSIX_PRIORITY_SCHEDULING #Posix P1003_1B real-time extensions
+
+options FFS #Berkeley Fast Filesystem
+options SOFTUPDATES #Enable FFS soft updates support
+options UFS_ACL #Support for access control lists
+options UFS_DIRHASH #Improve performance on big directories
+options ROOTDEVNAME=\"ufs:ada0s1a\"
+
+
+# Debugging for use in -current
+#options DEADLKRES #Enable the deadlock resolver
+options INVARIANTS #Enable calls of extra sanity checking
+options INVARIANT_SUPPORT #Extra sanity checks of internal structures, required by INVARIANTS
+#options WITNESS #Enable checks to detect deadlocks and cycles
+#options WITNESS_SKIPSPIN #Don't run witness on spinlocks for speed
+
+device loop
+device ether
+device le
+device miibus
+device md
+device bpf
+device uart
Property changes on: trunk/sys/mips/conf/MALTA64
___________________________________________________________________
Added: mnbsd:nokeywords
## -0,0 +1 ##
+MidnightBSD=%H
\ No newline at end of property
Added: trunk/sys/mips/conf/OCTEON1
===================================================================
--- trunk/sys/mips/conf/OCTEON1 (rev 0)
+++ trunk/sys/mips/conf/OCTEON1 2018-05-26 21:55:02 UTC (rev 9987)
@@ -0,0 +1,322 @@
+#
+# OCTEON1 -- Generic kernel configuration file for FreeBSD/MIPS on Cavium Octeon
+#
+# For more information on this file, please read the config(5) manual page,
+# and/or the handbook section on Kernel Configuration Files:
+#
+# http://www.FreeBSD.org/doc/en_US.ISO8859-1/books/handbook/kernelconfig-config.html
+#
+# The handbook is also available locally in /usr/share/doc/handbook
+# if you've installed the doc distribution, otherwise always see the
+# FreeBSD World Wide Web server (http://www.FreeBSD.org/) for the
+# latest information.
+#
+# An exhaustive list of options and more detailed explanations of the
+# device lines is also present in the ../../conf/NOTES and NOTES files.
+# If you are in doubt as to the purpose or necessity of a line, check first
+# in NOTES.
+#
+# $FreeBSD: stable/10/sys/mips/conf/OCTEON1 265388 2014-05-05 20:35:35Z ken $
+
+ident OCTEON1
+
+makeoptions ARCH_FLAGS="-march=octeon -mabi=64"
+makeoptions LDSCRIPT_NAME=ldscript.mips.octeon1
+
+# Don't build any modules yet.
+makeoptions MODULES_OVERRIDE=""
+makeoptions KERNLOADADDR=0xffffffff80100000
+
+# We don't need to build a trampolined version of the kernel.
+makeoptions WITHOUT_KERNEL_TRAMPOLINE=1
+
+include "../cavium/std.octeon1"
+
+hints "OCTEON1.hints" #Default places to look for devices.
+
+makeoptions DEBUG=-g #Build kernel with gdb(1) debug symbols
+
+# Board-specific support that cannot be auto-detected at runtime.
+#options OCTEON_VENDOR_LANNER # Support for Lanner boards.
+#options OCTEON_VENDOR_RADISYS # Support for Radisys boards.
+#options OCTEON_VENDOR_UBIQUITI # Support for Ubiquiti boards.
+#options OCTEON_VENDOR_GEFES # Support for GE LANIC boards
+#options OCTEON_BOARD_CAPK_0100ND # Support for CAPK-0100nd.
+
+# Compile for a specified Octeon model. If not specified, support for
+# detection at runtime will be used instead, which may give inferior
+# performance.
+#
+# See sys/contrib/octeon-sdk/octeon-model.h for possible values.
+#options OCTEON_MODEL=OCTEON_CN58XX_PASS1_1
+
+options SCHED_ULE # ULE scheduler
+options PREEMPTION # Enable kernel thread preemption
+options INET # InterNETworking
+options INET6 # IPv6 communications protocols
+options SCTP # Stream Control Transmission Protocol
+options FFS # Berkeley Fast Filesystem
+options SOFTUPDATES # Enable FFS soft updates support
+options UFS_ACL # Support for access control lists
+options UFS_DIRHASH # Improve performance on big directories
+options UFS_GJOURNAL # Enable gjournal-based UFS journaling
+options MD_ROOT # MD is a potential root device
+options NFSCL # Network Filesystem Client
+options NFSD # Network Filesystem Server
+options NFSLOCKD # Network Lock Manager
+options NFS_ROOT # NFS usable as /, requires NFSCL
+options MSDOSFS # MSDOS Filesystem
+options CD9660 # ISO 9660 Filesystem
+options PROCFS # Process filesystem (requires PSEUDOFS)
+options PSEUDOFS # Pseudo-filesystem framework
+options GEOM_PART_GPT # GUID Partition Tables.
+options GEOM_LABEL # Provides labelization
+options COMPAT_FREEBSD32 # Compatible with o32 binaries
+options SCSI_DELAY=5000 # Delay (in ms) before probing SCSI
+options KTRACE # ktrace(1) support
+options STACK # stack(9) support
+options SYSVSHM # SYSV-style shared memory
+options SYSVMSG # SYSV-style message queues
+options SYSVSEM # SYSV-style semaphores
+options _KPOSIX_PRIORITY_SCHEDULING # POSIX P1003_1B real-time extensions
+options PRINTF_BUFR_SIZE=128 # Prevent printf output being interspersed.
+options HWPMC_HOOKS # Necessary kernel hooks for hwpmc(4)
+options AUDIT # Security event auditing
+options MAC # TrustedBSD MAC Framework
+#options KDTRACE_FRAME # Ensure frames are compiled in
+#options KDTRACE_HOOKS # Kernel DTrace hooks
+options INCLUDE_CONFIG_FILE # Include this file in kernel
+options NO_SWAPPING # Disable support for paging
+
+# Debugging for use in -current
+options KDB # Enable kernel debugger support.
+options DDB # Support DDB.
+options GDB # Support remote GDB.
+options DEADLKRES # Enable the deadlock resolver
+options INVARIANTS # Enable calls of extra sanity checking
+options INVARIANT_SUPPORT # Extra sanity checks of internal structures, required by INVARIANTS
+options WITNESS # Enable checks to detect deadlocks and cycles
+options WITNESS_SKIPSPIN # Don't run witness on spinlocks for speed
+options MALLOC_DEBUG_MAXZONES=8 # Separate malloc(9) zones
+
+# Make an SMP-capable kernel by default
+options SMP # Symmetric MultiProcessor Kernel
+
+# Bus support.
+device pci
+
+# ATA controllers
+device ahci # AHCI-compatible SATA controllers
+device ata # Legacy ATA/SATA controllers
+options ATA_STATIC_ID # Static device numbering
+device mvs # Marvell 88SX50XX/88SX60XX/88SX70XX/SoC SATA
+device siis # SiliconImage SiI3124/SiI3132/SiI3531 SATA
+
+# On-board Compact Flash driver.
+device cf
+options ROOTDEVNAME=\"ufs:cf0s2a\" # Default root filesystem.
+
+# SCSI Controllers
+device ahc # AHA2940 and onboard AIC7xxx devices
+options AHC_REG_PRETTY_PRINT # Print register bitfields in debug
+ # output. Adds ~128k to driver.
+device ahd # AHA39320/29320 and onboard AIC79xx devices
+options AHD_REG_PRETTY_PRINT # Print register bitfields in debug
+ # output. Adds ~215k to driver.
+device esp # AMD Am53C974 (Tekram DC-390(T))
+device hptiop # Highpoint RocketRaid 3xxx series
+device isp # Qlogic family
+#device ispfw # Firmware for QLogic HBAs- normally a module
+device mpt # LSI-Logic MPT-Fusion
+device mps # LSI-Logic MPT-Fusion 2
+device mpr # LSI-Logic MPT-Fusion 3
+#device ncr # NCR/Symbios Logic
+device trm # Tekram DC395U/UW/F DC315U adapters
+
+device adv # Advansys SCSI adapters
+device adw # Advansys wide SCSI adapters
+device aic # Adaptec 15[012]x SCSI adapters, AIC-6[23]60.
+device bt # Buslogic/Mylex MultiMaster SCSI adapters
+
+# ATA/SCSI peripherals
+device scbus # SCSI bus (required for ATA/SCSI)
+device ch # SCSI media changers
+device da # Direct Access (disks)
+device sa # Sequential Access (tape etc)
+device cd # CD
+device pass # Passthrough device (direct ATA/SCSI access)
+device ses # Enclosure Services (SES and SAF-TE)
+
+# RAID controllers interfaced to the SCSI subsystem
+device amr # AMI MegaRAID
+#XXX it is not 64-bit clean, -scottl
+#device asr # DPT SmartRAID V, VI and Adaptec SCSI RAID
+device ciss # Compaq Smart RAID 5*
+device dpt # DPT Smartcache III, IV - See NOTES for options
+device iir # Intel Integrated RAID
+device ips # IBM (Adaptec) ServeRAID
+device mly # Mylex AcceleRAID/eXtremeRAID
+
+# RAID controllers
+device aac # Adaptec FSA RAID
+device aacp # SCSI passthrough for aac (requires CAM)
+device ida # Compaq Smart RAID
+device mfi # LSI MegaRAID SAS
+device mlx # Mylex DAC960 family
+#XXX pointer/int warnings
+#device pst # Promise Supertrak SX6000
+device twe # 3ware ATA RAID
+
+# PCCARD (PCMCIA) support
+# PCMCIA and cardbus bridge support
+device cbb # cardbus (yenta) bridge
+device pccard # PC Card (16-bit) bus
+device cardbus # CardBus (32-bit) bus
+
+# Serial (COM) ports
+device uart # Generic UART driver
+
+# If you've got a "dumb" serial or parallel PCI card that is
+# supported by the puc(4) glue driver, uncomment the following
+# line to enable it (connects to sio, uart and/or ppc drivers):
+#device puc
+
+# On-board Cavium Octeon Ethernet.
+# NOTE: Be sure to keep the 'device miibus' line in order to use these NICs!
+device octe
+
+# Cavium Octeon management Ethernet.
+device octm
+
+# Switch PHY support for the octe driver. These currently present a VLAN per
+# physical port, but may eventually provide support for DSA or similar instead.
+#device mv88e61xxphy # Marvell 88E61XX
+
+# PCI Ethernet NICs.
+device de # DEC/Intel DC21x4x (``Tulip'')
+device em # Intel PRO/1000 Gigabit Ethernet Family
+device igb # Intel PRO/1000 PCIE Server Gigabit Family
+device ixgbe # Intel PRO/10GbE PCIE Ethernet Family
+device le # AMD Am7900 LANCE and Am79C9xx PCnet
+device ti # Alteon Networks Tigon I/II gigabit Ethernet
+device txp # 3Com 3cR990 (``Typhoon'')
+device vx # 3Com 3c590, 3c595 (``Vortex'')
+
+# PCI Ethernet NICs that use the common MII bus controller code.
+# NOTE: Be sure to keep the 'device miibus' line in order to use these NICs!
+device miibus # MII bus support
+device ae # Attansic/Atheros L2 FastEthernet
+device age # Attansic/Atheros L1 Gigabit Ethernet
+device alc # Atheros AR8131/AR8132 Ethernet
+device ale # Atheros AR8121/AR8113/AR8114 Ethernet
+device bce # Broadcom BCM5706/BCM5708 Gigabit Ethernet
+device bfe # Broadcom BCM440x 10/100 Ethernet
+device bge # Broadcom BCM570xx Gigabit Ethernet
+device dc # DEC/Intel 21143 and various workalikes
+device et # Agere ET1310 10/100/Gigabit Ethernet
+device fxp # Intel EtherExpress PRO/100B (82557, 82558)
+device jme # JMicron JMC250 Gigabit/JMC260 Fast Ethernet
+device lge # Level 1 LXT1001 gigabit Ethernet
+device msk # Marvell/SysKonnect Yukon II Gigabit Ethernet
+device nge # NatSemi DP83820 gigabit Ethernet
+#device nve # nVidia nForce MCP on-board Ethernet Networking
+device pcn # AMD Am79C97x PCI 10/100 (precedence over 'le')
+device re # RealTek 8139C+/8169/8169S/8110S
+device rl # RealTek 8129/8139
+device sf # Adaptec AIC-6915 (``Starfire'')
+device sge # Silicon Integrated Systems SiS190/191
+device sis # Silicon Integrated Systems SiS 900/SiS 7016
+device sk # SysKonnect SK-984x & SK-982x gigabit Ethernet
+device ste # Sundance ST201 (D-Link DFE-550TX)
+device stge # Sundance/Tamarack TC9021 gigabit Ethernet
+device tl # Texas Instruments ThunderLAN
+device tx # SMC EtherPower II (83c170 ``EPIC'')
+device vge # VIA VT612x gigabit Ethernet
+device vr # VIA Rhine, Rhine II
+device wb # Winbond W89C840F
+device xl # 3Com 3c90x (``Boomerang'', ``Cyclone'')
+
+# Wireless NIC cards
+device wlan # 802.11 support
+options IEEE80211_DEBUG # enable debug msgs
+options IEEE80211_AMPDU_AGE # age frames in AMPDU reorder q's
+options IEEE80211_SUPPORT_MESH # enable 802.11s draft support
+device wlan_wep # 802.11 WEP support
+device wlan_ccmp # 802.11 CCMP support
+device wlan_tkip # 802.11 TKIP support
+device wlan_amrr # AMRR transmit rate control algorithm
+device an # Aironet 4500/4800 802.11 wireless NICs.
+device ath # Atheros NIC's
+device ath_pci # Atheros pci/cardbus glue
+device ath_hal # pci/cardbus chip support
+options AH_SUPPORT_AR5416 # enable AR5416 tx/rx descriptors
+device ath_rate_sample # SampleRate tx rate control for ath
+device ral # Ralink Technology RT2500 wireless NICs.
+device wi # WaveLAN/Intersil/Symbol 802.11 wireless NICs.
+
+# Pseudo devices.
+device loop # Network loopback
+device random # Entropy device
+device ether # Ethernet support
+device vlan # 802.1Q VLAN support
+device tun # Packet tunnel.
+device md # Memory "disks"
+device gif # IPv6 and IPv4 tunneling
+device faith # IPv6-to-IPv4 relaying (translation)
+device firmware # firmware assist module
+
+# The `bpf' device enables the Berkeley Packet Filter.
+# Be aware of the administrative consequences of enabling this!
+# Note that 'bpf' is required for DHCP.
+device bpf # Berkeley packet filter
+
+# Hardware watchdog support.
+#device octeon_wdog # Octeon hardware watchdog
+
+# USB support
+options USB_DEBUG # enable debug msgs
+device octusb # Cavium Octeon on-board USB interface (USB 2.0)
+device uhci # UHCI PCI->USB interface
+device ohci # OHCI PCI->USB interface
+device ehci # EHCI PCI->USB interface (USB 2.0)
+device usb # USB Bus (required)
+#device udbp # USB Double Bulk Pipe devices
+device uhid # "Human Interface Devices"
+device ulpt # Printer
+device umass # Disks/Mass storage - Requires scbus and da
+device ums # Mouse
+device urio # Diamond Rio 500 MP3 player
+# USB Serial devices
+device u3g # USB-based 3G modems (Option, Huawei, Sierra)
+device uark # Technologies ARK3116 based serial adapters
+device ubsa # Belkin F5U103 and compatible serial adapters
+device uftdi # For FTDI usb serial adapters
+device uipaq # Some WinCE based devices
+device uplcom # Prolific PL-2303 serial adapters
+device uslcom # SI Labs CP2101/CP2102 serial adapters
+device uvisor # Visor and Palm devices
+device uvscom # USB serial support for DDI pocket's PHS
+# USB Ethernet, requires miibus
+device aue # ADMtek USB Ethernet
+device axe # ASIX Electronics USB Ethernet
+device cdce # Generic USB over Ethernet
+device cue # CATC USB Ethernet
+device kue # Kawasaki LSI USB Ethernet
+device rue # RealTek RTL8150 USB Ethernet
+device udav # Davicom DM9601E USB
+# USB Wireless
+device rum # Ralink Technology RT2501USB wireless NICs
+device uath # Atheros AR5523 wireless NICs
+device ural # Ralink Technology RT2500USB wireless NICs
+device zyd # ZyDAS zd1211/zd1211b wireless NICs
+
+# crypto subsystem
+device crypto # core crypto support
+device cryptodev # /dev/crypto for access to h/w
+device cryptocteon # Octeon coprocessor 2 crypto offload
+
+# GPIO support
+#device gpio
+
+# PMC support
+#device hwpmc
Property changes on: trunk/sys/mips/conf/OCTEON1
___________________________________________________________________
Added: mnbsd:nokeywords
## -0,0 +1 ##
+MidnightBSD=%H
\ No newline at end of property
Added: trunk/sys/mips/conf/OCTEON1.hints
===================================================================
--- trunk/sys/mips/conf/OCTEON1.hints (rev 0)
+++ trunk/sys/mips/conf/OCTEON1.hints 2018-05-26 21:55:02 UTC (rev 9987)
@@ -0,0 +1,13 @@
+# $FreeBSD: stable/10/sys/mips/conf/OCTEON1.hints 210311 2010-07-20 19:25:11Z jmallett $
+# device.hints
+# All these values are complete nonsense...
+hw.uart.console="io:0x1"
+hint.ciu.0.at="nexus"
+hint.rtc.0.at="nexus"
+hint.obio.0.at="ciu"
+hint.obio.0.maddr="0x1"
+hint.obio.0.msize="0x1"
+hint.obio.0.flags="0x1"
+hint.uart.0.at="obio"
+hint.uart.0.maddr="0x1"
+hint.uart.0.flags="0x1"
Property changes on: trunk/sys/mips/conf/OCTEON1.hints
___________________________________________________________________
Added: mnbsd:nokeywords
## -0,0 +1 ##
+MidnightBSD=%H
\ No newline at end of property
Added: trunk/sys/mips/conf/PB47
===================================================================
--- trunk/sys/mips/conf/PB47 (rev 0)
+++ trunk/sys/mips/conf/PB47 2018-05-26 21:55:02 UTC (rev 9987)
@@ -0,0 +1,40 @@
+#
+# Atheros PB47 reference board.
+#
+# * one MiniPCI+ slot (modified to allow two idsel lines
+# on the one slot, for a specific kind of internal-only
+# NIC;
+# * one XMII slot
+# * One ethernet PHY
+# * Akros Silicon AS1834
+# * 8MB NOR SPI flash
+# * 64MB RAM
+#
+# $FreeBSD: stable/10/sys/mips/conf/PB47 266331 2014-05-17 17:34:37Z ian $
+#
+
+include "AR71XX_BASE"
+ident "PB47"
+hints "PB47.hints"
+
+# Enable the uboot environment stuff rather then the
+# redboot stuff.
+options AR71XX_ENV_UBOOT
+
+# XXX TODO: add uboot boot parameter parsing to extract MAC, RAM.
+# Right now it will just detect 32mb out of 64mb, as well as
+# return a garbage MAC address.
+options AR71XX_REALMEM=64*1024*1024
+
+# For DOS - enable if required
+options MSDOSFS
+
+# uncompress - to boot read-only lzma natively from flash
+device geom_uncompress
+options GEOM_UNCOMPRESS
+
+# Used for the static uboot partition map
+device geom_map
+
+# Boot off of the rootfs, as defined in the geom_map setup.
+options ROOTDEVNAME=\"ufs:map/rootfs.uncompress\"
Property changes on: trunk/sys/mips/conf/PB47
___________________________________________________________________
Added: mnbsd:nokeywords
## -0,0 +1 ##
+MidnightBSD=%H
\ No newline at end of property
Added: trunk/sys/mips/conf/PB47.hints
===================================================================
--- trunk/sys/mips/conf/PB47.hints (rev 0)
+++ trunk/sys/mips/conf/PB47.hints 2018-05-26 21:55:02 UTC (rev 9987)
@@ -0,0 +1,79 @@
+
+# $FreeBSD: stable/10/sys/mips/conf/PB47.hints 228988 2011-12-30 09:48:35Z adrian $
+
+# There's two interfaces, but only one socket is populated.
+#
+# There's an AR8021 PHY attached to arge1.
+#
+# XXX TODO: figure out where to extract the MAC from.
+hint.arge.1.phymask=0x01
+
+# XXX TODO: pass in hints for the GPIO -> LED mapping for the
+# minipci slot. The specific customer reference design NIC
+# wires GPIO5 from each AR9220 to one of two GPIO pins on the
+# MiniPCI bus. However, this may be very specific to the NIC
+# being used.
+
+# The default flash layout:
+# uboot: 192k
+# env: 64k
+# rootfs: 6144k
+# uimage (kernel): 1728k
+# caldata: 64k
+#
+# We steal 64k from the end of rootfs to store the local config.
+
+hint.map.0.at="flash/spi0"
+hint.map.0.start=0x00000000
+hint.map.0.end=0x000030000
+hint.map.0.name="uboot"
+hint.map.0.readonly=1
+
+hint.map.1.at="flash/spi0"
+hint.map.1.start=0x00030000
+hint.map.1.end=0x00040000
+hint.map.1.name="uboot-env"
+hint.map.1.readonly=1
+
+hint.map.2.at="flash/spi0"
+hint.map.2.start=0x00040000
+hint.map.2.end=0x00630000
+hint.map.2.name="rootfs"
+hint.map.2.readonly=1
+
+hint.map.3.at="flash/spi0"
+hint.map.3.start=0x00630000
+hint.map.3.end=0x00640000
+hint.map.3.name="cfg"
+hint.map.3.readonly=0
+
+hint.map.4.at="flash/spi0"
+hint.map.4.start=0x00640000
+hint.map.4.end=0x007f0000
+hint.map.4.name="kernel"
+hint.map.4.readonly=1
+
+hint.map.5.at="flash/spi0"
+hint.map.5.start=0x007f0000
+hint.map.5.end=0x00800000
+hint.map.5.name="art"
+hint.map.5.readonly=1
+
+# Don't flip on anything that isn't already enabled by the
+# bootloader.
+hint.gpio.0.function_set=0x00000000
+hint.gpio.0.function_clear=0x00000000
+
+# Which GPIO lines to enable - just GPIO2/3 for the LEDs.
+hint.gpio.0.pinmask=0x0000000c
+
+# GPIO2 and GPIO3 are LEDs, where 0=on and 1=off.
+# XXX TODO: teach gpioled about polarity?
+hint.gpioled.0.at="gpiobus0"
+hint.gpioled.0.pins="0x0004"
+hint.gpioled.0.name="led1"
+
+hint.gpioled.1.at="gpiobus0"
+hint.gpioled.1.pins="0x0008"
+hint.gpioled.1.name="led2"
+
Property changes on: trunk/sys/mips/conf/PB47.hints
___________________________________________________________________
Added: mnbsd:nokeywords
## -0,0 +1 ##
+MidnightBSD=%H
\ No newline at end of property
Added: trunk/sys/mips/conf/PB92
===================================================================
--- trunk/sys/mips/conf/PB92 (rev 0)
+++ trunk/sys/mips/conf/PB92 2018-05-26 21:55:02 UTC (rev 9987)
@@ -0,0 +1,135 @@
+#
+# PB92 -- Kernel configuration file for FreeBSD/mips for Atheros PB92 reference
+# board (AR7242)
+#
+# $FreeBSD: stable/10/sys/mips/conf/PB92 266331 2014-05-17 17:34:37Z ian $
+#
+
+ident PB92
+# XXX The default load address in the Uboot environment is 0x80010000
+makeoptions KERNLOADADDR=0x80050000
+options HZ=1000
+
+# The PB92 has 32mb of RAM; hard-code that
+options AR71XX_REALMEM=32*1024*1024
+
+# It's UBOOT, not Redboot - without this, things will hang at startup
+options AR71XX_ENV_UBOOT
+
+# We have to build most things as modules rather than in the kernel.
+# The PB92 has 4MB of SPI flash and the default kernel "partition"
+# is only 892KiB. In order to try and squeeze into that (so people
+# who already are using it without modifying the default flash layout)
+# we need to cut down on a lot of things.
+
+makeoptions MODULES_OVERRIDE="ath ath_pci ath_ahb bridgestp if_bridge if_gif if_gre random wlan wlan_acl wlan_amrr wlan_ccmp wlan_rssadapt wlan_tkip wlan_wep wlan_xauth usb ar71xx"
+
+hints "PB92.hints"
+include "../atheros/std.ar71xx"
+
+makeoptions DEBUG=-g #Build kernel with gdb(1) debug symbols
+makeoptions MODULES_OVERRIDE=""
+
+options DDB
+options KDB
+
+options SCHED_4BSD #4BSD scheduler
+options INET #InterNETworking
+# Can't do IPv6 - it just doesn't fit.
+# options INET6
+# options NFSCL #Network Filesystem Client
+options PSEUDOFS #Pseudo-filesystem framework
+options _KPOSIX_PRIORITY_SCHEDULING #Posix P1003_1B real-time extensions
+options ALQ
+
+# Debugging for use in -current
+options DEADLKRES
+options INVARIANTS
+options INVARIANT_SUPPORT
+options WITNESS
+options WITNESS_SKIPSPIN
+options FFS #Berkeley Fast Filesystem
+#options SOFTUPDATES #Enable FFS soft updates support
+#options UFS_ACL #Support for access control lists
+#options UFS_DIRHASH #Improve performance on big directories
+
+# Support uncompress lzma rootfs
+device geom_uncompress
+options GEOM_UNCOMPRESS
+options ROOTDEVNAME=\"ufs:/dev/map/rootfs.uncompress\"
+
+# PCI bus
+device pci
+device ar724x_pci
+
+# NVRAM U-Boot Environment -> Kernel environment
+device nvram2env
+
+# Wireless NIC cards
+options IEEE80211_DEBUG
+options IEEE80211_SUPPORT_MESH
+options IEEE80211_SUPPORT_TDMA
+options IEEE80211_ALQ
+#device wlan # 802.11 support
+#device wlan_wep # 802.11 WEP support
+#device wlan_ccmp # 802.11 CCMP support
+#device wlan_tkip # 802.11 TKIP support
+#device wlan_xauth # 802.11 hostap support
+
+#device ath # Atheros pci/cardbus NIC's
+#device ath_pci # PCI/PCIe bus glue
+options ATH_DEBUG
+options ATH_ENABLE_11N
+options ATH_DIAGAPI
+
+# device ath_hal
+options AH_SUPPORT_AR5416
+options AH_DEBUG
+options AH_DEBUG_ALQ
+
+# device ath_rate_sample
+
+device mii
+device arge
+
+# USB devices - PB92 has EHCI only
+
+#device usb
+options USB_EHCI_BIG_ENDIAN_DESC # handle big-endian byte order
+options USB_DEBUG
+options USB_HOST_ALIGN=32
+#device ehci
+
+# Mass storage
+#device scbus
+#device umass
+#device da
+
+# Read MSDOS formatted disks
+# options MSDOSFS
+
+# GPIO Bus
+#device gpio
+#device gpioled
+
+# SPI and flash
+device spibus
+device ar71xx_spi
+device mx25l
+
+# The flash is statically partitioned; add in that
+device geom_map
+
+device ar71xx_wdog
+
+# Serial
+device uart
+device uart_ar71xx
+
+# Network twiddling
+device loop
+device ether
+#device md
+#device bpf
+#device random
+#device if_bridge
Property changes on: trunk/sys/mips/conf/PB92
___________________________________________________________________
Added: mnbsd:nokeywords
## -0,0 +1 ##
+MidnightBSD=%H
\ No newline at end of property
Added: trunk/sys/mips/conf/PB92.hints
===================================================================
--- trunk/sys/mips/conf/PB92.hints (rev 0)
+++ trunk/sys/mips/conf/PB92.hints 2018-05-26 21:55:02 UTC (rev 9987)
@@ -0,0 +1,113 @@
+# $FreeBSD: stable/10/sys/mips/conf/PB92.hints 221489 2011-05-05 09:04:49Z adrian $
+hint.apb.0.at="nexus0"
+hint.apb.0.irq=4
+
+# uart0
+hint.uart.0.at="apb0"
+# see atheros/uart_cpu_ar71xx.c why +3
+hint.uart.0.maddr=0x18020003
+hint.uart.0.msize=0x18
+hint.uart.0.irq=3
+
+#ehci - note the 0x100 offset for the AR913x/AR724x
+hint.ehci.0.at="nexus0"
+hint.ehci.0.maddr=0x1b000100
+hint.ehci.0.msize=0x00ffff00
+hint.ehci.0.irq=1
+
+# pci
+hint.pcib.0.at="nexus0"
+hint.pcib.0.irq=0
+
+# arge0
+hint.arge.0.at="nexus0"
+hint.arge.0.maddr=0x19000000
+hint.arge.0.msize=0x1000
+hint.arge.0.irq=2
+
+# AR8316 workaround for now
+hint.arge.0.media=1000
+hint.arge.0.fduplex=1
+hint.arge.0.phymask=0x3
+
+# GPIO
+hint.gpio.0.at="apb0"
+hint.gpio.0.maddr=0x18040000
+hint.gpio.0.msize=0x1000
+hint.gpio.0.irq=2
+
+# Signal leds
+hint.gpioled.0.at="gpiobus0"
+hint.gpioled.0.name="sig1"
+hint.gpioled.0.pins=0x0001 # pin 0
+hint.gpioled.1.at="gpiobus0"
+hint.gpioled.1.name="sig2"
+hint.gpioled.1.pins=0x0002 # pin 1
+hint.gpioled.2.at="gpiobus0"
+hint.gpioled.2.name="sig3"
+hint.gpioled.2.pins=0x0800 # pin 11
+hint.gpioled.3.at="gpiobus0"
+hint.gpioled.3.name="sig4"
+hint.gpioled.3.pins=0x0080 # pin 7
+
+# SPI controller/bus
+hint.spi.0.at="nexus0"
+hint.spi.0.maddr=0x1f000000
+hint.spi.0.msize=0x10
+
+# SPI flash
+hint.mx25l.0.at="spibus0"
+hint.mx25l.0.cs=0
+
+# Watchdog
+hint.ar71xx_wdog.0.at="nexus0"
+
+# nvram mapping - XXX ?
+hint.nvram.0.base=0x1f030000
+hint.nvram.0.maxsize=0x2000
+hint.nvram.0.flags=3 # 1 = No check, 2 = Format Generic
+hint.nvram.1.base=0x1f032000
+hint.nvram.1.maxsize=0x4000
+hint.nvram.1.flags=3 # 1 = No check, 2 = Format Generic
+
+# GEOM_MAP
+#
+# From my PB92 environment:
+#
+# mtdparts=ar7240-nor0:256k(u-boot),64k(u-boot-env),2752k(rootfs),896k(uImage),64k(NVRAM),64k(ART)
+
+hint.map.0.at="flash/spi0"
+hint.map.0.start=0x00000000
+hint.map.0.end=0x00040000 # 256k u-boot
+hint.map.0.name="u-boot"
+hint.map.0.readonly=1
+
+hint.map.1.at="flash/spi0"
+hint.map.1.start=0x00040000
+hint.map.1.end=0x00050000 # 64k u-boot-env
+hint.map.1.name="u-boot-env"
+hint.map.1.readonly=0
+
+hint.map.2.at="flash/spi0"
+hint.map.2.start=0x00050000
+hint.map.2.end=0x00300000 # 2752k rootfs
+hint.map.2.name="rootfs"
+hint.map.2.readonly=1
+
+hint.map.3.at="flash/spi0"
+hint.map.3.start=0x00300000
+hint.map.3.end=0x003e0000 # 896k uImage
+hint.map.3.name="uImage"
+hint.map.3.readonly=0
+
+hint.map.4.at="flash/spi0"
+hint.map.4.start=0x003e0000
+hint.map.4.end=0x003f0000 # 64k NVRAM
+hint.map.4.name="NVRAM"
+hint.map.4.readonly=0
+
+hint.map.5.at="flash/spi0"
+hint.map.5.start=0x003f0000
+hint.map.5.end=0x00400000 # 64k ART
+hint.map.5.name="ART"
+hint.map.5.readonly=1
Property changes on: trunk/sys/mips/conf/PB92.hints
___________________________________________________________________
Added: mnbsd:nokeywords
## -0,0 +1 ##
+MidnightBSD=%H
\ No newline at end of property
Added: trunk/sys/mips/conf/PICOSTATION_M2HP
===================================================================
--- trunk/sys/mips/conf/PICOSTATION_M2HP (rev 0)
+++ trunk/sys/mips/conf/PICOSTATION_M2HP 2018-05-26 21:55:02 UTC (rev 9987)
@@ -0,0 +1,68 @@
+#
+# Specific board setup for the Picostation M2 HP board.
+#
+# This board has the following hardware:
+#
+# + AR7241 CPU SoC
+# + AR9287 Wifi
+# + Integrated switch (XXX speed?)
+# + 8MB flash
+# + 32MB RAM
+# + uboot environment
+
+# $FreeBSD: stable/10/sys/mips/conf/PICOSTATION_M2HP 266331 2014-05-17 17:34:37Z ian $
+
+include "AR724X_BASE"
+ident "PICOSTATION_M2HP"
+hints "PICOSTATION_M2HP.hints"
+
+options AR71XX_REALMEM=32*1024*1024
+
+options AR71XX_ENV_UBOOT
+
+# Limit inlines
+makeoptions INLINE_LIMIT=768
+
+# We bite the performance overhead for now; the kernel won't
+# fit if the mutexes are inlined.
+options MUTEX_NOINLINE
+options RWLOCK_NOINLINE
+options SX_NOINLINE
+
+# There's no need to enable swapping on this platform.
+options NO_SWAPPING
+
+# For DOS - enable if required
+# options MSDOSFS
+
+# uncompress - to boot read-only lzma natively from flash
+device geom_uncompress
+options GEOM_UNCOMPRESS
+options ROOTDEVNAME=\"ufs:/dev/map/rootfs.uncompress\"
+
+# Not enough space for these..
+nooptions INVARIANTS
+nooptions INVARIANT_SUPPORT
+nooptions WITNESS
+nooptions WITNESS_SKIPSPIN
+nooptions DEBUG_REDZONE
+nooptions DEBUG_MEMGUARD
+
+# Used for the static uboot partition map
+device geom_map
+
+# Options needed for the EEPROM based calibration/PCI configuration data.
+options AR71XX_ATH_EEPROM # Fetch EEPROM/PCI config from flash
+options ATH_EEPROM_FIRMWARE # Use EEPROM from flash
+device firmware # Used by the above
+
+# Options required for miiproxy and mdiobus
+options ARGE_MDIO # Export an MDIO bus separate from arge
+device miiproxy # MDIO bus <-> MII PHY rendezvous
+
+device etherswitch
+device arswitch
+
+# Enable GPIO
+device gpio
+device gpioled
Property changes on: trunk/sys/mips/conf/PICOSTATION_M2HP
___________________________________________________________________
Added: mnbsd:nokeywords
## -0,0 +1 ##
+MidnightBSD=%H
\ No newline at end of property
Added: trunk/sys/mips/conf/PICOSTATION_M2HP.hints
===================================================================
--- trunk/sys/mips/conf/PICOSTATION_M2HP.hints (rev 0)
+++ trunk/sys/mips/conf/PICOSTATION_M2HP.hints 2018-05-26 21:55:02 UTC (rev 9987)
@@ -0,0 +1,103 @@
+# $FreeBSD: stable/10/sys/mips/conf/PICOSTATION_M2HP.hints 276716 2015-01-05 19:54:40Z hiren $
+
+# arge1 MDIO bus
+hint.argemdio.0.at="nexus0"
+hint.argemdio.0.maddr=0x1a000000
+hint.argemdio.0.msize=0x1000
+hint.argemdio.0.order=0
+
+# Override MAC Address with the one on EEPROM
+hint.arge.0.eeprommac=0x1fff0000
+
+# arge0: dedicated switch port; RMII; dedicated PHY 4 on switch, connected
+# via internal switch MDIO bus.
+hint.arge.0.media=100 # Map to 100/full
+hint.arge.0.fduplex=1 #
+hint.arge.0.phymask=0x10 # PHY4
+hint.arge.0.mdio=mdioproxy1 # .. off of the switch mdiobus
+
+# arge1: nail to 1000/full, RMII - connected to the switch
+hint.arge.1.media=1000 # Map to 1000/full
+hint.arge.1.fduplex=1 #
+hint.arge.1.phymask=0x0 # no directly mapped PHYs
+
+#
+# AR7240 switch config
+#
+hint.arswitch.0.at="mdio0"
+hint.arswitch.0.is_7240=1 # We need to be explicitly told this
+hint.arswitch.0.numphys=4 # 4 active switch PHYs (PHY 0 -> 3)
+hint.arswitch.0.phy4cpu=1 # Yes, PHY 4 == dedicated PHY
+hint.arswitch.0.is_rgmii=0 # No, not RGMII
+hint.arswitch.0.is_gmii=0 # No, not GMII
+
+# ath0 hint - pcie slot 0
+hint.pcib.0.bus.0.0.0.ath_fixup_addr=0x1fff1000
+hint.pcib.0.bus.0.0.0.ath_fixup_size=4096
+
+# ath
+hint.ath.0.eeprom_firmware="pcib.0.bus.0.0.0.eeprom_firmware"
+
+# GPIO pins
+# Pin 0: red led (sig1)
+# Pin 1: yellow led (sig2)
+# Pin 11: green len (sig3)
+# Pin 7: green len (sig4)
+# Pin 12: Reset switch
+hint.gpio.0.pinmask=0x1883
+
+# Signal leds
+hint.gpioled.0.at="gpiobus0"
+hint.gpioled.0.name="sig1"
+hint.gpioled.0.pins=0x0001 # pin 0
+hint.gpioled.1.at="gpiobus0"
+hint.gpioled.1.name="sig2"
+hint.gpioled.1.pins=0x0002 # pin 1
+hint.gpioled.2.at="gpiobus0"
+hint.gpioled.2.name="sig3"
+hint.gpioled.2.pins=0x0800 # pin 11
+hint.gpioled.3.at="gpiobus0"
+hint.gpioled.3.name="sig4"
+hint.gpioled.3.pins=0x0080 # pin 7
+
+# GEOM_MAP
+#
+# Picostation M2 HP
+#
+# mtdparts=ar7240-nor0:256k(u-boot),64k(u-boot-env),1024k(kernel),6528k(rootfs),256k(cfg),64k(EEPROM)
+
+hint.map.0.at="flash/spi0"
+hint.map.0.start=0x00000000
+hint.map.0.end=0x00040000 # 256k u-boot
+hint.map.0.name="u-boot"
+hint.map.0.readonly=1
+
+hint.map.1.at="flash/spi0"
+hint.map.1.start=0x00040000
+hint.map.1.end=0x00050000 # 64k u-boot-env
+hint.map.1.name="u-boot-env"
+hint.map.1.readonly=1
+
+hint.map.2.at="flash/spi0"
+hint.map.2.start=0x00050000
+hint.map.2.end="search:0x00100000:0x10000:.!/bin/sh"
+hint.map.2.name="kernel"
+hint.map.2.readonly=1
+
+hint.map.3.at="flash/spi0"
+hint.map.3.start="search:0x00100000:0x10000:.!/bin/sh"
+hint.map.3.end=0x007b0000
+hint.map.3.name="rootfs"
+hint.map.3.readonly=0
+
+hint.map.4.at="flash/spi0"
+hint.map.4.start=0x007b0000
+hint.map.4.end=0x007f0000 # 256k cfg
+hint.map.4.name="cfg"
+hint.map.4.readonly=0
+
+hint.map.5.at="flash/spi0"
+hint.map.5.start=0x007f0000
+hint.map.5.end=0x00800000 # 64k EEPROM
+hint.map.5.name="eeprom"
+hint.map.5.readonly=1
Property changes on: trunk/sys/mips/conf/PICOSTATION_M2HP.hints
___________________________________________________________________
Added: mnbsd:nokeywords
## -0,0 +1 ##
+MidnightBSD=%H
\ No newline at end of property
Added: trunk/sys/mips/conf/QEMU
===================================================================
--- trunk/sys/mips/conf/QEMU (rev 0)
+++ trunk/sys/mips/conf/QEMU 2018-05-26 21:55:02 UTC (rev 9987)
@@ -0,0 +1,49 @@
+# QEMU -- Generic kernel configuration file for FreeBSD/mips
+#
+# For more information on this file, please read the handbook section on
+# Kernel Configuration Files:
+#
+# http://www.FreeBSD.org/doc/en_US.ISO8859-1/books/handbook/kernelconfig-config.html
+#
+# The handbook is also available locally in /usr/share/doc/handbook
+# if you've installed the doc distribution, otherwise always see the
+# FreeBSD World Wide Web server (http://www.FreeBSD.org/) for the
+# latest information.
+#
+# An exhaustive list of options and more detailed explanations of the
+# device lines is also present in the ../../conf/NOTES and NOTES files.
+# If you are in doubt as to the purpose or necessity of a line, check first
+# in NOTES.
+#
+# $FreeBSD: stable/10/sys/mips/conf/QEMU 221753 2011-05-11 00:52:41Z gonzo $
+
+cpu CPU_MIPS32
+ident QEMU
+
+# Don't build any modules yet.
+makeoptions MODULES_OVERRIDE=""
+
+include "../adm5120/std.adm5120"
+
+makeoptions DEBUG=-g #Build kernel with gdb(1) debug symbols
+
+options DDB
+options KDB
+
+options SCHED_4BSD #4BSD scheduler
+options INET #InterNETworking
+options NFSCL #Network Filesystem Client
+options NFS_ROOT #NFS usable as /, requires NFSCL
+options PSEUDOFS #Pseudo-filesystem framework
+options _KPOSIX_PRIORITY_SCHEDULING #Posix P1003_1B real-time extensions
+
+# Debugging for use in -current
+#options DEADLKRES #Enable the deadlock resolver
+#options INVARIANTS #Enable calls of extra sanity checking
+#options INVARIANT_SUPPORT #Extra sanity checks of internal structures, required by INVARIANTS
+#options WITNESS #Enable checks to detect deadlocks and cycles
+#options WITNESS_SKIPSPIN #Don't run witness on spinlocks for speed
+
+device loop
+device ether
+device md
Property changes on: trunk/sys/mips/conf/QEMU
___________________________________________________________________
Added: mnbsd:nokeywords
## -0,0 +1 ##
+MidnightBSD=%H
\ No newline at end of property
Added: trunk/sys/mips/conf/ROUTERSTATION
===================================================================
--- trunk/sys/mips/conf/ROUTERSTATION (rev 0)
+++ trunk/sys/mips/conf/ROUTERSTATION 2018-05-26 21:55:02 UTC (rev 9987)
@@ -0,0 +1,28 @@
+#
+# Ubiquiti Routerstation: Boot from onboard flash
+#
+# $FreeBSD: stable/10/sys/mips/conf/ROUTERSTATION 266331 2014-05-17 17:34:37Z ian $
+#
+
+include "AR71XX_BASE"
+ident "ROUTERSTATION"
+hints "ROUTERSTATION.hints"
+
+# XXX Is there an RTC on the RS?
+
+# GEOM modules
+device geom_redboot # to get access to the SPI flash partitions
+device geom_uzip # compressed in-memory filesystem support
+options GEOM_UZIP
+
+# For DOS
+options MSDOSFS
+
+# Etherswitch support
+options ARGE_MDIO
+device miiproxy
+device etherswitch
+device ukswitch
+
+# Boot path - redboot MFS
+options ROOTDEVNAME=\"ufs:redboot/rootfs.uzip\"
Property changes on: trunk/sys/mips/conf/ROUTERSTATION
___________________________________________________________________
Added: mnbsd:nokeywords
## -0,0 +1 ##
+MidnightBSD=%H
\ No newline at end of property
Added: trunk/sys/mips/conf/ROUTERSTATION.hints
===================================================================
--- trunk/sys/mips/conf/ROUTERSTATION.hints (rev 0)
+++ trunk/sys/mips/conf/ROUTERSTATION.hints 2018-05-26 21:55:02 UTC (rev 9987)
@@ -0,0 +1,48 @@
+#
+# $FreeBSD: stable/10/sys/mips/conf/ROUTERSTATION.hints 254989 2013-08-28 14:43:04Z loos $
+#
+
+# arge0 mdio bus
+hint.argemdio.0.at="nexus0"
+hint.argemdio.0.maddr=0x19000000
+hint.argemdio.0.msize=0x1000
+hint.argemdio.0.order=0
+
+# Uncomment this hint for RS (not PRO)
+# PHY20 = 1 << 20
+hint.arge.0.phymask=0x100000
+hint.arge.0.mdio=mdioproxy1 # .. off of the switch mdiobus
+
+# should be 100 for RS
+hint.arge.1.media=100
+hint.arge.1.fduplex=1
+hint.arge.1.phymask=0x0
+hint.arge.1.mdio=mdioproxy1 # .. off of the switch mdiobus
+
+# ukswitch
+hint.ukswitch.0.at="mdio0"
+hint.ukswitch.0.phymask=0x30000
+
+# Don't flip on anything that isn't already enabled.
+# This includes leaving the SPI CS1/CS2 pins as GPIO pins as they're
+# not used here.
+hint.gpio.0.function_set=0x00000000
+hint.gpio.0.function_clear=0x00000000
+
+# These are the GPIO LEDs and buttons which can be software controlled.
+hint.gpio.0.pinmask=0x000000ff
+
+# GPIO 0: Pin 1
+# GPIO 1: Pin 2
+# GPIO 2: RF LED
+# GPIO 3: Pin 3
+# GPIO 4: Pin 4
+# GPIO 5: Pin 5
+# GPIO 6: Pin 6
+# GPIO 7: Pin 7
+
+# RF led
+hint.gpioled.0.at="gpiobus0"
+hint.gpioled.0.name="rf"
+# pin 2
+hint.gpioled.0.pins=0x0004
Property changes on: trunk/sys/mips/conf/ROUTERSTATION.hints
___________________________________________________________________
Added: mnbsd:nokeywords
## -0,0 +1 ##
+MidnightBSD=%H
\ No newline at end of property
Added: trunk/sys/mips/conf/ROUTERSTATION_MFS
===================================================================
--- trunk/sys/mips/conf/ROUTERSTATION_MFS (rev 0)
+++ trunk/sys/mips/conf/ROUTERSTATION_MFS 2018-05-26 21:55:02 UTC (rev 9987)
@@ -0,0 +1,19 @@
+#
+# Ubiquiti Routerstation: boot from MFS
+#
+# $FreeBSD: stable/10/sys/mips/conf/ROUTERSTATION_MFS 266331 2014-05-17 17:34:37Z ian $
+#
+
+include "AR71XX_BASE"
+ident "ROUTERSTATION_MFS"
+hints "ROUTERSTATION.hints"
+
+# GEOM modules
+device geom_redboot # to get access to the SPI flash partitions
+device geom_uzip # compressed in-memory filesystem hackery!
+options GEOM_UZIP
+
+options ROOTDEVNAME=\"ufs:md0.uzip\"
+
+options MD_ROOT
+options MD_ROOT_SIZE="6144"
Property changes on: trunk/sys/mips/conf/ROUTERSTATION_MFS
___________________________________________________________________
Added: mnbsd:nokeywords
## -0,0 +1 ##
+MidnightBSD=%H
\ No newline at end of property
Added: trunk/sys/mips/conf/RSPRO
===================================================================
--- trunk/sys/mips/conf/RSPRO (rev 0)
+++ trunk/sys/mips/conf/RSPRO 2018-05-26 21:55:02 UTC (rev 9987)
@@ -0,0 +1,30 @@
+#
+# Routerstation Pro: boot from on-board flash
+#
+# $FreeBSD: stable/10/sys/mips/conf/RSPRO 266331 2014-05-17 17:34:37Z ian $
+#
+
+include "AR71XX_BASE"
+ident "RSPRO"
+hints "RSPRO.hints"
+
+# RTC - requires hackery in the spibus code to work
+device pcf2123_rtc
+
+# GEOM modules
+device geom_redboot # to get access to the SPI flash partitions
+device geom_uzip # compressed in-memory filesystem support
+options GEOM_UZIP
+
+# For DOS
+options MSDOSFS
+
+# For etherswitch support
+options ARGE_MDIO
+device miiproxy
+device etherswitch
+device arswitch
+
+# Boot off of flash
+options ROOTDEVNAME=\"ufs:redboot/rootfs.uzip\"
+
Property changes on: trunk/sys/mips/conf/RSPRO
___________________________________________________________________
Added: mnbsd:nokeywords
## -0,0 +1 ##
+MidnightBSD=%H
\ No newline at end of property
Added: trunk/sys/mips/conf/RSPRO.hints
===================================================================
--- trunk/sys/mips/conf/RSPRO.hints (rev 0)
+++ trunk/sys/mips/conf/RSPRO.hints 2018-05-26 21:55:02 UTC (rev 9987)
@@ -0,0 +1,49 @@
+# $FreeBSD: stable/10/sys/mips/conf/RSPRO.hints 242718 2012-11-07 22:46:30Z ray $
+
+# arge0 mdio bus
+hint.argemdio.0.at="nexus0"
+hint.argemdio.0.maddr=0x19000000
+hint.argemdio.0.msize=0x1000
+hint.argemdio.0.order=0
+
+# arge0: dedicated switch port
+hint.arge.0.phymask=0x10 # PHY4
+hint.arge.0.miimode=3 # RGMII
+hint.arge.0.mdio=mdioproxy1 # .. off of the switch mdiobus
+
+# arge1: nail to 1000/full, RGMII - connected to the switch
+hint.arge.1.media=1000 # Map to 1000/full
+hint.arge.1.fduplex=1 #
+hint.arge.1.phymask=0x0 # no directly mapped PHYs
+hint.arge.1.miimode=3 # RGMII
+
+hint.arswitch.0.at="mdio0"
+hint.arswitch.0.is_7240=0
+hint.arswitch.0.numphys=4
+hint.arswitch.0.phy4cpu=1
+hint.arswitch.0.is_rgmii=1
+hint.arswitch.0.is_gmii=0
+
+# Don't flip on anything that isn't already enabled.
+# This includes leaving the SPI CS1/CS2 pins as GPIO pins as they're
+# not used here.
+hint.gpio.0.function_set=0x00000000
+hint.gpio.0.function_clear=0x00000000
+
+# These are the GPIO LEDs and buttons which can be software controlled.
+hint.gpio.0.pinmask=0x000000ff
+
+# GPIO 0: Pin 1
+# GPIO 1: Pin 2
+# GPIO 2: RF LED
+# GPIO 3: Pin 3
+# GPIO 4: Pin 4
+# GPIO 5: Pin 5
+# GPIO 6: Pin 6
+# GPIO 7: Pin 7
+
+# RF led
+hint.gpioled.0.at="gpiobus0"
+hint.gpioled.0.name="rf"
+# pin 2
+hint.gpioled.0.pins=0x0004
Property changes on: trunk/sys/mips/conf/RSPRO.hints
___________________________________________________________________
Added: mnbsd:nokeywords
## -0,0 +1 ##
+MidnightBSD=%H
\ No newline at end of property
Added: trunk/sys/mips/conf/RSPRO_MFS
===================================================================
--- trunk/sys/mips/conf/RSPRO_MFS (rev 0)
+++ trunk/sys/mips/conf/RSPRO_MFS 2018-05-26 21:55:02 UTC (rev 9987)
@@ -0,0 +1,23 @@
+#
+# Ubiquiti Routerstation Pro: boot from MFS
+#
+# $FreeBSD: stable/10/sys/mips/conf/RSPRO_MFS 266331 2014-05-17 17:34:37Z ian $
+#
+
+include "AR71XX_BASE"
+ident "RSPRO_MFS"
+hints "RSPRO.hints"
+
+# RTC - requires hackery in the spibus code to work
+device pcf2123_rtc
+
+# GEOM modules
+device geom_redboot # to get access to the SPI flash partitions
+device geom_uzip # compressed in-memory filesystem hackery!
+options GEOM_UZIP
+
+# Boot from the first MFS uzip
+options ROOTDEVNAME=\"ufs:md0.uzip\"
+
+options MD_ROOT
+options MD_ROOT_SIZE="6144"
Property changes on: trunk/sys/mips/conf/RSPRO_MFS
___________________________________________________________________
Added: mnbsd:nokeywords
## -0,0 +1 ##
+MidnightBSD=%H
\ No newline at end of property
Added: trunk/sys/mips/conf/RSPRO_STANDALONE
===================================================================
--- trunk/sys/mips/conf/RSPRO_STANDALONE (rev 0)
+++ trunk/sys/mips/conf/RSPRO_STANDALONE 2018-05-26 21:55:02 UTC (rev 9987)
@@ -0,0 +1,24 @@
+#
+# Ubiquiti Routerstation Pro: boot from first DOS-partitioned, BSD
+# sliced flash disk.
+#
+# $FreeBSD: stable/10/sys/mips/conf/RSPRO_STANDALONE 266331 2014-05-17 17:34:37Z ian $
+#
+
+include "AR71XX_BASE"
+ident "RSPRO_STANDALONE"
+hints "RSPRO.hints"
+
+# RTC - requires hackery in the spibus code to work
+device pcf2123_rtc
+
+# GEOM modules
+device geom_redboot # to get access to the SPI flash partitions
+device geom_uzip # compressed in-memory filesystem support
+options GEOM_UZIP
+
+# For DOS
+options MSDOSFS
+
+# .. first DOS-partitioned, BSD sliced flash disk
+options ROOTDEVNAME=\"ufs:da0s1a\"
Property changes on: trunk/sys/mips/conf/RSPRO_STANDALONE
___________________________________________________________________
Added: mnbsd:nokeywords
## -0,0 +1 ##
+MidnightBSD=%H
\ No newline at end of property
Added: trunk/sys/mips/conf/RT305X
===================================================================
--- trunk/sys/mips/conf/RT305X (rev 0)
+++ trunk/sys/mips/conf/RT305X 2018-05-26 21:55:02 UTC (rev 9987)
@@ -0,0 +1,132 @@
+# RT305X -- Kernel configuration file for FreeBSD/mips for Ralink RT305xF systems
+#
+# For more information on this file, please read the handbook section on
+# Kernel Configuration Files:
+#
+# http://www.FreeBSD.org/doc/en_US.ISO8859-1/books/handbook/kernelconfig-config.html
+#
+# The handbook is also available locally in /usr/share/doc/handbook
+# if you've installed the doc distribution, otherwise always see the
+# FreeBSD World Wide Web server (http://www.FreeBSD.org/) for the
+# latest information.
+#
+# An exhaustive list of options and more detailed explanations of the
+# device lines is also present in the ../../conf/NOTES and NOTES files.
+# If you are in doubt as to the purpose or necessity of a line, check first
+# in NOTES.
+#
+# $FreeBSD: stable/10/sys/mips/conf/RT305X 266331 2014-05-17 17:34:37Z ian $
+
+ident RT305X
+
+machine mips mipsel
+makeoptions MIPS_LITTLE_ENDIAN=defined
+makeoptions KERNLOADADDR=0x80001000
+
+# Don't build any modules yet.
+makeoptions MODULES_OVERRIDE="wlan_xauth wlan_wep wlan_tkip wlan_acl wlan_amrr wlan_ccmp wlan_rssadapt random if_bridge bridgestp msdosfs md ipfw dummynet libalias geom/geom_label ufs usb/uplcom usb/u3g usb/umodem usb/umass usb/ucom cam zlib"
+makeoptions RT3052F
+
+include "../rt305x/std.rt305x"
+
+hints "RT305X.hints" #Default places to look for devices.
+
+#makeoptions DEBUG=-g #Build kernel with gdb(1) debug symbols
+
+# Debugging for use in -current
+#options DEADLKRES #Enable the deadlock resolver
+#options INVARIANTS #Enable calls of extra sanity checking
+#options INVARIANT_SUPPORT #Extra sanity checks of internal structures, required by INVARIANTS
+#options WITNESS #Enable checks to detect deadlocks and cycles
+#options WITNESS_SKIPSPIN #Don't run witness on spinlocks for speed
+#options DIAGNOSTIC
+#options DEBUG_LOCKS
+#options DEBUG_VFS_LOCKS
+#options GDB
+options DDB
+options KDB
+
+options SCHED_ULE
+#options SCHED_4BSD #4BSD scheduler
+#options COMPAT_43
+options INET #InterNETworking
+options NFSCL #Network Filesystem Client
+options NFS_ROOT #NFS usable as /, requires NFSCL
+options PSEUDOFS #Pseudo-filesystem framework
+#options _KPOSIX_PRIORITY_SCHEDULING #Posix P1003_1B real-time extensions
+
+options BOOTP
+#options BOOTP_NFSROOT
+options BOOTP_NFSV3
+options BOOTP_WIRED_TO=rt0
+options BOOTP_COMPAT
+options CD9660 # ISO 9660 Filesystem
+options ROOTDEVNAME=\"cd9660:/dev/map/rootfs.uncompress\"
+options TMPFS # TMP Memory Filesystem
+
+#options FFS #Berkeley Fast Filesystem
+#options SOFTUPDATES #Enable FFS soft updates support
+#options UFS_ACL #Support for access control lists
+#options UFS_DIRHASH #Improve performance on big directories
+#options ROOTDEVNAME=\"nfs:10.0.0.1:/mnt/bsd\"
+
+# Options for making kernel less hangry
+makeoptions INLINE_LIMIT=1024
+options MAXUSERS=3
+options MAXFILES=512
+options NSFBUFS=256
+options SHMALL=128
+options MSGBUF_SIZE=65536
+
+# Options for making kernel smallest
+options NO_SYSCTL_DESCR # No description string of sysctl
+#options NO_FFS_SNAPSHOT # Disable Snapshot supporting
+options SCSI_NO_SENSE_STRINGS
+options SCSI_NO_OP_STRINGS
+options RWLOCK_NOINLINE
+options SX_NOINLINE
+options NO_SWAPPING
+options MROUTING # Multicast routing
+options IPFIREWALL_DEFAULT_TO_ACCEPT
+
+device random
+device loop
+# RT3050F, RT3052F have only pseudo PHYs, so mii not required
+device rt
+
+device ether
+device bpf # Berkeley packet filter
+device vlan
+#device lagg
+#device if_bridge
+device uart
+nodevice uart_ns8250
+device tun # Packet tunnel.
+
+device wlan
+
+
+device gpio
+device gpioled
+
+device cfi # Detect Flash memmory
+device cfid
+
+device nvram2env
+
+device usb
+#device dotg # DWC like USB OTG Controller driver
+#device u3g
+#device umodem
+#device uplcom
+#device umass
+#device da
+#device pass
+#device scbus
+options SCSI_DELAY=1000 # Delay (in ms) before probing SCSI
+
+#options USB_EHCI_BIG_ENDIAN_DESC # handle big-endian byte order
+#options USB_DEBUG
+#options USB_REQ_DEBUG
+
+
Property changes on: trunk/sys/mips/conf/RT305X
___________________________________________________________________
Added: mnbsd:nokeywords
## -0,0 +1 ##
+MidnightBSD=%H
\ No newline at end of property
Added: trunk/sys/mips/conf/RT305X.hints
===================================================================
--- trunk/sys/mips/conf/RT305X.hints (rev 0)
+++ trunk/sys/mips/conf/RT305X.hints 2018-05-26 21:55:02 UTC (rev 9987)
@@ -0,0 +1,137 @@
+# $FreeBSD: stable/10/sys/mips/conf/RT305X.hints 224009 2011-07-14 11:53:23Z ray $
+# device.hints
+hint.obio.0.at="nexus0"
+hint.obio.0.maddr=0x10000000
+hint.obio.0.msize=0x10000000
+
+hint.nvram.0.sig=0xe5e60a74
+hint.nvram.0.base=0x1f030000
+hint.nvram.0.maxsize=0x2000
+hint.nvram.0.flags=3 # 1 = No check, 2 = Format Generic
+hint.nvram.1.sig=0x5a045e94
+hint.nvram.1.base=0x1f032000
+hint.nvram.1.maxsize=0x4000
+hint.nvram.1.flags=3 # 1 = No check, 2 = Format Generic
+
+# on-board Ralink Frame Engine
+hint.rt.0.at="nexus0"
+hint.rt.0.maddr=0x10100000
+hint.rt.0.msize=0x10000
+hint.rt.0.irq=3
+# macaddr can be statically set
+#hint.rt.0.macaddr="xx:xx:xx:xx:xx:xx"
+
+# on-board Ralink 2872 802.11n core
+hint.rt2860.0.at="nexus0"
+hint.rt2860.0.maddr=0x10180000
+hint.rt2860.0.msize=0x40000
+hint.rt2860.0.irq=4
+
+# uart0
+#hint.uart.0.at="obio0"
+#hint.uart.0.maddr=0x10000C00
+#hint.uart.0.msize=0x100
+#hint.uart.0.irq=12
+#hint.uart.0.flags="0x30"
+
+# uart1
+#hint.uart.1.at="obio0"
+#hint.uart.1.maddr=0x10000500
+#hint.uart.1.msize=0x100
+#hint.uart.1.irq=5
+#hint.uart.1.flags="0x30"
+
+
+# gpio
+# GPIO0 - WPS BTN IN II IO
+hint.gpiobutton.0.at="gpiobus0"
+hint.gpiobutton.0.pins="0x01"
+hint.gpiobutton.0.name="wps"
+hint.gpiobutton.0.flags="0x0581"
+
+# GPIO7 - MODE SW AP IN II IO
+hint.gpiobutton.1.at="gpiobus0"
+hint.gpiobutton.1.pins="0x80"
+hint.gpiobutton.1.name="mode_ap"
+hint.gpiobutton.1.flags="0x0581"
+
+# GPIO8 - ST LEDRED OUT /* 2pin BiDir RED/BLUE LED */
+# GPIO9 - ST LEDBLUE OUT
+hint.gpioled.0.at="gpiobus0"
+hint.gpioled.0.pins="0x100"
+hint.gpioled.0.name="status_red"
+hint.gpioled.0.flags="0x0002"
+hint.gpioled.1.at="gpiobus0"
+hint.gpioled.1.pins="0x200"
+#hint.gpioled.1.name="status_blue"
+hint.gpioled.1.name="status"
+hint.gpioled.1.flags="0x0002"
+
+# GPIO10 - RST BTN IN II IO
+hint.gpiobutton.2.at="gpiobus0"
+hint.gpiobutton.2.pins="0x400"
+hint.gpiobutton.2.name="reset"
+hint.gpiobutton.2.flags="0x0581"
+
+# GPIO11 - MODE SW CL IN II IO
+hint.gpiobutton.3.at="gpiobus0"
+hint.gpiobutton.3.pins="0x800"
+hint.gpiobutton.3.name="mode_wlan_client"
+hint.gpiobutton.3.flags="0x0581"
+
+# GPIO14 - WPS LED OUT II IO
+hint.gpioled.2.at="gpiobus0"
+hint.gpioled.2.pins="0x4000"
+hint.gpioled.2.name="wps"
+hint.gpioled.2.flags="0x0182"
+
+
+
+#0x00000000-0x00030000 : "Bootloader"
+#0x00030000-0x00040000 : "Factory"
+#0x00040000-0x00070000 : "Config"
+#0x00070000-0x000b0000 : "Language"
+#0x000b0000-0x001a0000 : "Kernel"
+#0x001a0000-0x01000000 : "RootFS"
+
+hint.map.0.at="cfid0"
+hint.map.0.start=0x00000000
+hint.map.0.end=0x00030000
+hint.map.0.name="bootloader"
+hint.map.0.readonly=1
+
+hint.map.1.at="cfid0"
+hint.map.1.start=0x00030000
+hint.map.1.end=0x00040000
+hint.map.1.name="factory"
+
+hint.map.2.at="cfid0"
+hint.map.2.start=0x00040000
+hint.map.2.end=0x00800000
+hint.map.2.name="upgrade"
+
+hint.map.3.at="cfid0"
+hint.map.3.start=0x00040000
+hint.map.3.end=0x00050000
+hint.map.3.name="config"
+
+hint.map.4.at="cfid0"
+hint.map.4.start=0x00000000
+hint.map.4.end=0x00000000
+hint.map.4.name="language"
+
+hint.map.5.at="cfid0"
+hint.map.5.start=0x00050000
+hint.map.5.end=0x00150000
+hint.map.5.name="kernel"
+
+hint.map.6.at="cfid0"
+hint.map.6.start=0x00150000
+hint.map.6.end=0x00800000
+hint.map.6.name="rootfs"
+
+
+hint.rt.0.phymask=0x1f
+hint.rt.0.media=100
+hint.rt.0.fduplex=1
+
Property changes on: trunk/sys/mips/conf/RT305X.hints
___________________________________________________________________
Added: mnbsd:nokeywords
## -0,0 +1 ##
+MidnightBSD=%H
\ No newline at end of property
Added: trunk/sys/mips/conf/SENTRY5
===================================================================
--- trunk/sys/mips/conf/SENTRY5 (rev 0)
+++ trunk/sys/mips/conf/SENTRY5 2018-05-26 21:55:02 UTC (rev 9987)
@@ -0,0 +1,86 @@
+#
+# $FreeBSD: stable/10/sys/mips/conf/SENTRY5 266331 2014-05-17 17:34:37Z ian $
+#
+# The Broadcom Sentry5 series of processors and boards is very commonly
+# used in COTS hardware including the Netgear WGT634U.
+#
+# Some tweaks are needed for use with this platform:
+#
+# * CFE firmware's ELF loader expects an ELF kernel which is linked so as
+# not to contain offsets in PT_LOAD which point behind the actual offset
+# of that PT header. FreeBSD normally links the first PT_LOAD header to
+# begin at offset 0.
+#
+# * Broadcom's support package for the internal bus, the Sonics
+# SiliconBackplane, needs to be integrated to detect and probe hardware
+# correctly.
+#
+# * The clock needs to be calibrated correctly, so that DELAY() may work.
+# One problem with this is that the low-level printf() routine calls DELAY(),
+# which currently causes divide-by-zero trap
+#
+# * The Broadcom CPUs have no FPU. Attempting to detect one by reading CP1's
+# status register causes an unhandled boot-time exception. An FPU emulator
+# will be necessary to support multi-user boot.
+#
+
+ident SENTRY5
+
+# XXX only siba should be hardwired for now; we will use
+# bus enumeration there
+hints "SENTRY5.hints"
+include "../sentry5/std.sentry5"
+
+# sentry5 normally ships with cfe firmware; use the console for now
+options CFE
+options CFE_CONSOLE
+options ALT_BREAK_TO_DEBUGGER
+
+makeoptions DEBUG=-g #Build kernel with gdb(1) debug symbols
+makeoptions MODULES_OVERRIDE=""
+
+options DDB
+options KDB
+
+options SCHED_4BSD #4BSD scheduler
+options INET #InterNETworking
+options NFSCL #Network Filesystem Client
+options NFS_ROOT #NFS usable as /, requires NFSCL
+options PSEUDOFS #Pseudo-filesystem framework
+options _KPOSIX_PRIORITY_SCHEDULING #Posix P1003_1B real-time extensions
+
+# Debugging for use in -current
+#options DEADLKRES
+options INVARIANTS
+options INVARIANT_SUPPORT
+
+#options BUS_DEBUG
+#makeoptions BUS_DEBUG
+
+device siba # Sonics SiliconBackplane
+device pci # siba_pcib
+
+# device bfe # XXX will build both pci and siba
+# device miibus # attachments
+
+# pci devices
+# notyet:
+#device ath # in pci slot
+#device ath_pci # Atheros pci/cardbus glue
+#device ath_hal # pci chip support
+#options AH_SUPPORT_AR5416 # enable AR5416 tx/rx descriptors
+
+options USB_DEBUG # enable debug msgs
+device usb # USB Bus (required)
+device uhci # UHCI PCI->USB interface
+device ehci # EHCI PCI->USB interface (USB 2.0)
+
+# need to teach the code to ignore the bridge....
+
+
+# XXX notyet; need to be auto probed children of siba_cc.
+#device uart
+
+device loop
+device ether
+device md
Property changes on: trunk/sys/mips/conf/SENTRY5
___________________________________________________________________
Added: mnbsd:nokeywords
## -0,0 +1 ##
+MidnightBSD=%H
\ No newline at end of property
Added: trunk/sys/mips/conf/SENTRY5.hints
===================================================================
--- trunk/sys/mips/conf/SENTRY5.hints (rev 0)
+++ trunk/sys/mips/conf/SENTRY5.hints 2018-05-26 21:55:02 UTC (rev 9987)
@@ -0,0 +1,5 @@
+# $FreeBSD: stable/10/sys/mips/conf/SENTRY5.hints 202175 2010-01-12 21:36:08Z imp $
+hint.siba.0.at="nexus0"
+hint.siba.0.maddr="0x18000000"
+hint.siba.0.msize="0x1000"
+# XXX irq?
Property changes on: trunk/sys/mips/conf/SENTRY5.hints
___________________________________________________________________
Added: mnbsd:nokeywords
## -0,0 +1 ##
+MidnightBSD=%H
\ No newline at end of property
Added: trunk/sys/mips/conf/SWARM
===================================================================
--- trunk/sys/mips/conf/SWARM (rev 0)
+++ trunk/sys/mips/conf/SWARM 2018-05-26 21:55:02 UTC (rev 9987)
@@ -0,0 +1,12 @@
+#
+# $FreeBSD: stable/10/sys/mips/conf/SWARM 233644 2012-03-29 02:54:35Z jmallett $
+#
+
+include "std.SWARM"
+
+ident SWARM
+
+machine mips mips
+
+makeoptions ARCH_FLAGS="-mabi=32 -march=mips32"
+makeoptions LDSCRIPT_NAME= ldscript.mips.cfe
Property changes on: trunk/sys/mips/conf/SWARM
___________________________________________________________________
Added: mnbsd:nokeywords
## -0,0 +1 ##
+MidnightBSD=%H
\ No newline at end of property
Added: trunk/sys/mips/conf/SWARM.hints
===================================================================
--- trunk/sys/mips/conf/SWARM.hints (rev 0)
+++ trunk/sys/mips/conf/SWARM.hints 2018-05-26 21:55:02 UTC (rev 9987)
@@ -0,0 +1,17 @@
+# $FreeBSD: stable/10/sys/mips/conf/SWARM.hints 202171 2010-01-12 20:52:41Z rpaulo $
+hint.zbbus.0.at="nexus0"
+hint.zbpci.0.at="zbbus0"
+hint.scd.0.at="zbbus0"
+
+#
+# SWARM IDE interface is on the generic bus at chip select 4.
+# The CS4 region is 64KB in size and starts at 0x100B0000.
+# The IDE interrupt is wired to GPIO4 (intsrc 36 to the interrupt mapper)
+#
+hint.ata.0.at="zbbus0"
+hint.ata.0.maddr=0x100B0000
+hint.ata.0.msize=0x10000
+hint.ata.0.irq=36
+#hint.ata.0.disabled=0
+#hint.ata.0.regoffset=0x1F0
+#hint.ata.0.regshift=5
Property changes on: trunk/sys/mips/conf/SWARM.hints
___________________________________________________________________
Added: mnbsd:nokeywords
## -0,0 +1 ##
+MidnightBSD=%H
\ No newline at end of property
Added: trunk/sys/mips/conf/SWARM64
===================================================================
--- trunk/sys/mips/conf/SWARM64 (rev 0)
+++ trunk/sys/mips/conf/SWARM64 2018-05-26 21:55:02 UTC (rev 9987)
@@ -0,0 +1,12 @@
+#
+# $FreeBSD: stable/10/sys/mips/conf/SWARM64 233644 2012-03-29 02:54:35Z jmallett $
+#
+
+include "std.SWARM"
+
+ident SWARM64
+
+machine mips mips64
+makeoptions ARCH_FLAGS="-mabi=64 -march=mips64"
+makeoptions LDSCRIPT_NAME=ldscript.mips.cfe
+makeoptions KERNLOADADDR=0xffffffff80001000
Property changes on: trunk/sys/mips/conf/SWARM64
___________________________________________________________________
Added: mnbsd:nokeywords
## -0,0 +1 ##
+MidnightBSD=%H
\ No newline at end of property
Added: trunk/sys/mips/conf/SWARM64_SMP
===================================================================
--- trunk/sys/mips/conf/SWARM64_SMP (rev 0)
+++ trunk/sys/mips/conf/SWARM64_SMP 2018-05-26 21:55:02 UTC (rev 9987)
@@ -0,0 +1,15 @@
+#
+# $FreeBSD: stable/10/sys/mips/conf/SWARM64_SMP 266331 2014-05-17 17:34:37Z ian $
+#
+
+include "std.SWARM"
+
+ident SWARM64_SMP
+
+options SMP
+options PRINTF_BUFR_SIZE=128
+
+machine mips mips64
+makeoptions ARCH_FLAGS="-mabi=64 -march=mips64"
+makeoptions LDSCRIPT_NAME=ldscript.mips.cfe
+makeoptions KERNLOADADDR=0xffffffff80001000
Property changes on: trunk/sys/mips/conf/SWARM64_SMP
___________________________________________________________________
Added: mnbsd:nokeywords
## -0,0 +1 ##
+MidnightBSD=%H
\ No newline at end of property
Added: trunk/sys/mips/conf/SWARM_SMP
===================================================================
--- trunk/sys/mips/conf/SWARM_SMP (rev 0)
+++ trunk/sys/mips/conf/SWARM_SMP 2018-05-26 21:55:02 UTC (rev 9987)
@@ -0,0 +1,15 @@
+#
+# $FreeBSD: stable/10/sys/mips/conf/SWARM_SMP 266331 2014-05-17 17:34:37Z ian $
+#
+
+include "std.SWARM"
+
+ident SWARM_SMP
+
+options SMP
+options PRINTF_BUFR_SIZE=128
+
+machine mips mips
+
+makeoptions ARCH_FLAGS="-mabi=32 -march=mips32"
+makeoptions LDSCRIPT_NAME= ldscript.mips.cfe
Property changes on: trunk/sys/mips/conf/SWARM_SMP
___________________________________________________________________
Added: mnbsd:nokeywords
## -0,0 +1 ##
+MidnightBSD=%H
\ No newline at end of property
Added: trunk/sys/mips/conf/TP-WN1043ND
===================================================================
--- trunk/sys/mips/conf/TP-WN1043ND (rev 0)
+++ trunk/sys/mips/conf/TP-WN1043ND 2018-05-26 21:55:02 UTC (rev 9987)
@@ -0,0 +1,59 @@
+#
+# TP-1043ND -- Kernel configuration file for the TP-Link WR-1043ND
+#
+# $FreeBSD: stable/10/sys/mips/conf/TP-WN1043ND 266331 2014-05-17 17:34:37Z ian $
+#
+
+# Include the default AR913x parameters common to all AR913x SoC users.
+include "AR91XX_BASE"
+
+ident TP-WN1043ND
+
+# Override hints with board values
+hints "TP-WN1043ND.hints"
+
+# Force the board memory - 32mb
+options AR71XX_REALMEM=32*1024*1024
+
+# i2c GPIO bus
+device gpioiic
+device iicbb
+device iicbus
+device iic
+
+# ethernet switch device
+device etherswitch
+
+# RTL8366RB support
+device rtl8366rb
+
+# read MSDOS formatted disks - USB
+options MSDOSFS
+
+# Enable the uboot environment stuff rather then the
+# redboot stuff.
+options AR71XX_ENV_UBOOT
+
+# uncompress - to boot natively from flash
+device geom_uncompress
+options GEOM_UNCOMPRESS
+
+# Used for the static uboot partition map
+device geom_map
+
+# Boot off of the rootfs, as defined in the geom_map setup.
+options ROOTDEVNAME=\"ufs:map/rootfs.uncompress\"
+
+# We bite the performance overhead for now; the kernel won't
+# fit if the mutexes are inlined.
+options MUTEX_NOINLINE
+options RWLOCK_NOINLINE
+options SX_NOINLINE
+
+# Remove everything we don't need. We need a _really_ small kernel!
+nooptions INVARIANTS
+nooptions INVARIANT_SUPPORT
+nooptions WITNESS
+nooptions WITNESS_SKIPSPIN
+nooptions DEBUG_REDZONE
+nooptions DEBUG_MEMGUARD
Property changes on: trunk/sys/mips/conf/TP-WN1043ND
___________________________________________________________________
Added: mnbsd:nokeywords
## -0,0 +1 ##
+MidnightBSD=%H
\ No newline at end of property
Added: trunk/sys/mips/conf/TP-WN1043ND.hints
===================================================================
--- trunk/sys/mips/conf/TP-WN1043ND.hints (rev 0)
+++ trunk/sys/mips/conf/TP-WN1043ND.hints 2018-05-26 21:55:02 UTC (rev 9987)
@@ -0,0 +1,133 @@
+#
+# This file adds to the values in AR91XX_BASE.hints.
+#
+# $FreeBSD: stable/10/sys/mips/conf/TP-WN1043ND.hints 235345 2012-05-12 17:41:42Z adrian $
+
+# Hard-code the PHY for now, until there's switch phy support.
+# hint.arge.0.phymask=0x000c
+hint.arge.0.phymask=0x0000
+hint.arge.0.media=1000
+hint.arge.0.fduplex=1
+# Where is the MAC address stored in flash for this particular unit.
+hint.arge.0.eeprommac=0x1f01fc00
+
+# This isn't used, but configure it anyway.
+# This should eventually just not be configured, but the if then
+# needs to be properly disabled or spurious interrupts occur.
+hint.arge.1.phymask=0x0
+
+# Where the ART is
+hint.ath.0.eepromaddr=0x1fff1000
+
+#
+# Define a slightly custom flash layout.
+
+# The default flash layout:
+#
+# 128k: uboot
+# 1024k: kernel
+# 4096k: rootfs
+# 2816: unknown
+# 64k: board config?
+# 64k: ART
+#
+# from printenv:
+# bootargs=console=ttyS0,115200 root=31:02 rootfstype=jffs2 init=/sbin/init
+# mtdparts=ar9100-nor0:128k(u-boot),1024k(kernel),4096k(rootfs),64k(art)
+
+# This isn't a lot of space!
+# So:
+# 128k: uboot
+# 2048k: kernel
+# 5888k: rootfs
+# 64k: config
+# 64k: ART
+
+hint.map.0.at="flash/spi0"
+hint.map.0.start=0x00000000
+hint.map.0.end=0x000200000
+hint.map.0.name="uboot"
+hint.map.0.readonly=1
+
+hint.map.1.at="flash/spi0"
+hint.map.1.start=0x00020000
+hint.map.1.end=0x00220000
+hint.map.1.name="kernel"
+hint.map.1.readonly=1
+
+hint.map.2.at="flash/spi0"
+hint.map.2.start=0x00220000
+hint.map.2.end=0x007e0000
+hint.map.2.name="rootfs"
+hint.map.2.readonly=1
+
+hint.map.3.at="flash/spi0"
+hint.map.3.start=0x007e0000
+hint.map.3.end=0x007f0000
+hint.map.3.name="cfg"
+hint.map.3.readonly=0
+
+# This is radio calibration section. It is (or should be!) unique
+# for each board, to take into account thermal and electrical differences
+# as well as the regulatory compliance data.
+#
+hint.map.4.at="flash/spi0"
+hint.map.4.start=0x007f0000
+hint.map.4.end=0x00800000
+hint.map.4.name="art"
+hint.map.4.readonly=1
+
+# GPIO specific configuration block
+
+# Don't flip on anything that isn't already enabled.
+# This includes leaving the SPI CS1/CS2 pins as GPIO pins as they're
+# not used here.
+hint.gpio.0.function_set=0x00002000
+hint.gpio.0.function_clear=0x00000000
+
+# These are the GPIO LEDs and buttons which can be software controlled.
+hint.gpio.0.pinmask=0x001c02ae
+
+# pin 1 - USB (LED)
+# pin 2 - System (LED)
+# Pin 3 - Reset (input)
+# Pin 5 - QSS (LED)
+# Pin 7 - QSS Button (input)
+# Pin 8 - wired into the chip reset line
+# Pin 9 - WLAN
+# Pin 10 - UART TX (not GPIO)
+# Pin 13 - UART RX (not GPIO)
+# Pin 18 - RTL8366RB switch data line
+# Pin 19 - RTL8366RB switch clock line
+# Pin 20 - "GPIO20"
+
+# LEDs are configured separately and driven by the LED device
+#hint.gpioled.0.at="gpiobus0"
+#hint.gpioled.0.name="usb"
+#hint.gpioled.0.pins=0x0002
+
+hint.gpioled.1.at="gpiobus0"
+hint.gpioled.1.name="system"
+hint.gpioled.1.pins=0x0004
+
+hint.gpioled.2.at="gpiobus0"
+hint.gpioled.2.name="qss"
+hint.gpioled.2.pins=0x0020
+
+hint.gpioled.3.at="gpiobus0"
+hint.gpioled.3.name="wlan"
+hint.gpioled.3.pins=0x0200
+
+# GPIO I2C bus
+hint.gpioiic.0.at="gpiobus0"
+hint.gpioiic.0.pins=0xc0000
+hint.gpioiic.0.scl=1
+hint.gpioiic.0.sda=0
+
+# I2C bus
+# Don't be strict about I2C protocol - the relaxed semantics are required
+# by the realtek switch PHY.
+hint.iicbus.0.strict=0
+
+# Bit bang bus - override default delay
+#hint.iicbb.0.udelay=3
Property changes on: trunk/sys/mips/conf/TP-WN1043ND.hints
___________________________________________________________________
Added: mnbsd:nokeywords
## -0,0 +1 ##
+MidnightBSD=%H
\ No newline at end of property
Added: trunk/sys/mips/conf/WZR-300HP
===================================================================
--- trunk/sys/mips/conf/WZR-300HP (rev 0)
+++ trunk/sys/mips/conf/WZR-300HP 2018-05-26 21:55:02 UTC (rev 9987)
@@ -0,0 +1,57 @@
+#
+# Specific board setup for the Buffalo Airstation WZR-300HP
+#
+# The WZR-300HP has the following hardware:
+#
+# + AR7242 CPU SoC
+# + AR9280 5GHz 11n
+# + AR8136 Gigabit switch
+# + 2 m25ll128 based 16MB flash
+# + 64MB RAM
+# + uboot environment
+
+# $FreeBSD: stable/10/sys/mips/conf/WZR-300HP 266331 2014-05-17 17:34:37Z ian $
+
+include "AR724X_BASE"
+ident "WZR-300HP"
+hints "WZR-300HP.hints"
+
+options AR71XX_REALMEM=64*1024*1024
+
+options AR71XX_ENV_UBOOT
+
+options BOOTVERBOSE
+# Don't include the SCSI/CAM strings in the default build
+options SCSI_NO_SENSE_STRINGS
+options SCSI_NO_OP_STRINGS
+
+# .. And no sysctl strings
+options NO_SYSCTL_DESCR
+
+# GEOM modules
+device geom_map # to get access to the SPI flash partitions
+device geom_uncompress # compressed in-memory filesystem hackery!
+
+options ROOTDEVNAME=\"ufs:/dev/map/rootfs.uncompress\"
+
+# options MD_ROOT
+# options MD_ROOT_SIZE="6144"
+
+options AR71XX_ATH_EEPROM # Fetch EEPROM/PCI config from flash
+options ATH_EEPROM_FIRMWARE # Use EEPROM from flash
+device firmware # Used by the above
+
+# Options required for miiproxy and mdiobus
+options ARGE_MDIO # Export an MDIO bus separate from arge
+device miiproxy # MDIO bus <-> MII PHY rendezvous
+
+device etherswitch
+device arswitch
+
+# Enable GPIO
+device gpio
+device gpioled
+
+# hwpmc
+device hwpmc_mips24k
+device hwpmc
Property changes on: trunk/sys/mips/conf/WZR-300HP
___________________________________________________________________
Added: mnbsd:nokeywords
## -0,0 +1 ##
+MidnightBSD=%H
\ No newline at end of property
Added: trunk/sys/mips/conf/WZR-300HP.hints
===================================================================
--- trunk/sys/mips/conf/WZR-300HP.hints (rev 0)
+++ trunk/sys/mips/conf/WZR-300HP.hints 2018-05-26 21:55:02 UTC (rev 9987)
@@ -0,0 +1,187 @@
+# $FreeBSD: stable/10/sys/mips/conf/WZR-300HP.hints 255659 2013-09-17 22:26:07Z sbruno $
+
+# arge0 is connected to the LAN side of the switch PHY.
+# arge1 is connected to the single port WAN side of the switch PHY.
+
+# arge1 MDIO bus
+hint.argemdio.0.at="nexus0"
+hint.argemdio.0.maddr=0x1a000000
+hint.argemdio.0.msize=0x1000
+hint.argemdio.0.order=0
+
+hint.arge.0.phymask=0x0
+hint.arge.0.media=1000
+hint.arge.0.fduplex=1
+hint.arge.0.eeprommac=0x1f05120c
+hint.arge.0.mdio=mdioproxy1 # .. off of the switch mdiobus
+
+
+# arge1: nail to 1000/full, RMII - connected to the switch
+hint.arge.1.media=1000 # Map to 1000/full
+hint.arge.1.fduplex=1 #
+hint.arge.1.phymask=0x0 # no directly mapped PHYs
+
+#
+# AR7240 switch config
+#
+hint.arswitch.0.at="mdio0"
+hint.arswitch.0.is_7240=1 # We need to be explicitly told this
+hint.arswitch.0.numphys=4 # 4 active switch PHYs (PHY 0 -> 3)
+hint.arswitch.0.phy4cpu=1 # Yes, PHY 4 == dedicated PHY
+hint.arswitch.0.is_rgmii=0 # No, not RGMII
+hint.arswitch.0.is_gmii=0 # No, not GMII
+
+# ath0 - slot 0
+hint.pcib.0.bus.0.0.0.ath_fixup_addr=0x1f051000
+hint.pcib.0.bus.0.0.0.ath_fixup_size=4096
+
+# .. and now, telling each ath(4) NIC where to find the firmware
+# image.
+hint.ath.0.eeprom_firmware="pcib.0.bus.0.0.0.eeprom_firmware"
+
+# Inherited from AR724X_BASE.hints
+#hint.mx25l.0.at="spibus0"
+#hint.mx25l.0.cs=0
+# This board has two 16 MB flash devices on difference Chip Select pins
+hint.mx25l.1.at="spibus0"
+hint.mx25l.1.cs=1
+
+
+# Geom MAP
+
+# The WRZ-300HP has 2 16MB flash part - HOWEVER, the 64k caldata isn't
+# at the end of the flash. It's ~ 328KB into the flash image.
+
+# mtdparts=ar7240-nor0:
+# 256k(u-boot)
+# 64k(u-boot-env)
+# 64k at 320k(ART)
+# 1152k at 384k(uImage)
+# 6592k at 1536k(rootfs)
+# 64k at 8128k(properties)
+
+# Uboot lies like a lying liar. OpenWRT does this:
+# [ 0.570000] Concatenating MTD devices:
+# [ 0.570000] (0): "spi0.0"
+# [ 0.570000] (1): "spi0.1"
+# [ 0.580000] into device "flash"
+# [ 0.580000] Creating 7 MTD partitions on "flash":
+# [ 0.590000] 0x000000000000-0x000000040000 : "u-boot"
+# [ 0.600000] 0x000000040000-0x000000050000 : "u-boot-env"
+# [ 0.600000] 0x000000050000-0x000000060000 : "art"
+# [ 0.610000] 0x000000060000-0x000000160000 : "kernel"
+# [ 0.620000] 0x000000160000-0x000001ff0000 : "rootfs"
+# [ 0.620000] mtd: partition "rootfs" set to be root filesystem
+# [ 0.630000] mtd: partition "rootfs_data" created automatically, ofs=330000, len=1CC0000
+# [ 0.640000] 0x000000330000-0x000001ff0000 : "rootfs_data"
+# [ 0.650000] 0x000001ff0000-0x000002000000 : "user_property"
+# [ 0.650000] 0x000000060000-0x000001ff0000 : "firmware"
+
+hint.map.0.at="flash/spi0"
+hint.map.0.start=0x00000000
+hint.map.0.end= 0x00040000
+hint.map.0.name="uboot"
+hint.map.0.readonly=1
+
+hint.map.1.at="flash/spi0"
+hint.map.1.start=0x00040000
+hint.map.1.end= 0x00050000 # 64k u-boot-env
+hint.map.1.name="u-boot-env"
+hint.map.1.readonly=1
+
+hint.map.2.at="flash/spi0"
+hint.map.2.start=0x00050000
+hint.map.2.end= 0x00060000 # 64k ART
+hint.map.2.name="ART"
+hint.map.2.readonly=1
+
+hint.map.3.at="flash/spi0"
+hint.map.3.start=0x00060000
+hint.map.3.end= 0x00160000
+hint.map.3.name="kernel"
+hint.map.3.readonly=1
+
+hint.map.4.at="flash/spi0"
+hint.map.4.start=0x00160000
+hint.map.4.end= 0x00FF0000
+hint.map.4.name="rootfs"
+hint.map.4.readonly=1
+
+#hint.map.5.at="flash/spi1"
+hint.map.5.at="flash/spi0"
+hint.map.5.start=0x00FF0000
+hint.map.5.end= 0x01000000
+hint.map.5.name="cfg"
+hint.map.5.readonly=0
+
+# GPIO specific configuration block
+
+#define GPIO_PIN_INPUT 0x0001 /* input direction */
+#define GPIO_PIN_OUTPUT 0x0002 /* output direction */
+#define GPIO_PIN_OPENDRAIN 0x0004 /* open-drain output */
+#define GPIO_PIN_PUSHPULL 0x0008 /* push-pull output */
+#define GPIO_PIN_TRISTATE 0x0010 /* output disabled */
+#define GPIO_PIN_PULLUP 0x0020 /* internal pull-up enabled */
+#define GPIO_PIN_PULLDOWN 0x0040 /* internal pull-down enabled */
+#define GPIO_PIN_INVIN 0x0080 /* invert input */
+#define GPIO_PIN_INVOUT 0x0100 /* invert output */
+#define GPIO_PIN_PULSATE 0x0200 /* pulsate in hardware */
+
+# Pin 1 - SCK
+# Pin 2 - SDA
+# Pin 3 - test 2
+# Pin 4 - test 3
+# Pin 5 - USB (LED Blue)
+# Pin 6 - test a
+# Pin 7 - Security (LED Orange)
+# Pin 8 - Router (LED Green)
+# Pin 9 - Movie Engine On (LED Blue)
+# Pin 10 - Movie Engine Off (LED Blue)
+# Pin 11 - test a
+# Pin 12 - test a
+# Pin 13 - test a
+# Pin 14 - USB Power (turn on by default)
+# Pin 15 - test a
+# Pin 16 - test a
+# Pin 17 - diag (LED red)
+
+# Don't flip on anything that isn't already enabled.
+# Force on USB power pin 14
+#hint.gpio.0.function_set=0x00000000
+#hint.gpio.0.function_clear=0x00000000
+
+# These are the GPIO LEDs and buttons which can be software controlled.
+hint.gpio.0.pinmask=0x000103D0
+
+hint.gpio.0.pinon=0x00000000
+
+hint.gpioiic.0.at="gpiobus0"
+hint.gpioiic.0.pins=0x0003
+hint.gpioiic.0.sda=0
+hint.gpioiic.0.scl=1
+
+# LEDs are configured separately and driven by the LED device
+# usb tested good
+hint.gpioled.0.at="gpiobus0"
+hint.gpioled.0.name="blue-usb"
+hint.gpioled.0.pins=0x00000010
+
+hint.gpioled.1.at="gpiobus0"
+hint.gpioled.1.name="orange-security"
+hint.gpioled.1.pins=0x00000040
+
+hint.gpioled.2.at="gpiobus0"
+hint.gpioled.2.name="green-router"
+hint.gpioled.2.pins=0x00000080
+
+hint.gpioled.3.at="gpiobus0"
+hint.gpioled.3.name="blue-movie-engine-on"
+hint.gpioled.3.pins=0x00000100
+
+hint.gpioled.4.at="gpiobus0"
+hint.gpioled.4.name="blue-movie-engine-off"
+hint.gpioled.4.pins=0x00000200
+
+hint.gpioled.5.at="gpiobus0"
+hint.gpioled.5.name="red-diag"
+hint.gpioled.5.pins=0x00010000
Property changes on: trunk/sys/mips/conf/WZR-300HP.hints
___________________________________________________________________
Added: mnbsd:nokeywords
## -0,0 +1 ##
+MidnightBSD=%H
\ No newline at end of property
Added: trunk/sys/mips/conf/XLP
===================================================================
--- trunk/sys/mips/conf/XLP (rev 0)
+++ trunk/sys/mips/conf/XLP 2018-05-26 21:55:02 UTC (rev 9987)
@@ -0,0 +1,28 @@
+# XLP -- Generic kernel configuration file for FreeBSD/mips
+#
+# For more information on this file, please read the handbook section on
+# Kernel Configuration Files:
+#
+# http://www.FreeBSD.org/doc/en_US.ISO8859-1/books/handbook/kernelconfig-config.html
+#
+# The handbook is also available locally in /usr/share/doc/handbook
+# if you've installed the doc distribution, otherwise always see the
+# FreeBSD World Wide Web server (http://www.FreeBSD.org/) for the
+# latest information.
+#
+# An exhaustive list of options and more detailed explanations of the
+# device lines is also present in the ../../conf/NOTES and NOTES files.
+# If you are in doubt as to the purpose or necessity of a line, check first
+# in NOTES.
+#
+# $FreeBSD: stable/10/sys/mips/conf/XLP 233644 2012-03-29 02:54:35Z jmallett $
+
+machine mips mips
+ident XLP
+
+makeoptions KERNLOADADDR=0x80100000
+
+include "std.XLP"
+
+makeoptions TRAMPLOADADDR=0xffffffff85000000
+makeoptions TRAMP_ARCH_FLAGS="-mabi=64 -march=mips64"
Property changes on: trunk/sys/mips/conf/XLP
___________________________________________________________________
Added: mnbsd:nokeywords
## -0,0 +1 ##
+MidnightBSD=%H
\ No newline at end of property
Added: trunk/sys/mips/conf/XLP.hints
===================================================================
--- trunk/sys/mips/conf/XLP.hints (rev 0)
+++ trunk/sys/mips/conf/XLP.hints 2018-05-26 21:55:02 UTC (rev 9987)
@@ -0,0 +1,5 @@
+# $FreeBSD: stable/10/sys/mips/conf/XLP.hints 233540 2012-03-27 11:17:04Z jchandra $
+
+# RTC
+hint.ds1374_rtc.0.at="iicbus1"
+hint.ds1374_rtc.0.addr=0xd0
Property changes on: trunk/sys/mips/conf/XLP.hints
___________________________________________________________________
Added: mnbsd:nokeywords
## -0,0 +1 ##
+MidnightBSD=%H
\ No newline at end of property
Added: trunk/sys/mips/conf/XLP64
===================================================================
--- trunk/sys/mips/conf/XLP64 (rev 0)
+++ trunk/sys/mips/conf/XLP64 2018-05-26 21:55:02 UTC (rev 9987)
@@ -0,0 +1,29 @@
+# XLP64 -- Generic kernel configuration file for FreeBSD/mips
+#
+# For more information on this file, please read the handbook section on
+# Kernel Configuration Files:
+#
+# http://www.FreeBSD.org/doc/en_US.ISO8859-1/books/handbook/kernelconfig-config.html
+#
+# The handbook is also available locally in /usr/share/doc/handbook
+# if you've installed the doc distribution, otherwise always see the
+# FreeBSD World Wide Web server (http://www.FreeBSD.org/) for the
+# latest information.
+#
+# An exhaustive list of options and more detailed explanations of the
+# device lines is also present in the ../../conf/NOTES and NOTES files.
+# If you are in doubt as to the purpose or necessity of a line, check first
+# in NOTES.
+#
+# $FreeBSD: stable/10/sys/mips/conf/XLP64 233644 2012-03-29 02:54:35Z jmallett $
+
+machine mips mips64
+ident XLP64
+
+makeoptions ARCH_FLAGS="-march=mips64r2 -mabi=64"
+makeoptions KERNLOADADDR=0xffffffff80100000
+
+include "std.XLP"
+
+makeoptions TRAMPLOADADDR=0xffffffff85000000
+makeoptions TRAMP_ARCH_FLAGS="-mabi=64 -march=mips64"
Property changes on: trunk/sys/mips/conf/XLP64
___________________________________________________________________
Added: mnbsd:nokeywords
## -0,0 +1 ##
+MidnightBSD=%H
\ No newline at end of property
Added: trunk/sys/mips/conf/XLPN32
===================================================================
--- trunk/sys/mips/conf/XLPN32 (rev 0)
+++ trunk/sys/mips/conf/XLPN32 2018-05-26 21:55:02 UTC (rev 9987)
@@ -0,0 +1,35 @@
+# XLPN32 -- Generic kernel configuration file for FreeBSD/mips
+#
+# For more information on this file, please read the handbook section on
+# Kernel Configuration Files:
+#
+# http://www.FreeBSD.org/doc/en_US.ISO8859-1/books/handbook/kernelconfig-config.html
+#
+# The handbook is also available locally in /usr/share/doc/handbook
+# if you've installed the doc distribution, otherwise always see the
+# FreeBSD World Wide Web server (http://www.FreeBSD.org/) for the
+# latest information.
+#
+# An exhaustive list of options and more detailed explanations of the
+# device lines is also present in the ../../conf/NOTES and NOTES files.
+# If you are in doubt as to the purpose or necessity of a line, check first
+# in NOTES.
+#
+# $FreeBSD: stable/10/sys/mips/conf/XLPN32 233644 2012-03-29 02:54:35Z jmallett $
+
+machine mips mipsn32
+ident XLPN32
+
+makeoptions ARCH_FLAGS="-march=mips64 -mabi=n32"
+makeoptions KERNLOADADDR=0x80100000
+
+include "std.XLP"
+
+nooption DDB
+nooption KDB
+nooption GDB
+nooption BREAK_TO_DEBUGGER
+nooption ALT_BREAK_TO_DEBUGGER
+
+makeoptions TRAMPLOADADDR=0xffffffff85000000
+makeoptions TRAMP_ARCH_FLAGS="-mabi=64 -march=mips64"
Property changes on: trunk/sys/mips/conf/XLPN32
___________________________________________________________________
Added: mnbsd:nokeywords
## -0,0 +1 ##
+MidnightBSD=%H
\ No newline at end of property
Added: trunk/sys/mips/conf/XLR
===================================================================
--- trunk/sys/mips/conf/XLR (rev 0)
+++ trunk/sys/mips/conf/XLR 2018-05-26 21:55:02 UTC (rev 9987)
@@ -0,0 +1,146 @@
+#################################RMI_BSD#####################################
+# Copyright (c) 2003-2009 RMI Corporation
+# All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions
+# are met:
+# 1. Redistributions of source code must retain the above copyright
+# notice, this list of conditions and the following disclaimer.
+# 2. Redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in the
+# documentation and/or other materials provided with the distribution.
+# 3. Neither the name of RMI Corporation, nor the names of its contributors,
+# may be used to endorse or promote products derived from this software
+# without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+# ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+# IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+# ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+# FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+# DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+# OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+# HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+# LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+# OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+# SUCH DAMAGE.
+#################################RMI_BSD#####################################
+# XLR -- Generic kernel configuration file for FreeBSD/mips
+#
+# For more information on this file, please read the handbook section on
+# Kernel Configuration Files:
+#
+# http://www.FreeBSD.org/doc/en_US.ISO8859-1/books/handbook/kernelconfig-config.html
+#
+# The handbook is also available locally in /usr/share/doc/handbook
+# if you've installed the doc distribution, otherwise always see the
+# FreeBSD World Wide Web server (http://www.FreeBSD.org/) for the
+# latest information.
+#
+# An exhaustive list of options and more detailed explanations of the
+# device lines is also present in the ../../conf/NOTES and NOTES files.
+# If you are in doubt as to the purpose or necessity of a line, check first
+# in NOTES.
+#
+# $FreeBSD: stable/10/sys/mips/conf/XLR 249083 2013-04-04 07:12:24Z mav $
+
+machine mips mips
+ident XLR
+include "../rmi/std.xlr"
+
+makeoptions MODULES_OVERRIDE=""
+makeoptions DEBUG=-g # Build kernel with gdb(1) debug symbols
+makeoptions KERNLOADADDR=0x80100000
+#profile 2
+
+options SCHED_ULE # ULE scheduler
+#options VERBOSE_SYSINIT
+#options SCHED_4BSD # 4BSD scheduler
+options SMP
+options PREEMPTION # Enable kernel thread preemption
+#options FULL_PREEMPTION # Enable kernel thread preemption
+options INET # InterNETworking
+options INET6 # IPv6 communications protocols
+options FFS # Berkeley Fast Filesystem
+#options SOFTUPDATES # Enable FFS soft updates support
+options UFS_ACL # Support for access control lists
+options UFS_DIRHASH # Improve performance on big directories
+options NFSCL
+options NFS_ROOT
+#
+options BOOTP
+options BOOTP_NFSROOT
+options BOOTP_NFSV3
+options BOOTP_WIRED_TO=nlge0
+options BOOTP_COMPAT
+options ROOTDEVNAME=\"nfs:10.1.1.8:/usr/extra/nfsroot\"
+#
+#options MD_ROOT # MD is a potential root device
+#options MD_ROOT_SIZE=27000
+#options MD_ROOT_SIZE=5120
+#options ROOTDEVNAME=\"ufs:md0\"
+options _KPOSIX_PRIORITY_SCHEDULING # POSIX P1003_1B real-time extensions
+options HZ=1000
+options NO_SWAPPING
+
+#Debugging options
+options KTRACE # ktrace(1) support
+options DDB
+options KDB
+options GDB
+options ALT_BREAK_TO_DEBUGGER
+options BREAK_TO_DEBUGGER
+#options DEADLKRES #Enable the deadlock resolver
+options INVARIANTS #Enable calls of extra sanity checking
+options INVARIANT_SUPPORT #Extra sanity checks of internal structures, required by INVARIANTS
+#options WITNESS #Enable checks to detect deadlocks and cycles
+#options WITNESS_SKIPSPIN #Don't run witness on spinlocks for speed
+#options KTR # ktr(4) and ktrdump(8) support
+#options KTR_COMPILE=(KTR_LOCK|KTR_PROC|KTR_INTR|KTR_CALLOUT|KTR_UMA|KTR_SYSC)
+#options KTR_ENTRIES=131072
+
+#options LOCK_PROFILING
+#options SLEEPQUEUE_PROFILING
+#options TURNSTILE_PROFILING
+
+device pci
+#device ata
+device uart
+# Pseudo
+device loop
+device random
+device md
+device bpf
+
+# Network
+device miibus
+device nlge
+device ether
+device re
+device msk
+
+device da
+device scbus
+device ehci # EHCI PCI->USB interface (USB 2.0)
+device usb # USB Bus (required)
+#options USB_DEBUG # enable debug msgs
+#device uhid # "Human Interface Devices"
+device umass # Disks/Mass storage - Requires scbus and da
+
+#device cfi
+
+#i2c
+device ic
+device iic
+device iicbb
+device iicbus
+device ds1374u # RTC on XLR boards
+device max6657 # Temparature sensor on XLR boards
+device at24co2n # EEPROM on XLR boards
+
+#crypto
+# Not yet
+#device cryptodev
+#device crypto
+#device rmisec
Property changes on: trunk/sys/mips/conf/XLR
___________________________________________________________________
Added: mnbsd:nokeywords
## -0,0 +1 ##
+MidnightBSD=%H
\ No newline at end of property
Added: trunk/sys/mips/conf/XLR64
===================================================================
--- trunk/sys/mips/conf/XLR64 (rev 0)
+++ trunk/sys/mips/conf/XLR64 2018-05-26 21:55:02 UTC (rev 9987)
@@ -0,0 +1,120 @@
+# XLR64 -- Kernel configuration file for N64 kernel on XLR/XLS
+#
+# For more information on this file, please read the handbook section on
+# Kernel Configuration Files:
+#
+# http://www.FreeBSD.org/doc/en_US.ISO8859-1/books/handbook/kernelconfig-config.html
+#
+# The handbook is also available locally in /usr/share/doc/handbook
+# if you've installed the doc distribution, otherwise always see the
+# FreeBSD World Wide Web server (http://www.FreeBSD.org/) for the
+# latest information.
+#
+# An exhaustive list of options and more detailed explanations of the
+# device lines is also present in the ../../conf/NOTES and NOTES files.
+# If you are in doubt as to the purpose or necessity of a line, check first
+# in NOTES.
+#
+# $FreeBSD: stable/10/sys/mips/conf/XLR64 253845 2013-07-31 17:21:18Z obrien $
+
+machine mips mips64
+ident XLR64
+include "../rmi/std.xlr"
+
+makeoptions MODULES_OVERRIDE=""
+makeoptions DEBUG=-g # Build kernel with gdb(1) debug symbols
+makeoptions ARCH_FLAGS="-march=mips64 -mabi=64"
+makeoptions KERNLOADADDR=0xffffffff80100000
+
+#profile 2
+
+options SCHED_ULE # ULE scheduler
+#options VERBOSE_SYSINIT
+#options SCHED_4BSD # 4BSD scheduler
+options SMP
+#options PREEMPTION # Enable kernel thread preemption
+#options FULL_PREEMPTION # Enable kernel thread preemption
+options INET # InterNETworking
+options INET6 # IPv6 communications protocols
+options FFS # Berkeley Fast Filesystem
+#options SOFTUPDATES # Enable FFS soft updates support
+options UFS_ACL # Support for access control lists
+options UFS_DIRHASH # Improve performance on big directories
+options NFSCL
+options NFS_ROOT
+#
+options BOOTP
+options BOOTP_NFSROOT
+options BOOTP_NFSV3
+options BOOTP_WIRED_TO=nlge0
+options BOOTP_COMPAT
+options ROOTDEVNAME=\"nfs:10.1.1.8:/usr/extra/nfsroot\"
+#
+#options MD_ROOT # MD is a potential root device
+#options MD_ROOT_SIZE=27000
+#options MD_ROOT_SIZE=5120
+#options ROOTDEVNAME=\"ufs:md0\"
+options _KPOSIX_PRIORITY_SCHEDULING # POSIX P1003_1B real-time extensions
+options HZ=1000
+options NO_SWAPPING
+
+#Debugging options
+options KTRACE # ktrace(1) support
+options DDB
+options KDB
+options GDB
+options ALT_BREAK_TO_DEBUGGER
+options BREAK_TO_DEBUGGER
+#options DEADLKRES #Enable the deadlock resolver
+options INVARIANTS #Enable calls of extra sanity checking
+options INVARIANT_SUPPORT #Extra sanity checks of internal structures, required by INVARIANTS
+#options WITNESS #Enable checks to detect deadlocks and cycles
+#options WITNESS_SKIPSPIN #Don't run witness on spinlocks for speed
+#options KTR # ktr(4) and ktrdump(8) support
+#options KTR_COMPILE=(KTR_LOCK|KTR_PROC|KTR_INTR|KTR_CALLOUT|KTR_UMA|KTR_SYSC)
+#options KTR_ENTRIES=131072
+
+#options LOCK_PROFILING
+#options SLEEPQUEUE_PROFILING
+#options TURNSTILE_PROFILING
+
+device pci
+#device ata
+device uart
+# Pseudo
+device loop
+device random
+device md
+device bpf
+
+# Network
+device miibus
+device nlge
+device ether
+device re
+device msk
+
+device da
+device scbus
+device ehci # EHCI PCI->USB interface (USB 2.0)
+device usb # USB Bus (required)
+options USB_DEBUG # enable debug msgs
+#device uhid # "Human Interface Devices"
+device umass # Disks/Mass storage - Requires scbus and da
+
+#device cfi
+
+#i2c
+device ic
+device iic
+device iicbb
+device iicbus
+device ds1374u # RTC on XLR boards
+device max6657 # Temparature sensor on XLR boards
+device at24co2n # EEPROM on XLR boards
+
+#crypto
+# Not yet
+#device cryptodev
+#device crypto
+#device rmisec
Property changes on: trunk/sys/mips/conf/XLR64
___________________________________________________________________
Added: mnbsd:nokeywords
## -0,0 +1 ##
+MidnightBSD=%H
\ No newline at end of property
Added: trunk/sys/mips/conf/XLRN32
===================================================================
--- trunk/sys/mips/conf/XLRN32 (rev 0)
+++ trunk/sys/mips/conf/XLRN32 2018-05-26 21:55:02 UTC (rev 9987)
@@ -0,0 +1,124 @@
+# XLRN32 -- Kernel configuration file for N32 kernel on XLR/XLS
+#
+# For more information on this file, please read the handbook section on
+# Kernel Configuration Files:
+#
+# http://www.FreeBSD.org/doc/en_US.ISO8859-1/books/handbook/kernelconfig-config.html
+#
+# The handbook is also available locally in /usr/share/doc/handbook
+# if you've installed the doc distribution, otherwise always see the
+# FreeBSD World Wide Web server (http://www.FreeBSD.org/) for the
+# latest information.
+#
+# An exhaustive list of options and more detailed explanations of the
+# device lines is also present in the ../../conf/NOTES and NOTES files.
+# If you are in doubt as to the purpose or necessity of a line, check first
+# in NOTES.
+#
+# $FreeBSD: stable/10/sys/mips/conf/XLRN32 266331 2014-05-17 17:34:37Z ian $
+
+machine mips mipsn32
+ident XLRN32
+include "../rmi/std.xlr"
+
+makeoptions MODULES_OVERRIDE=""
+makeoptions DEBUG=-g # Build kernel with gdb(1) debug symbols
+makeoptions ARCH_FLAGS="-march=mips64 -mabi=n32"
+makeoptions KERNLOADADDR=0x80100000
+
+#profile 2
+
+options SCHED_ULE # ULE scheduler
+#options VERBOSE_SYSINIT
+#options SCHED_4BSD # 4BSD scheduler
+options SMP
+options PREEMPTION # Enable kernel thread preemption
+#options FULL_PREEMPTION # Enable kernel thread preemption
+options INET # InterNETworking
+options INET6 # IPv6 communications protocols
+options FFS # Berkeley Fast Filesystem
+#options SOFTUPDATES # Enable FFS soft updates support
+options UFS_ACL # Support for access control lists
+options UFS_DIRHASH # Improve performance on big directories
+options NFSCL
+options NFS_ROOT
+#
+options BOOTP
+options BOOTP_NFSROOT
+options BOOTP_NFSV3
+options BOOTP_WIRED_TO=nlge0
+options BOOTP_COMPAT
+options ROOTDEVNAME=\"nfs:10.1.1.8:/usr/extra/nfsroot\"
+#
+#options MD_ROOT # MD is a potential root device
+#options MD_ROOT_SIZE=27000
+#options MD_ROOT_SIZE=5120
+#options ROOTDEVNAME=\"ufs:md0\"
+options _KPOSIX_PRIORITY_SCHEDULING # POSIX P1003_1B real-time extensions
+options HZ=1000
+options NO_SWAPPING
+
+#Debugging options
+options KTRACE # ktrace(1) support
+#options DDB
+#options KDB
+#options GDB
+#options ALT_BREAK_TO_DEBUGGER
+#options DEADLKRES #Enable the deadlock resolver
+options INVARIANTS #Enable calls of extra sanity checking
+options INVARIANT_SUPPORT #Extra sanity checks of internal structures, required by INVARIANTS
+#options WITNESS #Enable checks to detect deadlocks and cycles
+#options WITNESS_SKIPSPIN #Don't run witness on spinlocks for speed
+#options KTR # ktr(4) and ktrdump(8) support
+#options KTR_COMPILE=(KTR_LOCK|KTR_PROC|KTR_INTR|KTR_CALLOUT|KTR_UMA|KTR_SYSC)
+#options KTR_ENTRIES=131072
+
+#options LOCK_PROFILING
+#options SLEEPQUEUE_PROFILING
+#options TURNSTILE_PROFILING
+
+device pci
+#device ata
+#options XLR_PERFMON # Enable XLR processor activity monitoring
+options BREAK_TO_DEBUGGER
+device uart
+# Pseudo
+device loop
+device random
+device md
+device bpf
+
+# Network
+device miibus
+device nlge
+device ether
+device re
+device msk
+
+device da
+device scbus
+#device ohci # OHCI PCI->USB interface
+device ehci # EHCI PCI->USB interface (USB 2.0)
+device usb # USB Bus (required)
+options USB_DEBUG # enable debug msgs
+#device udbp # USB Double Bulk Pipe devices
+#device ugen # Generic
+#device uhid # "Human Interface Devices"
+device umass # Disks/Mass storage - Requires scbus and da
+
+#device cfi
+
+#i2c
+device ic
+device iic
+device iicbb
+device iicbus
+device ds1374u # RTC on XLR boards
+device max6657 # Temparature sensor on XLR boards
+device at24co2n # EEPROM on XLR boards
+
+#crypto
+# Not yet
+#device cryptodev
+#device crypto
+#device rmisec
Property changes on: trunk/sys/mips/conf/XLRN32
___________________________________________________________________
Added: mnbsd:nokeywords
## -0,0 +1 ##
+MidnightBSD=%H
\ No newline at end of property
Added: trunk/sys/mips/conf/std.SWARM
===================================================================
--- trunk/sys/mips/conf/std.SWARM (rev 0)
+++ trunk/sys/mips/conf/std.SWARM 2018-05-26 21:55:02 UTC (rev 9987)
@@ -0,0 +1,60 @@
+#
+# $FreeBSD: stable/10/sys/mips/conf/std.SWARM 266331 2014-05-17 17:34:37Z ian $
+#
+
+hints "SWARM.hints"
+include "../sibyte/std.sibyte"
+
+options CFE
+options CFE_CONSOLE
+options CFE_ENV
+options ALT_BREAK_TO_DEBUGGER
+
+cpu CPU_SB1
+
+makeoptions DEBUG=-g #Build kernel with gdb(1) debug symbols
+makeoptions MODULES_OVERRIDE=""
+
+options DDB
+options KDB
+
+options SCHED_4BSD #4BSD scheduler
+options INET #InterNETworking
+options NFSCL #Network Filesystem Client
+options NFS_ROOT #NFS usable as /, requires NFSCL
+options PSEUDOFS #Pseudo-filesystem framework
+options _KPOSIX_PRIORITY_SCHEDULING #Posix P1003_1B real-time extensions
+
+# Debugging for use in -current
+#options DEADLKRES
+options INVARIANTS
+options INVARIANT_SUPPORT
+options WITNESS
+
+options FFS #Fast filesystem
+
+options KTRACE
+
+device pci
+device miibus
+device bge
+device loop
+device ether
+device md
+device random
+
+options USB_DEBUG
+device usb
+device ohci
+device uhci
+device ehci
+
+device umass
+
+device scbus
+device cd
+device da
+device pass
+
+device ata
+options ATA_STATIC_ID # Static device numbering
Property changes on: trunk/sys/mips/conf/std.SWARM
___________________________________________________________________
Added: mnbsd:nokeywords
## -0,0 +1 ##
+MidnightBSD=%H
\ No newline at end of property
Added: trunk/sys/mips/conf/std.XLP
===================================================================
--- trunk/sys/mips/conf/std.XLP (rev 0)
+++ trunk/sys/mips/conf/std.XLP 2018-05-26 21:55:02 UTC (rev 9987)
@@ -0,0 +1,116 @@
+# $FreeBSD: stable/10/sys/mips/conf/std.XLP 266331 2014-05-17 17:34:37Z ian $
+
+include "../nlm/std.xlp"
+makeoptions MODULES_OVERRIDE=""
+makeoptions DEBUG=-g # Build kernel with gdb(1) debug symbols
+#profile 2
+
+hints "XLP.hints"
+
+options SCHED_ULE # ULE scheduler
+#options VERBOSE_SYSINIT
+#options SCHED_4BSD # 4BSD scheduler
+options SMP
+options PREEMPTION # Enable kernel thread preemption
+#options FULL_PREEMPTION # Enable kernel thread preemption
+options INET # InterNETworking
+options INET6 # IPv6 communications protocols
+options FFS # Berkeley Fast Filesystem
+#options SOFTUPDATES # Enable FFS soft updates support
+options UFS_ACL # Support for access control lists
+options UFS_DIRHASH # Improve performance on big directories
+options NFSCL
+options NFS_ROOT
+options MSDOSFS #MSDOS Filesystem
+#
+#options BOOTP
+#options BOOTP_NFSROOT
+#options BOOTP_NFSV3
+#options BOOTP_WIRED_TO=nlge0
+#options BOOTP_COMPAT
+#options ROOTDEVNAME=\"nfs:10.1.1.8:/usr/extra/nfsroot\"
+
+options MD_ROOT # MD is a potential root device
+options MD_ROOT_SIZE=132000
+options ROOTDEVNAME=\"ufs:md0\"
+options _KPOSIX_PRIORITY_SCHEDULING # POSIX P1003_1B real-time extensions
+options HZ=1000
+options NO_SWAPPING
+
+# Debugging options
+options KTRACE # ktrace(1) support
+options DDB
+options KDB
+options GDB
+options BREAK_TO_DEBUGGER
+options ALT_BREAK_TO_DEBUGGER
+#options DEADLKRES # Enable the deadlock resolver
+#options INVARIANTS
+#options INVARIANT_SUPPORT
+#options WITNESS # Detect deadlocks and cycles
+#options WITNESS_SKIPSPIN # Don't run witness on spinlocks for speed
+#options KTR # ktr(4) and ktrdump(8) support
+#options KTR_COMPILE=(KTR_LOCK|KTR_PROC|KTR_INTR|KTR_CALLOUT|KTR_UMA|KTR_SYSC)
+#options KTR_ENTRIES=131072
+#options LOCK_DEBUG
+#options LOCK_PROFILING
+
+options GEOM_UZIP
+
+# Device tree
+options FDT
+options FDT_DTB_STATIC
+makeoptions FDT_DTS_FILE=xlp-basic.dts
+
+# Pseudo
+device loop
+device random
+device md
+device bpf
+
+# Network
+device miibus
+device ether
+device xlpge
+#device re
+device msk
+device em
+
+# Disks
+device siis
+device da
+device scbus
+#device ata
+
+# USB
+device usb # USB Bus (required)
+device ehci # EHCI PCI->USB interface (USB 2.0)
+#options USB_DEBUG # enable debug msgs
+#device ugen # Generic
+#device uhid # "Human Interface Devices"
+device umass # Requires scbus and da
+
+# i2c driver and devices
+device iic
+device iicbus
+device iicoc
+device ds1374 # RTC on XLP boards
+
+# Crypto
+device crypto
+device cryptodev
+device nlmsec
+device nlmrsa
+
+# Options that use crypto
+options IPSEC
+options GEOM_ELI
+
+# NOR
+device cfi
+device cfid
+
+# MMC/SD
+device mmc # MMC/SD bus
+device mmcsd # MMC/SD memory card
+device sdhci # Generic PCI SD Host Controller
Property changes on: trunk/sys/mips/conf/std.XLP
___________________________________________________________________
Added: mnbsd:nokeywords
## -0,0 +1 ##
+MidnightBSD=%H
\ No newline at end of property
Added: trunk/sys/mips/gxemul/files.gxemul
===================================================================
--- trunk/sys/mips/gxemul/files.gxemul (rev 0)
+++ trunk/sys/mips/gxemul/files.gxemul 2018-05-26 21:55:02 UTC (rev 9987)
@@ -0,0 +1,8 @@
+# $FreeBSD: stable/10/sys/mips/gxemul/files.gxemul 235117 2012-05-07 04:15:46Z jmallett $
+dev/gxemul/cons/gxemul_cons.c optional gxemul_cons
+mips/gxemul/gxemul_machdep.c standard
+mips/mips/intr_machdep.c standard
+mips/mips/tick.c standard
+
+dev/gxemul/disk/gxemul_disk.c optional gxemul_disk
+dev/gxemul/ether/if_gx.c optional gxemul_ether
Property changes on: trunk/sys/mips/gxemul/files.gxemul
___________________________________________________________________
Added: mnbsd:nokeywords
## -0,0 +1 ##
+MidnightBSD=%H
\ No newline at end of property
Added: trunk/sys/mips/gxemul/gxemul_machdep.c
===================================================================
--- trunk/sys/mips/gxemul/gxemul_machdep.c (rev 0)
+++ trunk/sys/mips/gxemul/gxemul_machdep.c 2018-05-26 21:55:02 UTC (rev 9987)
@@ -0,0 +1,238 @@
+/* $MidnightBSD$ */
+/*-
+ * Copyright (c) 2006 Wojciech A. Koszek <wkoszek at FreeBSD.org>
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ */
+#include <sys/cdefs.h>
+__FBSDID("$FreeBSD: stable/10/sys/mips/gxemul/gxemul_machdep.c 247297 2013-02-26 01:00:11Z attilio $");
+
+#include "opt_ddb.h"
+
+#include <sys/param.h>
+#include <sys/conf.h>
+#include <sys/kernel.h>
+#include <sys/systm.h>
+#include <sys/imgact.h>
+#include <sys/bio.h>
+#include <sys/buf.h>
+#include <sys/bus.h>
+#include <sys/cpu.h>
+#include <sys/cons.h>
+#include <sys/exec.h>
+#include <sys/ucontext.h>
+#include <sys/proc.h>
+#include <sys/kdb.h>
+#include <sys/ptrace.h>
+#include <sys/reboot.h>
+#include <sys/signalvar.h>
+#include <sys/sysent.h>
+#include <sys/sysproto.h>
+#include <sys/user.h>
+
+#include <vm/vm.h>
+#include <vm/vm_object.h>
+#include <vm/vm_page.h>
+
+#include <machine/clock.h>
+#include <machine/cpu.h>
+#include <machine/cpuregs.h>
+#include <machine/hwfunc.h>
+#include <machine/md_var.h>
+#include <machine/pmap.h>
+#include <machine/trap.h>
+
+#ifdef SMP
+#include <sys/smp.h>
+#include <machine/smp.h>
+#endif
+
+#include <mips/gxemul/mpreg.h>
+
+extern int *edata;
+extern int *end;
+
+void
+platform_cpu_init()
+{
+ /* Nothing special */
+}
+
+static void
+mips_init(void)
+{
+ int i;
+
+ for (i = 0; i < 10; i++) {
+ phys_avail[i] = 0;
+ }
+
+ /* phys_avail regions are in bytes */
+ phys_avail[0] = MIPS_KSEG0_TO_PHYS(kernel_kseg0_end);
+ phys_avail[1] = ctob(realmem);
+
+ dump_avail[0] = phys_avail[0];
+ dump_avail[1] = phys_avail[1];
+
+ physmem = realmem;
+
+ init_param1();
+ init_param2(physmem);
+ mips_cpu_init();
+ pmap_bootstrap();
+ mips_proc0_init();
+ mutex_init();
+ kdb_init();
+#ifdef KDB
+ if (boothowto & RB_KDB)
+ kdb_enter(KDB_WHY_BOOTFLAGS, "Boot flags requested debugger");
+#endif
+}
+
+/*
+ * Perform a board-level soft-reset.
+ *
+ * XXXRW: Does gxemul have a moral equivalent to board-level reset?
+ */
+void
+platform_reset(void)
+{
+
+ panic("%s: not yet", __func__);
+}
+
+void
+platform_start(__register_t a0, __register_t a1, __register_t a2,
+ __register_t a3)
+{
+ vm_offset_t kernend;
+ uint64_t platform_counter_freq;
+ int argc = a0;
+ char **argv = (char **)a1;
+ char **envp = (char **)a2;
+ int i;
+
+ /* clear the BSS and SBSS segments */
+ kernend = (vm_offset_t)&end;
+ memset(&edata, 0, kernend - (vm_offset_t)(&edata));
+
+ mips_postboot_fixup();
+
+ mips_pcpu0_init();
+
+ /*
+ * XXXRW: Support for the gxemul real-time clock required in order to
+ * usefully determine our emulated timer frequency. Go with something
+ * classic as the default in the mean time.
+ */
+ platform_counter_freq = MIPS_DEFAULT_HZ;
+ mips_timer_early_init(platform_counter_freq);
+
+ cninit();
+ printf("entry: platform_start()\n");
+
+ bootverbose = 1;
+ if (bootverbose) {
+ printf("cmd line: ");
+ for (i = 0; i < argc; i++)
+ printf("%s ", argv[i]);
+ printf("\n");
+
+ if (envp != NULL) {
+ printf("envp:\n");
+ for (i = 0; envp[i]; i += 2)
+ printf("\t%s = %s\n", envp[i], envp[i+1]);
+ } else {
+ printf("no envp.\n");
+ }
+ }
+
+ realmem = btoc(GXEMUL_MP_DEV_READ(GXEMUL_MP_DEV_MEMORY));
+ mips_init();
+
+ mips_timer_init_params(platform_counter_freq, 0);
+}
+
+#ifdef SMP
+void
+platform_ipi_send(int cpuid)
+{
+ GXEMUL_MP_DEV_WRITE(GXEMUL_MP_DEV_IPI_ONE, (1 << 16) | cpuid);
+}
+
+void
+platform_ipi_clear(void)
+{
+ GXEMUL_MP_DEV_WRITE(GXEMUL_MP_DEV_IPI_READ, 0);
+}
+
+int
+platform_ipi_intrnum(void)
+{
+ return (GXEMUL_MP_DEV_IPI_INTERRUPT - 2);
+}
+
+struct cpu_group *
+platform_smp_topo(void)
+{
+ return (smp_topo_none());
+}
+
+void
+platform_init_ap(int cpuid)
+{
+ int ipi_int_mask, clock_int_mask;
+
+ /*
+ * Unmask the clock and ipi interrupts.
+ */
+ clock_int_mask = hard_int_mask(5);
+ ipi_int_mask = hard_int_mask(platform_ipi_intrnum());
+ set_intr_mask(ipi_int_mask | clock_int_mask);
+}
+
+void
+platform_cpu_mask(cpuset_t *mask)
+{
+ unsigned i, n;
+
+ n = GXEMUL_MP_DEV_READ(GXEMUL_MP_DEV_NCPUS);
+ CPU_ZERO(mask);
+ for (i = 0; i < n; i++)
+ CPU_SET(i, mask);
+}
+
+int
+platform_processor_id(void)
+{
+ return (GXEMUL_MP_DEV_READ(GXEMUL_MP_DEV_WHOAMI));
+}
+
+int
+platform_start_ap(int cpuid)
+{
+ GXEMUL_MP_DEV_WRITE(GXEMUL_MP_DEV_STARTADDR, (intptr_t)mpentry);
+ GXEMUL_MP_DEV_WRITE(GXEMUL_MP_DEV_START, cpuid);
+ return (0);
+}
+#endif /* SMP */
Property changes on: trunk/sys/mips/gxemul/gxemul_machdep.c
___________________________________________________________________
Added: svn:eol-style
## -0,0 +1 ##
+native
\ No newline at end of property
Added: svn:keywords
## -0,0 +1 ##
+MidnightBSD=%H
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+text/plain
\ No newline at end of property
Added: trunk/sys/mips/gxemul/mpreg.h
===================================================================
--- trunk/sys/mips/gxemul/mpreg.h (rev 0)
+++ trunk/sys/mips/gxemul/mpreg.h 2018-05-26 21:55:02 UTC (rev 9987)
@@ -0,0 +1,63 @@
+/* $MidnightBSD$ */
+/*-
+ * Copyright (c) 2004-2012 Juli Mallett <jmallett at FreeBSD.org>
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ * $FreeBSD: stable/10/sys/mips/gxemul/mpreg.h 255212 2013-09-04 20:34:36Z gonzo $
+ */
+
+#ifndef _MIPS_GXEMUL_MPREG_H_
+#define _MIPS_GXEMUL_MPREG_H_
+
+#define GXEMUL_MP_DEV_BASE 0x11000000
+
+#define GXEMUL_MP_DEV_WHOAMI 0x0000
+#define GXEMUL_MP_DEV_NCPUS 0x0010
+#define GXEMUL_MP_DEV_START 0x0020
+#define GXEMUL_MP_DEV_STARTADDR 0x0030
+#define GXEMUL_MP_DEV_STACK 0x0070
+#define GXEMUL_MP_DEV_RANDOM 0x0080
+#define GXEMUL_MP_DEV_MEMORY 0x0090
+#define GXEMUL_MP_DEV_IPI_ONE 0x00a0
+#define GXEMUL_MP_DEV_IPI_MANY 0x00b0
+#define GXEMUL_MP_DEV_IPI_READ 0x00c0
+#define GXEMUL_MP_DEV_CYCLES 0x00d0
+
+#ifdef _LP64
+#define GXEMUL_MP_DEV_FUNCTION(f) \
+ (volatile uint64_t *)MIPS_PHYS_TO_DIRECT_UNCACHED(GXEMUL_MP_DEV_BASE + (f))
+#define GXEMUL_MP_DEV_READ(f) \
+ (volatile uint64_t)*GXEMUL_MP_DEV_FUNCTION(f)
+#else
+#define GXEMUL_MP_DEV_FUNCTION(f) \
+ (volatile uint32_t *)MIPS_PHYS_TO_DIRECT_UNCACHED(GXEMUL_MP_DEV_BASE + (f))
+#define GXEMUL_MP_DEV_READ(f) \
+ (volatile uint32_t)*GXEMUL_MP_DEV_FUNCTION(f)
+#endif
+#define GXEMUL_MP_DEV_WRITE(f, v) \
+ *GXEMUL_MP_DEV_FUNCTION(f) = (v)
+
+#define GXEMUL_MP_DEV_IPI_INTERRUPT (6)
+
+#endif /* !_MIPS_GXEMUL_MPREG_H */
Property changes on: trunk/sys/mips/gxemul/mpreg.h
___________________________________________________________________
Added: svn:eol-style
## -0,0 +1 ##
+native
\ No newline at end of property
Added: svn:keywords
## -0,0 +1 ##
+MidnightBSD=%H
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+text/plain
\ No newline at end of property
Added: trunk/sys/mips/gxemul/std.gxemul
===================================================================
--- trunk/sys/mips/gxemul/std.gxemul (rev 0)
+++ trunk/sys/mips/gxemul/std.gxemul 2018-05-26 21:55:02 UTC (rev 9987)
@@ -0,0 +1,4 @@
+# $FreeBSD: stable/10/sys/mips/gxemul/std.gxemul 234920 2012-05-02 08:10:15Z rwatson $
+files "../gxemul/files.gxemul"
+
+cpu CPU_MIPS4KC
Property changes on: trunk/sys/mips/gxemul/std.gxemul
___________________________________________________________________
Added: mnbsd:nokeywords
## -0,0 +1 ##
+MidnightBSD=%H
\ No newline at end of property
Added: trunk/sys/mips/idt/files.idt
===================================================================
--- trunk/sys/mips/idt/files.idt (rev 0)
+++ trunk/sys/mips/idt/files.idt 2018-05-26 21:55:02 UTC (rev 9987)
@@ -0,0 +1,10 @@
+# $FreeBSD: stable/10/sys/mips/idt/files.idt 202175 2010-01-12 21:36:08Z imp $
+
+mips/idt/idt_machdep.c standard
+mips/idt/idtpci.c optional pci
+mips/idt/if_kr.c optional kr
+mips/idt/obio.c standard
+mips/idt/uart_cpu_rc32434.c optional uart
+mips/idt/uart_bus_rc32434.c optional uart
+mips/mips/intr_machdep.c standard
+mips/mips/tick.c standard
Property changes on: trunk/sys/mips/idt/files.idt
___________________________________________________________________
Added: mnbsd:nokeywords
## -0,0 +1 ##
+MidnightBSD=%H
\ No newline at end of property
Added: trunk/sys/mips/idt/idt_machdep.c
===================================================================
--- trunk/sys/mips/idt/idt_machdep.c (rev 0)
+++ trunk/sys/mips/idt/idt_machdep.c 2018-05-26 21:55:02 UTC (rev 9987)
@@ -0,0 +1,179 @@
+/* $MidnightBSD$ */
+/*-
+ * Copyright (C) 2007 by Oleksandr Tymoshenko. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+ * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+ * IN NO EVENT SHALL THE AUTHOR OR HIS RELATIVES BE LIABLE FOR ANY DIRECT,
+ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF MIND, USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
+ * THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * $Id: $
+ *
+ */
+
+#include <sys/cdefs.h>
+__FBSDID("$FreeBSD: stable/10/sys/mips/idt/idt_machdep.c 247297 2013-02-26 01:00:11Z attilio $");
+
+#include "opt_ddb.h"
+
+#include <sys/param.h>
+#include <sys/conf.h>
+#include <sys/kernel.h>
+#include <sys/systm.h>
+#include <sys/imgact.h>
+#include <sys/bio.h>
+#include <sys/buf.h>
+#include <sys/bus.h>
+#include <sys/cpu.h>
+#include <sys/cons.h>
+#include <sys/exec.h>
+#include <sys/ucontext.h>
+#include <sys/proc.h>
+#include <sys/kdb.h>
+#include <sys/ptrace.h>
+#include <sys/reboot.h>
+#include <sys/signalvar.h>
+#include <sys/sysent.h>
+#include <sys/sysproto.h>
+#include <sys/user.h>
+
+#include <vm/vm.h>
+#include <vm/vm_object.h>
+#include <vm/vm_page.h>
+
+#include <machine/cache.h>
+#include <machine/clock.h>
+#include <machine/cpu.h>
+#include <machine/cpuinfo.h>
+#include <machine/cpufunc.h>
+#include <machine/cpuregs.h>
+#include <machine/hwfunc.h>
+#include <machine/intr_machdep.h>
+#include <machine/locore.h>
+#include <machine/md_var.h>
+#include <machine/pte.h>
+#include <machine/sigframe.h>
+#include <machine/trap.h>
+#include <machine/vmparam.h>
+
+extern int *edata;
+extern int *end;
+
+void
+platform_cpu_init()
+{
+ /* Nothing special */
+}
+
+void
+platform_reset(void)
+{
+ volatile unsigned int * p = (void *)0xb8008000;
+ /*
+ * TODO: we should take care of TLB stuff here. Otherwise
+ * board does not boots properly next time
+ */
+
+ /* Write 0x8000_0001 to the Reset register */
+ *p = 0x80000001;
+
+ __asm __volatile("li $25, 0xbfc00000");
+ __asm __volatile("j $25");
+}
+
+void
+platform_start(__register_t a0, __register_t a1,
+ __register_t a2 __unused, __register_t a3 __unused)
+{
+ uint64_t platform_counter_freq;
+ vm_offset_t kernend;
+ int argc = a0;
+ char **argv = (char **)a1;
+ int i, mem;
+
+
+ /* clear the BSS and SBSS segments */
+ kernend = (vm_offset_t)&end;
+ memset(&edata, 0, kernend - (vm_offset_t)(&edata));
+
+ mips_postboot_fixup();
+
+ /* Initialize pcpu stuff */
+ mips_pcpu0_init();
+
+ /*
+ * Looking for mem=XXM argument
+ */
+ mem = 0; /* Just something to start with */
+ for (i=0; i < argc; i++) {
+ if (strncmp(argv[i], "mem=", 4) == 0) {
+ mem = strtol(argv[i] + 4, NULL, 0);
+ break;
+ }
+ }
+
+ bootverbose = 1;
+ if (mem > 0)
+ realmem = btoc(mem << 20);
+ else
+ realmem = btoc(32 << 20);
+
+ for (i = 0; i < 10; i++) {
+ phys_avail[i] = 0;
+ }
+
+ /* phys_avail regions are in bytes */
+ phys_avail[0] = MIPS_KSEG0_TO_PHYS(kernel_kseg0_end);
+ phys_avail[1] = ctob(realmem);
+
+ dump_avail[0] = phys_avail[0];
+ dump_avail[1] = phys_avail[1];
+
+ physmem = realmem;
+
+ /*
+ * ns8250 uart code uses DELAY so ticker should be inititalized
+ * before cninit. And tick_init_params refers to hz, so * init_param1
+ * should be called first.
+ */
+ init_param1();
+ /* TODO: parse argc,argv */
+ platform_counter_freq = 330000000UL;
+ mips_timer_init_params(platform_counter_freq, 1);
+ cninit();
+ /* Panic here, after cninit */
+ if (mem == 0)
+ panic("No mem=XX parameter in arguments");
+
+ printf("cmd line: ");
+ for (i=0; i < argc; i++)
+ printf("%s ", argv[i]);
+ printf("\n");
+
+ init_param2(physmem);
+ mips_cpu_init();
+ pmap_bootstrap();
+ mips_proc0_init();
+ mutex_init();
+ kdb_init();
+#ifdef KDB
+ if (boothowto & RB_KDB)
+ kdb_enter(KDB_WHY_BOOTFLAGS, "Boot flags requested debugger");
+#endif
+}
Property changes on: trunk/sys/mips/idt/idt_machdep.c
___________________________________________________________________
Added: svn:eol-style
## -0,0 +1 ##
+native
\ No newline at end of property
Added: svn:keywords
## -0,0 +1 ##
+MidnightBSD=%H
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+text/plain
\ No newline at end of property
Added: trunk/sys/mips/idt/idtpci.c
===================================================================
--- trunk/sys/mips/idt/idtpci.c (rev 0)
+++ trunk/sys/mips/idt/idtpci.c 2018-05-26 21:55:02 UTC (rev 9987)
@@ -0,0 +1,558 @@
+/* $MidnightBSD$ */
+/* $NetBSD: idtpci.c,v 1.1 2007/03/20 08:52:02 dyoung Exp $ */
+
+/*-
+ * Copyright (c) 2007 David Young.
+ * Copyright (c) 2007 Oleskandr Tymoshenko. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or
+ * without modification, are permitted provided that the following
+ * conditions are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above
+ * copyright notice, this list of conditions and the following
+ * disclaimer in the documentation and/or other materials provided
+ * with the distribution.
+ * 3. The name of the author may not be used to endorse or promote
+ * products derived from this software without specific prior
+ * written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
+ * PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY,
+ * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
+ * TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
+ * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ */
+/*-
+ * Copyright (c) 2006 Itronix Inc.
+ * All rights reserved.
+ *
+ * Written by Garrett D'Amore for Itronix Inc.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * 3. The name of Itronix Inc. may not be used to endorse
+ * or promote products derived from this software without specific
+ * prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ITRONIX INC. ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL ITRONIX INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <sys/cdefs.h>
+__FBSDID("$FreeBSD: stable/10/sys/mips/idt/idtpci.c 227843 2011-11-22 21:28:20Z marius $");
+
+#include <sys/param.h>
+#include <sys/systm.h>
+
+#include <sys/bus.h>
+#include <sys/interrupt.h>
+#include <sys/malloc.h>
+#include <sys/kernel.h>
+#include <sys/module.h>
+#include <sys/rman.h>
+
+#include <vm/vm.h>
+#include <vm/pmap.h>
+#include <vm/vm_extern.h>
+
+#include <machine/bus.h>
+#include <machine/cpu.h>
+#include <machine/pmap.h>
+
+#include <dev/pci/pcivar.h>
+#include <dev/pci/pcireg.h>
+
+#include <dev/pci/pcib_private.h>
+#include "pcib_if.h"
+
+#include <mips/idt/idtreg.h>
+
+#ifdef IDTPCI_DEBUG
+int idtpci_debug = 1;
+#define IDTPCI_DPRINTF(__fmt, ...) \
+do { \
+ if (idtpci_debug) \
+ printf((__fmt), __VA_ARGS__); \
+} while (/*CONSTCOND*/0)
+#else /* !IDTPCI_DEBUG */
+#define IDTPCI_DPRINTF(__fmt, ...) do { } while (/*CONSTCOND*/0)
+#endif /* IDTPCI_DEBUG */
+
+#define IDTPCI_TAG_BUS_MASK 0x007f0000
+#define IDTPCI_TAG_DEVICE_MASK 0x00007800
+#define IDTPCI_TAG_FUNCTION_MASK 0x00000300
+#define IDTPCI_TAG_REGISTER_MASK 0x0000007c
+
+#define IDTPCI_MAX_DEVICE
+
+#define REG_READ(o) *((volatile uint32_t *)MIPS_PHYS_TO_KSEG1(IDT_BASE_PCI + (o)))
+#define REG_WRITE(o,v) (REG_READ(o)) = (v)
+
+unsigned int korina_fixup[24] = {
+ 0x00000157, 0x00000000, 0x00003c04, 0x00000008, 0x18800001, 0x18000001,
+ 0x48000008, 0x00000000, 0x00000000, 0x00000000, 0x011d0214, 0x00000000,
+ 0x00000000, 0x00000000, 0x38080101, 0x00008080, 0x00000d6e, 0x00000000,
+ 0x00000051, 0x00000000, 0x00000055, 0x18000000, 0x00000000, 0x00000000
+};
+
+struct idtpci_softc {
+ device_t sc_dev;
+
+ int sc_busno;
+ struct rman sc_mem_rman[2];
+ struct rman sc_io_rman[2];
+ struct rman sc_irq_rman;
+};
+
+static uint32_t
+idtpci_make_addr(int bus, int slot, int func, int reg)
+{
+
+ return 0x80000000 | (bus << 16) | (slot << 11) | (func << 8) | reg;
+}
+
+static int
+idtpci_probe(device_t dev)
+{
+
+ return (0);
+}
+
+static int
+idtpci_attach(device_t dev)
+{
+ int busno = 0;
+ struct idtpci_softc *sc = device_get_softc(dev);
+ unsigned int pci_data, force_endianess = 0;
+ int i;
+ bus_addr_t addr;
+
+ sc->sc_dev = dev;
+ sc->sc_busno = busno;
+
+ /* TODO: Check for host mode */
+
+ /* Enabled PCI, IG mode, EAP mode */
+ REG_WRITE(IDT_PCI_CNTL, IDT_PCI_CNTL_IGM | IDT_PCI_CNTL_EAP |
+ IDT_PCI_CNTL_EN);
+ /* Wait while "Reset in progress bit" set */
+ while(1) {
+ pci_data = REG_READ(IDT_PCI_STATUS);
+ if((pci_data & IDT_PCI_STATUS_RIP) == 0)
+ break;
+ }
+
+ /* Reset status register */
+ REG_WRITE(IDT_PCI_STATUS, 0);
+ /* Mask interrupts related to status register */
+ REG_WRITE(IDT_PCI_STATUS_MASK, 0xffffffff);
+
+ /* Disable PCI decoupled access */
+ REG_WRITE(IDT_PCI_DAC, 0);
+ /* Zero status and mask DA interrupts */
+ REG_WRITE(IDT_PCI_DAS, 0);
+ REG_WRITE(IDT_PCI_DASM, 0x7f);
+
+ /* Init PCI messaging unit */
+ /* Disable messaging interrupts */
+ REG_WRITE(IDT_PCI_IIC, 0);
+ REG_WRITE(IDT_PCI_IIM, 0xffffffff);
+ REG_WRITE(IDT_PCI_OIC, 0);
+ REG_WRITE(IDT_PCI_OIM, 0);
+
+#ifdef __MIPSEB__
+ force_endianess = IDT_PCI_LBA_FE;
+#endif
+
+ /* LBA0 -- memory window */
+ REG_WRITE(IDT_PCI_LBA0, IDT_PCIMEM0_BASE);
+ REG_WRITE(IDT_PCI_LBA0_MAP, IDT_PCIMEM0_BASE);
+ REG_WRITE(IDT_PCI_LBA0_CNTL, IDT_PCI_LBA_SIZE_16MB | force_endianess);
+ pci_data = REG_READ(IDT_PCI_LBA0_CNTL);
+
+ /* LBA1 -- memory window */
+ REG_WRITE(IDT_PCI_LBA1, IDT_PCIMEM1_BASE);
+ REG_WRITE(IDT_PCI_LBA1_MAP, IDT_PCIMEM1_BASE);
+ REG_WRITE(IDT_PCI_LBA1_CNTL, IDT_PCI_LBA_SIZE_256MB | force_endianess);
+ pci_data = REG_READ(IDT_PCI_LBA1_CNTL);
+
+ /* LBA2 -- IO window */
+ REG_WRITE(IDT_PCI_LBA2, IDT_PCIMEM2_BASE);
+ REG_WRITE(IDT_PCI_LBA2_MAP, IDT_PCIMEM2_BASE);
+ REG_WRITE(IDT_PCI_LBA2_CNTL, IDT_PCI_LBA_SIZE_4MB | IDT_PCI_LBA_MSI |
+ force_endianess);
+ pci_data = REG_READ(IDT_PCI_LBA2_CNTL);
+
+ /* LBA3 -- IO window */
+ REG_WRITE(IDT_PCI_LBA3, IDT_PCIMEM3_BASE);
+ REG_WRITE(IDT_PCI_LBA3_MAP, IDT_PCIMEM3_BASE);
+ REG_WRITE(IDT_PCI_LBA3_CNTL, IDT_PCI_LBA_SIZE_1MB | IDT_PCI_LBA_MSI |
+ force_endianess);
+ pci_data = REG_READ(IDT_PCI_LBA3_CNTL);
+
+
+ pci_data = REG_READ(IDT_PCI_CNTL) & ~IDT_PCI_CNTL_TNR;
+ REG_WRITE(IDT_PCI_CNTL, pci_data);
+ pci_data = REG_READ(IDT_PCI_CNTL);
+
+ /* Rewrite Target Control register with default values */
+ REG_WRITE(IDT_PCI_TC, (IDT_PCI_TC_DTIMER << 8) | IDT_PCI_TC_RTIMER);
+
+ /* Perform Korina fixup */
+ addr = idtpci_make_addr(0, 0, 0, 4);
+ for (i = 0; i < 24; i++) {
+
+ REG_WRITE(IDT_PCI_CFG_ADDR, addr);
+ REG_WRITE(IDT_PCI_CFG_DATA, korina_fixup[i]);
+ __asm__ volatile ("sync");
+
+ REG_WRITE(IDT_PCI_CFG_ADDR, 0);
+ REG_WRITE(IDT_PCI_CFG_DATA, 0);
+ addr += 4;
+ }
+
+ /* Use KSEG1 to access IO ports for it is uncached */
+ sc->sc_io_rman[0].rm_type = RMAN_ARRAY;
+ sc->sc_io_rman[0].rm_descr = "IDTPCI I/O Ports window 1";
+ if (rman_init(&sc->sc_io_rman[0]) != 0 ||
+ rman_manage_region(&sc->sc_io_rman[0],
+ IDT_PCIMEM2_BASE, IDT_PCIMEM2_BASE + IDT_PCIMEM2_SIZE - 1) != 0) {
+ panic("idtpci_attach: failed to set up I/O rman");
+ }
+
+ sc->sc_io_rman[1].rm_type = RMAN_ARRAY;
+ sc->sc_io_rman[1].rm_descr = "IDTPCI I/O Ports window 2";
+ if (rman_init(&sc->sc_io_rman[1]) != 0 ||
+ rman_manage_region(&sc->sc_io_rman[1],
+ IDT_PCIMEM3_BASE, IDT_PCIMEM3_BASE + IDT_PCIMEM3_SIZE - 1) != 0) {
+ panic("idtpci_attach: failed to set up I/O rman");
+ }
+
+ /* Use KSEG1 to access PCI memory for it is uncached */
+ sc->sc_mem_rman[0].rm_type = RMAN_ARRAY;
+ sc->sc_mem_rman[0].rm_descr = "IDTPCI PCI Memory window 1";
+ if (rman_init(&sc->sc_mem_rman[0]) != 0 ||
+ rman_manage_region(&sc->sc_mem_rman[0],
+ IDT_PCIMEM0_BASE, IDT_PCIMEM0_BASE + IDT_PCIMEM0_SIZE) != 0) {
+ panic("idtpci_attach: failed to set up memory rman");
+ }
+
+ sc->sc_mem_rman[1].rm_type = RMAN_ARRAY;
+ sc->sc_mem_rman[1].rm_descr = "IDTPCI PCI Memory window 2";
+ if (rman_init(&sc->sc_mem_rman[1]) != 0 ||
+ rman_manage_region(&sc->sc_mem_rman[1],
+ IDT_PCIMEM1_BASE, IDT_PCIMEM1_BASE + IDT_PCIMEM1_SIZE) != 0) {
+ panic("idtpci_attach: failed to set up memory rman");
+ }
+
+ sc->sc_irq_rman.rm_type = RMAN_ARRAY;
+ sc->sc_irq_rman.rm_descr = "IDTPCI PCI IRQs";
+ if (rman_init(&sc->sc_irq_rman) != 0 ||
+ rman_manage_region(&sc->sc_irq_rman, PCI_IRQ_BASE,
+ PCI_IRQ_END) != 0)
+ panic("idtpci_attach: failed to set up IRQ rman");
+
+ device_add_child(dev, "pci", busno);
+ return (bus_generic_attach(dev));
+}
+
+static int
+idtpci_maxslots(device_t dev)
+{
+
+ return (PCI_SLOTMAX);
+}
+
+static uint32_t
+idtpci_read_config(device_t dev, u_int bus, u_int slot, u_int func, u_int reg,
+ int bytes)
+{
+ uint32_t data;
+ uint32_t shift, mask;
+ bus_addr_t addr;
+
+ IDTPCI_DPRINTF("%s: tag (%x, %x, %x) reg %d(%d)\n", __func__,
+ bus, slot, func, reg, bytes);
+
+ addr = idtpci_make_addr(bus, slot, func, reg);
+
+ REG_WRITE(IDT_PCI_CFG_ADDR, addr);
+ data = REG_READ(IDT_PCI_CFG_DATA);
+
+ switch (reg % 4) {
+ case 3:
+ shift = 24;
+ break;
+ case 2:
+ shift = 16;
+ break;
+ case 1:
+ shift = 8;
+ break;
+ default:
+ shift = 0;
+ break;
+ }
+
+ switch (bytes) {
+ case 1:
+ mask = 0xff;
+ data = (data >> shift) & mask;
+ break;
+ case 2:
+ mask = 0xffff;
+ if (reg % 4 == 0)
+ data = data & mask;
+ else
+ data = (data >> 16) & mask;
+ break;
+ case 4:
+ break;
+ default:
+ panic("%s: wrong bytes count", __func__);
+ break;
+ }
+
+ __asm__ volatile ("sync");
+ IDTPCI_DPRINTF("%s: read 0x%x\n", __func__, data);
+
+ return (data);
+}
+
+static void
+idtpci_write_config(device_t dev, u_int bus, u_int slot, u_int func, u_int reg,
+ uint32_t data, int bytes)
+{
+ bus_addr_t addr;
+ uint32_t reg_data;
+ uint32_t shift, mask;
+
+ IDTPCI_DPRINTF("%s: tag (%x, %x, %x) reg %d(%d) data %08x\n", __func__,
+ bus, slot, func, reg, bytes, data);
+
+ if (bytes != 4) {
+ reg_data = idtpci_read_config(dev, bus, slot, func, reg, 4);
+
+ switch (reg % 4) {
+ case 3:
+ shift = 24;
+ break;
+ case 2:
+ shift = 16;
+ break;
+ case 1:
+ shift = 8;
+ break;
+ default:
+ shift = 0;
+ break;
+ }
+
+ switch (bytes) {
+ case 1:
+ mask = 0xff;
+ data = (reg_data & ~ (mask << shift)) | (data << shift);
+ break;
+ case 2:
+ mask = 0xffff;
+ if (reg % 4 == 0)
+ data = (reg_data & ~mask) | data;
+ else
+ data = (reg_data & ~ (mask << shift)) |
+ (data << shift);
+ break;
+ case 4:
+ break;
+ default:
+ panic("%s: wrong bytes count", __func__);
+ break;
+ }
+ }
+
+ addr = idtpci_make_addr(bus, slot, func, reg);
+
+
+ REG_WRITE(IDT_PCI_CFG_ADDR, addr);
+ REG_WRITE(IDT_PCI_CFG_DATA, data);
+ __asm__ volatile ("sync");
+
+ REG_WRITE(IDT_PCI_CFG_ADDR, 0);
+ REG_WRITE(IDT_PCI_CFG_DATA, 0);
+}
+
+static int
+idtpci_route_interrupt(device_t pcib, device_t device, int pin)
+{
+ static int idt_pci_table[2][12] =
+ {
+ { 0, 0, 2, 3, 2, 3, 0, 0, 0, 0, 0, 1 },
+ { 0, 0, 1, 3, 0, 2, 1, 3, 0, 2, 1, 3 }
+ };
+ int dev, bus, irq;
+
+ dev = pci_get_slot(device);
+ bus = pci_get_bus(device);
+ if (bootverbose)
+ device_printf(pcib, "routing pin %d for %s\n", pin,
+ device_get_nameunit(device));
+ if (bus >= 0 && bus <= 1 &&
+ dev >= 0 && dev <= 11) {
+ irq = IP_IRQ(6, idt_pci_table[bus][dev] + 4);
+ if (bootverbose)
+ printf("idtpci: %d/%d/%d -> IRQ%d\n",
+ pci_get_bus(device), dev, pci_get_function(device),
+ irq);
+ return (irq);
+ } else
+ printf("idtpci: no mapping for %d/%d/%d\n",
+ pci_get_bus(device), dev, pci_get_function(device));
+
+ return (-1);
+}
+
+static int
+idtpci_read_ivar(device_t dev, device_t child, int which, uintptr_t *result)
+{
+ struct idtpci_softc *sc = device_get_softc(dev);
+
+ switch (which) {
+ case PCIB_IVAR_DOMAIN:
+ *result = 0;
+ return (0);
+ case PCIB_IVAR_BUS:
+ *result = sc->sc_busno;
+ return (0);
+ }
+
+ return (ENOENT);
+}
+
+static int
+idtpci_write_ivar(device_t dev, device_t child, int which, uintptr_t result)
+{
+ struct idtpci_softc * sc = device_get_softc(dev);
+
+ switch (which) {
+ case PCIB_IVAR_BUS:
+ sc->sc_busno = result;
+ return (0);
+ }
+ return (ENOENT);
+}
+
+static struct resource *
+idtpci_alloc_resource(device_t bus, device_t child, int type, int *rid,
+ u_long start, u_long end, u_long count, u_int flags)
+{
+
+ struct idtpci_softc *sc = device_get_softc(bus);
+ struct resource *rv = NULL;
+ struct rman *rm1, *rm2;
+
+ switch (type) {
+ case SYS_RES_IRQ:
+ rm1 = &sc->sc_irq_rman;
+ rm2 = NULL;
+ break;
+ case SYS_RES_MEMORY:
+ rm1 = &sc->sc_mem_rman[0];
+ rm2 = &sc->sc_mem_rman[1];
+ break;
+ case SYS_RES_IOPORT:
+ rm1 = &sc->sc_io_rman[0];
+ rm2 = &sc->sc_io_rman[1];
+ break;
+ default:
+ return (NULL);
+ }
+
+ rv = rman_reserve_resource(rm1, start, end, count, flags, child);
+
+ /* Try second window if it exists */
+ if ((rv == NULL) && (rm2 != NULL))
+ rv = rman_reserve_resource(rm2, start, end, count, flags,
+ child);
+
+ if (rv == NULL)
+ return (NULL);
+
+ rman_set_rid(rv, *rid);
+
+ if (flags & RF_ACTIVE) {
+ if (bus_activate_resource(child, type, *rid, rv)) {
+ rman_release_resource(rv);
+ return (NULL);
+ }
+ }
+
+ return (rv);
+}
+
+static int
+idtpci_teardown_intr(device_t dev, device_t child, struct resource *res,
+ void *cookie)
+{
+
+ return (intr_event_remove_handler(cookie));
+}
+
+static device_method_t idtpci_methods[] = {
+ /* Device interface */
+ DEVMETHOD(device_probe, idtpci_probe),
+ DEVMETHOD(device_attach, idtpci_attach),
+ DEVMETHOD(device_shutdown, bus_generic_shutdown),
+ DEVMETHOD(device_suspend, bus_generic_suspend),
+ DEVMETHOD(device_resume, bus_generic_resume),
+
+ /* Bus interface */
+ DEVMETHOD(bus_read_ivar, idtpci_read_ivar),
+ DEVMETHOD(bus_write_ivar, idtpci_write_ivar),
+ DEVMETHOD(bus_alloc_resource, idtpci_alloc_resource),
+ DEVMETHOD(bus_release_resource, bus_generic_release_resource),
+ DEVMETHOD(bus_activate_resource, bus_generic_activate_resource),
+ DEVMETHOD(bus_deactivate_resource, bus_generic_deactivate_resource),
+ DEVMETHOD(bus_setup_intr, bus_generic_setup_intr),
+ DEVMETHOD(bus_teardown_intr, idtpci_teardown_intr),
+
+ /* pcib interface */
+ DEVMETHOD(pcib_maxslots, idtpci_maxslots),
+ DEVMETHOD(pcib_read_config, idtpci_read_config),
+ DEVMETHOD(pcib_write_config, idtpci_write_config),
+ DEVMETHOD(pcib_route_interrupt, idtpci_route_interrupt),
+
+ DEVMETHOD_END
+};
+
+static driver_t idtpci_driver = {
+ "pcib",
+ idtpci_methods,
+ sizeof(struct idtpci_softc),
+};
+
+static devclass_t idtpci_devclass;
+
+DRIVER_MODULE(idtpci, obio, idtpci_driver, idtpci_devclass, 0, 0);
Property changes on: trunk/sys/mips/idt/idtpci.c
___________________________________________________________________
Added: svn:eol-style
## -0,0 +1 ##
+native
\ No newline at end of property
Added: svn:keywords
## -0,0 +1 ##
+MidnightBSD=%H
\ No newline at end of property
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## -0,0 +1 ##
+text/plain
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Added: trunk/sys/mips/idt/idtreg.h
===================================================================
--- trunk/sys/mips/idt/idtreg.h (rev 0)
+++ trunk/sys/mips/idt/idtreg.h 2018-05-26 21:55:02 UTC (rev 9987)
@@ -0,0 +1,154 @@
+/* $MidnightBSD$ */
+/*-
+ * Copyright (C) 2007 by Oleksandr Tymoshenko. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+ * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+ * IN NO EVENT SHALL THE AUTHOR OR HIS RELATIVES BE LIABLE FOR ANY DIRECT,
+ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF MIND, USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
+ * THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * $FreeBSD: stable/10/sys/mips/idt/idtreg.h 202175 2010-01-12 21:36:08Z imp $
+ *
+ */
+#ifndef __IDTREG_H__
+#define __IDTREG_H__
+
+/* Interrupt controller */
+#define IDT_BASE_ICU 0x18038000
+#define ICU_IPEND2 0x00
+#define ICU_ITEST2 0x04
+#define ICU_IMASK2 0x08
+#define ICU_IPEND3 0x0C
+#define ICU_ITEST3 0x10
+#define ICU_IMASK3 0x14
+#define ICU_IPEND4 0x18
+#define ICU_ITEST4 0x1c
+#define ICU_IMASK4 0x20
+#define ICU_IPEND5 0x24
+#define ICU_ITEST5 0x28
+#define ICU_IMASK5 0x2c
+#define ICU_IPEND6 0x30
+#define ICU_ITEST6 0x34
+#define ICU_IMASK6 0x38
+#define ICU_NMIPS 0x3c
+
+#define IDT_BASE_GPIO 0x18050000
+#define GPIO_FUNC 0x00
+#define GPIO_CFG 0x04
+#define GPIO_DATA 0x08
+#define GPIO_ILEVEL 0x0C
+#define GPIO_ISTAT 0x10
+#define GPIO_NMIEN 0x14
+
+#define IDT_BASE_UART0 0x18058000
+
+/* PCI controller */
+#define IDT_BASE_PCI 0x18080000
+#define IDT_PCI_CNTL 0x00
+#define IDT_PCI_CNTL_EN 0x001
+#define IDT_PCI_CNTL_TNR 0x002
+#define IDT_PCI_CNTL_SCE 0x004
+#define IDT_PCI_CNTL_IEN 0x008
+#define IDT_PCI_CNTL_AAA 0x010
+#define IDT_PCI_CNTL_EAP 0x020
+#define IDT_PCI_CNTL_IGM 0x200
+#define IDT_PCI_STATUS 0x04
+#define IDT_PCI_STATUS_RIP 0x20000
+#define IDT_PCI_STATUS_MASK 0x08
+#define IDT_PCI_CFG_ADDR 0x0C
+#define IDT_PCI_CFG_DATA 0x10
+/* LBA stuff */
+#define IDT_PCI_LBA0 0x14
+#define IDT_PCI_LBA0_CNTL 0x18
+#define IDT_PCI_LBA_MSI 0x01
+#define IDT_PCI_LBA_SIZE_1MB (0x14 << 2)
+#define IDT_PCI_LBA_SIZE_2MB (0x15 << 2)
+#define IDT_PCI_LBA_SIZE_4MB (0x16 << 2)
+#define IDT_PCI_LBA_SIZE_8MB (0x17 << 2)
+#define IDT_PCI_LBA_SIZE_16MB (0x18 << 2)
+#define IDT_PCI_LBA_SIZE_32MB (0x19 << 2)
+#define IDT_PCI_LBA_SIZE_64MB (0x1A << 2)
+#define IDT_PCI_LBA_SIZE_128MB (0x1B << 2)
+#define IDT_PCI_LBA_SIZE_256MB (0x1C << 2)
+#define IDT_PCI_LBA_FE 0x80
+#define IDT_PCI_LBA_RT 0x100
+#define IDT_PCI_LBA0_MAP 0x1C
+#define IDT_PCI_LBA1 0x20
+#define IDT_PCI_LBA1_CNTL 0x24
+#define IDT_PCI_LBA1_MAP 0x28
+#define IDT_PCI_LBA2 0x2C
+#define IDT_PCI_LBA2_CNTL 0x30
+#define IDT_PCI_LBA2_MAP 0x34
+#define IDT_PCI_LBA3 0x38
+#define IDT_PCI_LBA3_CNTL 0x3C
+#define IDT_PCI_LBA3_MAP 0x40
+/* decoupled registers */
+#define IDT_PCI_DAC 0x44
+#define IDT_PCI_DAS 0x48
+#define IDT_PCI_DASM 0x4C
+
+#define IDT_PCI_TC 0x5C
+#define IDT_PCI_TC_RTIMER 0x10
+#define IDT_PCI_TC_DTIMER 0x08
+/* Messaging unit of PCI controller */
+#define IDT_PCI_IIC 0x8024
+#define IDT_PCI_IIM 0x8028
+#define IDT_PCI_OIC 0x8030
+#define IDT_PCI_OIM 0x8034
+
+/* PCI-related stuff */
+#define IDT_PCIMEM0_BASE 0x50000000
+#define IDT_PCIMEM0_SIZE 0x01000000
+
+#define IDT_PCIMEM1_BASE 0x60000000
+#define IDT_PCIMEM1_SIZE 0x10000000
+
+#define IDT_PCIMEM2_BASE 0x18C00000
+#define IDT_PCIMEM2_SIZE 0x00400000
+
+#define IDT_PCIMEM3_BASE 0x18800000
+#define IDT_PCIMEM3_SIZE 0x00100000
+
+/* Interrupts-related stuff */
+#define IRQ_BASE 8
+/* Convert <IPbit, irq_offset> pair to IRQ number */
+#define IP_IRQ(IPbit, offset) ((IPbit - 2) * 32 + (offset) + IRQ_BASE)
+/* The last one available IRQ */
+#define IRQ_END IP_IRQ(6, 31)
+#define ICU_GROUP_REG_OFFSET 0x0C
+
+#define ICU_IP(irq) (((irq) - IRQ_BASE) & 0x1f)
+#define ICU_IP_BIT(irq) (1 << ICU_IP(irq))
+#define ICU_GROUP(irq) (((irq) - IRQ_BASE) >> 5)
+
+#define ICU_GROUP_MASK_REG(group) \
+ (ICU_IMASK2 + ((((group) - 2) * ICU_GROUP_REG_OFFSET)))
+#define ICU_GROUP_IPEND_REG(group) \
+ (ICU_IPEND2 + ((((group) - 2) * ICU_GROUP_REG_OFFSET)))
+
+#define ICU_IRQ_MASK_REG(irq) \
+ (ICU_IMASK2 + ((ICU_GROUP(irq) * ICU_GROUP_REG_OFFSET)))
+#define ICU_IRQ_IPEND_REG(irq) \
+ (ICU_IPEND2 + ((ICU_GROUP(irq) * ICU_GROUP_REG_OFFSET)))
+
+#define PCI_IRQ_BASE IP_IRQ(6, 4)
+#define PCI_IRQ_END IP_IRQ(6, 7)
+
+#endif /* __IDTREG_H__ */
+
Property changes on: trunk/sys/mips/idt/idtreg.h
___________________________________________________________________
Added: svn:eol-style
## -0,0 +1 ##
+native
\ No newline at end of property
Added: svn:keywords
## -0,0 +1 ##
+MidnightBSD=%H
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+text/plain
\ No newline at end of property
Added: trunk/sys/mips/idt/if_kr.c
===================================================================
--- trunk/sys/mips/idt/if_kr.c (rev 0)
+++ trunk/sys/mips/idt/if_kr.c 2018-05-26 21:55:02 UTC (rev 9987)
@@ -0,0 +1,1611 @@
+/* $MidnightBSD$ */
+/*-
+ * Copyright (C) 2007
+ * Oleksandr Tymoshenko <gonzo at freebsd.org>. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+ * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+ * IN NO EVENT SHALL THE AUTHOR OR HIS RELATIVES BE LIABLE FOR ANY DIRECT,
+ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF MIND, USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
+ * THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * $Id: $
+ *
+ */
+
+#include <sys/cdefs.h>
+__FBSDID("$FreeBSD: stable/10/sys/mips/idt/if_kr.c 243882 2012-12-05 08:04:20Z glebius $");
+
+/*
+ * RC32434 Ethernet interface driver
+ */
+#include <sys/param.h>
+#include <sys/endian.h>
+#include <sys/systm.h>
+#include <sys/sockio.h>
+#include <sys/mbuf.h>
+#include <sys/malloc.h>
+#include <sys/kernel.h>
+#include <sys/module.h>
+#include <sys/socket.h>
+#include <sys/taskqueue.h>
+
+#include <net/if.h>
+#include <net/if_arp.h>
+#include <net/ethernet.h>
+#include <net/if_dl.h>
+#include <net/if_media.h>
+#include <net/if_types.h>
+
+#include <net/bpf.h>
+
+#include <machine/bus.h>
+#include <machine/resource.h>
+#include <sys/bus.h>
+#include <sys/rman.h>
+
+#include <dev/mii/mii.h>
+#include <dev/mii/miivar.h>
+
+#include <dev/pci/pcireg.h>
+#include <dev/pci/pcivar.h>
+
+MODULE_DEPEND(kr, ether, 1, 1, 1);
+MODULE_DEPEND(kr, miibus, 1, 1, 1);
+
+#include "miibus_if.h"
+
+#include <mips/idt/if_krreg.h>
+
+#define KR_DEBUG
+
+static int kr_attach(device_t);
+static int kr_detach(device_t);
+static int kr_ifmedia_upd(struct ifnet *);
+static void kr_ifmedia_sts(struct ifnet *, struct ifmediareq *);
+static int kr_ioctl(struct ifnet *, u_long, caddr_t);
+static void kr_init(void *);
+static void kr_init_locked(struct kr_softc *);
+static void kr_link_task(void *, int);
+static int kr_miibus_readreg(device_t, int, int);
+static void kr_miibus_statchg(device_t);
+static int kr_miibus_writereg(device_t, int, int, int);
+static int kr_probe(device_t);
+static void kr_reset(struct kr_softc *);
+static int kr_resume(device_t);
+static int kr_rx_ring_init(struct kr_softc *);
+static int kr_tx_ring_init(struct kr_softc *);
+static int kr_shutdown(device_t);
+static void kr_start(struct ifnet *);
+static void kr_start_locked(struct ifnet *);
+static void kr_stop(struct kr_softc *);
+static int kr_suspend(device_t);
+
+static void kr_rx(struct kr_softc *);
+static void kr_tx(struct kr_softc *);
+static void kr_rx_intr(void *);
+static void kr_tx_intr(void *);
+static void kr_rx_und_intr(void *);
+static void kr_tx_ovr_intr(void *);
+static void kr_tick(void *);
+
+static void kr_dmamap_cb(void *, bus_dma_segment_t *, int, int);
+static int kr_dma_alloc(struct kr_softc *);
+static void kr_dma_free(struct kr_softc *);
+static int kr_newbuf(struct kr_softc *, int);
+static __inline void kr_fixup_rx(struct mbuf *);
+
+static device_method_t kr_methods[] = {
+ /* Device interface */
+ DEVMETHOD(device_probe, kr_probe),
+ DEVMETHOD(device_attach, kr_attach),
+ DEVMETHOD(device_detach, kr_detach),
+ DEVMETHOD(device_suspend, kr_suspend),
+ DEVMETHOD(device_resume, kr_resume),
+ DEVMETHOD(device_shutdown, kr_shutdown),
+
+ /* MII interface */
+ DEVMETHOD(miibus_readreg, kr_miibus_readreg),
+ DEVMETHOD(miibus_writereg, kr_miibus_writereg),
+ DEVMETHOD(miibus_statchg, kr_miibus_statchg),
+
+ DEVMETHOD_END
+};
+
+static driver_t kr_driver = {
+ "kr",
+ kr_methods,
+ sizeof(struct kr_softc)
+};
+
+static devclass_t kr_devclass;
+
+DRIVER_MODULE(kr, obio, kr_driver, kr_devclass, 0, 0);
+DRIVER_MODULE(miibus, kr, miibus_driver, miibus_devclass, 0, 0);
+
+static int
+kr_probe(device_t dev)
+{
+
+ device_set_desc(dev, "RC32434 Ethernet interface");
+ return (0);
+}
+
+static int
+kr_attach(device_t dev)
+{
+ uint8_t eaddr[ETHER_ADDR_LEN];
+ struct ifnet *ifp;
+ struct kr_softc *sc;
+ int error = 0, rid;
+ int unit;
+
+ sc = device_get_softc(dev);
+ unit = device_get_unit(dev);
+ sc->kr_dev = dev;
+
+ mtx_init(&sc->kr_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK,
+ MTX_DEF);
+ callout_init_mtx(&sc->kr_stat_callout, &sc->kr_mtx, 0);
+ TASK_INIT(&sc->kr_link_task, 0, kr_link_task, sc);
+ pci_enable_busmaster(dev);
+
+ /* Map control/status registers. */
+ sc->kr_rid = 0;
+ sc->kr_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &sc->kr_rid,
+ RF_ACTIVE);
+
+ if (sc->kr_res == NULL) {
+ device_printf(dev, "couldn't map memory\n");
+ error = ENXIO;
+ goto fail;
+ }
+
+ sc->kr_btag = rman_get_bustag(sc->kr_res);
+ sc->kr_bhandle = rman_get_bushandle(sc->kr_res);
+
+ /* Allocate interrupts */
+ rid = 0;
+ sc->kr_rx_irq = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, KR_RX_IRQ,
+ KR_RX_IRQ, 1, RF_SHAREABLE | RF_ACTIVE);
+
+ if (sc->kr_rx_irq == NULL) {
+ device_printf(dev, "couldn't map rx interrupt\n");
+ error = ENXIO;
+ goto fail;
+ }
+
+ rid = 0;
+ sc->kr_tx_irq = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, KR_TX_IRQ,
+ KR_TX_IRQ, 1, RF_SHAREABLE | RF_ACTIVE);
+
+ if (sc->kr_tx_irq == NULL) {
+ device_printf(dev, "couldn't map tx interrupt\n");
+ error = ENXIO;
+ goto fail;
+ }
+
+ rid = 0;
+ sc->kr_rx_und_irq = bus_alloc_resource(dev, SYS_RES_IRQ, &rid,
+ KR_RX_UND_IRQ, KR_RX_UND_IRQ, 1, RF_SHAREABLE | RF_ACTIVE);
+
+ if (sc->kr_rx_und_irq == NULL) {
+ device_printf(dev, "couldn't map rx underrun interrupt\n");
+ error = ENXIO;
+ goto fail;
+ }
+
+ rid = 0;
+ sc->kr_tx_ovr_irq = bus_alloc_resource(dev, SYS_RES_IRQ, &rid,
+ KR_TX_OVR_IRQ, KR_TX_OVR_IRQ, 1, RF_SHAREABLE | RF_ACTIVE);
+
+ if (sc->kr_tx_ovr_irq == NULL) {
+ device_printf(dev, "couldn't map tx overrun interrupt\n");
+ error = ENXIO;
+ goto fail;
+ }
+
+ /* Allocate ifnet structure. */
+ ifp = sc->kr_ifp = if_alloc(IFT_ETHER);
+
+ if (ifp == NULL) {
+ device_printf(dev, "couldn't allocate ifnet structure\n");
+ error = ENOSPC;
+ goto fail;
+ }
+ ifp->if_softc = sc;
+ if_initname(ifp, device_get_name(dev), device_get_unit(dev));
+ ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
+ ifp->if_ioctl = kr_ioctl;
+ ifp->if_start = kr_start;
+ ifp->if_init = kr_init;
+
+ /* XXX: add real size */
+ IFQ_SET_MAXLEN(&ifp->if_snd, 9);
+ ifp->if_snd.ifq_maxlen = 9;
+ IFQ_SET_READY(&ifp->if_snd);
+
+ ifp->if_capenable = ifp->if_capabilities;
+
+ eaddr[0] = 0x00;
+ eaddr[1] = 0x0C;
+ eaddr[2] = 0x42;
+ eaddr[3] = 0x09;
+ eaddr[4] = 0x5E;
+ eaddr[5] = 0x6B;
+
+ if (kr_dma_alloc(sc) != 0) {
+ error = ENXIO;
+ goto fail;
+ }
+
+ /* TODO: calculate prescale */
+ CSR_WRITE_4(sc, KR_ETHMCP, (165000000 / (1250000 + 1)) & ~1);
+
+ CSR_WRITE_4(sc, KR_MIIMCFG, KR_MIIMCFG_R);
+ DELAY(1000);
+ CSR_WRITE_4(sc, KR_MIIMCFG, 0);
+
+ /* Do MII setup. */
+ error = mii_attach(dev, &sc->kr_miibus, ifp, kr_ifmedia_upd,
+ kr_ifmedia_sts, BMSR_DEFCAPMASK, MII_PHY_ANY, MII_OFFSET_ANY, 0);
+ if (error != 0) {
+ device_printf(dev, "attaching PHYs failed\n");
+ goto fail;
+ }
+
+ /* Call MI attach routine. */
+ ether_ifattach(ifp, eaddr);
+
+ /* Hook interrupt last to avoid having to lock softc */
+ error = bus_setup_intr(dev, sc->kr_rx_irq, INTR_TYPE_NET | INTR_MPSAFE,
+ NULL, kr_rx_intr, sc, &sc->kr_rx_intrhand);
+
+ if (error) {
+ device_printf(dev, "couldn't set up rx irq\n");
+ ether_ifdetach(ifp);
+ goto fail;
+ }
+
+ error = bus_setup_intr(dev, sc->kr_tx_irq, INTR_TYPE_NET | INTR_MPSAFE,
+ NULL, kr_tx_intr, sc, &sc->kr_tx_intrhand);
+
+ if (error) {
+ device_printf(dev, "couldn't set up tx irq\n");
+ ether_ifdetach(ifp);
+ goto fail;
+ }
+
+ error = bus_setup_intr(dev, sc->kr_rx_und_irq,
+ INTR_TYPE_NET | INTR_MPSAFE, NULL, kr_rx_und_intr, sc,
+ &sc->kr_rx_und_intrhand);
+
+ if (error) {
+ device_printf(dev, "couldn't set up rx underrun irq\n");
+ ether_ifdetach(ifp);
+ goto fail;
+ }
+
+ error = bus_setup_intr(dev, sc->kr_tx_ovr_irq,
+ INTR_TYPE_NET | INTR_MPSAFE, NULL, kr_tx_ovr_intr, sc,
+ &sc->kr_tx_ovr_intrhand);
+
+ if (error) {
+ device_printf(dev, "couldn't set up tx overrun irq\n");
+ ether_ifdetach(ifp);
+ goto fail;
+ }
+
+fail:
+ if (error)
+ kr_detach(dev);
+
+ return (error);
+}
+
+static int
+kr_detach(device_t dev)
+{
+ struct kr_softc *sc = device_get_softc(dev);
+ struct ifnet *ifp = sc->kr_ifp;
+
+ KASSERT(mtx_initialized(&sc->kr_mtx), ("vr mutex not initialized"));
+
+ /* These should only be active if attach succeeded */
+ if (device_is_attached(dev)) {
+ KR_LOCK(sc);
+ sc->kr_detach = 1;
+ kr_stop(sc);
+ KR_UNLOCK(sc);
+ taskqueue_drain(taskqueue_swi, &sc->kr_link_task);
+ ether_ifdetach(ifp);
+ }
+ if (sc->kr_miibus)
+ device_delete_child(dev, sc->kr_miibus);
+ bus_generic_detach(dev);
+
+ if (sc->kr_rx_intrhand)
+ bus_teardown_intr(dev, sc->kr_rx_irq, sc->kr_rx_intrhand);
+ if (sc->kr_rx_irq)
+ bus_release_resource(dev, SYS_RES_IRQ, 0, sc->kr_rx_irq);
+ if (sc->kr_tx_intrhand)
+ bus_teardown_intr(dev, sc->kr_tx_irq, sc->kr_tx_intrhand);
+ if (sc->kr_tx_irq)
+ bus_release_resource(dev, SYS_RES_IRQ, 0, sc->kr_tx_irq);
+ if (sc->kr_rx_und_intrhand)
+ bus_teardown_intr(dev, sc->kr_rx_und_irq,
+ sc->kr_rx_und_intrhand);
+ if (sc->kr_rx_und_irq)
+ bus_release_resource(dev, SYS_RES_IRQ, 0, sc->kr_rx_und_irq);
+ if (sc->kr_tx_ovr_intrhand)
+ bus_teardown_intr(dev, sc->kr_tx_ovr_irq,
+ sc->kr_tx_ovr_intrhand);
+ if (sc->kr_tx_ovr_irq)
+ bus_release_resource(dev, SYS_RES_IRQ, 0, sc->kr_tx_ovr_irq);
+
+ if (sc->kr_res)
+ bus_release_resource(dev, SYS_RES_MEMORY, sc->kr_rid,
+ sc->kr_res);
+
+ if (ifp)
+ if_free(ifp);
+
+ kr_dma_free(sc);
+
+ mtx_destroy(&sc->kr_mtx);
+
+ return (0);
+
+}
+
+static int
+kr_suspend(device_t dev)
+{
+
+ panic("%s", __func__);
+ return 0;
+}
+
+static int
+kr_resume(device_t dev)
+{
+
+ panic("%s", __func__);
+ return 0;
+}
+
+static int
+kr_shutdown(device_t dev)
+{
+ struct kr_softc *sc;
+
+ sc = device_get_softc(dev);
+
+ KR_LOCK(sc);
+ kr_stop(sc);
+ KR_UNLOCK(sc);
+
+ return (0);
+}
+
+static int
+kr_miibus_readreg(device_t dev, int phy, int reg)
+{
+ struct kr_softc * sc = device_get_softc(dev);
+ int i, result;
+
+ i = KR_MII_TIMEOUT;
+ while ((CSR_READ_4(sc, KR_MIIMIND) & KR_MIIMIND_BSY) && i)
+ i--;
+
+ if (i == 0)
+ device_printf(dev, "phy mii is busy %d:%d\n", phy, reg);
+
+ CSR_WRITE_4(sc, KR_MIIMADDR, (phy << 8) | reg);
+
+ i = KR_MII_TIMEOUT;
+ while ((CSR_READ_4(sc, KR_MIIMIND) & KR_MIIMIND_BSY) && i)
+ i--;
+
+ if (i == 0)
+ device_printf(dev, "phy mii is busy %d:%d\n", phy, reg);
+
+ CSR_WRITE_4(sc, KR_MIIMCMD, KR_MIIMCMD_RD);
+
+ i = KR_MII_TIMEOUT;
+ while ((CSR_READ_4(sc, KR_MIIMIND) & KR_MIIMIND_BSY) && i)
+ i--;
+
+ if (i == 0)
+ device_printf(dev, "phy mii read is timed out %d:%d\n", phy,
+ reg);
+
+ if (CSR_READ_4(sc, KR_MIIMIND) & KR_MIIMIND_NV)
+ printf("phy mii readreg failed %d:%d: data not valid\n",
+ phy, reg);
+
+ result = CSR_READ_4(sc , KR_MIIMRDD);
+ CSR_WRITE_4(sc, KR_MIIMCMD, 0);
+
+ return (result);
+}
+
+static int
+kr_miibus_writereg(device_t dev, int phy, int reg, int data)
+{
+ struct kr_softc * sc = device_get_softc(dev);
+ int i;
+
+ i = KR_MII_TIMEOUT;
+ while ((CSR_READ_4(sc, KR_MIIMIND) & KR_MIIMIND_BSY) && i)
+ i--;
+
+ if (i == 0)
+ device_printf(dev, "phy mii is busy %d:%d\n", phy, reg);
+
+ CSR_WRITE_4(sc, KR_MIIMADDR, (phy << 8) | reg);
+
+ i = KR_MII_TIMEOUT;
+ while ((CSR_READ_4(sc, KR_MIIMIND) & KR_MIIMIND_BSY) && i)
+ i--;
+
+ if (i == 0)
+ device_printf(dev, "phy mii is busy %d:%d\n", phy, reg);
+
+ CSR_WRITE_4(sc, KR_MIIMWTD, data);
+
+ i = KR_MII_TIMEOUT;
+ while ((CSR_READ_4(sc, KR_MIIMIND) & KR_MIIMIND_BSY) && i)
+ i--;
+
+ if (i == 0)
+ device_printf(dev, "phy mii is busy %d:%d\n", phy, reg);
+
+ return (0);
+}
+
+static void
+kr_miibus_statchg(device_t dev)
+{
+ struct kr_softc *sc;
+
+ sc = device_get_softc(dev);
+ taskqueue_enqueue(taskqueue_swi, &sc->kr_link_task);
+}
+
+static void
+kr_link_task(void *arg, int pending)
+{
+ struct kr_softc *sc;
+ struct mii_data *mii;
+ struct ifnet *ifp;
+ /* int lfdx, mfdx; */
+
+ sc = (struct kr_softc *)arg;
+
+ KR_LOCK(sc);
+ mii = device_get_softc(sc->kr_miibus);
+ ifp = sc->kr_ifp;
+ if (mii == NULL || ifp == NULL ||
+ (ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) {
+ KR_UNLOCK(sc);
+ return;
+ }
+
+ if (mii->mii_media_status & IFM_ACTIVE) {
+ if (IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE)
+ sc->kr_link_status = 1;
+ } else
+ sc->kr_link_status = 0;
+
+ KR_UNLOCK(sc);
+}
+
+static void
+kr_reset(struct kr_softc *sc)
+{
+ int i;
+
+ CSR_WRITE_4(sc, KR_ETHINTFC, 0);
+
+ for (i = 0; i < KR_TIMEOUT; i++) {
+ DELAY(10);
+ if (!(CSR_READ_4(sc, KR_ETHINTFC) & ETH_INTFC_RIP))
+ break;
+ }
+
+ if (i == KR_TIMEOUT)
+ device_printf(sc->kr_dev, "reset time out\n");
+}
+
+static void
+kr_init(void *xsc)
+{
+ struct kr_softc *sc = xsc;
+
+ KR_LOCK(sc);
+ kr_init_locked(sc);
+ KR_UNLOCK(sc);
+}
+
+static void
+kr_init_locked(struct kr_softc *sc)
+{
+ struct ifnet *ifp = sc->kr_ifp;
+ struct mii_data *mii;
+
+ KR_LOCK_ASSERT(sc);
+
+ mii = device_get_softc(sc->kr_miibus);
+
+ kr_stop(sc);
+ kr_reset(sc);
+
+ CSR_WRITE_4(sc, KR_ETHINTFC, ETH_INTFC_EN);
+
+ /* Init circular RX list. */
+ if (kr_rx_ring_init(sc) != 0) {
+ device_printf(sc->kr_dev,
+ "initialization failed: no memory for rx buffers\n");
+ kr_stop(sc);
+ return;
+ }
+
+ /* Init tx descriptors. */
+ kr_tx_ring_init(sc);
+
+ KR_DMA_WRITE_REG(KR_DMA_RXCHAN, DMA_S, 0);
+ KR_DMA_WRITE_REG(KR_DMA_RXCHAN, DMA_NDPTR, 0);
+ KR_DMA_WRITE_REG(KR_DMA_RXCHAN, DMA_DPTR,
+ sc->kr_rdata.kr_rx_ring_paddr);
+
+
+ KR_DMA_CLEARBITS_REG(KR_DMA_RXCHAN, DMA_SM,
+ DMA_SM_H | DMA_SM_E | DMA_SM_D) ;
+
+ KR_DMA_WRITE_REG(KR_DMA_TXCHAN, DMA_S, 0);
+ KR_DMA_WRITE_REG(KR_DMA_TXCHAN, DMA_NDPTR, 0);
+ KR_DMA_WRITE_REG(KR_DMA_TXCHAN, DMA_DPTR, 0);
+ KR_DMA_CLEARBITS_REG(KR_DMA_TXCHAN, DMA_SM,
+ DMA_SM_F | DMA_SM_E);
+
+
+ /* Accept only packets destined for THIS Ethernet device address */
+ CSR_WRITE_4(sc, KR_ETHARC, 1);
+
+ /*
+ * Set all Ethernet address registers to the same initial values
+ * set all four addresses to 66-88-aa-cc-dd-ee
+ */
+ CSR_WRITE_4(sc, KR_ETHSAL0, 0x42095E6B);
+ CSR_WRITE_4(sc, KR_ETHSAH0, 0x0000000C);
+
+ CSR_WRITE_4(sc, KR_ETHSAL1, 0x42095E6B);
+ CSR_WRITE_4(sc, KR_ETHSAH1, 0x0000000C);
+
+ CSR_WRITE_4(sc, KR_ETHSAL2, 0x42095E6B);
+ CSR_WRITE_4(sc, KR_ETHSAH2, 0x0000000C);
+
+ CSR_WRITE_4(sc, KR_ETHSAL3, 0x42095E6B);
+ CSR_WRITE_4(sc, KR_ETHSAH3, 0x0000000C);
+
+ CSR_WRITE_4(sc, KR_ETHMAC2,
+ KR_ETH_MAC2_PEN | KR_ETH_MAC2_CEN | KR_ETH_MAC2_FD);
+
+ CSR_WRITE_4(sc, KR_ETHIPGT, KR_ETHIPGT_FULL_DUPLEX);
+ CSR_WRITE_4(sc, KR_ETHIPGR, 0x12); /* minimum value */
+
+ CSR_WRITE_4(sc, KR_MIIMCFG, KR_MIIMCFG_R);
+ DELAY(1000);
+ CSR_WRITE_4(sc, KR_MIIMCFG, 0);
+
+ /* TODO: calculate prescale */
+ CSR_WRITE_4(sc, KR_ETHMCP, (165000000 / (1250000 + 1)) & ~1);
+
+ /* FIFO Tx threshold level */
+ CSR_WRITE_4(sc, KR_ETHFIFOTT, 0x30);
+
+ CSR_WRITE_4(sc, KR_ETHMAC1, KR_ETH_MAC1_RE);
+
+ sc->kr_link_status = 0;
+ mii_mediachg(mii);
+
+ ifp->if_drv_flags |= IFF_DRV_RUNNING;
+ ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
+
+ callout_reset(&sc->kr_stat_callout, hz, kr_tick, sc);
+}
+
+static void
+kr_start(struct ifnet *ifp)
+{
+ struct kr_softc *sc;
+
+ sc = ifp->if_softc;
+
+ KR_LOCK(sc);
+ kr_start_locked(ifp);
+ KR_UNLOCK(sc);
+}
+
+/*
+ * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data
+ * pointers to the fragment pointers.
+ */
+static int
+kr_encap(struct kr_softc *sc, struct mbuf **m_head)
+{
+ struct kr_txdesc *txd;
+ struct kr_desc *desc, *prev_desc;
+ bus_dma_segment_t txsegs[KR_MAXFRAGS];
+ uint32_t link_addr;
+ int error, i, nsegs, prod, si, prev_prod;
+
+ KR_LOCK_ASSERT(sc);
+
+ prod = sc->kr_cdata.kr_tx_prod;
+ txd = &sc->kr_cdata.kr_txdesc[prod];
+ error = bus_dmamap_load_mbuf_sg(sc->kr_cdata.kr_tx_tag, txd->tx_dmamap,
+ *m_head, txsegs, &nsegs, BUS_DMA_NOWAIT);
+ if (error == EFBIG) {
+ panic("EFBIG");
+ } else if (error != 0)
+ return (error);
+ if (nsegs == 0) {
+ m_freem(*m_head);
+ *m_head = NULL;
+ return (EIO);
+ }
+
+ /* Check number of available descriptors. */
+ if (sc->kr_cdata.kr_tx_cnt + nsegs >= (KR_TX_RING_CNT - 1)) {
+ bus_dmamap_unload(sc->kr_cdata.kr_tx_tag, txd->tx_dmamap);
+ return (ENOBUFS);
+ }
+
+ txd->tx_m = *m_head;
+ bus_dmamap_sync(sc->kr_cdata.kr_tx_tag, txd->tx_dmamap,
+ BUS_DMASYNC_PREWRITE);
+
+ si = prod;
+
+ /*
+ * Make a list of descriptors for this packet. DMA controller will
+ * walk through it while kr_link is not zero. The last one should
+ * have COF flag set, to pickup next chain from NDPTR
+ */
+ prev_prod = prod;
+ desc = prev_desc = NULL;
+ for (i = 0; i < nsegs; i++) {
+ desc = &sc->kr_rdata.kr_tx_ring[prod];
+ desc->kr_ctl = KR_DMASIZE(txsegs[i].ds_len) | KR_CTL_IOF;
+ if (i == 0)
+ desc->kr_devcs = KR_DMATX_DEVCS_FD;
+ desc->kr_ca = txsegs[i].ds_addr;
+ desc->kr_link = 0;
+ /* link with previous descriptor */
+ if (prev_desc)
+ prev_desc->kr_link = KR_TX_RING_ADDR(sc, prod);
+
+ sc->kr_cdata.kr_tx_cnt++;
+ prev_desc = desc;
+ KR_INC(prod, KR_TX_RING_CNT);
+ }
+
+ /*
+ * Set COF for last descriptor and mark last fragment with LD flag
+ */
+ if (desc) {
+ desc->kr_ctl |= KR_CTL_COF;
+ desc->kr_devcs |= KR_DMATX_DEVCS_LD;
+ }
+
+ /* Update producer index. */
+ sc->kr_cdata.kr_tx_prod = prod;
+
+ /* Sync descriptors. */
+ bus_dmamap_sync(sc->kr_cdata.kr_tx_ring_tag,
+ sc->kr_cdata.kr_tx_ring_map,
+ BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
+
+ /* Start transmitting */
+ /* Check if new list is queued in NDPTR */
+ if (KR_DMA_READ_REG(KR_DMA_TXCHAN, DMA_NDPTR) == 0) {
+ /* NDPTR is not busy - start new list */
+ KR_DMA_WRITE_REG(KR_DMA_TXCHAN, DMA_NDPTR,
+ KR_TX_RING_ADDR(sc, si));
+ }
+ else {
+ link_addr = KR_TX_RING_ADDR(sc, si);
+ /* Get previous descriptor */
+ si = (si + KR_TX_RING_CNT - 1) % KR_TX_RING_CNT;
+ desc = &sc->kr_rdata.kr_tx_ring[si];
+ desc->kr_link = link_addr;
+ }
+
+ return (0);
+}
+
+static void
+kr_start_locked(struct ifnet *ifp)
+{
+ struct kr_softc *sc;
+ struct mbuf *m_head;
+ int enq;
+
+ sc = ifp->if_softc;
+
+ KR_LOCK_ASSERT(sc);
+
+ if ((ifp->if_drv_flags & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) !=
+ IFF_DRV_RUNNING || sc->kr_link_status == 0 )
+ return;
+
+ for (enq = 0; !IFQ_DRV_IS_EMPTY(&ifp->if_snd) &&
+ sc->kr_cdata.kr_tx_cnt < KR_TX_RING_CNT - 2; ) {
+ IFQ_DRV_DEQUEUE(&ifp->if_snd, m_head);
+ if (m_head == NULL)
+ break;
+ /*
+ * Pack the data into the transmit ring. If we
+ * don't have room, set the OACTIVE flag and wait
+ * for the NIC to drain the ring.
+ */
+ if (kr_encap(sc, &m_head)) {
+ if (m_head == NULL)
+ break;
+ IFQ_DRV_PREPEND(&ifp->if_snd, m_head);
+ ifp->if_drv_flags |= IFF_DRV_OACTIVE;
+ break;
+ }
+
+ enq++;
+ /*
+ * If there's a BPF listener, bounce a copy of this frame
+ * to him.
+ */
+ ETHER_BPF_MTAP(ifp, m_head);
+ }
+}
+
+static void
+kr_stop(struct kr_softc *sc)
+{
+ struct ifnet *ifp;
+
+ KR_LOCK_ASSERT(sc);
+
+
+ ifp = sc->kr_ifp;
+ ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE);
+ callout_stop(&sc->kr_stat_callout);
+
+ /* mask out RX interrupts */
+ KR_DMA_SETBITS_REG(KR_DMA_RXCHAN, DMA_SM,
+ DMA_SM_D | DMA_SM_H | DMA_SM_E);
+
+ /* mask out TX interrupts */
+ KR_DMA_SETBITS_REG(KR_DMA_TXCHAN, DMA_SM,
+ DMA_SM_F | DMA_SM_E);
+
+ /* Abort RX DMA transactions */
+ if (KR_DMA_READ_REG(KR_DMA_RXCHAN, DMA_C) & DMA_C_R) {
+ /* Set ABORT bit if trunsuction is in progress */
+ KR_DMA_WRITE_REG(KR_DMA_RXCHAN, DMA_C, DMA_C_ABORT);
+ /* XXX: Add timeout */
+ while ((KR_DMA_READ_REG(KR_DMA_RXCHAN, DMA_S) & DMA_S_H) == 0)
+ DELAY(10);
+ KR_DMA_WRITE_REG(KR_DMA_RXCHAN, DMA_S, 0);
+ }
+ KR_DMA_WRITE_REG(KR_DMA_RXCHAN, DMA_DPTR, 0);
+ KR_DMA_WRITE_REG(KR_DMA_RXCHAN, DMA_NDPTR, 0);
+
+ /* Abort TX DMA transactions */
+ if (KR_DMA_READ_REG(KR_DMA_TXCHAN, DMA_C) & DMA_C_R) {
+ /* Set ABORT bit if trunsuction is in progress */
+ KR_DMA_WRITE_REG(KR_DMA_TXCHAN, DMA_C, DMA_C_ABORT);
+ /* XXX: Add timeout */
+ while ((KR_DMA_READ_REG(KR_DMA_TXCHAN, DMA_S) & DMA_S_H) == 0)
+ DELAY(10);
+ KR_DMA_WRITE_REG(KR_DMA_TXCHAN, DMA_S, 0);
+ }
+ KR_DMA_WRITE_REG(KR_DMA_TXCHAN, DMA_DPTR, 0);
+ KR_DMA_WRITE_REG(KR_DMA_TXCHAN, DMA_NDPTR, 0);
+
+ CSR_WRITE_4(sc, KR_ETHINTFC, 0);
+}
+
+
+static int
+kr_ioctl(struct ifnet *ifp, u_long command, caddr_t data)
+{
+ struct kr_softc *sc = ifp->if_softc;
+ struct ifreq *ifr = (struct ifreq *) data;
+ struct mii_data *mii;
+ int error;
+
+ switch (command) {
+ case SIOCSIFFLAGS:
+#if 0
+ KR_LOCK(sc);
+ if (ifp->if_flags & IFF_UP) {
+ if (ifp->if_drv_flags & IFF_DRV_RUNNING) {
+ if ((ifp->if_flags ^ sc->kr_if_flags) &
+ (IFF_PROMISC | IFF_ALLMULTI))
+ kr_set_filter(sc);
+ } else {
+ if (sc->kr_detach == 0)
+ kr_init_locked(sc);
+ }
+ } else {
+ if (ifp->if_drv_flags & IFF_DRV_RUNNING)
+ kr_stop(sc);
+ }
+ sc->kr_if_flags = ifp->if_flags;
+ KR_UNLOCK(sc);
+#endif
+ error = 0;
+ break;
+ case SIOCADDMULTI:
+ case SIOCDELMULTI:
+#if 0
+ KR_LOCK(sc);
+ kr_set_filter(sc);
+ KR_UNLOCK(sc);
+#endif
+ error = 0;
+ break;
+ case SIOCGIFMEDIA:
+ case SIOCSIFMEDIA:
+ mii = device_get_softc(sc->kr_miibus);
+ error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command);
+ break;
+ case SIOCSIFCAP:
+ error = 0;
+#if 0
+ mask = ifr->ifr_reqcap ^ ifp->if_capenable;
+ if ((mask & IFCAP_HWCSUM) != 0) {
+ ifp->if_capenable ^= IFCAP_HWCSUM;
+ if ((IFCAP_HWCSUM & ifp->if_capenable) &&
+ (IFCAP_HWCSUM & ifp->if_capabilities))
+ ifp->if_hwassist = KR_CSUM_FEATURES;
+ else
+ ifp->if_hwassist = 0;
+ }
+ if ((mask & IFCAP_VLAN_HWTAGGING) != 0) {
+ ifp->if_capenable ^= IFCAP_VLAN_HWTAGGING;
+ if (IFCAP_VLAN_HWTAGGING & ifp->if_capenable &&
+ IFCAP_VLAN_HWTAGGING & ifp->if_capabilities &&
+ ifp->if_drv_flags & IFF_DRV_RUNNING) {
+ KR_LOCK(sc);
+ kr_vlan_setup(sc);
+ KR_UNLOCK(sc);
+ }
+ }
+ VLAN_CAPABILITIES(ifp);
+#endif
+ break;
+ default:
+ error = ether_ioctl(ifp, command, data);
+ break;
+ }
+
+ return (error);
+}
+
+/*
+ * Set media options.
+ */
+static int
+kr_ifmedia_upd(struct ifnet *ifp)
+{
+ struct kr_softc *sc;
+ struct mii_data *mii;
+ struct mii_softc *miisc;
+ int error;
+
+ sc = ifp->if_softc;
+ KR_LOCK(sc);
+ mii = device_get_softc(sc->kr_miibus);
+ LIST_FOREACH(miisc, &mii->mii_phys, mii_list)
+ PHY_RESET(miisc);
+ error = mii_mediachg(mii);
+ KR_UNLOCK(sc);
+
+ return (error);
+}
+
+/*
+ * Report current media status.
+ */
+static void
+kr_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr)
+{
+ struct kr_softc *sc = ifp->if_softc;
+ struct mii_data *mii;
+
+ mii = device_get_softc(sc->kr_miibus);
+ KR_LOCK(sc);
+ mii_pollstat(mii);
+ ifmr->ifm_active = mii->mii_media_active;
+ ifmr->ifm_status = mii->mii_media_status;
+ KR_UNLOCK(sc);
+}
+
+struct kr_dmamap_arg {
+ bus_addr_t kr_busaddr;
+};
+
+static void
+kr_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nseg, int error)
+{
+ struct kr_dmamap_arg *ctx;
+
+ if (error != 0)
+ return;
+ ctx = arg;
+ ctx->kr_busaddr = segs[0].ds_addr;
+}
+
+static int
+kr_dma_alloc(struct kr_softc *sc)
+{
+ struct kr_dmamap_arg ctx;
+ struct kr_txdesc *txd;
+ struct kr_rxdesc *rxd;
+ int error, i;
+
+ /* Create parent DMA tag. */
+ error = bus_dma_tag_create(
+ bus_get_dma_tag(sc->kr_dev), /* parent */
+ 1, 0, /* alignment, boundary */
+ BUS_SPACE_MAXADDR_32BIT, /* lowaddr */
+ BUS_SPACE_MAXADDR, /* highaddr */
+ NULL, NULL, /* filter, filterarg */
+ BUS_SPACE_MAXSIZE_32BIT, /* maxsize */
+ 0, /* nsegments */
+ BUS_SPACE_MAXSIZE_32BIT, /* maxsegsize */
+ 0, /* flags */
+ NULL, NULL, /* lockfunc, lockarg */
+ &sc->kr_cdata.kr_parent_tag);
+ if (error != 0) {
+ device_printf(sc->kr_dev, "failed to create parent DMA tag\n");
+ goto fail;
+ }
+ /* Create tag for Tx ring. */
+ error = bus_dma_tag_create(
+ sc->kr_cdata.kr_parent_tag, /* parent */
+ KR_RING_ALIGN, 0, /* alignment, boundary */
+ BUS_SPACE_MAXADDR, /* lowaddr */
+ BUS_SPACE_MAXADDR, /* highaddr */
+ NULL, NULL, /* filter, filterarg */
+ KR_TX_RING_SIZE, /* maxsize */
+ 1, /* nsegments */
+ KR_TX_RING_SIZE, /* maxsegsize */
+ 0, /* flags */
+ NULL, NULL, /* lockfunc, lockarg */
+ &sc->kr_cdata.kr_tx_ring_tag);
+ if (error != 0) {
+ device_printf(sc->kr_dev, "failed to create Tx ring DMA tag\n");
+ goto fail;
+ }
+
+ /* Create tag for Rx ring. */
+ error = bus_dma_tag_create(
+ sc->kr_cdata.kr_parent_tag, /* parent */
+ KR_RING_ALIGN, 0, /* alignment, boundary */
+ BUS_SPACE_MAXADDR, /* lowaddr */
+ BUS_SPACE_MAXADDR, /* highaddr */
+ NULL, NULL, /* filter, filterarg */
+ KR_RX_RING_SIZE, /* maxsize */
+ 1, /* nsegments */
+ KR_RX_RING_SIZE, /* maxsegsize */
+ 0, /* flags */
+ NULL, NULL, /* lockfunc, lockarg */
+ &sc->kr_cdata.kr_rx_ring_tag);
+ if (error != 0) {
+ device_printf(sc->kr_dev, "failed to create Rx ring DMA tag\n");
+ goto fail;
+ }
+
+ /* Create tag for Tx buffers. */
+ error = bus_dma_tag_create(
+ sc->kr_cdata.kr_parent_tag, /* parent */
+ sizeof(uint32_t), 0, /* alignment, boundary */
+ BUS_SPACE_MAXADDR, /* lowaddr */
+ BUS_SPACE_MAXADDR, /* highaddr */
+ NULL, NULL, /* filter, filterarg */
+ MCLBYTES * KR_MAXFRAGS, /* maxsize */
+ KR_MAXFRAGS, /* nsegments */
+ MCLBYTES, /* maxsegsize */
+ 0, /* flags */
+ NULL, NULL, /* lockfunc, lockarg */
+ &sc->kr_cdata.kr_tx_tag);
+ if (error != 0) {
+ device_printf(sc->kr_dev, "failed to create Tx DMA tag\n");
+ goto fail;
+ }
+
+ /* Create tag for Rx buffers. */
+ error = bus_dma_tag_create(
+ sc->kr_cdata.kr_parent_tag, /* parent */
+ KR_RX_ALIGN, 0, /* alignment, boundary */
+ BUS_SPACE_MAXADDR, /* lowaddr */
+ BUS_SPACE_MAXADDR, /* highaddr */
+ NULL, NULL, /* filter, filterarg */
+ MCLBYTES, /* maxsize */
+ 1, /* nsegments */
+ MCLBYTES, /* maxsegsize */
+ 0, /* flags */
+ NULL, NULL, /* lockfunc, lockarg */
+ &sc->kr_cdata.kr_rx_tag);
+ if (error != 0) {
+ device_printf(sc->kr_dev, "failed to create Rx DMA tag\n");
+ goto fail;
+ }
+
+ /* Allocate DMA'able memory and load the DMA map for Tx ring. */
+ error = bus_dmamem_alloc(sc->kr_cdata.kr_tx_ring_tag,
+ (void **)&sc->kr_rdata.kr_tx_ring, BUS_DMA_WAITOK |
+ BUS_DMA_COHERENT | BUS_DMA_ZERO, &sc->kr_cdata.kr_tx_ring_map);
+ if (error != 0) {
+ device_printf(sc->kr_dev,
+ "failed to allocate DMA'able memory for Tx ring\n");
+ goto fail;
+ }
+
+ ctx.kr_busaddr = 0;
+ error = bus_dmamap_load(sc->kr_cdata.kr_tx_ring_tag,
+ sc->kr_cdata.kr_tx_ring_map, sc->kr_rdata.kr_tx_ring,
+ KR_TX_RING_SIZE, kr_dmamap_cb, &ctx, 0);
+ if (error != 0 || ctx.kr_busaddr == 0) {
+ device_printf(sc->kr_dev,
+ "failed to load DMA'able memory for Tx ring\n");
+ goto fail;
+ }
+ sc->kr_rdata.kr_tx_ring_paddr = ctx.kr_busaddr;
+
+ /* Allocate DMA'able memory and load the DMA map for Rx ring. */
+ error = bus_dmamem_alloc(sc->kr_cdata.kr_rx_ring_tag,
+ (void **)&sc->kr_rdata.kr_rx_ring, BUS_DMA_WAITOK |
+ BUS_DMA_COHERENT | BUS_DMA_ZERO, &sc->kr_cdata.kr_rx_ring_map);
+ if (error != 0) {
+ device_printf(sc->kr_dev,
+ "failed to allocate DMA'able memory for Rx ring\n");
+ goto fail;
+ }
+
+ ctx.kr_busaddr = 0;
+ error = bus_dmamap_load(sc->kr_cdata.kr_rx_ring_tag,
+ sc->kr_cdata.kr_rx_ring_map, sc->kr_rdata.kr_rx_ring,
+ KR_RX_RING_SIZE, kr_dmamap_cb, &ctx, 0);
+ if (error != 0 || ctx.kr_busaddr == 0) {
+ device_printf(sc->kr_dev,
+ "failed to load DMA'able memory for Rx ring\n");
+ goto fail;
+ }
+ sc->kr_rdata.kr_rx_ring_paddr = ctx.kr_busaddr;
+
+ /* Create DMA maps for Tx buffers. */
+ for (i = 0; i < KR_TX_RING_CNT; i++) {
+ txd = &sc->kr_cdata.kr_txdesc[i];
+ txd->tx_m = NULL;
+ txd->tx_dmamap = NULL;
+ error = bus_dmamap_create(sc->kr_cdata.kr_tx_tag, 0,
+ &txd->tx_dmamap);
+ if (error != 0) {
+ device_printf(sc->kr_dev,
+ "failed to create Tx dmamap\n");
+ goto fail;
+ }
+ }
+ /* Create DMA maps for Rx buffers. */
+ if ((error = bus_dmamap_create(sc->kr_cdata.kr_rx_tag, 0,
+ &sc->kr_cdata.kr_rx_sparemap)) != 0) {
+ device_printf(sc->kr_dev,
+ "failed to create spare Rx dmamap\n");
+ goto fail;
+ }
+ for (i = 0; i < KR_RX_RING_CNT; i++) {
+ rxd = &sc->kr_cdata.kr_rxdesc[i];
+ rxd->rx_m = NULL;
+ rxd->rx_dmamap = NULL;
+ error = bus_dmamap_create(sc->kr_cdata.kr_rx_tag, 0,
+ &rxd->rx_dmamap);
+ if (error != 0) {
+ device_printf(sc->kr_dev,
+ "failed to create Rx dmamap\n");
+ goto fail;
+ }
+ }
+
+fail:
+ return (error);
+}
+
+static void
+kr_dma_free(struct kr_softc *sc)
+{
+ struct kr_txdesc *txd;
+ struct kr_rxdesc *rxd;
+ int i;
+
+ /* Tx ring. */
+ if (sc->kr_cdata.kr_tx_ring_tag) {
+ if (sc->kr_cdata.kr_tx_ring_map)
+ bus_dmamap_unload(sc->kr_cdata.kr_tx_ring_tag,
+ sc->kr_cdata.kr_tx_ring_map);
+ if (sc->kr_cdata.kr_tx_ring_map &&
+ sc->kr_rdata.kr_tx_ring)
+ bus_dmamem_free(sc->kr_cdata.kr_tx_ring_tag,
+ sc->kr_rdata.kr_tx_ring,
+ sc->kr_cdata.kr_tx_ring_map);
+ sc->kr_rdata.kr_tx_ring = NULL;
+ sc->kr_cdata.kr_tx_ring_map = NULL;
+ bus_dma_tag_destroy(sc->kr_cdata.kr_tx_ring_tag);
+ sc->kr_cdata.kr_tx_ring_tag = NULL;
+ }
+ /* Rx ring. */
+ if (sc->kr_cdata.kr_rx_ring_tag) {
+ if (sc->kr_cdata.kr_rx_ring_map)
+ bus_dmamap_unload(sc->kr_cdata.kr_rx_ring_tag,
+ sc->kr_cdata.kr_rx_ring_map);
+ if (sc->kr_cdata.kr_rx_ring_map &&
+ sc->kr_rdata.kr_rx_ring)
+ bus_dmamem_free(sc->kr_cdata.kr_rx_ring_tag,
+ sc->kr_rdata.kr_rx_ring,
+ sc->kr_cdata.kr_rx_ring_map);
+ sc->kr_rdata.kr_rx_ring = NULL;
+ sc->kr_cdata.kr_rx_ring_map = NULL;
+ bus_dma_tag_destroy(sc->kr_cdata.kr_rx_ring_tag);
+ sc->kr_cdata.kr_rx_ring_tag = NULL;
+ }
+ /* Tx buffers. */
+ if (sc->kr_cdata.kr_tx_tag) {
+ for (i = 0; i < KR_TX_RING_CNT; i++) {
+ txd = &sc->kr_cdata.kr_txdesc[i];
+ if (txd->tx_dmamap) {
+ bus_dmamap_destroy(sc->kr_cdata.kr_tx_tag,
+ txd->tx_dmamap);
+ txd->tx_dmamap = NULL;
+ }
+ }
+ bus_dma_tag_destroy(sc->kr_cdata.kr_tx_tag);
+ sc->kr_cdata.kr_tx_tag = NULL;
+ }
+ /* Rx buffers. */
+ if (sc->kr_cdata.kr_rx_tag) {
+ for (i = 0; i < KR_RX_RING_CNT; i++) {
+ rxd = &sc->kr_cdata.kr_rxdesc[i];
+ if (rxd->rx_dmamap) {
+ bus_dmamap_destroy(sc->kr_cdata.kr_rx_tag,
+ rxd->rx_dmamap);
+ rxd->rx_dmamap = NULL;
+ }
+ }
+ if (sc->kr_cdata.kr_rx_sparemap) {
+ bus_dmamap_destroy(sc->kr_cdata.kr_rx_tag,
+ sc->kr_cdata.kr_rx_sparemap);
+ sc->kr_cdata.kr_rx_sparemap = 0;
+ }
+ bus_dma_tag_destroy(sc->kr_cdata.kr_rx_tag);
+ sc->kr_cdata.kr_rx_tag = NULL;
+ }
+
+ if (sc->kr_cdata.kr_parent_tag) {
+ bus_dma_tag_destroy(sc->kr_cdata.kr_parent_tag);
+ sc->kr_cdata.kr_parent_tag = NULL;
+ }
+}
+
+/*
+ * Initialize the transmit descriptors.
+ */
+static int
+kr_tx_ring_init(struct kr_softc *sc)
+{
+ struct kr_ring_data *rd;
+ struct kr_txdesc *txd;
+ bus_addr_t addr;
+ int i;
+
+ sc->kr_cdata.kr_tx_prod = 0;
+ sc->kr_cdata.kr_tx_cons = 0;
+ sc->kr_cdata.kr_tx_cnt = 0;
+ sc->kr_cdata.kr_tx_pkts = 0;
+
+ rd = &sc->kr_rdata;
+ bzero(rd->kr_tx_ring, KR_TX_RING_SIZE);
+ for (i = 0; i < KR_TX_RING_CNT; i++) {
+ if (i == KR_TX_RING_CNT - 1)
+ addr = KR_TX_RING_ADDR(sc, 0);
+ else
+ addr = KR_TX_RING_ADDR(sc, i + 1);
+ rd->kr_tx_ring[i].kr_ctl = KR_CTL_IOF;
+ rd->kr_tx_ring[i].kr_ca = 0;
+ rd->kr_tx_ring[i].kr_devcs = 0;
+ rd->kr_tx_ring[i].kr_link = 0;
+ txd = &sc->kr_cdata.kr_txdesc[i];
+ txd->tx_m = NULL;
+ }
+
+ bus_dmamap_sync(sc->kr_cdata.kr_tx_ring_tag,
+ sc->kr_cdata.kr_tx_ring_map,
+ BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
+
+ return (0);
+}
+
+/*
+ * Initialize the RX descriptors and allocate mbufs for them. Note that
+ * we arrange the descriptors in a closed ring, so that the last descriptor
+ * points back to the first.
+ */
+static int
+kr_rx_ring_init(struct kr_softc *sc)
+{
+ struct kr_ring_data *rd;
+ struct kr_rxdesc *rxd;
+ bus_addr_t addr;
+ int i;
+
+ sc->kr_cdata.kr_rx_cons = 0;
+
+ rd = &sc->kr_rdata;
+ bzero(rd->kr_rx_ring, KR_RX_RING_SIZE);
+ for (i = 0; i < KR_RX_RING_CNT; i++) {
+ rxd = &sc->kr_cdata.kr_rxdesc[i];
+ rxd->rx_m = NULL;
+ rxd->desc = &rd->kr_rx_ring[i];
+ if (i == KR_RX_RING_CNT - 1)
+ addr = KR_RX_RING_ADDR(sc, 0);
+ else
+ addr = KR_RX_RING_ADDR(sc, i + 1);
+ rd->kr_rx_ring[i].kr_ctl = KR_CTL_IOD;
+ if (i == KR_RX_RING_CNT - 1)
+ rd->kr_rx_ring[i].kr_ctl |= KR_CTL_COD;
+ rd->kr_rx_ring[i].kr_devcs = 0;
+ rd->kr_rx_ring[i].kr_ca = 0;
+ rd->kr_rx_ring[i].kr_link = addr;
+ if (kr_newbuf(sc, i) != 0)
+ return (ENOBUFS);
+ }
+
+ bus_dmamap_sync(sc->kr_cdata.kr_rx_ring_tag,
+ sc->kr_cdata.kr_rx_ring_map,
+ BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
+
+ return (0);
+}
+
+/*
+ * Initialize an RX descriptor and attach an MBUF cluster.
+ */
+static int
+kr_newbuf(struct kr_softc *sc, int idx)
+{
+ struct kr_desc *desc;
+ struct kr_rxdesc *rxd;
+ struct mbuf *m;
+ bus_dma_segment_t segs[1];
+ bus_dmamap_t map;
+ int nsegs;
+
+ m = m_getcl(M_NOWAIT, MT_DATA, M_PKTHDR);
+ if (m == NULL)
+ return (ENOBUFS);
+ m->m_len = m->m_pkthdr.len = MCLBYTES;
+ m_adj(m, sizeof(uint64_t));
+
+ if (bus_dmamap_load_mbuf_sg(sc->kr_cdata.kr_rx_tag,
+ sc->kr_cdata.kr_rx_sparemap, m, segs, &nsegs, 0) != 0) {
+ m_freem(m);
+ return (ENOBUFS);
+ }
+ KASSERT(nsegs == 1, ("%s: %d segments returned!", __func__, nsegs));
+
+ rxd = &sc->kr_cdata.kr_rxdesc[idx];
+ if (rxd->rx_m != NULL) {
+ bus_dmamap_sync(sc->kr_cdata.kr_rx_tag, rxd->rx_dmamap,
+ BUS_DMASYNC_POSTREAD);
+ bus_dmamap_unload(sc->kr_cdata.kr_rx_tag, rxd->rx_dmamap);
+ }
+ map = rxd->rx_dmamap;
+ rxd->rx_dmamap = sc->kr_cdata.kr_rx_sparemap;
+ sc->kr_cdata.kr_rx_sparemap = map;
+ bus_dmamap_sync(sc->kr_cdata.kr_rx_tag, rxd->rx_dmamap,
+ BUS_DMASYNC_PREREAD);
+ rxd->rx_m = m;
+ desc = rxd->desc;
+ desc->kr_ca = segs[0].ds_addr;
+ desc->kr_ctl |= KR_DMASIZE(segs[0].ds_len);
+ rxd->saved_ca = desc->kr_ca ;
+ rxd->saved_ctl = desc->kr_ctl ;
+
+ return (0);
+}
+
+static __inline void
+kr_fixup_rx(struct mbuf *m)
+{
+ int i;
+ uint16_t *src, *dst;
+
+ src = mtod(m, uint16_t *);
+ dst = src - 1;
+
+ for (i = 0; i < (m->m_len / sizeof(uint16_t) + 1); i++)
+ *dst++ = *src++;
+
+ m->m_data -= ETHER_ALIGN;
+}
+
+
+static void
+kr_tx(struct kr_softc *sc)
+{
+ struct kr_txdesc *txd;
+ struct kr_desc *cur_tx;
+ struct ifnet *ifp;
+ uint32_t ctl, devcs;
+ int cons, prod;
+
+ KR_LOCK_ASSERT(sc);
+
+ cons = sc->kr_cdata.kr_tx_cons;
+ prod = sc->kr_cdata.kr_tx_prod;
+ if (cons == prod)
+ return;
+
+ bus_dmamap_sync(sc->kr_cdata.kr_tx_ring_tag,
+ sc->kr_cdata.kr_tx_ring_map,
+ BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
+
+ ifp = sc->kr_ifp;
+ /*
+ * Go through our tx list and free mbufs for those
+ * frames that have been transmitted.
+ */
+ for (; cons != prod; KR_INC(cons, KR_TX_RING_CNT)) {
+ cur_tx = &sc->kr_rdata.kr_tx_ring[cons];
+ ctl = cur_tx->kr_ctl;
+ devcs = cur_tx->kr_devcs;
+ /* Check if descriptor has "finished" flag */
+ if ((ctl & KR_CTL_F) == 0)
+ break;
+
+ sc->kr_cdata.kr_tx_cnt--;
+ ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
+
+ txd = &sc->kr_cdata.kr_txdesc[cons];
+
+ if (devcs & KR_DMATX_DEVCS_TOK)
+ ifp->if_opackets++;
+ else {
+ ifp->if_oerrors++;
+ /* collisions: medium busy, late collision */
+ if ((devcs & KR_DMATX_DEVCS_EC) ||
+ (devcs & KR_DMATX_DEVCS_LC))
+ ifp->if_collisions++;
+ }
+
+ bus_dmamap_sync(sc->kr_cdata.kr_tx_tag, txd->tx_dmamap,
+ BUS_DMASYNC_POSTWRITE);
+ bus_dmamap_unload(sc->kr_cdata.kr_tx_tag, txd->tx_dmamap);
+
+ /* Free only if it's first descriptor in list */
+ if (txd->tx_m)
+ m_freem(txd->tx_m);
+ txd->tx_m = NULL;
+
+ /* reset descriptor */
+ cur_tx->kr_ctl = KR_CTL_IOF;
+ cur_tx->kr_devcs = 0;
+ cur_tx->kr_ca = 0;
+ cur_tx->kr_link = 0;
+ }
+
+ sc->kr_cdata.kr_tx_cons = cons;
+
+ bus_dmamap_sync(sc->kr_cdata.kr_tx_ring_tag,
+ sc->kr_cdata.kr_tx_ring_map, BUS_DMASYNC_PREWRITE);
+}
+
+
+static void
+kr_rx(struct kr_softc *sc)
+{
+ struct kr_rxdesc *rxd;
+ struct ifnet *ifp = sc->kr_ifp;
+ int cons, prog, packet_len, count, error;
+ struct kr_desc *cur_rx;
+ struct mbuf *m;
+
+ KR_LOCK_ASSERT(sc);
+
+ cons = sc->kr_cdata.kr_rx_cons;
+
+ bus_dmamap_sync(sc->kr_cdata.kr_rx_ring_tag,
+ sc->kr_cdata.kr_rx_ring_map,
+ BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
+
+ for (prog = 0; prog < KR_RX_RING_CNT; KR_INC(cons, KR_RX_RING_CNT)) {
+ cur_rx = &sc->kr_rdata.kr_rx_ring[cons];
+ rxd = &sc->kr_cdata.kr_rxdesc[cons];
+ m = rxd->rx_m;
+
+ if ((cur_rx->kr_ctl & KR_CTL_D) == 0)
+ break;
+
+ prog++;
+
+ packet_len = KR_PKTSIZE(cur_rx->kr_devcs);
+ count = m->m_len - KR_DMASIZE(cur_rx->kr_ctl);
+ /* Assume it's error */
+ error = 1;
+
+ if (packet_len != count)
+ ifp->if_ierrors++;
+ else if (count < 64)
+ ifp->if_ierrors++;
+ else if ((cur_rx->kr_devcs & KR_DMARX_DEVCS_LD) == 0)
+ ifp->if_ierrors++;
+ else if ((cur_rx->kr_devcs & KR_DMARX_DEVCS_ROK) != 0) {
+ error = 0;
+ bus_dmamap_sync(sc->kr_cdata.kr_rx_tag, rxd->rx_dmamap,
+ BUS_DMASYNC_PREREAD);
+ m = rxd->rx_m;
+ kr_fixup_rx(m);
+ m->m_pkthdr.rcvif = ifp;
+ /* Skip 4 bytes of CRC */
+ m->m_pkthdr.len = m->m_len = packet_len - ETHER_CRC_LEN;
+ ifp->if_ipackets++;
+
+ KR_UNLOCK(sc);
+ (*ifp->if_input)(ifp, m);
+ KR_LOCK(sc);
+ }
+
+ if (error) {
+ /* Restore CONTROL and CA values, reset DEVCS */
+ cur_rx->kr_ctl = rxd->saved_ctl;
+ cur_rx->kr_ca = rxd->saved_ca;
+ cur_rx->kr_devcs = 0;
+ }
+ else {
+ /* Reinit descriptor */
+ cur_rx->kr_ctl = KR_CTL_IOD;
+ if (cons == KR_RX_RING_CNT - 1)
+ cur_rx->kr_ctl |= KR_CTL_COD;
+ cur_rx->kr_devcs = 0;
+ cur_rx->kr_ca = 0;
+ if (kr_newbuf(sc, cons) != 0) {
+ device_printf(sc->kr_dev,
+ "Failed to allocate buffer\n");
+ break;
+ }
+ }
+
+ bus_dmamap_sync(sc->kr_cdata.kr_rx_ring_tag,
+ sc->kr_cdata.kr_rx_ring_map,
+ BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
+
+ }
+
+ if (prog > 0) {
+ sc->kr_cdata.kr_rx_cons = cons;
+
+ bus_dmamap_sync(sc->kr_cdata.kr_rx_ring_tag,
+ sc->kr_cdata.kr_rx_ring_map,
+ BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
+ }
+}
+
+static void
+kr_rx_intr(void *arg)
+{
+ struct kr_softc *sc = arg;
+ uint32_t status;
+
+ KR_LOCK(sc);
+
+ /* mask out interrupts */
+ KR_DMA_SETBITS_REG(KR_DMA_RXCHAN, DMA_SM,
+ DMA_SM_D | DMA_SM_H | DMA_SM_E);
+
+ status = KR_DMA_READ_REG(KR_DMA_RXCHAN, DMA_S);
+ if (status & (DMA_S_D | DMA_S_E | DMA_S_H)) {
+ kr_rx(sc);
+
+ if (status & DMA_S_E)
+ device_printf(sc->kr_dev, "RX DMA error\n");
+ }
+
+ /* Reread status */
+ status = KR_DMA_READ_REG(KR_DMA_RXCHAN, DMA_S);
+
+ /* restart DMA RX if it has been halted */
+ if (status & DMA_S_H) {
+ KR_DMA_WRITE_REG(KR_DMA_RXCHAN, DMA_DPTR,
+ KR_RX_RING_ADDR(sc, sc->kr_cdata.kr_rx_cons));
+ }
+
+ KR_DMA_WRITE_REG(KR_DMA_RXCHAN, DMA_S, ~status);
+
+ /* Enable F, H, E interrupts */
+ KR_DMA_CLEARBITS_REG(KR_DMA_RXCHAN, DMA_SM,
+ DMA_SM_D | DMA_SM_H | DMA_SM_E);
+
+ KR_UNLOCK(sc);
+}
+
+static void
+kr_tx_intr(void *arg)
+{
+ struct kr_softc *sc = arg;
+ uint32_t status;
+
+ KR_LOCK(sc);
+
+ /* mask out interrupts */
+ KR_DMA_SETBITS_REG(KR_DMA_TXCHAN, DMA_SM,
+ DMA_SM_F | DMA_SM_E);
+
+ status = KR_DMA_READ_REG(KR_DMA_TXCHAN, DMA_S);
+ if (status & (DMA_S_F | DMA_S_E)) {
+ kr_tx(sc);
+ if (status & DMA_S_E)
+ device_printf(sc->kr_dev, "DMA error\n");
+ }
+
+ KR_DMA_WRITE_REG(KR_DMA_TXCHAN, DMA_S, ~status);
+
+ /* Enable F, E interrupts */
+ KR_DMA_CLEARBITS_REG(KR_DMA_TXCHAN, DMA_SM,
+ DMA_SM_F | DMA_SM_E);
+
+ KR_UNLOCK(sc);
+
+}
+
+static void
+kr_rx_und_intr(void *arg)
+{
+
+ panic("interrupt: %s\n", __func__);
+}
+
+static void
+kr_tx_ovr_intr(void *arg)
+{
+
+ panic("interrupt: %s\n", __func__);
+}
+
+static void
+kr_tick(void *xsc)
+{
+ struct kr_softc *sc = xsc;
+ struct mii_data *mii;
+
+ KR_LOCK_ASSERT(sc);
+
+ mii = device_get_softc(sc->kr_miibus);
+ mii_tick(mii);
+ callout_reset(&sc->kr_stat_callout, hz, kr_tick, sc);
+}
Property changes on: trunk/sys/mips/idt/if_kr.c
___________________________________________________________________
Added: svn:eol-style
## -0,0 +1 ##
+native
\ No newline at end of property
Added: svn:keywords
## -0,0 +1 ##
+MidnightBSD=%H
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+text/plain
\ No newline at end of property
Added: trunk/sys/mips/idt/if_krreg.h
===================================================================
--- trunk/sys/mips/idt/if_krreg.h (rev 0)
+++ trunk/sys/mips/idt/if_krreg.h 2018-05-26 21:55:02 UTC (rev 9987)
@@ -0,0 +1,285 @@
+/* $MidnightBSD$ */
+/*-
+ * Copyright (C) 2007
+ * Oleksandr Tymoshenko <gonzo at freebsd.org>. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+ * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+ * IN NO EVENT SHALL THE AUTHOR OR HIS RELATIVES BE LIABLE FOR ANY DIRECT,
+ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF MIND, USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
+ * THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * $FreeBSD: stable/10/sys/mips/idt/if_krreg.h 202175 2010-01-12 21:36:08Z imp $
+ *
+ */
+
+#ifndef __IF_KRREG_H__
+#define __IF_KRREG_H__
+
+#define KR_ETHINTFC 0x0000 /* Ethernet interface control */
+#define ETH_INTFC_EN 0x0001
+#define ETH_INTFC_RIP 0x0004
+#define ETH_INTFC_EN 0x0001
+#define KR_ETHFIFOTT 0x0004 /* Ethernet FIFO transmit threshold */
+#define KR_ETHARC 0x0008 /* Ethernet address recognition control */
+#define KR_ETHHASH0 0x000C /* Ethernet hash table 0 */
+#define KR_ETHHASH1 0x0010 /* Ethernet hash table 1 */
+#define KR_ETHPFS 0x0024 /* Ethernet pause frame status */
+#define KR_ETHMCP 0x0028 /* Ethernet management clock prescalar */
+#define KR_ETHSAL0 0x0100 /* Ethernet station address 0 low */
+#define KR_ETHSAH0 0x0104 /* Ethernet station address 0 high */
+#define KR_ETHSAL1 0x0108 /* Ethernet station address 1 low */
+#define KR_ETHSAH1 0x010C /* Ethernet station address 1 high */
+#define KR_ETHSAL2 0x0110 /* Ethernet station address 2 low */
+#define KR_ETHSAH2 0x0114 /* Ethernet station address 2 high */
+#define KR_ETHSAL3 0x0118 /* Ethernet station address 3 low */
+#define KR_ETHSAH3 0x011C /* Ethernet station address 3 high */
+#define KR_ETHRBC 0x0120 /* Ethernet receive byte count */
+#define KR_ETHRPC 0x0124 /* Ethernet receive packet count */
+#define KR_ETHRUPC 0x0128 /* Ethernet receive undersized packet cnt */
+#define KR_ETHRFC 0x012C /* Ethernet receive fragment count */
+#define KR_ETHTBC 0x0130 /* Ethernet transmit byte count */
+#define KR_ETHGPF 0x0134 /* Ethernet generate pause frame */
+#define KR_ETHMAC1 0x0200 /* Ethernet MAC configuration 1 */
+#define KR_ETH_MAC1_RE 0x01
+#define KR_ETH_MAC1_PAF 0x02
+#define KR_ETH_MAC1_MR 0x80
+#define KR_ETHMAC2 0x0204 /* Ethernet MAC configuration 2 */
+#define KR_ETH_MAC2_FD 0x01
+#define KR_ETH_MAC2_FLC 0x02
+#define KR_ETH_MAC2_HFE 0x04
+#define KR_ETH_MAC2_DC 0x08
+#define KR_ETH_MAC2_CEN 0x10
+#define KR_ETH_MAC2_PEN 0x20
+#define KR_ETH_MAC2_VPE 0x08
+#define KR_ETHIPGT 0x0208 /* Ethernet back-to-back inter-packet gap */
+#define KR_ETHIPGR 0x020C /* Ethernet non back-to-back inter-packet gap */
+#define KR_ETHCLRT 0x0210 /* Ethernet collision window retry */
+#define KR_ETHMAXF 0x0214 /* Ethernet maximum frame length */
+#define KR_ETHMTEST 0x021C /* Ethernet MAC test */
+#define KR_MIIMCFG 0x0220 /* MII management configuration */
+#define KR_MIIMCFG_R 0x8000
+#define KR_MIIMCMD 0x0224 /* MII management command */
+#define KR_MIIMCMD_RD 0x01
+#define KR_MIIMCMD_SCN 0x02
+#define KR_MIIMADDR 0x0228 /* MII management address */
+#define KR_MIIMWTD 0x022C /* MII management write data */
+#define KR_MIIMRDD 0x0230 /* MII management read data */
+#define KR_MIIMIND 0x0234 /* MII management indicators */
+#define KR_MIIMIND_BSY 0x1
+#define KR_MIIMIND_SCN 0x2
+#define KR_MIIMIND_NV 0x4
+#define KR_ETHCFSA0 0x0240 /* Ethernet control frame station address 0 */
+#define KR_ETHCFSA1 0x0244 /* Ethernet control frame station address 1 */
+#define KR_ETHCFSA2 0x0248 /* Ethernet control frame station address 2 */
+
+#define KR_ETHIPGT_HALF_DUPLEX 0x12
+#define KR_ETHIPGT_FULL_DUPLEX 0x15
+
+#define KR_TIMEOUT 0xf000
+#define KR_MII_TIMEOUT 0xf000
+
+#define KR_RX_IRQ 40
+#define KR_TX_IRQ 41
+#define KR_RX_UND_IRQ 42
+#define KR_TX_OVR_IRQ 43
+#define RC32434_DMA_BASE_ADDR MIPS_PHYS_TO_KSEG1(0x18040000)
+#define DMA_C 0x00
+#define DMA_C_R 0x01
+#define DMA_C_ABORT 0x10
+#define DMA_S 0x04
+#define DMA_S_F 0x01
+#define DMA_S_D 0x02
+#define DMA_S_C 0x04
+#define DMA_S_E 0x08
+#define DMA_S_H 0x10
+#define DMA_SM 0x08
+#define DMA_SM_F 0x01
+#define DMA_SM_D 0x02
+#define DMA_SM_C 0x04
+#define DMA_SM_E 0x08
+#define DMA_SM_H 0x10
+#define DMA_DPTR 0x0C
+#define DMA_NDPTR 0x10
+
+#define RC32434_DMA_CHAN_SIZE 0x14
+#define KR_DMA_RXCHAN 0
+#define KR_DMA_TXCHAN 1
+
+#define KR_DMA_READ_REG(chan, reg) \
+ (*(volatile uint32_t *) \
+ (RC32434_DMA_BASE_ADDR + chan * RC32434_DMA_CHAN_SIZE + reg))
+
+#define KR_DMA_WRITE_REG(chan, reg, val) \
+ ((*(volatile uint32_t *) \
+ (RC32434_DMA_BASE_ADDR + chan * RC32434_DMA_CHAN_SIZE + reg)) = val)
+
+#define KR_DMA_SETBITS_REG(chan, reg, bits) \
+ KR_DMA_WRITE_REG((chan), (reg), KR_DMA_READ_REG((chan), (reg)) | (bits))
+
+#define KR_DMA_CLEARBITS_REG(chan, reg, bits) \
+ KR_DMA_WRITE_REG((chan), (reg), \
+ KR_DMA_READ_REG((chan), (reg)) & ~(bits))
+
+struct kr_desc {
+ uint32_t kr_ctl;
+ uint32_t kr_ca;
+ uint32_t kr_devcs;
+ uint32_t kr_link;
+};
+
+
+#define KR_DMASIZE(len) ((len) & ((1 << 18)-1))
+#define KR_PKTSIZE(len) ((len & 0xffff0000) >> 16)
+
+#define KR_CTL_COF 0x02000000
+#define KR_CTL_COD 0x04000000
+#define KR_CTL_IOF 0x08000000
+#define KR_CTL_IOD 0x10000000
+#define KR_CTL_T 0x20000000
+#define KR_CTL_D 0x40000000
+#define KR_CTL_F 0x80000000
+
+#define KR_DMARX_DEVCS_RSV 0x00000001
+#define KR_DMARX_DEVCS_LD 0x00000002
+#define KR_DMARX_DEVCS_ROK 0x00000004
+#define KR_DMARX_DEVCS_FM 0x00000008
+#define KR_DMARX_DEVCS_MP 0x00000010
+#define KR_DMARX_DEVCS_BP 0x00000020
+#define KR_DMARX_DEVCS_VLT 0x00000040
+#define KR_DMARX_DEVCS_CF 0x00000080
+#define KR_DMARX_DEVCS_OVR 0x00000100
+#define KR_DMARX_DEVCS_CRC 0x00000200
+#define KR_DMARX_DEVCS_CV 0x00000400
+#define KR_DMARX_DEVCS_DB 0x00000800
+#define KR_DMARX_DEVCS_LE 0x00001000
+#define KR_DMARX_DEVCS_LOR 0x00002000
+#define KR_DMARX_DEVCS_CES 0x00004000
+
+#define KR_DMATX_DEVCS_FD 0x00000001
+#define KR_DMATX_DEVCS_LD 0x00000002
+#define KR_DMATX_DEVCS_OEN 0x00000004
+#define KR_DMATX_DEVCS_PEN 0x00000008
+#define KR_DMATX_DEVCS_CEN 0x00000010
+#define KR_DMATX_DEVCS_HEN 0x00000020
+#define KR_DMATX_DEVCS_TOK 0x00000040
+#define KR_DMATX_DEVCS_MP 0x00000080
+#define KR_DMATX_DEVCS_BP 0x00000100
+#define KR_DMATX_DEVCS_UND 0x00000200
+#define KR_DMATX_DEVCS_OF 0x00000400
+#define KR_DMATX_DEVCS_ED 0x00000800
+#define KR_DMATX_DEVCS_EC 0x00001000
+#define KR_DMATX_DEVCS_LC 0x00002000
+#define KR_DMATX_DEVCS_TD 0x00004000
+#define KR_DMATX_DEVCS_CRC 0x00008000
+#define KR_DMATX_DEVCS_LE 0x00010000
+
+#define KR_RX_RING_CNT 128
+#define KR_TX_RING_CNT 128
+#define KR_TX_RING_SIZE sizeof(struct kr_desc) * KR_TX_RING_CNT
+#define KR_RX_RING_SIZE sizeof(struct kr_desc) * KR_RX_RING_CNT
+#define KR_RING_ALIGN sizeof(struct kr_desc)
+#define KR_RX_ALIGN sizeof(uint32_t)
+#define KR_MAXFRAGS 8
+#define KR_TX_INTR_THRESH 8
+
+#define KR_TX_RING_ADDR(sc, i) \
+ ((sc)->kr_rdata.kr_tx_ring_paddr + sizeof(struct kr_desc) * (i))
+#define KR_RX_RING_ADDR(sc, i) \
+ ((sc)->kr_rdata.kr_rx_ring_paddr + sizeof(struct kr_desc) * (i))
+#define KR_INC(x,y) (x) = (((x) + 1) % y)
+
+struct kr_txdesc {
+ struct mbuf *tx_m;
+ bus_dmamap_t tx_dmamap;
+};
+
+struct kr_rxdesc {
+ struct mbuf *rx_m;
+ bus_dmamap_t rx_dmamap;
+ struct kr_desc *desc;
+ /* Use this values on error instead of allocating new mbuf */
+ uint32_t saved_ctl, saved_ca;
+};
+
+struct kr_chain_data {
+ bus_dma_tag_t kr_parent_tag;
+ bus_dma_tag_t kr_tx_tag;
+ struct kr_txdesc kr_txdesc[KR_TX_RING_CNT];
+ bus_dma_tag_t kr_rx_tag;
+ struct kr_rxdesc kr_rxdesc[KR_RX_RING_CNT];
+ bus_dma_tag_t kr_tx_ring_tag;
+ bus_dma_tag_t kr_rx_ring_tag;
+ bus_dmamap_t kr_tx_ring_map;
+ bus_dmamap_t kr_rx_ring_map;
+ bus_dmamap_t kr_rx_sparemap;
+ int kr_tx_pkts;
+ int kr_tx_prod;
+ int kr_tx_cons;
+ int kr_tx_cnt;
+ int kr_rx_cons;
+};
+
+struct kr_ring_data {
+ struct kr_desc *kr_rx_ring;
+ struct kr_desc *kr_tx_ring;
+ bus_addr_t kr_rx_ring_paddr;
+ bus_addr_t kr_tx_ring_paddr;
+};
+
+struct kr_softc {
+ struct ifnet *kr_ifp; /* interface info */
+ bus_space_handle_t kr_bhandle; /* bus space handle */
+ bus_space_tag_t kr_btag; /* bus space tag */
+ device_t kr_dev;
+ struct resource *kr_res;
+ int kr_rid;
+ struct resource *kr_rx_irq;
+ void *kr_rx_intrhand;
+ struct resource *kr_tx_irq;
+ void *kr_tx_intrhand;
+ struct resource *kr_rx_und_irq;
+ void *kr_rx_und_intrhand;
+ struct resource *kr_tx_ovr_irq;
+ void *kr_tx_ovr_intrhand;
+ device_t kr_miibus;
+ bus_dma_tag_t kr_parent_tag;
+ bus_dma_tag_t kr_tag;
+ struct mtx kr_mtx;
+ struct callout kr_stat_callout;
+ struct task kr_link_task;
+ struct kr_chain_data kr_cdata;
+ struct kr_ring_data kr_rdata;
+ int kr_link_status;
+ int kr_detach;
+};
+
+#define KR_LOCK(_sc) mtx_lock(&(_sc)->kr_mtx)
+#define KR_UNLOCK(_sc) mtx_unlock(&(_sc)->kr_mtx)
+#define KR_LOCK_ASSERT(_sc) mtx_assert(&(_sc)->kr_mtx, MA_OWNED)
+
+/*
+ * register space access macros
+ */
+#define CSR_WRITE_4(sc, reg, val) \
+ bus_space_write_4(sc->kr_btag, sc->kr_bhandle, reg, val)
+
+#define CSR_READ_4(sc, reg) \
+ bus_space_read_4(sc->kr_btag, sc->kr_bhandle, reg)
+
+#endif /* __IF_KRREG_H__ */
Property changes on: trunk/sys/mips/idt/if_krreg.h
___________________________________________________________________
Added: svn:eol-style
## -0,0 +1 ##
+native
\ No newline at end of property
Added: svn:keywords
## -0,0 +1 ##
+MidnightBSD=%H
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+text/plain
\ No newline at end of property
Added: trunk/sys/mips/idt/obio.c
===================================================================
--- trunk/sys/mips/idt/obio.c (rev 0)
+++ trunk/sys/mips/idt/obio.c 2018-05-26 21:55:02 UTC (rev 9987)
@@ -0,0 +1,487 @@
+/* $MidnightBSD$ */
+/*-
+ * Copyright (c) 2007, Oleksandr Tymoshenko <gonzo at freebsd.org>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * 3. All advertising materials mentioning features or use of this software
+ * must display the following acknowledgement:
+ * This product includes software developed for the NetBSD Project by
+ * Wasabi Systems, Inc.
+ * 4. The name of Wasabi Systems, Inc. may not be used to endorse
+ * or promote products derived from this software without specific prior
+ * written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <sys/cdefs.h>
+__FBSDID("$FreeBSD: stable/10/sys/mips/idt/obio.c 265999 2014-05-14 01:35:43Z ian $");
+
+#include <sys/param.h>
+#include <sys/systm.h>
+#include <sys/bus.h>
+#include <sys/interrupt.h>
+#include <sys/kernel.h>
+#include <sys/module.h>
+#include <sys/rman.h>
+#include <sys/malloc.h>
+
+#include <machine/bus.h>
+
+#include <mips/idt/idtreg.h>
+#include <mips/idt/obiovar.h>
+
+#define ICU_REG_READ(o) \
+ *((volatile uint32_t *)MIPS_PHYS_TO_KSEG1(IDT_BASE_ICU + (o)))
+#define ICU_REG_WRITE(o,v) (ICU_REG_READ(o)) = (v)
+
+#define GPIO_REG_READ(o) \
+ *((volatile uint32_t *)MIPS_PHYS_TO_KSEG1(IDT_BASE_GPIO + (o)))
+#define GPIO_REG_WRITE(o,v) (GPIO_REG_READ(o)) = (v)
+
+static int obio_activate_resource(device_t, device_t, int, int,
+ struct resource *);
+static device_t obio_add_child(device_t, u_int, const char *, int);
+static struct resource *
+ obio_alloc_resource(device_t, device_t, int, int *, u_long,
+ u_long, u_long, u_int);
+static int obio_attach(device_t);
+static int obio_deactivate_resource(device_t, device_t, int, int,
+ struct resource *);
+static struct resource_list *
+ obio_get_resource_list(device_t, device_t);
+static void obio_hinted_child(device_t, const char *, int);
+static int obio_intr(void *);
+static int obio_probe(device_t);
+static int obio_release_resource(device_t, device_t, int, int,
+ struct resource *);
+static int obio_setup_intr(device_t, device_t, struct resource *, int,
+ driver_filter_t *, driver_intr_t *, void *, void **);
+static int obio_teardown_intr(device_t, device_t, struct resource *,
+ void *);
+
+static void
+obio_mask_irq(void *arg)
+{
+ unsigned int irq = (unsigned int)arg;
+ int ip_bit, mask, mask_register;
+
+ /* mask IRQ */
+ mask_register = ICU_IRQ_MASK_REG(irq);
+ ip_bit = ICU_IP_BIT(irq);
+
+ mask = ICU_REG_READ(mask_register);
+ ICU_REG_WRITE(mask_register, mask | ip_bit);
+}
+
+static void
+obio_unmask_irq(void *arg)
+{
+ unsigned int irq = (unsigned int)arg;
+ int ip_bit, mask, mask_register;
+
+ /* unmask IRQ */
+ mask_register = ICU_IRQ_MASK_REG(irq);
+ ip_bit = ICU_IP_BIT(irq);
+
+ mask = ICU_REG_READ(mask_register);
+ ICU_REG_WRITE(mask_register, mask & ~ip_bit);
+}
+
+static int
+obio_probe(device_t dev)
+{
+
+ return (BUS_PROBE_NOWILDCARD);
+}
+
+static int
+obio_attach(device_t dev)
+{
+ struct obio_softc *sc = device_get_softc(dev);
+ int rid, irq;
+
+ sc->oba_mem_rman.rm_type = RMAN_ARRAY;
+ sc->oba_mem_rman.rm_descr = "OBIO memeory";
+ if (rman_init(&sc->oba_mem_rman) != 0 ||
+ rman_manage_region(&sc->oba_mem_rman, OBIO_MEM_START,
+ OBIO_MEM_START + OBIO_MEM_SIZE) != 0)
+ panic("obio_attach: failed to set up I/O rman");
+
+ sc->oba_irq_rman.rm_type = RMAN_ARRAY;
+ sc->oba_irq_rman.rm_descr = "OBIO IRQ";
+
+ if (rman_init(&sc->oba_irq_rman) != 0 ||
+ rman_manage_region(&sc->oba_irq_rman, IRQ_BASE, IRQ_END) != 0)
+ panic("obio_attach: failed to set up IRQ rman");
+
+ /* Hook up our interrupt handlers. We should handle IRQ0..IRQ4*/
+ for(irq = 0; irq < 5; irq++) {
+ if ((sc->sc_irq[irq] = bus_alloc_resource(dev, SYS_RES_IRQ,
+ &rid, irq, irq, 1, RF_SHAREABLE | RF_ACTIVE)) == NULL) {
+ device_printf(dev, "unable to allocate IRQ resource\n");
+ return (ENXIO);
+ }
+
+ if ((bus_setup_intr(dev, sc->sc_irq[irq], INTR_TYPE_MISC,
+ obio_intr, NULL, sc, &sc->sc_ih[irq]))) {
+ device_printf(dev,
+ "WARNING: unable to register interrupt handler\n");
+ return (ENXIO);
+ }
+ }
+
+ bus_generic_probe(dev);
+ bus_enumerate_hinted_children(dev);
+ bus_generic_attach(dev);
+
+ return (0);
+}
+
+static struct resource *
+obio_alloc_resource(device_t bus, device_t child, int type, int *rid,
+ u_long start, u_long end, u_long count, u_int flags)
+{
+ struct obio_softc *sc = device_get_softc(bus);
+ struct obio_ivar *ivar = device_get_ivars(child);
+ struct resource *rv;
+ struct resource_list_entry *rle;
+ struct rman *rm;
+ int isdefault, needactivate, passthrough;
+
+ isdefault = (start == 0UL && end == ~0UL);
+ needactivate = flags & RF_ACTIVE;
+ passthrough = (device_get_parent(child) != bus);
+ rle = NULL;
+
+ if (passthrough)
+ return (BUS_ALLOC_RESOURCE(device_get_parent(bus), child, type,
+ rid, start, end, count, flags));
+
+ /*
+ * If this is an allocation of the "default" range for a given RID,
+ * and we know what the resources for this device are (ie. they aren't
+ * maintained by a child bus), then work out the start/end values.
+ */
+ if (isdefault) {
+ rle = resource_list_find(&ivar->resources, type, *rid);
+ if (rle == NULL)
+ return (NULL);
+ if (rle->res != NULL) {
+ panic("%s: resource entry is busy", __func__);
+ }
+ start = rle->start;
+ end = rle->end;
+ count = rle->count;
+ }
+
+ switch (type) {
+ case SYS_RES_IRQ:
+ rm = &sc->oba_irq_rman;
+ break;
+ case SYS_RES_MEMORY:
+ rm = &sc->oba_mem_rman;
+ break;
+ default:
+ printf("%s: unknown resource type %d\n", __func__, type);
+ return (0);
+ }
+
+ rv = rman_reserve_resource(rm, start, end, count, flags, child);
+ if (rv == 0) {
+ printf("%s: could not reserve resource\n", __func__);
+ return (0);
+ }
+
+ rman_set_rid(rv, *rid);
+
+ if (needactivate) {
+ if (bus_activate_resource(child, type, *rid, rv)) {
+ printf("%s: could not activate resource\n", __func__);
+ rman_release_resource(rv);
+ return (0);
+ }
+ }
+
+ return (rv);
+}
+
+static int
+obio_activate_resource(device_t bus, device_t child, int type, int rid,
+ struct resource *r)
+{
+
+ /* XXX: should we mask/unmask IRQ here? */
+ return (BUS_ACTIVATE_RESOURCE(device_get_parent(bus), child,
+ type, rid, r));
+}
+
+static int
+obio_deactivate_resource(device_t bus, device_t child, int type, int rid,
+ struct resource *r)
+{
+
+ /* XXX: should we mask/unmask IRQ here? */
+ return (BUS_DEACTIVATE_RESOURCE(device_get_parent(bus), child,
+ type, rid, r));
+}
+
+static int
+obio_release_resource(device_t dev, device_t child, int type,
+ int rid, struct resource *r)
+{
+ struct resource_list *rl;
+ struct resource_list_entry *rle;
+
+ rl = obio_get_resource_list(dev, child);
+ if (rl == NULL)
+ return (EINVAL);
+ rle = resource_list_find(rl, type, rid);
+ if (rle == NULL)
+ return (EINVAL);
+ rman_release_resource(r);
+ rle->res = NULL;
+
+ return (0);
+}
+
+static int
+obio_setup_intr(device_t dev, device_t child, struct resource *ires,
+ int flags, driver_filter_t *filt, driver_intr_t *handler,
+ void *arg, void **cookiep)
+{
+ struct obio_softc *sc = device_get_softc(dev);
+ struct intr_event *event;
+ int irq, ip_bit, error, mask, mask_register;
+
+ irq = rman_get_start(ires);
+
+ if (irq >= NIRQS)
+ panic("%s: bad irq %d", __func__, irq);
+
+ event = sc->sc_eventstab[irq];
+ if (event == NULL) {
+ error = intr_event_create(&event, (void *)irq, 0, irq,
+ obio_mask_irq, obio_unmask_irq,
+ NULL, NULL,
+ "obio intr%d:", irq);
+
+ sc->sc_eventstab[irq] = event;
+ }
+
+ intr_event_add_handler(event, device_get_nameunit(child), filt,
+ handler, arg, intr_priority(flags), flags, cookiep);
+
+ /* unmask IRQ */
+ mask_register = ICU_IRQ_MASK_REG(irq);
+ ip_bit = ICU_IP_BIT(irq);
+
+ mask = ICU_REG_READ(mask_register);
+ ICU_REG_WRITE(mask_register, mask & ~ip_bit);
+
+ return (0);
+}
+
+static int
+obio_teardown_intr(device_t dev, device_t child, struct resource *ires,
+ void *cookie)
+{
+ struct obio_softc *sc = device_get_softc(dev);
+ int irq, result;
+ uint32_t mask_register, mask, ip_bit;
+
+ irq = rman_get_start(ires);
+ if (irq >= NIRQS)
+ panic("%s: bad irq %d", __func__, irq);
+
+ if (sc->sc_eventstab[irq] == NULL)
+ panic("Trying to teardown unoccupied IRQ");
+
+ /* mask IRQ */
+ mask_register = ICU_IRQ_MASK_REG(irq);
+ ip_bit = ICU_IP_BIT(irq);
+
+ mask = ICU_REG_READ(mask_register);
+ ICU_REG_WRITE(mask_register, mask | ip_bit);
+
+ result = intr_event_remove_handler(cookie);
+ if (!result)
+ sc->sc_eventstab[irq] = NULL;
+
+ return (result);
+}
+
+static int
+obio_intr(void *arg)
+{
+ struct obio_softc *sc = arg;
+ struct intr_event *event;
+ uint32_t irqstat, ipend, imask, xpend;
+ int irq, thread, group, i;
+
+ irqstat = 0;
+ irq = 0;
+ for (group = 2; group <= 6; group++) {
+ ipend = ICU_REG_READ(ICU_GROUP_IPEND_REG(group));
+ imask = ICU_REG_READ(ICU_GROUP_MASK_REG(group));
+ xpend = ipend;
+ ipend &= ~imask;
+
+ while ((i = fls(xpend)) != 0) {
+ xpend &= ~(1 << (i - 1));
+ irq = IP_IRQ(group, i - 1);
+ }
+
+ while ((i = fls(ipend)) != 0) {
+ ipend &= ~(1 << (i - 1));
+ irq = IP_IRQ(group, i - 1);
+ event = sc->sc_eventstab[irq];
+ thread = 0;
+ if (!event || TAILQ_EMPTY(&event->ie_handlers)) {
+ /* TODO: Log stray IRQs */
+ continue;
+ }
+
+ /* TODO: frame instead of NULL? */
+ intr_event_handle(event, NULL);
+ /* XXX: Log stray IRQs */
+ }
+ }
+#if 0
+ ipend = ICU_REG_READ(ICU_IPEND2);
+ printf("ipend2 = %08x!\n", ipend);
+
+ ipend = ICU_REG_READ(ICU_IPEND3);
+ printf("ipend3 = %08x!\n", ipend);
+
+ ipend = ICU_REG_READ(ICU_IPEND4);
+ printf("ipend4 = %08x!\n", ipend);
+ ipend = ICU_REG_READ(ICU_IPEND5);
+ printf("ipend5 = %08x!\n", ipend);
+
+ ipend = ICU_REG_READ(ICU_IPEND6);
+ printf("ipend6 = %08x!\n", ipend);
+#endif
+ while (irqstat != 0) {
+ if ((irqstat & 1) == 1) {
+ }
+
+ irq++;
+ irqstat >>= 1;
+ }
+
+ return (FILTER_HANDLED);
+}
+
+static void
+obio_hinted_child(device_t bus, const char *dname, int dunit)
+{
+ device_t child;
+ long maddr;
+ int msize;
+ int irq;
+ int result;
+
+ child = BUS_ADD_CHILD(bus, 0, dname, dunit);
+
+ /*
+ * Set hard-wired resources for hinted child using
+ * specific RIDs.
+ */
+ resource_long_value(dname, dunit, "maddr", &maddr);
+ resource_int_value(dname, dunit, "msize", &msize);
+
+
+ result = bus_set_resource(child, SYS_RES_MEMORY, 0,
+ maddr, msize);
+ if (result != 0)
+ device_printf(bus, "warning: bus_set_resource() failed\n");
+
+ if (resource_int_value(dname, dunit, "irq", &irq) == 0) {
+ result = bus_set_resource(child, SYS_RES_IRQ, 0, irq, 1);
+ if (result != 0)
+ device_printf(bus,
+ "warning: bus_set_resource() failed\n");
+ }
+}
+
+static device_t
+obio_add_child(device_t bus, u_int order, const char *name, int unit)
+{
+ device_t child;
+ struct obio_ivar *ivar;
+
+ ivar = malloc(sizeof(struct obio_ivar), M_DEVBUF, M_WAITOK | M_ZERO);
+ if (ivar == NULL) {
+ printf("Failed to allocate ivar\n");
+ return (0);
+ }
+ resource_list_init(&ivar->resources);
+
+ child = device_add_child_ordered(bus, order, name, unit);
+ if (child == NULL) {
+ printf("Can't add child %s%d ordered\n", name, unit);
+ return (0);
+ }
+
+ device_set_ivars(child, ivar);
+
+ return (child);
+}
+
+/*
+ * Helper routine for bus_generic_rl_get_resource/bus_generic_rl_set_resource
+ * Provides pointer to resource_list for these routines
+ */
+static struct resource_list *
+obio_get_resource_list(device_t dev, device_t child)
+{
+ struct obio_ivar *ivar;
+
+ ivar = device_get_ivars(child);
+ return (&(ivar->resources));
+}
+
+static device_method_t obio_methods[] = {
+ DEVMETHOD(bus_activate_resource, obio_activate_resource),
+ DEVMETHOD(bus_add_child, obio_add_child),
+ DEVMETHOD(bus_alloc_resource, obio_alloc_resource),
+ DEVMETHOD(bus_deactivate_resource, obio_deactivate_resource),
+ DEVMETHOD(bus_get_resource_list, obio_get_resource_list),
+ DEVMETHOD(bus_hinted_child, obio_hinted_child),
+ DEVMETHOD(bus_release_resource, obio_release_resource),
+ DEVMETHOD(bus_setup_intr, obio_setup_intr),
+ DEVMETHOD(bus_teardown_intr, obio_teardown_intr),
+ DEVMETHOD(device_attach, obio_attach),
+ DEVMETHOD(device_probe, obio_probe),
+ DEVMETHOD(bus_get_resource, bus_generic_rl_get_resource),
+ DEVMETHOD(bus_set_resource, bus_generic_rl_set_resource),
+
+ {0, 0},
+};
+
+static driver_t obio_driver = {
+ "obio",
+ obio_methods,
+ sizeof(struct obio_softc),
+};
+static devclass_t obio_devclass;
+
+DRIVER_MODULE(obio, nexus, obio_driver, obio_devclass, 0, 0);
Property changes on: trunk/sys/mips/idt/obio.c
___________________________________________________________________
Added: svn:eol-style
## -0,0 +1 ##
+native
\ No newline at end of property
Added: svn:keywords
## -0,0 +1 ##
+MidnightBSD=%H
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+text/plain
\ No newline at end of property
Added: trunk/sys/mips/idt/obiovar.h
===================================================================
--- trunk/sys/mips/idt/obiovar.h (rev 0)
+++ trunk/sys/mips/idt/obiovar.h 2018-05-26 21:55:02 UTC (rev 9987)
@@ -0,0 +1,68 @@
+/* $MidnightBSD$ */
+/* $NetBSD: obiovar.h,v 1.4 2003/06/16 17:40:53 thorpej Exp $ */
+
+/*-
+ * Copyright (c) 2002, 2003 Wasabi Systems, Inc.
+ * All rights reserved.
+ *
+ * Written by Jason R. Thorpe for Wasabi Systems, Inc.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * 3. All advertising materials mentioning features or use of this software
+ * must display the following acknowledgement:
+ * This product includes software developed for the NetBSD Project by
+ * Wasabi Systems, Inc.
+ * 4. The name of Wasabi Systems, Inc. may not be used to endorse
+ * or promote products derived from this software without specific prior
+ * written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * $FreeBSD: stable/10/sys/mips/idt/obiovar.h 202175 2010-01-12 21:36:08Z imp $
+ *
+ */
+
+#ifndef _ADM5120_OBIOVAR_H_
+#define _ADM5120_OBIOVAR_H_
+
+#include <sys/rman.h>
+
+/* Number of controller's IRQs */
+#define NIRQS 32*5
+
+/* Number of CPU IRQ lines */
+#define MIPS_IRQS 5
+
+#define OBIO_MEM_START 0x18000000L
+#define OBIO_MEM_SIZE 0x200000
+
+struct obio_softc {
+ struct rman oba_mem_rman;
+ struct rman oba_irq_rman;
+ struct intr_event *sc_eventstab[NIRQS]; /* IRQ events structs */
+ struct resource *sc_irq[MIPS_IRQS]; /* IRQ resource */
+ void *sc_ih[MIPS_IRQS]; /* interrupt cookie */
+};
+
+struct obio_ivar {
+ struct resource_list resources;
+};
+
+#endif /* _ADM5120_OBIOVAR_H_ */
Property changes on: trunk/sys/mips/idt/obiovar.h
___________________________________________________________________
Added: svn:eol-style
## -0,0 +1 ##
+native
\ No newline at end of property
Added: svn:keywords
## -0,0 +1 ##
+MidnightBSD=%H
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+text/plain
\ No newline at end of property
Added: trunk/sys/mips/idt/std.idt
===================================================================
--- trunk/sys/mips/idt/std.idt (rev 0)
+++ trunk/sys/mips/idt/std.idt 2018-05-26 21:55:02 UTC (rev 9987)
@@ -0,0 +1,6 @@
+# $FreeBSD: stable/10/sys/mips/idt/std.idt 232896 2012-03-12 21:25:32Z jmallett $
+# Standard include file for IDT
+
+files "../idt/files.idt"
+
+machine mips mipsel
Property changes on: trunk/sys/mips/idt/std.idt
___________________________________________________________________
Added: mnbsd:nokeywords
## -0,0 +1 ##
+MidnightBSD=%H
\ No newline at end of property
Added: trunk/sys/mips/idt/uart_bus_rc32434.c
===================================================================
--- trunk/sys/mips/idt/uart_bus_rc32434.c (rev 0)
+++ trunk/sys/mips/idt/uart_bus_rc32434.c 2018-05-26 21:55:02 UTC (rev 9987)
@@ -0,0 +1,101 @@
+/* $MidnightBSD$ */
+/*-
+ * Copyright (c) 2007 Bruce M. Simpson.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * $Id$
+ */
+/*
+ * Skeleton of this file was based on respective code for ARM
+ * code written by Olivier Houchard.
+ */
+
+/*
+ * XXXMIPS: This file is hacked from arm/... . XXXMIPS here means this file is
+ * experimental and was written for MIPS32 port.
+ */
+#include "opt_uart.h"
+
+#include <sys/cdefs.h>
+__FBSDID("$FreeBSD: stable/10/sys/mips/idt/uart_bus_rc32434.c 202175 2010-01-12 21:36:08Z imp $");
+
+#include <sys/param.h>
+#include <sys/systm.h>
+#include <sys/bus.h>
+#include <sys/conf.h>
+#include <sys/kernel.h>
+#include <sys/module.h>
+#include <machine/bus.h>
+#include <sys/rman.h>
+#include <machine/resource.h>
+#include <mips/idt/idtreg.h>
+
+#include <dev/pci/pcivar.h>
+
+#include <dev/uart/uart.h>
+#include <dev/uart/uart_bus.h>
+#include <dev/uart/uart_cpu.h>
+
+#include <dev/ic/ns16550.h>
+
+#include "uart_if.h"
+
+static int uart_rc32434_probe(device_t dev);
+
+extern struct uart_class uart_rc32434_uart_class;
+
+static device_method_t uart_rc32434_methods[] = {
+ /* Device interface */
+ DEVMETHOD(device_probe, uart_rc32434_probe),
+ DEVMETHOD(device_attach, uart_bus_attach),
+ DEVMETHOD(device_detach, uart_bus_detach),
+ { 0, 0 }
+};
+
+static driver_t uart_rc32434_driver = {
+ uart_driver_name,
+ uart_rc32434_methods,
+ sizeof(struct uart_softc),
+};
+
+extern SLIST_HEAD(uart_devinfo_list, uart_devinfo) uart_sysdevs;
+
+static int
+uart_rc32434_probe(device_t dev)
+{
+ struct uart_softc *sc;
+
+ sc = device_get_softc(dev);
+ sc->sc_sysdev = SLIST_FIRST(&uart_sysdevs);
+ sc->sc_class = &uart_ns8250_class;
+ bcopy(&sc->sc_sysdev->bas, &sc->sc_bas, sizeof(sc->sc_bas));
+ sc->sc_sysdev->bas.regshft = 2;
+ sc->sc_sysdev->bas.bst = mips_bus_space_generic;
+ sc->sc_sysdev->bas.bsh = MIPS_PHYS_TO_KSEG1(IDT_BASE_UART0);
+ sc->sc_bas.regshft = 2;
+ sc->sc_bas.bst = mips_bus_space_generic;
+ sc->sc_bas.bsh = MIPS_PHYS_TO_KSEG1(IDT_BASE_UART0);
+
+ return (uart_bus_probe(dev, 2, 330000000UL/2, 0, 0));
+}
+
+DRIVER_MODULE(uart, obio, uart_rc32434_driver, uart_devclass, 0, 0);
Property changes on: trunk/sys/mips/idt/uart_bus_rc32434.c
___________________________________________________________________
Added: svn:eol-style
## -0,0 +1 ##
+native
\ No newline at end of property
Added: svn:keywords
## -0,0 +1 ##
+MidnightBSD=%H
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+text/plain
\ No newline at end of property
Added: trunk/sys/mips/idt/uart_cpu_rc32434.c
===================================================================
--- trunk/sys/mips/idt/uart_cpu_rc32434.c (rev 0)
+++ trunk/sys/mips/idt/uart_cpu_rc32434.c 2018-05-26 21:55:02 UTC (rev 9987)
@@ -0,0 +1,86 @@
+/* $MidnightBSD$ */
+/*-
+ * Copyright (c) 2006 Wojciech A. Koszek <wkoszek at FreeBSD.org>
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ * $Id$
+ */
+/*
+ * Skeleton of this file was based on respective code for ARM
+ * code written by Olivier Houchard.
+ */
+/*
+ * XXXMIPS: This file is hacked from arm/... . XXXMIPS here means this file is
+ * experimental and was written for MIPS32 port.
+ */
+#include "opt_uart.h"
+
+#include <sys/cdefs.h>
+__FBSDID("$FreeBSD: stable/10/sys/mips/idt/uart_cpu_rc32434.c 202175 2010-01-12 21:36:08Z imp $");
+
+#include <sys/param.h>
+#include <sys/systm.h>
+#include <sys/bus.h>
+#include <sys/cons.h>
+
+#include <machine/bus.h>
+
+#include <dev/uart/uart.h>
+#include <dev/uart/uart_cpu.h>
+
+extern struct uart_class uart_rc32434_uart_class;
+bus_space_tag_t uart_bus_space_io;
+bus_space_tag_t uart_bus_space_mem;
+
+int
+uart_cpu_eqres(struct uart_bas *b1, struct uart_bas *b2)
+{
+
+ return ((b1->bsh == b2->bsh && b1->bst == b2->bst) ? 1 : 0);
+}
+
+int
+uart_cpu_getdev(int devtype, struct uart_devinfo *di)
+{
+ uint32_t maddr;
+
+ if (resource_int_value("uart", 0, "maddr", &maddr) != 0 ||
+ maddr == 0)
+ return (ENXIO);
+
+ /* Got it. Fill in the instance and return it. */
+ di->ops = uart_getops(&uart_ns8250_class);
+ di->bas.chan = 0;
+ di->bas.bst = mips_bus_space_generic;
+ di->bas.regshft = 2;
+ di->bas.rclk = 330000000UL/2; /* IPbus clock */
+ di->baudrate = 115200;
+ di->databits = 8;
+ di->stopbits = 1;
+ di->parity = UART_PARITY_NONE;
+ uart_bus_space_io = 0;
+ uart_bus_space_mem = mips_bus_space_generic;
+ di->bas.bsh = MIPS_PHYS_TO_KSEG1(maddr);
+ return (0);
+}
Property changes on: trunk/sys/mips/idt/uart_cpu_rc32434.c
___________________________________________________________________
Added: svn:eol-style
## -0,0 +1 ##
+native
\ No newline at end of property
Added: svn:keywords
## -0,0 +1 ##
+MidnightBSD=%H
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+text/plain
\ No newline at end of property
Added: trunk/sys/mips/include/_align.h
===================================================================
--- trunk/sys/mips/include/_align.h (rev 0)
+++ trunk/sys/mips/include/_align.h 2018-05-26 21:55:02 UTC (rev 9987)
@@ -0,0 +1,54 @@
+/* $MidnightBSD$ */
+/* $OpenBSD: param.h,v 1.11 1998/08/30 22:05:35 millert Exp $ */
+
+/*-
+ * Copyright (c) 1988 University of Utah.
+ * Copyright (c) 1992, 1993
+ * The Regents of the University of California. All rights reserved.
+ *
+ * This code is derived from software contributed to Berkeley by
+ * the Systems Programming Group of the University of Utah Computer
+ * Science Department and Ralph Campbell.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * 4. Neither the name of the University nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ * from: Utah Hdr: machparam.h 1.11 89/08/14
+ * from: @(#)param.h 8.1 (Berkeley) 6/10/93
+ * JNPR: param.h,v 1.6.2.1 2007/09/10 07:49:36 girish
+ * $FreeBSD: stable/10/sys/mips/include/_align.h 202175 2010-01-12 21:36:08Z imp $
+ */
+
+#ifndef _MIPS_INCLUDE__ALIGN_H_
+#define _MIPS_INCLUDE__ALIGN_H_
+
+/*
+ * Round p (pointer or byte index) up to a correctly-aligned value for all
+ * data types (int, long, ...). The result is u_long and must be cast to
+ * any desired pointer type.
+ */
+#define _ALIGNBYTES 7
+#define _ALIGN(p) (((u_long)(p) + _ALIGNBYTES) &~ _ALIGNBYTES)
+
+#endif /* !_MIPS_INCLUDE__ALIGN_H_ */
Property changes on: trunk/sys/mips/include/_align.h
___________________________________________________________________
Added: svn:eol-style
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+native
\ No newline at end of property
Added: svn:keywords
## -0,0 +1 ##
+MidnightBSD=%H
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+text/plain
\ No newline at end of property
Added: trunk/sys/mips/include/_bus.h
===================================================================
--- trunk/sys/mips/include/_bus.h (rev 0)
+++ trunk/sys/mips/include/_bus.h 2018-05-26 21:55:02 UTC (rev 9987)
@@ -0,0 +1,51 @@
+/* $MidnightBSD$ */
+/*-
+ * Copyright (c) 2005 M. Warner Losh.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions, and the following disclaimer,
+ * without modification, immediately at the beginning of the file.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in
+ * the documentation and/or other materials provided with the
+ * distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ * from: src/sys/i386/include/_bus.h,v 1.1 2005/04/18 21:45:33 imp
+ * $FreeBSD: stable/10/sys/mips/include/_bus.h 232896 2012-03-12 21:25:32Z jmallett $
+ */
+
+#ifndef MIPS_INCLUDE__BUS_H
+#define MIPS_INCLUDE__BUS_H
+
+/*
+ * Bus address and size types
+ */
+#if defined(CPU_CNMIPS) && !defined(__mips_n64)
+typedef uint64_t bus_addr_t;
+#else
+typedef uintptr_t bus_addr_t;
+#endif
+typedef uintptr_t bus_size_t;
+
+/*
+ * Access methods for bus resources and address space.
+ */
+typedef struct bus_space *bus_space_tag_t;
+typedef bus_addr_t bus_space_handle_t;
+#endif /* MIPS_INCLUDE__BUS_H */
Property changes on: trunk/sys/mips/include/_bus.h
___________________________________________________________________
Added: svn:eol-style
## -0,0 +1 ##
+native
\ No newline at end of property
Added: svn:keywords
## -0,0 +1 ##
+MidnightBSD=%H
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+text/plain
\ No newline at end of property
Added: trunk/sys/mips/include/_inttypes.h
===================================================================
--- trunk/sys/mips/include/_inttypes.h (rev 0)
+++ trunk/sys/mips/include/_inttypes.h 2018-05-26 21:55:02 UTC (rev 9987)
@@ -0,0 +1,223 @@
+/* $MidnightBSD$ */
+/*-
+ * Copyright (c) 2001 The NetBSD Foundation, Inc.
+ * All rights reserved.
+ *
+ * This code is derived from software contributed to The NetBSD Foundation
+ * by Klaus Klein.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
+ * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * From: $NetBSD: int_fmtio.h,v 1.2 2001/04/26 16:25:21 kleink Exp $
+ * from: src/sys/i386/include/_inttypes.h,v 1.2 2002/06/30 05:48:02 mike
+ * $FreeBSD: stable/10/sys/mips/include/_inttypes.h 218266 2011-02-04 13:09:46Z tijl $
+ */
+
+#ifndef _MACHINE_INTTYPES_H_
+#define _MACHINE_INTTYPES_H_
+
+/*
+ * Macros for format specifiers.
+ */
+
+#ifdef __mips_n64
+#define __PRI64 "l"
+#define __PRIptr "l"
+#else
+#define __PRI64 "ll"
+#define __PRIptr
+#endif
+
+/* fprintf(3) macros for signed integers. */
+
+#define PRId8 "d" /* int8_t */
+#define PRId16 "d" /* int16_t */
+#define PRId32 "d" /* int32_t */
+#define PRId64 __PRI64"d" /* int64_t */
+#define PRIdLEAST8 "d" /* int_least8_t */
+#define PRIdLEAST16 "d" /* int_least16_t */
+#define PRIdLEAST32 "d" /* int_least32_t */
+#define PRIdLEAST64 __PRI64"d" /* int_least64_t */
+#define PRIdFAST8 "d" /* int_fast8_t */
+#define PRIdFAST16 "d" /* int_fast16_t */
+#define PRIdFAST32 "d" /* int_fast32_t */
+#define PRIdFAST64 __PRI64"d" /* int_fast64_t */
+#define PRIdMAX "jd" /* intmax_t */
+#define PRIdPTR __PRIptr"d" /* intptr_t */
+
+#define PRIi8 "i" /* int8_t */
+#define PRIi16 "i" /* int16_t */
+#define PRIi32 "i" /* int32_t */
+#define PRIi64 __PRI64"i" /* int64_t */
+#define PRIiLEAST8 "i" /* int_least8_t */
+#define PRIiLEAST16 "i" /* int_least16_t */
+#define PRIiLEAST32 "i" /* int_least32_t */
+#define PRIiLEAST64 __PRI64"i" /* int_least64_t */
+#define PRIiFAST8 "i" /* int_fast8_t */
+#define PRIiFAST16 "i" /* int_fast16_t */
+#define PRIiFAST32 "i" /* int_fast32_t */
+#define PRIiFAST64 __PRI64"i" /* int_fast64_t */
+#define PRIiMAX "ji" /* intmax_t */
+#define PRIiPTR __PRIptr"i" /* intptr_t */
+
+/* fprintf(3) macros for unsigned integers. */
+
+#define PRIo8 "o" /* uint8_t */
+#define PRIo16 "o" /* uint16_t */
+#define PRIo32 "o" /* uint32_t */
+#define PRIo64 __PRI64"o" /* uint64_t */
+#define PRIoLEAST8 "o" /* uint_least8_t */
+#define PRIoLEAST16 "o" /* uint_least16_t */
+#define PRIoLEAST32 "o" /* uint_least32_t */
+#define PRIoLEAST64 __PRI64"o" /* uint_least64_t */
+#define PRIoFAST8 "o" /* uint_fast8_t */
+#define PRIoFAST16 "o" /* uint_fast16_t */
+#define PRIoFAST32 "o" /* uint_fast32_t */
+#define PRIoFAST64 __PRI64"o" /* uint_fast64_t */
+#define PRIoMAX "jo" /* uintmax_t */
+#define PRIoPTR __PRIptr"o" /* uintptr_t */
+
+#define PRIu8 "u" /* uint8_t */
+#define PRIu16 "u" /* uint16_t */
+#define PRIu32 "u" /* uint32_t */
+#define PRIu64 __PRI64"u" /* uint64_t */
+#define PRIuLEAST8 "u" /* uint_least8_t */
+#define PRIuLEAST16 "u" /* uint_least16_t */
+#define PRIuLEAST32 "u" /* uint_least32_t */
+#define PRIuLEAST64 __PRI64"u" /* uint_least64_t */
+#define PRIuFAST8 "u" /* uint_fast8_t */
+#define PRIuFAST16 "u" /* uint_fast16_t */
+#define PRIuFAST32 "u" /* uint_fast32_t */
+#define PRIuFAST64 __PRI64"u" /* uint_fast64_t */
+#define PRIuMAX "ju" /* uintmax_t */
+#define PRIuPTR __PRIptr"u" /* uintptr_t */
+
+#define PRIx8 "x" /* uint8_t */
+#define PRIx16 "x" /* uint16_t */
+#define PRIx32 "x" /* uint32_t */
+#define PRIx64 __PRI64"x" /* uint64_t */
+#define PRIxLEAST8 "x" /* uint_least8_t */
+#define PRIxLEAST16 "x" /* uint_least16_t */
+#define PRIxLEAST32 "x" /* uint_least32_t */
+#define PRIxLEAST64 __PRI64"x" /* uint_least64_t */
+#define PRIxFAST8 "x" /* uint_fast8_t */
+#define PRIxFAST16 "x" /* uint_fast16_t */
+#define PRIxFAST32 "x" /* uint_fast32_t */
+#define PRIxFAST64 __PRI64"x" /* uint_fast64_t */
+#define PRIxMAX "jx" /* uintmax_t */
+#define PRIxPTR __PRIptr"x" /* uintptr_t */
+
+#define PRIX8 "X" /* uint8_t */
+#define PRIX16 "X" /* uint16_t */
+#define PRIX32 "X" /* uint32_t */
+#define PRIX64 __PRI64"X" /* uint64_t */
+#define PRIXLEAST8 "X" /* uint_least8_t */
+#define PRIXLEAST16 "X" /* uint_least16_t */
+#define PRIXLEAST32 "X" /* uint_least32_t */
+#define PRIXLEAST64 __PRI64"X" /* uint_least64_t */
+#define PRIXFAST8 "X" /* uint_fast8_t */
+#define PRIXFAST16 "X" /* uint_fast16_t */
+#define PRIXFAST32 "X" /* uint_fast32_t */
+#define PRIXFAST64 __PRI64"X" /* uint_fast64_t */
+#define PRIXMAX "jX" /* uintmax_t */
+#define PRIXPTR __PRIptr"X" /* uintptr_t */
+
+/* fscanf(3) macros for signed integers. */
+
+#define SCNd8 "hhd" /* int8_t */
+#define SCNd16 "hd" /* int16_t */
+#define SCNd32 "d" /* int32_t */
+#define SCNd64 __PRI64"d" /* int64_t */
+#define SCNdLEAST8 "hhd" /* int_least8_t */
+#define SCNdLEAST16 "hd" /* int_least16_t */
+#define SCNdLEAST32 "d" /* int_least32_t */
+#define SCNdLEAST64 __PRI64"d" /* int_least64_t */
+#define SCNdFAST8 "d" /* int_fast8_t */
+#define SCNdFAST16 "d" /* int_fast16_t */
+#define SCNdFAST32 "d" /* int_fast32_t */
+#define SCNdFAST64 __PRI64"d" /* int_fast64_t */
+#define SCNdMAX "jd" /* intmax_t */
+#define SCNdPTR __PRIptr"d" /* intptr_t */
+
+#define SCNi8 "hhi" /* int8_t */
+#define SCNi16 "hi" /* int16_t */
+#define SCNi32 "i" /* int32_t */
+#define SCNi64 __PRI64"i" /* int64_t */
+#define SCNiLEAST8 "hhi" /* int_least8_t */
+#define SCNiLEAST16 "hi" /* int_least16_t */
+#define SCNiLEAST32 "i" /* int_least32_t */
+#define SCNiLEAST64 __PRI64"i" /* int_least64_t */
+#define SCNiFAST8 "i" /* int_fast8_t */
+#define SCNiFAST16 "i" /* int_fast16_t */
+#define SCNiFAST32 "i" /* int_fast32_t */
+#define SCNiFAST64 __PRI64"i" /* int_fast64_t */
+#define SCNiMAX "ji" /* intmax_t */
+#define SCNiPTR __PRIptr"i" /* intptr_t */
+
+/* fscanf(3) macros for unsigned integers. */
+
+#define SCNo8 "hho" /* uint8_t */
+#define SCNo16 "ho" /* uint16_t */
+#define SCNo32 "o" /* uint32_t */
+#define SCNo64 __PRI64"o" /* uint64_t */
+#define SCNoLEAST8 "hho" /* uint_least8_t */
+#define SCNoLEAST16 "ho" /* uint_least16_t */
+#define SCNoLEAST32 "o" /* uint_least32_t */
+#define SCNoLEAST64 __PRI64"o" /* uint_least64_t */
+#define SCNoFAST8 "o" /* uint_fast8_t */
+#define SCNoFAST16 "o" /* uint_fast16_t */
+#define SCNoFAST32 "o" /* uint_fast32_t */
+#define SCNoFAST64 __PRI64"o" /* uint_fast64_t */
+#define SCNoMAX "jo" /* uintmax_t */
+#define SCNoPTR __PRIptr"o" /* uintptr_t */
+
+#define SCNu8 "hhu" /* uint8_t */
+#define SCNu16 "hu" /* uint16_t */
+#define SCNu32 "u" /* uint32_t */
+#define SCNu64 __PRI64"u" /* uint64_t */
+#define SCNuLEAST8 "hhu" /* uint_least8_t */
+#define SCNuLEAST16 "hu" /* uint_least16_t */
+#define SCNuLEAST32 "u" /* uint_least32_t */
+#define SCNuLEAST64 __PRI64"u" /* uint_least64_t */
+#define SCNuFAST8 "u" /* uint_fast8_t */
+#define SCNuFAST16 "u" /* uint_fast16_t */
+#define SCNuFAST32 "u" /* uint_fast32_t */
+#define SCNuFAST64 __PRI64"u" /* uint_fast64_t */
+#define SCNuMAX "ju" /* uintmax_t */
+#define SCNuPTR __PRIptr"u" /* uintptr_t */
+
+#define SCNx8 "hhx" /* uint8_t */
+#define SCNx16 "hx" /* uint16_t */
+#define SCNx32 "x" /* uint32_t */
+#define SCNx64 __PRI64"x" /* uint64_t */
+#define SCNxLEAST8 "hhx" /* uint_least8_t */
+#define SCNxLEAST16 "hx" /* uint_least16_t */
+#define SCNxLEAST32 "x" /* uint_least32_t */
+#define SCNxLEAST64 __PRI64"x" /* uint_least64_t */
+#define SCNxFAST8 "x" /* uint_fast8_t */
+#define SCNxFAST16 "x" /* uint_fast16_t */
+#define SCNxFAST32 "x" /* uint_fast32_t */
+#define SCNxFAST64 __PRI64"x" /* uint_fast64_t */
+#define SCNxMAX "jx" /* uintmax_t */
+#define SCNxPTR __PRIptr"x" /* uintptr_t */
+
+#endif /* !_MACHINE_INTTYPES_H_ */
Property changes on: trunk/sys/mips/include/_inttypes.h
___________________________________________________________________
Added: svn:eol-style
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+native
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+MidnightBSD=%H
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+text/plain
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Added: trunk/sys/mips/include/_limits.h
===================================================================
--- trunk/sys/mips/include/_limits.h (rev 0)
+++ trunk/sys/mips/include/_limits.h 2018-05-26 21:55:02 UTC (rev 9987)
@@ -0,0 +1,95 @@
+/* $MidnightBSD$ */
+/*-
+ * Copyright (c) 1988, 1993
+ * The Regents of the University of California. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * 4. Neither the name of the University nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ * @(#)limits.h 8.3 (Berkeley) 1/4/94
+ * from: src/sys/i386/include/_limits.h,v 1.27 2005/01/06 22:18:15 imp
+ * $FreeBSD: stable/10/sys/mips/include/_limits.h 218266 2011-02-04 13:09:46Z tijl $
+ */
+
+#ifndef _MACHINE__LIMITS_H_
+#define _MACHINE__LIMITS_H_
+
+/*
+ * According to ANSI (section 2.2.4.2), the values below must be usable by
+ * #if preprocessing directives. Additionally, the expression must have the
+ * same type as would an expression that is an object of the corresponding
+ * type converted according to the integral promotions. The subtraction for
+ * INT_MIN, etc., is so the value is not unsigned; e.g., 0x80000000 is an
+ * unsigned int for 32-bit two's complement ANSI compilers (section 3.1.3.2).
+ */
+
+#define __CHAR_BIT 8 /* number of bits in a char */
+
+#define __SCHAR_MAX 0x7f /* max value for a signed char */
+#define __SCHAR_MIN (-0x7f - 1) /* min value for a signed char */
+
+#define __UCHAR_MAX 0xff /* max value for an unsigned char */
+
+#define __USHRT_MAX 0xffff /* max value for an unsigned short */
+#define __SHRT_MAX 0x7fff /* max value for a short */
+#define __SHRT_MIN (-0x7fff - 1) /* min value for a short */
+
+#define __UINT_MAX 0xffffffff /* max value for an unsigned int */
+#define __INT_MAX 0x7fffffff /* max value for an int */
+#define __INT_MIN (-0x7fffffff - 1) /* min value for an int */
+
+#ifdef __mips_n64
+#define __ULONG_MAX 0xffffffffffffffff
+#define __LONG_MAX 0x7fffffffffffffff
+#define __LONG_MIN (-0x7fffffffffffffff - 1)
+#define __LONG_BIT 64
+#else
+#define __ULONG_MAX 0xffffffffUL /* max value for an unsigned long */
+#define __LONG_MAX 0x7fffffffL /* max value for a long */
+#define __LONG_MIN (-0x7fffffffL - 1) /* min value for a long */
+#define __LONG_BIT 32
+#endif
+
+ /* max value for an unsigned long long */
+#define __ULLONG_MAX 0xffffffffffffffffULL
+#define __LLONG_MAX 0x7fffffffffffffffLL /* max value for a long long */
+#define __LLONG_MIN (-0x7fffffffffffffffLL - 1) /* min for a long long */
+
+#define __SSIZE_MAX __LONG_MAX /* max value for a ssize_t */
+
+#define __SIZE_T_MAX __ULONG_MAX /* max value for a size_t */
+
+#define __OFF_MAX __LLONG_MAX /* max value for an off_t */
+#define __OFF_MIN __LLONG_MIN /* min value for an off_t */
+
+/* Quads and long longs are the same size. Ensure they stay in sync. */
+#define __UQUAD_MAX __ULLONG_MAX /* max value for a uquad_t */
+#define __QUAD_MAX __LLONG_MAX /* max value for a quad_t */
+#define __QUAD_MIN __LLONG_MIN /* min value for a quad_t */
+
+#define __WORD_BIT 32
+
+#define __MINSIGSTKSZ (512 * 4)
+
+#endif /* !_MACHINE__LIMITS_H_ */
Property changes on: trunk/sys/mips/include/_limits.h
___________________________________________________________________
Added: svn:eol-style
## -0,0 +1 ##
+native
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+MidnightBSD=%H
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+text/plain
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Added: trunk/sys/mips/include/_stdint.h
===================================================================
--- trunk/sys/mips/include/_stdint.h (rev 0)
+++ trunk/sys/mips/include/_stdint.h 2018-05-26 21:55:02 UTC (rev 9987)
@@ -0,0 +1,198 @@
+/* $MidnightBSD$ */
+/*-
+ * Copyright (c) 2001, 2002 Mike Barcroft <mike at FreeBSD.org>
+ * Copyright (c) 2001 The NetBSD Foundation, Inc.
+ * All rights reserved.
+ *
+ * This code is derived from software contributed to The NetBSD Foundation
+ * by Klaus Klein.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * 3. All advertising materials mentioning features or use of this software
+ * must display the following acknowledgement:
+ * This product includes software developed by the NetBSD
+ * Foundation, Inc. and its contributors.
+ * 4. Neither the name of The NetBSD Foundation nor the names of its
+ * contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
+ * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * from: src/sys/i386/include/_stdint.h,v 1.2 2004/05/18 16:04:57 stefanf
+ * $FreeBSD: stable/10/sys/mips/include/_stdint.h 255194 2013-09-03 22:04:55Z imp $
+ */
+
+#ifndef _MACHINE__STDINT_H_
+#define _MACHINE__STDINT_H_
+
+#if !defined(__cplusplus) || defined(__STDC_CONSTANT_MACROS)
+
+#define INT8_C(c) (c)
+#define INT16_C(c) (c)
+#define INT32_C(c) (c)
+
+#define UINT8_C(c) (c)
+#define UINT16_C(c) (c)
+#define UINT32_C(c) (c ## U)
+
+#ifdef __mips_n64
+#define INT64_C(c) (c ## L)
+#define UINT64_C(c) (c ## UL)
+#else
+#define INT64_C(c) (c ## LL)
+#define UINT64_C(c) (c ## ULL)
+#endif
+
+#define INTMAX_C(c) INT64_C(c)
+#define UINTMAX_C(c) UINT64_C(c)
+
+#endif /* !defined(__cplusplus) || defined(__STDC_CONSTANT_MACROS) */
+
+#if !defined(__cplusplus) || defined(__STDC_LIMIT_MACROS)
+
+#ifndef __INT64_C
+#ifdef __mips_n64
+#define __INT64_C(c) (c ## L)
+#define __UINT64_C(c) (c ## UL)
+#else
+#define __INT64_C(c) (c ## LL)
+#define __UINT64_C(c) (c ## ULL)
+#endif
+#endif
+
+/*
+ * ISO/IEC 9899:1999
+ * 7.18.2.1 Limits of exact-width integer types
+ */
+/* Minimum values of exact-width signed integer types. */
+#define INT8_MIN (-0x7f-1)
+#define INT16_MIN (-0x7fff-1)
+#define INT32_MIN (-0x7fffffff-1)
+#define INT64_MIN (-__INT64_C(0x7fffffffffffffff)-1)
+
+/* Maximum values of exact-width signed integer types. */
+#define INT8_MAX 0x7f
+#define INT16_MAX 0x7fff
+#define INT32_MAX 0x7fffffff
+#define INT64_MAX __INT64_C(0x7fffffffffffffff)
+
+/* Maximum values of exact-width unsigned integer types. */
+#define UINT8_MAX 0xff
+#define UINT16_MAX 0xffff
+#define UINT32_MAX 0xffffffff
+#define UINT64_MAX __UINT64_C(0xffffffffffffffff)
+
+/*
+ * ISO/IEC 9899:1999
+ * 7.18.2.2 Limits of minimum-width integer types
+ */
+/* Minimum values of minimum-width signed integer types. */
+#define INT_LEAST8_MIN INT8_MIN
+#define INT_LEAST16_MIN INT16_MIN
+#define INT_LEAST32_MIN INT32_MIN
+#define INT_LEAST64_MIN INT64_MIN
+
+/* Maximum values of minimum-width signed integer types. */
+#define INT_LEAST8_MAX INT8_MAX
+#define INT_LEAST16_MAX INT16_MAX
+#define INT_LEAST32_MAX INT32_MAX
+#define INT_LEAST64_MAX INT64_MAX
+
+/* Maximum values of minimum-width unsigned integer types. */
+#define UINT_LEAST8_MAX UINT8_MAX
+#define UINT_LEAST16_MAX UINT16_MAX
+#define UINT_LEAST32_MAX UINT32_MAX
+#define UINT_LEAST64_MAX UINT64_MAX
+
+/*
+ * ISO/IEC 9899:1999
+ * 7.18.2.3 Limits of fastest minimum-width integer types
+ */
+/* Minimum values of fastest minimum-width signed integer types. */
+#define INT_FAST8_MIN INT32_MIN
+#define INT_FAST16_MIN INT32_MIN
+#define INT_FAST32_MIN INT32_MIN
+#define INT_FAST64_MIN INT64_MIN
+
+/* Maximum values of fastest minimum-width signed integer types. */
+#define INT_FAST8_MAX INT32_MAX
+#define INT_FAST16_MAX INT32_MAX
+#define INT_FAST32_MAX INT32_MAX
+#define INT_FAST64_MAX INT64_MAX
+
+/* Maximum values of fastest minimum-width unsigned integer types. */
+#define UINT_FAST8_MAX UINT32_MAX
+#define UINT_FAST16_MAX UINT32_MAX
+#define UINT_FAST32_MAX UINT32_MAX
+#define UINT_FAST64_MAX UINT64_MAX
+
+/*
+ * ISO/IEC 9899:1999
+ * 7.18.2.4 Limits of integer types capable of holding object pointers
+ */
+#ifdef __mips_n64
+#define INTPTR_MIN INT64_MIN
+#define INTPTR_MAX INT64_MAX
+#define UINTPTR_MAX UINT64_MAX
+#else
+#define INTPTR_MIN INT32_MIN
+#define INTPTR_MAX INT32_MAX
+#define UINTPTR_MAX UINT32_MAX
+#endif
+
+/*
+ * ISO/IEC 9899:1999
+ * 7.18.2.5 Limits of greatest-width integer types
+ */
+#define INTMAX_MIN INT64_MIN
+#define INTMAX_MAX INT64_MAX
+#define UINTMAX_MAX UINT64_MAX
+
+/*
+ * ISO/IEC 9899:1999
+ * 7.18.3 Limits of other integer types
+ */
+#ifdef __mips_n64
+/* Limits of ptrdiff_t. */
+#define PTRDIFF_MIN INT64_MIN
+#define PTRDIFF_MAX INT64_MAX
+
+/* Limit of size_t. */
+#define SIZE_MAX UINT64_MAX
+#else
+/* Limits of ptrdiff_t. */
+#define PTRDIFF_MIN INT32_MIN
+#define PTRDIFF_MAX INT32_MAX
+
+/* Limit of size_t. */
+#define SIZE_MAX UINT32_MAX
+#endif
+
+/* Limits of sig_atomic_t. */
+#define SIG_ATOMIC_MIN INT32_MIN
+#define SIG_ATOMIC_MAX INT32_MAX
+
+/* Limits of wint_t. */
+#define WINT_MIN INT32_MIN
+#define WINT_MAX INT32_MAX
+
+#endif /* !defined(__cplusplus) || defined(__STDC_LIMIT_MACROS) */
+
+#endif /* !_MACHINE__STDINT_H_ */
Property changes on: trunk/sys/mips/include/_stdint.h
___________________________________________________________________
Added: svn:eol-style
## -0,0 +1 ##
+native
\ No newline at end of property
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## -0,0 +1 ##
+MidnightBSD=%H
\ No newline at end of property
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## -0,0 +1 ##
+text/plain
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Added: trunk/sys/mips/include/_types.h
===================================================================
--- trunk/sys/mips/include/_types.h (rev 0)
+++ trunk/sys/mips/include/_types.h 2018-05-26 21:55:02 UTC (rev 9987)
@@ -0,0 +1,168 @@
+/* $MidnightBSD$ */
+/*-
+ * Copyright (c) 2002 Mike Barcroft <mike at FreeBSD.org>
+ * Copyright (c) 1990, 1993
+ * The Regents of the University of California. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * 3. All advertising materials mentioning features or use of this software
+ * must display the following acknowledgement:
+ * This product includes software developed by the University of
+ * California, Berkeley and its contributors.
+ * 4. Neither the name of the University nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ * From: @(#)ansi.h 8.2 (Berkeley) 1/4/94
+ * From: @(#)types.h 8.3 (Berkeley) 1/5/94
+ * from: src/sys/i386/include/_types.h,v 1.12 2005/07/02 23:13:31 thompsa
+ * $FreeBSD: stable/10/sys/mips/include/_types.h 264496 2014-04-15 09:41:52Z tijl $
+ */
+
+#ifndef _MACHINE__TYPES_H_
+#define _MACHINE__TYPES_H_
+
+#ifndef _SYS_CDEFS_H_
+#error this file needs sys/cdefs.h as a prerequisite
+#endif
+
+/*
+ * Basic types upon which most other types are built.
+ */
+typedef signed char __int8_t;
+typedef unsigned char __uint8_t;
+typedef short __int16_t;
+typedef unsigned short __uint16_t;
+typedef int __int32_t;
+typedef unsigned int __uint32_t;
+#ifdef __mips_n64
+typedef long __int64_t;
+typedef unsigned long __uint64_t;
+#else
+#ifndef lint
+__extension__
+#endif
+/* LONGLONG */
+typedef long long __int64_t;
+#ifndef lint
+__extension__
+#endif
+/* LONGLONG */
+typedef unsigned long long __uint64_t;
+#endif
+
+/*
+ * Standard type definitions.
+ */
+typedef __int32_t __clock_t; /* clock()... */
+typedef double __double_t;
+typedef float __float_t;
+#ifdef __mips_n64
+typedef __int64_t __critical_t;
+typedef __int64_t __intfptr_t;
+typedef __int64_t __intptr_t;
+#else
+typedef __int32_t __critical_t;
+typedef __int32_t __intfptr_t;
+typedef __int32_t __intptr_t;
+#endif
+typedef __int64_t __intmax_t;
+typedef __int32_t __int_fast8_t;
+typedef __int32_t __int_fast16_t;
+typedef __int32_t __int_fast32_t;
+typedef __int64_t __int_fast64_t;
+typedef __int8_t __int_least8_t;
+typedef __int16_t __int_least16_t;
+typedef __int32_t __int_least32_t;
+typedef __int64_t __int_least64_t;
+#if defined(__mips_n64) || defined(__mips_n32)
+typedef __int64_t __register_t;
+typedef __int64_t f_register_t;
+#else
+typedef __int32_t __register_t;
+typedef __int32_t f_register_t;
+#endif
+#ifdef __mips_n64
+typedef __int64_t __ptrdiff_t;
+typedef __int64_t __segsz_t;
+typedef __uint64_t __size_t;
+typedef __int64_t __ssize_t;
+typedef __uint64_t __uintfptr_t;
+typedef __uint64_t __uintptr_t;
+#else
+typedef __int32_t __ptrdiff_t; /* ptr1 - ptr2 */
+typedef __int32_t __segsz_t; /* segment size (in pages) */
+typedef __uint32_t __size_t; /* sizeof() */
+typedef __int32_t __ssize_t; /* byte count or error */
+typedef __uint32_t __uintfptr_t;
+typedef __uint32_t __uintptr_t;
+#endif
+typedef __int64_t __time_t; /* time()... */
+typedef __uint64_t __uintmax_t;
+typedef __uint32_t __uint_fast8_t;
+typedef __uint32_t __uint_fast16_t;
+typedef __uint32_t __uint_fast32_t;
+typedef __uint64_t __uint_fast64_t;
+typedef __uint8_t __uint_least8_t;
+typedef __uint16_t __uint_least16_t;
+typedef __uint32_t __uint_least32_t;
+typedef __uint64_t __uint_least64_t;
+#if defined(__mips_n64) || defined(__mips_n32)
+typedef __uint64_t __u_register_t;
+#else
+typedef __uint32_t __u_register_t;
+#endif
+#ifdef __mips_n64
+typedef __uint64_t __vm_offset_t;
+typedef __uint64_t __vm_size_t;
+#else
+typedef __uint32_t __vm_offset_t;
+typedef __uint32_t __vm_size_t;
+#endif
+#if defined(__mips_n64) || defined(__mips_n32) /* PHYSADDR_64_BIT */
+typedef __uint64_t __vm_paddr_t;
+#else
+typedef __uint32_t __vm_paddr_t;
+#endif
+
+typedef __int64_t __vm_ooffset_t;
+typedef __uint64_t __vm_pindex_t;
+typedef int ___wchar_t;
+
+#define __WCHAR_MIN __INT_MIN /* min value for a wchar_t */
+#define __WCHAR_MAX __INT_MAX /* max value for a wchar_t */
+
+/*
+ * Unusual type definitions.
+ */
+#ifdef __GNUCLIKE_BUILTIN_VARARGS
+typedef __builtin_va_list __va_list; /* internally known to gcc */
+#else
+typedef char * __va_list;
+#endif /* __GNUCLIKE_BUILTIN_VARARGS */
+#if defined(__GNUC_VA_LIST_COMPATIBILITY) && !defined(__GNUC_VA_LIST) \
+ && !defined(__NO_GNUC_VA_LIST)
+#define __GNUC_VA_LIST
+typedef __va_list __gnuc_va_list; /* compatibility w/GNU headers*/
+#endif
+
+#endif /* !_MACHINE__TYPES_H_ */
Property changes on: trunk/sys/mips/include/_types.h
___________________________________________________________________
Added: svn:eol-style
## -0,0 +1 ##
+native
\ No newline at end of property
Added: svn:keywords
## -0,0 +1 ##
+MidnightBSD=%H
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+text/plain
\ No newline at end of property
Added: trunk/sys/mips/include/asm.h
===================================================================
--- trunk/sys/mips/include/asm.h (rev 0)
+++ trunk/sys/mips/include/asm.h 2018-05-26 21:55:02 UTC (rev 9987)
@@ -0,0 +1,752 @@
+/* $MidnightBSD$ */
+/* $NetBSD: asm.h,v 1.29 2000/12/14 21:29:51 jeffs Exp $ */
+
+/*
+ * Copyright (c) 1992, 1993
+ * The Regents of the University of California. All rights reserved.
+ *
+ * This code is derived from software contributed to Berkeley by
+ * Ralph Campbell.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * 4. Neither the name of the University nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ * @(#)machAsmDefs.h 8.1 (Berkeley) 6/10/93
+ * JNPR: asm.h,v 1.10 2007/08/09 11:23:32 katta
+ * $FreeBSD: stable/10/sys/mips/include/asm.h 295019 2016-01-28 22:34:29Z brooks $
+ */
+
+/*
+ * machAsmDefs.h --
+ *
+ * Macros used when writing assembler programs.
+ *
+ * Copyright (C) 1989 Digital Equipment Corporation.
+ * Permission to use, copy, modify, and distribute this software and
+ * its documentation for any purpose and without fee is hereby granted,
+ * provided that the above copyright notice appears in all copies.
+ * Digital Equipment Corporation makes no representations about the
+ * suitability of this software for any purpose. It is provided "as is"
+ * without express or implied warranty.
+ *
+ * from: Header: /sprite/src/kernel/mach/ds3100.md/RCS/machAsmDefs.h,
+ * v 1.2 89/08/15 18:28:24 rab Exp SPRITE (DECWRL)
+ */
+
+#ifndef _MACHINE_ASM_H_
+#define _MACHINE_ASM_H_
+
+#include <machine/regdef.h>
+#include <machine/endian.h>
+#include <machine/cdefs.h>
+
+#undef __FBSDID
+#if !defined(lint) && !defined(STRIP_FBSDID)
+#define __FBSDID(s) .ident s
+#else
+#define __FBSDID(s) /* nothing */
+#endif
+
+/*
+ * Define -pg profile entry code.
+ * Must always be noreorder, must never use a macro instruction
+ * Final addiu to t9 must always equal the size of this _KERN_MCOUNT
+ */
+#define _KERN_MCOUNT \
+ .set push; \
+ .set noreorder; \
+ .set noat; \
+ subu sp,sp,16; \
+ sw t9,12(sp); \
+ move AT,ra; \
+ lui t9,%hi(_mcount); \
+ addiu t9,t9,%lo(_mcount); \
+ jalr t9; \
+ nop; \
+ lw t9,4(sp); \
+ addiu sp,sp,8; \
+ addiu t9,t9,40; \
+ .set pop;
+
+#ifdef GPROF
+#define MCOUNT _KERN_MCOUNT
+#else
+#define MCOUNT
+#endif
+
+#define _C_LABEL(x) x
+
+#ifdef USE_AENT
+#define AENT(x) \
+ .aent x, 0
+#else
+#define AENT(x)
+#endif
+
+/*
+ * WARN_REFERENCES: create a warning if the specified symbol is referenced
+ */
+#define WARN_REFERENCES(_sym,_msg) \
+ .section .gnu.warning. ## _sym ; .ascii _msg ; .text
+
+#ifdef __ELF__
+# define _C_LABEL(x) x
+#else
+# define _C_LABEL(x) _ ## x
+#endif
+
+/*
+ * WEAK_ALIAS: create a weak alias.
+ */
+#define WEAK_ALIAS(alias,sym) \
+ .weak alias; \
+ alias = sym
+
+/*
+ * STRONG_ALIAS: create a strong alias.
+ */
+#define STRONG_ALIAS(alias,sym) \
+ .globl alias; \
+ alias = sym
+
+#define GLOBAL(sym) \
+ .globl sym; sym:
+
+#define ENTRY(sym) \
+ .text; .globl sym; .ent sym; sym:
+
+#define ASM_ENTRY(sym) \
+ .text; .globl sym; .type sym, at function; sym:
+
+/*
+ * LEAF
+ * A leaf routine does
+ * - call no other function,
+ * - never use any register that callee-saved (S0-S8), and
+ * - not use any local stack storage.
+ */
+#define LEAF(x) \
+ .globl _C_LABEL(x); \
+ .ent _C_LABEL(x), 0; \
+_C_LABEL(x): ; \
+ .frame sp, 0, ra; \
+ MCOUNT
+
+/*
+ * LEAF_NOPROFILE
+ * No profilable leaf routine.
+ */
+#define LEAF_NOPROFILE(x) \
+ .globl _C_LABEL(x); \
+ .ent _C_LABEL(x), 0; \
+_C_LABEL(x): ; \
+ .frame sp, 0, ra
+
+/*
+ * XLEAF
+ * declare alternate entry to leaf routine
+ */
+#define XLEAF(x) \
+ .globl _C_LABEL(x); \
+ AENT (_C_LABEL(x)); \
+_C_LABEL(x):
+
+/*
+ * NESTED
+ * A function calls other functions and needs
+ * therefore stack space to save/restore registers.
+ */
+#define NESTED(x, fsize, retpc) \
+ .globl _C_LABEL(x); \
+ .ent _C_LABEL(x), 0; \
+_C_LABEL(x): ; \
+ .frame sp, fsize, retpc; \
+ MCOUNT
+
+/*
+ * NESTED_NOPROFILE(x)
+ * No profilable nested routine.
+ */
+#define NESTED_NOPROFILE(x, fsize, retpc) \
+ .globl _C_LABEL(x); \
+ .ent _C_LABEL(x), 0; \
+_C_LABEL(x): ; \
+ .frame sp, fsize, retpc
+
+/*
+ * XNESTED
+ * declare alternate entry point to nested routine.
+ */
+#define XNESTED(x) \
+ .globl _C_LABEL(x); \
+ AENT (_C_LABEL(x)); \
+_C_LABEL(x):
+
+/*
+ * END
+ * Mark end of a procedure.
+ */
+#define END(x) \
+ .end _C_LABEL(x)
+
+/*
+ * IMPORT -- import external symbol
+ */
+#define IMPORT(sym, size) \
+ .extern _C_LABEL(sym),size
+
+/*
+ * EXPORT -- export definition of symbol
+ */
+#define EXPORT(x) \
+ .globl _C_LABEL(x); \
+_C_LABEL(x):
+
+/*
+ * VECTOR
+ * exception vector entrypoint
+ * XXX: regmask should be used to generate .mask
+ */
+#define VECTOR(x, regmask) \
+ .ent _C_LABEL(x),0; \
+ EXPORT(x); \
+
+#define VECTOR_END(x) \
+ EXPORT(x ## End); \
+ END(x)
+
+/*
+ * Macros to panic and printf from assembly language.
+ */
+#define PANIC(msg) \
+ PTR_LA a0, 9f; \
+ jal _C_LABEL(panic); \
+ nop; \
+ MSG(msg)
+
+#define PANIC_KSEG0(msg, reg) PANIC(msg)
+
+#define PRINTF(msg) \
+ PTR_LA a0, 9f; \
+ jal _C_LABEL(printf); \
+ nop; \
+ MSG(msg)
+
+#define MSG(msg) \
+ .rdata; \
+9: .asciiz msg; \
+ .text
+
+#define ASMSTR(str) \
+ .asciiz str; \
+ .align 3
+
+/*
+ * Call ast if required
+ *
+ * XXX Do we really need to disable interrupts?
+ */
+#define DO_AST \
+44: \
+ mfc0 t0, MIPS_COP_0_STATUS ;\
+ and a0, t0, MIPS_SR_INT_IE ;\
+ xor t0, a0, t0 ;\
+ mtc0 t0, MIPS_COP_0_STATUS ;\
+ COP0_SYNC ;\
+ GET_CPU_PCPU(s1) ;\
+ PTR_L s3, PC_CURPCB(s1) ;\
+ PTR_L s1, PC_CURTHREAD(s1) ;\
+ lw s2, TD_FLAGS(s1) ;\
+ li s0, TDF_ASTPENDING | TDF_NEEDRESCHED;\
+ and s2, s0 ;\
+ mfc0 t0, MIPS_COP_0_STATUS ;\
+ or t0, a0, t0 ;\
+ mtc0 t0, MIPS_COP_0_STATUS ;\
+ COP0_SYNC ;\
+ beq s2, zero, 4f ;\
+ nop ;\
+ PTR_LA s0, _C_LABEL(ast) ;\
+ jalr s0 ;\
+ PTR_ADDU a0, s3, U_PCB_REGS ;\
+ j 44b ;\
+ nop ;\
+4:
+
+
+/*
+ * XXX retain dialects XXX
+ */
+#define ALEAF(x) XLEAF(x)
+#define NLEAF(x) LEAF_NOPROFILE(x)
+#define NON_LEAF(x, fsize, retpc) NESTED(x, fsize, retpc)
+#define NNON_LEAF(x, fsize, retpc) NESTED_NOPROFILE(x, fsize, retpc)
+
+#if defined(__mips_o32)
+#define SZREG 4
+#else
+#define SZREG 8
+#endif
+
+#if defined(__mips_o32) || defined(__mips_o64)
+#define ALSK 7 /* stack alignment */
+#define ALMASK -7 /* stack alignment */
+#define SZFPREG 4
+#define FP_L lwc1
+#define FP_S swc1
+#else
+#define ALSK 15 /* stack alignment */
+#define ALMASK -15 /* stack alignment */
+#define SZFPREG 8
+#define FP_L ldc1
+#define FP_S sdc1
+#endif
+
+/*
+ * standard callframe {
+ * register_t cf_pad[N]; o32/64 (N=0), n32 (N=1) n64 (N=1)
+ * register_t cf_args[4]; arg0 - arg3 (only on o32 and o64)
+ * register_t cf_gp; global pointer (only on n32 and n64)
+ * register_t cf_sp; frame pointer
+ * register_t cf_ra; return address
+ * };
+ */
+#if defined(__mips_o32) || defined(__mips_o64)
+#define CALLFRAME_SIZ (SZREG * (4 + 2))
+#define CALLFRAME_S0 0
+#elif defined(__mips_n32) || defined(__mips_n64)
+#define CALLFRAME_SIZ (SZREG * 4)
+#define CALLFRAME_S0 (CALLFRAME_SIZ - 4 * SZREG)
+#endif
+#ifndef _KERNEL
+#define CALLFRAME_GP (CALLFRAME_SIZ - 3 * SZREG)
+#endif
+#define CALLFRAME_SP (CALLFRAME_SIZ - 2 * SZREG)
+#define CALLFRAME_RA (CALLFRAME_SIZ - 1 * SZREG)
+
+/*
+ * Endian-independent assembly-code aliases for unaligned memory accesses.
+ */
+#if _BYTE_ORDER == _LITTLE_ENDIAN
+# define LWHI lwr
+# define LWLO lwl
+# define SWHI swr
+# define SWLO swl
+# if SZREG == 4
+# define REG_LHI lwr
+# define REG_LLO lwl
+# define REG_SHI swr
+# define REG_SLO swl
+# else
+# define REG_LHI ldr
+# define REG_LLO ldl
+# define REG_SHI sdr
+# define REG_SLO sdl
+# endif
+#endif
+
+#if _BYTE_ORDER == _BIG_ENDIAN
+# define LWHI lwl
+# define LWLO lwr
+# define SWHI swl
+# define SWLO swr
+# if SZREG == 4
+# define REG_LHI lwl
+# define REG_LLO lwr
+# define REG_SHI swl
+# define REG_SLO swr
+# else
+# define REG_LHI ldl
+# define REG_LLO ldr
+# define REG_SHI sdl
+# define REG_SLO sdr
+# endif
+#endif
+
+/*
+ * While it would be nice to be compatible with the SGI
+ * REG_L and REG_S macros, because they do not take parameters, it
+ * is impossible to use them with the _MIPS_SIM_ABIX32 model.
+ *
+ * These macros hide the use of mips3 instructions from the
+ * assembler to prevent the assembler from generating 64-bit style
+ * ABI calls.
+ */
+#if _MIPS_SZPTR == 32
+#define PTR_ADD add
+#define PTR_ADDI addi
+#define PTR_ADDU addu
+#define PTR_ADDIU addiu
+#define PTR_SUB add
+#define PTR_SUBI subi
+#define PTR_SUBU subu
+#define PTR_SUBIU subu
+#define PTR_L lw
+#define PTR_LA la
+#define PTR_LI li
+#define PTR_S sw
+#define PTR_SLL sll
+#define PTR_SLLV sllv
+#define PTR_SRL srl
+#define PTR_SRLV srlv
+#define PTR_SRA sra
+#define PTR_SRAV srav
+#define PTR_LL ll
+#define PTR_SC sc
+#define PTR_WORD .word
+#define PTR_SCALESHIFT 2
+#else /* _MIPS_SZPTR == 64 */
+#define PTR_ADD dadd
+#define PTR_ADDI daddi
+#define PTR_ADDU daddu
+#define PTR_ADDIU daddiu
+#define PTR_SUB dadd
+#define PTR_SUBI dsubi
+#define PTR_SUBU dsubu
+#define PTR_SUBIU dsubu
+#define PTR_L ld
+#define PTR_LA dla
+#define PTR_LI dli
+#define PTR_S sd
+#define PTR_SLL dsll
+#define PTR_SLLV dsllv
+#define PTR_SRL dsrl
+#define PTR_SRLV dsrlv
+#define PTR_SRA dsra
+#define PTR_SRAV dsrav
+#define PTR_LL lld
+#define PTR_SC scd
+#define PTR_WORD .dword
+#define PTR_SCALESHIFT 3
+#endif /* _MIPS_SZPTR == 64 */
+
+#if _MIPS_SZINT == 32
+#define INT_ADD add
+#define INT_ADDI addi
+#define INT_ADDU addu
+#define INT_ADDIU addiu
+#define INT_SUB add
+#define INT_SUBI subi
+#define INT_SUBU subu
+#define INT_SUBIU subu
+#define INT_L lw
+#define INT_LA la
+#define INT_S sw
+#define INT_SLL sll
+#define INT_SLLV sllv
+#define INT_SRL srl
+#define INT_SRLV srlv
+#define INT_SRA sra
+#define INT_SRAV srav
+#define INT_LL ll
+#define INT_SC sc
+#define INT_WORD .word
+#define INT_SCALESHIFT 2
+#else
+#define INT_ADD dadd
+#define INT_ADDI daddi
+#define INT_ADDU daddu
+#define INT_ADDIU daddiu
+#define INT_SUB dadd
+#define INT_SUBI dsubi
+#define INT_SUBU dsubu
+#define INT_SUBIU dsubu
+#define INT_L ld
+#define INT_LA dla
+#define INT_S sd
+#define INT_SLL dsll
+#define INT_SLLV dsllv
+#define INT_SRL dsrl
+#define INT_SRLV dsrlv
+#define INT_SRA dsra
+#define INT_SRAV dsrav
+#define INT_LL lld
+#define INT_SC scd
+#define INT_WORD .dword
+#define INT_SCALESHIFT 3
+#endif
+
+#if _MIPS_SZLONG == 32
+#define LONG_ADD add
+#define LONG_ADDI addi
+#define LONG_ADDU addu
+#define LONG_ADDIU addiu
+#define LONG_SUB add
+#define LONG_SUBI subi
+#define LONG_SUBU subu
+#define LONG_SUBIU subu
+#define LONG_L lw
+#define LONG_LA la
+#define LONG_S sw
+#define LONG_SLL sll
+#define LONG_SLLV sllv
+#define LONG_SRL srl
+#define LONG_SRLV srlv
+#define LONG_SRA sra
+#define LONG_SRAV srav
+#define LONG_LL ll
+#define LONG_SC sc
+#define LONG_WORD .word
+#define LONG_SCALESHIFT 2
+#else
+#define LONG_ADD dadd
+#define LONG_ADDI daddi
+#define LONG_ADDU daddu
+#define LONG_ADDIU daddiu
+#define LONG_SUB dadd
+#define LONG_SUBI dsubi
+#define LONG_SUBU dsubu
+#define LONG_SUBIU dsubu
+#define LONG_L ld
+#define LONG_LA dla
+#define LONG_S sd
+#define LONG_SLL dsll
+#define LONG_SLLV dsllv
+#define LONG_SRL dsrl
+#define LONG_SRLV dsrlv
+#define LONG_SRA dsra
+#define LONG_SRAV dsrav
+#define LONG_LL lld
+#define LONG_SC scd
+#define LONG_WORD .dword
+#define LONG_SCALESHIFT 3
+#endif
+
+#if SZREG == 4
+#define REG_L lw
+#define REG_S sw
+#define REG_LI li
+#define REG_ADDU addu
+#define REG_SLL sll
+#define REG_SLLV sllv
+#define REG_SRL srl
+#define REG_SRLV srlv
+#define REG_SRA sra
+#define REG_SRAV srav
+#define REG_LL ll
+#define REG_SC sc
+#define REG_SCALESHIFT 2
+#else
+#define REG_L ld
+#define REG_S sd
+#define REG_LI dli
+#define REG_ADDU daddu
+#define REG_SLL dsll
+#define REG_SLLV dsllv
+#define REG_SRL dsrl
+#define REG_SRLV dsrlv
+#define REG_SRA dsra
+#define REG_SRAV dsrav
+#define REG_LL lld
+#define REG_SC scd
+#define REG_SCALESHIFT 3
+#endif
+
+#if _MIPS_ISA == _MIPS_ISA_MIPS1 || _MIPS_ISA == _MIPS_ISA_MIPS2 || \
+ _MIPS_ISA == _MIPS_ISA_MIPS32
+#define MFC0 mfc0
+#define MTC0 mtc0
+#endif
+#if _MIPS_ISA == _MIPS_ISA_MIPS3 || _MIPS_ISA == _MIPS_ISA_MIPS4 || \
+ _MIPS_ISA == _MIPS_ISA_MIPS64
+#define MFC0 dmfc0
+#define MTC0 dmtc0
+#endif
+
+#if defined(__mips_o32) || defined(__mips_o64)
+
+#ifdef __ABICALLS__
+#define CPRESTORE(r) .cprestore r
+#define CPLOAD(r) .cpload r
+#else
+#define CPRESTORE(r) /* not needed */
+#define CPLOAD(r) /* not needed */
+#endif
+
+#define SETUP_GP \
+ .set push; \
+ .set noreorder; \
+ .cpload t9; \
+ .set pop
+#define SETUP_GPX(r) \
+ .set push; \
+ .set noreorder; \
+ move r,ra; /* save old ra */ \
+ bal 7f; \
+ nop; \
+ 7: .cpload ra; \
+ move ra,r; \
+ .set pop
+#define SETUP_GPX_L(r,lbl) \
+ .set push; \
+ .set noreorder; \
+ move r,ra; /* save old ra */ \
+ bal lbl; \
+ nop; \
+ lbl: .cpload ra; \
+ move ra,r; \
+ .set pop
+#define SAVE_GP(x) .cprestore x
+
+#define SETUP_GP64(a,b) /* n32/n64 specific */
+#define SETUP_GP64_R(a,b) /* n32/n64 specific */
+#define SETUP_GPX64(a,b) /* n32/n64 specific */
+#define SETUP_GPX64_L(a,b,c) /* n32/n64 specific */
+#define RESTORE_GP64 /* n32/n64 specific */
+#define USE_ALT_CP(a) /* n32/n64 specific */
+#endif /* __mips_o32 || __mips_o64 */
+
+#if defined(__mips_o32) || defined(__mips_o64)
+#define REG_PROLOGUE .set push
+#define REG_EPILOGUE .set pop
+#endif
+#if defined(__mips_n32) || defined(__mips_n64)
+#define REG_PROLOGUE .set push ; .set mips3
+#define REG_EPILOGUE .set pop
+#endif
+
+#if defined(__mips_n32) || defined(__mips_n64)
+#define SETUP_GP /* o32 specific */
+#define SETUP_GPX(r) /* o32 specific */
+#define SETUP_GPX_L(r,lbl) /* o32 specific */
+#define SAVE_GP(x) /* o32 specific */
+#define SETUP_GP64(a,b) .cpsetup $25, a, b
+#define SETUP_GPX64(a,b) \
+ .set push; \
+ move b,ra; \
+ .set noreorder; \
+ bal 7f; \
+ nop; \
+ 7: .set pop; \
+ .cpsetup ra, a, 7b; \
+ move ra,b
+#define SETUP_GPX64_L(a,b,c) \
+ .set push; \
+ move b,ra; \
+ .set noreorder; \
+ bal c; \
+ nop; \
+ c: .set pop; \
+ .cpsetup ra, a, c; \
+ move ra,b
+#define RESTORE_GP64 .cpreturn
+#define USE_ALT_CP(a) .cplocal a
+#endif /* __mips_n32 || __mips_n64 */
+
+#define GET_CPU_PCPU(reg) \
+ PTR_L reg, _C_LABEL(pcpup);
+
+/*
+ * Description of the setjmp buffer
+ *
+ * word 0 magic number (dependant on creator)
+ * 1 RA
+ * 2 S0
+ * 3 S1
+ * 4 S2
+ * 5 S3
+ * 6 S4
+ * 7 S5
+ * 8 S6
+ * 9 S7
+ * 10 SP
+ * 11 S8
+ * 12 GP (dependent on ABI)
+ * 13 signal mask (dependant on magic)
+ * 14 (con't)
+ * 15 (con't)
+ * 16 (con't)
+ *
+ * The magic number number identifies the jmp_buf and
+ * how the buffer was created as well as providing
+ * a sanity check
+ *
+ */
+
+#define _JB_MAGIC__SETJMP 0xBADFACED
+#define _JB_MAGIC_SETJMP 0xFACEDBAD
+
+/* Valid for all jmp_buf's */
+
+#define _JB_MAGIC 0
+#define _JB_REG_RA 1
+#define _JB_REG_S0 2
+#define _JB_REG_S1 3
+#define _JB_REG_S2 4
+#define _JB_REG_S3 5
+#define _JB_REG_S4 6
+#define _JB_REG_S5 7
+#define _JB_REG_S6 8
+#define _JB_REG_S7 9
+#define _JB_REG_SP 10
+#define _JB_REG_S8 11
+#if defined(__mips_n32) || defined(__mips_n64)
+#define _JB_REG_GP 12
+#endif
+
+/* Only valid with the _JB_MAGIC_SETJMP magic */
+
+#define _JB_SIGMASK 13
+#define __JB_SIGMASK_REMAINDER 14 /* sigmask_t is 128-bits */
+
+#define _JB_FPREG_F20 15
+#define _JB_FPREG_F21 16
+#define _JB_FPREG_F22 17
+#define _JB_FPREG_F23 18
+#define _JB_FPREG_F24 19
+#define _JB_FPREG_F25 20
+#define _JB_FPREG_F26 21
+#define _JB_FPREG_F27 22
+#define _JB_FPREG_F28 23
+#define _JB_FPREG_F29 24
+#define _JB_FPREG_F30 25
+#define _JB_FPREG_F31 26
+#define _JB_FPREG_FCSR 27
+
+/*
+ * Various macros for dealing with TLB hazards
+ * (a) why so many?
+ * (b) when to use?
+ * (c) why not used everywhere?
+ */
+/*
+ * Assume that w alaways need nops to escape CP0 hazard
+ * TODO: Make hazard delays configurable. Stuck with 5 cycles on the moment
+ * For more info on CP0 hazards see Chapter 7 (p.99) of "MIPS32 Architecture
+ * For Programmers Volume III: The MIPS32 Privileged Resource Architecture"
+ */
+#if defined(CPU_NLM)
+#define HAZARD_DELAY sll $0,3
+#define ITLBNOPFIX sll $0,3
+#elif defined(CPU_RMI)
+#define HAZARD_DELAY
+#define ITLBNOPFIX
+#elif defined(CPU_MIPS74KC)
+#define HAZARD_DELAY sll $0,$0,3
+#define ITLBNOPFIX sll $0,$0,3
+#else
+#define ITLBNOPFIX nop;nop;nop;nop;nop;nop;nop;nop;nop;sll $0,$0,3;
+#define HAZARD_DELAY nop;nop;nop;nop;sll $0,$0,3;
+#endif
+
+#endif /* !_MACHINE_ASM_H_ */
Property changes on: trunk/sys/mips/include/asm.h
___________________________________________________________________
Added: svn:eol-style
## -0,0 +1 ##
+native
\ No newline at end of property
Added: svn:keywords
## -0,0 +1 ##
+MidnightBSD=%H
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+text/plain
\ No newline at end of property
Added: trunk/sys/mips/include/atomic.h
===================================================================
--- trunk/sys/mips/include/atomic.h (rev 0)
+++ trunk/sys/mips/include/atomic.h 2018-05-26 21:55:02 UTC (rev 9987)
@@ -0,0 +1,645 @@
+/* $MidnightBSD$ */
+/*-
+ * Copyright (c) 1998 Doug Rabson
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ * from: src/sys/alpha/include/atomic.h,v 1.21.2.3 2005/10/06 18:12:05 jhb
+ * $FreeBSD: stable/10/sys/mips/include/atomic.h 252965 2013-07-07 16:12:22Z imp $
+ */
+
+#ifndef _MACHINE_ATOMIC_H_
+#define _MACHINE_ATOMIC_H_
+
+#ifndef _SYS_CDEFS_H_
+#error this file needs sys/cdefs.h as a prerequisite
+#endif
+
+/*
+ * Note: All the 64-bit atomic operations are only atomic when running
+ * in 64-bit mode. It is assumed that code compiled for n32 and n64
+ * fits into this definition and no further safeties are needed.
+ *
+ * It is also assumed that the add, subtract and other arithmetic is
+ * done on numbers not pointers. The special rules for n32 pointers
+ * do not have atomic operations defined for them, but generally shouldn't
+ * need atomic operations.
+ */
+#ifndef __MIPS_PLATFORM_SYNC_NOPS
+#define __MIPS_PLATFORM_SYNC_NOPS ""
+#endif
+
+static __inline void
+mips_sync(void)
+{
+ __asm __volatile (".set noreorder\n"
+ "\tsync\n"
+ __MIPS_PLATFORM_SYNC_NOPS
+ ".set reorder\n"
+ : : : "memory");
+}
+
+#define mb() mips_sync()
+#define wmb() mips_sync()
+#define rmb() mips_sync()
+
+/*
+ * Various simple arithmetic on memory which is atomic in the presence
+ * of interrupts and SMP safe.
+ */
+
+void atomic_set_8(__volatile uint8_t *, uint8_t);
+void atomic_clear_8(__volatile uint8_t *, uint8_t);
+void atomic_add_8(__volatile uint8_t *, uint8_t);
+void atomic_subtract_8(__volatile uint8_t *, uint8_t);
+
+void atomic_set_16(__volatile uint16_t *, uint16_t);
+void atomic_clear_16(__volatile uint16_t *, uint16_t);
+void atomic_add_16(__volatile uint16_t *, uint16_t);
+void atomic_subtract_16(__volatile uint16_t *, uint16_t);
+
+static __inline void
+atomic_set_32(__volatile uint32_t *p, uint32_t v)
+{
+ uint32_t temp;
+
+ __asm __volatile (
+ "1:\tll %0, %3\n\t" /* load old value */
+ "or %0, %2, %0\n\t" /* calculate new value */
+ "sc %0, %1\n\t" /* attempt to store */
+ "beqz %0, 1b\n\t" /* spin if failed */
+ : "=&r" (temp), "=m" (*p)
+ : "r" (v), "m" (*p)
+ : "memory");
+
+}
+
+static __inline void
+atomic_clear_32(__volatile uint32_t *p, uint32_t v)
+{
+ uint32_t temp;
+ v = ~v;
+
+ __asm __volatile (
+ "1:\tll %0, %3\n\t" /* load old value */
+ "and %0, %2, %0\n\t" /* calculate new value */
+ "sc %0, %1\n\t" /* attempt to store */
+ "beqz %0, 1b\n\t" /* spin if failed */
+ : "=&r" (temp), "=m" (*p)
+ : "r" (v), "m" (*p)
+ : "memory");
+}
+
+static __inline void
+atomic_add_32(__volatile uint32_t *p, uint32_t v)
+{
+ uint32_t temp;
+
+ __asm __volatile (
+ "1:\tll %0, %3\n\t" /* load old value */
+ "addu %0, %2, %0\n\t" /* calculate new value */
+ "sc %0, %1\n\t" /* attempt to store */
+ "beqz %0, 1b\n\t" /* spin if failed */
+ : "=&r" (temp), "=m" (*p)
+ : "r" (v), "m" (*p)
+ : "memory");
+}
+
+static __inline void
+atomic_subtract_32(__volatile uint32_t *p, uint32_t v)
+{
+ uint32_t temp;
+
+ __asm __volatile (
+ "1:\tll %0, %3\n\t" /* load old value */
+ "subu %0, %2\n\t" /* calculate new value */
+ "sc %0, %1\n\t" /* attempt to store */
+ "beqz %0, 1b\n\t" /* spin if failed */
+ : "=&r" (temp), "=m" (*p)
+ : "r" (v), "m" (*p)
+ : "memory");
+}
+
+static __inline uint32_t
+atomic_readandclear_32(__volatile uint32_t *addr)
+{
+ uint32_t result,temp;
+
+ __asm __volatile (
+ "1:\tll %0,%3\n\t" /* load current value, asserting lock */
+ "li %1,0\n\t" /* value to store */
+ "sc %1,%2\n\t" /* attempt to store */
+ "beqz %1, 1b\n\t" /* if the store failed, spin */
+ : "=&r"(result), "=&r"(temp), "=m" (*addr)
+ : "m" (*addr)
+ : "memory");
+
+ return result;
+}
+
+static __inline uint32_t
+atomic_readandset_32(__volatile uint32_t *addr, uint32_t value)
+{
+ uint32_t result,temp;
+
+ __asm __volatile (
+ "1:\tll %0,%3\n\t" /* load current value, asserting lock */
+ "or %1,$0,%4\n\t"
+ "sc %1,%2\n\t" /* attempt to store */
+ "beqz %1, 1b\n\t" /* if the store failed, spin */
+ : "=&r"(result), "=&r"(temp), "=m" (*addr)
+ : "m" (*addr), "r" (value)
+ : "memory");
+
+ return result;
+}
+
+#if defined(__mips_n64) || defined(__mips_n32)
+static __inline void
+atomic_set_64(__volatile uint64_t *p, uint64_t v)
+{
+ uint64_t temp;
+
+ __asm __volatile (
+ "1:\n\t"
+ "lld %0, %3\n\t" /* load old value */
+ "or %0, %2, %0\n\t" /* calculate new value */
+ "scd %0, %1\n\t" /* attempt to store */
+ "beqz %0, 1b\n\t" /* spin if failed */
+ : "=&r" (temp), "=m" (*p)
+ : "r" (v), "m" (*p)
+ : "memory");
+
+}
+
+static __inline void
+atomic_clear_64(__volatile uint64_t *p, uint64_t v)
+{
+ uint64_t temp;
+ v = ~v;
+
+ __asm __volatile (
+ "1:\n\t"
+ "lld %0, %3\n\t" /* load old value */
+ "and %0, %2, %0\n\t" /* calculate new value */
+ "scd %0, %1\n\t" /* attempt to store */
+ "beqz %0, 1b\n\t" /* spin if failed */
+ : "=&r" (temp), "=m" (*p)
+ : "r" (v), "m" (*p)
+ : "memory");
+}
+
+static __inline void
+atomic_add_64(__volatile uint64_t *p, uint64_t v)
+{
+ uint64_t temp;
+
+ __asm __volatile (
+ "1:\n\t"
+ "lld %0, %3\n\t" /* load old value */
+ "daddu %0, %2, %0\n\t" /* calculate new value */
+ "scd %0, %1\n\t" /* attempt to store */
+ "beqz %0, 1b\n\t" /* spin if failed */
+ : "=&r" (temp), "=m" (*p)
+ : "r" (v), "m" (*p)
+ : "memory");
+}
+
+static __inline void
+atomic_subtract_64(__volatile uint64_t *p, uint64_t v)
+{
+ uint64_t temp;
+
+ __asm __volatile (
+ "1:\n\t"
+ "lld %0, %3\n\t" /* load old value */
+ "dsubu %0, %2\n\t" /* calculate new value */
+ "scd %0, %1\n\t" /* attempt to store */
+ "beqz %0, 1b\n\t" /* spin if failed */
+ : "=&r" (temp), "=m" (*p)
+ : "r" (v), "m" (*p)
+ : "memory");
+}
+
+static __inline uint64_t
+atomic_readandclear_64(__volatile uint64_t *addr)
+{
+ uint64_t result,temp;
+
+ __asm __volatile (
+ "1:\n\t"
+ "lld %0, %3\n\t" /* load old value */
+ "li %1, 0\n\t" /* value to store */
+ "scd %1, %2\n\t" /* attempt to store */
+ "beqz %1, 1b\n\t" /* if the store failed, spin */
+ : "=&r"(result), "=&r"(temp), "=m" (*addr)
+ : "m" (*addr)
+ : "memory");
+
+ return result;
+}
+
+static __inline uint64_t
+atomic_readandset_64(__volatile uint64_t *addr, uint64_t value)
+{
+ uint64_t result,temp;
+
+ __asm __volatile (
+ "1:\n\t"
+ "lld %0,%3\n\t" /* Load old value*/
+ "or %1,$0,%4\n\t"
+ "scd %1,%2\n\t" /* attempt to store */
+ "beqz %1, 1b\n\t" /* if the store failed, spin */
+ : "=&r"(result), "=&r"(temp), "=m" (*addr)
+ : "m" (*addr), "r" (value)
+ : "memory");
+
+ return result;
+}
+#endif
+
+#define ATOMIC_ACQ_REL(NAME, WIDTH) \
+static __inline void \
+atomic_##NAME##_acq_##WIDTH(__volatile uint##WIDTH##_t *p, uint##WIDTH##_t v)\
+{ \
+ atomic_##NAME##_##WIDTH(p, v); \
+ mips_sync(); \
+} \
+ \
+static __inline void \
+atomic_##NAME##_rel_##WIDTH(__volatile uint##WIDTH##_t *p, uint##WIDTH##_t v)\
+{ \
+ mips_sync(); \
+ atomic_##NAME##_##WIDTH(p, v); \
+}
+
+/* Variants of simple arithmetic with memory barriers. */
+ATOMIC_ACQ_REL(set, 8)
+ATOMIC_ACQ_REL(clear, 8)
+ATOMIC_ACQ_REL(add, 8)
+ATOMIC_ACQ_REL(subtract, 8)
+ATOMIC_ACQ_REL(set, 16)
+ATOMIC_ACQ_REL(clear, 16)
+ATOMIC_ACQ_REL(add, 16)
+ATOMIC_ACQ_REL(subtract, 16)
+ATOMIC_ACQ_REL(set, 32)
+ATOMIC_ACQ_REL(clear, 32)
+ATOMIC_ACQ_REL(add, 32)
+ATOMIC_ACQ_REL(subtract, 32)
+#if defined(__mips_n64) || defined(__mips_n32)
+ATOMIC_ACQ_REL(set, 64)
+ATOMIC_ACQ_REL(clear, 64)
+ATOMIC_ACQ_REL(add, 64)
+ATOMIC_ACQ_REL(subtract, 64)
+#endif
+
+#undef ATOMIC_ACQ_REL
+
+/*
+ * We assume that a = b will do atomic loads and stores.
+ */
+#define ATOMIC_STORE_LOAD(WIDTH) \
+static __inline uint##WIDTH##_t \
+atomic_load_acq_##WIDTH(__volatile uint##WIDTH##_t *p) \
+{ \
+ uint##WIDTH##_t v; \
+ \
+ v = *p; \
+ mips_sync(); \
+ return (v); \
+} \
+ \
+static __inline void \
+atomic_store_rel_##WIDTH(__volatile uint##WIDTH##_t *p, uint##WIDTH##_t v)\
+{ \
+ mips_sync(); \
+ *p = v; \
+}
+
+ATOMIC_STORE_LOAD(32)
+ATOMIC_STORE_LOAD(64)
+#if !defined(__mips_n64) && !defined(__mips_n32)
+void atomic_store_64(__volatile uint64_t *, uint64_t *);
+void atomic_load_64(__volatile uint64_t *, uint64_t *);
+#else
+static __inline void
+atomic_store_64(__volatile uint64_t *p, uint64_t *v)
+{
+ *p = *v;
+}
+
+static __inline void
+atomic_load_64(__volatile uint64_t *p, uint64_t *v)
+{
+ *v = *p;
+}
+#endif
+
+#undef ATOMIC_STORE_LOAD
+
+/*
+ * Atomically compare the value stored at *p with cmpval and if the
+ * two values are equal, update the value of *p with newval. Returns
+ * zero if the compare failed, nonzero otherwise.
+ */
+static __inline uint32_t
+atomic_cmpset_32(__volatile uint32_t* p, uint32_t cmpval, uint32_t newval)
+{
+ uint32_t ret;
+
+ __asm __volatile (
+ "1:\tll %0, %4\n\t" /* load old value */
+ "bne %0, %2, 2f\n\t" /* compare */
+ "move %0, %3\n\t" /* value to store */
+ "sc %0, %1\n\t" /* attempt to store */
+ "beqz %0, 1b\n\t" /* if it failed, spin */
+ "j 3f\n\t"
+ "2:\n\t"
+ "li %0, 0\n\t"
+ "3:\n"
+ : "=&r" (ret), "=m" (*p)
+ : "r" (cmpval), "r" (newval), "m" (*p)
+ : "memory");
+
+ return ret;
+}
+
+/*
+ * Atomically compare the value stored at *p with cmpval and if the
+ * two values are equal, update the value of *p with newval. Returns
+ * zero if the compare failed, nonzero otherwise.
+ */
+static __inline uint32_t
+atomic_cmpset_acq_32(__volatile uint32_t *p, uint32_t cmpval, uint32_t newval)
+{
+ int retval;
+
+ retval = atomic_cmpset_32(p, cmpval, newval);
+ mips_sync();
+ return (retval);
+}
+
+static __inline uint32_t
+atomic_cmpset_rel_32(__volatile uint32_t *p, uint32_t cmpval, uint32_t newval)
+{
+ mips_sync();
+ return (atomic_cmpset_32(p, cmpval, newval));
+}
+
+/*
+ * Atomically add the value of v to the integer pointed to by p and return
+ * the previous value of *p.
+ */
+static __inline uint32_t
+atomic_fetchadd_32(__volatile uint32_t *p, uint32_t v)
+{
+ uint32_t value, temp;
+
+ __asm __volatile (
+ "1:\tll %0, %1\n\t" /* load old value */
+ "addu %2, %3, %0\n\t" /* calculate new value */
+ "sc %2, %1\n\t" /* attempt to store */
+ "beqz %2, 1b\n\t" /* spin if failed */
+ : "=&r" (value), "=m" (*p), "=&r" (temp)
+ : "r" (v), "m" (*p));
+ return (value);
+}
+
+#if defined(__mips_n64) || defined(__mips_n32)
+/*
+ * Atomically compare the value stored at *p with cmpval and if the
+ * two values are equal, update the value of *p with newval. Returns
+ * zero if the compare failed, nonzero otherwise.
+ */
+static __inline uint64_t
+atomic_cmpset_64(__volatile uint64_t* p, uint64_t cmpval, uint64_t newval)
+{
+ uint64_t ret;
+
+ __asm __volatile (
+ "1:\n\t"
+ "lld %0, %4\n\t" /* load old value */
+ "bne %0, %2, 2f\n\t" /* compare */
+ "move %0, %3\n\t" /* value to store */
+ "scd %0, %1\n\t" /* attempt to store */
+ "beqz %0, 1b\n\t" /* if it failed, spin */
+ "j 3f\n\t"
+ "2:\n\t"
+ "li %0, 0\n\t"
+ "3:\n"
+ : "=&r" (ret), "=m" (*p)
+ : "r" (cmpval), "r" (newval), "m" (*p)
+ : "memory");
+
+ return ret;
+}
+
+/*
+ * Atomically compare the value stored at *p with cmpval and if the
+ * two values are equal, update the value of *p with newval. Returns
+ * zero if the compare failed, nonzero otherwise.
+ */
+static __inline uint64_t
+atomic_cmpset_acq_64(__volatile uint64_t *p, uint64_t cmpval, uint64_t newval)
+{
+ int retval;
+
+ retval = atomic_cmpset_64(p, cmpval, newval);
+ mips_sync();
+ return (retval);
+}
+
+static __inline uint64_t
+atomic_cmpset_rel_64(__volatile uint64_t *p, uint64_t cmpval, uint64_t newval)
+{
+ mips_sync();
+ return (atomic_cmpset_64(p, cmpval, newval));
+}
+
+/*
+ * Atomically add the value of v to the integer pointed to by p and return
+ * the previous value of *p.
+ */
+static __inline uint64_t
+atomic_fetchadd_64(__volatile uint64_t *p, uint64_t v)
+{
+ uint64_t value, temp;
+
+ __asm __volatile (
+ "1:\n\t"
+ "lld %0, %1\n\t" /* load old value */
+ "daddu %2, %3, %0\n\t" /* calculate new value */
+ "scd %2, %1\n\t" /* attempt to store */
+ "beqz %2, 1b\n\t" /* spin if failed */
+ : "=&r" (value), "=m" (*p), "=&r" (temp)
+ : "r" (v), "m" (*p));
+ return (value);
+}
+#endif
+
+/* Operations on chars. */
+#define atomic_set_char atomic_set_8
+#define atomic_set_acq_char atomic_set_acq_8
+#define atomic_set_rel_char atomic_set_rel_8
+#define atomic_clear_char atomic_clear_8
+#define atomic_clear_acq_char atomic_clear_acq_8
+#define atomic_clear_rel_char atomic_clear_rel_8
+#define atomic_add_char atomic_add_8
+#define atomic_add_acq_char atomic_add_acq_8
+#define atomic_add_rel_char atomic_add_rel_8
+#define atomic_subtract_char atomic_subtract_8
+#define atomic_subtract_acq_char atomic_subtract_acq_8
+#define atomic_subtract_rel_char atomic_subtract_rel_8
+
+/* Operations on shorts. */
+#define atomic_set_short atomic_set_16
+#define atomic_set_acq_short atomic_set_acq_16
+#define atomic_set_rel_short atomic_set_rel_16
+#define atomic_clear_short atomic_clear_16
+#define atomic_clear_acq_short atomic_clear_acq_16
+#define atomic_clear_rel_short atomic_clear_rel_16
+#define atomic_add_short atomic_add_16
+#define atomic_add_acq_short atomic_add_acq_16
+#define atomic_add_rel_short atomic_add_rel_16
+#define atomic_subtract_short atomic_subtract_16
+#define atomic_subtract_acq_short atomic_subtract_acq_16
+#define atomic_subtract_rel_short atomic_subtract_rel_16
+
+/* Operations on ints. */
+#define atomic_set_int atomic_set_32
+#define atomic_set_acq_int atomic_set_acq_32
+#define atomic_set_rel_int atomic_set_rel_32
+#define atomic_clear_int atomic_clear_32
+#define atomic_clear_acq_int atomic_clear_acq_32
+#define atomic_clear_rel_int atomic_clear_rel_32
+#define atomic_add_int atomic_add_32
+#define atomic_add_acq_int atomic_add_acq_32
+#define atomic_add_rel_int atomic_add_rel_32
+#define atomic_subtract_int atomic_subtract_32
+#define atomic_subtract_acq_int atomic_subtract_acq_32
+#define atomic_subtract_rel_int atomic_subtract_rel_32
+#define atomic_cmpset_int atomic_cmpset_32
+#define atomic_cmpset_acq_int atomic_cmpset_acq_32
+#define atomic_cmpset_rel_int atomic_cmpset_rel_32
+#define atomic_load_acq_int atomic_load_acq_32
+#define atomic_store_rel_int atomic_store_rel_32
+#define atomic_readandclear_int atomic_readandclear_32
+#define atomic_readandset_int atomic_readandset_32
+#define atomic_fetchadd_int atomic_fetchadd_32
+
+/*
+ * I think the following is right, even for n32. For n32 the pointers
+ * are still 32-bits, so we need to operate on them as 32-bit quantities,
+ * even though they are sign extended in operation. For longs, there's
+ * no question because they are always 32-bits.
+ */
+#ifdef __mips_n64
+/* Operations on longs. */
+#define atomic_set_long atomic_set_64
+#define atomic_set_acq_long atomic_set_acq_64
+#define atomic_set_rel_long atomic_set_rel_64
+#define atomic_clear_long atomic_clear_64
+#define atomic_clear_acq_long atomic_clear_acq_64
+#define atomic_clear_rel_long atomic_clear_rel_64
+#define atomic_add_long atomic_add_64
+#define atomic_add_acq_long atomic_add_acq_64
+#define atomic_add_rel_long atomic_add_rel_64
+#define atomic_subtract_long atomic_subtract_64
+#define atomic_subtract_acq_long atomic_subtract_acq_64
+#define atomic_subtract_rel_long atomic_subtract_rel_64
+#define atomic_cmpset_long atomic_cmpset_64
+#define atomic_cmpset_acq_long atomic_cmpset_acq_64
+#define atomic_cmpset_rel_long atomic_cmpset_rel_64
+#define atomic_load_acq_long atomic_load_acq_64
+#define atomic_store_rel_long atomic_store_rel_64
+#define atomic_fetchadd_long atomic_fetchadd_64
+#define atomic_readandclear_long atomic_readandclear_64
+
+#else /* !__mips_n64 */
+
+/* Operations on longs. */
+#define atomic_set_long(p, v) \
+ atomic_set_32((volatile u_int *)(p), (u_int)(v))
+#define atomic_set_acq_long(p, v) \
+ atomic_set_acq_32((volatile u_int *)(p), (u_int)(v))
+#define atomic_set_rel_long(p, v) \
+ atomic_set_rel_32((volatile u_int *)(p), (u_int)(v))
+#define atomic_clear_long(p, v) \
+ atomic_clear_32((volatile u_int *)(p), (u_int)(v))
+#define atomic_clear_acq_long(p, v) \
+ atomic_clear_acq_32((volatile u_int *)(p), (u_int)(v))
+#define atomic_clear_rel_long(p, v) \
+ atomic_clear_rel_32((volatile u_int *)(p), (u_int)(v))
+#define atomic_add_long(p, v) \
+ atomic_add_32((volatile u_int *)(p), (u_int)(v))
+#define atomic_add_acq_long(p, v) \
+ atomic_add_32((volatile u_int *)(p), (u_int)(v))
+#define atomic_add_rel_long(p, v) \
+ atomic_add_32((volatile u_int *)(p), (u_int)(v))
+#define atomic_subtract_long(p, v) \
+ atomic_subtract_32((volatile u_int *)(p), (u_int)(v))
+#define atomic_subtract_acq_long(p, v) \
+ atomic_subtract_acq_32((volatile u_int *)(p), (u_int)(v))
+#define atomic_subtract_rel_long(p, v) \
+ atomic_subtract_rel_32((volatile u_int *)(p), (u_int)(v))
+#define atomic_cmpset_long(p, cmpval, newval) \
+ atomic_cmpset_32((volatile u_int *)(p), (u_int)(cmpval), \
+ (u_int)(newval))
+#define atomic_cmpset_acq_long(p, cmpval, newval) \
+ atomic_cmpset_acq_32((volatile u_int *)(p), (u_int)(cmpval), \
+ (u_int)(newval))
+#define atomic_cmpset_rel_long(p, cmpval, newval) \
+ atomic_cmpset_rel_32((volatile u_int *)(p), (u_int)(cmpval), \
+ (u_int)(newval))
+#define atomic_load_acq_long(p) \
+ (u_long)atomic_load_acq_32((volatile u_int *)(p))
+#define atomic_store_rel_long(p, v) \
+ atomic_store_rel_32((volatile u_int *)(p), (u_int)(v))
+#define atomic_fetchadd_long(p, v) \
+ atomic_fetchadd_32((volatile u_int *)(p), (u_int)(v))
+#define atomic_readandclear_long(p) \
+ atomic_readandclear_32((volatile u_int *)(p))
+
+#endif /* __mips_n64 */
+
+/* Operations on pointers. */
+#define atomic_set_ptr atomic_set_long
+#define atomic_set_acq_ptr atomic_set_acq_long
+#define atomic_set_rel_ptr atomic_set_rel_long
+#define atomic_clear_ptr atomic_clear_long
+#define atomic_clear_acq_ptr atomic_clear_acq_long
+#define atomic_clear_rel_ptr atomic_clear_rel_long
+#define atomic_add_ptr atomic_add_long
+#define atomic_add_acq_ptr atomic_add_acq_long
+#define atomic_add_rel_ptr atomic_add_rel_long
+#define atomic_subtract_ptr atomic_subtract_long
+#define atomic_subtract_acq_ptr atomic_subtract_acq_long
+#define atomic_subtract_rel_ptr atomic_subtract_rel_long
+#define atomic_cmpset_ptr atomic_cmpset_long
+#define atomic_cmpset_acq_ptr atomic_cmpset_acq_long
+#define atomic_cmpset_rel_ptr atomic_cmpset_rel_long
+#define atomic_load_acq_ptr atomic_load_acq_long
+#define atomic_store_rel_ptr atomic_store_rel_long
+#define atomic_readandclear_ptr atomic_readandclear_long
+
+#endif /* ! _MACHINE_ATOMIC_H_ */
Property changes on: trunk/sys/mips/include/atomic.h
___________________________________________________________________
Added: svn:eol-style
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+native
\ No newline at end of property
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## -0,0 +1 ##
+MidnightBSD=%H
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Added: trunk/sys/mips/include/bootinfo.h
===================================================================
--- trunk/sys/mips/include/bootinfo.h (rev 0)
+++ trunk/sys/mips/include/bootinfo.h 2018-05-26 21:55:02 UTC (rev 9987)
@@ -0,0 +1,143 @@
+/* $MidnightBSD$ */
+/*-
+ * Copyright (C) 1994 by Rodney W. Grimes, Milwaukie, Oregon 97222
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer as
+ * the first lines of this file unmodified.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * 3. All advertising materials mentioning features or use of this software
+ * must display the following acknowledgement:
+ * This product includes software developed by Rodney W. Grimes.
+ * 4. The name of the author may not be used to endorse or promote products
+ * derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY RODNEY W. GRIMES ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL RODNEY W. GRIMES BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ * $FreeBSD: stable/10/sys/mips/include/bootinfo.h 202175 2010-01-12 21:36:08Z imp $
+ */
+
+#ifndef _MACHINE_BOOTINFO_H_
+#define _MACHINE_BOOTINFO_H_
+
+/* Only change the version number if you break compatibility. */
+#define BOOTINFO_VERSION 1
+
+#define N_BIOS_GEOM 8
+
+#define MIPS_BOOTINFO_MAGIC 0xCDEACDEA
+
+/* Extended OLV bootinfo struct. The data area includes a list of named
+ OIDs and associated data values. The format is:
+
+ NUL-terminated dotted-string name
+ 2 byte length, in big-endian order
+ LENGTH bytes of data
+ [...]
+
+ The two magic fields are used to guard against other bootloaders that
+ may place other sorts of data here. */
+
+struct bootinfo_ext {
+#define BOOTINFO_EXT_MAGIC1 0x55aa00ff
+ unsigned int magic1;
+ unsigned char *data;
+ unsigned int size;
+#define BOOTINFO_EXT_MAGIC2 0x32719187
+ unsigned int magic2;
+};
+
+#define BOOTINFO_EXT_MAX_SIZE 16384
+
+/*
+ * A zero bootinfo field often means that there is no info available.
+ * Flags are used to indicate the validity of fields where zero is a
+ * normal value.
+ */
+struct bootinfo {
+ u_int32_t bi_version;
+ u_int32_t bi_kernelname; /* represents a char * */
+ u_int32_t bi_nfs_diskless; /* struct nfs_diskless * */
+ /* End of fields that are always present. */
+#define bi_endcommon bi_n_bios_used
+ u_int32_t bi_n_bios_used;
+ u_int32_t bi_bios_geom[N_BIOS_GEOM];
+ u_int32_t bi_size;
+ u_int8_t bi_memsizes_valid;
+ u_int8_t bi_bios_dev; /* bootdev BIOS unit number */
+ u_int8_t bi_pad[2];
+ u_int32_t bi_basemem;
+ u_int32_t bi_extmem;
+ u_int32_t bi_symtab; /* struct symtab * */
+ u_int32_t bi_esymtab; /* struct symtab * */
+ /* Items below only from advanced bootloader */
+ u_int32_t bi_kernend; /* end of kernel space */
+ u_int32_t bi_envp; /* environment */
+ u_int32_t bi_modulep; /* preloaded modules */
+};
+
+#ifdef _KERNEL
+extern struct bootinfo bootinfo;
+#endif
+
+/*
+ * Constants for converting boot-style device number to type,
+ * adaptor (uba, mba, etc), unit number and partition number.
+ * Type (== major device number) is in the low byte
+ * for backward compatibility. Except for that of the "magic
+ * number", each mask applies to the shifted value.
+ * Format:
+ * (4) (4) (4) (4) (8) (8)
+ * --------------------------------
+ * |MA | AD| CT| UN| PART | TYPE |
+ * --------------------------------
+ */
+#define B_ADAPTORSHIFT 24
+#define B_ADAPTORMASK 0x0f
+#define B_ADAPTOR(val) (((val) >> B_ADAPTORSHIFT) & B_ADAPTORMASK)
+#define B_CONTROLLERSHIFT 20
+#define B_CONTROLLERMASK 0xf
+#define B_CONTROLLER(val) (((val)>>B_CONTROLLERSHIFT) & B_CONTROLLERMASK)
+#define B_SLICESHIFT 20
+#define B_SLICEMASK 0xff
+#define B_SLICE(val) (((val)>>B_SLICESHIFT) & B_SLICEMASK)
+#define B_UNITSHIFT 16
+#define B_UNITMASK 0xf
+#define B_UNIT(val) (((val) >> B_UNITSHIFT) & B_UNITMASK)
+#define B_PARTITIONSHIFT 8
+#define B_PARTITIONMASK 0xff
+#define B_PARTITION(val) (((val) >> B_PARTITIONSHIFT) & B_PARTITIONMASK)
+#define B_TYPESHIFT 0
+#define B_TYPEMASK 0xff
+#define B_TYPE(val) (((val) >> B_TYPESHIFT) & B_TYPEMASK)
+
+#define B_MAGICMASK 0xf0000000
+#define B_DEVMAGIC 0xa0000000
+
+#define MAKEBOOTDEV(type, adaptor, controller, unit, partition) \
+ (((type) << B_TYPESHIFT) | ((adaptor) << B_ADAPTORSHIFT) | \
+ ((controller) << B_CONTROLLERSHIFT) | ((unit) << B_UNITSHIFT) | \
+ ((partition) << B_PARTITIONSHIFT) | B_DEVMAGIC)
+
+#define BASE_SLICE 2
+#define COMPATIBILITY_SLICE 0
+#define MAX_SLICES 32
+#define WHOLE_DISK_SLICE 1
+
+#endif /* !_MACHINE_BOOTINFO_H_ */
Property changes on: trunk/sys/mips/include/bootinfo.h
___________________________________________________________________
Added: svn:eol-style
## -0,0 +1 ##
+native
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Added: svn:keywords
## -0,0 +1 ##
+MidnightBSD=%H
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+text/plain
\ No newline at end of property
Added: trunk/sys/mips/include/bus.h
===================================================================
--- trunk/sys/mips/include/bus.h (rev 0)
+++ trunk/sys/mips/include/bus.h 2018-05-26 21:55:02 UTC (rev 9987)
@@ -0,0 +1,736 @@
+/* $MidnightBSD$ */
+/* $NetBSD: bus.h,v 1.11 2003/07/28 17:35:54 thorpej Exp $ */
+
+/*-
+ * Copyright (c) 1996, 1997, 1998, 2001 The NetBSD Foundation, Inc.
+ * All rights reserved.
+ *
+ * This code is derived from software contributed to The NetBSD Foundation
+ * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility,
+ * NASA Ames Research Center.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
+ * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/*-
+ * Copyright (c) 1996 Charles M. Hannum. All rights reserved.
+ * Copyright (c) 1996 Christopher G. Demetriou. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * 3. All advertising materials mentioning features or use of this software
+ * must display the following acknowledgement:
+ * This product includes software developed by Christopher G. Demetriou
+ * for the NetBSD Project.
+ * 4. The name of the author may not be used to endorse or promote products
+ * derived from this software without specific prior written permission
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+ * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+ * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * $FreeBSD: stable/10/sys/mips/include/bus.h 263687 2014-03-24 13:48:04Z emaste $
+ */
+
+#ifndef _MACHINE_BUS_H_
+#define _MACHINE_BUS_H_
+
+#include <machine/_bus.h>
+
+struct bus_space {
+ /* cookie */
+ void *bs_cookie;
+
+ /* mapping/unmapping */
+ int (*bs_map) (void *, bus_addr_t, bus_size_t,
+ int, bus_space_handle_t *);
+ void (*bs_unmap) (void *, bus_space_handle_t, bus_size_t);
+ int (*bs_subregion) (void *, bus_space_handle_t,
+ bus_size_t, bus_size_t, bus_space_handle_t *);
+
+ /* allocation/deallocation */
+ int (*bs_alloc) (void *, bus_addr_t, bus_addr_t,
+ bus_size_t, bus_size_t, bus_size_t, int,
+ bus_addr_t *, bus_space_handle_t *);
+ void (*bs_free) (void *, bus_space_handle_t,
+ bus_size_t);
+
+ /* get kernel virtual address */
+ /* barrier */
+ void (*bs_barrier) (void *, bus_space_handle_t,
+ bus_size_t, bus_size_t, int);
+
+ /* read (single) */
+ u_int8_t (*bs_r_1) (void *, bus_space_handle_t, bus_size_t);
+ u_int16_t (*bs_r_2) (void *, bus_space_handle_t, bus_size_t);
+ u_int32_t (*bs_r_4) (void *, bus_space_handle_t, bus_size_t);
+ u_int64_t (*bs_r_8) (void *, bus_space_handle_t, bus_size_t);
+
+ /* read multiple */
+ void (*bs_rm_1) (void *, bus_space_handle_t, bus_size_t,
+ u_int8_t *, bus_size_t);
+ void (*bs_rm_2) (void *, bus_space_handle_t, bus_size_t,
+ u_int16_t *, bus_size_t);
+ void (*bs_rm_4) (void *, bus_space_handle_t,
+ bus_size_t, u_int32_t *, bus_size_t);
+ void (*bs_rm_8) (void *, bus_space_handle_t,
+ bus_size_t, u_int64_t *, bus_size_t);
+
+ /* read region */
+ void (*bs_rr_1) (void *, bus_space_handle_t,
+ bus_size_t, u_int8_t *, bus_size_t);
+ void (*bs_rr_2) (void *, bus_space_handle_t,
+ bus_size_t, u_int16_t *, bus_size_t);
+ void (*bs_rr_4) (void *, bus_space_handle_t,
+ bus_size_t, u_int32_t *, bus_size_t);
+ void (*bs_rr_8) (void *, bus_space_handle_t,
+ bus_size_t, u_int64_t *, bus_size_t);
+
+ /* write (single) */
+ void (*bs_w_1) (void *, bus_space_handle_t,
+ bus_size_t, u_int8_t);
+ void (*bs_w_2) (void *, bus_space_handle_t,
+ bus_size_t, u_int16_t);
+ void (*bs_w_4) (void *, bus_space_handle_t,
+ bus_size_t, u_int32_t);
+ void (*bs_w_8) (void *, bus_space_handle_t,
+ bus_size_t, u_int64_t);
+
+ /* write multiple */
+ void (*bs_wm_1) (void *, bus_space_handle_t,
+ bus_size_t, const u_int8_t *, bus_size_t);
+ void (*bs_wm_2) (void *, bus_space_handle_t,
+ bus_size_t, const u_int16_t *, bus_size_t);
+ void (*bs_wm_4) (void *, bus_space_handle_t,
+ bus_size_t, const u_int32_t *, bus_size_t);
+ void (*bs_wm_8) (void *, bus_space_handle_t,
+ bus_size_t, const u_int64_t *, bus_size_t);
+
+ /* write region */
+ void (*bs_wr_1) (void *, bus_space_handle_t,
+ bus_size_t, const u_int8_t *, bus_size_t);
+ void (*bs_wr_2) (void *, bus_space_handle_t,
+ bus_size_t, const u_int16_t *, bus_size_t);
+ void (*bs_wr_4) (void *, bus_space_handle_t,
+ bus_size_t, const u_int32_t *, bus_size_t);
+ void (*bs_wr_8) (void *, bus_space_handle_t,
+ bus_size_t, const u_int64_t *, bus_size_t);
+
+ /* set multiple */
+ void (*bs_sm_1) (void *, bus_space_handle_t,
+ bus_size_t, u_int8_t, bus_size_t);
+ void (*bs_sm_2) (void *, bus_space_handle_t,
+ bus_size_t, u_int16_t, bus_size_t);
+ void (*bs_sm_4) (void *, bus_space_handle_t,
+ bus_size_t, u_int32_t, bus_size_t);
+ void (*bs_sm_8) (void *, bus_space_handle_t,
+ bus_size_t, u_int64_t, bus_size_t);
+
+ /* set region */
+ void (*bs_sr_1) (void *, bus_space_handle_t,
+ bus_size_t, u_int8_t, bus_size_t);
+ void (*bs_sr_2) (void *, bus_space_handle_t,
+ bus_size_t, u_int16_t, bus_size_t);
+ void (*bs_sr_4) (void *, bus_space_handle_t,
+ bus_size_t, u_int32_t, bus_size_t);
+ void (*bs_sr_8) (void *, bus_space_handle_t,
+ bus_size_t, u_int64_t, bus_size_t);
+
+ /* copy */
+ void (*bs_c_1) (void *, bus_space_handle_t, bus_size_t,
+ bus_space_handle_t, bus_size_t, bus_size_t);
+ void (*bs_c_2) (void *, bus_space_handle_t, bus_size_t,
+ bus_space_handle_t, bus_size_t, bus_size_t);
+ void (*bs_c_4) (void *, bus_space_handle_t, bus_size_t,
+ bus_space_handle_t, bus_size_t, bus_size_t);
+ void (*bs_c_8) (void *, bus_space_handle_t, bus_size_t,
+ bus_space_handle_t, bus_size_t, bus_size_t);
+
+ /* read stream (single) */
+ u_int8_t (*bs_r_1_s) (void *, bus_space_handle_t, bus_size_t);
+ u_int16_t (*bs_r_2_s) (void *, bus_space_handle_t, bus_size_t);
+ u_int32_t (*bs_r_4_s) (void *, bus_space_handle_t, bus_size_t);
+ u_int64_t (*bs_r_8_s) (void *, bus_space_handle_t, bus_size_t);
+
+ /* read multiple stream */
+ void (*bs_rm_1_s) (void *, bus_space_handle_t, bus_size_t,
+ u_int8_t *, bus_size_t);
+ void (*bs_rm_2_s) (void *, bus_space_handle_t, bus_size_t,
+ u_int16_t *, bus_size_t);
+ void (*bs_rm_4_s) (void *, bus_space_handle_t,
+ bus_size_t, u_int32_t *, bus_size_t);
+ void (*bs_rm_8_s) (void *, bus_space_handle_t,
+ bus_size_t, u_int64_t *, bus_size_t);
+
+ /* read region stream */
+ void (*bs_rr_1_s) (void *, bus_space_handle_t,
+ bus_size_t, u_int8_t *, bus_size_t);
+ void (*bs_rr_2_s) (void *, bus_space_handle_t,
+ bus_size_t, u_int16_t *, bus_size_t);
+ void (*bs_rr_4_s) (void *, bus_space_handle_t,
+ bus_size_t, u_int32_t *, bus_size_t);
+ void (*bs_rr_8_s) (void *, bus_space_handle_t,
+ bus_size_t, u_int64_t *, bus_size_t);
+
+ /* write stream (single) */
+ void (*bs_w_1_s) (void *, bus_space_handle_t,
+ bus_size_t, u_int8_t);
+ void (*bs_w_2_s) (void *, bus_space_handle_t,
+ bus_size_t, u_int16_t);
+ void (*bs_w_4_s) (void *, bus_space_handle_t,
+ bus_size_t, u_int32_t);
+ void (*bs_w_8_s) (void *, bus_space_handle_t,
+ bus_size_t, u_int64_t);
+
+ /* write multiple stream */
+ void (*bs_wm_1_s) (void *, bus_space_handle_t,
+ bus_size_t, const u_int8_t *, bus_size_t);
+ void (*bs_wm_2_s) (void *, bus_space_handle_t,
+ bus_size_t, const u_int16_t *, bus_size_t);
+ void (*bs_wm_4_s) (void *, bus_space_handle_t,
+ bus_size_t, const u_int32_t *, bus_size_t);
+ void (*bs_wm_8_s) (void *, bus_space_handle_t,
+ bus_size_t, const u_int64_t *, bus_size_t);
+
+ /* write region stream */
+ void (*bs_wr_1_s) (void *, bus_space_handle_t,
+ bus_size_t, const u_int8_t *, bus_size_t);
+ void (*bs_wr_2_s) (void *, bus_space_handle_t,
+ bus_size_t, const u_int16_t *, bus_size_t);
+ void (*bs_wr_4_s) (void *, bus_space_handle_t,
+ bus_size_t, const u_int32_t *, bus_size_t);
+ void (*bs_wr_8_s) (void *, bus_space_handle_t,
+ bus_size_t, const u_int64_t *, bus_size_t);
+};
+
+
+/*
+ * Utility macros; INTERNAL USE ONLY.
+ */
+#define __bs_c(a,b) __CONCAT(a,b)
+#define __bs_opname(op,size) __bs_c(__bs_c(__bs_c(bs_,op),_),size)
+
+#define __bs_rs(sz, t, h, o) \
+ (*(t)->__bs_opname(r,sz))((t)->bs_cookie, h, o)
+#define __bs_ws(sz, t, h, o, v) \
+ (*(t)->__bs_opname(w,sz))((t)->bs_cookie, h, o, v)
+#define __bs_nonsingle(type, sz, t, h, o, a, c) \
+ (*(t)->__bs_opname(type,sz))((t)->bs_cookie, h, o, a, c)
+#define __bs_set(type, sz, t, h, o, v, c) \
+ (*(t)->__bs_opname(type,sz))((t)->bs_cookie, h, o, v, c)
+#define __bs_copy(sz, t, h1, o1, h2, o2, cnt) \
+ (*(t)->__bs_opname(c,sz))((t)->bs_cookie, h1, o1, h2, o2, cnt)
+
+#define __bs_opname_s(op,size) __bs_c(__bs_c(__bs_c(__bs_c(bs_,op),_),size),_s)
+#define __bs_rs_s(sz, t, h, o) \
+ (*(t)->__bs_opname_s(r,sz))((t)->bs_cookie, h, o)
+#define __bs_ws_s(sz, t, h, o, v) \
+ (*(t)->__bs_opname_s(w,sz))((t)->bs_cookie, h, o, v)
+#define __bs_nonsingle_s(type, sz, t, h, o, a, c) \
+ (*(t)->__bs_opname_s(type,sz))((t)->bs_cookie, h, o, a, c)
+
+
+/*
+ * Mapping and unmapping operations.
+ */
+#define bus_space_map(t, a, s, c, hp) \
+ (*(t)->bs_map)((t)->bs_cookie, (a), (s), (c), (hp))
+#define bus_space_unmap(t, h, s) \
+ (*(t)->bs_unmap)((t)->bs_cookie, (h), (s))
+#define bus_space_subregion(t, h, o, s, hp) \
+ (*(t)->bs_subregion)((t)->bs_cookie, (h), (o), (s), (hp))
+
+
+/*
+ * Allocation and deallocation operations.
+ */
+#define bus_space_alloc(t, rs, re, s, a, b, c, ap, hp) \
+ (*(t)->bs_alloc)((t)->bs_cookie, (rs), (re), (s), (a), (b), \
+ (c), (ap), (hp))
+#define bus_space_free(t, h, s) \
+ (*(t)->bs_free)((t)->bs_cookie, (h), (s))
+
+/*
+ * Bus barrier operations.
+ */
+#define bus_space_barrier(t, h, o, l, f) \
+ (*(t)->bs_barrier)((t)->bs_cookie, (h), (o), (l), (f))
+
+#define BUS_SPACE_BARRIER_READ 0x01
+#define BUS_SPACE_BARRIER_WRITE 0x02
+
+/*
+ * Bus read (single) operations.
+ */
+#define bus_space_read_1(t, h, o) __bs_rs(1,(t),(h),(o))
+#define bus_space_read_2(t, h, o) __bs_rs(2,(t),(h),(o))
+#define bus_space_read_4(t, h, o) __bs_rs(4,(t),(h),(o))
+#define bus_space_read_8(t, h, o) __bs_rs(8,(t),(h),(o))
+
+#define bus_space_read_stream_1(t, h, o) __bs_rs_s(1,(t), (h), (o))
+#define bus_space_read_stream_2(t, h, o) __bs_rs_s(2,(t), (h), (o))
+#define bus_space_read_stream_4(t, h, o) __bs_rs_s(4,(t), (h), (o))
+#define bus_space_read_stream_8(t, h, o) __bs_rs_s(8,8,(t),(h),(o))
+
+/*
+ * Bus read multiple operations.
+ */
+#define bus_space_read_multi_1(t, h, o, a, c) \
+ __bs_nonsingle(rm,1,(t),(h),(o),(a),(c))
+#define bus_space_read_multi_2(t, h, o, a, c) \
+ __bs_nonsingle(rm,2,(t),(h),(o),(a),(c))
+#define bus_space_read_multi_4(t, h, o, a, c) \
+ __bs_nonsingle(rm,4,(t),(h),(o),(a),(c))
+#define bus_space_read_multi_8(t, h, o, a, c) \
+ __bs_nonsingle(rm,8,(t),(h),(o),(a),(c))
+
+#define bus_space_read_multi_stream_1(t, h, o, a, c) \
+ __bs_nonsingle_s(rm,1,(t),(h),(o),(a),(c))
+#define bus_space_read_multi_stream_2(t, h, o, a, c) \
+ __bs_nonsingle_s(rm,2,(t),(h),(o),(a),(c))
+#define bus_space_read_multi_stream_4(t, h, o, a, c) \
+ __bs_nonsingle_s(rm,4,(t),(h),(o),(a),(c))
+#define bus_space_read_multi_stream_8(t, h, o, a, c) \
+ __bs_nonsingle_s(rm,8,(t),(h),(o),(a),(c))
+
+
+/*
+ * Bus read region operations.
+ */
+#define bus_space_read_region_1(t, h, o, a, c) \
+ __bs_nonsingle(rr,1,(t),(h),(o),(a),(c))
+#define bus_space_read_region_2(t, h, o, a, c) \
+ __bs_nonsingle(rr,2,(t),(h),(o),(a),(c))
+#define bus_space_read_region_4(t, h, o, a, c) \
+ __bs_nonsingle(rr,4,(t),(h),(o),(a),(c))
+#define bus_space_read_region_8(t, h, o, a, c) \
+ __bs_nonsingle(rr,8,(t),(h),(o),(a),(c))
+
+#define bus_space_read_region_stream_1(t, h, o, a, c) \
+ __bs_nonsingle_s(rr,1,(t),(h),(o),(a),(c))
+#define bus_space_read_region_stream_2(t, h, o, a, c) \
+ __bs_nonsingle_s(rr,2,(t),(h),(o),(a),(c))
+#define bus_space_read_region_stream_4(t, h, o, a, c) \
+ __bs_nonsingle_s(rr,4,(t),(h),(o),(a),(c))
+#define bus_space_read_region_stream_8(t, h, o, a, c) \
+ __bs_nonsingle_s(rr,8,(t),(h),(o),(a),(c))
+
+
+/*
+ * Bus write (single) operations.
+ */
+#define bus_space_write_1(t, h, o, v) __bs_ws(1,(t),(h),(o),(v))
+#define bus_space_write_2(t, h, o, v) __bs_ws(2,(t),(h),(o),(v))
+#define bus_space_write_4(t, h, o, v) __bs_ws(4,(t),(h),(o),(v))
+#define bus_space_write_8(t, h, o, v) __bs_ws(8,(t),(h),(o),(v))
+
+#define bus_space_write_stream_1(t, h, o, v) __bs_ws_s(1,(t),(h),(o),(v))
+#define bus_space_write_stream_2(t, h, o, v) __bs_ws_s(2,(t),(h),(o),(v))
+#define bus_space_write_stream_4(t, h, o, v) __bs_ws_s(4,(t),(h),(o),(v))
+#define bus_space_write_stream_8(t, h, o, v) __bs_ws_s(8,(t),(h),(o),(v))
+
+
+/*
+ * Bus write multiple operations.
+ */
+#define bus_space_write_multi_1(t, h, o, a, c) \
+ __bs_nonsingle(wm,1,(t),(h),(o),(a),(c))
+#define bus_space_write_multi_2(t, h, o, a, c) \
+ __bs_nonsingle(wm,2,(t),(h),(o),(a),(c))
+#define bus_space_write_multi_4(t, h, o, a, c) \
+ __bs_nonsingle(wm,4,(t),(h),(o),(a),(c))
+#define bus_space_write_multi_8(t, h, o, a, c) \
+ __bs_nonsingle(wm,8,(t),(h),(o),(a),(c))
+
+#define bus_space_write_multi_stream_1(t, h, o, a, c) \
+ __bs_nonsingle_s(wm,1,(t),(h),(o),(a),(c))
+#define bus_space_write_multi_stream_2(t, h, o, a, c) \
+ __bs_nonsingle_s(wm,2,(t),(h),(o),(a),(c))
+#define bus_space_write_multi_stream_4(t, h, o, a, c) \
+ __bs_nonsingle_s(wm,4,(t),(h),(o),(a),(c))
+#define bus_space_write_multi_stream_8(t, h, o, a, c) \
+ __bs_nonsingle_s(wm,8,(t),(h),(o),(a),(c))
+
+
+/*
+ * Bus write region operations.
+ */
+#define bus_space_write_region_1(t, h, o, a, c) \
+ __bs_nonsingle(wr,1,(t),(h),(o),(a),(c))
+#define bus_space_write_region_2(t, h, o, a, c) \
+ __bs_nonsingle(wr,2,(t),(h),(o),(a),(c))
+#define bus_space_write_region_4(t, h, o, a, c) \
+ __bs_nonsingle(wr,4,(t),(h),(o),(a),(c))
+#define bus_space_write_region_8(t, h, o, a, c) \
+ __bs_nonsingle(wr,8,(t),(h),(o),(a),(c))
+
+#define bus_space_write_region_stream_1(t, h, o, a, c) \
+ __bs_nonsingle_s(wr,1,(t),(h),(o),(a),(c))
+#define bus_space_write_region_stream_2(t, h, o, a, c) \
+ __bs_nonsingle_s(wr,2,(t),(h),(o),(a),(c))
+#define bus_space_write_region_stream_4(t, h, o, a, c) \
+ __bs_nonsingle_s(wr,4,(t),(h),(o),(a),(c))
+#define bus_space_write_region_stream_8(t, h, o, a, c) \
+ __bs_nonsingle_s(wr,8,(t),(h),(o),(a),(c))
+
+
+/*
+ * Set multiple operations.
+ */
+#define bus_space_set_multi_1(t, h, o, v, c) \
+ __bs_set(sm,1,(t),(h),(o),(v),(c))
+#define bus_space_set_multi_2(t, h, o, v, c) \
+ __bs_set(sm,2,(t),(h),(o),(v),(c))
+#define bus_space_set_multi_4(t, h, o, v, c) \
+ __bs_set(sm,4,(t),(h),(o),(v),(c))
+#define bus_space_set_multi_8(t, h, o, v, c) \
+ __bs_set(sm,8,(t),(h),(o),(v),(c))
+
+
+/*
+ * Set region operations.
+ */
+#define bus_space_set_region_1(t, h, o, v, c) \
+ __bs_set(sr,1,(t),(h),(o),(v),(c))
+#define bus_space_set_region_2(t, h, o, v, c) \
+ __bs_set(sr,2,(t),(h),(o),(v),(c))
+#define bus_space_set_region_4(t, h, o, v, c) \
+ __bs_set(sr,4,(t),(h),(o),(v),(c))
+#define bus_space_set_region_8(t, h, o, v, c) \
+ __bs_set(sr,8,(t),(h),(o),(v),(c))
+
+
+/*
+ * Copy operations.
+ */
+#define bus_space_copy_region_1(t, h1, o1, h2, o2, c) \
+ __bs_copy(1, t, h1, o1, h2, o2, c)
+#define bus_space_copy_region_2(t, h1, o1, h2, o2, c) \
+ __bs_copy(2, t, h1, o1, h2, o2, c)
+#define bus_space_copy_region_4(t, h1, o1, h2, o2, c) \
+ __bs_copy(4, t, h1, o1, h2, o2, c)
+#define bus_space_copy_region_8(t, h1, o1, h2, o2, c) \
+ __bs_copy(8, t, h1, o1, h2, o2, c)
+
+/*
+ * Macros to provide prototypes for all the functions used in the
+ * bus_space structure
+ */
+
+#define bs_map_proto(f) \
+int __bs_c(f,_bs_map) (void *t, bus_addr_t addr, \
+ bus_size_t size, int cacheable, bus_space_handle_t *bshp);
+
+#define bs_unmap_proto(f) \
+void __bs_c(f,_bs_unmap) (void *t, bus_space_handle_t bsh, \
+ bus_size_t size);
+
+#define bs_subregion_proto(f) \
+int __bs_c(f,_bs_subregion) (void *t, bus_space_handle_t bsh, \
+ bus_size_t offset, bus_size_t size, \
+ bus_space_handle_t *nbshp);
+
+#define bs_alloc_proto(f) \
+int __bs_c(f,_bs_alloc) (void *t, bus_addr_t rstart, \
+ bus_addr_t rend, bus_size_t size, bus_size_t align, \
+ bus_size_t boundary, int cacheable, bus_addr_t *addrp, \
+ bus_space_handle_t *bshp);
+
+#define bs_free_proto(f) \
+void __bs_c(f,_bs_free) (void *t, bus_space_handle_t bsh, \
+ bus_size_t size);
+
+#define bs_barrier_proto(f) \
+void __bs_c(f,_bs_barrier) (void *t, bus_space_handle_t bsh, \
+ bus_size_t offset, bus_size_t len, int flags);
+
+#define bs_r_1_proto(f) \
+u_int8_t __bs_c(f,_bs_r_1) (void *t, bus_space_handle_t bsh, \
+ bus_size_t offset);
+
+#define bs_r_2_proto(f) \
+u_int16_t __bs_c(f,_bs_r_2) (void *t, bus_space_handle_t bsh, \
+ bus_size_t offset);
+
+#define bs_r_4_proto(f) \
+u_int32_t __bs_c(f,_bs_r_4) (void *t, bus_space_handle_t bsh, \
+ bus_size_t offset);
+
+#define bs_r_8_proto(f) \
+u_int64_t __bs_c(f,_bs_r_8) (void *t, bus_space_handle_t bsh, \
+ bus_size_t offset);
+
+#define bs_r_1_s_proto(f) \
+u_int8_t __bs_c(f,_bs_r_1_s) (void *t, bus_space_handle_t bsh, \
+ bus_size_t offset);
+
+#define bs_r_2_s_proto(f) \
+u_int16_t __bs_c(f,_bs_r_2_s) (void *t, bus_space_handle_t bsh, \
+ bus_size_t offset);
+
+#define bs_r_4_s_proto(f) \
+u_int32_t __bs_c(f,_bs_r_4_s) (void *t, bus_space_handle_t bsh, \
+ bus_size_t offset);
+
+#define bs_w_1_proto(f) \
+void __bs_c(f,_bs_w_1) (void *t, bus_space_handle_t bsh, \
+ bus_size_t offset, u_int8_t value);
+
+#define bs_w_2_proto(f) \
+void __bs_c(f,_bs_w_2) (void *t, bus_space_handle_t bsh, \
+ bus_size_t offset, u_int16_t value);
+
+#define bs_w_4_proto(f) \
+void __bs_c(f,_bs_w_4) (void *t, bus_space_handle_t bsh, \
+ bus_size_t offset, u_int32_t value);
+
+#define bs_w_8_proto(f) \
+void __bs_c(f,_bs_w_8) (void *t, bus_space_handle_t bsh, \
+ bus_size_t offset, u_int64_t value);
+
+#define bs_w_1_s_proto(f) \
+void __bs_c(f,_bs_w_1_s) (void *t, bus_space_handle_t bsh, \
+ bus_size_t offset, u_int8_t value);
+
+#define bs_w_2_s_proto(f) \
+void __bs_c(f,_bs_w_2_s) (void *t, bus_space_handle_t bsh, \
+ bus_size_t offset, u_int16_t value);
+
+#define bs_w_4_s_proto(f) \
+void __bs_c(f,_bs_w_4_s) (void *t, bus_space_handle_t bsh, \
+ bus_size_t offset, u_int32_t value);
+
+#define bs_rm_1_proto(f) \
+void __bs_c(f,_bs_rm_1) (void *t, bus_space_handle_t bsh, \
+ bus_size_t offset, u_int8_t *addr, bus_size_t count);
+
+#define bs_rm_2_proto(f) \
+void __bs_c(f,_bs_rm_2) (void *t, bus_space_handle_t bsh, \
+ bus_size_t offset, u_int16_t *addr, bus_size_t count);
+
+#define bs_rm_4_proto(f) \
+void __bs_c(f,_bs_rm_4) (void *t, bus_space_handle_t bsh, \
+ bus_size_t offset, u_int32_t *addr, bus_size_t count);
+
+#define bs_rm_8_proto(f) \
+void __bs_c(f,_bs_rm_8) (void *t, bus_space_handle_t bsh, \
+ bus_size_t offset, u_int64_t *addr, bus_size_t count);
+
+#define bs_wm_1_proto(f) \
+void __bs_c(f,_bs_wm_1) (void *t, bus_space_handle_t bsh, \
+ bus_size_t offset, const u_int8_t *addr, bus_size_t count);
+
+#define bs_wm_2_proto(f) \
+void __bs_c(f,_bs_wm_2) (void *t, bus_space_handle_t bsh, \
+ bus_size_t offset, const u_int16_t *addr, bus_size_t count);
+
+#define bs_wm_4_proto(f) \
+void __bs_c(f,_bs_wm_4) (void *t, bus_space_handle_t bsh, \
+ bus_size_t offset, const u_int32_t *addr, bus_size_t count);
+
+#define bs_wm_8_proto(f) \
+void __bs_c(f,_bs_wm_8) (void *t, bus_space_handle_t bsh, \
+ bus_size_t offset, const u_int64_t *addr, bus_size_t count);
+
+#define bs_rr_1_proto(f) \
+void __bs_c(f, _bs_rr_1) (void *t, bus_space_handle_t bsh, \
+ bus_size_t offset, u_int8_t *addr, bus_size_t count);
+
+#define bs_rr_2_proto(f) \
+void __bs_c(f, _bs_rr_2) (void *t, bus_space_handle_t bsh, \
+ bus_size_t offset, u_int16_t *addr, bus_size_t count);
+
+#define bs_rr_4_proto(f) \
+void __bs_c(f, _bs_rr_4) (void *t, bus_space_handle_t bsh, \
+ bus_size_t offset, u_int32_t *addr, bus_size_t count);
+
+#define bs_rr_8_proto(f) \
+void __bs_c(f, _bs_rr_8) (void *t, bus_space_handle_t bsh, \
+ bus_size_t offset, u_int64_t *addr, bus_size_t count);
+
+#define bs_wr_1_proto(f) \
+void __bs_c(f, _bs_wr_1) (void *t, bus_space_handle_t bsh, \
+ bus_size_t offset, const u_int8_t *addr, bus_size_t count);
+
+#define bs_wr_2_proto(f) \
+void __bs_c(f, _bs_wr_2) (void *t, bus_space_handle_t bsh, \
+ bus_size_t offset, const u_int16_t *addr, bus_size_t count);
+
+#define bs_wr_4_proto(f) \
+void __bs_c(f, _bs_wr_4) (void *t, bus_space_handle_t bsh, \
+ bus_size_t offset, const u_int32_t *addr, bus_size_t count);
+
+#define bs_wr_8_proto(f) \
+void __bs_c(f, _bs_wr_8) (void *t, bus_space_handle_t bsh, \
+ bus_size_t offset, const u_int64_t *addr, bus_size_t count);
+
+#define bs_sm_1_proto(f) \
+void __bs_c(f,_bs_sm_1) (void *t, bus_space_handle_t bsh, \
+ bus_size_t offset, u_int8_t value, bus_size_t count);
+
+#define bs_sm_2_proto(f) \
+void __bs_c(f,_bs_sm_2) (void *t, bus_space_handle_t bsh, \
+ bus_size_t offset, u_int16_t value, bus_size_t count);
+
+#define bs_sm_4_proto(f) \
+void __bs_c(f,_bs_sm_4) (void *t, bus_space_handle_t bsh, \
+ bus_size_t offset, u_int32_t value, bus_size_t count);
+
+#define bs_sm_8_proto(f) \
+void __bs_c(f,_bs_sm_8) (void *t, bus_space_handle_t bsh, \
+ bus_size_t offset, u_int64_t value, bus_size_t count);
+
+#define bs_sr_1_proto(f) \
+void __bs_c(f,_bs_sr_1) (void *t, bus_space_handle_t bsh, \
+ bus_size_t offset, u_int8_t value, bus_size_t count);
+
+#define bs_sr_2_proto(f) \
+void __bs_c(f,_bs_sr_2) (void *t, bus_space_handle_t bsh, \
+ bus_size_t offset, u_int16_t value, bus_size_t count);
+
+#define bs_sr_4_proto(f) \
+void __bs_c(f,_bs_sr_4) (void *t, bus_space_handle_t bsh, \
+ bus_size_t offset, u_int32_t value, bus_size_t count);
+
+#define bs_sr_8_proto(f) \
+void __bs_c(f,_bs_sr_8) (void *t, bus_space_handle_t bsh, \
+ bus_size_t offset, u_int64_t value, bus_size_t count);
+
+#define bs_c_1_proto(f) \
+void __bs_c(f,_bs_c_1) (void *t, bus_space_handle_t bsh1, \
+ bus_size_t offset1, bus_space_handle_t bsh2, \
+ bus_size_t offset2, bus_size_t count);
+
+#define bs_c_2_proto(f) \
+void __bs_c(f,_bs_c_2) (void *t, bus_space_handle_t bsh1, \
+ bus_size_t offset1, bus_space_handle_t bsh2, \
+ bus_size_t offset2, bus_size_t count);
+
+#define bs_c_4_proto(f) \
+void __bs_c(f,_bs_c_4) (void *t, bus_space_handle_t bsh1, \
+ bus_size_t offset1, bus_space_handle_t bsh2, \
+ bus_size_t offset2, bus_size_t count);
+
+#define bs_c_8_proto(f) \
+void __bs_c(f,_bs_c_8) (void *t, bus_space_handle_t bsh1, \
+ bus_size_t offset1, bus_space_handle_t bsh2, \
+ bus_size_t offset2, bus_size_t count);
+
+#define DECLARE_BUS_SPACE_PROTOTYPES(f) \
+ bs_map_proto(f); \
+ bs_unmap_proto(f); \
+ bs_subregion_proto(f); \
+ bs_alloc_proto(f); \
+ bs_free_proto(f); \
+ bs_barrier_proto(f); \
+ bs_r_1_proto(f); \
+ bs_r_2_proto(f); \
+ bs_r_4_proto(f); \
+ bs_r_8_proto(f); \
+ bs_r_1_s_proto(f); \
+ bs_r_2_s_proto(f); \
+ bs_r_4_s_proto(f); \
+ bs_w_1_proto(f); \
+ bs_w_2_proto(f); \
+ bs_w_4_proto(f); \
+ bs_w_8_proto(f); \
+ bs_w_1_s_proto(f); \
+ bs_w_2_s_proto(f); \
+ bs_w_4_s_proto(f); \
+ bs_rm_1_proto(f); \
+ bs_rm_2_proto(f); \
+ bs_rm_4_proto(f); \
+ bs_rm_8_proto(f); \
+ bs_wm_1_proto(f); \
+ bs_wm_2_proto(f); \
+ bs_wm_4_proto(f); \
+ bs_wm_8_proto(f); \
+ bs_rr_1_proto(f); \
+ bs_rr_2_proto(f); \
+ bs_rr_4_proto(f); \
+ bs_rr_8_proto(f); \
+ bs_wr_1_proto(f); \
+ bs_wr_2_proto(f); \
+ bs_wr_4_proto(f); \
+ bs_wr_8_proto(f); \
+ bs_sm_1_proto(f); \
+ bs_sm_2_proto(f); \
+ bs_sm_4_proto(f); \
+ bs_sm_8_proto(f); \
+ bs_sr_1_proto(f); \
+ bs_sr_2_proto(f); \
+ bs_sr_4_proto(f); \
+ bs_sr_8_proto(f); \
+ bs_c_1_proto(f); \
+ bs_c_2_proto(f); \
+ bs_c_4_proto(f); \
+ bs_c_8_proto(f);
+
+#define BUS_SPACE_ALIGNED_POINTER(p, t) ALIGNED_POINTER(p, t)
+
+#define BUS_SPACE_MAXADDR_24BIT 0xFFFFFF
+#define BUS_SPACE_MAXSIZE_24BIT 0xFFFFFF
+
+#define BUS_SPACE_MAXADDR_32BIT 0xFFFFFFFF
+#define BUS_SPACE_MAXSIZE_32BIT 0xFFFFFFFF
+
+#if defined(__mips_n64)
+#define BUS_SPACE_MAXADDR 0xFFFFFFFFFFFFFFFFUL
+#define BUS_SPACE_MAXSIZE 0xFFFFFFFFFFFFFFFFUL
+#else
+#define BUS_SPACE_MAXADDR 0xFFFFFFFFUL
+#define BUS_SPACE_MAXSIZE 0xFFFFFFFFUL
+#endif
+
+
+#define BUS_SPACE_UNRESTRICTED (~0)
+
+/*
+ * declare generic bus space, it suits all needs in
+ */
+DECLARE_BUS_SPACE_PROTOTYPES(generic);
+extern bus_space_tag_t mips_bus_space_generic;
+extern bus_space_tag_t mips_bus_space_fdt;
+
+/* Special bus space for RMI processors */
+#if defined(CPU_RMI) || defined (CPU_NLM)
+extern bus_space_tag_t rmi_bus_space;
+extern bus_space_tag_t rmi_pci_bus_space;
+extern bus_space_tag_t rmi_uart_bus_space;
+#endif
+
+#include <machine/bus_dma.h>
+
+#endif /* _MACHINE_BUS_H_ */
Property changes on: trunk/sys/mips/include/bus.h
___________________________________________________________________
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Added: trunk/sys/mips/include/bus_dma.h
===================================================================
--- trunk/sys/mips/include/bus_dma.h (rev 0)
+++ trunk/sys/mips/include/bus_dma.h 2018-05-26 21:55:02 UTC (rev 9987)
@@ -0,0 +1,35 @@
+/* $MidnightBSD$ */
+/*-
+ * Copyright (c) 2005 Scott Long
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ * $FreeBSD: stable/10/sys/mips/include/bus_dma.h 202175 2010-01-12 21:36:08Z imp $
+ */
+
+#ifndef _MIPS_BUS_DMA_H_
+#define _MIPS_BUS_DMA_H_
+
+#include <sys/bus_dma.h>
+
+#endif /* _MIPS_BUS_DMA_H_ */
Property changes on: trunk/sys/mips/include/bus_dma.h
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Added: trunk/sys/mips/include/cache.h
===================================================================
--- trunk/sys/mips/include/cache.h (rev 0)
+++ trunk/sys/mips/include/cache.h 2018-05-26 21:55:02 UTC (rev 9987)
@@ -0,0 +1,223 @@
+/* $MidnightBSD$ */
+/* $NetBSD: cache.h,v 1.6 2003/02/17 11:35:01 simonb Exp $ */
+
+/*
+ * Copyright 2001 Wasabi Systems, Inc.
+ * All rights reserved.
+ *
+ * Written by Jason R. Thorpe for Wasabi Systems, Inc.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * 3. All advertising materials mentioning features or use of this software
+ * must display the following acknowledgement:
+ * This product includes software developed for the NetBSD Project by
+ * Wasabi Systems, Inc.
+ * 4. The name of Wasabi Systems, Inc. may not be used to endorse
+ * or promote products derived from this software without specific prior
+ * written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * $FreeBSD: stable/10/sys/mips/include/cache.h 232855 2012-03-12 08:13:04Z jmallett $
+ */
+
+#ifndef _MACHINE_CACHE_H_
+#define _MACHINE_CACHE_H_
+
+/*
+ * Cache operations.
+ *
+ * We define the following primitives:
+ *
+ * --- Instruction cache synchronization (mandatory):
+ *
+ * icache_sync_all Synchronize I-cache
+ *
+ * icache_sync_range Synchronize I-cache range
+ *
+ * icache_sync_range_index (index ops)
+ *
+ * --- Primary data cache (mandatory):
+ *
+ * pdcache_wbinv_all Write-back Invalidate primary D-cache
+ *
+ * pdcache_wbinv_range Write-back Invalidate primary D-cache range
+ *
+ * pdcache_wbinv_range_index (index ops)
+ *
+ * pdcache_inv_range Invalidate primary D-cache range
+ *
+ * pdcache_wb_range Write-back primary D-cache range
+ *
+ * --- Secondary data cache (optional):
+ *
+ * sdcache_wbinv_all Write-back Invalidate secondary D-cache
+ *
+ * sdcache_wbinv_range Write-back Invalidate secondary D-cache range
+ *
+ * sdcache_wbinv_range_index (index ops)
+ *
+ * sdcache_inv_range Invalidate secondary D-cache range
+ *
+ * sdcache_wb_range Write-back secondary D-cache range
+ *
+ * There are some rules that must be followed:
+ *
+ * I-cache Synch (all or range):
+ * The goal is to synchronize the instruction stream,
+ * so you may need to write-back dirty data cache
+ * blocks first. If a range is requested, and you
+ * can't synchronize just a range, you have to hit
+ * the whole thing.
+ *
+ * D-cache Write-back Invalidate range:
+ * If you can't WB-Inv a range, you must WB-Inv the
+ * entire D-cache.
+ *
+ * D-cache Invalidate:
+ * If you can't Inv the D-cache without doing a
+ * Write-back, YOU MUST PANIC. This is to catch
+ * errors in calling code. Callers must be aware
+ * of this scenario, and must handle it appropriately
+ * (consider the bus_dma(9) operations).
+ *
+ * D-cache Write-back:
+ * If you can't Write-back without doing an invalidate,
+ * that's fine. Then treat this as a WB-Inv. Skipping
+ * the invalidate is merely an optimization.
+ *
+ * All operations:
+ * Valid virtual addresses must be passed to the
+ * cache operation.
+ *
+ * Finally, these primitives are grouped together in reasonable
+ * ways. For all operations described here, first the primary
+ * cache is frobbed, then the secondary cache frobbed, if the
+ * operation for the secondary cache exists.
+ *
+ * mips_icache_sync_all Synchronize I-cache
+ *
+ * mips_icache_sync_range Synchronize I-cache range
+ *
+ * mips_icache_sync_range_index (index ops)
+ *
+ * mips_dcache_wbinv_all Write-back Invalidate D-cache
+ *
+ * mips_dcache_wbinv_range Write-back Invalidate D-cache range
+ *
+ * mips_dcache_wbinv_range_index (index ops)
+ *
+ * mips_dcache_inv_range Invalidate D-cache range
+ *
+ * mips_dcache_wb_range Write-back D-cache range
+ */
+
+struct mips_cache_ops {
+ void (*mco_icache_sync_all)(void);
+ void (*mco_icache_sync_range)(vm_offset_t, vm_size_t);
+ void (*mco_icache_sync_range_index)(vm_offset_t, vm_size_t);
+
+ void (*mco_pdcache_wbinv_all)(void);
+ void (*mco_pdcache_wbinv_range)(vm_offset_t, vm_size_t);
+ void (*mco_pdcache_wbinv_range_index)(vm_offset_t, vm_size_t);
+ void (*mco_pdcache_inv_range)(vm_offset_t, vm_size_t);
+ void (*mco_pdcache_wb_range)(vm_offset_t, vm_size_t);
+
+ /* These are called only by the (mipsNN) icache functions. */
+ void (*mco_intern_pdcache_wbinv_all)(void);
+ void (*mco_intern_pdcache_wbinv_range_index)(vm_offset_t, vm_size_t);
+ void (*mco_intern_pdcache_wb_range)(vm_offset_t, vm_size_t);
+
+ void (*mco_sdcache_wbinv_all)(void);
+ void (*mco_sdcache_wbinv_range)(vm_offset_t, vm_size_t);
+ void (*mco_sdcache_wbinv_range_index)(vm_offset_t, vm_size_t);
+ void (*mco_sdcache_inv_range)(vm_offset_t, vm_size_t);
+ void (*mco_sdcache_wb_range)(vm_offset_t, vm_size_t);
+
+ /* These are called only by the (mipsNN) icache functions. */
+ void (*mco_intern_sdcache_wbinv_all)(void);
+ void (*mco_intern_sdcache_wbinv_range_index)(vm_offset_t, vm_size_t);
+ void (*mco_intern_sdcache_wb_range)(vm_offset_t, vm_size_t);
+};
+
+extern struct mips_cache_ops mips_cache_ops;
+
+/* PRIMARY CACHE VARIABLES */
+extern int mips_picache_linesize;
+extern int mips_pdcache_linesize;
+
+#define __mco_noargs(prefix, x) \
+do { \
+ (*mips_cache_ops.mco_ ## prefix ## p ## x )(); \
+ if (*mips_cache_ops.mco_ ## prefix ## s ## x ) \
+ (*mips_cache_ops.mco_ ## prefix ## s ## x )(); \
+} while (/*CONSTCOND*/0)
+
+#define __mco_2args(prefix, x, a, b) \
+do { \
+ (*mips_cache_ops.mco_ ## prefix ## p ## x )((a), (b)); \
+ if (*mips_cache_ops.mco_ ## prefix ## s ## x ) \
+ (*mips_cache_ops.mco_ ## prefix ## s ## x )((a), (b)); \
+} while (/*CONSTCOND*/0)
+
+#define mips_icache_sync_all() \
+ (*mips_cache_ops.mco_icache_sync_all)()
+
+#define mips_icache_sync_range(v, s) \
+ (*mips_cache_ops.mco_icache_sync_range)((v), (s))
+
+#define mips_icache_sync_range_index(v, s) \
+ (*mips_cache_ops.mco_icache_sync_range_index)((v), (s))
+
+#define mips_dcache_wbinv_all() \
+ __mco_noargs(, dcache_wbinv_all)
+
+#define mips_dcache_wbinv_range(v, s) \
+ __mco_2args(, dcache_wbinv_range, (v), (s))
+
+#define mips_dcache_wbinv_range_index(v, s) \
+ __mco_2args(, dcache_wbinv_range_index, (v), (s))
+
+#define mips_dcache_inv_range(v, s) \
+ __mco_2args(, dcache_inv_range, (v), (s))
+
+#define mips_dcache_wb_range(v, s) \
+ __mco_2args(, dcache_wb_range, (v), (s))
+
+/*
+ * Private D-cache functions only called from (currently only the
+ * mipsNN) I-cache functions.
+ */
+#define mips_intern_dcache_wbinv_all() \
+ __mco_noargs(intern_, dcache_wbinv_all)
+
+#define mips_intern_dcache_wbinv_range_index(v, s) \
+ __mco_2args(intern_, dcache_wbinv_range_index, (v), (s))
+
+#define mips_intern_dcache_wb_range(v, s) \
+ __mco_2args(intern_, dcache_wb_range, (v), (s))
+
+/* forward declaration */
+struct mips_cpuinfo;
+
+void mips_config_cache(struct mips_cpuinfo *);
+
+#include <machine/cache_mipsNN.h>
+#endif /* _MACHINE_CACHE_H_ */
Property changes on: trunk/sys/mips/include/cache.h
___________________________________________________________________
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Added: trunk/sys/mips/include/cache_mipsNN.h
===================================================================
--- trunk/sys/mips/include/cache_mipsNN.h (rev 0)
+++ trunk/sys/mips/include/cache_mipsNN.h 2018-05-26 21:55:02 UTC (rev 9987)
@@ -0,0 +1,72 @@
+/* $MidnightBSD$ */
+/* $NetBSD: cache_mipsNN.h,v 1.4 2003/02/17 11:35:02 simonb Exp $ */
+
+/*
+ * Copyright 2002 Wasabi Systems, Inc.
+ * All rights reserved.
+ *
+ * Written by Simon Burge for Wasabi Systems, Inc.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * 3. All advertising materials mentioning features or use of this software
+ * must display the following acknowledgement:
+ * This product includes software developed for the NetBSD Project by
+ * Wasabi Systems, Inc.
+ * 4. The name of Wasabi Systems, Inc. may not be used to endorse
+ * or promote products derived from this software without specific prior
+ * written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * $FreeBSD: stable/10/sys/mips/include/cache_mipsNN.h 210311 2010-07-20 19:25:11Z jmallett $
+ */
+#ifndef _MACHINE_CACHE_MIPSNN_H_
+#define _MACHINE_CACHE_MIPSNN_H_
+
+void mipsNN_cache_init(struct mips_cpuinfo *);
+
+void mipsNN_icache_sync_all_16(void);
+void mipsNN_icache_sync_all_32(void);
+void mipsNN_icache_sync_range_16(vm_offset_t, vm_size_t);
+void mipsNN_icache_sync_range_32(vm_offset_t, vm_size_t);
+void mipsNN_icache_sync_range_index_16(vm_offset_t, vm_size_t);
+void mipsNN_icache_sync_range_index_32(vm_offset_t, vm_size_t);
+void mipsNN_pdcache_wbinv_all_16(void);
+void mipsNN_pdcache_wbinv_all_32(void);
+void mipsNN_pdcache_wbinv_range_16(vm_offset_t, vm_size_t);
+void mipsNN_pdcache_wbinv_range_32(vm_offset_t, vm_size_t);
+void mipsNN_pdcache_wbinv_range_index_16(vm_offset_t, vm_size_t);
+void mipsNN_pdcache_wbinv_range_index_32(vm_offset_t, vm_size_t);
+void mipsNN_pdcache_inv_range_16(vm_offset_t, vm_size_t);
+void mipsNN_pdcache_inv_range_32(vm_offset_t, vm_size_t);
+void mipsNN_pdcache_wb_range_16(vm_offset_t, vm_size_t);
+void mipsNN_pdcache_wb_range_32(vm_offset_t, vm_size_t);
+#ifdef CPU_CNMIPS
+void mipsNN_icache_sync_all_128(void);
+void mipsNN_icache_sync_range_128(vm_offset_t, vm_size_t);
+void mipsNN_icache_sync_range_index_128(vm_offset_t, vm_size_t);
+void mipsNN_pdcache_wbinv_all_128(void);
+void mipsNN_pdcache_wbinv_range_128(vm_offset_t, vm_size_t);
+void mipsNN_pdcache_wbinv_range_index_128(vm_offset_t, vm_size_t);
+void mipsNN_pdcache_inv_range_128(vm_offset_t, vm_size_t);
+void mipsNN_pdcache_wb_range_128(vm_offset_t, vm_size_t);
+#endif
+
+#endif /* _MACHINE_CACHE_MIPSNN_H_ */
Property changes on: trunk/sys/mips/include/cache_mipsNN.h
___________________________________________________________________
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Added: trunk/sys/mips/include/cache_r4k.h
===================================================================
--- trunk/sys/mips/include/cache_r4k.h (rev 0)
+++ trunk/sys/mips/include/cache_r4k.h 2018-05-26 21:55:02 UTC (rev 9987)
@@ -0,0 +1,384 @@
+/* $MidnightBSD$ */
+/* $NetBSD: cache_r4k.h,v 1.10 2003/03/08 04:43:26 rafal Exp $ */
+
+/*
+ * Copyright 2001 Wasabi Systems, Inc.
+ * All rights reserved.
+ *
+ * Written by Jason R. Thorpe for Wasabi Systems, Inc.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * 3. All advertising materials mentioning features or use of this software
+ * must display the following acknowledgement:
+ * This product includes software developed for the NetBSD Project by
+ * Wasabi Systems, Inc.
+ * 4. The name of Wasabi Systems, Inc. may not be used to endorse
+ * or promote products derived from this software without specific prior
+ * written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * $FreeBSD: stable/10/sys/mips/include/cache_r4k.h 202175 2010-01-12 21:36:08Z imp $
+ */
+
+/*
+ * Cache definitions/operations for R4000-style caches.
+ */
+
+#define CACHE_R4K_I 0
+#define CACHE_R4K_D 1
+#define CACHE_R4K_SI 2
+#define CACHE_R4K_SD 3
+
+#define CACHEOP_R4K_INDEX_INV (0 << 2) /* I, SI */
+#define CACHEOP_R4K_INDEX_WB_INV (0 << 2) /* D, SD */
+#define CACHEOP_R4K_INDEX_LOAD_TAG (1 << 2) /* all */
+#define CACHEOP_R4K_INDEX_STORE_TAG (2 << 2) /* all */
+#define CACHEOP_R4K_CREATE_DIRTY_EXCL (3 << 2) /* D, SD */
+#define CACHEOP_R4K_HIT_INV (4 << 2) /* all */
+#define CACHEOP_R4K_HIT_WB_INV (5 << 2) /* D, SD */
+#define CACHEOP_R4K_FILL (5 << 2) /* I */
+#define CACHEOP_R4K_HIT_WB (6 << 2) /* I, D, SD */
+#define CACHEOP_R4K_HIT_SET_VIRTUAL (7 << 2) /* SI, SD */
+
+#if !defined(LOCORE)
+
+/*
+ * cache_r4k_op_line:
+ *
+ * Perform the specified cache operation on a single line.
+ */
+#define cache_op_r4k_line(va, op) \
+do { \
+ __asm __volatile( \
+ ".set noreorder \n\t" \
+ "cache %1, 0(%0) \n\t" \
+ ".set reorder" \
+ : \
+ : "r" (va), "i" (op) \
+ : "memory"); \
+} while (/*CONSTCOND*/0)
+
+/*
+ * cache_r4k_op_8lines_16:
+ *
+ * Perform the specified cache operation on 8 16-byte cache lines.
+ */
+#define cache_r4k_op_8lines_16(va, op) \
+do { \
+ __asm __volatile( \
+ ".set noreorder \n\t" \
+ "cache %1, 0x00(%0); cache %1, 0x10(%0) \n\t" \
+ "cache %1, 0x20(%0); cache %1, 0x30(%0) \n\t" \
+ "cache %1, 0x40(%0); cache %1, 0x50(%0) \n\t" \
+ "cache %1, 0x60(%0); cache %1, 0x70(%0) \n\t" \
+ ".set reorder" \
+ : \
+ : "r" (va), "i" (op) \
+ : "memory"); \
+} while (/*CONSTCOND*/0)
+
+/*
+ * cache_r4k_op_8lines_32:
+ *
+ * Perform the specified cache operation on 8 32-byte cache lines.
+ */
+#define cache_r4k_op_8lines_32(va, op) \
+do { \
+ __asm __volatile( \
+ ".set noreorder \n\t" \
+ "cache %1, 0x00(%0); cache %1, 0x20(%0) \n\t" \
+ "cache %1, 0x40(%0); cache %1, 0x60(%0) \n\t" \
+ "cache %1, 0x80(%0); cache %1, 0xa0(%0) \n\t" \
+ "cache %1, 0xc0(%0); cache %1, 0xe0(%0) \n\t" \
+ ".set reorder" \
+ : \
+ : "r" (va), "i" (op) \
+ : "memory"); \
+} while (/*CONSTCOND*/0)
+
+/*
+ * cache_r4k_op_32lines_16:
+ *
+ * Perform the specified cache operation on 32 16-byte
+ * cache lines.
+ */
+#define cache_r4k_op_32lines_16(va, op) \
+do { \
+ __asm __volatile( \
+ ".set noreorder \n\t" \
+ "cache %1, 0x000(%0); cache %1, 0x010(%0); \n\t" \
+ "cache %1, 0x020(%0); cache %1, 0x030(%0); \n\t" \
+ "cache %1, 0x040(%0); cache %1, 0x050(%0); \n\t" \
+ "cache %1, 0x060(%0); cache %1, 0x070(%0); \n\t" \
+ "cache %1, 0x080(%0); cache %1, 0x090(%0); \n\t" \
+ "cache %1, 0x0a0(%0); cache %1, 0x0b0(%0); \n\t" \
+ "cache %1, 0x0c0(%0); cache %1, 0x0d0(%0); \n\t" \
+ "cache %1, 0x0e0(%0); cache %1, 0x0f0(%0); \n\t" \
+ "cache %1, 0x100(%0); cache %1, 0x110(%0); \n\t" \
+ "cache %1, 0x120(%0); cache %1, 0x130(%0); \n\t" \
+ "cache %1, 0x140(%0); cache %1, 0x150(%0); \n\t" \
+ "cache %1, 0x160(%0); cache %1, 0x170(%0); \n\t" \
+ "cache %1, 0x180(%0); cache %1, 0x190(%0); \n\t" \
+ "cache %1, 0x1a0(%0); cache %1, 0x1b0(%0); \n\t" \
+ "cache %1, 0x1c0(%0); cache %1, 0x1d0(%0); \n\t" \
+ "cache %1, 0x1e0(%0); cache %1, 0x1f0(%0); \n\t" \
+ ".set reorder" \
+ : \
+ : "r" (va), "i" (op) \
+ : "memory"); \
+} while (/*CONSTCOND*/0)
+
+/*
+ * cache_r4k_op_32lines_32:
+ *
+ * Perform the specified cache operation on 32 32-byte
+ * cache lines.
+ */
+#define cache_r4k_op_32lines_32(va, op) \
+do { \
+ __asm __volatile( \
+ ".set noreorder \n\t" \
+ "cache %1, 0x000(%0); cache %1, 0x020(%0); \n\t" \
+ "cache %1, 0x040(%0); cache %1, 0x060(%0); \n\t" \
+ "cache %1, 0x080(%0); cache %1, 0x0a0(%0); \n\t" \
+ "cache %1, 0x0c0(%0); cache %1, 0x0e0(%0); \n\t" \
+ "cache %1, 0x100(%0); cache %1, 0x120(%0); \n\t" \
+ "cache %1, 0x140(%0); cache %1, 0x160(%0); \n\t" \
+ "cache %1, 0x180(%0); cache %1, 0x1a0(%0); \n\t" \
+ "cache %1, 0x1c0(%0); cache %1, 0x1e0(%0); \n\t" \
+ "cache %1, 0x200(%0); cache %1, 0x220(%0); \n\t" \
+ "cache %1, 0x240(%0); cache %1, 0x260(%0); \n\t" \
+ "cache %1, 0x280(%0); cache %1, 0x2a0(%0); \n\t" \
+ "cache %1, 0x2c0(%0); cache %1, 0x2e0(%0); \n\t" \
+ "cache %1, 0x300(%0); cache %1, 0x320(%0); \n\t" \
+ "cache %1, 0x340(%0); cache %1, 0x360(%0); \n\t" \
+ "cache %1, 0x380(%0); cache %1, 0x3a0(%0); \n\t" \
+ "cache %1, 0x3c0(%0); cache %1, 0x3e0(%0); \n\t" \
+ ".set reorder" \
+ : \
+ : "r" (va), "i" (op) \
+ : "memory"); \
+} while (/*CONSTCOND*/0)
+
+/*
+ * cache_r4k_op_32lines_128:
+ *
+ * Perform the specified cache operation on 32 128-byte
+ * cache lines.
+ */
+#define cache_r4k_op_32lines_128(va, op) \
+do { \
+ __asm __volatile( \
+ ".set noreorder \n\t" \
+ "cache %1, 0x0000(%0); cache %1, 0x0080(%0); \n\t" \
+ "cache %1, 0x0100(%0); cache %1, 0x0180(%0); \n\t" \
+ "cache %1, 0x0200(%0); cache %1, 0x0280(%0); \n\t" \
+ "cache %1, 0x0300(%0); cache %1, 0x0380(%0); \n\t" \
+ "cache %1, 0x0400(%0); cache %1, 0x0480(%0); \n\t" \
+ "cache %1, 0x0500(%0); cache %1, 0x0580(%0); \n\t" \
+ "cache %1, 0x0600(%0); cache %1, 0x0680(%0); \n\t" \
+ "cache %1, 0x0700(%0); cache %1, 0x0780(%0); \n\t" \
+ "cache %1, 0x0800(%0); cache %1, 0x0880(%0); \n\t" \
+ "cache %1, 0x0900(%0); cache %1, 0x0980(%0); \n\t" \
+ "cache %1, 0x0a00(%0); cache %1, 0x0a80(%0); \n\t" \
+ "cache %1, 0x0b00(%0); cache %1, 0x0b80(%0); \n\t" \
+ "cache %1, 0x0c00(%0); cache %1, 0x0c80(%0); \n\t" \
+ "cache %1, 0x0d00(%0); cache %1, 0x0d80(%0); \n\t" \
+ "cache %1, 0x0e00(%0); cache %1, 0x0e80(%0); \n\t" \
+ "cache %1, 0x0f00(%0); cache %1, 0x0f80(%0); \n\t" \
+ ".set reorder" \
+ : \
+ : "r" (va), "i" (op) \
+ : "memory"); \
+} while (/*CONSTCOND*/0)
+
+/*
+ * cache_r4k_op_16lines_16_2way:
+ *
+ * Perform the specified cache operation on 16 16-byte
+ * cache lines, 2-ways.
+ */
+#define cache_r4k_op_16lines_16_2way(va1, va2, op) \
+do { \
+ __asm __volatile( \
+ ".set noreorder \n\t" \
+ "cache %2, 0x000(%0); cache %2, 0x000(%1); \n\t" \
+ "cache %2, 0x010(%0); cache %2, 0x010(%1); \n\t" \
+ "cache %2, 0x020(%0); cache %2, 0x020(%1); \n\t" \
+ "cache %2, 0x030(%0); cache %2, 0x030(%1); \n\t" \
+ "cache %2, 0x040(%0); cache %2, 0x040(%1); \n\t" \
+ "cache %2, 0x050(%0); cache %2, 0x050(%1); \n\t" \
+ "cache %2, 0x060(%0); cache %2, 0x060(%1); \n\t" \
+ "cache %2, 0x070(%0); cache %2, 0x070(%1); \n\t" \
+ "cache %2, 0x080(%0); cache %2, 0x080(%1); \n\t" \
+ "cache %2, 0x090(%0); cache %2, 0x090(%1); \n\t" \
+ "cache %2, 0x0a0(%0); cache %2, 0x0a0(%1); \n\t" \
+ "cache %2, 0x0b0(%0); cache %2, 0x0b0(%1); \n\t" \
+ "cache %2, 0x0c0(%0); cache %2, 0x0c0(%1); \n\t" \
+ "cache %2, 0x0d0(%0); cache %2, 0x0d0(%1); \n\t" \
+ "cache %2, 0x0e0(%0); cache %2, 0x0e0(%1); \n\t" \
+ "cache %2, 0x0f0(%0); cache %2, 0x0f0(%1); \n\t" \
+ ".set reorder" \
+ : \
+ : "r" (va1), "r" (va2), "i" (op) \
+ : "memory"); \
+} while (/*CONSTCOND*/0)
+
+/*
+ * cache_r4k_op_16lines_32_2way:
+ *
+ * Perform the specified cache operation on 16 32-byte
+ * cache lines, 2-ways.
+ */
+#define cache_r4k_op_16lines_32_2way(va1, va2, op) \
+do { \
+ __asm __volatile( \
+ ".set noreorder \n\t" \
+ "cache %2, 0x000(%0); cache %2, 0x000(%1); \n\t" \
+ "cache %2, 0x020(%0); cache %2, 0x020(%1); \n\t" \
+ "cache %2, 0x040(%0); cache %2, 0x040(%1); \n\t" \
+ "cache %2, 0x060(%0); cache %2, 0x060(%1); \n\t" \
+ "cache %2, 0x080(%0); cache %2, 0x080(%1); \n\t" \
+ "cache %2, 0x0a0(%0); cache %2, 0x0a0(%1); \n\t" \
+ "cache %2, 0x0c0(%0); cache %2, 0x0c0(%1); \n\t" \
+ "cache %2, 0x0e0(%0); cache %2, 0x0e0(%1); \n\t" \
+ "cache %2, 0x100(%0); cache %2, 0x100(%1); \n\t" \
+ "cache %2, 0x120(%0); cache %2, 0x120(%1); \n\t" \
+ "cache %2, 0x140(%0); cache %2, 0x140(%1); \n\t" \
+ "cache %2, 0x160(%0); cache %2, 0x160(%1); \n\t" \
+ "cache %2, 0x180(%0); cache %2, 0x180(%1); \n\t" \
+ "cache %2, 0x1a0(%0); cache %2, 0x1a0(%1); \n\t" \
+ "cache %2, 0x1c0(%0); cache %2, 0x1c0(%1); \n\t" \
+ "cache %2, 0x1e0(%0); cache %2, 0x1e0(%1); \n\t" \
+ ".set reorder" \
+ : \
+ : "r" (va1), "r" (va2), "i" (op) \
+ : "memory"); \
+} while (/*CONSTCOND*/0)
+
+/*
+ * cache_r4k_op_8lines_16_4way:
+ *
+ * Perform the specified cache operation on 8 16-byte
+ * cache lines, 4-ways.
+ */
+#define cache_r4k_op_8lines_16_4way(va1, va2, va3, va4, op) \
+do { \
+ __asm __volatile( \
+ ".set noreorder \n\t" \
+ "cache %4, 0x000(%0); cache %4, 0x000(%1); \n\t" \
+ "cache %4, 0x000(%2); cache %4, 0x000(%3); \n\t" \
+ "cache %4, 0x010(%0); cache %4, 0x010(%1); \n\t" \
+ "cache %4, 0x010(%2); cache %4, 0x010(%3); \n\t" \
+ "cache %4, 0x020(%0); cache %4, 0x020(%1); \n\t" \
+ "cache %4, 0x020(%2); cache %4, 0x020(%3); \n\t" \
+ "cache %4, 0x030(%0); cache %4, 0x030(%1); \n\t" \
+ "cache %4, 0x030(%2); cache %4, 0x030(%3); \n\t" \
+ "cache %4, 0x040(%0); cache %4, 0x040(%1); \n\t" \
+ "cache %4, 0x040(%2); cache %4, 0x040(%3); \n\t" \
+ "cache %4, 0x050(%0); cache %4, 0x050(%1); \n\t" \
+ "cache %4, 0x050(%2); cache %4, 0x050(%3); \n\t" \
+ "cache %4, 0x060(%0); cache %4, 0x060(%1); \n\t" \
+ "cache %4, 0x060(%2); cache %4, 0x060(%3); \n\t" \
+ "cache %4, 0x070(%0); cache %4, 0x070(%1); \n\t" \
+ "cache %4, 0x070(%2); cache %4, 0x070(%3); \n\t" \
+ ".set reorder" \
+ : \
+ : "r" (va1), "r" (va2), "r" (va3), "r" (va4), "i" (op) \
+ : "memory"); \
+} while (/*CONSTCOND*/0)
+
+/*
+ * cache_r4k_op_8lines_32_4way:
+ *
+ * Perform the specified cache operation on 8 32-byte
+ * cache lines, 4-ways.
+ */
+#define cache_r4k_op_8lines_32_4way(va1, va2, va3, va4, op) \
+do { \
+ __asm __volatile( \
+ ".set noreorder \n\t" \
+ "cache %4, 0x000(%0); cache %4, 0x000(%1); \n\t" \
+ "cache %4, 0x000(%2); cache %4, 0x000(%3); \n\t" \
+ "cache %4, 0x020(%0); cache %4, 0x020(%1); \n\t" \
+ "cache %4, 0x020(%2); cache %4, 0x020(%3); \n\t" \
+ "cache %4, 0x040(%0); cache %4, 0x040(%1); \n\t" \
+ "cache %4, 0x040(%2); cache %4, 0x040(%3); \n\t" \
+ "cache %4, 0x060(%0); cache %4, 0x060(%1); \n\t" \
+ "cache %4, 0x060(%2); cache %4, 0x060(%3); \n\t" \
+ "cache %4, 0x080(%0); cache %4, 0x080(%1); \n\t" \
+ "cache %4, 0x080(%2); cache %4, 0x080(%3); \n\t" \
+ "cache %4, 0x0a0(%0); cache %4, 0x0a0(%1); \n\t" \
+ "cache %4, 0x0a0(%2); cache %4, 0x0a0(%3); \n\t" \
+ "cache %4, 0x0c0(%0); cache %4, 0x0c0(%1); \n\t" \
+ "cache %4, 0x0c0(%2); cache %4, 0x0c0(%3); \n\t" \
+ "cache %4, 0x0e0(%0); cache %4, 0x0e0(%1); \n\t" \
+ "cache %4, 0x0e0(%2); cache %4, 0x0e0(%3); \n\t" \
+ ".set reorder" \
+ : \
+ : "r" (va1), "r" (va2), "r" (va3), "r" (va4), "i" (op) \
+ : "memory"); \
+} while (/*CONSTCOND*/0)
+
+void r4k_icache_sync_all_16(void);
+void r4k_icache_sync_range_16(vm_paddr_t, vm_size_t);
+void r4k_icache_sync_range_index_16(vm_paddr_t, vm_size_t);
+
+void r4k_icache_sync_all_32(void);
+void r4k_icache_sync_range_32(vm_paddr_t, vm_size_t);
+void r4k_icache_sync_range_index_32(vm_paddr_t, vm_size_t);
+
+void r4k_pdcache_wbinv_all_16(void);
+void r4k_pdcache_wbinv_range_16(vm_paddr_t, vm_size_t);
+void r4k_pdcache_wbinv_range_index_16(vm_paddr_t, vm_size_t);
+
+void r4k_pdcache_inv_range_16(vm_paddr_t, vm_size_t);
+void r4k_pdcache_wb_range_16(vm_paddr_t, vm_size_t);
+
+void r4k_pdcache_wbinv_all_32(void);
+void r4k_pdcache_wbinv_range_32(vm_paddr_t, vm_size_t);
+void r4k_pdcache_wbinv_range_index_32(vm_paddr_t, vm_size_t);
+
+void r4k_pdcache_inv_range_32(vm_paddr_t, vm_size_t);
+void r4k_pdcache_wb_range_32(vm_paddr_t, vm_size_t);
+
+void r4k_sdcache_wbinv_all_32(void);
+void r4k_sdcache_wbinv_range_32(vm_paddr_t, vm_size_t);
+void r4k_sdcache_wbinv_range_index_32(vm_paddr_t, vm_size_t);
+
+void r4k_sdcache_inv_range_32(vm_paddr_t, vm_size_t);
+void r4k_sdcache_wb_range_32(vm_paddr_t, vm_size_t);
+
+void r4k_sdcache_wbinv_all_128(void);
+void r4k_sdcache_wbinv_range_128(vm_paddr_t, vm_size_t);
+void r4k_sdcache_wbinv_range_index_128(vm_paddr_t, vm_size_t);
+
+void r4k_sdcache_inv_range_128(vm_paddr_t, vm_size_t);
+void r4k_sdcache_wb_range_128(vm_paddr_t, vm_size_t);
+
+void r4k_sdcache_wbinv_all_generic(void);
+void r4k_sdcache_wbinv_range_generic(vm_paddr_t, vm_size_t);
+void r4k_sdcache_wbinv_range_index_generic(vm_paddr_t, vm_size_t);
+
+void r4k_sdcache_inv_range_generic(vm_paddr_t, vm_size_t);
+void r4k_sdcache_wb_range_generic(vm_paddr_t, vm_size_t);
+
+#endif /* !LOCORE */
Property changes on: trunk/sys/mips/include/cache_r4k.h
___________________________________________________________________
Added: svn:eol-style
## -0,0 +1 ##
+native
\ No newline at end of property
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## -0,0 +1 ##
+MidnightBSD=%H
\ No newline at end of property
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## -0,0 +1 ##
+text/plain
\ No newline at end of property
Added: trunk/sys/mips/include/cdefs.h
===================================================================
--- trunk/sys/mips/include/cdefs.h (rev 0)
+++ trunk/sys/mips/include/cdefs.h 2018-05-26 21:55:02 UTC (rev 9987)
@@ -0,0 +1,77 @@
+/* $MidnightBSD$ */
+/* $NetBSD: cdefs.h,v 1.12 2006/08/27 19:04:30 matt Exp $ */
+
+/*
+ * Copyright (c) 1995 Carnegie-Mellon University.
+ * All rights reserved.
+ *
+ * Author: Chris G. Demetriou
+ *
+ * Permission to use, copy, modify and distribute this software and
+ * its documentation is hereby granted, provided that both the copyright
+ * notice and this permission notice appear in all copies of the
+ * software, derivative works or modified versions, and any portions
+ * thereof, and that both notices appear in supporting documentation.
+ *
+ * CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS"
+ * CONDITION. CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND
+ * FOR ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE.
+ *
+ * Carnegie Mellon requests users of this software to return to
+ *
+ * Software Distribution Coordinator or Software.Distribution at CS.CMU.EDU
+ * School of Computer Science
+ * Carnegie Mellon University
+ * Pittsburgh PA 15213-3890
+ *
+ * any improvements or extensions that they make and grant Carnegie the
+ * rights to redistribute these changes.
+ *
+ * $FreeBSD: stable/10/sys/mips/include/cdefs.h 204557 2010-03-02 07:27:30Z imp $
+ */
+
+#ifndef _MIPS_CDEFS_H_
+#define _MIPS_CDEFS_H_
+
+/*
+ * These are depreciated. Use __mips_{o32,o64,n32,n64} instead.
+ */
+/* MIPS Subprogram Interface Model */
+#define _MIPS_SIM_ABIX32 4 /* 64 bit safe, ILP32 o32 model */
+#define _MIPS_SIM_ABI64 3
+#define _MIPS_SIM_NABI32 2 /* 64bit safe, ILP32 n32 model */
+#define _MIPS_SIM_ABI32 1
+
+#define _MIPS_BSD_API_LP32 _MIPS_SIM_ABI32
+#define _MIPS_BSD_API_LP32_64CLEAN _MIPS_SIM_ABIX32
+#define _MIPS_BSD_API_LP64 _MIPS_SIM_ABI64
+
+#define _MIPS_BSD_API_O32 _MIPS_SIM_ABI32
+#define _MIPS_BSD_API_O64 _MIPS_SIM_ABIX32
+#define _MIPS_BSD_API_N32 _MIPS_SIM_NABI32
+#define _MIPS_BSD_API_N64 _MIPS_SIM_ABI64
+
+#define _MIPS_SIM_NEWABI_P(abi) ((abi) == _MIPS_SIM_NABI32 || \
+ (abi) == _MIPS_SIM_ABI64)
+
+#define _MIPS_SIM_LP64_P(abi) ((abi) == _MIPS_SIM_ABIX32 || \
+ (abi) == _MIPS_SIM_ABI64)
+
+#if defined(__mips_n64)
+#define _MIPS_BSD_API _MIPS_BSD_API_N64
+#elif defined(__mips_n32)
+#define _MIPS_BSD_API _MIPS_BSD_API_N32
+#elif defined(__mips_o64)
+#define _MIPS_BSD_API _MIPS_BSD_API_O64
+#else
+#define _MIPS_BSD_API _MIPS_BSD_API_O32
+#endif
+
+#define _MIPS_ISA_MIPS1 1
+#define _MIPS_ISA_MIPS2 2
+#define _MIPS_ISA_MIPS3 3
+#define _MIPS_ISA_MIPS4 4
+#define _MIPS_ISA_MIPS32 5
+#define _MIPS_ISA_MIPS64 6
+
+#endif /* !_MIPS_CDEFS_H_ */
Property changes on: trunk/sys/mips/include/cdefs.h
___________________________________________________________________
Added: svn:eol-style
## -0,0 +1 ##
+native
\ No newline at end of property
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## -0,0 +1 ##
+MidnightBSD=%H
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+text/plain
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Added: trunk/sys/mips/include/clock.h
===================================================================
--- trunk/sys/mips/include/clock.h (rev 0)
+++ trunk/sys/mips/include/clock.h 2018-05-26 21:55:02 UTC (rev 9987)
@@ -0,0 +1,48 @@
+/* $MidnightBSD$ */
+/*
+ * Garrett Wollman, September 1994.
+ * This file is in the public domain.
+ * Kernel interface to machine-dependent clock driver.
+ *
+ * JNPR: clock.h,v 1.6.2.1 2007/08/29 09:36:05 girish
+ * from: src/sys/alpha/include/clock.h,v 1.5 1999/12/29 04:27:55 peter
+ * $FreeBSD: stable/10/sys/mips/include/clock.h 210100 2010-07-15 01:58:20Z imp $
+ */
+
+#ifndef _MACHINE_CLOCK_H_
+#define _MACHINE_CLOCK_H_
+
+#include <sys/bus.h>
+
+#ifdef _KERNEL
+
+extern int cpu_clock;
+
+extern uint32_t clockintr(uint32_t, struct trapframe *);
+
+#define wall_cmos_clock 0
+#define adjkerntz 0
+
+/*
+ * Default is to assume a CPU pipeline clock of 100Mhz, and
+ * that CP0_COUNT increments every 2 cycles.
+ */
+#define MIPS_DEFAULT_HZ (100 * 1000 * 1000)
+
+void mips_timer_early_init(uint64_t clock_hz);
+void mips_timer_init_params(uint64_t, int);
+
+extern uint64_t counter_freq;
+extern int clocks_running;
+
+/*
+ * The 'platform_timecounter' pointer may be used to register a
+ * platform-specific timecounter.
+ *
+ * A default timecounter based on the CP0 COUNT register is always registered.
+ */
+extern struct timecounter *platform_timecounter;
+
+#endif
+
+#endif /* !_MACHINE_CLOCK_H_ */
Property changes on: trunk/sys/mips/include/clock.h
___________________________________________________________________
Added: svn:eol-style
## -0,0 +1 ##
+native
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## -0,0 +1 ##
+MidnightBSD=%H
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+text/plain
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Added: trunk/sys/mips/include/counter.h
===================================================================
--- trunk/sys/mips/include/counter.h (rev 0)
+++ trunk/sys/mips/include/counter.h 2018-05-26 21:55:02 UTC (rev 9987)
@@ -0,0 +1,95 @@
+/* $MidnightBSD$ */
+/*-
+ * Copyright (c) 2012 Konstantin Belousov <kib at FreeBSD.org>
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ * $FreeBSD: stable/10/sys/mips/include/counter.h 252434 2013-07-01 02:48:27Z kib $
+ */
+
+#ifndef __MACHINE_COUNTER_H__
+#define __MACHINE_COUNTER_H__
+
+#include <sys/pcpu.h>
+#ifdef INVARIANTS
+#include <sys/proc.h>
+#endif
+
+#define counter_enter() critical_enter()
+#define counter_exit() critical_exit()
+
+#ifdef IN_SUBR_COUNTER_C
+/* XXXKIB non-atomic 64bit read on 32bit */
+static inline uint64_t
+counter_u64_read_one(uint64_t *p, int cpu)
+{
+
+ return (*(uint64_t *)((char *)p + sizeof(struct pcpu) * cpu));
+}
+
+static inline uint64_t
+counter_u64_fetch_inline(uint64_t *p)
+{
+ uint64_t r;
+ int i;
+
+ r = 0;
+ for (i = 0; i < mp_ncpus; i++)
+ r += counter_u64_read_one((uint64_t *)p, i);
+
+ return (r);
+}
+
+/* XXXKIB non-atomic 64bit store on 32bit, might interrupt increment */
+static void
+counter_u64_zero_one_cpu(void *arg)
+{
+
+ *((uint64_t *)((char *)arg + sizeof(struct pcpu) *
+ PCPU_GET(cpuid))) = 0;
+}
+
+static inline void
+counter_u64_zero_inline(counter_u64_t c)
+{
+
+ smp_rendezvous(smp_no_rendevous_barrier, counter_u64_zero_one_cpu,
+ smp_no_rendevous_barrier, c);
+}
+#endif
+
+#define counter_u64_add_protected(c, inc) do { \
+ CRITICAL_ASSERT(curthread); \
+ *(uint64_t *)zpcpu_get(c) += (inc); \
+} while (0)
+
+static inline void
+counter_u64_add(counter_u64_t c, int64_t inc)
+{
+
+ counter_enter();
+ counter_u64_add_protected(c, inc);
+ counter_exit();
+}
+
+#endif /* ! __MACHINE_COUNTER_H__ */
Property changes on: trunk/sys/mips/include/counter.h
___________________________________________________________________
Added: svn:eol-style
## -0,0 +1 ##
+native
\ No newline at end of property
Added: svn:keywords
## -0,0 +1 ##
+MidnightBSD=%H
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+text/plain
\ No newline at end of property
Added: trunk/sys/mips/include/cpu.h
===================================================================
--- trunk/sys/mips/include/cpu.h (rev 0)
+++ trunk/sys/mips/include/cpu.h 2018-05-26 21:55:02 UTC (rev 9987)
@@ -0,0 +1,90 @@
+/* $MidnightBSD$ */
+/* $OpenBSD: cpu.h,v 1.4 1998/09/15 10:50:12 pefo Exp $ */
+
+/*-
+ * Copyright (c) 1992, 1993
+ * The Regents of the University of California. All rights reserved.
+ *
+ * This code is derived from software contributed to Berkeley by
+ * Ralph Campbell and Rick Macklem.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * 4. Neither the name of the University nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ * Copyright (C) 1989 Digital Equipment Corporation.
+ * Permission to use, copy, modify, and distribute this software and
+ * its documentation for any purpose and without fee is hereby granted,
+ * provided that the above copyright notice appears in all copies.
+ * Digital Equipment Corporation makes no representations about the
+ * suitability of this software for any purpose. It is provided "as is"
+ * without express or implied warranty.
+ *
+ * from: @(#)cpu.h 8.4 (Berkeley) 1/4/94
+ * JNPR: cpu.h,v 1.9.2.2 2007/09/10 08:23:46 girish
+ * $FreeBSD: stable/10/sys/mips/include/cpu.h 253750 2013-07-28 18:44:17Z avg $
+ */
+
+#ifndef _MACHINE_CPU_H_
+#define _MACHINE_CPU_H_
+
+#include <machine/endian.h>
+
+/* BEGIN: these are going away */
+
+#define soft_int_mask(softintr) (1 << ((softintr) + 8))
+#define hard_int_mask(hardintr) (1 << ((hardintr) + 10))
+
+/* END: These are going away */
+
+/*
+ * Exported definitions unique to mips cpu support.
+ */
+
+#ifndef _LOCORE
+#include <machine/cpufunc.h>
+#include <machine/frame.h>
+
+#define TRAPF_USERMODE(framep) (((framep)->sr & MIPS_SR_KSU_USER) != 0)
+#define TRAPF_PC(framep) ((framep)->pc)
+#define cpu_getstack(td) ((td)->td_frame->sp)
+#define cpu_setstack(td, nsp) ((td)->td_frame->sp = (nsp))
+#define cpu_spinwait() /* nothing */
+
+/*
+ * A machine-independent interface to the CPU's counter.
+ */
+#define get_cyclecount() mips_rd_count()
+#endif /* !_LOCORE */
+
+#if defined(_KERNEL) && !defined(_LOCORE)
+
+extern char btext[];
+extern char etext[];
+
+void swi_vm(void *);
+void cpu_halt(void);
+void cpu_reset(void);
+
+#endif /* _KERNEL */
+#endif /* !_MACHINE_CPU_H_ */
Property changes on: trunk/sys/mips/include/cpu.h
___________________________________________________________________
Added: svn:eol-style
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+native
\ No newline at end of property
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## -0,0 +1 ##
+MidnightBSD=%H
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+text/plain
\ No newline at end of property
Added: trunk/sys/mips/include/cpufunc.h
===================================================================
--- trunk/sys/mips/include/cpufunc.h (rev 0)
+++ trunk/sys/mips/include/cpufunc.h 2018-05-26 21:55:02 UTC (rev 9987)
@@ -0,0 +1,374 @@
+/* $MidnightBSD$ */
+/* $OpenBSD: pio.h,v 1.2 1998/09/15 10:50:12 pefo Exp $ */
+
+/*-
+ * Copyright (c) 2002-2004 Juli Mallett. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ */
+/*
+ * Copyright (c) 1995-1999 Per Fogelstrom. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * 3. All advertising materials mentioning features or use of this software
+ * must display the following acknowledgement:
+ * This product includes software developed by Per Fogelstrom.
+ * 4. The name of the author may not be used to endorse or promote products
+ * derived from this software without specific prior written permission
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+ * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+ * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * JNPR: cpufunc.h,v 1.5 2007/08/09 11:23:32 katta
+ * $FreeBSD: stable/10/sys/mips/include/cpufunc.h 257528 2013-11-01 21:17:45Z brooks $
+ */
+
+#ifndef _MACHINE_CPUFUNC_H_
+#define _MACHINE_CPUFUNC_H_
+
+#include <sys/types.h>
+#include <machine/cpuregs.h>
+
+/*
+ * These functions are required by user-land atomi ops
+ */
+
+static __inline void
+mips_barrier(void)
+{
+#if defined(CPU_CNMIPS) || defined(CPU_RMI) || defined(CPU_NLM)
+ __compiler_membar();
+#else
+ __asm __volatile (".set noreorder\n\t"
+ "nop\n\t"
+ "nop\n\t"
+ "nop\n\t"
+ "nop\n\t"
+ "nop\n\t"
+ "nop\n\t"
+ "nop\n\t"
+ "nop\n\t"
+ ".set reorder\n\t"
+ : : : "memory");
+#endif
+}
+
+static __inline void
+mips_cp0_sync(void)
+{
+ __asm __volatile (__XSTRING(COP0_SYNC));
+}
+
+static __inline void
+mips_wbflush(void)
+{
+#if defined(CPU_CNMIPS)
+ __asm __volatile (".set noreorder\n\t"
+ "syncw\n\t"
+ ".set reorder\n"
+ : : : "memory");
+#else
+ __asm __volatile ("sync" : : : "memory");
+ mips_barrier();
+#endif
+}
+
+#ifdef _KERNEL
+/*
+ * XXX
+ * It would be nice to add variants that read/write register_t, to avoid some
+ * ABI checks.
+ */
+#if defined(__mips_n32) || defined(__mips_n64)
+#define MIPS_RW64_COP0(n,r) \
+static __inline uint64_t \
+mips_rd_ ## n (void) \
+{ \
+ int v0; \
+ __asm __volatile ("dmfc0 %[v0], $"__XSTRING(r)";" \
+ : [v0] "=&r"(v0)); \
+ mips_barrier(); \
+ return (v0); \
+} \
+static __inline void \
+mips_wr_ ## n (uint64_t a0) \
+{ \
+ __asm __volatile ("dmtc0 %[a0], $"__XSTRING(r)";" \
+ __XSTRING(COP0_SYNC)";" \
+ "nop;" \
+ "nop;" \
+ : \
+ : [a0] "r"(a0)); \
+ mips_barrier(); \
+} struct __hack
+
+#define MIPS_RW64_COP0_SEL(n,r,s) \
+static __inline uint64_t \
+mips_rd_ ## n(void) \
+{ \
+ int v0; \
+ __asm __volatile ("dmfc0 %[v0], $"__XSTRING(r)", "__XSTRING(s)";" \
+ : [v0] "=&r"(v0)); \
+ mips_barrier(); \
+ return (v0); \
+} \
+static __inline void \
+mips_wr_ ## n(uint64_t a0) \
+{ \
+ __asm __volatile ("dmtc0 %[a0], $"__XSTRING(r)", "__XSTRING(s)";" \
+ __XSTRING(COP0_SYNC)";" \
+ : \
+ : [a0] "r"(a0)); \
+ mips_barrier(); \
+} struct __hack
+
+#if defined(__mips_n64)
+MIPS_RW64_COP0(excpc, MIPS_COP_0_EXC_PC);
+MIPS_RW64_COP0(entryhi, MIPS_COP_0_TLB_HI);
+MIPS_RW64_COP0(pagemask, MIPS_COP_0_TLB_PG_MASK);
+#ifdef CPU_CNMIPS
+MIPS_RW64_COP0_SEL(cvmcount, MIPS_COP_0_COUNT, 6);
+MIPS_RW64_COP0_SEL(cvmctl, MIPS_COP_0_COUNT, 7);
+MIPS_RW64_COP0_SEL(cvmmemctl, MIPS_COP_0_COMPARE, 7);
+MIPS_RW64_COP0_SEL(icache_err, MIPS_COP_0_CACHE_ERR, 0);
+MIPS_RW64_COP0_SEL(dcache_err, MIPS_COP_0_CACHE_ERR, 1);
+#endif
+#endif
+#if defined(__mips_n64) || defined(__mips_n32) /* PHYSADDR_64_BIT */
+MIPS_RW64_COP0(entrylo0, MIPS_COP_0_TLB_LO0);
+MIPS_RW64_COP0(entrylo1, MIPS_COP_0_TLB_LO1);
+#endif
+MIPS_RW64_COP0(xcontext, MIPS_COP_0_TLB_XCONTEXT);
+
+#undef MIPS_RW64_COP0
+#undef MIPS_RW64_COP0_SEL
+#endif
+
+#define MIPS_RW32_COP0(n,r) \
+static __inline uint32_t \
+mips_rd_ ## n (void) \
+{ \
+ int v0; \
+ __asm __volatile ("mfc0 %[v0], $"__XSTRING(r)";" \
+ : [v0] "=&r"(v0)); \
+ mips_barrier(); \
+ return (v0); \
+} \
+static __inline void \
+mips_wr_ ## n (uint32_t a0) \
+{ \
+ __asm __volatile ("mtc0 %[a0], $"__XSTRING(r)";" \
+ __XSTRING(COP0_SYNC)";" \
+ "nop;" \
+ "nop;" \
+ : \
+ : [a0] "r"(a0)); \
+ mips_barrier(); \
+} struct __hack
+
+#define MIPS_RW32_COP0_SEL(n,r,s) \
+static __inline uint32_t \
+mips_rd_ ## n(void) \
+{ \
+ int v0; \
+ __asm __volatile ("mfc0 %[v0], $"__XSTRING(r)", "__XSTRING(s)";" \
+ : [v0] "=&r"(v0)); \
+ mips_barrier(); \
+ return (v0); \
+} \
+static __inline void \
+mips_wr_ ## n(uint32_t a0) \
+{ \
+ __asm __volatile ("mtc0 %[a0], $"__XSTRING(r)", "__XSTRING(s)";" \
+ __XSTRING(COP0_SYNC)";" \
+ "nop;" \
+ "nop;" \
+ : \
+ : [a0] "r"(a0)); \
+ mips_barrier(); \
+} struct __hack
+
+#ifdef CPU_CNMIPS
+static __inline void mips_sync_icache (void)
+{
+ __asm __volatile (
+ ".set push\n"
+ ".set mips64\n"
+ ".word 0x041f0000\n" /* xxx ICACHE */
+ "nop\n"
+ ".set pop\n"
+ : : );
+}
+#endif
+
+MIPS_RW32_COP0(compare, MIPS_COP_0_COMPARE);
+MIPS_RW32_COP0(config, MIPS_COP_0_CONFIG);
+MIPS_RW32_COP0_SEL(config1, MIPS_COP_0_CONFIG, 1);
+MIPS_RW32_COP0_SEL(config2, MIPS_COP_0_CONFIG, 2);
+MIPS_RW32_COP0_SEL(config3, MIPS_COP_0_CONFIG, 3);
+#ifdef CPU_CNMIPS
+MIPS_RW32_COP0_SEL(config4, MIPS_COP_0_CONFIG, 4);
+#endif
+#ifdef BERI_LARGE_TLB
+MIPS_RW32_COP0_SEL(config5, MIPS_COP_0_CONFIG, 5);
+#endif
+#if defined(CPU_NLM) || defined(BERI_LARGE_TLB)
+MIPS_RW32_COP0_SEL(config6, MIPS_COP_0_CONFIG, 6);
+#endif
+#ifdef CPU_NLM
+MIPS_RW32_COP0_SEL(config7, MIPS_COP_0_CONFIG, 7);
+#endif
+MIPS_RW32_COP0(count, MIPS_COP_0_COUNT);
+MIPS_RW32_COP0(index, MIPS_COP_0_TLB_INDEX);
+MIPS_RW32_COP0(wired, MIPS_COP_0_TLB_WIRED);
+MIPS_RW32_COP0(cause, MIPS_COP_0_CAUSE);
+#if !defined(__mips_n64)
+MIPS_RW32_COP0(excpc, MIPS_COP_0_EXC_PC);
+#endif
+MIPS_RW32_COP0(status, MIPS_COP_0_STATUS);
+
+/* XXX: Some of these registers are specific to MIPS32. */
+#if !defined(__mips_n64)
+MIPS_RW32_COP0(entryhi, MIPS_COP_0_TLB_HI);
+MIPS_RW32_COP0(pagemask, MIPS_COP_0_TLB_PG_MASK);
+#endif
+#ifdef CPU_NLM
+MIPS_RW32_COP0_SEL(pagegrain, MIPS_COP_0_TLB_PG_MASK, 1);
+#endif
+#if !defined(__mips_n64) && !defined(__mips_n32) /* !PHYSADDR_64_BIT */
+MIPS_RW32_COP0(entrylo0, MIPS_COP_0_TLB_LO0);
+MIPS_RW32_COP0(entrylo1, MIPS_COP_0_TLB_LO1);
+#endif
+MIPS_RW32_COP0(prid, MIPS_COP_0_PRID);
+/* XXX 64-bit? */
+MIPS_RW32_COP0_SEL(ebase, MIPS_COP_0_PRID, 1);
+MIPS_RW32_COP0(watchlo, MIPS_COP_0_WATCH_LO);
+MIPS_RW32_COP0_SEL(watchlo1, MIPS_COP_0_WATCH_LO, 1);
+MIPS_RW32_COP0_SEL(watchlo2, MIPS_COP_0_WATCH_LO, 2);
+MIPS_RW32_COP0_SEL(watchlo3, MIPS_COP_0_WATCH_LO, 3);
+MIPS_RW32_COP0(watchhi, MIPS_COP_0_WATCH_HI);
+MIPS_RW32_COP0_SEL(watchhi1, MIPS_COP_0_WATCH_HI, 1);
+MIPS_RW32_COP0_SEL(watchhi2, MIPS_COP_0_WATCH_HI, 2);
+MIPS_RW32_COP0_SEL(watchhi3, MIPS_COP_0_WATCH_HI, 3);
+
+MIPS_RW32_COP0_SEL(perfcnt0, MIPS_COP_0_PERFCNT, 0);
+MIPS_RW32_COP0_SEL(perfcnt1, MIPS_COP_0_PERFCNT, 1);
+MIPS_RW32_COP0_SEL(perfcnt2, MIPS_COP_0_PERFCNT, 2);
+MIPS_RW32_COP0_SEL(perfcnt3, MIPS_COP_0_PERFCNT, 3);
+
+#undef MIPS_RW32_COP0
+#undef MIPS_RW32_COP0_SEL
+
+static __inline register_t
+intr_disable(void)
+{
+ register_t s;
+
+ s = mips_rd_status();
+ mips_wr_status(s & ~MIPS_SR_INT_IE);
+
+ return (s & MIPS_SR_INT_IE);
+}
+
+static __inline register_t
+intr_enable(void)
+{
+ register_t s;
+
+ s = mips_rd_status();
+ mips_wr_status(s | MIPS_SR_INT_IE);
+
+ return (s);
+}
+
+static __inline void
+intr_restore(register_t ie)
+{
+ if (ie == MIPS_SR_INT_IE) {
+ intr_enable();
+ }
+}
+
+static __inline uint32_t
+set_intr_mask(uint32_t mask)
+{
+ uint32_t ostatus;
+
+ ostatus = mips_rd_status();
+ mask = (ostatus & ~MIPS_SR_INT_MASK) | (mask & MIPS_SR_INT_MASK);
+ mips_wr_status(mask);
+ return (ostatus);
+}
+
+static __inline uint32_t
+get_intr_mask(void)
+{
+
+ return (mips_rd_status() & MIPS_SR_INT_MASK);
+}
+
+static __inline void
+breakpoint(void)
+{
+ __asm __volatile ("break");
+}
+
+#if defined(__GNUC__) && !defined(__mips_o32)
+#define mips3_ld(a) (*(const volatile uint64_t *)(a))
+#define mips3_sd(a, v) (*(volatile uint64_t *)(a) = (v))
+#else
+uint64_t mips3_ld(volatile uint64_t *va);
+void mips3_sd(volatile uint64_t *, uint64_t);
+#endif /* __GNUC__ */
+
+#endif /* _KERNEL */
+
+#define readb(va) (*(volatile uint8_t *) (va))
+#define readw(va) (*(volatile uint16_t *) (va))
+#define readl(va) (*(volatile uint32_t *) (va))
+#if defined(__GNUC__) && !defined(__mips_o32)
+#define readq(a) (*(volatile uint64_t *)(a))
+#endif
+
+#define writeb(va, d) (*(volatile uint8_t *) (va) = (d))
+#define writew(va, d) (*(volatile uint16_t *) (va) = (d))
+#define writel(va, d) (*(volatile uint32_t *) (va) = (d))
+#if defined(__GNUC__) && !defined(__mips_o32)
+#define writeq(va, d) (*(volatile uint64_t *) (va) = (d))
+#endif
+
+#endif /* !_MACHINE_CPUFUNC_H_ */
Property changes on: trunk/sys/mips/include/cpufunc.h
___________________________________________________________________
Added: svn:eol-style
## -0,0 +1 ##
+native
\ No newline at end of property
Added: svn:keywords
## -0,0 +1 ##
+MidnightBSD=%H
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+text/plain
\ No newline at end of property
Added: trunk/sys/mips/include/cpuinfo.h
===================================================================
--- trunk/sys/mips/include/cpuinfo.h (rev 0)
+++ trunk/sys/mips/include/cpuinfo.h 2018-05-26 21:55:02 UTC (rev 9987)
@@ -0,0 +1,77 @@
+/* $MidnightBSD$ */
+/* $NetBSD: cpu.h,v 1.70 2003/01/17 23:36:08 thorpej Exp $ */
+
+/*-
+ * Copyright (c) 1992, 1993
+ * The Regents of the University of California. All rights reserved.
+ *
+ * This code is derived from software contributed to Berkeley by
+ * Ralph Campbell and Rick Macklem.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * 3. All advertising materials mentioning features or use of this software
+ * must display the following acknowledgement:
+ * This product includes software developed by the University of
+ * California, Berkeley and its contributors.
+ * 4. Neither the name of the University nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ * $FreeBSD: stable/10/sys/mips/include/cpuinfo.h 204690 2010-03-04 05:37:19Z neel $
+ * @(#)cpu.h 8.4 (Berkeley) 1/4/94
+ */
+
+#ifndef _CPUINFO_H_
+#define _CPUINFO_H_
+
+/*
+ * Exported definitions unique to NetBSD/mips cpu support.
+ */
+
+#ifdef _KERNEL
+#ifndef LOCORE
+
+struct mips_cpuinfo {
+ u_int8_t cpu_vendor;
+ u_int8_t cpu_rev;
+ u_int8_t cpu_impl;
+ u_int8_t tlb_type;
+ u_int16_t tlb_nentries;
+ u_int8_t icache_virtual;
+ boolean_t cache_coherent_dma;
+ struct {
+ u_int32_t ic_size;
+ u_int8_t ic_linesize;
+ u_int8_t ic_nways;
+ u_int16_t ic_nsets;
+ u_int32_t dc_size;
+ u_int8_t dc_linesize;
+ u_int8_t dc_nways;
+ u_int16_t dc_nsets;
+ } l1;
+};
+
+extern struct mips_cpuinfo cpuinfo;
+
+#endif /* !LOCORE */
+#endif /* _KERNEL */
+#endif /* _CPUINFO_H_ */
Property changes on: trunk/sys/mips/include/cpuinfo.h
___________________________________________________________________
Added: svn:eol-style
## -0,0 +1 ##
+native
\ No newline at end of property
Added: svn:keywords
## -0,0 +1 ##
+MidnightBSD=%H
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+text/plain
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Added: trunk/sys/mips/include/cpuregs.h
===================================================================
--- trunk/sys/mips/include/cpuregs.h (rev 0)
+++ trunk/sys/mips/include/cpuregs.h 2018-05-26 21:55:02 UTC (rev 9987)
@@ -0,0 +1,631 @@
+/* $MidnightBSD$ */
+/* $NetBSD: cpuregs.h,v 1.70 2006/05/15 02:26:54 simonb Exp $ */
+
+/*
+ * Copyright (c) 1992, 1993
+ * The Regents of the University of California. All rights reserved.
+ *
+ * This code is derived from software contributed to Berkeley by
+ * Ralph Campbell and Rick Macklem.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * 3. Neither the name of the University nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ * @(#)machConst.h 8.1 (Berkeley) 6/10/93
+ *
+ * machConst.h --
+ *
+ * Machine dependent constants.
+ *
+ * Copyright (C) 1989 Digital Equipment Corporation.
+ * Permission to use, copy, modify, and distribute this software and
+ * its documentation for any purpose and without fee is hereby granted,
+ * provided that the above copyright notice appears in all copies.
+ * Digital Equipment Corporation makes no representations about the
+ * suitability of this software for any purpose. It is provided "as is"
+ * without express or implied warranty.
+ *
+ * from: Header: /sprite/src/kernel/mach/ds3100.md/RCS/machConst.h,
+ * v 9.2 89/10/21 15:55:22 jhh Exp SPRITE (DECWRL)
+ * from: Header: /sprite/src/kernel/mach/ds3100.md/RCS/machAddrs.h,
+ * v 1.2 89/08/15 18:28:21 rab Exp SPRITE (DECWRL)
+ * from: Header: /sprite/src/kernel/vm/ds3100.md/RCS/vmPmaxConst.h,
+ * v 9.1 89/09/18 17:33:00 shirriff Exp SPRITE (DECWRL)
+ *
+ * $FreeBSD: stable/10/sys/mips/include/cpuregs.h 256172 2013-10-09 00:27:12Z adrian $
+ */
+
+#ifndef _MIPS_CPUREGS_H_
+#define _MIPS_CPUREGS_H_
+
+/*
+ * Address space.
+ * 32-bit mips CPUS partition their 32-bit address space into four segments:
+ *
+ * kuseg 0x00000000 - 0x7fffffff User virtual mem, mapped
+ * kseg0 0x80000000 - 0x9fffffff Physical memory, cached, unmapped
+ * kseg1 0xa0000000 - 0xbfffffff Physical memory, uncached, unmapped
+ * kseg2 0xc0000000 - 0xffffffff kernel-virtual, mapped
+ *
+ * Caching of mapped addresses is controlled by bits in the TLB entry.
+ */
+
+#define MIPS_KSEG0_LARGEST_PHYS (0x20000000)
+#define MIPS_KSEG0_PHYS_MASK (0x1fffffff)
+#define MIPS_XKPHYS_LARGEST_PHYS (0x10000000000) /* 40 bit PA */
+#define MIPS_XKPHYS_PHYS_MASK (0x0ffffffffff)
+
+#ifndef LOCORE
+#define MIPS_KUSEG_START 0x00000000
+#define MIPS_KSEG0_START ((intptr_t)(int32_t)0x80000000)
+#define MIPS_KSEG0_END ((intptr_t)(int32_t)0x9fffffff)
+#define MIPS_KSEG1_START ((intptr_t)(int32_t)0xa0000000)
+#define MIPS_KSEG1_END ((intptr_t)(int32_t)0xbfffffff)
+#define MIPS_KSSEG_START ((intptr_t)(int32_t)0xc0000000)
+#define MIPS_KSSEG_END ((intptr_t)(int32_t)0xdfffffff)
+#define MIPS_KSEG3_START ((intptr_t)(int32_t)0xe0000000)
+#define MIPS_KSEG3_END ((intptr_t)(int32_t)0xffffffff)
+#define MIPS_KSEG2_START MIPS_KSSEG_START
+#define MIPS_KSEG2_END MIPS_KSSEG_END
+#endif
+
+#define MIPS_PHYS_TO_KSEG0(x) ((uintptr_t)(x) | MIPS_KSEG0_START)
+#define MIPS_PHYS_TO_KSEG1(x) ((uintptr_t)(x) | MIPS_KSEG1_START)
+#define MIPS_KSEG0_TO_PHYS(x) ((uintptr_t)(x) & MIPS_KSEG0_PHYS_MASK)
+#define MIPS_KSEG1_TO_PHYS(x) ((uintptr_t)(x) & MIPS_KSEG0_PHYS_MASK)
+
+#define MIPS_IS_KSEG0_ADDR(x) \
+ (((vm_offset_t)(x) >= MIPS_KSEG0_START) && \
+ ((vm_offset_t)(x) <= MIPS_KSEG0_END))
+#define MIPS_IS_KSEG1_ADDR(x) \
+ (((vm_offset_t)(x) >= MIPS_KSEG1_START) && \
+ ((vm_offset_t)(x) <= MIPS_KSEG1_END))
+#define MIPS_IS_VALID_PTR(x) (MIPS_IS_KSEG0_ADDR(x) || \
+ MIPS_IS_KSEG1_ADDR(x))
+
+/*
+ * Cache Coherency Attributes:
+ * UC: Uncached.
+ * UA: Uncached accelerated.
+ * C: Cacheable, coherency unspecified.
+ * CNC: Cacheable non-coherent.
+ * CC: Cacheable coherent.
+ * CCE: Cacheable coherent, exclusive read.
+ * CCEW: Cacheable coherent, exclusive write.
+ * CCUOW: Cacheable coherent, update on write.
+ *
+ * Note that some bits vary in meaning across implementations (and that the
+ * listing here is no doubt incomplete) and that the optimal cached mode varies
+ * between implementations. 0x02 is required to be UC and 0x03 is required to
+ * be a least C.
+ *
+ * We define the following logical bits:
+ * UNCACHED:
+ * The optimal uncached mode for the target CPU type. This must
+ * be suitable for use in accessing memory-mapped devices.
+ * CACHED: The optional cached mode for the target CPU type.
+ */
+
+#define MIPS_CCA_UC 0x02 /* Uncached. */
+#define MIPS_CCA_C 0x03 /* Cacheable, coherency unspecified. */
+
+#if defined(CPU_R4000) || defined(CPU_R10000)
+#define MIPS_CCA_CNC 0x03
+#define MIPS_CCA_CCE 0x04
+#define MIPS_CCA_CCEW 0x05
+
+#ifdef CPU_R4000
+#define MIPS_CCA_CCUOW 0x06
+#endif
+
+#ifdef CPU_R10000
+#define MIPS_CCA_UA 0x07
+#endif
+
+#define MIPS_CCA_CACHED MIPS_CCA_CCEW
+#endif /* defined(CPU_R4000) || defined(CPU_R10000) */
+
+#if defined(CPU_SB1)
+#define MIPS_CCA_CC 0x05 /* Cacheable Coherent. */
+#endif
+
+#if defined(CPU_MIPS74KC)
+#define MIPS_CCA_UNCACHED 0x02
+#define MIPS_CCA_CACHED 0x00
+#endif
+
+#ifndef MIPS_CCA_UNCACHED
+#define MIPS_CCA_UNCACHED MIPS_CCA_UC
+#endif
+
+/*
+ * If we don't know which cached mode to use and there is a cache coherent
+ * mode, use it. If there is not a cache coherent mode, use the required
+ * cacheable mode.
+ */
+#ifndef MIPS_CCA_CACHED
+#ifdef MIPS_CCA_CC
+#define MIPS_CCA_CACHED MIPS_CCA_CC
+#else
+#define MIPS_CCA_CACHED MIPS_CCA_C
+#endif
+#endif
+
+#define MIPS_PHYS_TO_XKPHYS(cca,x) \
+ ((0x2ULL << 62) | ((unsigned long long)(cca) << 59) | (x))
+#define MIPS_PHYS_TO_XKPHYS_CACHED(x) \
+ ((0x2ULL << 62) | ((unsigned long long)(MIPS_CCA_CACHED) << 59) | (x))
+#define MIPS_PHYS_TO_XKPHYS_UNCACHED(x) \
+ ((0x2ULL << 62) | ((unsigned long long)(MIPS_CCA_UNCACHED) << 59) | (x))
+
+#define MIPS_XKPHYS_TO_PHYS(x) ((uintptr_t)(x) & MIPS_XKPHYS_PHYS_MASK)
+
+#define MIPS_XKPHYS_START 0x8000000000000000
+#define MIPS_XKPHYS_END 0xbfffffffffffffff
+#define MIPS_XUSEG_START 0x0000000000000000
+#define MIPS_XUSEG_END 0x0000010000000000
+#define MIPS_XKSEG_START 0xc000000000000000
+#define MIPS_XKSEG_END 0xc00000ff80000000
+#define MIPS_XKSEG_COMPAT32_START 0xffffffff80000000
+#define MIPS_XKSEG_COMPAT32_END 0xffffffffffffffff
+#define MIPS_XKSEG_TO_COMPAT32(va) ((va) & 0xffffffff)
+
+#ifdef __mips_n64
+#define MIPS_DIRECT_MAPPABLE(pa) 1
+#define MIPS_PHYS_TO_DIRECT(pa) MIPS_PHYS_TO_XKPHYS_CACHED(pa)
+#define MIPS_PHYS_TO_DIRECT_UNCACHED(pa) MIPS_PHYS_TO_XKPHYS_UNCACHED(pa)
+#define MIPS_DIRECT_TO_PHYS(va) MIPS_XKPHYS_TO_PHYS(va)
+#else
+#define MIPS_DIRECT_MAPPABLE(pa) ((pa) < MIPS_KSEG0_LARGEST_PHYS)
+#define MIPS_PHYS_TO_DIRECT(pa) MIPS_PHYS_TO_KSEG0(pa)
+#define MIPS_PHYS_TO_DIRECT_UNCACHED(pa) MIPS_PHYS_TO_KSEG1(pa)
+#define MIPS_DIRECT_TO_PHYS(va) MIPS_KSEG0_TO_PHYS(va)
+#endif
+
+/* CPU dependent mtc0 hazard hook */
+#if defined(CPU_CNMIPS) || defined(CPU_RMI)
+#define COP0_SYNC
+#elif defined(CPU_NLM)
+#define COP0_SYNC .word 0xc0 /* ehb */
+#elif defined(CPU_SB1)
+#define COP0_SYNC ssnop; ssnop; ssnop; ssnop; ssnop; ssnop; ssnop; ssnop; ssnop
+#elif defined(CPU_MIPS74KC)
+#define COP0_SYNC .word 0xc0 /* ehb */
+#else
+/*
+ * Pick a reasonable default based on the "typical" spacing described in the
+ * "CP0 Hazards" chapter of MIPS Architecture Book Vol III.
+ */
+#define COP0_SYNC ssnop; ssnop; ssnop; ssnop; .word 0xc0;
+#endif
+#define COP0_HAZARD_FPUENABLE nop; nop; nop; nop;
+
+/*
+ * The bits in the cause register.
+ *
+ * Bits common to r3000 and r4000:
+ *
+ * MIPS_CR_BR_DELAY Exception happened in branch delay slot.
+ * MIPS_CR_COP_ERR Coprocessor error.
+ * MIPS_CR_IP Interrupt pending bits defined below.
+ * (same meaning as in CAUSE register).
+ * MIPS_CR_EXC_CODE The exception type (see exception codes below).
+ *
+ * Differences:
+ * r3k has 4 bits of execption type, r4k has 5 bits.
+ */
+#define MIPS_CR_BR_DELAY 0x80000000
+#define MIPS_CR_COP_ERR 0x30000000
+#define MIPS_CR_EXC_CODE 0x0000007C /* five bits */
+#define MIPS_CR_IP 0x0000FF00
+#define MIPS_CR_EXC_CODE_SHIFT 2
+#define MIPS_CR_COP_ERR_SHIFT 28
+
+/*
+ * The bits in the status register. All bits are active when set to 1.
+ *
+ * R3000 status register fields:
+ * MIPS_SR_COP_USABILITY Control the usability of the four coprocessors.
+ * MIPS_SR_TS TLB shutdown.
+ *
+ * MIPS_SR_INT_IE Master (current) interrupt enable bit.
+ *
+ * Differences:
+ * r3k has cache control is via frobbing SR register bits, whereas the
+ * r4k cache control is via explicit instructions.
+ * r3k has a 3-entry stack of kernel/user bits, whereas the
+ * r4k has kernel/supervisor/user.
+ */
+#define MIPS_SR_COP_USABILITY 0xf0000000
+#define MIPS_SR_COP_0_BIT 0x10000000
+#define MIPS_SR_COP_1_BIT 0x20000000
+#define MIPS_SR_COP_2_BIT 0x40000000
+
+ /* r4k and r3k differences, see below */
+
+#define MIPS_SR_MX 0x01000000 /* MIPS64 */
+#define MIPS_SR_PX 0x00800000 /* MIPS64 */
+#define MIPS_SR_BEV 0x00400000 /* Use boot exception vector */
+#define MIPS_SR_TS 0x00200000
+#define MIPS_SR_DE 0x00010000
+
+#define MIPS_SR_INT_IE 0x00000001
+/*#define MIPS_SR_MBZ 0x0f8000c0*/ /* Never used, true for r3k */
+#define MIPS_SR_INT_MASK 0x0000ff00
+
+/*
+ * R4000 status register bit definitons,
+ * where different from r2000/r3000.
+ */
+#define MIPS_SR_XX 0x80000000
+#define MIPS_SR_RP 0x08000000
+#define MIPS_SR_FR 0x04000000
+#define MIPS_SR_RE 0x02000000
+
+#define MIPS_SR_DIAG_DL 0x01000000 /* QED 52xx */
+#define MIPS_SR_DIAG_IL 0x00800000 /* QED 52xx */
+#define MIPS_SR_SR 0x00100000
+#define MIPS_SR_NMI 0x00080000 /* MIPS32/64 */
+#define MIPS_SR_DIAG_CH 0x00040000
+#define MIPS_SR_DIAG_CE 0x00020000
+#define MIPS_SR_DIAG_PE 0x00010000
+#define MIPS_SR_EIE 0x00010000 /* TX79/R5900 */
+#define MIPS_SR_KX 0x00000080
+#define MIPS_SR_SX 0x00000040
+#define MIPS_SR_UX 0x00000020
+#define MIPS_SR_KSU_MASK 0x00000018
+#define MIPS_SR_KSU_USER 0x00000010
+#define MIPS_SR_KSU_SUPER 0x00000008
+#define MIPS_SR_KSU_KERNEL 0x00000000
+#define MIPS_SR_ERL 0x00000004
+#define MIPS_SR_EXL 0x00000002
+
+/*
+ * The interrupt masks.
+ * If a bit in the mask is 1 then the interrupt is enabled (or pending).
+ */
+#define MIPS_INT_MASK 0xff00
+#define MIPS_INT_MASK_5 0x8000
+#define MIPS_INT_MASK_4 0x4000
+#define MIPS_INT_MASK_3 0x2000
+#define MIPS_INT_MASK_2 0x1000
+#define MIPS_INT_MASK_1 0x0800
+#define MIPS_INT_MASK_0 0x0400
+#define MIPS_HARD_INT_MASK 0xfc00
+#define MIPS_SOFT_INT_MASK_1 0x0200
+#define MIPS_SOFT_INT_MASK_0 0x0100
+
+/*
+ * The bits in the MIPS3 config register.
+ *
+ * bit 0..5: R/W, Bit 6..31: R/O
+ */
+
+/* kseg0 coherency algorithm - see MIPS3_TLB_ATTR values */
+#define MIPS_CONFIG_K0_MASK 0x00000007
+
+/*
+ * R/W Update on Store Conditional
+ * 0: Store Conditional uses coherency algorithm specified by TLB
+ * 1: Store Conditional uses cacheable coherent update on write
+ */
+#define MIPS_CONFIG_CU 0x00000008
+
+#define MIPS_CONFIG_DB 0x00000010 /* Primary D-cache line size */
+#define MIPS_CONFIG_IB 0x00000020 /* Primary I-cache line size */
+#define MIPS_CONFIG_CACHE_L1_LSIZE(config, bit) \
+ (((config) & (bit)) ? 32 : 16)
+
+#define MIPS_CONFIG_DC_MASK 0x000001c0 /* Primary D-cache size */
+#define MIPS_CONFIG_DC_SHIFT 6
+#define MIPS_CONFIG_IC_MASK 0x00000e00 /* Primary I-cache size */
+#define MIPS_CONFIG_IC_SHIFT 9
+#define MIPS_CONFIG_C_DEFBASE 0x1000 /* default base 2^12 */
+
+/* Cache size mode indication: available only on Vr41xx CPUs */
+#define MIPS_CONFIG_CS 0x00001000
+#define MIPS_CONFIG_C_4100BASE 0x0400 /* base is 2^10 if CS=1 */
+#define MIPS_CONFIG_CACHE_SIZE(config, mask, base, shift) \
+ ((base) << (((config) & (mask)) >> (shift)))
+
+/* External cache enable: Controls L2 for R5000/Rm527x and L3 for Rm7000 */
+#define MIPS_CONFIG_SE 0x00001000
+
+/* Block ordering: 0: sequential, 1: sub-block */
+#define MIPS_CONFIG_EB 0x00002000
+
+/* ECC mode - 0: ECC mode, 1: parity mode */
+#define MIPS_CONFIG_EM 0x00004000
+
+/* BigEndianMem - 0: kernel and memory are little endian, 1: big endian */
+#define MIPS_CONFIG_BE 0x00008000
+
+/* Dirty Shared coherency state - 0: enabled, 1: disabled */
+#define MIPS_CONFIG_SM 0x00010000
+
+/* Secondary Cache - 0: present, 1: not present */
+#define MIPS_CONFIG_SC 0x00020000
+
+/* System Port width - 0: 64-bit, 1: 32-bit (QED RM523x), 2,3: reserved */
+#define MIPS_CONFIG_EW_MASK 0x000c0000
+#define MIPS_CONFIG_EW_SHIFT 18
+
+/* Secondary Cache port width - 0: 128-bit data path to S-cache, 1: reserved */
+#define MIPS_CONFIG_SW 0x00100000
+
+/* Split Secondary Cache Mode - 0: I/D mixed, 1: I/D separated by SCAddr(17) */
+#define MIPS_CONFIG_SS 0x00200000
+
+/* Secondary Cache line size */
+#define MIPS_CONFIG_SB_MASK 0x00c00000
+#define MIPS_CONFIG_SB_SHIFT 22
+#define MIPS_CONFIG_CACHE_L2_LSIZE(config) \
+ (0x10 << (((config) & MIPS_CONFIG_SB_MASK) >> MIPS_CONFIG_SB_SHIFT))
+
+/* Write back data rate */
+#define MIPS_CONFIG_EP_MASK 0x0f000000
+#define MIPS_CONFIG_EP_SHIFT 24
+
+/* System clock ratio - this value is CPU dependent */
+#define MIPS_CONFIG_EC_MASK 0x70000000
+#define MIPS_CONFIG_EC_SHIFT 28
+
+/* Master-Checker Mode - 1: enabled */
+#define MIPS_CONFIG_CM 0x80000000
+
+/*
+ * The bits in the MIPS4 config register.
+ */
+
+/*
+ * Location of exception vectors.
+ *
+ * Common vectors: reset and UTLB miss.
+ */
+#define MIPS_RESET_EXC_VEC ((intptr_t)(int32_t)0xBFC00000)
+#define MIPS_UTLB_MISS_EXC_VEC ((intptr_t)(int32_t)0x80000000)
+
+/*
+ * MIPS-III exception vectors
+ */
+#define MIPS_XTLB_MISS_EXC_VEC ((intptr_t)(int32_t)0x80000080)
+#define MIPS_CACHE_ERR_EXC_VEC ((intptr_t)(int32_t)0x80000100)
+#define MIPS_GEN_EXC_VEC ((intptr_t)(int32_t)0x80000180)
+
+/*
+ * MIPS32/MIPS64 (and some MIPS3) dedicated interrupt vector.
+ */
+#define MIPS_INTR_EXC_VEC 0x80000200
+
+/*
+ * Coprocessor 0 registers:
+ *
+ * v--- width for mips I,III,32,64
+ * (3=32bit, 6=64bit, i=impl dep)
+ * 0 MIPS_COP_0_TLB_INDEX 3333 TLB Index.
+ * 1 MIPS_COP_0_TLB_RANDOM 3333 TLB Random.
+ * 2 MIPS_COP_0_TLB_LO0 .636 r4k TLB entry low.
+ * 3 MIPS_COP_0_TLB_LO1 .636 r4k TLB entry low, extended.
+ * 4 MIPS_COP_0_TLB_CONTEXT 3636 TLB Context.
+ * 5 MIPS_COP_0_TLB_PG_MASK .333 TLB Page Mask register.
+ * 6 MIPS_COP_0_TLB_WIRED .333 Wired TLB number.
+ * 7 MIPS_COP_0_INFO ..33 Info registers
+ * 8 MIPS_COP_0_BAD_VADDR 3636 Bad virtual address.
+ * 9 MIPS_COP_0_COUNT .333 Count register.
+ * 10 MIPS_COP_0_TLB_HI 3636 TLB entry high.
+ * 11 MIPS_COP_0_COMPARE .333 Compare (against Count).
+ * 12 MIPS_COP_0_STATUS 3333 Status register.
+ * 13 MIPS_COP_0_CAUSE 3333 Exception cause register.
+ * 14 MIPS_COP_0_EXC_PC 3636 Exception PC.
+ * 15 MIPS_COP_0_PRID 3333 Processor revision identifier.
+ * 16 MIPS_COP_0_CONFIG 3333 Configuration register.
+ * 16/1 MIPS_COP_0_CONFIG1 ..33 Configuration register 1.
+ * 16/2 MIPS_COP_0_CONFIG2 ..33 Configuration register 2.
+ * 16/3 MIPS_COP_0_CONFIG3 ..33 Configuration register 3.
+ * 16/4 MIPS_COP_0_CONFIG4 ..33 Configuration register 4.
+ * 17 MIPS_COP_0_LLADDR .336 Load Linked Address.
+ * 18 MIPS_COP_0_WATCH_LO .336 WatchLo register.
+ * 19 MIPS_COP_0_WATCH_HI .333 WatchHi register.
+ * 20 MIPS_COP_0_TLB_XCONTEXT .6.6 TLB XContext register.
+ * 23 MIPS_COP_0_DEBUG .... Debug JTAG register.
+ * 24 MIPS_COP_0_DEPC .... DEPC JTAG register.
+ * 25 MIPS_COP_0_PERFCNT ..36 Performance Counter register.
+ * 26 MIPS_COP_0_ECC .3ii ECC / Error Control register.
+ * 27 MIPS_COP_0_CACHE_ERR .3ii Cache Error register.
+ * 28/0 MIPS_COP_0_TAG_LO .3ii Cache TagLo register (instr).
+ * 28/1 MIPS_COP_0_DATA_LO ..ii Cache DataLo register (instr).
+ * 28/2 MIPS_COP_0_TAG_LO ..ii Cache TagLo register (data).
+ * 28/3 MIPS_COP_0_DATA_LO ..ii Cache DataLo register (data).
+ * 29/0 MIPS_COP_0_TAG_HI .3ii Cache TagHi register (instr).
+ * 29/1 MIPS_COP_0_DATA_HI ..ii Cache DataHi register (instr).
+ * 29/2 MIPS_COP_0_TAG_HI ..ii Cache TagHi register (data).
+ * 29/3 MIPS_COP_0_DATA_HI ..ii Cache DataHi register (data).
+ * 30 MIPS_COP_0_ERROR_PC .636 Error EPC register.
+ * 31 MIPS_COP_0_DESAVE .... DESAVE JTAG register.
+ */
+
+/* Deal with inclusion from an assembly file. */
+#if defined(_LOCORE) || defined(LOCORE)
+#define _(n) $n
+#else
+#define _(n) n
+#endif
+
+
+#define MIPS_COP_0_TLB_INDEX _(0)
+#define MIPS_COP_0_TLB_RANDOM _(1)
+ /* Name and meaning of TLB bits for $2 differ on r3k and r4k. */
+
+#define MIPS_COP_0_TLB_CONTEXT _(4)
+ /* $5 and $6 new with MIPS-III */
+#define MIPS_COP_0_BAD_VADDR _(8)
+#define MIPS_COP_0_TLB_HI _(10)
+#define MIPS_COP_0_STATUS _(12)
+#define MIPS_COP_0_CAUSE _(13)
+#define MIPS_COP_0_EXC_PC _(14)
+#define MIPS_COP_0_PRID _(15)
+
+/* MIPS-III */
+#define MIPS_COP_0_TLB_LO0 _(2)
+#define MIPS_COP_0_TLB_LO1 _(3)
+
+#define MIPS_COP_0_TLB_PG_MASK _(5)
+#define MIPS_COP_0_TLB_WIRED _(6)
+
+#define MIPS_COP_0_COUNT _(9)
+#define MIPS_COP_0_COMPARE _(11)
+
+#define MIPS_COP_0_CONFIG _(16)
+#define MIPS_COP_0_LLADDR _(17)
+#define MIPS_COP_0_WATCH_LO _(18)
+#define MIPS_COP_0_WATCH_HI _(19)
+#define MIPS_COP_0_TLB_XCONTEXT _(20)
+#define MIPS_COP_0_ECC _(26)
+#define MIPS_COP_0_CACHE_ERR _(27)
+#define MIPS_COP_0_TAG_LO _(28)
+#define MIPS_COP_0_TAG_HI _(29)
+#define MIPS_COP_0_ERROR_PC _(30)
+
+/* MIPS32/64 */
+#define MIPS_COP_0_INFO _(7)
+#define MIPS_COP_0_DEBUG _(23)
+#define MIPS_COP_0_DEPC _(24)
+#define MIPS_COP_0_PERFCNT _(25)
+#define MIPS_COP_0_DATA_LO _(28)
+#define MIPS_COP_0_DATA_HI _(29)
+#define MIPS_COP_0_DESAVE _(31)
+
+/* MIPS32 Config register definitions */
+#define MIPS_MMU_NONE 0x00 /* No MMU present */
+#define MIPS_MMU_TLB 0x01 /* Standard TLB */
+#define MIPS_MMU_BAT 0x02 /* Standard BAT */
+#define MIPS_MMU_FIXED 0x03 /* Standard fixed mapping */
+
+#define MIPS_CONFIG0_MT_MASK 0x00000380 /* bits 9..7 MMU Type */
+#define MIPS_CONFIG0_MT_SHIFT 7
+#define MIPS_CONFIG0_BE 0x00008000 /* data is big-endian */
+#define MIPS_CONFIG0_VI 0x00000004 /* instruction cache is virtual */
+
+#define MIPS_CONFIG1_TLBSZ_MASK 0x7E000000 /* bits 30..25 # tlb entries minus one */
+#define MIPS_CONFIG1_TLBSZ_SHIFT 25
+
+#define MIPS_CONFIG1_IS_MASK 0x01C00000 /* bits 24..22 icache sets per way */
+#define MIPS_CONFIG1_IS_SHIFT 22
+#define MIPS_CONFIG1_IL_MASK 0x00380000 /* bits 21..19 icache line size */
+#define MIPS_CONFIG1_IL_SHIFT 19
+#define MIPS_CONFIG1_IA_MASK 0x00070000 /* bits 18..16 icache associativity */
+#define MIPS_CONFIG1_IA_SHIFT 16
+#define MIPS_CONFIG1_DS_MASK 0x0000E000 /* bits 15..13 dcache sets per way */
+#define MIPS_CONFIG1_DS_SHIFT 13
+#define MIPS_CONFIG1_DL_MASK 0x00001C00 /* bits 12..10 dcache line size */
+#define MIPS_CONFIG1_DL_SHIFT 10
+#define MIPS_CONFIG1_DA_MASK 0x00000380 /* bits 9.. 7 dcache associativity */
+#define MIPS_CONFIG1_DA_SHIFT 7
+#define MIPS_CONFIG1_LOWBITS 0x0000007F
+#define MIPS_CONFIG1_C2 0x00000040 /* Coprocessor 2 implemented */
+#define MIPS_CONFIG1_MD 0x00000020 /* MDMX ASE implemented (MIPS64) */
+#define MIPS_CONFIG1_PC 0x00000010 /* Performance counters implemented */
+#define MIPS_CONFIG1_WR 0x00000008 /* Watch registers implemented */
+#define MIPS_CONFIG1_CA 0x00000004 /* MIPS16e ISA implemented */
+#define MIPS_CONFIG1_EP 0x00000002 /* EJTAG implemented */
+#define MIPS_CONFIG1_FP 0x00000001 /* FPU implemented */
+
+#define MIPS_CONFIG4_MMUSIZEEXT 0x000000FF /* bits 7.. 0 MMU Size Extension */
+#define MIPS_CONFIG4_MMUEXTDEF 0x0000C000 /* bits 15.14 MMU Extension Definition */
+#define MIPS_CONFIG4_MMUEXTDEF_MMUSIZEEXT 0x00004000 /* This values denotes CONFIG4 bits */
+
+/*
+ * Values for the code field in a break instruction.
+ */
+#define MIPS_BREAK_INSTR 0x0000000d
+#define MIPS_BREAK_VAL_MASK 0x03ff0000
+#define MIPS_BREAK_VAL_SHIFT 16
+#define MIPS_BREAK_KDB_VAL 512
+#define MIPS_BREAK_SSTEP_VAL 513
+#define MIPS_BREAK_BRKPT_VAL 514
+#define MIPS_BREAK_SOVER_VAL 515
+#define MIPS_BREAK_DDB_VAL 516
+#define MIPS_BREAK_KDB (MIPS_BREAK_INSTR | \
+ (MIPS_BREAK_KDB_VAL << MIPS_BREAK_VAL_SHIFT))
+#define MIPS_BREAK_SSTEP (MIPS_BREAK_INSTR | \
+ (MIPS_BREAK_SSTEP_VAL << MIPS_BREAK_VAL_SHIFT))
+#define MIPS_BREAK_BRKPT (MIPS_BREAK_INSTR | \
+ (MIPS_BREAK_BRKPT_VAL << MIPS_BREAK_VAL_SHIFT))
+#define MIPS_BREAK_SOVER (MIPS_BREAK_INSTR | \
+ (MIPS_BREAK_SOVER_VAL << MIPS_BREAK_VAL_SHIFT))
+#define MIPS_BREAK_DDB (MIPS_BREAK_INSTR | \
+ (MIPS_BREAK_DDB_VAL << MIPS_BREAK_VAL_SHIFT))
+
+/*
+ * Mininum and maximum cache sizes.
+ */
+#define MIPS_MIN_CACHE_SIZE (16 * 1024)
+#define MIPS_MAX_CACHE_SIZE (256 * 1024)
+#define MIPS_MAX_PCACHE_SIZE (32 * 1024) /* max. primary cache size */
+
+/*
+ * The floating point version and status registers.
+ */
+#define MIPS_FPU_ID $0
+#define MIPS_FPU_CSR $31
+
+/*
+ * The floating point coprocessor status register bits.
+ */
+#define MIPS_FPU_ROUNDING_BITS 0x00000003
+#define MIPS_FPU_ROUND_RN 0x00000000
+#define MIPS_FPU_ROUND_RZ 0x00000001
+#define MIPS_FPU_ROUND_RP 0x00000002
+#define MIPS_FPU_ROUND_RM 0x00000003
+#define MIPS_FPU_STICKY_BITS 0x0000007c
+#define MIPS_FPU_STICKY_INEXACT 0x00000004
+#define MIPS_FPU_STICKY_UNDERFLOW 0x00000008
+#define MIPS_FPU_STICKY_OVERFLOW 0x00000010
+#define MIPS_FPU_STICKY_DIV0 0x00000020
+#define MIPS_FPU_STICKY_INVALID 0x00000040
+#define MIPS_FPU_ENABLE_BITS 0x00000f80
+#define MIPS_FPU_ENABLE_INEXACT 0x00000080
+#define MIPS_FPU_ENABLE_UNDERFLOW 0x00000100
+#define MIPS_FPU_ENABLE_OVERFLOW 0x00000200
+#define MIPS_FPU_ENABLE_DIV0 0x00000400
+#define MIPS_FPU_ENABLE_INVALID 0x00000800
+#define MIPS_FPU_EXCEPTION_BITS 0x0003f000
+#define MIPS_FPU_EXCEPTION_INEXACT 0x00001000
+#define MIPS_FPU_EXCEPTION_UNDERFLOW 0x00002000
+#define MIPS_FPU_EXCEPTION_OVERFLOW 0x00004000
+#define MIPS_FPU_EXCEPTION_DIV0 0x00008000
+#define MIPS_FPU_EXCEPTION_INVALID 0x00010000
+#define MIPS_FPU_EXCEPTION_UNIMPL 0x00020000
+#define MIPS_FPU_COND_BIT 0x00800000
+#define MIPS_FPU_FLUSH_BIT 0x01000000 /* r4k, MBZ on r3k */
+#define MIPS_FPC_MBZ_BITS 0xfe7c0000
+
+
+/*
+ * Constants to determine if have a floating point instruction.
+ */
+#define MIPS_OPCODE_SHIFT 26
+#define MIPS_OPCODE_C1 0x11
+
+#endif /* _MIPS_CPUREGS_H_ */
Property changes on: trunk/sys/mips/include/cpuregs.h
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Added: trunk/sys/mips/include/db_machdep.h
===================================================================
--- trunk/sys/mips/include/db_machdep.h (rev 0)
+++ trunk/sys/mips/include/db_machdep.h 2018-05-26 21:55:02 UTC (rev 9987)
@@ -0,0 +1,100 @@
+/* $MidnightBSD$ */
+/* $OpenBSD: db_machdep.h,v 1.2 1998/09/15 10:50:12 pefo Exp $ */
+
+/*
+ * Copyright (c) 1998 Per Fogelstrom, Opsycon AB
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * 3. All advertising materials mentioning features or use of this software
+ * must display the following acknowledgement:
+ * This product includes software developed under OpenBSD by
+ * Per Fogelstrom, Opsycon AB, Sweden.
+ * 4. The name of the author may not be used to endorse or promote products
+ * derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS
+ * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ * JNPR: db_machdep.h,v 1.7 2006/10/16 12:30:34 katta
+ * $FreeBSD: stable/10/sys/mips/include/db_machdep.h 230094 2012-01-13 23:31:36Z gonzo $
+ */
+
+#ifndef _MIPS_DB_MACHDEP_H_
+#define _MIPS_DB_MACHDEP_H_
+
+#include <machine/frame.h>
+#include <machine/trap.h>
+#include <machine/endian.h>
+
+typedef struct trapframe db_regs_t;
+extern db_regs_t ddb_regs; /* register state */
+
+typedef vm_offset_t db_addr_t; /* address - unsigned */
+typedef register_t db_expr_t; /* expression - signed */
+
+#if BYTE_ORDER == _BIG_ENDIAN
+#define BYTE_MSF (1)
+#endif
+
+#define SOFTWARE_SSTEP /* Need software single step */
+#define SOFTWARE_SSTEP_EMUL /* next_instr_address() emulates 100% */
+db_addr_t next_instr_address(db_addr_t, boolean_t);
+#define BKPT_SIZE (4)
+#define BKPT_SET(ins) (MIPS_BREAK_DDB)
+#define DB_VALID_BREAKPOINT(addr) (((addr) & 3) == 0)
+
+#define IS_BREAKPOINT_TRAP(type, code) ((type) == T_BREAK)
+#define IS_WATCHPOINT_TRAP(type, code) (0) /* XXX mips3 watchpoint */
+
+#define PC_REGS() ((db_addr_t)kdb_thrctx->pcb_regs.pc)
+#define BKPT_SKIP \
+ do { \
+ if((db_get_value(kdb_frame->pc, sizeof(int), FALSE) & \
+ ~MIPS_BREAK_VAL_MASK) == MIPS_BREAK_INSTR) { \
+ kdb_frame->pc += BKPT_SIZE; \
+ kdb_thrctx->pcb_regs.pc += BKPT_SIZE; \
+ } \
+ } while (0);
+
+
+/*
+ * Test of instructions to see class.
+ */
+#define IT_CALL 0x01
+#define IT_BRANCH 0x02
+#define IT_LOAD 0x03
+#define IT_STORE 0x04
+
+#define inst_branch(i) (db_inst_type(i) == IT_BRANCH)
+#define inst_trap_return(i) ((i) & 0)
+#define inst_call(i) (db_inst_type(i) == IT_CALL)
+#define inst_return(i) ((i) == 0x03e00008)
+#define inst_load(i) (db_inst_type(i) == IT_LOAD)
+#define inst_store(i) (db_inst_type(i) == IT_STORE)
+
+#define DB_SMALL_VALUE_MAX 0x7fffffff
+#define DB_SMALL_VALUE_MIN (-0x400001)
+
+int db_inst_type(int);
+db_addr_t branch_taken(int inst, db_addr_t pc);
+void stacktrace_subr(register_t pc, register_t sp, register_t ra, int (*)(const char *, ...));
+int32_t kdbpeek(int *);
+int64_t kdbpeekd(int *);
+
+#endif /* !_MIPS_DB_MACHDEP_H_ */
Property changes on: trunk/sys/mips/include/db_machdep.h
___________________________________________________________________
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Added: trunk/sys/mips/include/elf.h
===================================================================
--- trunk/sys/mips/include/elf.h (rev 0)
+++ trunk/sys/mips/include/elf.h 2018-05-26 21:55:02 UTC (rev 9987)
@@ -0,0 +1,262 @@
+/* $MidnightBSD$ */
+/*
+ * Copyright (c) 2013 M. Warner Losh. All Rights Reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ * $FreeBSD: stable/10/sys/mips/include/elf.h 294459 2016-01-20 21:06:24Z emaste $
+ */
+
+/*-
+ * Copyright (c) 2013 The NetBSD Foundation, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
+ * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * See below starting with the line with $NetBSD...$ for code this applies to.
+ */
+
+#ifndef __MIPS_ELF_H
+#define __MIPS_ELF_H
+
+/* FreeBSD specific bits - derived from FreeBSD specific files and changes to old elf.h */
+
+/*
+ * Define __ELF_WORD_SIZE based on the ABI, if not defined yet. This sets
+ * the proper defaults when we're not trying to do 32-bit on 64-bit systems.
+ * We include both 32 and 64 bit versions so we can support multiple ABIs.
+ */
+#ifndef __ELF_WORD_SIZE
+#if defined(__mips_n64)
+#define __ELF_WORD_SIZE 64
+#else
+#define __ELF_WORD_SIZE 32
+#endif
+#endif
+#include <sys/elf32.h>
+#include <sys/elf64.h>
+#include <sys/elf_generic.h>
+
+#define ELF_ARCH EM_MIPS
+#define ELF_ARCH32 EM_MIPS
+
+#define ELF_MACHINE_OK(x) ((x) == ELF_ARCH)
+
+/* Define "machine" characteristics */
+#if __ELF_WORD_SIZE == 32
+#define ELF_TARG_CLASS ELFCLASS32
+#else
+#define ELF_TARG_CLASS ELFCLASS64
+#endif
+#ifdef __MIPSEB__
+#define ELF_TARG_DATA ELFDATA2MSB
+#else
+#define ELF_TARG_DATA ELFDATA2LSB
+#endif
+#define ELF_TARG_MACH EM_MIPS
+#define ELF_TARG_VER 1
+
+/*
+ * Auxiliary vector entries for passing information to the interpreter.
+ *
+ * The i386 supplement to the SVR4 ABI specification names this "auxv_t",
+ * but POSIX lays claim to all symbols ending with "_t".
+ */
+typedef struct { /* Auxiliary vector entry on initial stack */
+ int a_type; /* Entry type. */
+ union {
+ int a_val; /* Integer value. */
+ void *a_ptr; /* Address. */
+ void (*a_fcn)(void); /* Function pointer (not used). */
+ } a_un;
+} Elf32_Auxinfo;
+
+typedef struct { /* Auxiliary vector entry on initial stack */
+ long a_type; /* Entry type. */
+ union {
+ long a_val; /* Integer value. */
+ void *a_ptr; /* Address. */
+ void (*a_fcn)(void); /* Function pointer (not used). */
+ } a_un;
+} Elf64_Auxinfo;
+
+__ElfType(Auxinfo);
+
+/* Values for a_type. */
+#define AT_NULL 0 /* Terminates the vector. */
+#define AT_IGNORE 1 /* Ignored entry. */
+#define AT_EXECFD 2 /* File descriptor of program to load. */
+#define AT_PHDR 3 /* Program header of program already loaded. */
+#define AT_PHENT 4 /* Size of each program header entry. */
+#define AT_PHNUM 5 /* Number of program header entries. */
+#define AT_PAGESZ 6 /* Page size in bytes. */
+#define AT_BASE 7 /* Interpreter's base address. */
+#define AT_FLAGS 8 /* Flags (unused for i386). */
+#define AT_ENTRY 9 /* Where interpreter should transfer control. */
+#define AT_NOTELF 10 /* Program is not ELF ?? */
+#define AT_UID 11 /* Real uid. */
+#define AT_EUID 12 /* Effective uid. */
+#define AT_GID 13 /* Real gid. */
+#define AT_EGID 14 /* Effective gid. */
+#define AT_EXECPATH 15 /* Path to the executable. */
+#define AT_CANARY 16 /* Canary for SSP */
+#define AT_CANARYLEN 17 /* Length of the canary. */
+#define AT_OSRELDATE 18 /* OSRELDATE. */
+#define AT_NCPUS 19 /* Number of CPUs. */
+#define AT_PAGESIZES 20 /* Pagesizes. */
+#define AT_PAGESIZESLEN 21 /* Number of pagesizes. */
+#define AT_TIMEKEEP 22 /* Pointer to timehands. */
+#define AT_STACKPROT 23 /* Initial stack protection. */
+
+#define AT_COUNT 24 /* Count of defined aux entry types. */
+
+#define ET_DYN_LOAD_ADDR 0x0120000
+
+/*
+ * Constant to mark start of symtab/strtab saved by trampoline
+ */
+#define SYMTAB_MAGIC 0x64656267
+
+/* from NetBSD's sys/mips/include/elf_machdep.h $NetBSD: elf_machdep.h,v 1.18 2013/05/23 21:39:49 christos Exp $ */
+
+/* mips relocs. */
+
+#define R_MIPS_NONE 0
+#define R_MIPS_16 1
+#define R_MIPS_32 2
+#define R_MIPS_REL32 3
+#define R_MIPS_REL R_MIPS_REL32
+#define R_MIPS_26 4
+#define R_MIPS_HI16 5 /* high 16 bits of symbol value */
+#define R_MIPS_LO16 6 /* low 16 bits of symbol value */
+#define R_MIPS_GPREL16 7 /* GP-relative reference */
+#define R_MIPS_LITERAL 8 /* Reference to literal section */
+#define R_MIPS_GOT16 9 /* Reference to global offset table */
+#define R_MIPS_GOT R_MIPS_GOT16
+#define R_MIPS_PC16 10 /* 16 bit PC relative reference */
+#define R_MIPS_CALL16 11 /* 16 bit call thru glbl offset tbl */
+#define R_MIPS_CALL R_MIPS_CALL16
+#define R_MIPS_GPREL32 12
+
+/* 13, 14, 15 are not defined at this point. */
+#define R_MIPS_UNUSED1 13
+#define R_MIPS_UNUSED2 14
+#define R_MIPS_UNUSED3 15
+
+/*
+ * The remaining relocs are apparently part of the 64-bit Irix ELF ABI.
+ */
+#define R_MIPS_SHIFT5 16
+#define R_MIPS_SHIFT6 17
+
+#define R_MIPS_64 18
+#define R_MIPS_GOT_DISP 19
+#define R_MIPS_GOT_PAGE 20
+#define R_MIPS_GOT_OFST 21
+#define R_MIPS_GOT_HI16 22
+#define R_MIPS_GOT_LO16 23
+#define R_MIPS_SUB 24
+#define R_MIPS_INSERT_A 25
+#define R_MIPS_INSERT_B 26
+#define R_MIPS_DELETE 27
+#define R_MIPS_HIGHER 28
+#define R_MIPS_HIGHEST 29
+#define R_MIPS_CALL_HI16 30
+#define R_MIPS_CALL_LO16 31
+#define R_MIPS_SCN_DISP 32
+#define R_MIPS_REL16 33
+#define R_MIPS_ADD_IMMEDIATE 34
+#define R_MIPS_PJUMP 35
+#define R_MIPS_RELGOT 36
+#define R_MIPS_JALR 37
+/* TLS relocations */
+
+#define R_MIPS_TLS_DTPMOD32 38 /* Module number 32 bit */
+#define R_MIPS_TLS_DTPREL32 39 /* Module-relative offset 32 bit */
+#define R_MIPS_TLS_DTPMOD64 40 /* Module number 64 bit */
+#define R_MIPS_TLS_DTPREL64 41 /* Module-relative offset 64 bit */
+#define R_MIPS_TLS_GD 42 /* 16 bit GOT offset for GD */
+#define R_MIPS_TLS_LDM 43 /* 16 bit GOT offset for LDM */
+#define R_MIPS_TLS_DTPREL_HI16 44 /* Module-relative offset, high 16 bits */
+#define R_MIPS_TLS_DTPREL_LO16 45 /* Module-relative offset, low 16 bits */
+#define R_MIPS_TLS_GOTTPREL 46 /* 16 bit GOT offset for IE */
+#define R_MIPS_TLS_TPREL32 47 /* TP-relative offset, 32 bit */
+#define R_MIPS_TLS_TPREL64 48 /* TP-relative offset, 64 bit */
+#define R_MIPS_TLS_TPREL_HI16 49 /* TP-relative offset, high 16 bits */
+#define R_MIPS_TLS_TPREL_LO16 50 /* TP-relative offset, low 16 bits */
+
+#define R_MIPS_max 51
+
+#define R_TYPE(name) __CONCAT(R_MIPS_,name)
+
+#define R_MIPS16_min 100
+#define R_MIPS16_26 100
+#define R_MIPS16_GPREL 101
+#define R_MIPS16_GOT16 102
+#define R_MIPS16_CALL16 103
+#define R_MIPS16_HI16 104
+#define R_MIPS16_LO16 105
+#define R_MIPS16_max 106
+
+#define R_MIPS_COPY 126
+#define R_MIPS_JUMP_SLOT 127
+
+/*
+ * ELF Flags
+ */
+
+#define EF_MIPS_ARCH_1 0x00000000 /* -mips1 code */
+#define EF_MIPS_ARCH_2 0x10000000 /* -mips2 code */
+#define EF_MIPS_ARCH_3 0x20000000 /* -mips3 code */
+#define EF_MIPS_ARCH_4 0x30000000 /* -mips4 code */
+#define EF_MIPS_ARCH_5 0x40000000 /* -mips5 code */
+#define EF_MIPS_ARCH_32 0x50000000 /* -mips32 code */
+#define EF_MIPS_ARCH_64 0x60000000 /* -mips64 code */
+#define EF_MIPS_ARCH_32R2 0x70000000 /* -mips32r2 code */
+#define EF_MIPS_ARCH_64R2 0x80000000 /* -mips64r2 code */
+
+#define EF_MIPS_ABI 0x0000f000
+#define EF_MIPS_ABI_O32 0x00001000
+#define EF_MIPS_ABI_O64 0x00002000
+#define EF_MIPS_ABI_EABI32 0x00003000
+#define EF_MIPS_ABI_EABI64 0x00004000
+
+#endif /* __MIPS_ELF_H */
Property changes on: trunk/sys/mips/include/elf.h
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\ No newline at end of property
Added: trunk/sys/mips/include/endian.h
===================================================================
--- trunk/sys/mips/include/endian.h (rev 0)
+++ trunk/sys/mips/include/endian.h 2018-05-26 21:55:02 UTC (rev 9987)
@@ -0,0 +1,147 @@
+/* $MidnightBSD$ */
+/*-
+ * Copyright (c) 1987, 1991 Regents of the University of California.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * 4. Neither the name of the University nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ * @(#)endian.h 7.8 (Berkeley) 4/3/91
+ * $FreeBSD: stable/10/sys/mips/include/endian.h 211159 2010-08-11 02:28:39Z neel $
+ */
+
+#ifndef _MACHINE_ENDIAN_H_
+#define _MACHINE_ENDIAN_H_
+
+#include <sys/cdefs.h>
+#ifndef __ASSEMBLER__
+#include <sys/_types.h>
+#endif
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+ * Definitions for byte order, according to byte significance from low
+ * address to high.
+ */
+#define _LITTLE_ENDIAN 1234 /* LSB first: i386, vax */
+#define _BIG_ENDIAN 4321 /* MSB first: 68000, ibm, net */
+#define _PDP_ENDIAN 3412 /* LSB first in word, MSW first in long */
+
+#ifdef __MIPSEB__
+#define _BYTE_ORDER _BIG_ENDIAN
+#else
+#define _BYTE_ORDER _LITTLE_ENDIAN
+#endif /* __MIBSEB__ */
+
+/*
+ * Deprecated variants that don't have enough underscores to be useful in more
+ * strict namespaces.
+ */
+#if __BSD_VISIBLE
+#define LITTLE_ENDIAN _LITTLE_ENDIAN
+#define BIG_ENDIAN _BIG_ENDIAN
+#define PDP_ENDIAN _PDP_ENDIAN
+#define BYTE_ORDER _BYTE_ORDER
+#endif
+
+#ifndef __ASSEMBLER__
+#if defined(__GNUCLIKE_BUILTIN_CONSTANT_P) && defined(__OPTIMIZE__)
+#define __is_constant(x) __builtin_constant_p(x)
+#else
+#define __is_constant(x) 0
+#endif
+
+#define __bswap16_const(x) (((x) >> 8) | (((x) << 8) & 0xff00))
+#define __bswap32_const(x) (((x) >> 24) | (((x) >> 8) & 0xff00) | \
+ (((x) << 8) & 0xff0000) | (((x) << 24) & 0xff000000))
+#define __bswap64_const(x) (((x) >> 56) | (((x) >> 40) & 0xff00) | \
+ (((x) >> 24) & 0xff0000) | (((x) >> 8) & 0xff000000) | \
+ (((x) << 8) & ((__uint64_t)0xff << 32)) | \
+ (((x) << 24) & ((__uint64_t)0xff << 40)) | \
+ (((x) << 40) & ((__uint64_t)0xff << 48)) | (((x) << 56)))
+
+static __inline __uint16_t
+__bswap16_var(__uint16_t _x)
+{
+
+ return ((_x >> 8) | ((_x << 8) & 0xff00));
+}
+
+static __inline __uint32_t
+__bswap32_var(__uint32_t _x)
+{
+
+ return ((_x >> 24) | ((_x >> 8) & 0xff00) | ((_x << 8) & 0xff0000) |
+ ((_x << 24) & 0xff000000));
+}
+
+static __inline __uint64_t
+__bswap64_var(__uint64_t _x)
+{
+
+ return ((_x >> 56) | ((_x >> 40) & 0xff00) | ((_x >> 24) & 0xff0000) |
+ ((_x >> 8) & 0xff000000) | ((_x << 8) & ((__uint64_t)0xff << 32)) |
+ ((_x << 24) & ((__uint64_t)0xff << 40)) |
+ ((_x << 40) & ((__uint64_t)0xff << 48)) | ((_x << 56)));
+}
+
+#define __bswap16(x) ((__uint16_t)(__is_constant((x)) ? \
+ __bswap16_const((__uint16_t)(x)) : __bswap16_var((__uint16_t)(x))))
+#define __bswap32(x) ((__uint32_t)(__is_constant((x)) ? \
+ __bswap32_const((__uint32_t)(x)) : __bswap32_var((__uint32_t)(x))))
+#define __bswap64(x) ((__uint64_t)(__is_constant((x)) ? \
+ __bswap64_const((__uint64_t)(x)) : __bswap64_var((__uint64_t)(x))))
+
+#ifdef __MIPSEB__
+#define __htonl(x) ((__uint32_t)(x))
+#define __htons(x) ((__uint16_t)(x))
+#define __ntohl(x) ((__uint32_t)(x))
+#define __ntohs(x) ((__uint16_t)(x))
+/*
+ * Define the order of 32-bit words in 64-bit words.
+ */
+/*
+ * XXXMIPS: Additional parentheses to make gcc more happy.
+ */
+#define _QUAD_HIGHWORD 0
+#define _QUAD_LOWWORD 1
+#else
+#define _QUAD_HIGHWORD 1
+#define _QUAD_LOWWORD 0
+#define __ntohl(x) (__bswap32((x)))
+#define __ntohs(x) (__bswap16((x)))
+#define __htonl(x) (__bswap32((x)))
+#define __htons(x) (__bswap16((x)))
+#endif /* _MIPSEB */
+
+#endif /* _ASSEMBLER_ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* !_MACHINE_ENDIAN_H_ */
Property changes on: trunk/sys/mips/include/endian.h
___________________________________________________________________
Added: svn:eol-style
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+native
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+MidnightBSD=%H
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## -0,0 +1 ##
+text/plain
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Added: trunk/sys/mips/include/exec.h
===================================================================
--- trunk/sys/mips/include/exec.h (rev 0)
+++ trunk/sys/mips/include/exec.h 2018-05-26 21:55:02 UTC (rev 9987)
@@ -0,0 +1,41 @@
+/* $MidnightBSD$ */
+/*-
+ * Copyright (c) 1992, 1993
+ * The Regents of the University of California. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * 4. Neither the name of the University nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ * @(#)exec.h 8.1 (Berkeley) 6/11/93
+ * from: src/sys/i386/include/exec.h,v 1.8 1999/08/28 00:44:11 peter
+ * JNPR: exec.h,v 1.3 2006/08/07 05:38:57 katta
+ * $FreeBSD: stable/10/sys/mips/include/exec.h 202175 2010-01-12 21:36:08Z imp $
+ */
+
+#ifndef _MACHINE_EXEC_H_
+#define _MACHINE_EXEC_H_
+
+#define __LDPGSZ 4096
+
+#endif /* !_MACHINE_EXEC_H_ */
Property changes on: trunk/sys/mips/include/exec.h
___________________________________________________________________
Added: svn:eol-style
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+native
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+text/plain
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Added: trunk/sys/mips/include/fdt.h
===================================================================
--- trunk/sys/mips/include/fdt.h (rev 0)
+++ trunk/sys/mips/include/fdt.h 2018-05-26 21:55:02 UTC (rev 9987)
@@ -0,0 +1,47 @@
+/* $MidnightBSD$ */
+/*-
+ * Copyright (c) 2010 The FreeBSD Foundation
+ * All rights reserved.
+ *
+ * This software was developed by Semihalf under sponsorship from
+ * the FreeBSD Foundation.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ * $FreeBSD: stable/10/sys/mips/include/fdt.h 266084 2014-05-14 19:18:58Z ian $
+ */
+
+#ifndef _MACHINE_FDT_H_
+#define _MACHINE_FDT_H_
+
+#include <machine/bus.h>
+
+/*
+ * Bus space tag. XXX endianess info needs to be derived from the blob.
+ */
+#if defined(CPU_RMI) || defined(CPU_NLM)
+#define fdtbus_bs_tag rmi_uart_bus_space
+#else
+#define fdtbus_bs_tag mips_bus_space_fdt
+#endif
+
+#endif /* _MACHINE_FDT_H_ */
Property changes on: trunk/sys/mips/include/fdt.h
___________________________________________________________________
Added: svn:eol-style
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+native
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+MidnightBSD=%H
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+text/plain
\ No newline at end of property
Added: trunk/sys/mips/include/float.h
===================================================================
--- trunk/sys/mips/include/float.h (rev 0)
+++ trunk/sys/mips/include/float.h 2018-05-26 21:55:02 UTC (rev 9987)
@@ -0,0 +1,102 @@
+/* $MidnightBSD$ */
+/*-
+ * Copyright (c) 1989 Regents of the University of California.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * 4. Neither the name of the University nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ * from: @(#)float.h 7.1 (Berkeley) 5/8/90
+ * from: src/sys/i386/include/float.h,v 1.8 1999/08/28 00:44:11 peter
+ * JNPR: float.h,v 1.4 2006/12/02 09:53:41 katta
+ * $FreeBSD: stable/10/sys/mips/include/float.h 230475 2012-01-23 06:36:41Z das $
+ */
+
+#ifndef _MACHINE_FLOAT_H_
+#define _MACHINE_FLOAT_H_ 1
+
+#include <sys/cdefs.h>
+
+__BEGIN_DECLS
+extern int __flt_rounds(void);
+__END_DECLS
+
+#define FLT_RADIX 2 /* b */
+#ifdef CPU_HAVEFPU
+#define FLT_ROUNDS __flt_rounds() /* FP addition rounds to nearest */
+#else
+#define FLT_ROUNDS (-1)
+#endif
+
+#if __ISO_C_VISIBLE >= 1999
+#define FLT_EVAL_METHOD 0
+#define DECIMAL_DIG 17
+#endif
+
+#define FLT_MANT_DIG 24 /* p */
+#define FLT_EPSILON 1.19209290E-07F /* b**(1-p) */
+#define FLT_DIG 6 /* floor((p-1)*log10(b))+(b == 10) */
+#define FLT_MIN_EXP (-125) /* emin */
+#define FLT_MIN 1.17549435E-38F /* b**(emin-1) */
+#define FLT_MIN_10_EXP (-37) /* ceil(log10(b**(emin-1))) */
+#define FLT_MAX_EXP 128 /* emax */
+#define FLT_MAX 3.40282347E+38F /* (1-b**(-p))*b**emax */
+#define FLT_MAX_10_EXP 38 /* floor(log10((1-b**(-p))*b**emax)) */
+#if __ISO_C_VISIBLE >= 2011
+#define FLT_TRUE_MIN 1.40129846E-45F /* b**(emin-p) */
+#define FLT_DECIMAL_DIG 9 /* ceil(1+p*log10(b)) */
+#define FLT_HAS_SUBNORM 1
+#endif /* __ISO_C_VISIBLE >= 2011 */
+
+#define DBL_MANT_DIG 53
+#define DBL_EPSILON 2.2204460492503131E-16
+#define DBL_DIG 15
+#define DBL_MIN_EXP (-1021)
+#define DBL_MIN 2.2250738585072014E-308
+#define DBL_MIN_10_EXP (-307)
+#define DBL_MAX_EXP 1024
+#define DBL_MAX 1.7976931348623157E+308
+#define DBL_MAX_10_EXP 308
+#if __ISO_C_VISIBLE >= 2011
+#define DBL_TRUE_MIN 4.9406564584124654E-324
+#define DBL_DECIMAL_DIG 17
+#define DBL_HAS_SUBNORM 1
+#endif /* __ISO_C_VISIBLE >= 2011 */
+
+#define LDBL_MANT_DIG DBL_MANT_DIG
+#define LDBL_EPSILON ((long double)DBL_EPSILON)
+#define LDBL_DIG DBL_DIG
+#define LDBL_MIN_EXP DBL_MIN_EXP
+#define LDBL_MIN ((long double)DBL_MIN)
+#define LDBL_MIN_10_EXP DBL_MIN_10_EXP
+#define LDBL_MAX_EXP DBL_MAX_EXP
+#define LDBL_MAX ((long double)DBL_MAX)
+#define LDBL_MAX_10_EXP DBL_MAX_10_EXP
+#if __ISO_C_VISIBLE >= 2011
+#define LDBL_TRUE_MIN ((long double)DBL_TRUE_MIN)
+#define LDBL_DECIMAL_DIG DBL_DECIMAL_DIG
+#define LDBL_HAS_SUBNORM DBL_HAS_SUBNORM
+#endif /* __ISO_C_VISIBLE >= 2011 */
+
+#endif /* _MACHINE_FLOAT_H_ */
Property changes on: trunk/sys/mips/include/float.h
___________________________________________________________________
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+MidnightBSD=%H
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+text/plain
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Added: trunk/sys/mips/include/floatingpoint.h
===================================================================
--- trunk/sys/mips/include/floatingpoint.h (rev 0)
+++ trunk/sys/mips/include/floatingpoint.h 2018-05-26 21:55:02 UTC (rev 9987)
@@ -0,0 +1,44 @@
+/* $MidnightBSD$ */
+/*-
+ * Copyright (c) 1993 Andrew Moore, Talke Studio
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * 3. All advertising materials mentioning features or use of this software
+ * must display the following acknowledgement:
+ * This product includes software developed by the University of
+ * California, Berkeley and its contributors.
+ * 4. Neither the name of the University nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ * from: @(#) floatingpoint.h 1.0 (Berkeley) 9/23/93
+ * $FreeBSD: stable/10/sys/mips/include/floatingpoint.h 202175 2010-01-12 21:36:08Z imp $
+ */
+
+#ifndef _FLOATINGPOINT_H_
+#define _FLOATINGPOINT_H_
+
+#include <sys/cdefs.h>
+#include <machine/ieeefp.h>
+
+#endif /* !_FLOATINGPOINT_H_ */
Property changes on: trunk/sys/mips/include/floatingpoint.h
___________________________________________________________________
Added: svn:eol-style
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Added: trunk/sys/mips/include/fls64.h
===================================================================
--- trunk/sys/mips/include/fls64.h (rev 0)
+++ trunk/sys/mips/include/fls64.h 2018-05-26 21:55:02 UTC (rev 9987)
@@ -0,0 +1,48 @@
+/* $MidnightBSD$ */
+/*-
+ * Copyright (c) 2003-2009 RMI Corporation
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * 3. Neither the name of RMI Corporation, nor the names of its contributors,
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ * RMI_BSD */
+#ifndef _MIPS_FLS64_H_
+#define _MIPS_FLS64_H_
+
+/*
+ * Find Last Set bit (64 bit)
+ */
+static inline int
+fls64(__uint64_t mask)
+{
+ int bit;
+
+ if (mask == 0)
+ return (0);
+ for (bit = 1; ((mask & 0x1ULL) == 0); bit++)
+ mask = mask >> 1;
+ return (bit);
+}
+#endif
Property changes on: trunk/sys/mips/include/fls64.h
___________________________________________________________________
Added: svn:eol-style
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+text/plain
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Added: trunk/sys/mips/include/fpu.h
===================================================================
--- trunk/sys/mips/include/fpu.h (rev 0)
+++ trunk/sys/mips/include/fpu.h 2018-05-26 21:55:02 UTC (rev 9987)
@@ -0,0 +1,10 @@
+/* $MidnightBSD$ */
+/*-
+ * This file is in the public domain.
+ *
+ * $FreeBSD: stable/10/sys/mips/include/fpu.h 202175 2010-01-12 21:36:08Z imp $
+ */
+#ifndef _MACHINE_FPU_H_
+#define _MACHINE_FPU_H_
+
+#endif /* !_MACHINE_FPU_H_ */
Property changes on: trunk/sys/mips/include/fpu.h
___________________________________________________________________
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+text/plain
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Added: trunk/sys/mips/include/frame.h
===================================================================
--- trunk/sys/mips/include/frame.h (rev 0)
+++ trunk/sys/mips/include/frame.h 2018-05-26 21:55:02 UTC (rev 9987)
@@ -0,0 +1,141 @@
+/* $MidnightBSD$ */
+/* $OpenBSD: frame.h,v 1.3 1998/09/15 10:50:12 pefo Exp $ */
+
+/*-
+ * Copyright (c) 1998 Per Fogelstrom, Opsycon AB
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * 3. All advertising materials mentioning features or use of this software
+ * must display the following acknowledgement:
+ * This product includes software developed under OpenBSD by
+ * Per Fogelstrom, Opsycon AB, Sweden.
+ * 4. The name of the author may not be used to endorse or promote products
+ * derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS
+ * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ * JNPR: frame.h,v 1.6.2.1 2007/09/10 08:14:57 girish
+ * $FreeBSD: stable/10/sys/mips/include/frame.h 249790 2013-04-23 09:38:18Z imp $
+ *
+ */
+#ifndef _MACHINE_FRAME_H_
+#define _MACHINE_FRAME_H_
+
+/* Note: This must also match regnum.h and regdef.h */
+
+struct trapframe {
+ register_t zero;
+ register_t ast;
+ register_t v0;
+ register_t v1;
+ register_t a0;
+ register_t a1;
+ register_t a2;
+ register_t a3;
+#if defined(__mips_n32) || defined(__mips_n64)
+ register_t a4;
+ register_t a5;
+ register_t a6;
+ register_t a7;
+ register_t t0;
+ register_t t1;
+ register_t t2;
+ register_t t3;
+#else
+ register_t t0;
+ register_t t1;
+ register_t t2;
+ register_t t3;
+ register_t t4;
+ register_t t5;
+ register_t t6;
+ register_t t7;
+#endif
+ register_t s0;
+ register_t s1;
+ register_t s2;
+ register_t s3;
+ register_t s4;
+ register_t s5;
+ register_t s6;
+ register_t s7;
+ register_t t8;
+ register_t t9;
+ register_t k0;
+ register_t k1;
+ register_t gp;
+ register_t sp;
+ register_t s8;
+ register_t ra;
+ register_t sr;
+ register_t mullo;
+ register_t mulhi;
+ register_t badvaddr;
+ register_t cause;
+ register_t pc;
+ /*
+ * FREEBSD_DEVELOPERS_FIXME:
+ * Include any other registers which are CPU-Specific and
+ * need to be part of the frame here.
+ *
+ * Also, be sure this matches what is defined in regnum.h
+ */
+ register_t ic; /* RM7k and RM9k specific */
+ register_t dummy; /* Alignment for 32-bit case */
+
+/* From here and on, only saved user processes. */
+
+ f_register_t f0;
+ f_register_t f1;
+ f_register_t f2;
+ f_register_t f3;
+ f_register_t f4;
+ f_register_t f5;
+ f_register_t f6;
+ f_register_t f7;
+ f_register_t f8;
+ f_register_t f9;
+ f_register_t f10;
+ f_register_t f11;
+ f_register_t f12;
+ f_register_t f13;
+ f_register_t f14;
+ f_register_t f15;
+ f_register_t f16;
+ f_register_t f17;
+ f_register_t f18;
+ f_register_t f19;
+ f_register_t f20;
+ f_register_t f21;
+ f_register_t f22;
+ f_register_t f23;
+ f_register_t f24;
+ f_register_t f25;
+ f_register_t f26;
+ f_register_t f27;
+ f_register_t f28;
+ f_register_t f29;
+ f_register_t f30;
+ f_register_t f31;
+ register_t fsr;
+ register_t fdummy;
+};
+
+#endif /* !_MACHINE_FRAME_H_ */
Property changes on: trunk/sys/mips/include/frame.h
___________________________________________________________________
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Added: trunk/sys/mips/include/gdb_machdep.h
===================================================================
--- trunk/sys/mips/include/gdb_machdep.h (rev 0)
+++ trunk/sys/mips/include/gdb_machdep.h 2018-05-26 21:55:02 UTC (rev 9987)
@@ -0,0 +1,57 @@
+/* $MidnightBSD$ */
+/*-
+ * Copyright (c) 2004 Marcel Moolenaar
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+ * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+ * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * from: src/sys/alpha/include/gdb_machdep.h,v 1.3 2005/01/05 20:05:50 imp
+ * JNPR: gdb_machdep.h,v 1.1 2007/08/09 12:25:25 katta
+ * $FreeBSD: stable/10/sys/mips/include/gdb_machdep.h 202175 2010-01-12 21:36:08Z imp $
+ */
+
+#ifndef _MACHINE_GDB_MACHDEP_H_
+#define _MACHINE_GDB_MACHDEP_H_
+
+#define GDB_BUFSZ 600
+#define GDB_NREGS 90
+#define GDB_REG_PC 37
+
+static __inline size_t
+gdb_cpu_regsz(int regnum)
+{
+
+ return (sizeof(long));
+}
+
+static __inline int
+gdb_cpu_query(void)
+{
+
+ return (0);
+}
+
+void *gdb_cpu_getreg(int, size_t *);
+void gdb_cpu_setreg(int, void *);
+int gdb_cpu_signal(int, int);
+
+#endif /* !_MACHINE_GDB_MACHDEP_H_ */
Property changes on: trunk/sys/mips/include/gdb_machdep.h
___________________________________________________________________
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+MidnightBSD=%H
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+text/plain
\ No newline at end of property
Added: trunk/sys/mips/include/hwfunc.h
===================================================================
--- trunk/sys/mips/include/hwfunc.h (rev 0)
+++ trunk/sys/mips/include/hwfunc.h 2018-05-26 21:55:02 UTC (rev 9987)
@@ -0,0 +1,102 @@
+/* $MidnightBSD$ */
+/*-
+ * Copyright (c) 2003-2004 Juli Mallett. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ * $FreeBSD: stable/10/sys/mips/include/hwfunc.h 232853 2012-03-12 07:34:15Z jmallett $
+ */
+
+#ifndef _MACHINE_HWFUNC_H_
+#define _MACHINE_HWFUNC_H_
+
+#include <sys/_cpuset.h>
+
+struct timecounter;
+
+/*
+ * Hooks downward into platform functionality.
+ */
+void platform_reset(void);
+void platform_start(__register_t, __register_t, __register_t, __register_t);
+
+/* For clocks and ticks and such */
+void platform_initclocks(void);
+uint64_t platform_get_frequency(void);
+unsigned platform_get_timecount(struct timecounter *);
+
+/* For hardware specific CPU initialization */
+void platform_cpu_init(void);
+
+#ifdef SMP
+
+/*
+ * Spin up the AP so that it starts executing MP bootstrap entry point: mpentry
+ *
+ * Returns 0 on sucess and non-zero on failure.
+ */
+int platform_start_ap(int processor_id);
+
+/*
+ * Platform-specific initialization that needs to be done when an AP starts
+ * running. This function is called from the MP bootstrap code in mpboot.S
+ */
+void platform_init_ap(int processor_id);
+
+/*
+ * Return a plaform-specific interrrupt number that is used to deliver IPIs.
+ *
+ * This hardware interrupt is used to deliver IPIs exclusively and must
+ * not be used for any other interrupt source.
+ */
+int platform_ipi_intrnum(void);
+
+/*
+ * Trigger a IPI interrupt on 'cpuid'.
+ */
+void platform_ipi_send(int cpuid);
+
+/*
+ * Quiesce the IPI interrupt source on the current cpu.
+ */
+void platform_ipi_clear(void);
+
+/*
+ * Return the processor id.
+ *
+ * Note that this function is called in early boot when stack is not available.
+ */
+extern int platform_processor_id(void);
+
+/*
+ * Return the cpumask of available processors.
+ */
+extern void platform_cpu_mask(cpuset_t *mask);
+
+/*
+ * Return the topology of processors on this platform
+ */
+struct cpu_group *platform_smp_topo(void);
+
+#endif /* SMP */
+
+#endif /* !_MACHINE_HWFUNC_H_ */
Property changes on: trunk/sys/mips/include/hwfunc.h
___________________________________________________________________
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Added: trunk/sys/mips/include/ieee.h
===================================================================
--- trunk/sys/mips/include/ieee.h (rev 0)
+++ trunk/sys/mips/include/ieee.h 2018-05-26 21:55:02 UTC (rev 9987)
@@ -0,0 +1,155 @@
+/* $MidnightBSD$ */
+/* $NetBSD: ieee754.h,v 1.4 2003/10/27 02:30:26 simonb Exp $ */
+
+/*-
+ * Copyright (c) 1992, 1993
+ * The Regents of the University of California. All rights reserved.
+ *
+ * This software was developed by the Computer Systems Engineering group
+ * at Lawrence Berkeley Laboratory under DARPA contract BG 91-66 and
+ * contributed to Berkeley.
+ *
+ * All advertising materials mentioning features or use of this software
+ * must display the following acknowledgement:
+ * This product includes software developed by the University of
+ * California, Lawrence Berkeley Laboratory.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * 3. Neither the name of the University nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ * @(#)ieee.h 8.1 (Berkeley) 6/11/93
+ *
+ * $FreeBSD: stable/10/sys/mips/include/ieee.h 202175 2010-01-12 21:36:08Z imp $
+ *
+ */
+
+/*
+ * NOTICE: This is not a standalone file. To use it, #include it in
+ * your port's ieee.h header.
+ */
+
+#include <machine/endian.h>
+
+/*
+ * <sys/ieee754.h> defines the layout of IEEE 754 floating point types.
+ * Only single-precision and double-precision types are defined here;
+ * extended types, if available, are defined in the machine-dependent
+ * header.
+ */
+
+/*
+ * Define the number of bits in each fraction and exponent.
+ *
+ * k k+1
+ * Note that 1.0 x 2 == 0.1 x 2 and that denorms are represented
+ *
+ * (-exp_bias+1)
+ * as fractions that look like 0.fffff x 2 . This means that
+ *
+ * -126
+ * the number 0.10000 x 2 , for instance, is the same as the normalized
+ *
+ * -127 -128
+ * float 1.0 x 2 . Thus, to represent 2 , we need one leading zero
+ *
+ * -129
+ * in the fraction; to represent 2 , we need two, and so on. This
+ *
+ * (-exp_bias-fracbits+1)
+ * implies that the smallest denormalized number is 2
+ *
+ * for whichever format we are talking about: for single precision, for
+ *
+ * -126 -149
+ * instance, we get .00000000000000000000001 x 2 , or 1.0 x 2 , and
+ *
+ * -149 == -127 - 23 + 1.
+ */
+#define SNG_EXPBITS 8
+#define SNG_FRACBITS 23
+
+#define DBL_EXPBITS 11
+#define DBL_FRACBITS 52
+
+struct ieee_single {
+#if _BYTE_ORDER == _BIG_ENDIAN
+ u_int sng_sign:1;
+ u_int sng_exp:8;
+ u_int sng_frac:23;
+#else
+ u_int sng_frac:23;
+ u_int sng_exp:8;
+ u_int sng_sign:1;
+#endif
+};
+
+struct ieee_double {
+#if _BYTE_ORDER == _BIG_ENDIAN
+ u_int dbl_sign:1;
+ u_int dbl_exp:11;
+ u_int dbl_frach:20;
+ u_int dbl_fracl;
+#else
+ u_int dbl_fracl;
+ u_int dbl_frach:20;
+ u_int dbl_exp:11;
+ u_int dbl_sign:1;
+#endif
+};
+
+/*
+ * Floats whose exponent is in [1..INFNAN) (of whatever type) are
+ * `normal'. Floats whose exponent is INFNAN are either Inf or NaN.
+ * Floats whose exponent is zero are either zero (iff all fraction
+ * bits are zero) or subnormal values.
+ *
+ * A NaN is a `signalling NaN' if its QUIETNAN bit is clear in its
+ * high fraction; if the bit is set, it is a `quiet NaN'.
+ */
+#define SNG_EXP_INFNAN 255
+#define DBL_EXP_INFNAN 2047
+
+#if 0
+#define SNG_QUIETNAN (1 << 22)
+#define DBL_QUIETNAN (1 << 19)
+#endif
+
+/*
+ * Exponent biases.
+ */
+#define SNG_EXP_BIAS 127
+#define DBL_EXP_BIAS 1023
+
+/*
+ * Convenience data structures.
+ */
+union ieee_single_u {
+ float sngu_f;
+ struct ieee_single sngu_sng;
+};
+
+union ieee_double_u {
+ double dblu_d;
+ struct ieee_double dblu_dbl;
+};
Property changes on: trunk/sys/mips/include/ieee.h
___________________________________________________________________
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Added: trunk/sys/mips/include/ieeefp.h
===================================================================
--- trunk/sys/mips/include/ieeefp.h (rev 0)
+++ trunk/sys/mips/include/ieeefp.h 2018-05-26 21:55:02 UTC (rev 9987)
@@ -0,0 +1,35 @@
+/* $MidnightBSD$ */
+/* $OpenBSD: ieeefp.h,v 1.2 1999/01/27 04:46:05 imp Exp $ */
+
+/*-
+ * Written by J.T. Conklin, Apr 11, 1995
+ * Public domain.
+ *
+ * JNPR: ieeefp.h,v 1.1 2006/08/07 05:38:57 katta
+ * $FreeBSD: stable/10/sys/mips/include/ieeefp.h 226607 2011-10-21 06:41:46Z das $
+ */
+
+#ifndef _MACHINE_IEEEFP_H_
+#define _MACHINE_IEEEFP_H_
+
+/* Deprecated historical FPU control interface */
+
+typedef int fp_except;
+typedef int fp_except_t;
+
+#define FP_X_IMP 0x01 /* imprecise (loss of precision) */
+#define FP_X_UFL 0x02 /* underflow exception */
+#define FP_X_OFL 0x04 /* overflow exception */
+#define FP_X_DZ 0x08 /* divide-by-zero exception */
+#define FP_X_INV 0x10 /* invalid operation exception */
+
+typedef enum {
+ FP_RN=0, /* round to nearest representable number */
+ FP_RZ=1, /* round to zero (truncate) */
+ FP_RP=2, /* round toward positive infinity */
+ FP_RM=3 /* round toward negative infinity */
+} fp_rnd;
+
+typedef fp_rnd fp_rnd_t;
+
+#endif /* !_MACHINE_IEEEFP_H_ */
Property changes on: trunk/sys/mips/include/ieeefp.h
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+text/plain
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Added: trunk/sys/mips/include/in_cksum.h
===================================================================
--- trunk/sys/mips/include/in_cksum.h (rev 0)
+++ trunk/sys/mips/include/in_cksum.h 2018-05-26 21:55:02 UTC (rev 9987)
@@ -0,0 +1,82 @@
+/* $MidnightBSD$ */
+/*-
+ * Copyright (c) 1990 The Regents of the University of California.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * 4. Neither the name of the University nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ * from tahoe: in_cksum.c 1.2 86/01/05
+ * from: @(#)in_cksum.c 1.3 (Berkeley) 1/19/91
+ * from: Id: in_cksum.c,v 1.8 1995/12/03 18:35:19 bde Exp
+ * from: src/sys/alpha/include/in_cksum.h,v 1.7 2005/03/02 21:33:20 joerg
+ * $FreeBSD: stable/10/sys/mips/include/in_cksum.h 235941 2012-05-24 22:00:48Z bz $
+ */
+
+#ifndef _MACHINE_IN_CKSUM_H_
+#define _MACHINE_IN_CKSUM_H_ 1
+
+#include <sys/cdefs.h>
+
+#define in_cksum(m, len) in_cksum_skip(m, len, 0)
+
+#if defined(IPVERSION) && (IPVERSION == 4)
+/*
+ * It it useful to have an Internet checksum routine which is inlineable
+ * and optimized specifically for the task of computing IP header checksums
+ * in the normal case (where there are no options and the header length is
+ * therefore always exactly five 32-bit words.
+ */
+#ifdef __CC_SUPPORTS___INLINE
+
+static __inline void
+in_cksum_update(struct ip *ip)
+{
+ int __tmpsum;
+ __tmpsum = (int)ntohs(ip->ip_sum) + 256;
+ ip->ip_sum = htons(__tmpsum + (__tmpsum >> 16));
+}
+
+#else
+
+#define in_cksum_update(ip) \
+ do { \
+ int __tmpsum; \
+ __tmpsum = (int)ntohs(ip->ip_sum) + 256; \
+ ip->ip_sum = htons(__tmpsum + (__tmpsum >> 16)); \
+ } while(0)
+
+#endif
+#endif
+
+#ifdef _KERNEL
+#if defined(IPVERSION) && (IPVERSION == 4)
+u_int in_cksum_hdr(const struct ip *ip);
+#endif
+u_short in_addword(u_short sum, u_short b);
+u_short in_pseudo(u_int sum, u_int b, u_int c);
+u_short in_cksum_skip(struct mbuf *m, int len, int skip);
+#endif
+
+#endif /* _MACHINE_IN_CKSUM_H_ */
Property changes on: trunk/sys/mips/include/in_cksum.h
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Added: trunk/sys/mips/include/intr_machdep.h
===================================================================
--- trunk/sys/mips/include/intr_machdep.h (rev 0)
+++ trunk/sys/mips/include/intr_machdep.h 2018-05-26 21:55:02 UTC (rev 9987)
@@ -0,0 +1,75 @@
+/* $MidnightBSD$ */
+/*-
+ * Copyright (c) 2004 Juli Mallett <jmallett at FreeBSD.org>
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ * $FreeBSD: stable/10/sys/mips/include/intr_machdep.h 228982 2011-12-30 03:54:22Z marcel $
+ */
+
+#ifndef _MACHINE_INTR_MACHDEP_H_
+#define _MACHINE_INTR_MACHDEP_H_
+
+#include <machine/atomic.h>
+
+#if defined(CPU_RMI) || defined(CPU_NLM)
+#define XLR_MAX_INTR 64
+#else
+#define NHARD_IRQS 6
+#define NSOFT_IRQS 2
+#endif
+
+struct trapframe;
+
+void cpu_init_interrupts(void);
+void cpu_establish_hardintr(const char *, driver_filter_t *, driver_intr_t *,
+ void *, int, int, void **);
+void cpu_establish_softintr(const char *, driver_filter_t *, void (*)(void*),
+ void *, int, int, void **);
+void cpu_intr(struct trapframe *);
+
+/*
+ * Allow a platform to override the default hard interrupt mask and unmask
+ * functions. The 'arg' can be cast safely to an 'int' and holds the mips
+ * hard interrupt number to mask or unmask.
+ */
+typedef void (*cpu_intr_mask_t)(void *arg);
+typedef void (*cpu_intr_unmask_t)(void *arg);
+void cpu_set_hardintr_mask_func(cpu_intr_mask_t func);
+void cpu_set_hardintr_unmask_func(cpu_intr_unmask_t func);
+
+/*
+ * Opaque datatype that represents intr counter
+ */
+typedef unsigned long* mips_intrcnt_t;
+
+mips_intrcnt_t mips_intrcnt_create(const char *);
+void mips_intrcnt_setname(mips_intrcnt_t, const char *);
+
+static __inline void
+mips_intrcnt_inc(mips_intrcnt_t counter)
+{
+ if (counter)
+ atomic_add_long(counter, 1);
+}
+#endif /* !_MACHINE_INTR_MACHDEP_H_ */
Property changes on: trunk/sys/mips/include/intr_machdep.h
___________________________________________________________________
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+MidnightBSD=%H
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+text/plain
\ No newline at end of property
Added: trunk/sys/mips/include/kdb.h
===================================================================
--- trunk/sys/mips/include/kdb.h (rev 0)
+++ trunk/sys/mips/include/kdb.h 2018-05-26 21:55:02 UTC (rev 9987)
@@ -0,0 +1,57 @@
+/* $MidnightBSD$ */
+/*-
+ * Copyright (c) 2004 Marcel Moolenaar
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+ * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+ * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * from: src/sys/alpha/include/kdb.h,v 1.2 2005/01/05 20:05:50 imp
+ * $FreeBSD: stable/10/sys/mips/include/kdb.h 204997 2010-03-11 07:17:14Z neel $
+ */
+
+#ifndef _MACHINE_KDB_H_
+#define _MACHINE_KDB_H_
+
+#include <machine/frame.h>
+
+#define KDB_STOPPEDPCB(pc) &stoppcbs[pc->pc_cpuid]
+
+static __inline void
+kdb_cpu_clear_singlestep(void)
+{
+}
+
+static __inline void
+kdb_cpu_set_singlestep(void)
+{
+}
+
+static __inline void
+kdb_cpu_trap(int vector, int _)
+{
+}
+
+static __inline void
+kdb_cpu_sync_icache(unsigned char *addr, size_t size)
+{
+}
+#endif /* _MACHINE_KDB_H_ */
Property changes on: trunk/sys/mips/include/kdb.h
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+text/plain
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Added: trunk/sys/mips/include/limits.h
===================================================================
--- trunk/sys/mips/include/limits.h (rev 0)
+++ trunk/sys/mips/include/limits.h 2018-05-26 21:55:02 UTC (rev 9987)
@@ -0,0 +1,46 @@
+/* $MidnightBSD$ */
+/*-
+ * Copyright (c) 1988, 1993
+ * The Regents of the University of California. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * 4. Neither the name of the University nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ * @(#)limits.h 8.3 (Berkeley) 1/4/94
+ * from: src/sys/i386/include/limits.h,v 1.27 2005/03/02 21:33:26 joerg
+ * $FreeBSD: stable/10/sys/mips/include/limits.h 202175 2010-01-12 21:36:08Z imp $
+ */
+
+#ifndef _MACHINE_LIMITS_H_
+#define _MACHINE_LIMITS_H_
+
+#include <sys/cdefs.h>
+
+#ifdef __CC_SUPPORTS_WARNING
+#warning "machine/limits.h is deprecated. Include sys/limits.h instead."
+#endif
+
+#include <sys/limits.h>
+
+#endif /* !_MACHINE_LIMITS_H_ */
Property changes on: trunk/sys/mips/include/limits.h
___________________________________________________________________
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+text/plain
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Added: trunk/sys/mips/include/locore.h
===================================================================
--- trunk/sys/mips/include/locore.h (rev 0)
+++ trunk/sys/mips/include/locore.h 2018-05-26 21:55:02 UTC (rev 9987)
@@ -0,0 +1,65 @@
+/* $MidnightBSD$ */
+/* $NetBSD: locore.h,v 1.78 2007/10/17 19:55:36 garbled Exp $ */
+
+/*
+ * Copyright 1996 The Board of Trustees of The Leland Stanford
+ * Junior University. All Rights Reserved.
+ *
+ * Permission to use, copy, modify, and distribute this
+ * software and its documentation for any purpose and without
+ * fee is hereby granted, provided that the above copyright
+ * notice appear in all copies. Stanford University
+ * makes no representations about the suitability of this
+ * software for any purpose. It is provided "as is" without
+ * express or implied warranty.
+ *
+ * $FreeBSD: stable/10/sys/mips/include/locore.h 232615 2012-03-06 19:01:32Z jmallett $
+ */
+
+/*
+ * Jump table for MIPS cpu locore functions that are implemented
+ * differently on different generations, or instruction-level
+ * archtecture (ISA) level, the Mips family.
+ *
+ * We currently provide support for MIPS I and MIPS III.
+ */
+
+#ifndef _MIPS_LOCORE_H
+#define _MIPS_LOCORE_H
+
+#include <machine/cpufunc.h>
+#include <machine/cpuregs.h>
+#include <machine/frame.h>
+#include <machine/md_var.h>
+
+/*
+ * CPU identification, from PRID register.
+ */
+
+#define MIPS_PRID_REV(x) (((x) >> 0) & 0x00ff)
+#define MIPS_PRID_IMPL(x) (((x) >> 8) & 0x00ff)
+
+/* pre-MIPS32/64 */
+#define MIPS_PRID_RSVD(x) (((x) >> 16) & 0xffff)
+#define MIPS_PRID_REV_MIN(x) ((MIPS_PRID_REV(x) >> 0) & 0x0f)
+#define MIPS_PRID_REV_MAJ(x) ((MIPS_PRID_REV(x) >> 4) & 0x0f)
+
+/* MIPS32/64 */
+#define MIPS_PRID_CID(x) (((x) >> 16) & 0x00ff) /* Company ID */
+#define MIPS_PRID_CID_PREHISTORIC 0x00 /* Not MIPS32/64 */
+#define MIPS_PRID_CID_MTI 0x01 /* MIPS Technologies, Inc. */
+#define MIPS_PRID_CID_BROADCOM 0x02 /* Broadcom */
+#define MIPS_PRID_CID_ALCHEMY 0x03 /* Alchemy Semiconductor */
+#define MIPS_PRID_CID_SIBYTE 0x04 /* SiByte */
+#define MIPS_PRID_CID_SANDCRAFT 0x05 /* SandCraft */
+#define MIPS_PRID_CID_PHILIPS 0x06 /* Philips */
+#define MIPS_PRID_CID_TOSHIBA 0x07 /* Toshiba */
+#define MIPS_PRID_CID_LSI 0x08 /* LSI */
+ /* 0x09 unannounced */
+ /* 0x0a unannounced */
+#define MIPS_PRID_CID_LEXRA 0x0b /* Lexra */
+#define MIPS_PRID_CID_RMI 0x0c /* RMI */
+#define MIPS_PRID_CID_CAVIUM 0x0d /* Cavium */
+#define MIPS_PRID_COPTS(x) (((x) >> 24) & 0x00ff) /* Company Options */
+
+#endif /* _MIPS_LOCORE_H */
Property changes on: trunk/sys/mips/include/locore.h
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Added: trunk/sys/mips/include/md_var.h
===================================================================
--- trunk/sys/mips/include/md_var.h (rev 0)
+++ trunk/sys/mips/include/md_var.h 2018-05-26 21:55:02 UTC (rev 9987)
@@ -0,0 +1,84 @@
+/* $MidnightBSD$ */
+/*-
+ * Copyright (c) 1995 Bruce D. Evans.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * 3. Neither the name of the author nor the names of contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ * from: src/sys/i386/include/md_var.h,v 1.35 2000/02/20 20:51:23 bsd
+ * JNPR: md_var.h,v 1.4 2006/10/16 12:30:34 katta
+ * $FreeBSD: stable/10/sys/mips/include/md_var.h 232855 2012-03-12 08:13:04Z jmallett $
+ */
+
+#ifndef _MACHINE_MD_VAR_H_
+#define _MACHINE_MD_VAR_H_
+
+#include <machine/reg.h>
+
+/*
+ * Miscellaneous machine-dependent declarations.
+ */
+extern long Maxmem;
+extern char sigcode[];
+extern int szsigcode;
+#if defined(__mips_n32) || defined(__mips_n64)
+extern char sigcode32[];
+extern int szsigcode32;
+#endif
+extern uint32_t *vm_page_dump;
+extern int vm_page_dump_size;
+
+extern vm_offset_t kstack0;
+extern vm_offset_t kernel_kseg0_end;
+
+void MipsSaveCurFPState(struct thread *);
+void fork_trampoline(void);
+uintptr_t MipsEmulateBranch(struct trapframe *, uintptr_t, int, uintptr_t);
+void MipsSwitchFPState(struct thread *, struct trapframe *);
+int is_cacheable_mem(vm_paddr_t addr);
+void mips_wait(void);
+
+#define MIPS_DEBUG 0
+
+#if MIPS_DEBUG
+#define MIPS_DEBUG_PRINT(fmt, args...) printf("%s: " fmt "\n" , __FUNCTION__ , ## args)
+#else
+#define MIPS_DEBUG_PRINT(fmt, args...)
+#endif
+
+void mips_vector_init(void);
+void mips_cpu_init(void);
+void mips_pcpu0_init(void);
+void mips_proc0_init(void);
+void mips_postboot_fixup(void);
+
+extern int busdma_swi_pending;
+void busdma_swi(void);
+
+struct dumperinfo;
+void dump_add_page(vm_paddr_t);
+void dump_drop_page(vm_paddr_t);
+void minidumpsys(struct dumperinfo *);
+#endif /* !_MACHINE_MD_VAR_H_ */
Property changes on: trunk/sys/mips/include/md_var.h
___________________________________________________________________
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Added: trunk/sys/mips/include/memdev.h
===================================================================
--- trunk/sys/mips/include/memdev.h (rev 0)
+++ trunk/sys/mips/include/memdev.h 2018-05-26 21:55:02 UTC (rev 9987)
@@ -0,0 +1,42 @@
+/* $MidnightBSD$ */
+/*-
+ * Copyright (c) 2004 Mark R V Murray
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer
+ * in this position and unchanged.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHORS ``AS IS'' AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+ * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+ * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * from: src/sys/alpha/include/memdev.h,v 1.2 2004/08/01 18:51:44 markm
+ * $FreeBSD: stable/10/sys/mips/include/memdev.h 217515 2011-01-17 22:58:28Z jkim $
+ */
+
+#ifndef _MACHINE_MEMDEV_H_
+#define _MACHINE_MEMDEV_H_
+
+#define CDEV_MINOR_MEM 0
+#define CDEV_MINOR_KMEM 1
+
+d_open_t memopen;
+d_read_t memrw;
+#define memioctl (d_ioctl_t *)NULL
+d_mmap_t memmmap;
+
+#endif /* _MACHINE_MEMDEV_H_ */
Property changes on: trunk/sys/mips/include/memdev.h
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Added: trunk/sys/mips/include/metadata.h
===================================================================
--- trunk/sys/mips/include/metadata.h (rev 0)
+++ trunk/sys/mips/include/metadata.h 2018-05-26 21:55:02 UTC (rev 9987)
@@ -0,0 +1,36 @@
+/* $MidnightBSD$ */
+/*-
+ * Copyright (c) 2003 Peter Wemm <peter at FreeBSD.org>
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ * $FreeBSD: stable/10/sys/mips/include/metadata.h 245330 2013-01-12 13:20:21Z rwatson $
+ */
+
+#ifndef _MACHINE_METADATA_H_
+#define _MACHINE_METADATA_H_
+
+#define MODINFOMD_SMAP 0x1001
+#define MODINFOMD_DTBP 0x1002
+
+#endif /* !_MACHINE_METADATA_H_ */
Property changes on: trunk/sys/mips/include/metadata.h
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Added: trunk/sys/mips/include/minidump.h
===================================================================
--- trunk/sys/mips/include/minidump.h (rev 0)
+++ trunk/sys/mips/include/minidump.h 2018-05-26 21:55:02 UTC (rev 9987)
@@ -0,0 +1,47 @@
+/* $MidnightBSD$ */
+/*-
+ * Copyright (c) 2006 Peter Wemm
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+ * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+ * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * $FreeBSD: stable/10/sys/mips/include/minidump.h 202175 2010-01-12 21:36:08Z imp $
+ */
+
+#ifndef _MACHINE_MINIDUMP_H_
+#define _MACHINE_MINIDUMP_H_ 1
+
+#define MINIDUMP_MAGIC "minidump FreeBSD/mips"
+#define MINIDUMP_VERSION 1
+
+struct minidumphdr {
+ char magic[24];
+ uint32_t version;
+ uint32_t msgbufsize;
+ uint32_t bitmapsize;
+ uint32_t ptesize;
+ uint64_t kernbase;
+ uint64_t dmapbase;
+ uint64_t dmapend;
+};
+
+#endif /* _MACHINE_MINIDUMP_H_ */
Property changes on: trunk/sys/mips/include/minidump.h
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Added: trunk/sys/mips/include/mips_opcode.h
===================================================================
--- trunk/sys/mips/include/mips_opcode.h (rev 0)
+++ trunk/sys/mips/include/mips_opcode.h 2018-05-26 21:55:02 UTC (rev 9987)
@@ -0,0 +1,424 @@
+/* $MidnightBSD$ */
+/* $OpenBSD: mips_opcode.h,v 1.2 1999/01/27 04:46:05 imp Exp $ */
+
+/*-
+ * Copyright (c) 1992, 1993
+ * The Regents of the University of California. All rights reserved.
+ *
+ * This code is derived from software contributed to Berkeley by
+ * Ralph Campbell.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * 4. Neither the name of the University nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ * from: @(#)mips_opcode.h 8.1 (Berkeley) 6/10/93
+ * JNPR: mips_opcode.h,v 1.1 2006/08/07 05:38:57 katta
+ * $FreeBSD: stable/10/sys/mips/include/mips_opcode.h 231312 2012-02-09 22:17:13Z gonzo $
+ */
+
+#ifndef _MACHINE_MIPS_OPCODE_H_
+#define _MACHINE_MIPS_OPCODE_H_
+
+/*
+ * Define the instruction formats and opcode values for the
+ * MIPS instruction set.
+ */
+#include <machine/endian.h>
+
+/*
+ * Define the instruction formats.
+ */
+typedef union {
+ unsigned word;
+
+#if BYTE_ORDER == BIG_ENDIAN
+ struct {
+ unsigned op: 6;
+ unsigned rs: 5;
+ unsigned rt: 5;
+ unsigned imm: 16;
+ } IType;
+
+ struct {
+ unsigned op: 6;
+ unsigned target: 26;
+ } JType;
+
+ struct {
+ unsigned op: 6;
+ unsigned rs: 5;
+ unsigned rt: 5;
+ unsigned rd: 5;
+ unsigned shamt: 5;
+ unsigned func: 6;
+ } RType;
+
+ struct {
+ unsigned op: 6; /* always '0x11' */
+ unsigned : 1; /* always '1' */
+ unsigned fmt: 4;
+ unsigned ft: 5;
+ unsigned fs: 5;
+ unsigned fd: 5;
+ unsigned func: 6;
+ } FRType;
+#endif
+#if BYTE_ORDER == LITTLE_ENDIAN
+ struct {
+ unsigned imm: 16;
+ unsigned rt: 5;
+ unsigned rs: 5;
+ unsigned op: 6;
+ } IType;
+
+ struct {
+ unsigned target: 26;
+ unsigned op: 6;
+ } JType;
+
+ struct {
+ unsigned func: 6;
+ unsigned shamt: 5;
+ unsigned rd: 5;
+ unsigned rt: 5;
+ unsigned rs: 5;
+ unsigned op: 6;
+ } RType;
+
+ struct {
+ unsigned func: 6;
+ unsigned fd: 5;
+ unsigned fs: 5;
+ unsigned ft: 5;
+ unsigned fmt: 4;
+ unsigned : 1; /* always '1' */
+ unsigned op: 6; /* always '0x11' */
+ } FRType;
+#endif
+} InstFmt;
+
+/* instruction field decoding macros */
+#define MIPS_INST_OPCODE(val) (val >> 26)
+#define MIPS_INST_RS(val) ((val & 0x03e00000) >> 21)
+#define MIPS_INST_RT(val) ((val & 0x001f0000) >> 16)
+#define MIPS_INST_IMM(val) ((val & 0x0000ffff))
+
+#define MIPS_INST_RD(val) ((val & 0x0000f800) >> 11)
+#define MIPS_INST_SA(val) ((val & 0x000007c0) >> 6)
+#define MIPS_INST_FUNC(val) (val & 0x0000003f)
+
+#define MIPS_INST_INDEX(val) (val & 0x03ffffff)
+
+/*
+ * the mips opcode and function table use a 3bit row and 3bit col
+ * number we define the following macro for easy transcribing
+ */
+
+#define MIPS_OPCODE(r, c) (((r & 0x07) << 3) | (c & 0x07))
+
+
+/*
+ * Values for the 'op' field.
+ */
+#define OP_SPECIAL 000
+#define OP_BCOND 001
+#define OP_J 002
+#define OP_JAL 003
+#define OP_BEQ 004
+#define OP_BNE 005
+#define OP_BLEZ 006
+#define OP_BGTZ 007
+
+#define OP_REGIMM OP_BCOND
+
+#define OP_ADDI 010
+#define OP_ADDIU 011
+#define OP_SLTI 012
+#define OP_SLTIU 013
+#define OP_ANDI 014
+#define OP_ORI 015
+#define OP_XORI 016
+#define OP_LUI 017
+
+#define OP_COP0 020
+#define OP_COP1 021
+#define OP_COP2 022
+#define OP_COP3 023
+#define OP_BEQL 024
+#define OP_BNEL 025
+#define OP_BLEZL 026
+#define OP_BGTZL 027
+
+#define OP_COP1X OP_COP3
+
+#define OP_DADDI 030
+#define OP_DADDIU 031
+#define OP_LDL 032
+#define OP_LDR 033
+
+#define OP_SPECIAL2 034
+#define OP_JALX 035
+
+#define OP_SPECIAL3 037
+
+#define OP_LB 040
+#define OP_LH 041
+#define OP_LWL 042
+#define OP_LW 043
+#define OP_LBU 044
+#define OP_LHU 045
+#define OP_LWR 046
+#define OP_LWU 047
+
+#define OP_SB 050
+#define OP_SH 051
+#define OP_SWL 052
+#define OP_SW 053
+#define OP_SDL 054
+#define OP_SDR 055
+#define OP_SWR 056
+#define OP_CACHE 057
+
+#define OP_LL 060
+#define OP_LWC1 061
+#define OP_LWC2 062
+#define OP_LWC3 063
+#define OP_LLD 064
+#define OP_LDC1 065
+#define OP_LDC2 066
+#define OP_LD 067
+
+#define OP_PREF OP_LWC3
+
+#define OP_SC 070
+#define OP_SWC1 071
+#define OP_SWC2 072
+#define OP_SWC3 073
+#define OP_SCD 074
+#define OP_SDC1 075
+#define OP_SDC2 076
+#define OP_SD 077
+
+/*
+ * Values for the 'func' field when 'op' == OP_SPECIAL.
+ */
+#define OP_SLL 000
+#define OP_MOVCI 001
+#define OP_SRL 002
+#define OP_SRA 003
+#define OP_SLLV 004
+#define OP_SRLV 006
+#define OP_SRAV 007
+
+#define OP_F_SLL OP_SLL
+#define OP_F_MOVCI OP_MOVCI
+#define OP_F_SRL OP_SRL
+#define OP_F_SRA OP_SRA
+#define OP_F_SLLV OP_SLLV
+#define OP_F_SRLV OP_SRLV
+#define OP_F_SRAV OP_SRAV
+
+#define OP_JR 010
+#define OP_JALR 011
+#define OP_MOVZ 012
+#define OP_MOVN 013
+#define OP_SYSCALL 014
+#define OP_BREAK 015
+#define OP_SYNC 017
+
+#define OP_F_JR OP_JR
+#define OP_F_JALR OP_JALR
+#define OP_F_MOVZ OP_MOVZ
+#define OP_F_MOVN OP_MOVN
+#define OP_F_SYSCALL OP_SYSCALL
+#define OP_F_BREAK OP_BREAK
+#define OP_F_SYNC OP_SYNC
+
+#define OP_MFHI 020
+#define OP_MTHI 021
+#define OP_MFLO 022
+#define OP_MTLO 023
+#define OP_DSLLV 024
+#define OP_DSRLV 026
+#define OP_DSRAV 027
+
+#define OP_F_MFHI OP_MFHI
+#define OP_F_MTHI OP_MTHI
+#define OP_F_MFLO OP_MFLO
+#define OP_F_MTLO OP_MTLO
+#define OP_F_DSLLV OP_DSLLV
+#define OP_F_DSRLV OP_DSRLV
+#define OP_F_DSRAV OP_DSRAV
+
+#define OP_MULT 030
+#define OP_MULTU 031
+#define OP_DIV 032
+#define OP_DIVU 033
+#define OP_DMULT 034
+#define OP_DMULTU 035
+#define OP_DDIV 036
+#define OP_DDIVU 037
+
+#define OP_F_MULT OP_MULT
+#define OP_F_MULTU OP_MULTU
+#define OP_F_DIV OP_DIV
+#define OP_F_DIVU OP_DIVU
+#define OP_F_DMULT OP_DMULT
+#define OP_F_DMULTU OP_DMULTU
+#define OP_F_DDIV OP_DDIV
+#define OP_F_DDIVU OP_DDIVU
+
+#define OP_ADD 040
+#define OP_ADDU 041
+#define OP_SUB 042
+#define OP_SUBU 043
+#define OP_AND 044
+#define OP_OR 045
+#define OP_XOR 046
+#define OP_NOR 047
+
+#define OP_F_ADD OP_ADD
+#define OP_F_ADDU OP_ADDU
+#define OP_F_SUB OP_SUB
+#define OP_F_SUBU OP_SUBU
+#define OP_F_AND OP_AND
+#define OP_F_OR OP_OR
+#define OP_F_XOR OP_XOR
+#define OP_F_NOR OP_NOR
+
+#define OP_SLT 052
+#define OP_SLTU 053
+#define OP_DADD 054
+#define OP_DADDU 055
+#define OP_DSUB 056
+#define OP_DSUBU 057
+
+#define OP_F_SLT OP_SLT
+#define OP_F_SLTU OP_SLTU
+#define OP_F_DADD OP_DADD
+#define OP_F_DADDU OP_DADDU
+#define OP_F_DSUB OP_DSUB
+#define OP_F_DSUBU OP_DSUBU
+
+#define OP_TGE 060
+#define OP_TGEU 061
+#define OP_TLT 062
+#define OP_TLTU 063
+#define OP_TEQ 064
+#define OP_TNE 066
+
+#define OP_F_TGE OP_TGE
+#define OP_F_TGEU OP_TGEU
+#define OP_F_TLT OP_TLT
+#define OP_F_TLTU OP_TLTU
+#define OP_F_TEQ OP_TEQ
+#define OP_F_TNE OP_TNE
+
+#define OP_DSLL 070
+#define OP_DSRL 072
+#define OP_DSRA 073
+#define OP_DSLL32 074
+#define OP_DSRL32 076
+#define OP_DSRA32 077
+
+#define OP_F_DSLL OP_DSLL
+#define OP_F_DSRL OP_DSRL
+#define OP_F_DSRA OP_DSRA
+#define OP_F_DSLL32 OP_DSLL32
+#define OP_F_DSRL32 OP_DSRL32
+#define OP_F_DSRA32 OP_DSRA32
+
+/*
+ * The REGIMM - register immediate instructions are further
+ * decoded using this table that has 2bit row numbers, hence
+ * a need for a new helper macro.
+ */
+
+#define MIPS_ROP(r, c) ((r & 0x03) << 3) | (c & 0x07)
+
+/*
+ * Values for the 'func' field when 'op' == OP_BCOND.
+ */
+#define OP_BLTZ 000
+#define OP_BGEZ 001
+#define OP_BLTZL 002
+#define OP_BGEZL 003
+
+#define OP_R_BLTZ OP_BLTZ
+#define OP_R_BGEZ OP_BGEZ
+#define OP_R_BLTZL OP_BLTZL
+#define OP_R_BGEZL OP_BGEZL
+
+#define OP_TGEI 010
+#define OP_TGEIU 011
+#define OP_TLTI 012
+#define OP_TLTIU 013
+#define OP_TEQI 014
+#define OP_TNEI 016
+
+#define OP_R_TGEI OP_TGEI
+#define OP_R_TGEIU OP_TGEIU
+#define OP_R_TLTI OP_TLTI
+#define OP_R_TLTIU OP_TLTIU
+#define OP_R_TEQI OP_TEQI
+#define OP_R_TNEI OP_TNEI
+
+#define OP_BLTZAL 020
+#define OP_BGEZAL 021
+#define OP_BLTZALL 022
+#define OP_BGEZALL 023
+
+#define OP_R_BLTZAL OP_BLTZAL
+#define OP_R_BGEZAL OP_BGEZAL
+#define OP_R_BLTZALL OP_BLTZALL
+#define OP_R_BGEZALL OP_BGEZALL
+
+/*
+ * Values for the 'func' field when 'op' == OP_SPECIAL3.
+ */
+#define OP_RDHWR 073
+
+/*
+ * Values for the 'rs' field when 'op' == OP_COPz.
+ */
+#define OP_MF 000
+#define OP_DMF 001
+#define OP_MT 004
+#define OP_DMT 005
+#define OP_BCx 010
+#define OP_BCy 014
+#define OP_CF 002
+#define OP_CT 006
+
+/*
+ * Values for the 'rt' field when 'op' == OP_COPz.
+ */
+#define COPz_BC_TF_MASK 0x01
+#define COPz_BC_TRUE 0x01
+#define COPz_BC_FALSE 0x00
+#define COPz_BCL_TF_MASK 0x02
+#define COPz_BCL_TRUE 0x02
+#define COPz_BCL_FALSE 0x00
+
+#endif /* !_MACHINE_MIPS_OPCODE_H_ */
Property changes on: trunk/sys/mips/include/mips_opcode.h
___________________________________________________________________
Added: svn:eol-style
## -0,0 +1 ##
+native
\ No newline at end of property
Added: svn:keywords
## -0,0 +1 ##
+MidnightBSD=%H
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+text/plain
\ No newline at end of property
Added: trunk/sys/mips/include/octeon_cop2.h
===================================================================
--- trunk/sys/mips/include/octeon_cop2.h (rev 0)
+++ trunk/sys/mips/include/octeon_cop2.h 2018-05-26 21:55:02 UTC (rev 9987)
@@ -0,0 +1,216 @@
+/* $MidnightBSD$ */
+/*-
+ * Copyright (c) 2011, Oleksandr Tymoshenko <gonzo at FreeBSD.org>
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice unmodified, this list of conditions, and the following
+ * disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ * $FreeBSD: stable/10/sys/mips/include/octeon_cop2.h 229677 2012-01-06 01:23:26Z gonzo $
+ *
+ */
+
+#ifndef __OCTEON_COP2_H__
+#define __OCTEON_COP2_H__
+
+/*
+ * COP2 registers of interest
+ */
+#define COP2_CRC_IV 0x201
+#define COP2_CRC_IV_SET COP2_CRC_IV
+#define COP2_CRC_LENGTH 0x202
+#define COP2_CRC_LENGTH_SET 0x1202
+#define COP2_CRC_POLY 0x200
+#define COP2_CRC_POLY_SET 0x4200
+#define COP2_LLM_DAT0 0x402
+#define COP2_LLM_DAT0_SET COP2_LLM_DAT0
+#define COP2_LLM_DAT1 0x40A
+#define COP2_LLM_DAT1_SET COP2_LLM_DAT1
+#define COP2_3DES_IV 0x084
+#define COP2_3DES_IV_SET COP2_3DES_IV
+#define COP2_3DES_KEY0 0x080
+#define COP2_3DES_KEY0_SET COP2_3DES_KEY0
+#define COP2_3DES_KEY1 0x081
+#define COP2_3DES_KEY1_SET COP2_3DES_KEY1
+#define COP2_3DES_KEY2 0x082
+#define COP2_3DES_KEY2_SET COP2_3DES_KEY2
+#define COP2_3DES_RESULT 0x088
+#define COP2_3DES_RESULT_SET 0x098
+#define COP2_AES_INP0 0x111
+#define COP2_AES_INP0_SET COP2_AES_INP0
+#define COP2_AES_IV0 0x102
+#define COP2_AES_IV0_SET COP2_AES_IV0
+#define COP2_AES_IV1 0x103
+#define COP2_AES_IV1_SET COP2_AES_IV1
+#define COP2_AES_KEY0 0x104
+#define COP2_AES_KEY0_SET COP2_AES_KEY0
+#define COP2_AES_KEY1 0x105
+#define COP2_AES_KEY1_SET COP2_AES_KEY1
+#define COP2_AES_KEY2 0x106
+#define COP2_AES_KEY2_SET COP2_AES_KEY2
+#define COP2_AES_KEY3 0x107
+#define COP2_AES_KEY3_SET COP2_AES_KEY3
+#define COP2_AES_KEYLEN 0x110
+#define COP2_AES_KEYLEN_SET COP2_AES_KEYLEN
+#define COP2_AES_RESULT0 0x100
+#define COP2_AES_RESULT0_SET COP2_AES_RESULT0
+#define COP2_AES_RESULT1 0x101
+#define COP2_AES_RESULT1_SET COP2_AES_RESULT1
+#define COP2_HSH_DATW0 0x240
+#define COP2_HSH_DATW0_SET COP2_HSH_DATW0
+#define COP2_HSH_DATW1 0x241
+#define COP2_HSH_DATW1_SET COP2_HSH_DATW1
+#define COP2_HSH_DATW2 0x242
+#define COP2_HSH_DATW2_SET COP2_HSH_DATW2
+#define COP2_HSH_DATW3 0x243
+#define COP2_HSH_DATW3_SET COP2_HSH_DATW3
+#define COP2_HSH_DATW4 0x244
+#define COP2_HSH_DATW4_SET COP2_HSH_DATW4
+#define COP2_HSH_DATW5 0x245
+#define COP2_HSH_DATW5_SET COP2_HSH_DATW5
+#define COP2_HSH_DATW6 0x246
+#define COP2_HSH_DATW6_SET COP2_HSH_DATW6
+#define COP2_HSH_DATW7 0x247
+#define COP2_HSH_DATW7_SET COP2_HSH_DATW7
+#define COP2_HSH_DATW8 0x248
+#define COP2_HSH_DATW8_SET COP2_HSH_DATW8
+#define COP2_HSH_DATW9 0x249
+#define COP2_HSH_DATW9_SET COP2_HSH_DATW9
+#define COP2_HSH_DATW10 0x24A
+#define COP2_HSH_DATW10_SET COP2_HSH_DATW10
+#define COP2_HSH_DATW11 0x24B
+#define COP2_HSH_DATW11_SET COP2_HSH_DATW11
+#define COP2_HSH_DATW12 0x24C
+#define COP2_HSH_DATW12_SET COP2_HSH_DATW12
+#define COP2_HSH_DATW13 0x24D
+#define COP2_HSH_DATW13_SET COP2_HSH_DATW13
+#define COP2_HSH_DATW14 0x24E
+#define COP2_HSH_DATW14_SET COP2_HSH_DATW14
+#define COP2_HSH_IVW0 0x250
+#define COP2_HSH_IVW0_SET COP2_HSH_IVW0
+#define COP2_HSH_IVW1 0x251
+#define COP2_HSH_IVW1_SET COP2_HSH_IVW1
+#define COP2_HSH_IVW2 0x252
+#define COP2_HSH_IVW2_SET COP2_HSH_IVW2
+#define COP2_HSH_IVW3 0x253
+#define COP2_HSH_IVW3_SET COP2_HSH_IVW3
+#define COP2_HSH_IVW4 0x254
+#define COP2_HSH_IVW4_SET COP2_HSH_IVW4
+#define COP2_HSH_IVW5 0x255
+#define COP2_HSH_IVW5_SET COP2_HSH_IVW5
+#define COP2_HSH_IVW6 0x256
+#define COP2_HSH_IVW6_SET COP2_HSH_IVW6
+#define COP2_HSH_IVW7 0x257
+#define COP2_HSH_IVW7_SET COP2_HSH_IVW7
+#define COP2_GFM_MULT0 0x258
+#define COP2_GFM_MULT0_SET COP2_GFM_MULT0
+#define COP2_GFM_MULT1 0x259
+#define COP2_GFM_MULT1_SET COP2_GFM_MULT1
+#define COP2_GFM_POLY 0x25E
+#define COP2_GFM_POLY_SET COP2_GFM_POLY
+#define COP2_GFM_RESULT0 0x25A
+#define COP2_GFM_RESULT0_SET COP2_GFM_RESULT0
+#define COP2_GFM_RESULT1 0x25B
+#define COP2_GFM_RESULT1_SET COP2_GFM_RESULT1
+#define COP2_HSH_DATW0_PASS1 0x040
+#define COP2_HSH_DATW0_PASS1_SET COP2_HSH_DATW0_PASS1
+#define COP2_HSH_DATW1_PASS1 0x041
+#define COP2_HSH_DATW1_PASS1_SET COP2_HSH_DATW1_PASS1
+#define COP2_HSH_DATW2_PASS1 0x042
+#define COP2_HSH_DATW2_PASS1_SET COP2_HSH_DATW2_PASS1
+#define COP2_HSH_DATW3_PASS1 0x043
+#define COP2_HSH_DATW3_PASS1_SET COP2_HSH_DATW3_PASS1
+#define COP2_HSH_DATW4_PASS1 0x044
+#define COP2_HSH_DATW4_PASS1_SET COP2_HSH_DATW4_PASS1
+#define COP2_HSH_DATW5_PASS1 0x045
+#define COP2_HSH_DATW5_PASS1_SET COP2_HSH_DATW5_PASS1
+#define COP2_HSH_DATW6_PASS1 0x046
+#define COP2_HSH_DATW6_PASS1_SET COP2_HSH_DATW6_PASS1
+#define COP2_HSH_IVW0_PASS1 0x048
+#define COP2_HSH_IVW0_PASS1_SET COP2_HSH_IVW0_PASS1
+#define COP2_HSH_IVW1_PASS1 0x049
+#define COP2_HSH_IVW1_PASS1_SET COP2_HSH_IVW1_PASS1
+#define COP2_HSH_IVW2_PASS1 0x04A
+#define COP2_HSH_IVW2_PASS1_SET COP2_HSH_IVW2_PASS1
+
+#ifndef LOCORE
+
+struct octeon_cop2_state {
+ /* 3DES */
+ /* 0x0084 */
+ unsigned long _3des_iv;
+ /* 0x0080..0x0082 */
+ unsigned long _3des_key[3];
+ /* 0x0088, set: 0x0098 */
+ unsigned long _3des_result;
+
+ /* AES */
+ /* 0x0111 */
+ unsigned long aes_inp0;
+ /* 0x0102..0x0103 */
+ unsigned long aes_iv[2];
+ /* 0x0104..0x0107 */
+ unsigned long aes_key[4];
+ /* 0x0110 */
+ unsigned long aes_keylen;
+ /* 0x0100..0x0101 */
+ unsigned long aes_result[2];
+
+ /* CRC */
+ /* 0x0201 */
+ unsigned long crc_iv;
+ /* 0x0202, set: 0x1202 */
+ unsigned long crc_length;
+ /* 0x0200, set: 0x4200 */
+ unsigned long crc_poly;
+
+ /* Low-latency memory stuff */
+ /* 0x0402, 0x040A */
+ unsigned long llm_dat[2];
+
+ /* SHA & MD5 */
+ /* 0x0240..0x024E */
+ unsigned long hsh_datw[15];
+ /* 0x0250..0x0257 */
+ unsigned long hsh_ivw[8];
+
+ /* GFM */
+ /* 0x0258..0x0259 */
+ unsigned long gfm_mult[2];
+ /* 0x025E */
+ unsigned long gfm_poly;
+ /* 0x025A..0x025B */
+ unsigned long gfm_result[2];
+};
+
+/* Prototypes */
+
+struct octeon_cop2_state* octeon_cop2_alloc_ctx(void);
+void octeon_cop2_free_ctx(struct octeon_cop2_state *);
+/*
+ * Save/restore part
+ */
+void octeon_cop2_save(struct octeon_cop2_state *);
+void octeon_cop2_restore(struct octeon_cop2_state *);
+
+#endif /* LOCORE */
+#endif /* __OCTEON_COP2_H__ */
Property changes on: trunk/sys/mips/include/octeon_cop2.h
___________________________________________________________________
Added: svn:eol-style
## -0,0 +1 ##
+native
\ No newline at end of property
Added: svn:keywords
## -0,0 +1 ##
+MidnightBSD=%H
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+text/plain
\ No newline at end of property
Added: trunk/sys/mips/include/ofw_machdep.h
===================================================================
--- trunk/sys/mips/include/ofw_machdep.h (rev 0)
+++ trunk/sys/mips/include/ofw_machdep.h 2018-05-26 21:55:02 UTC (rev 9987)
@@ -0,0 +1,49 @@
+/* $MidnightBSD$ */
+/*-
+ * Copyright (c) 2001 by Thomas Moestl <tmm at FreeBSD.org>.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+ * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+ * IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
+ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
+ * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * $FreeBSD: stable/10/sys/mips/include/ofw_machdep.h 226496 2011-10-18 07:29:21Z jchandra $
+ */
+
+#ifndef _MACHINE_OFW_MACHDEP_H_
+#define _MACHINE_OFW_MACHDEP_H_
+
+#include <sys/cdefs.h>
+#include <sys/types.h>
+#include <sys/rman.h>
+#include <sys/bus.h>
+#include <dev/ofw/openfirm.h>
+
+typedef uint32_t cell_t;
+struct mem_region {
+ vm_offset_t mr_start;
+ vm_size_t mr_size;
+};
+
+
+int OF_decode_addr(phandle_t, int, bus_space_tag_t *, bus_space_handle_t *);
+void OF_getetheraddr(device_t dev, u_char *addr);
+void OF_initial_setup(void *fdt_ptr, void *junk, int (*openfirm)(void *));
+
+#endif /* _MACHINE_OFW_MACHDEP_H_ */
Property changes on: trunk/sys/mips/include/ofw_machdep.h
___________________________________________________________________
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+MidnightBSD=%H
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+text/plain
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Added: trunk/sys/mips/include/param.h
===================================================================
--- trunk/sys/mips/include/param.h (rev 0)
+++ trunk/sys/mips/include/param.h 2018-05-26 21:55:02 UTC (rev 9987)
@@ -0,0 +1,186 @@
+/* $MidnightBSD$ */
+/* $OpenBSD: param.h,v 1.11 1998/08/30 22:05:35 millert Exp $ */
+
+/*-
+ * Copyright (c) 1988 University of Utah.
+ * Copyright (c) 1992, 1993
+ * The Regents of the University of California. All rights reserved.
+ *
+ * This code is derived from software contributed to Berkeley by
+ * the Systems Programming Group of the University of Utah Computer
+ * Science Department and Ralph Campbell.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * 4. Neither the name of the University nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ * from: Utah Hdr: machparam.h 1.11 89/08/14
+ * from: @(#)param.h 8.1 (Berkeley) 6/10/93
+ * JNPR: param.h,v 1.6.2.1 2007/09/10 07:49:36 girish
+ * $FreeBSD: stable/10/sys/mips/include/param.h 274648 2014-11-18 12:53:32Z kib $
+ */
+
+#ifndef _MIPS_INCLUDE_PARAM_H_
+#define _MIPS_INCLUDE_PARAM_H_
+
+#include <machine/_align.h>
+
+#include <sys/cdefs.h>
+#ifdef _KERNEL
+#ifndef _LOCORE
+#include <machine/cpu.h>
+#endif
+#endif
+
+#define __PCI_REROUTE_INTERRUPT
+
+#ifndef MACHINE
+#define MACHINE "mips"
+#endif
+#ifndef MACHINE_ARCH
+#if _BYTE_ORDER == _BIG_ENDIAN
+#ifdef __mips_n64
+#define MACHINE_ARCH "mips64"
+#ifndef MACHINE_ARCH32
+#define MACHINE_ARCH32 "mips"
+#endif
+#elif defined(__mips_n32)
+#define MACHINE_ARCH "mipsn32"
+#else
+#define MACHINE_ARCH "mips"
+#endif
+#else
+#ifdef __mips_n64
+#define MACHINE_ARCH "mips64el"
+#ifndef MACHINE_ARCH32
+#define MACHINE_ARCH32 "mipsel"
+#endif
+#elif defined(__mips_n32)
+#define MACHINE_ARCH "mipsn32el"
+#else
+#define MACHINE_ARCH "mipsel"
+#endif
+#endif
+#endif
+
+/*
+ * OBJFORMAT_NAMES is a comma-separated list of the object formats
+ * that are supported on the architecture.
+ */
+#define OBJFORMAT_NAMES "elf"
+#define OBJFORMAT_DEFAULT "elf"
+
+#define MID_MACHINE 0 /* None but has to be defined */
+
+#ifdef SMP
+#define MAXSMPCPU 32
+#ifndef MAXCPU
+#define MAXCPU MAXSMPCPU
+#endif
+#else
+#define MAXSMPCPU 1
+#define MAXCPU 1
+#endif
+
+#ifndef MAXMEMDOM
+#define MAXMEMDOM 1
+#endif
+
+/*
+ * Round p (pointer or byte index) up to a correctly-aligned value for all
+ * data types (int, long, ...). The result is u_int and must be cast to
+ * any desired pointer type.
+ */
+
+#define ALIGNBYTES _ALIGNBYTES
+#define ALIGN(p) _ALIGN(p)
+/*
+ * ALIGNED_POINTER is a boolean macro that checks whether an address
+ * is valid to fetch data elements of type t from on this architecture.
+ * This does not reflect the optimal alignment, just the possibility
+ * (within reasonable limits).
+ */
+#define ALIGNED_POINTER(p, t) ((((unsigned long)(p)) & (sizeof (t) - 1)) == 0)
+
+/*
+ * CACHE_LINE_SIZE is the compile-time maximum cache line size for an
+ * architecture. It should be used with appropriate caution.
+ */
+#define CACHE_LINE_SHIFT 6
+#define CACHE_LINE_SIZE (1 << CACHE_LINE_SHIFT)
+
+#define PAGE_SHIFT 12 /* LOG2(PAGE_SIZE) */
+#define PAGE_SIZE (1<<PAGE_SHIFT) /* bytes/page */
+#define PAGE_MASK (PAGE_SIZE-1)
+
+#define NPTEPG (PAGE_SIZE/(sizeof (pt_entry_t)))
+#define NPDEPG (PAGE_SIZE/(sizeof (pd_entry_t)))
+
+#if defined(__mips_n32) || defined(__mips_n64) /* PHYSADDR_64_BIT */
+#define NPTEPGSHIFT 9 /* LOG2(NPTEPG) */
+#else
+#define NPTEPGSHIFT 10 /* LOG2(NPTEPG) */
+#endif
+
+#ifdef __mips_n64
+#define NPDEPGSHIFT 9 /* LOG2(NPTEPG) */
+#define SEGSHIFT (PAGE_SHIFT + NPTEPGSHIFT + NPDEPGSHIFT)
+#define NBSEG (1ul << SEGSHIFT)
+#define PDRSHIFT (PAGE_SHIFT + NPTEPGSHIFT)
+#define PDRMASK ((1 << PDRSHIFT) - 1)
+#else
+#define NPDEPGSHIFT 10 /* LOG2(NPTEPG) */
+#define SEGSHIFT (PAGE_SHIFT + NPTEPGSHIFT)
+#define NBSEG (1 << SEGSHIFT) /* bytes/segment */
+#define PDRSHIFT SEGSHIFT /* alias for SEG in 32 bit */
+#define PDRMASK ((1 << PDRSHIFT) - 1)
+#endif
+#define NBPDR (1 << PDRSHIFT) /* bytes/pagedir */
+#define SEGMASK (NBSEG - 1) /* byte offset into segment */
+
+#define MAXPAGESIZES 1 /* max supported pagesizes */
+
+#define MAXDUMPPGS 1 /* xxx: why is this only one? */
+
+/*
+ * The kernel stack needs to be aligned on a (PAGE_SIZE * 2) boundary.
+ */
+#define KSTACK_PAGES 2 /* kernel stack */
+#define KSTACK_GUARD_PAGES 2 /* pages of kstack guard; 0 disables */
+
+/*
+ * Mach derived conversion macros
+ */
+#define round_page(x) (((x) + PAGE_MASK) & ~PAGE_MASK)
+#define trunc_page(x) ((x) & ~PAGE_MASK)
+
+#define atop(x) ((x) >> PAGE_SHIFT)
+#define ptoa(x) ((x) << PAGE_SHIFT)
+
+#define pgtok(x) ((x) * (PAGE_SIZE / 1024))
+
+#ifdef _KERNEL
+#define NO_FUEWORD 1
+#endif
+
+#endif /* !_MIPS_INCLUDE_PARAM_H_ */
Property changes on: trunk/sys/mips/include/param.h
___________________________________________________________________
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Added: trunk/sys/mips/include/pcb.h
===================================================================
--- trunk/sys/mips/include/pcb.h (rev 0)
+++ trunk/sys/mips/include/pcb.h 2018-05-26 21:55:02 UTC (rev 9987)
@@ -0,0 +1,86 @@
+/* $MidnightBSD$ */
+/* $OpenBSD: pcb.h,v 1.3 1998/09/15 10:50:12 pefo Exp $ */
+
+/*-
+ * Copyright (c) 1988 University of Utah.
+ * Copyright (c) 1992, 1993
+ * The Regents of the University of California. All rights reserved.
+ *
+ * This code is derived from software contributed to Berkeley by
+ * the Systems Programming Group of the University of Utah Computer
+ * Science Department and Ralph Campbell.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * 4. Neither the name of the University nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ * from: Utah Hdr: pcb.h 1.13 89/04/23
+ * from: @(#)pcb.h 8.1 (Berkeley) 6/10/93
+ * JNPR: pcb.h,v 1.2 2006/08/07 11:51:17 katta
+ * $FreeBSD: stable/10/sys/mips/include/pcb.h 249882 2013-04-25 06:29:23Z imp $
+ */
+
+#ifndef _MACHINE_PCB_H_
+#define _MACHINE_PCB_H_
+
+/*
+ * used by switch.S
+ */
+#define PCB_REG_S0 0
+#define PCB_REG_S1 1
+#define PCB_REG_S2 2
+#define PCB_REG_S3 3
+#define PCB_REG_S4 4
+#define PCB_REG_S5 5
+#define PCB_REG_S6 6
+#define PCB_REG_S7 7
+#define PCB_REG_SP 8
+#define PCB_REG_S8 9
+#define PCB_REG_RA 10
+#define PCB_REG_SR 11
+#define PCB_REG_GP 12
+#define PCB_REG_PC 13
+
+#ifndef LOCORE
+#include <machine/frame.h>
+
+/*
+ * MIPS process control block
+ */
+struct pcb
+{
+ struct trapframe pcb_regs; /* saved CPU and registers */
+ __register_t pcb_context[14]; /* kernel context for resume */
+ void *pcb_onfault; /* for copyin/copyout faults */
+ register_t pcb_tpc;
+};
+
+#ifdef _KERNEL
+extern struct pcb *curpcb; /* the current running pcb */
+
+void makectx(struct trapframe *, struct pcb *);
+int savectx(struct pcb *) __returns_twice;
+#endif
+#endif
+
+#endif /* !_MACHINE_PCB_H_ */
Property changes on: trunk/sys/mips/include/pcb.h
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Added: trunk/sys/mips/include/pcpu.h
===================================================================
--- trunk/sys/mips/include/pcpu.h (rev 0)
+++ trunk/sys/mips/include/pcpu.h 2018-05-26 21:55:02 UTC (rev 9987)
@@ -0,0 +1,85 @@
+/* $MidnightBSD$ */
+/*-
+ * Copyright (c) 1999 Luoqi Chen <luoqi at freebsd.org>
+ * Copyright (c) Peter Wemm <peter at netplex.com.au>
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ * from: src/sys/alpha/include/pcpu.h,v 1.15 2004/11/05 19:16:44 jhb
+ * $FreeBSD: stable/10/sys/mips/include/pcpu.h 290080 2015-10-27 22:57:58Z jhb $
+ */
+
+#ifndef _MACHINE_PCPU_H_
+#define _MACHINE_PCPU_H_
+
+#include <machine/cpufunc.h>
+#include <machine/pte.h>
+
+#define PCPU_MD_COMMON_FIELDS \
+ pd_entry_t *pc_segbase; /* curthread segbase */ \
+ struct pmap *pc_curpmap; /* pmap of curthread */ \
+ u_int32_t pc_next_asid; /* next ASID to alloc */ \
+ u_int32_t pc_asid_generation; /* current ASID generation */ \
+ u_int pc_pending_ipis; /* IPIs pending to this CPU */
+
+#ifdef __mips_n64
+#define PCPU_MD_MIPS64_FIELDS \
+ PCPU_MD_COMMON_FIELDS \
+ char __pad[61]
+#else
+#define PCPU_MD_MIPS32_FIELDS \
+ PCPU_MD_COMMON_FIELDS \
+ char __pad[133]
+#endif
+
+#ifdef __mips_n64
+#define PCPU_MD_FIELDS PCPU_MD_MIPS64_FIELDS
+#else
+#define PCPU_MD_FIELDS PCPU_MD_MIPS32_FIELDS
+#endif
+
+#ifdef _KERNEL
+
+extern char pcpu_space[MAXCPU][PAGE_SIZE * 2];
+#define PCPU_ADDR(cpu) (struct pcpu *)(pcpu_space[(cpu)])
+
+extern struct pcpu *pcpup;
+#define PCPUP pcpup
+
+#define PCPU_ADD(member, value) (PCPUP->pc_ ## member += (value))
+#define PCPU_GET(member) (PCPUP->pc_ ## member)
+#define PCPU_INC(member) PCPU_ADD(member, 1)
+#define PCPU_PTR(member) (&PCPUP->pc_ ## member)
+#define PCPU_SET(member,value) (PCPUP->pc_ ## member = (value))
+#define PCPU_LAZY_INC(member) (++PCPUP->pc_ ## member)
+
+#ifdef SMP
+/*
+ * Instantiate the wired TLB entry at PCPU_TLB_ENTRY to map 'pcpu' at 'pcpup'.
+ */
+void mips_pcpu_tlb_init(struct pcpu *pcpu);
+#endif
+
+#endif /* _KERNEL */
+
+#endif /* !_MACHINE_PCPU_H_ */
Property changes on: trunk/sys/mips/include/pcpu.h
___________________________________________________________________
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Added: trunk/sys/mips/include/pmap.h
===================================================================
--- trunk/sys/mips/include/pmap.h (rev 0)
+++ trunk/sys/mips/include/pmap.h 2018-05-26 21:55:02 UTC (rev 9987)
@@ -0,0 +1,188 @@
+/* $MidnightBSD$ */
+/*-
+ * Copyright (c) 1991 Regents of the University of California.
+ * All rights reserved.
+ *
+ * This code is derived from software contributed to Berkeley by
+ * the Systems Programming Group of the University of Utah Computer
+ * Science Department and William Jolitz of UUNET Technologies Inc.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * 4. Neither the name of the University nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ * Derived from hp300 version by Mike Hibler, this version by William
+ * Jolitz uses a recursive map [a pde points to the page directory] to
+ * map the page tables using the pagetables themselves. This is done to
+ * reduce the impact on kernel virtual memory for lots of sparse address
+ * space, and to reduce the cost of memory to each process.
+ *
+ * from: hp300: @(#)pmap.h 7.2 (Berkeley) 12/16/90
+ * from: @(#)pmap.h 7.4 (Berkeley) 5/12/91
+ * from: src/sys/i386/include/pmap.h,v 1.65.2.2 2000/11/30 01:54:42 peter
+ * JNPR: pmap.h,v 1.7.2.1 2007/09/10 07:44:12 girish
+ * $FreeBSD: stable/10/sys/mips/include/pmap.h 243030 2012-11-14 17:33:00Z alc $
+ */
+
+#ifndef _MACHINE_PMAP_H_
+#define _MACHINE_PMAP_H_
+
+#include <machine/vmparam.h>
+#include <machine/pte.h>
+
+#if defined(__mips_n32) || defined(__mips_n64) /* PHYSADDR_64BIT */
+#define NKPT 256 /* mem > 4G, vm_page_startup needs more KPTs */
+#else
+#define NKPT 120 /* actual number of kernel page tables */
+#endif
+
+#ifndef LOCORE
+
+#include <sys/queue.h>
+#include <sys/_cpuset.h>
+#include <sys/_lock.h>
+#include <sys/_mutex.h>
+
+/*
+ * Pmap stuff
+ */
+struct pv_entry;
+struct pv_chunk;
+
+struct md_page {
+ int pv_flags;
+ TAILQ_HEAD(, pv_entry) pv_list;
+};
+
+#define PV_TABLE_REF 0x02 /* referenced */
+
+#define ASID_BITS 8
+#define ASIDGEN_BITS (32 - ASID_BITS)
+#define ASIDGEN_MASK ((1 << ASIDGEN_BITS) - 1)
+
+struct pmap {
+ pd_entry_t *pm_segtab; /* KVA of segment table */
+ TAILQ_HEAD(, pv_chunk) pm_pvchunk; /* list of mappings in pmap */
+ cpuset_t pm_active; /* active on cpus */
+ struct {
+ u_int32_t asid:ASID_BITS; /* TLB address space tag */
+ u_int32_t gen:ASIDGEN_BITS; /* its generation number */
+ } pm_asid[MAXSMPCPU];
+ struct pmap_statistics pm_stats; /* pmap statistics */
+ struct mtx pm_mtx;
+};
+
+typedef struct pmap *pmap_t;
+
+#ifdef _KERNEL
+
+pt_entry_t *pmap_pte(pmap_t, vm_offset_t);
+vm_paddr_t pmap_kextract(vm_offset_t va);
+
+#define vtophys(va) pmap_kextract(((vm_offset_t) (va)))
+#define pmap_asid(pmap) (pmap)->pm_asid[PCPU_GET(cpuid)].asid
+
+extern struct pmap kernel_pmap_store;
+#define kernel_pmap (&kernel_pmap_store)
+
+#define PMAP_LOCK(pmap) mtx_lock(&(pmap)->pm_mtx)
+#define PMAP_LOCK_ASSERT(pmap, type) mtx_assert(&(pmap)->pm_mtx, (type))
+#define PMAP_LOCK_DESTROY(pmap) mtx_destroy(&(pmap)->pm_mtx)
+#define PMAP_LOCK_INIT(pmap) mtx_init(&(pmap)->pm_mtx, "pmap", \
+ NULL, MTX_DEF)
+#define PMAP_LOCKED(pmap) mtx_owned(&(pmap)->pm_mtx)
+#define PMAP_MTX(pmap) (&(pmap)->pm_mtx)
+#define PMAP_TRYLOCK(pmap) mtx_trylock(&(pmap)->pm_mtx)
+#define PMAP_UNLOCK(pmap) mtx_unlock(&(pmap)->pm_mtx)
+
+/*
+ * For each vm_page_t, there is a list of all currently valid virtual
+ * mappings of that page. An entry is a pv_entry_t, the list is pv_table.
+ */
+typedef struct pv_entry {
+ vm_offset_t pv_va; /* virtual address for mapping */
+ TAILQ_ENTRY(pv_entry) pv_list;
+} *pv_entry_t;
+
+/*
+ * pv_entries are allocated in chunks per-process. This avoids the
+ * need to track per-pmap assignments.
+ */
+#ifdef __mips_n64
+#define _NPCM 3
+#define _NPCPV 168
+#else
+#define _NPCM 11
+#define _NPCPV 336
+#endif
+struct pv_chunk {
+ pmap_t pc_pmap;
+ TAILQ_ENTRY(pv_chunk) pc_list;
+ u_long pc_map[_NPCM]; /* bitmap; 1 = free */
+ TAILQ_ENTRY(pv_chunk) pc_lru;
+ struct pv_entry pc_pventry[_NPCPV];
+};
+
+/*
+ * physmem_desc[] is a superset of phys_avail[] and describes all the
+ * memory present in the system.
+ *
+ * phys_avail[] is similar but does not include the memory stolen by
+ * pmap_steal_memory().
+ *
+ * Each memory region is described by a pair of elements in the array
+ * so we can describe up to (PHYS_AVAIL_ENTRIES / 2) distinct memory
+ * regions.
+ */
+#define PHYS_AVAIL_ENTRIES 10
+extern vm_paddr_t phys_avail[PHYS_AVAIL_ENTRIES + 2];
+extern vm_paddr_t physmem_desc[PHYS_AVAIL_ENTRIES + 2];
+
+extern vm_offset_t virtual_avail;
+extern vm_offset_t virtual_end;
+
+extern vm_paddr_t dump_avail[PHYS_AVAIL_ENTRIES + 2];
+
+#define pmap_page_get_memattr(m) VM_MEMATTR_DEFAULT
+#define pmap_page_is_mapped(m) (!TAILQ_EMPTY(&(m)->md.pv_list))
+#define pmap_page_is_write_mapped(m) (((m)->aflags & PGA_WRITEABLE) != 0)
+#define pmap_page_set_memattr(m, ma) (void)0
+
+void pmap_bootstrap(void);
+void *pmap_mapdev(vm_paddr_t, vm_size_t);
+void pmap_unmapdev(vm_offset_t, vm_size_t);
+vm_offset_t pmap_steal_memory(vm_size_t size);
+void pmap_kenter(vm_offset_t va, vm_paddr_t pa);
+void pmap_kenter_attr(vm_offset_t va, vm_paddr_t pa, int attr);
+void pmap_kremove(vm_offset_t va);
+void *pmap_kenter_temporary(vm_paddr_t pa, int i);
+void pmap_kenter_temporary_free(vm_paddr_t pa);
+void pmap_flush_pvcache(vm_page_t m);
+int pmap_emulate_modified(pmap_t pmap, vm_offset_t va);
+void pmap_grow_direct_page_cache(void);
+
+#endif /* _KERNEL */
+
+#endif /* !LOCORE */
+
+#endif /* !_MACHINE_PMAP_H_ */
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Added: trunk/sys/mips/include/pmc_mdep.h
===================================================================
--- trunk/sys/mips/include/pmc_mdep.h (rev 0)
+++ trunk/sys/mips/include/pmc_mdep.h 2018-05-26 21:55:02 UTC (rev 9987)
@@ -0,0 +1,81 @@
+/* $MidnightBSD$ */
+/*-
+ * This file is in the public domain.
+ *
+ * from: src/sys/alpha/include/pmc_mdep.h,v 1.2 2005/06/09 19:45:06 jkoshy
+ * $FreeBSD: stable/10/sys/mips/include/pmc_mdep.h 233628 2012-03-28 20:58:30Z fabient $
+ */
+
+#ifndef _MACHINE_PMC_MDEP_H_
+#define _MACHINE_PMC_MDEP_H_
+
+#define PMC_MDEP_CLASS_INDEX_MIPS 1
+
+union pmc_md_op_pmcallocate {
+ uint64_t __pad[4];
+};
+
+/* Logging */
+#if defined(__mips_n64)
+#define PMCLOG_READADDR PMCLOG_READ64
+#define PMCLOG_EMITADDR PMCLOG_EMIT64
+#else
+#define PMCLOG_READADDR PMCLOG_READ32
+#define PMCLOG_EMITADDR PMCLOG_EMIT32
+#endif
+
+#if _KERNEL
+
+/*
+ * MIPS event codes are encoded with a select bit. The
+ * select bit is used when writing to CP0 so that we
+ * can select either counter 0/2 or 1/3. The cycle
+ * and instruction counters are special in that they
+ * can be counted on either 0/2 or 1/3.
+ */
+
+#define MIPS_CTR_ALL 255 /* Count events in any counter. */
+#define MIPS_CTR_0 0 /* Counter 0 Event */
+#define MIPS_CTR_1 1 /* Counter 1 Event */
+
+struct mips_event_code_map {
+ uint32_t pe_ev; /* enum value */
+ uint8_t pe_counter; /* Which counter this can be counted in. */
+ uint8_t pe_code; /* numeric code */
+};
+
+struct mips_pmc_spec {
+ uint32_t ps_cpuclass;
+ uint32_t ps_cputype;
+ uint32_t ps_capabilities;
+ int ps_counter_width;
+};
+
+union pmc_md_pmc {
+ uint32_t pm_mips_evsel;
+};
+
+#define PMC_TRAPFRAME_TO_PC(TF) ((TF)->pc)
+
+extern const struct mips_event_code_map mips_event_codes[];
+extern const int mips_event_codes_size;
+extern int mips_npmcs;
+extern struct mips_pmc_spec mips_pmc_spec;
+
+/*
+ * Prototypes
+ */
+struct pmc_mdep *pmc_mips_initialize(void);
+void pmc_mips_finalize(struct pmc_mdep *_md);
+
+/*
+ * CPU-specific functions
+ */
+
+uint32_t mips_get_perfctl(int cpu, int ri, uint32_t event, uint32_t caps);
+uint64_t mips_pmcn_read(unsigned int pmc);
+uint64_t mips_pmcn_write(unsigned int pmc, uint64_t v);
+
+#endif /* _KERNEL */
+
+#endif /* !_MACHINE_PMC_MDEP_H_ */
Property changes on: trunk/sys/mips/include/pmc_mdep.h
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Added: trunk/sys/mips/include/proc.h
===================================================================
--- trunk/sys/mips/include/proc.h (rev 0)
+++ trunk/sys/mips/include/proc.h 2018-05-26 21:55:02 UTC (rev 9987)
@@ -0,0 +1,100 @@
+/* $MidnightBSD$ */
+/* $OpenBSD: proc.h,v 1.2 1998/09/15 10:50:12 pefo Exp $ */
+
+/*-
+ * Copyright (c) 1992, 1993
+ * The Regents of the University of California. All rights reserved.
+ *
+ * This code is derived from software contributed to Berkeley by
+ * Ralph Campbell.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * 4. Neither the name of the University nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ * @(#)proc.h 8.1 (Berkeley) 6/10/93
+ * JNPR: proc.h,v 1.7.2.1 2007/09/10 06:25:24 girish
+ * $FreeBSD: stable/10/sys/mips/include/proc.h 232855 2012-03-12 08:13:04Z jmallett $
+ */
+
+#ifndef _MACHINE_PROC_H_
+#define _MACHINE_PROC_H_
+
+#ifdef CPU_CNMIPS
+#include <machine/octeon_cop2.h>
+#endif
+
+/*
+ * Machine-dependent part of the proc structure.
+ */
+struct mdthread {
+ int md_flags; /* machine-dependent flags */
+#if defined(__mips_n64) || defined(__mips_n32) /* PHYSADDR_64_BIT */
+ uint64_t md_upte[KSTACK_PAGES]; /* ptes for mapping u pcb */
+#else
+ int md_upte[KSTACK_PAGES];
+#endif
+ int md_ss_addr; /* single step address for ptrace */
+ int md_ss_instr; /* single step instruction for ptrace */
+ register_t md_saved_intr;
+ u_int md_spinlock_count;
+/* The following is CPU dependent, but kept in for compatibility */
+ int md_pc_ctrl; /* performance counter control */
+ int md_pc_count; /* performance counter */
+ int md_pc_spill; /* performance counter spill */
+ void *md_tls;
+#ifdef CPU_CNMIPS
+ struct octeon_cop2_state *md_cop2; /* kernel context */
+ struct octeon_cop2_state *md_ucop2; /* userland context */
+#define COP2_OWNER_USERLAND 0x0000 /* Userland owns COP2 */
+#define COP2_OWNER_KERNEL 0x0001 /* Kernel owns COP2 */
+ int md_cop2owner;
+#endif
+};
+
+/* md_flags */
+#define MDTD_FPUSED 0x0001 /* Process used the FPU */
+#define MDTD_COP2USED 0x0002 /* Process used the COP2 */
+
+struct mdproc {
+ /* empty */
+};
+
+#ifdef _KERNEL
+struct syscall_args {
+ u_int code;
+ struct sysent *callp;
+ register_t args[8];
+ int narg;
+ struct trapframe *trapframe;
+};
+#endif
+
+#ifdef __mips_n64
+#define KINFO_PROC_SIZE 1088
+#define KINFO_PROC32_SIZE 816
+#else
+#define KINFO_PROC_SIZE 816
+#endif
+
+#endif /* !_MACHINE_PROC_H_ */
Property changes on: trunk/sys/mips/include/proc.h
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Added: trunk/sys/mips/include/profile.h
===================================================================
--- trunk/sys/mips/include/profile.h (rev 0)
+++ trunk/sys/mips/include/profile.h 2018-05-26 21:55:02 UTC (rev 9987)
@@ -0,0 +1,183 @@
+/* $MidnightBSD$ */
+/* $OpenBSD: profile.h,v 1.2 1999/01/27 04:46:05 imp Exp $ */
+/*-
+ * Copyright (c) 1992, 1993
+ * The Regents of the University of California. All rights reserved.
+ *
+ * This code is derived from software contributed to Berkeley by
+ * Ralph Campbell.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * 4. Neither the name of the University nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ * from: @(#)profile.h 8.1 (Berkeley) 6/10/93
+ * JNPR: profile.h,v 1.4 2006/12/02 09:53:41 katta
+ * $FreeBSD: stable/10/sys/mips/include/profile.h 210606 2010-07-29 14:04:29Z jchandra $
+ */
+#ifndef _MACHINE_PROFILE_H_
+#define _MACHINE_PROFILE_H_
+
+#define _MCOUNT_DECL void ___mcount
+
+/*XXX The cprestore instruction is a "dummy" to shut up as(1). */
+
+/*XXX This is not MIPS64 safe. */
+
+#define MCOUNT \
+ __asm(".globl _mcount;" \
+ ".type _mcount, at function;" \
+ "_mcount:;" \
+ ".set noreorder;" \
+ ".set noat;" \
+ ".cpload $25;" \
+ ".cprestore 4;" \
+ "sw $4,8($29);" \
+ "sw $5,12($29);" \
+ "sw $6,16($29);" \
+ "sw $7,20($29);" \
+ "sw $1,0($29);" \
+ "sw $31,4($29);" \
+ "move $5,$31;" \
+ "jal ___mcount;" \
+ "move $4,$1;" \
+ "lw $4,8($29);" \
+ "lw $5,12($29);" \
+ "lw $6,16($29);" \
+ "lw $7,20($29);" \
+ "lw $31,4($29);" \
+ "lw $1,0($29);" \
+ "addu $29,$29,8;" \
+ "j $31;" \
+ "move $31,$1;" \
+ ".set reorder;" \
+ ".set at");
+
+#ifdef _KERNEL
+/*
+ * The following two macros do splhigh and splx respectively.
+ * They have to be defined this way because these are real
+ * functions on the MIPS, and we do not want to invoke mcount
+ * recursively.
+ */
+
+#define MCOUNT_DECL(s) u_long s;
+#ifdef SMP
+extern int mcount_lock;
+#define MCOUNT_ENTER(s) { \
+ s = intr_disable(); \
+ while (!atomic_cmpset_acq_int(&mcount_lock, 0, 1)) \
+ /* nothing */ ; \
+}
+#define MCOUNT_EXIT(s) { \
+ atomic_store_rel_int(&mcount_lock, 0); \
+ intr_restore(s); \
+}
+#else
+#define MCOUNT_ENTER(s) { s = intr_disable(); }
+#define MCOUNT_EXIT(s) (intr_restore(s))
+#endif
+
+/* REVISIT for mips */
+/*
+ * Config generates something to tell the compiler to align functions on 16
+ * byte boundaries. A strict alignment is good for keeping the tables small.
+ */
+#define FUNCTION_ALIGNMENT 16
+
+#ifdef GUPROF
+struct gmonparam;
+void stopguprof __P((struct gmonparam *p));
+#else
+#define stopguprof(p)
+#endif /* GUPROF */
+
+#else /* !_KERNEL */
+
+#define FUNCTION_ALIGNMENT 4
+
+#ifdef __mips_n64
+typedef u_long uintfptr_t;
+#else
+typedef u_int uintfptr_t;
+#endif
+
+#endif /* _KERNEL */
+
+/*
+ * An unsigned integral type that can hold non-negative difference between
+ * function pointers.
+ */
+#ifdef __mips_n64
+typedef u_long fptrdiff_t;
+#else
+typedef u_int fptrdiff_t;
+#endif
+
+#ifdef _KERNEL
+
+void mcount(uintfptr_t frompc, uintfptr_t selfpc);
+
+#ifdef GUPROF
+struct gmonparam;
+
+void nullfunc_loop_profiled(void);
+void nullfunc_profiled(void);
+void startguprof(struct gmonparam *p);
+void stopguprof(struct gmonparam *p);
+#else
+#define startguprof(p)
+#define stopguprof(p)
+#endif /* GUPROF */
+
+#else /* !_KERNEL */
+
+#include <sys/cdefs.h>
+
+__BEGIN_DECLS
+#ifdef __GNUC__
+#ifdef __ELF__
+void mcount(void) __asm(".mcount");
+#else
+void mcount(void) __asm("mcount");
+#endif
+#endif
+void _mcount(uintfptr_t frompc, uintfptr_t selfpc);
+__END_DECLS
+
+#endif /* _KERNEL */
+
+#ifdef GUPROF
+/* XXX doesn't quite work outside kernel yet. */
+extern int cputime_bias;
+
+__BEGIN_DECLS
+int cputime(void);
+void empty_loop(void);
+void mexitcount(uintfptr_t selfpc);
+void nullfunc(void);
+void nullfunc_loop(void);
+__END_DECLS
+#endif
+
+#endif /* !_MACHINE_PROFILE_H_ */
Property changes on: trunk/sys/mips/include/profile.h
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Added: trunk/sys/mips/include/pte.h
===================================================================
--- trunk/sys/mips/include/pte.h (rev 0)
+++ trunk/sys/mips/include/pte.h 2018-05-26 21:55:02 UTC (rev 9987)
@@ -0,0 +1,192 @@
+/* $MidnightBSD$ */
+/*-
+ * Copyright (c) 2004-2010 Juli Mallett <jmallett at FreeBSD.org>
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ * $FreeBSD: stable/10/sys/mips/include/pte.h 257523 2013-11-01 20:30:19Z brooks $
+ */
+
+#ifndef _MACHINE_PTE_H_
+#define _MACHINE_PTE_H_
+
+#ifndef _LOCORE
+#if defined(__mips_n64) || defined(__mips_n32) /* PHYSADDR_64_BIT */
+typedef uint64_t pt_entry_t;
+#else
+typedef uint32_t pt_entry_t;
+#endif
+typedef pt_entry_t *pd_entry_t;
+#endif
+
+/*
+ * TLB and PTE management. Most things operate within the context of
+ * EntryLo0,1, and begin with TLBLO_. Things which work with EntryHi
+ * start with TLBHI_. PTE bits begin with PTE_.
+ *
+ * Note that we use the same size VM and TLB pages.
+ */
+#define TLB_PAGE_SHIFT (PAGE_SHIFT)
+#define TLB_PAGE_SIZE (1 << TLB_PAGE_SHIFT)
+#define TLB_PAGE_MASK (TLB_PAGE_SIZE - 1)
+
+/*
+ * TLB PageMask register. Has mask bits set above the default, 4K, page mask.
+ */
+#define TLBMASK_SHIFT (13)
+#define TLBMASK_MASK ((PAGE_MASK >> TLBMASK_SHIFT) << TLBMASK_SHIFT)
+
+/*
+ * FreeBSD/mips page-table entries take a near-identical format to MIPS TLB
+ * entries, each consisting of two 32-bit or 64-bit values ("EntryHi" and
+ * "EntryLo"). MIPS4k and MIPS64 both define certain bits in TLB entries as
+ * reserved, and these must be zero-filled by software. We overload these
+ * bits in PTE entries to hold PTE_ flags such as RO, W, and MANAGED.
+ * However, we must mask these out when writing to TLB entries to ensure that
+ * they do not become visible to hardware -- especially on MIPS64r2 which has
+ * an extended physical memory space.
+ *
+ * When using n64 and n32, shift software-defined bits into the MIPS64r2
+ * reserved range, which runs from bit 55 ... 63. In other configurations
+ * (32-bit MIPS4k and compatible), shift them out to bits 29 ... 31.
+ *
+ * NOTE: This means that for 32-bit use of CP0, we aren't able to set the top
+ * bit of PFN to a non-zero value, as software is using it! This physical
+ * memory size limit may not be sufficiently enforced elsewhere.
+ */
+#if defined(__mips_n64) || defined(__mips_n32) /* PHYSADDR_64_BIT */
+#define TLBLO_SWBITS_SHIFT (55)
+#define TLBLO_SWBITS_CLEAR_SHIFT (9)
+#define TLBLO_PFN_MASK 0x3FFFFFFC0ULL
+#else
+#define TLBLO_SWBITS_SHIFT (29)
+#define TLBLO_SWBITS_CLEAR_SHIFT (3)
+#define TLBLO_PFN_MASK (0x1FFFFFC0)
+#endif
+#define TLBLO_PFN_SHIFT (6)
+#define TLBLO_SWBITS_MASK ((pt_entry_t)0x7 << TLBLO_SWBITS_SHIFT)
+#define TLBLO_PA_TO_PFN(pa) ((((pa) >> TLB_PAGE_SHIFT) << TLBLO_PFN_SHIFT) & TLBLO_PFN_MASK)
+#define TLBLO_PFN_TO_PA(pfn) ((vm_paddr_t)((pfn) >> TLBLO_PFN_SHIFT) << TLB_PAGE_SHIFT)
+#define TLBLO_PTE_TO_PFN(pte) ((pte) & TLBLO_PFN_MASK)
+#define TLBLO_PTE_TO_PA(pte) (TLBLO_PFN_TO_PA(TLBLO_PTE_TO_PFN((pte))))
+
+/*
+ * XXX This comment is not correct for anything more modern than R4K.
+ *
+ * VPN for EntryHi register. Upper two bits select user, supervisor,
+ * or kernel. Bits 61 to 40 copy bit 63. VPN2 is bits 39 and down to
+ * as low as 13, down to PAGE_SHIFT, to index 2 TLB pages*. From bit 12
+ * to bit 8 there is a 5-bit 0 field. Low byte is ASID.
+ *
+ * XXX This comment is not correct for FreeBSD.
+ * Note that in FreeBSD, we map 2 TLB pages is equal to 1 VM page.
+ */
+#define TLBHI_ASID_MASK (0xff)
+#if defined(__mips_n64)
+#define TLBHI_R_SHIFT 62
+#define TLBHI_R_USER (0x00UL << TLBHI_R_SHIFT)
+#define TLBHI_R_SUPERVISOR (0x01UL << TLBHI_R_SHIFT)
+#define TLBHI_R_KERNEL (0x03UL << TLBHI_R_SHIFT)
+#define TLBHI_R_MASK (0x03UL << TLBHI_R_SHIFT)
+#define TLBHI_VA_R(va) ((va) & TLBHI_R_MASK)
+#define TLBHI_FILL_SHIFT 40
+#define TLBHI_VPN2_SHIFT (TLB_PAGE_SHIFT + 1)
+#define TLBHI_VPN2_MASK (((~((1UL << TLBHI_VPN2_SHIFT) - 1)) << (63 - TLBHI_FILL_SHIFT)) >> (63 - TLBHI_FILL_SHIFT))
+#define TLBHI_VA_TO_VPN2(va) ((va) & TLBHI_VPN2_MASK)
+#define TLBHI_ENTRY(va, asid) ((TLBHI_VA_R((va))) /* Region. */ | \
+ (TLBHI_VA_TO_VPN2((va))) /* VPN2. */ | \
+ ((asid) & TLBHI_ASID_MASK))
+#else /* !defined(__mips_n64) */
+#define TLBHI_PAGE_MASK (2 * PAGE_SIZE - 1)
+#define TLBHI_ENTRY(va, asid) (((va) & ~TLBHI_PAGE_MASK) | ((asid) & TLBHI_ASID_MASK))
+#endif /* defined(__mips_n64) */
+
+/*
+ * TLB flags managed in hardware:
+ * C: Cache attribute.
+ * D: Dirty bit. This means a page is writable. It is not
+ * set at first, and a write is trapped, and the dirty
+ * bit is set. See also PTE_RO.
+ * V: Valid bit. Obvious, isn't it?
+ * G: Global bit. This means that this mapping is present
+ * in EVERY address space, and to ignore the ASID when
+ * it is matched.
+ */
+#define PTE_C(attr) ((attr & 0x07) << 3)
+#define PTE_C_UNCACHED (PTE_C(MIPS_CCA_UNCACHED))
+#define PTE_C_CACHE (PTE_C(MIPS_CCA_CACHED))
+#define PTE_D 0x04
+#define PTE_V 0x02
+#define PTE_G 0x01
+
+/*
+ * VM flags managed in software:
+ * RO: Read only. Never set PTE_D on this page, and don't
+ * listen to requests to write to it.
+ * W: Wired. ???
+ * MANAGED:Managed. This PTE maps a managed page.
+ *
+ * These bits should not be written into the TLB, so must first be masked out
+ * explicitly in C, or using CLEAR_PTE_SWBITS() in assembly.
+ */
+#define PTE_RO ((pt_entry_t)0x01 << TLBLO_SWBITS_SHIFT)
+#define PTE_W ((pt_entry_t)0x02 << TLBLO_SWBITS_SHIFT)
+#define PTE_MANAGED ((pt_entry_t)0x04 << TLBLO_SWBITS_SHIFT)
+
+/*
+ * PTE management functions for bits defined above.
+ */
+#define pte_clear(pte, bit) (*(pte) &= ~(bit))
+#define pte_set(pte, bit) (*(pte) |= (bit))
+#define pte_test(pte, bit) ((*(pte) & (bit)) == (bit))
+
+/* Assembly support for PTE access*/
+#ifdef LOCORE
+#if defined(__mips_n64) || defined(__mips_n32) /* PHYSADDR_64_BIT */
+#define PTESHIFT 3
+#define PTE2MASK 0xff0 /* for the 2-page lo0/lo1 */
+#define PTEMASK 0xff8
+#define PTESIZE 8
+#define PTE_L ld
+#define PTE_MTC0 dmtc0
+#define CLEAR_PTE_SWBITS(pr)
+#else
+#define PTESHIFT 2
+#define PTE2MASK 0xff8 /* for the 2-page lo0/lo1 */
+#define PTEMASK 0xffc
+#define PTESIZE 4
+#define PTE_L lw
+#define PTE_MTC0 mtc0
+#define CLEAR_PTE_SWBITS(r) LONG_SLL r, TLBLO_SWBITS_CLEAR_SHIFT; LONG_SRL r, TLBLO_SWBITS_CLEAR_SHIFT /* remove swbits */
+#endif /* defined(__mips_n64) || defined(__mips_n32) */
+
+#if defined(__mips_n64)
+#define PTRSHIFT 3
+#define PDEPTRMASK 0xff8
+#else
+#define PTRSHIFT 2
+#define PDEPTRMASK 0xffc
+#endif
+
+#endif /* LOCORE */
+#endif /* !_MACHINE_PTE_H_ */
Property changes on: trunk/sys/mips/include/pte.h
___________________________________________________________________
Added: svn:eol-style
## -0,0 +1 ##
+native
\ No newline at end of property
Added: svn:keywords
## -0,0 +1 ##
+MidnightBSD=%H
\ No newline at end of property
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+text/plain
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Added: trunk/sys/mips/include/ptrace.h
===================================================================
--- trunk/sys/mips/include/ptrace.h (rev 0)
+++ trunk/sys/mips/include/ptrace.h 2018-05-26 21:55:02 UTC (rev 9987)
@@ -0,0 +1,38 @@
+/* $MidnightBSD$ */
+/*-
+ * Copyright (c) 1992, 1993
+ * The Regents of the University of California. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * 4. Neither the name of the University nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ * @(#)ptrace.h 8.1 (Berkeley) 6/11/93
+ * from: src/sys/i386/include/ptrace.h,v 1.14 2005/05/31 09:43:04 dfr
+ * $FreeBSD: stable/10/sys/mips/include/ptrace.h 202175 2010-01-12 21:36:08Z imp $
+ */
+
+#ifndef _MACHINE_PTRACE_H_
+#define _MACHINE_PTRACE_H_
+
+#endif
Property changes on: trunk/sys/mips/include/ptrace.h
___________________________________________________________________
Added: svn:eol-style
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Added: trunk/sys/mips/include/reg.h
===================================================================
--- trunk/sys/mips/include/reg.h (rev 0)
+++ trunk/sys/mips/include/reg.h 2018-05-26 21:55:02 UTC (rev 9987)
@@ -0,0 +1,112 @@
+/* $MidnightBSD$ */
+/* $OpenBSD: reg.h,v 1.1 1998/01/28 11:14:53 pefo Exp $ */
+
+/*-
+ * Copyright (c) 1988 University of Utah.
+ * Copyright (c) 1992, 1993
+ * The Regents of the University of California. All rights reserved.
+ *
+ * This code is derived from software contributed to Berkeley by
+ * the Systems Programming Group of the University of Utah Computer
+ * Science Department and Ralph Campbell.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * 4. Neither the name of the University nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ * from: Utah Hdr: reg.h 1.1 90/07/09
+ * @(#)reg.h 8.2 (Berkeley) 1/11/94
+ * JNPR: reg.h,v 1.6 2006/09/15 12:52:34 katta
+ * $FreeBSD: stable/10/sys/mips/include/reg.h 283910 2015-06-02 14:54:53Z jhb $
+ */
+
+#ifndef _MACHINE_REG_H_
+#define _MACHINE_REG_H_
+
+#if defined(_KERNEL) && !defined(KLD_MODULE) && !defined(_STANDALONE)
+#include "opt_compat.h"
+#endif
+
+/*
+ * Location of the users' stored registers relative to ZERO.
+ * must be visible to assembly code.
+ */
+#include <machine/regnum.h>
+
+/*
+ * Register set accessible via /proc/$pid/reg
+ */
+struct reg {
+ register_t r_regs[NUMSAVEREGS]; /* numbered as above */
+};
+
+struct fpreg {
+ f_register_t r_regs[NUMFPREGS];
+};
+
+/*
+ * Placeholder.
+ */
+struct dbreg {
+ unsigned long junk;
+};
+
+#ifdef __LP64__
+/* Must match struct trapframe */
+struct reg32 {
+ uint32_t r_regs[NUMSAVEREGS];
+};
+
+struct fpreg32 {
+ int32_t r_regs[NUMFPREGS];
+};
+
+struct dbreg32 {
+ uint32_t junk;
+};
+
+#define __HAVE_REG32
+#endif
+
+#ifdef _KERNEL
+int fill_fpregs(struct thread *, struct fpreg *);
+int fill_regs(struct thread *, struct reg *);
+int set_fpregs(struct thread *, struct fpreg *);
+int set_regs(struct thread *, struct reg *);
+int fill_dbregs(struct thread *, struct dbreg *);
+int set_dbregs(struct thread *, struct dbreg *);
+#endif
+
+#ifdef COMPAT_FREEBSD32
+struct image_params;
+
+int fill_regs32(struct thread *, struct reg32 *);
+int set_regs32(struct thread *, struct reg32 *);
+int fill_fpregs32(struct thread *, struct fpreg32 *);
+int set_fpregs32(struct thread *, struct fpreg32 *);
+
+#define fill_dbregs32(td, reg) 0
+#define set_dbregs32(td, reg) 0
+#endif
+
+#endif /* !_MACHINE_REG_H_ */
Property changes on: trunk/sys/mips/include/reg.h
___________________________________________________________________
Added: svn:eol-style
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+MidnightBSD=%H
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+text/plain
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Added: trunk/sys/mips/include/regdef.h
===================================================================
--- trunk/sys/mips/include/regdef.h (rev 0)
+++ trunk/sys/mips/include/regdef.h 2018-05-26 21:55:02 UTC (rev 9987)
@@ -0,0 +1,109 @@
+/* $MidnightBSD$ */
+/* $NetBSD: regdef.h,v 1.12 2005/12/11 12:18:09 christos Exp $ */
+
+/*
+ * Copyright (c) 1992, 1993
+ * The Regents of the University of California. All rights reserved.
+ *
+ * This code is derived from software contributed to Berkeley by
+ * Ralph Campbell. This file is derived from the MIPS RISC
+ * Architecture book by Gerry Kane.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * 3. Neither the name of the University nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ * @(#)regdef.h 8.1 (Berkeley) 6/10/93
+ * $FreeBSD: stable/10/sys/mips/include/regdef.h 250138 2013-05-01 06:57:46Z imp $
+ */
+
+#ifndef _MIPS_REGDEF_H
+#define _MIPS_REGDEF_H
+
+#include <machine/cdefs.h> /* for API selection */
+
+#define zero $0 /* always zero */
+#define AT $at /* assembler temporary */
+#define v0 $2 /* return value */
+#define v1 $3
+#define a0 $4 /* argument registers */
+#define a1 $5
+#define a2 $6
+#define a3 $7
+#if defined(__mips_n32) || defined(__mips_n64)
+#define a4 $8
+#define a5 $9
+#define a6 $10
+#define a7 $11
+#define t0 $12 /* temp registers (not saved across subroutine calls) */
+#define t1 $13
+#define t2 $14
+#define t3 $15
+#else
+#define t0 $8 /* temp registers (not saved across subroutine calls) */
+#define t1 $9
+#define t2 $10
+#define t3 $11
+#define t4 $12
+#define t5 $13
+#define t6 $14
+#define t7 $15
+#endif /* __mips_n32 || __mips_n64 */
+#define s0 $16 /* saved across subroutine calls (callee saved) */
+#define s1 $17
+#define s2 $18
+#define s3 $19
+#define s4 $20
+#define s5 $21
+#define s6 $22
+#define s7 $23
+#define t8 $24 /* two more temporary registers */
+#define t9 $25
+#define k0 $26 /* kernel temporary */
+#define k1 $27
+#define gp $28 /* global pointer */
+#define sp $29 /* stack pointer */
+#define s8 $30 /* one more callee saved */
+#define ra $31 /* return address */
+
+/*
+ * These are temp registers whose names can be used in either the old
+ * or new ABI, although they map to different physical registers. In
+ * the old ABI, they map to t4-t7, and in the new ABI, they map to a4-a7.
+ *
+ * Because they overlap with the last 4 arg regs in the new ABI, ta0-ta3
+ * should be used only when we need more than t0-t3.
+ */
+#if defined(__mips_n32) || defined(__mips_n64)
+#define ta0 $8
+#define ta1 $9
+#define ta2 $10
+#define ta3 $11
+#else
+#define ta0 $12
+#define ta1 $13
+#define ta2 $14
+#define ta3 $15
+#endif /* __mips_n32 || __mips_n64 */
+
+#endif /* _MIPS_REGDEF_H */
Property changes on: trunk/sys/mips/include/regdef.h
___________________________________________________________________
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+text/plain
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Added: trunk/sys/mips/include/regnum.h
===================================================================
--- trunk/sys/mips/include/regnum.h (rev 0)
+++ trunk/sys/mips/include/regnum.h 2018-05-26 21:55:02 UTC (rev 9987)
@@ -0,0 +1,209 @@
+/* $MidnightBSD$ */
+/* $OpenBSD: regnum.h,v 1.3 1999/01/27 04:46:06 imp Exp $ */
+
+/*-
+ * Copyright (c) 1988 University of Utah.
+ * Copyright (c) 1992, 1993
+ * The Regents of the University of California. All rights reserved.
+ *
+ * This code is derived from software contributed to Berkeley by
+ * the Systems Programming Group of the University of Utah Computer
+ * Science Department and Ralph Campbell.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * 4. Neither the name of the University nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ * from: Utah Hdr: reg.h 1.1 90/07/09
+ * @(#)reg.h 8.2 (Berkeley) 1/11/94
+ * JNPR: regnum.h,v 1.6 2007/08/09 11:23:32 katta
+ * $FreeBSD: stable/10/sys/mips/include/regnum.h 249901 2013-04-25 17:23:54Z imp $
+ */
+
+#ifndef _MACHINE_REGNUM_H_
+#define _MACHINE_REGNUM_H_
+
+/*
+ * Location of the saved registers relative to ZERO.
+ * This must match struct trapframe defined in frame.h exactly.
+ * This must also match regdef.h.
+ */
+#define ZERO 0
+#define AST 1
+#define V0 2
+#define V1 3
+#define A0 4
+#define A1 5
+#define A2 6
+#define A3 7
+#if defined(__mips_n32) || defined(__mips_n64)
+#define A4 8
+#define A5 9
+#define A6 10
+#define A7 11
+#define T0 12
+#define T1 13
+#define T2 14
+#define T3 15
+#else
+#define T0 8
+#define T1 9
+#define T2 10
+#define T3 11
+#define T4 12
+#define T5 13
+#define T6 14
+#define T7 15
+#endif
+#define S0 16
+#define S1 17
+#define S2 18
+#define S3 19
+#define S4 20
+#define S5 21
+#define S6 22
+#define S7 23
+#define T8 24
+#define T9 25
+#define K0 26
+#define K1 27
+#define GP 28
+#define SP 29
+#define S8 30
+#define RA 31
+#define SR 32
+#define PS SR /* alias for SR */
+#define MULLO 33
+#define MULHI 34
+#define BADVADDR 35
+#define CAUSE 36
+#define PC 37
+/*
+ * IC is valid only on RM7K and RM9K processors. Access to this is
+ * controlled by IC_INT_REG which defined in kernel config
+ */
+#define IC 38
+#define DUMMY 39 /* for 8 byte alignment */
+#define NUMSAVEREGS 40
+
+/*
+ * Pseudo registers so we save a complete set of registers regardless of
+ * the ABI. See regdef.h for a more complete explanation.
+ */
+#if defined(__mips_n32) || defined(__mips_n64)
+#define TA0 8
+#define TA1 9
+#define TA2 10
+#define TA3 11
+#else
+#define TA0 12
+#define TA1 13
+#define TA2 14
+#define TA3 15
+#endif
+
+
+/*
+ * Index of FP registers in 'struct frame', counting from the beginning
+ * of the frame (i.e., including the general registers).
+ */
+#define FPBASE NUMSAVEREGS
+#define F0 (FPBASE+0)
+#define F1 (FPBASE+1)
+#define F2 (FPBASE+2)
+#define F3 (FPBASE+3)
+#define F4 (FPBASE+4)
+#define F5 (FPBASE+5)
+#define F6 (FPBASE+6)
+#define F7 (FPBASE+7)
+#define F8 (FPBASE+8)
+#define F9 (FPBASE+9)
+#define F10 (FPBASE+10)
+#define F11 (FPBASE+11)
+#define F12 (FPBASE+12)
+#define F13 (FPBASE+13)
+#define F14 (FPBASE+14)
+#define F15 (FPBASE+15)
+#define F16 (FPBASE+16)
+#define F17 (FPBASE+17)
+#define F18 (FPBASE+18)
+#define F19 (FPBASE+19)
+#define F20 (FPBASE+20)
+#define F21 (FPBASE+21)
+#define F22 (FPBASE+22)
+#define F23 (FPBASE+23)
+#define F24 (FPBASE+24)
+#define F25 (FPBASE+25)
+#define F26 (FPBASE+26)
+#define F27 (FPBASE+27)
+#define F28 (FPBASE+28)
+#define F29 (FPBASE+29)
+#define F30 (FPBASE+30)
+#define F31 (FPBASE+31)
+#define FSR (FPBASE+32)
+#define FSR_DUMMY (FPBASE+33) /* For 8 byte alignment */
+
+#define NUMFPREGS 34
+
+#define NREGS (NUMSAVEREGS + NUMFPREGS)
+
+/*
+ * Index of FP registers in 'struct frame', relative to the base
+ * of the FP registers in frame (i.e., *not* including the general
+ * registers).
+ */
+#define F0_NUM (0)
+#define F1_NUM (1)
+#define F2_NUM (2)
+#define F3_NUM (3)
+#define F4_NUM (4)
+#define F5_NUM (5)
+#define F6_NUM (6)
+#define F7_NUM (7)
+#define F8_NUM (8)
+#define F9_NUM (9)
+#define F10_NUM (10)
+#define F11_NUM (11)
+#define F12_NUM (12)
+#define F13_NUM (13)
+#define F14_NUM (14)
+#define F15_NUM (15)
+#define F16_NUM (16)
+#define F17_NUM (17)
+#define F18_NUM (18)
+#define F19_NUM (19)
+#define F20_NUM (20)
+#define F21_NUM (21)
+#define F22_NUM (22)
+#define F23_NUM (23)
+#define F24_NUM (24)
+#define F25_NUM (25)
+#define F26_NUM (26)
+#define F27_NUM (27)
+#define F28_NUM (28)
+#define F29_NUM (29)
+#define F30_NUM (30)
+#define F31_NUM (31)
+#define FSR_NUM (32)
+
+#endif /* !_MACHINE_REGNUM_H_ */
Property changes on: trunk/sys/mips/include/regnum.h
___________________________________________________________________
Added: svn:eol-style
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+MidnightBSD=%H
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+text/plain
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Added: trunk/sys/mips/include/reloc.h
===================================================================
--- trunk/sys/mips/include/reloc.h (rev 0)
+++ trunk/sys/mips/include/reloc.h 2018-05-26 21:55:02 UTC (rev 9987)
@@ -0,0 +1,36 @@
+/* $MidnightBSD$ */
+/*
+ * Copyright (c) 1998 John Birrell <jb at cimlogic.com.au>.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * 3. All advertising materials mentioning features or use of this software
+ * must display the following acknowledgement:
+ * This product includes software developed by John Birrell.
+ * 4. Neither the name of the author nor the names of any co-contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY JOHN BIRRELL AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ * from: src/sys/alpha/include/reloc.h,v 1.1.1.1.6.1 2000/08/03 00:48:04 peter
+ * JNPR: reloc.h,v 1.3 2006/08/07 05:38:57 katta
+ * $FreeBSD: stable/10/sys/mips/include/reloc.h 202175 2010-01-12 21:36:08Z imp $
+ */
Property changes on: trunk/sys/mips/include/reloc.h
___________________________________________________________________
Added: svn:eol-style
## -0,0 +1 ##
+native
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+MidnightBSD=%H
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+text/plain
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Added: trunk/sys/mips/include/resource.h
===================================================================
--- trunk/sys/mips/include/resource.h (rev 0)
+++ trunk/sys/mips/include/resource.h 2018-05-26 21:55:02 UTC (rev 9987)
@@ -0,0 +1,47 @@
+/* $MidnightBSD$ */
+/*-
+ * Copyright 1998 Massachusetts Institute of Technology
+ *
+ * Permission to use, copy, modify, and distribute this software and
+ * its documentation for any purpose and without fee is hereby
+ * granted, provided that both the above copyright notice and this
+ * permission notice appear in all copies, that both the above
+ * copyright notice and this permission notice appear in all
+ * supporting documentation, and that the name of M.I.T. not be used
+ * in advertising or publicity pertaining to distribution of the
+ * software without specific, written prior permission. M.I.T. makes
+ * no representations about the suitability of this software for any
+ * purpose. It is provided "as is" without express or implied
+ * warranty.
+ *
+ * THIS SOFTWARE IS PROVIDED BY M.I.T. ``AS IS''. M.I.T. DISCLAIMS
+ * ALL EXPRESS OR IMPLIED WARRANTIES WITH REGARD TO THIS SOFTWARE,
+ * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT
+ * SHALL M.I.T. BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
+ * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
+ * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ * from: src/sys/i386/include/resource.h,v 1.3 1999/10/14 21:38:30 dfr
+ * JNPR: resource.h,v 1.3 2006/08/07 05:38:57 katta
+ * $FreeBSD: stable/10/sys/mips/include/resource.h 202175 2010-01-12 21:36:08Z imp $
+ */
+
+#ifndef _MACHINE_RESOURCE_H_
+#define _MACHINE_RESOURCE_H_ 1
+
+/*
+ * Definitions of resource types for Intel Architecture machines
+ * with support for legacy ISA devices and drivers.
+ */
+
+#define SYS_RES_IRQ 1 /* interrupt lines */
+#define SYS_RES_DRQ 2 /* isa dma lines */
+#define SYS_RES_MEMORY 3 /* i/o memory */
+#define SYS_RES_IOPORT 4 /* i/o ports */
+
+#endif /* !_MACHINE_RESOURCE_H_ */
Property changes on: trunk/sys/mips/include/resource.h
___________________________________________________________________
Added: svn:eol-style
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+MidnightBSD=%H
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+text/plain
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Added: trunk/sys/mips/include/runq.h
===================================================================
--- trunk/sys/mips/include/runq.h (rev 0)
+++ trunk/sys/mips/include/runq.h 2018-05-26 21:55:02 UTC (rev 9987)
@@ -0,0 +1,61 @@
+/* $MidnightBSD$ */
+/*-
+ * Copyright (c) 2001 Jake Burkholder <jake at FreeBSD.org>
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ * from: src/sys/i386/include/runq.h,v 1.3 2005/01/06 22:18:15 imp
+ * $FreeBSD: stable/10/sys/mips/include/runq.h 210605 2010-07-29 13:52:46Z jchandra $
+ */
+
+#ifndef _MACHINE_RUNQ_H_
+#define _MACHINE_RUNQ_H_
+
+#ifdef __mips_n64
+#define RQB_LEN (1) /* Number of priority status words. */
+#define RQB_L2BPW (6) /* Log2(sizeof(rqb_word_t) * NBBY)). */
+#else
+#define RQB_LEN (2) /* Number of priority status words. */
+#define RQB_L2BPW (5) /* Log2(sizeof(rqb_word_t) * NBBY)). */
+#endif
+#define RQB_BPW (1<<RQB_L2BPW) /* Bits in an rqb_word_t. */
+
+#define RQB_BIT(pri) (1ul << ((pri) & (RQB_BPW - 1)))
+#define RQB_WORD(pri) ((pri) >> RQB_L2BPW)
+
+#ifdef __mips_n64
+#define RQB_FFS(word) (ffsl(word) - 1)
+#else
+#define RQB_FFS(word) (ffs(word) - 1)
+#endif
+
+/*
+ * Type of run queue status word.
+ */
+#ifdef __mips_n64
+typedef u_int64_t rqb_word_t;
+#else
+typedef u_int32_t rqb_word_t;
+#endif
+
+#endif
Property changes on: trunk/sys/mips/include/runq.h
___________________________________________________________________
Added: svn:eol-style
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+text/plain
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Added: trunk/sys/mips/include/sc_machdep.h
===================================================================
--- trunk/sys/mips/include/sc_machdep.h (rev 0)
+++ trunk/sys/mips/include/sc_machdep.h 2018-05-26 21:55:02 UTC (rev 9987)
@@ -0,0 +1,72 @@
+/* $MidnightBSD$ */
+/*-
+ * Copyright (c) 2003 Jake Burkholder.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ * $FreeBSD: stable/10/sys/mips/include/sc_machdep.h 239684 2012-08-25 17:57:50Z rwatson $
+ */
+
+#ifndef _MACHINE_SC_MACHDEP_H_
+#define _MACHINE_SC_MACHDEP_H_
+
+/* Color attributes for foreground text */
+
+#define FG_BLACK 0x0
+#define FG_BLUE 0x1
+#define FG_GREEN 0x2
+#define FG_CYAN 0x3
+#define FG_RED 0x4
+#define FG_MAGENTA 0x5
+#define FG_BROWN 0x6
+#define FG_LIGHTGREY 0x7 /* aka white */
+#define FG_DARKGREY 0x8
+#define FG_LIGHTBLUE 0x9
+#define FG_LIGHTGREEN 0xa
+#define FG_LIGHTCYAN 0xb
+#define FG_LIGHTRED 0xc
+#define FG_LIGHTMAGENTA 0xd
+#define FG_YELLOW 0xe
+#define FG_WHITE 0xf /* aka bright white */
+#define FG_BLINK 0x80
+
+/* Color attributes for text background */
+
+#define BG_BLACK 0x00
+#define BG_BLUE 0x10
+#define BG_GREEN 0x20
+#define BG_CYAN 0x30
+#define BG_RED 0x40
+#define BG_MAGENTA 0x50
+#define BG_BROWN 0x60
+#define BG_LIGHTGREY 0x70
+#define BG_DARKGREY 0x80
+#define BG_LIGHTBLUE 0x90
+#define BG_LIGHTGREEN 0xa0
+#define BG_LIGHTCYAN 0xb0
+#define BG_LIGHTRED 0xc0
+#define BG_LIGHTMAGENTA 0xd0
+#define BG_YELLOW 0xe0
+#define BG_WHITE 0xf0
+
+#endif /* !_MACHINE_SC_MACHDEP_H_ */
Property changes on: trunk/sys/mips/include/sc_machdep.h
___________________________________________________________________
Added: svn:eol-style
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Added: trunk/sys/mips/include/setjmp.h
===================================================================
--- trunk/sys/mips/include/setjmp.h (rev 0)
+++ trunk/sys/mips/include/setjmp.h 2018-05-26 21:55:02 UTC (rev 9987)
@@ -0,0 +1,68 @@
+/* $MidnightBSD$ */
+/* From: NetBSD: setjmp.h,v 1.2 1997/04/06 08:47:41 cgd Exp */
+
+/*-
+ * Copyright (c) 1994, 1995 Carnegie-Mellon University.
+ * All rights reserved.
+ *
+ * Author: Chris G. Demetriou
+ *
+ * Permission to use, copy, modify and distribute this software and
+ * its documentation is hereby granted, provided that both the copyright
+ * notice and this permission notice appear in all copies of the
+ * software, derivative works or modified versions, and any portions
+ * thereof, and that both notices appear in supporting documentation.
+ *
+ * CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS"
+ * CONDITION. CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND
+ * FOR ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE.
+ *
+ * Carnegie Mellon requests users of this software to return to
+ *
+ * Software Distribution Coordinator or Software.Distribution at CS.CMU.EDU
+ * School of Computer Science
+ * Carnegie Mellon University
+ * Pittsburgh PA 15213-3890
+ *
+ * any improvements or extensions that they make and grant Carnegie the
+ * rights to redistribute these changes.
+ *
+ * JNPR: setjmp.h,v 1.2 2006/12/02 09:53:41 katta
+ * $FreeBSD: stable/10/sys/mips/include/setjmp.h 209500 2010-06-24 08:08:43Z jchandra $
+ */
+
+#ifndef _MACHINE_SETJMP_H_
+#define _MACHINE_SETJMP_H_
+
+/*
+ * machine/setjmp.h: machine dependent setjmp-related information.
+ */
+
+#include <sys/cdefs.h>
+
+#define _JBLEN 95 /* size, in longs (or long longs), of a jmp_buf */
+
+/*
+ * jmp_buf and sigjmp_buf are encapsulated in different structs to force
+ * compile-time diagnostics for mismatches. The structs are the same
+ * internally to avoid some run-time errors for mismatches.
+ */
+#ifndef _LOCORE
+#ifndef __ASSEMBLER__
+#if __BSD_VISIBLE || __POSIX_VISIBLE || __XSI_VISIBLE
+#ifdef __mips_n32
+typedef struct _sigjmp_buf { long long _sjb[_JBLEN + 1]; } sigjmp_buf[1];
+#else
+typedef struct _sigjmp_buf { long _sjb[_JBLEN + 1]; } sigjmp_buf[1];
+#endif
+#endif
+
+#ifdef __mips_n32
+typedef struct _jmp_buf { long long _jb[_JBLEN + 1]; } jmp_buf[1];
+#else
+typedef struct _jmp_buf { long _jb[_JBLEN + 1]; } jmp_buf[1];
+#endif
+#endif /* __ASSEMBLER__ */
+#endif /* _LOCORE */
+
+#endif /* _MACHINE_SETJMP_H_ */
Property changes on: trunk/sys/mips/include/setjmp.h
___________________________________________________________________
Added: svn:eol-style
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+text/plain
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Added: trunk/sys/mips/include/sf_buf.h
===================================================================
--- trunk/sys/mips/include/sf_buf.h (rev 0)
+++ trunk/sys/mips/include/sf_buf.h 2018-05-26 21:55:02 UTC (rev 9987)
@@ -0,0 +1,100 @@
+/* $MidnightBSD$ */
+/*-
+ * Copyright (c) 2003 Alan L. Cox <alc at cs.rice.edu>
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ * $FreeBSD: stable/10/sys/mips/include/sf_buf.h 255318 2013-09-06 17:44:13Z glebius $
+ */
+
+#ifndef _MACHINE_SF_BUF_H_
+#define _MACHINE_SF_BUF_H_
+
+#ifdef __mips_n64
+#include <vm/vm.h>
+#include <vm/vm_param.h>
+#include <vm/vm_page.h>
+#else
+#include <sys/queue.h>
+#endif
+
+#ifdef __mips_n64
+/* In 64 bit the whole memory is directly mapped */
+struct sf_buf;
+
+static inline struct sf_buf *
+sf_buf_alloc(struct vm_page *m, int pri)
+{
+
+ return ((struct sf_buf *)m);
+}
+
+static inline void
+sf_buf_free(struct sf_buf *sf)
+{
+}
+
+static __inline vm_offset_t
+sf_buf_kva(struct sf_buf *sf)
+{
+ vm_page_t m;
+
+ m = (vm_page_t)sf;
+ return (MIPS_PHYS_TO_DIRECT(VM_PAGE_TO_PHYS(m)));
+}
+
+static __inline struct vm_page *
+sf_buf_page(struct sf_buf *sf)
+{
+
+ return ((vm_page_t)sf);
+}
+
+#else /* ! __mips_n64 */
+struct vm_page;
+
+struct sf_buf {
+ SLIST_ENTRY(sf_buf) free_list; /* list of free buffer slots */
+ struct vm_page *m; /* currently mapped page */
+ vm_offset_t kva; /* va of mapping */
+};
+
+struct sf_buf * sf_buf_alloc(struct vm_page *m, int flags);
+void sf_buf_free(struct sf_buf *sf);
+
+static __inline vm_offset_t
+sf_buf_kva(struct sf_buf *sf)
+{
+
+ return (sf->kva);
+}
+
+static __inline struct vm_page *
+sf_buf_page(struct sf_buf *sf)
+{
+
+ return (sf->m);
+}
+#endif /* __mips_n64 */
+
+#endif /* !_MACHINE_SF_BUF_H_ */
Property changes on: trunk/sys/mips/include/sf_buf.h
___________________________________________________________________
Added: svn:eol-style
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Added: trunk/sys/mips/include/sigframe.h
===================================================================
--- trunk/sys/mips/include/sigframe.h (rev 0)
+++ trunk/sys/mips/include/sigframe.h 2018-05-26 21:55:02 UTC (rev 9987)
@@ -0,0 +1,68 @@
+/* $MidnightBSD$ */
+/*-
+ * Copyright (c) 1999 Marcel Moolenaar
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer
+ * in this position and unchanged.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ * derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+ * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+ * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * from: src/sys/alpha/include/sigframe.h,v 1.1 1999/09/29 15:06:26 marcel
+ * from: sigframe.h,v 1.1 2006/08/07 05:38:57 katta
+ * $FreeBSD: stable/10/sys/mips/include/sigframe.h 232449 2012-03-03 08:19:18Z jmallett $
+ */
+#ifndef _MACHINE_SIGFRAME_H_
+#define _MACHINE_SIGFRAME_H_
+
+#if defined(_KERNEL) && !defined(KLD_MODULE) && !defined(_STANDALONE)
+#include "opt_compat.h"
+#endif
+
+/*
+ * WARNING: code in locore.s assumes the layout shown for sf_signum
+ * thru sf_addr so... don't alter them!
+ */
+struct sigframe {
+ register_t sf_signum;
+ register_t sf_siginfo; /* code or pointer to sf_si */
+ register_t sf_ucontext; /* points to sf_uc */
+ register_t sf_addr; /* undocumented 4th arg */
+ ucontext_t sf_uc; /* = *sf_ucontext */
+ siginfo_t sf_si; /* = *sf_siginfo (SA_SIGINFO case) */
+ unsigned long __spare__[2];
+};
+
+#if (defined(__mips_n32) || defined(__mips_n64)) && defined(COMPAT_FREEBSD32)
+#include <compat/freebsd32/freebsd32_signal.h>
+
+struct sigframe32 {
+ int32_t sf_signum;
+ int32_t sf_siginfo; /* code or pointer to sf_si */
+ int32_t sf_ucontext; /* points to sf_uc */
+ int32_t sf_addr; /* undocumented 4th arg */
+ ucontext32_t sf_uc; /* = *sf_ucontext */
+ struct siginfo32 sf_si; /* = *sf_siginfo (SA_SIGINFO case) */
+ uint32_t __spare__[2];
+};
+#endif
+
+#endif /* !_MACHINE_SIGFRAME_H_ */
Property changes on: trunk/sys/mips/include/sigframe.h
___________________________________________________________________
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Added: trunk/sys/mips/include/signal.h
===================================================================
--- trunk/sys/mips/include/signal.h (rev 0)
+++ trunk/sys/mips/include/signal.h 2018-05-26 21:55:02 UTC (rev 9987)
@@ -0,0 +1,81 @@
+/* $MidnightBSD$ */
+/* $OpenBSD: signal.h,v 1.2 1999/01/27 04:10:03 imp Exp $ */
+
+/*
+ * Copyright (c) 1992, 1993
+ * The Regents of the University of California. All rights reserved.
+ *
+ * This code is derived from software contributed to Berkeley by
+ * Ralph Campbell.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * 4. Neither the name of the University nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ * @(#)signal.h 8.1 (Berkeley) 6/10/93
+ * JNPR: signal.h,v 1.4 2007/01/08 04:58:37 katta
+ * $FreeBSD: stable/10/sys/mips/include/signal.h 202175 2010-01-12 21:36:08Z imp $
+ */
+
+#ifndef _MACHINE_SIGNAL_H_
+#define _MACHINE_SIGNAL_H_
+
+#include <sys/cdefs.h>
+#include <sys/_sigset.h>
+
+/*
+ * Machine-dependent signal definitions
+ */
+
+typedef int sig_atomic_t;
+
+#if !defined(_ANSI_SOURCE) && !defined(_POSIX_SOURCE)
+/*
+ * Information pushed on stack when a signal is delivered.
+ * This is used by the kernel to restore state following
+ * execution of the signal handler. It is also made available
+ * to the handler to allow it to restore state properly if
+ * a non-standard exit is performed.
+ */
+
+struct sigcontext {
+ /*
+ * The fields following 'sc_mask' must match the definition
+ * of struct __mcontext. That way we can support
+ * struct sigcontext and ucontext_t at the same
+ * time.
+ */
+ __sigset_t sc_mask; /* signal mask to restore */
+ int sc_onstack; /* sigstack state to restore */
+ __register_t sc_pc; /* pc at time of signal */
+ __register_t sc_regs[32]; /* processor regs 0 to 31 */
+ __register_t mullo, mulhi; /* mullo and mulhi registers... */
+ int sc_fpused; /* fp has been used */
+ f_register_t sc_fpregs[33]; /* fp regs 0 to 31 and csr */
+ __register_t sc_fpc_eir; /* fp exception instruction reg */
+ int xxx[8]; /* XXX reserved */
+};
+
+#endif /* !_ANSI_SOURCE && !_POSIX_SOURCE */
+
+#endif /* !_MACHINE_SIGNAL_H_ */
Property changes on: trunk/sys/mips/include/signal.h
___________________________________________________________________
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Added: trunk/sys/mips/include/smp.h
===================================================================
--- trunk/sys/mips/include/smp.h (rev 0)
+++ trunk/sys/mips/include/smp.h 2018-05-26 21:55:02 UTC (rev 9987)
@@ -0,0 +1,48 @@
+/* $MidnightBSD$ */
+/*-
+ * ----------------------------------------------------------------------------
+ * "THE BEER-WARE LICENSE" (Revision 42):
+ * <phk at FreeBSD.org> wrote this file. As long as you retain this notice you
+ * can do whatever you want with this stuff. If we meet some day, and you think
+ * this stuff is worth it, you can buy me a beer in return. Poul-Henning Kamp
+ * ----------------------------------------------------------------------------
+ *
+ * from: src/sys/alpha/include/smp.h,v 1.8 2005/01/05 20:05:50 imp
+ * JNPR: smp.h,v 1.3 2006/12/02 09:53:41 katta
+ * $FreeBSD: stable/10/sys/mips/include/smp.h 222813 2011-06-07 08:46:13Z attilio $
+ *
+ */
+
+#ifndef _MACHINE_SMP_H_
+#define _MACHINE_SMP_H_
+
+#ifdef _KERNEL
+
+#include <sys/_cpuset.h>
+
+#include <machine/pcb.h>
+
+/*
+ * Interprocessor interrupts for SMP.
+ */
+#define IPI_RENDEZVOUS 0x0002
+#define IPI_AST 0x0004
+#define IPI_STOP 0x0008
+#define IPI_STOP_HARD 0x0008
+#define IPI_PREEMPT 0x0010
+#define IPI_HARDCLOCK 0x0020
+
+#ifndef LOCORE
+
+void ipi_all_but_self(int ipi);
+void ipi_cpu(int cpu, u_int ipi);
+void ipi_selected(cpuset_t cpus, int ipi);
+void smp_init_secondary(u_int32_t cpuid);
+void mpentry(void);
+
+extern struct pcb stoppcbs[];
+
+#endif /* !LOCORE */
+#endif /* _KERNEL */
+
+#endif /* _MACHINE_SMP_H_ */
Property changes on: trunk/sys/mips/include/smp.h
___________________________________________________________________
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Added: trunk/sys/mips/include/stdarg.h
===================================================================
--- trunk/sys/mips/include/stdarg.h (rev 0)
+++ trunk/sys/mips/include/stdarg.h 2018-05-26 21:55:02 UTC (rev 9987)
@@ -0,0 +1,145 @@
+/* $MidnightBSD$ */
+/*
+ * JNPR: stdarg.h,v 1.3 2006/09/15 12:52:34 katta
+ * $FreeBSD: stable/10/sys/mips/include/stdarg.h 202175 2010-01-12 21:36:08Z imp $
+ */
+
+#ifndef _MACHINE_STDARG_H_
+#define _MACHINE_STDARG_H_
+#include <sys/cdefs.h>
+#include <sys/_types.h>
+
+
+#if __GNUC__ >= 3
+
+#ifndef _VA_LIST_DECLARED
+#define _VA_LIST_DECLARED
+typedef __va_list va_list;
+#endif
+#define va_start(v,l) __builtin_va_start((v),l)
+#define va_end __builtin_va_end
+#define va_arg __builtin_va_arg
+#define va_copy __builtin_va_copy
+
+#else /* __GNUC__ */
+
+
+/* ---------------------------------------- */
+/* VARARGS for MIPS/GNU CC */
+/* ---------------------------------------- */
+
+#include <machine/endian.h>
+
+/* These macros implement varargs for GNU C--either traditional or ANSI. */
+
+/* Define __gnuc_va_list. */
+
+#ifndef __GNUC_VA_LIST
+#define __GNUC_VA_LIST
+
+typedef char * __gnuc_va_list;
+typedef __gnuc_va_list va_list;
+
+#endif /* ! __GNUC_VA_LIST */
+
+/* If this is for internal libc use, don't define anything but
+ __gnuc_va_list. */
+
+#ifndef _VA_MIPS_H_ENUM
+#define _VA_MIPS_H_ENUM
+enum {
+ __no_type_class = -1,
+ __void_type_class,
+ __integer_type_class,
+ __char_type_class,
+ __enumeral_type_class,
+ __boolean_type_class,
+ __pointer_type_class,
+ __reference_type_class,
+ __offset_type_class,
+ __real_type_class,
+ __complex_type_class,
+ __function_type_class,
+ __method_type_class,
+ __record_type_class,
+ __union_type_class,
+ __array_type_class,
+ __string_type_class,
+ __set_type_class,
+ __file_type_class,
+ __lang_type_class
+};
+#endif
+
+/* In GCC version 2, we want an ellipsis at the end of the declaration
+ of the argument list. GCC version 1 can't parse it. */
+
+#if __GNUC__ > 1
+#define __va_ellipsis ...
+#else
+#define __va_ellipsis
+#endif
+
+
+#define va_start(__AP, __LASTARG) \
+ (__AP = (__gnuc_va_list) __builtin_next_arg (__LASTARG))
+
+#define va_end(__AP) ((void)0)
+
+
+/* We cast to void * and then to TYPE * because this avoids
+ a warning about increasing the alignment requirement. */
+/* The __mips64 cases are reversed from the 32 bit cases, because the standard
+ 32 bit calling convention left-aligns all parameters smaller than a word,
+ whereas the __mips64 calling convention does not (and hence they are
+ right aligned). */
+
+#ifdef __mips64
+
+#define __va_rounded_size(__TYPE) (((sizeof (__TYPE) + 8 - 1) / 8) * 8)
+
+#define __va_reg_size 8
+
+#if defined(__MIPSEB__) || (BYTE_ORDER == BIG_ENDIAN)
+#define va_arg(__AP, __type) \
+ ((__type *) (void *) (__AP = (char *) \
+ ((((__PTRDIFF_TYPE__)__AP + 8 - 1) & -8) \
+ + __va_rounded_size (__type))))[-1]
+#else /* ! __MIPSEB__ && !BYTE_ORDER == BIG_ENDIAN */
+#define va_arg(__AP, __type) \
+ ((__AP = (char *) ((((__PTRDIFF_TYPE__)__AP + 8 - 1) & -8) \
+ + __va_rounded_size (__type))), \
+ *(__type *) (void *) (__AP - __va_rounded_size (__type)))
+#endif /* ! __MIPSEB__ && !BYTE_ORDER == BIG_ENDIAN */
+
+#else /* ! __mips64 */
+
+#define __va_rounded_size(__TYPE) \
+ (((sizeof (__TYPE) + sizeof (int) - 1) / sizeof (int)) * sizeof (int))
+
+#define __va_reg_size 4
+
+#if defined(__MIPSEB__) || (BYTE_ORDER == BIG_ENDIAN)
+/* For big-endian machines. */
+#define va_arg(__AP, __type) \
+ ((__AP = (char *) ((__alignof__ (__type) > 4 \
+ ? ((__PTRDIFF_TYPE__)__AP + 8 - 1) & -8 \
+ : ((__PTRDIFF_TYPE__)__AP + 4 - 1) & -4) \
+ + __va_rounded_size (__type))), \
+ *(__type *) (void *) (__AP - __va_rounded_size (__type)))
+#else /* ! __MIPSEB__ && !BYTE_ORDER == BIG_ENDIAN */
+/* For little-endian machines. */
+#define va_arg(__AP, __type) \
+ ((__type *) (void *) (__AP = (char *) ((__alignof__(__type) > 4 \
+ ? ((__PTRDIFF_TYPE__)__AP + 8 - 1) & -8 \
+ : ((__PTRDIFF_TYPE__)__AP + 4 - 1) & -4) \
+ + __va_rounded_size(__type))))[-1]
+#endif /* ! __MIPSEB__ && !BYTE_ORDER == BIG_ENDIAN */
+#endif /* ! __mips64 */
+
+/* Copy __gnuc_va_list into another variable of this type. */
+#define __va_copy(dest, src) (dest) = (src)
+#define va_copy(dest, src) (dest) = (src)
+
+#endif /* __GNUC__ */
+#endif /* _MACHINE_STDARG_H_ */
Property changes on: trunk/sys/mips/include/stdarg.h
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Added: trunk/sys/mips/include/sysarch.h
===================================================================
--- trunk/sys/mips/include/sysarch.h (rev 0)
+++ trunk/sys/mips/include/sysarch.h 2018-05-26 21:55:02 UTC (rev 9987)
@@ -0,0 +1,50 @@
+/* $MidnightBSD$ */
+/*-
+ * Copyright (c) 1993 The Regents of the University of California.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * 4. Neither the name of the University nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ * $FreeBSD: stable/10/sys/mips/include/sysarch.h 202175 2010-01-12 21:36:08Z imp $
+ */
+
+/*
+ * Architecture specific syscalls (MIPS)
+ */
+#ifndef _MACHINE_SYSARCH_H_
+#define _MACHINE_SYSARCH_H_
+
+#define MIPS_SET_TLS 1
+#define MIPS_GET_TLS 2
+
+#ifndef _KERNEL
+#include <sys/cdefs.h>
+
+__BEGIN_DECLS
+int sysarch(int, void *);
+__END_DECLS
+#endif
+
+#endif /* !_MACHINE_SYSARCH_H_ */
Property changes on: trunk/sys/mips/include/sysarch.h
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Added: trunk/sys/mips/include/tlb.h
===================================================================
--- trunk/sys/mips/include/tlb.h (rev 0)
+++ trunk/sys/mips/include/tlb.h 2018-05-26 21:55:02 UTC (rev 9987)
@@ -0,0 +1,61 @@
+/* $MidnightBSD$ */
+/*-
+ * Copyright (c) 2004-2010 Juli Mallett <jmallett at FreeBSD.org>
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ * $FreeBSD: stable/10/sys/mips/include/tlb.h 241123 2012-10-02 07:14:22Z alc $
+ */
+
+#ifndef _MACHINE_TLB_H_
+#define _MACHINE_TLB_H_
+
+/*
+ * The first TLB entry that write random hits.
+ * TLB entry 0 maps the kernel stack of the currently running thread
+ * TLB entry 1 maps the pcpu area of processor (only for SMP builds)
+ */
+#define KSTACK_TLB_ENTRY 0
+#ifdef SMP
+#define PCPU_TLB_ENTRY 1
+#define VMWIRED_ENTRIES 2
+#else
+#define VMWIRED_ENTRIES 1
+#endif /* SMP */
+
+/*
+ * The number of process id entries.
+ */
+#define VMNUM_PIDS 256
+
+extern int num_tlbentries;
+
+void tlb_insert_wired(unsigned, vm_offset_t, pt_entry_t, pt_entry_t);
+void tlb_invalidate_address(struct pmap *, vm_offset_t);
+void tlb_invalidate_all(void);
+void tlb_invalidate_all_user(struct pmap *);
+void tlb_invalidate_range(struct pmap *, vm_offset_t, vm_offset_t);
+void tlb_save(void);
+void tlb_update(struct pmap *, vm_offset_t, pt_entry_t);
+
+#endif /* !_MACHINE_TLB_H_ */
Property changes on: trunk/sys/mips/include/tlb.h
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Added: trunk/sys/mips/include/tls.h
===================================================================
--- trunk/sys/mips/include/tls.h (rev 0)
+++ trunk/sys/mips/include/tls.h 2018-05-26 21:55:02 UTC (rev 9987)
@@ -0,0 +1,56 @@
+/* $MidnightBSD$ */
+/*-
+ * Copyright (c) 2012 Oleksandr Tymoshenko
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions, and the following disclaimer,
+ * without modification, immediately at the beginning of the file.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in
+ * the documentation and/or other materials provided with the
+ * distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ * $FreeBSD: stable/10/sys/mips/include/tls.h 232583 2012-03-06 07:47:28Z jmallett $
+ *
+ */
+
+#ifndef __MIPS_TLS_H__
+#define __MIPS_TLS_H__
+
+#if defined(_KERNEL) && !defined(KLD_MODULE) && !defined(_STANDALONE)
+#include "opt_compat.h"
+#endif
+
+/*
+ * TLS parameters
+ */
+
+#define TLS_TP_OFFSET 0x7000
+#define TLS_DTP_OFFSET 0x8000
+
+#ifdef __mips_n64
+#define TLS_TCB_SIZE 16
+#ifdef COMPAT_FREEBSD32
+#define TLS_TCB_SIZE32 8
+#endif
+#else
+#define TLS_TCB_SIZE 8
+#endif
+
+#endif /* __MIPS_TLS_H__ */
Property changes on: trunk/sys/mips/include/tls.h
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Added: trunk/sys/mips/include/trap.h
===================================================================
--- trunk/sys/mips/include/trap.h (rev 0)
+++ trunk/sys/mips/include/trap.h 2018-05-26 21:55:02 UTC (rev 9987)
@@ -0,0 +1,122 @@
+/* $MidnightBSD$ */
+/* $OpenBSD: trap.h,v 1.3 1999/01/27 04:46:06 imp Exp $ */
+
+/*-
+ * Copyright (c) 1988 University of Utah.
+ * Copyright (c) 1992, 1993
+ * The Regents of the University of California. All rights reserved.
+ *
+ * This code is derived from software contributed to Berkeley by
+ * the Systems Programming Group of the University of Utah Computer
+ * Science Department and Ralph Campbell.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * 4. Neither the name of the University nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ * from: Utah Hdr: trap.h 1.1 90/07/09
+ * from: @(#)trap.h 8.1 (Berkeley) 6/10/93
+ * JNPR: trap.h,v 1.3 2006/12/02 09:53:41 katta
+ * $FreeBSD: stable/10/sys/mips/include/trap.h 232853 2012-03-12 07:34:15Z jmallett $
+ */
+
+#ifndef _MACHINE_TRAP_H_
+#define _MACHINE_TRAP_H_
+
+/*
+ * Trap codes also known in trap.c for name strings.
+ * Used for indexing so modify with care.
+ */
+
+#define T_INT 0 /* Interrupt pending */
+#define T_TLB_MOD 1 /* TLB modified fault */
+#define T_TLB_LD_MISS 2 /* TLB miss on load or ifetch */
+#define T_TLB_ST_MISS 3 /* TLB miss on a store */
+#define T_ADDR_ERR_LD 4 /* Address error on a load or ifetch */
+#define T_ADDR_ERR_ST 5 /* Address error on a store */
+#define T_BUS_ERR_IFETCH 6 /* Bus error on an ifetch */
+#define T_BUS_ERR_LD_ST 7 /* Bus error on a load or store */
+#define T_SYSCALL 8 /* System call */
+#define T_BREAK 9 /* Breakpoint */
+#define T_RES_INST 10 /* Reserved instruction exception */
+#define T_COP_UNUSABLE 11 /* Coprocessor unusable */
+#define T_OVFLOW 12 /* Arithmetic overflow */
+#define T_TRAP 13 /* Trap instruction */
+#define T_VCEI 14 /* Virtual coherency instruction */
+#define T_FPE 15 /* Floating point exception */
+#define T_IWATCH 16 /* Inst. Watch address reference */
+#define T_C2E 18 /* Exception from coprocessor 2 */
+#define T_DWATCH 23 /* Data Watch address reference */
+#define T_MCHECK 24 /* Received an MCHECK */
+#define T_VCED 31 /* Virtual coherency data */
+
+#define T_USER 0x20 /* user-mode flag or'ed with type */
+
+#if !defined(SMP) && (defined(DDB) || defined(DEBUG))
+
+struct trapdebug { /* trap history buffer for debugging */
+ register_t status;
+ register_t cause;
+ register_t vadr;
+ register_t pc;
+ register_t ra;
+ register_t sp;
+ register_t code;
+};
+
+#define trapdebug_enter(x, cd) { \
+ register_t s = intr_disable(); \
+ trp->status = x->sr; \
+ trp->cause = x->cause; \
+ trp->vadr = x->badvaddr; \
+ trp->pc = x->pc; \
+ trp->sp = x->sp; \
+ trp->ra = x->ra; \
+ trp->code = cd; \
+ if (++trp == &trapdebug[TRAPSIZE]) \
+ trp = trapdebug; \
+ intr_restore(s); \
+}
+
+#define TRAPSIZE 10 /* Trap log buffer length */
+extern struct trapdebug trapdebug[TRAPSIZE], *trp;
+
+void trapDump(char *msg);
+
+#else
+
+#define trapdebug_enter(x, cd)
+
+#endif
+
+void MipsFPTrap(u_int, u_int, u_int);
+void MipsKernGenException(void);
+void MipsKernIntr(void);
+void MipsTLBInvalidException(void);
+void MipsTLBMissException(void);
+void MipsUserGenException(void);
+void MipsUserIntr(void);
+
+register_t trap(struct trapframe *);
+
+#endif /* !_MACHINE_TRAP_H_ */
Property changes on: trunk/sys/mips/include/trap.h
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Added: trunk/sys/mips/include/ucontext.h
===================================================================
--- trunk/sys/mips/include/ucontext.h (rev 0)
+++ trunk/sys/mips/include/ucontext.h 2018-05-26 21:55:02 UTC (rev 9987)
@@ -0,0 +1,139 @@
+/* $MidnightBSD$ */
+/*
+ * Copyright (c) 1992, 1993
+ * The Regents of the University of California. All rights reserved.
+ *
+ * This code is derived from software contributed to Berkeley by
+ * Ralph Campbell.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * 4. Neither the name of the University nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ * @(#)ucontext.h 8.1 (Berkeley) 6/10/93
+ * JNPR: ucontext.h,v 1.2 2007/08/09 11:23:32 katta
+ * $FreeBSD: stable/10/sys/mips/include/ucontext.h 232584 2012-03-06 07:50:45Z jmallett $
+ */
+
+#ifndef _MACHINE_UCONTEXT_H_
+#define _MACHINE_UCONTEXT_H_
+
+#ifndef _LOCORE
+
+#if defined(_KERNEL) && !defined(KLD_MODULE) && !defined(_STANDALONE)
+#include "opt_compat.h"
+#endif
+
+typedef struct __mcontext {
+ /*
+ * These fields must match the corresponding fields in struct
+ * sigcontext which follow 'sc_mask'. That way we can support
+ * struct sigcontext and ucontext_t at the same time.
+ */
+ int mc_onstack; /* sigstack state to restore */
+ register_t mc_pc; /* pc at time of signal */
+ register_t mc_regs[32]; /* processor regs 0 to 31 */
+ register_t sr; /* status register */
+ register_t mullo, mulhi; /* mullo and mulhi registers... */
+ int mc_fpused; /* fp has been used */
+ f_register_t mc_fpregs[33]; /* fp regs 0 to 31 and csr */
+ register_t mc_fpc_eir; /* fp exception instruction reg */
+ void *mc_tls; /* pointer to TLS area */
+ int __spare__[8]; /* XXX reserved */
+} mcontext_t;
+
+#if (defined(__mips_n32) || defined(__mips_n64)) && defined(COMPAT_FREEBSD32)
+#include <compat/freebsd32/freebsd32_signal.h>
+
+typedef struct __mcontext32 {
+ int mc_onstack;
+ int32_t mc_pc;
+ int32_t mc_regs[32];
+ int32_t sr;
+ int32_t mullo, mulhi;
+ int mc_fpused;
+ int32_t mc_fpregs[33];
+ int32_t mc_fpc_eir;
+ int32_t mc_tls;
+ int __spare__[8];
+} mcontext32_t;
+
+typedef struct __ucontext32 {
+ sigset_t uc_sigmask;
+ mcontext32_t uc_mcontext;
+ uint32_t uc_link;
+ struct sigaltstack32 uc_stack;
+ uint32_t uc_flags;
+ uint32_t __spare__[4];
+} ucontext32_t;
+#endif
+#endif
+
+#ifndef SZREG
+#if defined(__mips_o32)
+#define SZREG 4
+#else
+#define SZREG 8
+#endif
+#endif
+
+/* offsets into mcontext_t */
+#define UCTX_REG(x) (4 + SZREG + (x)*SZREG)
+
+#define UCR_ZERO UCTX_REG(0)
+#define UCR_AT UCTX_REG(1)
+#define UCR_V0 UCTX_REG(2)
+#define UCR_V1 UCTX_REG(3)
+#define UCR_A0 UCTX_REG(4)
+#define UCR_A1 UCTX_REG(5)
+#define UCR_A2 UCTX_REG(6)
+#define UCR_A3 UCTX_REG(7)
+#define UCR_T0 UCTX_REG(8)
+#define UCR_T1 UCTX_REG(9)
+#define UCR_T2 UCTX_REG(10)
+#define UCR_T3 UCTX_REG(11)
+#define UCR_T4 UCTX_REG(12)
+#define UCR_T5 UCTX_REG(13)
+#define UCR_T6 UCTX_REG(14)
+#define UCR_T7 UCTX_REG(15)
+#define UCR_S0 UCTX_REG(16)
+#define UCR_S1 UCTX_REG(17)
+#define UCR_S2 UCTX_REG(18)
+#define UCR_S3 UCTX_REG(19)
+#define UCR_S4 UCTX_REG(20)
+#define UCR_S5 UCTX_REG(21)
+#define UCR_S6 UCTX_REG(22)
+#define UCR_S7 UCTX_REG(23)
+#define UCR_T8 UCTX_REG(24)
+#define UCR_T9 UCTX_REG(25)
+#define UCR_K0 UCTX_REG(26)
+#define UCR_K1 UCTX_REG(27)
+#define UCR_GP UCTX_REG(28)
+#define UCR_SP UCTX_REG(29)
+#define UCR_S8 UCTX_REG(30)
+#define UCR_RA UCTX_REG(31)
+#define UCR_SR UCTX_REG(32)
+#define UCR_MDLO UCTX_REG(33)
+#define UCR_MDHI UCTX_REG(34)
+
+#endif /* !_MACHINE_UCONTEXT_H_ */
Property changes on: trunk/sys/mips/include/ucontext.h
___________________________________________________________________
Added: svn:eol-style
## -0,0 +1 ##
+native
\ No newline at end of property
Added: svn:keywords
## -0,0 +1 ##
+MidnightBSD=%H
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+text/plain
\ No newline at end of property
Added: trunk/sys/mips/include/varargs.h
===================================================================
--- trunk/sys/mips/include/varargs.h (rev 0)
+++ trunk/sys/mips/include/varargs.h 2018-05-26 21:55:02 UTC (rev 9987)
@@ -0,0 +1,60 @@
+/* $MidnightBSD$ */
+/* $NetBSD: varargs.h,v 1.16 1999/01/22 14:19:54 mycroft Exp $ */
+
+/*-
+ * Copyright (c) 1992, 1993
+ * The Regents of the University of California. All rights reserved.
+ * (c) UNIX System Laboratories, Inc.
+ * All or some portions of this file are derived from material licensed
+ * to the University of California by American Telephone and Telegraph
+ * Co. or Unix System Laboratories, Inc. and are reproduced herein with
+ * the permission of UNIX System Laboratories, Inc.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * 4. Neither the name of the University nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ * @(#)varargs.h 8.2 (Berkeley) 3/22/94
+ * JNPR: varargs.h,v 1.1 2006/08/07 05:38:57 katta
+ * $FreeBSD: stable/10/sys/mips/include/varargs.h 202175 2010-01-12 21:36:08Z imp $
+ */
+
+#ifndef _MIPS_VARARGS_H_
+#define _MIPS_VARARGS_H_
+
+#include <machine/stdarg.h>
+
+#if __GNUC__ == 1
+#define __va_ellipsis
+#else
+#define __va_ellipsis ...
+#endif
+
+#define va_alist __builtin_va_alist
+#define va_dcl long __builtin_va_alist; __va_ellipsis
+
+#undef va_start
+#define va_start(ap) \
+ ((ap) = (va_list)&__builtin_va_alist)
+
+#endif /* !_MIPS_VARARGS_H_ */
Property changes on: trunk/sys/mips/include/varargs.h
___________________________________________________________________
Added: svn:eol-style
## -0,0 +1 ##
+native
\ No newline at end of property
Added: svn:keywords
## -0,0 +1 ##
+MidnightBSD=%H
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+text/plain
\ No newline at end of property
Added: trunk/sys/mips/include/vdso.h
===================================================================
--- trunk/sys/mips/include/vdso.h (rev 0)
+++ trunk/sys/mips/include/vdso.h 2018-05-26 21:55:02 UTC (rev 9987)
@@ -0,0 +1,42 @@
+/* $MidnightBSD$ */
+/*-
+ * Copyright 2012 Konstantin Belousov <kib at FreeBSD.ORG>.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+ * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+ * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * $FreeBSD: stable/10/sys/mips/include/vdso.h 237433 2012-06-22 07:06:40Z kib $
+ */
+
+#ifndef _MIPS_VDSO_H
+#define _MIPS_VDSO_H
+
+#define VDSO_TIMEHANDS_MD \
+ uint32_t th_res[8];
+
+#ifdef _KERNEL
+#ifdef COMPAT_FREEBSD32
+
+#define VDSO_TIMEHANDS_MD32 VDSO_TIMEHANDS_MD
+
+#endif
+#endif
+#endif
Property changes on: trunk/sys/mips/include/vdso.h
___________________________________________________________________
Added: svn:eol-style
## -0,0 +1 ##
+native
\ No newline at end of property
Added: svn:keywords
## -0,0 +1 ##
+MidnightBSD=%H
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+text/plain
\ No newline at end of property
Added: trunk/sys/mips/include/vm.h
===================================================================
--- trunk/sys/mips/include/vm.h (rev 0)
+++ trunk/sys/mips/include/vm.h 2018-05-26 21:55:02 UTC (rev 9987)
@@ -0,0 +1,39 @@
+/* $MidnightBSD$ */
+/*-
+ * Copyright (c) 2009 Alan L. Cox <alc at cs.rice.edu>
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ * $FreeBSD: stable/10/sys/mips/include/vm.h 233670 2012-03-29 16:48:36Z jhb $
+ */
+
+#ifndef _MACHINE_VM_H_
+#define _MACHINE_VM_H_
+
+#include <machine/pte.h>
+
+/* Memory attributes. */
+#define VM_MEMATTR_UNCACHEABLE ((vm_memattr_t)PTE_C_UNCACHED)
+#define VM_MEMATTR_DEFAULT ((vm_memattr_t)PTE_C_CACHE)
+
+#endif /* !_MACHINE_VM_H_ */
Property changes on: trunk/sys/mips/include/vm.h
___________________________________________________________________
Added: svn:eol-style
## -0,0 +1 ##
+native
\ No newline at end of property
Added: svn:keywords
## -0,0 +1 ##
+MidnightBSD=%H
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+text/plain
\ No newline at end of property
Added: trunk/sys/mips/include/vmparam.h
===================================================================
--- trunk/sys/mips/include/vmparam.h (rev 0)
+++ trunk/sys/mips/include/vmparam.h 2018-05-26 21:55:02 UTC (rev 9987)
@@ -0,0 +1,189 @@
+/* $MidnightBSD$ */
+/* $OpenBSD: vmparam.h,v 1.2 1998/09/15 10:50:12 pefo Exp $ */
+/* $NetBSD: vmparam.h,v 1.5 1994/10/26 21:10:10 cgd Exp $ */
+
+/*
+ * Copyright (c) 1988 University of Utah.
+ * Copyright (c) 1992, 1993
+ * The Regents of the University of California. All rights reserved.
+ *
+ * This code is derived from software contributed to Berkeley by
+ * the Systems Programming Group of the University of Utah Computer
+ * Science Department and Ralph Campbell.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * 4. Neither the name of the University nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ * from: Utah Hdr: vmparam.h 1.16 91/01/18
+ * @(#)vmparam.h 8.2 (Berkeley) 4/22/94
+ * JNPR: vmparam.h,v 1.3.2.1 2007/09/10 06:01:28 girish
+ * $FreeBSD: stable/10/sys/mips/include/vmparam.h 285634 2015-07-16 14:41:58Z kib $
+ */
+
+#ifndef _MACHINE_VMPARAM_H_
+#define _MACHINE_VMPARAM_H_
+
+/*
+ * Machine dependent constants mips processors.
+ */
+
+/*
+ * Virtual memory related constants, all in bytes
+ */
+#ifndef MAXTSIZ
+#define MAXTSIZ (128UL*1024*1024) /* max text size */
+#endif
+#ifndef DFLDSIZ
+#define DFLDSIZ (128UL*1024*1024) /* initial data size limit */
+#endif
+#ifndef MAXDSIZ
+#define MAXDSIZ (1*1024UL*1024*1024) /* max data size */
+#endif
+#ifndef DFLSSIZ
+#define DFLSSIZ (8UL*1024*1024) /* initial stack size limit */
+#endif
+#ifndef MAXSSIZ
+#define MAXSSIZ (64UL*1024*1024) /* max stack size */
+#endif
+#ifndef SGROWSIZ
+#define SGROWSIZ (128UL*1024) /* amount to grow stack */
+#endif
+
+/*
+ * Mach derived constants
+ */
+
+/* user/kernel map constants */
+#define VM_MIN_ADDRESS ((vm_offset_t)0x00000000)
+#define VM_MAX_ADDRESS ((vm_offset_t)(intptr_t)(int32_t)0xffffffff)
+
+#define VM_MINUSER_ADDRESS ((vm_offset_t)0x00000000)
+
+#ifdef __mips_n64
+#define VM_MAXUSER_ADDRESS (VM_MINUSER_ADDRESS + (NPDEPG * NBSEG))
+#define VM_MIN_KERNEL_ADDRESS ((vm_offset_t)0xc000000000000000)
+#define VM_MAX_KERNEL_ADDRESS (VM_MIN_KERNEL_ADDRESS + (NPDEPG * NBSEG))
+#else
+#define VM_MAXUSER_ADDRESS ((vm_offset_t)0x80000000)
+#define VM_MIN_KERNEL_ADDRESS ((vm_offset_t)0xC0000000)
+#define VM_MAX_KERNEL_ADDRESS ((vm_offset_t)0xFFFFC000)
+#endif
+
+#define KERNBASE ((vm_offset_t)(intptr_t)(int32_t)0x80000000)
+/*
+ * USRSTACK needs to start a little below 0x8000000 because the R8000
+ * and some QED CPUs perform some virtual address checks before the
+ * offset is calculated.
+ */
+#define USRSTACK (VM_MAXUSER_ADDRESS - PAGE_SIZE)
+#ifdef __mips_n64
+#define FREEBSD32_USRSTACK (((vm_offset_t)0x80000000) - PAGE_SIZE)
+#endif
+
+/*
+ * Disable superpage reservations. (not sure if this is right
+ * I copied it from ARM)
+ */
+#ifndef VM_NRESERVLEVEL
+#define VM_NRESERVLEVEL 0
+#endif
+
+/*
+ * How many physical pages per kmem arena virtual page.
+ */
+#ifndef VM_KMEM_SIZE_SCALE
+#define VM_KMEM_SIZE_SCALE (3)
+#endif
+
+/*
+ * Optional floor (in bytes) on the size of the kmem arena.
+ */
+#ifndef VM_KMEM_SIZE_MIN
+#define VM_KMEM_SIZE_MIN (12 * 1024 * 1024)
+#endif
+
+/*
+ * Optional ceiling (in bytes) on the size of the kmem arena: 40% of the
+ * kernel map.
+ */
+#ifndef VM_KMEM_SIZE_MAX
+#define VM_KMEM_SIZE_MAX ((VM_MAX_KERNEL_ADDRESS - \
+ VM_MIN_KERNEL_ADDRESS + 1) * 2 / 5)
+#endif
+
+/* initial pagein size of beginning of executable file */
+#ifndef VM_INITIAL_PAGEIN
+#define VM_INITIAL_PAGEIN 16
+#endif
+
+#define UMA_MD_SMALL_ALLOC
+
+/*
+ * max number of non-contig chunks of physical RAM you can have
+ */
+#define VM_PHYSSEG_MAX 32
+
+/*
+ * The physical address space is sparsely populated.
+ */
+#define VM_PHYSSEG_SPARSE
+
+/*
+ * Create three free page pools: VM_FREEPOOL_DEFAULT is the default pool
+ * from which physical pages are allocated and VM_FREEPOOL_DIRECT is
+ * the pool from which physical pages for small UMA objects are
+ * allocated.
+ */
+#define VM_NFREEPOOL 3
+#define VM_FREEPOOL_CACHE 2
+#define VM_FREEPOOL_DEFAULT 0
+#define VM_FREEPOOL_DIRECT 1
+
+/*
+ * Create up to two free lists on !__mips_n64: VM_FREELIST_DEFAULT is for
+ * physical pages that are above the largest physical address that is
+ * accessible through the direct map (KSEG0) and VM_FREELIST_LOWMEM is for
+ * physical pages that are below that address. VM_LOWMEM_BOUNDARY is the
+ * physical address for the end of the direct map (KSEG0).
+ */
+#ifdef __mips_n64
+#define VM_NFREELIST 1
+#define VM_FREELIST_DEFAULT 0
+#define VM_FREELIST_DIRECT VM_FREELIST_DEFAULT
+#else
+#define VM_NFREELIST 2
+#define VM_FREELIST_DEFAULT 0
+#define VM_FREELIST_LOWMEM 1
+#define VM_FREELIST_DIRECT VM_FREELIST_LOWMEM
+#define VM_LOWMEM_BOUNDARY ((vm_paddr_t)0x20000000)
+#endif
+
+/*
+ * The largest allocation size is 1MB.
+ */
+#define VM_NFREEORDER 9
+
+#define ZERO_REGION_SIZE (64 * 1024) /* 64KB */
+
+#endif /* !_MACHINE_VMPARAM_H_ */
Property changes on: trunk/sys/mips/include/vmparam.h
___________________________________________________________________
Added: svn:eol-style
## -0,0 +1 ##
+native
\ No newline at end of property
Added: svn:keywords
## -0,0 +1 ##
+MidnightBSD=%H
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+text/plain
\ No newline at end of property
Added: trunk/sys/mips/malta/files.malta
===================================================================
--- trunk/sys/mips/malta/files.malta (rev 0)
+++ trunk/sys/mips/malta/files.malta 2018-05-26 21:55:02 UTC (rev 9987)
@@ -0,0 +1,12 @@
+# $FreeBSD: stable/10/sys/mips/malta/files.malta 255083 2013-08-30 20:28:35Z gonzo $
+mips/malta/gt.c standard
+mips/malta/gt_pci.c standard
+mips/malta/gt_pci_bus_space.c standard
+mips/malta/obio.c optional uart
+mips/malta/uart_cpu_maltausart.c optional uart
+mips/malta/uart_bus_maltausart.c optional uart
+dev/uart/uart_dev_ns8250.c optional uart
+mips/malta/malta_machdep.c standard
+mips/malta/yamon.c standard
+mips/mips/intr_machdep.c standard
+mips/mips/tick.c standard
Property changes on: trunk/sys/mips/malta/files.malta
___________________________________________________________________
Added: mnbsd:nokeywords
## -0,0 +1 ##
+MidnightBSD=%H
\ No newline at end of property
Added: trunk/sys/mips/malta/gt.c
===================================================================
--- trunk/sys/mips/malta/gt.c (rev 0)
+++ trunk/sys/mips/malta/gt.c 2018-05-26 21:55:02 UTC (rev 9987)
@@ -0,0 +1,131 @@
+/* $MidnightBSD$ */
+/*-
+ * Copyright (c) 2005 Olivier Houchard. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+ * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+ * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <sys/cdefs.h>
+__FBSDID("$FreeBSD: stable/10/sys/mips/malta/gt.c 265999 2014-05-14 01:35:43Z ian $");
+
+#include <sys/param.h>
+#include <sys/systm.h>
+#include <sys/bus.h>
+#include <sys/kernel.h>
+#include <sys/malloc.h>
+#include <sys/module.h>
+#include <sys/rman.h>
+#include <sys/types.h>
+
+#include <vm/vm.h>
+#include <vm/vm_kern.h>
+#include <vm/pmap.h>
+#include <vm/vm_page.h>
+#include <vm/vm_extern.h>
+
+#include <dev/ic/i8259.h>
+
+#include <machine/bus.h>
+#include <machine/intr_machdep.h>
+
+#include <mips/malta/gtvar.h>
+
+static int
+gt_probe(device_t dev)
+{
+ device_set_desc(dev, "GT64120 chip");
+ return (BUS_PROBE_NOWILDCARD);
+}
+
+static void
+gt_identify(driver_t *drv, device_t parent)
+{
+ BUS_ADD_CHILD(parent, 0, "gt", 0);
+}
+
+static int
+gt_attach(device_t dev)
+{
+ struct gt_softc *sc = device_get_softc(dev);
+ sc->dev = dev;
+
+ device_add_child(dev, "pcib", 0);
+ bus_generic_probe(dev);
+ bus_generic_attach(dev);
+
+
+ return (0);
+}
+
+static struct resource *
+gt_alloc_resource(device_t dev, device_t child, int type, int *rid,
+ u_long start, u_long end, u_long count, u_int flags)
+{
+ return (BUS_ALLOC_RESOURCE(device_get_parent(dev), child,
+ type, rid, start, end, count, flags));
+
+}
+
+static int
+gt_setup_intr(device_t dev, device_t child,
+ struct resource *ires, int flags, driver_filter_t *filt,
+ driver_intr_t *intr, void *arg, void **cookiep)
+{
+ return BUS_SETUP_INTR(device_get_parent(dev), child, ires, flags,
+ filt, intr, arg, cookiep);
+}
+
+static int
+gt_teardown_intr(device_t dev, device_t child, struct resource *res,
+ void *cookie)
+{
+ return (BUS_TEARDOWN_INTR(device_get_parent(dev), child, res, cookie));
+}
+
+static int
+gt_activate_resource(device_t dev, device_t child, int type, int rid,
+ struct resource *r)
+{
+ return (BUS_ACTIVATE_RESOURCE(device_get_parent(dev), child,
+ type, rid, r));
+}
+
+static device_method_t gt_methods[] = {
+ DEVMETHOD(device_probe, gt_probe),
+ DEVMETHOD(device_identify, gt_identify),
+ DEVMETHOD(device_attach, gt_attach),
+
+ DEVMETHOD(bus_setup_intr, gt_setup_intr),
+ DEVMETHOD(bus_teardown_intr, gt_teardown_intr),
+ DEVMETHOD(bus_alloc_resource, gt_alloc_resource),
+ DEVMETHOD(bus_activate_resource, gt_activate_resource),
+
+ DEVMETHOD_END
+};
+
+static driver_t gt_driver = {
+ "gt",
+ gt_methods,
+ sizeof(struct gt_softc),
+};
+static devclass_t gt_devclass;
+
+DRIVER_MODULE(gt, nexus, gt_driver, gt_devclass, 0, 0);
Property changes on: trunk/sys/mips/malta/gt.c
___________________________________________________________________
Added: svn:eol-style
## -0,0 +1 ##
+native
\ No newline at end of property
Added: svn:keywords
## -0,0 +1 ##
+MidnightBSD=%H
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+text/plain
\ No newline at end of property
Added: trunk/sys/mips/malta/gt_pci.c
===================================================================
--- trunk/sys/mips/malta/gt_pci.c (rev 0)
+++ trunk/sys/mips/malta/gt_pci.c 2018-05-26 21:55:02 UTC (rev 9987)
@@ -0,0 +1,775 @@
+/* $MidnightBSD$ */
+/* $NetBSD: gt_pci.c,v 1.4 2003/07/15 00:24:54 lukem Exp $ */
+
+/*-
+ * Copyright (c) 2001, 2002 Wasabi Systems, Inc.
+ * All rights reserved.
+ *
+ * Written by Jason R. Thorpe for Wasabi Systems, Inc.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * 3. All advertising materials mentioning features or use of this software
+ * must display the following acknowledgement:
+ * This product includes software developed for the NetBSD Project by
+ * Wasabi Systems, Inc.
+ * 4. The name of Wasabi Systems, Inc. may not be used to endorse
+ * or promote products derived from this software without specific prior
+ * written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/*
+ * PCI configuration support for gt I/O Processor chip.
+ */
+
+#include <sys/cdefs.h>
+__FBSDID("$FreeBSD: stable/10/sys/mips/malta/gt_pci.c 261455 2014-02-04 03:36:42Z eadler $");
+
+#include <sys/param.h>
+#include <sys/systm.h>
+
+#include <sys/bus.h>
+#include <sys/endian.h>
+#include <sys/interrupt.h>
+#include <sys/malloc.h>
+#include <sys/kernel.h>
+#include <sys/module.h>
+#include <sys/rman.h>
+
+#include <vm/vm.h>
+#include <vm/pmap.h>
+#include <vm/vm_extern.h>
+
+#include <machine/bus.h>
+#include <machine/cpu.h>
+#include <machine/pmap.h>
+
+#include <mips/malta/maltareg.h>
+
+#include <mips/malta/gtreg.h>
+#include <mips/malta/gtvar.h>
+
+#include <isa/isareg.h>
+#include <dev/ic/i8259.h>
+
+#include <dev/pci/pcireg.h>
+#include <dev/pci/pcivar.h>
+
+#include <dev/pci/pcib_private.h>
+#include "pcib_if.h"
+
+#include <mips/malta/gt_pci_bus_space.h>
+
+#define ICU_LEN 16 /* number of ISA IRQs */
+
+/*
+ * XXX: These defines are from NetBSD's <dev/ic/i8259reg.h>. Respective file
+ * from FreeBSD src tree <dev/ic/i8259.h> lacks some definitions.
+ */
+#define PIC_OCW1 1
+#define PIC_OCW2 0
+#define PIC_OCW3 0
+
+#define OCW2_SELECT 0
+#define OCW2_ILS(x) ((x) << 0) /* interrupt level select */
+
+#define OCW3_POLL_IRQ(x) ((x) & 0x7f)
+#define OCW3_POLL_PENDING (1U << 7)
+
+/*
+ * Galileo controller's registers are LE so convert to then
+ * to/from native byte order. We rely on boot loader or emulator
+ * to set "swap bytes" configuration correctly for us
+ */
+#define GT_PCI_DATA(v) htole32((v))
+#define GT_HOST_DATA(v) le32toh((v))
+
+struct gt_pci_softc;
+
+struct gt_pci_intr_cookie {
+ int irq;
+ struct gt_pci_softc *sc;
+};
+
+struct gt_pci_softc {
+ device_t sc_dev;
+ bus_space_tag_t sc_st;
+ bus_space_handle_t sc_ioh_icu1;
+ bus_space_handle_t sc_ioh_icu2;
+ bus_space_handle_t sc_ioh_elcr;
+
+ int sc_busno;
+ struct rman sc_mem_rman;
+ struct rman sc_io_rman;
+ struct rman sc_irq_rman;
+ unsigned long sc_mem;
+ bus_space_handle_t sc_io;
+
+ struct resource *sc_irq;
+ struct intr_event *sc_eventstab[ICU_LEN];
+ struct gt_pci_intr_cookie sc_intr_cookies[ICU_LEN];
+ uint16_t sc_imask;
+ uint16_t sc_elcr;
+
+ uint16_t sc_reserved;
+
+ void *sc_ih;
+};
+
+static void gt_pci_set_icus(struct gt_pci_softc *);
+static int gt_pci_intr(void *v);
+static int gt_pci_probe(device_t);
+static int gt_pci_attach(device_t);
+static int gt_pci_activate_resource(device_t, device_t, int, int,
+ struct resource *);
+static int gt_pci_setup_intr(device_t, device_t, struct resource *,
+ int, driver_filter_t *, driver_intr_t *, void *, void **);
+static int gt_pci_teardown_intr(device_t, device_t, struct resource *, void*);
+static int gt_pci_maxslots(device_t );
+static int gt_pci_conf_setup(struct gt_pci_softc *, int, int, int, int,
+ uint32_t *);
+static uint32_t gt_pci_read_config(device_t, u_int, u_int, u_int, u_int, int);
+static void gt_pci_write_config(device_t, u_int, u_int, u_int, u_int,
+ uint32_t, int);
+static int gt_pci_route_interrupt(device_t pcib, device_t dev, int pin);
+static struct resource * gt_pci_alloc_resource(device_t, device_t, int,
+ int *, u_long, u_long, u_long, u_int);
+
+static void
+gt_pci_mask_irq(void *source)
+{
+ struct gt_pci_intr_cookie *cookie = source;
+ struct gt_pci_softc *sc = cookie->sc;
+ int irq = cookie->irq;
+
+ sc->sc_imask |= (1 << irq);
+ sc->sc_elcr |= (1 << irq);
+
+ gt_pci_set_icus(sc);
+}
+
+static void
+gt_pci_unmask_irq(void *source)
+{
+ struct gt_pci_intr_cookie *cookie = source;
+ struct gt_pci_softc *sc = cookie->sc;
+ int irq = cookie->irq;
+
+ /* Enable it, set trigger mode. */
+ sc->sc_imask &= ~(1 << irq);
+ sc->sc_elcr &= ~(1 << irq);
+
+ gt_pci_set_icus(sc);
+}
+
+static void
+gt_pci_set_icus(struct gt_pci_softc *sc)
+{
+ /* Enable the cascade IRQ (2) if 8-15 is enabled. */
+ if ((sc->sc_imask & 0xff00) != 0xff00)
+ sc->sc_imask &= ~(1U << 2);
+ else
+ sc->sc_imask |= (1U << 2);
+
+ bus_space_write_1(sc->sc_st, sc->sc_ioh_icu1, PIC_OCW1,
+ sc->sc_imask & 0xff);
+ bus_space_write_1(sc->sc_st, sc->sc_ioh_icu2, PIC_OCW1,
+ (sc->sc_imask >> 8) & 0xff);
+
+ bus_space_write_1(sc->sc_st, sc->sc_ioh_elcr, 0,
+ sc->sc_elcr & 0xff);
+ bus_space_write_1(sc->sc_st, sc->sc_ioh_elcr, 1,
+ (sc->sc_elcr >> 8) & 0xff);
+}
+
+static int
+gt_pci_intr(void *v)
+{
+ struct gt_pci_softc *sc = v;
+ struct intr_event *event;
+ int irq;
+
+ for (;;) {
+ bus_space_write_1(sc->sc_st, sc->sc_ioh_icu1, PIC_OCW3,
+ OCW3_SEL | OCW3_P);
+ irq = bus_space_read_1(sc->sc_st, sc->sc_ioh_icu1, PIC_OCW3);
+ if ((irq & OCW3_POLL_PENDING) == 0)
+ {
+ return FILTER_HANDLED;
+ }
+
+ irq = OCW3_POLL_IRQ(irq);
+
+ if (irq == 2) {
+ bus_space_write_1(sc->sc_st, sc->sc_ioh_icu2,
+ PIC_OCW3, OCW3_SEL | OCW3_P);
+ irq = bus_space_read_1(sc->sc_st, sc->sc_ioh_icu2,
+ PIC_OCW3);
+ if (irq & OCW3_POLL_PENDING)
+ irq = OCW3_POLL_IRQ(irq) + 8;
+ else
+ irq = 2;
+ }
+
+ event = sc->sc_eventstab[irq];
+
+ if (!event || TAILQ_EMPTY(&event->ie_handlers))
+ continue;
+
+ /* TODO: frame instead of NULL? */
+ intr_event_handle(event, NULL);
+ /* XXX: Log stray IRQs */
+
+ /* Send a specific EOI to the 8259. */
+ if (irq > 7) {
+ bus_space_write_1(sc->sc_st, sc->sc_ioh_icu2,
+ PIC_OCW2, OCW2_SELECT | OCW2_EOI | OCW2_SL |
+ OCW2_ILS(irq & 7));
+ irq = 2;
+ }
+
+ bus_space_write_1(sc->sc_st, sc->sc_ioh_icu1, PIC_OCW2,
+ OCW2_SELECT | OCW2_EOI | OCW2_SL | OCW2_ILS(irq));
+ }
+
+ return FILTER_HANDLED;
+}
+
+static int
+gt_pci_probe(device_t dev)
+{
+ device_set_desc(dev, "GT64120 PCI bridge");
+ return (0);
+}
+
+static int
+gt_pci_attach(device_t dev)
+{
+
+ uint32_t busno;
+ struct gt_pci_softc *sc = device_get_softc(dev);
+ int rid;
+
+ busno = 0;
+ sc->sc_dev = dev;
+ sc->sc_busno = busno;
+ sc->sc_st = mips_bus_space_generic;
+
+ /* Use KSEG1 to access IO ports for it is uncached */
+ sc->sc_io = MIPS_PHYS_TO_KSEG1(MALTA_PCI0_IO_BASE);
+ sc->sc_io_rman.rm_type = RMAN_ARRAY;
+ sc->sc_io_rman.rm_descr = "GT64120 PCI I/O Ports";
+ /*
+ * First 256 bytes are ISA's registers: e.g. i8259's
+ * So do not use them for general purpose PCI I/O window
+ */
+ if (rman_init(&sc->sc_io_rman) != 0 ||
+ rman_manage_region(&sc->sc_io_rman, 0x100, 0xffff) != 0) {
+ panic("gt_pci_attach: failed to set up I/O rman");
+ }
+
+ /* Use KSEG1 to access PCI memory for it is uncached */
+ sc->sc_mem = MIPS_PHYS_TO_KSEG1(MALTA_PCIMEM1_BASE);
+ sc->sc_mem_rman.rm_type = RMAN_ARRAY;
+ sc->sc_mem_rman.rm_descr = "GT64120 PCI Memory";
+ if (rman_init(&sc->sc_mem_rman) != 0 ||
+ rman_manage_region(&sc->sc_mem_rman,
+ sc->sc_mem, sc->sc_mem + MALTA_PCIMEM1_SIZE) != 0) {
+ panic("gt_pci_attach: failed to set up memory rman");
+ }
+ sc->sc_irq_rman.rm_type = RMAN_ARRAY;
+ sc->sc_irq_rman.rm_descr = "GT64120 PCI IRQs";
+ if (rman_init(&sc->sc_irq_rman) != 0 ||
+ rman_manage_region(&sc->sc_irq_rman, 1, 31) != 0)
+ panic("gt_pci_attach: failed to set up IRQ rman");
+
+ /*
+ * Map the PIC/ELCR registers.
+ */
+#if 0
+ if (bus_space_map(sc->sc_st, 0x4d0, 2, 0, &sc->sc_ioh_elcr) != 0)
+ device_printf(dev, "unable to map ELCR registers\n");
+ if (bus_space_map(sc->sc_st, IO_ICU1, 2, 0, &sc->sc_ioh_icu1) != 0)
+ device_printf(dev, "unable to map ICU1 registers\n");
+ if (bus_space_map(sc->sc_st, IO_ICU2, 2, 0, &sc->sc_ioh_icu2) != 0)
+ device_printf(dev, "unable to map ICU2 registers\n");
+#else
+ sc->sc_ioh_elcr = sc->sc_io + 0x4d0;
+ sc->sc_ioh_icu1 = sc->sc_io + IO_ICU1;
+ sc->sc_ioh_icu2 = sc->sc_io + IO_ICU2;
+#endif
+
+
+ /* All interrupts default to "masked off". */
+ sc->sc_imask = 0xffff;
+
+ /* All interrupts default to edge-triggered. */
+ sc->sc_elcr = 0;
+
+ /*
+ * Initialize the 8259s.
+ */
+ /* reset, program device, 4 bytes */
+ bus_space_write_1(sc->sc_st, sc->sc_ioh_icu1, 0,
+ ICW1_RESET | ICW1_IC4);
+ /*
+ * XXX: values from NetBSD's <dev/ic/i8259reg.h>
+ */
+ bus_space_write_1(sc->sc_st, sc->sc_ioh_icu1, 1,
+ 0/*XXX*/);
+ bus_space_write_1(sc->sc_st, sc->sc_ioh_icu1, 1,
+ 1 << 2);
+ bus_space_write_1(sc->sc_st, sc->sc_ioh_icu1, 1,
+ ICW4_8086);
+
+ /* mask all interrupts */
+ bus_space_write_1(sc->sc_st, sc->sc_ioh_icu1, 1,
+ sc->sc_imask & 0xff);
+
+ /* enable special mask mode */
+ bus_space_write_1(sc->sc_st, sc->sc_ioh_icu1, 0,
+ OCW3_SEL | OCW3_ESMM | OCW3_SMM);
+
+ /* read IRR by default */
+ bus_space_write_1(sc->sc_st, sc->sc_ioh_icu1, 0,
+ OCW3_SEL | OCW3_RR);
+
+ /* reset, program device, 4 bytes */
+ bus_space_write_1(sc->sc_st, sc->sc_ioh_icu2, 0,
+ ICW1_RESET | ICW1_IC4);
+ bus_space_write_1(sc->sc_st, sc->sc_ioh_icu2, 1,
+ 0/*XXX*/);
+ bus_space_write_1(sc->sc_st, sc->sc_ioh_icu2, 1,
+ 1 << 2);
+ bus_space_write_1(sc->sc_st, sc->sc_ioh_icu2, 1,
+ ICW4_8086);
+
+ /* mask all interrupts */
+ bus_space_write_1(sc->sc_st, sc->sc_ioh_icu2, 1,
+ sc->sc_imask & 0xff);
+
+ /* enable special mask mode */
+ bus_space_write_1(sc->sc_st, sc->sc_ioh_icu2, 0,
+ OCW3_SEL | OCW3_ESMM | OCW3_SMM);
+
+ /* read IRR by default */
+ bus_space_write_1(sc->sc_st, sc->sc_ioh_icu2, 0,
+ OCW3_SEL | OCW3_RR);
+
+ /*
+ * Default all interrupts to edge-triggered.
+ */
+ bus_space_write_1(sc->sc_st, sc->sc_ioh_elcr, 0,
+ sc->sc_elcr & 0xff);
+ bus_space_write_1(sc->sc_st, sc->sc_ioh_elcr, 1,
+ (sc->sc_elcr >> 8) & 0xff);
+
+ /*
+ * Some ISA interrupts are reserved for devices that
+ * we know are hard-wired to certain IRQs.
+ */
+ sc->sc_reserved =
+ (1U << 0) | /* timer */
+ (1U << 1) | /* keyboard controller (keyboard) */
+ (1U << 2) | /* PIC cascade */
+ (1U << 3) | /* COM 2 */
+ (1U << 4) | /* COM 1 */
+ (1U << 6) | /* floppy */
+ (1U << 7) | /* centronics */
+ (1U << 8) | /* RTC */
+ (1U << 9) | /* I2C */
+ (1U << 12) | /* keyboard controller (mouse) */
+ (1U << 14) | /* IDE primary */
+ (1U << 15); /* IDE secondary */
+
+ /* Hook up our interrupt handler. */
+ if ((sc->sc_irq = bus_alloc_resource(dev, SYS_RES_IRQ, &rid,
+ MALTA_SOUTHBRIDGE_INTR, MALTA_SOUTHBRIDGE_INTR, 1,
+ RF_SHAREABLE | RF_ACTIVE)) == NULL) {
+ device_printf(dev, "unable to allocate IRQ resource\n");
+ return ENXIO;
+ }
+
+ if ((bus_setup_intr(dev, sc->sc_irq, INTR_TYPE_MISC,
+ gt_pci_intr, NULL, sc, &sc->sc_ih))) {
+ device_printf(dev,
+ "WARNING: unable to register interrupt handler\n");
+ return ENXIO;
+ }
+
+ /* Initialize memory and i/o rmans. */
+ device_add_child(dev, "pci", busno);
+ return (bus_generic_attach(dev));
+}
+
+static int
+gt_pci_maxslots(device_t dev)
+{
+ return (PCI_SLOTMAX);
+}
+
+static int
+gt_pci_conf_setup(struct gt_pci_softc *sc, int bus, int slot, int func,
+ int reg, uint32_t *addr)
+{
+ *addr = (bus << 16) | (slot << 11) | (func << 8) | reg;
+
+ return (0);
+}
+
+static uint32_t
+gt_pci_read_config(device_t dev, u_int bus, u_int slot, u_int func, u_int reg,
+ int bytes)
+{
+ struct gt_pci_softc *sc = device_get_softc(dev);
+ uint32_t data;
+ uint32_t addr;
+ uint32_t shift, mask;
+
+ if (gt_pci_conf_setup(sc, bus, slot, func, reg & ~3, &addr))
+ return (uint32_t)(-1);
+
+ /* Clear cause register bits. */
+ GT_REGVAL(GT_INTR_CAUSE) = GT_PCI_DATA(0);
+ GT_REGVAL(GT_PCI0_CFG_ADDR) = GT_PCI_DATA((1U << 31) | addr);
+ /*
+ * Galileo system controller is special
+ */
+ if ((bus == 0) && (slot == 0))
+ data = GT_PCI_DATA(GT_REGVAL(GT_PCI0_CFG_DATA));
+ else
+ data = GT_REGVAL(GT_PCI0_CFG_DATA);
+
+ /* Check for master abort. */
+ if (GT_HOST_DATA(GT_REGVAL(GT_INTR_CAUSE)) & (GTIC_MASABORT0 | GTIC_TARABORT0))
+ data = (uint32_t) -1;
+
+ switch(reg % 4)
+ {
+ case 3:
+ shift = 24;
+ break;
+ case 2:
+ shift = 16;
+ break;
+ case 1:
+ shift = 8;
+ break;
+ default:
+ shift = 0;
+ break;
+ }
+
+ switch(bytes)
+ {
+ case 1:
+ mask = 0xff;
+ data = (data >> shift) & mask;
+ break;
+ case 2:
+ mask = 0xffff;
+ if(reg % 4 == 0)
+ data = data & mask;
+ else
+ data = (data >> 16) & mask;
+ break;
+ case 4:
+ break;
+ default:
+ panic("gt_pci_readconfig: wrong bytes count");
+ break;
+ }
+#if 0
+ printf("PCICONF_READ(%02x:%02x.%02x[%04x] -> %02x(%d)\n",
+ bus, slot, func, reg, data, bytes);
+#endif
+
+ return (data);
+}
+
+static void
+gt_pci_write_config(device_t dev, u_int bus, u_int slot, u_int func, u_int reg,
+ uint32_t data, int bytes)
+{
+ struct gt_pci_softc *sc = device_get_softc(dev);
+ uint32_t addr;
+ uint32_t reg_data;
+ uint32_t shift, mask;
+
+ if(bytes != 4)
+ {
+ reg_data = gt_pci_read_config(dev, bus, slot, func, reg, 4);
+
+ shift = 8 * (reg & 3);
+
+ switch(bytes)
+ {
+ case 1:
+ mask = 0xff;
+ data = (reg_data & ~ (mask << shift)) | (data << shift);
+ break;
+ case 2:
+ mask = 0xffff;
+ if(reg % 4 == 0)
+ data = (reg_data & ~mask) | data;
+ else
+ data = (reg_data & ~ (mask << shift)) |
+ (data << shift);
+ break;
+ case 4:
+ break;
+ default:
+ panic("gt_pci_readconfig: wrong bytes count");
+ break;
+ }
+ }
+
+ if (gt_pci_conf_setup(sc, bus, slot, func, reg & ~3, &addr))
+ return;
+
+ /* The galileo has problems accessing device 31. */
+ if (bus == 0 && slot == 31)
+ return;
+
+ /* XXX: no support for bus > 0 yet */
+ if (bus > 0)
+ return;
+
+ /* Clear cause register bits. */
+ GT_REGVAL(GT_INTR_CAUSE) = GT_PCI_DATA(0);
+
+ GT_REGVAL(GT_PCI0_CFG_ADDR) = GT_PCI_DATA((1U << 31) | addr);
+
+ /*
+ * Galileo system controller is special
+ */
+ if ((bus == 0) && (slot == 0))
+ GT_REGVAL(GT_PCI0_CFG_DATA) = GT_PCI_DATA(data);
+ else
+ GT_REGVAL(GT_PCI0_CFG_DATA) = data;
+
+#if 0
+ printf("PCICONF_WRITE(%02x:%02x.%02x[%04x] -> %02x(%d)\n",
+ bus, slot, func, reg, data, bytes);
+#endif
+
+}
+
+static int
+gt_pci_route_interrupt(device_t pcib, device_t dev, int pin)
+{
+ int bus;
+ int device;
+ int func;
+ /* struct gt_pci_softc *sc = device_get_softc(pcib); */
+ bus = pci_get_bus(dev);
+ device = pci_get_slot(dev);
+ func = pci_get_function(dev);
+ /*
+ * XXXMIPS: We need routing logic. This is just a stub .
+ */
+ switch (device) {
+ case 9: /*
+ * PIIX4 IDE adapter. HW IRQ0
+ */
+ return 0;
+ case 11: /* Ethernet */
+ return 10;
+ default:
+ device_printf(pcib, "no IRQ mapping for %d/%d/%d/%d\n", bus, device, func, pin);
+
+ }
+ return (0);
+
+}
+
+static int
+gt_read_ivar(device_t dev, device_t child, int which, uintptr_t *result)
+{
+ struct gt_pci_softc *sc = device_get_softc(dev);
+ switch (which) {
+ case PCIB_IVAR_DOMAIN:
+ *result = 0;
+ return (0);
+ case PCIB_IVAR_BUS:
+ *result = sc->sc_busno;
+ return (0);
+
+ }
+ return (ENOENT);
+}
+
+static int
+gt_write_ivar(device_t dev, device_t child, int which, uintptr_t result)
+{
+ struct gt_pci_softc * sc = device_get_softc(dev);
+
+ switch (which) {
+ case PCIB_IVAR_BUS:
+ sc->sc_busno = result;
+ return (0);
+ }
+ return (ENOENT);
+}
+
+static struct resource *
+gt_pci_alloc_resource(device_t bus, device_t child, int type, int *rid,
+ u_long start, u_long end, u_long count, u_int flags)
+{
+ struct gt_pci_softc *sc = device_get_softc(bus);
+ struct resource *rv = NULL;
+ struct rman *rm;
+ bus_space_handle_t bh = 0;
+
+ switch (type) {
+ case SYS_RES_IRQ:
+ rm = &sc->sc_irq_rman;
+ break;
+ case SYS_RES_MEMORY:
+ rm = &sc->sc_mem_rman;
+ bh = sc->sc_mem;
+ break;
+ case SYS_RES_IOPORT:
+ rm = &sc->sc_io_rman;
+ bh = sc->sc_io;
+ break;
+ default:
+ return (NULL);
+ }
+
+ rv = rman_reserve_resource(rm, start, end, count, flags, child);
+ if (rv == NULL)
+ return (NULL);
+ rman_set_rid(rv, *rid);
+ if (type != SYS_RES_IRQ) {
+ bh += (rman_get_start(rv));
+
+ rman_set_bustag(rv, gt_pci_bus_space);
+ rman_set_bushandle(rv, bh);
+ if (flags & RF_ACTIVE) {
+ if (bus_activate_resource(child, type, *rid, rv)) {
+ rman_release_resource(rv);
+ return (NULL);
+ }
+ }
+ }
+ return (rv);
+}
+
+static int
+gt_pci_activate_resource(device_t bus, device_t child, int type, int rid,
+ struct resource *r)
+{
+ bus_space_handle_t p;
+ int error;
+
+ if ((type == SYS_RES_MEMORY) || (type == SYS_RES_IOPORT)) {
+ error = bus_space_map(rman_get_bustag(r),
+ rman_get_bushandle(r), rman_get_size(r), 0, &p);
+ if (error)
+ return (error);
+ rman_set_bushandle(r, p);
+ }
+ return (rman_activate_resource(r));
+}
+
+static int
+gt_pci_setup_intr(device_t dev, device_t child, struct resource *ires,
+ int flags, driver_filter_t *filt, driver_intr_t *handler,
+ void *arg, void **cookiep)
+{
+ struct gt_pci_softc *sc = device_get_softc(dev);
+ struct intr_event *event;
+ int irq, error;
+
+ irq = rman_get_start(ires);
+ if (irq >= ICU_LEN || irq == 2)
+ panic("%s: bad irq or type", __func__);
+
+ event = sc->sc_eventstab[irq];
+ sc->sc_intr_cookies[irq].irq = irq;
+ sc->sc_intr_cookies[irq].sc = sc;
+ if (event == NULL) {
+ error = intr_event_create(&event,
+ (void *)&sc->sc_intr_cookies[irq], 0, irq,
+ gt_pci_mask_irq, gt_pci_unmask_irq,
+ NULL, NULL, "gt_pci intr%d:", irq);
+ if (error)
+ return 0;
+ sc->sc_eventstab[irq] = event;
+ }
+
+ intr_event_add_handler(event, device_get_nameunit(child), filt,
+ handler, arg, intr_priority(flags), flags, cookiep);
+
+ gt_pci_unmask_irq((void *)&sc->sc_intr_cookies[irq]);
+ return 0;
+}
+
+static int
+gt_pci_teardown_intr(device_t dev, device_t child, struct resource *res,
+ void *cookie)
+{
+ struct gt_pci_softc *sc = device_get_softc(dev);
+ int irq;
+
+ irq = rman_get_start(res);
+ gt_pci_mask_irq((void *)&sc->sc_intr_cookies[irq]);
+
+ return (intr_event_remove_handler(cookie));
+}
+
+static device_method_t gt_pci_methods[] = {
+ /* Device interface */
+ DEVMETHOD(device_probe, gt_pci_probe),
+ DEVMETHOD(device_attach, gt_pci_attach),
+ DEVMETHOD(device_shutdown, bus_generic_shutdown),
+ DEVMETHOD(device_suspend, bus_generic_suspend),
+ DEVMETHOD(device_resume, bus_generic_resume),
+
+ /* Bus interface */
+ DEVMETHOD(bus_read_ivar, gt_read_ivar),
+ DEVMETHOD(bus_write_ivar, gt_write_ivar),
+ DEVMETHOD(bus_alloc_resource, gt_pci_alloc_resource),
+ DEVMETHOD(bus_release_resource, bus_generic_release_resource),
+ DEVMETHOD(bus_activate_resource, gt_pci_activate_resource),
+ DEVMETHOD(bus_deactivate_resource, bus_generic_deactivate_resource),
+ DEVMETHOD(bus_setup_intr, gt_pci_setup_intr),
+ DEVMETHOD(bus_teardown_intr, gt_pci_teardown_intr),
+
+ /* pcib interface */
+ DEVMETHOD(pcib_maxslots, gt_pci_maxslots),
+ DEVMETHOD(pcib_read_config, gt_pci_read_config),
+ DEVMETHOD(pcib_write_config, gt_pci_write_config),
+ DEVMETHOD(pcib_route_interrupt, gt_pci_route_interrupt),
+
+ DEVMETHOD_END
+};
+
+static driver_t gt_pci_driver = {
+ "pcib",
+ gt_pci_methods,
+ sizeof(struct gt_pci_softc),
+};
+
+static devclass_t gt_pci_devclass;
+
+DRIVER_MODULE(gt_pci, gt, gt_pci_driver, gt_pci_devclass, 0, 0);
Property changes on: trunk/sys/mips/malta/gt_pci.c
___________________________________________________________________
Added: svn:eol-style
## -0,0 +1 ##
+native
\ No newline at end of property
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## -0,0 +1 ##
+MidnightBSD=%H
\ No newline at end of property
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## -0,0 +1 ##
+text/plain
\ No newline at end of property
Added: trunk/sys/mips/malta/gt_pci_bus_space.c
===================================================================
--- trunk/sys/mips/malta/gt_pci_bus_space.c (rev 0)
+++ trunk/sys/mips/malta/gt_pci_bus_space.c 2018-05-26 21:55:02 UTC (rev 9987)
@@ -0,0 +1,410 @@
+/* $MidnightBSD$ */
+/* $NetBSD: bus.h,v 1.12 1997/10/01 08:25:15 fvdl Exp $ */
+/*-
+ * $Id: bus.h,v 1.6 2007/08/09 11:23:32 katta Exp $
+ *
+ * Copyright (c) 1996, 1997 The NetBSD Foundation, Inc.
+ * All rights reserved.
+ *
+ * This code is derived from software contributed to The NetBSD Foundation
+ * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility,
+ * NASA Ames Research Center.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * 3. All advertising materials mentioning features or use of this software
+ * must display the following acknowledgement:
+ * This product includes software developed by the NetBSD
+ * Foundation, Inc. and its contributors.
+ * 4. Neither the name of The NetBSD Foundation nor the names of its
+ * contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
+ * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/*
+ * Copyright (c) 1996 Charles M. Hannum. All rights reserved.
+ * Copyright (c) 1996 Christopher G. Demetriou. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * 3. All advertising materials mentioning features or use of this software
+ * must display the following acknowledgement:
+ * This product includes software developed by Christopher G. Demetriou
+ * for the NetBSD Project.
+ * 4. The name of the author may not be used to endorse or promote products
+ * derived from this software without specific prior written permission
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+ * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+ * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * from: src/sys/alpha/include/bus.h,v 1.5 1999/08/28 00:38:40 peter
+ * $FreeBSD: stable/10/sys/mips/malta/gt_pci_bus_space.c 255083 2013-08-30 20:28:35Z gonzo $
+ */
+#include <sys/cdefs.h>
+__FBSDID("$FreeBSD: stable/10/sys/mips/malta/gt_pci_bus_space.c 255083 2013-08-30 20:28:35Z gonzo $");
+
+#include <sys/param.h>
+#include <sys/systm.h>
+#include <sys/bus.h>
+#include <sys/endian.h>
+#include <sys/kernel.h>
+#include <sys/malloc.h>
+#include <sys/ktr.h>
+
+#include <vm/vm.h>
+#include <vm/pmap.h>
+#include <vm/vm_kern.h>
+#include <vm/vm_extern.h>
+
+#include <machine/bus.h>
+#include <machine/cache.h>
+#include <mips/malta/gt_pci_bus_space.h>
+
+static bs_r_2_proto(gt_pci);
+static bs_r_4_proto(gt_pci);
+static bs_w_2_proto(gt_pci);
+static bs_w_4_proto(gt_pci);
+static bs_rm_2_proto(gt_pci);
+static bs_rm_4_proto(gt_pci);
+static bs_wm_2_proto(gt_pci);
+static bs_wm_4_proto(gt_pci);
+static bs_rr_2_proto(gt_pci);
+static bs_rr_4_proto(gt_pci);
+static bs_wr_2_proto(gt_pci);
+static bs_wr_4_proto(gt_pci);
+static bs_sm_2_proto(gt_pci);
+static bs_sm_4_proto(gt_pci);
+static bs_sr_2_proto(gt_pci);
+static bs_sr_4_proto(gt_pci);
+
+static struct bus_space gt_pci_space = {
+ /* cookie */
+ .bs_cookie = (void *) 0,
+
+ /* mapping/unmapping */
+ .bs_map = generic_bs_map,
+ .bs_unmap = generic_bs_unmap,
+ .bs_subregion = generic_bs_subregion,
+
+ /* allocation/deallocation */
+ .bs_alloc = generic_bs_alloc,
+ .bs_free = generic_bs_free,
+
+ /* barrier */
+ .bs_barrier = generic_bs_barrier,
+
+ /* read (single) */
+ .bs_r_1 = generic_bs_r_1,
+ .bs_r_2 = gt_pci_bs_r_2,
+ .bs_r_4 = gt_pci_bs_r_4,
+ .bs_r_8 = NULL,
+
+ /* read multiple */
+ .bs_rm_1 = generic_bs_rm_1,
+ .bs_rm_2 = gt_pci_bs_rm_2,
+ .bs_rm_4 = gt_pci_bs_rm_4,
+ .bs_rm_8 = NULL,
+
+ /* read region */
+ .bs_rr_1 = generic_bs_rr_1,
+ .bs_rr_2 = gt_pci_bs_rr_2,
+ .bs_rr_4 = gt_pci_bs_rr_4,
+ .bs_rr_8 = NULL,
+
+ /* write (single) */
+ .bs_w_1 = generic_bs_w_1,
+ .bs_w_2 = gt_pci_bs_w_2,
+ .bs_w_4 = gt_pci_bs_w_4,
+ .bs_w_8 = NULL,
+
+ /* write multiple */
+ .bs_wm_1 = generic_bs_wm_1,
+ .bs_wm_2 = gt_pci_bs_wm_2,
+ .bs_wm_4 = gt_pci_bs_wm_4,
+ .bs_wm_8 = NULL,
+
+ /* write region */
+ .bs_wr_1 = generic_bs_wr_1,
+ .bs_wr_2 = gt_pci_bs_wr_2,
+ .bs_wr_4 = gt_pci_bs_wr_4,
+ .bs_wr_8 = NULL,
+
+ /* set multiple */
+ .bs_sm_1 = generic_bs_sm_1,
+ .bs_sm_2 = gt_pci_bs_sm_2,
+ .bs_sm_4 = gt_pci_bs_sm_4,
+ .bs_sm_8 = NULL,
+
+ /* set region */
+ .bs_sr_1 = generic_bs_sr_1,
+ .bs_sr_2 = gt_pci_bs_sr_2,
+ .bs_sr_4 = gt_pci_bs_sr_4,
+ .bs_sr_8 = NULL,
+
+ /* copy */
+ .bs_c_1 = generic_bs_c_1,
+ .bs_c_2 = generic_bs_c_2,
+ .bs_c_4 = generic_bs_c_4,
+ .bs_c_8 = NULL,
+
+ /* read (single) stream */
+ .bs_r_1_s = generic_bs_r_1,
+ .bs_r_2_s = generic_bs_r_2,
+ .bs_r_4_s = generic_bs_r_4,
+ .bs_r_8_s = NULL,
+
+ /* read multiple stream */
+ .bs_rm_1_s = generic_bs_rm_1,
+ .bs_rm_2_s = generic_bs_rm_2,
+ .bs_rm_4_s = generic_bs_rm_4,
+ .bs_rm_8_s = NULL,
+
+ /* read region stream */
+ .bs_rr_1_s = generic_bs_rr_1,
+ .bs_rr_2_s = generic_bs_rr_2,
+ .bs_rr_4_s = generic_bs_rr_4,
+ .bs_rr_8_s = NULL,
+
+ /* write (single) stream */
+ .bs_w_1_s = generic_bs_w_1,
+ .bs_w_2_s = generic_bs_w_2,
+ .bs_w_4_s = generic_bs_w_4,
+ .bs_w_8_s = NULL,
+
+ /* write multiple stream */
+ .bs_wm_1_s = generic_bs_wm_1,
+ .bs_wm_2_s = generic_bs_wm_2,
+ .bs_wm_4_s = generic_bs_wm_4,
+ .bs_wm_8_s = NULL,
+
+ /* write region stream */
+ .bs_wr_1_s = generic_bs_wr_1,
+ .bs_wr_2_s = generic_bs_wr_2,
+ .bs_wr_4_s = generic_bs_wr_4,
+ .bs_wr_8_s = NULL,
+};
+
+#define rd16(a) le16toh(readw(a))
+#define rd32(a) le32toh(readl(a))
+#define wr16(a, v) writew(a, htole16(v))
+#define wr32(a, v) writel(a, htole32(v))
+
+/* generic bus_space tag */
+bus_space_tag_t gt_pci_bus_space = >_pci_space;
+
+uint16_t
+gt_pci_bs_r_2(void *t, bus_space_handle_t handle,
+ bus_size_t offset)
+{
+
+ return (rd16(handle + offset));
+}
+
+uint32_t
+gt_pci_bs_r_4(void *t, bus_space_handle_t handle,
+ bus_size_t offset)
+{
+
+ return (rd32(handle + offset));
+}
+
+void
+gt_pci_bs_rm_2(void *t, bus_space_handle_t bsh,
+ bus_size_t offset, uint16_t *addr, size_t count)
+{
+ bus_addr_t baddr = bsh + offset;
+
+ while (count--)
+ *addr++ = rd16(baddr);
+}
+
+void
+gt_pci_bs_rm_4(void *t, bus_space_handle_t bsh,
+ bus_size_t offset, uint32_t *addr, size_t count)
+{
+ bus_addr_t baddr = bsh + offset;
+
+ while (count--)
+ *addr++ = rd32(baddr);
+}
+
+/*
+ * Read `count' 2 or 4 byte quantities from bus space
+ * described by tag/handle and starting at `offset' and copy into
+ * buffer provided.
+ */
+void
+gt_pci_bs_rr_2(void *t, bus_space_handle_t bsh,
+ bus_size_t offset, uint16_t *addr, size_t count)
+{
+ bus_addr_t baddr = bsh + offset;
+
+ while (count--) {
+ *addr++ = rd16(baddr);
+ baddr += 2;
+ }
+}
+
+void
+gt_pci_bs_rr_4(void *t, bus_space_handle_t bsh,
+ bus_size_t offset, uint32_t *addr, size_t count)
+{
+ bus_addr_t baddr = bsh + offset;
+
+ while (count--) {
+ *addr++ = rd32(baddr);
+ baddr += 4;
+ }
+}
+
+/*
+ * Write the 2 or 4 byte value `value' to bus space
+ * described by tag/handle/offset.
+ */
+void
+gt_pci_bs_w_2(void *t, bus_space_handle_t bsh,
+ bus_size_t offset, uint16_t value)
+{
+
+ wr16(bsh + offset, value);
+}
+
+void
+gt_pci_bs_w_4(void *t, bus_space_handle_t bsh,
+ bus_size_t offset, uint32_t value)
+{
+
+ wr32(bsh + offset, value);
+}
+
+/*
+ * Write `count' 2 or 4 byte quantities from the buffer
+ * provided to bus space described by tag/handle/offset.
+ */
+void
+gt_pci_bs_wm_2(void *t, bus_space_handle_t bsh,
+ bus_size_t offset, const uint16_t *addr, size_t count)
+{
+ bus_addr_t baddr = bsh + offset;
+
+ while (count--)
+ wr16(baddr, *addr++);
+}
+
+void
+gt_pci_bs_wm_4(void *t, bus_space_handle_t bsh,
+ bus_size_t offset, const uint32_t *addr, size_t count)
+{
+ bus_addr_t baddr = bsh + offset;
+
+ while (count--)
+ wr32(baddr, *addr++);
+}
+
+/*
+ * Write `count' 2 or 4 byte quantities from the buffer provided
+ * to bus space described by tag/handle starting at `offset'.
+ */
+void
+gt_pci_bs_wr_2(void *t, bus_space_handle_t bsh,
+ bus_size_t offset, const uint16_t *addr, size_t count)
+{
+ bus_addr_t baddr = bsh + offset;
+
+ while (count--) {
+ wr16(baddr, *addr++);
+ baddr += 2;
+ }
+}
+
+void
+gt_pci_bs_wr_4(void *t, bus_space_handle_t bsh,
+ bus_size_t offset, const uint32_t *addr, size_t count)
+{
+ bus_addr_t baddr = bsh + offset;
+
+ while (count--) {
+ wr32(baddr, *addr++);
+ baddr += 4;
+ }
+}
+
+/*
+ * Write the 2 or 4 byte value `val' to bus space described
+ * by tag/handle/offset `count' times.
+ */
+void
+gt_pci_bs_sm_2(void *t, bus_space_handle_t bsh,
+ bus_size_t offset, uint16_t value, size_t count)
+{
+ bus_addr_t addr = bsh + offset;
+
+ while (count--)
+ wr16(addr, value);
+}
+
+void
+gt_pci_bs_sm_4(void *t, bus_space_handle_t bsh,
+ bus_size_t offset, uint32_t value, size_t count)
+{
+ bus_addr_t addr = bsh + offset;
+
+ while (count--)
+ wr32(addr, value);
+}
+
+/*
+ * Write `count' 2 or 4 byte value `val' to bus space described
+ * by tag/handle starting at `offset'.
+ */
+void
+gt_pci_bs_sr_2(void *t, bus_space_handle_t bsh,
+ bus_size_t offset, uint16_t value, size_t count)
+{
+ bus_addr_t addr = bsh + offset;
+
+ for (; count != 0; count--, addr += 2)
+ wr16(addr, value);
+}
+
+void
+gt_pci_bs_sr_4(void *t, bus_space_handle_t bsh,
+ bus_size_t offset, uint32_t value, size_t count)
+{
+ bus_addr_t addr = bsh + offset;
+
+ for (; count != 0; count--, addr += 4)
+ wr32(addr, value);
+}
Property changes on: trunk/sys/mips/malta/gt_pci_bus_space.c
___________________________________________________________________
Added: svn:eol-style
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+native
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+text/plain
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Added: trunk/sys/mips/malta/gt_pci_bus_space.h
===================================================================
--- trunk/sys/mips/malta/gt_pci_bus_space.h (rev 0)
+++ trunk/sys/mips/malta/gt_pci_bus_space.h 2018-05-26 21:55:02 UTC (rev 9987)
@@ -0,0 +1,37 @@
+/* $MidnightBSD$ */
+/*-
+ * Copyright (c) 2009, Oleksandr Tymoshenko <gonzo at FreeBSD.org>
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice unmodified, this list of conditions, and the following
+ * disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ * $FreeBSD: stable/10/sys/mips/malta/gt_pci_bus_space.h 255083 2013-08-30 20:28:35Z gonzo $
+ *
+ */
+
+#ifndef __GT_PCI_BUS_SPACEH__
+#define __GT_PCI_BUS_SPACEH__
+
+extern bus_space_tag_t gt_pci_bus_space;
+
+#endif /* __GT_PCI_BUS_SPACEH__ */
Property changes on: trunk/sys/mips/malta/gt_pci_bus_space.h
___________________________________________________________________
Added: svn:eol-style
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Added: svn:mime-type
## -0,0 +1 ##
+text/plain
\ No newline at end of property
Added: trunk/sys/mips/malta/gtreg.h
===================================================================
--- trunk/sys/mips/malta/gtreg.h (rev 0)
+++ trunk/sys/mips/malta/gtreg.h 2018-05-26 21:55:02 UTC (rev 9987)
@@ -0,0 +1,120 @@
+/* $MidnightBSD$ */
+/* $NetBSD: gtreg.h,v 1.2 2005/12/24 20:07:03 perry Exp $ */
+
+/*-
+ * Copyright (c) 1997, 1998, 2001 The NetBSD Foundation, Inc.
+ * All rights reserved.
+ *
+ * This code is derived from software contributed to The NetBSD Foundation
+ * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility,
+ * NASA Ames Research Center.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
+ * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * $FreeBSD: stable/10/sys/mips/malta/gtreg.h 204646 2010-03-03 17:55:51Z joel $
+ */
+
+
+
+#define GT_REGVAL(x) *((volatile u_int32_t *) \
+ (MIPS_PHYS_TO_KSEG1(MALTA_CORECTRL_BASE + (x))))
+
+/* CPU Configuration Register Map */
+#define GT_CPU_INT 0x000
+#define GT_MULTIGT 0x120
+
+/* CPU Address Decode Register Map */
+
+/* CPU Error Report Register Map */
+
+/* CPU Sync Barrier Register Map */
+
+/* SDRAM and Device Address Decode Register Map */
+
+/* SDRAM Configuration Register Map */
+
+/* SDRAM Parameters Register Map */
+
+/* ECC Register Map */
+
+/* Device Parameters Register Map */
+
+/* DMA Record Register Map */
+
+/* DMA Arbiter Register Map */
+
+/* Timer/Counter Register Map */
+//#define GT_TC_0 0x850
+//#define GT_TC_1 0x854
+//#define GT_TC_2 0x858
+//#define GT_TC_3 0x85c
+//#define GT_TC_CONTROL 0x864
+
+/* PCI Internal Register Map */
+#define GT_PCI0_CFG_ADDR 0xcf8
+#define GT_PCI0_CFG_DATA 0xcfc
+#define GT_PCI0_INTR_ACK 0xc34
+
+/* Interrupts Register Map */
+#define GT_INTR_CAUSE 0xc18
+#define GTIC_INTSUM 0x00000001
+#define GTIC_MEMOUT 0x00000002
+#define GTIC_DMAOUT 0x00000004
+#define GTIC_CPUOUT 0x00000008
+#define GTIC_DMA0COMP 0x00000010
+#define GTIC_DMA1COMP 0x00000020
+#define GTIC_DMA2COMP 0x00000040
+#define GTIC_DMA3COMP 0x00000080
+#define GTIC_T0EXP 0x00000100
+#define GTIC_T1EXP 0x00000200
+#define GTIC_T2EXP 0x00000400
+#define GTIC_T3EXP 0x00000800
+#define GTIC_MASRDERR0 0x00001000
+#define GTIC_SLVWRERR0 0x00002000
+#define GTIC_MASWRERR0 0x00004000
+#define GTIC_SLVRDERR0 0x00008000
+#define GTIC_ADDRERR0 0x00010000
+#define GTIC_MEMERR 0x00020000
+#define GTIC_MASABORT0 0x00040000
+#define GTIC_TARABORT0 0x00080000
+#define GTIC_RETRYCNT0 0x00100000
+#define GTIC_PMCINT_0 0x00200000
+#define GTIC_CPUINT 0x0c300000
+#define GTIC_PCINT 0xc3000000
+#define GTIC_CPUINTSUM 0x40000000
+#define GTIC_PCIINTSUM 0x80000000
+
+/* PCI Configuration Register Map */
+//#define GT_PCICONFIGBASE 0
+//#define GT_PCIDID BONITO(GT_PCICONFIGBASE + 0x00)
+//#define GT_PCICMD BONITO(GT_PCICONFIGBASE + 0x04)
+//#define GT_PCICLASS BONITO(GT_PCICONFIGBASE + 0x08)
+//#define GT_PCILTIMER BONITO(GT_PCICONFIGBASE + 0x0c)
+//#define GT_PCIBASE0 BONITO(GT_PCICONFIGBASE + 0x10)
+//#define GT_PCIBASE1 BONITO(GT_PCICONFIGBASE + 0x14)
+//#define GT_PCIBASE2 BONITO(GT_PCICONFIGBASE + 0x18)
+//#define GT_PCIEXPRBASE BONITO(GT_PCICONFIGBASE + 0x30)
+//#define GT_PCIINT BONITO(GT_PCICONFIGBASE + 0x3c)
+
+/* PCI Configuration, Function 1, Register Map */
+
+/* I2O Support Register Map */
Property changes on: trunk/sys/mips/malta/gtreg.h
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Added: trunk/sys/mips/malta/gtvar.h
===================================================================
--- trunk/sys/mips/malta/gtvar.h (rev 0)
+++ trunk/sys/mips/malta/gtvar.h 2018-05-26 21:55:02 UTC (rev 9987)
@@ -0,0 +1,37 @@
+/* $MidnightBSD$ */
+/*-
+ * Copyright (c) 2005 Olivier Houchard. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+ * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+ * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/* $FreeBSD: stable/10/sys/mips/malta/gtvar.h 202175 2010-01-12 21:36:08Z imp $ */
+
+#ifndef _GTVAR_H_
+#define _GTVAR_H_
+
+#include <sys/rman.h>
+
+struct gt_softc {
+ device_t dev;
+};
+
+#endif /* _GTVAR_H_ */
Property changes on: trunk/sys/mips/malta/gtvar.h
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Added: trunk/sys/mips/malta/malta_machdep.c
===================================================================
--- trunk/sys/mips/malta/malta_machdep.c (rev 0)
+++ trunk/sys/mips/malta/malta_machdep.c 2018-05-26 21:55:02 UTC (rev 9987)
@@ -0,0 +1,315 @@
+/* $MidnightBSD$ */
+/*-
+ * Copyright (c) 2006 Wojciech A. Koszek <wkoszek at FreeBSD.org>
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ * $FreeBSD: stable/10/sys/mips/malta/malta_machdep.c 255088 2013-08-31 01:24:05Z gonzo $
+ */
+#include <sys/cdefs.h>
+__FBSDID("$FreeBSD: stable/10/sys/mips/malta/malta_machdep.c 255088 2013-08-31 01:24:05Z gonzo $");
+
+#include "opt_ddb.h"
+
+#include <sys/param.h>
+#include <sys/conf.h>
+#include <sys/kernel.h>
+#include <sys/systm.h>
+#include <sys/imgact.h>
+#include <sys/bio.h>
+#include <sys/buf.h>
+#include <sys/bus.h>
+#include <sys/cpu.h>
+#include <sys/cons.h>
+#include <sys/exec.h>
+#include <sys/ucontext.h>
+#include <sys/proc.h>
+#include <sys/kdb.h>
+#include <sys/ptrace.h>
+#include <sys/reboot.h>
+#include <sys/signalvar.h>
+#include <sys/sysent.h>
+#include <sys/sysproto.h>
+#include <sys/user.h>
+
+#include <vm/vm.h>
+#include <vm/vm_object.h>
+#include <vm/vm_page.h>
+
+#include <machine/clock.h>
+#include <machine/cpu.h>
+#include <machine/cpuregs.h>
+#include <machine/hwfunc.h>
+#include <machine/md_var.h>
+#include <machine/pmap.h>
+#include <machine/trap.h>
+
+#ifdef TICK_USE_YAMON_FREQ
+#include <mips/malta/yamon.h>
+#endif
+
+#ifdef TICK_USE_MALTA_RTC
+#include <mips/mips4k/malta/maltareg.h>
+#include <dev/mc146818/mc146818reg.h>
+#include <isa/rtc.h>
+#endif
+
+#include <mips/malta/maltareg.h>
+
+extern int *edata;
+extern int *end;
+
+void lcd_init(void);
+void lcd_puts(char *);
+void malta_reset(void);
+
+/*
+ * Temporary boot environment used at startup.
+ */
+static char boot1_env[4096];
+
+/*
+ * Offsets to MALTA LCD characters.
+ */
+static int malta_lcd_offs[] = {
+ MALTA_ASCIIPOS0,
+ MALTA_ASCIIPOS1,
+ MALTA_ASCIIPOS2,
+ MALTA_ASCIIPOS3,
+ MALTA_ASCIIPOS4,
+ MALTA_ASCIIPOS5,
+ MALTA_ASCIIPOS6,
+ MALTA_ASCIIPOS7
+};
+
+void
+platform_cpu_init()
+{
+ /* Nothing special */
+}
+
+/*
+ * Put character to Malta LCD at given position.
+ */
+static void
+malta_lcd_putc(int pos, char c)
+{
+ void *addr;
+ char *ch;
+
+ if (pos < 0 || pos > 7)
+ return;
+ addr = (void *)(MALTA_ASCII_BASE + malta_lcd_offs[pos]);
+ ch = (char *)MIPS_PHYS_TO_KSEG0(addr);
+ *ch = c;
+}
+
+/*
+ * Print given string on LCD.
+ */
+static void
+malta_lcd_print(char *str)
+{
+ int i;
+
+ if (str == NULL)
+ return;
+
+ for (i = 0; *str != '\0'; i++, str++)
+ malta_lcd_putc(i, *str);
+}
+
+void
+lcd_init(void)
+{
+ malta_lcd_print("FreeBSD_");
+}
+
+void
+lcd_puts(char *s)
+{
+ malta_lcd_print(s);
+}
+
+#ifdef TICK_USE_MALTA_RTC
+static __inline uint8_t
+rtcin(uint8_t addr)
+{
+
+ *((volatile uint8_t *)
+ MIPS_PHYS_TO_KSEG1(MALTA_PCI0_ADDR(MALTA_RTCADR))) = addr;
+ return (*((volatile uint8_t *)
+ MIPS_PHYS_TO_KSEG1(MALTA_PCI0_ADDR(MALTA_RTCDAT))));
+}
+
+static __inline void
+writertc(uint8_t addr, uint8_t val)
+{
+
+ *((volatile uint8_t *)
+ MIPS_PHYS_TO_KSEG1(MALTA_PCI0_ADDR(MALTA_RTCADR))) = addr;
+ *((volatile uint8_t *)
+ MIPS_PHYS_TO_KSEG1(MALTA_PCI0_ADDR(MALTA_RTCDAT))) = val;
+}
+#endif
+
+static void
+mips_init(void)
+{
+ int i;
+
+ for (i = 0; i < 10; i++) {
+ phys_avail[i] = 0;
+ }
+
+ /* phys_avail regions are in bytes */
+ phys_avail[0] = MIPS_KSEG0_TO_PHYS(kernel_kseg0_end);
+ phys_avail[1] = ctob(realmem);
+
+ dump_avail[0] = phys_avail[0];
+ dump_avail[1] = phys_avail[1];
+
+ physmem = realmem;
+
+ init_param1();
+ init_param2(physmem);
+ mips_cpu_init();
+ pmap_bootstrap();
+ mips_proc0_init();
+ mutex_init();
+ kdb_init();
+#ifdef KDB
+ if (boothowto & RB_KDB)
+ kdb_enter(KDB_WHY_BOOTFLAGS, "Boot flags requested debugger");
+#endif
+}
+
+/*
+ * Perform a board-level soft-reset.
+ * Note that this is not emulated by gxemul.
+ */
+void
+platform_reset(void)
+{
+ char *c;
+
+ c = (char *)MIPS_PHYS_TO_KSEG0(MALTA_SOFTRES);
+ *c = MALTA_GORESET;
+}
+
+static uint64_t
+malta_cpu_freq(void)
+{
+ uint64_t platform_counter_freq = 0;
+
+#if defined(TICK_USE_YAMON_FREQ)
+ /*
+ * If we are running on a board which uses YAMON firmware,
+ * then query CPU pipeline clock from the syscon object.
+ * If unsuccessful, use hard-coded default.
+ */
+ platform_counter_freq = yamon_getcpufreq();
+
+#elif defined(TICK_USE_MALTA_RTC)
+ /*
+ * If we are running on a board with the MC146818 RTC,
+ * use it to determine CPU pipeline clock frequency.
+ */
+ u_int64_t counterval[2];
+
+ /* Set RTC to binary mode. */
+ writertc(RTC_STATUSB, (rtcin(RTC_STATUSB) | RTCSB_BCD));
+
+ /* Busy-wait for falling edge of RTC update. */
+ while (((rtcin(RTC_STATUSA) & RTCSA_TUP) == 0))
+ ;
+ while (((rtcin(RTC_STATUSA)& RTCSA_TUP) != 0))
+ ;
+ counterval[0] = mips_rd_count();
+
+ /* Busy-wait for falling edge of RTC update. */
+ while (((rtcin(RTC_STATUSA) & RTCSA_TUP) == 0))
+ ;
+ while (((rtcin(RTC_STATUSA)& RTCSA_TUP) != 0))
+ ;
+ counterval[1] = mips_rd_count();
+
+ platform_counter_freq = counterval[1] - counterval[0];
+#endif
+
+ if (platform_counter_freq == 0)
+ platform_counter_freq = MIPS_DEFAULT_HZ;
+
+ return (platform_counter_freq);
+}
+
+void
+platform_start(__register_t a0, __register_t a1, __register_t a2,
+ __register_t a3)
+{
+ vm_offset_t kernend;
+ uint64_t platform_counter_freq;
+ int argc = a0;
+ int32_t *argv = (int32_t*)a1;
+ int32_t *envp = (int32_t*)a2;
+ unsigned int memsize = a3;
+ int i;
+
+ /* clear the BSS and SBSS segments */
+ kernend = (vm_offset_t)&end;
+ memset(&edata, 0, kernend - (vm_offset_t)(&edata));
+
+ mips_postboot_fixup();
+
+ mips_pcpu0_init();
+ platform_counter_freq = malta_cpu_freq();
+ mips_timer_early_init(platform_counter_freq);
+ init_static_kenv(boot1_env, sizeof(boot1_env));
+
+ cninit();
+ printf("entry: platform_start()\n");
+
+ bootverbose = 1;
+ /*
+ * YAMON uses 32bit pointers to strings so
+ * convert them to proper type manually
+ */
+ if (bootverbose) {
+ printf("cmd line: ");
+ for (i = 0; i < argc; i++)
+ printf("%s ", (char*)(intptr_t)argv[i]);
+ printf("\n");
+
+ printf("envp:\n");
+ for (i = 0; envp[i]; i += 2)
+ printf("\t%s = %s\n", (char*)(intptr_t)envp[i],
+ (char*)(intptr_t)envp[i+1]);
+
+ printf("memsize = %08x\n", memsize);
+ }
+
+ realmem = btoc(memsize);
+ mips_init();
+
+ mips_timer_init_params(platform_counter_freq, 0);
+}
Property changes on: trunk/sys/mips/malta/malta_machdep.c
___________________________________________________________________
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Added: trunk/sys/mips/malta/maltareg.h
===================================================================
--- trunk/sys/mips/malta/maltareg.h (rev 0)
+++ trunk/sys/mips/malta/maltareg.h 2018-05-26 21:55:02 UTC (rev 9987)
@@ -0,0 +1,244 @@
+/* $MidnightBSD$ */
+/* $NetBSD: maltareg.h,v 1.1 2002/03/07 14:44:04 simonb Exp $ */
+
+/*
+ * Copyright 2002 Wasabi Systems, Inc.
+ * All rights reserved.
+ *
+ * Written by Simon Burge for Wasabi Systems, Inc.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * 3. All advertising materials mentioning features or use of this software
+ * must display the following acknowledgement:
+ * This product includes software developed for the NetBSD Project by
+ * Wasabi Systems, Inc.
+ * 4. The name of Wasabi Systems, Inc. may not be used to endorse
+ * or promote products derived from this software without specific prior
+ * written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * $FreeBSD: stable/10/sys/mips/malta/maltareg.h 202175 2010-01-12 21:36:08Z imp $
+ */
+
+/*
+ Memory Map
+
+ 0000.0000 * 128MB Typically SDRAM (on Core Board)
+ 0800.0000 * 256MB Typically PCI
+ 1800.0000 * 62MB Typically PCI
+ 1be0.0000 * 2MB Typically System controller's internal registers
+ 1c00.0000 * 32MB Typically not used
+ 1e00.0000 4MB Monitor Flash
+ 1e40.0000 12MB reserved
+ 1f00.0000 12MB Switches
+ LEDs
+ ASCII display
+ Soft reset
+ FPGA revision number
+ CBUS UART (tty2)
+ General Purpose I/O
+ I2C controller
+ 1f10.0000 * 11MB Typically System Controller specific
+ 1fc0.0000 4MB Maps to Monitor Flash
+ 1fd0.0000 * 3MB Typically System Controller specific
+
+ * depends on implementation of the Core Board and of software
+ */
+
+/*
+ CPU interrupts
+
+ NMI South Bridge or NMI button
+ 0 South Bridge INTR
+ 1 South Bridge SMI
+ 2 CBUS UART (tty2)
+ 3 COREHI (Core Card)
+ 4 CORELO (Core Card)
+ 5 Not used, driven inactive (typically CPU internal timer interrupt
+
+ IRQ mapping (as used by YAMON)
+
+ 0 Timer South Bridge
+ 1 Keyboard SuperIO
+ 2 Reserved by South Bridge (for cascading)
+ 3 UART (tty1) SuperIO
+ 4 UART (tty0) SuperIO
+ 5 Not used
+ 6 Floppy Disk SuperIO
+ 7 Parallel Port SuperIO
+ 8 Real Time Clock South Bridge
+ 9 I2C bus South Bridge
+ 10 PCI A,B,eth PCI slot 1..4, Ethernet
+ 11 PCI C,audio PCI slot 1..4, Audio, USB (South Bridge)
+ PCI D,USB
+ 12 Mouse SuperIO
+ 13 Reserved by South Bridge
+ 14 Primary IDE Primary IDE slot
+ 15 Secondary IDE Secondary IDE slot/Compact flash connector
+ */
+
+#define MALTA_SYSTEMRAM_BASE 0x00000000ul /* System RAM: */
+#define MALTA_SYSTEMRAM_SIZE 0x08000000 /* 128 MByte */
+
+#define MALTA_PCIMEM1_BASE 0x08000000ul /* PCI 1 memory: */
+#define MALTA_PCIMEM1_SIZE 0x08000000 /* 128 MByte */
+
+#define MALTA_PCIMEM2_BASE 0x10000000ul /* PCI 2 memory: */
+#define MALTA_PCIMEM2_SIZE 0x08000000 /* 128 MByte */
+
+#define MALTA_PCIMEM3_BASE 0x18000000ul /* PCI 3 memory */
+#define MALTA_PCIMEM3_SIZE 0x03e00000 /* 62 MByte */
+
+#define MALTA_CORECTRL_BASE 0x1be00000ul /* Core control: */
+#define MALTA_CORECTRL_SIZE 0x00200000 /* 2 MByte */
+
+#define MALTA_RESERVED_BASE1 0x1c000000ul /* Reserved: */
+#define MALTA_RESERVED_SIZE1 0x02000000 /* 32 MByte */
+
+#define MALTA_MONITORFLASH_BASE 0x1e000000ul /* Monitor Flash: */
+#define MALTA_MONITORFLASH_SIZE 0x003e0000 /* 4 MByte */
+#define MALTA_MONITORFLASH_SECTORSIZE 0x00010000 /* Sect. = 64 KB */
+
+#define MALTA_FILEFLASH_BASE 0x1e3e0000ul /* File Flash (for monitor): */
+#define MALTA_FILEFLASH_SIZE 0x00020000 /* 128 KByte */
+
+#define MALTA_FILEFLASH_SECTORSIZE 0x00010000 /* Sect. = 64 KB */
+
+#define MALTA_RESERVED_BASE2 0x1e400000ul /* Reserved: */
+#define MALTA_RESERVED_SIZE2 0x00c00000 /* 12 MByte */
+
+#define MALTA_FPGA_BASE 0x1f000000ul /* FPGA: */
+#define MALTA_FPGA_SIZE 0x00c00000 /* 12 MByte */
+
+#define MALTA_NMISTATUS (MALTA_FPGA_BASE + 0x24)
+#define MALTA_NMI_SB 0x2 /* Pending NMI from the South Bridge */
+#define MALTA_NMI_ONNMI 0x1 /* Pending NMI from the ON/NMI push button */
+
+#define MALTA_NMIACK (MALTA_FPGA_BASE + 0x104)
+#define MALTA_NMIACK_ONNMI 0x1 /* Write 1 to acknowledge ON/NMI */
+
+#define MALTA_SWITCH (MALTA_FPGA_BASE + 0x200)
+#define MALTA_SWITCH_MASK 0xff /* settings of DIP switch S2 */
+
+#define MALTA_STATUS (MALTA_FPGA_BASE + 0x208)
+#define MALTA_ST_MFWR 0x10 /* Monitor Flash is write protected (JP1) */
+#define MALTA_S54 0x08 /* switch S5-4 - set YAMON factory default mode */
+#define MALTA_S53 0x04 /* switch S5-3 */
+#define MALTA_BIGEND 0x02 /* switch S5-2 - big endian mode */
+
+#define MALTA_JMPRS (MALTA_FPGA_BASE + 0x210)
+#define MALTA_JMPRS_PCICLK 0x1c /* PCI clock frequency */
+#define MALTA_JMPRS_EELOCK 0x02 /* I2C EEPROM is write protected */
+
+#define MALTA_LEDBAR (MALTA_FPGA_BASE + 0x408)
+#define MALTA_ASCIIWORD (MALTA_FPGA_BASE + 0x410)
+#define MALTA_ASCII_BASE (MALTA_FPGA_BASE + 0x418)
+#define MALTA_ASCIIPOS0 0x00
+#define MALTA_ASCIIPOS1 0x08
+#define MALTA_ASCIIPOS2 0x10
+#define MALTA_ASCIIPOS3 0x18
+#define MALTA_ASCIIPOS4 0x20
+#define MALTA_ASCIIPOS5 0x28
+#define MALTA_ASCIIPOS6 0x30
+#define MALTA_ASCIIPOS7 0x38
+
+#define MALTA_SOFTRES (MALTA_FPGA_BASE + 0x500)
+#define MALTA_GORESET 0x42 /* write this to MALTA_SOFTRES for board reset */
+
+/*
+ * BRKRES is the number of milliseconds before a "break" on tty will
+ * trigger a reset. A value of 0 will disable the reset.
+ */
+#define MALTA_BRKRES (MALTA_FPGA_BASE + 0x508)
+#define MALTA_BRKRES_MASK 0xff
+
+#define MALTA_CBUSUART (MALTA_FPGA_BASE + 0x900)
+/* 16C550C UART, 8 bit registers on 8 byte boundaries */
+/* RXTX 0x00 */
+/* INTEN 0x08 */
+/* IIFIFO 0x10 */
+/* LCTRL 0x18 */
+/* MCTRL 0x20 */
+/* LSTAT 0x28 */
+/* MSTAT 0x30 */
+/* SCRATCH 0x38 */
+#define MALTA_CBUSUART_INTR 2
+
+#define MALTA_GPIO_BASE (MALTA_FPGA_BASE + 0xa00)
+#define MALTA_GPOUT 0x0
+#define MALTA_GPINP 0x8
+
+#define MALTA_I2C_BASE (MALTA_FPGA_BASE + 0xb00)
+#define MALTA_I2CINP 0x00
+#define MALTA_I2COE 0x08
+#define MALTA_I2COUT 0x10
+#define MALTA_I2CSEL 0x18
+
+#define MALTA_BOOTROM_BASE 0x1fc00000ul /* Boot ROM: */
+#define MALTA_BOOTROM_SIZE 0x00400000 /* 4 MByte */
+
+#define MALTA_REVISION 0x1fc00010ul
+#define MALTA_REV_FPGRV 0xff0000 /* CBUS FPGA revision */
+#define MALTA_REV_CORID 0x00fc00 /* Core Board ID */
+#define MALTA_REV_CORRV 0x000300 /* Core Board Revision */
+#define MALTA_REV_PROID 0x0000f0 /* Product ID */
+#define MALTA_REV_PRORV 0x00000f /* Product Revision */
+
+/* PCI definitions */
+#define MALTA_SOUTHBRIDGE_INTR 0
+
+#define MALTA_PCI0_IO_BASE MALTA_PCIMEM3_BASE
+#define MALTA_PCI0_ADDR( addr ) (MALTA_PCI0_IO_BASE + (addr))
+
+#define MALTA_RTCADR 0x70 // MALTA_PCI_IO_ADDR8(0x70)
+#define MALTA_RTCDAT 0x71 // MALTA_PCI_IO_ADDR8(0x71)
+
+#define MALTA_SMSC_COM1_ADR 0x3f8
+#define MALTA_SMSC_COM2_ADR 0x2f8
+#define MALTA_UART0ADR MALTA_PCI0_ADDR(MALTA_SMSC_COM1_ADR)
+#define MALTA_UART1ADR MALTA_SMSC_COM2_ADR // MALTA_PCI0_ADDR(MALTA_SMSC_COM2_ADR)
+
+#define MALTA_SMSC_1284_ADR 0x378
+#define MALTA_1284ADR MALTA_SMSC_1284_ADR // MALTA_PCI0_ADDR(MALTA_SMSC_1284_ADR)
+
+#define MALTA_SMSC_FDD_ADR 0x3f0
+#define MALTA_FDDADR MALTA_SMSC_FDD_ADR // MALTA_PCI0_ADDR(MALTA_SMSC_FDD_ADR)
+
+#define MALTA_SMSC_KYBD_ADR 0x60 /* Fixed 0x60, 0x64 */
+#define MALTA_KYBDADR MALTA_SMSC_KYBD_ADR // MALTA_PCI0_ADDR(MALTA_SMSC_KYBD_ADR)
+#define MALTA_SMSC_MOUSE_ADR MALTA_SMSC_KYBD_ADR
+#define MALTA_MOUSEADR MALTA_KYBDADR
+
+
+#define MALTA_DMA_PCI_PCIBASE 0x00000000UL
+#define MALTA_DMA_PCI_PHYSBASE 0x00000000UL
+#define MALTA_DMA_PCI_SIZE (256 * 1024 * 1024)
+
+#define MALTA_DMA_ISA_PCIBASE 0x00800000UL
+#define MALTA_DMA_ISA_PHYSBASE 0x00000000UL
+#define MALTA_DMA_ISA_SIZE (8 * 1024 * 1024)
+
+#ifndef _LOCORE
+void led_bar(uint8_t);
+void led_display_word(uint32_t);
+void led_display_str(const char *);
+void led_display_char(int, uint8_t);
+#endif
Property changes on: trunk/sys/mips/malta/maltareg.h
___________________________________________________________________
Added: svn:eol-style
## -0,0 +1 ##
+native
\ No newline at end of property
Added: svn:keywords
## -0,0 +1 ##
+MidnightBSD=%H
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+text/plain
\ No newline at end of property
Added: trunk/sys/mips/malta/obio.c
===================================================================
--- trunk/sys/mips/malta/obio.c (rev 0)
+++ trunk/sys/mips/malta/obio.c 2018-05-26 21:55:02 UTC (rev 9987)
@@ -0,0 +1,184 @@
+/* $MidnightBSD$ */
+/* $NetBSD: obio.c,v 1.11 2003/07/15 00:25:05 lukem Exp $ */
+
+/*-
+ * Copyright (c) 2001, 2002, 2003 Wasabi Systems, Inc.
+ * All rights reserved.
+ *
+ * Written by Jason R. Thorpe for Wasabi Systems, Inc.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * 3. All advertising materials mentioning features or use of this software
+ * must display the following acknowledgement:
+ * This product includes software developed for the NetBSD Project by
+ * Wasabi Systems, Inc.
+ * 4. The name of Wasabi Systems, Inc. may not be used to endorse
+ * or promote products derived from this software without specific prior
+ * written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/*
+ * On-board device autoconfiguration support for Intel IQ80321
+ * evaluation boards.
+ */
+
+#include <sys/cdefs.h>
+__FBSDID("$FreeBSD: stable/10/sys/mips/malta/obio.c 202175 2010-01-12 21:36:08Z imp $");
+
+#include <sys/param.h>
+#include <sys/systm.h>
+#include <sys/bus.h>
+#include <sys/kernel.h>
+#include <sys/module.h>
+#include <sys/rman.h>
+#include <sys/malloc.h>
+
+#include <machine/bus.h>
+
+#include <mips/malta/maltareg.h>
+#include <mips/malta/obiovar.h>
+
+int obio_probe(device_t);
+int obio_attach(device_t);
+
+/*
+ * A bit tricky and hackish. Since we need OBIO to rely
+ * on PCI we make it pseudo-pci device. But there should
+ * be only one such device, so we use this static flag
+ * to prevent false positives on every real PCI device probe.
+ */
+static int have_one = 0;
+
+int
+obio_probe(device_t dev)
+{
+ if (!have_one) {
+ have_one = 1;
+ return 0;
+ }
+ return (ENXIO);
+}
+
+int
+obio_attach(device_t dev)
+{
+ struct obio_softc *sc = device_get_softc(dev);
+
+ sc->oba_st = mips_bus_space_generic;
+ sc->oba_addr = MIPS_PHYS_TO_KSEG1(MALTA_UART0ADR);
+ sc->oba_size = MALTA_PCIMEM3_SIZE;
+ sc->oba_rman.rm_type = RMAN_ARRAY;
+ sc->oba_rman.rm_descr = "OBIO I/O";
+ if (rman_init(&sc->oba_rman) != 0 ||
+ rman_manage_region(&sc->oba_rman,
+ sc->oba_addr, sc->oba_addr + sc->oba_size) != 0)
+ panic("obio_attach: failed to set up I/O rman");
+ sc->oba_irq_rman.rm_type = RMAN_ARRAY;
+ sc->oba_irq_rman.rm_descr = "OBIO IRQ";
+
+ /*
+ * This module is intended for UART purposes only and
+ * it's IRQ is 4
+ */
+ if (rman_init(&sc->oba_irq_rman) != 0 ||
+ rman_manage_region(&sc->oba_irq_rman, 4, 4) != 0)
+ panic("obio_attach: failed to set up IRQ rman");
+
+ device_add_child(dev, "uart", 0);
+ bus_generic_probe(dev);
+ bus_generic_attach(dev);
+
+ return (0);
+}
+
+static struct resource *
+obio_alloc_resource(device_t bus, device_t child, int type, int *rid,
+ u_long start, u_long end, u_long count, u_int flags)
+{
+ struct resource *rv;
+ struct rman *rm;
+ bus_space_tag_t bt = 0;
+ bus_space_handle_t bh = 0;
+ struct obio_softc *sc = device_get_softc(bus);
+
+ switch (type) {
+ case SYS_RES_IRQ:
+ rm = &sc->oba_irq_rman;
+ break;
+ case SYS_RES_MEMORY:
+ return (NULL);
+ case SYS_RES_IOPORT:
+ rm = &sc->oba_rman;
+ bt = sc->oba_st;
+ bh = sc->oba_addr;
+ start = bh;
+ break;
+ default:
+ return (NULL);
+ }
+
+
+ rv = rman_reserve_resource(rm, start, end, count, flags, child);
+ if (rv == NULL)
+ return (NULL);
+ if (type == SYS_RES_IRQ)
+ return (rv);
+ rman_set_rid(rv, *rid);
+ rman_set_bustag(rv, bt);
+ rman_set_bushandle(rv, bh);
+
+ if (0) {
+ if (bus_activate_resource(child, type, *rid, rv)) {
+ rman_release_resource(rv);
+ return (NULL);
+ }
+ }
+ return (rv);
+
+}
+
+static int
+obio_activate_resource(device_t bus, device_t child, int type, int rid,
+ struct resource *r)
+{
+ return (0);
+}
+static device_method_t obio_methods[] = {
+ DEVMETHOD(device_probe, obio_probe),
+ DEVMETHOD(device_attach, obio_attach),
+
+ DEVMETHOD(bus_alloc_resource, obio_alloc_resource),
+ DEVMETHOD(bus_activate_resource, obio_activate_resource),
+ DEVMETHOD(bus_setup_intr, bus_generic_setup_intr),
+ DEVMETHOD(bus_teardown_intr, bus_generic_teardown_intr),
+
+ {0, 0},
+};
+
+static driver_t obio_driver = {
+ "obio",
+ obio_methods,
+ sizeof(struct obio_softc),
+};
+static devclass_t obio_devclass;
+
+DRIVER_MODULE(obio, pci, obio_driver, obio_devclass, 0, 0);
Property changes on: trunk/sys/mips/malta/obio.c
___________________________________________________________________
Added: svn:eol-style
## -0,0 +1 ##
+native
\ No newline at end of property
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## -0,0 +1 ##
+MidnightBSD=%H
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+text/plain
\ No newline at end of property
Added: trunk/sys/mips/malta/obiovar.h
===================================================================
--- trunk/sys/mips/malta/obiovar.h (rev 0)
+++ trunk/sys/mips/malta/obiovar.h 2018-05-26 21:55:02 UTC (rev 9987)
@@ -0,0 +1,59 @@
+/* $MidnightBSD$ */
+/* $NetBSD: obiovar.h,v 1.4 2003/06/16 17:40:53 thorpej Exp $ */
+
+/*-
+ * Copyright (c) 2002, 2003 Wasabi Systems, Inc.
+ * All rights reserved.
+ *
+ * Written by Jason R. Thorpe for Wasabi Systems, Inc.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * 3. All advertising materials mentioning features or use of this software
+ * must display the following acknowledgement:
+ * This product includes software developed for the NetBSD Project by
+ * Wasabi Systems, Inc.
+ * 4. The name of Wasabi Systems, Inc. may not be used to endorse
+ * or promote products derived from this software without specific prior
+ * written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * $FreeBSD: stable/10/sys/mips/malta/obiovar.h 202175 2010-01-12 21:36:08Z imp $
+ *
+ */
+
+#ifndef _MALTA_OBIOVAR_H_
+#define _MALTA_OBIOVAR_H_
+
+#include <sys/rman.h>
+
+struct obio_softc {
+ bus_space_tag_t oba_st; /* bus space tag */
+ bus_addr_t oba_addr; /* address of device */
+ bus_size_t oba_size; /* size of device */
+ int oba_width; /* bus width */
+ int oba_irq; /* XINT interrupt bit # */
+ struct rman oba_rman;
+ struct rman oba_irq_rman;
+
+};
+extern struct bus_space obio_bs_tag;
+
+#endif /* _MALTA_OBIOVAR_H_ */
Property changes on: trunk/sys/mips/malta/obiovar.h
___________________________________________________________________
Added: svn:eol-style
## -0,0 +1 ##
+native
\ No newline at end of property
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## -0,0 +1 ##
+MidnightBSD=%H
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+text/plain
\ No newline at end of property
Added: trunk/sys/mips/malta/std.malta
===================================================================
--- trunk/sys/mips/malta/std.malta (rev 0)
+++ trunk/sys/mips/malta/std.malta 2018-05-26 21:55:02 UTC (rev 9987)
@@ -0,0 +1,11 @@
+# $FreeBSD: stable/10/sys/mips/malta/std.malta 249083 2013-04-04 07:12:24Z mav $
+files "../malta/files.malta"
+
+cpu CPU_MIPS4KC
+device pci
+device ata
+
+device scbus # SCSI bus (required for ATA/SCSI)
+device cd # CD
+device da # Direct Access (disks)
+device pass # Passthrough device (direct ATA/SCSI access)
Property changes on: trunk/sys/mips/malta/std.malta
___________________________________________________________________
Added: mnbsd:nokeywords
## -0,0 +1 ##
+MidnightBSD=%H
\ No newline at end of property
Added: trunk/sys/mips/malta/uart_bus_maltausart.c
===================================================================
--- trunk/sys/mips/malta/uart_bus_maltausart.c (rev 0)
+++ trunk/sys/mips/malta/uart_bus_maltausart.c 2018-05-26 21:55:02 UTC (rev 9987)
@@ -0,0 +1,92 @@
+/* $MidnightBSD$ */
+/*-
+ * Copyright (c) 2006 Wojciech A. Koszek <wkoszek at FreeBSD.org>
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * $Id$
+ */
+/*
+ * Skeleton of this file was based on respective code for ARM
+ * code written by Olivier Houchard.
+ */
+
+#include "opt_uart.h"
+
+#include <sys/cdefs.h>
+__FBSDID("$FreeBSD: stable/10/sys/mips/malta/uart_bus_maltausart.c 202175 2010-01-12 21:36:08Z imp $");
+
+#include <sys/param.h>
+#include <sys/systm.h>
+#include <sys/bus.h>
+#include <sys/conf.h>
+#include <sys/kernel.h>
+#include <sys/module.h>
+#include <machine/bus.h>
+#include <sys/rman.h>
+#include <machine/resource.h>
+
+#include <dev/pci/pcivar.h>
+
+#include <dev/uart/uart.h>
+#include <dev/uart/uart_bus.h>
+#include <dev/uart/uart_cpu.h>
+
+#include <mips/malta/maltareg.h>
+
+#include "uart_if.h"
+
+static int uart_malta_probe(device_t dev);
+
+extern struct uart_class malta_uart_class;
+
+static device_method_t uart_malta_methods[] = {
+ /* Device interface */
+ DEVMETHOD(device_probe, uart_malta_probe),
+ DEVMETHOD(device_attach, uart_bus_attach),
+ DEVMETHOD(device_detach, uart_bus_detach),
+ { 0, 0 }
+};
+
+static driver_t uart_malta_driver = {
+ uart_driver_name,
+ uart_malta_methods,
+ sizeof(struct uart_softc),
+};
+
+extern SLIST_HEAD(uart_devinfo_list, uart_devinfo) uart_sysdevs;
+static int
+uart_malta_probe(device_t dev)
+{
+ struct uart_softc *sc;
+
+ sc = device_get_softc(dev);
+ sc->sc_sysdev = SLIST_FIRST(&uart_sysdevs);
+ sc->sc_class = &uart_ns8250_class;
+ bcopy(&sc->sc_sysdev->bas, &sc->sc_bas, sizeof(sc->sc_bas));
+ sc->sc_sysdev->bas.bst = mips_bus_space_generic;
+ sc->sc_sysdev->bas.bsh = MIPS_PHYS_TO_KSEG1(MALTA_UART0ADR);
+ sc->sc_bas.bst = mips_bus_space_generic;
+ sc->sc_bas.bsh = MIPS_PHYS_TO_KSEG1(MALTA_UART0ADR);
+ return(uart_bus_probe(dev, 0, 0, 0, 0));
+}
+
+DRIVER_MODULE(uart, obio, uart_malta_driver, uart_devclass, 0, 0);
Property changes on: trunk/sys/mips/malta/uart_bus_maltausart.c
___________________________________________________________________
Added: svn:eol-style
## -0,0 +1 ##
+native
\ No newline at end of property
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## -0,0 +1 ##
+MidnightBSD=%H
\ No newline at end of property
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## -0,0 +1 ##
+text/plain
\ No newline at end of property
Added: trunk/sys/mips/malta/uart_cpu_maltausart.c
===================================================================
--- trunk/sys/mips/malta/uart_cpu_maltausart.c (rev 0)
+++ trunk/sys/mips/malta/uart_cpu_maltausart.c 2018-05-26 21:55:02 UTC (rev 9987)
@@ -0,0 +1,79 @@
+/* $MidnightBSD$ */
+/*-
+ * Copyright (c) 2006 Wojciech A. Koszek <wkoszek at FreeBSD.org>
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ * $Id$
+ */
+/*
+ * Skeleton of this file was based on respective code for ARM
+ * code written by Olivier Houchard.
+ */
+#include "opt_uart.h"
+
+#include <sys/cdefs.h>
+__FBSDID("$FreeBSD: stable/10/sys/mips/malta/uart_cpu_maltausart.c 202175 2010-01-12 21:36:08Z imp $");
+
+#include <sys/param.h>
+#include <sys/systm.h>
+#include <sys/bus.h>
+#include <sys/cons.h>
+
+#include <machine/bus.h>
+
+#include <dev/uart/uart.h>
+#include <dev/uart/uart_cpu.h>
+
+#include <mips/malta/maltareg.h>
+
+bus_space_tag_t uart_bus_space_io;
+bus_space_tag_t uart_bus_space_mem;
+
+extern struct uart_ops malta_usart_ops;
+extern struct bus_space malta_bs_tag;
+
+int
+uart_cpu_eqres(struct uart_bas *b1, struct uart_bas *b2)
+{
+ return ((b1->bsh == b2->bsh && b1->bst == b2->bst) ? 1 : 0);
+}
+
+int
+uart_cpu_getdev(int devtype, struct uart_devinfo *di)
+{
+ di->ops = uart_getops(&uart_ns8250_class);
+ di->bas.chan = 0;
+ di->bas.bst = mips_bus_space_generic;
+ di->bas.bsh = MIPS_PHYS_TO_KSEG1(MALTA_UART0ADR);
+ di->bas.regshft = 0;
+ di->bas.rclk = 0;
+ di->baudrate = 0; /* retain the baudrate configured by YAMON */
+ di->databits = 8;
+ di->stopbits = 1;
+ di->parity = UART_PARITY_NONE;
+
+ uart_bus_space_io = NULL;
+ uart_bus_space_mem = mips_bus_space_generic;
+ return (0);
+}
Property changes on: trunk/sys/mips/malta/uart_cpu_maltausart.c
___________________________________________________________________
Added: svn:eol-style
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+native
\ No newline at end of property
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## -0,0 +1 ##
+MidnightBSD=%H
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## -0,0 +1 ##
+text/plain
\ No newline at end of property
Added: trunk/sys/mips/malta/yamon.c
===================================================================
--- trunk/sys/mips/malta/yamon.c (rev 0)
+++ trunk/sys/mips/malta/yamon.c 2018-05-26 21:55:02 UTC (rev 9987)
@@ -0,0 +1,67 @@
+/* $MidnightBSD$ */
+/*-
+ * Copyright (c) 2006-2008 Bruce M. Simpson
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions, and the following disclaimer,
+ * without modification, immediately at the beginning of the file.
+ * 2. The name of the author may not be used to endorse or promote products
+ * derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ */
+
+#include <sys/cdefs.h>
+__FBSDID("$FreeBSD: stable/10/sys/mips/malta/yamon.c 254944 2013-08-27 01:08:55Z gonzo $");
+
+#include <sys/param.h>
+#include <sys/systm.h>
+
+#include <mips/malta/yamon.h>
+
+char *
+yamon_getenv(char *name)
+{
+ char *value;
+ yamon_env_t *p;
+
+ value = NULL;
+ for (p = *fenvp; p->name != NULL; ++p) {
+ if (!strcmp(name, p->name)) {
+ value = p->value;
+ break;
+ }
+ }
+
+ return (value);
+}
+
+uint32_t
+yamon_getcpufreq(void)
+{
+ uint32_t freq;
+ int ret;
+
+ freq = 0;
+ ret = YAMON_SYSCON_READ(SYSCON_BOARD_CPU_CLOCK_FREQ_ID, &freq,
+ sizeof(freq));
+ if (ret != 0)
+ freq = 0;
+
+ return (freq);
+}
Property changes on: trunk/sys/mips/malta/yamon.c
___________________________________________________________________
Added: svn:eol-style
## -0,0 +1 ##
+native
\ No newline at end of property
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## -0,0 +1 ##
+MidnightBSD=%H
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+text/plain
\ No newline at end of property
Added: trunk/sys/mips/malta/yamon.h
===================================================================
--- trunk/sys/mips/malta/yamon.h (rev 0)
+++ trunk/sys/mips/malta/yamon.h 2018-05-26 21:55:02 UTC (rev 9987)
@@ -0,0 +1,94 @@
+/* $MidnightBSD$ */
+/*-
+ * Copyright 2002 Wasabi Systems, Inc.
+ * All rights reserved.
+ *
+ * Written by Simon Burge for Wasabi Systems, Inc.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * 3. All advertising materials mentioning features or use of this software
+ * must display the following acknowledgement:
+ * This product includes software developed for the NetBSD Project by
+ * Wasabi Systems, Inc.
+ * 4. The name of Wasabi Systems, Inc. may not be used to endorse
+ * or promote products derived from this software without specific prior
+ * written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * $FreeBSD: stable/10/sys/mips/malta/yamon.h 202175 2010-01-12 21:36:08Z imp $
+ */
+
+#ifndef _MALTA_YAMON_H_
+#define _MALTA_YAMON_H_
+
+#define YAMON_FUNCTION_BASE 0x1fc00500ul
+
+#define YAMON_PRINT_COUNT_OFS (YAMON_FUNCTION_BASE + 0x04)
+#define YAMON_EXIT_OFS (YAMON_FUNCTION_BASE + 0x20)
+#define YAMON_FLUSH_CACHE_OFS (YAMON_FUNCTION_BASE + 0x2c)
+#define YAMON_PRINT_OFS (YAMON_FUNCTION_BASE + 0x34)
+#define YAMON_REG_CPU_ISR_OFS (YAMON_FUNCTION_BASE + 0x38)
+#define YAMON_DEREG_CPU_ISR_OFS (YAMON_FUNCTION_BASE + 0x3c)
+#define YAMON_REG_IC_ISR_OFS (YAMON_FUNCTION_BASE + 0x40)
+#define YAMON_DEREG_IC_ISR_OFS (YAMON_FUNCTION_BASE + 0x44)
+#define YAMON_REG_ESR_OFS (YAMON_FUNCTION_BASE + 0x48)
+#define YAMON_DEREG_ESR_OFS (YAMON_FUNCTION_BASE + 0x4c)
+#define YAMON_GETCHAR_OFS (YAMON_FUNCTION_BASE + 0x50)
+#define YAMON_SYSCON_READ_OFS (YAMON_FUNCTION_BASE + 0x54)
+
+#define YAMON_FUNC(ofs) ((long)(*(int32_t *)(MIPS_PHYS_TO_KSEG0(ofs))))
+
+typedef void (*t_yamon_print_count)(uint32_t port, char *s, uint32_t count);
+#define YAMON_PRINT_COUNT(s, count) \
+ ((t_yamon_print_count)(YAMON_FUNC(YAMON_PRINT_COUNT_OFS)))(0, s, count)
+
+typedef void (*t_yamon_exit)(uint32_t rc);
+#define YAMON_EXIT(rc) ((t_yamon_exit)(YAMON_FUNC(YAMON_EXIT_OFS)))(rc)
+
+typedef void (*t_yamon_print)(uint32_t port, const char *s);
+#define YAMON_PRINT(s) ((t_yamon_print)(YAMON_FUNC(YAMON_PRINT_OFS)))(0, s)
+
+typedef int (*t_yamon_getchar)(uint32_t port, char *ch);
+#define YAMON_GETCHAR(ch) \
+ ((t_yamon_getchar)(YAMON_FUNC(YAMON_GETCHAR_OFS)))(0, ch)
+
+typedef int t_yamon_syscon_id;
+typedef int (*t_yamon_syscon_read)(t_yamon_syscon_id id, void *param,
+ uint32_t size);
+#define YAMON_SYSCON_READ(id, param, size) \
+ ((t_yamon_syscon_read)(YAMON_FUNC(YAMON_SYSCON_READ_OFS))) \
+ (id, param, size)
+
+typedef struct {
+ char *name;
+ char *value;
+} yamon_env_t;
+
+#define SYSCON_BOARD_CPU_CLOCK_FREQ_ID 34 /* UINT32 */
+#define SYSCON_BOARD_BUS_CLOCK_FREQ_ID 35 /* UINT32 */
+#define SYSCON_BOARD_PCI_FREQ_KHZ_ID 36 /* UINT32 */
+
+char* yamon_getenv(char *name);
+uint32_t yamon_getcpufreq(void);
+
+extern yamon_env_t *fenvp[];
+
+#endif /* _MALTA_YAMON_H_ */
Property changes on: trunk/sys/mips/malta/yamon.h
___________________________________________________________________
Added: svn:eol-style
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+native
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+MidnightBSD=%H
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+text/plain
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Added: trunk/sys/mips/mips/autoconf.c
===================================================================
--- trunk/sys/mips/mips/autoconf.c (rev 0)
+++ trunk/sys/mips/mips/autoconf.c 2018-05-26 21:55:02 UTC (rev 9987)
@@ -0,0 +1,114 @@
+/* $MidnightBSD$ */
+/*-
+ * Copyright (c) 1990 The Regents of the University of California.
+ * All rights reserved.
+ *
+ * This code is derived from software contributed to Berkeley by
+ * William Jolitz.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * 4. Neither the name of the University nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ * from: @(#)autoconf.c 7.1 (Berkeley) 5/9/91
+ */
+
+#include <sys/cdefs.h>
+__FBSDID("$FreeBSD: stable/10/sys/mips/mips/autoconf.c 206834 2010-04-19 07:34:26Z jmallett $");
+
+/*
+ * Setup the system to run on the current machine.
+ *
+ * Configure() is called at boot time and initializes the vba
+ * device tables and the memory controller monitoring. Available
+ * devices are determined (from possibilities mentioned in ioconf.c),
+ * and the drivers are initialized.
+ */
+#include "opt_bootp.h"
+#include "opt_bus.h"
+
+#include <sys/param.h>
+#include <sys/systm.h>
+#include <sys/bus.h>
+#include <sys/conf.h>
+#include <sys/reboot.h>
+#include <sys/kernel.h>
+#include <sys/malloc.h>
+#include <sys/mount.h>
+#include <sys/cons.h>
+
+#include <sys/socket.h>
+#include <net/if.h>
+#include <net/if_dl.h>
+#include <net/if_types.h>
+#include <net/if_var.h>
+#include <net/ethernet.h>
+#include <netinet/in.h>
+
+#include <machine/cpufunc.h>
+#include <machine/md_var.h>
+
+static void configure_first(void *);
+static void configure(void *);
+static void configure_final(void *);
+
+SYSINIT(configure1, SI_SUB_CONFIGURE, SI_ORDER_FIRST, configure_first, NULL);
+/* SI_ORDER_SECOND is hookable */
+SYSINIT(configure2, SI_SUB_CONFIGURE, SI_ORDER_THIRD, configure, NULL);
+/* SI_ORDER_MIDDLE is hookable */
+SYSINIT(configure3, SI_SUB_CONFIGURE, SI_ORDER_ANY, configure_final, NULL);
+
+/*
+ * Determine i/o configuration for a machine.
+ */
+static void
+configure_first(dummy)
+ void *dummy;
+{
+
+ /* nexus0 is the top of the mips device tree */
+ device_add_child(root_bus, "nexus", 0);
+}
+
+static void
+configure(dummy)
+ void *dummy;
+{
+
+ /* initialize new bus architecture */
+ root_bus_configure();
+}
+
+static void
+configure_final(dummy)
+ void *dummy;
+{
+ intr_enable();
+
+ cninit_finish();
+
+ if (bootverbose)
+ printf("Device configuration finished.\n");
+
+ cold = 0;
+}
Property changes on: trunk/sys/mips/mips/autoconf.c
___________________________________________________________________
Added: svn:eol-style
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+native
\ No newline at end of property
Added: svn:keywords
## -0,0 +1 ##
+MidnightBSD=%H
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+text/plain
\ No newline at end of property
Added: trunk/sys/mips/mips/bcopy.S
===================================================================
--- trunk/sys/mips/mips/bcopy.S (rev 0)
+++ trunk/sys/mips/mips/bcopy.S 2018-05-26 21:55:02 UTC (rev 9987)
@@ -0,0 +1,287 @@
+/* $MidnightBSD$ */
+/* $NetBSD: bcopy.S,v 1.3 2009/12/14 00:39:00 matt Exp $ */
+
+/*
+ * Mach Operating System
+ * Copyright (c) 1993 Carnegie Mellon University
+ * All Rights Reserved.
+ *
+ * Permission to use, copy, modify and distribute this software and its
+ * documentation is hereby granted, provided that both the copyright
+ * notice and this permission notice appear in all copies of the
+ * software, derivative works or modified versions, and any portions
+ * thereof, and that both notices appear in supporting documentation.
+ *
+ * CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS"
+ * CONDITION. CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND FOR
+ * ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE.
+ *
+ * Carnegie Mellon requests users of this software to return to
+ *
+ * Software Distribution Coordinator or Software.Distribution at CS.CMU.EDU
+ * School of Computer Science
+ * Carnegie Mellon University
+ * Pittsburgh PA 15213-3890
+ *
+ * any improvements or extensions that they make and grant Carnegie Mellon
+ * the rights to redistribute these changes.
+ */
+
+/*
+ * File: mips_bcopy.s
+ * Author: Chris Maeda
+ * Date: June 1993
+ *
+ * Fast copy routine. Derived from aligned_block_copy.
+ */
+
+
+#include <machine/asm.h>
+__FBSDID("$FreeBSD: stable/10/sys/mips/mips/bcopy.S 255367 2013-09-07 16:31:30Z jchandra $");
+
+#include <machine/endian.h>
+
+#if defined(LIBC_SCCS) && !defined(lint)
+#if 0
+ ASMSTR("from: @(#)mips_bcopy.s 2.2 CMU 18/06/93")
+#else
+ ASMSTR("$NetBSD: bcopy.S,v 1.3 2009/12/14 00:39:00 matt Exp $")
+#endif
+#endif /* LIBC_SCCS and not lint */
+
+#ifdef __ABICALLS__
+ .abicalls
+#endif
+
+/*
+ * bcopy(caddr_t src, caddr_t dst, unsigned int len)
+ *
+ * a0 src address
+ * a1 dst address
+ * a2 length
+ */
+
+#define SRCREG a0
+#define DSTREG a1
+#define SIZEREG a2
+
+LEAF(memcpy)
+ .set noat
+ .set noreorder
+
+ move v0, a0
+ move a0, a1
+ move a1, v0
+
+ALEAF(bcopy)
+ALEAF(ovbcopy)
+ /*
+ * Make sure we can copy forwards.
+ */
+ sltu t0,SRCREG,DSTREG # t0 == SRCREG < DSTREG
+ bne t0,zero,6f # copy backwards
+
+ /*
+ * There are four alignment cases (with frequency)
+ * (Based on measurements taken with a DECstation 5000/200
+ * inside a Mach kernel.)
+ *
+ * aligned -> aligned (mostly)
+ * unaligned -> aligned (sometimes)
+ * aligned,unaligned -> unaligned (almost never)
+ *
+ * Note that we could add another case that checks if
+ * the destination and source are unaligned but the
+ * copy is alignable. eg if src and dest are both
+ * on a halfword boundary.
+ */
+ andi t1,DSTREG,(SZREG-1) # get last bits of dest
+ bne t1,zero,3f # dest unaligned
+ andi t0,SRCREG,(SZREG-1) # get last bits of src
+ bne t0,zero,5f
+
+ /*
+ * Forward aligned->aligned copy, 8 words at a time.
+ */
+98:
+ li AT,-(SZREG*8)
+ and t0,SIZEREG,AT # count truncated to multiples
+ PTR_ADDU a3,SRCREG,t0 # run fast loop up to this addr
+ sltu AT,SRCREG,a3 # any work to do?
+ beq AT,zero,2f
+ PTR_SUBU SIZEREG,t0
+
+ /*
+ * loop body
+ */
+1: # cp
+ REG_L t3,(0*SZREG)(SRCREG)
+ REG_L v1,(1*SZREG)(SRCREG)
+ REG_L t0,(2*SZREG)(SRCREG)
+ REG_L t1,(3*SZREG)(SRCREG)
+ PTR_ADDU SRCREG,SZREG*8
+ REG_S t3,(0*SZREG)(DSTREG)
+ REG_S v1,(1*SZREG)(DSTREG)
+ REG_S t0,(2*SZREG)(DSTREG)
+ REG_S t1,(3*SZREG)(DSTREG)
+ REG_L t1,(-1*SZREG)(SRCREG)
+ REG_L t0,(-2*SZREG)(SRCREG)
+ REG_L v1,(-3*SZREG)(SRCREG)
+ REG_L t3,(-4*SZREG)(SRCREG)
+ PTR_ADDU DSTREG,SZREG*8
+ REG_S t1,(-1*SZREG)(DSTREG)
+ REG_S t0,(-2*SZREG)(DSTREG)
+ REG_S v1,(-3*SZREG)(DSTREG)
+ bne SRCREG,a3,1b
+ REG_S t3,(-4*SZREG)(DSTREG)
+
+ /*
+ * Copy a word at a time, no loop unrolling.
+ */
+2: # wordcopy
+ andi t2,SIZEREG,(SZREG-1) # get byte count / SZREG
+ PTR_SUBU t2,SIZEREG,t2 # t2 = words to copy * SZREG
+ beq t2,zero,3f
+ PTR_ADDU t0,SRCREG,t2 # stop at t0
+ PTR_SUBU SIZEREG,SIZEREG,t2
+1:
+ REG_L t3,0(SRCREG)
+ PTR_ADDU SRCREG,SZREG
+ REG_S t3,0(DSTREG)
+ bne SRCREG,t0,1b
+ PTR_ADDU DSTREG,SZREG
+
+3: # bytecopy
+ beq SIZEREG,zero,4f # nothing left to do?
+ nop
+1:
+ lb t3,0(SRCREG)
+ PTR_ADDU SRCREG,1
+ sb t3,0(DSTREG)
+ PTR_SUBU SIZEREG,1
+ bgtz SIZEREG,1b
+ PTR_ADDU DSTREG,1
+
+4: # copydone
+ j ra
+ nop
+
+ /*
+ * Copy from unaligned source to aligned dest.
+ */
+5: # destaligned
+ andi t0,SIZEREG,(SZREG-1) # t0 = bytecount mod SZREG
+ PTR_SUBU a3,SIZEREG,t0 # number of words to transfer
+ beq a3,zero,3b
+ nop
+ move SIZEREG,t0 # this many to do after we are done
+ PTR_ADDU a3,SRCREG,a3 # stop point
+
+1:
+ REG_LHI t3,0(SRCREG)
+ REG_LLO t3,SZREG-1(SRCREG)
+ PTR_ADDI SRCREG,SZREG
+ REG_S t3,0(DSTREG)
+ bne SRCREG,a3,1b
+ PTR_ADDI DSTREG,SZREG
+
+ b 3b
+ nop
+
+6: # backcopy -- based on above
+ PTR_ADDU SRCREG,SIZEREG
+ PTR_ADDU DSTREG,SIZEREG
+ andi t1,DSTREG,SZREG-1 # get last 3 bits of dest
+ bne t1,zero,3f
+ andi t0,SRCREG,SZREG-1 # get last 3 bits of src
+ bne t0,zero,5f
+
+ /*
+ * Forward aligned->aligned copy, 8*4 bytes at a time.
+ */
+ li AT,(-8*SZREG)
+ and t0,SIZEREG,AT # count truncated to multiple of 32
+ beq t0,zero,2f # any work to do?
+ PTR_SUBU SIZEREG,t0
+ PTR_SUBU a3,SRCREG,t0
+
+ /*
+ * loop body
+ */
+1: # cp
+ REG_L t3,(-4*SZREG)(SRCREG)
+ REG_L v1,(-3*SZREG)(SRCREG)
+ REG_L t0,(-2*SZREG)(SRCREG)
+ REG_L t1,(-1*SZREG)(SRCREG)
+ PTR_SUBU SRCREG,8*SZREG
+ REG_S t3,(-4*SZREG)(DSTREG)
+ REG_S v1,(-3*SZREG)(DSTREG)
+ REG_S t0,(-2*SZREG)(DSTREG)
+ REG_S t1,(-1*SZREG)(DSTREG)
+ REG_L t1,(3*SZREG)(SRCREG)
+ REG_L t0,(2*SZREG)(SRCREG)
+ REG_L v1,(1*SZREG)(SRCREG)
+ REG_L t3,(0*SZREG)(SRCREG)
+ PTR_SUBU DSTREG,8*SZREG
+ REG_S t1,(3*SZREG)(DSTREG)
+ REG_S t0,(2*SZREG)(DSTREG)
+ REG_S v1,(1*SZREG)(DSTREG)
+ bne SRCREG,a3,1b
+ REG_S t3,(0*SZREG)(DSTREG)
+
+ /*
+ * Copy a word at a time, no loop unrolling.
+ */
+2: # wordcopy
+ andi t2,SIZEREG,SZREG-1 # get byte count / 4
+ PTR_SUBU t2,SIZEREG,t2 # t2 = number of words to copy
+ beq t2,zero,3f
+ PTR_SUBU t0,SRCREG,t2 # stop at t0
+ PTR_SUBU SIZEREG,SIZEREG,t2
+1:
+ REG_L t3,-SZREG(SRCREG)
+ PTR_SUBU SRCREG,SZREG
+ REG_S t3,-SZREG(DSTREG)
+ bne SRCREG,t0,1b
+ PTR_SUBU DSTREG,SZREG
+
+3: # bytecopy
+ beq SIZEREG,zero,4f # nothing left to do?
+ nop
+1:
+ lb t3,-1(SRCREG)
+ PTR_SUBU SRCREG,1
+ sb t3,-1(DSTREG)
+ PTR_SUBU SIZEREG,1
+ bgtz SIZEREG,1b
+ PTR_SUBU DSTREG,1
+
+4: # copydone
+ j ra
+ nop
+
+ /*
+ * Copy from unaligned source to aligned dest.
+ */
+5: # destaligned
+ andi t0,SIZEREG,SZREG-1 # t0 = bytecount mod 4
+ PTR_SUBU a3,SIZEREG,t0 # number of words to transfer
+ beq a3,zero,3b
+ nop
+ move SIZEREG,t0 # this many to do after we are done
+ PTR_SUBU a3,SRCREG,a3 # stop point
+
+1:
+ REG_LHI t3,-SZREG(SRCREG)
+ REG_LLO t3,-1(SRCREG)
+ PTR_SUBU SRCREG,SZREG
+ REG_S t3,-SZREG(DSTREG)
+ bne SRCREG,a3,1b
+ PTR_SUBU DSTREG,SZREG
+
+ b 3b
+ nop
+
+ .set reorder
+ .set at
+END(memcpy)
Property changes on: trunk/sys/mips/mips/bcopy.S
___________________________________________________________________
Added: svn:eol-style
## -0,0 +1 ##
+native
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## -0,0 +1 ##
+MidnightBSD=%H
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Added: trunk/sys/mips/mips/bus_space_fdt.c
===================================================================
--- trunk/sys/mips/mips/bus_space_fdt.c (rev 0)
+++ trunk/sys/mips/mips/bus_space_fdt.c 2018-05-26 21:55:02 UTC (rev 9987)
@@ -0,0 +1,206 @@
+/* $MidnightBSD$ */
+/* $NetBSD: bus.h,v 1.12 1997/10/01 08:25:15 fvdl Exp $ */
+/*-
+ * $Id: bus.h,v 1.6 2007/08/09 11:23:32 katta Exp $
+ *
+ * Copyright (c) 1996, 1997 The NetBSD Foundation, Inc.
+ * All rights reserved.
+ *
+ * This code is derived from software contributed to The NetBSD Foundation
+ * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility,
+ * NASA Ames Research Center.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
+ * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/*
+ * Copyright (c) 1996 Charles M. Hannum. All rights reserved.
+ * Copyright (c) 1996 Christopher G. Demetriou. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * 3. All advertising materials mentioning features or use of this software
+ * must display the following acknowledgement:
+ * This product includes software developed by Christopher G. Demetriou
+ * for the NetBSD Project.
+ * 4. The name of the author may not be used to endorse or promote products
+ * derived from this software without specific prior written permission
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+ * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+ * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * from: src/sys/alpha/include/bus.h,v 1.5 1999/08/28 00:38:40 peter
+ * $FreeBSD: stable/10/sys/mips/mips/bus_space_fdt.c 263687 2014-03-24 13:48:04Z emaste $
+ */
+#include <sys/cdefs.h>
+__FBSDID("$FreeBSD: stable/10/sys/mips/mips/bus_space_fdt.c 263687 2014-03-24 13:48:04Z emaste $");
+
+#include <sys/param.h>
+#include <sys/systm.h>
+#include <sys/bus.h>
+#include <sys/kernel.h>
+#include <sys/malloc.h>
+#include <sys/ktr.h>
+
+#include <vm/vm.h>
+#include <vm/pmap.h>
+#include <vm/vm_kern.h>
+#include <vm/vm_extern.h>
+
+#include <machine/bus.h>
+#include <machine/cache.h>
+
+static int fdt_bs_map(void *, bus_addr_t, bus_size_t, int,
+ bus_space_handle_t *);
+
+static struct bus_space fdt_space = {
+ /* cookie */
+ .bs_cookie = (void *) 0,
+
+ /* mapping/unmapping */
+ .bs_map = fdt_bs_map,
+ .bs_unmap = generic_bs_unmap,
+ .bs_subregion = generic_bs_subregion,
+
+ /* allocation/deallocation */
+ .bs_alloc = generic_bs_alloc,
+ .bs_free = generic_bs_free,
+
+ /* barrier */
+ .bs_barrier = generic_bs_barrier,
+
+ /* read (single) */
+ .bs_r_1 = generic_bs_r_1,
+ .bs_r_2 = generic_bs_r_2,
+ .bs_r_4 = generic_bs_r_4,
+ .bs_r_8 = generic_bs_r_8,
+
+ /* read multiple */
+ .bs_rm_1 = generic_bs_rm_1,
+ .bs_rm_2 = generic_bs_rm_2,
+ .bs_rm_4 = generic_bs_rm_4,
+ .bs_rm_8 = generic_bs_rm_8,
+
+ /* read region */
+ .bs_rr_1 = generic_bs_rr_1,
+ .bs_rr_2 = generic_bs_rr_2,
+ .bs_rr_4 = generic_bs_rr_4,
+ .bs_rr_8 = generic_bs_rr_8,
+
+ /* write (single) */
+ .bs_w_1 = generic_bs_w_1,
+ .bs_w_2 = generic_bs_w_2,
+ .bs_w_4 = generic_bs_w_4,
+ .bs_w_8 = generic_bs_w_8,
+
+ /* write multiple */
+ .bs_wm_1 = generic_bs_wm_1,
+ .bs_wm_2 = generic_bs_wm_2,
+ .bs_wm_4 = generic_bs_wm_4,
+ .bs_wm_8 = generic_bs_wm_8,
+
+ /* write region */
+ .bs_wr_1 = generic_bs_wr_1,
+ .bs_wr_2 = generic_bs_wr_2,
+ .bs_wr_4 = generic_bs_wr_4,
+ .bs_wr_8 = generic_bs_wr_8,
+
+ /* set multiple */
+ .bs_sm_1 = generic_bs_sm_1,
+ .bs_sm_2 = generic_bs_sm_2,
+ .bs_sm_4 = generic_bs_sm_4,
+ .bs_sm_8 = generic_bs_sm_8,
+
+ /* set region */
+ .bs_sr_1 = generic_bs_sr_1,
+ .bs_sr_2 = generic_bs_sr_2,
+ .bs_sr_4 = generic_bs_sr_4,
+ .bs_sr_8 = generic_bs_sr_8,
+
+ /* copy */
+ .bs_c_1 = generic_bs_c_1,
+ .bs_c_2 = generic_bs_c_2,
+ .bs_c_4 = generic_bs_c_4,
+ .bs_c_8 = generic_bs_c_8,
+
+ /* read (single) stream */
+ .bs_r_1_s = generic_bs_r_1,
+ .bs_r_2_s = generic_bs_r_2,
+ .bs_r_4_s = generic_bs_r_4,
+ .bs_r_8_s = generic_bs_r_8,
+
+ /* read multiple stream */
+ .bs_rm_1_s = generic_bs_rm_1,
+ .bs_rm_2_s = generic_bs_rm_2,
+ .bs_rm_4_s = generic_bs_rm_4,
+ .bs_rm_8_s = generic_bs_rm_8,
+
+ /* read region stream */
+ .bs_rr_1_s = generic_bs_rr_1,
+ .bs_rr_2_s = generic_bs_rr_2,
+ .bs_rr_4_s = generic_bs_rr_4,
+ .bs_rr_8_s = generic_bs_rr_8,
+
+ /* write (single) stream */
+ .bs_w_1_s = generic_bs_w_1,
+ .bs_w_2_s = generic_bs_w_2,
+ .bs_w_4_s = generic_bs_w_4,
+ .bs_w_8_s = generic_bs_w_8,
+
+ /* write multiple stream */
+ .bs_wm_1_s = generic_bs_wm_1,
+ .bs_wm_2_s = generic_bs_wm_2,
+ .bs_wm_4_s = generic_bs_wm_4,
+ .bs_wm_8_s = generic_bs_wm_8,
+
+ /* write region stream */
+ .bs_wr_1_s = generic_bs_wr_1,
+ .bs_wr_2_s = generic_bs_wr_2,
+ .bs_wr_4_s = generic_bs_wr_4,
+ .bs_wr_8_s = generic_bs_wr_8,
+};
+
+/* generic bus_space tag */
+bus_space_tag_t mips_bus_space_fdt = &fdt_space;
+
+static int
+fdt_bs_map(void *t __unused, bus_addr_t addr, bus_size_t size __unused,
+ int flags __unused, bus_space_handle_t *bshp)
+{
+
+ *bshp = MIPS_PHYS_TO_DIRECT_UNCACHED(addr);
+ return (0);
+}
Property changes on: trunk/sys/mips/mips/bus_space_fdt.c
___________________________________________________________________
Added: svn:eol-style
## -0,0 +1 ##
+native
\ No newline at end of property
Added: svn:keywords
## -0,0 +1 ##
+MidnightBSD=%H
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+text/plain
\ No newline at end of property
Added: trunk/sys/mips/mips/bus_space_generic.c
===================================================================
--- trunk/sys/mips/mips/bus_space_generic.c (rev 0)
+++ trunk/sys/mips/mips/bus_space_generic.c 2018-05-26 21:55:02 UTC (rev 9987)
@@ -0,0 +1,750 @@
+/* $MidnightBSD$ */
+/* $NetBSD: bus.h,v 1.12 1997/10/01 08:25:15 fvdl Exp $ */
+/*-
+ * $Id: bus.h,v 1.6 2007/08/09 11:23:32 katta Exp $
+ *
+ * Copyright (c) 1996, 1997 The NetBSD Foundation, Inc.
+ * All rights reserved.
+ *
+ * This code is derived from software contributed to The NetBSD Foundation
+ * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility,
+ * NASA Ames Research Center.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
+ * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/*
+ * Copyright (c) 1996 Charles M. Hannum. All rights reserved.
+ * Copyright (c) 1996 Christopher G. Demetriou. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * 3. All advertising materials mentioning features or use of this software
+ * must display the following acknowledgement:
+ * This product includes software developed by Christopher G. Demetriou
+ * for the NetBSD Project.
+ * 4. The name of the author may not be used to endorse or promote products
+ * derived from this software without specific prior written permission
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+ * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+ * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * from: src/sys/alpha/include/bus.h,v 1.5 1999/08/28 00:38:40 peter
+ * $FreeBSD: stable/10/sys/mips/mips/bus_space_generic.c 263687 2014-03-24 13:48:04Z emaste $
+ */
+#include <sys/cdefs.h>
+__FBSDID("$FreeBSD: stable/10/sys/mips/mips/bus_space_generic.c 263687 2014-03-24 13:48:04Z emaste $");
+
+#include <sys/param.h>
+#include <sys/systm.h>
+#include <sys/bus.h>
+#include <sys/kernel.h>
+#include <sys/malloc.h>
+#include <sys/ktr.h>
+
+#include <vm/vm.h>
+#include <vm/pmap.h>
+#include <vm/vm_kern.h>
+#include <vm/vm_extern.h>
+
+#include <machine/bus.h>
+#include <machine/cache.h>
+
+static struct bus_space generic_space = {
+ /* cookie */
+ .bs_cookie = (void *) 0,
+
+ /* mapping/unmapping */
+ .bs_map = generic_bs_map,
+ .bs_unmap = generic_bs_unmap,
+ .bs_subregion = generic_bs_subregion,
+
+ /* allocation/deallocation */
+ .bs_alloc = generic_bs_alloc,
+ .bs_free = generic_bs_free,
+
+ /* barrier */
+ .bs_barrier = generic_bs_barrier,
+
+ /* read (single) */
+ .bs_r_1 = generic_bs_r_1,
+ .bs_r_2 = generic_bs_r_2,
+ .bs_r_4 = generic_bs_r_4,
+ .bs_r_8 = generic_bs_r_8,
+
+ /* read multiple */
+ .bs_rm_1 = generic_bs_rm_1,
+ .bs_rm_2 = generic_bs_rm_2,
+ .bs_rm_4 = generic_bs_rm_4,
+ .bs_rm_8 = generic_bs_rm_8,
+
+ /* read region */
+ .bs_rr_1 = generic_bs_rr_1,
+ .bs_rr_2 = generic_bs_rr_2,
+ .bs_rr_4 = generic_bs_rr_4,
+ .bs_rr_8 = generic_bs_rr_8,
+
+ /* write (single) */
+ .bs_w_1 = generic_bs_w_1,
+ .bs_w_2 = generic_bs_w_2,
+ .bs_w_4 = generic_bs_w_4,
+ .bs_w_8 = generic_bs_w_8,
+
+ /* write multiple */
+ .bs_wm_1 = generic_bs_wm_1,
+ .bs_wm_2 = generic_bs_wm_2,
+ .bs_wm_4 = generic_bs_wm_4,
+ .bs_wm_8 = generic_bs_wm_8,
+
+ /* write region */
+ .bs_wr_1 = generic_bs_wr_1,
+ .bs_wr_2 = generic_bs_wr_2,
+ .bs_wr_4 = generic_bs_wr_4,
+ .bs_wr_8 = generic_bs_wr_8,
+
+ /* set multiple */
+ .bs_sm_1 = generic_bs_sm_1,
+ .bs_sm_2 = generic_bs_sm_2,
+ .bs_sm_4 = generic_bs_sm_4,
+ .bs_sm_8 = generic_bs_sm_8,
+
+ /* set region */
+ .bs_sr_1 = generic_bs_sr_1,
+ .bs_sr_2 = generic_bs_sr_2,
+ .bs_sr_4 = generic_bs_sr_4,
+ .bs_sr_8 = generic_bs_sr_8,
+
+ /* copy */
+ .bs_c_1 = generic_bs_c_1,
+ .bs_c_2 = generic_bs_c_2,
+ .bs_c_4 = generic_bs_c_4,
+ .bs_c_8 = generic_bs_c_8,
+
+ /* read (single) stream */
+ .bs_r_1_s = generic_bs_r_1,
+ .bs_r_2_s = generic_bs_r_2,
+ .bs_r_4_s = generic_bs_r_4,
+ .bs_r_8_s = generic_bs_r_8,
+
+ /* read multiple stream */
+ .bs_rm_1_s = generic_bs_rm_1,
+ .bs_rm_2_s = generic_bs_rm_2,
+ .bs_rm_4_s = generic_bs_rm_4,
+ .bs_rm_8_s = generic_bs_rm_8,
+
+ /* read region stream */
+ .bs_rr_1_s = generic_bs_rr_1,
+ .bs_rr_2_s = generic_bs_rr_2,
+ .bs_rr_4_s = generic_bs_rr_4,
+ .bs_rr_8_s = generic_bs_rr_8,
+
+ /* write (single) stream */
+ .bs_w_1_s = generic_bs_w_1,
+ .bs_w_2_s = generic_bs_w_2,
+ .bs_w_4_s = generic_bs_w_4,
+ .bs_w_8_s = generic_bs_w_8,
+
+ /* write multiple stream */
+ .bs_wm_1_s = generic_bs_wm_1,
+ .bs_wm_2_s = generic_bs_wm_2,
+ .bs_wm_4_s = generic_bs_wm_4,
+ .bs_wm_8_s = generic_bs_wm_8,
+
+ /* write region stream */
+ .bs_wr_1_s = generic_bs_wr_1,
+ .bs_wr_2_s = generic_bs_wr_2,
+ .bs_wr_4_s = generic_bs_wr_4,
+ .bs_wr_8_s = generic_bs_wr_8,
+};
+
+/* Ultra-gross kludge */
+#if defined(CPU_CNMIPS) && (defined(__mips_n32) || defined(__mips_o32))
+#include <contrib/octeon-sdk/cvmx.h>
+#define rd8(a) cvmx_read64_uint8(a)
+#define rd16(a) cvmx_read64_uint16(a)
+#define rd32(a) cvmx_read64_uint32(a)
+#define rd64(a) cvmx_read64_uint64(a)
+#define wr8(a, v) cvmx_write64_uint8(a, v)
+#define wr16(a, v) cvmx_write64_uint16(a, v)
+#define wr32(a, v) cvmx_write64_uint32(a, v)
+#define wr64(a, v) cvmx_write64_uint64(a, v)
+#elif defined(CPU_SB1) && _BYTE_ORDER == _BIG_ENDIAN
+#include <mips/sibyte/sb_bus_space.h>
+#define rd8(a) sb_big_endian_read8(a)
+#define rd16(a) sb_big_endian_read16(a)
+#define rd32(a) sb_big_endian_read32(a)
+#define wr8(a, v) sb_big_endian_write8(a, v)
+#define wr16(a, v) sb_big_endian_write16(a, v)
+#define wr32(a, v) sb_big_endian_write32(a, v)
+#else
+#define rd8(a) readb(a)
+#define rd16(a) readw(a)
+#define rd32(a) readl(a)
+#ifdef readq
+#define rd64(a) readq((a))
+#endif
+#define wr8(a, v) writeb(a, v)
+#define wr16(a, v) writew(a, v)
+#define wr32(a, v) writel(a, v)
+#ifdef writeq
+#define wr64(a, v) writeq(a, v)
+#endif
+#endif
+
+/* generic bus_space tag */
+bus_space_tag_t mips_bus_space_generic = &generic_space;
+
+int
+generic_bs_map(void *t __unused, bus_addr_t addr,
+ bus_size_t size __unused, int flags __unused,
+ bus_space_handle_t *bshp)
+{
+
+ *bshp = addr;
+ return (0);
+}
+
+void
+generic_bs_unmap(void *t __unused, bus_space_handle_t bh __unused,
+ bus_size_t size __unused)
+{
+
+ /* Do nothing */
+}
+
+int
+generic_bs_subregion(void *t __unused, bus_space_handle_t handle,
+ bus_size_t offset, bus_size_t size __unused,
+ bus_space_handle_t *bshp)
+{
+
+ *bshp = handle + offset;
+ return (0);
+}
+
+int
+generic_bs_alloc(void *t, bus_addr_t rstart, bus_addr_t rend,
+ bus_size_t size, bus_size_t alignment, bus_size_t boundary, int flags,
+ bus_addr_t *bpap, bus_space_handle_t *bshp)
+{
+
+ panic("%s: not implemented", __func__);
+}
+
+void
+generic_bs_free(void *t, bus_space_handle_t bsh, bus_size_t size)
+{
+
+ panic("%s: not implemented", __func__);
+}
+
+uint8_t
+generic_bs_r_1(void *t, bus_space_handle_t handle,
+ bus_size_t offset)
+{
+
+ return (rd8(handle + offset));
+}
+
+uint16_t
+generic_bs_r_2(void *t, bus_space_handle_t handle,
+ bus_size_t offset)
+{
+
+ return (rd16(handle + offset));
+}
+
+uint32_t
+generic_bs_r_4(void *t, bus_space_handle_t handle,
+ bus_size_t offset)
+{
+
+ return (rd32(handle + offset));
+}
+
+uint64_t
+generic_bs_r_8(void *t, bus_space_handle_t handle, bus_size_t offset)
+{
+
+#ifdef rd64
+ return(rd64(handle + offset));
+#else
+ panic("%s: not implemented", __func__);
+#endif
+}
+
+void
+generic_bs_rm_1(void *t, bus_space_handle_t bsh,
+ bus_size_t offset, uint8_t *addr, size_t count)
+{
+
+ while (count--)
+ *addr++ = rd8(bsh + offset);
+}
+
+void
+generic_bs_rm_2(void *t, bus_space_handle_t bsh,
+ bus_size_t offset, uint16_t *addr, size_t count)
+{
+ bus_addr_t baddr = bsh + offset;
+
+ while (count--)
+ *addr++ = rd16(baddr);
+}
+
+void
+generic_bs_rm_4(void *t, bus_space_handle_t bsh,
+ bus_size_t offset, uint32_t *addr, size_t count)
+{
+ bus_addr_t baddr = bsh + offset;
+
+ while (count--)
+ *addr++ = rd32(baddr);
+}
+
+void
+generic_bs_rm_8(void *t, bus_space_handle_t bsh, bus_size_t offset,
+ uint64_t *addr, size_t count)
+{
+#ifdef rd64
+ bus_addr_t baddr = bsh + offset;
+
+ while (count--)
+ *addr++ = rd64(baddr);
+#else
+ panic("%s: not implemented", __func__);
+#endif
+}
+
+/*
+ * Read `count' 1, 2, 4, or 8 byte quantities from bus space
+ * described by tag/handle and starting at `offset' and copy into
+ * buffer provided.
+ */
+void
+generic_bs_rr_1(void *t, bus_space_handle_t bsh,
+ bus_size_t offset, uint8_t *addr, size_t count)
+{
+ bus_addr_t baddr = bsh + offset;
+
+ while (count--) {
+ *addr++ = rd8(baddr);
+ baddr += 1;
+ }
+}
+
+void
+generic_bs_rr_2(void *t, bus_space_handle_t bsh,
+ bus_size_t offset, uint16_t *addr, size_t count)
+{
+ bus_addr_t baddr = bsh + offset;
+
+ while (count--) {
+ *addr++ = rd16(baddr);
+ baddr += 2;
+ }
+}
+
+void
+generic_bs_rr_4(void *t, bus_space_handle_t bsh,
+ bus_size_t offset, uint32_t *addr, size_t count)
+{
+ bus_addr_t baddr = bsh + offset;
+
+ while (count--) {
+ *addr++ = rd32(baddr);
+ baddr += 4;
+ }
+}
+
+void
+generic_bs_rr_8(void *t, bus_space_handle_t bsh, bus_size_t offset,
+ uint64_t *addr, size_t count)
+{
+#ifdef rd64
+ bus_addr_t baddr = bsh + offset;
+
+ while (count--) {
+ *addr++ = rd64(baddr);
+ baddr += 8;
+ }
+#else
+ panic("%s: not implemented", __func__);
+#endif
+}
+
+/*
+ * Write the 1, 2, 4, or 8 byte value `value' to bus space
+ * described by tag/handle/offset.
+ */
+void
+generic_bs_w_1(void *t, bus_space_handle_t bsh,
+ bus_size_t offset, uint8_t value)
+{
+
+ wr8(bsh + offset, value);
+}
+
+void
+generic_bs_w_2(void *t, bus_space_handle_t bsh,
+ bus_size_t offset, uint16_t value)
+{
+
+ wr16(bsh + offset, value);
+}
+
+void
+generic_bs_w_4(void *t, bus_space_handle_t bsh,
+ bus_size_t offset, uint32_t value)
+{
+
+ wr32(bsh + offset, value);
+}
+
+void
+generic_bs_w_8(void *t, bus_space_handle_t bsh, bus_size_t offset,
+ uint64_t value)
+{
+
+#ifdef wr64
+ wr64(bsh + offset, value);
+#else
+ panic("%s: not implemented", __func__);
+#endif
+}
+
+/*
+ * Write `count' 1, 2, 4, or 8 byte quantities from the buffer
+ * provided to bus space described by tag/handle/offset.
+ */
+void
+generic_bs_wm_1(void *t, bus_space_handle_t bsh,
+ bus_size_t offset, const uint8_t *addr, size_t count)
+{
+ bus_addr_t baddr = bsh + offset;
+
+ while (count--)
+ wr8(baddr, *addr++);
+}
+
+void
+generic_bs_wm_2(void *t, bus_space_handle_t bsh,
+ bus_size_t offset, const uint16_t *addr, size_t count)
+{
+ bus_addr_t baddr = bsh + offset;
+
+ while (count--)
+ wr16(baddr, *addr++);
+}
+
+void
+generic_bs_wm_4(void *t, bus_space_handle_t bsh,
+ bus_size_t offset, const uint32_t *addr, size_t count)
+{
+ bus_addr_t baddr = bsh + offset;
+
+ while (count--)
+ wr32(baddr, *addr++);
+}
+
+void
+generic_bs_wm_8(void *t, bus_space_handle_t bsh, bus_size_t offset,
+ const uint64_t *addr, size_t count)
+{
+#ifdef wr64
+ bus_addr_t baddr = bsh + offset;
+
+ while (count--)
+ wr64(baddr, *addr++);
+#else
+ panic("%s: not implemented", __func__);
+#endif
+}
+
+/*
+ * Write `count' 1, 2, 4, or 8 byte quantities from the buffer provided
+ * to bus space described by tag/handle starting at `offset'.
+ */
+void
+generic_bs_wr_1(void *t, bus_space_handle_t bsh,
+ bus_size_t offset, const uint8_t *addr, size_t count)
+{
+ bus_addr_t baddr = bsh + offset;
+
+ while (count--) {
+ wr8(baddr, *addr++);
+ baddr += 1;
+ }
+}
+
+void
+generic_bs_wr_2(void *t, bus_space_handle_t bsh,
+ bus_size_t offset, const uint16_t *addr, size_t count)
+{
+ bus_addr_t baddr = bsh + offset;
+
+ while (count--) {
+ wr16(baddr, *addr++);
+ baddr += 2;
+ }
+}
+
+void
+generic_bs_wr_4(void *t, bus_space_handle_t bsh,
+ bus_size_t offset, const uint32_t *addr, size_t count)
+{
+ bus_addr_t baddr = bsh + offset;
+
+ while (count--) {
+ wr32(baddr, *addr++);
+ baddr += 4;
+ }
+}
+
+void
+generic_bs_wr_8(void *t, bus_space_handle_t bsh, bus_size_t offset,
+ const uint64_t *addr, size_t count)
+{
+#ifdef wr64
+ bus_addr_t baddr = bsh + offset;
+
+ while (count--) {
+ wr64(baddr, *addr++);
+ baddr += 8;
+ }
+#else
+ panic("%s: not implemented", __func__);
+#endif
+}
+
+/*
+ * Write the 1, 2, 4, or 8 byte value `val' to bus space described
+ * by tag/handle/offset `count' times.
+ */
+void
+generic_bs_sm_1(void *t, bus_space_handle_t bsh,
+ bus_size_t offset, uint8_t value, size_t count)
+{
+ bus_addr_t addr = bsh + offset;
+
+ while (count--)
+ wr8(addr, value);
+}
+
+void
+generic_bs_sm_2(void *t, bus_space_handle_t bsh,
+ bus_size_t offset, uint16_t value, size_t count)
+{
+ bus_addr_t addr = bsh + offset;
+
+ while (count--)
+ wr16(addr, value);
+}
+
+void
+generic_bs_sm_4(void *t, bus_space_handle_t bsh,
+ bus_size_t offset, uint32_t value, size_t count)
+{
+ bus_addr_t addr = bsh + offset;
+
+ while (count--)
+ wr32(addr, value);
+}
+
+void
+generic_bs_sm_8(void *t, bus_space_handle_t bsh, bus_size_t offset,
+ uint64_t value, size_t count)
+{
+#ifdef wr64
+ bus_addr_t addr = bsh + offset;
+
+ while (count--)
+ wr64(addr, value);
+#else
+ panic("%s: not implemented", __func__);
+#endif
+}
+
+/*
+ * Write `count' 1, 2, 4, or 8 byte value `val' to bus space described
+ * by tag/handle starting at `offset'.
+ */
+void
+generic_bs_sr_1(void *t, bus_space_handle_t bsh,
+ bus_size_t offset, uint8_t value, size_t count)
+{
+ bus_addr_t addr = bsh + offset;
+
+ for (; count != 0; count--, addr++)
+ wr8(addr, value);
+}
+
+void
+generic_bs_sr_2(void *t, bus_space_handle_t bsh,
+ bus_size_t offset, uint16_t value, size_t count)
+{
+ bus_addr_t addr = bsh + offset;
+
+ for (; count != 0; count--, addr += 2)
+ wr16(addr, value);
+}
+
+void
+generic_bs_sr_4(void *t, bus_space_handle_t bsh,
+ bus_size_t offset, uint32_t value, size_t count)
+{
+ bus_addr_t addr = bsh + offset;
+
+ for (; count != 0; count--, addr += 4)
+ wr32(addr, value);
+}
+
+void
+generic_bs_sr_8(void *t, bus_space_handle_t bsh, bus_size_t offset,
+ uint64_t value, size_t count)
+{
+#ifdef wr64
+ bus_addr_t addr = bsh + offset;
+
+ for (; count != 0; count--, addr += 8)
+ wr64(addr, value);
+#else
+ panic("%s: not implemented", __func__);
+#endif
+}
+
+/*
+ * Copy `count' 1, 2, 4, or 8 byte values from bus space starting
+ * at tag/bsh1/off1 to bus space starting at tag/bsh2/off2.
+ */
+void
+generic_bs_c_1(void *t, bus_space_handle_t bsh1,
+ bus_size_t off1, bus_space_handle_t bsh2,
+ bus_size_t off2, size_t count)
+{
+ bus_addr_t addr1 = bsh1 + off1;
+ bus_addr_t addr2 = bsh2 + off2;
+
+ if (addr1 >= addr2) {
+ /* src after dest: copy forward */
+ for (; count != 0; count--, addr1++, addr2++)
+ wr8(addr2, rd8(addr1));
+ } else {
+ /* dest after src: copy backwards */
+ for (addr1 += (count - 1), addr2 += (count - 1);
+ count != 0; count--, addr1--, addr2--)
+ wr8(addr2, rd8(addr1));
+ }
+}
+
+void
+generic_bs_c_2(void *t, bus_space_handle_t bsh1,
+ bus_size_t off1, bus_space_handle_t bsh2,
+ bus_size_t off2, size_t count)
+{
+ bus_addr_t addr1 = bsh1 + off1;
+ bus_addr_t addr2 = bsh2 + off2;
+
+ if (addr1 >= addr2) {
+ /* src after dest: copy forward */
+ for (; count != 0; count--, addr1 += 2, addr2 += 2)
+ wr16(addr2, rd16(addr1));
+ } else {
+ /* dest after src: copy backwards */
+ for (addr1 += 2 * (count - 1), addr2 += 2 * (count - 1);
+ count != 0; count--, addr1 -= 2, addr2 -= 2)
+ wr16(addr2, rd16(addr1));
+ }
+}
+
+void
+generic_bs_c_4(void *t, bus_space_handle_t bsh1,
+ bus_size_t off1, bus_space_handle_t bsh2,
+ bus_size_t off2, size_t count)
+{
+ bus_addr_t addr1 = bsh1 + off1;
+ bus_addr_t addr2 = bsh2 + off2;
+
+ if (addr1 >= addr2) {
+ /* src after dest: copy forward */
+ for (; count != 0; count--, addr1 += 4, addr2 += 4)
+ wr32(addr2, rd32(addr1));
+ } else {
+ /* dest after src: copy backwards */
+ for (addr1 += 4 * (count - 1), addr2 += 4 * (count - 1);
+ count != 0; count--, addr1 -= 4, addr2 -= 4)
+ wr32(addr2, rd32(addr1));
+ }
+}
+
+void
+generic_bs_c_8(void *t, bus_space_handle_t bsh1, bus_size_t off1,
+ bus_space_handle_t bsh2, bus_size_t off2, size_t count)
+{
+#if defined(rd64) && defined(wr64)
+ bus_addr_t addr1 = bsh1 + off1;
+ bus_addr_t addr2 = bsh2 + off2;
+
+ if (addr1 >= addr2) {
+ /* src after dest: copy forward */
+ for (; count != 0; count--, addr1 += 8, addr2 += 8)
+ wr64(addr2, rd64(addr1));
+ } else {
+ /* dest after src: copy backwards */
+ for (addr1 += 8 * (count - 1), addr2 += 8 * (count - 1);
+ count != 0; count--, addr1 -= 8, addr2 -= 8)
+ wr64(addr2, rd64(addr1));
+ }
+#else
+ panic("%s: not implemented", __func__);
+#endif
+}
+
+void
+generic_bs_barrier(void *t __unused,
+ bus_space_handle_t bsh __unused,
+ bus_size_t offset __unused, bus_size_t len __unused,
+ int flags)
+{
+#if 0
+ if (flags & BUS_SPACE_BARRIER_WRITE)
+ mips_dcache_wbinv_all();
+#endif
+ if (flags & BUS_SPACE_BARRIER_READ)
+ rmb();
+ if (flags & BUS_SPACE_BARRIER_WRITE)
+ wmb();
+}
Property changes on: trunk/sys/mips/mips/bus_space_generic.c
___________________________________________________________________
Added: svn:eol-style
## -0,0 +1 ##
+native
\ No newline at end of property
Added: svn:keywords
## -0,0 +1 ##
+MidnightBSD=%H
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+text/plain
\ No newline at end of property
Added: trunk/sys/mips/mips/busdma_machdep.c
===================================================================
--- trunk/sys/mips/mips/busdma_machdep.c (rev 0)
+++ trunk/sys/mips/mips/busdma_machdep.c 2018-05-26 21:55:02 UTC (rev 9987)
@@ -0,0 +1,1427 @@
+/* $MidnightBSD$ */
+/*-
+ * Copyright (c) 2006 Oleksandr Tymoshenko
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions, and the following disclaimer,
+ * without modification, immediately at the beginning of the file.
+ * 2. The name of the author may not be used to endorse or promote products
+ * derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ * From i386/busdma_machdep.c,v 1.26 2002/04/19 22:58:09 alfred
+ */
+
+#include <sys/cdefs.h>
+__FBSDID("$FreeBSD: stable/10/sys/mips/mips/busdma_machdep.c 282506 2015-05-05 19:47:17Z hselasky $");
+
+/*
+ * MIPS bus dma support routines
+ */
+
+#include <sys/param.h>
+#include <sys/systm.h>
+#include <sys/malloc.h>
+#include <sys/bus.h>
+#include <sys/interrupt.h>
+#include <sys/lock.h>
+#include <sys/proc.h>
+#include <sys/memdesc.h>
+#include <sys/mutex.h>
+#include <sys/ktr.h>
+#include <sys/kernel.h>
+#include <sys/sysctl.h>
+#include <sys/uio.h>
+
+#include <vm/vm.h>
+#include <vm/vm_page.h>
+#include <vm/vm_map.h>
+
+#include <machine/atomic.h>
+#include <machine/bus.h>
+#include <machine/cache.h>
+#include <machine/cpufunc.h>
+#include <machine/cpuinfo.h>
+#include <machine/md_var.h>
+
+#define MAX_BPAGES 64
+#define BUS_DMA_COULD_BOUNCE BUS_DMA_BUS3
+#define BUS_DMA_MIN_ALLOC_COMP BUS_DMA_BUS4
+
+struct bounce_zone;
+
+struct bus_dma_tag {
+ bus_dma_tag_t parent;
+ bus_size_t alignment;
+ bus_addr_t boundary;
+ bus_addr_t lowaddr;
+ bus_addr_t highaddr;
+ bus_dma_filter_t *filter;
+ void *filterarg;
+ bus_size_t maxsize;
+ u_int nsegments;
+ bus_size_t maxsegsz;
+ int flags;
+ int ref_count;
+ int map_count;
+ bus_dma_lock_t *lockfunc;
+ void *lockfuncarg;
+ bus_dma_segment_t *segments;
+ struct bounce_zone *bounce_zone;
+};
+
+struct bounce_page {
+ vm_offset_t vaddr; /* kva of bounce buffer */
+ vm_offset_t vaddr_nocache; /* kva of bounce buffer uncached */
+ bus_addr_t busaddr; /* Physical address */
+ vm_offset_t datavaddr; /* kva of client data */
+ bus_addr_t dataaddr; /* client physical address */
+ bus_size_t datacount; /* client data count */
+ STAILQ_ENTRY(bounce_page) links;
+};
+
+struct sync_list {
+ vm_offset_t vaddr; /* kva of bounce buffer */
+ bus_addr_t busaddr; /* Physical address */
+ bus_size_t datacount; /* client data count */
+};
+
+int busdma_swi_pending;
+
+struct bounce_zone {
+ STAILQ_ENTRY(bounce_zone) links;
+ STAILQ_HEAD(bp_list, bounce_page) bounce_page_list;
+ int total_bpages;
+ int free_bpages;
+ int reserved_bpages;
+ int active_bpages;
+ int total_bounced;
+ int total_deferred;
+ int map_count;
+ bus_size_t alignment;
+ bus_addr_t lowaddr;
+ char zoneid[8];
+ char lowaddrid[20];
+ struct sysctl_ctx_list sysctl_tree;
+ struct sysctl_oid *sysctl_tree_top;
+};
+
+static struct mtx bounce_lock;
+static int total_bpages;
+static int busdma_zonecount;
+static STAILQ_HEAD(, bounce_zone) bounce_zone_list;
+
+static SYSCTL_NODE(_hw, OID_AUTO, busdma, CTLFLAG_RD, 0, "Busdma parameters");
+SYSCTL_INT(_hw_busdma, OID_AUTO, total_bpages, CTLFLAG_RD, &total_bpages, 0,
+ "Total bounce pages");
+
+#define DMAMAP_UNCACHEABLE 0x8
+#define DMAMAP_ALLOCATED 0x10
+#define DMAMAP_MALLOCUSED 0x20
+
+struct bus_dmamap {
+ struct bp_list bpages;
+ int pagesneeded;
+ int pagesreserved;
+ bus_dma_tag_t dmat;
+ struct memdesc mem;
+ int flags;
+ void *origbuffer;
+ void *allocbuffer;
+ TAILQ_ENTRY(bus_dmamap) freelist;
+ STAILQ_ENTRY(bus_dmamap) links;
+ bus_dmamap_callback_t *callback;
+ void *callback_arg;
+ int sync_count;
+ struct sync_list *slist;
+};
+
+static STAILQ_HEAD(, bus_dmamap) bounce_map_waitinglist;
+static STAILQ_HEAD(, bus_dmamap) bounce_map_callbacklist;
+
+static TAILQ_HEAD(,bus_dmamap) dmamap_freelist =
+ TAILQ_HEAD_INITIALIZER(dmamap_freelist);
+
+#define BUSDMA_STATIC_MAPS 128
+static struct bus_dmamap map_pool[BUSDMA_STATIC_MAPS];
+
+static struct mtx busdma_mtx;
+
+MTX_SYSINIT(busdma_mtx, &busdma_mtx, "busdma lock", MTX_DEF);
+
+static void init_bounce_pages(void *dummy);
+static int alloc_bounce_zone(bus_dma_tag_t dmat);
+static int alloc_bounce_pages(bus_dma_tag_t dmat, u_int numpages);
+static int reserve_bounce_pages(bus_dma_tag_t dmat, bus_dmamap_t map,
+ int commit);
+static bus_addr_t add_bounce_page(bus_dma_tag_t dmat, bus_dmamap_t map,
+ vm_offset_t vaddr, bus_addr_t addr,
+ bus_size_t size);
+static void free_bounce_page(bus_dma_tag_t dmat, struct bounce_page *bpage);
+
+/* Default tag, as most drivers provide no parent tag. */
+bus_dma_tag_t mips_root_dma_tag;
+
+/*
+ * Return true if a match is made.
+ *
+ * To find a match walk the chain of bus_dma_tag_t's looking for 'paddr'.
+ *
+ * If paddr is within the bounds of the dma tag then call the filter callback
+ * to check for a match, if there is no filter callback then assume a match.
+ */
+static int
+run_filter(bus_dma_tag_t dmat, bus_addr_t paddr)
+{
+ int retval;
+
+ retval = 0;
+
+ do {
+ if (((paddr > dmat->lowaddr && paddr <= dmat->highaddr)
+ || ((paddr & (dmat->alignment - 1)) != 0))
+ && (dmat->filter == NULL
+ || (*dmat->filter)(dmat->filterarg, paddr) != 0))
+ retval = 1;
+
+ dmat = dmat->parent;
+ } while (retval == 0 && dmat != NULL);
+ return (retval);
+}
+
+static void
+mips_dmamap_freelist_init(void *dummy)
+{
+ int i;
+
+ for (i = 0; i < BUSDMA_STATIC_MAPS; i++)
+ TAILQ_INSERT_HEAD(&dmamap_freelist, &map_pool[i], freelist);
+}
+
+SYSINIT(busdma, SI_SUB_VM, SI_ORDER_ANY, mips_dmamap_freelist_init, NULL);
+
+/*
+ * Check to see if the specified page is in an allowed DMA range.
+ */
+
+static __inline int
+_bus_dma_can_bounce(vm_offset_t lowaddr, vm_offset_t highaddr)
+{
+ int i;
+ for (i = 0; phys_avail[i] && phys_avail[i + 1]; i += 2) {
+ if ((lowaddr >= phys_avail[i] && lowaddr <= phys_avail[i + 1])
+ || (lowaddr < phys_avail[i] &&
+ highaddr > phys_avail[i]))
+ return (1);
+ }
+ return (0);
+}
+
+/*
+ * Convenience function for manipulating driver locks from busdma (during
+ * busdma_swi, for example). Drivers that don't provide their own locks
+ * should specify &Giant to dmat->lockfuncarg. Drivers that use their own
+ * non-mutex locking scheme don't have to use this at all.
+ */
+void
+busdma_lock_mutex(void *arg, bus_dma_lock_op_t op)
+{
+ struct mtx *dmtx;
+
+ dmtx = (struct mtx *)arg;
+ switch (op) {
+ case BUS_DMA_LOCK:
+ mtx_lock(dmtx);
+ break;
+ case BUS_DMA_UNLOCK:
+ mtx_unlock(dmtx);
+ break;
+ default:
+ panic("Unknown operation 0x%x for busdma_lock_mutex!", op);
+ }
+}
+
+/*
+ * dflt_lock should never get called. It gets put into the dma tag when
+ * lockfunc == NULL, which is only valid if the maps that are associated
+ * with the tag are meant to never be defered.
+ * XXX Should have a way to identify which driver is responsible here.
+ */
+static void
+dflt_lock(void *arg, bus_dma_lock_op_t op)
+{
+#ifdef INVARIANTS
+ panic("driver error: busdma dflt_lock called");
+#else
+ printf("DRIVER_ERROR: busdma dflt_lock called\n");
+#endif
+}
+
+static __inline bus_dmamap_t
+_busdma_alloc_dmamap(bus_dma_tag_t dmat)
+{
+ struct sync_list *slist;
+ bus_dmamap_t map;
+
+ slist = malloc(sizeof(*slist) * dmat->nsegments, M_DEVBUF, M_NOWAIT);
+ if (slist == NULL)
+ return (NULL);
+ mtx_lock(&busdma_mtx);
+ map = TAILQ_FIRST(&dmamap_freelist);
+ if (map)
+ TAILQ_REMOVE(&dmamap_freelist, map, freelist);
+ mtx_unlock(&busdma_mtx);
+ if (!map) {
+ map = malloc(sizeof(*map), M_DEVBUF, M_NOWAIT | M_ZERO);
+ if (map)
+ map->flags = DMAMAP_ALLOCATED;
+ } else
+ map->flags = 0;
+ if (map != NULL) {
+ STAILQ_INIT(&map->bpages);
+ map->slist = slist;
+ } else
+ free(slist, M_DEVBUF);
+ return (map);
+}
+
+static __inline void
+_busdma_free_dmamap(bus_dmamap_t map)
+{
+ free(map->slist, M_DEVBUF);
+ if (map->flags & DMAMAP_ALLOCATED)
+ free(map, M_DEVBUF);
+ else {
+ mtx_lock(&busdma_mtx);
+ TAILQ_INSERT_HEAD(&dmamap_freelist, map, freelist);
+ mtx_unlock(&busdma_mtx);
+ }
+}
+
+/*
+ * Allocate a device specific dma_tag.
+ */
+#define SEG_NB 1024
+
+int
+bus_dma_tag_create(bus_dma_tag_t parent, bus_size_t alignment,
+ bus_addr_t boundary, bus_addr_t lowaddr,
+ bus_addr_t highaddr, bus_dma_filter_t *filter,
+ void *filterarg, bus_size_t maxsize, int nsegments,
+ bus_size_t maxsegsz, int flags, bus_dma_lock_t *lockfunc,
+ void *lockfuncarg, bus_dma_tag_t *dmat)
+{
+ bus_dma_tag_t newtag;
+ int error = 0;
+ /* Return a NULL tag on failure */
+ *dmat = NULL;
+ if (!parent)
+ parent = mips_root_dma_tag;
+
+ newtag = (bus_dma_tag_t)malloc(sizeof(*newtag), M_DEVBUF, M_NOWAIT);
+ if (newtag == NULL) {
+ CTR4(KTR_BUSDMA, "%s returned tag %p tag flags 0x%x error %d",
+ __func__, newtag, 0, error);
+ return (ENOMEM);
+ }
+
+ newtag->parent = parent;
+ newtag->alignment = alignment;
+ newtag->boundary = boundary;
+ newtag->lowaddr = trunc_page((vm_offset_t)lowaddr) + (PAGE_SIZE - 1);
+ newtag->highaddr = trunc_page((vm_offset_t)highaddr) + (PAGE_SIZE - 1);
+ newtag->filter = filter;
+ newtag->filterarg = filterarg;
+ newtag->maxsize = maxsize;
+ newtag->nsegments = nsegments;
+ newtag->maxsegsz = maxsegsz;
+ newtag->flags = flags;
+ if (cpuinfo.cache_coherent_dma)
+ newtag->flags |= BUS_DMA_COHERENT;
+ newtag->ref_count = 1; /* Count ourself */
+ newtag->map_count = 0;
+ if (lockfunc != NULL) {
+ newtag->lockfunc = lockfunc;
+ newtag->lockfuncarg = lockfuncarg;
+ } else {
+ newtag->lockfunc = dflt_lock;
+ newtag->lockfuncarg = NULL;
+ }
+ newtag->segments = NULL;
+
+ /*
+ * Take into account any restrictions imposed by our parent tag
+ */
+ if (parent != NULL) {
+ newtag->lowaddr = MIN(parent->lowaddr, newtag->lowaddr);
+ newtag->highaddr = MAX(parent->highaddr, newtag->highaddr);
+ if (newtag->boundary == 0)
+ newtag->boundary = parent->boundary;
+ else if (parent->boundary != 0)
+ newtag->boundary =
+ MIN(parent->boundary, newtag->boundary);
+ if ((newtag->filter != NULL) ||
+ ((parent->flags & BUS_DMA_COULD_BOUNCE) != 0))
+ newtag->flags |= BUS_DMA_COULD_BOUNCE;
+ if (newtag->filter == NULL) {
+ /*
+ * Short circuit looking at our parent directly
+ * since we have encapsulated all of its information
+ */
+ newtag->filter = parent->filter;
+ newtag->filterarg = parent->filterarg;
+ newtag->parent = parent->parent;
+ }
+ if (newtag->parent != NULL)
+ atomic_add_int(&parent->ref_count, 1);
+ }
+ if (_bus_dma_can_bounce(newtag->lowaddr, newtag->highaddr)
+ || newtag->alignment > 1)
+ newtag->flags |= BUS_DMA_COULD_BOUNCE;
+
+ if (((newtag->flags & BUS_DMA_COULD_BOUNCE) != 0) &&
+ (flags & BUS_DMA_ALLOCNOW) != 0) {
+ struct bounce_zone *bz;
+
+ /* Must bounce */
+
+ if ((error = alloc_bounce_zone(newtag)) != 0) {
+ free(newtag, M_DEVBUF);
+ return (error);
+ }
+ bz = newtag->bounce_zone;
+
+ if (ptoa(bz->total_bpages) < maxsize) {
+ int pages;
+
+ pages = atop(maxsize) - bz->total_bpages;
+
+ /* Add pages to our bounce pool */
+ if (alloc_bounce_pages(newtag, pages) < pages)
+ error = ENOMEM;
+ }
+ /* Performed initial allocation */
+ newtag->flags |= BUS_DMA_MIN_ALLOC_COMP;
+ } else
+ newtag->bounce_zone = NULL;
+ if (error != 0)
+ free(newtag, M_DEVBUF);
+ else
+ *dmat = newtag;
+ CTR4(KTR_BUSDMA, "%s returned tag %p tag flags 0x%x error %d",
+ __func__, newtag, (newtag != NULL ? newtag->flags : 0), error);
+
+ return (error);
+}
+
+int
+bus_dma_tag_destroy(bus_dma_tag_t dmat)
+{
+#ifdef KTR
+ bus_dma_tag_t dmat_copy = dmat;
+#endif
+
+ if (dmat != NULL) {
+ if (dmat->map_count != 0)
+ return (EBUSY);
+
+ while (dmat != NULL) {
+ bus_dma_tag_t parent;
+
+ parent = dmat->parent;
+ atomic_subtract_int(&dmat->ref_count, 1);
+ if (dmat->ref_count == 0) {
+ if (dmat->segments != NULL)
+ free(dmat->segments, M_DEVBUF);
+ free(dmat, M_DEVBUF);
+ /*
+ * Last reference count, so
+ * release our reference
+ * count on our parent.
+ */
+ dmat = parent;
+ } else
+ dmat = NULL;
+ }
+ }
+ CTR2(KTR_BUSDMA, "%s tag %p", __func__, dmat_copy);
+
+ return (0);
+}
+
+#include <sys/kdb.h>
+/*
+ * Allocate a handle for mapping from kva/uva/physical
+ * address space into bus device space.
+ */
+int
+bus_dmamap_create(bus_dma_tag_t dmat, int flags, bus_dmamap_t *mapp)
+{
+ bus_dmamap_t newmap;
+ int error = 0;
+
+ if (dmat->segments == NULL) {
+ dmat->segments = (bus_dma_segment_t *)malloc(
+ sizeof(bus_dma_segment_t) * dmat->nsegments, M_DEVBUF,
+ M_NOWAIT);
+ if (dmat->segments == NULL) {
+ CTR3(KTR_BUSDMA, "%s: tag %p error %d",
+ __func__, dmat, ENOMEM);
+ return (ENOMEM);
+ }
+ }
+
+ newmap = _busdma_alloc_dmamap(dmat);
+ if (newmap == NULL) {
+ CTR3(KTR_BUSDMA, "%s: tag %p error %d", __func__, dmat, ENOMEM);
+ return (ENOMEM);
+ }
+ *mapp = newmap;
+ newmap->dmat = dmat;
+ newmap->allocbuffer = NULL;
+ newmap->sync_count = 0;
+ dmat->map_count++;
+
+ /*
+ * Bouncing might be required if the driver asks for an active
+ * exclusion region, a data alignment that is stricter than 1, and/or
+ * an active address boundary.
+ */
+ if (dmat->flags & BUS_DMA_COULD_BOUNCE) {
+
+ /* Must bounce */
+ struct bounce_zone *bz;
+ int maxpages;
+
+ if (dmat->bounce_zone == NULL) {
+ if ((error = alloc_bounce_zone(dmat)) != 0) {
+ _busdma_free_dmamap(newmap);
+ *mapp = NULL;
+ return (error);
+ }
+ }
+ bz = dmat->bounce_zone;
+
+ /* Initialize the new map */
+ STAILQ_INIT(&((*mapp)->bpages));
+
+ /*
+ * Attempt to add pages to our pool on a per-instance
+ * basis up to a sane limit.
+ */
+ maxpages = MAX_BPAGES;
+ if ((dmat->flags & BUS_DMA_MIN_ALLOC_COMP) == 0
+ || (bz->map_count > 0 && bz->total_bpages < maxpages)) {
+ int pages;
+
+ pages = MAX(atop(dmat->maxsize), 1);
+ pages = MIN(maxpages - bz->total_bpages, pages);
+ pages = MAX(pages, 1);
+ if (alloc_bounce_pages(dmat, pages) < pages)
+ error = ENOMEM;
+
+ if ((dmat->flags & BUS_DMA_MIN_ALLOC_COMP) == 0) {
+ if (error == 0)
+ dmat->flags |= BUS_DMA_MIN_ALLOC_COMP;
+ } else {
+ error = 0;
+ }
+ }
+ bz->map_count++;
+ }
+
+ CTR4(KTR_BUSDMA, "%s: tag %p tag flags 0x%x error %d",
+ __func__, dmat, dmat->flags, error);
+
+ return (0);
+}
+
+/*
+ * Destroy a handle for mapping from kva/uva/physical
+ * address space into bus device space.
+ */
+int
+bus_dmamap_destroy(bus_dma_tag_t dmat, bus_dmamap_t map)
+{
+
+ if (STAILQ_FIRST(&map->bpages) != NULL || map->sync_count != 0) {
+ CTR3(KTR_BUSDMA, "%s: tag %p error %d",
+ __func__, dmat, EBUSY);
+ return (EBUSY);
+ }
+ if (dmat->bounce_zone)
+ dmat->bounce_zone->map_count--;
+ dmat->map_count--;
+ _busdma_free_dmamap(map);
+ CTR2(KTR_BUSDMA, "%s: tag %p error 0", __func__, dmat);
+ return (0);
+}
+
+/*
+ * Allocate a piece of memory that can be efficiently mapped into
+ * bus device space based on the constraints lited in the dma tag.
+ * A dmamap to for use with dmamap_load is also allocated.
+ */
+int
+bus_dmamem_alloc(bus_dma_tag_t dmat, void** vaddr, int flags,
+ bus_dmamap_t *mapp)
+{
+ bus_dmamap_t newmap = NULL;
+
+ int mflags;
+
+ if (flags & BUS_DMA_NOWAIT)
+ mflags = M_NOWAIT;
+ else
+ mflags = M_WAITOK;
+ if (dmat->segments == NULL) {
+ dmat->segments = (bus_dma_segment_t *)malloc(
+ sizeof(bus_dma_segment_t) * dmat->nsegments, M_DEVBUF,
+ mflags);
+ if (dmat->segments == NULL) {
+ CTR4(KTR_BUSDMA, "%s: tag %p tag flags 0x%x error %d",
+ __func__, dmat, dmat->flags, ENOMEM);
+ return (ENOMEM);
+ }
+ }
+ if (flags & BUS_DMA_ZERO)
+ mflags |= M_ZERO;
+
+ newmap = _busdma_alloc_dmamap(dmat);
+ if (newmap == NULL) {
+ CTR4(KTR_BUSDMA, "%s: tag %p tag flags 0x%x error %d",
+ __func__, dmat, dmat->flags, ENOMEM);
+ return (ENOMEM);
+ }
+ dmat->map_count++;
+ *mapp = newmap;
+ newmap->dmat = dmat;
+ newmap->sync_count = 0;
+
+ /*
+ * If all the memory is coherent with DMA then we don't need to
+ * do anything special for a coherent mapping request.
+ */
+ if (dmat->flags & BUS_DMA_COHERENT)
+ flags &= ~BUS_DMA_COHERENT;
+
+ /*
+ * Allocate uncacheable memory if all else fails.
+ */
+ if (flags & BUS_DMA_COHERENT)
+ newmap->flags |= DMAMAP_UNCACHEABLE;
+
+ if (dmat->maxsize <= PAGE_SIZE &&
+ (dmat->alignment < dmat->maxsize) &&
+ !_bus_dma_can_bounce(dmat->lowaddr, dmat->highaddr) &&
+ !(newmap->flags & DMAMAP_UNCACHEABLE)) {
+ *vaddr = malloc(dmat->maxsize, M_DEVBUF, mflags);
+ newmap->flags |= DMAMAP_MALLOCUSED;
+ } else {
+ /*
+ * XXX Use Contigmalloc until it is merged into this facility
+ * and handles multi-seg allocations. Nobody is doing
+ * multi-seg allocations yet though.
+ */
+ *vaddr = contigmalloc(dmat->maxsize, M_DEVBUF, mflags,
+ 0ul, dmat->lowaddr, dmat->alignment? dmat->alignment : 1ul,
+ dmat->boundary);
+ }
+ if (*vaddr == NULL) {
+ if (newmap != NULL) {
+ _busdma_free_dmamap(newmap);
+ dmat->map_count--;
+ }
+ *mapp = NULL;
+ return (ENOMEM);
+ }
+
+ if (newmap->flags & DMAMAP_UNCACHEABLE) {
+ void *tmpaddr = (void *)*vaddr;
+
+ if (tmpaddr) {
+ tmpaddr = (void *)pmap_mapdev(vtophys(tmpaddr),
+ dmat->maxsize);
+ newmap->origbuffer = *vaddr;
+ newmap->allocbuffer = tmpaddr;
+ mips_dcache_wbinv_range((vm_offset_t)*vaddr,
+ dmat->maxsize);
+ *vaddr = tmpaddr;
+ } else
+ newmap->origbuffer = newmap->allocbuffer = NULL;
+ } else
+ newmap->origbuffer = newmap->allocbuffer = NULL;
+
+ return (0);
+}
+
+/*
+ * Free a piece of memory and it's allocated dmamap, that was allocated
+ * via bus_dmamem_alloc. Make the same choice for free/contigfree.
+ */
+void
+bus_dmamem_free(bus_dma_tag_t dmat, void *vaddr, bus_dmamap_t map)
+{
+ if (map->allocbuffer) {
+ KASSERT(map->allocbuffer == vaddr,
+ ("Trying to freeing the wrong DMA buffer"));
+ vaddr = map->origbuffer;
+ }
+
+ if (map->flags & DMAMAP_UNCACHEABLE)
+ pmap_unmapdev((vm_offset_t)map->allocbuffer, dmat->maxsize);
+ if (map->flags & DMAMAP_MALLOCUSED)
+ free(vaddr, M_DEVBUF);
+ else
+ contigfree(vaddr, dmat->maxsize, M_DEVBUF);
+
+ dmat->map_count--;
+ _busdma_free_dmamap(map);
+ CTR3(KTR_BUSDMA, "%s: tag %p flags 0x%x", __func__, dmat, dmat->flags);
+}
+
+static void
+_bus_dmamap_count_phys(bus_dma_tag_t dmat, bus_dmamap_t map, vm_paddr_t buf,
+ bus_size_t buflen, int flags)
+{
+ bus_addr_t curaddr;
+ bus_size_t sgsize;
+
+ if ((map->pagesneeded == 0)) {
+ CTR3(KTR_BUSDMA, "lowaddr= %d, boundary= %d, alignment= %d",
+ dmat->lowaddr, dmat->boundary, dmat->alignment);
+ CTR2(KTR_BUSDMA, "map= %p, pagesneeded= %d",
+ map, map->pagesneeded);
+ /*
+ * Count the number of bounce pages
+ * needed in order to complete this transfer
+ */
+ curaddr = buf;
+ while (buflen != 0) {
+ sgsize = MIN(buflen, dmat->maxsegsz);
+ if (run_filter(dmat, curaddr) != 0) {
+ sgsize = MIN(sgsize, PAGE_SIZE);
+ map->pagesneeded++;
+ }
+ curaddr += sgsize;
+ buflen -= sgsize;
+ }
+ CTR1(KTR_BUSDMA, "pagesneeded= %d\n", map->pagesneeded);
+ }
+}
+
+static void
+_bus_dmamap_count_pages(bus_dma_tag_t dmat, bus_dmamap_t map, pmap_t pmap,
+ void *buf, bus_size_t buflen, int flags)
+{
+ vm_offset_t vaddr;
+ vm_offset_t vendaddr;
+ bus_addr_t paddr;
+
+ if ((map->pagesneeded == 0)) {
+ CTR3(KTR_BUSDMA, "lowaddr= %d, boundary= %d, alignment= %d",
+ dmat->lowaddr, dmat->boundary, dmat->alignment);
+ CTR2(KTR_BUSDMA, "map= %p, pagesneeded= %d",
+ map, map->pagesneeded);
+ /*
+ * Count the number of bounce pages
+ * needed in order to complete this transfer
+ */
+ vaddr = (vm_offset_t)buf;
+ vendaddr = (vm_offset_t)buf + buflen;
+
+ while (vaddr < vendaddr) {
+ bus_size_t sg_len;
+
+ KASSERT(kernel_pmap == pmap, ("pmap is not kernel pmap"));
+ sg_len = PAGE_SIZE - ((vm_offset_t)vaddr & PAGE_MASK);
+ paddr = pmap_kextract(vaddr);
+ if (((dmat->flags & BUS_DMA_COULD_BOUNCE) != 0) &&
+ run_filter(dmat, paddr) != 0) {
+ sg_len = roundup2(sg_len, dmat->alignment);
+ map->pagesneeded++;
+ }
+ vaddr += sg_len;
+ }
+ CTR1(KTR_BUSDMA, "pagesneeded= %d\n", map->pagesneeded);
+ }
+}
+
+static int
+_bus_dmamap_reserve_pages(bus_dma_tag_t dmat, bus_dmamap_t map,int flags)
+{
+
+ /* Reserve Necessary Bounce Pages */
+ mtx_lock(&bounce_lock);
+ if (flags & BUS_DMA_NOWAIT) {
+ if (reserve_bounce_pages(dmat, map, 0) != 0) {
+ mtx_unlock(&bounce_lock);
+ return (ENOMEM);
+ }
+ } else {
+ if (reserve_bounce_pages(dmat, map, 1) != 0) {
+ /* Queue us for resources */
+ STAILQ_INSERT_TAIL(&bounce_map_waitinglist,
+ map, links);
+ mtx_unlock(&bounce_lock);
+ return (EINPROGRESS);
+ }
+ }
+ mtx_unlock(&bounce_lock);
+
+ return (0);
+}
+
+/*
+ * Add a single contiguous physical range to the segment list.
+ */
+static int
+_bus_dmamap_addseg(bus_dma_tag_t dmat, bus_dmamap_t map, bus_addr_t curaddr,
+ bus_size_t sgsize, bus_dma_segment_t *segs, int *segp)
+{
+ bus_addr_t baddr, bmask;
+ int seg;
+
+ /*
+ * Make sure we don't cross any boundaries.
+ */
+ bmask = ~(dmat->boundary - 1);
+ if (dmat->boundary > 0) {
+ baddr = (curaddr + dmat->boundary) & bmask;
+ if (sgsize > (baddr - curaddr))
+ sgsize = (baddr - curaddr);
+ }
+ /*
+ * Insert chunk into a segment, coalescing with
+ * the previous segment if possible.
+ */
+ seg = *segp;
+ if (seg >= 0 &&
+ curaddr == segs[seg].ds_addr + segs[seg].ds_len &&
+ (segs[seg].ds_len + sgsize) <= dmat->maxsegsz &&
+ (dmat->boundary == 0 ||
+ (segs[seg].ds_addr & bmask) == (curaddr & bmask))) {
+ segs[seg].ds_len += sgsize;
+ } else {
+ if (++seg >= dmat->nsegments)
+ return (0);
+ segs[seg].ds_addr = curaddr;
+ segs[seg].ds_len = sgsize;
+ }
+ *segp = seg;
+ return (sgsize);
+}
+
+/*
+ * Utility function to load a physical buffer. segp contains
+ * the starting segment on entrace, and the ending segment on exit.
+ */
+int
+_bus_dmamap_load_phys(bus_dma_tag_t dmat, bus_dmamap_t map,
+ vm_paddr_t buf, bus_size_t buflen, int flags, bus_dma_segment_t *segs,
+ int *segp)
+{
+ bus_addr_t curaddr;
+ bus_size_t sgsize;
+ int error;
+
+ if (segs == NULL)
+ segs = dmat->segments;
+
+ if ((dmat->flags & BUS_DMA_COULD_BOUNCE) != 0) {
+ _bus_dmamap_count_phys(dmat, map, buf, buflen, flags);
+ if (map->pagesneeded != 0) {
+ error = _bus_dmamap_reserve_pages(dmat, map, flags);
+ if (error)
+ return (error);
+ }
+ }
+
+ while (buflen > 0) {
+ curaddr = buf;
+ sgsize = MIN(buflen, dmat->maxsegsz);
+ if (((dmat->flags & BUS_DMA_COULD_BOUNCE) != 0) &&
+ map->pagesneeded != 0 && run_filter(dmat, curaddr)) {
+ sgsize = MIN(sgsize, PAGE_SIZE);
+ curaddr = add_bounce_page(dmat, map, 0, curaddr,
+ sgsize);
+ }
+ sgsize = _bus_dmamap_addseg(dmat, map, curaddr, sgsize, segs,
+ segp);
+ if (sgsize == 0)
+ break;
+ buf += sgsize;
+ buflen -= sgsize;
+ }
+
+ /*
+ * Did we fit?
+ */
+ if (buflen != 0) {
+ _bus_dmamap_unload(dmat, map);
+ return (EFBIG); /* XXX better return value here? */
+ }
+ return (0);
+}
+
+int
+_bus_dmamap_load_ma(bus_dma_tag_t dmat, bus_dmamap_t map,
+ struct vm_page **ma, bus_size_t tlen, int ma_offs, int flags,
+ bus_dma_segment_t *segs, int *segp)
+{
+
+ return (bus_dmamap_load_ma_triv(dmat, map, ma, tlen, ma_offs, flags,
+ segs, segp));
+}
+
+/*
+ * Utility function to load a linear buffer. segp contains
+ * the starting segment on entrance, and the ending segment on exit.
+ * first indicates if this is the first invocation of this function.
+ */
+int
+_bus_dmamap_load_buffer(bus_dma_tag_t dmat, bus_dmamap_t map, void *buf,
+ bus_size_t buflen, struct pmap *pmap, int flags, bus_dma_segment_t *segs,
+ int *segp)
+{
+ bus_size_t sgsize;
+ bus_addr_t curaddr;
+ struct sync_list *sl;
+ vm_offset_t vaddr = (vm_offset_t)buf;
+ int error = 0;
+
+
+ if (segs == NULL)
+ segs = dmat->segments;
+
+ if ((dmat->flags & BUS_DMA_COULD_BOUNCE) != 0) {
+ _bus_dmamap_count_pages(dmat, map, pmap, buf, buflen, flags);
+ if (map->pagesneeded != 0) {
+ error = _bus_dmamap_reserve_pages(dmat, map, flags);
+ if (error)
+ return (error);
+ }
+ }
+ CTR3(KTR_BUSDMA, "lowaddr= %d boundary= %d, "
+ "alignment= %d", dmat->lowaddr, dmat->boundary, dmat->alignment);
+
+ while (buflen > 0) {
+ /*
+ * Get the physical address for this segment.
+ *
+ * XXX Don't support checking for coherent mappings
+ * XXX in user address space.
+ */
+ KASSERT(kernel_pmap == pmap, ("pmap is not kernel pmap"));
+ curaddr = pmap_kextract(vaddr);
+
+ /*
+ * Compute the segment size, and adjust counts.
+ */
+ sgsize = PAGE_SIZE - ((u_long)curaddr & PAGE_MASK);
+ if (sgsize > dmat->maxsegsz)
+ sgsize = dmat->maxsegsz;
+ if (buflen < sgsize)
+ sgsize = buflen;
+
+ if (((dmat->flags & BUS_DMA_COULD_BOUNCE) != 0) &&
+ map->pagesneeded != 0 && run_filter(dmat, curaddr)) {
+ curaddr = add_bounce_page(dmat, map, vaddr, curaddr,
+ sgsize);
+ } else {
+ sl = &map->slist[map->sync_count - 1];
+ if (map->sync_count == 0 ||
+ vaddr != sl->vaddr + sl->datacount) {
+ if (++map->sync_count > dmat->nsegments)
+ goto cleanup;
+ sl++;
+ sl->vaddr = vaddr;
+ sl->datacount = sgsize;
+ sl->busaddr = curaddr;
+ } else
+ sl->datacount += sgsize;
+ }
+ sgsize = _bus_dmamap_addseg(dmat, map, curaddr, sgsize, segs,
+ segp);
+ if (sgsize == 0)
+ break;
+ vaddr += sgsize;
+ buflen -= sgsize;
+ }
+
+cleanup:
+ /*
+ * Did we fit?
+ */
+ if (buflen != 0) {
+ _bus_dmamap_unload(dmat, map);
+ error = EFBIG; /* XXX better return value here? */
+ }
+ return (error);
+}
+
+void
+__bus_dmamap_waitok(bus_dma_tag_t dmat, bus_dmamap_t map,
+ struct memdesc *mem, bus_dmamap_callback_t *callback, void *callback_arg)
+{
+
+ KASSERT(dmat != NULL, ("dmatag is NULL"));
+ KASSERT(map != NULL, ("dmamap is NULL"));
+ map->mem = *mem;
+ map->callback = callback;
+ map->callback_arg = callback_arg;
+}
+
+bus_dma_segment_t *
+_bus_dmamap_complete(bus_dma_tag_t dmat, bus_dmamap_t map,
+ bus_dma_segment_t *segs, int nsegs, int error)
+{
+
+ if (segs == NULL)
+ segs = dmat->segments;
+ return (segs);
+}
+
+/*
+ * Release the mapping held by map.
+ */
+void
+_bus_dmamap_unload(bus_dma_tag_t dmat, bus_dmamap_t map)
+{
+ struct bounce_page *bpage;
+
+ while ((bpage = STAILQ_FIRST(&map->bpages)) != NULL) {
+ STAILQ_REMOVE_HEAD(&map->bpages, links);
+ free_bounce_page(dmat, bpage);
+ }
+ map->sync_count = 0;
+ return;
+}
+
+static void
+bus_dmamap_sync_buf(vm_offset_t buf, int len, bus_dmasync_op_t op)
+{
+ char tmp_cl[mips_pdcache_linesize], tmp_clend[mips_pdcache_linesize];
+ vm_offset_t buf_cl, buf_clend;
+ vm_size_t size_cl, size_clend;
+ int cache_linesize_mask = mips_pdcache_linesize - 1;
+
+ /*
+ * dcache invalidation operates on cache line aligned addresses
+ * and could modify areas of memory that share the same cache line
+ * at the beginning and the ending of the buffer. In order to
+ * prevent a data loss we save these chunks in temporary buffer
+ * before invalidation and restore them afer it
+ */
+ buf_cl = buf & ~cache_linesize_mask;
+ size_cl = buf & cache_linesize_mask;
+ buf_clend = buf + len;
+ size_clend = (mips_pdcache_linesize -
+ (buf_clend & cache_linesize_mask)) & cache_linesize_mask;
+
+ switch (op) {
+ case BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE:
+ case BUS_DMASYNC_POSTREAD:
+
+ /*
+ * Save buffers that might be modified by invalidation
+ */
+ if (size_cl)
+ memcpy (tmp_cl, (void*)buf_cl, size_cl);
+ if (size_clend)
+ memcpy (tmp_clend, (void*)buf_clend, size_clend);
+ mips_dcache_inv_range(buf, len);
+ /*
+ * Restore them
+ */
+ if (size_cl)
+ memcpy ((void*)buf_cl, tmp_cl, size_cl);
+ if (size_clend)
+ memcpy ((void*)buf_clend, tmp_clend, size_clend);
+ /*
+ * Copies above have brought corresponding memory
+ * cache lines back into dirty state. Write them back
+ * out and invalidate affected cache lines again if
+ * necessary.
+ */
+ if (size_cl)
+ mips_dcache_wbinv_range(buf_cl, size_cl);
+ if (size_clend && (size_cl == 0 ||
+ buf_clend - buf_cl > mips_pdcache_linesize))
+ mips_dcache_wbinv_range(buf_clend, size_clend);
+ break;
+
+ case BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE:
+ mips_dcache_wbinv_range(buf_cl, len);
+ break;
+
+ case BUS_DMASYNC_PREREAD:
+ /*
+ * Save buffers that might be modified by invalidation
+ */
+ if (size_cl)
+ memcpy (tmp_cl, (void *)buf_cl, size_cl);
+ if (size_clend)
+ memcpy (tmp_clend, (void *)buf_clend, size_clend);
+ mips_dcache_inv_range(buf, len);
+ /*
+ * Restore them
+ */
+ if (size_cl)
+ memcpy ((void *)buf_cl, tmp_cl, size_cl);
+ if (size_clend)
+ memcpy ((void *)buf_clend, tmp_clend, size_clend);
+ /*
+ * Copies above have brought corresponding memory
+ * cache lines back into dirty state. Write them back
+ * out and invalidate affected cache lines again if
+ * necessary.
+ */
+ if (size_cl)
+ mips_dcache_wbinv_range(buf_cl, size_cl);
+ if (size_clend && (size_cl == 0 ||
+ buf_clend - buf_cl > mips_pdcache_linesize))
+ mips_dcache_wbinv_range(buf_clend, size_clend);
+ break;
+
+ case BUS_DMASYNC_PREWRITE:
+ mips_dcache_wb_range(buf, len);
+ break;
+ }
+}
+
+static void
+_bus_dmamap_sync_bp(bus_dma_tag_t dmat, bus_dmamap_t map, bus_dmasync_op_t op)
+{
+ struct bounce_page *bpage;
+
+ STAILQ_FOREACH(bpage, &map->bpages, links) {
+ if (op & BUS_DMASYNC_PREWRITE) {
+ if (bpage->datavaddr != 0)
+ bcopy((void *)bpage->datavaddr,
+ (void *)(bpage->vaddr_nocache != 0 ?
+ bpage->vaddr_nocache :
+ bpage->vaddr),
+ bpage->datacount);
+ else
+ physcopyout(bpage->dataaddr,
+ (void *)(bpage->vaddr_nocache != 0 ?
+ bpage->vaddr_nocache :
+ bpage->vaddr),
+ bpage->datacount);
+ if (bpage->vaddr_nocache == 0) {
+ mips_dcache_wb_range(bpage->vaddr,
+ bpage->datacount);
+ }
+ dmat->bounce_zone->total_bounced++;
+ }
+ if (op & BUS_DMASYNC_POSTREAD) {
+ if (bpage->vaddr_nocache == 0) {
+ mips_dcache_inv_range(bpage->vaddr,
+ bpage->datacount);
+ }
+ if (bpage->datavaddr != 0)
+ bcopy((void *)(bpage->vaddr_nocache != 0 ?
+ bpage->vaddr_nocache : bpage->vaddr),
+ (void *)bpage->datavaddr, bpage->datacount);
+ else
+ physcopyin((void *)(bpage->vaddr_nocache != 0 ?
+ bpage->vaddr_nocache : bpage->vaddr),
+ bpage->dataaddr, bpage->datacount);
+ dmat->bounce_zone->total_bounced++;
+ }
+ }
+}
+
+void
+_bus_dmamap_sync(bus_dma_tag_t dmat, bus_dmamap_t map, bus_dmasync_op_t op)
+{
+ struct sync_list *sl, *end;
+
+ if (op == BUS_DMASYNC_POSTWRITE)
+ return;
+ if (STAILQ_FIRST(&map->bpages))
+ _bus_dmamap_sync_bp(dmat, map, op);
+
+ if (dmat->flags & BUS_DMA_COHERENT)
+ return;
+
+ if (map->flags & DMAMAP_UNCACHEABLE)
+ return;
+
+ CTR3(KTR_BUSDMA, "%s: op %x flags %x", __func__, op, map->flags);
+ if (map->sync_count) {
+ end = &map->slist[map->sync_count];
+ for (sl = &map->slist[0]; sl != end; sl++)
+ bus_dmamap_sync_buf(sl->vaddr, sl->datacount, op);
+ }
+}
+
+static void
+init_bounce_pages(void *dummy __unused)
+{
+
+ total_bpages = 0;
+ STAILQ_INIT(&bounce_zone_list);
+ STAILQ_INIT(&bounce_map_waitinglist);
+ STAILQ_INIT(&bounce_map_callbacklist);
+ mtx_init(&bounce_lock, "bounce pages lock", NULL, MTX_DEF);
+}
+SYSINIT(bpages, SI_SUB_LOCK, SI_ORDER_ANY, init_bounce_pages, NULL);
+
+static struct sysctl_ctx_list *
+busdma_sysctl_tree(struct bounce_zone *bz)
+{
+ return (&bz->sysctl_tree);
+}
+
+static struct sysctl_oid *
+busdma_sysctl_tree_top(struct bounce_zone *bz)
+{
+ return (bz->sysctl_tree_top);
+}
+
+static int
+alloc_bounce_zone(bus_dma_tag_t dmat)
+{
+ struct bounce_zone *bz;
+
+ /* Check to see if we already have a suitable zone */
+ STAILQ_FOREACH(bz, &bounce_zone_list, links) {
+ if ((dmat->alignment <= bz->alignment)
+ && (dmat->lowaddr >= bz->lowaddr)) {
+ dmat->bounce_zone = bz;
+ return (0);
+ }
+ }
+
+ if ((bz = (struct bounce_zone *)malloc(sizeof(*bz), M_DEVBUF,
+ M_NOWAIT | M_ZERO)) == NULL)
+ return (ENOMEM);
+
+ STAILQ_INIT(&bz->bounce_page_list);
+ bz->free_bpages = 0;
+ bz->reserved_bpages = 0;
+ bz->active_bpages = 0;
+ bz->lowaddr = dmat->lowaddr;
+ bz->alignment = MAX(dmat->alignment, PAGE_SIZE);
+ bz->map_count = 0;
+ snprintf(bz->zoneid, 8, "zone%d", busdma_zonecount);
+ busdma_zonecount++;
+ snprintf(bz->lowaddrid, 18, "%#jx", (uintmax_t)bz->lowaddr);
+ STAILQ_INSERT_TAIL(&bounce_zone_list, bz, links);
+ dmat->bounce_zone = bz;
+
+ sysctl_ctx_init(&bz->sysctl_tree);
+ bz->sysctl_tree_top = SYSCTL_ADD_NODE(&bz->sysctl_tree,
+ SYSCTL_STATIC_CHILDREN(_hw_busdma), OID_AUTO, bz->zoneid,
+ CTLFLAG_RD, 0, "");
+ if (bz->sysctl_tree_top == NULL) {
+ sysctl_ctx_free(&bz->sysctl_tree);
+ return (0); /* XXX error code? */
+ }
+
+ SYSCTL_ADD_INT(busdma_sysctl_tree(bz),
+ SYSCTL_CHILDREN(busdma_sysctl_tree_top(bz)), OID_AUTO,
+ "total_bpages", CTLFLAG_RD, &bz->total_bpages, 0,
+ "Total bounce pages");
+ SYSCTL_ADD_INT(busdma_sysctl_tree(bz),
+ SYSCTL_CHILDREN(busdma_sysctl_tree_top(bz)), OID_AUTO,
+ "free_bpages", CTLFLAG_RD, &bz->free_bpages, 0,
+ "Free bounce pages");
+ SYSCTL_ADD_INT(busdma_sysctl_tree(bz),
+ SYSCTL_CHILDREN(busdma_sysctl_tree_top(bz)), OID_AUTO,
+ "reserved_bpages", CTLFLAG_RD, &bz->reserved_bpages, 0,
+ "Reserved bounce pages");
+ SYSCTL_ADD_INT(busdma_sysctl_tree(bz),
+ SYSCTL_CHILDREN(busdma_sysctl_tree_top(bz)), OID_AUTO,
+ "active_bpages", CTLFLAG_RD, &bz->active_bpages, 0,
+ "Active bounce pages");
+ SYSCTL_ADD_INT(busdma_sysctl_tree(bz),
+ SYSCTL_CHILDREN(busdma_sysctl_tree_top(bz)), OID_AUTO,
+ "total_bounced", CTLFLAG_RD, &bz->total_bounced, 0,
+ "Total bounce requests");
+ SYSCTL_ADD_INT(busdma_sysctl_tree(bz),
+ SYSCTL_CHILDREN(busdma_sysctl_tree_top(bz)), OID_AUTO,
+ "total_deferred", CTLFLAG_RD, &bz->total_deferred, 0,
+ "Total bounce requests that were deferred");
+ SYSCTL_ADD_STRING(busdma_sysctl_tree(bz),
+ SYSCTL_CHILDREN(busdma_sysctl_tree_top(bz)), OID_AUTO,
+ "lowaddr", CTLFLAG_RD, bz->lowaddrid, 0, "");
+ SYSCTL_ADD_UAUTO(busdma_sysctl_tree(bz),
+ SYSCTL_CHILDREN(busdma_sysctl_tree_top(bz)), OID_AUTO,
+ "alignment", CTLFLAG_RD, &bz->alignment, "");
+
+ return (0);
+}
+
+static int
+alloc_bounce_pages(bus_dma_tag_t dmat, u_int numpages)
+{
+ struct bounce_zone *bz;
+ int count;
+
+ bz = dmat->bounce_zone;
+ count = 0;
+ while (numpages > 0) {
+ struct bounce_page *bpage;
+
+ bpage = (struct bounce_page *)malloc(sizeof(*bpage), M_DEVBUF,
+ M_NOWAIT | M_ZERO);
+
+ if (bpage == NULL)
+ break;
+ bpage->vaddr = (vm_offset_t)contigmalloc(PAGE_SIZE, M_DEVBUF,
+ M_NOWAIT, 0ul,
+ bz->lowaddr,
+ PAGE_SIZE,
+ 0);
+ if (bpage->vaddr == 0) {
+ free(bpage, M_DEVBUF);
+ break;
+ }
+ bpage->busaddr = pmap_kextract(bpage->vaddr);
+ bpage->vaddr_nocache =
+ (vm_offset_t)pmap_mapdev(bpage->busaddr, PAGE_SIZE);
+ mtx_lock(&bounce_lock);
+ STAILQ_INSERT_TAIL(&bz->bounce_page_list, bpage, links);
+ total_bpages++;
+ bz->total_bpages++;
+ bz->free_bpages++;
+ mtx_unlock(&bounce_lock);
+ count++;
+ numpages--;
+ }
+ return (count);
+}
+
+static int
+reserve_bounce_pages(bus_dma_tag_t dmat, bus_dmamap_t map, int commit)
+{
+ struct bounce_zone *bz;
+ int pages;
+
+ mtx_assert(&bounce_lock, MA_OWNED);
+ bz = dmat->bounce_zone;
+ pages = MIN(bz->free_bpages, map->pagesneeded - map->pagesreserved);
+ if (commit == 0 && map->pagesneeded > (map->pagesreserved + pages))
+ return (map->pagesneeded - (map->pagesreserved + pages));
+ bz->free_bpages -= pages;
+ bz->reserved_bpages += pages;
+ map->pagesreserved += pages;
+ pages = map->pagesneeded - map->pagesreserved;
+
+ return (pages);
+}
+
+static bus_addr_t
+add_bounce_page(bus_dma_tag_t dmat, bus_dmamap_t map, vm_offset_t vaddr,
+ bus_addr_t addr, bus_size_t size)
+{
+ struct bounce_zone *bz;
+ struct bounce_page *bpage;
+
+ KASSERT(dmat->bounce_zone != NULL, ("no bounce zone in dma tag"));
+ KASSERT(map != NULL, ("add_bounce_page: bad map %p", map));
+
+ bz = dmat->bounce_zone;
+ if (map->pagesneeded == 0)
+ panic("add_bounce_page: map doesn't need any pages");
+ map->pagesneeded--;
+
+ if (map->pagesreserved == 0)
+ panic("add_bounce_page: map doesn't need any pages");
+ map->pagesreserved--;
+
+ mtx_lock(&bounce_lock);
+ bpage = STAILQ_FIRST(&bz->bounce_page_list);
+ if (bpage == NULL)
+ panic("add_bounce_page: free page list is empty");
+
+ STAILQ_REMOVE_HEAD(&bz->bounce_page_list, links);
+ bz->reserved_bpages--;
+ bz->active_bpages++;
+ mtx_unlock(&bounce_lock);
+
+ if (dmat->flags & BUS_DMA_KEEP_PG_OFFSET) {
+ /* Page offset needs to be preserved. */
+ bpage->vaddr |= addr & PAGE_MASK;
+ bpage->busaddr |= addr & PAGE_MASK;
+ }
+ bpage->datavaddr = vaddr;
+ bpage->dataaddr = addr;
+ bpage->datacount = size;
+ STAILQ_INSERT_TAIL(&(map->bpages), bpage, links);
+ return (bpage->busaddr);
+}
+
+static void
+free_bounce_page(bus_dma_tag_t dmat, struct bounce_page *bpage)
+{
+ struct bus_dmamap *map;
+ struct bounce_zone *bz;
+
+ bz = dmat->bounce_zone;
+ bpage->datavaddr = 0;
+ bpage->datacount = 0;
+ if (dmat->flags & BUS_DMA_KEEP_PG_OFFSET) {
+ /*
+ * Reset the bounce page to start at offset 0. Other uses
+ * of this bounce page may need to store a full page of
+ * data and/or assume it starts on a page boundary.
+ */
+ bpage->vaddr &= ~PAGE_MASK;
+ bpage->busaddr &= ~PAGE_MASK;
+ }
+
+ mtx_lock(&bounce_lock);
+ STAILQ_INSERT_HEAD(&bz->bounce_page_list, bpage, links);
+ bz->free_bpages++;
+ bz->active_bpages--;
+ if ((map = STAILQ_FIRST(&bounce_map_waitinglist)) != NULL) {
+ if (reserve_bounce_pages(map->dmat, map, 1) == 0) {
+ STAILQ_REMOVE_HEAD(&bounce_map_waitinglist, links);
+ STAILQ_INSERT_TAIL(&bounce_map_callbacklist,
+ map, links);
+ busdma_swi_pending = 1;
+ bz->total_deferred++;
+ swi_sched(vm_ih, 0);
+ }
+ }
+ mtx_unlock(&bounce_lock);
+}
+
+void
+busdma_swi(void)
+{
+ bus_dma_tag_t dmat;
+ struct bus_dmamap *map;
+
+ mtx_lock(&bounce_lock);
+ while ((map = STAILQ_FIRST(&bounce_map_callbacklist)) != NULL) {
+ STAILQ_REMOVE_HEAD(&bounce_map_callbacklist, links);
+ mtx_unlock(&bounce_lock);
+ dmat = map->dmat;
+ (dmat->lockfunc)(dmat->lockfuncarg, BUS_DMA_LOCK);
+ bus_dmamap_load_mem(map->dmat, map, &map->mem, map->callback,
+ map->callback_arg, BUS_DMA_WAITOK);
+ (dmat->lockfunc)(dmat->lockfuncarg, BUS_DMA_UNLOCK);
+ mtx_lock(&bounce_lock);
+ }
+ mtx_unlock(&bounce_lock);
+}
Property changes on: trunk/sys/mips/mips/busdma_machdep.c
___________________________________________________________________
Added: svn:eol-style
## -0,0 +1 ##
+native
\ No newline at end of property
Added: svn:keywords
## -0,0 +1 ##
+MidnightBSD=%H
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+text/plain
\ No newline at end of property
Added: trunk/sys/mips/mips/cache.c
===================================================================
--- trunk/sys/mips/mips/cache.c (rev 0)
+++ trunk/sys/mips/mips/cache.c 2018-05-26 21:55:02 UTC (rev 9987)
@@ -0,0 +1,279 @@
+/* $MidnightBSD$ */
+/* $NetBSD: cache.c,v 1.33 2005/12/24 23:24:01 perry Exp $ */
+
+/*-
+ * Copyright 2001, 2002 Wasabi Systems, Inc.
+ * All rights reserved.
+ *
+ * Written by Jason R. Thorpe and Simon Burge for Wasabi Systems, Inc.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * 3. All advertising materials mentioning features or use of this software
+ * must display the following acknowledgement:
+ * This product includes software developed for the NetBSD Project by
+ * Wasabi Systems, Inc.
+ * 4. The name of Wasabi Systems, Inc. may not be used to endorse
+ * or promote products derived from this software without specific prior
+ * written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/*-
+ * Copyright 2000, 2001
+ * Broadcom Corporation. All rights reserved.
+ *
+ * This software is furnished under license and may be used and copied only
+ * in accordance with the following terms and conditions. Subject to these
+ * conditions, you may download, copy, install, use, modify and distribute
+ * modified or unmodified copies of this software in source and/or binary
+ * form. No title or ownership is transferred hereby.
+ *
+ * 1) Any source code used, modified or distributed must reproduce and
+ * retain this copyright notice and list of conditions as they appear in
+ * the source file.
+ *
+ * 2) No right is granted to use any trade name, trademark, or logo of
+ * Broadcom Corporation. The "Broadcom Corporation" name may not be
+ * used to endorse or promote products derived from this software
+ * without the prior written permission of Broadcom Corporation.
+ *
+ * 3) THIS SOFTWARE IS PROVIDED "AS-IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING BUT NOT LIMITED TO, ANY IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, OR
+ * NON-INFRINGEMENT ARE DISCLAIMED. IN NO EVENT SHALL BROADCOM BE LIABLE
+ * FOR ANY DAMAGES WHATSOEVER, AND IN PARTICULAR, BROADCOM SHALL NOT BE
+ * LIABLE FOR DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
+ * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
+ * OR OTHERWISE), EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <sys/cdefs.h>
+__FBSDID("$FreeBSD: stable/10/sys/mips/mips/cache.c 261277 2014-01-29 22:01:42Z brooks $");
+
+#include <sys/types.h>
+#include <sys/systm.h>
+
+#include <machine/cpuinfo.h>
+#include <machine/cache.h>
+
+struct mips_cache_ops mips_cache_ops;
+
+#if defined(MIPS_DISABLE_L1_CACHE) || defined(CPU_RMI) || defined(CPU_NLM)
+static void
+cache_noop(vm_offset_t va, vm_size_t size)
+{
+}
+#endif
+
+void
+mips_config_cache(struct mips_cpuinfo * cpuinfo)
+{
+
+ switch (cpuinfo->l1.ic_linesize) {
+ case 16:
+ mips_cache_ops.mco_icache_sync_all = mipsNN_icache_sync_all_16;
+ mips_cache_ops.mco_icache_sync_range =
+ mipsNN_icache_sync_range_16;
+ mips_cache_ops.mco_icache_sync_range_index =
+ mipsNN_icache_sync_range_index_16;
+ break;
+ case 32:
+ mips_cache_ops.mco_icache_sync_all = mipsNN_icache_sync_all_32;
+ mips_cache_ops.mco_icache_sync_range =
+ mipsNN_icache_sync_range_32;
+ mips_cache_ops.mco_icache_sync_range_index =
+ mipsNN_icache_sync_range_index_32;
+ break;
+#ifdef CPU_CNMIPS
+ case 128:
+ mips_cache_ops.mco_icache_sync_all = mipsNN_icache_sync_all_128;
+ mips_cache_ops.mco_icache_sync_range =
+ mipsNN_icache_sync_range_128;
+ mips_cache_ops.mco_icache_sync_range_index =
+ mipsNN_icache_sync_range_index_128;
+ break;
+#endif
+
+#ifdef MIPS_DISABLE_L1_CACHE
+ case 0:
+ mips_cache_ops.mco_icache_sync_all = (void (*)(void))cache_noop;
+ mips_cache_ops.mco_icache_sync_range = cache_noop;
+ mips_cache_ops.mco_icache_sync_range_index = cache_noop;
+ break;
+#endif
+ default:
+ panic("no Icache ops for %d byte lines",
+ cpuinfo->l1.ic_linesize);
+ }
+
+ switch (cpuinfo->l1.dc_linesize) {
+ case 16:
+ mips_cache_ops.mco_pdcache_wbinv_all =
+ mips_cache_ops.mco_intern_pdcache_wbinv_all =
+ mipsNN_pdcache_wbinv_all_16;
+ mips_cache_ops.mco_pdcache_wbinv_range =
+ mipsNN_pdcache_wbinv_range_16;
+ mips_cache_ops.mco_pdcache_wbinv_range_index =
+ mips_cache_ops.mco_intern_pdcache_wbinv_range_index =
+ mipsNN_pdcache_wbinv_range_index_16;
+ mips_cache_ops.mco_pdcache_inv_range =
+ mipsNN_pdcache_inv_range_16;
+ mips_cache_ops.mco_pdcache_wb_range =
+ mips_cache_ops.mco_intern_pdcache_wb_range =
+ mipsNN_pdcache_wb_range_16;
+ break;
+ case 32:
+ mips_cache_ops.mco_pdcache_wbinv_all =
+ mips_cache_ops.mco_intern_pdcache_wbinv_all =
+ mipsNN_pdcache_wbinv_all_32;
+#if defined(CPU_RMI) || defined(CPU_NLM)
+ mips_cache_ops.mco_pdcache_wbinv_range = cache_noop;
+#else
+ mips_cache_ops.mco_pdcache_wbinv_range =
+ mipsNN_pdcache_wbinv_range_32;
+#endif
+#if defined(CPU_RMI) || defined(CPU_NLM)
+ mips_cache_ops.mco_pdcache_wbinv_range_index =
+ mips_cache_ops.mco_intern_pdcache_wbinv_range_index = cache_noop;
+ mips_cache_ops.mco_pdcache_inv_range = cache_noop;
+#else
+ mips_cache_ops.mco_pdcache_wbinv_range_index =
+ mips_cache_ops.mco_intern_pdcache_wbinv_range_index =
+ mipsNN_pdcache_wbinv_range_index_32;
+ mips_cache_ops.mco_pdcache_inv_range =
+ mipsNN_pdcache_inv_range_32;
+#endif
+#if defined(CPU_RMI) || defined(CPU_NLM)
+ mips_cache_ops.mco_pdcache_wb_range =
+ mips_cache_ops.mco_intern_pdcache_wb_range = cache_noop;
+#else
+ mips_cache_ops.mco_pdcache_wb_range =
+ mips_cache_ops.mco_intern_pdcache_wb_range =
+ mipsNN_pdcache_wb_range_32;
+#endif
+ break;
+#ifdef CPU_CNMIPS
+ case 128:
+ mips_cache_ops.mco_pdcache_wbinv_all =
+ mips_cache_ops.mco_intern_pdcache_wbinv_all =
+ mipsNN_pdcache_wbinv_all_128;
+ mips_cache_ops.mco_pdcache_wbinv_range =
+ mipsNN_pdcache_wbinv_range_128;
+ mips_cache_ops.mco_pdcache_wbinv_range_index =
+ mips_cache_ops.mco_intern_pdcache_wbinv_range_index =
+ mipsNN_pdcache_wbinv_range_index_128;
+ mips_cache_ops.mco_pdcache_inv_range =
+ mipsNN_pdcache_inv_range_128;
+ mips_cache_ops.mco_pdcache_wb_range =
+ mips_cache_ops.mco_intern_pdcache_wb_range =
+ mipsNN_pdcache_wb_range_128;
+ break;
+#endif
+#ifdef MIPS_DISABLE_L1_CACHE
+ case 0:
+ mips_cache_ops.mco_pdcache_wbinv_all =
+ mips_cache_ops.mco_intern_pdcache_wbinv_all =
+ (void (*)(void))cache_noop;
+ mips_cache_ops.mco_pdcache_wbinv_range = cache_noop;
+ mips_cache_ops.mco_pdcache_wbinv_range_index = cache_noop;
+ mips_cache_ops.mco_intern_pdcache_wbinv_range_index =
+ cache_noop;
+ mips_cache_ops.mco_pdcache_inv_range = cache_noop;
+ mips_cache_ops.mco_pdcache_wb_range = cache_noop;
+ mips_cache_ops.mco_intern_pdcache_wb_range = cache_noop;
+ break;
+#endif
+ default:
+ panic("no Dcache ops for %d byte lines",
+ cpuinfo->l1.dc_linesize);
+ }
+
+ mipsNN_cache_init(cpuinfo);
+
+#if 0
+ if (mips_cpu_flags &
+ (CPU_MIPS_D_CACHE_COHERENT | CPU_MIPS_I_D_CACHE_COHERENT)) {
+#ifdef CACHE_DEBUG
+ printf(" Dcache is coherent\n");
+#endif
+ mips_cache_ops.mco_pdcache_wbinv_all =
+ (void (*)(void))cache_noop;
+ mips_cache_ops.mco_pdcache_wbinv_range = cache_noop;
+ mips_cache_ops.mco_pdcache_wbinv_range_index = cache_noop;
+ mips_cache_ops.mco_pdcache_inv_range = cache_noop;
+ mips_cache_ops.mco_pdcache_wb_range = cache_noop;
+ }
+ if (mips_cpu_flags & CPU_MIPS_I_D_CACHE_COHERENT) {
+#ifdef CACHE_DEBUG
+ printf(" Icache is coherent against Dcache\n");
+#endif
+ mips_cache_ops.mco_intern_pdcache_wbinv_all =
+ (void (*)(void))cache_noop;
+ mips_cache_ops.mco_intern_pdcache_wbinv_range_index =
+ cache_noop;
+ mips_cache_ops.mco_intern_pdcache_wb_range = cache_noop;
+ }
+#endif
+
+ /* Check that all cache ops are set up. */
+ /* must have primary Icache */
+ if (cpuinfo->l1.ic_size) {
+
+ if (!mips_cache_ops.mco_icache_sync_all)
+ panic("no icache_sync_all cache op");
+ if (!mips_cache_ops.mco_icache_sync_range)
+ panic("no icache_sync_range cache op");
+ if (!mips_cache_ops.mco_icache_sync_range_index)
+ panic("no icache_sync_range_index cache op");
+ }
+ /* must have primary Dcache */
+ if (cpuinfo->l1.dc_size) {
+ if (!mips_cache_ops.mco_pdcache_wbinv_all)
+ panic("no pdcache_wbinv_all");
+ if (!mips_cache_ops.mco_pdcache_wbinv_range)
+ panic("no pdcache_wbinv_range");
+ if (!mips_cache_ops.mco_pdcache_wbinv_range_index)
+ panic("no pdcache_wbinv_range_index");
+ if (!mips_cache_ops.mco_pdcache_inv_range)
+ panic("no pdcache_inv_range");
+ if (!mips_cache_ops.mco_pdcache_wb_range)
+ panic("no pdcache_wb_range");
+ }
+
+ /* XXXMIPS: No secondary cache handlers yet */
+#ifdef notyet
+ if (mips_sdcache_size) {
+ if (!mips_cache_ops.mco_sdcache_wbinv_all)
+ panic("no sdcache_wbinv_all");
+ if (!mips_cache_ops.mco_sdcache_wbinv_range)
+ panic("no sdcache_wbinv_range");
+ if (!mips_cache_ops.mco_sdcache_wbinv_range_index)
+ panic("no sdcache_wbinv_range_index");
+ if (!mips_cache_ops.mco_sdcache_inv_range)
+ panic("no sdcache_inv_range");
+ if (!mips_cache_ops.mco_sdcache_wb_range)
+ panic("no sdcache_wb_range");
+ }
+#endif
+}
Property changes on: trunk/sys/mips/mips/cache.c
___________________________________________________________________
Added: svn:eol-style
## -0,0 +1 ##
+native
\ No newline at end of property
Added: svn:keywords
## -0,0 +1 ##
+MidnightBSD=%H
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+text/plain
\ No newline at end of property
Added: trunk/sys/mips/mips/cache_mipsNN.c
===================================================================
--- trunk/sys/mips/mips/cache_mipsNN.c (rev 0)
+++ trunk/sys/mips/mips/cache_mipsNN.c 2018-05-26 21:55:02 UTC (rev 9987)
@@ -0,0 +1,639 @@
+/* $MidnightBSD$ */
+/* $NetBSD: cache_mipsNN.c,v 1.10 2005/12/24 20:07:19 perry Exp $ */
+
+/*
+ * Copyright 2001 Wasabi Systems, Inc.
+ * All rights reserved.
+ *
+ * Written by Jason R. Thorpe and Simon Burge for Wasabi Systems, Inc.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * 3. All advertising materials mentioning features or use of this software
+ * must display the following acknowledgement:
+ * This product includes software developed for the NetBSD Project by
+ * Wasabi Systems, Inc.
+ * 4. The name of Wasabi Systems, Inc. may not be used to endorse
+ * or promote products derived from this software without specific prior
+ * written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <sys/cdefs.h>
+__FBSDID("$FreeBSD: stable/10/sys/mips/mips/cache_mipsNN.c 232896 2012-03-12 21:25:32Z jmallett $");
+
+#include <sys/types.h>
+#include <sys/systm.h>
+#include <sys/param.h>
+
+#include <machine/cache.h>
+#include <machine/cache_r4k.h>
+#include <machine/cpuinfo.h>
+
+#define round_line16(x) (((x) + 15) & ~15)
+#define trunc_line16(x) ((x) & ~15)
+
+#define round_line32(x) (((x) + 31) & ~31)
+#define trunc_line32(x) ((x) & ~31)
+
+#if defined(CPU_NLM)
+static __inline void
+xlp_sync(void)
+{
+ __asm __volatile (
+ ".set push \n"
+ ".set noreorder \n"
+ ".set mips64 \n"
+ "dla $8, 1f \n"
+ "/* jr.hb $8 */ \n"
+ ".word 0x1000408 \n"
+ "nop \n"
+ "1: nop \n"
+ ".set pop \n"
+ : : : "$8");
+}
+#endif
+
+#if defined(SB1250_PASS1)
+#define SYNC __asm volatile("sync; sync")
+#elif defined(CPU_NLM)
+#define SYNC xlp_sync()
+#else
+#define SYNC __asm volatile("sync")
+#endif
+
+#if defined(CPU_CNMIPS)
+#define SYNCI mips_sync_icache();
+#elif defined(CPU_NLM)
+#define SYNCI xlp_sync()
+#else
+#define SYNCI
+#endif
+
+/*
+ * Exported variables for consumers like bus_dma code
+ */
+int mips_picache_linesize;
+int mips_pdcache_linesize;
+
+static int picache_size;
+static int picache_stride;
+static int picache_loopcount;
+static int picache_way_mask;
+static int pdcache_size;
+static int pdcache_stride;
+static int pdcache_loopcount;
+static int pdcache_way_mask;
+
+void
+mipsNN_cache_init(struct mips_cpuinfo * cpuinfo)
+{
+ int flush_multiple_lines_per_way;
+
+ flush_multiple_lines_per_way = cpuinfo->l1.ic_nsets * cpuinfo->l1.ic_linesize * cpuinfo->l1.ic_linesize > PAGE_SIZE;
+ if (cpuinfo->icache_virtual) {
+ /*
+ * With a virtual Icache we don't need to flush
+ * multiples of the page size with index ops; we just
+ * need to flush one pages' worth.
+ */
+ flush_multiple_lines_per_way = 0;
+ }
+
+ if (flush_multiple_lines_per_way) {
+ picache_stride = PAGE_SIZE;
+ picache_loopcount = (cpuinfo->l1.ic_nsets * cpuinfo->l1.ic_linesize / PAGE_SIZE) *
+ cpuinfo->l1.ic_nways;
+ } else {
+ picache_stride = cpuinfo->l1.ic_nsets * cpuinfo->l1.ic_linesize;
+ picache_loopcount = cpuinfo->l1.ic_nways;
+ }
+
+ if (cpuinfo->l1.dc_nsets * cpuinfo->l1.dc_linesize < PAGE_SIZE) {
+ pdcache_stride = cpuinfo->l1.dc_nsets * cpuinfo->l1.dc_linesize;
+ pdcache_loopcount = cpuinfo->l1.dc_nways;
+ } else {
+ pdcache_stride = PAGE_SIZE;
+ pdcache_loopcount = (cpuinfo->l1.dc_nsets * cpuinfo->l1.dc_linesize / PAGE_SIZE) *
+ cpuinfo->l1.dc_nways;
+ }
+
+ mips_picache_linesize = cpuinfo->l1.ic_linesize;
+ mips_pdcache_linesize = cpuinfo->l1.dc_linesize;
+
+ picache_size = cpuinfo->l1.ic_size;
+ picache_way_mask = cpuinfo->l1.ic_nways - 1;
+ pdcache_size = cpuinfo->l1.dc_size;
+ pdcache_way_mask = cpuinfo->l1.dc_nways - 1;
+
+#define CACHE_DEBUG
+#ifdef CACHE_DEBUG
+ printf("Cache info:\n");
+ if (cpuinfo->icache_virtual)
+ printf(" icache is virtual\n");
+ printf(" picache_stride = %d\n", picache_stride);
+ printf(" picache_loopcount = %d\n", picache_loopcount);
+ printf(" pdcache_stride = %d\n", pdcache_stride);
+ printf(" pdcache_loopcount = %d\n", pdcache_loopcount);
+#endif
+}
+
+void
+mipsNN_icache_sync_all_16(void)
+{
+ vm_offset_t va, eva;
+
+ va = MIPS_PHYS_TO_KSEG0(0);
+ eva = va + picache_size;
+
+ /*
+ * Since we're hitting the whole thing, we don't have to
+ * worry about the N different "ways".
+ */
+
+ mips_intern_dcache_wbinv_all();
+
+ while (va < eva) {
+ cache_r4k_op_32lines_16(va, CACHE_R4K_I|CACHEOP_R4K_INDEX_INV);
+ va += (32 * 16);
+ }
+
+ SYNC;
+}
+
+void
+mipsNN_icache_sync_all_32(void)
+{
+ vm_offset_t va, eva;
+
+ va = MIPS_PHYS_TO_KSEG0(0);
+ eva = va + picache_size;
+
+ /*
+ * Since we're hitting the whole thing, we don't have to
+ * worry about the N different "ways".
+ */
+
+ mips_intern_dcache_wbinv_all();
+
+ while (va < eva) {
+ cache_r4k_op_32lines_32(va, CACHE_R4K_I|CACHEOP_R4K_INDEX_INV);
+ va += (32 * 32);
+ }
+
+ SYNC;
+}
+
+void
+mipsNN_icache_sync_range_16(vm_offset_t va, vm_size_t size)
+{
+ vm_offset_t eva;
+
+ eva = round_line16(va + size);
+ va = trunc_line16(va);
+
+ mips_intern_dcache_wb_range(va, (eva - va));
+
+ while ((eva - va) >= (32 * 16)) {
+ cache_r4k_op_32lines_16(va, CACHE_R4K_I|CACHEOP_R4K_HIT_INV);
+ va += (32 * 16);
+ }
+
+ while (va < eva) {
+ cache_op_r4k_line(va, CACHE_R4K_I|CACHEOP_R4K_HIT_INV);
+ va += 16;
+ }
+
+ SYNC;
+}
+
+void
+mipsNN_icache_sync_range_32(vm_offset_t va, vm_size_t size)
+{
+ vm_offset_t eva;
+
+ eva = round_line32(va + size);
+ va = trunc_line32(va);
+
+ mips_intern_dcache_wb_range(va, (eva - va));
+
+ while ((eva - va) >= (32 * 32)) {
+ cache_r4k_op_32lines_32(va, CACHE_R4K_I|CACHEOP_R4K_HIT_INV);
+ va += (32 * 32);
+ }
+
+ while (va < eva) {
+ cache_op_r4k_line(va, CACHE_R4K_I|CACHEOP_R4K_HIT_INV);
+ va += 32;
+ }
+
+ SYNC;
+}
+
+void
+mipsNN_icache_sync_range_index_16(vm_offset_t va, vm_size_t size)
+{
+ vm_offset_t eva, tmpva;
+ int i, stride, loopcount;
+
+ /*
+ * Since we're doing Index ops, we expect to not be able
+ * to access the address we've been given. So, get the
+ * bits that determine the cache index, and make a KSEG0
+ * address out of them.
+ */
+ va = MIPS_PHYS_TO_KSEG0(va & picache_way_mask);
+
+ eva = round_line16(va + size);
+ va = trunc_line16(va);
+
+ /*
+ * GCC generates better code in the loops if we reference local
+ * copies of these global variables.
+ */
+ stride = picache_stride;
+ loopcount = picache_loopcount;
+
+ mips_intern_dcache_wbinv_range_index(va, (eva - va));
+
+ while ((eva - va) >= (8 * 16)) {
+ tmpva = va;
+ for (i = 0; i < loopcount; i++, tmpva += stride)
+ cache_r4k_op_8lines_16(tmpva,
+ CACHE_R4K_I|CACHEOP_R4K_INDEX_INV);
+ va += 8 * 16;
+ }
+
+ while (va < eva) {
+ tmpva = va;
+ for (i = 0; i < loopcount; i++, tmpva += stride)
+ cache_op_r4k_line(tmpva,
+ CACHE_R4K_I|CACHEOP_R4K_INDEX_INV);
+ va += 16;
+ }
+}
+
+void
+mipsNN_icache_sync_range_index_32(vm_offset_t va, vm_size_t size)
+{
+ vm_offset_t eva, tmpva;
+ int i, stride, loopcount;
+
+ /*
+ * Since we're doing Index ops, we expect to not be able
+ * to access the address we've been given. So, get the
+ * bits that determine the cache index, and make a KSEG0
+ * address out of them.
+ */
+ va = MIPS_PHYS_TO_KSEG0(va & picache_way_mask);
+
+ eva = round_line32(va + size);
+ va = trunc_line32(va);
+
+ /*
+ * GCC generates better code in the loops if we reference local
+ * copies of these global variables.
+ */
+ stride = picache_stride;
+ loopcount = picache_loopcount;
+
+ mips_intern_dcache_wbinv_range_index(va, (eva - va));
+
+ while ((eva - va) >= (8 * 32)) {
+ tmpva = va;
+ for (i = 0; i < loopcount; i++, tmpva += stride)
+ cache_r4k_op_8lines_32(tmpva,
+ CACHE_R4K_I|CACHEOP_R4K_INDEX_INV);
+ va += 8 * 32;
+ }
+
+ while (va < eva) {
+ tmpva = va;
+ for (i = 0; i < loopcount; i++, tmpva += stride)
+ cache_op_r4k_line(tmpva,
+ CACHE_R4K_I|CACHEOP_R4K_INDEX_INV);
+ va += 32;
+ }
+}
+
+void
+mipsNN_pdcache_wbinv_all_16(void)
+{
+ vm_offset_t va, eva;
+
+ va = MIPS_PHYS_TO_KSEG0(0);
+ eva = va + pdcache_size;
+
+ /*
+ * Since we're hitting the whole thing, we don't have to
+ * worry about the N different "ways".
+ */
+
+ while (va < eva) {
+ cache_r4k_op_32lines_16(va,
+ CACHE_R4K_D|CACHEOP_R4K_INDEX_WB_INV);
+ va += (32 * 16);
+ }
+
+ SYNC;
+}
+
+void
+mipsNN_pdcache_wbinv_all_32(void)
+{
+ vm_offset_t va, eva;
+
+ va = MIPS_PHYS_TO_KSEG0(0);
+ eva = va + pdcache_size;
+
+ /*
+ * Since we're hitting the whole thing, we don't have to
+ * worry about the N different "ways".
+ */
+
+ while (va < eva) {
+ cache_r4k_op_32lines_32(va,
+ CACHE_R4K_D|CACHEOP_R4K_INDEX_WB_INV);
+ va += (32 * 32);
+ }
+
+ SYNC;
+}
+
+void
+mipsNN_pdcache_wbinv_range_16(vm_offset_t va, vm_size_t size)
+{
+ vm_offset_t eva;
+
+ eva = round_line16(va + size);
+ va = trunc_line16(va);
+
+ while ((eva - va) >= (32 * 16)) {
+ cache_r4k_op_32lines_16(va,
+ CACHE_R4K_D|CACHEOP_R4K_HIT_WB_INV);
+ va += (32 * 16);
+ }
+
+ while (va < eva) {
+ cache_op_r4k_line(va, CACHE_R4K_D|CACHEOP_R4K_HIT_WB_INV);
+ va += 16;
+ }
+
+ SYNC;
+}
+
+void
+mipsNN_pdcache_wbinv_range_32(vm_offset_t va, vm_size_t size)
+{
+ vm_offset_t eva;
+
+ eva = round_line32(va + size);
+ va = trunc_line32(va);
+
+ while ((eva - va) >= (32 * 32)) {
+ cache_r4k_op_32lines_32(va,
+ CACHE_R4K_D|CACHEOP_R4K_HIT_WB_INV);
+ va += (32 * 32);
+ }
+
+ while (va < eva) {
+ cache_op_r4k_line(va, CACHE_R4K_D|CACHEOP_R4K_HIT_WB_INV);
+ va += 32;
+ }
+
+ SYNC;
+}
+
+void
+mipsNN_pdcache_wbinv_range_index_16(vm_offset_t va, vm_size_t size)
+{
+ vm_offset_t eva, tmpva;
+ int i, stride, loopcount;
+
+ /*
+ * Since we're doing Index ops, we expect to not be able
+ * to access the address we've been given. So, get the
+ * bits that determine the cache index, and make a KSEG0
+ * address out of them.
+ */
+ va = MIPS_PHYS_TO_KSEG0(va & pdcache_way_mask);
+
+ eva = round_line16(va + size);
+ va = trunc_line16(va);
+
+ /*
+ * GCC generates better code in the loops if we reference local
+ * copies of these global variables.
+ */
+ stride = pdcache_stride;
+ loopcount = pdcache_loopcount;
+
+ while ((eva - va) >= (8 * 16)) {
+ tmpva = va;
+ for (i = 0; i < loopcount; i++, tmpva += stride)
+ cache_r4k_op_8lines_16(tmpva,
+ CACHE_R4K_D|CACHEOP_R4K_INDEX_WB_INV);
+ va += 8 * 16;
+ }
+
+ while (va < eva) {
+ tmpva = va;
+ for (i = 0; i < loopcount; i++, tmpva += stride)
+ cache_op_r4k_line(tmpva,
+ CACHE_R4K_D|CACHEOP_R4K_INDEX_WB_INV);
+ va += 16;
+ }
+}
+
+void
+mipsNN_pdcache_wbinv_range_index_32(vm_offset_t va, vm_size_t size)
+{
+ vm_offset_t eva, tmpva;
+ int i, stride, loopcount;
+
+ /*
+ * Since we're doing Index ops, we expect to not be able
+ * to access the address we've been given. So, get the
+ * bits that determine the cache index, and make a KSEG0
+ * address out of them.
+ */
+ va = MIPS_PHYS_TO_KSEG0(va & pdcache_way_mask);
+
+ eva = round_line32(va + size);
+ va = trunc_line32(va);
+
+ /*
+ * GCC generates better code in the loops if we reference local
+ * copies of these global variables.
+ */
+ stride = pdcache_stride;
+ loopcount = pdcache_loopcount;
+
+ while ((eva - va) >= (8 * 32)) {
+ tmpva = va;
+ for (i = 0; i < loopcount; i++, tmpva += stride)
+ cache_r4k_op_8lines_32(tmpva,
+ CACHE_R4K_D|CACHEOP_R4K_INDEX_WB_INV);
+ va += 8 * 32;
+ }
+
+ while (va < eva) {
+ tmpva = va;
+ for (i = 0; i < loopcount; i++, tmpva += stride)
+ cache_op_r4k_line(tmpva,
+ CACHE_R4K_D|CACHEOP_R4K_INDEX_WB_INV);
+ va += 32;
+ }
+}
+
+void
+mipsNN_pdcache_inv_range_16(vm_offset_t va, vm_size_t size)
+{
+ vm_offset_t eva;
+
+ eva = round_line16(va + size);
+ va = trunc_line16(va);
+
+ while ((eva - va) >= (32 * 16)) {
+ cache_r4k_op_32lines_16(va, CACHE_R4K_D|CACHEOP_R4K_HIT_INV);
+ va += (32 * 16);
+ }
+
+ while (va < eva) {
+ cache_op_r4k_line(va, CACHE_R4K_D|CACHEOP_R4K_HIT_INV);
+ va += 16;
+ }
+
+ SYNC;
+}
+
+void
+mipsNN_pdcache_inv_range_32(vm_offset_t va, vm_size_t size)
+{
+ vm_offset_t eva;
+
+ eva = round_line32(va + size);
+ va = trunc_line32(va);
+
+ while ((eva - va) >= (32 * 32)) {
+ cache_r4k_op_32lines_32(va, CACHE_R4K_D|CACHEOP_R4K_HIT_INV);
+ va += (32 * 32);
+ }
+
+ while (va < eva) {
+ cache_op_r4k_line(va, CACHE_R4K_D|CACHEOP_R4K_HIT_INV);
+ va += 32;
+ }
+
+ SYNC;
+}
+
+void
+mipsNN_pdcache_wb_range_16(vm_offset_t va, vm_size_t size)
+{
+ vm_offset_t eva;
+
+ eva = round_line16(va + size);
+ va = trunc_line16(va);
+
+ while ((eva - va) >= (32 * 16)) {
+ cache_r4k_op_32lines_16(va, CACHE_R4K_D|CACHEOP_R4K_HIT_WB);
+ va += (32 * 16);
+ }
+
+ while (va < eva) {
+ cache_op_r4k_line(va, CACHE_R4K_D|CACHEOP_R4K_HIT_WB);
+ va += 16;
+ }
+
+ SYNC;
+}
+
+void
+mipsNN_pdcache_wb_range_32(vm_offset_t va, vm_size_t size)
+{
+ vm_offset_t eva;
+
+ eva = round_line32(va + size);
+ va = trunc_line32(va);
+
+ while ((eva - va) >= (32 * 32)) {
+ cache_r4k_op_32lines_32(va, CACHE_R4K_D|CACHEOP_R4K_HIT_WB);
+ va += (32 * 32);
+ }
+
+ while (va < eva) {
+ cache_op_r4k_line(va, CACHE_R4K_D|CACHEOP_R4K_HIT_WB);
+ va += 32;
+ }
+
+ SYNC;
+}
+
+
+#ifdef CPU_CNMIPS
+
+void
+mipsNN_icache_sync_all_128(void)
+{
+ SYNCI
+}
+
+void
+mipsNN_icache_sync_range_128(vm_offset_t va, vm_size_t size)
+{
+ SYNC;
+}
+
+void
+mipsNN_icache_sync_range_index_128(vm_offset_t va, vm_size_t size)
+{
+}
+
+
+void
+mipsNN_pdcache_wbinv_all_128(void)
+{
+}
+
+
+void
+mipsNN_pdcache_wbinv_range_128(vm_offset_t va, vm_size_t size)
+{
+ SYNC;
+}
+
+void
+mipsNN_pdcache_wbinv_range_index_128(vm_offset_t va, vm_size_t size)
+{
+}
+
+void
+mipsNN_pdcache_inv_range_128(vm_offset_t va, vm_size_t size)
+{
+}
+
+void
+mipsNN_pdcache_wb_range_128(vm_offset_t va, vm_size_t size)
+{
+ SYNC;
+}
+
+#endif
Property changes on: trunk/sys/mips/mips/cache_mipsNN.c
___________________________________________________________________
Added: svn:eol-style
## -0,0 +1 ##
+native
\ No newline at end of property
Added: svn:keywords
## -0,0 +1 ##
+MidnightBSD=%H
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+text/plain
\ No newline at end of property
Added: trunk/sys/mips/mips/cpu.c
===================================================================
--- trunk/sys/mips/mips/cpu.c (rev 0)
+++ trunk/sys/mips/mips/cpu.c 2018-05-26 21:55:02 UTC (rev 9987)
@@ -0,0 +1,437 @@
+/* $MidnightBSD$ */
+/*-
+ * Copyright (c) 2004 Juli Mallett. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ */
+
+#include <sys/cdefs.h>
+__FBSDID("$FreeBSD: stable/10/sys/mips/mips/cpu.c 261277 2014-01-29 22:01:42Z brooks $");
+
+#include <sys/param.h>
+#include <sys/kernel.h>
+#include <sys/module.h>
+#include <sys/stdint.h>
+
+#include <sys/bus.h>
+#include <sys/rman.h>
+#include <sys/sysctl.h>
+#include <sys/systm.h>
+
+#include <vm/vm.h>
+#include <vm/vm_page.h>
+
+#include <machine/cache.h>
+#include <machine/cpufunc.h>
+#include <machine/cpuinfo.h>
+#include <machine/cpuregs.h>
+#include <machine/intr_machdep.h>
+#include <machine/locore.h>
+#include <machine/pte.h>
+#include <machine/tlb.h>
+#include <machine/hwfunc.h>
+
+#if defined(CPU_CNMIPS)
+#include <contrib/octeon-sdk/cvmx.h>
+#include <contrib/octeon-sdk/octeon-model.h>
+#endif
+
+static void cpu_identify(void);
+
+struct mips_cpuinfo cpuinfo;
+
+/*
+ * Attempt to identify the MIPS CPU as much as possible.
+ *
+ * XXX: Assumes the CPU is MIPS{32,64}{,r2} compliant.
+ * XXX: For now, skip config register selections 2 and 3
+ * as we don't currently use L2/L3 cache or additional
+ * MIPS32 processor features.
+ */
+static void
+mips_get_identity(struct mips_cpuinfo *cpuinfo)
+{
+ u_int32_t prid;
+ u_int32_t cfg0;
+ u_int32_t cfg1;
+#if defined(CPU_CNMIPS)
+ u_int32_t cfg4;
+#endif
+ u_int32_t tmp;
+
+ memset(cpuinfo, 0, sizeof(struct mips_cpuinfo));
+
+ /* Read and store the PrID ID for CPU identification. */
+ prid = mips_rd_prid();
+ cpuinfo->cpu_vendor = MIPS_PRID_CID(prid);
+ cpuinfo->cpu_rev = MIPS_PRID_REV(prid);
+ cpuinfo->cpu_impl = MIPS_PRID_IMPL(prid);
+
+ /* Read config register selection 0 to learn TLB type. */
+ cfg0 = mips_rd_config();
+
+ cpuinfo->tlb_type =
+ ((cfg0 & MIPS_CONFIG0_MT_MASK) >> MIPS_CONFIG0_MT_SHIFT);
+ cpuinfo->icache_virtual = cfg0 & MIPS_CONFIG0_VI;
+
+ /* If config register selection 1 does not exist, exit. */
+ if (!(cfg0 & MIPS_CONFIG_CM))
+ return;
+
+ /* Learn TLB size and L1 cache geometry. */
+ cfg1 = mips_rd_config1();
+
+#if defined(CPU_NLM)
+ /* Account for Extended TLB entries in XLP */
+ tmp = mips_rd_config6();
+ cpuinfo->tlb_nentries = ((tmp >> 16) & 0xffff) + 1;
+#elif defined(BERI_LARGE_TLB)
+ /* Check if we support extended TLB entries and if so activate. */
+ tmp = mips_rd_config5();
+#define BERI_CP5_LTLB_SUPPORTED 0x1
+ if (tmp & BERI_CP5_LTLB_SUPPORTED) {
+ /* See how many extra TLB entries we have. */
+ tmp = mips_rd_config6();
+ cpuinfo->tlb_nentries = (tmp >> 16) + 1;
+ /* Activate the extended entries. */
+ mips_wr_config6(tmp|0x4);
+ } else
+#endif
+#if !defined(CPU_NLM)
+ cpuinfo->tlb_nentries =
+ ((cfg1 & MIPS_CONFIG1_TLBSZ_MASK) >> MIPS_CONFIG1_TLBSZ_SHIFT) + 1;
+#endif
+#if defined(CPU_CNMIPS)
+ /* Add extended TLB size information from config4. */
+ cfg4 = mips_rd_config4();
+ if ((cfg4 & MIPS_CONFIG4_MMUEXTDEF) == MIPS_CONFIG4_MMUEXTDEF_MMUSIZEEXT)
+ cpuinfo->tlb_nentries += (cfg4 & MIPS_CONFIG4_MMUSIZEEXT) * 0x40;
+#endif
+
+ /* L1 instruction cache. */
+#ifdef MIPS_DISABLE_L1_CACHE
+ cpuinfo->l1.ic_linesize = 0;
+#else
+ tmp = (cfg1 & MIPS_CONFIG1_IL_MASK) >> MIPS_CONFIG1_IL_SHIFT;
+ if (tmp != 0) {
+ cpuinfo->l1.ic_linesize = 1 << (tmp + 1);
+ cpuinfo->l1.ic_nways = (((cfg1 & MIPS_CONFIG1_IA_MASK) >> MIPS_CONFIG1_IA_SHIFT)) + 1;
+ cpuinfo->l1.ic_nsets =
+ 1 << (((cfg1 & MIPS_CONFIG1_IS_MASK) >> MIPS_CONFIG1_IS_SHIFT) + 6);
+ }
+#endif
+
+ /* L1 data cache. */
+#ifdef MIPS_DISABLE_L1_CACHE
+ cpuinfo->l1.dc_linesize = 0;
+#else
+#ifndef CPU_CNMIPS
+ tmp = (cfg1 & MIPS_CONFIG1_DL_MASK) >> MIPS_CONFIG1_DL_SHIFT;
+ if (tmp != 0) {
+ cpuinfo->l1.dc_linesize = 1 << (tmp + 1);
+ cpuinfo->l1.dc_nways =
+ (((cfg1 & MIPS_CONFIG1_DA_MASK) >> MIPS_CONFIG1_DA_SHIFT)) + 1;
+ cpuinfo->l1.dc_nsets =
+ 1 << (((cfg1 & MIPS_CONFIG1_DS_MASK) >> MIPS_CONFIG1_DS_SHIFT) + 6);
+ }
+#else
+ /*
+ * Some Octeon cache configuration parameters are by model family, not
+ * config1.
+ */
+ if (OCTEON_IS_MODEL(OCTEON_CN3XXX)) {
+ /* Octeon and Octeon XL. */
+ cpuinfo->l1.dc_nsets = 1;
+ cpuinfo->l1.dc_nways = 64;
+ } else if (OCTEON_IS_MODEL(OCTEON_CN5XXX)) {
+ /* Octeon Plus. */
+ cpuinfo->l1.dc_nsets = 2;
+ cpuinfo->l1.dc_nways = 64;
+ } else if (OCTEON_IS_MODEL(OCTEON_CN6XXX)) {
+ /* Octeon II. */
+ cpuinfo->l1.dc_nsets = 8;
+ cpuinfo->l1.dc_nways = 32;
+
+ cpuinfo->l1.ic_nsets = 8;
+ cpuinfo->l1.ic_nways = 37;
+ } else {
+ panic("%s: unsupported Cavium Networks CPU.", __func__);
+ }
+
+ /* All Octeon models use 128 byte line size. */
+ cpuinfo->l1.dc_linesize = 128;
+#endif
+#endif
+
+ cpuinfo->l1.ic_size = cpuinfo->l1.ic_linesize
+ * cpuinfo->l1.ic_nsets * cpuinfo->l1.ic_nways;
+ cpuinfo->l1.dc_size = cpuinfo->l1.dc_linesize
+ * cpuinfo->l1.dc_nsets * cpuinfo->l1.dc_nways;
+}
+
+void
+mips_cpu_init(void)
+{
+ platform_cpu_init();
+ mips_get_identity(&cpuinfo);
+ num_tlbentries = cpuinfo.tlb_nentries;
+ mips_wr_wired(0);
+ tlb_invalidate_all();
+ mips_wr_wired(VMWIRED_ENTRIES);
+ mips_config_cache(&cpuinfo);
+ mips_vector_init();
+
+ mips_icache_sync_all();
+ mips_dcache_wbinv_all();
+ /* Print some info about CPU */
+ cpu_identify();
+}
+
+static void
+cpu_identify(void)
+{
+ uint32_t cfg0, cfg1, cfg2, cfg3;
+ printf("cpu%d: ", 0); /* XXX per-cpu */
+ switch (cpuinfo.cpu_vendor) {
+ case MIPS_PRID_CID_MTI:
+ printf("MIPS Technologies");
+ break;
+ case MIPS_PRID_CID_BROADCOM:
+ case MIPS_PRID_CID_SIBYTE:
+ printf("Broadcom");
+ break;
+ case MIPS_PRID_CID_ALCHEMY:
+ printf("AMD");
+ break;
+ case MIPS_PRID_CID_SANDCRAFT:
+ printf("Sandcraft");
+ break;
+ case MIPS_PRID_CID_PHILIPS:
+ printf("Philips");
+ break;
+ case MIPS_PRID_CID_TOSHIBA:
+ printf("Toshiba");
+ break;
+ case MIPS_PRID_CID_LSI:
+ printf("LSI");
+ break;
+ case MIPS_PRID_CID_LEXRA:
+ printf("Lexra");
+ break;
+ case MIPS_PRID_CID_RMI:
+ printf("RMI");
+ break;
+ case MIPS_PRID_CID_CAVIUM:
+ printf("Cavium");
+ break;
+ case MIPS_PRID_CID_PREHISTORIC:
+ default:
+ printf("Unknown cid %#x", cpuinfo.cpu_vendor);
+ break;
+ }
+ printf(" processor v%d.%d\n", cpuinfo.cpu_rev, cpuinfo.cpu_impl);
+
+ printf(" MMU: ");
+ if (cpuinfo.tlb_type == MIPS_MMU_NONE) {
+ printf("none present\n");
+ } else {
+ if (cpuinfo.tlb_type == MIPS_MMU_TLB) {
+ printf("Standard TLB");
+ } else if (cpuinfo.tlb_type == MIPS_MMU_BAT) {
+ printf("Standard BAT");
+ } else if (cpuinfo.tlb_type == MIPS_MMU_FIXED) {
+ printf("Fixed mapping");
+ }
+ printf(", %d entries\n", cpuinfo.tlb_nentries);
+ }
+
+ printf(" L1 i-cache: ");
+ if (cpuinfo.l1.ic_linesize == 0) {
+ printf("disabled");
+ } else {
+ if (cpuinfo.l1.ic_nways == 1) {
+ printf("direct-mapped with");
+ } else {
+ printf ("%d ways of", cpuinfo.l1.ic_nways);
+ }
+ printf(" %d sets, %d bytes per line\n",
+ cpuinfo.l1.ic_nsets, cpuinfo.l1.ic_linesize);
+ }
+
+ printf(" L1 d-cache: ");
+ if (cpuinfo.l1.dc_linesize == 0) {
+ printf("disabled");
+ } else {
+ if (cpuinfo.l1.dc_nways == 1) {
+ printf("direct-mapped with");
+ } else {
+ printf ("%d ways of", cpuinfo.l1.dc_nways);
+ }
+ printf(" %d sets, %d bytes per line\n",
+ cpuinfo.l1.dc_nsets, cpuinfo.l1.dc_linesize);
+ }
+
+ cfg0 = mips_rd_config();
+ /* If config register selection 1 does not exist, exit. */
+ if (!(cfg0 & MIPS_CONFIG_CM))
+ return;
+
+ cfg1 = mips_rd_config1();
+ printf(" Config1=0x%b\n", cfg1,
+ "\20\7COP2\6MDMX\5PerfCount\4WatchRegs\3MIPS16\2EJTAG\1FPU");
+
+ /* If config register selection 2 does not exist, exit. */
+ if (!(cfg1 & MIPS_CONFIG_CM))
+ return;
+ cfg2 = mips_rd_config2();
+ /*
+ * Config2 contains no useful information other then Config3
+ * existence flag
+ */
+
+ /* If config register selection 3 does not exist, exit. */
+ if (!(cfg2 & MIPS_CONFIG_CM))
+ return;
+ cfg3 = mips_rd_config3();
+
+ /* Print Config3 if it contains any useful info */
+ if (cfg3 & ~(0x80000000))
+ printf(" Config3=0x%b\n", cfg3, "\20\2SmartMIPS\1TraceLogic");
+}
+
+static struct rman cpu_hardirq_rman;
+
+static devclass_t cpu_devclass;
+
+/*
+ * Device methods
+ */
+static int cpu_probe(device_t);
+static int cpu_attach(device_t);
+static struct resource *cpu_alloc_resource(device_t, device_t, int, int *,
+ u_long, u_long, u_long, u_int);
+static int cpu_setup_intr(device_t, device_t, struct resource *, int,
+ driver_filter_t *f, driver_intr_t *, void *,
+ void **);
+
+static device_method_t cpu_methods[] = {
+ /* Device interface */
+ DEVMETHOD(device_probe, cpu_probe),
+ DEVMETHOD(device_attach, cpu_attach),
+ DEVMETHOD(device_detach, bus_generic_detach),
+ DEVMETHOD(device_shutdown, bus_generic_shutdown),
+
+ /* Bus interface */
+ DEVMETHOD(bus_alloc_resource, cpu_alloc_resource),
+ DEVMETHOD(bus_setup_intr, cpu_setup_intr),
+ DEVMETHOD(bus_teardown_intr, bus_generic_teardown_intr),
+
+ { 0, 0 }
+};
+
+static driver_t cpu_driver = {
+ "cpu", cpu_methods, 1
+};
+
+static int
+cpu_probe(device_t dev)
+{
+ return (0);
+}
+
+static int
+cpu_attach(device_t dev)
+{
+ int error;
+#ifdef notyet
+ device_t clock;
+#endif
+
+ cpu_hardirq_rman.rm_start = 0;
+ cpu_hardirq_rman.rm_end = 5;
+ cpu_hardirq_rman.rm_type = RMAN_ARRAY;
+ cpu_hardirq_rman.rm_descr = "CPU Hard Interrupts";
+
+ error = rman_init(&cpu_hardirq_rman);
+ if (error != 0) {
+ device_printf(dev, "failed to initialize irq resources\n");
+ return (error);
+ }
+ /* XXX rman_manage_all. */
+ error = rman_manage_region(&cpu_hardirq_rman,
+ cpu_hardirq_rman.rm_start,
+ cpu_hardirq_rman.rm_end);
+ if (error != 0) {
+ device_printf(dev, "failed to manage irq resources\n");
+ return (error);
+ }
+
+ if (device_get_unit(dev) != 0)
+ panic("can't attach more cpus");
+ device_set_desc(dev, "MIPS32 processor");
+
+#ifdef notyet
+ clock = device_add_child(dev, "clock", device_get_unit(dev));
+ if (clock == NULL)
+ device_printf(dev, "clock failed to attach");
+#endif
+
+ return (bus_generic_attach(dev));
+}
+
+static struct resource *
+cpu_alloc_resource(device_t dev, device_t child, int type, int *rid,
+ u_long start, u_long end, u_long count, u_int flags)
+{
+ struct resource *res;
+
+ if (type != SYS_RES_IRQ)
+ return (NULL);
+ res = rman_reserve_resource(&cpu_hardirq_rman, start, end, count, 0,
+ child);
+ return (res);
+}
+
+static int
+cpu_setup_intr(device_t dev, device_t child, struct resource *res, int flags,
+ driver_filter_t *filt, driver_intr_t *handler, void *arg,
+ void **cookiep)
+{
+ int error;
+ int intr;
+
+ error = rman_activate_resource(res);
+ if (error != 0) {
+ device_printf(child, "could not activate irq\n");
+ return (error);
+ }
+
+ intr = rman_get_start(res);
+
+ cpu_establish_hardintr(device_get_nameunit(child), filt, handler, arg,
+ intr, flags, cookiep);
+ device_printf(child, "established CPU interrupt %d\n", intr);
+ return (0);
+}
+
+DRIVER_MODULE(cpu, root, cpu_driver, cpu_devclass, 0, 0);
Property changes on: trunk/sys/mips/mips/cpu.c
___________________________________________________________________
Added: svn:eol-style
## -0,0 +1 ##
+native
\ No newline at end of property
Added: svn:keywords
## -0,0 +1 ##
+MidnightBSD=%H
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+text/plain
\ No newline at end of property
Added: trunk/sys/mips/mips/db_disasm.c
===================================================================
--- trunk/sys/mips/mips/db_disasm.c (rev 0)
+++ trunk/sys/mips/mips/db_disasm.c 2018-05-26 21:55:02 UTC (rev 9987)
@@ -0,0 +1,394 @@
+/* $MidnightBSD$ */
+/* $OpenBSD: db_disasm.c,v 1.1 1998/03/16 09:03:24 pefo Exp $ */
+/*-
+ * Copyright (c) 1991, 1993
+ * The Regents of the University of California. All rights reserved.
+ *
+ * This code is derived from software contributed to Berkeley by
+ * Ralph Campbell.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * 3. All advertising materials mentioning features or use of this software
+ * must display the following acknowledgement:
+ * This product includes software developed by the University of
+ * California, Berkeley and its contributors.
+ * 4. Neither the name of the University nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ * from: @(#)kadb.c 8.1 (Berkeley) 6/10/93
+ * Id: db_disasm.c,v 1.1 1998/03/16 09:03:24 pefo Exp
+ * JNPR: db_disasm.c,v 1.1 2006/08/07 05:38:57 katta
+ */
+
+#include <sys/cdefs.h>
+__FBSDID("$FreeBSD: stable/10/sys/mips/mips/db_disasm.c 229798 2012-01-08 00:34:39Z gonzo $");
+
+#include <sys/param.h>
+#include <vm/vm_param.h>
+#include <vm/vm.h>
+#include <vm/pmap.h>
+#include <sys/systm.h>
+
+#include <machine/mips_opcode.h>
+#include <machine/db_machdep.h>
+#include <ddb/ddb.h>
+#include <ddb/db_output.h>
+
+static char *op_name[64] = {
+/* 0 */ "spec", "bcond","j", "jal", "beq", "bne", "blez", "bgtz",
+/* 8 */ "addi", "addiu","slti", "sltiu","andi", "ori", "xori", "lui",
+/*16 */ "cop0", "cop1", "cop2", "cop3", "beql", "bnel", "blezl","bgtzl",
+/*24 */ "daddi","daddiu","ldl", "ldr", "op34", "op35", "op36", "op37",
+/*32 */ "lb", "lh", "lwl", "lw", "lbu", "lhu", "lwr", "lwu",
+/*40 */ "sb", "sh", "swl", "sw", "sdl", "sdr", "swr", "cache",
+/*48 */ "ll", "lwc1", "lwc2", "lwc3", "lld", "ldc1", "ldc2", "ld",
+/*56 */ "sc", "swc1", "swc2", "swc3", "scd", "sdc1", "sdc2", "sd"
+};
+
+static char *spec_name[64] = {
+/* 0 */ "sll", "spec01","srl", "sra", "sllv", "spec05","srlv","srav",
+/* 8 */ "jr", "jalr", "spec12","spec13","syscall","break","spec16","sync",
+/*16 */ "mfhi", "mthi", "mflo", "mtlo", "dsllv","spec25","dsrlv","dsrav",
+/*24 */ "mult", "multu","div", "divu", "dmult","dmultu","ddiv","ddivu",
+/*32 */ "add", "addu", "sub", "subu", "and", "or", "xor", "nor",
+/*40 */ "spec50","spec51","slt","sltu", "dadd","daddu","dsub","dsubu",
+/*48 */ "tge","tgeu","tlt","tltu","teq","spec65","tne","spec67",
+/*56 */ "dsll","spec71","dsrl","dsra","dsll32","spec75","dsrl32","dsra32"
+};
+
+static char *bcond_name[32] = {
+/* 0 */ "bltz", "bgez", "bltzl", "bgezl", "?", "?", "?", "?",
+/* 8 */ "tgei", "tgeiu", "tlti", "tltiu", "teqi", "?", "tnei", "?",
+/*16 */ "bltzal", "bgezal", "bltzall", "bgezall", "?", "?", "?", "?",
+/*24 */ "?", "?", "?", "?", "?", "?", "?", "?",
+};
+
+static char *cop1_name[64] = {
+/* 0 */ "fadd", "fsub", "fmpy", "fdiv", "fsqrt","fabs", "fmov", "fneg",
+/* 8 */ "fop08","fop09","fop0a","fop0b","fop0c","fop0d","fop0e","fop0f",
+/*16 */ "fop10","fop11","fop12","fop13","fop14","fop15","fop16","fop17",
+/*24 */ "fop18","fop19","fop1a","fop1b","fop1c","fop1d","fop1e","fop1f",
+/*32 */ "fcvts","fcvtd","fcvte","fop23","fcvtw","fop25","fop26","fop27",
+/*40 */ "fop28","fop29","fop2a","fop2b","fop2c","fop2d","fop2e","fop2f",
+/*48 */ "fcmp.f","fcmp.un","fcmp.eq","fcmp.ueq","fcmp.olt","fcmp.ult",
+ "fcmp.ole","fcmp.ule",
+/*56 */ "fcmp.sf","fcmp.ngle","fcmp.seq","fcmp.ngl","fcmp.lt","fcmp.nge",
+ "fcmp.le","fcmp.ngt"
+};
+
+static char *fmt_name[16] = {
+ "s", "d", "e", "fmt3",
+ "w", "fmt5", "fmt6", "fmt7",
+ "fmt8", "fmt9", "fmta", "fmtb",
+ "fmtc", "fmtd", "fmte", "fmtf"
+};
+
+static char *reg_name[32] = {
+ "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3",
+ "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7",
+ "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
+ "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra"
+};
+
+static char *c0_opname[64] = {
+ "c0op00","tlbr", "tlbwi", "c0op03","c0op04","c0op05","tlbwr", "c0op07",
+ "tlbp", "c0op11","c0op12","c0op13","c0op14","c0op15","c0op16","c0op17",
+ "rfe", "c0op21","c0op22","c0op23","c0op24","c0op25","c0op26","c0op27",
+ "eret","c0op31","c0op32","c0op33","c0op34","c0op35","c0op36","c0op37",
+ "c0op40","c0op41","c0op42","c0op43","c0op44","c0op45","c0op46","c0op47",
+ "c0op50","c0op51","c0op52","c0op53","c0op54","c0op55","c0op56","c0op57",
+ "c0op60","c0op61","c0op62","c0op63","c0op64","c0op65","c0op66","c0op67",
+ "c0op70","c0op71","c0op72","c0op73","c0op74","c0op75","c0op77","c0op77",
+};
+
+static char *c0_reg[32] = {
+ "index","random","tlblo0","tlblo1","context","tlbmask","wired","c0r7",
+ "badvaddr","count","tlbhi","c0r11","sr","cause","epc", "prid",
+ "config","lladr","watchlo","watchhi","xcontext","c0r21","c0r22","c0r23",
+ "c0r24","c0r25","ecc","cacheerr","taglo","taghi","errepc","c0r31"
+};
+
+static int md_printins(int ins, int mdbdot);
+
+db_addr_t
+db_disasm(db_addr_t loc, boolean_t altfmt)
+
+{
+ int ins;
+
+ if (vtophys((vm_offset_t)loc)) {
+ db_read_bytes((vm_offset_t)loc, (size_t)sizeof(int),
+ (char *)&ins);
+ md_printins(ins, loc);
+ }
+
+ return (loc + sizeof(int));
+}
+
+/* ARGSUSED */
+static int
+md_printins(int ins, int mdbdot)
+{
+ InstFmt i;
+ int delay = 0;
+
+ i.word = ins;
+
+ switch (i.JType.op) {
+ case OP_SPECIAL:
+ if (i.word == 0) {
+ db_printf("nop");
+ break;
+ }
+ if (i.RType.func == OP_ADDU && i.RType.rt == 0) {
+ db_printf("move\t%s,%s",
+ reg_name[i.RType.rd], reg_name[i.RType.rs]);
+ break;
+ }
+ db_printf("%s", spec_name[i.RType.func]);
+ switch (i.RType.func) {
+ case OP_SLL:
+ case OP_SRL:
+ case OP_SRA:
+ case OP_DSLL:
+ case OP_DSRL:
+ case OP_DSRA:
+ case OP_DSLL32:
+ case OP_DSRL32:
+ case OP_DSRA32:
+ db_printf("\t%s,%s,%d", reg_name[i.RType.rd],
+ reg_name[i.RType.rt], i.RType.shamt);
+ break;
+
+ case OP_SLLV:
+ case OP_SRLV:
+ case OP_SRAV:
+ case OP_DSLLV:
+ case OP_DSRLV:
+ case OP_DSRAV:
+ db_printf("\t%s,%s,%s", reg_name[i.RType.rd],
+ reg_name[i.RType.rt], reg_name[i.RType.rs]);
+ break;
+
+ case OP_MFHI:
+ case OP_MFLO:
+ db_printf("\t%s", reg_name[i.RType.rd]);
+ break;
+
+ case OP_JR:
+ case OP_JALR:
+ delay = 1;
+ /* FALLTHROUGH */
+ case OP_MTLO:
+ case OP_MTHI:
+ db_printf("\t%s", reg_name[i.RType.rs]);
+ break;
+
+ case OP_MULT:
+ case OP_MULTU:
+ case OP_DMULT:
+ case OP_DMULTU:
+ case OP_DIV:
+ case OP_DIVU:
+ case OP_DDIV:
+ case OP_DDIVU:
+ db_printf("\t%s,%s",
+ reg_name[i.RType.rs], reg_name[i.RType.rt]);
+ break;
+
+ case OP_SYSCALL:
+ case OP_SYNC:
+ break;
+
+ case OP_BREAK:
+ db_printf("\t%d", (i.RType.rs << 5) | i.RType.rt);
+ break;
+
+ default:
+ db_printf("\t%s,%s,%s", reg_name[i.RType.rd],
+ reg_name[i.RType.rs], reg_name[i.RType.rt]);
+ };
+ break;
+
+ case OP_BCOND:
+ db_printf("%s\t%s,", bcond_name[i.IType.rt],
+ reg_name[i.IType.rs]);
+ goto pr_displ;
+
+ case OP_BLEZ:
+ case OP_BLEZL:
+ case OP_BGTZ:
+ case OP_BGTZL:
+ db_printf("%s\t%s,", op_name[i.IType.op],
+ reg_name[i.IType.rs]);
+ goto pr_displ;
+
+ case OP_BEQ:
+ case OP_BEQL:
+ if (i.IType.rs == 0 && i.IType.rt == 0) {
+ db_printf("b\t");
+ goto pr_displ;
+ }
+ /* FALLTHROUGH */
+ case OP_BNE:
+ case OP_BNEL:
+ db_printf("%s\t%s,%s,", op_name[i.IType.op],
+ reg_name[i.IType.rs], reg_name[i.IType.rt]);
+ pr_displ:
+ delay = 1;
+ db_printf("0x%08x", mdbdot + 4 + ((short)i.IType.imm << 2));
+ break;
+
+ case OP_COP0:
+ switch (i.RType.rs) {
+ case OP_BCx:
+ case OP_BCy:
+ db_printf("bc0%c\t",
+ "ft"[i.RType.rt & COPz_BC_TF_MASK]);
+ goto pr_displ;
+
+ case OP_MT:
+ db_printf("mtc0\t%s,%s",
+ reg_name[i.RType.rt], c0_reg[i.RType.rd]);
+ break;
+
+ case OP_DMT:
+ db_printf("dmtc0\t%s,%s",
+ reg_name[i.RType.rt], c0_reg[i.RType.rd]);
+ break;
+
+ case OP_MF:
+ db_printf("mfc0\t%s,%s",
+ reg_name[i.RType.rt], c0_reg[i.RType.rd]);
+ break;
+
+ case OP_DMF:
+ db_printf("dmfc0\t%s,%s",
+ reg_name[i.RType.rt], c0_reg[i.RType.rd]);
+ break;
+
+ default:
+ db_printf("%s", c0_opname[i.FRType.func]);
+ };
+ break;
+
+ case OP_COP1:
+ switch (i.RType.rs) {
+ case OP_BCx:
+ case OP_BCy:
+ db_printf("bc1%c\t",
+ "ft"[i.RType.rt & COPz_BC_TF_MASK]);
+ goto pr_displ;
+
+ case OP_MT:
+ db_printf("mtc1\t%s,f%d",
+ reg_name[i.RType.rt], i.RType.rd);
+ break;
+
+ case OP_MF:
+ db_printf("mfc1\t%s,f%d",
+ reg_name[i.RType.rt], i.RType.rd);
+ break;
+
+ case OP_CT:
+ db_printf("ctc1\t%s,f%d",
+ reg_name[i.RType.rt], i.RType.rd);
+ break;
+
+ case OP_CF:
+ db_printf("cfc1\t%s,f%d",
+ reg_name[i.RType.rt], i.RType.rd);
+ break;
+
+ default:
+ db_printf("%s.%s\tf%d,f%d,f%d",
+ cop1_name[i.FRType.func], fmt_name[i.FRType.fmt],
+ i.FRType.fd, i.FRType.fs, i.FRType.ft);
+ };
+ break;
+
+ case OP_J:
+ case OP_JAL:
+ db_printf("%s\t", op_name[i.JType.op]);
+ db_printf("0x%8x",(mdbdot & 0xF0000000) | (i.JType.target << 2));
+ delay = 1;
+ break;
+
+ case OP_LWC1:
+ case OP_SWC1:
+ db_printf("%s\tf%d,", op_name[i.IType.op], i.IType.rt);
+ goto loadstore;
+
+ case OP_LB:
+ case OP_LH:
+ case OP_LW:
+ case OP_LD:
+ case OP_LBU:
+ case OP_LHU:
+ case OP_LWU:
+ case OP_SB:
+ case OP_SH:
+ case OP_SW:
+ case OP_SD:
+ db_printf("%s\t%s,", op_name[i.IType.op],
+ reg_name[i.IType.rt]);
+ loadstore:
+ db_printf("%d(%s)", (short)i.IType.imm, reg_name[i.IType.rs]);
+ break;
+
+ case OP_ORI:
+ case OP_XORI:
+ if (i.IType.rs == 0) {
+ db_printf("li\t%s,0x%x",
+ reg_name[i.IType.rt], i.IType.imm);
+ break;
+ }
+ /* FALLTHROUGH */
+ case OP_ANDI:
+ db_printf("%s\t%s,%s,0x%x", op_name[i.IType.op],
+ reg_name[i.IType.rt], reg_name[i.IType.rs], i.IType.imm);
+ break;
+
+ case OP_LUI:
+ db_printf("%s\t%s,0x%x", op_name[i.IType.op],
+ reg_name[i.IType.rt], i.IType.imm);
+ break;
+
+ case OP_ADDI:
+ case OP_DADDI:
+ case OP_ADDIU:
+ case OP_DADDIU:
+ if (i.IType.rs == 0) {
+ db_printf("li\t%s,%d", reg_name[i.IType.rt],
+ (short)i.IType.imm);
+ break;
+ }
+ /* FALLTHROUGH */
+ default:
+ db_printf("%s\t%s,%s,%d", op_name[i.IType.op],
+ reg_name[i.IType.rt], reg_name[i.IType.rs],
+ (short)i.IType.imm);
+ }
+ db_printf("\n");
+ return (delay);
+}
Property changes on: trunk/sys/mips/mips/db_disasm.c
___________________________________________________________________
Added: svn:eol-style
## -0,0 +1 ##
+native
\ No newline at end of property
Added: svn:keywords
## -0,0 +1 ##
+MidnightBSD=%H
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+text/plain
\ No newline at end of property
Added: trunk/sys/mips/mips/db_interface.c
===================================================================
--- trunk/sys/mips/mips/db_interface.c (rev 0)
+++ trunk/sys/mips/mips/db_interface.c 2018-05-26 21:55:02 UTC (rev 9987)
@@ -0,0 +1,349 @@
+/* $MidnightBSD$ */
+/* $OpenBSD: db_machdep.c,v 1.2 1998/09/15 10:50:13 pefo Exp $ */
+
+/*-
+ * Copyright (c) 1998 Per Fogelstrom, Opsycon AB
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * 3. All advertising materials mentioning features or use of this software
+ * must display the following acknowledgement:
+ * This product includes software developed under OpenBSD by
+ * Per Fogelstrom, Opsycon AB, Sweden.
+ * 4. The name of the author may not be used to endorse or promote products
+ * derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS
+ * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ * JNPR: db_interface.c,v 1.6.2.1 2007/08/29 12:24:49 girish
+ */
+
+#include <sys/cdefs.h>
+__FBSDID("$FreeBSD: stable/10/sys/mips/mips/db_interface.c 250138 2013-05-01 06:57:46Z imp $");
+
+#include <sys/types.h>
+#include <sys/param.h>
+#include <sys/systm.h>
+#include <sys/cons.h>
+#include <sys/lock.h>
+#include <vm/vm.h>
+#include <vm/vm_object.h>
+#include <vm/vm_page.h>
+#include <vm/pmap.h>
+#include <vm/vm_map.h>
+#include <sys/user.h>
+#include <sys/proc.h>
+#include <sys/reboot.h>
+
+#include <machine/cache.h>
+#include <machine/db_machdep.h>
+#include <machine/mips_opcode.h>
+#include <machine/vmparam.h>
+#include <machine/md_var.h>
+#include <machine/setjmp.h>
+
+#include <ddb/ddb.h>
+#include <ddb/db_sym.h>
+#include <ddb/db_access.h>
+#include <ddb/db_output.h>
+#include <ddb/db_variables.h>
+#include <sys/kdb.h>
+
+static db_varfcn_t db_frame;
+
+#define DB_OFFSET(x) (db_expr_t *)offsetof(struct trapframe, x)
+struct db_variable db_regs[] = {
+ { "at", DB_OFFSET(ast), db_frame },
+ { "v0", DB_OFFSET(v0), db_frame },
+ { "v1", DB_OFFSET(v1), db_frame },
+ { "a0", DB_OFFSET(a0), db_frame },
+ { "a1", DB_OFFSET(a1), db_frame },
+ { "a2", DB_OFFSET(a2), db_frame },
+ { "a3", DB_OFFSET(a3), db_frame },
+#if defined(__mips_n32) || defined(__mips_n64)
+ { "a4", DB_OFFSET(a4), db_frame },
+ { "a5", DB_OFFSET(a5), db_frame },
+ { "a6", DB_OFFSET(a6), db_frame },
+ { "a7", DB_OFFSET(a7), db_frame },
+ { "t0", DB_OFFSET(t0), db_frame },
+ { "t1", DB_OFFSET(t1), db_frame },
+ { "t2", DB_OFFSET(t2), db_frame },
+ { "t3", DB_OFFSET(t3), db_frame },
+#else
+ { "t0", DB_OFFSET(t0), db_frame },
+ { "t1", DB_OFFSET(t1), db_frame },
+ { "t2", DB_OFFSET(t2), db_frame },
+ { "t3", DB_OFFSET(t3), db_frame },
+ { "t4", DB_OFFSET(t4), db_frame },
+ { "t5", DB_OFFSET(t5), db_frame },
+ { "t6", DB_OFFSET(t6), db_frame },
+ { "t7", DB_OFFSET(t7), db_frame },
+#endif
+ { "s0", DB_OFFSET(s0), db_frame },
+ { "s1", DB_OFFSET(s1), db_frame },
+ { "s2", DB_OFFSET(s2), db_frame },
+ { "s3", DB_OFFSET(s3), db_frame },
+ { "s4", DB_OFFSET(s4), db_frame },
+ { "s5", DB_OFFSET(s5), db_frame },
+ { "s6", DB_OFFSET(s6), db_frame },
+ { "s7", DB_OFFSET(s7), db_frame },
+ { "t8", DB_OFFSET(t8), db_frame },
+ { "t9", DB_OFFSET(t9), db_frame },
+ { "k0", DB_OFFSET(k0), db_frame },
+ { "k1", DB_OFFSET(k1), db_frame },
+ { "gp", DB_OFFSET(gp), db_frame },
+ { "sp", DB_OFFSET(sp), db_frame },
+ { "s8", DB_OFFSET(s8), db_frame },
+ { "ra", DB_OFFSET(ra), db_frame },
+ { "sr", DB_OFFSET(sr), db_frame },
+ { "lo", DB_OFFSET(mullo), db_frame },
+ { "hi", DB_OFFSET(mulhi), db_frame },
+ { "bad", DB_OFFSET(badvaddr), db_frame },
+ { "cs", DB_OFFSET(cause), db_frame },
+ { "pc", DB_OFFSET(pc), db_frame },
+};
+struct db_variable *db_eregs = db_regs + sizeof(db_regs)/sizeof(db_regs[0]);
+
+int (*do_db_log_stack_trace_cmd)(char *);
+
+static int
+db_frame(struct db_variable *vp, db_expr_t *valuep, int op)
+{
+ register_t *reg;
+
+ if (kdb_frame == NULL)
+ return (0);
+
+ reg = (register_t *)((uintptr_t)kdb_frame + (size_t)(intptr_t)vp->valuep);
+ if (op == DB_VAR_GET)
+ *valuep = *reg;
+ else
+ *reg = *valuep;
+ return (1);
+}
+
+int
+db_read_bytes(vm_offset_t addr, size_t size, char *data)
+{
+ jmp_buf jb;
+ void *prev_jb;
+ int ret;
+
+ prev_jb = kdb_jmpbuf(jb);
+ ret = setjmp(jb);
+ if (ret == 0) {
+ /*
+ * 'addr' could be a memory-mapped I/O address. Try to
+ * do atomic load/store in unit of size requested.
+ */
+ if ((size == 2 || size == 4 || size == 8) &&
+ ((addr & (size -1)) == 0) &&
+ (((vm_offset_t)data & (size -1)) == 0)) {
+ switch (size) {
+ case 2:
+ *(uint16_t *)data = *(uint16_t *)addr;
+ break;
+ case 4:
+ *(uint32_t *)data = *(uint32_t *)addr;
+ break;
+ case 8:
+ atomic_load_64((volatile u_int64_t *)addr,
+ (u_int64_t *)data);
+ break;
+ }
+ } else {
+ char *src;
+
+ src = (char *)addr;
+ while (size-- > 0)
+ *data++ = *src++;
+ }
+ }
+
+ (void)kdb_jmpbuf(prev_jb);
+ return (ret);
+}
+
+int
+db_write_bytes(vm_offset_t addr, size_t size, char *data)
+{
+ int ret;
+ jmp_buf jb;
+ void *prev_jb;
+
+ prev_jb = kdb_jmpbuf(jb);
+ ret = setjmp(jb);
+
+ if (ret == 0) {
+ /*
+ * 'addr' could be a memory-mapped I/O address. Try to
+ * do atomic load/store in unit of size requested.
+ */
+ if ((size == 2 || size == 4 || size == 8) &&
+ ((addr & (size -1)) == 0) &&
+ (((vm_offset_t)data & (size -1)) == 0)) {
+ switch (size) {
+ case 2:
+ *(uint16_t *)addr = *(uint16_t *)data;
+ break;
+ case 4:
+ *(uint32_t *)addr = *(uint32_t *)data;
+ break;
+ case 8:
+ atomic_store_64((volatile u_int64_t *)addr,
+ (u_int64_t *)data);
+ break;
+ }
+ } else {
+ char *dst;
+ size_t len = size;
+
+ dst = (char *)addr;
+ while (len-- > 0)
+ *dst++ = *data++;
+ }
+
+ mips_icache_sync_range((db_addr_t) addr, size);
+ mips_dcache_wbinv_range((db_addr_t) addr, size);
+ }
+ (void)kdb_jmpbuf(prev_jb);
+ return (ret);
+}
+
+/*
+ * To do a single step ddb needs to know the next address
+ * that we will get to. It means that we need to find out
+ * both the address for a branch taken and for not taken, NOT! :-)
+ * MipsEmulateBranch will do the job to find out _exactly_ which
+ * address we will end up at so the 'dual bp' method is not
+ * requiered.
+ */
+db_addr_t
+next_instr_address(db_addr_t pc, boolean_t bd)
+{
+ db_addr_t next;
+
+ next = (db_addr_t)MipsEmulateBranch(kdb_frame, pc, 0, 0);
+ return (next);
+}
+
+
+/*
+ * Decode instruction and figure out type.
+ */
+int
+db_inst_type(int ins)
+{
+ InstFmt inst;
+ int ityp = 0;
+
+ inst.word = ins;
+ switch ((int)inst.JType.op) {
+ case OP_SPECIAL:
+ switch ((int)inst.RType.func) {
+ case OP_JR:
+ ityp = IT_BRANCH;
+ break;
+ case OP_JALR:
+ case OP_SYSCALL:
+ ityp = IT_CALL;
+ break;
+ }
+ break;
+
+ case OP_BCOND:
+ switch ((int)inst.IType.rt) {
+ case OP_BLTZ:
+ case OP_BLTZL:
+ case OP_BGEZ:
+ case OP_BGEZL:
+ ityp = IT_BRANCH;
+ break;
+
+ case OP_BLTZAL:
+ case OP_BLTZALL:
+ case OP_BGEZAL:
+ case OP_BGEZALL:
+ ityp = IT_CALL;
+ break;
+ }
+ break;
+
+ case OP_JAL:
+ ityp = IT_CALL;
+ break;
+
+ case OP_J:
+ case OP_BEQ:
+ case OP_BEQL:
+ case OP_BNE:
+ case OP_BNEL:
+ case OP_BLEZ:
+ case OP_BLEZL:
+ case OP_BGTZ:
+ case OP_BGTZL:
+ ityp = IT_BRANCH;
+ break;
+
+ case OP_COP1:
+ switch (inst.RType.rs) {
+ case OP_BCx:
+ case OP_BCy:
+ ityp = IT_BRANCH;
+ break;
+ }
+ break;
+
+ case OP_LB:
+ case OP_LH:
+ case OP_LW:
+ case OP_LD:
+ case OP_LBU:
+ case OP_LHU:
+ case OP_LWU:
+ case OP_LWC1:
+ ityp = IT_LOAD;
+ break;
+
+ case OP_SB:
+ case OP_SH:
+ case OP_SW:
+ case OP_SD:
+ case OP_SWC1:
+ ityp = IT_STORE;
+ break;
+ }
+ return (ityp);
+}
+
+/*
+ * Return the next pc if the given branch is taken.
+ * MachEmulateBranch() runs analysis for branch delay slot.
+ */
+db_addr_t
+branch_taken(int inst, db_addr_t pc)
+{
+ db_addr_t ra;
+ register_t fpucsr;
+
+ /* TBD: when is fsr set */
+ fpucsr = (curthread) ? curthread->td_pcb->pcb_regs.fsr : 0;
+ ra = (db_addr_t)MipsEmulateBranch(kdb_frame, pc, fpucsr, 0);
+ return (ra);
+}
Property changes on: trunk/sys/mips/mips/db_interface.c
___________________________________________________________________
Added: svn:eol-style
## -0,0 +1 ##
+native
\ No newline at end of property
Added: svn:keywords
## -0,0 +1 ##
+MidnightBSD=%H
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+text/plain
\ No newline at end of property
Added: trunk/sys/mips/mips/db_trace.c
===================================================================
--- trunk/sys/mips/mips/db_trace.c (rev 0)
+++ trunk/sys/mips/mips/db_trace.c 2018-05-26 21:55:02 UTC (rev 9987)
@@ -0,0 +1,467 @@
+/* $MidnightBSD$ */
+/*-
+ * Copyright (c) 2004-2005, Juniper Networks, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ * JNPR: db_trace.c,v 1.8 2007/08/09 11:23:32 katta
+ */
+
+#include <sys/cdefs.h>
+__FBSDID("$FreeBSD: stable/10/sys/mips/mips/db_trace.c 251103 2013-05-29 16:51:03Z marcel $");
+
+#include <sys/param.h>
+#include <sys/systm.h>
+#include <sys/kdb.h>
+#include <sys/proc.h>
+#include <sys/stack.h>
+#include <sys/sysent.h>
+
+#include <machine/db_machdep.h>
+#include <machine/md_var.h>
+#include <machine/mips_opcode.h>
+#include <machine/pcb.h>
+#include <machine/trap.h>
+
+#include <ddb/ddb.h>
+#include <ddb/db_sym.h>
+
+extern char _locore[];
+extern char _locoreEnd[];
+extern char edata[];
+
+/*
+ * A function using a stack frame has the following instruction as the first
+ * one: [d]addiu sp,sp,-<frame_size>
+ *
+ * We make use of this to detect starting address of a function. This works
+ * better than using 'j ra' instruction to signify end of the previous
+ * function (for e.g. functions like boot() or panic() do not actually
+ * emit a 'j ra' instruction).
+ *
+ * XXX the abi does not require that the addiu instruction be the first one.
+ */
+#define MIPS_START_OF_FUNCTION(ins) ((((ins) & 0xffff8000) == 0x27bd8000) \
+ || (((ins) & 0xffff8000) == 0x67bd8000))
+
+/*
+ * MIPS ABI 3.0 requires that all functions return using the 'j ra' instruction
+ *
+ * XXX gcc doesn't do this for functions with __noreturn__ attribute.
+ */
+#define MIPS_END_OF_FUNCTION(ins) ((ins) == 0x03e00008)
+
+#if defined(__mips_n64)
+# define MIPS_IS_VALID_KERNELADDR(reg) ((((reg) & 3) == 0) && \
+ ((vm_offset_t)(reg) >= MIPS_XKPHYS_START))
+#else
+# define MIPS_IS_VALID_KERNELADDR(reg) ((((reg) & 3) == 0) && \
+ ((vm_offset_t)(reg) >= MIPS_KSEG0_START))
+#endif
+
+/*
+ * Functions ``special'' enough to print by name
+ */
+#ifdef __STDC__
+#define Name(_fn) { (void*)_fn, # _fn }
+#else
+#define Name(_fn) { _fn, "_fn"}
+#endif
+static struct {
+ void *addr;
+ char *name;
+} names[] = {
+
+ Name(trap),
+ Name(MipsKernGenException),
+ Name(MipsUserGenException),
+ Name(MipsKernIntr),
+ Name(MipsUserIntr),
+ Name(cpu_switch),
+ {
+ 0, 0
+ }
+};
+
+/*
+ * Map a function address to a string name, if known; or a hex string.
+ */
+static char *
+fn_name(uintptr_t addr)
+{
+ static char buf[17];
+ int i = 0;
+
+ db_expr_t diff;
+ c_db_sym_t sym;
+ char *symname;
+
+ diff = 0;
+ symname = NULL;
+ sym = db_search_symbol((db_addr_t)addr, DB_STGY_ANY, &diff);
+ db_symbol_values(sym, (const char **)&symname, (db_expr_t *)0);
+ if (symname && diff == 0)
+ return (symname);
+
+ for (i = 0; names[i].name; i++)
+ if (names[i].addr == (void *)addr)
+ return (names[i].name);
+ sprintf(buf, "%jx", (uintmax_t)addr);
+ return (buf);
+}
+
+void
+stacktrace_subr(register_t pc, register_t sp, register_t ra,
+ int (*printfn) (const char *,...))
+{
+ InstFmt i;
+ /*
+ * Arrays for a0..a3 registers and flags if content
+ * of these registers is valid, e.g. obtained from the stack
+ */
+ int valid_args[4];
+ uintptr_t args[4];
+ uintptr_t va, subr;
+ unsigned instr, mask;
+ unsigned int frames = 0;
+ int more, stksize, j;
+
+/* Jump here when done with a frame, to start a new one */
+loop:
+
+ /*
+ * Invalidate arguments values
+ */
+ valid_args[0] = 0;
+ valid_args[1] = 0;
+ valid_args[2] = 0;
+ valid_args[3] = 0;
+/* Jump here after a nonstandard (interrupt handler) frame */
+ stksize = 0;
+ subr = 0;
+ if (frames++ > 100) {
+ (*printfn) ("\nstackframe count exceeded\n");
+ /* return breaks stackframe-size heuristics with gcc -O2 */
+ goto finish; /* XXX */
+ }
+ /* check for bad SP: could foul up next frame */
+ /*XXX MIPS64 bad: this hard-coded SP is lame */
+ if (!MIPS_IS_VALID_KERNELADDR(sp)) {
+ (*printfn) ("SP 0x%jx: not in kernel\n", sp);
+ ra = 0;
+ subr = 0;
+ goto done;
+ }
+#define Between(x, y, z) \
+ ( ((x) <= (y)) && ((y) < (z)) )
+#define pcBetween(a,b) \
+ Between((uintptr_t)a, pc, (uintptr_t)b)
+
+ /*
+ * Check for current PC in exception handler code that don't have a
+ * preceding "j ra" at the tail of the preceding function. Depends
+ * on relative ordering of functions in exception.S, swtch.S.
+ */
+ if (pcBetween(MipsKernGenException, MipsUserGenException))
+ subr = (uintptr_t)MipsKernGenException;
+ else if (pcBetween(MipsUserGenException, MipsKernIntr))
+ subr = (uintptr_t)MipsUserGenException;
+ else if (pcBetween(MipsKernIntr, MipsUserIntr))
+ subr = (uintptr_t)MipsKernIntr;
+ else if (pcBetween(MipsUserIntr, MipsTLBInvalidException))
+ subr = (uintptr_t)MipsUserIntr;
+ else if (pcBetween(MipsTLBInvalidException, MipsTLBMissException))
+ subr = (uintptr_t)MipsTLBInvalidException;
+ else if (pcBetween(fork_trampoline, savectx))
+ subr = (uintptr_t)fork_trampoline;
+ else if (pcBetween(savectx, cpu_throw))
+ subr = (uintptr_t)savectx;
+ else if (pcBetween(cpu_throw, cpu_switch))
+ subr = (uintptr_t)cpu_throw;
+ else if (pcBetween(cpu_switch, MipsSwitchFPState))
+ subr = (uintptr_t)cpu_switch;
+ else if (pcBetween(_locore, _locoreEnd)) {
+ subr = (uintptr_t)_locore;
+ ra = 0;
+ goto done;
+ }
+ /* check for bad PC */
+ /*XXX MIPS64 bad: These hard coded constants are lame */
+ if (!MIPS_IS_VALID_KERNELADDR(pc)) {
+ (*printfn) ("PC 0x%jx: not in kernel\n", pc);
+ ra = 0;
+ goto done;
+ }
+ /*
+ * Find the beginning of the current subroutine by scanning
+ * backwards from the current PC for the end of the previous
+ * subroutine.
+ */
+ if (!subr) {
+ va = pc - sizeof(int);
+ while (1) {
+ instr = kdbpeek((int *)va);
+
+ if (MIPS_START_OF_FUNCTION(instr))
+ break;
+
+ if (MIPS_END_OF_FUNCTION(instr)) {
+ /* skip over branch-delay slot instruction */
+ va += 2 * sizeof(int);
+ break;
+ }
+
+ va -= sizeof(int);
+ }
+
+ /* skip over nulls which might separate .o files */
+ while ((instr = kdbpeek((int *)va)) == 0)
+ va += sizeof(int);
+ subr = va;
+ }
+ /* scan forwards to find stack size and any saved registers */
+ stksize = 0;
+ more = 3;
+ mask = 0;
+ for (va = subr; more; va += sizeof(int),
+ more = (more == 3) ? 3 : more - 1) {
+ /* stop if hit our current position */
+ if (va >= pc)
+ break;
+ instr = kdbpeek((int *)va);
+ i.word = instr;
+ switch (i.JType.op) {
+ case OP_SPECIAL:
+ switch (i.RType.func) {
+ case OP_JR:
+ case OP_JALR:
+ more = 2; /* stop after next instruction */
+ break;
+
+ case OP_SYSCALL:
+ case OP_BREAK:
+ more = 1; /* stop now */
+ };
+ break;
+
+ case OP_BCOND:
+ case OP_J:
+ case OP_JAL:
+ case OP_BEQ:
+ case OP_BNE:
+ case OP_BLEZ:
+ case OP_BGTZ:
+ more = 2; /* stop after next instruction */
+ break;
+
+ case OP_COP0:
+ case OP_COP1:
+ case OP_COP2:
+ case OP_COP3:
+ switch (i.RType.rs) {
+ case OP_BCx:
+ case OP_BCy:
+ more = 2; /* stop after next instruction */
+ };
+ break;
+
+ case OP_SW:
+ /* look for saved registers on the stack */
+ if (i.IType.rs != 29)
+ break;
+ /* only restore the first one */
+ if (mask & (1 << i.IType.rt))
+ break;
+ mask |= (1 << i.IType.rt);
+ switch (i.IType.rt) {
+ case 4:/* a0 */
+ args[0] = kdbpeek((int *)(sp + (short)i.IType.imm));
+ valid_args[0] = 1;
+ break;
+
+ case 5:/* a1 */
+ args[1] = kdbpeek((int *)(sp + (short)i.IType.imm));
+ valid_args[1] = 1;
+ break;
+
+ case 6:/* a2 */
+ args[2] = kdbpeek((int *)(sp + (short)i.IType.imm));
+ valid_args[2] = 1;
+ break;
+
+ case 7:/* a3 */
+ args[3] = kdbpeek((int *)(sp + (short)i.IType.imm));
+ valid_args[3] = 1;
+ break;
+
+ case 31: /* ra */
+ ra = kdbpeek((int *)(sp + (short)i.IType.imm));
+ }
+ break;
+
+ case OP_SD:
+ /* look for saved registers on the stack */
+ if (i.IType.rs != 29)
+ break;
+ /* only restore the first one */
+ if (mask & (1 << i.IType.rt))
+ break;
+ mask |= (1 << i.IType.rt);
+ switch (i.IType.rt) {
+ case 4:/* a0 */
+ args[0] = kdbpeekd((int *)(sp + (short)i.IType.imm));
+ valid_args[0] = 1;
+ break;
+
+ case 5:/* a1 */
+ args[1] = kdbpeekd((int *)(sp + (short)i.IType.imm));
+ valid_args[1] = 1;
+ break;
+
+ case 6:/* a2 */
+ args[2] = kdbpeekd((int *)(sp + (short)i.IType.imm));
+ valid_args[2] = 1;
+ break;
+
+ case 7:/* a3 */
+ args[3] = kdbpeekd((int *)(sp + (short)i.IType.imm));
+ valid_args[3] = 1;
+ break;
+
+ case 31: /* ra */
+ ra = kdbpeekd((int *)(sp + (short)i.IType.imm));
+ }
+ break;
+
+ case OP_ADDI:
+ case OP_ADDIU:
+ case OP_DADDI:
+ case OP_DADDIU:
+ /* look for stack pointer adjustment */
+ if (i.IType.rs != 29 || i.IType.rt != 29)
+ break;
+ stksize = -((short)i.IType.imm);
+ }
+ }
+
+done:
+ (*printfn) ("%s+%x (", fn_name(subr), pc - subr);
+ for (j = 0; j < 4; j ++) {
+ if (j > 0)
+ (*printfn)(",");
+ if (valid_args[j])
+ (*printfn)("%x", args[j]);
+ else
+ (*printfn)("?");
+ }
+
+ (*printfn) (") ra %jx sp %jx sz %d\n", ra, sp, stksize);
+
+ if (ra) {
+ if (pc == ra && stksize == 0)
+ (*printfn) ("stacktrace: loop!\n");
+ else {
+ pc = ra;
+ sp += stksize;
+ ra = 0;
+ goto loop;
+ }
+ } else {
+finish:
+ if (curproc)
+ (*printfn) ("pid %d\n", curproc->p_pid);
+ else
+ (*printfn) ("curproc NULL\n");
+ }
+}
+
+
+int
+db_md_set_watchpoint(db_expr_t addr, db_expr_t size)
+{
+
+ return(0);
+}
+
+
+int
+db_md_clr_watchpoint(db_expr_t addr, db_expr_t size)
+{
+
+ return(0);
+}
+
+
+void
+db_md_list_watchpoints()
+{
+}
+
+void
+db_trace_self(void)
+{
+ db_trace_thread (curthread, -1);
+ return;
+}
+
+int
+db_trace_thread(struct thread *thr, int count)
+{
+ register_t pc, ra, sp;
+ struct pcb *ctx;
+
+ if (thr == curthread) {
+ sp = (register_t)(intptr_t)__builtin_frame_address(0);
+ ra = (register_t)(intptr_t)__builtin_return_address(0);
+
+ __asm __volatile(
+ "jal 99f\n"
+ "nop\n"
+ "99:\n"
+ "move %0, $31\n" /* get ra */
+ "move $31, %1\n" /* restore ra */
+ : "=r" (pc)
+ : "r" (ra));
+
+ } else {
+ ctx = kdb_thr_ctx(thr);
+ sp = (register_t)ctx->pcb_context[PCB_REG_SP];
+ pc = (register_t)ctx->pcb_context[PCB_REG_PC];
+ ra = (register_t)ctx->pcb_context[PCB_REG_RA];
+ }
+
+ stacktrace_subr(pc, sp, ra,
+ (int (*) (const char *, ...))db_printf);
+
+ return (0);
+}
+
+void
+db_show_mdpcpu(struct pcpu *pc)
+{
+
+ db_printf("ipis = 0x%x\n", pc->pc_pending_ipis);
+ db_printf("next ASID = %d\n", pc->pc_next_asid);
+ db_printf("GENID = %d\n", pc->pc_asid_generation);
+ return;
+}
Property changes on: trunk/sys/mips/mips/db_trace.c
___________________________________________________________________
Added: svn:eol-style
## -0,0 +1 ##
+native
\ No newline at end of property
Added: svn:keywords
## -0,0 +1 ##
+MidnightBSD=%H
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+text/plain
\ No newline at end of property
Added: trunk/sys/mips/mips/dump_machdep.c
===================================================================
--- trunk/sys/mips/mips/dump_machdep.c (rev 0)
+++ trunk/sys/mips/mips/dump_machdep.c 2018-05-26 21:55:02 UTC (rev 9987)
@@ -0,0 +1,371 @@
+/* $MidnightBSD$ */
+/*-
+ * Copyright (c) 2002 Marcel Moolenaar
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+ * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+ * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <sys/cdefs.h>
+__FBSDID("$FreeBSD: stable/10/sys/mips/mips/dump_machdep.c 224845 2011-08-13 17:17:04Z attilio $");
+
+#include "opt_watchdog.h"
+
+#include <sys/param.h>
+#include <sys/systm.h>
+#include <sys/conf.h>
+#include <sys/cons.h>
+#include <sys/sysctl.h>
+#include <sys/kernel.h>
+#include <sys/proc.h>
+#include <sys/kerneldump.h>
+#ifdef SW_WATCHDOG
+#include <sys/watchdog.h>
+#endif
+#include <vm/vm.h>
+#include <vm/pmap.h>
+#include <machine/elf.h>
+#include <machine/md_var.h>
+#include <machine/pcb.h>
+#include <machine/cache.h>
+
+CTASSERT(sizeof(struct kerneldumpheader) == 512);
+
+int do_minidump = 1;
+TUNABLE_INT("debug.minidump", &do_minidump);
+SYSCTL_INT(_debug, OID_AUTO, minidump, CTLFLAG_RW, &do_minidump, 0,
+ "Enable mini crash dumps");
+
+/*
+ * Don't touch the first SIZEOF_METADATA bytes on the dump device. This
+ * is to protect us from metadata and to protect metadata from us.
+ */
+#define SIZEOF_METADATA (64*1024)
+
+#define MD_ALIGN(x) (((off_t)(x) + PAGE_MASK) & ~PAGE_MASK)
+#define DEV_ALIGN(x) (((off_t)(x) + (DEV_BSIZE-1)) & ~(DEV_BSIZE-1))
+extern struct pcb dumppcb;
+
+struct md_pa {
+ vm_paddr_t md_start;
+ vm_paddr_t md_size;
+};
+
+typedef int callback_t(struct md_pa *, int, void *);
+
+static struct kerneldumpheader kdh;
+static off_t dumplo, fileofs;
+
+/* Handle buffered writes. */
+static char buffer[DEV_BSIZE];
+static size_t fragsz;
+
+/* XXX: I suppose 20 should be enough. */
+static struct md_pa dump_map[20];
+
+static void
+md_pa_init(void)
+{
+ int n, idx;
+
+ bzero(dump_map, sizeof(dump_map));
+ for (n = 0; n < sizeof(dump_map) / sizeof(dump_map[0]); n++) {
+ idx = n * 2;
+ if (dump_avail[idx] == 0 && dump_avail[idx + 1] == 0)
+ break;
+ dump_map[n].md_start = dump_avail[idx];
+ dump_map[n].md_size = dump_avail[idx + 1] - dump_avail[idx];
+ }
+}
+
+static struct md_pa *
+md_pa_first(void)
+{
+
+ return (&dump_map[0]);
+}
+
+static struct md_pa *
+md_pa_next(struct md_pa *mdp)
+{
+
+ mdp++;
+ if (mdp->md_size == 0)
+ mdp = NULL;
+ return (mdp);
+}
+
+static int
+buf_write(struct dumperinfo *di, char *ptr, size_t sz)
+{
+ size_t len;
+ int error;
+
+ while (sz) {
+ len = DEV_BSIZE - fragsz;
+ if (len > sz)
+ len = sz;
+ bcopy(ptr, buffer + fragsz, len);
+ fragsz += len;
+ ptr += len;
+ sz -= len;
+ if (fragsz == DEV_BSIZE) {
+ error = dump_write(di, buffer, 0, dumplo,
+ DEV_BSIZE);
+ if (error)
+ return error;
+ dumplo += DEV_BSIZE;
+ fragsz = 0;
+ }
+ }
+
+ return (0);
+}
+
+static int
+buf_flush(struct dumperinfo *di)
+{
+ int error;
+
+ if (fragsz == 0)
+ return (0);
+
+ error = dump_write(di, buffer, 0, dumplo, DEV_BSIZE);
+ dumplo += DEV_BSIZE;
+ fragsz = 0;
+ return (error);
+}
+
+extern vm_offset_t kernel_l1kva;
+extern char *pouet2;
+
+static int
+cb_dumpdata(struct md_pa *mdp, int seqnr, void *arg)
+{
+ struct dumperinfo *di = (struct dumperinfo*)arg;
+ vm_paddr_t pa;
+ uint32_t pgs;
+ size_t counter, sz, chunk;
+ int c, error;
+
+ error = 0; /* catch case in which chunk size is 0 */
+ counter = 0;
+ pgs = mdp->md_size / PAGE_SIZE;
+ pa = mdp->md_start;
+
+ printf(" chunk %d: %dMB (%d pages)", seqnr, pgs * PAGE_SIZE / (
+ 1024*1024), pgs);
+
+ /* Make sure we write coherent datas. */
+ mips_dcache_wbinv_all();
+ while (pgs) {
+ chunk = pgs;
+ if (chunk > MAXDUMPPGS)
+ chunk = MAXDUMPPGS;
+ sz = chunk << PAGE_SHIFT;
+ counter += sz;
+ if (counter >> 24) {
+ printf(" %d", pgs * PAGE_SIZE);
+ counter &= (1<<24) - 1;
+ }
+
+#ifdef SW_WATCHDOG
+ wdog_kern_pat(WD_LASTVAL);
+#endif
+ error = dump_write(di, (void *)(intptr_t)(pa),0, dumplo, sz); /* XXX fix PA */
+ if (error)
+ break;
+ dumplo += sz;
+ pgs -= chunk;
+ pa += sz;
+
+ /* Check for user abort. */
+ c = cncheckc();
+ if (c == 0x03)
+ return (ECANCELED);
+ if (c != -1)
+ printf(" (CTRL-C to abort) ");
+ }
+ printf(" ... %s\n", (error) ? "fail" : "ok");
+ return (error);
+}
+
+static int
+cb_dumphdr(struct md_pa *mdp, int seqnr, void *arg)
+{
+ struct dumperinfo *di = (struct dumperinfo*)arg;
+ Elf_Phdr phdr;
+ uint64_t size;
+ int error;
+
+ size = mdp->md_size;
+ bzero(&phdr, sizeof(phdr));
+ phdr.p_type = PT_LOAD;
+ phdr.p_flags = PF_R; /* XXX */
+ phdr.p_offset = fileofs;
+ phdr.p_vaddr = mdp->md_start;
+ phdr.p_paddr = mdp->md_start;
+ phdr.p_filesz = size;
+ phdr.p_memsz = size;
+ phdr.p_align = PAGE_SIZE;
+
+ error = buf_write(di, (char*)&phdr, sizeof(phdr));
+ fileofs += phdr.p_filesz;
+ return (error);
+}
+
+static int
+cb_size(struct md_pa *mdp, int seqnr, void *arg)
+{
+ uint32_t *sz = (uint32_t*)arg;
+
+ *sz += (uint32_t)mdp->md_size;
+ return (0);
+}
+
+static int
+foreach_chunk(callback_t cb, void *arg)
+{
+ struct md_pa *mdp;
+ int error, seqnr;
+
+ seqnr = 0;
+ mdp = md_pa_first();
+ while (mdp != NULL) {
+ error = (*cb)(mdp, seqnr++, arg);
+ if (error)
+ return (-error);
+ mdp = md_pa_next(mdp);
+ }
+ return (seqnr);
+}
+
+void
+dumpsys(struct dumperinfo *di)
+{
+ Elf_Ehdr ehdr;
+ uint32_t dumpsize;
+ off_t hdrgap;
+ size_t hdrsz;
+ int error;
+
+ if (do_minidump) {
+ minidumpsys(di);
+ return;
+ }
+
+ bzero(&ehdr, sizeof(ehdr));
+ ehdr.e_ident[EI_MAG0] = ELFMAG0;
+ ehdr.e_ident[EI_MAG1] = ELFMAG1;
+ ehdr.e_ident[EI_MAG2] = ELFMAG2;
+ ehdr.e_ident[EI_MAG3] = ELFMAG3;
+ ehdr.e_ident[EI_CLASS] = ELF_CLASS;
+#if BYTE_ORDER == LITTLE_ENDIAN
+ ehdr.e_ident[EI_DATA] = ELFDATA2LSB;
+#else
+ ehdr.e_ident[EI_DATA] = ELFDATA2MSB;
+#endif
+ ehdr.e_ident[EI_VERSION] = EV_CURRENT;
+ ehdr.e_ident[EI_OSABI] = ELFOSABI_STANDALONE; /* XXX big picture? */
+ ehdr.e_type = ET_CORE;
+ ehdr.e_machine = EM_MIPS;
+ ehdr.e_phoff = sizeof(ehdr);
+ ehdr.e_flags = 0;
+ ehdr.e_ehsize = sizeof(ehdr);
+ ehdr.e_phentsize = sizeof(Elf_Phdr);
+ ehdr.e_shentsize = sizeof(Elf_Shdr);
+
+ md_pa_init();
+
+ /* Calculate dump size. */
+ dumpsize = 0L;
+ ehdr.e_phnum = foreach_chunk(cb_size, &dumpsize);
+ hdrsz = ehdr.e_phoff + ehdr.e_phnum * ehdr.e_phentsize;
+ fileofs = MD_ALIGN(hdrsz);
+ dumpsize += fileofs;
+ hdrgap = fileofs - DEV_ALIGN(hdrsz);
+
+ /* Determine dump offset on device. */
+ if (di->mediasize < SIZEOF_METADATA + dumpsize + sizeof(kdh) * 2) {
+ error = ENOSPC;
+ goto fail;
+ }
+ dumplo = di->mediaoffset + di->mediasize - dumpsize;
+ dumplo -= sizeof(kdh) * 2;
+
+ mkdumpheader(&kdh, KERNELDUMPMAGIC, KERNELDUMP_MIPS_VERSION, dumpsize, di->blocksize);
+
+ printf("Dumping %llu MB (%d chunks)\n", (long long)dumpsize >> 20,
+ ehdr.e_phnum);
+
+ /* Dump leader */
+ error = dump_write(di, &kdh, 0, dumplo, sizeof(kdh));
+ if (error)
+ goto fail;
+ dumplo += sizeof(kdh);
+
+ /* Dump ELF header */
+ error = buf_write(di, (char*)&ehdr, sizeof(ehdr));
+ if (error)
+ goto fail;
+
+ /* Dump program headers */
+ error = foreach_chunk(cb_dumphdr, di);
+ if (error < 0)
+ goto fail;
+ buf_flush(di);
+
+ /*
+ * All headers are written using blocked I/O, so we know the
+ * current offset is (still) block aligned. Skip the alignement
+ * in the file to have the segment contents aligned at page
+ * boundary. We cannot use MD_ALIGN on dumplo, because we don't
+ * care and may very well be unaligned within the dump device.
+ */
+ dumplo += hdrgap;
+
+ /* Dump memory chunks (updates dumplo) */
+ error = foreach_chunk(cb_dumpdata, di);
+ if (error < 0)
+ goto fail;
+
+ /* Dump trailer */
+ error = dump_write(di, &kdh, 0, dumplo, sizeof(kdh));
+ if (error)
+ goto fail;
+
+ /* Signal completion, signoff and exit stage left. */
+ dump_write(di, NULL, 0, 0, 0);
+ printf("\nDump complete\n");
+ return;
+
+ fail:
+ if (error < 0)
+ error = -error;
+
+ if (error == ECANCELED)
+ printf("\nDump aborted\n");
+ else if (error == ENOSPC)
+ printf("\nDump failed. Partition too small.\n");
+ else
+ printf("\n** DUMP FAILED (ERROR %d) **\n", error);
+}
Property changes on: trunk/sys/mips/mips/dump_machdep.c
___________________________________________________________________
Added: svn:eol-style
## -0,0 +1 ##
+native
\ No newline at end of property
Added: svn:keywords
## -0,0 +1 ##
+MidnightBSD=%H
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+text/plain
\ No newline at end of property
Added: trunk/sys/mips/mips/elf_machdep.c
===================================================================
--- trunk/sys/mips/mips/elf_machdep.c (rev 0)
+++ trunk/sys/mips/mips/elf_machdep.c 2018-05-26 21:55:02 UTC (rev 9987)
@@ -0,0 +1,360 @@
+/* $MidnightBSD$ */
+/*-
+ * Copyright 1996-1998 John D. Polstra.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+ * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+ * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * from: src/sys/i386/i386/elf_machdep.c,v 1.20 2004/08/11 02:35:05 marcel
+ */
+
+#include <sys/cdefs.h>
+__FBSDID("$FreeBSD: stable/10/sys/mips/mips/elf_machdep.c 294136 2016-01-16 07:56:49Z dchagin $");
+
+#include <sys/param.h>
+#include <sys/kernel.h>
+#include <sys/systm.h>
+#include <sys/exec.h>
+#include <sys/imgact.h>
+#include <sys/linker.h>
+#include <sys/sysent.h>
+#include <sys/imgact_elf.h>
+#include <sys/proc.h>
+#include <sys/syscall.h>
+#include <sys/signalvar.h>
+#include <sys/vnode.h>
+
+#include <vm/vm.h>
+#include <vm/pmap.h>
+#include <vm/vm_param.h>
+
+#include <machine/elf.h>
+#include <machine/md_var.h>
+#include <machine/cache.h>
+
+#ifdef __mips_n64
+struct sysentvec elf64_freebsd_sysvec = {
+ .sv_size = SYS_MAXSYSCALL,
+ .sv_table = sysent,
+ .sv_mask = 0,
+ .sv_sigsize = 0,
+ .sv_sigtbl = NULL,
+ .sv_errsize = 0,
+ .sv_errtbl = NULL,
+ .sv_transtrap = NULL,
+ .sv_fixup = __elfN(freebsd_fixup),
+ .sv_sendsig = sendsig,
+ .sv_sigcode = sigcode,
+ .sv_szsigcode = &szsigcode,
+ .sv_prepsyscall = NULL,
+ .sv_name = "FreeBSD ELF64",
+ .sv_coredump = __elfN(coredump),
+ .sv_imgact_try = NULL,
+ .sv_minsigstksz = MINSIGSTKSZ,
+ .sv_pagesize = PAGE_SIZE,
+ .sv_minuser = VM_MIN_ADDRESS,
+ .sv_maxuser = VM_MAXUSER_ADDRESS,
+ .sv_usrstack = USRSTACK,
+ .sv_psstrings = PS_STRINGS,
+ .sv_stackprot = VM_PROT_ALL,
+ .sv_copyout_strings = exec_copyout_strings,
+ .sv_setregs = exec_setregs,
+ .sv_fixlimit = NULL,
+ .sv_maxssiz = NULL,
+ .sv_flags = SV_ABI_FREEBSD | SV_LP64,
+ .sv_set_syscall_retval = cpu_set_syscall_retval,
+ .sv_fetch_syscall_args = cpu_fetch_syscall_args,
+ .sv_syscallnames = syscallnames,
+ .sv_schedtail = NULL,
+ .sv_thread_detach = NULL,
+ .sv_trap = NULL,
+};
+
+static Elf64_Brandinfo freebsd_brand_info = {
+ .brand = ELFOSABI_FREEBSD,
+ .machine = EM_MIPS,
+ .compat_3_brand = "FreeBSD",
+ .emul_path = NULL,
+ .interp_path = "/libexec/ld-elf.so.1",
+ .sysvec = &elf64_freebsd_sysvec,
+ .interp_newpath = NULL,
+ .flags = 0
+};
+
+SYSINIT(elf64, SI_SUB_EXEC, SI_ORDER_ANY,
+ (sysinit_cfunc_t) elf64_insert_brand_entry,
+ &freebsd_brand_info);
+
+void
+elf64_dump_thread(struct thread *td __unused, void *dst __unused,
+ size_t *off __unused)
+{
+}
+#else
+struct sysentvec elf32_freebsd_sysvec = {
+ .sv_size = SYS_MAXSYSCALL,
+ .sv_table = sysent,
+ .sv_mask = 0,
+ .sv_sigsize = 0,
+ .sv_sigtbl = NULL,
+ .sv_errsize = 0,
+ .sv_errtbl = NULL,
+ .sv_transtrap = NULL,
+ .sv_fixup = __elfN(freebsd_fixup),
+ .sv_sendsig = sendsig,
+ .sv_sigcode = sigcode,
+ .sv_szsigcode = &szsigcode,
+ .sv_prepsyscall = NULL,
+ .sv_name = "FreeBSD ELF32",
+ .sv_coredump = __elfN(coredump),
+ .sv_imgact_try = NULL,
+ .sv_minsigstksz = MINSIGSTKSZ,
+ .sv_pagesize = PAGE_SIZE,
+ .sv_minuser = VM_MIN_ADDRESS,
+ .sv_maxuser = VM_MAXUSER_ADDRESS,
+ .sv_usrstack = USRSTACK,
+ .sv_psstrings = PS_STRINGS,
+ .sv_stackprot = VM_PROT_ALL,
+ .sv_copyout_strings = exec_copyout_strings,
+ .sv_setregs = exec_setregs,
+ .sv_fixlimit = NULL,
+ .sv_maxssiz = NULL,
+ .sv_flags = SV_ABI_FREEBSD | SV_ILP32,
+ .sv_set_syscall_retval = cpu_set_syscall_retval,
+ .sv_fetch_syscall_args = cpu_fetch_syscall_args,
+ .sv_syscallnames = syscallnames,
+ .sv_schedtail = NULL,
+ .sv_thread_detach = NULL,
+ .sv_trap = NULL,
+};
+
+static Elf32_Brandinfo freebsd_brand_info = {
+ .brand = ELFOSABI_FREEBSD,
+ .machine = EM_MIPS,
+ .compat_3_brand = "FreeBSD",
+ .emul_path = NULL,
+ .interp_path = "/libexec/ld-elf.so.1",
+ .sysvec = &elf32_freebsd_sysvec,
+ .interp_newpath = NULL,
+ .flags = 0
+};
+
+SYSINIT(elf32, SI_SUB_EXEC, SI_ORDER_FIRST,
+ (sysinit_cfunc_t) elf32_insert_brand_entry,
+ &freebsd_brand_info);
+
+void
+elf32_dump_thread(struct thread *td __unused, void *dst __unused,
+ size_t *off __unused)
+{
+}
+#endif
+
+/* Process one elf relocation with addend. */
+static int
+elf_reloc_internal(linker_file_t lf, Elf_Addr relocbase, const void *data,
+ int type, int local, elf_lookup_fn lookup)
+{
+ Elf32_Addr *where = (Elf32_Addr *)NULL;
+ Elf_Addr addr;
+ Elf_Addr addend = (Elf_Addr)0;
+ Elf_Word rtype = (Elf_Word)0, symidx;
+ const Elf_Rel *rel = NULL;
+ const Elf_Rela *rela = NULL;
+ int error;
+
+ /*
+ * Stash R_MIPS_HI16 info so we can use it when processing R_MIPS_LO16
+ */
+ static Elf_Addr ahl;
+ static Elf32_Addr *where_hi16;
+
+ switch (type) {
+ case ELF_RELOC_REL:
+ rel = (const Elf_Rel *)data;
+ where = (Elf32_Addr *) (relocbase + rel->r_offset);
+ rtype = ELF_R_TYPE(rel->r_info);
+ symidx = ELF_R_SYM(rel->r_info);
+ switch (rtype) {
+ case R_MIPS_64:
+ addend = *(Elf64_Addr *)where;
+ break;
+ default:
+ addend = *where;
+ break;
+ }
+
+ break;
+ case ELF_RELOC_RELA:
+ rela = (const Elf_Rela *)data;
+ where = (Elf32_Addr *) (relocbase + rela->r_offset);
+ addend = rela->r_addend;
+ rtype = ELF_R_TYPE(rela->r_info);
+ symidx = ELF_R_SYM(rela->r_info);
+ break;
+ default:
+ panic("unknown reloc type %d\n", type);
+ }
+
+ switch (rtype) {
+ case R_MIPS_NONE: /* none */
+ break;
+
+ case R_MIPS_32: /* S + A */
+ error = lookup(lf, symidx, 1, &addr);
+ if (error != 0)
+ return (-1);
+ addr += addend;
+ if (*where != addr)
+ *where = (Elf32_Addr)addr;
+ break;
+
+ case R_MIPS_26: /* ((A << 2) | (P & 0xf0000000) + S) >> 2 */
+ error = lookup(lf, symidx, 1, &addr);
+ if (error != 0)
+ return (-1);
+
+ addend &= 0x03ffffff;
+ /*
+ * Addendum for .rela R_MIPS_26 is not shifted right
+ */
+ if (rela == NULL)
+ addend <<= 2;
+
+ addr += ((Elf_Addr)where & 0xf0000000) | addend;
+ addr >>= 2;
+
+ *where &= ~0x03ffffff;
+ *where |= addr & 0x03ffffff;
+ break;
+
+ case R_MIPS_64: /* S + A */
+ error = lookup(lf, symidx, 1, &addr);
+ if (error != 0)
+ return (-1);
+ addr += addend;
+ if (*(Elf64_Addr*)where != addr)
+ *(Elf64_Addr*)where = addr;
+ break;
+
+ case R_MIPS_HI16: /* ((AHL + S) - ((short)(AHL + S)) >> 16 */
+ if (rela != NULL) {
+ error = lookup(lf, symidx, 1, &addr);
+ if (error != 0)
+ return (-1);
+ addr += addend;
+ *where &= 0xffff0000;
+ *where |= ((((long long) addr + 0x8000LL) >> 16) & 0xffff);
+ }
+ else {
+ ahl = addend << 16;
+ where_hi16 = where;
+ }
+ break;
+
+ case R_MIPS_LO16: /* AHL + S */
+ if (rela != NULL) {
+ error = lookup(lf, symidx, 1, &addr);
+ if (error != 0)
+ return (-1);
+ addr += addend;
+ *where &= 0xffff0000;
+ *where |= addr & 0xffff;
+ }
+ else {
+ ahl += (int16_t)addend;
+ error = lookup(lf, symidx, 1, &addr);
+ if (error != 0)
+ return (-1);
+
+ addend &= 0xffff0000;
+ addend |= (uint16_t)(ahl + addr);
+ *where = addend;
+
+ addend = *where_hi16;
+ addend &= 0xffff0000;
+ addend |= ((ahl + addr) - (int16_t)(ahl + addr)) >> 16;
+ *where_hi16 = addend;
+ }
+
+ break;
+
+ case R_MIPS_HIGHER: /* %higher(A+S) */
+ error = lookup(lf, symidx, 1, &addr);
+ if (error != 0)
+ return (-1);
+ addr += addend;
+ *where &= 0xffff0000;
+ *where |= (((long long)addr + 0x80008000LL) >> 32) & 0xffff;
+ break;
+
+ case R_MIPS_HIGHEST: /* %highest(A+S) */
+ error = lookup(lf, symidx, 1, &addr);
+ if (error != 0)
+ return (-1);
+ addr += addend;
+ *where &= 0xffff0000;
+ *where |= (((long long)addr + 0x800080008000LL) >> 48) & 0xffff;
+ break;
+
+ default:
+ printf("kldload: unexpected relocation type %d\n",
+ rtype);
+ return (-1);
+ }
+
+ return(0);
+}
+
+int
+elf_reloc(linker_file_t lf, Elf_Addr relocbase, const void *data, int type,
+ elf_lookup_fn lookup)
+{
+
+ return (elf_reloc_internal(lf, relocbase, data, type, 0, lookup));
+}
+
+int
+elf_reloc_local(linker_file_t lf, Elf_Addr relocbase, const void *data,
+ int type, elf_lookup_fn lookup)
+{
+
+ return (elf_reloc_internal(lf, relocbase, data, type, 1, lookup));
+}
+
+int
+elf_cpu_load_file(linker_file_t lf __unused)
+{
+
+ /*
+ * Sync the I and D caches to make sure our relocations are visible.
+ */
+ mips_icache_sync_all();
+
+ return (0);
+}
+
+int
+elf_cpu_unload_file(linker_file_t lf __unused)
+{
+
+ return (0);
+}
Property changes on: trunk/sys/mips/mips/elf_machdep.c
___________________________________________________________________
Added: svn:eol-style
## -0,0 +1 ##
+native
\ No newline at end of property
Added: svn:keywords
## -0,0 +1 ##
+MidnightBSD=%H
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+text/plain
\ No newline at end of property
Added: trunk/sys/mips/mips/elf_trampoline.c
===================================================================
--- trunk/sys/mips/mips/elf_trampoline.c (rev 0)
+++ trunk/sys/mips/mips/elf_trampoline.c 2018-05-26 21:55:02 UTC (rev 9987)
@@ -0,0 +1,225 @@
+/* $MidnightBSD$ */
+/*-
+ * Copyright (c) 2005 Olivier Houchard. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+ * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+ * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <sys/cdefs.h>
+__FBSDID("$FreeBSD: stable/10/sys/mips/mips/elf_trampoline.c 256171 2013-10-09 00:22:21Z adrian $");
+#include <machine/asm.h>
+#include <sys/param.h>
+
+#if ELFSIZE == 64
+#include <sys/elf64.h>
+#else
+#include <sys/elf32.h>
+#endif
+
+/*
+ * Since we are compiled outside of the normal kernel build process, we
+ * need to include opt_global.h manually.
+ */
+#include "opt_global.h"
+
+#include <sys/inflate.h>
+#include <machine/elf.h>
+#include <machine/cpufunc.h>
+#include <machine/stdarg.h>
+
+#ifndef KERNNAME
+#error Kernel name not provided
+#endif
+
+extern char kernel_start[];
+extern char kernel_end[];
+
+static __inline void *
+memcpy(void *dst, const void *src, size_t len)
+{
+ const char *s = src;
+ char *d = dst;
+
+ while (len) {
+ if (0 && len >= 4 && !((vm_offset_t)d & 3) &&
+ !((vm_offset_t)s & 3)) {
+ *(uint32_t *)d = *(uint32_t *)s;
+ s += 4;
+ d += 4;
+ len -= 4;
+ } else {
+ *d++ = *s++;
+ len--;
+ }
+ }
+ return (dst);
+}
+
+static __inline void
+bzero(void *addr, size_t count)
+{
+ char *tmp = (char *)addr;
+
+ while (count > 0) {
+ if (count >= 4 && !((vm_offset_t)tmp & 3)) {
+ *(uint32_t *)tmp = 0;
+ tmp += 4;
+ count -= 4;
+ } else {
+ *tmp = 0;
+ tmp++;
+ count--;
+ }
+ }
+}
+
+/*
+ * Convert number to pointer, truncate on 64->32 case, sign extend
+ * in 32->64 case
+ */
+#define mkptr(x) ((void *)(intptr_t)(int)(x))
+
+/*
+ * Relocate PT_LOAD segements of kernel ELF image to their respective
+ * virtual addresses and return entry point
+ */
+void *
+load_kernel(void * kstart)
+{
+#if ELFSIZE == 64
+ Elf64_Ehdr *eh;
+ Elf64_Phdr phdr[64] /* XXX */;
+ Elf64_Shdr shdr[64] /* XXX */;
+#else
+ Elf32_Ehdr *eh;
+ Elf32_Phdr phdr[64] /* XXX */;
+ Elf32_Shdr shdr[64] /* XXX */;
+#endif
+ int i, j;
+ void *entry_point;
+ vm_offset_t loadend = 0;
+ intptr_t lastaddr;
+ int symtabindex = -1;
+ int symstrindex = -1;
+ Elf_Size tmp;
+
+#if ELFSIZE == 64
+ eh = (Elf64_Ehdr *)kstart;
+#else
+ eh = (Elf32_Ehdr *)kstart;
+#endif
+ entry_point = mkptr(eh->e_entry);
+ memcpy(phdr, (void *)(kstart + eh->e_phoff),
+ eh->e_phnum * sizeof(phdr[0]));
+
+ memcpy(shdr, (void *)(kstart + eh->e_shoff),
+ sizeof(*shdr) * eh->e_shnum);
+
+ if (eh->e_shnum * eh->e_shentsize != 0 && eh->e_shoff != 0) {
+ for (i = 0; i < eh->e_shnum; i++) {
+ if (shdr[i].sh_type == SHT_SYMTAB) {
+ /*
+ * XXX: check if .symtab is in PT_LOAD?
+ */
+ if (shdr[i].sh_offset != 0 &&
+ shdr[i].sh_size != 0) {
+ symtabindex = i;
+ symstrindex = shdr[i].sh_link;
+ }
+ }
+ }
+ }
+
+ /*
+ * Copy loadable segments
+ */
+ for (i = 0; i < eh->e_phnum; i++) {
+ volatile char c;
+
+ if (phdr[i].p_type != PT_LOAD)
+ continue;
+
+ memcpy(mkptr(phdr[i].p_vaddr),
+ (void*)(kstart + phdr[i].p_offset), phdr[i].p_filesz);
+
+ /* Clean space from oversized segments, eg: bss. */
+ if (phdr[i].p_filesz < phdr[i].p_memsz)
+ bzero(mkptr(phdr[i].p_vaddr + phdr[i].p_filesz),
+ phdr[i].p_memsz - phdr[i].p_filesz);
+
+ if (loadend < phdr[i].p_vaddr + phdr[i].p_memsz)
+ loadend = phdr[i].p_vaddr + phdr[i].p_memsz;
+ }
+
+ /* Now grab the symbol tables. */
+ lastaddr = (intptr_t)(int)loadend;
+ if (symtabindex >= 0 && symstrindex >= 0) {
+ tmp = SYMTAB_MAGIC;
+ memcpy((void *)lastaddr, &tmp, sizeof(tmp));
+ lastaddr += sizeof(Elf_Size);
+ tmp = shdr[symtabindex].sh_size +
+ shdr[symstrindex].sh_size + 2*sizeof(Elf_Size);
+ memcpy((void *)lastaddr, &tmp, sizeof(tmp));
+ lastaddr += sizeof(Elf_Size);
+ /* .symtab size */
+ tmp = shdr[symtabindex].sh_size;
+ memcpy((void *)lastaddr, &tmp, sizeof(tmp));
+ lastaddr += sizeof(shdr[symtabindex].sh_size);
+ /* .symtab data */
+ memcpy((void*)lastaddr,
+ shdr[symtabindex].sh_offset + kstart,
+ shdr[symtabindex].sh_size);
+ lastaddr += shdr[symtabindex].sh_size;
+
+ /* .strtab size */
+ tmp = shdr[symstrindex].sh_size;
+ memcpy((void *)lastaddr, &tmp, sizeof(tmp));
+ lastaddr += sizeof(shdr[symstrindex].sh_size);
+
+ /* .strtab data */
+ memcpy((void*)lastaddr,
+ shdr[symstrindex].sh_offset + kstart,
+ shdr[symstrindex].sh_size);
+ } else {
+ /* Do not take any chances */
+ tmp = 0;
+ memcpy((void *)lastaddr, &tmp, sizeof(tmp));
+ }
+
+ return entry_point;
+}
+
+void
+_startC(register_t a0, register_t a1, register_t a2, register_t a3)
+{
+ unsigned int * code;
+ int i;
+ void (*entry_point)(register_t, register_t, register_t, register_t);
+
+ /*
+ * Relocate segment to the predefined memory location
+ * Most likely it will be KSEG0/KSEG1 address
+ */
+ entry_point = load_kernel(kernel_start);
+
+ /* Pass saved registers to original _start */
+ entry_point(a0, a1, a2, a3);
+}
Property changes on: trunk/sys/mips/mips/elf_trampoline.c
___________________________________________________________________
Added: svn:eol-style
## -0,0 +1 ##
+native
\ No newline at end of property
Added: svn:keywords
## -0,0 +1 ##
+MidnightBSD=%H
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+text/plain
\ No newline at end of property
Added: trunk/sys/mips/mips/exception.S
===================================================================
--- trunk/sys/mips/mips/exception.S (rev 0)
+++ trunk/sys/mips/mips/exception.S 2018-05-26 21:55:02 UTC (rev 9987)
@@ -0,0 +1,1262 @@
+/* $MidnightBSD$ */
+/* $OpenBSD: locore.S,v 1.18 1998/09/15 10:58:53 pefo Exp $ */
+/*-
+ * Copyright (c) 1992, 1993
+ * The Regents of the University of California. All rights reserved.
+ *
+ * This code is derived from software contributed to Berkeley by
+ * Digital Equipment Corporation and Ralph Campbell.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * 4. Neither the name of the University nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ * Copyright (C) 1989 Digital Equipment Corporation.
+ * Permission to use, copy, modify, and distribute this software and
+ * its documentation for any purpose and without fee is hereby granted,
+ * provided that the above copyright notice appears in all copies.
+ * Digital Equipment Corporation makes no representations about the
+ * suitability of this software for any purpose. It is provided "as is"
+ * without express or implied warranty.
+ *
+ * from: Header: /sprite/src/kernel/mach/ds3100.md/RCS/loMem.s,
+ * v 1.1 89/07/11 17:55:04 nelson Exp SPRITE (DECWRL)
+ * from: Header: /sprite/src/kernel/mach/ds3100.md/RCS/machAsm.s,
+ * v 9.2 90/01/29 18:00:39 shirriff Exp SPRITE (DECWRL)
+ * from: Header: /sprite/src/kernel/vm/ds3100.md/vmPmaxAsm.s,
+ * v 1.1 89/07/10 14:27:41 nelson Exp SPRITE (DECWRL)
+ * from: @(#)locore.s 8.5 (Berkeley) 1/4/94
+ * JNPR: exception.S,v 1.5 2007/01/08 04:58:37 katta
+ * $FreeBSD: stable/10/sys/mips/mips/exception.S 233412 2012-03-24 05:17:38Z gonzo $
+ */
+
+/*
+ * Contains code that is the first executed at boot time plus
+ * assembly language support routines.
+ */
+
+#include "opt_ddb.h"
+#include "opt_kdtrace.h"
+#include <machine/asm.h>
+#include <machine/cpu.h>
+#include <machine/regnum.h>
+#include <machine/cpuregs.h>
+#include <machine/pte.h>
+
+#include "assym.s"
+
+ .set noreorder # Noreorder is default style!
+
+#ifdef KDTRACE_HOOKS
+ .data
+ .globl dtrace_invop_jump_addr
+ .align 4
+ .type dtrace_invop_jump_addr, @object
+ .size dtrace_invop_jump_addr, 8
+dtrace_invop_jump_addr:
+ .word 0
+ .word 0
+ .globl dtrace_invop_calltrap_addr
+ .align 4
+ .type dtrace_invop_calltrap_addr, @object
+ .size dtrace_invop_calltrap_addr, 8
+dtrace_invop_calltrap_addr:
+ .word 0
+ .word 0
+
+ .text
+#endif
+
+/*
+ * Reasonable limit
+ */
+#define INTRCNT_COUNT 256
+
+
+/*
+ *----------------------------------------------------------------------------
+ *
+ * MipsTLBMiss --
+ *
+ * Vector code for the TLB-miss exception vector 0x80000000.
+ *
+ * This code is copied to the TLB exception vector address to
+ * which the CPU jumps in response to an exception or a TLB miss.
+ * NOTE: This code must be position independent!!!
+ *
+ *
+ */
+VECTOR(MipsTLBMiss, unknown)
+ .set push
+ .set noat
+ j MipsDoTLBMiss
+ MFC0 k0, MIPS_COP_0_BAD_VADDR # get the fault address
+ .set pop
+VECTOR_END(MipsTLBMiss)
+
+/*
+ *----------------------------------------------------------------------------
+ *
+ * MipsDoTLBMiss --
+ *
+ * This is the real TLB Miss Handler code.
+ * 'segbase' points to the base of the segment table for user processes.
+ *
+ * Don't check for invalid pte's here. We load them as well and
+ * let the processor trap to load the correct value after service.
+ *----------------------------------------------------------------------------
+ */
+ .set push
+ .set noat
+MipsDoTLBMiss:
+ bltz k0, 1f #02: k0<0 -> 1f (kernel fault)
+ PTR_SRL k0, k0, SEGSHIFT - PTRSHIFT #03: k0=seg offset (almost)
+
+ GET_CPU_PCPU(k1)
+ PTR_L k1, PC_SEGBASE(k1)
+ beqz k1, 2f #05: make sure segbase is not null
+ andi k0, k0, PDEPTRMASK #06: k0=seg offset
+ PTR_ADDU k1, k0, k1 #07: k1=seg entry address
+
+ PTR_L k1, 0(k1) #08: k1=seg entry
+ MFC0 k0, MIPS_COP_0_BAD_VADDR #09: k0=bad address (again)
+ beq k1, zero, 2f #0a: ==0 -- no page table
+#ifdef __mips_n64
+ PTR_SRL k0, PDRSHIFT - PTRSHIFT # k0=VPN
+ andi k0, k0, PDEPTRMASK # k0=pde offset
+ PTR_ADDU k1, k0, k1 # k1=pde entry address
+ PTR_L k1, 0(k1) # k1=pde entry
+ MFC0 k0, MIPS_COP_0_BAD_VADDR # k0=bad address (again)
+ beq k1, zero, 2f # ==0 -- no page table
+#endif
+ PTR_SRL k0, PAGE_SHIFT - PTESHIFT #0b: k0=VPN (aka va>>10)
+ andi k0, k0, PTE2MASK #0c: k0=page tab offset
+ PTR_ADDU k1, k1, k0 #0d: k1=pte address
+ PTE_L k0, 0(k1) #0e: k0=lo0 pte
+ PTE_L k1, PTESIZE(k1) #0f: k1=lo0 pte
+ CLEAR_PTE_SWBITS(k0)
+ PTE_MTC0 k0, MIPS_COP_0_TLB_LO0 #12: lo0 is loaded
+ COP0_SYNC
+ CLEAR_PTE_SWBITS(k1)
+ PTE_MTC0 k1, MIPS_COP_0_TLB_LO1 #15: lo1 is loaded
+ COP0_SYNC
+ tlbwr #1a: write to tlb
+ HAZARD_DELAY
+ eret #1f: retUrn from exception
+1: j MipsTLBMissException #20: kernel exception
+ nop #21: branch delay slot
+2: j SlowFault #22: no page table present
+ nop #23: branch delay slot
+ .set pop
+
+/*
+ * This code is copied to the general exception vector address to
+ * handle all execptions except RESET and TLBMiss.
+ * NOTE: This code must be position independent!!!
+ */
+VECTOR(MipsException, unknown)
+/*
+ * Find out what mode we came from and jump to the proper handler.
+ */
+ .set noat
+ mfc0 k0, MIPS_COP_0_STATUS # Get the status register
+ mfc0 k1, MIPS_COP_0_CAUSE # Get the cause register value.
+ and k0, k0, MIPS_SR_KSU_USER # test for user mode
+ # sneaky but the bits are
+ # with us........
+ sll k0, k0, 3 # shift user bit for cause index
+ and k1, k1, MIPS_CR_EXC_CODE # Mask out the cause bits.
+ or k1, k1, k0 # change index to user table
+#if defined(__mips_n64)
+ PTR_SLL k1, k1, 1 # shift to get 8-byte offset
+#endif
+1:
+ PTR_LA k0, _C_LABEL(machExceptionTable) # get base of the jump table
+ PTR_ADDU k0, k0, k1 # Get the address of the
+ # function entry. Note that
+ # the cause is already
+ # shifted left by 2 bits so
+ # we dont have to shift.
+ PTR_L k0, 0(k0) # Get the function address
+ nop
+ j k0 # Jump to the function.
+ nop
+ .set at
+VECTOR_END(MipsException)
+
+/*
+ * We couldn't find a TLB entry.
+ * Find out what mode we came from and call the appropriate handler.
+ */
+SlowFault:
+ .set noat
+ mfc0 k0, MIPS_COP_0_STATUS
+ nop
+ and k0, k0, MIPS_SR_KSU_USER
+ bne k0, zero, _C_LABEL(MipsUserGenException)
+ nop
+ .set at
+/*
+ * Fall though ...
+ */
+
+/*----------------------------------------------------------------------------
+ *
+ * MipsKernGenException --
+ *
+ * Handle an exception from kernel mode.
+ *
+ * Results:
+ * None.
+ *
+ * Side effects:
+ * None.
+ *
+ *----------------------------------------------------------------------------
+ */
+
+#define SAVE_REG(reg, offs, base) \
+ REG_S reg, CALLFRAME_SIZ + (SZREG * offs) (base)
+
+#if defined(CPU_CNMIPS)
+#define CLEAR_STATUS \
+ mfc0 a0, MIPS_COP_0_STATUS ;\
+ li a2, (MIPS_SR_KX | MIPS_SR_SX | MIPS_SR_UX) ; \
+ or a0, a0, a2 ; \
+ li a2, ~(MIPS_SR_INT_IE | MIPS_SR_EXL | MIPS_SR_KSU_USER) ; \
+ and a0, a0, a2 ; \
+ mtc0 a0, MIPS_COP_0_STATUS ; \
+ ITLBNOPFIX
+#elif defined(CPU_RMI) || defined(CPU_NLM)
+#define CLEAR_STATUS \
+ mfc0 a0, MIPS_COP_0_STATUS ;\
+ li a2, (MIPS_SR_KX | MIPS_SR_UX | MIPS_SR_COP_2_BIT) ; \
+ or a0, a0, a2 ; \
+ li a2, ~(MIPS_SR_INT_IE | MIPS_SR_EXL | MIPS_SR_KSU_USER) ; \
+ and a0, a0, a2 ; \
+ mtc0 a0, MIPS_COP_0_STATUS ; \
+ ITLBNOPFIX
+#else
+#define CLEAR_STATUS \
+ mfc0 a0, MIPS_COP_0_STATUS ;\
+ li a2, ~(MIPS_SR_INT_IE | MIPS_SR_EXL | MIPS_SR_KSU_USER) ; \
+ and a0, a0, a2 ; \
+ mtc0 a0, MIPS_COP_0_STATUS ; \
+ ITLBNOPFIX
+#endif
+
+/*
+ * Save CPU and CP0 register state.
+ *
+ * This is straightforward except for saving the exception program
+ * counter. The ddb backtrace code looks for the first instruction
+ * matching the form "sw ra, (off)sp" to figure out the address of the
+ * calling function. So we must make sure that we save the exception
+ * PC by staging it through 'ra' as opposed to any other register.
+ */
+#define SAVE_CPU \
+ SAVE_REG(AT, AST, sp) ;\
+ .set at ; \
+ SAVE_REG(v0, V0, sp) ;\
+ SAVE_REG(v1, V1, sp) ;\
+ SAVE_REG(a0, A0, sp) ;\
+ SAVE_REG(a1, A1, sp) ;\
+ SAVE_REG(a2, A2, sp) ;\
+ SAVE_REG(a3, A3, sp) ;\
+ SAVE_REG(t0, T0, sp) ;\
+ SAVE_REG(t1, T1, sp) ;\
+ SAVE_REG(t2, T2, sp) ;\
+ SAVE_REG(t3, T3, sp) ;\
+ SAVE_REG(ta0, TA0, sp) ;\
+ SAVE_REG(ta1, TA1, sp) ;\
+ SAVE_REG(ta2, TA2, sp) ;\
+ SAVE_REG(ta3, TA3, sp) ;\
+ SAVE_REG(t8, T8, sp) ;\
+ SAVE_REG(t9, T9, sp) ;\
+ SAVE_REG(gp, GP, sp) ;\
+ SAVE_REG(s0, S0, sp) ;\
+ SAVE_REG(s1, S1, sp) ;\
+ SAVE_REG(s2, S2, sp) ;\
+ SAVE_REG(s3, S3, sp) ;\
+ SAVE_REG(s4, S4, sp) ;\
+ SAVE_REG(s5, S5, sp) ;\
+ SAVE_REG(s6, S6, sp) ;\
+ SAVE_REG(s7, S7, sp) ;\
+ SAVE_REG(s8, S8, sp) ;\
+ mflo v0 ;\
+ mfhi v1 ;\
+ mfc0 a0, MIPS_COP_0_STATUS ;\
+ mfc0 a1, MIPS_COP_0_CAUSE ;\
+ MFC0 a2, MIPS_COP_0_BAD_VADDR;\
+ MFC0 a3, MIPS_COP_0_EXC_PC ;\
+ SAVE_REG(v0, MULLO, sp) ;\
+ SAVE_REG(v1, MULHI, sp) ;\
+ SAVE_REG(a0, SR, sp) ;\
+ SAVE_REG(a1, CAUSE, sp) ;\
+ SAVE_REG(a2, BADVADDR, sp) ;\
+ move t0, ra ;\
+ move ra, a3 ;\
+ SAVE_REG(ra, PC, sp) ;\
+ move ra, t0 ;\
+ SAVE_REG(ra, RA, sp) ;\
+ PTR_ADDU v0, sp, KERN_EXC_FRAME_SIZE ;\
+ SAVE_REG(v0, SP, sp) ;\
+ CLEAR_STATUS ;\
+ PTR_ADDU a0, sp, CALLFRAME_SIZ ;\
+ ITLBNOPFIX
+
+#define RESTORE_REG(reg, offs, base) \
+ REG_L reg, CALLFRAME_SIZ + (SZREG * offs) (base)
+
+#define RESTORE_CPU \
+ CLEAR_STATUS ;\
+ RESTORE_REG(k0, SR, sp) ;\
+ RESTORE_REG(t0, MULLO, sp) ;\
+ RESTORE_REG(t1, MULHI, sp) ;\
+ mtlo t0 ;\
+ mthi t1 ;\
+ MTC0 v0, MIPS_COP_0_EXC_PC ;\
+ .set noat ;\
+ RESTORE_REG(AT, AST, sp) ;\
+ RESTORE_REG(v0, V0, sp) ;\
+ RESTORE_REG(v1, V1, sp) ;\
+ RESTORE_REG(a0, A0, sp) ;\
+ RESTORE_REG(a1, A1, sp) ;\
+ RESTORE_REG(a2, A2, sp) ;\
+ RESTORE_REG(a3, A3, sp) ;\
+ RESTORE_REG(t0, T0, sp) ;\
+ RESTORE_REG(t1, T1, sp) ;\
+ RESTORE_REG(t2, T2, sp) ;\
+ RESTORE_REG(t3, T3, sp) ;\
+ RESTORE_REG(ta0, TA0, sp) ;\
+ RESTORE_REG(ta1, TA1, sp) ;\
+ RESTORE_REG(ta2, TA2, sp) ;\
+ RESTORE_REG(ta3, TA3, sp) ;\
+ RESTORE_REG(t8, T8, sp) ;\
+ RESTORE_REG(t9, T9, sp) ;\
+ RESTORE_REG(s0, S0, sp) ;\
+ RESTORE_REG(s1, S1, sp) ;\
+ RESTORE_REG(s2, S2, sp) ;\
+ RESTORE_REG(s3, S3, sp) ;\
+ RESTORE_REG(s4, S4, sp) ;\
+ RESTORE_REG(s5, S5, sp) ;\
+ RESTORE_REG(s6, S6, sp) ;\
+ RESTORE_REG(s7, S7, sp) ;\
+ RESTORE_REG(s8, S8, sp) ;\
+ RESTORE_REG(gp, GP, sp) ;\
+ RESTORE_REG(ra, RA, sp) ;\
+ PTR_ADDU sp, sp, KERN_EXC_FRAME_SIZE;\
+ mtc0 k0, MIPS_COP_0_STATUS
+
+
+/*
+ * The kernel exception stack contains 18 saved general registers,
+ * the status register and the multiply lo and high registers.
+ * In addition, we set this up for linkage conventions.
+ */
+#define KERN_REG_SIZE (NUMSAVEREGS * SZREG)
+#define KERN_EXC_FRAME_SIZE (CALLFRAME_SIZ + KERN_REG_SIZE + 16)
+
+NNON_LEAF(MipsKernGenException, KERN_EXC_FRAME_SIZE, ra)
+ .set noat
+ PTR_SUBU sp, sp, KERN_EXC_FRAME_SIZE
+ .mask 0x80000000, (CALLFRAME_RA - KERN_EXC_FRAME_SIZE)
+/*
+ * Save CPU state, building 'frame'.
+ */
+ SAVE_CPU
+/*
+ * Call the exception handler. a0 points at the saved frame.
+ */
+ PTR_LA gp, _C_LABEL(_gp)
+ PTR_LA k0, _C_LABEL(trap)
+ jalr k0
+ REG_S a3, CALLFRAME_RA + KERN_REG_SIZE(sp) # for debugging
+
+ /*
+ * Update interrupt and CPU mask in saved status register
+ * Some of interrupts could be disabled by
+ * intr filters if interrupts are enabled later
+ * in trap handler
+ */
+ mfc0 a0, MIPS_COP_0_STATUS
+ and a0, a0, (MIPS_SR_INT_MASK|MIPS_SR_COP_USABILITY)
+ RESTORE_REG(a1, SR, sp)
+ and a1, a1, ~(MIPS_SR_INT_MASK|MIPS_SR_COP_USABILITY)
+ or a1, a1, a0
+ SAVE_REG(a1, SR, sp)
+ RESTORE_CPU # v0 contains the return address.
+ sync
+ eret
+ .set at
+END(MipsKernGenException)
+
+
+#define SAVE_U_PCB_REG(reg, offs, base) \
+ REG_S reg, U_PCB_REGS + (SZREG * offs) (base)
+
+#define RESTORE_U_PCB_REG(reg, offs, base) \
+ REG_L reg, U_PCB_REGS + (SZREG * offs) (base)
+
+/*----------------------------------------------------------------------------
+ *
+ * MipsUserGenException --
+ *
+ * Handle an exception from user mode.
+ *
+ * Results:
+ * None.
+ *
+ * Side effects:
+ * None.
+ *
+ *----------------------------------------------------------------------------
+ */
+NNON_LEAF(MipsUserGenException, CALLFRAME_SIZ, ra)
+ .set noat
+ .mask 0x80000000, (CALLFRAME_RA - CALLFRAME_SIZ)
+/*
+ * Save all of the registers except for the kernel temporaries in u.u_pcb.
+ */
+ GET_CPU_PCPU(k1)
+ PTR_L k1, PC_CURPCB(k1)
+ SAVE_U_PCB_REG(AT, AST, k1)
+ .set at
+ SAVE_U_PCB_REG(v0, V0, k1)
+ SAVE_U_PCB_REG(v1, V1, k1)
+ SAVE_U_PCB_REG(a0, A0, k1)
+ mflo v0
+ SAVE_U_PCB_REG(a1, A1, k1)
+ SAVE_U_PCB_REG(a2, A2, k1)
+ SAVE_U_PCB_REG(a3, A3, k1)
+ SAVE_U_PCB_REG(t0, T0, k1)
+ mfhi v1
+ SAVE_U_PCB_REG(t1, T1, k1)
+ SAVE_U_PCB_REG(t2, T2, k1)
+ SAVE_U_PCB_REG(t3, T3, k1)
+ SAVE_U_PCB_REG(ta0, TA0, k1)
+ mfc0 a0, MIPS_COP_0_STATUS # First arg is the status reg.
+ SAVE_U_PCB_REG(ta1, TA1, k1)
+ SAVE_U_PCB_REG(ta2, TA2, k1)
+ SAVE_U_PCB_REG(ta3, TA3, k1)
+ SAVE_U_PCB_REG(s0, S0, k1)
+ mfc0 a1, MIPS_COP_0_CAUSE # Second arg is the cause reg.
+ SAVE_U_PCB_REG(s1, S1, k1)
+ SAVE_U_PCB_REG(s2, S2, k1)
+ SAVE_U_PCB_REG(s3, S3, k1)
+ SAVE_U_PCB_REG(s4, S4, k1)
+ MFC0 a2, MIPS_COP_0_BAD_VADDR # Third arg is the fault addr
+ SAVE_U_PCB_REG(s5, S5, k1)
+ SAVE_U_PCB_REG(s6, S6, k1)
+ SAVE_U_PCB_REG(s7, S7, k1)
+ SAVE_U_PCB_REG(t8, T8, k1)
+ MFC0 a3, MIPS_COP_0_EXC_PC # Fourth arg is the pc.
+ SAVE_U_PCB_REG(t9, T9, k1)
+ SAVE_U_PCB_REG(gp, GP, k1)
+ SAVE_U_PCB_REG(sp, SP, k1)
+ SAVE_U_PCB_REG(s8, S8, k1)
+ PTR_SUBU sp, k1, CALLFRAME_SIZ # switch to kernel SP
+ SAVE_U_PCB_REG(ra, RA, k1)
+ SAVE_U_PCB_REG(v0, MULLO, k1)
+ SAVE_U_PCB_REG(v1, MULHI, k1)
+ SAVE_U_PCB_REG(a0, SR, k1)
+ SAVE_U_PCB_REG(a1, CAUSE, k1)
+ SAVE_U_PCB_REG(a2, BADVADDR, k1)
+ SAVE_U_PCB_REG(a3, PC, k1)
+ REG_S a3, CALLFRAME_RA(sp) # for debugging
+ PTR_LA gp, _C_LABEL(_gp) # switch to kernel GP
+# Turn off fpu and enter kernel mode
+ and t0, a0, ~(MIPS_SR_COP_1_BIT | MIPS_SR_EXL | MIPS_SR_KSU_MASK | MIPS_SR_INT_IE)
+#if defined(CPU_CNMIPS)
+ and t0, t0, ~(MIPS_SR_COP_2_BIT)
+ or t0, t0, (MIPS_SR_KX | MIPS_SR_SX | MIPS_SR_UX | MIPS_SR_PX)
+#elif defined(CPU_RMI) || defined(CPU_NLM)
+ or t0, t0, (MIPS_SR_KX | MIPS_SR_UX | MIPS_SR_COP_2_BIT)
+#endif
+ mtc0 t0, MIPS_COP_0_STATUS
+ PTR_ADDU a0, k1, U_PCB_REGS
+ ITLBNOPFIX
+
+/*
+ * Call the exception handler.
+ */
+ PTR_LA k0, _C_LABEL(trap)
+ jalr k0
+ nop
+
+/*
+ * Restore user registers and return.
+ * First disable interrupts and set exeption level.
+ */
+ DO_AST
+
+ CLEAR_STATUS
+
+/*
+ * The use of k1 for storing the PCB pointer must be done only
+ * after interrupts are disabled. Otherwise it will get overwritten
+ * by the interrupt code.
+ */
+ GET_CPU_PCPU(k1)
+ PTR_L k1, PC_CURPCB(k1)
+
+ /*
+ * Update interrupt mask in saved status register
+ * Some of interrupts could be enabled by ithread
+ * scheduled by ast()
+ */
+ mfc0 a0, MIPS_COP_0_STATUS
+ and a0, a0, MIPS_SR_INT_MASK
+ RESTORE_U_PCB_REG(a1, SR, k1)
+ and a1, a1, ~MIPS_SR_INT_MASK
+ or a1, a1, a0
+ SAVE_U_PCB_REG(a1, SR, k1)
+
+ RESTORE_U_PCB_REG(t0, MULLO, k1)
+ RESTORE_U_PCB_REG(t1, MULHI, k1)
+ mtlo t0
+ mthi t1
+ RESTORE_U_PCB_REG(a0, PC, k1)
+ RESTORE_U_PCB_REG(v0, V0, k1)
+ MTC0 a0, MIPS_COP_0_EXC_PC # set return address
+ RESTORE_U_PCB_REG(v1, V1, k1)
+ RESTORE_U_PCB_REG(a0, A0, k1)
+ RESTORE_U_PCB_REG(a1, A1, k1)
+ RESTORE_U_PCB_REG(a2, A2, k1)
+ RESTORE_U_PCB_REG(a3, A3, k1)
+ RESTORE_U_PCB_REG(t0, T0, k1)
+ RESTORE_U_PCB_REG(t1, T1, k1)
+ RESTORE_U_PCB_REG(t2, T2, k1)
+ RESTORE_U_PCB_REG(t3, T3, k1)
+ RESTORE_U_PCB_REG(ta0, TA0, k1)
+ RESTORE_U_PCB_REG(ta1, TA1, k1)
+ RESTORE_U_PCB_REG(ta2, TA2, k1)
+ RESTORE_U_PCB_REG(ta3, TA3, k1)
+ RESTORE_U_PCB_REG(s0, S0, k1)
+ RESTORE_U_PCB_REG(s1, S1, k1)
+ RESTORE_U_PCB_REG(s2, S2, k1)
+ RESTORE_U_PCB_REG(s3, S3, k1)
+ RESTORE_U_PCB_REG(s4, S4, k1)
+ RESTORE_U_PCB_REG(s5, S5, k1)
+ RESTORE_U_PCB_REG(s6, S6, k1)
+ RESTORE_U_PCB_REG(s7, S7, k1)
+ RESTORE_U_PCB_REG(t8, T8, k1)
+ RESTORE_U_PCB_REG(t9, T9, k1)
+ RESTORE_U_PCB_REG(gp, GP, k1)
+ RESTORE_U_PCB_REG(sp, SP, k1)
+ RESTORE_U_PCB_REG(k0, SR, k1)
+ RESTORE_U_PCB_REG(s8, S8, k1)
+ RESTORE_U_PCB_REG(ra, RA, k1)
+ .set noat
+ RESTORE_U_PCB_REG(AT, AST, k1)
+
+ mtc0 k0, MIPS_COP_0_STATUS # still exception level
+ ITLBNOPFIX
+ sync
+ eret
+ .set at
+END(MipsUserGenException)
+
+ .set push
+ .set noat
+NON_LEAF(mips_wait, CALLFRAME_SIZ, ra)
+ PTR_SUBU sp, sp, CALLFRAME_SIZ
+ .mask 0x80000000, (CALLFRAME_RA - CALLFRAME_SIZ)
+ REG_S ra, CALLFRAME_RA(sp) # save RA
+ mfc0 t0, MIPS_COP_0_STATUS
+ xori t1, t0, MIPS_SR_INT_IE
+ mtc0 t1, MIPS_COP_0_STATUS
+ COP0_SYNC
+ jal sched_runnable
+ nop
+ REG_L ra, CALLFRAME_RA(sp)
+ mfc0 t0, MIPS_COP_0_STATUS
+ ori t1, t0, MIPS_SR_INT_IE
+ .align 4
+GLOBAL(MipsWaitStart) # this is 16 byte aligned
+ mtc0 t1, MIPS_COP_0_STATUS
+ bnez v0, MipsWaitEnd
+ nop
+ wait
+GLOBAL(MipsWaitEnd) # MipsWaitStart + 16
+ jr ra
+ PTR_ADDU sp, sp, CALLFRAME_SIZ
+END(mips_wait)
+ .set pop
+
+/*----------------------------------------------------------------------------
+ *
+ * MipsKernIntr --
+ *
+ * Handle an interrupt from kernel mode.
+ * Interrupts use the standard kernel stack.
+ * switch_exit sets up a kernel stack after exit so interrupts won't fail.
+ *
+ * Results:
+ * None.
+ *
+ * Side effects:
+ * None.
+ *
+ *----------------------------------------------------------------------------
+ */
+
+NNON_LEAF(MipsKernIntr, KERN_EXC_FRAME_SIZE, ra)
+ .set noat
+ PTR_SUBU sp, sp, KERN_EXC_FRAME_SIZE
+ .mask 0x80000000, (CALLFRAME_RA - KERN_EXC_FRAME_SIZE)
+
+/*
+ * Check for getting interrupts just before wait
+ */
+ MFC0 k0, MIPS_COP_0_EXC_PC
+ ori k0, 0xf
+ xori k0, 0xf # 16 byte align
+ PTR_LA k1, MipsWaitStart
+ bne k0, k1, 1f
+ nop
+ PTR_ADDU k1, 16 # skip over wait
+ MTC0 k1, MIPS_COP_0_EXC_PC
+1:
+/*
+ * Save CPU state, building 'frame'.
+ */
+ SAVE_CPU
+/*
+ * Call the interrupt handler. a0 points at the saved frame.
+ */
+ PTR_LA gp, _C_LABEL(_gp)
+ PTR_LA k0, _C_LABEL(cpu_intr)
+ jalr k0
+ REG_S a3, CALLFRAME_RA + KERN_REG_SIZE(sp) # for debugging
+
+ /*
+ * Update interrupt and CPU mask in saved status register
+ * Some of interrupts could be disabled by
+ * intr filters if interrupts are enabled later
+ * in trap handler
+ */
+ mfc0 a0, MIPS_COP_0_STATUS
+ and a0, a0, (MIPS_SR_INT_MASK|MIPS_SR_COP_USABILITY)
+ RESTORE_REG(a1, SR, sp)
+ and a1, a1, ~(MIPS_SR_INT_MASK|MIPS_SR_COP_USABILITY)
+ or a1, a1, a0
+ SAVE_REG(a1, SR, sp)
+ REG_L v0, CALLFRAME_RA + KERN_REG_SIZE(sp)
+ RESTORE_CPU # v0 contains the return address.
+ sync
+ eret
+ .set at
+END(MipsKernIntr)
+
+/*----------------------------------------------------------------------------
+ *
+ * MipsUserIntr --
+ *
+ * Handle an interrupt from user mode.
+ * Note: we save minimal state in the u.u_pcb struct and use the standard
+ * kernel stack since there has to be a u page if we came from user mode.
+ * If there is a pending software interrupt, then save the remaining state
+ * and call softintr(). This is all because if we call switch() inside
+ * interrupt(), not all the user registers have been saved in u.u_pcb.
+ *
+ * Results:
+ * None.
+ *
+ * Side effects:
+ * None.
+ *
+ *----------------------------------------------------------------------------
+ */
+NNON_LEAF(MipsUserIntr, CALLFRAME_SIZ, ra)
+ .set noat
+ .mask 0x80000000, (CALLFRAME_RA - CALLFRAME_SIZ)
+/*
+ * Save the relevant user registers into the u.u_pcb struct.
+ * We don't need to save s0 - s8 because the compiler does it for us.
+ */
+ GET_CPU_PCPU(k1)
+ PTR_L k1, PC_CURPCB(k1)
+ SAVE_U_PCB_REG(AT, AST, k1)
+ .set at
+ SAVE_U_PCB_REG(v0, V0, k1)
+ SAVE_U_PCB_REG(v1, V1, k1)
+ SAVE_U_PCB_REG(a0, A0, k1)
+ SAVE_U_PCB_REG(a1, A1, k1)
+ SAVE_U_PCB_REG(a2, A2, k1)
+ SAVE_U_PCB_REG(a3, A3, k1)
+ SAVE_U_PCB_REG(t0, T0, k1)
+ SAVE_U_PCB_REG(t1, T1, k1)
+ SAVE_U_PCB_REG(t2, T2, k1)
+ SAVE_U_PCB_REG(t3, T3, k1)
+ SAVE_U_PCB_REG(ta0, TA0, k1)
+ SAVE_U_PCB_REG(ta1, TA1, k1)
+ SAVE_U_PCB_REG(ta2, TA2, k1)
+ SAVE_U_PCB_REG(ta3, TA3, k1)
+ SAVE_U_PCB_REG(t8, T8, k1)
+ SAVE_U_PCB_REG(t9, T9, k1)
+ SAVE_U_PCB_REG(gp, GP, k1)
+ SAVE_U_PCB_REG(sp, SP, k1)
+ SAVE_U_PCB_REG(ra, RA, k1)
+/*
+ * save remaining user state in u.u_pcb.
+ */
+ SAVE_U_PCB_REG(s0, S0, k1)
+ SAVE_U_PCB_REG(s1, S1, k1)
+ SAVE_U_PCB_REG(s2, S2, k1)
+ SAVE_U_PCB_REG(s3, S3, k1)
+ SAVE_U_PCB_REG(s4, S4, k1)
+ SAVE_U_PCB_REG(s5, S5, k1)
+ SAVE_U_PCB_REG(s6, S6, k1)
+ SAVE_U_PCB_REG(s7, S7, k1)
+ SAVE_U_PCB_REG(s8, S8, k1)
+
+ mflo v0 # get lo/hi late to avoid stall
+ mfhi v1
+ mfc0 a0, MIPS_COP_0_STATUS
+ mfc0 a1, MIPS_COP_0_CAUSE
+ MFC0 a3, MIPS_COP_0_EXC_PC
+ SAVE_U_PCB_REG(v0, MULLO, k1)
+ SAVE_U_PCB_REG(v1, MULHI, k1)
+ SAVE_U_PCB_REG(a0, SR, k1)
+ SAVE_U_PCB_REG(a1, CAUSE, k1)
+ SAVE_U_PCB_REG(a3, PC, k1) # PC in a3, note used later!
+ PTR_SUBU sp, k1, CALLFRAME_SIZ # switch to kernel SP
+ PTR_LA gp, _C_LABEL(_gp) # switch to kernel GP
+
+# Turn off fpu, disable interrupts, set kernel mode kernel mode, clear exception level.
+ and t0, a0, ~(MIPS_SR_COP_1_BIT | MIPS_SR_EXL | MIPS_SR_INT_IE | MIPS_SR_KSU_MASK)
+#ifdef CPU_CNMIPS
+ and t0, t0, ~(MIPS_SR_COP_2_BIT)
+ or t0, t0, (MIPS_SR_KX | MIPS_SR_SX | MIPS_SR_UX | MIPS_SR_PX)
+#elif defined(CPU_RMI) || defined(CPU_NLM)
+ or t0, t0, (MIPS_SR_KX | MIPS_SR_UX | MIPS_SR_COP_2_BIT)
+#endif
+ mtc0 t0, MIPS_COP_0_STATUS
+ ITLBNOPFIX
+ PTR_ADDU a0, k1, U_PCB_REGS
+/*
+ * Call the interrupt handler.
+ */
+ PTR_LA k0, _C_LABEL(cpu_intr)
+ jalr k0
+ REG_S a3, CALLFRAME_RA(sp) # for debugging
+
+/*
+ * Enable interrupts before doing ast().
+ *
+ * On SMP kernels the AST processing might trigger IPI to other processors.
+ * If that processor is also doing AST processing with interrupts disabled
+ * then we may deadlock.
+ */
+ mfc0 a0, MIPS_COP_0_STATUS
+ or a0, a0, MIPS_SR_INT_IE
+ mtc0 a0, MIPS_COP_0_STATUS
+ ITLBNOPFIX
+
+/*
+ * DO_AST enabled interrupts
+ */
+ DO_AST
+
+/*
+ * Restore user registers and return.
+ */
+ CLEAR_STATUS
+
+ GET_CPU_PCPU(k1)
+ PTR_L k1, PC_CURPCB(k1)
+
+ /*
+ * Update interrupt mask in saved status register
+ * Some of interrupts could be disabled by
+ * intr filters
+ */
+ mfc0 a0, MIPS_COP_0_STATUS
+ and a0, a0, MIPS_SR_INT_MASK
+ RESTORE_U_PCB_REG(a1, SR, k1)
+ and a1, a1, ~MIPS_SR_INT_MASK
+ or a1, a1, a0
+ SAVE_U_PCB_REG(a1, SR, k1)
+
+ RESTORE_U_PCB_REG(s0, S0, k1)
+ RESTORE_U_PCB_REG(s1, S1, k1)
+ RESTORE_U_PCB_REG(s2, S2, k1)
+ RESTORE_U_PCB_REG(s3, S3, k1)
+ RESTORE_U_PCB_REG(s4, S4, k1)
+ RESTORE_U_PCB_REG(s5, S5, k1)
+ RESTORE_U_PCB_REG(s6, S6, k1)
+ RESTORE_U_PCB_REG(s7, S7, k1)
+ RESTORE_U_PCB_REG(s8, S8, k1)
+ RESTORE_U_PCB_REG(t0, MULLO, k1)
+ RESTORE_U_PCB_REG(t1, MULHI, k1)
+ RESTORE_U_PCB_REG(t2, PC, k1)
+ mtlo t0
+ mthi t1
+ MTC0 t2, MIPS_COP_0_EXC_PC # set return address
+ RESTORE_U_PCB_REG(v0, V0, k1)
+ RESTORE_U_PCB_REG(v1, V1, k1)
+ RESTORE_U_PCB_REG(a0, A0, k1)
+ RESTORE_U_PCB_REG(a1, A1, k1)
+ RESTORE_U_PCB_REG(a2, A2, k1)
+ RESTORE_U_PCB_REG(a3, A3, k1)
+ RESTORE_U_PCB_REG(t0, T0, k1)
+ RESTORE_U_PCB_REG(t1, T1, k1)
+ RESTORE_U_PCB_REG(t2, T2, k1)
+ RESTORE_U_PCB_REG(t3, T3, k1)
+ RESTORE_U_PCB_REG(ta0, TA0, k1)
+ RESTORE_U_PCB_REG(ta1, TA1, k1)
+ RESTORE_U_PCB_REG(ta2, TA2, k1)
+ RESTORE_U_PCB_REG(ta3, TA3, k1)
+ RESTORE_U_PCB_REG(t8, T8, k1)
+ RESTORE_U_PCB_REG(t9, T9, k1)
+ RESTORE_U_PCB_REG(gp, GP, k1)
+ RESTORE_U_PCB_REG(k0, SR, k1)
+ RESTORE_U_PCB_REG(sp, SP, k1)
+ RESTORE_U_PCB_REG(ra, RA, k1)
+ .set noat
+ RESTORE_U_PCB_REG(AT, AST, k1)
+
+ mtc0 k0, MIPS_COP_0_STATUS # SR with EXL set.
+ ITLBNOPFIX
+ sync
+ eret
+ .set at
+END(MipsUserIntr)
+
+NLEAF(MipsTLBInvalidException)
+ .set push
+ .set noat
+ .set noreorder
+
+ MFC0 k0, MIPS_COP_0_BAD_VADDR
+ PTR_LI k1, VM_MAXUSER_ADDRESS
+ sltu k1, k0, k1
+ bnez k1, 1f
+ nop
+
+ /* Kernel address. */
+ lui k1, %hi(kernel_segmap) # k1=hi of segbase
+ b 2f
+ PTR_L k1, %lo(kernel_segmap)(k1) # k1=segment tab base
+
+1: /* User address. */
+ GET_CPU_PCPU(k1)
+ PTR_L k1, PC_SEGBASE(k1)
+
+2: /* Validate page directory pointer. */
+ beqz k1, 3f
+ nop
+
+ PTR_SRL k0, SEGSHIFT - PTRSHIFT # k0=seg offset (almost)
+ beq k1, zero, MipsKernGenException # ==0 -- no seg tab
+ andi k0, k0, PDEPTRMASK #06: k0=seg offset
+ PTR_ADDU k1, k0, k1 # k1=seg entry address
+ PTR_L k1, 0(k1) # k1=seg entry
+
+ /* Validate page table pointer. */
+ beqz k1, 3f
+ nop
+
+#ifdef __mips_n64
+ MFC0 k0, MIPS_COP_0_BAD_VADDR
+ PTR_SRL k0, PDRSHIFT - PTRSHIFT # k0=pde offset (almost)
+ beq k1, zero, MipsKernGenException # ==0 -- no pde tab
+ andi k0, k0, PDEPTRMASK # k0=pde offset
+ PTR_ADDU k1, k0, k1 # k1=pde entry address
+ PTR_L k1, 0(k1) # k1=pde entry
+
+ /* Validate pde table pointer. */
+ beqz k1, 3f
+ nop
+#endif
+ MFC0 k0, MIPS_COP_0_BAD_VADDR # k0=bad address (again)
+ PTR_SRL k0, PAGE_SHIFT - PTESHIFT # k0=VPN
+ andi k0, k0, PTEMASK # k0=page tab offset
+ PTR_ADDU k1, k1, k0 # k1=pte address
+ PTE_L k0, 0(k1) # k0=this PTE
+
+ /* Validate page table entry. */
+ andi k0, PTE_V
+ beqz k0, 3f
+ nop
+
+ /* Check whether this is an even or odd entry. */
+ andi k0, k1, PTESIZE
+ bnez k0, odd_page
+ nop
+
+ PTE_L k0, 0(k1)
+ PTE_L k1, PTESIZE(k1)
+ CLEAR_PTE_SWBITS(k0)
+ PTE_MTC0 k0, MIPS_COP_0_TLB_LO0
+ COP0_SYNC
+ CLEAR_PTE_SWBITS(k1)
+ PTE_MTC0 k1, MIPS_COP_0_TLB_LO1
+ COP0_SYNC
+
+ b tlb_insert_entry
+ nop
+
+odd_page:
+ PTE_L k0, -PTESIZE(k1)
+ PTE_L k1, 0(k1)
+ CLEAR_PTE_SWBITS(k0)
+ PTE_MTC0 k0, MIPS_COP_0_TLB_LO0
+ COP0_SYNC
+ CLEAR_PTE_SWBITS(k1)
+ PTE_MTC0 k1, MIPS_COP_0_TLB_LO1
+ COP0_SYNC
+
+tlb_insert_entry:
+ tlbp
+ HAZARD_DELAY
+ mfc0 k0, MIPS_COP_0_TLB_INDEX
+ bltz k0, tlb_insert_random
+ nop
+ tlbwi
+ eret
+ ssnop
+
+tlb_insert_random:
+ tlbwr
+ eret
+ ssnop
+
+3:
+ /*
+ * Branch to the comprehensive exception processing.
+ */
+ mfc0 k1, MIPS_COP_0_STATUS
+ andi k1, k1, MIPS_SR_KSU_USER
+ bnez k1, _C_LABEL(MipsUserGenException)
+ nop
+
+ /*
+ * Check for kernel stack overflow.
+ */
+ GET_CPU_PCPU(k1)
+ PTR_L k0, PC_CURTHREAD(k1)
+ PTR_L k0, TD_KSTACK(k0)
+ sltu k0, k0, sp
+ bnez k0, _C_LABEL(MipsKernGenException)
+ nop
+
+ /*
+ * Kernel stack overflow.
+ *
+ * Move to a valid stack before we call panic. We use the boot stack
+ * for this purpose.
+ */
+ GET_CPU_PCPU(k1)
+ lw k1, PC_CPUID(k1)
+ sll k1, k1, PAGE_SHIFT + 1
+
+ PTR_LA k0, _C_LABEL(pcpu_space)
+ PTR_ADDU k0, PAGE_SIZE * 2
+ PTR_ADDU k0, k0, k1
+
+ /*
+ * Stash the original value of 'sp' so we can update trapframe later.
+ * We assume that SAVE_CPU does not trash 'k1'.
+ */
+ move k1, sp
+
+ move sp, k0
+ PTR_SUBU sp, sp, KERN_EXC_FRAME_SIZE
+
+ move k0, ra
+ move ra, zero
+ REG_S ra, CALLFRAME_RA(sp) /* stop the ddb backtrace right here */
+ REG_S zero, CALLFRAME_SP(sp)
+ move ra, k0
+
+ SAVE_CPU
+
+ /*
+ * Now restore the value of 'sp' at the time of the tlb exception in
+ * the trapframe.
+ */
+ SAVE_REG(k1, SP, sp)
+
+ /*
+ * Squelch any more overflow checks by setting the stack base to 0.
+ */
+ GET_CPU_PCPU(k1)
+ PTR_L k0, PC_CURTHREAD(k1)
+ PTR_S zero, TD_KSTACK(k0)
+
+ move a1, a0
+ PANIC("kernel stack overflow - trapframe at %p")
+
+ /*
+ * This nop is necessary so that the 'ra' remains within the bounds
+ * of this handler. Otherwise the ddb backtrace code will think that
+ * the panic() was called from MipsTLBMissException.
+ */
+ nop
+
+ .set pop
+END(MipsTLBInvalidException)
+
+/*----------------------------------------------------------------------------
+ *
+ * MipsTLBMissException --
+ *
+ * Handle a TLB miss exception from kernel mode in kernel space.
+ * The BaddVAddr, Context, and EntryHi registers contain the failed
+ * virtual address.
+ *
+ * Results:
+ * None.
+ *
+ * Side effects:
+ * None.
+ *
+ *----------------------------------------------------------------------------
+ */
+NLEAF(MipsTLBMissException)
+ .set noat
+ MFC0 k0, MIPS_COP_0_BAD_VADDR # k0=bad address
+ PTR_LI k1, VM_MAX_KERNEL_ADDRESS # check fault address against
+ sltu k1, k1, k0 # upper bound of kernel_segmap
+ bnez k1, MipsKernGenException # out of bound
+ lui k1, %hi(kernel_segmap) # k1=hi of segbase
+ PTR_SRL k0, SEGSHIFT - PTRSHIFT # k0=seg offset (almost)
+ PTR_L k1, %lo(kernel_segmap)(k1) # k1=segment tab base
+ beq k1, zero, MipsKernGenException # ==0 -- no seg tab
+ andi k0, k0, PDEPTRMASK #06: k0=seg offset
+ PTR_ADDU k1, k0, k1 # k1=seg entry address
+ PTR_L k1, 0(k1) # k1=seg entry
+ MFC0 k0, MIPS_COP_0_BAD_VADDR # k0=bad address (again)
+ beq k1, zero, MipsKernGenException # ==0 -- no page table
+#ifdef __mips_n64
+ PTR_SRL k0, PDRSHIFT - PTRSHIFT # k0=VPN
+ andi k0, k0, PDEPTRMASK # k0=pde offset
+ PTR_ADDU k1, k0, k1 # k1=pde entry address
+ PTR_L k1, 0(k1) # k1=pde entry
+ MFC0 k0, MIPS_COP_0_BAD_VADDR # k0=bad address (again)
+ beq k1, zero, MipsKernGenException # ==0 -- no page table
+#endif
+ PTR_SRL k0, PAGE_SHIFT - PTESHIFT # k0=VPN
+ andi k0, k0, PTE2MASK # k0=page tab offset
+ PTR_ADDU k1, k1, k0 # k1=pte address
+ PTE_L k0, 0(k1) # k0=lo0 pte
+ PTE_L k1, PTESIZE(k1) # k1=lo1 pte
+ CLEAR_PTE_SWBITS(k0)
+ PTE_MTC0 k0, MIPS_COP_0_TLB_LO0 # lo0 is loaded
+ COP0_SYNC
+ CLEAR_PTE_SWBITS(k1)
+ PTE_MTC0 k1, MIPS_COP_0_TLB_LO1 # lo1 is loaded
+ COP0_SYNC
+ tlbwr # write to tlb
+ HAZARD_DELAY
+ eret # return from exception
+ .set at
+END(MipsTLBMissException)
+
+/*----------------------------------------------------------------------------
+ *
+ * MipsFPTrap --
+ *
+ * Handle a floating point Trap.
+ *
+ * MipsFPTrap(statusReg, causeReg, pc)
+ * unsigned statusReg;
+ * unsigned causeReg;
+ * unsigned pc;
+ *
+ * Results:
+ * None.
+ *
+ * Side effects:
+ * None.
+ *
+ *----------------------------------------------------------------------------
+ */
+NON_LEAF(MipsFPTrap, CALLFRAME_SIZ, ra)
+ PTR_SUBU sp, sp, CALLFRAME_SIZ
+ mfc0 t0, MIPS_COP_0_STATUS
+ REG_S ra, CALLFRAME_RA(sp)
+ .mask 0x80000000, (CALLFRAME_RA - CALLFRAME_SIZ)
+
+ or t1, t0, MIPS_SR_COP_1_BIT
+ mtc0 t1, MIPS_COP_0_STATUS
+ ITLBNOPFIX
+ cfc1 t1, MIPS_FPU_CSR # stall til FP done
+ cfc1 t1, MIPS_FPU_CSR # now get status
+ nop
+ sll t2, t1, (31 - 17) # unimplemented operation?
+ bgez t2, 3f # no, normal trap
+ nop
+/*
+ * We got an unimplemented operation trap so
+ * fetch the instruction, compute the next PC and emulate the instruction.
+ */
+ bgez a1, 1f # Check the branch delay bit.
+ nop
+/*
+ * The instruction is in the branch delay slot so the branch will have to
+ * be emulated to get the resulting PC.
+ */
+ PTR_S a2, CALLFRAME_SIZ + 8(sp)
+ GET_CPU_PCPU(a0)
+#mips64 unsafe?
+ PTR_L a0, PC_CURPCB(a0)
+ PTR_ADDU a0, a0, U_PCB_REGS # first arg is ptr to CPU registers
+ move a1, a2 # second arg is instruction PC
+ move a2, t1 # third arg is floating point CSR
+ PTR_LA t3, _C_LABEL(MipsEmulateBranch) # compute PC after branch
+ jalr t3 # compute PC after branch
+ move a3, zero # fourth arg is FALSE
+/*
+ * Now load the floating-point instruction in the branch delay slot
+ * to be emulated.
+ */
+ PTR_L a2, CALLFRAME_SIZ + 8(sp) # restore EXC pc
+ b 2f
+ lw a0, 4(a2) # a0 = coproc instruction
+/*
+ * This is not in the branch delay slot so calculate the resulting
+ * PC (epc + 4) into v0 and continue to MipsEmulateFP().
+ */
+1:
+ lw a0, 0(a2) # a0 = coproc instruction
+#xxx mips64 unsafe?
+ PTR_ADDU v0, a2, 4 # v0 = next pc
+2:
+ GET_CPU_PCPU(t2)
+ PTR_L t2, PC_CURPCB(t2)
+ SAVE_U_PCB_REG(v0, PC, t2) # save new pc
+/*
+ * Check to see if the instruction to be emulated is a floating-point
+ * instruction.
+ */
+ srl a3, a0, MIPS_OPCODE_SHIFT
+ beq a3, MIPS_OPCODE_C1, 4f # this should never fail
+ nop
+/*
+ * Send a floating point exception signal to the current process.
+ */
+3:
+ GET_CPU_PCPU(a0)
+ PTR_L a0, PC_CURTHREAD(a0) # get current thread
+ cfc1 a2, MIPS_FPU_CSR # code = FP execptions
+ ctc1 zero, MIPS_FPU_CSR # Clear exceptions
+ PTR_LA t3, _C_LABEL(trapsignal)
+ jalr t3
+ li a1, SIGFPE
+ b FPReturn
+ nop
+
+/*
+ * Finally, we can call MipsEmulateFP() where a0 is the instruction to emulate.
+ */
+4:
+ PTR_LA t3, _C_LABEL(MipsEmulateFP)
+ jalr t3
+ nop
+
+/*
+ * Turn off the floating point coprocessor and return.
+ */
+FPReturn:
+ mfc0 t0, MIPS_COP_0_STATUS
+ PTR_L ra, CALLFRAME_RA(sp)
+ and t0, t0, ~MIPS_SR_COP_1_BIT
+ mtc0 t0, MIPS_COP_0_STATUS
+ ITLBNOPFIX
+ j ra
+ PTR_ADDU sp, sp, CALLFRAME_SIZ
+END(MipsFPTrap)
+
+/*
+ * Interrupt counters for vmstat.
+ */
+ .data
+ .globl intrcnt
+ .globl sintrcnt
+ .globl intrnames
+ .globl sintrnames
+intrnames:
+ .space INTRCNT_COUNT * (MAXCOMLEN + 1) * 2
+sintrnames:
+#ifdef __mips_n64
+ .quad INTRCNT_COUNT * (MAXCOMLEN + 1) * 2
+#else
+ .int INTRCNT_COUNT * (MAXCOMLEN + 1) * 2
+#endif
+
+ .align (_MIPS_SZLONG / 8)
+intrcnt:
+ .space INTRCNT_COUNT * (_MIPS_SZLONG / 8) * 2
+sintrcnt:
+#ifdef __mips_n64
+ .quad INTRCNT_COUNT * (_MIPS_SZLONG / 8) * 2
+#else
+ .int INTRCNT_COUNT * (_MIPS_SZLONG / 8) * 2
+#endif
+
+
+/*
+ * Vector to real handler in KSEG1.
+ */
+ .text
+VECTOR(MipsCache, unknown)
+ PTR_LA k0, _C_LABEL(MipsCacheException)
+ li k1, MIPS_KSEG0_PHYS_MASK
+ and k0, k1
+ PTR_LI k1, MIPS_KSEG1_START
+ or k0, k1
+ j k0
+ nop
+VECTOR_END(MipsCache)
+
+ .set at
+
+
+/*
+ * Panic on cache errors. A lot more could be done to recover
+ * from some types of errors but it is tricky.
+ */
+NESTED_NOPROFILE(MipsCacheException, KERN_EXC_FRAME_SIZE, ra)
+ .set noat
+ .mask 0x80000000, -4
+ PTR_LA k0, _C_LABEL(panic) # return to panic
+ PTR_LA a0, 9f # panicstr
+ MFC0 a1, MIPS_COP_0_ERROR_PC
+ mfc0 a2, MIPS_COP_0_CACHE_ERR # 3rd arg cache error
+
+ MTC0 k0, MIPS_COP_0_ERROR_PC # set return address
+
+ mfc0 k0, MIPS_COP_0_STATUS # restore status
+ li k1, MIPS_SR_DIAG_PE # ignore further errors
+ or k0, k1
+ mtc0 k0, MIPS_COP_0_STATUS # restore status
+ COP0_SYNC
+
+ eret
+
+ MSG("cache error @ EPC 0x%x CachErr 0x%x");
+ .set at
+END(MipsCacheException)
Property changes on: trunk/sys/mips/mips/exception.S
___________________________________________________________________
Added: svn:eol-style
## -0,0 +1 ##
+native
\ No newline at end of property
Added: svn:keywords
## -0,0 +1 ##
+MidnightBSD=%H
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+text/plain
\ No newline at end of property
Added: trunk/sys/mips/mips/fp.S
===================================================================
--- trunk/sys/mips/mips/fp.S (rev 0)
+++ trunk/sys/mips/mips/fp.S 2018-05-26 21:55:02 UTC (rev 9987)
@@ -0,0 +1,3609 @@
+/* $MidnightBSD$ */
+/* $OpenBSD: fp.S,v 1.2 1998/03/16 09:03:31 pefo Exp $ */
+/*-
+ * Copyright (c) 1992, 1993
+ * The Regents of the University of California. All rights reserved.
+ *
+ * This code is derived from software contributed to Berkeley by
+ * Ralph Campbell.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * 4. Neither the name of the University nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ * from: @(#)fp.s 8.1 (Berkeley) 6/10/93
+ * JNPR: fp.S,v 1.1 2006/08/07 05:38:57 katta
+ * $FreeBSD: stable/10/sys/mips/mips/fp.S 210038 2010-07-14 00:41:22Z imp $
+ */
+
+/*
+ * Standard header stuff.
+ */
+
+#include <machine/asm.h>
+#include <machine/regnum.h>
+#include <machine/cpuregs.h>
+
+#include "assym.s"
+
+#define SEXP_INF 0xff
+#define DEXP_INF 0x7ff
+#define SEXP_BIAS 127
+#define DEXP_BIAS 1023
+#define SEXP_MIN -126
+#define DEXP_MIN -1022
+#define SEXP_MAX 127
+#define DEXP_MAX 1023
+#define WEXP_MAX 30 /* maximum unbiased exponent for int */
+#define WEXP_MIN -1 /* minimum unbiased exponent for int */
+#define SFRAC_BITS 23
+#define DFRAC_BITS 52
+#define SIMPL_ONE 0x00800000
+#define DIMPL_ONE 0x00100000
+#define SLEAD_ZEROS 31 - 23
+#define DLEAD_ZEROS 31 - 20
+#define STICKYBIT 1
+#define GUARDBIT 0x80000000
+#define SSIGNAL_NAN 0x00400000
+#define DSIGNAL_NAN 0x00080000
+#define SQUIET_NAN 0x003fffff
+#define DQUIET_NAN0 0x0007ffff
+#define DQUIET_NAN1 0xffffffff
+#define INT_MIN 0x80000000
+#define INT_MAX 0x7fffffff
+
+#define COND_UNORDERED 0x1
+#define COND_EQUAL 0x2
+#define COND_LESS 0x4
+#define COND_SIGNAL 0x8
+
+/*----------------------------------------------------------------------------
+ *
+ * MipsEmulateFP --
+ *
+ * Emulate unimplemented floating point operations.
+ * This routine should only be called by MipsFPInterrupt().
+ *
+ * MipsEmulateFP(instr)
+ * unsigned instr;
+ *
+ * Results:
+ * None.
+ *
+ * Side effects:
+ * Floating point registers are modified according to instruction.
+ *
+ *----------------------------------------------------------------------------
+ */
+NON_LEAF(MipsEmulateFP, CALLFRAME_SIZ, ra)
+ subu sp, sp, CALLFRAME_SIZ
+ sw ra, CALLFRAME_RA(sp)
+/*
+ * Decode the FMT field (bits 24-21) and FUNCTION field (bits 5-0).
+ */
+ srl v0, a0, 21 - 2 # get FMT field
+ and v0, v0, 0xF << 2 # mask FMT field
+ and v1, a0, 0x3F # mask FUNC field
+ sll v1, v1, 5 # align for table lookup
+ bgt v0, 4 << 2, ill # illegal format
+
+ or v1, v1, v0
+ cfc1 a1, MIPS_FPU_CSR # get exception register
+ lw a3, func_fmt_tbl(v1) # switch on FUNC & FMT
+ and a1, a1, ~MIPS_FPU_EXCEPTION_UNIMPL # clear exception
+ ctc1 a1, MIPS_FPU_CSR
+ j a3
+
+ .rdata
+func_fmt_tbl:
+ .word add_s # 0
+ .word add_d # 0
+ .word ill # 0
+ .word ill # 0
+ .word ill # 0
+ .word ill # 0
+ .word ill # 0
+ .word ill # 0
+ .word sub_s # 1
+ .word sub_d # 1
+ .word ill # 1
+ .word ill # 1
+ .word ill # 1
+ .word ill # 1
+ .word ill # 1
+ .word ill # 1
+ .word mul_s # 2
+ .word mul_d # 2
+ .word ill # 2
+ .word ill # 2
+ .word ill # 2
+ .word ill # 2
+ .word ill # 2
+ .word ill # 2
+ .word div_s # 3
+ .word div_d # 3
+ .word ill # 3
+ .word ill # 3
+ .word ill # 3
+ .word ill # 3
+ .word ill # 3
+ .word ill # 3
+ .word ill # 4
+ .word ill # 4
+ .word ill # 4
+ .word ill # 4
+ .word ill # 4
+ .word ill # 4
+ .word ill # 4
+ .word ill # 4
+ .word abs_s # 5
+ .word abs_d # 5
+ .word ill # 5
+ .word ill # 5
+ .word ill # 5
+ .word ill # 5
+ .word ill # 5
+ .word ill # 5
+ .word mov_s # 6
+ .word mov_d # 6
+ .word ill # 6
+ .word ill # 6
+ .word ill # 6
+ .word ill # 6
+ .word ill # 6
+ .word ill # 6
+ .word neg_s # 7
+ .word neg_d # 7
+ .word ill # 7
+ .word ill # 7
+ .word ill # 7
+ .word ill # 7
+ .word ill # 7
+ .word ill # 7
+ .word ill # 8
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+ .word cmp_d # 48
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+ .word cmp_d # 49
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+ .word cmp_s # 50
+ .word cmp_d # 50
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+ .word ill # 50
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+ .word ill # 50
+ .word ill # 50
+ .word ill # 50
+ .word cmp_s # 51
+ .word cmp_d # 51
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+ .word cmp_d # 52
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+ .word cmp_d # 53
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+ .word cmp_d # 57
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+ .word cmp_d # 58
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+ .word cmp_s # 59
+ .word cmp_d # 59
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+ .word cmp_d # 60
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+ .word ill # 60
+ .word ill # 60
+ .word ill # 60
+ .word ill # 60
+ .word cmp_s # 61
+ .word cmp_d # 61
+ .word ill # 61
+ .word ill # 61
+ .word ill # 61
+ .word ill # 61
+ .word ill # 61
+ .word ill # 61
+ .word cmp_s # 62
+ .word cmp_d # 62
+ .word ill # 62
+ .word ill # 62
+ .word ill # 62
+ .word ill # 62
+ .word ill # 62
+ .word ill # 62
+ .word cmp_s # 63
+ .word cmp_d # 63
+ .word ill # 63
+ .word ill # 63
+ .word ill # 63
+ .word ill # 63
+ .word ill # 63
+ .word ill # 63
+ .text
+
+/*
+ * Single precision subtract.
+ */
+sub_s:
+ jal get_ft_fs_s
+ xor ta0, ta0, 1 # negate FT sign bit
+ b add_sub_s
+/*
+ * Single precision add.
+ */
+add_s:
+ jal get_ft_fs_s
+add_sub_s:
+ bne t1, SEXP_INF, 1f # is FS an infinity?
+ bne ta1, SEXP_INF, result_fs_s # if FT is not inf, result=FS
+ bne t2, zero, result_fs_s # if FS is NAN, result is FS
+ bne ta2, zero, result_ft_s # if FT is NAN, result is FT
+ bne t0, ta0, invalid_s # both infinities same sign?
+ b result_fs_s # result is in FS
+1:
+ beq ta1, SEXP_INF, result_ft_s # if FT is inf, result=FT
+ bne t1, zero, 4f # is FS a denormalized num?
+ beq t2, zero, 3f # is FS zero?
+ bne ta1, zero, 2f # is FT a denormalized num?
+ beq ta2, zero, result_fs_s # FT is zero, result=FS
+ jal renorm_fs_s
+ jal renorm_ft_s
+ b 5f
+2:
+ jal renorm_fs_s
+ subu ta1, ta1, SEXP_BIAS # unbias FT exponent
+ or ta2, ta2, SIMPL_ONE # set implied one bit
+ b 5f
+3:
+ bne ta1, zero, result_ft_s # if FT != 0, result=FT
+ bne ta2, zero, result_ft_s
+ and v0, a1, MIPS_FPU_ROUNDING_BITS # get rounding mode
+ bne v0, MIPS_FPU_ROUND_RM, 1f # round to -infinity?
+ or t0, t0, ta0 # compute result sign
+ b result_fs_s
+1:
+ and t0, t0, ta0 # compute result sign
+ b result_fs_s
+4:
+ bne ta1, zero, 2f # is FT a denormalized num?
+ beq ta2, zero, result_fs_s # FT is zero, result=FS
+ subu t1, t1, SEXP_BIAS # unbias FS exponent
+ or t2, t2, SIMPL_ONE # set implied one bit
+ jal renorm_ft_s
+ b 5f
+2:
+ subu t1, t1, SEXP_BIAS # unbias FS exponent
+ or t2, t2, SIMPL_ONE # set implied one bit
+ subu ta1, ta1, SEXP_BIAS # unbias FT exponent
+ or ta2, ta2, SIMPL_ONE # set implied one bit
+/*
+ * Perform the addition.
+ */
+5:
+ move t8, zero # no shifted bits (sticky reg)
+ beq t1, ta1, 4f # no shift needed
+ subu v0, t1, ta1 # v0 = difference of exponents
+ move v1, v0 # v1 = abs(difference)
+ bge v0, zero, 1f
+ negu v1
+1:
+ ble v1, SFRAC_BITS+2, 2f # is difference too great?
+ li t8, STICKYBIT # set the sticky bit
+ bge v0, zero, 1f # check which exp is larger
+ move t1, ta1 # result exp is FTs
+ move t2, zero # FSs fraction shifted is zero
+ b 4f
+1:
+ move ta2, zero # FTs fraction shifted is zero
+ b 4f
+2:
+ li t9, 32 # compute 32 - abs(exp diff)
+ subu t9, t9, v1
+ bgt v0, zero, 3f # if FS > FT, shift FTs frac
+ move t1, ta1 # FT > FS, result exp is FTs
+ sll t8, t2, t9 # save bits shifted out
+ srl t2, t2, v1 # shift FSs fraction
+ b 4f
+3:
+ sll t8, ta2, t9 # save bits shifted out
+ srl ta2, ta2, v1 # shift FTs fraction
+4:
+ bne t0, ta0, 1f # if signs differ, subtract
+ addu t2, t2, ta2 # add fractions
+ b norm_s
+1:
+ blt t2, ta2, 3f # subtract larger from smaller
+ bne t2, ta2, 2f # if same, result=0
+ move t1, zero # result=0
+ move t2, zero
+ and v0, a1, MIPS_FPU_ROUNDING_BITS # get rounding mode
+ bne v0, MIPS_FPU_ROUND_RM, 1f # round to -infinity?
+ or t0, t0, ta0 # compute result sign
+ b result_fs_s
+1:
+ and t0, t0, ta0 # compute result sign
+ b result_fs_s
+2:
+ sltu t9, zero, t8 # compute t2:zero - ta2:t8
+ subu t8, zero, t8
+ subu t2, t2, ta2 # subtract fractions
+ subu t2, t2, t9 # subtract barrow
+ b norm_s
+3:
+ move t0, ta0 # sign of result = FTs
+ sltu t9, zero, t8 # compute ta2:zero - t2:t8
+ subu t8, zero, t8
+ subu t2, ta2, t2 # subtract fractions
+ subu t2, t2, t9 # subtract barrow
+ b norm_s
+
+/*
+ * Double precision subtract.
+ */
+sub_d:
+ jal get_ft_fs_d
+ xor ta0, ta0, 1 # negate sign bit
+ b add_sub_d
+/*
+ * Double precision add.
+ */
+add_d:
+ jal get_ft_fs_d
+add_sub_d:
+ bne t1, DEXP_INF, 1f # is FS an infinity?
+ bne ta1, DEXP_INF, result_fs_d # if FT is not inf, result=FS
+ bne t2, zero, result_fs_d # if FS is NAN, result is FS
+ bne t3, zero, result_fs_d
+ bne ta2, zero, result_ft_d # if FT is NAN, result is FT
+ bne ta3, zero, result_ft_d
+ bne t0, ta0, invalid_d # both infinities same sign?
+ b result_fs_d # result is in FS
+1:
+ beq ta1, DEXP_INF, result_ft_d # if FT is inf, result=FT
+ bne t1, zero, 4f # is FS a denormalized num?
+ bne t2, zero, 1f # is FS zero?
+ beq t3, zero, 3f
+1:
+ bne ta1, zero, 2f # is FT a denormalized num?
+ bne ta2, zero, 1f
+ beq ta3, zero, result_fs_d # FT is zero, result=FS
+1:
+ jal renorm_fs_d
+ jal renorm_ft_d
+ b 5f
+2:
+ jal renorm_fs_d
+ subu ta1, ta1, DEXP_BIAS # unbias FT exponent
+ or ta2, ta2, DIMPL_ONE # set implied one bit
+ b 5f
+3:
+ bne ta1, zero, result_ft_d # if FT != 0, result=FT
+ bne ta2, zero, result_ft_d
+ bne ta3, zero, result_ft_d
+ and v0, a1, MIPS_FPU_ROUNDING_BITS # get rounding mode
+ bne v0, MIPS_FPU_ROUND_RM, 1f # round to -infinity?
+ or t0, t0, ta0 # compute result sign
+ b result_fs_d
+1:
+ and t0, t0, ta0 # compute result sign
+ b result_fs_d
+4:
+ bne ta1, zero, 2f # is FT a denormalized num?
+ bne ta2, zero, 1f
+ beq ta3, zero, result_fs_d # FT is zero, result=FS
+1:
+ subu t1, t1, DEXP_BIAS # unbias FS exponent
+ or t2, t2, DIMPL_ONE # set implied one bit
+ jal renorm_ft_d
+ b 5f
+2:
+ subu t1, t1, DEXP_BIAS # unbias FS exponent
+ or t2, t2, DIMPL_ONE # set implied one bit
+ subu ta1, ta1, DEXP_BIAS # unbias FT exponent
+ or ta2, ta2, DIMPL_ONE # set implied one bit
+/*
+ * Perform the addition.
+ */
+5:
+ move t8, zero # no shifted bits (sticky reg)
+ beq t1, ta1, 4f # no shift needed
+ subu v0, t1, ta1 # v0 = difference of exponents
+ move v1, v0 # v1 = abs(difference)
+ bge v0, zero, 1f
+ negu v1
+1:
+ ble v1, DFRAC_BITS+2, 2f # is difference too great?
+ li t8, STICKYBIT # set the sticky bit
+ bge v0, zero, 1f # check which exp is larger
+ move t1, ta1 # result exp is FTs
+ move t2, zero # FSs fraction shifted is zero
+ move t3, zero
+ b 4f
+1:
+ move ta2, zero # FTs fraction shifted is zero
+ move ta3, zero
+ b 4f
+2:
+ li t9, 32
+ bge v0, zero, 3f # if FS > FT, shift FTs frac
+ move t1, ta1 # FT > FS, result exp is FTs
+ blt v1, t9, 1f # shift right by < 32?
+ subu v1, v1, t9
+ subu t9, t9, v1
+ sll t8, t2, t9 # save bits shifted out
+ sltu t9, zero, t3 # dont lose any one bits
+ or t8, t8, t9 # save sticky bit
+ srl t3, t2, v1 # shift FSs fraction
+ move t2, zero
+ b 4f
+1:
+ subu t9, t9, v1
+ sll t8, t3, t9 # save bits shifted out
+ srl t3, t3, v1 # shift FSs fraction
+ sll t9, t2, t9 # save bits shifted out of t2
+ or t3, t3, t9 # and put into t3
+ srl t2, t2, v1
+ b 4f
+3:
+ blt v1, t9, 1f # shift right by < 32?
+ subu v1, v1, t9
+ subu t9, t9, v1
+ sll t8, ta2, t9 # save bits shifted out
+ srl ta3, ta2, v1 # shift FTs fraction
+ move ta2, zero
+ b 4f
+1:
+ subu t9, t9, v1
+ sll t8, ta3, t9 # save bits shifted out
+ srl ta3, ta3, v1 # shift FTs fraction
+ sll t9, ta2, t9 # save bits shifted out of t2
+ or ta3, ta3, t9 # and put into t3
+ srl ta2, ta2, v1
+4:
+ bne t0, ta0, 1f # if signs differ, subtract
+ addu t3, t3, ta3 # add fractions
+ sltu t9, t3, ta3 # compute carry
+ addu t2, t2, ta2 # add fractions
+ addu t2, t2, t9 # add carry
+ b norm_d
+1:
+ blt t2, ta2, 3f # subtract larger from smaller
+ bne t2, ta2, 2f
+ bltu t3, ta3, 3f
+ bne t3, ta3, 2f # if same, result=0
+ move t1, zero # result=0
+ move t2, zero
+ move t3, zero
+ and v0, a1, MIPS_FPU_ROUNDING_BITS # get rounding mode
+ bne v0, MIPS_FPU_ROUND_RM, 1f # round to -infinity?
+ or t0, t0, ta0 # compute result sign
+ b result_fs_d
+1:
+ and t0, t0, ta0 # compute result sign
+ b result_fs_d
+2:
+ beq t8, zero, 1f # compute t2:t3:zero - ta2:ta3:t8
+ subu t8, zero, t8
+ sltu v0, t3, 1 # compute barrow out
+ subu t3, t3, 1 # subtract barrow
+ subu t2, t2, v0
+1:
+ sltu v0, t3, ta3
+ subu t3, t3, ta3 # subtract fractions
+ subu t2, t2, ta2 # subtract fractions
+ subu t2, t2, v0 # subtract barrow
+ b norm_d
+3:
+ move t0, ta0 # sign of result = FTs
+ beq t8, zero, 1f # compute ta2:ta3:zero - t2:t3:t8
+ subu t8, zero, t8
+ sltu v0, ta3, 1 # compute barrow out
+ subu ta3, ta3, 1 # subtract barrow
+ subu ta2, ta2, v0
+1:
+ sltu v0, ta3, t3
+ subu t3, ta3, t3 # subtract fractions
+ subu t2, ta2, t2 # subtract fractions
+ subu t2, t2, v0 # subtract barrow
+ b norm_d
+
+/*
+ * Single precision multiply.
+ */
+mul_s:
+ jal get_ft_fs_s
+ xor t0, t0, ta0 # compute sign of result
+ move ta0, t0
+ bne t1, SEXP_INF, 2f # is FS an infinity?
+ bne t2, zero, result_fs_s # if FS is a NAN, result=FS
+ bne ta1, SEXP_INF, 1f # FS is inf, is FT an infinity?
+ bne ta2, zero, result_ft_s # if FT is a NAN, result=FT
+ b result_fs_s # result is infinity
+1:
+ bne ta1, zero, result_fs_s # inf * zero? if no, result=FS
+ bne ta2, zero, result_fs_s
+ b invalid_s # infinity * zero is invalid
+2:
+ bne ta1, SEXP_INF, 1f # FS != inf, is FT an infinity?
+ bne t1, zero, result_ft_s # zero * inf? if no, result=FT
+ bne t2, zero, result_ft_s
+ bne ta2, zero, result_ft_s # if FT is a NAN, result=FT
+ b invalid_s # zero * infinity is invalid
+1:
+ bne t1, zero, 1f # is FS zero?
+ beq t2, zero, result_fs_s # result is zero
+ jal renorm_fs_s
+ b 2f
+1:
+ subu t1, t1, SEXP_BIAS # unbias FS exponent
+ or t2, t2, SIMPL_ONE # set implied one bit
+2:
+ bne ta1, zero, 1f # is FT zero?
+ beq ta2, zero, result_ft_s # result is zero
+ jal renorm_ft_s
+ b 2f
+1:
+ subu ta1, ta1, SEXP_BIAS # unbias FT exponent
+ or ta2, ta2, SIMPL_ONE # set implied one bit
+2:
+ addu t1, t1, ta1 # compute result exponent
+ addu t1, t1, 9 # account for binary point
+ multu t2, ta2 # multiply fractions
+ mflo t8
+ mfhi t2
+ b norm_s
+
+/*
+ * Double precision multiply.
+ */
+mul_d:
+ jal get_ft_fs_d
+ xor t0, t0, ta0 # compute sign of result
+ move ta0, t0
+ bne t1, DEXP_INF, 2f # is FS an infinity?
+ bne t2, zero, result_fs_d # if FS is a NAN, result=FS
+ bne t3, zero, result_fs_d
+ bne ta1, DEXP_INF, 1f # FS is inf, is FT an infinity?
+ bne ta2, zero, result_ft_d # if FT is a NAN, result=FT
+ bne ta3, zero, result_ft_d
+ b result_fs_d # result is infinity
+1:
+ bne ta1, zero, result_fs_d # inf * zero? if no, result=FS
+ bne ta2, zero, result_fs_d
+ bne ta3, zero, result_fs_d
+ b invalid_d # infinity * zero is invalid
+2:
+ bne ta1, DEXP_INF, 1f # FS != inf, is FT an infinity?
+ bne t1, zero, result_ft_d # zero * inf? if no, result=FT
+ bne t2, zero, result_ft_d # if FS is a NAN, result=FS
+ bne t3, zero, result_ft_d
+ bne ta2, zero, result_ft_d # if FT is a NAN, result=FT
+ bne ta3, zero, result_ft_d
+ b invalid_d # zero * infinity is invalid
+1:
+ bne t1, zero, 2f # is FS zero?
+ bne t2, zero, 1f
+ beq t3, zero, result_fs_d # result is zero
+1:
+ jal renorm_fs_d
+ b 3f
+2:
+ subu t1, t1, DEXP_BIAS # unbias FS exponent
+ or t2, t2, DIMPL_ONE # set implied one bit
+3:
+ bne ta1, zero, 2f # is FT zero?
+ bne ta2, zero, 1f
+ beq ta3, zero, result_ft_d # result is zero
+1:
+ jal renorm_ft_d
+ b 3f
+2:
+ subu ta1, ta1, DEXP_BIAS # unbias FT exponent
+ or ta2, ta2, DIMPL_ONE # set implied one bit
+3:
+ addu t1, t1, ta1 # compute result exponent
+ addu t1, t1, 12 # ???
+ multu t3, ta3 # multiply fractions (low * low)
+ move ta0, t2 # free up t2,t3 for result
+ move ta1, t3
+ mflo a3 # save low order bits
+ mfhi t8
+ not v0, t8
+ multu ta0, ta3 # multiply FS(high) * FT(low)
+ mflo v1
+ mfhi t3 # init low result
+ sltu v0, v0, v1 # compute carry
+ addu t8, v1
+ multu ta1, ta2 # multiply FS(low) * FT(high)
+ addu t3, t3, v0 # add carry
+ not v0, t8
+ mflo v1
+ mfhi t2
+ sltu v0, v0, v1
+ addu t8, v1
+ multu ta0, ta2 # multiply FS(high) * FT(high)
+ addu t3, v0
+ not v1, t3
+ sltu v1, v1, t2
+ addu t3, t2
+ not v0, t3
+ mfhi t2
+ addu t2, v1
+ mflo v1
+ sltu v0, v0, v1
+ addu t2, v0
+ addu t3, v1
+ sltu a3, zero, a3 # reduce t8,a3 to just t8
+ or t8, a3
+ b norm_d
+
+/*
+ * Single precision divide.
+ */
+div_s:
+ jal get_ft_fs_s
+ xor t0, t0, ta0 # compute sign of result
+ move ta0, t0
+ bne t1, SEXP_INF, 1f # is FS an infinity?
+ bne t2, zero, result_fs_s # if FS is NAN, result is FS
+ bne ta1, SEXP_INF, result_fs_s # is FT an infinity?
+ bne ta2, zero, result_ft_s # if FT is NAN, result is FT
+ b invalid_s # infinity/infinity is invalid
+1:
+ bne ta1, SEXP_INF, 1f # is FT an infinity?
+ bne ta2, zero, result_ft_s # if FT is NAN, result is FT
+ move t1, zero # x / infinity is zero
+ move t2, zero
+ b result_fs_s
+1:
+ bne t1, zero, 2f # is FS zero?
+ bne t2, zero, 1f
+ bne ta1, zero, result_fs_s # FS=zero, is FT zero?
+ beq ta2, zero, invalid_s # 0 / 0
+ b result_fs_s # result = zero
+1:
+ jal renorm_fs_s
+ b 3f
+2:
+ subu t1, t1, SEXP_BIAS # unbias FS exponent
+ or t2, t2, SIMPL_ONE # set implied one bit
+3:
+ bne ta1, zero, 2f # is FT zero?
+ bne ta2, zero, 1f
+ or a1, a1, MIPS_FPU_EXCEPTION_DIV0 | MIPS_FPU_STICKY_DIV0
+ and v0, a1, MIPS_FPU_ENABLE_DIV0 # trap enabled?
+ bne v0, zero, fpe_trap
+ ctc1 a1, MIPS_FPU_CSR # save exceptions
+ li t1, SEXP_INF # result is infinity
+ move t2, zero
+ b result_fs_s
+1:
+ jal renorm_ft_s
+ b 3f
+2:
+ subu ta1, ta1, SEXP_BIAS # unbias FT exponent
+ or ta2, ta2, SIMPL_ONE # set implied one bit
+3:
+ subu t1, t1, ta1 # compute exponent
+ subu t1, t1, 3 # compensate for result position
+ li v0, SFRAC_BITS+3 # number of bits to divide
+ move t8, t2 # init dividend
+ move t2, zero # init result
+1:
+ bltu t8, ta2, 3f # is dividend >= divisor?
+2:
+ subu t8, t8, ta2 # subtract divisor from dividend
+ or t2, t2, 1 # remember that we did
+ bne t8, zero, 3f # if not done, continue
+ sll t2, t2, v0 # shift result to final position
+ b norm_s
+3:
+ sll t8, t8, 1 # shift dividend
+ sll t2, t2, 1 # shift result
+ subu v0, v0, 1 # are we done?
+ bne v0, zero, 1b # no, continue
+ b norm_s
+
+/*
+ * Double precision divide.
+ */
+div_d:
+ jal get_ft_fs_d
+ xor t0, t0, ta0 # compute sign of result
+ move ta0, t0
+ bne t1, DEXP_INF, 1f # is FS an infinity?
+ bne t2, zero, result_fs_d # if FS is NAN, result is FS
+ bne t3, zero, result_fs_d
+ bne ta1, DEXP_INF, result_fs_d # is FT an infinity?
+ bne ta2, zero, result_ft_d # if FT is NAN, result is FT
+ bne ta3, zero, result_ft_d
+ b invalid_d # infinity/infinity is invalid
+1:
+ bne ta1, DEXP_INF, 1f # is FT an infinity?
+ bne ta2, zero, result_ft_d # if FT is NAN, result is FT
+ bne ta3, zero, result_ft_d
+ move t1, zero # x / infinity is zero
+ move t2, zero
+ move t3, zero
+ b result_fs_d
+1:
+ bne t1, zero, 2f # is FS zero?
+ bne t2, zero, 1f
+ bne t3, zero, 1f
+ bne ta1, zero, result_fs_d # FS=zero, is FT zero?
+ bne ta2, zero, result_fs_d
+ beq ta3, zero, invalid_d # 0 / 0
+ b result_fs_d # result = zero
+1:
+ jal renorm_fs_d
+ b 3f
+2:
+ subu t1, t1, DEXP_BIAS # unbias FS exponent
+ or t2, t2, DIMPL_ONE # set implied one bit
+3:
+ bne ta1, zero, 2f # is FT zero?
+ bne ta2, zero, 1f
+ bne ta3, zero, 1f
+ or a1, a1, MIPS_FPU_EXCEPTION_DIV0 | MIPS_FPU_STICKY_DIV0
+ and v0, a1, MIPS_FPU_ENABLE_DIV0 # trap enabled?
+ bne v0, zero, fpe_trap
+ ctc1 a1, MIPS_FPU_CSR # Save exceptions
+ li t1, DEXP_INF # result is infinity
+ move t2, zero
+ move t3, zero
+ b result_fs_d
+1:
+ jal renorm_ft_d
+ b 3f
+2:
+ subu ta1, ta1, DEXP_BIAS # unbias FT exponent
+ or ta2, ta2, DIMPL_ONE # set implied one bit
+3:
+ subu t1, t1, ta1 # compute exponent
+ subu t1, t1, 3 # compensate for result position
+ li v0, DFRAC_BITS+3 # number of bits to divide
+ move t8, t2 # init dividend
+ move t9, t3
+ move t2, zero # init result
+ move t3, zero
+1:
+ bltu t8, ta2, 3f # is dividend >= divisor?
+ bne t8, ta2, 2f
+ bltu t9, ta3, 3f
+2:
+ sltu v1, t9, ta3 # subtract divisor from dividend
+ subu t9, t9, ta3
+ subu t8, t8, ta2
+ subu t8, t8, v1
+ or t3, t3, 1 # remember that we did
+ bne t8, zero, 3f # if not done, continue
+ bne t9, zero, 3f
+ li v1, 32 # shift result to final position
+ blt v0, v1, 2f # shift < 32 bits?
+ subu v0, v0, v1 # shift by > 32 bits
+ sll t2, t3, v0 # shift upper part
+ move t3, zero
+ b norm_d
+2:
+ subu v1, v1, v0 # shift by < 32 bits
+ sll t2, t2, v0 # shift upper part
+ srl t9, t3, v1 # save bits shifted out
+ or t2, t2, t9 # and put into upper part
+ sll t3, t3, v0
+ b norm_d
+3:
+ sll t8, t8, 1 # shift dividend
+ srl v1, t9, 31 # save bit shifted out
+ or t8, t8, v1 # and put into upper part
+ sll t9, t9, 1
+ sll t2, t2, 1 # shift result
+ srl v1, t3, 31 # save bit shifted out
+ or t2, t2, v1 # and put into upper part
+ sll t3, t3, 1
+ subu v0, v0, 1 # are we done?
+ bne v0, zero, 1b # no, continue
+ sltu v0, zero, t9 # be sure to save any one bits
+ or t8, t8, v0 # from the lower remainder
+ b norm_d
+
+/*
+ * Single precision absolute value.
+ */
+abs_s:
+ jal get_fs_s
+ move t0, zero # set sign positive
+ b result_fs_s
+
+/*
+ * Double precision absolute value.
+ */
+abs_d:
+ jal get_fs_d
+ move t0, zero # set sign positive
+ b result_fs_d
+
+/*
+ * Single precision move.
+ */
+mov_s:
+ jal get_fs_s
+ b result_fs_s
+
+/*
+ * Double precision move.
+ */
+mov_d:
+ jal get_fs_d
+ b result_fs_d
+
+/*
+ * Single precision negate.
+ */
+neg_s:
+ jal get_fs_s
+ xor t0, t0, 1 # reverse sign
+ b result_fs_s
+
+/*
+ * Double precision negate.
+ */
+neg_d:
+ jal get_fs_d
+ xor t0, t0, 1 # reverse sign
+ b result_fs_d
+
+/*
+ * Convert double to single.
+ */
+cvt_s_d:
+ jal get_fs_d
+ bne t1, DEXP_INF, 1f # is FS an infinity?
+ li t1, SEXP_INF # convert to single
+ sll t2, t2, 3 # convert D fraction to S
+ srl t8, t3, 32 - 3
+ or t2, t2, t8
+ b result_fs_s
+1:
+ bne t1, zero, 2f # is FS zero?
+ bne t2, zero, 1f
+ beq t3, zero, result_fs_s # result=0
+1:
+ jal renorm_fs_d
+ subu t1, t1, 3 # correct exp for shift below
+ b 3f
+2:
+ subu t1, t1, DEXP_BIAS # unbias exponent
+ or t2, t2, DIMPL_ONE # add implied one bit
+3:
+ sll t2, t2, 3 # convert D fraction to S
+ srl t8, t3, 32 - 3
+ or t2, t2, t8
+ sll t8, t3, 3
+ b norm_noshift_s
+
+/*
+ * Convert integer to single.
+ */
+cvt_s_w:
+ jal get_fs_int
+ bne t2, zero, 1f # check for zero
+ move t1, zero
+ b result_fs_s
+/*
+ * Find out how many leading zero bits are in t2 and put in t9.
+ */
+1:
+ move v0, t2
+ move t9, zero
+ srl v1, v0, 16
+ bne v1, zero, 1f
+ addu t9, 16
+ sll v0, 16
+1:
+ srl v1, v0, 24
+ bne v1, zero, 1f
+ addu t9, 8
+ sll v0, 8
+1:
+ srl v1, v0, 28
+ bne v1, zero, 1f
+ addu t9, 4
+ sll v0, 4
+1:
+ srl v1, v0, 30
+ bne v1, zero, 1f
+ addu t9, 2
+ sll v0, 2
+1:
+ srl v1, v0, 31
+ bne v1, zero, 1f
+ addu t9, 1
+/*
+ * Now shift t2 the correct number of bits.
+ */
+1:
+ subu t9, t9, SLEAD_ZEROS # dont count leading zeros
+ li t1, 23 # init exponent
+ subu t1, t1, t9 # compute exponent
+ beq t9, zero, 1f
+ li v0, 32
+ blt t9, zero, 2f # if shift < 0, shift right
+ subu v0, v0, t9
+ sll t2, t2, t9 # shift left
+1:
+ add t1, t1, SEXP_BIAS # bias exponent
+ and t2, t2, ~SIMPL_ONE # clear implied one bit
+ b result_fs_s
+2:
+ negu t9 # shift right by t9
+ subu v0, v0, t9
+ sll t8, t2, v0 # save bits shifted out
+ srl t2, t2, t9
+ b norm_noshift_s
+
+/*
+ * Convert single to double.
+ */
+cvt_d_s:
+ jal get_fs_s
+ move t3, zero
+ bne t1, SEXP_INF, 1f # is FS an infinity?
+ li t1, DEXP_INF # convert to double
+ b result_fs_d
+1:
+ bne t1, zero, 2f # is FS denormalized or zero?
+ beq t2, zero, result_fs_d # is FS zero?
+ jal renorm_fs_s
+ move t8, zero
+ b norm_d
+2:
+ addu t1, t1, DEXP_BIAS - SEXP_BIAS # bias exponent correctly
+ sll t3, t2, 32 - 3 # convert S fraction to D
+ srl t2, t2, 3
+ b result_fs_d
+
+/*
+ * Convert integer to double.
+ */
+cvt_d_w:
+ jal get_fs_int
+ bne t2, zero, 1f # check for zero
+ move t1, zero # result=0
+ move t3, zero
+ b result_fs_d
+/*
+ * Find out how many leading zero bits are in t2 and put in t9.
+ */
+1:
+ move v0, t2
+ move t9, zero
+ srl v1, v0, 16
+ bne v1, zero, 1f
+ addu t9, 16
+ sll v0, 16
+1:
+ srl v1, v0, 24
+ bne v1, zero, 1f
+ addu t9, 8
+ sll v0, 8
+1:
+ srl v1, v0, 28
+ bne v1, zero, 1f
+ addu t9, 4
+ sll v0, 4
+1:
+ srl v1, v0, 30
+ bne v1, zero, 1f
+ addu t9, 2
+ sll v0, 2
+1:
+ srl v1, v0, 31
+ bne v1, zero, 1f
+ addu t9, 1
+/*
+ * Now shift t2 the correct number of bits.
+ */
+1:
+ subu t9, t9, DLEAD_ZEROS # dont count leading zeros
+ li t1, DEXP_BIAS + 20 # init exponent
+ subu t1, t1, t9 # compute exponent
+ beq t9, zero, 1f
+ li v0, 32
+ blt t9, zero, 2f # if shift < 0, shift right
+ subu v0, v0, t9
+ sll t2, t2, t9 # shift left
+1:
+ and t2, t2, ~DIMPL_ONE # clear implied one bit
+ move t3, zero
+ b result_fs_d
+2:
+ negu t9 # shift right by t9
+ subu v0, v0, t9
+ sll t3, t2, v0
+ srl t2, t2, t9
+ and t2, t2, ~DIMPL_ONE # clear implied one bit
+ b result_fs_d
+
+/*
+ * Convert single to integer.
+ */
+cvt_w_s:
+ jal get_fs_s
+ bne t1, SEXP_INF, 1f # is FS an infinity?
+ bne t2, zero, invalid_w # invalid conversion
+1:
+ bne t1, zero, 1f # is FS zero?
+ beq t2, zero, result_fs_w # result is zero
+ move t2, zero # result is an inexact zero
+ b inexact_w
+1:
+ subu t1, t1, SEXP_BIAS # unbias exponent
+ or t2, t2, SIMPL_ONE # add implied one bit
+ sll t3, t2, 32 - 3 # convert S fraction to D
+ srl t2, t2, 3
+ b cvt_w
+
+/*
+ * Convert double to integer.
+ */
+cvt_w_d:
+ jal get_fs_d
+ bne t1, DEXP_INF, 1f # is FS an infinity?
+ bne t2, zero, invalid_w # invalid conversion
+ bne t3, zero, invalid_w # invalid conversion
+1:
+ bne t1, zero, 2f # is FS zero?
+ bne t2, zero, 1f
+ beq t3, zero, result_fs_w # result is zero
+1:
+ move t2, zero # result is an inexact zero
+ b inexact_w
+2:
+ subu t1, t1, DEXP_BIAS # unbias exponent
+ or t2, t2, DIMPL_ONE # add implied one bit
+cvt_w:
+ blt t1, WEXP_MIN, underflow_w # is exponent too small?
+ li v0, WEXP_MAX+1
+ bgt t1, v0, overflow_w # is exponent too large?
+ bne t1, v0, 1f # special check for INT_MIN
+ beq t0, zero, overflow_w # if positive, overflow
+ bne t2, DIMPL_ONE, overflow_w
+ bne t3, zero, overflow_w
+ li t2, INT_MIN # result is INT_MIN
+ b result_fs_w
+1:
+ subu v0, t1, 20 # compute amount to shift
+ beq v0, zero, 2f # is shift needed?
+ li v1, 32
+ blt v0, zero, 1f # if shift < 0, shift right
+ subu v1, v1, v0 # shift left
+ sll t2, t2, v0
+ srl t9, t3, v1 # save bits shifted out of t3
+ or t2, t2, t9 # and put into t2
+ sll t3, t3, v0 # shift FSs fraction
+ b 2f
+1:
+ negu v0 # shift right by v0
+ subu v1, v1, v0
+ sll t8, t3, v1 # save bits shifted out
+ sltu t8, zero, t8 # dont lose any ones
+ srl t3, t3, v0 # shift FSs fraction
+ or t3, t3, t8
+ sll t9, t2, v1 # save bits shifted out of t2
+ or t3, t3, t9 # and put into t3
+ srl t2, t2, v0
+/*
+ * round result (t0 is sign, t2 is integer part, t3 is fractional part).
+ */
+2:
+ and v0, a1, MIPS_FPU_ROUNDING_BITS # get rounding mode
+ beq v0, MIPS_FPU_ROUND_RN, 3f # round to nearest
+ beq v0, MIPS_FPU_ROUND_RZ, 5f # round to zero (truncate)
+ beq v0, MIPS_FPU_ROUND_RP, 1f # round to +infinity
+ beq t0, zero, 5f # if sign is positive, truncate
+ b 2f
+1:
+ bne t0, zero, 5f # if sign is negative, truncate
+2:
+ beq t3, zero, 5f # if no fraction bits, continue
+ addu t2, t2, 1 # add rounding bit
+ blt t2, zero, overflow_w # overflow?
+ b 5f
+3:
+ li v0, GUARDBIT # load guard bit for rounding
+ addu v0, v0, t3 # add remainder
+ sltu v1, v0, t3 # compute carry out
+ beq v1, zero, 4f # if no carry, continue
+ addu t2, t2, 1 # add carry to result
+ blt t2, zero, overflow_w # overflow?
+4:
+ bne v0, zero, 5f # if rounded remainder is zero
+ and t2, t2, ~1 # clear LSB (round to nearest)
+5:
+ beq t0, zero, 1f # result positive?
+ negu t2 # convert to negative integer
+1:
+ beq t3, zero, result_fs_w # is result exact?
+/*
+ * Handle inexact exception.
+ */
+inexact_w:
+ or a1, a1, MIPS_FPU_EXCEPTION_INEXACT | MIPS_FPU_STICKY_INEXACT
+ and v0, a1, MIPS_FPU_ENABLE_INEXACT
+ bne v0, zero, fpe_trap
+ ctc1 a1, MIPS_FPU_CSR # save exceptions
+ b result_fs_w
+
+/*
+ * Conversions to integer which overflow will trap (if enabled),
+ * or generate an inexact trap (if enabled),
+ * or generate an invalid exception.
+ */
+overflow_w:
+ or a1, a1, MIPS_FPU_EXCEPTION_OVERFLOW | MIPS_FPU_STICKY_OVERFLOW
+ and v0, a1, MIPS_FPU_ENABLE_OVERFLOW
+ bne v0, zero, fpe_trap
+ and v0, a1, MIPS_FPU_ENABLE_INEXACT
+ bne v0, zero, inexact_w # inexact traps enabled?
+ b invalid_w
+
+/*
+ * Conversions to integer which underflow will trap (if enabled),
+ * or generate an inexact trap (if enabled),
+ * or generate an invalid exception.
+ */
+underflow_w:
+ or a1, a1, MIPS_FPU_EXCEPTION_UNDERFLOW | MIPS_FPU_STICKY_UNDERFLOW
+ and v0, a1, MIPS_FPU_ENABLE_UNDERFLOW
+ bne v0, zero, fpe_trap
+ and v0, a1, MIPS_FPU_ENABLE_INEXACT
+ bne v0, zero, inexact_w # inexact traps enabled?
+ b invalid_w
+
+/*
+ * Compare single.
+ */
+cmp_s:
+ jal get_cmp_s
+ bne t1, SEXP_INF, 1f # is FS an infinity?
+ bne t2, zero, unordered # FS is a NAN
+1:
+ bne ta1, SEXP_INF, 2f # is FT an infinity?
+ bne ta2, zero, unordered # FT is a NAN
+2:
+ sll t1, t1, 23 # reassemble exp & frac
+ or t1, t1, t2
+ sll ta1, ta1, 23 # reassemble exp & frac
+ or ta1, ta1, ta2
+ beq t0, zero, 1f # is FS positive?
+ negu t1
+1:
+ beq ta0, zero, 1f # is FT positive?
+ negu ta1
+1:
+ li v0, COND_LESS
+ blt t1, ta1, test_cond # is FS < FT?
+ li v0, COND_EQUAL
+ beq t1, ta1, test_cond # is FS == FT?
+ move v0, zero # FS > FT
+ b test_cond
+
+/*
+ * Compare double.
+ */
+cmp_d:
+ jal get_cmp_d
+ bne t1, DEXP_INF, 1f # is FS an infinity?
+ bne t2, zero, unordered
+ bne t3, zero, unordered # FS is a NAN
+1:
+ bne ta1, DEXP_INF, 2f # is FT an infinity?
+ bne ta2, zero, unordered
+ bne ta3, zero, unordered # FT is a NAN
+2:
+ sll t1, t1, 20 # reassemble exp & frac
+ or t1, t1, t2
+ sll ta1, ta1, 20 # reassemble exp & frac
+ or ta1, ta1, ta2
+ beq t0, zero, 1f # is FS positive?
+ not t3 # negate t1,t3
+ not t1
+ addu t3, t3, 1
+ seq v0, t3, zero # compute carry
+ addu t1, t1, v0
+1:
+ beq ta0, zero, 1f # is FT positive?
+ not ta3 # negate ta1,ta3
+ not ta1
+ addu ta3, ta3, 1
+ seq v0, ta3, zero # compute carry
+ addu ta1, ta1, v0
+1:
+ li v0, COND_LESS
+ blt t1, ta1, test_cond # is FS(MSW) < FT(MSW)?
+ move v0, zero
+ bne t1, ta1, test_cond # is FS(MSW) > FT(MSW)?
+ li v0, COND_LESS
+ bltu t3, ta3, test_cond # is FS(LSW) < FT(LSW)?
+ li v0, COND_EQUAL
+ beq t3, ta3, test_cond # is FS(LSW) == FT(LSW)?
+ move v0, zero # FS > FT
+test_cond:
+ and v0, v0, a0 # condition match instruction?
+set_cond:
+ bne v0, zero, 1f
+ and a1, a1, ~MIPS_FPU_COND_BIT # clear condition bit
+ b 2f
+1:
+ or a1, a1, MIPS_FPU_COND_BIT # set condition bit
+2:
+ ctc1 a1, MIPS_FPU_CSR # save condition bit
+ b done
+
+unordered:
+ and v0, a0, COND_UNORDERED # this cmp match unordered?
+ bne v0, zero, 1f
+ and a1, a1, ~MIPS_FPU_COND_BIT # clear condition bit
+ b 2f
+1:
+ or a1, a1, MIPS_FPU_COND_BIT # set condition bit
+2:
+ and v0, a0, COND_SIGNAL
+ beq v0, zero, 1f # is this a signaling cmp?
+ or a1, a1, MIPS_FPU_EXCEPTION_INVALID | MIPS_FPU_STICKY_INVALID
+ and v0, a1, MIPS_FPU_ENABLE_INVALID
+ bne v0, zero, fpe_trap
+1:
+ ctc1 a1, MIPS_FPU_CSR # save condition bit
+ b done
+
+/*
+ * Determine the amount to shift the fraction in order to restore the
+ * normalized position. After that, round and handle exceptions.
+ */
+norm_s:
+ move v0, t2
+ move t9, zero # t9 = num of leading zeros
+ bne t2, zero, 1f
+ move v0, t8
+ addu t9, 32
+1:
+ srl v1, v0, 16
+ bne v1, zero, 1f
+ addu t9, 16
+ sll v0, 16
+1:
+ srl v1, v0, 24
+ bne v1, zero, 1f
+ addu t9, 8
+ sll v0, 8
+1:
+ srl v1, v0, 28
+ bne v1, zero, 1f
+ addu t9, 4
+ sll v0, 4
+1:
+ srl v1, v0, 30
+ bne v1, zero, 1f
+ addu t9, 2
+ sll v0, 2
+1:
+ srl v1, v0, 31
+ bne v1, zero, 1f
+ addu t9, 1
+/*
+ * Now shift t2,t8 the correct number of bits.
+ */
+1:
+ subu t9, t9, SLEAD_ZEROS # dont count leading zeros
+ subu t1, t1, t9 # adjust the exponent
+ beq t9, zero, norm_noshift_s
+ li v1, 32
+ blt t9, zero, 1f # if shift < 0, shift right
+ subu v1, v1, t9
+ sll t2, t2, t9 # shift t2,t8 left
+ srl v0, t8, v1 # save bits shifted out
+ or t2, t2, v0
+ sll t8, t8, t9
+ b norm_noshift_s
+1:
+ negu t9 # shift t2,t8 right by t9
+ subu v1, v1, t9
+ sll v0, t8, v1 # save bits shifted out
+ sltu v0, zero, v0 # be sure to save any one bits
+ srl t8, t8, t9
+ or t8, t8, v0
+ sll v0, t2, v1 # save bits shifted out
+ or t8, t8, v0
+ srl t2, t2, t9
+norm_noshift_s:
+ move ta1, t1 # save unrounded exponent
+ move ta2, t2 # save unrounded fraction
+ and v0, a1, MIPS_FPU_ROUNDING_BITS # get rounding mode
+ beq v0, MIPS_FPU_ROUND_RN, 3f # round to nearest
+ beq v0, MIPS_FPU_ROUND_RZ, 5f # round to zero (truncate)
+ beq v0, MIPS_FPU_ROUND_RP, 1f # round to +infinity
+ beq t0, zero, 5f # if sign is positive, truncate
+ b 2f
+1:
+ bne t0, zero, 5f # if sign is negative, truncate
+2:
+ beq t8, zero, 5f # if exact, continue
+ addu t2, t2, 1 # add rounding bit
+ bne t2, SIMPL_ONE<<1, 5f # need to adjust exponent?
+ addu t1, t1, 1 # adjust exponent
+ srl t2, t2, 1 # renormalize fraction
+ b 5f
+3:
+ li v0, GUARDBIT # load guard bit for rounding
+ addu v0, v0, t8 # add remainder
+ sltu v1, v0, t8 # compute carry out
+ beq v1, zero, 4f # if no carry, continue
+ addu t2, t2, 1 # add carry to result
+ bne t2, SIMPL_ONE<<1, 4f # need to adjust exponent?
+ addu t1, t1, 1 # adjust exponent
+ srl t2, t2, 1 # renormalize fraction
+4:
+ bne v0, zero, 5f # if rounded remainder is zero
+ and t2, t2, ~1 # clear LSB (round to nearest)
+5:
+ bgt t1, SEXP_MAX, overflow_s # overflow?
+ blt t1, SEXP_MIN, underflow_s # underflow?
+ bne t8, zero, inexact_s # is result inexact?
+ addu t1, t1, SEXP_BIAS # bias exponent
+ and t2, t2, ~SIMPL_ONE # clear implied one bit
+ b result_fs_s
+
+/*
+ * Handle inexact exception.
+ */
+inexact_s:
+ addu t1, t1, SEXP_BIAS # bias exponent
+ and t2, t2, ~SIMPL_ONE # clear implied one bit
+inexact_nobias_s:
+ jal set_fd_s # save result
+ or a1, a1, MIPS_FPU_EXCEPTION_INEXACT | MIPS_FPU_STICKY_INEXACT
+ and v0, a1, MIPS_FPU_ENABLE_INEXACT
+ bne v0, zero, fpe_trap
+ ctc1 a1, MIPS_FPU_CSR # save exceptions
+ b done
+
+/*
+ * Overflow will trap (if enabled),
+ * or generate an inexact trap (if enabled),
+ * or generate an infinity.
+ */
+overflow_s:
+ or a1, a1, MIPS_FPU_EXCEPTION_OVERFLOW | MIPS_FPU_STICKY_OVERFLOW
+ and v0, a1, MIPS_FPU_ENABLE_OVERFLOW
+ beq v0, zero, 1f
+ subu t1, t1, 192 # bias exponent
+ and t2, t2, ~SIMPL_ONE # clear implied one bit
+ jal set_fd_s # save result
+ b fpe_trap
+1:
+ and v0, a1, MIPS_FPU_ROUNDING_BITS # get rounding mode
+ beq v0, MIPS_FPU_ROUND_RN, 3f # round to nearest
+ beq v0, MIPS_FPU_ROUND_RZ, 1f # round to zero (truncate)
+ beq v0, MIPS_FPU_ROUND_RP, 2f # round to +infinity
+ bne t0, zero, 3f
+1:
+ li t1, SEXP_MAX # result is max finite
+ li t2, 0x007fffff
+ b inexact_s
+2:
+ bne t0, zero, 1b
+3:
+ li t1, SEXP_MAX + 1 # result is infinity
+ move t2, zero
+ b inexact_s
+
+/*
+ * In this implementation, "tininess" is detected "after rounding" and
+ * "loss of accuracy" is detected as "an inexact result".
+ */
+underflow_s:
+ and v0, a1, MIPS_FPU_ENABLE_UNDERFLOW
+ beq v0, zero, 1f
+/*
+ * Underflow is enabled so compute the result and trap.
+ */
+ addu t1, t1, 192 # bias exponent
+ and t2, t2, ~SIMPL_ONE # clear implied one bit
+ jal set_fd_s # save result
+ or a1, a1, MIPS_FPU_EXCEPTION_UNDERFLOW | MIPS_FPU_STICKY_UNDERFLOW
+ b fpe_trap
+/*
+ * Underflow is not enabled so compute the result,
+ * signal inexact result (if it is) and trap (if enabled).
+ */
+1:
+ move t1, ta1 # get unrounded exponent
+ move t2, ta2 # get unrounded fraction
+ li t9, SEXP_MIN # compute shift amount
+ subu t9, t9, t1 # shift t2,t8 right by t9
+ blt t9, SFRAC_BITS+2, 3f # shift all the bits out?
+ move t1, zero # result is inexact zero
+ move t2, zero
+ or a1, a1, MIPS_FPU_EXCEPTION_UNDERFLOW | MIPS_FPU_STICKY_UNDERFLOW
+/*
+ * Now round the zero result.
+ * Only need to worry about rounding to +- infinity when the sign matches.
+ */
+ and v0, a1, MIPS_FPU_ROUNDING_BITS # get rounding mode
+ beq v0, MIPS_FPU_ROUND_RN, inexact_nobias_s # round to nearest
+ beq v0, MIPS_FPU_ROUND_RZ, inexact_nobias_s # round to zero
+ beq v0, MIPS_FPU_ROUND_RP, 1f # round to +infinity
+ beq t0, zero, inexact_nobias_s # if sign is positive, truncate
+ b 2f
+1:
+ bne t0, zero, inexact_nobias_s # if sign is negative, truncate
+2:
+ addu t2, t2, 1 # add rounding bit
+ b inexact_nobias_s
+3:
+ li v1, 32
+ subu v1, v1, t9
+ sltu v0, zero, t8 # be sure to save any one bits
+ sll t8, t2, v1 # save bits shifted out
+ or t8, t8, v0 # include sticky bits
+ srl t2, t2, t9
+/*
+ * Now round the denormalized result.
+ */
+ and v0, a1, MIPS_FPU_ROUNDING_BITS # get rounding mode
+ beq v0, MIPS_FPU_ROUND_RN, 3f # round to nearest
+ beq v0, MIPS_FPU_ROUND_RZ, 5f # round to zero (truncate)
+ beq v0, MIPS_FPU_ROUND_RP, 1f # round to +infinity
+ beq t0, zero, 5f # if sign is positive, truncate
+ b 2f
+1:
+ bne t0, zero, 5f # if sign is negative, truncate
+2:
+ beq t8, zero, 5f # if exact, continue
+ addu t2, t2, 1 # add rounding bit
+ b 5f
+3:
+ li v0, GUARDBIT # load guard bit for rounding
+ addu v0, v0, t8 # add remainder
+ sltu v1, v0, t8 # compute carry out
+ beq v1, zero, 4f # if no carry, continue
+ addu t2, t2, 1 # add carry to result
+4:
+ bne v0, zero, 5f # if rounded remainder is zero
+ and t2, t2, ~1 # clear LSB (round to nearest)
+5:
+ move t1, zero # denorm or zero exponent
+ jal set_fd_s # save result
+ beq t8, zero, done # check for exact result
+ or a1, a1, MIPS_FPU_EXCEPTION_UNDERFLOW | MIPS_FPU_STICKY_UNDERFLOW
+ or a1, a1, MIPS_FPU_EXCEPTION_INEXACT | MIPS_FPU_STICKY_INEXACT
+ and v0, a1, MIPS_FPU_ENABLE_INEXACT
+ bne v0, zero, fpe_trap
+ ctc1 a1, MIPS_FPU_CSR # save exceptions
+ b done
+
+/*
+ * Determine the amount to shift the fraction in order to restore the
+ * normalized position. After that, round and handle exceptions.
+ */
+norm_d:
+ move v0, t2
+ move t9, zero # t9 = num of leading zeros
+ bne t2, zero, 1f
+ move v0, t3
+ addu t9, 32
+ bne t3, zero, 1f
+ move v0, t8
+ addu t9, 32
+1:
+ srl v1, v0, 16
+ bne v1, zero, 1f
+ addu t9, 16
+ sll v0, 16
+1:
+ srl v1, v0, 24
+ bne v1, zero, 1f
+ addu t9, 8
+ sll v0, 8
+1:
+ srl v1, v0, 28
+ bne v1, zero, 1f
+ addu t9, 4
+ sll v0, 4
+1:
+ srl v1, v0, 30
+ bne v1, zero, 1f
+ addu t9, 2
+ sll v0, 2
+1:
+ srl v1, v0, 31
+ bne v1, zero, 1f
+ addu t9, 1
+/*
+ * Now shift t2,t3,t8 the correct number of bits.
+ */
+1:
+ subu t9, t9, DLEAD_ZEROS # dont count leading zeros
+ subu t1, t1, t9 # adjust the exponent
+ beq t9, zero, norm_noshift_d
+ li v1, 32
+ blt t9, zero, 2f # if shift < 0, shift right
+ blt t9, v1, 1f # shift by < 32?
+ subu t9, t9, v1 # shift by >= 32
+ subu v1, v1, t9
+ sll t2, t3, t9 # shift left by t9
+ srl v0, t8, v1 # save bits shifted out
+ or t2, t2, v0
+ sll t3, t8, t9
+ move t8, zero
+ b norm_noshift_d
+1:
+ subu v1, v1, t9
+ sll t2, t2, t9 # shift left by t9
+ srl v0, t3, v1 # save bits shifted out
+ or t2, t2, v0
+ sll t3, t3, t9
+ srl v0, t8, v1 # save bits shifted out
+ or t3, t3, v0
+ sll t8, t8, t9
+ b norm_noshift_d
+2:
+ negu t9 # shift right by t9
+ subu v1, v1, t9 # (known to be < 32 bits)
+ sll v0, t8, v1 # save bits shifted out
+ sltu v0, zero, v0 # be sure to save any one bits
+ srl t8, t8, t9
+ or t8, t8, v0
+ sll v0, t3, v1 # save bits shifted out
+ or t8, t8, v0
+ srl t3, t3, t9
+ sll v0, t2, v1 # save bits shifted out
+ or t3, t3, v0
+ srl t2, t2, t9
+norm_noshift_d:
+ move ta1, t1 # save unrounded exponent
+ move ta2, t2 # save unrounded fraction (MS)
+ move ta3, t3 # save unrounded fraction (LS)
+ and v0, a1, MIPS_FPU_ROUNDING_BITS # get rounding mode
+ beq v0, MIPS_FPU_ROUND_RN, 3f # round to nearest
+ beq v0, MIPS_FPU_ROUND_RZ, 5f # round to zero (truncate)
+ beq v0, MIPS_FPU_ROUND_RP, 1f # round to +infinity
+ beq t0, zero, 5f # if sign is positive, truncate
+ b 2f
+1:
+ bne t0, zero, 5f # if sign is negative, truncate
+2:
+ beq t8, zero, 5f # if exact, continue
+ addu t3, t3, 1 # add rounding bit
+ bne t3, zero, 5f # branch if no carry
+ addu t2, t2, 1 # add carry
+ bne t2, DIMPL_ONE<<1, 5f # need to adjust exponent?
+ addu t1, t1, 1 # adjust exponent
+ srl t2, t2, 1 # renormalize fraction
+ b 5f
+3:
+ li v0, GUARDBIT # load guard bit for rounding
+ addu v0, v0, t8 # add remainder
+ sltu v1, v0, t8 # compute carry out
+ beq v1, zero, 4f # branch if no carry
+ addu t3, t3, 1 # add carry
+ bne t3, zero, 4f # branch if no carry
+ addu t2, t2, 1 # add carry to result
+ bne t2, DIMPL_ONE<<1, 4f # need to adjust exponent?
+ addu t1, t1, 1 # adjust exponent
+ srl t2, t2, 1 # renormalize fraction
+4:
+ bne v0, zero, 5f # if rounded remainder is zero
+ and t3, t3, ~1 # clear LSB (round to nearest)
+5:
+ bgt t1, DEXP_MAX, overflow_d # overflow?
+ blt t1, DEXP_MIN, underflow_d # underflow?
+ bne t8, zero, inexact_d # is result inexact?
+ addu t1, t1, DEXP_BIAS # bias exponent
+ and t2, t2, ~DIMPL_ONE # clear implied one bit
+ b result_fs_d
+
+/*
+ * Handle inexact exception.
+ */
+inexact_d:
+ addu t1, t1, DEXP_BIAS # bias exponent
+ and t2, t2, ~DIMPL_ONE # clear implied one bit
+inexact_nobias_d:
+ jal set_fd_d # save result
+ or a1, a1, MIPS_FPU_EXCEPTION_INEXACT | MIPS_FPU_STICKY_INEXACT
+ and v0, a1, MIPS_FPU_ENABLE_INEXACT
+ bne v0, zero, fpe_trap
+ ctc1 a1, MIPS_FPU_CSR # save exceptions
+ b done
+
+/*
+ * Overflow will trap (if enabled),
+ * or generate an inexact trap (if enabled),
+ * or generate an infinity.
+ */
+overflow_d:
+ or a1, a1, MIPS_FPU_EXCEPTION_OVERFLOW | MIPS_FPU_STICKY_OVERFLOW
+ and v0, a1, MIPS_FPU_ENABLE_OVERFLOW
+ beq v0, zero, 1f
+ subu t1, t1, 1536 # bias exponent
+ and t2, t2, ~DIMPL_ONE # clear implied one bit
+ jal set_fd_d # save result
+ b fpe_trap
+1:
+ and v0, a1, MIPS_FPU_ROUNDING_BITS # get rounding mode
+ beq v0, MIPS_FPU_ROUND_RN, 3f # round to nearest
+ beq v0, MIPS_FPU_ROUND_RZ, 1f # round to zero (truncate)
+ beq v0, MIPS_FPU_ROUND_RP, 2f # round to +infinity
+ bne t0, zero, 3f
+1:
+ li t1, DEXP_MAX # result is max finite
+ li t2, 0x000fffff
+ li t3, 0xffffffff
+ b inexact_d
+2:
+ bne t0, zero, 1b
+3:
+ li t1, DEXP_MAX + 1 # result is infinity
+ move t2, zero
+ move t3, zero
+ b inexact_d
+
+/*
+ * In this implementation, "tininess" is detected "after rounding" and
+ * "loss of accuracy" is detected as "an inexact result".
+ */
+underflow_d:
+ and v0, a1, MIPS_FPU_ENABLE_UNDERFLOW
+ beq v0, zero, 1f
+/*
+ * Underflow is enabled so compute the result and trap.
+ */
+ addu t1, t1, 1536 # bias exponent
+ and t2, t2, ~DIMPL_ONE # clear implied one bit
+ jal set_fd_d # save result
+ or a1, a1, MIPS_FPU_EXCEPTION_UNDERFLOW | MIPS_FPU_STICKY_UNDERFLOW
+ b fpe_trap
+/*
+ * Underflow is not enabled so compute the result,
+ * signal inexact result (if it is) and trap (if enabled).
+ */
+1:
+ move t1, ta1 # get unrounded exponent
+ move t2, ta2 # get unrounded fraction (MS)
+ move t3, ta3 # get unrounded fraction (LS)
+ li t9, DEXP_MIN # compute shift amount
+ subu t9, t9, t1 # shift t2,t8 right by t9
+ blt t9, DFRAC_BITS+2, 3f # shift all the bits out?
+ move t1, zero # result is inexact zero
+ move t2, zero
+ move t3, zero
+ or a1, a1, MIPS_FPU_EXCEPTION_UNDERFLOW | MIPS_FPU_STICKY_UNDERFLOW
+/*
+ * Now round the zero result.
+ * Only need to worry about rounding to +- infinity when the sign matches.
+ */
+ and v0, a1, MIPS_FPU_ROUNDING_BITS # get rounding mode
+ beq v0, MIPS_FPU_ROUND_RN, inexact_nobias_d # round to nearest
+ beq v0, MIPS_FPU_ROUND_RZ, inexact_nobias_d # round to zero
+ beq v0, MIPS_FPU_ROUND_RP, 1f # round to +infinity
+ beq t0, zero, inexact_nobias_d # if sign is positive, truncate
+ b 2f
+1:
+ bne t0, zero, inexact_nobias_d # if sign is negative, truncate
+2:
+ addu t3, t3, 1 # add rounding bit
+ b inexact_nobias_d
+3:
+ li v1, 32
+ blt t9, v1, 1f # shift by < 32?
+ subu t9, t9, v1 # shift right by >= 32
+ subu v1, v1, t9
+ sltu v0, zero, t8 # be sure to save any one bits
+ sll t8, t2, v1 # save bits shifted out
+ or t8, t8, v0 # include sticky bits
+ srl t3, t2, t9
+ move t2, zero
+ b 2f
+1:
+ subu v1, v1, t9 # shift right by t9
+ sltu v0, zero, t8 # be sure to save any one bits
+ sll t8, t3, v1 # save bits shifted out
+ or t8, t8, v0 # include sticky bits
+ srl t3, t3, t9
+ sll v0, t2, v1 # save bits shifted out
+ or t3, t3, v0
+ srl t2, t2, t9
+/*
+ * Now round the denormalized result.
+ */
+2:
+ and v0, a1, MIPS_FPU_ROUNDING_BITS # get rounding mode
+ beq v0, MIPS_FPU_ROUND_RN, 3f # round to nearest
+ beq v0, MIPS_FPU_ROUND_RZ, 5f # round to zero (truncate)
+ beq v0, MIPS_FPU_ROUND_RP, 1f # round to +infinity
+ beq t0, zero, 5f # if sign is positive, truncate
+ b 2f
+1:
+ bne t0, zero, 5f # if sign is negative, truncate
+2:
+ beq t8, zero, 5f # if exact, continue
+ addu t3, t3, 1 # add rounding bit
+ bne t3, zero, 5f # if no carry, continue
+ addu t2, t2, 1 # add carry
+ b 5f
+3:
+ li v0, GUARDBIT # load guard bit for rounding
+ addu v0, v0, t8 # add remainder
+ sltu v1, v0, t8 # compute carry out
+ beq v1, zero, 4f # if no carry, continue
+ addu t3, t3, 1 # add rounding bit
+ bne t3, zero, 4f # if no carry, continue
+ addu t2, t2, 1 # add carry
+4:
+ bne v0, zero, 5f # if rounded remainder is zero
+ and t3, t3, ~1 # clear LSB (round to nearest)
+5:
+ move t1, zero # denorm or zero exponent
+ jal set_fd_d # save result
+ beq t8, zero, done # check for exact result
+ or a1, a1, MIPS_FPU_EXCEPTION_UNDERFLOW | MIPS_FPU_STICKY_UNDERFLOW
+ or a1, a1, MIPS_FPU_EXCEPTION_INEXACT | MIPS_FPU_STICKY_INEXACT
+ and v0, a1, MIPS_FPU_ENABLE_INEXACT
+ bne v0, zero, fpe_trap
+ ctc1 a1, MIPS_FPU_CSR # save exceptions
+ b done
+
+/*
+ * Signal an invalid operation if the trap is enabled; otherwise,
+ * the result is a quiet NAN.
+ */
+invalid_s: # trap invalid operation
+ or a1, a1, MIPS_FPU_EXCEPTION_INVALID | MIPS_FPU_STICKY_INVALID
+ and v0, a1, MIPS_FPU_ENABLE_INVALID
+ bne v0, zero, fpe_trap
+ ctc1 a1, MIPS_FPU_CSR # save exceptions
+ move t0, zero # result is a quiet NAN
+ li t1, SEXP_INF
+ li t2, SQUIET_NAN
+ jal set_fd_s # save result (in t0,t1,t2)
+ b done
+
+/*
+ * Signal an invalid operation if the trap is enabled; otherwise,
+ * the result is a quiet NAN.
+ */
+invalid_d: # trap invalid operation
+ or a1, a1, MIPS_FPU_EXCEPTION_INVALID | MIPS_FPU_STICKY_INVALID
+ and v0, a1, MIPS_FPU_ENABLE_INVALID
+ bne v0, zero, fpe_trap
+ ctc1 a1, MIPS_FPU_CSR # save exceptions
+ move t0, zero # result is a quiet NAN
+ li t1, DEXP_INF
+ li t2, DQUIET_NAN0
+ li t3, DQUIET_NAN1
+ jal set_fd_d # save result (in t0,t1,t2,t3)
+ b done
+
+/*
+ * Signal an invalid operation if the trap is enabled; otherwise,
+ * the result is INT_MAX or INT_MIN.
+ */
+invalid_w: # trap invalid operation
+ or a1, a1, MIPS_FPU_EXCEPTION_INVALID | MIPS_FPU_STICKY_INVALID
+ and v0, a1, MIPS_FPU_ENABLE_INVALID
+ bne v0, zero, fpe_trap
+ ctc1 a1, MIPS_FPU_CSR # save exceptions
+ bne t0, zero, 1f
+ li t2, INT_MAX # result is INT_MAX
+ b result_fs_w
+1:
+ li t2, INT_MIN # result is INT_MIN
+ b result_fs_w
+
+/*
+ * Trap if the hardware should have handled this case.
+ */
+fpe_trap:
+ move a2, a1 # code = FP CSR
+ ctc1 a1, MIPS_FPU_CSR # save exceptions
+ break 0
+
+/*
+ * Send an illegal instruction signal to the current process.
+ */
+ill:
+ ctc1 a1, MIPS_FPU_CSR # save exceptions
+ move a2, a0 # code = FP instruction
+ break 0
+
+result_ft_s:
+ move t0, ta0 # result is FT
+ move t1, ta1
+ move t2, ta2
+result_fs_s: # result is FS
+ jal set_fd_s # save result (in t0,t1,t2)
+ b done
+
+result_fs_w:
+ jal set_fd_word # save result (in t2)
+ b done
+
+result_ft_d:
+ move t0, ta0 # result is FT
+ move t1, ta1
+ move t2, ta2
+ move t3, ta3
+result_fs_d: # result is FS
+ jal set_fd_d # save result (in t0,t1,t2,t3)
+
+done:
+ lw ra, CALLFRAME_RA(sp)
+ addu sp, sp, CALLFRAME_SIZ
+ j ra
+END(MipsEmulateFP)
+
+/*----------------------------------------------------------------------------
+ * get_fs_int --
+ *
+ * Read (integer) the FS register (bits 15-11).
+ * This is an internal routine used by MipsEmulateFP only.
+ *
+ * Results:
+ * t0 contains the sign
+ * t2 contains the fraction
+ *
+ *----------------------------------------------------------------------------
+ */
+LEAF(get_fs_int)
+ srl a3, a0, 12 - 2 # get FS field (even regs only)
+ and a3, a3, 0xF << 2 # mask FS field
+ lw a3, get_fs_int_tbl(a3) # switch on register number
+ j a3
+
+ .rdata
+get_fs_int_tbl:
+ .word get_fs_int_f0
+ .word get_fs_int_f2
+ .word get_fs_int_f4
+ .word get_fs_int_f6
+ .word get_fs_int_f8
+ .word get_fs_int_f10
+ .word get_fs_int_f12
+ .word get_fs_int_f14
+ .word get_fs_int_f16
+ .word get_fs_int_f18
+ .word get_fs_int_f20
+ .word get_fs_int_f22
+ .word get_fs_int_f24
+ .word get_fs_int_f26
+ .word get_fs_int_f28
+ .word get_fs_int_f30
+ .text
+
+get_fs_int_f0:
+ mfc1 t2, $f0
+ b get_fs_int_done
+get_fs_int_f2:
+ mfc1 t2, $f2
+ b get_fs_int_done
+get_fs_int_f4:
+ mfc1 t2, $f4
+ b get_fs_int_done
+get_fs_int_f6:
+ mfc1 t2, $f6
+ b get_fs_int_done
+get_fs_int_f8:
+ mfc1 t2, $f8
+ b get_fs_int_done
+get_fs_int_f10:
+ mfc1 t2, $f10
+ b get_fs_int_done
+get_fs_int_f12:
+ mfc1 t2, $f12
+ b get_fs_int_done
+get_fs_int_f14:
+ mfc1 t2, $f14
+ b get_fs_int_done
+get_fs_int_f16:
+ mfc1 t2, $f16
+ b get_fs_int_done
+get_fs_int_f18:
+ mfc1 t2, $f18
+ b get_fs_int_done
+get_fs_int_f20:
+ mfc1 t2, $f20
+ b get_fs_int_done
+get_fs_int_f22:
+ mfc1 t2, $f22
+ b get_fs_int_done
+get_fs_int_f24:
+ mfc1 t2, $f24
+ b get_fs_int_done
+get_fs_int_f26:
+ mfc1 t2, $f26
+ b get_fs_int_done
+get_fs_int_f28:
+ mfc1 t2, $f28
+ b get_fs_int_done
+get_fs_int_f30:
+ mfc1 t2, $f30
+get_fs_int_done:
+ srl t0, t2, 31 # init the sign bit
+ bge t2, zero, 1f
+ negu t2
+1:
+ j ra
+END(get_fs_int)
+
+/*----------------------------------------------------------------------------
+ * get_ft_fs_s --
+ *
+ * Read (single precision) the FT register (bits 20-16) and
+ * the FS register (bits 15-11) and break up into fields.
+ * This is an internal routine used by MipsEmulateFP only.
+ *
+ * Results:
+ * t0 contains the FS sign
+ * t1 contains the FS (biased) exponent
+ * t2 contains the FS fraction
+ * ta0 contains the FT sign
+ * ta1 contains the FT (biased) exponent
+ * ta2 contains the FT fraction
+ *
+ *----------------------------------------------------------------------------
+ */
+LEAF(get_ft_fs_s)
+ srl a3, a0, 17 - 2 # get FT field (even regs only)
+ and a3, a3, 0xF << 2 # mask FT field
+ lw a3, get_ft_s_tbl(a3) # switch on register number
+ j a3
+
+ .rdata
+get_ft_s_tbl:
+ .word get_ft_s_f0
+ .word get_ft_s_f2
+ .word get_ft_s_f4
+ .word get_ft_s_f6
+ .word get_ft_s_f8
+ .word get_ft_s_f10
+ .word get_ft_s_f12
+ .word get_ft_s_f14
+ .word get_ft_s_f16
+ .word get_ft_s_f18
+ .word get_ft_s_f20
+ .word get_ft_s_f22
+ .word get_ft_s_f24
+ .word get_ft_s_f26
+ .word get_ft_s_f28
+ .word get_ft_s_f30
+ .text
+
+get_ft_s_f0:
+ mfc1 ta0, $f0
+ b get_ft_s_done
+get_ft_s_f2:
+ mfc1 ta0, $f2
+ b get_ft_s_done
+get_ft_s_f4:
+ mfc1 ta0, $f4
+ b get_ft_s_done
+get_ft_s_f6:
+ mfc1 ta0, $f6
+ b get_ft_s_done
+get_ft_s_f8:
+ mfc1 ta0, $f8
+ b get_ft_s_done
+get_ft_s_f10:
+ mfc1 ta0, $f10
+ b get_ft_s_done
+get_ft_s_f12:
+ mfc1 ta0, $f12
+ b get_ft_s_done
+get_ft_s_f14:
+ mfc1 ta0, $f14
+ b get_ft_s_done
+get_ft_s_f16:
+ mfc1 ta0, $f16
+ b get_ft_s_done
+get_ft_s_f18:
+ mfc1 ta0, $f18
+ b get_ft_s_done
+get_ft_s_f20:
+ mfc1 ta0, $f20
+ b get_ft_s_done
+get_ft_s_f22:
+ mfc1 ta0, $f22
+ b get_ft_s_done
+get_ft_s_f24:
+ mfc1 ta0, $f24
+ b get_ft_s_done
+get_ft_s_f26:
+ mfc1 ta0, $f26
+ b get_ft_s_done
+get_ft_s_f28:
+ mfc1 ta0, $f28
+ b get_ft_s_done
+get_ft_s_f30:
+ mfc1 ta0, $f30
+get_ft_s_done:
+ srl ta1, ta0, 23 # get exponent
+ and ta1, ta1, 0xFF
+ and ta2, ta0, 0x7FFFFF # get fraction
+ srl ta0, ta0, 31 # get sign
+ bne ta1, SEXP_INF, 1f # is it a signaling NAN?
+ and v0, ta2, SSIGNAL_NAN
+ bne v0, zero, invalid_s
+1:
+ /* fall through to get FS */
+
+/*----------------------------------------------------------------------------
+ * get_fs_s --
+ *
+ * Read (single precision) the FS register (bits 15-11) and
+ * break up into fields.
+ * This is an internal routine used by MipsEmulateFP only.
+ *
+ * Results:
+ * t0 contains the sign
+ * t1 contains the (biased) exponent
+ * t2 contains the fraction
+ *
+ *----------------------------------------------------------------------------
+ */
+ALEAF(get_fs_s)
+ srl a3, a0, 12 - 2 # get FS field (even regs only)
+ and a3, a3, 0xF << 2 # mask FS field
+ lw a3, get_fs_s_tbl(a3) # switch on register number
+ j a3
+
+ .rdata
+get_fs_s_tbl:
+ .word get_fs_s_f0
+ .word get_fs_s_f2
+ .word get_fs_s_f4
+ .word get_fs_s_f6
+ .word get_fs_s_f8
+ .word get_fs_s_f10
+ .word get_fs_s_f12
+ .word get_fs_s_f14
+ .word get_fs_s_f16
+ .word get_fs_s_f18
+ .word get_fs_s_f20
+ .word get_fs_s_f22
+ .word get_fs_s_f24
+ .word get_fs_s_f26
+ .word get_fs_s_f28
+ .word get_fs_s_f30
+ .text
+
+get_fs_s_f0:
+ mfc1 t0, $f0
+ b get_fs_s_done
+get_fs_s_f2:
+ mfc1 t0, $f2
+ b get_fs_s_done
+get_fs_s_f4:
+ mfc1 t0, $f4
+ b get_fs_s_done
+get_fs_s_f6:
+ mfc1 t0, $f6
+ b get_fs_s_done
+get_fs_s_f8:
+ mfc1 t0, $f8
+ b get_fs_s_done
+get_fs_s_f10:
+ mfc1 t0, $f10
+ b get_fs_s_done
+get_fs_s_f12:
+ mfc1 t0, $f12
+ b get_fs_s_done
+get_fs_s_f14:
+ mfc1 t0, $f14
+ b get_fs_s_done
+get_fs_s_f16:
+ mfc1 t0, $f16
+ b get_fs_s_done
+get_fs_s_f18:
+ mfc1 t0, $f18
+ b get_fs_s_done
+get_fs_s_f20:
+ mfc1 t0, $f20
+ b get_fs_s_done
+get_fs_s_f22:
+ mfc1 t0, $f22
+ b get_fs_s_done
+get_fs_s_f24:
+ mfc1 t0, $f24
+ b get_fs_s_done
+get_fs_s_f26:
+ mfc1 t0, $f26
+ b get_fs_s_done
+get_fs_s_f28:
+ mfc1 t0, $f28
+ b get_fs_s_done
+get_fs_s_f30:
+ mfc1 t0, $f30
+get_fs_s_done:
+ srl t1, t0, 23 # get exponent
+ and t1, t1, 0xFF
+ and t2, t0, 0x7FFFFF # get fraction
+ srl t0, t0, 31 # get sign
+ bne t1, SEXP_INF, 1f # is it a signaling NAN?
+ and v0, t2, SSIGNAL_NAN
+ bne v0, zero, invalid_s
+1:
+ j ra
+END(get_ft_fs_s)
+
+/*----------------------------------------------------------------------------
+ * get_ft_fs_d --
+ *
+ * Read (double precision) the FT register (bits 20-16) and
+ * the FS register (bits 15-11) and break up into fields.
+ * This is an internal routine used by MipsEmulateFP only.
+ *
+ * Results:
+ * t0 contains the FS sign
+ * t1 contains the FS (biased) exponent
+ * t2 contains the FS fraction
+ * t3 contains the FS remaining fraction
+ * ta0 contains the FT sign
+ * ta1 contains the FT (biased) exponent
+ * ta2 contains the FT fraction
+ * ta3 contains the FT remaining fraction
+ *
+ *----------------------------------------------------------------------------
+ */
+LEAF(get_ft_fs_d)
+ srl a3, a0, 17 - 2 # get FT field (even regs only)
+ and a3, a3, 0xF << 2 # mask FT field
+ lw a3, get_ft_d_tbl(a3) # switch on register number
+ j a3
+
+ .rdata
+get_ft_d_tbl:
+ .word get_ft_d_f0
+ .word get_ft_d_f2
+ .word get_ft_d_f4
+ .word get_ft_d_f6
+ .word get_ft_d_f8
+ .word get_ft_d_f10
+ .word get_ft_d_f12
+ .word get_ft_d_f14
+ .word get_ft_d_f16
+ .word get_ft_d_f18
+ .word get_ft_d_f20
+ .word get_ft_d_f22
+ .word get_ft_d_f24
+ .word get_ft_d_f26
+ .word get_ft_d_f28
+ .word get_ft_d_f30
+ .text
+
+get_ft_d_f0:
+ mfc1 ta3, $f0
+ mfc1 ta0, $f1
+ b get_ft_d_done
+get_ft_d_f2:
+ mfc1 ta3, $f2
+ mfc1 ta0, $f3
+ b get_ft_d_done
+get_ft_d_f4:
+ mfc1 ta3, $f4
+ mfc1 ta0, $f5
+ b get_ft_d_done
+get_ft_d_f6:
+ mfc1 ta3, $f6
+ mfc1 ta0, $f7
+ b get_ft_d_done
+get_ft_d_f8:
+ mfc1 ta3, $f8
+ mfc1 ta0, $f9
+ b get_ft_d_done
+get_ft_d_f10:
+ mfc1 ta3, $f10
+ mfc1 ta0, $f11
+ b get_ft_d_done
+get_ft_d_f12:
+ mfc1 ta3, $f12
+ mfc1 ta0, $f13
+ b get_ft_d_done
+get_ft_d_f14:
+ mfc1 ta3, $f14
+ mfc1 ta0, $f15
+ b get_ft_d_done
+get_ft_d_f16:
+ mfc1 ta3, $f16
+ mfc1 ta0, $f17
+ b get_ft_d_done
+get_ft_d_f18:
+ mfc1 ta3, $f18
+ mfc1 ta0, $f19
+ b get_ft_d_done
+get_ft_d_f20:
+ mfc1 ta3, $f20
+ mfc1 ta0, $f21
+ b get_ft_d_done
+get_ft_d_f22:
+ mfc1 ta3, $f22
+ mfc1 ta0, $f23
+ b get_ft_d_done
+get_ft_d_f24:
+ mfc1 ta3, $f24
+ mfc1 ta0, $f25
+ b get_ft_d_done
+get_ft_d_f26:
+ mfc1 ta3, $f26
+ mfc1 ta0, $f27
+ b get_ft_d_done
+get_ft_d_f28:
+ mfc1 ta3, $f28
+ mfc1 ta0, $f29
+ b get_ft_d_done
+get_ft_d_f30:
+ mfc1 ta3, $f30
+ mfc1 ta0, $f31
+get_ft_d_done:
+ srl ta1, ta0, 20 # get exponent
+ and ta1, ta1, 0x7FF
+ and ta2, ta0, 0xFFFFF # get fraction
+ srl ta0, ta0, 31 # get sign
+ bne ta1, DEXP_INF, 1f # is it a signaling NAN?
+ and v0, ta2, DSIGNAL_NAN
+ bne v0, zero, invalid_d
+1:
+ /* fall through to get FS */
+
+/*----------------------------------------------------------------------------
+ * get_fs_d --
+ *
+ * Read (double precision) the FS register (bits 15-11) and
+ * break up into fields.
+ * This is an internal routine used by MipsEmulateFP only.
+ *
+ * Results:
+ * t0 contains the sign
+ * t1 contains the (biased) exponent
+ * t2 contains the fraction
+ * t3 contains the remaining fraction
+ *
+ *----------------------------------------------------------------------------
+ */
+ALEAF(get_fs_d)
+ srl a3, a0, 12 - 2 # get FS field (even regs only)
+ and a3, a3, 0xF << 2 # mask FS field
+ lw a3, get_fs_d_tbl(a3) # switch on register number
+ j a3
+
+ .rdata
+get_fs_d_tbl:
+ .word get_fs_d_f0
+ .word get_fs_d_f2
+ .word get_fs_d_f4
+ .word get_fs_d_f6
+ .word get_fs_d_f8
+ .word get_fs_d_f10
+ .word get_fs_d_f12
+ .word get_fs_d_f14
+ .word get_fs_d_f16
+ .word get_fs_d_f18
+ .word get_fs_d_f20
+ .word get_fs_d_f22
+ .word get_fs_d_f24
+ .word get_fs_d_f26
+ .word get_fs_d_f28
+ .word get_fs_d_f30
+ .text
+
+get_fs_d_f0:
+ mfc1 t3, $f0
+ mfc1 t0, $f1
+ b get_fs_d_done
+get_fs_d_f2:
+ mfc1 t3, $f2
+ mfc1 t0, $f3
+ b get_fs_d_done
+get_fs_d_f4:
+ mfc1 t3, $f4
+ mfc1 t0, $f5
+ b get_fs_d_done
+get_fs_d_f6:
+ mfc1 t3, $f6
+ mfc1 t0, $f7
+ b get_fs_d_done
+get_fs_d_f8:
+ mfc1 t3, $f8
+ mfc1 t0, $f9
+ b get_fs_d_done
+get_fs_d_f10:
+ mfc1 t3, $f10
+ mfc1 t0, $f11
+ b get_fs_d_done
+get_fs_d_f12:
+ mfc1 t3, $f12
+ mfc1 t0, $f13
+ b get_fs_d_done
+get_fs_d_f14:
+ mfc1 t3, $f14
+ mfc1 t0, $f15
+ b get_fs_d_done
+get_fs_d_f16:
+ mfc1 t3, $f16
+ mfc1 t0, $f17
+ b get_fs_d_done
+get_fs_d_f18:
+ mfc1 t3, $f18
+ mfc1 t0, $f19
+ b get_fs_d_done
+get_fs_d_f20:
+ mfc1 t3, $f20
+ mfc1 t0, $f21
+ b get_fs_d_done
+get_fs_d_f22:
+ mfc1 t3, $f22
+ mfc1 t0, $f23
+ b get_fs_d_done
+get_fs_d_f24:
+ mfc1 t3, $f24
+ mfc1 t0, $f25
+ b get_fs_d_done
+get_fs_d_f26:
+ mfc1 t3, $f26
+ mfc1 t0, $f27
+ b get_fs_d_done
+get_fs_d_f28:
+ mfc1 t3, $f28
+ mfc1 t0, $f29
+ b get_fs_d_done
+get_fs_d_f30:
+ mfc1 t3, $f30
+ mfc1 t0, $f31
+get_fs_d_done:
+ srl t1, t0, 20 # get exponent
+ and t1, t1, 0x7FF
+ and t2, t0, 0xFFFFF # get fraction
+ srl t0, t0, 31 # get sign
+ bne t1, DEXP_INF, 1f # is it a signaling NAN?
+ and v0, t2, DSIGNAL_NAN
+ bne v0, zero, invalid_d
+1:
+ j ra
+END(get_ft_fs_d)
+
+/*----------------------------------------------------------------------------
+ * get_cmp_s --
+ *
+ * Read (single precision) the FS register (bits 15-11) and
+ * the FT register (bits 20-16) and break up into fields.
+ * This is an internal routine used by MipsEmulateFP only.
+ *
+ * Results:
+ * t0 contains the sign
+ * t1 contains the (biased) exponent
+ * t2 contains the fraction
+ * ta0 contains the sign
+ * ta1 contains the (biased) exponent
+ * ta2 contains the fraction
+ *
+ *----------------------------------------------------------------------------
+ */
+LEAF(get_cmp_s)
+ srl a3, a0, 12 - 2 # get FS field (even regs only)
+ and a3, a3, 0xF << 2 # mask FS field
+ lw a3, cmp_fs_s_tbl(a3) # switch on register number
+ j a3
+
+ .rdata
+cmp_fs_s_tbl:
+ .word cmp_fs_s_f0
+ .word cmp_fs_s_f2
+ .word cmp_fs_s_f4
+ .word cmp_fs_s_f6
+ .word cmp_fs_s_f8
+ .word cmp_fs_s_f10
+ .word cmp_fs_s_f12
+ .word cmp_fs_s_f14
+ .word cmp_fs_s_f16
+ .word cmp_fs_s_f18
+ .word cmp_fs_s_f20
+ .word cmp_fs_s_f22
+ .word cmp_fs_s_f24
+ .word cmp_fs_s_f26
+ .word cmp_fs_s_f28
+ .word cmp_fs_s_f30
+ .text
+
+cmp_fs_s_f0:
+ mfc1 t0, $f0
+ b cmp_fs_s_done
+cmp_fs_s_f2:
+ mfc1 t0, $f2
+ b cmp_fs_s_done
+cmp_fs_s_f4:
+ mfc1 t0, $f4
+ b cmp_fs_s_done
+cmp_fs_s_f6:
+ mfc1 t0, $f6
+ b cmp_fs_s_done
+cmp_fs_s_f8:
+ mfc1 t0, $f8
+ b cmp_fs_s_done
+cmp_fs_s_f10:
+ mfc1 t0, $f10
+ b cmp_fs_s_done
+cmp_fs_s_f12:
+ mfc1 t0, $f12
+ b cmp_fs_s_done
+cmp_fs_s_f14:
+ mfc1 t0, $f14
+ b cmp_fs_s_done
+cmp_fs_s_f16:
+ mfc1 t0, $f16
+ b cmp_fs_s_done
+cmp_fs_s_f18:
+ mfc1 t0, $f18
+ b cmp_fs_s_done
+cmp_fs_s_f20:
+ mfc1 t0, $f20
+ b cmp_fs_s_done
+cmp_fs_s_f22:
+ mfc1 t0, $f22
+ b cmp_fs_s_done
+cmp_fs_s_f24:
+ mfc1 t0, $f24
+ b cmp_fs_s_done
+cmp_fs_s_f26:
+ mfc1 t0, $f26
+ b cmp_fs_s_done
+cmp_fs_s_f28:
+ mfc1 t0, $f28
+ b cmp_fs_s_done
+cmp_fs_s_f30:
+ mfc1 t0, $f30
+cmp_fs_s_done:
+ srl t1, t0, 23 # get exponent
+ and t1, t1, 0xFF
+ and t2, t0, 0x7FFFFF # get fraction
+ srl t0, t0, 31 # get sign
+
+ srl a3, a0, 17 - 2 # get FT field (even regs only)
+ and a3, a3, 0xF << 2 # mask FT field
+ lw a3, cmp_ft_s_tbl(a3) # switch on register number
+ j a3
+
+ .rdata
+cmp_ft_s_tbl:
+ .word cmp_ft_s_f0
+ .word cmp_ft_s_f2
+ .word cmp_ft_s_f4
+ .word cmp_ft_s_f6
+ .word cmp_ft_s_f8
+ .word cmp_ft_s_f10
+ .word cmp_ft_s_f12
+ .word cmp_ft_s_f14
+ .word cmp_ft_s_f16
+ .word cmp_ft_s_f18
+ .word cmp_ft_s_f20
+ .word cmp_ft_s_f22
+ .word cmp_ft_s_f24
+ .word cmp_ft_s_f26
+ .word cmp_ft_s_f28
+ .word cmp_ft_s_f30
+ .text
+
+cmp_ft_s_f0:
+ mfc1 ta0, $f0
+ b cmp_ft_s_done
+cmp_ft_s_f2:
+ mfc1 ta0, $f2
+ b cmp_ft_s_done
+cmp_ft_s_f4:
+ mfc1 ta0, $f4
+ b cmp_ft_s_done
+cmp_ft_s_f6:
+ mfc1 ta0, $f6
+ b cmp_ft_s_done
+cmp_ft_s_f8:
+ mfc1 ta0, $f8
+ b cmp_ft_s_done
+cmp_ft_s_f10:
+ mfc1 ta0, $f10
+ b cmp_ft_s_done
+cmp_ft_s_f12:
+ mfc1 ta0, $f12
+ b cmp_ft_s_done
+cmp_ft_s_f14:
+ mfc1 ta0, $f14
+ b cmp_ft_s_done
+cmp_ft_s_f16:
+ mfc1 ta0, $f16
+ b cmp_ft_s_done
+cmp_ft_s_f18:
+ mfc1 ta0, $f18
+ b cmp_ft_s_done
+cmp_ft_s_f20:
+ mfc1 ta0, $f20
+ b cmp_ft_s_done
+cmp_ft_s_f22:
+ mfc1 ta0, $f22
+ b cmp_ft_s_done
+cmp_ft_s_f24:
+ mfc1 ta0, $f24
+ b cmp_ft_s_done
+cmp_ft_s_f26:
+ mfc1 ta0, $f26
+ b cmp_ft_s_done
+cmp_ft_s_f28:
+ mfc1 ta0, $f28
+ b cmp_ft_s_done
+cmp_ft_s_f30:
+ mfc1 ta0, $f30
+cmp_ft_s_done:
+ srl ta1, ta0, 23 # get exponent
+ and ta1, ta1, 0xFF
+ and ta2, ta0, 0x7FFFFF # get fraction
+ srl ta0, ta0, 31 # get sign
+ j ra
+END(get_cmp_s)
+
+/*----------------------------------------------------------------------------
+ * get_cmp_d --
+ *
+ * Read (double precision) the FS register (bits 15-11) and
+ * the FT register (bits 20-16) and break up into fields.
+ * This is an internal routine used by MipsEmulateFP only.
+ *
+ * Results:
+ * t0 contains the sign
+ * t1 contains the (biased) exponent
+ * t2 contains the fraction
+ * t3 contains the remaining fraction
+ * ta0 contains the sign
+ * ta1 contains the (biased) exponent
+ * ta2 contains the fraction
+ * ta3 contains the remaining fraction
+ *
+ *----------------------------------------------------------------------------
+ */
+LEAF(get_cmp_d)
+ srl a3, a0, 12 - 2 # get FS field (even regs only)
+ and a3, a3, 0xF << 2 # mask FS field
+ lw a3, cmp_fs_d_tbl(a3) # switch on register number
+ j a3
+
+ .rdata
+cmp_fs_d_tbl:
+ .word cmp_fs_d_f0
+ .word cmp_fs_d_f2
+ .word cmp_fs_d_f4
+ .word cmp_fs_d_f6
+ .word cmp_fs_d_f8
+ .word cmp_fs_d_f10
+ .word cmp_fs_d_f12
+ .word cmp_fs_d_f14
+ .word cmp_fs_d_f16
+ .word cmp_fs_d_f18
+ .word cmp_fs_d_f20
+ .word cmp_fs_d_f22
+ .word cmp_fs_d_f24
+ .word cmp_fs_d_f26
+ .word cmp_fs_d_f28
+ .word cmp_fs_d_f30
+ .text
+
+cmp_fs_d_f0:
+ mfc1 t3, $f0
+ mfc1 t0, $f1
+ b cmp_fs_d_done
+cmp_fs_d_f2:
+ mfc1 t3, $f2
+ mfc1 t0, $f3
+ b cmp_fs_d_done
+cmp_fs_d_f4:
+ mfc1 t3, $f4
+ mfc1 t0, $f5
+ b cmp_fs_d_done
+cmp_fs_d_f6:
+ mfc1 t3, $f6
+ mfc1 t0, $f7
+ b cmp_fs_d_done
+cmp_fs_d_f8:
+ mfc1 t3, $f8
+ mfc1 t0, $f9
+ b cmp_fs_d_done
+cmp_fs_d_f10:
+ mfc1 t3, $f10
+ mfc1 t0, $f11
+ b cmp_fs_d_done
+cmp_fs_d_f12:
+ mfc1 t3, $f12
+ mfc1 t0, $f13
+ b cmp_fs_d_done
+cmp_fs_d_f14:
+ mfc1 t3, $f14
+ mfc1 t0, $f15
+ b cmp_fs_d_done
+cmp_fs_d_f16:
+ mfc1 t3, $f16
+ mfc1 t0, $f17
+ b cmp_fs_d_done
+cmp_fs_d_f18:
+ mfc1 t3, $f18
+ mfc1 t0, $f19
+ b cmp_fs_d_done
+cmp_fs_d_f20:
+ mfc1 t3, $f20
+ mfc1 t0, $f21
+ b cmp_fs_d_done
+cmp_fs_d_f22:
+ mfc1 t3, $f22
+ mfc1 t0, $f23
+ b cmp_fs_d_done
+cmp_fs_d_f24:
+ mfc1 t3, $f24
+ mfc1 t0, $f25
+ b cmp_fs_d_done
+cmp_fs_d_f26:
+ mfc1 t3, $f26
+ mfc1 t0, $f27
+ b cmp_fs_d_done
+cmp_fs_d_f28:
+ mfc1 t3, $f28
+ mfc1 t0, $f29
+ b cmp_fs_d_done
+cmp_fs_d_f30:
+ mfc1 t3, $f30
+ mfc1 t0, $f31
+cmp_fs_d_done:
+ srl t1, t0, 20 # get exponent
+ and t1, t1, 0x7FF
+ and t2, t0, 0xFFFFF # get fraction
+ srl t0, t0, 31 # get sign
+
+ srl a3, a0, 17 - 2 # get FT field (even regs only)
+ and a3, a3, 0xF << 2 # mask FT field
+ lw a3, cmp_ft_d_tbl(a3) # switch on register number
+ j a3
+
+ .rdata
+cmp_ft_d_tbl:
+ .word cmp_ft_d_f0
+ .word cmp_ft_d_f2
+ .word cmp_ft_d_f4
+ .word cmp_ft_d_f6
+ .word cmp_ft_d_f8
+ .word cmp_ft_d_f10
+ .word cmp_ft_d_f12
+ .word cmp_ft_d_f14
+ .word cmp_ft_d_f16
+ .word cmp_ft_d_f18
+ .word cmp_ft_d_f20
+ .word cmp_ft_d_f22
+ .word cmp_ft_d_f24
+ .word cmp_ft_d_f26
+ .word cmp_ft_d_f28
+ .word cmp_ft_d_f30
+ .text
+
+cmp_ft_d_f0:
+ mfc1 ta3, $f0
+ mfc1 ta0, $f1
+ b cmp_ft_d_done
+cmp_ft_d_f2:
+ mfc1 ta3, $f2
+ mfc1 ta0, $f3
+ b cmp_ft_d_done
+cmp_ft_d_f4:
+ mfc1 ta3, $f4
+ mfc1 ta0, $f5
+ b cmp_ft_d_done
+cmp_ft_d_f6:
+ mfc1 ta3, $f6
+ mfc1 ta0, $f7
+ b cmp_ft_d_done
+cmp_ft_d_f8:
+ mfc1 ta3, $f8
+ mfc1 ta0, $f9
+ b cmp_ft_d_done
+cmp_ft_d_f10:
+ mfc1 ta3, $f10
+ mfc1 ta0, $f11
+ b cmp_ft_d_done
+cmp_ft_d_f12:
+ mfc1 ta3, $f12
+ mfc1 ta0, $f13
+ b cmp_ft_d_done
+cmp_ft_d_f14:
+ mfc1 ta3, $f14
+ mfc1 ta0, $f15
+ b cmp_ft_d_done
+cmp_ft_d_f16:
+ mfc1 ta3, $f16
+ mfc1 ta0, $f17
+ b cmp_ft_d_done
+cmp_ft_d_f18:
+ mfc1 ta3, $f18
+ mfc1 ta0, $f19
+ b cmp_ft_d_done
+cmp_ft_d_f20:
+ mfc1 ta3, $f20
+ mfc1 ta0, $f21
+ b cmp_ft_d_done
+cmp_ft_d_f22:
+ mfc1 ta3, $f22
+ mfc1 ta0, $f23
+ b cmp_ft_d_done
+cmp_ft_d_f24:
+ mfc1 ta3, $f24
+ mfc1 ta0, $f25
+ b cmp_ft_d_done
+cmp_ft_d_f26:
+ mfc1 ta3, $f26
+ mfc1 ta0, $f27
+ b cmp_ft_d_done
+cmp_ft_d_f28:
+ mfc1 ta3, $f28
+ mfc1 ta0, $f29
+ b cmp_ft_d_done
+cmp_ft_d_f30:
+ mfc1 ta3, $f30
+ mfc1 ta0, $f31
+cmp_ft_d_done:
+ srl ta1, ta0, 20 # get exponent
+ and ta1, ta1, 0x7FF
+ and ta2, ta0, 0xFFFFF # get fraction
+ srl ta0, ta0, 31 # get sign
+ j ra
+END(get_cmp_d)
+
+/*----------------------------------------------------------------------------
+ * set_fd_s --
+ *
+ * Write (single precision) the FD register (bits 10-6).
+ * This is an internal routine used by MipsEmulateFP only.
+ *
+ * Arguments:
+ * a0 contains the FP instruction
+ * t0 contains the sign
+ * t1 contains the (biased) exponent
+ * t2 contains the fraction
+ *
+ * set_fd_word --
+ *
+ * Write (integer) the FD register (bits 10-6).
+ * This is an internal routine used by MipsEmulateFP only.
+ *
+ * Arguments:
+ * a0 contains the FP instruction
+ * t2 contains the integer
+ *
+ *----------------------------------------------------------------------------
+ */
+LEAF(set_fd_s)
+ sll t0, t0, 31 # position sign
+ sll t1, t1, 23 # position exponent
+ or t2, t2, t0
+ or t2, t2, t1
+ALEAF(set_fd_word)
+ srl a3, a0, 7 - 2 # get FD field (even regs only)
+ and a3, a3, 0xF << 2 # mask FT field
+ lw a3, set_fd_s_tbl(a3) # switch on register number
+ j a3
+
+ .rdata
+set_fd_s_tbl:
+ .word set_fd_s_f0
+ .word set_fd_s_f2
+ .word set_fd_s_f4
+ .word set_fd_s_f6
+ .word set_fd_s_f8
+ .word set_fd_s_f10
+ .word set_fd_s_f12
+ .word set_fd_s_f14
+ .word set_fd_s_f16
+ .word set_fd_s_f18
+ .word set_fd_s_f20
+ .word set_fd_s_f22
+ .word set_fd_s_f24
+ .word set_fd_s_f26
+ .word set_fd_s_f28
+ .word set_fd_s_f30
+ .text
+
+set_fd_s_f0:
+ mtc1 t2, $f0
+ j ra
+set_fd_s_f2:
+ mtc1 t2, $f2
+ j ra
+set_fd_s_f4:
+ mtc1 t2, $f4
+ j ra
+set_fd_s_f6:
+ mtc1 t2, $f6
+ j ra
+set_fd_s_f8:
+ mtc1 t2, $f8
+ j ra
+set_fd_s_f10:
+ mtc1 t2, $f10
+ j ra
+set_fd_s_f12:
+ mtc1 t2, $f12
+ j ra
+set_fd_s_f14:
+ mtc1 t2, $f14
+ j ra
+set_fd_s_f16:
+ mtc1 t2, $f16
+ j ra
+set_fd_s_f18:
+ mtc1 t2, $f18
+ j ra
+set_fd_s_f20:
+ mtc1 t2, $f20
+ j ra
+set_fd_s_f22:
+ mtc1 t2, $f22
+ j ra
+set_fd_s_f24:
+ mtc1 t2, $f24
+ j ra
+set_fd_s_f26:
+ mtc1 t2, $f26
+ j ra
+set_fd_s_f28:
+ mtc1 t2, $f28
+ j ra
+set_fd_s_f30:
+ mtc1 t2, $f30
+ j ra
+END(set_fd_s)
+
+/*----------------------------------------------------------------------------
+ * set_fd_d --
+ *
+ * Write (double precision) the FT register (bits 10-6).
+ * This is an internal routine used by MipsEmulateFP only.
+ *
+ * Arguments:
+ * a0 contains the FP instruction
+ * t0 contains the sign
+ * t1 contains the (biased) exponent
+ * t2 contains the fraction
+ * t3 contains the remaining fraction
+ *
+ *----------------------------------------------------------------------------
+ */
+LEAF(set_fd_d)
+ sll t0, t0, 31 # set sign
+ sll t1, t1, 20 # set exponent
+ or t0, t0, t1
+ or t0, t0, t2 # set fraction
+ srl a3, a0, 7 - 2 # get FD field (even regs only)
+ and a3, a3, 0xF << 2 # mask FD field
+ lw a3, set_fd_d_tbl(a3) # switch on register number
+ j a3
+
+ .rdata
+set_fd_d_tbl:
+ .word set_fd_d_f0
+ .word set_fd_d_f2
+ .word set_fd_d_f4
+ .word set_fd_d_f6
+ .word set_fd_d_f8
+ .word set_fd_d_f10
+ .word set_fd_d_f12
+ .word set_fd_d_f14
+ .word set_fd_d_f16
+ .word set_fd_d_f18
+ .word set_fd_d_f20
+ .word set_fd_d_f22
+ .word set_fd_d_f24
+ .word set_fd_d_f26
+ .word set_fd_d_f28
+ .word set_fd_d_f30
+ .text
+
+set_fd_d_f0:
+ mtc1 t3, $f0
+ mtc1 t0, $f1
+ j ra
+set_fd_d_f2:
+ mtc1 t3, $f2
+ mtc1 t0, $f3
+ j ra
+set_fd_d_f4:
+ mtc1 t3, $f4
+ mtc1 t0, $f5
+ j ra
+set_fd_d_f6:
+ mtc1 t3, $f6
+ mtc1 t0, $f7
+ j ra
+set_fd_d_f8:
+ mtc1 t3, $f8
+ mtc1 t0, $f9
+ j ra
+set_fd_d_f10:
+ mtc1 t3, $f10
+ mtc1 t0, $f11
+ j ra
+set_fd_d_f12:
+ mtc1 t3, $f12
+ mtc1 t0, $f13
+ j ra
+set_fd_d_f14:
+ mtc1 t3, $f14
+ mtc1 t0, $f15
+ j ra
+set_fd_d_f16:
+ mtc1 t3, $f16
+ mtc1 t0, $f17
+ j ra
+set_fd_d_f18:
+ mtc1 t3, $f18
+ mtc1 t0, $f19
+ j ra
+set_fd_d_f20:
+ mtc1 t3, $f20
+ mtc1 t0, $f21
+ j ra
+set_fd_d_f22:
+ mtc1 t3, $f22
+ mtc1 t0, $f23
+ j ra
+set_fd_d_f24:
+ mtc1 t3, $f24
+ mtc1 t0, $f25
+ j ra
+set_fd_d_f26:
+ mtc1 t3, $f26
+ mtc1 t0, $f27
+ j ra
+set_fd_d_f28:
+ mtc1 t3, $f28
+ mtc1 t0, $f29
+ j ra
+set_fd_d_f30:
+ mtc1 t3, $f30
+ mtc1 t0, $f31
+ j ra
+END(set_fd_d)
+
+/*----------------------------------------------------------------------------
+ * renorm_fs_s --
+ *
+ * Results:
+ * t1 unbiased exponent
+ * t2 normalized fraction
+ *
+ *----------------------------------------------------------------------------
+ */
+LEAF(renorm_fs_s)
+/*
+ * Find out how many leading zero bits are in t2 and put in t9.
+ */
+ move v0, t2
+ move t9, zero
+ srl v1, v0, 16
+ bne v1, zero, 1f
+ addu t9, 16
+ sll v0, 16
+1:
+ srl v1, v0, 24
+ bne v1, zero, 1f
+ addu t9, 8
+ sll v0, 8
+1:
+ srl v1, v0, 28
+ bne v1, zero, 1f
+ addu t9, 4
+ sll v0, 4
+1:
+ srl v1, v0, 30
+ bne v1, zero, 1f
+ addu t9, 2
+ sll v0, 2
+1:
+ srl v1, v0, 31
+ bne v1, zero, 1f
+ addu t9, 1
+/*
+ * Now shift t2 the correct number of bits.
+ */
+1:
+ subu t9, t9, SLEAD_ZEROS # dont count normal leading zeros
+ li t1, SEXP_MIN
+ subu t1, t1, t9 # adjust exponent
+ sll t2, t2, t9
+ j ra
+END(renorm_fs_s)
+
+/*----------------------------------------------------------------------------
+ * renorm_fs_d --
+ *
+ * Results:
+ * t1 unbiased exponent
+ * t2,t3 normalized fraction
+ *
+ *----------------------------------------------------------------------------
+ */
+LEAF(renorm_fs_d)
+/*
+ * Find out how many leading zero bits are in t2,t3 and put in t9.
+ */
+ move v0, t2
+ move t9, zero
+ bne t2, zero, 1f
+ move v0, t3
+ addu t9, 32
+1:
+ srl v1, v0, 16
+ bne v1, zero, 1f
+ addu t9, 16
+ sll v0, 16
+1:
+ srl v1, v0, 24
+ bne v1, zero, 1f
+ addu t9, 8
+ sll v0, 8
+1:
+ srl v1, v0, 28
+ bne v1, zero, 1f
+ addu t9, 4
+ sll v0, 4
+1:
+ srl v1, v0, 30
+ bne v1, zero, 1f
+ addu t9, 2
+ sll v0, 2
+1:
+ srl v1, v0, 31
+ bne v1, zero, 1f
+ addu t9, 1
+/*
+ * Now shift t2,t3 the correct number of bits.
+ */
+1:
+ subu t9, t9, DLEAD_ZEROS # dont count normal leading zeros
+ li t1, DEXP_MIN
+ subu t1, t1, t9 # adjust exponent
+ li v0, 32
+ blt t9, v0, 1f
+ subu t9, t9, v0 # shift fraction left >= 32 bits
+ sll t2, t3, t9
+ move t3, zero
+ j ra
+1:
+ subu v0, v0, t9 # shift fraction left < 32 bits
+ sll t2, t2, t9
+ srl v1, t3, v0
+ or t2, t2, v1
+ sll t3, t3, t9
+ j ra
+END(renorm_fs_d)
+
+/*----------------------------------------------------------------------------
+ * renorm_ft_s --
+ *
+ * Results:
+ * ta1 unbiased exponent
+ * ta2 normalized fraction
+ *
+ *----------------------------------------------------------------------------
+ */
+LEAF(renorm_ft_s)
+/*
+ * Find out how many leading zero bits are in ta2 and put in t9.
+ */
+ move v0, ta2
+ move t9, zero
+ srl v1, v0, 16
+ bne v1, zero, 1f
+ addu t9, 16
+ sll v0, 16
+1:
+ srl v1, v0, 24
+ bne v1, zero, 1f
+ addu t9, 8
+ sll v0, 8
+1:
+ srl v1, v0, 28
+ bne v1, zero, 1f
+ addu t9, 4
+ sll v0, 4
+1:
+ srl v1, v0, 30
+ bne v1, zero, 1f
+ addu t9, 2
+ sll v0, 2
+1:
+ srl v1, v0, 31
+ bne v1, zero, 1f
+ addu t9, 1
+/*
+ * Now shift ta2 the correct number of bits.
+ */
+1:
+ subu t9, t9, SLEAD_ZEROS # dont count normal leading zeros
+ li ta1, SEXP_MIN
+ subu ta1, ta1, t9 # adjust exponent
+ sll ta2, ta2, t9
+ j ra
+END(renorm_ft_s)
+
+/*----------------------------------------------------------------------------
+ * renorm_ft_d --
+ *
+ * Results:
+ * ta1 unbiased exponent
+ * ta2,ta3 normalized fraction
+ *
+ *----------------------------------------------------------------------------
+ */
+LEAF(renorm_ft_d)
+/*
+ * Find out how many leading zero bits are in ta2,ta3 and put in t9.
+ */
+ move v0, ta2
+ move t9, zero
+ bne ta2, zero, 1f
+ move v0, ta3
+ addu t9, 32
+1:
+ srl v1, v0, 16
+ bne v1, zero, 1f
+ addu t9, 16
+ sll v0, 16
+1:
+ srl v1, v0, 24
+ bne v1, zero, 1f
+ addu t9, 8
+ sll v0, 8
+1:
+ srl v1, v0, 28
+ bne v1, zero, 1f
+ addu t9, 4
+ sll v0, 4
+1:
+ srl v1, v0, 30
+ bne v1, zero, 1f
+ addu t9, 2
+ sll v0, 2
+1:
+ srl v1, v0, 31
+ bne v1, zero, 1f
+ addu t9, 1
+/*
+ * Now shift ta2,ta3 the correct number of bits.
+ */
+1:
+ subu t9, t9, DLEAD_ZEROS # dont count normal leading zeros
+ li ta1, DEXP_MIN
+ subu ta1, ta1, t9 # adjust exponent
+ li v0, 32
+ blt t9, v0, 1f
+ subu t9, t9, v0 # shift fraction left >= 32 bits
+ sll ta2, ta3, t9
+ move ta3, zero
+ j ra
+1:
+ subu v0, v0, t9 # shift fraction left < 32 bits
+ sll ta2, ta2, t9
+ srl v1, ta3, v0
+ or ta2, ta2, v1
+ sll ta3, ta3, t9
+ j ra
+END(renorm_ft_d)
Property changes on: trunk/sys/mips/mips/fp.S
___________________________________________________________________
Added: svn:eol-style
## -0,0 +1 ##
+native
\ No newline at end of property
Added: svn:keywords
## -0,0 +1 ##
+MidnightBSD=%H
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+text/plain
\ No newline at end of property
Added: trunk/sys/mips/mips/freebsd32_machdep.c
===================================================================
--- trunk/sys/mips/mips/freebsd32_machdep.c (rev 0)
+++ trunk/sys/mips/mips/freebsd32_machdep.c 2018-05-26 21:55:02 UTC (rev 9987)
@@ -0,0 +1,493 @@
+/* $MidnightBSD$ */
+/*-
+ * Copyright (c) 2012 Juli Mallett <jmallett at FreeBSD.org>
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ * $FreeBSD: stable/10/sys/mips/mips/freebsd32_machdep.c 294136 2016-01-16 07:56:49Z dchagin $
+ */
+
+/*
+ * Based on nwhitehorn's COMPAT_FREEBSD32 support code for PowerPC64.
+ */
+
+#include "opt_compat.h"
+
+#define __ELF_WORD_SIZE 32
+
+#include <sys/types.h>
+#include <sys/param.h>
+#include <sys/kernel.h>
+#include <sys/systm.h>
+#include <sys/sysent.h>
+#include <sys/exec.h>
+#include <sys/imgact.h>
+#include <sys/malloc.h>
+#include <sys/proc.h>
+#include <sys/namei.h>
+#include <sys/fcntl.h>
+#include <sys/sysent.h>
+#include <sys/imgact_elf.h>
+#include <sys/syscall.h>
+#include <sys/syscallsubr.h>
+#include <sys/sysproto.h>
+#include <sys/signalvar.h>
+#include <sys/vnode.h>
+#include <sys/linker.h>
+
+#include <vm/vm.h>
+#include <vm/vm_param.h>
+
+#include <machine/md_var.h>
+#include <machine/reg.h>
+#include <machine/sigframe.h>
+#include <machine/sysarch.h>
+
+#include <compat/freebsd32/freebsd32_signal.h>
+#include <compat/freebsd32/freebsd32_util.h>
+#include <compat/freebsd32/freebsd32_proto.h>
+
+static void freebsd32_exec_setregs(struct thread *, struct image_params *, u_long);
+static int get_mcontext32(struct thread *, mcontext32_t *, int);
+static int set_mcontext32(struct thread *, mcontext32_t *);
+static void freebsd32_sendsig(sig_t, ksiginfo_t *, sigset_t *);
+
+extern const char *freebsd32_syscallnames[];
+
+struct sysentvec elf32_freebsd_sysvec = {
+ .sv_size = SYS_MAXSYSCALL,
+ .sv_table = freebsd32_sysent,
+ .sv_mask = 0,
+ .sv_sigsize = 0,
+ .sv_sigtbl = NULL,
+ .sv_errsize = 0,
+ .sv_errtbl = NULL,
+ .sv_transtrap = NULL,
+ .sv_fixup = __elfN(freebsd_fixup),
+ .sv_sendsig = freebsd32_sendsig,
+ .sv_sigcode = sigcode32,
+ .sv_szsigcode = &szsigcode32,
+ .sv_prepsyscall = NULL,
+ .sv_name = "FreeBSD ELF32",
+ .sv_coredump = __elfN(coredump),
+ .sv_imgact_try = NULL,
+ .sv_minsigstksz = MINSIGSTKSZ,
+ .sv_pagesize = PAGE_SIZE,
+ .sv_minuser = VM_MIN_ADDRESS,
+ .sv_maxuser = ((vm_offset_t)0x80000000),
+ .sv_usrstack = FREEBSD32_USRSTACK,
+ .sv_psstrings = FREEBSD32_PS_STRINGS,
+ .sv_stackprot = VM_PROT_ALL,
+ .sv_copyout_strings = freebsd32_copyout_strings,
+ .sv_setregs = freebsd32_exec_setregs,
+ .sv_fixlimit = NULL,
+ .sv_maxssiz = NULL,
+ .sv_flags = SV_ABI_FREEBSD | SV_ILP32,
+ .sv_set_syscall_retval = cpu_set_syscall_retval,
+ .sv_fetch_syscall_args = cpu_fetch_syscall_args,
+ .sv_syscallnames = freebsd32_syscallnames,
+ .sv_schedtail = NULL,
+ .sv_thread_detach = NULL,
+ .sv_trap = NULL,
+};
+INIT_SYSENTVEC(elf32_sysvec, &elf32_freebsd_sysvec);
+
+static Elf32_Brandinfo freebsd_brand_info = {
+ .brand = ELFOSABI_FREEBSD,
+ .machine = EM_MIPS,
+ .compat_3_brand = "FreeBSD",
+ .emul_path = NULL,
+ .interp_path = "/libexec/ld-elf.so.1",
+ .sysvec = &elf32_freebsd_sysvec,
+ .interp_newpath = "/libexec/ld-elf32.so.1",
+ .flags = 0
+};
+
+SYSINIT(elf32, SI_SUB_EXEC, SI_ORDER_FIRST,
+ (sysinit_cfunc_t) elf32_insert_brand_entry,
+ &freebsd_brand_info);
+
+static void
+freebsd32_exec_setregs(struct thread *td, struct image_params *imgp, u_long stack)
+{
+ exec_setregs(td, imgp, stack);
+
+ /*
+ * See comment in exec_setregs about running 32-bit binaries with 64-bit
+ * registers.
+ */
+ td->td_frame->sp -= 65536;
+
+ /*
+ * Clear extended address space bit for userland.
+ */
+ td->td_frame->sr &= ~MIPS_SR_UX;
+}
+
+int
+set_regs32(struct thread *td, struct reg32 *regs)
+{
+ struct reg r;
+ unsigned i;
+
+ for (i = 0; i < NUMSAVEREGS; i++)
+ r.r_regs[i] = regs->r_regs[i];
+
+ return (set_regs(td, &r));
+}
+
+int
+fill_regs32(struct thread *td, struct reg32 *regs)
+{
+ struct reg r;
+ unsigned i;
+ int error;
+
+ error = fill_regs(td, &r);
+ if (error != 0)
+ return (error);
+
+ for (i = 0; i < NUMSAVEREGS; i++)
+ regs->r_regs[i] = r.r_regs[i];
+
+ return (0);
+}
+
+int
+set_fpregs32(struct thread *td, struct fpreg32 *fpregs)
+{
+ struct fpreg fp;
+ unsigned i;
+
+ for (i = 0; i < NUMFPREGS; i++)
+ fp.r_regs[i] = fpregs->r_regs[i];
+
+ return (set_fpregs(td, &fp));
+}
+
+int
+fill_fpregs32(struct thread *td, struct fpreg32 *fpregs)
+{
+ struct fpreg fp;
+ unsigned i;
+ int error;
+
+ error = fill_fpregs(td, &fp);
+ if (error != 0)
+ return (error);
+
+ for (i = 0; i < NUMFPREGS; i++)
+ fpregs->r_regs[i] = fp.r_regs[i];
+
+ return (0);
+}
+
+static int
+get_mcontext32(struct thread *td, mcontext32_t *mcp, int flags)
+{
+ mcontext_t mcp64;
+ unsigned i;
+ int error;
+
+ error = get_mcontext(td, &mcp64, flags);
+ if (error != 0)
+ return (error);
+
+ mcp->mc_onstack = mcp64.mc_onstack;
+ mcp->mc_pc = mcp64.mc_pc;
+ for (i = 0; i < 32; i++)
+ mcp->mc_regs[i] = mcp64.mc_regs[i];
+ mcp->sr = mcp64.sr;
+ mcp->mullo = mcp64.mullo;
+ mcp->mulhi = mcp64.mulhi;
+ mcp->mc_fpused = mcp64.mc_fpused;
+ for (i = 0; i < 33; i++)
+ mcp->mc_fpregs[i] = mcp64.mc_fpregs[i];
+ mcp->mc_fpc_eir = mcp64.mc_fpc_eir;
+ mcp->mc_tls = (int32_t)(intptr_t)mcp64.mc_tls;
+
+ return (0);
+}
+
+static int
+set_mcontext32(struct thread *td, mcontext32_t *mcp)
+{
+ mcontext_t mcp64;
+ unsigned i;
+
+ mcp64.mc_onstack = mcp->mc_onstack;
+ mcp64.mc_pc = mcp->mc_pc;
+ for (i = 0; i < 32; i++)
+ mcp64.mc_regs[i] = mcp->mc_regs[i];
+ mcp64.sr = mcp->sr;
+ mcp64.mullo = mcp->mullo;
+ mcp64.mulhi = mcp->mulhi;
+ mcp64.mc_fpused = mcp->mc_fpused;
+ for (i = 0; i < 33; i++)
+ mcp64.mc_fpregs[i] = mcp->mc_fpregs[i];
+ mcp64.mc_fpc_eir = mcp->mc_fpc_eir;
+ mcp64.mc_tls = (void *)(intptr_t)mcp->mc_tls;
+
+ return (set_mcontext(td, &mcp64));
+}
+
+int
+freebsd32_sigreturn(struct thread *td, struct freebsd32_sigreturn_args *uap)
+{
+ ucontext32_t uc;
+ int error;
+
+ CTR2(KTR_SIG, "sigreturn: td=%p ucp=%p", td, uap->sigcntxp);
+
+ if (copyin(uap->sigcntxp, &uc, sizeof(uc)) != 0) {
+ CTR1(KTR_SIG, "sigreturn: efault td=%p", td);
+ return (EFAULT);
+ }
+
+ error = set_mcontext32(td, &uc.uc_mcontext);
+ if (error != 0)
+ return (error);
+
+ kern_sigprocmask(td, SIG_SETMASK, &uc.uc_sigmask, NULL, 0);
+
+#if 0
+ CTR3(KTR_SIG, "sigreturn: return td=%p pc=%#x sp=%#x",
+ td, uc.uc_mcontext.mc_srr0, uc.uc_mcontext.mc_gpr[1]);
+#endif
+
+ return (EJUSTRETURN);
+}
+
+/*
+ * The first two fields of a ucontext_t are the signal mask and the machine
+ * context. The next field is uc_link; we want to avoid destroying the link
+ * when copying out contexts.
+ */
+#define UC32_COPY_SIZE offsetof(ucontext32_t, uc_link)
+
+int
+freebsd32_getcontext(struct thread *td, struct freebsd32_getcontext_args *uap)
+{
+ ucontext32_t uc;
+ int ret;
+
+ if (uap->ucp == NULL)
+ ret = EINVAL;
+ else {
+ get_mcontext32(td, &uc.uc_mcontext, GET_MC_CLEAR_RET);
+ PROC_LOCK(td->td_proc);
+ uc.uc_sigmask = td->td_sigmask;
+ PROC_UNLOCK(td->td_proc);
+ ret = copyout(&uc, uap->ucp, UC32_COPY_SIZE);
+ }
+ return (ret);
+}
+
+int
+freebsd32_setcontext(struct thread *td, struct freebsd32_setcontext_args *uap)
+{
+ ucontext32_t uc;
+ int ret;
+
+ if (uap->ucp == NULL)
+ ret = EINVAL;
+ else {
+ ret = copyin(uap->ucp, &uc, UC32_COPY_SIZE);
+ if (ret == 0) {
+ ret = set_mcontext32(td, &uc.uc_mcontext);
+ if (ret == 0) {
+ kern_sigprocmask(td, SIG_SETMASK,
+ &uc.uc_sigmask, NULL, 0);
+ }
+ }
+ }
+ return (ret == 0 ? EJUSTRETURN : ret);
+}
+
+int
+freebsd32_swapcontext(struct thread *td, struct freebsd32_swapcontext_args *uap)
+{
+ ucontext32_t uc;
+ int ret;
+
+ if (uap->oucp == NULL || uap->ucp == NULL)
+ ret = EINVAL;
+ else {
+ get_mcontext32(td, &uc.uc_mcontext, GET_MC_CLEAR_RET);
+ PROC_LOCK(td->td_proc);
+ uc.uc_sigmask = td->td_sigmask;
+ PROC_UNLOCK(td->td_proc);
+ ret = copyout(&uc, uap->oucp, UC32_COPY_SIZE);
+ if (ret == 0) {
+ ret = copyin(uap->ucp, &uc, UC32_COPY_SIZE);
+ if (ret == 0) {
+ ret = set_mcontext32(td, &uc.uc_mcontext);
+ if (ret == 0) {
+ kern_sigprocmask(td, SIG_SETMASK,
+ &uc.uc_sigmask, NULL, 0);
+ }
+ }
+ }
+ }
+ return (ret == 0 ? EJUSTRETURN : ret);
+}
+
+#define UCONTEXT_MAGIC 0xACEDBADE
+
+/*
+ * Send an interrupt to process.
+ *
+ * Stack is set up to allow sigcode stored
+ * at top to call routine, followed by kcall
+ * to sigreturn routine below. After sigreturn
+ * resets the signal mask, the stack, and the
+ * frame pointer, it returns to the user
+ * specified pc, psl.
+ */
+static void
+freebsd32_sendsig(sig_t catcher, ksiginfo_t *ksi, sigset_t *mask)
+{
+ struct proc *p;
+ struct thread *td;
+ struct fpreg32 fpregs;
+ struct reg32 regs;
+ struct sigacts *psp;
+ struct sigframe32 sf, *sfp;
+ int sig;
+ int oonstack;
+ unsigned i;
+
+ td = curthread;
+ p = td->td_proc;
+ PROC_LOCK_ASSERT(p, MA_OWNED);
+ sig = ksi->ksi_signo;
+ psp = p->p_sigacts;
+ mtx_assert(&psp->ps_mtx, MA_OWNED);
+
+ fill_regs32(td, ®s);
+ oonstack = sigonstack(td->td_frame->sp);
+
+ /* save user context */
+ bzero(&sf, sizeof sf);
+ sf.sf_uc.uc_sigmask = *mask;
+ sf.sf_uc.uc_stack.ss_sp = (int32_t)(intptr_t)td->td_sigstk.ss_sp;
+ sf.sf_uc.uc_stack.ss_size = td->td_sigstk.ss_size;
+ sf.sf_uc.uc_stack.ss_flags = td->td_sigstk.ss_flags;
+ sf.sf_uc.uc_mcontext.mc_onstack = (oonstack) ? 1 : 0;
+ sf.sf_uc.uc_mcontext.mc_pc = regs.r_regs[PC];
+ sf.sf_uc.uc_mcontext.mullo = regs.r_regs[MULLO];
+ sf.sf_uc.uc_mcontext.mulhi = regs.r_regs[MULHI];
+ sf.sf_uc.uc_mcontext.mc_tls = (int32_t)(intptr_t)td->td_md.md_tls;
+ sf.sf_uc.uc_mcontext.mc_regs[0] = UCONTEXT_MAGIC; /* magic number */
+ for (i = 1; i < 32; i++)
+ sf.sf_uc.uc_mcontext.mc_regs[i] = regs.r_regs[i];
+ sf.sf_uc.uc_mcontext.mc_fpused = td->td_md.md_flags & MDTD_FPUSED;
+ if (sf.sf_uc.uc_mcontext.mc_fpused) {
+ /* if FPU has current state, save it first */
+ if (td == PCPU_GET(fpcurthread))
+ MipsSaveCurFPState(td);
+ fill_fpregs32(td, &fpregs);
+ for (i = 0; i < 33; i++)
+ sf.sf_uc.uc_mcontext.mc_fpregs[i] = fpregs.r_regs[i];
+ }
+
+ /* Allocate and validate space for the signal handler context. */
+ if ((td->td_pflags & TDP_ALTSTACK) != 0 && !oonstack &&
+ SIGISMEMBER(psp->ps_sigonstack, sig)) {
+ sfp = (struct sigframe32 *)((vm_offset_t)(td->td_sigstk.ss_sp +
+ td->td_sigstk.ss_size - sizeof(struct sigframe32))
+ & ~(sizeof(__int64_t) - 1));
+ } else
+ sfp = (struct sigframe32 *)((vm_offset_t)(td->td_frame->sp -
+ sizeof(struct sigframe32)) & ~(sizeof(__int64_t) - 1));
+
+ /* Build the argument list for the signal handler. */
+ td->td_frame->a0 = sig;
+ td->td_frame->a2 = (register_t)(intptr_t)&sfp->sf_uc;
+ if (SIGISMEMBER(psp->ps_siginfo, sig)) {
+ /* Signal handler installed with SA_SIGINFO. */
+ td->td_frame->a1 = (register_t)(intptr_t)&sfp->sf_si;
+ /* sf.sf_ahu.sf_action = (__siginfohandler_t *)catcher; */
+
+ /* fill siginfo structure */
+ sf.sf_si.si_signo = sig;
+ sf.sf_si.si_code = ksi->ksi_code;
+ sf.sf_si.si_addr = td->td_frame->badvaddr;
+ } else {
+ /* Old FreeBSD-style arguments. */
+ td->td_frame->a1 = ksi->ksi_code;
+ td->td_frame->a3 = td->td_frame->badvaddr;
+ /* sf.sf_ahu.sf_handler = catcher; */
+ }
+
+ mtx_unlock(&psp->ps_mtx);
+ PROC_UNLOCK(p);
+
+ /*
+ * Copy the sigframe out to the user's stack.
+ */
+ if (copyout(&sf, sfp, sizeof(struct sigframe32)) != 0) {
+ /*
+ * Something is wrong with the stack pointer.
+ * ...Kill the process.
+ */
+ PROC_LOCK(p);
+ sigexit(td, SIGILL);
+ }
+
+ td->td_frame->pc = (register_t)(intptr_t)catcher;
+ td->td_frame->t9 = (register_t)(intptr_t)catcher;
+ td->td_frame->sp = (register_t)(intptr_t)sfp;
+ /*
+ * Signal trampoline code is at base of user stack.
+ */
+ td->td_frame->ra = (register_t)(intptr_t)FREEBSD32_PS_STRINGS - *(p->p_sysent->sv_szsigcode);
+ PROC_LOCK(p);
+ mtx_lock(&psp->ps_mtx);
+}
+
+int
+freebsd32_sysarch(struct thread *td, struct freebsd32_sysarch_args *uap)
+{
+ int error;
+ int32_t tlsbase;
+
+ switch (uap->op) {
+ case MIPS_SET_TLS:
+ td->td_md.md_tls = (void *)(intptr_t)uap->parms;
+ return (0);
+ case MIPS_GET_TLS:
+ tlsbase = (int32_t)(intptr_t)td->td_md.md_tls;
+ error = copyout(&tlsbase, uap->parms, sizeof(tlsbase));
+ return (error);
+ default:
+ break;
+ }
+ return (EINVAL);
+}
+
+void
+elf32_dump_thread(struct thread *td __unused, void *dst __unused,
+ size_t *off __unused)
+{
+}
Property changes on: trunk/sys/mips/mips/freebsd32_machdep.c
___________________________________________________________________
Added: svn:eol-style
## -0,0 +1 ##
+native
\ No newline at end of property
Added: svn:keywords
## -0,0 +1 ##
+MidnightBSD=%H
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+text/plain
\ No newline at end of property
Added: trunk/sys/mips/mips/gdb_machdep.c
===================================================================
--- trunk/sys/mips/mips/gdb_machdep.c (rev 0)
+++ trunk/sys/mips/mips/gdb_machdep.c 2018-05-26 21:55:02 UTC (rev 9987)
@@ -0,0 +1,190 @@
+/* $MidnightBSD$ */
+/* $NetBSD: kgdb_machdep.c,v 1.11 2005/12/24 22:45:35 perry Exp $ */
+
+/*-
+ * Copyright (c) 2004 Marcel Moolenaar
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHORS ``AS IS'' AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+ * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+ * IN NO EVENT SHALL THE AUTHORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+/*-
+ * Copyright (c) 1997 The NetBSD Foundation, Inc.
+ * All rights reserved.
+ *
+ * This code is derived from software contributed to The NetBSD Foundation
+ * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility,
+ * NASA Ames Research Center.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
+ * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/*
+ * Copyright (c) 1996 Matthias Pfaller.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * 3. All advertising materials mentioning features or use of this software
+ * must display the following acknowledgement:
+ * This product includes software developed by Matthias Pfaller.
+ * 4. The name of the author may not be used to endorse or promote products
+ * derived from this software without specific prior written permission
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+ * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+ * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * JNPR: gdb_machdep.c,v 1.1 2007/08/09 12:25:25 katta
+ * $FreeBSD: stable/10/sys/mips/mips/gdb_machdep.c 263687 2014-03-24 13:48:04Z emaste $
+ */
+
+#include <sys/cdefs.h>
+
+#include <sys/param.h>
+#include <sys/systm.h>
+#include <sys/kdb.h>
+#include <sys/kernel.h>
+#include <sys/signal.h>
+#include <sys/pcpu.h>
+
+#include <machine/gdb_machdep.h>
+#include <machine/pcb.h>
+#include <machine/reg.h>
+#include <machine/trap.h>
+
+#include <gdb/gdb.h>
+
+void *
+gdb_cpu_getreg(int regnum, size_t *regsz)
+{
+
+ *regsz = gdb_cpu_regsz(regnum);
+ if (kdb_thread == curthread) {
+ register_t *zero_ptr = &kdb_frame->zero;
+ return zero_ptr + regnum;
+ }
+
+ switch (regnum) {
+ /*
+ * S0..S7
+ */
+ case 16:
+ case 17:
+ case 18:
+ case 19:
+ case 20:
+ case 21:
+ case 22:
+ case 23:
+ return (&kdb_thrctx->pcb_context[PCB_REG_S0 + regnum - 16]);
+ case 28:
+ return (&kdb_thrctx->pcb_context[PCB_REG_GP]);
+ case 29:
+ return (&kdb_thrctx->pcb_context[PCB_REG_SP]);
+ case 30:
+ return (&kdb_thrctx->pcb_context[PCB_REG_S8]);
+ case 31:
+ return (&kdb_thrctx->pcb_context[PCB_REG_RA]);
+ case 37:
+ return (&kdb_thrctx->pcb_context[PCB_REG_PC]);
+ }
+ return (NULL);
+}
+
+void
+gdb_cpu_setreg(int regnum, void *val)
+{
+ switch (regnum) {
+ case GDB_REG_PC:
+ kdb_thrctx->pcb_context[10] = *(register_t *)val;
+ if (kdb_thread == curthread)
+ kdb_frame->pc = *(register_t *)val;
+ }
+}
+
+int
+gdb_cpu_signal(int entry, int code)
+{
+ switch (entry) {
+ case T_TLB_MOD:
+ case T_TLB_MOD+T_USER:
+ case T_TLB_LD_MISS:
+ case T_TLB_ST_MISS:
+ case T_TLB_LD_MISS+T_USER:
+ case T_TLB_ST_MISS+T_USER:
+ case T_ADDR_ERR_LD: /* misaligned access */
+ case T_ADDR_ERR_ST: /* misaligned access */
+ case T_BUS_ERR_LD_ST: /* BERR asserted to CPU */
+ case T_ADDR_ERR_LD+T_USER: /* misaligned or kseg access */
+ case T_ADDR_ERR_ST+T_USER: /* misaligned or kseg access */
+ case T_BUS_ERR_IFETCH+T_USER: /* BERR asserted to CPU */
+ case T_BUS_ERR_LD_ST+T_USER: /* BERR asserted to CPU */
+ return (SIGSEGV);
+
+ case T_BREAK:
+ case T_BREAK+T_USER:
+ return (SIGTRAP);
+
+ case T_RES_INST+T_USER:
+ case T_COP_UNUSABLE+T_USER:
+ return (SIGILL);
+
+ case T_FPE+T_USER:
+ case T_OVFLOW+T_USER:
+ return (SIGFPE);
+
+ default:
+ return (SIGEMT);
+ }
+}
Property changes on: trunk/sys/mips/mips/gdb_machdep.c
___________________________________________________________________
Added: svn:eol-style
## -0,0 +1 ##
+native
\ No newline at end of property
Added: svn:keywords
## -0,0 +1 ##
+MidnightBSD=%H
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+text/plain
\ No newline at end of property
Added: trunk/sys/mips/mips/genassym.c
===================================================================
--- trunk/sys/mips/mips/genassym.c (rev 0)
+++ trunk/sys/mips/mips/genassym.c 2018-05-26 21:55:02 UTC (rev 9987)
@@ -0,0 +1,171 @@
+/* $MidnightBSD$ */
+/*-
+ * Copyright (c) 1982, 1990 The Regents of the University of California.
+ * All rights reserved.
+ *
+ * This code is derived from software contributed to Berkeley by
+ * William Jolitz.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * 4. Neither the name of the University nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ * from: @(#)genassym.c 5.11 (Berkeley) 5/10/91
+ * from: src/sys/i386/i386/genassym.c,v 1.86.2.1 2000/05/16 06:58:06 dillon
+ * JNPR: genassym.c,v 1.4 2007/08/09 11:23:32 katta
+ */
+
+#include <sys/cdefs.h>
+__FBSDID("$FreeBSD: stable/10/sys/mips/mips/genassym.c 232587 2012-03-06 08:40:21Z jmallett $");
+
+#include <sys/param.h>
+#include <sys/systm.h>
+#include <sys/assym.h>
+#include <machine/pte.h>
+#include <sys/proc.h>
+#include <sys/errno.h>
+#include <sys/lock.h>
+#include <sys/mutex.h>
+#include <sys/socket.h>
+#include <sys/resourcevar.h>
+#include <sys/ucontext.h>
+#include <sys/vmmeter.h>
+#include <vm/vm.h>
+#include <vm/vm_param.h>
+#include <vm/pmap.h>
+#include <vm/vm_map.h>
+#include <machine/cpuregs.h>
+#include <machine/pcb.h>
+#include <machine/sigframe.h>
+#include <machine/proc.h>
+
+#ifdef CPU_CNMIPS
+#include <machine/octeon_cop2.h>
+#endif
+
+#ifndef offsetof
+#define offsetof(t,m) (int)((&((t *)0L)->m))
+#endif
+
+ASSYM(TD_PCB, offsetof(struct thread, td_pcb));
+ASSYM(TD_UPTE, offsetof(struct thread, td_md.md_upte));
+ASSYM(TD_KSTACK, offsetof(struct thread, td_kstack));
+ASSYM(TD_FLAGS, offsetof(struct thread, td_flags));
+ASSYM(TD_LOCK, offsetof(struct thread, td_lock));
+ASSYM(TD_MDFLAGS, offsetof(struct thread, td_md.md_flags));
+
+ASSYM(U_PCB_REGS, offsetof(struct pcb, pcb_regs.zero));
+ASSYM(U_PCB_CONTEXT, offsetof(struct pcb, pcb_context));
+ASSYM(U_PCB_ONFAULT, offsetof(struct pcb, pcb_onfault));
+ASSYM(U_PCB_FPREGS, offsetof(struct pcb, pcb_regs.f0));
+
+ASSYM(PC_CURPCB, offsetof(struct pcpu, pc_curpcb));
+ASSYM(PC_SEGBASE, offsetof(struct pcpu, pc_segbase));
+ASSYM(PC_CURTHREAD, offsetof(struct pcpu, pc_curthread));
+ASSYM(PC_FPCURTHREAD, offsetof(struct pcpu, pc_fpcurthread));
+ASSYM(PC_CPUID, offsetof(struct pcpu, pc_cpuid));
+
+ASSYM(VM_MAX_KERNEL_ADDRESS, VM_MAX_KERNEL_ADDRESS);
+ASSYM(VM_MAXUSER_ADDRESS, VM_MAXUSER_ADDRESS);
+ASSYM(SIGF_UC, offsetof(struct sigframe, sf_uc));
+#ifdef COMPAT_FREEBSD32
+ASSYM(SIGF32_UC, offsetof(struct sigframe32, sf_uc));
+#endif
+ASSYM(SIGFPE, SIGFPE);
+ASSYM(PAGE_SHIFT, PAGE_SHIFT);
+ASSYM(PAGE_SIZE, PAGE_SIZE);
+ASSYM(PDRSHIFT, PDRSHIFT);
+ASSYM(SEGSHIFT, SEGSHIFT);
+ASSYM(TDF_NEEDRESCHED, TDF_NEEDRESCHED);
+ASSYM(TDF_ASTPENDING, TDF_ASTPENDING);
+ASSYM(MAXCOMLEN, MAXCOMLEN);
+ASSYM(MDTD_COP2USED, MDTD_COP2USED);
+
+ASSYM(MIPS_KSEG0_START, MIPS_KSEG0_START);
+ASSYM(MIPS_KSEG1_START, MIPS_KSEG1_START);
+ASSYM(MIPS_KSEG2_START, MIPS_KSEG2_START);
+ASSYM(MIPS_XKSEG_START, MIPS_XKSEG_START);
+
+#ifdef CPU_CNMIPS
+ASSYM(TD_COP2OWNER, offsetof(struct thread, td_md.md_cop2owner));
+ASSYM(TD_COP2, offsetof(struct thread, td_md.md_cop2));
+ASSYM(TD_UCOP2, offsetof(struct thread, td_md.md_ucop2));
+ASSYM(COP2_CRC_IV_OFFSET, offsetof(struct octeon_cop2_state, crc_iv));
+ASSYM(COP2_CRC_LENGTH_OFFSET, offsetof(struct octeon_cop2_state, crc_length));
+ASSYM(COP2_CRC_POLY_OFFSET, offsetof(struct octeon_cop2_state, crc_poly));
+ASSYM(COP2_LLM_DAT0_OFFSET, offsetof(struct octeon_cop2_state, llm_dat));
+ASSYM(COP2_LLM_DAT1_OFFSET, offsetof(struct octeon_cop2_state, llm_dat) + 8);
+ASSYM(COP2_3DES_IV_OFFSET, offsetof(struct octeon_cop2_state, _3des_iv));
+ASSYM(COP2_3DES_KEY0_OFFSET, offsetof(struct octeon_cop2_state, _3des_key));
+ASSYM(COP2_3DES_KEY1_OFFSET, offsetof(struct octeon_cop2_state, _3des_key) + 8);
+ASSYM(COP2_3DES_KEY2_OFFSET, offsetof(struct octeon_cop2_state, _3des_key) + 16);
+ASSYM(COP2_3DES_RESULT_OFFSET, offsetof(struct octeon_cop2_state, _3des_result));
+ASSYM(COP2_AES_INP0_OFFSET, offsetof(struct octeon_cop2_state, aes_inp0));
+ASSYM(COP2_AES_IV0_OFFSET, offsetof(struct octeon_cop2_state, aes_iv));
+ASSYM(COP2_AES_IV1_OFFSET, offsetof(struct octeon_cop2_state, aes_iv) + 8);
+ASSYM(COP2_AES_KEY0_OFFSET, offsetof(struct octeon_cop2_state, aes_key));
+ASSYM(COP2_AES_KEY1_OFFSET, offsetof(struct octeon_cop2_state, aes_key) + 8);
+ASSYM(COP2_AES_KEY2_OFFSET, offsetof(struct octeon_cop2_state, aes_key) + 16);
+ASSYM(COP2_AES_KEY3_OFFSET, offsetof(struct octeon_cop2_state, aes_key) + 24);
+ASSYM(COP2_AES_KEYLEN_OFFSET, offsetof(struct octeon_cop2_state, aes_keylen));
+ASSYM(COP2_AES_RESULT0_OFFSET, offsetof(struct octeon_cop2_state, aes_result));
+ASSYM(COP2_AES_RESULT1_OFFSET, offsetof(struct octeon_cop2_state, aes_result) + 8);
+ASSYM(COP2_HSH_DATW0_OFFSET, offsetof(struct octeon_cop2_state, hsh_datw));
+ASSYM(COP2_HSH_DATW1_OFFSET, offsetof(struct octeon_cop2_state, hsh_datw) + 8);
+ASSYM(COP2_HSH_DATW2_OFFSET, offsetof(struct octeon_cop2_state, hsh_datw) + 16);
+ASSYM(COP2_HSH_DATW3_OFFSET, offsetof(struct octeon_cop2_state, hsh_datw) + 24);
+ASSYM(COP2_HSH_DATW4_OFFSET, offsetof(struct octeon_cop2_state, hsh_datw) + 32);
+ASSYM(COP2_HSH_DATW5_OFFSET, offsetof(struct octeon_cop2_state, hsh_datw) + 40);
+ASSYM(COP2_HSH_DATW6_OFFSET, offsetof(struct octeon_cop2_state, hsh_datw) + 48);
+ASSYM(COP2_HSH_DATW7_OFFSET, offsetof(struct octeon_cop2_state, hsh_datw) + 56);
+ASSYM(COP2_HSH_DATW8_OFFSET, offsetof(struct octeon_cop2_state, hsh_datw) + 64);
+ASSYM(COP2_HSH_DATW9_OFFSET, offsetof(struct octeon_cop2_state, hsh_datw) + 72);
+ASSYM(COP2_HSH_DATW10_OFFSET, offsetof(struct octeon_cop2_state, hsh_datw) + 80);
+ASSYM(COP2_HSH_DATW11_OFFSET, offsetof(struct octeon_cop2_state, hsh_datw) + 88);
+ASSYM(COP2_HSH_DATW12_OFFSET, offsetof(struct octeon_cop2_state, hsh_datw) + 96);
+ASSYM(COP2_HSH_DATW13_OFFSET, offsetof(struct octeon_cop2_state, hsh_datw) + 104);
+ASSYM(COP2_HSH_DATW14_OFFSET, offsetof(struct octeon_cop2_state, hsh_datw) + 112);
+ASSYM(COP2_HSH_IVW0_OFFSET, offsetof(struct octeon_cop2_state, hsh_ivw));
+ASSYM(COP2_HSH_IVW1_OFFSET, offsetof(struct octeon_cop2_state, hsh_ivw) + 8);
+ASSYM(COP2_HSH_IVW2_OFFSET, offsetof(struct octeon_cop2_state, hsh_ivw) + 16);
+ASSYM(COP2_HSH_IVW3_OFFSET, offsetof(struct octeon_cop2_state, hsh_ivw) + 24);
+ASSYM(COP2_HSH_IVW4_OFFSET, offsetof(struct octeon_cop2_state, hsh_ivw) + 32);
+ASSYM(COP2_HSH_IVW5_OFFSET, offsetof(struct octeon_cop2_state, hsh_ivw) + 40);
+ASSYM(COP2_HSH_IVW6_OFFSET, offsetof(struct octeon_cop2_state, hsh_ivw) + 48);
+ASSYM(COP2_HSH_IVW7_OFFSET, offsetof(struct octeon_cop2_state, hsh_ivw) + 56);
+ASSYM(COP2_GFM_MULT0_OFFSET, offsetof(struct octeon_cop2_state, gfm_mult));
+ASSYM(COP2_GFM_MULT1_OFFSET, offsetof(struct octeon_cop2_state, gfm_mult) + 8);
+ASSYM(COP2_GFM_POLY_OFFSET, offsetof(struct octeon_cop2_state, gfm_poly));
+ASSYM(COP2_GFM_RESULT0_OFFSET, offsetof(struct octeon_cop2_state, gfm_result));
+ASSYM(COP2_GFM_RESULT1_OFFSET, offsetof(struct octeon_cop2_state, gfm_result) + 8);
+ASSYM(COP2_HSH_DATW0_PASS1_OFFSET, offsetof(struct octeon_cop2_state, hsh_datw));
+ASSYM(COP2_HSH_DATW1_PASS1_OFFSET, offsetof(struct octeon_cop2_state, hsh_datw) + 8);
+ASSYM(COP2_HSH_DATW2_PASS1_OFFSET, offsetof(struct octeon_cop2_state, hsh_datw) + 16);
+ASSYM(COP2_HSH_DATW3_PASS1_OFFSET, offsetof(struct octeon_cop2_state, hsh_datw) + 24);
+ASSYM(COP2_HSH_DATW4_PASS1_OFFSET, offsetof(struct octeon_cop2_state, hsh_datw) + 32);
+ASSYM(COP2_HSH_DATW5_PASS1_OFFSET, offsetof(struct octeon_cop2_state, hsh_datw) + 40);
+ASSYM(COP2_HSH_DATW6_PASS1_OFFSET, offsetof(struct octeon_cop2_state, hsh_datw) + 48);
+ASSYM(COP2_HSH_IVW0_PASS1_OFFSET, offsetof(struct octeon_cop2_state, hsh_ivw));
+ASSYM(COP2_HSH_IVW1_PASS1_OFFSET, offsetof(struct octeon_cop2_state, hsh_ivw) + 8);
+ASSYM(COP2_HSH_IVW2_PASS1_OFFSET, offsetof(struct octeon_cop2_state, hsh_ivw) + 16);
+#endif
Property changes on: trunk/sys/mips/mips/genassym.c
___________________________________________________________________
Added: svn:eol-style
## -0,0 +1 ##
+native
\ No newline at end of property
Added: svn:keywords
## -0,0 +1 ##
+MidnightBSD=%H
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+text/plain
\ No newline at end of property
Added: trunk/sys/mips/mips/in_cksum.c
===================================================================
--- trunk/sys/mips/mips/in_cksum.c (rev 0)
+++ trunk/sys/mips/mips/in_cksum.c 2018-05-26 21:55:02 UTC (rev 9987)
@@ -0,0 +1,249 @@
+/* $MidnightBSD$ */
+/*-
+ * Copyright (c) 1988, 1992, 1993
+ * The Regents of the University of California. All rights reserved.
+ * Copyright (c) 1996
+ * Matt Thomas <matt at 3am-software.com>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * 3. All advertising materials mentioning features or use of this software
+ * must display the following acknowledgement:
+ * This product includes software developed by the University of
+ * California, Berkeley and its contributors.
+ * 4. Neither the name of the University nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ * @(#)in_cksum.c 8.1 (Berkeley) 6/10/93
+ */
+
+#include <sys/cdefs.h>
+__FBSDID("$FreeBSD: stable/10/sys/mips/mips/in_cksum.c 202175 2010-01-12 21:36:08Z imp $");
+
+#include <sys/param.h>
+#include <sys/mbuf.h>
+#include <sys/systm.h>
+#include <netinet/in_systm.h>
+#include <netinet/in.h>
+#include <netinet/ip.h>
+#include <machine/in_cksum.h>
+
+/*
+ * Checksum routine for Internet Protocol family headers
+ * (Portable Alpha version).
+ *
+ * This routine is very heavily used in the network
+ * code and should be modified for each CPU to be as fast as possible.
+ */
+
+#define ADDCARRY(x) (x > 65535 ? x -= 65535 : x)
+#define REDUCE32 \
+ { \
+ q_util.q = sum; \
+ sum = q_util.s[0] + q_util.s[1] + q_util.s[2] + q_util.s[3]; \
+ }
+#define REDUCE16 \
+ { \
+ q_util.q = sum; \
+ l_util.l = q_util.s[0] + q_util.s[1] + q_util.s[2] + q_util.s[3]; \
+ sum = l_util.s[0] + l_util.s[1]; \
+ ADDCARRY(sum); \
+ }
+
+static const u_int32_t in_masks[] = {
+#if _BYTE_ORDER == _LITTLE_ENDIAN
+ /*0 bytes*/ /*1 byte*/ /*2 bytes*/ /*3 bytes*/
+ 0x00000000, 0x000000FF, 0x0000FFFF, 0x00FFFFFF, /* offset 0 */
+ 0x00000000, 0x0000FF00, 0x00FFFF00, 0xFFFFFF00, /* offset 1 */
+ 0x00000000, 0x00FF0000, 0xFFFF0000, 0xFFFF0000, /* offset 2 */
+ 0x00000000, 0xFF000000, 0xFF000000, 0xFF000000, /* offset 3 */
+#else
+ /*0 bytes*/ /*1 byte*/ /*2 bytes*/ /*3 bytes*/
+ 0x00000000, 0xFF000000, 0xFFFF0000, 0xFFFFFF00, /* offset 0 */
+ 0x00000000, 0x00FF0000, 0x00FFFF00, 0x00FFFFFF, /* offset 1 */
+ 0x00000000, 0x0000FF00, 0x0000FFFF, 0x0000FFFF, /* offset 2 */
+ 0x00000000, 0x000000FF, 0x000000FF, 0x000000FF, /* offset 3 */
+#endif
+};
+
+union l_util {
+ u_int16_t s[2];
+ u_int32_t l;
+};
+union q_util {
+ u_int16_t s[4];
+ u_int32_t l[2];
+ u_int64_t q;
+};
+
+static u_int64_t
+in_cksumdata(const void *buf, int len)
+{
+ const u_int32_t *lw = (const u_int32_t *) buf;
+ u_int64_t sum = 0;
+ u_int64_t prefilled;
+ int offset;
+ union q_util q_util;
+
+ if ((3 & (long) lw) == 0 && len == 20) {
+ sum = (u_int64_t) lw[0] + lw[1] + lw[2] + lw[3] + lw[4];
+ REDUCE32;
+ return sum;
+ }
+
+ if ((offset = 3 & (long) lw) != 0) {
+ const u_int32_t *masks = in_masks + (offset << 2);
+ lw = (u_int32_t *) (((long) lw) - offset);
+ sum = *lw++ & masks[len >= 3 ? 3 : len];
+ len -= 4 - offset;
+ if (len <= 0) {
+ REDUCE32;
+ return sum;
+ }
+ }
+#if 0
+ /*
+ * Force to cache line boundary.
+ */
+ offset = 32 - (0x1f & (long) lw);
+ if (offset < 32 && len > offset) {
+ len -= offset;
+ if (4 & offset) {
+ sum += (u_int64_t) lw[0];
+ lw += 1;
+ }
+ if (8 & offset) {
+ sum += (u_int64_t) lw[0] + lw[1];
+ lw += 2;
+ }
+ if (16 & offset) {
+ sum += (u_int64_t) lw[0] + lw[1] + lw[2] + lw[3];
+ lw += 4;
+ }
+ }
+#endif
+ /*
+ * access prefilling to start load of next cache line.
+ * then add current cache line
+ * save result of prefilling for loop iteration.
+ */
+ prefilled = lw[0];
+ while ((len -= 32) >= 4) {
+ u_int64_t prefilling = lw[8];
+ sum += prefilled + lw[1] + lw[2] + lw[3]
+ + lw[4] + lw[5] + lw[6] + lw[7];
+ lw += 8;
+ prefilled = prefilling;
+ }
+ if (len >= 0) {
+ sum += prefilled + lw[1] + lw[2] + lw[3]
+ + lw[4] + lw[5] + lw[6] + lw[7];
+ lw += 8;
+ } else {
+ len += 32;
+ }
+ while ((len -= 16) >= 0) {
+ sum += (u_int64_t) lw[0] + lw[1] + lw[2] + lw[3];
+ lw += 4;
+ }
+ len += 16;
+ while ((len -= 4) >= 0) {
+ sum += (u_int64_t) *lw++;
+ }
+ len += 4;
+ if (len > 0)
+ sum += (u_int64_t) (in_masks[len] & *lw);
+ REDUCE32;
+ return sum;
+}
+
+u_short
+in_addword(u_short a, u_short b)
+{
+ u_int64_t sum = a + b;
+
+ ADDCARRY(sum);
+ return (sum);
+}
+
+u_short
+in_pseudo(u_int32_t a, u_int32_t b, u_int32_t c)
+{
+ u_int64_t sum;
+ union q_util q_util;
+ union l_util l_util;
+
+ sum = (u_int64_t) a + b + c;
+ REDUCE16;
+ return (sum);
+}
+
+u_short
+in_cksum_skip(struct mbuf *m, int len, int skip)
+{
+ u_int64_t sum = 0;
+ int mlen = 0;
+ int clen = 0;
+ caddr_t addr;
+ union q_util q_util;
+ union l_util l_util;
+
+ len -= skip;
+ for (; skip && m; m = m->m_next) {
+ if (m->m_len > skip) {
+ mlen = m->m_len - skip;
+ addr = mtod(m, caddr_t) + skip;
+ goto skip_start;
+ } else {
+ skip -= m->m_len;
+ }
+ }
+
+ for (; m && len; m = m->m_next) {
+ if (m->m_len == 0)
+ continue;
+ mlen = m->m_len;
+ addr = mtod(m, caddr_t);
+skip_start:
+ if (len < mlen)
+ mlen = len;
+
+ if ((clen ^ (uintptr_t) addr) & 1)
+ sum += in_cksumdata(addr, mlen) << 8;
+ else
+ sum += in_cksumdata(addr, mlen);
+
+ clen += mlen;
+ len -= mlen;
+ }
+ REDUCE16;
+ return (~sum & 0xffff);
+}
+
+u_int in_cksum_hdr(const struct ip *ip)
+{
+ u_int64_t sum = in_cksumdata(ip, sizeof(struct ip));
+ union q_util q_util;
+ union l_util l_util;
+ REDUCE16;
+ return (~sum & 0xffff);
+}
Property changes on: trunk/sys/mips/mips/in_cksum.c
___________________________________________________________________
Added: svn:eol-style
## -0,0 +1 ##
+native
\ No newline at end of property
Added: svn:keywords
## -0,0 +1 ##
+MidnightBSD=%H
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+text/plain
\ No newline at end of property
Added: trunk/sys/mips/mips/inckern.S
===================================================================
--- trunk/sys/mips/mips/inckern.S (rev 0)
+++ trunk/sys/mips/mips/inckern.S 2018-05-26 21:55:02 UTC (rev 9987)
@@ -0,0 +1,48 @@
+/* $MidnightBSD$ */
+/*-
+ * Copyright (c) 2005 Olivier Houchard. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+ * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+ * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <machine/asm.h>
+__FBSDID("$FreeBSD: stable/10/sys/mips/mips/inckern.S 216474 2010-12-16 04:56:03Z jchandra $")
+
+ENTRY(_start)
+ PTR_LA t0, kernel_end
+ move sp, t0
+ add sp, 0x2000
+ and sp, ~0x7
+ PTR_LA t0, _startC
+ j t0
+ nop
+END(_start)
+
+#ifndef KERNNAME
+#error Need a kernel name here
+#endif
+
+.section ".real_kernel","aw"
+.globl kernel_start;
+kernel_start:
+.incbin KERNNAME
+.globl kernel_end;
+kernel_end:
Property changes on: trunk/sys/mips/mips/inckern.S
___________________________________________________________________
Added: svn:eol-style
## -0,0 +1 ##
+native
\ No newline at end of property
Added: svn:keywords
## -0,0 +1 ##
+MidnightBSD=%H
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+text/plain
\ No newline at end of property
Added: trunk/sys/mips/mips/intr_machdep.c
===================================================================
--- trunk/sys/mips/mips/intr_machdep.c (rev 0)
+++ trunk/sys/mips/mips/intr_machdep.c 2018-05-26 21:55:02 UTC (rev 9987)
@@ -0,0 +1,279 @@
+/* $MidnightBSD$ */
+/*-
+ * Copyright (c) 2006 Oleksandr Tymoshenko
+ * Copyright (c) 2002-2004 Juli Mallett <jmallett at FreeBSD.org>
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions, and the following disclaimer,
+ * without modification, immediately at the beginning of the file.
+ * 2. The name of the author may not be used to endorse or promote products
+ * derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ */
+
+#include <sys/cdefs.h>
+__FBSDID("$FreeBSD: stable/10/sys/mips/mips/intr_machdep.c 233318 2012-03-22 17:47:52Z gonzo $");
+
+#include "opt_hwpmc_hooks.h"
+
+#include <sys/param.h>
+#include <sys/systm.h>
+#include <sys/bus.h>
+#include <sys/interrupt.h>
+#include <sys/pmc.h>
+#include <sys/pmckern.h>
+
+#include <machine/clock.h>
+#include <machine/cpu.h>
+#include <machine/cpufunc.h>
+#include <machine/cpuinfo.h>
+#include <machine/cpuregs.h>
+#include <machine/frame.h>
+#include <machine/intr_machdep.h>
+#include <machine/md_var.h>
+#include <machine/trap.h>
+
+static struct intr_event *hardintr_events[NHARD_IRQS];
+static struct intr_event *softintr_events[NSOFT_IRQS];
+static mips_intrcnt_t mips_intr_counters[NSOFT_IRQS + NHARD_IRQS];
+
+static int intrcnt_index;
+
+static cpu_intr_mask_t hardintr_mask_func;
+static cpu_intr_unmask_t hardintr_unmask_func;
+
+mips_intrcnt_t
+mips_intrcnt_create(const char* name)
+{
+ mips_intrcnt_t counter = &intrcnt[intrcnt_index++];
+
+ mips_intrcnt_setname(counter, name);
+ return counter;
+}
+
+void
+mips_intrcnt_setname(mips_intrcnt_t counter, const char *name)
+{
+ int idx = counter - intrcnt;
+
+ KASSERT(counter != NULL, ("mips_intrcnt_setname: NULL counter"));
+
+ snprintf(intrnames + (MAXCOMLEN + 1) * idx,
+ MAXCOMLEN + 1, "%-*s", MAXCOMLEN, name);
+}
+
+static void
+mips_mask_hard_irq(void *source)
+{
+ uintptr_t irq = (uintptr_t)source;
+
+ mips_wr_status(mips_rd_status() & ~(((1 << irq) << 8) << 2));
+}
+
+static void
+mips_unmask_hard_irq(void *source)
+{
+ uintptr_t irq = (uintptr_t)source;
+
+ mips_wr_status(mips_rd_status() | (((1 << irq) << 8) << 2));
+}
+
+static void
+mips_mask_soft_irq(void *source)
+{
+ uintptr_t irq = (uintptr_t)source;
+
+ mips_wr_status(mips_rd_status() & ~((1 << irq) << 8));
+}
+
+static void
+mips_unmask_soft_irq(void *source)
+{
+ uintptr_t irq = (uintptr_t)source;
+
+ mips_wr_status(mips_rd_status() | ((1 << irq) << 8));
+}
+
+/*
+ * Perform initialization of interrupts prior to setting
+ * handlings
+ */
+void
+cpu_init_interrupts()
+{
+ int i;
+ char name[MAXCOMLEN + 1];
+
+ /*
+ * Initialize all available vectors so spare IRQ
+ * would show up in systat output
+ */
+ for (i = 0; i < NSOFT_IRQS; i++) {
+ snprintf(name, MAXCOMLEN + 1, "sint%d:", i);
+ mips_intr_counters[i] = mips_intrcnt_create(name);
+ }
+
+ for (i = 0; i < NHARD_IRQS; i++) {
+ snprintf(name, MAXCOMLEN + 1, "int%d:", i);
+ mips_intr_counters[NSOFT_IRQS + i] = mips_intrcnt_create(name);
+ }
+}
+
+void
+cpu_set_hardintr_mask_func(cpu_intr_mask_t func)
+{
+
+ hardintr_mask_func = func;
+}
+
+void
+cpu_set_hardintr_unmask_func(cpu_intr_unmask_t func)
+{
+
+ hardintr_unmask_func = func;
+}
+
+void
+cpu_establish_hardintr(const char *name, driver_filter_t *filt,
+ void (*handler)(void*), void *arg, int irq, int flags, void **cookiep)
+{
+ struct intr_event *event;
+ int error;
+
+ /*
+ * We have 6 levels, but thats 0 - 5 (not including 6)
+ */
+ if (irq < 0 || irq >= NHARD_IRQS)
+ panic("%s called for unknown hard intr %d", __func__, irq);
+
+ if (hardintr_mask_func == NULL)
+ hardintr_mask_func = mips_mask_hard_irq;
+
+ if (hardintr_unmask_func == NULL)
+ hardintr_unmask_func = mips_unmask_hard_irq;
+
+ event = hardintr_events[irq];
+ if (event == NULL) {
+ error = intr_event_create(&event, (void *)(uintptr_t)irq, 0,
+ irq, hardintr_mask_func, hardintr_unmask_func,
+ NULL, NULL, "int%d", irq);
+ if (error)
+ return;
+ hardintr_events[irq] = event;
+ mips_unmask_hard_irq((void*)(uintptr_t)irq);
+ }
+
+ intr_event_add_handler(event, name, filt, handler, arg,
+ intr_priority(flags), flags, cookiep);
+
+ mips_intrcnt_setname(mips_intr_counters[NSOFT_IRQS + irq],
+ event->ie_fullname);
+}
+
+void
+cpu_establish_softintr(const char *name, driver_filter_t *filt,
+ void (*handler)(void*), void *arg, int irq, int flags,
+ void **cookiep)
+{
+ struct intr_event *event;
+ int error;
+
+#if 0
+ printf("Establish SOFT IRQ %d: filt %p handler %p arg %p\n",
+ irq, filt, handler, arg);
+#endif
+ if (irq < 0 || irq > NSOFT_IRQS)
+ panic("%s called for unknown hard intr %d", __func__, irq);
+
+ event = softintr_events[irq];
+ if (event == NULL) {
+ error = intr_event_create(&event, (void *)(uintptr_t)irq, 0,
+ irq, mips_mask_soft_irq, mips_unmask_soft_irq,
+ NULL, NULL, "sint%d:", irq);
+ if (error)
+ return;
+ softintr_events[irq] = event;
+ mips_unmask_soft_irq((void*)(uintptr_t)irq);
+ }
+
+ intr_event_add_handler(event, name, filt, handler, arg,
+ intr_priority(flags), flags, cookiep);
+
+ mips_intrcnt_setname(mips_intr_counters[irq], event->ie_fullname);
+}
+
+void
+cpu_intr(struct trapframe *tf)
+{
+ struct intr_event *event;
+ register_t cause, status;
+ int hard, i, intr;
+
+ critical_enter();
+
+ cause = mips_rd_cause();
+ status = mips_rd_status();
+ intr = (cause & MIPS_INT_MASK) >> 8;
+ /*
+ * Do not handle masked interrupts. They were masked by
+ * pre_ithread function (mips_mask_XXX_intr) and will be
+ * unmasked once ithread is through with handler
+ */
+ intr &= (status & MIPS_INT_MASK) >> 8;
+ while ((i = fls(intr)) != 0) {
+ intr &= ~(1 << (i - 1));
+ switch (i) {
+ case 1: case 2:
+ /* Software interrupt. */
+ i--; /* Get a 0-offset interrupt. */
+ hard = 0;
+ event = softintr_events[i];
+ mips_intrcnt_inc(mips_intr_counters[i]);
+ break;
+ default:
+ /* Hardware interrupt. */
+ i -= 2; /* Trim software interrupt bits. */
+ i--; /* Get a 0-offset interrupt. */
+ hard = 1;
+ event = hardintr_events[i];
+ mips_intrcnt_inc(mips_intr_counters[NSOFT_IRQS + i]);
+ break;
+ }
+
+ if (!event || TAILQ_EMPTY(&event->ie_handlers)) {
+ printf("stray %s interrupt %d\n",
+ hard ? "hard" : "soft", i);
+ continue;
+ }
+
+ if (intr_event_handle(event, tf) != 0) {
+ printf("stray %s interrupt %d\n",
+ hard ? "hard" : "soft", i);
+ }
+ }
+
+ KASSERT(i == 0, ("all interrupts handled"));
+
+ critical_exit();
+
+#ifdef HWPMC_HOOKS
+ if (pmc_hook && (PCPU_GET(curthread)->td_pflags & TDP_CALLCHAIN))
+ pmc_hook(PCPU_GET(curthread), PMC_FN_USER_CALLCHAIN, tf);
+#endif
+}
Property changes on: trunk/sys/mips/mips/intr_machdep.c
___________________________________________________________________
Added: svn:eol-style
## -0,0 +1 ##
+native
\ No newline at end of property
Added: svn:keywords
## -0,0 +1 ##
+MidnightBSD=%H
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+text/plain
\ No newline at end of property
Added: trunk/sys/mips/mips/libkern_machdep.c
===================================================================
--- trunk/sys/mips/mips/libkern_machdep.c (rev 0)
+++ trunk/sys/mips/mips/libkern_machdep.c 2018-05-26 21:55:02 UTC (rev 9987)
@@ -0,0 +1,40 @@
+/* $MidnightBSD$ */
+/*-
+ * Copyright (c) 2012 Juli Mallett <jmallett at FreeBSD.org>
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ * $FreeBSD: stable/10/sys/mips/mips/libkern_machdep.c 232896 2012-03-12 21:25:32Z jmallett $
+ */
+
+/*
+ * Include libkern support routines for 64-bit operations when building o32
+ * kernels.
+ */
+#if defined(__mips_o32)
+#include <libkern/divdi3.c>
+#include <libkern/moddi3.c>
+#include <libkern/qdivrem.c>
+#include <libkern/udivdi3.c>
+#include <libkern/umoddi3.c>
+#endif
Property changes on: trunk/sys/mips/mips/libkern_machdep.c
___________________________________________________________________
Added: svn:eol-style
## -0,0 +1 ##
+native
\ No newline at end of property
Added: svn:keywords
## -0,0 +1 ##
+MidnightBSD=%H
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+text/plain
\ No newline at end of property
Added: trunk/sys/mips/mips/locore.S
===================================================================
--- trunk/sys/mips/mips/locore.S (rev 0)
+++ trunk/sys/mips/mips/locore.S 2018-05-26 21:55:02 UTC (rev 9987)
@@ -0,0 +1,188 @@
+/* $MidnightBSD$ */
+/* $OpenBSD: locore.S,v 1.18 1998/09/15 10:58:53 pefo Exp $ */
+/*-
+ * Copyright (c) 1992, 1993
+ * The Regents of the University of California. All rights reserved.
+ *
+ * This code is derived from software contributed to Berkeley by
+ * Digital Equipment Corporation and Ralph Campbell.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * 4. Neither the name of the University nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ * Copyright (C) 1989 Digital Equipment Corporation.
+ * Permission to use, copy, modify, and distribute this software and
+ * its documentation for any purpose and without fee is hereby granted,
+ * provided that the above copyright notice appears in all copies.
+ * Digital Equipment Corporation makes no representations about the
+ * suitability of this software for any purpose. It is provided "as is"
+ * without express or implied warranty.
+ *
+ * from: Header: /sprite/src/kernel/mach/ds3100.md/RCS/loMem.s,
+ * v 1.1 89/07/11 17:55:04 nelson Exp SPRITE (DECWRL)
+ * from: Header: /sprite/src/kernel/mach/ds3100.md/RCS/machAsm.s,
+ * v 9.2 90/01/29 18:00:39 shirriff Exp SPRITE (DECWRL)
+ * from: Header: /sprite/src/kernel/vm/ds3100.md/vmPmaxAsm.s,
+ * v 1.1 89/07/10 14:27:41 nelson Exp SPRITE (DECWRL)
+ *
+ * from: @(#)locore.s 8.5 (Berkeley) 1/4/94
+ * JNPR: locore.S,v 1.6.2.1 2007/08/29 12:24:49 girish
+ * $FreeBSD: stable/10/sys/mips/mips/locore.S 232615 2012-03-06 19:01:32Z jmallett $
+ */
+
+/*
+ * FREEBSD_DEVELOPERS_FIXME
+ * The start routine below was written for a multi-core CPU
+ * with each core being hyperthreaded. This serves as an example
+ * for a complex CPU architecture. For a different CPU complex
+ * please make necessary changes to read CPU-ID etc.
+ * A clean solution would be to have a different locore file for
+ * each CPU type.
+ */
+
+/*
+ * Contains code that is the first executed at boot time plus
+ * assembly language support routines.
+ */
+
+#include <machine/asm.h>
+#include <machine/cpu.h>
+#include <machine/cpuregs.h>
+#include <machine/regnum.h>
+
+#include "assym.s"
+
+ .data
+#ifdef YAMON
+GLOBAL(fenvp)
+ .space 4 # Assumes mips32? Is that OK?
+#endif
+
+ .set noreorder
+
+ .text
+
+GLOBAL(btext)
+ASM_ENTRY(_start)
+VECTOR(_locore, unknown)
+ /* UNSAFE TO USE a0..a3, need to preserve the args from boot loader */
+ mtc0 zero, MIPS_COP_0_CAUSE # Clear soft interrupts
+
+#if defined(CPU_CNMIPS)
+ /*
+ * t1: Bits to set explicitly:
+ * Enable FPU
+ */
+
+ /* Set these bits */
+ li t1, (MIPS_SR_COP_0_BIT | MIPS_SR_PX | MIPS_SR_KX | MIPS_SR_UX | MIPS_SR_SX | MIPS_SR_BEV)
+
+ /* Reset these bits */
+ li t0, ~(MIPS_SR_DE | MIPS_SR_SR | MIPS_SR_ERL | MIPS_SR_EXL | MIPS_SR_INT_IE | MIPS_SR_COP_2_BIT)
+#elif defined (CPU_RMI) || defined (CPU_NLM)
+ /* Set these bits */
+ li t1, (MIPS_SR_COP_2_BIT | MIPS_SR_COP_0_BIT | MIPS_SR_KX | MIPS_SR_UX)
+
+ /* Reset these bits */
+ li t0, ~(MIPS_SR_BEV | MIPS_SR_SR | MIPS_SR_INT_IE)
+#else
+ /*
+ * t0: Bits to preserve if set:
+ * Soft reset
+ * Boot exception vectors (firmware-provided)
+ */
+ li t0, (MIPS_SR_BEV | MIPS_SR_SR)
+ /*
+ * t1: Bits to set explicitly:
+ * Enable FPU
+ */
+ li t1, MIPS_SR_COP_1_BIT
+#ifdef __mips_n64
+ or t1, MIPS_SR_KX | MIPS_SR_SX | MIPS_SR_UX
+#endif
+#endif
+ /*
+ * Read coprocessor 0 status register, clear bits not
+ * preserved (namely, clearing interrupt bits), and set
+ * bits we want to explicitly set.
+ */
+ mfc0 t2, MIPS_COP_0_STATUS
+ and t2, t0
+ or t2, t1
+ mtc0 t2, MIPS_COP_0_STATUS
+ COP0_SYNC
+
+ /* Make sure KSEG0 is cached */
+ li t0, MIPS_CCA_CACHED
+ mtc0 t0, MIPS_COP_0_CONFIG
+ COP0_SYNC
+
+ /*xxximp
+ * now that we pass a0...a3 to the platform_init routine, do we need
+ * to stash this stuff here?
+ */
+#ifdef YAMON
+ /* Save YAMON boot environment pointer */
+ sw a2, _C_LABEL(fenvp)
+#endif
+
+#if defined(CPU_CNMIPS) && defined(SMP)
+ .set push
+ .set mips32r2
+ rdhwr t2, $0
+ beqz t2, 1f
+ nop
+ j octeon_ap_wait
+ nop
+ .set pop
+1:
+#endif
+
+ /*
+ * Initialize stack and call machine startup.
+ */
+ PTR_LA sp, _C_LABEL(pcpu_space)
+ PTR_ADDU sp, (PAGE_SIZE * 2) - CALLFRAME_SIZ
+
+ REG_S zero, CALLFRAME_RA(sp) # Zero out old ra for debugger
+ REG_S zero, CALLFRAME_SP(sp) # Zero out old fp for debugger
+
+ PTR_LA gp, _C_LABEL(_gp)
+
+ /* Call the platform-specific startup code. */
+ jal _C_LABEL(platform_start)
+ nop
+
+ PTR_LA sp, _C_LABEL(thread0)
+ PTR_L a0, TD_PCB(sp)
+ REG_LI t0, ~7
+ and a0, a0, t0
+ PTR_SUBU sp, a0, CALLFRAME_SIZ
+
+ jal _C_LABEL(mi_startup) # mi_startup(frame)
+ sw zero, CALLFRAME_SIZ - 8(sp) # Zero out old fp for debugger
+
+ PANIC("Startup failed!")
+
+VECTOR_END(_locore)
Property changes on: trunk/sys/mips/mips/locore.S
___________________________________________________________________
Added: svn:eol-style
## -0,0 +1 ##
+native
\ No newline at end of property
Added: svn:keywords
## -0,0 +1 ##
+MidnightBSD=%H
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+text/plain
\ No newline at end of property
Added: trunk/sys/mips/mips/machdep.c
===================================================================
--- trunk/sys/mips/mips/machdep.c (rev 0)
+++ trunk/sys/mips/mips/machdep.c 2018-05-26 21:55:02 UTC (rev 9987)
@@ -0,0 +1,573 @@
+/* $MidnightBSD$ */
+ /* $OpenBSD: machdep.c,v 1.33 1998/09/15 10:58:54 pefo Exp $ */
+/* tracked to 1.38 */
+/*
+ * Copyright (c) 1988 University of Utah.
+ * Copyright (c) 1992, 1993
+ * The Regents of the University of California. All rights reserved.
+ *
+ * This code is derived from software contributed to Berkeley by
+ * the Systems Programming Group of the University of Utah Computer
+ * Science Department, The Mach Operating System project at
+ * Carnegie-Mellon University and Ralph Campbell.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * 4. Neither the name of the University nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ * from: @(#)machdep.c 8.3 (Berkeley) 1/12/94
+ * Id: machdep.c,v 1.33 1998/09/15 10:58:54 pefo Exp
+ * JNPR: machdep.c,v 1.11.2.3 2007/08/29 12:24:49
+ */
+
+#include <sys/cdefs.h>
+__FBSDID("$FreeBSD: stable/10/sys/mips/mips/machdep.c 262717 2014-03-03 20:28:27Z brooks $");
+
+#include "opt_ddb.h"
+#include "opt_md.h"
+
+#include <sys/param.h>
+#include <sys/proc.h>
+#include <sys/systm.h>
+#include <sys/buf.h>
+#include <sys/bus.h>
+#include <sys/conf.h>
+#include <sys/cpu.h>
+#include <sys/kernel.h>
+#include <sys/linker.h>
+#include <sys/malloc.h>
+#include <sys/mbuf.h>
+#include <sys/msgbuf.h>
+#include <sys/reboot.h>
+#include <sys/rwlock.h>
+#include <sys/sched.h>
+#include <sys/sysctl.h>
+#include <sys/sysproto.h>
+#include <sys/vmmeter.h>
+
+#include <vm/vm.h>
+#include <vm/vm_kern.h>
+#include <vm/vm_object.h>
+#include <vm/vm_page.h>
+#include <vm/pmap.h>
+#include <vm/vm_map.h>
+#include <vm/vm_pager.h>
+#include <vm/vm_extern.h>
+#include <sys/socket.h>
+
+#include <sys/user.h>
+#include <sys/interrupt.h>
+#include <sys/cons.h>
+#include <sys/syslog.h>
+#include <machine/asm.h>
+#include <machine/bootinfo.h>
+#include <machine/cache.h>
+#include <machine/clock.h>
+#include <machine/cpu.h>
+#include <machine/cpuregs.h>
+#include <machine/elf.h>
+#include <machine/hwfunc.h>
+#include <machine/intr_machdep.h>
+#include <machine/md_var.h>
+#include <machine/tlb.h>
+#ifdef DDB
+#include <sys/kdb.h>
+#include <ddb/ddb.h>
+#endif
+
+#include <sys/random.h>
+#include <net/if.h>
+
+#define BOOTINFO_DEBUG 0
+
+char machine[] = "mips";
+SYSCTL_STRING(_hw, HW_MACHINE, machine, CTLFLAG_RD, machine, 0, "Machine class");
+
+char cpu_model[80];
+SYSCTL_STRING(_hw, HW_MODEL, model, CTLFLAG_RD, cpu_model, 0, "Machine model");
+
+char cpu_board[80];
+SYSCTL_STRING(_hw, OID_AUTO, board, CTLFLAG_RD, cpu_board, 0, "Machine board");
+
+int cold = 1;
+long realmem = 0;
+long Maxmem = 0;
+int cpu_clock = MIPS_DEFAULT_HZ;
+SYSCTL_INT(_hw, OID_AUTO, clockrate, CTLFLAG_RD,
+ &cpu_clock, 0, "CPU instruction clock rate");
+int clocks_running = 0;
+
+vm_offset_t kstack0;
+
+/*
+ * Each entry in the pcpu_space[] array is laid out in the following manner:
+ * struct pcpu for cpu 'n' pcpu_space[n]
+ * boot stack for cpu 'n' pcpu_space[n] + PAGE_SIZE * 2 - CALLFRAME_SIZ
+ *
+ * Note that the boot stack grows downwards and we assume that we never
+ * use enough stack space to trample over the 'struct pcpu' that is at
+ * the beginning of the array.
+ *
+ * The array is aligned on a (PAGE_SIZE * 2) boundary so that the 'struct pcpu'
+ * is always in the even page frame of the wired TLB entry on SMP kernels.
+ *
+ * The array is in the .data section so that the stack does not get zeroed out
+ * when the .bss section is zeroed.
+ */
+char pcpu_space[MAXCPU][PAGE_SIZE * 2] \
+ __aligned(PAGE_SIZE * 2) __section(".data");
+
+struct pcpu *pcpup = (struct pcpu *)pcpu_space;
+
+vm_paddr_t phys_avail[PHYS_AVAIL_ENTRIES + 2];
+vm_paddr_t physmem_desc[PHYS_AVAIL_ENTRIES + 2];
+vm_paddr_t dump_avail[PHYS_AVAIL_ENTRIES + 2];
+
+#ifdef UNIMPLEMENTED
+struct platform platform;
+#endif
+
+static void cpu_startup(void *);
+SYSINIT(cpu, SI_SUB_CPU, SI_ORDER_FIRST, cpu_startup, NULL);
+
+struct kva_md_info kmi;
+
+int cpucfg; /* Value of processor config register */
+int num_tlbentries = 64; /* Size of the CPU tlb */
+int cputype;
+
+extern char MipsException[], MipsExceptionEnd[];
+
+/* TLB miss handler address and end */
+extern char MipsTLBMiss[], MipsTLBMissEnd[];
+
+/* Cache error handler */
+extern char MipsCache[], MipsCacheEnd[];
+
+/* MIPS wait skip region */
+extern char MipsWaitStart[], MipsWaitEnd[];
+
+extern char edata[], end[];
+#ifdef DDB
+extern vm_offset_t ksym_start, ksym_end;
+#endif
+
+u_int32_t bootdev;
+struct bootinfo bootinfo;
+/*
+ * First kseg0 address available for use. By default it's equal to &end.
+ * But in some cases there might be additional data placed right after
+ * _end by loader or ELF trampoline.
+ */
+vm_offset_t kernel_kseg0_end = (vm_offset_t)&end;
+
+static void
+cpu_startup(void *dummy)
+{
+
+ if (boothowto & RB_VERBOSE)
+ bootverbose++;
+
+ printf("real memory = %ju (%juK bytes)\n", ptoa((uintmax_t)realmem),
+ ptoa((uintmax_t)realmem) / 1024);
+
+ /*
+ * Display any holes after the first chunk of extended memory.
+ */
+ if (bootverbose) {
+ int indx;
+
+ printf("Physical memory chunk(s):\n");
+ for (indx = 0; phys_avail[indx + 1] != 0; indx += 2) {
+ vm_paddr_t size1 = phys_avail[indx + 1] - phys_avail[indx];
+
+ printf("0x%08jx - 0x%08jx, %ju bytes (%ju pages)\n",
+ (uintmax_t)phys_avail[indx],
+ (uintmax_t)phys_avail[indx + 1] - 1,
+ (uintmax_t)size1,
+ (uintmax_t)size1 / PAGE_SIZE);
+ }
+ }
+
+ vm_ksubmap_init(&kmi);
+
+ printf("avail memory = %ju (%juMB)\n",
+ ptoa((uintmax_t)cnt.v_free_count),
+ ptoa((uintmax_t)cnt.v_free_count) / 1048576);
+ cpu_init_interrupts();
+
+ /*
+ * Set up buffers, so they can be used to read disk labels.
+ */
+ bufinit();
+ vm_pager_bufferinit();
+}
+
+/*
+ * Shutdown the CPU as much as possible
+ */
+void
+cpu_reset(void)
+{
+
+ platform_reset();
+}
+
+/*
+ * Flush the D-cache for non-DMA I/O so that the I-cache can
+ * be made coherent later.
+ */
+void
+cpu_flush_dcache(void *ptr, size_t len)
+{
+ /* TBD */
+}
+
+/* Get current clock frequency for the given cpu id. */
+int
+cpu_est_clockrate(int cpu_id, uint64_t *rate)
+{
+
+ return (ENXIO);
+}
+
+/*
+ * Shutdown the CPU as much as possible
+ */
+void
+cpu_halt(void)
+{
+ for (;;)
+ ;
+}
+
+SYSCTL_STRUCT(_machdep, OID_AUTO, bootinfo, CTLFLAG_RD, &bootinfo,
+ bootinfo, "Bootinfo struct: kernel filename, BIOS harddisk geometry, etc");
+
+/*
+ * Initialize per cpu data structures, include curthread.
+ */
+void
+mips_pcpu0_init()
+{
+ /* Initialize pcpu info of cpu-zero */
+ pcpu_init(PCPU_ADDR(0), 0, sizeof(struct pcpu));
+ PCPU_SET(curthread, &thread0);
+}
+
+/*
+ * Initialize mips and configure to run kernel
+ */
+void
+mips_proc0_init(void)
+{
+#ifdef SMP
+ if (platform_processor_id() != 0)
+ panic("BSP must be processor number 0");
+#endif
+ proc_linkup0(&proc0, &thread0);
+
+ KASSERT((kstack0 & PAGE_MASK) == 0,
+ ("kstack0 is not aligned on a page boundary: 0x%0lx",
+ (long)kstack0));
+ thread0.td_kstack = kstack0;
+ thread0.td_kstack_pages = KSTACK_PAGES;
+ /*
+ * Do not use cpu_thread_alloc to initialize these fields
+ * thread0 is the only thread that has kstack located in KSEG0
+ * while cpu_thread_alloc handles kstack allocated in KSEG2.
+ */
+ thread0.td_pcb = (struct pcb *)(thread0.td_kstack +
+ thread0.td_kstack_pages * PAGE_SIZE) - 1;
+ thread0.td_frame = &thread0.td_pcb->pcb_regs;
+
+ /* Steal memory for the dynamic per-cpu area. */
+ dpcpu_init((void *)pmap_steal_memory(DPCPU_SIZE), 0);
+
+ PCPU_SET(curpcb, thread0.td_pcb);
+ /*
+ * There is no need to initialize md_upte array for thread0 as it's
+ * located in .bss section and should be explicitly zeroed during
+ * kernel initialization.
+ */
+}
+
+void
+cpu_initclocks(void)
+{
+
+ platform_initclocks();
+ cpu_initclocks_bsp();
+}
+
+struct msgbuf *msgbufp=0;
+
+/*
+ * Initialize the hardware exception vectors, and the jump table used to
+ * call locore cache and TLB management functions, based on the kind
+ * of CPU the kernel is running on.
+ */
+void
+mips_vector_init(void)
+{
+ /*
+ * Make sure that the Wait region logic is not been
+ * changed
+ */
+ if (MipsWaitEnd - MipsWaitStart != 16)
+ panic("startup: MIPS wait region not correct");
+ /*
+ * Copy down exception vector code.
+ */
+ if (MipsTLBMissEnd - MipsTLBMiss > 0x80)
+ panic("startup: UTLB code too large");
+
+ if (MipsCacheEnd - MipsCache > 0x80)
+ panic("startup: Cache error code too large");
+
+ bcopy(MipsTLBMiss, (void *)MIPS_UTLB_MISS_EXC_VEC,
+ MipsTLBMissEnd - MipsTLBMiss);
+
+ /*
+ * XXXRW: Why don't we install the XTLB handler for all 64-bit
+ * architectures?
+ */
+#if defined(__mips_n64) || defined(CPU_RMI) || defined(CPU_NLM) || defined(CPU_BERI)
+/* Fake, but sufficient, for the 32-bit with 64-bit hardware addresses */
+ bcopy(MipsTLBMiss, (void *)MIPS_XTLB_MISS_EXC_VEC,
+ MipsTLBMissEnd - MipsTLBMiss);
+#endif
+
+ bcopy(MipsException, (void *)MIPS_GEN_EXC_VEC,
+ MipsExceptionEnd - MipsException);
+
+ bcopy(MipsCache, (void *)MIPS_CACHE_ERR_EXC_VEC,
+ MipsCacheEnd - MipsCache);
+
+ /*
+ * Clear out the I and D caches.
+ */
+ mips_icache_sync_all();
+ mips_dcache_wbinv_all();
+
+ /*
+ * Mask all interrupts. Each interrupt will be enabled
+ * when handler is installed for it
+ */
+ set_intr_mask(0);
+
+ /* Clear BEV in SR so we start handling our own exceptions */
+ mips_wr_status(mips_rd_status() & ~MIPS_SR_BEV);
+}
+
+/*
+ * Fix kernel_kseg0_end address in case trampoline placed debug sympols
+ * data there
+ */
+void
+mips_postboot_fixup(void)
+{
+ static char fake_preload[256];
+ caddr_t preload_ptr = (caddr_t)&fake_preload[0];
+ size_t size = 0;
+
+#define PRELOAD_PUSH_VALUE(type, value) do { \
+ *(type *)(preload_ptr + size) = (value); \
+ size += sizeof(type); \
+} while (0);
+
+ /*
+ * Provide kernel module file information
+ */
+ PRELOAD_PUSH_VALUE(uint32_t, MODINFO_NAME);
+ PRELOAD_PUSH_VALUE(uint32_t, strlen("kernel") + 1);
+ strcpy((char*)(preload_ptr + size), "kernel");
+ size += strlen("kernel") + 1;
+ size = roundup(size, sizeof(u_long));
+
+ PRELOAD_PUSH_VALUE(uint32_t, MODINFO_TYPE);
+ PRELOAD_PUSH_VALUE(uint32_t, strlen("elf kernel") + 1);
+ strcpy((char*)(preload_ptr + size), "elf kernel");
+ size += strlen("elf kernel") + 1;
+ size = roundup(size, sizeof(u_long));
+
+ PRELOAD_PUSH_VALUE(uint32_t, MODINFO_ADDR);
+ PRELOAD_PUSH_VALUE(uint32_t, sizeof(vm_offset_t));
+ PRELOAD_PUSH_VALUE(vm_offset_t, KERNLOADADDR);
+ size = roundup(size, sizeof(u_long));
+
+ PRELOAD_PUSH_VALUE(uint32_t, MODINFO_SIZE);
+ PRELOAD_PUSH_VALUE(uint32_t, sizeof(size_t));
+ PRELOAD_PUSH_VALUE(size_t, (size_t)&end - KERNLOADADDR);
+ size = roundup(size, sizeof(u_long));
+
+ /* End marker */
+ PRELOAD_PUSH_VALUE(uint32_t, 0);
+ PRELOAD_PUSH_VALUE(uint32_t, 0);
+
+#undef PRELOAD_PUSH_VALUE
+
+ KASSERT((size < sizeof(fake_preload)),
+ ("fake preload size is more thenallocated"));
+
+ preload_metadata = (void *)fake_preload;
+
+#ifdef DDB
+ Elf_Size *trampoline_data = (Elf_Size*)kernel_kseg0_end;
+ Elf_Size symtabsize = 0;
+
+ if (trampoline_data[0] == SYMTAB_MAGIC) {
+ symtabsize = trampoline_data[1];
+ kernel_kseg0_end += 2 * sizeof(Elf_Size);
+ /* start of .symtab */
+ ksym_start = kernel_kseg0_end;
+ kernel_kseg0_end += symtabsize;
+ /* end of .strtab */
+ ksym_end = kernel_kseg0_end;
+ }
+#endif
+}
+
+#ifdef SMP
+void
+mips_pcpu_tlb_init(struct pcpu *pcpu)
+{
+ vm_paddr_t pa;
+ pt_entry_t pte;
+
+ /*
+ * Map the pcpu structure at the virtual address 'pcpup'.
+ * We use a wired tlb index to do this one-time mapping.
+ */
+ pa = vtophys(pcpu);
+ pte = PTE_D | PTE_V | PTE_G | PTE_C_CACHE;
+ tlb_insert_wired(PCPU_TLB_ENTRY, (vm_offset_t)pcpup,
+ TLBLO_PA_TO_PFN(pa) | pte,
+ TLBLO_PA_TO_PFN(pa + PAGE_SIZE) | pte);
+}
+#endif
+
+/*
+ * Initialise a struct pcpu.
+ */
+void
+cpu_pcpu_init(struct pcpu *pcpu, int cpuid, size_t size)
+{
+
+ pcpu->pc_next_asid = 1;
+ pcpu->pc_asid_generation = 1;
+#ifdef SMP
+ if ((vm_offset_t)pcpup >= VM_MIN_KERNEL_ADDRESS &&
+ (vm_offset_t)pcpup <= VM_MAX_KERNEL_ADDRESS) {
+ mips_pcpu_tlb_init(pcpu);
+ }
+#endif
+}
+
+int
+fill_dbregs(struct thread *td, struct dbreg *dbregs)
+{
+
+ /* No debug registers on mips */
+ return (ENOSYS);
+}
+
+int
+set_dbregs(struct thread *td, struct dbreg *dbregs)
+{
+
+ /* No debug registers on mips */
+ return (ENOSYS);
+}
+
+void
+spinlock_enter(void)
+{
+ struct thread *td;
+ register_t intr;
+
+ td = curthread;
+ if (td->td_md.md_spinlock_count == 0) {
+ intr = intr_disable();
+ td->td_md.md_spinlock_count = 1;
+ td->td_md.md_saved_intr = intr;
+ } else
+ td->td_md.md_spinlock_count++;
+ critical_enter();
+}
+
+void
+spinlock_exit(void)
+{
+ struct thread *td;
+ register_t intr;
+
+ td = curthread;
+ critical_exit();
+ intr = td->td_md.md_saved_intr;
+ td->td_md.md_spinlock_count--;
+ if (td->td_md.md_spinlock_count == 0)
+ intr_restore(intr);
+}
+
+/*
+ * call platform specific code to halt (until next interrupt) for the idle loop
+ */
+void
+cpu_idle(int busy)
+{
+ KASSERT((mips_rd_status() & MIPS_SR_INT_IE) != 0,
+ ("interrupts disabled in idle process."));
+ KASSERT((mips_rd_status() & MIPS_INT_MASK) != 0,
+ ("all interrupts masked in idle process."));
+
+ if (!busy) {
+ critical_enter();
+ cpu_idleclock();
+ }
+ mips_wait();
+ if (!busy) {
+ cpu_activeclock();
+ critical_exit();
+ }
+}
+
+int
+cpu_idle_wakeup(int cpu)
+{
+
+ return (0);
+}
+
+int
+is_cacheable_mem(vm_paddr_t pa)
+{
+ int i;
+
+ for (i = 0; physmem_desc[i + 1] != 0; i += 2) {
+ if (pa >= physmem_desc[i] && pa < physmem_desc[i + 1])
+ return (1);
+ }
+
+ return (0);
+}
Property changes on: trunk/sys/mips/mips/machdep.c
___________________________________________________________________
Added: svn:eol-style
## -0,0 +1 ##
+native
\ No newline at end of property
Added: svn:keywords
## -0,0 +1 ##
+MidnightBSD=%H
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+text/plain
\ No newline at end of property
Added: trunk/sys/mips/mips/mem.c
===================================================================
--- trunk/sys/mips/mips/mem.c (rev 0)
+++ trunk/sys/mips/mips/mem.c 2018-05-26 21:55:02 UTC (rev 9987)
@@ -0,0 +1,167 @@
+/* $MidnightBSD$ */
+/*-
+ * Copyright (c) 1988 University of Utah.
+ * Copyright (c) 1982, 1986, 1990 The Regents of the University of California.
+ * All rights reserved.
+ *
+ * This code is derived from software contributed to Berkeley by
+ * the Systems Programming Group of the University of Utah Computer
+ * Science Department, and code derived from software contributed to
+ * Berkeley by William Jolitz.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * 4. Neither the name of the University nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ * from: Utah $Hdr: mem.c 1.13 89/10/08$
+ * from: @(#)mem.c 7.2 (Berkeley) 5/9/91
+ */
+
+#include <sys/cdefs.h>
+__FBSDID("$FreeBSD: stable/10/sys/mips/mips/mem.c 278746 2015-02-14 08:44:12Z kib $");
+
+/*
+ * Memory special file
+ */
+
+#include <sys/param.h>
+#include <sys/conf.h>
+#include <sys/fcntl.h>
+#include <sys/kernel.h>
+#include <sys/lock.h>
+#include <sys/malloc.h>
+#include <sys/memrange.h>
+#include <sys/module.h>
+#include <sys/mutex.h>
+#include <sys/proc.h>
+#include <sys/msgbuf.h>
+#include <sys/systm.h>
+#include <sys/signalvar.h>
+#include <sys/uio.h>
+
+#include <machine/md_var.h>
+#include <machine/vmparam.h>
+
+#include <vm/vm.h>
+#include <vm/pmap.h>
+#include <vm/vm_extern.h>
+#include <vm/vm_page.h>
+
+#include <machine/memdev.h>
+
+struct mem_range_softc mem_range_softc;
+
+/* ARGSUSED */
+int
+memrw(struct cdev *dev, struct uio *uio, int flags)
+{
+ struct iovec *iov;
+ int error = 0;
+ vm_offset_t va, eva, off, v;
+ vm_prot_t prot;
+ struct vm_page m;
+ vm_page_t marr;
+ vm_size_t cnt;
+
+ cnt = 0;
+ error = 0;
+
+ pmap_page_init(&m);
+ while (uio->uio_resid > 0 && !error) {
+ iov = uio->uio_iov;
+ if (iov->iov_len == 0) {
+ uio->uio_iov++;
+ uio->uio_iovcnt--;
+ if (uio->uio_iovcnt < 0)
+ panic("memrw");
+ continue;
+ }
+ if (dev2unit(dev) == CDEV_MINOR_MEM) {
+ v = uio->uio_offset;
+
+ off = uio->uio_offset & PAGE_MASK;
+ cnt = PAGE_SIZE - ((vm_offset_t)iov->iov_base &
+ PAGE_MASK);
+ cnt = min(cnt, PAGE_SIZE - off);
+ cnt = min(cnt, iov->iov_len);
+
+ m.phys_addr = trunc_page(v);
+ marr = &m;
+ error = uiomove_fromphys(&marr, off, cnt, uio);
+ }
+ else if (dev2unit(dev) == CDEV_MINOR_KMEM) {
+ va = uio->uio_offset;
+
+ va = trunc_page(uio->uio_offset);
+ eva = round_page(uio->uio_offset
+ + iov->iov_len);
+
+ /*
+ * Make sure that all the pages are currently resident
+ * so that we don't create any zero-fill pages.
+ */
+ if (va >= VM_MIN_KERNEL_ADDRESS &&
+ eva <= VM_MAX_KERNEL_ADDRESS) {
+ for (; va < eva; va += PAGE_SIZE)
+ if (pmap_extract(kernel_pmap, va) == 0)
+ return (EFAULT);
+
+ prot = (uio->uio_rw == UIO_READ)
+ ? VM_PROT_READ : VM_PROT_WRITE;
+
+ va = uio->uio_offset;
+ if (kernacc((void *) va, iov->iov_len, prot)
+ == FALSE)
+ return (EFAULT);
+ }
+
+ va = uio->uio_offset;
+ error = uiomove((void *)va, iov->iov_len, uio);
+ continue;
+ }
+ }
+
+ return (error);
+}
+
+/*
+ * allow user processes to MMAP some memory sections
+ * instead of going through read/write
+ */
+int
+memmmap(struct cdev *dev, vm_ooffset_t offset, vm_paddr_t *paddr,
+ int prot, vm_memattr_t *memattr)
+{
+ /*
+ * /dev/mem is the only one that makes sense through this
+ * interface. For /dev/kmem any physaddr we return here
+ * could be transient and hence incorrect or invalid at
+ * a later time.
+ */
+ if (dev2unit(dev) != CDEV_MINOR_MEM)
+ return (-1);
+
+ *paddr = offset;
+
+ return (0);
+}
Property changes on: trunk/sys/mips/mips/mem.c
___________________________________________________________________
Added: svn:eol-style
## -0,0 +1 ##
+native
\ No newline at end of property
Added: svn:keywords
## -0,0 +1 ##
+MidnightBSD=%H
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+text/plain
\ No newline at end of property
Added: trunk/sys/mips/mips/minidump_machdep.c
===================================================================
--- trunk/sys/mips/mips/minidump_machdep.c (rev 0)
+++ trunk/sys/mips/mips/minidump_machdep.c 2018-05-26 21:55:02 UTC (rev 9987)
@@ -0,0 +1,341 @@
+/* $MidnightBSD$ */
+/*-
+ * Copyright (c) 2010 Oleksandr Tymoshenko <gonzo at freebsd.org>
+ * Copyright (c) 2008 Semihalf, Grzegorz Bernacki
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+ * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+ * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * from: FreeBSD: src/sys/arm/arm/minidump_machdep.c v214223
+ */
+
+#include <sys/cdefs.h>
+__FBSDID("$FreeBSD: stable/10/sys/mips/mips/minidump_machdep.c 216148 2010-12-03 14:20:20Z jchandra $");
+
+#include <sys/param.h>
+#include <sys/systm.h>
+#include <sys/conf.h>
+#include <sys/cons.h>
+#include <sys/kernel.h>
+#include <sys/kerneldump.h>
+#include <sys/msgbuf.h>
+#include <vm/vm.h>
+#include <vm/pmap.h>
+#include <machine/pmap.h>
+#include <machine/atomic.h>
+#include <machine/elf.h>
+#include <machine/md_var.h>
+#include <machine/vmparam.h>
+#include <machine/minidump.h>
+#include <machine/cache.h>
+
+CTASSERT(sizeof(struct kerneldumpheader) == 512);
+
+/*
+ * Don't touch the first SIZEOF_METADATA bytes on the dump device. This
+ * is to protect us from metadata and to protect metadata from us.
+ */
+#define SIZEOF_METADATA (64*1024)
+
+uint32_t *vm_page_dump;
+int vm_page_dump_size;
+
+static struct kerneldumpheader kdh;
+static off_t dumplo;
+static off_t origdumplo;
+
+/* Handle chunked writes. */
+static uint64_t counter, progress;
+/* Just auxiliary bufffer */
+static char tmpbuffer[PAGE_SIZE];
+
+extern pd_entry_t *kernel_segmap;
+
+CTASSERT(sizeof(*vm_page_dump) == 4);
+
+static int
+is_dumpable(vm_paddr_t pa)
+{
+ int i;
+
+ for (i = 0; dump_avail[i] != 0 || dump_avail[i + 1] != 0; i += 2) {
+ if (pa >= dump_avail[i] && pa < dump_avail[i + 1])
+ return (1);
+ }
+ return (0);
+}
+
+void
+dump_add_page(vm_paddr_t pa)
+{
+ int idx, bit;
+
+ pa >>= PAGE_SHIFT;
+ idx = pa >> 5; /* 2^5 = 32 */
+ bit = pa & 31;
+ atomic_set_int(&vm_page_dump[idx], 1ul << bit);
+}
+
+void
+dump_drop_page(vm_paddr_t pa)
+{
+ int idx, bit;
+
+ pa >>= PAGE_SHIFT;
+ idx = pa >> 5; /* 2^5 = 32 */
+ bit = pa & 31;
+ atomic_clear_int(&vm_page_dump[idx], 1ul << bit);
+}
+
+#define PG2MB(pgs) (((pgs) + (1 << 8) - 1) >> 8)
+
+static int
+write_buffer(struct dumperinfo *di, char *ptr, size_t sz)
+{
+ size_t len;
+ int error, c;
+ u_int maxdumpsz;
+
+ maxdumpsz = di->maxiosize;
+
+ if (maxdumpsz == 0) /* seatbelt */
+ maxdumpsz = PAGE_SIZE;
+
+ error = 0;
+
+ while (sz) {
+ len = min(maxdumpsz, sz);
+ counter += len;
+ progress -= len;
+
+ if (counter >> 22) {
+ printf(" %jd", PG2MB(progress >> PAGE_SHIFT));
+ counter &= (1<<22) - 1;
+ }
+
+ if (ptr) {
+ error = dump_write(di, ptr, 0, dumplo, len);
+ if (error)
+ return (error);
+ dumplo += len;
+ ptr += len;
+ sz -= len;
+ } else {
+ panic("pa is not supported");
+ }
+
+ /* Check for user abort. */
+ c = cncheckc();
+ if (c == 0x03)
+ return (ECANCELED);
+ if (c != -1)
+ printf(" (CTRL-C to abort) ");
+ }
+
+ return (0);
+}
+
+void
+minidumpsys(struct dumperinfo *di)
+{
+ struct minidumphdr mdhdr;
+ uint64_t dumpsize;
+ uint32_t ptesize;
+ uint32_t bits;
+ vm_paddr_t pa;
+ vm_offset_t prev_pte = 0;
+ uint32_t count = 0;
+ vm_offset_t va;
+ pt_entry_t *pte;
+ int i, bit, error;
+ void *dump_va;
+
+ /* Flush cache */
+ mips_dcache_wbinv_all();
+
+ counter = 0;
+ /* Walk page table pages, set bits in vm_page_dump */
+ ptesize = 0;
+
+ for (va = VM_MIN_KERNEL_ADDRESS; va < kernel_vm_end; va += NBPDR) {
+ ptesize += PAGE_SIZE;
+ pte = pmap_pte(kernel_pmap, va);
+ KASSERT(pte != NULL, ("pte for %jx is NULL", (uintmax_t)va));
+ for (i = 0; i < NPTEPG; i++) {
+ if (pte_test(&pte[i], PTE_V)) {
+ pa = TLBLO_PTE_TO_PA(pte[i]);
+ if (is_dumpable(pa))
+ dump_add_page(pa);
+ }
+ }
+ }
+
+ /*
+ * Now mark pages from 0 to phys_avail[0], that's where kernel
+ * and pages allocated by pmap_steal reside
+ */
+ for (pa = 0; pa < phys_avail[0]; pa += PAGE_SIZE) {
+ if (is_dumpable(pa))
+ dump_add_page(pa);
+ }
+
+ /* Calculate dump size. */
+ dumpsize = ptesize;
+ dumpsize += round_page(msgbufp->msg_size);
+ dumpsize += round_page(vm_page_dump_size);
+
+ for (i = 0; i < vm_page_dump_size / sizeof(*vm_page_dump); i++) {
+ bits = vm_page_dump[i];
+ while (bits) {
+ bit = ffs(bits) - 1;
+ pa = (((uint64_t)i * sizeof(*vm_page_dump) * NBBY) +
+ bit) * PAGE_SIZE;
+ /* Clear out undumpable pages now if needed */
+ if (is_dumpable(pa))
+ dumpsize += PAGE_SIZE;
+ else
+ dump_drop_page(pa);
+ bits &= ~(1ul << bit);
+ }
+ }
+
+ dumpsize += PAGE_SIZE;
+
+ /* Determine dump offset on device. */
+ if (di->mediasize < SIZEOF_METADATA + dumpsize + sizeof(kdh) * 2) {
+ error = ENOSPC;
+ goto fail;
+ }
+
+ origdumplo = dumplo = di->mediaoffset + di->mediasize - dumpsize;
+ dumplo -= sizeof(kdh) * 2;
+ progress = dumpsize;
+
+ /* Initialize mdhdr */
+ bzero(&mdhdr, sizeof(mdhdr));
+ strcpy(mdhdr.magic, MINIDUMP_MAGIC);
+ mdhdr.version = MINIDUMP_VERSION;
+ mdhdr.msgbufsize = msgbufp->msg_size;
+ mdhdr.bitmapsize = vm_page_dump_size;
+ mdhdr.ptesize = ptesize;
+ mdhdr.kernbase = VM_MIN_KERNEL_ADDRESS;
+
+ mkdumpheader(&kdh, KERNELDUMPMAGIC, KERNELDUMP_MIPS_VERSION, dumpsize,
+ di->blocksize);
+
+ printf("Physical memory: %ju MB\n",
+ (uintmax_t)ptoa((uintmax_t)physmem) / 1048576);
+ printf("Dumping %llu MB:", (long long)dumpsize >> 20);
+
+ /* Dump leader */
+ error = dump_write(di, &kdh, 0, dumplo, sizeof(kdh));
+ if (error)
+ goto fail;
+ dumplo += sizeof(kdh);
+
+ /* Dump my header */
+ bzero(tmpbuffer, sizeof(tmpbuffer));
+ bcopy(&mdhdr, tmpbuffer, sizeof(mdhdr));
+ error = write_buffer(di, tmpbuffer, PAGE_SIZE);
+ if (error)
+ goto fail;
+
+ /* Dump msgbuf up front */
+ error = write_buffer(di, (char *)msgbufp->msg_ptr,
+ round_page(msgbufp->msg_size));
+ if (error)
+ goto fail;
+
+ /* Dump bitmap */
+ error = write_buffer(di, (char *)vm_page_dump,
+ round_page(vm_page_dump_size));
+ if (error)
+ goto fail;
+
+ /* Dump kernel page table pages */
+ for (va = VM_MIN_KERNEL_ADDRESS; va < kernel_vm_end; va += NBPDR) {
+ pte = pmap_pte(kernel_pmap, va);
+ KASSERT(pte != NULL, ("pte for %jx is NULL", (uintmax_t)va));
+ if (!count) {
+ prev_pte = (vm_offset_t)pte;
+ count++;
+ }
+ else {
+ if ((vm_offset_t)pte == (prev_pte + count * PAGE_SIZE))
+ count++;
+ else {
+ error = write_buffer(di, (char*)prev_pte,
+ count * PAGE_SIZE);
+ if (error)
+ goto fail;
+ count = 1;
+ prev_pte = (vm_offset_t)pte;
+ }
+ }
+ }
+
+ if (count) {
+ error = write_buffer(di, (char*)prev_pte, count * PAGE_SIZE);
+ if (error)
+ goto fail;
+ count = 0;
+ prev_pte = 0;
+ }
+
+ /* Dump memory chunks page by page*/
+ for (i = 0; i < vm_page_dump_size / sizeof(*vm_page_dump); i++) {
+ bits = vm_page_dump[i];
+ while (bits) {
+ bit = ffs(bits) - 1;
+ pa = (((uint64_t)i * sizeof(*vm_page_dump) * NBBY) +
+ bit) * PAGE_SIZE;
+ dump_va = pmap_kenter_temporary(pa, 0);
+ error = write_buffer(di, dump_va, PAGE_SIZE);
+ if (error)
+ goto fail;
+ pmap_kenter_temporary_free(pa);
+ bits &= ~(1ul << bit);
+ }
+ }
+
+ /* Dump trailer */
+ error = dump_write(di, &kdh, 0, dumplo, sizeof(kdh));
+ if (error)
+ goto fail;
+ dumplo += sizeof(kdh);
+
+ /* Signal completion, signoff and exit stage left. */
+ dump_write(di, NULL, 0, 0, 0);
+ printf("\nDump complete\n");
+ return;
+
+fail:
+ if (error < 0)
+ error = -error;
+
+ if (error == ECANCELED)
+ printf("\nDump aborted\n");
+ else if (error == ENOSPC)
+ printf("\nDump failed. Partition too small.\n");
+ else
+ printf("\n** DUMP FAILED (ERROR %d) **\n", error);
+}
Property changes on: trunk/sys/mips/mips/minidump_machdep.c
___________________________________________________________________
Added: svn:eol-style
## -0,0 +1 ##
+native
\ No newline at end of property
Added: svn:keywords
## -0,0 +1 ##
+MidnightBSD=%H
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+text/plain
\ No newline at end of property
Added: trunk/sys/mips/mips/mp_machdep.c
===================================================================
--- trunk/sys/mips/mips/mp_machdep.c (rev 0)
+++ trunk/sys/mips/mips/mp_machdep.c 2018-05-26 21:55:02 UTC (rev 9987)
@@ -0,0 +1,359 @@
+/* $MidnightBSD$ */
+/*-
+ * Copyright (c) 2009 Neelkanth Natu
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ */
+
+#include <sys/cdefs.h>
+__FBSDID("$FreeBSD: stable/10/sys/mips/mips/mp_machdep.c 265606 2014-05-07 20:28:27Z scottl $");
+
+#include <sys/param.h>
+#include <sys/systm.h>
+#include <sys/cpuset.h>
+#include <sys/ktr.h>
+#include <sys/proc.h>
+#include <sys/lock.h>
+#include <sys/malloc.h>
+#include <sys/mutex.h>
+#include <sys/kernel.h>
+#include <sys/pcpu.h>
+#include <sys/smp.h>
+#include <sys/sched.h>
+#include <sys/bus.h>
+
+#include <vm/vm.h>
+#include <vm/pmap.h>
+#include <vm/vm_extern.h>
+#include <vm/vm_kern.h>
+
+#include <machine/clock.h>
+#include <machine/smp.h>
+#include <machine/hwfunc.h>
+#include <machine/intr_machdep.h>
+#include <machine/cache.h>
+#include <machine/tlb.h>
+
+struct pcb stoppcbs[MAXCPU];
+
+static void *dpcpu;
+static struct mtx ap_boot_mtx;
+
+static volatile int aps_ready;
+static volatile int mp_naps;
+
+static void
+ipi_send(struct pcpu *pc, int ipi)
+{
+
+ CTR3(KTR_SMP, "%s: cpu=%d, ipi=%x", __func__, pc->pc_cpuid, ipi);
+
+ atomic_set_32(&pc->pc_pending_ipis, ipi);
+ platform_ipi_send(pc->pc_cpuid);
+
+ CTR1(KTR_SMP, "%s: sent", __func__);
+}
+
+void
+ipi_all_but_self(int ipi)
+{
+ cpuset_t other_cpus;
+
+ other_cpus = all_cpus;
+ CPU_CLR(PCPU_GET(cpuid), &other_cpus);
+ ipi_selected(other_cpus, ipi);
+}
+
+/* Send an IPI to a set of cpus. */
+void
+ipi_selected(cpuset_t cpus, int ipi)
+{
+ struct pcpu *pc;
+
+ STAILQ_FOREACH(pc, &cpuhead, pc_allcpu) {
+ if (CPU_ISSET(pc->pc_cpuid, &cpus)) {
+ CTR3(KTR_SMP, "%s: pc: %p, ipi: %x\n", __func__, pc,
+ ipi);
+ ipi_send(pc, ipi);
+ }
+ }
+}
+
+/* Send an IPI to a specific CPU. */
+void
+ipi_cpu(int cpu, u_int ipi)
+{
+
+ CTR3(KTR_SMP, "%s: cpu: %d, ipi: %x\n", __func__, cpu, ipi);
+ ipi_send(cpuid_to_pcpu[cpu], ipi);
+}
+
+/*
+ * Handle an IPI sent to this processor.
+ */
+static int
+mips_ipi_handler(void *arg)
+{
+ u_int cpu, ipi, ipi_bitmap;
+ int bit;
+
+ cpu = PCPU_GET(cpuid);
+
+ platform_ipi_clear(); /* quiesce the pending ipi interrupt */
+
+ ipi_bitmap = atomic_readandclear_int(PCPU_PTR(pending_ipis));
+ if (ipi_bitmap == 0)
+ return (FILTER_STRAY);
+
+ CTR1(KTR_SMP, "smp_handle_ipi(), ipi_bitmap=%x", ipi_bitmap);
+
+ while ((bit = ffs(ipi_bitmap))) {
+ bit = bit - 1;
+ ipi = 1 << bit;
+ ipi_bitmap &= ~ipi;
+ switch (ipi) {
+ case IPI_RENDEZVOUS:
+ CTR0(KTR_SMP, "IPI_RENDEZVOUS");
+ smp_rendezvous_action();
+ break;
+
+ case IPI_AST:
+ CTR0(KTR_SMP, "IPI_AST");
+ break;
+
+ case IPI_STOP:
+ /*
+ * IPI_STOP_HARD is mapped to IPI_STOP so it is not
+ * necessary to add it in the switch.
+ */
+ CTR0(KTR_SMP, "IPI_STOP or IPI_STOP_HARD");
+
+ savectx(&stoppcbs[cpu]);
+ tlb_save();
+
+ /* Indicate we are stopped */
+ CPU_SET_ATOMIC(cpu, &stopped_cpus);
+
+ /* Wait for restart */
+ while (!CPU_ISSET(cpu, &started_cpus))
+ cpu_spinwait();
+
+ CPU_CLR_ATOMIC(cpu, &started_cpus);
+ CPU_CLR_ATOMIC(cpu, &stopped_cpus);
+ CTR0(KTR_SMP, "IPI_STOP (restart)");
+ break;
+ case IPI_PREEMPT:
+ CTR1(KTR_SMP, "%s: IPI_PREEMPT", __func__);
+ sched_preempt(curthread);
+ break;
+ case IPI_HARDCLOCK:
+ CTR1(KTR_SMP, "%s: IPI_HARDCLOCK", __func__);
+ hardclockintr();
+ break;
+ default:
+ panic("Unknown IPI 0x%0x on cpu %d", ipi, curcpu);
+ }
+ }
+
+ return (FILTER_HANDLED);
+}
+
+static int
+start_ap(int cpuid)
+{
+ int cpus, ms;
+
+ cpus = mp_naps;
+ dpcpu = (void *)kmem_malloc(kernel_arena, DPCPU_SIZE, M_WAITOK | M_ZERO);
+
+ mips_sync();
+
+ if (platform_start_ap(cpuid) != 0)
+ return (-1); /* could not start AP */
+
+ for (ms = 0; ms < 5000; ++ms) {
+ if (mp_naps > cpus)
+ return (0); /* success */
+ else
+ DELAY(1000);
+ }
+
+ return (-2); /* timeout initializing AP */
+}
+
+void
+cpu_mp_setmaxid(void)
+{
+ cpuset_t cpumask;
+ int cpu, last;
+
+ platform_cpu_mask(&cpumask);
+ mp_ncpus = 0;
+ last = 1;
+ while ((cpu = CPU_FFS(&cpumask)) != 0) {
+ last = cpu;
+ cpu--;
+ CPU_CLR(cpu, &cpumask);
+ mp_ncpus++;
+ }
+ if (mp_ncpus <= 0)
+ mp_ncpus = 1;
+
+ mp_maxid = min(last, MAXCPU) - 1;
+}
+
+void
+cpu_mp_announce(void)
+{
+ /* NOTHING */
+}
+
+struct cpu_group *
+cpu_topo(void)
+{
+ return (platform_smp_topo());
+}
+
+int
+cpu_mp_probe(void)
+{
+
+ return (mp_ncpus > 1);
+}
+
+void
+cpu_mp_start(void)
+{
+ int error, cpuid;
+ cpuset_t cpumask;
+
+ mtx_init(&ap_boot_mtx, "ap boot", NULL, MTX_SPIN);
+
+ CPU_ZERO(&all_cpus);
+ platform_cpu_mask(&cpumask);
+
+ while (!CPU_EMPTY(&cpumask)) {
+ cpuid = CPU_FFS(&cpumask) - 1;
+ CPU_CLR(cpuid, &cpumask);
+
+ if (cpuid >= MAXCPU) {
+ printf("cpu_mp_start: ignoring AP #%d.\n", cpuid);
+ continue;
+ }
+
+ if (cpuid != platform_processor_id()) {
+ if ((error = start_ap(cpuid)) != 0) {
+ printf("AP #%d failed to start: %d\n", cpuid, error);
+ continue;
+ }
+ if (bootverbose)
+ printf("AP #%d started!\n", cpuid);
+ }
+ CPU_SET(cpuid, &all_cpus);
+ }
+}
+
+void
+smp_init_secondary(u_int32_t cpuid)
+{
+
+ /* TLB */
+ mips_wr_wired(0);
+ tlb_invalidate_all();
+ mips_wr_wired(VMWIRED_ENTRIES);
+
+ /*
+ * We assume that the L1 cache on the APs is identical to the one
+ * on the BSP.
+ */
+ mips_dcache_wbinv_all();
+ mips_icache_sync_all();
+
+ mips_sync();
+
+ mips_wr_entryhi(0);
+
+ pcpu_init(PCPU_ADDR(cpuid), cpuid, sizeof(struct pcpu));
+ dpcpu_init(dpcpu, cpuid);
+
+ /* The AP has initialized successfully - allow the BSP to proceed */
+ ++mp_naps;
+
+ /* Spin until the BSP is ready to release the APs */
+ while (!aps_ready)
+ ;
+
+ /* Initialize curthread. */
+ KASSERT(PCPU_GET(idlethread) != NULL, ("no idle thread"));
+ PCPU_SET(curthread, PCPU_GET(idlethread));
+
+ mtx_lock_spin(&ap_boot_mtx);
+
+ smp_cpus++;
+
+ CTR1(KTR_SMP, "SMP: AP CPU #%d launched", PCPU_GET(cpuid));
+
+ if (bootverbose)
+ printf("SMP: AP CPU #%d launched.\n", PCPU_GET(cpuid));
+
+ if (smp_cpus == mp_ncpus) {
+ atomic_store_rel_int(&smp_started, 1);
+ }
+
+ mtx_unlock_spin(&ap_boot_mtx);
+
+ while (smp_started == 0)
+ ; /* nothing */
+
+ /* Start per-CPU event timers. */
+ cpu_initclocks_ap();
+
+ /* enter the scheduler */
+ sched_throw(NULL);
+
+ panic("scheduler returned us to %s", __func__);
+ /* NOTREACHED */
+}
+
+static void
+release_aps(void *dummy __unused)
+{
+ int ipi_irq;
+
+ if (mp_ncpus == 1)
+ return;
+
+ /*
+ * IPI handler
+ */
+ ipi_irq = platform_ipi_intrnum();
+ cpu_establish_hardintr("ipi", mips_ipi_handler, NULL, NULL, ipi_irq,
+ INTR_TYPE_MISC | INTR_EXCL, NULL);
+
+ atomic_store_rel_int(&aps_ready, 1);
+
+ while (smp_started == 0)
+ ; /* nothing */
+}
+
+SYSINIT(start_aps, SI_SUB_SMP, SI_ORDER_FIRST, release_aps, NULL);
Property changes on: trunk/sys/mips/mips/mp_machdep.c
___________________________________________________________________
Added: svn:eol-style
## -0,0 +1 ##
+native
\ No newline at end of property
Added: svn:keywords
## -0,0 +1 ##
+MidnightBSD=%H
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+text/plain
\ No newline at end of property
Added: trunk/sys/mips/mips/mpboot.S
===================================================================
--- trunk/sys/mips/mips/mpboot.S (rev 0)
+++ trunk/sys/mips/mips/mpboot.S 2018-05-26 21:55:02 UTC (rev 9987)
@@ -0,0 +1,90 @@
+/* $MidnightBSD$ */
+/*-
+ * Copyright (c) 2010 Neelkanth Natu
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ * $FreeBSD: stable/10/sys/mips/mips/mpboot.S 232630 2012-03-06 23:08:02Z jmallett $
+ */
+
+#include <machine/asm.h>
+#include <machine/cpu.h>
+#include <machine/cpuregs.h>
+
+#include "assym.s"
+
+ .text
+ .set noat
+ .set noreorder
+
+/* XXX move this to a header file */
+#if defined(CPU_CNMIPS)
+#define CLEAR_STATUS \
+ mfc0 a0, MIPS_COP_0_STATUS ;\
+ li a2, (MIPS_SR_KX | MIPS_SR_SX | MIPS_SR_UX) ; \
+ or a0, a0, a2 ; \
+ li a2, ~(MIPS_SR_INT_IE | MIPS_SR_EXL | MIPS_SR_KSU_USER | MIPS_SR_BEV) ; \
+ and a0, a0, a2 ; \
+ mtc0 a0, MIPS_COP_0_STATUS
+#elif defined(__mips_n64)
+#define CLEAR_STATUS \
+ li a0, (MIPS_SR_KX | MIPS_SR_UX) ; \
+ mtc0 a0, MIPS_COP_0_STATUS
+#else
+#define CLEAR_STATUS \
+ mtc0 zero, MIPS_COP_0_STATUS
+#endif
+
+GLOBAL(mpentry)
+ CLEAR_STATUS /* disable interrupts */
+
+ mtc0 zero, MIPS_COP_0_CAUSE /* clear soft interrupts */
+
+ li t0, MIPS_CCA_CACHED /* make sure kseg0 is cached */
+ mtc0 t0, MIPS_COP_0_CONFIG
+ COP0_SYNC
+
+ jal platform_processor_id /* get the processor number */
+ nop
+ move s0, v0
+
+ /*
+ * Initialize stack and call machine startup
+ */
+ PTR_LA sp, _C_LABEL(pcpu_space)
+ addiu sp, (PAGE_SIZE * 2) - CALLFRAME_SIZ
+ sll t0, s0, PAGE_SHIFT + 1
+ addu sp, sp, t0
+
+ /* Zero out old ra and old fp for debugger */
+ sw zero, CALLFRAME_SIZ - 4(sp)
+ sw zero, CALLFRAME_SIZ - 8(sp)
+
+ PTR_LA gp, _C_LABEL(_gp)
+
+ jal platform_init_ap
+ move a0, s0
+ jal smp_init_secondary
+ move a0, s0
+
+ PANIC("AP startup failed!")
Property changes on: trunk/sys/mips/mips/mpboot.S
___________________________________________________________________
Added: svn:eol-style
## -0,0 +1 ##
+native
\ No newline at end of property
Added: svn:keywords
## -0,0 +1 ##
+MidnightBSD=%H
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+text/plain
\ No newline at end of property
Added: trunk/sys/mips/mips/nexus.c
===================================================================
--- trunk/sys/mips/mips/nexus.c (rev 0)
+++ trunk/sys/mips/mips/nexus.c 2018-05-26 21:55:02 UTC (rev 9987)
@@ -0,0 +1,497 @@
+/* $MidnightBSD$ */
+/*-
+ * Copyright 1998 Massachusetts Institute of Technology
+ *
+ * Permission to use, copy, modify, and distribute this software and
+ * its documentation for any purpose and without fee is hereby
+ * granted, provided that both the above copyright notice and this
+ * permission notice appear in all copies, that both the above
+ * copyright notice and this permission notice appear in all
+ * supporting documentation, and that the name of M.I.T. not be used
+ * in advertising or publicity pertaining to distribution of the
+ * software without specific, written prior permission. M.I.T. makes
+ * no representations about the suitability of this software for any
+ * purpose. It is provided "as is" without express or implied
+ * warranty.
+ *
+ * THIS SOFTWARE IS PROVIDED BY M.I.T. ``AS IS''. M.I.T. DISCLAIMS
+ * ALL EXPRESS OR IMPLIED WARRANTIES WITH REGARD TO THIS SOFTWARE,
+ * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT
+ * SHALL M.I.T. BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
+ * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
+ * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ */
+
+/*
+ * This code implements a `root nexus' for MIPS Architecture
+ * machines. The function of the root nexus is to serve as an
+ * attachment point for both processors and buses, and to manage
+ * resources which are common to all of them. In particular,
+ * this code implements the core resource managers for interrupt
+ * requests and memory address space.
+ */
+
+#include <sys/cdefs.h>
+__FBSDID("$FreeBSD: stable/10/sys/mips/mips/nexus.c 266160 2014-05-15 17:30:16Z ian $");
+
+#include <sys/param.h>
+#include <sys/systm.h>
+#include <sys/bus.h>
+#include <sys/kernel.h>
+#include <sys/malloc.h>
+#include <sys/module.h>
+#include <sys/rman.h>
+#include <sys/interrupt.h>
+
+#include <vm/vm.h>
+#include <vm/pmap.h>
+
+#include <machine/bus.h>
+#include <machine/intr_machdep.h>
+#include <machine/pmap.h>
+#include <machine/resource.h>
+#include <machine/vmparam.h>
+
+#include "opt_platform.h"
+
+#undef NEXUS_DEBUG
+#ifdef NEXUS_DEBUG
+#define dprintf printf
+#else
+#define dprintf(x, arg...)
+#endif /* NEXUS_DEBUG */
+
+#define NUM_MIPS_IRQS 6
+
+static MALLOC_DEFINE(M_NEXUSDEV, "nexusdev", "Nexus device");
+
+struct nexus_device {
+ struct resource_list nx_resources;
+};
+
+#define DEVTONX(dev) ((struct nexus_device *)device_get_ivars(dev))
+
+static struct rman irq_rman;
+static struct rman mem_rman;
+
+static struct resource *
+ nexus_alloc_resource(device_t, device_t, int, int *, u_long,
+ u_long, u_long, u_int);
+static device_t nexus_add_child(device_t, u_int, const char *, int);
+static int nexus_attach(device_t);
+static void nexus_delete_resource(device_t, device_t, int, int);
+static struct resource_list *
+ nexus_get_reslist(device_t, device_t);
+static int nexus_get_resource(device_t, device_t, int, int, u_long *,
+ u_long *);
+static int nexus_print_child(device_t, device_t);
+static int nexus_print_all_resources(device_t dev);
+static int nexus_probe(device_t);
+static int nexus_release_resource(device_t, device_t, int, int,
+ struct resource *);
+static int nexus_set_resource(device_t, device_t, int, int, u_long,
+ u_long);
+static int nexus_activate_resource(device_t, device_t, int, int,
+ struct resource *);
+static int nexus_deactivate_resource(device_t, device_t, int, int,
+ struct resource *);
+static void nexus_hinted_child(device_t, const char *, int);
+static int nexus_setup_intr(device_t dev, device_t child,
+ struct resource *res, int flags, driver_filter_t *filt,
+ driver_intr_t *intr, void *arg, void **cookiep);
+static int nexus_teardown_intr(device_t, device_t, struct resource *,
+ void *);
+
+static device_method_t nexus_methods[] = {
+ /* Device interface */
+ DEVMETHOD(device_probe, nexus_probe),
+ DEVMETHOD(device_attach, nexus_attach),
+
+ /* Bus interface */
+ DEVMETHOD(bus_add_child, nexus_add_child),
+ DEVMETHOD(bus_alloc_resource, nexus_alloc_resource),
+ DEVMETHOD(bus_delete_resource, nexus_delete_resource),
+ DEVMETHOD(bus_get_resource, nexus_get_resource),
+ DEVMETHOD(bus_get_resource_list, nexus_get_reslist),
+ DEVMETHOD(bus_print_child, nexus_print_child),
+ DEVMETHOD(bus_release_resource, nexus_release_resource),
+ DEVMETHOD(bus_set_resource, nexus_set_resource),
+ DEVMETHOD(bus_setup_intr, nexus_setup_intr),
+ DEVMETHOD(bus_teardown_intr, nexus_teardown_intr),
+ DEVMETHOD(bus_activate_resource,nexus_activate_resource),
+ DEVMETHOD(bus_deactivate_resource, nexus_deactivate_resource),
+ DEVMETHOD(bus_hinted_child, nexus_hinted_child),
+
+ { 0, 0 }
+};
+
+static driver_t nexus_driver = {
+ "nexus",
+ nexus_methods,
+ 1 /* no softc */
+};
+static devclass_t nexus_devclass;
+
+static int
+nexus_probe(device_t dev)
+{
+
+ device_set_desc(dev, "MIPS32 root nexus");
+
+ irq_rman.rm_start = 0;
+ irq_rman.rm_end = NUM_MIPS_IRQS - 1;
+ irq_rman.rm_type = RMAN_ARRAY;
+ irq_rman.rm_descr = "Hardware IRQs";
+ if (rman_init(&irq_rman) != 0 ||
+ rman_manage_region(&irq_rman, 0, NUM_MIPS_IRQS - 1) != 0) {
+ panic("%s: irq_rman", __func__);
+ }
+
+ mem_rman.rm_start = 0;
+ mem_rman.rm_end = ~0ul;
+ mem_rman.rm_type = RMAN_ARRAY;
+ mem_rman.rm_descr = "Memory addresses";
+ if (rman_init(&mem_rman) != 0 ||
+ rman_manage_region(&mem_rman, 0, ~0) != 0) {
+ panic("%s: mem_rman", __func__);
+ }
+
+ return (0);
+}
+
+static int
+nexus_attach(device_t dev)
+{
+
+ bus_generic_probe(dev);
+ bus_enumerate_hinted_children(dev);
+ bus_generic_attach(dev);
+
+ return (0);
+}
+
+static int
+nexus_print_child(device_t bus, device_t child)
+{
+ int retval = 0;
+
+ retval += bus_print_child_header(bus, child);
+ retval += nexus_print_all_resources(child);
+ if (device_get_flags(child))
+ retval += printf(" flags %#x", device_get_flags(child));
+ retval += printf(" on %s\n", device_get_nameunit(bus));
+
+ return (retval);
+}
+
+static int
+nexus_print_all_resources(device_t dev)
+{
+ struct nexus_device *ndev = DEVTONX(dev);
+ struct resource_list *rl = &ndev->nx_resources;
+ int retval = 0;
+
+ if (STAILQ_FIRST(rl))
+ retval += printf(" at");
+
+ retval += resource_list_print_type(rl, "mem", SYS_RES_MEMORY, "%#lx");
+ retval += resource_list_print_type(rl, "irq", SYS_RES_IRQ, "%ld");
+
+ return (retval);
+}
+
+static device_t
+nexus_add_child(device_t bus, u_int order, const char *name, int unit)
+{
+ device_t child;
+ struct nexus_device *ndev;
+
+ ndev = malloc(sizeof(struct nexus_device), M_NEXUSDEV, M_NOWAIT|M_ZERO);
+ if (!ndev)
+ return (0);
+ resource_list_init(&ndev->nx_resources);
+
+ child = device_add_child_ordered(bus, order, name, unit);
+ if (child == NULL) {
+ device_printf(bus, "failed to add child: %s%d\n", name, unit);
+ return (0);
+ }
+
+ /* should we free this in nexus_child_detached? */
+ device_set_ivars(child, ndev);
+
+ return (child);
+}
+
+/*
+ * Allocate a resource on behalf of child. NB: child is usually going to be a
+ * child of one of our descendants, not a direct child of nexus0.
+ * (Exceptions include footbridge.)
+ */
+static struct resource *
+nexus_alloc_resource(device_t bus, device_t child, int type, int *rid,
+ u_long start, u_long end, u_long count, u_int flags)
+{
+ struct nexus_device *ndev = DEVTONX(child);
+ struct resource *rv;
+ struct resource_list_entry *rle;
+ struct rman *rm;
+ int isdefault, needactivate, passthrough;
+
+ dprintf("%s: entry (%p, %p, %d, %p, %p, %p, %ld, %d)\n",
+ __func__, bus, child, type, rid, (void *)(intptr_t)start,
+ (void *)(intptr_t)end, count, flags);
+ dprintf("%s: requested rid is %d\n", __func__, *rid);
+
+ isdefault = (start == 0UL && end == ~0UL && count == 1);
+ needactivate = flags & RF_ACTIVE;
+ passthrough = (device_get_parent(child) != bus);
+ rle = NULL;
+
+ /*
+ * If this is an allocation of the "default" range for a given RID,
+ * and we know what the resources for this device are (ie. they aren't
+ * maintained by a child bus), then work out the start/end values.
+ */
+ if (isdefault) {
+ rle = resource_list_find(&ndev->nx_resources, type, *rid);
+ if (rle == NULL)
+ return (NULL);
+ if (rle->res != NULL) {
+ panic("%s: resource entry is busy", __func__);
+ }
+ start = rle->start;
+ end = rle->end;
+ count = rle->count;
+ }
+
+ switch (type) {
+ case SYS_RES_IRQ:
+ rm = &irq_rman;
+ break;
+ case SYS_RES_MEMORY:
+ rm = &mem_rman;
+ break;
+ default:
+ printf("%s: unknown resource type %d\n", __func__, type);
+ return (0);
+ }
+
+ rv = rman_reserve_resource(rm, start, end, count, flags, child);
+ if (rv == 0) {
+ printf("%s: could not reserve resource for %s\n", __func__,
+ device_get_nameunit(child));
+ return (0);
+ }
+
+ rman_set_rid(rv, *rid);
+
+ if (needactivate) {
+ if (bus_activate_resource(child, type, *rid, rv)) {
+ printf("%s: could not activate resource\n", __func__);
+ rman_release_resource(rv);
+ return (0);
+ }
+ }
+
+ return (rv);
+}
+
+static struct resource_list *
+nexus_get_reslist(device_t dev, device_t child)
+{
+ struct nexus_device *ndev = DEVTONX(child);
+
+ return (&ndev->nx_resources);
+}
+
+static int
+nexus_set_resource(device_t dev, device_t child, int type, int rid,
+ u_long start, u_long count)
+{
+ struct nexus_device *ndev = DEVTONX(child);
+ struct resource_list *rl = &ndev->nx_resources;
+ struct resource_list_entry *rle;
+
+ dprintf("%s: entry (%p, %p, %d, %d, %p, %ld)\n",
+ __func__, dev, child, type, rid, (void *)(intptr_t)start, count);
+
+ rle = resource_list_add(rl, type, rid, start, start + count - 1,
+ count);
+ if (rle == NULL)
+ return (ENXIO);
+
+ return (0);
+}
+
+static int
+nexus_get_resource(device_t dev, device_t child, int type, int rid,
+ u_long *startp, u_long *countp)
+{
+ struct nexus_device *ndev = DEVTONX(child);
+ struct resource_list *rl = &ndev->nx_resources;
+ struct resource_list_entry *rle;
+
+ rle = resource_list_find(rl, type, rid);
+ if (!rle)
+ return(ENOENT);
+ if (startp)
+ *startp = rle->start;
+ if (countp)
+ *countp = rle->count;
+ return (0);
+}
+
+static void
+nexus_delete_resource(device_t dev, device_t child, int type, int rid)
+{
+ struct nexus_device *ndev = DEVTONX(child);
+ struct resource_list *rl = &ndev->nx_resources;
+
+ dprintf("%s: entry\n", __func__);
+
+ resource_list_delete(rl, type, rid);
+}
+
+static int
+nexus_release_resource(device_t bus, device_t child, int type, int rid,
+ struct resource *r)
+{
+ dprintf("%s: entry\n", __func__);
+
+ if (rman_get_flags(r) & RF_ACTIVE) {
+ int error = bus_deactivate_resource(child, type, rid, r);
+ if (error)
+ return error;
+ }
+
+ return (rman_release_resource(r));
+}
+
+static int
+nexus_activate_resource(device_t bus, device_t child, int type, int rid,
+ struct resource *r)
+{
+ void *vaddr;
+ vm_paddr_t paddr;
+ vm_size_t psize;
+
+ /*
+ * If this is a memory resource, use pmap_mapdev to map it.
+ */
+ if (type == SYS_RES_MEMORY || type == SYS_RES_IOPORT) {
+ paddr = rman_get_start(r);
+ psize = rman_get_size(r);
+ vaddr = pmap_mapdev(paddr, psize);
+
+ rman_set_virtual(r, vaddr);
+ rman_set_bustag(r, mips_bus_space_generic);
+ rman_set_bushandle(r, (bus_space_handle_t)(uintptr_t)vaddr);
+ }
+
+ return (rman_activate_resource(r));
+}
+
+static int
+nexus_deactivate_resource(device_t bus, device_t child, int type, int rid,
+ struct resource *r)
+{
+ vm_offset_t va;
+
+ if (type == SYS_RES_MEMORY) {
+ va = (vm_offset_t)rman_get_virtual(r);
+ pmap_unmapdev(va, rman_get_size(r));
+ }
+
+ return (rman_deactivate_resource(r));
+}
+
+static int
+nexus_setup_intr(device_t dev, device_t child, struct resource *res, int flags,
+ driver_filter_t *filt, driver_intr_t *intr, void *arg, void **cookiep)
+{
+ register_t s;
+ int irq;
+
+ s = intr_disable();
+ irq = rman_get_start(res);
+ if (irq >= NUM_MIPS_IRQS) {
+ intr_restore(s);
+ return (0);
+ }
+
+ cpu_establish_hardintr(device_get_nameunit(child), filt, intr, arg,
+ irq, flags, cookiep);
+ intr_restore(s);
+ return (0);
+}
+
+static int
+nexus_teardown_intr(device_t dev, device_t child, struct resource *r, void *ih)
+{
+
+ printf("Unimplemented %s at %s:%d\n", __func__, __FILE__, __LINE__);
+ return (0);
+}
+
+static void
+nexus_hinted_child(device_t bus, const char *dname, int dunit)
+{
+ device_t child;
+ long maddr;
+ int msize;
+ int order;
+ int result;
+ int irq;
+ int mem_hints_count;
+
+ if ((resource_int_value(dname, dunit, "order", &order)) != 0)
+ order = 1000;
+ child = BUS_ADD_CHILD(bus, order, dname, dunit);
+ if (child == NULL)
+ return;
+
+ /*
+ * Set hard-wired resources for hinted child using
+ * specific RIDs.
+ */
+ mem_hints_count = 0;
+ if (resource_long_value(dname, dunit, "maddr", &maddr) == 0)
+ mem_hints_count++;
+ if (resource_int_value(dname, dunit, "msize", &msize) == 0)
+ mem_hints_count++;
+
+ /* check if all info for mem resource has been provided */
+ if ((mem_hints_count > 0) && (mem_hints_count < 2)) {
+ printf("Either maddr or msize hint is missing for %s%d\n",
+ dname, dunit);
+ }
+ else if (mem_hints_count) {
+ dprintf("%s: discovered hinted child %s at maddr %p(%d)\n",
+ __func__, device_get_nameunit(child),
+ (void *)(intptr_t)maddr, msize);
+
+ result = bus_set_resource(child, SYS_RES_MEMORY, 0, maddr,
+ msize);
+ if (result != 0) {
+ device_printf(bus,
+ "warning: bus_set_resource() failed\n");
+ }
+ }
+
+ if (resource_int_value(dname, dunit, "irq", &irq) == 0) {
+ result = bus_set_resource(child, SYS_RES_IRQ, 0, irq, 1);
+ if (result != 0)
+ device_printf(bus,
+ "warning: bus_set_resource() failed\n");
+ }
+}
+
+DRIVER_MODULE(nexus, root, nexus_driver, nexus_devclass, 0, 0);
Property changes on: trunk/sys/mips/mips/nexus.c
___________________________________________________________________
Added: svn:eol-style
## -0,0 +1 ##
+native
\ No newline at end of property
Added: svn:keywords
## -0,0 +1 ##
+MidnightBSD=%H
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+text/plain
\ No newline at end of property
Added: trunk/sys/mips/mips/octeon_cop2.c
===================================================================
--- trunk/sys/mips/mips/octeon_cop2.c (rev 0)
+++ trunk/sys/mips/mips/octeon_cop2.c 2018-05-26 21:55:02 UTC (rev 9987)
@@ -0,0 +1,63 @@
+/* $MidnightBSD$ */
+/*-
+ * Copyright (c) 2011, Oleksandr Tymoshenko <gonzo at FreeBSD.org>
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice unmodified, this list of conditions, and the following
+ * disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ */
+
+#include <sys/cdefs.h>
+__FBSDID("$FreeBSD: stable/10/sys/mips/mips/octeon_cop2.c 229677 2012-01-06 01:23:26Z gonzo $");
+
+#include <sys/types.h>
+#include <sys/systm.h>
+#include <sys/param.h>
+#include <sys/kernel.h>
+#include <vm/uma.h>
+
+#include <machine/octeon_cop2.h>
+
+static uma_zone_t ctxzone;
+
+static void
+octeon_cop2_init(void* dummy)
+{
+ printf("Create COP2 context zone\n");
+ ctxzone = uma_zcreate("COP2 context",
+ sizeof(struct octeon_cop2_state),
+ NULL, NULL, NULL, NULL, 8, 0);
+}
+
+struct octeon_cop2_state *
+octeon_cop2_alloc_ctx()
+{
+ return uma_zalloc(ctxzone, M_NOWAIT);
+}
+
+void
+octeon_cop2_free_ctx(struct octeon_cop2_state *ctx)
+{
+ uma_zfree(ctxzone, ctx);
+}
+
+SYSINIT(octeon_cop2, SI_SUB_CPU, SI_ORDER_FIRST, octeon_cop2_init, NULL);
Property changes on: trunk/sys/mips/mips/octeon_cop2.c
___________________________________________________________________
Added: svn:eol-style
## -0,0 +1 ##
+native
\ No newline at end of property
Added: svn:keywords
## -0,0 +1 ##
+MidnightBSD=%H
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+text/plain
\ No newline at end of property
Added: trunk/sys/mips/mips/octeon_cop2_swtch.S
===================================================================
--- trunk/sys/mips/mips/octeon_cop2_swtch.S (rev 0)
+++ trunk/sys/mips/mips/octeon_cop2_swtch.S 2018-05-26 21:55:02 UTC (rev 9987)
@@ -0,0 +1,247 @@
+/* $MidnightBSD$ */
+/*-
+ * Copyright (c) 2011 Oleksandr Tymoshenko
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ * $FreeBSD: stable/10/sys/mips/mips/octeon_cop2_swtch.S 229677 2012-01-06 01:23:26Z gonzo $
+ */
+
+#include <machine/asm.h>
+#include <machine/cpuregs.h>
+#include <machine/octeon_cop2.h>
+
+#include "assym.s"
+
+.set noreorder
+
+#define SAVE_COP2_REGISTER(reg) \
+ dmfc2 t1, reg; sd t1, reg##_OFFSET(a0)
+
+
+#define RESTORE_COP2_REGISTER(reg) \
+ ld t1, reg##_OFFSET(a0); dmtc2 t1, reg##_SET
+
+LEAF(octeon_cop2_save)
+
+ /* save original cop2 status in t2*/
+ mfc0 t2, MIPS_COP_0_STATUS
+ or t0, t2, MIPS_SR_COP_2_BIT
+ and t0, t0, ~MIPS_SR_INT_IE
+ mtc0 t0, MIPS_COP_0_STATUS
+
+ /* Get CvmCtl register */
+ dmfc0 t0, $9, 7
+
+ /* CRC state */
+ SAVE_COP2_REGISTER(COP2_CRC_IV)
+ SAVE_COP2_REGISTER(COP2_CRC_LENGTH)
+ SAVE_COP2_REGISTER(COP2_CRC_POLY)
+
+ /* if CvmCtl[NODFA_CP2] -> save_nodfa */
+ bbit1 t0, 28, save_nodfa
+ nop
+
+ /* LLM state */
+ SAVE_COP2_REGISTER(COP2_LLM_DAT0)
+ SAVE_COP2_REGISTER(COP2_LLM_DAT1)
+
+save_nodfa:
+ /* crypto stuff is irrelevant if CvmCtl[NOCRYPTO] */
+ bbit1 t0, 26, save_done
+ nop
+
+ SAVE_COP2_REGISTER(COP2_3DES_IV)
+ SAVE_COP2_REGISTER(COP2_3DES_KEY0)
+ SAVE_COP2_REGISTER(COP2_3DES_KEY1)
+ SAVE_COP2_REGISTER(COP2_3DES_KEY2)
+ SAVE_COP2_REGISTER(COP2_3DES_RESULT)
+
+ SAVE_COP2_REGISTER(COP2_AES_INP0)
+ SAVE_COP2_REGISTER(COP2_AES_IV0)
+ SAVE_COP2_REGISTER(COP2_AES_IV1)
+ SAVE_COP2_REGISTER(COP2_AES_KEY0)
+ SAVE_COP2_REGISTER(COP2_AES_KEY1)
+ SAVE_COP2_REGISTER(COP2_AES_KEY2)
+ SAVE_COP2_REGISTER(COP2_AES_KEY3)
+ SAVE_COP2_REGISTER(COP2_AES_KEYLEN)
+ SAVE_COP2_REGISTER(COP2_AES_RESULT0)
+ SAVE_COP2_REGISTER(COP2_AES_RESULT1)
+
+ dmfc0 t0, $15
+ li t1, 0x000d0000 /* Octeon Pass1 */
+ beq t0, t1, save_pass1
+ nop
+
+ SAVE_COP2_REGISTER(COP2_HSH_DATW0)
+ SAVE_COP2_REGISTER(COP2_HSH_DATW1)
+ SAVE_COP2_REGISTER(COP2_HSH_DATW2)
+ SAVE_COP2_REGISTER(COP2_HSH_DATW3)
+ SAVE_COP2_REGISTER(COP2_HSH_DATW4)
+ SAVE_COP2_REGISTER(COP2_HSH_DATW5)
+ SAVE_COP2_REGISTER(COP2_HSH_DATW6)
+ SAVE_COP2_REGISTER(COP2_HSH_DATW7)
+ SAVE_COP2_REGISTER(COP2_HSH_DATW8)
+ SAVE_COP2_REGISTER(COP2_HSH_DATW9)
+ SAVE_COP2_REGISTER(COP2_HSH_DATW10)
+ SAVE_COP2_REGISTER(COP2_HSH_DATW11)
+ SAVE_COP2_REGISTER(COP2_HSH_DATW12)
+ SAVE_COP2_REGISTER(COP2_HSH_DATW13)
+ SAVE_COP2_REGISTER(COP2_HSH_DATW14)
+ SAVE_COP2_REGISTER(COP2_HSH_IVW0)
+ SAVE_COP2_REGISTER(COP2_HSH_IVW1)
+ SAVE_COP2_REGISTER(COP2_HSH_IVW2)
+ SAVE_COP2_REGISTER(COP2_HSH_IVW3)
+ SAVE_COP2_REGISTER(COP2_HSH_IVW4)
+ SAVE_COP2_REGISTER(COP2_HSH_IVW5)
+ SAVE_COP2_REGISTER(COP2_HSH_IVW6)
+ SAVE_COP2_REGISTER(COP2_HSH_IVW7)
+ SAVE_COP2_REGISTER(COP2_GFM_MULT0)
+ SAVE_COP2_REGISTER(COP2_GFM_MULT1)
+ SAVE_COP2_REGISTER(COP2_GFM_POLY)
+ SAVE_COP2_REGISTER(COP2_GFM_RESULT0)
+ SAVE_COP2_REGISTER(COP2_GFM_RESULT1)
+ /* restore saved COP2 status */
+ mtc0 t2, MIPS_COP_0_STATUS
+ jr ra
+ nop
+
+save_pass1:
+ SAVE_COP2_REGISTER(COP2_HSH_DATW0_PASS1)
+ SAVE_COP2_REGISTER(COP2_HSH_DATW1_PASS1)
+ SAVE_COP2_REGISTER(COP2_HSH_DATW2_PASS1)
+ SAVE_COP2_REGISTER(COP2_HSH_DATW3_PASS1)
+ SAVE_COP2_REGISTER(COP2_HSH_DATW4_PASS1)
+ SAVE_COP2_REGISTER(COP2_HSH_DATW5_PASS1)
+ SAVE_COP2_REGISTER(COP2_HSH_DATW6_PASS1)
+ SAVE_COP2_REGISTER(COP2_HSH_IVW0_PASS1)
+ SAVE_COP2_REGISTER(COP2_HSH_IVW1_PASS1)
+ SAVE_COP2_REGISTER(COP2_HSH_IVW2_PASS1)
+
+save_done:
+ /* restore saved COP2 status */
+ mtc0 t2, MIPS_COP_0_STATUS
+ jr ra
+ nop
+END(octeon_cop2_save)
+
+LEAF(octeon_cop2_restore)
+ /* save original cop2 status in t2*/
+ mfc0 t2, MIPS_COP_0_STATUS
+ or t0, t2, MIPS_SR_COP_2_BIT
+ and t0, t0, ~MIPS_SR_INT_IE
+ mtc0 t0, MIPS_COP_0_STATUS
+ /* Get CvmCtl register */
+ dmfc0 t0, $9, 7
+
+ /* CRC state */
+ RESTORE_COP2_REGISTER(COP2_CRC_IV)
+ RESTORE_COP2_REGISTER(COP2_CRC_LENGTH)
+ RESTORE_COP2_REGISTER(COP2_CRC_POLY)
+
+ /* if CvmCtl[NODFA_CP2] -> save_nodfa */
+ bbit1 t0, 28, restore_nodfa
+ nop
+
+ /* LLM state */
+ RESTORE_COP2_REGISTER(COP2_LLM_DAT0)
+ RESTORE_COP2_REGISTER(COP2_LLM_DAT1)
+
+restore_nodfa:
+ /* crypto stuff is irrelevant if CvmCtl[NOCRYPTO] */
+ bbit1 t0, 26, restore_done
+ nop
+
+ RESTORE_COP2_REGISTER(COP2_3DES_IV)
+ RESTORE_COP2_REGISTER(COP2_3DES_KEY0)
+ RESTORE_COP2_REGISTER(COP2_3DES_KEY1)
+ RESTORE_COP2_REGISTER(COP2_3DES_KEY2)
+ RESTORE_COP2_REGISTER(COP2_3DES_RESULT)
+
+ RESTORE_COP2_REGISTER(COP2_AES_INP0)
+ RESTORE_COP2_REGISTER(COP2_AES_IV0)
+ RESTORE_COP2_REGISTER(COP2_AES_IV1)
+ RESTORE_COP2_REGISTER(COP2_AES_KEY0)
+ RESTORE_COP2_REGISTER(COP2_AES_KEY1)
+ RESTORE_COP2_REGISTER(COP2_AES_KEY2)
+ RESTORE_COP2_REGISTER(COP2_AES_KEY3)
+ RESTORE_COP2_REGISTER(COP2_AES_KEYLEN)
+ RESTORE_COP2_REGISTER(COP2_AES_RESULT0)
+ RESTORE_COP2_REGISTER(COP2_AES_RESULT1)
+
+ dmfc0 t0, $15
+ li t1, 0x000d0000 /* Octeon Pass1 */
+ beq t0, t1, restore_pass1
+ nop
+
+ RESTORE_COP2_REGISTER(COP2_HSH_DATW0)
+ RESTORE_COP2_REGISTER(COP2_HSH_DATW1)
+ RESTORE_COP2_REGISTER(COP2_HSH_DATW2)
+ RESTORE_COP2_REGISTER(COP2_HSH_DATW3)
+ RESTORE_COP2_REGISTER(COP2_HSH_DATW4)
+ RESTORE_COP2_REGISTER(COP2_HSH_DATW5)
+ RESTORE_COP2_REGISTER(COP2_HSH_DATW6)
+ RESTORE_COP2_REGISTER(COP2_HSH_DATW7)
+ RESTORE_COP2_REGISTER(COP2_HSH_DATW8)
+ RESTORE_COP2_REGISTER(COP2_HSH_DATW9)
+ RESTORE_COP2_REGISTER(COP2_HSH_DATW10)
+ RESTORE_COP2_REGISTER(COP2_HSH_DATW11)
+ RESTORE_COP2_REGISTER(COP2_HSH_DATW12)
+ RESTORE_COP2_REGISTER(COP2_HSH_DATW13)
+ RESTORE_COP2_REGISTER(COP2_HSH_DATW14)
+ RESTORE_COP2_REGISTER(COP2_HSH_IVW0)
+ RESTORE_COP2_REGISTER(COP2_HSH_IVW1)
+ RESTORE_COP2_REGISTER(COP2_HSH_IVW2)
+ RESTORE_COP2_REGISTER(COP2_HSH_IVW3)
+ RESTORE_COP2_REGISTER(COP2_HSH_IVW4)
+ RESTORE_COP2_REGISTER(COP2_HSH_IVW5)
+ RESTORE_COP2_REGISTER(COP2_HSH_IVW6)
+ RESTORE_COP2_REGISTER(COP2_HSH_IVW7)
+ RESTORE_COP2_REGISTER(COP2_GFM_MULT0)
+ RESTORE_COP2_REGISTER(COP2_GFM_MULT1)
+ RESTORE_COP2_REGISTER(COP2_GFM_POLY)
+ RESTORE_COP2_REGISTER(COP2_GFM_RESULT0)
+ RESTORE_COP2_REGISTER(COP2_GFM_RESULT1)
+ /* restore saved COP2 status */
+ mtc0 t2, MIPS_COP_0_STATUS
+ jr ra
+ nop
+
+restore_pass1:
+ RESTORE_COP2_REGISTER(COP2_HSH_DATW0_PASS1)
+ RESTORE_COP2_REGISTER(COP2_HSH_DATW1_PASS1)
+ RESTORE_COP2_REGISTER(COP2_HSH_DATW2_PASS1)
+ RESTORE_COP2_REGISTER(COP2_HSH_DATW3_PASS1)
+ RESTORE_COP2_REGISTER(COP2_HSH_DATW4_PASS1)
+ RESTORE_COP2_REGISTER(COP2_HSH_DATW5_PASS1)
+ RESTORE_COP2_REGISTER(COP2_HSH_DATW6_PASS1)
+ RESTORE_COP2_REGISTER(COP2_HSH_IVW0_PASS1)
+ RESTORE_COP2_REGISTER(COP2_HSH_IVW1_PASS1)
+ RESTORE_COP2_REGISTER(COP2_HSH_IVW2_PASS1)
+
+restore_done:
+ /* restore saved COP2 status */
+ mtc0 t2, MIPS_COP_0_STATUS
+ jr ra
+ nop
+END(octeon_cop2_restore)
Property changes on: trunk/sys/mips/mips/octeon_cop2_swtch.S
___________________________________________________________________
Added: svn:eol-style
## -0,0 +1 ##
+native
\ No newline at end of property
Added: svn:keywords
## -0,0 +1 ##
+MidnightBSD=%H
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+text/plain
\ No newline at end of property
Added: trunk/sys/mips/mips/pm_machdep.c
===================================================================
--- trunk/sys/mips/mips/pm_machdep.c (rev 0)
+++ trunk/sys/mips/mips/pm_machdep.c 2018-05-26 21:55:02 UTC (rev 9987)
@@ -0,0 +1,538 @@
+/* $MidnightBSD$ */
+/*-
+ * Copyright (c) 1992 Terrence R. Lambert.
+ * Copyright (c) 1982, 1987, 1990 The Regents of the University of California.
+ * All rights reserved.
+ *
+ * This code is derived from software contributed to Berkeley by
+ * William Jolitz.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * 4. Neither the name of the University nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ * from: @(#)machdep.c 7.4 (Berkeley) 6/3/91
+ * from: src/sys/i386/i386/machdep.c,v 1.385.2.3 2000/05/10 02:04:46 obrien
+ * JNPR: pm_machdep.c,v 1.9.2.1 2007/08/16 15:59:10 girish
+ */
+
+#include <sys/cdefs.h>
+__FBSDID("$FreeBSD: stable/10/sys/mips/mips/pm_machdep.c 293581 2016-01-09 17:39:41Z dchagin $");
+
+#include "opt_compat.h"
+
+#include <sys/types.h>
+#include <sys/param.h>
+#include <sys/systm.h>
+#include <sys/sysent.h>
+#include <sys/proc.h>
+#include <sys/signalvar.h>
+#include <sys/exec.h>
+#include <sys/imgact.h>
+#include <sys/ucontext.h>
+#include <sys/lock.h>
+#include <sys/syscallsubr.h>
+#include <sys/sysproto.h>
+#include <sys/ptrace.h>
+#include <sys/syslog.h>
+#include <vm/vm.h>
+#include <vm/pmap.h>
+#include <vm/vm_map.h>
+#include <vm/vm_extern.h>
+#include <sys/user.h>
+#include <sys/uio.h>
+#include <machine/reg.h>
+#include <machine/md_var.h>
+#include <machine/sigframe.h>
+#include <machine/vmparam.h>
+#include <sys/vnode.h>
+#include <fs/pseudofs/pseudofs.h>
+#include <fs/procfs/procfs.h>
+
+#define UCONTEXT_MAGIC 0xACEDBADE
+
+/*
+ * Send an interrupt to process.
+ *
+ * Stack is set up to allow sigcode stored
+ * at top to call routine, followed by kcall
+ * to sigreturn routine below. After sigreturn
+ * resets the signal mask, the stack, and the
+ * frame pointer, it returns to the user
+ * specified pc, psl.
+ */
+void
+sendsig(sig_t catcher, ksiginfo_t *ksi, sigset_t *mask)
+{
+ struct proc *p;
+ struct thread *td;
+ struct trapframe *regs;
+ struct sigacts *psp;
+ struct sigframe sf, *sfp;
+ int sig;
+ int oonstack;
+
+ td = curthread;
+ p = td->td_proc;
+ PROC_LOCK_ASSERT(p, MA_OWNED);
+ sig = ksi->ksi_signo;
+ psp = p->p_sigacts;
+ mtx_assert(&psp->ps_mtx, MA_OWNED);
+
+ regs = td->td_frame;
+ oonstack = sigonstack(regs->sp);
+
+ /* save user context */
+ bzero(&sf, sizeof(struct sigframe));
+ sf.sf_uc.uc_sigmask = *mask;
+ sf.sf_uc.uc_stack = td->td_sigstk;
+ sf.sf_uc.uc_mcontext.mc_onstack = (oonstack) ? 1 : 0;
+ sf.sf_uc.uc_mcontext.mc_pc = regs->pc;
+ sf.sf_uc.uc_mcontext.mullo = regs->mullo;
+ sf.sf_uc.uc_mcontext.mulhi = regs->mulhi;
+ sf.sf_uc.uc_mcontext.mc_tls = td->td_md.md_tls;
+ sf.sf_uc.uc_mcontext.mc_regs[0] = UCONTEXT_MAGIC; /* magic number */
+ bcopy((void *)®s->ast, (void *)&sf.sf_uc.uc_mcontext.mc_regs[1],
+ sizeof(sf.sf_uc.uc_mcontext.mc_regs) - sizeof(register_t));
+ sf.sf_uc.uc_mcontext.mc_fpused = td->td_md.md_flags & MDTD_FPUSED;
+ if (sf.sf_uc.uc_mcontext.mc_fpused) {
+ /* if FPU has current state, save it first */
+ if (td == PCPU_GET(fpcurthread))
+ MipsSaveCurFPState(td);
+ bcopy((void *)&td->td_frame->f0,
+ (void *)sf.sf_uc.uc_mcontext.mc_fpregs,
+ sizeof(sf.sf_uc.uc_mcontext.mc_fpregs));
+ }
+
+ /* Allocate and validate space for the signal handler context. */
+ if ((td->td_pflags & TDP_ALTSTACK) != 0 && !oonstack &&
+ SIGISMEMBER(psp->ps_sigonstack, sig)) {
+ sfp = (struct sigframe *)((vm_offset_t)(td->td_sigstk.ss_sp +
+ td->td_sigstk.ss_size - sizeof(struct sigframe))
+ & ~(sizeof(__int64_t) - 1));
+ } else
+ sfp = (struct sigframe *)((vm_offset_t)(regs->sp -
+ sizeof(struct sigframe)) & ~(sizeof(__int64_t) - 1));
+
+ /* Build the argument list for the signal handler. */
+ regs->a0 = sig;
+ regs->a2 = (register_t)(intptr_t)&sfp->sf_uc;
+ if (SIGISMEMBER(psp->ps_siginfo, sig)) {
+ /* Signal handler installed with SA_SIGINFO. */
+ regs->a1 = (register_t)(intptr_t)&sfp->sf_si;
+ /* sf.sf_ahu.sf_action = (__siginfohandler_t *)catcher; */
+
+ /* fill siginfo structure */
+ sf.sf_si.si_signo = sig;
+ sf.sf_si.si_code = ksi->ksi_code;
+ sf.sf_si.si_addr = (void*)(intptr_t)regs->badvaddr;
+ } else {
+ /* Old FreeBSD-style arguments. */
+ regs->a1 = ksi->ksi_code;
+ regs->a3 = regs->badvaddr;
+ /* sf.sf_ahu.sf_handler = catcher; */
+ }
+
+ mtx_unlock(&psp->ps_mtx);
+ PROC_UNLOCK(p);
+
+ /*
+ * Copy the sigframe out to the user's stack.
+ */
+ if (copyout(&sf, sfp, sizeof(struct sigframe)) != 0) {
+ /*
+ * Something is wrong with the stack pointer.
+ * ...Kill the process.
+ */
+ PROC_LOCK(p);
+ sigexit(td, SIGILL);
+ }
+
+ regs->pc = (register_t)(intptr_t)catcher;
+ regs->t9 = (register_t)(intptr_t)catcher;
+ regs->sp = (register_t)(intptr_t)sfp;
+ /*
+ * Signal trampoline code is at base of user stack.
+ */
+ regs->ra = (register_t)(intptr_t)PS_STRINGS - *(p->p_sysent->sv_szsigcode);
+ PROC_LOCK(p);
+ mtx_lock(&psp->ps_mtx);
+}
+
+#ifdef GONE_IN_7
+/*
+ * Build siginfo_t for SA thread
+ */
+void
+cpu_thread_siginfo(int sig, u_long code, siginfo_t *si)
+{
+ struct proc *p;
+ struct thread *td;
+
+ td = curthread;
+ p = td->td_proc;
+ PROC_LOCK_ASSERT(p, MA_OWNED);
+
+ bzero(si, sizeof(*si));
+ si->si_signo = sig;
+ si->si_code = code;
+ /* XXXKSE fill other fields */
+}
+#endif
+
+/*
+ * System call to cleanup state after a signal
+ * has been taken. Reset signal mask and
+ * stack state from context left by sendsig (above).
+ * Return to previous pc as specified by
+ * context left by sendsig.
+ */
+int
+sys_sigreturn(struct thread *td, struct sigreturn_args *uap)
+{
+ ucontext_t uc;
+ int error;
+
+ error = copyin(uap->sigcntxp, &uc, sizeof(uc));
+ if (error != 0)
+ return (error);
+
+ error = set_mcontext(td, &uc.uc_mcontext);
+ if (error != 0)
+ return (error);
+
+ kern_sigprocmask(td, SIG_SETMASK, &uc.uc_sigmask, NULL, 0);
+
+ return (EJUSTRETURN);
+}
+
+int
+ptrace_set_pc(struct thread *td, unsigned long addr)
+{
+ td->td_frame->pc = (register_t) addr;
+ return 0;
+}
+
+static int
+ptrace_read_int(struct thread *td, off_t addr, int *v)
+{
+ struct iovec iov;
+ struct uio uio;
+
+ PROC_LOCK_ASSERT(td->td_proc, MA_NOTOWNED);
+ iov.iov_base = (caddr_t) v;
+ iov.iov_len = sizeof(int);
+ uio.uio_iov = &iov;
+ uio.uio_iovcnt = 1;
+ uio.uio_offset = (off_t)addr;
+ uio.uio_resid = sizeof(int);
+ uio.uio_segflg = UIO_SYSSPACE;
+ uio.uio_rw = UIO_READ;
+ uio.uio_td = td;
+ return proc_rwmem(td->td_proc, &uio);
+}
+
+static int
+ptrace_write_int(struct thread *td, off_t addr, int v)
+{
+ struct iovec iov;
+ struct uio uio;
+
+ PROC_LOCK_ASSERT(td->td_proc, MA_NOTOWNED);
+ iov.iov_base = (caddr_t) &v;
+ iov.iov_len = sizeof(int);
+ uio.uio_iov = &iov;
+ uio.uio_iovcnt = 1;
+ uio.uio_offset = (off_t)addr;
+ uio.uio_resid = sizeof(int);
+ uio.uio_segflg = UIO_SYSSPACE;
+ uio.uio_rw = UIO_WRITE;
+ uio.uio_td = td;
+ return proc_rwmem(td->td_proc, &uio);
+}
+
+int
+ptrace_single_step(struct thread *td)
+{
+ unsigned va;
+ struct trapframe *locr0 = td->td_frame;
+ int i;
+ int bpinstr = MIPS_BREAK_SSTEP;
+ int curinstr;
+ struct proc *p;
+
+ p = td->td_proc;
+ PROC_UNLOCK(p);
+ /*
+ * Fetch what's at the current location.
+ */
+ ptrace_read_int(td, (off_t)locr0->pc, &curinstr);
+
+ /* compute next address after current location */
+ if(curinstr != 0) {
+ va = MipsEmulateBranch(locr0, locr0->pc, locr0->fsr,
+ (uintptr_t)&curinstr);
+ } else {
+ va = locr0->pc + 4;
+ }
+ if (td->td_md.md_ss_addr) {
+ printf("SS %s (%d): breakpoint already set at %x (va %x)\n",
+ p->p_comm, p->p_pid, td->td_md.md_ss_addr, va); /* XXX */
+ return (EFAULT);
+ }
+ td->td_md.md_ss_addr = va;
+ /*
+ * Fetch what's at the current location.
+ */
+ ptrace_read_int(td, (off_t)va, &td->td_md.md_ss_instr);
+
+ /*
+ * Store breakpoint instruction at the "next" location now.
+ */
+ i = ptrace_write_int (td, va, bpinstr);
+
+ /*
+ * The sync'ing of I & D caches is done by procfs_domem()
+ * through procfs_rwmem().
+ */
+
+ PROC_LOCK(p);
+ if (i < 0)
+ return (EFAULT);
+#if 0
+ printf("SS %s (%d): breakpoint set at %x: %x (pc %x) br %x\n",
+ p->p_comm, p->p_pid, p->p_md.md_ss_addr,
+ p->p_md.md_ss_instr, locr0->pc, curinstr); /* XXX */
+#endif
+ return (0);
+}
+
+
+void
+makectx(struct trapframe *tf, struct pcb *pcb)
+{
+
+ pcb->pcb_regs.ra = tf->ra;
+ pcb->pcb_regs.pc = tf->pc;
+ pcb->pcb_regs.sp = tf->sp;
+}
+
+int
+fill_regs(struct thread *td, struct reg *regs)
+{
+ memcpy(regs, td->td_frame, sizeof(struct reg));
+ return (0);
+}
+
+int
+set_regs(struct thread *td, struct reg *regs)
+{
+ struct trapframe *f;
+ register_t sr;
+
+ f = (struct trapframe *) td->td_frame;
+ /*
+ * Don't allow the user to change SR
+ */
+ sr = f->sr;
+ memcpy(td->td_frame, regs, sizeof(struct reg));
+ f->sr = sr;
+ return (0);
+}
+
+int
+get_mcontext(struct thread *td, mcontext_t *mcp, int flags)
+{
+ struct trapframe *tp;
+
+ tp = td->td_frame;
+ PROC_LOCK(curthread->td_proc);
+ mcp->mc_onstack = sigonstack(tp->sp);
+ PROC_UNLOCK(curthread->td_proc);
+ bcopy((void *)&td->td_frame->zero, (void *)&mcp->mc_regs,
+ sizeof(mcp->mc_regs));
+
+ mcp->mc_fpused = td->td_md.md_flags & MDTD_FPUSED;
+ if (mcp->mc_fpused) {
+ bcopy((void *)&td->td_frame->f0, (void *)&mcp->mc_fpregs,
+ sizeof(mcp->mc_fpregs));
+ }
+ if (flags & GET_MC_CLEAR_RET) {
+ mcp->mc_regs[V0] = 0;
+ mcp->mc_regs[V1] = 0;
+ mcp->mc_regs[A3] = 0;
+ }
+
+ mcp->mc_pc = td->td_frame->pc;
+ mcp->mullo = td->td_frame->mullo;
+ mcp->mulhi = td->td_frame->mulhi;
+ mcp->mc_tls = td->td_md.md_tls;
+ return (0);
+}
+
+int
+set_mcontext(struct thread *td, mcontext_t *mcp)
+{
+ struct trapframe *tp;
+
+ tp = td->td_frame;
+ bcopy((void *)&mcp->mc_regs, (void *)&td->td_frame->zero,
+ sizeof(mcp->mc_regs));
+
+ td->td_md.md_flags = mcp->mc_fpused & MDTD_FPUSED;
+ if (mcp->mc_fpused) {
+ bcopy((void *)&mcp->mc_fpregs, (void *)&td->td_frame->f0,
+ sizeof(mcp->mc_fpregs));
+ }
+ td->td_frame->pc = mcp->mc_pc;
+ td->td_frame->mullo = mcp->mullo;
+ td->td_frame->mulhi = mcp->mulhi;
+ td->td_md.md_tls = mcp->mc_tls;
+ /* Dont let user to set any bits in Status and casue registers */
+
+ return (0);
+}
+
+int
+fill_fpregs(struct thread *td, struct fpreg *fpregs)
+{
+ if (td == PCPU_GET(fpcurthread))
+ MipsSaveCurFPState(td);
+ memcpy(fpregs, &td->td_frame->f0, sizeof(struct fpreg));
+ return 0;
+}
+
+int
+set_fpregs(struct thread *td, struct fpreg *fpregs)
+{
+ if (PCPU_GET(fpcurthread) == td)
+ PCPU_SET(fpcurthread, (struct thread *)0);
+ memcpy(&td->td_frame->f0, fpregs, sizeof(struct fpreg));
+ return 0;
+}
+
+
+/*
+ * Clear registers on exec
+ * $sp is set to the stack pointer passed in. $pc is set to the entry
+ * point given by the exec_package passed in, as is $t9 (used for PIC
+ * code by the MIPS elf abi).
+ */
+void
+exec_setregs(struct thread *td, struct image_params *imgp, u_long stack)
+{
+
+ bzero((caddr_t)td->td_frame, sizeof(struct trapframe));
+
+ /*
+ * The stack pointer has to be aligned to accommodate the largest
+ * datatype at minimum. This probably means it should be 16-byte
+ * aligned, but for now we're 8-byte aligning it.
+ */
+ td->td_frame->sp = ((register_t) stack) & ~(sizeof(__int64_t) - 1);
+
+ /*
+ * If we're running o32 or n32 programs but have 64-bit registers,
+ * GCC may use stack-relative addressing near the top of user
+ * address space that, due to sign extension, will yield an
+ * invalid address. For instance, if sp is 0x7fffff00 then GCC
+ * might do something like this to load a word from 0x7ffffff0:
+ *
+ * addu sp, sp, 32768
+ * lw t0, -32528(sp)
+ *
+ * On systems with 64-bit registers, sp is sign-extended to
+ * 0xffffffff80007f00 and the load is instead done from
+ * 0xffffffff7ffffff0.
+ *
+ * To prevent this, we subtract 64K from the stack pointer here.
+ *
+ * For consistency, we should just always do this unless we're
+ * running n64 programs. For now, since we don't support
+ * COMPAT_FREEBSD32 on n64 kernels, we just do it unless we're
+ * running n64 kernels.
+ */
+#if !defined(__mips_n64)
+ td->td_frame->sp -= 65536;
+#endif
+
+ td->td_frame->pc = imgp->entry_addr & ~3;
+ td->td_frame->t9 = imgp->entry_addr & ~3; /* abicall req */
+ td->td_frame->sr = MIPS_SR_KSU_USER | MIPS_SR_EXL | MIPS_SR_INT_IE |
+ (mips_rd_status() & MIPS_SR_INT_MASK);
+#if defined(__mips_n32)
+ td->td_frame->sr |= MIPS_SR_PX;
+#elif defined(__mips_n64)
+ td->td_frame->sr |= MIPS_SR_PX | MIPS_SR_UX | MIPS_SR_KX;
+#endif
+ /*
+ * FREEBSD_DEVELOPERS_FIXME:
+ * Setup any other CPU-Specific registers (Not MIPS Standard)
+ * and/or bits in other standard MIPS registers (if CPU-Specific)
+ * that are needed.
+ */
+
+ /*
+ * Set up arguments for the rtld-capable crt0:
+ * a0 stack pointer
+ * a1 rtld cleanup (filled in by dynamic loader)
+ * a2 rtld object (filled in by dynamic loader)
+ * a3 ps_strings
+ */
+ td->td_frame->a0 = (register_t) stack;
+ td->td_frame->a1 = 0;
+ td->td_frame->a2 = 0;
+ td->td_frame->a3 = (register_t)imgp->ps_strings;
+
+ td->td_md.md_flags &= ~MDTD_FPUSED;
+ if (PCPU_GET(fpcurthread) == td)
+ PCPU_SET(fpcurthread, (struct thread *)0);
+ td->td_md.md_ss_addr = 0;
+}
+
+int
+ptrace_clear_single_step(struct thread *td)
+{
+ int i;
+ struct proc *p;
+
+ p = td->td_proc;
+ PROC_LOCK_ASSERT(p, MA_OWNED);
+ if (!td->td_md.md_ss_addr)
+ return EINVAL;
+
+ /*
+ * Restore original instruction and clear BP
+ */
+ i = ptrace_write_int (td, td->td_md.md_ss_addr, td->td_md.md_ss_instr);
+
+ /* The sync'ing of I & D caches is done by procfs_domem(). */
+
+ if (i < 0) {
+ log(LOG_ERR, "SS %s %d: can't restore instruction at %x: %x\n",
+ p->p_comm, p->p_pid, td->td_md.md_ss_addr,
+ td->td_md.md_ss_instr);
+ }
+ td->td_md.md_ss_addr = 0;
+ return 0;
+}
Property changes on: trunk/sys/mips/mips/pm_machdep.c
___________________________________________________________________
Added: svn:eol-style
## -0,0 +1 ##
+native
\ No newline at end of property
Added: svn:keywords
## -0,0 +1 ##
+MidnightBSD=%H
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+text/plain
\ No newline at end of property
Added: trunk/sys/mips/mips/pmap.c
===================================================================
--- trunk/sys/mips/mips/pmap.c (rev 0)
+++ trunk/sys/mips/mips/pmap.c 2018-05-26 21:55:02 UTC (rev 9987)
@@ -0,0 +1,3523 @@
+/* $MidnightBSD$ */
+/*
+ * Copyright (c) 1991 Regents of the University of California.
+ * All rights reserved.
+ * Copyright (c) 1994 John S. Dyson
+ * All rights reserved.
+ * Copyright (c) 1994 David Greenman
+ * All rights reserved.
+ *
+ * This code is derived from software contributed to Berkeley by
+ * the Systems Programming Group of the University of Utah Computer
+ * Science Department and William Jolitz of UUNET Technologies Inc.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * 4. Neither the name of the University nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ * from: @(#)pmap.c 7.7 (Berkeley) 5/12/91
+ * from: src/sys/i386/i386/pmap.c,v 1.250.2.8 2000/11/21 00:09:14 ps
+ * JNPR: pmap.c,v 1.11.2.1 2007/08/16 11:51:06 girish
+ */
+
+/*
+ * Manages physical address maps.
+ *
+ * Since the information managed by this module is
+ * also stored by the logical address mapping module,
+ * this module may throw away valid virtual-to-physical
+ * mappings at almost any time. However, invalidations
+ * of virtual-to-physical mappings must be done as
+ * requested.
+ *
+ * In order to cope with hardware architectures which
+ * make virtual-to-physical map invalidates expensive,
+ * this module may delay invalidate or reduced protection
+ * operations until such time as they are actually
+ * necessary. This module is given full information as
+ * to which processors are currently using which maps,
+ * and to when physical maps must be made correct.
+ */
+
+#include <sys/cdefs.h>
+__FBSDID("$FreeBSD: stable/10/sys/mips/mips/pmap.c 310133 2016-12-16 01:06:35Z jhb $");
+
+#include "opt_ddb.h"
+#include "opt_pmap.h"
+
+#include <sys/param.h>
+#include <sys/systm.h>
+#include <sys/lock.h>
+#include <sys/mman.h>
+#include <sys/msgbuf.h>
+#include <sys/mutex.h>
+#include <sys/pcpu.h>
+#include <sys/proc.h>
+#include <sys/rwlock.h>
+#include <sys/sched.h>
+#include <sys/smp.h>
+#include <sys/sysctl.h>
+#include <sys/vmmeter.h>
+
+#ifdef DDB
+#include <ddb/ddb.h>
+#endif
+
+#include <vm/vm.h>
+#include <vm/vm_param.h>
+#include <vm/vm_kern.h>
+#include <vm/vm_page.h>
+#include <vm/vm_map.h>
+#include <vm/vm_object.h>
+#include <vm/vm_extern.h>
+#include <vm/vm_pageout.h>
+#include <vm/vm_pager.h>
+#include <vm/uma.h>
+
+#include <machine/cache.h>
+#include <machine/md_var.h>
+#include <machine/tlb.h>
+
+#undef PMAP_DEBUG
+
+#if !defined(DIAGNOSTIC)
+#define PMAP_INLINE __inline
+#else
+#define PMAP_INLINE
+#endif
+
+#ifdef PV_STATS
+#define PV_STAT(x) do { x ; } while (0)
+#else
+#define PV_STAT(x) do { } while (0)
+#endif
+
+/*
+ * Get PDEs and PTEs for user/kernel address space
+ */
+#define pmap_seg_index(v) (((v) >> SEGSHIFT) & (NPDEPG - 1))
+#define pmap_pde_index(v) (((v) >> PDRSHIFT) & (NPDEPG - 1))
+#define pmap_pte_index(v) (((v) >> PAGE_SHIFT) & (NPTEPG - 1))
+#define pmap_pde_pindex(v) ((v) >> PDRSHIFT)
+
+#ifdef __mips_n64
+#define NUPDE (NPDEPG * NPDEPG)
+#define NUSERPGTBLS (NUPDE + NPDEPG)
+#else
+#define NUPDE (NPDEPG)
+#define NUSERPGTBLS (NUPDE)
+#endif
+
+#define is_kernel_pmap(x) ((x) == kernel_pmap)
+
+struct pmap kernel_pmap_store;
+pd_entry_t *kernel_segmap;
+
+vm_offset_t virtual_avail; /* VA of first avail page (after kernel bss) */
+vm_offset_t virtual_end; /* VA of last avail page (end of kernel AS) */
+
+static int nkpt;
+unsigned pmap_max_asid; /* max ASID supported by the system */
+
+#define PMAP_ASID_RESERVED 0
+
+vm_offset_t kernel_vm_end = VM_MIN_KERNEL_ADDRESS;
+
+static void pmap_asid_alloc(pmap_t pmap);
+
+static struct rwlock_padalign pvh_global_lock;
+
+/*
+ * Data for the pv entry allocation mechanism
+ */
+static TAILQ_HEAD(pch, pv_chunk) pv_chunks = TAILQ_HEAD_INITIALIZER(pv_chunks);
+static int pv_entry_count;
+
+static void free_pv_chunk(struct pv_chunk *pc);
+static void free_pv_entry(pmap_t pmap, pv_entry_t pv);
+static pv_entry_t get_pv_entry(pmap_t pmap, boolean_t try);
+static vm_page_t pmap_pv_reclaim(pmap_t locked_pmap);
+static void pmap_pvh_free(struct md_page *pvh, pmap_t pmap, vm_offset_t va);
+static pv_entry_t pmap_pvh_remove(struct md_page *pvh, pmap_t pmap,
+ vm_offset_t va);
+static vm_page_t pmap_alloc_direct_page(unsigned int index, int req);
+static vm_page_t pmap_enter_quick_locked(pmap_t pmap, vm_offset_t va,
+ vm_page_t m, vm_prot_t prot, vm_page_t mpte);
+static int pmap_remove_pte(struct pmap *pmap, pt_entry_t *ptq, vm_offset_t va,
+ pd_entry_t pde);
+static void pmap_remove_page(struct pmap *pmap, vm_offset_t va);
+static void pmap_remove_entry(struct pmap *pmap, vm_page_t m, vm_offset_t va);
+static boolean_t pmap_try_insert_pv_entry(pmap_t pmap, vm_page_t mpte,
+ vm_offset_t va, vm_page_t m);
+static void pmap_update_page(pmap_t pmap, vm_offset_t va, pt_entry_t pte);
+static void pmap_invalidate_all(pmap_t pmap);
+static void pmap_invalidate_page(pmap_t pmap, vm_offset_t va);
+static void _pmap_unwire_ptp(pmap_t pmap, vm_offset_t va, vm_page_t m);
+
+static vm_page_t pmap_allocpte(pmap_t pmap, vm_offset_t va, u_int flags);
+static vm_page_t _pmap_allocpte(pmap_t pmap, unsigned ptepindex, u_int flags);
+static int pmap_unuse_pt(pmap_t, vm_offset_t, pd_entry_t);
+static pt_entry_t init_pte_prot(vm_page_t m, vm_prot_t access, vm_prot_t prot);
+
+static void pmap_invalidate_page_action(void *arg);
+static void pmap_invalidate_range_action(void *arg);
+static void pmap_update_page_action(void *arg);
+
+#ifndef __mips_n64
+/*
+ * This structure is for high memory (memory above 512Meg in 32 bit) support.
+ * The highmem area does not have a KSEG0 mapping, and we need a mechanism to
+ * do temporary per-CPU mappings for pmap_zero_page, pmap_copy_page etc.
+ *
+ * At bootup, we reserve 2 virtual pages per CPU for mapping highmem pages. To
+ * access a highmem physical address on a CPU, we map the physical address to
+ * the reserved virtual address for the CPU in the kernel pagetable. This is
+ * done with interrupts disabled(although a spinlock and sched_pin would be
+ * sufficient).
+ */
+struct local_sysmaps {
+ vm_offset_t base;
+ uint32_t saved_intr;
+ uint16_t valid1, valid2;
+};
+static struct local_sysmaps sysmap_lmem[MAXCPU];
+
+static __inline void
+pmap_alloc_lmem_map(void)
+{
+ int i;
+
+ for (i = 0; i < MAXCPU; i++) {
+ sysmap_lmem[i].base = virtual_avail;
+ virtual_avail += PAGE_SIZE * 2;
+ sysmap_lmem[i].valid1 = sysmap_lmem[i].valid2 = 0;
+ }
+}
+
+static __inline vm_offset_t
+pmap_lmem_map1(vm_paddr_t phys)
+{
+ struct local_sysmaps *sysm;
+ pt_entry_t *pte, npte;
+ vm_offset_t va;
+ uint32_t intr;
+ int cpu;
+
+ intr = intr_disable();
+ cpu = PCPU_GET(cpuid);
+ sysm = &sysmap_lmem[cpu];
+ sysm->saved_intr = intr;
+ va = sysm->base;
+ npte = TLBLO_PA_TO_PFN(phys) | PTE_C_CACHE | PTE_D | PTE_V | PTE_G;
+ pte = pmap_pte(kernel_pmap, va);
+ *pte = npte;
+ sysm->valid1 = 1;
+ return (va);
+}
+
+static __inline vm_offset_t
+pmap_lmem_map2(vm_paddr_t phys1, vm_paddr_t phys2)
+{
+ struct local_sysmaps *sysm;
+ pt_entry_t *pte, npte;
+ vm_offset_t va1, va2;
+ uint32_t intr;
+ int cpu;
+
+ intr = intr_disable();
+ cpu = PCPU_GET(cpuid);
+ sysm = &sysmap_lmem[cpu];
+ sysm->saved_intr = intr;
+ va1 = sysm->base;
+ va2 = sysm->base + PAGE_SIZE;
+ npte = TLBLO_PA_TO_PFN(phys1) | PTE_C_CACHE | PTE_D | PTE_V | PTE_G;
+ pte = pmap_pte(kernel_pmap, va1);
+ *pte = npte;
+ npte = TLBLO_PA_TO_PFN(phys2) | PTE_C_CACHE | PTE_D | PTE_V | PTE_G;
+ pte = pmap_pte(kernel_pmap, va2);
+ *pte = npte;
+ sysm->valid1 = 1;
+ sysm->valid2 = 1;
+ return (va1);
+}
+
+static __inline void
+pmap_lmem_unmap(void)
+{
+ struct local_sysmaps *sysm;
+ pt_entry_t *pte;
+ int cpu;
+
+ cpu = PCPU_GET(cpuid);
+ sysm = &sysmap_lmem[cpu];
+ pte = pmap_pte(kernel_pmap, sysm->base);
+ *pte = PTE_G;
+ tlb_invalidate_address(kernel_pmap, sysm->base);
+ sysm->valid1 = 0;
+ if (sysm->valid2) {
+ pte = pmap_pte(kernel_pmap, sysm->base + PAGE_SIZE);
+ *pte = PTE_G;
+ tlb_invalidate_address(kernel_pmap, sysm->base + PAGE_SIZE);
+ sysm->valid2 = 0;
+ }
+ intr_restore(sysm->saved_intr);
+}
+#else /* __mips_n64 */
+
+static __inline void
+pmap_alloc_lmem_map(void)
+{
+}
+
+static __inline vm_offset_t
+pmap_lmem_map1(vm_paddr_t phys)
+{
+
+ return (0);
+}
+
+static __inline vm_offset_t
+pmap_lmem_map2(vm_paddr_t phys1, vm_paddr_t phys2)
+{
+
+ return (0);
+}
+
+static __inline vm_offset_t
+pmap_lmem_unmap(void)
+{
+
+ return (0);
+}
+#endif /* !__mips_n64 */
+
+/*
+ * Page table entry lookup routines.
+ */
+static __inline pd_entry_t *
+pmap_segmap(pmap_t pmap, vm_offset_t va)
+{
+
+ return (&pmap->pm_segtab[pmap_seg_index(va)]);
+}
+
+#ifdef __mips_n64
+static __inline pd_entry_t *
+pmap_pdpe_to_pde(pd_entry_t *pdpe, vm_offset_t va)
+{
+ pd_entry_t *pde;
+
+ pde = (pd_entry_t *)*pdpe;
+ return (&pde[pmap_pde_index(va)]);
+}
+
+static __inline pd_entry_t *
+pmap_pde(pmap_t pmap, vm_offset_t va)
+{
+ pd_entry_t *pdpe;
+
+ pdpe = pmap_segmap(pmap, va);
+ if (*pdpe == NULL)
+ return (NULL);
+
+ return (pmap_pdpe_to_pde(pdpe, va));
+}
+#else
+static __inline pd_entry_t *
+pmap_pdpe_to_pde(pd_entry_t *pdpe, vm_offset_t va)
+{
+
+ return (pdpe);
+}
+
+static __inline
+pd_entry_t *pmap_pde(pmap_t pmap, vm_offset_t va)
+{
+
+ return (pmap_segmap(pmap, va));
+}
+#endif
+
+static __inline pt_entry_t *
+pmap_pde_to_pte(pd_entry_t *pde, vm_offset_t va)
+{
+ pt_entry_t *pte;
+
+ pte = (pt_entry_t *)*pde;
+ return (&pte[pmap_pte_index(va)]);
+}
+
+pt_entry_t *
+pmap_pte(pmap_t pmap, vm_offset_t va)
+{
+ pd_entry_t *pde;
+
+ pde = pmap_pde(pmap, va);
+ if (pde == NULL || *pde == NULL)
+ return (NULL);
+
+ return (pmap_pde_to_pte(pde, va));
+}
+
+vm_offset_t
+pmap_steal_memory(vm_size_t size)
+{
+ vm_paddr_t bank_size, pa;
+ vm_offset_t va;
+
+ size = round_page(size);
+ bank_size = phys_avail[1] - phys_avail[0];
+ while (size > bank_size) {
+ int i;
+
+ for (i = 0; phys_avail[i + 2]; i += 2) {
+ phys_avail[i] = phys_avail[i + 2];
+ phys_avail[i + 1] = phys_avail[i + 3];
+ }
+ phys_avail[i] = 0;
+ phys_avail[i + 1] = 0;
+ if (!phys_avail[0])
+ panic("pmap_steal_memory: out of memory");
+ bank_size = phys_avail[1] - phys_avail[0];
+ }
+
+ pa = phys_avail[0];
+ phys_avail[0] += size;
+ if (MIPS_DIRECT_MAPPABLE(pa) == 0)
+ panic("Out of memory below 512Meg?");
+ va = MIPS_PHYS_TO_DIRECT(pa);
+ bzero((caddr_t)va, size);
+ return (va);
+}
+
+/*
+ * Bootstrap the system enough to run with virtual memory. This
+ * assumes that the phys_avail array has been initialized.
+ */
+static void
+pmap_create_kernel_pagetable(void)
+{
+ int i, j;
+ vm_offset_t ptaddr;
+ pt_entry_t *pte;
+#ifdef __mips_n64
+ pd_entry_t *pde;
+ vm_offset_t pdaddr;
+ int npt, npde;
+#endif
+
+ /*
+ * Allocate segment table for the kernel
+ */
+ kernel_segmap = (pd_entry_t *)pmap_steal_memory(PAGE_SIZE);
+
+ /*
+ * Allocate second level page tables for the kernel
+ */
+#ifdef __mips_n64
+ npde = howmany(NKPT, NPDEPG);
+ pdaddr = pmap_steal_memory(PAGE_SIZE * npde);
+#endif
+ nkpt = NKPT;
+ ptaddr = pmap_steal_memory(PAGE_SIZE * nkpt);
+
+ /*
+ * The R[4-7]?00 stores only one copy of the Global bit in the
+ * translation lookaside buffer for each 2 page entry. Thus invalid
+ * entrys must have the Global bit set so when Entry LO and Entry HI
+ * G bits are anded together they will produce a global bit to store
+ * in the tlb.
+ */
+ for (i = 0, pte = (pt_entry_t *)ptaddr; i < (nkpt * NPTEPG); i++, pte++)
+ *pte = PTE_G;
+
+#ifdef __mips_n64
+ for (i = 0, npt = nkpt; npt > 0; i++) {
+ kernel_segmap[i] = (pd_entry_t)(pdaddr + i * PAGE_SIZE);
+ pde = (pd_entry_t *)kernel_segmap[i];
+
+ for (j = 0; j < NPDEPG && npt > 0; j++, npt--)
+ pde[j] = (pd_entry_t)(ptaddr + (i * NPDEPG + j) * PAGE_SIZE);
+ }
+#else
+ for (i = 0, j = pmap_seg_index(VM_MIN_KERNEL_ADDRESS); i < nkpt; i++, j++)
+ kernel_segmap[j] = (pd_entry_t)(ptaddr + (i * PAGE_SIZE));
+#endif
+
+ PMAP_LOCK_INIT(kernel_pmap);
+ kernel_pmap->pm_segtab = kernel_segmap;
+ CPU_FILL(&kernel_pmap->pm_active);
+ TAILQ_INIT(&kernel_pmap->pm_pvchunk);
+ kernel_pmap->pm_asid[0].asid = PMAP_ASID_RESERVED;
+ kernel_pmap->pm_asid[0].gen = 0;
+ kernel_vm_end += nkpt * NPTEPG * PAGE_SIZE;
+}
+
+void
+pmap_bootstrap(void)
+{
+ int i;
+ int need_local_mappings = 0;
+
+ /* Sort. */
+again:
+ for (i = 0; phys_avail[i + 1] != 0; i += 2) {
+ /*
+ * Keep the memory aligned on page boundary.
+ */
+ phys_avail[i] = round_page(phys_avail[i]);
+ phys_avail[i + 1] = trunc_page(phys_avail[i + 1]);
+
+ if (i < 2)
+ continue;
+ if (phys_avail[i - 2] > phys_avail[i]) {
+ vm_paddr_t ptemp[2];
+
+ ptemp[0] = phys_avail[i + 0];
+ ptemp[1] = phys_avail[i + 1];
+
+ phys_avail[i + 0] = phys_avail[i - 2];
+ phys_avail[i + 1] = phys_avail[i - 1];
+
+ phys_avail[i - 2] = ptemp[0];
+ phys_avail[i - 1] = ptemp[1];
+ goto again;
+ }
+ }
+
+ /*
+ * In 32 bit, we may have memory which cannot be mapped directly.
+ * This memory will need temporary mapping before it can be
+ * accessed.
+ */
+ if (!MIPS_DIRECT_MAPPABLE(phys_avail[i - 1] - 1))
+ need_local_mappings = 1;
+
+ /*
+ * Copy the phys_avail[] array before we start stealing memory from it.
+ */
+ for (i = 0; phys_avail[i + 1] != 0; i += 2) {
+ physmem_desc[i] = phys_avail[i];
+ physmem_desc[i + 1] = phys_avail[i + 1];
+ }
+
+ Maxmem = atop(phys_avail[i - 1]);
+
+ if (bootverbose) {
+ printf("Physical memory chunk(s):\n");
+ for (i = 0; phys_avail[i + 1] != 0; i += 2) {
+ vm_paddr_t size;
+
+ size = phys_avail[i + 1] - phys_avail[i];
+ printf("%#08jx - %#08jx, %ju bytes (%ju pages)\n",
+ (uintmax_t) phys_avail[i],
+ (uintmax_t) phys_avail[i + 1] - 1,
+ (uintmax_t) size, (uintmax_t) size / PAGE_SIZE);
+ }
+ printf("Maxmem is 0x%0jx\n", ptoa((uintmax_t)Maxmem));
+ }
+ /*
+ * Steal the message buffer from the beginning of memory.
+ */
+ msgbufp = (struct msgbuf *)pmap_steal_memory(msgbufsize);
+ msgbufinit(msgbufp, msgbufsize);
+
+ /*
+ * Steal thread0 kstack.
+ */
+ kstack0 = pmap_steal_memory(KSTACK_PAGES << PAGE_SHIFT);
+
+ virtual_avail = VM_MIN_KERNEL_ADDRESS;
+ virtual_end = VM_MAX_KERNEL_ADDRESS;
+
+#ifdef SMP
+ /*
+ * Steal some virtual address space to map the pcpu area.
+ */
+ virtual_avail = roundup2(virtual_avail, PAGE_SIZE * 2);
+ pcpup = (struct pcpu *)virtual_avail;
+ virtual_avail += PAGE_SIZE * 2;
+
+ /*
+ * Initialize the wired TLB entry mapping the pcpu region for
+ * the BSP at 'pcpup'. Up until this point we were operating
+ * with the 'pcpup' for the BSP pointing to a virtual address
+ * in KSEG0 so there was no need for a TLB mapping.
+ */
+ mips_pcpu_tlb_init(PCPU_ADDR(0));
+
+ if (bootverbose)
+ printf("pcpu is available at virtual address %p.\n", pcpup);
+#endif
+
+ if (need_local_mappings)
+ pmap_alloc_lmem_map();
+ pmap_create_kernel_pagetable();
+ pmap_max_asid = VMNUM_PIDS;
+ mips_wr_entryhi(0);
+ mips_wr_pagemask(0);
+
+ /*
+ * Initialize the global pv list lock.
+ */
+ rw_init(&pvh_global_lock, "pmap pv global");
+}
+
+/*
+ * Initialize a vm_page's machine-dependent fields.
+ */
+void
+pmap_page_init(vm_page_t m)
+{
+
+ TAILQ_INIT(&m->md.pv_list);
+ m->md.pv_flags = 0;
+}
+
+/*
+ * Initialize the pmap module.
+ * Called by vm_init, to initialize any structures that the pmap
+ * system needs to map virtual memory.
+ */
+void
+pmap_init(void)
+{
+}
+
+/***************************************************
+ * Low level helper routines.....
+ ***************************************************/
+
+#ifdef SMP
+static __inline void
+pmap_call_on_active_cpus(pmap_t pmap, void (*fn)(void *), void *arg)
+{
+ int cpuid, cpu, self;
+ cpuset_t active_cpus;
+
+ sched_pin();
+ if (is_kernel_pmap(pmap)) {
+ smp_rendezvous(NULL, fn, NULL, arg);
+ goto out;
+ }
+ /* Force ASID update on inactive CPUs */
+ CPU_FOREACH(cpu) {
+ if (!CPU_ISSET(cpu, &pmap->pm_active))
+ pmap->pm_asid[cpu].gen = 0;
+ }
+ cpuid = PCPU_GET(cpuid);
+ /*
+ * XXX: barrier/locking for active?
+ *
+ * Take a snapshot of active here, any further changes are ignored.
+ * tlb update/invalidate should be harmless on inactive CPUs
+ */
+ active_cpus = pmap->pm_active;
+ self = CPU_ISSET(cpuid, &active_cpus);
+ CPU_CLR(cpuid, &active_cpus);
+ /* Optimize for the case where this cpu is the only active one */
+ if (CPU_EMPTY(&active_cpus)) {
+ if (self)
+ fn(arg);
+ } else {
+ if (self)
+ CPU_SET(cpuid, &active_cpus);
+ smp_rendezvous_cpus(active_cpus, NULL, fn, NULL, arg);
+ }
+out:
+ sched_unpin();
+}
+#else /* !SMP */
+static __inline void
+pmap_call_on_active_cpus(pmap_t pmap, void (*fn)(void *), void *arg)
+{
+ int cpuid;
+
+ if (is_kernel_pmap(pmap)) {
+ fn(arg);
+ return;
+ }
+ cpuid = PCPU_GET(cpuid);
+ if (!CPU_ISSET(cpuid, &pmap->pm_active))
+ pmap->pm_asid[cpuid].gen = 0;
+ else
+ fn(arg);
+}
+#endif /* SMP */
+
+static void
+pmap_invalidate_all(pmap_t pmap)
+{
+
+ pmap_call_on_active_cpus(pmap,
+ (void (*)(void *))tlb_invalidate_all_user, pmap);
+}
+
+struct pmap_invalidate_page_arg {
+ pmap_t pmap;
+ vm_offset_t va;
+};
+
+static void
+pmap_invalidate_page_action(void *arg)
+{
+ struct pmap_invalidate_page_arg *p = arg;
+
+ tlb_invalidate_address(p->pmap, p->va);
+}
+
+static void
+pmap_invalidate_page(pmap_t pmap, vm_offset_t va)
+{
+ struct pmap_invalidate_page_arg arg;
+
+ arg.pmap = pmap;
+ arg.va = va;
+ pmap_call_on_active_cpus(pmap, pmap_invalidate_page_action, &arg);
+}
+
+struct pmap_invalidate_range_arg {
+ pmap_t pmap;
+ vm_offset_t sva;
+ vm_offset_t eva;
+};
+
+static void
+pmap_invalidate_range_action(void *arg)
+{
+ struct pmap_invalidate_range_arg *p = arg;
+
+ tlb_invalidate_range(p->pmap, p->sva, p->eva);
+}
+
+static void
+pmap_invalidate_range(pmap_t pmap, vm_offset_t sva, vm_offset_t eva)
+{
+ struct pmap_invalidate_range_arg arg;
+
+ arg.pmap = pmap;
+ arg.sva = sva;
+ arg.eva = eva;
+ pmap_call_on_active_cpus(pmap, pmap_invalidate_range_action, &arg);
+}
+
+struct pmap_update_page_arg {
+ pmap_t pmap;
+ vm_offset_t va;
+ pt_entry_t pte;
+};
+
+static void
+pmap_update_page_action(void *arg)
+{
+ struct pmap_update_page_arg *p = arg;
+
+ tlb_update(p->pmap, p->va, p->pte);
+}
+
+static void
+pmap_update_page(pmap_t pmap, vm_offset_t va, pt_entry_t pte)
+{
+ struct pmap_update_page_arg arg;
+
+ arg.pmap = pmap;
+ arg.va = va;
+ arg.pte = pte;
+ pmap_call_on_active_cpus(pmap, pmap_update_page_action, &arg);
+}
+
+/*
+ * Routine: pmap_extract
+ * Function:
+ * Extract the physical page address associated
+ * with the given map/virtual_address pair.
+ */
+vm_paddr_t
+pmap_extract(pmap_t pmap, vm_offset_t va)
+{
+ pt_entry_t *pte;
+ vm_offset_t retval = 0;
+
+ PMAP_LOCK(pmap);
+ pte = pmap_pte(pmap, va);
+ if (pte) {
+ retval = TLBLO_PTE_TO_PA(*pte) | (va & PAGE_MASK);
+ }
+ PMAP_UNLOCK(pmap);
+ return (retval);
+}
+
+/*
+ * Routine: pmap_extract_and_hold
+ * Function:
+ * Atomically extract and hold the physical page
+ * with the given pmap and virtual address pair
+ * if that mapping permits the given protection.
+ */
+vm_page_t
+pmap_extract_and_hold(pmap_t pmap, vm_offset_t va, vm_prot_t prot)
+{
+ pt_entry_t pte, *ptep;
+ vm_paddr_t pa, pte_pa;
+ vm_page_t m;
+
+ m = NULL;
+ pa = 0;
+ PMAP_LOCK(pmap);
+retry:
+ ptep = pmap_pte(pmap, va);
+ if (ptep != NULL) {
+ pte = *ptep;
+ if (pte_test(&pte, PTE_V) && (!pte_test(&pte, PTE_RO) ||
+ (prot & VM_PROT_WRITE) == 0)) {
+ pte_pa = TLBLO_PTE_TO_PA(pte);
+ if (vm_page_pa_tryrelock(pmap, pte_pa, &pa))
+ goto retry;
+ m = PHYS_TO_VM_PAGE(pte_pa);
+ vm_page_hold(m);
+ }
+ }
+ PA_UNLOCK_COND(pa);
+ PMAP_UNLOCK(pmap);
+ return (m);
+}
+
+/***************************************************
+ * Low level mapping routines.....
+ ***************************************************/
+
+/*
+ * add a wired page to the kva
+ */
+void
+pmap_kenter_attr(vm_offset_t va, vm_paddr_t pa, int attr)
+{
+ pt_entry_t *pte;
+ pt_entry_t opte, npte;
+
+#ifdef PMAP_DEBUG
+ printf("pmap_kenter: va: %p -> pa: %p\n", (void *)va, (void *)pa);
+#endif
+
+ pte = pmap_pte(kernel_pmap, va);
+ opte = *pte;
+ npte = TLBLO_PA_TO_PFN(pa) | attr | PTE_D | PTE_V | PTE_G;
+ *pte = npte;
+ if (pte_test(&opte, PTE_V) && opte != npte)
+ pmap_update_page(kernel_pmap, va, npte);
+}
+
+void
+pmap_kenter(vm_offset_t va, vm_paddr_t pa)
+{
+
+ KASSERT(is_cacheable_mem(pa),
+ ("pmap_kenter: memory at 0x%lx is not cacheable", (u_long)pa));
+
+ pmap_kenter_attr(va, pa, PTE_C_CACHE);
+}
+
+/*
+ * remove a page from the kernel pagetables
+ */
+ /* PMAP_INLINE */ void
+pmap_kremove(vm_offset_t va)
+{
+ pt_entry_t *pte;
+
+ /*
+ * Write back all caches from the page being destroyed
+ */
+ mips_dcache_wbinv_range_index(va, PAGE_SIZE);
+
+ pte = pmap_pte(kernel_pmap, va);
+ *pte = PTE_G;
+ pmap_invalidate_page(kernel_pmap, va);
+}
+
+/*
+ * Used to map a range of physical addresses into kernel
+ * virtual address space.
+ *
+ * The value passed in '*virt' is a suggested virtual address for
+ * the mapping. Architectures which can support a direct-mapped
+ * physical to virtual region can return the appropriate address
+ * within that region, leaving '*virt' unchanged. Other
+ * architectures should map the pages starting at '*virt' and
+ * update '*virt' with the first usable address after the mapped
+ * region.
+ *
+ * Use XKPHYS for 64 bit, and KSEG0 where possible for 32 bit.
+ */
+vm_offset_t
+pmap_map(vm_offset_t *virt, vm_paddr_t start, vm_paddr_t end, int prot)
+{
+ vm_offset_t va, sva;
+
+ if (MIPS_DIRECT_MAPPABLE(end - 1))
+ return (MIPS_PHYS_TO_DIRECT(start));
+
+ va = sva = *virt;
+ while (start < end) {
+ pmap_kenter(va, start);
+ va += PAGE_SIZE;
+ start += PAGE_SIZE;
+ }
+ *virt = va;
+ return (sva);
+}
+
+/*
+ * Add a list of wired pages to the kva
+ * this routine is only used for temporary
+ * kernel mappings that do not need to have
+ * page modification or references recorded.
+ * Note that old mappings are simply written
+ * over. The page *must* be wired.
+ */
+void
+pmap_qenter(vm_offset_t va, vm_page_t *m, int count)
+{
+ int i;
+ vm_offset_t origva = va;
+
+ for (i = 0; i < count; i++) {
+ pmap_flush_pvcache(m[i]);
+ pmap_kenter(va, VM_PAGE_TO_PHYS(m[i]));
+ va += PAGE_SIZE;
+ }
+
+ mips_dcache_wbinv_range_index(origva, PAGE_SIZE*count);
+}
+
+/*
+ * this routine jerks page mappings from the
+ * kernel -- it is meant only for temporary mappings.
+ */
+void
+pmap_qremove(vm_offset_t va, int count)
+{
+ pt_entry_t *pte;
+ vm_offset_t origva;
+
+ if (count < 1)
+ return;
+ mips_dcache_wbinv_range_index(va, PAGE_SIZE * count);
+ origva = va;
+ do {
+ pte = pmap_pte(kernel_pmap, va);
+ *pte = PTE_G;
+ va += PAGE_SIZE;
+ } while (--count > 0);
+ pmap_invalidate_range(kernel_pmap, origva, va);
+}
+
+/***************************************************
+ * Page table page management routines.....
+ ***************************************************/
+
+/*
+ * Decrements a page table page's wire count, which is used to record the
+ * number of valid page table entries within the page. If the wire count
+ * drops to zero, then the page table page is unmapped. Returns TRUE if the
+ * page table page was unmapped and FALSE otherwise.
+ */
+static PMAP_INLINE boolean_t
+pmap_unwire_ptp(pmap_t pmap, vm_offset_t va, vm_page_t m)
+{
+
+ --m->wire_count;
+ if (m->wire_count == 0) {
+ _pmap_unwire_ptp(pmap, va, m);
+ return (TRUE);
+ } else
+ return (FALSE);
+}
+
+static void
+_pmap_unwire_ptp(pmap_t pmap, vm_offset_t va, vm_page_t m)
+{
+ pd_entry_t *pde;
+
+ PMAP_LOCK_ASSERT(pmap, MA_OWNED);
+ /*
+ * unmap the page table page
+ */
+#ifdef __mips_n64
+ if (m->pindex < NUPDE)
+ pde = pmap_pde(pmap, va);
+ else
+ pde = pmap_segmap(pmap, va);
+#else
+ pde = pmap_pde(pmap, va);
+#endif
+ *pde = 0;
+ pmap->pm_stats.resident_count--;
+
+#ifdef __mips_n64
+ if (m->pindex < NUPDE) {
+ pd_entry_t *pdp;
+ vm_page_t pdpg;
+
+ /*
+ * Recursively decrement next level pagetable refcount
+ */
+ pdp = (pd_entry_t *)*pmap_segmap(pmap, va);
+ pdpg = PHYS_TO_VM_PAGE(MIPS_DIRECT_TO_PHYS(pdp));
+ pmap_unwire_ptp(pmap, va, pdpg);
+ }
+#endif
+
+ /*
+ * If the page is finally unwired, simply free it.
+ */
+ vm_page_free_zero(m);
+ atomic_subtract_int(&cnt.v_wire_count, 1);
+}
+
+/*
+ * After removing a page table entry, this routine is used to
+ * conditionally free the page, and manage the hold/wire counts.
+ */
+static int
+pmap_unuse_pt(pmap_t pmap, vm_offset_t va, pd_entry_t pde)
+{
+ vm_page_t mpte;
+
+ if (va >= VM_MAXUSER_ADDRESS)
+ return (0);
+ KASSERT(pde != 0, ("pmap_unuse_pt: pde != 0"));
+ mpte = PHYS_TO_VM_PAGE(MIPS_DIRECT_TO_PHYS(pde));
+ return (pmap_unwire_ptp(pmap, va, mpte));
+}
+
+void
+pmap_pinit0(pmap_t pmap)
+{
+ int i;
+
+ PMAP_LOCK_INIT(pmap);
+ pmap->pm_segtab = kernel_segmap;
+ CPU_ZERO(&pmap->pm_active);
+ for (i = 0; i < MAXCPU; i++) {
+ pmap->pm_asid[i].asid = PMAP_ASID_RESERVED;
+ pmap->pm_asid[i].gen = 0;
+ }
+ PCPU_SET(curpmap, pmap);
+ TAILQ_INIT(&pmap->pm_pvchunk);
+ bzero(&pmap->pm_stats, sizeof pmap->pm_stats);
+}
+
+void
+pmap_grow_direct_page_cache()
+{
+
+#ifdef __mips_n64
+ vm_pageout_grow_cache(3, 0, MIPS_XKPHYS_LARGEST_PHYS);
+#else
+ vm_pageout_grow_cache(3, 0, MIPS_KSEG0_LARGEST_PHYS);
+#endif
+}
+
+static vm_page_t
+pmap_alloc_direct_page(unsigned int index, int req)
+{
+ vm_page_t m;
+
+ m = vm_page_alloc_freelist(VM_FREELIST_DIRECT, req | VM_ALLOC_WIRED |
+ VM_ALLOC_ZERO);
+ if (m == NULL)
+ return (NULL);
+
+ if ((m->flags & PG_ZERO) == 0)
+ pmap_zero_page(m);
+
+ m->pindex = index;
+ return (m);
+}
+
+/*
+ * Initialize a preallocated and zeroed pmap structure,
+ * such as one in a vmspace structure.
+ */
+int
+pmap_pinit(pmap_t pmap)
+{
+ vm_offset_t ptdva;
+ vm_page_t ptdpg;
+ int i;
+
+ /*
+ * allocate the page directory page
+ */
+ while ((ptdpg = pmap_alloc_direct_page(NUSERPGTBLS, VM_ALLOC_NORMAL)) == NULL)
+ pmap_grow_direct_page_cache();
+
+ ptdva = MIPS_PHYS_TO_DIRECT(VM_PAGE_TO_PHYS(ptdpg));
+ pmap->pm_segtab = (pd_entry_t *)ptdva;
+ CPU_ZERO(&pmap->pm_active);
+ for (i = 0; i < MAXCPU; i++) {
+ pmap->pm_asid[i].asid = PMAP_ASID_RESERVED;
+ pmap->pm_asid[i].gen = 0;
+ }
+ TAILQ_INIT(&pmap->pm_pvchunk);
+ bzero(&pmap->pm_stats, sizeof pmap->pm_stats);
+
+ return (1);
+}
+
+/*
+ * this routine is called if the page table page is not
+ * mapped correctly.
+ */
+static vm_page_t
+_pmap_allocpte(pmap_t pmap, unsigned ptepindex, u_int flags)
+{
+ vm_offset_t pageva;
+ vm_page_t m;
+
+ /*
+ * Find or fabricate a new pagetable page
+ */
+ if ((m = pmap_alloc_direct_page(ptepindex, VM_ALLOC_NORMAL)) == NULL) {
+ if ((flags & PMAP_ENTER_NOSLEEP) == 0) {
+ PMAP_UNLOCK(pmap);
+ rw_wunlock(&pvh_global_lock);
+ pmap_grow_direct_page_cache();
+ rw_wlock(&pvh_global_lock);
+ PMAP_LOCK(pmap);
+ }
+
+ /*
+ * Indicate the need to retry. While waiting, the page
+ * table page may have been allocated.
+ */
+ return (NULL);
+ }
+
+ /*
+ * Map the pagetable page into the process address space, if it
+ * isn't already there.
+ */
+ pageva = MIPS_PHYS_TO_DIRECT(VM_PAGE_TO_PHYS(m));
+
+#ifdef __mips_n64
+ if (ptepindex >= NUPDE) {
+ pmap->pm_segtab[ptepindex - NUPDE] = (pd_entry_t)pageva;
+ } else {
+ pd_entry_t *pdep, *pde;
+ int segindex = ptepindex >> (SEGSHIFT - PDRSHIFT);
+ int pdeindex = ptepindex & (NPDEPG - 1);
+ vm_page_t pg;
+
+ pdep = &pmap->pm_segtab[segindex];
+ if (*pdep == NULL) {
+ /* recurse for allocating page dir */
+ if (_pmap_allocpte(pmap, NUPDE + segindex,
+ flags) == NULL) {
+ /* alloc failed, release current */
+ --m->wire_count;
+ atomic_subtract_int(&cnt.v_wire_count, 1);
+ vm_page_free_zero(m);
+ return (NULL);
+ }
+ } else {
+ pg = PHYS_TO_VM_PAGE(MIPS_DIRECT_TO_PHYS(*pdep));
+ pg->wire_count++;
+ }
+ /* Next level entry */
+ pde = (pd_entry_t *)*pdep;
+ pde[pdeindex] = (pd_entry_t)pageva;
+ }
+#else
+ pmap->pm_segtab[ptepindex] = (pd_entry_t)pageva;
+#endif
+ pmap->pm_stats.resident_count++;
+ return (m);
+}
+
+static vm_page_t
+pmap_allocpte(pmap_t pmap, vm_offset_t va, u_int flags)
+{
+ unsigned ptepindex;
+ pd_entry_t *pde;
+ vm_page_t m;
+
+ /*
+ * Calculate pagetable page index
+ */
+ ptepindex = pmap_pde_pindex(va);
+retry:
+ /*
+ * Get the page directory entry
+ */
+ pde = pmap_pde(pmap, va);
+
+ /*
+ * If the page table page is mapped, we just increment the hold
+ * count, and activate it.
+ */
+ if (pde != NULL && *pde != NULL) {
+ m = PHYS_TO_VM_PAGE(MIPS_DIRECT_TO_PHYS(*pde));
+ m->wire_count++;
+ } else {
+ /*
+ * Here if the pte page isn't mapped, or if it has been
+ * deallocated.
+ */
+ m = _pmap_allocpte(pmap, ptepindex, flags);
+ if (m == NULL && (flags & PMAP_ENTER_NOSLEEP) == 0)
+ goto retry;
+ }
+ return (m);
+}
+
+
+/***************************************************
+ * Pmap allocation/deallocation routines.
+ ***************************************************/
+
+/*
+ * Release any resources held by the given physical map.
+ * Called when a pmap initialized by pmap_pinit is being released.
+ * Should only be called if the map contains no valid mappings.
+ */
+void
+pmap_release(pmap_t pmap)
+{
+ vm_offset_t ptdva;
+ vm_page_t ptdpg;
+
+ KASSERT(pmap->pm_stats.resident_count == 0,
+ ("pmap_release: pmap resident count %ld != 0",
+ pmap->pm_stats.resident_count));
+
+ ptdva = (vm_offset_t)pmap->pm_segtab;
+ ptdpg = PHYS_TO_VM_PAGE(MIPS_DIRECT_TO_PHYS(ptdva));
+
+ ptdpg->wire_count--;
+ atomic_subtract_int(&cnt.v_wire_count, 1);
+ vm_page_free_zero(ptdpg);
+}
+
+/*
+ * grow the number of kernel page table entries, if needed
+ */
+void
+pmap_growkernel(vm_offset_t addr)
+{
+ vm_page_t nkpg;
+ pd_entry_t *pde, *pdpe;
+ pt_entry_t *pte;
+ int i;
+
+ mtx_assert(&kernel_map->system_mtx, MA_OWNED);
+ addr = roundup2(addr, NBSEG);
+ if (addr - 1 >= kernel_map->max_offset)
+ addr = kernel_map->max_offset;
+ while (kernel_vm_end < addr) {
+ pdpe = pmap_segmap(kernel_pmap, kernel_vm_end);
+#ifdef __mips_n64
+ if (*pdpe == 0) {
+ /* new intermediate page table entry */
+ nkpg = pmap_alloc_direct_page(nkpt, VM_ALLOC_INTERRUPT);
+ if (nkpg == NULL)
+ panic("pmap_growkernel: no memory to grow kernel");
+ *pdpe = (pd_entry_t)MIPS_PHYS_TO_DIRECT(VM_PAGE_TO_PHYS(nkpg));
+ continue; /* try again */
+ }
+#endif
+ pde = pmap_pdpe_to_pde(pdpe, kernel_vm_end);
+ if (*pde != 0) {
+ kernel_vm_end = (kernel_vm_end + NBPDR) & ~PDRMASK;
+ if (kernel_vm_end - 1 >= kernel_map->max_offset) {
+ kernel_vm_end = kernel_map->max_offset;
+ break;
+ }
+ continue;
+ }
+
+ /*
+ * This index is bogus, but out of the way
+ */
+ nkpg = pmap_alloc_direct_page(nkpt, VM_ALLOC_INTERRUPT);
+ if (!nkpg)
+ panic("pmap_growkernel: no memory to grow kernel");
+ nkpt++;
+ *pde = (pd_entry_t)MIPS_PHYS_TO_DIRECT(VM_PAGE_TO_PHYS(nkpg));
+
+ /*
+ * The R[4-7]?00 stores only one copy of the Global bit in
+ * the translation lookaside buffer for each 2 page entry.
+ * Thus invalid entrys must have the Global bit set so when
+ * Entry LO and Entry HI G bits are anded together they will
+ * produce a global bit to store in the tlb.
+ */
+ pte = (pt_entry_t *)*pde;
+ for (i = 0; i < NPTEPG; i++)
+ pte[i] = PTE_G;
+
+ kernel_vm_end = (kernel_vm_end + NBPDR) & ~PDRMASK;
+ if (kernel_vm_end - 1 >= kernel_map->max_offset) {
+ kernel_vm_end = kernel_map->max_offset;
+ break;
+ }
+ }
+}
+
+/***************************************************
+ * page management routines.
+ ***************************************************/
+
+CTASSERT(sizeof(struct pv_chunk) == PAGE_SIZE);
+#ifdef __mips_n64
+CTASSERT(_NPCM == 3);
+CTASSERT(_NPCPV == 168);
+#else
+CTASSERT(_NPCM == 11);
+CTASSERT(_NPCPV == 336);
+#endif
+
+static __inline struct pv_chunk *
+pv_to_chunk(pv_entry_t pv)
+{
+
+ return ((struct pv_chunk *)((uintptr_t)pv & ~(uintptr_t)PAGE_MASK));
+}
+
+#define PV_PMAP(pv) (pv_to_chunk(pv)->pc_pmap)
+
+#ifdef __mips_n64
+#define PC_FREE0_1 0xfffffffffffffffful
+#define PC_FREE2 0x000000fffffffffful
+#else
+#define PC_FREE0_9 0xfffffffful /* Free values for index 0 through 9 */
+#define PC_FREE10 0x0000fffful /* Free values for index 10 */
+#endif
+
+static const u_long pc_freemask[_NPCM] = {
+#ifdef __mips_n64
+ PC_FREE0_1, PC_FREE0_1, PC_FREE2
+#else
+ PC_FREE0_9, PC_FREE0_9, PC_FREE0_9,
+ PC_FREE0_9, PC_FREE0_9, PC_FREE0_9,
+ PC_FREE0_9, PC_FREE0_9, PC_FREE0_9,
+ PC_FREE0_9, PC_FREE10
+#endif
+};
+
+static SYSCTL_NODE(_vm, OID_AUTO, pmap, CTLFLAG_RD, 0, "VM/pmap parameters");
+
+SYSCTL_INT(_vm_pmap, OID_AUTO, pv_entry_count, CTLFLAG_RD, &pv_entry_count, 0,
+ "Current number of pv entries");
+
+#ifdef PV_STATS
+static int pc_chunk_count, pc_chunk_allocs, pc_chunk_frees, pc_chunk_tryfail;
+
+SYSCTL_INT(_vm_pmap, OID_AUTO, pc_chunk_count, CTLFLAG_RD, &pc_chunk_count, 0,
+ "Current number of pv entry chunks");
+SYSCTL_INT(_vm_pmap, OID_AUTO, pc_chunk_allocs, CTLFLAG_RD, &pc_chunk_allocs, 0,
+ "Current number of pv entry chunks allocated");
+SYSCTL_INT(_vm_pmap, OID_AUTO, pc_chunk_frees, CTLFLAG_RD, &pc_chunk_frees, 0,
+ "Current number of pv entry chunks frees");
+SYSCTL_INT(_vm_pmap, OID_AUTO, pc_chunk_tryfail, CTLFLAG_RD, &pc_chunk_tryfail, 0,
+ "Number of times tried to get a chunk page but failed.");
+
+static long pv_entry_frees, pv_entry_allocs;
+static int pv_entry_spare;
+
+SYSCTL_LONG(_vm_pmap, OID_AUTO, pv_entry_frees, CTLFLAG_RD, &pv_entry_frees, 0,
+ "Current number of pv entry frees");
+SYSCTL_LONG(_vm_pmap, OID_AUTO, pv_entry_allocs, CTLFLAG_RD, &pv_entry_allocs, 0,
+ "Current number of pv entry allocs");
+SYSCTL_INT(_vm_pmap, OID_AUTO, pv_entry_spare, CTLFLAG_RD, &pv_entry_spare, 0,
+ "Current number of spare pv entries");
+#endif
+
+/*
+ * We are in a serious low memory condition. Resort to
+ * drastic measures to free some pages so we can allocate
+ * another pv entry chunk.
+ */
+static vm_page_t
+pmap_pv_reclaim(pmap_t locked_pmap)
+{
+ struct pch newtail;
+ struct pv_chunk *pc;
+ pd_entry_t *pde;
+ pmap_t pmap;
+ pt_entry_t *pte, oldpte;
+ pv_entry_t pv;
+ vm_offset_t va;
+ vm_page_t m, m_pc;
+ u_long inuse;
+ int bit, field, freed, idx;
+
+ PMAP_LOCK_ASSERT(locked_pmap, MA_OWNED);
+ pmap = NULL;
+ m_pc = NULL;
+ TAILQ_INIT(&newtail);
+ while ((pc = TAILQ_FIRST(&pv_chunks)) != NULL) {
+ TAILQ_REMOVE(&pv_chunks, pc, pc_lru);
+ if (pmap != pc->pc_pmap) {
+ if (pmap != NULL) {
+ pmap_invalidate_all(pmap);
+ if (pmap != locked_pmap)
+ PMAP_UNLOCK(pmap);
+ }
+ pmap = pc->pc_pmap;
+ /* Avoid deadlock and lock recursion. */
+ if (pmap > locked_pmap)
+ PMAP_LOCK(pmap);
+ else if (pmap != locked_pmap && !PMAP_TRYLOCK(pmap)) {
+ pmap = NULL;
+ TAILQ_INSERT_TAIL(&newtail, pc, pc_lru);
+ continue;
+ }
+ }
+
+ /*
+ * Destroy every non-wired, 4 KB page mapping in the chunk.
+ */
+ freed = 0;
+ for (field = 0; field < _NPCM; field++) {
+ for (inuse = ~pc->pc_map[field] & pc_freemask[field];
+ inuse != 0; inuse &= ~(1UL << bit)) {
+ bit = ffsl(inuse) - 1;
+ idx = field * sizeof(inuse) * NBBY + bit;
+ pv = &pc->pc_pventry[idx];
+ va = pv->pv_va;
+ pde = pmap_pde(pmap, va);
+ KASSERT(pde != NULL && *pde != 0,
+ ("pmap_pv_reclaim: pde"));
+ pte = pmap_pde_to_pte(pde, va);
+ oldpte = *pte;
+ if (pte_test(&oldpte, PTE_W))
+ continue;
+ if (is_kernel_pmap(pmap))
+ *pte = PTE_G;
+ else
+ *pte = 0;
+ m = PHYS_TO_VM_PAGE(TLBLO_PTE_TO_PA(oldpte));
+ if (pte_test(&oldpte, PTE_D))
+ vm_page_dirty(m);
+ if (m->md.pv_flags & PV_TABLE_REF)
+ vm_page_aflag_set(m, PGA_REFERENCED);
+ m->md.pv_flags &= ~PV_TABLE_REF;
+ TAILQ_REMOVE(&m->md.pv_list, pv, pv_list);
+ if (TAILQ_EMPTY(&m->md.pv_list))
+ vm_page_aflag_clear(m, PGA_WRITEABLE);
+ pc->pc_map[field] |= 1UL << bit;
+ pmap_unuse_pt(pmap, va, *pde);
+ freed++;
+ }
+ }
+ if (freed == 0) {
+ TAILQ_INSERT_TAIL(&newtail, pc, pc_lru);
+ continue;
+ }
+ /* Every freed mapping is for a 4 KB page. */
+ pmap->pm_stats.resident_count -= freed;
+ PV_STAT(pv_entry_frees += freed);
+ PV_STAT(pv_entry_spare += freed);
+ pv_entry_count -= freed;
+ TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
+ for (field = 0; field < _NPCM; field++)
+ if (pc->pc_map[field] != pc_freemask[field]) {
+ TAILQ_INSERT_HEAD(&pmap->pm_pvchunk, pc,
+ pc_list);
+ TAILQ_INSERT_TAIL(&newtail, pc, pc_lru);
+
+ /*
+ * One freed pv entry in locked_pmap is
+ * sufficient.
+ */
+ if (pmap == locked_pmap)
+ goto out;
+ break;
+ }
+ if (field == _NPCM) {
+ PV_STAT(pv_entry_spare -= _NPCPV);
+ PV_STAT(pc_chunk_count--);
+ PV_STAT(pc_chunk_frees++);
+ /* Entire chunk is free; return it. */
+ m_pc = PHYS_TO_VM_PAGE(MIPS_DIRECT_TO_PHYS(
+ (vm_offset_t)pc));
+ break;
+ }
+ }
+out:
+ TAILQ_CONCAT(&pv_chunks, &newtail, pc_lru);
+ if (pmap != NULL) {
+ pmap_invalidate_all(pmap);
+ if (pmap != locked_pmap)
+ PMAP_UNLOCK(pmap);
+ }
+ return (m_pc);
+}
+
+/*
+ * free the pv_entry back to the free list
+ */
+static void
+free_pv_entry(pmap_t pmap, pv_entry_t pv)
+{
+ struct pv_chunk *pc;
+ int bit, field, idx;
+
+ rw_assert(&pvh_global_lock, RA_WLOCKED);
+ PMAP_LOCK_ASSERT(pmap, MA_OWNED);
+ PV_STAT(pv_entry_frees++);
+ PV_STAT(pv_entry_spare++);
+ pv_entry_count--;
+ pc = pv_to_chunk(pv);
+ idx = pv - &pc->pc_pventry[0];
+ field = idx / (sizeof(u_long) * NBBY);
+ bit = idx % (sizeof(u_long) * NBBY);
+ pc->pc_map[field] |= 1ul << bit;
+ for (idx = 0; idx < _NPCM; idx++)
+ if (pc->pc_map[idx] != pc_freemask[idx]) {
+ /*
+ * 98% of the time, pc is already at the head of the
+ * list. If it isn't already, move it to the head.
+ */
+ if (__predict_false(TAILQ_FIRST(&pmap->pm_pvchunk) !=
+ pc)) {
+ TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
+ TAILQ_INSERT_HEAD(&pmap->pm_pvchunk, pc,
+ pc_list);
+ }
+ return;
+ }
+ TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
+ free_pv_chunk(pc);
+}
+
+static void
+free_pv_chunk(struct pv_chunk *pc)
+{
+ vm_page_t m;
+
+ TAILQ_REMOVE(&pv_chunks, pc, pc_lru);
+ PV_STAT(pv_entry_spare -= _NPCPV);
+ PV_STAT(pc_chunk_count--);
+ PV_STAT(pc_chunk_frees++);
+ /* entire chunk is free, return it */
+ m = PHYS_TO_VM_PAGE(MIPS_DIRECT_TO_PHYS((vm_offset_t)pc));
+ vm_page_unwire(m, 0);
+ vm_page_free(m);
+}
+
+/*
+ * get a new pv_entry, allocating a block from the system
+ * when needed.
+ */
+static pv_entry_t
+get_pv_entry(pmap_t pmap, boolean_t try)
+{
+ struct pv_chunk *pc;
+ pv_entry_t pv;
+ vm_page_t m;
+ int bit, field, idx;
+
+ rw_assert(&pvh_global_lock, RA_WLOCKED);
+ PMAP_LOCK_ASSERT(pmap, MA_OWNED);
+ PV_STAT(pv_entry_allocs++);
+ pv_entry_count++;
+retry:
+ pc = TAILQ_FIRST(&pmap->pm_pvchunk);
+ if (pc != NULL) {
+ for (field = 0; field < _NPCM; field++) {
+ if (pc->pc_map[field]) {
+ bit = ffsl(pc->pc_map[field]) - 1;
+ break;
+ }
+ }
+ if (field < _NPCM) {
+ idx = field * sizeof(pc->pc_map[field]) * NBBY + bit;
+ pv = &pc->pc_pventry[idx];
+ pc->pc_map[field] &= ~(1ul << bit);
+ /* If this was the last item, move it to tail */
+ for (field = 0; field < _NPCM; field++)
+ if (pc->pc_map[field] != 0) {
+ PV_STAT(pv_entry_spare--);
+ return (pv); /* not full, return */
+ }
+ TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
+ TAILQ_INSERT_TAIL(&pmap->pm_pvchunk, pc, pc_list);
+ PV_STAT(pv_entry_spare--);
+ return (pv);
+ }
+ }
+ /* No free items, allocate another chunk */
+ m = vm_page_alloc_freelist(VM_FREELIST_DIRECT, VM_ALLOC_NORMAL |
+ VM_ALLOC_WIRED);
+ if (m == NULL) {
+ if (try) {
+ pv_entry_count--;
+ PV_STAT(pc_chunk_tryfail++);
+ return (NULL);
+ }
+ m = pmap_pv_reclaim(pmap);
+ if (m == NULL)
+ goto retry;
+ }
+ PV_STAT(pc_chunk_count++);
+ PV_STAT(pc_chunk_allocs++);
+ pc = (struct pv_chunk *)MIPS_PHYS_TO_DIRECT(VM_PAGE_TO_PHYS(m));
+ pc->pc_pmap = pmap;
+ pc->pc_map[0] = pc_freemask[0] & ~1ul; /* preallocated bit 0 */
+ for (field = 1; field < _NPCM; field++)
+ pc->pc_map[field] = pc_freemask[field];
+ TAILQ_INSERT_TAIL(&pv_chunks, pc, pc_lru);
+ pv = &pc->pc_pventry[0];
+ TAILQ_INSERT_HEAD(&pmap->pm_pvchunk, pc, pc_list);
+ PV_STAT(pv_entry_spare += _NPCPV - 1);
+ return (pv);
+}
+
+static pv_entry_t
+pmap_pvh_remove(struct md_page *pvh, pmap_t pmap, vm_offset_t va)
+{
+ pv_entry_t pv;
+
+ rw_assert(&pvh_global_lock, RA_WLOCKED);
+ TAILQ_FOREACH(pv, &pvh->pv_list, pv_list) {
+ if (pmap == PV_PMAP(pv) && va == pv->pv_va) {
+ TAILQ_REMOVE(&pvh->pv_list, pv, pv_list);
+ break;
+ }
+ }
+ return (pv);
+}
+
+static void
+pmap_pvh_free(struct md_page *pvh, pmap_t pmap, vm_offset_t va)
+{
+ pv_entry_t pv;
+
+ pv = pmap_pvh_remove(pvh, pmap, va);
+ KASSERT(pv != NULL, ("pmap_pvh_free: pv not found, pa %lx va %lx",
+ (u_long)VM_PAGE_TO_PHYS(__containerof(pvh, struct vm_page, md)),
+ (u_long)va));
+ free_pv_entry(pmap, pv);
+}
+
+static void
+pmap_remove_entry(pmap_t pmap, vm_page_t m, vm_offset_t va)
+{
+
+ rw_assert(&pvh_global_lock, RA_WLOCKED);
+ pmap_pvh_free(&m->md, pmap, va);
+ if (TAILQ_EMPTY(&m->md.pv_list))
+ vm_page_aflag_clear(m, PGA_WRITEABLE);
+}
+
+/*
+ * Conditionally create a pv entry.
+ */
+static boolean_t
+pmap_try_insert_pv_entry(pmap_t pmap, vm_page_t mpte, vm_offset_t va,
+ vm_page_t m)
+{
+ pv_entry_t pv;
+
+ rw_assert(&pvh_global_lock, RA_WLOCKED);
+ PMAP_LOCK_ASSERT(pmap, MA_OWNED);
+ if ((pv = get_pv_entry(pmap, TRUE)) != NULL) {
+ pv->pv_va = va;
+ TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_list);
+ return (TRUE);
+ } else
+ return (FALSE);
+}
+
+/*
+ * pmap_remove_pte: do the things to unmap a page in a process
+ */
+static int
+pmap_remove_pte(struct pmap *pmap, pt_entry_t *ptq, vm_offset_t va,
+ pd_entry_t pde)
+{
+ pt_entry_t oldpte;
+ vm_page_t m;
+ vm_paddr_t pa;
+
+ rw_assert(&pvh_global_lock, RA_WLOCKED);
+ PMAP_LOCK_ASSERT(pmap, MA_OWNED);
+
+ /*
+ * Write back all cache lines from the page being unmapped.
+ */
+ mips_dcache_wbinv_range_index(va, PAGE_SIZE);
+
+ oldpte = *ptq;
+ if (is_kernel_pmap(pmap))
+ *ptq = PTE_G;
+ else
+ *ptq = 0;
+
+ if (pte_test(&oldpte, PTE_W))
+ pmap->pm_stats.wired_count -= 1;
+
+ pmap->pm_stats.resident_count -= 1;
+
+ if (pte_test(&oldpte, PTE_MANAGED)) {
+ pa = TLBLO_PTE_TO_PA(oldpte);
+ m = PHYS_TO_VM_PAGE(pa);
+ if (pte_test(&oldpte, PTE_D)) {
+ KASSERT(!pte_test(&oldpte, PTE_RO),
+ ("%s: modified page not writable: va: %p, pte: %#jx",
+ __func__, (void *)va, (uintmax_t)oldpte));
+ vm_page_dirty(m);
+ }
+ if (m->md.pv_flags & PV_TABLE_REF)
+ vm_page_aflag_set(m, PGA_REFERENCED);
+ m->md.pv_flags &= ~PV_TABLE_REF;
+
+ pmap_remove_entry(pmap, m, va);
+ }
+ return (pmap_unuse_pt(pmap, va, pde));
+}
+
+/*
+ * Remove a single page from a process address space
+ */
+static void
+pmap_remove_page(struct pmap *pmap, vm_offset_t va)
+{
+ pd_entry_t *pde;
+ pt_entry_t *ptq;
+
+ rw_assert(&pvh_global_lock, RA_WLOCKED);
+ PMAP_LOCK_ASSERT(pmap, MA_OWNED);
+ pde = pmap_pde(pmap, va);
+ if (pde == NULL || *pde == 0)
+ return;
+ ptq = pmap_pde_to_pte(pde, va);
+
+ /*
+ * If there is no pte for this address, just skip it!
+ */
+ if (!pte_test(ptq, PTE_V))
+ return;
+
+ (void)pmap_remove_pte(pmap, ptq, va, *pde);
+ pmap_invalidate_page(pmap, va);
+}
+
+/*
+ * Remove the given range of addresses from the specified map.
+ *
+ * It is assumed that the start and end are properly
+ * rounded to the page size.
+ */
+void
+pmap_remove(pmap_t pmap, vm_offset_t sva, vm_offset_t eva)
+{
+ pd_entry_t *pde, *pdpe;
+ pt_entry_t *pte;
+ vm_offset_t va, va_next;
+
+ /*
+ * Perform an unsynchronized read. This is, however, safe.
+ */
+ if (pmap->pm_stats.resident_count == 0)
+ return;
+
+ rw_wlock(&pvh_global_lock);
+ PMAP_LOCK(pmap);
+
+ /*
+ * special handling of removing one page. a very common operation
+ * and easy to short circuit some code.
+ */
+ if ((sva + PAGE_SIZE) == eva) {
+ pmap_remove_page(pmap, sva);
+ goto out;
+ }
+ for (; sva < eva; sva = va_next) {
+ pdpe = pmap_segmap(pmap, sva);
+#ifdef __mips_n64
+ if (*pdpe == 0) {
+ va_next = (sva + NBSEG) & ~SEGMASK;
+ if (va_next < sva)
+ va_next = eva;
+ continue;
+ }
+#endif
+ va_next = (sva + NBPDR) & ~PDRMASK;
+ if (va_next < sva)
+ va_next = eva;
+
+ pde = pmap_pdpe_to_pde(pdpe, sva);
+ if (*pde == NULL)
+ continue;
+
+ /*
+ * Limit our scan to either the end of the va represented
+ * by the current page table page, or to the end of the
+ * range being removed.
+ */
+ if (va_next > eva)
+ va_next = eva;
+
+ va = va_next;
+ for (pte = pmap_pde_to_pte(pde, sva); sva != va_next; pte++,
+ sva += PAGE_SIZE) {
+ if (!pte_test(pte, PTE_V)) {
+ if (va != va_next) {
+ pmap_invalidate_range(pmap, va, sva);
+ va = va_next;
+ }
+ continue;
+ }
+ if (va == va_next)
+ va = sva;
+ if (pmap_remove_pte(pmap, pte, sva, *pde)) {
+ sva += PAGE_SIZE;
+ break;
+ }
+ }
+ if (va != va_next)
+ pmap_invalidate_range(pmap, va, sva);
+ }
+out:
+ rw_wunlock(&pvh_global_lock);
+ PMAP_UNLOCK(pmap);
+}
+
+/*
+ * Routine: pmap_remove_all
+ * Function:
+ * Removes this physical page from
+ * all physical maps in which it resides.
+ * Reflects back modify bits to the pager.
+ *
+ * Notes:
+ * Original versions of this routine were very
+ * inefficient because they iteratively called
+ * pmap_remove (slow...)
+ */
+
+void
+pmap_remove_all(vm_page_t m)
+{
+ pv_entry_t pv;
+ pmap_t pmap;
+ pd_entry_t *pde;
+ pt_entry_t *pte, tpte;
+
+ KASSERT((m->oflags & VPO_UNMANAGED) == 0,
+ ("pmap_remove_all: page %p is not managed", m));
+ rw_wlock(&pvh_global_lock);
+
+ if (m->md.pv_flags & PV_TABLE_REF)
+ vm_page_aflag_set(m, PGA_REFERENCED);
+
+ while ((pv = TAILQ_FIRST(&m->md.pv_list)) != NULL) {
+ pmap = PV_PMAP(pv);
+ PMAP_LOCK(pmap);
+
+ /*
+ * If it's last mapping writeback all caches from
+ * the page being destroyed
+ */
+ if (TAILQ_NEXT(pv, pv_list) == NULL)
+ mips_dcache_wbinv_range_index(pv->pv_va, PAGE_SIZE);
+
+ pmap->pm_stats.resident_count--;
+
+ pde = pmap_pde(pmap, pv->pv_va);
+ KASSERT(pde != NULL && *pde != 0, ("pmap_remove_all: pde"));
+ pte = pmap_pde_to_pte(pde, pv->pv_va);
+
+ tpte = *pte;
+ if (is_kernel_pmap(pmap))
+ *pte = PTE_G;
+ else
+ *pte = 0;
+
+ if (pte_test(&tpte, PTE_W))
+ pmap->pm_stats.wired_count--;
+
+ /*
+ * Update the vm_page_t clean and reference bits.
+ */
+ if (pte_test(&tpte, PTE_D)) {
+ KASSERT(!pte_test(&tpte, PTE_RO),
+ ("%s: modified page not writable: va: %p, pte: %#jx",
+ __func__, (void *)pv->pv_va, (uintmax_t)tpte));
+ vm_page_dirty(m);
+ }
+ pmap_invalidate_page(pmap, pv->pv_va);
+
+ TAILQ_REMOVE(&m->md.pv_list, pv, pv_list);
+ pmap_unuse_pt(pmap, pv->pv_va, *pde);
+ free_pv_entry(pmap, pv);
+ PMAP_UNLOCK(pmap);
+ }
+
+ vm_page_aflag_clear(m, PGA_WRITEABLE);
+ m->md.pv_flags &= ~PV_TABLE_REF;
+ rw_wunlock(&pvh_global_lock);
+}
+
+/*
+ * Set the physical protection on the
+ * specified range of this map as requested.
+ */
+void
+pmap_protect(pmap_t pmap, vm_offset_t sva, vm_offset_t eva, vm_prot_t prot)
+{
+ pt_entry_t pbits, *pte;
+ pd_entry_t *pde, *pdpe;
+ vm_offset_t va, va_next;
+ vm_paddr_t pa;
+ vm_page_t m;
+
+ if ((prot & VM_PROT_READ) == VM_PROT_NONE) {
+ pmap_remove(pmap, sva, eva);
+ return;
+ }
+ if (prot & VM_PROT_WRITE)
+ return;
+
+ PMAP_LOCK(pmap);
+ for (; sva < eva; sva = va_next) {
+ pdpe = pmap_segmap(pmap, sva);
+#ifdef __mips_n64
+ if (*pdpe == 0) {
+ va_next = (sva + NBSEG) & ~SEGMASK;
+ if (va_next < sva)
+ va_next = eva;
+ continue;
+ }
+#endif
+ va_next = (sva + NBPDR) & ~PDRMASK;
+ if (va_next < sva)
+ va_next = eva;
+
+ pde = pmap_pdpe_to_pde(pdpe, sva);
+ if (*pde == NULL)
+ continue;
+
+ /*
+ * Limit our scan to either the end of the va represented
+ * by the current page table page, or to the end of the
+ * range being write protected.
+ */
+ if (va_next > eva)
+ va_next = eva;
+
+ va = va_next;
+ for (pte = pmap_pde_to_pte(pde, sva); sva != va_next; pte++,
+ sva += PAGE_SIZE) {
+ pbits = *pte;
+ if (!pte_test(&pbits, PTE_V) || pte_test(&pbits,
+ PTE_RO)) {
+ if (va != va_next) {
+ pmap_invalidate_range(pmap, va, sva);
+ va = va_next;
+ }
+ continue;
+ }
+ pte_set(&pbits, PTE_RO);
+ if (pte_test(&pbits, PTE_D)) {
+ pte_clear(&pbits, PTE_D);
+ if (pte_test(&pbits, PTE_MANAGED)) {
+ pa = TLBLO_PTE_TO_PA(pbits);
+ m = PHYS_TO_VM_PAGE(pa);
+ vm_page_dirty(m);
+ }
+ if (va == va_next)
+ va = sva;
+ } else {
+ /*
+ * Unless PTE_D is set, any TLB entries
+ * mapping "sva" don't allow write access, so
+ * they needn't be invalidated.
+ */
+ if (va != va_next) {
+ pmap_invalidate_range(pmap, va, sva);
+ va = va_next;
+ }
+ }
+ *pte = pbits;
+ }
+ if (va != va_next)
+ pmap_invalidate_range(pmap, va, sva);
+ }
+ PMAP_UNLOCK(pmap);
+}
+
+/*
+ * Insert the given physical page (p) at
+ * the specified virtual address (v) in the
+ * target physical map with the protection requested.
+ *
+ * If specified, the page will be wired down, meaning
+ * that the related pte can not be reclaimed.
+ *
+ * NB: This is the only routine which MAY NOT lazy-evaluate
+ * or lose information. That is, this routine must actually
+ * insert this page into the given map NOW.
+ */
+int
+pmap_enter(pmap_t pmap, vm_offset_t va, vm_page_t m, vm_prot_t prot,
+ u_int flags, int8_t psind __unused)
+{
+ vm_paddr_t pa, opa;
+ pt_entry_t *pte;
+ pt_entry_t origpte, newpte;
+ pv_entry_t pv;
+ vm_page_t mpte, om;
+
+ va &= ~PAGE_MASK;
+ KASSERT(va <= VM_MAX_KERNEL_ADDRESS, ("pmap_enter: toobig"));
+ KASSERT((m->oflags & VPO_UNMANAGED) != 0 || va < kmi.clean_sva ||
+ va >= kmi.clean_eva,
+ ("pmap_enter: managed mapping within the clean submap"));
+ if ((m->oflags & VPO_UNMANAGED) == 0 && !vm_page_xbusied(m))
+ VM_OBJECT_ASSERT_LOCKED(m->object);
+ pa = VM_PAGE_TO_PHYS(m);
+ newpte = TLBLO_PA_TO_PFN(pa) | init_pte_prot(m, flags, prot);
+ if ((flags & PMAP_ENTER_WIRED) != 0)
+ newpte |= PTE_W;
+ if (is_kernel_pmap(pmap))
+ newpte |= PTE_G;
+ if (is_cacheable_mem(pa))
+ newpte |= PTE_C_CACHE;
+ else
+ newpte |= PTE_C_UNCACHED;
+
+ mpte = NULL;
+
+ rw_wlock(&pvh_global_lock);
+ PMAP_LOCK(pmap);
+
+ /*
+ * In the case that a page table page is not resident, we are
+ * creating it here.
+ */
+ if (va < VM_MAXUSER_ADDRESS) {
+ mpte = pmap_allocpte(pmap, va, flags);
+ if (mpte == NULL) {
+ KASSERT((flags & PMAP_ENTER_NOSLEEP) != 0,
+ ("pmap_allocpte failed with sleep allowed"));
+ rw_wunlock(&pvh_global_lock);
+ PMAP_UNLOCK(pmap);
+ return (KERN_RESOURCE_SHORTAGE);
+ }
+ }
+ pte = pmap_pte(pmap, va);
+
+ /*
+ * Page Directory table entry not valid, we need a new PT page
+ */
+ if (pte == NULL) {
+ panic("pmap_enter: invalid page directory, pdir=%p, va=%p",
+ (void *)pmap->pm_segtab, (void *)va);
+ }
+ om = NULL;
+ origpte = *pte;
+ opa = TLBLO_PTE_TO_PA(origpte);
+
+ /*
+ * Mapping has not changed, must be protection or wiring change.
+ */
+ if (pte_test(&origpte, PTE_V) && opa == pa) {
+ /*
+ * Wiring change, just update stats. We don't worry about
+ * wiring PT pages as they remain resident as long as there
+ * are valid mappings in them. Hence, if a user page is
+ * wired, the PT page will be also.
+ */
+ if (pte_test(&newpte, PTE_W) && !pte_test(&origpte, PTE_W))
+ pmap->pm_stats.wired_count++;
+ else if (!pte_test(&newpte, PTE_W) && pte_test(&origpte,
+ PTE_W))
+ pmap->pm_stats.wired_count--;
+
+ KASSERT(!pte_test(&origpte, PTE_D | PTE_RO),
+ ("%s: modified page not writable: va: %p, pte: %#jx",
+ __func__, (void *)va, (uintmax_t)origpte));
+
+ /*
+ * Remove extra pte reference
+ */
+ if (mpte)
+ mpte->wire_count--;
+
+ if (pte_test(&origpte, PTE_MANAGED)) {
+ m->md.pv_flags |= PV_TABLE_REF;
+ om = m;
+ newpte |= PTE_MANAGED;
+ if (!pte_test(&newpte, PTE_RO))
+ vm_page_aflag_set(m, PGA_WRITEABLE);
+ }
+ goto validate;
+ }
+
+ pv = NULL;
+
+ /*
+ * Mapping has changed, invalidate old range and fall through to
+ * handle validating new mapping.
+ */
+ if (opa) {
+ if (pte_test(&origpte, PTE_W))
+ pmap->pm_stats.wired_count--;
+
+ if (pte_test(&origpte, PTE_MANAGED)) {
+ om = PHYS_TO_VM_PAGE(opa);
+ pv = pmap_pvh_remove(&om->md, pmap, va);
+ }
+ if (mpte != NULL) {
+ mpte->wire_count--;
+ KASSERT(mpte->wire_count > 0,
+ ("pmap_enter: missing reference to page table page,"
+ " va: %p", (void *)va));
+ }
+ } else
+ pmap->pm_stats.resident_count++;
+
+ /*
+ * Enter on the PV list if part of our managed memory.
+ */
+ if ((m->oflags & VPO_UNMANAGED) == 0) {
+ m->md.pv_flags |= PV_TABLE_REF;
+ if (pv == NULL)
+ pv = get_pv_entry(pmap, FALSE);
+ pv->pv_va = va;
+ TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_list);
+ newpte |= PTE_MANAGED;
+ if (!pte_test(&newpte, PTE_RO))
+ vm_page_aflag_set(m, PGA_WRITEABLE);
+ } else if (pv != NULL)
+ free_pv_entry(pmap, pv);
+
+ /*
+ * Increment counters
+ */
+ if (pte_test(&newpte, PTE_W))
+ pmap->pm_stats.wired_count++;
+
+validate:
+
+#ifdef PMAP_DEBUG
+ printf("pmap_enter: va: %p -> pa: %p\n", (void *)va, (void *)pa);
+#endif
+
+ /*
+ * if the mapping or permission bits are different, we need to
+ * update the pte.
+ */
+ if (origpte != newpte) {
+ *pte = newpte;
+ if (pte_test(&origpte, PTE_V)) {
+ if (pte_test(&origpte, PTE_MANAGED) && opa != pa) {
+ if (om->md.pv_flags & PV_TABLE_REF)
+ vm_page_aflag_set(om, PGA_REFERENCED);
+ om->md.pv_flags &= ~PV_TABLE_REF;
+ }
+ if (pte_test(&origpte, PTE_D)) {
+ KASSERT(!pte_test(&origpte, PTE_RO),
+ ("pmap_enter: modified page not writable:"
+ " va: %p, pte: %#jx", (void *)va, (uintmax_t)origpte));
+ if (pte_test(&origpte, PTE_MANAGED))
+ vm_page_dirty(om);
+ }
+ if (pte_test(&origpte, PTE_MANAGED) &&
+ TAILQ_EMPTY(&om->md.pv_list))
+ vm_page_aflag_clear(om, PGA_WRITEABLE);
+ pmap_update_page(pmap, va, newpte);
+ }
+ }
+
+ /*
+ * Sync I & D caches for executable pages. Do this only if the
+ * target pmap belongs to the current process. Otherwise, an
+ * unresolvable TLB miss may occur.
+ */
+ if (!is_kernel_pmap(pmap) && (pmap == &curproc->p_vmspace->vm_pmap) &&
+ (prot & VM_PROT_EXECUTE)) {
+ mips_icache_sync_range(va, PAGE_SIZE);
+ mips_dcache_wbinv_range(va, PAGE_SIZE);
+ }
+ rw_wunlock(&pvh_global_lock);
+ PMAP_UNLOCK(pmap);
+ return (KERN_SUCCESS);
+}
+
+/*
+ * this code makes some *MAJOR* assumptions:
+ * 1. Current pmap & pmap exists.
+ * 2. Not wired.
+ * 3. Read access.
+ * 4. No page table pages.
+ * but is *MUCH* faster than pmap_enter...
+ */
+
+void
+pmap_enter_quick(pmap_t pmap, vm_offset_t va, vm_page_t m, vm_prot_t prot)
+{
+
+ rw_wlock(&pvh_global_lock);
+ PMAP_LOCK(pmap);
+ (void)pmap_enter_quick_locked(pmap, va, m, prot, NULL);
+ rw_wunlock(&pvh_global_lock);
+ PMAP_UNLOCK(pmap);
+}
+
+static vm_page_t
+pmap_enter_quick_locked(pmap_t pmap, vm_offset_t va, vm_page_t m,
+ vm_prot_t prot, vm_page_t mpte)
+{
+ pt_entry_t *pte;
+ vm_paddr_t pa;
+
+ KASSERT(va < kmi.clean_sva || va >= kmi.clean_eva ||
+ (m->oflags & VPO_UNMANAGED) != 0,
+ ("pmap_enter_quick_locked: managed mapping within the clean submap"));
+ rw_assert(&pvh_global_lock, RA_WLOCKED);
+ PMAP_LOCK_ASSERT(pmap, MA_OWNED);
+
+ /*
+ * In the case that a page table page is not resident, we are
+ * creating it here.
+ */
+ if (va < VM_MAXUSER_ADDRESS) {
+ pd_entry_t *pde;
+ unsigned ptepindex;
+
+ /*
+ * Calculate pagetable page index
+ */
+ ptepindex = pmap_pde_pindex(va);
+ if (mpte && (mpte->pindex == ptepindex)) {
+ mpte->wire_count++;
+ } else {
+ /*
+ * Get the page directory entry
+ */
+ pde = pmap_pde(pmap, va);
+
+ /*
+ * If the page table page is mapped, we just
+ * increment the hold count, and activate it.
+ */
+ if (pde && *pde != 0) {
+ mpte = PHYS_TO_VM_PAGE(
+ MIPS_DIRECT_TO_PHYS(*pde));
+ mpte->wire_count++;
+ } else {
+ mpte = _pmap_allocpte(pmap, ptepindex,
+ PMAP_ENTER_NOSLEEP);
+ if (mpte == NULL)
+ return (mpte);
+ }
+ }
+ } else {
+ mpte = NULL;
+ }
+
+ pte = pmap_pte(pmap, va);
+ if (pte_test(pte, PTE_V)) {
+ if (mpte != NULL) {
+ mpte->wire_count--;
+ mpte = NULL;
+ }
+ return (mpte);
+ }
+
+ /*
+ * Enter on the PV list if part of our managed memory.
+ */
+ if ((m->oflags & VPO_UNMANAGED) == 0 &&
+ !pmap_try_insert_pv_entry(pmap, mpte, va, m)) {
+ if (mpte != NULL) {
+ pmap_unwire_ptp(pmap, va, mpte);
+ mpte = NULL;
+ }
+ return (mpte);
+ }
+
+ /*
+ * Increment counters
+ */
+ pmap->pm_stats.resident_count++;
+
+ pa = VM_PAGE_TO_PHYS(m);
+
+ /*
+ * Now validate mapping with RO protection
+ */
+ *pte = PTE_RO | TLBLO_PA_TO_PFN(pa) | PTE_V;
+ if ((m->oflags & VPO_UNMANAGED) == 0)
+ *pte |= PTE_MANAGED;
+
+ if (is_cacheable_mem(pa))
+ *pte |= PTE_C_CACHE;
+ else
+ *pte |= PTE_C_UNCACHED;
+
+ if (is_kernel_pmap(pmap))
+ *pte |= PTE_G;
+ else {
+ /*
+ * Sync I & D caches. Do this only if the target pmap
+ * belongs to the current process. Otherwise, an
+ * unresolvable TLB miss may occur. */
+ if (pmap == &curproc->p_vmspace->vm_pmap) {
+ va &= ~PAGE_MASK;
+ mips_icache_sync_range(va, PAGE_SIZE);
+ mips_dcache_wbinv_range(va, PAGE_SIZE);
+ }
+ }
+ return (mpte);
+}
+
+/*
+ * Make a temporary mapping for a physical address. This is only intended
+ * to be used for panic dumps.
+ *
+ * Use XKPHYS for 64 bit, and KSEG0 where possible for 32 bit.
+ */
+void *
+pmap_kenter_temporary(vm_paddr_t pa, int i)
+{
+ vm_offset_t va;
+
+ if (i != 0)
+ printf("%s: ERROR!!! More than one page of virtual address mapping not supported\n",
+ __func__);
+
+ if (MIPS_DIRECT_MAPPABLE(pa)) {
+ va = MIPS_PHYS_TO_DIRECT(pa);
+ } else {
+#ifndef __mips_n64 /* XXX : to be converted to new style */
+ int cpu;
+ register_t intr;
+ struct local_sysmaps *sysm;
+ pt_entry_t *pte, npte;
+
+ /* If this is used other than for dumps, we may need to leave
+ * interrupts disasbled on return. If crash dumps don't work when
+ * we get to this point, we might want to consider this (leaving things
+ * disabled as a starting point ;-)
+ */
+ intr = intr_disable();
+ cpu = PCPU_GET(cpuid);
+ sysm = &sysmap_lmem[cpu];
+ /* Since this is for the debugger, no locks or any other fun */
+ npte = TLBLO_PA_TO_PFN(pa) | PTE_C_CACHE | PTE_D | PTE_V |
+ PTE_G;
+ pte = pmap_pte(kernel_pmap, sysm->base);
+ *pte = npte;
+ sysm->valid1 = 1;
+ pmap_update_page(kernel_pmap, sysm->base, npte);
+ va = sysm->base;
+ intr_restore(intr);
+#endif
+ }
+ return ((void *)va);
+}
+
+void
+pmap_kenter_temporary_free(vm_paddr_t pa)
+{
+#ifndef __mips_n64 /* XXX : to be converted to new style */
+ int cpu;
+ register_t intr;
+ struct local_sysmaps *sysm;
+#endif
+
+ if (MIPS_DIRECT_MAPPABLE(pa)) {
+ /* nothing to do for this case */
+ return;
+ }
+#ifndef __mips_n64 /* XXX : to be converted to new style */
+ cpu = PCPU_GET(cpuid);
+ sysm = &sysmap_lmem[cpu];
+ if (sysm->valid1) {
+ pt_entry_t *pte;
+
+ intr = intr_disable();
+ pte = pmap_pte(kernel_pmap, sysm->base);
+ *pte = PTE_G;
+ pmap_invalidate_page(kernel_pmap, sysm->base);
+ intr_restore(intr);
+ sysm->valid1 = 0;
+ }
+#endif
+}
+
+/*
+ * Maps a sequence of resident pages belonging to the same object.
+ * The sequence begins with the given page m_start. This page is
+ * mapped at the given virtual address start. Each subsequent page is
+ * mapped at a virtual address that is offset from start by the same
+ * amount as the page is offset from m_start within the object. The
+ * last page in the sequence is the page with the largest offset from
+ * m_start that can be mapped at a virtual address less than the given
+ * virtual address end. Not every virtual page between start and end
+ * is mapped; only those for which a resident page exists with the
+ * corresponding offset from m_start are mapped.
+ */
+void
+pmap_enter_object(pmap_t pmap, vm_offset_t start, vm_offset_t end,
+ vm_page_t m_start, vm_prot_t prot)
+{
+ vm_page_t m, mpte;
+ vm_pindex_t diff, psize;
+
+ VM_OBJECT_ASSERT_LOCKED(m_start->object);
+
+ psize = atop(end - start);
+ mpte = NULL;
+ m = m_start;
+ rw_wlock(&pvh_global_lock);
+ PMAP_LOCK(pmap);
+ while (m != NULL && (diff = m->pindex - m_start->pindex) < psize) {
+ mpte = pmap_enter_quick_locked(pmap, start + ptoa(diff), m,
+ prot, mpte);
+ m = TAILQ_NEXT(m, listq);
+ }
+ rw_wunlock(&pvh_global_lock);
+ PMAP_UNLOCK(pmap);
+}
+
+/*
+ * pmap_object_init_pt preloads the ptes for a given object
+ * into the specified pmap. This eliminates the blast of soft
+ * faults on process startup and immediately after an mmap.
+ */
+void
+pmap_object_init_pt(pmap_t pmap, vm_offset_t addr,
+ vm_object_t object, vm_pindex_t pindex, vm_size_t size)
+{
+ VM_OBJECT_ASSERT_WLOCKED(object);
+ KASSERT(object->type == OBJT_DEVICE || object->type == OBJT_SG,
+ ("pmap_object_init_pt: non-device object"));
+}
+
+/*
+ * Clear the wired attribute from the mappings for the specified range of
+ * addresses in the given pmap. Every valid mapping within that range
+ * must have the wired attribute set. In contrast, invalid mappings
+ * cannot have the wired attribute set, so they are ignored.
+ *
+ * The wired attribute of the page table entry is not a hardware feature,
+ * so there is no need to invalidate any TLB entries.
+ */
+void
+pmap_unwire(pmap_t pmap, vm_offset_t sva, vm_offset_t eva)
+{
+ pd_entry_t *pde, *pdpe;
+ pt_entry_t *pte;
+ vm_offset_t va_next;
+
+ PMAP_LOCK(pmap);
+ for (; sva < eva; sva = va_next) {
+ pdpe = pmap_segmap(pmap, sva);
+#ifdef __mips_n64
+ if (*pdpe == NULL) {
+ va_next = (sva + NBSEG) & ~SEGMASK;
+ if (va_next < sva)
+ va_next = eva;
+ continue;
+ }
+#endif
+ va_next = (sva + NBPDR) & ~PDRMASK;
+ if (va_next < sva)
+ va_next = eva;
+ pde = pmap_pdpe_to_pde(pdpe, sva);
+ if (*pde == NULL)
+ continue;
+ if (va_next > eva)
+ va_next = eva;
+ for (pte = pmap_pde_to_pte(pde, sva); sva != va_next; pte++,
+ sva += PAGE_SIZE) {
+ if (!pte_test(pte, PTE_V))
+ continue;
+ if (!pte_test(pte, PTE_W))
+ panic("pmap_unwire: pte %#jx is missing PG_W",
+ (uintmax_t)*pte);
+ pte_clear(pte, PTE_W);
+ pmap->pm_stats.wired_count--;
+ }
+ }
+ PMAP_UNLOCK(pmap);
+}
+
+/*
+ * Copy the range specified by src_addr/len
+ * from the source map to the range dst_addr/len
+ * in the destination map.
+ *
+ * This routine is only advisory and need not do anything.
+ */
+
+void
+pmap_copy(pmap_t dst_pmap, pmap_t src_pmap, vm_offset_t dst_addr,
+ vm_size_t len, vm_offset_t src_addr)
+{
+}
+
+/*
+ * pmap_zero_page zeros the specified hardware page by mapping
+ * the page into KVM and using bzero to clear its contents.
+ *
+ * Use XKPHYS for 64 bit, and KSEG0 where possible for 32 bit.
+ */
+void
+pmap_zero_page(vm_page_t m)
+{
+ vm_offset_t va;
+ vm_paddr_t phys = VM_PAGE_TO_PHYS(m);
+
+ if (MIPS_DIRECT_MAPPABLE(phys)) {
+ va = MIPS_PHYS_TO_DIRECT(phys);
+ bzero((caddr_t)va, PAGE_SIZE);
+ mips_dcache_wbinv_range(va, PAGE_SIZE);
+ } else {
+ va = pmap_lmem_map1(phys);
+ bzero((caddr_t)va, PAGE_SIZE);
+ mips_dcache_wbinv_range(va, PAGE_SIZE);
+ pmap_lmem_unmap();
+ }
+}
+
+/*
+ * pmap_zero_page_area zeros the specified hardware page by mapping
+ * the page into KVM and using bzero to clear its contents.
+ *
+ * off and size may not cover an area beyond a single hardware page.
+ */
+void
+pmap_zero_page_area(vm_page_t m, int off, int size)
+{
+ vm_offset_t va;
+ vm_paddr_t phys = VM_PAGE_TO_PHYS(m);
+
+ if (MIPS_DIRECT_MAPPABLE(phys)) {
+ va = MIPS_PHYS_TO_DIRECT(phys);
+ bzero((char *)(caddr_t)va + off, size);
+ mips_dcache_wbinv_range(va + off, size);
+ } else {
+ va = pmap_lmem_map1(phys);
+ bzero((char *)va + off, size);
+ mips_dcache_wbinv_range(va + off, size);
+ pmap_lmem_unmap();
+ }
+}
+
+void
+pmap_zero_page_idle(vm_page_t m)
+{
+ vm_offset_t va;
+ vm_paddr_t phys = VM_PAGE_TO_PHYS(m);
+
+ if (MIPS_DIRECT_MAPPABLE(phys)) {
+ va = MIPS_PHYS_TO_DIRECT(phys);
+ bzero((caddr_t)va, PAGE_SIZE);
+ mips_dcache_wbinv_range(va, PAGE_SIZE);
+ } else {
+ va = pmap_lmem_map1(phys);
+ bzero((caddr_t)va, PAGE_SIZE);
+ mips_dcache_wbinv_range(va, PAGE_SIZE);
+ pmap_lmem_unmap();
+ }
+}
+
+/*
+ * pmap_copy_page copies the specified (machine independent)
+ * page by mapping the page into virtual memory and using
+ * bcopy to copy the page, one machine dependent page at a
+ * time.
+ *
+ * Use XKPHYS for 64 bit, and KSEG0 where possible for 32 bit.
+ */
+void
+pmap_copy_page(vm_page_t src, vm_page_t dst)
+{
+ vm_offset_t va_src, va_dst;
+ vm_paddr_t phys_src = VM_PAGE_TO_PHYS(src);
+ vm_paddr_t phys_dst = VM_PAGE_TO_PHYS(dst);
+
+ if (MIPS_DIRECT_MAPPABLE(phys_src) && MIPS_DIRECT_MAPPABLE(phys_dst)) {
+ /* easy case, all can be accessed via KSEG0 */
+ /*
+ * Flush all caches for VA that are mapped to this page
+ * to make sure that data in SDRAM is up to date
+ */
+ pmap_flush_pvcache(src);
+ mips_dcache_wbinv_range_index(
+ MIPS_PHYS_TO_DIRECT(phys_dst), PAGE_SIZE);
+ va_src = MIPS_PHYS_TO_DIRECT(phys_src);
+ va_dst = MIPS_PHYS_TO_DIRECT(phys_dst);
+ bcopy((caddr_t)va_src, (caddr_t)va_dst, PAGE_SIZE);
+ mips_dcache_wbinv_range(va_dst, PAGE_SIZE);
+ } else {
+ va_src = pmap_lmem_map2(phys_src, phys_dst);
+ va_dst = va_src + PAGE_SIZE;
+ bcopy((void *)va_src, (void *)va_dst, PAGE_SIZE);
+ mips_dcache_wbinv_range(va_dst, PAGE_SIZE);
+ pmap_lmem_unmap();
+ }
+}
+
+int unmapped_buf_allowed;
+
+void
+pmap_copy_pages(vm_page_t ma[], vm_offset_t a_offset, vm_page_t mb[],
+ vm_offset_t b_offset, int xfersize)
+{
+ char *a_cp, *b_cp;
+ vm_page_t a_m, b_m;
+ vm_offset_t a_pg_offset, b_pg_offset;
+ vm_paddr_t a_phys, b_phys;
+ int cnt;
+
+ while (xfersize > 0) {
+ a_pg_offset = a_offset & PAGE_MASK;
+ cnt = min(xfersize, PAGE_SIZE - a_pg_offset);
+ a_m = ma[a_offset >> PAGE_SHIFT];
+ a_phys = VM_PAGE_TO_PHYS(a_m);
+ b_pg_offset = b_offset & PAGE_MASK;
+ cnt = min(cnt, PAGE_SIZE - b_pg_offset);
+ b_m = mb[b_offset >> PAGE_SHIFT];
+ b_phys = VM_PAGE_TO_PHYS(b_m);
+ if (MIPS_DIRECT_MAPPABLE(a_phys) &&
+ MIPS_DIRECT_MAPPABLE(b_phys)) {
+ pmap_flush_pvcache(a_m);
+ mips_dcache_wbinv_range_index(
+ MIPS_PHYS_TO_DIRECT(b_phys), PAGE_SIZE);
+ a_cp = (char *)MIPS_PHYS_TO_DIRECT(a_phys) +
+ a_pg_offset;
+ b_cp = (char *)MIPS_PHYS_TO_DIRECT(b_phys) +
+ b_pg_offset;
+ bcopy(a_cp, b_cp, cnt);
+ mips_dcache_wbinv_range((vm_offset_t)b_cp, cnt);
+ } else {
+ a_cp = (char *)pmap_lmem_map2(a_phys, b_phys);
+ b_cp = (char *)a_cp + PAGE_SIZE;
+ a_cp += a_pg_offset;
+ b_cp += b_pg_offset;
+ bcopy(a_cp, b_cp, cnt);
+ mips_dcache_wbinv_range((vm_offset_t)b_cp, cnt);
+ pmap_lmem_unmap();
+ }
+ a_offset += cnt;
+ b_offset += cnt;
+ xfersize -= cnt;
+ }
+}
+
+/*
+ * Returns true if the pmap's pv is one of the first
+ * 16 pvs linked to from this page. This count may
+ * be changed upwards or downwards in the future; it
+ * is only necessary that true be returned for a small
+ * subset of pmaps for proper page aging.
+ */
+boolean_t
+pmap_page_exists_quick(pmap_t pmap, vm_page_t m)
+{
+ pv_entry_t pv;
+ int loops = 0;
+ boolean_t rv;
+
+ KASSERT((m->oflags & VPO_UNMANAGED) == 0,
+ ("pmap_page_exists_quick: page %p is not managed", m));
+ rv = FALSE;
+ rw_wlock(&pvh_global_lock);
+ TAILQ_FOREACH(pv, &m->md.pv_list, pv_list) {
+ if (PV_PMAP(pv) == pmap) {
+ rv = TRUE;
+ break;
+ }
+ loops++;
+ if (loops >= 16)
+ break;
+ }
+ rw_wunlock(&pvh_global_lock);
+ return (rv);
+}
+
+/*
+ * Remove all pages from specified address space
+ * this aids process exit speeds. Also, this code
+ * is special cased for current process only, but
+ * can have the more generic (and slightly slower)
+ * mode enabled. This is much faster than pmap_remove
+ * in the case of running down an entire address space.
+ */
+void
+pmap_remove_pages(pmap_t pmap)
+{
+ pd_entry_t *pde;
+ pt_entry_t *pte, tpte;
+ pv_entry_t pv;
+ vm_page_t m;
+ struct pv_chunk *pc, *npc;
+ u_long inuse, bitmask;
+ int allfree, bit, field, idx;
+
+ if (pmap != vmspace_pmap(curthread->td_proc->p_vmspace)) {
+ printf("warning: pmap_remove_pages called with non-current pmap\n");
+ return;
+ }
+ rw_wlock(&pvh_global_lock);
+ PMAP_LOCK(pmap);
+ TAILQ_FOREACH_SAFE(pc, &pmap->pm_pvchunk, pc_list, npc) {
+ allfree = 1;
+ for (field = 0; field < _NPCM; field++) {
+ inuse = ~pc->pc_map[field] & pc_freemask[field];
+ while (inuse != 0) {
+ bit = ffsl(inuse) - 1;
+ bitmask = 1UL << bit;
+ idx = field * sizeof(inuse) * NBBY + bit;
+ pv = &pc->pc_pventry[idx];
+ inuse &= ~bitmask;
+
+ pde = pmap_pde(pmap, pv->pv_va);
+ KASSERT(pde != NULL && *pde != 0,
+ ("pmap_remove_pages: pde"));
+ pte = pmap_pde_to_pte(pde, pv->pv_va);
+ if (!pte_test(pte, PTE_V))
+ panic("pmap_remove_pages: bad pte");
+ tpte = *pte;
+
+/*
+ * We cannot remove wired pages from a process' mapping at this time
+ */
+ if (pte_test(&tpte, PTE_W)) {
+ allfree = 0;
+ continue;
+ }
+ *pte = is_kernel_pmap(pmap) ? PTE_G : 0;
+
+ m = PHYS_TO_VM_PAGE(TLBLO_PTE_TO_PA(tpte));
+ KASSERT(m != NULL,
+ ("pmap_remove_pages: bad tpte %#jx",
+ (uintmax_t)tpte));
+
+ /*
+ * Update the vm_page_t clean and reference bits.
+ */
+ if (pte_test(&tpte, PTE_D))
+ vm_page_dirty(m);
+
+ /* Mark free */
+ PV_STAT(pv_entry_frees++);
+ PV_STAT(pv_entry_spare++);
+ pv_entry_count--;
+ pc->pc_map[field] |= bitmask;
+ pmap->pm_stats.resident_count--;
+ TAILQ_REMOVE(&m->md.pv_list, pv, pv_list);
+ if (TAILQ_EMPTY(&m->md.pv_list))
+ vm_page_aflag_clear(m, PGA_WRITEABLE);
+ pmap_unuse_pt(pmap, pv->pv_va, *pde);
+ }
+ }
+ if (allfree) {
+ TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
+ free_pv_chunk(pc);
+ }
+ }
+ pmap_invalidate_all(pmap);
+ PMAP_UNLOCK(pmap);
+ rw_wunlock(&pvh_global_lock);
+}
+
+/*
+ * pmap_testbit tests bits in pte's
+ */
+static boolean_t
+pmap_testbit(vm_page_t m, int bit)
+{
+ pv_entry_t pv;
+ pmap_t pmap;
+ pt_entry_t *pte;
+ boolean_t rv = FALSE;
+
+ if (m->oflags & VPO_UNMANAGED)
+ return (rv);
+
+ rw_assert(&pvh_global_lock, RA_WLOCKED);
+ TAILQ_FOREACH(pv, &m->md.pv_list, pv_list) {
+ pmap = PV_PMAP(pv);
+ PMAP_LOCK(pmap);
+ pte = pmap_pte(pmap, pv->pv_va);
+ rv = pte_test(pte, bit);
+ PMAP_UNLOCK(pmap);
+ if (rv)
+ break;
+ }
+ return (rv);
+}
+
+/*
+ * pmap_page_wired_mappings:
+ *
+ * Return the number of managed mappings to the given physical page
+ * that are wired.
+ */
+int
+pmap_page_wired_mappings(vm_page_t m)
+{
+ pv_entry_t pv;
+ pmap_t pmap;
+ pt_entry_t *pte;
+ int count;
+
+ count = 0;
+ if ((m->oflags & VPO_UNMANAGED) != 0)
+ return (count);
+ rw_wlock(&pvh_global_lock);
+ TAILQ_FOREACH(pv, &m->md.pv_list, pv_list) {
+ pmap = PV_PMAP(pv);
+ PMAP_LOCK(pmap);
+ pte = pmap_pte(pmap, pv->pv_va);
+ if (pte_test(pte, PTE_W))
+ count++;
+ PMAP_UNLOCK(pmap);
+ }
+ rw_wunlock(&pvh_global_lock);
+ return (count);
+}
+
+/*
+ * Clear the write and modified bits in each of the given page's mappings.
+ */
+void
+pmap_remove_write(vm_page_t m)
+{
+ pmap_t pmap;
+ pt_entry_t pbits, *pte;
+ pv_entry_t pv;
+
+ KASSERT((m->oflags & VPO_UNMANAGED) == 0,
+ ("pmap_remove_write: page %p is not managed", m));
+
+ /*
+ * If the page is not exclusive busied, then PGA_WRITEABLE cannot be
+ * set by another thread while the object is locked. Thus,
+ * if PGA_WRITEABLE is clear, no page table entries need updating.
+ */
+ VM_OBJECT_ASSERT_WLOCKED(m->object);
+ if (!vm_page_xbusied(m) && (m->aflags & PGA_WRITEABLE) == 0)
+ return;
+ rw_wlock(&pvh_global_lock);
+ TAILQ_FOREACH(pv, &m->md.pv_list, pv_list) {
+ pmap = PV_PMAP(pv);
+ PMAP_LOCK(pmap);
+ pte = pmap_pte(pmap, pv->pv_va);
+ KASSERT(pte != NULL && pte_test(pte, PTE_V),
+ ("page on pv_list has no pte"));
+ pbits = *pte;
+ if (pte_test(&pbits, PTE_D)) {
+ pte_clear(&pbits, PTE_D);
+ vm_page_dirty(m);
+ }
+ pte_set(&pbits, PTE_RO);
+ if (pbits != *pte) {
+ *pte = pbits;
+ pmap_update_page(pmap, pv->pv_va, pbits);
+ }
+ PMAP_UNLOCK(pmap);
+ }
+ vm_page_aflag_clear(m, PGA_WRITEABLE);
+ rw_wunlock(&pvh_global_lock);
+}
+
+/*
+ * pmap_ts_referenced:
+ *
+ * Return the count of reference bits for a page, clearing all of them.
+ */
+int
+pmap_ts_referenced(vm_page_t m)
+{
+
+ KASSERT((m->oflags & VPO_UNMANAGED) == 0,
+ ("pmap_ts_referenced: page %p is not managed", m));
+ if (m->md.pv_flags & PV_TABLE_REF) {
+ rw_wlock(&pvh_global_lock);
+ m->md.pv_flags &= ~PV_TABLE_REF;
+ rw_wunlock(&pvh_global_lock);
+ return (1);
+ }
+ return (0);
+}
+
+/*
+ * pmap_is_modified:
+ *
+ * Return whether or not the specified physical page was modified
+ * in any physical maps.
+ */
+boolean_t
+pmap_is_modified(vm_page_t m)
+{
+ boolean_t rv;
+
+ KASSERT((m->oflags & VPO_UNMANAGED) == 0,
+ ("pmap_is_modified: page %p is not managed", m));
+
+ /*
+ * If the page is not exclusive busied, then PGA_WRITEABLE cannot be
+ * concurrently set while the object is locked. Thus, if PGA_WRITEABLE
+ * is clear, no PTEs can have PTE_D set.
+ */
+ VM_OBJECT_ASSERT_WLOCKED(m->object);
+ if (!vm_page_xbusied(m) && (m->aflags & PGA_WRITEABLE) == 0)
+ return (FALSE);
+ rw_wlock(&pvh_global_lock);
+ rv = pmap_testbit(m, PTE_D);
+ rw_wunlock(&pvh_global_lock);
+ return (rv);
+}
+
+/* N/C */
+
+/*
+ * pmap_is_prefaultable:
+ *
+ * Return whether or not the specified virtual address is elgible
+ * for prefault.
+ */
+boolean_t
+pmap_is_prefaultable(pmap_t pmap, vm_offset_t addr)
+{
+ pd_entry_t *pde;
+ pt_entry_t *pte;
+ boolean_t rv;
+
+ rv = FALSE;
+ PMAP_LOCK(pmap);
+ pde = pmap_pde(pmap, addr);
+ if (pde != NULL && *pde != 0) {
+ pte = pmap_pde_to_pte(pde, addr);
+ rv = (*pte == 0);
+ }
+ PMAP_UNLOCK(pmap);
+ return (rv);
+}
+
+/*
+ * Apply the given advice to the specified range of addresses within the
+ * given pmap. Depending on the advice, clear the referenced and/or
+ * modified flags in each mapping and set the mapped page's dirty field.
+ */
+void
+pmap_advise(pmap_t pmap, vm_offset_t sva, vm_offset_t eva, int advice)
+{
+ pd_entry_t *pde, *pdpe;
+ pt_entry_t *pte;
+ vm_offset_t va, va_next;
+ vm_paddr_t pa;
+ vm_page_t m;
+
+ if (advice != MADV_DONTNEED && advice != MADV_FREE)
+ return;
+ rw_wlock(&pvh_global_lock);
+ PMAP_LOCK(pmap);
+ for (; sva < eva; sva = va_next) {
+ pdpe = pmap_segmap(pmap, sva);
+#ifdef __mips_n64
+ if (*pdpe == 0) {
+ va_next = (sva + NBSEG) & ~SEGMASK;
+ if (va_next < sva)
+ va_next = eva;
+ continue;
+ }
+#endif
+ va_next = (sva + NBPDR) & ~PDRMASK;
+ if (va_next < sva)
+ va_next = eva;
+
+ pde = pmap_pdpe_to_pde(pdpe, sva);
+ if (*pde == NULL)
+ continue;
+
+ /*
+ * Limit our scan to either the end of the va represented
+ * by the current page table page, or to the end of the
+ * range being write protected.
+ */
+ if (va_next > eva)
+ va_next = eva;
+
+ va = va_next;
+ for (pte = pmap_pde_to_pte(pde, sva); sva != va_next; pte++,
+ sva += PAGE_SIZE) {
+ if (!pte_test(pte, PTE_MANAGED | PTE_V)) {
+ if (va != va_next) {
+ pmap_invalidate_range(pmap, va, sva);
+ va = va_next;
+ }
+ continue;
+ }
+ pa = TLBLO_PTE_TO_PA(*pte);
+ m = PHYS_TO_VM_PAGE(pa);
+ m->md.pv_flags &= ~PV_TABLE_REF;
+ if (pte_test(pte, PTE_D)) {
+ if (advice == MADV_DONTNEED) {
+ /*
+ * Future calls to pmap_is_modified()
+ * can be avoided by making the page
+ * dirty now.
+ */
+ vm_page_dirty(m);
+ } else {
+ pte_clear(pte, PTE_D);
+ if (va == va_next)
+ va = sva;
+ }
+ } else {
+ /*
+ * Unless PTE_D is set, any TLB entries
+ * mapping "sva" don't allow write access, so
+ * they needn't be invalidated.
+ */
+ if (va != va_next) {
+ pmap_invalidate_range(pmap, va, sva);
+ va = va_next;
+ }
+ }
+ }
+ if (va != va_next)
+ pmap_invalidate_range(pmap, va, sva);
+ }
+ rw_wunlock(&pvh_global_lock);
+ PMAP_UNLOCK(pmap);
+}
+
+/*
+ * Clear the modify bits on the specified physical page.
+ */
+void
+pmap_clear_modify(vm_page_t m)
+{
+ pmap_t pmap;
+ pt_entry_t *pte;
+ pv_entry_t pv;
+
+ KASSERT((m->oflags & VPO_UNMANAGED) == 0,
+ ("pmap_clear_modify: page %p is not managed", m));
+ VM_OBJECT_ASSERT_WLOCKED(m->object);
+ KASSERT(!vm_page_xbusied(m),
+ ("pmap_clear_modify: page %p is exclusive busied", m));
+
+ /*
+ * If the page is not PGA_WRITEABLE, then no PTEs can have PTE_D set.
+ * If the object containing the page is locked and the page is not
+ * write busied, then PGA_WRITEABLE cannot be concurrently set.
+ */
+ if ((m->aflags & PGA_WRITEABLE) == 0)
+ return;
+ rw_wlock(&pvh_global_lock);
+ TAILQ_FOREACH(pv, &m->md.pv_list, pv_list) {
+ pmap = PV_PMAP(pv);
+ PMAP_LOCK(pmap);
+ pte = pmap_pte(pmap, pv->pv_va);
+ if (pte_test(pte, PTE_D)) {
+ pte_clear(pte, PTE_D);
+ pmap_update_page(pmap, pv->pv_va, *pte);
+ }
+ PMAP_UNLOCK(pmap);
+ }
+ rw_wunlock(&pvh_global_lock);
+}
+
+/*
+ * pmap_is_referenced:
+ *
+ * Return whether or not the specified physical page was referenced
+ * in any physical maps.
+ */
+boolean_t
+pmap_is_referenced(vm_page_t m)
+{
+
+ KASSERT((m->oflags & VPO_UNMANAGED) == 0,
+ ("pmap_is_referenced: page %p is not managed", m));
+ return ((m->md.pv_flags & PV_TABLE_REF) != 0);
+}
+
+/*
+ * Miscellaneous support routines follow
+ */
+
+/*
+ * Map a set of physical memory pages into the kernel virtual
+ * address space. Return a pointer to where it is mapped. This
+ * routine is intended to be used for mapping device memory,
+ * NOT real memory.
+ *
+ * Use XKPHYS uncached for 64 bit, and KSEG1 where possible for 32 bit.
+ */
+void *
+pmap_mapdev(vm_paddr_t pa, vm_size_t size)
+{
+ vm_offset_t va, tmpva, offset;
+
+ /*
+ * KSEG1 maps only first 512M of phys address space. For
+ * pa > 0x20000000 we should make proper mapping * using pmap_kenter.
+ */
+ if (MIPS_DIRECT_MAPPABLE(pa + size - 1))
+ return ((void *)MIPS_PHYS_TO_DIRECT_UNCACHED(pa));
+ else {
+ offset = pa & PAGE_MASK;
+ size = roundup(size + offset, PAGE_SIZE);
+
+ va = kva_alloc(size);
+ if (!va)
+ panic("pmap_mapdev: Couldn't alloc kernel virtual memory");
+ pa = trunc_page(pa);
+ for (tmpva = va; size > 0;) {
+ pmap_kenter_attr(tmpva, pa, PTE_C_UNCACHED);
+ size -= PAGE_SIZE;
+ tmpva += PAGE_SIZE;
+ pa += PAGE_SIZE;
+ }
+ }
+
+ return ((void *)(va + offset));
+}
+
+void
+pmap_unmapdev(vm_offset_t va, vm_size_t size)
+{
+#ifndef __mips_n64
+ vm_offset_t base, offset;
+
+ /* If the address is within KSEG1 then there is nothing to do */
+ if (va >= MIPS_KSEG1_START && va <= MIPS_KSEG1_END)
+ return;
+
+ base = trunc_page(va);
+ offset = va & PAGE_MASK;
+ size = roundup(size + offset, PAGE_SIZE);
+ kva_free(base, size);
+#endif
+}
+
+/*
+ * perform the pmap work for mincore
+ */
+int
+pmap_mincore(pmap_t pmap, vm_offset_t addr, vm_paddr_t *locked_pa)
+{
+ pt_entry_t *ptep, pte;
+ vm_paddr_t pa;
+ vm_page_t m;
+ int val;
+
+ PMAP_LOCK(pmap);
+retry:
+ ptep = pmap_pte(pmap, addr);
+ pte = (ptep != NULL) ? *ptep : 0;
+ if (!pte_test(&pte, PTE_V)) {
+ val = 0;
+ goto out;
+ }
+ val = MINCORE_INCORE;
+ if (pte_test(&pte, PTE_D))
+ val |= MINCORE_MODIFIED | MINCORE_MODIFIED_OTHER;
+ pa = TLBLO_PTE_TO_PA(pte);
+ if (pte_test(&pte, PTE_MANAGED)) {
+ /*
+ * This may falsely report the given address as
+ * MINCORE_REFERENCED. Unfortunately, due to the lack of
+ * per-PTE reference information, it is impossible to
+ * determine if the address is MINCORE_REFERENCED.
+ */
+ m = PHYS_TO_VM_PAGE(pa);
+ if ((m->aflags & PGA_REFERENCED) != 0)
+ val |= MINCORE_REFERENCED | MINCORE_REFERENCED_OTHER;
+ }
+ if ((val & (MINCORE_MODIFIED_OTHER | MINCORE_REFERENCED_OTHER)) !=
+ (MINCORE_MODIFIED_OTHER | MINCORE_REFERENCED_OTHER) &&
+ pte_test(&pte, PTE_MANAGED)) {
+ /* Ensure that "PHYS_TO_VM_PAGE(pa)->object" doesn't change. */
+ if (vm_page_pa_tryrelock(pmap, pa, locked_pa))
+ goto retry;
+ } else
+out:
+ PA_UNLOCK_COND(*locked_pa);
+ PMAP_UNLOCK(pmap);
+ return (val);
+}
+
+void
+pmap_activate(struct thread *td)
+{
+ pmap_t pmap, oldpmap;
+ struct proc *p = td->td_proc;
+ u_int cpuid;
+
+ critical_enter();
+
+ pmap = vmspace_pmap(p->p_vmspace);
+ oldpmap = PCPU_GET(curpmap);
+ cpuid = PCPU_GET(cpuid);
+
+ if (oldpmap)
+ CPU_CLR_ATOMIC(cpuid, &oldpmap->pm_active);
+ CPU_SET_ATOMIC(cpuid, &pmap->pm_active);
+ pmap_asid_alloc(pmap);
+ if (td == curthread) {
+ PCPU_SET(segbase, pmap->pm_segtab);
+ mips_wr_entryhi(pmap->pm_asid[cpuid].asid);
+ }
+
+ PCPU_SET(curpmap, pmap);
+ critical_exit();
+}
+
+static void
+pmap_sync_icache_one(void *arg __unused)
+{
+
+ mips_icache_sync_all();
+ mips_dcache_wbinv_all();
+}
+
+void
+pmap_sync_icache(pmap_t pm, vm_offset_t va, vm_size_t sz)
+{
+
+ smp_rendezvous(NULL, pmap_sync_icache_one, NULL, NULL);
+}
+
+/*
+ * Increase the starting virtual address of the given mapping if a
+ * different alignment might result in more superpage mappings.
+ */
+void
+pmap_align_superpage(vm_object_t object, vm_ooffset_t offset,
+ vm_offset_t *addr, vm_size_t size)
+{
+ vm_offset_t superpage_offset;
+
+ if (size < NBSEG)
+ return;
+ if (object != NULL && (object->flags & OBJ_COLORED) != 0)
+ offset += ptoa(object->pg_color);
+ superpage_offset = offset & SEGMASK;
+ if (size - ((NBSEG - superpage_offset) & SEGMASK) < NBSEG ||
+ (*addr & SEGMASK) == superpage_offset)
+ return;
+ if ((*addr & SEGMASK) < superpage_offset)
+ *addr = (*addr & ~SEGMASK) + superpage_offset;
+ else
+ *addr = ((*addr + SEGMASK) & ~SEGMASK) + superpage_offset;
+}
+
+#ifdef DDB
+DB_SHOW_COMMAND(ptable, ddb_pid_dump)
+{
+ pmap_t pmap;
+ struct thread *td = NULL;
+ struct proc *p;
+ int i, j, k;
+ vm_paddr_t pa;
+ vm_offset_t va;
+
+ if (have_addr) {
+ td = db_lookup_thread(addr, TRUE);
+ if (td == NULL) {
+ db_printf("Invalid pid or tid");
+ return;
+ }
+ p = td->td_proc;
+ if (p->p_vmspace == NULL) {
+ db_printf("No vmspace for process");
+ return;
+ }
+ pmap = vmspace_pmap(p->p_vmspace);
+ } else
+ pmap = kernel_pmap;
+
+ db_printf("pmap:%p segtab:%p asid:%x generation:%x\n",
+ pmap, pmap->pm_segtab, pmap->pm_asid[0].asid,
+ pmap->pm_asid[0].gen);
+ for (i = 0; i < NPDEPG; i++) {
+ pd_entry_t *pdpe;
+ pt_entry_t *pde;
+ pt_entry_t pte;
+
+ pdpe = (pd_entry_t *)pmap->pm_segtab[i];
+ if (pdpe == NULL)
+ continue;
+ db_printf("[%4d] %p\n", i, pdpe);
+#ifdef __mips_n64
+ for (j = 0; j < NPDEPG; j++) {
+ pde = (pt_entry_t *)pdpe[j];
+ if (pde == NULL)
+ continue;
+ db_printf("\t[%4d] %p\n", j, pde);
+#else
+ {
+ j = 0;
+ pde = (pt_entry_t *)pdpe;
+#endif
+ for (k = 0; k < NPTEPG; k++) {
+ pte = pde[k];
+ if (pte == 0 || !pte_test(&pte, PTE_V))
+ continue;
+ pa = TLBLO_PTE_TO_PA(pte);
+ va = ((u_long)i << SEGSHIFT) | (j << PDRSHIFT) | (k << PAGE_SHIFT);
+ db_printf("\t\t[%04d] va: %p pte: %8jx pa:%jx\n",
+ k, (void *)va, (uintmax_t)pte, (uintmax_t)pa);
+ }
+ }
+ }
+}
+#endif
+
+#if defined(DEBUG)
+
+static void pads(pmap_t pm);
+void pmap_pvdump(vm_offset_t pa);
+
+/* print address space of pmap*/
+static void
+pads(pmap_t pm)
+{
+ unsigned va, i, j;
+ pt_entry_t *ptep;
+
+ if (pm == kernel_pmap)
+ return;
+ for (i = 0; i < NPTEPG; i++)
+ if (pm->pm_segtab[i])
+ for (j = 0; j < NPTEPG; j++) {
+ va = (i << SEGSHIFT) + (j << PAGE_SHIFT);
+ if (pm == kernel_pmap && va < KERNBASE)
+ continue;
+ if (pm != kernel_pmap &&
+ va >= VM_MAXUSER_ADDRESS)
+ continue;
+ ptep = pmap_pte(pm, va);
+ if (pte_test(ptep, PTE_V))
+ printf("%x:%x ", va, *(int *)ptep);
+ }
+
+}
+
+void
+pmap_pvdump(vm_offset_t pa)
+{
+ register pv_entry_t pv;
+ vm_page_t m;
+
+ printf("pa %x", pa);
+ m = PHYS_TO_VM_PAGE(pa);
+ for (pv = TAILQ_FIRST(&m->md.pv_list); pv;
+ pv = TAILQ_NEXT(pv, pv_list)) {
+ printf(" -> pmap %p, va %x", (void *)pv->pv_pmap, pv->pv_va);
+ pads(pv->pv_pmap);
+ }
+ printf(" ");
+}
+
+/* N/C */
+#endif
+
+
+/*
+ * Allocate TLB address space tag (called ASID or TLBPID) and return it.
+ * It takes almost as much or more time to search the TLB for a
+ * specific ASID and flush those entries as it does to flush the entire TLB.
+ * Therefore, when we allocate a new ASID, we just take the next number. When
+ * we run out of numbers, we flush the TLB, increment the generation count
+ * and start over. ASID zero is reserved for kernel use.
+ */
+static void
+pmap_asid_alloc(pmap)
+ pmap_t pmap;
+{
+ if (pmap->pm_asid[PCPU_GET(cpuid)].asid != PMAP_ASID_RESERVED &&
+ pmap->pm_asid[PCPU_GET(cpuid)].gen == PCPU_GET(asid_generation));
+ else {
+ if (PCPU_GET(next_asid) == pmap_max_asid) {
+ tlb_invalidate_all_user(NULL);
+ PCPU_SET(asid_generation,
+ (PCPU_GET(asid_generation) + 1) & ASIDGEN_MASK);
+ if (PCPU_GET(asid_generation) == 0) {
+ PCPU_SET(asid_generation, 1);
+ }
+ PCPU_SET(next_asid, 1); /* 0 means invalid */
+ }
+ pmap->pm_asid[PCPU_GET(cpuid)].asid = PCPU_GET(next_asid);
+ pmap->pm_asid[PCPU_GET(cpuid)].gen = PCPU_GET(asid_generation);
+ PCPU_SET(next_asid, PCPU_GET(next_asid) + 1);
+ }
+}
+
+static pt_entry_t
+init_pte_prot(vm_page_t m, vm_prot_t access, vm_prot_t prot)
+{
+ pt_entry_t rw;
+
+ if (!(prot & VM_PROT_WRITE))
+ rw = PTE_V | PTE_RO;
+ else if ((m->oflags & VPO_UNMANAGED) == 0) {
+ if ((access & VM_PROT_WRITE) != 0)
+ rw = PTE_V | PTE_D;
+ else
+ rw = PTE_V;
+ } else
+ /* Needn't emulate a modified bit for unmanaged pages. */
+ rw = PTE_V | PTE_D;
+ return (rw);
+}
+
+/*
+ * pmap_emulate_modified : do dirty bit emulation
+ *
+ * On SMP, update just the local TLB, other CPUs will update their
+ * TLBs from PTE lazily, if they get the exception.
+ * Returns 0 in case of sucess, 1 if the page is read only and we
+ * need to fault.
+ */
+int
+pmap_emulate_modified(pmap_t pmap, vm_offset_t va)
+{
+ pt_entry_t *pte;
+
+ PMAP_LOCK(pmap);
+ pte = pmap_pte(pmap, va);
+ if (pte == NULL)
+ panic("pmap_emulate_modified: can't find PTE");
+#ifdef SMP
+ /* It is possible that some other CPU changed m-bit */
+ if (!pte_test(pte, PTE_V) || pte_test(pte, PTE_D)) {
+ tlb_update(pmap, va, *pte);
+ PMAP_UNLOCK(pmap);
+ return (0);
+ }
+#else
+ if (!pte_test(pte, PTE_V) || pte_test(pte, PTE_D))
+ panic("pmap_emulate_modified: invalid pte");
+#endif
+ if (pte_test(pte, PTE_RO)) {
+ PMAP_UNLOCK(pmap);
+ return (1);
+ }
+ pte_set(pte, PTE_D);
+ tlb_update(pmap, va, *pte);
+ if (!pte_test(pte, PTE_MANAGED))
+ panic("pmap_emulate_modified: unmanaged page");
+ PMAP_UNLOCK(pmap);
+ return (0);
+}
+
+/*
+ * Routine: pmap_kextract
+ * Function:
+ * Extract the physical page address associated
+ * virtual address.
+ */
+vm_paddr_t
+pmap_kextract(vm_offset_t va)
+{
+ int mapped;
+
+ /*
+ * First, the direct-mapped regions.
+ */
+#if defined(__mips_n64)
+ if (va >= MIPS_XKPHYS_START && va < MIPS_XKPHYS_END)
+ return (MIPS_XKPHYS_TO_PHYS(va));
+#endif
+ if (va >= MIPS_KSEG0_START && va < MIPS_KSEG0_END)
+ return (MIPS_KSEG0_TO_PHYS(va));
+
+ if (va >= MIPS_KSEG1_START && va < MIPS_KSEG1_END)
+ return (MIPS_KSEG1_TO_PHYS(va));
+
+ /*
+ * User virtual addresses.
+ */
+ if (va < VM_MAXUSER_ADDRESS) {
+ pt_entry_t *ptep;
+
+ if (curproc && curproc->p_vmspace) {
+ ptep = pmap_pte(&curproc->p_vmspace->vm_pmap, va);
+ if (ptep) {
+ return (TLBLO_PTE_TO_PA(*ptep) |
+ (va & PAGE_MASK));
+ }
+ return (0);
+ }
+ }
+
+ /*
+ * Should be kernel virtual here, otherwise fail
+ */
+ mapped = (va >= MIPS_KSEG2_START || va < MIPS_KSEG2_END);
+#if defined(__mips_n64)
+ mapped = mapped || (va >= MIPS_XKSEG_START || va < MIPS_XKSEG_END);
+#endif
+ /*
+ * Kernel virtual.
+ */
+
+ if (mapped) {
+ pt_entry_t *ptep;
+
+ /* Is the kernel pmap initialized? */
+ if (!CPU_EMPTY(&kernel_pmap->pm_active)) {
+ /* It's inside the virtual address range */
+ ptep = pmap_pte(kernel_pmap, va);
+ if (ptep) {
+ return (TLBLO_PTE_TO_PA(*ptep) |
+ (va & PAGE_MASK));
+ }
+ }
+ return (0);
+ }
+
+ panic("%s for unknown address space %p.", __func__, (void *)va);
+}
+
+
+void
+pmap_flush_pvcache(vm_page_t m)
+{
+ pv_entry_t pv;
+
+ if (m != NULL) {
+ for (pv = TAILQ_FIRST(&m->md.pv_list); pv;
+ pv = TAILQ_NEXT(pv, pv_list)) {
+ mips_dcache_wbinv_range_index(pv->pv_va, PAGE_SIZE);
+ }
+ }
+}
Property changes on: trunk/sys/mips/mips/pmap.c
___________________________________________________________________
Added: svn:eol-style
## -0,0 +1 ##
+native
\ No newline at end of property
Added: svn:keywords
## -0,0 +1 ##
+MidnightBSD=%H
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+text/plain
\ No newline at end of property
Added: trunk/sys/mips/mips/ptrace_machdep.c
===================================================================
--- trunk/sys/mips/mips/ptrace_machdep.c (rev 0)
+++ trunk/sys/mips/mips/ptrace_machdep.c 2018-05-26 21:55:02 UTC (rev 9987)
@@ -0,0 +1,38 @@
+/* $MidnightBSD$ */
+/*-
+ * Copyright (c) 2009 M. Warner Losh.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ */
+
+#if 0
+#include <sys/cdefs.h>
+__FBSDID("$FreeBSD: stable/10/sys/mips/mips/ptrace_machdep.c 202105 2010-01-11 19:21:52Z imp $");
+
+/*
+ * This file is a place holder for MIPS. Some models of MIPS may need special
+ * functions here, but for now nothing is needed. The MI parts of ptrace
+ * suffice.
+ */
+#endif
Property changes on: trunk/sys/mips/mips/ptrace_machdep.c
___________________________________________________________________
Added: svn:eol-style
## -0,0 +1 ##
+native
\ No newline at end of property
Added: svn:keywords
## -0,0 +1 ##
+MidnightBSD=%H
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+text/plain
\ No newline at end of property
Added: trunk/sys/mips/mips/sc_machdep.c
===================================================================
--- trunk/sys/mips/mips/sc_machdep.c (rev 0)
+++ trunk/sys/mips/mips/sc_machdep.c 2018-05-26 21:55:02 UTC (rev 9987)
@@ -0,0 +1,91 @@
+/* $MidnightBSD$ */
+/*-
+ * Copyright (c) 2003 Jake Burkholder.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ */
+
+#include <sys/cdefs.h>
+__FBSDID("$FreeBSD: stable/10/sys/mips/mips/sc_machdep.c 239670 2012-08-25 08:09:37Z rwatson $");
+
+#include <sys/param.h>
+#include <sys/systm.h>
+#include <sys/kernel.h>
+#include <sys/module.h>
+#include <sys/bus.h>
+#include <sys/cons.h>
+#include <sys/kbio.h>
+#include <sys/consio.h>
+#include <sys/sysctl.h>
+
+#include <dev/syscons/syscons.h>
+
+static sc_softc_t sc_softcs[8];
+
+int
+sc_get_cons_priority(int *unit, int *flags)
+{
+
+ *unit = 0;
+ *flags = 0;
+ return (CN_INTERNAL);
+}
+
+int
+sc_max_unit(void)
+{
+ return (1);
+}
+
+sc_softc_t *
+sc_get_softc(int unit, int flags)
+{
+ sc_softc_t *sc;
+
+ if (unit < 0)
+ return (NULL);
+ sc = &sc_softcs[unit];
+ sc->unit = unit;
+ if ((sc->flags & SC_INIT_DONE) == 0) {
+ sc->keyboard = -1;
+ sc->adapter = -1;
+ sc->cursor_char = SC_CURSOR_CHAR;
+ sc->mouse_char = SC_MOUSE_CHAR;
+ }
+ return (sc);
+}
+
+void
+sc_get_bios_values(bios_values_t *values)
+{
+ values->cursor_start = 0;
+ values->cursor_end = 32;
+ values->shift_state = 0;
+}
+
+int
+sc_tone(int hz)
+{
+ return (0);
+}
Property changes on: trunk/sys/mips/mips/sc_machdep.c
___________________________________________________________________
Added: svn:eol-style
## -0,0 +1 ##
+native
\ No newline at end of property
Added: svn:keywords
## -0,0 +1 ##
+MidnightBSD=%H
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+text/plain
\ No newline at end of property
Added: trunk/sys/mips/mips/stack_machdep.c
===================================================================
--- trunk/sys/mips/mips/stack_machdep.c (rev 0)
+++ trunk/sys/mips/mips/stack_machdep.c 2018-05-26 21:55:02 UTC (rev 9987)
@@ -0,0 +1,157 @@
+/* $MidnightBSD$ */
+/*-
+ * Copyright (c) 2005 Antoine Brodin
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ */
+
+#include <sys/cdefs.h>
+__FBSDID("$FreeBSD: stable/10/sys/mips/mips/stack_machdep.c 250576 2013-05-12 16:43:26Z eadler $");
+
+#include <sys/types.h>
+#include <sys/systm.h>
+#include <sys/param.h>
+#include <sys/proc.h>
+#include <sys/stack.h>
+
+#include <machine/mips_opcode.h>
+
+#include <machine/param.h>
+#include <machine/pcb.h>
+#include <machine/regnum.h>
+
+static u_register_t
+stack_register_fetch(u_register_t sp, u_register_t stack_pos)
+{
+ u_register_t * stack =
+ ((u_register_t *)(intptr_t)sp + (size_t)stack_pos/sizeof(u_register_t));
+
+ return *stack;
+}
+
+static void
+stack_capture(struct stack *st, u_register_t pc, u_register_t sp)
+{
+ u_register_t ra = 0, i, stacksize;
+ short ra_stack_pos = 0;
+ InstFmt insn;
+
+ stack_zero(st);
+
+ for (;;) {
+ stacksize = 0;
+ if (pc <= (u_register_t)(intptr_t)btext)
+ break;
+ for (i = pc; i >= (u_register_t)(intptr_t)btext; i -= sizeof (insn)) {
+ bcopy((void *)(intptr_t)i, &insn, sizeof insn);
+ switch (insn.IType.op) {
+ case OP_ADDI:
+ case OP_ADDIU:
+ case OP_DADDI:
+ case OP_DADDIU:
+ if (insn.IType.rs != SP || insn.IType.rt != SP)
+ break;
+ stacksize = -(short)insn.IType.imm;
+ break;
+
+ case OP_SW:
+ case OP_SD:
+ if (insn.IType.rs != SP || insn.IType.rt != RA)
+ break;
+ ra_stack_pos = (short)insn.IType.imm;
+ break;
+ default:
+ break;
+ }
+
+ if (stacksize)
+ break;
+ }
+
+ if (stack_put(st, pc) == -1)
+ break;
+
+ for (i = pc; !ra; i += sizeof (insn)) {
+ bcopy((void *)(intptr_t)i, &insn, sizeof insn);
+
+ switch (insn.IType.op) {
+ case OP_SPECIAL:
+ if((insn.RType.func == OP_JR))
+ {
+ if (ra >= (u_register_t)(intptr_t)btext)
+ break;
+ if (insn.RType.rs != RA)
+ break;
+ ra = stack_register_fetch(sp,
+ ra_stack_pos);
+ if (!ra)
+ goto done;
+ ra -= 8;
+ }
+ break;
+ default:
+ break;
+ }
+ /* eret */
+ if (insn.word == 0x42000018)
+ goto done;
+ }
+
+ if (pc == ra && stacksize == 0)
+ break;
+
+ sp += stacksize;
+ pc = ra;
+ ra = 0;
+ }
+done:
+ return;
+}
+
+void
+stack_save_td(struct stack *st, struct thread *td)
+{
+ u_register_t pc, sp;
+
+ if (TD_IS_SWAPPED(td))
+ panic("stack_save_td: swapped");
+ if (TD_IS_RUNNING(td))
+ panic("stack_save_td: running");
+
+ pc = td->td_pcb->pcb_regs.pc;
+ sp = td->td_pcb->pcb_regs.sp;
+ stack_capture(st, pc, sp);
+}
+
+void
+stack_save(struct stack *st)
+{
+ u_register_t pc, sp;
+
+ if (curthread == NULL)
+ panic("stack_save: curthread == NULL");
+
+ pc = curthread->td_pcb->pcb_regs.pc;
+ sp = curthread->td_pcb->pcb_regs.sp;
+ stack_capture(st, pc, sp);
+}
Property changes on: trunk/sys/mips/mips/stack_machdep.c
___________________________________________________________________
Added: svn:eol-style
## -0,0 +1 ##
+native
\ No newline at end of property
Added: svn:keywords
## -0,0 +1 ##
+MidnightBSD=%H
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+text/plain
\ No newline at end of property
Added: trunk/sys/mips/mips/stdatomic.c
===================================================================
--- trunk/sys/mips/mips/stdatomic.c (rev 0)
+++ trunk/sys/mips/mips/stdatomic.c 2018-05-26 21:55:02 UTC (rev 9987)
@@ -0,0 +1,397 @@
+/* $MidnightBSD$ */
+/*-
+ * Copyright (c) 2013 Ed Schouten <ed at FreeBSD.org>
+ * All rights reserved.
+ *
+ * Copyright (c) 1998 Doug Rabson
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ */
+
+#include <sys/cdefs.h>
+__FBSDID("$FreeBSD: stable/10/sys/mips/mips/stdatomic.c 251781 2013-06-15 08:15:22Z ed $");
+
+#include <sys/stdatomic.h>
+#include <sys/types.h>
+
+#ifdef _KERNEL
+#include "opt_global.h"
+#endif
+
+#if defined(__SYNC_ATOMICS)
+
+/*
+ * Memory barriers.
+ *
+ * It turns out __sync_synchronize() does not emit any code when used
+ * with GCC 4.2. Implement our own version that does work reliably.
+ *
+ * Although __sync_lock_test_and_set() should only perform an acquire
+ * barrier, make it do a full barrier like the other functions. This
+ * should make <stdatomic.h>'s atomic_exchange_explicit() work reliably.
+ */
+
+static inline void
+do_sync(void)
+{
+
+ __asm volatile (
+#if !defined(_KERNEL) || defined(SMP)
+ ".set noreorder\n"
+ "\tsync\n"
+ "\tnop\n"
+ "\tnop\n"
+ "\tnop\n"
+ "\tnop\n"
+ "\tnop\n"
+ "\tnop\n"
+ "\tnop\n"
+ "\tnop\n"
+ ".set reorder\n"
+#else /* _KERNEL && !SMP */
+ ""
+#endif /* !KERNEL || SMP */
+ : : : "memory");
+}
+
+typedef union {
+ uint8_t v8[4];
+ uint32_t v32;
+} reg_t;
+
+/*
+ * Given a memory address pointing to an 8-bit or 16-bit integer, return
+ * the address of the 32-bit word containing it.
+ */
+
+static inline uint32_t *
+round_to_word(void *ptr)
+{
+
+ return ((uint32_t *)((intptr_t)ptr & ~3));
+}
+
+/*
+ * Utility functions for loading and storing 8-bit and 16-bit integers
+ * in 32-bit words at an offset corresponding with the location of the
+ * atomic variable.
+ */
+
+static inline void
+put_1(reg_t *r, const uint8_t *offset_ptr, uint8_t val)
+{
+ size_t offset;
+
+ offset = (intptr_t)offset_ptr & 3;
+ r->v8[offset] = val;
+}
+
+static inline uint8_t
+get_1(const reg_t *r, const uint8_t *offset_ptr)
+{
+ size_t offset;
+
+ offset = (intptr_t)offset_ptr & 3;
+ return (r->v8[offset]);
+}
+
+static inline void
+put_2(reg_t *r, const uint16_t *offset_ptr, uint16_t val)
+{
+ size_t offset;
+ union {
+ uint16_t in;
+ uint8_t out[2];
+ } bytes;
+
+ offset = (intptr_t)offset_ptr & 3;
+ bytes.in = val;
+ r->v8[offset] = bytes.out[0];
+ r->v8[offset + 1] = bytes.out[1];
+}
+
+static inline uint16_t
+get_2(const reg_t *r, const uint16_t *offset_ptr)
+{
+ size_t offset;
+ union {
+ uint8_t in[2];
+ uint16_t out;
+ } bytes;
+
+ offset = (intptr_t)offset_ptr & 3;
+ bytes.in[0] = r->v8[offset];
+ bytes.in[1] = r->v8[offset + 1];
+ return (bytes.out);
+}
+
+/*
+ * 8-bit and 16-bit routines.
+ *
+ * These operations are not natively supported by the CPU, so we use
+ * some shifting and bitmasking on top of the 32-bit instructions.
+ */
+
+#define EMIT_LOCK_TEST_AND_SET_N(N, uintN_t) \
+uintN_t \
+__sync_lock_test_and_set_##N(uintN_t *mem, uintN_t val) \
+{ \
+ uint32_t *mem32; \
+ reg_t val32, negmask, old; \
+ uint32_t temp; \
+ \
+ mem32 = round_to_word(mem); \
+ val32.v32 = 0x00000000; \
+ put_##N(&val32, mem, val); \
+ negmask.v32 = 0xffffffff; \
+ put_##N(&negmask, mem, 0); \
+ \
+ do_sync(); \
+ __asm volatile ( \
+ "1:" \
+ "\tll %0, %5\n" /* Load old value. */ \
+ "\tand %2, %4, %0\n" /* Remove the old value. */ \
+ "\tor %2, %3\n" /* Put in the new value. */ \
+ "\tsc %2, %1\n" /* Attempt to store. */ \
+ "\tbeqz %2, 1b\n" /* Spin if failed. */ \
+ : "=&r" (old.v32), "=m" (*mem32), "=&r" (temp) \
+ : "r" (val32.v32), "r" (negmask.v32), "m" (*mem32)); \
+ return (get_##N(&old, mem)); \
+}
+
+EMIT_LOCK_TEST_AND_SET_N(1, uint8_t)
+EMIT_LOCK_TEST_AND_SET_N(2, uint16_t)
+
+#define EMIT_VAL_COMPARE_AND_SWAP_N(N, uintN_t) \
+uintN_t \
+__sync_val_compare_and_swap_##N(uintN_t *mem, uintN_t expected, \
+ uintN_t desired) \
+{ \
+ uint32_t *mem32; \
+ reg_t expected32, desired32, posmask, old; \
+ uint32_t negmask, temp; \
+ \
+ mem32 = round_to_word(mem); \
+ expected32.v32 = 0x00000000; \
+ put_##N(&expected32, mem, expected); \
+ desired32.v32 = 0x00000000; \
+ put_##N(&desired32, mem, desired); \
+ posmask.v32 = 0x00000000; \
+ put_##N(&posmask, mem, ~0); \
+ negmask = ~posmask.v32; \
+ \
+ do_sync(); \
+ __asm volatile ( \
+ "1:" \
+ "\tll %0, %7\n" /* Load old value. */ \
+ "\tand %2, %5, %0\n" /* Isolate the old value. */ \
+ "\tbne %2, %3, 2f\n" /* Compare to expected value. */\
+ "\tand %2, %6, %0\n" /* Remove the old value. */ \
+ "\tor %2, %4\n" /* Put in the new value. */ \
+ "\tsc %2, %1\n" /* Attempt to store. */ \
+ "\tbeqz %2, 1b\n" /* Spin if failed. */ \
+ "2:" \
+ : "=&r" (old), "=m" (*mem32), "=&r" (temp) \
+ : "r" (expected32.v32), "r" (desired32.v32), \
+ "r" (posmask.v32), "r" (negmask), "m" (*mem32)); \
+ return (get_##N(&old, mem)); \
+}
+
+EMIT_VAL_COMPARE_AND_SWAP_N(1, uint8_t)
+EMIT_VAL_COMPARE_AND_SWAP_N(2, uint16_t)
+
+#define EMIT_ARITHMETIC_FETCH_AND_OP_N(N, uintN_t, name, op) \
+uintN_t \
+__sync_##name##_##N(uintN_t *mem, uintN_t val) \
+{ \
+ uint32_t *mem32; \
+ reg_t val32, posmask, old; \
+ uint32_t negmask, temp1, temp2; \
+ \
+ mem32 = round_to_word(mem); \
+ val32.v32 = 0x00000000; \
+ put_##N(&val32, mem, val); \
+ posmask.v32 = 0x00000000; \
+ put_##N(&posmask, mem, ~0); \
+ negmask = ~posmask.v32; \
+ \
+ do_sync(); \
+ __asm volatile ( \
+ "1:" \
+ "\tll %0, %7\n" /* Load old value. */ \
+ "\t"op" %2, %0, %4\n" /* Calculate new value. */ \
+ "\tand %2, %5\n" /* Isolate the new value. */ \
+ "\tand %3, %6, %0\n" /* Remove the old value. */ \
+ "\tor %2, %3\n" /* Put in the new value. */ \
+ "\tsc %2, %1\n" /* Attempt to store. */ \
+ "\tbeqz %2, 1b\n" /* Spin if failed. */ \
+ : "=&r" (old.v32), "=m" (*mem32), "=&r" (temp1), \
+ "=&r" (temp2) \
+ : "r" (val32.v32), "r" (posmask.v32), "r" (negmask), \
+ "m" (*mem32)); \
+ return (get_##N(&old, mem)); \
+}
+
+EMIT_ARITHMETIC_FETCH_AND_OP_N(1, uint8_t, fetch_and_add, "addu")
+EMIT_ARITHMETIC_FETCH_AND_OP_N(1, uint8_t, fetch_and_sub, "subu")
+EMIT_ARITHMETIC_FETCH_AND_OP_N(2, uint16_t, fetch_and_add, "addu")
+EMIT_ARITHMETIC_FETCH_AND_OP_N(2, uint16_t, fetch_and_sub, "subu")
+
+#define EMIT_BITWISE_FETCH_AND_OP_N(N, uintN_t, name, op, idempotence) \
+uintN_t \
+__sync_##name##_##N(uintN_t *mem, uintN_t val) \
+{ \
+ uint32_t *mem32; \
+ reg_t val32, old; \
+ uint32_t temp; \
+ \
+ mem32 = round_to_word(mem); \
+ val32.v32 = idempotence ? 0xffffffff : 0x00000000; \
+ put_##N(&val32, mem, val); \
+ \
+ do_sync(); \
+ __asm volatile ( \
+ "1:" \
+ "\tll %0, %4\n" /* Load old value. */ \
+ "\t"op" %2, %3, %0\n" /* Calculate new value. */ \
+ "\tsc %2, %1\n" /* Attempt to store. */ \
+ "\tbeqz %2, 1b\n" /* Spin if failed. */ \
+ : "=&r" (old.v32), "=m" (*mem32), "=&r" (temp) \
+ : "r" (val32.v32), "m" (*mem32)); \
+ return (get_##N(&old, mem)); \
+}
+
+EMIT_BITWISE_FETCH_AND_OP_N(1, uint8_t, fetch_and_and, "and", 1)
+EMIT_BITWISE_FETCH_AND_OP_N(1, uint8_t, fetch_and_or, "or", 0)
+EMIT_BITWISE_FETCH_AND_OP_N(1, uint8_t, fetch_and_xor, "xor", 0)
+EMIT_BITWISE_FETCH_AND_OP_N(2, uint16_t, fetch_and_and, "and", 1)
+EMIT_BITWISE_FETCH_AND_OP_N(2, uint16_t, fetch_and_or, "or", 0)
+EMIT_BITWISE_FETCH_AND_OP_N(2, uint16_t, fetch_and_xor, "xor", 0)
+
+/*
+ * 32-bit routines.
+ */
+
+uint32_t
+__sync_val_compare_and_swap_4(uint32_t *mem, uint32_t expected,
+ uint32_t desired)
+{
+ uint32_t old, temp;
+
+ do_sync();
+ __asm volatile (
+ "1:"
+ "\tll %0, %5\n" /* Load old value. */
+ "\tbne %0, %3, 2f\n" /* Compare to expected value. */
+ "\tmove %2, %4\n" /* Value to store. */
+ "\tsc %2, %1\n" /* Attempt to store. */
+ "\tbeqz %2, 1b\n" /* Spin if failed. */
+ "2:"
+ : "=&r" (old), "=m" (*mem), "=&r" (temp)
+ : "r" (expected), "r" (desired), "m" (*mem));
+ return (old);
+}
+
+#define EMIT_FETCH_AND_OP_4(name, op) \
+uint32_t \
+__sync_##name##_4(uint32_t *mem, uint32_t val) \
+{ \
+ uint32_t old, temp; \
+ \
+ do_sync(); \
+ __asm volatile ( \
+ "1:" \
+ "\tll %0, %4\n" /* Load old value. */ \
+ "\t"op"\n" /* Calculate new value. */ \
+ "\tsc %2, %1\n" /* Attempt to store. */ \
+ "\tbeqz %2, 1b\n" /* Spin if failed. */ \
+ : "=&r" (old), "=m" (*mem), "=&r" (temp) \
+ : "r" (val), "m" (*mem)); \
+ return (old); \
+}
+
+EMIT_FETCH_AND_OP_4(lock_test_and_set, "move %2, %3")
+EMIT_FETCH_AND_OP_4(fetch_and_add, "addu %2, %0, %3")
+EMIT_FETCH_AND_OP_4(fetch_and_and, "and %2, %0, %3")
+EMIT_FETCH_AND_OP_4(fetch_and_or, "or %2, %0, %3")
+EMIT_FETCH_AND_OP_4(fetch_and_sub, "subu %2, %0, %3")
+EMIT_FETCH_AND_OP_4(fetch_and_xor, "xor %2, %0, %3")
+
+/*
+ * 64-bit routines.
+ *
+ * Note: All the 64-bit atomic operations are only atomic when running
+ * in 64-bit mode. It is assumed that code compiled for n32 and n64 fits
+ * into this definition and no further safeties are needed.
+ */
+
+#if defined(__mips_n32) || defined(__mips_n64)
+
+uint64_t
+__sync_val_compare_and_swap_8(uint64_t *mem, uint64_t expected,
+ uint64_t desired)
+{
+ uint64_t old, temp;
+
+ do_sync();
+ __asm volatile (
+ "1:"
+ "\tlld %0, %5\n" /* Load old value. */
+ "\tbne %0, %3, 2f\n" /* Compare to expected value. */
+ "\tmove %2, %4\n" /* Value to store. */
+ "\tscd %2, %1\n" /* Attempt to store. */
+ "\tbeqz %2, 1b\n" /* Spin if failed. */
+ "2:"
+ : "=&r" (old), "=m" (*mem), "=&r" (temp)
+ : "r" (expected), "r" (desired), "m" (*mem));
+ return (old);
+}
+
+#define EMIT_FETCH_AND_OP_8(name, op) \
+uint64_t \
+__sync_##name##_8(uint64_t *mem, uint64_t val) \
+{ \
+ uint64_t old, temp; \
+ \
+ do_sync(); \
+ __asm volatile ( \
+ "1:" \
+ "\tlld %0, %4\n" /* Load old value. */ \
+ "\t"op"\n" /* Calculate new value. */ \
+ "\tscd %2, %1\n" /* Attempt to store. */ \
+ "\tbeqz %2, 1b\n" /* Spin if failed. */ \
+ : "=&r" (old), "=m" (*mem), "=&r" (temp) \
+ : "r" (val), "m" (*mem)); \
+ return (old); \
+}
+
+EMIT_FETCH_AND_OP_8(lock_test_and_set, "move %2, %3")
+EMIT_FETCH_AND_OP_8(fetch_and_add, "daddu %2, %0, %3")
+EMIT_FETCH_AND_OP_8(fetch_and_and, "and %2, %0, %3")
+EMIT_FETCH_AND_OP_8(fetch_and_or, "or %2, %0, %3")
+EMIT_FETCH_AND_OP_8(fetch_and_sub, "dsubu %2, %0, %3")
+EMIT_FETCH_AND_OP_8(fetch_and_xor, "xor %2, %0, %3")
+
+#endif /* __mips_n32 || __mips_n64 */
+
+#endif /* __SYNC_ATOMICS */
Property changes on: trunk/sys/mips/mips/stdatomic.c
___________________________________________________________________
Added: svn:eol-style
## -0,0 +1 ##
+native
\ No newline at end of property
Added: svn:keywords
## -0,0 +1 ##
+MidnightBSD=%H
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+text/plain
\ No newline at end of property
Added: trunk/sys/mips/mips/support.S
===================================================================
--- trunk/sys/mips/mips/support.S (rev 0)
+++ trunk/sys/mips/mips/support.S 2018-05-26 21:55:02 UTC (rev 9987)
@@ -0,0 +1,1100 @@
+/* $MidnightBSD$ */
+/* $OpenBSD: locore.S,v 1.18 1998/09/15 10:58:53 pefo Exp $ */
+/*-
+ * Copyright (c) 1992, 1993
+ * The Regents of the University of California. All rights reserved.
+ *
+ * This code is derived from software contributed to Berkeley by
+ * Digital Equipment Corporation and Ralph Campbell.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * 4. Neither the name of the University nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ * Copyright (C) 1989 Digital Equipment Corporation.
+ * Permission to use, copy, modify, and distribute this software and
+ * its documentation for any purpose and without fee is hereby granted,
+ * provided that the above copyright notice appears in all copies.
+ * Digital Equipment Corporation makes no representations about the
+ * suitability of this software for any purpose. It is provided "as is"
+ * without express or implied warranty.
+ *
+ * from: Header: /sprite/src/kernel/mach/ds3100.md/RCS/loMem.s,
+ * v 1.1 89/07/11 17:55:04 nelson Exp SPRITE (DECWRL)
+ * from: Header: /sprite/src/kernel/mach/ds3100.md/RCS/machAsm.s,
+ * v 9.2 90/01/29 18:00:39 shirriff Exp SPRITE (DECWRL)
+ * from: Header: /sprite/src/kernel/vm/ds3100.md/vmPmaxAsm.s,
+ * v 1.1 89/07/10 14:27:41 nelson Exp SPRITE (DECWRL)
+ *
+ * from: @(#)locore.s 8.5 (Berkeley) 1/4/94
+ * JNPR: support.S,v 1.5.2.2 2007/08/29 10:03:49 girish
+ * $FreeBSD: stable/10/sys/mips/mips/support.S 255367 2013-09-07 16:31:30Z jchandra $
+ */
+
+/*
+ * Copyright (c) 1997 Jonathan Stone (hereinafter referred to as the author)
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * 3. All advertising materials mentioning features or use of this software
+ * must display the following acknowledgement:
+ * This product includes software developed by Jonathan R. Stone for
+ * the NetBSD Project.
+ * 4. The name of the author may not be used to endorse or promote products
+ * derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ */
+
+/*
+ * Contains assembly language support routines.
+ */
+
+#include "opt_ddb.h"
+#include <sys/errno.h>
+#include <machine/asm.h>
+#include <machine/cpu.h>
+#include <machine/regnum.h>
+#include <machine/cpuregs.h>
+#include <machine/pcb.h>
+
+#include "assym.s"
+
+ .set noreorder # Noreorder is default style!
+
+/*
+ * Primitives
+ */
+
+ .text
+
+/*
+ * See if access to addr with a len type instruction causes a machine check.
+ * len is length of access (1=byte, 2=short, 4=int)
+ *
+ * badaddr(addr, len)
+ * char *addr;
+ * int len;
+ */
+LEAF(badaddr)
+ PTR_LA v0, baderr
+ GET_CPU_PCPU(v1)
+ PTR_L v1, PC_CURPCB(v1)
+ bne a1, 1, 2f
+ PTR_S v0, U_PCB_ONFAULT(v1)
+ b 5f
+ lbu v0, (a0)
+2:
+ bne a1, 2, 4f
+ nop
+ b 5f
+ lhu v0, (a0)
+4:
+ lw v0, (a0)
+5:
+ PTR_S zero, U_PCB_ONFAULT(v1)
+ j ra
+ move v0, zero # made it w/o errors
+baderr:
+ j ra
+ li v0, 1 # trap sends us here
+END(badaddr)
+
+/*
+ * int copystr(void *kfaddr, void *kdaddr, size_t maxlen, size_t *lencopied)
+ * Copy a NIL-terminated string, at most maxlen characters long. Return the
+ * number of characters copied (including the NIL) in *lencopied. If the
+ * string is too long, return ENAMETOOLONG; else return 0.
+ */
+LEAF(copystr)
+ move t0, a2
+ beq a2, zero, 4f
+1:
+ lbu v0, 0(a0)
+ PTR_SUBU a2, a2, 1
+ beq v0, zero, 2f
+ sb v0, 0(a1) # each byte until NIL
+ PTR_ADDU a0, a0, 1
+ bne a2, zero, 1b # less than maxlen
+ PTR_ADDU a1, a1, 1
+4:
+ li v0, ENAMETOOLONG # run out of space
+2:
+ beq a3, zero, 3f # return num. of copied bytes
+ PTR_SUBU a2, t0, a2 # if the 4th arg was non-NULL
+ PTR_S a2, 0(a3)
+3:
+ j ra # v0 is 0 or ENAMETOOLONG
+ nop
+END(copystr)
+
+
+/*
+ * Copy a null terminated string from the user address space into
+ * the kernel address space.
+ *
+ * copyinstr(fromaddr, toaddr, maxlength, &lencopied)
+ * caddr_t fromaddr;
+ * caddr_t toaddr;
+ * u_int maxlength;
+ * u_int *lencopied;
+ */
+NON_LEAF(copyinstr, CALLFRAME_SIZ, ra)
+ PTR_SUBU sp, sp, CALLFRAME_SIZ
+ .mask 0x80000000, (CALLFRAME_RA - CALLFRAME_SIZ)
+ PTR_LA v0, copyerr
+ blt a0, zero, _C_LABEL(copyerr) # make sure address is in user space
+ REG_S ra, CALLFRAME_RA(sp)
+ GET_CPU_PCPU(v1)
+ PTR_L v1, PC_CURPCB(v1)
+ jal _C_LABEL(copystr)
+ PTR_S v0, U_PCB_ONFAULT(v1)
+ REG_L ra, CALLFRAME_RA(sp)
+ GET_CPU_PCPU(v1)
+ PTR_L v1, PC_CURPCB(v1)
+ PTR_S zero, U_PCB_ONFAULT(v1)
+ j ra
+ PTR_ADDU sp, sp, CALLFRAME_SIZ
+END(copyinstr)
+
+/*
+ * Copy a null terminated string from the kernel address space into
+ * the user address space.
+ *
+ * copyoutstr(fromaddr, toaddr, maxlength, &lencopied)
+ * caddr_t fromaddr;
+ * caddr_t toaddr;
+ * u_int maxlength;
+ * u_int *lencopied;
+ */
+NON_LEAF(copyoutstr, CALLFRAME_SIZ, ra)
+ PTR_SUBU sp, sp, CALLFRAME_SIZ
+ .mask 0x80000000, (CALLFRAME_RA - CALLFRAME_SIZ)
+ PTR_LA v0, copyerr
+ blt a1, zero, _C_LABEL(copyerr) # make sure address is in user space
+ REG_S ra, CALLFRAME_RA(sp)
+ GET_CPU_PCPU(v1)
+ PTR_L v1, PC_CURPCB(v1)
+ jal _C_LABEL(copystr)
+ PTR_S v0, U_PCB_ONFAULT(v1)
+ REG_L ra, CALLFRAME_RA(sp)
+ GET_CPU_PCPU(v1)
+ PTR_L v1, PC_CURPCB(v1)
+ PTR_S zero, U_PCB_ONFAULT(v1)
+ j ra
+ PTR_ADDU sp, sp, CALLFRAME_SIZ
+END(copyoutstr)
+
+/*
+ * Copy specified amount of data from user space into the kernel
+ * copyin(from, to, len)
+ * caddr_t *from; (user source address)
+ * caddr_t *to; (kernel destination address)
+ * unsigned len;
+ */
+NON_LEAF(copyin, CALLFRAME_SIZ, ra)
+ PTR_SUBU sp, sp, CALLFRAME_SIZ
+ .mask 0x80000000, (CALLFRAME_RA - CALLFRAME_SIZ)
+ PTR_LA v0, copyerr
+ blt a0, zero, _C_LABEL(copyerr) # make sure address is in user space
+ REG_S ra, CALLFRAME_RA(sp)
+ GET_CPU_PCPU(v1)
+ PTR_L v1, PC_CURPCB(v1)
+ jal _C_LABEL(bcopy)
+ PTR_S v0, U_PCB_ONFAULT(v1)
+ REG_L ra, CALLFRAME_RA(sp)
+ GET_CPU_PCPU(v1)
+ PTR_L v1, PC_CURPCB(v1) # bcopy modified v1, so reload
+ PTR_S zero, U_PCB_ONFAULT(v1)
+ PTR_ADDU sp, sp, CALLFRAME_SIZ
+ j ra
+ move v0, zero
+END(copyin)
+
+/*
+ * Copy specified amount of data from kernel to the user space
+ * copyout(from, to, len)
+ * caddr_t *from; (kernel source address)
+ * caddr_t *to; (user destination address)
+ * unsigned len;
+ */
+NON_LEAF(copyout, CALLFRAME_SIZ, ra)
+ PTR_SUBU sp, sp, CALLFRAME_SIZ
+ .mask 0x80000000, (CALLFRAME_RA - CALLFRAME_SIZ)
+ PTR_LA v0, copyerr
+ blt a1, zero, _C_LABEL(copyerr) # make sure address is in user space
+ REG_S ra, CALLFRAME_RA(sp)
+ GET_CPU_PCPU(v1)
+ PTR_L v1, PC_CURPCB(v1)
+ jal _C_LABEL(bcopy)
+ PTR_S v0, U_PCB_ONFAULT(v1)
+ REG_L ra, CALLFRAME_RA(sp)
+ GET_CPU_PCPU(v1)
+ PTR_L v1, PC_CURPCB(v1) # bcopy modified v1, so reload
+ PTR_S zero, U_PCB_ONFAULT(v1)
+ PTR_ADDU sp, sp, CALLFRAME_SIZ
+ j ra
+ move v0, zero
+END(copyout)
+
+LEAF(copyerr)
+ REG_L ra, CALLFRAME_RA(sp)
+ PTR_ADDU sp, sp, CALLFRAME_SIZ
+ j ra
+ li v0, EFAULT # return error
+END(copyerr)
+
+/*
+ * {fu,su},{ibyte,isword,iword}, fetch or store a byte, short or word to
+ * user text space.
+ * {fu,su},{byte,sword,word}, fetch or store a byte, short or word to
+ * user data space.
+ */
+#ifdef __mips_n64
+LEAF(fuword64)
+ALEAF(fuword)
+ PTR_LA v0, fswberr
+ blt a0, zero, fswberr # make sure address is in user space
+ nop
+ GET_CPU_PCPU(v1)
+ PTR_L v1, PC_CURPCB(v1)
+ PTR_S v0, U_PCB_ONFAULT(v1)
+ ld v0, 0(a0) # fetch word
+ j ra
+ PTR_S zero, U_PCB_ONFAULT(v1)
+END(fuword64)
+#endif
+
+LEAF(fuword32)
+#ifndef __mips_n64
+ALEAF(fuword)
+#endif
+ PTR_LA v0, fswberr
+ blt a0, zero, fswberr # make sure address is in user space
+ nop
+ GET_CPU_PCPU(v1)
+ PTR_L v1, PC_CURPCB(v1)
+ PTR_S v0, U_PCB_ONFAULT(v1)
+ lw v0, 0(a0) # fetch word
+ j ra
+ PTR_S zero, U_PCB_ONFAULT(v1)
+END(fuword32)
+
+LEAF(fusword)
+ PTR_LA v0, fswberr
+ blt a0, zero, fswberr # make sure address is in user space
+ nop
+ GET_CPU_PCPU(v1)
+ PTR_L v1, PC_CURPCB(v1)
+ PTR_S v0, U_PCB_ONFAULT(v1)
+ lhu v0, 0(a0) # fetch short
+ j ra
+ PTR_S zero, U_PCB_ONFAULT(v1)
+END(fusword)
+
+LEAF(fubyte)
+ PTR_LA v0, fswberr
+ blt a0, zero, fswberr # make sure address is in user space
+ nop
+ GET_CPU_PCPU(v1)
+ PTR_L v1, PC_CURPCB(v1)
+ PTR_S v0, U_PCB_ONFAULT(v1)
+ lbu v0, 0(a0) # fetch byte
+ j ra
+ PTR_S zero, U_PCB_ONFAULT(v1)
+END(fubyte)
+
+LEAF(suword32)
+#ifndef __mips_n64
+XLEAF(suword)
+#endif
+ PTR_LA v0, fswberr
+ blt a0, zero, fswberr # make sure address is in user space
+ nop
+ GET_CPU_PCPU(v1)
+ PTR_L v1, PC_CURPCB(v1)
+ PTR_S v0, U_PCB_ONFAULT(v1)
+ sw a1, 0(a0) # store word
+ PTR_S zero, U_PCB_ONFAULT(v1)
+ j ra
+ move v0, zero
+END(suword32)
+
+#ifdef __mips_n64
+LEAF(suword64)
+XLEAF(suword)
+ PTR_LA v0, fswberr
+ blt a0, zero, fswberr # make sure address is in user space
+ nop
+ GET_CPU_PCPU(v1)
+ PTR_L v1, PC_CURPCB(v1)
+ PTR_S v0, U_PCB_ONFAULT(v1)
+ sd a1, 0(a0) # store word
+ PTR_S zero, U_PCB_ONFAULT(v1)
+ j ra
+ move v0, zero
+END(suword64)
+#endif
+
+/*
+ * casuword(9)
+ * <v0>u_long casuword(<a0>u_long *p, <a1>u_long oldval, <a2>u_long newval)
+ */
+/*
+ * casuword32(9)
+ * <v0>uint32_t casuword(<a0>uint32_t *p, <a1>uint32_t oldval,
+ * <a2>uint32_t newval)
+ */
+LEAF(casuword32)
+#ifndef __mips_n64
+XLEAF(casuword)
+#endif
+ PTR_LA v0, fswberr
+ blt a0, zero, fswberr # make sure address is in user space
+ nop
+ GET_CPU_PCPU(v1)
+ PTR_L v1, PC_CURPCB(v1)
+ PTR_S v0, U_PCB_ONFAULT(v1)
+1:
+ move t0, a2
+ ll v0, 0(a0)
+ bne a1, v0, 2f
+ nop
+ sc t0, 0(a0) # store word
+ beqz t0, 1b
+ nop
+ j 3f
+ nop
+2:
+ li v0, -1
+3:
+ PTR_S zero, U_PCB_ONFAULT(v1)
+ jr ra
+ nop
+END(casuword32)
+
+#ifdef __mips_n64
+LEAF(casuword64)
+XLEAF(casuword)
+ PTR_LA v0, fswberr
+ blt a0, zero, fswberr # make sure address is in user space
+ nop
+ GET_CPU_PCPU(v1)
+ PTR_L v1, PC_CURPCB(v1)
+ PTR_S v0, U_PCB_ONFAULT(v1)
+1:
+ move t0, a2
+ lld v0, 0(a0)
+ bne a1, v0, 2f
+ nop
+ scd t0, 0(a0) # store double word
+ beqz t0, 1b
+ nop
+ j 3f
+ nop
+2:
+ li v0, -1
+3:
+ PTR_S zero, U_PCB_ONFAULT(v1)
+ jr ra
+ nop
+END(casuword64)
+#endif
+
+/*
+ * Will have to flush the instruction cache if byte merging is done in hardware.
+ */
+LEAF(susword)
+ PTR_LA v0, fswberr
+ blt a0, zero, fswberr # make sure address is in user space
+ nop
+ GET_CPU_PCPU(v1)
+ PTR_L v1, PC_CURPCB(v1)
+ PTR_S v0, U_PCB_ONFAULT(v1)
+ sh a1, 0(a0) # store short
+ PTR_S zero, U_PCB_ONFAULT(v1)
+ j ra
+ move v0, zero
+END(susword)
+
+LEAF(subyte)
+ PTR_LA v0, fswberr
+ blt a0, zero, fswberr # make sure address is in user space
+ nop
+ GET_CPU_PCPU(v1)
+ PTR_L v1, PC_CURPCB(v1)
+ PTR_S v0, U_PCB_ONFAULT(v1)
+ sb a1, 0(a0) # store byte
+ PTR_S zero, U_PCB_ONFAULT(v1)
+ j ra
+ move v0, zero
+END(subyte)
+
+LEAF(fswberr)
+ j ra
+ li v0, -1
+END(fswberr)
+
+/*
+ * fuswintr and suswintr are just like fusword and susword except that if
+ * the page is not in memory or would cause a trap, then we return an error.
+ * The important thing is to prevent sleep() and switch().
+ */
+LEAF(fuswintr)
+ PTR_LA v0, fswintrberr
+ blt a0, zero, fswintrberr # make sure address is in user space
+ nop
+ GET_CPU_PCPU(v1)
+ PTR_L v1, PC_CURPCB(v1)
+ PTR_S v0, U_PCB_ONFAULT(v1)
+ lhu v0, 0(a0) # fetch short
+ j ra
+ PTR_S zero, U_PCB_ONFAULT(v1)
+END(fuswintr)
+
+LEAF(suswintr)
+ PTR_LA v0, fswintrberr
+ blt a0, zero, fswintrberr # make sure address is in user space
+ nop
+ GET_CPU_PCPU(v1)
+ PTR_L v1, PC_CURPCB(v1)
+ PTR_S v0, U_PCB_ONFAULT(v1)
+ sh a1, 0(a0) # store short
+ PTR_S zero, U_PCB_ONFAULT(v1)
+ j ra
+ move v0, zero
+END(suswintr)
+
+LEAF(fswintrberr)
+ j ra
+ li v0, -1
+END(fswintrberr)
+
+/*
+ * memset(void *s1, int c, int len)
+ * NetBSD: memset.S,v 1.3 2001/10/16 15:40:53 uch Exp
+ */
+LEAF(memset)
+ .set noreorder
+ blt a2, 12, memsetsmallclr # small amount to clear?
+ move v0, a0 # save s1 for result
+
+ sll t1, a1, 8 # compute c << 8 in t1
+ or t1, t1, a1 # compute c << 8 | c in 11
+ sll t2, t1, 16 # shift that left 16
+ or t1, t2, t1 # or together
+
+ PTR_SUBU t0, zero, a0 # compute # bytes to word align address
+ and t0, t0, 3
+ beq t0, zero, 1f # skip if word aligned
+ PTR_SUBU a2, a2, t0 # subtract from remaining count
+ SWHI t1, 0(a0) # store 1, 2, or 3 bytes to align
+ PTR_ADDU a0, a0, t0
+1:
+ and v1, a2, 3 # compute number of whole words left
+ PTR_SUBU t0, a2, v1
+ PTR_SUBU a2, a2, t0
+ PTR_ADDU t0, t0, a0 # compute ending address
+2:
+ PTR_ADDU a0, a0, 4 # clear words
+ bne a0, t0, 2b # unrolling loop does not help
+ sw t1, -4(a0) # since we are limited by memory speed
+
+memsetsmallclr:
+ ble a2, zero, 2f
+ PTR_ADDU t0, a2, a0 # compute ending address
+1:
+ PTR_ADDU a0, a0, 1 # clear bytes
+ bne a0, t0, 1b
+ sb a1, -1(a0)
+2:
+ j ra
+ nop
+ .set reorder
+END(memset)
+
+/*
+ * bzero(s1, n)
+ */
+LEAF(bzero)
+ALEAF(blkclr)
+ .set noreorder
+ blt a1, 12, smallclr # small amount to clear?
+ PTR_SUBU a3, zero, a0 # compute # bytes to word align address
+ and a3, a3, 3
+ beq a3, zero, 1f # skip if word aligned
+ PTR_SUBU a1, a1, a3 # subtract from remaining count
+ SWHI zero, 0(a0) # clear 1, 2, or 3 bytes to align
+ PTR_ADDU a0, a0, a3
+1:
+ and v0, a1, 3 # compute number of words left
+ PTR_SUBU a3, a1, v0
+ move a1, v0
+ PTR_ADDU a3, a3, a0 # compute ending address
+2:
+ PTR_ADDU a0, a0, 4 # clear words
+ bne a0, a3, 2b # unrolling loop does not help
+ sw zero, -4(a0) # since we are limited by memory speed
+smallclr:
+ ble a1, zero, 2f
+ PTR_ADDU a3, a1, a0 # compute ending address
+1:
+ PTR_ADDU a0, a0, 1 # clear bytes
+ bne a0, a3, 1b
+ sb zero, -1(a0)
+2:
+ j ra
+ nop
+END(bzero)
+
+
+/*
+ * bcmp(s1, s2, n)
+ */
+LEAF(bcmp)
+ .set noreorder
+ blt a2, 16, smallcmp # is it worth any trouble?
+ xor v0, a0, a1 # compare low two bits of addresses
+ and v0, v0, 3
+ PTR_SUBU a3, zero, a1 # compute # bytes to word align address
+ bne v0, zero, unalignedcmp # not possible to align addresses
+ and a3, a3, 3
+
+ beq a3, zero, 1f
+ PTR_SUBU a2, a2, a3 # subtract from remaining count
+ move v0, v1 # init v0,v1 so unmodified bytes match
+ LWHI v0, 0(a0) # read 1, 2, or 3 bytes
+ LWHI v1, 0(a1)
+ PTR_ADDU a1, a1, a3
+ bne v0, v1, nomatch
+ PTR_ADDU a0, a0, a3
+1:
+ and a3, a2, ~3 # compute number of whole words left
+ PTR_SUBU a2, a2, a3 # which has to be >= (16-3) & ~3
+ PTR_ADDU a3, a3, a0 # compute ending address
+2:
+ lw v0, 0(a0) # compare words
+ lw v1, 0(a1)
+ PTR_ADDU a0, a0, 4
+ bne v0, v1, nomatch
+ PTR_ADDU a1, a1, 4
+ bne a0, a3, 2b
+ nop
+ b smallcmp # finish remainder
+ nop
+unalignedcmp:
+ beq a3, zero, 2f
+ PTR_SUBU a2, a2, a3 # subtract from remaining count
+ PTR_ADDU a3, a3, a0 # compute ending address
+1:
+ lbu v0, 0(a0) # compare bytes until a1 word aligned
+ lbu v1, 0(a1)
+ PTR_ADDU a0, a0, 1
+ bne v0, v1, nomatch
+ PTR_ADDU a1, a1, 1
+ bne a0, a3, 1b
+ nop
+2:
+ and a3, a2, ~3 # compute number of whole words left
+ PTR_SUBU a2, a2, a3 # which has to be >= (16-3) & ~3
+ PTR_ADDU a3, a3, a0 # compute ending address
+3:
+ LWHI v0, 0(a0) # compare words a0 unaligned, a1 aligned
+ LWLO v0, 3(a0)
+ lw v1, 0(a1)
+ PTR_ADDU a0, a0, 4
+ bne v0, v1, nomatch
+ PTR_ADDU a1, a1, 4
+ bne a0, a3, 3b
+ nop
+smallcmp:
+ ble a2, zero, match
+ PTR_ADDU a3, a2, a0 # compute ending address
+1:
+ lbu v0, 0(a0)
+ lbu v1, 0(a1)
+ PTR_ADDU a0, a0, 1
+ bne v0, v1, nomatch
+ PTR_ADDU a1, a1, 1
+ bne a0, a3, 1b
+ nop
+match:
+ j ra
+ move v0, zero
+nomatch:
+ j ra
+ li v0, 1
+END(bcmp)
+
+
+/*
+ * bit = ffs(value)
+ */
+LEAF(ffs)
+ .set noreorder
+ beq a0, zero, 2f
+ move v0, zero
+1:
+ and v1, a0, 1 # bit set?
+ addu v0, v0, 1
+ beq v1, zero, 1b # no, continue
+ srl a0, a0, 1
+2:
+ j ra
+ nop
+END(ffs)
+
+/**
+ * void
+ * atomic_set_16(u_int16_t *a, u_int16_t b)
+ * {
+ * *a |= b;
+ * }
+ */
+LEAF(atomic_set_16)
+ .set noreorder
+ srl a0, a0, 2 # round down address to be 32-bit aligned
+ sll a0, a0, 2
+ andi a1, a1, 0xffff
+1:
+ ll t0, 0(a0)
+ or t0, t0, a1
+ sc t0, 0(a0)
+ beq t0, zero, 1b
+ nop
+ j ra
+ nop
+END(atomic_set_16)
+
+/**
+ * void
+ * atomic_clear_16(u_int16_t *a, u_int16_t b)
+ * {
+ * *a &= ~b;
+ * }
+ */
+LEAF(atomic_clear_16)
+ .set noreorder
+ srl a0, a0, 2 # round down address to be 32-bit aligned
+ sll a0, a0, 2
+ nor a1, zero, a1
+1:
+ ll t0, 0(a0)
+ move t1, t0
+ andi t1, t1, 0xffff # t1 has the original lower 16 bits
+ and t1, t1, a1 # t1 has the new lower 16 bits
+ srl t0, t0, 16 # preserve original top 16 bits
+ sll t0, t0, 16
+ or t0, t0, t1
+ sc t0, 0(a0)
+ beq t0, zero, 1b
+ nop
+ j ra
+ nop
+END(atomic_clear_16)
+
+
+/**
+ * void
+ * atomic_subtract_16(uint16_t *a, uint16_t b)
+ * {
+ * *a -= b;
+ * }
+ */
+LEAF(atomic_subtract_16)
+ .set noreorder
+ srl a0, a0, 2 # round down address to be 32-bit aligned
+ sll a0, a0, 2
+1:
+ ll t0, 0(a0)
+ move t1, t0
+ andi t1, t1, 0xffff # t1 has the original lower 16 bits
+ subu t1, t1, a1
+ andi t1, t1, 0xffff # t1 has the new lower 16 bits
+ srl t0, t0, 16 # preserve original top 16 bits
+ sll t0, t0, 16
+ or t0, t0, t1
+ sc t0, 0(a0)
+ beq t0, zero, 1b
+ nop
+ j ra
+ nop
+END(atomic_subtract_16)
+
+/**
+ * void
+ * atomic_add_16(uint16_t *a, uint16_t b)
+ * {
+ * *a += b;
+ * }
+ */
+LEAF(atomic_add_16)
+ .set noreorder
+ srl a0, a0, 2 # round down address to be 32-bit aligned
+ sll a0, a0, 2
+1:
+ ll t0, 0(a0)
+ move t1, t0
+ andi t1, t1, 0xffff # t1 has the original lower 16 bits
+ addu t1, t1, a1
+ andi t1, t1, 0xffff # t1 has the new lower 16 bits
+ srl t0, t0, 16 # preserve original top 16 bits
+ sll t0, t0, 16
+ or t0, t0, t1
+ sc t0, 0(a0)
+ beq t0, zero, 1b
+ nop
+ j ra
+ nop
+END(atomic_add_16)
+
+/**
+ * void
+ * atomic_add_8(uint8_t *a, uint8_t b)
+ * {
+ * *a += b;
+ * }
+ */
+LEAF(atomic_add_8)
+ .set noreorder
+ srl a0, a0, 2 # round down address to be 32-bit aligned
+ sll a0, a0, 2
+1:
+ ll t0, 0(a0)
+ move t1, t0
+ andi t1, t1, 0xff # t1 has the original lower 8 bits
+ addu t1, t1, a1
+ andi t1, t1, 0xff # t1 has the new lower 8 bits
+ srl t0, t0, 8 # preserve original top 24 bits
+ sll t0, t0, 8
+ or t0, t0, t1
+ sc t0, 0(a0)
+ beq t0, zero, 1b
+ nop
+ j ra
+ nop
+END(atomic_add_8)
+
+
+/**
+ * void
+ * atomic_subtract_8(uint8_t *a, uint8_t b)
+ * {
+ * *a += b;
+ * }
+ */
+LEAF(atomic_subtract_8)
+ .set noreorder
+ srl a0, a0, 2 # round down address to be 32-bit aligned
+ sll a0, a0, 2
+1:
+ ll t0, 0(a0)
+ move t1, t0
+ andi t1, t1, 0xff # t1 has the original lower 8 bits
+ subu t1, t1, a1
+ andi t1, t1, 0xff # t1 has the new lower 8 bits
+ srl t0, t0, 8 # preserve original top 24 bits
+ sll t0, t0, 8
+ or t0, t0, t1
+ sc t0, 0(a0)
+ beq t0, zero, 1b
+ nop
+ j ra
+ nop
+END(atomic_subtract_8)
+
+/*
+ * atomic 64-bit register read/write assembly language support routines.
+ */
+
+ .set noreorder # Noreorder is default style!
+
+#if !defined(__mips_n64) && !defined(__mips_n32)
+ /*
+ * I don't know if these routines have the right number of
+ * NOPs in it for all processors. XXX
+ *
+ * Maybe it would be better to just leave this undefined in that case.
+ *
+ * XXX These routines are not safe in the case of a TLB miss on a1 or
+ * a0 unless the trapframe is 64-bit, which it just isn't with O32.
+ * If we take any exception, not just an interrupt, the upper
+ * 32-bits will be clobbered. Use only N32 and N64 kernels if you
+ * want to use 64-bit registers while interrupts are enabled or
+ * with memory operations. Since this isn't even using load-linked
+ * and store-conditional, perhaps it should just use two registers
+ * instead, as is right and good with the O32 ABI.
+ */
+LEAF(atomic_store_64)
+ mfc0 t1, MIPS_COP_0_STATUS
+ and t2, t1, ~MIPS_SR_INT_IE
+ mtc0 t2, MIPS_COP_0_STATUS
+ nop
+ nop
+ nop
+ nop
+ ld t0, (a1)
+ nop
+ nop
+ sd t0, (a0)
+ nop
+ nop
+ mtc0 t1,MIPS_COP_0_STATUS
+ nop
+ nop
+ nop
+ nop
+ j ra
+ nop
+END(atomic_store_64)
+
+LEAF(atomic_load_64)
+ mfc0 t1, MIPS_COP_0_STATUS
+ and t2, t1, ~MIPS_SR_INT_IE
+ mtc0 t2, MIPS_COP_0_STATUS
+ nop
+ nop
+ nop
+ nop
+ ld t0, (a0)
+ nop
+ nop
+ sd t0, (a1)
+ nop
+ nop
+ mtc0 t1,MIPS_COP_0_STATUS
+ nop
+ nop
+ nop
+ nop
+ j ra
+ nop
+END(atomic_load_64)
+#endif
+
+#if defined(DDB) || defined(DEBUG)
+
+LEAF(kdbpeek)
+ PTR_LA v1, ddberr
+ and v0, a0, 3 # unaligned ?
+ GET_CPU_PCPU(t1)
+ PTR_L t1, PC_CURPCB(t1)
+ bne v0, zero, 1f
+ PTR_S v1, U_PCB_ONFAULT(t1)
+
+ lw v0, (a0)
+ jr ra
+ PTR_S zero, U_PCB_ONFAULT(t1)
+
+1:
+ LWHI v0, 0(a0)
+ LWLO v0, 3(a0)
+ jr ra
+ PTR_S zero, U_PCB_ONFAULT(t1)
+END(kdbpeek)
+
+LEAF(kdbpeekd)
+ PTR_LA v1, ddberr
+ and v0, a0, 3 # unaligned ?
+ GET_CPU_PCPU(t1)
+ PTR_L t1, PC_CURPCB(t1)
+ bne v0, zero, 1f
+ PTR_S v1, U_PCB_ONFAULT(t1)
+
+ ld v0, (a0)
+ jr ra
+ PTR_S zero, U_PCB_ONFAULT(t1)
+
+1:
+ REG_LHI v0, 0(a0)
+ REG_LLO v0, 7(a0)
+ jr ra
+ PTR_S zero, U_PCB_ONFAULT(t1)
+END(kdbpeekd)
+
+ddberr:
+ jr ra
+ nop
+
+#if defined(DDB)
+LEAF(kdbpoke)
+ PTR_LA v1, ddberr
+ and v0, a0, 3 # unaligned ?
+ GET_CPU_PCPU(t1)
+ PTR_L t1, PC_CURPCB(t1)
+ bne v0, zero, 1f
+ PTR_S v1, U_PCB_ONFAULT(t1)
+
+ sw a1, (a0)
+ jr ra
+ PTR_S zero, U_PCB_ONFAULT(t1)
+
+1:
+ SWHI a1, 0(a0)
+ SWLO a1, 3(a0)
+ jr ra
+ PTR_S zero, U_PCB_ONFAULT(t1)
+END(kdbpoke)
+
+ .data
+ .globl esym
+esym: .word 0
+
+#endif /* DDB */
+#endif /* DDB || DEBUG */
+
+ .text
+LEAF(breakpoint)
+ break MIPS_BREAK_SOVER_VAL
+ jr ra
+ nop
+END(breakpoint)
+
+LEAF(setjmp)
+ mfc0 v0, MIPS_COP_0_STATUS # Later the "real" spl value!
+ REG_S s0, (SZREG * PCB_REG_S0)(a0)
+ REG_S s1, (SZREG * PCB_REG_S1)(a0)
+ REG_S s2, (SZREG * PCB_REG_S2)(a0)
+ REG_S s3, (SZREG * PCB_REG_S3)(a0)
+ REG_S s4, (SZREG * PCB_REG_S4)(a0)
+ REG_S s5, (SZREG * PCB_REG_S5)(a0)
+ REG_S s6, (SZREG * PCB_REG_S6)(a0)
+ REG_S s7, (SZREG * PCB_REG_S7)(a0)
+ REG_S s8, (SZREG * PCB_REG_S8)(a0)
+ REG_S sp, (SZREG * PCB_REG_SP)(a0)
+ REG_S ra, (SZREG * PCB_REG_RA)(a0)
+ REG_S v0, (SZREG * PCB_REG_SR)(a0)
+ jr ra
+ li v0, 0 # setjmp return
+END(setjmp)
+
+LEAF(longjmp)
+ REG_L v0, (SZREG * PCB_REG_SR)(a0)
+ REG_L ra, (SZREG * PCB_REG_RA)(a0)
+ REG_L s0, (SZREG * PCB_REG_S0)(a0)
+ REG_L s1, (SZREG * PCB_REG_S1)(a0)
+ REG_L s2, (SZREG * PCB_REG_S2)(a0)
+ REG_L s3, (SZREG * PCB_REG_S3)(a0)
+ REG_L s4, (SZREG * PCB_REG_S4)(a0)
+ REG_L s5, (SZREG * PCB_REG_S5)(a0)
+ REG_L s6, (SZREG * PCB_REG_S6)(a0)
+ REG_L s7, (SZREG * PCB_REG_S7)(a0)
+ REG_L s8, (SZREG * PCB_REG_S8)(a0)
+ REG_L sp, (SZREG * PCB_REG_SP)(a0)
+ mtc0 v0, MIPS_COP_0_STATUS # Later the "real" spl value!
+ ITLBNOPFIX
+ jr ra
+ li v0, 1 # longjmp return
+END(longjmp)
+
+LEAF(mips3_ld)
+ .set push
+ .set noreorder
+ .set mips64
+#if defined(__mips_o32)
+ mfc0 t0, MIPS_COP_0_STATUS # turn off interrupts
+ and t1, t0, ~(MIPS_SR_INT_IE)
+ mtc0 t1, MIPS_COP_0_STATUS
+ COP0_SYNC
+ nop
+ nop
+ nop
+
+ ld v0, 0(a0)
+#if _BYTE_ORDER == _BIG_ENDIAN
+ dsll v1, v0, 32
+ dsra v1, v1, 32 # low word in v1
+ dsra v0, v0, 32 # high word in v0
+#else
+ dsra v1, v0, 32 # high word in v1
+ dsll v0, v0, 32
+ dsra v0, v0, 32 # low word in v0
+#endif
+
+ mtc0 t0, MIPS_COP_0_STATUS # restore intr status.
+ COP0_SYNC
+ nop
+#else /* !__mips_o32 */
+ ld v0, 0(a0)
+#endif /* !__mips_o32 */
+
+ jr ra
+ nop
+ .set pop
+END(mips3_ld)
+
+LEAF(mips3_sd)
+ .set push
+ .set mips64
+ .set noreorder
+#if defined(__mips_o32)
+ mfc0 t0, MIPS_COP_0_STATUS # turn off interrupts
+ and t1, t0, ~(MIPS_SR_INT_IE)
+ mtc0 t1, MIPS_COP_0_STATUS
+ COP0_SYNC
+ nop
+ nop
+ nop
+
+ # NOTE: a1 is padding!
+
+#if _BYTE_ORDER == _BIG_ENDIAN
+ dsll a2, a2, 32 # high word in a2
+ dsll a3, a3, 32 # low word in a3
+ dsrl a3, a3, 32
+#else
+ dsll a2, a2, 32 # low word in a2
+ dsrl a2, a2, 32
+ dsll a3, a3, 32 # high word in a3
+#endif
+ or a1, a2, a3
+ sd a1, 0(a0)
+
+ mtc0 t0, MIPS_COP_0_STATUS # restore intr status.
+ COP0_SYNC
+ nop
+#else /* !__mips_o32 */
+ sd a1, 0(a0)
+#endif /* !__mips_o32 */
+
+ jr ra
+ nop
+ .set pop
+END(mips3_sd)
Property changes on: trunk/sys/mips/mips/support.S
___________________________________________________________________
Added: svn:eol-style
## -0,0 +1 ##
+native
\ No newline at end of property
Added: svn:keywords
## -0,0 +1 ##
+MidnightBSD=%H
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+text/plain
\ No newline at end of property
Added: trunk/sys/mips/mips/swtch.S
===================================================================
--- trunk/sys/mips/mips/swtch.S (rev 0)
+++ trunk/sys/mips/mips/swtch.S 2018-05-26 21:55:02 UTC (rev 9987)
@@ -0,0 +1,648 @@
+/* $MidnightBSD$ */
+/* $OpenBSD: locore.S,v 1.18 1998/09/15 10:58:53 pefo Exp $ */
+/*-
+ * Copyright (c) 1992, 1993
+ * The Regents of the University of California. All rights reserved.
+ *
+ * This code is derived from software contributed to Berkeley by
+ * Digital Equipment Corporation and Ralph Campbell.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * 4. Neither the name of the University nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ * Copyright (C) 1989 Digital Equipment Corporation.
+ * Permission to use, copy, modify, and distribute this software and
+ * its documentation for any purpose and without fee is hereby granted,
+ * provided that the above copyright notice appears in all copies.
+ * Digital Equipment Corporation makes no representations about the
+ * suitability of this software for any purpose. It is provided "as is"
+ * without express or implied warranty.
+ *
+ * from: Header: /sprite/src/kernel/mach/ds3100.md/RCS/loMem.s,
+ * v 1.1 89/07/11 17:55:04 nelson Exp SPRITE (DECWRL)
+ * from: Header: /sprite/src/kernel/mach/ds3100.md/RCS/machAsm.s,
+ * v 9.2 90/01/29 18:00:39 shirriff Exp SPRITE (DECWRL)
+ * from: Header: /sprite/src/kernel/vm/ds3100.md/vmPmaxAsm.s,
+ * v 1.1 89/07/10 14:27:41 nelson Exp SPRITE (DECWRL)
+ *
+ * from: @(#)locore.s 8.5 (Berkeley) 1/4/94
+ * JNPR: swtch.S,v 1.6.2.1 2007/09/10 10:36:50 girish
+ * $FreeBSD: stable/10/sys/mips/mips/swtch.S 249901 2013-04-25 17:23:54Z imp $
+ */
+
+/*
+ * Contains code that is the first executed at boot time plus
+ * assembly language support routines.
+ */
+
+#include "opt_compat.h"
+#include <sys/syscall.h>
+#include <machine/asm.h>
+#include <machine/cpu.h>
+#include <machine/cpuregs.h>
+#include <machine/regnum.h>
+#include <machine/pte.h>
+#include <machine/pcb.h>
+
+#include "assym.s"
+
+ .set noreorder # Noreorder is default style!
+
+#define SAVE_U_PCB_REG(reg, offs, base) \
+ REG_S reg, U_PCB_REGS + (SZREG * offs) (base)
+
+#define RESTORE_U_PCB_REG(reg, offs, base) \
+ REG_L reg, U_PCB_REGS + (SZREG * offs) (base)
+
+#define SAVE_U_PCB_FPREG(reg, offs, base) \
+ FP_S reg, U_PCB_FPREGS + (SZFPREG * offs) (base)
+
+#define RESTORE_U_PCB_FPREG(reg, offs, base) \
+ FP_L reg, U_PCB_FPREGS + (SZFPREG * offs) (base)
+
+#define SAVE_U_PCB_FPSR(reg, offs, base) \
+ REG_S reg, U_PCB_FPREGS + (SZFPREG * offs) (base)
+
+#define RESTORE_U_PCB_FPSR(reg, offs, base) \
+ REG_L reg, U_PCB_FPREGS + (SZFPREG * offs) (base)
+
+#define SAVE_U_PCB_CONTEXT(reg, offs, base) \
+ REG_S reg, U_PCB_CONTEXT + (SZREG * offs) (base)
+
+#define RESTORE_U_PCB_CONTEXT(reg, offs, base) \
+ REG_L reg, U_PCB_CONTEXT + (SZREG * offs) (base)
+
+
+/*
+ * Setup for and return to user.
+ */
+LEAF(fork_trampoline)
+ move a0,s0
+ move a1,s1
+ jal _C_LABEL(fork_exit)
+ move a2,s2 #BDSlot
+
+ DO_AST
+
+ mfc0 v0, MIPS_COP_0_STATUS
+ and v0, ~(MIPS_SR_INT_IE)
+ mtc0 v0, MIPS_COP_0_STATUS # disable interrupts
+ COP0_SYNC
+/*
+ * The use of k1 for storing the PCB pointer must be done only
+ * after interrupts are disabled. Otherwise it will get overwritten
+ * by the interrupt code.
+ */
+ .set noat
+ GET_CPU_PCPU(k1)
+ PTR_L k1, PC_CURPCB(k1)
+
+ RESTORE_U_PCB_REG(t0, MULLO, k1)
+ RESTORE_U_PCB_REG(t1, MULHI, k1)
+ mtlo t0
+ mthi t1
+ RESTORE_U_PCB_REG(a0, PC, k1)
+ RESTORE_U_PCB_REG(AT, AST, k1)
+ RESTORE_U_PCB_REG(v0, V0, k1)
+ MTC0 a0, MIPS_COP_0_EXC_PC # set return address
+
+ RESTORE_U_PCB_REG(v1, V1, k1)
+ RESTORE_U_PCB_REG(a0, A0, k1)
+ RESTORE_U_PCB_REG(a1, A1, k1)
+ RESTORE_U_PCB_REG(a2, A2, k1)
+ RESTORE_U_PCB_REG(a3, A3, k1)
+ RESTORE_U_PCB_REG(t0, T0, k1)
+ RESTORE_U_PCB_REG(t1, T1, k1)
+ RESTORE_U_PCB_REG(t2, T2, k1)
+ RESTORE_U_PCB_REG(t3, T3, k1)
+ RESTORE_U_PCB_REG(ta0, TA0, k1)
+ RESTORE_U_PCB_REG(ta1, TA1, k1)
+ RESTORE_U_PCB_REG(ta2, TA2, k1)
+ RESTORE_U_PCB_REG(ta3, TA3, k1)
+ RESTORE_U_PCB_REG(s0, S0, k1)
+ RESTORE_U_PCB_REG(s1, S1, k1)
+ RESTORE_U_PCB_REG(s2, S2, k1)
+ RESTORE_U_PCB_REG(s3, S3, k1)
+ RESTORE_U_PCB_REG(s4, S4, k1)
+ RESTORE_U_PCB_REG(s5, S5, k1)
+ RESTORE_U_PCB_REG(s6, S6, k1)
+ RESTORE_U_PCB_REG(s7, S7, k1)
+ RESTORE_U_PCB_REG(t8, T8, k1)
+ RESTORE_U_PCB_REG(t9, T9, k1)
+ RESTORE_U_PCB_REG(k0, SR, k1)
+ RESTORE_U_PCB_REG(gp, GP, k1)
+ RESTORE_U_PCB_REG(s8, S8, k1)
+ RESTORE_U_PCB_REG(ra, RA, k1)
+ RESTORE_U_PCB_REG(sp, SP, k1)
+ li k1, ~MIPS_SR_INT_MASK
+ and k0, k0, k1
+ mfc0 k1, MIPS_COP_0_STATUS
+ and k1, k1, MIPS_SR_INT_MASK
+ or k0, k0, k1
+ mtc0 k0, MIPS_COP_0_STATUS # switch to user mode (when eret...)
+ HAZARD_DELAY
+ sync
+ eret
+ .set at
+END(fork_trampoline)
+
+/*
+ * Update pcb, saving current processor state.
+ * Note: this only works if pcbp != curproc's pcb since
+ * cpu_switch() will copy over pcb_context.
+ *
+ * savectx(struct pcb *pcbp);
+ */
+LEAF(savectx)
+ SAVE_U_PCB_CONTEXT(s0, PCB_REG_S0, a0)
+ SAVE_U_PCB_CONTEXT(s1, PCB_REG_S1, a0)
+ SAVE_U_PCB_CONTEXT(s2, PCB_REG_S2, a0)
+ SAVE_U_PCB_CONTEXT(s3, PCB_REG_S3, a0)
+ mfc0 v0, MIPS_COP_0_STATUS
+ SAVE_U_PCB_CONTEXT(s4, PCB_REG_S4, a0)
+ SAVE_U_PCB_CONTEXT(s5, PCB_REG_S5, a0)
+ SAVE_U_PCB_CONTEXT(s6, PCB_REG_S6, a0)
+ SAVE_U_PCB_CONTEXT(s7, PCB_REG_S7, a0)
+ SAVE_U_PCB_CONTEXT(sp, PCB_REG_SP, a0)
+ SAVE_U_PCB_CONTEXT(s8, PCB_REG_S8, a0)
+ SAVE_U_PCB_CONTEXT(ra, PCB_REG_RA, a0)
+ SAVE_U_PCB_CONTEXT(v0, PCB_REG_SR, a0)
+ SAVE_U_PCB_CONTEXT(gp, PCB_REG_GP, a0)
+
+ move v0, ra /* save 'ra' before we trash it */
+ jal 1f
+ nop
+1:
+ SAVE_U_PCB_CONTEXT(ra, PCB_REG_PC, a0)
+ move ra, v0 /* restore 'ra' before returning */
+
+ j ra
+ move v0, zero
+END(savectx)
+
+NON_LEAF(cpu_throw, CALLFRAME_SIZ, ra)
+ mfc0 t0, MIPS_COP_0_STATUS # t0 = saved status register
+ nop
+ nop
+ and a3, t0, ~(MIPS_SR_INT_IE)
+ mtc0 a3, MIPS_COP_0_STATUS # Disable all interrupts
+ ITLBNOPFIX
+ j mips_sw1 # We're not interested in old
+ # thread's context, so jump
+ # right to action
+ nop # BDSLOT
+END(cpu_throw)
+
+/*
+ * cpu_switch(struct thread *old, struct thread *new, struct mutex *mtx);
+ * a0 - old
+ * a1 - new
+ * a2 - mtx
+ * Find the highest priority process and resume it.
+ */
+NON_LEAF(cpu_switch, CALLFRAME_SIZ, ra)
+ mfc0 t0, MIPS_COP_0_STATUS # t0 = saved status register
+ nop
+ nop
+ and a3, t0, ~(MIPS_SR_INT_IE)
+ mtc0 a3, MIPS_COP_0_STATUS # Disable all interrupts
+ ITLBNOPFIX
+ beqz a0, mips_sw1
+ move a3, a0
+ PTR_L a0, TD_PCB(a0) # load PCB addr of curproc
+ SAVE_U_PCB_CONTEXT(sp, PCB_REG_SP, a0) # save old sp
+ PTR_SUBU sp, sp, CALLFRAME_SIZ
+ REG_S ra, CALLFRAME_RA(sp)
+ .mask 0x80000000, (CALLFRAME_RA - CALLFRAME_SIZ)
+ SAVE_U_PCB_CONTEXT(s0, PCB_REG_S0, a0) # do a 'savectx()'
+ SAVE_U_PCB_CONTEXT(s1, PCB_REG_S1, a0)
+ SAVE_U_PCB_CONTEXT(s2, PCB_REG_S2, a0)
+ SAVE_U_PCB_CONTEXT(s3, PCB_REG_S3, a0)
+ SAVE_U_PCB_CONTEXT(s4, PCB_REG_S4, a0)
+ SAVE_U_PCB_CONTEXT(s5, PCB_REG_S5, a0)
+ SAVE_U_PCB_CONTEXT(s6, PCB_REG_S6, a0)
+ SAVE_U_PCB_CONTEXT(s7, PCB_REG_S7, a0)
+ SAVE_U_PCB_CONTEXT(s8, PCB_REG_S8, a0)
+ SAVE_U_PCB_CONTEXT(ra, PCB_REG_RA, a0) # save return address
+ SAVE_U_PCB_CONTEXT(t0, PCB_REG_SR, a0) # save status register
+ SAVE_U_PCB_CONTEXT(gp, PCB_REG_GP, a0)
+ jal getpc
+ nop
+getpc:
+ SAVE_U_PCB_CONTEXT(ra, PCB_REG_PC, a0) # save return address
+
+#ifdef CPU_CNMIPS
+
+ lw t2, TD_MDFLAGS(a3) # get md_flags
+ and t1, t2, MDTD_COP2USED
+ beqz t1, cop2_untouched
+ nop
+
+ /* Clear cop2used flag */
+ and t2, t2, ~MDTD_COP2USED
+ sw t2, TD_MDFLAGS(a3)
+
+ and t2, t0, ~MIPS_SR_COP_2_BIT # clear COP_2 enable bit
+ SAVE_U_PCB_CONTEXT(t2, PCB_REG_SR, a0) # save status register
+
+ RESTORE_U_PCB_REG(t0, PS, a0) # get CPU status register
+ and t2, t0, ~MIPS_SR_COP_2_BIT # clear COP_2 enable bit
+ SAVE_U_PCB_REG(t2, PS, a0) # save stratus register
+
+ /* preserve a0..a3 */
+ move s0, a0
+ move s1, a1
+ move s2, a2
+ move s3, a3
+
+ /* does kernel own COP2 context? */
+ lw t1, TD_COP2OWNER(a3) # get md_cop2owner
+ beqz t1, userland_cop2 # 0 - it's userland context
+ nop
+
+ PTR_L a0, TD_COP2(a3)
+ beqz a0, no_cop2_context
+ nop
+
+ j do_cop2_save
+ nop
+
+userland_cop2:
+
+ PTR_L a0, TD_UCOP2(a3)
+ beqz a0, no_cop2_context
+ nop
+
+do_cop2_save:
+ jal octeon_cop2_save
+ nop
+
+no_cop2_context:
+ move a3, s3
+ move a2, s2
+ move a1, s1
+ move a0, s0
+
+cop2_untouched:
+#endif
+
+ PTR_S a2, TD_LOCK(a3) # Switchout td_lock
+
+mips_sw1:
+#if defined(SMP) && defined(SCHED_ULE)
+ PTR_LA t0, _C_LABEL(blocked_lock)
+blocked_loop:
+ PTR_L t1, TD_LOCK(a1)
+ beq t0, t1, blocked_loop
+ nop
+#endif
+ move s7, a1 # Store newthread
+/*
+ * Switch to new context.
+ */
+ GET_CPU_PCPU(a3)
+ PTR_S a1, PC_CURTHREAD(a3)
+ PTR_L a2, TD_PCB(a1)
+ PTR_S a2, PC_CURPCB(a3)
+ PTR_L v0, TD_KSTACK(a1)
+#if defined(__mips_n64)
+ PTR_LI s0, MIPS_XKSEG_START
+#else
+ PTR_LI s0, MIPS_KSEG2_START # If Uarea addr is below kseg2,
+#endif
+ bltu v0, s0, sw2 # no need to insert in TLB.
+ PTE_L a1, TD_UPTE + 0(s7) # a1 = u. pte #0
+ PTE_L a2, TD_UPTE + PTESIZE(s7) # a2 = u. pte #1
+/*
+ * Wiredown the USPACE of newproc in TLB entry#0. Check whether target
+ * USPACE is already in another place of TLB before that, and if so
+ * invalidate that TLB entry.
+ * NOTE: This is hard coded to UPAGES == 2.
+ * Also, there should be no TLB faults at this point.
+ */
+ MTC0 v0, MIPS_COP_0_TLB_HI # VPN = va
+ HAZARD_DELAY
+ tlbp # probe VPN
+ HAZARD_DELAY
+ mfc0 s0, MIPS_COP_0_TLB_INDEX
+ HAZARD_DELAY
+
+ PTR_LI t1, MIPS_KSEG0_START # invalidate tlb entry
+ bltz s0, entry0set
+ nop
+ sll s0, PAGE_SHIFT + 1
+ addu t1, s0
+ MTC0 t1, MIPS_COP_0_TLB_HI
+ PTE_MTC0 zero, MIPS_COP_0_TLB_LO0
+ PTE_MTC0 zero, MIPS_COP_0_TLB_LO1
+ HAZARD_DELAY
+ tlbwi
+ HAZARD_DELAY
+ MTC0 v0, MIPS_COP_0_TLB_HI # set VPN again
+
+entry0set:
+/* SMP!! - Works only for unshared TLB case - i.e. no v-cpus */
+ mtc0 zero, MIPS_COP_0_TLB_INDEX # TLB entry #0
+ HAZARD_DELAY
+ PTE_MTC0 a1, MIPS_COP_0_TLB_LO0 # upte[0]
+ HAZARD_DELAY
+ PTE_MTC0 a2, MIPS_COP_0_TLB_LO1 # upte[1]
+ HAZARD_DELAY
+ tlbwi # set TLB entry #0
+ HAZARD_DELAY
+/*
+ * Now running on new u struct.
+ */
+sw2:
+ PTR_L s0, TD_PCB(s7)
+ RESTORE_U_PCB_CONTEXT(sp, PCB_REG_SP, s0)
+ PTR_LA t1, _C_LABEL(pmap_activate) # s7 = new proc pointer
+ jalr t1 # s7 = new proc pointer
+ move a0, s7 # BDSLOT
+/*
+ * Restore registers and return.
+ */
+ move a0, s0
+ RESTORE_U_PCB_CONTEXT(gp, PCB_REG_GP, a0)
+ RESTORE_U_PCB_CONTEXT(v0, PCB_REG_SR, a0) # restore kernel context
+ RESTORE_U_PCB_CONTEXT(ra, PCB_REG_RA, a0)
+ RESTORE_U_PCB_CONTEXT(s0, PCB_REG_S0, a0)
+ RESTORE_U_PCB_CONTEXT(s1, PCB_REG_S1, a0)
+ RESTORE_U_PCB_CONTEXT(s2, PCB_REG_S2, a0)
+ RESTORE_U_PCB_CONTEXT(s3, PCB_REG_S3, a0)
+ RESTORE_U_PCB_CONTEXT(s4, PCB_REG_S4, a0)
+ RESTORE_U_PCB_CONTEXT(s5, PCB_REG_S5, a0)
+ RESTORE_U_PCB_CONTEXT(s6, PCB_REG_S6, a0)
+ RESTORE_U_PCB_CONTEXT(s7, PCB_REG_S7, a0)
+ RESTORE_U_PCB_CONTEXT(s8, PCB_REG_S8, a0)
+
+ mfc0 t0, MIPS_COP_0_STATUS
+ and t0, t0, MIPS_SR_INT_MASK
+ and v0, v0, ~MIPS_SR_INT_MASK
+ or v0, v0, t0
+ mtc0 v0, MIPS_COP_0_STATUS
+ ITLBNOPFIX
+
+ j ra
+ nop
+END(cpu_switch)
+
+/*----------------------------------------------------------------------------
+ *
+ * MipsSwitchFPState --
+ *
+ * Save the current state into 'from' and restore it from 'to'.
+ *
+ * MipsSwitchFPState(from, to)
+ * struct thread *from;
+ * struct trapframe *to;
+ *
+ * Results:
+ * None.
+ *
+ * Side effects:
+ * None.
+ *
+ *----------------------------------------------------------------------------
+ */
+LEAF(MipsSwitchFPState)
+ mfc0 t1, MIPS_COP_0_STATUS # Save old SR
+ li t0, MIPS_SR_COP_1_BIT # enable the coprocessor
+ mtc0 t0, MIPS_COP_0_STATUS
+ ITLBNOPFIX
+
+ beq a0, zero, 1f # skip save if NULL pointer
+ nop
+/*
+ * First read out the status register to make sure that all FP operations
+ * have completed.
+ */
+ PTR_L a0, TD_PCB(a0) # get pointer to pcb for proc
+ cfc1 t0, MIPS_FPU_CSR # stall til FP done
+ cfc1 t0, MIPS_FPU_CSR # now get status
+ li t3, ~MIPS_SR_COP_1_BIT
+ RESTORE_U_PCB_REG(t2, PS, a0) # get CPU status register
+ SAVE_U_PCB_FPSR(t0, FSR_NUM, a0) # save FP status
+ and t2, t2, t3 # clear COP_1 enable bit
+ SAVE_U_PCB_REG(t2, PS, a0) # save new status register
+/*
+ * Save the floating point registers.
+ */
+ SAVE_U_PCB_FPREG($f0, F0_NUM, a0)
+ SAVE_U_PCB_FPREG($f1, F1_NUM, a0)
+ SAVE_U_PCB_FPREG($f2, F2_NUM, a0)
+ SAVE_U_PCB_FPREG($f3, F3_NUM, a0)
+ SAVE_U_PCB_FPREG($f4, F4_NUM, a0)
+ SAVE_U_PCB_FPREG($f5, F5_NUM, a0)
+ SAVE_U_PCB_FPREG($f6, F6_NUM, a0)
+ SAVE_U_PCB_FPREG($f7, F7_NUM, a0)
+ SAVE_U_PCB_FPREG($f8, F8_NUM, a0)
+ SAVE_U_PCB_FPREG($f9, F9_NUM, a0)
+ SAVE_U_PCB_FPREG($f10, F10_NUM, a0)
+ SAVE_U_PCB_FPREG($f11, F11_NUM, a0)
+ SAVE_U_PCB_FPREG($f12, F12_NUM, a0)
+ SAVE_U_PCB_FPREG($f13, F13_NUM, a0)
+ SAVE_U_PCB_FPREG($f14, F14_NUM, a0)
+ SAVE_U_PCB_FPREG($f15, F15_NUM, a0)
+ SAVE_U_PCB_FPREG($f16, F16_NUM, a0)
+ SAVE_U_PCB_FPREG($f17, F17_NUM, a0)
+ SAVE_U_PCB_FPREG($f18, F18_NUM, a0)
+ SAVE_U_PCB_FPREG($f19, F19_NUM, a0)
+ SAVE_U_PCB_FPREG($f20, F20_NUM, a0)
+ SAVE_U_PCB_FPREG($f21, F21_NUM, a0)
+ SAVE_U_PCB_FPREG($f22, F22_NUM, a0)
+ SAVE_U_PCB_FPREG($f23, F23_NUM, a0)
+ SAVE_U_PCB_FPREG($f24, F24_NUM, a0)
+ SAVE_U_PCB_FPREG($f25, F25_NUM, a0)
+ SAVE_U_PCB_FPREG($f26, F26_NUM, a0)
+ SAVE_U_PCB_FPREG($f27, F27_NUM, a0)
+ SAVE_U_PCB_FPREG($f28, F28_NUM, a0)
+ SAVE_U_PCB_FPREG($f29, F29_NUM, a0)
+ SAVE_U_PCB_FPREG($f30, F30_NUM, a0)
+ SAVE_U_PCB_FPREG($f31, F31_NUM, a0)
+
+1:
+/*
+ * Restore the floating point registers.
+ */
+ RESTORE_U_PCB_FPSR(t0, FSR_NUM, a1) # get status register
+ RESTORE_U_PCB_FPREG($f0, F0_NUM, a1)
+ RESTORE_U_PCB_FPREG($f1, F1_NUM, a1)
+ RESTORE_U_PCB_FPREG($f2, F2_NUM, a1)
+ RESTORE_U_PCB_FPREG($f3, F3_NUM, a1)
+ RESTORE_U_PCB_FPREG($f4, F4_NUM, a1)
+ RESTORE_U_PCB_FPREG($f5, F5_NUM, a1)
+ RESTORE_U_PCB_FPREG($f6, F6_NUM, a1)
+ RESTORE_U_PCB_FPREG($f7, F7_NUM, a1)
+ RESTORE_U_PCB_FPREG($f8, F8_NUM, a1)
+ RESTORE_U_PCB_FPREG($f9, F9_NUM, a1)
+ RESTORE_U_PCB_FPREG($f10, F10_NUM, a1)
+ RESTORE_U_PCB_FPREG($f11, F11_NUM, a1)
+ RESTORE_U_PCB_FPREG($f12, F12_NUM, a1)
+ RESTORE_U_PCB_FPREG($f13, F13_NUM, a1)
+ RESTORE_U_PCB_FPREG($f14, F14_NUM, a1)
+ RESTORE_U_PCB_FPREG($f15, F15_NUM, a1)
+ RESTORE_U_PCB_FPREG($f16, F16_NUM, a1)
+ RESTORE_U_PCB_FPREG($f17, F17_NUM, a1)
+ RESTORE_U_PCB_FPREG($f18, F18_NUM, a1)
+ RESTORE_U_PCB_FPREG($f19, F19_NUM, a1)
+ RESTORE_U_PCB_FPREG($f20, F20_NUM, a1)
+ RESTORE_U_PCB_FPREG($f21, F21_NUM, a1)
+ RESTORE_U_PCB_FPREG($f22, F22_NUM, a1)
+ RESTORE_U_PCB_FPREG($f23, F23_NUM, a1)
+ RESTORE_U_PCB_FPREG($f24, F24_NUM, a1)
+ RESTORE_U_PCB_FPREG($f25, F25_NUM, a1)
+ RESTORE_U_PCB_FPREG($f26, F26_NUM, a1)
+ RESTORE_U_PCB_FPREG($f27, F27_NUM, a1)
+ RESTORE_U_PCB_FPREG($f28, F28_NUM, a1)
+ RESTORE_U_PCB_FPREG($f29, F29_NUM, a1)
+ RESTORE_U_PCB_FPREG($f30, F30_NUM, a1)
+ RESTORE_U_PCB_FPREG($f31, F31_NUM, a1)
+
+ and t0, t0, ~MIPS_FPU_EXCEPTION_BITS
+ ctc1 t0, MIPS_FPU_CSR
+ nop
+
+ mtc0 t1, MIPS_COP_0_STATUS # Restore the status register.
+ ITLBNOPFIX
+ j ra
+ nop
+END(MipsSwitchFPState)
+
+/*----------------------------------------------------------------------------
+ *
+ * MipsSaveCurFPState --
+ *
+ * Save the current floating point coprocessor state.
+ *
+ * MipsSaveCurFPState(td)
+ * struct thread *td;
+ *
+ * Results:
+ * None.
+ *
+ * Side effects:
+ * machFPCurProcPtr is cleared.
+ *
+ *----------------------------------------------------------------------------
+ */
+LEAF(MipsSaveCurFPState)
+ PTR_L a0, TD_PCB(a0) # get pointer to pcb for thread
+ mfc0 t1, MIPS_COP_0_STATUS # Disable interrupts and
+ li t0, MIPS_SR_COP_1_BIT # enable the coprocessor
+ mtc0 t0, MIPS_COP_0_STATUS
+ ITLBNOPFIX
+ GET_CPU_PCPU(a1)
+ PTR_S zero, PC_FPCURTHREAD(a1) # indicate state has been saved
+/*
+ * First read out the status register to make sure that all FP operations
+ * have completed.
+ */
+ RESTORE_U_PCB_REG(t2, PS, a0) # get CPU status register
+ li t3, ~MIPS_SR_COP_1_BIT
+ and t2, t2, t3 # clear COP_1 enable bit
+ cfc1 t0, MIPS_FPU_CSR # stall til FP done
+ cfc1 t0, MIPS_FPU_CSR # now get status
+ SAVE_U_PCB_REG(t2, PS, a0) # save new status register
+ SAVE_U_PCB_FPSR(t0, FSR_NUM, a0) # save FP status
+/*
+ * Save the floating point registers.
+ */
+ SAVE_U_PCB_FPREG($f0, F0_NUM, a0)
+ SAVE_U_PCB_FPREG($f1, F1_NUM, a0)
+ SAVE_U_PCB_FPREG($f2, F2_NUM, a0)
+ SAVE_U_PCB_FPREG($f3, F3_NUM, a0)
+ SAVE_U_PCB_FPREG($f4, F4_NUM, a0)
+ SAVE_U_PCB_FPREG($f5, F5_NUM, a0)
+ SAVE_U_PCB_FPREG($f6, F6_NUM, a0)
+ SAVE_U_PCB_FPREG($f7, F7_NUM, a0)
+ SAVE_U_PCB_FPREG($f8, F8_NUM, a0)
+ SAVE_U_PCB_FPREG($f9, F9_NUM, a0)
+ SAVE_U_PCB_FPREG($f10, F10_NUM, a0)
+ SAVE_U_PCB_FPREG($f11, F11_NUM, a0)
+ SAVE_U_PCB_FPREG($f12, F12_NUM, a0)
+ SAVE_U_PCB_FPREG($f13, F13_NUM, a0)
+ SAVE_U_PCB_FPREG($f14, F14_NUM, a0)
+ SAVE_U_PCB_FPREG($f15, F15_NUM, a0)
+ SAVE_U_PCB_FPREG($f16, F16_NUM, a0)
+ SAVE_U_PCB_FPREG($f17, F17_NUM, a0)
+ SAVE_U_PCB_FPREG($f18, F18_NUM, a0)
+ SAVE_U_PCB_FPREG($f19, F19_NUM, a0)
+ SAVE_U_PCB_FPREG($f20, F20_NUM, a0)
+ SAVE_U_PCB_FPREG($f21, F21_NUM, a0)
+ SAVE_U_PCB_FPREG($f22, F22_NUM, a0)
+ SAVE_U_PCB_FPREG($f23, F23_NUM, a0)
+ SAVE_U_PCB_FPREG($f24, F24_NUM, a0)
+ SAVE_U_PCB_FPREG($f25, F25_NUM, a0)
+ SAVE_U_PCB_FPREG($f26, F26_NUM, a0)
+ SAVE_U_PCB_FPREG($f27, F27_NUM, a0)
+ SAVE_U_PCB_FPREG($f28, F28_NUM, a0)
+ SAVE_U_PCB_FPREG($f29, F29_NUM, a0)
+ SAVE_U_PCB_FPREG($f30, F30_NUM, a0)
+ SAVE_U_PCB_FPREG($f31, F31_NUM, a0)
+
+ mtc0 t1, MIPS_COP_0_STATUS # Restore the status register.
+ ITLBNOPFIX
+ j ra
+ nop
+END(MipsSaveCurFPState)
+
+/*
+ * This code is copied the user's stack for returning from signal handlers
+ * (see sendsig() and sigreturn()). We have to compute the address
+ * of the sigcontext struct for the sigreturn call.
+ */
+ .globl _C_LABEL(sigcode)
+_C_LABEL(sigcode):
+ PTR_ADDU a0, sp, SIGF_UC # address of ucontext
+ li v0, SYS_sigreturn
+# sigreturn (ucp)
+ syscall
+ break 0 # just in case sigreturn fails
+ .globl _C_LABEL(esigcode)
+_C_LABEL(esigcode):
+
+ .data
+ .globl szsigcode
+szsigcode:
+ .long esigcode-sigcode
+ .text
+
+#if (defined(__mips_n32) || defined(__mips_n64)) && defined(COMPAT_FREEBSD32)
+ .globl _C_LABEL(sigcode32)
+_C_LABEL(sigcode32):
+ addu a0, sp, SIGF32_UC # address of ucontext
+ li v0, SYS_sigreturn
+# sigreturn (ucp)
+ syscall
+ break 0 # just in case sigreturn fails
+ .globl _C_LABEL(esigcode32)
+_C_LABEL(esigcode32):
+
+ .data
+ .globl szsigcode32
+szsigcode32:
+ .long esigcode32-sigcode32
+ .text
+#endif
Property changes on: trunk/sys/mips/mips/swtch.S
___________________________________________________________________
Added: svn:eol-style
## -0,0 +1 ##
+native
\ No newline at end of property
Added: svn:keywords
## -0,0 +1 ##
+MidnightBSD=%H
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+text/plain
\ No newline at end of property
Added: trunk/sys/mips/mips/sys_machdep.c
===================================================================
--- trunk/sys/mips/mips/sys_machdep.c (rev 0)
+++ trunk/sys/mips/mips/sys_machdep.c 2018-05-26 21:55:02 UTC (rev 9987)
@@ -0,0 +1,74 @@
+/* $MidnightBSD$ */
+/*-
+ * Copyright (c) 1990 The Regents of the University of California.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * 3. All advertising materials mentioning features or use of this software
+ * must display the following acknowledgement:
+ * This product includes software developed by the University of
+ * California, Berkeley and its contributors.
+ * 4. Neither the name of the University nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ * from: @(#)sys_machdep.c 5.5 (Berkeley) 1/19/91
+ */
+
+#include <sys/cdefs.h>
+__FBSDID("$FreeBSD: stable/10/sys/mips/mips/sys_machdep.c 232767 2012-03-10 06:31:28Z jmallett $");
+
+#include <sys/param.h>
+#include <sys/systm.h>
+#include <sys/proc.h>
+#include <sys/sysproto.h>
+#include <sys/syscall.h>
+#include <sys/sysent.h>
+
+#include <machine/sysarch.h>
+
+#ifndef _SYS_SYSPROTO_H_
+struct sysarch_args {
+ int op;
+ char *parms;
+};
+#endif
+
+int
+sysarch(struct thread *td, struct sysarch_args *uap)
+{
+ int error;
+ void *tlsbase;
+
+ switch (uap->op) {
+ case MIPS_SET_TLS:
+ td->td_md.md_tls = uap->parms;
+ return (0);
+ case MIPS_GET_TLS:
+ tlsbase = td->td_md.md_tls;
+ error = copyout(&tlsbase, uap->parms, sizeof(tlsbase));
+ return (error);
+ default:
+ break;
+ }
+ return (EINVAL);
+}
Property changes on: trunk/sys/mips/mips/sys_machdep.c
___________________________________________________________________
Added: svn:eol-style
## -0,0 +1 ##
+native
\ No newline at end of property
Added: svn:keywords
## -0,0 +1 ##
+MidnightBSD=%H
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+text/plain
\ No newline at end of property
Added: trunk/sys/mips/mips/tick.c
===================================================================
--- trunk/sys/mips/mips/tick.c (rev 0)
+++ trunk/sys/mips/mips/tick.c 2018-05-26 21:55:02 UTC (rev 9987)
@@ -0,0 +1,388 @@
+/* $MidnightBSD$ */
+/*-
+ * Copyright (c) 2006-2007 Bruce M. Simpson.
+ * Copyright (c) 2003-2004 Juli Mallett.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ */
+
+/*
+ * Simple driver for the 32-bit interval counter built in to all
+ * MIPS32 CPUs.
+ */
+
+#include <sys/cdefs.h>
+__FBSDID("$FreeBSD: stable/10/sys/mips/mips/tick.c 265999 2014-05-14 01:35:43Z ian $");
+
+#include <sys/param.h>
+#include <sys/systm.h>
+#include <sys/sysctl.h>
+#include <sys/bus.h>
+#include <sys/kernel.h>
+#include <sys/module.h>
+#include <sys/rman.h>
+#include <sys/power.h>
+#include <sys/smp.h>
+#include <sys/time.h>
+#include <sys/timeet.h>
+#include <sys/timetc.h>
+
+#include <machine/hwfunc.h>
+#include <machine/clock.h>
+#include <machine/locore.h>
+#include <machine/md_var.h>
+
+uint64_t counter_freq;
+
+struct timecounter *platform_timecounter;
+
+static DPCPU_DEFINE(uint32_t, cycles_per_tick);
+static uint32_t cycles_per_usec;
+
+static DPCPU_DEFINE(volatile uint32_t, counter_upper);
+static DPCPU_DEFINE(volatile uint32_t, counter_lower_last);
+static DPCPU_DEFINE(uint32_t, compare_ticks);
+static DPCPU_DEFINE(uint32_t, lost_ticks);
+
+struct clock_softc {
+ int intr_rid;
+ struct resource *intr_res;
+ void *intr_handler;
+ struct timecounter tc;
+ struct eventtimer et;
+};
+static struct clock_softc *softc;
+
+/*
+ * Device methods
+ */
+static int clock_probe(device_t);
+static void clock_identify(driver_t *, device_t);
+static int clock_attach(device_t);
+static unsigned counter_get_timecount(struct timecounter *tc);
+
+void
+mips_timer_early_init(uint64_t clock_hz)
+{
+ /* Initialize clock early so that we can use DELAY sooner */
+ counter_freq = clock_hz;
+ cycles_per_usec = (clock_hz / (1000 * 1000));
+}
+
+void
+platform_initclocks(void)
+{
+
+ if (platform_timecounter != NULL)
+ tc_init(platform_timecounter);
+}
+
+static uint64_t
+tick_ticker(void)
+{
+ uint64_t ret;
+ uint32_t ticktock;
+ uint32_t t_lower_last, t_upper;
+
+ /*
+ * Disable preemption because we are working with cpu specific data.
+ */
+ critical_enter();
+
+ /*
+ * Note that even though preemption is disabled, interrupts are
+ * still enabled. In particular there is a race with clock_intr()
+ * reading the values of 'counter_upper' and 'counter_lower_last'.
+ *
+ * XXX this depends on clock_intr() being executed periodically
+ * so that 'counter_upper' and 'counter_lower_last' are not stale.
+ */
+ do {
+ t_upper = DPCPU_GET(counter_upper);
+ t_lower_last = DPCPU_GET(counter_lower_last);
+ } while (t_upper != DPCPU_GET(counter_upper));
+
+ ticktock = mips_rd_count();
+
+ critical_exit();
+
+ /* COUNT register wrapped around */
+ if (ticktock < t_lower_last)
+ t_upper++;
+
+ ret = ((uint64_t)t_upper << 32) | ticktock;
+ return (ret);
+}
+
+void
+mips_timer_init_params(uint64_t platform_counter_freq, int double_count)
+{
+
+ /*
+ * XXX: Do not use printf here: uart code 8250 may use DELAY so this
+ * function should be called before cninit.
+ */
+ counter_freq = platform_counter_freq;
+ /*
+ * XXX: Some MIPS32 cores update the Count register only every two
+ * pipeline cycles.
+ * We know this because of status registers in CP0, make it automatic.
+ */
+ if (double_count != 0)
+ counter_freq /= 2;
+
+ cycles_per_usec = counter_freq / (1 * 1000 * 1000);
+ set_cputicker(tick_ticker, counter_freq, 1);
+}
+
+static int
+sysctl_machdep_counter_freq(SYSCTL_HANDLER_ARGS)
+{
+ int error;
+ uint64_t freq;
+
+ if (softc == NULL)
+ return (EOPNOTSUPP);
+ freq = counter_freq;
+ error = sysctl_handle_64(oidp, &freq, sizeof(freq), req);
+ if (error == 0 && req->newptr != NULL) {
+ counter_freq = freq;
+ softc->et.et_frequency = counter_freq;
+ softc->tc.tc_frequency = counter_freq;
+ }
+ return (error);
+}
+
+SYSCTL_PROC(_machdep, OID_AUTO, counter_freq, CTLTYPE_U64 | CTLFLAG_RW,
+ NULL, 0, sysctl_machdep_counter_freq, "QU",
+ "Timecounter frequency in Hz");
+
+static unsigned
+counter_get_timecount(struct timecounter *tc)
+{
+
+ return (mips_rd_count());
+}
+
+/*
+ * Wait for about n microseconds (at least!).
+ */
+void
+DELAY(int n)
+{
+ uint32_t cur, last, delta, usecs;
+
+ /*
+ * This works by polling the timer and counting the number of
+ * microseconds that go by.
+ */
+ last = mips_rd_count();
+ delta = usecs = 0;
+
+ while (n > usecs) {
+ cur = mips_rd_count();
+
+ /* Check to see if the timer has wrapped around. */
+ if (cur < last)
+ delta += cur + (0xffffffff - last) + 1;
+ else
+ delta += cur - last;
+
+ last = cur;
+
+ if (delta >= cycles_per_usec) {
+ usecs += delta / cycles_per_usec;
+ delta %= cycles_per_usec;
+ }
+ }
+}
+
+static int
+clock_start(struct eventtimer *et, sbintime_t first, sbintime_t period)
+{
+ uint32_t fdiv, div, next;
+
+ if (period != 0) {
+ div = (et->et_frequency * period) >> 32;
+ } else
+ div = 0;
+ if (first != 0)
+ fdiv = (et->et_frequency * first) >> 32;
+ else
+ fdiv = div;
+ DPCPU_SET(cycles_per_tick, div);
+ next = mips_rd_count() + fdiv;
+ DPCPU_SET(compare_ticks, next);
+ mips_wr_compare(next);
+ return (0);
+}
+
+static int
+clock_stop(struct eventtimer *et)
+{
+
+ DPCPU_SET(cycles_per_tick, 0);
+ mips_wr_compare(0xffffffff);
+ return (0);
+}
+
+/*
+ * Device section of file below
+ */
+static int
+clock_intr(void *arg)
+{
+ struct clock_softc *sc = (struct clock_softc *)arg;
+ uint32_t cycles_per_tick;
+ uint32_t count, compare_last, compare_next, lost_ticks;
+
+ cycles_per_tick = DPCPU_GET(cycles_per_tick);
+ /*
+ * Set next clock edge.
+ */
+ count = mips_rd_count();
+ compare_last = DPCPU_GET(compare_ticks);
+ if (cycles_per_tick > 0) {
+ compare_next = count + cycles_per_tick;
+ DPCPU_SET(compare_ticks, compare_next);
+ mips_wr_compare(compare_next);
+ } else /* In one-shot mode timer should be stopped after the event. */
+ mips_wr_compare(0xffffffff);
+
+ /* COUNT register wrapped around */
+ if (count < DPCPU_GET(counter_lower_last)) {
+ DPCPU_SET(counter_upper, DPCPU_GET(counter_upper) + 1);
+ }
+ DPCPU_SET(counter_lower_last, count);
+
+ if (cycles_per_tick > 0) {
+
+ /*
+ * Account for the "lost time" between when the timer interrupt
+ * fired and when 'clock_intr' actually started executing.
+ */
+ lost_ticks = DPCPU_GET(lost_ticks);
+ lost_ticks += count - compare_last;
+
+ /*
+ * If the COUNT and COMPARE registers are no longer in sync
+ * then make up some reasonable value for the 'lost_ticks'.
+ *
+ * This could happen, for e.g., after we resume normal
+ * operations after exiting the debugger.
+ */
+ if (lost_ticks > 2 * cycles_per_tick)
+ lost_ticks = cycles_per_tick;
+
+ while (lost_ticks >= cycles_per_tick) {
+ if (sc->et.et_active)
+ sc->et.et_event_cb(&sc->et, sc->et.et_arg);
+ lost_ticks -= cycles_per_tick;
+ }
+ DPCPU_SET(lost_ticks, lost_ticks);
+ }
+ if (sc->et.et_active)
+ sc->et.et_event_cb(&sc->et, sc->et.et_arg);
+ return (FILTER_HANDLED);
+}
+
+static int
+clock_probe(device_t dev)
+{
+
+ if (device_get_unit(dev) != 0)
+ panic("can't attach more clocks");
+
+ device_set_desc(dev, "Generic MIPS32 ticker");
+ return (BUS_PROBE_NOWILDCARD);
+}
+
+static void
+clock_identify(driver_t * drv, device_t parent)
+{
+
+ BUS_ADD_CHILD(parent, 0, "clock", 0);
+}
+
+static int
+clock_attach(device_t dev)
+{
+ struct clock_softc *sc;
+ int error;
+
+ softc = sc = device_get_softc(dev);
+ sc->intr_rid = 0;
+ sc->intr_res = bus_alloc_resource(dev,
+ SYS_RES_IRQ, &sc->intr_rid, 5, 5, 1, RF_ACTIVE);
+ if (sc->intr_res == NULL) {
+ device_printf(dev, "failed to allocate irq\n");
+ return (ENXIO);
+ }
+ error = bus_setup_intr(dev, sc->intr_res, INTR_TYPE_CLK,
+ clock_intr, NULL, sc, &sc->intr_handler);
+ if (error != 0) {
+ device_printf(dev, "bus_setup_intr returned %d\n", error);
+ return (error);
+ }
+
+ sc->tc.tc_get_timecount = counter_get_timecount;
+ sc->tc.tc_counter_mask = 0xffffffff;
+ sc->tc.tc_frequency = counter_freq;
+ sc->tc.tc_name = "MIPS32";
+ sc->tc.tc_quality = 800;
+ sc->tc.tc_priv = sc;
+ tc_init(&sc->tc);
+ sc->et.et_name = "MIPS32";
+ sc->et.et_flags = ET_FLAGS_PERIODIC | ET_FLAGS_ONESHOT |
+ ET_FLAGS_PERCPU;
+ sc->et.et_quality = 800;
+ sc->et.et_frequency = counter_freq;
+ sc->et.et_min_period = 0x00004000LLU; /* To be safe. */
+ sc->et.et_max_period = (0xfffffffeLLU << 32) / sc->et.et_frequency;
+ sc->et.et_start = clock_start;
+ sc->et.et_stop = clock_stop;
+ sc->et.et_priv = sc;
+ et_register(&sc->et);
+ return (0);
+}
+
+static device_method_t clock_methods[] = {
+ /* Device interface */
+ DEVMETHOD(device_probe, clock_probe),
+ DEVMETHOD(device_identify, clock_identify),
+ DEVMETHOD(device_attach, clock_attach),
+ DEVMETHOD(device_detach, bus_generic_detach),
+ DEVMETHOD(device_shutdown, bus_generic_shutdown),
+
+ {0, 0}
+};
+
+static driver_t clock_driver = {
+ "clock",
+ clock_methods,
+ sizeof(struct clock_softc),
+};
+
+static devclass_t clock_devclass;
+
+DRIVER_MODULE(clock, nexus, clock_driver, clock_devclass, 0, 0);
Property changes on: trunk/sys/mips/mips/tick.c
___________________________________________________________________
Added: svn:eol-style
## -0,0 +1 ##
+native
\ No newline at end of property
Added: svn:keywords
## -0,0 +1 ##
+MidnightBSD=%H
\ No newline at end of property
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## -0,0 +1 ##
+text/plain
\ No newline at end of property
Added: trunk/sys/mips/mips/tlb.c
===================================================================
--- trunk/sys/mips/mips/tlb.c (rev 0)
+++ trunk/sys/mips/mips/tlb.c 2018-05-26 21:55:02 UTC (rev 9987)
@@ -0,0 +1,395 @@
+/* $MidnightBSD$ */
+/*-
+ * Copyright (c) 2004-2010 Juli Mallett <jmallett at FreeBSD.org>
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ * $FreeBSD: stable/10/sys/mips/mips/tlb.c 255935 2013-09-29 10:14:16Z adrian $
+ */
+
+#include "opt_ddb.h"
+
+#include <sys/param.h>
+#include <sys/kernel.h>
+#include <sys/systm.h>
+#include <sys/pcpu.h>
+#include <sys/smp.h>
+
+#include <vm/vm.h>
+#include <vm/pmap.h>
+
+#include <machine/pte.h>
+#include <machine/tlb.h>
+
+#if defined(CPU_CNMIPS)
+#define MIPS_MAX_TLB_ENTRIES 128
+#elif defined(CPU_NLM)
+#define MIPS_MAX_TLB_ENTRIES (2048 + 128)
+#else
+#define MIPS_MAX_TLB_ENTRIES 64
+#endif
+
+struct tlb_state {
+ unsigned wired;
+ struct tlb_entry {
+ register_t entryhi;
+ register_t entrylo0;
+ register_t entrylo1;
+ register_t pagemask;
+ } entry[MIPS_MAX_TLB_ENTRIES];
+};
+
+static struct tlb_state tlb_state[MAXCPU];
+
+#if 0
+/*
+ * PageMask must increment in steps of 2 bits.
+ */
+COMPILE_TIME_ASSERT(POPCNT(TLBMASK_MASK) % 2 == 0);
+#endif
+
+static inline void
+tlb_probe(void)
+{
+ __asm __volatile ("tlbp" : : : "memory");
+ mips_cp0_sync();
+}
+
+static inline void
+tlb_read(void)
+{
+ __asm __volatile ("tlbr" : : : "memory");
+ mips_cp0_sync();
+}
+
+static inline void
+tlb_write_indexed(void)
+{
+ __asm __volatile ("tlbwi" : : : "memory");
+ mips_cp0_sync();
+}
+
+static inline void
+tlb_write_random(void)
+{
+ __asm __volatile ("tlbwr" : : : "memory");
+ mips_cp0_sync();
+}
+
+static void tlb_invalidate_one(unsigned);
+
+void
+tlb_insert_wired(unsigned i, vm_offset_t va, pt_entry_t pte0, pt_entry_t pte1)
+{
+ register_t asid;
+ register_t s;
+
+ va &= ~PAGE_MASK;
+
+ s = intr_disable();
+ asid = mips_rd_entryhi() & TLBHI_ASID_MASK;
+
+ mips_wr_index(i);
+ mips_wr_pagemask(0);
+ mips_wr_entryhi(TLBHI_ENTRY(va, 0));
+ mips_wr_entrylo0(pte0);
+ mips_wr_entrylo1(pte1);
+ tlb_write_indexed();
+
+ mips_wr_entryhi(asid);
+ intr_restore(s);
+}
+
+void
+tlb_invalidate_address(struct pmap *pmap, vm_offset_t va)
+{
+ register_t asid;
+ register_t s;
+ int i;
+
+ va &= ~PAGE_MASK;
+
+ s = intr_disable();
+ asid = mips_rd_entryhi() & TLBHI_ASID_MASK;
+
+ mips_wr_pagemask(0);
+ mips_wr_entryhi(TLBHI_ENTRY(va, pmap_asid(pmap)));
+ tlb_probe();
+ i = mips_rd_index();
+ if (i >= 0)
+ tlb_invalidate_one(i);
+
+ mips_wr_entryhi(asid);
+ intr_restore(s);
+}
+
+void
+tlb_invalidate_all(void)
+{
+ register_t asid;
+ register_t s;
+ unsigned i;
+
+ s = intr_disable();
+ asid = mips_rd_entryhi() & TLBHI_ASID_MASK;
+
+ for (i = mips_rd_wired(); i < num_tlbentries; i++)
+ tlb_invalidate_one(i);
+
+ mips_wr_entryhi(asid);
+ intr_restore(s);
+}
+
+void
+tlb_invalidate_all_user(struct pmap *pmap)
+{
+ register_t asid;
+ register_t s;
+ unsigned i;
+
+ s = intr_disable();
+ asid = mips_rd_entryhi() & TLBHI_ASID_MASK;
+
+ for (i = mips_rd_wired(); i < num_tlbentries; i++) {
+ register_t uasid;
+
+ mips_wr_index(i);
+ tlb_read();
+
+ uasid = mips_rd_entryhi() & TLBHI_ASID_MASK;
+ if (pmap == NULL) {
+ /*
+ * Invalidate all non-kernel entries.
+ */
+ if (uasid == 0)
+ continue;
+ } else {
+ /*
+ * Invalidate this pmap's entries.
+ */
+ if (uasid != pmap_asid(pmap))
+ continue;
+ }
+ tlb_invalidate_one(i);
+ }
+
+ mips_wr_entryhi(asid);
+ intr_restore(s);
+}
+
+/*
+ * Invalidates any TLB entries that map a virtual page from the specified
+ * address range. If "end" is zero, then every virtual page is considered to
+ * be within the address range's upper bound.
+ */
+void
+tlb_invalidate_range(pmap_t pmap, vm_offset_t start, vm_offset_t end)
+{
+ register_t asid, end_hi, hi, hi_pagemask, s, save_asid, start_hi;
+ int i;
+
+ KASSERT(start < end || (end == 0 && start > 0),
+ ("tlb_invalidate_range: invalid range"));
+
+ /*
+ * Truncate the virtual address "start" to an even page frame number,
+ * and round the virtual address "end" to an even page frame number.
+ */
+ start &= ~((1 << TLBMASK_SHIFT) - 1);
+ end = (end + (1 << TLBMASK_SHIFT) - 1) & ~((1 << TLBMASK_SHIFT) - 1);
+
+ s = intr_disable();
+ save_asid = mips_rd_entryhi() & TLBHI_ASID_MASK;
+
+ asid = pmap_asid(pmap);
+ start_hi = TLBHI_ENTRY(start, asid);
+ end_hi = TLBHI_ENTRY(end, asid);
+
+ /*
+ * Select the fastest method for invalidating the TLB entries.
+ */
+ if (end - start < num_tlbentries << TLBMASK_SHIFT || (end == 0 &&
+ start >= -(num_tlbentries << TLBMASK_SHIFT))) {
+ /*
+ * The virtual address range is small compared to the size of
+ * the TLB. Probe the TLB for each even numbered page frame
+ * within the virtual address range.
+ */
+ for (hi = start_hi; hi != end_hi; hi += 1 << TLBMASK_SHIFT) {
+ mips_wr_pagemask(0);
+ mips_wr_entryhi(hi);
+ tlb_probe();
+ i = mips_rd_index();
+ if (i >= 0)
+ tlb_invalidate_one(i);
+ }
+ } else {
+ /*
+ * The virtual address range is large compared to the size of
+ * the TLB. Test every non-wired TLB entry.
+ */
+ for (i = mips_rd_wired(); i < num_tlbentries; i++) {
+ mips_wr_index(i);
+ tlb_read();
+ hi = mips_rd_entryhi();
+ if ((hi & TLBHI_ASID_MASK) == asid && (hi < end_hi ||
+ end == 0)) {
+ /*
+ * If "hi" is a large page that spans
+ * "start_hi", then it must be invalidated.
+ */
+ hi_pagemask = mips_rd_pagemask();
+ if (hi >= (start_hi & ~(hi_pagemask <<
+ TLBMASK_SHIFT)))
+ tlb_invalidate_one(i);
+ }
+ }
+ }
+
+ mips_wr_entryhi(save_asid);
+ intr_restore(s);
+}
+
+/* XXX Only if DDB? */
+void
+tlb_save(void)
+{
+ unsigned ntlb, i, cpu;
+
+ cpu = PCPU_GET(cpuid);
+ if (num_tlbentries > MIPS_MAX_TLB_ENTRIES)
+ ntlb = MIPS_MAX_TLB_ENTRIES;
+ else
+ ntlb = num_tlbentries;
+ tlb_state[cpu].wired = mips_rd_wired();
+ for (i = 0; i < ntlb; i++) {
+ mips_wr_index(i);
+ tlb_read();
+
+ tlb_state[cpu].entry[i].entryhi = mips_rd_entryhi();
+ tlb_state[cpu].entry[i].pagemask = mips_rd_pagemask();
+ tlb_state[cpu].entry[i].entrylo0 = mips_rd_entrylo0();
+ tlb_state[cpu].entry[i].entrylo1 = mips_rd_entrylo1();
+ }
+}
+
+void
+tlb_update(struct pmap *pmap, vm_offset_t va, pt_entry_t pte)
+{
+ register_t asid;
+ register_t s;
+ int i;
+
+ va &= ~PAGE_MASK;
+ pte &= ~TLBLO_SWBITS_MASK;
+
+ s = intr_disable();
+ asid = mips_rd_entryhi() & TLBHI_ASID_MASK;
+
+ mips_wr_pagemask(0);
+ mips_wr_entryhi(TLBHI_ENTRY(va, pmap_asid(pmap)));
+ tlb_probe();
+ i = mips_rd_index();
+ if (i >= 0) {
+ tlb_read();
+
+ if ((va & PAGE_SIZE) == 0) {
+ mips_wr_entrylo0(pte);
+ } else {
+ mips_wr_entrylo1(pte);
+ }
+ tlb_write_indexed();
+ }
+
+ mips_wr_entryhi(asid);
+ intr_restore(s);
+}
+
+static void
+tlb_invalidate_one(unsigned i)
+{
+ /* XXX an invalid ASID? */
+ mips_wr_entryhi(TLBHI_ENTRY(MIPS_KSEG0_START + (2 * i * PAGE_SIZE), 0));
+ mips_wr_entrylo0(0);
+ mips_wr_entrylo1(0);
+ mips_wr_pagemask(0);
+ mips_wr_index(i);
+ tlb_write_indexed();
+}
+
+#ifdef DDB
+#include <ddb/ddb.h>
+
+DB_SHOW_COMMAND(tlb, ddb_dump_tlb)
+{
+ register_t ehi, elo0, elo1, epagemask;
+ unsigned i, cpu, ntlb;
+
+ /*
+ * XXX
+ * The worst conversion from hex to decimal ever.
+ */
+ if (have_addr)
+ cpu = ((addr >> 4) % 16) * 10 + (addr % 16);
+ else
+ cpu = PCPU_GET(cpuid);
+
+ if (cpu < 0 || cpu >= mp_ncpus) {
+ db_printf("Invalid CPU %u\n", cpu);
+ return;
+ }
+ if (num_tlbentries > MIPS_MAX_TLB_ENTRIES) {
+ ntlb = MIPS_MAX_TLB_ENTRIES;
+ db_printf("Warning: Only %d of %d TLB entries saved!\n",
+ ntlb, num_tlbentries);
+ } else
+ ntlb = num_tlbentries;
+
+ if (cpu == PCPU_GET(cpuid))
+ tlb_save();
+
+ db_printf("Beginning TLB dump for CPU %u...\n", cpu);
+ for (i = 0; i < ntlb; i++) {
+ if (i == tlb_state[cpu].wired) {
+ if (i != 0)
+ db_printf("^^^ WIRED ENTRIES ^^^\n");
+ else
+ db_printf("(No wired entries.)\n");
+ }
+
+ /* XXX PageMask. */
+ ehi = tlb_state[cpu].entry[i].entryhi;
+ elo0 = tlb_state[cpu].entry[i].entrylo0;
+ elo1 = tlb_state[cpu].entry[i].entrylo1;
+ epagemask = tlb_state[cpu].entry[i].pagemask;
+
+ if (elo0 == 0 && elo1 == 0)
+ continue;
+
+ db_printf("#%u\t=> %jx (pagemask %jx)\n", i, (intmax_t)ehi, (intmax_t) epagemask);
+ db_printf(" Lo0\t%jx\t(%#jx)\n", (intmax_t)elo0, (intmax_t)TLBLO_PTE_TO_PA(elo0));
+ db_printf(" Lo1\t%jx\t(%#jx)\n", (intmax_t)elo1, (intmax_t)TLBLO_PTE_TO_PA(elo1));
+ }
+ db_printf("Finished.\n");
+}
+#endif
Property changes on: trunk/sys/mips/mips/tlb.c
___________________________________________________________________
Added: svn:eol-style
## -0,0 +1 ##
+native
\ No newline at end of property
Added: svn:keywords
## -0,0 +1 ##
+MidnightBSD=%H
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+text/plain
\ No newline at end of property
Added: trunk/sys/mips/mips/trap.c
===================================================================
--- trunk/sys/mips/mips/trap.c (rev 0)
+++ trunk/sys/mips/mips/trap.c 2018-05-26 21:55:02 UTC (rev 9987)
@@ -0,0 +1,1714 @@
+/* $MidnightBSD$ */
+/* $OpenBSD: trap.c,v 1.19 1998/09/30 12:40:41 pefo Exp $ */
+/* tracked to 1.23 */
+/*-
+ * Copyright (c) 1988 University of Utah.
+ * Copyright (c) 1992, 1993
+ * The Regents of the University of California. All rights reserved.
+ *
+ * This code is derived from software contributed to Berkeley by
+ * the Systems Programming Group of the University of Utah Computer
+ * Science Department and Ralph Campbell.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * 4. Neither the name of the University nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ * from: Utah Hdr: trap.c 1.32 91/04/06
+ *
+ * from: @(#)trap.c 8.5 (Berkeley) 1/11/94
+ * JNPR: trap.c,v 1.13.2.2 2007/08/29 10:03:49 girish
+ */
+#include <sys/cdefs.h>
+__FBSDID("$FreeBSD: stable/10/sys/mips/mips/trap.c 269752 2014-08-09 14:05:01Z markj $");
+
+#include "opt_compat.h"
+#include "opt_ddb.h"
+#include "opt_global.h"
+#include "opt_ktrace.h"
+#include "opt_kdtrace.h"
+
+#include <sys/param.h>
+#include <sys/systm.h>
+#include <sys/sysent.h>
+#include <sys/proc.h>
+#include <sys/kernel.h>
+#include <sys/signalvar.h>
+#include <sys/syscall.h>
+#include <sys/lock.h>
+#include <vm/vm.h>
+#include <vm/vm_extern.h>
+#include <vm/vm_kern.h>
+#include <vm/vm_page.h>
+#include <vm/vm_map.h>
+#include <vm/vm_param.h>
+#include <sys/vmmeter.h>
+#include <sys/ptrace.h>
+#include <sys/user.h>
+#include <sys/buf.h>
+#include <sys/vnode.h>
+#include <sys/pioctl.h>
+#include <sys/sysctl.h>
+#include <sys/syslog.h>
+#include <sys/bus.h>
+#ifdef KTRACE
+#include <sys/ktrace.h>
+#endif
+#include <net/netisr.h>
+
+#include <machine/trap.h>
+#include <machine/cpu.h>
+#include <machine/pte.h>
+#include <machine/pmap.h>
+#include <machine/md_var.h>
+#include <machine/mips_opcode.h>
+#include <machine/frame.h>
+#include <machine/regnum.h>
+#include <machine/tls.h>
+
+#ifdef DDB
+#include <machine/db_machdep.h>
+#include <ddb/db_sym.h>
+#include <ddb/ddb.h>
+#include <sys/kdb.h>
+#endif
+
+#ifdef KDTRACE_HOOKS
+#include <sys/dtrace_bsd.h>
+#endif
+
+#ifdef TRAP_DEBUG
+int trap_debug = 0;
+SYSCTL_INT(_machdep, OID_AUTO, trap_debug, CTLFLAG_RW,
+ &trap_debug, 0, "Debug information on all traps");
+#endif
+
+#define lbu_macro(data, addr) \
+ __asm __volatile ("lbu %0, 0x0(%1)" \
+ : "=r" (data) /* outputs */ \
+ : "r" (addr)); /* inputs */
+
+#define lb_macro(data, addr) \
+ __asm __volatile ("lb %0, 0x0(%1)" \
+ : "=r" (data) /* outputs */ \
+ : "r" (addr)); /* inputs */
+
+#define lwl_macro(data, addr) \
+ __asm __volatile ("lwl %0, 0x0(%1)" \
+ : "=r" (data) /* outputs */ \
+ : "r" (addr)); /* inputs */
+
+#define lwr_macro(data, addr) \
+ __asm __volatile ("lwr %0, 0x0(%1)" \
+ : "=r" (data) /* outputs */ \
+ : "r" (addr)); /* inputs */
+
+#define ldl_macro(data, addr) \
+ __asm __volatile ("ldl %0, 0x0(%1)" \
+ : "=r" (data) /* outputs */ \
+ : "r" (addr)); /* inputs */
+
+#define ldr_macro(data, addr) \
+ __asm __volatile ("ldr %0, 0x0(%1)" \
+ : "=r" (data) /* outputs */ \
+ : "r" (addr)); /* inputs */
+
+#define sb_macro(data, addr) \
+ __asm __volatile ("sb %0, 0x0(%1)" \
+ : /* outputs */ \
+ : "r" (data), "r" (addr)); /* inputs */
+
+#define swl_macro(data, addr) \
+ __asm __volatile ("swl %0, 0x0(%1)" \
+ : /* outputs */ \
+ : "r" (data), "r" (addr)); /* inputs */
+
+#define swr_macro(data, addr) \
+ __asm __volatile ("swr %0, 0x0(%1)" \
+ : /* outputs */ \
+ : "r" (data), "r" (addr)); /* inputs */
+
+#define sdl_macro(data, addr) \
+ __asm __volatile ("sdl %0, 0x0(%1)" \
+ : /* outputs */ \
+ : "r" (data), "r" (addr)); /* inputs */
+
+#define sdr_macro(data, addr) \
+ __asm __volatile ("sdr %0, 0x0(%1)" \
+ : /* outputs */ \
+ : "r" (data), "r" (addr)); /* inputs */
+
+static void log_illegal_instruction(const char *, struct trapframe *);
+static void log_bad_page_fault(char *, struct trapframe *, int);
+static void log_frame_dump(struct trapframe *frame);
+static void get_mapping_info(vm_offset_t, pd_entry_t **, pt_entry_t **);
+
+#ifdef TRAP_DEBUG
+static void trap_frame_dump(struct trapframe *frame);
+#endif
+
+void (*machExceptionTable[]) (void)= {
+/*
+ * The kernel exception handlers.
+ */
+ MipsKernIntr, /* external interrupt */
+ MipsKernGenException, /* TLB modification */
+ MipsTLBInvalidException,/* TLB miss (load or instr. fetch) */
+ MipsTLBInvalidException,/* TLB miss (store) */
+ MipsKernGenException, /* address error (load or I-fetch) */
+ MipsKernGenException, /* address error (store) */
+ MipsKernGenException, /* bus error (I-fetch) */
+ MipsKernGenException, /* bus error (load or store) */
+ MipsKernGenException, /* system call */
+ MipsKernGenException, /* breakpoint */
+ MipsKernGenException, /* reserved instruction */
+ MipsKernGenException, /* coprocessor unusable */
+ MipsKernGenException, /* arithmetic overflow */
+ MipsKernGenException, /* trap exception */
+ MipsKernGenException, /* virtual coherence exception inst */
+ MipsKernGenException, /* floating point exception */
+ MipsKernGenException, /* reserved */
+ MipsKernGenException, /* reserved */
+ MipsKernGenException, /* reserved */
+ MipsKernGenException, /* reserved */
+ MipsKernGenException, /* reserved */
+ MipsKernGenException, /* reserved */
+ MipsKernGenException, /* reserved */
+ MipsKernGenException, /* watch exception */
+ MipsKernGenException, /* reserved */
+ MipsKernGenException, /* reserved */
+ MipsKernGenException, /* reserved */
+ MipsKernGenException, /* reserved */
+ MipsKernGenException, /* reserved */
+ MipsKernGenException, /* reserved */
+ MipsKernGenException, /* reserved */
+ MipsKernGenException, /* virtual coherence exception data */
+/*
+ * The user exception handlers.
+ */
+ MipsUserIntr, /* 0 */
+ MipsUserGenException, /* 1 */
+ MipsTLBInvalidException,/* 2 */
+ MipsTLBInvalidException,/* 3 */
+ MipsUserGenException, /* 4 */
+ MipsUserGenException, /* 5 */
+ MipsUserGenException, /* 6 */
+ MipsUserGenException, /* 7 */
+ MipsUserGenException, /* 8 */
+ MipsUserGenException, /* 9 */
+ MipsUserGenException, /* 10 */
+ MipsUserGenException, /* 11 */
+ MipsUserGenException, /* 12 */
+ MipsUserGenException, /* 13 */
+ MipsUserGenException, /* 14 */
+ MipsUserGenException, /* 15 */
+ MipsUserGenException, /* 16 */
+ MipsUserGenException, /* 17 */
+ MipsUserGenException, /* 18 */
+ MipsUserGenException, /* 19 */
+ MipsUserGenException, /* 20 */
+ MipsUserGenException, /* 21 */
+ MipsUserGenException, /* 22 */
+ MipsUserGenException, /* 23 */
+ MipsUserGenException, /* 24 */
+ MipsUserGenException, /* 25 */
+ MipsUserGenException, /* 26 */
+ MipsUserGenException, /* 27 */
+ MipsUserGenException, /* 28 */
+ MipsUserGenException, /* 29 */
+ MipsUserGenException, /* 20 */
+ MipsUserGenException, /* 31 */
+};
+
+char *trap_type[] = {
+ "external interrupt",
+ "TLB modification",
+ "TLB miss (load or instr. fetch)",
+ "TLB miss (store)",
+ "address error (load or I-fetch)",
+ "address error (store)",
+ "bus error (I-fetch)",
+ "bus error (load or store)",
+ "system call",
+ "breakpoint",
+ "reserved instruction",
+ "coprocessor unusable",
+ "arithmetic overflow",
+ "trap",
+ "virtual coherency instruction",
+ "floating point",
+ "reserved 16",
+ "reserved 17",
+ "reserved 18",
+ "reserved 19",
+ "reserved 20",
+ "reserved 21",
+ "reserved 22",
+ "watch",
+ "reserved 24",
+ "reserved 25",
+ "reserved 26",
+ "reserved 27",
+ "reserved 28",
+ "reserved 29",
+ "reserved 30",
+ "virtual coherency data",
+};
+
+#if !defined(SMP) && (defined(DDB) || defined(DEBUG))
+struct trapdebug trapdebug[TRAPSIZE], *trp = trapdebug;
+#endif
+
+#if defined(DDB) || defined(DEBUG)
+void stacktrace(struct trapframe *);
+void logstacktrace(struct trapframe *);
+#endif
+
+#define KERNLAND(x) ((vm_offset_t)(x) >= VM_MIN_KERNEL_ADDRESS && (vm_offset_t)(x) < VM_MAX_KERNEL_ADDRESS)
+#define DELAYBRANCH(x) ((int)(x) < 0)
+
+/*
+ * MIPS load/store access type
+ */
+enum {
+ MIPS_LHU_ACCESS = 1,
+ MIPS_LH_ACCESS,
+ MIPS_LWU_ACCESS,
+ MIPS_LW_ACCESS,
+ MIPS_LD_ACCESS,
+ MIPS_SH_ACCESS,
+ MIPS_SW_ACCESS,
+ MIPS_SD_ACCESS
+};
+
+char *access_name[] = {
+ "Load Halfword Unsigned",
+ "Load Halfword",
+ "Load Word Unsigned",
+ "Load Word",
+ "Load Doubleword",
+ "Store Halfword",
+ "Store Word",
+ "Store Doubleword"
+};
+
+#ifdef CPU_CNMIPS
+#include <machine/octeon_cop2.h>
+#endif
+
+static int allow_unaligned_acc = 1;
+
+SYSCTL_INT(_vm, OID_AUTO, allow_unaligned_acc, CTLFLAG_RW,
+ &allow_unaligned_acc, 0, "Allow unaligned accesses");
+
+/*
+ * FP emulation is assumed to work on O32, but the code is outdated and crufty
+ * enough that it's a more sensible default to have it disabled when using
+ * other ABIs. At the very least, it needs a lot of help in using
+ * type-semantic ABI-oblivious macros for everything it does.
+ */
+#if defined(__mips_o32)
+static int emulate_fp = 1;
+#else
+static int emulate_fp = 0;
+#endif
+SYSCTL_INT(_machdep, OID_AUTO, emulate_fp, CTLFLAG_RW,
+ &emulate_fp, 0, "Emulate unimplemented FPU instructions");
+
+static int emulate_unaligned_access(struct trapframe *frame, int mode);
+
+extern void fswintrberr(void); /* XXX */
+
+int
+cpu_fetch_syscall_args(struct thread *td, struct syscall_args *sa)
+{
+ struct trapframe *locr0 = td->td_frame;
+ struct sysentvec *se;
+ int error, nsaved;
+
+ bzero(sa->args, sizeof(sa->args));
+
+ /* compute next PC after syscall instruction */
+ td->td_pcb->pcb_tpc = sa->trapframe->pc; /* Remember if restart */
+ if (DELAYBRANCH(sa->trapframe->cause)) /* Check BD bit */
+ locr0->pc = MipsEmulateBranch(locr0, sa->trapframe->pc, 0, 0);
+ else
+ locr0->pc += sizeof(int);
+ sa->code = locr0->v0;
+
+ switch (sa->code) {
+ case SYS___syscall:
+ case SYS_syscall:
+ /*
+ * This is an indirect syscall, in which the code is the first argument.
+ */
+#if (!defined(__mips_n32) && !defined(__mips_n64)) || defined(COMPAT_FREEBSD32)
+ if (sa->code == SYS___syscall && SV_PROC_FLAG(td->td_proc, SV_ILP32)) {
+ /*
+ * Like syscall, but code is a quad, so as to maintain alignment
+ * for the rest of the arguments.
+ */
+ if (_QUAD_LOWWORD == 0)
+ sa->code = locr0->a0;
+ else
+ sa->code = locr0->a1;
+ sa->args[0] = locr0->a2;
+ sa->args[1] = locr0->a3;
+ nsaved = 2;
+ break;
+ }
+#endif
+ /*
+ * This is either not a quad syscall, or is a quad syscall with a
+ * new ABI in which quads fit in a single register.
+ */
+ sa->code = locr0->a0;
+ sa->args[0] = locr0->a1;
+ sa->args[1] = locr0->a2;
+ sa->args[2] = locr0->a3;
+ nsaved = 3;
+#if defined(__mips_n32) || defined(__mips_n64)
+#ifdef COMPAT_FREEBSD32
+ if (!SV_PROC_FLAG(td->td_proc, SV_ILP32)) {
+#endif
+ /*
+ * Non-o32 ABIs support more arguments in registers.
+ */
+ sa->args[3] = locr0->a4;
+ sa->args[4] = locr0->a5;
+ sa->args[5] = locr0->a6;
+ sa->args[6] = locr0->a7;
+ nsaved += 4;
+#ifdef COMPAT_FREEBSD32
+ }
+#endif
+#endif
+ break;
+ default:
+ /*
+ * A direct syscall, arguments are just parameters to the syscall.
+ */
+ sa->args[0] = locr0->a0;
+ sa->args[1] = locr0->a1;
+ sa->args[2] = locr0->a2;
+ sa->args[3] = locr0->a3;
+ nsaved = 4;
+#if defined (__mips_n32) || defined(__mips_n64)
+#ifdef COMPAT_FREEBSD32
+ if (!SV_PROC_FLAG(td->td_proc, SV_ILP32)) {
+#endif
+ /*
+ * Non-o32 ABIs support more arguments in registers.
+ */
+ sa->args[4] = locr0->a4;
+ sa->args[5] = locr0->a5;
+ sa->args[6] = locr0->a6;
+ sa->args[7] = locr0->a7;
+ nsaved += 4;
+#ifdef COMPAT_FREEBSD32
+ }
+#endif
+#endif
+ break;
+ }
+
+#ifdef TRAP_DEBUG
+ if (trap_debug)
+ printf("SYSCALL #%d pid:%u\n", sa->code, td->td_proc->p_pid);
+#endif
+
+ se = td->td_proc->p_sysent;
+ /*
+ * XXX
+ * Shouldn't this go before switching on the code?
+ */
+ if (se->sv_mask)
+ sa->code &= se->sv_mask;
+
+ if (sa->code >= se->sv_size)
+ sa->callp = &se->sv_table[0];
+ else
+ sa->callp = &se->sv_table[sa->code];
+
+ sa->narg = sa->callp->sy_narg;
+
+ if (sa->narg > nsaved) {
+#if defined(__mips_n32) || defined(__mips_n64)
+ /*
+ * XXX
+ * Is this right for new ABIs? I think the 4 there
+ * should be 8, size there are 8 registers to skip,
+ * not 4, but I'm not certain.
+ */
+#ifdef COMPAT_FREEBSD32
+ if (!SV_PROC_FLAG(td->td_proc, SV_ILP32))
+#endif
+ printf("SYSCALL #%u pid:%u, narg (%u) > nsaved (%u).\n",
+ sa->code, td->td_proc->p_pid, sa->narg, nsaved);
+#endif
+#if (defined(__mips_n32) || defined(__mips_n64)) && defined(COMPAT_FREEBSD32)
+ if (SV_PROC_FLAG(td->td_proc, SV_ILP32)) {
+ unsigned i;
+ int32_t arg;
+
+ error = 0; /* XXX GCC is awful. */
+ for (i = nsaved; i < sa->narg; i++) {
+ error = copyin((caddr_t)(intptr_t)(locr0->sp +
+ (4 + (i - nsaved)) * sizeof(int32_t)),
+ (caddr_t)&arg, sizeof arg);
+ if (error != 0)
+ break;
+ sa->args[i] = arg;
+ }
+ } else
+#endif
+ error = copyin((caddr_t)(intptr_t)(locr0->sp +
+ 4 * sizeof(register_t)), (caddr_t)&sa->args[nsaved],
+ (u_int)(sa->narg - nsaved) * sizeof(register_t));
+ if (error != 0) {
+ locr0->v0 = error;
+ locr0->a3 = 1;
+ }
+ } else
+ error = 0;
+
+ if (error == 0) {
+ td->td_retval[0] = 0;
+ td->td_retval[1] = locr0->v1;
+ }
+
+ return (error);
+}
+
+#undef __FBSDID
+#define __FBSDID(x)
+#include "../../kern/subr_syscall.c"
+
+/*
+ * Handle an exception.
+ * Called from MipsKernGenException() or MipsUserGenException()
+ * when a processor trap occurs.
+ * In the case of a kernel trap, we return the pc where to resume if
+ * p->p_addr->u_pcb.pcb_onfault is set, otherwise, return old pc.
+ */
+register_t
+trap(struct trapframe *trapframe)
+{
+ int type, usermode;
+ int i = 0;
+ unsigned ucode = 0;
+ struct thread *td = curthread;
+ struct proc *p = curproc;
+ vm_prot_t ftype;
+ pmap_t pmap;
+ int access_type;
+ ksiginfo_t ksi;
+ char *msg = NULL;
+ intptr_t addr = 0;
+ register_t pc;
+ int cop;
+ register_t *frame_regs;
+
+ trapdebug_enter(trapframe, 0);
+
+ type = (trapframe->cause & MIPS_CR_EXC_CODE) >> MIPS_CR_EXC_CODE_SHIFT;
+ if (TRAPF_USERMODE(trapframe)) {
+ type |= T_USER;
+ usermode = 1;
+ } else {
+ usermode = 0;
+ }
+
+ /*
+ * Enable hardware interrupts if they were on before the trap. If it
+ * was off disable all so we don't accidently enable it when doing a
+ * return to userland.
+ */
+ if (trapframe->sr & MIPS_SR_INT_IE) {
+ set_intr_mask(trapframe->sr & MIPS_SR_INT_MASK);
+ intr_enable();
+ } else {
+ intr_disable();
+ }
+
+#ifdef TRAP_DEBUG
+ if (trap_debug) {
+ static vm_offset_t last_badvaddr = 0;
+ static vm_offset_t this_badvaddr = 0;
+ static int count = 0;
+ u_int32_t pid;
+
+ printf("trap type %x (%s - ", type,
+ trap_type[type & (~T_USER)]);
+
+ if (type & T_USER)
+ printf("user mode)\n");
+ else
+ printf("kernel mode)\n");
+
+#ifdef SMP
+ printf("cpuid = %d\n", PCPU_GET(cpuid));
+#endif
+ pid = mips_rd_entryhi() & TLBHI_ASID_MASK;
+ printf("badaddr = %#jx, pc = %#jx, ra = %#jx, sp = %#jx, sr = %jx, pid = %d, ASID = %u\n",
+ (intmax_t)trapframe->badvaddr, (intmax_t)trapframe->pc, (intmax_t)trapframe->ra,
+ (intmax_t)trapframe->sp, (intmax_t)trapframe->sr,
+ (curproc ? curproc->p_pid : -1), pid);
+
+ switch (type & ~T_USER) {
+ case T_TLB_MOD:
+ case T_TLB_LD_MISS:
+ case T_TLB_ST_MISS:
+ case T_ADDR_ERR_LD:
+ case T_ADDR_ERR_ST:
+ this_badvaddr = trapframe->badvaddr;
+ break;
+ case T_SYSCALL:
+ this_badvaddr = trapframe->ra;
+ break;
+ default:
+ this_badvaddr = trapframe->pc;
+ break;
+ }
+ if ((last_badvaddr == this_badvaddr) &&
+ ((type & ~T_USER) != T_SYSCALL)) {
+ if (++count == 3) {
+ trap_frame_dump(trapframe);
+ panic("too many faults at %p\n", (void *)last_badvaddr);
+ }
+ } else {
+ last_badvaddr = this_badvaddr;
+ count = 0;
+ }
+ }
+#endif
+
+#ifdef KDTRACE_HOOKS
+ /*
+ * A trap can occur while DTrace executes a probe. Before
+ * executing the probe, DTrace blocks re-scheduling and sets
+ * a flag in it's per-cpu flags to indicate that it doesn't
+ * want to fault. On returning from the probe, the no-fault
+ * flag is cleared and finally re-scheduling is enabled.
+ *
+ * If the DTrace kernel module has registered a trap handler,
+ * call it and if it returns non-zero, assume that it has
+ * handled the trap and modified the trap frame so that this
+ * function can return normally.
+ */
+ /*
+ * XXXDTRACE: add pid probe handler here (if ever)
+ */
+ if (!usermode) {
+ if (dtrace_trap_func != NULL && (*dtrace_trap_func)(trapframe, type))
+ return (trapframe->pc);
+ }
+#endif
+
+ switch (type) {
+ case T_MCHECK:
+#ifdef DDB
+ kdb_trap(type, 0, trapframe);
+#endif
+ panic("MCHECK\n");
+ break;
+ case T_TLB_MOD:
+ /* check for kernel address */
+ if (KERNLAND(trapframe->badvaddr)) {
+ if (pmap_emulate_modified(kernel_pmap,
+ trapframe->badvaddr) != 0) {
+ ftype = VM_PROT_WRITE;
+ goto kernel_fault;
+ }
+ return (trapframe->pc);
+ }
+ /* FALLTHROUGH */
+
+ case T_TLB_MOD + T_USER:
+ pmap = &p->p_vmspace->vm_pmap;
+ if (pmap_emulate_modified(pmap, trapframe->badvaddr) != 0) {
+ ftype = VM_PROT_WRITE;
+ goto dofault;
+ }
+ if (!usermode)
+ return (trapframe->pc);
+ goto out;
+
+ case T_TLB_LD_MISS:
+ case T_TLB_ST_MISS:
+ ftype = (type == T_TLB_ST_MISS) ? VM_PROT_WRITE : VM_PROT_READ;
+ /* check for kernel address */
+ if (KERNLAND(trapframe->badvaddr)) {
+ vm_offset_t va;
+ int rv;
+
+ kernel_fault:
+ va = trunc_page((vm_offset_t)trapframe->badvaddr);
+ rv = vm_fault(kernel_map, va, ftype, VM_FAULT_NORMAL);
+ if (rv == KERN_SUCCESS)
+ return (trapframe->pc);
+ if (td->td_pcb->pcb_onfault != NULL) {
+ pc = (register_t)(intptr_t)td->td_pcb->pcb_onfault;
+ td->td_pcb->pcb_onfault = NULL;
+ return (pc);
+ }
+ goto err;
+ }
+
+ /*
+ * It is an error for the kernel to access user space except
+ * through the copyin/copyout routines.
+ */
+ if (td->td_pcb->pcb_onfault == NULL)
+ goto err;
+
+ /* check for fuswintr() or suswintr() getting a page fault */
+ /* XXX There must be a nicer way to do this. */
+ if (td->td_pcb->pcb_onfault == fswintrberr) {
+ pc = (register_t)(intptr_t)td->td_pcb->pcb_onfault;
+ td->td_pcb->pcb_onfault = NULL;
+ return (pc);
+ }
+
+ goto dofault;
+
+ case T_TLB_LD_MISS + T_USER:
+ ftype = VM_PROT_READ;
+ goto dofault;
+
+ case T_TLB_ST_MISS + T_USER:
+ ftype = VM_PROT_WRITE;
+dofault:
+ {
+ vm_offset_t va;
+ struct vmspace *vm;
+ vm_map_t map;
+ int rv = 0;
+
+ vm = p->p_vmspace;
+ map = &vm->vm_map;
+ va = trunc_page((vm_offset_t)trapframe->badvaddr);
+ if (KERNLAND(trapframe->badvaddr)) {
+ /*
+ * Don't allow user-mode faults in kernel
+ * address space.
+ */
+ goto nogo;
+ }
+
+ /*
+ * Keep swapout from messing with us during this
+ * critical time.
+ */
+ PROC_LOCK(p);
+ ++p->p_lock;
+ PROC_UNLOCK(p);
+
+ rv = vm_fault(map, va, ftype, VM_FAULT_NORMAL);
+
+ PROC_LOCK(p);
+ --p->p_lock;
+ PROC_UNLOCK(p);
+ /*
+ * XXXDTRACE: add dtrace_doubletrap_func here?
+ */
+#ifdef VMFAULT_TRACE
+ printf("vm_fault(%p (pmap %p), %p (%p), %x, %d) -> %x at pc %p\n",
+ map, &vm->vm_pmap, (void *)va, (void *)(intptr_t)trapframe->badvaddr,
+ ftype, VM_FAULT_NORMAL, rv, (void *)(intptr_t)trapframe->pc);
+#endif
+
+ if (rv == KERN_SUCCESS) {
+ if (!usermode) {
+ return (trapframe->pc);
+ }
+ goto out;
+ }
+ nogo:
+ if (!usermode) {
+ if (td->td_pcb->pcb_onfault != NULL) {
+ pc = (register_t)(intptr_t)td->td_pcb->pcb_onfault;
+ td->td_pcb->pcb_onfault = NULL;
+ return (pc);
+ }
+ goto err;
+ }
+ ucode = ftype;
+ i = ((rv == KERN_PROTECTION_FAILURE) ? SIGBUS : SIGSEGV);
+ addr = trapframe->pc;
+
+ msg = "BAD_PAGE_FAULT";
+ log_bad_page_fault(msg, trapframe, type);
+
+ break;
+ }
+
+ case T_ADDR_ERR_LD + T_USER: /* misaligned or kseg access */
+ case T_ADDR_ERR_ST + T_USER: /* misaligned or kseg access */
+ if (trapframe->badvaddr < 0 ||
+ trapframe->badvaddr >= VM_MAXUSER_ADDRESS) {
+ msg = "ADDRESS_SPACE_ERR";
+ } else if (allow_unaligned_acc) {
+ int mode;
+
+ if (type == (T_ADDR_ERR_LD + T_USER))
+ mode = VM_PROT_READ;
+ else
+ mode = VM_PROT_WRITE;
+
+ access_type = emulate_unaligned_access(trapframe, mode);
+ if (access_type != 0)
+ goto out;
+ msg = "ALIGNMENT_FIX_ERR";
+ } else {
+ msg = "ADDRESS_ERR";
+ }
+
+ /* FALL THROUGH */
+
+ case T_BUS_ERR_IFETCH + T_USER: /* BERR asserted to cpu */
+ case T_BUS_ERR_LD_ST + T_USER: /* BERR asserted to cpu */
+ ucode = 0; /* XXX should be VM_PROT_something */
+ i = SIGBUS;
+ addr = trapframe->pc;
+ if (!msg)
+ msg = "BUS_ERR";
+ log_bad_page_fault(msg, trapframe, type);
+ break;
+
+ case T_SYSCALL + T_USER:
+ {
+ struct syscall_args sa;
+ int error;
+
+ sa.trapframe = trapframe;
+ error = syscallenter(td, &sa);
+
+#if !defined(SMP) && (defined(DDB) || defined(DEBUG))
+ if (trp == trapdebug)
+ trapdebug[TRAPSIZE - 1].code = sa.code;
+ else
+ trp[-1].code = sa.code;
+#endif
+ trapdebug_enter(td->td_frame, -sa.code);
+
+ /*
+ * The sync'ing of I & D caches for SYS_ptrace() is
+ * done by procfs_domem() through procfs_rwmem()
+ * instead of being done here under a special check
+ * for SYS_ptrace().
+ */
+ syscallret(td, error, &sa);
+ return (trapframe->pc);
+ }
+
+#ifdef DDB
+ case T_BREAK:
+ kdb_trap(type, 0, trapframe);
+ return (trapframe->pc);
+#endif
+
+ case T_BREAK + T_USER:
+ {
+ intptr_t va;
+ uint32_t instr;
+
+ /* compute address of break instruction */
+ va = trapframe->pc;
+ if (DELAYBRANCH(trapframe->cause))
+ va += sizeof(int);
+
+ /* read break instruction */
+ instr = fuword32((caddr_t)va);
+#if 0
+ printf("trap: %s (%d) breakpoint %x at %x: (adr %x ins %x)\n",
+ p->p_comm, p->p_pid, instr, trapframe->pc,
+ p->p_md.md_ss_addr, p->p_md.md_ss_instr); /* XXX */
+#endif
+ if (td->td_md.md_ss_addr != va ||
+ instr != MIPS_BREAK_SSTEP) {
+ i = SIGTRAP;
+ addr = trapframe->pc;
+ break;
+ }
+ /*
+ * The restoration of the original instruction and
+ * the clearing of the berakpoint will be done later
+ * by the call to ptrace_clear_single_step() in
+ * issignal() when SIGTRAP is processed.
+ */
+ addr = trapframe->pc;
+ i = SIGTRAP;
+ break;
+ }
+
+ case T_IWATCH + T_USER:
+ case T_DWATCH + T_USER:
+ {
+ intptr_t va;
+
+ /* compute address of trapped instruction */
+ va = trapframe->pc;
+ if (DELAYBRANCH(trapframe->cause))
+ va += sizeof(int);
+ printf("watch exception @ %p\n", (void *)va);
+ i = SIGTRAP;
+ addr = va;
+ break;
+ }
+
+ case T_TRAP + T_USER:
+ {
+ intptr_t va;
+ uint32_t instr;
+ struct trapframe *locr0 = td->td_frame;
+
+ /* compute address of trap instruction */
+ va = trapframe->pc;
+ if (DELAYBRANCH(trapframe->cause))
+ va += sizeof(int);
+ /* read break instruction */
+ instr = fuword32((caddr_t)va);
+
+ if (DELAYBRANCH(trapframe->cause)) { /* Check BD bit */
+ locr0->pc = MipsEmulateBranch(locr0, trapframe->pc, 0,
+ 0);
+ } else {
+ locr0->pc += sizeof(int);
+ }
+ addr = va;
+ i = SIGEMT; /* Stuff it with something for now */
+ break;
+ }
+
+ case T_RES_INST + T_USER:
+ {
+ InstFmt inst;
+ inst = *(InstFmt *)(intptr_t)trapframe->pc;
+ switch (inst.RType.op) {
+ case OP_SPECIAL3:
+ switch (inst.RType.func) {
+ case OP_RDHWR:
+ /* Register 29 used for TLS */
+ if (inst.RType.rd == 29) {
+ frame_regs = &(trapframe->zero);
+ frame_regs[inst.RType.rt] = (register_t)(intptr_t)td->td_md.md_tls;
+#if defined(__mips_n64) && defined(COMPAT_FREEBSD32)
+ if (SV_PROC_FLAG(td->td_proc, SV_ILP32))
+ frame_regs[inst.RType.rt] += TLS_TP_OFFSET + TLS_TCB_SIZE32;
+ else
+#endif
+ frame_regs[inst.RType.rt] += TLS_TP_OFFSET + TLS_TCB_SIZE;
+ trapframe->pc += sizeof(int);
+ goto out;
+ }
+ break;
+ }
+ break;
+ }
+
+ log_illegal_instruction("RES_INST", trapframe);
+ i = SIGILL;
+ addr = trapframe->pc;
+ }
+ break;
+ case T_C2E:
+ case T_C2E + T_USER:
+ goto err;
+ break;
+ case T_COP_UNUSABLE:
+#ifdef CPU_CNMIPS
+ cop = (trapframe->cause & MIPS_CR_COP_ERR) >> MIPS_CR_COP_ERR_SHIFT;
+ /* Handle only COP2 exception */
+ if (cop != 2)
+ goto err;
+
+ addr = trapframe->pc;
+ /* save userland cop2 context if it has been touched */
+ if ((td->td_md.md_flags & MDTD_COP2USED) &&
+ (td->td_md.md_cop2owner == COP2_OWNER_USERLAND)) {
+ if (td->td_md.md_ucop2)
+ octeon_cop2_save(td->td_md.md_ucop2);
+ else
+ panic("COP2 was used in user mode but md_ucop2 is NULL");
+ }
+
+ if (td->td_md.md_cop2 == NULL) {
+ td->td_md.md_cop2 = octeon_cop2_alloc_ctx();
+ if (td->td_md.md_cop2 == NULL)
+ panic("Failed to allocate COP2 context");
+ memset(td->td_md.md_cop2, 0, sizeof(*td->td_md.md_cop2));
+ }
+
+ octeon_cop2_restore(td->td_md.md_cop2);
+
+ /* Make userland re-request its context */
+ td->td_frame->sr &= ~MIPS_SR_COP_2_BIT;
+ td->td_md.md_flags |= MDTD_COP2USED;
+ td->td_md.md_cop2owner = COP2_OWNER_KERNEL;
+ /* Enable COP2, it will be disabled in cpu_switch */
+ mips_wr_status(mips_rd_status() | MIPS_SR_COP_2_BIT);
+ return (trapframe->pc);
+#else
+ goto err;
+ break;
+#endif
+
+ case T_COP_UNUSABLE + T_USER:
+ cop = (trapframe->cause & MIPS_CR_COP_ERR) >> MIPS_CR_COP_ERR_SHIFT;
+ if (cop == 1) {
+#if !defined(CPU_HAVEFPU)
+ /* FP (COP1) instruction */
+ log_illegal_instruction("COP1_UNUSABLE", trapframe);
+ i = SIGILL;
+ break;
+#else
+ addr = trapframe->pc;
+ MipsSwitchFPState(PCPU_GET(fpcurthread), td->td_frame);
+ PCPU_SET(fpcurthread, td);
+ td->td_frame->sr |= MIPS_SR_COP_1_BIT;
+ td->td_md.md_flags |= MDTD_FPUSED;
+ goto out;
+#endif
+ }
+#ifdef CPU_CNMIPS
+ else if (cop == 2) {
+ addr = trapframe->pc;
+ if ((td->td_md.md_flags & MDTD_COP2USED) &&
+ (td->td_md.md_cop2owner == COP2_OWNER_KERNEL)) {
+ if (td->td_md.md_cop2)
+ octeon_cop2_save(td->td_md.md_cop2);
+ else
+ panic("COP2 was used in kernel mode but md_cop2 is NULL");
+ }
+
+ if (td->td_md.md_ucop2 == NULL) {
+ td->td_md.md_ucop2 = octeon_cop2_alloc_ctx();
+ if (td->td_md.md_ucop2 == NULL)
+ panic("Failed to allocate userland COP2 context");
+ memset(td->td_md.md_ucop2, 0, sizeof(*td->td_md.md_ucop2));
+ }
+
+ octeon_cop2_restore(td->td_md.md_ucop2);
+
+ td->td_frame->sr |= MIPS_SR_COP_2_BIT;
+ td->td_md.md_flags |= MDTD_COP2USED;
+ td->td_md.md_cop2owner = COP2_OWNER_USERLAND;
+ goto out;
+ }
+#endif
+ else {
+ log_illegal_instruction("COPn_UNUSABLE", trapframe);
+ i = SIGILL; /* only FPU instructions allowed */
+ break;
+ }
+
+ case T_FPE:
+#if !defined(SMP) && (defined(DDB) || defined(DEBUG))
+ trapDump("fpintr");
+#else
+ printf("FPU Trap: PC %#jx CR %x SR %x\n",
+ (intmax_t)trapframe->pc, (unsigned)trapframe->cause, (unsigned)trapframe->sr);
+ goto err;
+#endif
+
+ case T_FPE + T_USER:
+ if (!emulate_fp) {
+ i = SIGILL;
+ addr = trapframe->pc;
+ break;
+ }
+ MipsFPTrap(trapframe->sr, trapframe->cause, trapframe->pc);
+ goto out;
+
+ case T_OVFLOW + T_USER:
+ i = SIGFPE;
+ addr = trapframe->pc;
+ break;
+
+ case T_ADDR_ERR_LD: /* misaligned access */
+ case T_ADDR_ERR_ST: /* misaligned access */
+#ifdef TRAP_DEBUG
+ if (trap_debug) {
+ printf("+++ ADDR_ERR: type = %d, badvaddr = %#jx\n", type,
+ (intmax_t)trapframe->badvaddr);
+ }
+#endif
+ /* Only allow emulation on a user address */
+ if (allow_unaligned_acc &&
+ ((vm_offset_t)trapframe->badvaddr < VM_MAXUSER_ADDRESS)) {
+ int mode;
+
+ if (type == T_ADDR_ERR_LD)
+ mode = VM_PROT_READ;
+ else
+ mode = VM_PROT_WRITE;
+
+ access_type = emulate_unaligned_access(trapframe, mode);
+ if (access_type != 0)
+ return (trapframe->pc);
+ }
+ /* FALLTHROUGH */
+
+ case T_BUS_ERR_LD_ST: /* BERR asserted to cpu */
+ if (td->td_pcb->pcb_onfault != NULL) {
+ pc = (register_t)(intptr_t)td->td_pcb->pcb_onfault;
+ td->td_pcb->pcb_onfault = NULL;
+ return (pc);
+ }
+
+ /* FALLTHROUGH */
+
+ default:
+err:
+
+#if !defined(SMP) && defined(DEBUG)
+ stacktrace(!usermode ? trapframe : td->td_frame);
+ trapDump("trap");
+#endif
+#ifdef SMP
+ printf("cpu:%d-", PCPU_GET(cpuid));
+#endif
+ printf("Trap cause = %d (%s - ", type,
+ trap_type[type & (~T_USER)]);
+
+ if (type & T_USER)
+ printf("user mode)\n");
+ else
+ printf("kernel mode)\n");
+
+#ifdef TRAP_DEBUG
+ if (trap_debug)
+ printf("badvaddr = %#jx, pc = %#jx, ra = %#jx, sr = %#jxx\n",
+ (intmax_t)trapframe->badvaddr, (intmax_t)trapframe->pc, (intmax_t)trapframe->ra,
+ (intmax_t)trapframe->sr);
+#endif
+
+#ifdef KDB
+ if (debugger_on_panic || kdb_active) {
+ kdb_trap(type, 0, trapframe);
+ }
+#endif
+ panic("trap");
+ }
+ td->td_frame->pc = trapframe->pc;
+ td->td_frame->cause = trapframe->cause;
+ td->td_frame->badvaddr = trapframe->badvaddr;
+ ksiginfo_init_trap(&ksi);
+ ksi.ksi_signo = i;
+ ksi.ksi_code = ucode;
+ ksi.ksi_addr = (void *)addr;
+ ksi.ksi_trapno = type;
+ trapsignal(td, &ksi);
+out:
+
+ /*
+ * Note: we should only get here if returning to user mode.
+ */
+ userret(td, trapframe);
+ return (trapframe->pc);
+}
+
+#if !defined(SMP) && (defined(DDB) || defined(DEBUG))
+void
+trapDump(char *msg)
+{
+ register_t s;
+ int i;
+
+ s = intr_disable();
+ printf("trapDump(%s)\n", msg);
+ for (i = 0; i < TRAPSIZE; i++) {
+ if (trp == trapdebug) {
+ trp = &trapdebug[TRAPSIZE - 1];
+ } else {
+ trp--;
+ }
+
+ if (trp->cause == 0)
+ break;
+
+ printf("%s: ADR %jx PC %jx CR %jx SR %jx\n",
+ trap_type[(trp->cause & MIPS_CR_EXC_CODE) >>
+ MIPS_CR_EXC_CODE_SHIFT],
+ (intmax_t)trp->vadr, (intmax_t)trp->pc,
+ (intmax_t)trp->cause, (intmax_t)trp->status);
+
+ printf(" RA %jx SP %jx code %d\n", (intmax_t)trp->ra,
+ (intmax_t)trp->sp, (int)trp->code);
+ }
+ intr_restore(s);
+}
+#endif
+
+
+/*
+ * Return the resulting PC as if the branch was executed.
+ */
+uintptr_t
+MipsEmulateBranch(struct trapframe *framePtr, uintptr_t instPC, int fpcCSR,
+ uintptr_t instptr)
+{
+ InstFmt inst;
+ register_t *regsPtr = (register_t *) framePtr;
+ uintptr_t retAddr = 0;
+ int condition;
+
+#define GetBranchDest(InstPtr, inst) \
+ (InstPtr + 4 + ((short)inst.IType.imm << 2))
+
+
+ if (instptr) {
+ if (instptr < MIPS_KSEG0_START)
+ inst.word = fuword32((void *)instptr);
+ else
+ inst = *(InstFmt *) instptr;
+ } else {
+ if ((vm_offset_t)instPC < MIPS_KSEG0_START)
+ inst.word = fuword32((void *)instPC);
+ else
+ inst = *(InstFmt *) instPC;
+ }
+
+ switch ((int)inst.JType.op) {
+ case OP_SPECIAL:
+ switch ((int)inst.RType.func) {
+ case OP_JR:
+ case OP_JALR:
+ retAddr = regsPtr[inst.RType.rs];
+ break;
+
+ default:
+ retAddr = instPC + 4;
+ break;
+ }
+ break;
+
+ case OP_BCOND:
+ switch ((int)inst.IType.rt) {
+ case OP_BLTZ:
+ case OP_BLTZL:
+ case OP_BLTZAL:
+ case OP_BLTZALL:
+ if ((int)(regsPtr[inst.RType.rs]) < 0)
+ retAddr = GetBranchDest(instPC, inst);
+ else
+ retAddr = instPC + 8;
+ break;
+
+ case OP_BGEZ:
+ case OP_BGEZL:
+ case OP_BGEZAL:
+ case OP_BGEZALL:
+ if ((int)(regsPtr[inst.RType.rs]) >= 0)
+ retAddr = GetBranchDest(instPC, inst);
+ else
+ retAddr = instPC + 8;
+ break;
+
+ case OP_TGEI:
+ case OP_TGEIU:
+ case OP_TLTI:
+ case OP_TLTIU:
+ case OP_TEQI:
+ case OP_TNEI:
+ retAddr = instPC + 4; /* Like syscall... */
+ break;
+
+ default:
+ panic("MipsEmulateBranch: Bad branch cond");
+ }
+ break;
+
+ case OP_J:
+ case OP_JAL:
+ retAddr = (inst.JType.target << 2) |
+ ((unsigned)(instPC + 4) & 0xF0000000);
+ break;
+
+ case OP_BEQ:
+ case OP_BEQL:
+ if (regsPtr[inst.RType.rs] == regsPtr[inst.RType.rt])
+ retAddr = GetBranchDest(instPC, inst);
+ else
+ retAddr = instPC + 8;
+ break;
+
+ case OP_BNE:
+ case OP_BNEL:
+ if (regsPtr[inst.RType.rs] != regsPtr[inst.RType.rt])
+ retAddr = GetBranchDest(instPC, inst);
+ else
+ retAddr = instPC + 8;
+ break;
+
+ case OP_BLEZ:
+ case OP_BLEZL:
+ if ((int)(regsPtr[inst.RType.rs]) <= 0)
+ retAddr = GetBranchDest(instPC, inst);
+ else
+ retAddr = instPC + 8;
+ break;
+
+ case OP_BGTZ:
+ case OP_BGTZL:
+ if ((int)(regsPtr[inst.RType.rs]) > 0)
+ retAddr = GetBranchDest(instPC, inst);
+ else
+ retAddr = instPC + 8;
+ break;
+
+ case OP_COP1:
+ switch (inst.RType.rs) {
+ case OP_BCx:
+ case OP_BCy:
+ if ((inst.RType.rt & COPz_BC_TF_MASK) == COPz_BC_TRUE)
+ condition = fpcCSR & MIPS_FPU_COND_BIT;
+ else
+ condition = !(fpcCSR & MIPS_FPU_COND_BIT);
+ if (condition)
+ retAddr = GetBranchDest(instPC, inst);
+ else
+ retAddr = instPC + 8;
+ break;
+
+ default:
+ retAddr = instPC + 4;
+ }
+ break;
+
+ default:
+ retAddr = instPC + 4;
+ }
+ return (retAddr);
+}
+
+
+#if defined(DDB) || defined(DEBUG)
+/*
+ * Print a stack backtrace.
+ */
+void
+stacktrace(struct trapframe *regs)
+{
+ stacktrace_subr(regs->pc, regs->sp, regs->ra, printf);
+}
+#endif
+
+static void
+log_frame_dump(struct trapframe *frame)
+{
+ log(LOG_ERR, "Trapframe Register Dump:\n");
+ log(LOG_ERR, "\tzero: %#jx\tat: %#jx\tv0: %#jx\tv1: %#jx\n",
+ (intmax_t)0, (intmax_t)frame->ast, (intmax_t)frame->v0, (intmax_t)frame->v1);
+
+ log(LOG_ERR, "\ta0: %#jx\ta1: %#jx\ta2: %#jx\ta3: %#jx\n",
+ (intmax_t)frame->a0, (intmax_t)frame->a1, (intmax_t)frame->a2, (intmax_t)frame->a3);
+
+#if defined(__mips_n32) || defined(__mips_n64)
+ log(LOG_ERR, "\ta4: %#jx\ta5: %#jx\ta6: %#jx\ta6: %#jx\n",
+ (intmax_t)frame->a4, (intmax_t)frame->a5, (intmax_t)frame->a6, (intmax_t)frame->a7);
+
+ log(LOG_ERR, "\tt0: %#jx\tt1: %#jx\tt2: %#jx\tt3: %#jx\n",
+ (intmax_t)frame->t0, (intmax_t)frame->t1, (intmax_t)frame->t2, (intmax_t)frame->t3);
+#else
+ log(LOG_ERR, "\tt0: %#jx\tt1: %#jx\tt2: %#jx\tt3: %#jx\n",
+ (intmax_t)frame->t0, (intmax_t)frame->t1, (intmax_t)frame->t2, (intmax_t)frame->t3);
+
+ log(LOG_ERR, "\tt4: %#jx\tt5: %#jx\tt6: %#jx\tt7: %#jx\n",
+ (intmax_t)frame->t4, (intmax_t)frame->t5, (intmax_t)frame->t6, (intmax_t)frame->t7);
+#endif
+ log(LOG_ERR, "\tt8: %#jx\tt9: %#jx\ts0: %#jx\ts1: %#jx\n",
+ (intmax_t)frame->t8, (intmax_t)frame->t9, (intmax_t)frame->s0, (intmax_t)frame->s1);
+
+ log(LOG_ERR, "\ts2: %#jx\ts3: %#jx\ts4: %#jx\ts5: %#jx\n",
+ (intmax_t)frame->s2, (intmax_t)frame->s3, (intmax_t)frame->s4, (intmax_t)frame->s5);
+
+ log(LOG_ERR, "\ts6: %#jx\ts7: %#jx\tk0: %#jx\tk1: %#jx\n",
+ (intmax_t)frame->s6, (intmax_t)frame->s7, (intmax_t)frame->k0, (intmax_t)frame->k1);
+
+ log(LOG_ERR, "\tgp: %#jx\tsp: %#jx\ts8: %#jx\tra: %#jx\n",
+ (intmax_t)frame->gp, (intmax_t)frame->sp, (intmax_t)frame->s8, (intmax_t)frame->ra);
+
+ log(LOG_ERR, "\tsr: %#jx\tmullo: %#jx\tmulhi: %#jx\tbadvaddr: %#jx\n",
+ (intmax_t)frame->sr, (intmax_t)frame->mullo, (intmax_t)frame->mulhi, (intmax_t)frame->badvaddr);
+
+#ifdef IC_REG
+ log(LOG_ERR, "\tcause: %#jx\tpc: %#jx\tic: %#jx\n",
+ (intmax_t)frame->cause, (intmax_t)frame->pc, (intmax_t)frame->ic);
+#else
+ log(LOG_ERR, "\tcause: %#jx\tpc: %#jx\n",
+ (intmax_t)frame->cause, (intmax_t)frame->pc);
+#endif
+}
+
+#ifdef TRAP_DEBUG
+static void
+trap_frame_dump(struct trapframe *frame)
+{
+ printf("Trapframe Register Dump:\n");
+ printf("\tzero: %#jx\tat: %#jx\tv0: %#jx\tv1: %#jx\n",
+ (intmax_t)0, (intmax_t)frame->ast, (intmax_t)frame->v0, (intmax_t)frame->v1);
+
+ printf("\ta0: %#jx\ta1: %#jx\ta2: %#jx\ta3: %#jx\n",
+ (intmax_t)frame->a0, (intmax_t)frame->a1, (intmax_t)frame->a2, (intmax_t)frame->a3);
+#if defined(__mips_n32) || defined(__mips_n64)
+ printf("\ta4: %#jx\ta5: %#jx\ta6: %#jx\ta7: %#jx\n",
+ (intmax_t)frame->a4, (intmax_t)frame->a5, (intmax_t)frame->a6, (intmax_t)frame->a7);
+
+ printf("\tt0: %#jx\tt1: %#jx\tt2: %#jx\tt3: %#jx\n",
+ (intmax_t)frame->t0, (intmax_t)frame->t1, (intmax_t)frame->t2, (intmax_t)frame->t3);
+#else
+ printf("\tt0: %#jx\tt1: %#jx\tt2: %#jx\tt3: %#jx\n",
+ (intmax_t)frame->t0, (intmax_t)frame->t1, (intmax_t)frame->t2, (intmax_t)frame->t3);
+
+ printf("\tt4: %#jx\tt5: %#jx\tt6: %#jx\tt7: %#jx\n",
+ (intmax_t)frame->t4, (intmax_t)frame->t5, (intmax_t)frame->t6, (intmax_t)frame->t7);
+#endif
+ printf("\tt8: %#jx\tt9: %#jx\ts0: %#jx\ts1: %#jx\n",
+ (intmax_t)frame->t8, (intmax_t)frame->t9, (intmax_t)frame->s0, (intmax_t)frame->s1);
+
+ printf("\ts2: %#jx\ts3: %#jx\ts4: %#jx\ts5: %#jx\n",
+ (intmax_t)frame->s2, (intmax_t)frame->s3, (intmax_t)frame->s4, (intmax_t)frame->s5);
+
+ printf("\ts6: %#jx\ts7: %#jx\tk0: %#jx\tk1: %#jx\n",
+ (intmax_t)frame->s6, (intmax_t)frame->s7, (intmax_t)frame->k0, (intmax_t)frame->k1);
+
+ printf("\tgp: %#jx\tsp: %#jx\ts8: %#jx\tra: %#jx\n",
+ (intmax_t)frame->gp, (intmax_t)frame->sp, (intmax_t)frame->s8, (intmax_t)frame->ra);
+
+ printf("\tsr: %#jx\tmullo: %#jx\tmulhi: %#jx\tbadvaddr: %#jx\n",
+ (intmax_t)frame->sr, (intmax_t)frame->mullo, (intmax_t)frame->mulhi, (intmax_t)frame->badvaddr);
+
+#ifdef IC_REG
+ printf("\tcause: %#jx\tpc: %#jx\tic: %#jx\n",
+ (intmax_t)frame->cause, (intmax_t)frame->pc, (intmax_t)frame->ic);
+#else
+ printf("\tcause: %#jx\tpc: %#jx\n",
+ (intmax_t)frame->cause, (intmax_t)frame->pc);
+#endif
+}
+
+#endif
+
+
+static void
+get_mapping_info(vm_offset_t va, pd_entry_t **pdepp, pt_entry_t **ptepp)
+{
+ pt_entry_t *ptep;
+ pd_entry_t *pdep;
+ struct proc *p = curproc;
+
+ pdep = (&(p->p_vmspace->vm_pmap.pm_segtab[(va >> SEGSHIFT) & (NPDEPG - 1)]));
+ if (*pdep)
+ ptep = pmap_pte(&p->p_vmspace->vm_pmap, va);
+ else
+ ptep = (pt_entry_t *)0;
+
+ *pdepp = pdep;
+ *ptepp = ptep;
+}
+
+static void
+log_illegal_instruction(const char *msg, struct trapframe *frame)
+{
+ pt_entry_t *ptep;
+ pd_entry_t *pdep;
+ unsigned int *addr;
+ struct thread *td;
+ struct proc *p;
+ register_t pc;
+
+ td = curthread;
+ p = td->td_proc;
+
+#ifdef SMP
+ printf("cpuid = %d\n", PCPU_GET(cpuid));
+#endif
+ pc = frame->pc + (DELAYBRANCH(frame->cause) ? 4 : 0);
+ log(LOG_ERR, "%s: pid %d tid %ld (%s), uid %d: pc %#jx ra %#jx\n",
+ msg, p->p_pid, (long)td->td_tid, p->p_comm,
+ p->p_ucred ? p->p_ucred->cr_uid : -1,
+ (intmax_t)pc,
+ (intmax_t)frame->ra);
+
+ /* log registers in trap frame */
+ log_frame_dump(frame);
+
+ get_mapping_info((vm_offset_t)pc, &pdep, &ptep);
+
+ /*
+ * Dump a few words around faulting instruction, if the addres is
+ * valid.
+ */
+ if (!(pc & 3) &&
+ useracc((caddr_t)(intptr_t)pc, sizeof(int) * 4, VM_PROT_READ)) {
+ /* dump page table entry for faulting instruction */
+ log(LOG_ERR, "Page table info for pc address %#jx: pde = %p, pte = %#jx\n",
+ (intmax_t)pc, (void *)(intptr_t)*pdep, (uintmax_t)(ptep ? *ptep : 0));
+
+ addr = (unsigned int *)(intptr_t)pc;
+ log(LOG_ERR, "Dumping 4 words starting at pc address %p: \n",
+ addr);
+ log(LOG_ERR, "%08x %08x %08x %08x\n",
+ addr[0], addr[1], addr[2], addr[3]);
+ } else {
+ log(LOG_ERR, "pc address %#jx is inaccessible, pde = %p, pte = %#jx\n",
+ (intmax_t)pc, (void *)(intptr_t)*pdep, (uintmax_t)(ptep ? *ptep : 0));
+ }
+}
+
+static void
+log_bad_page_fault(char *msg, struct trapframe *frame, int trap_type)
+{
+ pt_entry_t *ptep;
+ pd_entry_t *pdep;
+ unsigned int *addr;
+ struct thread *td;
+ struct proc *p;
+ char *read_or_write;
+ register_t pc;
+
+ trap_type &= ~T_USER;
+
+ td = curthread;
+ p = td->td_proc;
+
+#ifdef SMP
+ printf("cpuid = %d\n", PCPU_GET(cpuid));
+#endif
+ switch (trap_type) {
+ case T_TLB_MOD:
+ case T_TLB_ST_MISS:
+ case T_ADDR_ERR_ST:
+ read_or_write = "write";
+ break;
+ case T_TLB_LD_MISS:
+ case T_ADDR_ERR_LD:
+ case T_BUS_ERR_IFETCH:
+ read_or_write = "read";
+ break;
+ default:
+ read_or_write = "unknown";
+ }
+
+ pc = frame->pc + (DELAYBRANCH(frame->cause) ? 4 : 0);
+ log(LOG_ERR, "%s: pid %d tid %ld (%s), uid %d: pc %#jx got a %s fault "
+ "(type %#x) at %#jx\n",
+ msg, p->p_pid, (long)td->td_tid, p->p_comm,
+ p->p_ucred ? p->p_ucred->cr_uid : -1,
+ (intmax_t)pc,
+ read_or_write,
+ trap_type,
+ (intmax_t)frame->badvaddr);
+
+ /* log registers in trap frame */
+ log_frame_dump(frame);
+
+ get_mapping_info((vm_offset_t)pc, &pdep, &ptep);
+
+ /*
+ * Dump a few words around faulting instruction, if the addres is
+ * valid.
+ */
+ if (!(pc & 3) && (pc != frame->badvaddr) &&
+ (trap_type != T_BUS_ERR_IFETCH) &&
+ useracc((caddr_t)(intptr_t)pc, sizeof(int) * 4, VM_PROT_READ)) {
+ /* dump page table entry for faulting instruction */
+ log(LOG_ERR, "Page table info for pc address %#jx: pde = %p, pte = %#jx\n",
+ (intmax_t)pc, (void *)(intptr_t)*pdep, (uintmax_t)(ptep ? *ptep : 0));
+
+ addr = (unsigned int *)(intptr_t)pc;
+ log(LOG_ERR, "Dumping 4 words starting at pc address %p: \n",
+ addr);
+ log(LOG_ERR, "%08x %08x %08x %08x\n",
+ addr[0], addr[1], addr[2], addr[3]);
+ } else {
+ log(LOG_ERR, "pc address %#jx is inaccessible, pde = %p, pte = %#jx\n",
+ (intmax_t)pc, (void *)(intptr_t)*pdep, (uintmax_t)(ptep ? *ptep : 0));
+ }
+
+ get_mapping_info((vm_offset_t)frame->badvaddr, &pdep, &ptep);
+ log(LOG_ERR, "Page table info for bad address %#jx: pde = %p, pte = %#jx\n",
+ (intmax_t)frame->badvaddr, (void *)(intptr_t)*pdep, (uintmax_t)(ptep ? *ptep : 0));
+}
+
+
+/*
+ * Unaligned load/store emulation
+ */
+static int
+mips_unaligned_load_store(struct trapframe *frame, int mode, register_t addr, register_t pc)
+{
+ register_t *reg = (register_t *) frame;
+ u_int32_t inst = *((u_int32_t *)(intptr_t)pc);
+ register_t value_msb, value;
+ unsigned size;
+
+ /*
+ * ADDR_ERR faults have higher priority than TLB
+ * Miss faults. Therefore, it is necessary to
+ * verify that the faulting address is a valid
+ * virtual address within the process' address space
+ * before trying to emulate the unaligned access.
+ */
+ switch (MIPS_INST_OPCODE(inst)) {
+ case OP_LHU: case OP_LH:
+ case OP_SH:
+ size = 2;
+ break;
+ case OP_LWU: case OP_LW:
+ case OP_SW:
+ size = 4;
+ break;
+ case OP_LD:
+ case OP_SD:
+ size = 8;
+ break;
+ default:
+ printf("%s: unhandled opcode in address error: %#x\n", __func__, MIPS_INST_OPCODE(inst));
+ return (0);
+ }
+
+ if (!useracc((void *)((vm_offset_t)addr & ~(size - 1)), size * 2, mode))
+ return (0);
+
+ /*
+ * XXX
+ * Handle LL/SC LLD/SCD.
+ */
+ switch (MIPS_INST_OPCODE(inst)) {
+ case OP_LHU:
+ KASSERT(mode == VM_PROT_READ, ("access mode must be read for load instruction."));
+ lbu_macro(value_msb, addr);
+ addr += 1;
+ lbu_macro(value, addr);
+ value |= value_msb << 8;
+ reg[MIPS_INST_RT(inst)] = value;
+ return (MIPS_LHU_ACCESS);
+
+ case OP_LH:
+ KASSERT(mode == VM_PROT_READ, ("access mode must be read for load instruction."));
+ lb_macro(value_msb, addr);
+ addr += 1;
+ lbu_macro(value, addr);
+ value |= value_msb << 8;
+ reg[MIPS_INST_RT(inst)] = value;
+ return (MIPS_LH_ACCESS);
+
+ case OP_LWU:
+ KASSERT(mode == VM_PROT_READ, ("access mode must be read for load instruction."));
+ lwl_macro(value, addr);
+ addr += 3;
+ lwr_macro(value, addr);
+ value &= 0xffffffff;
+ reg[MIPS_INST_RT(inst)] = value;
+ return (MIPS_LWU_ACCESS);
+
+ case OP_LW:
+ KASSERT(mode == VM_PROT_READ, ("access mode must be read for load instruction."));
+ lwl_macro(value, addr);
+ addr += 3;
+ lwr_macro(value, addr);
+ reg[MIPS_INST_RT(inst)] = value;
+ return (MIPS_LW_ACCESS);
+
+#if defined(__mips_n32) || defined(__mips_n64)
+ case OP_LD:
+ KASSERT(mode == VM_PROT_READ, ("access mode must be read for load instruction."));
+ ldl_macro(value, addr);
+ addr += 7;
+ ldr_macro(value, addr);
+ reg[MIPS_INST_RT(inst)] = value;
+ return (MIPS_LD_ACCESS);
+#endif
+
+ case OP_SH:
+ KASSERT(mode == VM_PROT_WRITE, ("access mode must be write for store instruction."));
+ value = reg[MIPS_INST_RT(inst)];
+ value_msb = value >> 8;
+ sb_macro(value_msb, addr);
+ addr += 1;
+ sb_macro(value, addr);
+ return (MIPS_SH_ACCESS);
+
+ case OP_SW:
+ KASSERT(mode == VM_PROT_WRITE, ("access mode must be write for store instruction."));
+ value = reg[MIPS_INST_RT(inst)];
+ swl_macro(value, addr);
+ addr += 3;
+ swr_macro(value, addr);
+ return (MIPS_SW_ACCESS);
+
+#if defined(__mips_n32) || defined(__mips_n64)
+ case OP_SD:
+ KASSERT(mode == VM_PROT_WRITE, ("access mode must be write for store instruction."));
+ value = reg[MIPS_INST_RT(inst)];
+ sdl_macro(value, addr);
+ addr += 7;
+ sdr_macro(value, addr);
+ return (MIPS_SD_ACCESS);
+#endif
+ }
+ panic("%s: should not be reached.", __func__);
+}
+
+
+static int
+emulate_unaligned_access(struct trapframe *frame, int mode)
+{
+ register_t pc;
+ int access_type = 0;
+
+ pc = frame->pc + (DELAYBRANCH(frame->cause) ? 4 : 0);
+
+ /*
+ * Fall through if it's instruction fetch exception
+ */
+ if (!((pc & 3) || (pc == frame->badvaddr))) {
+
+ /*
+ * Handle unaligned load and store
+ */
+
+ /*
+ * Return access type if the instruction was emulated.
+ * Otherwise restore pc and fall through.
+ */
+ access_type = mips_unaligned_load_store(frame,
+ mode, frame->badvaddr, pc);
+
+ if (access_type) {
+ if (DELAYBRANCH(frame->cause))
+ frame->pc = MipsEmulateBranch(frame, frame->pc,
+ 0, 0);
+ else
+ frame->pc += 4;
+
+ log(LOG_INFO, "Unaligned %s: pc=%#jx, badvaddr=%#jx\n",
+ access_name[access_type - 1], (intmax_t)pc,
+ (intmax_t)frame->badvaddr);
+ }
+ }
+ return access_type;
+}
Property changes on: trunk/sys/mips/mips/trap.c
___________________________________________________________________
Added: svn:eol-style
## -0,0 +1 ##
+native
\ No newline at end of property
Added: svn:keywords
## -0,0 +1 ##
+MidnightBSD=%H
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## -0,0 +1 ##
+text/plain
\ No newline at end of property
Added: trunk/sys/mips/mips/uio_machdep.c
===================================================================
--- trunk/sys/mips/mips/uio_machdep.c (rev 0)
+++ trunk/sys/mips/mips/uio_machdep.c 2018-05-26 21:55:02 UTC (rev 9987)
@@ -0,0 +1,146 @@
+/* $MidnightBSD$ */
+/*-
+ * Copyright (c) 2004 Alan L. Cox <alc at cs.rice.edu>
+ * Copyright (c) 1982, 1986, 1991, 1993
+ * The Regents of the University of California. All rights reserved.
+ * (c) UNIX System Laboratories, Inc.
+ * All or some portions of this file are derived from material licensed
+ * to the University of California by American Telephone and Telegraph
+ * Co. or Unix System Laboratories, Inc. and are reproduced herein with
+ * the permission of UNIX System Laboratories, Inc.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * 3. Neither the name of the University nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ * @(#)kern_subr.c 8.3 (Berkeley) 1/21/94
+ */
+
+#include <sys/cdefs.h>
+__FBSDID("$FreeBSD: stable/10/sys/mips/mips/uio_machdep.c 266312 2014-05-17 13:59:11Z ian $");
+
+#include <sys/param.h>
+#include <sys/systm.h>
+#include <sys/kernel.h>
+#include <sys/lock.h>
+#include <sys/mutex.h>
+#include <sys/proc.h>
+#include <sys/sf_buf.h>
+#include <sys/uio.h>
+
+#include <vm/vm.h>
+#include <vm/vm_page.h>
+#include <vm/vm_param.h>
+
+#include <machine/cache.h>
+
+/*
+ * Implement uiomove(9) from physical memory using a combination
+ * of the direct mapping and sf_bufs to reduce the creation and
+ * destruction of ephemeral mappings.
+ */
+int
+uiomove_fromphys(vm_page_t ma[], vm_offset_t offset, int n, struct uio *uio)
+{
+ struct sf_buf *sf;
+ struct thread *td = curthread;
+ struct iovec *iov;
+ void *cp;
+ vm_offset_t page_offset;
+ vm_paddr_t pa;
+ vm_page_t m;
+ size_t cnt;
+ int error = 0;
+ int save = 0;
+
+ KASSERT(uio->uio_rw == UIO_READ || uio->uio_rw == UIO_WRITE,
+ ("uiomove_fromphys: mode"));
+ KASSERT(uio->uio_segflg != UIO_USERSPACE || uio->uio_td == curthread,
+ ("uiomove_fromphys proc"));
+ save = td->td_pflags & TDP_DEADLKTREAT;
+ td->td_pflags |= TDP_DEADLKTREAT;
+ while (n > 0 && uio->uio_resid) {
+ iov = uio->uio_iov;
+ cnt = iov->iov_len;
+ if (cnt == 0) {
+ uio->uio_iov++;
+ uio->uio_iovcnt--;
+ continue;
+ }
+ if (cnt > n)
+ cnt = n;
+ page_offset = offset & PAGE_MASK;
+ cnt = ulmin(cnt, PAGE_SIZE - page_offset);
+ m = ma[offset >> PAGE_SHIFT];
+ pa = VM_PAGE_TO_PHYS(m);
+ if (MIPS_DIRECT_MAPPABLE(pa)) {
+ sf = NULL;
+ cp = (char *)MIPS_PHYS_TO_DIRECT(pa) + page_offset;
+ /*
+ * flush all mappings to this page, KSEG0 address first
+ * in order to get it overwritten by correct data
+ */
+ mips_dcache_wbinv_range((vm_offset_t)cp, cnt);
+ pmap_flush_pvcache(m);
+ } else {
+ sf = sf_buf_alloc(m, 0);
+ cp = (char *)sf_buf_kva(sf) + page_offset;
+ }
+ switch (uio->uio_segflg) {
+ case UIO_USERSPACE:
+ maybe_yield();
+ if (uio->uio_rw == UIO_READ)
+ error = copyout(cp, iov->iov_base, cnt);
+ else
+ error = copyin(iov->iov_base, cp, cnt);
+ if (error) {
+ if (sf != NULL)
+ sf_buf_free(sf);
+ goto out;
+ }
+ break;
+ case UIO_SYSSPACE:
+ if (uio->uio_rw == UIO_READ)
+ bcopy(cp, iov->iov_base, cnt);
+ else
+ bcopy(iov->iov_base, cp, cnt);
+ break;
+ case UIO_NOCOPY:
+ break;
+ }
+ if (sf != NULL)
+ sf_buf_free(sf);
+ else
+ mips_dcache_wbinv_range((vm_offset_t)cp, cnt);
+ iov->iov_base = (char *)iov->iov_base + cnt;
+ iov->iov_len -= cnt;
+ uio->uio_resid -= cnt;
+ uio->uio_offset += cnt;
+ offset += cnt;
+ n -= cnt;
+ }
+out:
+ if (save == 0)
+ td->td_pflags &= ~TDP_DEADLKTREAT;
+ return (error);
+}
Property changes on: trunk/sys/mips/mips/uio_machdep.c
___________________________________________________________________
Added: svn:eol-style
## -0,0 +1 ##
+native
\ No newline at end of property
Added: svn:keywords
## -0,0 +1 ##
+MidnightBSD=%H
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+text/plain
\ No newline at end of property
Added: trunk/sys/mips/mips/uma_machdep.c
===================================================================
--- trunk/sys/mips/mips/uma_machdep.c (rev 0)
+++ trunk/sys/mips/mips/uma_machdep.c 2018-05-26 21:55:02 UTC (rev 9987)
@@ -0,0 +1,84 @@
+/* $MidnightBSD$ */
+/*-
+ * Copyright (c) 2003 Alan L. Cox <alc at cs.rice.edu>
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ */
+
+#include <sys/cdefs.h>
+__FBSDID("$FreeBSD: stable/10/sys/mips/mips/uma_machdep.c 287945 2015-09-17 23:31:44Z rstone $");
+
+#include <sys/param.h>
+#include <sys/lock.h>
+#include <sys/malloc.h>
+#include <sys/mutex.h>
+#include <sys/systm.h>
+#include <vm/vm.h>
+#include <vm/vm_page.h>
+#include <vm/vm_pageout.h>
+#include <vm/uma.h>
+#include <vm/uma_int.h>
+#include <machine/md_var.h>
+#include <machine/vmparam.h>
+
+void *
+uma_small_alloc(uma_zone_t zone, vm_size_t bytes, u_int8_t *flags, int wait)
+{
+ vm_paddr_t pa;
+ vm_page_t m;
+ int pflags;
+ void *va;
+
+ *flags = UMA_SLAB_PRIV;
+ pflags = malloc2vm_flags(wait) | VM_ALLOC_WIRED;
+
+ for (;;) {
+ m = vm_page_alloc_freelist(VM_FREELIST_DIRECT, pflags);
+ if (m == NULL) {
+ if (wait & M_NOWAIT)
+ return (NULL);
+ else
+ pmap_grow_direct_page_cache();
+ } else
+ break;
+ }
+
+ pa = VM_PAGE_TO_PHYS(m);
+ va = (void *)MIPS_PHYS_TO_DIRECT(pa);
+ if ((wait & M_ZERO) && (m->flags & PG_ZERO) == 0)
+ bzero(va, PAGE_SIZE);
+ return (va);
+}
+
+void
+uma_small_free(void *mem, vm_size_t size, u_int8_t flags)
+{
+ vm_page_t m;
+ vm_paddr_t pa;
+
+ pa = MIPS_DIRECT_TO_PHYS((vm_offset_t)mem);
+ m = PHYS_TO_VM_PAGE(pa);
+ m->wire_count--;
+ vm_page_free(m);
+ atomic_subtract_int(&cnt.v_wire_count, 1);
+}
Property changes on: trunk/sys/mips/mips/uma_machdep.c
___________________________________________________________________
Added: svn:eol-style
## -0,0 +1 ##
+native
\ No newline at end of property
Added: svn:keywords
## -0,0 +1 ##
+MidnightBSD=%H
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+text/plain
\ No newline at end of property
Added: trunk/sys/mips/mips/vm_machdep.c
===================================================================
--- trunk/sys/mips/mips/vm_machdep.c (rev 0)
+++ trunk/sys/mips/mips/vm_machdep.c 2018-05-26 21:55:02 UTC (rev 9987)
@@ -0,0 +1,739 @@
+/* $MidnightBSD$ */
+/*-
+ * Copyright (c) 1982, 1986 The Regents of the University of California.
+ * Copyright (c) 1989, 1990 William Jolitz
+ * Copyright (c) 1994 John Dyson
+ * All rights reserved.
+ *
+ * This code is derived from software contributed to Berkeley by
+ * the Systems Programming Group of the University of Utah Computer
+ * Science Department, and William Jolitz.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * 4. Neither the name of the University nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ * from: @(#)vm_machdep.c 7.3 (Berkeley) 5/13/91
+ * Utah $Hdr: vm_machdep.c 1.16.1.1 89/06/23$
+ * from: src/sys/i386/i386/vm_machdep.c,v 1.132.2.2 2000/08/26 04:19:26 yokota
+ * JNPR: vm_machdep.c,v 1.8.2.2 2007/08/16 15:59:17 girish
+ */
+
+#include <sys/cdefs.h>
+__FBSDID("$FreeBSD: stable/10/sys/mips/mips/vm_machdep.c 255786 2013-09-22 13:36:52Z glebius $");
+
+#include "opt_compat.h"
+#include "opt_ddb.h"
+
+#include <sys/param.h>
+#include <sys/systm.h>
+#include <sys/malloc.h>
+#include <sys/proc.h>
+#include <sys/syscall.h>
+#include <sys/sysent.h>
+#include <sys/buf.h>
+#include <sys/vnode.h>
+#include <sys/vmmeter.h>
+#include <sys/kernel.h>
+#include <sys/sysctl.h>
+#include <sys/unistd.h>
+
+#include <machine/cache.h>
+#include <machine/clock.h>
+#include <machine/cpu.h>
+#include <machine/md_var.h>
+#include <machine/pcb.h>
+
+#include <vm/vm.h>
+#include <vm/vm_extern.h>
+#include <vm/pmap.h>
+#include <vm/vm_kern.h>
+#include <vm/vm_map.h>
+#include <vm/vm_page.h>
+#include <vm/vm_pageout.h>
+#include <vm/vm_param.h>
+#include <vm/uma.h>
+#include <vm/uma_int.h>
+
+#include <sys/user.h>
+#include <sys/mbuf.h>
+#ifndef __mips_n64
+#include <sys/sf_buf.h>
+#endif
+
+/* Duplicated from asm.h */
+#if defined(__mips_o32)
+#define SZREG 4
+#else
+#define SZREG 8
+#endif
+#if defined(__mips_o32) || defined(__mips_o64)
+#define CALLFRAME_SIZ (SZREG * (4 + 2))
+#elif defined(__mips_n32) || defined(__mips_n64)
+#define CALLFRAME_SIZ (SZREG * 4)
+#endif
+
+#ifndef __mips_n64
+
+#ifndef NSFBUFS
+#define NSFBUFS (512 + maxusers * 16)
+#endif
+
+static int nsfbufs;
+static int nsfbufspeak;
+static int nsfbufsused;
+
+SYSCTL_INT(_kern_ipc, OID_AUTO, nsfbufs, CTLFLAG_RDTUN, &nsfbufs, 0,
+ "Maximum number of sendfile(2) sf_bufs available");
+SYSCTL_INT(_kern_ipc, OID_AUTO, nsfbufspeak, CTLFLAG_RD, &nsfbufspeak, 0,
+ "Number of sendfile(2) sf_bufs at peak usage");
+SYSCTL_INT(_kern_ipc, OID_AUTO, nsfbufsused, CTLFLAG_RD, &nsfbufsused, 0,
+ "Number of sendfile(2) sf_bufs in use");
+
+static void sf_buf_init(void *arg);
+SYSINIT(sock_sf, SI_SUB_MBUF, SI_ORDER_ANY, sf_buf_init, NULL);
+
+/*
+ * Expanded sf_freelist head. Really an SLIST_HEAD() in disguise, with the
+ * sf_freelist head with the sf_lock mutex.
+ */
+static struct {
+ SLIST_HEAD(, sf_buf) sf_head;
+ struct mtx sf_lock;
+} sf_freelist;
+
+static u_int sf_buf_alloc_want;
+#endif /* !__mips_n64 */
+
+/*
+ * Finish a fork operation, with process p2 nearly set up.
+ * Copy and update the pcb, set up the stack so that the child
+ * ready to run and return to user mode.
+ */
+void
+cpu_fork(register struct thread *td1,register struct proc *p2,
+ struct thread *td2,int flags)
+{
+ register struct proc *p1;
+ struct pcb *pcb2;
+
+ p1 = td1->td_proc;
+ if ((flags & RFPROC) == 0)
+ return;
+ /* It is assumed that the vm_thread_alloc called
+ * cpu_thread_alloc() before cpu_fork is called.
+ */
+
+ /* Point the pcb to the top of the stack */
+ pcb2 = td2->td_pcb;
+
+ /* Copy p1's pcb, note that in this case
+ * our pcb also includes the td_frame being copied
+ * too. The older mips2 code did an additional copy
+ * of the td_frame, for us that's not needed any
+ * longer (this copy does them both)
+ */
+ bcopy(td1->td_pcb, pcb2, sizeof(*pcb2));
+
+ /* Point mdproc and then copy over td1's contents
+ * md_proc is empty for MIPS
+ */
+ td2->td_md.md_flags = td1->td_md.md_flags & MDTD_FPUSED;
+
+ /*
+ * Set up return-value registers as fork() libc stub expects.
+ */
+ td2->td_frame->v0 = 0;
+ td2->td_frame->v1 = 1;
+ td2->td_frame->a3 = 0;
+
+ if (td1 == PCPU_GET(fpcurthread))
+ MipsSaveCurFPState(td1);
+
+ pcb2->pcb_context[PCB_REG_RA] = (register_t)(intptr_t)fork_trampoline;
+ /* Make sp 64-bit aligned */
+ pcb2->pcb_context[PCB_REG_SP] = (register_t)(((vm_offset_t)td2->td_pcb &
+ ~(sizeof(__int64_t) - 1)) - CALLFRAME_SIZ);
+ pcb2->pcb_context[PCB_REG_S0] = (register_t)(intptr_t)fork_return;
+ pcb2->pcb_context[PCB_REG_S1] = (register_t)(intptr_t)td2;
+ pcb2->pcb_context[PCB_REG_S2] = (register_t)(intptr_t)td2->td_frame;
+ pcb2->pcb_context[PCB_REG_SR] = mips_rd_status() &
+ (MIPS_SR_KX | MIPS_SR_UX | MIPS_SR_INT_MASK);
+ /*
+ * FREEBSD_DEVELOPERS_FIXME:
+ * Setup any other CPU-Specific registers (Not MIPS Standard)
+ * and/or bits in other standard MIPS registers (if CPU-Specific)
+ * that are needed.
+ */
+
+ td2->td_md.md_tls = td1->td_md.md_tls;
+ td2->td_md.md_saved_intr = MIPS_SR_INT_IE;
+ td2->td_md.md_spinlock_count = 1;
+#ifdef CPU_CNMIPS
+ if (td1->td_md.md_flags & MDTD_COP2USED) {
+ if (td1->td_md.md_cop2owner == COP2_OWNER_USERLAND) {
+ if (td1->td_md.md_ucop2)
+ octeon_cop2_save(td1->td_md.md_ucop2);
+ else
+ panic("cpu_fork: ucop2 is NULL but COP2 is enabled");
+ }
+ else {
+ if (td1->td_md.md_cop2)
+ octeon_cop2_save(td1->td_md.md_cop2);
+ else
+ panic("cpu_fork: cop2 is NULL but COP2 is enabled");
+ }
+ }
+
+ if (td1->td_md.md_cop2) {
+ td2->td_md.md_cop2 = octeon_cop2_alloc_ctx();
+ memcpy(td2->td_md.md_cop2, td1->td_md.md_cop2,
+ sizeof(*td1->td_md.md_cop2));
+ }
+ if (td1->td_md.md_ucop2) {
+ td2->td_md.md_ucop2 = octeon_cop2_alloc_ctx();
+ memcpy(td2->td_md.md_ucop2, td1->td_md.md_ucop2,
+ sizeof(*td1->td_md.md_ucop2));
+ }
+ td2->td_md.md_cop2owner = td1->td_md.md_cop2owner;
+ pcb2->pcb_context[PCB_REG_SR] |= MIPS_SR_PX | MIPS_SR_UX | MIPS_SR_KX | MIPS_SR_SX;
+ /* Clear COP2 bits for userland & kernel */
+ td2->td_frame->sr &= ~MIPS_SR_COP_2_BIT;
+ pcb2->pcb_context[PCB_REG_SR] &= ~MIPS_SR_COP_2_BIT;
+#endif
+}
+
+/*
+ * Intercept the return address from a freshly forked process that has NOT
+ * been scheduled yet.
+ *
+ * This is needed to make kernel threads stay in kernel mode.
+ */
+void
+cpu_set_fork_handler(struct thread *td, void (*func) __P((void *)), void *arg)
+{
+ /*
+ * Note that the trap frame follows the args, so the function
+ * is really called like this: func(arg, frame);
+ */
+ td->td_pcb->pcb_context[PCB_REG_S0] = (register_t)(intptr_t)func;
+ td->td_pcb->pcb_context[PCB_REG_S1] = (register_t)(intptr_t)arg;
+}
+
+void
+cpu_exit(struct thread *td)
+{
+}
+
+void
+cpu_thread_exit(struct thread *td)
+{
+
+ if (PCPU_GET(fpcurthread) == td)
+ PCPU_GET(fpcurthread) = (struct thread *)0;
+#ifdef CPU_CNMIPS
+ if (td->td_md.md_cop2)
+ memset(td->td_md.md_cop2, 0,
+ sizeof(*td->td_md.md_cop2));
+ if (td->td_md.md_ucop2)
+ memset(td->td_md.md_ucop2, 0,
+ sizeof(*td->td_md.md_ucop2));
+#endif
+}
+
+void
+cpu_thread_free(struct thread *td)
+{
+#ifdef CPU_CNMIPS
+ if (td->td_md.md_cop2)
+ octeon_cop2_free_ctx(td->td_md.md_cop2);
+ if (td->td_md.md_ucop2)
+ octeon_cop2_free_ctx(td->td_md.md_ucop2);
+ td->td_md.md_cop2 = NULL;
+ td->td_md.md_ucop2 = NULL;
+#endif
+}
+
+void
+cpu_thread_clean(struct thread *td)
+{
+}
+
+void
+cpu_thread_swapin(struct thread *td)
+{
+ pt_entry_t *pte;
+ int i;
+
+ /*
+ * The kstack may be at a different physical address now.
+ * Cache the PTEs for the Kernel stack in the machine dependent
+ * part of the thread struct so cpu_switch() can quickly map in
+ * the pcb struct and kernel stack.
+ */
+ for (i = 0; i < KSTACK_PAGES; i++) {
+ pte = pmap_pte(kernel_pmap, td->td_kstack + i * PAGE_SIZE);
+ td->td_md.md_upte[i] = *pte & ~TLBLO_SWBITS_MASK;
+ }
+}
+
+void
+cpu_thread_swapout(struct thread *td)
+{
+}
+
+void
+cpu_thread_alloc(struct thread *td)
+{
+ pt_entry_t *pte;
+ int i;
+
+ KASSERT((td->td_kstack & (1 << PAGE_SHIFT)) == 0, ("kernel stack must be aligned."));
+ td->td_pcb = (struct pcb *)(td->td_kstack +
+ td->td_kstack_pages * PAGE_SIZE) - 1;
+ td->td_frame = &td->td_pcb->pcb_regs;
+
+ for (i = 0; i < KSTACK_PAGES; i++) {
+ pte = pmap_pte(kernel_pmap, td->td_kstack + i * PAGE_SIZE);
+ td->td_md.md_upte[i] = *pte & ~TLBLO_SWBITS_MASK;
+ }
+}
+
+void
+cpu_set_syscall_retval(struct thread *td, int error)
+{
+ struct trapframe *locr0 = td->td_frame;
+ unsigned int code;
+ int quad_syscall;
+
+ code = locr0->v0;
+ quad_syscall = 0;
+#if defined(__mips_n32) || defined(__mips_n64)
+#ifdef COMPAT_FREEBSD32
+ if (code == SYS___syscall && SV_PROC_FLAG(td->td_proc, SV_ILP32))
+ quad_syscall = 1;
+#endif
+#else
+ if (code == SYS___syscall)
+ quad_syscall = 1;
+#endif
+
+ if (code == SYS_syscall)
+ code = locr0->a0;
+ else if (code == SYS___syscall) {
+ if (quad_syscall)
+ code = _QUAD_LOWWORD ? locr0->a1 : locr0->a0;
+ else
+ code = locr0->a0;
+ }
+
+ switch (error) {
+ case 0:
+ if (quad_syscall && code != SYS_lseek) {
+ /*
+ * System call invoked through the
+ * SYS___syscall interface but the
+ * return value is really just 32
+ * bits.
+ */
+ locr0->v0 = td->td_retval[0];
+ if (_QUAD_LOWWORD)
+ locr0->v1 = td->td_retval[0];
+ locr0->a3 = 0;
+ } else {
+ locr0->v0 = td->td_retval[0];
+ locr0->v1 = td->td_retval[1];
+ locr0->a3 = 0;
+ }
+ break;
+
+ case ERESTART:
+ locr0->pc = td->td_pcb->pcb_tpc;
+ break;
+
+ case EJUSTRETURN:
+ break; /* nothing to do */
+
+ default:
+ if (quad_syscall && code != SYS_lseek) {
+ locr0->v0 = error;
+ if (_QUAD_LOWWORD)
+ locr0->v1 = error;
+ locr0->a3 = 1;
+ } else {
+ locr0->v0 = error;
+ locr0->a3 = 1;
+ }
+ }
+}
+
+/*
+ * Initialize machine state (pcb and trap frame) for a new thread about to
+ * upcall. Put enough state in the new thread's PCB to get it to go back
+ * userret(), where we can intercept it again to set the return (upcall)
+ * Address and stack, along with those from upcalls that are from other sources
+ * such as those generated in thread_userret() itself.
+ */
+void
+cpu_set_upcall(struct thread *td, struct thread *td0)
+{
+ struct pcb *pcb2;
+
+ /* Point the pcb to the top of the stack. */
+ pcb2 = td->td_pcb;
+
+ /*
+ * Copy the upcall pcb. This loads kernel regs.
+ * Those not loaded individually below get their default
+ * values here.
+ *
+ * XXXKSE It might be a good idea to simply skip this as
+ * the values of the other registers may be unimportant.
+ * This would remove any requirement for knowing the KSE
+ * at this time (see the matching comment below for
+ * more analysis) (need a good safe default).
+ * In MIPS, the trapframe is the first element of the PCB
+ * and gets copied when we copy the PCB. No separate copy
+ * is needed.
+ */
+ bcopy(td0->td_pcb, pcb2, sizeof(*pcb2));
+
+ /*
+ * Set registers for trampoline to user mode.
+ */
+
+ pcb2->pcb_context[PCB_REG_RA] = (register_t)(intptr_t)fork_trampoline;
+ /* Make sp 64-bit aligned */
+ pcb2->pcb_context[PCB_REG_SP] = (register_t)(((vm_offset_t)td->td_pcb &
+ ~(sizeof(__int64_t) - 1)) - CALLFRAME_SIZ);
+ pcb2->pcb_context[PCB_REG_S0] = (register_t)(intptr_t)fork_return;
+ pcb2->pcb_context[PCB_REG_S1] = (register_t)(intptr_t)td;
+ pcb2->pcb_context[PCB_REG_S2] = (register_t)(intptr_t)td->td_frame;
+ /* Dont set IE bit in SR. sched lock release will take care of it */
+ pcb2->pcb_context[PCB_REG_SR] = mips_rd_status() &
+ (MIPS_SR_PX | MIPS_SR_KX | MIPS_SR_UX | MIPS_SR_INT_MASK);
+
+ /*
+ * FREEBSD_DEVELOPERS_FIXME:
+ * Setup any other CPU-Specific registers (Not MIPS Standard)
+ * that are needed.
+ */
+
+ /* SMP Setup to release sched_lock in fork_exit(). */
+ td->td_md.md_spinlock_count = 1;
+ td->td_md.md_saved_intr = MIPS_SR_INT_IE;
+#if 0
+ /* Maybe we need to fix this? */
+ td->td_md.md_saved_sr = ( (MIPS_SR_COP_2_BIT | MIPS_SR_COP_0_BIT) |
+ (MIPS_SR_PX | MIPS_SR_UX | MIPS_SR_KX | MIPS_SR_SX) |
+ (MIPS_SR_INT_IE | MIPS_HARD_INT_MASK));
+#endif
+}
+
+/*
+ * Set that machine state for performing an upcall that has to
+ * be done in thread_userret() so that those upcalls generated
+ * in thread_userret() itself can be done as well.
+ */
+void
+cpu_set_upcall_kse(struct thread *td, void (*entry)(void *), void *arg,
+ stack_t *stack)
+{
+ struct trapframe *tf;
+ register_t sp;
+
+ /*
+ * At the point where a function is called, sp must be 8
+ * byte aligned[for compatibility with 64-bit CPUs]
+ * in ``See MIPS Run'' by D. Sweetman, p. 269
+ * align stack
+ */
+ sp = ((register_t)(intptr_t)(stack->ss_sp + stack->ss_size) & ~0x7) -
+ CALLFRAME_SIZ;
+
+ /*
+ * Set the trap frame to point at the beginning of the uts
+ * function.
+ */
+ tf = td->td_frame;
+ bzero(tf, sizeof(struct trapframe));
+ tf->sp = sp;
+ tf->pc = (register_t)(intptr_t)entry;
+ /*
+ * MIPS ABI requires T9 to be the same as PC
+ * in subroutine entry point
+ */
+ tf->t9 = (register_t)(intptr_t)entry;
+ tf->a0 = (register_t)(intptr_t)arg;
+
+ /*
+ * Keep interrupt mask
+ */
+ td->td_frame->sr = MIPS_SR_KSU_USER | MIPS_SR_EXL | MIPS_SR_INT_IE |
+ (mips_rd_status() & MIPS_SR_INT_MASK);
+#if defined(__mips_n32)
+ td->td_frame->sr |= MIPS_SR_PX;
+#elif defined(__mips_n64)
+ td->td_frame->sr |= MIPS_SR_PX | MIPS_SR_UX | MIPS_SR_KX;
+#endif
+/* tf->sr |= (ALL_INT_MASK & idle_mask) | SR_INT_ENAB; */
+ /**XXX the above may now be wrong -- mips2 implements this as panic */
+ /*
+ * FREEBSD_DEVELOPERS_FIXME:
+ * Setup any other CPU-Specific registers (Not MIPS Standard)
+ * that are needed.
+ */
+}
+
+/*
+ * Implement the pre-zeroed page mechanism.
+ * This routine is called from the idle loop.
+ */
+
+#define ZIDLE_LO(v) ((v) * 2 / 3)
+#define ZIDLE_HI(v) ((v) * 4 / 5)
+
+/*
+ * Allocate a pool of sf_bufs (sendfile(2) or "super-fast" if you prefer. :-))
+ */
+#ifndef __mips_n64
+static void
+sf_buf_init(void *arg)
+{
+ struct sf_buf *sf_bufs;
+ vm_offset_t sf_base;
+ int i;
+
+ nsfbufs = NSFBUFS;
+ TUNABLE_INT_FETCH("kern.ipc.nsfbufs", &nsfbufs);
+
+ mtx_init(&sf_freelist.sf_lock, "sf_bufs list lock", NULL, MTX_DEF);
+ SLIST_INIT(&sf_freelist.sf_head);
+ sf_base = kva_alloc(nsfbufs * PAGE_SIZE);
+ sf_bufs = malloc(nsfbufs * sizeof(struct sf_buf), M_TEMP,
+ M_NOWAIT | M_ZERO);
+ for (i = 0; i < nsfbufs; i++) {
+ sf_bufs[i].kva = sf_base + i * PAGE_SIZE;
+ SLIST_INSERT_HEAD(&sf_freelist.sf_head, &sf_bufs[i], free_list);
+ }
+ sf_buf_alloc_want = 0;
+}
+
+/*
+ * Get an sf_buf from the freelist. Will block if none are available.
+ */
+struct sf_buf *
+sf_buf_alloc(struct vm_page *m, int flags)
+{
+ struct sf_buf *sf;
+ int error;
+
+ mtx_lock(&sf_freelist.sf_lock);
+ while ((sf = SLIST_FIRST(&sf_freelist.sf_head)) == NULL) {
+ if (flags & SFB_NOWAIT)
+ break;
+ sf_buf_alloc_want++;
+ SFSTAT_INC(sf_allocwait);
+ error = msleep(&sf_freelist, &sf_freelist.sf_lock,
+ (flags & SFB_CATCH) ? PCATCH | PVM : PVM, "sfbufa", 0);
+ sf_buf_alloc_want--;
+
+ /*
+ * If we got a signal, don't risk going back to sleep.
+ */
+ if (error)
+ break;
+ }
+ if (sf != NULL) {
+ SLIST_REMOVE_HEAD(&sf_freelist.sf_head, free_list);
+ sf->m = m;
+ nsfbufsused++;
+ nsfbufspeak = imax(nsfbufspeak, nsfbufsused);
+ pmap_qenter(sf->kva, &sf->m, 1);
+ }
+ mtx_unlock(&sf_freelist.sf_lock);
+ return (sf);
+}
+
+/*
+ * Release resources back to the system.
+ */
+void
+sf_buf_free(struct sf_buf *sf)
+{
+ pmap_qremove(sf->kva, 1);
+ mtx_lock(&sf_freelist.sf_lock);
+ SLIST_INSERT_HEAD(&sf_freelist.sf_head, sf, free_list);
+ nsfbufsused--;
+ if (sf_buf_alloc_want > 0)
+ wakeup(&sf_freelist);
+ mtx_unlock(&sf_freelist.sf_lock);
+}
+#endif /* !__mips_n64 */
+
+/*
+ * Software interrupt handler for queued VM system processing.
+ */
+void
+swi_vm(void *dummy)
+{
+
+ if (busdma_swi_pending)
+ busdma_swi();
+}
+
+int
+cpu_set_user_tls(struct thread *td, void *tls_base)
+{
+
+ td->td_md.md_tls = (char*)tls_base;
+
+ return (0);
+}
+
+#ifdef DDB
+#include <ddb/ddb.h>
+
+#define DB_PRINT_REG(ptr, regname) \
+ db_printf(" %-12s %p\n", #regname, (void *)(intptr_t)((ptr)->regname))
+
+#define DB_PRINT_REG_ARRAY(ptr, arrname, regname) \
+ db_printf(" %-12s %p\n", #regname, (void *)(intptr_t)((ptr)->arrname[regname]))
+
+static void
+dump_trapframe(struct trapframe *trapframe)
+{
+
+ db_printf("Trapframe at %p\n", trapframe);
+
+ DB_PRINT_REG(trapframe, zero);
+ DB_PRINT_REG(trapframe, ast);
+ DB_PRINT_REG(trapframe, v0);
+ DB_PRINT_REG(trapframe, v1);
+ DB_PRINT_REG(trapframe, a0);
+ DB_PRINT_REG(trapframe, a1);
+ DB_PRINT_REG(trapframe, a2);
+ DB_PRINT_REG(trapframe, a3);
+#if defined(__mips_n32) || defined(__mips_n64)
+ DB_PRINT_REG(trapframe, a4);
+ DB_PRINT_REG(trapframe, a5);
+ DB_PRINT_REG(trapframe, a6);
+ DB_PRINT_REG(trapframe, a7);
+ DB_PRINT_REG(trapframe, t0);
+ DB_PRINT_REG(trapframe, t1);
+ DB_PRINT_REG(trapframe, t2);
+ DB_PRINT_REG(trapframe, t3);
+#else
+ DB_PRINT_REG(trapframe, t0);
+ DB_PRINT_REG(trapframe, t1);
+ DB_PRINT_REG(trapframe, t2);
+ DB_PRINT_REG(trapframe, t3);
+ DB_PRINT_REG(trapframe, t4);
+ DB_PRINT_REG(trapframe, t5);
+ DB_PRINT_REG(trapframe, t6);
+ DB_PRINT_REG(trapframe, t7);
+#endif
+ DB_PRINT_REG(trapframe, s0);
+ DB_PRINT_REG(trapframe, s1);
+ DB_PRINT_REG(trapframe, s2);
+ DB_PRINT_REG(trapframe, s3);
+ DB_PRINT_REG(trapframe, s4);
+ DB_PRINT_REG(trapframe, s5);
+ DB_PRINT_REG(trapframe, s6);
+ DB_PRINT_REG(trapframe, s7);
+ DB_PRINT_REG(trapframe, t8);
+ DB_PRINT_REG(trapframe, t9);
+ DB_PRINT_REG(trapframe, k0);
+ DB_PRINT_REG(trapframe, k1);
+ DB_PRINT_REG(trapframe, gp);
+ DB_PRINT_REG(trapframe, sp);
+ DB_PRINT_REG(trapframe, s8);
+ DB_PRINT_REG(trapframe, ra);
+ DB_PRINT_REG(trapframe, sr);
+ DB_PRINT_REG(trapframe, mullo);
+ DB_PRINT_REG(trapframe, mulhi);
+ DB_PRINT_REG(trapframe, badvaddr);
+ DB_PRINT_REG(trapframe, cause);
+ DB_PRINT_REG(trapframe, pc);
+}
+
+DB_SHOW_COMMAND(pcb, ddb_dump_pcb)
+{
+ struct thread *td;
+ struct pcb *pcb;
+ struct trapframe *trapframe;
+
+ /* Determine which thread to examine. */
+ if (have_addr)
+ td = db_lookup_thread(addr, TRUE);
+ else
+ td = curthread;
+
+ pcb = td->td_pcb;
+
+ db_printf("Thread %d at %p\n", td->td_tid, td);
+
+ db_printf("PCB at %p\n", pcb);
+
+ trapframe = &pcb->pcb_regs;
+ dump_trapframe(trapframe);
+
+ db_printf("PCB Context:\n");
+ DB_PRINT_REG_ARRAY(pcb, pcb_context, PCB_REG_S0);
+ DB_PRINT_REG_ARRAY(pcb, pcb_context, PCB_REG_S1);
+ DB_PRINT_REG_ARRAY(pcb, pcb_context, PCB_REG_S2);
+ DB_PRINT_REG_ARRAY(pcb, pcb_context, PCB_REG_S3);
+ DB_PRINT_REG_ARRAY(pcb, pcb_context, PCB_REG_S4);
+ DB_PRINT_REG_ARRAY(pcb, pcb_context, PCB_REG_S5);
+ DB_PRINT_REG_ARRAY(pcb, pcb_context, PCB_REG_S6);
+ DB_PRINT_REG_ARRAY(pcb, pcb_context, PCB_REG_S7);
+ DB_PRINT_REG_ARRAY(pcb, pcb_context, PCB_REG_SP);
+ DB_PRINT_REG_ARRAY(pcb, pcb_context, PCB_REG_S8);
+ DB_PRINT_REG_ARRAY(pcb, pcb_context, PCB_REG_RA);
+ DB_PRINT_REG_ARRAY(pcb, pcb_context, PCB_REG_SR);
+ DB_PRINT_REG_ARRAY(pcb, pcb_context, PCB_REG_GP);
+ DB_PRINT_REG_ARRAY(pcb, pcb_context, PCB_REG_PC);
+
+ db_printf("PCB onfault = %p\n", pcb->pcb_onfault);
+ db_printf("md_saved_intr = 0x%0lx\n", (long)td->td_md.md_saved_intr);
+ db_printf("md_spinlock_count = %d\n", td->td_md.md_spinlock_count);
+
+ if (td->td_frame != trapframe) {
+ db_printf("td->td_frame %p is not the same as pcb_regs %p\n",
+ td->td_frame, trapframe);
+ }
+}
+
+/*
+ * Dump the trapframe beginning at address specified by first argument.
+ */
+DB_SHOW_COMMAND(trapframe, ddb_dump_trapframe)
+{
+
+ if (!have_addr)
+ return;
+
+ dump_trapframe((struct trapframe *)addr);
+}
+
+#endif /* DDB */
Property changes on: trunk/sys/mips/mips/vm_machdep.c
___________________________________________________________________
Added: svn:eol-style
## -0,0 +1 ##
+native
\ No newline at end of property
Added: svn:keywords
## -0,0 +1 ##
+MidnightBSD=%H
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+text/plain
\ No newline at end of property
Added: trunk/sys/mips/nlm/board.c
===================================================================
--- trunk/sys/mips/nlm/board.c (rev 0)
+++ trunk/sys/mips/nlm/board.c 2018-05-26 21:55:02 UTC (rev 9987)
@@ -0,0 +1,538 @@
+/* $MidnightBSD$ */
+/*-
+ * Copyright 2003-2011 Netlogic Microsystems (Netlogic). All rights
+ * reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in
+ * the documentation and/or other materials provided with the
+ * distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY Netlogic Microsystems ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL NETLOGIC OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
+ * THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * NETLOGIC_BSD */
+
+#include <sys/cdefs.h>
+__FBSDID("$FreeBSD: stable/10/sys/mips/nlm/board.c 255368 2013-09-07 18:26:16Z jchandra $");
+#include <sys/param.h>
+#include <sys/systm.h>
+#include <sys/bus.h>
+#include <sys/kernel.h>
+#include <sys/lock.h>
+#include <sys/mutex.h>
+
+#include <net/ethernet.h>
+
+#include <mips/nlm/hal/mips-extns.h>
+#include <mips/nlm/hal/haldefs.h>
+#include <mips/nlm/hal/iomap.h>
+#include <mips/nlm/hal/fmn.h>
+#include <mips/nlm/hal/pic.h>
+#include <mips/nlm/hal/sys.h>
+#include <mips/nlm/hal/nae.h>
+#include <mips/nlm/hal/uart.h>
+#include <mips/nlm/hal/poe.h>
+
+#include <mips/nlm/xlp.h>
+#include <mips/nlm/board.h>
+#include <mips/nlm/msgring.h>
+
+static uint8_t board_eeprom_buf[EEPROM_SIZE];
+static int board_eeprom_set;
+
+struct xlp_board_info xlp_board_info;
+
+struct vfbid_tbl {
+ int vfbid;
+ int dest_vc;
+};
+
+/* XXXJC : this should be derived from msg thread mask */
+static struct vfbid_tbl nlm_vfbid[] = {
+ /* NULL FBID should map to cpu0 to detect NAE send msg errors */
+ {127, 0}, /* NAE <-> NAE mappings */
+ {51, 1019}, {50, 1018}, {49, 1017}, {48, 1016},
+ {47, 1015}, {46, 1014}, {45, 1013}, {44, 1012},
+ {43, 1011}, {42, 1010}, {41, 1009}, {40, 1008},
+ {39, 1007}, {38, 1006}, {37, 1005}, {36, 1004},
+ {35, 1003}, {34, 1002}, {33, 1001}, {32, 1000},
+ /* NAE <-> CPU mappings, freeback got to vc 3 of each thread */
+ {31, 127}, {30, 123}, {29, 119}, {28, 115},
+ {27, 111}, {26, 107}, {25, 103}, {24, 99},
+ {23, 95}, {22, 91}, {21, 87}, {20, 83},
+ {19, 79}, {18, 75}, {17, 71}, {16, 67},
+ {15, 63}, {14, 59}, {13, 55}, {12, 51},
+ {11, 47}, {10, 43}, { 9, 39}, { 8, 35},
+ { 7, 31}, { 6, 27}, { 5, 23}, { 4, 19},
+ { 3, 15}, { 2, 11}, { 1, 7}, { 0, 3},
+};
+
+static struct vfbid_tbl nlm3xx_vfbid[] = {
+ /* NULL FBID should map to cpu0 to detect NAE send msg errors */
+ {127, 0}, /* NAE <-> NAE mappings */
+ {39, 503}, {38, 502}, {37, 501}, {36, 500},
+ {35, 499}, {34, 498}, {33, 497}, {32, 496},
+ /* NAE <-> CPU mappings, freeback got to vc 3 of each thread */
+ {31, 127}, {30, 123}, {29, 119}, {28, 115},
+ {27, 111}, {26, 107}, {25, 103}, {24, 99},
+ {23, 95}, {22, 91}, {21, 87}, {20, 83},
+ {19, 79}, {18, 75}, {17, 71}, {16, 67},
+ {15, 63}, {14, 59}, {13, 55}, {12, 51},
+ {11, 47}, {10, 43}, { 9, 39}, { 8, 35},
+ { 7, 31}, { 6, 27}, { 5, 23}, { 4, 19},
+ { 3, 15}, { 2, 11}, { 1, 7}, { 0, 3},
+};
+
+int
+nlm_get_vfbid_mapping(int vfbid)
+{
+ int i, nentries;
+ struct vfbid_tbl *p;
+
+ if (nlm_is_xlp3xx()) {
+ nentries = sizeof(nlm3xx_vfbid)/sizeof(struct vfbid_tbl);
+ p = nlm3xx_vfbid;
+ } else {
+ nentries = sizeof(nlm_vfbid)/sizeof(struct vfbid_tbl);
+ p = nlm_vfbid;
+ }
+
+ for (i = 0; i < nentries; i++) {
+ if (p[i].vfbid == vfbid)
+ return (p[i].dest_vc);
+ }
+
+ return (-1);
+}
+
+int
+nlm_get_poe_distvec(int vec, uint32_t *distvec)
+{
+
+ if (vec != 0)
+ return (-1); /* we support just vec 0 */
+ nlm_calc_poe_distvec(xlp_msg_thread_mask, 0, 0, 0,
+ 0x1 << XLPGE_RX_VC, distvec);
+ return (0);
+}
+
+/*
+ * All our knowledge of chip and board that cannot be detected by probing
+ * at run-time goes here
+ */
+
+void
+xlpge_get_macaddr(uint8_t *macaddr)
+{
+
+ if (board_eeprom_set == 0) {
+ /* No luck, take some reasonable value */
+ macaddr[0] = 0x00; macaddr[1] = 0x0f; macaddr[2] = 0x30;
+ macaddr[3] = 0x20; macaddr[4] = 0x0d; macaddr[5] = 0x5b;
+ } else
+ memcpy(macaddr, &board_eeprom_buf[EEPROM_MACADDR_OFFSET],
+ ETHER_ADDR_LEN);
+}
+
+static void
+nlm_setup_port_defaults(struct xlp_port_ivars *p)
+{
+ p->loopback_mode = 0;
+ p->num_channels = 1;
+ p->free_desc_sizes = 2048;
+ p->vlan_pri_en = 0;
+ p->hw_parser_en = 1;
+ p->ieee1588_userval = 0;
+ p->ieee1588_ptpoff = 0;
+ p->ieee1588_tmr1 = 0;
+ p->ieee1588_tmr2 = 0;
+ p->ieee1588_tmr3 = 0;
+ p->ieee1588_inc_intg = 0;
+ p->ieee1588_inc_den = 1;
+ p->ieee1588_inc_num = 1;
+
+ if (nlm_is_xlp3xx()) {
+ p->stg2_fifo_size = XLP3XX_STG2_FIFO_SZ;
+ p->eh_fifo_size = XLP3XX_EH_FIFO_SZ;
+ p->frout_fifo_size = XLP3XX_FROUT_FIFO_SZ;
+ p->ms_fifo_size = XLP3XX_MS_FIFO_SZ;
+ p->pkt_fifo_size = XLP3XX_PKT_FIFO_SZ;
+ p->pktlen_fifo_size = XLP3XX_PKTLEN_FIFO_SZ;
+ p->max_stg2_offset = XLP3XX_MAX_STG2_OFFSET;
+ p->max_eh_offset = XLP3XX_MAX_EH_OFFSET;
+ p->max_frout_offset = XLP3XX_MAX_FREE_OUT_OFFSET;
+ p->max_ms_offset = XLP3XX_MAX_MS_OFFSET;
+ p->max_pmem_offset = XLP3XX_MAX_PMEM_OFFSET;
+ p->stg1_2_credit = XLP3XX_STG1_2_CREDIT;
+ p->stg2_eh_credit = XLP3XX_STG2_EH_CREDIT;
+ p->stg2_frout_credit = XLP3XX_STG2_FROUT_CREDIT;
+ p->stg2_ms_credit = XLP3XX_STG2_MS_CREDIT;
+ } else {
+ p->stg2_fifo_size = XLP8XX_STG2_FIFO_SZ;
+ p->eh_fifo_size = XLP8XX_EH_FIFO_SZ;
+ p->frout_fifo_size = XLP8XX_FROUT_FIFO_SZ;
+ p->ms_fifo_size = XLP8XX_MS_FIFO_SZ;
+ p->pkt_fifo_size = XLP8XX_PKT_FIFO_SZ;
+ p->pktlen_fifo_size = XLP8XX_PKTLEN_FIFO_SZ;
+ p->max_stg2_offset = XLP8XX_MAX_STG2_OFFSET;
+ p->max_eh_offset = XLP8XX_MAX_EH_OFFSET;
+ p->max_frout_offset = XLP8XX_MAX_FREE_OUT_OFFSET;
+ p->max_ms_offset = XLP8XX_MAX_MS_OFFSET;
+ p->max_pmem_offset = XLP8XX_MAX_PMEM_OFFSET;
+ p->stg1_2_credit = XLP8XX_STG1_2_CREDIT;
+ p->stg2_eh_credit = XLP8XX_STG2_EH_CREDIT;
+ p->stg2_frout_credit = XLP8XX_STG2_FROUT_CREDIT;
+ p->stg2_ms_credit = XLP8XX_STG2_MS_CREDIT;
+ }
+
+ switch (p->type) {
+ case SGMIIC:
+ p->num_free_descs = 52;
+ p->iface_fifo_size = 13;
+ p->rxbuf_size = 128;
+ p->rx_slots_reqd = SGMII_CAL_SLOTS;
+ p->tx_slots_reqd = SGMII_CAL_SLOTS;
+ if (nlm_is_xlp3xx())
+ p->pseq_fifo_size = 30;
+ else
+ p->pseq_fifo_size = 62;
+ break;
+ case ILC:
+ p->num_free_descs = 150;
+ p->rxbuf_size = 944;
+ p->rx_slots_reqd = IL8_CAL_SLOTS;
+ p->tx_slots_reqd = IL8_CAL_SLOTS;
+ p->pseq_fifo_size = 225;
+ p->iface_fifo_size = 55;
+ break;
+ case XAUIC:
+ default:
+ p->num_free_descs = 150;
+ p->rxbuf_size = 944;
+ p->rx_slots_reqd = XAUI_CAL_SLOTS;
+ p->tx_slots_reqd = XAUI_CAL_SLOTS;
+ if (nlm_is_xlp3xx()) {
+ p->pseq_fifo_size = 120;
+ p->iface_fifo_size = 52;
+ } else {
+ p->pseq_fifo_size = 225;
+ p->iface_fifo_size = 55;
+ }
+ break;
+ }
+}
+
+/* XLP 8XX evaluation boards have the following phy-addr
+ * assignment. There are two external mdio buses in XLP --
+ * bus 0 and bus 1. The management ports (16 and 17) are
+ * on mdio bus 0 while blocks/complexes[0 to 3] are all
+ * on mdio bus 1. The phy_addr on bus 0 (mgmt ports 16
+ * and 17) match the port numbers.
+ * These are the details:
+ * block port phy_addr mdio_bus
+ * ====================================
+ * 0 0 4 1
+ * 0 1 7 1
+ * 0 2 6 1
+ * 0 3 5 1
+ * 1 0 8 1
+ * 1 1 11 1
+ * 1 2 10 1
+ * 1 3 9 1
+ * 2 0 0 1
+ * 2 1 3 1
+ * 2 2 2 1
+ * 2 3 1 1
+ * 3 0 12 1
+ * 3 1 15 1
+ * 3 2 14 1
+ * 3 3 13 1
+ *
+ * 4 0 16 0
+ * 4 1 17 0
+ *
+ * The XLP 3XX evaluation boards have the following phy-addr
+ * assignments.
+ * block port phy_addr mdio_bus
+ * ====================================
+ * 0 0 4 0
+ * 0 1 7 0
+ * 0 2 6 0
+ * 0 3 5 0
+ * 1 0 8 0
+ * 1 1 11 0
+ * 1 2 10 0
+ * 1 3 9 0
+ */
+static void
+nlm_board_get_phyaddr(int block, int port, int *phyaddr)
+{
+ switch (block) {
+ case 0: switch (port) {
+ case 0: *phyaddr = 4; break;
+ case 1: *phyaddr = 7; break;
+ case 2: *phyaddr = 6; break;
+ case 3: *phyaddr = 5; break;
+ }
+ break;
+ case 1: switch (port) {
+ case 0: *phyaddr = 8; break;
+ case 1: *phyaddr = 11; break;
+ case 2: *phyaddr = 10; break;
+ case 3: *phyaddr = 9; break;
+ }
+ break;
+ case 2: switch (port) {
+ case 0: *phyaddr = 0; break;
+ case 1: *phyaddr = 3; break;
+ case 2: *phyaddr = 2; break;
+ case 3: *phyaddr = 1; break;
+ }
+ break;
+ case 3: switch (port) {
+ case 0: *phyaddr = 12; break;
+ case 1: *phyaddr = 15; break;
+ case 2: *phyaddr = 14; break;
+ case 3: *phyaddr = 13; break;
+ }
+ break;
+ case 4: switch (port) { /* management SGMII */
+ case 0: *phyaddr = 16; break;
+ case 1: *phyaddr = 17; break;
+ }
+ break;
+ }
+}
+
+
+static void
+nlm_print_processor_info(void)
+{
+ uint32_t procid;
+ int prid, rev;
+ char *chip, *revstr;
+
+ procid = mips_rd_prid();
+ prid = (procid >> 8) & 0xff;
+ rev = procid & 0xff;
+
+ switch (prid) {
+ case CHIP_PROCESSOR_ID_XLP_8XX:
+ chip = "XLP 832";
+ break;
+ case CHIP_PROCESSOR_ID_XLP_3XX:
+ chip = "XLP 3xx";
+ break;
+ case CHIP_PROCESSOR_ID_XLP_432:
+ case CHIP_PROCESSOR_ID_XLP_416:
+ chip = "XLP 4xx";
+ break;
+ default:
+ chip = "XLP ?xx";
+ break;
+ }
+ switch (rev) {
+ case 0:
+ revstr = "A0"; break;
+ case 1:
+ revstr = "A1"; break;
+ case 2:
+ revstr = "A2"; break;
+ case 3:
+ revstr = "B0"; break;
+ case 4:
+ revstr = "B1"; break;
+ default:
+ revstr = "??"; break;
+ }
+
+ printf("Processor info:\n");
+ printf(" Netlogic %s %s [%x]\n", chip, revstr, procid);
+}
+
+/*
+ * All our knowledge of chip and board that cannot be detected by probing
+ * at run-time goes here
+ */
+static int
+nlm_setup_xlp_board(int node)
+{
+ struct xlp_board_info *boardp;
+ struct xlp_node_info *nodep;
+ struct xlp_nae_ivars *naep;
+ struct xlp_block_ivars *blockp;
+ struct xlp_port_ivars *portp;
+ uint64_t cpldbase, nae_pcibase;
+ int block, port, rv, dbtype, usecpld = 0, evp = 0, svp = 0;
+ uint8_t *b;
+
+ /* start with a clean slate */
+ boardp = &xlp_board_info;
+ if (boardp->nodemask == 0)
+ memset(boardp, 0, sizeof(xlp_board_info));
+ boardp->nodemask |= (1 << node);
+ nlm_print_processor_info();
+
+ b = board_eeprom_buf;
+ rv = nlm_board_eeprom_read(node, EEPROM_I2CBUS, EEPROM_I2CADDR, 0, b,
+ EEPROM_SIZE);
+ if (rv == 0) {
+ board_eeprom_set = 1;
+ printf("Board info (EEPROM on i2c@%d at %#X):\n",
+ EEPROM_I2CBUS, EEPROM_I2CADDR);
+ printf(" Model: %7.7s %2.2s\n", &b[16], &b[24]);
+ printf(" Serial #: %3.3s-%2.2s\n", &b[27], &b[31]);
+ printf(" MAC addr: %02x:%02x:%02x:%02x:%02x:%02x\n",
+ b[2], b[3], b[4], b[5], b[6], b[7]);
+ } else
+ printf("Board Info: Error on EEPROM read (i2c@%d %#X).\n",
+ EEPROM_I2CBUS, EEPROM_I2CADDR);
+
+ nae_pcibase = nlm_get_nae_pcibase(node);
+ nodep = &boardp->nodes[node];
+ naep = &nodep->nae_ivars;
+ naep->node = node;
+
+ /* frequency at which network block runs */
+ naep->freq = 500;
+
+ /* CRC16 polynomial used for flow table generation */
+ naep->flow_crc_poly = 0xffff;
+ naep->hw_parser_en = 1;
+ naep->prepad_en = 1;
+ naep->prepad_size = 3; /* size in 16 byte units */
+ naep->ieee_1588_en = 1;
+
+ naep->ilmask = 0x0; /* set this based on daughter card */
+ naep->xauimask = 0x0; /* set this based on daughter card */
+ naep->sgmiimask = 0x0; /* set this based on daughter card */
+ naep->nblocks = nae_num_complex(nae_pcibase);
+ if (strncmp(&b[16], "PCIE", 4) == 0) {
+ usecpld = 0; /* XLP PCIe card */
+ /* Broadcom's XLP PCIe card has the following
+ * blocks fixed.
+ * blk 0-XAUI, 1-XAUI, 4-SGMII(one port) */
+ naep->blockmask = 0x13;
+ } else if (strncmp(&b[16], "MB-EVP", 6) == 0) {
+ usecpld = 1; /* XLP non-PCIe card which has CPLD */
+ evp = 1;
+ naep->blockmask = (1 << naep->nblocks) - 1;
+ } else if ((strncmp(&b[16], "MB-S", 4) == 0) ||
+ (strncmp(&b[16], "MB_S", 4) == 0)) {
+ usecpld = 1; /* XLP non-PCIe card which has CPLD */
+ svp = 1;
+ /* 3xx chip reports one block extra which is a bug */
+ naep->nblocks = naep->nblocks - 1;
+ naep->blockmask = (1 << naep->nblocks) - 1;
+ } else {
+ printf("ERROR!!! Board type:%7s didn't match any board"
+ " type we support\n", &b[16]);
+ return (-1);
+ }
+ cpldbase = nlm_board_cpld_base(node, XLP_EVB_CPLD_CHIPSELECT);
+
+ /* pretty print network config */
+ printf("Network config");
+ if (usecpld)
+ printf("(from CPLD@%d):\n", XLP_EVB_CPLD_CHIPSELECT);
+ else
+ printf("(defaults):\n");
+ printf(" NAE@%d Blocks: ", node);
+ for (block = 0; block < naep->nblocks; block++) {
+ char *s = "???";
+
+ if ((naep->blockmask & (1 << block)) == 0)
+ continue;
+ blockp = &naep->block_ivars[block];
+ blockp->block = block;
+ if (usecpld)
+ dbtype = nlm_board_cpld_dboard_type(cpldbase, block);
+ else
+ dbtype = DCARD_XAUI; /* default XAUI */
+
+ /* XLP PCIe cards */
+ if ((!evp && !svp) && ((block == 2) || (block == 3)))
+ dbtype = DCARD_NOT_PRSNT;
+
+ if (block == 4) {
+ /* management block 4 on 8xx or XLP PCIe */
+ blockp->type = SGMIIC;
+ if (evp)
+ blockp->portmask = 0x3;
+ else
+ blockp->portmask = 0x1;
+ naep->sgmiimask |= (1 << block);
+ } else {
+ switch (dbtype) {
+ case DCARD_ILAKEN:
+ blockp->type = ILC;
+ blockp->portmask = 0x1;
+ naep->ilmask |= (1 << block);
+ break;
+ case DCARD_SGMII:
+ blockp->type = SGMIIC;
+ blockp->portmask = 0xf;
+ naep->sgmiimask |= (1 << block);
+ break;
+ case DCARD_XAUI:
+ blockp->type = XAUIC;
+ blockp->portmask = 0x1;
+ naep->xauimask |= (1 << block);
+ break;
+ default: /* DCARD_NOT_PRSNT */
+ blockp->type = UNKNOWN;
+ blockp->portmask = 0;
+ break;
+ }
+ }
+ if (blockp->type != UNKNOWN) {
+ for (port = 0; port < PORTS_PER_CMPLX; port++) {
+ if ((blockp->portmask & (1 << port)) == 0)
+ continue;
+ portp = &blockp->port_ivars[port];
+ nlm_board_get_phyaddr(block, port,
+ &portp->phy_addr);
+ if (svp || (block == 4))
+ portp->mdio_bus = 0;
+ else
+ portp->mdio_bus = 1;
+ portp->port = port;
+ portp->block = block;
+ portp->node = node;
+ portp->type = blockp->type;
+ nlm_setup_port_defaults(portp);
+ }
+ }
+ switch (blockp->type) {
+ case SGMIIC : s = "SGMII"; break;
+ case XAUIC : s = "XAUI"; break;
+ case ILC : s = "IL"; break;
+ }
+ printf(" [%d %s]", block, s);
+ }
+ printf("\n");
+ return (0);
+}
+
+int nlm_board_info_setup(void)
+{
+ if (nlm_setup_xlp_board(0) != 0)
+ return (-1);
+ return (0);
+}
Property changes on: trunk/sys/mips/nlm/board.c
___________________________________________________________________
Added: svn:eol-style
## -0,0 +1 ##
+native
\ No newline at end of property
Added: svn:keywords
## -0,0 +1 ##
+MidnightBSD=%H
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+text/plain
\ No newline at end of property
Added: trunk/sys/mips/nlm/board.h
===================================================================
--- trunk/sys/mips/nlm/board.h (rev 0)
+++ trunk/sys/mips/nlm/board.h 2018-05-26 21:55:02 UTC (rev 9987)
@@ -0,0 +1,158 @@
+/* $MidnightBSD$ */
+/*-
+ * Copyright 2003-2011 Netlogic Microsystems (Netlogic). All rights
+ * reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in
+ * the documentation and/or other materials provided with the
+ * distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY Netlogic Microsystems ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL NETLOGIC OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
+ * THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * NETLOGIC_BSD
+ * $FreeBSD: stable/10/sys/mips/nlm/board.h 255368 2013-09-07 18:26:16Z jchandra $
+ */
+
+#ifndef __NLM_BOARD_H__
+#define __NLM_BOARD_H__
+
+#define XLP_NAE_NBLOCKS 5
+#define XLP_NAE_NPORTS 4
+
+/*
+ * EVP board EEPROM info
+ */
+#define EEPROM_I2CBUS 1
+#define EEPROM_I2CADDR 0xAE
+#define EEPROM_SIZE 48
+#define EEPROM_MACADDR_OFFSET 2
+
+/* used if there is no FDT */
+#define BOARD_CONSOLE_SPEED 115200
+#define BOARD_CONSOLE_UART 0
+
+/*
+ * EVP board CPLD chip select and daughter card info field
+ */
+#define XLP_EVB_CPLD_CHIPSELECT 2
+
+#define DCARD_ILAKEN 0x0
+#define DCARD_SGMII 0x1
+#define DCARD_XAUI 0x2
+#define DCARD_NOT_PRSNT 0x3
+
+#if !defined(LOCORE) && !defined(__ASSEMBLY__)
+/*
+ * NAE configuration
+ */
+
+struct xlp_port_ivars {
+ int port;
+ int block;
+ int node;
+ int type;
+ int phy_addr;
+ int mdio_bus;
+ int loopback_mode;
+ int num_channels;
+ int free_desc_sizes;
+ int num_free_descs;
+ int pseq_fifo_size;
+ int iface_fifo_size;
+ int rxbuf_size;
+ int rx_slots_reqd;
+ int tx_slots_reqd;
+ int vlan_pri_en;
+ int stg2_fifo_size;
+ int eh_fifo_size;
+ int frout_fifo_size;
+ int ms_fifo_size;
+ int pkt_fifo_size;
+ int pktlen_fifo_size;
+ int max_stg2_offset;
+ int max_eh_offset;
+ int max_frout_offset;
+ int max_ms_offset;
+ int max_pmem_offset;
+ int stg1_2_credit;
+ int stg2_eh_credit;
+ int stg2_frout_credit;
+ int stg2_ms_credit;
+ int hw_parser_en;
+ u_int ieee1588_inc_intg;
+ u_int ieee1588_inc_den;
+ u_int ieee1588_inc_num;
+ uint64_t ieee1588_userval;
+ uint64_t ieee1588_ptpoff;
+ uint64_t ieee1588_tmr1;
+ uint64_t ieee1588_tmr2;
+ uint64_t ieee1588_tmr3;
+};
+
+struct xlp_block_ivars {
+ int block;
+ int type;
+ u_int portmask;
+ struct xlp_port_ivars port_ivars[XLP_NAE_NPORTS];
+};
+
+struct xlp_nae_ivars {
+ int node;
+ int nblocks;
+ u_int blockmask;
+ u_int ilmask;
+ u_int xauimask;
+ u_int sgmiimask;
+ int freq;
+ u_int flow_crc_poly;
+ u_int hw_parser_en;
+ u_int prepad_en;
+ u_int prepad_size; /* size in 16 byte units */
+ u_int ieee_1588_en;
+ struct xlp_block_ivars block_ivars[XLP_NAE_NBLOCKS];
+};
+
+struct xlp_board_info {
+ u_int nodemask;
+ struct xlp_node_info {
+ struct xlp_nae_ivars nae_ivars;
+ } nodes[XLP_MAX_NODES];
+};
+
+extern struct xlp_board_info xlp_board_info;
+
+/* Network configuration */
+int nlm_get_vfbid_mapping(int);
+int nlm_get_poe_distvec(int vec, uint32_t *distvec);
+void xlpge_get_macaddr(uint8_t *macaddr);
+
+int nlm_board_info_setup(void);
+
+/* EEPROM & CPLD */
+int nlm_board_eeprom_read(int node, int i2cbus, int addr, int offs,
+ uint8_t *buf,int sz);
+uint64_t nlm_board_cpld_base(int node, int chipselect);
+int nlm_board_cpld_majorversion(uint64_t cpldbase);
+int nlm_board_cpld_minorversion(uint64_t cpldbase);
+void nlm_board_cpld_reset(uint64_t cpldbase);
+int nlm_board_cpld_dboard_type(uint64_t cpldbase, int slot);
+
+#endif
+#endif
Property changes on: trunk/sys/mips/nlm/board.h
___________________________________________________________________
Added: svn:eol-style
## -0,0 +1 ##
+native
\ No newline at end of property
Added: svn:keywords
## -0,0 +1 ##
+MidnightBSD=%H
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+text/plain
\ No newline at end of property
Added: trunk/sys/mips/nlm/board_cpld.c
===================================================================
--- trunk/sys/mips/nlm/board_cpld.c (rev 0)
+++ trunk/sys/mips/nlm/board_cpld.c 2018-05-26 21:55:02 UTC (rev 9987)
@@ -0,0 +1,114 @@
+/* $MidnightBSD$ */
+/*-
+ * Copyright (c) 2003-2012 Broadcom Corporation
+ * All Rights Reserved
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in
+ * the documentation and/or other materials provided with the
+ * distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY BROADCOM ``AS IS'' AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL BROADCOM OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
+ * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
+ * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
+ * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <sys/cdefs.h>
+__FBSDID("$FreeBSD: stable/10/sys/mips/nlm/board_cpld.c 255368 2013-09-07 18:26:16Z jchandra $");
+#include <sys/param.h>
+#include <sys/systm.h>
+#include <sys/endian.h>
+
+#include <mips/nlm/hal/mips-extns.h>
+#include <mips/nlm/hal/haldefs.h>
+#include <mips/nlm/hal/iomap.h>
+#include <mips/nlm/hal/gbu.h>
+
+#include <mips/nlm/board.h>
+
+#define CPLD_REVISION 0x0
+#define CPLD_RESET 0x1
+#define CPLD_CTRL 0x2
+#define CPLD_RSVD 0x3
+#define CPLD_PWR_CTRL 0x4
+#define CPLD_MISC 0x5
+#define CPLD_CTRL_STATUS 0x6
+#define CPLD_PWR_INTR_STATUS 0x7
+#define CPLD_DATA 0x8
+
+static __inline
+int nlm_cpld_read(uint64_t base, int reg)
+{
+ uint16_t val;
+
+ val = *(volatile uint16_t *)(long)(base + reg * 2);
+ return le16toh(val);
+}
+
+static __inline void
+nlm_cpld_write(uint64_t base, int reg, uint16_t data)
+{
+ data = htole16(data);
+ *(volatile uint16_t *)(long)(base + reg * 2) = data;
+}
+
+int
+nlm_board_cpld_majorversion(uint64_t base)
+{
+ return (nlm_cpld_read(base, CPLD_REVISION) >> 8);
+}
+
+int
+nlm_board_cpld_minorversion(uint64_t base)
+{
+ return (nlm_cpld_read(base, CPLD_REVISION) & 0xff);
+}
+
+uint64_t nlm_board_cpld_base(int node, int chipselect)
+{
+ uint64_t gbubase, cpld_phys;
+
+ gbubase = nlm_get_gbu_regbase(node);
+ cpld_phys = nlm_read_gbu_reg(gbubase, GBU_CS_BASEADDR(chipselect));
+ return (MIPS_PHYS_TO_KSEG1(cpld_phys << 8));
+}
+
+void
+nlm_board_cpld_reset(uint64_t base)
+{
+
+ nlm_cpld_write(base, CPLD_RESET, 1 << 15);
+ for(;;)
+ __asm __volatile("wait");
+}
+
+/* get daughter board type */
+int
+nlm_board_cpld_dboard_type(uint64_t base, int slot)
+{
+ uint16_t val;
+ int shift = 0;
+
+ switch (slot) {
+ case 0: shift = 0; break;
+ case 1: shift = 4; break;
+ case 2: shift = 2; break;
+ case 3: shift = 6; break;
+ }
+ val = nlm_cpld_read(base, CPLD_CTRL_STATUS) >> shift;
+ return (val & 0x3);
+}
Property changes on: trunk/sys/mips/nlm/board_cpld.c
___________________________________________________________________
Added: svn:eol-style
## -0,0 +1 ##
+native
\ No newline at end of property
Added: svn:keywords
## -0,0 +1 ##
+MidnightBSD=%H
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+text/plain
\ No newline at end of property
Added: trunk/sys/mips/nlm/board_eeprom.c
===================================================================
--- trunk/sys/mips/nlm/board_eeprom.c (rev 0)
+++ trunk/sys/mips/nlm/board_eeprom.c 2018-05-26 21:55:02 UTC (rev 9987)
@@ -0,0 +1,173 @@
+/* $MidnightBSD$ */
+/*-
+ * Copyright (c) 2003-2012 Broadcom Corporation
+ * All Rights Reserved
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in
+ * the documentation and/or other materials provided with the
+ * distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY BROADCOM ``AS IS'' AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL BROADCOM OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
+ * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
+ * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
+ * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <sys/cdefs.h>
+__FBSDID("$FreeBSD: stable/10/sys/mips/nlm/board_eeprom.c 233542 2012-03-27 12:25:47Z jchandra $");
+#include <sys/param.h>
+#include <sys/endian.h>
+#include <sys/systm.h>
+#include <sys/kernel.h>
+#include <sys/limits.h>
+#include <sys/bus.h>
+
+#include <dev/iicbus/iicoc.h>
+
+#include <mips/nlm/hal/haldefs.h>
+#include <mips/nlm/hal/iomap.h>
+#include <mips/nlm/hal/mips-extns.h> /* needed by board.h */
+
+#include <mips/nlm/board.h>
+
+/*
+ * We have to read the EEPROM in early boot (now only for MAC addr)
+ * but later for board information. Use simple polled mode driver
+ * for I2C
+ */
+#define oc_read_reg(reg) nlm_read_reg(eeprom_i2c_base, reg)
+#define oc_write_reg(reg, val) nlm_write_reg(eeprom_i2c_base, reg, val)
+
+static uint64_t eeprom_i2c_base;
+
+static int
+oc_wait_on_status(uint8_t bit)
+{
+ int tries = I2C_TIMEOUT;
+ uint8_t status;
+
+ do {
+ status = oc_read_reg(OC_I2C_STATUS_REG);
+ } while ((status & bit) != 0 && --tries > 0);
+
+ return (tries == 0 ? -1: 0);
+}
+
+static int
+oc_rd_cmd(uint8_t cmd)
+{
+ uint8_t data;
+
+ oc_write_reg(OC_I2C_CMD_REG, cmd);
+ if (oc_wait_on_status(OC_STATUS_TIP) < 0)
+ return (-1);
+
+ data = oc_read_reg(OC_I2C_DATA_REG);
+ return (data);
+}
+
+static int
+oc_wr_cmd(uint8_t data, uint8_t cmd)
+{
+ oc_write_reg(OC_I2C_DATA_REG, data);
+ oc_write_reg(OC_I2C_CMD_REG, cmd);
+
+ if (oc_wait_on_status(OC_STATUS_TIP) < 0)
+ return (-1);
+ return (0);
+}
+
+int
+nlm_board_eeprom_read(int node, int bus, int addr, int offs, uint8_t *buf,
+ int sz)
+{
+ int rd, i;
+ char *err = NULL;
+
+ eeprom_i2c_base = nlm_pcicfg_base(XLP_IO_I2C_OFFSET(node, bus)) +
+ XLP_IO_PCI_HDRSZ;
+
+ if (oc_wait_on_status(OC_STATUS_BUSY) < 0) {
+ err = "Not idle";
+ goto err_exit;
+ }
+
+ /* write start */
+ if (oc_wr_cmd(addr, OC_COMMAND_START)) {
+ err = "I2C write start failed.";
+ goto err_exit;
+ }
+
+ if (oc_read_reg(OC_I2C_STATUS_REG) & OC_STATUS_NACK) {
+ err = "No ack after start";
+ goto err_exit_stop;
+ }
+
+ if (oc_read_reg(OC_I2C_STATUS_REG) & OC_STATUS_AL) {
+ err = "I2C Bus Arbitration Lost";
+ goto err_exit_stop;
+ }
+
+ /* Write offset */
+ if (oc_wr_cmd(offs, OC_COMMAND_WRITE)) {
+ err = "I2C write slave offset failed.";
+ goto err_exit_stop;
+ }
+
+ if (oc_read_reg(OC_I2C_STATUS_REG) & OC_STATUS_NACK) {
+ err = "No ack after write";
+ goto err_exit_stop;
+ }
+
+ /* read start */
+ if (oc_wr_cmd(addr | 1, OC_COMMAND_START)) {
+ err = "I2C read start failed.";
+ goto err_exit_stop;
+ }
+
+ if (oc_read_reg(OC_I2C_STATUS_REG) & OC_STATUS_NACK) {
+ err = "No ack after read start";
+ goto err_exit_stop;
+ }
+
+ for (i = 0; i < sz - 1; i++) {
+ if ((rd = oc_rd_cmd(OC_COMMAND_READ)) < 0) {
+ err = "I2C read data byte failed.";
+ goto err_exit_stop;
+ }
+ buf[i] = rd;
+ }
+
+ /* last byte */
+ if ((rd = oc_rd_cmd(OC_COMMAND_RDNACK)) < 0) {
+ err = "I2C read last data byte failed.";
+ goto err_exit_stop;
+ }
+ buf[sz - 1] = rd;
+
+err_exit_stop:
+ oc_write_reg(OC_I2C_CMD_REG, OC_COMMAND_STOP);
+ if (oc_wait_on_status(OC_STATUS_BUSY) < 0)
+ printf("%s: stop failed", __func__);
+
+err_exit:
+ if (err) {
+ printf("%s: Failed (%s)\n", __func__, err);
+ return (-1);
+ }
+ return (0);
+}
Property changes on: trunk/sys/mips/nlm/board_eeprom.c
___________________________________________________________________
Added: svn:eol-style
## -0,0 +1 ##
+native
\ No newline at end of property
Added: svn:keywords
## -0,0 +1 ##
+MidnightBSD=%H
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+text/plain
\ No newline at end of property
Added: trunk/sys/mips/nlm/bus_space_rmi.c
===================================================================
--- trunk/sys/mips/nlm/bus_space_rmi.c (rev 0)
+++ trunk/sys/mips/nlm/bus_space_rmi.c 2018-05-26 21:55:02 UTC (rev 9987)
@@ -0,0 +1,773 @@
+/* $MidnightBSD$ */
+/*
+ * Copyright 2003-2011 Netlogic Microsystems (Netlogic). All rights
+ * reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in
+ * the documentation and/or other materials provided with the
+ * distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY Netlogic Microsystems ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL NETLOGIC OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
+ * THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * NETLOGIC_BSD */
+
+#include <sys/cdefs.h>
+__FBSDID("$FreeBSD: stable/10/sys/mips/nlm/bus_space_rmi.c 239487 2012-08-21 09:37:23Z jchandra $");
+
+#include <sys/param.h>
+#include <sys/systm.h>
+#include <sys/bus.h>
+#include <sys/kernel.h>
+#include <sys/endian.h>
+#include <sys/malloc.h>
+#include <sys/ktr.h>
+
+#include <vm/vm.h>
+#include <vm/pmap.h>
+#include <vm/vm_kern.h>
+#include <vm/vm_extern.h>
+
+#include <machine/bus.h>
+#include <machine/cache.h>
+
+static int
+rmi_bus_space_map(void *t, bus_addr_t addr,
+ bus_size_t size, int flags,
+ bus_space_handle_t *bshp);
+
+static void
+rmi_bus_space_unmap(void *t, bus_space_handle_t bsh,
+ bus_size_t size);
+
+static int
+rmi_bus_space_subregion(void *t,
+ bus_space_handle_t bsh,
+ bus_size_t offset, bus_size_t size,
+ bus_space_handle_t *nbshp);
+
+static u_int8_t
+rmi_bus_space_read_1(void *t,
+ bus_space_handle_t handle,
+ bus_size_t offset);
+
+static u_int16_t
+rmi_bus_space_read_2(void *t,
+ bus_space_handle_t handle,
+ bus_size_t offset);
+
+static u_int32_t
+rmi_bus_space_read_4(void *t,
+ bus_space_handle_t handle,
+ bus_size_t offset);
+
+static void
+rmi_bus_space_read_multi_1(void *t,
+ bus_space_handle_t handle,
+ bus_size_t offset, u_int8_t *addr,
+ size_t count);
+
+static void
+rmi_bus_space_read_multi_2(void *t,
+ bus_space_handle_t handle,
+ bus_size_t offset, u_int16_t *addr,
+ size_t count);
+
+static void
+rmi_bus_space_read_multi_4(void *t,
+ bus_space_handle_t handle,
+ bus_size_t offset, u_int32_t *addr,
+ size_t count);
+
+static void
+rmi_bus_space_read_region_1(void *t,
+ bus_space_handle_t bsh,
+ bus_size_t offset, u_int8_t *addr,
+ size_t count);
+
+static void
+rmi_bus_space_read_region_2(void *t,
+ bus_space_handle_t bsh,
+ bus_size_t offset, u_int16_t *addr,
+ size_t count);
+
+static void
+rmi_bus_space_read_region_4(void *t,
+ bus_space_handle_t bsh,
+ bus_size_t offset, u_int32_t *addr,
+ size_t count);
+
+static void
+rmi_bus_space_write_1(void *t,
+ bus_space_handle_t handle,
+ bus_size_t offset, u_int8_t value);
+
+static void
+rmi_bus_space_write_2(void *t,
+ bus_space_handle_t handle,
+ bus_size_t offset, u_int16_t value);
+
+static void
+rmi_bus_space_write_4(void *t,
+ bus_space_handle_t handle,
+ bus_size_t offset, u_int32_t value);
+
+static void
+rmi_bus_space_write_multi_1(void *t,
+ bus_space_handle_t handle,
+ bus_size_t offset,
+ const u_int8_t *addr,
+ size_t count);
+
+static void
+rmi_bus_space_write_multi_2(void *t,
+ bus_space_handle_t handle,
+ bus_size_t offset,
+ const u_int16_t *addr,
+ size_t count);
+
+static void
+rmi_bus_space_write_multi_4(void *t,
+ bus_space_handle_t handle,
+ bus_size_t offset,
+ const u_int32_t *addr,
+ size_t count);
+
+static void
+rmi_bus_space_write_region_2(void *t,
+ bus_space_handle_t bsh,
+ bus_size_t offset,
+ const u_int16_t *addr,
+ size_t count);
+
+static void
+rmi_bus_space_write_region_4(void *t,
+ bus_space_handle_t bsh,
+ bus_size_t offset,
+ const u_int32_t *addr,
+ size_t count);
+
+
+static void
+rmi_bus_space_set_region_2(void *t,
+ bus_space_handle_t bsh,
+ bus_size_t offset, u_int16_t value,
+ size_t count);
+static void
+rmi_bus_space_set_region_4(void *t,
+ bus_space_handle_t bsh,
+ bus_size_t offset, u_int32_t value,
+ size_t count);
+
+static void
+rmi_bus_space_barrier(void *tag __unused, bus_space_handle_t bsh __unused,
+ bus_size_t offset __unused, bus_size_t len __unused, int flags);
+
+static void
+rmi_bus_space_copy_region_2(void *t,
+ bus_space_handle_t bsh1,
+ bus_size_t off1,
+ bus_space_handle_t bsh2,
+ bus_size_t off2, size_t count);
+
+u_int8_t
+rmi_bus_space_read_stream_1(void *t, bus_space_handle_t handle,
+ bus_size_t offset);
+
+static u_int16_t
+rmi_bus_space_read_stream_2(void *t, bus_space_handle_t handle,
+ bus_size_t offset);
+
+static u_int32_t
+rmi_bus_space_read_stream_4(void *t, bus_space_handle_t handle,
+ bus_size_t offset);
+static void
+rmi_bus_space_read_multi_stream_1(void *t,
+ bus_space_handle_t handle,
+ bus_size_t offset, u_int8_t *addr,
+ size_t count);
+
+static void
+rmi_bus_space_read_multi_stream_2(void *t,
+ bus_space_handle_t handle,
+ bus_size_t offset, u_int16_t *addr,
+ size_t count);
+
+static void
+rmi_bus_space_read_multi_stream_4(void *t,
+ bus_space_handle_t handle,
+ bus_size_t offset, u_int32_t *addr,
+ size_t count);
+
+void
+rmi_bus_space_write_stream_1(void *t, bus_space_handle_t bsh,
+ bus_size_t offset, u_int8_t value);
+static void
+rmi_bus_space_write_stream_2(void *t, bus_space_handle_t handle,
+ bus_size_t offset, u_int16_t value);
+
+static void
+rmi_bus_space_write_stream_4(void *t, bus_space_handle_t handle,
+ bus_size_t offset, u_int32_t value);
+
+static void
+rmi_bus_space_write_multi_stream_1(void *t,
+ bus_space_handle_t handle,
+ bus_size_t offset,
+ const u_int8_t *addr,
+ size_t count);
+static void
+rmi_bus_space_write_multi_stream_2(void *t,
+ bus_space_handle_t handle,
+ bus_size_t offset,
+ const u_int16_t *addr,
+ size_t count);
+
+static void
+rmi_bus_space_write_multi_stream_4(void *t,
+ bus_space_handle_t handle,
+ bus_size_t offset,
+ const u_int32_t *addr,
+ size_t count);
+
+#define TODO() printf("XLP bus space: '%s' unimplemented\n", __func__)
+
+static struct bus_space local_rmi_bus_space = {
+ /* cookie */
+ (void *)0,
+
+ /* mapping/unmapping */
+ rmi_bus_space_map,
+ rmi_bus_space_unmap,
+ rmi_bus_space_subregion,
+
+ /* allocation/deallocation */
+ NULL,
+ NULL,
+
+ /* barrier */
+ rmi_bus_space_barrier,
+
+ /* read (single) */
+ rmi_bus_space_read_1,
+ rmi_bus_space_read_2,
+ rmi_bus_space_read_4,
+ NULL,
+
+ /* read multiple */
+ rmi_bus_space_read_multi_1,
+ rmi_bus_space_read_multi_2,
+ rmi_bus_space_read_multi_4,
+ NULL,
+
+ /* read region */
+ rmi_bus_space_read_region_1,
+ rmi_bus_space_read_region_2,
+ rmi_bus_space_read_region_4,
+ NULL,
+
+ /* write (single) */
+ rmi_bus_space_write_1,
+ rmi_bus_space_write_2,
+ rmi_bus_space_write_4,
+ NULL,
+
+ /* write multiple */
+ rmi_bus_space_write_multi_1,
+ rmi_bus_space_write_multi_2,
+ rmi_bus_space_write_multi_4,
+ NULL,
+
+ /* write region */
+ NULL,
+ rmi_bus_space_write_region_2,
+ rmi_bus_space_write_region_4,
+ NULL,
+
+ /* set multiple */
+ NULL,
+ NULL,
+ NULL,
+ NULL,
+
+ /* set region */
+ NULL,
+ rmi_bus_space_set_region_2,
+ rmi_bus_space_set_region_4,
+ NULL,
+
+ /* copy */
+ NULL,
+ rmi_bus_space_copy_region_2,
+ NULL,
+ NULL,
+
+ /* read (single) stream */
+ rmi_bus_space_read_stream_1,
+ rmi_bus_space_read_stream_2,
+ rmi_bus_space_read_stream_4,
+ NULL,
+
+ /* read multiple stream */
+ rmi_bus_space_read_multi_stream_1,
+ rmi_bus_space_read_multi_stream_2,
+ rmi_bus_space_read_multi_stream_4,
+ NULL,
+
+ /* read region stream */
+ rmi_bus_space_read_region_1,
+ rmi_bus_space_read_region_2,
+ rmi_bus_space_read_region_4,
+ NULL,
+
+ /* write (single) stream */
+ rmi_bus_space_write_stream_1,
+ rmi_bus_space_write_stream_2,
+ rmi_bus_space_write_stream_4,
+ NULL,
+
+ /* write multiple stream */
+ rmi_bus_space_write_multi_stream_1,
+ rmi_bus_space_write_multi_stream_2,
+ rmi_bus_space_write_multi_stream_4,
+ NULL,
+
+ /* write region stream */
+ NULL,
+ rmi_bus_space_write_region_2,
+ rmi_bus_space_write_region_4,
+ NULL,
+};
+
+/* generic bus_space tag */
+bus_space_tag_t rmi_bus_space = &local_rmi_bus_space;
+
+/*
+ * Map a region of device bus space into CPU virtual address space.
+ */
+static int
+rmi_bus_space_map(void *t __unused, bus_addr_t addr,
+ bus_size_t size __unused, int flags __unused,
+ bus_space_handle_t *bshp)
+{
+
+ *bshp = MIPS_PHYS_TO_DIRECT_UNCACHED(addr);
+ return (0);
+}
+
+/*
+ * Unmap a region of device bus space.
+ */
+static void
+rmi_bus_space_unmap(void *t __unused, bus_space_handle_t bsh __unused,
+ bus_size_t size __unused)
+{
+}
+
+/*
+ * Get a new handle for a subregion of an already-mapped area of bus space.
+ */
+
+static int
+rmi_bus_space_subregion(void *t __unused, bus_space_handle_t bsh,
+ bus_size_t offset, bus_size_t size __unused,
+ bus_space_handle_t *nbshp)
+{
+ *nbshp = bsh + offset;
+ return (0);
+}
+
+/*
+ * Read a 1, 2, 4, or 8 byte quantity from bus space
+ * described by tag/handle/offset.
+ */
+
+static u_int8_t
+rmi_bus_space_read_1(void *tag, bus_space_handle_t handle,
+ bus_size_t offset)
+{
+ return (u_int8_t) (*(volatile u_int8_t *)(handle + offset));
+}
+
+static u_int16_t
+rmi_bus_space_read_2(void *tag, bus_space_handle_t handle,
+ bus_size_t offset)
+{
+ return (u_int16_t)(*(volatile u_int16_t *)(handle + offset));
+}
+
+static u_int32_t
+rmi_bus_space_read_4(void *tag, bus_space_handle_t handle,
+ bus_size_t offset)
+{
+ return (*(volatile u_int32_t *)(handle + offset));
+}
+
+
+/*
+ * Read `count' 1, 2, 4, or 8 byte quantities from bus space
+ * described by tag/handle/offset and copy into buffer provided.
+ */
+static void
+rmi_bus_space_read_multi_1(void *tag, bus_space_handle_t handle,
+ bus_size_t offset, u_int8_t *addr, size_t count)
+{
+ TODO();
+}
+
+static void
+rmi_bus_space_read_multi_2(void *tag, bus_space_handle_t handle,
+ bus_size_t offset, u_int16_t *addr, size_t count)
+{
+ TODO();
+}
+
+static void
+rmi_bus_space_read_multi_4(void *tag, bus_space_handle_t handle,
+ bus_size_t offset, u_int32_t *addr, size_t count)
+{
+ TODO();
+}
+
+/*
+ * Write the 1, 2, 4, or 8 byte value `value' to bus space
+ * described by tag/handle/offset.
+ */
+
+static void
+rmi_bus_space_write_1(void *tag, bus_space_handle_t handle,
+ bus_size_t offset, u_int8_t value)
+{
+ *(volatile u_int8_t *)(handle + offset) = value;
+}
+
+static void
+rmi_bus_space_write_2(void *tag, bus_space_handle_t handle,
+ bus_size_t offset, u_int16_t value)
+{
+ *(volatile u_int16_t *)(handle + offset) = value;
+}
+
+static void
+rmi_bus_space_write_4(void *tag, bus_space_handle_t handle,
+ bus_size_t offset, u_int32_t value)
+{
+ *(volatile u_int32_t *)(handle + offset) = value;
+}
+
+
+/*
+ * Write `count' 1, 2, 4, or 8 byte quantities from the buffer
+ * provided to bus space described by tag/handle/offset.
+ */
+
+
+static void
+rmi_bus_space_write_multi_1(void *tag, bus_space_handle_t handle,
+ bus_size_t offset, const u_int8_t *addr, size_t count)
+{
+ TODO();
+}
+
+static void
+rmi_bus_space_write_multi_2(void *tag, bus_space_handle_t handle,
+ bus_size_t offset, const u_int16_t *addr, size_t count)
+{
+ TODO();
+}
+
+static void
+rmi_bus_space_write_multi_4(void *tag, bus_space_handle_t handle,
+ bus_size_t offset, const u_int32_t *addr, size_t count)
+{
+ TODO();
+}
+
+/*
+ * Write `count' 1, 2, 4, or 8 byte value `val' to bus space described
+ * by tag/handle starting at `offset'.
+ */
+
+static void
+rmi_bus_space_set_region_2(void *t, bus_space_handle_t bsh,
+ bus_size_t offset, u_int16_t value, size_t count)
+{
+ bus_addr_t addr = bsh + offset;
+
+ for (; count != 0; count--, addr += 2)
+ (*(volatile u_int32_t *)(addr)) = value;
+}
+
+static void
+rmi_bus_space_set_region_4(void *t, bus_space_handle_t bsh,
+ bus_size_t offset, u_int32_t value, size_t count)
+{
+ bus_addr_t addr = bsh + offset;
+
+ for (; count != 0; count--, addr += 4)
+ (*(volatile u_int32_t *)(addr)) = value;
+}
+
+
+/*
+ * Copy `count' 1, 2, 4, or 8 byte values from bus space starting
+ * at tag/bsh1/off1 to bus space starting at tag/bsh2/off2.
+ */
+static void
+rmi_bus_space_copy_region_2(void *t, bus_space_handle_t bsh1,
+ bus_size_t off1, bus_space_handle_t bsh2,
+ bus_size_t off2, size_t count)
+{
+ printf("bus_space_copy_region_2 - unimplemented\n");
+}
+
+/*
+ * Read `count' 1, 2, 4, or 8 byte quantities from bus space
+ * described by tag/handle/offset and copy into buffer provided.
+ */
+
+u_int8_t
+rmi_bus_space_read_stream_1(void *t, bus_space_handle_t handle,
+ bus_size_t offset)
+{
+
+ return *((volatile u_int8_t *)(handle + offset));
+}
+
+
+static u_int16_t
+rmi_bus_space_read_stream_2(void *t, bus_space_handle_t handle,
+ bus_size_t offset)
+{
+ return *(volatile u_int16_t *)(handle + offset);
+}
+
+
+static u_int32_t
+rmi_bus_space_read_stream_4(void *t, bus_space_handle_t handle,
+ bus_size_t offset)
+{
+ return (*(volatile u_int32_t *)(handle + offset));
+}
+
+
+static void
+rmi_bus_space_read_multi_stream_1(void *tag, bus_space_handle_t handle,
+ bus_size_t offset, u_int8_t *addr, size_t count)
+{
+ TODO();
+}
+
+static void
+rmi_bus_space_read_multi_stream_2(void *tag, bus_space_handle_t handle,
+ bus_size_t offset, u_int16_t *addr, size_t count)
+{
+ TODO();
+}
+
+static void
+rmi_bus_space_read_multi_stream_4(void *tag, bus_space_handle_t handle,
+ bus_size_t offset, u_int32_t *addr, size_t count)
+{
+ TODO();
+}
+
+
+/*
+ * Read `count' 1, 2, 4, or 8 byte quantities from bus space
+ * described by tag/handle and starting at `offset' and copy into
+ * buffer provided.
+ */
+void
+rmi_bus_space_read_region_1(void *t, bus_space_handle_t bsh,
+ bus_size_t offset, u_int8_t *addr, size_t count)
+{
+ TODO();
+}
+
+void
+rmi_bus_space_read_region_2(void *t, bus_space_handle_t bsh,
+ bus_size_t offset, u_int16_t *addr, size_t count)
+{
+ TODO();
+}
+
+void
+rmi_bus_space_read_region_4(void *t, bus_space_handle_t bsh,
+ bus_size_t offset, u_int32_t *addr, size_t count)
+{
+ bus_addr_t baddr = bsh + offset;
+
+ while (count--) {
+ *addr++ = (*(volatile u_int32_t *)(baddr));
+ baddr += 4;
+ }
+}
+
+void
+rmi_bus_space_write_stream_1(void *t, bus_space_handle_t handle,
+ bus_size_t offset, u_int8_t value)
+{
+ TODO();
+}
+
+
+static void
+rmi_bus_space_write_stream_2(void *t, bus_space_handle_t handle,
+ bus_size_t offset, u_int16_t value)
+{
+ TODO();
+}
+
+
+static void
+rmi_bus_space_write_stream_4(void *t, bus_space_handle_t handle,
+ bus_size_t offset, u_int32_t value)
+{
+ TODO();
+}
+
+
+static void
+rmi_bus_space_write_multi_stream_1(void *tag, bus_space_handle_t handle,
+ bus_size_t offset, const u_int8_t *addr, size_t count)
+{
+ TODO();
+}
+
+static void
+rmi_bus_space_write_multi_stream_2(void *tag, bus_space_handle_t handle,
+ bus_size_t offset, const u_int16_t *addr, size_t count)
+{
+ TODO();
+}
+
+static void
+rmi_bus_space_write_multi_stream_4(void *tag, bus_space_handle_t handle,
+ bus_size_t offset, const u_int32_t *addr, size_t count)
+{
+ TODO();
+}
+
+void
+rmi_bus_space_write_region_2(void *t,
+ bus_space_handle_t bsh,
+ bus_size_t offset,
+ const u_int16_t *addr,
+ size_t count)
+{
+ TODO();
+}
+
+void
+rmi_bus_space_write_region_4(void *t, bus_space_handle_t bsh,
+ bus_size_t offset, const u_int32_t *addr, size_t count)
+{
+ TODO();
+}
+
+static void
+rmi_bus_space_barrier(void *tag __unused, bus_space_handle_t bsh __unused,
+ bus_size_t offset __unused, bus_size_t len __unused, int flags)
+{
+}
+
+/*
+ * need a special bus space for this, because the Netlogic SoC
+ * UART allows only 32 bit access to its registers
+ */
+
+static u_int8_t
+rmi_uart_bus_space_read_1(void *tag, bus_space_handle_t handle,
+ bus_size_t offset)
+{
+ return (u_int8_t)(*(volatile u_int32_t *)(handle + offset));
+}
+
+static void
+rmi_uart_bus_space_write_1(void *tag, bus_space_handle_t handle,
+ bus_size_t offset, u_int8_t value)
+{
+ *(volatile u_int32_t *)(handle + offset) = value;
+}
+
+static struct bus_space local_rmi_uart_bus_space = {
+ /* cookie */
+ (void *)0,
+
+ /* mapping/unmapping */
+ rmi_bus_space_map,
+ rmi_bus_space_unmap,
+ rmi_bus_space_subregion,
+
+ /* allocation/deallocation */
+ NULL,
+ NULL,
+
+ /* barrier */
+ rmi_bus_space_barrier,
+
+ /* read (single) */
+ rmi_uart_bus_space_read_1, NULL, NULL, NULL,
+
+ /* read multiple */
+ NULL, NULL, NULL, NULL,
+
+ /* read region */
+ NULL, NULL, NULL, NULL,
+
+ /* write (single) */
+ rmi_uart_bus_space_write_1, NULL, NULL, NULL,
+
+ /* write multiple */
+ NULL, NULL, NULL, NULL,
+
+ /* write region */
+ NULL, NULL, NULL, NULL,
+
+ /* set multiple */
+ NULL, NULL, NULL, NULL,
+
+ /* set region */
+ NULL, NULL, NULL, NULL,
+
+ /* copy */
+ NULL, NULL, NULL, NULL,
+
+ /* read (single) stream */
+ NULL, NULL, NULL, NULL,
+
+ /* read multiple stream */
+ NULL, NULL, NULL, NULL,
+
+ /* read region stream */
+ NULL, NULL, NULL, NULL,
+
+ /* write (single) stream */
+ NULL, NULL, NULL, NULL,
+
+ /* write multiple stream */
+ NULL, NULL, NULL, NULL,
+
+ /* write region stream */
+ NULL, NULL, NULL, NULL,
+};
+
+/* generic bus_space tag */
+bus_space_tag_t rmi_uart_bus_space = &local_rmi_uart_bus_space;
Property changes on: trunk/sys/mips/nlm/bus_space_rmi.c
___________________________________________________________________
Added: svn:eol-style
## -0,0 +1 ##
+native
\ No newline at end of property
Added: svn:keywords
## -0,0 +1 ##
+MidnightBSD=%H
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+text/plain
\ No newline at end of property
Added: trunk/sys/mips/nlm/bus_space_rmi_pci.c
===================================================================
--- trunk/sys/mips/nlm/bus_space_rmi_pci.c (rev 0)
+++ trunk/sys/mips/nlm/bus_space_rmi_pci.c 2018-05-26 21:55:02 UTC (rev 9987)
@@ -0,0 +1,769 @@
+/* $MidnightBSD$ */
+/*-
+ * Copyright 2003-2011 Netlogic Microsystems (Netlogic). All rights
+ * reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in
+ * the documentation and/or other materials provided with the
+ * distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY Netlogic Microsystems ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL NETLOGIC OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
+ * THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * NETLOGIC_BSD */
+
+#include <sys/cdefs.h>
+__FBSDID("$FreeBSD: stable/10/sys/mips/nlm/bus_space_rmi_pci.c 225394 2011-09-05 10:45:29Z jchandra $");
+
+#include <sys/param.h>
+#include <sys/systm.h>
+#include <sys/bus.h>
+#include <sys/kernel.h>
+#include <sys/endian.h>
+#include <sys/malloc.h>
+#include <sys/ktr.h>
+
+#include <vm/vm.h>
+#include <vm/pmap.h>
+#include <vm/vm_kern.h>
+#include <vm/vm_extern.h>
+
+#include <machine/bus.h>
+#include <machine/cache.h>
+
+static int
+rmi_pci_bus_space_map(void *t, bus_addr_t addr,
+ bus_size_t size, int flags,
+ bus_space_handle_t * bshp);
+
+static void
+rmi_pci_bus_space_unmap(void *t, bus_space_handle_t bsh,
+ bus_size_t size);
+
+static int
+rmi_pci_bus_space_subregion(void *t,
+ bus_space_handle_t bsh,
+ bus_size_t offset, bus_size_t size,
+ bus_space_handle_t * nbshp);
+
+static u_int8_t
+rmi_pci_bus_space_read_1(void *t,
+ bus_space_handle_t handle,
+ bus_size_t offset);
+
+static u_int16_t
+rmi_pci_bus_space_read_2(void *t,
+ bus_space_handle_t handle,
+ bus_size_t offset);
+
+static u_int32_t
+rmi_pci_bus_space_read_4(void *t,
+ bus_space_handle_t handle,
+ bus_size_t offset);
+
+static void
+rmi_pci_bus_space_read_multi_1(void *t,
+ bus_space_handle_t handle,
+ bus_size_t offset, u_int8_t * addr,
+ size_t count);
+
+static void
+rmi_pci_bus_space_read_multi_2(void *t,
+ bus_space_handle_t handle,
+ bus_size_t offset, u_int16_t * addr,
+ size_t count);
+
+static void
+rmi_pci_bus_space_read_multi_4(void *t,
+ bus_space_handle_t handle,
+ bus_size_t offset, u_int32_t * addr,
+ size_t count);
+
+static void
+rmi_pci_bus_space_read_region_1(void *t,
+ bus_space_handle_t bsh,
+ bus_size_t offset, u_int8_t * addr,
+ size_t count);
+
+static void
+rmi_pci_bus_space_read_region_2(void *t,
+ bus_space_handle_t bsh,
+ bus_size_t offset, u_int16_t * addr,
+ size_t count);
+
+static void
+rmi_pci_bus_space_read_region_4(void *t,
+ bus_space_handle_t bsh,
+ bus_size_t offset, u_int32_t * addr,
+ size_t count);
+
+static void
+rmi_pci_bus_space_write_1(void *t,
+ bus_space_handle_t handle,
+ bus_size_t offset, u_int8_t value);
+
+static void
+rmi_pci_bus_space_write_2(void *t,
+ bus_space_handle_t handle,
+ bus_size_t offset, u_int16_t value);
+
+static void
+rmi_pci_bus_space_write_4(void *t,
+ bus_space_handle_t handle,
+ bus_size_t offset, u_int32_t value);
+
+static void
+rmi_pci_bus_space_write_multi_1(void *t,
+ bus_space_handle_t handle,
+ bus_size_t offset,
+ const u_int8_t * addr,
+ size_t count);
+
+static void
+rmi_pci_bus_space_write_multi_2(void *t,
+ bus_space_handle_t handle,
+ bus_size_t offset,
+ const u_int16_t * addr,
+ size_t count);
+
+static void
+rmi_pci_bus_space_write_multi_4(void *t,
+ bus_space_handle_t handle,
+ bus_size_t offset,
+ const u_int32_t * addr,
+ size_t count);
+
+static void
+rmi_pci_bus_space_write_region_2(void *t,
+ bus_space_handle_t bsh,
+ bus_size_t offset,
+ const u_int16_t * addr,
+ size_t count);
+
+static void
+rmi_pci_bus_space_write_region_4(void *t,
+ bus_space_handle_t bsh,
+ bus_size_t offset,
+ const u_int32_t * addr,
+ size_t count);
+
+
+static void
+rmi_pci_bus_space_set_region_2(void *t,
+ bus_space_handle_t bsh,
+ bus_size_t offset, u_int16_t value,
+ size_t count);
+static void
+rmi_pci_bus_space_set_region_4(void *t,
+ bus_space_handle_t bsh,
+ bus_size_t offset, u_int32_t value,
+ size_t count);
+
+static void
+rmi_pci_bus_space_barrier(void *tag __unused, bus_space_handle_t bsh __unused,
+ bus_size_t offset __unused, bus_size_t len __unused, int flags);
+
+static void
+rmi_pci_bus_space_copy_region_2(void *t,
+ bus_space_handle_t bsh1,
+ bus_size_t off1,
+ bus_space_handle_t bsh2,
+ bus_size_t off2, size_t count);
+
+u_int8_t
+rmi_pci_bus_space_read_stream_1(void *t, bus_space_handle_t handle,
+ bus_size_t offset);
+
+static u_int16_t
+rmi_pci_bus_space_read_stream_2(void *t, bus_space_handle_t handle,
+ bus_size_t offset);
+
+static u_int32_t
+rmi_pci_bus_space_read_stream_4(void *t, bus_space_handle_t handle,
+ bus_size_t offset);
+static void
+rmi_pci_bus_space_read_multi_stream_1(void *t,
+ bus_space_handle_t handle,
+ bus_size_t offset, u_int8_t * addr,
+ size_t count);
+
+static void
+rmi_pci_bus_space_read_multi_stream_2(void *t,
+ bus_space_handle_t handle,
+ bus_size_t offset, u_int16_t * addr,
+ size_t count);
+
+static void
+rmi_pci_bus_space_read_multi_stream_4(void *t,
+ bus_space_handle_t handle,
+ bus_size_t offset, u_int32_t * addr,
+ size_t count);
+
+void
+rmi_pci_bus_space_write_stream_1(void *t, bus_space_handle_t bsh,
+ bus_size_t offset, u_int8_t value);
+static void
+rmi_pci_bus_space_write_stream_2(void *t, bus_space_handle_t handle,
+ bus_size_t offset, u_int16_t value);
+
+static void
+rmi_pci_bus_space_write_stream_4(void *t, bus_space_handle_t handle,
+ bus_size_t offset, u_int32_t value);
+
+static void
+rmi_pci_bus_space_write_multi_stream_1(void *t,
+ bus_space_handle_t handle,
+ bus_size_t offset,
+ const u_int8_t * addr,
+ size_t count);
+static void
+rmi_pci_bus_space_write_multi_stream_2(void *t,
+ bus_space_handle_t handle,
+ bus_size_t offset,
+ const u_int16_t * addr,
+ size_t count);
+
+static void
+rmi_pci_bus_space_write_multi_stream_4(void *t,
+ bus_space_handle_t handle,
+ bus_size_t offset,
+ const u_int32_t * addr,
+ size_t count);
+
+#define TODO() printf("XLR memory bus space function '%s' unimplemented\n", __func__)
+
+static struct bus_space local_rmi_pci_bus_space = {
+ /* cookie */
+ (void *)0,
+
+ /* mapping/unmapping */
+ rmi_pci_bus_space_map,
+ rmi_pci_bus_space_unmap,
+ rmi_pci_bus_space_subregion,
+
+ /* allocation/deallocation */
+ NULL,
+ NULL,
+
+ /* barrier */
+ rmi_pci_bus_space_barrier,
+
+ /* read (single) */
+ rmi_pci_bus_space_read_1,
+ rmi_pci_bus_space_read_2,
+ rmi_pci_bus_space_read_4,
+ NULL,
+
+ /* read multiple */
+ rmi_pci_bus_space_read_multi_1,
+ rmi_pci_bus_space_read_multi_2,
+ rmi_pci_bus_space_read_multi_4,
+ NULL,
+
+ /* read region */
+ rmi_pci_bus_space_read_region_1,
+ rmi_pci_bus_space_read_region_2,
+ rmi_pci_bus_space_read_region_4,
+ NULL,
+
+ /* write (single) */
+ rmi_pci_bus_space_write_1,
+ rmi_pci_bus_space_write_2,
+ rmi_pci_bus_space_write_4,
+ NULL,
+
+ /* write multiple */
+ rmi_pci_bus_space_write_multi_1,
+ rmi_pci_bus_space_write_multi_2,
+ rmi_pci_bus_space_write_multi_4,
+ NULL,
+
+ /* write region */
+ NULL,
+ rmi_pci_bus_space_write_region_2,
+ rmi_pci_bus_space_write_region_4,
+ NULL,
+
+ /* set multiple */
+ NULL,
+ NULL,
+ NULL,
+ NULL,
+
+ /* set region */
+ NULL,
+ rmi_pci_bus_space_set_region_2,
+ rmi_pci_bus_space_set_region_4,
+ NULL,
+
+ /* copy */
+ NULL,
+ rmi_pci_bus_space_copy_region_2,
+ NULL,
+ NULL,
+
+ /* read (single) stream */
+ rmi_pci_bus_space_read_stream_1,
+ rmi_pci_bus_space_read_stream_2,
+ rmi_pci_bus_space_read_stream_4,
+ NULL,
+
+ /* read multiple stream */
+ rmi_pci_bus_space_read_multi_stream_1,
+ rmi_pci_bus_space_read_multi_stream_2,
+ rmi_pci_bus_space_read_multi_stream_4,
+ NULL,
+
+ /* read region stream */
+ rmi_pci_bus_space_read_region_1,
+ rmi_pci_bus_space_read_region_2,
+ rmi_pci_bus_space_read_region_4,
+ NULL,
+
+ /* write (single) stream */
+ rmi_pci_bus_space_write_stream_1,
+ rmi_pci_bus_space_write_stream_2,
+ rmi_pci_bus_space_write_stream_4,
+ NULL,
+
+ /* write multiple stream */
+ rmi_pci_bus_space_write_multi_stream_1,
+ rmi_pci_bus_space_write_multi_stream_2,
+ rmi_pci_bus_space_write_multi_stream_4,
+ NULL,
+
+ /* write region stream */
+ NULL,
+ rmi_pci_bus_space_write_region_2,
+ rmi_pci_bus_space_write_region_4,
+ NULL,
+};
+
+/* generic bus_space tag */
+bus_space_tag_t rmi_pci_bus_space = &local_rmi_pci_bus_space;
+
+/*
+ * Map a region of device bus space into CPU virtual address space.
+ */
+static int
+rmi_pci_bus_space_map(void *t __unused, bus_addr_t addr,
+ bus_size_t size __unused, int flags __unused,
+ bus_space_handle_t * bshp)
+{
+ *bshp = addr;
+ return (0);
+}
+
+/*
+ * Unmap a region of device bus space.
+ */
+static void
+rmi_pci_bus_space_unmap(void *t __unused, bus_space_handle_t bsh __unused,
+ bus_size_t size __unused)
+{
+}
+
+/*
+ * Get a new handle for a subregion of an already-mapped area of bus space.
+ */
+
+static int
+rmi_pci_bus_space_subregion(void *t __unused, bus_space_handle_t bsh,
+ bus_size_t offset, bus_size_t size __unused,
+ bus_space_handle_t * nbshp)
+{
+ *nbshp = bsh + offset;
+ return (0);
+}
+
+/*
+ * Read a 1, 2, 4, or 8 byte quantity from bus space
+ * described by tag/handle/offset.
+ */
+
+static u_int8_t
+rmi_pci_bus_space_read_1(void *tag, bus_space_handle_t handle,
+ bus_size_t offset)
+{
+ return (u_int8_t) (*(volatile u_int8_t *)(handle + offset));
+}
+
+static u_int16_t
+rmi_pci_bus_space_read_2(void *tag, bus_space_handle_t handle,
+ bus_size_t offset)
+{
+ u_int16_t value;
+
+ value = *(volatile u_int16_t *)(handle + offset);
+ return bswap16(value);
+}
+
+static u_int32_t
+rmi_pci_bus_space_read_4(void *tag, bus_space_handle_t handle,
+ bus_size_t offset)
+{
+ uint32_t value;
+
+ value = *(volatile u_int32_t *)(handle + offset);
+ return bswap32(value);
+}
+
+/*
+ * Read `count' 1, 2, 4, or 8 byte quantities from bus space
+ * described by tag/handle/offset and copy into buffer provided.
+ */
+static void
+rmi_pci_bus_space_read_multi_1(void *tag, bus_space_handle_t handle,
+ bus_size_t offset, u_int8_t * addr, size_t count)
+{
+ while (count--) {
+ *addr = *(volatile u_int8_t *)(handle + offset);
+ addr++;
+ }
+}
+
+static void
+rmi_pci_bus_space_read_multi_2(void *tag, bus_space_handle_t handle,
+ bus_size_t offset, u_int16_t * addr, size_t count)
+{
+
+ while (count--) {
+ *addr = *(volatile u_int16_t *)(handle + offset);
+ *addr = bswap16(*addr);
+ addr++;
+ }
+}
+
+static void
+rmi_pci_bus_space_read_multi_4(void *tag, bus_space_handle_t handle,
+ bus_size_t offset, u_int32_t * addr, size_t count)
+{
+
+ while (count--) {
+ *addr = *(volatile u_int32_t *)(handle + offset);
+ *addr = bswap32(*addr);
+ addr++;
+ }
+}
+
+/*
+ * Write the 1, 2, 4, or 8 byte value `value' to bus space
+ * described by tag/handle/offset.
+ */
+
+static void
+rmi_pci_bus_space_write_1(void *tag, bus_space_handle_t handle,
+ bus_size_t offset, u_int8_t value)
+{
+ mips_sync();
+ *(volatile u_int8_t *)(handle + offset) = value;
+}
+
+static void
+rmi_pci_bus_space_write_2(void *tag, bus_space_handle_t handle,
+ bus_size_t offset, u_int16_t value)
+{
+ mips_sync();
+ *(volatile u_int16_t *)(handle + offset) = bswap16(value);
+}
+
+
+static void
+rmi_pci_bus_space_write_4(void *tag, bus_space_handle_t handle,
+ bus_size_t offset, u_int32_t value)
+{
+ mips_sync();
+ *(volatile u_int32_t *)(handle + offset) = bswap32(value);
+}
+
+/*
+ * Write `count' 1, 2, 4, or 8 byte quantities from the buffer
+ * provided to bus space described by tag/handle/offset.
+ */
+
+
+static void
+rmi_pci_bus_space_write_multi_1(void *tag, bus_space_handle_t handle,
+ bus_size_t offset, const u_int8_t * addr, size_t count)
+{
+ mips_sync();
+ while (count--) {
+ (*(volatile u_int8_t *)(handle + offset)) = *addr;
+ addr++;
+ }
+}
+
+static void
+rmi_pci_bus_space_write_multi_2(void *tag, bus_space_handle_t handle,
+ bus_size_t offset, const u_int16_t * addr, size_t count)
+{
+ mips_sync();
+ while (count--) {
+ (*(volatile u_int16_t *)(handle + offset)) = bswap16(*addr);
+ addr++;
+ }
+}
+
+static void
+rmi_pci_bus_space_write_multi_4(void *tag, bus_space_handle_t handle,
+ bus_size_t offset, const u_int32_t * addr, size_t count)
+{
+ mips_sync();
+ while (count--) {
+ (*(volatile u_int32_t *)(handle + offset)) = bswap32(*addr);
+ addr++;
+ }
+}
+
+/*
+ * Write `count' 1, 2, 4, or 8 byte value `val' to bus space described
+ * by tag/handle starting at `offset'.
+ */
+
+static void
+rmi_pci_bus_space_set_region_2(void *t, bus_space_handle_t bsh,
+ bus_size_t offset, u_int16_t value, size_t count)
+{
+ bus_addr_t addr = bsh + offset;
+
+ for (; count != 0; count--, addr += 2)
+ (*(volatile u_int16_t *)(addr)) = value;
+}
+
+static void
+rmi_pci_bus_space_set_region_4(void *t, bus_space_handle_t bsh,
+ bus_size_t offset, u_int32_t value, size_t count)
+{
+ bus_addr_t addr = bsh + offset;
+
+ for (; count != 0; count--, addr += 4)
+ (*(volatile u_int32_t *)(addr)) = value;
+}
+
+
+/*
+ * Copy `count' 1, 2, 4, or 8 byte values from bus space starting
+ * at tag/bsh1/off1 to bus space starting at tag/bsh2/off2.
+ */
+static void
+rmi_pci_bus_space_copy_region_2(void *t, bus_space_handle_t bsh1,
+ bus_size_t off1, bus_space_handle_t bsh2,
+ bus_size_t off2, size_t count)
+{
+ TODO();
+}
+
+/*
+ * Read `count' 1, 2, 4, or 8 byte quantities from bus space
+ * described by tag/handle/offset and copy into buffer provided.
+ */
+
+u_int8_t
+rmi_pci_bus_space_read_stream_1(void *t, bus_space_handle_t handle,
+ bus_size_t offset)
+{
+
+ return *((volatile u_int8_t *)(handle + offset));
+}
+
+
+static u_int16_t
+rmi_pci_bus_space_read_stream_2(void *t, bus_space_handle_t handle,
+ bus_size_t offset)
+{
+ return *(volatile u_int16_t *)(handle + offset);
+}
+
+
+static u_int32_t
+rmi_pci_bus_space_read_stream_4(void *t, bus_space_handle_t handle,
+ bus_size_t offset)
+{
+ return (*(volatile u_int32_t *)(handle + offset));
+}
+
+
+static void
+rmi_pci_bus_space_read_multi_stream_1(void *tag, bus_space_handle_t handle,
+ bus_size_t offset, u_int8_t * addr, size_t count)
+{
+ while (count--) {
+ *addr = (*(volatile u_int8_t *)(handle + offset));
+ addr++;
+ }
+}
+
+static void
+rmi_pci_bus_space_read_multi_stream_2(void *tag, bus_space_handle_t handle,
+ bus_size_t offset, u_int16_t * addr, size_t count)
+{
+ while (count--) {
+ *addr = (*(volatile u_int16_t *)(handle + offset));
+ addr++;
+ }
+}
+
+static void
+rmi_pci_bus_space_read_multi_stream_4(void *tag, bus_space_handle_t handle,
+ bus_size_t offset, u_int32_t * addr, size_t count)
+{
+ while (count--) {
+ *addr = (*(volatile u_int32_t *)(handle + offset));
+ addr++;
+ }
+}
+
+
+
+/*
+ * Read `count' 1, 2, 4, or 8 byte quantities from bus space
+ * described by tag/handle and starting at `offset' and copy into
+ * buffer provided.
+ */
+void
+rmi_pci_bus_space_read_region_1(void *t, bus_space_handle_t bsh,
+ bus_size_t offset, u_int8_t * addr, size_t count)
+{
+ bus_addr_t baddr = bsh + offset;
+
+ while (count--) {
+ *addr++ = (*(volatile u_int8_t *)(baddr));
+ baddr += 1;
+ }
+}
+
+void
+rmi_pci_bus_space_read_region_2(void *t, bus_space_handle_t bsh,
+ bus_size_t offset, u_int16_t * addr, size_t count)
+{
+ bus_addr_t baddr = bsh + offset;
+
+ while (count--) {
+ *addr++ = (*(volatile u_int16_t *)(baddr));
+ baddr += 2;
+ }
+}
+
+void
+rmi_pci_bus_space_read_region_4(void *t, bus_space_handle_t bsh,
+ bus_size_t offset, u_int32_t * addr, size_t count)
+{
+ bus_addr_t baddr = bsh + offset;
+
+ while (count--) {
+ *addr++ = (*(volatile u_int32_t *)(baddr));
+ baddr += 4;
+ }
+}
+
+
+void
+rmi_pci_bus_space_write_stream_1(void *t, bus_space_handle_t handle,
+ bus_size_t offset, u_int8_t value)
+{
+ mips_sync();
+ *(volatile u_int8_t *)(handle + offset) = value;
+}
+
+static void
+rmi_pci_bus_space_write_stream_2(void *t, bus_space_handle_t handle,
+ bus_size_t offset, u_int16_t value)
+{
+ mips_sync();
+ *(volatile u_int16_t *)(handle + offset) = value;
+}
+
+
+static void
+rmi_pci_bus_space_write_stream_4(void *t, bus_space_handle_t handle,
+ bus_size_t offset, u_int32_t value)
+{
+ mips_sync();
+ *(volatile u_int32_t *)(handle + offset) = value;
+}
+
+
+static void
+rmi_pci_bus_space_write_multi_stream_1(void *tag, bus_space_handle_t handle,
+ bus_size_t offset, const u_int8_t * addr, size_t count)
+{
+ mips_sync();
+ while (count--) {
+ (*(volatile u_int8_t *)(handle + offset)) = *addr;
+ addr++;
+ }
+}
+
+static void
+rmi_pci_bus_space_write_multi_stream_2(void *tag, bus_space_handle_t handle,
+ bus_size_t offset, const u_int16_t * addr, size_t count)
+{
+ mips_sync();
+ while (count--) {
+ (*(volatile u_int16_t *)(handle + offset)) = *addr;
+ addr++;
+ }
+}
+
+static void
+rmi_pci_bus_space_write_multi_stream_4(void *tag, bus_space_handle_t handle,
+ bus_size_t offset, const u_int32_t * addr, size_t count)
+{
+ mips_sync();
+ while (count--) {
+ (*(volatile u_int32_t *)(handle + offset)) = *addr;
+ addr++;
+ }
+}
+
+void
+rmi_pci_bus_space_write_region_2(void *t,
+ bus_space_handle_t bsh,
+ bus_size_t offset,
+ const u_int16_t * addr,
+ size_t count)
+{
+ bus_addr_t baddr = (bus_addr_t) bsh + offset;
+
+ while (count--) {
+ (*(volatile u_int16_t *)(baddr)) = *addr;
+ addr++;
+ baddr += 2;
+ }
+}
+
+void
+rmi_pci_bus_space_write_region_4(void *t, bus_space_handle_t bsh,
+ bus_size_t offset, const u_int32_t * addr, size_t count)
+{
+ bus_addr_t baddr = bsh + offset;
+
+ while (count--) {
+ (*(volatile u_int32_t *)(baddr)) = *addr;
+ addr++;
+ baddr += 4;
+ }
+}
+
+static void
+rmi_pci_bus_space_barrier(void *tag __unused, bus_space_handle_t bsh __unused,
+ bus_size_t offset __unused, bus_size_t len __unused, int flags)
+{
+
+}
Property changes on: trunk/sys/mips/nlm/bus_space_rmi_pci.c
___________________________________________________________________
Added: svn:eol-style
## -0,0 +1 ##
+native
\ No newline at end of property
Added: svn:keywords
## -0,0 +1 ##
+MidnightBSD=%H
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+text/plain
\ No newline at end of property
Added: trunk/sys/mips/nlm/clock.h
===================================================================
--- trunk/sys/mips/nlm/clock.h (rev 0)
+++ trunk/sys/mips/nlm/clock.h 2018-05-26 21:55:02 UTC (rev 9987)
@@ -0,0 +1,43 @@
+/* $MidnightBSD$ */
+/*-
+ * Copyright 2003-2011 Netlogic Microsystems (Netlogic). All rights
+ * reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in
+ * the documentation and/or other materials provided with the
+ * distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY Netlogic Microsystems ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL NETLOGIC OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
+ * THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * NETLOGIC_BSD
+ * $FreeBSD: stable/10/sys/mips/nlm/clock.h 225394 2011-09-05 10:45:29Z jchandra $
+ */
+
+#ifndef _RMI_CLOCK_H_
+#define _RMI_CLOCK_H_
+
+#define XLP_PIC_HZ 133000000U
+#define XLP_CPU_HZ (nlm_cpu_frequency)
+
+void count_compare_clockhandler(struct trapframe *);
+void pic_hardclockhandler(struct trapframe *);
+void pic_timecounthandler(struct trapframe *);
+
+#endif /* _RMI_CLOCK_H_ */
Property changes on: trunk/sys/mips/nlm/clock.h
___________________________________________________________________
Added: svn:eol-style
## -0,0 +1 ##
+native
\ No newline at end of property
Added: svn:keywords
## -0,0 +1 ##
+MidnightBSD=%H
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+text/plain
\ No newline at end of property
Added: trunk/sys/mips/nlm/cms.c
===================================================================
--- trunk/sys/mips/nlm/cms.c (rev 0)
+++ trunk/sys/mips/nlm/cms.c 2018-05-26 21:55:02 UTC (rev 9987)
@@ -0,0 +1,502 @@
+/* $MidnightBSD$ */
+/*-
+ * Copyright 2003-2011 Netlogic Microsystems (Netlogic). All rights
+ * reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in
+ * the documentation and/or other materials provided with the
+ * distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY Netlogic Microsystems ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL NETLOGIC OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
+ * THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * NETLOGIC_BSD */
+
+#include <sys/cdefs.h>
+__FBSDID("$FreeBSD: stable/10/sys/mips/nlm/cms.c 233534 2012-03-27 07:47:13Z jchandra $");
+#include <sys/types.h>
+#include <sys/systm.h>
+#include <sys/param.h>
+#include <sys/lock.h>
+#include <sys/mutex.h>
+#include <sys/proc.h>
+#include <sys/limits.h>
+#include <sys/bus.h>
+
+#include <sys/ktr.h>
+#include <sys/kernel.h>
+#include <sys/kthread.h>
+#include <sys/proc.h>
+#include <sys/resourcevar.h>
+#include <sys/sched.h>
+#include <sys/unistd.h>
+#include <sys/sysctl.h>
+#include <sys/malloc.h>
+
+#include <machine/reg.h>
+#include <machine/cpu.h>
+#include <machine/hwfunc.h>
+#include <machine/mips_opcode.h>
+#include <machine/param.h>
+#include <machine/intr_machdep.h>
+
+#include <mips/nlm/hal/mips-extns.h>
+#include <mips/nlm/hal/haldefs.h>
+#include <mips/nlm/hal/iomap.h>
+#include <mips/nlm/hal/cop2.h>
+#include <mips/nlm/hal/fmn.h>
+#include <mips/nlm/hal/pic.h>
+
+#include <mips/nlm/msgring.h>
+#include <mips/nlm/interrupt.h>
+#include <mips/nlm/xlp.h>
+
+#define MSGRNG_NSTATIONS 1024
+/*
+ * Keep track of our message ring handler threads, each core has a
+ * different message station. Ideally we will need to start a few
+ * message handling threads every core, and wake them up depending on
+ * load
+ */
+struct msgring_thread {
+ struct thread *thread; /* msgring handler threads */
+ int needed; /* thread needs to wake up */
+};
+static struct msgring_thread msgring_threads[XLP_MAX_CORES * XLP_MAX_THREADS];
+static struct proc *msgring_proc; /* all threads are under a proc */
+
+/*
+ * The device drivers can register a handler for the messages sent
+ * from a station (corresponding to the device).
+ */
+struct tx_stn_handler {
+ msgring_handler action;
+ void *arg;
+};
+static struct tx_stn_handler msgmap[MSGRNG_NSTATIONS];
+static struct mtx msgmap_lock;
+uint32_t xlp_msg_thread_mask;
+static int xlp_msg_threads_per_core = XLP_MAX_THREADS;
+
+static void create_msgring_thread(int hwtid);
+static int msgring_process_fast_intr(void *arg);
+
+/* Debug counters */
+static int msgring_nintr[XLP_MAX_CORES * XLP_MAX_THREADS];
+static int msgring_wakeup_sleep[XLP_MAX_CORES * XLP_MAX_THREADS];
+static int msgring_wakeup_nosleep[XLP_MAX_CORES * XLP_MAX_THREADS];
+static int fmn_msgcount[XLP_MAX_CORES * XLP_MAX_THREADS][4];
+static int fmn_loops[XLP_MAX_CORES * XLP_MAX_THREADS];
+
+/* Whether polled driver implementation */
+static int polled = 0;
+
+/* We do only i/o device credit setup here. CPU credit setup is now
+ * moved to xlp_msgring_cpu_init() so that the credits get setup
+ * only if the CPU exists. xlp_msgring_cpu_init() gets called from
+ * platform_init_ap; and this makes it easy for us to setup CMS
+ * credits for various types of XLP chips, with varying number of
+ * cpu's and cores.
+ */
+static void
+xlp_cms_credit_setup(int credit)
+{
+ uint64_t cmspcibase, cmsbase, pcibase;
+ uint32_t devoffset;
+ int dev, fn, maxqid;
+ int src, qid, i;
+
+ for (i = 0; i < XLP_MAX_NODES; i++) {
+ cmspcibase = nlm_get_cms_pcibase(i);
+ if (!nlm_dev_exists(XLP_IO_CMS_OFFSET(i)))
+ continue;
+ cmsbase = nlm_get_cms_regbase(i);
+ maxqid = nlm_read_reg(cmspcibase, XLP_PCI_DEVINFO_REG0);
+ for (dev = 0; dev < 8; dev++) {
+ for (fn = 0; fn < 8; fn++) {
+ devoffset = XLP_HDR_OFFSET(i, 0, dev, fn);
+ if (nlm_dev_exists(devoffset) == 0)
+ continue;
+ pcibase = nlm_pcicfg_base(devoffset);
+ src = nlm_qidstart(pcibase);
+ if (src == 0)
+ continue;
+#if 0 /* Debug */
+ printf("Setup CMS credits for queues ");
+ printf("[%d to %d] from src %d\n", 0,
+ maxqid, src);
+#endif
+ for (qid = 0; qid < maxqid; qid++)
+ nlm_cms_setup_credits(cmsbase, qid,
+ src, credit);
+ }
+ }
+ }
+}
+
+void
+xlp_msgring_cpu_init(int node, int cpu, int credit)
+{
+ uint64_t cmspcibase = nlm_get_cms_pcibase(node);
+ uint64_t cmsbase = nlm_get_cms_regbase(node);
+ int qid, maxqid, src;
+
+ maxqid = nlm_read_reg(cmspcibase, XLP_PCI_DEVINFO_REG0);
+
+ /* cpu credit setup is done only from thread-0 of each core */
+ if((cpu % 4) == 0) {
+ src = cpu << 2; /* each thread has 4 vc's */
+ for (qid = 0; qid < maxqid; qid++)
+ nlm_cms_setup_credits(cmsbase, qid, src, credit);
+ }
+}
+
+/*
+ * Drain out max_messages for the buckets set in the bucket mask.
+ * Use max_msgs = 0 to drain out all messages.
+ */
+int
+xlp_handle_msg_vc(u_int vcmask, int max_msgs)
+{
+ struct nlm_fmn_msg msg;
+ int srcid = 0, size = 0, code = 0;
+ struct tx_stn_handler *he;
+ uint32_t mflags, status;
+ int n_msgs = 0, vc, m, hwtid;
+ u_int msgmask;
+
+ hwtid = nlm_cpuid();
+ for (;;) {
+ /* check if VC empty */
+ mflags = nlm_save_flags_cop2();
+ status = nlm_read_c2_msgstatus1();
+ nlm_restore_flags(mflags);
+
+ msgmask = ((status >> 24) & 0xf) ^ 0xf;
+ msgmask &= vcmask;
+ if (msgmask == 0)
+ break;
+ m = 0;
+ for (vc = 0; vc < 4; vc++) {
+ if ((msgmask & (1 << vc)) == 0)
+ continue;
+
+ mflags = nlm_save_flags_cop2();
+ status = nlm_fmn_msgrcv(vc, &srcid, &size, &code,
+ &msg);
+ nlm_restore_flags(mflags);
+ if (status != 0) /* no msg or error */
+ continue;
+ if (srcid < 0 && srcid >= 1024) {
+ printf("[%s]: bad src id %d\n", __func__,
+ srcid);
+ continue;
+ }
+ he = &msgmap[srcid];
+ if(he->action != NULL)
+ (he->action)(vc, size, code, srcid, &msg,
+ he->arg);
+#if 0
+ else
+ printf("[%s]: No Handler for msg from stn %d,"
+ " vc=%d, size=%d, msg0=%jx, droppinge\n",
+ __func__, srcid, vc, size,
+ (uintmax_t)msg.msg[0]);
+#endif
+ fmn_msgcount[hwtid][vc] += 1;
+ m++; /* msgs handled in this iter */
+ }
+ if (m == 0)
+ break; /* nothing done in this iter */
+ n_msgs += m;
+ if (max_msgs > 0 && n_msgs >= max_msgs)
+ break;
+ }
+
+ return (n_msgs);
+}
+
+static void
+xlp_discard_msg_vc(u_int vcmask)
+{
+ struct nlm_fmn_msg msg;
+ int srcid = 0, size = 0, code = 0, vc;
+ uint32_t mflags, status;
+
+ for (vc = 0; vc < 4; vc++) {
+ for (;;) {
+ mflags = nlm_save_flags_cop2();
+ status = nlm_fmn_msgrcv(vc, &srcid,
+ &size, &code, &msg);
+ nlm_restore_flags(mflags);
+
+ /* break if there is no msg or error */
+ if (status != 0)
+ break;
+ }
+ }
+}
+
+void
+xlp_cms_enable_intr(int node, int cpu, int type, int watermark)
+{
+ uint64_t cmsbase;
+ int i, qid;
+
+ cmsbase = nlm_get_cms_regbase(node);
+
+ for (i = 0; i < 4; i++) {
+ qid = (i + (cpu * 4)) & 0x7f;
+ nlm_cms_per_queue_level_intr(cmsbase, qid, type, watermark);
+ nlm_cms_per_queue_timer_intr(cmsbase, qid, 0x1, 0);
+ }
+}
+
+static int
+msgring_process_fast_intr(void *arg)
+{
+ struct msgring_thread *mthd;
+ struct thread *td;
+ int cpu;
+
+ cpu = nlm_cpuid();
+ mthd = &msgring_threads[cpu];
+ msgring_nintr[cpu]++;
+ td = mthd->thread;
+
+ /* clear pending interrupts */
+ nlm_write_c0_eirr(1ULL << IRQ_MSGRING);
+
+ /* wake up the target thread */
+ mthd->needed = 1;
+ thread_lock(td);
+ if (TD_AWAITING_INTR(td)) {
+ msgring_wakeup_sleep[cpu]++;
+ TD_CLR_IWAIT(td);
+ sched_add(td, SRQ_INTR);
+ } else
+ msgring_wakeup_nosleep[cpu]++;
+
+ thread_unlock(td);
+
+ return (FILTER_HANDLED);
+}
+
+static void
+msgring_process(void * arg)
+{
+ volatile struct msgring_thread *mthd;
+ struct thread *td;
+ uint32_t mflags, msgstatus1;
+ int hwtid, nmsgs;
+
+ hwtid = (intptr_t)arg;
+ mthd = &msgring_threads[hwtid];
+ td = mthd->thread;
+ KASSERT(curthread == td,
+ ("%s:msg_ithread and proc linkage out of sync", __func__));
+
+ /* First bind this thread to the right CPU */
+ thread_lock(td);
+ sched_bind(td, xlp_hwtid_to_cpuid[hwtid]);
+ thread_unlock(td);
+
+ if (hwtid != nlm_cpuid())
+ printf("Misscheduled hwtid %d != cpuid %d\n", hwtid,
+ nlm_cpuid());
+
+ xlp_discard_msg_vc(0xf);
+ xlp_msgring_cpu_init(nlm_nodeid(), nlm_cpuid(), CMS_DEFAULT_CREDIT);
+ if (polled == 0) {
+ mflags = nlm_save_flags_cop2();
+ nlm_fmn_cpu_init(IRQ_MSGRING, 0, 0, 0, 0, 0);
+ nlm_restore_flags(mflags);
+ xlp_cms_enable_intr(nlm_nodeid(), nlm_cpuid(), 0x2, 0);
+ /* clear pending interrupts.
+ * they will get re-raised if still valid */
+ nlm_write_c0_eirr(1ULL << IRQ_MSGRING);
+ }
+
+ /* start processing messages */
+ for (;;) {
+ atomic_store_rel_int(&mthd->needed, 0);
+ nmsgs = xlp_handle_msg_vc(0xf, 0);
+
+ /* sleep */
+ if (polled == 0) {
+ /* clear VC-pend bits */
+ mflags = nlm_save_flags_cop2();
+ msgstatus1 = nlm_read_c2_msgstatus1();
+ msgstatus1 |= (0xf << 16);
+ nlm_write_c2_msgstatus1(msgstatus1);
+ nlm_restore_flags(mflags);
+
+ thread_lock(td);
+ if (mthd->needed) {
+ thread_unlock(td);
+ continue;
+ }
+ sched_class(td, PRI_ITHD);
+ TD_SET_IWAIT(td);
+ mi_switch(SW_VOL, NULL);
+ thread_unlock(td);
+ } else
+ pause("wmsg", 1);
+
+ fmn_loops[hwtid]++;
+ }
+}
+
+static void
+create_msgring_thread(int hwtid)
+{
+ struct msgring_thread *mthd;
+ struct thread *td;
+ int error;
+
+ mthd = &msgring_threads[hwtid];
+ error = kproc_kthread_add(msgring_process, (void *)(uintptr_t)hwtid,
+ &msgring_proc, &td, RFSTOPPED, 2, "msgrngproc",
+ "msgthr%d", hwtid);
+ if (error)
+ panic("kproc_kthread_add() failed with %d", error);
+ mthd->thread = td;
+
+ thread_lock(td);
+ sched_class(td, PRI_ITHD);
+ sched_add(td, SRQ_INTR);
+ thread_unlock(td);
+}
+
+int
+register_msgring_handler(int startb, int endb, msgring_handler action,
+ void *arg)
+{
+ int i;
+
+ if (bootverbose)
+ printf("Register handler %d-%d %p(%p)\n",
+ startb, endb, action, arg);
+ KASSERT(startb >= 0 && startb <= endb && endb < MSGRNG_NSTATIONS,
+ ("Invalid value for bucket range %d,%d", startb, endb));
+
+ mtx_lock_spin(&msgmap_lock);
+ for (i = startb; i <= endb; i++) {
+ KASSERT(msgmap[i].action == NULL,
+ ("Bucket %d already used [action %p]", i, msgmap[i].action));
+ msgmap[i].action = action;
+ msgmap[i].arg = arg;
+ }
+ mtx_unlock_spin(&msgmap_lock);
+ return (0);
+}
+
+/*
+ * Initialize the messaging subsystem.
+ *
+ * Message Stations are shared among all threads in a cpu core, this
+ * has to be called once from every core which is online.
+ */
+static void
+xlp_msgring_config(void *arg)
+{
+ void *cookie;
+ unsigned int thrmask, mask;
+ int i;
+
+ /* used polled handler for Ax silion */
+ if (nlm_is_xlp8xx_ax())
+ polled = 1;
+
+ /* Don't poll on all threads, if polled */
+ if (polled)
+ xlp_msg_threads_per_core -= 1;
+
+ mtx_init(&msgmap_lock, "msgring", NULL, MTX_SPIN);
+ if (xlp_threads_per_core < xlp_msg_threads_per_core)
+ xlp_msg_threads_per_core = xlp_threads_per_core;
+ thrmask = ((1 << xlp_msg_threads_per_core) - 1);
+ mask = 0;
+ for (i = 0; i < XLP_MAX_CORES; i++) {
+ mask <<= XLP_MAX_THREADS;
+ mask |= thrmask;
+ }
+ xlp_msg_thread_mask = xlp_hw_thread_mask & mask;
+#if 0
+ printf("CMS Message handler thread mask %#jx\n",
+ (uintmax_t)xlp_msg_thread_mask);
+#endif
+ xlp_cms_credit_setup(CMS_DEFAULT_CREDIT);
+ create_msgring_thread(0);
+ cpu_establish_hardintr("msgring", msgring_process_fast_intr, NULL,
+ NULL, IRQ_MSGRING, INTR_TYPE_NET, &cookie);
+}
+
+/*
+ * Start message ring processing threads on other CPUs, after SMP start
+ */
+static void
+start_msgring_threads(void *arg)
+{
+ int hwt;
+
+ for (hwt = 1; hwt < XLP_MAX_CORES * XLP_MAX_THREADS; hwt++) {
+ if ((xlp_msg_thread_mask & (1 << hwt)) == 0)
+ continue;
+ create_msgring_thread(hwt);
+ }
+}
+
+SYSINIT(xlp_msgring_config, SI_SUB_DRIVERS, SI_ORDER_FIRST,
+ xlp_msgring_config, NULL);
+SYSINIT(start_msgring_threads, SI_SUB_SMP, SI_ORDER_MIDDLE,
+ start_msgring_threads, NULL);
+
+/*
+ * DEBUG support, XXX: static buffer, not locked
+ */
+static int
+sys_print_debug(SYSCTL_HANDLER_ARGS)
+{
+ int error, nb, i, fs;
+ static char xprintb[4096], *buf;
+
+ buf = xprintb;
+ fs = sizeof(xprintb);
+ nb = snprintf(buf, fs,
+ "\nID vc0 vc1 vc2 vc3 loops\n");
+ buf += nb;
+ fs -= nb;
+ for (i = 0; i < 32; i++) {
+ if ((xlp_hw_thread_mask & (1 << i)) == 0)
+ continue;
+ nb = snprintf(buf, fs,
+ "%2d: %8d %8d %8d %8d %8d\n", i,
+ fmn_msgcount[i][0], fmn_msgcount[i][1],
+ fmn_msgcount[i][2], fmn_msgcount[i][3],
+ fmn_loops[i]);
+ buf += nb;
+ fs -= nb;
+ }
+ error = SYSCTL_OUT(req, xprintb, buf - xprintb);
+ return (error);
+}
+
+SYSCTL_PROC(_debug, OID_AUTO, msgring, CTLTYPE_STRING | CTLFLAG_RD, 0, 0,
+ sys_print_debug, "A", "msgring debug info");
Property changes on: trunk/sys/mips/nlm/cms.c
___________________________________________________________________
Added: svn:eol-style
## -0,0 +1 ##
+native
\ No newline at end of property
Added: svn:keywords
## -0,0 +1 ##
+MidnightBSD=%H
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## -0,0 +1 ##
+text/plain
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Added: trunk/sys/mips/nlm/dev/cfi_pci_xlp.c
===================================================================
--- trunk/sys/mips/nlm/dev/cfi_pci_xlp.c (rev 0)
+++ trunk/sys/mips/nlm/dev/cfi_pci_xlp.c 2018-05-26 21:55:02 UTC (rev 9987)
@@ -0,0 +1,78 @@
+/* $MidnightBSD$ */
+/*-
+ * Copyright (c) 2003-2012 Broadcom Corporation
+ * All Rights Reserved
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in
+ * the documentation and/or other materials provided with the
+ * distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY BROADCOM ``AS IS'' AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL BROADCOM OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
+ * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
+ * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
+ * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <sys/cdefs.h>
+__FBSDID("$FreeBSD: stable/10/sys/mips/nlm/dev/cfi_pci_xlp.c 233556 2012-03-27 15:16:38Z jchandra $");
+
+#include <sys/param.h>
+#include <sys/systm.h>
+#include <sys/bus.h>
+#include <sys/conf.h>
+#include <sys/kernel.h>
+#include <sys/module.h>
+#include <machine/bus.h>
+#include <sys/rman.h>
+#include <machine/resource.h>
+
+#include <dev/pci/pcivar.h>
+
+#include <dev/cfi/cfi_var.h>
+
+#include <mips/nlm/hal/haldefs.h>
+#include <mips/nlm/hal/iomap.h>
+
+static int cfi_xlp_probe(device_t dev);
+
+static device_method_t cfi_xlp_methods[] = {
+ /* Device interface */
+ DEVMETHOD(device_probe, cfi_xlp_probe),
+ DEVMETHOD(device_attach, cfi_attach),
+ DEVMETHOD(device_detach, cfi_detach),
+ DEVMETHOD_END
+};
+
+static driver_t cfi_xlp_driver = {
+ cfi_driver_name,
+ cfi_xlp_methods,
+ sizeof(struct cfi_softc),
+};
+
+static int
+cfi_xlp_probe(device_t dev)
+{
+
+ if (pci_get_vendor(dev) != PCI_VENDOR_NETLOGIC ||
+ pci_get_device(dev) != PCI_DEVICE_ID_NLM_NOR)
+ return (ENXIO);
+
+ device_set_desc(dev, "Netlogic XLP NOR Bus");
+ return (cfi_probe(dev));
+}
+
+DRIVER_MODULE(cfi_xlp, pci, cfi_xlp_driver, cfi_devclass, 0, 0);
Property changes on: trunk/sys/mips/nlm/dev/cfi_pci_xlp.c
___________________________________________________________________
Added: svn:eol-style
## -0,0 +1 ##
+native
\ No newline at end of property
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## -0,0 +1 ##
+MidnightBSD=%H
\ No newline at end of property
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## -0,0 +1 ##
+text/plain
\ No newline at end of property
Added: trunk/sys/mips/nlm/dev/net/mdio.c
===================================================================
--- trunk/sys/mips/nlm/dev/net/mdio.c (rev 0)
+++ trunk/sys/mips/nlm/dev/net/mdio.c 2018-05-26 21:55:02 UTC (rev 9987)
@@ -0,0 +1,334 @@
+/* $MidnightBSD$ */
+/*-
+ * Copyright (c) 2003-2012 Broadcom Corporation
+ * All Rights Reserved
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in
+ * the documentation and/or other materials provided with the
+ * distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY BROADCOM ``AS IS'' AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL BROADCOM OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
+ * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
+ * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
+ * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <sys/cdefs.h>
+__FBSDID("$FreeBSD: stable/10/sys/mips/nlm/dev/net/mdio.c 245881 2013-01-24 15:14:22Z jchandra $");
+#include <sys/types.h>
+#include <sys/systm.h>
+
+#include <mips/nlm/hal/mips-extns.h>
+#include <mips/nlm/hal/haldefs.h>
+#include <mips/nlm/hal/iomap.h>
+#include <mips/nlm/hal/sys.h>
+#include <mips/nlm/hal/nae.h>
+#include <mips/nlm/hal/mdio.h>
+
+#include <mips/nlm/xlp.h>
+
+/* Internal MDIO READ/WRITE Routines */
+int
+nlm_int_gmac_mdio_read(uint64_t nae_base, int bus, int block,
+ int intf_type, int phyaddr, int regidx)
+{
+ uint32_t mdio_ld_cmd;
+ uint32_t ctrlval;
+
+ ctrlval = INT_MDIO_CTRL_SMP |
+ (phyaddr << INT_MDIO_CTRL_PHYADDR_POS) |
+ (regidx << INT_MDIO_CTRL_DEVTYPE_POS) |
+ (2 << INT_MDIO_CTRL_OP_POS) |
+ (1 << INT_MDIO_CTRL_ST_POS) |
+ (7 << INT_MDIO_CTRL_XDIV_POS) |
+ (2 << INT_MDIO_CTRL_TA_POS) |
+ (2 << INT_MDIO_CTRL_MIIM_POS) |
+ (1 << INT_MDIO_CTRL_MCDIV_POS);
+
+ mdio_ld_cmd = nlm_read_nae_reg(nae_base,
+ NAE_REG(block, intf_type, (INT_MDIO_CTRL + bus * 4)));
+ if (mdio_ld_cmd & INT_MDIO_CTRL_CMD_LOAD) {
+ nlm_write_nae_reg(nae_base,
+ NAE_REG(block, intf_type, (INT_MDIO_CTRL + bus*4)),
+ (mdio_ld_cmd & ~INT_MDIO_CTRL_CMD_LOAD));
+ }
+
+ nlm_write_nae_reg(nae_base,
+ NAE_REG(block, intf_type, (INT_MDIO_CTRL + bus * 4)),
+ ctrlval);
+
+ /* Toggle Load Cmd Bit */
+ nlm_write_nae_reg(nae_base,
+ NAE_REG(block, intf_type, (INT_MDIO_CTRL + bus * 4)),
+ ctrlval | (1 << INT_MDIO_CTRL_LOAD_POS));
+
+ /* poll master busy bit until it is not busy */
+ while(nlm_read_nae_reg(nae_base,
+ NAE_REG(block, intf_type, (INT_MDIO_RD_STAT + bus * 4))) &
+ INT_MDIO_STAT_MBSY) {
+ }
+
+ nlm_write_nae_reg(nae_base,
+ NAE_REG(block, intf_type, (INT_MDIO_CTRL + bus * 4)),
+ ctrlval);
+
+ /* Read the data back */
+ return nlm_read_nae_reg(nae_base,
+ NAE_REG(block, intf_type, (INT_MDIO_RD_STAT + bus * 4)));
+}
+
+/* Internal MDIO WRITE Routines */
+int
+nlm_int_gmac_mdio_write(uint64_t nae_base, int bus, int block,
+ int intf_type, int phyaddr, int regidx, uint16_t val)
+{
+ uint32_t mdio_ld_cmd;
+ uint32_t ctrlval;
+
+ ctrlval = INT_MDIO_CTRL_SMP |
+ (phyaddr << INT_MDIO_CTRL_PHYADDR_POS) |
+ (regidx << INT_MDIO_CTRL_DEVTYPE_POS) |
+ (1 << INT_MDIO_CTRL_OP_POS) |
+ (1 << INT_MDIO_CTRL_ST_POS) |
+ (7 << INT_MDIO_CTRL_XDIV_POS) |
+ (2 << INT_MDIO_CTRL_TA_POS) |
+ (1 << INT_MDIO_CTRL_MIIM_POS) |
+ (1 << INT_MDIO_CTRL_MCDIV_POS);
+
+ mdio_ld_cmd = nlm_read_nae_reg(nae_base,
+ NAE_REG(block, intf_type, (INT_MDIO_CTRL + bus * 4)));
+ if (mdio_ld_cmd & INT_MDIO_CTRL_CMD_LOAD) {
+ nlm_write_nae_reg(nae_base,
+ NAE_REG(block, intf_type, (INT_MDIO_CTRL + bus*4)),
+ (mdio_ld_cmd & ~INT_MDIO_CTRL_CMD_LOAD));
+ }
+
+ /* load data into ctrl data reg */
+ nlm_write_nae_reg(nae_base,
+ NAE_REG(block, intf_type, (INT_MDIO_CTRL_DATA + bus * 4)),
+ val);
+
+ nlm_write_nae_reg(nae_base,
+ NAE_REG(block, intf_type, (INT_MDIO_CTRL + bus * 4)),
+ ctrlval);
+
+ nlm_write_nae_reg(nae_base,
+ NAE_REG(block, intf_type, (INT_MDIO_CTRL + bus * 4)),
+ ctrlval | (1 << INT_MDIO_CTRL_LOAD_POS));
+
+ /* poll master busy bit until it is not busy */
+ while(nlm_read_nae_reg(nae_base,
+ NAE_REG(block, intf_type, (INT_MDIO_RD_STAT + bus * 4))) &
+ INT_MDIO_STAT_MBSY) {
+ }
+
+ nlm_write_nae_reg(nae_base,
+ NAE_REG(block, intf_type, (INT_MDIO_CTRL + bus * 4)),
+ ctrlval);
+
+ return (0);
+}
+
+int
+nlm_int_gmac_mdio_reset(uint64_t nae_base, int bus, int block,
+ int intf_type)
+{
+ uint32_t val;
+
+ val = (7 << INT_MDIO_CTRL_XDIV_POS) |
+ (1 << INT_MDIO_CTRL_MCDIV_POS) |
+ (INT_MDIO_CTRL_SMP);
+
+ nlm_write_nae_reg(nae_base,
+ NAE_REG(block, intf_type, (INT_MDIO_CTRL + bus * 4)),
+ val | INT_MDIO_CTRL_RST);
+
+ nlm_write_nae_reg(nae_base,
+ NAE_REG(block, intf_type, (INT_MDIO_CTRL + bus * 4)),
+ val);
+
+ return (0);
+}
+
+/*
+ * nae_gmac_mdio_read - Read sgmii phy register
+ *
+ * Input parameters:
+ * bus - bus number, nae has two external gmac bus: 0 and 1
+ * phyaddr - PHY's address
+ * regidx - index of register to read
+ *
+ * Return value:
+ * value read (16 bits), or 0xffffffff if an error occurred.
+ */
+int
+nlm_gmac_mdio_read(uint64_t nae_base, int bus, int block,
+ int intf_type, int phyaddr, int regidx)
+{
+ uint32_t mdio_ld_cmd;
+ uint32_t ctrlval;
+
+ mdio_ld_cmd = nlm_read_nae_reg(nae_base, NAE_REG(block, intf_type,
+ (EXT_G0_MDIO_CTRL + bus * 4)));
+ if (mdio_ld_cmd & EXT_G_MDIO_CMD_LCD) {
+ nlm_write_nae_reg(nae_base,
+ NAE_REG(block, intf_type, (EXT_G0_MDIO_CTRL+bus*4)),
+ (mdio_ld_cmd & ~EXT_G_MDIO_CMD_LCD));
+ while(nlm_read_nae_reg(nae_base,
+ NAE_REG(block, intf_type,
+ (EXT_G0_MDIO_RD_STAT + bus * 4))) &
+ EXT_G_MDIO_STAT_MBSY);
+ }
+
+ ctrlval = EXT_G_MDIO_CMD_SP |
+ (phyaddr << EXT_G_MDIO_PHYADDR_POS) |
+ (regidx << EXT_G_MDIO_REGADDR_POS);
+ if (nlm_is_xlp8xx_ax() || nlm_is_xlp8xx_b0() || nlm_is_xlp3xx_ax())
+ ctrlval |= EXT_G_MDIO_DIV;
+ else
+ ctrlval |= EXT_G_MDIO_DIV_WITH_HW_DIV64;
+
+ nlm_write_nae_reg(nae_base,
+ NAE_REG(block, intf_type, (EXT_G0_MDIO_CTRL+bus*4)),
+ ctrlval);
+
+ nlm_write_nae_reg(nae_base,
+ NAE_REG(block, intf_type, (EXT_G0_MDIO_CTRL+bus*4)),
+ ctrlval | (1<<18));
+ DELAY(1000);
+ /* poll master busy bit until it is not busy */
+ while(nlm_read_nae_reg(nae_base,
+ NAE_REG(block, intf_type, (EXT_G0_MDIO_RD_STAT + bus * 4))) &
+ EXT_G_MDIO_STAT_MBSY);
+
+ nlm_write_nae_reg(nae_base,
+ NAE_REG(block, intf_type, (EXT_G0_MDIO_CTRL+bus*4)),
+ ctrlval);
+
+ /* Read the data back */
+ return nlm_read_nae_reg(nae_base,
+ NAE_REG(block, intf_type, (EXT_G0_MDIO_RD_STAT + bus * 4)));
+}
+
+/*
+ * nae_gmac_mdio_write -Write sgmac mii PHY register.
+ *
+ * Input parameters:
+ * bus - bus number, nae has two external gmac bus: 0 and 1
+ * phyaddr - PHY to use
+ * regidx - register within the PHY
+ * val - data to write to register
+ *
+ * Return value:
+ * 0 - success
+ */
+int
+nlm_gmac_mdio_write(uint64_t nae_base, int bus, int block,
+ int intf_type, int phyaddr, int regidx, uint16_t val)
+{
+ uint32_t mdio_ld_cmd;
+ uint32_t ctrlval;
+
+ mdio_ld_cmd = nlm_read_nae_reg(nae_base, NAE_REG(block, intf_type,
+ (EXT_G0_MDIO_CTRL + bus * 4)));
+ if (mdio_ld_cmd & EXT_G_MDIO_CMD_LCD) {
+ nlm_write_nae_reg(nae_base,
+ NAE_REG(block, intf_type, (EXT_G0_MDIO_CTRL+bus*4)),
+ (mdio_ld_cmd & ~EXT_G_MDIO_CMD_LCD));
+ while(nlm_read_nae_reg(nae_base,
+ NAE_REG(block, intf_type,
+ (EXT_G0_MDIO_RD_STAT + bus * 4))) &
+ EXT_G_MDIO_STAT_MBSY);
+ }
+
+ /* load data into ctrl data reg */
+ nlm_write_nae_reg(nae_base,
+ NAE_REG(block, intf_type, (EXT_G0_MDIO_CTRL_DATA+bus*4)),
+ val);
+
+ ctrlval = EXT_G_MDIO_CMD_SP |
+ (phyaddr << EXT_G_MDIO_PHYADDR_POS) |
+ (regidx << EXT_G_MDIO_REGADDR_POS);
+ if (nlm_is_xlp8xx_ax() || nlm_is_xlp8xx_b0() || nlm_is_xlp3xx_ax())
+ ctrlval |= EXT_G_MDIO_DIV;
+ else
+ ctrlval |= EXT_G_MDIO_DIV_WITH_HW_DIV64;
+
+ nlm_write_nae_reg(nae_base,
+ NAE_REG(block, intf_type, (EXT_G0_MDIO_CTRL+bus*4)),
+ ctrlval);
+
+ nlm_write_nae_reg(nae_base,
+ NAE_REG(block, intf_type, (EXT_G0_MDIO_CTRL+bus*4)),
+ ctrlval | EXT_G_MDIO_CMD_LCD);
+ DELAY(1000);
+
+ /* poll master busy bit until it is not busy */
+ while(nlm_read_nae_reg(nae_base,
+ NAE_REG(block, intf_type,
+ (EXT_G0_MDIO_RD_STAT + bus * 4))) & EXT_G_MDIO_STAT_MBSY);
+
+ nlm_write_nae_reg(nae_base,
+ NAE_REG(block, intf_type, (EXT_G0_MDIO_CTRL+bus*4)),
+ ctrlval);
+
+ return (0);
+}
+
+/*
+ * nae_gmac_mdio_reset -Reset sgmii mdio module.
+ *
+ * Input parameters:
+ * bus - bus number, nae has two external gmac bus: 0 and 1
+ *
+ * Return value:
+ * 0 - success
+ */
+int
+nlm_gmac_mdio_reset(uint64_t nae_base, int bus, int block,
+ int intf_type)
+{
+ uint32_t ctrlval;
+
+ ctrlval = nlm_read_nae_reg(nae_base,
+ NAE_REG(block, intf_type, (EXT_G0_MDIO_CTRL+bus*4)));
+
+ if (nlm_is_xlp8xx_ax() || nlm_is_xlp8xx_b0() || nlm_is_xlp3xx_ax())
+ ctrlval |= EXT_G_MDIO_DIV;
+ else
+ ctrlval |= EXT_G_MDIO_DIV_WITH_HW_DIV64;
+
+ nlm_write_nae_reg(nae_base,
+ NAE_REG(block, intf_type, (EXT_G0_MDIO_CTRL + bus * 4)),
+ EXT_G_MDIO_MMRST | ctrlval);
+ nlm_write_nae_reg(nae_base,
+ NAE_REG(block, intf_type, (EXT_G0_MDIO_CTRL + bus * 4)), ctrlval);
+ return (0);
+}
+
+/*
+ * nlm_mdio_reset_all : reset all internal and external MDIO
+ */
+void
+nlm_mdio_reset_all(uint64_t nae_base)
+{
+ /* reset internal MDIO */
+ nlm_int_gmac_mdio_reset(nae_base, 0, BLOCK_7, LANE_CFG);
+ /* reset external MDIO */
+ nlm_gmac_mdio_reset(nae_base, 0, BLOCK_7, LANE_CFG);
+ nlm_gmac_mdio_reset(nae_base, 1, BLOCK_7, LANE_CFG);
+}
Property changes on: trunk/sys/mips/nlm/dev/net/mdio.c
___________________________________________________________________
Added: svn:eol-style
## -0,0 +1 ##
+native
\ No newline at end of property
Added: svn:keywords
## -0,0 +1 ##
+MidnightBSD=%H
\ No newline at end of property
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## -0,0 +1 ##
+text/plain
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Added: trunk/sys/mips/nlm/dev/net/nae.c
===================================================================
--- trunk/sys/mips/nlm/dev/net/nae.c (rev 0)
+++ trunk/sys/mips/nlm/dev/net/nae.c 2018-05-26 21:55:02 UTC (rev 9987)
@@ -0,0 +1,1455 @@
+/* $MidnightBSD$ */
+/*-
+ * Copyright (c) 2003-2012 Broadcom Corporation
+ * All Rights Reserved
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in
+ * the documentation and/or other materials provided with the
+ * distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY BROADCOM ``AS IS'' AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL BROADCOM OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
+ * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
+ * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
+ * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <sys/cdefs.h>
+__FBSDID("$FreeBSD: stable/10/sys/mips/nlm/dev/net/nae.c 261455 2014-02-04 03:36:42Z eadler $");
+#include <sys/types.h>
+#include <sys/systm.h>
+
+#include <mips/nlm/hal/mips-extns.h>
+#include <mips/nlm/hal/haldefs.h>
+#include <mips/nlm/hal/iomap.h>
+#include <mips/nlm/hal/sys.h>
+#include <mips/nlm/hal/nae.h>
+#include <mips/nlm/hal/mdio.h>
+#include <mips/nlm/hal/sgmii.h>
+#include <mips/nlm/hal/xaui.h>
+
+#include <mips/nlm/board.h>
+#include <mips/nlm/xlp.h>
+
+void
+nlm_nae_flush_free_fifo(uint64_t nae_base, int nblocks)
+{
+ uint32_t data, fifo_mask;
+
+ fifo_mask = (1 << (4 * nblocks)) - 1;
+
+ nlm_write_nae_reg(nae_base, NAE_RX_FREE_FIFO_POP, fifo_mask);
+ do {
+ data = nlm_read_nae_reg(nae_base, NAE_RX_FREE_FIFO_POP);
+ } while (data != fifo_mask);
+
+ nlm_write_nae_reg(nae_base, NAE_RX_FREE_FIFO_POP, 0);
+}
+
+void
+nlm_program_nae_parser_seq_fifo(uint64_t nae_base, int maxports,
+ struct nae_port_config *cfg)
+{
+ uint32_t val;
+ int start = 0, size, i;
+
+ for (i = 0; i < maxports; i++) {
+ size = cfg[i].pseq_fifo_size;
+ val = (((size & 0x1fff) << 17) |
+ ((start & 0xfff) << 5) |
+ (i & 0x1f));
+ nlm_write_nae_reg(nae_base, NAE_PARSER_SEQ_FIFO_CFG, val);
+ start += size;
+ }
+}
+
+void
+nlm_setup_rx_cal_cfg(uint64_t nae_base, int total_num_ports,
+ struct nae_port_config *cfg)
+{
+ int rx_slots = 0, port;
+ int cal_len, cal = 0, last_free = 0;
+ uint32_t val;
+
+ for (port = 0; port < total_num_ports; port++) {
+ if (cfg[port].rx_slots_reqd)
+ rx_slots += cfg[port].rx_slots_reqd;
+ if (rx_slots > MAX_CAL_SLOTS) {
+ rx_slots = MAX_CAL_SLOTS;
+ break;
+ }
+ }
+
+ cal_len = rx_slots - 1;
+
+ do {
+ if (cal >= MAX_CAL_SLOTS)
+ break;
+ last_free = cal;
+ for (port = 0; port < total_num_ports; port++) {
+ if (cfg[port].rx_slots_reqd > 0) {
+ val = (cal_len << 16) | (port << 8) | cal;
+ nlm_write_nae_reg(nae_base,
+ NAE_RX_IF_SLOT_CAL, val);
+ cal++;
+ cfg[port].rx_slots_reqd--;
+ }
+ }
+ if (last_free == cal)
+ break;
+ } while (1);
+}
+
+void
+nlm_setup_tx_cal_cfg(uint64_t nae_base, int total_num_ports,
+ struct nae_port_config *cfg)
+{
+ int tx_slots = 0, port;
+ int cal = 0, last_free = 0;
+ uint32_t val;
+
+ for (port = 0; port < total_num_ports; port++) {
+ if (cfg[port].tx_slots_reqd)
+ tx_slots += cfg[port].tx_slots_reqd;
+ if (tx_slots > MAX_CAL_SLOTS) {
+ tx_slots = MAX_CAL_SLOTS;
+ break;
+ }
+ }
+
+ nlm_write_nae_reg(nae_base, NAE_EGR_NIOR_CAL_LEN_REG, tx_slots - 1);
+ do {
+ if (cal >= MAX_CAL_SLOTS)
+ break;
+ last_free = cal;
+ for (port = 0; port < total_num_ports; port++) {
+ if (cfg[port].tx_slots_reqd > 0) {
+ val = (port << 7) | (cal << 1) | 1;
+ nlm_write_nae_reg(nae_base,
+ NAE_EGR_NIOR_CRDT_CAL_PROG, val);
+ cal++;
+ cfg[port].tx_slots_reqd--;
+ }
+ }
+ if (last_free == cal)
+ break;
+ } while (1);
+}
+
+void
+nlm_deflate_frin_fifo_carving(uint64_t nae_base, int total_num_ports)
+{
+ const int minimum_size = 8;
+ uint32_t value;
+ int intf, start;
+
+ for (intf = 0; intf < total_num_ports; intf++) {
+ start = minimum_size * intf;
+ value = (minimum_size << 20) | (start << 8) | (intf);
+ nlm_write_nae_reg(nae_base, NAE_FREE_IN_FIFO_CFG, value);
+ }
+}
+
+void
+nlm_reset_nae(int node)
+{
+ uint64_t sysbase;
+ uint64_t nae_base;
+ uint64_t nae_pcibase;
+ uint32_t rx_config;
+ uint32_t bar0;
+ int reset_bit;
+
+ sysbase = nlm_get_sys_regbase(node);
+ nae_base = nlm_get_nae_regbase(node);
+ nae_pcibase = nlm_get_nae_pcibase(node);
+
+ bar0 = nlm_read_pci_reg(nae_pcibase, XLP_PCI_CFGREG4);
+
+#if BYTE_ORDER == LITTLE_ENDIAN
+ if (nlm_is_xlp8xx_ax()) {
+ uint8_t val;
+ /* membar fixup */
+ val = (bar0 >> 24) & 0xff;
+ bar0 = (val << 24) | (val << 16) | (val << 8) | val;
+ }
+#endif
+
+ if (nlm_is_xlp3xx())
+ reset_bit = 6;
+ else
+ reset_bit = 9;
+
+ /* Reset NAE */
+ nlm_write_sys_reg(sysbase, SYS_RESET, (1 << reset_bit));
+
+ /* XXXJC - 1s delay here may be too high */
+ DELAY(1000000);
+ nlm_write_sys_reg(sysbase, SYS_RESET, (0 << reset_bit));
+ DELAY(1000000);
+
+ rx_config = nlm_read_nae_reg(nae_base, NAE_RX_CONFIG);
+ nlm_write_pci_reg(nae_pcibase, XLP_PCI_CFGREG4, bar0);
+}
+
+void
+nlm_setup_poe_class_config(uint64_t nae_base, int max_poe_classes,
+ int num_contexts, int *poe_cl_tbl)
+{
+ uint32_t val;
+ int i, max_poe_class_ctxt_tbl_sz;
+
+ max_poe_class_ctxt_tbl_sz = num_contexts/max_poe_classes;
+ for (i = 0; i < max_poe_class_ctxt_tbl_sz; i++) {
+ val = (poe_cl_tbl[(i/max_poe_classes) & 0x7] << 8) | i;
+ nlm_write_nae_reg(nae_base, NAE_POE_CLASS_SETUP_CFG, val);
+ }
+}
+
+void
+nlm_setup_vfbid_mapping(uint64_t nae_base)
+{
+ uint32_t val;
+ int dest_vc, vfbid;
+
+ /* 127 is max vfbid */
+ for (vfbid = 127; vfbid >= 0; vfbid--) {
+ dest_vc = nlm_get_vfbid_mapping(vfbid);
+ if (dest_vc < 0)
+ continue;
+ val = (dest_vc << 16) | (vfbid << 4) | 1;
+ nlm_write_nae_reg(nae_base, NAE_VFBID_DESTMAP_CMD, val);
+ }
+}
+
+void
+nlm_setup_flow_crc_poly(uint64_t nae_base, uint32_t poly)
+{
+ nlm_write_nae_reg(nae_base, NAE_FLOW_CRC16_POLY_CFG, poly);
+}
+
+void
+nlm_setup_iface_fifo_cfg(uint64_t nae_base, int maxports,
+ struct nae_port_config *cfg)
+{
+ uint32_t reg;
+ int fifo_xoff_thresh = 12;
+ int i, size;
+ int cur_iface_start = 0;
+
+ for (i = 0; i < maxports; i++) {
+ size = cfg[i].iface_fifo_size;
+ reg = ((fifo_xoff_thresh << 25) |
+ ((size & 0x1ff) << 16) |
+ ((cur_iface_start & 0xff) << 8) |
+ (i & 0x1f));
+ nlm_write_nae_reg(nae_base, NAE_IFACE_FIFO_CFG, reg);
+ cur_iface_start += size;
+ }
+}
+
+void
+nlm_setup_rx_base_config(uint64_t nae_base, int maxports,
+ struct nae_port_config *cfg)
+{
+ int base = 0;
+ uint32_t val;
+ int i;
+ int id;
+
+ for (i = 0; i < (maxports/2); i++) {
+ id = 0x12 + i; /* RX_IF_BASE_CONFIG0 */
+
+ val = (base & 0x3ff);
+ base += cfg[(i * 2)].num_channels;
+
+ val |= ((base & 0x3ff) << 16);
+ base += cfg[(i * 2) + 1].num_channels;
+
+ nlm_write_nae_reg(nae_base, NAE_REG(7, 0, id), val);
+ }
+}
+
+void
+nlm_setup_rx_buf_config(uint64_t nae_base, int maxports,
+ struct nae_port_config *cfg)
+{
+ uint32_t val;
+ int i, sz, k;
+ int context = 0;
+ int base = 0;
+
+ for (i = 0; i < maxports; i++) {
+ if (cfg[i].type == UNKNOWN)
+ continue;
+ for (k = 0; k < cfg[i].num_channels; k++) {
+ /* write index (context num) */
+ nlm_write_nae_reg(nae_base, NAE_RXBUF_BASE_DPTH_ADDR,
+ (context+k));
+
+ /* write value (rx buf sizes) */
+ sz = cfg[i].rxbuf_size;
+ val = 0x80000000 | ((base << 2) & 0x3fff); /* base */
+ val |= (((sz << 2) & 0x3fff) << 16); /* size */
+
+ nlm_write_nae_reg(nae_base, NAE_RXBUF_BASE_DPTH, val);
+ nlm_write_nae_reg(nae_base, NAE_RXBUF_BASE_DPTH,
+ (0x7fffffff & val));
+ base += sz;
+ }
+ context += cfg[i].num_channels;
+ }
+}
+
+void
+nlm_setup_freein_fifo_cfg(uint64_t nae_base, struct nae_port_config *cfg)
+{
+ int size, i;
+ uint32_t reg;
+ int start = 0, maxbufpool;
+
+ if (nlm_is_xlp8xx())
+ maxbufpool = MAX_FREE_FIFO_POOL_8XX;
+ else
+ maxbufpool = MAX_FREE_FIFO_POOL_3XX;
+ for (i = 0; i < maxbufpool; i++) {
+ /* Each entry represents 2 descs; hence division by 2 */
+ size = (cfg[i].num_free_descs / 2);
+ if (size == 0)
+ size = 8;
+ reg = ((size & 0x3ff ) << 20) | /* fcSize */
+ ((start & 0x1ff) << 8) | /* fcStart */
+ (i & 0x1f);
+
+ nlm_write_nae_reg(nae_base, NAE_FREE_IN_FIFO_CFG, reg);
+ start += size;
+ }
+}
+
+/* XXX function name */
+int
+nlm_get_flow_mask(int num_ports)
+{
+ const int max_bits = 5; /* upto 32 ports */
+ int i;
+
+ /* Compute the number of bits to needed to
+ * represent all the ports */
+ for (i = 0; i < max_bits; i++) {
+ if (num_ports <= (2 << i))
+ return (i + 1);
+ }
+ return (max_bits);
+}
+
+void
+nlm_program_flow_cfg(uint64_t nae_base, int port,
+ uint32_t cur_flow_base, uint32_t flow_mask)
+{
+ uint32_t val;
+
+ val = (cur_flow_base << 16) | port;
+ val |= ((flow_mask & 0x1f) << 8);
+ nlm_write_nae_reg(nae_base, NAE_FLOW_BASEMASK_CFG, val);
+}
+
+void
+xlp_ax_nae_lane_reset_txpll(uint64_t nae_base, int block, int lane_ctrl,
+ int mode)
+{
+ uint32_t val = 0, saved_data;
+ int rext_sel = 0;
+
+ val = PHY_LANE_CTRL_RST |
+ PHY_LANE_CTRL_PWRDOWN |
+ (mode << PHY_LANE_CTRL_PHYMODE_POS);
+
+ /* set comma bypass for XAUI */
+ if (mode != PHYMODE_SGMII)
+ val |= PHY_LANE_CTRL_BPC_XAUI;
+
+ nlm_write_nae_reg(nae_base, NAE_REG(block, PHY, lane_ctrl), val);
+
+ if (lane_ctrl != 4) {
+ rext_sel = (1 << 23);
+ if (mode != PHYMODE_SGMII)
+ rext_sel |= PHY_LANE_CTRL_BPC_XAUI;
+
+ val = nlm_read_nae_reg(nae_base,
+ NAE_REG(block, PHY, lane_ctrl));
+ val &= ~PHY_LANE_CTRL_RST;
+ val |= rext_sel;
+
+ /* Resetting PMA for non-zero lanes */
+ nlm_write_nae_reg(nae_base,
+ NAE_REG(block, PHY, lane_ctrl), val);
+
+ DELAY(20000); /* 20 ms delay, XXXJC: needed? */
+
+ val |= PHY_LANE_CTRL_RST;
+ nlm_write_nae_reg(nae_base,
+ NAE_REG(block, PHY, lane_ctrl), val);
+
+ val = 0;
+ }
+
+ /* Come out of reset for TXPLL */
+ saved_data = nlm_read_nae_reg(nae_base,
+ NAE_REG(block, PHY, lane_ctrl)) & 0xFFC00000;
+
+ nlm_write_nae_reg(nae_base,
+ NAE_REG(block, PHY, lane_ctrl),
+ (0x66 << PHY_LANE_CTRL_ADDR_POS)
+ | PHY_LANE_CTRL_CMD_READ
+ | PHY_LANE_CTRL_CMD_START
+ | PHY_LANE_CTRL_RST
+ | rext_sel
+ | val );
+
+ while (((val = nlm_read_nae_reg(nae_base,
+ NAE_REG(block, PHY, lane_ctrl))) &
+ PHY_LANE_CTRL_CMD_PENDING));
+
+ val &= 0xFF;
+ /* set bit[4] to 0 */
+ val &= ~(1 << 4);
+ nlm_write_nae_reg(nae_base,
+ NAE_REG(block, PHY, lane_ctrl),
+ (0x66 << PHY_LANE_CTRL_ADDR_POS)
+ | PHY_LANE_CTRL_CMD_WRITE
+ | PHY_LANE_CTRL_CMD_START
+ | (0x0 << 19) /* (0x4 << 19) */
+ | rext_sel
+ | saved_data
+ | val );
+
+ /* re-do */
+ nlm_write_nae_reg(nae_base,
+ NAE_REG(block, PHY, lane_ctrl),
+ (0x66 << PHY_LANE_CTRL_ADDR_POS)
+ | PHY_LANE_CTRL_CMD_WRITE
+ | PHY_LANE_CTRL_CMD_START
+ | (0x0 << 19) /* (0x4 << 19) */
+ | rext_sel
+ | saved_data
+ | val );
+
+ while (!((val = nlm_read_nae_reg(nae_base,
+ NAE_REG(block, PHY, (lane_ctrl - PHY_LANE_0_CTRL)))) &
+ PHY_LANE_STAT_PCR));
+
+ /* Clear the Power Down bit */
+ val = nlm_read_nae_reg(nae_base, NAE_REG(block, PHY, lane_ctrl));
+ val &= ~((1 << 29) | (0x7ffff));
+ nlm_write_nae_reg(nae_base, NAE_REG(block, PHY, lane_ctrl),
+ (rext_sel | val));
+}
+
+void
+xlp_nae_lane_reset_txpll(uint64_t nae_base, int block, int lane_ctrl,
+ int mode)
+{
+ uint32_t val = 0;
+ int rext_sel = 0;
+
+ if (lane_ctrl != 4)
+ rext_sel = (1 << 23);
+
+ val = nlm_read_nae_reg(nae_base,
+ NAE_REG(block, PHY, lane_ctrl));
+
+ /* set comma bypass for XAUI */
+ if (mode != PHYMODE_SGMII)
+ val |= PHY_LANE_CTRL_BPC_XAUI;
+ val |= 0x100000;
+ val |= (mode << PHY_LANE_CTRL_PHYMODE_POS);
+ val &= ~(0x20000);
+ nlm_write_nae_reg(nae_base,
+ NAE_REG(block, PHY, lane_ctrl), val);
+
+ val = nlm_read_nae_reg(nae_base,
+ NAE_REG(block, PHY, lane_ctrl));
+ val |= 0x40000000;
+ nlm_write_nae_reg(nae_base,
+ NAE_REG(block, PHY, lane_ctrl), val);
+
+ /* clear the power down bit */
+ val = nlm_read_nae_reg(nae_base,
+ NAE_REG(block, PHY, lane_ctrl));
+ val &= ~( (1 << 29) | (0x7ffff));
+ nlm_write_nae_reg(nae_base,
+ NAE_REG(block, PHY, lane_ctrl), rext_sel | val);
+}
+
+void
+xlp_nae_config_lane_gmac(uint64_t nae_base, int cplx_mask)
+{
+ int block, lane_ctrl;
+ int cplx_lane_enable;
+ int lane_enable = 0;
+
+ cplx_lane_enable = LM_SGMII |
+ (LM_SGMII << 4) |
+ (LM_SGMII << 8) |
+ (LM_SGMII << 12);
+
+ /* Lane mode progamming */
+ block = 7;
+
+ /* Complexes 0, 1 */
+ if (cplx_mask & 0x1)
+ lane_enable |= cplx_lane_enable;
+
+ if (cplx_mask & 0x2)
+ lane_enable |= (cplx_lane_enable << 16);
+
+ if (lane_enable) {
+ nlm_write_nae_reg(nae_base,
+ NAE_REG(block, LANE_CFG, LANE_CFG_CPLX_0_1),
+ lane_enable);
+ lane_enable = 0;
+ }
+ /* Complexes 2 3 */
+ if (cplx_mask & 0x4)
+ lane_enable |= cplx_lane_enable;
+
+ if (cplx_mask & 0x8)
+ lane_enable |= (cplx_lane_enable << 16);
+
+ nlm_write_nae_reg(nae_base,
+ NAE_REG(block, LANE_CFG, LANE_CFG_CPLX_2_3),
+ lane_enable);
+
+ /* complex 4 */
+ /* XXXJC : fix duplicate code */
+ if (cplx_mask & 0x10) {
+ nlm_write_nae_reg(nae_base,
+ NAE_REG(block, LANE_CFG, LANE_CFG_CPLX_4),
+ ((LM_SGMII << 4) | LM_SGMII));
+ for (lane_ctrl = PHY_LANE_0_CTRL;
+ lane_ctrl <= PHY_LANE_1_CTRL; lane_ctrl++) {
+ if (!nlm_is_xlp8xx_ax())
+ xlp_nae_lane_reset_txpll(nae_base,
+ 4, lane_ctrl, PHYMODE_SGMII);
+ else
+ xlp_ax_nae_lane_reset_txpll(nae_base, 4,
+ lane_ctrl, PHYMODE_SGMII);
+ }
+ }
+
+ for (block = 0; block < 4; block++) {
+ if ((cplx_mask & (1 << block)) == 0)
+ continue;
+
+ for (lane_ctrl = PHY_LANE_0_CTRL;
+ lane_ctrl <= PHY_LANE_3_CTRL; lane_ctrl++) {
+ if (!nlm_is_xlp8xx_ax())
+ xlp_nae_lane_reset_txpll(nae_base,
+ block, lane_ctrl, PHYMODE_SGMII);
+ else
+ xlp_ax_nae_lane_reset_txpll(nae_base, block,
+ lane_ctrl, PHYMODE_SGMII);
+ }
+ }
+}
+
+void
+config_egress_fifo_carvings(uint64_t nae_base, int hwport, int start_ctxt,
+ int num_ctxts, int max_ctxts, struct nae_port_config *cfg)
+{
+ static uint32_t cur_start[6] = {0, 0, 0, 0, 0, 0};
+ uint32_t data = 0;
+ uint32_t start = 0, size, offset;
+ int i, limit;
+
+ limit = start_ctxt + num_ctxts;
+ /* Stage 2 FIFO */
+ start = cur_start[0];
+ for (i = start_ctxt; i < limit; i++) {
+ size = cfg[hwport].stg2_fifo_size / max_ctxts;
+ if (size)
+ offset = size - 1;
+ else
+ offset = size;
+ if (offset > cfg[hwport].max_stg2_offset)
+ offset = cfg[hwport].max_stg2_offset;
+ data = offset << 23 |
+ start << 11 |
+ i << 1 |
+ 1;
+ nlm_write_nae_reg(nae_base, NAE_STG2_PMEM_PROG, data);
+ start += size;
+ }
+ cur_start[0] = start;
+
+ /* EH FIFO */
+ start = cur_start[1];
+ for (i = start_ctxt; i < limit; i++) {
+ size = cfg[hwport].eh_fifo_size / max_ctxts;
+ if (size)
+ offset = size - 1;
+ else
+ offset = size ;
+ if (offset > cfg[hwport].max_eh_offset)
+ offset = cfg[hwport].max_eh_offset;
+ data = offset << 23 |
+ start << 11 |
+ i << 1 |
+ 1;
+ nlm_write_nae_reg(nae_base, NAE_EH_PMEM_PROG, data);
+ start += size;
+ }
+ cur_start[1] = start;
+
+ /* FROUT FIFO */
+ start = cur_start[2];
+ for (i = start_ctxt; i < limit; i++) {
+ size = cfg[hwport].frout_fifo_size / max_ctxts;
+ if (size)
+ offset = size - 1;
+ else
+ offset = size ;
+ if (offset > cfg[hwport].max_frout_offset)
+ offset = cfg[hwport].max_frout_offset;
+ data = offset << 23 |
+ start << 11 |
+ i << 1 |
+ 1;
+ nlm_write_nae_reg(nae_base, NAE_FREE_PMEM_PROG, data);
+ start += size;
+ }
+ cur_start[2] = start;
+
+ /* MS FIFO */
+ start = cur_start[3];
+ for (i = start_ctxt; i < limit; i++) {
+ size = cfg[hwport].ms_fifo_size / max_ctxts;
+ if (size)
+ offset = size - 1;
+ else
+ offset = size ;
+ if (offset > cfg[hwport].max_ms_offset)
+ offset = cfg[hwport].max_ms_offset;
+ data = offset << 22 | /* FIXME in PRM */
+ start << 11 |
+ i << 1 |
+ 1;
+ nlm_write_nae_reg(nae_base, NAE_STR_PMEM_CMD, data);
+ start += size;
+ }
+ cur_start[3] = start;
+
+ /* PKT FIFO */
+ start = cur_start[4];
+ for (i = start_ctxt; i < limit; i++) {
+ size = cfg[hwport].pkt_fifo_size / max_ctxts;
+ if (size)
+ offset = size - 1;
+ else
+ offset = size ;
+ if (offset > cfg[hwport].max_pmem_offset)
+ offset = cfg[hwport].max_pmem_offset;
+ nlm_write_nae_reg(nae_base, NAE_TX_PKT_PMEM_CMD1, offset);
+
+ data = start << 11 |
+ i << 1 |
+ 1;
+ nlm_write_nae_reg(nae_base, NAE_TX_PKT_PMEM_CMD0, data);
+ start += size;
+ }
+ cur_start[4] = start;
+
+ /* PKT LEN FIFO */
+ start = cur_start[5];
+ for (i = start_ctxt; i < limit; i++) {
+ size = cfg[hwport].pktlen_fifo_size / max_ctxts;
+ if (size)
+ offset = size - 1;
+ else
+ offset = size ;
+ data = offset << 22 |
+ start << 11 |
+ i << 1 |
+ 1;
+ nlm_write_nae_reg(nae_base, NAE_TX_PKTLEN_PMEM_CMD, data);
+ start += size;
+ }
+ cur_start[5] = start;
+}
+
+void
+config_egress_fifo_credits(uint64_t nae_base, int hwport, int start_ctxt,
+ int num_ctxts, int max_ctxts, struct nae_port_config *cfg)
+{
+ uint32_t data, credit, max_credit;
+ int i, limit;
+
+ limit = start_ctxt + num_ctxts;
+ /* Stage1 -> Stage2 */
+ max_credit = cfg[hwport].max_stg2_offset + 1;
+ for (i = start_ctxt; i < limit; i++) {
+ credit = cfg[hwport].stg1_2_credit / max_ctxts;
+ if (credit > max_credit)
+ credit = max_credit;
+ data = credit << 16 |
+ i << 4 |
+ 1;
+ nlm_write_nae_reg(nae_base, NAE_STG1_STG2CRDT_CMD, data);
+ }
+
+ /* Stage2 -> EH */
+ max_credit = cfg[hwport].max_eh_offset + 1;
+ for (i = start_ctxt; i < limit; i++) {
+ credit = cfg[hwport].stg2_eh_credit / max_ctxts;
+ if (credit > max_credit)
+ credit = max_credit;
+ data = credit << 16 |
+ i << 4 |
+ 1;
+ nlm_write_nae_reg(nae_base, NAE_STG2_EHCRDT_CMD, data);
+ }
+
+ /* Stage2 -> Frout */
+ max_credit = cfg[hwport].max_frout_offset + 1;
+ for (i = start_ctxt; i < limit; i++) {
+ credit = cfg[hwport].stg2_frout_credit / max_ctxts;
+ if (credit > max_credit)
+ credit = max_credit;
+ data = credit << 16 |
+ i << 4 |
+ 1;
+ nlm_write_nae_reg(nae_base, NAE_EH_FREECRDT_CMD, data);
+ }
+
+ /* Stage2 -> MS */
+ max_credit = cfg[hwport].max_ms_offset + 1;
+ for (i = start_ctxt; i < limit; i++) {
+ credit = cfg[hwport].stg2_ms_credit / max_ctxts;
+ if (credit > max_credit)
+ credit = max_credit;
+ data = credit << 16 |
+ i << 4 |
+ 1;
+ nlm_write_nae_reg(nae_base, NAE_STG2_STRCRDT_CMD, data);
+ }
+}
+
+void
+nlm_config_freein_fifo_uniq_cfg(uint64_t nae_base, int port,
+ int nblock_free_desc)
+{
+ uint32_t val;
+ int size_in_clines;
+
+ size_in_clines = (nblock_free_desc / NAE_CACHELINE_SIZE);
+ val = (size_in_clines << 8) | (port & 0x1f);
+ nlm_write_nae_reg(nae_base, NAE_FREEIN_FIFO_UNIQ_SZ_CFG, val);
+}
+
+/* XXXJC: redundant, see ucore_spray_config() */
+void
+nlm_config_ucore_iface_mask_cfg(uint64_t nae_base, int port,
+ int nblock_ucore_mask)
+{
+ uint32_t val;
+
+ val = ( 0x1U << 31) | ((nblock_ucore_mask & 0xffff) << 8) |
+ (port & 0x1f);
+ nlm_write_nae_reg(nae_base, NAE_UCORE_IFACEMASK_CFG, val);
+}
+
+int
+nlm_nae_init_netior(uint64_t nae_base, int nblocks)
+{
+ uint32_t ctrl1, ctrl2, ctrl3;
+
+ if (nblocks == 5)
+ ctrl3 = 0x07 << 18;
+ else
+ ctrl3 = 0;
+
+ switch (nblocks) {
+ case 2:
+ ctrl1 = 0xff;
+ ctrl2 = 0x0707;
+ break;
+ case 4:
+ case 5:
+ ctrl1 = 0xfffff;
+ ctrl2 = 0x07070707;
+ break;
+ default:
+ printf("WARNING: unsupported blocks %d\n", nblocks);
+ return (-1);
+ }
+
+ nlm_write_nae_reg(nae_base, NAE_LANE_CFG_SOFTRESET, 0);
+ nlm_write_nae_reg(nae_base, NAE_NETIOR_MISC_CTRL3, ctrl3);
+ nlm_write_nae_reg(nae_base, NAE_NETIOR_MISC_CTRL2, ctrl2);
+ nlm_write_nae_reg(nae_base, NAE_NETIOR_MISC_CTRL1, ctrl1);
+ nlm_write_nae_reg(nae_base, NAE_NETIOR_MISC_CTRL1, 0x0);
+ return (0);
+}
+
+void
+nlm_nae_init_ingress(uint64_t nae_base, uint32_t desc_size)
+{
+ uint32_t rx_cfg;
+ uint32_t parser_threshold = 384;
+
+ rx_cfg = nlm_read_nae_reg(nae_base, NAE_RX_CONFIG);
+ rx_cfg &= ~(0x3 << 1); /* reset max message size */
+ rx_cfg &= ~(0xff << 4); /* clear freein desc cluster size */
+ rx_cfg &= ~(0x3f << 24); /* reset rx status mask */ /*XXX: why not 7f */
+
+ rx_cfg |= 1; /* rx enable */
+ rx_cfg |= (0x0 << 1); /* max message size */
+ rx_cfg |= (0x43 & 0x7f) << 24; /* rx status mask */
+ rx_cfg |= ((desc_size / 64) & 0xff) << 4; /* freein desc cluster size */
+ nlm_write_nae_reg(nae_base, NAE_RX_CONFIG, rx_cfg);
+ nlm_write_nae_reg(nae_base, NAE_PARSER_CONFIG,
+ (parser_threshold & 0x3ff) |
+ (((parser_threshold / desc_size) + 1) & 0xff) << 12 |
+ (((parser_threshold / 64) % desc_size) & 0xff) << 20);
+
+ /*nlm_write_nae_reg(nae_base, NAE_RX_FREE_FIFO_THRESH, 33);*/
+}
+
+void
+nlm_nae_init_egress(uint64_t nae_base)
+{
+ uint32_t tx_cfg;
+
+ tx_cfg = nlm_read_nae_reg(nae_base, NAE_TX_CONFIG);
+ if (!nlm_is_xlp8xx_ax()) {
+ nlm_write_nae_reg(nae_base, NAE_TX_CONFIG,
+ tx_cfg |
+ 0x1 | /* tx enable */
+ 0x2 | /* tx ace */
+ 0x4 | /* tx compatible */
+ (1 << 3));
+ } else {
+ nlm_write_nae_reg(nae_base, NAE_TX_CONFIG,
+ tx_cfg |
+ 0x1 | /* tx enable */
+ 0x2); /* tx ace */
+ }
+}
+
+uint32_t
+ucore_spray_config(uint32_t interface, uint32_t ucore_mask, int cmd)
+{
+ return ((cmd & 0x1) << 31) | ((ucore_mask & 0xffff) << 8) |
+ (interface & 0x1f);
+}
+
+void
+nlm_nae_init_ucore(uint64_t nae_base, int if_num, u_int ucore_mask)
+{
+ uint32_t ucfg;
+
+ ucfg = ucore_spray_config(if_num, ucore_mask, 1); /* 1 : write */
+ nlm_write_nae_reg(nae_base, NAE_UCORE_IFACEMASK_CFG, ucfg);
+}
+
+uint64_t
+nae_tx_desc(u_int type, u_int rdex, u_int fbid, u_int len, uint64_t addr)
+{
+ return ((uint64_t)type << 62) |
+ ((uint64_t)rdex << 61) |
+ ((uint64_t)fbid << 54) |
+ ((uint64_t)len << 40) | addr;
+}
+
+void
+nlm_setup_l2type(uint64_t nae_base, int hwport, uint32_t l2extlen,
+ uint32_t l2extoff, uint32_t extra_hdrsize, uint32_t proto_offset,
+ uint32_t fixed_hdroff, uint32_t l2proto)
+{
+ uint32_t val;
+
+ val = ((l2extlen & 0x3f) << 26) |
+ ((l2extoff & 0x3f) << 20) |
+ ((extra_hdrsize & 0x3f) << 14) |
+ ((proto_offset & 0x3f) << 8) |
+ ((fixed_hdroff & 0x3f) << 2) |
+ (l2proto & 0x3);
+ nlm_write_nae_reg(nae_base, (NAE_L2_TYPE_PORT0 + hwport), val);
+}
+
+void
+nlm_setup_l3ctable_mask(uint64_t nae_base, int hwport, uint32_t ptmask,
+ uint32_t l3portmask)
+{
+ uint32_t val;
+
+ val = ((ptmask & 0x1) << 6) |
+ ((l3portmask & 0x1) << 5) |
+ (hwport & 0x1f);
+ nlm_write_nae_reg(nae_base, NAE_L3_CTABLE_MASK0, val);
+}
+
+void
+nlm_setup_l3ctable_even(uint64_t nae_base, int entry, uint32_t l3hdroff,
+ uint32_t ipcsum_en, uint32_t l4protooff,
+ uint32_t l2proto, uint32_t eth_type)
+{
+ uint32_t val;
+
+ val = ((l3hdroff & 0x3f) << 26) |
+ ((l4protooff & 0x3f) << 20) |
+ ((ipcsum_en & 0x1) << 18) |
+ ((l2proto & 0x3) << 16) |
+ (eth_type & 0xffff);
+ nlm_write_nae_reg(nae_base, (NAE_L3CTABLE0 + (entry * 2)), val);
+}
+
+void
+nlm_setup_l3ctable_odd(uint64_t nae_base, int entry, uint32_t l3off0,
+ uint32_t l3len0, uint32_t l3off1, uint32_t l3len1,
+ uint32_t l3off2, uint32_t l3len2)
+{
+ uint32_t val;
+
+ val = ((l3off0 & 0x3f) << 26) |
+ ((l3len0 & 0x1f) << 21) |
+ ((l3off1 & 0x3f) << 15) |
+ ((l3len1 & 0x1f) << 10) |
+ ((l3off2 & 0x3f) << 4) |
+ (l3len2 & 0xf);
+ nlm_write_nae_reg(nae_base, (NAE_L3CTABLE0 + ((entry * 2) + 1)), val);
+}
+
+void
+nlm_setup_l4ctable_even(uint64_t nae_base, int entry, uint32_t im,
+ uint32_t l3cm, uint32_t l4pm, uint32_t port,
+ uint32_t l3camaddr, uint32_t l4proto)
+{
+ uint32_t val;
+
+ val = ((im & 0x1) << 19) |
+ ((l3cm & 0x1) << 18) |
+ ((l4pm & 0x1) << 17) |
+ ((port & 0x1f) << 12) |
+ ((l3camaddr & 0xf) << 8) |
+ (l4proto & 0xff);
+ nlm_write_nae_reg(nae_base, (NAE_L4CTABLE0 + (entry * 2)), val);
+}
+
+void
+nlm_setup_l4ctable_odd(uint64_t nae_base, int entry, uint32_t l4off0,
+ uint32_t l4len0, uint32_t l4off1, uint32_t l4len1)
+{
+ uint32_t val;
+
+ val = ((l4off0 & 0x3f) << 21) |
+ ((l4len0 & 0xf) << 17) |
+ ((l4off1 & 0x3f) << 11) |
+ (l4len1 & 0xf);
+ nlm_write_nae_reg(nae_base, (NAE_L4CTABLE0 + ((entry * 2) + 1)), val);
+}
+
+void
+nlm_enable_hardware_parser(uint64_t nae_base)
+{
+ uint32_t val;
+
+ val = nlm_read_nae_reg(nae_base, NAE_RX_CONFIG);
+ val |= (1 << 12); /* hardware parser enable */
+ nlm_write_nae_reg(nae_base, NAE_RX_CONFIG, val);
+
+ /***********************************************
+ * program L3 CAM table
+ ***********************************************/
+
+ /*
+ * entry-0 is ipv4 MPLS type 1 label
+ */
+ /* l3hdroff = 4 bytes, ether_type = 0x8847 for MPLS_type1 */
+ nlm_setup_l3ctable_even(nae_base, 0, 4, 1, 9, 1, 0x8847);
+ /* l3off0 (8 bytes) -> l3len0 (1 byte) := ip proto
+ * l3off1 (12 bytes) -> l3len1 (4 bytes) := src ip
+ * l3off2 (16 bytes) -> l3len2 (4 bytes) := dst ip
+ */
+ nlm_setup_l3ctable_odd(nae_base, 0, 9, 1, 12, 4, 16, 4);
+
+ /*
+ * entry-1 is for ethernet IPv4 packets
+ */
+ nlm_setup_l3ctable_even(nae_base, 1, 0, 1, 9, 1, 0x0800);
+ /* l3off0 (8 bytes) -> l3len0 (1 byte) := ip proto
+ * l3off1 (12 bytes) -> l3len1 (4 bytes) := src ip
+ * l3off2 (16 bytes) -> l3len2 (4 bytes) := dst ip
+ */
+ nlm_setup_l3ctable_odd(nae_base, 1, 9, 1, 12, 4, 16, 4);
+
+ /*
+ * entry-2 is for ethernet IPv6 packets
+ */
+ nlm_setup_l3ctable_even(nae_base, 2, 0, 1, 6, 1, 0x86dd);
+ /* l3off0 (6 bytes) -> l3len0 (1 byte) := next header (ip proto)
+ * l3off1 (8 bytes) -> l3len1 (16 bytes) := src ip
+ * l3off2 (24 bytes) -> l3len2 (16 bytes) := dst ip
+ */
+ nlm_setup_l3ctable_odd(nae_base, 2, 6, 1, 8, 16, 24, 16);
+
+ /*
+ * entry-3 is for ethernet ARP packets
+ */
+ nlm_setup_l3ctable_even(nae_base, 3, 0, 0, 9, 1, 0x0806);
+ /* extract 30 bytes from packet start */
+ nlm_setup_l3ctable_odd(nae_base, 3, 0, 30, 0, 0, 0, 0);
+
+ /*
+ * entry-4 is for ethernet FCoE packets
+ */
+ nlm_setup_l3ctable_even(nae_base, 4, 0, 0, 9, 1, 0x8906);
+ /* FCoE packet consists of 4 byte start-of-frame,
+ * and 24 bytes of frame header, followed by
+ * 64 bytes of optional-header (ESP, network..),
+ * 2048 bytes of payload, 36 bytes of optional
+ * "fill bytes" or ESP trailer, 4 bytes of CRC,
+ * and 4 bytes of end-of-frame
+ * We extract the first 4 + 24 = 28 bytes
+ */
+ nlm_setup_l3ctable_odd(nae_base, 4, 0, 28, 0, 0, 0, 0);
+
+ /*
+ * entry-5 is for vlan tagged frames (0x8100)
+ */
+ nlm_setup_l3ctable_even(nae_base, 5, 0, 0, 9, 1, 0x8100);
+ /* we extract 31 bytes from the payload */
+ nlm_setup_l3ctable_odd(nae_base, 5, 0, 31, 0, 0, 0, 0);
+
+ /*
+ * entry-6 is for ieee 802.1ad provider bridging
+ * tagged frames (0x88a8)
+ */
+ nlm_setup_l3ctable_even(nae_base, 6, 0, 0, 9, 1, 0x88a8);
+ /* we extract 31 bytes from the payload */
+ nlm_setup_l3ctable_odd(nae_base, 6, 0, 31, 0, 0, 0, 0);
+
+ /*
+ * entry-7 is for Cisco's Q-in-Q tagged frames (0x9100)
+ */
+ nlm_setup_l3ctable_even(nae_base, 7, 0, 0, 9, 1, 0x9100);
+ /* we extract 31 bytes from the payload */
+ nlm_setup_l3ctable_odd(nae_base, 7, 0, 31, 0, 0, 0, 0);
+
+ /*
+ * entry-8 is for Ethernet Jumbo frames (0x8870)
+ */
+ nlm_setup_l3ctable_even(nae_base, 8, 0, 0, 9, 1, 0x8870);
+ /* we extract 31 bytes from the payload */
+ nlm_setup_l3ctable_odd(nae_base, 8, 0, 31, 0, 0, 0, 0);
+
+ /*
+ * entry-9 is for MPLS Multicast frames (0x8848)
+ */
+ nlm_setup_l3ctable_even(nae_base, 9, 0, 0, 9, 1, 0x8848);
+ /* we extract 31 bytes from the payload */
+ nlm_setup_l3ctable_odd(nae_base, 9, 0, 31, 0, 0, 0, 0);
+
+ /*
+ * entry-10 is for IEEE 802.1ae MAC Security frames (0x88e5)
+ */
+ nlm_setup_l3ctable_even(nae_base, 10, 0, 0, 9, 1, 0x88e5);
+ /* we extract 31 bytes from the payload */
+ nlm_setup_l3ctable_odd(nae_base, 10, 0, 31, 0, 0, 0, 0);
+
+ /*
+ * entry-11 is for PTP frames (0x88f7)
+ */
+ nlm_setup_l3ctable_even(nae_base, 11, 0, 0, 9, 1, 0x88f7);
+ /* PTP messages can be sent as UDP messages over
+ * IPv4 or IPv6; and as a raw ethernet message
+ * with ethertype 0x88f7. The message contents
+ * are the same for UDP or ethernet based encapsulations
+ * The header is 34 bytes long, and we extract
+ * it all out.
+ */
+ nlm_setup_l3ctable_odd(nae_base, 11, 0, 31, 31, 2, 0, 0);
+
+ /*
+ * entry-12 is for ethernet Link Control Protocol (LCP)
+ * used with PPPoE
+ */
+ nlm_setup_l3ctable_even(nae_base, 12, 0, 0, 9, 1, 0xc021);
+ /* LCP packet consists of 1 byte of code, 1 byte of
+ * identifier and two bytes of length followed by
+ * data (upto length bytes).
+ * We extract 4 bytes from start of packet
+ */
+ nlm_setup_l3ctable_odd(nae_base, 12, 0, 4, 0, 0, 0, 0);
+
+ /*
+ * entry-13 is for ethernet Link Quality Report (0xc025)
+ * used with PPPoE
+ */
+ nlm_setup_l3ctable_even(nae_base, 13, 0, 0, 9, 1, 0xc025);
+ /* We extract 31 bytes from packet start */
+ nlm_setup_l3ctable_odd(nae_base, 13, 0, 31, 0, 0, 0, 0);
+
+ /*
+ * entry-14 is for PPPoE Session (0x8864)
+ */
+ nlm_setup_l3ctable_even(nae_base, 14, 0, 0, 9, 1, 0x8864);
+ /* We extract 31 bytes from packet start */
+ nlm_setup_l3ctable_odd(nae_base, 14, 0, 31, 0, 0, 0, 0);
+
+ /*
+ * entry-15 - default entry
+ */
+ nlm_setup_l3ctable_even(nae_base, 15, 0, 0, 0, 0, 0x0000);
+ /* We extract 31 bytes from packet start */
+ nlm_setup_l3ctable_odd(nae_base, 15, 0, 31, 0, 0, 0, 0);
+
+ /***********************************************
+ * program L4 CAM table
+ ***********************************************/
+
+ /*
+ * entry-0 - tcp packets (0x6)
+ */
+ nlm_setup_l4ctable_even(nae_base, 0, 0, 0, 1, 0, 0, 0x6);
+ /* tcp header is 20 bytes without tcp options
+ * We extract 20 bytes from tcp start */
+ nlm_setup_l4ctable_odd(nae_base, 0, 0, 15, 15, 5);
+
+ /*
+ * entry-1 - udp packets (0x11)
+ */
+ nlm_setup_l4ctable_even(nae_base, 1, 0, 0, 1, 0, 0, 0x11);
+ /* udp header is 8 bytes in size.
+ * We extract 8 bytes from udp start */
+ nlm_setup_l4ctable_odd(nae_base, 1, 0, 8, 0, 0);
+
+ /*
+ * entry-2 - sctp packets (0x84)
+ */
+ nlm_setup_l4ctable_even(nae_base, 2, 0, 0, 1, 0, 0, 0x84);
+ /* sctp packets have a 12 byte generic header
+ * and various chunks.
+ * We extract 12 bytes from sctp start */
+ nlm_setup_l4ctable_odd(nae_base, 2, 0, 12, 0, 0);
+
+ /*
+ * entry-3 - RDP packets (0x1b)
+ */
+ nlm_setup_l4ctable_even(nae_base, 3, 0, 0, 1, 0, 0, 0x1b);
+ /* RDP packets have 18 bytes of generic header
+ * before variable header starts.
+ * We extract 18 bytes from rdp start */
+ nlm_setup_l4ctable_odd(nae_base, 3, 0, 15, 15, 3);
+
+ /*
+ * entry-4 - DCCP packets (0x21)
+ */
+ nlm_setup_l4ctable_even(nae_base, 4, 0, 0, 1, 0, 0, 0x21);
+ /* DCCP has two types of generic headers of
+ * sizes 16 bytes and 12 bytes if X = 1.
+ * We extract 16 bytes from dccp start */
+ nlm_setup_l4ctable_odd(nae_base, 4, 0, 15, 15, 1);
+
+ /*
+ * entry-5 - ipv6 encapsulated in ipv4 packets (0x29)
+ */
+ nlm_setup_l4ctable_even(nae_base, 5, 0, 0, 1, 0, 0, 0x29);
+ /* ipv4 header is 20 bytes excluding IP options.
+ * We extract 20 bytes from IPv4 start */
+ nlm_setup_l4ctable_odd(nae_base, 5, 0, 15, 15, 5);
+
+ /*
+ * entry-6 - ip in ip encapsulation packets (0x04)
+ */
+ nlm_setup_l4ctable_even(nae_base, 6, 0, 0, 1, 0, 0, 0x04);
+ /* ipv4 header is 20 bytes excluding IP options.
+ * We extract 20 bytes from ipv4 start */
+ nlm_setup_l4ctable_odd(nae_base, 6, 0, 15, 15, 5);
+
+ /*
+ * entry-7 - default entry (0x0)
+ */
+ nlm_setup_l4ctable_even(nae_base, 7, 0, 0, 1, 0, 0, 0x0);
+ /* We extract 20 bytes from packet start */
+ nlm_setup_l4ctable_odd(nae_base, 7, 0, 15, 15, 5);
+}
+
+void
+nlm_enable_hardware_parser_per_port(uint64_t nae_base, int block, int port)
+{
+ int hwport = (block * 4) + (port & 0x3);
+
+ /* program L2 and L3 header extraction for each port */
+ /* enable ethernet L2 mode on port */
+ nlm_setup_l2type(nae_base, hwport, 0, 0, 0, 0, 0, 1);
+
+ /* l2proto and ethtype included in l3cam */
+ nlm_setup_l3ctable_mask(nae_base, hwport, 1, 0);
+}
+
+void
+nlm_prepad_enable(uint64_t nae_base, int size)
+{
+ uint32_t val;
+
+ val = nlm_read_nae_reg(nae_base, NAE_RX_CONFIG);
+ val |= (1 << 13); /* prepad enable */
+ val |= ((size & 0x3) << 22); /* prepad size */
+ nlm_write_nae_reg(nae_base, NAE_RX_CONFIG, val);
+}
+
+void
+nlm_setup_1588_timer(uint64_t nae_base, struct nae_port_config *cfg)
+{
+ uint32_t hi, lo, val;
+
+ hi = cfg[0].ieee1588_userval >> 32;
+ lo = cfg[0].ieee1588_userval & 0xffffffff;
+ nlm_write_nae_reg(nae_base, NAE_1588_PTP_USER_VALUE_HI, hi);
+ nlm_write_nae_reg(nae_base, NAE_1588_PTP_USER_VALUE_LO, lo);
+
+ hi = cfg[0].ieee1588_ptpoff >> 32;
+ lo = cfg[0].ieee1588_ptpoff & 0xffffffff;
+ nlm_write_nae_reg(nae_base, NAE_1588_PTP_OFFSET_HI, hi);
+ nlm_write_nae_reg(nae_base, NAE_1588_PTP_OFFSET_LO, lo);
+
+ hi = cfg[0].ieee1588_tmr1 >> 32;
+ lo = cfg[0].ieee1588_tmr1 & 0xffffffff;
+ nlm_write_nae_reg(nae_base, NAE_1588_PTP_TMR1_HI, hi);
+ nlm_write_nae_reg(nae_base, NAE_1588_PTP_TMR1_LO, lo);
+
+ hi = cfg[0].ieee1588_tmr2 >> 32;
+ lo = cfg[0].ieee1588_tmr2 & 0xffffffff;
+ nlm_write_nae_reg(nae_base, NAE_1588_PTP_TMR2_HI, hi);
+ nlm_write_nae_reg(nae_base, NAE_1588_PTP_TMR2_LO, lo);
+
+ hi = cfg[0].ieee1588_tmr3 >> 32;
+ lo = cfg[0].ieee1588_tmr3 & 0xffffffff;
+ nlm_write_nae_reg(nae_base, NAE_1588_PTP_TMR3_HI, hi);
+ nlm_write_nae_reg(nae_base, NAE_1588_PTP_TMR3_LO, lo);
+
+ nlm_write_nae_reg(nae_base, NAE_1588_PTP_INC_INTG,
+ cfg[0].ieee1588_inc_intg);
+ nlm_write_nae_reg(nae_base, NAE_1588_PTP_INC_NUM,
+ cfg[0].ieee1588_inc_num);
+ nlm_write_nae_reg(nae_base, NAE_1588_PTP_INC_DEN,
+ cfg[0].ieee1588_inc_den);
+
+ val = nlm_read_nae_reg(nae_base, NAE_1588_PTP_CONTROL);
+ /* set and clear freq_mul = 1 */
+ nlm_write_nae_reg(nae_base, NAE_1588_PTP_CONTROL, val | (0x1 << 1));
+ nlm_write_nae_reg(nae_base, NAE_1588_PTP_CONTROL, val);
+ /* set and clear load_user_val = 1 */
+ nlm_write_nae_reg(nae_base, NAE_1588_PTP_CONTROL, val | (0x1 << 6));
+ nlm_write_nae_reg(nae_base, NAE_1588_PTP_CONTROL, val);
+}
+
+void
+nlm_mac_enable(uint64_t nae_base, int nblock, int port_type, int port)
+{
+ uint32_t mac_cfg1, xaui_cfg;
+ uint32_t netwk_inf;
+ int iface = port & 0x3;
+
+ switch(port_type) {
+ case SGMIIC:
+ netwk_inf = nlm_read_nae_reg(nae_base,
+ SGMII_NET_IFACE_CTRL(nblock, iface));
+ nlm_write_nae_reg(nae_base,
+ SGMII_NET_IFACE_CTRL(nblock, iface),
+ netwk_inf |
+ (1 << 2)); /* enable tx */
+ mac_cfg1 = nlm_read_nae_reg(nae_base,
+ SGMII_MAC_CONF1(nblock, iface));
+ nlm_write_nae_reg(nae_base,
+ SGMII_MAC_CONF1(nblock, iface),
+ mac_cfg1 |
+ (1 << 2) | /* rx enable */
+ 1); /* tx enable */
+ break;
+ case XAUIC:
+ xaui_cfg = nlm_read_nae_reg(nae_base,
+ XAUI_CONFIG1(nblock));
+ nlm_write_nae_reg(nae_base,
+ XAUI_CONFIG1(nblock),
+ xaui_cfg |
+ XAUI_CONFIG_TFEN |
+ XAUI_CONFIG_RFEN);
+ break;
+ case ILC:
+ break;
+ }
+}
+
+void
+nlm_mac_disable(uint64_t nae_base, int nblock, int port_type, int port)
+{
+ uint32_t mac_cfg1, xaui_cfg;
+ uint32_t netwk_inf;
+ int iface = port & 0x3;
+
+ switch(port_type) {
+ case SGMIIC:
+ mac_cfg1 = nlm_read_nae_reg(nae_base,
+ SGMII_MAC_CONF1(nblock, iface));
+ nlm_write_nae_reg(nae_base,
+ SGMII_MAC_CONF1(nblock, iface),
+ mac_cfg1 &
+ ~((1 << 2) | /* rx enable */
+ 1)); /* tx enable */
+ netwk_inf = nlm_read_nae_reg(nae_base,
+ SGMII_NET_IFACE_CTRL(nblock, iface));
+ nlm_write_nae_reg(nae_base,
+ SGMII_NET_IFACE_CTRL(nblock, iface),
+ netwk_inf &
+ ~(1 << 2)); /* enable tx */
+ break;
+ case XAUIC:
+ xaui_cfg = nlm_read_nae_reg(nae_base,
+ XAUI_CONFIG1(nblock));
+ nlm_write_nae_reg(nae_base,
+ XAUI_CONFIG1(nblock),
+ xaui_cfg &
+ ~(XAUI_CONFIG_TFEN |
+ XAUI_CONFIG_RFEN));
+ break;
+ case ILC:
+ break;
+ }
+}
+
+/*
+ * Set IOR credits for the ports in ifmask to valmask
+ */
+static void
+nlm_nae_set_ior_credit(uint64_t nae_base, uint32_t ifmask, uint32_t valmask)
+{
+ uint32_t tx_config, tx_ior_credit;
+
+ tx_ior_credit = nlm_read_nae_reg(nae_base, NAE_TX_IORCRDT_INIT);
+ tx_ior_credit &= ~ifmask;
+ tx_ior_credit |= valmask;
+ nlm_write_nae_reg(nae_base, NAE_TX_IORCRDT_INIT, tx_ior_credit);
+
+ tx_config = nlm_read_nae_reg(nae_base, NAE_TX_CONFIG);
+ /* need to toggle these bits for credits to be loaded */
+ nlm_write_nae_reg(nae_base, NAE_TX_CONFIG,
+ tx_config | (TXINITIORCR(ifmask)));
+ nlm_write_nae_reg(nae_base, NAE_TX_CONFIG,
+ tx_config & ~(TXINITIORCR(ifmask)));
+}
+
+int
+nlm_nae_open_if(uint64_t nae_base, int nblock, int port_type,
+ int port, uint32_t desc_size)
+{
+ uint32_t netwk_inf;
+ uint32_t mac_cfg1, netior_ctrl3;
+ int iface, iface_ctrl_reg, iface_ctrl3_reg, conf1_reg, conf2_reg;
+
+ switch (port_type) {
+ case XAUIC:
+ netwk_inf = nlm_read_nae_reg(nae_base,
+ XAUI_NETIOR_XGMAC_CTRL1(nblock));
+ netwk_inf |= (1 << NETIOR_XGMAC_STATS_CLR_POS);
+ nlm_write_nae_reg(nae_base,
+ XAUI_NETIOR_XGMAC_CTRL1(nblock), netwk_inf);
+
+ nlm_nae_set_ior_credit(nae_base, 0xf << port, 0xf << port);
+ break;
+
+ case ILC:
+ nlm_nae_set_ior_credit(nae_base, 0xff << port, 0xff << port);
+ break;
+
+ case SGMIIC:
+ nlm_nae_set_ior_credit(nae_base, 0x1 << port, 0);
+
+ /*
+ * XXXJC: split this and merge to sgmii.c
+ * some of this is duplicated from there.
+ */
+ /* init phy id to access internal PCS */
+ iface = port & 0x3;
+ iface_ctrl_reg = SGMII_NET_IFACE_CTRL(nblock, iface);
+ conf1_reg = SGMII_MAC_CONF1(nblock, iface);
+ conf2_reg = SGMII_MAC_CONF2(nblock, iface);
+
+ netwk_inf = nlm_read_nae_reg(nae_base, iface_ctrl_reg);
+ netwk_inf &= 0x7ffffff;
+ netwk_inf |= (port << 27);
+ nlm_write_nae_reg(nae_base, iface_ctrl_reg, netwk_inf);
+
+ /* Sofreset sgmii port - set bit 11 to 0 */
+ netwk_inf &= 0xfffff7ff;
+ nlm_write_nae_reg(nae_base, iface_ctrl_reg, netwk_inf);
+
+ /* Reset Gmac */
+ mac_cfg1 = nlm_read_nae_reg(nae_base, conf1_reg);
+ nlm_write_nae_reg(nae_base, conf1_reg,
+ mac_cfg1 |
+ (1U << 31) | /* soft reset */
+ (1 << 2) | /* rx enable */
+ (1)); /* tx enable */
+
+ /* default to 1G */
+ nlm_write_nae_reg(nae_base,
+ conf2_reg,
+ (0x7 << 12) | /* interface preamble length */
+ (0x2 << 8) | /* interface mode */
+ (0x1 << 2) | /* pad crc enable */
+ (0x1)); /* full duplex */
+
+ /* clear gmac reset */
+ mac_cfg1 = nlm_read_nae_reg(nae_base, conf1_reg);
+ nlm_write_nae_reg(nae_base, conf1_reg, mac_cfg1 & ~(1U << 31));
+
+ /* clear speed debug bit */
+ iface_ctrl3_reg = SGMII_NET_IFACE_CTRL3(nblock, iface);
+ netior_ctrl3 = nlm_read_nae_reg(nae_base, iface_ctrl3_reg);
+ nlm_write_nae_reg(nae_base, iface_ctrl3_reg,
+ netior_ctrl3 & ~(1 << 6));
+
+ /* disable TX, RX for now */
+ mac_cfg1 = nlm_read_nae_reg(nae_base, conf1_reg);
+ nlm_write_nae_reg(nae_base, conf1_reg, mac_cfg1 & ~(0x5));
+ netwk_inf = nlm_read_nae_reg(nae_base, iface_ctrl_reg);
+ nlm_write_nae_reg(nae_base, iface_ctrl_reg,
+ netwk_inf & ~(0x1 << 2));
+
+ /* clear stats counters */
+ netwk_inf = nlm_read_nae_reg(nae_base, iface_ctrl_reg);
+ nlm_write_nae_reg(nae_base, iface_ctrl_reg,
+ netwk_inf | (1 << 15));
+
+ /* enable stats counters */
+ netwk_inf = nlm_read_nae_reg(nae_base, iface_ctrl_reg);
+ nlm_write_nae_reg(nae_base, iface_ctrl_reg,
+ (netwk_inf & ~(1 << 15)) | (1 << 16));
+
+ /* flow control? */
+ mac_cfg1 = nlm_read_nae_reg(nae_base, conf1_reg);
+ nlm_write_nae_reg(nae_base, conf1_reg,
+ mac_cfg1 | (0x3 << 4));
+ break;
+ }
+
+ nlm_nae_init_ingress(nae_base, desc_size);
+ nlm_nae_init_egress(nae_base);
+
+ return (0);
+}
Property changes on: trunk/sys/mips/nlm/dev/net/nae.c
___________________________________________________________________
Added: svn:eol-style
## -0,0 +1 ##
+native
\ No newline at end of property
Added: svn:keywords
## -0,0 +1 ##
+MidnightBSD=%H
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+text/plain
\ No newline at end of property
Added: trunk/sys/mips/nlm/dev/net/sgmii.c
===================================================================
--- trunk/sys/mips/nlm/dev/net/sgmii.c (rev 0)
+++ trunk/sys/mips/nlm/dev/net/sgmii.c 2018-05-26 21:55:02 UTC (rev 9987)
@@ -0,0 +1,210 @@
+/* $MidnightBSD$ */
+/*-
+ * Copyright (c) 2003-2012 Broadcom Corporation
+ * All Rights Reserved
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in
+ * the documentation and/or other materials provided with the
+ * distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY BROADCOM ``AS IS'' AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL BROADCOM OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
+ * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
+ * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
+ * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <sys/cdefs.h>
+__FBSDID("$FreeBSD: stable/10/sys/mips/nlm/dev/net/sgmii.c 245881 2013-01-24 15:14:22Z jchandra $");
+#include <sys/types.h>
+#include <sys/systm.h>
+
+#include <mips/nlm/hal/mips-extns.h>
+#include <mips/nlm/hal/haldefs.h>
+#include <mips/nlm/hal/iomap.h>
+#include <mips/nlm/hal/sys.h>
+#include <mips/nlm/hal/nae.h>
+#include <mips/nlm/hal/mdio.h>
+#include <mips/nlm/hal/sgmii.h>
+
+void
+nlm_configure_sgmii_interface(uint64_t nae_base, int block, int port,
+ int mtu, int loopback)
+{
+ uint32_t data1, data2;
+
+ /* Apply a soft reset */
+ data1 = (0x1 << 31); /* soft reset */
+ if (loopback)
+ data1 |= (0x01 << 8);
+ data1 |= (0x01 << 2); /* Rx enable */
+ data1 |= 0x01; /* Tx enable */
+ nlm_write_nae_reg(nae_base, NAE_REG(block, port, MAC_CONF1), data1);
+
+ data2 = (0x7 << 12) | /* pre-amble length=7 */
+ (0x2 << 8) | /* byteMode */
+ 0x1; /* fullDuplex */
+ nlm_write_nae_reg(nae_base, NAE_REG(block, port, MAC_CONF2), data2);
+
+ /* Remove a soft reset */
+ data1 &= ~(0x01 << 31);
+ nlm_write_nae_reg(nae_base, NAE_REG(block, port, MAC_CONF1), data1);
+
+ /* setup sgmii max frame length */
+ nlm_write_nae_reg(nae_base, SGMII_MAX_FRAME(block, port), mtu);
+}
+
+void
+nlm_sgmii_pcs_init(uint64_t nae_base, uint32_t cplx_mask)
+{
+ xlp_nae_config_lane_gmac(nae_base, cplx_mask);
+}
+
+void
+nlm_nae_setup_mac(uint64_t nae_base, int nblock, int iface, int reset,
+ int rx_en, int tx_en, int speed, int duplex)
+{
+ uint32_t mac_cfg1, mac_cfg2, netwk_inf;
+
+ mac_cfg1 = nlm_read_nae_reg(nae_base,
+ SGMII_MAC_CONF1(nblock,iface));
+ mac_cfg2 = nlm_read_nae_reg(nae_base,
+ SGMII_MAC_CONF2(nblock,iface));
+ netwk_inf = nlm_read_nae_reg(nae_base,
+ SGMII_NET_IFACE_CTRL(nblock, iface));
+
+ mac_cfg1 &= ~(0x1 << 31); /* remove reset */
+ mac_cfg1 &= ~(0x1 << 2); /* remove rx */
+ mac_cfg1 &= ~(0x1); /* remove tx */
+ mac_cfg2 &= ~(0x3 << 8); /* remove interface mode bits */
+ mac_cfg2 &= ~(0x1); /* remove duplex */
+ netwk_inf &= ~(0x1 << 2); /* remove tx */
+ netwk_inf &= ~(0x3); /* remove speed */
+
+ switch (speed) {
+ case NLM_SGMII_SPEED_10:
+ netwk_inf |= 0x0; /* 2.5 Mhz clock for 10 Mbps */
+ mac_cfg2 |= (0x1 << 8); /* enable 10/100 Mbps */
+ break;
+ case NLM_SGMII_SPEED_100:
+ netwk_inf |= 0x1; /* 25 Mhz clock for 100 Mbps */
+ mac_cfg2 |= (0x1 << 8); /* enable 10/100 Mbps */
+ break;
+ default: /* make it as 1G */
+ netwk_inf |= 0x2; /* 125 Mhz clock for 1G */
+ mac_cfg2 |= (0x2 << 8); /* enable 1G */
+ break;
+ }
+
+ if (reset)
+ mac_cfg1 |= (0x1 << 31); /* set reset */
+
+ if (rx_en)
+ mac_cfg1 |= (0x1 << 2); /* set rx */
+
+ nlm_write_nae_reg(nae_base,
+ SGMII_NET_IFACE_CTRL(nblock, iface),
+ netwk_inf);
+
+ if (tx_en) {
+ mac_cfg1 |= 0x1; /* set tx */
+ netwk_inf |= (0x1 << 2); /* set tx */
+ }
+
+ switch (duplex) {
+ case NLM_SGMII_DUPLEX_HALF:
+ /* duplexity is already set to half duplex */
+ break;
+ default:
+ mac_cfg2 |= 0x1; /* set full duplex */
+ }
+
+ nlm_write_nae_reg(nae_base, SGMII_MAC_CONF1(nblock, iface), mac_cfg1);
+ nlm_write_nae_reg(nae_base, SGMII_MAC_CONF2(nblock, iface), mac_cfg2);
+ nlm_write_nae_reg(nae_base, SGMII_NET_IFACE_CTRL(nblock, iface),
+ netwk_inf);
+}
+
+void
+nlm_nae_setup_rx_mode_sgmii(uint64_t base, int nblock, int iface, int port_type,
+ int broadcast_en, int multicast_en, int pause_en, int promisc_en)
+{
+ uint32_t val;
+
+ /* bit[17] of vlan_typefilter - allows packet matching in MAC.
+ * When DA filtering is disabled, this bit and bit[16] should
+ * be zero.
+ * bit[16] of vlan_typefilter - Allows hash matching to be used
+ * for DA filtering. When DA filtering is disabled, this bit and
+ * bit[17] should be zero.
+ * Both bits have to be set only if you want to turn on both
+ * features / modes.
+ */
+ if (promisc_en == 1) {
+ val = nlm_read_nae_reg(base,
+ SGMII_NETIOR_VLANTYPE_FILTER(nblock, iface));
+ val &= (~(0x3 << 16));
+ nlm_write_nae_reg(base,
+ SGMII_NETIOR_VLANTYPE_FILTER(nblock, iface), val);
+ } else {
+ val = nlm_read_nae_reg(base,
+ SGMII_NETIOR_VLANTYPE_FILTER(nblock, iface));
+ val |= (0x1 << 17);
+ nlm_write_nae_reg(base,
+ SGMII_NETIOR_VLANTYPE_FILTER(nblock, iface), val);
+ }
+
+ val = ((broadcast_en & 0x1) << 10) |
+ ((pause_en & 0x1) << 9) |
+ ((multicast_en & 0x1) << 8) |
+ ((promisc_en & 0x1) << 7) | /* unicast_enable - enables promisc mode */
+ 1; /* MAC address is always valid */
+
+ nlm_write_nae_reg(base, SGMII_MAC_FILTER_CONFIG(nblock, iface), val);
+
+}
+
+void
+nlm_nae_setup_mac_addr_sgmii(uint64_t base, int nblock, int iface,
+ int port_type, uint8_t *mac_addr)
+{
+ nlm_write_nae_reg(base,
+ SGMII_MAC_ADDR0_LO(nblock, iface),
+ (mac_addr[5] << 24) |
+ (mac_addr[4] << 16) |
+ (mac_addr[3] << 8) |
+ mac_addr[2]);
+
+ nlm_write_nae_reg(base,
+ SGMII_MAC_ADDR0_HI(nblock, iface),
+ (mac_addr[1] << 24) |
+ (mac_addr[0] << 16));
+
+ nlm_write_nae_reg(base,
+ SGMII_MAC_ADDR_MASK0_LO(nblock, iface),
+ 0xffffffff);
+ nlm_write_nae_reg(base,
+ SGMII_MAC_ADDR_MASK0_HI(nblock, iface),
+ 0xffffffff);
+
+ nlm_nae_setup_rx_mode_sgmii(base, nblock, iface,
+ SGMIIC,
+ 1, /* broadcast enabled */
+ 1, /* multicast enabled */
+ 0, /* do not accept pause frames */
+ 0 /* promisc mode disabled */
+ );
+}
Property changes on: trunk/sys/mips/nlm/dev/net/sgmii.c
___________________________________________________________________
Added: svn:eol-style
## -0,0 +1 ##
+native
\ No newline at end of property
Added: svn:keywords
## -0,0 +1 ##
+MidnightBSD=%H
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+text/plain
\ No newline at end of property
Added: trunk/sys/mips/nlm/dev/net/ucore/crt0_basic.S
===================================================================
--- trunk/sys/mips/nlm/dev/net/ucore/crt0_basic.S (rev 0)
+++ trunk/sys/mips/nlm/dev/net/ucore/crt0_basic.S 2018-05-26 21:55:02 UTC (rev 9987)
@@ -0,0 +1,67 @@
+/* $MidnightBSD$ */
+/*-
+ * Copyright (c) 2003-2012 Broadcom Corporation
+ * All Rights Reserved
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in
+ * the documentation and/or other materials provided with the
+ * distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY BROADCOM ``AS IS'' AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL BROADCOM OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
+ * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
+ * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
+ * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * $FreeBSD: stable/10/sys/mips/nlm/dev/net/ucore/crt0_basic.S 233545 2012-03-27 14:05:12Z jchandra $
+ */
+
+#include <machine/asm.h>
+
+ .text
+ .align 2
+ .globl _start
+ .ent _start
+_start:
+ .set noreorder
+ la gp, _gp
+ .end _start
+
+ .globl __stack
+
+ .ent zerobss
+zerobss:
+ la v0, _fbss
+ la v1, _end
+3:
+ sw zero, 0(v0)
+ bltu v0,v1,3b
+ addiu v0,v0,4 # executed in delay slot
+ la sp, __stack # set stack pointer
+ .end zerobss
+
+ .ent init
+init:
+ addiu a1,sp,32 # argv = sp + 32
+ addiu a2,sp,40 # envp = sp + 40
+ sw zero,(a1) # argv[argc] = 0
+ sw zero,(a2) # envp[0] = 0
+ jal main # call the program start function
+ move a0,zero # set argc to 0
+1: b 1b
+ nop
+ .end init
+
Property changes on: trunk/sys/mips/nlm/dev/net/ucore/crt0_basic.S
___________________________________________________________________
Added: svn:eol-style
## -0,0 +1 ##
+native
\ No newline at end of property
Added: svn:keywords
## -0,0 +1 ##
+MidnightBSD=%H
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+text/plain
\ No newline at end of property
Added: trunk/sys/mips/nlm/dev/net/ucore/ld.ucore.S
===================================================================
--- trunk/sys/mips/nlm/dev/net/ucore/ld.ucore.S (rev 0)
+++ trunk/sys/mips/nlm/dev/net/ucore/ld.ucore.S 2018-05-26 21:55:02 UTC (rev 9987)
@@ -0,0 +1,163 @@
+/* $MidnightBSD$ */
+/*-
+ * Copyright (c) 2003-2012 Broadcom Corporation
+ * All Rights Reserved
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in
+ * the documentation and/or other materials provided with the
+ * distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY BROADCOM ``AS IS'' AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL BROADCOM OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
+ * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
+ * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
+ * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * $FreeBSD: stable/10/sys/mips/nlm/dev/net/ucore/ld.ucore.S 233545 2012-03-27 14:05:12Z jchandra $
+ */
+
+ENTRY(_start)
+OUTPUT_FORMAT(elf32-tradbigmips)
+__DYNAMIC = 0;
+
+SECTIONS
+{
+ . = 0x0;
+ _loadaddr = . ;
+
+ /* ----------------------------------------- */
+
+ .text : {
+ _ftext = . ;
+ PROVIDE (eprol = .);
+ _shim_reg = . ;
+ *(.text)
+ *(.text.*)
+ *(.gnu.linkonce.t*)
+ *(.mips16.fn.*)
+ *(.mips16.call.*)
+ }
+ .init : {
+ KEEP(*(.init))
+ *(.init)
+ }
+ .fini : {
+ *(.fini)
+ }
+ .rel.sdata : {
+ PROVIDE (__runtime_reloc_start = .);
+ *(.rel.sdata)
+ PROVIDE (__runtime_reloc_stop = .);
+ }
+ PROVIDE (etext = .);
+ .ctors :
+ {
+ KEEP (*crtbegin.o(.ctors))
+ KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))
+ KEEP (*(SORT(.ctors.*)))
+ KEEP (*(.ctors))
+ }
+ .dtors :
+ {
+ KEEP (*crtbegin.o(.dtors))
+ KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))
+ KEEP (*(SORT(.dtors.*)))
+ KEEP (*(.dtors))
+ }
+ . = .;
+ .rodata : {
+ *(.rdata)
+ *(.rodata)
+ *(.rodata.*)
+ *(.gnu.linkonce.r*)
+ }
+ . = . + (0x1000 - .) ;
+
+ /* ----------------------------------------- */
+
+ . = 0x8000 ;
+ magicstart = . ;
+ .magicregs : {
+ *(.magicregs)
+ }
+ magicend = . ;
+
+ /* ----------------------------------------- */
+
+ . = 0x18000 ;
+ shmemstart = . ;
+ .sharedmem : {
+ *(.sharedmem)
+ }
+ shmemend = . ;
+
+ /* ----------------------------------------- */
+
+ . = 0xFF800 ;
+ .data : {
+ *(.data)
+ *(.data.*)
+ *(.gnu.linkonce.d*)
+ }
+ . = ALIGN(8);
+ .lit8 : {
+ *(.lit8)
+ }
+ .lit4 : {
+ *(.lit4)
+ }
+ .sdata : {
+ *(.sdata)
+ *(.sdata.*)
+ *(.gnu.linkonce.s*)
+ }
+ . = ALIGN (8);
+ PROVIDE (edata = .);
+ _edata = .;
+ _fbss = .;
+ .sbss : {
+ *(.sbss)
+ *(.scommon)
+ }
+ .bss : {
+ _bss_start = . ;
+ *(.bss)
+ *(COMMON)
+ }
+ _bss_end = . ;
+ _end = .;
+
+ _gp = . ;
+ __global = _gp ;
+ . = ALIGN (8);
+
+ PROVIDE(__stackmarker = .) ;
+
+ . = 0xFFA00 ;
+
+ /* 32 + 4(argc) + 4(argv), aligned to 64 */
+ PROVIDE(__stack = . - 64);
+
+ /* ----------------------------------------- */
+
+ . = 0xFFE00 ;
+ .pktbuf : {
+ *(.pktbuf)
+ }
+ . = . + (0x100000 - .) ;
+
+ PROVIDE(_endaddr = 0x0 + 0x100000);
+}
Property changes on: trunk/sys/mips/nlm/dev/net/ucore/ld.ucore.S
___________________________________________________________________
Added: svn:eol-style
## -0,0 +1 ##
+native
\ No newline at end of property
Added: svn:keywords
## -0,0 +1 ##
+MidnightBSD=%H
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+text/plain
\ No newline at end of property
Added: trunk/sys/mips/nlm/dev/net/ucore/ucore.h
===================================================================
--- trunk/sys/mips/nlm/dev/net/ucore/ucore.h (rev 0)
+++ trunk/sys/mips/nlm/dev/net/ucore/ucore.h 2018-05-26 21:55:02 UTC (rev 9987)
@@ -0,0 +1,353 @@
+/* $MidnightBSD$ */
+/*-
+ * Copyright (c) 2003-2012 Broadcom Corporation
+ * All Rights Reserved
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in
+ * the documentation and/or other materials provided with the
+ * distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY BROADCOM ``AS IS'' AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL BROADCOM OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
+ * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
+ * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
+ * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * $FreeBSD: stable/10/sys/mips/nlm/dev/net/ucore/ucore.h 233657 2012-03-29 11:46:29Z jchandra $
+ */
+#ifndef __NLM_UCORE_H__
+#define __NLM_UCORE_H__
+
+/* Microcode registers */
+#define UCORE_OUTBUF_DONE 0x8000
+#define UCORE_RX_PKT_RDY 0x8004
+#define UCORE_RX_PKT_INFO 0x8008
+#define UCORE_CAM0 0x800c
+#define UCORE_CAM1 0x8010
+#define UCORE_CAM2 0x8014
+#define UCORE_CAM3 0x8018
+#define UCORE_CAM_RESULT 0x801c
+#define UCORE_CSUMINFO 0x8020
+#define UCORE_CRCINFO 0x8024
+#define UCORE_CRCPOS 0x8028
+#define UCORE_FR_FIFOEMPTY 0x802c
+#define UCORE_PKT_DISTR 0x8030
+
+#define PACKET_MEMORY 0xFFE00
+#define PACKET_DATA_OFFSET 64
+#define SHARED_SCRATCH_MEM 0x18000
+
+/* Distribution mode */
+#define VAL_PDM(x) (((x) & 0x7) << 0)
+
+/* Dest distribution or distribution list */
+#define VAL_DEST(x) (((x) & 0x3ff) << 8)
+#define VAL_PDL(x) (((x) & 0xf) << 4)
+
+/*output buffer done*/
+#define VAL_FSV(x) (x << 19)
+#define VAL_FFS(x) (x << 14)
+
+#define FWD_DEST_ONLY 1
+#define FWD_ENQ_DIST_VEC 2
+#define FWD_ENQ_DEST 3
+#define FWD_DIST_VEC 4
+#define FWD_ENQ_DIST_VEC_SER 6
+#define FWD_ENQ_DEST_SER 7
+
+#define USE_HASH_DST (1 << 20)
+
+static __inline unsigned int
+nlm_read_ucore_reg(int reg)
+{
+ volatile unsigned int *addr = (volatile void *)reg;
+
+ return (*addr);
+}
+
+static __inline void
+nlm_write_ucore_reg(int reg, unsigned int val)
+{
+ volatile unsigned int *addr = (volatile void *)reg;
+
+ *addr = val;
+}
+
+#define NLM_DEFINE_UCORE(name, reg) \
+static __inline unsigned int \
+nlm_read_ucore_##name(void) \
+{ \
+ return nlm_read_ucore_reg(reg); \
+} \
+ \
+static __inline void \
+nlm_write_ucore_##name(unsigned int v) \
+{ \
+ nlm_write_ucore_reg(reg, v); \
+} struct __hack
+
+
+NLM_DEFINE_UCORE(obufdone, UCORE_OUTBUF_DONE);
+NLM_DEFINE_UCORE(rxpktrdy, UCORE_RX_PKT_RDY);
+NLM_DEFINE_UCORE(rxpktinfo, UCORE_RX_PKT_INFO);
+NLM_DEFINE_UCORE(cam0, UCORE_CAM0);
+NLM_DEFINE_UCORE(cam1, UCORE_CAM1);
+NLM_DEFINE_UCORE(cam2, UCORE_CAM2);
+NLM_DEFINE_UCORE(cam3, UCORE_CAM3);
+NLM_DEFINE_UCORE(camresult, UCORE_CAM_RESULT);
+NLM_DEFINE_UCORE(csuminfo, UCORE_CSUMINFO);
+NLM_DEFINE_UCORE(crcinfo, UCORE_CRCINFO);
+NLM_DEFINE_UCORE(crcpos, UCORE_CRCPOS);
+NLM_DEFINE_UCORE(freefifo_empty, UCORE_FR_FIFOEMPTY);
+NLM_DEFINE_UCORE(pktdistr, UCORE_PKT_DISTR);
+
+/*
+ * l3cachelines - number of cache lines to allocate into l3
+ * fsv - 0 : use interface-id for selecting the free fifo pool
+ * 1 : use free fifo pool selected by FFS field
+ * ffs - selects which free fifo pool to use to take a free fifo
+ * prepad_en - If this field is set to 1, part or all of the
+ * 64 byte prepad seen by micro engines, is written
+ * infront of every packet.
+ * prepad_ovride - If this field is 1, the ucore system uses
+ * prepad configuration defined in this register,
+ * 0 means that it uses the configuration defined
+ * in NAE RX_CONFIG register
+ * prepad_size - number of 16 byte words in the 64-byte prepad
+ * seen by micro engines and dma'ed to memory as
+ * pkt prepad. This field is meaningful only if
+ * prepad_en and prepad_ovride is set.
+ * 0 : 1 word
+ * 1 : 2 words
+ * 2 : 3 words
+ * 3 : 4 words
+ * prepad[0-3]: writing 0 to this means that the 1st 16 byte offset
+ * of prepad in micro engine, gets setup as prepad0/1/2/3.
+ * prepad word.
+ * 1 : means 2nd 16 byte chunk in prepad0/1/2/3
+ * 2 : means 3rd 16 byte chunk in prepad0/1/2/3
+ * 3 : means 4rth 16 byte chunk in prepad0/1/2/3
+ * pkt_discard - packet will be discarded if this is set to 1
+ * rd5 - value (single bit) to be inserted in bit 5, the unclassified
+ * pkt bit of receive descriptor. If this bit is set, HPRE bit
+ * should also be set in ucore_rxpktready register
+ */
+static __inline__ void
+nlm_ucore_pkt_done(int l3cachelines, int fsv, int ffs, int prepad_en,
+ int prepad_ovride, int prepad_size, int prepad0, int prepad1,
+ int prepad2, int prepad3, int pkt_discard, int rd5)
+{
+ unsigned int val = 0;
+
+ val |= ((l3cachelines & 0xfff) << 20);
+ val |= ((fsv & 0x1) << 19);
+ val |= ((ffs & 0x1f) << 14);
+ val |= ((prepad_en & 0x1) << 3);
+ val |= ((prepad_ovride & 0x1) << 2);
+ val |= ((prepad_size & 0x3) << 12);
+ val |= ((prepad0 & 0x3) << 4);
+ val |= ((prepad1 & 0x3) << 6);
+ val |= ((prepad2 & 0x3) << 8);
+ val |= ((prepad3 & 0x3) << 10);
+ val |= ((pkt_discard & 0x1) << 1);
+ val |= ((rd5 & 0x1) << 0);
+
+ nlm_write_ucore_obufdone(val);
+}
+
+/* Get the class full vector field from POE.
+ * The POE maintains a threshold for each class.
+ * A bit in this field will be set corresponding to the class approaching
+ * class full status.
+ */
+static __inline__ int
+nlm_ucore_get_rxpkt_poeclassfullvec(unsigned int pktrdy)
+{
+ return ((pktrdy >> 24) & 0xff);
+}
+
+/* This function returns 1 if the hardware parser extraction process
+ * resulted in an error. Else, returns 0.
+ */
+static __inline__ int
+nlm_ucore_get_rxpkt_hwparsererr(unsigned int pktrdy)
+{
+ return ((pktrdy >> 23) & 0x1);
+}
+
+/* This function returns the context number assigned to incoming
+ * packet
+ */
+static __inline__ int
+nlm_ucore_get_rxpkt_context(unsigned int pktrdy)
+{
+ return ((pktrdy >> 13) & 0x3ff);
+}
+
+/* this function returns the channel number of incoming packet,
+ * and applies only to interlaken.
+ */
+static __inline__ int
+nlm_ucore_get_rxpkt_channel(unsigned int pktrdy)
+{
+ return ((pktrdy >> 5) & 0xff);
+}
+
+/* This function returns the interface number on which the pkt
+ * was received
+ */
+static __inline__ int
+nlm_ucore_get_rxpkt_interface(unsigned int pktrdy)
+{
+ return (pktrdy & 0x1f);
+}
+
+/* This function returns 1 if end of packet (EOP) is set in
+ * packet data.
+ */
+static __inline__ int
+nlm_ucore_get_rxpkt_eop(unsigned int rxpkt_info)
+{
+ return ((rxpkt_info >> 9) & 0x1);
+}
+
+/* This function returns packet length of received pkt */
+static __inline__ int
+nlm_ucore_get_rxpktlen(unsigned int rxpkt_info)
+{
+ return (rxpkt_info & 0x1ff);
+}
+
+/* this function sets up the ucore TCAM keys. */
+static __inline__ void
+nlm_ucore_setup_camkey(unsigned int cam_key0, unsigned int cam_key1,
+ unsigned int cam_key2, unsigned int cam_key3)
+{
+ nlm_write_ucore_cam0(cam_key0);
+ nlm_write_ucore_cam1(cam_key1);
+ nlm_write_ucore_cam2(cam_key2);
+ nlm_write_ucore_cam3(cam_key3);
+}
+
+/* This function checks if the cam result is valid or not.
+ * If valid, it returns the result, else it returns 0.
+ */
+static __inline__ int
+nlm_ucore_get_cam_result(unsigned int cam_result)
+{
+ if (((cam_result >> 15) & 0x1) == 1) /* valid result */
+ return (cam_result & 0x3fff);
+
+ return 0;
+}
+
+/* This function sets up the csum in ucore.
+ * iphdr_start - defines the start of ip header (to check - is this byte
+ * position???)
+ * iphdr_len - This field is auto filled by h/w parser if zero, else
+ * the value defined will be used.
+ */
+static __inline__ void
+nlm_ucore_csum_setup(int iphdr_start, int iphdr_len)
+{
+ unsigned int val = 0;
+
+ val |= ((iphdr_len & 0xff) << 8);
+ val |= (iphdr_len & 0xff);
+ nlm_write_ucore_csuminfo(val);
+}
+
+/* crcpos - position of crc in pkt. If crc position is within startcrc and
+ * endcrc, zero out these bytes in the packet before computing crc. This
+ * field is not needed for FCoE.
+ * cps - If 1, uses the polynomial in RX_CRC_POLY1 of NAE register.
+ * if 0, uses the polynomial in RX_CRC_POLY0 of NAE register.
+ * fcoe - If this is 1, crc calculation starts from 'startCRC' and the CRC
+ * engine ends calculation before the last byte.
+ * cbm - if 1, enables crc byte mirroring, where bits within a byte will get
+ * reversed (mirrored) during calculation of crc.
+ * cfi - If 1, performs a final inversion of crc before comarison is done during
+ * pkt reception.
+ * startcrc - This field is always required for both FCoE and SCTP crc.
+ * endcrc - This information needs to be setup only for SCTP. For FCoE this
+ * information is provided by hardware.
+ * valid - if set to 1, CRC status is placed into bit 2 of rx descriptor
+ * if set to 0, TCP checksum status is placed into bit 2 of rx descriptor
+ * keysize - defines the number of bytes in the pre-pad that contains the key
+ */
+static __inline__ void
+nlm_ucore_crc_setup(int crcpos, int cps, int cfi, int cbm, int fcoe,
+ int keysize, int valid, int startcrc, int endcrc)
+{
+ unsigned int val = 0;
+
+ val |= ((cfi & 0x1) << 20);
+ val |= ((cbm & 0x1) << 19);
+ val |= ((fcoe & 0x1) << 18);
+ val |= ((cps & 0x1) << 16);
+ val |= (crcpos & 0xffff);
+
+ nlm_write_ucore_crcpos(val);
+
+ val = 0;
+ val |= ((keysize & 0x3f) << 25);
+ val |= ((valid & 0x1) << 24);
+ val |= ((endcrc & 0xffff) << 8);
+ val |= (startcrc & 0xff);
+
+ nlm_write_ucore_crcinfo(val);
+}
+
+/* This function returns a fifo empty vector, where each bit provides
+ * the status of a fifo pool, where if the pool is empty the bit gets
+ * set to 1.
+ */
+static __inline__ int
+nlm_ucore_get_fifoempty(unsigned int fifoempty)
+{
+ return (fifoempty & 0xfffff);
+}
+
+/* This function controls how POE will distribute the packet.
+ * pdm - is the packet distribution mode, where
+ * 0x0 - means packet distribution mode is not used
+ * 0x1 - means forwarding based on destination only (no enqueue)
+ * 0x2 - means forwarding based on FID and distr vector (enqueue)
+ * 0x3 - means forwarding based on dest and FID (enqueue)
+ * 0x4 - means forwarding based on distr vec (no enqueue)
+ * 0x6 - means forward based on FID (enqueue), distr vec and serial mode
+ * 0x7 - means forward based on FID (enqueue), dest and serial mode
+ * mc3 - If 1, then the 3 most significant bits of distribution list are taken
+ * from context->class_table
+ * pdl - poe distribution list
+ * dest - fixed destination setup
+ * hash - if 1, use hash based destination
+ */
+static __inline__ void
+nlm_ucore_setup_poepktdistr(int pdm, int mc3, int pdl, int dest, int hash)
+{
+ unsigned int val = 0;
+
+ val |= ((hash & 0x1) << 20);
+ val |= ((dest & 0xfff) << 8);
+ val |= ((pdl & 0xf) << 4);
+ val |= ((mc3 & 0x1) << 3);
+ val |= (pdm & 0x7);
+
+ nlm_write_ucore_pktdistr(val);
+}
+
+#endif
Property changes on: trunk/sys/mips/nlm/dev/net/ucore/ucore.h
___________________________________________________________________
Added: svn:eol-style
## -0,0 +1 ##
+native
\ No newline at end of property
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## -0,0 +1 ##
+MidnightBSD=%H
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## -0,0 +1 ##
+text/plain
\ No newline at end of property
Added: trunk/sys/mips/nlm/dev/net/ucore/ucore_app.c
===================================================================
--- trunk/sys/mips/nlm/dev/net/ucore/ucore_app.c (rev 0)
+++ trunk/sys/mips/nlm/dev/net/ucore/ucore_app.c 2018-05-26 21:55:02 UTC (rev 9987)
@@ -0,0 +1,59 @@
+/* $MidnightBSD$ */
+/*-
+ * Copyright (c) 2003-2012 Broadcom Corporation
+ * All Rights Reserved
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in
+ * the documentation and/or other materials provided with the
+ * distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY BROADCOM ``AS IS'' AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL BROADCOM OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
+ * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
+ * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
+ * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * $FreeBSD: stable/10/sys/mips/nlm/dev/net/ucore/ucore_app.c 233657 2012-03-29 11:46:29Z jchandra $
+ */
+
+#include "ucore.h"
+
+int main(void)
+{
+#if 0
+ volatile unsigned int *pkt =
+ (volatile unsigned int *) (PACKET_MEMORY + PACKET_DATA_OFFSET);
+ int intf, hw_parser_error, context;
+#endif
+ unsigned int pktrdy;
+ int num_cachelines = 1518 / 64 ; /* pktsize / L3 cacheline size */
+
+
+ /* Spray packets to using distribution vector */
+ while (1) {
+ pktrdy = nlm_read_ucore_rxpktrdy();
+#if 0
+ intf = pktrdy & 0x1f;
+ context = (pktrdy >> 13) & 0x3ff;
+ hw_parser_error = (pktrdy >> 23) & 0x1;
+#endif
+ nlm_ucore_setup_poepktdistr(FWD_DIST_VEC, 0, 0, 0, 0);
+ nlm_ucore_pkt_done(num_cachelines, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0);
+ }
+
+ return (0);
+}
Property changes on: trunk/sys/mips/nlm/dev/net/ucore/ucore_app.c
___________________________________________________________________
Added: svn:eol-style
## -0,0 +1 ##
+native
\ No newline at end of property
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## -0,0 +1 ##
+MidnightBSD=%H
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+text/plain
\ No newline at end of property
Added: trunk/sys/mips/nlm/dev/net/xaui.c
===================================================================
--- trunk/sys/mips/nlm/dev/net/xaui.c (rev 0)
+++ trunk/sys/mips/nlm/dev/net/xaui.c 2018-05-26 21:55:02 UTC (rev 9987)
@@ -0,0 +1,250 @@
+/* $MidnightBSD$ */
+/*-
+ * Copyright (c) 2003-2012 Broadcom Corporation
+ * All Rights Reserved
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in
+ * the documentation and/or other materials provided with the
+ * distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY BROADCOM ``AS IS'' AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL BROADCOM OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
+ * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
+ * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
+ * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <sys/cdefs.h>
+__FBSDID("$FreeBSD: stable/10/sys/mips/nlm/dev/net/xaui.c 255368 2013-09-07 18:26:16Z jchandra $");
+#include <sys/types.h>
+#include <sys/systm.h>
+
+#include <mips/nlm/hal/mips-extns.h>
+#include <mips/nlm/hal/haldefs.h>
+#include <mips/nlm/hal/iomap.h>
+#include <mips/nlm/hal/sys.h>
+#include <mips/nlm/hal/nae.h>
+#include <mips/nlm/hal/mdio.h>
+#include <mips/nlm/hal/sgmii.h>
+#include <mips/nlm/hal/xaui.h>
+
+#include <mips/nlm/xlp.h>
+void
+nlm_xaui_pcs_init(uint64_t nae_base, int xaui_cplx_mask)
+{
+ int block, lane_ctrl, reg;
+ int cplx_lane_enable;
+ int lane_enable = 0;
+ uint32_t regval;
+
+ cplx_lane_enable = LM_XAUI |
+ (LM_XAUI << 4) |
+ (LM_XAUI << 8) |
+ (LM_XAUI << 12);
+
+ if (xaui_cplx_mask == 0)
+ return;
+
+ /* write 0x2 to enable SGMII for all lane */
+ block = 7;
+
+ if (xaui_cplx_mask & 0x3) { /* Complexes 0, 1 */
+ lane_enable = nlm_read_nae_reg(nae_base,
+ NAE_REG(block, LANE_CFG, LANE_CFG_CPLX_0_1));
+ if (xaui_cplx_mask & 0x1) { /* Complex 0 */
+ lane_enable &= ~(0xFFFF);
+ lane_enable |= cplx_lane_enable;
+ }
+ if (xaui_cplx_mask & 0x2) { /* Complex 1 */
+ lane_enable &= ~(0xFFFF<<16);
+ lane_enable |= (cplx_lane_enable << 16);
+ }
+ nlm_write_nae_reg(nae_base,
+ NAE_REG(block, LANE_CFG, LANE_CFG_CPLX_0_1),
+ lane_enable);
+ }
+ lane_enable = 0;
+ if (xaui_cplx_mask & 0xc) { /* Complexes 2, 3 */
+ lane_enable = nlm_read_nae_reg(nae_base,
+ NAE_REG(block, LANE_CFG, LANE_CFG_CPLX_2_3));
+ if (xaui_cplx_mask & 0x4) { /* Complex 2 */
+ lane_enable &= ~(0xFFFF);
+ lane_enable |= cplx_lane_enable;
+ }
+ if (xaui_cplx_mask & 0x8) { /* Complex 3 */
+ lane_enable &= ~(0xFFFF<<16);
+ lane_enable |= (cplx_lane_enable << 16);
+ }
+ nlm_write_nae_reg(nae_base,
+ NAE_REG(block, LANE_CFG, LANE_CFG_CPLX_2_3),
+ lane_enable);
+ }
+
+ /* Bring txpll out of reset */
+ for (block = 0; block < 4; block++) {
+ if ((xaui_cplx_mask & (1 << block)) == 0)
+ continue;
+
+ for (lane_ctrl = PHY_LANE_0_CTRL;
+ lane_ctrl <= PHY_LANE_3_CTRL; lane_ctrl++) {
+ if (!nlm_is_xlp8xx_ax())
+ xlp_nae_lane_reset_txpll(nae_base,
+ block, lane_ctrl, PHYMODE_XAUI);
+ else
+ xlp_ax_nae_lane_reset_txpll(nae_base, block,
+ lane_ctrl, PHYMODE_XAUI);
+ }
+ }
+
+ /* Wait for Rx & TX clock stable */
+ for (block = 0; block < 4; block++) {
+ if ((xaui_cplx_mask & (1 << block)) == 0)
+ continue;
+
+ for (lane_ctrl = PHY_LANE_0_CTRL;
+ lane_ctrl <= PHY_LANE_3_CTRL; lane_ctrl++) {
+
+ reg = NAE_REG(block, PHY, lane_ctrl - 4);
+ /* Wait for TX clock to be set */
+ do {
+ regval = nlm_read_nae_reg(nae_base, reg);
+ } while ((regval & LANE_TX_CLK) == 0);
+
+ /* Wait for RX clock to be set */
+ do {
+ regval = nlm_read_nae_reg(nae_base, reg);
+ } while ((regval & LANE_RX_CLK) == 0);
+
+ /* Wait for XAUI Lane fault to be cleared */
+ do {
+ regval = nlm_read_nae_reg(nae_base, reg);
+ } while ((regval & XAUI_LANE_FAULT) != 0);
+ }
+ }
+}
+
+void
+nlm_nae_setup_rx_mode_xaui(uint64_t base, int nblock, int iface, int port_type,
+ int broadcast_en, int multicast_en, int pause_en, int promisc_en)
+{
+ uint32_t val;
+
+ val = ((broadcast_en & 0x1) << 10) |
+ ((pause_en & 0x1) << 9) |
+ ((multicast_en & 0x1) << 8) |
+ ((promisc_en & 0x1) << 7) | /* unicast_enable - enables promisc mode */
+ 1; /* MAC address is always valid */
+
+ nlm_write_nae_reg(base, XAUI_MAC_FILTER_CFG(nblock), val);
+}
+
+void
+nlm_nae_setup_mac_addr_xaui(uint64_t base, int nblock, int iface,
+ int port_type, unsigned char *mac_addr)
+{
+ nlm_write_nae_reg(base,
+ XAUI_MAC_ADDR0_LO(nblock),
+ (mac_addr[5] << 24) |
+ (mac_addr[4] << 16) |
+ (mac_addr[3] << 8) |
+ mac_addr[2]);
+
+ nlm_write_nae_reg(base,
+ XAUI_MAC_ADDR0_HI(nblock),
+ (mac_addr[1] << 24) |
+ (mac_addr[0] << 16));
+
+ nlm_write_nae_reg(base,
+ XAUI_MAC_ADDR_MASK0_LO(nblock),
+ 0xffffffff);
+ nlm_write_nae_reg(base,
+ XAUI_MAC_ADDR_MASK0_HI(nblock),
+ 0xffffffff);
+
+ nlm_nae_setup_rx_mode_xaui(base, nblock, iface,
+ XAUIC,
+ 1, /* broadcast enabled */
+ 1, /* multicast enabled */
+ 0, /* do not accept pause frames */
+ 0 /* promisc mode disabled */
+ );
+}
+
+void
+nlm_config_xaui_mtu(uint64_t nae_base, int nblock,
+ int max_tx_frame_sz, int max_rx_frame_sz)
+{
+ uint32_t tx_words = max_tx_frame_sz >> 2; /* max_tx_frame_sz / 4 */
+
+ /* write max frame length */
+ nlm_write_nae_reg(nae_base,
+ XAUI_MAX_FRAME_LEN(nblock),
+ ((tx_words & 0x3ff) << 16) | (max_rx_frame_sz & 0xffff));
+}
+
+void
+nlm_config_xaui(uint64_t nae_base, int nblock,
+ int max_tx_frame_sz, int max_rx_frame_sz, int vlan_pri_en)
+{
+ uint32_t val;
+
+ val = nlm_read_nae_reg(nae_base, XAUI_NETIOR_XGMAC_CTRL1(nblock));
+ val &= ~(0x1 << 11); /* clear soft reset */
+ nlm_write_nae_reg(nae_base, XAUI_NETIOR_XGMAC_CTRL1(nblock), val);
+
+ val = nlm_read_nae_reg(nae_base, XAUI_NETIOR_XGMAC_CTRL1(nblock));
+ val &= ~(0x3 << 11); /* clear soft reset and hard reset */
+ nlm_write_nae_reg(nae_base, XAUI_NETIOR_XGMAC_CTRL1(nblock), val);
+ nlm_write_nae_reg(nae_base, XAUI_CONFIG0(nblock), 0xffffffff);
+ nlm_write_nae_reg(nae_base, XAUI_CONFIG0(nblock), 0);
+
+ /* Enable tx/rx frame */
+ val = 0x000010A8;
+ val |= XAUI_CONFIG_LENCHK;
+ val |= XAUI_CONFIG_GENFCS;
+ val |= XAUI_CONFIG_PAD_64;
+ nlm_write_nae_reg(nae_base, XAUI_CONFIG1(nblock), val);
+
+ /* write max frame length */
+ nlm_config_xaui_mtu(nae_base, nblock, max_tx_frame_sz,
+ max_rx_frame_sz);
+
+ /* set stats counter */
+ val = nlm_read_nae_reg(nae_base, XAUI_NETIOR_XGMAC_CTRL1(nblock));
+ val |= (0x1 << NETIOR_XGMAC_VLAN_DC_POS);
+ val |= (0x1 << NETIOR_XGMAC_STATS_EN_POS);
+ if (vlan_pri_en) {
+ val |= (0x1 << NETIOR_XGMAC_TX_PFC_EN_POS);
+ val |= (0x1 << NETIOR_XGMAC_RX_PFC_EN_POS);
+ val |= (0x1 << NETIOR_XGMAC_TX_PAUSE_POS);
+ } else {
+ val &= ~(0x1 << NETIOR_XGMAC_TX_PFC_EN_POS);
+ val |= (0x1 << NETIOR_XGMAC_TX_PAUSE_POS);
+ }
+ nlm_write_nae_reg(nae_base, XAUI_NETIOR_XGMAC_CTRL1(nblock), val);
+ /* configure on / off timer */
+ if (vlan_pri_en)
+ val = 0xF1230000; /* PFC mode, offtimer = 0xf123, ontimer = 0 */
+ else
+ val = 0x0000F123; /* link level FC mode, offtimer = 0xf123 */
+ nlm_write_nae_reg(nae_base, XAUI_NETIOR_XGMAC_CTRL2(nblock), val);
+
+ /* set xaui tx threshold */
+ val = nlm_read_nae_reg(nae_base, XAUI_NETIOR_XGMAC_CTRL3(nblock));
+ val &= ~(0x1f << 10);
+ val |= ~(15 << 10);
+ nlm_write_nae_reg(nae_base, XAUI_NETIOR_XGMAC_CTRL3(nblock), val);
+}
Property changes on: trunk/sys/mips/nlm/dev/net/xaui.c
___________________________________________________________________
Added: svn:eol-style
## -0,0 +1 ##
+native
\ No newline at end of property
Added: svn:keywords
## -0,0 +1 ##
+MidnightBSD=%H
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+text/plain
\ No newline at end of property
Added: trunk/sys/mips/nlm/dev/net/xlpge.c
===================================================================
--- trunk/sys/mips/nlm/dev/net/xlpge.c (rev 0)
+++ trunk/sys/mips/nlm/dev/net/xlpge.c 2018-05-26 21:55:02 UTC (rev 9987)
@@ -0,0 +1,1545 @@
+/* $MidnightBSD$ */
+/*-
+ * Copyright (c) 2003-2012 Broadcom Corporation
+ * All Rights Reserved
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in
+ * the documentation and/or other materials provided with the
+ * distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY BROADCOM ``AS IS'' AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL BROADCOM OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
+ * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
+ * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
+ * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <sys/cdefs.h>
+__FBSDID("$FreeBSD: stable/10/sys/mips/nlm/dev/net/xlpge.c 314667 2017-03-04 13:03:31Z avg $");
+#include <sys/endian.h>
+#include <sys/systm.h>
+#include <sys/sockio.h>
+#include <sys/param.h>
+#include <sys/lock.h>
+#include <sys/mutex.h>
+#include <sys/proc.h>
+#include <sys/limits.h>
+#include <sys/bus.h>
+#include <sys/mbuf.h>
+#include <sys/malloc.h>
+#include <sys/kernel.h>
+#include <sys/module.h>
+#include <sys/socket.h>
+#define __RMAN_RESOURCE_VISIBLE
+#include <sys/rman.h>
+#include <sys/taskqueue.h>
+
+#include <net/if.h>
+#include <net/if_arp.h>
+#include <net/ethernet.h>
+#include <net/if_dl.h>
+#include <net/if_media.h>
+#include <net/bpf.h>
+#include <net/if_types.h>
+#include <net/if_vlan_var.h>
+
+#include <dev/pci/pcivar.h>
+
+#include <netinet/in_systm.h>
+#include <netinet/in.h>
+#include <netinet/ip.h>
+
+#include <vm/vm.h>
+#include <vm/pmap.h>
+#include <vm/uma.h>
+
+#include <machine/reg.h>
+#include <machine/cpu.h>
+#include <machine/mips_opcode.h>
+#include <machine/asm.h>
+#include <machine/cpuregs.h>
+
+#include <machine/param.h>
+#include <machine/intr_machdep.h>
+#include <machine/clock.h> /* for DELAY */
+#include <machine/bus.h>
+#include <machine/resource.h>
+#include <mips/nlm/hal/haldefs.h>
+#include <mips/nlm/hal/iomap.h>
+#include <mips/nlm/hal/mips-extns.h>
+#include <mips/nlm/hal/cop2.h>
+#include <mips/nlm/hal/fmn.h>
+#include <mips/nlm/hal/sys.h>
+#include <mips/nlm/hal/nae.h>
+#include <mips/nlm/hal/mdio.h>
+#include <mips/nlm/hal/sgmii.h>
+#include <mips/nlm/hal/xaui.h>
+#include <mips/nlm/hal/poe.h>
+#include <ucore_app_bin.h>
+#include <mips/nlm/hal/ucore_loader.h>
+#include <mips/nlm/xlp.h>
+#include <mips/nlm/board.h>
+#include <mips/nlm/msgring.h>
+
+#include <dev/mii/mii.h>
+#include <dev/mii/miivar.h>
+#include "miidevs.h"
+#include <dev/mii/brgphyreg.h>
+#include "miibus_if.h"
+#include <sys/sysctl.h>
+
+#include <mips/nlm/dev/net/xlpge.h>
+
+/*#define XLP_DRIVER_LOOPBACK*/
+
+static struct nae_port_config nae_port_config[64];
+
+int poe_cl_tbl[MAX_POE_CLASSES] = {
+ 0x0, 0x249249,
+ 0x492492, 0x6db6db,
+ 0x924924, 0xb6db6d,
+ 0xdb6db6, 0xffffff
+};
+
+/* #define DUMP_PACKET */
+
+static uint64_t
+nlm_paddr_ld(uint64_t paddr)
+{
+ uint64_t xkaddr = 0x9800000000000000 | paddr;
+
+ return (nlm_load_dword_daddr(xkaddr));
+}
+
+struct nlm_xlp_portdata ifp_ports[64];
+static uma_zone_t nl_tx_desc_zone;
+
+/* This implementation will register the following tree of device
+ * registration:
+ * pcibus
+ * |
+ * xlpnae (1 instance - virtual entity)
+ * |
+ * xlpge
+ * (18 sgmii / 4 xaui / 2 interlaken instances)
+ * |
+ * miibus
+ */
+
+static int nlm_xlpnae_probe(device_t);
+static int nlm_xlpnae_attach(device_t);
+static int nlm_xlpnae_detach(device_t);
+static int nlm_xlpnae_suspend(device_t);
+static int nlm_xlpnae_resume(device_t);
+static int nlm_xlpnae_shutdown(device_t);
+
+static device_method_t nlm_xlpnae_methods[] = {
+ /* Methods from the device interface */
+ DEVMETHOD(device_probe, nlm_xlpnae_probe),
+ DEVMETHOD(device_attach, nlm_xlpnae_attach),
+ DEVMETHOD(device_detach, nlm_xlpnae_detach),
+ DEVMETHOD(device_suspend, nlm_xlpnae_suspend),
+ DEVMETHOD(device_resume, nlm_xlpnae_resume),
+ DEVMETHOD(device_shutdown, nlm_xlpnae_shutdown),
+
+ DEVMETHOD(bus_driver_added, bus_generic_driver_added),
+
+ DEVMETHOD_END
+};
+
+static driver_t nlm_xlpnae_driver = {
+ "xlpnae",
+ nlm_xlpnae_methods,
+ sizeof(struct nlm_xlpnae_softc)
+};
+
+static devclass_t nlm_xlpnae_devclass;
+
+static int nlm_xlpge_probe(device_t);
+static int nlm_xlpge_attach(device_t);
+static int nlm_xlpge_detach(device_t);
+static int nlm_xlpge_suspend(device_t);
+static int nlm_xlpge_resume(device_t);
+static int nlm_xlpge_shutdown(device_t);
+
+/* mii override functions */
+static int nlm_xlpge_mii_read(struct device *, int, int);
+static int nlm_xlpge_mii_write(struct device *, int, int, int);
+static void nlm_xlpge_mii_statchg(device_t);
+
+static device_method_t nlm_xlpge_methods[] = {
+ /* Methods from the device interface */
+ DEVMETHOD(device_probe, nlm_xlpge_probe),
+ DEVMETHOD(device_attach, nlm_xlpge_attach),
+ DEVMETHOD(device_detach, nlm_xlpge_detach),
+ DEVMETHOD(device_suspend, nlm_xlpge_suspend),
+ DEVMETHOD(device_resume, nlm_xlpge_resume),
+ DEVMETHOD(device_shutdown, nlm_xlpge_shutdown),
+
+ /* Methods from the nexus bus needed for explicitly
+ * probing children when driver is loaded as a kernel module
+ */
+ DEVMETHOD(miibus_readreg, nlm_xlpge_mii_read),
+ DEVMETHOD(miibus_writereg, nlm_xlpge_mii_write),
+ DEVMETHOD(miibus_statchg, nlm_xlpge_mii_statchg),
+
+ /* Terminate method list */
+ DEVMETHOD_END
+};
+
+static driver_t nlm_xlpge_driver = {
+ "xlpge",
+ nlm_xlpge_methods,
+ sizeof(struct nlm_xlpge_softc)
+};
+
+static devclass_t nlm_xlpge_devclass;
+
+DRIVER_MODULE(xlpnae, pci, nlm_xlpnae_driver, nlm_xlpnae_devclass, 0, 0);
+DRIVER_MODULE(xlpge, xlpnae, nlm_xlpge_driver, nlm_xlpge_devclass, 0, 0);
+DRIVER_MODULE(miibus, xlpge, miibus_driver, miibus_devclass, 0, 0);
+
+MODULE_DEPEND(pci, xlpnae, 1, 1, 1);
+MODULE_DEPEND(xlpnae, xlpge, 1, 1, 1);
+MODULE_DEPEND(xlpge, ether, 1, 1, 1);
+MODULE_DEPEND(xlpge, miibus, 1, 1, 1);
+
+#define SGMII_RCV_CONTEXT_WIDTH 8
+
+/* prototypes */
+static void nlm_xlpge_msgring_handler(int vc, int size,
+ int code, int srcid, struct nlm_fmn_msg *msg, void *data);
+static void nlm_xlpge_submit_rx_free_desc(struct nlm_xlpge_softc *sc, int num);
+static void nlm_xlpge_init(void *addr);
+static void nlm_xlpge_port_disable(struct nlm_xlpge_softc *sc);
+static void nlm_xlpge_port_enable(struct nlm_xlpge_softc *sc);
+
+/* globals */
+int dbg_on = 1;
+int cntx2port[524];
+
+static __inline void
+atomic_incr_long(unsigned long *addr)
+{
+ atomic_add_long(addr, 1);
+}
+
+/*
+ * xlpnae driver implementation
+ */
+static int
+nlm_xlpnae_probe(device_t dev)
+{
+ if (pci_get_vendor(dev) != PCI_VENDOR_NETLOGIC ||
+ pci_get_device(dev) != PCI_DEVICE_ID_NLM_NAE)
+ return (ENXIO);
+
+ return (BUS_PROBE_DEFAULT);
+}
+
+static void
+nlm_xlpnae_print_frin_desc_carving(struct nlm_xlpnae_softc *sc)
+{
+ int intf;
+ uint32_t value;
+ int start, size;
+
+ /* XXXJC: use max_ports instead of 20 ? */
+ for (intf = 0; intf < 20; intf++) {
+ nlm_write_nae_reg(sc->base, NAE_FREE_IN_FIFO_CFG,
+ (0x80000000 | intf));
+ value = nlm_read_nae_reg(sc->base, NAE_FREE_IN_FIFO_CFG);
+ size = 2 * ((value >> 20) & 0x3ff);
+ start = 2 * ((value >> 8) & 0x1ff);
+ }
+}
+
+static void
+nlm_config_egress(struct nlm_xlpnae_softc *sc, int nblock,
+ int context_base, int hwport, int max_channels)
+{
+ int offset, num_channels;
+ uint32_t data;
+
+ num_channels = sc->portcfg[hwport].num_channels;
+
+ data = (2048 << 12) | (hwport << 4) | 1;
+ nlm_write_nae_reg(sc->base, NAE_TX_IF_BURSTMAX_CMD, data);
+
+ data = ((context_base + num_channels - 1) << 22) |
+ (context_base << 12) | (hwport << 4) | 1;
+ nlm_write_nae_reg(sc->base, NAE_TX_DDR_ACTVLIST_CMD, data);
+
+ config_egress_fifo_carvings(sc->base, hwport,
+ context_base, num_channels, max_channels, sc->portcfg);
+ config_egress_fifo_credits(sc->base, hwport,
+ context_base, num_channels, max_channels, sc->portcfg);
+
+ data = nlm_read_nae_reg(sc->base, NAE_DMA_TX_CREDIT_TH);
+ data |= (1 << 25) | (1 << 24);
+ nlm_write_nae_reg(sc->base, NAE_DMA_TX_CREDIT_TH, data);
+
+ for (offset = 0; offset < num_channels; offset++) {
+ nlm_write_nae_reg(sc->base, NAE_TX_SCHED_MAP_CMD1,
+ NAE_DRR_QUANTA);
+ data = (hwport << 15) | ((context_base + offset) << 5);
+ if (sc->cmplx_type[nblock] == ILC)
+ data |= (offset << 20);
+ nlm_write_nae_reg(sc->base, NAE_TX_SCHED_MAP_CMD0, data | 1);
+ nlm_write_nae_reg(sc->base, NAE_TX_SCHED_MAP_CMD0, data);
+ }
+}
+
+static int
+xlpnae_get_maxchannels(struct nlm_xlpnae_softc *sc)
+{
+ int maxchans = 0;
+ int i;
+
+ for (i = 0; i < sc->max_ports; i++) {
+ if (sc->portcfg[i].type == UNKNOWN)
+ continue;
+ maxchans += sc->portcfg[i].num_channels;
+ }
+
+ return (maxchans);
+}
+
+static void
+nlm_setup_interface(struct nlm_xlpnae_softc *sc, int nblock,
+ int port, uint32_t cur_flow_base, uint32_t flow_mask,
+ int max_channels, int context)
+{
+ uint64_t nae_base = sc->base;
+ int mtu = 1536; /* XXXJC: don't hard code */
+ uint32_t ucore_mask;
+
+ if (sc->cmplx_type[nblock] == XAUIC)
+ nlm_config_xaui(nae_base, nblock, mtu,
+ mtu, sc->portcfg[port].vlan_pri_en);
+ nlm_config_freein_fifo_uniq_cfg(nae_base,
+ port, sc->portcfg[port].free_desc_sizes);
+ nlm_config_ucore_iface_mask_cfg(nae_base,
+ port, sc->portcfg[port].ucore_mask);
+
+ nlm_program_flow_cfg(nae_base, port, cur_flow_base, flow_mask);
+
+ if (sc->cmplx_type[nblock] == SGMIIC)
+ nlm_configure_sgmii_interface(nae_base, nblock, port, mtu, 0);
+
+ nlm_config_egress(sc, nblock, context, port, max_channels);
+
+ nlm_nae_init_netior(nae_base, sc->nblocks);
+ nlm_nae_open_if(nae_base, nblock, sc->cmplx_type[nblock], port,
+ sc->portcfg[port].free_desc_sizes);
+
+ /* XXXJC: check mask calculation */
+ ucore_mask = (1 << sc->nucores) - 1;
+ nlm_nae_init_ucore(nae_base, port, ucore_mask);
+}
+
+static void
+nlm_setup_interfaces(struct nlm_xlpnae_softc *sc)
+{
+ uint64_t nae_base;
+ uint32_t cur_slot, cur_slot_base;
+ uint32_t cur_flow_base, port, flow_mask;
+ int max_channels;
+ int i, context;
+
+ cur_slot = 0;
+ cur_slot_base = 0;
+ cur_flow_base = 0;
+ nae_base = sc->base;
+ flow_mask = nlm_get_flow_mask(sc->total_num_ports);
+ /* calculate max_channels */
+ max_channels = xlpnae_get_maxchannels(sc);
+
+ port = 0;
+ context = 0;
+ for (i = 0; i < sc->max_ports; i++) {
+ if (sc->portcfg[i].type == UNKNOWN)
+ continue;
+ nlm_setup_interface(sc, sc->portcfg[i].block, i, cur_flow_base,
+ flow_mask, max_channels, context);
+ cur_flow_base += sc->per_port_num_flows;
+ context += sc->portcfg[i].num_channels;
+ }
+}
+
+static void
+nlm_xlpnae_init(int node, struct nlm_xlpnae_softc *sc)
+{
+ uint64_t nae_base;
+ uint32_t ucoremask = 0;
+ uint32_t val;
+ int i;
+
+ nae_base = sc->base;
+
+ nlm_nae_flush_free_fifo(nae_base, sc->nblocks);
+ nlm_deflate_frin_fifo_carving(nae_base, sc->max_ports);
+ nlm_reset_nae(node);
+
+ for (i = 0; i < sc->nucores; i++) /* XXXJC: code repeated below */
+ ucoremask |= (0x1 << i);
+ printf("Loading 0x%x ucores with microcode\n", ucoremask);
+ nlm_ucore_load_all(nae_base, ucoremask, 1);
+
+ val = nlm_set_device_frequency(node, DFS_DEVICE_NAE, sc->freq);
+ printf("Setup NAE frequency to %dMHz\n", val);
+
+ nlm_mdio_reset_all(nae_base);
+
+ printf("Initialze SGMII PCS for blocks 0x%x\n", sc->sgmiimask);
+ nlm_sgmii_pcs_init(nae_base, sc->sgmiimask);
+
+ printf("Initialze XAUI PCS for blocks 0x%x\n", sc->xauimask);
+ nlm_xaui_pcs_init(nae_base, sc->xauimask);
+
+ /* clear NETIOR soft reset */
+ nlm_write_nae_reg(nae_base, NAE_LANE_CFG_SOFTRESET, 0x0);
+
+ /* Disable RX enable bit in RX_CONFIG */
+ val = nlm_read_nae_reg(nae_base, NAE_RX_CONFIG);
+ val &= 0xfffffffe;
+ nlm_write_nae_reg(nae_base, NAE_RX_CONFIG, val);
+
+ if (nlm_is_xlp8xx_ax() == 0) {
+ val = nlm_read_nae_reg(nae_base, NAE_TX_CONFIG);
+ val &= ~(1 << 3);
+ nlm_write_nae_reg(nae_base, NAE_TX_CONFIG, val);
+ }
+
+ nlm_setup_poe_class_config(nae_base, MAX_POE_CLASSES,
+ sc->ncontexts, poe_cl_tbl);
+
+ nlm_setup_vfbid_mapping(nae_base);
+
+ nlm_setup_flow_crc_poly(nae_base, sc->flow_crc_poly);
+
+ nlm_setup_rx_cal_cfg(nae_base, sc->max_ports, sc->portcfg);
+ /* note: xlp8xx Ax does not have Tx Calendering */
+ if (!nlm_is_xlp8xx_ax())
+ nlm_setup_tx_cal_cfg(nae_base, sc->max_ports, sc->portcfg);
+
+ nlm_setup_interfaces(sc);
+ nlm_config_poe(sc->poe_base, sc->poedv_base);
+
+ if (sc->hw_parser_en)
+ nlm_enable_hardware_parser(nae_base);
+
+ if (sc->prepad_en)
+ nlm_prepad_enable(nae_base, sc->prepad_size);
+
+ if (sc->ieee_1588_en)
+ nlm_setup_1588_timer(sc->base, sc->portcfg);
+}
+
+static void
+nlm_xlpnae_update_pde(void *dummy __unused)
+{
+ struct nlm_xlpnae_softc *sc;
+ uint32_t dv[NUM_WORDS_PER_DV];
+ device_t dev;
+ int vec;
+
+ dev = devclass_get_device(devclass_find("xlpnae"), 0);
+ sc = device_get_softc(dev);
+
+ nlm_write_poe_reg(sc->poe_base, POE_DISTR_EN, 0);
+ for (vec = 0; vec < NUM_DIST_VEC; vec++) {
+ if (nlm_get_poe_distvec(vec, dv) != 0)
+ continue;
+
+ nlm_write_poe_distvec(sc->poedv_base, vec, dv);
+ }
+ nlm_write_poe_reg(sc->poe_base, POE_DISTR_EN, 1);
+}
+
+SYSINIT(nlm_xlpnae_update_pde, SI_SUB_SMP, SI_ORDER_ANY,
+ nlm_xlpnae_update_pde, NULL);
+
+/* configuration common for sgmii, xaui, ilaken goes here */
+static void
+nlm_setup_portcfg(struct nlm_xlpnae_softc *sc, struct xlp_nae_ivars *naep,
+ int block, int port)
+{
+ int i;
+ uint32_t ucore_mask = 0;
+ struct xlp_block_ivars *bp;
+ struct xlp_port_ivars *p;
+
+ bp = &(naep->block_ivars[block]);
+ p = &(bp->port_ivars[port & 0x3]);
+
+ sc->portcfg[port].node = p->node;
+ sc->portcfg[port].block = p->block;
+ sc->portcfg[port].port = p->port;
+ sc->portcfg[port].type = p->type;
+ sc->portcfg[port].mdio_bus = p->mdio_bus;
+ sc->portcfg[port].phy_addr = p->phy_addr;
+ sc->portcfg[port].loopback_mode = p->loopback_mode;
+ sc->portcfg[port].num_channels = p->num_channels;
+ if (p->free_desc_sizes != MCLBYTES) {
+ printf("[%d, %d] Error: free_desc_sizes %d != %d\n",
+ block, port, p->free_desc_sizes, MCLBYTES);
+ return;
+ }
+ sc->portcfg[port].free_desc_sizes = p->free_desc_sizes;
+ for (i = 0; i < sc->nucores; i++) /* XXXJC: configure this */
+ ucore_mask |= (0x1 << i);
+ sc->portcfg[port].ucore_mask = ucore_mask;
+ sc->portcfg[port].vlan_pri_en = p->vlan_pri_en;
+ sc->portcfg[port].num_free_descs = p->num_free_descs;
+ sc->portcfg[port].iface_fifo_size = p->iface_fifo_size;
+ sc->portcfg[port].rxbuf_size = p->rxbuf_size;
+ sc->portcfg[port].rx_slots_reqd = p->rx_slots_reqd;
+ sc->portcfg[port].tx_slots_reqd = p->tx_slots_reqd;
+ sc->portcfg[port].pseq_fifo_size = p->pseq_fifo_size;
+
+ sc->portcfg[port].stg2_fifo_size = p->stg2_fifo_size;
+ sc->portcfg[port].eh_fifo_size = p->eh_fifo_size;
+ sc->portcfg[port].frout_fifo_size = p->frout_fifo_size;
+ sc->portcfg[port].ms_fifo_size = p->ms_fifo_size;
+ sc->portcfg[port].pkt_fifo_size = p->pkt_fifo_size;
+ sc->portcfg[port].pktlen_fifo_size = p->pktlen_fifo_size;
+ sc->portcfg[port].max_stg2_offset = p->max_stg2_offset;
+ sc->portcfg[port].max_eh_offset = p->max_eh_offset;
+ sc->portcfg[port].max_frout_offset = p->max_frout_offset;
+ sc->portcfg[port].max_ms_offset = p->max_ms_offset;
+ sc->portcfg[port].max_pmem_offset = p->max_pmem_offset;
+ sc->portcfg[port].stg1_2_credit = p->stg1_2_credit;
+ sc->portcfg[port].stg2_eh_credit = p->stg2_eh_credit;
+ sc->portcfg[port].stg2_frout_credit = p->stg2_frout_credit;
+ sc->portcfg[port].stg2_ms_credit = p->stg2_ms_credit;
+ sc->portcfg[port].ieee1588_inc_intg = p->ieee1588_inc_intg;
+ sc->portcfg[port].ieee1588_inc_den = p->ieee1588_inc_den;
+ sc->portcfg[port].ieee1588_inc_num = p->ieee1588_inc_num;
+ sc->portcfg[port].ieee1588_userval = p->ieee1588_userval;
+ sc->portcfg[port].ieee1588_ptpoff = p->ieee1588_ptpoff;
+ sc->portcfg[port].ieee1588_tmr1 = p->ieee1588_tmr1;
+ sc->portcfg[port].ieee1588_tmr2 = p->ieee1588_tmr2;
+ sc->portcfg[port].ieee1588_tmr3 = p->ieee1588_tmr3;
+
+ sc->total_free_desc += sc->portcfg[port].free_desc_sizes;
+ sc->total_num_ports++;
+}
+
+static int
+nlm_xlpnae_attach(device_t dev)
+{
+ struct xlp_nae_ivars *nae_ivars;
+ struct nlm_xlpnae_softc *sc;
+ device_t tmpd;
+ uint32_t dv[NUM_WORDS_PER_DV];
+ int port, i, j, nchan, nblock, node, qstart, qnum;
+ int offset, context, txq_base, rxvcbase;
+ uint64_t poe_pcibase, nae_pcibase;
+
+ node = pci_get_slot(dev) / 8;
+ nae_ivars = &xlp_board_info.nodes[node].nae_ivars;
+
+ sc = device_get_softc(dev);
+ sc->xlpnae_dev = dev;
+ sc->node = nae_ivars->node;
+ sc->base = nlm_get_nae_regbase(sc->node);
+ sc->poe_base = nlm_get_poe_regbase(sc->node);
+ sc->poedv_base = nlm_get_poedv_regbase(sc->node);
+ sc->portcfg = nae_port_config;
+ sc->blockmask = nae_ivars->blockmask;
+ sc->ilmask = nae_ivars->ilmask;
+ sc->xauimask = nae_ivars->xauimask;
+ sc->sgmiimask = nae_ivars->sgmiimask;
+ sc->nblocks = nae_ivars->nblocks;
+ sc->freq = nae_ivars->freq;
+
+ /* flow table generation is done by CRC16 polynomial */
+ sc->flow_crc_poly = nae_ivars->flow_crc_poly;
+
+ sc->hw_parser_en = nae_ivars->hw_parser_en;
+ sc->prepad_en = nae_ivars->prepad_en;
+ sc->prepad_size = nae_ivars->prepad_size;
+ sc->ieee_1588_en = nae_ivars->ieee_1588_en;
+
+ nae_pcibase = nlm_get_nae_pcibase(sc->node);
+ sc->ncontexts = nlm_read_reg(nae_pcibase, XLP_PCI_DEVINFO_REG5);
+ sc->nucores = nlm_num_uengines(nae_pcibase);
+
+ for (nblock = 0; nblock < sc->nblocks; nblock++) {
+ sc->cmplx_type[nblock] = nae_ivars->block_ivars[nblock].type;
+ sc->portmask[nblock] = nae_ivars->block_ivars[nblock].portmask;
+ }
+
+ for (i = 0; i < sc->ncontexts; i++)
+ cntx2port[i] = 18; /* 18 is an invalid port */
+
+ if (sc->nblocks == 5)
+ sc->max_ports = 18; /* 8xx has a block 4 with 2 ports */
+ else
+ sc->max_ports = sc->nblocks * PORTS_PER_CMPLX;
+
+ for (i = 0; i < sc->max_ports; i++)
+ sc->portcfg[i].type = UNKNOWN; /* Port Not Present */
+ /*
+ * Now setup all internal fifo carvings based on
+ * total number of ports in the system
+ */
+ sc->total_free_desc = 0;
+ sc->total_num_ports = 0;
+ port = 0;
+ context = 0;
+ txq_base = nlm_qidstart(nae_pcibase);
+ rxvcbase = txq_base + sc->ncontexts;
+ for (i = 0; i < sc->nblocks; i++) {
+ uint32_t portmask;
+
+ if ((nae_ivars->blockmask & (1 << i)) == 0) {
+ port += 4;
+ continue;
+ }
+ portmask = nae_ivars->block_ivars[i].portmask;
+ for (j = 0; j < PORTS_PER_CMPLX; j++, port++) {
+ if ((portmask & (1 << j)) == 0)
+ continue;
+ nlm_setup_portcfg(sc, nae_ivars, i, port);
+ nchan = sc->portcfg[port].num_channels;
+ for (offset = 0; offset < nchan; offset++)
+ cntx2port[context + offset] = port;
+ sc->portcfg[port].txq = txq_base + context;
+ sc->portcfg[port].rxfreeq = rxvcbase + port;
+ context += nchan;
+ }
+ }
+
+ poe_pcibase = nlm_get_poe_pcibase(sc->node);
+ sc->per_port_num_flows =
+ nlm_poe_max_flows(poe_pcibase) / sc->total_num_ports;
+
+ /* zone for P2P descriptors */
+ nl_tx_desc_zone = uma_zcreate("NL Tx Desc",
+ sizeof(struct xlpge_tx_desc), NULL, NULL, NULL, NULL,
+ NAE_CACHELINE_SIZE, 0);
+
+ /* NAE FMN messages have CMS src station id's in the
+ * range of qstart to qnum.
+ */
+ qstart = nlm_qidstart(nae_pcibase);
+ qnum = nlm_qnum(nae_pcibase);
+ if (register_msgring_handler(qstart, qstart + qnum - 1,
+ nlm_xlpge_msgring_handler, sc)) {
+ panic("Couldn't register NAE msgring handler\n");
+ }
+
+ /* POE FMN messages have CMS src station id's in the
+ * range of qstart to qnum.
+ */
+ qstart = nlm_qidstart(poe_pcibase);
+ qnum = nlm_qnum(poe_pcibase);
+ if (register_msgring_handler(qstart, qstart + qnum - 1,
+ nlm_xlpge_msgring_handler, sc)) {
+ panic("Couldn't register POE msgring handler\n");
+ }
+
+ nlm_xlpnae_init(node, sc);
+
+ for (i = 0; i < sc->max_ports; i++) {
+ char desc[32];
+ int block, port;
+
+ if (sc->portcfg[i].type == UNKNOWN)
+ continue;
+ block = sc->portcfg[i].block;
+ port = sc->portcfg[i].port;
+ tmpd = device_add_child(dev, "xlpge", i);
+ device_set_ivars(tmpd,
+ &(nae_ivars->block_ivars[block].port_ivars[port]));
+ sprintf(desc, "XLP NAE Port %d,%d", block, port);
+ device_set_desc_copy(tmpd, desc);
+ }
+ nlm_setup_iface_fifo_cfg(sc->base, sc->max_ports, sc->portcfg);
+ nlm_setup_rx_base_config(sc->base, sc->max_ports, sc->portcfg);
+ nlm_setup_rx_buf_config(sc->base, sc->max_ports, sc->portcfg);
+ nlm_setup_freein_fifo_cfg(sc->base, sc->portcfg);
+ nlm_program_nae_parser_seq_fifo(sc->base, sc->max_ports, sc->portcfg);
+
+ nlm_xlpnae_print_frin_desc_carving(sc);
+ bus_generic_probe(dev);
+ bus_generic_attach(dev);
+
+ /*
+ * Enable only boot cpu at this point, full distribution comes
+ * only after SMP is started
+ */
+ nlm_write_poe_reg(sc->poe_base, POE_DISTR_EN, 0);
+ nlm_calc_poe_distvec(0x1, 0, 0, 0, 0x1 << XLPGE_RX_VC, dv);
+ nlm_write_poe_distvec(sc->poedv_base, 0, dv);
+ nlm_write_poe_reg(sc->poe_base, POE_DISTR_EN, 1);
+
+ return (0);
+}
+
+static int
+nlm_xlpnae_detach(device_t dev)
+{
+ /* TODO - free zone here */
+ return (0);
+}
+
+static int
+nlm_xlpnae_suspend(device_t dev)
+{
+ return (0);
+}
+
+static int
+nlm_xlpnae_resume(device_t dev)
+{
+ return (0);
+}
+
+static int
+nlm_xlpnae_shutdown(device_t dev)
+{
+ return (0);
+}
+
+/*
+ * xlpge driver implementation
+ */
+
+static void
+nlm_xlpge_mac_set_rx_mode(struct nlm_xlpge_softc *sc)
+{
+ if (sc->if_flags & IFF_PROMISC) {
+ if (sc->type == SGMIIC)
+ nlm_nae_setup_rx_mode_sgmii(sc->base_addr,
+ sc->block, sc->port, sc->type, 1 /* broadcast */,
+ 1/* multicast */, 0 /* pause */, 1 /* promisc */);
+ else
+ nlm_nae_setup_rx_mode_xaui(sc->base_addr,
+ sc->block, sc->port, sc->type, 1 /* broadcast */,
+ 1/* multicast */, 0 /* pause */, 1 /* promisc */);
+ } else {
+ if (sc->type == SGMIIC)
+ nlm_nae_setup_rx_mode_sgmii(sc->base_addr,
+ sc->block, sc->port, sc->type, 1 /* broadcast */,
+ 1/* multicast */, 0 /* pause */, 0 /* promisc */);
+ else
+ nlm_nae_setup_rx_mode_xaui(sc->base_addr,
+ sc->block, sc->port, sc->type, 1 /* broadcast */,
+ 1/* multicast */, 0 /* pause */, 0 /* promisc */);
+ }
+}
+
+static int
+nlm_xlpge_ioctl(struct ifnet *ifp, u_long command, caddr_t data)
+{
+ struct mii_data *mii;
+ struct nlm_xlpge_softc *sc;
+ struct ifreq *ifr;
+ int error;
+
+ sc = ifp->if_softc;
+ error = 0;
+ ifr = (struct ifreq *)data;
+
+ switch (command) {
+ case SIOCSIFFLAGS:
+ XLPGE_LOCK(sc);
+ sc->if_flags = ifp->if_flags;
+ if (ifp->if_flags & IFF_UP) {
+ if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0)
+ nlm_xlpge_init(sc);
+ else
+ nlm_xlpge_port_enable(sc);
+ nlm_xlpge_mac_set_rx_mode(sc);
+ sc->link = NLM_LINK_UP;
+ } else {
+ if (ifp->if_drv_flags & IFF_DRV_RUNNING)
+ nlm_xlpge_port_disable(sc);
+ sc->link = NLM_LINK_DOWN;
+ }
+ XLPGE_UNLOCK(sc);
+ error = 0;
+ break;
+ case SIOCGIFMEDIA:
+ case SIOCSIFMEDIA:
+ if (sc->mii_bus != NULL) {
+ mii = device_get_softc(sc->mii_bus);
+ error = ifmedia_ioctl(ifp, ifr, &mii->mii_media,
+ command);
+ }
+ break;
+ default:
+ error = ether_ioctl(ifp, command, data);
+ break;
+ }
+
+ return (error);
+}
+
+static int
+xlpge_tx(struct ifnet *ifp, struct mbuf *mbuf_chain)
+{
+ struct nlm_fmn_msg msg;
+ struct xlpge_tx_desc *p2p;
+ struct nlm_xlpge_softc *sc;
+ struct mbuf *m;
+ vm_paddr_t paddr;
+ int fbid, dst, pos, err;
+ int ret = 0, tx_msgstatus, retries;
+
+ err = 0;
+ if (mbuf_chain == NULL)
+ return (0);
+
+ sc = ifp->if_softc;
+ p2p = NULL;
+ if (!(ifp->if_drv_flags & IFF_DRV_RUNNING) ||
+ ifp->if_drv_flags & IFF_DRV_OACTIVE) {
+ err = ENXIO;
+ goto fail;
+ }
+
+ /* free a few in coming messages on the fb vc */
+ xlp_handle_msg_vc(1 << XLPGE_FB_VC, 2);
+
+ /* vfb id table is setup to map cpu to vc 3 of the cpu */
+ fbid = nlm_cpuid();
+ dst = sc->txq;
+
+ pos = 0;
+ p2p = uma_zalloc(nl_tx_desc_zone, M_NOWAIT);
+ if (p2p == NULL) {
+ printf("alloc fail\n");
+ err = ENOBUFS;
+ goto fail;
+ }
+
+ for (m = mbuf_chain; m != NULL; m = m->m_next) {
+ vm_offset_t buf = (vm_offset_t) m->m_data;
+ int len = m->m_len;
+ int frag_sz;
+ uint64_t desc;
+
+ /*printf("m_data = %p len %d\n", m->m_data, len); */
+ while (len) {
+ if (pos == XLP_NTXFRAGS - 3) {
+ device_printf(sc->xlpge_dev,
+ "packet defrag %d\n",
+ m_length(mbuf_chain, NULL));
+ err = ENOBUFS; /* TODO fix error */
+ goto fail;
+ }
+ paddr = vtophys(buf);
+ frag_sz = PAGE_SIZE - (buf & PAGE_MASK);
+ if (len < frag_sz)
+ frag_sz = len;
+ desc = nae_tx_desc(P2D_NEOP, 0, 127,
+ frag_sz, paddr);
+ p2p->frag[pos] = htobe64(desc);
+ pos++;
+ len -= frag_sz;
+ buf += frag_sz;
+ }
+ }
+
+ KASSERT(pos != 0, ("Zero-length mbuf chain?\n"));
+
+ /* Make the last one P2D EOP */
+ p2p->frag[pos-1] |= htobe64((uint64_t)P2D_EOP << 62);
+
+ /* stash useful pointers in the desc */
+ p2p->frag[XLP_NTXFRAGS-3] = 0xf00bad;
+ p2p->frag[XLP_NTXFRAGS-2] = (uintptr_t)p2p;
+ p2p->frag[XLP_NTXFRAGS-1] = (uintptr_t)mbuf_chain;
+
+ paddr = vtophys(p2p);
+ msg.msg[0] = nae_tx_desc(P2P, 0, fbid, pos, paddr);
+
+ for (retries = 16; retries > 0; retries--) {
+ ret = nlm_fmn_msgsend(dst, 1, FMN_SWCODE_NAE, &msg);
+ if (ret == 0)
+ return (0);
+ }
+
+fail:
+ if (ret != 0) {
+ tx_msgstatus = nlm_read_c2_txmsgstatus();
+ if ((tx_msgstatus >> 24) & 0x1)
+ device_printf(sc->xlpge_dev, "Transmit queue full - ");
+ if ((tx_msgstatus >> 3) & 0x1)
+ device_printf(sc->xlpge_dev, "ECC error - ");
+ if ((tx_msgstatus >> 2) & 0x1)
+ device_printf(sc->xlpge_dev, "Pending Sync - ");
+ if ((tx_msgstatus >> 1) & 0x1)
+ device_printf(sc->xlpge_dev,
+ "Insufficient input queue credits - ");
+ if (tx_msgstatus & 0x1)
+ device_printf(sc->xlpge_dev,
+ "Insufficient output queue credits - ");
+ }
+ device_printf(sc->xlpge_dev, "Send failed! err = %d\n", err);
+ if (p2p)
+ uma_zfree(nl_tx_desc_zone, p2p);
+ m_freem(mbuf_chain);
+ /*atomic_incr_long(&ifp->if_iqdrops); */
+ ifp->if_iqdrops++;
+ return (err);
+}
+
+
+static int
+nlm_xlpge_gmac_config_speed(struct nlm_xlpge_softc *sc)
+{
+ struct mii_data *mii;
+
+ if (sc->type == XAUIC || sc->type == ILC)
+ return (0);
+
+ if (sc->mii_bus) {
+ mii = device_get_softc(sc->mii_bus);
+ mii_pollstat(mii);
+ }
+
+ return (0);
+}
+
+static void
+nlm_xlpge_port_disable(struct nlm_xlpge_softc *sc)
+{
+ struct ifnet *ifp;
+
+ ifp = sc->xlpge_if;
+ ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
+
+ callout_stop(&sc->xlpge_callout);
+ nlm_mac_disable(sc->base_addr, sc->block, sc->type, sc->port);
+}
+
+static void
+nlm_mii_pollstat(void *arg)
+{
+ struct nlm_xlpge_softc *sc = (struct nlm_xlpge_softc *)arg;
+ struct mii_data *mii = NULL;
+
+ if (sc->mii_bus) {
+ mii = device_get_softc(sc->mii_bus);
+
+ KASSERT(mii != NULL, ("mii ptr is NULL"));
+
+ mii_pollstat(mii);
+
+ callout_reset(&sc->xlpge_callout, hz,
+ nlm_mii_pollstat, sc);
+ }
+}
+
+static void
+nlm_xlpge_port_enable(struct nlm_xlpge_softc *sc)
+{
+ if ((sc->type != SGMIIC) && (sc->type != XAUIC))
+ return;
+ nlm_mac_enable(sc->base_addr, sc->block, sc->type, sc->port);
+ nlm_mii_pollstat((void *)sc);
+}
+
+static void
+nlm_xlpge_init(void *addr)
+{
+ struct nlm_xlpge_softc *sc;
+ struct ifnet *ifp;
+ struct mii_data *mii = NULL;
+
+ sc = (struct nlm_xlpge_softc *)addr;
+ ifp = sc->xlpge_if;
+
+ if (ifp->if_drv_flags & IFF_DRV_RUNNING)
+ return;
+
+ if (sc->mii_bus) {
+ mii = device_get_softc(sc->mii_bus);
+ mii_mediachg(mii);
+ }
+
+ nlm_xlpge_gmac_config_speed(sc);
+ ifp->if_drv_flags |= IFF_DRV_RUNNING;
+ ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
+ nlm_xlpge_port_enable(sc);
+
+ /* start the callout */
+ callout_reset(&sc->xlpge_callout, hz, nlm_mii_pollstat, sc);
+}
+
+/*
+ * Read the MAC address from FDT or board eeprom.
+ */
+static void
+xlpge_read_mac_addr(struct nlm_xlpge_softc *sc)
+{
+
+ xlpge_get_macaddr(sc->dev_addr);
+ /* last octet is port specific */
+ sc->dev_addr[5] += (sc->block * 4) + sc->port;
+
+ if (sc->type == SGMIIC)
+ nlm_nae_setup_mac_addr_sgmii(sc->base_addr, sc->block,
+ sc->port, sc->type, sc->dev_addr);
+ else if (sc->type == XAUIC)
+ nlm_nae_setup_mac_addr_xaui(sc->base_addr, sc->block,
+ sc->port, sc->type, sc->dev_addr);
+}
+
+
+static int
+xlpge_mediachange(struct ifnet *ifp)
+{
+ return (0);
+}
+
+static void
+xlpge_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr)
+{
+ struct nlm_xlpge_softc *sc;
+ struct mii_data *md;
+
+ md = NULL;
+ sc = ifp->if_softc;
+
+ if (sc->mii_bus)
+ md = device_get_softc(sc->mii_bus);
+
+ ifmr->ifm_status = IFM_AVALID;
+ ifmr->ifm_active = IFM_ETHER;
+
+ if (sc->link == NLM_LINK_DOWN)
+ return;
+
+ if (md != NULL)
+ ifmr->ifm_active = md->mii_media.ifm_cur->ifm_media;
+ ifmr->ifm_status |= IFM_ACTIVE;
+}
+
+static int
+nlm_xlpge_ifinit(struct nlm_xlpge_softc *sc)
+{
+ struct ifnet *ifp;
+ device_t dev;
+ int port = sc->block * 4 + sc->port;
+
+ dev = sc->xlpge_dev;
+ ifp = sc->xlpge_if = if_alloc(IFT_ETHER);
+ /*(sc->network_sc)->ifp_ports[port].xlpge_if = ifp;*/
+ ifp_ports[port].xlpge_if = ifp;
+
+ if (ifp == NULL) {
+ device_printf(dev, "cannot if_alloc()\n");
+ return (ENOSPC);
+ }
+ ifp->if_softc = sc;
+ if_initname(ifp, device_get_name(dev), device_get_unit(dev));
+ ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
+ sc->if_flags = ifp->if_flags;
+ /*ifp->if_capabilities = IFCAP_TXCSUM | IFCAP_VLAN_HWTAGGING;*/
+ ifp->if_capabilities = 0;
+ ifp->if_capenable = ifp->if_capabilities;
+ ifp->if_ioctl = nlm_xlpge_ioctl;
+ ifp->if_init = nlm_xlpge_init ;
+ ifp->if_hwassist = 0;
+ ifp->if_snd.ifq_drv_maxlen = NLM_XLPGE_TXQ_SIZE; /* TODO: make this a sysint */
+ IFQ_SET_MAXLEN(&ifp->if_snd, ifp->if_snd.ifq_drv_maxlen);
+ IFQ_SET_READY(&ifp->if_snd);
+
+ ifmedia_init(&sc->xlpge_mii.mii_media, 0, xlpge_mediachange,
+ xlpge_mediastatus);
+ ifmedia_add(&sc->xlpge_mii.mii_media, IFM_ETHER | IFM_AUTO, 0, NULL);
+ ifmedia_set(&sc->xlpge_mii.mii_media, IFM_ETHER | IFM_AUTO);
+ sc->xlpge_mii.mii_media.ifm_media =
+ sc->xlpge_mii.mii_media.ifm_cur->ifm_media;
+ xlpge_read_mac_addr(sc);
+
+ ether_ifattach(ifp, sc->dev_addr);
+
+ /* override if_transmit : per ifnet(9), do it after if_attach */
+ ifp->if_transmit = xlpge_tx;
+
+ return (0);
+}
+
+static int
+nlm_xlpge_probe(device_t dev)
+{
+ return (BUS_PROBE_DEFAULT);
+}
+
+static void *
+get_buf(void)
+{
+ struct mbuf *m_new;
+ uint64_t *md;
+#ifdef INVARIANTS
+ vm_paddr_t temp1, temp2;
+#endif
+
+ if ((m_new = m_getcl(M_NOWAIT, MT_DATA, M_PKTHDR)) == NULL)
+ return (NULL);
+ m_new->m_len = m_new->m_pkthdr.len = MCLBYTES;
+ KASSERT(((uintptr_t)m_new->m_data & (NAE_CACHELINE_SIZE - 1)) == 0,
+ ("m_new->m_data is not cacheline aligned"));
+ md = (uint64_t *)m_new->m_data;
+ md[0] = (intptr_t)m_new; /* Back Ptr */
+ md[1] = 0xf00bad;
+ m_adj(m_new, NAE_CACHELINE_SIZE);
+
+#ifdef INVARIANTS
+ temp1 = vtophys((vm_offset_t) m_new->m_data);
+ temp2 = vtophys((vm_offset_t) m_new->m_data + 1536);
+ KASSERT((temp1 + 1536) == temp2,
+ ("Alloced buffer is not contiguous"));
+#endif
+ return ((void *)m_new->m_data);
+}
+
+static void
+nlm_xlpge_mii_init(device_t dev, struct nlm_xlpge_softc *sc)
+{
+ int error;
+
+ error = mii_attach(dev, &sc->mii_bus, sc->xlpge_if,
+ xlpge_mediachange, xlpge_mediastatus,
+ BMSR_DEFCAPMASK, sc->phy_addr, MII_OFFSET_ANY, 0);
+
+ if (error) {
+ device_printf(dev, "attaching PHYs failed\n");
+ sc->mii_bus = NULL;
+ }
+
+ if (sc->mii_bus != NULL) {
+ /* enable MDIO interrupts in the PHY */
+ /* XXXJC: TODO */
+ }
+}
+
+static int
+xlpge_stats_sysctl(SYSCTL_HANDLER_ARGS)
+{
+ struct nlm_xlpge_softc *sc;
+ uint32_t val;
+ int reg, field;
+
+ sc = arg1;
+ field = arg2;
+ reg = SGMII_STATS_MLR(sc->block, sc->port) + field;
+ val = nlm_read_nae_reg(sc->base_addr, reg);
+ return (sysctl_handle_int(oidp, &val, 0, req));
+}
+
+static void
+nlm_xlpge_setup_stats_sysctl(device_t dev, struct nlm_xlpge_softc *sc)
+{
+ struct sysctl_ctx_list *ctx;
+ struct sysctl_oid_list *child;
+ struct sysctl_oid *tree;
+
+ ctx = device_get_sysctl_ctx(dev);
+ tree = device_get_sysctl_tree(dev);
+ child = SYSCTL_CHILDREN(tree);
+
+#define XLPGE_STAT(name, offset, desc) \
+ SYSCTL_ADD_PROC(ctx, child, OID_AUTO, name, \
+ CTLTYPE_UINT | CTLFLAG_RD, sc, offset, \
+ xlpge_stats_sysctl, "IU", desc)
+
+ XLPGE_STAT("tr127", nlm_sgmii_stats_tr127, "TxRx 64 - 127 Bytes");
+ XLPGE_STAT("tr255", nlm_sgmii_stats_tr255, "TxRx 128 - 255 Bytes");
+ XLPGE_STAT("tr511", nlm_sgmii_stats_tr511, "TxRx 256 - 511 Bytes");
+ XLPGE_STAT("tr1k", nlm_sgmii_stats_tr1k, "TxRx 512 - 1023 Bytes");
+ XLPGE_STAT("trmax", nlm_sgmii_stats_trmax, "TxRx 1024 - 1518 Bytes");
+ XLPGE_STAT("trmgv", nlm_sgmii_stats_trmgv, "TxRx 1519 - 1522 Bytes");
+
+ XLPGE_STAT("rbyt", nlm_sgmii_stats_rbyt, "Rx Bytes");
+ XLPGE_STAT("rpkt", nlm_sgmii_stats_rpkt, "Rx Packets");
+ XLPGE_STAT("rfcs", nlm_sgmii_stats_rfcs, "Rx FCS Error");
+ XLPGE_STAT("rmca", nlm_sgmii_stats_rmca, "Rx Multicast Packets");
+ XLPGE_STAT("rbca", nlm_sgmii_stats_rbca, "Rx Broadcast Packets");
+ XLPGE_STAT("rxcf", nlm_sgmii_stats_rxcf, "Rx Control Frames");
+ XLPGE_STAT("rxpf", nlm_sgmii_stats_rxpf, "Rx Pause Frames");
+ XLPGE_STAT("rxuo", nlm_sgmii_stats_rxuo, "Rx Unknown Opcode");
+ XLPGE_STAT("raln", nlm_sgmii_stats_raln, "Rx Alignment Errors");
+ XLPGE_STAT("rflr", nlm_sgmii_stats_rflr, "Rx Framelength Errors");
+ XLPGE_STAT("rcde", nlm_sgmii_stats_rcde, "Rx Code Errors");
+ XLPGE_STAT("rcse", nlm_sgmii_stats_rcse, "Rx Carrier Sense Errors");
+ XLPGE_STAT("rund", nlm_sgmii_stats_rund, "Rx Undersize Packet Errors");
+ XLPGE_STAT("rovr", nlm_sgmii_stats_rovr, "Rx Oversize Packet Errors");
+ XLPGE_STAT("rfrg", nlm_sgmii_stats_rfrg, "Rx Fragments");
+ XLPGE_STAT("rjbr", nlm_sgmii_stats_rjbr, "Rx Jabber");
+
+ XLPGE_STAT("tbyt", nlm_sgmii_stats_tbyt, "Tx Bytes");
+ XLPGE_STAT("tpkt", nlm_sgmii_stats_tpkt, "Tx Packets");
+ XLPGE_STAT("tmca", nlm_sgmii_stats_tmca, "Tx Multicast Packets");
+ XLPGE_STAT("tbca", nlm_sgmii_stats_tbca, "Tx Broadcast Packets");
+ XLPGE_STAT("txpf", nlm_sgmii_stats_txpf, "Tx Pause Frame");
+ XLPGE_STAT("tdfr", nlm_sgmii_stats_tdfr, "Tx Deferral Packets");
+ XLPGE_STAT("tedf", nlm_sgmii_stats_tedf, "Tx Excessive Deferral Pkts");
+ XLPGE_STAT("tscl", nlm_sgmii_stats_tscl, "Tx Single Collisions");
+ XLPGE_STAT("tmcl", nlm_sgmii_stats_tmcl, "Tx Multiple Collisions");
+ XLPGE_STAT("tlcl", nlm_sgmii_stats_tlcl, "Tx Late Collision Pkts");
+ XLPGE_STAT("txcl", nlm_sgmii_stats_txcl, "Tx Excessive Collisions");
+ XLPGE_STAT("tncl", nlm_sgmii_stats_tncl, "Tx Total Collisions");
+ XLPGE_STAT("tjbr", nlm_sgmii_stats_tjbr, "Tx Jabber Frames");
+ XLPGE_STAT("tfcs", nlm_sgmii_stats_tfcs, "Tx FCS Errors");
+ XLPGE_STAT("txcf", nlm_sgmii_stats_txcf, "Tx Control Frames");
+ XLPGE_STAT("tovr", nlm_sgmii_stats_tovr, "Tx Oversize Frames");
+ XLPGE_STAT("tund", nlm_sgmii_stats_tund, "Tx Undersize Frames");
+ XLPGE_STAT("tfrg", nlm_sgmii_stats_tfrg, "Tx Fragments");
+#undef XLPGE_STAT
+}
+
+static int
+nlm_xlpge_attach(device_t dev)
+{
+ struct xlp_port_ivars *pv;
+ struct nlm_xlpge_softc *sc;
+ int port;
+
+ pv = device_get_ivars(dev);
+ sc = device_get_softc(dev);
+ sc->xlpge_dev = dev;
+ sc->mii_bus = NULL;
+ sc->block = pv->block;
+ sc->node = pv->node;
+ sc->port = pv->port;
+ sc->type = pv->type;
+ sc->xlpge_if = NULL;
+ sc->phy_addr = pv->phy_addr;
+ sc->mdio_bus = pv->mdio_bus;
+ sc->portcfg = nae_port_config;
+ sc->hw_parser_en = pv->hw_parser_en;
+
+ /* default settings */
+ sc->speed = NLM_SGMII_SPEED_10;
+ sc->duplexity = NLM_SGMII_DUPLEX_FULL;
+ sc->link = NLM_LINK_DOWN;
+ sc->flowctrl = NLM_FLOWCTRL_DISABLED;
+
+ sc->network_sc = device_get_softc(device_get_parent(dev));
+ sc->base_addr = sc->network_sc->base;
+ sc->prepad_en = sc->network_sc->prepad_en;
+ sc->prepad_size = sc->network_sc->prepad_size;
+
+ callout_init(&sc->xlpge_callout, 1);
+
+ XLPGE_LOCK_INIT(sc, device_get_nameunit(dev));
+
+ port = (sc->block*4)+sc->port;
+ sc->nfree_desc = nae_port_config[port].num_free_descs;
+ sc->txq = nae_port_config[port].txq;
+ sc->rxfreeq = nae_port_config[port].rxfreeq;
+
+ nlm_xlpge_submit_rx_free_desc(sc, sc->nfree_desc);
+ if (sc->hw_parser_en)
+ nlm_enable_hardware_parser_per_port(sc->base_addr,
+ sc->block, sc->port);
+
+ nlm_xlpge_ifinit(sc);
+ ifp_ports[port].xlpge_sc = sc;
+ nlm_xlpge_mii_init(dev, sc);
+
+ nlm_xlpge_setup_stats_sysctl(dev, sc);
+
+ return (0);
+}
+
+static int
+nlm_xlpge_detach(device_t dev)
+{
+ return (0);
+}
+
+static int
+nlm_xlpge_suspend(device_t dev)
+{
+ return (0);
+}
+
+static int
+nlm_xlpge_resume(device_t dev)
+{
+ return (0);
+}
+
+static int
+nlm_xlpge_shutdown(device_t dev)
+{
+ return (0);
+}
+
+/*
+ * miibus function with custom implementation
+ */
+static int
+nlm_xlpge_mii_read(struct device *dev, int phyaddr, int regidx)
+{
+ struct nlm_xlpge_softc *sc;
+ int val;
+
+ sc = device_get_softc(dev);
+ if (sc->type == SGMIIC)
+ val = nlm_gmac_mdio_read(sc->base_addr, sc->mdio_bus,
+ BLOCK_7, LANE_CFG, phyaddr, regidx);
+ else
+ val = 0xffff;
+
+ return (val);
+}
+
+static int
+nlm_xlpge_mii_write(struct device *dev, int phyaddr, int regidx, int val)
+{
+ struct nlm_xlpge_softc *sc;
+
+ sc = device_get_softc(dev);
+ if (sc->type == SGMIIC)
+ nlm_gmac_mdio_write(sc->base_addr, sc->mdio_bus, BLOCK_7,
+ LANE_CFG, phyaddr, regidx, val);
+
+ return (0);
+}
+
+static void
+nlm_xlpge_mii_statchg(device_t dev)
+{
+ struct nlm_xlpge_softc *sc;
+ struct mii_data *mii;
+ char *speed, *duplexity;
+
+ sc = device_get_softc(dev);
+ if (sc->mii_bus == NULL)
+ return;
+
+ mii = device_get_softc(sc->mii_bus);
+ if (mii->mii_media_status & IFM_ACTIVE) {
+ if (IFM_SUBTYPE(mii->mii_media_active) == IFM_10_T) {
+ sc->speed = NLM_SGMII_SPEED_10;
+ speed = "10Mbps";
+ } else if (IFM_SUBTYPE(mii->mii_media_active) == IFM_100_TX) {
+ sc->speed = NLM_SGMII_SPEED_100;
+ speed = "100Mbps";
+ } else { /* default to 1G */
+ sc->speed = NLM_SGMII_SPEED_1000;
+ speed = "1Gbps";
+ }
+
+ if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) {
+ sc->duplexity = NLM_SGMII_DUPLEX_FULL;
+ duplexity = "full";
+ } else {
+ sc->duplexity = NLM_SGMII_DUPLEX_HALF;
+ duplexity = "half";
+ }
+
+ printf("Port [%d, %d] setup with speed=%s duplex=%s\n",
+ sc->block, sc->port, speed, duplexity);
+
+ nlm_nae_setup_mac(sc->base_addr, sc->block, sc->port, 0, 1, 1,
+ sc->speed, sc->duplexity);
+ }
+}
+
+/*
+ * xlpge support function implementations
+ */
+static void
+nlm_xlpge_release_mbuf(uint64_t paddr)
+{
+ uint64_t mag, desc, mbuf;
+
+ paddr += (XLP_NTXFRAGS - 3) * sizeof(uint64_t);
+ mag = nlm_paddr_ld(paddr);
+ desc = nlm_paddr_ld(paddr + sizeof(uint64_t));
+ mbuf = nlm_paddr_ld(paddr + 2 * sizeof(uint64_t));
+
+ if (mag != 0xf00bad) {
+ /* somebody else packet Error - FIXME in intialization */
+ printf("cpu %d: ERR Tx packet paddr %jx, mag %jx, desc %jx mbuf %jx\n",
+ nlm_cpuid(), (uintmax_t)paddr, (uintmax_t)mag,
+ (intmax_t)desc, (uintmax_t)mbuf);
+ return;
+ }
+ m_freem((struct mbuf *)(uintptr_t)mbuf);
+ uma_zfree(nl_tx_desc_zone, (void *)(uintptr_t)desc);
+}
+
+static void
+nlm_xlpge_rx(struct nlm_xlpge_softc *sc, int port, vm_paddr_t paddr, int len)
+{
+ struct ifnet *ifp;
+ struct mbuf *m;
+ vm_offset_t temp;
+ unsigned long mag;
+ int prepad_size;
+
+ ifp = sc->xlpge_if;
+ temp = nlm_paddr_ld(paddr - NAE_CACHELINE_SIZE);
+ mag = nlm_paddr_ld(paddr - NAE_CACHELINE_SIZE + sizeof(uint64_t));
+
+ m = (struct mbuf *)(intptr_t)temp;
+ if (mag != 0xf00bad) {
+ /* somebody else packet Error - FIXME in intialization */
+ printf("cpu %d: ERR Rx packet paddr %jx, temp %p, mag %lx\n",
+ nlm_cpuid(), (uintmax_t)paddr, (void *)temp, mag);
+ return;
+ }
+
+ m->m_pkthdr.rcvif = ifp;
+
+#ifdef DUMP_PACKET
+ {
+ int i = 0, j = 64;
+ unsigned char *buf = (char *)m->m_data;
+ printf("(cpu_%d: nlge_rx, !RX_COPY) Rx Packet: length=%d\n",
+ nlm_cpuid(), len);
+ if (len < j)
+ j = len;
+ if (sc->prepad_en)
+ j += ((sc->prepad_size + 1) * 16);
+ for (i = 0; i < j; i++) {
+ if (i && (i % 16) == 0)
+ printf("\n");
+ printf("%02x ", buf[i]);
+ }
+ printf("\n");
+ }
+#endif
+
+ if (sc->prepad_en) {
+ prepad_size = ((sc->prepad_size + 1) * 16);
+ m->m_data += prepad_size;
+ m->m_pkthdr.len = m->m_len = (len - prepad_size);
+ } else
+ m->m_pkthdr.len = m->m_len = len;
+
+ /*atomic_incr_long(&ifp->if_ipackets);*/
+ ifp->if_ipackets++;
+#ifdef XLP_DRIVER_LOOPBACK
+ if (port == 16 || port == 17)
+ (*ifp->if_input)(ifp, m);
+ else
+ xlpge_tx(ifp, m);
+#else
+ (*ifp->if_input)(ifp, m);
+#endif
+}
+
+void
+nlm_xlpge_submit_rx_free_desc(struct nlm_xlpge_softc *sc, int num)
+{
+ int i, size, ret, n;
+ struct nlm_fmn_msg msg;
+ void *ptr;
+
+ for(i = 0; i < num; i++) {
+ memset(&msg, 0, sizeof(msg));
+ ptr = get_buf();
+ if (!ptr) {
+ device_printf(sc->xlpge_dev, "Cannot allocate mbuf\n");
+ break;
+ }
+
+ msg.msg[0] = vtophys(ptr);
+ if (msg.msg[0] == 0) {
+ printf("Bad ptr for %p\n", ptr);
+ break;
+ }
+ size = 1;
+
+ n = 0;
+ while (1) {
+ /* on success returns 1, else 0 */
+ ret = nlm_fmn_msgsend(sc->rxfreeq, size, 0, &msg);
+ if (ret == 0)
+ break;
+ if (n++ > 10000) {
+ printf("Too many credit fails for send free desc\n");
+ break;
+ }
+ }
+ }
+}
+
+void
+nlm_xlpge_msgring_handler(int vc, int size, int code, int src_id,
+ struct nlm_fmn_msg *msg, void *data)
+{
+ uint64_t phys_addr;
+ struct nlm_xlpnae_softc *sc;
+ struct nlm_xlpge_softc *xlpge_sc;
+ struct ifnet *ifp;
+ uint32_t context;
+ uint32_t port = 0;
+ uint32_t length;
+
+ sc = (struct nlm_xlpnae_softc *)data;
+ KASSERT(sc != NULL, ("Null sc in msgring handler"));
+
+ if (size == 1) { /* process transmit complete */
+ phys_addr = msg->msg[0] & 0xffffffffffULL;
+
+ /* context is SGMII_RCV_CONTEXT_NUM + three bit vlan type
+ * or vlan priority
+ */
+ context = (msg->msg[0] >> 40) & 0x3fff;
+ port = cntx2port[context];
+
+ if (port >= XLP_MAX_PORTS) {
+ printf("%s:%d Bad port %d (context=%d)\n",
+ __func__, __LINE__, port, context);
+ return;
+ }
+ ifp = ifp_ports[port].xlpge_if;
+ xlpge_sc = ifp_ports[port].xlpge_sc;
+
+ nlm_xlpge_release_mbuf(phys_addr);
+
+ /*atomic_incr_long(&ifp->if_opackets);*/
+ ifp->if_opackets++;
+
+ } else if (size > 1) { /* Recieve packet */
+ phys_addr = msg->msg[1] & 0xffffffffc0ULL;
+ length = (msg->msg[1] >> 40) & 0x3fff;
+ length -= MAC_CRC_LEN;
+
+ /* context is SGMII_RCV_CONTEXT_NUM + three bit vlan type
+ * or vlan priority
+ */
+ context = (msg->msg[1] >> 54) & 0x3ff;
+ port = cntx2port[context];
+
+ if (port >= XLP_MAX_PORTS) {
+ printf("%s:%d Bad port %d (context=%d)\n",
+ __func__, __LINE__, port, context);
+ return;
+ }
+
+ ifp = ifp_ports[port].xlpge_if;
+ xlpge_sc = ifp_ports[port].xlpge_sc;
+
+ nlm_xlpge_rx(xlpge_sc, port, phys_addr, length);
+ /* return back a free descriptor to NA */
+ nlm_xlpge_submit_rx_free_desc(xlpge_sc, 1);
+ }
+}
Property changes on: trunk/sys/mips/nlm/dev/net/xlpge.c
___________________________________________________________________
Added: svn:eol-style
## -0,0 +1 ##
+native
\ No newline at end of property
Added: svn:keywords
## -0,0 +1 ##
+MidnightBSD=%H
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+text/plain
\ No newline at end of property
Added: trunk/sys/mips/nlm/dev/net/xlpge.h
===================================================================
--- trunk/sys/mips/nlm/dev/net/xlpge.h (rev 0)
+++ trunk/sys/mips/nlm/dev/net/xlpge.h 2018-05-26 21:55:02 UTC (rev 9987)
@@ -0,0 +1,139 @@
+/* $MidnightBSD$ */
+/*-
+ * Copyright (c) 2003-2012 Broadcom Corporation
+ * All Rights Reserved
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in
+ * the documentation and/or other materials provided with the
+ * distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY BROADCOM ``AS IS'' AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL BROADCOM OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
+ * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
+ * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
+ * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * $FreeBSD: stable/10/sys/mips/nlm/dev/net/xlpge.h 255368 2013-09-07 18:26:16Z jchandra $
+ */
+
+#ifndef __XLPGE_H__
+#define __XLPGE_H__
+
+#define NLM_XLPGE_TXQ_SIZE 1024
+#define MAC_CRC_LEN 4
+
+enum xlpge_link_state {
+ NLM_LINK_DOWN,
+ NLM_LINK_UP
+};
+
+enum xlpge_floctrl_status {
+ NLM_FLOWCTRL_DISABLED,
+ NLM_FLOWCTRL_ENABLED
+};
+
+struct nlm_xlp_portdata {
+ struct ifnet *xlpge_if;
+ struct nlm_xlpge_softc *xlpge_sc;
+};
+
+struct nlm_xlpnae_softc {
+ device_t xlpnae_dev;
+ int node; /* XLP Node id */
+ uint64_t base; /* NAE IO base */
+ uint64_t poe_base; /* POE IO base */
+ uint64_t poedv_base; /* POE distribution vec IO base */
+
+ int freq; /* frequency of nae block */
+ int flow_crc_poly; /* Flow CRC16 polynomial */
+ int total_free_desc; /* total for node */
+ int max_ports;
+ int total_num_ports;
+ int per_port_num_flows;
+
+ u_int nucores;
+ u_int nblocks;
+ u_int num_complex;
+ u_int ncontexts;
+
+ /* Ingress side parameters */
+ u_int num_desc; /* no of descriptors in each packet */
+ u_int parser_threshold;/* threshold of entries above which */
+ /* the parser sequencer is scheduled */
+ /* NetIOR configs */
+ u_int cmplx_type[8]; /* XXXJC: redundant? */
+ struct nae_port_config *portcfg;
+ u_int blockmask;
+ u_int portmask[XLP_NAE_NBLOCKS];
+ u_int ilmask;
+ u_int xauimask;
+ u_int sgmiimask;
+ u_int hw_parser_en;
+ u_int prepad_en;
+ u_int prepad_size;
+ u_int driver_mode;
+ u_int ieee_1588_en;
+};
+
+struct nlm_xlpge_softc {
+ struct ifnet *xlpge_if; /* should be first member */
+ /* see - mii.c:miibus_attach() */
+ device_t xlpge_dev;
+ device_t mii_bus;
+ struct nlm_xlpnae_softc *network_sc;
+ uint64_t base_addr; /* NAE IO base */
+ int node; /* node id (quickread) */
+ int block; /* network block id (quickread) */
+ int port; /* port id - among the 18 in XLP */
+ int type; /* port type - see xlp_gmac_port_types */
+ int valid; /* boolean: valid port or not */
+ struct mii_data xlpge_mii;
+ int nfree_desc; /* No of free descriptors sent to port */
+ int phy_addr; /* PHY id for the interface */
+
+ int speed; /* Port speed */
+ int duplexity; /* Port duplexity */
+ int link; /* Port link status */
+ int flowctrl; /* Port flow control setting */
+
+ unsigned char dev_addr[ETHER_ADDR_LEN];
+ struct mtx sc_lock;
+ int if_flags;
+ struct nae_port_config *portcfg;
+ struct callout xlpge_callout;
+ int mdio_bus;
+ int txq;
+ int rxfreeq;
+ int hw_parser_en;
+ int prepad_en;
+ int prepad_size;
+};
+
+#define XLP_NTXFRAGS 16
+#define NULL_VFBID 127
+
+struct xlpge_tx_desc {
+ uint64_t frag[XLP_NTXFRAGS];
+};
+
+#define XLPGE_LOCK_INIT(_sc, _name) \
+ mtx_init(&(_sc)->sc_lock, _name, MTX_NETWORK_LOCK, MTX_DEF)
+#define XLPGE_LOCK_DESTROY(_sc) mtx_destroy(&(_sc)->sc_lock)
+#define XLPGE_LOCK(_sc) mtx_lock(&(_sc)->sc_lock)
+#define XLPGE_UNLOCK(_sc) mtx_unlock(&(_sc)->sc_lock)
+#define XLPGE_LOCK_ASSERT(_sc) mtx_assert(&(_sc)->sc_lock, MA_OWNED)
+
+#endif
Property changes on: trunk/sys/mips/nlm/dev/net/xlpge.h
___________________________________________________________________
Added: svn:eol-style
## -0,0 +1 ##
+native
\ No newline at end of property
Added: svn:keywords
## -0,0 +1 ##
+MidnightBSD=%H
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+text/plain
\ No newline at end of property
Added: trunk/sys/mips/nlm/dev/sec/nlmrsa.c
===================================================================
--- trunk/sys/mips/nlm/dev/sec/nlmrsa.c (rev 0)
+++ trunk/sys/mips/nlm/dev/sec/nlmrsa.c 2018-05-26 21:55:02 UTC (rev 9987)
@@ -0,0 +1,556 @@
+/* $MidnightBSD$ */
+/*-
+ * Copyright (c) 2003-2012 Broadcom Corporation
+ * All Rights Reserved
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in
+ * the documentation and/or other materials provided with the
+ * distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY BROADCOM ``AS IS'' AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL BROADCOM OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
+ * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
+ * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
+ * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <sys/cdefs.h>
+__FBSDID("$FreeBSD: stable/10/sys/mips/nlm/dev/sec/nlmrsa.c 256046 2013-10-04 11:11:51Z jchandra $");
+
+#include <sys/cdefs.h>
+#include <sys/param.h>
+#include <sys/systm.h>
+#include <sys/proc.h>
+#include <sys/errno.h>
+#include <sys/endian.h>
+#include <sys/malloc.h>
+#include <sys/kernel.h>
+#include <sys/module.h>
+#include <sys/mbuf.h>
+#include <sys/lock.h>
+#include <sys/mutex.h>
+#include <sys/sysctl.h>
+#include <sys/bus.h>
+#include <sys/random.h>
+#include <sys/rman.h>
+#include <sys/uio.h>
+#include <sys/kobj.h>
+
+#include <dev/pci/pcivar.h>
+
+#include <opencrypto/cryptodev.h>
+
+#include "cryptodev_if.h"
+
+#include <vm/vm.h>
+#include <vm/pmap.h>
+
+#include <mips/nlm/hal/haldefs.h>
+#include <mips/nlm/hal/iomap.h>
+#include <mips/nlm/xlp.h>
+#include <mips/nlm/hal/sys.h>
+#include <mips/nlm/hal/fmn.h>
+#include <mips/nlm/hal/nlmsaelib.h>
+#include <mips/nlm/dev/sec/rsa_ucode.h>
+#include <mips/nlm/hal/cop2.h>
+#include <mips/nlm/hal/mips-extns.h>
+#include <mips/nlm/msgring.h>
+#include <mips/nlm/dev/sec/nlmrsalib.h>
+
+#ifdef NLM_RSA_DEBUG
+static void print_krp_params(struct cryptkop *krp);
+#endif
+
+static int xlp_rsa_init(struct xlp_rsa_softc *sc, int node);
+static int xlp_rsa_newsession(device_t , uint32_t *, struct cryptoini *);
+static int xlp_rsa_freesession(device_t , uint64_t);
+static int xlp_rsa_kprocess(device_t , struct cryptkop *, int);
+static int xlp_get_rsa_opsize(struct xlp_rsa_command *cmd, unsigned int bits);
+static void xlp_free_cmd_params(struct xlp_rsa_command *cmd);
+static int xlp_rsa_inp2hwformat(uint8_t *src, uint8_t *dst,
+ uint32_t paramsize, uint8_t result);
+
+static int xlp_rsa_probe(device_t);
+static int xlp_rsa_attach(device_t);
+static int xlp_rsa_detach(device_t);
+
+static device_method_t xlp_rsa_methods[] = {
+ /* device interface */
+ DEVMETHOD(device_probe, xlp_rsa_probe),
+ DEVMETHOD(device_attach, xlp_rsa_attach),
+ DEVMETHOD(device_detach, xlp_rsa_detach),
+
+ /* bus interface */
+ DEVMETHOD(bus_print_child, bus_generic_print_child),
+ DEVMETHOD(bus_driver_added, bus_generic_driver_added),
+
+ /* crypto device methods */
+ DEVMETHOD(cryptodev_newsession, xlp_rsa_newsession),
+ DEVMETHOD(cryptodev_freesession, xlp_rsa_freesession),
+ DEVMETHOD(cryptodev_kprocess, xlp_rsa_kprocess),
+
+ DEVMETHOD_END
+};
+
+static driver_t xlp_rsa_driver = {
+ "nlmrsa",
+ xlp_rsa_methods,
+ sizeof(struct xlp_rsa_softc)
+};
+static devclass_t xlp_rsa_devclass;
+
+DRIVER_MODULE(nlmrsa, pci, xlp_rsa_driver, xlp_rsa_devclass, 0, 0);
+MODULE_DEPEND(nlmrsa, crypto, 1, 1, 1);
+
+#ifdef NLM_RSA_DEBUG
+static void
+print_krp_params(struct cryptkop *krp)
+{
+ int i;
+
+ printf("krp->krp_op :%d\n", krp->krp_op);
+ printf("krp->krp_status :%d\n", krp->krp_status);
+ printf("krp->krp_iparams:%d\n", krp->krp_iparams);
+ printf("krp->krp_oparams:%d\n", krp->krp_oparams);
+ for (i = 0; i < krp->krp_iparams + krp->krp_oparams; i++) {
+ printf("krp->krp_param[%d].crp_p :0x%llx\n", i,
+ (unsigned long long)krp->krp_param[i].crp_p);
+ printf("krp->krp_param[%d].crp_nbits :%d\n", i,
+ krp->krp_param[i].crp_nbits);
+ printf("krp->krp_param[%d].crp_nbytes :%d\n", i,
+ howmany(krp->krp_param[i].crp_nbits, 8));
+ }
+}
+#endif
+
+static int
+xlp_rsa_init(struct xlp_rsa_softc *sc, int node)
+{
+ struct xlp_rsa_command *cmd = NULL;
+ uint32_t fbvc, dstvc, endsel, regval;
+ struct nlm_fmn_msg m;
+ int err, ret, i;
+ uint64_t base;
+
+ /* Register interrupt handler for the RSA/ECC CMS messages */
+ if (register_msgring_handler(sc->rsaecc_vc_start,
+ sc->rsaecc_vc_end, nlm_xlprsaecc_msgring_handler, sc) != 0) {
+ err = -1;
+ printf("Couldn't register rsa/ecc msgring handler\n");
+ goto errout;
+ }
+ fbvc = nlm_cpuid() * 4 + XLPGE_FB_VC;
+ /* Do the CMS credit initialization */
+ /* Currently it is configured by default to 50 when kernel comes up */
+
+#if BYTE_ORDER == LITTLE_ENDIAN
+ for (i = 0; i < nitems(nlm_rsa_ucode_data); i++)
+ nlm_rsa_ucode_data[i] = htobe64(nlm_rsa_ucode_data[i]);
+#endif
+ for (dstvc = sc->rsaecc_vc_start; dstvc <= sc->rsaecc_vc_end; dstvc++) {
+ cmd = malloc(sizeof(struct xlp_rsa_command), M_DEVBUF,
+ M_NOWAIT | M_ZERO);
+ KASSERT(cmd != NULL, ("%s:cmd is NULL\n", __func__));
+ cmd->rsasrc = contigmalloc(sizeof(nlm_rsa_ucode_data),
+ M_DEVBUF,
+ (M_WAITOK | M_ZERO),
+ 0UL /* low address */, -1UL /* high address */,
+ XLP_L2L3_CACHELINE_SIZE /* alignment */,
+ 0UL /* boundary */);
+ KASSERT(cmd->rsasrc != NULL,
+ ("%s:cmd->rsasrc is NULL\n", __func__));
+ memcpy(cmd->rsasrc, nlm_rsa_ucode_data,
+ sizeof(nlm_rsa_ucode_data));
+ m.msg[0] = nlm_crypto_form_rsa_ecc_fmn_entry0(1, 0x70, 0,
+ vtophys(cmd->rsasrc));
+ m.msg[1] = nlm_crypto_form_rsa_ecc_fmn_entry1(0, 1, fbvc,
+ vtophys(cmd->rsasrc));
+ /* Software scratch pad */
+ m.msg[2] = (uintptr_t)cmd;
+ m.msg[3] = 0;
+
+ ret = nlm_fmn_msgsend(dstvc, 3, FMN_SWCODE_RSA, &m);
+ if (ret != 0) {
+ err = -1;
+ printf("%s: msgsnd failed (%x)\n", __func__, ret);
+ goto errout;
+ }
+ }
+ /* Configure so that all VCs send request to all RSA pipes */
+ base = nlm_get_rsa_regbase(node);
+ if (nlm_is_xlp3xx()) {
+ endsel = 1;
+ regval = 0xFFFF;
+ } else {
+ endsel = 3;
+ regval = 0x07FFFFFF;
+ }
+ for (i = 0; i < endsel; i++)
+ nlm_write_rsa_reg(base, RSA_ENG_SEL_0 + i, regval);
+ return (0);
+errout:
+ xlp_free_cmd_params(cmd);
+ return (err);
+}
+
+/* This function is called from an interrupt handler */
+void
+nlm_xlprsaecc_msgring_handler(int vc, int size, int code, int src_id,
+ struct nlm_fmn_msg *msg, void *data)
+{
+ struct xlp_rsa_command *cmd;
+ struct xlp_rsa_softc *sc;
+ struct crparam *outparam;
+ int ostart;
+
+ KASSERT(code == FMN_SWCODE_RSA,
+ ("%s: bad code = %d, expected code = %d\n", __func__, code,
+ FMN_SWCODE_RSA));
+
+ sc = data;
+ KASSERT(src_id >= sc->rsaecc_vc_start && src_id <= sc->rsaecc_vc_end,
+ ("%s: bad src_id = %d, expect %d - %d\n", __func__,
+ src_id, sc->rsaecc_vc_start, sc->rsaecc_vc_end));
+
+ cmd = (struct xlp_rsa_command *)(uintptr_t)msg->msg[1];
+ KASSERT(cmd != NULL, ("%s:cmd not received properly\n", __func__));
+
+ if (RSA_ERROR(msg->msg[0]) != 0) {
+ printf("%s: Message rcv msg0 %llx msg1 %llx err %x \n",
+ __func__, (unsigned long long)msg->msg[0],
+ (unsigned long long)msg->msg[1],
+ (int)RSA_ERROR(msg->msg[0]));
+ cmd->krp->krp_status = EBADMSG;
+ }
+
+ if (cmd->krp != NULL) {
+ ostart = cmd->krp->krp_iparams;
+ outparam = &cmd->krp->krp_param[ostart];
+ xlp_rsa_inp2hwformat(cmd->rsasrc + cmd->rsaopsize * ostart,
+ outparam->crp_p,
+ howmany(outparam->crp_nbits, 8),
+ 1);
+ crypto_kdone(cmd->krp);
+ }
+
+ xlp_free_cmd_params(cmd);
+}
+
+static int
+xlp_rsa_probe(device_t dev)
+{
+ struct xlp_rsa_softc *sc;
+
+ if (pci_get_vendor(dev) == PCI_VENDOR_NETLOGIC &&
+ pci_get_device(dev) == PCI_DEVICE_ID_NLM_RSA) {
+ sc = device_get_softc(dev);
+ return (BUS_PROBE_DEFAULT);
+ }
+ return (ENXIO);
+}
+
+/*
+ * Attach an interface that successfully probed.
+ */
+static int
+xlp_rsa_attach(device_t dev)
+{
+ struct xlp_rsa_softc *sc = device_get_softc(dev);
+ uint64_t base;
+ int qstart, qnum;
+ int freq, node;
+
+ sc->sc_dev = dev;
+
+ node = nlm_get_device_node(pci_get_slot(dev));
+ freq = nlm_set_device_frequency(node, DFS_DEVICE_RSA, 250);
+ if (bootverbose)
+ device_printf(dev, "RSA Freq: %dMHz\n", freq);
+ if (pci_get_device(dev) == PCI_DEVICE_ID_NLM_RSA) {
+ device_set_desc(dev, "XLP RSA/ECC Accelerator");
+ if ((sc->sc_cid = crypto_get_driverid(dev,
+ CRYPTOCAP_F_HARDWARE)) < 0) {
+ printf("xlp_rsaecc-err:couldn't get the driver id\n");
+ goto error_exit;
+ }
+ if (crypto_kregister(sc->sc_cid, CRK_MOD_EXP, 0) != 0)
+ goto error_exit;
+
+ base = nlm_get_rsa_pcibase(node);
+ qstart = nlm_qidstart(base);
+ qnum = nlm_qnum(base);
+ sc->rsaecc_vc_start = qstart;
+ sc->rsaecc_vc_end = qstart + qnum - 1;
+ }
+ if (xlp_rsa_init(sc, node) != 0)
+ goto error_exit;
+ device_printf(dev, "RSA Initialization complete!\n");
+ return (0);
+
+error_exit:
+ return (ENXIO);
+}
+
+/*
+ * Detach an interface that successfully probed.
+ */
+static int
+xlp_rsa_detach(device_t dev)
+{
+ return (0);
+}
+
+/*
+ * Allocate a new 'session' and return an encoded session id. 'sidp'
+ * contains our registration id, and should contain an encoded session
+ * id on successful allocation.
+ */
+static int
+xlp_rsa_newsession(device_t dev, u_int32_t *sidp, struct cryptoini *cri)
+{
+ struct xlp_rsa_softc *sc = device_get_softc(dev);
+ struct xlp_rsa_session *ses = NULL;
+ int sesn;
+
+ if (sidp == NULL || cri == NULL || sc == NULL)
+ return (EINVAL);
+
+ if (sc->sc_sessions == NULL) {
+ ses = sc->sc_sessions = malloc(sizeof(struct xlp_rsa_session),
+ M_DEVBUF, M_NOWAIT);
+ if (ses == NULL)
+ return (ENOMEM);
+ sesn = 0;
+ sc->sc_nsessions = 1;
+ } else {
+ for (sesn = 0; sesn < sc->sc_nsessions; sesn++) {
+ if (!sc->sc_sessions[sesn].hs_used) {
+ ses = &sc->sc_sessions[sesn];
+ break;
+ }
+ }
+
+ if (ses == NULL) {
+ sesn = sc->sc_nsessions;
+ ses = malloc((sesn + 1) * sizeof(*ses),
+ M_DEVBUF, M_NOWAIT);
+ if (ses == NULL)
+ return (ENOMEM);
+ bcopy(sc->sc_sessions, ses, sesn * sizeof(*ses));
+ bzero(sc->sc_sessions, sesn * sizeof(*ses));
+ free(sc->sc_sessions, M_DEVBUF);
+ sc->sc_sessions = ses;
+ ses = &sc->sc_sessions[sesn];
+ sc->sc_nsessions++;
+ }
+ }
+ bzero(ses, sizeof(*ses));
+ ses->sessionid = sesn;
+ ses->hs_used = 1;
+
+ *sidp = XLP_RSA_SID(device_get_unit(sc->sc_dev), sesn);
+ return (0);
+}
+
+/*
+ * Deallocate a session.
+ * XXX this routine should run a zero'd mac/encrypt key into context ram.
+ * XXX to blow away any keys already stored there.
+ */
+static int
+xlp_rsa_freesession(device_t dev, u_int64_t tid)
+{
+ struct xlp_rsa_softc *sc = device_get_softc(dev);
+ int session;
+ u_int32_t sid = CRYPTO_SESID2LID(tid);
+
+ if (sc == NULL)
+ return (EINVAL);
+
+ session = XLP_RSA_SESSION(sid);
+ if (session >= sc->sc_nsessions)
+ return (EINVAL);
+
+ sc->sc_sessions[session].hs_used = 0;
+ return (0);
+}
+
+static void
+xlp_free_cmd_params(struct xlp_rsa_command *cmd)
+{
+
+ if (cmd == NULL)
+ return;
+ if (cmd->rsasrc != NULL) {
+ if (cmd->krp == NULL) /* Micro code load */
+ contigfree(cmd->rsasrc, sizeof(nlm_rsa_ucode_data),
+ M_DEVBUF);
+ else
+ free(cmd->rsasrc, M_DEVBUF);
+ }
+ free(cmd, M_DEVBUF);
+}
+
+static int
+xlp_get_rsa_opsize(struct xlp_rsa_command *cmd, unsigned int bits)
+{
+
+ if (bits == 0 || bits > 8192)
+ return (-1);
+ /* XLP hardware expects always a fixed size with unused bytes
+ * zeroed out in the input data */
+ if (bits <= 512) {
+ cmd->rsatype = 0x40;
+ cmd->rsaopsize = 64;
+ } else if (bits <= 1024) {
+ cmd->rsatype = 0x41;
+ cmd->rsaopsize = 128;
+ } else if (bits <= 2048) {
+ cmd->rsatype = 0x42;
+ cmd->rsaopsize = 256;
+ } else if (bits <= 4096) {
+ cmd->rsatype = 0x43;
+ cmd->rsaopsize = 512;
+ } else if (bits <= 8192) {
+ cmd->rsatype = 0x44;
+ cmd->rsaopsize = 1024;
+ }
+ return (0);
+}
+
+static int
+xlp_rsa_inp2hwformat(uint8_t *src, uint8_t *dst, uint32_t paramsize,
+ uint8_t result)
+{
+ uint32_t pdwords, pbytes;
+ int i, j, k;
+
+ pdwords = paramsize / 8;
+ pbytes = paramsize % 8;
+
+ for (i = 0, k = 0; i < pdwords; i++) {
+ /* copy dwords of inp/hw to hw/out format */
+ for (j = 7; j >= 0; j--, k++)
+ dst[i * 8 + j] = src[k];
+ }
+ if (pbytes) {
+ if (result == 0) {
+ /* copy rem bytes of input data to hw format */
+ for (j = 7; k < paramsize; j--, k++)
+ dst[i * 8 + j] = src[k];
+ } else {
+ /* copy rem bytes of hw data to exp output format */
+ for (j = 7; k < paramsize; j--, k++)
+ dst[k] = src[i * 8 + j];
+ }
+ }
+
+ return (0);
+}
+
+static int
+nlm_crypto_complete_rsa_request(struct xlp_rsa_softc *sc,
+ struct xlp_rsa_command *cmd)
+{
+ unsigned int fbvc;
+ struct nlm_fmn_msg m;
+ int ret;
+
+ fbvc = nlm_cpuid() * 4 + XLPGE_FB_VC;
+
+ m.msg[0] = nlm_crypto_form_rsa_ecc_fmn_entry0(1, cmd->rsatype,
+ cmd->rsafn, vtophys(cmd->rsasrc));
+ m.msg[1] = nlm_crypto_form_rsa_ecc_fmn_entry1(0, 1, fbvc,
+ vtophys(cmd->rsasrc + cmd->rsaopsize * cmd->krp->krp_iparams));
+ /* Software scratch pad */
+ m.msg[2] = (uintptr_t)cmd;
+ m.msg[3] = 0;
+
+ /* Send the message to rsa engine vc */
+ ret = nlm_fmn_msgsend(sc->rsaecc_vc_start, 3, FMN_SWCODE_RSA, &m);
+ if (ret != 0) {
+#ifdef NLM_SEC_DEBUG
+ printf("%s: msgsnd failed (%x)\n", __func__, ret);
+#endif
+ return (ERESTART);
+ }
+ return (0);
+}
+
+static int
+xlp_rsa_kprocess(device_t dev, struct cryptkop *krp, int hint)
+{
+ struct xlp_rsa_softc *sc = device_get_softc(dev);
+ struct xlp_rsa_command *cmd;
+ struct crparam *kp;
+ int err, i;
+
+ if (krp == NULL || krp->krp_callback == NULL)
+ return (EINVAL);
+
+ cmd = malloc(sizeof(struct xlp_rsa_command), M_DEVBUF,
+ M_NOWAIT | M_ZERO);
+ KASSERT(cmd != NULL, ("%s:cmd is NULL\n", __func__));
+ cmd->krp = krp;
+
+#ifdef NLM_RSA_DEBUG
+ print_krp_params(krp);
+#endif
+ err = EOPNOTSUPP;
+ switch (krp->krp_op) {
+ case CRK_MOD_EXP:
+ if (krp->krp_iparams == 3 && krp->krp_oparams == 1)
+ break;
+ goto errout;
+ default:
+ device_printf(dev, "Op:%d not yet supported\n", krp->krp_op);
+ goto errout;
+ }
+
+ err = xlp_get_rsa_opsize(cmd,
+ krp->krp_param[krp->krp_iparams - 1].crp_nbits);
+ if (err != 0) {
+ err = EINVAL;
+ goto errout;
+ }
+ cmd->rsafn = 0; /* Mod Exp */
+ cmd->rsasrc = malloc(
+ cmd->rsaopsize * (krp->krp_iparams + krp->krp_oparams),
+ M_DEVBUF,
+ M_NOWAIT | M_ZERO);
+ if (cmd->rsasrc == NULL) {
+ err = ENOMEM;
+ goto errout;
+ }
+
+ for (i = 0, kp = krp->krp_param; i < krp->krp_iparams; i++, kp++) {
+ KASSERT(kp->crp_nbits != 0,
+ ("%s: parameter[%d]'s length is zero\n", __func__, i));
+ xlp_rsa_inp2hwformat(kp->crp_p,
+ cmd->rsasrc + i * cmd->rsaopsize,
+ howmany(kp->crp_nbits, 8), 0);
+ }
+ err = nlm_crypto_complete_rsa_request(sc, cmd);
+ if (err != 0)
+ goto errout;
+
+ return (0);
+errout:
+ xlp_free_cmd_params(cmd);
+ krp->krp_status = err;
+ crypto_kdone(krp);
+ return (err);
+}
Property changes on: trunk/sys/mips/nlm/dev/sec/nlmrsa.c
___________________________________________________________________
Added: svn:eol-style
## -0,0 +1 ##
+native
\ No newline at end of property
Added: svn:keywords
## -0,0 +1 ##
+MidnightBSD=%H
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+text/plain
\ No newline at end of property
Added: trunk/sys/mips/nlm/dev/sec/nlmrsalib.h
===================================================================
--- trunk/sys/mips/nlm/dev/sec/nlmrsalib.h (rev 0)
+++ trunk/sys/mips/nlm/dev/sec/nlmrsalib.h 2018-05-26 21:55:02 UTC (rev 9987)
@@ -0,0 +1,71 @@
+/* $MidnightBSD$ */
+/*-
+ * Copyright (c) 2003-2012 Broadcom Corporation
+ * All Rights Reserved
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in
+ * the documentation and/or other materials provided with the
+ * distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY BROADCOM ``AS IS'' AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL BROADCOM OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
+ * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
+ * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
+ * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * $FreeBSD: stable/10/sys/mips/nlm/dev/sec/nlmrsalib.h 256045 2013-10-04 10:01:20Z jchandra $
+ */
+#ifndef _NLMRSALIB_H_
+#define _NLMRSALIB_H_
+
+#define XLP_RSA_SESSION(sid) ((sid) & 0x000007ff)
+#define XLP_RSA_SID(crd,ses) (((crd) << 28) | ((ses) & 0x7ff))
+
+#define RSA_ERROR(msg0) (((msg0) >> 53) & 0x1f)
+
+struct xlp_rsa_session {
+ uint32_t sessionid;
+ int hs_used;
+};
+
+struct xlp_rsa_command {
+ uint16_t session_num;
+ struct xlp_rsa_session *ses;
+ struct cryptkop *krp;
+ uint8_t *rsasrc;
+ uint32_t rsaopsize;
+ uint32_t rsatype;
+ uint32_t rsafn;
+};
+
+/*
+ * Holds data specific to nlm security accelerators
+ */
+struct xlp_rsa_softc {
+ device_t sc_dev; /* device backpointer */
+ uint64_t rsa_base;
+ int sc_cid;
+ struct xlp_rsa_session *sc_sessions;
+ int sc_nsessions;
+ int rsaecc_vc_start;
+ int rsaecc_vc_end;
+};
+
+void
+nlm_xlprsaecc_msgring_handler(int vc, int size, int code, int src_id,
+ struct nlm_fmn_msg *msg, void *data);
+
+#endif /* _NLMRSALIB_H_ */
Property changes on: trunk/sys/mips/nlm/dev/sec/nlmrsalib.h
___________________________________________________________________
Added: svn:eol-style
## -0,0 +1 ##
+native
\ No newline at end of property
Added: svn:keywords
## -0,0 +1 ##
+MidnightBSD=%H
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+text/plain
\ No newline at end of property
Added: trunk/sys/mips/nlm/dev/sec/nlmsec.c
===================================================================
--- trunk/sys/mips/nlm/dev/sec/nlmsec.c (rev 0)
+++ trunk/sys/mips/nlm/dev/sec/nlmsec.c 2018-05-26 21:55:02 UTC (rev 9987)
@@ -0,0 +1,851 @@
+/* $MidnightBSD$ */
+/*-
+ * Copyright (c) 2003-2012 Broadcom Corporation
+ * All Rights Reserved
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in
+ * the documentation and/or other materials provided with the
+ * distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY BROADCOM ``AS IS'' AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL BROADCOM OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
+ * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
+ * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
+ * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <sys/cdefs.h>
+__FBSDID("$FreeBSD: stable/10/sys/mips/nlm/dev/sec/nlmsec.c 233541 2012-03-27 11:43:46Z jchandra $");
+
+#include <sys/cdefs.h>
+#include <sys/param.h>
+#include <sys/systm.h>
+#include <sys/proc.h>
+#include <sys/errno.h>
+#include <sys/malloc.h>
+#include <sys/kernel.h>
+#include <sys/module.h>
+#include <sys/mbuf.h>
+#include <sys/lock.h>
+#include <sys/mutex.h>
+#include <sys/sysctl.h>
+#include <sys/bus.h>
+#include <sys/random.h>
+#include <sys/rman.h>
+#include <sys/uio.h>
+#include <sys/kobj.h>
+
+#include <dev/pci/pcivar.h>
+
+#include <opencrypto/cryptodev.h>
+
+#include "cryptodev_if.h"
+
+#include <vm/vm.h>
+#include <vm/pmap.h>
+
+#include <mips/nlm/hal/haldefs.h>
+#include <mips/nlm/hal/iomap.h>
+#include <mips/nlm/xlp.h>
+#include <mips/nlm/hal/sys.h>
+#include <mips/nlm/hal/fmn.h>
+#include <mips/nlm/hal/nlmsaelib.h>
+#include <mips/nlm/dev/sec/nlmseclib.h>
+#include <mips/nlm/hal/cop2.h>
+#include <mips/nlm/hal/mips-extns.h>
+#include <mips/nlm/msgring.h>
+
+unsigned int creditleft;
+
+void xlp_sec_print_data(struct cryptop *crp);
+
+static int xlp_sec_init(struct xlp_sec_softc *sc);
+static int xlp_sec_newsession(device_t , uint32_t *, struct cryptoini *);
+static int xlp_sec_freesession(device_t , uint64_t);
+static int xlp_sec_process(device_t , struct cryptop *, int);
+static int xlp_copyiv(struct xlp_sec_softc *, struct xlp_sec_command *,
+ struct cryptodesc *enccrd);
+static int xlp_get_nsegs(struct cryptop *, unsigned int *);
+static int xlp_alloc_cmd_params(struct xlp_sec_command *, unsigned int);
+static void xlp_free_cmd_params(struct xlp_sec_command *);
+
+static int xlp_sec_probe(device_t);
+static int xlp_sec_attach(device_t);
+static int xlp_sec_detach(device_t);
+
+static device_method_t xlp_sec_methods[] = {
+ /* device interface */
+ DEVMETHOD(device_probe, xlp_sec_probe),
+ DEVMETHOD(device_attach, xlp_sec_attach),
+ DEVMETHOD(device_detach, xlp_sec_detach),
+
+ /* bus interface */
+ DEVMETHOD(bus_print_child, bus_generic_print_child),
+ DEVMETHOD(bus_driver_added, bus_generic_driver_added),
+
+ /* crypto device methods */
+ DEVMETHOD(cryptodev_newsession, xlp_sec_newsession),
+ DEVMETHOD(cryptodev_freesession,xlp_sec_freesession),
+ DEVMETHOD(cryptodev_process, xlp_sec_process),
+
+ DEVMETHOD_END
+};
+
+static driver_t xlp_sec_driver = {
+ "nlmsec",
+ xlp_sec_methods,
+ sizeof(struct xlp_sec_softc)
+};
+static devclass_t xlp_sec_devclass;
+
+DRIVER_MODULE(nlmsec, pci, xlp_sec_driver, xlp_sec_devclass, 0, 0);
+MODULE_DEPEND(nlmsec, crypto, 1, 1, 1);
+
+void
+nlm_xlpsec_msgring_handler(int vc, int size, int code, int src_id,
+ struct nlm_fmn_msg *msg, void *data);
+
+#ifdef NLM_SEC_DEBUG
+
+#define extract_bits(x, bitshift, bitcnt) \
+ (((unsigned long long)x >> bitshift) & ((1ULL << bitcnt) - 1))
+
+void
+print_crypto_params(struct xlp_sec_command *cmd, struct nlm_fmn_msg m)
+{
+ unsigned long long msg0,msg1,msg2,msg3,msg4,msg5,msg6,msg7,msg8;
+
+ msg0 = cmd->ctrlp->desc0;
+ msg1 = cmd->paramp->desc0;
+ msg2 = cmd->paramp->desc1;
+ msg3 = cmd->paramp->desc2;
+ msg4 = cmd->paramp->desc3;
+ msg5 = cmd->paramp->segment[0][0];
+ msg6 = cmd->paramp->segment[0][1];
+ msg7 = m.msg[0];
+ msg8 = m.msg[1];
+
+ printf("msg0 %llx msg1 %llx msg2 %llx msg3 %llx msg4 %llx msg5 %llx"
+ "msg6 %llx msg7 %llx msg8 %llx\n", msg0, msg1, msg2, msg3, msg4,
+ msg5, msg6, msg7, msg8);
+
+ printf("c0: hmac %d htype %d hmode %d ctype %d cmode %d arc4 %x\n",
+ (unsigned int)extract_bits(msg0, 61, 1),
+ (unsigned int)extract_bits(msg0, 52, 8),
+ (unsigned int)extract_bits(msg0, 43, 8),
+ (unsigned int)extract_bits(msg0, 34, 8),
+ (unsigned int)extract_bits(msg0, 25, 8),
+ (unsigned int)extract_bits(msg0, 0, 23));
+
+ printf("p0: tls %d hsrc %d hl3 %d enc %d ivl %d hd %llx\n",
+ (unsigned int)extract_bits(msg1, 63, 1),
+ (unsigned int)extract_bits(msg1,62,1),
+ (unsigned int)extract_bits(msg1,60,1),
+ (unsigned int)extract_bits(msg1,59,1),
+ (unsigned int)extract_bits(msg1,41,16), extract_bits(msg1,0,40));
+
+ printf("p1: clen %u hl %u\n", (unsigned int)extract_bits(msg2, 32, 32),
+ (unsigned int)extract_bits(msg2,0,32));
+
+ printf("p2: ivoff %d cbit %d coff %d hbit %d hclb %d hoff %d\n",
+ (unsigned int)extract_bits(msg3, 45, 17),
+ (unsigned int)extract_bits(msg3, 42,3),
+ (unsigned int)extract_bits(msg3, 22,16),
+ (unsigned int)extract_bits(msg3, 19,3),
+ (unsigned int)extract_bits(msg3, 18,1),
+ (unsigned int)extract_bits(msg3, 0, 16));
+
+ printf("p3: desfbid %d tlen %d arc4 %x hmacpad %d\n",
+ (unsigned int)extract_bits(msg4, 48,16),
+ (unsigned int)extract_bits(msg4,11,16),
+ (unsigned int)extract_bits(msg4,6,3),
+ (unsigned int)extract_bits(msg4,5,1));
+
+ printf("p4: sflen %d sddr %llx \n",
+ (unsigned int)extract_bits(msg5, 48, 16),extract_bits(msg5, 0, 40));
+
+ printf("p5: dflen %d cl3 %d cclob %d cdest %llx \n",
+ (unsigned int)extract_bits(msg6, 48, 16),
+ (unsigned int)extract_bits(msg6, 46, 1),
+ (unsigned int)extract_bits(msg6, 41, 1), extract_bits(msg6, 0, 40));
+
+ printf("fmn0: fbid %d dfrlen %d dfrv %d cklen %d cdescaddr %llx\n",
+ (unsigned int)extract_bits(msg7, 48, 16),
+ (unsigned int)extract_bits(msg7,46,2),
+ (unsigned int)extract_bits(msg7,45,1),
+ (unsigned int)extract_bits(msg7,40,5),
+ (extract_bits(msg7,0,34)<< 6));
+
+ printf("fmn1: arc4 %d hklen %d pdesclen %d pktdescad %llx\n",
+ (unsigned int)extract_bits(msg8, 63, 1),
+ (unsigned int)extract_bits(msg8,56,5),
+ (unsigned int)extract_bits(msg8,43,12),
+ (extract_bits(msg8,0,34) << 6));
+
+ return;
+}
+
+void
+xlp_sec_print_data(struct cryptop *crp)
+{
+ int i, key_len;
+ struct cryptodesc *crp_desc;
+
+ printf("session id = 0x%llx, crp_ilen = %d, crp_olen=%d \n",
+ crp->crp_sid, crp->crp_ilen, crp->crp_olen);
+
+ printf("crp_flags = 0x%x\n", crp->crp_flags);
+
+ printf("crp buf:\n");
+ for (i = 0; i < crp->crp_ilen; i++) {
+ printf("%c ", crp->crp_buf[i]);
+ if (i % 10 == 0)
+ printf("\n");
+ }
+
+ printf("\n");
+ printf("****************** desc ****************\n");
+ crp_desc = crp->crp_desc;
+ printf("crd_skip=%d, crd_len=%d, crd_flags=0x%x, crd_alg=%d\n",
+ crp_desc->crd_skip, crp_desc->crd_len, crp_desc->crd_flags,
+ crp_desc->crd_alg);
+
+ key_len = crp_desc->crd_klen / 8;
+ printf("key(%d) :\n", key_len);
+ for (i = 0; i < key_len; i++)
+ printf("%d", crp_desc->crd_key[i]);
+ printf("\n");
+
+ printf(" IV : \n");
+ for (i = 0; i < EALG_MAX_BLOCK_LEN; i++)
+ printf("%d", crp_desc->crd_iv[i]);
+ printf("\n");
+
+ printf("crd_next=%p\n", crp_desc->crd_next);
+ return;
+}
+
+void
+print_cmd(struct xlp_sec_command *cmd)
+{
+ printf("session_num :%d\n",cmd->session_num);
+ printf("crp :0x%x\n",(uint32_t)cmd->crp);
+ printf("enccrd :0x%x\n",(uint32_t)cmd->enccrd);
+ printf("maccrd :0x%x\n",(uint32_t)cmd->maccrd);
+ printf("ses :%d\n",(uint32_t)cmd->ses);
+ printf("ctrlp :0x%x\n",(uint32_t)cmd->ctrlp);
+ printf("paramp :0x%x\n",(uint32_t)cmd->paramp);
+ printf("hashdest :0x%x\n",(uint32_t)cmd->hashdest);
+ printf("hashsrc :%d\n",cmd->hashsrc);
+ printf("hmacpad :%d\n",cmd->hmacpad);
+ printf("hashoff :%d\n",cmd->hashoff);
+ printf("hashlen :%d\n",cmd->hashlen);
+ printf("cipheroff :%d\n",cmd->cipheroff);
+ printf("cipherlen :%d\n",cmd->cipherlen);
+ printf("ivoff :%d\n",cmd->ivoff);
+ printf("ivlen :%d\n",cmd->ivlen);
+ printf("hashalg :%d\n",cmd->hashalg);
+ printf("hashmode :%d\n",cmd->hashmode);
+ printf("cipheralg :%d\n",cmd->cipheralg);
+ printf("ciphermode :%d\n",cmd->ciphermode);
+ printf("nsegs :%d\n",cmd->nsegs);
+ printf("hash_dst_len :%d\n",cmd->hash_dst_len);
+}
+#endif /* NLM_SEC_DEBUG */
+
+static int
+xlp_sec_init(struct xlp_sec_softc *sc)
+{
+
+ /* Register interrupt handler for the SEC CMS messages */
+ if (register_msgring_handler(sc->sec_vc_start,
+ sc->sec_vc_end, nlm_xlpsec_msgring_handler, sc) != 0) {
+ printf("Couldn't register sec msgring handler\n");
+ return (-1);
+ }
+
+ /* Do the CMS credit initialization */
+ /* Currently it is configured by default to 50 when kernel comes up */
+
+ return (0);
+}
+
+/* This function is called from an interrupt handler */
+void
+nlm_xlpsec_msgring_handler(int vc, int size, int code, int src_id,
+ struct nlm_fmn_msg *msg, void *data)
+{
+ struct xlp_sec_command *cmd = NULL;
+ struct xlp_sec_softc *sc = NULL;
+ struct cryptodesc *crd = NULL;
+ unsigned int ivlen = 0;
+
+ KASSERT(code == FMN_SWCODE_CRYPTO,
+ ("%s: bad code = %d, expected code = %d\n", __FUNCTION__,
+ code, FMN_SWCODE_CRYPTO));
+
+ sc = (struct xlp_sec_softc *)data;
+ KASSERT(src_id >= sc->sec_vc_start && src_id <= sc->sec_vc_end,
+ ("%s: bad src_id = %d, expect %d - %d\n", __FUNCTION__,
+ src_id, sc->sec_vc_start, sc->sec_vc_end));
+
+ cmd = (struct xlp_sec_command *)(uintptr_t)msg->msg[0];
+ KASSERT(cmd != NULL && cmd->crp != NULL,
+ ("%s :cmd not received properly\n",__FUNCTION__));
+
+ KASSERT(CRYPTO_ERROR(msg->msg[1]) == 0,
+ ("%s: Message rcv msg0 %llx msg1 %llx err %x \n", __FUNCTION__,
+ (unsigned long long)msg->msg[0], (unsigned long long)msg->msg[1],
+ (int)CRYPTO_ERROR(msg->msg[1])));
+
+ crd = cmd->enccrd;
+ /* Copy the last 8 or 16 bytes to the session iv, so that in few
+ * cases this will be used as IV for the next request
+ */
+ if (crd != NULL) {
+ if ((crd->crd_alg == CRYPTO_DES_CBC ||
+ crd->crd_alg == CRYPTO_3DES_CBC ||
+ crd->crd_alg == CRYPTO_AES_CBC) &&
+ (crd->crd_flags & CRD_F_ENCRYPT)) {
+ ivlen = ((crd->crd_alg == CRYPTO_AES_CBC) ?
+ XLP_SEC_AES_IV_LENGTH : XLP_SEC_DES_IV_LENGTH);
+ crypto_copydata(cmd->crp->crp_flags, cmd->crp->crp_buf,
+ crd->crd_skip + crd->crd_len - ivlen, ivlen,
+ sc->sc_sessions[cmd->session_num].ses_iv);
+ }
+ }
+
+ /* If there are not enough credits to send, then send request
+ * will fail with ERESTART and the driver will be blocked until it is
+ * unblocked here after knowing that there are sufficient credits to
+ * send the request again.
+ */
+ if (sc->sc_needwakeup) {
+ atomic_add_int(&creditleft, sc->sec_msgsz);
+ if (creditleft >= (NLM_CRYPTO_LEFT_REQS)) {
+ crypto_unblock(sc->sc_cid, sc->sc_needwakeup);
+ sc->sc_needwakeup &= (~(CRYPTO_SYMQ | CRYPTO_ASYMQ));
+ }
+ }
+ if(cmd->maccrd) {
+ crypto_copyback(cmd->crp->crp_flags,
+ cmd->crp->crp_buf, cmd->maccrd->crd_inject,
+ cmd->hash_dst_len, cmd->hashdest);
+ }
+
+ /* This indicates completion of the crypto operation */
+ crypto_done(cmd->crp);
+
+ xlp_free_cmd_params(cmd);
+
+ return;
+}
+
+static int
+xlp_sec_probe(device_t dev)
+{
+ struct xlp_sec_softc *sc;
+
+ if (pci_get_vendor(dev) == PCI_VENDOR_NETLOGIC &&
+ pci_get_device(dev) == PCI_DEVICE_ID_NLM_SAE) {
+ sc = device_get_softc(dev);
+ return (BUS_PROBE_DEFAULT);
+ }
+ return (ENXIO);
+}
+
+/*
+ * Attach an interface that successfully probed.
+ */
+static int
+xlp_sec_attach(device_t dev)
+{
+ struct xlp_sec_softc *sc = device_get_softc(dev);
+ uint64_t base;
+ int qstart, qnum;
+ int freq, node;
+
+ sc->sc_dev = dev;
+
+ node = nlm_get_device_node(pci_get_slot(dev));
+ freq = nlm_set_device_frequency(node, DFS_DEVICE_SAE, 250);
+ if (bootverbose)
+ device_printf(dev, "SAE Freq: %dMHz\n", freq);
+ if(pci_get_device(dev) == PCI_DEVICE_ID_NLM_SAE) {
+ device_set_desc(dev, "XLP Security Accelerator");
+ sc->sc_cid = crypto_get_driverid(dev, CRYPTOCAP_F_HARDWARE);
+ if (sc->sc_cid < 0) {
+ printf("xlp_sec - error : could not get the driver"
+ " id\n");
+ goto error_exit;
+ }
+ if (crypto_register(sc->sc_cid, CRYPTO_DES_CBC, 0, 0) != 0)
+ printf("register failed for CRYPTO_DES_CBC\n");
+
+ if (crypto_register(sc->sc_cid, CRYPTO_3DES_CBC, 0, 0) != 0)
+ printf("register failed for CRYPTO_3DES_CBC\n");
+
+ if (crypto_register(sc->sc_cid, CRYPTO_AES_CBC, 0, 0) != 0)
+ printf("register failed for CRYPTO_AES_CBC\n");
+
+ if (crypto_register(sc->sc_cid, CRYPTO_ARC4, 0, 0) != 0)
+ printf("register failed for CRYPTO_ARC4\n");
+
+ if (crypto_register(sc->sc_cid, CRYPTO_MD5, 0, 0) != 0)
+ printf("register failed for CRYPTO_MD5\n");
+
+ if (crypto_register(sc->sc_cid, CRYPTO_SHA1, 0, 0) != 0)
+ printf("register failed for CRYPTO_SHA1\n");
+
+ if (crypto_register(sc->sc_cid, CRYPTO_MD5_HMAC, 0, 0) != 0)
+ printf("register failed for CRYPTO_MD5_HMAC\n");
+
+ if (crypto_register(sc->sc_cid, CRYPTO_SHA1_HMAC, 0, 0) != 0)
+ printf("register failed for CRYPTO_SHA1_HMAC\n");
+
+ base = nlm_get_sec_pcibase(node);
+ qstart = nlm_qidstart(base);
+ qnum = nlm_qnum(base);
+ sc->sec_vc_start = qstart;
+ sc->sec_vc_end = qstart + qnum - 1;
+ }
+
+ if (xlp_sec_init(sc) != 0)
+ goto error_exit;
+ if (bootverbose)
+ device_printf(dev, "SEC Initialization complete!\n");
+ return (0);
+
+error_exit:
+ return (ENXIO);
+
+}
+
+/*
+ * Detach an interface that successfully probed.
+ */
+static int
+xlp_sec_detach(device_t dev)
+{
+ return (0);
+}
+
+/*
+ * Allocate a new 'session' and return an encoded session id. 'sidp'
+ * contains our registration id, and should contain an encoded session
+ * id on successful allocation.
+ */
+static int
+xlp_sec_newsession(device_t dev, u_int32_t *sidp, struct cryptoini *cri)
+{
+ struct cryptoini *c;
+ struct xlp_sec_softc *sc = device_get_softc(dev);
+ int mac = 0, cry = 0, sesn;
+ struct xlp_sec_session *ses = NULL;
+ struct xlp_sec_command *cmd = NULL;
+
+ if (sidp == NULL || cri == NULL || sc == NULL)
+ return (EINVAL);
+
+ if (sc->sc_sessions == NULL) {
+ ses = sc->sc_sessions = malloc(sizeof(struct xlp_sec_session),
+ M_DEVBUF, M_NOWAIT);
+ if (ses == NULL)
+ return (ENOMEM);
+ sesn = 0;
+ sc->sc_nsessions = 1;
+ } else {
+ for (sesn = 0; sesn < sc->sc_nsessions; sesn++) {
+ if (!sc->sc_sessions[sesn].hs_used) {
+ ses = &sc->sc_sessions[sesn];
+ break;
+ }
+ }
+
+ if (ses == NULL) {
+ sesn = sc->sc_nsessions;
+ ses = malloc((sesn + 1)*sizeof(struct xlp_sec_session),
+ M_DEVBUF, M_NOWAIT);
+ if (ses == NULL)
+ return (ENOMEM);
+ bcopy(sc->sc_sessions, ses, sesn * sizeof(*ses));
+ bzero(sc->sc_sessions, sesn * sizeof(*ses));
+ free(sc->sc_sessions, M_DEVBUF);
+ sc->sc_sessions = ses;
+ ses = &sc->sc_sessions[sesn];
+ sc->sc_nsessions++;
+ }
+ }
+ bzero(ses, sizeof(*ses));
+ ses->sessionid = sesn;
+ cmd = &ses->cmd;
+ ses->hs_used = 1;
+
+ for (c = cri; c != NULL; c = c->cri_next) {
+ switch (c->cri_alg) {
+ case CRYPTO_MD5:
+ case CRYPTO_SHA1:
+ case CRYPTO_MD5_HMAC:
+ case CRYPTO_SHA1_HMAC:
+ if (mac)
+ return (EINVAL);
+ mac = 1;
+ ses->hs_mlen = c->cri_mlen;
+ if (ses->hs_mlen == 0) {
+ switch (c->cri_alg) {
+ case CRYPTO_MD5:
+ case CRYPTO_MD5_HMAC:
+ ses->hs_mlen = 16;
+ break;
+ case CRYPTO_SHA1:
+ case CRYPTO_SHA1_HMAC:
+ ses->hs_mlen = 20;
+ break;
+ }
+ }
+ break;
+ case CRYPTO_DES_CBC:
+ case CRYPTO_3DES_CBC:
+ case CRYPTO_AES_CBC:
+ /* XXX this may read fewer, does it matter? */
+ read_random(ses->ses_iv, c->cri_alg ==
+ CRYPTO_AES_CBC ? XLP_SEC_AES_IV_LENGTH :
+ XLP_SEC_DES_IV_LENGTH);
+ /* FALLTHROUGH */
+ case CRYPTO_ARC4:
+ if (cry)
+ return (EINVAL);
+ cry = 1;
+ break;
+ default:
+ return (EINVAL);
+ }
+ }
+ if (mac == 0 && cry == 0)
+ return (EINVAL);
+
+ cmd->hash_dst_len = ses->hs_mlen;
+ *sidp = XLP_SEC_SID(device_get_unit(sc->sc_dev), sesn);
+ return (0);
+}
+
+/*
+ * Deallocate a session.
+ * XXX this routine should run a zero'd mac/encrypt key into context ram.
+ * XXX to blow away any keys already stored there.
+ */
+static int
+xlp_sec_freesession(device_t dev, u_int64_t tid)
+{
+ struct xlp_sec_softc *sc = device_get_softc(dev);
+ int session;
+ u_int32_t sid = CRYPTO_SESID2LID(tid);
+
+ if (sc == NULL)
+ return (EINVAL);
+
+ session = XLP_SEC_SESSION(sid);
+ if (session >= sc->sc_nsessions)
+ return (EINVAL);
+
+ sc->sc_sessions[session].hs_used = 0;
+ return (0);
+}
+
+static int
+xlp_copyiv(struct xlp_sec_softc *sc, struct xlp_sec_command *cmd,
+ struct cryptodesc *enccrd)
+{
+ unsigned int ivlen = 0;
+ int session;
+ struct cryptop *crp = NULL;
+
+ crp = cmd->crp;
+ session = cmd->session_num;
+
+ if (enccrd->crd_alg != CRYPTO_ARC4) {
+ ivlen = ((enccrd->crd_alg == CRYPTO_AES_CBC) ?
+ XLP_SEC_AES_IV_LENGTH : XLP_SEC_DES_IV_LENGTH);
+ if (enccrd->crd_flags & CRD_F_ENCRYPT) {
+ if (enccrd->crd_flags & CRD_F_IV_EXPLICIT) {
+ bcopy(enccrd->crd_iv, cmd->iv, ivlen);
+ } else {
+ bcopy(sc->sc_sessions[session].ses_iv, cmd->iv,
+ ivlen);
+ }
+ if ((enccrd->crd_flags & CRD_F_IV_PRESENT) == 0) {
+ crypto_copyback(crp->crp_flags,
+ crp->crp_buf, enccrd->crd_inject,
+ ivlen, cmd->iv);
+ }
+ } else {
+ if (enccrd->crd_flags & CRD_F_IV_EXPLICIT) {
+ bcopy(enccrd->crd_iv, cmd->iv, ivlen);
+ } else {
+ crypto_copydata(crp->crp_flags, crp->crp_buf,
+ enccrd->crd_inject, ivlen, cmd->iv);
+ }
+ }
+ }
+ return (0);
+}
+
+static int
+xlp_get_nsegs(struct cryptop *crp, unsigned int *nsegs)
+{
+
+ if (crp->crp_flags & CRYPTO_F_IMBUF) {
+ struct mbuf *m = NULL;
+
+ m = (struct mbuf *)crp->crp_buf;
+ while (m != NULL) {
+ *nsegs += NLM_CRYPTO_NUM_SEGS_REQD(m->m_len);
+ m = m->m_next;
+ }
+ } else if (crp->crp_flags & CRYPTO_F_IOV) {
+ struct uio *uio = NULL;
+ struct iovec *iov = NULL;
+ int iol = 0;
+
+ uio = (struct uio *)crp->crp_buf;
+ iov = (struct iovec *)uio->uio_iov;
+ iol = uio->uio_iovcnt;
+ while (iol > 0) {
+ *nsegs += NLM_CRYPTO_NUM_SEGS_REQD(iov->iov_len);
+ iol--;
+ iov++;
+ }
+ } else {
+ *nsegs = NLM_CRYPTO_NUM_SEGS_REQD(crp->crp_ilen);
+ }
+ return (0);
+}
+
+static int
+xlp_alloc_cmd_params(struct xlp_sec_command *cmd, unsigned int nsegs)
+{
+ int err = 0;
+
+ if(cmd == NULL) {
+ err = EINVAL;
+ goto error;
+ }
+ if ((cmd->ctrlp = malloc(sizeof(struct nlm_crypto_pkt_ctrl), M_DEVBUF,
+ M_NOWAIT | M_ZERO)) == NULL) {
+ err = ENOMEM;
+ goto error;
+ }
+ if (((uintptr_t)cmd->ctrlp & (XLP_L2L3_CACHELINE_SIZE - 1))) {
+ err = EINVAL;
+ goto error;
+ }
+ /* (nsegs - 1) because one seg is part of the structure already */
+ if ((cmd->paramp = malloc(sizeof(struct nlm_crypto_pkt_param) +
+ (16 * (nsegs - 1)), M_DEVBUF, M_NOWAIT | M_ZERO)) == NULL) {
+ err = ENOMEM;
+ goto error;
+ }
+ if (((uintptr_t)cmd->paramp & (XLP_L2L3_CACHELINE_SIZE - 1))) {
+ err = EINVAL;
+ goto error;
+ }
+ if ((cmd->iv = malloc(EALG_MAX_BLOCK_LEN, M_DEVBUF,
+ M_NOWAIT | M_ZERO)) == NULL) {
+ err = ENOMEM;
+ goto error;
+ }
+ if ((cmd->hashdest = malloc(HASH_MAX_LEN, M_DEVBUF,
+ M_NOWAIT | M_ZERO)) == NULL) {
+ err = ENOMEM;
+ goto error;
+ }
+error:
+ return (err);
+}
+
+static void
+xlp_free_cmd_params(struct xlp_sec_command *cmd)
+{
+ if (cmd->ctrlp != NULL)
+ free(cmd->ctrlp, M_DEVBUF);
+ if (cmd->paramp != NULL)
+ free(cmd->paramp, M_DEVBUF);
+ if (cmd->iv != NULL)
+ free(cmd->iv, M_DEVBUF);
+ if (cmd->hashdest != NULL)
+ free(cmd->hashdest, M_DEVBUF);
+ if (cmd != NULL)
+ free(cmd, M_DEVBUF);
+ return;
+}
+
+static int
+xlp_sec_process(device_t dev, struct cryptop *crp, int hint)
+{
+ struct xlp_sec_softc *sc = device_get_softc(dev);
+ struct xlp_sec_command *cmd = NULL;
+ int session, err = -1, ret = 0;
+ struct cryptodesc *crd1, *crd2;
+ struct xlp_sec_session *ses;
+ unsigned int nsegs = 0;
+
+ if (crp == NULL || crp->crp_callback == NULL) {
+ return (EINVAL);
+ }
+ session = XLP_SEC_SESSION(crp->crp_sid);
+ if (sc == NULL || session >= sc->sc_nsessions) {
+ err = EINVAL;
+ goto errout;
+ }
+ ses = &sc->sc_sessions[session];
+
+ if ((cmd = malloc(sizeof(struct xlp_sec_command), M_DEVBUF,
+ M_NOWAIT | M_ZERO)) == NULL) {
+ err = ENOMEM;
+ goto errout;
+ }
+
+ cmd->crp = crp;
+ cmd->session_num = session;
+ cmd->hash_dst_len = ses->hs_mlen;
+
+ if ((crd1 = crp->crp_desc) == NULL) {
+ err = EINVAL;
+ goto errout;
+ }
+ crd2 = crd1->crd_next;
+
+ if ((ret = xlp_get_nsegs(crp, &nsegs)) != 0) {
+ err = EINVAL;
+ goto errout;
+ }
+ if (((crd1 != NULL) && (crd1->crd_flags & CRD_F_IV_EXPLICIT)) ||
+ ((crd2 != NULL) && (crd2->crd_flags & CRD_F_IV_EXPLICIT))) {
+ /* Since IV is given as separate segment to avoid copy */
+ nsegs += 1;
+ }
+ cmd->nsegs = nsegs;
+
+ if ((err = xlp_alloc_cmd_params(cmd, nsegs)) != 0)
+ goto errout;
+
+ if ((crd1 != NULL) && (crd2 == NULL)) {
+ if (crd1->crd_alg == CRYPTO_DES_CBC ||
+ crd1->crd_alg == CRYPTO_3DES_CBC ||
+ crd1->crd_alg == CRYPTO_AES_CBC ||
+ crd1->crd_alg == CRYPTO_ARC4) {
+ cmd->enccrd = crd1;
+ cmd->maccrd = NULL;
+ if ((ret = nlm_get_cipher_param(cmd)) != 0) {
+ err = EINVAL;
+ goto errout;
+ }
+ if (crd1->crd_flags & CRD_F_IV_EXPLICIT)
+ cmd->cipheroff = cmd->ivlen;
+ else
+ cmd->cipheroff = cmd->enccrd->crd_skip;
+ cmd->cipherlen = cmd->enccrd->crd_len;
+ if (crd1->crd_flags & CRD_F_IV_PRESENT)
+ cmd->ivoff = 0;
+ else
+ cmd->ivoff = cmd->enccrd->crd_inject;
+ if ((err = xlp_copyiv(sc, cmd, cmd->enccrd)) != 0)
+ goto errout;
+ if ((err = nlm_crypto_do_cipher(sc, cmd)) != 0)
+ goto errout;
+ } else if (crd1->crd_alg == CRYPTO_MD5_HMAC ||
+ crd1->crd_alg == CRYPTO_SHA1_HMAC ||
+ crd1->crd_alg == CRYPTO_SHA1 ||
+ crd1->crd_alg == CRYPTO_MD5) {
+ cmd->enccrd = NULL;
+ cmd->maccrd = crd1;
+ if ((ret = nlm_get_digest_param(cmd)) != 0) {
+ err = EINVAL;
+ goto errout;
+ }
+ cmd->hashoff = cmd->maccrd->crd_skip;
+ cmd->hashlen = cmd->maccrd->crd_len;
+ cmd->hmacpad = 0;
+ cmd->hashsrc = 0;
+ if ((err = nlm_crypto_do_digest(sc, cmd)) != 0)
+ goto errout;
+ } else {
+ err = EINVAL;
+ goto errout;
+ }
+ } else if( (crd1 != NULL) && (crd2 != NULL) ) {
+ if ((crd1->crd_alg == CRYPTO_MD5_HMAC ||
+ crd1->crd_alg == CRYPTO_SHA1_HMAC ||
+ crd1->crd_alg == CRYPTO_MD5 ||
+ crd1->crd_alg == CRYPTO_SHA1) &&
+ (crd2->crd_alg == CRYPTO_DES_CBC ||
+ crd2->crd_alg == CRYPTO_3DES_CBC ||
+ crd2->crd_alg == CRYPTO_AES_CBC ||
+ crd2->crd_alg == CRYPTO_ARC4)) {
+ cmd->maccrd = crd1;
+ cmd->enccrd = crd2;
+ } else if ((crd1->crd_alg == CRYPTO_DES_CBC ||
+ crd1->crd_alg == CRYPTO_ARC4 ||
+ crd1->crd_alg == CRYPTO_3DES_CBC ||
+ crd1->crd_alg == CRYPTO_AES_CBC) &&
+ (crd2->crd_alg == CRYPTO_MD5_HMAC ||
+ crd2->crd_alg == CRYPTO_SHA1_HMAC ||
+ crd2->crd_alg == CRYPTO_MD5 ||
+ crd2->crd_alg == CRYPTO_SHA1)) {
+ cmd->enccrd = crd1;
+ cmd->maccrd = crd2;
+ } else {
+ err = EINVAL;
+ goto errout;
+ }
+ if ((ret = nlm_get_cipher_param(cmd)) != 0) {
+ err = EINVAL;
+ goto errout;
+ }
+ if ((ret = nlm_get_digest_param(cmd)) != 0) {
+ err = EINVAL;
+ goto errout;
+ }
+ cmd->ivoff = cmd->enccrd->crd_inject;
+ cmd->hashoff = cmd->maccrd->crd_skip;
+ cmd->hashlen = cmd->maccrd->crd_len;
+ cmd->hmacpad = 0;
+ if (cmd->enccrd->crd_flags & CRD_F_ENCRYPT)
+ cmd->hashsrc = 1;
+ else
+ cmd->hashsrc = 0;
+ cmd->cipheroff = cmd->enccrd->crd_skip;
+ cmd->cipherlen = cmd->enccrd->crd_len;
+ if ((err = xlp_copyiv(sc, cmd, cmd->enccrd)) != 0)
+ goto errout;
+ if ((err = nlm_crypto_do_cipher_digest(sc, cmd)) != 0)
+ goto errout;
+ } else {
+ err = EINVAL;
+ goto errout;
+ }
+ return (0);
+errout:
+ xlp_free_cmd_params(cmd);
+ if (err == ERESTART) {
+ sc->sc_needwakeup |= CRYPTO_SYMQ;
+ creditleft = 0;
+ return (err);
+ }
+ crp->crp_etype = err;
+ crypto_done(crp);
+ return (err);
+}
Property changes on: trunk/sys/mips/nlm/dev/sec/nlmsec.c
___________________________________________________________________
Added: svn:eol-style
## -0,0 +1 ##
+native
\ No newline at end of property
Added: svn:keywords
## -0,0 +1 ##
+MidnightBSD=%H
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+text/plain
\ No newline at end of property
Added: trunk/sys/mips/nlm/dev/sec/nlmseclib.c
===================================================================
--- trunk/sys/mips/nlm/dev/sec/nlmseclib.c (rev 0)
+++ trunk/sys/mips/nlm/dev/sec/nlmseclib.c 2018-05-26 21:55:02 UTC (rev 9987)
@@ -0,0 +1,308 @@
+/* $MidnightBSD$ */
+/*-
+ * Copyright (c) 2003-2012 Broadcom Corporation
+ * All Rights Reserved
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in
+ * the documentation and/or other materials provided with the
+ * distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY BROADCOM ``AS IS'' AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL BROADCOM OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
+ * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
+ * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
+ * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <sys/cdefs.h>
+__FBSDID("$FreeBSD: stable/10/sys/mips/nlm/dev/sec/nlmseclib.c 233541 2012-03-27 11:43:46Z jchandra $");
+
+#include <sys/param.h>
+#include <sys/types.h>
+#include <sys/systm.h>
+#include <sys/kernel.h>
+#include <sys/module.h>
+#include <sys/malloc.h>
+#include <sys/mbuf.h>
+#include <sys/lock.h>
+#include <sys/mutex.h>
+#include <sys/bus.h>
+#include <sys/uio.h>
+#include <machine/bus.h>
+#include <machine/md_var.h>
+#include <machine/cpuregs.h>
+
+#include <vm/vm.h>
+#include <vm/pmap.h>
+
+#include <opencrypto/cryptodev.h>
+
+#include <mips/nlm/hal/haldefs.h>
+#include <mips/nlm/hal/cop2.h>
+#include <mips/nlm/hal/fmn.h>
+#include <mips/nlm/hal/mips-extns.h>
+#include <mips/nlm/hal/nlmsaelib.h>
+#include <mips/nlm/dev/sec/nlmseclib.h>
+
+static int
+nlm_crypto_complete_sec_request(struct xlp_sec_softc *sc,
+ struct xlp_sec_command *cmd)
+{
+ unsigned int fbvc;
+ struct nlm_fmn_msg m;
+ int ret;
+
+ fbvc = nlm_cpuid() / CMS_MAX_VCPU_VC;
+ m.msg[0] = m.msg[1] = m.msg[2] = m.msg[3] = 0;
+
+ m.msg[0] = nlm_crypto_form_pkt_fmn_entry0(fbvc, 0, 0,
+ cmd->ctrlp->cipherkeylen, vtophys(cmd->ctrlp));
+
+ m.msg[1] = nlm_crypto_form_pkt_fmn_entry1(0, cmd->ctrlp->hashkeylen,
+ NLM_CRYPTO_PKT_DESC_SIZE(cmd->nsegs), vtophys(cmd->paramp));
+
+ /* Software scratch pad */
+ m.msg[2] = (uintptr_t)cmd;
+ sc->sec_msgsz = 3;
+
+ /* Send the message to sec/rsa engine vc */
+ ret = nlm_fmn_msgsend(sc->sec_vc_start, sc->sec_msgsz,
+ FMN_SWCODE_CRYPTO, &m);
+ if (ret != 0) {
+#ifdef NLM_SEC_DEBUG
+ printf("%s: msgsnd failed (%x)\n", __func__, ret);
+#endif
+ return (ERESTART);
+ }
+ return (0);
+}
+
+int
+nlm_crypto_form_srcdst_segs(struct xlp_sec_command *cmd)
+{
+ unsigned int srcseg = 0, dstseg = 0;
+ struct cryptodesc *cipdesc = NULL;
+ struct cryptop *crp = NULL;
+
+ crp = cmd->crp;
+ cipdesc = cmd->enccrd;
+
+ if (cipdesc != NULL) {
+ /* IV is given as ONE segment to avoid copy */
+ if (cipdesc->crd_flags & CRD_F_IV_EXPLICIT) {
+ srcseg = nlm_crypto_fill_src_seg(cmd->paramp, srcseg,
+ cmd->iv, cmd->ivlen);
+ dstseg = nlm_crypto_fill_dst_seg(cmd->paramp, dstseg,
+ cmd->iv, cmd->ivlen);
+ }
+ }
+
+ if (crp->crp_flags & CRYPTO_F_IMBUF) {
+ struct mbuf *m = NULL;
+
+ m = (struct mbuf *)crp->crp_buf;
+ while (m != NULL) {
+ srcseg = nlm_crypto_fill_src_seg(cmd->paramp, srcseg,
+ mtod(m,caddr_t), m->m_len);
+ if (cipdesc != NULL) {
+ dstseg = nlm_crypto_fill_dst_seg(cmd->paramp,
+ dstseg, mtod(m,caddr_t), m->m_len);
+ }
+ m = m->m_next;
+ }
+ } else if (crp->crp_flags & CRYPTO_F_IOV) {
+ struct uio *uio = NULL;
+ struct iovec *iov = NULL;
+ int iol = 0;
+
+ uio = (struct uio *)crp->crp_buf;
+ iov = (struct iovec *)uio->uio_iov;
+ iol = uio->uio_iovcnt;
+
+ while (iol > 0) {
+ srcseg = nlm_crypto_fill_src_seg(cmd->paramp, srcseg,
+ (caddr_t)iov->iov_base, iov->iov_len);
+ if (cipdesc != NULL) {
+ dstseg = nlm_crypto_fill_dst_seg(cmd->paramp,
+ dstseg, (caddr_t)iov->iov_base,
+ iov->iov_len);
+ }
+ iov++;
+ iol--;
+ }
+ } else {
+ srcseg = nlm_crypto_fill_src_seg(cmd->paramp, srcseg,
+ ((caddr_t)crp->crp_buf), crp->crp_ilen);
+ if (cipdesc != NULL) {
+ dstseg = nlm_crypto_fill_dst_seg(cmd->paramp, dstseg,
+ ((caddr_t)crp->crp_buf), crp->crp_ilen);
+ }
+ }
+ return (0);
+}
+
+int
+nlm_crypto_do_cipher(struct xlp_sec_softc *sc, struct xlp_sec_command *cmd)
+{
+ struct cryptodesc *cipdesc = NULL;
+ unsigned char *cipkey = NULL;
+ int ret = 0;
+
+ cipdesc = cmd->enccrd;
+ cipkey = (unsigned char *)cipdesc->crd_key;
+ if (cmd->cipheralg == NLM_CIPHER_3DES) {
+ if (!(cipdesc->crd_flags & CRD_F_ENCRYPT)) {
+ uint64_t *k, *tkey;
+ k = (uint64_t *)cipdesc->crd_key;
+ tkey = (uint64_t *)cmd->des3key;
+ tkey[2] = k[0];
+ tkey[1] = k[1];
+ tkey[0] = k[2];
+ cipkey = (unsigned char *)tkey;
+ }
+ }
+ nlm_crypto_fill_pkt_ctrl(cmd->ctrlp, 0, NLM_HASH_BYPASS, 0,
+ cmd->cipheralg, cmd->ciphermode, cipkey,
+ (cipdesc->crd_klen >> 3), NULL, 0);
+
+ nlm_crypto_fill_cipher_pkt_param(cmd->ctrlp, cmd->paramp,
+ (cipdesc->crd_flags & CRD_F_ENCRYPT) ? 1 : 0, cmd->ivoff,
+ cmd->ivlen, cmd->cipheroff, cmd->cipherlen);
+ nlm_crypto_form_srcdst_segs(cmd);
+
+ ret = nlm_crypto_complete_sec_request(sc, cmd);
+ return (ret);
+}
+
+int
+nlm_crypto_do_digest(struct xlp_sec_softc *sc, struct xlp_sec_command *cmd)
+{
+ struct cryptodesc *digdesc = NULL;
+ int ret=0;
+
+ digdesc = cmd->maccrd;
+
+ nlm_crypto_fill_pkt_ctrl(cmd->ctrlp, (digdesc->crd_klen) ? 1 : 0,
+ cmd->hashalg, cmd->hashmode, NLM_CIPHER_BYPASS, 0,
+ NULL, 0, digdesc->crd_key, digdesc->crd_klen >> 3);
+
+ nlm_crypto_fill_auth_pkt_param(cmd->ctrlp, cmd->paramp,
+ cmd->hashoff, cmd->hashlen, cmd->hmacpad,
+ (unsigned char *)cmd->hashdest);
+
+ nlm_crypto_form_srcdst_segs(cmd);
+
+ ret = nlm_crypto_complete_sec_request(sc, cmd);
+
+ return (ret);
+}
+
+int
+nlm_crypto_do_cipher_digest(struct xlp_sec_softc *sc,
+ struct xlp_sec_command *cmd)
+{
+ struct cryptodesc *cipdesc=NULL, *digdesc=NULL;
+ unsigned char *cipkey = NULL;
+ int ret=0;
+
+ cipdesc = cmd->enccrd;
+ digdesc = cmd->maccrd;
+
+ cipkey = (unsigned char *)cipdesc->crd_key;
+ if (cmd->cipheralg == NLM_CIPHER_3DES) {
+ if (!(cipdesc->crd_flags & CRD_F_ENCRYPT)) {
+ uint64_t *k, *tkey;
+ k = (uint64_t *)cipdesc->crd_key;
+ tkey = (uint64_t *)cmd->des3key;
+ tkey[2] = k[0];
+ tkey[1] = k[1];
+ tkey[0] = k[2];
+ cipkey = (unsigned char *)tkey;
+ }
+ }
+ nlm_crypto_fill_pkt_ctrl(cmd->ctrlp, (digdesc->crd_klen) ? 1 : 0,
+ cmd->hashalg, cmd->hashmode, cmd->cipheralg, cmd->ciphermode,
+ cipkey, (cipdesc->crd_klen >> 3),
+ digdesc->crd_key, (digdesc->crd_klen >> 3));
+
+ nlm_crypto_fill_cipher_auth_pkt_param(cmd->ctrlp, cmd->paramp,
+ (cipdesc->crd_flags & CRD_F_ENCRYPT) ? 1 : 0, cmd->hashsrc,
+ cmd->ivoff, cmd->ivlen, cmd->hashoff, cmd->hashlen,
+ cmd->hmacpad, cmd->cipheroff, cmd->cipherlen,
+ (unsigned char *)cmd->hashdest);
+
+ nlm_crypto_form_srcdst_segs(cmd);
+
+ ret = nlm_crypto_complete_sec_request(sc, cmd);
+ return (ret);
+}
+
+int
+nlm_get_digest_param(struct xlp_sec_command *cmd)
+{
+ switch(cmd->maccrd->crd_alg) {
+ case CRYPTO_MD5:
+ cmd->hashalg = NLM_HASH_MD5;
+ cmd->hashmode = NLM_HASH_MODE_SHA1;
+ break;
+ case CRYPTO_SHA1:
+ cmd->hashalg = NLM_HASH_SHA;
+ cmd->hashmode = NLM_HASH_MODE_SHA1;
+ break;
+ case CRYPTO_MD5_HMAC:
+ cmd->hashalg = NLM_HASH_MD5;
+ cmd->hashmode = NLM_HASH_MODE_SHA1;
+ break;
+ case CRYPTO_SHA1_HMAC:
+ cmd->hashalg = NLM_HASH_SHA;
+ cmd->hashmode = NLM_HASH_MODE_SHA1;
+ break;
+ default:
+ /* Not supported */
+ return (-1);
+ }
+ return (0);
+}
+int
+nlm_get_cipher_param(struct xlp_sec_command *cmd)
+{
+ switch(cmd->enccrd->crd_alg) {
+ case CRYPTO_DES_CBC:
+ cmd->cipheralg = NLM_CIPHER_DES;
+ cmd->ciphermode = NLM_CIPHER_MODE_CBC;
+ cmd->ivlen = XLP_SEC_DES_IV_LENGTH;
+ break;
+ case CRYPTO_3DES_CBC:
+ cmd->cipheralg = NLM_CIPHER_3DES;
+ cmd->ciphermode = NLM_CIPHER_MODE_CBC;
+ cmd->ivlen = XLP_SEC_DES_IV_LENGTH;
+ break;
+ case CRYPTO_AES_CBC:
+ cmd->cipheralg = NLM_CIPHER_AES128;
+ cmd->ciphermode = NLM_CIPHER_MODE_CBC;
+ cmd->ivlen = XLP_SEC_AES_IV_LENGTH;
+ break;
+ case CRYPTO_ARC4:
+ cmd->cipheralg = NLM_CIPHER_ARC4;
+ cmd->ciphermode = NLM_CIPHER_MODE_ECB;
+ cmd->ivlen = XLP_SEC_ARC4_IV_LENGTH;
+ break;
+ default:
+ /* Not supported */
+ return (-1);
+ }
+ return (0);
+}
Property changes on: trunk/sys/mips/nlm/dev/sec/nlmseclib.c
___________________________________________________________________
Added: svn:eol-style
## -0,0 +1 ##
+native
\ No newline at end of property
Added: svn:keywords
## -0,0 +1 ##
+MidnightBSD=%H
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+text/plain
\ No newline at end of property
Added: trunk/sys/mips/nlm/dev/sec/nlmseclib.h
===================================================================
--- trunk/sys/mips/nlm/dev/sec/nlmseclib.h (rev 0)
+++ trunk/sys/mips/nlm/dev/sec/nlmseclib.h 2018-05-26 21:55:02 UTC (rev 9987)
@@ -0,0 +1,158 @@
+/* $MidnightBSD$ */
+/*-
+ * Copyright (c) 2003-2012 Broadcom Corporation
+ * All Rights Reserved
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in
+ * the documentation and/or other materials provided with the
+ * distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY BROADCOM ``AS IS'' AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL BROADCOM OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
+ * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
+ * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
+ * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * $FreeBSD: stable/10/sys/mips/nlm/dev/sec/nlmseclib.h 233541 2012-03-27 11:43:46Z jchandra $
+ */
+
+#ifndef _NLMSECLIB_H_
+#define _NLMSECLIB_H_
+
+/*
+ * Cryptographic parameter definitions
+ */
+#define XLP_SEC_DES_KEY_LENGTH 8 /* Bytes */
+#define XLP_SEC_3DES_KEY_LENGTH 24 /* Bytes */
+#define XLP_SEC_AES128_KEY_LENGTH 16 /* Bytes */
+#define XLP_SEC_AES192_KEY_LENGTH 24 /* Bytes */
+#define XLP_SEC_AES256_KEY_LENGTH 32 /* Bytes */
+#define XLP_SEC_AES128F8_KEY_LENGTH 32 /* Bytes */
+#define XLP_SEC_AES192F8_KEY_LENGTH 48 /* Bytes */
+#define XLP_SEC_AES256F8_KEY_LENGTH 64 /* Bytes */
+#define XLP_SEC_KASUMI_F8_KEY_LENGTH 16 /* Bytes */
+#define XLP_SEC_MAX_CRYPT_KEY_LENGTH XLP_SEC_AES256F8_KEY_LENGTH
+
+
+#define XLP_SEC_DES_IV_LENGTH 8 /* Bytes */
+#define XLP_SEC_AES_IV_LENGTH 16 /* Bytes */
+#define XLP_SEC_ARC4_IV_LENGTH 0 /* Bytes */
+#define XLP_SEC_KASUMI_F8_IV_LENGTH 16 /* Bytes */
+#define XLP_SEC_MAX_IV_LENGTH 16 /* Bytes */
+#define XLP_SEC_IV_LENGTH_BYTES 8 /* Bytes */
+
+#define XLP_SEC_AES_BLOCK_SIZE 16 /* Bytes */
+#define XLP_SEC_DES_BLOCK_SIZE 8 /* Bytes */
+#define XLP_SEC_3DES_BLOCK_SIZE 8 /* Bytes */
+
+#define XLP_SEC_MD5_BLOCK_SIZE 64 /* Bytes */
+#define XLP_SEC_SHA1_BLOCK_SIZE 64 /* Bytes */
+#define XLP_SEC_SHA256_BLOCK_SIZE 64 /* Bytes */
+#define XLP_SEC_SHA384_BLOCK_SIZE 128 /* Bytes */
+#define XLP_SEC_SHA512_BLOCK_SIZE 128 /* Bytes */
+#define XLP_SEC_GCM_BLOCK_SIZE 16 /* XXX: Bytes */
+#define XLP_SEC_KASUMI_F9_BLOCK_SIZE 16 /* XXX: Bytes */
+#define XLP_SEC_MAX_BLOCK_SIZE 64 /* Max of MD5/SHA */
+#define XLP_SEC_MD5_LENGTH 16 /* Bytes */
+#define XLP_SEC_SHA1_LENGTH 20 /* Bytes */
+#define XLP_SEC_SHA256_LENGTH 32 /* Bytes */
+#define XLP_SEC_SHA384_LENGTH 64 /* Bytes */
+#define XLP_SEC_SHA512_LENGTH 64 /* Bytes */
+#define XLP_SEC_GCM_LENGTH 16 /* Bytes */
+#define XLP_SEC_KASUMI_F9_LENGTH 16 /* Bytes */
+#define XLP_SEC_KASUMI_F9_RESULT_LENGTH 4 /* Bytes */
+#define XLP_SEC_HMAC_LENGTH 64 /* Max of MD5/SHA/SHA256 */
+#define XLP_SEC_MAX_AUTH_KEY_LENGTH XLP_SEC_SHA512_BLOCK_SIZE
+#define XLP_SEC_MAX_RC4_STATE_SIZE 264 /* char s[256], int i, int j */
+
+#define XLP_SEC_SESSION(sid) ((sid) & 0x000007ff)
+#define XLP_SEC_SID(crd,ses) (((crd) << 28) | ((ses) & 0x7ff))
+
+#define CRYPTO_ERROR(msg1) ((unsigned int)msg1)
+
+#define NLM_CRYPTO_LEFT_REQS (CMS_DEFAULT_CREDIT/2)
+#define NLM_CRYPTO_NUM_SEGS_REQD(__bufsize) \
+ ((__bufsize + NLM_CRYPTO_MAX_SEG_LEN - 1) / NLM_CRYPTO_MAX_SEG_LEN)
+
+#define NLM_CRYPTO_PKT_DESC_SIZE(nsegs) (32 + (nsegs * 16))
+
+extern unsigned int creditleft;
+
+struct xlp_sec_command {
+ uint16_t session_num;
+ struct cryptop *crp;
+ struct cryptodesc *enccrd, *maccrd;
+ struct xlp_sec_session *ses;
+ struct nlm_crypto_pkt_ctrl *ctrlp;
+ struct nlm_crypto_pkt_param *paramp;
+ void *iv;
+ uint8_t des3key[24];
+ uint8_t *hashdest;
+ uint8_t hashsrc;
+ uint8_t hmacpad;
+ uint32_t hashoff;
+ uint32_t hashlen;
+ uint32_t cipheroff;
+ uint32_t cipherlen;
+ uint32_t ivoff;
+ uint32_t ivlen;
+ uint32_t hashalg;
+ uint32_t hashmode;
+ uint32_t cipheralg;
+ uint32_t ciphermode;
+ uint32_t nsegs;
+ uint32_t hash_dst_len; /* used to store hash alg dst size */
+};
+
+struct xlp_sec_session {
+ uint32_t sessionid;
+ int hs_used;
+ int hs_mlen;
+ uint8_t ses_iv[EALG_MAX_BLOCK_LEN];
+ struct xlp_sec_command cmd;
+};
+
+/*
+ * Holds data specific to nlm security accelerators
+ */
+struct xlp_sec_softc {
+ device_t sc_dev; /* device backpointer */
+ uint64_t sec_base;
+ int32_t sc_cid;
+ struct xlp_sec_session *sc_sessions;
+ int sc_nsessions;
+ int sc_needwakeup;
+ uint32_t sec_vc_start;
+ uint32_t sec_vc_end;
+ uint32_t sec_msgsz;
+};
+
+#ifdef NLM_SEC_DEBUG
+void print_crypto_params(struct xlp_sec_command *cmd, struct nlm_fmn_msg m);
+void xlp_sec_print_data(struct cryptop *crp);
+void print_cmd(struct xlp_sec_command *cmd);
+#endif
+int nlm_crypto_form_srcdst_segs(struct xlp_sec_command *cmd);
+int nlm_crypto_do_cipher(struct xlp_sec_softc *sc,
+ struct xlp_sec_command *cmd);
+int nlm_crypto_do_digest(struct xlp_sec_softc *sc,
+ struct xlp_sec_command *cmd);
+int nlm_crypto_do_cipher_digest(struct xlp_sec_softc *sc,
+ struct xlp_sec_command *cmd);
+int nlm_get_digest_param(struct xlp_sec_command *cmd);
+int nlm_get_cipher_param(struct xlp_sec_command *cmd);
+
+#endif /* _NLMSECLIB_H_ */
Property changes on: trunk/sys/mips/nlm/dev/sec/nlmseclib.h
___________________________________________________________________
Added: svn:eol-style
## -0,0 +1 ##
+native
\ No newline at end of property
Added: svn:keywords
## -0,0 +1 ##
+MidnightBSD=%H
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+text/plain
\ No newline at end of property
Added: trunk/sys/mips/nlm/dev/sec/rsa_ucode.h
===================================================================
--- trunk/sys/mips/nlm/dev/sec/rsa_ucode.h (rev 0)
+++ trunk/sys/mips/nlm/dev/sec/rsa_ucode.h 2018-05-26 21:55:02 UTC (rev 9987)
@@ -0,0 +1,957 @@
+/* $MidnightBSD$ */
+/*-
+ * Copyright (c) 2003-2012 Broadcom Corporation
+ * All Rights Reserved
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in
+ * the documentation and/or other materials provided with the
+ * distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY BROADCOM ``AS IS'' AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL BROADCOM OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
+ * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
+ * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
+ * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * $FreeBSD: stable/10/sys/mips/nlm/dev/sec/rsa_ucode.h 233541 2012-03-27 11:43:46Z jchandra $
+ */
+
+#ifndef _NLM_HAL_RSA_UCODE_H
+#define _NLM_HAL_RSA_UCODE_H
+static uint64_t nlm_rsa_ucode_data [] = {
+ 0x0000000000000000ULL,
+ 0x00000000503840ecULL,
+ 0x00000001903800ecULL,
+ 0x00000002c03820ecULL,
+ 0x0000003760000044ULL,
+ 0x0000000000000014ULL,
+ 0x000000071000000cULL,
+ 0x00000007d000010cULL,
+ 0x0000001b80000c0cULL,
+ 0x00000000e03fc0ecULL,
+ 0x00000001103fc1ecULL,
+ 0x00000001403f42ecULL,
+ 0x00000001403fc4ecULL,
+ 0x0000003760000044ULL,
+ 0x000000001800003cULL,
+ 0x0000000d8000030cULL,
+ 0x0000000630000044ULL,
+ 0x000000002800003cULL,
+ 0x0000000ef000030cULL,
+ 0x0000000630000044ULL,
+ 0x00000000503fc23cULL,
+ 0x00000000a03fc33cULL,
+ 0x00000001403fc43cULL,
+ 0x00000010c000030cULL,
+ 0x0000000630000044ULL,
+ 0x0000000000000014ULL,
+ 0x000000071000000cULL,
+ 0x0000001c1000070cULL,
+ 0x0000002500000d0cULL,
+ 0x00000027c0000e0cULL,
+ 0x0000002d60000f0cULL,
+ 0x00000002603f00ecULL,
+ 0x00000002603f82ecULL,
+ 0x00000002803f83ecULL,
+ 0x00000002803f04ecULL,
+ 0x00000002a03f06ecULL,
+ 0x00000002a03f88ecULL,
+ 0x0000003760000044ULL,
+ 0x000000086000010cULL,
+ 0x00000003f0000044ULL,
+ 0x00000008d000010cULL,
+ 0x00000004b0000044ULL,
+ 0x00000008d000010cULL,
+ 0x0000000570000044ULL,
+ 0x000000000000001cULL,
+ 0x000000076000000cULL,
+ 0x0000001c1000070cULL,
+ 0x0000002690000d0cULL,
+ 0x0000002990000e0cULL,
+ 0x0000002e10000f0cULL,
+ 0x00000003903f20ecULL,
+ 0x00000003903fa2ecULL,
+ 0x00000003b03fa3ecULL,
+ 0x00000003b03f24ecULL,
+ 0x00000003d03f26ecULL,
+ 0x00000003d03fa8ecULL,
+ 0x0000003760000044ULL,
+ 0x000000096000010cULL,
+ 0x00000003f0000044ULL,
+ 0x0000000a0000010cULL,
+ 0x00000004b0000044ULL,
+ 0x0000000a0000010cULL,
+ 0x0000000570000044ULL,
+ 0x000000000800003cULL,
+ 0x0000000af000020cULL,
+ 0x0000000bc000030cULL,
+ 0x000000129000040cULL,
+ 0x000000178000050cULL,
+ 0x000000191000060cULL,
+ 0x0000001ff000080cULL,
+ 0x000000205000090cULL,
+ 0x00000022c0000a0cULL,
+ 0x00000020b0000b0cULL,
+ 0x0000001ac0000c0cULL,
+ 0x0000000680000044ULL,
+ 0x000000001000003cULL,
+ 0x0000000b5000020cULL,
+ 0x0000000c5000030cULL,
+ 0x000000137000040cULL,
+ 0x00000017e000050cULL,
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+ 0x000000040400000aULL,
+ 0x000000000000002cULL,
+ 0x0000000c0000800eULL,
+ 0x0000000c0400880aULL,
+ 0x000000080000007cULL,
+ 0x0000000004000002ULL,
+ 0x00000006808b0013ULL,
+ 0x0000000000000034ULL,
+ 0x0000000000000002ULL,
+ 0x0000002ff000005cULL,
+ 0x0000002f4000004cULL,
+ 0x00000002000b0101ULL,
+ 0x0000000a000b0003ULL,
+ 0x0000003760000044ULL,
+ 0x0000000000000034ULL,
+ 0x0000000c0000000aULL,
+ 0x0000002ff0000054ULL,
+ 0x0000000c0000800aULL,
+ 0x0000002fb000004cULL,
+ 0x0000003640000044ULL,
+ 0x0000000c0000800aULL,
+ 0x000000040400000aULL,
+ 0x000000000000002cULL,
+ 0x0000000c0000800eULL,
+ 0x0000000c0400880aULL,
+ 0x000000080000007cULL,
+ 0x000000040400000aULL,
+ 0x000000000000002cULL,
+ 0x0000000c0000800eULL,
+ 0x0000000c0400880aULL,
+ 0x000000080000007cULL,
+ 0x0000003640000044ULL,
+ 0x000000080180000aULL,
+ 0x0000000001820002ULL,
+ 0x00000007040b0013ULL,
+ 0x000000040200000aULL,
+ 0x000000000000002cULL,
+ 0x0000000c0180430eULL,
+ 0x0000000c0200440aULL,
+ 0x000000080000007cULL,
+ 0x0000000001010002ULL,
+ 0x00000006108b0093ULL,
+ 0x0000000005010002ULL,
+ 0x00000006108b0093ULL,
+ 0x0000000000000000ULL,
+ 0x00000032e01f80e4ULL,
+ 0x00000034401f81e4ULL,
+ 0x00000034601f82e4ULL,
+ 0x0000000c0181020aULL,
+ 0x0000000c0181030aULL,
+ 0x0000001c000000d4ULL,
+ 0x0000000000004002ULL,
+ 0x0000005000a0410aULL,
+ 0x0000000001004202ULL,
+ 0x000000500021000aULL,
+ 0x0000000000810102ULL,
+ 0x000000500121020aULL,
+ 0x000000200000202aULL,
+ 0x00000000000000fcULL,
+ 0x0000000c000000a4ULL,
+ 0x0000000000000002ULL,
+ 0x0000000600098003ULL,
+ 0x0000000000810002ULL,
+ 0x0000000610898093ULL,
+ 0x0000003760000044ULL,
+ 0x0000000004000002ULL,
+ 0x00000006808b0013ULL,
+ 0x0000000004800102ULL,
+ 0x00000006808b0013ULL,
+ 0x0000000005000202ULL,
+ 0x00000006808b0013ULL,
+ 0x0000000000000034ULL,
+ 0x0000000000000002ULL,
+ 0x000000342000005cULL,
+ 0x000000334000004cULL,
+ 0x0000001000000084ULL,
+ 0x00000006000b0009ULL,
+ 0x00000002000b0101ULL,
+ 0x0000002000000084ULL,
+ 0x00000006000b0009ULL,
+ 0x0000003760000044ULL,
+ 0x0000000000000034ULL,
+ 0x00000034000000d4ULL,
+ 0x0000003420000054ULL,
+ 0x00000038000000d4ULL,
+ 0x00000033e000004cULL,
+ 0x00000031d0000044ULL,
+ 0x00000038000000d4ULL,
+ 0x00000031d0000044ULL,
+ 0x00000034000000d4ULL,
+ 0x00000031d0000044ULL,
+ 0x000000080180000aULL,
+ 0x0000000001820002ULL,
+ 0x00000007040b0013ULL,
+ 0x0000000005840002ULL,
+ 0x00000007040b0013ULL,
+ 0x0000003c000000d4ULL,
+ 0x00000004000000a4ULL,
+ 0x000000200000402aULL,
+ 0x0000000000000012ULL,
+ 0x00000000000b0001ULL,
+ 0x0000000000098101ULL,
+ 0x0000003760000044ULL,
+ 0x000000040200000aULL,
+ 0x000000000000002cULL,
+ 0x0000000c0000400eULL,
+ 0x0000000c0200440aULL,
+ 0x000000080000007cULL,
+ 0x00000036c01f87e4ULL,
+ 0x00000036401f89e4ULL,
+ 0x000000040200000aULL,
+ 0x000000000000002cULL,
+ 0x0000000c0400480eULL,
+ 0x0000000c0200440aULL,
+ 0x000000080000007cULL,
+ 0x00000036a01f86e4ULL,
+ 0x000000080180000aULL,
+ 0x00000036601f84e4ULL,
+ 0x00000036801f85e4ULL,
+ 0x000000300001000aULL,
+ 0x0000003760000044ULL,
+ 0x000000140006800aULL,
+ 0x0000003640000044ULL,
+ 0x000000180006800aULL,
+ 0x0000003640000044ULL,
+ 0x0000000c0000800aULL,
+ 0x0000003640000044ULL,
+ 0x0000000c0181080aULL,
+ 0x0000001c000000d4ULL,
+ 0x00000004000000a4ULL,
+ 0x0000000c0000400aULL,
+ 0x0000003640000044ULL,
+ 0x0000000c0181000aULL,
+ 0x0000001c000000d4ULL,
+ 0x00000004000000a4ULL,
+ 0x000000140001140aULL,
+ 0x0000003640000044ULL,
+ 0x0000000c000000a4ULL,
+ 0x0000000000000044ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL,
+};
+
+#endif /* _NLM_HAL_RSA_UCODE_H_ */
Property changes on: trunk/sys/mips/nlm/dev/sec/rsa_ucode.h
___________________________________________________________________
Added: svn:eol-style
## -0,0 +1 ##
+native
\ No newline at end of property
Added: svn:keywords
## -0,0 +1 ##
+MidnightBSD=%H
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+text/plain
\ No newline at end of property
Added: trunk/sys/mips/nlm/dev/uart_pci_xlp.c
===================================================================
--- trunk/sys/mips/nlm/dev/uart_pci_xlp.c (rev 0)
+++ trunk/sys/mips/nlm/dev/uart_pci_xlp.c 2018-05-26 21:55:02 UTC (rev 9987)
@@ -0,0 +1,84 @@
+/* $MidnightBSD$ */
+/*-
+ * Copyright (c) 2003-2012 Broadcom Corporation
+ * All Rights Reserved
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in
+ * the documentation and/or other materials provided with the
+ * distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY BROADCOM ``AS IS'' AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL BROADCOM OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
+ * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
+ * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
+ * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <sys/cdefs.h>
+__FBSDID("$FreeBSD: stable/10/sys/mips/nlm/dev/uart_pci_xlp.c 233549 2012-03-27 14:48:40Z jchandra $");
+
+#include <sys/param.h>
+#include <sys/systm.h>
+#include <sys/bus.h>
+#include <sys/conf.h>
+#include <sys/kernel.h>
+#include <sys/module.h>
+#include <machine/bus.h>
+#include <sys/rman.h>
+#include <machine/resource.h>
+
+#include <dev/pci/pcivar.h>
+
+#include <mips/nlm/hal/haldefs.h>
+#include <mips/nlm/hal/iomap.h>
+#include <mips/nlm/hal/uart.h>
+
+#include <dev/uart/uart.h>
+#include <dev/uart/uart_bus.h>
+
+static int uart_soc_probe(device_t dev);
+
+static device_method_t uart_soc_methods[] = {
+ /* Device interface */
+ DEVMETHOD(device_probe, uart_soc_probe),
+ DEVMETHOD(device_attach, uart_bus_attach),
+ DEVMETHOD(device_detach, uart_bus_detach),
+
+ DEVMETHOD_END
+};
+
+static driver_t uart_soc_driver = {
+ uart_driver_name,
+ uart_soc_methods,
+ sizeof(struct uart_softc),
+};
+
+static int
+uart_soc_probe(device_t dev)
+{
+ struct uart_softc *sc;
+
+ if (pci_get_vendor(dev) != PCI_VENDOR_NETLOGIC ||
+ pci_get_device(dev) != PCI_DEVICE_ID_NLM_UART)
+ return (ENXIO);
+
+ sc = device_get_softc(dev);
+ sc->sc_class = &uart_ns8250_class;
+ device_set_desc(dev, "Netlogic SoC UART");
+ return (uart_bus_probe(dev, 2, XLP_IO_CLK, 0, 0));
+}
+
+DRIVER_MODULE(uart_soc, pci, uart_soc_driver, uart_devclass, 0, 0);
Property changes on: trunk/sys/mips/nlm/dev/uart_pci_xlp.c
___________________________________________________________________
Added: svn:eol-style
## -0,0 +1 ##
+native
\ No newline at end of property
Added: svn:keywords
## -0,0 +1 ##
+MidnightBSD=%H
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+text/plain
\ No newline at end of property
Added: trunk/sys/mips/nlm/files.xlp
===================================================================
--- trunk/sys/mips/nlm/files.xlp (rev 0)
+++ trunk/sys/mips/nlm/files.xlp 2018-05-26 21:55:02 UTC (rev 9987)
@@ -0,0 +1,42 @@
+# $FreeBSD: stable/10/sys/mips/nlm/files.xlp 233637 2012-03-29 02:03:06Z jmallett $
+mips/nlm/hal/nlm_hal.c standard
+mips/nlm/hal/fmn.c standard
+mips/nlm/xlp_machdep.c standard
+mips/nlm/intr_machdep.c standard
+mips/nlm/tick.c standard
+mips/nlm/board.c standard
+mips/nlm/cms.c standard
+mips/nlm/bus_space_rmi.c standard
+mips/nlm/bus_space_rmi_pci.c standard
+mips/nlm/mpreset.S standard
+mips/nlm/board_eeprom.c standard
+mips/nlm/board_cpld.c standard
+mips/nlm/xlp_pci.c optional pci
+mips/nlm/uart_cpu_xlp.c optional uart
+mips/nlm/usb_init.c optional usb
+#
+# Simple SoC devices
+mips/nlm/dev/uart_pci_xlp.c optional uart
+mips/nlm/dev/cfi_pci_xlp.c optional cfi
+#
+# Network driver and micro-core code
+mips/nlm/dev/net/nae.c optional xlpge
+mips/nlm/dev/net/mdio.c optional xlpge
+mips/nlm/dev/net/sgmii.c optional xlpge
+mips/nlm/dev/net/xaui.c optional xlpge
+mips/nlm/dev/net/xlpge.c optional xlpge
+ucore_app.bin optional xlpge \
+ compile-with "${CC} -EB -march=mips32 -mabi=32 -msoft-float -I. -I$S -O3 -funroll-loops -finline-limit=20000 -fno-tree-loop-optimize -fomit-frame-pointer -mno-branch-likely -fno-pic -mno-abicalls -ffunction-sections -fdata-sections -G0 -Wall -Werror -c $S/$M/nlm/dev/net/ucore/crt0_basic.S $S/$M/nlm/dev/net/ucore/ucore_app.c && ${LD} -melf32btsmip_fbsd -d -warn-common -T$S/$M/nlm/dev/net/ucore/ld.ucore.S crt0_basic.o ucore_app.o -o ucore_app && ${OBJCOPY} -S -O binary -R .note -R .comment ucore_app ${.TARGET}" \
+ no-obj no-implicit-rule before-depend \
+ clean "crt0_basic.o ucore_app.o ucore_app ucore_app.bin"
+ucore_app_bin.h optional xlpge \
+ dependency "ucore_app.bin" \
+ compile-with "file2c -sx 'static char ucore_app_bin[] = {' '};' < ucore_app.bin > ${.TARGET}" \
+ no-obj no-implicit-rule before-depend \
+ clean "ucore_app_bin.h"
+#
+# Security Driver
+#
+mips/nlm/dev/sec/nlmsec.c optional nlmsec
+mips/nlm/dev/sec/nlmseclib.c optional nlmsec
+mips/nlm/dev/sec/nlmrsa.c optional nlmrsa
Property changes on: trunk/sys/mips/nlm/files.xlp
___________________________________________________________________
Added: mnbsd:nokeywords
## -0,0 +1 ##
+MidnightBSD=%H
\ No newline at end of property
Added: trunk/sys/mips/nlm/hal/bridge.h
===================================================================
--- trunk/sys/mips/nlm/hal/bridge.h (rev 0)
+++ trunk/sys/mips/nlm/hal/bridge.h 2018-05-26 21:55:02 UTC (rev 9987)
@@ -0,0 +1,185 @@
+/* $MidnightBSD$ */
+/*-
+ * Copyright 2003-2011 Netlogic Microsystems (Netlogic). All rights
+ * reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in
+ * the documentation and/or other materials provided with the
+ * distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY Netlogic Microsystems ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL NETLOGIC OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
+ * THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * NETLOGIC_BSD
+ * $FreeBSD: stable/10/sys/mips/nlm/hal/bridge.h 227722 2011-11-19 14:06:15Z jchandra $
+ */
+
+#ifndef __NLM_HAL_BRIDGE_H__
+#define __NLM_HAL_BRIDGE_H__
+
+/**
+* @file_name mio.h
+* @author Netlogic Microsystems
+* @brief Basic definitions of XLP memory and io subsystem
+*/
+
+/*
+ * BRIDGE specific registers
+ *
+ * These registers start after the PCIe header, which has 0x40
+ * standard entries
+ */
+#define BRIDGE_MODE 0x00
+#define BRIDGE_PCI_CFG_BASE 0x01
+#define BRIDGE_PCI_CFG_LIMIT 0x02
+#define BRIDGE_PCIE_CFG_BASE 0x03
+#define BRIDGE_PCIE_CFG_LIMIT 0x04
+#define BRIDGE_BUSNUM_BAR0 0x05
+#define BRIDGE_BUSNUM_BAR1 0x06
+#define BRIDGE_BUSNUM_BAR2 0x07
+#define BRIDGE_BUSNUM_BAR3 0x08
+#define BRIDGE_BUSNUM_BAR4 0x09
+#define BRIDGE_BUSNUM_BAR5 0x0a
+#define BRIDGE_BUSNUM_BAR6 0x0b
+#define BRIDGE_FLASH_BAR0 0x0c
+#define BRIDGE_FLASH_BAR1 0x0d
+#define BRIDGE_FLASH_BAR2 0x0e
+#define BRIDGE_FLASH_BAR3 0x0f
+#define BRIDGE_FLASH_LIMIT0 0x10
+#define BRIDGE_FLASH_LIMIT1 0x11
+#define BRIDGE_FLASH_LIMIT2 0x12
+#define BRIDGE_FLASH_LIMIT3 0x13
+
+#define BRIDGE_DRAM_BAR(i) (0x14 + (i))
+#define BRIDGE_DRAM_BAR0 0x14
+#define BRIDGE_DRAM_BAR1 0x15
+#define BRIDGE_DRAM_BAR2 0x16
+#define BRIDGE_DRAM_BAR3 0x17
+#define BRIDGE_DRAM_BAR4 0x18
+#define BRIDGE_DRAM_BAR5 0x19
+#define BRIDGE_DRAM_BAR6 0x1a
+#define BRIDGE_DRAM_BAR7 0x1b
+
+#define BRIDGE_DRAM_LIMIT(i) (0x1c + (i))
+#define BRIDGE_DRAM_LIMIT0 0x1c
+#define BRIDGE_DRAM_LIMIT1 0x1d
+#define BRIDGE_DRAM_LIMIT2 0x1e
+#define BRIDGE_DRAM_LIMIT3 0x1f
+#define BRIDGE_DRAM_LIMIT4 0x20
+#define BRIDGE_DRAM_LIMIT5 0x21
+#define BRIDGE_DRAM_LIMIT6 0x22
+#define BRIDGE_DRAM_LIMIT7 0x23
+
+#define BRIDGE_DRAM_NODE_TRANSLN0 0x24
+#define BRIDGE_DRAM_NODE_TRANSLN1 0x25
+#define BRIDGE_DRAM_NODE_TRANSLN2 0x26
+#define BRIDGE_DRAM_NODE_TRANSLN3 0x27
+#define BRIDGE_DRAM_NODE_TRANSLN4 0x28
+#define BRIDGE_DRAM_NODE_TRANSLN5 0x29
+#define BRIDGE_DRAM_NODE_TRANSLN6 0x2a
+#define BRIDGE_DRAM_NODE_TRANSLN7 0x2b
+#define BRIDGE_DRAM_CHNL_TRANSLN0 0x2c
+#define BRIDGE_DRAM_CHNL_TRANSLN1 0x2d
+#define BRIDGE_DRAM_CHNL_TRANSLN2 0x2e
+#define BRIDGE_DRAM_CHNL_TRANSLN3 0x2f
+#define BRIDGE_DRAM_CHNL_TRANSLN4 0x30
+#define BRIDGE_DRAM_CHNL_TRANSLN5 0x31
+#define BRIDGE_DRAM_CHNL_TRANSLN6 0x32
+#define BRIDGE_DRAM_CHNL_TRANSLN7 0x33
+#define BRIDGE_PCIEMEM_BASE0 0x34
+#define BRIDGE_PCIEMEM_BASE1 0x35
+#define BRIDGE_PCIEMEM_BASE2 0x36
+#define BRIDGE_PCIEMEM_BASE3 0x37
+#define BRIDGE_PCIEMEM_LIMIT0 0x38
+#define BRIDGE_PCIEMEM_LIMIT1 0x39
+#define BRIDGE_PCIEMEM_LIMIT2 0x3a
+#define BRIDGE_PCIEMEM_LIMIT3 0x3b
+#define BRIDGE_PCIEIO_BASE0 0x3c
+#define BRIDGE_PCIEIO_BASE1 0x3d
+#define BRIDGE_PCIEIO_BASE2 0x3e
+#define BRIDGE_PCIEIO_BASE3 0x3f
+#define BRIDGE_PCIEIO_LIMIT0 0x40
+#define BRIDGE_PCIEIO_LIMIT1 0x41
+#define BRIDGE_PCIEIO_LIMIT2 0x42
+#define BRIDGE_PCIEIO_LIMIT3 0x43
+#define BRIDGE_PCIEMEM_BASE4 0x44
+#define BRIDGE_PCIEMEM_BASE5 0x45
+#define BRIDGE_PCIEMEM_BASE6 0x46
+#define BRIDGE_PCIEMEM_LIMIT4 0x47
+#define BRIDGE_PCIEMEM_LIMIT5 0x48
+#define BRIDGE_PCIEMEM_LIMIT6 0x49
+#define BRIDGE_PCIEIO_BASE4 0x4a
+#define BRIDGE_PCIEIO_BASE5 0x4b
+#define BRIDGE_PCIEIO_BASE6 0x4c
+#define BRIDGE_PCIEIO_LIMIT4 0x4d
+#define BRIDGE_PCIEIO_LIMIT5 0x4e
+#define BRIDGE_PCIEIO_LIMIT6 0x4f
+#define BRIDGE_NBU_EVENT_CNT_CTL 0x50
+#define BRIDGE_EVNTCTR1_LOW 0x51
+#define BRIDGE_EVNTCTR1_HI 0x52
+#define BRIDGE_EVNT_CNT_CTL2 0x53
+#define BRIDGE_EVNTCTR2_LOW 0x54
+#define BRIDGE_EVNTCTR2_HI 0x55
+#define BRIDGE_TRACEBUF_MATCH0 0x56
+#define BRIDGE_TRACEBUF_MATCH1 0x57
+#define BRIDGE_TRACEBUF_MATCH_LOW 0x58
+#define BRIDGE_TRACEBUF_MATCH_HI 0x59
+#define BRIDGE_TRACEBUF_CTRL 0x5a
+#define BRIDGE_TRACEBUF_INIT 0x5b
+#define BRIDGE_TRACEBUF_ACCESS 0x5c
+#define BRIDGE_TRACEBUF_READ_DATA0 0x5d
+#define BRIDGE_TRACEBUF_READ_DATA1 0x5d
+#define BRIDGE_TRACEBUF_READ_DATA2 0x5f
+#define BRIDGE_TRACEBUF_READ_DATA3 0x60
+#define BRIDGE_TRACEBUF_STATUS 0x61
+#define BRIDGE_ADDRESS_ERROR0 0x62
+#define BRIDGE_ADDRESS_ERROR1 0x63
+#define BRIDGE_ADDRESS_ERROR2 0x64
+#define BRIDGE_TAG_ECC_ADDR_ERROR0 0x65
+#define BRIDGE_TAG_ECC_ADDR_ERROR1 0x66
+#define BRIDGE_TAG_ECC_ADDR_ERROR2 0x67
+#define BRIDGE_LINE_FLUSH0 0x68
+#define BRIDGE_LINE_FLUSH1 0x69
+#define BRIDGE_NODE_ID 0x6a
+#define BRIDGE_ERROR_INTERRUPT_EN 0x6b
+#define BRIDGE_PCIE0_WEIGHT 0x2c0
+#define BRIDGE_PCIE1_WEIGHT 0x2c1
+#define BRIDGE_PCIE2_WEIGHT 0x2c2
+#define BRIDGE_PCIE3_WEIGHT 0x2c3
+#define BRIDGE_USB_WEIGHT 0x2c4
+#define BRIDGE_NET_WEIGHT 0x2c5
+#define BRIDGE_POE_WEIGHT 0x2c6
+#define BRIDGE_CMS_WEIGHT 0x2c7
+#define BRIDGE_DMAENG_WEIGHT 0x2c8
+#define BRIDGE_SEC_WEIGHT 0x2c9
+#define BRIDGE_COMP_WEIGHT 0x2ca
+#define BRIDGE_GIO_WEIGHT 0x2cb
+#define BRIDGE_FLASH_WEIGHT 0x2cc
+
+#if !defined(LOCORE) && !defined(__ASSEMBLY__)
+
+#define nlm_read_bridge_reg(b, r) nlm_read_reg(b, r)
+#define nlm_write_bridge_reg(b, r, v) nlm_write_reg(b, r, v)
+#define nlm_get_bridge_pcibase(node) \
+ nlm_pcicfg_base(XLP_IO_BRIDGE_OFFSET(node))
+#define nlm_get_bridge_regbase(node) \
+ (nlm_get_bridge_pcibase(node) + XLP_IO_PCI_HDRSZ)
+
+#endif
+#endif
Property changes on: trunk/sys/mips/nlm/hal/bridge.h
___________________________________________________________________
Added: svn:eol-style
## -0,0 +1 ##
+native
\ No newline at end of property
Added: svn:keywords
## -0,0 +1 ##
+MidnightBSD=%H
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+text/plain
\ No newline at end of property
Added: trunk/sys/mips/nlm/hal/cop2.h
===================================================================
--- trunk/sys/mips/nlm/hal/cop2.h (rev 0)
+++ trunk/sys/mips/nlm/hal/cop2.h 2018-05-26 21:55:02 UTC (rev 9987)
@@ -0,0 +1,303 @@
+/* $MidnightBSD$ */
+/*-
+ * Copyright 2003-2011 Netlogic Microsystems (Netlogic). All rights
+ * reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in
+ * the documentation and/or other materials provided with the
+ * distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY Netlogic Microsystems ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL NETLOGIC OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
+ * THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * NETLOGIC_BSD
+ * $FreeBSD: stable/10/sys/mips/nlm/hal/cop2.h 227783 2011-11-21 08:12:36Z jchandra $
+ */
+
+#ifndef __NLM_HAL_COP2_H__
+#define __NLM_HAL_COP2_H__
+
+#define COP2_TX_BUF 0
+#define COP2_RX_BUF 1
+#define COP2_TXMSGSTATUS 2
+#define COP2_RXMSGSTATUS 3
+#define COP2_MSGSTATUS1 4
+#define COP2_MSGCONFIG 5
+#define COP2_MSGERROR 6
+
+#define CROSSTHR_POPQ_EN 0x01
+#define VC0_POPQ_EN 0x02
+#define VC1_POPQ_EN 0x04
+#define VC2_POPQ_EN 0x08
+#define VC3_POPQ_EN 0x10
+#define ALL_VC_POPQ_EN 0x1E
+#define ALL_VC_CT_POPQ_EN 0x1F
+
+struct nlm_fmn_msg {
+ uint64_t msg[4];
+};
+
+#define NLM_DEFINE_COP2_ACCESSORS32(name, reg, sel) \
+static inline uint32_t nlm_read_c2_##name(void) \
+{ \
+ uint32_t __rv; \
+ __asm__ __volatile__ ( \
+ ".set push\n" \
+ ".set noreorder\n" \
+ ".set mips64\n" \
+ "mfc2 %0, $%1, %2\n" \
+ ".set pop\n" \
+ : "=r" (__rv) \
+ : "i" (reg), "i" (sel)); \
+ return __rv; \
+} \
+ \
+static inline void nlm_write_c2_##name(uint32_t val) \
+{ \
+ __asm__ __volatile__( \
+ ".set push\n" \
+ ".set noreorder\n" \
+ ".set mips64\n" \
+ "mtc2 %0, $%1, %2\n" \
+ ".set pop\n" \
+ : : "r" (val), "i" (reg), "i" (sel)); \
+} struct __hack
+
+#if (__mips == 64)
+#define NLM_DEFINE_COP2_ACCESSORS64(name, reg, sel) \
+static inline uint64_t nlm_read_c2_##name(void) \
+{ \
+ uint64_t __rv; \
+ __asm__ __volatile__ ( \
+ ".set push\n" \
+ ".set noreorder\n" \
+ ".set mips64\n" \
+ "dmfc2 %0, $%1, %2\n" \
+ ".set pop\n" \
+ : "=r" (__rv) \
+ : "i" (reg), "i" (sel)); \
+ return __rv; \
+} \
+ \
+static inline void nlm_write_c2_##name(uint64_t val) \
+{ \
+ __asm__ __volatile__ ( \
+ ".set push\n" \
+ ".set noreorder\n" \
+ ".set mips64\n" \
+ "dmtc2 %0, $%1, %2\n" \
+ ".set pop\n" \
+ : : "r" (val), "i" (reg), "i" (sel)); \
+} struct __hack
+
+#else
+
+#define NLM_DEFINE_COP2_ACCESSORS64(name, reg, sel) \
+static inline uint64_t nlm_read_c2_##name(void) \
+{ \
+ uint32_t __high, __low; \
+ __asm__ __volatile__ ( \
+ ".set push\n" \
+ ".set noreorder\n" \
+ ".set mips64\n" \
+ "dmfc2 $8, $%2, %3\n" \
+ "dsra32 %0, $8, 0\n" \
+ "sll %1, $8, 0\n" \
+ ".set pop\n" \
+ : "=r"(__high), "=r"(__low) \
+ : "i"(reg), "i"(sel) \
+ : "$8"); \
+ \
+ return ((uint64_t)__high << 32) | __low; \
+} \
+ \
+static inline void nlm_write_c2_##name(uint64_t val) \
+{ \
+ uint32_t __high = val >> 32; \
+ uint32_t __low = val & 0xffffffff; \
+ __asm__ __volatile__ ( \
+ ".set push\n" \
+ ".set noreorder\n" \
+ ".set mips64\n" \
+ "dsll32 $8, %1, 0\n" \
+ "dsll32 $9, %0, 0\n" \
+ "dsrl32 $8, $8, 0\n" \
+ "or $8, $8, $9\n" \
+ "dmtc2 $8, $%2, %3\n" \
+ ".set pop\n" \
+ : : "r"(__high), "r"(__low), "i"(reg), "i"(sel) \
+ : "$8", "$9"); \
+} struct __hack
+
+#endif
+
+NLM_DEFINE_COP2_ACCESSORS64(txbuf0, COP2_TX_BUF, 0);
+NLM_DEFINE_COP2_ACCESSORS64(txbuf1, COP2_TX_BUF, 1);
+NLM_DEFINE_COP2_ACCESSORS64(txbuf2, COP2_TX_BUF, 2);
+NLM_DEFINE_COP2_ACCESSORS64(txbuf3, COP2_TX_BUF, 3);
+
+NLM_DEFINE_COP2_ACCESSORS64(rxbuf0, COP2_RX_BUF, 0);
+NLM_DEFINE_COP2_ACCESSORS64(rxbuf1, COP2_RX_BUF, 1);
+NLM_DEFINE_COP2_ACCESSORS64(rxbuf2, COP2_RX_BUF, 2);
+NLM_DEFINE_COP2_ACCESSORS64(rxbuf3, COP2_RX_BUF, 3);
+
+NLM_DEFINE_COP2_ACCESSORS32(txmsgstatus, COP2_TXMSGSTATUS, 0);
+NLM_DEFINE_COP2_ACCESSORS32(rxmsgstatus, COP2_RXMSGSTATUS, 0);
+NLM_DEFINE_COP2_ACCESSORS32(msgstatus1, COP2_MSGSTATUS1, 0);
+NLM_DEFINE_COP2_ACCESSORS32(msgconfig, COP2_MSGCONFIG, 0);
+NLM_DEFINE_COP2_ACCESSORS32(msgerror0, COP2_MSGERROR, 0);
+NLM_DEFINE_COP2_ACCESSORS32(msgerror1, COP2_MSGERROR, 1);
+NLM_DEFINE_COP2_ACCESSORS32(msgerror2, COP2_MSGERROR, 2);
+NLM_DEFINE_COP2_ACCESSORS32(msgerror3, COP2_MSGERROR, 3);
+
+/* successful completion returns 1, else 0 */
+static inline int
+nlm_msgsend(int val)
+{
+ int result;
+ __asm__ volatile (
+ ".set push\n"
+ ".set noreorder\n"
+ ".set mips64\n"
+ "move $8, %1\n"
+ "sync\n"
+ "/* msgsnds $9, $8 */\n"
+ ".word 0x4a084801\n"
+ "move %0, $9\n"
+ ".set pop\n"
+ : "=r" (result)
+ : "r" (val)
+ : "$8", "$9");
+ return result;
+}
+
+static inline int
+nlm_msgld(int vc)
+{
+ int val;
+ __asm__ volatile (
+ ".set push\n"
+ ".set noreorder\n"
+ ".set mips64\n"
+ "move $8, %1\n"
+ "/* msgld $9, $8 */\n"
+ ".word 0x4a084802\n"
+ "move %0, $9\n"
+ ".set pop\n"
+ : "=r" (val)
+ : "r" (vc)
+ : "$8", "$9");
+ return val;
+}
+
+static inline void
+nlm_msgwait(int vc)
+{
+ __asm__ volatile (
+ ".set push\n"
+ ".set noreorder\n"
+ ".set mips64\n"
+ "move $8, %0\n"
+ "/* msgwait $8 */\n"
+ ".word 0x4a080003\n"
+ ".set pop\n"
+ : : "r" (vc)
+ : "$8");
+}
+
+static inline int
+nlm_fmn_msgsend(int dstid, int size, int swcode, struct nlm_fmn_msg *m)
+{
+ uint32_t flags, status;
+ int rv;
+
+ size -= 1;
+ flags = nlm_save_flags_cop2();
+ switch (size) {
+ case 3:
+ nlm_write_c2_txbuf3(m->msg[3]);
+ case 2:
+ nlm_write_c2_txbuf2(m->msg[2]);
+ case 1:
+ nlm_write_c2_txbuf1(m->msg[1]);
+ case 0:
+ nlm_write_c2_txbuf0(m->msg[0]);
+ }
+
+ dstid |= ((swcode << 24) | (size << 16));
+ status = nlm_msgsend(dstid);
+ rv = !status;
+ if (rv != 0)
+ rv = nlm_read_c2_txmsgstatus();
+ nlm_restore_flags(flags);
+
+ return rv;
+}
+
+static inline int
+nlm_fmn_msgrcv(int vc, int *srcid, int *size, int *code, struct nlm_fmn_msg *m)
+{
+ uint32_t status;
+ uint32_t msg_status, flags;
+ int tmp_sz, rv;
+
+ flags = nlm_save_flags_cop2();
+ status = nlm_msgld(vc); /* will return 0, if error */
+ rv = !status;
+ if (rv == 0) {
+ msg_status = nlm_read_c2_rxmsgstatus();
+ *size = ((msg_status >> 26) & 0x3) + 1;
+ *code = (msg_status >> 18) & 0xff;
+ *srcid = (msg_status >> 4) & 0xfff;
+ tmp_sz = *size - 1;
+ switch (tmp_sz) {
+ case 3:
+ m->msg[3] = nlm_read_c2_rxbuf3();
+ case 2:
+ m->msg[2] = nlm_read_c2_rxbuf2();
+ case 1:
+ m->msg[1] = nlm_read_c2_rxbuf1();
+ case 0:
+ m->msg[0] = nlm_read_c2_rxbuf0();
+ }
+ }
+ nlm_restore_flags(flags);
+
+ return rv;
+}
+
+static inline void
+nlm_fmn_cpu_init(int int_vec, int ecc_en, int v0pe, int v1pe, int v2pe, int v3pe)
+{
+ uint32_t val = nlm_read_c2_msgconfig();
+
+ /* Note: in XLP PRM 0.8.1, the int_vec bits are un-documented
+ * in msgconfig register of cop2.
+ * As per chip/cpu RTL, [16:20] bits consist of int_vec.
+ */
+ val |= (((int_vec & 0x1f) << 16) |
+ ((ecc_en & 0x1) << 8) |
+ ((v3pe & 0x1) << 4) |
+ ((v2pe & 0x1) << 3) |
+ ((v1pe & 0x1) << 2) |
+ ((v0pe & 0x1) << 1));
+
+ nlm_write_c2_msgconfig(val);
+}
+#endif
Property changes on: trunk/sys/mips/nlm/hal/cop2.h
___________________________________________________________________
Added: svn:eol-style
## -0,0 +1 ##
+native
\ No newline at end of property
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## -0,0 +1 ##
+MidnightBSD=%H
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## -0,0 +1 ##
+text/plain
\ No newline at end of property
Added: trunk/sys/mips/nlm/hal/cpucontrol.h
===================================================================
--- trunk/sys/mips/nlm/hal/cpucontrol.h (rev 0)
+++ trunk/sys/mips/nlm/hal/cpucontrol.h 2018-05-26 21:55:02 UTC (rev 9987)
@@ -0,0 +1,195 @@
+/* $MidnightBSD$ */
+/*-
+ * Copyright 2003-2011 Netlogic Microsystems (Netlogic). All rights
+ * reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in
+ * the documentation and/or other materials provided with the
+ * distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY Netlogic Microsystems ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL NETLOGIC OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
+ * THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * NETLOGIC_BSD
+ * $FreeBSD: stable/10/sys/mips/nlm/hal/cpucontrol.h 228271 2011-12-05 02:56:08Z jchandra $
+ */
+
+#ifndef __NLM_HAL_CPUCONTROL_H__
+#define __NLM_HAL_CPUCONTROL_H__
+
+#define CPU_BLOCKID_IFU 0
+#define CPU_BLOCKID_ICU 1
+#define CPU_BLOCKID_IEU 2
+#define CPU_BLOCKID_LSU 3
+#define CPU_BLOCKID_MMU 4
+#define CPU_BLOCKID_PRF 5
+#define CPU_BLOCKID_SCH 7
+#define CPU_BLOCKID_SCU 8
+#define CPU_BLOCKID_FPU 9
+#define CPU_BLOCKID_MAP 10
+
+#define LSU_DEFEATURE 0x304
+#define LSU_DEBUG_ADDR 0x305
+#define LSU_DEBUG_DATA0 0x306
+#define LSU_CERRLOG_REGID 0x09
+#define SCHED_DEFEATURE 0x700
+
+/* Offsets of interest from the 'MAP' Block */
+#define MAP_THREADMODE 0x00
+#define MAP_EXT_EBASE_ENABLE 0x04
+#define MAP_CCDI_CONFIG 0x08
+#define MAP_THRD0_CCDI_STATUS 0x0c
+#define MAP_THRD1_CCDI_STATUS 0x10
+#define MAP_THRD2_CCDI_STATUS 0x14
+#define MAP_THRD3_CCDI_STATUS 0x18
+#define MAP_THRD0_DEBUG_MODE 0x1c
+#define MAP_THRD1_DEBUG_MODE 0x20
+#define MAP_THRD2_DEBUG_MODE 0x24
+#define MAP_THRD3_DEBUG_MODE 0x28
+#define MAP_MISC_STATE 0x60
+#define MAP_DEBUG_READ_CTL 0x64
+#define MAP_DEBUG_READ_REG0 0x68
+#define MAP_DEBUG_READ_REG1 0x6c
+
+#define MMU_SETUP 0x400
+#define MMU_LFSRSEED 0x401
+#define MMU_HPW_NUM_PAGE_LVL 0x410
+#define MMU_PGWKR_PGDBASE 0x411
+#define MMU_PGWKR_PGDSHFT 0x412
+#define MMU_PGWKR_PGDMASK 0x413
+#define MMU_PGWKR_PUDSHFT 0x414
+#define MMU_PGWKR_PUDMASK 0x415
+#define MMU_PGWKR_PMDSHFT 0x416
+#define MMU_PGWKR_PMDMASK 0x417
+#define MMU_PGWKR_PTESHFT 0x418
+#define MMU_PGWKR_PTEMASK 0x419
+
+
+#if !defined(LOCORE) && !defined(__ASSEMBLY__)
+#if defined(__mips_n64) || defined(__mips_n32)
+static __inline uint64_t
+nlm_mfcr(uint32_t reg)
+{
+ uint64_t res;
+
+ __asm__ __volatile__(
+ ".set push\n\t"
+ ".set noreorder\n\t"
+ "move $9, %1\n\t"
+ ".word 0x71280018\n\t" /* mfcr $8, $9 */
+ "move %0, $8\n\t"
+ ".set pop\n"
+ : "=r" (res) : "r"(reg)
+ : "$8", "$9"
+ );
+ return (res);
+}
+
+static __inline void
+nlm_mtcr(uint32_t reg, uint64_t value)
+{
+ __asm__ __volatile__(
+ ".set push\n\t"
+ ".set noreorder\n\t"
+ "move $8, %0\n"
+ "move $9, %1\n"
+ ".word 0x71280019\n" /* mtcr $8, $9 */
+ ".set pop\n"
+ :
+ : "r" (value), "r" (reg)
+ : "$8", "$9"
+ );
+}
+
+#else /* !(defined(__mips_n64) || defined(__mips_n32)) */
+
+static __inline__ uint64_t
+nlm_mfcr(uint32_t reg)
+{
+ uint32_t hi, lo;
+
+ __asm__ __volatile__ (
+ ".set push\n"
+ ".set mips64\n"
+ "move $8, %2\n"
+ ".word 0x71090018\n"
+ "nop \n"
+ "dsra32 %0, $9, 0\n"
+ "sll %1, $9, 0\n"
+ ".set pop\n"
+ : "=r"(hi), "=r"(lo)
+ : "r"(reg) : "$8", "$9");
+
+ return (((uint64_t)hi) << 32) | lo;
+}
+
+static __inline__ void
+nlm_mtcr(uint32_t reg, uint64_t val)
+{
+ uint32_t hi, lo;
+
+ hi = val >> 32;
+ lo = val & 0xffffffff;
+
+ __asm__ __volatile__ (
+ ".set push\n"
+ ".set mips64\n"
+ "move $9, %0\n"
+ "dsll32 $9, %1, 0\n"
+ "dsll32 $8, %0, 0\n"
+ "dsrl32 $9, $9, 0\n"
+ "or $9, $9, $8\n"
+ "move $8, %2\n"
+ ".word 0x71090019\n"
+ "nop \n"
+ ".set pop\n"
+ : :"r"(hi), "r"(lo), "r"(reg)
+ : "$8", "$9");
+}
+#endif /* (defined(__mips_n64) || defined(__mips_n32)) */
+
+/* hashindex_en = 1 to enable hash mode, hashindex_en=0 to disable
+ * global_mode = 1 to enable global mode, global_mode=0 to disable
+ * clk_gating = 0 to enable clock gating, clk_gating=1 to disable
+ */
+static __inline__ void nlm_mmu_setup(int hashindex_en, int global_mode,
+ int clk_gating)
+{
+ uint32_t mmusetup = 0;
+
+ mmusetup |= (hashindex_en << 13);
+ mmusetup |= (clk_gating << 3);
+ mmusetup |= (global_mode << 0);
+ nlm_mtcr(MMU_SETUP, mmusetup);
+}
+
+static __inline__ void nlm_mmu_lfsr_seed (int thr0_seed, int thr1_seed,
+ int thr2_seed, int thr3_seed)
+{
+ uint32_t seed = nlm_mfcr(MMU_LFSRSEED);
+
+ seed |= ((thr3_seed & 0x7f) << 23);
+ seed |= ((thr2_seed & 0x7f) << 16);
+ seed |= ((thr1_seed & 0x7f) << 7);
+ seed |= ((thr0_seed & 0x7f) << 0);
+ nlm_mtcr(MMU_LFSRSEED, seed);
+}
+
+#endif /* __ASSEMBLY__ */
+#endif /* __NLM_CPUCONTROL_H__ */
Property changes on: trunk/sys/mips/nlm/hal/cpucontrol.h
___________________________________________________________________
Added: svn:eol-style
## -0,0 +1 ##
+native
\ No newline at end of property
Added: svn:keywords
## -0,0 +1 ##
+MidnightBSD=%H
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+text/plain
\ No newline at end of property
Added: trunk/sys/mips/nlm/hal/fmn.c
===================================================================
--- trunk/sys/mips/nlm/hal/fmn.c (rev 0)
+++ trunk/sys/mips/nlm/hal/fmn.c 2018-05-26 21:55:02 UTC (rev 9987)
@@ -0,0 +1,355 @@
+/* $MidnightBSD$ */
+/*-
+ * Copyright 2003-2011 Netlogic Microsystems (Netlogic). All rights
+ * reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in
+ * the documentation and/or other materials provided with the
+ * distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY Netlogic Microsystems ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL NETLOGIC OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
+ * THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * NETLOGIC_BSD */
+
+#include <sys/cdefs.h>
+__FBSDID("$FreeBSD: stable/10/sys/mips/nlm/hal/fmn.c 245883 2013-01-24 15:23:01Z jchandra $");
+#include <sys/types.h>
+#include <sys/systm.h>
+
+#include <machine/cpufunc.h>
+#include <mips/nlm/hal/mips-extns.h>
+#include <mips/nlm/hal/haldefs.h>
+#include <mips/nlm/hal/iomap.h>
+#include <mips/nlm/hal/fmn.h>
+
+/* XLP can take upto 16K of FMN messages per hardware queue, as spill.
+* But, configuring all 16K causes the total spill memory to required
+* to blow upto 192MB for single chip configuration, and 768MB in four
+* chip configuration. Hence for now, we will setup the per queue spill
+* as 1K FMN messages. With this, the total spill memory needed for 1024
+* hardware queues (with 12bytes per single entry FMN message) becomes
+* (1*1024)*12*1024queues = 12MB. For the four chip config, the memory
+* needed = 12 * 4 = 48MB.
+*/
+uint64_t nlm_cms_spill_total_messages = 1 * 1024;
+
+/* On a XLP832, we have the following FMN stations:
+* CPU stations: 8
+* PCIE0 stations: 1
+* PCIE1 stations: 1
+* PCIE2 stations: 1
+* PCIE3 stations: 1
+* GDX stations: 1
+* CRYPTO stations: 1
+* RSA stations: 1
+* CMP stations: 1
+* POE stations: 1
+* NAE stations: 1
+* ==================
+* Total : 18 stations per chip
+*
+* For all 4 nodes, there are 18*4 = 72 FMN stations
+*/
+uint32_t nlm_cms_total_stations = 18 * 4 /*xlp_num_nodes*/;
+
+/**
+ * Takes inputs as node, queue_size and maximum number of queues.
+ * Calculates the base, start & end and returns the same for a
+ * defined qid.
+ *
+ * The output queues are maintained in the internal output buffer
+ * which is a on-chip SRAM structure. For the actial hardware
+ * internal implementation, It is a structure which consists
+ * of eight banks of 4096-entry x message-width SRAMs. The SRAM
+ * implementation is designed to run at 1GHz with a 1-cycle read/write
+ * access. A read/write transaction can be initiated for each bank
+ * every cycle for a total of eight accesses per cycle. Successive
+ * entries of the same output queue are placed in successive banks.
+ * This is done to spread different read & write accesses to same/different
+ * output queue over as many different banks as possible so that they
+ * can be scheduled concurrently. Spreading the accesses to as many banks
+ * as possible to maximize the concurrency internally is important for
+ * achieving the desired peak throughput. This is done by h/w implementation
+ * itself.
+ *
+ * Output queues are allocated from this internal output buffer by
+ * software. The total capacity of the output buffer is 32K-entry.
+ * Each output queue can be sized from 32-entry to 1024-entry in
+ * increments of 32-entry. This is done by specifying a Start & a
+ * End pointer: pointers to the first & last 32-entry chunks allocated
+ * to the output queue.
+ *
+ * To optimize the storage required for 1024 OQ pointers, the upper 5-bits
+ * are shared by the Start & the End pointer. The side-effect of this
+ * optimization is that an OQ can't cross a 1024-entry boundary. Also, the
+ * lower 5-bits don't need to be specified in the Start & the End pointer
+ * as the allocation is in increments of 32-entries.
+ *
+ * Queue occupancy is tracked by a Head & a Tail pointer. Tail pointer
+ * indicates the location to which next entry will be written & Head
+ * pointer indicates the location from which next entry will be read. When
+ * these pointers reach the top of the allocated space (indicated by the
+ * End pointer), they are reset to the bottom of the allocated space
+ * (indicated by the Start pointer).
+ *
+ * Output queue pointer information:
+ * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+ *
+ * 14 10 9 5 4 0
+ * ------------------
+ * | base ptr |
+ * ------------------
+ * ----------------
+ * | start ptr |
+ * ----------------
+ * ----------------
+ * | end ptr |
+ * ----------------
+ * ------------------------------------
+ * | head ptr |
+ * ------------------------------------
+ * ------------------------------------
+ * | tail ptr |
+ * ------------------------------------
+ * Note:
+ * A total of 1024 segments can sit on one software-visible "bank"
+ * of internal SRAM. Each segment contains 32 entries. Also note
+ * that sw-visible "banks" are not the same as the actual internal
+ * 8-bank implementation of hardware. It is an optimization of
+ * internal access.
+ *
+ */
+
+void nlm_cms_setup_credits(uint64_t base, int destid, int srcid, int credit)
+{
+ uint64_t val;
+
+ val = (((uint64_t)credit << 24) | (destid << 12) | (srcid << 0));
+ nlm_write_cms_reg(base, CMS_OUTPUTQ_CREDIT_CFG, val);
+
+}
+
+/*
+ * base - CMS module base address for this node.
+ * qid - is the output queue id otherwise called as vc id
+ * spill_base - is the 40-bit physical address of spill memory. Must be
+ 4KB aligned.
+ * nsegs - No of segments where a "1" indicates 4KB. Spill size must be
+ * a multiple of 4KB.
+ */
+int nlm_cms_alloc_spill_q(uint64_t base, int qid, uint64_t spill_base,
+ int nsegs)
+{
+ uint64_t queue_config;
+ uint32_t spill_start;
+
+ if (nsegs > CMS_MAX_SPILL_SEGMENTS_PER_QUEUE) {
+ return 1;
+ }
+
+ queue_config = nlm_read_cms_reg(base,(CMS_OUTPUTQ_CONFIG(qid)));
+
+ spill_start = ((spill_base >> 12) & 0x3F);
+ /* Spill configuration */
+ queue_config = (((uint64_t)CMS_SPILL_ENA << 62) |
+ (((spill_base >> 18) & 0x3FFFFF) << 27) |
+ (spill_start + nsegs - 1) << 21 |
+ (spill_start << 15));
+
+ nlm_write_cms_reg(base,(CMS_OUTPUTQ_CONFIG(qid)),queue_config);
+
+ return 0;
+}
+
+uint64_t nlm_cms_get_onchip_queue (uint64_t base, int qid)
+{
+ return nlm_read_cms_reg(base, CMS_OUTPUTQ_CONFIG(qid));
+}
+
+void nlm_cms_set_onchip_queue (uint64_t base, int qid, uint64_t val)
+{
+ uint64_t rdval;
+
+ rdval = nlm_read_cms_reg(base, CMS_OUTPUTQ_CONFIG(qid));
+ rdval |= val;
+ nlm_write_cms_reg(base, CMS_OUTPUTQ_CONFIG(qid), rdval);
+}
+
+void nlm_cms_per_queue_level_intr(uint64_t base, int qid, int sub_type,
+ int intr_val)
+{
+ uint64_t val;
+
+ val = nlm_read_cms_reg(base, CMS_OUTPUTQ_CONFIG(qid));
+
+ val &= ~((0x7ULL << 56) | (0x3ULL << 54));
+
+ val |= (((uint64_t)sub_type<<54) |
+ ((uint64_t)intr_val<<56));
+
+ nlm_write_cms_reg(base, CMS_OUTPUTQ_CONFIG(qid), val);
+}
+
+void nlm_cms_per_queue_timer_intr(uint64_t base, int qid, int sub_type,
+ int intr_val)
+{
+ uint64_t val;
+
+ val = nlm_read_cms_reg(base, CMS_OUTPUTQ_CONFIG(qid));
+
+ val &= ~((0x7ULL << 51) | (0x3ULL << 49));
+
+ val |= (((uint64_t)sub_type<<49) |
+ ((uint64_t)intr_val<<51));
+
+ nlm_write_cms_reg(base, CMS_OUTPUTQ_CONFIG(qid), val);
+}
+
+/* returns 1 if interrupt has been generated for this output queue */
+int nlm_cms_outputq_intr_check(uint64_t base, int qid)
+{
+ uint64_t val;
+ val = nlm_read_cms_reg(base, CMS_OUTPUTQ_CONFIG(qid));
+
+ return ((val >> 59) & 0x1);
+}
+
+void nlm_cms_outputq_clr_intr(uint64_t base, int qid)
+{
+ uint64_t val;
+ val = nlm_read_cms_reg(base, CMS_OUTPUTQ_CONFIG(qid));
+ val |= (1ULL<<59);
+ nlm_write_cms_reg(base, CMS_OUTPUTQ_CONFIG(qid), val);
+}
+
+void nlm_cms_illegal_dst_error_intr(uint64_t base, int en)
+{
+ uint64_t val;
+
+ val = nlm_read_cms_reg(base, CMS_MSG_CONFIG);
+ val |= (en<<8);
+ nlm_write_cms_reg(base, CMS_MSG_CONFIG, val);
+}
+
+void nlm_cms_timeout_error_intr(uint64_t base, int en)
+{
+ uint64_t val;
+
+ val = nlm_read_cms_reg(base, CMS_MSG_CONFIG);
+ val |= (en<<7);
+ nlm_write_cms_reg(base, CMS_MSG_CONFIG, val);
+}
+
+void nlm_cms_biu_error_resp_intr(uint64_t base, int en)
+{
+ uint64_t val;
+
+ val = nlm_read_cms_reg(base, CMS_MSG_CONFIG);
+ val |= (en<<6);
+ nlm_write_cms_reg(base, CMS_MSG_CONFIG, val);
+}
+
+void nlm_cms_spill_uncorrectable_ecc_error_intr(uint64_t base, int en)
+{
+ uint64_t val;
+
+ val = nlm_read_cms_reg(base, CMS_MSG_CONFIG);
+ val |= (en<<5) | (en<<3);
+ nlm_write_cms_reg(base, CMS_MSG_CONFIG, val);
+}
+
+void nlm_cms_spill_correctable_ecc_error_intr(uint64_t base, int en)
+{
+ uint64_t val;
+
+ val = nlm_read_cms_reg(base, CMS_MSG_CONFIG);
+ val |= (en<<4) | (en<<2);
+ nlm_write_cms_reg(base, CMS_MSG_CONFIG, val);
+}
+
+void nlm_cms_outputq_uncorrectable_ecc_error_intr(uint64_t base, int en)
+{
+ uint64_t val;
+
+ val = nlm_read_cms_reg(base, CMS_MSG_CONFIG);
+ val |= (en<<1);
+ nlm_write_cms_reg(base, CMS_MSG_CONFIG, val);
+}
+
+void nlm_cms_outputq_correctable_ecc_error_intr(uint64_t base, int en)
+{
+ uint64_t val;
+
+ val = nlm_read_cms_reg(base, CMS_MSG_CONFIG);
+ val |= (en<<0);
+ nlm_write_cms_reg(base, CMS_MSG_CONFIG, val);
+}
+
+uint64_t nlm_cms_network_error_status(uint64_t base)
+{
+ return nlm_read_cms_reg(base, CMS_MSG_ERR);
+}
+
+int nlm_cms_get_net_error_code(uint64_t err)
+{
+ return ((err >> 12) & 0xf);
+}
+
+int nlm_cms_get_net_error_syndrome(uint64_t err)
+{
+ return ((err >> 32) & 0x1ff);
+}
+
+int nlm_cms_get_net_error_ramindex(uint64_t err)
+{
+ return ((err >> 44) & 0x7fff);
+}
+
+int nlm_cms_get_net_error_outputq(uint64_t err)
+{
+ return ((err >> 16) & 0xfff);
+}
+
+/*========================= FMN Tracing related APIs ================*/
+
+void nlm_cms_trace_setup(uint64_t base, int en, uint64_t trace_base,
+ uint64_t trace_limit, int match_dstid_en,
+ int dst_id, int match_srcid_en, int src_id,
+ int wrap)
+{
+ uint64_t val;
+
+ nlm_write_cms_reg(base, CMS_TRACE_BASE_ADDR, trace_base);
+ nlm_write_cms_reg(base, CMS_TRACE_LIMIT_ADDR, trace_limit);
+
+ val = nlm_read_cms_reg(base, CMS_TRACE_CONFIG);
+ val |= (((uint64_t)match_dstid_en << 39) |
+ ((dst_id & 0xfff) << 24) |
+ (match_srcid_en << 23) |
+ ((src_id & 0xfff) << 8) |
+ (wrap << 1) |
+ (en << 0));
+ nlm_write_cms_reg(base, CMS_MSG_CONFIG, val);
+}
+
+void nlm_cms_endian_byte_swap (uint64_t base, int en)
+{
+ nlm_write_cms_reg(base, CMS_MSG_ENDIAN_SWAP, en);
+}
Property changes on: trunk/sys/mips/nlm/hal/fmn.c
___________________________________________________________________
Added: svn:eol-style
## -0,0 +1 ##
+native
\ No newline at end of property
Added: svn:keywords
## -0,0 +1 ##
+MidnightBSD=%H
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+text/plain
\ No newline at end of property
Added: trunk/sys/mips/nlm/hal/fmn.h
===================================================================
--- trunk/sys/mips/nlm/hal/fmn.h (rev 0)
+++ trunk/sys/mips/nlm/hal/fmn.h 2018-05-26 21:55:02 UTC (rev 9987)
@@ -0,0 +1,246 @@
+/* $MidnightBSD$ */
+/*-
+ * Copyright 2003-2011 Netlogic Microsystems (Netlogic). All rights
+ * reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in
+ * the documentation and/or other materials provided with the
+ * distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY Netlogic Microsystems ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL NETLOGIC OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
+ * THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * NETLOGIC_BSD
+ * $FreeBSD: stable/10/sys/mips/nlm/hal/fmn.h 227783 2011-11-21 08:12:36Z jchandra $
+ */
+
+#ifndef __NLM_FMNV2_H__
+#define __NLM_FMNV2_H__
+
+/**
+* @file_name fmn.h
+* @author Netlogic Microsystems
+* @brief HAL for Fast message network V2
+*/
+
+/* FMN configuration registers */
+#define CMS_OUTPUTQ_CONFIG(i) ((i)*2)
+#define CMS_MAX_OUTPUTQ 1024
+#define CMS_OUTPUTQ_CREDIT_CFG (0x2000/4)
+#define CMS_MSG_CONFIG (0x2008/4)
+#define CMS_MSG_ERR (0x2010/4)
+#define CMS_TRACE_CONFIG (0x2018/4)
+#define CMS_TRACE_BASE_ADDR (0x2020/4)
+#define CMS_TRACE_LIMIT_ADDR (0x2028/4)
+#define CMS_TRACE_CURRENT_ADDR (0x2030/4)
+#define CMS_MSG_ENDIAN_SWAP (0x2038/4)
+
+#define CMS_CPU_PUSHQ(node, core, thread, vc) \
+ (((node)<<10) | ((core)<<4) | ((thread)<<2) | ((vc)<<0))
+#define CMS_POPQ(node, queue) (((node)<<10) | (queue))
+#define CMS_IO_PUSHQ(node, queue) (((node)<<10) | (queue))
+
+#define CMS_POPQ_QID(i) (128+(i))
+
+/* FMN Level Interrupt Type */
+#define CMS_LVL_INTR_DISABLE 0
+#define CMS_LVL_LOW_WATERMARK 1
+#define CMS_LVL_HI_WATERMARK 2
+
+/* FMN Level interrupt trigger values */
+#define CMS_QUEUE_NON_EMPTY 0
+#define CMS_QUEUE_QUARTER_FULL 1
+#define CMS_QUEUE_HALF_FULL 2
+#define CMS_QUEUE_THREE_QUARTER_FULL 3
+#define CMS_QUEUE_FULL 4
+
+/* FMN Timer Interrupt Type */
+#define CMS_TIMER_INTR_DISABLE 0
+#define CMS_TIMER_CONSUMER 1
+#define CMS_TIMER_PRODUCER 1
+
+/* FMN timer interrupt trigger values */
+#define CMS_TWO_POW_EIGHT_CYCLES 0
+#define CMS_TWO_POW_TEN_CYCLES 1
+#define CMS_TWO_POW_TWELVE_CYCLES 2
+#define CMS_TWO_POW_FOURTEEN_CYCLES 3
+#define CMS_TWO_POW_SIXTEEN_CYCLES 4
+#define CMS_TWO_POW_EIGHTTEEN_CYCLES 5
+#define CMS_TWO_POW_TWENTY_CYCLES 6
+#define CMS_TWO_POW_TWENTYTWO_CYCLES 7
+
+#define CMS_QUEUE_ENA 1ULL
+#define CMS_QUEUE_DIS 0
+#define CMS_SPILL_ENA 1ULL
+#define CMS_SPILL_DIS 0
+
+#define CMS_MAX_VCPU_VC 4
+
+/* Each XLP chip can hold upto 32K messages on the chip itself */
+#define CMS_ON_CHIP_MESG_SPACE (32*1024)
+#define CMS_MAX_ONCHIP_SEGMENTS 1024
+#define CMS_MAX_SPILL_SEGMENTS_PER_QUEUE 64
+
+/* FMN Network error */
+#define CMS_ILLEGAL_DST_ERROR 0x100
+#define CMS_BIU_TIMEOUT_ERROR 0x080
+#define CMS_BIU_ERROR 0x040
+#define CMS_SPILL_FILL_UNCORRECT_ECC_ERROR 0x020
+#define CMS_SPILL_FILL_CORRECT_ECC_ERROR 0x010
+#define CMS_SPILL_UNCORRECT_ECC_ERROR 0x008
+#define CMS_SPILL_CORRECT_ECC_ERROR 0x004
+#define CMS_OUTPUTQ_UNCORRECT_ECC_ERROR 0x002
+#define CMS_OUTPUTQ_CORRECT_ECC_ERROR 0x001
+
+/* worst case, a single entry message consists of a 4 byte header
+ * and an 8-byte entry = 12 bytes in total
+ */
+#define CMS_SINGLE_ENTRY_MSG_SIZE 12
+/* total spill memory needed for one FMN queue */
+#define CMS_PER_QUEUE_SPILL_MEM(spilltotmsgs) \
+ ((spilltotmsgs) * (CMS_SINGLE_ENTRY_MSG_SIZE))
+
+/* FMN Src station id's */
+#define CMS_CPU0_SRC_STID (0 << 4)
+#define CMS_CPU1_SRC_STID (1 << 4)
+#define CMS_CPU2_SRC_STID (2 << 4)
+#define CMS_CPU3_SRC_STID (3 << 4)
+#define CMS_CPU4_SRC_STID (4 << 4)
+#define CMS_CPU5_SRC_STID (5 << 4)
+#define CMS_CPU6_SRC_STID (6 << 4)
+#define CMS_CPU7_SRC_STID (7 << 4)
+#define CMS_PCIE0_SRC_STID 256
+#define CMS_PCIE1_SRC_STID 258
+#define CMS_PCIE2_SRC_STID 260
+#define CMS_PCIE3_SRC_STID 262
+#define CMS_DTE_SRC_STID 264
+#define CMS_RSA_ECC_SRC_STID 272
+#define CMS_CRYPTO_SRC_STID 281
+#define CMS_CMP_SRC_STID 298
+#define CMS_POE_SRC_STID 384
+#define CMS_NAE_SRC_STID 476
+
+/* POPQ related defines */
+#define CMS_POPQID_START 128
+#define CMS_POPQID_END 255
+
+#define CMS_INT_RCVD 0x800000000000000ULL
+
+#define nlm_read_cms_reg(b, r) nlm_read_reg64_xkphys(b,r)
+#define nlm_write_cms_reg(b, r, v) nlm_write_reg64_xkphys(b,r,v)
+#define nlm_get_cms_pcibase(node) \
+ nlm_pcicfg_base(XLP_IO_CMS_OFFSET(node))
+#define nlm_get_cms_regbase(node) \
+ nlm_xkphys_map_pcibar0(nlm_get_cms_pcibase(node))
+
+#define XLP_CMS_ON_CHIP_PER_QUEUE_SPACE(node) \
+ ((XLP_CMS_ON_CHIP_MESG_SPACE)/ \
+ (nlm_read_reg(nlm_pcibase_cms(node), \
+ XLP_PCI_DEVINFO_REG0))
+/* total spill memory needed */
+#define XLP_CMS_TOTAL_SPILL_MEM(node, spilltotmsgs) \
+ ((XLP_CMS_PER_QUEUE_SPILL_MEM(spilltotmsgs)) * \
+ (nlm_read_reg(nlm_pcibase_cms(node), \
+ XLP_PCI_DEVINFO_REG0))
+#define CMS_TOTAL_QUEUE_SIZE(node, spilltotmsgs) \
+ ((spilltotmsgs) + (CMS_ON_CHIP_PER_QUEUE_SPACE(node)))
+
+enum fmn_swcode {
+ FMN_SWCODE_CPU0=1,
+ FMN_SWCODE_CPU1,
+ FMN_SWCODE_CPU2,
+ FMN_SWCODE_CPU3,
+ FMN_SWCODE_CPU4,
+ FMN_SWCODE_CPU5,
+ FMN_SWCODE_CPU6,
+ FMN_SWCODE_CPU7,
+ FMN_SWCODE_CPU8,
+ FMN_SWCODE_CPU9,
+ FMN_SWCODE_CPU10,
+ FMN_SWCODE_CPU11,
+ FMN_SWCODE_CPU12,
+ FMN_SWCODE_CPU13,
+ FMN_SWCODE_CPU14,
+ FMN_SWCODE_CPU15,
+ FMN_SWCODE_CPU16,
+ FMN_SWCODE_CPU17,
+ FMN_SWCODE_CPU18,
+ FMN_SWCODE_CPU19,
+ FMN_SWCODE_CPU20,
+ FMN_SWCODE_CPU21,
+ FMN_SWCODE_CPU22,
+ FMN_SWCODE_CPU23,
+ FMN_SWCODE_CPU24,
+ FMN_SWCODE_CPU25,
+ FMN_SWCODE_CPU26,
+ FMN_SWCODE_CPU27,
+ FMN_SWCODE_CPU28,
+ FMN_SWCODE_CPU29,
+ FMN_SWCODE_CPU30,
+ FMN_SWCODE_CPU31,
+ FMN_SWCODE_CPU32,
+ FMN_SWCODE_PCIE0,
+ FMN_SWCODE_PCIE1,
+ FMN_SWCODE_PCIE2,
+ FMN_SWCODE_PCIE3,
+ FMN_SWCODE_DTE,
+ FMN_SWCODE_CRYPTO,
+ FMN_SWCODE_RSA,
+ FMN_SWCODE_CMP,
+ FMN_SWCODE_POE,
+ FMN_SWCODE_NAE,
+};
+
+extern uint64_t nlm_cms_spill_total_messages;
+extern uint32_t nlm_cms_total_stations;
+
+extern uint64_t cms_base_addr(int node);
+extern int nlm_cms_verify_credit_config (int spill_en, int tot_credit);
+extern int nlm_cms_get_oc_space(int qsize, int max_queues, int qid, int *ocbase, int *ocstart, int *ocend);
+extern void nlm_cms_setup_credits (uint64_t base, int destid, int srcid, int credit);
+extern int nlm_cms_config_onchip_queue (uint64_t base, uint64_t cms_spill_base, int qid, int spill_en);
+extern void nlm_cms_default_setup(int node, uint64_t spill_base, int spill_en, int popq_en);
+extern uint64_t nlm_cms_get_onchip_queue (uint64_t base, int qid);
+extern void nlm_cms_set_onchip_queue (uint64_t base, int qid, uint64_t val);
+extern void nlm_cms_per_queue_level_intr(uint64_t base, int qid, int sub_type, int intr_val);
+extern void nlm_cms_level_intr(int node, int sub_type, int intr_val);
+extern void nlm_cms_per_queue_timer_intr(uint64_t base, int qid, int sub_type, int intr_val);
+extern void nlm_cms_timer_intr(int node, int en, int sub_type, int intr_val);
+extern int nlm_cms_outputq_intr_check(uint64_t base, int qid);
+extern void nlm_cms_outputq_clr_intr(uint64_t base, int qid);
+extern void nlm_cms_illegal_dst_error_intr(uint64_t base, int en);
+extern void nlm_cms_timeout_error_intr(uint64_t base, int en);
+extern void nlm_cms_biu_error_resp_intr(uint64_t base, int en);
+extern void nlm_cms_spill_uncorrectable_ecc_error_intr(uint64_t base, int en);
+extern void nlm_cms_spill_correctable_ecc_error_intr(uint64_t base, int en);
+extern void nlm_cms_outputq_uncorrectable_ecc_error_intr(uint64_t base, int en);
+extern void nlm_cms_outputq_correctable_ecc_error_intr(uint64_t base, int en);
+extern uint64_t nlm_cms_network_error_status(uint64_t base);
+extern int nlm_cms_get_net_error_code(uint64_t err);
+extern int nlm_cms_get_net_error_syndrome(uint64_t err);
+extern int nlm_cms_get_net_error_ramindex(uint64_t err);
+extern int nlm_cms_get_net_error_outputq(uint64_t err);
+extern void nlm_cms_trace_setup(uint64_t base, int en, uint64_t trace_base, uint64_t trace_limit, int match_dstid_en, int dst_id, int match_srcid_en, int src_id, int wrap);
+extern void nlm_cms_endian_byte_swap (uint64_t base, int en);
+extern uint8_t xlp_msg_send(uint8_t vc, uint8_t size);
+extern int nlm_cms_alloc_spill_q(uint64_t base, int qid, uint64_t spill_base,
+ int nsegs);
+extern int nlm_cms_alloc_onchip_q(uint64_t base, int qid, int nsegs);
+
+#endif
Property changes on: trunk/sys/mips/nlm/hal/fmn.h
___________________________________________________________________
Added: svn:eol-style
## -0,0 +1 ##
+native
\ No newline at end of property
Added: svn:keywords
## -0,0 +1 ##
+MidnightBSD=%H
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+text/plain
\ No newline at end of property
Added: trunk/sys/mips/nlm/hal/gbu.h
===================================================================
--- trunk/sys/mips/nlm/hal/gbu.h (rev 0)
+++ trunk/sys/mips/nlm/hal/gbu.h 2018-05-26 21:55:02 UTC (rev 9987)
@@ -0,0 +1,101 @@
+/* $MidnightBSD$ */
+/*-
+ * Copyright (c) 2003-2012 Broadcom Corporation
+ * All Rights Reserved
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in
+ * the documentation and/or other materials provided with the
+ * distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY BROADCOM ``AS IS'' AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL BROADCOM OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
+ * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
+ * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
+ * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * $FreeBSD: stable/10/sys/mips/nlm/hal/gbu.h 233542 2012-03-27 12:25:47Z jchandra $
+ */
+#ifndef _NLM_HAL_GBU_H__
+#define _NLM_HAL_GBU_H__
+
+/* Global Bus Unit (GBU) for flash Specific registers */
+
+#define GBU_CS_BASEADDR(cs) (0x0+cs)
+#define GBU_CS0_BASEADDR 0x0
+#define GBU_CS1_BASEADDR 0x1
+#define GBU_CS2_BASEADDR 0x2
+#define GBU_CS3_BASEADDR 0x3
+#define GBU_CS4_BASEADDR 0x4
+#define GBU_CS5_BASEADDR 0x5
+#define GBU_CS6_BASEADDR 0x6
+#define GBU_CS7_BASEADDR 0x7
+#define GBU_CS_BASELIMIT(cs) (0x8+cs)
+#define GBU_CS0_BASELIMIT 0x8
+#define GBU_CS1_BASELIMIT 0x9
+#define GBU_CS2_BASELIMIT 0xa
+#define GBU_CS3_BASELIMIT 0xb
+#define GBU_CS4_BASELIMIT 0xc
+#define GBU_CS5_BASELIMIT 0xd
+#define GBU_CS6_BASELIMIT 0xe
+#define GBU_CS7_BASELIMIT 0xf
+#define GBU_CS_DEVPARAM(cs) (0x10+cs)
+#define GBU_CS0_DEVPARAM 0x10
+#define GBU_CS1_DEVPARAM 0x11
+#define GBU_CS2_DEVPARAM 0x12
+#define GBU_CS3_DEVPARAM 0x13
+#define GBU_CS4_DEVPARAM 0x14
+#define GBU_CS5_DEVPARAM 0x15
+#define GBU_CS6_DEVPARAM 0x16
+#define GBU_CS7_DEVPARAM 0x17
+#define GBU_CS_DEVTIME0(cs) (0x18+cs)
+#define GBU_CS0_DEVTIME0 0x18
+#define GBU_CS1_DEVTIME0 0x1a
+#define GBU_CS2_DEVTIME0 0x1c
+#define GBU_CS3_DEVTIME0 0x1e
+#define GBU_CS4_DEVTIME0 0x20
+#define GBU_CS5_DEVTIME0 0x22
+#define GBU_CS6_DEVTIME0 0x24
+#define GBU_CS7_DEVTIME0 0x26
+#define GBU_CS_DEVTIME1(cs) (0x19+cs)
+#define GBU_CS0_DEVTIME1 0x19
+#define GBU_CS1_DEVTIME1 0x1b
+#define GBU_CS2_DEVTIME1 0x1d
+#define GBU_CS3_DEVTIME1 0x1f
+#define GBU_CS4_DEVTIME1 0x21
+#define GBU_CS5_DEVTIME1 0x23
+#define GBU_CS6_DEVTIME1 0x25
+#define GBU_CS7_DEVTIME1 0x27
+#define GBU_SYSCTRL 0x28
+#define GBU_BYTESWAP 0x29
+#define GBU_DI_TIMEOUT_VAL 0x2d
+#define GBU_INTSTAT 0x2e
+#define GBU_INTEN 0x2f
+#define GBU_STATUS 0x30
+#define GBU_ERRLOG0 0x2a
+#define GBU_ERRLOG1 0x2b
+#define GBU_ERRLOG2 0x2c
+
+#if !defined(LOCORE) && !defined(__ASSEMBLY__)
+
+#define nlm_read_gbu_reg(b, r) nlm_read_reg(b, r)
+#define nlm_write_gbu_reg(b, r, v) nlm_write_reg(b, r, v)
+#define nlm_get_gbu_pcibase(node) \
+ nlm_pcicfg_base(XLP_IO_NOR_OFFSET(node))
+#define nlm_get_gbu_regbase(node) \
+ (nlm_get_gbu_pcibase(node) + XLP_IO_PCI_HDRSZ)
+
+#endif /* !LOCORE && !__ASSEMBLY__ */
+#endif /* _NLM_HAL_GBU_H__ */
Property changes on: trunk/sys/mips/nlm/hal/gbu.h
___________________________________________________________________
Added: svn:eol-style
## -0,0 +1 ##
+native
\ No newline at end of property
Added: svn:keywords
## -0,0 +1 ##
+MidnightBSD=%H
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+text/plain
\ No newline at end of property
Added: trunk/sys/mips/nlm/hal/haldefs.h
===================================================================
--- trunk/sys/mips/nlm/hal/haldefs.h (rev 0)
+++ trunk/sys/mips/nlm/hal/haldefs.h 2018-05-26 21:55:02 UTC (rev 9987)
@@ -0,0 +1,438 @@
+/* $MidnightBSD$ */
+/*-
+ * Copyright 2003-2011 Netlogic Microsystems (Netlogic). All rights
+ * reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in
+ * the documentation and/or other materials provided with the
+ * distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY Netlogic Microsystems ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL NETLOGIC OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
+ * THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * NETLOGIC_BSD
+ * $FreeBSD: stable/10/sys/mips/nlm/hal/haldefs.h 227722 2011-11-19 14:06:15Z jchandra $
+ */
+
+#ifndef __NLM_HAL_MMIO_H__
+#define __NLM_HAL_MMIO_H__
+
+/*
+ * This file contains platform specific memory mapped IO implementation
+ * and will provide a way to read 32/64 bit memory mapped registers in
+ * all ABIs
+ */
+
+/*
+ * For o32 compilation, we have to disable interrupts and enable KX bit to
+ * access 64 bit addresses or data.
+ *
+ * We need to disable interrupts because we save just the lower 32 bits of
+ * registers in interrupt handling. So if we get hit by an interrupt while
+ * using the upper 32 bits of a register, we lose.
+ */
+static inline uint32_t nlm_save_flags_kx(void)
+{
+ uint32_t sr = mips_rd_status();
+
+ mips_wr_status((sr & ~MIPS_SR_INT_IE) | MIPS_SR_KX);
+ return (sr);
+}
+
+static inline uint32_t nlm_save_flags_cop2(void)
+{
+ uint32_t sr = mips_rd_status();
+
+ mips_wr_status((sr & ~MIPS_SR_INT_IE) | MIPS_SR_COP_2_BIT);
+ return (sr);
+}
+
+static inline void nlm_restore_flags(uint32_t sr)
+{
+ mips_wr_status(sr);
+}
+
+static inline uint32_t
+nlm_load_word(uint64_t addr)
+{
+ volatile uint32_t *p = (volatile uint32_t *)(long)addr;
+
+ return *p;
+}
+
+static inline void
+nlm_store_word(uint64_t addr, uint32_t val)
+{
+ volatile uint32_t *p = (volatile uint32_t *)(long)addr;
+
+ *p = val;
+}
+
+#if defined(__mips_n64) || defined(__mips_n32)
+static inline uint64_t
+nlm_load_dword(volatile uint64_t addr)
+{
+ volatile uint64_t *p = (volatile uint64_t *)(long)addr;
+
+ return *p;
+}
+
+static inline void
+nlm_store_dword(volatile uint64_t addr, uint64_t val)
+{
+ volatile uint64_t *p = (volatile uint64_t *)(long)addr;
+
+ *p = val;
+}
+
+#else /* o32 */
+static inline uint64_t
+nlm_load_dword(uint64_t addr)
+{
+ volatile uint64_t *p = (volatile uint64_t *)(long)addr;
+ uint32_t valhi, vallo, sr;
+
+ sr = nlm_save_flags_kx();
+ __asm__ __volatile__(
+ ".set push\n\t"
+ ".set mips64\n\t"
+ "ld $8, 0(%2)\n\t"
+ "dsra32 %0, $8, 0\n\t"
+ "sll %1, $8, 0\n\t"
+ ".set pop\n"
+ : "=r"(valhi), "=r"(vallo)
+ : "r"(p)
+ : "$8");
+ nlm_restore_flags(sr);
+
+ return ((uint64_t)valhi << 32) | vallo;
+}
+
+static inline void
+nlm_store_dword(uint64_t addr, uint64_t val)
+{
+ volatile uint64_t *p = (volatile uint64_t *)(long)addr;
+ uint32_t valhi, vallo, sr;
+
+ valhi = val >> 32;
+ vallo = val & 0xffffffff;
+
+ sr = nlm_save_flags_kx();
+ __asm__ __volatile__(
+ ".set push\n\t"
+ ".set mips64\n\t"
+ "dsll32 $8, %1, 0\n\t"
+ "dsll32 $9, %2, 0\n\t" /* get rid of the */
+ "dsrl32 $9, $9, 0\n\t" /* sign extend */
+ "or $9, $9, $8\n\t"
+ "sd $9, 0(%0)\n\t"
+ ".set pop\n"
+ : : "r"(p), "r"(valhi), "r"(vallo)
+ : "$8", "$9", "memory");
+ nlm_restore_flags(sr);
+}
+#endif
+
+#if defined(__mips_n64)
+static inline uint64_t
+nlm_load_word_daddr(uint64_t addr)
+{
+ volatile uint32_t *p = (volatile uint32_t *)(long)addr;
+
+ return *p;
+}
+
+static inline void
+nlm_store_word_daddr(uint64_t addr, uint32_t val)
+{
+ volatile uint32_t *p = (volatile uint32_t *)(long)addr;
+
+ *p = val;
+}
+
+static inline uint64_t
+nlm_load_dword_daddr(uint64_t addr)
+{
+ volatile uint64_t *p = (volatile uint64_t *)(long)addr;
+
+ return *p;
+}
+
+static inline void
+nlm_store_dword_daddr(uint64_t addr, uint64_t val)
+{
+ volatile uint64_t *p = (volatile uint64_t *)(long)addr;
+
+ *p = val;
+}
+
+#elif defined(__mips_n32)
+
+static inline uint64_t
+nlm_load_word_daddr(uint64_t addr)
+{
+ uint32_t val;
+
+ __asm__ __volatile__(
+ ".set push\n\t"
+ ".set mips64\n\t"
+ "lw %0, 0(%1)\n\t"
+ ".set pop\n"
+ : "=r"(val)
+ : "r"(addr));
+
+ return val;
+}
+
+static inline void
+nlm_store_word_daddr(uint64_t addr, uint32_t val)
+{
+ __asm__ __volatile__(
+ ".set push\n\t"
+ ".set mips64\n\t"
+ "sw %0, 0(%1)\n\t"
+ ".set pop\n"
+ : : "r"(val), "r"(addr)
+ : "memory");
+}
+
+static inline uint64_t
+nlm_load_dword_daddr(uint64_t addr)
+{
+ uint64_t val;
+
+ __asm__ __volatile__(
+ ".set push\n\t"
+ ".set mips64\n\t"
+ "ld %0, 0(%1)\n\t"
+ ".set pop\n"
+ : "=r"(val)
+ : "r"(addr));
+ return val;
+}
+
+static inline void
+nlm_store_dword_daddr(uint64_t addr, uint64_t val)
+{
+ __asm__ __volatile__(
+ ".set push\n\t"
+ ".set mips64\n\t"
+ "sd %0, 0(%1)\n\t"
+ ".set pop\n"
+ : : "r"(val), "r"(addr)
+ : "memory");
+}
+
+#else /* o32 */
+static inline uint64_t
+nlm_load_word_daddr(uint64_t addr)
+{
+ uint32_t val, addrhi, addrlo, sr;
+
+ addrhi = addr >> 32;
+ addrlo = addr & 0xffffffff;
+
+ sr = nlm_save_flags_kx();
+ __asm__ __volatile__(
+ ".set push\n\t"
+ ".set mips64\n\t"
+ "dsll32 $8, %1, 0\n\t"
+ "dsll32 $9, %2, 0\n\t"
+ "dsrl32 $9, $9, 0\n\t"
+ "or $9, $9, $8\n\t"
+ "lw %0, 0($9)\n\t"
+ ".set pop\n"
+ : "=r"(val)
+ : "r"(addrhi), "r"(addrlo)
+ : "$8", "$9");
+ nlm_restore_flags(sr);
+
+ return val;
+
+}
+
+static inline void
+nlm_store_word_daddr(uint64_t addr, uint32_t val)
+{
+ uint32_t addrhi, addrlo, sr;
+
+ addrhi = addr >> 32;
+ addrlo = addr & 0xffffffff;
+
+ sr = nlm_save_flags_kx();
+ __asm__ __volatile__(
+ ".set push\n\t"
+ ".set mips64\n\t"
+ "dsll32 $8, %1, 0\n\t"
+ "dsll32 $9, %2, 0\n\t"
+ "dsrl32 $9, $9, 0\n\t"
+ "or $9, $9, $8\n\t"
+ "sw %0, 0($9)\n\t"
+ ".set pop\n"
+ : : "r"(val), "r"(addrhi), "r"(addrlo)
+ : "$8", "$9", "memory");
+ nlm_restore_flags(sr);
+}
+
+static inline uint64_t
+nlm_load_dword_daddr(uint64_t addr)
+{
+ uint32_t addrh, addrl, sr;
+ uint32_t valh, vall;
+
+ addrh = addr >> 32;
+ addrl = addr & 0xffffffff;
+
+ sr = nlm_save_flags_kx();
+ __asm__ __volatile__(
+ ".set push\n\t"
+ ".set mips64\n\t"
+ "dsll32 $8, %2, 0\n\t"
+ "dsll32 $9, %3, 0\n\t"
+ "dsrl32 $9, $9, 0\n\t"
+ "or $9, $9, $8\n\t"
+ "ld $8, 0($9)\n\t"
+ "dsra32 %0, $8, 0\n\t"
+ "sll %1, $8, 0\n\t"
+ ".set pop\n"
+ : "=r"(valh), "=r"(vall)
+ : "r"(addrh), "r"(addrl)
+ : "$8", "$9");
+ nlm_restore_flags(sr);
+
+ return ((uint64_t)valh << 32) | vall;
+}
+
+static inline void
+nlm_store_dword_daddr(uint64_t addr, uint64_t val)
+{
+ uint32_t addrh, addrl, sr;
+ uint32_t valh, vall;
+
+ addrh = addr >> 32;
+ addrl = addr & 0xffffffff;
+ valh = val >> 32;
+ vall = val & 0xffffffff;
+
+ sr = nlm_save_flags_kx();
+ __asm__ __volatile__(
+ ".set push\n\t"
+ ".set mips64\n\t"
+ "dsll32 $8, %2, 0\n\t"
+ "dsll32 $9, %3, 0\n\t"
+ "dsrl32 $9, $9, 0\n\t"
+ "or $9, $9, $8\n\t"
+ "dsll32 $8, %0, 0\n\t"
+ "dsll32 $10, %1, 0\n\t"
+ "dsrl32 $10, $10, 0\n\t"
+ "or $8, $8, $10\n\t"
+ "sd $8, 0($9)\n\t"
+ ".set pop\n"
+ : : "r"(valh), "r"(vall), "r"(addrh), "r"(addrl)
+ : "$8", "$9", "memory");
+ nlm_restore_flags(sr);
+}
+#endif /* __mips_n64 */
+
+static inline uint32_t
+nlm_read_reg(uint64_t base, uint32_t reg)
+{
+ volatile uint32_t *addr = (volatile uint32_t *)(long)base + reg;
+
+ return *addr;
+}
+
+static inline void
+nlm_write_reg(uint64_t base, uint32_t reg, uint32_t val)
+{
+ volatile uint32_t *addr = (volatile uint32_t *)(long)base + reg;
+
+ *addr = val;
+}
+
+static inline uint64_t
+nlm_read_reg64(uint64_t base, uint32_t reg)
+{
+ uint64_t addr = base + (reg >> 1) * sizeof(uint64_t);
+
+ return nlm_load_dword(addr);
+}
+
+static inline void
+nlm_write_reg64(uint64_t base, uint32_t reg, uint64_t val)
+{
+ uint64_t addr = base + (reg >> 1) * sizeof(uint64_t);
+
+ return nlm_store_dword(addr, val);
+}
+
+/*
+ * Routines to store 32/64 bit values to 64 bit addresses,
+ * used when going thru XKPHYS to access registers
+ */
+static inline uint32_t
+nlm_read_reg_xkphys(uint64_t base, uint32_t reg)
+{
+ uint64_t addr = base + reg * sizeof(uint32_t);
+
+ return nlm_load_word_daddr(addr);
+}
+
+static inline void
+nlm_write_reg_xkphys(uint64_t base, uint32_t reg, uint32_t val)
+{
+ uint64_t addr = base + reg * sizeof(uint32_t);
+ return nlm_store_word_daddr(addr, val);
+}
+
+static inline uint64_t
+nlm_read_reg64_xkphys(uint64_t base, uint32_t reg)
+{
+ uint64_t addr = base + (reg >> 1) * sizeof(uint64_t);
+
+ return nlm_load_dword_daddr(addr);
+}
+
+static inline void
+nlm_write_reg64_xkphys(uint64_t base, uint32_t reg, uint64_t val)
+{
+ uint64_t addr = base + (reg >> 1) * sizeof(uint64_t);
+
+ return nlm_store_dword_daddr(addr, val);
+}
+
+/* Location where IO base is mapped */
+extern uint64_t xlp_io_base;
+
+static inline uint64_t
+nlm_pcicfg_base(uint32_t devoffset)
+{
+ return xlp_io_base + devoffset;
+}
+
+static inline uint64_t
+nlm_xkphys_map_pcibar0(uint64_t pcibase)
+{
+ uint64_t paddr;
+
+ paddr = nlm_read_reg(pcibase, 0x4) & ~0xfu;
+ return (uint64_t)0x9000000000000000 | paddr;
+}
+
+#endif
Property changes on: trunk/sys/mips/nlm/hal/haldefs.h
___________________________________________________________________
Added: svn:eol-style
## -0,0 +1 ##
+native
\ No newline at end of property
Added: svn:keywords
## -0,0 +1 ##
+MidnightBSD=%H
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+text/plain
\ No newline at end of property
Added: trunk/sys/mips/nlm/hal/interlaken.h
===================================================================
--- trunk/sys/mips/nlm/hal/interlaken.h (rev 0)
+++ trunk/sys/mips/nlm/hal/interlaken.h 2018-05-26 21:55:02 UTC (rev 9987)
@@ -0,0 +1,71 @@
+/* $MidnightBSD$ */
+/*-
+ * Copyright (c) 2003-2012 Broadcom Corporation
+ * All Rights Reserved
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in
+ * the documentation and/or other materials provided with the
+ * distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY BROADCOM ``AS IS'' AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL BROADCOM OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
+ * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
+ * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
+ * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * $FreeBSD: stable/10/sys/mips/nlm/hal/interlaken.h 233545 2012-03-27 14:05:12Z jchandra $
+ */
+#ifndef __NLM_ILAKEN_H__
+#define __NLM_ILAKEN_H__
+
+/**
+* @file_name interlaken.h
+* @author Netlogic Microsystems
+* @brief Basic definitions of XLP ILAKEN ports
+*/
+
+#define ILK_TX_CONTROL(block) NAE_REG(block, 5, 0x00)
+#define ILK_TX_RATE_LIMIT(block) NAE_REG(block, 5, 0x01)
+#define ILK_TX_META_CTRL(block) NAE_REG(block, 5, 0x02)
+#define ILK_RX_CTRL(block) NAE_REG(block, 5, 0x03)
+#define ILK_RX_STATUS1(block) NAE_REG(block, 5, 0x04)
+#define ILK_RX_STATUS2(block) NAE_REG(block, 5, 0x05)
+#define ILK_GENERAL_CTRL1(block) NAE_REG(block, 5, 0x06)
+#define ILK_STATUS3(block) NAE_REG(block, 5, 0x07)
+#define ILK_RX_FC_TMAP0(block) NAE_REG(block, 5, 0x08)
+#define ILK_RX_FC_TMAP1(block) NAE_REG(block, 5, 0x09)
+#define ILK_RX_FC_TMAP2(block) NAE_REG(block, 5, 0x0a)
+#define ILK_RX_FC_TMAP3(block) NAE_REG(block, 5, 0x0b)
+#define ILK_RX_FC_TMAP4(block) NAE_REG(block, 5, 0x0c)
+#define ILK_RX_FC_TADDR(block) NAE_REG(block, 5, 0x0d)
+#define ILK_GENERAL_CTRL2(block) NAE_REG(block, 5, 0x0e)
+#define ILK_GENERAL_CTRL3(block) NAE_REG(block, 5, 0x0f)
+#define ILK_SMALL_COUNT0(block) NAE_REG(block, 5, 0x10)
+#define ILK_SMALL_COUNT1(block) NAE_REG(block, 5, 0x11)
+#define ILK_SMALL_COUNT2(block) NAE_REG(block, 5, 0x12)
+#define ILK_SMALL_COUNT3(block) NAE_REG(block, 5, 0x13)
+#define ILK_SMALL_COUNT4(block) NAE_REG(block, 5, 0x14)
+#define ILK_SMALL_COUNT5(block) NAE_REG(block, 5, 0x15)
+#define ILK_SMALL_COUNT6(block) NAE_REG(block, 5, 0x16)
+#define ILK_SMALL_COUNT7(block) NAE_REG(block, 5, 0x17)
+#define ILK_MID_COUNT0(block) NAE_REG(block, 5, 0x18)
+#define ILK_MID_COUNT1(block) NAE_REG(block, 5, 0x19)
+#define ILK_LARGE_COUNT0(block) NAE_REG(block, 5, 0x1a)
+#define ILK_LARGE_COUNT1(block) NAE_REG(block, 5, 0x1b)
+#define ILK_LARGE_COUNT_H0(block) NAE_REG(block, 5, 0x1c)
+#define ILK_LARGE_COUNT_H1(block) NAE_REG(block, 5, 0x1d)
+
+#endif
Property changes on: trunk/sys/mips/nlm/hal/interlaken.h
___________________________________________________________________
Added: svn:eol-style
## -0,0 +1 ##
+native
\ No newline at end of property
Added: svn:keywords
## -0,0 +1 ##
+MidnightBSD=%H
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+text/plain
\ No newline at end of property
Added: trunk/sys/mips/nlm/hal/iomap.h
===================================================================
--- trunk/sys/mips/nlm/hal/iomap.h (rev 0)
+++ trunk/sys/mips/nlm/hal/iomap.h 2018-05-26 21:55:02 UTC (rev 9987)
@@ -0,0 +1,207 @@
+/* $MidnightBSD$ */
+/*-
+ * Copyright 2003-2011 Netlogic Microsystems (Netlogic). All rights
+ * reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in
+ * the documentation and/or other materials provided with the
+ * distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY Netlogic Microsystems ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL NETLOGIC OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
+ * THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * NETLOGIC_BSD
+ * $FreeBSD: stable/10/sys/mips/nlm/hal/iomap.h 233545 2012-03-27 14:05:12Z jchandra $
+ */
+
+#ifndef __NLM_HAL_IOMAP_H__
+#define __NLM_HAL_IOMAP_H__
+
+#define XLP_DEFAULT_IO_BASE 0x18000000
+#define NMI_BASE 0xbfc00000
+#define XLP_IO_CLK 133333333
+
+#define XLP_L2L3_CACHELINE_SIZE 64
+#define XLP_PCIE_CFG_SIZE 0x1000 /* 4K */
+#define XLP_PCIE_DEV_BLK_SIZE (8 * XLP_PCIE_CFG_SIZE)
+#define XLP_PCIE_BUS_BLK_SIZE (256 * XLP_PCIE_DEV_BLK_SIZE)
+#define XLP_IO_SIZE (64 << 20) /* ECFG space size */
+#define XLP_IO_PCI_HDRSZ 0x100
+#define XLP_IO_DEV(node, dev) ((dev) + (node) * 8)
+#define XLP_HDR_OFFSET(node, bus, dev, fn) (((bus) << 20) | \
+ ((XLP_IO_DEV(node, dev)) << 15) | ((fn) << 12))
+
+#define XLP_IO_BRIDGE_OFFSET(node) XLP_HDR_OFFSET(node, 0, 0, 0)
+/* coherent inter chip */
+#define XLP_IO_CIC0_OFFSET(node) XLP_HDR_OFFSET(node, 0, 0, 1)
+#define XLP_IO_CIC1_OFFSET(node) XLP_HDR_OFFSET(node, 0, 0, 2)
+#define XLP_IO_CIC2_OFFSET(node) XLP_HDR_OFFSET(node, 0, 0, 3)
+#define XLP_IO_PIC_OFFSET(node) XLP_HDR_OFFSET(node, 0, 0, 4)
+
+#define XLP_IO_PCIE_OFFSET(node, i) XLP_HDR_OFFSET(node, 0, 1, i)
+#define XLP_IO_PCIE0_OFFSET(node) XLP_HDR_OFFSET(node, 0, 1, 0)
+#define XLP_IO_PCIE1_OFFSET(node) XLP_HDR_OFFSET(node, 0, 1, 1)
+#define XLP_IO_PCIE2_OFFSET(node) XLP_HDR_OFFSET(node, 0, 1, 2)
+#define XLP_IO_PCIE3_OFFSET(node) XLP_HDR_OFFSET(node, 0, 1, 3)
+
+#define XLP_IO_USB_OFFSET(node, i) XLP_HDR_OFFSET(node, 0, 2, i)
+#define XLP_IO_USB_EHCI0_OFFSET(node) XLP_HDR_OFFSET(node, 0, 2, 0)
+#define XLP_IO_USB_OHCI0_OFFSET(node) XLP_HDR_OFFSET(node, 0, 2, 1)
+#define XLP_IO_USB_OHCI1_OFFSET(node) XLP_HDR_OFFSET(node, 0, 2, 2)
+#define XLP_IO_USB_EHCI1_OFFSET(node) XLP_HDR_OFFSET(node, 0, 2, 3)
+#define XLP_IO_USB_OHCI2_OFFSET(node) XLP_HDR_OFFSET(node, 0, 2, 4)
+#define XLP_IO_USB_OHCI3_OFFSET(node) XLP_HDR_OFFSET(node, 0, 2, 5)
+
+#define XLP_IO_NAE_OFFSET(node) XLP_HDR_OFFSET(node, 0, 3, 0)
+#define XLP_IO_POE_OFFSET(node) XLP_HDR_OFFSET(node, 0, 3, 1)
+#define XLP_IO_SATA_OFFSET(node) XLP_HDR_OFFSET(node, 0, 3, 2)
+
+#define XLP_IO_CMS_OFFSET(node) XLP_HDR_OFFSET(node, 0, 4, 0)
+
+#define XLP_IO_DMA_OFFSET(node) XLP_HDR_OFFSET(node, 0, 5, 0)
+#define XLP_IO_SEC_OFFSET(node) XLP_HDR_OFFSET(node, 0, 5, 1)
+#define XLP_IO_RSA_OFFSET(node) XLP_HDR_OFFSET(node, 0, 5, 2)
+#define XLP_IO_CMP_OFFSET(node) XLP_HDR_OFFSET(node, 0, 5, 3)
+#define XLP_IO_SRIO_OFFSET(node) XLP_HDR_OFFSET(node, 0, 5, 4)
+#define XLP_IO_REGEX_OFFSET(node) XLP_HDR_OFFSET(node, 0, 5, 5)
+
+#define XLP_IO_UART_OFFSET(node, i) XLP_HDR_OFFSET(node, 0, 6, i)
+#define XLP_IO_UART0_OFFSET(node) XLP_HDR_OFFSET(node, 0, 6, 0)
+#define XLP_IO_UART1_OFFSET(node) XLP_HDR_OFFSET(node, 0, 6, 1)
+#define XLP_IO_I2C_OFFSET(node, i) XLP_HDR_OFFSET(node, 0, 6, 2 + i)
+#define XLP_IO_I2C0_OFFSET(node) XLP_HDR_OFFSET(node, 0, 6, 2)
+#define XLP_IO_I2C1_OFFSET(node) XLP_HDR_OFFSET(node, 0, 6, 3)
+#define XLP_IO_GPIO_OFFSET(node) XLP_HDR_OFFSET(node, 0, 6, 4)
+/* system management */
+#define XLP_IO_SYS_OFFSET(node) XLP_HDR_OFFSET(node, 0, 6, 5)
+#define XLP_IO_JTAG_OFFSET(node) XLP_HDR_OFFSET(node, 0, 6, 6)
+
+#define XLP_IO_NOR_OFFSET(node) XLP_HDR_OFFSET(node, 0, 7, 0)
+#define XLP_IO_NAND_OFFSET(node) XLP_HDR_OFFSET(node, 0, 7, 1)
+#define XLP_IO_SPI_OFFSET(node) XLP_HDR_OFFSET(node, 0, 7, 2)
+/* SD flash */
+#define XLP_IO_SD_OFFSET(node) XLP_HDR_OFFSET(node, 0, 7, 3)
+#define XLP_IO_MMC_OFFSET(node, slot) \
+ ((XLP_IO_SD_OFFSET(node))+(slot*0x100)+XLP_IO_PCI_HDRSZ)
+
+/* PCI config header register id's */
+#define XLP_PCI_CFGREG0 0x00
+#define XLP_PCI_CFGREG1 0x01
+#define XLP_PCI_CFGREG2 0x02
+#define XLP_PCI_CFGREG3 0x03
+#define XLP_PCI_CFGREG4 0x04
+#define XLP_PCI_CFGREG5 0x05
+#define XLP_PCI_DEVINFO_REG0 0x30
+#define XLP_PCI_DEVINFO_REG1 0x31
+#define XLP_PCI_DEVINFO_REG2 0x32
+#define XLP_PCI_DEVINFO_REG3 0x33
+#define XLP_PCI_DEVINFO_REG4 0x34
+#define XLP_PCI_DEVINFO_REG5 0x35
+#define XLP_PCI_DEVINFO_REG6 0x36
+#define XLP_PCI_DEVINFO_REG7 0x37
+#define XLP_PCI_DEVSCRATCH_REG0 0x38
+#define XLP_PCI_DEVSCRATCH_REG1 0x39
+#define XLP_PCI_DEVSCRATCH_REG2 0x3a
+#define XLP_PCI_DEVSCRATCH_REG3 0x3b
+#define XLP_PCI_MSGSTN_REG 0x3c
+#define XLP_PCI_IRTINFO_REG 0x3d
+#define XLP_PCI_UCODEINFO_REG 0x3e
+#define XLP_PCI_SBB_WT_REG 0x3f
+
+/* PCI IDs for SoC device */
+#define PCI_VENDOR_NETLOGIC 0x184e
+
+#define PCI_DEVICE_ID_NLM_ROOT 0x1001
+#define PCI_DEVICE_ID_NLM_ICI 0x1002
+#define PCI_DEVICE_ID_NLM_PIC 0x1003
+#define PCI_DEVICE_ID_NLM_PCIE 0x1004
+#define PCI_DEVICE_ID_NLM_EHCI 0x1007
+#define PCI_DEVICE_ID_NLM_ILK 0x1008
+#define PCI_DEVICE_ID_NLM_NAE 0x1009
+#define PCI_DEVICE_ID_NLM_POE 0x100A
+#define PCI_DEVICE_ID_NLM_FMN 0x100B
+#define PCI_DEVICE_ID_NLM_RAID 0x100D
+#define PCI_DEVICE_ID_NLM_SAE 0x100D
+#define PCI_DEVICE_ID_NLM_RSA 0x100E
+#define PCI_DEVICE_ID_NLM_CMP 0x100F
+#define PCI_DEVICE_ID_NLM_UART 0x1010
+#define PCI_DEVICE_ID_NLM_I2C 0x1011
+#define PCI_DEVICE_ID_NLM_NOR 0x1015
+#define PCI_DEVICE_ID_NLM_NAND 0x1016
+#define PCI_DEVICE_ID_NLM_MMC 0x1018
+
+#if !defined(LOCORE) && !defined(__ASSEMBLY__)
+
+#define nlm_read_pci_reg(b, r) nlm_read_reg(b, r)
+#define nlm_write_pci_reg(b, r, v) nlm_write_reg(b, r, v)
+
+extern uint64_t xlp_sys_base;
+extern uint64_t xlp_pic_base;
+
+static __inline__ int
+nlm_dev_exists(uint32_t devoffset)
+{
+ uint64_t pcibase = nlm_pcicfg_base(devoffset);
+
+ return (nlm_read_reg(pcibase, XLP_PCI_CFGREG0) != 0xffffffff);
+}
+
+static __inline__ int
+nlm_qidstart(uint64_t pcibase)
+{
+ return (nlm_read_reg(pcibase, XLP_PCI_MSGSTN_REG) & 0xffff);
+}
+
+static __inline__ int
+nlm_qnum(uint64_t pcibase)
+{
+ return (nlm_read_reg(pcibase, XLP_PCI_MSGSTN_REG) >> 16);
+}
+
+static __inline__ int
+nlm_irtstart(uint64_t pcibase)
+{
+ return (nlm_read_reg(pcibase, XLP_PCI_IRTINFO_REG) & 0xffff);
+}
+
+static __inline__ int
+nlm_irtnum(uint64_t pcibase)
+{
+ return (nlm_read_reg(pcibase, XLP_PCI_IRTINFO_REG) >> 16);
+}
+
+static __inline__ int
+nlm_num_uengines(uint64_t pcibase)
+{
+ return nlm_read_reg(pcibase, XLP_PCI_UCODEINFO_REG);
+}
+
+/*
+ * Find node on which a given Soc device is located.
+ * input is the pci device (slot) number.
+ */
+static __inline__ int
+nlm_get_device_node(int device)
+{
+ return (device / 8);
+}
+
+#endif /* !LOCORE or !__ASSEMBLY */
+
+#endif /* __NLM_HAL_IOMAP_H__ */
Property changes on: trunk/sys/mips/nlm/hal/iomap.h
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+native
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+MidnightBSD=%H
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Added: trunk/sys/mips/nlm/hal/mdio.h
===================================================================
--- trunk/sys/mips/nlm/hal/mdio.h (rev 0)
+++ trunk/sys/mips/nlm/hal/mdio.h 2018-05-26 21:55:02 UTC (rev 9987)
@@ -0,0 +1,107 @@
+/* $MidnightBSD$ */
+/*-
+ * Copyright (c) 2003-2012 Broadcom Corporation
+ * All Rights Reserved
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in
+ * the documentation and/or other materials provided with the
+ * distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY BROADCOM ``AS IS'' AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL BROADCOM OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
+ * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
+ * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
+ * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * $FreeBSD: stable/10/sys/mips/nlm/hal/mdio.h 245881 2013-01-24 15:14:22Z jchandra $
+ */
+
+#ifndef __NLM_MDIO_H__
+#define __NLM_MDIO_H__
+
+/**
+* @file_name mdio.h
+* @author Netlogic Microsystems
+* @brief Access functions for XLP MDIO
+*/
+#define INT_MDIO_CTRL 0x19
+#define INT_MDIO_CTRL_DATA 0x1A
+#define INT_MDIO_RD_STAT 0x1B
+#define INT_MDIO_LINK_STAT 0x1C
+#define EXT_G0_MDIO_CTRL 0x1D
+#define EXT_G1_MDIO_CTRL 0x21
+#define EXT_G0_MDIO_CTRL_DATA 0x1E
+#define EXT_G1_MDIO_CTRL_DATA 0x22
+#define EXT_G0_MDIO_LINK_STAT 0x20
+#define EXT_G1_MDIO_LINK_STAT 0x24
+#define EXT_G0_MDIO_RD_STAT 0x1F
+#define EXT_G1_MDIO_RD_STAT 0x23
+
+#define INT_MDIO_CTRL_ST_POS 0
+#define INT_MDIO_CTRL_OP_POS 2
+#define INT_MDIO_CTRL_PHYADDR_POS 4
+#define INT_MDIO_CTRL_DEVTYPE_POS 9
+#define INT_MDIO_CTRL_TA_POS 14
+#define INT_MDIO_CTRL_MIIM_POS 16
+#define INT_MDIO_CTRL_LOAD_POS 19
+#define INT_MDIO_CTRL_XDIV_POS 21
+#define INT_MDIO_CTRL_MCDIV_POS 28
+#define INT_MDIO_CTRL_RST 0x40000000
+#define INT_MDIO_CTRL_SMP 0x00100000
+#define INT_MDIO_CTRL_CMD_LOAD 0x00080000
+
+#define INT_MDIO_RD_STAT_MASK 0x0000FFFF
+#define INT_MDIO_STAT_LFV 0x00010000
+#define INT_MDIO_STAT_SC 0x00020000
+#define INT_MDIO_STAT_SM 0x00040000
+#define INT_MDIO_STAT_MIILFS 0x00080000
+#define INT_MDIO_STAT_MBSY 0x00100000
+
+#define EXT_G_MDIO_CLOCK_DIV_4 0
+#define EXT_G_MDIO_CLOCK_DIV_2 1
+#define EXT_G_MDIO_CLOCK_DIV_1 2
+#define EXT_G_MDIO_REGADDR_POS 5
+#define EXT_G_MDIO_PHYADDR_POS 10
+#define EXT_G_MDIO_CMD_SP 0x00008000
+#define EXT_G_MDIO_CMD_PSIA 0x00010000
+#define EXT_G_MDIO_CMD_LCD 0x00020000
+#define EXT_G_MDIO_CMD_RDS 0x00040000
+#define EXT_G_MDIO_CMD_SC 0x00080000
+#define EXT_G_MDIO_MMRST 0x00100000
+#define EXT_G_MDIO_DIV 0x0000001E
+#define EXT_G_MDIO_DIV_WITH_HW_DIV64 0x00000010
+
+#define EXT_G_MDIO_RD_STAT_MASK 0x0000FFFF
+#define EXT_G_MDIO_STAT_LFV 0x00010000
+#define EXT_G_MDIO_STAT_SC 0x00020000
+#define EXT_G_MDIO_STAT_SM 0x00040000
+#define EXT_G_MDIO_STAT_MIILFS 0x00080000
+#define EXT_G_MDIO_STAT_MBSY 0x80000000
+#define MDIO_OP_CMD_READ 0x10
+#define MDIO_OP_CMD_WRITE 0x01
+
+#if !defined(LOCORE) && !defined(__ASSEMBLY__)
+
+int nlm_int_gmac_mdio_read(uint64_t, int, int, int, int, int);
+int nlm_int_gmac_mdio_write(uint64_t, int, int, int, int, int, uint16_t);
+int nlm_int_gmac_mdio_reset(uint64_t, int, int, int);
+int nlm_gmac_mdio_read(uint64_t, int, int, int, int, int);
+int nlm_gmac_mdio_write(uint64_t, int, int, int, int, int, uint16_t);
+int nlm_gmac_mdio_reset(uint64_t, int, int, int);
+void nlm_mdio_reset_all(uint64_t);
+
+#endif /* !(LOCORE) && !(__ASSEMBLY__) */
+#endif
Property changes on: trunk/sys/mips/nlm/hal/mdio.h
___________________________________________________________________
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## -0,0 +1 ##
+native
\ No newline at end of property
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## -0,0 +1 ##
+MidnightBSD=%H
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+text/plain
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Added: trunk/sys/mips/nlm/hal/mips-extns.h
===================================================================
--- trunk/sys/mips/nlm/hal/mips-extns.h (rev 0)
+++ trunk/sys/mips/nlm/hal/mips-extns.h 2018-05-26 21:55:02 UTC (rev 9987)
@@ -0,0 +1,275 @@
+/* $MidnightBSD$ */
+/*-
+ * Copyright 2003-2011 Netlogic Microsystems (Netlogic). All rights
+ * reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in
+ * the documentation and/or other materials provided with the
+ * distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY Netlogic Microsystems ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL NETLOGIC OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
+ * THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * NETLOGIC_BSD
+ * $FreeBSD: stable/10/sys/mips/nlm/hal/mips-extns.h 227722 2011-11-19 14:06:15Z jchandra $
+ */
+
+#ifndef __NLM_MIPS_EXTNS_H__
+#define __NLM_MIPS_EXTNS_H__
+
+#if !defined(LOCORE) && !defined(__ASSEMBLY__)
+static __inline__ int32_t nlm_swapw(int32_t *loc, int32_t val)
+{
+ int32_t oldval = 0;
+
+ __asm__ __volatile__ (
+ ".set push\n"
+ ".set noreorder\n"
+ "move $9, %2\n"
+ "move $8, %3\n"
+ ".word 0x71280014\n" /* "swapw $8, $9\n" */
+ "move %1, $8\n"
+ ".set pop\n"
+ : "+m" (*loc), "=r" (oldval)
+ : "r" (loc), "r" (val)
+ : "$8", "$9" );
+
+ return oldval;
+}
+
+static __inline__ uint32_t nlm_swapwu(int32_t *loc, uint32_t val)
+{
+ uint32_t oldval;
+
+ __asm__ __volatile__ (
+ ".set push\n"
+ ".set noreorder\n"
+ "move $9, %2\n"
+ "move $8, %3\n"
+ ".word 0x71280015\n" /* "swapwu $8, $9\n" */
+ "move %1, $8\n"
+ ".set pop\n"
+ : "+m" (*loc), "=r" (oldval)
+ : "r" (loc), "r" (val)
+ : "$8", "$9" );
+
+ return oldval;
+}
+
+#if (__mips == 64)
+static __inline__ uint64_t nlm_swapd(int32_t *loc, uint64_t val)
+{
+ uint64_t oldval;
+
+ __asm__ __volatile__ (
+ ".set push\n"
+ ".set noreorder\n"
+ "move $9, %2\n"
+ "move $8, %3\n"
+ ".word 0x71280014\n" /* "swapw $8, $9\n" */
+ "move %1, $8\n"
+ ".set pop\n"
+ : "+m" (*loc), "=r" (oldval)
+ : "r" (loc), "r" (val)
+ : "$8", "$9" );
+
+ return oldval;
+}
+#endif
+
+/*
+ * Atomic increment a unsigned int
+ */
+static __inline unsigned int
+nlm_ldaddwu(unsigned int value, unsigned int *addr)
+{
+ __asm__ __volatile__(
+ ".set push\n"
+ ".set noreorder\n"
+ "move $8, %2\n"
+ "move $9, %3\n"
+ ".word 0x71280011\n" /* ldaddwu $8, $9 */
+ "move %0, $8\n"
+ ".set pop\n"
+ : "=&r"(value), "+m"(*addr)
+ : "0"(value), "r" ((unsigned long)addr)
+ : "$8", "$9");
+
+ return (value);
+}
+/*
+ * 32 bit read write for c0
+ */
+#define read_c0_register32(reg, sel) \
+({ \
+ uint32_t __rv; \
+ __asm__ __volatile__( \
+ ".set push\n\t" \
+ ".set mips32\n\t" \
+ "mfc0 %0, $%1, %2\n\t" \
+ ".set pop\n" \
+ : "=r" (__rv) : "i" (reg), "i" (sel) ); \
+ __rv; \
+ })
+
+#define write_c0_register32(reg, sel, value) \
+ __asm__ __volatile__( \
+ ".set push\n\t" \
+ ".set mips32\n\t" \
+ "mtc0 %0, $%1, %2\n\t" \
+ ".set pop\n" \
+ : : "r" (value), "i" (reg), "i" (sel) );
+
+#if defined(__mips_n64) || defined(__mips_n32)
+/*
+ * On 64 bit compilation, the operations are simple
+ */
+#define read_c0_register64(reg, sel) \
+({ \
+ uint64_t __rv; \
+ __asm__ __volatile__( \
+ ".set push\n\t" \
+ ".set mips64\n\t" \
+ "dmfc0 %0, $%1, %2\n\t" \
+ ".set pop\n" \
+ : "=r" (__rv) : "i" (reg), "i" (sel) ); \
+ __rv; \
+ })
+
+#define write_c0_register64(reg, sel, value) \
+ __asm__ __volatile__( \
+ ".set push\n\t" \
+ ".set mips64\n\t" \
+ "dmtc0 %0, $%1, %2\n\t" \
+ ".set pop\n" \
+ : : "r" (value), "i" (reg), "i" (sel) );
+#else /* ! (defined(__mips_n64) || defined(__mips_n32)) */
+
+/*
+ * 32 bit compilation, 64 bit values has to split
+ */
+#define read_c0_register64(reg, sel) \
+({ \
+ uint32_t __high, __low; \
+ __asm__ __volatile__( \
+ ".set push\n\t" \
+ ".set noreorder\n\t" \
+ ".set mips64\n\t" \
+ "dmfc0 $8, $%2, %3\n\t" \
+ "dsra32 %0, $8, 0\n\t" \
+ "sll %1, $8, 0\n\t" \
+ ".set pop\n" \
+ : "=r"(__high), "=r"(__low): "i"(reg), "i"(sel) \
+ : "$8"); \
+ ((uint64_t)__high << 32) | __low; \
+})
+
+#define write_c0_register64(reg, sel, value) \
+do { \
+ uint32_t __high = value >> 32; \
+ uint32_t __low = value & 0xffffffff; \
+ __asm__ __volatile__( \
+ ".set push\n\t" \
+ ".set noreorder\n\t" \
+ ".set mips64\n\t" \
+ "dsll32 $8, %1, 0\n\t" \
+ "dsll32 $9, %0, 0\n\t" \
+ "dsrl32 $8, $8, 0\n\t" \
+ "or $8, $8, $9\n\t" \
+ "dmtc0 $8, $%2, %3\n\t" \
+ ".set pop" \
+ :: "r"(__high), "r"(__low), "i"(reg), "i"(sel) \
+ :"$8", "$9"); \
+} while(0)
+
+#endif
+/* functions to write to and read from the extended
+ * cp0 registers.
+ * EIRR : Extended Interrupt Request Register
+ * cp0 register 9 sel 6
+ * bits 0...7 are same as cause register 8...15
+ * EIMR : Extended Interrupt Mask Register
+ * cp0 register 9 sel 7
+ * bits 0...7 are same as status register 8...15
+ */
+static __inline uint64_t
+nlm_read_c0_eirr(void)
+{
+
+ return (read_c0_register64(9, 6));
+}
+
+static __inline void
+nlm_write_c0_eirr(uint64_t val)
+{
+
+ write_c0_register64(9, 6, val);
+}
+
+static __inline uint64_t
+nlm_read_c0_eimr(void)
+{
+
+ return (read_c0_register64(9, 7));
+}
+
+static __inline void
+nlm_write_c0_eimr(uint64_t val)
+{
+
+ write_c0_register64(9, 7, val);
+}
+
+static __inline__ uint32_t
+nlm_read_c0_ebase(void)
+{
+
+ return (read_c0_register32(15, 1));
+}
+
+static __inline__ int
+nlm_nodeid(void)
+{
+ return (nlm_read_c0_ebase() >> 5) & 0x3;
+}
+
+static __inline__ int
+nlm_cpuid(void)
+{
+ return nlm_read_c0_ebase() & 0x1f;
+}
+
+static __inline__ int
+nlm_threadid(void)
+{
+ return nlm_read_c0_ebase() & 0x3;
+}
+
+static __inline__ int
+nlm_coreid(void)
+{
+ return (nlm_read_c0_ebase() >> 2) & 0x7;
+}
+#endif
+
+#define XLP_MAX_NODES 4
+#define XLP_MAX_CORES 8
+#define XLP_MAX_THREADS 4
+
+#endif
Property changes on: trunk/sys/mips/nlm/hal/mips-extns.h
___________________________________________________________________
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+native
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+MidnightBSD=%H
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+text/plain
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Added: trunk/sys/mips/nlm/hal/mmu.h
===================================================================
--- trunk/sys/mips/nlm/hal/mmu.h (rev 0)
+++ trunk/sys/mips/nlm/hal/mmu.h 2018-05-26 21:55:02 UTC (rev 9987)
@@ -0,0 +1,166 @@
+/* $MidnightBSD$ */
+/*-
+ * Copyright 2003-2011 Netlogic Microsystems (Netlogic). All rights
+ * reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in
+ * the documentation and/or other materials provided with the
+ * distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY Netlogic Microsystems ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL NETLOGIC OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
+ * THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * NETLOGIC_BSD
+ * $FreeBSD: stable/10/sys/mips/nlm/hal/mmu.h 227722 2011-11-19 14:06:15Z jchandra $
+ */
+
+#ifndef __XLP_MMU_H__
+#define __XLP_MMU_H__
+
+#include <mips/nlm/hal/mips-extns.h>
+
+static __inline__ uint32_t
+nlm_read_c0_config6(void)
+{
+ uint32_t rv;
+
+ __asm__ __volatile__ (
+ ".set push\n"
+ ".set mips64\n"
+ "mfc0 %0, $16, 6\n"
+ ".set pop\n"
+ : "=r" (rv));
+
+ return rv;
+}
+
+static __inline__ void
+nlm_write_c0_config6(uint32_t value)
+{
+ __asm__ __volatile__ (
+ ".set push\n"
+ ".set mips64\n"
+ "mtc0 %0, $16, 6\n"
+ ".set pop\n"
+ : : "r" (value));
+}
+
+static __inline__ uint32_t
+nlm_read_c0_config7(void)
+{
+ uint32_t rv;
+
+ __asm__ __volatile__ (
+ ".set push\n"
+ ".set mips64\n"
+ "mfc0 %0, $16, 7\n"
+ ".set pop\n"
+ : "=r" (rv));
+
+ return rv;
+}
+
+static __inline__ void
+nlm_write_c0_config7(uint32_t value)
+{
+ __asm__ __volatile__ (
+ ".set push\n"
+ ".set mips64\n"
+ "mtc0 %0, $16, 7\n"
+ ".set pop\n"
+ : : "r" (value));
+}
+/**
+ * On power on reset, XLP comes up with 64 TLBs.
+ * Large-variable-tlb's (ELVT) and extended TLB is disabled.
+ * Enabling large-variable-tlb's sets up the standard
+ * TLB size from 64 to 128 TLBs.
+ * Enabling fixed TLB (EFT) sets up an additional 2048 tlbs.
+ * ELVT + EFT = 128 + 2048 = 2176 TLB entries.
+ * threads 64-entry-standard-tlb 128-entry-standard-tlb
+ * per std-tlb-only| std+EFT | std-tlb-only| std+EFT
+ * core | | |
+ * --------------------------------------------------------
+ * 1 64 64+2048 128 128+2048
+ * 2 64 64+1024 64 64+1024
+ * 4 32 32+512 32 32+512
+ *
+ * 1(G) 64 64+2048 128 128+2048
+ * 2(G) 128 128+2048 128 128+2048
+ * 4(G) 128 128+2048 128 128+2048
+ * (G) = Global mode
+ */
+
+
+/* en = 1 to enable
+ * en = 0 to disable
+ */
+static __inline__ void nlm_large_variable_tlb_en (int en)
+{
+ unsigned int val;
+
+ val = nlm_read_c0_config6();
+ val |= (en << 5);
+ nlm_write_c0_config6(val);
+ return;
+}
+
+/* en = 1 to enable
+ * en = 0 to disable
+ */
+static __inline__ void nlm_pagewalker_en(int en)
+{
+ unsigned int val;
+
+ val = nlm_read_c0_config6();
+ val |= (en << 3);
+ nlm_write_c0_config6(val);
+ return;
+}
+
+/* en = 1 to enable
+ * en = 0 to disable
+ */
+static __inline__ void nlm_extended_tlb_en(int en)
+{
+ unsigned int val;
+
+ val = nlm_read_c0_config6();
+ val |= (en << 2);
+ nlm_write_c0_config6(val);
+ return;
+}
+
+static __inline__ int nlm_get_num_combined_tlbs(void)
+{
+ return (((nlm_read_c0_config6() >> 16) & 0xffff) + 1);
+}
+
+/* get number of variable TLB entries */
+static __inline__ int nlm_get_num_vtlbs(void)
+{
+ return (((nlm_read_c0_config6() >> 6) & 0x3ff) + 1);
+}
+
+static __inline__ void nlm_setup_extended_pagemask(int mask)
+{
+ nlm_write_c0_config7(mask);
+}
+
+#endif
Property changes on: trunk/sys/mips/nlm/hal/mmu.h
___________________________________________________________________
Added: svn:eol-style
## -0,0 +1 ##
+native
\ No newline at end of property
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## -0,0 +1 ##
+MidnightBSD=%H
\ No newline at end of property
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## -0,0 +1 ##
+text/plain
\ No newline at end of property
Added: trunk/sys/mips/nlm/hal/nae.h
===================================================================
--- trunk/sys/mips/nlm/hal/nae.h (rev 0)
+++ trunk/sys/mips/nlm/hal/nae.h 2018-05-26 21:55:02 UTC (rev 9987)
@@ -0,0 +1,657 @@
+/* $MidnightBSD$ */
+/*-
+ * Copyright (c) 2003-2012 Broadcom Corporation
+ * All Rights Reserved
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in
+ * the documentation and/or other materials provided with the
+ * distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY BROADCOM ``AS IS'' AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL BROADCOM OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
+ * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
+ * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
+ * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * $FreeBSD: stable/10/sys/mips/nlm/hal/nae.h 255368 2013-09-07 18:26:16Z jchandra $
+ */
+
+#ifndef __NLM_NAE_H__
+#define __NLM_NAE_H__
+
+/**
+* @file_name nae.h
+* @author Netlogic Microsystems
+* @brief Basic definitions of XLP Networt Accelerator Engine
+*/
+
+/* NAE specific registers */
+#define NAE_REG(blk, intf, reg) (((blk) << 11) | ((intf) << 7) | (reg))
+
+/* ingress path registers */
+#define NAE_RX_CONFIG NAE_REG(7, 0, 0x10)
+#define NAE_RX_IF_BASE_CONFIG0 NAE_REG(7, 0, 0x12)
+#define NAE_RX_IF_BASE_CONFIG1 NAE_REG(7, 0, 0x13)
+#define NAE_RX_IF_BASE_CONFIG2 NAE_REG(7, 0, 0x14)
+#define NAE_RX_IF_BASE_CONFIG3 NAE_REG(7, 0, 0x15)
+#define NAE_RX_IF_BASE_CONFIG4 NAE_REG(7, 0, 0x16)
+#define NAE_RX_IF_BASE_CONFIG5 NAE_REG(7, 0, 0x17)
+#define NAE_RX_IF_BASE_CONFIG6 NAE_REG(7, 0, 0x18)
+#define NAE_RX_IF_BASE_CONFIG7 NAE_REG(7, 0, 0x19)
+#define NAE_RX_IF_BASE_CONFIG8 NAE_REG(7, 0, 0x1a)
+#define NAE_RX_IF_BASE_CONFIG9 NAE_REG(7, 0, 0x1b)
+#define NAE_RX_IF_VEC_VALID NAE_REG(7, 0, 0x1c)
+#define NAE_RX_IF_SLOT_CAL NAE_REG(7, 0, 0x1d)
+#define NAE_PARSER_CONFIG NAE_REG(7, 0, 0x1e)
+#define NAE_PARSER_SEQ_FIFO_CFG NAE_REG(7, 0, 0x1f)
+#define NAE_FREE_IN_FIFO_CFG NAE_REG(7, 0, 0x20)
+#define NAE_RXBUF_BASE_DPTH_ADDR NAE_REG(7, 0, 0x21)
+#define NAE_RXBUF_BASE_DPTH NAE_REG(7, 0, 0x22)
+#define NAE_RX_UCORE_CFG NAE_REG(7, 0, 0x23)
+#define NAE_RX_UCORE_CAM_MASK0 NAE_REG(7, 0, 0x24)
+#define NAE_RX_UCORE_CAM_MASK1 NAE_REG(7, 0, 0x25)
+#define NAE_RX_UCORE_CAM_MASK2 NAE_REG(7, 0, 0x26)
+#define NAE_RX_UCORE_CAM_MASK3 NAE_REG(7, 0, 0x27)
+#define NAE_FREEIN_FIFO_UNIQ_SZ_CFG NAE_REG(7, 0, 0x28)
+#define NAE_RX_CRC_POLY0_CFG NAE_REG(7, 0, 0x2a)
+#define NAE_RX_CRC_POLY1_CFG NAE_REG(7, 0, 0x2b)
+#define NAE_FREE_SPILL0_MEM_CFG NAE_REG(7, 0, 0x2c)
+#define NAE_FREE_SPILL1_MEM_CFG NAE_REG(7, 0, 0x2d)
+#define NAE_FREEFIFO_THRESH_CFG NAE_REG(7, 0, 0x2e)
+#define NAE_FLOW_CRC16_POLY_CFG NAE_REG(7, 0, 0x2f)
+#define NAE_EGR_NIOR_CAL_LEN_REG NAE_REG(7, 0, 0x4e)
+#define NAE_EGR_NIOR_CRDT_CAL_PROG NAE_REG(7, 0, 0x52)
+#define NAE_TEST NAE_REG(7, 0, 0x5f)
+#define NAE_BIU_TIMEOUT_CFG NAE_REG(7, 0, 0x60)
+#define NAE_BIU_CFG NAE_REG(7, 0, 0x61)
+#define NAE_RX_FREE_FIFO_POP NAE_REG(7, 0, 0x62)
+#define NAE_RX_DSBL_ECC NAE_REG(7, 0, 0x63)
+#define NAE_FLOW_BASEMASK_CFG NAE_REG(7, 0, 0x80)
+#define NAE_POE_CLASS_SETUP_CFG NAE_REG(7, 0, 0x81)
+#define NAE_UCORE_IFACEMASK_CFG NAE_REG(7, 0, 0x82)
+#define NAE_RXBUF_XOFFON_THRESH NAE_REG(7, 0, 0x83)
+#define NAE_FLOW_TABLE1_CFG NAE_REG(7, 0, 0x84)
+#define NAE_FLOW_TABLE2_CFG NAE_REG(7, 0, 0x85)
+#define NAE_FLOW_TABLE3_CFG NAE_REG(7, 0, 0x86)
+#define NAE_RX_FREE_FIFO_THRESH NAE_REG(7, 0, 0x87)
+#define NAE_RX_PARSER_UNCLA NAE_REG(7, 0, 0x88)
+#define NAE_RX_BUF_INTR_THRESH NAE_REG(7, 0, 0x89)
+#define NAE_IFACE_FIFO_CFG NAE_REG(7, 0, 0x8a)
+#define NAE_PARSER_SEQ_FIFO_THRESH_CFG NAE_REG(7, 0, 0x8b)
+#define NAE_RX_ERRINJ_CTRL0 NAE_REG(7, 0, 0x8c)
+#define NAE_RX_ERRINJ_CTRL1 NAE_REG(7, 0, 0x8d)
+#define NAE_RX_ERR_LATCH0 NAE_REG(7, 0, 0x8e)
+#define NAE_RX_ERR_LATCH1 NAE_REG(7, 0, 0x8f)
+#define NAE_RX_PERF_CTR_CFG NAE_REG(7, 0, 0xa0)
+#define NAE_RX_PERF_CTR_VAL NAE_REG(7, 0, 0xa1)
+
+/* NAE hardware parser registers */
+#define NAE_L2_TYPE_PORT0 NAE_REG(7, 0, 0x210)
+#define NAE_L2_TYPE_PORT1 NAE_REG(7, 0, 0x211)
+#define NAE_L2_TYPE_PORT2 NAE_REG(7, 0, 0x212)
+#define NAE_L2_TYPE_PORT3 NAE_REG(7, 0, 0x213)
+#define NAE_L2_TYPE_PORT4 NAE_REG(7, 0, 0x214)
+#define NAE_L2_TYPE_PORT5 NAE_REG(7, 0, 0x215)
+#define NAE_L2_TYPE_PORT6 NAE_REG(7, 0, 0x216)
+#define NAE_L2_TYPE_PORT7 NAE_REG(7, 0, 0x217)
+#define NAE_L2_TYPE_PORT8 NAE_REG(7, 0, 0x218)
+#define NAE_L2_TYPE_PORT9 NAE_REG(7, 0, 0x219)
+#define NAE_L2_TYPE_PORT10 NAE_REG(7, 0, 0x21a)
+#define NAE_L2_TYPE_PORT11 NAE_REG(7, 0, 0x21b)
+#define NAE_L2_TYPE_PORT12 NAE_REG(7, 0, 0x21c)
+#define NAE_L2_TYPE_PORT13 NAE_REG(7, 0, 0x21d)
+#define NAE_L2_TYPE_PORT14 NAE_REG(7, 0, 0x21e)
+#define NAE_L2_TYPE_PORT15 NAE_REG(7, 0, 0x21f)
+#define NAE_L2_TYPE_PORT16 NAE_REG(7, 0, 0x220)
+#define NAE_L2_TYPE_PORT17 NAE_REG(7, 0, 0x221)
+#define NAE_L2_TYPE_PORT18 NAE_REG(7, 0, 0x222)
+#define NAE_L2_TYPE_PORT19 NAE_REG(7, 0, 0x223)
+#define NAE_L3_CTABLE_MASK0 NAE_REG(7, 0, 0x22c)
+#define NAE_L3_CTABLE_MASK1 NAE_REG(7, 0, 0x22d)
+#define NAE_L3_CTABLE_MASK2 NAE_REG(7, 0, 0x22e)
+#define NAE_L3_CTABLE_MASK3 NAE_REG(7, 0, 0x22f)
+#define NAE_L3CTABLE0 NAE_REG(7, 0, 0x230)
+#define NAE_L3CTABLE1 NAE_REG(7, 0, 0x231)
+#define NAE_L3CTABLE2 NAE_REG(7, 0, 0x232)
+#define NAE_L3CTABLE3 NAE_REG(7, 0, 0x233)
+#define NAE_L3CTABLE4 NAE_REG(7, 0, 0x234)
+#define NAE_L3CTABLE5 NAE_REG(7, 0, 0x235)
+#define NAE_L3CTABLE6 NAE_REG(7, 0, 0x236)
+#define NAE_L3CTABLE7 NAE_REG(7, 0, 0x237)
+#define NAE_L3CTABLE8 NAE_REG(7, 0, 0x238)
+#define NAE_L3CTABLE9 NAE_REG(7, 0, 0x239)
+#define NAE_L3CTABLE10 NAE_REG(7, 0, 0x23a)
+#define NAE_L3CTABLE11 NAE_REG(7, 0, 0x23b)
+#define NAE_L3CTABLE12 NAE_REG(7, 0, 0x23c)
+#define NAE_L3CTABLE13 NAE_REG(7, 0, 0x23d)
+#define NAE_L3CTABLE14 NAE_REG(7, 0, 0x23e)
+#define NAE_L3CTABLE15 NAE_REG(7, 0, 0x23f)
+#define NAE_L4CTABLE0 NAE_REG(7, 0, 0x250)
+#define NAE_L4CTABLE1 NAE_REG(7, 0, 0x251)
+#define NAE_L4CTABLE2 NAE_REG(7, 0, 0x252)
+#define NAE_L4CTABLE3 NAE_REG(7, 0, 0x253)
+#define NAE_L4CTABLE4 NAE_REG(7, 0, 0x254)
+#define NAE_L4CTABLE5 NAE_REG(7, 0, 0x255)
+#define NAE_L4CTABLE6 NAE_REG(7, 0, 0x256)
+#define NAE_L4CTABLE7 NAE_REG(7, 0, 0x257)
+#define NAE_IPV6_EXT_HEADER0 NAE_REG(7, 0, 0x260)
+#define NAE_IPV6_EXT_HEADER1 NAE_REG(7, 0, 0x261)
+#define NAE_VLAN_TYPES01 NAE_REG(7, 0, 0x262)
+#define NAE_VLAN_TYPES23 NAE_REG(7, 0, 0x263)
+
+/* NAE Egress path registers */
+#define NAE_TX_CONFIG NAE_REG(7, 0, 0x11)
+#define NAE_DMA_TX_CREDIT_TH NAE_REG(7, 0, 0x29)
+#define NAE_STG1_STG2CRDT_CMD NAE_REG(7, 0, 0x30)
+#define NAE_STG2_EHCRDT_CMD NAE_REG(7, 0, 0x32)
+#define NAE_EH_FREECRDT_CMD NAE_REG(7, 0, 0x34)
+#define NAE_STG2_STRCRDT_CMD NAE_REG(7, 0, 0x36)
+#define NAE_TXFIFO_IFACEMAP_CMD NAE_REG(7, 0, 0x38)
+#define NAE_VFBID_DESTMAP_CMD NAE_REG(7, 0, 0x3a)
+#define NAE_STG1_PMEM_PROG NAE_REG(7, 0, 0x3c)
+#define NAE_STG2_PMEM_PROG NAE_REG(7, 0, 0x3e)
+#define NAE_EH_PMEM_PROG NAE_REG(7, 0, 0x40)
+#define NAE_FREE_PMEM_PROG NAE_REG(7, 0, 0x42)
+#define NAE_TX_DDR_ACTVLIST_CMD NAE_REG(7, 0, 0x44)
+#define NAE_TX_IF_BURSTMAX_CMD NAE_REG(7, 0, 0x46)
+#define NAE_TX_IF_ENABLE_CMD NAE_REG(7, 0, 0x48)
+#define NAE_TX_PKTLEN_PMEM_CMD NAE_REG(7, 0, 0x4a)
+#define NAE_TX_SCHED_MAP_CMD0 NAE_REG(7, 0, 0x4c)
+#define NAE_TX_SCHED_MAP_CMD1 NAE_REG(7, 0, 0x4d)
+#define NAE_TX_PKT_PMEM_CMD0 NAE_REG(7, 0, 0x50)
+#define NAE_TX_PKT_PMEM_CMD1 NAE_REG(7, 0, 0x51)
+#define NAE_TX_SCHED_CTRL NAE_REG(7, 0, 0x53)
+#define NAE_TX_CRC_POLY0 NAE_REG(7, 0, 0x54)
+#define NAE_TX_CRC_POLY1 NAE_REG(7, 0, 0x55)
+#define NAE_TX_CRC_POLY2 NAE_REG(7, 0, 0x56)
+#define NAE_TX_CRC_POLY3 NAE_REG(7, 0, 0x57)
+#define NAE_STR_PMEM_CMD NAE_REG(7, 0, 0x58)
+#define NAE_TX_IORCRDT_INIT NAE_REG(7, 0, 0x59)
+#define NAE_TX_DSBL_ECC NAE_REG(7, 0, 0x5a)
+#define NAE_TX_IORCRDT_IGNORE NAE_REG(7, 0, 0x5b)
+#define NAE_IF0_1588_TMSTMP_HI NAE_REG(7, 0, 0x300)
+#define NAE_IF1_1588_TMSTMP_HI NAE_REG(7, 0, 0x302)
+#define NAE_IF2_1588_TMSTMP_HI NAE_REG(7, 0, 0x304)
+#define NAE_IF3_1588_TMSTMP_HI NAE_REG(7, 0, 0x306)
+#define NAE_IF4_1588_TMSTMP_HI NAE_REG(7, 0, 0x308)
+#define NAE_IF5_1588_TMSTMP_HI NAE_REG(7, 0, 0x30a)
+#define NAE_IF6_1588_TMSTMP_HI NAE_REG(7, 0, 0x30c)
+#define NAE_IF7_1588_TMSTMP_HI NAE_REG(7, 0, 0x30e)
+#define NAE_IF8_1588_TMSTMP_HI NAE_REG(7, 0, 0x310)
+#define NAE_IF9_1588_TMSTMP_HI NAE_REG(7, 0, 0x312)
+#define NAE_IF10_1588_TMSTMP_HI NAE_REG(7, 0, 0x314)
+#define NAE_IF11_1588_TMSTMP_HI NAE_REG(7, 0, 0x316)
+#define NAE_IF12_1588_TMSTMP_HI NAE_REG(7, 0, 0x318)
+#define NAE_IF13_1588_TMSTMP_HI NAE_REG(7, 0, 0x31a)
+#define NAE_IF14_1588_TMSTMP_HI NAE_REG(7, 0, 0x31c)
+#define NAE_IF15_1588_TMSTMP_HI NAE_REG(7, 0, 0x31e)
+#define NAE_IF16_1588_TMSTMP_HI NAE_REG(7, 0, 0x320)
+#define NAE_IF17_1588_TMSTMP_HI NAE_REG(7, 0, 0x322)
+#define NAE_IF18_1588_TMSTMP_HI NAE_REG(7, 0, 0x324)
+#define NAE_IF19_1588_TMSTMP_HI NAE_REG(7, 0, 0x326)
+#define NAE_IF0_1588_TMSTMP_LO NAE_REG(7, 0, 0x301)
+#define NAE_IF1_1588_TMSTMP_LO NAE_REG(7, 0, 0x303)
+#define NAE_IF2_1588_TMSTMP_LO NAE_REG(7, 0, 0x305)
+#define NAE_IF3_1588_TMSTMP_LO NAE_REG(7, 0, 0x307)
+#define NAE_IF4_1588_TMSTMP_LO NAE_REG(7, 0, 0x309)
+#define NAE_IF5_1588_TMSTMP_LO NAE_REG(7, 0, 0x30b)
+#define NAE_IF6_1588_TMSTMP_LO NAE_REG(7, 0, 0x30d)
+#define NAE_IF7_1588_TMSTMP_LO NAE_REG(7, 0, 0x30f)
+#define NAE_IF8_1588_TMSTMP_LO NAE_REG(7, 0, 0x311)
+#define NAE_IF9_1588_TMSTMP_LO NAE_REG(7, 0, 0x313)
+#define NAE_IF10_1588_TMSTMP_LO NAE_REG(7, 0, 0x315)
+#define NAE_IF11_1588_TMSTMP_LO NAE_REG(7, 0, 0x317)
+#define NAE_IF12_1588_TMSTMP_LO NAE_REG(7, 0, 0x319)
+#define NAE_IF13_1588_TMSTMP_LO NAE_REG(7, 0, 0x31b)
+#define NAE_IF14_1588_TMSTMP_LO NAE_REG(7, 0, 0x31d)
+#define NAE_IF15_1588_TMSTMP_LO NAE_REG(7, 0, 0x31f)
+#define NAE_IF16_1588_TMSTMP_LO NAE_REG(7, 0, 0x321)
+#define NAE_IF17_1588_TMSTMP_LO NAE_REG(7, 0, 0x323)
+#define NAE_IF18_1588_TMSTMP_LO NAE_REG(7, 0, 0x325)
+#define NAE_IF19_1588_TMSTMP_LO NAE_REG(7, 0, 0x327)
+#define NAE_TX_EL0 NAE_REG(7, 0, 0x328)
+#define NAE_TX_EL1 NAE_REG(7, 0, 0x329)
+#define NAE_EIC0 NAE_REG(7, 0, 0x32a)
+#define NAE_EIC1 NAE_REG(7, 0, 0x32b)
+#define NAE_STG1_STG2CRDT_STATUS NAE_REG(7, 0, 0x32c)
+#define NAE_STG2_EHCRDT_STATUS NAE_REG(7, 0, 0x32d)
+#define NAE_STG2_FREECRDT_STATUS NAE_REG(7, 0, 0x32e)
+#define NAE_STG2_STRCRDT_STATUS NAE_REG(7, 0, 0x32f)
+#define NAE_TX_PERF_CNTR_INTR_STATUS NAE_REG(7, 0, 0x330)
+#define NAE_TX_PERF_CNTR_ROLL_STATUS NAE_REG(7, 0, 0x331)
+#define NAE_TX_PERF_CNTR0 NAE_REG(7, 0, 0x332)
+#define NAE_TX_PERF_CNTR1 NAE_REG(7, 0, 0x334)
+#define NAE_TX_PERF_CNTR2 NAE_REG(7, 0, 0x336)
+#define NAE_TX_PERF_CNTR3 NAE_REG(7, 0, 0x338)
+#define NAE_TX_PERF_CNTR4 NAE_REG(7, 0, 0x33a)
+#define NAE_TX_PERF_CNTR0_CTL NAE_REG(7, 0, 0x333)
+#define NAE_TX_PERF_CNTR1_CTL NAE_REG(7, 0, 0x335)
+#define NAE_TX_PERF_CNTR2_CTL NAE_REG(7, 0, 0x337)
+#define NAE_TX_PERF_CNTR3_CTL NAE_REG(7, 0, 0x339)
+#define NAE_TX_PERF_CNTR4_CTL NAE_REG(7, 0, 0x33b)
+#define NAE_VFBID_DESTMAP_STATUS NAE_REG(7, 0, 0x380)
+#define NAE_STG2_PMEM_STATUS NAE_REG(7, 0, 0x381)
+#define NAE_EH_PMEM_STATUS NAE_REG(7, 0, 0x382)
+#define NAE_FREE_PMEM_STATUS NAE_REG(7, 0, 0x383)
+#define NAE_TX_DDR_ACTVLIST_STATUS NAE_REG(7, 0, 0x384)
+#define NAE_TX_IF_BURSTMAX_STATUS NAE_REG(7, 0, 0x385)
+#define NAE_TX_PKTLEN_PMEM_STATUS NAE_REG(7, 0, 0x386)
+#define NAE_TX_SCHED_MAP_STATUS0 NAE_REG(7, 0, 0x387)
+#define NAE_TX_SCHED_MAP_STATUS1 NAE_REG(7, 0, 0x388)
+#define NAE_TX_PKT_PMEM_STATUS NAE_REG(7, 0, 0x389)
+#define NAE_STR_PMEM_STATUS NAE_REG(7, 0, 0x38a)
+
+/* Network interface interrupt registers */
+#define NAE_NET_IF0_INTR_STAT NAE_REG(7, 0, 0x280)
+#define NAE_NET_IF1_INTR_STAT NAE_REG(7, 0, 0x282)
+#define NAE_NET_IF2_INTR_STAT NAE_REG(7, 0, 0x284)
+#define NAE_NET_IF3_INTR_STAT NAE_REG(7, 0, 0x286)
+#define NAE_NET_IF4_INTR_STAT NAE_REG(7, 0, 0x288)
+#define NAE_NET_IF5_INTR_STAT NAE_REG(7, 0, 0x28a)
+#define NAE_NET_IF6_INTR_STAT NAE_REG(7, 0, 0x28c)
+#define NAE_NET_IF7_INTR_STAT NAE_REG(7, 0, 0x28e)
+#define NAE_NET_IF8_INTR_STAT NAE_REG(7, 0, 0x290)
+#define NAE_NET_IF9_INTR_STAT NAE_REG(7, 0, 0x292)
+#define NAE_NET_IF10_INTR_STAT NAE_REG(7, 0, 0x294)
+#define NAE_NET_IF11_INTR_STAT NAE_REG(7, 0, 0x296)
+#define NAE_NET_IF12_INTR_STAT NAE_REG(7, 0, 0x298)
+#define NAE_NET_IF13_INTR_STAT NAE_REG(7, 0, 0x29a)
+#define NAE_NET_IF14_INTR_STAT NAE_REG(7, 0, 0x29c)
+#define NAE_NET_IF15_INTR_STAT NAE_REG(7, 0, 0x29e)
+#define NAE_NET_IF16_INTR_STAT NAE_REG(7, 0, 0x2a0)
+#define NAE_NET_IF17_INTR_STAT NAE_REG(7, 0, 0x2a2)
+#define NAE_NET_IF18_INTR_STAT NAE_REG(7, 0, 0x2a4)
+#define NAE_NET_IF19_INTR_STAT NAE_REG(7, 0, 0x2a6)
+#define NAE_NET_IF0_INTR_MASK NAE_REG(7, 0, 0x281)
+#define NAE_NET_IF1_INTR_MASK NAE_REG(7, 0, 0x283)
+#define NAE_NET_IF2_INTR_MASK NAE_REG(7, 0, 0x285)
+#define NAE_NET_IF3_INTR_MASK NAE_REG(7, 0, 0x287)
+#define NAE_NET_IF4_INTR_MASK NAE_REG(7, 0, 0x289)
+#define NAE_NET_IF5_INTR_MASK NAE_REG(7, 0, 0x28b)
+#define NAE_NET_IF6_INTR_MASK NAE_REG(7, 0, 0x28d)
+#define NAE_NET_IF7_INTR_MASK NAE_REG(7, 0, 0x28f)
+#define NAE_NET_IF8_INTR_MASK NAE_REG(7, 0, 0x291)
+#define NAE_NET_IF9_INTR_MASK NAE_REG(7, 0, 0x293)
+#define NAE_NET_IF10_INTR_MASK NAE_REG(7, 0, 0x295)
+#define NAE_NET_IF11_INTR_MASK NAE_REG(7, 0, 0x297)
+#define NAE_NET_IF12_INTR_MASK NAE_REG(7, 0, 0x299)
+#define NAE_NET_IF13_INTR_MASK NAE_REG(7, 0, 0x29b)
+#define NAE_NET_IF14_INTR_MASK NAE_REG(7, 0, 0x29d)
+#define NAE_NET_IF15_INTR_MASK NAE_REG(7, 0, 0x29f)
+#define NAE_NET_IF16_INTR_MASK NAE_REG(7, 0, 0x2a1)
+#define NAE_NET_IF17_INTR_MASK NAE_REG(7, 0, 0x2a3)
+#define NAE_NET_IF18_INTR_MASK NAE_REG(7, 0, 0x2a5)
+#define NAE_NET_IF19_INTR_MASK NAE_REG(7, 0, 0x2a7)
+#define NAE_COMMON0_INTR_STAT NAE_REG(7, 0, 0x2a8)
+#define NAE_COMMON0_INTR_MASK NAE_REG(7, 0, 0x2a9)
+#define NAE_COMMON1_INTR_STAT NAE_REG(7, 0, 0x2aa)
+#define NAE_COMMON1_INTR_MASK NAE_REG(7, 0, 0x2ab)
+
+/* Network Interface Low-block Registers */
+#define NAE_PHY_LANE0_STATUS(block) NAE_REG(block, 0xe, 0)
+#define NAE_PHY_LANE1_STATUS(block) NAE_REG(block, 0xe, 1)
+#define NAE_PHY_LANE2_STATUS(block) NAE_REG(block, 0xe, 2)
+#define NAE_PHY_LANE3_STATUS(block) NAE_REG(block, 0xe, 3)
+#define NAE_PHY_LANE0_CTRL(block) NAE_REG(block, 0xe, 4)
+#define NAE_PHY_LANE1_CTRL(block) NAE_REG(block, 0xe, 5)
+#define NAE_PHY_LANE2_CTRL(block) NAE_REG(block, 0xe, 6)
+#define NAE_PHY_LANE3_CTRL(block) NAE_REG(block, 0xe, 7)
+
+/* Network interface Top-block registers */
+#define NAE_LANE_CFG_CPLX_0_1 NAE_REG(7, 0, 0x780)
+#define NAE_LANE_CFG_CPLX_2_3 NAE_REG(7, 0, 0x781)
+#define NAE_LANE_CFG_CPLX_4 NAE_REG(7, 0, 0x782)
+#define NAE_LANE_CFG_SOFTRESET NAE_REG(7, 0, 0x783)
+#define NAE_1588_PTP_OFFSET_HI NAE_REG(7, 0, 0x784)
+#define NAE_1588_PTP_OFFSET_LO NAE_REG(7, 0, 0x785)
+#define NAE_1588_PTP_INC_DEN NAE_REG(7, 0, 0x786)
+#define NAE_1588_PTP_INC_NUM NAE_REG(7, 0, 0x787)
+#define NAE_1588_PTP_INC_INTG NAE_REG(7, 0, 0x788)
+#define NAE_1588_PTP_CONTROL NAE_REG(7, 0, 0x789)
+#define NAE_1588_PTP_STATUS NAE_REG(7, 0, 0x78a)
+#define NAE_1588_PTP_USER_VALUE_HI NAE_REG(7, 0, 0x78b)
+#define NAE_1588_PTP_USER_VALUE_LO NAE_REG(7, 0, 0x78c)
+#define NAE_1588_PTP_TMR1_HI NAE_REG(7, 0, 0x78d)
+#define NAE_1588_PTP_TMR1_LO NAE_REG(7, 0, 0x78e)
+#define NAE_1588_PTP_TMR2_HI NAE_REG(7, 0, 0x78f)
+#define NAE_1588_PTP_TMR2_LO NAE_REG(7, 0, 0x790)
+#define NAE_1588_PTP_TMR3_HI NAE_REG(7, 0, 0x791)
+#define NAE_1588_PTP_TMR3_LO NAE_REG(7, 0, 0x792)
+#define NAE_TX_FC_CAL_IDX_TBL_CTRL NAE_REG(7, 0, 0x793)
+#define NAE_TX_FC_CAL_TBL_CTRL NAE_REG(7, 0, 0x794)
+#define NAE_TX_FC_CAL_TBL_DATA0 NAE_REG(7, 0, 0x795)
+#define NAE_TX_FC_CAL_TBL_DATA1 NAE_REG(7, 0, 0x796)
+#define NAE_TX_FC_CAL_TBL_DATA2 NAE_REG(7, 0, 0x797)
+#define NAE_TX_FC_CAL_TBL_DATA3 NAE_REG(7, 0, 0x798)
+#define NAE_INT_MDIO_CTRL NAE_REG(7, 0, 0x799)
+#define NAE_INT_MDIO_CTRL_DATA NAE_REG(7, 0, 0x79a)
+#define NAE_INT_MDIO_RD_STAT NAE_REG(7, 0, 0x79b)
+#define NAE_INT_MDIO_LINK_STAT NAE_REG(7, 0, 0x79c)
+#define NAE_EXT_G0_MDIO_CTRL NAE_REG(7, 0, 0x79d)
+#define NAE_EXT_G1_MDIO_CTRL NAE_REG(7, 0, 0x7a1)
+#define NAE_EXT_G0_MDIO_CTRL_DATA NAE_REG(7, 0, 0x79e)
+#define NAE_EXT_G1_MDIO_CTRL_DATA NAE_REG(7, 0, 0x7a2)
+#define NAE_EXT_G0_MDIO_RD_STAT NAE_REG(7, 0, 0x79f)
+#define NAE_EXT_G1_MDIO_RD_STAT NAE_REG(7, 0, 0x7a3)
+#define NAE_EXT_G0_MDIO_LINK_STAT NAE_REG(7, 0, 0x7a0)
+#define NAE_EXT_G1_MDIO_LINK_STAT NAE_REG(7, 0, 0x7a4)
+#define NAE_EXT_XG0_MDIO_CTRL NAE_REG(7, 0, 0x7a5)
+#define NAE_EXT_XG1_MDIO_CTRL NAE_REG(7, 0, 0x7a9)
+#define NAE_EXT_XG0_MDIO_CTRL_DATA NAE_REG(7, 0, 0x7a6)
+#define NAE_EXT_XG1_MDIO_CTRL_DATA NAE_REG(7, 0, 0x7aa)
+#define NAE_EXT_XG0_MDIO_RD_STAT NAE_REG(7, 0, 0x7a7)
+#define NAE_EXT_XG1_MDIO_RD_STAT NAE_REG(7, 0, 0x7ab)
+#define NAE_EXT_XG0_MDIO_LINK_STAT NAE_REG(7, 0, 0x7a8)
+#define NAE_EXT_XG1_MDIO_LINK_STAT NAE_REG(7, 0, 0x7ac)
+#define NAE_GMAC_FC_SLOT0 NAE_REG(7, 0, 0x7ad)
+#define NAE_GMAC_FC_SLOT1 NAE_REG(7, 0, 0x7ae)
+#define NAE_GMAC_FC_SLOT2 NAE_REG(7, 0, 0x7af)
+#define NAE_GMAC_FC_SLOT3 NAE_REG(7, 0, 0x7b0)
+#define NAE_NETIOR_NTB_SLOT NAE_REG(7, 0, 0x7b1)
+#define NAE_NETIOR_MISC_CTRL0 NAE_REG(7, 0, 0x7b2)
+#define NAE_NETIOR_INT0 NAE_REG(7, 0, 0x7b3)
+#define NAE_NETIOR_INT0_MASK NAE_REG(7, 0, 0x7b4)
+#define NAE_NETIOR_INT1 NAE_REG(7, 0, 0x7b5)
+#define NAE_NETIOR_INT1_MASK NAE_REG(7, 0, 0x7b6)
+#define NAE_GMAC_PFC_REPEAT NAE_REG(7, 0, 0x7b7)
+#define NAE_XGMAC_PFC_REPEAT NAE_REG(7, 0, 0x7b8)
+#define NAE_NETIOR_MISC_CTRL1 NAE_REG(7, 0, 0x7b9)
+#define NAE_NETIOR_MISC_CTRL2 NAE_REG(7, 0, 0x7ba)
+#define NAE_NETIOR_INT2 NAE_REG(7, 0, 0x7bb)
+#define NAE_NETIOR_INT2_MASK NAE_REG(7, 0, 0x7bc)
+#define NAE_NETIOR_MISC_CTRL3 NAE_REG(7, 0, 0x7bd)
+
+/* Network interface lane configuration registers */
+#define NAE_LANE_CFG_MISCREG1 NAE_REG(7, 0xf, 0x39)
+#define NAE_LANE_CFG_MISCREG2 NAE_REG(7, 0xf, 0x3A)
+
+/* Network interface soft reset register */
+#define NAE_SOFT_RESET NAE_REG(7, 0xf, 3)
+
+/* ucore instruction/shared CAM RAM access */
+#define NAE_UCORE_SHARED_RAM_OFFSET 0x10000
+
+#define PORTS_PER_CMPLX 4
+#define NAE_CACHELINE_SIZE 64
+
+#define PHY_LANE_0_CTRL 4
+#define PHY_LANE_1_CTRL 5
+#define PHY_LANE_2_CTRL 6
+#define PHY_LANE_3_CTRL 7
+
+#define PHY_LANE_STAT_SRCS 0x00000001
+#define PHY_LANE_STAT_STD 0x00000010
+#define PHY_LANE_STAT_SFEA 0x00000020
+#define PHY_LANE_STAT_STCS 0x00000040
+#define PHY_LANE_STAT_SPC 0x00000200
+#define PHY_LANE_STAT_XLF 0x00000400
+#define PHY_LANE_STAT_PCR 0x00000800
+
+#define PHY_LANE_CTRL_DATA_POS 0
+#define PHY_LANE_CTRL_ADDR_POS 8
+#define PHY_LANE_CTRL_CMD_READ 0x00010000
+#define PHY_LANE_CTRL_CMD_WRITE 0x00000000
+#define PHY_LANE_CTRL_CMD_START 0x00020000
+#define PHY_LANE_CTRL_CMD_PENDING 0x00040000
+#define PHY_LANE_CTRL_ALL 0x00200000
+#define PHY_LANE_CTRL_FAST_INIT 0x00400000
+#define PHY_LANE_CTRL_REXSEL_POS 23
+#define PHY_LANE_CTRL_PHYMODE_POS 25
+#define PHY_LANE_CTRL_PWRDOWN 0x20000000
+#define PHY_LANE_CTRL_RST 0x40000000
+#define PHY_LANE_CTRL_RST_XAUI 0xc0000000
+#define PHY_LANE_CTRL_BPC_XAUI 0x80000000
+
+#define LANE_CFG_CPLX_0_1 0x0
+#define LANE_CFG_CPLX_2_3 0x1
+#define LANE_CFG_CPLX_4 0x2
+
+#define MAC_CONF1 0x0
+#define MAC_CONF2 0x1
+#define MAX_FRM 0x4
+
+#define NETIOR_GMAC_CTRL1 0x7F
+#define NETIOR_GMAC_CTRL2 0x7E
+#define NETIOR_GMAC_CTRL3 0x7C
+
+#define SGMII_CAL_SLOTS 3
+#define XAUI_CAL_SLOTS 13
+#define IL8_CAL_SLOTS 26
+#define IL4_CAL_SLOTS 10
+
+#define NAE_DRR_QUANTA 2048
+
+#define XLP3XX_STG2_FIFO_SZ 512
+#define XLP3XX_EH_FIFO_SZ 512
+#define XLP3XX_FROUT_FIFO_SZ 512
+#define XLP3XX_MS_FIFO_SZ 512
+#define XLP3XX_PKT_FIFO_SZ 8192
+#define XLP3XX_PKTLEN_FIFO_SZ 512
+
+#define XLP3XX_MAX_STG2_OFFSET 0x7F
+#define XLP3XX_MAX_EH_OFFSET 0x1f
+#define XLP3XX_MAX_FREE_OUT_OFFSET 0x1f
+#define XLP3XX_MAX_MS_OFFSET 0xF
+#define XLP3XX_MAX_PMEM_OFFSET 0x7FE
+
+#define XLP3XX_STG1_2_CREDIT XLP3XX_STG2_FIFO_SZ
+#define XLP3XX_STG2_EH_CREDIT XLP3XX_EH_FIFO_SZ
+#define XLP3XX_STG2_FROUT_CREDIT XLP3XX_FROUT_FIFO_SZ
+#define XLP3XX_STG2_MS_CREDIT XLP3XX_MS_FIFO_SZ
+
+#define XLP8XX_STG2_FIFO_SZ 2048
+#define XLP8XX_EH_FIFO_SZ 4096
+#define XLP8XX_FROUT_FIFO_SZ 4096
+#define XLP8XX_MS_FIFO_SZ 2048
+#define XLP8XX_PKT_FIFO_SZ 16384
+#define XLP8XX_PKTLEN_FIFO_SZ 2048
+
+#define XLP8XX_MAX_STG2_OFFSET 0x7F
+#define XLP8XX_MAX_EH_OFFSET 0x7F
+#define XLP8XX_MAX_FREE_OUT_OFFSET 0x7F
+#define XLP8XX_MAX_MS_OFFSET 0x1F
+#define XLP8XX_MAX_PMEM_OFFSET 0x7FE
+
+#define XLP8XX_STG1_2_CREDIT XLP8XX_STG2_FIFO_SZ
+#define XLP8XX_STG2_EH_CREDIT XLP8XX_EH_FIFO_SZ
+#define XLP8XX_STG2_FROUT_CREDIT XLP8XX_FROUT_FIFO_SZ
+#define XLP8XX_STG2_MS_CREDIT XLP8XX_MS_FIFO_SZ
+
+#define MAX_CAL_SLOTS 64
+#define XLP_MAX_PORTS 18
+#define XLP_STORM_MAX_PORTS 8
+
+#define MAX_FREE_FIFO_POOL_8XX 20
+#define MAX_FREE_FIFO_POOL_3XX 9
+
+#if !defined(LOCORE) && !defined(__ASSEMBLY__)
+
+#define nlm_read_nae_reg(b, r) nlm_read_reg_xkphys(b, r)
+#define nlm_write_nae_reg(b, r, v) nlm_write_reg_xkphys(b, r, v)
+#define nlm_get_nae_pcibase(node) \
+ nlm_pcicfg_base(XLP_IO_NAE_OFFSET(node))
+#define nlm_get_nae_regbase(node) \
+ nlm_xkphys_map_pcibar0(nlm_get_nae_pcibase(node))
+
+#define MAX_POE_CLASSES 8
+#define MAX_POE_CLASS_CTXT_TBL_SZ ((NUM_CONTEXTS / MAX_POE_CLASSES) + 1)
+#define TXINITIORCR(x) (((x) & 0x7ffff) << 8)
+
+enum XLPNAE_TX_TYPE {
+ P2D_NEOP = 0,
+ P2P,
+ P2D_EOP,
+ MSC
+};
+
+enum nblock_type {
+ UNKNOWN = 0, /* DONT MAKE IT NON-ZERO */
+ SGMIIC = 1,
+ XAUIC = 2,
+ ILC = 3
+};
+
+enum nae_interface_type {
+ GMAC_0 = 0,
+ GMAC_1,
+ GMAC_2,
+ GMAC_3,
+ XGMAC,
+ INTERLAKEN,
+ PHY = 0xE,
+ LANE_CFG = 0xF,
+};
+
+enum {
+ LM_UNCONNECTED = 0,
+ LM_SGMII = 1,
+ LM_XAUI = 2,
+ LM_IL = 3,
+};
+
+enum nae_block {
+ BLOCK_0 = 0,
+ BLOCK_1,
+ BLOCK_2,
+ BLOCK_3,
+ BLOCK_4,
+ BLOCK_5,
+ BLOCK_6,
+ BLOCK_7,
+};
+
+enum {
+ PHYMODE_NONE = 0,
+ PHYMODE_HS_SGMII = 1,
+ PHYMODE_XAUI = 1,
+ PHYMODE_SGMII = 2,
+ PHYMODE_IL = 3,
+};
+
+static __inline int
+nae_num_complex(uint64_t nae_pcibase)
+{
+ return (nlm_read_reg(nae_pcibase, XLP_PCI_DEVINFO_REG0) & 0xff);
+}
+
+static __inline int
+nae_num_context(uint64_t nae_pcibase)
+{
+ return (nlm_read_reg(nae_pcibase, XLP_PCI_DEVINFO_REG5));
+}
+
+/* per port config structure */
+struct nae_port_config {
+ int node; /* node id (quickread) */
+ int block; /* network block id (quickread) */
+ int port; /* port id - among the 18 in XLP */
+ int type; /* port type - see xlp_gmac_port_types */
+ int mdio_bus;
+ int phy_addr;
+ int num_channels;
+ int num_free_descs;
+ int free_desc_sizes;
+ int ucore_mask;
+ int loopback_mode; /* is complex is in loopback? */
+ uint32_t freein_spill_size; /* Freein spill size for each port */
+ uint32_t free_fifo_size; /* (512entries x 2desc/entry)1024desc */
+ uint32_t iface_fifo_size;/* 256 entries x 64B/entry = 16KB */
+ uint32_t pseq_fifo_size; /* 1024 entries - 1 pktlen/entry */
+ uint32_t rxbuf_size; /* 4096 entries x 64B = 256KB */
+ uint32_t rx_if_base_config;
+ uint32_t rx_slots_reqd;
+ uint32_t tx_slots_reqd;
+ uint32_t stg2_fifo_size;
+ uint32_t eh_fifo_size;
+ uint32_t frout_fifo_size;
+ uint32_t ms_fifo_size;
+ uint32_t pkt_fifo_size;
+ uint32_t pktlen_fifo_size;
+ uint32_t max_stg2_offset;
+ uint32_t max_eh_offset;
+ uint32_t max_frout_offset;
+ uint32_t max_ms_offset;
+ uint32_t max_pmem_offset;
+ uint32_t stg1_2_credit;
+ uint32_t stg2_eh_credit;
+ uint32_t stg2_frout_credit;
+ uint32_t stg2_ms_credit;
+ uint32_t vlan_pri_en;
+ uint32_t txq;
+ uint32_t rxfreeq;
+ uint32_t ieee1588_inc_intg;
+ uint32_t ieee1588_inc_den;
+ uint32_t ieee1588_inc_num;
+ uint64_t ieee1588_userval;
+ uint64_t ieee1588_ptpoff;
+ uint64_t ieee1588_tmr1;
+ uint64_t ieee1588_tmr2;
+ uint64_t ieee1588_tmr3;
+};
+
+void nlm_nae_flush_free_fifo(uint64_t nae_base, int nblocks);
+void nlm_program_nae_parser_seq_fifo(uint64_t, int, struct nae_port_config *);
+void nlm_setup_rx_cal_cfg(uint64_t, int, struct nae_port_config *);
+void nlm_setup_tx_cal_cfg(uint64_t, int, struct nae_port_config *cfg);
+void nlm_deflate_frin_fifo_carving(uint64_t, int);
+void nlm_reset_nae(int);
+int nlm_set_nae_frequency(int, int);
+void nlm_setup_poe_class_config(uint64_t nae_base, int max_poe_classes,
+ int num_contexts, int *poe_cl_tbl);
+void nlm_setup_vfbid_mapping(uint64_t);
+void nlm_setup_flow_crc_poly(uint64_t, uint32_t);
+void nlm_setup_iface_fifo_cfg(uint64_t, int, struct nae_port_config *);
+void nlm_setup_rx_base_config(uint64_t, int, struct nae_port_config *);
+void nlm_setup_rx_buf_config(uint64_t, int, struct nae_port_config *);
+void nlm_setup_freein_fifo_cfg(uint64_t, struct nae_port_config *);
+int nlm_get_flow_mask(int);
+void nlm_program_flow_cfg(uint64_t, int, uint32_t, uint32_t);
+void xlp_ax_nae_lane_reset_txpll(uint64_t, int, int, int);
+void xlp_nae_lane_reset_txpll(uint64_t, int, int, int);
+void xlp_nae_config_lane_gmac(uint64_t, int);
+void config_egress_fifo_carvings(uint64_t, int, int, int, int,
+ struct nae_port_config *);
+void config_egress_fifo_credits(uint64_t, int, int, int, int,
+ struct nae_port_config *);
+void nlm_config_freein_fifo_uniq_cfg(uint64_t, int, int);
+void nlm_config_ucore_iface_mask_cfg(uint64_t, int, int);
+int nlm_nae_init_netior(uint64_t nae_base, int nblocks);
+void nlm_nae_init_ingress(uint64_t, uint32_t);
+void nlm_nae_init_egress(uint64_t);
+uint32_t ucore_spray_config(uint32_t, uint32_t, int);
+void nlm_nae_init_ucore(uint64_t nae_base, int if_num, uint32_t ucore_mask);
+int nlm_nae_open_if(uint64_t, int, int, int, uint32_t);
+void nlm_mac_enable(uint64_t, int, int, int);
+void nlm_mac_disable(uint64_t, int, int, int);
+uint64_t nae_tx_desc(u_int, u_int, u_int, u_int, uint64_t);
+void nlm_setup_l2type(uint64_t, int, uint32_t, uint32_t, uint32_t,
+ uint32_t, uint32_t, uint32_t);
+void nlm_setup_l3ctable_mask(uint64_t, int, uint32_t, uint32_t);
+void nlm_setup_l3ctable_even(uint64_t, int, uint32_t, uint32_t, uint32_t,
+ uint32_t, uint32_t);
+void nlm_setup_l3ctable_odd(uint64_t, int, uint32_t, uint32_t, uint32_t,
+ uint32_t, uint32_t, uint32_t);
+void nlm_setup_l4ctable_even(uint64_t, int, uint32_t, uint32_t, uint32_t,
+ uint32_t, uint32_t, uint32_t);
+void nlm_setup_l4ctable_odd(uint64_t, int, uint32_t, uint32_t, uint32_t, uint32_t);
+void nlm_enable_hardware_parser(uint64_t);
+void nlm_enable_hardware_parser_per_port(uint64_t, int, int);
+void nlm_prepad_enable(uint64_t, int);
+void nlm_setup_1588_timer(uint64_t, struct nae_port_config *);
+
+#endif /* !(LOCORE) && !(__ASSEMBLY__) */
+
+#endif
Property changes on: trunk/sys/mips/nlm/hal/nae.h
___________________________________________________________________
Added: svn:eol-style
## -0,0 +1 ##
+native
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## -0,0 +1 ##
+MidnightBSD=%H
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+text/plain
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Added: trunk/sys/mips/nlm/hal/nlm_hal.c
===================================================================
--- trunk/sys/mips/nlm/hal/nlm_hal.c (rev 0)
+++ trunk/sys/mips/nlm/hal/nlm_hal.c 2018-05-26 21:55:02 UTC (rev 9987)
@@ -0,0 +1,113 @@
+/* $MidnightBSD$ */
+/*-
+ * Copyright 2003-2011 Netlogic Microsystems (Netlogic). All rights
+ * reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in
+ * the documentation and/or other materials provided with the
+ * distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY Netlogic Microsystems ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL NETLOGIC OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
+ * THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * NETLOGIC_BSD */
+
+#include <sys/cdefs.h>
+__FBSDID("$FreeBSD: stable/10/sys/mips/nlm/hal/nlm_hal.c 255368 2013-09-07 18:26:16Z jchandra $");
+#include <sys/param.h>
+#include <sys/types.h>
+#include <sys/systm.h>
+
+#include <mips/nlm/hal/mips-extns.h>
+#include <mips/nlm/hal/haldefs.h>
+#include <mips/nlm/hal/iomap.h>
+#include <mips/nlm/hal/sys.h>
+#include <mips/nlm/xlp.h>
+
+uint32_t
+xlp_get_cpu_frequency(int node, int core)
+{
+ uint64_t sysbase = nlm_get_sys_regbase(node);
+ unsigned int pll_divf, pll_divr, dfs_div, ext_div;
+ unsigned int rstval, dfsval;
+
+ rstval = nlm_read_sys_reg(sysbase, SYS_POWER_ON_RESET_CFG);
+ dfsval = nlm_read_sys_reg(sysbase, SYS_CORE_DFS_DIV_VALUE);
+ pll_divf = ((rstval >> 10) & 0x7f) + 1;
+ pll_divr = ((rstval >> 8) & 0x3) + 1;
+ if (!nlm_is_xlp8xx_ax())
+ ext_div = ((rstval >> 30) & 0x3) + 1;
+ else
+ ext_div = 1;
+ dfs_div = ((dfsval >> (core << 2)) & 0xf) + 1;
+
+ return ((800000000ULL * pll_divf)/(3 * pll_divr * ext_div * dfs_div));
+}
+
+static u_int
+nlm_get_device_frequency(uint64_t sysbase, int devtype)
+{
+ uint32_t pllctrl, dfsdiv, spf, spr, div_val;
+ int extra_div;
+
+ pllctrl = nlm_read_sys_reg(sysbase, SYS_PLL_CTRL);
+ if (devtype <= 7)
+ div_val = nlm_read_sys_reg(sysbase, SYS_DFS_DIV_VALUE0);
+ else {
+ devtype -= 8;
+ div_val = nlm_read_sys_reg(sysbase, SYS_DFS_DIV_VALUE1);
+ }
+ dfsdiv = ((div_val >> (devtype << 2)) & 0xf) + 1;
+ spf = (pllctrl >> 3 & 0x7f) + 1;
+ spr = (pllctrl >> 1 & 0x03) + 1;
+ if (devtype == DFS_DEVICE_NAE && !nlm_is_xlp8xx_ax())
+ extra_div = 2;
+ else
+ extra_div = 1;
+
+ return ((400 * spf) / (3 * extra_div * spr * dfsdiv));
+}
+
+int
+nlm_set_device_frequency(int node, int devtype, int frequency)
+{
+ uint64_t sysbase;
+ u_int cur_freq;
+ int dec_div;
+
+ sysbase = nlm_get_sys_regbase(node);
+ cur_freq = nlm_get_device_frequency(sysbase, devtype);
+ if (cur_freq < (frequency - 5))
+ dec_div = 1;
+ else
+ dec_div = 0;
+
+ for(;;) {
+ if ((cur_freq >= (frequency - 5)) && (cur_freq <= frequency))
+ break;
+ if (dec_div)
+ nlm_write_sys_reg(sysbase, SYS_DFS_DIV_DEC_CTRL,
+ (1 << devtype));
+ else
+ nlm_write_sys_reg(sysbase, SYS_DFS_DIV_INC_CTRL,
+ (1 << devtype));
+ cur_freq = nlm_get_device_frequency(sysbase, devtype);
+ }
+ return (nlm_get_device_frequency(sysbase, devtype));
+}
Property changes on: trunk/sys/mips/nlm/hal/nlm_hal.c
___________________________________________________________________
Added: svn:eol-style
## -0,0 +1 ##
+native
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## -0,0 +1 ##
+MidnightBSD=%H
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+text/plain
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Added: trunk/sys/mips/nlm/hal/nlmsaelib.h
===================================================================
--- trunk/sys/mips/nlm/hal/nlmsaelib.h (rev 0)
+++ trunk/sys/mips/nlm/hal/nlmsaelib.h 2018-05-26 21:55:02 UTC (rev 9987)
@@ -0,0 +1,608 @@
+/* $MidnightBSD$ */
+/*-
+ * Copyright (c) 2003-2012 Broadcom Corporation
+ * All Rights Reserved
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in
+ * the documentation and/or other materials provided with the
+ * distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY BROADCOM ``AS IS'' AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL BROADCOM OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
+ * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
+ * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
+ * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * $FreeBSD: stable/10/sys/mips/nlm/hal/nlmsaelib.h 233541 2012-03-27 11:43:46Z jchandra $
+ */
+
+#ifndef _NLM_HAL_CRYPTO_H_
+#define _NLM_HAL_CRYPTO_H_
+
+#define SAE_CFG_REG 0x00
+#define SAE_ENG_SEL_0 0x01
+#define SAE_ENG_SEL_1 0x02
+#define SAE_ENG_SEL_2 0x03
+#define SAE_ENG_SEL_3 0x04
+#define SAE_ENG_SEL_4 0x05
+#define SAE_ENG_SEL_5 0x06
+#define SAE_ENG_SEL_6 0x07
+#define SAE_ENG_SEL_7 0x08
+
+#define RSA_CFG_REG 0x00
+#define RSA_ENG_SEL_0 0x01
+#define RSA_ENG_SEL_1 0x02
+#define RSA_ENG_SEL_2 0x03
+
+#define nlm_read_sec_reg(b, r) nlm_read_reg(b, r)
+#define nlm_write_sec_reg(b, r, v) nlm_write_reg(b, r, v)
+#define nlm_get_sec_pcibase(node) nlm_pcicfg_base(XLP_IO_SEC_OFFSET(node))
+#define nlm_get_sec_regbase(node) \
+ (nlm_get_sec_pcibase(node) + XLP_IO_PCI_HDRSZ)
+
+#define nlm_read_rsa_reg(b, r) nlm_read_reg(b, r)
+#define nlm_write_rsa_reg(b, r, v) nlm_write_reg(b, r, v)
+#define nlm_get_rsa_pcibase(node) nlm_pcicfg_base(XLP_IO_RSA_OFFSET(node))
+#define nlm_get_rsa_regbase(node) \
+ (nlm_get_rsa_pcibase(node) + XLP_IO_PCI_HDRSZ)
+
+#define nlm_pcibase_sec(node) nlm_pcicfg_base(XLP_IO_SEC_OFFSET(node))
+#define nlm_qidstart_sec(node) nlm_qidstart_kseg(nlm_pcibase_sec(node))
+#define nlm_qnum_sec(node) nlm_qnum_kseg(nlm_pcibase_sec(node))
+
+/*
+ * Since buffer allocation for crypto at kernel is done as malloc, each
+ * segment size is given as page size which is 4K by default
+ */
+#define NLM_CRYPTO_MAX_SEG_LEN PAGE_SIZE
+
+#define MAX_KEY_LEN_IN_DW 20
+
+#define left_shift64(x, bitshift, numofbits) \
+ ((uint64_t)(x) << (bitshift))
+
+#define left_shift64_mask(x, bitshift, numofbits) \
+ (((uint64_t)(x) & ((1ULL << (numofbits)) - 1)) << (bitshift))
+
+/**
+* @brief cipher algorithms
+* @ingroup crypto
+*/
+enum nlm_cipher_algo {
+ NLM_CIPHER_BYPASS = 0,
+ NLM_CIPHER_DES = 1,
+ NLM_CIPHER_3DES = 2,
+ NLM_CIPHER_AES128 = 3,
+ NLM_CIPHER_AES192 = 4,
+ NLM_CIPHER_AES256 = 5,
+ NLM_CIPHER_ARC4 = 6,
+ NLM_CIPHER_KASUMI_F8 = 7,
+ NLM_CIPHER_SNOW3G_F8 = 8,
+ NLM_CIPHER_CAMELLIA128 = 9,
+ NLM_CIPHER_CAMELLIA192 = 0xA,
+ NLM_CIPHER_CAMELLIA256 = 0xB,
+ NLM_CIPHER_MAX = 0xC,
+};
+
+/**
+* @brief cipher modes
+* @ingroup crypto
+*/
+enum nlm_cipher_mode {
+ NLM_CIPHER_MODE_ECB = 0,
+ NLM_CIPHER_MODE_CBC = 1,
+ NLM_CIPHER_MODE_CFB = 2,
+ NLM_CIPHER_MODE_OFB = 3,
+ NLM_CIPHER_MODE_CTR = 4,
+ NLM_CIPHER_MODE_AES_F8 = 5,
+ NLM_CIPHER_MODE_GCM = 6,
+ NLM_CIPHER_MODE_CCM = 7,
+ NLM_CIPHER_MODE_UNDEFINED1 = 8,
+ NLM_CIPHER_MODE_UNDEFINED2 = 9,
+ NLM_CIPHER_MODE_LRW = 0xA,
+ NLM_CIPHER_MODE_XTS = 0xB,
+ NLM_CIPHER_MODE_MAX = 0xC,
+};
+
+/**
+* @brief hash algorithms
+* @ingroup crypto
+*/
+enum nlm_hash_algo {
+ NLM_HASH_BYPASS = 0,
+ NLM_HASH_MD5 = 1,
+ NLM_HASH_SHA = 2,
+ NLM_HASH_UNDEFINED = 3,
+ NLM_HASH_AES128 = 4,
+ NLM_HASH_AES192 = 5,
+ NLM_HASH_AES256 = 6,
+ NLM_HASH_KASUMI_F9 = 7,
+ NLM_HASH_SNOW3G_F9 = 8,
+ NLM_HASH_CAMELLIA128 = 9,
+ NLM_HASH_CAMELLIA192 = 0xA,
+ NLM_HASH_CAMELLIA256 = 0xB,
+ NLM_HASH_GHASH = 0xC,
+ NLM_HASH_MAX = 0xD
+};
+
+/**
+* @brief hash modes
+* @ingroup crypto
+*/
+enum nlm_hash_mode {
+ NLM_HASH_MODE_SHA1 = 0, /* Only SHA */
+ NLM_HASH_MODE_SHA224 = 1, /* Only SHA */
+ NLM_HASH_MODE_SHA256 = 2, /* Only SHA */
+ NLM_HASH_MODE_SHA384 = 3, /* Only SHA */
+ NLM_HASH_MODE_SHA512 = 4, /* Only SHA */
+ NLM_HASH_MODE_CMAC = 5, /* AES and Camellia */
+ NLM_HASH_MODE_XCBC = 6, /* AES and Camellia */
+ NLM_HASH_MODE_CBC_MAC = 7, /* AES and Camellia */
+ NLM_HASH_MODE_CCM = 8, /* AES */
+ NLM_HASH_MODE_GCM = 9, /* AES */
+ NLM_HASH_MODE_MAX = 0xA,
+};
+
+/**
+* @brief crypto control descriptor, should be cache aligned
+* @ingroup crypto
+*/
+struct nlm_crypto_pkt_ctrl {
+ uint64_t desc0;
+ /* combination of cipher and hash keys */
+ uint64_t key[MAX_KEY_LEN_IN_DW];
+ uint32_t cipherkeylen;
+ uint32_t hashkeylen;
+ uint32_t taglen;
+};
+
+/**
+* @brief crypto packet descriptor, should be cache aligned
+* @ingroup crypto
+*/
+struct nlm_crypto_pkt_param {
+ uint64_t desc0;
+ uint64_t desc1;
+ uint64_t desc2;
+ uint64_t desc3;
+ uint64_t segment[1][2];
+};
+
+static __inline__ uint64_t
+nlm_crypto_form_rsa_ecc_fmn_entry0(unsigned int l3alloc, unsigned int type,
+ unsigned int func, uint64_t srcaddr)
+{
+ return (left_shift64(l3alloc, 61, 1) |
+ left_shift64(type, 46, 7) |
+ left_shift64(func, 40, 6) |
+ left_shift64(srcaddr, 0, 40));
+}
+
+static __inline__ uint64_t
+nlm_crypto_form_rsa_ecc_fmn_entry1(unsigned int dstclobber,
+ unsigned int l3alloc, unsigned int fbvc, uint64_t dstaddr)
+{
+ return (left_shift64(dstclobber, 62, 1) |
+ left_shift64(l3alloc, 61, 1) |
+ left_shift64(fbvc, 40, 12) |
+ left_shift64(dstaddr, 0, 40));
+}
+
+/**
+* @brief Generate cypto control descriptor
+* @ingroup crypto
+* hmac : 1 for hash with hmac
+* hashalg, see hash_alg enums
+* hashmode, see hash_mode enums
+* cipherhalg, see cipher_alg enums
+* ciphermode, see cipher_mode enums
+* arc4_cipherkeylen : length of arc4 cipher key, 0 is interpreted as 32
+* arc4_keyinit :
+* cfbmask : cipher text for feedback,
+* 0(1 bit), 1(2 bits), 2(4 bits), 3(8 bits), 4(16bits), 5(32 bits),
+* 6(64 bits), 7(128 bits)
+*/
+static __inline__ uint64_t
+nlm_crypto_form_pkt_ctrl_desc(unsigned int hmac, unsigned int hashalg,
+ unsigned int hashmode, unsigned int cipheralg, unsigned int ciphermode,
+ unsigned int arc4_cipherkeylen, unsigned int arc4_keyinit,
+ unsigned int cfbmask)
+{
+ return (left_shift64(hmac, 61, 1) |
+ left_shift64(hashalg, 52, 8) |
+ left_shift64(hashmode, 43, 8) |
+ left_shift64(cipheralg, 34, 8) |
+ left_shift64(ciphermode, 25, 8) |
+ left_shift64(arc4_cipherkeylen, 18, 5) |
+ left_shift64(arc4_keyinit, 17, 1) |
+ left_shift64(cfbmask, 0, 3));
+}
+/**
+* @brief Generate cypto packet descriptor 0
+* @ingroup crypto
+* tls : 1 (tls enabled) 0(tls disabled)
+* hash_source : 1 (encrypted data is sent to the auth engine)
+* 0 (plain data is sent to the auth engine)
+* hashout_l3alloc : 1 (auth output is transited through l3 cache)
+* encrypt : 1 (for encrypt) 0 (for decrypt)
+* ivlen : iv length in bytes
+* hashdst_addr : hash out physical address, byte aligned
+*/
+static __inline__ uint64_t
+nlm_crypto_form_pkt_desc0(unsigned int tls, unsigned int hash_source,
+ unsigned int hashout_l3alloc, unsigned int encrypt, unsigned int ivlen,
+ uint64_t hashdst_addr)
+{
+ return (left_shift64(tls, 63, 1) |
+ left_shift64(hash_source, 62, 1) |
+ left_shift64(hashout_l3alloc, 60, 1) |
+ left_shift64(encrypt, 59, 1) |
+ left_shift64_mask((ivlen - 1), 41, 16) |
+ left_shift64(hashdst_addr, 0, 40));
+}
+
+/**
+* @brief Generate cypto packet descriptor 1
+* @ingroup crypto
+* cipherlen : cipher length in bytes
+* hashlen : hash length in bytes
+*/
+static __inline__ uint64_t
+nlm_crypto_form_pkt_desc1(unsigned int cipherlen, unsigned int hashlen)
+{
+ return (left_shift64_mask((cipherlen - 1), 32, 32) |
+ left_shift64_mask((hashlen - 1), 0, 32));
+}
+
+/**
+* @brief Generate cypto packet descriptor 2
+* @ingroup crypto
+* ivoff : iv offset, offset from start of src data addr
+* ciperbit_cnt : number of valid bits in the last input byte to the cipher,
+* 0 (8 bits), 1 (1 bit)..7 (7 bits)
+* cipheroff : cipher offset, offset from start of src data addr
+* hashbit_cnt : number of valid bits in the last input byte to the auth
+* 0 (8 bits), 1 (1 bit)..7 (7 bits)
+* hashclobber : 1 (hash output will be written as multiples of cachelines, no
+* read modify write)
+* hashoff : hash offset, offset from start of src data addr
+*/
+
+static __inline__ uint64_t
+nlm_crypto_form_pkt_desc2(unsigned int ivoff, unsigned int cipherbit_cnt,
+ unsigned int cipheroff, unsigned int hashbit_cnt, unsigned int hashclobber,
+ unsigned int hashoff)
+{
+ return (left_shift64(ivoff , 45, 16) |
+ left_shift64(cipherbit_cnt, 42, 3) |
+ left_shift64(cipheroff, 22, 16) |
+ left_shift64(hashbit_cnt, 19, 3) |
+ left_shift64(hashclobber, 18, 1) |
+ left_shift64(hashoff, 0, 16));
+}
+
+/**
+* @brief Generate cypto packet descriptor 3
+* @ingroup crypto
+* designer_vc : designer freeback fmn destination id
+* taglen : length in bits of the tag generated by the auth engine
+* md5 (128 bits), sha1 (160), sha224 (224), sha384 (384),
+* sha512 (512), Kasumi (32), snow3g (32), gcm (128)
+* hmacpad : 1 if hmac padding is already done
+*/
+static __inline__ uint64_t
+nlm_crypto_form_pkt_desc3(unsigned int designer_vc, unsigned int taglen,
+ unsigned int arc4_state_save_l3, unsigned int arc4_save_state,
+ unsigned int hmacpad)
+{
+ return (left_shift64(designer_vc, 48, 16) |
+ left_shift64(taglen, 11, 16) |
+ left_shift64(arc4_state_save_l3, 8, 1) |
+ left_shift64(arc4_save_state, 6, 1) |
+ left_shift64(hmacpad, 5, 1));
+}
+
+/**
+* @brief Generate cypto packet descriptor 4
+* @ingroup crypto
+* srcfraglen : length of the source fragment(header + data + tail) in bytes
+* srcfragaddr : physical address of the srouce fragment
+*/
+static __inline__ uint64_t
+nlm_crypto_form_pkt_desc4(uint64_t srcfraglen,
+ unsigned int srcfragaddr )
+{
+ return (left_shift64_mask((srcfraglen - 1), 48, 16) |
+ left_shift64(srcfragaddr, 0, 40));
+}
+
+/**
+* @brief Generate cypto packet descriptor 5
+* @ingroup crypto
+* dstfraglen : length of the dst fragment(header + data + tail) in bytes
+* chipherout_l3alloc : 1(cipher output is transited through l3 cache)
+* cipherclobber : 1 (cipher output will be written as multiples of cachelines,
+* no read modify write)
+* chiperdst_addr : physical address of the cipher destination address
+*/
+static __inline__ uint64_t
+nlm_crypto_form_pkt_desc5(unsigned int dstfraglen,
+ unsigned int cipherout_l3alloc, unsigned int cipherclobber,
+ uint64_t cipherdst_addr)
+
+{
+ return (left_shift64_mask((dstfraglen - 1), 48, 16) |
+ left_shift64(cipherout_l3alloc, 46, 1) |
+ left_shift64(cipherclobber, 41, 1) |
+ left_shift64(cipherdst_addr, 0, 40));
+}
+
+/**
+ * @brief Generate crypto packet fmn message entry 0
+ * @ingroup crypto
+ * freeback_vc: freeback response destination address
+ * designer_fblen : Designer freeback length, 1 - 4
+ * designerdesc_valid : designer desc valid or not
+ * cipher_keylen : cipher key length in bytes
+ * ctrldesc_addr : physicall address of the control descriptor
+ */
+static __inline__ uint64_t
+nlm_crypto_form_pkt_fmn_entry0(unsigned int freeback_vc,
+ unsigned int designer_fblen, unsigned int designerdesc_valid,
+ unsigned int cipher_keylen, uint64_t cntldesc_addr)
+{
+ return (left_shift64(freeback_vc, 48, 16) |
+ left_shift64_mask(designer_fblen - 1, 46, 2) |
+ left_shift64(designerdesc_valid, 45, 1) |
+ left_shift64_mask(((cipher_keylen + 7) >> 3), 40, 5) |
+ left_shift64(cntldesc_addr >> 6, 0, 34));
+}
+
+/**
+ * @brief Generate crypto packet fmn message entry 1
+ * @ingroup crypto
+ * arc4load_state : 1 if load state required 0 otherwise
+ * hash_keylen : hash key length in bytes
+ * pktdesc_size : packet descriptor size in bytes
+ * pktdesc_addr : physicall address of the packet descriptor
+ */
+static __inline__ uint64_t
+nlm_crypto_form_pkt_fmn_entry1(unsigned int arc4load_state,
+ unsigned int hash_keylen, unsigned int pktdesc_size,
+ uint64_t pktdesc_addr)
+{
+ return (left_shift64(arc4load_state, 63, 1) |
+ left_shift64_mask(((hash_keylen + 7) >> 3), 56, 5) |
+ left_shift64_mask(((pktdesc_size >> 4) - 1), 43, 12) |
+ left_shift64(pktdesc_addr >> 6, 0, 34));
+}
+
+static __inline__ int
+nlm_crypto_get_hklen_taglen(enum nlm_hash_algo hashalg,
+ enum nlm_hash_mode hashmode, unsigned int *taglen, unsigned int *hklen)
+{
+ if (hashalg == NLM_HASH_MD5) {
+ *taglen = 128;
+ *hklen = 64;
+ } else if (hashalg == NLM_HASH_SHA) {
+ switch (hashmode) {
+ case NLM_HASH_MODE_SHA1:
+ *taglen = 160;
+ *hklen = 64;
+ break;
+ case NLM_HASH_MODE_SHA224:
+ *taglen = 224;
+ *hklen = 64;
+ break;
+ case NLM_HASH_MODE_SHA256:
+ *taglen = 256;
+ *hklen = 64;
+ break;
+ case NLM_HASH_MODE_SHA384:
+ *taglen = 384;
+ *hklen = 128;
+ break;
+ case NLM_HASH_MODE_SHA512:
+ *taglen = 512;
+ *hklen = 128;
+ break;
+ default:
+ printf("Error : invalid shaid (%s)\n", __func__);
+ return (-1);
+ }
+ } else if (hashalg == NLM_HASH_KASUMI_F9) {
+ *taglen = 32;
+ *hklen = 0;
+ } else if (hashalg == NLM_HASH_SNOW3G_F9) {
+ *taglen = 32;
+ *hklen = 0;
+ } else if (hashmode == NLM_HASH_MODE_XCBC) {
+ *taglen = 128;
+ *hklen = 0;
+ } else if (hashmode == NLM_HASH_MODE_GCM) {
+ *taglen = 128;
+ *hklen = 0;
+ } else if (hashalg == NLM_HASH_BYPASS) {
+ *taglen = 0;
+ *hklen = 0;
+ } else {
+ printf("Error:Hash alg/mode not found\n");
+ return (-1);
+ }
+
+ /* TODO : Add remaining cases */
+ return (0);
+}
+
+/**
+* @brief Generate fill cryto control info structure
+* @ingroup crypto
+* hmac : 1 for hash with hmac
+* hashalg: see above, hash_alg enums
+* hashmode: see above, hash_mode enums
+* cipherhalg: see above, cipher_alg enums
+* ciphermode: see above, cipher_mode enums
+*
+*/
+static __inline__ int
+nlm_crypto_fill_pkt_ctrl(struct nlm_crypto_pkt_ctrl *ctrl, unsigned int hmac,
+ enum nlm_hash_algo hashalg, enum nlm_hash_mode hashmode,
+ enum nlm_cipher_algo cipheralg, enum nlm_cipher_mode ciphermode,
+ unsigned char *cipherkey, unsigned int cipherkeylen,
+ unsigned char *hashkey, unsigned int hashkeylen)
+{
+ unsigned int taglen = 0, hklen = 0;
+
+ ctrl->desc0 = nlm_crypto_form_pkt_ctrl_desc(hmac, hashalg, hashmode,
+ cipheralg, ciphermode, 0, 0, 0);
+ memset(ctrl->key, 0, sizeof(ctrl->key));
+ if (cipherkey)
+ memcpy(ctrl->key, cipherkey, cipherkeylen);
+ if (hashkey)
+ memcpy((unsigned char *)&ctrl->key[(cipherkeylen + 7) / 8],
+ hashkey, hashkeylen);
+ if (nlm_crypto_get_hklen_taglen(hashalg, hashmode, &taglen, &hklen)
+ < 0)
+ return (-1);
+
+ ctrl->cipherkeylen = cipherkeylen;
+ ctrl->hashkeylen = hklen;
+ ctrl->taglen = taglen;
+
+ /* TODO : add the invalid checks and return error */
+ return (0);
+}
+
+/**
+* @brief Top level function for generation pkt desc 0 to 3 for cipher auth
+* @ingroup crypto
+* ctrl : pointer to control structure
+* param : pointer to the param structure
+* encrypt : 1(for encrypt) 0(for decrypt)
+* hash_source : 1(encrypted data is sent to the auth engine) 0(plain data is
+* sent to the auth engine)
+* ivoff : iv offset from start of data
+* ivlen : iv length in bytes
+* hashoff : hash offset from start of data
+* hashlen : hash length in bytes
+* hmacpad : hmac padding required or not, 1 if already padded
+* cipheroff : cipher offset from start of data
+* cipherlen : cipher length in bytes
+* hashdst_addr : hash destination physical address
+*/
+static __inline__ void
+nlm_crypto_fill_cipher_auth_pkt_param(struct nlm_crypto_pkt_ctrl *ctrl,
+ struct nlm_crypto_pkt_param *param, unsigned int encrypt,
+ unsigned int hash_source, unsigned int ivoff, unsigned int ivlen,
+ unsigned int hashoff, unsigned int hashlen, unsigned int hmacpad,
+ unsigned int cipheroff, unsigned int cipherlen, unsigned char *hashdst_addr)
+{
+ param->desc0 = nlm_crypto_form_pkt_desc0(0, hash_source, 1, encrypt,
+ ivlen, vtophys(hashdst_addr));
+ param->desc1 = nlm_crypto_form_pkt_desc1(cipherlen, hashlen);
+ param->desc2 = nlm_crypto_form_pkt_desc2(ivoff, 0, cipheroff, 0, 0,
+ hashoff);
+ param->desc3 = nlm_crypto_form_pkt_desc3(0, ctrl->taglen, 0, 0,
+ hmacpad);
+}
+
+/**
+* @brief Top level function for generation pkt desc 0 to 3 for cipher operation
+* @ingroup crypto
+* ctrl : pointer to control structure
+* param : pointer to the param structure
+* encrypt : 1(for encrypt) 0(for decrypt)
+* ivoff : iv offset from start of data
+* ivlen : iv length in bytes
+* cipheroff : cipher offset from start of data
+* cipherlen : cipher length in bytes
+*/
+
+
+static __inline__ void
+nlm_crypto_fill_cipher_pkt_param(struct nlm_crypto_pkt_ctrl *ctrl,
+ struct nlm_crypto_pkt_param *param, unsigned int encrypt,
+ unsigned int ivoff, unsigned int ivlen, unsigned int cipheroff,
+ unsigned int cipherlen)
+{
+ param->desc0 = nlm_crypto_form_pkt_desc0(0, 0, 0, encrypt, ivlen, 0ULL);
+ param->desc1 = nlm_crypto_form_pkt_desc1(cipherlen, 1);
+ param->desc2 = nlm_crypto_form_pkt_desc2(ivoff, 0, cipheroff, 0, 0, 0);
+ param->desc3 = nlm_crypto_form_pkt_desc3(0, ctrl->taglen, 0, 0, 0);
+}
+
+/**
+* @brief Top level function for generation pkt desc 0 to 3 for auth operation
+* @ingroup crypto
+* ctrl : pointer to control structure
+* param : pointer to the param structure
+* hashoff : hash offset from start of data
+* hashlen : hash length in bytes
+* hmacpad : hmac padding required or not, 1 if already padded
+* hashdst_addr : hash destination physical address
+*/
+static __inline__ void
+nlm_crypto_fill_auth_pkt_param(struct nlm_crypto_pkt_ctrl *ctrl,
+ struct nlm_crypto_pkt_param *param, unsigned int hashoff,
+ unsigned int hashlen, unsigned int hmacpad, unsigned char *hashdst_addr)
+{
+ param->desc0 = nlm_crypto_form_pkt_desc0(0, 0, 1, 0, 1,
+ vtophys(hashdst_addr));
+ param->desc1 = nlm_crypto_form_pkt_desc1(1, hashlen);
+ param->desc2 = nlm_crypto_form_pkt_desc2(0, 0, 0, 0, 0, hashoff);
+ param->desc3 = nlm_crypto_form_pkt_desc3(0, ctrl->taglen, 0, 0,
+ hmacpad);
+}
+
+static __inline__ unsigned int
+nlm_crypto_fill_src_seg(struct nlm_crypto_pkt_param *param, int seg,
+ unsigned char *input, unsigned int inlen)
+{
+ unsigned off = 0, len = 0;
+ unsigned int remlen = inlen;
+
+ for (; remlen > 0;) {
+ len = remlen > NLM_CRYPTO_MAX_SEG_LEN ?
+ NLM_CRYPTO_MAX_SEG_LEN : remlen;
+ param->segment[seg][0] = nlm_crypto_form_pkt_desc4(len,
+ vtophys(input + off));
+ remlen -= len;
+ off += len;
+ seg++;
+ }
+ return (seg);
+}
+
+static __inline__ unsigned int
+nlm_crypto_fill_dst_seg(struct nlm_crypto_pkt_param *param,
+ int seg, unsigned char *output, unsigned int outlen)
+{
+ unsigned off = 0, len = 0;
+ unsigned int remlen = outlen;
+
+ for (; remlen > 0;) {
+ len = remlen > NLM_CRYPTO_MAX_SEG_LEN ?
+ NLM_CRYPTO_MAX_SEG_LEN : remlen;
+ param->segment[seg][1] = nlm_crypto_form_pkt_desc5(len, 1, 0,
+ vtophys(output + off));
+ remlen -= len;
+ off += len;
+ seg++;
+ }
+ return (seg);
+}
+
+#endif
Property changes on: trunk/sys/mips/nlm/hal/nlmsaelib.h
___________________________________________________________________
Added: svn:eol-style
## -0,0 +1 ##
+native
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## -0,0 +1 ##
+MidnightBSD=%H
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## -0,0 +1 ##
+text/plain
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Added: trunk/sys/mips/nlm/hal/pcibus.h
===================================================================
--- trunk/sys/mips/nlm/hal/pcibus.h (rev 0)
+++ trunk/sys/mips/nlm/hal/pcibus.h 2018-05-26 21:55:02 UTC (rev 9987)
@@ -0,0 +1,122 @@
+/* $MidnightBSD$ */
+/*-
+ * Copyright 2003-2011 Netlogic Microsystems (Netlogic). All rights
+ * reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in
+ * the documentation and/or other materials provided with the
+ * distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY Netlogic Microsystems ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL NETLOGIC OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
+ * THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * NETLOGIC_BSD
+ * $FreeBSD: stable/10/sys/mips/nlm/hal/pcibus.h 233563 2012-03-27 15:39:55Z jchandra $
+ */
+
+#ifndef __XLP_PCIBUS_H__
+#define __XLP_PCIBUS_H__
+
+#define MSI_MIPS_ADDR_BASE 0xfee00000
+/* MSI support */
+#define MSI_MIPS_ADDR_DEST 0x000ff000
+#define MSI_MIPS_ADDR_RH 0x00000008
+#define MSI_MIPS_ADDR_RH_OFF 0x00000000
+#define MSI_MIPS_ADDR_RH_ON 0x00000008
+#define MSI_MIPS_ADDR_DM 0x00000004
+#define MSI_MIPS_ADDR_DM_PHYSICAL 0x00000000
+#define MSI_MIPS_ADDR_DM_LOGICAL 0x00000004
+
+/* Fields in data for Intel MSI messages. */
+#define MSI_MIPS_DATA_TRGRMOD 0x00008000 /* Trigger mode */
+#define MSI_MIPS_DATA_TRGREDG 0x00000000 /* edge */
+#define MSI_MIPS_DATA_TRGRLVL 0x00008000 /* level */
+
+#define MSI_MIPS_DATA_LEVEL 0x00004000 /* Polarity. */
+#define MSI_MIPS_DATA_DEASSERT 0x00000000
+#define MSI_MIPS_DATA_ASSERT 0x00004000
+
+#define MSI_MIPS_DATA_DELMOD 0x00000700 /* Delivery Mode */
+#define MSI_MIPS_DATA_DELFIXED 0x00000000 /* fixed */
+#define MSI_MIPS_DATA_DELLOPRI 0x00000100 /* lowest priority */
+
+#define MSI_MIPS_DATA_INTVEC 0x000000ff
+
+/* PCIE Memory and IO regions */
+#define PCIE_MEM_BASE 0xd0000000ULL
+#define PCIE_MEM_LIMIT 0xdfffffffULL
+#define PCIE_IO_BASE 0x14000000ULL
+#define PCIE_IO_LIMIT 0x15ffffffULL
+
+#define PCIE_BRIDGE_CMD 0x1
+#define PCIE_BRIDGE_MSI_CAP 0x14
+#define PCIE_BRIDGE_MSI_ADDRL 0x15
+#define PCIE_BRIDGE_MSI_ADDRH 0x16
+#define PCIE_BRIDGE_MSI_DATA 0x17
+
+/* XLP Global PCIE configuration space registers */
+#define PCIE_BYTE_SWAP_MEM_BASE 0x247
+#define PCIE_BYTE_SWAP_MEM_LIM 0x248
+#define PCIE_BYTE_SWAP_IO_BASE 0x249
+#define PCIE_BYTE_SWAP_IO_LIM 0x24A
+#define PCIE_MSI_STATUS 0x25A
+#define PCIE_MSI_EN 0x25B
+#define PCIE_INT_EN0 0x261
+
+/* PCIE_MSI_EN */
+#define PCIE_MSI_VECTOR_INT_EN 0xFFFFFFFF
+
+/* PCIE_INT_EN0 */
+#define PCIE_MSI_INT_EN (1 << 9)
+
+/* XXXJC: Ax workaround */
+#define PCIE_LINK0_IRT 78
+
+#if !defined(LOCORE) && !defined(__ASSEMBLY__)
+
+#define nlm_read_pcie_reg(b, r) nlm_read_reg(b, r)
+#define nlm_write_pcie_reg(b, r, v) nlm_write_reg(b, r, v)
+#define nlm_get_pcie_base(node, inst) \
+ nlm_pcicfg_base(XLP_IO_PCIE_OFFSET(node, inst))
+#define nlm_get_pcie_regbase(node, inst) \
+ (nlm_get_pcie_base(node, inst) + XLP_IO_PCI_HDRSZ)
+
+static __inline int
+xlp_pcie_link_irt(int link)
+{
+ if ((link < 0) || (link > 3))
+ return (-1);
+
+ return (PCIE_LINK0_IRT + link);
+}
+
+/*
+ * Build Intel MSI message and data values from a source. AMD64 systems
+ * seem to be compatible, so we use the same function for both.
+ */
+#define MIPS_MSI_ADDR(cpu) \
+ (MSI_MIPS_ADDR_BASE | (cpu) << 12 | \
+ MSI_MIPS_ADDR_RH_OFF | MSI_MIPS_ADDR_DM_PHYSICAL)
+
+#define MIPS_MSI_DATA(irq) \
+ (MSI_MIPS_DATA_TRGRLVL | MSI_MIPS_DATA_DELFIXED | \
+ MSI_MIPS_DATA_ASSERT | (irq))
+
+#endif
+#endif /* __XLP_PCIBUS_H__ */
Property changes on: trunk/sys/mips/nlm/hal/pcibus.h
___________________________________________________________________
Added: svn:eol-style
## -0,0 +1 ##
+native
\ No newline at end of property
Added: svn:keywords
## -0,0 +1 ##
+MidnightBSD=%H
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+text/plain
\ No newline at end of property
Added: trunk/sys/mips/nlm/hal/pic.h
===================================================================
--- trunk/sys/mips/nlm/hal/pic.h (rev 0)
+++ trunk/sys/mips/nlm/hal/pic.h 2018-05-26 21:55:02 UTC (rev 9987)
@@ -0,0 +1,317 @@
+/* $MidnightBSD$ */
+/*-
+ * Copyright 2003-2011 Netlogic Microsystems (Netlogic). All rights
+ * reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in
+ * the documentation and/or other materials provided with the
+ * distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY Netlogic Microsystems ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL NETLOGIC OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
+ * THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * NETLOGIC_BSD
+ * $FreeBSD: stable/10/sys/mips/nlm/hal/pic.h 233563 2012-03-27 15:39:55Z jchandra $
+ */
+
+#ifndef _NLM_HAL_PIC_H
+#define _NLM_HAL_PIC_H
+
+/* PIC Specific registers */
+#define PIC_CTRL 0x00
+
+/* PIC control register defines */
+#define PIC_CTRL_ITV 32 /* interrupt timeout value */
+#define PIC_CTRL_ICI 19 /* ICI interrupt timeout enable */
+#define PIC_CTRL_ITE 18 /* interrupt timeout enable */
+#define PIC_CTRL_STE 10 /* system timer interrupt enable */
+#define PIC_CTRL_WWR1 8 /* watchdog 1 wraparound count for reset */
+#define PIC_CTRL_WWR0 6 /* watchdog 0 wraparound count for reset */
+#define PIC_CTRL_WWN1 4 /* watchdog 1 wraparound count for NMI */
+#define PIC_CTRL_WWN0 2 /* watchdog 0 wraparound count for NMI */
+#define PIC_CTRL_WTE 0 /* watchdog timer enable */
+
+/* PIC Status register defines */
+#define PIC_ICI_STATUS 33 /* ICI interrupt timeout status */
+#define PIC_ITE_STATUS 32 /* interrupt timeout status */
+#define PIC_STS_STATUS 4 /* System timer interrupt status */
+#define PIC_WNS_STATUS 2 /* NMI status for watchdog timers */
+#define PIC_WIS_STATUS 0 /* Interrupt status for watchdog timers */
+
+/* PIC IPI control register offsets */
+#define PIC_IPICTRL_NMI 32
+#define PIC_IPICTRL_RIV 20 /* received interrupt vector */
+#define PIC_IPICTRL_IDB 16 /* interrupt destination base */
+#define PIC_IPICTRL_DTE 0 /* interrupt destination thread enables */
+
+/* PIC IRT register offsets */
+#define PIC_IRT_ENABLE 31
+#define PIC_IRT_NMI 29
+#define PIC_IRT_SCH 28 /* Scheduling scheme */
+#define PIC_IRT_RVEC 20 /* Interrupt receive vectors */
+#define PIC_IRT_DT 19 /* Destination type */
+#define PIC_IRT_DB 16 /* Destination base */
+#define PIC_IRT_DTE 0 /* Destination thread enables */
+
+#define PIC_BYTESWAP 0x02
+#define PIC_STATUS 0x04
+#define PIC_INTR_TIMEOUT 0x06
+#define PIC_ICI0_INTR_TIMEOUT 0x08
+#define PIC_ICI1_INTR_TIMEOUT 0x0a
+#define PIC_ICI2_INTR_TIMEOUT 0x0c
+#define PIC_IPI_CTL 0x0e
+#define PIC_INT_ACK 0x10
+#define PIC_INT_PENDING0 0x12
+#define PIC_INT_PENDING1 0x14
+#define PIC_INT_PENDING2 0x16
+
+#define PIC_WDOG0_MAXVAL 0x18
+#define PIC_WDOG0_COUNT 0x1a
+#define PIC_WDOG0_ENABLE0 0x1c
+#define PIC_WDOG0_ENABLE1 0x1e
+#define PIC_WDOG0_BEATCMD 0x20
+#define PIC_WDOG0_BEAT0 0x22
+#define PIC_WDOG0_BEAT1 0x24
+
+#define PIC_WDOG1_MAXVAL 0x26
+#define PIC_WDOG1_COUNT 0x28
+#define PIC_WDOG1_ENABLE0 0x2a
+#define PIC_WDOG1_ENABLE1 0x2c
+#define PIC_WDOG1_BEATCMD 0x2e
+#define PIC_WDOG1_BEAT0 0x30
+#define PIC_WDOG1_BEAT1 0x32
+
+#define PIC_WDOG_MAXVAL(i) (PIC_WDOG0_MAXVAL + ((i) ? 7 : 0))
+#define PIC_WDOG_COUNT(i) (PIC_WDOG0_COUNT + ((i) ? 7 : 0))
+#define PIC_WDOG_ENABLE0(i) (PIC_WDOG0_ENABLE0 + ((i) ? 7 : 0))
+#define PIC_WDOG_ENABLE1(i) (PIC_WDOG0_ENABLE1 + ((i) ? 7 : 0))
+#define PIC_WDOG_BEATCMD(i) (PIC_WDOG0_BEATCMD + ((i) ? 7 : 0))
+#define PIC_WDOG_BEAT0(i) (PIC_WDOG0_BEAT0 + ((i) ? 7 : 0))
+#define PIC_WDOG_BEAT1(i) (PIC_WDOG0_BEAT1 + ((i) ? 7 : 0))
+
+#define PIC_TIMER0_MAXVAL 0x34
+#define PIC_TIMER1_MAXVAL 0x36
+#define PIC_TIMER2_MAXVAL 0x38
+#define PIC_TIMER3_MAXVAL 0x3a
+#define PIC_TIMER4_MAXVAL 0x3c
+#define PIC_TIMER5_MAXVAL 0x3e
+#define PIC_TIMER6_MAXVAL 0x40
+#define PIC_TIMER7_MAXVAL 0x42
+#define PIC_TIMER_MAXVAL(i) (PIC_TIMER0_MAXVAL + ((i) * 2))
+
+#define PIC_TIMER0_COUNT 0x44
+#define PIC_TIMER1_COUNT 0x46
+#define PIC_TIMER2_COUNT 0x48
+#define PIC_TIMER3_COUNT 0x4a
+#define PIC_TIMER4_COUNT 0x4c
+#define PIC_TIMER5_COUNT 0x4e
+#define PIC_TIMER6_COUNT 0x50
+#define PIC_TIMER7_COUNT 0x52
+#define PIC_TIMER_COUNT(i) (PIC_TIMER0_COUNT + ((i) * 2))
+
+#define PIC_ITE0_N0_N1 0x54
+#define PIC_ITE1_N0_N1 0x58
+#define PIC_ITE2_N0_N1 0x5c
+#define PIC_ITE3_N0_N1 0x60
+#define PIC_ITE4_N0_N1 0x64
+#define PIC_ITE5_N0_N1 0x68
+#define PIC_ITE6_N0_N1 0x6c
+#define PIC_ITE7_N0_N1 0x70
+#define PIC_ITE_N0_N1(i) (PIC_ITE0_N0_N1 + ((i) * 4))
+
+#define PIC_ITE0_N2_N3 0x56
+#define PIC_ITE1_N2_N3 0x5a
+#define PIC_ITE2_N2_N3 0x5e
+#define PIC_ITE3_N2_N3 0x62
+#define PIC_ITE4_N2_N3 0x66
+#define PIC_ITE5_N2_N3 0x6a
+#define PIC_ITE6_N2_N3 0x6e
+#define PIC_ITE7_N2_N3 0x72
+#define PIC_ITE_N2_N3(i) (PIC_ITE0_N2_N3 + ((i) * 4))
+
+#define PIC_IRT0 0x74
+#define PIC_IRT(i) (PIC_IRT0 + ((i) * 2))
+
+#define TIMER_CYCLES_MAXVAL 0xffffffffffffffffULL
+
+/*
+ * IRT Map
+ */
+#define PIC_IRT_WD_0_INDEX 0
+#define PIC_IRT_WD_1_INDEX 1
+#define PIC_IRT_WD_NMI_0_INDEX 2
+#define PIC_IRT_WD_NMI_1_INDEX 3
+#define PIC_IRT_TIMER_0_INDEX 4
+#define PIC_IRT_TIMER_1_INDEX 5
+#define PIC_IRT_TIMER_2_INDEX 6
+#define PIC_IRT_TIMER_3_INDEX 7
+#define PIC_IRT_TIMER_4_INDEX 8
+#define PIC_IRT_TIMER_5_INDEX 9
+#define PIC_IRT_TIMER_6_INDEX 10
+#define PIC_IRT_TIMER_7_INDEX 11
+#define PIC_IRT_CLOCK_INDEX PIC_IRT_TIMER_7_INDEX
+#define PIC_IRT_TIMER_INDEX(num) ((num) + PIC_IRT_TIMER_0_INDEX)
+
+#define PIC_CLOCK_TIMER 7
+#define PIC_IRQ_BASE 8
+
+#if !defined(LOCORE) && !defined(__ASSEMBLY__)
+
+#define PIC_IRT_FIRST_IRQ (PIC_IRQ_BASE)
+#define PIC_IRT_LAST_IRQ 63
+#define XLP_IRQ_IS_PICINTR(irq) ((irq) >= PIC_IRT_FIRST_IRQ)
+
+/*
+ * Misc
+ */
+#define PIC_IRT_VALID 1
+#define PIC_LOCAL_SCHEDULING 1
+#define PIC_GLOBAL_SCHEDULING 0
+
+#define nlm_read_pic_reg(b, r) nlm_read_reg64(b, r)
+#define nlm_write_pic_reg(b, r, v) nlm_write_reg64(b, r, v)
+#define nlm_get_pic_pcibase(node) nlm_pcicfg_base(XLP_IO_PIC_OFFSET(node))
+#define nlm_get_pic_regbase(node) (nlm_get_pic_pcibase(node) + XLP_IO_PCI_HDRSZ)
+
+/* IRT and h/w interrupt routines */
+static inline int
+nlm_pic_read_irt(uint64_t base, int irt_index)
+{
+ return nlm_read_pic_reg(base, PIC_IRT(irt_index));
+}
+
+static inline void
+nlm_pic_send_ipi(uint64_t base, int cpu, int vec, int nmi)
+{
+ uint64_t ipi;
+ int node, ncpu;
+
+ node = cpu / 32;
+ ncpu = cpu & 0x1f;
+ ipi = ((uint64_t)nmi << 31) | (vec << 20) | (node << 17) |
+ (1 << (cpu & 0xf));
+ if (ncpu > 15)
+ ipi |= 0x10000; /* Setting bit 16 to select cpus 16-31 */
+
+ nlm_write_pic_reg(base, PIC_IPI_CTL, ipi);
+}
+
+static inline uint64_t
+nlm_pic_read_control(uint64_t base)
+{
+ return nlm_read_pic_reg(base, PIC_CTRL);
+}
+
+static inline void
+nlm_pic_write_control(uint64_t base, uint64_t control)
+{
+ nlm_write_pic_reg(base, PIC_CTRL, control);
+}
+
+static inline void
+nlm_pic_update_control(uint64_t base, uint64_t control)
+{
+ uint64_t val;
+
+ val = nlm_read_pic_reg(base, PIC_CTRL);
+ nlm_write_pic_reg(base, PIC_CTRL, control | val);
+}
+
+static inline void
+nlm_pic_ack(uint64_t base, int irt_num)
+{
+ nlm_write_pic_reg(base, PIC_INT_ACK, irt_num);
+
+ /* Ack the Status register for Watchdog & System timers */
+ if (irt_num < 12)
+ nlm_write_pic_reg(base, PIC_STATUS, (1 << irt_num));
+}
+
+static inline void
+nlm_set_irt_to_cpu(uint64_t base, int irt, int cpu)
+{
+ uint64_t val;
+
+ val = nlm_read_pic_reg(base, PIC_IRT(irt));
+ val |= cpu & 0xf;
+ if (cpu > 15)
+ val |= 1 << 16;
+ nlm_write_pic_reg(base, PIC_IRT(irt), val);
+}
+
+static inline void
+nlm_pic_write_irt(uint64_t base, int irt_num, int en, int nmi,
+ int sch, int vec, int dt, int db, int dte)
+{
+ uint64_t val;
+
+ val = (((uint64_t)en & 0x1) << 31) | ((nmi & 0x1) << 29) |
+ ((sch & 0x1) << 28) | ((vec & 0x3f) << 20) |
+ ((dt & 0x1) << 19) | ((db & 0x7) << 16) |
+ (dte & 0xffff);
+
+ nlm_write_pic_reg(base, PIC_IRT(irt_num), val);
+}
+
+static inline void
+nlm_pic_write_irt_direct(uint64_t base, int irt_num, int en, int nmi,
+ int sch, int vec, int cpu)
+{
+ nlm_pic_write_irt(base, irt_num, en, nmi, sch, vec, 1,
+ (cpu >> 4), /* thread group */
+ 1 << (cpu & 0xf)); /* thread mask */
+}
+
+static inline uint64_t
+nlm_pic_read_timer(uint64_t base, int timer)
+{
+ return nlm_read_pic_reg(base, PIC_TIMER_COUNT(timer));
+}
+
+static inline void
+nlm_pic_write_timer(uint64_t base, int timer, uint64_t value)
+{
+ nlm_write_pic_reg(base, PIC_TIMER_COUNT(timer), value);
+}
+
+static inline void
+nlm_pic_set_timer(uint64_t base, int timer, uint64_t value, int irq, int cpu)
+{
+ uint64_t pic_ctrl;
+ int en, nmi;
+
+ en = nmi = 0;
+ if (irq > 0)
+ en = 1;
+ else if (irq < 0) {
+ en = nmi = 1;
+ irq = -irq;
+ }
+ nlm_write_pic_reg(base, PIC_TIMER_MAXVAL(timer), value);
+ nlm_pic_write_irt_direct(base, PIC_IRT_TIMER_INDEX(timer),
+ en, nmi, 0, irq, cpu);
+
+ /* enable the timer */
+ pic_ctrl = nlm_read_pic_reg(base, PIC_CTRL);
+ pic_ctrl |= (1 << (PIC_CTRL_STE + timer));
+ nlm_write_pic_reg(base, PIC_CTRL, pic_ctrl);
+}
+
+#endif /* __ASSEMBLY__ */
+#endif /* _NLM_HAL_PIC_H */
Property changes on: trunk/sys/mips/nlm/hal/pic.h
___________________________________________________________________
Added: svn:eol-style
## -0,0 +1 ##
+native
\ No newline at end of property
Added: svn:keywords
## -0,0 +1 ##
+MidnightBSD=%H
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+text/plain
\ No newline at end of property
Added: trunk/sys/mips/nlm/hal/poe.h
===================================================================
--- trunk/sys/mips/nlm/hal/poe.h (rev 0)
+++ trunk/sys/mips/nlm/hal/poe.h 2018-05-26 21:55:02 UTC (rev 9987)
@@ -0,0 +1,353 @@
+/* $MidnightBSD$ */
+/*-
+ * Copyright (c) 2003-2012 Broadcom Corporation
+ * All Rights Reserved
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in
+ * the documentation and/or other materials provided with the
+ * distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY BROADCOM ``AS IS'' AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL BROADCOM OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
+ * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
+ * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
+ * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * $FreeBSD: stable/10/sys/mips/nlm/hal/poe.h 233545 2012-03-27 14:05:12Z jchandra $
+ */
+
+#ifndef __NLM_POE_H__
+#define __NLM_POE_H__
+
+/**
+* @file_name poe.h
+* @author Netlogic Microsystems
+* @brief Basic definitions of XLP Packet Order Engine
+*/
+
+/* POE specific registers */
+#define POE_CL0_ENQ_SPILL_BASE_LO 0x0
+#define POE_CL1_ENQ_SPILL_BASE_LO 0x2
+#define POE_CL2_ENQ_SPILL_BASE_LO 0x4
+#define POE_CL3_ENQ_SPILL_BASE_LO 0x6
+#define POE_CL4_ENQ_SPILL_BASE_LO 0x8
+#define POE_CL5_ENQ_SPILL_BASE_LO 0xa
+#define POE_CL6_ENQ_SPILL_BASE_LO 0xc
+#define POE_CL7_ENQ_SPILL_BASE_LO 0xe
+#define POE_CL0_ENQ_SPILL_BASE_HI 0x1
+#define POE_CL1_ENQ_SPILL_BASE_HI 0x3
+#define POE_CL2_ENQ_SPILL_BASE_HI 0x5
+#define POE_CL3_ENQ_SPILL_BASE_HI 0x7
+#define POE_CL4_ENQ_SPILL_BASE_HI 0x9
+#define POE_CL5_ENQ_SPILL_BASE_HI 0xb
+#define POE_CL6_ENQ_SPILL_BASE_HI 0xd
+#define POE_CL7_ENQ_SPILL_BASE_HI 0xf
+#define POE_CL0_DEQ_SPILL_BASE_LO 0x10
+#define POE_CL1_DEQ_SPILL_BASE_LO 0x12
+#define POE_CL2_DEQ_SPILL_BASE_LO 0x14
+#define POE_CL3_DEQ_SPILL_BASE_LO 0x16
+#define POE_CL4_DEQ_SPILL_BASE_LO 0x18
+#define POE_CL5_DEQ_SPILL_BASE_LO 0x1a
+#define POE_CL6_DEQ_SPILL_BASE_LO 0x1c
+#define POE_CL7_DEQ_SPILL_BASE_LO 0x1e
+#define POE_CL0_DEQ_SPILL_BASE_HI 0x11
+#define POE_CL1_DEQ_SPILL_BASE_HI 0x13
+#define POE_CL2_DEQ_SPILL_BASE_HI 0x15
+#define POE_CL3_DEQ_SPILL_BASE_HI 0x17
+#define POE_CL4_DEQ_SPILL_BASE_HI 0x19
+#define POE_CL5_DEQ_SPILL_BASE_HI 0x1b
+#define POE_CL6_DEQ_SPILL_BASE_HI 0x1d
+#define POE_CL7_DEQ_SPILL_BASE_HI 0x1f
+#define POE_MSG_STORAGE_BASE_ADDR_LO 0x20
+#define POE_MSG_STORAGE_BASE_ADDR_HI 0x21
+#define POE_FBP_BASE_ADDR_LO 0x22
+#define POE_FBP_BASE_ADDR_HI 0x23
+#define POE_CL0_ENQ_SPILL_MAXLINE_LO 0x24
+#define POE_CL1_ENQ_SPILL_MAXLINE_LO 0x25
+#define POE_CL2_ENQ_SPILL_MAXLINE_LO 0x26
+#define POE_CL3_ENQ_SPILL_MAXLINE_LO 0x27
+#define POE_CL4_ENQ_SPILL_MAXLINE_LO 0x28
+#define POE_CL5_ENQ_SPILL_MAXLINE_LO 0x29
+#define POE_CL6_ENQ_SPILL_MAXLINE_LO 0x2a
+#define POE_CL7_ENQ_SPILL_MAXLINE_LO 0x2b
+#define POE_CL0_ENQ_SPILL_MAXLINE_HI 0x2c
+#define POE_CL1_ENQ_SPILL_MAXLINE_HI 0x2d
+#define POE_CL2_ENQ_SPILL_MAXLINE_HI 0x2e
+#define POE_CL3_ENQ_SPILL_MAXLINE_HI 0x2f
+#define POE_CL4_ENQ_SPILL_MAXLINE_HI 0x30
+#define POE_CL5_ENQ_SPILL_MAXLINE_HI 0x31
+#define POE_CL6_ENQ_SPILL_MAXLINE_HI 0x32
+#define POE_CL7_ENQ_SPILL_MAXLINE_HI 0x33
+#define POE_MAX_FLOW_MSG0 0x40
+#define POE_MAX_FLOW_MSG1 0x41
+#define POE_MAX_FLOW_MSG2 0x42
+#define POE_MAX_FLOW_MSG3 0x43
+#define POE_MAX_FLOW_MSG4 0x44
+#define POE_MAX_FLOW_MSG5 0x45
+#define POE_MAX_FLOW_MSG6 0x46
+#define POE_MAX_FLOW_MSG7 0x47
+#define POE_MAX_MSG_CL0 0x48
+#define POE_MAX_MSG_CL1 0x49
+#define POE_MAX_MSG_CL2 0x4a
+#define POE_MAX_MSG_CL3 0x4b
+#define POE_MAX_MSG_CL4 0x4c
+#define POE_MAX_MSG_CL5 0x4d
+#define POE_MAX_MSG_CL6 0x4e
+#define POE_MAX_MSG_CL7 0x4f
+#define POE_MAX_LOC_BUF_STG_CL0 0x50
+#define POE_MAX_LOC_BUF_STG_CL1 0x51
+#define POE_MAX_LOC_BUF_STG_CL2 0x52
+#define POE_MAX_LOC_BUF_STG_CL3 0x53
+#define POE_MAX_LOC_BUF_STG_CL4 0x54
+#define POE_MAX_LOC_BUF_STG_CL5 0x55
+#define POE_MAX_LOC_BUF_STG_CL6 0x56
+#define POE_MAX_LOC_BUF_STG_CL7 0x57
+#define POE_ENQ_MSG_COUNT0_SIZE 0x58
+#define POE_ENQ_MSG_COUNT1_SIZE 0x59
+#define POE_ENQ_MSG_COUNT2_SIZE 0x5a
+#define POE_ENQ_MSG_COUNT3_SIZE 0x5b
+#define POE_ENQ_MSG_COUNT4_SIZE 0x5c
+#define POE_ENQ_MSG_COUNT5_SIZE 0x5d
+#define POE_ENQ_MSG_COUNT6_SIZE 0x5e
+#define POE_ENQ_MSG_COUNT7_SIZE 0x5f
+#define POE_ERR_MSG_DESCRIP_LO0 0x60
+#define POE_ERR_MSG_DESCRIP_LO1 0x62
+#define POE_ERR_MSG_DESCRIP_LO2 0x64
+#define POE_ERR_MSG_DESCRIP_LO3 0x66
+#define POE_ERR_MSG_DESCRIP_HI0 0x61
+#define POE_ERR_MSG_DESCRIP_HI1 0x63
+#define POE_ERR_MSG_DESCRIP_HI2 0x65
+#define POE_ERR_MSG_DESCRIP_HI3 0x67
+#define POE_OOO_MSG_CNT_LO 0x68
+#define POE_IN_ORDER_MSG_CNT_LO 0x69
+#define POE_LOC_BUF_STOR_CNT_LO 0x6a
+#define POE_EXT_BUF_STOR_CNT_LO 0x6b
+#define POE_LOC_BUF_ALLOC_CNT_LO 0x6c
+#define POE_EXT_BUF_ALLOC_CNT_LO 0x6d
+#define POE_OOO_MSG_CNT_HI 0x6e
+#define POE_IN_ORDER_MSG_CNT_HI 0x6f
+#define POE_LOC_BUF_STOR_CNT_HI 0x70
+#define POE_EXT_BUF_STOR_CNT_HI 0x71
+#define POE_LOC_BUF_ALLOC_CNT_HI 0x72
+#define POE_EXT_BUF_ALLOC_CNT_HI 0x73
+#define POE_MODE_ERR_FLOW_ID 0x74
+#define POE_STATISTICS_ENABLE 0x75
+#define POE_MAX_SIZE_FLOW 0x76
+#define POE_MAX_SIZE 0x77
+#define POE_FBP_SP 0x78
+#define POE_FBP_SP_EN 0x79
+#define POE_LOC_ALLOC_EN 0x7a
+#define POE_EXT_ALLOC_EN 0x7b
+#define POE_DISTR_0_DROP_CNT 0xc0
+#define POE_DISTR_1_DROP_CNT 0xc1
+#define POE_DISTR_2_DROP_CNT 0xc2
+#define POE_DISTR_3_DROP_CNT 0xc3
+#define POE_DISTR_4_DROP_CNT 0xc4
+#define POE_DISTR_5_DROP_CNT 0xc5
+#define POE_DISTR_6_DROP_CNT 0xc6
+#define POE_DISTR_7_DROP_CNT 0xc7
+#define POE_DISTR_8_DROP_CNT 0xc8
+#define POE_DISTR_9_DROP_CNT 0xc9
+#define POE_DISTR_10_DROP_CNT 0xca
+#define POE_DISTR_11_DROP_CNT 0xcb
+#define POE_DISTR_12_DROP_CNT 0xcc
+#define POE_DISTR_13_DROP_CNT 0xcd
+#define POE_DISTR_14_DROP_CNT 0xce
+#define POE_DISTR_15_DROP_CNT 0xcf
+#define POE_CLASS_0_DROP_CNT 0xd0
+#define POE_CLASS_1_DROP_CNT 0xd1
+#define POE_CLASS_2_DROP_CNT 0xd2
+#define POE_CLASS_3_DROP_CNT 0xd3
+#define POE_CLASS_4_DROP_CNT 0xd4
+#define POE_CLASS_5_DROP_CNT 0xd5
+#define POE_CLASS_6_DROP_CNT 0xd6
+#define POE_CLASS_7_DROP_CNT 0xd7
+#define POE_DISTR_C0_DROP_CNT 0xd8
+#define POE_DISTR_C1_DROP_CNT 0xd9
+#define POE_DISTR_C2_DROP_CNT 0xda
+#define POE_DISTR_C3_DROP_CNT 0xdb
+#define POE_DISTR_C4_DROP_CNT 0xdc
+#define POE_DISTR_C5_DROP_CNT 0xdd
+#define POE_DISTR_C6_DROP_CNT 0xde
+#define POE_DISTR_C7_DROP_CNT 0xdf
+#define POE_CPU_DROP_CNT 0xe0
+#define POE_MAX_FLOW_DROP_CNT 0xe1
+#define POE_INTERRUPT_VEC 0x140
+#define POE_INTERRUPT_MASK 0x141
+#define POE_FATALERR_MASK 0x142
+#define POE_IDI_CFG 0x143
+#define POE_TIMEOUT_VALUE 0x144
+#define POE_CACHE_ALLOC_EN 0x145
+#define POE_FBP_ECC_ERR_CNT 0x146
+#define POE_MSG_STRG_ECC_ERR_CNT 0x147
+#define POE_FID_INFO_ECC_ERR_CNT 0x148
+#define POE_MSG_INFO_ECC_ERR_CNT 0x149
+#define POE_LL_ECC_ERR_CNT 0x14a
+#define POE_SIZE_ECC_ERR_CNT 0x14b
+#define POE_FMN_TXCR_ECC_ERR_CNT 0x14c
+#define POE_ENQ_INSPIL_ECC_ERR_CNT 0x14d
+#define POE_ENQ_OUTSPIL_ECC_ERR_CNT 0x14e
+#define POE_DEQ_OUTSPIL_ECC_ERR_CNT 0x14f
+#define POE_ENQ_MSG_SENT 0x150
+#define POE_ENQ_MSG_CNT 0x151
+#define POE_FID_RDATA 0x152
+#define POE_FID_WDATA 0x153
+#define POE_FID_CMD 0x154
+#define POE_FID_ADDR 0x155
+#define POE_MSG_INFO_CMD 0x156
+#define POE_MSG_INFO_ADDR 0x157
+#define POE_MSG_INFO_RDATA 0x158
+#define POE_LL_CMD 0x159
+#define POE_LL_ADDR 0x15a
+#define POE_LL_RDATA 0x15b
+#define POE_MSG_STG_CMD 0x15c
+#define POE_MSG_STG_ADDR 0x15d
+#define POE_MSG_STG_RDATA 0x15e
+#define POE_DISTR_THRESHOLD_0 0x1c0
+#define POE_DISTR_THRESHOLD_1 0x1c1
+#define POE_DISTR_THRESHOLD_2 0x1c2
+#define POE_DISTR_THRESHOLD_3 0x1c3
+#define POE_DISTR_THRESHOLD_4 0x1c4
+#define POE_DISTR_THRESHOLD(i) (0x1c0 + (i))
+#define POE_DISTR_EN 0x1c5
+#define POE_ENQ_SPILL_THOLD 0x1c8
+#define POE_DEQ_SPILL_THOLD 0x1c9
+#define POE_DEQ_SPILL_TIMER 0x1ca
+#define POE_DISTR_CLASS_DROP_EN 0x1cb
+#define POE_DISTR_VEC_DROP_EN 0x1cc
+#define POE_DISTR_DROP_TIMER 0x1cd
+#define POE_ERROR_LOG_W0 0x1ce
+#define POE_ERROR_LOG_W1 0x1cf
+#define POE_ERROR_LOG_W2 0x1d0
+#define POE_ERR_INJ_CTRL0 0x1d1
+#define POE_TX_TIMER 0x1d4
+
+#define NUM_DIST_VEC 16
+#define NUM_WORDS_PER_DV 16
+#define MAX_DV_TBL_ENTRIES (NUM_DIST_VEC * NUM_WORDS_PER_DV)
+#define POE_DIST_THRESHOLD_VAL 0xa
+
+/*
+ * POE distribution vectors
+ *
+ * Each vector is 512 bit with msb indicating vc 512 and lsb indicating vc 0
+ * 512-bit-vector is specified as 16 32-bit words.
+ * Left most word has the vc range 511-479 right most word has vc range 31 - 0
+ * Each word has the MSB select higer vc number and LSB select lower vc num
+ */
+#define POE_DISTVECT_BASE 0x100
+#define POE_DISTVECT(vec) (POE_DISTVECT_BASE + 16 * (vec))
+#define POE_DISTVECT_OFFSET(node,cpu) (4 * (3 - (node)) + (3 - (cpu)/8))
+#define POE_DISTVECT_SHIFT(node,cpu) (((cpu) % 8 ) * 4)
+
+#if !defined(LOCORE) && !defined(__ASSEMBLY__)
+
+#define nlm_read_poe_reg(b, r) nlm_read_reg(b, r)
+#define nlm_write_poe_reg(b, r, v) nlm_write_reg(b, r, v)
+#define nlm_read_poedv_reg(b, r) nlm_read_reg_xkphys(b, r)
+#define nlm_write_poedv_reg(b, r, v) nlm_write_reg_xkphys(b, r, v)
+#define nlm_get_poe_pcibase(node) \
+ nlm_pcicfg_base(XLP_IO_POE_OFFSET(node))
+#define nlm_get_poe_regbase(node) \
+ (nlm_get_poe_pcibase(node) + XLP_IO_PCI_HDRSZ)
+#define nlm_get_poedv_regbase(node) \
+ nlm_xkphys_map_pcibar0(nlm_get_poe_pcibase(node))
+
+static __inline int
+nlm_poe_max_flows(uint64_t poe_pcibase)
+{
+ return (nlm_read_reg(poe_pcibase, XLP_PCI_DEVINFO_REG0));
+}
+
+/*
+ * Helper function, calculate the distribution vector
+ * cm0, cm1, cm2, cm3 : CPU masks for nodes 0..3
+ * thr_vcmask: destination VCs for a thread
+ */
+static __inline void
+nlm_calc_poe_distvec(uint32_t cm0, uint32_t cm1, uint32_t cm2, uint32_t cm3,
+ uint32_t thr_vcmask, uint32_t *distvec)
+{
+ uint32_t cpumask = 0, val;
+ int i, cpu, node, startcpu, index;
+
+ thr_vcmask &= 0xf;
+ for (node = 0; node < XLP_MAX_NODES; node++) {
+ switch (node) {
+ case 0: cpumask = cm0; break;
+ case 1: cpumask = cm1; break;
+ case 2: cpumask = cm2; break;
+ case 3: cpumask = cm3; break;
+ }
+
+ for (i = 0; i < 4; i++) {
+ val = 0;
+ startcpu = 31 - i * 8;
+ for (cpu = startcpu; cpu >= startcpu - 7; cpu--) {
+ val <<= 4;
+ if (cpumask & (1U << cpu))
+ val |= thr_vcmask;
+ }
+ index = POE_DISTVECT_OFFSET(node, startcpu);
+ distvec[index] = val;
+ }
+ }
+}
+
+static __inline int
+nlm_write_poe_distvec(uint64_t poedv_base, int vec, uint32_t *distvec)
+{
+ uint32_t reg;
+ int i;
+
+ if (vec < 0 || vec >= NUM_DIST_VEC)
+ return (-1);
+
+ for (i = 0; i < NUM_WORDS_PER_DV; i++) {
+ reg = POE_DISTVECT(vec) + i;
+ nlm_write_poedv_reg(poedv_base, reg, distvec[i]);
+ }
+
+ return (0);
+}
+
+static __inline void
+nlm_config_poe(uint64_t poe_base, uint64_t poedv_base)
+{
+ uint32_t zerodv[NUM_WORDS_PER_DV];
+ int i;
+
+ /* First disable distribution vector logic */
+ nlm_write_poe_reg(poe_base, POE_DISTR_EN, 0);
+
+ memset(zerodv, 0, sizeof(zerodv));
+ for (i = 0; i < NUM_DIST_VEC; i++)
+ nlm_write_poe_distvec(poedv_base, i, zerodv);
+
+ /* set the threshold */
+ for (i = 0; i < 5; i++)
+ nlm_write_poe_reg(poe_base, POE_DISTR_THRESHOLD(i),
+ POE_DIST_THRESHOLD_VAL);
+
+ nlm_write_poe_reg(poe_base, POE_DISTR_EN, 1);
+
+ /* always enable local message store */
+ nlm_write_poe_reg(poe_base, POE_LOC_ALLOC_EN, 1);
+
+ nlm_write_poe_reg(poe_base, POE_TX_TIMER, 0x3);
+}
+#endif /* !(LOCORE) && !(__ASSEMBLY__) */
+#endif
Property changes on: trunk/sys/mips/nlm/hal/poe.h
___________________________________________________________________
Added: svn:eol-style
## -0,0 +1 ##
+native
\ No newline at end of property
Added: svn:keywords
## -0,0 +1 ##
+MidnightBSD=%H
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+text/plain
\ No newline at end of property
Added: trunk/sys/mips/nlm/hal/sgmii.h
===================================================================
--- trunk/sys/mips/nlm/hal/sgmii.h (rev 0)
+++ trunk/sys/mips/nlm/hal/sgmii.h 2018-05-26 21:55:02 UTC (rev 9987)
@@ -0,0 +1,218 @@
+/* $MidnightBSD$ */
+/*-
+ * Copyright (c) 2003-2012 Broadcom Corporation
+ * All Rights Reserved
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in
+ * the documentation and/or other materials provided with the
+ * distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY BROADCOM ``AS IS'' AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL BROADCOM OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
+ * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
+ * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
+ * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * $FreeBSD: stable/10/sys/mips/nlm/hal/sgmii.h 233545 2012-03-27 14:05:12Z jchandra $
+ */
+
+#ifndef __NLM_SGMII_H__
+#define __NLM_SGMII_H__
+
+/**
+* @file_name sgmii.h
+* @author Netlogic Microsystems
+* @brief Basic definitions of XLP SGMII ports
+*/
+
+#define SGMII_MAC_CONF1(block, i) NAE_REG(block, i, 0x00)
+#define SGMII_MAC_CONF2(block, i) NAE_REG(block, i, 0x01)
+#define SGMII_IPG_IFG(block, i) NAE_REG(block, i, 0x02)
+#define SGMII_HLF_DUP(block, i) NAE_REG(block, i, 0x03)
+#define SGMII_MAX_FRAME(block, i) NAE_REG(block, i, 0x04)
+#define SGMII_TEST(block, i) NAE_REG(block, i, 0x07)
+#define SGMII_MIIM_CONF(block, i) NAE_REG(block, i, 0x08)
+#define SGMII_MIIM_CMD(block, i) NAE_REG(block, i, 0x09)
+#define SGMII_MIIM_ADDR(block, i) NAE_REG(block, i, 0x0a)
+#define SGMII_MIIM_CTRL(block, i) NAE_REG(block, i, 0x0b)
+#define SGMII_MIIM_STAT(block, i) NAE_REG(block, i, 0x0c)
+#define SGMII_MIIM_IND(block, i) NAE_REG(block, i, 0x0d)
+#define SGMII_IO_CTRL(block, i) NAE_REG(block, i, 0x0e)
+#define SGMII_IO_STAT(block, i) NAE_REG(block, i, 0x0f)
+#define SGMII_STATS_MLR(block, i) NAE_REG(block, i, 0x1f)
+#define SGMII_STATS_TR64(block, i) NAE_REG(block, i, 0x20)
+#define SGMII_STATS_TR127(block, i) NAE_REG(block, i, 0x21)
+#define SGMII_STATS_TR255(block, i) NAE_REG(block, i, 0x22)
+#define SGMII_STATS_TR511(block, i) NAE_REG(block, i, 0x23)
+#define SGMII_STATS_TR1K(block, i) NAE_REG(block, i, 0x24)
+#define SGMII_STATS_TRMAX(block, i) NAE_REG(block, i, 0x25)
+#define SGMII_STATS_TRMGV(block, i) NAE_REG(block, i, 0x26)
+#define SGMII_STATS_RBYT(block, i) NAE_REG(block, i, 0x27)
+#define SGMII_STATS_RPKT(block, i) NAE_REG(block, i, 0x28)
+#define SGMII_STATS_RFCS(block, i) NAE_REG(block, i, 0x29)
+#define SGMII_STATS_RMCA(block, i) NAE_REG(block, i, 0x2a)
+#define SGMII_STATS_RBCA(block, i) NAE_REG(block, i, 0x2b)
+#define SGMII_STATS_RXCF(block, i) NAE_REG(block, i, 0x2c)
+#define SGMII_STATS_RXPF(block, i) NAE_REG(block, i, 0x2d)
+#define SGMII_STATS_RXUO(block, i) NAE_REG(block, i, 0x2e)
+#define SGMII_STATS_RALN(block, i) NAE_REG(block, i, 0x2f)
+#define SGMII_STATS_RFLR(block, i) NAE_REG(block, i, 0x30)
+#define SGMII_STATS_RCDE(block, i) NAE_REG(block, i, 0x31)
+#define SGMII_STATS_RCSE(block, i) NAE_REG(block, i, 0x32)
+#define SGMII_STATS_RUND(block, i) NAE_REG(block, i, 0x33)
+#define SGMII_STATS_ROVR(block, i) NAE_REG(block, i, 0x34)
+#define SGMII_STATS_RFRG(block, i) NAE_REG(block, i, 0x35)
+#define SGMII_STATS_RJBR(block, i) NAE_REG(block, i, 0x36)
+#define SGMII_STATS_TBYT(block, i) NAE_REG(block, i, 0x38)
+#define SGMII_STATS_TPKT(block, i) NAE_REG(block, i, 0x39)
+#define SGMII_STATS_TMCA(block, i) NAE_REG(block, i, 0x3a)
+#define SGMII_STATS_TBCA(block, i) NAE_REG(block, i, 0x3b)
+#define SGMII_STATS_TXPF(block, i) NAE_REG(block, i, 0x3c)
+#define SGMII_STATS_TDFR(block, i) NAE_REG(block, i, 0x3d)
+#define SGMII_STATS_TEDF(block, i) NAE_REG(block, i, 0x3e)
+#define SGMII_STATS_TSCL(block, i) NAE_REG(block, i, 0x3f)
+#define SGMII_STATS_TMCL(block, i) NAE_REG(block, i, 0x40)
+#define SGMII_STATS_TLCL(block, i) NAE_REG(block, i, 0x41)
+#define SGMII_STATS_TXCL(block, i) NAE_REG(block, i, 0x42)
+#define SGMII_STATS_TNCL(block, i) NAE_REG(block, i, 0x43)
+#define SGMII_STATS_TJBR(block, i) NAE_REG(block, i, 0x46)
+#define SGMII_STATS_TFCS(block, i) NAE_REG(block, i, 0x47)
+#define SGMII_STATS_TXCF(block, i) NAE_REG(block, i, 0x48)
+#define SGMII_STATS_TOVR(block, i) NAE_REG(block, i, 0x49)
+#define SGMII_STATS_TUND(block, i) NAE_REG(block, i, 0x4a)
+#define SGMII_STATS_TFRG(block, i) NAE_REG(block, i, 0x4b)
+#define SGMII_STATS_CAR1(block, i) NAE_REG(block, i, 0x4c)
+#define SGMII_STATS_CAR2(block, i) NAE_REG(block, i, 0x4d)
+#define SGMII_STATS_CAM1(block, i) NAE_REG(block, i, 0x4e)
+#define SGMII_STATS_CAM2(block, i) NAE_REG(block, i, 0x4f)
+#define SGMII_MAC_ADDR0_LO(block, i) NAE_REG(block, i, 0x50)
+#define SGMII_MAC_ADDR0_HI(block, i) NAE_REG(block, i, 0x51)
+#define SGMII_MAC_ADDR1_LO(block, i) NAE_REG(block, i, 0x52)
+#define SGMII_MAC_ADDR1_HI(block, i) NAE_REG(block, i, 0x53)
+#define SGMII_MAC_ADDR2_LO(block, i) NAE_REG(block, i, 0x54)
+#define SGMII_MAC_ADDR2_HI(block, i) NAE_REG(block, i, 0x55)
+#define SGMII_MAC_ADDR3_LO(block, i) NAE_REG(block, i, 0x56)
+#define SGMII_MAC_ADDR3_HI(block, i) NAE_REG(block, i, 0x57)
+#define SGMII_MAC_ADDR_MASK0_LO(block, i) NAE_REG(block, i, 0x58)
+#define SGMII_MAC_ADDR_MASK0_HI(block, i) NAE_REG(block, i, 0x59)
+#define SGMII_MAC_ADDR_MASK1_LO(block, i) NAE_REG(block, i, 0x5a)
+#define SGMII_MAC_ADDR_MASK1_HI(block, i) NAE_REG(block, i, 0x5b)
+#define SGMII_MAC_FILTER_CONFIG(block, i) NAE_REG(block, i, 0x5c)
+#define SGMII_HASHTBL_VEC_B31_0(block, i) NAE_REG(block, i, 0x60)
+#define SGMII_HASHTBL_VEC_B63_32(block, i) NAE_REG(block, i, 0x61)
+#define SGMII_HASHTBL_VEC_B95_64(block, i) NAE_REG(block, i, 0x62)
+#define SGMII_HASHTBL_VEC_B127_96(block, i) NAE_REG(block, i, 0x63)
+#define SGMII_HASHTBL_VEC_B159_128(block, i) NAE_REG(block, i, 0x64)
+#define SGMII_HASHTBL_VEC_B191_160(block, i) NAE_REG(block, i, 0x65)
+#define SGMII_HASHTBL_VEC_B223_192(block, i) NAE_REG(block, i, 0x66)
+#define SGMII_HASHTBL_VEC_B255_224(block, i) NAE_REG(block, i, 0x67)
+#define SGMII_HASHTBL_VEC_B287_256(block, i) NAE_REG(block, i, 0x68)
+#define SGMII_HASHTBL_VEC_B319_288(block, i) NAE_REG(block, i, 0x69)
+#define SGMII_HASHTBL_VEC_B351_320(block, i) NAE_REG(block, i, 0x6a)
+#define SGMII_HASHTBL_VEC_B383_352(block, i) NAE_REG(block, i, 0x6b)
+#define SGMII_HASHTBL_VEC_B415_384(block, i) NAE_REG(block, i, 0x6c)
+#define SGMII_HASHTBL_VEC_B447_416(block, i) NAE_REG(block, i, 0x6d)
+#define SGMII_HASHTBL_VEC_B479_448(block, i) NAE_REG(block, i, 0x6e)
+#define SGMII_HASHTBL_VEC_B511_480(block, i) NAE_REG(block, i, 0x6f)
+
+#define SGMII_NETIOR_VLANTYPE_FILTER(block, i) NAE_REG(block, i, 0x76)
+#define SGMII_NETIOR_RXDROP_CNTR(block, i) NAE_REG(block, i, 0x77)
+#define SGMII_NETIOR_PAUSE_QUANTAMULT(block, i) NAE_REG(block, i, 0x78)
+#define SGMII_NETIOR_MAC_CTRL_OPCODE(block, i) NAE_REG(block, i, 0x79)
+#define SGMII_NETIOR_MAC_DA_H(block, i) NAE_REG(block, i, 0x7a)
+#define SGMII_NETIOR_MAC_DA_L(block, i) NAE_REG(block, i, 0x7b)
+#define SGMII_NET_IFACE_CTRL3(block, i) NAE_REG(block, i, 0x7c)
+#define SGMII_NETIOR_GMAC_STAT(block, i) NAE_REG(block, i, 0x7d)
+#define SGMII_NET_IFACE_CTRL2(block, i) NAE_REG(block, i, 0x7e)
+#define SGMII_NET_IFACE_CTRL(block, i) NAE_REG(block, i, 0x7f)
+
+#if !defined(LOCORE) && !defined(__ASSEMBLY__)
+/* speed */
+enum nlm_sgmii_speed {
+ NLM_SGMII_SPEED_10,
+ NLM_SGMII_SPEED_100,
+ NLM_SGMII_SPEED_1000,
+ NLM_SGMII_SPEED_RSVD
+};
+
+/* duplexity */
+enum nlm_sgmii_duplex_mode {
+ NLM_SGMII_DUPLEX_AUTO,
+ NLM_SGMII_DUPLEX_HALF,
+ NLM_SGMII_DUPLEX_FULL
+};
+
+/* stats */
+enum {
+ nlm_sgmii_stats_mlr,
+ nlm_sgmii_stats_tr64,
+ nlm_sgmii_stats_tr127,
+ nlm_sgmii_stats_tr255,
+ nlm_sgmii_stats_tr511,
+ nlm_sgmii_stats_tr1k,
+ nlm_sgmii_stats_trmax,
+ nlm_sgmii_stats_trmgv,
+ nlm_sgmii_stats_rbyt,
+ nlm_sgmii_stats_rpkt,
+ nlm_sgmii_stats_rfcs,
+ nlm_sgmii_stats_rmca,
+ nlm_sgmii_stats_rbca,
+ nlm_sgmii_stats_rxcf,
+ nlm_sgmii_stats_rxpf,
+ nlm_sgmii_stats_rxuo,
+ nlm_sgmii_stats_raln,
+ nlm_sgmii_stats_rflr,
+ nlm_sgmii_stats_rcde,
+ nlm_sgmii_stats_rcse,
+ nlm_sgmii_stats_rund,
+ nlm_sgmii_stats_rovr,
+ nlm_sgmii_stats_rfrg,
+ nlm_sgmii_stats_rjbr,
+ nlm_sgmii_stats_rdummy, /* not used */
+ nlm_sgmii_stats_tbyt,
+ nlm_sgmii_stats_tpkt,
+ nlm_sgmii_stats_tmca,
+ nlm_sgmii_stats_tbca,
+ nlm_sgmii_stats_txpf,
+ nlm_sgmii_stats_tdfr,
+ nlm_sgmii_stats_tedf,
+ nlm_sgmii_stats_tscl,
+ nlm_sgmii_stats_tmcl,
+ nlm_sgmii_stats_tlcl,
+ nlm_sgmii_stats_txcl,
+ nlm_sgmii_stats_tncl,
+ nlm_sgmii_stats_tjbr,
+ nlm_sgmii_stats_tfcs,
+ nlm_sgmii_stats_txcf,
+ nlm_sgmii_stats_tovr,
+ nlm_sgmii_stats_tund,
+ nlm_sgmii_stats_tfrg,
+ nlm_sgmii_stats_car1,
+ nlm_sgmii_stats_car2,
+ nlm_sgmii_stats_cam1,
+ nlm_sgmii_stats_cam2
+};
+
+void nlm_configure_sgmii_interface(uint64_t, int, int, int, int);
+void nlm_sgmii_pcs_init(uint64_t, uint32_t);
+void nlm_nae_setup_mac(uint64_t, int, int, int, int, int, int, int);
+void nlm_nae_setup_rx_mode_sgmii(uint64_t, int, int, int, int, int,
+ int, int);
+void nlm_nae_setup_mac_addr_sgmii(uint64_t, int, int, int, uint8_t *);
+
+#endif /* !(LOCORE) && !(__ASSEMBLY__) */
+
+#endif
Property changes on: trunk/sys/mips/nlm/hal/sgmii.h
___________________________________________________________________
Added: svn:eol-style
## -0,0 +1 ##
+native
\ No newline at end of property
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## -0,0 +1 ##
+MidnightBSD=%H
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+text/plain
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Added: trunk/sys/mips/nlm/hal/sys.h
===================================================================
--- trunk/sys/mips/nlm/hal/sys.h (rev 0)
+++ trunk/sys/mips/nlm/hal/sys.h 2018-05-26 21:55:02 UTC (rev 9987)
@@ -0,0 +1,160 @@
+/* $MidnightBSD$ */
+/*-
+ * Copyright 2003-2011 Netlogic Microsystems (Netlogic). All rights
+ * reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in
+ * the documentation and/or other materials provided with the
+ * distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY Netlogic Microsystems ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL NETLOGIC OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
+ * THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * NETLOGIC_BSD
+ * $FreeBSD: stable/10/sys/mips/nlm/hal/sys.h 255368 2013-09-07 18:26:16Z jchandra $
+ */
+
+#ifndef __NLM_HAL_SYS_H__
+#define __NLM_HAL_SYS_H__
+
+/**
+* @file_name sys.h
+* @author Netlogic Microsystems
+* @brief HAL for System configuration registers
+*/
+#define SYS_CHIP_RESET 0x00
+#define SYS_POWER_ON_RESET_CFG 0x01
+#define SYS_EFUSE_DEVICE_CFG_STATUS0 0x02
+#define SYS_EFUSE_DEVICE_CFG_STATUS1 0x03
+#define SYS_EFUSE_DEVICE_CFG_STATUS2 0x04
+#define SYS_EFUSE_DEVICE_CFG3 0x05
+#define SYS_EFUSE_DEVICE_CFG4 0x06
+#define SYS_EFUSE_DEVICE_CFG5 0x07
+#define SYS_EFUSE_DEVICE_CFG6 0x08
+#define SYS_EFUSE_DEVICE_CFG7 0x09
+#define SYS_PLL_CTRL 0x0a
+#define SYS_CPU_RESET 0x0b
+#define SYS_CPU_NONCOHERENT_MODE 0x0d
+#define SYS_CORE_DFS_DIS_CTRL 0x0e
+#define SYS_CORE_DFS_RST_CTRL 0x0f
+#define SYS_CORE_DFS_BYP_CTRL 0x10
+#define SYS_CORE_DFS_PHA_CTRL 0x11
+#define SYS_CORE_DFS_DIV_INC_CTRL 0x12
+#define SYS_CORE_DFS_DIV_DEC_CTRL 0x13
+#define SYS_CORE_DFS_DIV_VALUE 0x14
+#define SYS_RESET 0x15
+#define SYS_DFS_DIS_CTRL 0x16
+#define SYS_DFS_RST_CTRL 0x17
+#define SYS_DFS_BYP_CTRL 0x18
+#define SYS_DFS_DIV_INC_CTRL 0x19
+#define SYS_DFS_DIV_DEC_CTRL 0x1a
+#define SYS_DFS_DIV_VALUE0 0x1b
+#define SYS_DFS_DIV_VALUE1 0x1c
+#define SYS_SENSE_AMP_DLY 0x1d
+#define SYS_SOC_SENSE_AMP_DLY 0x1e
+#define SYS_CTRL0 0x1f
+#define SYS_CTRL1 0x20
+#define SYS_TIMEOUT_BS1 0x21
+#define SYS_BYTE_SWAP 0x22
+#define SYS_VRM_VID 0x23
+#define SYS_PWR_RAM_CMD 0x24
+#define SYS_PWR_RAM_ADDR 0x25
+#define SYS_PWR_RAM_DATA0 0x26
+#define SYS_PWR_RAM_DATA1 0x27
+#define SYS_PWR_RAM_DATA2 0x28
+#define SYS_PWR_UCODE 0x29
+#define SYS_CPU0_PWR_STATUS 0x2a
+#define SYS_CPU1_PWR_STATUS 0x2b
+#define SYS_CPU2_PWR_STATUS 0x2c
+#define SYS_CPU3_PWR_STATUS 0x2d
+#define SYS_CPU4_PWR_STATUS 0x2e
+#define SYS_CPU5_PWR_STATUS 0x2f
+#define SYS_CPU6_PWR_STATUS 0x30
+#define SYS_CPU7_PWR_STATUS 0x31
+#define SYS_STATUS 0x32
+#define SYS_INT_POL 0x33
+#define SYS_INT_TYPE 0x34
+#define SYS_INT_STATUS 0x35
+#define SYS_INT_MASK0 0x36
+#define SYS_INT_MASK1 0x37
+#define SYS_UCO_S_ECC 0x38
+#define SYS_UCO_M_ECC 0x39
+#define SYS_UCO_ADDR 0x3a
+#define SYS_PLL_DFS_BYP_CTRL 0x3a /* Bx stepping */
+#define SYS_UCO_INSTR 0x3b
+#define SYS_MEM_BIST0 0x3c
+#define SYS_MEM_BIST1 0x3d
+#define SYS_PLL_DFS_DIV_VALUE 0x3d /* Bx stepping */
+#define SYS_MEM_BIST2 0x3e
+#define SYS_MEM_BIST3 0x3f
+#define SYS_MEM_BIST4 0x40
+#define SYS_MEM_BIST5 0x41
+#define SYS_MEM_BIST6 0x42
+#define SYS_MEM_BIST7 0x43
+#define SYS_MEM_BIST8 0x44
+#define SYS_MEM_BIST9 0x45
+#define SYS_MEM_BIST10 0x46
+#define SYS_MEM_BIST11 0x47
+#define SYS_MEM_BIST12 0x48
+#define SYS_SCRTCH0 0x49
+#define SYS_SCRTCH1 0x4a
+#define SYS_SCRTCH2 0x4b
+#define SYS_SCRTCH3 0x4c
+
+#if !defined(LOCORE) && !defined(__ASSEMBLY__)
+
+#define nlm_read_sys_reg(b, r) nlm_read_reg(b, r)
+#define nlm_write_sys_reg(b, r, v) nlm_write_reg(b, r, v)
+#define nlm_get_sys_pcibase(node) nlm_pcicfg_base(XLP_IO_SYS_OFFSET(node))
+#define nlm_get_sys_regbase(node) (nlm_get_sys_pcibase(node) + XLP_IO_PCI_HDRSZ)
+
+enum {
+ /* Don't change order and it must start from zero */
+ DFS_DEVICE_NAE = 0,
+ DFS_DEVICE_SAE,
+ DFS_DEVICE_RSA,
+ DFS_DEVICE_DTRE,
+ DFS_DEVICE_CMP,
+ DFS_DEVICE_KBP,
+ DFS_DEVICE_DMC,
+ DFS_DEVICE_NAND,
+ DFS_DEVICE_MMC,
+ DFS_DEVICE_NOR,
+ DFS_DEVICE_CORE,
+ DFS_DEVICE_REGEX_SLOW,
+ DFS_DEVICE_REGEX_FAST,
+ DFS_DEVICE_SATA,
+ INVALID_DFS_DEVICE = 0xFF
+};
+
+static __inline
+void nlm_sys_enable_block(uint64_t sys_base, int block)
+{
+ uint32_t dfsdis, mask;
+
+ mask = 1 << block;
+ dfsdis = nlm_read_sys_reg(sys_base, SYS_DFS_DIS_CTRL);
+ if ((dfsdis & mask) == 0)
+ return; /* already enabled, nothing to do */
+ dfsdis &= ~mask;
+ nlm_write_sys_reg(sys_base, SYS_DFS_DIS_CTRL, dfsdis);
+}
+
+#endif
+#endif
Property changes on: trunk/sys/mips/nlm/hal/sys.h
___________________________________________________________________
Added: svn:eol-style
## -0,0 +1 ##
+native
\ No newline at end of property
Added: svn:keywords
## -0,0 +1 ##
+MidnightBSD=%H
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+text/plain
\ No newline at end of property
Added: trunk/sys/mips/nlm/hal/uart.h
===================================================================
--- trunk/sys/mips/nlm/hal/uart.h (rev 0)
+++ trunk/sys/mips/nlm/hal/uart.h 2018-05-26 21:55:02 UTC (rev 9987)
@@ -0,0 +1,189 @@
+/* $MidnightBSD$ */
+/*-
+ * Copyright 2003-2011 Netlogic Microsystems (Netlogic). All rights
+ * reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in
+ * the documentation and/or other materials provided with the
+ * distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY Netlogic Microsystems ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL NETLOGIC OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
+ * THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * NETLOGIC_BSD
+ * $FreeBSD: stable/10/sys/mips/nlm/hal/uart.h 227722 2011-11-19 14:06:15Z jchandra $
+ */
+
+#ifndef __XLP_HAL_UART_H__
+#define __XLP_HAL_UART_H__
+
+/* UART Specific registers */
+#define UART_RX_DATA 0x00
+#define UART_TX_DATA 0x00
+
+#define UART_INT_EN 0x01
+#define UART_INT_ID 0x02
+#define UART_FIFO_CTL 0x02
+#define UART_LINE_CTL 0x03
+#define UART_MODEM_CTL 0x04
+#define UART_LINE_STS 0x05
+#define UART_MODEM_STS 0x06
+
+#define UART_DIVISOR0 0x00
+#define UART_DIVISOR1 0x01
+
+#define BASE_BAUD (XLP_IO_CLK/16)
+#define BAUD_DIVISOR(baud) (BASE_BAUD / baud)
+
+/* LCR mask values */
+#define LCR_5BITS 0x00
+#define LCR_6BITS 0x01
+#define LCR_7BITS 0x02
+#define LCR_8BITS 0x03
+#define LCR_STOPB 0x04
+#define LCR_PENAB 0x08
+#define LCR_PODD 0x00
+#define LCR_PEVEN 0x10
+#define LCR_PONE 0x20
+#define LCR_PZERO 0x30
+#define LCR_SBREAK 0x40
+#define LCR_EFR_ENABLE 0xbf
+#define LCR_DLAB 0x80
+
+/* MCR mask values */
+#define MCR_DTR 0x01
+#define MCR_RTS 0x02
+#define MCR_DRS 0x04
+#define MCR_IE 0x08
+#define MCR_LOOPBACK 0x10
+
+/* FCR mask values */
+#define FCR_RCV_RST 0x02
+#define FCR_XMT_RST 0x04
+#define FCR_RX_LOW 0x00
+#define FCR_RX_MEDL 0x40
+#define FCR_RX_MEDH 0x80
+#define FCR_RX_HIGH 0xc0
+
+/* IER mask values */
+#define IER_ERXRDY 0x1
+#define IER_ETXRDY 0x2
+#define IER_ERLS 0x4
+#define IER_EMSC 0x8
+
+#if !defined(LOCORE) && !defined(__ASSEMBLY__)
+
+#define nlm_read_uart_reg(b, r) nlm_read_reg(b, r)
+#define nlm_write_uart_reg(b, r, v) nlm_write_reg(b, r, v)
+#define nlm_get_uart_pcibase(node, inst) \
+ nlm_pcicfg_base(XLP_IO_UART_OFFSET(node, inst))
+#define nlm_get_uart_regbase(node, inst) \
+ (nlm_get_uart_pcibase(node, inst) + XLP_IO_PCI_HDRSZ)
+
+static inline void
+nlm_uart_set_baudrate(uint64_t base, int baud)
+{
+ uint32_t lcr;
+
+ lcr = nlm_read_uart_reg(base, UART_LINE_CTL);
+
+ /* enable divisor register, and write baud values */
+ nlm_write_uart_reg(base, UART_LINE_CTL, lcr | (1 << 7));
+ nlm_write_uart_reg(base, UART_DIVISOR0,
+ (BAUD_DIVISOR(baud) & 0xff));
+ nlm_write_uart_reg(base, UART_DIVISOR1,
+ ((BAUD_DIVISOR(baud) >> 8) & 0xff));
+
+ /* restore default lcr */
+ nlm_write_uart_reg(base, UART_LINE_CTL, lcr);
+}
+
+static inline void
+nlm_uart_outbyte(uint64_t base, char c)
+{
+ uint32_t lsr;
+
+ for (;;) {
+ lsr = nlm_read_uart_reg(base, UART_LINE_STS);
+ if (lsr & 0x20)
+ break;
+ }
+
+ nlm_write_uart_reg(base, UART_TX_DATA, (int)c);
+}
+
+static inline char
+nlm_uart_inbyte(uint64_t base)
+{
+ int data, lsr;
+
+ for (;;) {
+ lsr = nlm_read_uart_reg(base, UART_LINE_STS);
+ if (lsr & 0x80) { /* parity/frame/break-error - push a zero */
+ data = 0;
+ break;
+ }
+ if (lsr & 0x01) { /* Rx data */
+ data = nlm_read_uart_reg(base, UART_RX_DATA);
+ break;
+ }
+ }
+
+ return (char)data;
+}
+
+static inline int
+nlm_uart_init(uint64_t base, int baud, int databits, int stopbits,
+ int parity, int int_en, int loopback)
+{
+ uint32_t lcr;
+
+ lcr = 0;
+ if (databits >= 8)
+ lcr |= LCR_8BITS;
+ else if (databits == 7)
+ lcr |= LCR_7BITS;
+ else if (databits == 6)
+ lcr |= LCR_6BITS;
+ else
+ lcr |= LCR_5BITS;
+
+ if (stopbits > 1)
+ lcr |= LCR_STOPB;
+
+ lcr |= parity << 3;
+
+ /* setup default lcr */
+ nlm_write_uart_reg(base, UART_LINE_CTL, lcr);
+
+ /* Reset the FIFOs */
+ nlm_write_uart_reg(base, UART_LINE_CTL, FCR_RCV_RST | FCR_XMT_RST);
+
+ nlm_uart_set_baudrate(base, baud);
+
+ if (loopback)
+ nlm_write_uart_reg(base, UART_MODEM_CTL, 0x1f);
+
+ if (int_en)
+ nlm_write_uart_reg(base, UART_INT_EN, IER_ERXRDY | IER_ETXRDY);
+
+ return 0;
+}
+#endif /* !LOCORE && !__ASSEMBLY__ */
+#endif /* __XLP_HAL_UART_H__ */
Property changes on: trunk/sys/mips/nlm/hal/uart.h
___________________________________________________________________
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Added: trunk/sys/mips/nlm/hal/ucore_loader.h
===================================================================
--- trunk/sys/mips/nlm/hal/ucore_loader.h (rev 0)
+++ trunk/sys/mips/nlm/hal/ucore_loader.h 2018-05-26 21:55:02 UTC (rev 9987)
@@ -0,0 +1,142 @@
+/* $MidnightBSD$ */
+/*-
+ * Copyright (c) 2003-2012 Broadcom Corporation
+ * All Rights Reserved
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in
+ * the documentation and/or other materials provided with the
+ * distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY BROADCOM ``AS IS'' AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL BROADCOM OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
+ * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
+ * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
+ * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * $FreeBSD: stable/10/sys/mips/nlm/hal/ucore_loader.h 245884 2013-01-24 15:49:47Z jchandra $
+ */
+
+#ifndef __NLM_UCORE_LOADER_H__
+#define __NLM_UCORE_LOADER_H__
+
+/**
+* @file_name ucore_loader.h
+* @author Netlogic Microsystems
+* @brief Ucore loader API header
+*/
+
+#define CODE_SIZE_PER_UCORE (4 << 10)
+
+static __inline__ void
+nlm_ucore_load_image(uint64_t nae_base, int ucore)
+{
+ uint64_t addr = nae_base + NAE_UCORE_SHARED_RAM_OFFSET +
+ (ucore * CODE_SIZE_PER_UCORE);
+ uint32_t *p = (uint32_t *)ucore_app_bin;
+ int i, size;
+
+ size = sizeof(ucore_app_bin)/sizeof(uint32_t);
+ for (i = 0; i < size; i++, addr += 4)
+ nlm_store_word_daddr(addr, htobe32(p[i]));
+
+ /* add a 'nop' if number of instructions are odd */
+ if (size & 0x1)
+ nlm_store_word_daddr(addr, 0x0);
+}
+
+static __inline int
+nlm_ucore_write_sharedmem(uint64_t nae_base, int index, uint32_t data)
+{
+ uint32_t ucore_cfg;
+ uint64_t addr = nae_base + NAE_UCORE_SHARED_RAM_OFFSET;
+
+ if (index > 128)
+ return (-1);
+
+ ucore_cfg = nlm_read_nae_reg(nae_base, NAE_RX_UCORE_CFG);
+ /* set iram to zero */
+ nlm_write_nae_reg(nae_base, NAE_RX_UCORE_CFG,
+ (ucore_cfg & ~(0x1 << 7)));
+
+ nlm_store_word_daddr(addr + (index * 4), data);
+
+ /* restore ucore config */
+ nlm_write_nae_reg(nae_base, NAE_RX_UCORE_CFG, ucore_cfg);
+ return (0);
+}
+
+static __inline uint32_t
+nlm_ucore_read_sharedmem(uint64_t nae_base, int index)
+{
+ uint64_t addr = nae_base + NAE_UCORE_SHARED_RAM_OFFSET;
+ uint32_t ucore_cfg, val;
+
+ ucore_cfg = nlm_read_nae_reg(nae_base, NAE_RX_UCORE_CFG);
+ /* set iram to zero */
+ nlm_write_nae_reg(nae_base, NAE_RX_UCORE_CFG,
+ (ucore_cfg & ~(0x1 << 7)));
+
+ val = nlm_load_word_daddr(addr + (index * 4));
+
+ /* restore ucore config */
+ nlm_write_nae_reg(nae_base, NAE_RX_UCORE_CFG, ucore_cfg);
+
+ return val;
+}
+
+static __inline__ int
+nlm_ucore_load_all(uint64_t nae_base, uint32_t ucore_mask, int nae_reset_done)
+{
+ int i, count = 0;
+ uint32_t mask;
+ uint32_t ucore_cfg = 0;
+
+ mask = ucore_mask & 0xffff;
+
+ /* Stop all ucores */
+ if (nae_reset_done == 0) { /* Skip the Ucore reset if NAE reset is done */
+ ucore_cfg = nlm_read_nae_reg(nae_base, NAE_RX_UCORE_CFG);
+ nlm_write_nae_reg(nae_base, NAE_RX_UCORE_CFG,
+ ucore_cfg | (1 << 24));
+
+ /* poll for ucore to get in to a wait state */
+ do {
+ ucore_cfg = nlm_read_nae_reg(nae_base,
+ NAE_RX_UCORE_CFG);
+ } while ((ucore_cfg & (1 << 25)) == 0);
+ }
+
+ for (i = 0; i < sizeof(ucore_mask) * NBBY; i++) {
+ if ((mask & (1 << i)) == 0)
+ continue;
+ nlm_ucore_load_image(nae_base, i);
+ count++;
+ }
+
+ /* Enable per-domain ucores */
+ ucore_cfg = nlm_read_nae_reg(nae_base, NAE_RX_UCORE_CFG);
+
+ /* write one to reset bits to put the ucores in reset */
+ ucore_cfg = ucore_cfg | (((mask) & 0xffff) << 8);
+ nlm_write_nae_reg(nae_base, NAE_RX_UCORE_CFG, ucore_cfg);
+
+ /* write zero to reset bits to pull them out of reset */
+ ucore_cfg = ucore_cfg & (~(((mask) & 0xffff) << 8)) & ~(1 << 24);
+ nlm_write_nae_reg(nae_base, NAE_RX_UCORE_CFG, ucore_cfg);
+
+ return (count);
+}
+#endif
Property changes on: trunk/sys/mips/nlm/hal/ucore_loader.h
___________________________________________________________________
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+text/plain
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Added: trunk/sys/mips/nlm/hal/usb.h
===================================================================
--- trunk/sys/mips/nlm/hal/usb.h (rev 0)
+++ trunk/sys/mips/nlm/hal/usb.h 2018-05-26 21:55:02 UTC (rev 9987)
@@ -0,0 +1,60 @@
+/* $MidnightBSD$ */
+/*-
+ * Copyright 2003-2011 Netlogic Microsystems (Netlogic). All rights
+ * reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in
+ * the documentation and/or other materials provided with the
+ * distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY Netlogic Microsystems ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL NETLOGIC OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
+ * THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * NETLOGIC_BSD
+ * $FreeBSD: stable/10/sys/mips/nlm/hal/usb.h 225394 2011-09-05 10:45:29Z jchandra $
+ */
+
+#ifndef __NLM_USB_H__
+#define __NLM_USB_H__
+
+#define USB_CTL_0 0x01
+#define USB_PHY_0 0x0A
+#define USB_PHY_RESET 0x01
+#define USB_PHY_PORT_RESET_0 0x10
+#define USB_PHY_PORT_RESET_1 0x20
+#define USB_CONTROLLER_RESET 0x01
+#define USB_INT_STATUS 0x0E
+#define USB_INT_EN 0x0F
+#define USB_PHY_INTERRUPT_EN 0x01
+#define USB_OHCI_INTERRUPT_EN 0x02
+#define USB_OHCI_INTERRUPT1_EN 0x04
+#define USB_OHCI_INTERRUPT2_EN 0x08
+#define USB_CTRL_INTERRUPT_EN 0x10
+
+
+#if !defined(LOCORE) && !defined(__ASSEMBLY__)
+
+#define nlm_read_usb_reg(b, r) nlm_read_reg(b,r)
+#define nlm_write_usb_reg(b, r, v) nlm_write_reg(b,r,v)
+#define nlm_get_usb_pcibase(node, inst) nlm_pcicfg_base(XLP_IO_USB_OFFSET(node, inst))
+#define nlm_get_usb_hcd_base(node, inst) nlm_xkphys_map_pcibar0(nlm_get_usb_pcibase(node, inst))
+#define nlm_get_usb_regbase(node, inst) (nlm_get_usb_pcibase(node, inst) + XLP_IO_PCI_HDRSZ)
+
+#endif
+#endif
Property changes on: trunk/sys/mips/nlm/hal/usb.h
___________________________________________________________________
Added: svn:eol-style
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+native
\ No newline at end of property
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+MidnightBSD=%H
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## -0,0 +1 ##
+text/plain
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Added: trunk/sys/mips/nlm/hal/xaui.h
===================================================================
--- trunk/sys/mips/nlm/hal/xaui.h (rev 0)
+++ trunk/sys/mips/nlm/hal/xaui.h 2018-05-26 21:55:02 UTC (rev 9987)
@@ -0,0 +1,194 @@
+/* $MidnightBSD$ */
+/*-
+ * Copyright (c) 2003-2012 Broadcom Corporation
+ * All Rights Reserved
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in
+ * the documentation and/or other materials provided with the
+ * distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY BROADCOM ``AS IS'' AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL BROADCOM OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
+ * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
+ * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
+ * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * $FreeBSD: stable/10/sys/mips/nlm/hal/xaui.h 233545 2012-03-27 14:05:12Z jchandra $
+ */
+#ifndef __NLM_XAUI_H__
+#define __NLM_XAUI_H__
+
+/**
+* @file_name xaui.h
+* @author Netlogic Microsystems
+* @brief Basic definitions of XLP XAUI ports
+*/
+#define XAUI_CONFIG0(block) NAE_REG(block, 4, 0x00)
+#define XAUI_CONFIG1(block) NAE_REG(block, 4, 0x01)
+#define XAUI_CONFIG2(block) NAE_REG(block, 4, 0x02)
+#define XAUI_CONFIG3(block) NAE_REG(block, 4, 0x03)
+/*
+#define XAUI_MAC_ADDR0_LO(block) NAE_REG(block, 4, 0x04)
+#define XAUI_MAC_ADDR0_HI(block) NAE_REG(block, 4, 0x05)
+*/
+#define XAUI_MAX_FRAME_LEN(block) NAE_REG(block, 4, 0x08)
+#define XAUI_REVISION_LVL(block) NAE_REG(block, 4, 0x0b)
+#define XAUI_MII_MGMT_CMD(block) NAE_REG(block, 4, 0x10)
+#define XAUI_MII_MGMT_FIELD(block) NAE_REG(block, 4, 0x11)
+#define XAUI_MII_MGMT_CFG(block) NAE_REG(block, 4, 0x12)
+#define XAUI_MIIM_LINK_FALL_VEC(block) NAE_REG(block, 4, 0x13)
+#define XAUI_MII_MGMT_IND(block) NAE_REG(block, 4, 0x14)
+#define XAUI_STATS_MLR(block) NAE_REG(block, 4, 0x1f)
+#define XAUI_STATS_TR64(block) NAE_REG(block, 4, 0x20)
+#define XAUI_STATS_TR127(block) NAE_REG(block, 4, 0x21)
+#define XAUI_STATS_TR255(block) NAE_REG(block, 4, 0x22)
+#define XAUI_STATS_TR511(block) NAE_REG(block, 4, 0x23)
+#define XAUI_STATS_TR1K(block) NAE_REG(block, 4, 0x24)
+#define XAUI_STATS_TRMAX(block) NAE_REG(block, 4, 0x25)
+#define XAUI_STATS_TRMGV(block) NAE_REG(block, 4, 0x26)
+#define XAUI_STATS_RBYT(block) NAE_REG(block, 4, 0x27)
+#define XAUI_STATS_RPKT(block) NAE_REG(block, 4, 0x28)
+#define XAUI_STATS_RFCS(block) NAE_REG(block, 4, 0x29)
+#define XAUI_STATS_RMCA(block) NAE_REG(block, 4, 0x2a)
+#define XAUI_STATS_RBCA(block) NAE_REG(block, 4, 0x2b)
+#define XAUI_STATS_RXCF(block) NAE_REG(block, 4, 0x2c)
+#define XAUI_STATS_RXPF(block) NAE_REG(block, 4, 0x2d)
+#define XAUI_STATS_RXUO(block) NAE_REG(block, 4, 0x2e)
+#define XAUI_STATS_RALN(block) NAE_REG(block, 4, 0x2f)
+#define XAUI_STATS_RFLR(block) NAE_REG(block, 4, 0x30)
+#define XAUI_STATS_RCDE(block) NAE_REG(block, 4, 0x31)
+#define XAUI_STATS_RCSE(block) NAE_REG(block, 4, 0x32)
+#define XAUI_STATS_RUND(block) NAE_REG(block, 4, 0x33)
+#define XAUI_STATS_ROVR(block) NAE_REG(block, 4, 0x34)
+#define XAUI_STATS_RFRG(block) NAE_REG(block, 4, 0x35)
+#define XAUI_STATS_RJBR(block) NAE_REG(block, 4, 0x36)
+#define XAUI_STATS_TBYT(block) NAE_REG(block, 4, 0x38)
+#define XAUI_STATS_TPKT(block) NAE_REG(block, 4, 0x39)
+#define XAUI_STATS_TMCA(block) NAE_REG(block, 4, 0x3a)
+#define XAUI_STATS_TBCA(block) NAE_REG(block, 4, 0x3b)
+#define XAUI_STATS_TXPF(block) NAE_REG(block, 4, 0x3c)
+#define XAUI_STATS_TDFR(block) NAE_REG(block, 4, 0x3d)
+#define XAUI_STATS_TEDF(block) NAE_REG(block, 4, 0x3e)
+#define XAUI_STATS_TSCL(block) NAE_REG(block, 4, 0x3f)
+#define XAUI_STATS_TMCL(block) NAE_REG(block, 4, 0x40)
+#define XAUI_STATS_TLCL(block) NAE_REG(block, 4, 0x41)
+#define XAUI_STATS_TXCL(block) NAE_REG(block, 4, 0x42)
+#define XAUI_STATS_TNCL(block) NAE_REG(block, 4, 0x43)
+#define XAUI_STATS_TJBR(block) NAE_REG(block, 4, 0x46)
+#define XAUI_STATS_TFCS(block) NAE_REG(block, 4, 0x47)
+#define XAUI_STATS_TXCF(block) NAE_REG(block, 4, 0x48)
+#define XAUI_STATS_TOVR(block) NAE_REG(block, 4, 0x49)
+#define XAUI_STATS_TUND(block) NAE_REG(block, 4, 0x4a)
+#define XAUI_STATS_TFRG(block) NAE_REG(block, 4, 0x4b)
+#define XAUI_STATS_CAR1(block) NAE_REG(block, 4, 0x4c)
+#define XAUI_STATS_CAR2(block) NAE_REG(block, 4, 0x4d)
+#define XAUI_STATS_CAM1(block) NAE_REG(block, 4, 0x4e)
+#define XAUI_STATS_CAM2(block) NAE_REG(block, 4, 0x4f)
+#define XAUI_MAC_ADDR0_LO(block) NAE_REG(block, 4, 0x50)
+#define XAUI_MAC_ADDR0_HI(block) NAE_REG(block, 4, 0x51)
+#define XAUI_MAC_ADDR1_LO(block) NAE_REG(block, 4, 0x52)
+#define XAUI_MAC_ADDR1_HI(block) NAE_REG(block, 4, 0x53)
+#define XAUI_MAC_ADDR2_LO(block) NAE_REG(block, 4, 0x54)
+#define XAUI_MAC_ADDR2_HI(block) NAE_REG(block, 4, 0x55)
+#define XAUI_MAC_ADDR3_LO(block) NAE_REG(block, 4, 0x56)
+#define XAUI_MAC_ADDR3_HI(block) NAE_REG(block, 4, 0x57)
+#define XAUI_MAC_ADDR_MASK0_LO(block) NAE_REG(block, 4, 0x58)
+#define XAUI_MAC_ADDR_MASK0_HI(block) NAE_REG(block, 4, 0x59)
+#define XAUI_MAC_ADDR_MASK1_LO(block) NAE_REG(block, 4, 0x5a)
+#define XAUI_MAC_ADDR_MASK1_HI(block) NAE_REG(block, 4, 0x5b)
+#define XAUI_MAC_FILTER_CFG(block) NAE_REG(block, 4, 0x5c)
+#define XAUI_HASHTBL_VEC_B31_0(block) NAE_REG(block, 4, 0x60)
+#define XAUI_HASHTBL_VEC_B63_32(block) NAE_REG(block, 4, 0x61)
+#define XAUI_HASHTBL_VEC_B95_64(block) NAE_REG(block, 4, 0x62)
+#define XAUI_HASHTBL_VEC_B127_96(block) NAE_REG(block, 4, 0x63)
+#define XAUI_HASHTBL_VEC_B159_128(block) NAE_REG(block, 4, 0x64)
+#define XAUI_HASHTBL_VEC_B191_160(block) NAE_REG(block, 4, 0x65)
+#define XAUI_HASHTBL_VEC_B223_192(block) NAE_REG(block, 4, 0x66)
+#define XAUI_HASHTBL_VEC_B255_224(block) NAE_REG(block, 4, 0x67)
+#define XAUI_HASHTBL_VEC_B287_256(block) NAE_REG(block, 4, 0x68)
+#define XAUI_HASHTBL_VEC_B319_288(block) NAE_REG(block, 4, 0x69)
+#define XAUI_HASHTBL_VEC_B351_320(block) NAE_REG(block, 4, 0x6a)
+#define XAUI_HASHTBL_VEC_B383_352(block) NAE_REG(block, 4, 0x6b)
+#define XAUI_HASHTBL_VEC_B415_384(block) NAE_REG(block, 4, 0x6c)
+#define XAUI_HASHTBL_VEC_B447_416(block) NAE_REG(block, 4, 0x6d)
+#define XAUI_HASHTBL_VEC_B479_448(block) NAE_REG(block, 4, 0x6e)
+#define XAUI_HASHTBL_VEC_B511_480(block) NAE_REG(block, 4, 0x6f)
+
+#define XAUI_NETIOR_XGMAC_MISC0(block) NAE_REG(block, 4, 0x76)
+#define XAUI_NETIOR_RX_ABORT_DROP_COUNT(block) NAE_REG(block, 4, 0x77)
+#define XAUI_NETIOR_MACCTRL_PAUSE_QUANTA(block) NAE_REG(block, 4, 0x78)
+#define XAUI_NETIOR_MACCTRL_OPCODE(block) NAE_REG(block, 4, 0x79)
+#define XAUI_NETIOR_MAC_DA_H(block) NAE_REG(block, 4, 0x7a)
+#define XAUI_NETIOR_MAC_DA_L(block) NAE_REG(block, 4, 0x7b)
+#define XAUI_NETIOR_XGMAC_STAT(block) NAE_REG(block, 4, 0x7c)
+#define XAUI_NETIOR_XGMAC_CTRL3(block) NAE_REG(block, 4, 0x7d)
+#define XAUI_NETIOR_XGMAC_CTRL2(block) NAE_REG(block, 4, 0x7e)
+#define XAUI_NETIOR_XGMAC_CTRL1(block) NAE_REG(block, 4, 0x7f)
+
+#define LANE_RX_CLK (1 << 0)
+#define LANE_TX_CLK (1 << 6)
+
+#define XAUI_LANE_FAULT 0x400
+#define XAUI_CONFIG_0 0
+
+#define XAUI_CONFIG_MACRST 0x80000000
+#define XAUI_CONFIG_RSTRCTL 0x00400000
+#define XAUI_CONFIG_RSTRFN 0x00200000
+#define XAUI_CONFIG_RSTTCTL 0x00040000
+#define XAUI_CONFIG_RSTTFN 0x00020000
+#define XAUI_CONFIG_RSTMIIM 0x00010000
+
+#define XAUI_CONFIG_1 1
+
+#define XAUI_CONFIG_TCTLEN 0x80000000
+#define XAUI_CONFIG_TFEN 0x40000000
+#define XAUI_CONFIG_RCTLEN 0x20000000
+#define XAUI_CONFIG_RFEN 0x10000000
+#define XAUI_CONFIG_DRPLT64 0x00000020
+#define XAUI_CONFIG_LENCHK 0x00000008
+#define XAUI_CONFIG_GENFCS 0x00000004
+#define XAUI_CONFIG_PAD_0 0x00000000
+#define XAUI_CONFIG_PAD_64 0x00000001
+#define XAUI_CONFIG_PAD_COND 0x00000002
+#define XAUI_CONFIG_PAD_68 0x00000003
+
+#define XAUI_PHY_CTRL_1 0x00
+
+#define NETIOR_XGMAC_CTRL1 0x7F
+#define NETIOR_XGMAC_CTRL3 0x7D
+
+#define NETIOR_XGMAC_VLAN_DC_POS 28
+#define NETIOR_XGMAC_PHYADDR_POS 23
+#define NETIOR_XGMAC_DEVID_POS 18
+#define NETIOR_XGMAC_STATS_EN_POS 17
+#define NETIOR_XGMAC_TX_PFC_EN_POS 14
+#define NETIOR_XGMAC_RX_PFC_EN_POS 13
+#define NETIOR_XGMAC_SOFT_RST_POS 11
+#define NETIOR_XGMAC_TX_PAUSE_POS 10
+
+#define NETIOR_XGMAC_STATS_CLR_POS 16
+
+#if !defined(LOCORE) && !defined(__ASSEMBLY__)
+
+void nlm_xaui_pcs_init(uint64_t, int);
+void nlm_nae_setup_rx_mode_xaui(uint64_t, int, int, int, int, int, int, int);
+void nlm_nae_setup_mac_addr_xaui(uint64_t, int, int, int, unsigned char *);
+void nlm_config_xaui_mtu(uint64_t, int, int, int);
+void nlm_config_xaui(uint64_t, int, int, int, int);
+
+#endif /* !(LOCORE) && !(__ASSEMBLY__) */
+
+#endif
Property changes on: trunk/sys/mips/nlm/hal/xaui.h
___________________________________________________________________
Added: svn:eol-style
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+native
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## -0,0 +1 ##
+MidnightBSD=%H
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## -0,0 +1 ##
+text/plain
\ No newline at end of property
Added: trunk/sys/mips/nlm/interrupt.h
===================================================================
--- trunk/sys/mips/nlm/interrupt.h (rev 0)
+++ trunk/sys/mips/nlm/interrupt.h 2018-05-26 21:55:02 UTC (rev 9987)
@@ -0,0 +1,51 @@
+/* $MidnightBSD$ */
+/*-
+ * Copyright 2003-2011 Netlogic Microsystems (Netlogic). All rights
+ * reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in
+ * the documentation and/or other materials provided with the
+ * distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY Netlogic Microsystems ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL NETLOGIC OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
+ * THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * NETLOGIC_BSD
+ * $FreeBSD: stable/10/sys/mips/nlm/interrupt.h 225394 2011-09-05 10:45:29Z jchandra $
+ */
+
+#ifndef _RMI_INTERRUPT_H_
+#define _RMI_INTERRUPT_H_
+
+/* Defines for the IRQ numbers */
+
+#define IRQ_IPI 41 /* 8-39 are mapped by PIC intr 0-31 */
+#define IRQ_MSGRING 6
+#define IRQ_TIMER 7
+
+/*
+ * XLR needs custom pre and post handlers for PCI/PCI-e interrupts
+ * XXX: maybe follow i386 intsrc model
+ */
+void xlp_establish_intr(const char *name, driver_filter_t filt,
+ driver_intr_t handler, void *arg, int irq, int flags,
+ void **cookiep, void (*busack)(int));
+void xlp_enable_irq(int irq);
+
+#endif /* _RMI_INTERRUPT_H_ */
Property changes on: trunk/sys/mips/nlm/interrupt.h
___________________________________________________________________
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Added: trunk/sys/mips/nlm/intr_machdep.c
===================================================================
--- trunk/sys/mips/nlm/intr_machdep.c (rev 0)
+++ trunk/sys/mips/nlm/intr_machdep.c 2018-05-26 21:55:02 UTC (rev 9987)
@@ -0,0 +1,254 @@
+/* $MidnightBSD$ */
+/*-
+ * Copyright 2003-2011 Netlogic Microsystems (Netlogic). All rights
+ * reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in
+ * the documentation and/or other materials provided with the
+ * distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY Netlogic Microsystems ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL NETLOGIC OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
+ * THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * NETLOGIC_BSD */
+
+#include <sys/cdefs.h>
+__FBSDID("$FreeBSD: stable/10/sys/mips/nlm/intr_machdep.c 233563 2012-03-27 15:39:55Z jchandra $");
+
+#include <sys/param.h>
+#include <sys/systm.h>
+#include <sys/bus.h>
+#include <sys/interrupt.h>
+#include <sys/kernel.h>
+
+#include <machine/cpu.h>
+#include <machine/cpufunc.h>
+#include <machine/cpuinfo.h>
+#include <machine/cpuregs.h>
+#include <machine/frame.h>
+#include <machine/intr_machdep.h>
+#include <machine/md_var.h>
+#include <machine/trap.h>
+#include <machine/hwfunc.h>
+
+#include <mips/nlm/hal/haldefs.h>
+#include <mips/nlm/hal/iomap.h>
+#include <mips/nlm/hal/mips-extns.h>
+#include <mips/nlm/interrupt.h>
+#include <mips/nlm/hal/pic.h>
+#include <mips/nlm/xlp.h>
+
+struct xlp_intrsrc {
+ void (*busack)(int); /* Additional ack */
+ struct intr_event *ie; /* event corresponding to intr */
+ int irq;
+};
+
+static struct xlp_intrsrc xlp_interrupts[XLR_MAX_INTR];
+static mips_intrcnt_t mips_intr_counters[XLR_MAX_INTR];
+static int intrcnt_index;
+
+void
+xlp_enable_irq(int irq)
+{
+ uint64_t eimr;
+
+ eimr = nlm_read_c0_eimr();
+ nlm_write_c0_eimr(eimr | (1ULL << irq));
+}
+
+void
+cpu_establish_softintr(const char *name, driver_filter_t * filt,
+ void (*handler) (void *), void *arg, int irq, int flags,
+ void **cookiep)
+{
+
+ panic("Soft interrupts unsupported!\n");
+}
+
+void
+cpu_establish_hardintr(const char *name, driver_filter_t * filt,
+ void (*handler) (void *), void *arg, int irq, int flags,
+ void **cookiep)
+{
+
+ xlp_establish_intr(name, filt, handler, arg, irq, flags,
+ cookiep, NULL);
+}
+
+static void
+xlp_post_filter(void *source)
+{
+ struct xlp_intrsrc *src = source;
+
+ if (src->busack)
+ src->busack(src->irq);
+ nlm_pic_ack(xlp_pic_base, xlp_irq_to_irt(src->irq));
+}
+
+static void
+xlp_pre_ithread(void *source)
+{
+ struct xlp_intrsrc *src = source;
+
+ if (src->busack)
+ src->busack(src->irq);
+}
+
+static void
+xlp_post_ithread(void *source)
+{
+ struct xlp_intrsrc *src = source;
+
+ nlm_pic_ack(xlp_pic_base, xlp_irq_to_irt(src->irq));
+}
+
+void
+xlp_establish_intr(const char *name, driver_filter_t filt,
+ driver_intr_t handler, void *arg, int irq, int flags,
+ void **cookiep, void (*busack)(int))
+{
+ struct intr_event *ie; /* descriptor for the IRQ */
+ struct xlp_intrsrc *src = NULL;
+ int errcode;
+
+ if (irq < 0 || irq > XLR_MAX_INTR)
+ panic("%s called for unknown hard intr %d", __func__, irq);
+
+ /*
+ * FIXME locking - not needed now, because we do this only on
+ * startup from CPU0
+ */
+ src = &xlp_interrupts[irq];
+ ie = src->ie;
+ if (ie == NULL) {
+ /*
+ * PIC based interrupts need ack in PIC, and some SoC
+ * components need additional acks (e.g. PCI)
+ */
+ if (XLP_IRQ_IS_PICINTR(irq))
+ errcode = intr_event_create(&ie, src, 0, irq,
+ xlp_pre_ithread, xlp_post_ithread, xlp_post_filter,
+ NULL, "hard intr%d:", irq);
+ else {
+ if (filt == NULL)
+ panic("Unsupported non filter percpu intr %d", irq);
+ errcode = intr_event_create(&ie, src, 0, irq,
+ NULL, NULL, NULL, NULL, "hard intr%d:", irq);
+ }
+ if (errcode) {
+ printf("Could not create event for intr %d\n", irq);
+ return;
+ }
+ src->irq = irq;
+ src->busack = busack;
+ src->ie = ie;
+ }
+ intr_event_add_handler(ie, name, filt, handler, arg,
+ intr_priority(flags), flags, cookiep);
+ xlp_enable_irq(irq);
+}
+
+void
+cpu_intr(struct trapframe *tf)
+{
+ struct intr_event *ie;
+ uint64_t eirr, eimr;
+ int i;
+
+ critical_enter();
+
+ /* find a list of enabled interrupts */
+ eirr = nlm_read_c0_eirr();
+ eimr = nlm_read_c0_eimr();
+ eirr &= eimr;
+
+ if (eirr == 0) {
+ critical_exit();
+ return;
+ }
+ /*
+ * No need to clear the EIRR here as the handler writes to
+ * compare which ACKs the interrupt.
+ */
+ if (eirr & (1 << IRQ_TIMER)) {
+ intr_event_handle(xlp_interrupts[IRQ_TIMER].ie, tf);
+ critical_exit();
+ return;
+ }
+
+ /* FIXME sched pin >? LOCK>? */
+ for (i = sizeof(eirr) * 8 - 1; i >= 0; i--) {
+ if ((eirr & (1ULL << i)) == 0)
+ continue;
+
+ ie = xlp_interrupts[i].ie;
+ /* Don't account special IRQs */
+ switch (i) {
+ case IRQ_IPI:
+ case IRQ_MSGRING:
+ break;
+ default:
+ mips_intrcnt_inc(mips_intr_counters[i]);
+ }
+
+ /* Ack the IRQ on the CPU */
+ nlm_write_c0_eirr(1ULL << i);
+ if (intr_event_handle(ie, tf) != 0) {
+ printf("stray interrupt %d\n", i);
+ }
+ }
+ critical_exit();
+}
+
+void
+mips_intrcnt_setname(mips_intrcnt_t counter, const char *name)
+{
+ int idx = counter - intrcnt;
+
+ KASSERT(counter != NULL, ("mips_intrcnt_setname: NULL counter"));
+
+ snprintf(intrnames + (MAXCOMLEN + 1) * idx,
+ MAXCOMLEN + 1, "%-*s", MAXCOMLEN, name);
+}
+
+mips_intrcnt_t
+mips_intrcnt_create(const char* name)
+{
+ mips_intrcnt_t counter = &intrcnt[intrcnt_index++];
+
+ mips_intrcnt_setname(counter, name);
+ return counter;
+}
+
+void
+cpu_init_interrupts()
+{
+ int i;
+ char name[MAXCOMLEN + 1];
+
+ /*
+ * Initialize all available vectors so spare IRQ
+ * would show up in systat output
+ */
+ for (i = 0; i < XLR_MAX_INTR; i++) {
+ snprintf(name, MAXCOMLEN + 1, "int%d:", i);
+ mips_intr_counters[i] = mips_intrcnt_create(name);
+ }
+}
Property changes on: trunk/sys/mips/nlm/intr_machdep.c
___________________________________________________________________
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+text/plain
\ No newline at end of property
Added: trunk/sys/mips/nlm/mpreset.S
===================================================================
--- trunk/sys/mips/nlm/mpreset.S (rev 0)
+++ trunk/sys/mips/nlm/mpreset.S 2018-05-26 21:55:02 UTC (rev 9987)
@@ -0,0 +1,202 @@
+/* $MidnightBSD$ */
+/*-
+ * Copyright 2003-2011 Netlogic Microsystems (Netlogic). All rights
+ * reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in
+ * the documentation and/or other materials provided with the
+ * distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY Netlogic Microsystems ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL NETLOGIC OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
+ * THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * NETLOGIC_BSD
+ * $FreeBSD: stable/10/sys/mips/nlm/mpreset.S 233535 2012-03-27 07:51:42Z jchandra $
+ */
+
+#include <machine/asm.h>
+#include <machine/cpu.h>
+#include <machine/cpuregs.h>
+#include <mips/nlm/hal/iomap.h>
+#include <mips/nlm/hal/sys.h>
+#include <mips/nlm/hal/cpucontrol.h>
+
+#define SYS_REG_KSEG1(node, reg) (0xa0000000 + XLP_DEFAULT_IO_BASE + \
+ XLP_IO_SYS_OFFSET(node) + XLP_IO_PCI_HDRSZ + (reg) * 4)
+#include "assym.s"
+
+ .text
+ .set noat
+ .set noreorder
+ .set mips64
+
+#define MFCR(rt,rs) .word ((0x1c<<26)|((rs)<<21)|((rt)<<16)|(0x18))
+#define MTCR(rt,rs) .word ((0x1c<<26)|((rs)<<21)|((rt)<<16)|(0x19))
+/*
+ * We need to do this to really flush the dcache before splitting it
+ */
+.macro flush_l1_dcache
+ .set push
+ .set noreorder
+ li $8, LSU_DEBUG_DATA0 /* use register number to handle */
+ li $9, LSU_DEBUG_ADDR /* different ABIs */
+ li t2, 0 /* index */
+ li t3, 0x1000 /* loop count, 512 sets * 8 whatever? */
+1:
+ sll v0, t2, 5
+ MTCR(0, 8)
+ ori v1, v0, 0x3 /* way0 | write_enable | write_active */
+ MTCR(3, 9)
+2:
+ MFCR(3, 9)
+ andi v1, 0x1 /* wait for write_active == 0 */
+ bnez v1, 2b
+ nop
+ MTCR(0, 8)
+ ori v1, v0, 0x7 /* way1 | write_enable | write_active */
+ MTCR(3, 9)
+3:
+ MFCR(3, 9)
+ andi v1, 0x1 /* wait for write_active == 0 */
+ bnez v1, 3b
+ nop
+ addi t2, 1
+ bne t3, t2, 1b
+ nop
+ .set pop
+.endm
+
+VECTOR(XLPResetEntry, unknown)
+ mfc0 t0, MIPS_COP_0_STATUS
+ li t1, 0x80000
+ and t1, t0, t1
+ bnez t1, nmi_handler
+ nop
+
+#ifdef SMP
+ /* Reset entry for secordary cores */
+ mfc0 t0, MIPS_COP_0_PRID, 1
+ srl t0, t0, 2 /* discard thread id */
+ andi t0, t0, 0x7 /* core id */
+ li t1, 1
+ sll t0, t1, t0
+ nor t0, t0, zero /* mask with core id bit clear */
+
+ /* clear CPU non-coherent bit */
+ li t2, SYS_REG_KSEG1(0, SYS_CPU_NONCOHERENT_MODE)
+ lw t1, 0(t2)
+ and t1, t1, t0
+ sw t1, 0(t2)
+ lw t1, 0(t2) /* read-back ensures operation complete */
+ sync
+
+ dla t2, mpentry
+ jr t2
+ nop
+#endif
+ nop
+ /* NOT REACHED */
+VECTOR_END(XLPResetEntry)
+
+
+ /* Not yet */
+nmi_handler:
+ nop
+ nop
+ j nmi_handler
+
+#ifdef SMP
+ /*
+ * Enable other threads in the core, called from thread 0
+ * of the core
+ */
+LEAF(xlp_enable_threads)
+ /*
+ * Save and restore callee saved registers of all ABIs
+ * Enabling threads trashes the registers
+ */
+ dmtc0 sp, $4, 2 /* SP saved in UserLocal */
+ ori sp, sp, 0x7
+ xori sp, sp, 0x7 /* align 64 bit */
+ addiu sp, sp, -128
+ mfc0 t1, MIPS_COP_0_STATUS
+ sd s0, 0(sp)
+ sd s1, 8(sp)
+ sd s2, 16(sp)
+ sd s3, 24(sp)
+ sd s4, 32(sp)
+ sd s5, 40(sp)
+ sd s6, 48(sp)
+ sd s7, 56(sp)
+ sd s8, 64(sp)
+ sd t1, 72(sp)
+ sd gp, 80(sp)
+ sd ra, 88(sp)
+
+ flush_l1_dcache
+
+ /* Use register number to work in o32 and n32 */
+ li $9, ((CPU_BLOCKID_MAP << 8) | MAP_THREADMODE)
+ move $8, a0
+ sync
+ MTCR(8, 9)
+ mfc0 t0, MIPS_COP_0_PRID, 1
+ andi t0, 0x3
+ beqz t0, 2f
+ nop
+ dla t1, mpentry /* child thread, go to hardware init */
+ jr t1
+ nop
+
+
+2: /*
+ * Parent hardware thread, restore registers, return
+ */
+#if 1
+ /*
+ * A0 Errata - Write MMU_SETUP after changing thread mode register.
+ */
+ li $9, 0x400
+ li $8, 0
+ MTCR(8, 9)
+ sll zero,3 /* ehb */
+#endif
+ dmfc0 t0, $4, 2 /* SP saved in UserLocal */
+ ori sp, t0, 0x7
+ xori sp, sp, 0x7 /* align 64 bit */
+ addiu sp, sp, -128
+ ld s0, 0(sp)
+ ld s1, 8(sp)
+ ld s2, 16(sp)
+ ld s3, 24(sp)
+ ld s4, 32(sp)
+ ld s5, 40(sp)
+ ld s6, 48(sp)
+ ld s7, 56(sp)
+ ld s8, 64(sp)
+ ld t1, 72(sp)
+ ld gp, 80(sp)
+ ld ra, 88(sp)
+ mfc0 t1, MIPS_COP_0_STATUS
+
+ move sp, t0 /* Restore the real SP */
+ jr.hb ra
+ nop
+END(xlp_enable_threads)
+#endif
Property changes on: trunk/sys/mips/nlm/mpreset.S
___________________________________________________________________
Added: svn:eol-style
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+MidnightBSD=%H
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Added: trunk/sys/mips/nlm/msgring.h
===================================================================
--- trunk/sys/mips/nlm/msgring.h (rev 0)
+++ trunk/sys/mips/nlm/msgring.h 2018-05-26 21:55:02 UTC (rev 9987)
@@ -0,0 +1,53 @@
+/* $MidnightBSD$ */
+/*-
+ * Copyright 2003-2011 Netlogic Microsystems (Netlogic). All rights
+ * reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in
+ * the documentation and/or other materials provided with the
+ * distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY Netlogic Microsystems ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL NETLOGIC OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
+ * THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * NETLOGIC_BSD
+ * $FreeBSD: stable/10/sys/mips/nlm/msgring.h 233545 2012-03-27 14:05:12Z jchandra $
+ */
+
+#ifndef _NLM_MSGRING_H
+#define _NLM_MSGRING_H
+#define CMS_DEFAULT_CREDIT 50
+/*
+ * packets are sent to VC 0 of a thread
+ * freebacks are sent to VC 3 of a thread
+ */
+#define XLPGE_RX_VC 0
+#define XLPGE_FB_VC 3
+
+extern uint32_t xlp_msg_thread_mask;
+
+struct nlm_fmn_msg;
+typedef void (*msgring_handler)(int, int, int, int, struct nlm_fmn_msg *, void *);
+
+int register_msgring_handler(int startb, int endb, msgring_handler action,
+ void *arg);
+int xlp_handle_msg_vc(u_int vcmask, int max_msgs);
+void xlp_msgring_cpu_init(int, int, int);
+void xlp_cms_enable_intr(int , int , int , int);
+#endif /* _NLM_MSGRING_H */
Property changes on: trunk/sys/mips/nlm/msgring.h
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+MidnightBSD=%H
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+text/plain
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Added: trunk/sys/mips/nlm/std.xlp
===================================================================
--- trunk/sys/mips/nlm/std.xlp (rev 0)
+++ trunk/sys/mips/nlm/std.xlp 2018-05-26 21:55:02 UTC (rev 9987)
@@ -0,0 +1,7 @@
+# $FreeBSD: stable/10/sys/mips/nlm/std.xlp 227663 2011-11-18 11:18:59Z jchandra $
+files "../nlm/files.xlp"
+cpu CPU_NLM
+
+# Devices needed always
+device uart
+device pci
Property changes on: trunk/sys/mips/nlm/std.xlp
___________________________________________________________________
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## -0,0 +1 ##
+MidnightBSD=%H
\ No newline at end of property
Added: trunk/sys/mips/nlm/tick.c
===================================================================
--- trunk/sys/mips/nlm/tick.c (rev 0)
+++ trunk/sys/mips/nlm/tick.c 2018-05-26 21:55:02 UTC (rev 9987)
@@ -0,0 +1,384 @@
+/* $MidnightBSD$ */
+/*-
+ * Copyright 2003-2011 Netlogic Microsystems (Netlogic). All rights
+ * reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in
+ * the documentation and/or other materials provided with the
+ * distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY Netlogic Microsystems ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL NETLOGIC OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
+ * THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * NETLOGIC_BSD */
+
+/*
+ * Simple driver for the 32-bit interval counter built in to all
+ * MIPS32 CPUs.
+ */
+
+#include <sys/cdefs.h>
+__FBSDID("$FreeBSD: stable/10/sys/mips/nlm/tick.c 265999 2014-05-14 01:35:43Z ian $");
+
+#include <sys/param.h>
+#include <sys/systm.h>
+#include <sys/sysctl.h>
+#include <sys/bus.h>
+#include <sys/kernel.h>
+#include <sys/module.h>
+#include <sys/rman.h>
+#include <sys/power.h>
+#include <sys/smp.h>
+#include <sys/time.h>
+#include <sys/timeet.h>
+#include <sys/timetc.h>
+
+#include <machine/hwfunc.h>
+#include <machine/clock.h>
+#include <machine/locore.h>
+#include <machine/md_var.h>
+#include <machine/intr_machdep.h>
+
+#include <mips/nlm/interrupt.h>
+
+uint64_t counter_freq;
+
+struct timecounter *platform_timecounter;
+
+static DPCPU_DEFINE(uint32_t, cycles_per_tick);
+static uint32_t cycles_per_usec;
+
+static DPCPU_DEFINE(volatile uint32_t, counter_upper);
+static DPCPU_DEFINE(volatile uint32_t, counter_lower_last);
+static DPCPU_DEFINE(uint32_t, compare_ticks);
+static DPCPU_DEFINE(uint32_t, lost_ticks);
+
+struct clock_softc {
+ int intr_rid;
+ struct resource *intr_res;
+ void *intr_handler;
+ struct timecounter tc;
+ struct eventtimer et;
+};
+static struct clock_softc *softc;
+
+/*
+ * Device methods
+ */
+static int clock_probe(device_t);
+static void clock_identify(driver_t *, device_t);
+static int clock_attach(device_t);
+static unsigned counter_get_timecount(struct timecounter *tc);
+
+void
+mips_timer_early_init(uint64_t clock_hz)
+{
+ /* Initialize clock early so that we can use DELAY sooner */
+ counter_freq = clock_hz;
+ cycles_per_usec = (clock_hz / (1000 * 1000));
+}
+
+void
+platform_initclocks(void)
+{
+
+ if (platform_timecounter != NULL)
+ tc_init(platform_timecounter);
+}
+
+static uint64_t
+tick_ticker(void)
+{
+ uint64_t ret;
+ uint32_t ticktock;
+ uint32_t t_lower_last, t_upper;
+
+ /*
+ * Disable preemption because we are working with cpu specific data.
+ */
+ critical_enter();
+
+ /*
+ * Note that even though preemption is disabled, interrupts are
+ * still enabled. In particular there is a race with clock_intr()
+ * reading the values of 'counter_upper' and 'counter_lower_last'.
+ *
+ * XXX this depends on clock_intr() being executed periodically
+ * so that 'counter_upper' and 'counter_lower_last' are not stale.
+ */
+ do {
+ t_upper = DPCPU_GET(counter_upper);
+ t_lower_last = DPCPU_GET(counter_lower_last);
+ } while (t_upper != DPCPU_GET(counter_upper));
+
+ ticktock = mips_rd_count();
+
+ critical_exit();
+
+ /* COUNT register wrapped around */
+ if (ticktock < t_lower_last)
+ t_upper++;
+
+ ret = ((uint64_t)t_upper << 32) | ticktock;
+ return (ret);
+}
+
+void
+mips_timer_init_params(uint64_t platform_counter_freq, int double_count)
+{
+
+ /*
+ * XXX: Do not use printf here: uart code 8250 may use DELAY so this
+ * function should be called before cninit.
+ */
+ counter_freq = platform_counter_freq;
+ /*
+ * XXX: Some MIPS32 cores update the Count register only every two
+ * pipeline cycles.
+ * We know this because of status registers in CP0, make it automatic.
+ */
+ if (double_count != 0)
+ counter_freq /= 2;
+
+ cycles_per_usec = counter_freq / (1 * 1000 * 1000);
+ set_cputicker(tick_ticker, counter_freq, 1);
+}
+
+static int
+sysctl_machdep_counter_freq(SYSCTL_HANDLER_ARGS)
+{
+ int error;
+ uint64_t freq;
+
+ if (softc == NULL)
+ return (EOPNOTSUPP);
+ freq = counter_freq;
+ error = sysctl_handle_64(oidp, &freq, sizeof(freq), req);
+ if (error == 0 && req->newptr != NULL) {
+ counter_freq = freq;
+ softc->et.et_frequency = counter_freq;
+ softc->tc.tc_frequency = counter_freq;
+ }
+ return (error);
+}
+
+SYSCTL_PROC(_machdep, OID_AUTO, counter_freq, CTLTYPE_U64 | CTLFLAG_RW,
+ NULL, 0, sysctl_machdep_counter_freq, "QU",
+ "Timecounter frequency in Hz");
+
+static unsigned
+counter_get_timecount(struct timecounter *tc)
+{
+
+ return (mips_rd_count());
+}
+
+/*
+ * Wait for about n microseconds (at least!).
+ */
+void
+DELAY(int n)
+{
+ uint32_t cur, last, delta, usecs;
+
+ /*
+ * This works by polling the timer and counting the number of
+ * microseconds that go by.
+ */
+ last = mips_rd_count();
+ delta = usecs = 0;
+
+ while (n > usecs) {
+ cur = mips_rd_count();
+
+ /* Check to see if the timer has wrapped around. */
+ if (cur < last)
+ delta += cur + (0xffffffff - last) + 1;
+ else
+ delta += cur - last;
+
+ last = cur;
+
+ if (delta >= cycles_per_usec) {
+ usecs += delta / cycles_per_usec;
+ delta %= cycles_per_usec;
+ }
+ }
+}
+
+static int
+clock_start(struct eventtimer *et, sbintime_t first, sbintime_t period)
+{
+ uint32_t fdiv, div, next;
+
+ if (period != 0)
+ div = (et->et_frequency * period) >> 32;
+ else
+ div = 0;
+ if (first != 0)
+ fdiv = (et->et_frequency * first) >> 32;
+ else
+ fdiv = div;
+ DPCPU_SET(cycles_per_tick, div);
+ next = mips_rd_count() + fdiv;
+ DPCPU_SET(compare_ticks, next);
+ mips_wr_compare(next);
+ return (0);
+}
+
+static int
+clock_stop(struct eventtimer *et)
+{
+
+ DPCPU_SET(cycles_per_tick, 0);
+ mips_wr_compare(0xffffffff);
+ return (0);
+}
+
+/*
+ * Device section of file below
+ */
+static int
+clock_intr(void *arg)
+{
+ struct clock_softc *sc = (struct clock_softc *)arg;
+ uint32_t cycles_per_tick;
+ uint32_t count, compare_last, compare_next, lost_ticks;
+
+ cycles_per_tick = DPCPU_GET(cycles_per_tick);
+ /*
+ * Set next clock edge.
+ */
+ count = mips_rd_count();
+ compare_last = DPCPU_GET(compare_ticks);
+ if (cycles_per_tick > 0) {
+ compare_next = count + cycles_per_tick;
+ DPCPU_SET(compare_ticks, compare_next);
+ mips_wr_compare(compare_next);
+ } else /* In one-shot mode timer should be stopped after the event. */
+ mips_wr_compare(0xffffffff);
+
+ /* COUNT register wrapped around */
+ if (count < DPCPU_GET(counter_lower_last)) {
+ DPCPU_SET(counter_upper, DPCPU_GET(counter_upper) + 1);
+ }
+ DPCPU_SET(counter_lower_last, count);
+
+ if (cycles_per_tick > 0) {
+
+ /*
+ * Account for the "lost time" between when the timer interrupt
+ * fired and when 'clock_intr' actually started executing.
+ */
+ lost_ticks = DPCPU_GET(lost_ticks);
+ lost_ticks += count - compare_last;
+
+ /*
+ * If the COUNT and COMPARE registers are no longer in sync
+ * then make up some reasonable value for the 'lost_ticks'.
+ *
+ * This could happen, for e.g., after we resume normal
+ * operations after exiting the debugger.
+ */
+ if (lost_ticks > 2 * cycles_per_tick)
+ lost_ticks = cycles_per_tick;
+
+ while (lost_ticks >= cycles_per_tick) {
+ if (sc->et.et_active)
+ sc->et.et_event_cb(&sc->et, sc->et.et_arg);
+ lost_ticks -= cycles_per_tick;
+ }
+ DPCPU_SET(lost_ticks, lost_ticks);
+ }
+ if (sc->et.et_active)
+ sc->et.et_event_cb(&sc->et, sc->et.et_arg);
+ return (FILTER_HANDLED);
+}
+
+static int
+clock_probe(device_t dev)
+{
+
+ if (device_get_unit(dev) != 0)
+ panic("can't attach more clocks");
+
+ device_set_desc(dev, "Generic MIPS32 ticker");
+ return (BUS_PROBE_NOWILDCARD);
+}
+
+static void
+clock_identify(driver_t * drv, device_t parent)
+{
+
+ BUS_ADD_CHILD(parent, 0, "clock", 0);
+}
+
+static int
+clock_attach(device_t dev)
+{
+ struct clock_softc *sc;
+
+ softc = sc = device_get_softc(dev);
+ cpu_establish_hardintr("compare", clock_intr, NULL,
+ sc, IRQ_TIMER, INTR_TYPE_CLK, &sc->intr_handler);
+
+ sc->tc.tc_get_timecount = counter_get_timecount;
+ sc->tc.tc_counter_mask = 0xffffffff;
+ sc->tc.tc_frequency = counter_freq;
+ sc->tc.tc_name = "MIPS32";
+ sc->tc.tc_quality = 800;
+ sc->tc.tc_priv = sc;
+ tc_init(&sc->tc);
+ sc->et.et_name = "MIPS32";
+#if 0
+ sc->et.et_flags = ET_FLAGS_PERIODIC | ET_FLAGS_ONESHOT |
+ ET_FLAGS_PERCPU;
+#endif
+ sc->et.et_flags = ET_FLAGS_PERIODIC | ET_FLAGS_PERCPU;
+ sc->et.et_quality = 800;
+ sc->et.et_frequency = counter_freq;
+ sc->et.et_min_period = 0x00004000LLU; /* To be safe. */
+ sc->et.et_max_period = (0xfffffffeLLU << 32) / sc->et.et_frequency;
+ sc->et.et_start = clock_start;
+ sc->et.et_stop = clock_stop;
+ sc->et.et_priv = sc;
+ et_register(&sc->et);
+ return (0);
+}
+
+static device_method_t clock_methods[] = {
+ /* Device interface */
+ DEVMETHOD(device_probe, clock_probe),
+ DEVMETHOD(device_identify, clock_identify),
+ DEVMETHOD(device_attach, clock_attach),
+ DEVMETHOD(device_detach, bus_generic_detach),
+ DEVMETHOD(device_shutdown, bus_generic_shutdown),
+
+ {0, 0}
+};
+
+static driver_t clock_driver = {
+ "clock",
+ clock_methods,
+ sizeof(struct clock_softc),
+};
+
+static devclass_t clock_devclass;
+
+DRIVER_MODULE(clock, nexus, clock_driver, clock_devclass, 0, 0);
Property changes on: trunk/sys/mips/nlm/tick.c
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Added: trunk/sys/mips/nlm/uart_cpu_xlp.c
===================================================================
--- trunk/sys/mips/nlm/uart_cpu_xlp.c (rev 0)
+++ trunk/sys/mips/nlm/uart_cpu_xlp.c 2018-05-26 21:55:02 UTC (rev 9987)
@@ -0,0 +1,96 @@
+/* $MidnightBSD$ */
+/*-
+ * Copyright 2003-2011 Netlogic Microsystems (Netlogic). All rights
+ * reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in
+ * the documentation and/or other materials provided with the
+ * distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY Netlogic Microsystems ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL NETLOGIC OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
+ * THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * NETLOGIC_BSD */
+
+/*
+ * Skeleton of this file was based on respective code for ARM
+ * code written by Olivier Houchard.
+ */
+/*
+ * XLRMIPS: This file is hacked from arm/...
+ */
+#include "opt_platform.h"
+
+#ifndef FDT /* use FDT uart when fdt is enable */
+#include "opt_uart.h"
+
+#include <sys/cdefs.h>
+__FBSDID("$FreeBSD: stable/10/sys/mips/nlm/uart_cpu_xlp.c 233549 2012-03-27 14:48:40Z jchandra $");
+
+#include <sys/param.h>
+#include <sys/systm.h>
+#include <sys/bus.h>
+#include <sys/cons.h>
+#include <sys/kdb.h>
+#include <sys/kernel.h>
+#include <sys/lock.h>
+#include <sys/mutex.h>
+
+#include <machine/bus.h>
+
+#include <dev/uart/uart.h>
+#include <dev/uart/uart_cpu.h>
+
+#include <mips/nlm/hal/haldefs.h>
+#include <mips/nlm/hal/iomap.h>
+#include <mips/nlm/hal/mips-extns.h>
+#include <mips/nlm/hal/uart.h>
+
+#include <mips/nlm/board.h>
+
+bus_space_tag_t uart_bus_space_io;
+bus_space_tag_t uart_bus_space_mem;
+
+int
+uart_cpu_eqres(struct uart_bas *b1, struct uart_bas *b2)
+{
+ return (b1->bsh == b2->bsh && b1->bst == b2->bst);
+}
+
+int
+uart_cpu_getdev(int devtype, struct uart_devinfo *di)
+{
+ di->ops = uart_getops(&uart_ns8250_class);
+ di->bas.chan = 0;
+ di->bas.bst = rmi_uart_bus_space;
+ di->bas.bsh = nlm_get_uart_regbase(0, BOARD_CONSOLE_UART);
+
+ di->bas.regshft = 2;
+ /* divisor = rclk / (baudrate * 16); */
+ di->bas.rclk = XLP_IO_CLK;
+ di->baudrate = BOARD_CONSOLE_SPEED;
+ di->databits = 8;
+ di->stopbits = 1;
+ di->parity = UART_PARITY_NONE;
+
+ uart_bus_space_io = NULL;
+ uart_bus_space_mem = rmi_uart_bus_space;
+ return (0);
+}
+#endif
Property changes on: trunk/sys/mips/nlm/uart_cpu_xlp.c
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Added: trunk/sys/mips/nlm/usb_init.c
===================================================================
--- trunk/sys/mips/nlm/usb_init.c (rev 0)
+++ trunk/sys/mips/nlm/usb_init.c 2018-05-26 21:55:02 UTC (rev 9987)
@@ -0,0 +1,92 @@
+/* $MidnightBSD$ */
+/*-
+ * Copyright 2003-2011 Netlogic Microsystems (Netlogic). All rights
+ * reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in
+ * the documentation and/or other materials provided with the
+ * distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY Netlogic Microsystems ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL NETLOGIC OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
+ * THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * NETLOGIC_BSD */
+
+#include <sys/cdefs.h>
+__FBSDID("$FreeBSD: stable/10/sys/mips/nlm/usb_init.c 227725 2011-11-19 14:33:14Z jchandra $");
+#include <sys/types.h>
+#include <sys/systm.h>
+#include <sys/param.h>
+#include <sys/kernel.h>
+
+#include <mips/nlm/hal/haldefs.h>
+#include <mips/nlm/hal/iomap.h>
+#include <mips/nlm/hal/usb.h>
+
+#include <mips/nlm/xlp.h>
+
+
+static void
+nlm_usb_intr_en(int node, int port)
+{
+ uint32_t val;
+ uint64_t port_addr;
+
+ port_addr = nlm_get_usb_regbase(node, port);
+ val = nlm_read_usb_reg(port_addr, USB_INT_EN);
+ val = USB_CTRL_INTERRUPT_EN | USB_OHCI_INTERRUPT_EN |
+ USB_OHCI_INTERRUPT1_EN | USB_CTRL_INTERRUPT_EN |
+ USB_OHCI_INTERRUPT_EN | USB_OHCI_INTERRUPT2_EN;
+ nlm_write_usb_reg(port_addr, USB_INT_EN, val);
+}
+
+static void
+nlm_usb_hw_reset(int node, int port)
+{
+ uint64_t port_addr;
+ uint32_t val;
+
+ /* reset USB phy */
+ port_addr = nlm_get_usb_regbase(node, port);
+ val = nlm_read_usb_reg(port_addr, USB_PHY_0);
+ val &= ~(USB_PHY_RESET | USB_PHY_PORT_RESET_0 | USB_PHY_PORT_RESET_1);
+ nlm_write_usb_reg(port_addr, USB_PHY_0, val);
+
+ DELAY(100);
+ val = nlm_read_usb_reg(port_addr, USB_CTL_0);
+ val &= ~(USB_CONTROLLER_RESET);
+ val |= 0x4;
+ nlm_write_usb_reg(port_addr, USB_CTL_0, val);
+}
+
+static void
+nlm_usb_init(void)
+{
+ /* XXX: should be checking if these are in Device mode here */
+ printf("Initialize USB Interface\n");
+ nlm_usb_hw_reset(0, 0);
+ nlm_usb_hw_reset(0, 3);
+
+ /* Enable PHY interrupts */
+ nlm_usb_intr_en(0, 0);
+ nlm_usb_intr_en(0, 3);
+}
+
+SYSINIT(nlm_usb_init, SI_SUB_CPU, SI_ORDER_MIDDLE,
+ nlm_usb_init, NULL);
Property changes on: trunk/sys/mips/nlm/usb_init.c
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Added: trunk/sys/mips/nlm/xlp.h
===================================================================
--- trunk/sys/mips/nlm/xlp.h (rev 0)
+++ trunk/sys/mips/nlm/xlp.h 2018-05-26 21:55:02 UTC (rev 9987)
@@ -0,0 +1,144 @@
+/* $MidnightBSD$ */
+/*-
+ * Copyright 2003-2011 Netlogic Microsystems (Netlogic). All rights
+ * reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in
+ * the documentation and/or other materials provided with the
+ * distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY Netlogic Microsystems ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL NETLOGIC OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
+ * THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * NETLOGIC_BSD
+ * $FreeBSD: stable/10/sys/mips/nlm/xlp.h 238290 2012-07-09 10:24:45Z jchandra $
+ */
+
+#ifndef __NLM_XLP_H__
+#define __NLM_XLP_H__
+#include <mips/nlm/hal/mips-extns.h>
+#include <mips/nlm/hal/iomap.h>
+
+#define PIC_UART_0_IRQ 9
+
+#define PIC_PCIE_0_IRQ 11
+#define PIC_PCIE_1_IRQ 12
+#define PIC_PCIE_2_IRQ 13
+#define PIC_PCIE_3_IRQ 14
+
+#define PIC_EHCI_0_IRQ 16
+#define PIC_MMC_IRQ 21
+/* 41 used by IRQ_SMP */
+
+
+/* XLP 8xx/4xx A0, A1, A2 CPU COP0 PRIDs */
+#define CHIP_PROCESSOR_ID_XLP_8XX 0x10
+#define CHIP_PROCESSOR_ID_XLP_3XX 0x11
+#define CHIP_PROCESSOR_ID_XLP_416 0x94
+#define CHIP_PROCESSOR_ID_XLP_432 0x14
+
+/* Revision id's */
+#define XLP_REVISION_A0 0x00
+#define XLP_REVISION_A1 0x01
+#define XLP_REVISION_A2 0x02
+#define XLP_REVISION_B0 0x03
+#define XLP_REVISION_B1 0x04
+
+#ifndef LOCORE
+/*
+ * FreeBSD can be started with few threads and cores turned off,
+ * so have a hardware thread id to FreeBSD cpuid mapping.
+ */
+extern int xlp_ncores;
+extern int xlp_threads_per_core;
+extern uint32_t xlp_hw_thread_mask;
+extern int xlp_cpuid_to_hwtid[];
+extern int xlp_hwtid_to_cpuid[];
+#ifdef SMP
+extern void xlp_enable_threads(int code);
+#endif
+uint32_t xlp_get_cpu_frequency(int node, int core);
+int nlm_set_device_frequency(int node, int devtype, int frequency);
+int xlp_irt_to_irq(int irt);
+int xlp_irq_to_irt(int irq);
+
+static __inline int nlm_processor_id(void)
+{
+ return ((mips_rd_prid() >> 8) & 0xff);
+}
+
+static __inline int nlm_is_xlp3xx(void)
+{
+
+ return (nlm_processor_id() == CHIP_PROCESSOR_ID_XLP_3XX);
+}
+
+static __inline int nlm_is_xlp3xx_ax(void)
+{
+ uint32_t procid = mips_rd_prid();
+ int prid = (procid >> 8) & 0xff;
+ int rev = procid & 0xff;
+
+ return (prid == CHIP_PROCESSOR_ID_XLP_3XX &&
+ rev < XLP_REVISION_B0);
+}
+
+static __inline int nlm_is_xlp4xx(void)
+{
+ int prid = nlm_processor_id();
+
+ return (prid == CHIP_PROCESSOR_ID_XLP_432 ||
+ prid == CHIP_PROCESSOR_ID_XLP_416);
+}
+
+static __inline int nlm_is_xlp8xx(void)
+{
+ int prid = nlm_processor_id();
+
+ return (prid == CHIP_PROCESSOR_ID_XLP_8XX ||
+ prid == CHIP_PROCESSOR_ID_XLP_432 ||
+ prid == CHIP_PROCESSOR_ID_XLP_416);
+}
+
+static __inline int nlm_is_xlp8xx_ax(void)
+{
+ uint32_t procid = mips_rd_prid();
+ int prid = (procid >> 8) & 0xff;
+ int rev = procid & 0xff;
+
+ return ((prid == CHIP_PROCESSOR_ID_XLP_8XX ||
+ prid == CHIP_PROCESSOR_ID_XLP_432 ||
+ prid == CHIP_PROCESSOR_ID_XLP_416) &&
+ (rev < XLP_REVISION_B0));
+}
+
+static __inline int nlm_is_xlp8xx_b0(void)
+{
+ uint32_t procid = mips_rd_prid();
+ int prid = (procid >> 8) & 0xff;
+ int rev = procid & 0xff;
+
+ return ((prid == CHIP_PROCESSOR_ID_XLP_8XX ||
+ prid == CHIP_PROCESSOR_ID_XLP_432 ||
+ prid == CHIP_PROCESSOR_ID_XLP_416) &&
+ rev == XLP_REVISION_B0);
+}
+
+#endif /* LOCORE */
+#endif /* __NLM_XLP_H__ */
Property changes on: trunk/sys/mips/nlm/xlp.h
___________________________________________________________________
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+native
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+MidnightBSD=%H
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Added: trunk/sys/mips/nlm/xlp_machdep.c
===================================================================
--- trunk/sys/mips/nlm/xlp_machdep.c (rev 0)
+++ trunk/sys/mips/nlm/xlp_machdep.c 2018-05-26 21:55:02 UTC (rev 9987)
@@ -0,0 +1,738 @@
+/* $MidnightBSD$ */
+/*-
+ * Copyright 2003-2011 Netlogic Microsystems (Netlogic). All rights
+ * reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in
+ * the documentation and/or other materials provided with the
+ * distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY Netlogic Microsystems ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL NETLOGIC OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
+ * THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * NETLOGIC_BSD */
+
+#include <sys/cdefs.h>
+__FBSDID("$FreeBSD: stable/10/sys/mips/nlm/xlp_machdep.c 261455 2014-02-04 03:36:42Z eadler $");
+
+#include "opt_ddb.h"
+#include "opt_platform.h"
+
+#include <sys/param.h>
+#include <sys/bus.h>
+#include <sys/conf.h>
+#include <sys/rtprio.h>
+#include <sys/systm.h>
+#include <sys/interrupt.h>
+#include <sys/limits.h>
+#include <sys/lock.h>
+#include <sys/malloc.h>
+#include <sys/mutex.h>
+#include <sys/random.h>
+
+#include <sys/cons.h> /* cinit() */
+#include <sys/kdb.h>
+#include <sys/reboot.h>
+#include <sys/queue.h>
+#include <sys/smp.h>
+#include <sys/timetc.h>
+
+#include <vm/vm.h>
+#include <vm/vm_page.h>
+
+#include <machine/cpu.h>
+#include <machine/cpufunc.h>
+#include <machine/cpuinfo.h>
+#include <machine/tlb.h>
+#include <machine/cpuregs.h>
+#include <machine/frame.h>
+#include <machine/hwfunc.h>
+#include <machine/md_var.h>
+#include <machine/asm.h>
+#include <machine/pmap.h>
+#include <machine/trap.h>
+#include <machine/clock.h>
+#include <machine/fls64.h>
+#include <machine/intr_machdep.h>
+#include <machine/smp.h>
+
+#include <mips/nlm/hal/mips-extns.h>
+#include <mips/nlm/hal/haldefs.h>
+#include <mips/nlm/hal/iomap.h>
+#include <mips/nlm/hal/sys.h>
+#include <mips/nlm/hal/pic.h>
+#include <mips/nlm/hal/uart.h>
+#include <mips/nlm/hal/mmu.h>
+#include <mips/nlm/hal/bridge.h>
+#include <mips/nlm/hal/cpucontrol.h>
+#include <mips/nlm/hal/cop2.h>
+
+#include <mips/nlm/clock.h>
+#include <mips/nlm/interrupt.h>
+#include <mips/nlm/board.h>
+#include <mips/nlm/xlp.h>
+#include <mips/nlm/msgring.h>
+
+#ifdef FDT
+#include <dev/fdt/fdt_common.h>
+#include <dev/ofw/openfirm.h>
+#endif
+
+/* 4KB static data aread to keep a copy of the bootload env until
+ the dynamic kenv is setup */
+char boot1_env[4096];
+
+uint64_t xlp_cpu_frequency;
+uint64_t xlp_io_base = MIPS_PHYS_TO_DIRECT_UNCACHED(XLP_DEFAULT_IO_BASE);
+
+int xlp_ncores;
+int xlp_threads_per_core;
+uint32_t xlp_hw_thread_mask;
+int xlp_cpuid_to_hwtid[MAXCPU];
+int xlp_hwtid_to_cpuid[MAXCPU];
+uint64_t xlp_pic_base;
+
+static int xlp_mmuval;
+
+extern uint32_t _end;
+extern char XLPResetEntry[], XLPResetEntryEnd[];
+
+static void
+xlp_setup_core(void)
+{
+ uint64_t reg;
+
+ reg = nlm_mfcr(LSU_DEFEATURE);
+ /* Enable Unaligned and L2HPE */
+ reg |= (1 << 30) | (1 << 23);
+ /*
+ * Experimental : Enable SUE
+ * Speculative Unmap Enable. Enable speculative L2 cache request for
+ * unmapped access.
+ */
+ reg |= (1ull << 31);
+ /* Clear S1RCM - A0 errata */
+ reg &= ~0xeull;
+ nlm_mtcr(LSU_DEFEATURE, reg);
+
+ reg = nlm_mfcr(SCHED_DEFEATURE);
+ /* Experimental: Disable BRU accepting ALU ops - A0 errata */
+ reg |= (1 << 24);
+ nlm_mtcr(SCHED_DEFEATURE, reg);
+}
+
+static void
+xlp_setup_mmu(void)
+{
+ uint32_t pagegrain;
+
+ if (nlm_threadid() == 0) {
+ nlm_setup_extended_pagemask(0);
+ nlm_large_variable_tlb_en(1);
+ nlm_extended_tlb_en(1);
+ nlm_mmu_setup(0, 0, 0);
+ }
+
+ /* Enable no-read, no-exec, large-physical-address */
+ pagegrain = mips_rd_pagegrain();
+ pagegrain |= (1U << 31) | /* RIE */
+ (1 << 30) | /* XIE */
+ (1 << 29); /* ELPA */
+ mips_wr_pagegrain(pagegrain);
+}
+
+static void
+xlp_enable_blocks(void)
+{
+ uint64_t sysbase;
+ int i;
+
+ for (i = 0; i < XLP_MAX_NODES; i++) {
+ if (!nlm_dev_exists(XLP_IO_SYS_OFFSET(i)))
+ continue;
+ sysbase = nlm_get_sys_regbase(i);
+ nlm_sys_enable_block(sysbase, DFS_DEVICE_RSA);
+ }
+}
+
+static void
+xlp_parse_mmu_options(void)
+{
+ uint64_t sysbase;
+ uint32_t cpu_map = xlp_hw_thread_mask;
+ uint32_t core0_thr_mask, core_thr_mask, cpu_rst_mask;
+ int i, j, k;
+
+#ifdef SMP
+ if (cpu_map == 0)
+ cpu_map = 0xffffffff;
+#else /* Uniprocessor! */
+ if (cpu_map == 0)
+ cpu_map = 0x1;
+ else if (cpu_map != 0x1) {
+ printf("WARNING: Starting uniprocessor kernel on cpumask [0x%lx]!\n"
+ "WARNING: Other CPUs will be unused.\n", (u_long)cpu_map);
+ cpu_map = 0x1;
+ }
+#endif
+
+ xlp_ncores = 1;
+ core0_thr_mask = cpu_map & 0xf;
+ switch (core0_thr_mask) {
+ case 1:
+ xlp_threads_per_core = 1;
+ xlp_mmuval = 0;
+ break;
+ case 3:
+ xlp_threads_per_core = 2;
+ xlp_mmuval = 2;
+ break;
+ case 0xf:
+ xlp_threads_per_core = 4;
+ xlp_mmuval = 3;
+ break;
+ default:
+ goto unsupp;
+ }
+
+ /* Try to find the enabled cores from SYS block */
+ sysbase = nlm_get_sys_regbase(0);
+ cpu_rst_mask = nlm_read_sys_reg(sysbase, SYS_CPU_RESET) & 0xff;
+
+ /* XLP 416 does not report this correctly, fix */
+ if (nlm_processor_id() == CHIP_PROCESSOR_ID_XLP_416)
+ cpu_rst_mask = 0xe;
+
+ /* Take out cores which do not exist on chip */
+ for (i = 1; i < XLP_MAX_CORES; i++) {
+ if ((cpu_rst_mask & (1 << i)) == 0)
+ cpu_map &= ~(0xfu << (4 * i));
+ }
+
+ /* Verify other cores' CPU masks */
+ for (i = 1; i < XLP_MAX_CORES; i++) {
+ core_thr_mask = (cpu_map >> (4 * i)) & 0xf;
+ if (core_thr_mask == 0)
+ continue;
+ if (core_thr_mask != core0_thr_mask)
+ goto unsupp;
+ xlp_ncores++;
+ }
+
+ xlp_hw_thread_mask = cpu_map;
+ /* setup hardware processor id to cpu id mapping */
+ for (i = 0; i< MAXCPU; i++)
+ xlp_cpuid_to_hwtid[i] =
+ xlp_hwtid_to_cpuid[i] = -1;
+ for (i = 0, k = 0; i < XLP_MAX_CORES; i++) {
+ if (((cpu_map >> (i * 4)) & 0xf) == 0)
+ continue;
+ for (j = 0; j < xlp_threads_per_core; j++) {
+ xlp_cpuid_to_hwtid[k] = i * 4 + j;
+ xlp_hwtid_to_cpuid[i * 4 + j] = k;
+ k++;
+ }
+ }
+
+ return;
+
+unsupp:
+ printf("ERROR : Unsupported CPU mask [use 1,2 or 4 threads per core].\n"
+ "\tcore0 thread mask [%lx], boot cpu mask [%lx].\n",
+ (u_long)core0_thr_mask, (u_long)cpu_map);
+ panic("Invalid CPU mask - halting.\n");
+ return;
+}
+
+/* Parse cmd line args as env - copied from ar71xx */
+static void
+xlp_parse_bootargs(char *cmdline)
+{
+ char *n, *v;
+
+ while ((v = strsep(&cmdline, " \n")) != NULL) {
+ if (*v == '\0')
+ continue;
+ if (*v == '-') {
+ while (*v != '\0') {
+ v++;
+ switch (*v) {
+ case 'a': boothowto |= RB_ASKNAME; break;
+ case 'd': boothowto |= RB_KDB; break;
+ case 'g': boothowto |= RB_GDB; break;
+ case 's': boothowto |= RB_SINGLE; break;
+ case 'v': boothowto |= RB_VERBOSE; break;
+ }
+ }
+ } else {
+ n = strsep(&v, "=");
+ if (v == NULL)
+ setenv(n, "1");
+ else
+ setenv(n, v);
+ }
+ }
+}
+
+#ifdef FDT
+static void
+xlp_bootargs_init(__register_t arg)
+{
+ char buf[2048]; /* early stack is big enough */
+ void *dtbp;
+ phandle_t chosen;
+ ihandle_t mask;
+
+ dtbp = (void *)(intptr_t)arg;
+#if defined(FDT_DTB_STATIC)
+ /*
+ * In case the device tree blob was not passed as argument try
+ * to use the statically embedded one.
+ */
+ if (dtbp == NULL)
+ dtbp = &fdt_static_dtb;
+#endif
+ if (OF_install(OFW_FDT, 0) == FALSE)
+ while (1);
+ if (OF_init((void *)dtbp) != 0)
+ while (1);
+ if (fdt_immr_addr(xlp_io_base) != 0)
+ while (1);
+ OF_interpret("perform-fixup", 0);
+
+ chosen = OF_finddevice("/chosen");
+ if (OF_getprop(chosen, "cpumask", &mask, sizeof(mask)) != -1) {
+ xlp_hw_thread_mask = mask;
+ }
+
+ if (OF_getprop(chosen, "bootargs", buf, sizeof(buf)) != -1)
+ xlp_parse_bootargs(buf);
+}
+#else
+/*
+ * arg is a pointer to the environment block, the format of the block is
+ * a=xyz\0b=pqr\0\0
+ */
+static void
+xlp_bootargs_init(__register_t arg)
+{
+ char buf[2048]; /* early stack is big enough */
+ char *p, *v, *n;
+ uint32_t mask;
+
+ /*
+ * provide backward compat for passing cpu mask as arg
+ */
+ if (arg & 1) {
+ xlp_hw_thread_mask = arg;
+ return;
+ }
+
+ p = (void *)(intptr_t)arg;
+ while (*p != '\0') {
+ strlcpy(buf, p, sizeof(buf));
+ v = buf;
+ n = strsep(&v, "=");
+ if (v == NULL)
+ setenv(n, "1");
+ else
+ setenv(n, v);
+ p += strlen(p) + 1;
+ }
+
+ /* CPU mask can be passed thru env */
+ if (getenv_uint("cpumask", &mask) != 0)
+ xlp_hw_thread_mask = mask;
+
+ /* command line argument */
+ v = getenv("bootargs");
+ if (v != NULL) {
+ strlcpy(buf, v, sizeof(buf));
+ xlp_parse_bootargs(buf);
+ freeenv(v);
+ }
+}
+#endif
+
+static void
+mips_init(void)
+{
+ init_param1();
+ init_param2(physmem);
+
+ mips_cpu_init();
+ cpuinfo.cache_coherent_dma = TRUE;
+ pmap_bootstrap();
+ mips_proc0_init();
+ mutex_init();
+#ifdef DDB
+ kdb_init();
+ if (boothowto & RB_KDB) {
+ kdb_enter("Boot flags requested debugger", NULL);
+ }
+#endif
+}
+
+unsigned int
+platform_get_timecount(struct timecounter *tc __unused)
+{
+ uint64_t count = nlm_pic_read_timer(xlp_pic_base, PIC_CLOCK_TIMER);
+
+ return (unsigned int)~count;
+}
+
+static void
+xlp_pic_init(void)
+{
+ struct timecounter pic_timecounter = {
+ platform_get_timecount, /* get_timecount */
+ 0, /* no poll_pps */
+ ~0U, /* counter_mask */
+ XLP_IO_CLK, /* frequency */
+ "XLRPIC", /* name */
+ 2000, /* quality (adjusted in code) */
+ };
+ int i;
+ int maxirt;
+
+ xlp_pic_base = nlm_get_pic_regbase(0); /* TOOD: Add other nodes */
+ maxirt = nlm_read_reg(nlm_get_pic_pcibase(nlm_nodeid()),
+ XLP_PCI_DEVINFO_REG0);
+ printf("Initializing PIC...@%jx %d IRTs\n", (uintmax_t)xlp_pic_base,
+ maxirt);
+ /* Bind all PIC irqs to cpu 0 */
+ for (i = 0; i < maxirt; i++)
+ nlm_pic_write_irt(xlp_pic_base, i, 0, 0, 1, 0,
+ 1, 0, 0x1);
+
+ nlm_pic_set_timer(xlp_pic_base, PIC_CLOCK_TIMER, ~0ULL, 0, 0);
+ platform_timecounter = &pic_timecounter;
+}
+
+#if defined(__mips_n32) || defined(__mips_n64) /* PHYSADDR_64_BIT */
+#ifdef XLP_SIM
+#define XLP_MEM_LIM 0x200000000ULL
+#else
+#define XLP_MEM_LIM 0x10000000000ULL
+#endif
+#else
+#define XLP_MEM_LIM 0xfffff000UL
+#endif
+static vm_paddr_t xlp_mem_excl[] = {
+ 0, 0, /* for kernel image region, see xlp_mem_init */
+ 0x0c000000, 0x14000000, /* uboot area, cms queue and other stuff */
+ 0x1fc00000, 0x1fd00000, /* reset vec */
+ 0x1e000000, 0x1e200000, /* poe buffers */
+};
+
+static int
+mem_exclude_add(vm_paddr_t *avail, vm_paddr_t mstart, vm_paddr_t mend)
+{
+ int nreg = sizeof(xlp_mem_excl)/sizeof(xlp_mem_excl[0]);
+ int i, pos;
+
+ pos = 0;
+ for (i = 0; i < nreg; i += 2) {
+ if (mstart > xlp_mem_excl[i + 1])
+ continue;
+ if (mstart < xlp_mem_excl[i]) {
+ avail[pos++] = mstart;
+ if (mend < xlp_mem_excl[i])
+ avail[pos++] = mend;
+ else
+ avail[pos++] = xlp_mem_excl[i];
+ }
+ mstart = xlp_mem_excl[i + 1];
+ if (mend <= mstart)
+ break;
+ }
+ if (mstart < mend) {
+ avail[pos++] = mstart;
+ avail[pos++] = mend;
+ }
+ return (pos);
+}
+
+static void
+xlp_mem_init(void)
+{
+ vm_paddr_t physsz, tmp;
+ uint64_t bridgebase, base, lim, val;
+ int i, j, k, n;
+
+ /* update kernel image area in exclude regions */
+ tmp = (vm_paddr_t)MIPS_KSEG0_TO_PHYS(&_end);
+ tmp = round_page(tmp) + 0x20000; /* round up */
+ xlp_mem_excl[1] = tmp;
+
+ printf("Memory (from DRAM BARs):\n");
+ bridgebase = nlm_get_bridge_regbase(0); /* TODO: Add other nodes */
+ physsz = 0;
+ for (i = 0, j = 0; i < 8; i++) {
+ val = nlm_read_bridge_reg(bridgebase, BRIDGE_DRAM_BAR(i));
+ val = (val >> 12) & 0xfffff;
+ base = val << 20;
+ val = nlm_read_bridge_reg(bridgebase, BRIDGE_DRAM_LIMIT(i));
+ val = (val >> 12) & 0xfffff;
+ if (val == 0) /* BAR not enabled */
+ continue;
+ lim = (val + 1) << 20;
+ printf(" BAR %d: %#jx - %#jx : ", i, (intmax_t)base,
+ (intmax_t)lim);
+
+ if (lim <= base) {
+ printf("\tskipped - malformed %#jx -> %#jx\n",
+ (intmax_t)base, (intmax_t)lim);
+ continue;
+ } else if (base >= XLP_MEM_LIM) {
+ printf(" skipped - outside usable limit %#jx.\n",
+ (intmax_t)XLP_MEM_LIM);
+ continue;
+ } else if (lim >= XLP_MEM_LIM) {
+ lim = XLP_MEM_LIM;
+ printf(" truncated to %#jx.\n", (intmax_t)XLP_MEM_LIM);
+ } else
+ printf(" usable\n");
+
+ /* exclude unusable regions from BAR and add rest */
+ n = mem_exclude_add(&phys_avail[j], base, lim);
+ for (k = j; k < j + n; k += 2) {
+ physsz += phys_avail[k + 1] - phys_avail[k];
+ printf("\tMem[%d]: %#jx - %#jx\n", k/2,
+ (intmax_t)phys_avail[k], (intmax_t)phys_avail[k+1]);
+ }
+ j = k;
+ }
+
+ /* setup final entry with 0 */
+ phys_avail[j] = phys_avail[j + 1] = 0;
+
+ /* copy phys_avail to dump_avail */
+ for (i = 0; i <= j + 1; i++)
+ dump_avail[i] = phys_avail[i];
+
+ realmem = physmem = btoc(physsz);
+}
+
+void
+platform_start(__register_t a0 __unused,
+ __register_t a1 __unused,
+ __register_t a2 __unused,
+ __register_t a3 __unused)
+{
+
+ /* Initialize pcpu stuff */
+ mips_pcpu0_init();
+
+ /* initialize console so that we have printf */
+ boothowto |= (RB_SERIAL | RB_MULTIPLE); /* Use multiple consoles */
+
+ init_static_kenv(boot1_env, sizeof(boot1_env));
+ xlp_bootargs_init(a0);
+
+ /* clockrate used by delay, so initialize it here */
+ xlp_cpu_frequency = xlp_get_cpu_frequency(0, 0);
+ cpu_clock = xlp_cpu_frequency / 1000000;
+ mips_timer_early_init(xlp_cpu_frequency);
+
+ /* Init console please */
+ cninit();
+
+ /* Early core init and fixes for errata */
+ xlp_setup_core();
+
+ xlp_parse_mmu_options();
+ xlp_mem_init();
+
+ bcopy(XLPResetEntry, (void *)MIPS_RESET_EXC_VEC,
+ XLPResetEntryEnd - XLPResetEntry);
+#ifdef SMP
+ /*
+ * We will enable the other threads in core 0 here
+ * so that the TLB and cache info is correct when
+ * mips_init runs
+ */
+ xlp_enable_threads(xlp_mmuval);
+#endif
+ /* setup for the startup core */
+ xlp_setup_mmu();
+
+ xlp_enable_blocks();
+
+ /* Read/Guess/setup board information */
+ nlm_board_info_setup();
+
+ /* MIPS generic init */
+ mips_init();
+
+ /*
+ * XLP specific post initialization
+ * initialize other on chip stuff
+ */
+ xlp_pic_init();
+
+ mips_timer_init_params(xlp_cpu_frequency, 0);
+}
+
+void
+platform_cpu_init()
+{
+}
+
+void
+platform_reset(void)
+{
+ uint64_t sysbase = nlm_get_sys_regbase(0);
+
+ nlm_write_sys_reg(sysbase, SYS_CHIP_RESET, 1);
+ for( ; ; )
+ __asm __volatile("wait");
+}
+
+#ifdef SMP
+/*
+ * XLP threads are started simultaneously when we enable threads, this will
+ * ensure that the threads are blocked in platform_init_ap, until they are
+ * ready to proceed to smp_init_secondary()
+ */
+static volatile int thr_unblock[4];
+
+int
+platform_start_ap(int cpuid)
+{
+ uint32_t coremask, val;
+ uint64_t sysbase = nlm_get_sys_regbase(0);
+ int hwtid = xlp_cpuid_to_hwtid[cpuid];
+ int core, thr;
+
+ core = hwtid / 4;
+ thr = hwtid % 4;
+ if (thr == 0) {
+ /* First thread in core, do core wake up */
+ coremask = 1u << core;
+
+ /* Enable core clock */
+ val = nlm_read_sys_reg(sysbase, SYS_CORE_DFS_DIS_CTRL);
+ val &= ~coremask;
+ nlm_write_sys_reg(sysbase, SYS_CORE_DFS_DIS_CTRL, val);
+
+ /* Remove CPU Reset */
+ val = nlm_read_sys_reg(sysbase, SYS_CPU_RESET);
+ val &= ~coremask & 0xff;
+ nlm_write_sys_reg(sysbase, SYS_CPU_RESET, val);
+
+ if (bootverbose)
+ printf("Waking up core %d ...", core);
+
+ /* Poll for CPU to mark itself coherent */
+ do {
+ val = nlm_read_sys_reg(sysbase, SYS_CPU_NONCOHERENT_MODE);
+ } while ((val & coremask) != 0);
+ if (bootverbose)
+ printf("Done\n");
+ } else {
+ /* otherwise release the threads stuck in platform_init_ap */
+ thr_unblock[thr] = 1;
+ }
+
+ return (0);
+}
+
+void
+platform_init_ap(int cpuid)
+{
+ uint32_t stat;
+ int thr;
+
+ /* The first thread has to setup the MMU and enable other threads */
+ thr = nlm_threadid();
+ if (thr == 0) {
+ xlp_setup_core();
+ xlp_enable_threads(xlp_mmuval);
+ } else {
+ /*
+ * FIXME busy wait here eats too many cycles, especially
+ * in the core 0 while bootup
+ */
+ while (thr_unblock[thr] == 0)
+ __asm__ __volatile__ ("nop;nop;nop;nop");
+ thr_unblock[thr] = 0;
+ }
+
+ xlp_setup_mmu();
+ stat = mips_rd_status();
+ KASSERT((stat & MIPS_SR_INT_IE) == 0,
+ ("Interrupts enabled in %s!", __func__));
+ stat |= MIPS_SR_COP_2_BIT | MIPS_SR_COP_0_BIT;
+ mips_wr_status(stat);
+
+ nlm_write_c0_eimr(0ull);
+ xlp_enable_irq(IRQ_IPI);
+ xlp_enable_irq(IRQ_TIMER);
+ xlp_enable_irq(IRQ_MSGRING);
+
+ return;
+}
+
+int
+platform_ipi_intrnum(void)
+{
+
+ return (IRQ_IPI);
+}
+
+void
+platform_ipi_send(int cpuid)
+{
+
+ nlm_pic_send_ipi(xlp_pic_base, xlp_cpuid_to_hwtid[cpuid],
+ platform_ipi_intrnum(), 0);
+}
+
+void
+platform_ipi_clear(void)
+{
+}
+
+int
+platform_processor_id(void)
+{
+
+ return (xlp_hwtid_to_cpuid[nlm_cpuid()]);
+}
+
+void
+platform_cpu_mask(cpuset_t *mask)
+{
+ int i, s;
+
+ CPU_ZERO(mask);
+ s = xlp_ncores * xlp_threads_per_core;
+ for (i = 0; i < s; i++)
+ CPU_SET(i, mask);
+}
+
+struct cpu_group *
+platform_smp_topo()
+{
+
+ return (smp_topo_2level(CG_SHARE_L2, xlp_ncores, CG_SHARE_L1,
+ xlp_threads_per_core, CG_FLAG_THREAD));
+}
+#endif
Property changes on: trunk/sys/mips/nlm/xlp_machdep.c
___________________________________________________________________
Added: svn:eol-style
## -0,0 +1 ##
+native
\ No newline at end of property
Added: svn:keywords
## -0,0 +1 ##
+MidnightBSD=%H
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+text/plain
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Added: trunk/sys/mips/nlm/xlp_pci.c
===================================================================
--- trunk/sys/mips/nlm/xlp_pci.c (rev 0)
+++ trunk/sys/mips/nlm/xlp_pci.c 2018-05-26 21:55:02 UTC (rev 9987)
@@ -0,0 +1,899 @@
+/* $MidnightBSD$ */
+/*-
+ * Copyright (c) 2003-2012 Broadcom Corporation
+ * All Rights Reserved
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in
+ * the documentation and/or other materials provided with the
+ * distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY BROADCOM ``AS IS'' AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL BROADCOM OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
+ * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
+ * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
+ * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <sys/cdefs.h>
+__FBSDID("$FreeBSD: stable/10/sys/mips/nlm/xlp_pci.c 265999 2014-05-14 01:35:43Z ian $");
+
+#include <sys/param.h>
+#include <sys/systm.h>
+#include <sys/types.h>
+#include <sys/kernel.h>
+#include <sys/module.h>
+#include <sys/malloc.h>
+#include <sys/bus.h>
+#include <sys/endian.h>
+#include <sys/rman.h>
+#include <sys/pciio.h>
+
+#include <vm/vm.h>
+#include <vm/vm_param.h>
+#include <vm/pmap.h>
+
+#include <dev/pci/pcivar.h>
+#include <dev/pci/pcireg.h>
+#include <dev/pci/pci_private.h>
+
+#include <dev/uart/uart.h>
+#include <dev/uart/uart_bus.h>
+#include <dev/uart/uart_cpu.h>
+
+#include <machine/bus.h>
+#include <machine/md_var.h>
+#include <machine/intr_machdep.h>
+#include <machine/cpuregs.h>
+
+#include <mips/nlm/hal/haldefs.h>
+#include <mips/nlm/interrupt.h>
+#include <mips/nlm/hal/iomap.h>
+#include <mips/nlm/hal/mips-extns.h>
+#include <mips/nlm/hal/pic.h>
+#include <mips/nlm/hal/bridge.h>
+#include <mips/nlm/hal/gbu.h>
+#include <mips/nlm/hal/pcibus.h>
+#include <mips/nlm/hal/uart.h>
+#include <mips/nlm/xlp.h>
+
+#include "pcib_if.h"
+#include "pci_if.h"
+
+#define EMUL_MEM_START 0x16000000UL
+#define EMUL_MEM_END 0x18ffffffUL
+
+/* SoC device qurik handling */
+static int irt_irq_map[4 * 256];
+static int irq_irt_map[64];
+
+static void
+xlp_add_irq(int node, int irt, int irq)
+{
+ int nodeirt = node * 256 + irt;
+
+ irt_irq_map[nodeirt] = irq;
+ irq_irt_map[irq] = nodeirt;
+}
+
+int
+xlp_irq_to_irt(int irq)
+{
+ return irq_irt_map[irq];
+}
+
+int
+xlp_irt_to_irq(int nodeirt)
+{
+ return irt_irq_map[nodeirt];
+}
+
+/* Override PCI a bit for SoC devices */
+
+enum {
+ INTERNAL_DEV = 0x1, /* internal device, skip on enumeration */
+ MEM_RES_EMUL = 0x2, /* no MEM or IO bar, custom res alloc */
+ SHARED_IRQ = 0x4,
+ DEV_MMIO32 = 0x8, /* byte access not allowed to mmio */
+};
+
+struct soc_dev_desc {
+ u_int devid; /* device ID */
+ int irqbase; /* start IRQ */
+ u_int flags; /* flags */
+ int ndevs; /* to keep track of number of devices */
+};
+
+struct soc_dev_desc xlp_dev_desc[] = {
+ { PCI_DEVICE_ID_NLM_ICI, 0, INTERNAL_DEV },
+ { PCI_DEVICE_ID_NLM_PIC, 0, INTERNAL_DEV },
+ { PCI_DEVICE_ID_NLM_FMN, 0, INTERNAL_DEV },
+ { PCI_DEVICE_ID_NLM_UART, PIC_UART_0_IRQ, MEM_RES_EMUL | DEV_MMIO32},
+ { PCI_DEVICE_ID_NLM_I2C, 0, MEM_RES_EMUL | DEV_MMIO32 },
+ { PCI_DEVICE_ID_NLM_NOR, 0, MEM_RES_EMUL },
+ { PCI_DEVICE_ID_NLM_MMC, PIC_MMC_IRQ, MEM_RES_EMUL },
+ { PCI_DEVICE_ID_NLM_EHCI, PIC_EHCI_0_IRQ, 0 }
+};
+
+struct xlp_devinfo {
+ struct pci_devinfo pcidev;
+ int irq;
+ int flags;
+ u_long mem_res_start;
+};
+
+static __inline struct soc_dev_desc *
+xlp_find_soc_desc(int devid)
+{
+ struct soc_dev_desc *p;
+ int i, n;
+
+ n = sizeof(xlp_dev_desc) / sizeof(xlp_dev_desc[0]);
+ for (i = 0, p = xlp_dev_desc; i < n; i++, p++)
+ if (p->devid == devid)
+ return (p);
+ return (NULL);
+}
+
+static struct resource *
+xlp_pci_alloc_resource(device_t bus, device_t child, int type, int *rid,
+ u_long start, u_long end, u_long count, u_int flags)
+{
+ struct resource *r;
+ struct xlp_devinfo *xlp_devinfo;
+ int busno;
+
+ /*
+ * Do custom allocation for MEMORY resource for SoC device if
+ * MEM_RES_EMUL flag is set
+ */
+ busno = pci_get_bus(child);
+ if ((type == SYS_RES_MEMORY || type == SYS_RES_IOPORT) && busno == 0) {
+ xlp_devinfo = (struct xlp_devinfo *)device_get_ivars(child);
+ if ((xlp_devinfo->flags & MEM_RES_EMUL) != 0) {
+ /* no emulation for IO ports */
+ if (type == SYS_RES_IOPORT)
+ return (NULL);
+
+ start = xlp_devinfo->mem_res_start;
+ count = XLP_PCIE_CFG_SIZE - XLP_IO_PCI_HDRSZ;
+
+ /* MMC needs to 2 slots with rids 16 and 20 and a
+ * fixup for size */
+ if (pci_get_device(child) == PCI_DEVICE_ID_NLM_MMC) {
+ count = 0x100;
+ if (*rid == 16)
+ ; /* first slot already setup */
+ else if (*rid == 20)
+ start += 0x100; /* second slot */
+ else
+ return (NULL);
+ }
+
+ end = start + count - 1;
+ r = BUS_ALLOC_RESOURCE(device_get_parent(bus), child,
+ type, rid, start, end, count, flags);
+ if (r == NULL)
+ return (NULL);
+ if ((xlp_devinfo->flags & DEV_MMIO32) != 0)
+ rman_set_bustag(r, rmi_uart_bus_space);
+ return (r);
+ }
+ }
+
+ /* Not custom alloc, use PCI code */
+ return (pci_alloc_resource(bus, child, type, rid, start, end, count,
+ flags));
+}
+
+static int
+xlp_pci_release_resource(device_t bus, device_t child, int type, int rid,
+ struct resource *r)
+{
+ u_long start;
+
+ /* If custom alloc, handle that */
+ start = rman_get_start(r);
+ if (type == SYS_RES_MEMORY && pci_get_bus(child) == 0 &&
+ start >= EMUL_MEM_START && start <= EMUL_MEM_END)
+ return (BUS_RELEASE_RESOURCE(device_get_parent(bus), child,
+ type, rid, r));
+
+ /* use default PCI function */
+ return (bus_generic_rl_release_resource(bus, child, type, rid, r));
+}
+
+static void
+xlp_add_soc_child(device_t pcib, device_t dev, int b, int s, int f)
+{
+ struct pci_devinfo *dinfo;
+ struct xlp_devinfo *xlp_dinfo;
+ struct soc_dev_desc *si;
+ uint64_t pcibase;
+ int domain, node, irt, irq, flags, devoffset, num;
+ uint16_t devid;
+
+ domain = pcib_get_domain(dev);
+ node = s / 8;
+ devoffset = XLP_HDR_OFFSET(node, 0, s % 8, f);
+ if (!nlm_dev_exists(devoffset))
+ return;
+
+ /* Find if there is a desc for the SoC device */
+ devid = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_DEVICE, 2);
+ si = xlp_find_soc_desc(devid);
+
+ /* update flags and irq from desc if available */
+ irq = 0;
+ flags = 0;
+ if (si != NULL) {
+ if (si->irqbase != 0)
+ irq = si->irqbase + si->ndevs;
+ flags = si->flags;
+ si->ndevs++;
+ }
+
+ /* skip internal devices */
+ if ((flags & INTERNAL_DEV) != 0)
+ return;
+
+ /* PCIe interfaces are special, bug in Ax */
+ if (devid == PCI_DEVICE_ID_NLM_PCIE) {
+ xlp_add_irq(node, xlp_pcie_link_irt(f), PIC_PCIE_0_IRQ + f);
+ } else {
+ /* Stash intline and pin in shadow reg for devices */
+ pcibase = nlm_pcicfg_base(devoffset);
+ irt = nlm_irtstart(pcibase);
+ num = nlm_irtnum(pcibase);
+ if (irq != 0 && num > 0) {
+ xlp_add_irq(node, irt, irq);
+ nlm_write_reg(pcibase, XLP_PCI_DEVSCRATCH_REG0,
+ (1 << 8) | irq);
+ }
+ }
+ dinfo = pci_read_device(pcib, domain, b, s, f, sizeof(*xlp_dinfo));
+ if (dinfo == NULL)
+ return;
+ xlp_dinfo = (struct xlp_devinfo *)dinfo;
+ xlp_dinfo->irq = irq;
+ xlp_dinfo->flags = flags;
+
+ /* memory resource from ecfg space, if MEM_RES_EMUL is set */
+ if ((flags & MEM_RES_EMUL) != 0)
+ xlp_dinfo->mem_res_start = XLP_DEFAULT_IO_BASE + devoffset +
+ XLP_IO_PCI_HDRSZ;
+ pci_add_child(dev, dinfo);
+}
+
+static int
+xlp_pci_attach(device_t dev)
+{
+ device_t pcib = device_get_parent(dev);
+ int maxslots, s, f, pcifunchigh;
+ int busno;
+ uint8_t hdrtype;
+
+ /*
+ * The on-chip devices are on a bus that is almost, but not
+ * quite, completely like PCI. Add those things by hand.
+ */
+ busno = pcib_get_bus(dev);
+ maxslots = PCIB_MAXSLOTS(pcib);
+ for (s = 0; s <= maxslots; s++) {
+ pcifunchigh = 0;
+ f = 0;
+ hdrtype = PCIB_READ_CONFIG(pcib, busno, s, f, PCIR_HDRTYPE, 1);
+ if ((hdrtype & PCIM_HDRTYPE) > PCI_MAXHDRTYPE)
+ continue;
+ if (hdrtype & PCIM_MFDEV)
+ pcifunchigh = PCI_FUNCMAX;
+ for (f = 0; f <= pcifunchigh; f++)
+ xlp_add_soc_child(pcib, dev, busno, s, f);
+ }
+ return (bus_generic_attach(dev));
+}
+
+static int
+xlp_pci_probe(device_t dev)
+{
+ device_t pcib;
+
+ pcib = device_get_parent(dev);
+ /*
+ * Only the top level bus has SoC devices, leave the rest to
+ * Generic PCI code
+ */
+ if (strcmp(device_get_nameunit(pcib), "pcib0") != 0)
+ return (ENXIO);
+ device_set_desc(dev, "XLP SoCbus");
+ return (BUS_PROBE_DEFAULT);
+}
+
+static devclass_t pci_devclass;
+static device_method_t xlp_pci_methods[] = {
+ /* Device interface */
+ DEVMETHOD(device_probe, xlp_pci_probe),
+ DEVMETHOD(device_attach, xlp_pci_attach),
+ DEVMETHOD(bus_alloc_resource, xlp_pci_alloc_resource),
+ DEVMETHOD(bus_release_resource, xlp_pci_release_resource),
+
+ DEVMETHOD_END
+};
+
+DEFINE_CLASS_1(pci, xlp_pci_driver, xlp_pci_methods, sizeof(struct pci_softc),
+ pci_driver);
+DRIVER_MODULE(xlp_pci, pcib, xlp_pci_driver, pci_devclass, 0, 0);
+
+static devclass_t pcib_devclass;
+static struct rman irq_rman, port_rman, mem_rman, emul_rman;
+
+static void
+xlp_pcib_init_resources(void)
+{
+ irq_rman.rm_start = 0;
+ irq_rman.rm_end = 255;
+ irq_rman.rm_type = RMAN_ARRAY;
+ irq_rman.rm_descr = "PCI Mapped Interrupts";
+ if (rman_init(&irq_rman)
+ || rman_manage_region(&irq_rman, 0, 255))
+ panic("pci_init_resources irq_rman");
+
+ port_rman.rm_start = 0;
+ port_rman.rm_end = ~0ul;
+ port_rman.rm_type = RMAN_ARRAY;
+ port_rman.rm_descr = "I/O ports";
+ if (rman_init(&port_rman)
+ || rman_manage_region(&port_rman, PCIE_IO_BASE, PCIE_IO_LIMIT))
+ panic("pci_init_resources port_rman");
+
+ mem_rman.rm_start = 0;
+ mem_rman.rm_end = ~0ul;
+ mem_rman.rm_type = RMAN_ARRAY;
+ mem_rman.rm_descr = "I/O memory";
+ if (rman_init(&mem_rman)
+ || rman_manage_region(&mem_rman, PCIE_MEM_BASE, PCIE_MEM_LIMIT))
+ panic("pci_init_resources mem_rman");
+
+ /*
+ * This includes the GBU (nor flash) memory range and the PCIe
+ * memory area.
+ */
+ emul_rman.rm_start = 0;
+ emul_rman.rm_end = ~0ul;
+ emul_rman.rm_type = RMAN_ARRAY;
+ emul_rman.rm_descr = "Emulated MEMIO";
+ if (rman_init(&emul_rman)
+ || rman_manage_region(&emul_rman, EMUL_MEM_START, EMUL_MEM_END))
+ panic("pci_init_resources emul_rman");
+}
+
+static int
+xlp_pcib_probe(device_t dev)
+{
+
+ device_set_desc(dev, "XLP PCI bus");
+ return (BUS_PROBE_NOWILDCARD);
+}
+
+static int
+xlp_pcib_read_ivar(device_t dev, device_t child, int which, uintptr_t *result)
+{
+
+ switch (which) {
+ case PCIB_IVAR_DOMAIN:
+ *result = 0;
+ return (0);
+ case PCIB_IVAR_BUS:
+ *result = 0;
+ return (0);
+ }
+ return (ENOENT);
+}
+
+static int
+xlp_pcib_write_ivar(device_t dev, device_t child, int which, uintptr_t result)
+{
+ switch (which) {
+ case PCIB_IVAR_DOMAIN:
+ return (EINVAL);
+ case PCIB_IVAR_BUS:
+ return (EINVAL);
+ }
+ return (ENOENT);
+}
+
+static int
+xlp_pcib_maxslots(device_t dev)
+{
+
+ return (PCI_SLOTMAX);
+}
+
+static u_int32_t
+xlp_pcib_read_config(device_t dev, u_int b, u_int s, u_int f,
+ u_int reg, int width)
+{
+ uint32_t data = 0;
+ uint64_t cfgaddr;
+ int regindex = reg/sizeof(uint32_t);
+
+ cfgaddr = nlm_pcicfg_base(XLP_HDR_OFFSET(0, b, s, f));
+ if ((width == 2) && (reg & 1))
+ return 0xFFFFFFFF;
+ else if ((width == 4) && (reg & 3))
+ return 0xFFFFFFFF;
+
+ /*
+ * The intline and int pin of SoC devices are DOA, except
+ * for bridges (slot %8 == 1).
+ * use the values we stashed in a writable PCI scratch reg.
+ */
+ if (b == 0 && regindex == 0xf && s % 8 > 1)
+ regindex = XLP_PCI_DEVSCRATCH_REG0;
+
+ data = nlm_read_pci_reg(cfgaddr, regindex);
+ if (width == 1)
+ return ((data >> ((reg & 3) << 3)) & 0xff);
+ else if (width == 2)
+ return ((data >> ((reg & 3) << 3)) & 0xffff);
+ else
+ return (data);
+}
+
+static void
+xlp_pcib_write_config(device_t dev, u_int b, u_int s, u_int f,
+ u_int reg, u_int32_t val, int width)
+{
+ uint64_t cfgaddr;
+ uint32_t data = 0;
+ int regindex = reg / sizeof(uint32_t);
+
+ cfgaddr = nlm_pcicfg_base(XLP_HDR_OFFSET(0, b, s, f));
+ if ((width == 2) && (reg & 1))
+ return;
+ else if ((width == 4) && (reg & 3))
+ return;
+
+ if (width == 1) {
+ data = nlm_read_pci_reg(cfgaddr, regindex);
+ data = (data & ~(0xff << ((reg & 3) << 3))) |
+ (val << ((reg & 3) << 3));
+ } else if (width == 2) {
+ data = nlm_read_pci_reg(cfgaddr, regindex);
+ data = (data & ~(0xffff << ((reg & 3) << 3))) |
+ (val << ((reg & 3) << 3));
+ } else {
+ data = val;
+ }
+
+ /*
+ * use shadow reg for intpin/intline which are dead
+ */
+ if (b == 0 && regindex == 0xf && s % 8 > 1)
+ regindex = XLP_PCI_DEVSCRATCH_REG0;
+ nlm_write_pci_reg(cfgaddr, regindex, data);
+}
+
+/*
+ * Enable byte swap in hardware when compiled big-endian.
+ * Programs a link's PCIe SWAP regions from the link's IO and MEM address
+ * ranges.
+ */
+static void
+xlp_pcib_hardware_swap_enable(int node, int link)
+{
+#if BYTE_ORDER == BIG_ENDIAN
+ uint64_t bbase, linkpcibase;
+ uint32_t bar;
+ int pcieoffset;
+
+ pcieoffset = XLP_IO_PCIE_OFFSET(node, link);
+ if (!nlm_dev_exists(pcieoffset))
+ return;
+
+ bbase = nlm_get_bridge_regbase(node);
+ linkpcibase = nlm_pcicfg_base(pcieoffset);
+ bar = nlm_read_bridge_reg(bbase, BRIDGE_PCIEMEM_BASE0 + link);
+ nlm_write_pci_reg(linkpcibase, PCIE_BYTE_SWAP_MEM_BASE, bar);
+
+ bar = nlm_read_bridge_reg(bbase, BRIDGE_PCIEMEM_LIMIT0 + link);
+ nlm_write_pci_reg(linkpcibase, PCIE_BYTE_SWAP_MEM_LIM, bar | 0xFFF);
+
+ bar = nlm_read_bridge_reg(bbase, BRIDGE_PCIEIO_BASE0 + link);
+ nlm_write_pci_reg(linkpcibase, PCIE_BYTE_SWAP_IO_BASE, bar);
+
+ bar = nlm_read_bridge_reg(bbase, BRIDGE_PCIEIO_LIMIT0 + link);
+ nlm_write_pci_reg(linkpcibase, PCIE_BYTE_SWAP_IO_LIM, bar | 0xFFF);
+#endif
+}
+
+static int
+xlp_pcib_attach(device_t dev)
+{
+ int node, link;
+
+ xlp_pcib_init_resources();
+
+ /* enable hardware swap on all nodes/links */
+ for (node = 0; node < XLP_MAX_NODES; node++)
+ for (link = 0; link < 4; link++)
+ xlp_pcib_hardware_swap_enable(node, link);
+
+ device_add_child(dev, "pci", 0);
+ bus_generic_attach(dev);
+ return (0);
+}
+
+static void
+xlp_pcib_identify(driver_t * driver, device_t parent)
+{
+
+ BUS_ADD_CHILD(parent, 0, "pcib", 0);
+}
+
+/*
+ * XLS PCIe can have upto 4 links, and each link has its on IRQ
+ * Find the link on which the device is on
+ */
+static int
+xlp_pcie_link(device_t pcib, device_t dev)
+{
+ device_t parent, tmp;
+
+ /* find the lane on which the slot is connected to */
+ tmp = dev;
+ while (1) {
+ parent = device_get_parent(tmp);
+ if (parent == NULL || parent == pcib) {
+ device_printf(dev, "Cannot find parent bus\n");
+ return (-1);
+ }
+ if (strcmp(device_get_nameunit(parent), "pci0") == 0)
+ break;
+ tmp = parent;
+ }
+ return (pci_get_function(tmp));
+}
+
+static int
+xlp_alloc_msi(device_t pcib, device_t dev, int count, int maxcount, int *irqs)
+{
+ int i, link;
+
+ /*
+ * Each link has 32 MSIs that can be allocated, but for now
+ * we only support one device per link.
+ * msi_alloc() equivalent is needed when we start supporting
+ * bridges on the PCIe link.
+ */
+ link = xlp_pcie_link(pcib, dev);
+ if (link == -1)
+ return (ENXIO);
+
+ /*
+ * encode the irq so that we know it is a MSI interrupt when we
+ * setup interrupts
+ */
+ for (i = 0; i < count; i++)
+ irqs[i] = 64 + link * 32 + i;
+
+ return (0);
+}
+
+static int
+xlp_release_msi(device_t pcib, device_t dev, int count, int *irqs)
+{
+ return (0);
+}
+
+static int
+xlp_map_msi(device_t pcib, device_t dev, int irq, uint64_t *addr,
+ uint32_t *data)
+{
+ int msi, irt;
+
+ if (irq >= 64) {
+ msi = irq - 64;
+ *addr = MIPS_MSI_ADDR(0);
+
+ irt = xlp_pcie_link_irt(msi/32);
+ if (irt != -1)
+ *data = MIPS_MSI_DATA(xlp_irt_to_irq(irt));
+ return (0);
+ } else {
+ device_printf(dev, "%s: map_msi for irq %d - ignored",
+ device_get_nameunit(pcib), irq);
+ return (ENXIO);
+ }
+}
+
+static void
+bridge_pcie_ack(int irq)
+{
+ uint32_t node,reg;
+ uint64_t base;
+
+ node = nlm_nodeid();
+ reg = PCIE_MSI_STATUS;
+
+ switch (irq) {
+ case PIC_PCIE_0_IRQ:
+ base = nlm_pcicfg_base(XLP_IO_PCIE0_OFFSET(node));
+ break;
+ case PIC_PCIE_1_IRQ:
+ base = nlm_pcicfg_base(XLP_IO_PCIE1_OFFSET(node));
+ break;
+ case PIC_PCIE_2_IRQ:
+ base = nlm_pcicfg_base(XLP_IO_PCIE2_OFFSET(node));
+ break;
+ case PIC_PCIE_3_IRQ:
+ base = nlm_pcicfg_base(XLP_IO_PCIE3_OFFSET(node));
+ break;
+ default:
+ return;
+ }
+
+ nlm_write_pci_reg(base, reg, 0xFFFFFFFF);
+ return;
+}
+
+static int
+mips_platform_pcib_setup_intr(device_t dev, device_t child,
+ struct resource *irq, int flags, driver_filter_t *filt,
+ driver_intr_t *intr, void *arg, void **cookiep)
+{
+ int error = 0;
+ int xlpirq;
+ void *extra_ack;
+
+ error = rman_activate_resource(irq);
+ if (error)
+ return error;
+ if (rman_get_start(irq) != rman_get_end(irq)) {
+ device_printf(dev, "Interrupt allocation %lu != %lu\n",
+ rman_get_start(irq), rman_get_end(irq));
+ return (EINVAL);
+ }
+ xlpirq = rman_get_start(irq);
+ if (xlpirq == 0)
+ return (0);
+
+ if (strcmp(device_get_name(dev), "pcib") != 0)
+ return (0);
+
+ /*
+ * temporary hack for MSI, we support just one device per
+ * link, and assign the link interrupt to the device interrupt
+ */
+ if (xlpirq >= 64) {
+ int node, val, link;
+ uint64_t base;
+
+ xlpirq -= 64;
+ if (xlpirq % 32 != 0)
+ return (0);
+
+ node = nlm_nodeid();
+ link = xlpirq / 32;
+ base = nlm_pcicfg_base(XLP_IO_PCIE_OFFSET(node,link));
+
+ /* MSI Interrupt Vector enable at bridge's configuration */
+ nlm_write_pci_reg(base, PCIE_MSI_EN, PCIE_MSI_VECTOR_INT_EN);
+
+ val = nlm_read_pci_reg(base, PCIE_INT_EN0);
+ /* MSI Interrupt enable at bridge's configuration */
+ nlm_write_pci_reg(base, PCIE_INT_EN0,
+ (val | PCIE_MSI_INT_EN));
+
+ /* legacy interrupt disable at bridge */
+ val = nlm_read_pci_reg(base, PCIE_BRIDGE_CMD);
+ nlm_write_pci_reg(base, PCIE_BRIDGE_CMD,
+ (val | PCIM_CMD_INTxDIS));
+
+ /* MSI address update at bridge */
+ nlm_write_pci_reg(base, PCIE_BRIDGE_MSI_ADDRL,
+ MSI_MIPS_ADDR_BASE);
+ nlm_write_pci_reg(base, PCIE_BRIDGE_MSI_ADDRH, 0);
+
+ val = nlm_read_pci_reg(base, PCIE_BRIDGE_MSI_CAP);
+ /* MSI capability enable at bridge */
+ nlm_write_pci_reg(base, PCIE_BRIDGE_MSI_CAP,
+ (val | (PCIM_MSICTRL_MSI_ENABLE << 16) |
+ (PCIM_MSICTRL_MMC_32 << 16)));
+
+ xlpirq = xlp_pcie_link_irt(xlpirq / 32);
+ if (xlpirq == -1)
+ return (EINVAL);
+ xlpirq = xlp_irt_to_irq(xlpirq);
+ }
+ /* Set all irqs to CPU 0 for now */
+ nlm_pic_write_irt_direct(xlp_pic_base, xlp_irq_to_irt(xlpirq), 1, 0,
+ PIC_LOCAL_SCHEDULING, xlpirq, 0);
+ extra_ack = NULL;
+ if (xlpirq >= PIC_PCIE_0_IRQ && xlpirq <= PIC_PCIE_3_IRQ)
+ extra_ack = bridge_pcie_ack;
+ xlp_establish_intr(device_get_name(child), filt,
+ intr, arg, xlpirq, flags, cookiep, extra_ack);
+
+ return (0);
+}
+
+static int
+mips_platform_pcib_teardown_intr(device_t dev, device_t child,
+ struct resource *irq, void *cookie)
+{
+ if (strcmp(device_get_name(child), "pci") == 0) {
+ /* if needed reprogram the pic to clear pcix related entry */
+ device_printf(dev, "teardown intr\n");
+ }
+ return (bus_generic_teardown_intr(dev, child, irq, cookie));
+}
+
+static struct resource *
+xlp_pcib_alloc_resource(device_t bus, device_t child, int type, int *rid,
+ u_long start, u_long end, u_long count, u_int flags)
+{
+ struct rman *rm = NULL;
+ struct resource *rv;
+ void *va;
+ int needactivate = flags & RF_ACTIVE;
+
+ switch (type) {
+ case SYS_RES_IRQ:
+ rm = &irq_rman;
+ break;
+
+ case SYS_RES_IOPORT:
+ rm = &port_rman;
+ break;
+
+ case SYS_RES_MEMORY:
+ if (start >= EMUL_MEM_START && start <= EMUL_MEM_END)
+ rm = &emul_rman;
+ else
+ rm = &mem_rman;
+ break;
+
+ default:
+ return (0);
+ }
+
+ rv = rman_reserve_resource(rm, start, end, count, flags, child);
+ if (rv == NULL)
+ return (NULL);
+
+ rman_set_rid(rv, *rid);
+
+ if (type == SYS_RES_MEMORY || type == SYS_RES_IOPORT) {
+ va = pmap_mapdev(start, count);
+ rman_set_bushandle(rv, (bus_space_handle_t)va);
+ rman_set_bustag(rv, rmi_bus_space);
+ }
+ if (needactivate) {
+ if (bus_activate_resource(child, type, *rid, rv)) {
+ rman_release_resource(rv);
+ return (NULL);
+ }
+ }
+ return (rv);
+}
+
+static int
+xlp_pcib_release_resource(device_t bus, device_t child, int type, int rid,
+ struct resource *r)
+{
+
+ return (rman_release_resource(r));
+}
+
+static int
+xlp_pcib_activate_resource(device_t bus, device_t child, int type, int rid,
+ struct resource *r)
+{
+
+ return (rman_activate_resource(r));
+}
+
+static int
+xlp_pcib_deactivate_resource(device_t bus, device_t child, int type, int rid,
+ struct resource *r)
+{
+
+ return (rman_deactivate_resource(r));
+}
+
+static int
+mips_pcib_route_interrupt(device_t bus, device_t dev, int pin)
+{
+ int irt, link;
+
+ /*
+ * Validate requested pin number.
+ */
+ if ((pin < 1) || (pin > 4))
+ return (255);
+
+ if (pci_get_bus(dev) == 0 &&
+ pci_get_vendor(dev) == PCI_VENDOR_NETLOGIC) {
+ /* SoC devices */
+ uint64_t pcibase;
+ int f, n, d, num;
+
+ f = pci_get_function(dev);
+ n = pci_get_slot(dev) / 8;
+ d = pci_get_slot(dev) % 8;
+
+ /*
+ * For PCIe links, return link IRT, for other SoC devices
+ * get the IRT from its PCIe header
+ */
+ if (d == 1) {
+ irt = xlp_pcie_link_irt(f);
+ } else {
+ pcibase = nlm_pcicfg_base(XLP_HDR_OFFSET(n, 0, d, f));
+ irt = nlm_irtstart(pcibase);
+ num = nlm_irtnum(pcibase);
+ if (num != 1)
+ device_printf(bus, "[%d:%d:%d] Error %d IRQs\n",
+ n, d, f, num);
+ }
+ } else {
+ /* Regular PCI devices */
+ link = xlp_pcie_link(bus, dev);
+ irt = xlp_pcie_link_irt(link);
+ }
+
+ if (irt != -1)
+ return (xlp_irt_to_irq(irt));
+
+ return (255);
+}
+
+static device_method_t xlp_pcib_methods[] = {
+ /* Device interface */
+ DEVMETHOD(device_identify, xlp_pcib_identify),
+ DEVMETHOD(device_probe, xlp_pcib_probe),
+ DEVMETHOD(device_attach, xlp_pcib_attach),
+
+ /* Bus interface */
+ DEVMETHOD(bus_read_ivar, xlp_pcib_read_ivar),
+ DEVMETHOD(bus_write_ivar, xlp_pcib_write_ivar),
+ DEVMETHOD(bus_alloc_resource, xlp_pcib_alloc_resource),
+ DEVMETHOD(bus_release_resource, xlp_pcib_release_resource),
+ DEVMETHOD(bus_activate_resource, xlp_pcib_activate_resource),
+ DEVMETHOD(bus_deactivate_resource, xlp_pcib_deactivate_resource),
+ DEVMETHOD(bus_setup_intr, mips_platform_pcib_setup_intr),
+ DEVMETHOD(bus_teardown_intr, mips_platform_pcib_teardown_intr),
+
+ /* pcib interface */
+ DEVMETHOD(pcib_maxslots, xlp_pcib_maxslots),
+ DEVMETHOD(pcib_read_config, xlp_pcib_read_config),
+ DEVMETHOD(pcib_write_config, xlp_pcib_write_config),
+ DEVMETHOD(pcib_route_interrupt, mips_pcib_route_interrupt),
+
+ DEVMETHOD(pcib_alloc_msi, xlp_alloc_msi),
+ DEVMETHOD(pcib_release_msi, xlp_release_msi),
+ DEVMETHOD(pcib_map_msi, xlp_map_msi),
+
+ DEVMETHOD_END
+};
+
+static driver_t xlp_pcib_driver = {
+ "pcib",
+ xlp_pcib_methods,
+ 1, /* no softc */
+};
+
+DRIVER_MODULE(pcib, nexus, xlp_pcib_driver, pcib_devclass, 0, 0);
Property changes on: trunk/sys/mips/nlm/xlp_pci.c
___________________________________________________________________
Added: svn:eol-style
## -0,0 +1 ##
+native
\ No newline at end of property
Added: svn:keywords
## -0,0 +1 ##
+MidnightBSD=%H
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+text/plain
\ No newline at end of property
Added: trunk/sys/mips/rmi/Makefile.msgring
===================================================================
--- trunk/sys/mips/rmi/Makefile.msgring (rev 0)
+++ trunk/sys/mips/rmi/Makefile.msgring 2018-05-26 21:55:02 UTC (rev 9987)
@@ -0,0 +1,14 @@
+RM = rm
+MSGRNG_CFG = msgring.cfg
+
+MSGRNG_CFG_C = $(patsubst %.cfg,%.c,$(MSGRNG_CFG))
+
+#all: msgring.l msgring.y msgring.cfg
+all: $(MSGRNG_CFG)
+ flex -omsgring.lex.c msgring.l
+ bison -d -omsgring.yacc.c msgring.y
+ gcc -g3 msgring.lex.c msgring.yacc.c -o msgring
+ ./msgring -i $(MSGRNG_CFG) -o $(MSGRNG_CFG_C)
+
+clean:
+ $(RM) -f msgring.lex.c msgring.yacc.c msgring.yacc.h msgring msgring.o*
Property changes on: trunk/sys/mips/rmi/Makefile.msgring
___________________________________________________________________
Added: mnbsd:nokeywords
## -0,0 +1 ##
+MidnightBSD=%H
\ No newline at end of property
Added: svn:eol-style
## -0,0 +1 ##
+native
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+text/plain
\ No newline at end of property
Added: trunk/sys/mips/rmi/board.c
===================================================================
--- trunk/sys/mips/rmi/board.c (rev 0)
+++ trunk/sys/mips/rmi/board.c 2018-05-26 21:55:02 UTC (rev 9987)
@@ -0,0 +1,594 @@
+/* $MidnightBSD$ */
+/*********************************************************************
+ *
+ * Copyright 2003-2006 Raza Microelectronics, Inc. (RMI). All rights
+ * reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in
+ * the documentation and/or other materials provided with the
+ * distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY Raza Microelectronics, Inc. ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL RMI OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES, LOSS OF USE, DATA, OR PROFITS, OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
+ * THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * *****************************RMI_2**********************************/
+#include <sys/cdefs.h> /* RCS ID & Copyright macro defns */
+__FBSDID("$FreeBSD: stable/10/sys/mips/rmi/board.c 216390 2010-12-12 06:00:26Z jchandra $");
+#include <sys/param.h>
+#include <sys/systm.h>
+#include <sys/bus.h>
+#include <sys/kernel.h>
+#include <sys/lock.h>
+#include <sys/mutex.h>
+
+#include <machine/cpufunc.h>
+#include <mips/rmi/msgring.h>
+#include <mips/rmi/rmi_boot_info.h>
+#include <mips/rmi/board.h>
+#include <mips/rmi/pic.h>
+
+#define XLR_I2C_RTC_ADDR 0xd0
+#define XLR_I2C_EEPROM_ADDR 0xa0
+#define XLR_I2C_TEMPSENSOR_ADDR 0x98
+#define XLR_I2C_ATX8_TEMPSENSOR_ADDR 0x9a
+
+struct stn_cc *xlr_core_cc_configs[] = { &cc_table_cpu_0, &cc_table_cpu_1,
+ &cc_table_cpu_2, &cc_table_cpu_3, &cc_table_cpu_4, &cc_table_cpu_5,
+ &cc_table_cpu_6, &cc_table_cpu_7};
+
+struct stn_cc *xls_core_cc_configs[] = { &xls_cc_table_cpu_0, &xls_cc_table_cpu_1,
+ &xls_cc_table_cpu_2, &xls_cc_table_cpu_3 };
+
+struct xlr_board_info xlr_board_info;
+
+static int
+xlr_pcmcia_present(void)
+{
+ xlr_reg_t *mmio = xlr_io_mmio(XLR_IO_GPIO_OFFSET);
+ uint32_t resetconf;
+
+ resetconf = xlr_read_reg(mmio, 21);
+ return ((resetconf & 0x4000) != 0);
+}
+
+static void
+xlr_chip_specific_overrides(struct xlr_board_info* board)
+{
+ struct xlr_gmac_block_t *blk0, *blk1, *blk2;
+ uint32_t chipid;
+ uint32_t revision;
+
+ blk0 = &board->gmac_block[0];
+ blk1 = &board->gmac_block[1];
+ blk2 = &board->gmac_block[2];
+
+ chipid = xlr_processor_id();
+ revision = xlr_revision();
+
+ if (revision == 0x04) { /* B2 */
+ switch (chipid) {
+ case 0x07: /* XLR 508 */
+ case 0x08: /* XLR 516 */
+ case 0x09: /* XLR 532 */
+ /* NA[12] not available */
+ memset(blk1, 0, sizeof(*blk1));
+ memset(blk2, 0, sizeof(*blk2));
+ break;
+ case 0x06: /* XLR 308 */
+ /* NA0 has 3 ports */
+ blk0->gmac_port[3].valid = 0;
+ blk0->num_ports--;
+ /* NA[12] not available */
+ memset(blk1, 0, sizeof(*blk1));
+ memset(blk2, 0, sizeof(*blk2));
+ break;
+ default:
+ break;
+ }
+ } else if (revision == 0x91) { /* C4 */
+ switch (chipid) {
+ case 0x0B: /* XLR 508 */
+ case 0x0A: /* XLR 516 */
+ case 0x08: /* XLR 532 */
+ /* NA[12] not available */
+ memset(blk1, 0, sizeof(*blk1));
+ memset(blk2, 0, sizeof(*blk2));
+ break;
+ case 0x0F: /* XLR 308 */
+ /* NA0 has 3 ports */
+ blk0->gmac_port[3].valid = 0;
+ blk0->num_ports--;
+ /* NA[12] not available */
+ memset(blk1, 0, sizeof(*blk1));
+ memset(blk2, 0, sizeof(*blk2));
+ break;
+ default:
+ break;
+ }
+ } else { /* other pre-production silicon */
+ switch (chipid) {
+ /* XLR 5xx */
+ case 0x0B:
+ case 0x0A:
+ case 0x07:
+ case 0x08:
+ case 0x09:
+ /* NA[12] not available */
+ memset(blk1, 0, sizeof(*blk1));
+ memset(blk2, 0, sizeof(*blk2));
+ break;
+ /* XLR 3xx */
+ case 0x0F:
+ case 0x06:
+ /* NA0 has 3 ports */
+ blk0->gmac_port[3].valid = 0;
+ blk0->num_ports--;
+ /* NA[12] not available */
+ memset(blk1, 0, sizeof(*blk1));
+ memset(blk2, 0, sizeof(*blk2));
+ break;
+ default:
+ break;
+ }
+ }
+}
+
+static void
+xlr_board_specific_overrides(struct xlr_board_info* board)
+{
+ struct xlr_gmac_block_t *blk1, *blk2;
+
+ blk1 = &board->gmac_block[1];
+ blk2 = &board->gmac_block[2];
+
+ switch (xlr_boot1_info.board_major_version) {
+ case RMI_XLR_BOARD_ARIZONA_I:
+ /* ATX-I has SPI-4, not XGMAC */
+ blk1->type = XLR_SPI4;
+ blk1->enabled = 0; /* nlge does not
+ support SPI-4 */
+ blk2->type = XLR_SPI4;
+ blk2->enabled = 0;
+ break;
+
+ case RMI_XLR_BOARD_ARIZONA_II:
+ /* XGMII_A --> VSC7281, XGMII_B --> VSC7281 */
+ blk1->enabled = 1;
+ blk1->num_ports = 1;
+ blk1->gmac_port[0].valid = 1;
+
+ blk2->enabled = 1;
+ blk2->num_ports = 1;
+ blk2->gmac_port[0].valid = 1;
+ default:
+ break;
+ }
+}
+
+static int
+quad0_xaui(void)
+{
+ xlr_reg_t *gpio_mmio =
+ (unsigned int *)(DEFAULT_XLR_IO_BASE + XLR_IO_GPIO_OFFSET);
+ uint32_t bit24;
+
+ bit24 = (xlr_read_reg(gpio_mmio, 0x15) >> 24) & 0x1;
+ return (bit24);
+}
+
+static int
+quad1_xaui(void)
+{
+ xlr_reg_t *gpio_mmio =
+ (unsigned int *)(DEFAULT_XLR_IO_BASE + XLR_IO_GPIO_OFFSET);
+ uint32_t bit25;
+
+ bit25 = (xlr_read_reg(gpio_mmio, 0x15) >> 25) & 0x1;
+ return (bit25);
+}
+
+static void
+xls_chip_specific_overrides(struct xlr_board_info* board)
+{
+ struct xlr_gmac_block_t *blk0, *blk1;
+ uint32_t chipid;
+
+ blk0 = &board->gmac_block[0];
+ blk1 = &board->gmac_block[1];
+ chipid = xlr_processor_id();
+
+ switch (chipid) {
+ case 0x8E: /* XLS208 */
+ case 0x8F: /* XLS204 */
+ /* NA1 is not available */
+ memset(blk1, 0, sizeof(*blk1));
+ break;
+ case 0xCE: /* XLS108 */
+ case 0xCF: /* XLS104 */
+ /* NA0 has 3 ports */
+ blk0->gmac_port[3].valid = 0;
+ blk0->num_ports--;
+ /* NA1 is not available */
+ memset(blk1, 0, sizeof(*blk1));
+ break;
+ default:
+ break;
+ }
+}
+
+static void
+xls_board_specific_overrides(struct xlr_board_info* board)
+{
+ struct xlr_gmac_block_t *blk0, *blk1;
+ int i;
+ struct xlr_i2c_dev_t* iic_blk;
+
+ blk0 = &board->gmac_block[0];
+ blk1 = &board->gmac_block[1];
+
+ switch (xlr_boot1_info.board_major_version) {
+ case RMI_XLR_BOARD_ARIZONA_VI:
+ blk0->mode = XLR_PORT0_RGMII;
+ blk0->gmac_port[0].type = XLR_RGMII;
+ blk0->gmac_port[0].phy_addr = 0;
+ blk0->gmac_port[0].mii_addr = XLR_IO_GMAC_4_OFFSET;
+ /* Because of the Octal PHY, SGMII Quad1 is MII is also bound
+ * to the PHY attached to SGMII0_MDC/MDIO/MDINT. */
+ for (i = 0; i < 4; i++) {
+ blk1->gmac_port[i].mii_addr = XLR_IO_GMAC_0_OFFSET;
+ blk1->gmac_port[i].serdes_addr = XLR_IO_GMAC_0_OFFSET;
+ }
+ blk1->gmac_port[1].mii_addr = XLR_IO_GMAC_0_OFFSET;
+ blk1->gmac_port[2].mii_addr = XLR_IO_GMAC_0_OFFSET;
+ blk1->gmac_port[3].mii_addr = XLR_IO_GMAC_0_OFFSET;
+
+ blk1->gmac_port[1].serdes_addr = XLR_IO_GMAC_0_OFFSET;
+ blk1->gmac_port[2].serdes_addr = XLR_IO_GMAC_0_OFFSET;
+ blk1->gmac_port[3].serdes_addr = XLR_IO_GMAC_0_OFFSET;
+
+ /* RGMII MDIO interrupt is thru NA1 and SGMII MDIO
+ * interrupts for ports in blk1 are from NA0 */
+ blk0->gmac_port[0].mdint_id = 1;
+
+ blk1->gmac_port[0].mdint_id = 0;
+ blk1->gmac_port[1].mdint_id = 0;
+ blk1->gmac_port[2].mdint_id = 0;
+ blk1->gmac_port[3].mdint_id = 0;
+
+ /* If we have a 4xx lite chip, don't enable the
+ * GMACs which are disabled in hardware */
+ if (xlr_is_xls4xx_lite()) {
+ xlr_reg_t *mmio = xlr_io_mmio(XLR_IO_GPIO_OFFSET);
+ uint32_t tmp;
+
+ /* Port 6 & 7 are not enabled on the condor 4xx, figure
+ * this out from the GPIO fuse bank */
+ tmp = xlr_read_reg(mmio, 35);
+ if ((tmp & (3 << 28)) != 0) {
+ blk1->enabled = 0x3;
+ blk1->gmac_port[2].valid = 0;
+ blk1->gmac_port[3].valid = 0;
+ blk1->num_ports = 2;
+ }
+ }
+ break;
+
+ case RMI_XLR_BOARD_ARIZONA_VIII:
+ iic_blk = &xlr_board_info.xlr_i2c_device[I2C_THERMAL];
+ if (iic_blk->enabled) {
+ iic_blk->addr = XLR_I2C_ATX8_TEMPSENSOR_ADDR;
+ }
+ if (blk1->enabled) {
+ /* There is just one Octal PHY on the board and it is
+ * connected to the MII interface for NA Quad 0. */
+ for (i = 0; i < 4; i++) {
+ blk1->gmac_port[i].mii_addr =
+ XLR_IO_GMAC_0_OFFSET;
+ blk1->gmac_port[i].mdint_id = 0;
+ }
+ }
+ break;
+
+ case RMI_XLR_BOARD_ARIZONA_XI:
+ case RMI_XLR_BOARD_ARIZONA_XII:
+ if (quad0_xaui()) { /* GMAC ports 0-3 are set to XAUI */
+ /* only GMAC0 is active i.e, the 0-th port on this quad.
+ * Disable all the other 7 possible ports. */
+ for (i = 1; i < MAX_NA_PORTS; i++) {
+ memset(&blk0->gmac_port[i], 0,
+ sizeof(blk0->gmac_port[i]));
+ }
+ /* Setup for XAUI on N/w Acc0: gmac0 */
+ blk0->type = XLR_XGMAC;
+ blk0->mode = XLR_XAUI;
+ blk0->num_ports = 1;
+ blk0->gmac_port[0].type = XLR_XAUI;
+ blk1->gmac_port[0].phy_addr = 16;
+ blk0->gmac_port[0].tx_bucket_id = blk0->station_txbase;
+ /* Other addresses etc need not be modified as XAUI_0
+ * shares its addresses with SGMII GMAC_0, which was
+ * set in the caller. */
+ }
+ else {
+ blk0->num_ports = 1; /* only 1 RGMII port */
+ blk0->mode = XLR_PORT0_RGMII;
+ blk0->gmac_port[0].type = XLR_RGMII;
+ blk0->gmac_port[0].phy_addr = 0;
+ blk0->gmac_port[0].mii_addr = XLR_IO_GMAC_0_OFFSET;
+ }
+
+ if (quad1_xaui()) { /* GMAC ports 4-7 are used for XAUI */
+ /* only GMAC4 is active i.e, the 0-th port on this quad.
+ * Disable all the other 7 possible ports. */
+ for (i = 1; i < MAX_NA_PORTS; i++) {
+ memset(&blk1->gmac_port[i], 0,
+ sizeof(blk1->gmac_port[i]));
+ }
+ /* Setup for XAUI on N/w Acc1: gmac4 */
+ blk1->type = XLR_XGMAC;
+ blk1->mode = XLR_XAUI;
+ blk1->num_ports = 1;
+ /* XAUI and SGMII ports share FMN buckets on N/w Acc 1;
+ so, station_txbase, station_rfr need not be
+ patched up. */
+ blk1->gmac_port[0].type = XLR_XAUI;
+ blk1->gmac_port[0].phy_addr = 16;
+ blk1->gmac_port[0].tx_bucket_id = blk1->station_txbase;
+ /* Other addresses etc need not be modified as XAUI_1
+ * shares its addresses with SGMII GMAC_4, which was
+ * set in the caller. */
+ }
+ break;
+
+ default:
+ break;
+ }
+}
+
+/*
+ * All our knowledge of chip and board that cannot be detected by probing
+ * at run-time goes here
+ */
+int
+xlr_board_info_setup()
+{
+ struct xlr_gmac_block_t *blk0, *blk1, *blk2;
+ struct xlr_i2c_dev_t* iic_blk;
+ int i;
+
+ /* This setup code is long'ish because the same base driver
+ * (if_nlge.c) is used for different:
+ * - CPUs (XLR/XLS)
+ * - boards (for each CPU, multiple board configs are possible
+ * and available).
+ *
+ * At the time of writing, there are atleast 12 boards, 4 with XLR
+ * and 8 with XLS. This means that the base driver needs to work with
+ * 12 different configurations, with varying levels of differences.
+ * To accomodate the different configs, the xlr_board_info struct
+ * has various attributes for paramters that could be different.
+ * These attributes are setup here and can be used directly in the
+ * base driver.
+ * It was seen that the setup code is not entirely trivial and
+ * it is possible to organize it in different ways. In the following,
+ * we choose an approach that sacrifices code-compactness/speed for
+ * readability. This is because configuration code executes once
+ * per reboot and hence has a minimal performance impact.
+ * On the other hand, driver debugging/enhancements require
+ * that different engineers can quickly comprehend the setup
+ * sequence. Hence, readability is seen as the key requirement for
+ * this code. It is for the reader to decide how much of this
+ * requirement is met with the current code organization !!
+ *
+ * The initialization is organized thus:
+ *
+ * if (CPU is XLS) {
+ * // initialize per XLS architecture
+ * // default inits (per chip spec)
+ * // chip-specific overrides
+ * // board-specific overrides
+ * } else if (CPU is XLR) {
+ * // initialize per XLR architecture
+ * // default inits (per chip spec)
+ * // chip-specific overrides
+ * // board-specific overrides
+ * }
+ *
+ * For each CPU family, all the default initializations
+ * are done for a fully-loaded device of that family.
+ * This configuration is then adjusted for the actual
+ * chip id. This is followed up with board specific
+ * overrides.
+ */
+
+ /* start with a clean slate */
+ memset(&xlr_board_info, 0, sizeof(xlr_board_info));
+ xlr_board_info.ata = xlr_pcmcia_present();
+
+ blk0 = &xlr_board_info.gmac_block[0];
+ blk1 = &xlr_board_info.gmac_block[1];
+ blk2 = &xlr_board_info.gmac_block[2];
+
+ iic_blk = xlr_board_info.xlr_i2c_device;
+ iic_blk[I2C_RTC].enabled = 1;
+ iic_blk[I2C_RTC].addr = XLR_I2C_RTC_ADDR;
+ iic_blk[I2C_THERMAL].enabled = 1;
+ iic_blk[I2C_THERMAL].addr = XLR_I2C_TEMPSENSOR_ADDR;
+ iic_blk[I2C_EEPROM].enabled = 1;
+ iic_blk[I2C_EEPROM].addr = XLR_I2C_EEPROM_ADDR;
+
+ if (xlr_is_xls()) {
+ xlr_board_info.is_xls = 1;
+ xlr_board_info.nr_cpus = 8;
+ xlr_board_info.usb = 1;
+ /* Board version 8 has NAND flash */
+ xlr_board_info.cfi =
+ (xlr_boot1_info.board_major_version != RMI_XLR_BOARD_ARIZONA_VIII);
+ xlr_board_info.pci_irq = 0;
+ xlr_board_info.credit_configs = xls_core_cc_configs;
+ xlr_board_info.bucket_sizes = &xls_bucket_sizes;
+ xlr_board_info.gmacports = MAX_NA_PORTS;
+
+ /* ---------------- Network Acc 0 ---------------- */
+
+ blk0->type = XLR_GMAC;
+ blk0->enabled = 0xf;
+ blk0->credit_config = &xls_cc_table_gmac0;
+ blk0->station_id = MSGRNG_STNID_GMAC;
+ blk0->station_txbase = MSGRNG_STNID_GMACTX0;
+ blk0->station_rfr = MSGRNG_STNID_GMACRFR_0;
+ blk0->mode = XLR_SGMII;
+ blk0->baseaddr = XLR_IO_GMAC_0_OFFSET;
+ blk0->baseirq = PIC_GMAC_0_IRQ;
+ blk0->baseinst = 0;
+
+ /* By default, assume SGMII is setup. But this can change based
+ on board-specific or setting-specific info. */
+ for (i = 0; i < 4; i++) {
+ blk0->gmac_port[i].valid = 1;
+ blk0->gmac_port[i].instance = i + blk0->baseinst;
+ blk0->gmac_port[i].type = XLR_SGMII;
+ blk0->gmac_port[i].phy_addr = i + 16;
+ blk0->gmac_port[i].tx_bucket_id =
+ blk0->station_txbase + i;
+ blk0->gmac_port[i].mdint_id = 0;
+ blk0->num_ports++;
+ blk0->gmac_port[i].base_addr = XLR_IO_GMAC_0_OFFSET + i * 0x1000;
+ blk0->gmac_port[i].mii_addr = XLR_IO_GMAC_0_OFFSET;
+ blk0->gmac_port[i].pcs_addr = XLR_IO_GMAC_0_OFFSET;
+ blk0->gmac_port[i].serdes_addr = XLR_IO_GMAC_0_OFFSET;
+ }
+
+ /* ---------------- Network Acc 1 ---------------- */
+ blk1->type = XLR_GMAC;
+ blk1->enabled = 0xf;
+ blk1->credit_config = &xls_cc_table_gmac1;
+ blk1->station_id = MSGRNG_STNID_GMAC1;
+ blk1->station_txbase = MSGRNG_STNID_GMAC1_TX0;
+ blk1->station_rfr = MSGRNG_STNID_GMAC1_FR_0;
+ blk1->mode = XLR_SGMII;
+ blk1->baseaddr = XLR_IO_GMAC_4_OFFSET;
+ blk1->baseirq = PIC_XGS_0_IRQ;
+ blk1->baseinst = 4;
+
+ for (i = 0; i < 4; i++) {
+ blk1->gmac_port[i].valid = 1;
+ blk1->gmac_port[i].instance = i + blk1->baseinst;
+ blk1->gmac_port[i].type = XLR_SGMII;
+ blk1->gmac_port[i].phy_addr = i + 20;
+ blk1->gmac_port[i].tx_bucket_id =
+ blk1->station_txbase + i;
+ blk1->gmac_port[i].mdint_id = 1;
+ blk1->num_ports++;
+ blk1->gmac_port[i].base_addr = XLR_IO_GMAC_4_OFFSET + i * 0x1000;
+ blk1->gmac_port[i].mii_addr = XLR_IO_GMAC_4_OFFSET;
+ blk1->gmac_port[i].pcs_addr = XLR_IO_GMAC_4_OFFSET;
+ blk1->gmac_port[i].serdes_addr = XLR_IO_GMAC_0_OFFSET;
+ }
+
+ /* ---------------- Network Acc 2 ---------------- */
+ xlr_board_info.gmac_block[2].enabled = 0; /* disabled on XLS */
+
+ xls_chip_specific_overrides(&xlr_board_info);
+ xls_board_specific_overrides(&xlr_board_info);
+
+ } else { /* XLR */
+ xlr_board_info.is_xls = 0;
+ xlr_board_info.nr_cpus = 32;
+ xlr_board_info.usb = 0;
+ xlr_board_info.cfi = 1;
+ xlr_board_info.pci_irq = 0;
+ xlr_board_info.credit_configs = xlr_core_cc_configs;
+ xlr_board_info.bucket_sizes = &bucket_sizes;
+ xlr_board_info.gmacports = 4;
+
+ /* ---------------- GMAC0 ---------------- */
+ blk0->type = XLR_GMAC;
+ blk0->enabled = 0xf;
+ blk0->credit_config = &cc_table_gmac;
+ blk0->station_id = MSGRNG_STNID_GMAC;
+ blk0->station_txbase = MSGRNG_STNID_GMACTX0;
+ blk0->station_rfr = MSGRNG_STNID_GMACRFR_0;
+ blk0->mode = XLR_RGMII;
+ blk0->baseaddr = XLR_IO_GMAC_0_OFFSET;
+ blk0->baseirq = PIC_GMAC_0_IRQ;
+ blk0->baseinst = 0;
+
+ /* first, do the common/easy stuff for all the ports */
+ for (i = 0; i < 4; i++) {
+ blk0->gmac_port[i].valid = 1;
+ blk0->gmac_port[i].instance = i + blk0->baseinst;
+ blk0->gmac_port[i].type = XLR_RGMII;
+ blk0->gmac_port[i].phy_addr = i;
+ blk0->gmac_port[i].tx_bucket_id =
+ blk0->station_txbase + i;
+ blk0->gmac_port[i].mdint_id = 0;
+ blk0->gmac_port[i].base_addr = XLR_IO_GMAC_0_OFFSET + i * 0x1000;
+ blk0->gmac_port[i].mii_addr = XLR_IO_GMAC_0_OFFSET;
+ /* RGMII ports, no PCS/SERDES */
+ blk0->num_ports++;
+ }
+
+ /* ---------------- XGMAC0 ---------------- */
+ blk1->type = XLR_XGMAC;
+ blk1->mode = XLR_XGMII;
+ blk1->enabled = 0;
+ blk1->credit_config = &cc_table_xgs_0;
+ blk1->station_txbase = MSGRNG_STNID_XGS0_TX;
+ blk1->station_rfr = MSGRNG_STNID_XMAC0RFR;
+ blk1->station_id = MSGRNG_STNID_XGS0FR;
+ blk1->baseaddr = XLR_IO_XGMAC_0_OFFSET;
+ blk1->baseirq = PIC_XGS_0_IRQ;
+ blk1->baseinst = 4;
+
+ blk1->gmac_port[0].type = XLR_XGMII;
+ blk1->gmac_port[0].instance = 0;
+ blk1->gmac_port[0].phy_addr = 0;
+ blk1->gmac_port[0].base_addr = XLR_IO_XGMAC_0_OFFSET;
+ blk1->gmac_port[0].mii_addr = XLR_IO_XGMAC_0_OFFSET;
+ blk1->gmac_port[0].tx_bucket_id = blk1->station_txbase;
+ blk1->gmac_port[0].mdint_id = 1;
+
+ /* ---------------- XGMAC1 ---------------- */
+ blk2->type = XLR_XGMAC;
+ blk2->mode = XLR_XGMII;
+ blk2->enabled = 0;
+ blk2->credit_config = &cc_table_xgs_1;
+ blk2->station_txbase = MSGRNG_STNID_XGS1_TX;
+ blk2->station_rfr = MSGRNG_STNID_XMAC1RFR;
+ blk2->station_id = MSGRNG_STNID_XGS1FR;
+ blk2->baseaddr = XLR_IO_XGMAC_1_OFFSET;
+ blk2->baseirq = PIC_XGS_1_IRQ;
+ blk2->baseinst = 5;
+
+ blk2->gmac_port[0].type = XLR_XGMII;
+ blk2->gmac_port[0].instance = 0;
+ blk2->gmac_port[0].phy_addr = 0;
+ blk2->gmac_port[0].base_addr = XLR_IO_XGMAC_1_OFFSET;
+ blk2->gmac_port[0].mii_addr = XLR_IO_XGMAC_1_OFFSET;
+ blk2->gmac_port[0].tx_bucket_id = blk2->station_txbase;
+ blk2->gmac_port[0].mdint_id = 2;
+
+ /* Done with default setup. Now handle chip and board-specific
+ variations. */
+ xlr_chip_specific_overrides(&xlr_board_info);
+ xlr_board_specific_overrides(&xlr_board_info);
+ }
+ return 0;
+}
Property changes on: trunk/sys/mips/rmi/board.c
___________________________________________________________________
Added: svn:eol-style
## -0,0 +1 ##
+native
\ No newline at end of property
Added: svn:keywords
## -0,0 +1 ##
+MidnightBSD=%H
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+text/plain
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Added: trunk/sys/mips/rmi/board.h
===================================================================
--- trunk/sys/mips/rmi/board.h (rev 0)
+++ trunk/sys/mips/rmi/board.h 2018-05-26 21:55:02 UTC (rev 9987)
@@ -0,0 +1,251 @@
+/* $MidnightBSD$ */
+/*-
+ * Copyright (c) 2003-2009 RMI Corporation
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * 3. Neither the name of RMI Corporation, nor the names of its contributors,
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ * RMI_BSD
+ * $FreeBSD: stable/10/sys/mips/rmi/board.h 216390 2010-12-12 06:00:26Z jchandra $
+ */
+#ifndef _RMI_BOARD_H_
+#define _RMI_BOARD_H_
+
+/*
+ * Engineering boards have a major/minor number in their EEPROM to
+ * identify their configuration
+ */
+#define RMI_XLR_BOARD_ARIZONA_I 1
+#define RMI_XLR_BOARD_ARIZONA_II 2
+#define RMI_XLR_BOARD_ARIZONA_III 3
+#define RMI_XLR_BOARD_ARIZONA_IV 4
+#define RMI_XLR_BOARD_ARIZONA_V 5
+#define RMI_XLR_BOARD_ARIZONA_VI 6
+#define RMI_XLR_BOARD_ARIZONA_VII 7
+#define RMI_XLR_BOARD_ARIZONA_VIII 8
+#define RMI_XLR_BOARD_ARIZONA_XI 11
+#define RMI_XLR_BOARD_ARIZONA_XII 12
+
+/*
+ * RMI Chips - Values in Processor ID field
+ */
+#define RMI_CHIP_XLR732 0x00
+#define RMI_CHIP_XLR716 0x02
+#define RMI_CHIP_XLR308 0x06
+#define RMI_CHIP_XLR532 0x09
+
+/*
+ * XLR C revisions
+ */
+#define RMI_CHIP_XLR308_C 0x0F
+#define RMI_CHIP_XLR508_C 0x0b
+#define RMI_CHIP_XLR516_C 0x0a
+#define RMI_CHIP_XLR532_C 0x08
+
+/*
+ * XLS processors
+ */
+#define RMI_CHIP_XLS408 0x88 /* Lite "Condor" */
+#define RMI_CHIP_XLS608 0x80 /* Internal */
+#define RMI_CHIP_XLS404 0x8c /* Lite "Condor" */
+#define RMI_CHIP_XLS208 0x8e
+#define RMI_CHIP_XLS204 0x8f
+#define RMI_CHIP_XLS108 0xce
+#define RMI_CHIP_XLS104 0xcf
+
+/*
+ * XLS B revision chips
+ */
+#define RMI_CHIP_XLS616_B0 0x40
+#define RMI_CHIP_XLS608_B0 0x4a
+#define RMI_CHIP_XLS416_B0 0x44
+#define RMI_CHIP_XLS412_B0 0x4c
+#define RMI_CHIP_XLS408_B0 0x4e
+#define RMI_CHIP_XLS404_B0 0x4f
+
+/*
+ * The XLS product line has chip versions 0x4x and 0x8x
+ */
+static __inline unsigned int
+xlr_is_xls(void)
+{
+ uint32_t prid = mips_rd_prid();
+
+ return ((prid & 0xf000) == 0x8000 || (prid & 0xf000) == 0x4000 ||
+ (prid & 0xf000) == 0xc000);
+}
+
+/*
+ * The last byte of the processor id field is revision
+ */
+static __inline unsigned int
+xlr_revision(void)
+{
+
+ return (mips_rd_prid() & 0xff);
+}
+
+/*
+ * The 15:8 byte of the PR Id register is the Processor ID
+ */
+static __inline unsigned int
+xlr_processor_id(void)
+{
+
+ return ((mips_rd_prid() & 0xff00) >> 8);
+}
+
+/*
+ * The processor is XLR and C-Series
+ */
+static __inline unsigned int
+xlr_is_c_revision(void)
+{
+ int processor_id = xlr_processor_id();
+ int revision_id = xlr_revision();
+
+ switch (processor_id) {
+ /*
+ * These are the relevant PIDs for XLR
+ * steppings (hawk and above). For these,
+ * PIDs, Rev-Ids of [5-9] indicate 'C'.
+ */
+ case RMI_CHIP_XLR308_C:
+ case RMI_CHIP_XLR508_C:
+ case RMI_CHIP_XLR516_C:
+ case RMI_CHIP_XLR532_C:
+ case RMI_CHIP_XLR716:
+ case RMI_CHIP_XLR732:
+ if (revision_id >= 5 && revision_id <= 9)
+ return (1);
+ default:
+ return (0);
+ }
+ return (0);
+}
+
+/*
+ * RMI Engineering boards which are PCI cards
+ * These should come up in PCI device mode (not yet)
+ */
+static __inline int
+xlr_board_pci(int board_major)
+{
+
+ return ((board_major == RMI_XLR_BOARD_ARIZONA_III) ||
+ (board_major == RMI_XLR_BOARD_ARIZONA_V));
+}
+
+static __inline int
+xlr_is_xls1xx(void)
+{
+ uint32_t chipid = xlr_processor_id();
+
+ return (chipid == 0xce || chipid == 0xcf);
+}
+
+static __inline int
+xlr_is_xls2xx(void)
+{
+ uint32_t chipid = xlr_processor_id();
+
+ return (chipid == 0x8e || chipid == 0x8f);
+}
+
+static __inline int
+xlr_is_xls4xx_lite(void)
+{
+ uint32_t chipid = xlr_processor_id();
+
+ return (chipid == 0x88 || chipid == 0x8c);
+}
+
+static __inline unsigned int
+xlr_is_xls_b0(void)
+{
+ uint32_t chipid = xlr_processor_id();
+
+ return (chipid >= 0x40 && chipid <= 0x4f);
+}
+
+/* SPI-4 --> 8 ports, 1G MAC --> 4 ports and 10G MAC --> 1 port */
+#define MAX_NA_PORTS 8
+
+/* all our knowledge of chip and board that cannot be detected run-time goes here */
+enum gmac_block_types { XLR_GMAC, XLR_XGMAC, XLR_SPI4};
+enum gmac_port_types { XLR_RGMII, XLR_SGMII, XLR_PORT0_RGMII, XLR_XGMII, XLR_XAUI };
+enum i2c_dev_types { I2C_RTC, I2C_THERMAL, I2C_EEPROM };
+
+struct xlr_board_info {
+ int is_xls;
+ int nr_cpus;
+ int usb; /* usb enabled ? */
+ int cfi; /* compact flash driver for NOR? */
+ int ata; /* ata driver */
+ int pci_irq;
+ struct stn_cc **credit_configs; /* pointer to Core station credits */
+ struct bucket_size *bucket_sizes; /* pointer to Core station bucket */
+ int *msgmap; /* mapping of message station to devices */
+ int gmacports; /* number of gmac ports on the board */
+ struct xlr_i2c_dev_t {
+ uint32_t addr;
+ unsigned int enabled; /* mask of devs enabled */
+ int type;
+ int unit;
+ char *dev_name;
+ } xlr_i2c_device[3];
+ struct xlr_gmac_block_t { /* refers to the set of GMACs controlled by a
+ network accelarator */
+ int type; /* see enum gmac_block_types */
+ unsigned int enabled; /* mask of ports enabled */
+ struct stn_cc *credit_config; /* credit configuration */
+ int station_id; /* station id for sending msgs */
+ int station_txbase; /* station id for tx */
+ int station_rfr; /* free desc bucket */
+ int mode; /* see gmac_block_modes */
+ uint32_t baseaddr; /* IO base */
+ int baseirq; /* first irq for this block, the rest are in sequence */
+ int baseinst; /* the first rge unit for this block */
+ int num_ports;
+ struct xlr_gmac_port {
+ int valid;
+ int type; /* see enum gmac_port_types */
+ uint32_t instance; /* identifies the GMAC to which
+ this port is bound to. */
+ uint32_t phy_addr;
+ uint32_t base_addr;
+ uint32_t mii_addr;
+ uint32_t pcs_addr;
+ uint32_t serdes_addr;
+ uint32_t tx_bucket_id;
+ uint32_t mdint_id;
+ } gmac_port[MAX_NA_PORTS];
+ } gmac_block [3];
+};
+
+extern struct xlr_board_info xlr_board_info;
+int xlr_board_info_setup(void);
+
+#endif
Property changes on: trunk/sys/mips/rmi/board.h
___________________________________________________________________
Added: svn:eol-style
## -0,0 +1 ##
+native
\ No newline at end of property
Added: svn:keywords
## -0,0 +1 ##
+MidnightBSD=%H
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+text/plain
\ No newline at end of property
Added: trunk/sys/mips/rmi/bus_space_rmi.c
===================================================================
--- trunk/sys/mips/rmi/bus_space_rmi.c (rev 0)
+++ trunk/sys/mips/rmi/bus_space_rmi.c 2018-05-26 21:55:02 UTC (rev 9987)
@@ -0,0 +1,687 @@
+/* $MidnightBSD$ */
+/*-
+ * Copyright (c) 2009 RMI Corporation
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ * $FreeBSD: stable/10/sys/mips/rmi/bus_space_rmi.c 204131 2010-02-20 16:32:33Z rrs $
+ */
+#include <sys/cdefs.h>
+__FBSDID("$FreeBSD: stable/10/sys/mips/rmi/bus_space_rmi.c 204131 2010-02-20 16:32:33Z rrs $");
+
+#include <sys/param.h>
+#include <sys/systm.h>
+#include <sys/bus.h>
+#include <sys/kernel.h>
+#include <sys/endian.h>
+#include <sys/malloc.h>
+#include <sys/ktr.h>
+
+#include <vm/vm.h>
+#include <vm/pmap.h>
+#include <vm/vm_kern.h>
+#include <vm/vm_extern.h>
+
+#include <machine/bus.h>
+#include <machine/cache.h>
+
+static int
+rmi_bus_space_map(void *t, bus_addr_t addr,
+ bus_size_t size, int flags,
+ bus_space_handle_t * bshp);
+
+static void
+rmi_bus_space_unmap(void *t, bus_space_handle_t bsh,
+ bus_size_t size);
+
+static int
+rmi_bus_space_subregion(void *t,
+ bus_space_handle_t bsh,
+ bus_size_t offset, bus_size_t size,
+ bus_space_handle_t * nbshp);
+
+static u_int8_t
+rmi_bus_space_read_1(void *t,
+ bus_space_handle_t handle,
+ bus_size_t offset);
+
+static u_int16_t
+rmi_bus_space_read_2(void *t,
+ bus_space_handle_t handle,
+ bus_size_t offset);
+
+static u_int32_t
+rmi_bus_space_read_4(void *t,
+ bus_space_handle_t handle,
+ bus_size_t offset);
+
+static void
+rmi_bus_space_read_multi_1(void *t,
+ bus_space_handle_t handle,
+ bus_size_t offset, u_int8_t * addr,
+ size_t count);
+
+static void
+rmi_bus_space_read_multi_2(void *t,
+ bus_space_handle_t handle,
+ bus_size_t offset, u_int16_t * addr,
+ size_t count);
+
+static void
+rmi_bus_space_read_multi_4(void *t,
+ bus_space_handle_t handle,
+ bus_size_t offset, u_int32_t * addr,
+ size_t count);
+
+static void
+rmi_bus_space_read_region_1(void *t,
+ bus_space_handle_t bsh,
+ bus_size_t offset, u_int8_t * addr,
+ size_t count);
+
+static void
+rmi_bus_space_read_region_2(void *t,
+ bus_space_handle_t bsh,
+ bus_size_t offset, u_int16_t * addr,
+ size_t count);
+
+static void
+rmi_bus_space_read_region_4(void *t,
+ bus_space_handle_t bsh,
+ bus_size_t offset, u_int32_t * addr,
+ size_t count);
+
+static void
+rmi_bus_space_write_1(void *t,
+ bus_space_handle_t handle,
+ bus_size_t offset, u_int8_t value);
+
+static void
+rmi_bus_space_write_2(void *t,
+ bus_space_handle_t handle,
+ bus_size_t offset, u_int16_t value);
+
+static void
+rmi_bus_space_write_4(void *t,
+ bus_space_handle_t handle,
+ bus_size_t offset, u_int32_t value);
+
+static void
+rmi_bus_space_write_multi_1(void *t,
+ bus_space_handle_t handle,
+ bus_size_t offset,
+ const u_int8_t * addr,
+ size_t count);
+
+static void
+rmi_bus_space_write_multi_2(void *t,
+ bus_space_handle_t handle,
+ bus_size_t offset,
+ const u_int16_t * addr,
+ size_t count);
+
+static void
+rmi_bus_space_write_multi_4(void *t,
+ bus_space_handle_t handle,
+ bus_size_t offset,
+ const u_int32_t * addr,
+ size_t count);
+
+static void
+rmi_bus_space_write_region_2(void *t,
+ bus_space_handle_t bsh,
+ bus_size_t offset,
+ const u_int16_t * addr,
+ size_t count);
+
+static void
+rmi_bus_space_write_region_4(void *t,
+ bus_space_handle_t bsh,
+ bus_size_t offset,
+ const u_int32_t * addr,
+ size_t count);
+
+
+static void
+rmi_bus_space_set_region_2(void *t,
+ bus_space_handle_t bsh,
+ bus_size_t offset, u_int16_t value,
+ size_t count);
+static void
+rmi_bus_space_set_region_4(void *t,
+ bus_space_handle_t bsh,
+ bus_size_t offset, u_int32_t value,
+ size_t count);
+
+static void
+rmi_bus_space_barrier(void *tag __unused, bus_space_handle_t bsh __unused,
+ bus_size_t offset __unused, bus_size_t len __unused, int flags);
+
+static void
+rmi_bus_space_copy_region_2(void *t,
+ bus_space_handle_t bsh1,
+ bus_size_t off1,
+ bus_space_handle_t bsh2,
+ bus_size_t off2, size_t count);
+
+u_int8_t
+rmi_bus_space_read_stream_1(void *t, bus_space_handle_t handle,
+ bus_size_t offset);
+
+static u_int16_t
+rmi_bus_space_read_stream_2(void *t, bus_space_handle_t handle,
+ bus_size_t offset);
+
+static u_int32_t
+rmi_bus_space_read_stream_4(void *t, bus_space_handle_t handle,
+ bus_size_t offset);
+static void
+rmi_bus_space_read_multi_stream_1(void *t,
+ bus_space_handle_t handle,
+ bus_size_t offset, u_int8_t * addr,
+ size_t count);
+
+static void
+rmi_bus_space_read_multi_stream_2(void *t,
+ bus_space_handle_t handle,
+ bus_size_t offset, u_int16_t * addr,
+ size_t count);
+
+static void
+rmi_bus_space_read_multi_stream_4(void *t,
+ bus_space_handle_t handle,
+ bus_size_t offset, u_int32_t * addr,
+ size_t count);
+
+void
+rmi_bus_space_write_stream_1(void *t, bus_space_handle_t bsh,
+ bus_size_t offset, u_int8_t value);
+static void
+rmi_bus_space_write_stream_2(void *t, bus_space_handle_t handle,
+ bus_size_t offset, u_int16_t value);
+
+static void
+rmi_bus_space_write_stream_4(void *t, bus_space_handle_t handle,
+ bus_size_t offset, u_int32_t value);
+
+static void
+rmi_bus_space_write_multi_stream_1(void *t,
+ bus_space_handle_t handle,
+ bus_size_t offset,
+ const u_int8_t * addr,
+ size_t count);
+static void
+rmi_bus_space_write_multi_stream_2(void *t,
+ bus_space_handle_t handle,
+ bus_size_t offset,
+ const u_int16_t * addr,
+ size_t count);
+
+static void
+rmi_bus_space_write_multi_stream_4(void *t,
+ bus_space_handle_t handle,
+ bus_size_t offset,
+ const u_int32_t * addr,
+ size_t count);
+
+#define TODO() printf("XLR memory bus space function '%s' unimplemented\n", __func__)
+
+static struct bus_space local_rmi_bus_space = {
+ /* cookie */
+ (void *)0,
+
+ /* mapping/unmapping */
+ rmi_bus_space_map,
+ rmi_bus_space_unmap,
+ rmi_bus_space_subregion,
+
+ /* allocation/deallocation */
+ NULL,
+ NULL,
+
+ /* barrier */
+ rmi_bus_space_barrier,
+
+ /* read (single) */
+ rmi_bus_space_read_1,
+ rmi_bus_space_read_2,
+ rmi_bus_space_read_4,
+ NULL,
+
+ /* read multiple */
+ rmi_bus_space_read_multi_1,
+ rmi_bus_space_read_multi_2,
+ rmi_bus_space_read_multi_4,
+ NULL,
+
+ /* read region */
+ rmi_bus_space_read_region_1,
+ rmi_bus_space_read_region_2,
+ rmi_bus_space_read_region_4,
+ NULL,
+
+ /* write (single) */
+ rmi_bus_space_write_1,
+ rmi_bus_space_write_2,
+ rmi_bus_space_write_4,
+ NULL,
+
+ /* write multiple */
+ rmi_bus_space_write_multi_1,
+ rmi_bus_space_write_multi_2,
+ rmi_bus_space_write_multi_4,
+ NULL,
+
+ /* write region */
+ NULL,
+ rmi_bus_space_write_region_2,
+ rmi_bus_space_write_region_4,
+ NULL,
+
+ /* set multiple */
+ NULL,
+ NULL,
+ NULL,
+ NULL,
+
+ /* set region */
+ NULL,
+ rmi_bus_space_set_region_2,
+ rmi_bus_space_set_region_4,
+ NULL,
+
+ /* copy */
+ NULL,
+ rmi_bus_space_copy_region_2,
+ NULL,
+ NULL,
+
+ /* read (single) stream */
+ rmi_bus_space_read_stream_1,
+ rmi_bus_space_read_stream_2,
+ rmi_bus_space_read_stream_4,
+ NULL,
+
+ /* read multiple stream */
+ rmi_bus_space_read_multi_stream_1,
+ rmi_bus_space_read_multi_stream_2,
+ rmi_bus_space_read_multi_stream_4,
+ NULL,
+
+ /* read region stream */
+ rmi_bus_space_read_region_1,
+ rmi_bus_space_read_region_2,
+ rmi_bus_space_read_region_4,
+ NULL,
+
+ /* write (single) stream */
+ rmi_bus_space_write_stream_1,
+ rmi_bus_space_write_stream_2,
+ rmi_bus_space_write_stream_4,
+ NULL,
+
+ /* write multiple stream */
+ rmi_bus_space_write_multi_stream_1,
+ rmi_bus_space_write_multi_stream_2,
+ rmi_bus_space_write_multi_stream_4,
+ NULL,
+
+ /* write region stream */
+ NULL,
+ rmi_bus_space_write_region_2,
+ rmi_bus_space_write_region_4,
+ NULL,
+};
+
+/* generic bus_space tag */
+bus_space_tag_t rmi_bus_space = &local_rmi_bus_space;
+
+/*
+ * Map a region of device bus space into CPU virtual address space.
+ */
+static int
+rmi_bus_space_map(void *t __unused, bus_addr_t addr,
+ bus_size_t size __unused, int flags __unused,
+ bus_space_handle_t * bshp)
+{
+
+ *bshp = addr;
+ return (0);
+}
+
+/*
+ * Unmap a region of device bus space.
+ */
+static void
+rmi_bus_space_unmap(void *t __unused, bus_space_handle_t bsh __unused,
+ bus_size_t size __unused)
+{
+}
+
+/*
+ * Get a new handle for a subregion of an already-mapped area of bus space.
+ */
+
+static int
+rmi_bus_space_subregion(void *t __unused, bus_space_handle_t bsh,
+ bus_size_t offset, bus_size_t size __unused,
+ bus_space_handle_t * nbshp)
+{
+ *nbshp = bsh + offset;
+ return (0);
+}
+
+/*
+ * Read a 1, 2, 4, or 8 byte quantity from bus space
+ * described by tag/handle/offset.
+ */
+
+static u_int8_t
+rmi_bus_space_read_1(void *tag, bus_space_handle_t handle,
+ bus_size_t offset)
+{
+ return (u_int8_t) (*(volatile u_int32_t *)(handle + offset));
+}
+
+static u_int16_t
+rmi_bus_space_read_2(void *tag, bus_space_handle_t handle,
+ bus_size_t offset)
+{
+ return (u_int16_t)(*(volatile u_int32_t *)(handle + offset));
+}
+
+static u_int32_t
+rmi_bus_space_read_4(void *tag, bus_space_handle_t handle,
+ bus_size_t offset)
+{
+ return (*(volatile u_int32_t *)(handle + offset));
+}
+
+
+/*
+ * Read `count' 1, 2, 4, or 8 byte quantities from bus space
+ * described by tag/handle/offset and copy into buffer provided.
+ */
+static void
+rmi_bus_space_read_multi_1(void *tag, bus_space_handle_t handle,
+ bus_size_t offset, u_int8_t * addr, size_t count)
+{
+ TODO();
+}
+
+static void
+rmi_bus_space_read_multi_2(void *tag, bus_space_handle_t handle,
+ bus_size_t offset, u_int16_t * addr, size_t count)
+{
+ TODO();
+}
+
+static void
+rmi_bus_space_read_multi_4(void *tag, bus_space_handle_t handle,
+ bus_size_t offset, u_int32_t * addr, size_t count)
+{
+ TODO();
+}
+
+/*
+ * Write the 1, 2, 4, or 8 byte value `value' to bus space
+ * described by tag/handle/offset.
+ */
+
+static void
+rmi_bus_space_write_1(void *tag, bus_space_handle_t handle,
+ bus_size_t offset, u_int8_t value)
+{
+ *(volatile u_int32_t *)(handle + offset) = (u_int32_t)value;
+}
+
+static void
+rmi_bus_space_write_2(void *tag, bus_space_handle_t handle,
+ bus_size_t offset, u_int16_t value)
+{
+ *(volatile u_int32_t *)(handle + offset) = (u_int32_t)value;
+}
+
+static void
+rmi_bus_space_write_4(void *tag, bus_space_handle_t handle,
+ bus_size_t offset, u_int32_t value)
+{
+ *(volatile u_int32_t *)(handle + offset) = value;
+}
+
+
+/*
+ * Write `count' 1, 2, 4, or 8 byte quantities from the buffer
+ * provided to bus space described by tag/handle/offset.
+ */
+
+
+static void
+rmi_bus_space_write_multi_1(void *tag, bus_space_handle_t handle,
+ bus_size_t offset, const u_int8_t * addr, size_t count)
+{
+ TODO();
+}
+
+static void
+rmi_bus_space_write_multi_2(void *tag, bus_space_handle_t handle,
+ bus_size_t offset, const u_int16_t * addr, size_t count)
+{
+ TODO();
+}
+
+static void
+rmi_bus_space_write_multi_4(void *tag, bus_space_handle_t handle,
+ bus_size_t offset, const u_int32_t * addr, size_t count)
+{
+ TODO();
+}
+
+/*
+ * Write `count' 1, 2, 4, or 8 byte value `val' to bus space described
+ * by tag/handle starting at `offset'.
+ */
+
+static void
+rmi_bus_space_set_region_2(void *t, bus_space_handle_t bsh,
+ bus_size_t offset, u_int16_t value, size_t count)
+{
+ bus_addr_t addr = bsh + offset;
+
+ for (; count != 0; count--, addr += 2)
+ (*(volatile u_int32_t *)(addr)) = value;
+}
+
+static void
+rmi_bus_space_set_region_4(void *t, bus_space_handle_t bsh,
+ bus_size_t offset, u_int32_t value, size_t count)
+{
+ bus_addr_t addr = bsh + offset;
+
+ for (; count != 0; count--, addr += 4)
+ (*(volatile u_int32_t *)(addr)) = value;
+}
+
+
+/*
+ * Copy `count' 1, 2, 4, or 8 byte values from bus space starting
+ * at tag/bsh1/off1 to bus space starting at tag/bsh2/off2.
+ */
+static void
+rmi_bus_space_copy_region_2(void *t, bus_space_handle_t bsh1,
+ bus_size_t off1, bus_space_handle_t bsh2,
+ bus_size_t off2, size_t count)
+{
+ printf("bus_space_copy_region_2 - unimplemented\n");
+}
+
+/*
+ * Read `count' 1, 2, 4, or 8 byte quantities from bus space
+ * described by tag/handle/offset and copy into buffer provided.
+ */
+
+u_int8_t
+rmi_bus_space_read_stream_1(void *t, bus_space_handle_t handle,
+ bus_size_t offset)
+{
+
+ return *((volatile u_int8_t *)(handle + offset));
+}
+
+
+static u_int16_t
+rmi_bus_space_read_stream_2(void *t, bus_space_handle_t handle,
+ bus_size_t offset)
+{
+ return *(volatile u_int16_t *)(handle + offset);
+}
+
+
+static u_int32_t
+rmi_bus_space_read_stream_4(void *t, bus_space_handle_t handle,
+ bus_size_t offset)
+{
+ return (*(volatile u_int32_t *)(handle + offset));
+}
+
+
+static void
+rmi_bus_space_read_multi_stream_1(void *tag, bus_space_handle_t handle,
+ bus_size_t offset, u_int8_t * addr, size_t count)
+{
+ TODO();
+}
+
+static void
+rmi_bus_space_read_multi_stream_2(void *tag, bus_space_handle_t handle,
+ bus_size_t offset, u_int16_t * addr, size_t count)
+{
+ TODO();
+}
+
+static void
+rmi_bus_space_read_multi_stream_4(void *tag, bus_space_handle_t handle,
+ bus_size_t offset, u_int32_t * addr, size_t count)
+{
+ TODO();
+}
+
+
+/*
+ * Read `count' 1, 2, 4, or 8 byte quantities from bus space
+ * described by tag/handle and starting at `offset' and copy into
+ * buffer provided.
+ */
+void
+rmi_bus_space_read_region_1(void *t, bus_space_handle_t bsh,
+ bus_size_t offset, u_int8_t * addr, size_t count)
+{
+ TODO();
+}
+
+void
+rmi_bus_space_read_region_2(void *t, bus_space_handle_t bsh,
+ bus_size_t offset, u_int16_t * addr, size_t count)
+{
+ TODO();
+}
+
+void
+rmi_bus_space_read_region_4(void *t, bus_space_handle_t bsh,
+ bus_size_t offset, u_int32_t * addr, size_t count)
+{
+ bus_addr_t baddr = bsh + offset;
+
+ while (count--) {
+ *addr++ = (*(volatile u_int32_t *)(baddr));
+ baddr += 4;
+ }
+}
+
+void
+rmi_bus_space_write_stream_1(void *t, bus_space_handle_t handle,
+ bus_size_t offset, u_int8_t value)
+{
+ TODO();
+}
+
+
+static void
+rmi_bus_space_write_stream_2(void *t, bus_space_handle_t handle,
+ bus_size_t offset, u_int16_t value)
+{
+ TODO();
+}
+
+
+static void
+rmi_bus_space_write_stream_4(void *t, bus_space_handle_t handle,
+ bus_size_t offset, u_int32_t value)
+{
+ TODO();
+}
+
+
+static void
+rmi_bus_space_write_multi_stream_1(void *tag, bus_space_handle_t handle,
+ bus_size_t offset, const u_int8_t * addr, size_t count)
+{
+ TODO();
+}
+
+static void
+rmi_bus_space_write_multi_stream_2(void *tag, bus_space_handle_t handle,
+ bus_size_t offset, const u_int16_t * addr, size_t count)
+{
+ TODO();
+}
+
+static void
+rmi_bus_space_write_multi_stream_4(void *tag, bus_space_handle_t handle,
+ bus_size_t offset, const u_int32_t * addr, size_t count)
+{
+ TODO();
+}
+
+void
+rmi_bus_space_write_region_2(void *t,
+ bus_space_handle_t bsh,
+ bus_size_t offset,
+ const u_int16_t * addr,
+ size_t count)
+{
+ TODO();
+}
+
+void
+rmi_bus_space_write_region_4(void *t, bus_space_handle_t bsh,
+ bus_size_t offset, const u_int32_t * addr, size_t count)
+{
+ TODO();
+}
+
+static void
+rmi_bus_space_barrier(void *tag __unused, bus_space_handle_t bsh __unused,
+ bus_size_t offset __unused, bus_size_t len __unused, int flags)
+{
+}
Property changes on: trunk/sys/mips/rmi/bus_space_rmi.c
___________________________________________________________________
Added: svn:eol-style
## -0,0 +1 ##
+native
\ No newline at end of property
Added: svn:keywords
## -0,0 +1 ##
+MidnightBSD=%H
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+text/plain
\ No newline at end of property
Added: trunk/sys/mips/rmi/bus_space_rmi_pci.c
===================================================================
--- trunk/sys/mips/rmi/bus_space_rmi_pci.c (rev 0)
+++ trunk/sys/mips/rmi/bus_space_rmi_pci.c 2018-05-26 21:55:02 UTC (rev 9987)
@@ -0,0 +1,762 @@
+/* $MidnightBSD$ */
+/*-
+ * Copyright (c) 2009 RMI Corporation
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ * $FreeBSD: stable/10/sys/mips/rmi/bus_space_rmi_pci.c 204175 2010-02-21 17:27:20Z rrs $
+ */
+#include <sys/cdefs.h>
+__FBSDID("$FreeBSD: stable/10/sys/mips/rmi/bus_space_rmi_pci.c 204175 2010-02-21 17:27:20Z rrs $");
+
+#include <sys/param.h>
+#include <sys/systm.h>
+#include <sys/bus.h>
+#include <sys/kernel.h>
+#include <sys/endian.h>
+#include <sys/malloc.h>
+#include <sys/ktr.h>
+
+#include <vm/vm.h>
+#include <vm/pmap.h>
+#include <vm/vm_kern.h>
+#include <vm/vm_extern.h>
+
+#include <machine/bus.h>
+#include <machine/cache.h>
+
+static int
+rmi_pci_bus_space_map(void *t, bus_addr_t addr,
+ bus_size_t size, int flags,
+ bus_space_handle_t * bshp);
+
+static void
+rmi_pci_bus_space_unmap(void *t, bus_space_handle_t bsh,
+ bus_size_t size);
+
+static int
+rmi_pci_bus_space_subregion(void *t,
+ bus_space_handle_t bsh,
+ bus_size_t offset, bus_size_t size,
+ bus_space_handle_t * nbshp);
+
+static u_int8_t
+rmi_pci_bus_space_read_1(void *t,
+ bus_space_handle_t handle,
+ bus_size_t offset);
+
+static u_int16_t
+rmi_pci_bus_space_read_2(void *t,
+ bus_space_handle_t handle,
+ bus_size_t offset);
+
+static u_int32_t
+rmi_pci_bus_space_read_4(void *t,
+ bus_space_handle_t handle,
+ bus_size_t offset);
+
+static void
+rmi_pci_bus_space_read_multi_1(void *t,
+ bus_space_handle_t handle,
+ bus_size_t offset, u_int8_t * addr,
+ size_t count);
+
+static void
+rmi_pci_bus_space_read_multi_2(void *t,
+ bus_space_handle_t handle,
+ bus_size_t offset, u_int16_t * addr,
+ size_t count);
+
+static void
+rmi_pci_bus_space_read_multi_4(void *t,
+ bus_space_handle_t handle,
+ bus_size_t offset, u_int32_t * addr,
+ size_t count);
+
+static void
+rmi_pci_bus_space_read_region_1(void *t,
+ bus_space_handle_t bsh,
+ bus_size_t offset, u_int8_t * addr,
+ size_t count);
+
+static void
+rmi_pci_bus_space_read_region_2(void *t,
+ bus_space_handle_t bsh,
+ bus_size_t offset, u_int16_t * addr,
+ size_t count);
+
+static void
+rmi_pci_bus_space_read_region_4(void *t,
+ bus_space_handle_t bsh,
+ bus_size_t offset, u_int32_t * addr,
+ size_t count);
+
+static void
+rmi_pci_bus_space_write_1(void *t,
+ bus_space_handle_t handle,
+ bus_size_t offset, u_int8_t value);
+
+static void
+rmi_pci_bus_space_write_2(void *t,
+ bus_space_handle_t handle,
+ bus_size_t offset, u_int16_t value);
+
+static void
+rmi_pci_bus_space_write_4(void *t,
+ bus_space_handle_t handle,
+ bus_size_t offset, u_int32_t value);
+
+static void
+rmi_pci_bus_space_write_multi_1(void *t,
+ bus_space_handle_t handle,
+ bus_size_t offset,
+ const u_int8_t * addr,
+ size_t count);
+
+static void
+rmi_pci_bus_space_write_multi_2(void *t,
+ bus_space_handle_t handle,
+ bus_size_t offset,
+ const u_int16_t * addr,
+ size_t count);
+
+static void
+rmi_pci_bus_space_write_multi_4(void *t,
+ bus_space_handle_t handle,
+ bus_size_t offset,
+ const u_int32_t * addr,
+ size_t count);
+
+static void
+rmi_pci_bus_space_write_region_2(void *t,
+ bus_space_handle_t bsh,
+ bus_size_t offset,
+ const u_int16_t * addr,
+ size_t count);
+
+static void
+rmi_pci_bus_space_write_region_4(void *t,
+ bus_space_handle_t bsh,
+ bus_size_t offset,
+ const u_int32_t * addr,
+ size_t count);
+
+
+static void
+rmi_pci_bus_space_set_region_2(void *t,
+ bus_space_handle_t bsh,
+ bus_size_t offset, u_int16_t value,
+ size_t count);
+static void
+rmi_pci_bus_space_set_region_4(void *t,
+ bus_space_handle_t bsh,
+ bus_size_t offset, u_int32_t value,
+ size_t count);
+
+static void
+rmi_pci_bus_space_barrier(void *tag __unused, bus_space_handle_t bsh __unused,
+ bus_size_t offset __unused, bus_size_t len __unused, int flags);
+
+static void
+rmi_pci_bus_space_copy_region_2(void *t,
+ bus_space_handle_t bsh1,
+ bus_size_t off1,
+ bus_space_handle_t bsh2,
+ bus_size_t off2, size_t count);
+
+u_int8_t
+rmi_pci_bus_space_read_stream_1(void *t, bus_space_handle_t handle,
+ bus_size_t offset);
+
+static u_int16_t
+rmi_pci_bus_space_read_stream_2(void *t, bus_space_handle_t handle,
+ bus_size_t offset);
+
+static u_int32_t
+rmi_pci_bus_space_read_stream_4(void *t, bus_space_handle_t handle,
+ bus_size_t offset);
+static void
+rmi_pci_bus_space_read_multi_stream_1(void *t,
+ bus_space_handle_t handle,
+ bus_size_t offset, u_int8_t * addr,
+ size_t count);
+
+static void
+rmi_pci_bus_space_read_multi_stream_2(void *t,
+ bus_space_handle_t handle,
+ bus_size_t offset, u_int16_t * addr,
+ size_t count);
+
+static void
+rmi_pci_bus_space_read_multi_stream_4(void *t,
+ bus_space_handle_t handle,
+ bus_size_t offset, u_int32_t * addr,
+ size_t count);
+
+void
+rmi_pci_bus_space_write_stream_1(void *t, bus_space_handle_t bsh,
+ bus_size_t offset, u_int8_t value);
+static void
+rmi_pci_bus_space_write_stream_2(void *t, bus_space_handle_t handle,
+ bus_size_t offset, u_int16_t value);
+
+static void
+rmi_pci_bus_space_write_stream_4(void *t, bus_space_handle_t handle,
+ bus_size_t offset, u_int32_t value);
+
+static void
+rmi_pci_bus_space_write_multi_stream_1(void *t,
+ bus_space_handle_t handle,
+ bus_size_t offset,
+ const u_int8_t * addr,
+ size_t count);
+static void
+rmi_pci_bus_space_write_multi_stream_2(void *t,
+ bus_space_handle_t handle,
+ bus_size_t offset,
+ const u_int16_t * addr,
+ size_t count);
+
+static void
+rmi_pci_bus_space_write_multi_stream_4(void *t,
+ bus_space_handle_t handle,
+ bus_size_t offset,
+ const u_int32_t * addr,
+ size_t count);
+
+#define TODO() printf("XLR memory bus space function '%s' unimplemented\n", __func__)
+
+static struct bus_space local_rmi_pci_bus_space = {
+ /* cookie */
+ (void *)0,
+
+ /* mapping/unmapping */
+ rmi_pci_bus_space_map,
+ rmi_pci_bus_space_unmap,
+ rmi_pci_bus_space_subregion,
+
+ /* allocation/deallocation */
+ NULL,
+ NULL,
+
+ /* barrier */
+ rmi_pci_bus_space_barrier,
+
+ /* read (single) */
+ rmi_pci_bus_space_read_1,
+ rmi_pci_bus_space_read_2,
+ rmi_pci_bus_space_read_4,
+ NULL,
+
+ /* read multiple */
+ rmi_pci_bus_space_read_multi_1,
+ rmi_pci_bus_space_read_multi_2,
+ rmi_pci_bus_space_read_multi_4,
+ NULL,
+
+ /* read region */
+ rmi_pci_bus_space_read_region_1,
+ rmi_pci_bus_space_read_region_2,
+ rmi_pci_bus_space_read_region_4,
+ NULL,
+
+ /* write (single) */
+ rmi_pci_bus_space_write_1,
+ rmi_pci_bus_space_write_2,
+ rmi_pci_bus_space_write_4,
+ NULL,
+
+ /* write multiple */
+ rmi_pci_bus_space_write_multi_1,
+ rmi_pci_bus_space_write_multi_2,
+ rmi_pci_bus_space_write_multi_4,
+ NULL,
+
+ /* write region */
+ NULL,
+ rmi_pci_bus_space_write_region_2,
+ rmi_pci_bus_space_write_region_4,
+ NULL,
+
+ /* set multiple */
+ NULL,
+ NULL,
+ NULL,
+ NULL,
+
+ /* set region */
+ NULL,
+ rmi_pci_bus_space_set_region_2,
+ rmi_pci_bus_space_set_region_4,
+ NULL,
+
+ /* copy */
+ NULL,
+ rmi_pci_bus_space_copy_region_2,
+ NULL,
+ NULL,
+
+ /* read (single) stream */
+ rmi_pci_bus_space_read_stream_1,
+ rmi_pci_bus_space_read_stream_2,
+ rmi_pci_bus_space_read_stream_4,
+ NULL,
+
+ /* read multiple stream */
+ rmi_pci_bus_space_read_multi_stream_1,
+ rmi_pci_bus_space_read_multi_stream_2,
+ rmi_pci_bus_space_read_multi_stream_4,
+ NULL,
+
+ /* read region stream */
+ rmi_pci_bus_space_read_region_1,
+ rmi_pci_bus_space_read_region_2,
+ rmi_pci_bus_space_read_region_4,
+ NULL,
+
+ /* write (single) stream */
+ rmi_pci_bus_space_write_stream_1,
+ rmi_pci_bus_space_write_stream_2,
+ rmi_pci_bus_space_write_stream_4,
+ NULL,
+
+ /* write multiple stream */
+ rmi_pci_bus_space_write_multi_stream_1,
+ rmi_pci_bus_space_write_multi_stream_2,
+ rmi_pci_bus_space_write_multi_stream_4,
+ NULL,
+
+ /* write region stream */
+ NULL,
+ rmi_pci_bus_space_write_region_2,
+ rmi_pci_bus_space_write_region_4,
+ NULL,
+};
+
+/* generic bus_space tag */
+bus_space_tag_t rmi_pci_bus_space = &local_rmi_pci_bus_space;
+
+/*
+ * Map a region of device bus space into CPU virtual address space.
+ */
+static int
+rmi_pci_bus_space_map(void *t __unused, bus_addr_t addr,
+ bus_size_t size __unused, int flags __unused,
+ bus_space_handle_t * bshp)
+{
+ *bshp = addr;
+ return (0);
+}
+
+/*
+ * Unmap a region of device bus space.
+ */
+static void
+rmi_pci_bus_space_unmap(void *t __unused, bus_space_handle_t bsh __unused,
+ bus_size_t size __unused)
+{
+}
+
+/*
+ * Get a new handle for a subregion of an already-mapped area of bus space.
+ */
+
+static int
+rmi_pci_bus_space_subregion(void *t __unused, bus_space_handle_t bsh,
+ bus_size_t offset, bus_size_t size __unused,
+ bus_space_handle_t * nbshp)
+{
+ *nbshp = bsh + offset;
+ return (0);
+}
+
+/*
+ * Read a 1, 2, 4, or 8 byte quantity from bus space
+ * described by tag/handle/offset.
+ */
+
+static u_int8_t
+rmi_pci_bus_space_read_1(void *tag, bus_space_handle_t handle,
+ bus_size_t offset)
+{
+ return (u_int8_t) (*(volatile u_int8_t *)(handle + offset));
+}
+
+static u_int16_t
+rmi_pci_bus_space_read_2(void *tag, bus_space_handle_t handle,
+ bus_size_t offset)
+{
+ return bswap16((u_int16_t) (*(volatile u_int16_t *)(handle + offset)));
+}
+
+static u_int32_t
+rmi_pci_bus_space_read_4(void *tag, bus_space_handle_t handle,
+ bus_size_t offset)
+{
+ return bswap32((*(volatile u_int32_t *)(handle + offset)));
+}
+
+
+/*
+ * Read `count' 1, 2, 4, or 8 byte quantities from bus space
+ * described by tag/handle/offset and copy into buffer provided.
+ */
+static void
+rmi_pci_bus_space_read_multi_1(void *tag, bus_space_handle_t handle,
+ bus_size_t offset, u_int8_t * addr, size_t count)
+{
+ while (count--) {
+ *addr = (*(volatile u_int8_t *)(handle + offset));
+ addr++;
+ }
+}
+
+static void
+rmi_pci_bus_space_read_multi_2(void *tag, bus_space_handle_t handle,
+ bus_size_t offset, u_int16_t * addr, size_t count)
+{
+
+ while (count--) {
+ *addr = *(volatile u_int16_t *)(handle + offset);
+ *addr = bswap16(*addr);
+ addr++;
+ }
+}
+
+static void
+rmi_pci_bus_space_read_multi_4(void *tag, bus_space_handle_t handle,
+ bus_size_t offset, u_int32_t * addr, size_t count)
+{
+
+ while (count--) {
+ *addr = *(volatile u_int32_t *)(handle + offset);
+ *addr = bswap32(*addr);
+ addr++;
+ }
+}
+
+/*
+ * Write the 1, 2, 4, or 8 byte value `value' to bus space
+ * described by tag/handle/offset.
+ */
+
+static void
+rmi_pci_bus_space_write_1(void *tag, bus_space_handle_t handle,
+ bus_size_t offset, u_int8_t value)
+{
+ mips_sync();
+ *(volatile u_int8_t *)(handle + offset) = value;
+}
+
+static void
+rmi_pci_bus_space_write_2(void *tag, bus_space_handle_t handle,
+ bus_size_t offset, u_int16_t value)
+{
+ mips_sync();
+ *(volatile u_int16_t *)(handle + offset) = bswap16(value);
+}
+
+
+static void
+rmi_pci_bus_space_write_4(void *tag, bus_space_handle_t handle,
+ bus_size_t offset, u_int32_t value)
+{
+ mips_sync();
+ *(volatile u_int32_t *)(handle + offset) = bswap32(value);
+}
+
+/*
+ * Write `count' 1, 2, 4, or 8 byte quantities from the buffer
+ * provided to bus space described by tag/handle/offset.
+ */
+
+
+static void
+rmi_pci_bus_space_write_multi_1(void *tag, bus_space_handle_t handle,
+ bus_size_t offset, const u_int8_t * addr, size_t count)
+{
+ mips_sync();
+ while (count--) {
+ (*(volatile u_int8_t *)(handle + offset)) = *addr;
+ addr++;
+ }
+}
+
+static void
+rmi_pci_bus_space_write_multi_2(void *tag, bus_space_handle_t handle,
+ bus_size_t offset, const u_int16_t * addr, size_t count)
+{
+ mips_sync();
+ while (count--) {
+ (*(volatile u_int16_t *)(handle + offset)) = bswap16(*addr);
+ addr++;
+ }
+}
+
+static void
+rmi_pci_bus_space_write_multi_4(void *tag, bus_space_handle_t handle,
+ bus_size_t offset, const u_int32_t * addr, size_t count)
+{
+ mips_sync();
+ while (count--) {
+ (*(volatile u_int32_t *)(handle + offset)) = bswap32(*addr);
+ addr++;
+ }
+}
+
+/*
+ * Write `count' 1, 2, 4, or 8 byte value `val' to bus space described
+ * by tag/handle starting at `offset'.
+ */
+
+static void
+rmi_pci_bus_space_set_region_2(void *t, bus_space_handle_t bsh,
+ bus_size_t offset, u_int16_t value, size_t count)
+{
+ bus_addr_t addr = bsh + offset;
+
+ for (; count != 0; count--, addr += 2)
+ (*(volatile u_int16_t *)(addr)) = value;
+}
+
+static void
+rmi_pci_bus_space_set_region_4(void *t, bus_space_handle_t bsh,
+ bus_size_t offset, u_int32_t value, size_t count)
+{
+ bus_addr_t addr = bsh + offset;
+
+ for (; count != 0; count--, addr += 4)
+ (*(volatile u_int32_t *)(addr)) = value;
+}
+
+
+/*
+ * Copy `count' 1, 2, 4, or 8 byte values from bus space starting
+ * at tag/bsh1/off1 to bus space starting at tag/bsh2/off2.
+ */
+static void
+rmi_pci_bus_space_copy_region_2(void *t, bus_space_handle_t bsh1,
+ bus_size_t off1, bus_space_handle_t bsh2,
+ bus_size_t off2, size_t count)
+{
+ TODO();
+}
+
+/*
+ * Read `count' 1, 2, 4, or 8 byte quantities from bus space
+ * described by tag/handle/offset and copy into buffer provided.
+ */
+
+u_int8_t
+rmi_pci_bus_space_read_stream_1(void *t, bus_space_handle_t handle,
+ bus_size_t offset)
+{
+
+ return *((volatile u_int8_t *)(handle + offset));
+}
+
+
+static u_int16_t
+rmi_pci_bus_space_read_stream_2(void *t, bus_space_handle_t handle,
+ bus_size_t offset)
+{
+ return *(volatile u_int16_t *)(handle + offset);
+}
+
+
+static u_int32_t
+rmi_pci_bus_space_read_stream_4(void *t, bus_space_handle_t handle,
+ bus_size_t offset)
+{
+ return (*(volatile u_int32_t *)(handle + offset));
+}
+
+
+static void
+rmi_pci_bus_space_read_multi_stream_1(void *tag, bus_space_handle_t handle,
+ bus_size_t offset, u_int8_t * addr, size_t count)
+{
+ while (count--) {
+ *addr = (*(volatile u_int8_t *)(handle + offset));
+ addr++;
+ }
+}
+
+static void
+rmi_pci_bus_space_read_multi_stream_2(void *tag, bus_space_handle_t handle,
+ bus_size_t offset, u_int16_t * addr, size_t count)
+{
+ while (count--) {
+ *addr = (*(volatile u_int16_t *)(handle + offset));
+ addr++;
+ }
+}
+
+static void
+rmi_pci_bus_space_read_multi_stream_4(void *tag, bus_space_handle_t handle,
+ bus_size_t offset, u_int32_t * addr, size_t count)
+{
+ while (count--) {
+ *addr = (*(volatile u_int32_t *)(handle + offset));
+ addr++;
+ }
+}
+
+
+
+/*
+ * Read `count' 1, 2, 4, or 8 byte quantities from bus space
+ * described by tag/handle and starting at `offset' and copy into
+ * buffer provided.
+ */
+void
+rmi_pci_bus_space_read_region_1(void *t, bus_space_handle_t bsh,
+ bus_size_t offset, u_int8_t * addr, size_t count)
+{
+ bus_addr_t baddr = bsh + offset;
+
+ while (count--) {
+ *addr++ = (*(volatile u_int8_t *)(baddr));
+ baddr += 1;
+ }
+}
+
+void
+rmi_pci_bus_space_read_region_2(void *t, bus_space_handle_t bsh,
+ bus_size_t offset, u_int16_t * addr, size_t count)
+{
+ bus_addr_t baddr = bsh + offset;
+
+ while (count--) {
+ *addr++ = (*(volatile u_int16_t *)(baddr));
+ baddr += 2;
+ }
+}
+
+void
+rmi_pci_bus_space_read_region_4(void *t, bus_space_handle_t bsh,
+ bus_size_t offset, u_int32_t * addr, size_t count)
+{
+ bus_addr_t baddr = bsh + offset;
+
+ while (count--) {
+ *addr++ = (*(volatile u_int32_t *)(baddr));
+ baddr += 4;
+ }
+}
+
+
+void
+rmi_pci_bus_space_write_stream_1(void *t, bus_space_handle_t handle,
+ bus_size_t offset, u_int8_t value)
+{
+ mips_sync();
+ *(volatile u_int8_t *)(handle + offset) = value;
+}
+
+static void
+rmi_pci_bus_space_write_stream_2(void *t, bus_space_handle_t handle,
+ bus_size_t offset, u_int16_t value)
+{
+ mips_sync();
+ *(volatile u_int16_t *)(handle + offset) = value;
+}
+
+
+static void
+rmi_pci_bus_space_write_stream_4(void *t, bus_space_handle_t handle,
+ bus_size_t offset, u_int32_t value)
+{
+ mips_sync();
+ *(volatile u_int32_t *)(handle + offset) = value;
+}
+
+
+static void
+rmi_pci_bus_space_write_multi_stream_1(void *tag, bus_space_handle_t handle,
+ bus_size_t offset, const u_int8_t * addr, size_t count)
+{
+ mips_sync();
+ while (count--) {
+ (*(volatile u_int8_t *)(handle + offset)) = *addr;
+ addr++;
+ }
+}
+
+static void
+rmi_pci_bus_space_write_multi_stream_2(void *tag, bus_space_handle_t handle,
+ bus_size_t offset, const u_int16_t * addr, size_t count)
+{
+ mips_sync();
+ while (count--) {
+ (*(volatile u_int16_t *)(handle + offset)) = *addr;
+ addr++;
+ }
+}
+
+static void
+rmi_pci_bus_space_write_multi_stream_4(void *tag, bus_space_handle_t handle,
+ bus_size_t offset, const u_int32_t * addr, size_t count)
+{
+ mips_sync();
+ while (count--) {
+ (*(volatile u_int32_t *)(handle + offset)) = *addr;
+ addr++;
+ }
+}
+
+void
+rmi_pci_bus_space_write_region_2(void *t,
+ bus_space_handle_t bsh,
+ bus_size_t offset,
+ const u_int16_t * addr,
+ size_t count)
+{
+ bus_addr_t baddr = (bus_addr_t) bsh + offset;
+
+ while (count--) {
+ (*(volatile u_int16_t *)(baddr)) = *addr;
+ addr++;
+ baddr += 2;
+ }
+}
+
+void
+rmi_pci_bus_space_write_region_4(void *t, bus_space_handle_t bsh,
+ bus_size_t offset, const u_int32_t * addr, size_t count)
+{
+ bus_addr_t baddr = bsh + offset;
+
+ while (count--) {
+ (*(volatile u_int32_t *)(baddr)) = *addr;
+ addr++;
+ baddr += 4;
+ }
+}
+
+static void
+rmi_pci_bus_space_barrier(void *tag __unused, bus_space_handle_t bsh __unused,
+ bus_size_t offset __unused, bus_size_t len __unused, int flags)
+{
+
+}
Property changes on: trunk/sys/mips/rmi/bus_space_rmi_pci.c
___________________________________________________________________
Added: svn:eol-style
## -0,0 +1 ##
+native
\ No newline at end of property
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## -0,0 +1 ##
+MidnightBSD=%H
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## -0,0 +1 ##
+text/plain
\ No newline at end of property
Added: trunk/sys/mips/rmi/dev/iic/at24co2n.c
===================================================================
--- trunk/sys/mips/rmi/dev/iic/at24co2n.c (rev 0)
+++ trunk/sys/mips/rmi/dev/iic/at24co2n.c 2018-05-26 21:55:02 UTC (rev 9987)
@@ -0,0 +1,141 @@
+/* $MidnightBSD$ */
+/*-
+ * Copyright (c) 2003-2009 RMI Corporation
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * 3. Neither the name of RMI Corporation, nor the names of its contributors,
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ * RMI_BSD */
+
+#include <sys/cdefs.h>
+__FBSDID("$FreeBSD: stable/10/sys/mips/rmi/dev/iic/at24co2n.c 216410 2010-12-13 17:53:38Z jchandra $");
+/*
+ * reading eeprom for the mac address .
+ */
+#include <sys/param.h>
+#include <sys/systm.h>
+#include <sys/kernel.h>
+#include <sys/lock.h>
+#include <sys/module.h>
+#include <sys/mutex.h>
+#include <sys/bus.h>
+#include <sys/resource.h>
+#include <sys/rman.h>
+#include <sys/sysctl.h>
+
+#include <machine/bus.h>
+#include <machine/cpu.h>
+#include <machine/cpufunc.h>
+#include <machine/frame.h>
+#include <machine/resource.h>
+
+#include <dev/iicbus/iiconf.h>
+#include <dev/iicbus/iicbus.h>
+
+#include "iicbus_if.h"
+
+#define AT24CO_EEPROM_ETH_MACADDR 0x20
+
+struct at24co2n_softc {
+ uint32_t sc_addr;
+ device_t sc_dev;
+ uint8_t sc_mac_addr[6];
+};
+
+static void at24co2n_read_mac(struct at24co2n_softc *);
+
+static int
+at24co2n_probe(device_t dev)
+{
+ device_set_desc(dev, "AT24Co2N-10SE-2.7 EEPROM for mac address");
+ return (0);
+}
+
+static int
+at24co2n_mac_sysctl(SYSCTL_HANDLER_ARGS)
+{
+ struct at24co2n_softc *sc = arg1;
+ char buf[24];
+ int len;
+ uint8_t *p;
+
+ at24co2n_read_mac(sc);
+ p = sc->sc_mac_addr;
+ len = snprintf(buf, sizeof(buf), "%02x:%02x:%02x:%02x:%02x:%02x",
+ p[0], p[1], p[2], p[3], p[4], p[5]);
+ return SYSCTL_OUT(req, buf, len);
+}
+
+
+static int
+at24co2n_attach(device_t dev)
+{
+ struct at24co2n_softc *sc = device_get_softc(dev);
+ struct sysctl_ctx_list *ctx = device_get_sysctl_ctx(dev);
+ struct sysctl_oid *tree = device_get_sysctl_tree(dev);
+
+ if(sc == NULL) {
+ printf("at24co2n_attach device_get_softc failed\n");
+ return (0);
+ }
+ sc->sc_dev = dev;
+ sc->sc_addr = iicbus_get_addr(dev);
+
+ SYSCTL_ADD_PROC(ctx, SYSCTL_CHILDREN(tree), OID_AUTO,
+ "eeprom-mac", CTLTYPE_STRING | CTLFLAG_RD, sc, 0,
+ at24co2n_mac_sysctl, "A", "mac address");
+
+ return (0);
+}
+
+static void
+at24co2n_read_mac(struct at24co2n_softc *sc)
+{
+ uint8_t addr = AT24CO_EEPROM_ETH_MACADDR;
+ struct iic_msg msgs[2] = {
+ { sc->sc_addr, IIC_M_WR, 1, &addr },
+ { sc->sc_addr, IIC_M_RD, 6, sc->sc_mac_addr},
+ };
+
+ iicbus_transfer(sc->sc_dev, msgs, 2);
+}
+
+static device_method_t at24co2n_methods[] = {
+ DEVMETHOD(device_probe, at24co2n_probe),
+ DEVMETHOD(device_attach, at24co2n_attach),
+
+ {0, 0},
+};
+
+static driver_t at24co2n_driver = {
+ "at24co2n",
+ at24co2n_methods,
+ sizeof(struct at24co2n_softc),
+};
+static devclass_t at24co2n_devclass;
+
+DRIVER_MODULE(at24co2n, iicbus, at24co2n_driver, at24co2n_devclass, 0, 0);
+MODULE_VERSION(at24co2n, 1);
+MODULE_DEPEND(at24co2n, iicbus, 1, 1, 1);
Property changes on: trunk/sys/mips/rmi/dev/iic/at24co2n.c
___________________________________________________________________
Added: svn:eol-style
## -0,0 +1 ##
+native
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## -0,0 +1 ##
+MidnightBSD=%H
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## -0,0 +1 ##
+text/plain
\ No newline at end of property
Added: trunk/sys/mips/rmi/dev/iic/ds1374u.c
===================================================================
--- trunk/sys/mips/rmi/dev/iic/ds1374u.c (rev 0)
+++ trunk/sys/mips/rmi/dev/iic/ds1374u.c 2018-05-26 21:55:02 UTC (rev 9987)
@@ -0,0 +1,148 @@
+/* $MidnightBSD$ */
+/*-
+ * Copyright (c) 2003-2009 RMI Corporation
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * 3. Neither the name of RMI Corporation, nor the names of its contributors,
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ * RMI_BSD */
+
+#include <sys/cdefs.h>
+__FBSDID("$FreeBSD: stable/10/sys/mips/rmi/dev/iic/ds1374u.c 216410 2010-12-13 17:53:38Z jchandra $");
+/*
+ * RTC chip sitting on the I2C bus.
+ */
+#include <sys/param.h>
+#include <sys/systm.h>
+#include <sys/kernel.h>
+#include <sys/module.h>
+#include <sys/bus.h>
+#include <sys/clock.h>
+#include <sys/time.h>
+#include <sys/resource.h>
+#include <sys/rman.h>
+
+#include <mips/include/bus.h>
+#include <mips/include/cpu.h>
+#include <mips/include/cpufunc.h>
+#include <mips/include/frame.h>
+#include <mips/include/resource.h>
+
+#include <dev/iicbus/iiconf.h>
+#include <dev/iicbus/iicbus.h>
+
+#include "iicbus_if.h"
+#include "clock_if.h"
+
+#define DS1374_RTC_COUNTER 0 /* counter (bytes 0-3) */
+
+struct ds1374u_softc {
+ uint32_t sc_addr;
+ device_t sc_dev;
+};
+
+static int
+ds1374u_probe(device_t dev)
+{
+ device_set_desc(dev, "DS1374U-33 RTC");
+ return (0);
+}
+
+static int
+ds1374u_attach(device_t dev)
+{
+ struct ds1374u_softc *sc = device_get_softc(dev);
+
+ if(sc==NULL) {
+ printf("ds1374u_attach device_get_softc failed\n");
+ return (0);
+ }
+ sc->sc_dev = dev;
+ sc->sc_addr = iicbus_get_addr(dev);
+
+ clock_register(dev, 1000);
+ return (0);
+}
+
+static int
+ds1374u_settime(device_t dev, struct timespec *ts)
+{
+ /* NB: register pointer precedes actual data */
+ uint8_t data[5] = { DS1374_RTC_COUNTER };
+ struct ds1374u_softc *sc = device_get_softc(dev);
+ struct iic_msg msgs[1] = {
+ { sc->sc_addr, IIC_M_WR, 5, data },
+ };
+
+ data[1] = (ts->tv_sec >> 0) & 0xff;
+ data[2] = (ts->tv_sec >> 8) & 0xff;
+ data[3] = (ts->tv_sec >> 16) & 0xff;
+ data[4] = (ts->tv_sec >> 24) & 0xff;
+
+ return iicbus_transfer(dev, msgs, 1);
+}
+
+static int
+ds1374u_gettime(device_t dev, struct timespec *ts)
+{
+ struct ds1374u_softc *sc = device_get_softc(dev);
+ uint8_t addr[1] = { DS1374_RTC_COUNTER };
+ uint8_t secs[4];
+ struct iic_msg msgs[2] = {
+ { sc->sc_addr, IIC_M_WR, 1, addr },
+ { sc->sc_addr, IIC_M_RD, 4, secs },
+ };
+ int error;
+
+ error = iicbus_transfer(dev, msgs, 2);
+ if (error == 0) {
+ /* counter has seconds since epoch */
+ ts->tv_sec = (secs[3] << 24) | (secs[2] << 16)
+ | (secs[1] << 8) | (secs[0] << 0);
+ ts->tv_nsec = 0;
+ }
+ return error;
+}
+
+static device_method_t ds1374u_methods[] = {
+ DEVMETHOD(device_probe, ds1374u_probe),
+ DEVMETHOD(device_attach, ds1374u_attach),
+
+ DEVMETHOD(clock_gettime, ds1374u_gettime),
+ DEVMETHOD(clock_settime, ds1374u_settime),
+
+ {0, 0},
+};
+
+static driver_t ds1374u_driver = {
+ "ds1374u",
+ ds1374u_methods,
+ sizeof(struct ds1374u_softc),
+};
+static devclass_t ds1374u_devclass;
+
+DRIVER_MODULE(ds1374u, iicbus, ds1374u_driver, ds1374u_devclass, 0, 0);
+MODULE_VERSION(ds1374u, 1);
+MODULE_DEPEND(ds1374u, iicbus, 1, 1, 1);
Property changes on: trunk/sys/mips/rmi/dev/iic/ds1374u.c
___________________________________________________________________
Added: svn:eol-style
## -0,0 +1 ##
+native
\ No newline at end of property
Added: svn:keywords
## -0,0 +1 ##
+MidnightBSD=%H
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Added: svn:mime-type
## -0,0 +1 ##
+text/plain
\ No newline at end of property
Added: trunk/sys/mips/rmi/dev/iic/max6657.c
===================================================================
--- trunk/sys/mips/rmi/dev/iic/max6657.c (rev 0)
+++ trunk/sys/mips/rmi/dev/iic/max6657.c 2018-05-26 21:55:02 UTC (rev 9987)
@@ -0,0 +1,159 @@
+/* $MidnightBSD$ */
+/*-
+ * Copyright (c) 2003-2009 RMI Corporation
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * 3. Neither the name of RMI Corporation, nor the names of its contributors,
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ * RMI_BSD */
+
+#include <sys/cdefs.h>
+__FBSDID("$FreeBSD: stable/10/sys/mips/rmi/dev/iic/max6657.c 216410 2010-12-13 17:53:38Z jchandra $");
+/*
+ * temperature sensor chip sitting on the I2C bus.
+ */
+#include <sys/param.h>
+#include <sys/systm.h>
+#include <sys/kernel.h>
+#include <sys/lock.h>
+#include <sys/module.h>
+#include <sys/mutex.h>
+#include <sys/bus.h>
+#include <sys/resource.h>
+#include <sys/rman.h>
+#include <sys/sysctl.h>
+
+#include <machine/bus.h>
+#include <machine/cpu.h>
+#include <machine/cpufunc.h>
+#include <machine/frame.h>
+#include <machine/resource.h>
+
+#include <dev/iicbus/iiconf.h>
+#include <dev/iicbus/iicbus.h>
+
+#include <mips/rmi/board.h>
+#include <mips/rmi/rmi_boot_info.h>
+#include "iicbus_if.h"
+
+#define MAX6657_EXT_TEMP 1
+
+struct max6657_softc {
+ uint32_t sc_addr;
+ device_t sc_dev;
+ int sc_curtemp;
+ int sc_lastupdate; /* in ticks */
+};
+
+static void max6657_update(struct max6657_softc *);
+static int max6657_read(device_t dev, uint32_t addr, int reg) ;
+
+static int
+max6657_probe(device_t dev)
+{
+ device_set_desc(dev, "MAX6657MSA Temperature Sensor");
+ return (0);
+}
+
+static int
+max6657_sysctl_temp(SYSCTL_HANDLER_ARGS)
+{
+ struct max6657_softc *sc = arg1;
+ int temp;
+
+ max6657_update(sc);
+ temp = sc->sc_curtemp ;
+ return sysctl_handle_int(oidp, &temp, 0, req);
+}
+
+static int
+max6657_attach(device_t dev)
+{
+ struct max6657_softc *sc = device_get_softc(dev);
+ struct sysctl_ctx_list *ctx = device_get_sysctl_ctx(dev);
+ struct sysctl_oid *tree = device_get_sysctl_tree(dev);
+
+ if(sc==NULL) {
+ printf("max6657_attach device_get_softc failed\n");
+ return (0);
+ }
+ sc->sc_dev = dev;
+ sc->sc_addr = iicbus_get_addr(dev);
+
+ SYSCTL_ADD_PROC(ctx, SYSCTL_CHILDREN(tree), OID_AUTO,
+ "temp", CTLTYPE_INT | CTLFLAG_RD, sc, 0,
+ max6657_sysctl_temp, "I", "operating temperature");
+
+ device_printf(dev, "Chip temperature {%d} Degree Celsius\n",
+ max6657_read(sc->sc_dev, sc->sc_addr, MAX6657_EXT_TEMP));
+
+ return (0);
+}
+
+static int
+max6657_read(device_t dev, uint32_t slave_addr, int reg)
+{
+ uint8_t addr = reg;
+ uint8_t data[1];
+ struct iic_msg msgs[2] = {
+ { slave_addr, IIC_M_WR, 1, &addr },
+ { slave_addr, IIC_M_RD, 1, data },
+ };
+
+ return iicbus_transfer(dev, msgs, 2) != 0 ? -1 : data[0];
+}
+
+
+static void
+max6657_update(struct max6657_softc *sc)
+{
+ int v;
+
+ /* NB: no point in updating any faster than the chip */
+ if (ticks - sc->sc_lastupdate > hz) {
+ v = max6657_read(sc->sc_dev, sc->sc_addr, MAX6657_EXT_TEMP);
+ if (v >= 0)
+ sc->sc_curtemp = v;
+ sc->sc_lastupdate = ticks;
+ }
+}
+
+static device_method_t max6657_methods[] = {
+ DEVMETHOD(device_probe, max6657_probe),
+ DEVMETHOD(device_attach, max6657_attach),
+
+ {0, 0},
+};
+
+static driver_t max6657_driver = {
+ "max6657",
+ max6657_methods,
+ sizeof(struct max6657_softc),
+};
+static devclass_t max6657_devclass;
+
+DRIVER_MODULE(max6657, iicbus, max6657_driver, max6657_devclass, 0, 0);
+MODULE_VERSION(max6657, 1);
+MODULE_DEPEND(max6657, iicbus, 1, 1, 1);
Property changes on: trunk/sys/mips/rmi/dev/iic/max6657.c
___________________________________________________________________
Added: svn:eol-style
## -0,0 +1 ##
+native
\ No newline at end of property
Added: svn:keywords
## -0,0 +1 ##
+MidnightBSD=%H
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+text/plain
\ No newline at end of property
Added: trunk/sys/mips/rmi/dev/nlge/if_nlge.c
===================================================================
--- trunk/sys/mips/rmi/dev/nlge/if_nlge.c (rev 0)
+++ trunk/sys/mips/rmi/dev/nlge/if_nlge.c 2018-05-26 21:55:02 UTC (rev 9987)
@@ -0,0 +1,2562 @@
+/* $MidnightBSD$ */
+/*-
+ * Copyright (c) 2003-2009 RMI Corporation
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * 3. Neither the name of RMI Corporation, nor the names of its contributors,
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ * RMI_BSD */
+
+/*
+ * The XLR device supports upto four 10/100/1000 Ethernet MACs and upto
+ * two 10G Ethernet MACs (of XGMII). Alternatively, each 10G port can used
+ * as a SPI-4 interface, with 8 ports per such interface. The MACs are
+ * encapsulated in another hardware block referred to as network accelerator,
+ * such that there are three instances of these in a XLR. One of them controls
+ * the four 1G RGMII ports while one each of the others controls an XGMII port.
+ * Enabling MACs requires configuring the corresponding network accelerator
+ * and the individual port.
+ * The XLS device supports upto 8 10/100/1000 Ethernet MACs or max 2 10G
+ * Ethernet MACs. The 1G MACs are of SGMII and 10G MACs are of XAUI
+ * interface. These ports are part of two network accelerators.
+ * The nlge driver configures and initializes non-SPI4 Ethernet ports in the
+ * XLR/XLS devices and enables data transfer on them.
+ */
+
+#include <sys/cdefs.h>
+__FBSDID("$FreeBSD: stable/10/sys/mips/rmi/dev/nlge/if_nlge.c 243882 2012-12-05 08:04:20Z glebius $");
+
+#ifdef HAVE_KERNEL_OPTION_HEADERS
+#include "opt_device_polling.h"
+#endif
+
+#include <sys/endian.h>
+#include <sys/systm.h>
+#include <sys/sockio.h>
+#include <sys/param.h>
+#include <sys/lock.h>
+#include <sys/mutex.h>
+#include <sys/proc.h>
+#include <sys/limits.h>
+#include <sys/bus.h>
+#include <sys/mbuf.h>
+#include <sys/malloc.h>
+#include <sys/kernel.h>
+#include <sys/module.h>
+#include <sys/socket.h>
+#define __RMAN_RESOURCE_VISIBLE
+#include <sys/rman.h>
+#include <sys/taskqueue.h>
+#include <sys/smp.h>
+#include <sys/sysctl.h>
+
+#include <net/if.h>
+#include <net/if_arp.h>
+#include <net/ethernet.h>
+#include <net/if_dl.h>
+#include <net/if_media.h>
+#include <net/bpf.h>
+#include <net/if_types.h>
+#include <net/if_vlan_var.h>
+
+#include <netinet/in_systm.h>
+#include <netinet/in.h>
+#include <netinet/ip.h>
+
+#include <vm/vm.h>
+#include <vm/pmap.h>
+#include <vm/uma.h>
+
+#include <machine/reg.h>
+#include <machine/cpu.h>
+#include <machine/mips_opcode.h>
+#include <machine/asm.h>
+#include <machine/cpuregs.h>
+#include <machine/param.h>
+#include <machine/intr_machdep.h>
+#include <machine/clock.h> /* for DELAY */
+#include <machine/bus.h>
+#include <machine/resource.h>
+
+#include <mips/rmi/interrupt.h>
+#include <mips/rmi/msgring.h>
+#include <mips/rmi/iomap.h>
+#include <mips/rmi/pic.h>
+#include <mips/rmi/board.h>
+#include <mips/rmi/rmi_mips_exts.h>
+#include <mips/rmi/rmi_boot_info.h>
+#include <mips/rmi/dev/xlr/atx_cpld.h>
+#include <mips/rmi/dev/xlr/xgmac_mdio.h>
+
+#include <dev/mii/mii.h>
+#include <dev/mii/miivar.h>
+#include "miidevs.h"
+#include <dev/mii/brgphyreg.h>
+#include "miibus_if.h"
+
+#include <mips/rmi/dev/nlge/if_nlge.h>
+
+MODULE_DEPEND(nlna, nlge, 1, 1, 1);
+MODULE_DEPEND(nlge, ether, 1, 1, 1);
+MODULE_DEPEND(nlge, miibus, 1, 1, 1);
+
+/* Network accelarator entry points */
+static int nlna_probe(device_t);
+static int nlna_attach(device_t);
+static int nlna_detach(device_t);
+static int nlna_suspend(device_t);
+static int nlna_resume(device_t);
+static int nlna_shutdown(device_t);
+
+/* GMAC port entry points */
+static int nlge_probe(device_t);
+static int nlge_attach(device_t);
+static int nlge_detach(device_t);
+static int nlge_suspend(device_t);
+static int nlge_resume(device_t);
+static void nlge_init(void *);
+static int nlge_ioctl(struct ifnet *, u_long, caddr_t);
+static int nlge_tx(struct ifnet *ifp, struct mbuf *m);
+static void nlge_rx(struct nlge_softc *sc, vm_paddr_t paddr, int len);
+
+static int nlge_mii_write(struct device *, int, int, int);
+static int nlge_mii_read(struct device *, int, int);
+static void nlge_mac_mii_statchg(device_t);
+static int nlge_mediachange(struct ifnet *ifp);
+static void nlge_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr);
+
+/* Other internal/helper functions */
+static void *get_buf(void);
+
+static void nlna_add_to_port_set(struct nlge_port_set *pset,
+ struct nlge_softc *sc);
+static void nlna_config_pde(struct nlna_softc *);
+static void nlna_config_parser(struct nlna_softc *);
+static void nlna_config_classifier(struct nlna_softc *);
+static void nlna_config_fifo_spill_area(struct nlna_softc *sc);
+static void nlna_config_translate_table(struct nlna_softc *sc);
+static void nlna_config_common(struct nlna_softc *);
+static void nlna_disable_ports(struct nlna_softc *sc);
+static void nlna_enable_intr(struct nlna_softc *sc);
+static void nlna_disable_intr(struct nlna_softc *sc);
+static void nlna_enable_ports(struct nlna_softc *sc);
+static void nlna_get_all_softc(device_t iodi_dev,
+ struct nlna_softc **sc_vec, uint32_t vec_sz);
+static void nlna_hw_init(struct nlna_softc *sc);
+static int nlna_is_last_active_na(struct nlna_softc *sc);
+static void nlna_media_specific_config(struct nlna_softc *sc);
+static void nlna_reset_ports(struct nlna_softc *sc,
+ struct xlr_gmac_block_t *blk);
+static struct nlna_softc *nlna_sc_init(device_t dev,
+ struct xlr_gmac_block_t *blk);
+static void nlna_setup_intr(struct nlna_softc *sc);
+static void nlna_smp_update_pde(void *dummy __unused);
+static void nlna_submit_rx_free_desc(struct nlna_softc *sc,
+ uint32_t n_desc);
+
+static int nlge_gmac_config_speed(struct nlge_softc *, int quick);
+static void nlge_hw_init(struct nlge_softc *sc);
+static int nlge_if_init(struct nlge_softc *sc);
+static void nlge_intr(void *arg);
+static int nlge_irq_init(struct nlge_softc *sc);
+static void nlge_irq_fini(struct nlge_softc *sc);
+static void nlge_media_specific_init(struct nlge_softc *sc);
+static void nlge_mii_init(device_t dev, struct nlge_softc *sc);
+static int nlge_mii_read_internal(xlr_reg_t *mii_base, int phyaddr,
+ int regidx);
+static void nlge_mii_write_internal(xlr_reg_t *mii_base, int phyaddr,
+ int regidx, int regval);
+void nlge_msgring_handler(int bucket, int size, int code,
+ int stid, struct msgrng_msg *msg, void *data);
+static void nlge_port_disable(struct nlge_softc *sc);
+static void nlge_port_enable(struct nlge_softc *sc);
+static void nlge_read_mac_addr(struct nlge_softc *sc);
+static void nlge_sc_init(struct nlge_softc *sc, device_t dev,
+ struct xlr_gmac_port *port_info);
+static void nlge_set_mac_addr(struct nlge_softc *sc);
+static void nlge_set_port_attribs(struct nlge_softc *,
+ struct xlr_gmac_port *);
+static void nlge_mac_set_rx_mode(struct nlge_softc *sc);
+static void nlge_sgmii_init(struct nlge_softc *sc);
+static int nlge_start_locked(struct ifnet *ifp, struct nlge_softc *sc,
+ struct mbuf *m);
+
+static int prepare_fmn_message(struct nlge_softc *sc,
+ struct msgrng_msg *msg, uint32_t *n_entries, struct mbuf *m_head,
+ uint64_t fr_stid, struct nlge_tx_desc **tx_desc);
+
+static void release_tx_desc(vm_paddr_t phy_addr);
+static int send_fmn_msg_tx(struct nlge_softc *, struct msgrng_msg *,
+ uint32_t n_entries);
+
+//#define DEBUG
+#ifdef DEBUG
+static int mac_debug = 1;
+#undef PDEBUG
+#define PDEBUG(fmt, args...) \
+ do {\
+ if (mac_debug) {\
+ printf("[%s@%d|%s]: cpu_%d: " fmt, \
+ __FILE__, __LINE__, __FUNCTION__, PCPU_GET(cpuid), ##args);\
+ }\
+ } while(0);
+
+/* Debug/dump functions */
+static void dump_reg(xlr_reg_t *addr, uint32_t offset, char *name);
+static void dump_gmac_registers(struct nlge_softc *);
+static void dump_na_registers(xlr_reg_t *base, int port_id);
+static void dump_mac_stats(struct nlge_softc *sc);
+static void dump_mii_regs(struct nlge_softc *sc) __attribute__((used));
+static void dump_mii_data(struct mii_data *mii) __attribute__((used));
+static void dump_board_info(struct xlr_board_info *);
+static void dump_pcs_regs(struct nlge_softc *sc, int phy);
+
+#else
+#undef PDEBUG
+#define PDEBUG(fmt, args...)
+#define dump_reg(a, o, n) /* nop */
+#define dump_gmac_registers(a) /* nop */
+#define dump_na_registers(a, p) /* nop */
+#define dump_board_info(b) /* nop */
+#define dump_mac_stats(sc) /* nop */
+#define dump_mii_regs(sc) /* nop */
+#define dump_mii_data(mii) /* nop */
+#define dump_pcs_regs(sc, phy) /* nop */
+#endif
+
+/* Wrappers etc. to export the driver entry points. */
+static device_method_t nlna_methods[] = {
+ /* Device interface */
+ DEVMETHOD(device_probe, nlna_probe),
+ DEVMETHOD(device_attach, nlna_attach),
+ DEVMETHOD(device_detach, nlna_detach),
+ DEVMETHOD(device_shutdown, nlna_shutdown),
+ DEVMETHOD(device_suspend, nlna_suspend),
+ DEVMETHOD(device_resume, nlna_resume),
+
+ /* bus interface : TBD : what are these for ? */
+ DEVMETHOD(bus_setup_intr, bus_generic_setup_intr),
+
+ DEVMETHOD_END
+};
+
+static driver_t nlna_driver = {
+ "nlna",
+ nlna_methods,
+ sizeof(struct nlna_softc)
+};
+
+static devclass_t nlna_devclass;
+
+static device_method_t nlge_methods[] = {
+ /* Device interface */
+ DEVMETHOD(device_probe, nlge_probe),
+ DEVMETHOD(device_attach, nlge_attach),
+ DEVMETHOD(device_detach, nlge_detach),
+ DEVMETHOD(device_shutdown, bus_generic_shutdown),
+ DEVMETHOD(device_suspend, nlge_suspend),
+ DEVMETHOD(device_resume, nlge_resume),
+
+ /* MII interface */
+ DEVMETHOD(miibus_readreg, nlge_mii_read),
+ DEVMETHOD(miibus_writereg, nlge_mii_write),
+ DEVMETHOD(miibus_statchg, nlge_mac_mii_statchg),
+
+ {0, 0}
+};
+
+static driver_t nlge_driver = {
+ "nlge",
+ nlge_methods,
+ sizeof(struct nlge_softc)
+};
+
+static devclass_t nlge_devclass;
+
+DRIVER_MODULE(nlna, iodi, nlna_driver, nlna_devclass, 0, 0);
+DRIVER_MODULE(nlge, nlna, nlge_driver, nlge_devclass, 0, 0);
+DRIVER_MODULE(miibus, nlge, miibus_driver, miibus_devclass, 0, 0);
+
+static uma_zone_t nl_tx_desc_zone;
+
+/* Tunables. */
+static int flow_classification = 0;
+TUNABLE_INT("hw.nlge.flow_classification", &flow_classification);
+
+#define NLGE_HW_CHKSUM 1
+
+static __inline void
+atomic_incr_long(unsigned long *addr)
+{
+ /* XXX: fix for 64 bit */
+ unsigned int *iaddr = (unsigned int *)addr;
+
+ xlr_ldaddwu(1, iaddr);
+}
+
+static int
+nlna_probe(device_t dev)
+{
+ return (BUS_PROBE_DEFAULT);
+}
+
+/*
+ * Add all attached GMAC/XGMAC ports to the device tree. Port
+ * configuration is spread in two regions - common configuration
+ * for all ports in the NA and per-port configuration in MAC-specific
+ * region. This function does the following:
+ * - adds the ports to the device tree
+ * - reset the ports
+ * - do all the common initialization
+ * - invoke bus_generic_attach for per-port configuration
+ * - supply initial free rx descriptors to ports
+ * - initialize s/w data structures
+ * - finally, enable interrupts (only in the last NA).
+ *
+ * For reference, sample address space for common and per-port
+ * registers is given below.
+ *
+ * The address map for RNA0 is: (typical value)
+ *
+ * XLR_IO_BASE +--------------------------------------+ 0xbef0_0000
+ * | |
+ * | |
+ * | |
+ * | |
+ * | |
+ * | |
+ * GMAC0 ---> +--------------------------------------+ 0xbef0_c000
+ * | |
+ * | |
+ * (common) -> |......................................| 0xbef0_c400
+ * | |
+ * | (RGMII/SGMII: common registers) |
+ * | |
+ * GMAC1 ---> |--------------------------------------| 0xbef0_d000
+ * | |
+ * | |
+ * (common) -> |......................................| 0xbef0_d400
+ * | |
+ * | (RGMII/SGMII: common registers) |
+ * | |
+ * |......................................|
+ * and so on ....
+ *
+ * Ref: Figure 14-3 and Table 14-1 of XLR PRM
+ */
+static int
+nlna_attach(device_t dev)
+{
+ struct xlr_gmac_block_t *block_info;
+ device_t gmac_dev;
+ struct nlna_softc *sc;
+ int error;
+ int i;
+ int id;
+
+ id = device_get_unit(dev);
+ block_info = device_get_ivars(dev);
+ if (!block_info->enabled) {
+ return 0;
+ }
+
+#ifdef DEBUG
+ dump_board_info(&xlr_board_info);
+#endif
+ /* Initialize nlna state in softc structure */
+ sc = nlna_sc_init(dev, block_info);
+
+ /* Add device's for the ports controlled by this NA. */
+ if (block_info->type == XLR_GMAC) {
+ KASSERT(id < 2, ("No GMACs supported with this network"
+ "accelerator: %d", id));
+ for (i = 0; i < sc->num_ports; i++) {
+ gmac_dev = device_add_child(dev, "nlge", -1);
+ device_set_ivars(gmac_dev, &block_info->gmac_port[i]);
+ }
+ } else if (block_info->type == XLR_XGMAC) {
+ KASSERT(id > 0 && id <= 2, ("No XGMACs supported with this"
+ "network accelerator: %d", id));
+ gmac_dev = device_add_child(dev, "nlge", -1);
+ device_set_ivars(gmac_dev, &block_info->gmac_port[0]);
+ } else if (block_info->type == XLR_SPI4) {
+ /* SPI4 is not supported here */
+ device_printf(dev, "Unsupported: NA with SPI4 type");
+ return (ENOTSUP);
+ }
+
+ nlna_reset_ports(sc, block_info);
+
+ /* Initialize Network Accelarator registers. */
+ nlna_hw_init(sc);
+
+ error = bus_generic_attach(dev);
+ if (error) {
+ device_printf(dev, "failed to attach port(s)\n");
+ goto fail;
+ }
+
+ /* Send out the initial pool of free-descriptors for the rx path */
+ nlna_submit_rx_free_desc(sc, MAX_FRIN_SPILL);
+
+ /* S/w data structure initializations shared by all NA's. */
+ if (nl_tx_desc_zone == NULL) {
+ /* Create a zone for allocating tx descriptors */
+ nl_tx_desc_zone = uma_zcreate("NL Tx Desc",
+ sizeof(struct nlge_tx_desc), NULL, NULL, NULL, NULL,
+ XLR_CACHELINE_SIZE, 0);
+ }
+
+ /* Enable NA interrupts */
+ nlna_setup_intr(sc);
+
+ return (0);
+
+fail:
+ return (error);
+}
+
+static int
+nlna_detach(device_t dev)
+{
+ struct nlna_softc *sc;
+
+ sc = device_get_softc(dev);
+ if (device_is_alive(dev)) {
+ nlna_disable_intr(sc);
+ /* This will make sure that per-port detach is complete
+ * and all traffic on the ports has been stopped. */
+ bus_generic_detach(dev);
+ uma_zdestroy(nl_tx_desc_zone);
+ }
+
+ return (0);
+}
+
+static int
+nlna_suspend(device_t dev)
+{
+
+ return (0);
+}
+
+static int
+nlna_resume(device_t dev)
+{
+
+ return (0);
+}
+
+static int
+nlna_shutdown(device_t dev)
+{
+ return (0);
+}
+
+
+/* GMAC port entry points */
+static int
+nlge_probe(device_t dev)
+{
+ struct nlge_softc *sc;
+ struct xlr_gmac_port *port_info;
+ int index;
+ char *desc[] = { "RGMII", "SGMII", "RGMII/SGMII", "XGMAC", "XAUI",
+ "Unknown"};
+
+ port_info = device_get_ivars(dev);
+ index = (port_info->type < XLR_RGMII || port_info->type > XLR_XAUI) ?
+ 5 : port_info->type;
+ device_set_desc_copy(dev, desc[index]);
+
+ sc = device_get_softc(dev);
+ nlge_sc_init(sc, dev, port_info);
+
+ nlge_port_disable(sc);
+
+ return (0);
+}
+
+static int
+nlge_attach(device_t dev)
+{
+ struct nlge_softc *sc;
+ struct nlna_softc *nsc;
+ int error;
+
+ sc = device_get_softc(dev);
+
+ nlge_if_init(sc);
+ nlge_mii_init(dev, sc);
+ error = nlge_irq_init(sc);
+ if (error)
+ return error;
+ nlge_hw_init(sc);
+
+ nsc = (struct nlna_softc *)device_get_softc(device_get_parent(dev));
+ nsc->child_sc[sc->instance] = sc;
+
+ return (0);
+}
+
+static int
+nlge_detach(device_t dev)
+{
+ struct nlge_softc *sc;
+ struct ifnet *ifp;
+
+ sc = device_get_softc(dev);
+ ifp = sc->nlge_if;
+
+ if (device_is_attached(dev)) {
+ nlge_port_disable(sc);
+ nlge_irq_fini(sc);
+ ether_ifdetach(ifp);
+ bus_generic_detach(dev);
+ }
+ if (ifp)
+ if_free(ifp);
+
+ return (0);
+}
+
+static int
+nlge_suspend(device_t dev)
+{
+ return (0);
+}
+
+static int
+nlge_resume(device_t dev)
+{
+ return (0);
+}
+
+static void
+nlge_init(void *addr)
+{
+ struct nlge_softc *sc;
+ struct ifnet *ifp;
+
+ sc = (struct nlge_softc *)addr;
+ ifp = sc->nlge_if;
+
+ if (ifp->if_drv_flags & IFF_DRV_RUNNING)
+ return;
+
+ nlge_gmac_config_speed(sc, 1);
+ ifp->if_drv_flags |= IFF_DRV_RUNNING;
+ ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
+ nlge_port_enable(sc);
+
+ if (sc->port_type == XLR_SGMII) {
+ dump_pcs_regs(sc, 27);
+ }
+ dump_gmac_registers(sc);
+ dump_mac_stats(sc);
+}
+
+static int
+nlge_ioctl(struct ifnet *ifp, u_long command, caddr_t data)
+{
+ struct mii_data *mii;
+ struct nlge_softc *sc;
+ struct ifreq *ifr;
+ int error;
+
+ sc = ifp->if_softc;
+ error = 0;
+ ifr = (struct ifreq *)data;
+
+ switch(command) {
+ case SIOCSIFFLAGS:
+ NLGE_LOCK(sc);
+ if (ifp->if_flags & IFF_UP) {
+ if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) {
+ nlge_init(sc);
+ }
+ if (ifp->if_flags & IFF_PROMISC &&
+ !(sc->if_flags & IFF_PROMISC)) {
+ sc->if_flags |= IFF_PROMISC;
+ nlge_mac_set_rx_mode(sc);
+ } else if (!(ifp->if_flags & IFF_PROMISC) &&
+ sc->if_flags & IFF_PROMISC) {
+ sc->if_flags &= IFF_PROMISC;
+ nlge_mac_set_rx_mode(sc);
+ }
+ } else {
+ if (ifp->if_drv_flags & IFF_DRV_RUNNING) {
+ nlge_port_disable(sc);
+ }
+ }
+ sc->if_flags = ifp->if_flags;
+ NLGE_UNLOCK(sc);
+ error = 0;
+ break;
+
+ case SIOCSIFMEDIA:
+ case SIOCGIFMEDIA:
+ if (sc->mii_bus != NULL) {
+ mii = (struct mii_data *)device_get_softc(sc->mii_bus);
+ error = ifmedia_ioctl(ifp, ifr, &mii->mii_media,
+ command);
+ }
+ break;
+
+ default:
+ error = ether_ioctl(ifp, command, data);
+ break;
+ }
+
+ return (error);
+}
+
+/* This function is called from an interrupt handler */
+void
+nlge_msgring_handler(int bucket, int size, int code, int stid,
+ struct msgrng_msg *msg, void *data)
+{
+ struct nlna_softc *na_sc;
+ struct nlge_softc *sc;
+ struct ifnet *ifp;
+ struct mbuf *m;
+ vm_paddr_t phys_addr;
+ uint32_t length;
+ int ctrl;
+ int tx_error;
+ int port;
+ int is_p2p;
+
+ is_p2p = 0;
+ tx_error = 0;
+ length = (msg->msg0 >> 40) & 0x3fff;
+ na_sc = (struct nlna_softc *)data;
+ if (length == 0) {
+ ctrl = CTRL_REG_FREE;
+ phys_addr = msg->msg0 & 0xffffffffffULL;
+ port = (msg->msg0 >> 54) & 0x0f;
+ is_p2p = (msg->msg0 >> 62) & 0x1;
+ tx_error = (msg->msg0 >> 58) & 0xf;
+ } else {
+ ctrl = CTRL_SNGL;
+ phys_addr = msg->msg0 & 0xffffffffe0ULL;
+ length = length - BYTE_OFFSET - MAC_CRC_LEN;
+ port = msg->msg0 & 0x0f;
+ }
+
+ sc = na_sc->child_sc[port];
+ if (sc == NULL) {
+ printf("Message (of %d len) with softc=NULL on %d port (type=%s)\n",
+ length, port, (ctrl == CTRL_SNGL ? "Pkt rx" :
+ "Freeback for tx packet"));
+ return;
+ }
+
+ if (ctrl == CTRL_REG_FREE || ctrl == CTRL_JUMBO_FREE) {
+ ifp = sc->nlge_if;
+ if (!tx_error) {
+ if (is_p2p) {
+ release_tx_desc(phys_addr);
+ } else {
+#ifdef __mips_n64
+ m = (struct mbuf *)(uintptr_t)xlr_paddr_ld(phys_addr);
+ m->m_nextpkt = NULL;
+#else
+ m = (struct mbuf *)(uintptr_t)phys_addr;
+#endif
+ m_freem(m);
+ }
+ NLGE_LOCK(sc);
+ if (ifp->if_drv_flags & IFF_DRV_OACTIVE){
+ ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
+ }
+ NLGE_UNLOCK(sc);
+ } else {
+ printf("ERROR: Tx fb error (%d) on port %d\n", tx_error,
+ port);
+ }
+ atomic_incr_long((tx_error) ? &ifp->if_oerrors: &ifp->if_opackets);
+ } else if (ctrl == CTRL_SNGL || ctrl == CTRL_START) {
+ /* Rx Packet */
+
+ nlge_rx(sc, phys_addr, length);
+ nlna_submit_rx_free_desc(na_sc, 1); /* return free descr to NA */
+ } else {
+ printf("[%s]: unrecognized ctrl=%d!\n", __func__, ctrl);
+ }
+
+}
+
+static int
+nlge_tx(struct ifnet *ifp, struct mbuf *m)
+{
+ return (nlge_start_locked(ifp, ifp->if_softc, m));
+}
+
+static int
+nlge_start_locked(struct ifnet *ifp, struct nlge_softc *sc, struct mbuf *m)
+{
+ struct msgrng_msg msg;
+ struct nlge_tx_desc *tx_desc;
+ uint64_t fr_stid;
+ uint32_t cpu;
+ uint32_t n_entries;
+ uint32_t tid;
+ int error, ret;
+
+ if (m == NULL)
+ return (0);
+
+ tx_desc = NULL;
+ error = 0;
+ if (!(ifp->if_drv_flags & IFF_DRV_RUNNING) ||
+ ifp->if_drv_flags & IFF_DRV_OACTIVE) {
+ error = ENXIO;
+ goto fail; // note: mbuf will get free'd
+ }
+
+ cpu = xlr_core_id();
+ tid = xlr_thr_id();
+ /* H/w threads [0, 2] --> bucket 6 and [1, 3] --> bucket 7 */
+ fr_stid = cpu * 8 + 6 + (tid % 2);
+
+ /*
+ * First, remove some freeback messages before transmitting
+ * any new packets. However, cap the number of messages
+ * drained to permit this thread to continue with its
+ * transmission.
+ *
+ * Mask for buckets {6, 7} is 0xc0
+ */
+ xlr_msgring_handler(0xc0, 4);
+
+ ret = prepare_fmn_message(sc, &msg, &n_entries, m, fr_stid, &tx_desc);
+ if (ret) {
+ error = (ret == 2) ? ENOBUFS : ENOTSUP;
+ goto fail;
+ }
+ ret = send_fmn_msg_tx(sc, &msg, n_entries);
+ if (ret != 0) {
+ error = EBUSY;
+ goto fail;
+ }
+
+ return (0);
+
+fail:
+ if (tx_desc != NULL) {
+ uma_zfree(nl_tx_desc_zone, tx_desc);
+ }
+ if (m != NULL) {
+ if (ifp->if_drv_flags & IFF_DRV_RUNNING) {
+ NLGE_LOCK(sc);
+ ifp->if_drv_flags |= IFF_DRV_OACTIVE;
+ NLGE_UNLOCK(sc);
+ }
+ m_freem(m);
+ atomic_incr_long(&ifp->if_iqdrops);
+ }
+ return (error);
+}
+
+static void
+nlge_rx(struct nlge_softc *sc, vm_paddr_t paddr, int len)
+{
+ struct ifnet *ifp;
+ struct mbuf *m;
+ uint64_t tm, mag;
+ uint32_t sr;
+
+ sr = xlr_enable_kx();
+ tm = xlr_paddr_ld(paddr - XLR_CACHELINE_SIZE);
+ mag = xlr_paddr_ld(paddr - XLR_CACHELINE_SIZE + sizeof(uint64_t));
+ xlr_restore_kx(sr);
+
+ m = (struct mbuf *)(intptr_t)tm;
+ if (mag != 0xf00bad) {
+ /* somebody else's packet. Error - FIXME in intialization */
+ printf("cpu %d: *ERROR* Not my packet paddr %jx\n",
+ xlr_core_id(), (uintmax_t)paddr);
+ return;
+ }
+
+ ifp = sc->nlge_if;
+
+#ifdef NLGE_HW_CHKSUM
+ m->m_pkthdr.csum_flags = CSUM_IP_CHECKED;
+ if (m->m_data[10] & 0x2) {
+ m->m_pkthdr.csum_flags |= CSUM_IP_VALID;
+ if (m->m_data[10] & 0x1) {
+ m->m_pkthdr.csum_flags |= (CSUM_DATA_VALID |
+ CSUM_PSEUDO_HDR);
+ m->m_pkthdr.csum_data = htons(0xffff);
+ }
+ }
+ m->m_data += NLGE_PREPAD_LEN;
+ len -= NLGE_PREPAD_LEN;
+#else
+ m->m_pkthdr.csum_flags = 0;
+#endif
+
+ /* align the data */
+ m->m_data += BYTE_OFFSET ;
+ m->m_pkthdr.len = m->m_len = len;
+ m->m_pkthdr.rcvif = ifp;
+
+ atomic_incr_long(&ifp->if_ipackets);
+ (*ifp->if_input)(ifp, m);
+}
+
+static int
+nlge_mii_write(struct device *dev, int phyaddr, int regidx, int regval)
+{
+ struct nlge_softc *sc;
+
+ sc = device_get_softc(dev);
+ if (sc->port_type != XLR_XGMII)
+ nlge_mii_write_internal(sc->mii_base, phyaddr, regidx, regval);
+
+ return (0);
+}
+
+static int
+nlge_mii_read(struct device *dev, int phyaddr, int regidx)
+{
+ struct nlge_softc *sc;
+ int val;
+
+ sc = device_get_softc(dev);
+ val = (sc->port_type == XLR_XGMII) ? (0xffff) :
+ nlge_mii_read_internal(sc->mii_base, phyaddr, regidx);
+
+ return (val);
+}
+
+static void
+nlge_mac_mii_statchg(device_t dev)
+{
+}
+
+static int
+nlge_mediachange(struct ifnet *ifp)
+{
+ return 0;
+}
+
+static void
+nlge_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr)
+{
+ struct nlge_softc *sc;
+ struct mii_data *md;
+
+ md = NULL;
+ sc = ifp->if_softc;
+ if (sc->mii_bus)
+ md = device_get_softc(sc->mii_bus);
+
+ ifmr->ifm_status = IFM_AVALID;
+ ifmr->ifm_active = IFM_ETHER;
+
+ if (sc->link == xlr_mac_link_down)
+ return;
+
+ if (md != NULL)
+ ifmr->ifm_active = md->mii_media.ifm_cur->ifm_media;
+ ifmr->ifm_status |= IFM_ACTIVE;
+}
+
+static struct nlna_softc *
+nlna_sc_init(device_t dev, struct xlr_gmac_block_t *blk)
+{
+ struct nlna_softc *sc;
+
+ sc = device_get_softc(dev);
+ memset(sc, 0, sizeof(*sc));
+ sc->nlna_dev = dev;
+ sc->base = xlr_io_mmio(blk->baseaddr);
+ sc->rfrbucket = blk->station_rfr;
+ sc->station_id = blk->station_id;
+ sc->na_type = blk->type;
+ sc->mac_type = blk->mode;
+ sc->num_ports = blk->num_ports;
+
+ sc->mdio_set.port_vec = sc->mdio_sc;
+ sc->mdio_set.vec_sz = XLR_MAX_MACS;
+
+ return (sc);
+}
+
+/*
+ * Do:
+ * - Initialize common GMAC registers (index range 0x100-0x3ff).
+ */
+static void
+nlna_hw_init(struct nlna_softc *sc)
+{
+
+ /*
+ * Register message ring handler for the NA block, messages from
+ * the GMAC will have source station id to the first bucket of the
+ * NA FMN station, so register just that station id.
+ */
+ if (register_msgring_handler(sc->station_id, sc->station_id + 1,
+ nlge_msgring_handler, sc)) {
+ panic("Couldn't register msgring handler\n");
+ }
+ nlna_config_fifo_spill_area(sc);
+ nlna_config_pde(sc);
+ nlna_config_common(sc);
+ nlna_config_parser(sc);
+ nlna_config_classifier(sc);
+}
+
+/*
+ * Enable interrupts on all the ports controlled by this NA. For now, we
+ * only care about the MII interrupt and this has to be enabled only
+ * on the port id0.
+ *
+ * This function is not in-sync with the regular way of doing things - it
+ * executes only in the context of the last active network accelerator (and
+ * thereby has some ugly accesses in the device tree). Though inelegant, it
+ * is necessary to do it this way as the per-port interrupts can be
+ * setup/enabled only after all the network accelerators have been
+ * initialized.
+ */
+static void
+nlna_setup_intr(struct nlna_softc *sc)
+{
+ struct nlna_softc *na_sc[XLR_MAX_NLNA];
+ struct nlge_port_set *pset;
+ struct xlr_gmac_port *port_info;
+ device_t iodi_dev;
+ int i, j;
+
+ if (!nlna_is_last_active_na(sc))
+ return ;
+
+ /* Collect all nlna softc pointers */
+ memset(na_sc, 0, sizeof(*na_sc) * XLR_MAX_NLNA);
+ iodi_dev = device_get_parent(sc->nlna_dev);
+ nlna_get_all_softc(iodi_dev, na_sc, XLR_MAX_NLNA);
+
+ /* Setup the MDIO interrupt lists. */
+ /*
+ * MDIO interrupts are coarse - a single interrupt line provides
+ * information about one of many possible ports. To figure out the
+ * exact port on which action is to be taken, all of the ports
+ * linked to an MDIO interrupt should be read. To enable this,
+ * ports need to add themselves to port sets.
+ */
+ for (i = 0; i < XLR_MAX_NLNA; i++) {
+ if (na_sc[i] == NULL)
+ continue;
+ for (j = 0; j < na_sc[i]->num_ports; j++) {
+ /* processing j-th port on i-th NA */
+ port_info = device_get_ivars(
+ na_sc[i]->child_sc[j]->nlge_dev);
+ pset = &na_sc[port_info->mdint_id]->mdio_set;
+ nlna_add_to_port_set(pset, na_sc[i]->child_sc[j]);
+ }
+ }
+
+ /* Enable interrupts */
+ for (i = 0; i < XLR_MAX_NLNA; i++) {
+ if (na_sc[i] != NULL && na_sc[i]->na_type != XLR_XGMAC) {
+ nlna_enable_intr(na_sc[i]);
+ }
+ }
+}
+
+static void
+nlna_add_to_port_set(struct nlge_port_set *pset, struct nlge_softc *sc)
+{
+ int i;
+
+ /* step past the non-NULL elements */
+ for (i = 0; i < pset->vec_sz && pset->port_vec[i] != NULL; i++) ;
+ if (i < pset->vec_sz)
+ pset->port_vec[i] = sc;
+ else
+ printf("warning: internal error: out-of-bounds for MDIO array");
+}
+
+static void
+nlna_enable_intr(struct nlna_softc *sc)
+{
+ int i;
+
+ for (i = 0; i < sc->num_ports; i++) {
+ if (sc->child_sc[i]->instance == 0)
+ NLGE_WRITE(sc->child_sc[i]->base, R_INTMASK,
+ (1 << O_INTMASK__MDInt));
+ }
+}
+
+static void
+nlna_disable_intr(struct nlna_softc *sc)
+{
+ int i;
+
+ for (i = 0; i < sc->num_ports; i++) {
+ if (sc->child_sc[i]->instance == 0)
+ NLGE_WRITE(sc->child_sc[i]->base, R_INTMASK, 0);
+ }
+}
+
+static int
+nlna_is_last_active_na(struct nlna_softc *sc)
+{
+ int id;
+
+ id = device_get_unit(sc->nlna_dev);
+ return (id == 2 || xlr_board_info.gmac_block[id + 1].enabled == 0);
+}
+
+static void
+nlna_submit_rx_free_desc(struct nlna_softc *sc, uint32_t n_desc)
+{
+ struct msgrng_msg msg;
+ void *ptr;
+ uint32_t msgrng_flags;
+ int i, n, stid, ret, code;
+
+ if (n_desc > 1) {
+ PDEBUG("Sending %d free-in descriptors to station=%d\n", n_desc,
+ sc->rfrbucket);
+ }
+
+ stid = sc->rfrbucket;
+ code = (sc->na_type == XLR_XGMAC) ? MSGRNG_CODE_XGMAC : MSGRNG_CODE_MAC;
+ memset(&msg, 0, sizeof(msg));
+
+ for (i = 0; i < n_desc; i++) {
+ ptr = get_buf();
+ if (!ptr) {
+ ret = -ENOMEM;
+ device_printf(sc->nlna_dev, "Cannot allocate mbuf\n");
+ break;
+ }
+
+ /* Send the free Rx desc to the MAC */
+ msg.msg0 = vtophys(ptr) & 0xffffffffe0ULL;
+ n = 0;
+ do {
+ msgrng_flags = msgrng_access_enable();
+ ret = message_send(1, code, stid, &msg);
+ msgrng_restore(msgrng_flags);
+ KASSERT(n++ < 100000, ("Too many credit fails in rx path\n"));
+ } while (ret != 0);
+ }
+}
+
+static __inline__ void *
+nlna_config_spill(xlr_reg_t *base, int reg_start_0, int reg_start_1,
+ int reg_size, int size)
+{
+ void *spill;
+ uint64_t phys_addr;
+ uint32_t spill_size;
+
+ spill_size = size;
+ spill = contigmalloc((spill_size + XLR_CACHELINE_SIZE), M_DEVBUF,
+ M_NOWAIT | M_ZERO, 0, 0xffffffff, XLR_CACHELINE_SIZE, 0);
+ if (spill == NULL || ((vm_offset_t) spill & (XLR_CACHELINE_SIZE - 1))) {
+ panic("Unable to allocate memory for spill area!\n");
+ }
+ phys_addr = vtophys(spill);
+ PDEBUG("Allocated spill %d bytes at %llx\n", size, phys_addr);
+ NLGE_WRITE(base, reg_start_0, (phys_addr >> 5) & 0xffffffff);
+ NLGE_WRITE(base, reg_start_1, (phys_addr >> 37) & 0x07);
+ NLGE_WRITE(base, reg_size, spill_size);
+
+ return (spill);
+}
+
+/*
+ * Configure the 6 FIFO's that are used by the network accelarator to
+ * communicate with the rest of the XLx device. 4 of the FIFO's are for
+ * packets from NA --> cpu (called Class FIFO's) and 2 are for feeding
+ * the NA with free descriptors.
+ */
+static void
+nlna_config_fifo_spill_area(struct nlna_softc *sc)
+{
+ sc->frin_spill = nlna_config_spill(sc->base,
+ R_REG_FRIN_SPILL_MEM_START_0,
+ R_REG_FRIN_SPILL_MEM_START_1,
+ R_REG_FRIN_SPILL_MEM_SIZE,
+ MAX_FRIN_SPILL *
+ sizeof(struct fr_desc));
+ sc->frout_spill = nlna_config_spill(sc->base,
+ R_FROUT_SPILL_MEM_START_0,
+ R_FROUT_SPILL_MEM_START_1,
+ R_FROUT_SPILL_MEM_SIZE,
+ MAX_FROUT_SPILL *
+ sizeof(struct fr_desc));
+ sc->class_0_spill = nlna_config_spill(sc->base,
+ R_CLASS0_SPILL_MEM_START_0,
+ R_CLASS0_SPILL_MEM_START_1,
+ R_CLASS0_SPILL_MEM_SIZE,
+ MAX_CLASS_0_SPILL *
+ sizeof(union rx_tx_desc));
+ sc->class_1_spill = nlna_config_spill(sc->base,
+ R_CLASS1_SPILL_MEM_START_0,
+ R_CLASS1_SPILL_MEM_START_1,
+ R_CLASS1_SPILL_MEM_SIZE,
+ MAX_CLASS_1_SPILL *
+ sizeof(union rx_tx_desc));
+ sc->class_2_spill = nlna_config_spill(sc->base,
+ R_CLASS2_SPILL_MEM_START_0,
+ R_CLASS2_SPILL_MEM_START_1,
+ R_CLASS2_SPILL_MEM_SIZE,
+ MAX_CLASS_2_SPILL *
+ sizeof(union rx_tx_desc));
+ sc->class_3_spill = nlna_config_spill(sc->base,
+ R_CLASS3_SPILL_MEM_START_0,
+ R_CLASS3_SPILL_MEM_START_1,
+ R_CLASS3_SPILL_MEM_SIZE,
+ MAX_CLASS_3_SPILL *
+ sizeof(union rx_tx_desc));
+}
+
+/* Set the CPU buckets that receive packets from the NA class FIFOs. */
+static void
+nlna_config_pde(struct nlna_softc *sc)
+{
+ uint64_t bucket_map;
+ uint32_t cpumask;
+ int i, cpu, bucket;
+
+ cpumask = 0x1;
+#ifdef SMP
+ /*
+ * rge may be called before SMP start in a BOOTP/NFSROOT
+ * setup. we will distribute packets to other cpus only when
+ * the SMP is started.
+ */
+ if (smp_started)
+ cpumask = xlr_hw_thread_mask;
+#endif
+ bucket_map = 0;
+ for (i = 0; i < 32; i++) {
+ if (cpumask & (1 << i)) {
+ cpu = i;
+ /* use bucket 0 and 1 on every core for NA msgs */
+ bucket = cpu/4 * 8;
+ bucket_map |= (3ULL << bucket);
+ }
+ }
+
+ NLGE_WRITE(sc->base, R_PDE_CLASS_0, (bucket_map & 0xffffffff));
+ NLGE_WRITE(sc->base, R_PDE_CLASS_0 + 1, ((bucket_map >> 32) & 0xffffffff));
+
+ NLGE_WRITE(sc->base, R_PDE_CLASS_1, (bucket_map & 0xffffffff));
+ NLGE_WRITE(sc->base, R_PDE_CLASS_1 + 1, ((bucket_map >> 32) & 0xffffffff));
+
+ NLGE_WRITE(sc->base, R_PDE_CLASS_2, (bucket_map & 0xffffffff));
+ NLGE_WRITE(sc->base, R_PDE_CLASS_2 + 1, ((bucket_map >> 32) & 0xffffffff));
+
+ NLGE_WRITE(sc->base, R_PDE_CLASS_3, (bucket_map & 0xffffffff));
+ NLGE_WRITE(sc->base, R_PDE_CLASS_3 + 1, ((bucket_map >> 32) & 0xffffffff));
+}
+
+/*
+ * Update the network accelerator packet distribution engine for SMP.
+ * On bootup, we have just the boot hw thread handling all packets, on SMP
+ * start, we can start distributing packets across all the cores which are up.
+ */
+static void
+nlna_smp_update_pde(void *dummy __unused)
+{
+ device_t iodi_dev;
+ struct nlna_softc *na_sc[XLR_MAX_NLNA];
+ int i;
+
+ printf("Updating packet distribution for SMP\n");
+
+ iodi_dev = devclass_get_device(devclass_find("iodi"), 0);
+ nlna_get_all_softc(iodi_dev, na_sc, XLR_MAX_NLNA);
+
+ for (i = 0; i < XLR_MAX_NLNA; i++) {
+ if (na_sc[i] == NULL)
+ continue;
+ nlna_disable_ports(na_sc[i]);
+ nlna_config_pde(na_sc[i]);
+ nlna_config_translate_table(na_sc[i]);
+ nlna_enable_ports(na_sc[i]);
+ }
+}
+
+SYSINIT(nlna_smp_update_pde, SI_SUB_SMP, SI_ORDER_ANY, nlna_smp_update_pde,
+ NULL);
+
+static void
+nlna_config_translate_table(struct nlna_softc *sc)
+{
+ uint32_t cpu_mask;
+ uint32_t val;
+ int bkts[32]; /* one bucket is assumed for each cpu */
+ int b1, b2, c1, c2, i, j, k;
+ int use_bkt;
+
+ if (!flow_classification)
+ return;
+
+ use_bkt = 1;
+ if (smp_started)
+ cpu_mask = xlr_hw_thread_mask;
+ else
+ return;
+
+ printf("Using %s-based distribution\n", (use_bkt) ? "bucket" : "class");
+
+ j = 0;
+ for(i = 0; i < 32; i++) {
+ if ((1 << i) & cpu_mask){
+ /* for each cpu, mark the 4+threadid bucket */
+ bkts[j] = ((i / 4) * 8) + (i % 4);
+ j++;
+ }
+ }
+
+ /*configure the 128 * 9 Translation table to send to available buckets*/
+ k = 0;
+ c1 = 3;
+ c2 = 0;
+ for(i = 0; i < 64; i++) {
+ /* Get the next 2 pairs of (class, bucket):
+ (c1, b1), (c2, b2).
+
+ c1, c2 limited to {0, 1, 2, 3}
+ i.e, the 4 classes defined by h/w
+ b1, b2 limited to { bkts[i], where 0 <= i < j}
+ i.e, the set of buckets computed in the
+ above loop.
+ */
+
+ c1 = (c1 + 1) & 3;
+ c2 = (c1 + 1) & 3;
+ b1 = bkts[k];
+ k = (k + 1) % j;
+ b2 = bkts[k];
+ k = (k + 1) % j;
+ PDEBUG("Translation table[%d] b1=%d b2=%d c1=%d c2=%d\n",
+ i, b1, b2, c1, c2);
+ val = ((c1 << 23) | (b1 << 17) | (use_bkt << 16) |
+ (c2 << 7) | (b2 << 1) | (use_bkt << 0));
+ NLGE_WRITE(sc->base, R_TRANSLATETABLE + i, val);
+ c1 = c2;
+ }
+}
+
+static void
+nlna_config_parser(struct nlna_softc *sc)
+{
+ uint32_t val;
+
+ /*
+ * Mark it as ETHERNET type.
+ */
+ NLGE_WRITE(sc->base, R_L2TYPE_0, 0x01);
+
+#ifndef NLGE_HW_CHKSUM
+ if (!flow_classification)
+ return;
+#endif
+
+ /* Use 7bit CRChash for flow classification with 127 as CRC polynomial*/
+ NLGE_WRITE(sc->base, R_PARSERCONFIGREG, ((0x7f << 8) | (1 << 1)));
+
+ /* configure the parser : L2 Type is configured in the bootloader */
+ /* extract IP: src, dest protocol */
+ NLGE_WRITE(sc->base, R_L3CTABLE,
+ (9 << 20) | (1 << 19) | (1 << 18) | (0x01 << 16) |
+ (0x0800 << 0));
+ NLGE_WRITE(sc->base, R_L3CTABLE + 1,
+ (9 << 25) | (1 << 21) | (12 << 14) | (4 << 10) | (16 << 4) | 4);
+#ifdef NLGE_HW_CHKSUM
+ device_printf(sc->nlna_dev, "Enabled h/w support to compute TCP/IP"
+ " checksum\n");
+#endif
+
+ /* Configure to extract SRC port and Dest port for TCP and UDP pkts */
+ NLGE_WRITE(sc->base, R_L4CTABLE, 6);
+ NLGE_WRITE(sc->base, R_L4CTABLE + 2, 17);
+ val = ((0 << 21) | (2 << 17) | (2 << 11) | (2 << 7));
+ NLGE_WRITE(sc->base, R_L4CTABLE + 1, val);
+ NLGE_WRITE(sc->base, R_L4CTABLE + 3, val);
+}
+
+static void
+nlna_config_classifier(struct nlna_softc *sc)
+{
+ int i;
+
+ if (sc->mac_type == XLR_XGMII) { /* TBD: XGMII init sequence */
+ /* xgmac translation table doesn't have sane values on reset */
+ for (i = 0; i < 64; i++)
+ NLGE_WRITE(sc->base, R_TRANSLATETABLE + i, 0x0);
+
+ /*
+ * use upper 7 bits of the parser extract to index the
+ * translate table
+ */
+ NLGE_WRITE(sc->base, R_PARSERCONFIGREG, 0x0);
+ }
+}
+
+/*
+ * Complete a bunch of h/w register initializations that are common for all the
+ * ports controlled by a NA.
+ */
+static void
+nlna_config_common(struct nlna_softc *sc)
+{
+ struct xlr_gmac_block_t *block_info;
+ struct stn_cc *gmac_cc_config;
+ int i;
+
+ block_info = device_get_ivars(sc->nlna_dev);
+ gmac_cc_config = block_info->credit_config;
+ for (i = 0; i < MAX_NUM_MSGRNG_STN_CC; i++) {
+ NLGE_WRITE(sc->base, R_CC_CPU0_0 + i,
+ gmac_cc_config->counters[i >> 3][i & 0x07]);
+ }
+
+ NLGE_WRITE(sc->base, R_MSG_TX_THRESHOLD, 3);
+
+ NLGE_WRITE(sc->base, R_DMACR0, 0xffffffff);
+ NLGE_WRITE(sc->base, R_DMACR1, 0xffffffff);
+ NLGE_WRITE(sc->base, R_DMACR2, 0xffffffff);
+ NLGE_WRITE(sc->base, R_DMACR3, 0xffffffff);
+ NLGE_WRITE(sc->base, R_FREEQCARVE, 0);
+
+ nlna_media_specific_config(sc);
+}
+
+static void
+nlna_media_specific_config(struct nlna_softc *sc)
+{
+ struct bucket_size *bucket_sizes;
+
+ bucket_sizes = xlr_board_info.bucket_sizes;
+ switch (sc->mac_type) {
+ case XLR_RGMII:
+ case XLR_SGMII:
+ case XLR_XAUI:
+ NLGE_WRITE(sc->base, R_GMAC_JFR0_BUCKET_SIZE,
+ bucket_sizes->bucket[MSGRNG_STNID_GMACJFR_0]);
+ NLGE_WRITE(sc->base, R_GMAC_RFR0_BUCKET_SIZE,
+ bucket_sizes->bucket[MSGRNG_STNID_GMACRFR_0]);
+ NLGE_WRITE(sc->base, R_GMAC_JFR1_BUCKET_SIZE,
+ bucket_sizes->bucket[MSGRNG_STNID_GMACJFR_1]);
+ NLGE_WRITE(sc->base, R_GMAC_RFR1_BUCKET_SIZE,
+ bucket_sizes->bucket[MSGRNG_STNID_GMACRFR_1]);
+
+ if (sc->mac_type == XLR_XAUI) {
+ NLGE_WRITE(sc->base, R_TXDATAFIFO0, (224 << 16));
+ }
+ break;
+
+ case XLR_XGMII:
+ NLGE_WRITE(sc->base, R_XGS_RFR_BUCKET_SIZE,
+ bucket_sizes->bucket[sc->rfrbucket]);
+
+ default:
+ break;
+ }
+}
+
+static void
+nlna_reset_ports(struct nlna_softc *sc, struct xlr_gmac_block_t *blk)
+{
+ xlr_reg_t *addr;
+ int i;
+ uint32_t rx_ctrl;
+
+ /* Refer Section 13.9.3 in the PRM for the reset sequence */
+
+ for (i = 0; i < sc->num_ports; i++) {
+ addr = xlr_io_mmio(blk->gmac_port[i].base_addr);
+
+ /* 1. Reset RxEnable in MAC_CONFIG */
+ switch (sc->mac_type) {
+ case XLR_RGMII:
+ case XLR_SGMII:
+ NLGE_UPDATE(addr, R_MAC_CONFIG_1, 0,
+ (1 << O_MAC_CONFIG_1__rxen));
+ break;
+ case XLR_XAUI:
+ case XLR_XGMII:
+ NLGE_UPDATE(addr, R_RX_CONTROL, 0,
+ (1 << O_RX_CONTROL__RxEnable));
+ break;
+ default:
+ printf("Error: Unsupported port_type=%d\n",
+ sc->mac_type);
+ }
+
+ /* 1.1 Wait for RxControl.RxHalt to be set */
+ do {
+ rx_ctrl = NLGE_READ(addr, R_RX_CONTROL);
+ } while (!(rx_ctrl & 0x2));
+
+ /* 2. Set the soft reset bit in RxControl */
+ NLGE_UPDATE(addr, R_RX_CONTROL, (1 << O_RX_CONTROL__SoftReset),
+ (1 << O_RX_CONTROL__SoftReset));
+
+ /* 2.1 Wait for RxControl.SoftResetDone to be set */
+ do {
+ rx_ctrl = NLGE_READ(addr, R_RX_CONTROL);
+ } while (!(rx_ctrl & 0x8));
+
+ /* 3. Clear the soft reset bit in RxControl */
+ NLGE_UPDATE(addr, R_RX_CONTROL, 0,
+ (1 << O_RX_CONTROL__SoftReset));
+
+ /* Turn off tx/rx on the port. */
+ NLGE_UPDATE(addr, R_RX_CONTROL, 0,
+ (1 << O_RX_CONTROL__RxEnable));
+ NLGE_UPDATE(addr, R_TX_CONTROL, 0,
+ (1 << O_TX_CONTROL__TxEnable));
+ }
+}
+
+static void
+nlna_disable_ports(struct nlna_softc *sc)
+{
+ int i;
+
+ for (i = 0; i < sc->num_ports; i++) {
+ if (sc->child_sc[i] != NULL)
+ nlge_port_disable(sc->child_sc[i]);
+ }
+}
+
+static void
+nlna_enable_ports(struct nlna_softc *sc)
+{
+ device_t nlge_dev, *devlist;
+ struct nlge_softc *port_sc;
+ int i, numdevs;
+
+ device_get_children(sc->nlna_dev, &devlist, &numdevs);
+ for (i = 0; i < numdevs; i++) {
+ nlge_dev = devlist[i];
+ if (nlge_dev == NULL)
+ continue;
+ port_sc = device_get_softc(nlge_dev);
+ if (port_sc->nlge_if->if_drv_flags & IFF_DRV_RUNNING)
+ nlge_port_enable(port_sc);
+ }
+ free(devlist, M_TEMP);
+}
+
+static void
+nlna_get_all_softc(device_t iodi_dev, struct nlna_softc **sc_vec,
+ uint32_t vec_sz)
+{
+ device_t na_dev;
+ int i;
+
+ for (i = 0; i < vec_sz; i++) {
+ sc_vec[i] = NULL;
+ na_dev = device_find_child(iodi_dev, "nlna", i);
+ if (na_dev != NULL)
+ sc_vec[i] = device_get_softc(na_dev);
+ }
+}
+
+static void
+nlge_port_disable(struct nlge_softc *sc)
+{
+ struct ifnet *ifp;
+ xlr_reg_t *base;
+ uint32_t rd;
+ int id, port_type;
+
+ id = sc->id;
+ port_type = sc->port_type;
+ base = sc->base;
+ ifp = sc->nlge_if;
+
+ NLGE_UPDATE(base, R_RX_CONTROL, 0x0, 1 << O_RX_CONTROL__RxEnable);
+ do {
+ rd = NLGE_READ(base, R_RX_CONTROL);
+ } while (!(rd & (1 << O_RX_CONTROL__RxHalt)));
+
+ NLGE_UPDATE(base, R_TX_CONTROL, 0, 1 << O_TX_CONTROL__TxEnable);
+ do {
+ rd = NLGE_READ(base, R_TX_CONTROL);
+ } while (!(rd & (1 << O_TX_CONTROL__TxIdle)));
+
+ switch (port_type) {
+ case XLR_RGMII:
+ case XLR_SGMII:
+ NLGE_UPDATE(base, R_MAC_CONFIG_1, 0,
+ ((1 << O_MAC_CONFIG_1__rxen) |
+ (1 << O_MAC_CONFIG_1__txen)));
+ break;
+ case XLR_XGMII:
+ case XLR_XAUI:
+ NLGE_UPDATE(base, R_XGMAC_CONFIG_1, 0,
+ ((1 << O_XGMAC_CONFIG_1__hsttfen) |
+ (1 << O_XGMAC_CONFIG_1__hstrfen)));
+ break;
+ default:
+ panic("Unknown MAC type on port %d\n", id);
+ }
+
+ if (ifp) {
+ ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE);
+ }
+}
+
+static void
+nlge_port_enable(struct nlge_softc *sc)
+{
+ struct xlr_gmac_port *self;
+ xlr_reg_t *base;
+
+ base = sc->base;
+ self = device_get_ivars(sc->nlge_dev);
+ if (xlr_board_info.is_xls && sc->port_type == XLR_RGMII)
+ NLGE_UPDATE(base, R_RX_CONTROL, (1 << O_RX_CONTROL__RGMII),
+ (1 << O_RX_CONTROL__RGMII));
+
+ NLGE_UPDATE(base, R_RX_CONTROL, (1 << O_RX_CONTROL__RxEnable),
+ (1 << O_RX_CONTROL__RxEnable));
+ NLGE_UPDATE(base, R_TX_CONTROL,
+ (1 << O_TX_CONTROL__TxEnable | RGE_TX_THRESHOLD_BYTES),
+ (1 << O_TX_CONTROL__TxEnable | 0x3fff));
+ switch (sc->port_type) {
+ case XLR_RGMII:
+ case XLR_SGMII:
+ NLGE_UPDATE(base, R_MAC_CONFIG_1,
+ ((1 << O_MAC_CONFIG_1__rxen) | (1 << O_MAC_CONFIG_1__txen)),
+ ((1 << O_MAC_CONFIG_1__rxen) | (1 << O_MAC_CONFIG_1__txen)));
+ break;
+ case XLR_XGMII:
+ case XLR_XAUI:
+ NLGE_UPDATE(base, R_XGMAC_CONFIG_1,
+ ((1 << O_XGMAC_CONFIG_1__hsttfen) | (1 << O_XGMAC_CONFIG_1__hstrfen)),
+ ((1 << O_XGMAC_CONFIG_1__hsttfen) | (1 << O_XGMAC_CONFIG_1__hstrfen)));
+ break;
+ default:
+ panic("Unknown MAC type on port %d\n", sc->id);
+ }
+}
+
+static void
+nlge_mac_set_rx_mode(struct nlge_softc *sc)
+{
+ uint32_t regval;
+
+ regval = NLGE_READ(sc->base, R_MAC_FILTER_CONFIG);
+
+ if (sc->if_flags & IFF_PROMISC) {
+ regval |= (1 << O_MAC_FILTER_CONFIG__BROADCAST_EN) |
+ (1 << O_MAC_FILTER_CONFIG__PAUSE_FRAME_EN) |
+ (1 << O_MAC_FILTER_CONFIG__ALL_MCAST_EN) |
+ (1 << O_MAC_FILTER_CONFIG__ALL_UCAST_EN);
+ } else {
+ regval &= ~((1 << O_MAC_FILTER_CONFIG__PAUSE_FRAME_EN) |
+ (1 << O_MAC_FILTER_CONFIG__ALL_UCAST_EN));
+ }
+
+ NLGE_WRITE(sc->base, R_MAC_FILTER_CONFIG, regval);
+}
+
+static void
+nlge_sgmii_init(struct nlge_softc *sc)
+{
+ xlr_reg_t *mmio_gpio;
+ int phy;
+
+ if (sc->port_type != XLR_SGMII)
+ return;
+
+ nlge_mii_write_internal(sc->serdes_addr, 26, 0, 0x6DB0);
+ nlge_mii_write_internal(sc->serdes_addr, 26, 1, 0xFFFF);
+ nlge_mii_write_internal(sc->serdes_addr, 26, 2, 0xB6D0);
+ nlge_mii_write_internal(sc->serdes_addr, 26, 3, 0x00FF);
+ nlge_mii_write_internal(sc->serdes_addr, 26, 4, 0x0000);
+ nlge_mii_write_internal(sc->serdes_addr, 26, 5, 0x0000);
+ nlge_mii_write_internal(sc->serdes_addr, 26, 6, 0x0005);
+ nlge_mii_write_internal(sc->serdes_addr, 26, 7, 0x0001);
+ nlge_mii_write_internal(sc->serdes_addr, 26, 8, 0x0000);
+ nlge_mii_write_internal(sc->serdes_addr, 26, 9, 0x0000);
+ nlge_mii_write_internal(sc->serdes_addr, 26,10, 0x0000);
+
+ /* program GPIO values for serdes init parameters */
+ DELAY(100);
+ mmio_gpio = xlr_io_mmio(XLR_IO_GPIO_OFFSET);
+ xlr_write_reg(mmio_gpio, 0x20, 0x7e6802);
+ xlr_write_reg(mmio_gpio, 0x10, 0x7104);
+ DELAY(100);
+
+ /*
+ * This kludge is needed to setup serdes (?) clock correctly on some
+ * XLS boards
+ */
+ if ((xlr_boot1_info.board_major_version == RMI_XLR_BOARD_ARIZONA_XI ||
+ xlr_boot1_info.board_major_version == RMI_XLR_BOARD_ARIZONA_XII) &&
+ xlr_boot1_info.board_minor_version == 4) {
+ /* use 125 Mhz instead of 156.25Mhz ref clock */
+ DELAY(100);
+ xlr_write_reg(mmio_gpio, 0x10, 0x7103);
+ xlr_write_reg(mmio_gpio, 0x21, 0x7103);
+ DELAY(100);
+ }
+
+ /* enable autoneg - more magic */
+ phy = sc->phy_addr % 4 + 27;
+ nlge_mii_write_internal(sc->pcs_addr, phy, 0, 0x1000);
+ DELAY(100000);
+ nlge_mii_write_internal(sc->pcs_addr, phy, 0, 0x0200);
+ DELAY(100000);
+}
+
+static void
+nlge_intr(void *arg)
+{
+ struct nlge_port_set *pset;
+ struct nlge_softc *sc;
+ struct nlge_softc *port_sc;
+ xlr_reg_t *base;
+ uint32_t intreg;
+ uint32_t intr_status;
+ int i;
+
+ sc = arg;
+ if (sc == NULL) {
+ printf("warning: No port registered for interrupt\n");
+ return;
+ }
+ base = sc->base;
+
+ intreg = NLGE_READ(base, R_INTREG);
+ if (intreg & (1 << O_INTREG__MDInt)) {
+ pset = sc->mdio_pset;
+ if (pset == NULL) {
+ printf("warning: No ports for MDIO interrupt\n");
+ return;
+ }
+ for (i = 0; i < pset->vec_sz; i++) {
+ port_sc = pset->port_vec[i];
+
+ if (port_sc == NULL)
+ continue;
+
+ /* Ack phy interrupt - clear on read*/
+ intr_status = nlge_mii_read_internal(port_sc->mii_base,
+ port_sc->phy_addr, 26);
+ PDEBUG("Phy_%d: int_status=0x%08x\n", port_sc->phy_addr,
+ intr_status);
+
+ if (!(intr_status & 0x8000)) {
+ /* no interrupt for this port */
+ continue;
+ }
+
+ if (intr_status & 0x2410) {
+ /* update link status for port */
+ nlge_gmac_config_speed(port_sc, 1);
+ } else {
+ printf("%s: Unsupported phy interrupt"
+ " (0x%08x)\n",
+ device_get_nameunit(port_sc->nlge_dev),
+ intr_status);
+ }
+ }
+ }
+
+ /* Clear the NA interrupt */
+ xlr_write_reg(base, R_INTREG, 0xffffffff);
+
+ return;
+}
+
+static int
+nlge_irq_init(struct nlge_softc *sc)
+{
+ struct resource irq_res;
+ struct nlna_softc *na_sc;
+ struct xlr_gmac_block_t *block_info;
+ device_t na_dev;
+ int ret;
+ int irq_num;
+
+ na_dev = device_get_parent(sc->nlge_dev);
+ block_info = device_get_ivars(na_dev);
+
+ irq_num = block_info->baseirq + sc->instance;
+ irq_res.__r_i = (struct resource_i *)(intptr_t) (irq_num);
+ ret = bus_setup_intr(sc->nlge_dev, &irq_res,
+ INTR_TYPE_NET | INTR_MPSAFE, NULL, nlge_intr, sc, NULL);
+ if (ret) {
+ nlge_detach(sc->nlge_dev);
+ device_printf(sc->nlge_dev, "couldn't set up irq: error=%d\n",
+ ret);
+ return (ENXIO);
+ }
+ PDEBUG("Setup intr for dev=%s, irq=%d\n",
+ device_get_nameunit(sc->nlge_dev), irq_num);
+
+ if (sc->instance == 0) {
+ na_sc = device_get_softc(na_dev);
+ sc->mdio_pset = &na_sc->mdio_set;
+ }
+ return (0);
+}
+
+static void
+nlge_irq_fini(struct nlge_softc *sc)
+{
+}
+
+static void
+nlge_hw_init(struct nlge_softc *sc)
+{
+ struct xlr_gmac_port *port_info;
+ xlr_reg_t *base;
+
+ base = sc->base;
+ port_info = device_get_ivars(sc->nlge_dev);
+ sc->tx_bucket_id = port_info->tx_bucket_id;
+
+ /* each packet buffer is 1536 bytes */
+ NLGE_WRITE(base, R_DESC_PACK_CTRL,
+ (1 << O_DESC_PACK_CTRL__MaxEntry) |
+#ifdef NLGE_HW_CHKSUM
+ (1 << O_DESC_PACK_CTRL__PrePadEnable) |
+#endif
+ (MAX_FRAME_SIZE << O_DESC_PACK_CTRL__RegularSize));
+ NLGE_WRITE(base, R_STATCTRL, ((1 << O_STATCTRL__Sten) |
+ (1 << O_STATCTRL__ClrCnt)));
+ NLGE_WRITE(base, R_L2ALLOCCTRL, 0xffffffff);
+ NLGE_WRITE(base, R_INTMASK, 0);
+ nlge_set_mac_addr(sc);
+ nlge_media_specific_init(sc);
+}
+
+static void
+nlge_sc_init(struct nlge_softc *sc, device_t dev,
+ struct xlr_gmac_port *port_info)
+{
+ memset(sc, 0, sizeof(*sc));
+ sc->nlge_dev = dev;
+ sc->id = device_get_unit(dev);
+ nlge_set_port_attribs(sc, port_info);
+}
+
+static void
+nlge_media_specific_init(struct nlge_softc *sc)
+{
+ struct mii_data *media;
+ struct bucket_size *bucket_sizes;
+
+ bucket_sizes = xlr_board_info.bucket_sizes;
+ switch (sc->port_type) {
+ case XLR_RGMII:
+ case XLR_SGMII:
+ case XLR_XAUI:
+ NLGE_UPDATE(sc->base, R_DESC_PACK_CTRL,
+ (BYTE_OFFSET << O_DESC_PACK_CTRL__ByteOffset),
+ (W_DESC_PACK_CTRL__ByteOffset <<
+ O_DESC_PACK_CTRL__ByteOffset));
+ NLGE_WRITE(sc->base, R_GMAC_TX0_BUCKET_SIZE + sc->instance,
+ bucket_sizes->bucket[sc->tx_bucket_id]);
+ if (sc->port_type != XLR_XAUI) {
+ nlge_gmac_config_speed(sc, 1);
+ if (sc->mii_bus) {
+ media = (struct mii_data *)device_get_softc(
+ sc->mii_bus);
+ }
+ }
+ break;
+
+ case XLR_XGMII:
+ NLGE_WRITE(sc->base, R_BYTEOFFSET0, 0x2);
+ NLGE_WRITE(sc->base, R_XGMACPADCALIBRATION, 0x30);
+ NLGE_WRITE(sc->base, R_XGS_TX0_BUCKET_SIZE,
+ bucket_sizes->bucket[sc->tx_bucket_id]);
+ break;
+ default:
+ break;
+ }
+}
+
+/*
+ * Read the MAC address from the XLR boot registers. All port addresses
+ * are identical except for the lowest octet.
+ */
+static void
+nlge_read_mac_addr(struct nlge_softc *sc)
+{
+ int i, j;
+
+ for (i = 0, j = 40; i < ETHER_ADDR_LEN && j >= 0; i++, j-= 8)
+ sc->dev_addr[i] = (xlr_boot1_info.mac_addr >> j) & 0xff;
+
+ sc->dev_addr[i - 1] += sc->id; /* last octet is port-specific */
+}
+
+/*
+ * Write the MAC address to the XLR MAC port. Also, set the address
+ * masks and MAC filter configuration.
+ */
+static void
+nlge_set_mac_addr(struct nlge_softc *sc)
+{
+ NLGE_WRITE(sc->base, R_MAC_ADDR0,
+ ((sc->dev_addr[5] << 24) | (sc->dev_addr[4] << 16) |
+ (sc->dev_addr[3] << 8) | (sc->dev_addr[2])));
+ NLGE_WRITE(sc->base, R_MAC_ADDR0 + 1,
+ ((sc->dev_addr[1] << 24) | (sc-> dev_addr[0] << 16)));
+
+ NLGE_WRITE(sc->base, R_MAC_ADDR_MASK2, 0xffffffff);
+ NLGE_WRITE(sc->base, R_MAC_ADDR_MASK2 + 1, 0xffffffff);
+ NLGE_WRITE(sc->base, R_MAC_ADDR_MASK3, 0xffffffff);
+ NLGE_WRITE(sc->base, R_MAC_ADDR_MASK3 + 1, 0xffffffff);
+
+ NLGE_WRITE(sc->base, R_MAC_FILTER_CONFIG,
+ (1 << O_MAC_FILTER_CONFIG__BROADCAST_EN) |
+ (1 << O_MAC_FILTER_CONFIG__ALL_MCAST_EN) |
+ (1 << O_MAC_FILTER_CONFIG__MAC_ADDR0_VALID));
+
+ if (sc->port_type == XLR_RGMII || sc->port_type == XLR_SGMII) {
+ NLGE_UPDATE(sc->base, R_IPG_IFG, MAC_B2B_IPG, 0x7f);
+ }
+}
+
+static int
+nlge_if_init(struct nlge_softc *sc)
+{
+ struct ifnet *ifp;
+ device_t dev;
+ int error;
+
+ error = 0;
+ dev = sc->nlge_dev;
+ NLGE_LOCK_INIT(sc, device_get_nameunit(dev));
+
+ ifp = sc->nlge_if = if_alloc(IFT_ETHER);
+ if (ifp == NULL) {
+ device_printf(dev, "can not if_alloc()\n");
+ error = ENOSPC;
+ goto fail;
+ }
+ ifp->if_softc = sc;
+ if_initname(ifp, device_get_name(dev), device_get_unit(dev));
+ ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
+ ifp->if_capabilities = 0;
+ ifp->if_capenable = ifp->if_capabilities;
+ ifp->if_ioctl = nlge_ioctl;
+ ifp->if_init = nlge_init;
+ ifp->if_hwassist = 0;
+ ifp->if_snd.ifq_drv_maxlen = RGE_TX_Q_SIZE;
+ IFQ_SET_MAXLEN(&ifp->if_snd, ifp->if_snd.ifq_drv_maxlen);
+ IFQ_SET_READY(&ifp->if_snd);
+
+ ifmedia_init(&sc->nlge_mii.mii_media, 0, nlge_mediachange,
+ nlge_mediastatus);
+ ifmedia_add(&sc->nlge_mii.mii_media, IFM_ETHER | IFM_AUTO, 0, NULL);
+ ifmedia_set(&sc->nlge_mii.mii_media, IFM_ETHER | IFM_AUTO);
+ sc->nlge_mii.mii_media.ifm_media = sc->nlge_mii.mii_media.ifm_cur->ifm_media;
+ nlge_read_mac_addr(sc);
+
+ ether_ifattach(ifp, sc->dev_addr);
+
+ /* override if_transmit : per ifnet(9), do it after if_attach */
+ ifp->if_transmit = nlge_tx;
+
+fail:
+ return (error);
+}
+
+static void
+nlge_mii_init(device_t dev, struct nlge_softc *sc)
+{
+ int error;
+
+ if (sc->port_type != XLR_XAUI && sc->port_type != XLR_XGMII) {
+ NLGE_WRITE(sc->mii_base, R_MII_MGMT_CONFIG, 0x07);
+ }
+ error = mii_attach(dev, &sc->mii_bus, sc->nlge_if, nlge_mediachange,
+ nlge_mediastatus, BMSR_DEFCAPMASK, sc->phy_addr, MII_OFFSET_ANY,
+ 0);
+ if (error) {
+ device_printf(dev, "attaching PHYs failed\n");
+ sc->mii_bus = NULL;
+ }
+ if (sc->mii_bus != NULL) {
+ /*
+ * Enable all MDIO interrupts in the phy. RX_ER bit seems to get
+ * set about every 1 sec in GigE mode, ignore it for now...
+ */
+ nlge_mii_write_internal(sc->mii_base, sc->phy_addr, 25,
+ 0xfffffffe);
+ }
+}
+
+/*
+ * Read a PHY register.
+ *
+ * Input parameters:
+ * mii_base - Base address of MII
+ * phyaddr - PHY's address
+ * regidx = index of register to read
+ *
+ * Return value:
+ * value read, or 0 if an error occurred.
+ */
+
+static int
+nlge_mii_read_internal(xlr_reg_t *mii_base, int phyaddr, int regidx)
+{
+ int i, val;
+
+ /* setup the phy reg to be used */
+ NLGE_WRITE(mii_base, R_MII_MGMT_ADDRESS,
+ (phyaddr << 8) | (regidx << 0));
+ /* Issue the read command */
+ NLGE_WRITE(mii_base, R_MII_MGMT_COMMAND,
+ (1 << O_MII_MGMT_COMMAND__rstat));
+
+ /* poll for the read cycle to complete */
+ for (i = 0; i < PHY_STATUS_RETRIES; i++) {
+ if (NLGE_READ(mii_base, R_MII_MGMT_INDICATORS) == 0)
+ break;
+ }
+
+ /* clear the read cycle */
+ NLGE_WRITE(mii_base, R_MII_MGMT_COMMAND, 0);
+
+ if (i == PHY_STATUS_RETRIES) {
+ return (0xffffffff);
+ }
+
+ val = NLGE_READ(mii_base, R_MII_MGMT_STATUS);
+
+ return (val);
+}
+
+/*
+ * Write a value to a PHY register.
+ *
+ * Input parameters:
+ * mii_base - Base address of MII
+ * phyaddr - PHY to use
+ * regidx - register within the PHY
+ * regval - data to write to register
+ *
+ * Return value:
+ * nothing
+ */
+static void
+nlge_mii_write_internal(xlr_reg_t *mii_base, int phyaddr, int regidx,
+ int regval)
+{
+ int i;
+
+ NLGE_WRITE(mii_base, R_MII_MGMT_ADDRESS,
+ (phyaddr << 8) | (regidx << 0));
+
+ /* Write the data which starts the write cycle */
+ NLGE_WRITE(mii_base, R_MII_MGMT_WRITE_DATA, regval);
+
+ /* poll for the write cycle to complete */
+ for (i = 0; i < PHY_STATUS_RETRIES; i++) {
+ if (NLGE_READ(mii_base, R_MII_MGMT_INDICATORS) == 0)
+ break;
+ }
+}
+
+/*
+ * Function to optimize the use of p2d descriptors for the given PDU.
+ * As it is on the fast-path (called during packet transmission), it
+ * described in more detail than the initialization functions.
+ *
+ * Input: mbuf chain (MC), pointer to fmn message
+ * Input constraints: None
+ * Output: FMN message to transmit the data in MC
+ * Return values: 0 - success
+ * 1 - MC cannot be handled (see Limitations below)
+ * 2 - MC cannot be handled presently (maybe worth re-trying)
+ * Other output: Number of entries filled in the FMN message
+ *
+ * Output structure/constraints:
+ * 1. Max 3 p2d's + 1 zero-len (ZL) p2d with virtual address of MC.
+ * 2. 3 p2d's + 1 p2p with max 14 p2d's (ZL p2d not required in this case).
+ * 3. Each p2d points to physically contiguous chunk of data (subject to
+ * entire MC requiring max 17 p2d's).
+ * Limitations:
+ * 1. MC's that require more than 17 p2d's are not handled.
+ * Benefits: MC's that require <= 3 p2d's avoid the overhead of allocating
+ * the p2p structure. Small packets (which typically give low
+ * performance) are expected to have a small MC that takes
+ * advantage of this.
+ */
+static int
+prepare_fmn_message(struct nlge_softc *sc, struct msgrng_msg *fmn_msg,
+ uint32_t *n_entries, struct mbuf *mbuf_chain, uint64_t fb_stn_id,
+ struct nlge_tx_desc **tx_desc)
+{
+ struct mbuf *m;
+ struct nlge_tx_desc *p2p;
+ uint64_t *cur_p2d;
+ uint64_t fbpaddr;
+ vm_offset_t buf;
+ vm_paddr_t paddr;
+ int msg_sz, p2p_sz, len, frag_sz;
+ /* Num entries per FMN msg is 4 for XLR/XLS */
+ const int FMN_SZ = sizeof(*fmn_msg) / sizeof(uint64_t);
+
+ msg_sz = p2p_sz = 0;
+ p2p = NULL;
+ cur_p2d = &fmn_msg->msg0;
+
+ for (m = mbuf_chain; m != NULL; m = m->m_next) {
+ buf = (vm_offset_t) m->m_data;
+ len = m->m_len;
+
+ while (len) {
+ if (msg_sz == (FMN_SZ - 1)) {
+ p2p = uma_zalloc(nl_tx_desc_zone, M_NOWAIT);
+ if (p2p == NULL) {
+ return (2);
+ }
+ /*
+ * Save the virtual address in the descriptor,
+ * it makes freeing easy.
+ */
+ p2p->frag[XLR_MAX_TX_FRAGS] =
+ (uint64_t)(vm_offset_t)p2p;
+ cur_p2d = &p2p->frag[0];
+ } else if (msg_sz == (FMN_SZ - 2 + XLR_MAX_TX_FRAGS)) {
+ uma_zfree(nl_tx_desc_zone, p2p);
+ return (1);
+ }
+ paddr = vtophys(buf);
+ frag_sz = PAGE_SIZE - (buf & PAGE_MASK);
+ if (len < frag_sz)
+ frag_sz = len;
+ *cur_p2d++ = (127ULL << 54) | ((uint64_t)frag_sz << 40)
+ | paddr;
+ msg_sz++;
+ if (p2p != NULL)
+ p2p_sz++;
+ len -= frag_sz;
+ buf += frag_sz;
+ }
+ }
+
+ if (msg_sz == 0) {
+ printf("Zero-length mbuf chain ??\n");
+ *n_entries = msg_sz ;
+ return (0);
+ }
+
+ /* set eop in most-recent p2d */
+ cur_p2d[-1] |= (1ULL << 63);
+
+#ifdef __mips_n64
+ /*
+ * On n64, we cannot store our mbuf pointer(64 bit) in the freeback
+ * message (40bit available), so we put the mbuf in m_nextpkt and
+ * use the physical addr of that in freeback message.
+ */
+ mbuf_chain->m_nextpkt = mbuf_chain;
+ fbpaddr = vtophys(&mbuf_chain->m_nextpkt);
+#else
+ /* Careful, don't sign extend when going to 64bit */
+ fbpaddr = (uint64_t)(uintptr_t)mbuf_chain;
+#endif
+ *cur_p2d = (1ULL << 63) | ((uint64_t)fb_stn_id << 54) | fbpaddr;
+ *tx_desc = p2p;
+
+ if (p2p != NULL) {
+ paddr = vtophys(p2p);
+ p2p_sz++;
+ fmn_msg->msg3 = (1ULL << 62) | ((uint64_t)fb_stn_id << 54) |
+ ((uint64_t)(p2p_sz * 8) << 40) | paddr;
+ *n_entries = FMN_SZ;
+ } else {
+ *n_entries = msg_sz + 1;
+ }
+
+ return (0);
+}
+
+static int
+send_fmn_msg_tx(struct nlge_softc *sc, struct msgrng_msg *msg,
+ uint32_t n_entries)
+{
+ uint32_t msgrng_flags;
+ int ret;
+ int i = 0;
+
+ do {
+ msgrng_flags = msgrng_access_enable();
+ ret = message_send(n_entries, MSGRNG_CODE_MAC,
+ sc->tx_bucket_id, msg);
+ msgrng_restore(msgrng_flags);
+ if (ret == 0)
+ return (0);
+ i++;
+ } while (i < 100000);
+
+ device_printf(sc->nlge_dev, "Too many credit fails in tx path\n");
+
+ return (1);
+}
+
+static void
+release_tx_desc(vm_paddr_t paddr)
+{
+ struct nlge_tx_desc *tx_desc;
+ uint32_t sr;
+ uint64_t vaddr;
+
+ paddr += (XLR_MAX_TX_FRAGS * sizeof(uint64_t));
+ sr = xlr_enable_kx();
+ vaddr = xlr_paddr_ld(paddr);
+ xlr_restore_kx(sr);
+
+ tx_desc = (struct nlge_tx_desc*)(intptr_t)vaddr;
+ uma_zfree(nl_tx_desc_zone, tx_desc);
+}
+
+static void *
+get_buf(void)
+{
+ struct mbuf *m_new;
+ uint64_t *md;
+#ifdef INVARIANTS
+ vm_paddr_t temp1, temp2;
+#endif
+
+ if ((m_new = m_getcl(M_NOWAIT, MT_DATA, M_PKTHDR)) == NULL)
+ return (NULL);
+ m_new->m_len = m_new->m_pkthdr.len = MCLBYTES;
+ m_adj(m_new, XLR_CACHELINE_SIZE - ((uintptr_t)m_new->m_data & 0x1f));
+ md = (uint64_t *)m_new->m_data;
+ md[0] = (intptr_t)m_new; /* Back Ptr */
+ md[1] = 0xf00bad;
+ m_adj(m_new, XLR_CACHELINE_SIZE);
+
+#ifdef INVARIANTS
+ temp1 = vtophys((vm_offset_t) m_new->m_data);
+ temp2 = vtophys((vm_offset_t) m_new->m_data + 1536);
+ if ((temp1 + 1536) != temp2)
+ panic("ALLOCED BUFFER IS NOT CONTIGUOUS\n");
+#endif
+
+ return ((void *)m_new->m_data);
+}
+
+static int
+nlge_gmac_config_speed(struct nlge_softc *sc, int quick)
+{
+ struct mii_data *md;
+ xlr_reg_t *mmio;
+ int bmsr, n_tries, max_tries;
+ int core_ctl[] = { 0x2, 0x1, 0x0, 0x1 };
+ int sgmii_speed[] = { SGMII_SPEED_10,
+ SGMII_SPEED_100,
+ SGMII_SPEED_1000,
+ SGMII_SPEED_100 }; /* default to 100Mbps */
+ char *speed_str[] = { "10",
+ "100",
+ "1000",
+ "unknown, defaulting to 100" };
+ int link_state = LINK_STATE_DOWN;
+
+ if (sc->port_type == XLR_XAUI || sc->port_type == XLR_XGMII)
+ return 0;
+
+ md = NULL;
+ mmio = sc->base;
+ if (sc->mii_base != NULL) {
+ max_tries = (quick == 1) ? 100 : 4000;
+ bmsr = 0;
+ for (n_tries = 0; n_tries < max_tries; n_tries++) {
+ bmsr = nlge_mii_read_internal(sc->mii_base,
+ sc->phy_addr, MII_BMSR);
+ if ((bmsr & BMSR_ACOMP) && (bmsr & BMSR_LINK))
+ break; /* Auto-negotiation is complete
+ and link is up */
+ DELAY(1000);
+ }
+ bmsr &= BMSR_LINK;
+ sc->link = (bmsr == 0) ? xlr_mac_link_down : xlr_mac_link_up;
+ sc->speed = nlge_mii_read_internal(sc->mii_base, sc->phy_addr, 28);
+ sc->speed = (sc->speed >> 3) & 0x03;
+ if (sc->link == xlr_mac_link_up) {
+ link_state = LINK_STATE_UP;
+ nlge_sgmii_init(sc);
+ }
+ if (sc->mii_bus)
+ md = (struct mii_data *)device_get_softc(sc->mii_bus);
+ }
+
+ if (sc->port_type != XLR_RGMII)
+ NLGE_WRITE(mmio, R_INTERFACE_CONTROL, sgmii_speed[sc->speed]);
+ if (sc->speed == xlr_mac_speed_10 || sc->speed == xlr_mac_speed_100 ||
+ sc->speed == xlr_mac_speed_rsvd) {
+ NLGE_WRITE(mmio, R_MAC_CONFIG_2, 0x7117);
+ } else if (sc->speed == xlr_mac_speed_1000) {
+ NLGE_WRITE(mmio, R_MAC_CONFIG_2, 0x7217);
+ if (md != NULL) {
+ ifmedia_set(&md->mii_media, IFM_MAKEWORD(IFM_ETHER,
+ IFM_1000_T, IFM_FDX, md->mii_instance));
+ }
+ }
+ NLGE_WRITE(mmio, R_CORECONTROL, core_ctl[sc->speed]);
+ if_link_state_change(sc->nlge_if, link_state);
+ printf("%s: [%sMbps]\n", device_get_nameunit(sc->nlge_dev),
+ speed_str[sc->speed]);
+
+ return (0);
+}
+
+/*
+ * This function is called for each port that was added to the device tree
+ * and it initializes the following port attributes:
+ * - type
+ * - base (base address to access port-specific registers)
+ * - mii_base
+ * - phy_addr
+ */
+static void
+nlge_set_port_attribs(struct nlge_softc *sc,
+ struct xlr_gmac_port *port_info)
+{
+ sc->instance = port_info->instance % 4; /* TBD: will not work for SPI-4 */
+ sc->port_type = port_info->type;
+ sc->base = xlr_io_mmio(port_info->base_addr);
+ sc->mii_base = xlr_io_mmio(port_info->mii_addr);
+ if (port_info->pcs_addr != 0)
+ sc->pcs_addr = xlr_io_mmio(port_info->pcs_addr);
+ if (port_info->serdes_addr != 0)
+ sc->serdes_addr = xlr_io_mmio(port_info->serdes_addr);
+ sc->phy_addr = port_info->phy_addr;
+
+ PDEBUG("Port%d: base=%p, mii_base=%p, phy_addr=%d\n", sc->id, sc->base,
+ sc->mii_base, sc->phy_addr);
+}
+
+/* ------------------------------------------------------------------------ */
+
+/* Debug dump functions */
+
+#ifdef DEBUG
+
+static void
+dump_reg(xlr_reg_t *base, uint32_t offset, char *name)
+{
+ int val;
+
+ val = NLGE_READ(base, offset);
+ printf("%-30s: 0x%8x 0x%8x\n", name, offset, val);
+}
+
+#define STRINGIFY(x) #x
+
+static void
+dump_na_registers(xlr_reg_t *base_addr, int port_id)
+{
+ PDEBUG("Register dump for NA (of port=%d)\n", port_id);
+ dump_reg(base_addr, R_PARSERCONFIGREG, STRINGIFY(R_PARSERCONFIGREG));
+ PDEBUG("Tx bucket sizes\n");
+ dump_reg(base_addr, R_GMAC_JFR0_BUCKET_SIZE,
+ STRINGIFY(R_GMAC_JFR0_BUCKET_SIZE));
+ dump_reg(base_addr, R_GMAC_RFR0_BUCKET_SIZE,
+ STRINGIFY(R_GMAC_RFR0_BUCKET_SIZE));
+ dump_reg(base_addr, R_GMAC_TX0_BUCKET_SIZE,
+ STRINGIFY(R_GMAC_TX0_BUCKET_SIZE));
+ dump_reg(base_addr, R_GMAC_TX1_BUCKET_SIZE,
+ STRINGIFY(R_GMAC_TX1_BUCKET_SIZE));
+ dump_reg(base_addr, R_GMAC_TX2_BUCKET_SIZE,
+ STRINGIFY(R_GMAC_TX2_BUCKET_SIZE));
+ dump_reg(base_addr, R_GMAC_TX3_BUCKET_SIZE,
+ STRINGIFY(R_GMAC_TX3_BUCKET_SIZE));
+ dump_reg(base_addr, R_GMAC_JFR1_BUCKET_SIZE,
+ STRINGIFY(R_GMAC_JFR1_BUCKET_SIZE));
+ dump_reg(base_addr, R_GMAC_RFR1_BUCKET_SIZE,
+ STRINGIFY(R_GMAC_RFR1_BUCKET_SIZE));
+ dump_reg(base_addr, R_TXDATAFIFO0, STRINGIFY(R_TXDATAFIFO0));
+ dump_reg(base_addr, R_TXDATAFIFO1, STRINGIFY(R_TXDATAFIFO1));
+}
+
+static void
+dump_gmac_registers(struct nlge_softc *sc)
+{
+ xlr_reg_t *base_addr = sc->base;
+ int port_id = sc->instance;
+
+ PDEBUG("Register dump for port=%d\n", port_id);
+ if (sc->port_type == XLR_RGMII || sc->port_type == XLR_SGMII) {
+ dump_reg(base_addr, R_MAC_CONFIG_1, STRINGIFY(R_MAC_CONFIG_1));
+ dump_reg(base_addr, R_MAC_CONFIG_2, STRINGIFY(R_MAC_CONFIG_2));
+ dump_reg(base_addr, R_IPG_IFG, STRINGIFY(R_IPG_IFG));
+ dump_reg(base_addr, R_HALF_DUPLEX, STRINGIFY(R_HALF_DUPLEX));
+ dump_reg(base_addr, R_MAXIMUM_FRAME_LENGTH,
+ STRINGIFY(R_MAXIMUM_FRAME_LENGTH));
+ dump_reg(base_addr, R_TEST, STRINGIFY(R_TEST));
+ dump_reg(base_addr, R_MII_MGMT_CONFIG,
+ STRINGIFY(R_MII_MGMT_CONFIG));
+ dump_reg(base_addr, R_MII_MGMT_COMMAND,
+ STRINGIFY(R_MII_MGMT_COMMAND));
+ dump_reg(base_addr, R_MII_MGMT_ADDRESS,
+ STRINGIFY(R_MII_MGMT_ADDRESS));
+ dump_reg(base_addr, R_MII_MGMT_WRITE_DATA,
+ STRINGIFY(R_MII_MGMT_WRITE_DATA));
+ dump_reg(base_addr, R_MII_MGMT_STATUS,
+ STRINGIFY(R_MII_MGMT_STATUS));
+ dump_reg(base_addr, R_MII_MGMT_INDICATORS,
+ STRINGIFY(R_MII_MGMT_INDICATORS));
+ dump_reg(base_addr, R_INTERFACE_CONTROL,
+ STRINGIFY(R_INTERFACE_CONTROL));
+ dump_reg(base_addr, R_INTERFACE_STATUS,
+ STRINGIFY(R_INTERFACE_STATUS));
+ } else if (sc->port_type == XLR_XAUI || sc->port_type == XLR_XGMII) {
+ dump_reg(base_addr, R_XGMAC_CONFIG_0,
+ STRINGIFY(R_XGMAC_CONFIG_0));
+ dump_reg(base_addr, R_XGMAC_CONFIG_1,
+ STRINGIFY(R_XGMAC_CONFIG_1));
+ dump_reg(base_addr, R_XGMAC_CONFIG_2,
+ STRINGIFY(R_XGMAC_CONFIG_2));
+ dump_reg(base_addr, R_XGMAC_CONFIG_3,
+ STRINGIFY(R_XGMAC_CONFIG_3));
+ dump_reg(base_addr, R_XGMAC_STATION_ADDRESS_LS,
+ STRINGIFY(R_XGMAC_STATION_ADDRESS_LS));
+ dump_reg(base_addr, R_XGMAC_STATION_ADDRESS_MS,
+ STRINGIFY(R_XGMAC_STATION_ADDRESS_MS));
+ dump_reg(base_addr, R_XGMAC_MAX_FRAME_LEN,
+ STRINGIFY(R_XGMAC_MAX_FRAME_LEN));
+ dump_reg(base_addr, R_XGMAC_REV_LEVEL,
+ STRINGIFY(R_XGMAC_REV_LEVEL));
+ dump_reg(base_addr, R_XGMAC_MIIM_COMMAND,
+ STRINGIFY(R_XGMAC_MIIM_COMMAND));
+ dump_reg(base_addr, R_XGMAC_MIIM_FILED,
+ STRINGIFY(R_XGMAC_MIIM_FILED));
+ dump_reg(base_addr, R_XGMAC_MIIM_CONFIG,
+ STRINGIFY(R_XGMAC_MIIM_CONFIG));
+ dump_reg(base_addr, R_XGMAC_MIIM_LINK_FAIL_VECTOR,
+ STRINGIFY(R_XGMAC_MIIM_LINK_FAIL_VECTOR));
+ dump_reg(base_addr, R_XGMAC_MIIM_INDICATOR,
+ STRINGIFY(R_XGMAC_MIIM_INDICATOR));
+ }
+
+ dump_reg(base_addr, R_MAC_ADDR0, STRINGIFY(R_MAC_ADDR0));
+ dump_reg(base_addr, R_MAC_ADDR0 + 1, STRINGIFY(R_MAC_ADDR0+1));
+ dump_reg(base_addr, R_MAC_ADDR1, STRINGIFY(R_MAC_ADDR1));
+ dump_reg(base_addr, R_MAC_ADDR2, STRINGIFY(R_MAC_ADDR2));
+ dump_reg(base_addr, R_MAC_ADDR3, STRINGIFY(R_MAC_ADDR3));
+ dump_reg(base_addr, R_MAC_ADDR_MASK2, STRINGIFY(R_MAC_ADDR_MASK2));
+ dump_reg(base_addr, R_MAC_ADDR_MASK3, STRINGIFY(R_MAC_ADDR_MASK3));
+ dump_reg(base_addr, R_MAC_FILTER_CONFIG, STRINGIFY(R_MAC_FILTER_CONFIG));
+ dump_reg(base_addr, R_TX_CONTROL, STRINGIFY(R_TX_CONTROL));
+ dump_reg(base_addr, R_RX_CONTROL, STRINGIFY(R_RX_CONTROL));
+ dump_reg(base_addr, R_DESC_PACK_CTRL, STRINGIFY(R_DESC_PACK_CTRL));
+ dump_reg(base_addr, R_STATCTRL, STRINGIFY(R_STATCTRL));
+ dump_reg(base_addr, R_L2ALLOCCTRL, STRINGIFY(R_L2ALLOCCTRL));
+ dump_reg(base_addr, R_INTMASK, STRINGIFY(R_INTMASK));
+ dump_reg(base_addr, R_INTREG, STRINGIFY(R_INTREG));
+ dump_reg(base_addr, R_TXRETRY, STRINGIFY(R_TXRETRY));
+ dump_reg(base_addr, R_CORECONTROL, STRINGIFY(R_CORECONTROL));
+ dump_reg(base_addr, R_BYTEOFFSET0, STRINGIFY(R_BYTEOFFSET0));
+ dump_reg(base_addr, R_BYTEOFFSET1, STRINGIFY(R_BYTEOFFSET1));
+ dump_reg(base_addr, R_L2TYPE_0, STRINGIFY(R_L2TYPE_0));
+ dump_na_registers(base_addr, port_id);
+}
+
+static void
+dump_fmn_cpu_credits_for_gmac(struct xlr_board_info *board, int gmac_id)
+{
+ struct stn_cc *cc;
+ int gmac_bucket_ids[] = { 97, 98, 99, 100, 101, 103 };
+ int j, k, r, c;
+ int n_gmac_buckets;
+
+ n_gmac_buckets = sizeof (gmac_bucket_ids) / sizeof (gmac_bucket_ids[0]);
+ for (j = 0; j < 8; j++) { // for each cpu
+ cc = board->credit_configs[j];
+ printf("Credits for Station CPU_%d ---> GMAC buckets (tx path)\n", j);
+ for (k = 0; k < n_gmac_buckets; k++) {
+ r = gmac_bucket_ids[k] / 8;
+ c = gmac_bucket_ids[k] % 8;
+ printf (" --> gmac%d_bucket_%-3d: credits=%d\n", gmac_id,
+ gmac_bucket_ids[k], cc->counters[r][c]);
+ }
+ }
+}
+
+static void
+dump_fmn_gmac_credits(struct xlr_board_info *board, int gmac_id)
+{
+ struct stn_cc *cc;
+ int j, k;
+
+ cc = board->gmac_block[gmac_id].credit_config;
+ printf("Credits for Station: GMAC_%d ---> CPU buckets (rx path)\n", gmac_id);
+ for (j = 0; j < 8; j++) { // for each cpu
+ printf(" ---> cpu_%d\n", j);
+ for (k = 0; k < 8; k++) { // for each bucket in cpu
+ printf(" ---> bucket_%d: credits=%d\n", j * 8 + k,
+ cc->counters[j][k]);
+ }
+ }
+}
+
+static void
+dump_board_info(struct xlr_board_info *board)
+{
+ struct xlr_gmac_block_t *gm;
+ int i, k;
+
+ printf("cpu=%x ", xlr_revision());
+ printf("board_version: major=%llx, minor=%llx\n",
+ xlr_boot1_info.board_major_version,
+ xlr_boot1_info.board_minor_version);
+ printf("is_xls=%d, nr_cpus=%d, usb=%s, cfi=%s, ata=%s\npci_irq=%d,"
+ "gmac_ports=%d\n", board->is_xls, board->nr_cpus,
+ board->usb ? "Yes" : "No", board->cfi ? "Yes": "No",
+ board->ata ? "Yes" : "No", board->pci_irq, board->gmacports);
+ printf("FMN: Core-station bucket sizes\n");
+ for (i = 0; i < 128; i++) {
+ if (i && ((i % 16) == 0))
+ printf("\n");
+ printf ("b[%d] = %d ", i, board->bucket_sizes->bucket[i]);
+ }
+ printf("\n");
+ for (i = 0; i < 3; i++) {
+ gm = &board->gmac_block[i];
+ printf("RNA_%d: type=%d, enabled=%s, mode=%d, station_id=%d,"
+ "station_txbase=%d, station_rfr=%d ", i, gm->type,
+ gm->enabled ? "Yes" : "No", gm->mode, gm->station_id,
+ gm->station_txbase, gm->station_rfr);
+ printf("n_ports=%d, baseaddr=%p, baseirq=%d, baseinst=%d\n",
+ gm->num_ports, (xlr_reg_t *)gm->baseaddr, gm->baseirq,
+ gm->baseinst);
+ }
+ for (k = 0; k < 3; k++) { // for each NA
+ dump_fmn_cpu_credits_for_gmac(board, k);
+ dump_fmn_gmac_credits(board, k);
+ }
+}
+
+static void
+dump_mac_stats(struct nlge_softc *sc)
+{
+ xlr_reg_t *addr;
+ uint32_t pkts_tx, pkts_rx;
+
+ addr = sc->base;
+ pkts_rx = NLGE_READ(sc->base, R_RPKT);
+ pkts_tx = NLGE_READ(sc->base, R_TPKT);
+
+ printf("[nlge_%d mac stats]: pkts_tx=%u, pkts_rx=%u\n", sc->id, pkts_tx,
+ pkts_rx);
+ if (pkts_rx > 0) {
+ uint32_t r;
+
+ /* dump all rx counters. we need this because pkts_rx includes
+ bad packets. */
+ for (r = R_RFCS; r <= R_ROVR; r++)
+ printf("[nlge_%d mac stats]: [0x%x]=%u\n", sc->id, r,
+ NLGE_READ(sc->base, r));
+ }
+ if (pkts_tx > 0) {
+ uint32_t r;
+
+ /* dump all tx counters. might be useful for debugging. */
+ for (r = R_TMCA; r <= R_TFRG; r++) {
+ if ((r == (R_TNCL + 1)) || (r == (R_TNCL + 2)))
+ continue;
+ printf("[nlge_%d mac stats]: [0x%x]=%u\n", sc->id, r,
+ NLGE_READ(sc->base, r));
+ }
+ }
+
+}
+
+static void
+dump_mii_regs(struct nlge_softc *sc)
+{
+ uint32_t mii_regs[] = { 0x0, 0x1, 0x2, 0x3, 0x4, 0x5, 0x6, 0x7,
+ 0x8, 0x9, 0xa, 0xf, 0x10, 0x11, 0x12, 0x13,
+ 0x14, 0x15, 0x16, 0x17, 0x18, 0x19, 0x1a, 0x1b,
+ 0x1c, 0x1d, 0x1e};
+ int i, n_regs;
+
+ if (sc->mii_base == NULL || sc->mii_bus == NULL)
+ return;
+
+ n_regs = sizeof (mii_regs) / sizeof (mii_regs[0]);
+ for (i = 0; i < n_regs; i++) {
+ printf("[mii_0x%x] = %x\n", mii_regs[i],
+ nlge_mii_read_internal(sc->mii_base, sc->phy_addr,
+ mii_regs[i]));
+ }
+}
+
+static void
+dump_ifmedia(struct ifmedia *ifm)
+{
+ printf("ifm_mask=%08x, ifm_media=%08x, cur=%p\n", ifm->ifm_mask,
+ ifm->ifm_media, ifm->ifm_cur);
+ if (ifm->ifm_cur != NULL) {
+ printf("Cur attribs: ifmedia_entry.ifm_media=%08x,"
+ " ifmedia_entry.ifm_data=%08x\n", ifm->ifm_cur->ifm_media,
+ ifm->ifm_cur->ifm_data);
+ }
+}
+
+static void
+dump_mii_data(struct mii_data *mii)
+{
+ dump_ifmedia(&mii->mii_media);
+ printf("ifp=%p, mii_instance=%d, mii_media_status=%08x,"
+ " mii_media_active=%08x\n", mii->mii_ifp, mii->mii_instance,
+ mii->mii_media_status, mii->mii_media_active);
+}
+
+static void
+dump_pcs_regs(struct nlge_softc *sc, int phy)
+{
+ int i, val;
+
+ printf("PCS regs from %p for phy=%d\n", sc->pcs_addr, phy);
+ for (i = 0; i < 18; i++) {
+ if (i == 2 || i == 3 || (i >= 9 && i <= 14))
+ continue;
+ val = nlge_mii_read_internal(sc->pcs_addr, phy, i);
+ printf("PHY:%d pcs[0x%x] is 0x%x\n", phy, i, val);
+ }
+}
+#endif
Property changes on: trunk/sys/mips/rmi/dev/nlge/if_nlge.c
___________________________________________________________________
Added: svn:eol-style
## -0,0 +1 ##
+native
\ No newline at end of property
Added: svn:keywords
## -0,0 +1 ##
+MidnightBSD=%H
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+text/plain
\ No newline at end of property
Added: trunk/sys/mips/rmi/dev/nlge/if_nlge.h
===================================================================
--- trunk/sys/mips/rmi/dev/nlge/if_nlge.h (rev 0)
+++ trunk/sys/mips/rmi/dev/nlge/if_nlge.h 2018-05-26 21:55:02 UTC (rev 9987)
@@ -0,0 +1,1183 @@
+/* $MidnightBSD$ */
+/*-
+ * Copyright (c) 2003-2009 RMI Corporation
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * 3. Neither the name of RMI Corporation, nor the names of its contributors,
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ * $FreeBSD: stable/10/sys/mips/rmi/dev/nlge/if_nlge.h 215939 2010-11-27 13:35:19Z jchandra $
+ *
+ * RMI_BSD
+ */
+
+/* #define MAC_SPLIT_MODE */
+
+#define MAC_SPACING 0x400
+#define XGMAC_SPACING 0x400
+
+/* PE-MCXMAC register and bit field definitions */
+#define R_MAC_CONFIG_1 0x00
+#define O_MAC_CONFIG_1__srst 31
+#define O_MAC_CONFIG_1__simr 30
+#define O_MAC_CONFIG_1__hrrmc 18
+#define W_MAC_CONFIG_1__hrtmc 2
+#define O_MAC_CONFIG_1__hrrfn 16
+#define W_MAC_CONFIG_1__hrtfn 2
+#define O_MAC_CONFIG_1__intlb 8
+#define O_MAC_CONFIG_1__rxfc 5
+#define O_MAC_CONFIG_1__txfc 4
+#define O_MAC_CONFIG_1__srxen 3
+#define O_MAC_CONFIG_1__rxen 2
+#define O_MAC_CONFIG_1__stxen 1
+#define O_MAC_CONFIG_1__txen 0
+#define R_MAC_CONFIG_2 0x01
+#define O_MAC_CONFIG_2__prlen 12
+#define W_MAC_CONFIG_2__prlen 4
+#define O_MAC_CONFIG_2__speed 8
+#define W_MAC_CONFIG_2__speed 2
+#define O_MAC_CONFIG_2__hugen 5
+#define O_MAC_CONFIG_2__flchk 4
+#define O_MAC_CONFIG_2__crce 1
+#define O_MAC_CONFIG_2__fulld 0
+#define R_IPG_IFG 0x02
+#define O_IPG_IFG__ipgr1 24
+#define W_IPG_IFG__ipgr1 7
+#define O_IPG_IFG__ipgr2 16
+#define W_IPG_IFG__ipgr2 7
+#define O_IPG_IFG__mifg 8
+#define W_IPG_IFG__mifg 8
+#define O_IPG_IFG__ipgt 0
+#define W_IPG_IFG__ipgt 7
+#define R_HALF_DUPLEX 0x03
+#define O_HALF_DUPLEX__abebt 24
+#define W_HALF_DUPLEX__abebt 4
+#define O_HALF_DUPLEX__abebe 19
+#define O_HALF_DUPLEX__bpnb 18
+#define O_HALF_DUPLEX__nobo 17
+#define O_HALF_DUPLEX__edxsdfr 16
+#define O_HALF_DUPLEX__retry 12
+#define W_HALF_DUPLEX__retry 4
+#define O_HALF_DUPLEX__lcol 0
+#define W_HALF_DUPLEX__lcol 10
+#define R_MAXIMUM_FRAME_LENGTH 0x04
+#define O_MAXIMUM_FRAME_LENGTH__maxf 0
+#define W_MAXIMUM_FRAME_LENGTH__maxf 16
+#define R_TEST 0x07
+#define O_TEST__mbof 3
+#define O_TEST__rthdf 2
+#define O_TEST__tpause 1
+#define O_TEST__sstct 0
+#define R_MII_MGMT_CONFIG 0x08
+#define O_MII_MGMT_CONFIG__scinc 5
+#define O_MII_MGMT_CONFIG__spre 4
+#define O_MII_MGMT_CONFIG__clks 3
+#define W_MII_MGMT_CONFIG__clks 3
+#define R_MII_MGMT_COMMAND 0x09
+#define O_MII_MGMT_COMMAND__scan 1
+#define O_MII_MGMT_COMMAND__rstat 0
+#define R_MII_MGMT_ADDRESS 0x0A
+#define O_MII_MGMT_ADDRESS__fiad 8
+#define W_MII_MGMT_ADDRESS__fiad 5
+#define O_MII_MGMT_ADDRESS__fgad 5
+#define W_MII_MGMT_ADDRESS__fgad 0
+#define R_MII_MGMT_WRITE_DATA 0x0B
+#define O_MII_MGMT_WRITE_DATA__ctld 0
+#define W_MII_MGMT_WRITE_DATA__ctld 16
+#define R_MII_MGMT_STATUS 0x0C
+#define R_MII_MGMT_INDICATORS 0x0D
+#define O_MII_MGMT_INDICATORS__nvalid 2
+#define O_MII_MGMT_INDICATORS__scan 1
+#define O_MII_MGMT_INDICATORS__busy 0
+#define R_INTERFACE_CONTROL 0x0E
+#define O_INTERFACE_CONTROL__hrstint 31
+#define O_INTERFACE_CONTROL__tbimode 27
+#define O_INTERFACE_CONTROL__ghdmode 26
+#define O_INTERFACE_CONTROL__lhdmode 25
+#define O_INTERFACE_CONTROL__phymod 24
+#define O_INTERFACE_CONTROL__hrrmi 23
+#define O_INTERFACE_CONTROL__rspd 16
+#define O_INTERFACE_CONTROL__hr100 15
+#define O_INTERFACE_CONTROL__frcq 10
+#define O_INTERFACE_CONTROL__nocfr 9
+#define O_INTERFACE_CONTROL__dlfct 8
+#define O_INTERFACE_CONTROL__enjab 0
+#define R_INTERFACE_STATUS 0x0F
+#define O_INTERFACE_STATUS__xsdfr 9
+#define O_INTERFACE_STATUS__ssrr 8
+#define W_INTERFACE_STATUS__ssrr 5
+#define O_INTERFACE_STATUS__miilf 3
+#define O_INTERFACE_STATUS__locar 2
+#define O_INTERFACE_STATUS__sqerr 1
+#define O_INTERFACE_STATUS__jabber 0
+#define R_STATION_ADDRESS_LS 0x10
+#define R_STATION_ADDRESS_MS 0x11
+
+/* A-XGMAC register and bit field definitions */
+#define R_XGMAC_CONFIG_0 0x00
+#define O_XGMAC_CONFIG_0__hstmacrst 31
+#define O_XGMAC_CONFIG_0__hstrstrctl 23
+#define O_XGMAC_CONFIG_0__hstrstrfn 22
+#define O_XGMAC_CONFIG_0__hstrsttctl 18
+#define O_XGMAC_CONFIG_0__hstrsttfn 17
+#define O_XGMAC_CONFIG_0__hstrstmiim 16
+#define O_XGMAC_CONFIG_0__hstloopback 8
+#define R_XGMAC_CONFIG_1 0x01
+#define O_XGMAC_CONFIG_1__hsttctlen 31
+#define O_XGMAC_CONFIG_1__hsttfen 30
+#define O_XGMAC_CONFIG_1__hstrctlen 29
+#define O_XGMAC_CONFIG_1__hstrfen 28
+#define O_XGMAC_CONFIG_1__tfen 26
+#define O_XGMAC_CONFIG_1__rfen 24
+#define O_XGMAC_CONFIG_1__hstrctlshrtp 12
+#define O_XGMAC_CONFIG_1__hstdlyfcstx 10
+#define W_XGMAC_CONFIG_1__hstdlyfcstx 2
+#define O_XGMAC_CONFIG_1__hstdlyfcsrx 8
+#define W_XGMAC_CONFIG_1__hstdlyfcsrx 2
+#define O_XGMAC_CONFIG_1__hstppen 7
+#define O_XGMAC_CONFIG_1__hstbytswp 6
+#define O_XGMAC_CONFIG_1__hstdrplt64 5
+#define O_XGMAC_CONFIG_1__hstprmscrx 4
+#define O_XGMAC_CONFIG_1__hstlenchk 3
+#define O_XGMAC_CONFIG_1__hstgenfcs 2
+#define O_XGMAC_CONFIG_1__hstpadmode 0
+#define W_XGMAC_CONFIG_1__hstpadmode 2
+#define R_XGMAC_CONFIG_2 0x02
+#define O_XGMAC_CONFIG_2__hsttctlfrcp 31
+#define O_XGMAC_CONFIG_2__hstmlnkflth 27
+#define O_XGMAC_CONFIG_2__hstalnkflth 26
+#define O_XGMAC_CONFIG_2__rflnkflt 24
+#define W_XGMAC_CONFIG_2__rflnkflt 2
+#define O_XGMAC_CONFIG_2__hstipgextmod 16
+#define W_XGMAC_CONFIG_2__hstipgextmod 5
+#define O_XGMAC_CONFIG_2__hstrctlfrcp 15
+#define O_XGMAC_CONFIG_2__hstipgexten 5
+#define O_XGMAC_CONFIG_2__hstmipgext 0
+#define W_XGMAC_CONFIG_2__hstmipgext 5
+#define R_XGMAC_CONFIG_3 0x03
+#define O_XGMAC_CONFIG_3__hstfltrfrm 31
+#define W_XGMAC_CONFIG_3__hstfltrfrm 16
+#define O_XGMAC_CONFIG_3__hstfltrfrmdc 15
+#define W_XGMAC_CONFIG_3__hstfltrfrmdc 16
+#define R_XGMAC_STATION_ADDRESS_LS 0x04
+#define O_XGMAC_STATION_ADDRESS_LS__hstmacadr0 0
+#define W_XGMAC_STATION_ADDRESS_LS__hstmacadr0 32
+#define R_XGMAC_STATION_ADDRESS_MS 0x05
+#define R_XGMAC_MAX_FRAME_LEN 0x08
+#define O_XGMAC_MAX_FRAME_LEN__hstmxfrmwctx 16
+#define W_XGMAC_MAX_FRAME_LEN__hstmxfrmwctx 14
+#define O_XGMAC_MAX_FRAME_LEN__hstmxfrmbcrx 0
+#define W_XGMAC_MAX_FRAME_LEN__hstmxfrmbcrx 16
+#define R_XGMAC_REV_LEVEL 0x0B
+#define O_XGMAC_REV_LEVEL__revlvl 0
+#define W_XGMAC_REV_LEVEL__revlvl 15
+#define R_XGMAC_MIIM_COMMAND 0x10
+#define O_XGMAC_MIIM_COMMAND__hstldcmd 3
+#define O_XGMAC_MIIM_COMMAND__hstmiimcmd 0
+#define W_XGMAC_MIIM_COMMAND__hstmiimcmd 3
+#define R_XGMAC_MIIM_FILED 0x11
+#define O_XGMAC_MIIM_FILED__hststfield 30
+#define W_XGMAC_MIIM_FILED__hststfield 2
+#define O_XGMAC_MIIM_FILED__hstopfield 28
+#define W_XGMAC_MIIM_FILED__hstopfield 2
+#define O_XGMAC_MIIM_FILED__hstphyadx 23
+#define W_XGMAC_MIIM_FILED__hstphyadx 5
+#define O_XGMAC_MIIM_FILED__hstregadx 18
+#define W_XGMAC_MIIM_FILED__hstregadx 5
+#define O_XGMAC_MIIM_FILED__hsttafield 16
+#define W_XGMAC_MIIM_FILED__hsttafield 2
+#define O_XGMAC_MIIM_FILED__miimrddat 0
+#define W_XGMAC_MIIM_FILED__miimrddat 16
+#define R_XGMAC_MIIM_CONFIG 0x12
+#define O_XGMAC_MIIM_CONFIG__hstnopram 7
+#define O_XGMAC_MIIM_CONFIG__hstclkdiv 0
+#define W_XGMAC_MIIM_CONFIG__hstclkdiv 7
+#define R_XGMAC_MIIM_LINK_FAIL_VECTOR 0x13
+#define O_XGMAC_MIIM_LINK_FAIL_VECTOR__miimlfvec 0
+#define W_XGMAC_MIIM_LINK_FAIL_VECTOR__miimlfvec 32
+#define R_XGMAC_MIIM_INDICATOR 0x14
+#define O_XGMAC_MIIM_INDICATOR__miimphylf 4
+#define O_XGMAC_MIIM_INDICATOR__miimmoncplt 3
+#define O_XGMAC_MIIM_INDICATOR__miimmonvld 2
+#define O_XGMAC_MIIM_INDICATOR__miimmon 1
+#define O_XGMAC_MIIM_INDICATOR__miimbusy 0
+
+/* GMAC stats registers */
+#define R_RBYT 0x27
+#define R_RPKT 0x28
+#define R_RFCS 0x29
+#define R_RMCA 0x2A
+#define R_RBCA 0x2B
+#define R_RXCF 0x2C
+#define R_RXPF 0x2D
+#define R_RXUO 0x2E
+#define R_RALN 0x2F
+#define R_RFLR 0x30
+#define R_RCDE 0x31
+#define R_RCSE 0x32
+#define R_RUND 0x33
+#define R_ROVR 0x34
+#define R_TBYT 0x38
+#define R_TPKT 0x39
+#define R_TMCA 0x3A
+#define R_TBCA 0x3B
+#define R_TXPF 0x3C
+#define R_TDFR 0x3D
+#define R_TEDF 0x3E
+#define R_TSCL 0x3F
+#define R_TMCL 0x40
+#define R_TLCL 0x41
+#define R_TXCL 0x42
+#define R_TNCL 0x43
+#define R_TJBR 0x46
+#define R_TFCS 0x47
+#define R_TXCF 0x48
+#define R_TOVR 0x49
+#define R_TUND 0x4A
+#define R_TFRG 0x4B
+
+/* Glue logic register and bit field definitions */
+#define R_MAC_ADDR0 0x50
+#define R_MAC_ADDR1 0x52
+#define R_MAC_ADDR2 0x54
+#define R_MAC_ADDR3 0x56
+#define R_MAC_ADDR_MASK2 0x58
+#define R_MAC_ADDR_MASK3 0x5A
+#define R_MAC_FILTER_CONFIG 0x5C
+#define O_MAC_FILTER_CONFIG__BROADCAST_EN 10
+#define O_MAC_FILTER_CONFIG__PAUSE_FRAME_EN 9
+#define O_MAC_FILTER_CONFIG__ALL_MCAST_EN 8
+#define O_MAC_FILTER_CONFIG__ALL_UCAST_EN 7
+#define O_MAC_FILTER_CONFIG__HASH_MCAST_EN 6
+#define O_MAC_FILTER_CONFIG__HASH_UCAST_EN 5
+#define O_MAC_FILTER_CONFIG__ADDR_MATCH_DISC 4
+#define O_MAC_FILTER_CONFIG__MAC_ADDR3_VALID 3
+#define O_MAC_FILTER_CONFIG__MAC_ADDR2_VALID 2
+#define O_MAC_FILTER_CONFIG__MAC_ADDR1_VALID 1
+#define O_MAC_FILTER_CONFIG__MAC_ADDR0_VALID 0
+#define R_HASH_TABLE_VECTOR 0x30
+#define R_TX_CONTROL 0x0A0
+#define O_TX_CONTROL__Tx15Halt 31
+#define O_TX_CONTROL__Tx14Halt 30
+#define O_TX_CONTROL__Tx13Halt 29
+#define O_TX_CONTROL__Tx12Halt 28
+#define O_TX_CONTROL__Tx11Halt 27
+#define O_TX_CONTROL__Tx10Halt 26
+#define O_TX_CONTROL__Tx9Halt 25
+#define O_TX_CONTROL__Tx8Halt 24
+#define O_TX_CONTROL__Tx7Halt 23
+#define O_TX_CONTROL__Tx6Halt 22
+#define O_TX_CONTROL__Tx5Halt 21
+#define O_TX_CONTROL__Tx4Halt 20
+#define O_TX_CONTROL__Tx3Halt 19
+#define O_TX_CONTROL__Tx2Halt 18
+#define O_TX_CONTROL__Tx1Halt 17
+#define O_TX_CONTROL__Tx0Halt 16
+#define O_TX_CONTROL__TxIdle 15
+#define O_TX_CONTROL__TxEnable 14
+#define O_TX_CONTROL__TxThreshold 0
+#define W_TX_CONTROL__TxThreshold 14
+#define R_RX_CONTROL 0x0A1
+#define O_RX_CONTROL__RGMII 10
+#define O_RX_CONTROL__SoftReset 2
+#define O_RX_CONTROL__RxHalt 1
+#define O_RX_CONTROL__RxEnable 0
+#define R_DESC_PACK_CTRL 0x0A2
+#define O_DESC_PACK_CTRL__ByteOffset 17
+#define W_DESC_PACK_CTRL__ByteOffset 3
+#define O_DESC_PACK_CTRL__PrePadEnable 16
+#define O_DESC_PACK_CTRL__MaxEntry 14
+#define W_DESC_PACK_CTRL__MaxEntry 2
+#define O_DESC_PACK_CTRL__RegularSize 0
+#define W_DESC_PACK_CTRL__RegularSize 14
+#define R_STATCTRL 0x0A3
+#define O_STATCTRL__OverFlowEn 4
+#define O_STATCTRL__GIG 3
+#define O_STATCTRL__Sten 2
+#define O_STATCTRL__ClrCnt 1
+#define O_STATCTRL__AutoZ 0
+#define R_L2ALLOCCTRL 0x0A4
+#define O_L2ALLOCCTRL__TxL2Allocate 9
+#define W_L2ALLOCCTRL__TxL2Allocate 9
+#define O_L2ALLOCCTRL__RxL2Allocate 0
+#define W_L2ALLOCCTRL__RxL2Allocate 9
+#define R_INTMASK 0x0A5
+#define O_INTMASK__Spi4TxError 28
+#define O_INTMASK__Spi4RxError 27
+#define O_INTMASK__RGMIIHalfDupCollision 27
+#define O_INTMASK__Abort 26
+#define O_INTMASK__Underrun 25
+#define O_INTMASK__DiscardPacket 24
+#define O_INTMASK__AsyncFifoFull 23
+#define O_INTMASK__TagFull 22
+#define O_INTMASK__Class3Full 21
+#define O_INTMASK__C3EarlyFull 20
+#define O_INTMASK__Class2Full 19
+#define O_INTMASK__C2EarlyFull 18
+#define O_INTMASK__Class1Full 17
+#define O_INTMASK__C1EarlyFull 16
+#define O_INTMASK__Class0Full 15
+#define O_INTMASK__C0EarlyFull 14
+#define O_INTMASK__RxDataFull 13
+#define O_INTMASK__RxEarlyFull 12
+#define O_INTMASK__RFreeEmpty 9
+#define O_INTMASK__RFEarlyEmpty 8
+#define O_INTMASK__P2PSpillEcc 7
+#define O_INTMASK__FreeDescFull 5
+#define O_INTMASK__FreeEarlyFull 4
+#define O_INTMASK__TxFetchError 3
+#define O_INTMASK__StatCarry 2
+#define O_INTMASK__MDInt 1
+#define O_INTMASK__TxIllegal 0
+#define R_INTREG 0x0A6
+#define O_INTREG__Spi4TxError 28
+#define O_INTREG__Spi4RxError 27
+#define O_INTREG__RGMIIHalfDupCollision 27
+#define O_INTREG__Abort 26
+#define O_INTREG__Underrun 25
+#define O_INTREG__DiscardPacket 24
+#define O_INTREG__AsyncFifoFull 23
+#define O_INTREG__TagFull 22
+#define O_INTREG__Class3Full 21
+#define O_INTREG__C3EarlyFull 20
+#define O_INTREG__Class2Full 19
+#define O_INTREG__C2EarlyFull 18
+#define O_INTREG__Class1Full 17
+#define O_INTREG__C1EarlyFull 16
+#define O_INTREG__Class0Full 15
+#define O_INTREG__C0EarlyFull 14
+#define O_INTREG__RxDataFull 13
+#define O_INTREG__RxEarlyFull 12
+#define O_INTREG__RFreeEmpty 9
+#define O_INTREG__RFEarlyEmpty 8
+#define O_INTREG__P2PSpillEcc 7
+#define O_INTREG__FreeDescFull 5
+#define O_INTREG__FreeEarlyFull 4
+#define O_INTREG__TxFetchError 3
+#define O_INTREG__StatCarry 2
+#define O_INTREG__MDInt 1
+#define O_INTREG__TxIllegal 0
+#define R_TXRETRY 0x0A7
+#define O_TXRETRY__CollisionRetry 6
+#define O_TXRETRY__BusErrorRetry 5
+#define O_TXRETRY__UnderRunRetry 4
+#define O_TXRETRY__Retries 0
+#define W_TXRETRY__Retries 4
+#define R_CORECONTROL 0x0A8
+#define O_CORECONTROL__ErrorThread 4
+#define W_CORECONTROL__ErrorThread 7
+#define O_CORECONTROL__Shutdown 2
+#define O_CORECONTROL__Speed 0
+#define W_CORECONTROL__Speed 2
+#define R_BYTEOFFSET0 0x0A9
+#define R_BYTEOFFSET1 0x0AA
+#define R_L2TYPE_0 0x0F0
+#define O_L2TYPE__ExtraHdrProtoSize 26
+#define W_L2TYPE__ExtraHdrProtoSize 5
+#define O_L2TYPE__ExtraHdrProtoOffset 20
+#define W_L2TYPE__ExtraHdrProtoOffset 6
+#define O_L2TYPE__ExtraHeaderSize 14
+#define W_L2TYPE__ExtraHeaderSize 6
+#define O_L2TYPE__ProtoOffset 8
+#define W_L2TYPE__ProtoOffset 6
+#define O_L2TYPE__L2HdrOffset 2
+#define W_L2TYPE__L2HdrOffset 6
+#define O_L2TYPE__L2Proto 0
+#define W_L2TYPE__L2Proto 2
+#define R_L2TYPE_1 0xF0
+#define R_L2TYPE_2 0xF0
+#define R_L2TYPE_3 0xF0
+#define R_PARSERCONFIGREG 0x100
+#define O_PARSERCONFIGREG__CRCHashPoly 8
+#define W_PARSERCONFIGREG__CRCHashPoly 7
+#define O_PARSERCONFIGREG__PrePadOffset 4
+#define W_PARSERCONFIGREG__PrePadOffset 4
+#define O_PARSERCONFIGREG__UseCAM 2
+#define O_PARSERCONFIGREG__UseHASH 1
+#define O_PARSERCONFIGREG__UseProto 0
+#define R_L3CTABLE 0x140
+#define O_L3CTABLE__Offset0 25
+#define W_L3CTABLE__Offset0 7
+#define O_L3CTABLE__Len0 21
+#define W_L3CTABLE__Len0 4
+#define O_L3CTABLE__Offset1 14
+#define W_L3CTABLE__Offset1 7
+#define O_L3CTABLE__Len1 10
+#define W_L3CTABLE__Len1 4
+#define O_L3CTABLE__Offset2 4
+#define W_L3CTABLE__Offset2 6
+#define O_L3CTABLE__Len2 0
+#define W_L3CTABLE__Len2 4
+#define O_L3CTABLE__L3HdrOffset 26
+#define W_L3CTABLE__L3HdrOffset 6
+#define O_L3CTABLE__L4ProtoOffset 20
+#define W_L3CTABLE__L4ProtoOffset 6
+#define O_L3CTABLE__IPChksumCompute 19
+#define O_L3CTABLE__L4Classify 18
+#define O_L3CTABLE__L2Proto 16
+#define W_L3CTABLE__L2Proto 2
+#define O_L3CTABLE__L3ProtoKey 0
+#define W_L3CTABLE__L3ProtoKey 16
+#define R_L4CTABLE 0x160
+#define O_L4CTABLE__Offset0 21
+#define W_L4CTABLE__Offset0 6
+#define O_L4CTABLE__Len0 17
+#define W_L4CTABLE__Len0 4
+#define O_L4CTABLE__Offset1 11
+#define W_L4CTABLE__Offset1 6
+#define O_L4CTABLE__Len1 7
+#define W_L4CTABLE__Len1 4
+#define O_L4CTABLE__TCPChksumEnable 0
+#define R_CAM4X128TABLE 0x172
+#define O_CAM4X128TABLE__ClassId 7
+#define W_CAM4X128TABLE__ClassId 2
+#define O_CAM4X128TABLE__BucketId 1
+#define W_CAM4X128TABLE__BucketId 6
+#define O_CAM4X128TABLE__UseBucket 0
+#define R_CAM4X128KEY 0x180
+#define R_TRANSLATETABLE 0x1A0
+#define R_DMACR0 0x200
+#define O_DMACR0__Data0WrMaxCr 27
+#define W_DMACR0__Data0WrMaxCr 3
+#define O_DMACR0__Data0RdMaxCr 24
+#define W_DMACR0__Data0RdMaxCr 3
+#define O_DMACR0__Data1WrMaxCr 21
+#define W_DMACR0__Data1WrMaxCr 3
+#define O_DMACR0__Data1RdMaxCr 18
+#define W_DMACR0__Data1RdMaxCr 3
+#define O_DMACR0__Data2WrMaxCr 15
+#define W_DMACR0__Data2WrMaxCr 3
+#define O_DMACR0__Data2RdMaxCr 12
+#define W_DMACR0__Data2RdMaxCr 3
+#define O_DMACR0__Data3WrMaxCr 9
+#define W_DMACR0__Data3WrMaxCr 3
+#define O_DMACR0__Data3RdMaxCr 6
+#define W_DMACR0__Data3RdMaxCr 3
+#define O_DMACR0__Data4WrMaxCr 3
+#define W_DMACR0__Data4WrMaxCr 3
+#define O_DMACR0__Data4RdMaxCr 0
+#define W_DMACR0__Data4RdMaxCr 3
+#define R_DMACR1 0x201
+#define O_DMACR1__Data5WrMaxCr 27
+#define W_DMACR1__Data5WrMaxCr 3
+#define O_DMACR1__Data5RdMaxCr 24
+#define W_DMACR1__Data5RdMaxCr 3
+#define O_DMACR1__Data6WrMaxCr 21
+#define W_DMACR1__Data6WrMaxCr 3
+#define O_DMACR1__Data6RdMaxCr 18
+#define W_DMACR1__Data6RdMaxCr 3
+#define O_DMACR1__Data7WrMaxCr 15
+#define W_DMACR1__Data7WrMaxCr 3
+#define O_DMACR1__Data7RdMaxCr 12
+#define W_DMACR1__Data7RdMaxCr 3
+#define O_DMACR1__Data8WrMaxCr 9
+#define W_DMACR1__Data8WrMaxCr 3
+#define O_DMACR1__Data8RdMaxCr 6
+#define W_DMACR1__Data8RdMaxCr 3
+#define O_DMACR1__Data9WrMaxCr 3
+#define W_DMACR1__Data9WrMaxCr 3
+#define O_DMACR1__Data9RdMaxCr 0
+#define W_DMACR1__Data9RdMaxCr 3
+#define R_DMACR2 0x202
+#define O_DMACR2__Data10WrMaxCr 27
+#define W_DMACR2__Data10WrMaxCr 3
+#define O_DMACR2__Data10RdMaxCr 24
+#define W_DMACR2__Data10RdMaxCr 3
+#define O_DMACR2__Data11WrMaxCr 21
+#define W_DMACR2__Data11WrMaxCr 3
+#define O_DMACR2__Data11RdMaxCr 18
+#define W_DMACR2__Data11RdMaxCr 3
+#define O_DMACR2__Data12WrMaxCr 15
+#define W_DMACR2__Data12WrMaxCr 3
+#define O_DMACR2__Data12RdMaxCr 12
+#define W_DMACR2__Data12RdMaxCr 3
+#define O_DMACR2__Data13WrMaxCr 9
+#define W_DMACR2__Data13WrMaxCr 3
+#define O_DMACR2__Data13RdMaxCr 6
+#define W_DMACR2__Data13RdMaxCr 3
+#define O_DMACR2__Data14WrMaxCr 3
+#define W_DMACR2__Data14WrMaxCr 3
+#define O_DMACR2__Data14RdMaxCr 0
+#define W_DMACR2__Data14RdMaxCr 3
+#define R_DMACR3 0x203
+#define O_DMACR3__Data15WrMaxCr 27
+#define W_DMACR3__Data15WrMaxCr 3
+#define O_DMACR3__Data15RdMaxCr 24
+#define W_DMACR3__Data15RdMaxCr 3
+#define O_DMACR3__SpClassWrMaxCr 21
+#define W_DMACR3__SpClassWrMaxCr 3
+#define O_DMACR3__SpClassRdMaxCr 18
+#define W_DMACR3__SpClassRdMaxCr 3
+#define O_DMACR3__JumFrInWrMaxCr 15
+#define W_DMACR3__JumFrInWrMaxCr 3
+#define O_DMACR3__JumFrInRdMaxCr 12
+#define W_DMACR3__JumFrInRdMaxCr 3
+#define O_DMACR3__RegFrInWrMaxCr 9
+#define W_DMACR3__RegFrInWrMaxCr 3
+#define O_DMACR3__RegFrInRdMaxCr 6
+#define W_DMACR3__RegFrInRdMaxCr 3
+#define O_DMACR3__FrOutWrMaxCr 3
+#define W_DMACR3__FrOutWrMaxCr 3
+#define O_DMACR3__FrOutRdMaxCr 0
+#define W_DMACR3__FrOutRdMaxCr 3
+#define R_REG_FRIN_SPILL_MEM_START_0 0x204
+#define O_REG_FRIN_SPILL_MEM_START_0__RegFrInSpillMemStart0 0
+#define W_REG_FRIN_SPILL_MEM_START_0__RegFrInSpillMemStart0 32
+#define R_REG_FRIN_SPILL_MEM_START_1 0x205
+#define O_REG_FRIN_SPILL_MEM_START_1__RegFrInSpillMemStart1 0
+#define W_REG_FRIN_SPILL_MEM_START_1__RegFrInSpillMemStart1 3
+#define R_REG_FRIN_SPILL_MEM_SIZE 0x206
+#define O_REG_FRIN_SPILL_MEM_SIZE__RegFrInSpillMemSize 0
+#define W_REG_FRIN_SPILL_MEM_SIZE__RegFrInSpillMemSize 32
+#define R_FROUT_SPILL_MEM_START_0 0x207
+#define O_FROUT_SPILL_MEM_START_0__FrOutSpillMemStart0 0
+#define W_FROUT_SPILL_MEM_START_0__FrOutSpillMemStart0 32
+#define R_FROUT_SPILL_MEM_START_1 0x208
+#define O_FROUT_SPILL_MEM_START_1__FrOutSpillMemStart1 0
+#define W_FROUT_SPILL_MEM_START_1__FrOutSpillMemStart1 3
+#define R_FROUT_SPILL_MEM_SIZE 0x209
+#define O_FROUT_SPILL_MEM_SIZE__FrOutSpillMemSize 0
+#define W_FROUT_SPILL_MEM_SIZE__FrOutSpillMemSize 32
+#define R_CLASS0_SPILL_MEM_START_0 0x20A
+#define O_CLASS0_SPILL_MEM_START_0__Class0SpillMemStart0 0
+#define W_CLASS0_SPILL_MEM_START_0__Class0SpillMemStart0 32
+#define R_CLASS0_SPILL_MEM_START_1 0x20B
+#define O_CLASS0_SPILL_MEM_START_1__Class0SpillMemStart1 0
+#define W_CLASS0_SPILL_MEM_START_1__Class0SpillMemStart1 3
+#define R_CLASS0_SPILL_MEM_SIZE 0x20C
+#define O_CLASS0_SPILL_MEM_SIZE__Class0SpillMemSize 0
+#define W_CLASS0_SPILL_MEM_SIZE__Class0SpillMemSize 32
+#define R_JUMFRIN_SPILL_MEM_START_0 0x20D
+#define O_JUMFRIN_SPILL_MEM_START_0__JumFrInSpillMemStar0 0
+#define W_JUMFRIN_SPILL_MEM_START_0__JumFrInSpillMemStar0 32
+#define R_JUMFRIN_SPILL_MEM_START_1 0x20E
+#define O_JUMFRIN_SPILL_MEM_START_1__JumFrInSpillMemStart1 0
+#define W_JUMFRIN_SPILL_MEM_START_1__JumFrInSpillMemStart1 3
+#define R_JUMFRIN_SPILL_MEM_SIZE 0x20F
+#define O_JUMFRIN_SPILL_MEM_SIZE__JumFrInSpillMemSize 0
+#define W_JUMFRIN_SPILL_MEM_SIZE__JumFrInSpillMemSize 32
+#define R_CLASS1_SPILL_MEM_START_0 0x210
+#define O_CLASS1_SPILL_MEM_START_0__Class1SpillMemStart0 0
+#define W_CLASS1_SPILL_MEM_START_0__Class1SpillMemStart0 32
+#define R_CLASS1_SPILL_MEM_START_1 0x211
+#define O_CLASS1_SPILL_MEM_START_1__Class1SpillMemStart1 0
+#define W_CLASS1_SPILL_MEM_START_1__Class1SpillMemStart1 3
+#define R_CLASS1_SPILL_MEM_SIZE 0x212
+#define O_CLASS1_SPILL_MEM_SIZE__Class1SpillMemSize 0
+#define W_CLASS1_SPILL_MEM_SIZE__Class1SpillMemSize 32
+#define R_CLASS2_SPILL_MEM_START_0 0x213
+#define O_CLASS2_SPILL_MEM_START_0__Class2SpillMemStart0 0
+#define W_CLASS2_SPILL_MEM_START_0__Class2SpillMemStart0 32
+#define R_CLASS2_SPILL_MEM_START_1 0x214
+#define O_CLASS2_SPILL_MEM_START_1__Class2SpillMemStart1 0
+#define W_CLASS2_SPILL_MEM_START_1__Class2SpillMemStart1 3
+#define R_CLASS2_SPILL_MEM_SIZE 0x215
+#define O_CLASS2_SPILL_MEM_SIZE__Class2SpillMemSize 0
+#define W_CLASS2_SPILL_MEM_SIZE__Class2SpillMemSize 32
+#define R_CLASS3_SPILL_MEM_START_0 0x216
+#define O_CLASS3_SPILL_MEM_START_0__Class3SpillMemStart0 0
+#define W_CLASS3_SPILL_MEM_START_0__Class3SpillMemStart0 32
+#define R_CLASS3_SPILL_MEM_START_1 0x217
+#define O_CLASS3_SPILL_MEM_START_1__Class3SpillMemStart1 0
+#define W_CLASS3_SPILL_MEM_START_1__Class3SpillMemStart1 3
+#define R_CLASS3_SPILL_MEM_SIZE 0x218
+#define O_CLASS3_SPILL_MEM_SIZE__Class3SpillMemSize 0
+#define W_CLASS3_SPILL_MEM_SIZE__Class3SpillMemSize 32
+#define R_REG_FRIN1_SPILL_MEM_START_0 0x219
+#define R_REG_FRIN1_SPILL_MEM_START_1 0x21a
+#define R_REG_FRIN1_SPILL_MEM_SIZE 0x21b
+#define R_SPIHNGY0 0x219
+#define O_SPIHNGY0__EG_HNGY_THRESH_0 24
+#define W_SPIHNGY0__EG_HNGY_THRESH_0 7
+#define O_SPIHNGY0__EG_HNGY_THRESH_1 16
+#define W_SPIHNGY0__EG_HNGY_THRESH_1 7
+#define O_SPIHNGY0__EG_HNGY_THRESH_2 8
+#define W_SPIHNGY0__EG_HNGY_THRESH_2 7
+#define O_SPIHNGY0__EG_HNGY_THRESH_3 0
+#define W_SPIHNGY0__EG_HNGY_THRESH_3 7
+#define R_SPIHNGY1 0x21A
+#define O_SPIHNGY1__EG_HNGY_THRESH_4 24
+#define W_SPIHNGY1__EG_HNGY_THRESH_4 7
+#define O_SPIHNGY1__EG_HNGY_THRESH_5 16
+#define W_SPIHNGY1__EG_HNGY_THRESH_5 7
+#define O_SPIHNGY1__EG_HNGY_THRESH_6 8
+#define W_SPIHNGY1__EG_HNGY_THRESH_6 7
+#define O_SPIHNGY1__EG_HNGY_THRESH_7 0
+#define W_SPIHNGY1__EG_HNGY_THRESH_7 7
+#define R_SPIHNGY2 0x21B
+#define O_SPIHNGY2__EG_HNGY_THRESH_8 24
+#define W_SPIHNGY2__EG_HNGY_THRESH_8 7
+#define O_SPIHNGY2__EG_HNGY_THRESH_9 16
+#define W_SPIHNGY2__EG_HNGY_THRESH_9 7
+#define O_SPIHNGY2__EG_HNGY_THRESH_10 8
+#define W_SPIHNGY2__EG_HNGY_THRESH_10 7
+#define O_SPIHNGY2__EG_HNGY_THRESH_11 0
+#define W_SPIHNGY2__EG_HNGY_THRESH_11 7
+#define R_SPIHNGY3 0x21C
+#define O_SPIHNGY3__EG_HNGY_THRESH_12 24
+#define W_SPIHNGY3__EG_HNGY_THRESH_12 7
+#define O_SPIHNGY3__EG_HNGY_THRESH_13 16
+#define W_SPIHNGY3__EG_HNGY_THRESH_13 7
+#define O_SPIHNGY3__EG_HNGY_THRESH_14 8
+#define W_SPIHNGY3__EG_HNGY_THRESH_14 7
+#define O_SPIHNGY3__EG_HNGY_THRESH_15 0
+#define W_SPIHNGY3__EG_HNGY_THRESH_15 7
+#define R_SPISTRV0 0x21D
+#define O_SPISTRV0__EG_STRV_THRESH_0 24
+#define W_SPISTRV0__EG_STRV_THRESH_0 7
+#define O_SPISTRV0__EG_STRV_THRESH_1 16
+#define W_SPISTRV0__EG_STRV_THRESH_1 7
+#define O_SPISTRV0__EG_STRV_THRESH_2 8
+#define W_SPISTRV0__EG_STRV_THRESH_2 7
+#define O_SPISTRV0__EG_STRV_THRESH_3 0
+#define W_SPISTRV0__EG_STRV_THRESH_3 7
+#define R_SPISTRV1 0x21E
+#define O_SPISTRV1__EG_STRV_THRESH_4 24
+#define W_SPISTRV1__EG_STRV_THRESH_4 7
+#define O_SPISTRV1__EG_STRV_THRESH_5 16
+#define W_SPISTRV1__EG_STRV_THRESH_5 7
+#define O_SPISTRV1__EG_STRV_THRESH_6 8
+#define W_SPISTRV1__EG_STRV_THRESH_6 7
+#define O_SPISTRV1__EG_STRV_THRESH_7 0
+#define W_SPISTRV1__EG_STRV_THRESH_7 7
+#define R_SPISTRV2 0x21F
+#define O_SPISTRV2__EG_STRV_THRESH_8 24
+#define W_SPISTRV2__EG_STRV_THRESH_8 7
+#define O_SPISTRV2__EG_STRV_THRESH_9 16
+#define W_SPISTRV2__EG_STRV_THRESH_9 7
+#define O_SPISTRV2__EG_STRV_THRESH_10 8
+#define W_SPISTRV2__EG_STRV_THRESH_10 7
+#define O_SPISTRV2__EG_STRV_THRESH_11 0
+#define W_SPISTRV2__EG_STRV_THRESH_11 7
+#define R_SPISTRV3 0x220
+#define O_SPISTRV3__EG_STRV_THRESH_12 24
+#define W_SPISTRV3__EG_STRV_THRESH_12 7
+#define O_SPISTRV3__EG_STRV_THRESH_13 16
+#define W_SPISTRV3__EG_STRV_THRESH_13 7
+#define O_SPISTRV3__EG_STRV_THRESH_14 8
+#define W_SPISTRV3__EG_STRV_THRESH_14 7
+#define O_SPISTRV3__EG_STRV_THRESH_15 0
+#define W_SPISTRV3__EG_STRV_THRESH_15 7
+#define R_TXDATAFIFO0 0x221
+#define O_TXDATAFIFO0__Tx0DataFifoStart 24
+#define W_TXDATAFIFO0__Tx0DataFifoStart 7
+#define O_TXDATAFIFO0__Tx0DataFifoSize 16
+#define W_TXDATAFIFO0__Tx0DataFifoSize 7
+#define O_TXDATAFIFO0__Tx1DataFifoStart 8
+#define W_TXDATAFIFO0__Tx1DataFifoStart 7
+#define O_TXDATAFIFO0__Tx1DataFifoSize 0
+#define W_TXDATAFIFO0__Tx1DataFifoSize 7
+#define R_TXDATAFIFO1 0x222
+#define O_TXDATAFIFO1__Tx2DataFifoStart 24
+#define W_TXDATAFIFO1__Tx2DataFifoStart 7
+#define O_TXDATAFIFO1__Tx2DataFifoSize 16
+#define W_TXDATAFIFO1__Tx2DataFifoSize 7
+#define O_TXDATAFIFO1__Tx3DataFifoStart 8
+#define W_TXDATAFIFO1__Tx3DataFifoStart 7
+#define O_TXDATAFIFO1__Tx3DataFifoSize 0
+#define W_TXDATAFIFO1__Tx3DataFifoSize 7
+#define R_TXDATAFIFO2 0x223
+#define O_TXDATAFIFO2__Tx4DataFifoStart 24
+#define W_TXDATAFIFO2__Tx4DataFifoStart 7
+#define O_TXDATAFIFO2__Tx4DataFifoSize 16
+#define W_TXDATAFIFO2__Tx4DataFifoSize 7
+#define O_TXDATAFIFO2__Tx5DataFifoStart 8
+#define W_TXDATAFIFO2__Tx5DataFifoStart 7
+#define O_TXDATAFIFO2__Tx5DataFifoSize 0
+#define W_TXDATAFIFO2__Tx5DataFifoSize 7
+#define R_TXDATAFIFO3 0x224
+#define O_TXDATAFIFO3__Tx6DataFifoStart 24
+#define W_TXDATAFIFO3__Tx6DataFifoStart 7
+#define O_TXDATAFIFO3__Tx6DataFifoSize 16
+#define W_TXDATAFIFO3__Tx6DataFifoSize 7
+#define O_TXDATAFIFO3__Tx7DataFifoStart 8
+#define W_TXDATAFIFO3__Tx7DataFifoStart 7
+#define O_TXDATAFIFO3__Tx7DataFifoSize 0
+#define W_TXDATAFIFO3__Tx7DataFifoSize 7
+#define R_TXDATAFIFO4 0x225
+#define O_TXDATAFIFO4__Tx8DataFifoStart 24
+#define W_TXDATAFIFO4__Tx8DataFifoStart 7
+#define O_TXDATAFIFO4__Tx8DataFifoSize 16
+#define W_TXDATAFIFO4__Tx8DataFifoSize 7
+#define O_TXDATAFIFO4__Tx9DataFifoStart 8
+#define W_TXDATAFIFO4__Tx9DataFifoStart 7
+#define O_TXDATAFIFO4__Tx9DataFifoSize 0
+#define W_TXDATAFIFO4__Tx9DataFifoSize 7
+#define R_TXDATAFIFO5 0x226
+#define O_TXDATAFIFO5__Tx10DataFifoStart 24
+#define W_TXDATAFIFO5__Tx10DataFifoStart 7
+#define O_TXDATAFIFO5__Tx10DataFifoSize 16
+#define W_TXDATAFIFO5__Tx10DataFifoSize 7
+#define O_TXDATAFIFO5__Tx11DataFifoStart 8
+#define W_TXDATAFIFO5__Tx11DataFifoStart 7
+#define O_TXDATAFIFO5__Tx11DataFifoSize 0
+#define W_TXDATAFIFO5__Tx11DataFifoSize 7
+#define R_TXDATAFIFO6 0x227
+#define O_TXDATAFIFO6__Tx12DataFifoStart 24
+#define W_TXDATAFIFO6__Tx12DataFifoStart 7
+#define O_TXDATAFIFO6__Tx12DataFifoSize 16
+#define W_TXDATAFIFO6__Tx12DataFifoSize 7
+#define O_TXDATAFIFO6__Tx13DataFifoStart 8
+#define W_TXDATAFIFO6__Tx13DataFifoStart 7
+#define O_TXDATAFIFO6__Tx13DataFifoSize 0
+#define W_TXDATAFIFO6__Tx13DataFifoSize 7
+#define R_TXDATAFIFO7 0x228
+#define O_TXDATAFIFO7__Tx14DataFifoStart 24
+#define W_TXDATAFIFO7__Tx14DataFifoStart 7
+#define O_TXDATAFIFO7__Tx14DataFifoSize 16
+#define W_TXDATAFIFO7__Tx14DataFifoSize 7
+#define O_TXDATAFIFO7__Tx15DataFifoStart 8
+#define W_TXDATAFIFO7__Tx15DataFifoStart 7
+#define O_TXDATAFIFO7__Tx15DataFifoSize 0
+#define W_TXDATAFIFO7__Tx15DataFifoSize 7
+#define R_RXDATAFIFO0 0x229
+#define O_RXDATAFIFO0__Rx0DataFifoStart 24
+#define W_RXDATAFIFO0__Rx0DataFifoStart 7
+#define O_RXDATAFIFO0__Rx0DataFifoSize 16
+#define W_RXDATAFIFO0__Rx0DataFifoSize 7
+#define O_RXDATAFIFO0__Rx1DataFifoStart 8
+#define W_RXDATAFIFO0__Rx1DataFifoStart 7
+#define O_RXDATAFIFO0__Rx1DataFifoSize 0
+#define W_RXDATAFIFO0__Rx1DataFifoSize 7
+#define R_RXDATAFIFO1 0x22A
+#define O_RXDATAFIFO1__Rx2DataFifoStart 24
+#define W_RXDATAFIFO1__Rx2DataFifoStart 7
+#define O_RXDATAFIFO1__Rx2DataFifoSize 16
+#define W_RXDATAFIFO1__Rx2DataFifoSize 7
+#define O_RXDATAFIFO1__Rx3DataFifoStart 8
+#define W_RXDATAFIFO1__Rx3DataFifoStart 7
+#define O_RXDATAFIFO1__Rx3DataFifoSize 0
+#define W_RXDATAFIFO1__Rx3DataFifoSize 7
+#define R_RXDATAFIFO2 0x22B
+#define O_RXDATAFIFO2__Rx4DataFifoStart 24
+#define W_RXDATAFIFO2__Rx4DataFifoStart 7
+#define O_RXDATAFIFO2__Rx4DataFifoSize 16
+#define W_RXDATAFIFO2__Rx4DataFifoSize 7
+#define O_RXDATAFIFO2__Rx5DataFifoStart 8
+#define W_RXDATAFIFO2__Rx5DataFifoStart 7
+#define O_RXDATAFIFO2__Rx5DataFifoSize 0
+#define W_RXDATAFIFO2__Rx5DataFifoSize 7
+#define R_RXDATAFIFO3 0x22C
+#define O_RXDATAFIFO3__Rx6DataFifoStart 24
+#define W_RXDATAFIFO3__Rx6DataFifoStart 7
+#define O_RXDATAFIFO3__Rx6DataFifoSize 16
+#define W_RXDATAFIFO3__Rx6DataFifoSize 7
+#define O_RXDATAFIFO3__Rx7DataFifoStart 8
+#define W_RXDATAFIFO3__Rx7DataFifoStart 7
+#define O_RXDATAFIFO3__Rx7DataFifoSize 0
+#define W_RXDATAFIFO3__Rx7DataFifoSize 7
+#define R_RXDATAFIFO4 0x22D
+#define O_RXDATAFIFO4__Rx8DataFifoStart 24
+#define W_RXDATAFIFO4__Rx8DataFifoStart 7
+#define O_RXDATAFIFO4__Rx8DataFifoSize 16
+#define W_RXDATAFIFO4__Rx8DataFifoSize 7
+#define O_RXDATAFIFO4__Rx9DataFifoStart 8
+#define W_RXDATAFIFO4__Rx9DataFifoStart 7
+#define O_RXDATAFIFO4__Rx9DataFifoSize 0
+#define W_RXDATAFIFO4__Rx9DataFifoSize 7
+#define R_RXDATAFIFO5 0x22E
+#define O_RXDATAFIFO5__Rx10DataFifoStart 24
+#define W_RXDATAFIFO5__Rx10DataFifoStart 7
+#define O_RXDATAFIFO5__Rx10DataFifoSize 16
+#define W_RXDATAFIFO5__Rx10DataFifoSize 7
+#define O_RXDATAFIFO5__Rx11DataFifoStart 8
+#define W_RXDATAFIFO5__Rx11DataFifoStart 7
+#define O_RXDATAFIFO5__Rx11DataFifoSize 0
+#define W_RXDATAFIFO5__Rx11DataFifoSize 7
+#define R_RXDATAFIFO6 0x22F
+#define O_RXDATAFIFO6__Rx12DataFifoStart 24
+#define W_RXDATAFIFO6__Rx12DataFifoStart 7
+#define O_RXDATAFIFO6__Rx12DataFifoSize 16
+#define W_RXDATAFIFO6__Rx12DataFifoSize 7
+#define O_RXDATAFIFO6__Rx13DataFifoStart 8
+#define W_RXDATAFIFO6__Rx13DataFifoStart 7
+#define O_RXDATAFIFO6__Rx13DataFifoSize 0
+#define W_RXDATAFIFO6__Rx13DataFifoSize 7
+#define R_RXDATAFIFO7 0x230
+#define O_RXDATAFIFO7__Rx14DataFifoStart 24
+#define W_RXDATAFIFO7__Rx14DataFifoStart 7
+#define O_RXDATAFIFO7__Rx14DataFifoSize 16
+#define W_RXDATAFIFO7__Rx14DataFifoSize 7
+#define O_RXDATAFIFO7__Rx15DataFifoStart 8
+#define W_RXDATAFIFO7__Rx15DataFifoStart 7
+#define O_RXDATAFIFO7__Rx15DataFifoSize 0
+#define W_RXDATAFIFO7__Rx15DataFifoSize 7
+#define R_XGMACPADCALIBRATION 0x231
+#define R_FREEQCARVE 0x233
+#define R_SPI4STATICDELAY0 0x240
+#define O_SPI4STATICDELAY0__DataLine7 28
+#define W_SPI4STATICDELAY0__DataLine7 4
+#define O_SPI4STATICDELAY0__DataLine6 24
+#define W_SPI4STATICDELAY0__DataLine6 4
+#define O_SPI4STATICDELAY0__DataLine5 20
+#define W_SPI4STATICDELAY0__DataLine5 4
+#define O_SPI4STATICDELAY0__DataLine4 16
+#define W_SPI4STATICDELAY0__DataLine4 4
+#define O_SPI4STATICDELAY0__DataLine3 12
+#define W_SPI4STATICDELAY0__DataLine3 4
+#define O_SPI4STATICDELAY0__DataLine2 8
+#define W_SPI4STATICDELAY0__DataLine2 4
+#define O_SPI4STATICDELAY0__DataLine1 4
+#define W_SPI4STATICDELAY0__DataLine1 4
+#define O_SPI4STATICDELAY0__DataLine0 0
+#define W_SPI4STATICDELAY0__DataLine0 4
+#define R_SPI4STATICDELAY1 0x241
+#define O_SPI4STATICDELAY1__DataLine15 28
+#define W_SPI4STATICDELAY1__DataLine15 4
+#define O_SPI4STATICDELAY1__DataLine14 24
+#define W_SPI4STATICDELAY1__DataLine14 4
+#define O_SPI4STATICDELAY1__DataLine13 20
+#define W_SPI4STATICDELAY1__DataLine13 4
+#define O_SPI4STATICDELAY1__DataLine12 16
+#define W_SPI4STATICDELAY1__DataLine12 4
+#define O_SPI4STATICDELAY1__DataLine11 12
+#define W_SPI4STATICDELAY1__DataLine11 4
+#define O_SPI4STATICDELAY1__DataLine10 8
+#define W_SPI4STATICDELAY1__DataLine10 4
+#define O_SPI4STATICDELAY1__DataLine9 4
+#define W_SPI4STATICDELAY1__DataLine9 4
+#define O_SPI4STATICDELAY1__DataLine8 0
+#define W_SPI4STATICDELAY1__DataLine8 4
+#define R_SPI4STATICDELAY2 0x242
+#define O_SPI4STATICDELAY0__TxStat1 8
+#define W_SPI4STATICDELAY0__TxStat1 4
+#define O_SPI4STATICDELAY0__TxStat0 4
+#define W_SPI4STATICDELAY0__TxStat0 4
+#define O_SPI4STATICDELAY0__RxControl 0
+#define W_SPI4STATICDELAY0__RxControl 4
+#define R_SPI4CONTROL 0x243
+#define O_SPI4CONTROL__StaticDelay 2
+#define O_SPI4CONTROL__LVDS_LVTTL 1
+#define O_SPI4CONTROL__SPI4Enable 0
+#define R_CLASSWATERMARKS 0x244
+#define O_CLASSWATERMARKS__Class0Watermark 24
+#define W_CLASSWATERMARKS__Class0Watermark 5
+#define O_CLASSWATERMARKS__Class1Watermark 16
+#define W_CLASSWATERMARKS__Class1Watermark 5
+#define O_CLASSWATERMARKS__Class3Watermark 0
+#define W_CLASSWATERMARKS__Class3Watermark 5
+#define R_RXWATERMARKS1 0x245
+#define O_RXWATERMARKS__Rx0DataWatermark 24
+#define W_RXWATERMARKS__Rx0DataWatermark 7
+#define O_RXWATERMARKS__Rx1DataWatermark 16
+#define W_RXWATERMARKS__Rx1DataWatermark 7
+#define O_RXWATERMARKS__Rx3DataWatermark 0
+#define W_RXWATERMARKS__Rx3DataWatermark 7
+#define R_RXWATERMARKS2 0x246
+#define O_RXWATERMARKS__Rx4DataWatermark 24
+#define W_RXWATERMARKS__Rx4DataWatermark 7
+#define O_RXWATERMARKS__Rx5DataWatermark 16
+#define W_RXWATERMARKS__Rx5DataWatermark 7
+#define O_RXWATERMARKS__Rx6DataWatermark 8
+#define W_RXWATERMARKS__Rx6DataWatermark 7
+#define O_RXWATERMARKS__Rx7DataWatermark 0
+#define W_RXWATERMARKS__Rx7DataWatermark 7
+#define R_RXWATERMARKS3 0x247
+#define O_RXWATERMARKS__Rx8DataWatermark 24
+#define W_RXWATERMARKS__Rx8DataWatermark 7
+#define O_RXWATERMARKS__Rx9DataWatermark 16
+#define W_RXWATERMARKS__Rx9DataWatermark 7
+#define O_RXWATERMARKS__Rx10DataWatermark 8
+#define W_RXWATERMARKS__Rx10DataWatermark 7
+#define O_RXWATERMARKS__Rx11DataWatermark 0
+#define W_RXWATERMARKS__Rx11DataWatermark 7
+#define R_RXWATERMARKS4 0x248
+#define O_RXWATERMARKS__Rx12DataWatermark 24
+#define W_RXWATERMARKS__Rx12DataWatermark 7
+#define O_RXWATERMARKS__Rx13DataWatermark 16
+#define W_RXWATERMARKS__Rx13DataWatermark 7
+#define O_RXWATERMARKS__Rx14DataWatermark 8
+#define W_RXWATERMARKS__Rx14DataWatermark 7
+#define O_RXWATERMARKS__Rx15DataWatermark 0
+#define W_RXWATERMARKS__Rx15DataWatermark 7
+#define R_FREEWATERMARKS 0x249
+#define O_FREEWATERMARKS__FreeOutWatermark 16
+#define W_FREEWATERMARKS__FreeOutWatermark 16
+#define O_FREEWATERMARKS__JumFrWatermark 8
+#define W_FREEWATERMARKS__JumFrWatermark 7
+#define O_FREEWATERMARKS__RegFrWatermark 0
+#define W_FREEWATERMARKS__RegFrWatermark 7
+#define R_EGRESSFIFOCARVINGSLOTS 0x24a
+
+#define CTRL_RES0 0
+#define CTRL_RES1 1
+#define CTRL_REG_FREE 2
+#define CTRL_JUMBO_FREE 3
+#define CTRL_CONT 4
+#define CTRL_EOP 5
+#define CTRL_START 6
+#define CTRL_SNGL 7
+
+#define CTRL_B0_NOT_EOP 0
+#define CTRL_B0_EOP 1
+
+#define R_ROUND_ROBIN_TABLE 0
+#define R_PDE_CLASS_0 0x300
+#define R_PDE_CLASS_1 0x302
+#define R_PDE_CLASS_2 0x304
+#define R_PDE_CLASS_3 0x306
+
+#define R_MSG_TX_THRESHOLD 0x308
+
+#define R_GMAC_JFR0_BUCKET_SIZE 0x320
+#define R_GMAC_RFR0_BUCKET_SIZE 0x321
+#define R_GMAC_TX0_BUCKET_SIZE 0x322
+#define R_GMAC_TX1_BUCKET_SIZE 0x323
+#define R_GMAC_TX2_BUCKET_SIZE 0x324
+#define R_GMAC_TX3_BUCKET_SIZE 0x325
+#define R_GMAC_JFR1_BUCKET_SIZE 0x326
+#define R_GMAC_RFR1_BUCKET_SIZE 0x327
+
+#define R_XGS_TX0_BUCKET_SIZE 0x320
+#define R_XGS_TX1_BUCKET_SIZE 0x321
+#define R_XGS_TX2_BUCKET_SIZE 0x322
+#define R_XGS_TX3_BUCKET_SIZE 0x323
+#define R_XGS_TX4_BUCKET_SIZE 0x324
+#define R_XGS_TX5_BUCKET_SIZE 0x325
+#define R_XGS_TX6_BUCKET_SIZE 0x326
+#define R_XGS_TX7_BUCKET_SIZE 0x327
+#define R_XGS_TX8_BUCKET_SIZE 0x328
+#define R_XGS_TX9_BUCKET_SIZE 0x329
+#define R_XGS_TX10_BUCKET_SIZE 0x32A
+#define R_XGS_TX11_BUCKET_SIZE 0x32B
+#define R_XGS_TX12_BUCKET_SIZE 0x32C
+#define R_XGS_TX13_BUCKET_SIZE 0x32D
+#define R_XGS_TX14_BUCKET_SIZE 0x32E
+#define R_XGS_TX15_BUCKET_SIZE 0x32F
+#define R_XGS_JFR_BUCKET_SIZE 0x330
+#define R_XGS_RFR_BUCKET_SIZE 0x331
+
+#define R_CC_CPU0_0 0x380
+#define R_CC_CPU1_0 0x388
+#define R_CC_CPU2_0 0x390
+#define R_CC_CPU3_0 0x398
+#define R_CC_CPU4_0 0x3a0
+#define R_CC_CPU5_0 0x3a8
+#define R_CC_CPU6_0 0x3b0
+#define R_CC_CPU7_0 0x3b8
+
+#define XLR_GMAC_BLK_SZ (XLR_IO_GMAC_1_OFFSET - \
+ XLR_IO_GMAC_0_OFFSET)
+
+/* Constants used for configuring the devices */
+
+#define RGE_TX_THRESHOLD 1024
+#define RGE_TX_Q_SIZE 1024
+
+#define MAC_B2B_IPG 88
+
+#define NLGE_PREPAD_LEN 32
+
+/* frame sizes need to be cacheline aligned */
+#define MAX_FRAME_SIZE (1536 + NLGE_PREPAD_LEN)
+#define MAX_FRAME_SIZE_JUMBO 9216
+#define RGE_TX_THRESHOLD_BYTES ETHER_MAX_LEN
+
+#define MAC_SKB_BACK_PTR_SIZE SMP_CACHE_BYTES
+#define MAC_PREPAD 0
+#define BYTE_OFFSET 2
+#define XLR_RX_BUF_SIZE (MAX_FRAME_SIZE + BYTE_OFFSET + \
+ MAC_PREPAD + MAC_SKB_BACK_PTR_SIZE + SMP_CACHE_BYTES)
+#define MAC_CRC_LEN 4
+#define MAX_NUM_MSGRNG_STN_CC 128
+#define MAX_MSG_SND_ATTEMPTS 100 /* 13 stns x 4 entry msg/stn +
+ headroom */
+
+#define MAC_FRIN_TO_BE_SENT_THRESHOLD 16
+
+#define MAX_NUM_DESC_SPILL 1024
+#define MAX_FRIN_SPILL (MAX_NUM_DESC_SPILL << 2)
+#define MAX_FROUT_SPILL (MAX_NUM_DESC_SPILL << 2)
+#define MAX_CLASS_0_SPILL (MAX_NUM_DESC_SPILL << 2)
+#define MAX_CLASS_1_SPILL (MAX_NUM_DESC_SPILL << 2)
+#define MAX_CLASS_2_SPILL (MAX_NUM_DESC_SPILL << 2)
+#define MAX_CLASS_3_SPILL (MAX_NUM_DESC_SPILL << 2)
+
+#define XLR_MAX_CORE 8
+
+#define XLR_MAX_NLNA 3
+#define XLR_MAX_MACS 8
+#define XLR_MAX_TX_FRAGS 14
+#define MAX_P2D_DESC_PER_PORT 512
+
+#define PHY_STATUS_RETRIES 25000
+
+/* Structs representing hardware data structures */
+struct size_1_desc {
+ uint64_t entry0;
+};
+
+struct size_2_desc {
+ uint64_t entry0;
+ uint64_t entry1;
+};
+
+struct size_3_desc {
+ uint64_t entry0;
+ uint64_t entry1;
+ uint64_t entry2;
+};
+
+struct size_4_desc {
+ uint64_t entry0;
+ uint64_t entry1;
+ uint64_t entry2;
+ uint64_t entry3;
+};
+
+struct fr_desc {
+ struct size_1_desc d1;
+};
+
+union rx_tx_desc {
+ struct size_2_desc d2;
+ /* struct size_3_desc d3; */
+ /* struct size_4_desc d4; */
+};
+
+
+extern unsigned char xlr_base_mac_addr[];
+
+/* Driver data structures and enums */
+
+typedef enum {
+ xlr_mac_speed_10, xlr_mac_speed_100,
+ xlr_mac_speed_1000, xlr_mac_speed_rsvd
+} xlr_mac_speed_t;
+
+typedef enum {
+ xlr_mac_duplex_auto, xlr_mac_duplex_half,
+ xlr_mac_duplex_full
+} xlr_mac_duplex_t;
+
+typedef enum {
+ xlr_mac_link_down,
+ xlr_mac_link_up,
+} xlr_mac_link_t;
+
+typedef enum {
+ xlr_mac_fc_auto, xlr_mac_fc_disabled, xlr_mac_fc_frame,
+ xlr_mac_fc_collision, xlr_mac_fc_carrier
+} xlr_mac_fc_t;
+
+enum {
+ SGMII_SPEED_10 = 0x00000000,
+ SGMII_SPEED_100 = 0x02000000,
+ SGMII_SPEED_1000 = 0x04000000,
+};
+
+struct nlge_softc;
+
+/*
+ * A data-structure to hold a set of related ports. The "sense" in which they
+ * are related is defined by the user of this data-structure.
+ *
+ * One example: a set of ports that are controlled thru a single MDIO line.
+ */
+struct nlge_port_set {
+ struct nlge_softc **port_vec;
+ uint32_t vec_sz;
+};
+
+/*
+ * nlna_softc has Network Accelerator (NA) attributes that are necessary to
+ * configure the h/w registers of this block. All the commmon configuration
+ * for a set of GMAC ports controlled by an NA is done from here.
+ */
+struct nlna_softc {
+ device_t nlna_dev;
+
+ uint32_t num_ports;
+ int na_type;
+ int mac_type;
+ xlr_reg_t *base;
+
+ struct fr_desc *frin_spill;
+ struct fr_desc *frout_spill;
+ union rx_tx_desc *class_0_spill;
+ union rx_tx_desc *class_1_spill;
+ union rx_tx_desc *class_2_spill;
+ union rx_tx_desc *class_3_spill;
+ uint32_t rfrbucket;
+ uint32_t station_id;
+
+ struct nlge_softc *child_sc[XLR_MAX_MACS];
+
+ /*
+ * Set of ports controlled/configured by the MII line
+ * of this network accelerator.
+ */
+ struct nlge_port_set mdio_set;
+ struct nlge_softc *mdio_sc[XLR_MAX_MACS];
+};
+
+struct nlge_softc {
+ struct ifnet *nlge_if; /* should be first member - cf.
+ mii.c:miibus_attach() */
+ struct mii_data nlge_mii;
+ struct nlge_port_set *mdio_pset;
+ device_t nlge_dev;
+ device_t mii_bus;
+ xlr_reg_t *base;
+ xlr_reg_t *mii_base;
+ xlr_reg_t *pcs_addr;
+ xlr_reg_t *serdes_addr;
+ int port_type;
+ int if_flags;
+ xlr_mac_speed_t speed;
+ xlr_mac_duplex_t duplex;
+ xlr_mac_link_t link;
+ xlr_mac_fc_t flow_ctrl;
+ uint32_t id;
+ uint32_t instance;
+ uint32_t phy_addr;
+ uint32_t tx_bucket_id;
+ uint8_t dev_addr[ETHER_ADDR_LEN];
+ struct mtx sc_lock;
+};
+
+
+struct nlge_tx_desc {
+ uint64_t frag[XLR_MAX_TX_FRAGS + 2];
+};
+
+#define MAX_TX_RING_SIZE (XLR_MAX_MACS * MAX_P2D_DESC_PER_PORT *\
+ sizeof(struct p2d_tx_desc))
+
+#define NLGE_WRITE(base, off, val) xlr_write_reg(base, off, val)
+#define NLGE_READ(base, off) xlr_read_reg(base, off)
+#define NLGE_UPDATE(base, off, val, mask) \
+ do { \
+ uint32_t rd_val, wrt_val; \
+ rd_val = NLGE_READ(base, off); \
+ wrt_val = (rd_val & ~mask) | (val & mask); \
+ NLGE_WRITE(base, off, wrt_val); \
+ } while (0)
+
+#define NLGE_LOCK_INIT(_sc, _name) \
+ mtx_init(&(_sc)->sc_lock, _name, MTX_NETWORK_LOCK, MTX_DEF)
+#define NLGE_LOCK_DESTROY(_sc) mtx_destroy(&(_sc)->sc_lock)
+#define NLGE_LOCK(_sc) mtx_lock(&(_sc)->sc_lock)
+#define NLGE_UNLOCK(_sc) mtx_unlock(&(_sc)->sc_lock)
+#define NLGE_LOCK_ASSERT(_sc) mtx_assert(&(_sc)->sc_lock, MA_OWNED)
+
Property changes on: trunk/sys/mips/rmi/dev/nlge/if_nlge.h
___________________________________________________________________
Added: svn:eol-style
## -0,0 +1 ##
+native
\ No newline at end of property
Added: svn:keywords
## -0,0 +1 ##
+MidnightBSD=%H
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+text/plain
\ No newline at end of property
Added: trunk/sys/mips/rmi/dev/sec/desc.h
===================================================================
--- trunk/sys/mips/rmi/dev/sec/desc.h (rev 0)
+++ trunk/sys/mips/rmi/dev/sec/desc.h 2018-05-26 21:55:02 UTC (rev 9987)
@@ -0,0 +1,3069 @@
+/* $MidnightBSD$ */
+/*-
+ * Copyright (c) 2003-2009 RMI Corporation
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * 3. Neither the name of RMI Corporation, nor the names of its contributors,
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ * $FreeBSD: stable/10/sys/mips/rmi/dev/sec/desc.h 212763 2010-09-16 20:23:22Z jchandra $
+ * RMI_BSD */
+#ifndef _DESC_H_
+#define _DESC_H_
+
+
+#define ONE_BIT 0x0000000000000001ULL
+#define TWO_BITS 0x0000000000000003ULL
+#define THREE_BITS 0x0000000000000007ULL
+#define FOUR_BITS 0x000000000000000fULL
+#define FIVE_BITS 0x000000000000001fULL
+#define SIX_BITS 0x000000000000003fULL
+#define SEVEN_BITS 0x000000000000007fULL
+#define EIGHT_BITS 0x00000000000000ffULL
+#define NINE_BITS 0x00000000000001ffULL
+#define ELEVEN_BITS 0x00000000000007ffULL
+#define TWELVE_BITS 0x0000000000000fffULL
+#define FOURTEEN_BITS 0x0000000000003fffULL
+#define TWENTYFOUR_BITS 0x0000000000ffffffULL
+#define THIRTY_TWO_BITS 0x00000000ffffffffULL
+#define THIRTY_FIVE_BITS 0x00000007ffffffffULL
+#define FOURTY_BITS 0x000000ffffffffffULL
+
+#define MSG_IN_CTL_LEN_BASE 40
+#define MSG_IN_CTL_ADDR_BASE 0
+
+#define GET_FIELD(word,field) \
+ ((word) & (field ## _MASK)) >> (field ## _LSB)
+
+#define FIELD_VALUE(field,value) (((value) & (field ## _BITS)) << (field ## _LSB))
+
+/*
+ * NOTE: this macro expects 'word' to be uninitialized (i.e. zeroed)
+ */
+#define SET_FIELD(word,field,value) \
+ { (word) |= (((value) & (field ## _BITS)) << (field ## _LSB)); }
+
+/*
+ * This macro clears 'word', then sets the value
+ */
+#define CLEAR_SET_FIELD(word,field,value) \
+ { (word) &= ~((field ## _BITS) << (field ## _LSB)); \
+ (word) |= (((value) & (field ## _BITS)) << (field ## _LSB)); }
+
+/*
+ * NOTE: May be used to build value specific mask
+ * (e.g. GEN_MASK(CTL_DSC_CPHR_3DES,CTL_DSC_CPHR_LSB)
+ */
+#define GEN_MASK(bits,lsb) ((bits) << (lsb))
+
+
+
+
+/*
+ * Security block data and control exchange
+ *
+ * A 2-word message ring descriptor is used to pass a pointer to the control descriptor data structure
+ * and a pointer to the packet descriptor data structure:
+ *
+ * 63 61 60 54 53 52 49 48 45 44 40
+ * 39 5 4 0
+ * ---------------------------------------------------------------------------------------------------------------------------------------------------------
+ * | Ctrl | Resp Dest Id Entry0 | IF_L2ALLOC | UNUSED | Control Length | UNUSED
+ * | 35 MSB of address of control descriptor data structure | Software Scratch0
+ * |
+ * ---------------------------------------------------------------------------------------------------------------------------------------------------------
+ * 3 7 1 4 4 5
+ * 35 5
+ *
+ * 63 61 60 54 53 52 51 50 46 45 44 40 39 5 4 0
+ * ---------------------------------------------------------------------------------------------------------------------------------------------------------
+ * | Ctrl | UNUSED | WRB_COH | WRB_L2ALLOC | DF_PTR_L2ALLOC | UNUSED | Data Length | UNUSED | 35 MSB of address of packet descriptor data structure | UNUSED |
+ * ---------------------------------------------------------------------------------------------------------------------------------------------------------
+ * 3 7 1 1 1 5 1 5 35 5
+ *
+ * Addresses assumed to be cache-line aligned, i.e., Address[4:0] ignored (using 5'h00 instead)
+ *
+ * Control length is the number of control cachelines to be read so user needs
+ * to round up
+ * the control length to closest integer multiple of 32 bytes. Note that at
+ * present (08/12/04)
+ * the longest (sensical) ctrl structure is <= 416 bytes, i.e., 13 cachelines.
+ *
+ * The packet descriptor data structure size is fixed at 1 cacheline (32 bytes).
+ * This effectively makes "Data Length" a Load/NoLoad bit. NoLoad causes an abort.
+ *
+ *
+ * Upon completion of operation, the security block returns a 2-word free descriptor
+ * in the following format:
+ *
+ * 63 61 60 54 53 52 51 49 48 47 40 39 0
+ * ----------------------------------------------------------------------------------------------------------------------------
+ * | Ctrl | Destination Id | 2'b00 | Desc Ctrl | 1'b0 | Instruction Error | Address of control descriptor data structure |
+ * ----------------------------------------------------------------------------------------------------------------------------
+ * | Ctrl | Destination Id | 2'b00 | Desc Ctrl | 1'b0 | Data Error | Address of packet descriptor data structure |
+ * ----------------------------------------------------------------------------------------------------------------------------
+ *
+ * The Instruction and Data Error codes are enumerated in the
+ * ControlDescriptor and PacketDescriptor sections below
+ *
+ */
+
+
+/*
+ * Operating assumptions
+ * =====================
+ *
+ *
+ * -> For all IpSec ops, I assume that all the IP/IPSec/TCP headers
+ * and the data are present at the specified source addresses.
+ * I also assume that all necessary header data already exists
+ * at the destination. Additionally, in AH I assume that all
+ * mutable fields (IP.{TOS, Flags, Offset, TTL, Header_Checksum})
+ * and the AH.Authentication_Data have been zeroed by the client.
+ *
+ *
+ * -> In principle, the HW can calculate TCP checksums on both
+ * incoming and outgoing data; however, since the TCP header
+ * contains the TCP checksum of the plain payload and the header
+ * is encrypted, two passes would be necessary to do checksum + encryption
+ * for outgoing messages;
+ * therefore the checksum engine will likely only be used during decryption
+ * (incoming).
+ *
+ *
+ * -> For all operations involving TCP checksum, I assume the client has filled
+ * the TCP checksum field with the appropriate value:
+ *
+ * - 0 for generation phase
+ * - actual value for verification phase (expecting 0 result)
+ *
+ *
+ * -> For ESP tunnel, the original IP header exists between the end of the
+ * ESP header and the beginning of the TCP header; it is assumed that the
+ * maximum length of this header is 16 k(32bit)words (used in CkSum_Offset).
+ *
+ *
+ * -> The authentication data is merely written to the destination address;
+ * the client is left with the task of comparing to the data in packet
+ * in decrypt.
+ *
+ * -> PacketDescriptor_t.dstLLWMask relevant to AES CTR mode only but it will
+ * affect all AES-related operations. It will not affect DES/3DES/bypass ops.
+ * The mask is applied to data as it emerges from the AES engine for the sole
+ * purpose of providing the authenticator and cksum engines with correct data.
+ * CAVEAT: the HW does not mask the incoming data. It is the user's responsibility
+ * to set to 0 the corresponding data in memory. If the surplus data is not masked
+ * in memory, cksum/auth results will be incorrect if those engines receive data
+ * straight from memory (i.e., not from cipher, as it happens while decoding)
+ */
+
+/*
+ * Fragmentation and offset related notes
+ * ======================================
+ *
+ *
+ * A) Rebuilding packets from fragments on dword boundaries. The discussion
+ * below is exemplified by tests memcpy_all_off_frags and memcpy_same_off_frags
+ *
+ * 1) The Offset before data/iv on first fragment is ALWAYS written back
+ * Non-zero dst dword or global offsets may cause more data to be
+ * written than the user-specified length.
+ *
+ *
+ * Example:
+ * --------
+ *
+ * Below is a source (first fragment) packet (@ ADD0 cache-aligned address).
+ * Assume we just copy it and relevant data starts on
+ * dword 3 so Cipher_Offset = IV_Offset = 3 (dwords).
+ * D0X denotes relevant data and G denotes dont care data.
+ * Offset data is also copied so Packet_Legth = 9 (dwords) * 8 = 72 (bytes)
+ * Segment_src_address = ADD0
+ *
+ * If we want to, e.g., copy so that the relevant (i.e., D0X) data
+ * starts at (cache-aligned address) ADD1, we need to specify
+ * Dst_dword_offset = 1 so D00 is moved from dword position 3 to 0 on next cache-line
+ * Cipher_dst_address = ADD1 - 0x20 so D00 is written to ADD1
+ *
+ * Note that the security engine always writes full cachelines
+ * therefore, data written to dword0 0 of ADD1 (denoted w/ ?) is what the sec pipe
+ * write back buffer contained from previous op.
+ *
+ *
+ * SOURCE: DESTINATION:
+ * ------- ------------
+ *
+ * Segment_src_address = ADD0 Cipher_dst_address = ADD1 - 0x20
+ * Packet_Legth = 72 Dst_dword_offset = 1
+ * Cipher_Offset = 3
+ * IV_Offset = 3
+ * Use_IV = ANY
+ *
+ *
+ *
+ * 3 2 1 0 3 2 1 0
+ * ----------------------- -----------------------
+ * | D00 | G | G | G | <- ADD0 | G | G | G | ? | <- ADD1 - 0x20
+ * ----------------------- -----------------------
+ * | D04 | D03 | D02 | D01 | | D03 | D02 | D01 | D00 | <- ADD1
+ * ----------------------- -----------------------
+ * | | | | D05 | | | | D05 | D04 |
+ * ----------------------- -----------------------
+ *
+ * 2) On fragments following the first, IV_Offset is overloaded to mean data offset
+ * (number of dwords to skip from beginning of cacheline before starting processing)
+ * and Use_IV is overloaded to mean do writeback the offset (in the clear).
+ * These fields in combination with Dst_dword_offset allow packet fragments with
+ * arbitrary boundaries/lengthd to be reasembled.
+ *
+ *
+ * Example:
+ * --------
+ *
+ * Assume data above was first fragment of a packet we'd like to merge to
+ * (second) fragment below located at ADD2. The written data should follow
+ * the previous data without gaps or overwrites. To achieve this, one should
+ * assert the "Next" field on the previous fragment and use self-explanatory
+ * set of parameters below
+ *
+ *
+ * SOURCE: DESTINATION:
+ * ------- ------------
+ *
+ * Segment_src_address = ADD2 Cipher_dst_address = ADD1 + 0x20
+ * Packet_Legth = 104 Dst_dword_offset = 1
+ * IV_Offset = 1
+ * Use_IV = 0
+ *
+ *
+ *
+ * 3 2 1 0 3 2 1 0
+ * ----------------------- -----------------------
+ * | D12 | D11 | D10 | G | <- ADD2 | G | G | G | ? | <- ADD1 - 0x20
+ * ----------------------- -----------------------
+ * | D16 | D15 | D14 | D13 | | D03 | D02 | D01 | D00 | <- ADD1
+ * ----------------------- -----------------------
+ * | D1a | D19 | D18 | D17 | | D11 | D10 | D05 | D04 | <- ADD1 + 0x20
+ * ----------------------- -----------------------
+ * | | | | D1b | | D15 | D14 | D13 | D12 |
+ * ----------------------- -----------------------
+ * | D19 | D18 | D17 | D16 |
+ * -----------------------
+ * | | | D1b | D1a |
+ * -----------------------
+ *
+ * It is note-worthy that the merging can only be achieved if Use_IV is 0. Indeed, the security
+ * engine always writes full lines, therefore ADD1 + 0x20 will be re-written. Setting Use_IV to 0
+ * will allow the sec pipe write back buffer to preserve D04, D05 from previous frag and only
+ * receive D10, D11 thereby preserving the integrity of the previous data.
+ *
+ * 3) On fragments following the first, !UseIV in combination w/ Dst_dword_offset >= (4 - IV_Offset)
+ * will cause a wraparound of the write thus achieving all 16 possible (Initial_Location, Final_Location)
+ * combinations for the data.
+ *
+ *
+ * Example:
+ * --------
+ *
+ * Contiguously merging 2 data sets above with a third located at ADD3. If this is the last fragment,
+ * reset its Next bit.
+ *
+ *
+ * SOURCE: DESTINATION:
+ * ------- ------------
+ *
+ * Segment_src_address = ADD3 Cipher_dst_address = ADD1 + 0x80
+ * Packet_Legth = 152 Dst_dword_offset = 3
+ * IV_Offset = 3
+ * Use_IV = 0
+ *
+ *
+ *
+ * 3 2 1 0 3 2 1 0
+ * ----------------------- -----------------------
+ * | D20 | G | G | G | <- ADD2 | G | G | G | ? | <- ADD1 - 0x20
+ * ----------------------- -----------------------
+ * | D24 | D23 | D22 | D21 | | D03 | D02 | D01 | D00 | <- ADD1
+ * ----------------------- -----------------------
+ * | D28 | D27 | D26 | D25 | | D11 | D10 | D05 | D04 | <- ADD1 + 0x20
+ * ----------------------- -----------------------
+ * | D2c | D2b | D2a | D29 | | D15 | D14 | D13 | D12 |
+ * ----------------------- -----------------------
+ * | | D2f | D2e | D2d | | D19 | D18 | D17 | D16 |
+ * ----------------------- -----------------------
+ * | D21 | D20 | D1b | D1a | <- ADD1 + 0x80
+ * -----------------------
+ * | D25 | D24 | D23 | D22 |
+ * -----------------------
+ * | D29 | D28 | D27 | D26 |
+ * -----------------------
+ * | D2d | D2c | D2b | D2a |
+ * -----------------------
+ * |(D2d)|(D2c)| D2f | D2e |
+ * -----------------------
+ *
+ * It is worth noticing that always writing full-lines causes the last 2 dwords in the reconstituted
+ * packet to be unnecessarily written: (D2d) and (D2c)
+ *
+ *
+ *
+ * B) Implications of fragmentation on AES
+ *
+ * 1) AES is a 128 bit block cipher; therefore it requires an even dword total data length
+ * Data fragments (provided there are more than 1) are allowed to have odd dword
+ * data lengths provided the total length (cumulated over fragments) is an even dword
+ * count; an error will be generated otherwise, upon receiving the last fragment descriptor
+ * (see error conditions below).
+ *
+ * 2) While using fragments with AES, a fragment (other than first) starting with a != 0 (IV) offset
+ * while the subsequent total dword count given to AES is odd may not be required to write
+ * its offset (UseIV). Doing so will cause an error (see error conditions below).
+ *
+ *
+ * Example:
+ * --------
+ *
+ * Suppose the first fragment has an odd DATA dword count and USES AES (as seen below)
+ *
+ * SOURCE: DESTINATION:
+ * ------- ------------
+ *
+ * Segment_src_address = ADD0 Cipher_dst_address = ADD1
+ * Packet_Legth = 64 Dst_dword_offset = 1
+ * Cipher_Offset = 3
+ * IV_Offset = 1
+ * Use_IV = 1
+ * Cipher = Any AES
+ * Next = 1
+ *
+ *
+ *
+ *
+ * 3 2 1 0 3 2 1 0
+ * ----------------------- -----------------------
+ * | D00 | IV1 | IV0 | G | <- ADD0 | E00 | IV1 | IV0 | G | <- ADD1
+ * ----------------------- -----------------------
+ * | D04 | D03 | D02 | D01 | | X | E03 | E02 | E01 |
+ * ----------------------- -----------------------
+ *
+ * At the end of processing of the previous fragment, the AES engine input buffer has D04
+ * and waits for next dword, therefore the writeback buffer cannot finish writing the fragment
+ * to destination (X instead of E04).
+ *
+ * If a second fragment now arrives with a non-0 offset and requires the offset data to be
+ * written to destination, the previous write (still needing the arrival of the last dword
+ * required by the AES to complete the previous operation) cannot complete before the present
+ * should start causing a deadlock.
+ */
+
+/*
+ * Command Control Word for Message Ring Descriptor
+ */
+
+/* #define MSG_CMD_CTL_CTL */
+#define MSG_CMD_CTL_CTL_LSB 61
+#define MSG_CMD_CTL_CTL_BITS THREE_BITS
+#define MSG_CMD_CTL_CTL_MASK (MSG_CMD_CTL_CTL_BITS << MSG_CMD_CTL_CTL_LSB)
+
+/* #define MSG_CMD_CTL_ID */
+#define MSG_CMD_CTL_ID_LSB 54
+#define MSG_CMD_CTL_ID_BITS SEVEN_BITS
+#define MSG_CMD_CTL_ID_MASK (MSG_CMD_CTL_ID_BITS << MSG_CMD_CTL_ID_LSB)
+
+/* #define MSG_CMD_CTL_LEN */
+#define MSG_CMD_CTL_LEN_LSB 45
+#define MSG_CMD_CTL_LEN_BITS FOUR_BITS
+#define MSG_CMD_CTL_LEN_MASK (MSG_CMD_CTL_LEN_BITS << MSG_CMD_CTL_LEN_LSB)
+
+
+/* #define MSG_CMD_CTL_ADDR */
+#define MSG_CMD_CTL_ADDR_LSB 0
+#define MSG_CMD_CTL_ADDR_BITS FOURTY_BITS
+#define MSG_CMD_CTL_ADDR_MASK (MSG_CMD_CTL_ADDR_BITS << MSG_CMD_CTL_ADDR_LSB)
+
+#define MSG_CMD_CTL_MASK (MSG_CMD_CTL_CTL_MASK | \
+ MSG_CMD_CTL_LEN_MASK | MSG_CMD_CTL_ADDR_MASK)
+
+/*
+ * Command Data Word for Message Ring Descriptor
+ */
+
+/* #define MSG_IN_DATA_CTL */
+#define MSG_CMD_DATA_CTL_LSB 61
+#define MSG_CMD_DATA_CTL_BITS THREE_BITS
+#define MSG_CMD_DATA_CTL_MASK (MSG_CMD_DATA_CTL_BITS << MSG_CMD_DATA_CTL_LSB)
+
+/* #define MSG_CMD_DATA_LEN */
+#define MSG_CMD_DATA_LEN_LOAD 1
+#define MSG_CMD_DATA_LEN_LSB 45
+#define MSG_CMD_DATA_LEN_BITS ONE_BIT
+#define MSG_CMD_DATA_LEN_MASK (MSG_CMD_DATA_LEN_BITS << MSG_CMD_DATA_LEN_LSB)
+
+/* #define MSG_CMD_DATA_ADDR */
+#define MSG_CMD_DATA_ADDR_LSB 0
+#define MSG_CMD_DATA_ADDR_BITS FOURTY_BITS
+#define MSG_CMD_DATA_ADDR_MASK (MSG_CMD_DATA_ADDR_BITS << MSG_CMD_DATA_ADDR_LSB)
+
+#define MSG_CMD_DATA_MASK (MSG_CMD_DATA_CTL_MASK | \
+ MSG_CMD_DATA_LEN_MASK | MSG_CMD_DATA_ADDR_MASK)
+
+
+/*
+ * Upon completion of operation, the Sec block returns a 2-word free descriptor
+ * in the following format:
+ *
+ * 63 61 60 54 53 52 51 49 48 40 39 0
+ * ----------------------------------------------------------------------------
+ * | Ctrl | Destination Id | 2'b00 | Desc Ctrl | Control Error | Source Address |
+ * ----------------------------------------------------------------------------
+ * | Ctrl | Destination Id | 2'b00 | Desc Ctrl | Data Error | Dest Address |
+ * ----------------------------------------------------------------------------
+ *
+ * The Control and Data Error codes are enumerated below
+ *
+ * Error conditions
+ * ================
+ *
+ * Control Error Code Control Error Condition
+ * ------------------ ---------------------------
+ * 9'h000 No Error
+ * 9'h001 Unknown Cipher Op ( Cipher == 3'h{6,7})
+ * 9'h002 Unknown or Illegal Mode ((Mode == 3'h{2,3,4} & !AES) | (Mode == 3'h{5,6,7}))
+ * 9'h004 Unsupported CkSum Src (CkSum_Src == 2'h{2,3} & CKSUM)
+ * 9'h008 Forbidden CFB Mask (AES & CFBMode & UseNewKeysCFBMask & CFBMask[7] & (| CFBMask[6:0]))
+ * 9'h010 Unknown Ctrl Op ((| Ctrl[63:37]) | (| Ctrl[15:14]))
+ * 9'h020 UNUSED
+ * 9'h040 UNUSED
+ * 9'h080 Data Read Error
+ * 9'h100 Descriptor Ctrl Field Error (D0.Ctrl != SOP || D1.Ctrl != EOP)
+ *
+ * Data Error Code Data Error Condition
+ * --------------- --------------------
+ * 9'h000 No Error
+ * 9'h001 Insufficient Data To Cipher (Packet_Length <= (Cipher_Offset or IV_Offset))
+ * 9'h002 Illegal IV Location ((Cipher_Offset < IV_Offset) | (Cipher_Offset <= IV_Offset & AES & ~CTR))
+ * 9'h004 Illegal Wordcount To AES (Packet_Length[3] != Cipher_Offset[0] & AES)
+ * 9'h008 Illegal Pad And ByteCount Spec (Hash_Byte_Count != 0 & !Pad_Hash)
+ * 9'h010 Insufficient Data To CkSum ({Packet_Length, 1'b0} <= CkSum_Offset)
+ * 9'h020 Unknown Data Op ((| dstLLWMask[63:60]) | (| dstLLWMask[57:40]) | (| authDst[63:40]) | (| ckSumDst[63:40]))
+ * 9'h040 Insufficient Data To Auth ({Packet_Length} <= Auth_Offset)
+ * 9'h080 Data Read Error
+ * 9'h100 UNUSED
+ */
+
+/*
+ * Result Control Word for Message Ring Descriptor
+ */
+
+/* #define MSG_RSLT_CTL_CTL */
+#define MSG_RSLT_CTL_CTL_LSB 61
+#define MSG_RSLT_CTL_CTL_BITS THREE_BITS
+#define MSG_RSLT_CTL_CTL_MASK \
+ (MSG_RSLT_CTL_CTL_BITS << MSG_RSLT_CTL_CTL_LSB)
+
+/* #define MSG_RSLT_CTL_DST_ID */
+#define MSG_RSLT_CTL_DST_ID_LSB 54
+#define MSG_RSLT_CTL_DST_ID_BITS SEVEN_BITS
+#define MSG_RSLT_CTL_DST_ID_MASK \
+ (MSG_RSLT_CTL_DST_ID_BITS << MSG_RSLT_CTL_DST_ID_LSB)
+
+/* #define MSG_RSLT_CTL_DSC_CTL */
+#define MSG_RSLT_CTL_DSC_CTL_LSB 49
+#define MSG_RSLT_CTL_DSC_CTL_BITS THREE_BITS
+#define MSG_RSLT_CTL_DSC_CTL_MASK \
+ (MSG_RSLT_CTL_DSC_CTL_BITS << MSG_RSLT_CTL_DSC_CTL_LSB)
+
+/* #define MSG_RSLT_CTL_INST_ERR */
+#define MSG_RSLT_CTL_INST_ERR_LSB 40
+#define MSG_RSLT_CTL_INST_ERR_BITS NINE_BITS
+#define MSG_RSLT_CTL_INST_ERR_MASK \
+ (MSG_RSLT_CTL_INST_ERR_BITS << MSG_RSLT_CTL_INST_ERR_LSB)
+
+/* #define MSG_RSLT_CTL_DSC_ADDR */
+#define MSG_RSLT_CTL_DSC_ADDR_LSB 0
+#define MSG_RSLT_CTL_DSC_ADDR_BITS FOURTY_BITS
+#define MSG_RSLT_CTL_DSC_ADDR_MASK \
+ (MSG_RSLT_CTL_DSC_ADDR_BITS << MSG_RSLT_CTL_DSC_ADDR_LSB)
+
+/* #define MSG_RSLT_CTL_MASK */
+#define MSG_RSLT_CTL_MASK \
+ (MSG_RSLT_CTL_CTRL_MASK | MSG_RSLT_CTL_DST_ID_MASK | \
+ MSG_RSLT_CTL_DSC_CTL_MASK | MSG_RSLT_CTL_INST_ERR_MASK | \
+ MSG_RSLT_CTL_DSC_ADDR_MASK)
+
+/*
+ * Result Data Word for Message Ring Descriptor
+ */
+/* #define MSG_RSLT_DATA_CTL */
+#define MSG_RSLT_DATA_CTL_LSB 61
+#define MSG_RSLT_DATA_CTL_BITS THREE_BITS
+#define MSG_RSLT_DATA_CTL_MASK \
+ (MSG_RSLT_DATA_CTL_BITS << MSG_RSLT_DATA_CTL_LSB)
+
+/* #define MSG_RSLT_DATA_DST_ID */
+#define MSG_RSLT_DATA_DST_ID_LSB 54
+#define MSG_RSLT_DATA_DST_ID_BITS SEVEN_BITS
+#define MSG_RSLT_DATA_DST_ID_MASK \
+ (MSG_RSLT_DATA_DST_ID_BITS << MSG_RSLT_DATA_DST_ID_LSB)
+
+/* #define MSG_RSLT_DATA_DSC_CTL */
+#define MSG_RSLT_DATA_DSC_CTL_LSB 49
+#define MSG_RSLT_DATA_DSC_CTL_BITS THREE_BITS
+#define MSG_RSLT_DATA_DSC_CTL_MASK \
+ (MSG_RSLT_DATA_DSC_CTL_BITS << MSG_RSLT_DATA_DSC_CTL_LSB)
+
+/* #define MSG_RSLT_DATA_INST_ERR */
+#define MSG_RSLT_DATA_INST_ERR_LSB 40
+#define MSG_RSLT_DATA_INST_ERR_BITS NINE_BITS
+#define MSG_RSLT_DATA_INST_ERR_MASK \
+ (MSG_RSLT_DATA_INST_ERR_BITS << MSG_RSLT_DATA_INST_ERR_LSB)
+
+/* #define MSG_RSLT_DATA_DSC_ADDR */
+#define MSG_RSLT_DATA_DSC_ADDR_LSB 0
+#define MSG_RSLT_DATA_DSC_ADDR_BITS FOURTY_BITS
+#define MSG_RSLT_DATA_DSC_ADDR_MASK \
+ (MSG_RSLT_DATA_DSC_ADDR_BITS << MSG_RSLT_DATA_DSC_ADDR_LSB)
+
+#define MSG_RSLT_DATA_MASK \
+ (MSG_RSLT_DATA_CTRL_MASK | MSG_RSLT_DATA_DST_ID_MASK | \
+ MSG_RSLT_DATA_DSC_CTL_MASK | MSG_RSLT_DATA_INST_ERR_MASK | \
+ MSG_RSLT_DATA_DSC_ADDR_MASK)
+
+
+/*
+ * Common Message Definitions
+ *
+ */
+
+/* #define MSG_CTL_OP_ADDR */
+#define MSG_CTL_OP_ADDR_LSB 0
+#define MSG_CTL_OP_ADDR_BITS FOURTY_BITS
+#define MSG_CTL_OP_ADDR_MASK (MSG_CTL_OP_ADDR_BITS << MSG_CTL_OP_ADDR_LSB)
+
+#define MSG_CTL_OP_TYPE
+#define MSG_CTL_OP_TYPE_LSB 3
+#define MSG_CTL_OP_TYPE_BITS TWO_BITS
+#define MSG_CTL_OP_TYPE_MASK \
+ (MSG_CTL_OP_TYPE_BITS << MSG_CTL_OP_TYPE_LSB)
+
+#define MSG0_CTL_OP_ENGINE_SYMKEY 0x01
+#define MSG0_CTL_OP_ENGINE_PUBKEY 0x02
+
+#define MSG1_CTL_OP_SYMKEY_PIPE0 0x00
+#define MSG1_CTL_OP_SYMKEY_PIPE1 0x01
+#define MSG1_CTL_OP_SYMKEY_PIPE2 0x02
+#define MSG1_CTL_OP_SYMKEY_PIPE3 0x03
+
+#define MSG1_CTL_OP_PUBKEY_PIPE0 0x00
+#define MSG1_CTL_OP_PUBKEY_PIPE1 0x01
+#define MSG1_CTL_OP_PUBKEY_PIPE2 0x02
+#define MSG1_CTL_OP_PUBKEY_PIPE3 0x03
+
+
+/* /----------------------------------------\
+ * | |
+ * | ControlDescriptor_s datastructure |
+ * | |
+ * \----------------------------------------/
+ *
+ *
+ * ControlDescriptor_t.Instruction
+ * -------------------------------
+ *
+ * 63 44 43 42 41 40 39 35 34 32 31 29 28
+ * --------------------------------------------------------------------------------------------------------------------
+ * || UNUSED || OverrideCipher | Arc4Wait4Save | SaveArc4State | LoadArc4State | Arc4KeyLen | Cipher | Mode | InCp_Key || ... CONT ...
+ * --------------------------------------------------------------------------------------------------------------------
+ * 20 1 1 1 1 5 3 3 1
+ * <-----------------------------------------------CIPHER--------------------------------------------------->
+ *
+ * 27 25 24 23 22 21 20 19 17 16 15 0
+ * -----------------------------------------------------------------------------
+ * || UNUSED | Hash_Hi | HMAC | Hash_Lo | InHs_Key || UNUSED || CkSum || UNUSED ||
+ * -----------------------------------------------------------------------------
+ * 3 1 1 2 1 3 1 16
+ * <---------------------HASH---------------------><-----------CKSUM----------->
+ *
+ * X0 CIPHER.Arc4Wait4Save = If op is Arc4 and it requires state saving, then
+ * setting this bit will cause the current op to
+ * delay subsequent op loading until saved state data
+ * becomes visible.
+ * CIPHER.OverrideCipher = Override encryption if PacketDescriptor_t.dstDataSettings.CipherPrefix
+ * is set; data will be copied out (and optionally auth/cksum)
+ * in the clear. This is used in GCM mode if auth only as we
+ * still need E(K, 0) calculated by cipher. Engine behavior is
+ * undefined if this bit is set and CipherPrefix is not.
+ * X0 SaveArc4State = Save Arc4 state at the end of Arc4 operation
+ * X0 LoadArc4State = Load Arc4 state at the beginning of an Arc4 operation
+ * This overriden by the InCp_Key setting for Arc4
+ * Arc4KeyLen = Length in bytes of Arc4 key (0 is interpreted as 32)
+ * Ignored for other ciphers
+ * For ARC4, IFetch/IDecode will always read exactly 4
+ * consecutive dwords into its CipherKey{0,3} regardless
+ * of this quantity; it will however only use the specified
+ * number of bytes.
+ * Cipher = 3'b000 Bypass
+ * 3'b001 DES
+ * 3'b010 3DES
+ * 3'b011 AES 128-bit key
+ * 3'b100 AES 192-bit key
+ * 3'b101 AES 256-bit key
+ * 3'b110 ARC4
+ * 3'b111 Kasumi f8
+ * Remainder UNDEFINED
+ * Mode = 3'b000 ECB
+ * 3'b001 CBC
+ * 3'b010 CFB (AES only, otherwise undefined)
+ * 3'b011 OFB (AES only, otherwise undefined)
+ * 3'b100 CTR (AES only, otherwise undefined)
+ * 3'b101 F8 (AES only, otherwise undefined)
+ * Remainder UNDEFINED
+ * InCp_Key = 1'b0 Preserve old Cipher Keys
+ * 1'b1 Load new Cipher Keys from memory to local registers
+ * and recalculate the Arc4 Sbox if Arc4 Cipher chosen;
+ * This overrides LoadArc4State setting.
+ * HASH.HMAC = 1'b0 Hash without HMAC
+ * 1'b1 Hash with HMAC
+ * Needs to be set to 0 for GCM and Kasumi F9 authenticators
+ * otherwise unpredictable results will be generated
+ * Hash = 2'b00 Hash NOP
+ * 2'b01 MD5
+ * 2'b10 SHA-1
+ * 2'b11 SHA-256
+ * 3'b100 SHA-384
+ * 3'b101 SHA-512
+ * 3'b110 GCM
+ * 3'b111 Kasumi f9
+ * InHs_Key = 1'b0 Preserve old HMAC Keys
+ * If GCM is selected as authenticator, leaving this bit
+ * at 0 will cause the engine to use the old H value.
+ * It will use the old SCI inside the decoder if
+ * CFBMask[1:0] == 2'b11.
+ * If Kasumi F9 authenticator, using 0 preserves
+ * old keys (IK) in decoder.
+ * 1'b1 Load new HMAC Keys from memory to local registers
+ * Setting this bit while Cipher=Arc4 and LoadArc4State=1
+ * causes the decoder to load the Arc4 state from the
+ * cacheline following the HMAC keys (Whether HASH.HMAC
+ * is set or not).
+ * If GCM is selected as authenticator, setting this bit
+ * causes both H (16 bytes) and SCI (8 bytes) to be loaded
+ * from memory to the decoder. H will be loaded to the engine
+ * but SCI is only loaded to the engine if CFBMask[1:0] == 2'b11.
+ * If Kasumi F9 authenticator, using 1 loads new keys (IK)
+ * from memory to decoder.
+ * CHECKSUM.CkSum = 1'b0 CkSum NOP
+ * 1'b1 INTERNET_CHECKSUM
+ *
+ *
+ *
+ */
+
+ /* #define CTRL_DSC_OVERRIDECIPHER */
+#define CTL_DSC_OVERRIDECIPHER_OFF 0
+#define CTL_DSC_OVERRIDECIPHER_ON 1
+#define CTL_DSC_OVERRIDECIPHER_LSB 43
+#define CTL_DSC_OVERRIDECIPHER_BITS ONE_BIT
+#define CTL_DSC_OVERRIDECIPHER_MASK (CTL_DSC_OVERRIDECIPHER_BITS << CTL_DSC_OVERRIDECIPHER_LSB)
+
+/* #define CTRL_DSC_ARC4_WAIT4SAVE */
+#define CTL_DSC_ARC4_WAIT4SAVE_OFF 0
+#define CTL_DSC_ARC4_WAIT4SAVE_ON 1
+#define CTL_DSC_ARC4_WAIT4SAVE_LSB 42
+#define CTL_DSC_ARC4_WAIT4SAVE_BITS ONE_BIT
+#define CTL_DSC_ARC4_WAIT4SAVE_MASK (CTL_DSC_ARC4_WAIT4SAVE_BITS << CTL_DSC_ARC4_WAIT4SAVE_LSB)
+
+/* #define CTRL_DSC_ARC4_SAVESTATE */
+#define CTL_DSC_ARC4_SAVESTATE_OFF 0
+#define CTL_DSC_ARC4_SAVESTATE_ON 1
+#define CTL_DSC_ARC4_SAVESTATE_LSB 41
+#define CTL_DSC_ARC4_SAVESTATE_BITS ONE_BIT
+#define CTL_DSC_ARC4_SAVESTATE_MASK (CTL_DSC_ARC4_SAVESTATE_BITS << CTL_DSC_ARC4_SAVESTATE_LSB)
+
+/* #define CTRL_DSC_ARC4_LOADSTATE */
+#define CTL_DSC_ARC4_LOADSTATE_OFF 0
+#define CTL_DSC_ARC4_LOADSTATE_ON 1
+#define CTL_DSC_ARC4_LOADSTATE_LSB 40
+#define CTL_DSC_ARC4_LOADSTATE_BITS ONE_BIT
+#define CTL_DSC_ARC4_LOADSTATE_MASK (CTL_DSC_ARC4_LOADSTATE_BITS << CTL_DSC_ARC4_LOADSTATE_LSB)
+
+/* #define CTRL_DSC_ARC4_KEYLEN */
+#define CTL_DSC_ARC4_KEYLEN_LSB 35
+#define CTL_DSC_ARC4_KEYLEN_BITS FIVE_BITS
+#define CTL_DSC_ARC4_KEYLEN_MASK (CTL_DSC_ARC4_KEYLEN_BITS << CTL_DSC_ARC4_KEYLEN_LSB)
+
+/* #define CTL_DSC_CPHR (cipher) */
+#define CTL_DSC_CPHR_BYPASS 0 /* undefined */
+#define CTL_DSC_CPHR_DES 1
+#define CTL_DSC_CPHR_3DES 2
+#define CTL_DSC_CPHR_AES128 3
+#define CTL_DSC_CPHR_AES192 4
+#define CTL_DSC_CPHR_AES256 5
+#define CTL_DSC_CPHR_ARC4 6
+#define CTL_DSC_CPHR_KASUMI_F8 7
+#define CTL_DSC_CPHR_LSB 32
+#define CTL_DSC_CPHR_BITS THREE_BITS
+#define CTL_DSC_CPHR_MASK (CTL_DSC_CPHR_BITS << CTL_DSC_CPHR_LSB)
+
+/* #define CTL_DSC_MODE */
+#define CTL_DSC_MODE_ECB 0
+#define CTL_DSC_MODE_CBC 1
+#define CTL_DSC_MODE_CFB 2
+#define CTL_DSC_MODE_OFB 3
+#define CTL_DSC_MODE_CTR 4
+#define CTL_DSC_MODE_F8 5
+#define CTL_DSC_MODE_LSB 29
+#define CTL_DSC_MODE_BITS THREE_BITS
+#define CTL_DSC_MODE_MASK (CTL_DSC_MODE_BITS << CTL_DSC_MODE_LSB)
+
+/* #define CTL_DSC_ICPHR */
+#define CTL_DSC_ICPHR_OKY 0 /* Old Keys */
+#define CTL_DSC_ICPHR_NKY 1 /* New Keys */
+#define CTL_DSC_ICPHR_LSB 28
+#define CTL_DSC_ICPHR_BITS ONE_BIT
+#define CTL_DSC_ICPHR_MASK (CTL_DSC_ICPHR_BITS << CTL_DSC_ICPHR_LSB)
+
+/* #define CTL_DSC_HASHHI */
+#define CTL_DSC_HASHHI_LSB 24
+#define CTL_DSC_HASHHI_BITS ONE_BIT
+#define CTL_DSC_HASHHI_MASK (CTL_DSC_HASHHI_BITS << CTL_DSC_HASHHI_LSB)
+
+/* #define CTL_DSC_HMAC */
+#define CTL_DSC_HMAC_OFF 0
+#define CTL_DSC_HMAC_ON 1
+#define CTL_DSC_HMAC_LSB 23
+#define CTL_DSC_HMAC_BITS ONE_BIT
+#define CTL_DSC_HMAC_MASK (CTL_DSC_HMAC_BITS << CTL_DSC_HMAC_LSB)
+
+/* #define CTL_DSC_HASH */
+#define CTL_DSC_HASH_NOP 0
+#define CTL_DSC_HASH_MD5 1
+#define CTL_DSC_HASH_SHA1 2
+#define CTL_DSC_HASH_SHA256 3
+#define CTL_DSC_HASH_SHA384 4
+#define CTL_DSC_HASH_SHA512 5
+#define CTL_DSC_HASH_GCM 6
+#define CTL_DSC_HASH_KASUMI_F9 7
+#define CTL_DSC_HASH_LSB 21
+#define CTL_DSC_HASH_BITS TWO_BITS
+#define CTL_DSC_HASH_MASK (CTL_DSC_HASH_BITS << CTL_DSC_HASH_LSB)
+
+/* #define CTL_DSC_IHASH */
+#define CTL_DSC_IHASH_OLD 0
+#define CTL_DSC_IHASH_NEW 1
+#define CTL_DSC_IHASH_LSB 20
+#define CTL_DSC_IHASH_BITS ONE_BIT
+#define CTL_DSC_IHASH_MASK (CTL_DSC_IHASH_BITS << CTL_DSC_IHASH_LSB)
+
+/* #define CTL_DSC_CKSUM */
+#define CTL_DSC_CKSUM_NOP 0
+#define CTL_DSC_CKSUM_IP 1
+#define CTL_DSC_CKSUM_LSB 16
+#define CTL_DSC_CKSUM_BITS ONE_BIT
+#define CTL_DSC_CKSUM_MASK (CTL_DSC_CKSUM_BITS << CTL_DSC_CKSUM_LSB)
+
+
+/*
+ * Component strcts and unions defining CipherHashInfo_u
+ */
+
+/* AES256, (ECB, CBC, OFB, CTR, CFB), HMAC (MD5, SHA-1, SHA-256) - 96 bytes */
+typedef struct AES256HMAC_s {
+ uint64_t cipherKey0;
+ uint64_t cipherKey1;
+ uint64_t cipherKey2;
+ uint64_t cipherKey3;
+ uint64_t hmacKey0;
+ uint64_t hmacKey1;
+ uint64_t hmacKey2;
+ uint64_t hmacKey3;
+ uint64_t hmacKey4;
+ uint64_t hmacKey5;
+ uint64_t hmacKey6;
+ uint64_t hmacKey7;
+} AES256HMAC_t, *AES256HMAC_pt;
+
+/* AES256, (ECB, CBC, OFB, CTR, CFB), HMAC (SHA-384, SHA-512) - 160 bytes */
+typedef struct AES256HMAC2_s {
+ uint64_t cipherKey0;
+ uint64_t cipherKey1;
+ uint64_t cipherKey2;
+ uint64_t cipherKey3;
+ uint64_t hmacKey0;
+ uint64_t hmacKey1;
+ uint64_t hmacKey2;
+ uint64_t hmacKey3;
+ uint64_t hmacKey4;
+ uint64_t hmacKey5;
+ uint64_t hmacKey6;
+ uint64_t hmacKey7;
+ uint64_t hmacKey8;
+ uint64_t hmacKey9;
+ uint64_t hmacKey10;
+ uint64_t hmacKey11;
+ uint64_t hmacKey12;
+ uint64_t hmacKey13;
+ uint64_t hmacKey14;
+ uint64_t hmacKey15;
+} AES256HMAC2_t, *AES256HMAC2_pt;
+
+/* AES256, (ECB, CBC, OFB, CTR, CFB), GCM - 56 bytes */
+typedef struct AES256GCM_s {
+ uint64_t cipherKey0;
+ uint64_t cipherKey1;
+ uint64_t cipherKey2;
+ uint64_t cipherKey3;
+ uint64_t GCMH0;
+ uint64_t GCMH1;
+ uint64_t GCMSCI;
+} AES256GCM_t, *AES256GCM_pt;
+
+/* AES256, (ECB, CBC, OFB, CTR, CFB), F9 - 56 bytes */
+typedef struct AES256F9_s {
+ uint64_t cipherKey0;
+ uint64_t cipherKey1;
+ uint64_t cipherKey2;
+ uint64_t cipherKey3;
+ uint64_t authKey0;
+ uint64_t authKey1;
+} AES256F9_t, *AES256F9_pt;
+
+/* AES256, (ECB, CBC, OFB, CTR, CFB), Non-HMAC (MD5, SHA-1, SHA-256) - 32 bytes */
+typedef struct AES256_s {
+ uint64_t cipherKey0;
+ uint64_t cipherKey1;
+ uint64_t cipherKey2;
+ uint64_t cipherKey3;
+} AES256_t, *AES256_pt;
+
+
+/* All AES192 possibilities */
+
+/* AES192, (ECB, CBC, OFB, CTR, CFB), HMAC (MD5, SHA-1, SHA-192) - 88 bytes */
+typedef struct AES192HMAC_s {
+ uint64_t cipherKey0;
+ uint64_t cipherKey1;
+ uint64_t cipherKey2;
+ uint64_t hmacKey0;
+ uint64_t hmacKey1;
+ uint64_t hmacKey2;
+ uint64_t hmacKey3;
+ uint64_t hmacKey4;
+ uint64_t hmacKey5;
+ uint64_t hmacKey6;
+ uint64_t hmacKey7;
+} AES192HMAC_t, *AES192HMAC_pt;
+
+/* AES192, (ECB, CBC, OFB, CTR, CFB), HMAC (SHA-384, SHA-512) - 152 bytes */
+typedef struct AES192HMAC2_s {
+ uint64_t cipherKey0;
+ uint64_t cipherKey1;
+ uint64_t cipherKey2;
+ uint64_t hmacKey0;
+ uint64_t hmacKey1;
+ uint64_t hmacKey2;
+ uint64_t hmacKey3;
+ uint64_t hmacKey4;
+ uint64_t hmacKey5;
+ uint64_t hmacKey6;
+ uint64_t hmacKey7;
+ uint64_t hmacKey8;
+ uint64_t hmacKey9;
+ uint64_t hmacKey10;
+ uint64_t hmacKey11;
+ uint64_t hmacKey12;
+ uint64_t hmacKey13;
+ uint64_t hmacKey14;
+ uint64_t hmacKey15;
+} AES192HMAC2_t, *AES192HMAC2_pt;
+
+/* AES192, (ECB, CBC, OFB, CTR, CFB), GCM - 48 bytes */
+typedef struct AES192GCM_s {
+ uint64_t cipherKey0;
+ uint64_t cipherKey1;
+ uint64_t cipherKey2;
+ uint64_t GCMH0;
+ uint64_t GCMH1;
+ uint64_t GCMSCI;
+} AES192GCM_t, *AES192GCM_pt;
+
+/* AES192, (ECB, CBC, OFB, CTR, CFB), F9 - 48 bytes */
+typedef struct AES192F9_s {
+ uint64_t cipherKey0;
+ uint64_t cipherKey1;
+ uint64_t cipherKey2;
+ uint64_t authKey0;
+ uint64_t authKey1;
+} AES192F9_t, *AES192F9_pt;
+
+/* AES192, (ECB, CBC, OFB, CTR, CFB), Non-HMAC (MD5, SHA-1, SHA-192) - 24 bytes */
+typedef struct AES192_s {
+ uint64_t cipherKey0;
+ uint64_t cipherKey1;
+ uint64_t cipherKey2;
+} AES192_t, *AES192_pt;
+
+
+/* All AES128 possibilities */
+
+/* AES128, (ECB, CBC, OFB, CTR, CFB), HMAC (MD5, SHA-1, SHA-128) - 80 bytes */
+typedef struct AES128HMAC_s {
+ uint64_t cipherKey0;
+ uint64_t cipherKey1;
+ uint64_t hmacKey0;
+ uint64_t hmacKey1;
+ uint64_t hmacKey2;
+ uint64_t hmacKey3;
+ uint64_t hmacKey4;
+ uint64_t hmacKey5;
+ uint64_t hmacKey6;
+ uint64_t hmacKey7;
+} AES128HMAC_t, *AES128HMAC_pt;
+
+/* AES128, (ECB, CBC, OFB, CTR, CFB), HMAC (SHA-384, SHA-612) - 144 bytes */
+typedef struct AES128HMAC2_s {
+ uint64_t cipherKey0;
+ uint64_t cipherKey1;
+ uint64_t hmacKey0;
+ uint64_t hmacKey1;
+ uint64_t hmacKey2;
+ uint64_t hmacKey3;
+ uint64_t hmacKey4;
+ uint64_t hmacKey5;
+ uint64_t hmacKey6;
+ uint64_t hmacKey7;
+ uint64_t hmacKey8;
+ uint64_t hmacKey9;
+ uint64_t hmacKey10;
+ uint64_t hmacKey11;
+ uint64_t hmacKey12;
+ uint64_t hmacKey13;
+ uint64_t hmacKey14;
+ uint64_t hmacKey15;
+} AES128HMAC2_t, *AES128HMAC2_pt;
+
+/* AES128, (ECB, CBC, OFB, CTR, CFB), GCM - 40 bytes */
+typedef struct AES128GCM_s {
+ uint64_t cipherKey0;
+ uint64_t cipherKey1;
+ uint64_t GCMH0;
+ uint64_t GCMH1;
+ uint64_t GCMSCI;
+} AES128GCM_t, *AES128GCM_pt;
+
+/* AES128, (ECB, CBC, OFB, CTR, CFB), F9 - 48 bytes */
+typedef struct AES128F9_s {
+ uint64_t cipherKey0;
+ uint64_t cipherKey1;
+ uint64_t authKey0;
+ uint64_t authKey1;
+} AES128F9_t, *AES128F9_pt;
+
+/* AES128, (ECB, CBC, OFB, CTR, CFB), Non-HMAC (MD5, SHA-1, SHA-128) - 16 bytes */
+typedef struct AES128_s {
+ uint64_t cipherKey0;
+ uint64_t cipherKey1;
+} AES128_t, *AES128_pt;
+
+/* AES128, (OFB F8), Non-HMAC (MD5, SHA-1, SHA-256) - 32 bytes */
+typedef struct AES128F8_s {
+ uint64_t cipherKey0;
+ uint64_t cipherKey1;
+ uint64_t cipherKeyMask0;
+ uint64_t cipherKeyMask1;
+} AES128F8_t, *AES128F8_pt;
+
+/* AES128, (OFB F8), HMAC (MD5, SHA-1, SHA-256) - 96 bytes */
+typedef struct AES128F8HMAC_s {
+ uint64_t cipherKey0;
+ uint64_t cipherKey1;
+ uint64_t cipherKeyMask0;
+ uint64_t cipherKeyMask1;
+ uint64_t hmacKey0;
+ uint64_t hmacKey1;
+ uint64_t hmacKey2;
+ uint64_t hmacKey3;
+ uint64_t hmacKey4;
+ uint64_t hmacKey5;
+ uint64_t hmacKey6;
+ uint64_t hmacKey7;
+} AES128F8HMAC_t, *AES128F8HMAC_pt;
+
+/* AES128, (OFB F8), HMAC (SHA-384, SHA-512) - 160 bytes */
+typedef struct AES128F8HMAC2_s {
+ uint64_t cipherKey0;
+ uint64_t cipherKey1;
+ uint64_t cipherKeyMask0;
+ uint64_t cipherKeyMask1;
+ uint64_t hmacKey0;
+ uint64_t hmacKey1;
+ uint64_t hmacKey2;
+ uint64_t hmacKey3;
+ uint64_t hmacKey4;
+ uint64_t hmacKey5;
+ uint64_t hmacKey6;
+ uint64_t hmacKey7;
+ uint64_t hmacKey8;
+ uint64_t hmacKey9;
+ uint64_t hmacKey10;
+ uint64_t hmacKey11;
+ uint64_t hmacKey12;
+ uint64_t hmacKey13;
+ uint64_t hmacKey14;
+ uint64_t hmacKey15;
+} AES128F8HMAC2_t, *AES128F8HMAC2_pt;
+
+/* AES192, (OFB F8), Non-HMAC (MD5, SHA-1, SHA-256) - 48 bytes */
+typedef struct AES192F8_s {
+ uint64_t cipherKey0;
+ uint64_t cipherKey1;
+ uint64_t cipherKey2;
+ uint64_t cipherKeyMask0;
+ uint64_t cipherKeyMask1;
+ uint64_t cipherKeyMask2;
+} AES192F8_t, *AES192F8_pt;
+
+/* AES192, (OFB F8), HMAC (MD5, SHA-1, SHA-256) - 112 bytes */
+typedef struct AES192F8HMAC_s {
+ uint64_t cipherKey0;
+ uint64_t cipherKey1;
+ uint64_t cipherKey2;
+ uint64_t cipherKeyMask0;
+ uint64_t cipherKeyMask1;
+ uint64_t cipherKeyMask2;
+ uint64_t hmacKey0;
+ uint64_t hmacKey1;
+ uint64_t hmacKey2;
+ uint64_t hmacKey3;
+ uint64_t hmacKey4;
+ uint64_t hmacKey5;
+ uint64_t hmacKey6;
+ uint64_t hmacKey7;
+} AES192F8HMAC_t, *AES192F8HMAC_pt;
+
+/* AES192, (OFB F8), HMAC (SHA-384, SHA-512) - 176 bytes */
+typedef struct AES192F8HMAC2_s {
+ uint64_t cipherKey0;
+ uint64_t cipherKey1;
+ uint64_t cipherKey2;
+ uint64_t cipherKeyMask0;
+ uint64_t cipherKeyMask1;
+ uint64_t cipherKeyMask2;
+ uint64_t hmacKey0;
+ uint64_t hmacKey1;
+ uint64_t hmacKey2;
+ uint64_t hmacKey3;
+ uint64_t hmacKey4;
+ uint64_t hmacKey5;
+ uint64_t hmacKey6;
+ uint64_t hmacKey7;
+ uint64_t hmacKey8;
+ uint64_t hmacKey9;
+ uint64_t hmacKey10;
+ uint64_t hmacKey11;
+ uint64_t hmacKey12;
+ uint64_t hmacKey13;
+ uint64_t hmacKey14;
+ uint64_t hmacKey15;
+} AES192F8HMAC2_t, *AES192F8HMAC2_pt;
+
+/* AES256, (OFB F8), Non-HMAC (MD5, SHA-1, SHA-256) - 64 bytes */
+typedef struct AES256F8_s {
+ uint64_t cipherKey0;
+ uint64_t cipherKey1;
+ uint64_t cipherKey2;
+ uint64_t cipherKey3;
+ uint64_t cipherKeyMask0;
+ uint64_t cipherKeyMask1;
+ uint64_t cipherKeyMask2;
+ uint64_t cipherKeyMask3;
+} AES256F8_t, *AES256F8_pt;
+
+/* AES256, (OFB F8), HMAC (MD5, SHA-1, SHA-256) - 128 bytes */
+typedef struct AES256F8HMAC_s {
+ uint64_t cipherKey0;
+ uint64_t cipherKey1;
+ uint64_t cipherKey2;
+ uint64_t cipherKey3;
+ uint64_t cipherKeyMask0;
+ uint64_t cipherKeyMask1;
+ uint64_t cipherKeyMask2;
+ uint64_t cipherKeyMask3;
+ uint64_t hmacKey0;
+ uint64_t hmacKey1;
+ uint64_t hmacKey2;
+ uint64_t hmacKey3;
+ uint64_t hmacKey4;
+ uint64_t hmacKey5;
+ uint64_t hmacKey6;
+ uint64_t hmacKey7;
+} AES256F8HMAC_t, *AES256F8HMAC_pt;
+
+/* AES256, (OFB F8), HMAC (SHA-384, SHA-512) - 192 bytes */
+typedef struct AES256F8HMAC2_s {
+ uint64_t cipherKey0;
+ uint64_t cipherKey1;
+ uint64_t cipherKey2;
+ uint64_t cipherKey3;
+ uint64_t cipherKeyMask0;
+ uint64_t cipherKeyMask1;
+ uint64_t cipherKeyMask2;
+ uint64_t cipherKeyMask3;
+ uint64_t hmacKey0;
+ uint64_t hmacKey1;
+ uint64_t hmacKey2;
+ uint64_t hmacKey3;
+ uint64_t hmacKey4;
+ uint64_t hmacKey5;
+ uint64_t hmacKey6;
+ uint64_t hmacKey7;
+ uint64_t hmacKey8;
+ uint64_t hmacKey9;
+ uint64_t hmacKey10;
+ uint64_t hmacKey11;
+ uint64_t hmacKey12;
+ uint64_t hmacKey13;
+ uint64_t hmacKey14;
+ uint64_t hmacKey15;
+} AES256F8HMAC2_t, *AES256F8HMAC2_pt;
+
+/* AES256, (F8), GCM - 40 bytes */
+typedef struct AES128F8GCM_s {
+ uint64_t cipherKey0;
+ uint64_t cipherKey2;
+ uint64_t GCMH0;
+ uint64_t GCMH1;
+ uint64_t GCMSCI;
+} AES128F8GCM_t, *AES128F8GCM_pt;
+
+/* AES256, (F8), GCM - 48 bytes */
+typedef struct AES192F8GCM_s {
+ uint64_t cipherKey0;
+ uint64_t cipherKey1;
+ uint64_t cipherKey2;
+ uint64_t GCMH0;
+ uint64_t GCMH1;
+ uint64_t GCMSCI;
+} AES192F8GCM_t, *AES192F8GCM_pt;
+
+/* AES256, (F8), GCM - 56 bytes */
+typedef struct AES256F8GCM_s {
+ uint64_t cipherKey0;
+ uint64_t cipherKey1;
+ uint64_t cipherKey2;
+ uint64_t cipherKey3;
+ uint64_t GCMH0;
+ uint64_t GCMH1;
+ uint64_t GCMSCI;
+} AES256F8GCM_t, *AES256F8GCM_pt;
+
+/* AES256, (F8), F9 - 40 bytes */
+typedef struct AES128F8F9_s {
+ uint64_t cipherKey0;
+ uint64_t cipherKey2;
+ uint64_t authKey0;
+ uint64_t authKey1;
+} AES128F8F9_t, *AES128F8F9_pt;
+
+/* AES256, (F8), F9 - 48 bytes */
+typedef struct AES192F8F9_s {
+ uint64_t cipherKey0;
+ uint64_t cipherKey1;
+ uint64_t cipherKey2;
+ uint64_t authKey0;
+ uint64_t authKey1;
+} AES192F8F9_t, *AES192F8F9_pt;
+
+/* AES256F8, (F8), F9 - 56 bytes */
+typedef struct AES256F8F9_s {
+ uint64_t cipherKey0;
+ uint64_t cipherKey1;
+ uint64_t cipherKey2;
+ uint64_t cipherKey3;
+ uint64_t authKey0;
+ uint64_t authKey1;
+} AES256F8F9_t, *AES256F8F9_pt;
+
+/* All DES possibilities */
+
+/* DES, (ECB, CBC), HMAC (MD5, SHA-1, SHA-128) - 72 bytes */
+typedef struct DESHMAC_s {
+ uint64_t cipherKey0;
+ uint64_t hmacKey0;
+ uint64_t hmacKey1;
+ uint64_t hmacKey2;
+ uint64_t hmacKey3;
+ uint64_t hmacKey4;
+ uint64_t hmacKey5;
+ uint64_t hmacKey6;
+ uint64_t hmacKey7;
+} DESHMAC_t, *DESHMAC_pt;
+
+/* DES, (ECB, CBC), HMAC (SHA-384, SHA-512) - 136 bytes */
+typedef struct DESHMAC2_s {
+ uint64_t cipherKey0;
+ uint64_t hmacKey0;
+ uint64_t hmacKey1;
+ uint64_t hmacKey2;
+ uint64_t hmacKey3;
+ uint64_t hmacKey4;
+ uint64_t hmacKey5;
+ uint64_t hmacKey6;
+ uint64_t hmacKey7;
+ uint64_t hmacKey8;
+ uint64_t hmacKey9;
+ uint64_t hmacKey10;
+ uint64_t hmacKey11;
+ uint64_t hmacKey12;
+ uint64_t hmacKey13;
+ uint64_t hmacKey14;
+ uint64_t hmacKey15;
+} DESHMAC2_t, *DESHMAC2_pt;
+
+/* DES, (ECB, CBC), GCM - 32 bytes */
+typedef struct DESGCM_s {
+ uint64_t cipherKey0;
+ uint64_t GCMH0;
+ uint64_t GCMH1;
+ uint64_t GCMSCI;
+} DESGCM_t, *DESGCM_pt;
+
+/* DES, (ECB, CBC), F9 - 32 bytes */
+typedef struct DESF9_s {
+ uint64_t cipherKey0;
+ uint64_t authKey0;
+ uint64_t authKey1;
+} DESF9_t, *DESF9_pt;
+
+/* DES, (ECB, CBC), Non-HMAC (MD5, SHA-1, SHA-128) - 9 bytes */
+typedef struct DES_s {
+ uint64_t cipherKey0;
+} DES_t, *DES_pt;
+
+
+/* All 3DES possibilities */
+
+/* 3DES, (ECB, CBC), HMAC (MD5, SHA-1, SHA-128) - 88 bytes */
+typedef struct DES3HMAC_s {
+ uint64_t cipherKey0;
+ uint64_t cipherKey1;
+ uint64_t cipherKey2;
+ uint64_t hmacKey0;
+ uint64_t hmacKey1;
+ uint64_t hmacKey2;
+ uint64_t hmacKey3;
+ uint64_t hmacKey4;
+ uint64_t hmacKey5;
+ uint64_t hmacKey6;
+ uint64_t hmacKey7;
+} DES3HMAC_t, *DES3HMAC_pt;
+
+/* 3DES, (ECB, CBC), HMAC (SHA-384, SHA-512) - 152 bytes */
+typedef struct DES3HMAC2_s {
+ uint64_t cipherKey0;
+ uint64_t cipherKey1;
+ uint64_t cipherKey2;
+ uint64_t hmacKey0;
+ uint64_t hmacKey1;
+ uint64_t hmacKey2;
+ uint64_t hmacKey3;
+ uint64_t hmacKey4;
+ uint64_t hmacKey5;
+ uint64_t hmacKey6;
+ uint64_t hmacKey7;
+ uint64_t hmacKey8;
+ uint64_t hmacKey9;
+ uint64_t hmacKey10;
+ uint64_t hmacKey11;
+ uint64_t hmacKey12;
+ uint64_t hmacKey13;
+ uint64_t hmacKey14;
+ uint64_t hmacKey15;
+} DES3HMAC2_t, *DES3HMAC2_pt;
+
+/* 3DES, (ECB, CBC), GCM - 48 bytes */
+typedef struct DES3GCM_s {
+ uint64_t cipherKey0;
+ uint64_t cipherKey1;
+ uint64_t cipherKey2;
+ uint64_t GCMH0;
+ uint64_t GCMH1;
+ uint64_t GCMSCI;
+} DES3GCM_t, *DES3GCM_pt;
+
+/* 3DES, (ECB, CBC), GCM - 48 bytes */
+typedef struct DES3F9_s {
+ uint64_t cipherKey0;
+ uint64_t cipherKey1;
+ uint64_t cipherKey2;
+ uint64_t authKey0;
+ uint64_t authKey1;
+} DES3F9_t, *DES3F9_pt;
+
+/* 3DES, (ECB, CBC), Non-HMAC (MD5, SHA-1, SHA-128) - 24 bytes */
+typedef struct DES3_s {
+ uint64_t cipherKey0;
+ uint64_t cipherKey1;
+ uint64_t cipherKey2;
+} DES3_t, *DES3_pt;
+
+
+/* HMAC only - no cipher */
+
+/* HMAC (MD5, SHA-1, SHA-128) - 64 bytes */
+typedef struct HMAC_s {
+ uint64_t hmacKey0;
+ uint64_t hmacKey1;
+ uint64_t hmacKey2;
+ uint64_t hmacKey3;
+ uint64_t hmacKey4;
+ uint64_t hmacKey5;
+ uint64_t hmacKey6;
+ uint64_t hmacKey7;
+} HMAC_t, *HMAC_pt;
+
+/* HMAC (SHA-384, SHA-512) - 128 bytes */
+typedef struct HMAC2_s {
+ uint64_t hmacKey0;
+ uint64_t hmacKey1;
+ uint64_t hmacKey2;
+ uint64_t hmacKey3;
+ uint64_t hmacKey4;
+ uint64_t hmacKey5;
+ uint64_t hmacKey6;
+ uint64_t hmacKey7;
+ uint64_t hmacKey8;
+ uint64_t hmacKey9;
+ uint64_t hmacKey10;
+ uint64_t hmacKey11;
+ uint64_t hmacKey12;
+ uint64_t hmacKey13;
+ uint64_t hmacKey14;
+ uint64_t hmacKey15;
+} HMAC2_t, *HMAC2_pt;
+
+/* GCM - 24 bytes */
+typedef struct GCM_s {
+ uint64_t GCMH0;
+ uint64_t GCMH1;
+ uint64_t GCMSCI;
+} GCM_t, *GCM_pt;
+
+/* F9 - 24 bytes */
+typedef struct F9_s {
+ uint64_t authKey0;
+ uint64_t authKey1;
+} F9_t, *F9_pt;
+
+/* All ARC4 possibilities */
+/* ARC4, HMAC (MD5, SHA-1, SHA-256) - 96 bytes */
+typedef struct ARC4HMAC_s {
+ uint64_t cipherKey0;
+ uint64_t cipherKey1;
+ uint64_t cipherKey2;
+ uint64_t cipherKey3;
+ uint64_t hmacKey0;
+ uint64_t hmacKey1;
+ uint64_t hmacKey2;
+ uint64_t hmacKey3;
+ uint64_t hmacKey4;
+ uint64_t hmacKey5;
+ uint64_t hmacKey6;
+ uint64_t hmacKey7;
+} ARC4HMAC_t, *ARC4HMAC_pt;
+
+/* ARC4, HMAC (SHA-384, SHA-512) - 160 bytes */
+typedef struct ARC4HMAC2_s {
+ uint64_t cipherKey0;
+ uint64_t cipherKey1;
+ uint64_t cipherKey2;
+ uint64_t cipherKey3;
+ uint64_t hmacKey0;
+ uint64_t hmacKey1;
+ uint64_t hmacKey2;
+ uint64_t hmacKey3;
+ uint64_t hmacKey4;
+ uint64_t hmacKey5;
+ uint64_t hmacKey6;
+ uint64_t hmacKey7;
+ uint64_t hmacKey8;
+ uint64_t hmacKey9;
+ uint64_t hmacKey10;
+ uint64_t hmacKey11;
+ uint64_t hmacKey12;
+ uint64_t hmacKey13;
+ uint64_t hmacKey14;
+ uint64_t hmacKey15;
+} ARC4HMAC2_t, *ARC4HMAC2_pt;
+
+/* ARC4, GCM - 56 bytes */
+typedef struct ARC4GCM_s {
+ uint64_t cipherKey0;
+ uint64_t cipherKey1;
+ uint64_t cipherKey2;
+ uint64_t cipherKey3;
+ uint64_t GCMH0;
+ uint64_t GCMH1;
+ uint64_t GCMSCI;
+} ARC4GCM_t, *ARC4GCM_pt;
+
+/* ARC4, F9 - 56 bytes */
+typedef struct ARC4F9_s {
+ uint64_t cipherKey0;
+ uint64_t cipherKey1;
+ uint64_t cipherKey2;
+ uint64_t cipherKey3;
+ uint64_t authKey0;
+ uint64_t authKey1;
+} ARC4F9_t, *ARC4F9_pt;
+
+/* ARC4, HMAC (MD5, SHA-1, SHA-256) - 408 bytes (not including 8 bytes from instruction) */
+typedef struct ARC4StateHMAC_s {
+ uint64_t cipherKey0;
+ uint64_t cipherKey1;
+ uint64_t cipherKey2;
+ uint64_t cipherKey3;
+ uint64_t hmacKey0;
+ uint64_t hmacKey1;
+ uint64_t hmacKey2;
+ uint64_t hmacKey3;
+ uint64_t hmacKey4;
+ uint64_t hmacKey5;
+ uint64_t hmacKey6;
+ uint64_t hmacKey7;
+ uint64_t PAD0;
+ uint64_t PAD1;
+ uint64_t PAD2;
+ uint64_t Arc4SboxData0;
+ uint64_t Arc4SboxData1;
+ uint64_t Arc4SboxData2;
+ uint64_t Arc4SboxData3;
+ uint64_t Arc4SboxData4;
+ uint64_t Arc4SboxData5;
+ uint64_t Arc4SboxData6;
+ uint64_t Arc4SboxData7;
+ uint64_t Arc4SboxData8;
+ uint64_t Arc4SboxData9;
+ uint64_t Arc4SboxData10;
+ uint64_t Arc4SboxData11;
+ uint64_t Arc4SboxData12;
+ uint64_t Arc4SboxData13;
+ uint64_t Arc4SboxData14;
+ uint64_t Arc4SboxData15;
+ uint64_t Arc4SboxData16;
+ uint64_t Arc4SboxData17;
+ uint64_t Arc4SboxData18;
+ uint64_t Arc4SboxData19;
+ uint64_t Arc4SboxData20;
+ uint64_t Arc4SboxData21;
+ uint64_t Arc4SboxData22;
+ uint64_t Arc4SboxData23;
+ uint64_t Arc4SboxData24;
+ uint64_t Arc4SboxData25;
+ uint64_t Arc4SboxData26;
+ uint64_t Arc4SboxData27;
+ uint64_t Arc4SboxData28;
+ uint64_t Arc4SboxData29;
+ uint64_t Arc4SboxData30;
+ uint64_t Arc4SboxData31;
+ uint64_t Arc4IJData;
+ uint64_t PAD3;
+ uint64_t PAD4;
+ uint64_t PAD5;
+} ARC4StateHMAC_t, *ARC4StateHMAC_pt;
+
+/* ARC4, HMAC (SHA-384, SHA-512) - 480 bytes (not including 8 bytes from instruction) */
+typedef struct ARC4StateHMAC2_s {
+ uint64_t cipherKey0;
+ uint64_t cipherKey1;
+ uint64_t cipherKey2;
+ uint64_t cipherKey3;
+ uint64_t hmacKey0;
+ uint64_t hmacKey1;
+ uint64_t hmacKey2;
+ uint64_t hmacKey3;
+ uint64_t hmacKey4;
+ uint64_t hmacKey5;
+ uint64_t hmacKey6;
+ uint64_t hmacKey7;
+ uint64_t hmacKey8;
+ uint64_t hmacKey9;
+ uint64_t hmacKey10;
+ uint64_t hmacKey11;
+ uint64_t hmacKey12;
+ uint64_t hmacKey13;
+ uint64_t hmacKey14;
+ uint64_t hmacKey15;
+ uint64_t PAD0;
+ uint64_t PAD1;
+ uint64_t PAD2;
+ uint64_t Arc4SboxData0;
+ uint64_t Arc4SboxData1;
+ uint64_t Arc4SboxData2;
+ uint64_t Arc4SboxData3;
+ uint64_t Arc4SboxData4;
+ uint64_t Arc4SboxData5;
+ uint64_t Arc4SboxData6;
+ uint64_t Arc4SboxData7;
+ uint64_t Arc4SboxData8;
+ uint64_t Arc4SboxData9;
+ uint64_t Arc4SboxData10;
+ uint64_t Arc4SboxData11;
+ uint64_t Arc4SboxData12;
+ uint64_t Arc4SboxData13;
+ uint64_t Arc4SboxData14;
+ uint64_t Arc4SboxData15;
+ uint64_t Arc4SboxData16;
+ uint64_t Arc4SboxData17;
+ uint64_t Arc4SboxData18;
+ uint64_t Arc4SboxData19;
+ uint64_t Arc4SboxData20;
+ uint64_t Arc4SboxData21;
+ uint64_t Arc4SboxData22;
+ uint64_t Arc4SboxData23;
+ uint64_t Arc4SboxData24;
+ uint64_t Arc4SboxData25;
+ uint64_t Arc4SboxData26;
+ uint64_t Arc4SboxData27;
+ uint64_t Arc4SboxData28;
+ uint64_t Arc4SboxData29;
+ uint64_t Arc4SboxData30;
+ uint64_t Arc4SboxData31;
+ uint64_t Arc4IJData;
+ uint64_t PAD3;
+ uint64_t PAD4;
+ uint64_t PAD5;
+} ARC4StateHMAC2_t, *ARC4StateHMAC2_pt;
+
+/* ARC4, GCM - 408 bytes (not including 8 bytes from instruction) */
+typedef struct ARC4StateGCM_s {
+ uint64_t cipherKey0;
+ uint64_t cipherKey1;
+ uint64_t cipherKey2;
+ uint64_t cipherKey3;
+ uint64_t GCMH0;
+ uint64_t GCMH1;
+ uint64_t GCMSCI;
+ uint64_t PAD0;
+ uint64_t PAD1;
+ uint64_t PAD2;
+ uint64_t PAD3;
+ uint64_t PAD4;
+ uint64_t PAD5;
+ uint64_t PAD6;
+ uint64_t PAD7;
+ uint64_t Arc4SboxData0;
+ uint64_t Arc4SboxData1;
+ uint64_t Arc4SboxData2;
+ uint64_t Arc4SboxData3;
+ uint64_t Arc4SboxData4;
+ uint64_t Arc4SboxData5;
+ uint64_t Arc4SboxData6;
+ uint64_t Arc4SboxData7;
+ uint64_t Arc4SboxData8;
+ uint64_t Arc4SboxData9;
+ uint64_t Arc4SboxData10;
+ uint64_t Arc4SboxData11;
+ uint64_t Arc4SboxData12;
+ uint64_t Arc4SboxData13;
+ uint64_t Arc4SboxData14;
+ uint64_t Arc4SboxData15;
+ uint64_t Arc4SboxData16;
+ uint64_t Arc4SboxData17;
+ uint64_t Arc4SboxData18;
+ uint64_t Arc4SboxData19;
+ uint64_t Arc4SboxData20;
+ uint64_t Arc4SboxData21;
+ uint64_t Arc4SboxData22;
+ uint64_t Arc4SboxData23;
+ uint64_t Arc4SboxData24;
+ uint64_t Arc4SboxData25;
+ uint64_t Arc4SboxData26;
+ uint64_t Arc4SboxData27;
+ uint64_t Arc4SboxData28;
+ uint64_t Arc4SboxData29;
+ uint64_t Arc4SboxData30;
+ uint64_t Arc4SboxData31;
+ uint64_t Arc4IJData;
+ uint64_t PAD8;
+ uint64_t PAD9;
+ uint64_t PAD10;
+} ARC4StateGCM_t, *ARC4StateGCM_pt;
+
+/* ARC4, F9 - 408 bytes (not including 8 bytes from instruction) */
+typedef struct ARC4StateF9_s {
+ uint64_t cipherKey0;
+ uint64_t cipherKey1;
+ uint64_t cipherKey2;
+ uint64_t cipherKey3;
+ uint64_t authKey0;
+ uint64_t authKey1;
+ uint64_t PAD0;
+ uint64_t PAD1;
+ uint64_t PAD2;
+ uint64_t PAD3;
+ uint64_t PAD4;
+ uint64_t PAD5;
+ uint64_t PAD6;
+ uint64_t PAD7;
+ uint64_t PAD8;
+ uint64_t Arc4SboxData0;
+ uint64_t Arc4SboxData1;
+ uint64_t Arc4SboxData2;
+ uint64_t Arc4SboxData3;
+ uint64_t Arc4SboxData4;
+ uint64_t Arc4SboxData5;
+ uint64_t Arc4SboxData6;
+ uint64_t Arc4SboxData7;
+ uint64_t Arc4SboxData8;
+ uint64_t Arc4SboxData9;
+ uint64_t Arc4SboxData10;
+ uint64_t Arc4SboxData11;
+ uint64_t Arc4SboxData12;
+ uint64_t Arc4SboxData13;
+ uint64_t Arc4SboxData14;
+ uint64_t Arc4SboxData15;
+ uint64_t Arc4SboxData16;
+ uint64_t Arc4SboxData17;
+ uint64_t Arc4SboxData18;
+ uint64_t Arc4SboxData19;
+ uint64_t Arc4SboxData20;
+ uint64_t Arc4SboxData21;
+ uint64_t Arc4SboxData22;
+ uint64_t Arc4SboxData23;
+ uint64_t Arc4SboxData24;
+ uint64_t Arc4SboxData25;
+ uint64_t Arc4SboxData26;
+ uint64_t Arc4SboxData27;
+ uint64_t Arc4SboxData28;
+ uint64_t Arc4SboxData29;
+ uint64_t Arc4SboxData30;
+ uint64_t Arc4SboxData31;
+ uint64_t Arc4IJData;
+ uint64_t PAD9;
+ uint64_t PAD10;
+ uint64_t PAD11;
+} ARC4StateF9_t, *ARC4StateF9_pt;
+
+/* ARC4, Non-HMAC (MD5, SHA-1, SHA-256) - 32 bytes */
+typedef struct ARC4_s {
+ uint64_t cipherKey0;
+ uint64_t cipherKey1;
+ uint64_t cipherKey2;
+ uint64_t cipherKey3;
+} ARC4_t, *ARC4_pt;
+
+/* ARC4, Non-HMAC (MD5, SHA-1, SHA-256) - 344 bytes (not including 8 bytes from instruction) */
+typedef struct ARC4State_s {
+ uint64_t cipherKey0;
+ uint64_t cipherKey1;
+ uint64_t cipherKey2;
+ uint64_t cipherKey3;
+ uint64_t PAD0;
+ uint64_t PAD1;
+ uint64_t PAD2;
+ uint64_t Arc4SboxData0;
+ uint64_t Arc4SboxData1;
+ uint64_t Arc4SboxData2;
+ uint64_t Arc4SboxData3;
+ uint64_t Arc4SboxData4;
+ uint64_t Arc4SboxData5;
+ uint64_t Arc4SboxData6;
+ uint64_t Arc4SboxData7;
+ uint64_t Arc4SboxData8;
+ uint64_t Arc4SboxData9;
+ uint64_t Arc4SboxData10;
+ uint64_t Arc4SboxData11;
+ uint64_t Arc4SboxData12;
+ uint64_t Arc4SboxData13;
+ uint64_t Arc4SboxData14;
+ uint64_t Arc4SboxData15;
+ uint64_t Arc4SboxData16;
+ uint64_t Arc4SboxData17;
+ uint64_t Arc4SboxData18;
+ uint64_t Arc4SboxData19;
+ uint64_t Arc4SboxData20;
+ uint64_t Arc4SboxData21;
+ uint64_t Arc4SboxData22;
+ uint64_t Arc4SboxData23;
+ uint64_t Arc4SboxData24;
+ uint64_t Arc4SboxData25;
+ uint64_t Arc4SboxData26;
+ uint64_t Arc4SboxData27;
+ uint64_t Arc4SboxData28;
+ uint64_t Arc4SboxData29;
+ uint64_t Arc4SboxData30;
+ uint64_t Arc4SboxData31;
+ uint64_t Arc4IJData;
+ uint64_t PAD3;
+ uint64_t PAD4;
+ uint64_t PAD5;
+} ARC4State_t, *ARC4State_pt;
+
+/* Kasumi f8 - 32 bytes */
+typedef struct KASUMIF8_s {
+ uint64_t cipherKey0;
+ uint64_t cipherKey1;
+} KASUMIF8_t, *KASUMIF8_pt;
+
+/* Kasumi f8 + HMAC (MD5, SHA-1, SHA-256) - 80 bytes */
+typedef struct KASUMIF8HMAC_s {
+ uint64_t cipherKey0;
+ uint64_t cipherKey1;
+ uint64_t hmacKey0;
+ uint64_t hmacKey1;
+ uint64_t hmacKey2;
+ uint64_t hmacKey3;
+ uint64_t hmacKey4;
+ uint64_t hmacKey5;
+ uint64_t hmacKey6;
+ uint64_t hmacKey7;
+} KASUMIF8HMAC_t, *KASUMIF8HMAC_pt;
+
+/* Kasumi f8 + HMAC (SHA-384, SHA-512) - 144 bytes */
+typedef struct KASUMIF8HMAC2_s {
+ uint64_t cipherKey0;
+ uint64_t cipherKey1;
+ uint64_t hmacKey0;
+ uint64_t hmacKey1;
+ uint64_t hmacKey2;
+ uint64_t hmacKey3;
+ uint64_t hmacKey4;
+ uint64_t hmacKey5;
+ uint64_t hmacKey6;
+ uint64_t hmacKey7;
+ uint64_t hmacKey8;
+ uint64_t hmacKey9;
+ uint64_t hmacKey10;
+ uint64_t hmacKey11;
+ uint64_t hmacKey12;
+ uint64_t hmacKey13;
+ uint64_t hmacKey14;
+ uint64_t hmacKey15;
+} KASUMIF8HMAC2_t, *KASUMIF8HMAC2_pt;
+
+/* Kasumi f8 + GCM - 144 bytes */
+typedef struct KASUMIF8GCM_s {
+ uint64_t cipherKey0;
+ uint64_t cipherKey1;
+ uint64_t GCMH0;
+ uint64_t GCMH1;
+ uint64_t GCMSCI;
+} KASUMIF8GCM_t, *KASUMIF8GCM_pt;
+
+/* Kasumi f8 + f9 - 32 bytes */
+typedef struct KASUMIF8F9_s {
+ uint64_t cipherKey0;
+ uint64_t cipherKey1;
+ uint64_t authKey0;
+ uint64_t authKey1;
+} KASUMIF8F9_t, *KASUMIF8F9_pt;
+
+typedef union CipherHashInfo_u {
+ AES256HMAC_t infoAES256HMAC;
+ AES256_t infoAES256;
+ AES192HMAC_t infoAES192HMAC;
+ AES192_t infoAES192;
+ AES128HMAC_t infoAES128HMAC;
+ AES128_t infoAES128;
+ DESHMAC_t infoDESHMAC;
+ DES_t infoDES;
+ DES3HMAC_t info3DESHMAC;
+ DES3_t info3DES;
+ HMAC_t infoHMAC;
+ /* ARC4 */
+ ARC4HMAC_t infoARC4HMAC;
+ ARC4StateHMAC_t infoARC4StateHMAC;
+ ARC4_t infoARC4;
+ ARC4State_t infoARC4State;
+ /* AES mode F8 */
+ AES256F8HMAC_t infoAES256F8HMAC;
+ AES256F8_t infoAES256F8;
+ AES192F8HMAC_t infoAES192F8HMAC;
+ AES192F8_t infoAES192F8;
+ AES128F8HMAC_t infoAES128F8HMAC;
+ AES128F8_t infoAES128F8;
+ /* KASUMI F8 */
+ KASUMIF8HMAC_t infoKASUMIF8HMAC;
+ KASUMIF8_t infoKASUMIF8;
+ /* GCM */
+ GCM_t infoGCM;
+ AES256F8GCM_t infoAES256F8GCM;
+ AES192F8GCM_t infoAES192F8GCM;
+ AES128F8GCM_t infoAES128F8GCM;
+ AES256GCM_t infoAES256GCM;
+ AES192GCM_t infoAES192GCM;
+ AES128GCM_t infoAES128GCM;
+ DESGCM_t infoDESGCM;
+ DES3GCM_t info3DESGCM;
+ ARC4GCM_t infoARC4GCM;
+ ARC4StateGCM_t infoARC4StateGCM;
+ KASUMIF8GCM_t infoKASUMIF8GCM;
+ /* HMAC2 */
+ HMAC2_t infoHMAC2;
+ AES256F8HMAC2_t infoAES256F8HMAC2;
+ AES192F8HMAC2_t infoAES192F8HMAC2;
+ AES128F8HMAC2_t infoAES128F8HMAC2;
+ AES256HMAC2_t infoAES256HMAC2;
+ AES192HMAC2_t infoAES192HMAC2;
+ AES128HMAC2_t infoAES128HMAC2;
+ DESHMAC2_t infoDESHMAC2;
+ DES3HMAC2_t info3DESHMAC2;
+ ARC4HMAC2_t infoARC4HMAC2;
+ ARC4StateHMAC2_t infoARC4StateHMAC2;
+ KASUMIF8HMAC2_t infoKASUMIF8HMAC2;
+ /* F9 */
+ F9_t infoF9;
+ AES256F8F9_t infoAES256F8F9;
+ AES192F8F9_t infoAES192F8F9;
+ AES128F8F9_t infoAES128F8F9;
+ AES256F9_t infoAES256F9;
+ AES192F9_t infoAES192F9;
+ AES128F9_t infoAES128F9;
+ DESF9_t infoDESF9;
+ DES3F9_t info3DESF9;
+ ARC4F9_t infoARC4F9;
+ ARC4StateF9_t infoARC4StateF9;
+ KASUMIF8F9_t infoKASUMIF8F9;
+} CipherHashInfo_t, *CipherHashInfo_pt;
+
+
+/*
+ *
+ * ControlDescriptor_s datastructure
+ *
+ */
+
+typedef struct ControlDescriptor_s {
+ uint64_t instruction;
+ CipherHashInfo_t cipherHashInfo;
+} ControlDescriptor_t, *ControlDescriptor_pt;
+
+
+
+
+/* **********************************************************************
+ * PacketDescriptor_t
+ * **********************************************************************
+ */
+
+/* /--------------------------------------------\
+ * | |
+ * | New PacketDescriptor_s datastructure |
+ * | |
+ * \--------------------------------------------/
+ *
+ *
+ *
+ * PacketDescriptor_t.srcLengthIVOffUseIVNext
+ * ------------------------------------------
+ *
+ * 63 62 61 59 58 57 56 54 53 43
+ * ------------------------------------------------------------------------------------------------
+ * || Load HMAC key || Pad Hash || Hash Byte Count || Next || Use IV || IV Offset || Packet length || ... CONT ...
+ * ------------------------------------------------------------------------------------------------
+ * 1 1 3 1 1 3 11
+ *
+ *
+ * 42 41 40 39 5 4 3 2
+ * 0
+ * ----------------------------------------------------------------------------------------------------
+ * || NLHMAC || Break || Wait || Segment src address || SRTCP || Reserved || Global src data offset ||
+ * ----------------------------------------------------------------------------------------------------
+ * 1 1 1 35 1 1 3
+ *
+ *
+ *
+ * Load HMAC key = 1'b0 Preserve old HMAC key stored in Auth engine (moot if HASH.HMAC == 0)
+ * 1'b1 Load HMAC key from ID registers at beginning of op
+ * If GCM is selected as authenticator, setting this bit
+ * will cause the H value from ID to be loaded to the engine
+ * If Kasumi F9 is selected as authenticator, setting this bit
+ * will cause the IK value from ID to be loaded to the engine.
+ * Pad Hash = 1'b0 HASH will assume the data was padded to be a multiple
+ * of 512 bits in length and that the last 64 bit word
+ * expresses the total datalength in bits seen by HASH engine
+ * 1'b1 The data was not padded to be a multiple of 512 bits in length;
+ * The Hash engine will do its own padding to generate the correct digest.
+ * Ignored by GCM (always does its own padding)
+ * Hash Byte Count Number of BYTES on last 64-bit data word to use in digest calculation RELEVANT ONLY IF Pad Hash IS SET
+ * 3'b000 Use all 8
+ * 3'b001 Use first (MS) byte only (0-out rest), i.e., 0xddXXXXXXXXXXXXXX
+ * 3'b010 Use first 2 bytes only (0-out rest), i.e., 0xddddXXXXXXXXXXXX ... etc
+ * Next = 1'b0 Finish (return msg descriptor) at end of operation
+ * 1'b1 Grab the next PacketDescriptor (i.e. next cache-line) when the current is complete.
+ * This allows for fragmentation/defragmentation and processing of large (>16kB) packets.
+ * The sequence of adjacent PacketDescriptor acts as a contiguous linked list of
+ * pointers to the actual packets with Next==0 on the last PacketDescriptor to end processing.
+ * Use IV = 1'b0 On first frag: Use old IV
+ * On subsequent frags: Do not write out to DST the (dword) offset data
+ * 1'b1 On first frag: Use data @ Segment_address + IV_Offset as IV
+ * On subsequent frags: Do write out to DST the (dword) offset data
+ * IV Offset = On first frag: Offset IN NB OF 8 BYTE WORDS (dwords) from beginning of packet
+ * (i.e. (Potentially byte-shifted) Segment address) to cipher IV
+ * On subsequent frags: Offset to beginning of data to process; data to offset won't
+ * be given to engines and will be written out to dst in the clear.
+ * ON SUBSEQUENT FRAGS, IV_Offset MAY NOT EXCEED 3; LARGER VALUES WILL CAUSE AN ERROR
+ * SEE ERROR CONDITIONS BELOW
+ * Packet length = Nb double words to stream in (Including Segment address->CP/IV/Auth/CkSum offsets)
+ * This is the total amount of data (x8 in bytes) read (+1 dword if "Global src data offset" != 0)
+ * This is the total amount of data (x8 in bytes) written (+1 dword if "Global dst data offset" != 0, if Dst dword offset == 0)
+ * If Packet length == 11'h7ff and (Global src data offset != 0 or Global dst data offset != 0)
+ * the operation is aborted (no mem writes occur)
+ * and the "Insufficient Data To Cipher" error flag is raised
+ * NLHMAC = No last to hmac. Setting this to 1 will prevent the transmission of the last DWORD
+ * to the authenticator, i.e., the DWORD before last will be designated as last for the purposes of authentication.
+ * Break = Break a wait (see below) state - causes the operation to be flushed and free descriptor to be returned.
+ * Activated if DFetch blocked by Wait and Wait still active.
+ * AS OF 02/10/2005 THIS FEATURE IS EXPERIMENTAL
+ * Wait = Setting that bit causes the operation to block in DFetch stage.
+ * DFetch will keep polling the memory location until the bit is reset at which time
+ * the pipe resumes normal operation. This feature is convenient for software dealing with fragmented packets.
+ * AS OF 02/10/2005 THIS FEATURE IS EXPERIMENTAL
+ * Segment src address = 35 MSB of pointer to src data (i.e., cache-line aligned)
+ * SRTCP = Bypass the cipher for the last 4 bytes of data, i.e. the last 4 bytes will be sent to memory
+ * and the authenticator in the clear. Applicable to last packet descriptor andlast frag only.
+ * This accommodates a requirement of SRTCP.
+ * Global src data offset = Nb BYTES to right-shift data by before presenting it to engines
+ * (0-7); allows realignment of byte-aligned, non-double-word aligned data
+ *
+ * PacketDescriptor_t.dstDataSettings
+ * ----------------------------------
+ *
+ *
+ * 63 62 60 59 58 56 55 54 53 52 41 40
+ * ------------------------------------------------------------------------------------------------------------
+ * || CipherPrefix | Arc4ByteCount | E/D | Cipher_Offset || Hash_Offset | Hash_Src || CkSum_Offset | CkSum_Src || ... CONT ...
+ * ------------------------------------------------------------------------------------------------------------
+ * 1 3 1 3 2 1 12 1
+ * <-----------------------CIPHER-----------------------><---------HASH-----------><-------CHECKSUM----------->
+ *
+ *
+ * CipherPrefix = 128'b0 will be sent to the selected cipher
+ * KEEP VALUE ON ALL FRAGS after the IV is loaded, before the actual data goes in.
+ * The result of that encryption (aka E(K, 0))will be stored
+ * locally and XOR-ed with the auth digest to create the final
+ * digest at the end of the auth OP:
+ * This is covered by the GCM spec
+ * AesPrefix = 1'b1 -> Force E=Cipher(K,0) before start of data encr.
+ * -> Digest ^= E
+ * AesPrefix = 1'b0 -> Regular digest
+ * This flag is ignored if no cipher is chosen (Bypass condition)
+ * X0 Arc4ByteCount = Number of BYTES on last 64-bit data word to encrypt
+ * 3'b000 Encrypt all 8
+ * 3'b001 Encrypt first (MS) byte only i.e., 0xddXXXXXXXXXXXXXX
+ * 3'b010 Encrypt first 2 bytes only i.e., 0xddddXXXXXXXXXXXX ... etc
+ * In reality, all are encrypted, however, the SBOX
+ * is not written past the last byte to encrypt
+ * E/D = 1'b0 Decrypt
+ * 1'b1 Encrypt
+ * Overloaded to also mean IV byte offset for first frag
+ * Cipher_Offset = Nb of words between the first data segment
+ * and word on which to start cipher operation
+ * (64 BIT WORDS !!!)
+ * Hash_Offset = Nb of words between the first data segment
+ * and word on which to start hashing
+ * (64 bit words)
+ * Hash_Src = 1'b0 DMA channel
+ * 1'b1 Cipher if word count exceeded Cipher_Offset;
+ * DMA channel otherwise
+ * CkSum_Offset = Nb of words between the first data segment
+ * and word on which to start
+ * checksum calculation (32 BIT WORDS !!!)
+ * CkSum_Src = 1'b0 DMA channel
+ * 1'b1 Cipher if word count exceeded Cipher_Offset
+ * DMA channel otherwise
+ * Cipher dst address = 35 MSB of pointer to dst location (i.e., cache-line aligned)
+ * Dst dword offset = Nb of double-words to left-shift data from spec'ed Cipher dst address before writing it to memory
+ * Global dst data offset = Nb BYTES to left-shift (double-word boundary aligned) data by before writing it to memory
+ *
+ *
+ * PacketDescriptor_t.authDstNonceLow
+ * ----------------------------------
+ *
+ * 63 40 39 5 4 0
+ * -----------------------------------------------------
+ * || Nonce_Low || Auth_dst_address || Cipher_Offset_Hi ||
+ * -----------------------------------------------------
+ * 24 35 5
+ *
+ *
+ *
+ * Nonce_Low = Nonce[23:0] 24 least significant bits of 32-bit long nonce
+ * Used by AES in counter mode
+ * Auth_dst_address = 35 MSB of pointer to authentication dst location (i.e., cache-line aligned)
+ * X0 Cipher_Offset_Hi = On first frag: 5 MSB of 8-bit Cipher_offset; will be concatenated to
+ * the top of PacketDescriptor_t.dstDataSettings.Cipher_Offset
+ * On subsequent frags: Ignored
+ *
+ *
+ * PacketDescriptor_t.ckSumDstNonceHiCFBMaskLLWMask
+ * ------------------------------------------------
+ *
+ *
+ * 63 61 60 58 57 56 55 48 47 40 39 5 4 0
+ * -------------------------------------------------------------------------------------------------------------------
+ * || Hash_Byte_Offset || Packet length bytes || LLWMask || CFB_Mask || Nonce_Hi || CkSum_dst_address || IV_Offset_Hi ||
+ * -------------------------------------------------------------------------------------------------------------------
+ * 3 3 2 8 8 35 5
+ *
+ *
+ * Hash_Byte_Offset = On first frag: Additional offset in bytes to be added to Hash_Offset
+ * to obtain the full offset applied to the data before
+ * submitting it to authenticator
+ * On subsequent frags: Same
+ * Packet length bytes = On one fragment payloads: Ignored (i.e. assumed to be 0, last dword used in its entirety)
+ * On fragments before last: Number of bytes on last fragment dword
+ * On last fragment: Ignored (i.e. assumed to be 0, last dword used in its entirety)
+ * LLWMask, aka, Last_long_word_mask = 2'b00 Give last 128 bit word from AES engine to auth/cksum/wrbbufer as is - applicable in AES CTR only
+ * 2'b11 Mask (zero-out) 32 least significant bits
+ * 2'b10 Mask 64 LSBs
+ * 2'b01 Mask 96 LSBs
+ * If the GCM authenticator is used, setting LLWMask to 2'b10 or 2'b01
+ * will also prevent the transmission of the last DWORD
+ * to the authenticator, i.e., the DWORD before last will
+ * be designated as last for the purposes of authentication.
+ * CFB_Mask = 8 bit mask used by AES in CFB mode
+ * In CTR mode:
+ * CFB_Mask[1:0] = 2'b00 -> Counter[127:0] = {Nonce[31:0], IV0[63:0], 4'h00000001} (only 1 IV exp
+ected) regular CTR
+ * 2'b01 -> Counter[127:0] = {Nonce[31:0], IV0[63:0], IV1[31:0]} (2 IV expected
+) CCMP
+ * 2'b10 -> Counter[127:0] = {IV1[63:0], IV0[31:0], Nonce[31:0]} (2 IV expected
+) GCM with SCI
+ * 2'b11 -> Counter[127:0] = {IDecode.SCI[63:0], IV0[31:0], Nonce[31:0]} (1 IV expected
+) GCM w/o SCI
+ * Nonce_Hi = Nonce[31:24] 8 most significant bits of 32-bit long nonce
+ * Used by AES in counter mode
+ * CkSum_dst_address = 35 MSB of pointer to cksum dst location (i.e., cache-line aligned)
+ * X0 IV_Offset_Hi = On first frag: 5 MSB of 8-bit IV offset; will be concatenated to
+ * the top of PacketDescriptor_t.srcLengthIVOffUseIVNext.IV_Offset
+ * On subsequent frags: Ignored
+ */
+
+/* #define PKT_DSC_LOADHMACKEY */
+#define PKT_DSC_LOADHMACKEY_OLD 0
+#define PKT_DSC_LOADHMACKEY_LOAD 1
+#define PKT_DSC_LOADHMACKEY_LSB 63
+#define PKT_DSC_LOADHMACKEY_BITS ONE_BIT
+#define PKT_DSC_LOADHMACKEY_MASK \
+ (PKT_DSC_LOADHMACKEY_BITS << PKT_DSC_LOADHMACKEY_LSB)
+
+/* #define PKT_DSC_PADHASH */
+#define PKT_DSC_PADHASH_PADDED 0
+#define PKT_DSC_PADHASH_PAD 1 /* requires padding */
+#define PKT_DSC_PADHASH_LSB 62
+#define PKT_DSC_PADHASH_BITS ONE_BIT
+#define PKT_DSC_PADHASH_MASK (PKT_DSC_PADHASH_BITS << PKT_DSC_PADHASH_LSB)
+
+/* #define PKT_DSC_HASHBYTES */
+#define PKT_DSC_HASHBYTES_ALL8 0
+#define PKT_DSC_HASHBYTES_MSB 1
+#define PKT_DSC_HASHBYTES_MSW 2
+#define PKT_DSC_HASHBYTES_LSB 59
+#define PKT_DSC_HASHBYTES_BITS THREE_BITS
+#define PKT_DSC_HASHBYTES_MASK \
+ (PKT_DSC_HASHBYTES_BITS << PKT_DSC_HASHBYTES_LSB)
+
+/* #define PKT_DSC_NEXT */
+#define PKT_DSC_NEXT_FINISH 0
+#define PKT_DSC_NEXT_DO 1
+#define PKT_DSC_NEXT_LSB 58
+#define PKT_DSC_NEXT_BITS ONE_BIT
+#define PKT_DSC_NEXT_MASK (PKT_DSC_NEXT_BITS << PKT_DSC_NEXT_LSB)
+
+/* #define PKT_DSC_IV */
+#define PKT_DSC_IV_OLD 0
+#define PKT_DSC_IV_NEW 1
+#define PKT_DSC_IV_LSB 57
+#define PKT_DSC_IV_BITS ONE_BIT
+#define PKT_DSC_IV_MASK (PKT_DSC_IV_BITS << PKT_DSC_IV_LSB)
+
+/* #define PKT_DSC_IVOFF */
+#define PKT_DSC_IVOFF_LSB 54
+#define PKT_DSC_IVOFF_BITS THREE_BITS
+#define PKT_DSC_IVOFF_MASK (PKT_DSC_IVOFF_BITS << PKT_DSC_IVOFF_LSB)
+
+/* #define PKT_DSC_PKTLEN */
+#define PKT_DSC_PKTLEN_LSB 43
+#define PKT_DSC_PKTLEN_BITS ELEVEN_BITS
+#define PKT_DSC_PKTLEN_MASK (PKT_DSC_PKTLEN_BITS << PKT_DSC_PKTLEN_LSB)
+
+/* #define PKT_DSC_NLHMAC */
+#define PKT_DSC_NLHMAC_LSB 42
+#define PKT_DSC_NLHMAC_BITS ONE_BIT
+#define PKT_DSC_NLHMAC_MASK (PKT_DSC_NLHMAC_BITS << PKT_DSC_NLHMAC_LSB)
+
+/* #define PKT_DSC_BREAK */
+#define PKT_DSC_BREAK_OLD 0
+#define PKT_DSC_BREAK_NEW 1
+#define PKT_DSC_BREAK_LSB 41
+#define PKT_DSC_BREAK_BITS ONE_BIT
+#define PKT_DSC_BREAK_MASK (PKT_DSC_BREAK_BITS << PKT_DSC_BREAK_LSB)
+
+/* #define PKT_DSC_WAIT */
+#define PKT_DSC_WAIT_OLD 0
+#define PKT_DSC_WAIT_NEW 1
+#define PKT_DSC_WAIT_LSB 40
+#define PKT_DSC_WAIT_BITS ONE_BIT
+#define PKT_DSC_WAIT_MASK (PKT_DSC_WAIT_BITS << PKT_DSC_WAIT_LSB)
+
+/* #define PKT_DSC_SEGADDR */
+#define PKT_DSC_SEGADDR_LSB 5
+#define PKT_DSC_SEGADDR_BITS FOURTY_BITS
+#define PKT_DSC_SEGADDR_MASK \
+ (PKT_DSC_SEGADDR_BITS << PKT_DSC_SEGADDR_LSB)
+
+/* #define PKT_DSC_SRTCP */
+#define PKT_DSC_SRTCP_OFF 0
+#define PKT_DSC_SRTCP_ON 1
+#define PKT_DSC_SRTCP_LSB 4
+#define PKT_DSC_SRTCP_BITS ONE_BIT
+#define PKT_DSC_SRTCP_MASK (PKT_DSC_SRTCP_BITS << PKT_DSC_SRTCP_LSB)
+
+#define PKT_DSC_SEGOFFSET_LSB 0
+#define PKT_DSC_SEGOFFSET_BITS THREE_BITS
+#define PKT_DSC_SEGOFFSET_MASK \
+ (PKT_DSC_SEGOFFSET_BITS << PKT_DSC_SEGOFFSET_LSB)
+
+/* **********************************************************************
+ * PacketDescriptor_t.dstDataSettings
+ * **********************************************************************
+ */
+/* #define PKT_DSC_ARC4BYTECOUNT */
+#define PKT_DSC_ARC4BYTECOUNT_ALL8 0
+#define PKT_DSC_ARC4BYTECOUNT_MSB 1
+#define PKT_DSC_ARC4BYTECOUNT_MSW 2
+#define PKT_DSC_ARC4BYTECOUNT_LSB 60
+#define PKT_DSC_ARC4BYTECOUNT_BITS THREE_BITS
+#define PKT_DSC_ARC4BYTECOUNT_MASK (PKT_DSC_ARC4BYTECOUNT_BITS << PKT_DSC_ARC4BYTECOUNT_LSB)
+
+/* #define PKT_DSC_SYM_OP (symmetric key operation) */
+#define PKT_DSC_SYM_OP_DECRYPT 0
+#define PKT_DSC_SYM_OP_ENCRYPT 1
+#define PKT_DSC_SYM_OP_LSB 59
+#define PKT_DSC_SYM_OP_BITS ONE_BIT
+#define PKT_DSC_SYM_OP_MASK (PKT_DSC_SYM_OP_BITS << PKT_DSC_SYM_OP_LSB)
+
+/* #define PKT_DSC_CPHROFF */
+#define PKT_DSC_CPHROFF_LSB 56
+#define PKT_DSC_CPHROFF_BITS THREE_BITS
+#define PKT_DSC_CPHROFF_MASK (PKT_DSC_CPHROFF_BITS << PKT_DSC_CPHROFF_LSB)
+
+/* #define PKT_DSC_HASHOFF */
+#define PKT_DSC_HASHOFF_LSB 54
+#define PKT_DSC_HASHOFF_BITS TWO_BITS
+#define PKT_DSC_HASHOFF_MASK (PKT_DSC_HASHOFF_BITS << PKT_DSC_HASHOFF_LSB)
+
+/* #define PKT_DSC_HASHSRC */
+#define PKT_DSC_HASHSRC_DMA 0
+#define PKT_DSC_HASHSRC_CIPHER 1
+#define PKT_DSC_HASHSRC_LSB 53
+#define PKT_DSC_HASHSRC_BITS ONE_BIT
+#define PKT_DSC_HASHSRC_MASK (PKT_DSC_HASHSRC_BITS << PKT_DSC_HASHSRC_LSB)
+
+/* #define PKT_DSC_CKSUMOFF */
+#define PKT_DSC_CKSUMOFF_LSB 41
+#define PKT_DSC_CKSUMOFF_BITS TWELVE_BITS
+#define PKT_DSC_CKSUMOFF_MASK (PKT_DSC_CKSUMOFF_BITS << PKT_DSC_CKSUMOFF_LSB)
+
+/* #define PKT_DSC_CKSUMSRC */
+#define PKT_DSC_CKSUMSRC_DMA 0
+#define PKT_DSC_CKSUMSRC_CIPHER 1
+#define PKT_DSC_CKSUMSRC_LSB 40
+#define PKT_DSC_CKSUMSRC_BITS ONE_BIT
+#define PKT_DSC_CKSUMSRC_MASK (PKT_DSC_CKSUMSRC_BITS << PKT_DSC_CKSUMSRC_LSB)
+
+/* #define PKT_DSC_CPHR_DST_ADDR */
+#define PKT_DSC_CPHR_DST_ADDR_LSB 0
+#define PKT_DSC_CPHR_DST_ADDR_BITS FOURTY_BITS
+#define PKT_DSC_CPHR_DST_ADDR_MASK \
+ (PKT_DSC_CPHR_DST_ADDR_BITS << PKT_DSC_CPHR_DST_ADDR_LSB)
+
+/* #define PKT_DSC_CPHR_DST_DWOFFSET */
+#define PKT_DSC_CPHR_DST_DWOFFSET_LSB 3
+#define PKT_DSC_CPHR_DST_DWOFFSET_BITS TWO_BITS
+#define PKT_DSC_CPHR_DST_DWOFFSET_MASK \
+ (PKT_DSC_CPHR_DST_DWOFFSET_BITS << PKT_DSC_CPHR_DST_DWOFFSET_LSB)
+
+ /* #define PKT_DSC_CPHR_DST_OFFSET */
+#define PKT_DSC_CPHR_DST_OFFSET_LSB 0
+#define PKT_DSC_CPHR_DST_OFFSET_BITS THREE_BITS
+#define PKT_DSC_CPHR_DST_OFFSET_MASK \
+ (PKT_DSC_CPHR_DST_OFFSET_BITS << PKT_DSC_CPHR_DST_OFFSET_LSB)
+
+/* **********************************************************************
+ * PacketDescriptor_t.authDstNonceLow
+ * **********************************************************************
+ */
+/* #define PKT_DSC_NONCE_LOW */
+#define PKT_DSC_NONCE_LOW_LSB 40
+#define PKT_DSC_NONCE_LOW_BITS TWENTYFOUR_BITS
+#define PKT_DSC_NONCE_LOW_MASK \
+ (PKT_DSC_NONCE_LOW_BITS << PKT_DSC_NONCE_LOW_LSB)
+
+/* #define PKT_DSC_AUTH_DST_ADDR */
+#define PKT_DSC_AUTH_DST_ADDR_LSB 0
+#define PKT_DSC_AUTH_DST_ADDR_BITS FOURTY_BITS
+#define PKT_DSC_AUTH_DST_ADDR_MASK \
+ (PKT_DSC_AUTH_DST_ADDR_BITS << PKT_DSC_AUTH_DST_ADDR_LSB)
+
+/* #define PKT_DSC_CIPH_OFF_HI */
+#define PKT_DSC_CIPH_OFF_HI_LSB 0
+#define PKT_DSC_CIPH_OFF_HI_BITS FIVE_BITS
+#define PKT_DSC_CIPH_OFF_HI_MASK (PKT_DSC_CIPH_OFF_HI_BITS << PKT_DSC_CIPH_OFF_HI_LSB)
+
+/* **********************************************************************
+ * PacketDescriptor_t.ckSumDstNonceHiCFBMaskLLWMask
+ * **********************************************************************
+ */
+/* #define PKT_DSC_HASH_BYTE_OFF */
+#define PKT_DSC_HASH_BYTE_OFF_LSB 61
+#define PKT_DSC_HASH_BYTE_OFF_BITS THREE_BITS
+#define PKT_DSC_HASH_BYTE_OFF_MASK (PKT_DSC_HASH_BYTE_OFF_BITS << PKT_DSC_HASH_BYTE_OFF_LSB)
+
+/* #define PKT_DSC_PKTLEN_BYTES */
+#define PKT_DSC_PKTLEN_BYTES_LSB 58
+#define PKT_DSC_PKTLEN_BYTES_BITS THREE_BITS
+#define PKT_DSC_PKTLEN_BYTES_MASK (PKT_DSC_PKTLEN_BYTES_BITS << PKT_DSC_PKTLEN_BYTES_LSB)
+
+/* #define PKT_DSC_LASTWORD */
+#define PKT_DSC_LASTWORD_128 0
+#define PKT_DSC_LASTWORD_96MASK 1
+#define PKT_DSC_LASTWORD_64MASK 2
+#define PKT_DSC_LASTWORD_32MASK 3
+#define PKT_DSC_LASTWORD_LSB 56
+#define PKT_DSC_LASTWORD_BITS TWO_BITS
+#define PKT_DSC_LASTWORD_MASK (PKT_DSC_LASTWORD_BITS << PKT_DSC_LASTWORD_LSB)
+
+/* #define PKT_DSC_CFB_MASK */
+#define PKT_DSC_CFB_MASK_LSB 48
+#define PKT_DSC_CFB_MASK_BITS EIGHT_BITS
+#define PKT_DSC_CFB_MASK_MASK (PKT_DSC_CFB_MASK_BITS << PKT_DSC_CFB_MASK_LSB)
+
+/* #define PKT_DSC_NONCE_HI */
+#define PKT_DSC_NONCE_HI_LSB 40
+#define PKT_DSC_NONCE_HI_BITS EIGHT_BITS
+#define PKT_DSC_NONCE_HI_MASK (PKT_DSC_NONCE_HI_BITS << PKT_DSC_NONCE_HI_LSB)
+
+/* #define PKT_DSC_CKSUM_DST_ADDR */
+#define PKT_DSC_CKSUM_DST_ADDR_LSB 5
+#define PKT_DSC_CKSUM_DST_ADDR_BITS THIRTY_FIVE_BITS
+#define PKT_DSC_CKSUM_DST_ADDR_MASK (PKT_DSC_CKSUM_DST_ADDR_BITS << PKT_DSC_CKSUM_DST_ADDR_LSB)
+
+/* #define PKT_DSC_IV_OFF_HI */
+#define PKT_DSC_IV_OFF_HI_LSB 0
+#define PKT_DSC_IV_OFF_HI_BITS FIVE_BITS
+#define PKT_DSC_IV_OFF_HI_MASK (PKT_DSC_IV_OFF_HI_BITS << PKT_DSC_IV_OFF_HI_LSB)
+
+
+/* ******************************************************************
+ * Control Error Code and Conditions
+ * ******************************************************************
+ */
+#define CTL_ERR_NONE 0x0000 /* No Error */
+#define CTL_ERR_CIPHER_OP 0x0001 /* Unknown Cipher Op */
+#define CTL_ERR_MODE 0x0002 /* Unknown or Not Allowed Mode */
+#define CTL_ERR_CHKSUM_SRC 0x0004 /* Unknown CkSum Src - UNUSED */
+#define CTL_ERR_CFB_MASK 0x0008 /* Forbidden CFB Mask - UNUSED */
+#define CTL_ERR_OP 0x0010 /* Unknown Ctrl Op - UNUSED */
+#define CTL_ERR_UNDEF1 0x0020 /* UNUSED */
+#define CTL_ERR_UNDEF2 0x0040 /* UNUSED */
+#define CTL_ERR_DATA_READ 0x0080 /* Data Read Error */
+#define CTL_ERR_DESC_CTRL 0x0100 /* Descriptor Ctrl Field Error */
+
+#define CTL_ERR_TIMEOUT 0x1000 /* Message Response Timeout */
+
+/* ******************************************************************
+ * Data Error Code and Conditions
+ * ******************************************************************
+ */
+#define DATA_ERR_NONE 0x0000 /* No Error */
+#define DATA_ERR_LEN_CIPHER 0x0001 /* Not Enough Data To Cipher */
+#define DATA_ERR_IV_ADDR 0x0002 /* Illegal IV Loacation */
+#define DATA_ERR_WD_LEN_AES 0x0004 /* Illegal Nb Words To AES */
+#define DATA_ERR_BYTE_COUNT 0x0008 /* Illegal Pad And ByteCount Spec */
+#define DATA_ERR_LEN_CKSUM 0x0010 /* Not Enough Data To CkSum */
+#define DATA_ERR_OP 0x0020 /* Unknown Data Op */
+#define DATA_ERR_UNDEF1 0x0040 /* UNUSED */
+#define DATA_ERR_READ 0x0080 /* Data Read Error */
+#define DATA_ERR_WRITE 0x0100 /* Data Write Error */
+
+
+/*
+ * Common Descriptor
+ * NOTE: Size of struct is size of cacheline.
+ */
+
+typedef struct OperationDescriptor_s {
+ uint64_t phys_self;
+ uint32_t stn_id;
+ uint32_t flags;
+ uint32_t cpu;
+ uint32_t seq_num;
+ uint64_t vaddr;
+} OperationDescriptor_t, *OperationDescriptor_pt;
+
+
+/*
+ * This defines the security data descriptor format
+ */
+typedef struct PacketDescriptor_s {
+ uint64_t srcLengthIVOffUseIVNext;
+ uint64_t dstDataSettings;
+ uint64_t authDstNonceLow;
+ uint64_t ckSumDstNonceHiCFBMaskLLWMask;
+} PacketDescriptor_t, *PacketDescriptor_pt;
+
+typedef struct {
+ uint8_t *user_auth;
+ uint8_t *user_src;
+ uint8_t *user_dest;
+ uint8_t *user_state;
+ uint8_t *kern_auth;
+ uint8_t *kern_src;
+ uint8_t *kern_dest;
+ uint8_t *kern_state;
+ uint8_t *aligned_auth;
+ uint8_t *aligned_src;
+ uint8_t *aligned_dest;
+ uint8_t *aligned_state;
+} xlr_sec_drv_user_t, *xlr_sec_drv_user_pt;
+
+typedef struct symkey_desc {
+ OperationDescriptor_t op_ctl; /* size is cacheline */
+ PacketDescriptor_t pkt_desc[2]; /* size is cacheline */
+ ControlDescriptor_t ctl_desc; /* makes this aligned */
+ uint64_t control; /* message word0 */
+ uint64_t data; /* message word1 */
+ uint64_t ctl_result;
+ uint64_t data_result;
+ struct symkey_desc *alloc; /* real allocated addr */
+ xlr_sec_drv_user_t user;
+ //volatile atomic_t flag_complete;
+ //struct semaphore sem_complete;
+ //wait_queue_t submit_wait;
+
+ uint8_t *next_src_buf;
+ uint32_t next_src_len;
+
+ uint8_t *next_dest_buf;
+ uint32_t next_dest_len;
+
+ uint8_t *next_auth_dest;
+ uint8_t *next_cksum_dest;
+
+ void *ses;
+} symkey_desc_t, *symkey_desc_pt;
+
+
+/*
+ * **************************************************************************
+ * RSA Block
+ * **************************************************************************
+ */
+
+/*
+ * RSA and ECC Block
+ * =================
+ *
+ * A 2-word message ring descriptor is used to pass all information
+ * pertaining to the RSA or ECC operation:
+ *
+ * 63 61 60 54 53 52 40 39 5 4 3 2 0
+ * -----------------------------------------------------------------------------------------------------
+ * | Ctrl | Op Class | Valid Op | Op Ctrl0 | Source Addr | Software Scratch0 | Global src data offset |
+ * -----------------------------------------------------------------------------------------------------
+ * 3 7 1 13 35 2 3
+ *
+ *
+ * 63 61 60 54 53 52 51 50 40 39 5 4 3 2 0
+ * --------------------------------------------------------------------------------------------------------------------------------
+ * | Ctrl | Destination Id | WRB_COH | WRB_L2ALLOC | DF_L2ALLOC | Op Ctrl1 | Dest Addr | Software Scratch1 | Global dst data offset |
+ * --------------------------------------------------------------------------------------------------------------------------------
+ * 3 7 1 1 1 11 35 2 3
+ *
+ *
+ * Op Class = 7'h0_0 Modular exponentiation
+ * 7'h0_1 ECC (including prime modular ops and binary GF ops)
+ * REMAINDER UNDEF
+ *
+ * Valid Op = 1'b1 Will cause operation to start; descriptors sent back at end of operation
+ * 1'b0 No operation performed; descriptors sent back right away
+ *
+ * RSA ECC
+ * === ===
+ * Op Ctrl0 = BlockWidth[1] {TYPE[6:0], FUNCTION[5:0]}
+ * LoadConstant[1]
+ * ExponentWidth[10:0]
+ * RSA Only
+ * ========
+ * Block Width = 1'b1 1024 bit op
+ * = 1'b0 512 bit op
+ * Load Constant = 1'b1 Load constant from data structure
+ * 1'b0 Preserve old constant (this assumes
+ * Source Addr points to RSAData_pt->Exponent
+ * or that the length of Constant is 0)
+ * Exponent Width = 11-bit expression of exponent width EXPRESSED IN NUMBER OF BITS
+ *
+ * ECC Only
+ * ========
+ *
+ * TYPE = 7'h0_0 ECC prime 160
+ * 7'h0_1 ECC prime 192
+ * 7'h0_2 ECC prime 224
+ * 7'h0_3 ECC prime 256
+ * 7'h0_4 ECC prime 384
+ * 7'h0_5 ECC prime 512
+ *
+ * 7'h0_6 through 7'h1_f UNDEF
+ *
+ * 7'h2_0 ECC bin 163
+ * 7'h2_1 ECC bin 191
+ * 7'h2_2 ECC bin 233
+ *
+ * 7'h2_3 through 7'h6_f UNDEF
+ *
+ * 7'h7_0 ECC UC load
+ *
+ * 7'b7_1 through 7'b7_f UNDEF
+ *
+ * Prime field Binary field
+ * =========== ============
+ * FUNCTION = 6'h0_0 Point multiplication R = k.P Point multiplication R = k.P
+ * 6'h0_1 Point addition R = P + Q Binary GF inversion C(x) = 1 / A(x) mod F(x)
+ * 6'h0_2 Point double R = 2 x P Binary GF multiplication C(x) = B(x) * A(x) mod F(x)
+ * 6'h0_3 Point verification R ? Binary GF addition C(x) = B(x) + A(x) mod F(x)
+ * 6'h0_4 Modular addition c = x + y mod m UNDEF
+ * 6'h0_5 Modular substraction c = x - y mod m UNDEF
+ * 6'h0_6 Modular multiplication c = x * y mod m UNDEF
+ * 6'h0_7 Modular division c = x / y mod m UNDEF
+ * 6'h0_8 Modular inversion c = 1 / y mod m UNDEF
+ * 6'h0_9 Modular reduction c = x mod m UNDEF
+ *
+ * 6'h0_a
+ * through UNDEF UNDEF
+ * 6'h3_f
+ *
+ * Source Addr = 35 MSB of pointer to source address (i.e., cache-line aligned)
+ *
+ * Software Scratch0 = Two bit field ignored by engine and returned as is in free descriptor
+ *
+ * Global src data offset = Nb BYTES to right-shift data by before presenting it to engines
+ * (0-7); allows realignment of byte-aligned, non-double-word aligned data
+ *
+ * RSA ECC
+ * === ===
+ * OpCtrl1 = ModulusWidth[10:0] Not used
+ * RSA Only
+ * ========
+ * Modulus Width = 11-bit expression of modulus width EXPRESSED IN NUMBER OF BITS
+ *
+ * Dest Addr = 35 MSB of pointer to destination address (i.e., cache-line aligned)
+ *
+ * Software Scratch1 = Two bit field ignored by engine and returned as is in free descriptor
+ *
+ * Global dst data offset = Nb BYTES to left-shift (double-word boundary aligned) data by before writing it to memory
+ *
+ *
+ */
+
+/*
+ * ECC data formats
+ */
+
+/**********************************************************
+ * *
+ * ECC prime data formats *
+ * *
+ **********************************************************
+ *
+ *
+ * The size of all quantities below is that of the precision
+ * of the chosen op (160, 192, ...) ROUNDED UP to a multiple
+ * of 8 bytes, i.e., 3 dwords (160, 192), 4 dwords (224, 256)
+ * 6 dwords (384) and 8 dwords (512) and padded with zeroes
+ * when necessary.
+ *
+ * The only exception to this is the key quantity (k) which
+ * needs to be rounded up to 32 bytes in all cases and padded
+ * with zeroes; therefore the key needs to be 4 dwords (160, 192,
+ * 224, 256) or 8 dwords (384, 512)
+ *
+ * The total lengths in dwords that are read and in
+ * bytes that are written, for each operation and
+ * length group, are specified at the bottom of each
+ * datastructure.
+ *
+ * In all that follows, m is the modulus and cst is the constant,
+ * cst = 2 ^ (2*length + 4) mod m . a and b are the curve
+ * parameters.
+ *
+ * 0) UC load
+ *
+ * DATA IN DATA OUT
+ * ======= ========
+ * src+glb_off-> Dword_0 N/A
+ * .
+ * .
+ * .
+ * Dword_331
+ * 332 dw
+ *
+ * 1) Point multiplication R(x_r, y_r) = k . P(x_p, y_p)
+ *
+ * DATA IN DATA OUT
+ * ======= ========
+ * src+glb_off-> x_p dst+glb_off-> x_r
+ * x_p y_r
+ * y_p 2x(3/4/6/8)=
+ * y_p 6/8/12/16 dw
+ * a
+ * k
+ * m
+ * cst
+ * 7x(3/4/6/8)+(4/4/8/8)=
+ * 25/32/50/64 dw
+ *
+ * 2) Point addition R(x_r, y_r) = P(x_p, y_p) + Q(x_q, y_q)
+ *
+ * DATA IN DATA OUT
+ * ======= ========
+ * src+glb_off-> x_p dst+glb_off-> x_r
+ * y_p y_r
+ * x_q 2x(3/4/6/8)=
+ * y_q 6/8/12/16 dw
+ * a
+ * m
+ * cst
+ * 7x(3/4/6/8)=
+ * 21/28/42/56 dw
+ *
+ * 3) Point double R(x_r, y_r) = 2 . P(x_p, y_p)
+ *
+ * DATA IN DATA OUT
+ * ======= ========
+ * src+glb_off-> x_p dst+glb_off-> x_r
+ * y_p y_r
+ * a 2x(3/4/6/8)=
+ * m 6/8/12/16 dw
+ * cst
+ * 5x(3/4/6/8)=
+ * 15/20/30/40 dw
+ *
+ * 4) Point verification Is_On_Curve = P(x_p, y_p) on curve ? 1 : 0
+ *
+ * DATA IN DATA OUT
+ * ======= ========
+ * src+glb_off-> x_p dst+glb_off-> Is_On_Curve
+ * y_p 1 dw
+ * a
+ * b
+ * m
+ * cst
+ * 6x(3/4/6/8)=
+ * 18/24/36/48 dw
+ *
+ * 5) Modular addition c = x + y mod m
+ *
+ * DATA IN DATA OUT
+ * ======= ========
+ * src+glb_off-> x dst+glb_off-> c
+ * y 3/4/6/8 dw
+ * m
+ * 3x(3/4/6/8)=
+ * 9/12/18/24 dw
+ *
+ * 6) Modular substraction c = x - y mod m
+ *
+ * DATA IN DATA OUT
+ * ======= ========
+ * src+glb_off-> x dst+glb_off-> c
+ * y 3/4/6/8 dw
+ * m
+ * 3x(3/4/6/8)=
+ * 9/12/18/24 dw
+ *
+ * 7) Modular multiplication c = x * y mod m
+ *
+ * DATA IN DATA OUT
+ * ======= ========
+ * src+glb_off-> x dst+glb_off-> c
+ * y 3/4/6/8 dw
+ * m
+ * cst
+ * 4x(3/4/6/8)=
+ * 12/16/24/32 dw
+ *
+ * 8) Modular division c = x / y mod m
+ *
+ * DATA IN DATA OUT
+ * ======= ========
+ * src+glb_off-> y dst+glb_off-> c
+ * x 3/4/6/8 dw
+ * m
+ * 3x(3/4/6/8)=
+ * 9/12/18/24 dw
+ *
+ * 9) Modular inversion c = 1 / y mod m
+ *
+ * DATA IN DATA OUT
+ * ======= ========
+ * src+glb_off-> y dst+glb_off-> c
+ * m 3/4/6/8 dw
+ * 2x(3/4/6/8)=
+ * 6/8/12/16 dw
+ *
+ * 10) Modular reduction c = x mod m
+ *
+ * DATA IN DATA OUT
+ * ======= ========
+ * src+glb_off-> x dst+glb_off-> c
+ * m 3/4/6/8 dw
+ * 2x(3/4/6/8)=
+ * 6/8/12/16 dw
+ *
+ */
+
+/**********************************************************
+ * *
+ * ECC binary data formats *
+ * *
+ **********************************************************
+ *
+ *
+ * The size of all quantities below is that of the precision
+ * of the chosen op (163, 191, 233) ROUNDED UP to a multiple
+ * of 8 bytes, i.e. 3 dwords for (163, 191) and 4 dwords for
+ * (233), padded with zeroes as necessary.
+ *
+ * The total lengths in dwords that are read and written,
+ * for each operation and length group, are specified
+ * at the bottom of each datastructure.
+ * In all that follows, b is the curve parameter.
+ *
+ * 1) Point multiplication R(x_r, y_r) = k . P(x_p, y_p)
+ *
+ * DATA IN DATA OUT
+ * ======= ========
+ * src+glb_off-> b dst+glb_off-> x_r
+ * k y_r
+ * x_p 2x(3/4)
+ * y_p 6/8 dw
+ * 4x(3/4)=
+ * 12/16 dw
+ *
+ * 2) Binary GF inversion C(x) = 1 / A(x) mod F(x)
+ *
+ * DATA IN DATA OUT
+ * ======= ========
+ * src+glb_off-> A dst+glb_off-> C
+ * 1x(3/4)= 1x(3/4)
+ * 3/4 dw 3/4 dw
+ *
+ * 3) Binary GF multiplication C(x) = B(x) * A(x) mod F(x)
+ *
+ * DATA IN DATA OUT
+ * ======= ========
+ * src+glb_off-> A dst+glb_off-> C
+ * B 1x(3/4)
+ * 2x(3/4)= 3/4 dw
+ * 6/8 dw
+ *
+ * 4) Binary GF addition C(x) = B(x) + A(x) mod F(x)
+ *
+ * DATA IN DATA OUT
+ * ======= ========
+ * src+glb_off-> A dst+glb_off-> C
+ * B 1x(3/4)
+ * 2x(3/4)= 3/4 dw
+ * 6/8dw
+ *
+ */
+
+/*
+ * RSA data format
+ */
+
+/*
+ * IMPORTANT NOTE:
+ *
+ * As specified in the datastructures below,
+ * the engine assumes all data (including
+ * exponent and modulus) to be adjacent on
+ * dword boundaries, e.g.,
+ *
+ * Operation length = 512 bits
+ * Exponent length = 16 bits
+ * Modulus length = 512 bits
+ *
+ * The engine expects to read:
+ *
+ * 63 0
+ * -----------------------
+ * | | Constant0
+ * -----------------------
+ * | | Constant1
+ * -----------------------
+ * | | Constant2
+ * -----------------------
+ * | | Constant3
+ * -----------------------
+ * | | Constant4
+ * -----------------------
+ * | | Constant5
+ * -----------------------
+ * | | Constant6
+ * -----------------------
+ * | | Constant7
+ * -----------------------
+ * | IGNORED |B1|B0| Exponent0 (Exponent length = 16 bits = 2 bytes, so only 2 least significant bytes of exponent used)
+ * -----------------------
+ * | | Modulus0
+ * -----------------------
+ * | | Modulus1
+ * -----------------------
+ * | | Modulus2
+ * -----------------------
+ * | | Modulus3
+ * -----------------------
+ * | | Modulus4
+ * -----------------------
+ * | | Modulus5
+ * -----------------------
+ * | | Modulus6
+ * -----------------------
+ * | | Modulus7
+ * -----------------------
+ * | | Message0
+ * -----------------------
+ * | | Message1
+ * -----------------------
+ * | | Message2
+ * -----------------------
+ * | | Message3
+ * -----------------------
+ * | | Message4
+ * -----------------------
+ * | | Message5
+ * -----------------------
+ * | | Message6
+ * -----------------------
+ * | | Message7
+ * -----------------------
+ *
+ */
+
+/* #define PUBKEY_CTL_CTL */
+#define PUBKEY_CTL_CTL_LSB 61
+#define PUBKEY_CTL_CTL_BITS THREE_BITS
+#define PUBKEY_CTL_CTL_MASK (PUBKEY_CTL_CTL_BITS << PUBKEY_CTL_CTL_LSB)
+
+/* #define PUBKEY_CTL_OP_CLASS */
+#define PUBKEY_CTL_OP_CLASS_RSA 0
+#define PUBKEY_CTL_OP_CLASS_ECC 1
+#define PUBKEY_CTL_OP_CLASS_LSB 54
+#define PUBKEY_CTL_OP_CLASS_BITS SEVEN_BITS
+#define PUBKEY_CTL_OP_CLASS_MASK (PUBKEY_CTL_OP_CLASS_BITS << PUBKEY_CTL_OP_CLASS_LSB)
+
+/* #define PUBKEY_CTL_VALID */
+#define PUBKEY_CTL_VALID_FALSE 0
+#define PUBKEY_CTL_VALID_TRUE 1
+#define PUBKEY_CTL_VALID_LSB 53
+#define PUBKEY_CTL_VALID_BITS ONE_BIT
+#define PUBKEY_CTL_VALID_MASK \
+ (PUBKEY_CTL_VALID_BITS << PUBKEY_CTL_VALID_LSB)
+
+/* #define PUBKEY_CTL_ECC_TYPE */
+#define PUBKEY_CTL_ECC_TYPE_PRIME_160 0
+#define PUBKEY_CTL_ECC_TYPE_PRIME_192 1
+#define PUBKEY_CTL_ECC_TYPE_PRIME_224 2
+#define PUBKEY_CTL_ECC_TYPE_PRIME_256 3
+#define PUBKEY_CTL_ECC_TYPE_PRIME_384 4
+#define PUBKEY_CTL_ECC_TYPE_PRIME_512 5
+#define PUBKEY_CTL_ECC_TYPE_BIN_163 0x20
+#define PUBKEY_CTL_ECC_TYPE_BIN_191 0x21
+#define PUBKEY_CTL_ECC_TYPE_BIN_233 0x22
+#define PUBKEY_CTL_ECC_TYPE_UC_LOAD 0x70
+#define PUBKEY_CTL_ECC_TYPE_LSB 46
+#define PUBKEY_CTL_ECC_TYPE_BITS SEVEN_BITS
+#define PUBKEY_CTL_ECC_TYPE_MASK (PUBKEY_CTL_ECC_TYPE_BITS << PUBKEY_CTL_ECC_TYPE_LSB)
+
+/* #define PUBKEY_CTL_ECC_FUNCTION */
+#define PUBKEY_CTL_ECC_FUNCTION_NOP 0
+#define PUBKEY_CTL_ECC_FUNCTION_POINT_MUL 0
+#define PUBKEY_CTL_ECC_FUNCTION_POINT_ADD 1
+#define PUBKEY_CTL_ECC_FUNCTION_POINT_DBL 2
+#define PUBKEY_CTL_ECC_FUNCTION_POINT_VFY 3
+#define PUBKEY_CTL_ECC_FUNCTION_MODULAR_ADD 4
+#define PUBKEY_CTL_ECC_FUNCTION_MODULAR_SUB 5
+#define PUBKEY_CTL_ECC_FUNCTION_MODULAR_MUL 6
+#define PUBKEY_CTL_ECC_FUNCTION_MODULAR_DIV 7
+#define PUBKEY_CTL_ECC_FUNCTION_MODULAR_INV 8
+#define PUBKEY_CTL_ECC_FUNCTION_MODULAR_RED 9
+#define PUBKEY_CTL_ECC_FUNCTION_LSB 40
+#define PUBKEY_CTL_ECC_FUNCTION_BITS SIX_BITS
+#define PUBKEY_CTL_ECC_FUNCTION_MASK (PUBKEY_CTL_ECC_FUNCTION_BITS << PUBKEY_CTL_ECC_FUNCTION_LSB)
+
+/* #define PUBKEY_CTL_BLKWIDTH */
+#define PUBKEY_CTL_BLKWIDTH_512 0
+#define PUBKEY_CTL_BLKWIDTH_1024 1
+#define PUBKEY_CTL_BLKWIDTH_LSB 52
+#define PUBKEY_CTL_BLKWIDTH_BITS ONE_BIT
+#define PUBKEY_CTL_BLKWIDTH_MASK \
+ (PUBKEY_CTL_BLKWIDTH_BITS << PUBKEY_CTL_BLKWIDTH_LSB)
+
+/* #define PUBKEY_CTL_LD_CONST */
+#define PUBKEY_CTL_LD_CONST_OLD 0
+#define PUBKEY_CTL_LD_CONST_NEW 1
+#define PUBKEY_CTL_LD_CONST_LSB 51
+#define PUBKEY_CTL_LD_CONST_BITS ONE_BIT
+#define PUBKEY_CTL_LD_CONST_MASK \
+ (PUBKEY_CTL_LD_CONST_BITS << PUBKEY_CTL_LD_CONST_LSB)
+
+/* #define PUBKEY_CTL_EXPWIDTH */
+#define PUBKEY_CTL_EXPWIDTH_LSB 40
+#define PUBKEY_CTL_EXPWIDTH_BITS ELEVEN_BITS
+#define PUBKEY_CTL_EXPWIDTH_MASK \
+ (PUBKEY_CTL_EXPWIDTH_BITS << PUBKEY_CTL_EXPWIDTH_LSB)
+
+/* #define PUBKEY_CTL_SRCADDR */
+#define PUBKEY_CTL_SRCADDR_LSB 0
+#define PUBKEY_CTL_SRCADDR_BITS FOURTY_BITS
+#define PUBKEY_CTL_SRCADDR_MASK \
+ (PUBKEY_CTL_SRCADDR_BITS << PUBKEY_CTL_SRCADDR_LSB)
+
+/* #define PUBKEY_CTL_SRC_OFFSET */
+#define PUBKEY_CTL_SRC_OFFSET_LSB 0
+#define PUBKEY_CTL_SRC_OFFSET_BITS THREE_BITS
+#define PUBKEY_CTL_SRC_OFFSET_MASK \
+ (PUBKEY_CTL_SRC_OFFSET_BITS << PUBKEY_CTL_SRC_OFFSET_LSB)
+
+
+/* #define PUBKEY_CTL1_CTL */
+#define PUBKEY_CTL1_CTL_LSB 61
+#define PUBKEY_CTL1_CTL_BITS THREE_BITS
+#define PUBKEY_CTL1_CTL_MASK (PUBKEY_CTL_CTL_BITS << PUBKEY_CTL_CTL_LSB)
+
+/* #define PUBKEY_CTL1_MODWIDTH */
+#define PUBKEY_CTL1_MODWIDTH_LSB 40
+#define PUBKEY_CTL1_MODWIDTH_BITS ELEVEN_BITS
+#define PUBKEY_CTL1_MODWIDTH_MASK \
+ (PUBKEY_CTL1_MODWIDTH_BITS << PUBKEY_CTL1_MODWIDTH_LSB)
+
+/* #define PUBKEY_CTL1_DSTADDR */
+#define PUBKEY_CTL1_DSTADDR_LSB 0
+#define PUBKEY_CTL1_DSTADDR_BITS FOURTY_BITS
+#define PUBKEY_CTL1_DSTADDR_MASK \
+ (PUBKEY_CTL1_DSTADDR_BITS << PUBKEY_CTL1_DSTADDR_LSB)
+
+/* #define PUBKEY_CTL1_DST_OFFSET */
+#define PUBKEY_CTL1_DST_OFFSET_LSB 0
+#define PUBKEY_CTL1_DST_OFFSET_BITS THREE_BITS
+#define PUBKEY_CTL1_DST_OFFSET_MASK \
+ (PUBKEY_CTL1_DST_OFFSET_BITS << PUBKEY_CTL1_DST_OFFSET_LSB)
+
+/*
+ * Upon completion of operation, the RSA block returns a 2-word free descriptor
+ * in the following format:
+ *
+ * 63 61 60 54 53 52 51 49 48 40 39 5 4 3 2 0
+ * -------------------------------------------------------------------------------------------------------------------------
+ * | Ctrl | Destination Id | 2'b00 | Desc Ctrl | Control Error | Source Address | Software Scratch0 | Global src data offset |
+ * -------------------------------------------------------------------------------------------------------------------------
+ * | Ctrl | Destination Id | 2'b00 | Desc Ctrl | Data Error | Dest Address | Software Scratch1 | Global dst data offset |
+ * -------------------------------------------------------------------------------------------------------------------------
+ *
+ * The Control and Data Error codes are enumerated below
+ *
+ * Error conditions
+ * ================
+ *
+ * Control Error Code Control Error Condition
+ * ------------------ -----------------------
+ * 9'h000 No Error
+ * 9'h001 Undefined Op Class
+ * 9'h002 Undefined ECC TYPE (ECC only)
+ * 9'h004 Undefined ECC FUNCTION (ECC only)
+ * 9'h008 ECC timeout (ECC only)
+ * 9'h010 UNUSED
+ * 9'h020 UNUSED
+ * 9'h040 UNUSED
+ * 9'h080 Data Read Error
+ * 9'h100 Descriptor Ctrl Field Error (D0.Ctrl != SOP || D1.Ctrl != EOP)
+ *
+ * Data Error Code Data Error Condition
+ * --------------- --------------------
+ * 9'h000 No Error
+ * 9'h001 Exponent Width > Block Width (RSA Only)
+ * 9'h002 Modulus Width > Block Width (RSA Only)
+ * 9'h004 UNUSED
+ * 9'h008 UNUSED
+ * 9'h010 UNUSED
+ * 9'h020 UNUSED
+ * 9'h040 UNUSED
+ * 9'h080 Data Read Error
+ * 9'h100 UNUSED
+ */
+
+/*
+ * Result Data Word for Message Ring Descriptor
+ */
+
+/* #define PUBKEY_RSLT_CTL_CTL */
+#define PUBKEY_RSLT_CTL_CTL_LSB 61
+#define PUBKEY_RSLT_CTL_CTL_BITS THREE_BITS
+#define PUBKEY_RSLT_CTL_CTL_MASK \
+ (PUBKEY_RSLT_CTL_CTL_BITS << PUBKEY_RSLT_CTL_CTL_LSB)
+
+/* #define PUBKEY_RSLT_CTL_DST_ID */
+#define PUBKEY_RSLT_CTL_DST_ID_LSB 54
+#define PUBKEY_RSLT_CTL_DST_ID_BITS SEVEN_BITS
+#define PUBKEY_RSLT_CTL_DST_ID_MASK \
+ (PUBKEY_RSLT_CTL_DST_ID_BITS << PUBKEY_RSLT_CTL_DST_ID_LSB)
+
+/* #define PUBKEY_RSLT_CTL_DESC_CTL */
+#define PUBKEY_RSLT_CTL_DESC_CTL_LSB 49
+#define PUBKEY_RSLT_CTL_DESC_CTL_BITS THREE_BITS
+#define PUBKEY_RSLT_CTL_DESC_CTL_MASK \
+ (PUBKEY_RSLT_CTL_DESC_CTL_BITS << PUBKEY_RSLT_CTL_DESC_CTL_LSB)
+
+
+/* #define PUBKEY_RSLT_CTL_ERROR */
+#define PUBKEY_RSLT_CTL_ERROR_LSB 40
+#define PUBKEY_RSLT_CTL_ERROR_BITS NINE_BITS
+#define PUBKEY_RSLT_CTL_ERROR_MASK \
+ (PUBKEY_RSLT_CTL_ERROR_BITS << PUBKEY_RSLT_CTL_ERROR_LSB)
+
+/* #define PUBKEY_RSLT_CTL_SRCADDR */
+#define PUBKEY_RSLT_CTL_SRCADDR_LSB 0
+#define PUBKEY_RSLT_CTL_SRCADDR_BITS FOURTY_BITS
+#define PUBKEY_RSLT_CTL_SRCADDR_MASK \
+ (PUBKEY_RSLT_CTL_SRCADDR_BITS << PUBKEY_RSLT_CTL_SRCADDR_LSB)
+
+
+/* #define PUBKEY_RSLT_DATA_CTL */
+#define PUBKEY_RSLT_DATA_CTL_LSB 61
+#define PUBKEY_RSLT_DATA_CTL_BITS THREE_BITS
+#define PUBKEY_RSLT_DATA_CTL_MASK \
+ (PUBKEY_RSLT_DATA_CTL_BITS << PUBKEY_RSLT_DATA_CTL_LSB)
+
+/* #define PUBKEY_RSLT_DATA_DST_ID */
+#define PUBKEY_RSLT_DATA_DST_ID_LSB 54
+#define PUBKEY_RSLT_DATA_DST_ID_BITS SEVEN_BITS
+#define PUBKEY_RSLT_DATA_DST_ID_MASK \
+ (PUBKEY_RSLT_DATA_DST_ID_BITS << PUBKEY_RSLT_DATA_DST_ID_LSB)
+
+/* #define PUBKEY_RSLT_DATA_DESC_CTL */
+#define PUBKEY_RSLT_DATA_DESC_CTL_LSB 49
+#define PUBKEY_RSLT_DATA_DESC_CTL_BITS THREE_BITS
+#define PUBKEY_RSLT_DATA_DESC_CTL_MASK \
+ (PUBKEY_RSLT_DATA_DESC_CTL_BITS << PUBKEY_RSLT_DATA_DESC_CTL_LSB)
+
+/* #define PUBKEY_RSLT_DATA_ERROR */
+#define PUBKEY_RSLT_DATA_ERROR_LSB 40
+#define PUBKEY_RSLT_DATA_ERROR_BITS NINE_BITS
+#define PUBKEY_RSLT_DATA_ERROR_MASK \
+ (PUBKEY_RSLT_DATA_ERROR_BITS << PUBKEY_RSLT_DATA_ERROR_LSB)
+
+/* #define PUBKEY_RSLT_DATA_DSTADDR */
+#define PUBKEY_RSLT_DATA_DSTADDR_LSB 40
+#define PUBKEY_RSLT_DATA_DSTADDR_BITS FOURTY_BITS
+#define PUBKEY_RSLT_DATA_DSTADDR_MASK \
+ (PUBKEY_RSLT_DATA_DSTADDR_BITS << PUBKEY_RSLT_DATA_DSTADDR_LSB)
+
+/*
+ * ******************************************************************
+ * RSA Block - Data Error Code and Conditions
+ * ******************************************************************
+ */
+
+#define PK_CTL_ERR_NONE 0x0000 /* No Error */
+#define PK_CTL_ERR_OP_CLASS 0x0001 /* Undefined Op Class */
+#define PK_CTL_ERR_ECC_TYPE 0x0002 /* Undefined ECC TYPE (ECC only) */
+#define PK_CTL_ERR_ECC_FUNCT 0x0004 /* Undefined ECC FUNCTION (ECC only) */
+#define PK_CTL_ERR_ECC_TIMEOUT 0x0008 /* ECC timeout (ECC only) */
+#define PK_CTL_ERR_READ 0x0080 /* Data Read Error */
+#define PK_CTL_ERR_DESC 0x0100 /* Descriptor Ctrl Field Error
+ * (D0.Ctrl != SOP || D1.Ctrl != EOP) */
+#define PK_CTL_ERR_TIMEOUT 0x1000 /* Message Responce Timeout */
+
+#define PK_DATA_ERR_NONE 0x0000 /* No Error */
+#define PK_DATA_ERR_EXP_WIDTH 0x0001 /* Exponent Width > Block Width */
+#define PK_DATA_ERR_MOD_WIDTH 0x0002 /* Modulus Width > Block Width */
+#define PK_DATA_ERR_READ 0x0080 /* Data Read Error */
+
+
+/*
+ * This defines the RSA data format
+ */
+/*
+ * typedef struct RSAData_s {
+ * uint64_t Constant;
+ * uint64_t Exponent;
+ * uint64_t Modulus;
+ * uint64_t Message;
+ *} RSAData_t, *RSAData_pt;
+ *
+ * typedef RSAData_t DHData_t;
+ * typedef RSAData_pt DHData_pt;
+ */
+
+typedef struct UserPubData_s {
+ uint8_t *source;
+ uint8_t *user_result;
+ uint32_t result_length;
+} UserPubData_t, *UserPubData_pt;
+
+typedef struct pubkey_desc {
+ OperationDescriptor_t op_ctl; /* size is cacheline */
+ uint8_t source[1024];
+ uint8_t dest[256]; /* 1024 makes cacheline-aligned */
+ uint64_t control0;
+ uint64_t control1;
+ uint64_t ctl_result;
+ uint64_t data_result;
+ struct pubkey_desc *alloc;
+ UserPubData_t kern; /* ptrs for temp buffers */
+ //volatile atomic_t flag_complete;
+ //struct semaphore sem_complete;
+ //wait_queue_t submit_wait;
+} pubkey_desc_t, *pubkey_desc_pt;
+
+/*
+ * KASUMI F8 and F9 use the IV0/IV1 fields :
+ *
+ * 63 41 40 39 37 36 32 31 0
+ * ----------------------------------------------------------------------------
+ * | |FX/DIRECTION| | F8/BEARER | F8/COUNT | IV0
+ * ----------------------------------------------------------------------------
+ * 1 5 32
+ *
+ * 63 32 31 0
+ * ----------------------------------------------------------------------------
+ * | F9/FRESH | F9/COUNT | IV1
+ * ----------------------------------------------------------------------------
+ * 32 32
+ */
+#endif /* _XLR_SEC_DESC_H_ */
Property changes on: trunk/sys/mips/rmi/dev/sec/desc.h
___________________________________________________________________
Added: svn:eol-style
## -0,0 +1 ##
+native
\ No newline at end of property
Added: svn:keywords
## -0,0 +1 ##
+MidnightBSD=%H
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+text/plain
\ No newline at end of property
Added: trunk/sys/mips/rmi/dev/sec/rmilib.c
===================================================================
--- trunk/sys/mips/rmi/dev/sec/rmilib.c (rev 0)
+++ trunk/sys/mips/rmi/dev/sec/rmilib.c 2018-05-26 21:55:02 UTC (rev 9987)
@@ -0,0 +1,3075 @@
+/* $MidnightBSD$ */
+/*-
+ * Copyright (c) 2003-2009 RMI Corporation
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * 3. Neither the name of RMI Corporation, nor the names of its contributors,
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ * RMI_BSD
+ */
+
+#include <sys/cdefs.h>
+__FBSDID("$FreeBSD: stable/10/sys/mips/rmi/dev/sec/rmilib.c 212763 2010-09-16 20:23:22Z jchandra $");
+
+#include <sys/param.h>
+#include <sys/types.h>
+#include <sys/systm.h>
+#include <sys/kernel.h>
+#include <sys/module.h>
+#include <sys/malloc.h>
+#include <sys/bus.h>
+#include <machine/bus.h>
+#include <machine/md_var.h>
+#include <machine/cpuregs.h>
+
+#include <vm/vm.h>
+#include <vm/pmap.h>
+
+#include <opencrypto/cryptodev.h>
+
+#include <mips/rmi/rmi_mips_exts.h>
+#include <mips/rmi/iomap.h>
+#include <mips/rmi/pic.h>
+#include <mips/rmi/rmi_boot_info.h>
+#include <mips/rmi/msgring.h>
+#include <mips/rmi/board.h>
+#include <mips/rmi/dev/sec/rmilib.h>
+#include <mips/rmi/dev/sec/desc.h>
+
+
+/* static int msgrng_stnid_pk0 = MSGRNG_STNID_PK0; */
+
+/* #define RMI_SEC_DEBUG */
+
+#define SMP_CACHE_BYTES XLR_CACHELINE_SIZE
+#define NUM_CHUNKS(size, bits) ( ((size)>>(bits)) + (((size)&((1<<(bits))-1))?1:0) )
+
+static const char nib2hex[] = "0123456789ABCDEF";
+symkey_desc_pt g_desc;
+struct xlr_sec_command *g_cmd;
+
+#ifdef XLR_SEC_CMD_DEBUG
+static void decode_symkey_desc(symkey_desc_pt desc, uint32_t cfg_vector);
+#endif
+
+static int xlr_sec_cipher_hash_command(xlr_sec_io_pt op, symkey_desc_pt desc,
+ uint8_t);
+static xlr_sec_error_t xlr_sec_setup_descriptor(xlr_sec_io_pt op,
+ unsigned int flags, symkey_desc_pt desc, uint32_t * cfg_vector);
+
+static xlr_sec_error_t xlr_sec_setup_packet(xlr_sec_io_pt op,
+ symkey_desc_pt desc, unsigned int flags, uint64_t * data,
+ PacketDescriptor_pt pkt_desc, ControlDescriptor_pt ctl_desc,
+ uint32_t vector, PacketDescriptor_pt next_pkt_desc,
+ uint8_t multi_frag_flag);
+static int xlr_sec_submit_message(symkey_desc_pt desc, uint32_t cfg_vector);
+static xlr_sec_error_t xlr_sec_setup_cipher(xlr_sec_io_pt op,
+ ControlDescriptor_pt ctl_desc, uint32_t * vector);
+static xlr_sec_error_t xlr_sec_setup_digest(xlr_sec_io_pt op,
+ ControlDescriptor_pt ctl_desc, uint32_t * vector);
+static xlr_sec_error_t xlr_sec_setup_cksum(xlr_sec_io_pt op,
+ ControlDescriptor_pt ctl_desc);
+static xlr_sec_error_t xlr_sec_control_setup(xlr_sec_io_pt op,
+ unsigned int flags, uint64_t * control, ControlDescriptor_pt ctl_desc,
+ xlr_sec_drv_user_t * user, uint32_t vector);
+static void xlr_sec_free_desc(symkey_desc_pt desc);
+
+void print_buf(char *desc, void *data, int len);
+xlr_sec_error_t xlr_sec_submit_op(symkey_desc_pt desc);
+void xlr_sec_msgring_handler(int bucket, int size, int code, int stid,
+ struct msgrng_msg *msg, void *data);
+
+void
+xlr_sec_init(struct xlr_sec_softc *sc)
+{
+ unsigned int i;
+ xlr_reg_t *mmio;
+
+ mmio = sc->mmio = xlr_io_mmio(XLR_IO_SECURITY_OFFSET);
+ xlr_write_reg(mmio, SEC_DMA_CREDIT, SEC_DMA_CREDIT_CONFIG);
+ xlr_write_reg(mmio, SEC_CONFIG2, SEC_CFG2_ROUND_ROBIN_ON);
+
+ for (i = 0; i < 8; i++)
+ xlr_write_reg(mmio,
+ SEC_MSG_BUCKET0_SIZE + i,
+ xlr_is_xls() ?
+ xls_bucket_sizes.bucket[MSGRNG_STNID_SEC + i] :
+ bucket_sizes.bucket[MSGRNG_STNID_SEC + i]);
+
+ for (i = 0; i < 128; i++)
+ xlr_write_reg(mmio,
+ SEC_CC_CPU0_0 + i,
+ xlr_is_xls() ?
+ xls_cc_table_sec.counters[i >> 3][i & 0x07] :
+ cc_table_sec.counters[i >> 3][i & 0x07]);
+
+ /*
+ * Register a bucket handler with the phoenix messaging subsystem
+ * For now, register handler for bucket 0->5 in msg stn 0
+ */
+ if (register_msgring_handler(TX_STN_SAE, xlr_sec_msgring_handler, NULL)) {
+ panic("Couldn't register msgring handler 0\n");
+ }
+ return;
+}
+
+int
+xlr_sec_setup(struct xlr_sec_session *ses,
+ struct xlr_sec_command *cmd,
+ symkey_desc_pt desc)
+{
+ xlr_sec_io_pt op;
+ int size, ret_val;
+ int iv_len;
+
+ desc->ses = ses;
+ op = &cmd->op;
+ if (op == NULL)
+ return (-ENOMEM);
+
+ desc->ctl_desc.instruction = 0;
+ memset(&desc->ctl_desc.cipherHashInfo, 0, sizeof(CipherHashInfo_t));
+ desc->control = 0;
+ desc->pkt_desc[0].srcLengthIVOffUseIVNext = 0;
+ desc->pkt_desc[0].dstDataSettings = 0;
+ desc->pkt_desc[0].authDstNonceLow = 0;
+ desc->pkt_desc[0].ckSumDstNonceHiCFBMaskLLWMask = 0;
+ desc->pkt_desc[1].srcLengthIVOffUseIVNext = 0;
+ desc->pkt_desc[1].dstDataSettings = 0;
+ desc->pkt_desc[1].authDstNonceLow = 0;
+ desc->pkt_desc[1].ckSumDstNonceHiCFBMaskLLWMask = 0;
+ desc->data = 0;
+ desc->ctl_result = 0;
+ desc->data_result = 0;
+
+ if (op->flags & XLR_SEC_FLAGS_HIGH_PRIORITY)
+ if (!xlr_is_xls())
+ desc->op_ctl.stn_id++;
+
+ desc->user.user_src = (uint8_t *) (unsigned long)op->source_buf;
+ desc->user.user_dest = (uint8_t *) (unsigned long)op->dest_buf;
+ desc->user.user_auth = (uint8_t *) (unsigned long)op->auth_dest;
+
+ if ((op->cipher_type == XLR_SEC_CIPHER_TYPE_ARC4) &&
+ (!op->rc4_state && (op->rc4_loadstate || op->rc4_savestate))) {
+ printf(" ** Load/Save State and no State **");
+ xlr_sec_free_desc(desc);
+ return (-EINVAL);
+ }
+ desc->user.user_state = (uint8_t *) (unsigned long)op->rc4_state;
+
+ switch (op->cipher_type) {
+ case XLR_SEC_CIPHER_TYPE_NONE:
+ iv_len = 0;
+ break;
+ case XLR_SEC_CIPHER_TYPE_DES:
+ case XLR_SEC_CIPHER_TYPE_3DES:
+ iv_len = XLR_SEC_DES_IV_LENGTH;
+ break;
+ case XLR_SEC_CIPHER_TYPE_AES128:
+ case XLR_SEC_CIPHER_TYPE_AES192:
+ case XLR_SEC_CIPHER_TYPE_AES256:
+ iv_len = XLR_SEC_AES_IV_LENGTH;
+ break;
+ case XLR_SEC_CIPHER_TYPE_ARC4:
+ iv_len = XLR_SEC_ARC4_IV_LENGTH;
+ break;
+ case XLR_SEC_CIPHER_TYPE_KASUMI_F8:
+ iv_len = XLR_SEC_KASUMI_F8_IV_LENGTH;
+ break;
+
+ default:
+ printf(" ** Undefined Cipher Type **");
+ xlr_sec_free_desc(desc);
+ return (-EINVAL);
+ }
+ size = op->source_buf_size + iv_len;
+
+ /*
+ * make sure that there are enough bytes for aes based stream
+ * ciphers
+ */
+ if (op->cipher_mode == XLR_SEC_CIPHER_MODE_F8 ||
+ op->cipher_mode == XLR_SEC_CIPHER_MODE_CTR)
+ size += XLR_SEC_AES_BLOCK_SIZE - 1;
+
+ if (op->cipher_type == XLR_SEC_CIPHER_TYPE_NONE) {
+ if (op->source_buf_size != 0) {
+ memcpy(desc->user.aligned_src,
+ (uint8_t *)(uintptr_t)op->source_buf,
+ op->source_buf_size);
+ }
+ } else {
+ if (ses->multi_frag_flag) {
+ /* copy IV into temporary kernel source buffer */
+ memcpy(desc->user.aligned_src, &op->initial_vector[0], iv_len);
+
+ /* copy input data to temporary kernel source buffer */
+ memcpy((uint8_t *) (desc->user.aligned_src + iv_len),
+ (uint8_t *) (unsigned long)op->source_buf, SEC_MAX_FRAG_LEN);
+
+ desc->next_src_len = op->source_buf_size - SEC_MAX_FRAG_LEN;
+ memcpy((uint8_t *) (desc->next_src_buf),
+ (uint8_t *) (unsigned long)(op->source_buf + SEC_MAX_FRAG_LEN),
+ desc->next_src_len);
+
+ op->source_buf_size = SEC_MAX_FRAG_LEN;
+ op->source_buf_size += iv_len;
+ } else {
+ /* copy IV into temporary kernel source buffer */
+ memcpy(desc->user.aligned_src, &op->initial_vector[0], iv_len);
+
+ /* copy input data to temporary kernel source buffer */
+ memcpy((uint8_t *) (desc->user.aligned_src + iv_len),
+ (uint8_t *) (unsigned long)op->source_buf, op->source_buf_size);
+ op->source_buf_size += iv_len;
+ }
+ }
+
+ /* Set source to new kernel space */
+ op->source_buf = (uint64_t) (unsigned long)desc->user.aligned_src;
+
+ /*
+ * Build new dest buffer, for Cipher output only
+ */
+ if (op->cipher_type == XLR_SEC_CIPHER_TYPE_NONE) {
+ /*
+ * Digest Engine *NEEDS* this, otherwise it will write at
+ * 0[x]
+ */
+ op->dest_buf = (uint64_t) (unsigned long)desc->user.aligned_src;
+ } else {
+ /* DEBUG -dpk */
+ XLR_SEC_CMD_DIAG("dest_buf_size = %d \n", op->dest_buf_size);
+ size = op->dest_buf_size + iv_len;
+
+ /*
+ * make sure that there are enough bytes for aes based
+ * stream ciphers
+ */
+ if (op->cipher_mode == XLR_SEC_CIPHER_MODE_F8 ||
+ op->cipher_mode == XLR_SEC_CIPHER_MODE_CTR)
+ size += XLR_SEC_AES_BLOCK_SIZE - 1;
+ op->dest_buf = (uint64_t) (unsigned long)desc->user.aligned_dest;
+ }
+
+ ret_val = xlr_sec_cipher_hash_command(op, desc, ses->multi_frag_flag);
+ return (ret_val);
+
+}
+
+static int
+xlr_sec_cipher_hash_command(xlr_sec_io_pt op, symkey_desc_pt desc,
+ uint8_t multi_frag_flag)
+{
+ xlr_sec_error_t err;
+ uint32_t cfg_vector;
+ unsigned int setup_flags = 0;
+
+ err = XLR_SEC_ERR_NONE;
+ cfg_vector = 0;
+
+ if ((op->digest_type == XLR_SEC_DIGEST_TYPE_NONE) &&
+ (op->cipher_type != XLR_SEC_CIPHER_TYPE_ARC4) &&
+ (op->cipher_mode != XLR_SEC_CIPHER_MODE_F8) &&
+ (op->cipher_type != XLR_SEC_CIPHER_TYPE_KASUMI_F8) &&
+ (op->source_buf_size & 0x7)) {
+ printf("Invalid Cipher Block Size, data len=%d\n",
+ op->source_buf_size);
+ return (-EINVAL);
+ }
+ do {
+
+ if ((op->cipher_type == XLR_SEC_CIPHER_TYPE_3DES) &&
+ (op->cipher_op == XLR_SEC_CIPHER_OP_DECRYPT))
+ setup_flags = XLR_SEC_SETUP_OP_FLIP_3DES_KEY;
+
+ err = xlr_sec_setup_descriptor(op,
+ setup_flags,
+ desc, &cfg_vector);
+ if (err != XLR_SEC_ERR_NONE)
+ break;
+
+ err = xlr_sec_setup_packet(op,
+ desc,
+ op->digest_type != XLR_SEC_DIGEST_TYPE_NONE ?
+ XLR_SEC_SETUP_OP_CIPHER_HMAC : 0,
+ &desc->data,
+ &desc->pkt_desc[0],
+ &desc->ctl_desc,
+ cfg_vector,
+ &desc->pkt_desc[1],
+ multi_frag_flag);
+ if (err != XLR_SEC_ERR_NONE)
+ break;
+ } while (0);
+ if (err != XLR_SEC_ERR_NONE) {
+ return (EINVAL);
+ }
+ err = xlr_sec_submit_message(desc, cfg_vector);
+ return err;
+}
+
+static xlr_sec_error_t
+xlr_sec_setup_descriptor(xlr_sec_io_pt op,
+ unsigned int flags,
+ symkey_desc_pt desc,
+ uint32_t * cfg_vector)
+{
+ xlr_sec_error_t err;
+
+ XLR_SEC_CMD_DIAG("xlr_sec_setup_descriptor: ENTER\n");
+
+ if ((err = xlr_sec_setup_cipher(op, &desc->ctl_desc, cfg_vector)) != XLR_SEC_ERR_NONE) {
+ XLR_SEC_CMD_DIAG("xlr_sec_setup_descriptor: xlr_sec_setup_cipher done err %d\n",
+ (int)err);
+ return err;
+ }
+ if (op->digest_type != XLR_SEC_DIGEST_TYPE_NONE) {
+ if ((err = xlr_sec_setup_digest(op, &desc->ctl_desc, cfg_vector)) != XLR_SEC_ERR_NONE) {
+ XLR_SEC_CMD_DIAG("xlr_sec_setup_descriptor: xlr_sec_setup_digest done err %d\n",
+ (int)err);
+ return err;
+ }
+ }
+ if ((err = xlr_sec_setup_cksum(op, &desc->ctl_desc)) != XLR_SEC_ERR_NONE) {
+ XLR_SEC_CMD_DIAG("xlr_sec_setup_descriptor: xlr_sec_setup_cksum done err %d\n",
+ (int)err);
+ return err;
+ }
+ if ((err = xlr_sec_control_setup(op,
+ flags,
+ &desc->control,
+ &desc->ctl_desc,
+ &desc->user,
+ *cfg_vector)) != XLR_SEC_ERR_NONE) {
+ XLR_SEC_CMD_DIAG("xlr_sec_setup_descriptor: xlr_sec_control_setup done err %d\n",
+ (int)err);
+ return err;
+ }
+ XLR_SEC_CMD_DIAG("xlr_sec_setup_descriptor: DONE\n");
+ return err;
+}
+
+
+
+static
+xlr_sec_error_t
+xlr_sec_setup_packet(xlr_sec_io_pt op,
+ symkey_desc_pt desc,
+ unsigned int flags,
+ uint64_t * data,
+ PacketDescriptor_pt pkt_desc,
+ ControlDescriptor_pt ctl_desc,
+ uint32_t vector,
+ PacketDescriptor_pt next_pkt_desc,
+ uint8_t multi_frag_flag)
+{
+ uint32_t len, next_len = 0, len_dwords, last_u64_bytes;
+ uint64_t addr;
+ uint64_t seg_addr, next_seg_addr = 0;
+ uint64_t byte_offset, global_offset;
+ uint32_t cipher_offset_dwords;
+
+ XLR_SEC_CMD_DIAG("xlr_sec_setup_packet: ENTER vector = %04x\n", vector);
+
+ /* physical address of the source buffer */
+ addr = (uint64_t) vtophys((void *)(unsigned long)op->source_buf);
+ /* cache-aligned base of the source buffer */
+ seg_addr = (addr & ~(SMP_CACHE_BYTES - 1));
+ /* offset in bytes to the source buffer start from the segment base */
+ byte_offset = addr - seg_addr;
+ /* global offset: 0-7 bytes */
+ global_offset = byte_offset & 0x7;
+
+
+ /*
+ * op->source_buf_size is expected to be the Nb double words to
+ * stream in (Including Segment address->CP/IV/Auth/CkSum offsets)
+ */
+
+ /*
+ * adjusted length of the whole thing, accounting for the added
+ * head, sans global_offset (per Paul S.)
+ */
+
+ len = op->source_buf_size + byte_offset - global_offset;
+ if (multi_frag_flag) {
+ next_seg_addr = (uint64_t)vtophys((void *)(uintptr_t)desc->next_src_buf);
+ next_seg_addr = (next_seg_addr & ~(SMP_CACHE_BYTES - 1));
+ next_len = desc->next_src_len;
+ }
+ /* length of the whole thing in dwords */
+ len_dwords = NUM_CHUNKS(len, 3);
+ /* number of bytes in the last chunk (len % 8) */
+ last_u64_bytes = len & 0x07;
+
+ if (op->cipher_offset & 0x7) {
+ printf("** cipher_offset(%d) fails 64-bit word alignment **",
+ op->cipher_offset);
+
+ return XLR_SEC_ERR_CIPHER_MODE; /* ! fix ! */
+ }
+ /*
+ * global_offset is only three bits, so work the number of the whole
+ * 8-byte words into the global offset. both offset and
+ * cipher_offset are byte counts
+ */
+ cipher_offset_dwords = (op->iv_offset + byte_offset) >> 3;
+
+ if (op->cipher_mode == XLR_SEC_CIPHER_MODE_F8 ||
+ op->cipher_mode == XLR_SEC_CIPHER_MODE_CTR) {
+ if (multi_frag_flag) {
+ int nlhmac = ((op->source_buf_size + global_offset + 7 - op->cipher_offset) >> 3) & 1;
+
+ pkt_desc->srcLengthIVOffUseIVNext =
+ FIELD_VALUE(PKT_DSC_HASHBYTES, len & 7) |
+ FIELD_VALUE(PKT_DSC_IVOFF, cipher_offset_dwords) |
+ FIELD_VALUE(PKT_DSC_PKTLEN, nlhmac + ((len + 7) >> 3)) |
+ FIELD_VALUE(PKT_DSC_NLHMAC, nlhmac) |
+ FIELD_VALUE(PKT_DSC_BREAK, 0) |
+ FIELD_VALUE(PKT_DSC_WAIT, 1) |
+ FIELD_VALUE(PKT_DSC_NEXT, 1) |
+ FIELD_VALUE(PKT_DSC_SEGADDR, seg_addr >> (PKT_DSC_SEGADDR_LSB)) |
+ FIELD_VALUE(PKT_DSC_SEGOFFSET, global_offset);
+ } else {
+ int nlhmac = ((op->source_buf_size + global_offset + 7 - op->cipher_offset) >> 3) & 1;
+
+ pkt_desc->srcLengthIVOffUseIVNext =
+ FIELD_VALUE(PKT_DSC_HASHBYTES, len & 7) |
+ FIELD_VALUE(PKT_DSC_IVOFF, cipher_offset_dwords) |
+ FIELD_VALUE(PKT_DSC_PKTLEN, nlhmac + ((len + 7) >> 3)) |
+ FIELD_VALUE(PKT_DSC_NLHMAC, nlhmac) |
+ FIELD_VALUE(PKT_DSC_BREAK, 0) |
+ FIELD_VALUE(PKT_DSC_WAIT, 0) |
+ FIELD_VALUE(PKT_DSC_SEGADDR, seg_addr >> (PKT_DSC_SEGADDR_LSB)) |
+ FIELD_VALUE(PKT_DSC_SEGOFFSET, global_offset);
+
+ }
+ } else {
+ if (multi_frag_flag) {
+ pkt_desc->srcLengthIVOffUseIVNext =
+ FIELD_VALUE(PKT_DSC_HASHBYTES, len & 7) |
+ FIELD_VALUE(PKT_DSC_IVOFF, cipher_offset_dwords) |
+ FIELD_VALUE(PKT_DSC_PKTLEN, (len + 7) >> 3) |
+ FIELD_VALUE(PKT_DSC_BREAK, 0) |
+ FIELD_VALUE(PKT_DSC_WAIT, 0) |
+ FIELD_VALUE(PKT_DSC_NEXT, 1) |
+ FIELD_VALUE(PKT_DSC_SEGADDR, seg_addr >> (PKT_DSC_SEGADDR_LSB)) |
+ FIELD_VALUE(PKT_DSC_SEGOFFSET, global_offset);
+
+
+ next_pkt_desc->srcLengthIVOffUseIVNext =
+ FIELD_VALUE(PKT_DSC_HASHBYTES, (next_len & 7)) |
+ FIELD_VALUE(PKT_DSC_IVOFF, 0) |
+ FIELD_VALUE(PKT_DSC_PKTLEN, (next_len + 7) >> 3) |
+ FIELD_VALUE(PKT_DSC_BREAK, 0) |
+ FIELD_VALUE(PKT_DSC_WAIT, 0) |
+ FIELD_VALUE(PKT_DSC_NEXT, 0) |
+ FIELD_VALUE(PKT_DSC_SEGADDR, next_seg_addr >> (PKT_DSC_SEGADDR_LSB)) |
+ FIELD_VALUE(PKT_DSC_SEGOFFSET, 0);
+
+
+ } else {
+ pkt_desc->srcLengthIVOffUseIVNext =
+ FIELD_VALUE(PKT_DSC_HASHBYTES, len & 7) |
+ FIELD_VALUE(PKT_DSC_IVOFF, cipher_offset_dwords) |
+ FIELD_VALUE(PKT_DSC_PKTLEN, (len + 7) >> 3) |
+ FIELD_VALUE(PKT_DSC_BREAK, 0) |
+ FIELD_VALUE(PKT_DSC_WAIT, 0) |
+ FIELD_VALUE(PKT_DSC_SEGADDR, seg_addr >> (PKT_DSC_SEGADDR_LSB)) |
+ FIELD_VALUE(PKT_DSC_SEGOFFSET, global_offset);
+
+
+ }
+ }
+
+ switch (op->pkt_hmac) {
+ case XLR_SEC_LOADHMACKEY_MODE_OLD:
+ CLEAR_SET_FIELD(pkt_desc->srcLengthIVOffUseIVNext,
+ PKT_DSC_LOADHMACKEY, PKT_DSC_LOADHMACKEY_OLD);
+ if (multi_frag_flag) {
+ CLEAR_SET_FIELD(next_pkt_desc->srcLengthIVOffUseIVNext,
+ PKT_DSC_LOADHMACKEY, PKT_DSC_LOADHMACKEY_OLD);
+
+ }
+ break;
+ case XLR_SEC_LOADHMACKEY_MODE_LOAD:
+ CLEAR_SET_FIELD(pkt_desc->srcLengthIVOffUseIVNext,
+ PKT_DSC_LOADHMACKEY, PKT_DSC_LOADHMACKEY_LOAD);
+ if (multi_frag_flag) {
+ CLEAR_SET_FIELD(next_pkt_desc->srcLengthIVOffUseIVNext,
+ PKT_DSC_LOADHMACKEY, PKT_DSC_LOADHMACKEY_LOAD);
+
+ }
+ break;
+ default:
+ if (vector & (XLR_SEC_VECTOR_HMAC | XLR_SEC_VECTOR_HMAC2 | XLR_SEC_VECTOR_GCM | XLR_SEC_VECTOR_F9)) {
+ XLR_SEC_CMD_DIAG("xlr_sec_setup_packet: ERR_LOADHMACKEY_MODE EXIT\n");
+ return XLR_SEC_ERR_LOADHMACKEY_MODE;
+ }
+ break;
+ }
+
+ switch (op->pkt_hash) {
+ case XLR_SEC_PADHASH_PADDED:
+ CLEAR_SET_FIELD(pkt_desc->srcLengthIVOffUseIVNext,
+ PKT_DSC_PADHASH, PKT_DSC_PADHASH_PADDED);
+ if (multi_frag_flag) {
+ CLEAR_SET_FIELD(next_pkt_desc->srcLengthIVOffUseIVNext,
+ PKT_DSC_PADHASH, PKT_DSC_PADHASH_PADDED);
+ }
+ break;
+ case XLR_SEC_PADHASH_PAD:
+ CLEAR_SET_FIELD(pkt_desc->srcLengthIVOffUseIVNext,
+ PKT_DSC_PADHASH, PKT_DSC_PADHASH_PAD);
+ if (multi_frag_flag) {
+ CLEAR_SET_FIELD(next_pkt_desc->srcLengthIVOffUseIVNext,
+ PKT_DSC_PADHASH, PKT_DSC_PADHASH_PAD);
+ }
+ break;
+ default:
+ if (vector & (XLR_SEC_VECTOR_MAC | XLR_SEC_VECTOR_HMAC | XLR_SEC_VECTOR_HMAC2)) {
+ XLR_SEC_CMD_DIAG("xlr_sec_setup_packet: ERR_PADHASH_MODE EXIT\n");
+ return XLR_SEC_ERR_PADHASH_MODE;
+ }
+ break;
+ }
+
+ switch (op->pkt_iv) {
+ case XLR_SEC_PKT_IV_OLD:
+ CLEAR_SET_FIELD(pkt_desc->srcLengthIVOffUseIVNext,
+ PKT_DSC_IV, PKT_DSC_IV_OLD);
+ if (multi_frag_flag) {
+ CLEAR_SET_FIELD(next_pkt_desc->srcLengthIVOffUseIVNext,
+ PKT_DSC_IV, PKT_DSC_IV_OLD);
+
+ }
+ break;
+ case XLR_SEC_PKT_IV_NEW:
+ CLEAR_SET_FIELD(pkt_desc->srcLengthIVOffUseIVNext,
+ PKT_DSC_IV, PKT_DSC_IV_NEW);
+ if (multi_frag_flag) {
+ CLEAR_SET_FIELD(next_pkt_desc->srcLengthIVOffUseIVNext,
+ PKT_DSC_IV, PKT_DSC_IV_NEW);
+
+ }
+ break;
+ default:
+ if (vector & XLR_SEC_VECTOR_CIPHER) {
+ XLR_SEC_CMD_DIAG("xlr_sec_setup_packet: ERR_PKT_IV_MODE EXIT\n");
+ return XLR_SEC_ERR_PKT_IV_MODE;
+ }
+ break;
+ }
+
+ XLR_SEC_CMD_DIAG("xlr_sec_setup_packet: src_buf=%llx phys_src_buf=%llx \n",
+ (unsigned long long)op->source_buf, (unsigned long long)addr);
+
+ XLR_SEC_CMD_DIAG("xlr_sec_setup_packet: seg_addr=%llx offset=%lld\n",
+ (unsigned long long)seg_addr, (unsigned long long)byte_offset);
+
+ XLR_SEC_CMD_DIAG("xlr_sec_setup_packet: global src offset: %d, iv_offset=%d\n",
+ cipher_offset_dwords, op->iv_offset);
+
+ XLR_SEC_CMD_DIAG("xlr_sec_setup_packet: src_buf_sz=%d PKT_LEN=%d\n",
+ op->source_buf_size, len_dwords);
+
+ /*
+ * same operation with the destination. cipher offset affects this,
+ * as well
+ */
+ if (multi_frag_flag) {
+ next_seg_addr = (uint64_t) vtophys((void *)(unsigned long)(desc->next_dest_buf));
+ next_seg_addr = (next_seg_addr & ~(SMP_CACHE_BYTES - 1));
+ }
+ addr = (uint64_t) vtophys((void *)(unsigned long)op->dest_buf);
+ seg_addr = (addr & ~(SMP_CACHE_BYTES - 1));
+ byte_offset = addr - seg_addr;
+ global_offset = byte_offset & 0x7;
+
+ XLR_SEC_CMD_DIAG("xlr_sec_setup_packet: dest_buf=%llx phys_dest_buf=%llx \n",
+ (unsigned long long)op->dest_buf, (unsigned long long)addr);
+
+ XLR_SEC_CMD_DIAG("xlr_sec_setup_packet: seg_addr=%llx offset=%lld\n",
+ (unsigned long long)seg_addr, (unsigned long long)byte_offset);
+
+ /*
+ * Dest Address = (Cipher Dest Address) + (Cipher Offset) + (Global
+ * Dest Data Offset)
+ *
+ * Cipher Dest Address - Cache-line (0xffffffffe0) Cipher Offset -
+ * Which (64-bit) Word in Cacheline (0-3) Global Dest Data Offset -
+ * Number of Bytes in (64-bit) Word before data
+ *
+ * It must be set for Digest-only Ops, since the Digest engine will
+ * write data to this address.
+ */
+ cipher_offset_dwords = (op->cipher_offset + byte_offset) >> 3;
+
+
+ pkt_desc->dstDataSettings =
+ /* SYM_OP, HASHSRC */
+ FIELD_VALUE(PKT_DSC_CPHROFF, cipher_offset_dwords) |
+ FIELD_VALUE(PKT_DSC_HASHOFF, (op->digest_offset + byte_offset) >> 3) |
+ FIELD_VALUE(PKT_DSC_CPHR_DST_ADDR, seg_addr) |
+ FIELD_VALUE(PKT_DSC_CPHR_DST_DWOFFSET, 0) |
+ FIELD_VALUE(PKT_DSC_CPHR_DST_OFFSET, global_offset);
+
+ if (multi_frag_flag) {
+ next_pkt_desc->dstDataSettings =
+ /* SYM_OP, HASHSRC */
+ FIELD_VALUE(PKT_DSC_CPHROFF, cipher_offset_dwords) |
+ FIELD_VALUE(PKT_DSC_HASHOFF, (op->digest_offset + byte_offset) >> 3) |
+ FIELD_VALUE(PKT_DSC_CPHR_DST_ADDR, next_seg_addr) |
+ FIELD_VALUE(PKT_DSC_CPHR_DST_DWOFFSET, 0) |
+ FIELD_VALUE(PKT_DSC_CPHR_DST_OFFSET, global_offset);
+
+ }
+ if (op->cipher_type == XLR_SEC_CIPHER_TYPE_ARC4)
+ pkt_desc->dstDataSettings |= FIELD_VALUE(PKT_DSC_ARC4BYTECOUNT, last_u64_bytes);
+
+ if (op->cipher_type != XLR_SEC_CIPHER_TYPE_NONE) {
+ switch (op->cipher_op) {
+ case XLR_SEC_CIPHER_OP_ENCRYPT:
+ CLEAR_SET_FIELD(pkt_desc->dstDataSettings,
+ PKT_DSC_SYM_OP, PKT_DSC_SYM_OP_ENCRYPT);
+ if (multi_frag_flag) {
+ CLEAR_SET_FIELD(next_pkt_desc->dstDataSettings,
+ PKT_DSC_SYM_OP, PKT_DSC_SYM_OP_ENCRYPT);
+
+ }
+ break;
+ case XLR_SEC_CIPHER_OP_DECRYPT:
+ CLEAR_SET_FIELD(pkt_desc->dstDataSettings,
+ PKT_DSC_SYM_OP, PKT_DSC_SYM_OP_DECRYPT);
+ if (multi_frag_flag) {
+ CLEAR_SET_FIELD(next_pkt_desc->dstDataSettings,
+ PKT_DSC_SYM_OP, PKT_DSC_SYM_OP_DECRYPT);
+
+ }
+ break;
+ default:
+ XLR_SEC_CMD_DIAG("xlr_sec_setup_packet: ERR_CIPHER_OP EXIT\n");
+ return XLR_SEC_ERR_CIPHER_OP;
+ }
+ }
+ if (flags & XLR_SEC_SETUP_OP_HMAC) {
+ switch (op->digest_src) {
+ case XLR_SEC_DIGEST_SRC_DMA:
+ CLEAR_SET_FIELD(pkt_desc->dstDataSettings,
+ PKT_DSC_HASHSRC, PKT_DSC_HASHSRC_DMA);
+ if (multi_frag_flag) {
+ CLEAR_SET_FIELD(next_pkt_desc->dstDataSettings,
+ PKT_DSC_HASHSRC, PKT_DSC_HASHSRC_DMA);
+
+ }
+ break;
+ case XLR_SEC_DIGEST_SRC_CPHR:
+ CLEAR_SET_FIELD(pkt_desc->dstDataSettings,
+ PKT_DSC_HASHSRC, PKT_DSC_HASHSRC_CIPHER);
+ if (multi_frag_flag) {
+ CLEAR_SET_FIELD(next_pkt_desc->dstDataSettings,
+ PKT_DSC_HASHSRC, PKT_DSC_HASHSRC_CIPHER);
+ }
+ break;
+ default:
+ XLR_SEC_CMD_DIAG("xlr_sec_setup_packet: ERR_DIGEST_SRC EXIT\n");
+ return XLR_SEC_ERR_DIGEST_SRC;
+ }
+ }
+ if (op->cksum_type != XLR_SEC_CKSUM_TYPE_NOP) {
+ switch (op->cksum_src) {
+ case XLR_SEC_CKSUM_SRC_DMA:
+ CLEAR_SET_FIELD(pkt_desc->dstDataSettings,
+ PKT_DSC_CKSUMSRC, PKT_DSC_CKSUMSRC_DMA);
+ if (multi_frag_flag) {
+ CLEAR_SET_FIELD(next_pkt_desc->dstDataSettings,
+ PKT_DSC_CKSUMSRC, PKT_DSC_CKSUMSRC_DMA);
+ }
+ break;
+ case XLR_SEC_CKSUM_SRC_CIPHER:
+ CLEAR_SET_FIELD(next_pkt_desc->dstDataSettings,
+ PKT_DSC_CKSUMSRC, PKT_DSC_CKSUMSRC_CIPHER);
+ if (multi_frag_flag) {
+ CLEAR_SET_FIELD(next_pkt_desc->dstDataSettings,
+ PKT_DSC_CKSUMSRC, PKT_DSC_CKSUMSRC_CIPHER);
+ }
+ break;
+ default:
+ XLR_SEC_CMD_DIAG("xlr_sec_setup_packet: ERR_CKSUM_SRC EXIT\n");
+ return XLR_SEC_ERR_CKSUM_SRC;
+ }
+ }
+ pkt_desc->ckSumDstNonceHiCFBMaskLLWMask =
+ FIELD_VALUE(PKT_DSC_HASH_BYTE_OFF, (op->digest_offset & 0x7)) |
+ FIELD_VALUE(PKT_DSC_PKTLEN_BYTES, 0) |
+ /* NONCE_HI, PKT_DSC_LASTWORD, CFB_MASK, CKSUM_DST_ADDR */
+ FIELD_VALUE(PKT_DSC_IV_OFF_HI, 0);
+
+ if (multi_frag_flag) {
+ next_pkt_desc->ckSumDstNonceHiCFBMaskLLWMask =
+ FIELD_VALUE(PKT_DSC_HASH_BYTE_OFF, (op->digest_offset & 0x7)) |
+ FIELD_VALUE(PKT_DSC_PKTLEN_BYTES, 0) |
+ /* NONCE_HI, PKT_DSC_LASTWORD, CFB_MASK, CKSUM_DST_ADDR */
+ FIELD_VALUE(PKT_DSC_IV_OFF_HI, 0);
+
+ }
+ switch (op->pkt_lastword) {
+ case XLR_SEC_LASTWORD_128:
+ CLEAR_SET_FIELD(pkt_desc->ckSumDstNonceHiCFBMaskLLWMask,
+ PKT_DSC_LASTWORD, PKT_DSC_LASTWORD_128);
+ if (multi_frag_flag) {
+ CLEAR_SET_FIELD(next_pkt_desc->ckSumDstNonceHiCFBMaskLLWMask,
+ PKT_DSC_LASTWORD, PKT_DSC_LASTWORD_128);
+
+ }
+ break;
+ case XLR_SEC_LASTWORD_96MASK:
+ CLEAR_SET_FIELD(pkt_desc->ckSumDstNonceHiCFBMaskLLWMask,
+ PKT_DSC_LASTWORD, PKT_DSC_LASTWORD_96MASK);
+ if (multi_frag_flag) {
+ CLEAR_SET_FIELD(next_pkt_desc->ckSumDstNonceHiCFBMaskLLWMask,
+ PKT_DSC_LASTWORD, PKT_DSC_LASTWORD_96MASK);
+ }
+ break;
+ case XLR_SEC_LASTWORD_64MASK:
+ CLEAR_SET_FIELD(pkt_desc->ckSumDstNonceHiCFBMaskLLWMask,
+ PKT_DSC_LASTWORD, PKT_DSC_LASTWORD_64MASK);
+ if (multi_frag_flag) {
+ CLEAR_SET_FIELD(next_pkt_desc->ckSumDstNonceHiCFBMaskLLWMask,
+ PKT_DSC_LASTWORD, PKT_DSC_LASTWORD_64MASK);
+ }
+ break;
+ case XLR_SEC_LASTWORD_32MASK:
+ CLEAR_SET_FIELD(pkt_desc->ckSumDstNonceHiCFBMaskLLWMask,
+ PKT_DSC_LASTWORD, PKT_DSC_LASTWORD_32MASK);
+ if (multi_frag_flag) {
+ CLEAR_SET_FIELD(next_pkt_desc->ckSumDstNonceHiCFBMaskLLWMask,
+ PKT_DSC_LASTWORD, PKT_DSC_LASTWORD_32MASK);
+ }
+ break;
+ default:
+ XLR_SEC_CMD_DIAG("xlr_sec_setup_packet: ERR_LASTWORD_MODE EXIT\n");
+ return XLR_SEC_ERR_LASTWORD_MODE;
+ }
+ CLEAR_SET_FIELD(pkt_desc->ckSumDstNonceHiCFBMaskLLWMask,
+ PKT_DSC_CFB_MASK, op->cfb_mask);
+ CLEAR_SET_FIELD(pkt_desc->ckSumDstNonceHiCFBMaskLLWMask,
+ PKT_DSC_NONCE_HI, htonl(op->nonce) >> 24);
+ CLEAR_SET_FIELD(pkt_desc->authDstNonceLow,
+ PKT_DSC_NONCE_LOW, htonl(op->nonce) & 0xffffff);
+
+ if (multi_frag_flag) {
+ CLEAR_SET_FIELD(next_pkt_desc->ckSumDstNonceHiCFBMaskLLWMask,
+ PKT_DSC_CFB_MASK, op->cfb_mask);
+ CLEAR_SET_FIELD(next_pkt_desc->ckSumDstNonceHiCFBMaskLLWMask,
+ PKT_DSC_NONCE_HI, htonl(op->nonce) >> 24);
+ CLEAR_SET_FIELD(next_pkt_desc->authDstNonceLow,
+ PKT_DSC_NONCE_LOW, htonl(op->nonce) & 0xffffff);
+
+
+ }
+ /* Auth Dest Address must be Cacheline aligned on input */
+ if (vector & (XLR_SEC_VECTOR_MAC | XLR_SEC_VECTOR_HMAC | XLR_SEC_VECTOR_HMAC2 | XLR_SEC_VECTOR_GCM | XLR_SEC_VECTOR_F9)) {
+ pkt_desc->authDstNonceLow |=
+ /* NONCE_LOW */
+ FIELD_VALUE(PKT_DSC_AUTH_DST_ADDR,
+ (uint64_t) vtophys((void *)(unsigned long)op->auth_dest)) |
+ FIELD_VALUE(PKT_DSC_CIPH_OFF_HI, 0);
+
+
+ if (multi_frag_flag) {
+ next_pkt_desc->authDstNonceLow |=
+ /* NONCE_LOW */
+ FIELD_VALUE(PKT_DSC_AUTH_DST_ADDR,
+ (uint64_t) vtophys((void *)(unsigned long)desc->next_auth_dest)) |
+ FIELD_VALUE(PKT_DSC_CIPH_OFF_HI, 0);
+
+
+ }
+ }
+ /* CkSum Dest Address must be Cacheline aligned on input */
+ if (op->cksum_type == XLR_SEC_CKSUM_TYPE_IP) {
+ CLEAR_SET_FIELD(pkt_desc->ckSumDstNonceHiCFBMaskLLWMask,
+ PKT_DSC_CKSUM_DST_ADDR,
+ (uint64_t) vtophys((void *)(unsigned long)op->cksum_dest));
+
+ if (multi_frag_flag) {
+ CLEAR_SET_FIELD(next_pkt_desc->ckSumDstNonceHiCFBMaskLLWMask,
+ PKT_DSC_CKSUM_DST_ADDR,
+ (uint64_t) vtophys((void *)(unsigned long)desc->next_cksum_dest));
+ }
+ }
+ /*
+ * XLR_SEC_CMD_DIAG (" xlr_sec_setup_packet(): pkt_desc=%llx
+ * phys_pkt_desc=%llx \n", (unsigned long long)pkt_desc, (unsigned
+ * long long)virt_to_phys(pkt_desc)); (unsigned long long)pkt_desc,
+ * (unsigned long long)vtophys(pkt_desc));
+ */
+ XLR_SEC_CMD_DIAG(" xlr_sec_setup_packet(): pkt_desc=%p phys_pkt_desc=%llx \n",
+ pkt_desc, (unsigned long long)vtophys(pkt_desc));
+
+ CLEAR_SET_FIELD(*data, MSG_CMD_DATA_ADDR, ((uint64_t) vtophys(pkt_desc)));
+ CLEAR_SET_FIELD(*data, MSG_CMD_DATA_CTL, SEC_EOP);
+ CLEAR_SET_FIELD(*data, MSG_CMD_DATA_LEN, MSG_CMD_DATA_LEN_LOAD);
+
+ XLR_SEC_CMD_DIAG("xlr_sec_setup_packet: DONE\n");
+
+#ifdef RMI_SEC_DEBUG
+ {
+ printf("data desc\n");
+ printf("srcLengthIVOffUseIVNext = 0x%llx\n", pkt_desc->srcLengthIVOffUseIVNext);
+ printf("dstDataSettings = 0x%llx\n", pkt_desc->dstDataSettings);
+ printf("authDstNonceLow = 0x%llx\n", pkt_desc->authDstNonceLow);
+ printf("ckSumDstNonceHiCFBMaskLLWMask = 0x%llx\n", pkt_desc->ckSumDstNonceHiCFBMaskLLWMask);
+ }
+
+ if (multi_frag_flag) {
+
+ printf("next data desc\n");
+ printf("srcLengthIVOffUseIVNext = 0x%llx\n", next_pkt_desc->srcLengthIVOffUseIVNext);
+ printf("dstDataSettings = 0x%llx\n", next_pkt_desc->dstDataSettings);
+ printf("authDstNonceLow = 0x%llx\n", next_pkt_desc->authDstNonceLow);
+ printf("ckSumDstNonceHiCFBMaskLLWMask = 0x%llx\n", next_pkt_desc->ckSumDstNonceHiCFBMaskLLWMask);
+ }
+#endif
+
+#ifdef SYMBOL
+ if (op->cipher_type == XLR_SEC_CIPHER_TYPE_ARC4) {
+ op->source_buf -= 0;
+ op->source_buf_size += 0;
+ op->dest_buf -= 0;
+ }
+#endif
+ return XLR_SEC_ERR_NONE;
+}
+
+
+static int
+identify_symkey_ctl_error(uint32_t code, xlr_sec_error_t err)
+{
+ int ret_val = EINVAL;
+
+ switch (code) {
+ case CTL_ERR_NONE:
+ XLR_SEC_CMD_DIAG("XLR_SEC_SEC: CTL Error: No Error\n");
+ ret_val = 0;
+ break;
+ case CTL_ERR_CIPHER_OP:
+ XLR_SEC_CMD_DIAG("XLR_SEC_SEC: CTL Error(CTL_ERR_CIPHER_OP) - Unknown Cipher Op \n");
+ break;
+ case CTL_ERR_MODE:
+ XLR_SEC_CMD_DIAG("XLR_SEC_SEC: CTL Error(CTL_ERR_MODE) - "
+ "Unknown or Not Allowed Mode \n");
+ break;
+ case CTL_ERR_CHKSUM_SRC:
+ XLR_SEC_CMD_DIAG("XLR_SEC_SEC: CTL Error(CTL_ERR_CHKSUM_SRC) - Unknown CkSum Src\n");
+ break;
+ case CTL_ERR_CFB_MASK:
+ XLR_SEC_CMD_DIAG("XLR_SEC_SEC: CTL Error(CTL_ERR_CFB_MASK) - Forbidden CFB Mask \n");
+ break;
+ case CTL_ERR_OP:
+ XLR_SEC_CMD_DIAG("XLR_SEC_SEC: CTL Error(CTL_ERR_OP) - Unknown Ctrl Op \n");
+ break;
+ case CTL_ERR_DATA_READ:
+ XLR_SEC_CMD_DIAG("XLR_SEC_SEC: CTL Error(CTL_ERR_DATA_READ) - Data Read Error\n");
+ break;
+ case CTL_ERR_DESC_CTRL:
+ XLR_SEC_CMD_DIAG("XLR_SEC_SEC: CTL Error(CTL_ERR_DESC_CTRL) - "
+ "Descriptor Ctrl Field Error \n");
+ break;
+ case CTL_ERR_UNDEF1:
+ case CTL_ERR_UNDEF2:
+ default:
+ XLR_SEC_CMD_DIAG("XLR_SEC_SEC: CTL Error: UNKNOWN CODE=%d \n", code);
+ break;
+ }
+ return ret_val;
+}
+
+static
+int
+identify_symkey_data_error(uint32_t code, xlr_sec_error_t err)
+{
+ int ret_val = -EINVAL;
+
+ switch (code) {
+ case DATA_ERR_NONE:
+ XLR_SEC_CMD_DIAG("XLR_SEC_SEC: DATA Error No Error\n");
+ ret_val = 0;
+ break;
+ case DATA_ERR_LEN_CIPHER:
+ XLR_SEC_CMD_DIAG("XLR_SEC_SEC: DATA Error() - Not Enough Data To Cipher\n");
+ break;
+ case DATA_ERR_IV_ADDR:
+ XLR_SEC_CMD_DIAG("XLR_SEC_SEC: DATA Error() - Illegal IV Loacation\n");
+ break;
+ case DATA_ERR_WD_LEN_AES:
+ XLR_SEC_CMD_DIAG("XLR_SEC_SEC: DATA Error() - Illegal Nb Words To AES\n");
+ break;
+ case DATA_ERR_BYTE_COUNT:
+ XLR_SEC_CMD_DIAG("XLR_SEC_SEC: DATA Error() - Illegal Pad And ByteCount Spec\n");
+ break;
+ case DATA_ERR_LEN_CKSUM:
+ XLR_SEC_CMD_DIAG("XLR_SEC_SEC: DATA Error() - Not Enough Data To CkSum\n");
+ break;
+ case DATA_ERR_OP:
+ XLR_SEC_CMD_DIAG("XLR_SEC_SEC: DATA Error() - Unknown Data Op \n");
+ break;
+ case DATA_ERR_READ:
+ XLR_SEC_CMD_DIAG("XLR_SEC_SEC: DATA Error() - Data Read Error \n");
+ break;
+ case DATA_ERR_WRITE:
+ XLR_SEC_CMD_DIAG("XLR_SEC_SEC: DATA Error() - Data Write Error \n");
+ break;
+ case DATA_ERR_UNDEF1:
+ default:
+ XLR_SEC_CMD_DIAG("XLR_SEC_SEC: DATA Error - UNKNOWN CODE=%d \n", code);
+ break;
+ }
+ return ret_val;
+}
+
+
+static int
+xlr_sec_submit_message(symkey_desc_pt desc, uint32_t cfg_vector)
+{
+ xlr_sec_error_t err;
+ uint32_t ctl_error, data_error;
+ int ret_val = 0;
+
+ XLR_SEC_CMD_DIAG("xlr_sec_submit_message: ENTER\n");
+ err = XLR_SEC_ERR_NONE;
+ XLR_SEC_CMD_DIAG_SYM_DESC(desc, cfg_vector);
+
+ do {
+ /* For now, send message and wait for response */
+ err = xlr_sec_submit_op(desc);
+
+ XLR_SEC_CMD_DIAG("xlr_sec_submit_message: err = %d \n", (uint32_t) err);
+
+ if (err != XLR_SEC_ERR_NONE) {
+ ret_val = (EINVAL);
+ break;
+ }
+ ctl_error = desc->ctl_result;
+ data_error = desc->data_result;
+
+ XLR_SEC_CMD_DIAG("xlr_sec_submit_message: ctl_error = %x data_error = %x\n",
+ ctl_error, data_error);
+
+ if ((ret_val = identify_symkey_ctl_error(ctl_error, err)) == 0)
+ ret_val = identify_symkey_data_error(data_error, err);
+
+ XLR_SEC_CMD_DIAG("xlr_sec_submit_message: identify error = %d \n", ret_val);
+
+ } while (0);
+
+ XLR_SEC_CMD_DIAG("xlr_sec_submit_message: DONE\n");
+ return (ret_val);
+}
+
+
+static
+xlr_sec_error_t
+xlr_sec_setup_cipher(xlr_sec_io_pt op,
+ ControlDescriptor_pt ctl_desc,
+ uint32_t * vector)
+{
+ uint32_t aes_flag = 0;
+ uint32_t cipher_vector = 0;
+
+ XLR_SEC_CMD_DIAG("xlr_sec_setup_cipher: ENTER vector = %04x\n", *vector);
+
+ switch (op->cipher_type) {
+ case XLR_SEC_CIPHER_TYPE_NONE:
+ SET_FIELD(ctl_desc->instruction, CTL_DSC_CPHR, CTL_DSC_CPHR_BYPASS);
+ XLR_SEC_CMD_DIAG("xlr_sec_setup_cipher: CIPHER_TYPE_NONE EXIT\n");
+ return XLR_SEC_ERR_NONE;
+ case XLR_SEC_CIPHER_TYPE_DES:
+ cipher_vector |= XLR_SEC_VECTOR_CIPHER_DES;
+ SET_FIELD(ctl_desc->instruction, CTL_DSC_CPHR, CTL_DSC_CPHR_DES);
+ break;
+ case XLR_SEC_CIPHER_TYPE_3DES:
+ cipher_vector |= XLR_SEC_VECTOR_CIPHER_3DES;
+ SET_FIELD(ctl_desc->instruction, CTL_DSC_CPHR, CTL_DSC_CPHR_3DES);
+ break;
+ case XLR_SEC_CIPHER_TYPE_AES128:
+ aes_flag = 1;
+ cipher_vector |= XLR_SEC_VECTOR_CIPHER_AES128;
+ SET_FIELD(ctl_desc->instruction, CTL_DSC_CPHR, CTL_DSC_CPHR_AES128);
+ break;
+ case XLR_SEC_CIPHER_TYPE_AES192:
+ aes_flag = 1;
+ cipher_vector |= XLR_SEC_VECTOR_CIPHER_AES192;
+ SET_FIELD(ctl_desc->instruction, CTL_DSC_CPHR, CTL_DSC_CPHR_AES192);
+ break;
+ case XLR_SEC_CIPHER_TYPE_AES256:
+ aes_flag = 1;
+ cipher_vector |= XLR_SEC_VECTOR_CIPHER_AES256;
+ SET_FIELD(ctl_desc->instruction, CTL_DSC_CPHR, CTL_DSC_CPHR_AES256);
+ break;
+ case XLR_SEC_CIPHER_TYPE_ARC4:
+ cipher_vector |= XLR_SEC_VECTOR_CIPHER_ARC4;
+ SET_FIELD(ctl_desc->instruction, CTL_DSC_CPHR, CTL_DSC_CPHR_ARC4);
+ SET_FIELD(ctl_desc->instruction, CTL_DSC_ARC4_KEYLEN,
+ op->rc4_key_len);
+ SET_FIELD(ctl_desc->instruction, CTL_DSC_ARC4_LOADSTATE,
+ op->rc4_loadstate);
+ SET_FIELD(ctl_desc->instruction, CTL_DSC_ARC4_SAVESTATE,
+ op->rc4_savestate);
+ if (op->rc4_loadstate || op->rc4_savestate)
+ cipher_vector |= XLR_SEC_VECTOR_STATE;
+ break;
+ case XLR_SEC_CIPHER_TYPE_KASUMI_F8:
+ aes_flag = 1;
+ cipher_vector |= XLR_SEC_VECTOR_CIPHER_KASUMI_F8;
+ SET_FIELD(ctl_desc->instruction, CTL_DSC_CPHR, CTL_DSC_CPHR_KASUMI_F8);
+ break;
+ default:
+ XLR_SEC_CMD_DIAG("xlr_sec_setup_cipher: ERR_CIPHER_TYPE EXIT\n");
+ return XLR_SEC_ERR_CIPHER_TYPE;
+ }
+
+ switch (op->cipher_mode) {
+ case XLR_SEC_CIPHER_MODE_ECB:
+ if (aes_flag == 1)
+ cipher_vector |= XLR_SEC_VECTOR_MODE_ECB_CBC_OFB;
+ else
+ cipher_vector |= XLR_SEC_VECTOR_MODE_ECB_CBC;
+ SET_FIELD(ctl_desc->instruction, CTL_DSC_MODE, CTL_DSC_MODE_ECB);
+ break;
+ case XLR_SEC_CIPHER_MODE_CBC:
+ if (aes_flag == 1)
+ cipher_vector |= XLR_SEC_VECTOR_MODE_ECB_CBC_OFB;
+ else
+ cipher_vector |= XLR_SEC_VECTOR_MODE_ECB_CBC;
+ SET_FIELD(ctl_desc->instruction, CTL_DSC_MODE, CTL_DSC_MODE_CBC);
+ break;
+ case XLR_SEC_CIPHER_MODE_OFB:
+ if (aes_flag == 0) {
+ XLR_SEC_CMD_DIAG("xlr_sec_setup_cipher: ERR_CIPHER_MODE EXIT\n");
+ return XLR_SEC_ERR_CIPHER_MODE;
+ }
+ cipher_vector |= XLR_SEC_VECTOR_MODE_ECB_CBC_OFB;
+ SET_FIELD(ctl_desc->instruction, CTL_DSC_MODE, CTL_DSC_MODE_OFB);
+ break;
+ case XLR_SEC_CIPHER_MODE_CTR:
+ if (aes_flag == 0) {
+ XLR_SEC_CMD_DIAG("xlr_sec_setup_cipher: ERR_CIPHER_MODE EXIT\n");
+ return XLR_SEC_ERR_CIPHER_MODE;
+ }
+ cipher_vector |= XLR_SEC_VECTOR_MODE_CTR_CFB;
+ SET_FIELD(ctl_desc->instruction, CTL_DSC_MODE, CTL_DSC_MODE_CTR);
+ break;
+ case XLR_SEC_CIPHER_MODE_CFB:
+ if (aes_flag == 0) {
+ XLR_SEC_CMD_DIAG("xlr_sec_setup_cipher: ERR_CIPHER_MODE EXIT\n");
+ return XLR_SEC_ERR_CIPHER_MODE;
+ }
+ cipher_vector |= XLR_SEC_VECTOR_MODE_CTR_CFB;
+ SET_FIELD(ctl_desc->instruction, CTL_DSC_MODE, CTL_DSC_MODE_CFB);
+ break;
+ case XLR_SEC_CIPHER_MODE_F8:
+ if (aes_flag == 0) {
+ XLR_SEC_CMD_DIAG("xlr_sec_setup_cipher: ERR_CIPHER_MODE EXIT\n");
+ return XLR_SEC_ERR_CIPHER_MODE;
+ }
+ cipher_vector |= XLR_SEC_VECTOR_MODE_F8;
+ SET_FIELD(ctl_desc->instruction, CTL_DSC_MODE, CTL_DSC_MODE_F8);
+ break;
+ default:
+ if (!(cipher_vector & (XLR_SEC_VECTOR_CIPHER_ARC4 | XLR_SEC_VECTOR_CIPHER_KASUMI_F8))) {
+ XLR_SEC_CMD_DIAG("xlr_sec_setup_cipher: ERR_CIPHER_MODE EXIT\n");
+ return XLR_SEC_ERR_CIPHER_MODE;
+ }
+ }
+
+ switch (op->cipher_init) {
+ case XLR_SEC_CIPHER_INIT_OK:
+ SET_FIELD(ctl_desc->instruction,
+ CTL_DSC_ICPHR, CTL_DSC_ICPHR_OKY);
+ break;
+
+ case XLR_SEC_CIPHER_INIT_NK:
+ SET_FIELD(ctl_desc->instruction,
+ CTL_DSC_ICPHR, CTL_DSC_ICPHR_NKY);
+ break;
+ default:
+ XLR_SEC_CMD_DIAG("xlr_sec_setup_cipher: ERR_CIPHER_INIT EXIT\n");
+ return XLR_SEC_ERR_CIPHER_INIT;
+ }
+
+ *vector |= cipher_vector;
+
+ XLR_SEC_CMD_DIAG("xlr_sec_setup_cipher: EXIT vector = %04x\n", *vector);
+
+ return XLR_SEC_ERR_NONE;
+}
+
+static
+xlr_sec_error_t
+xlr_sec_setup_digest(xlr_sec_io_pt op,
+ ControlDescriptor_pt ctl_desc,
+ uint32_t * vector)
+{
+ uint32_t hash_flag = 0;
+ uint32_t hmac_flag = 0;
+ uint32_t digest_vector = 0;
+
+ XLR_SEC_CMD_DIAG("xlr_sec_setup_digest: ENTER vector = %04x\n", *vector);
+
+ switch (op->digest_type) {
+ case XLR_SEC_DIGEST_TYPE_MD5:
+ digest_vector |= XLR_SEC_VECTOR_MAC;
+ SET_FIELD(ctl_desc->instruction, CTL_DSC_HASH, CTL_DSC_HASH_MD5);
+ break;
+ case XLR_SEC_DIGEST_TYPE_SHA1:
+ digest_vector |= XLR_SEC_VECTOR_MAC;
+ SET_FIELD(ctl_desc->instruction, CTL_DSC_HASH, CTL_DSC_HASH_SHA1);
+ break;
+ case XLR_SEC_DIGEST_TYPE_SHA256:
+ digest_vector |= XLR_SEC_VECTOR_MAC;
+ SET_FIELD(ctl_desc->instruction, CTL_DSC_HASH, CTL_DSC_HASH_SHA256);
+ break;
+ case XLR_SEC_DIGEST_TYPE_SHA384:
+ digest_vector |= XLR_SEC_VECTOR_MAC;
+ SET_FIELD(ctl_desc->instruction, CTL_DSC_HASHHI, CTL_DSC_HASH_SHA384 >> 2);
+ SET_FIELD(ctl_desc->instruction, CTL_DSC_HASH, CTL_DSC_HASH_SHA384);
+ break;
+ case XLR_SEC_DIGEST_TYPE_SHA512:
+ digest_vector |= XLR_SEC_VECTOR_MAC;
+ SET_FIELD(ctl_desc->instruction, CTL_DSC_HASHHI, CTL_DSC_HASH_SHA512 >> 2);
+ SET_FIELD(ctl_desc->instruction, CTL_DSC_HASH, CTL_DSC_HASH_SHA512);
+ break;
+ case XLR_SEC_DIGEST_TYPE_GCM:
+ hash_flag = 1;
+ digest_vector |= XLR_SEC_VECTOR_GCM;
+ SET_FIELD(ctl_desc->instruction, CTL_DSC_HASHHI, CTL_DSC_HASH_GCM >> 2);
+ SET_FIELD(ctl_desc->instruction, CTL_DSC_HASH, CTL_DSC_HASH_GCM);
+ break;
+ case XLR_SEC_DIGEST_TYPE_KASUMI_F9:
+ hash_flag = 1;
+ digest_vector |= XLR_SEC_VECTOR_F9;
+ SET_FIELD(ctl_desc->instruction, CTL_DSC_HASHHI, CTL_DSC_HASH_KASUMI_F9 >> 2);
+ SET_FIELD(ctl_desc->instruction, CTL_DSC_HASH, CTL_DSC_HASH_KASUMI_F9);
+ break;
+ case XLR_SEC_DIGEST_TYPE_HMAC_MD5:
+ hmac_flag = 1;
+ digest_vector |= XLR_SEC_VECTOR_HMAC;
+ SET_FIELD(ctl_desc->instruction, CTL_DSC_HASH, CTL_DSC_HASH_MD5);
+ break;
+ case XLR_SEC_DIGEST_TYPE_HMAC_SHA1:
+ hmac_flag = 1;
+ digest_vector |= XLR_SEC_VECTOR_HMAC;
+ SET_FIELD(ctl_desc->instruction, CTL_DSC_HASH, CTL_DSC_HASH_SHA1);
+ break;
+ case XLR_SEC_DIGEST_TYPE_HMAC_SHA256:
+ hmac_flag = 1;
+ digest_vector |= XLR_SEC_VECTOR_HMAC;
+ SET_FIELD(ctl_desc->instruction, CTL_DSC_HASH, CTL_DSC_HASH_SHA256);
+ break;
+ case XLR_SEC_DIGEST_TYPE_HMAC_SHA384:
+ hmac_flag = 1;
+ digest_vector |= XLR_SEC_VECTOR_HMAC2;
+ SET_FIELD(ctl_desc->instruction, CTL_DSC_HASHHI, CTL_DSC_HASH_SHA384 >> 2);
+ SET_FIELD(ctl_desc->instruction, CTL_DSC_HASH, CTL_DSC_HASH_SHA384);
+ break;
+ case XLR_SEC_DIGEST_TYPE_HMAC_SHA512:
+ hmac_flag = 1;
+ digest_vector |= XLR_SEC_VECTOR_HMAC2;
+ SET_FIELD(ctl_desc->instruction, CTL_DSC_HASHHI, CTL_DSC_HASH_SHA512 >> 2);
+ SET_FIELD(ctl_desc->instruction, CTL_DSC_HASH, CTL_DSC_HASH_SHA512);
+ break;
+ default:
+ return XLR_SEC_ERR_DIGEST_TYPE;
+ }
+
+ if (hmac_flag == 1) {
+ SET_FIELD(ctl_desc->instruction, CTL_DSC_HMAC, CTL_DSC_HMAC_ON);
+
+ }
+ if (hmac_flag || hash_flag) {
+ switch (op->digest_init) {
+ case XLR_SEC_DIGEST_INIT_OLDKEY:
+ SET_FIELD(ctl_desc->instruction, CTL_DSC_IHASH, CTL_DSC_IHASH_OLD);
+ break;
+ case XLR_SEC_DIGEST_INIT_NEWKEY:
+ SET_FIELD(ctl_desc->instruction, CTL_DSC_IHASH, CTL_DSC_IHASH_NEW);
+ break;
+ default:
+ return XLR_SEC_ERR_DIGEST_INIT;
+ }
+ } /* hmac_flag */
+ *vector |= digest_vector;
+
+ XLR_SEC_CMD_DIAG("xlr_sec_setup_digest: EXIT vector = %04x\n", *vector);
+ return XLR_SEC_ERR_NONE;
+}
+
+static
+xlr_sec_error_t
+xlr_sec_setup_cksum(xlr_sec_io_pt op,
+ ControlDescriptor_pt ctl_desc)
+{
+ switch (op->cksum_type) {
+ case XLR_SEC_CKSUM_TYPE_NOP:
+ SET_FIELD(ctl_desc->instruction, CTL_DSC_CKSUM, CTL_DSC_CKSUM_NOP);
+ return XLR_SEC_ERR_NONE;
+ case XLR_SEC_CKSUM_TYPE_IP:
+ SET_FIELD(ctl_desc->instruction, CTL_DSC_CKSUM, CTL_DSC_CKSUM_IP);
+ break;
+ default:
+ return XLR_SEC_ERR_CKSUM_TYPE;
+ }
+
+ return XLR_SEC_ERR_NONE;
+}
+
+
+static
+xlr_sec_error_t
+xlr_sec_control_setup(xlr_sec_io_pt op,
+ unsigned int flags,
+ uint64_t * control,
+ ControlDescriptor_pt ctl_desc,
+ xlr_sec_drv_user_t * user,
+ uint32_t vector)
+{
+ uint64_t *hmac_key = NULL;
+ uint64_t *cipher_key = NULL;
+ uint64_t *cipher_state = NULL;
+ uint32_t ctl_size = 0;
+ uint64_t ctl_addr = 0;
+ uint32_t cipher_keylen = 0;
+ uint32_t hmac_keylen = 0;
+ uint32_t ctl_len;
+
+#ifdef SYM_DEBUG
+ XLR_SEC_CMD_DIAG(" ENTER vector = %04x\n", vector);
+#endif
+
+ switch (vector) {
+ case XLR_SEC_VECTOR_MAC:
+ XLR_SEC_CMD_DIAG(" XLR_SEC_VECTOR_MAC \n");
+ ctl_size = sizeof(HMAC_t);
+ break;
+ case XLR_SEC_VECTOR_HMAC:
+ XLR_SEC_CMD_DIAG("XLR_SEC_VECTOR_HMAC \n");
+ hmac_key = &ctl_desc->cipherHashInfo.infoHMAC.hmacKey0;
+ hmac_keylen = sizeof(HMAC_t);
+ ctl_size = sizeof(HMAC_t);
+ break;
+ case XLR_SEC_VECTOR_CIPHER_ARC4:
+ XLR_SEC_CMD_DIAG("XLR_SEC_VECTOR_CIPHER_ARC4\n");
+ cipher_key = &ctl_desc->cipherHashInfo.infoARC4.cipherKey0;
+ cipher_keylen = op->rc4_key_len;
+ ctl_size = sizeof(ARC4_t);
+ break;
+ case XLR_SEC_VECTOR_CIPHER_ARC4__HMAC:
+ XLR_SEC_CMD_DIAG("XLR_SEC_VECTOR_CIPHER_ARC4__HMAC\n");
+ cipher_key = &ctl_desc->cipherHashInfo.infoARC4HMAC.cipherKey0;
+ hmac_key = &ctl_desc->cipherHashInfo.infoARC4HMAC.hmacKey0;
+ cipher_keylen = op->rc4_key_len;
+ hmac_keylen = sizeof(HMAC_t);
+ ctl_size = sizeof(ARC4HMAC_t);
+ break;
+ case XLR_SEC_VECTOR_CIPHER_ARC4__STATE:
+ XLR_SEC_CMD_DIAG("XLR_SEC_VECTOR_CIPHER_ARC4__STATE\n");
+ cipher_key = &ctl_desc->cipherHashInfo.infoARC4State.cipherKey0;
+ cipher_state =
+ &ctl_desc->cipherHashInfo.infoARC4State.Arc4SboxData0;
+ cipher_keylen = op->rc4_key_len;
+ ctl_size = sizeof(ARC4State_t);
+ break;
+ case XLR_SEC_VECTOR_CIPHER_ARC4__HMAC__STATE:
+ XLR_SEC_CMD_DIAG("XLR_SEC_VECTOR_CIPHER_ARC4__HMAC__STATE\n");
+ cipher_key = &ctl_desc->cipherHashInfo.infoARC4StateHMAC.cipherKey0;
+ cipher_state =
+ &ctl_desc->cipherHashInfo.infoARC4StateHMAC.Arc4SboxData0;
+ hmac_key = &ctl_desc->cipherHashInfo.infoARC4StateHMAC.hmacKey0;
+ cipher_keylen = op->rc4_key_len;
+ hmac_keylen = sizeof(HMAC_t);
+ ctl_size = sizeof(ARC4StateHMAC_t);
+ break;
+ case XLR_SEC_VECTOR_CIPHER_KASUMI_F8:
+ XLR_SEC_CMD_DIAG("XLR_SEC_VECTOR_CIPHER_KASUMI_F8\n");
+ cipher_key = &ctl_desc->cipherHashInfo.infoKASUMIF8.cipherKey0;
+ cipher_keylen = XLR_SEC_KASUMI_F8_KEY_LENGTH;
+ ctl_size = sizeof(KASUMIF8_t);
+ break;
+ case XLR_SEC_VECTOR_CIPHER_KASUMI_F8__HMAC:
+ XLR_SEC_CMD_DIAG("XLR_SEC_VECTOR_CIPHER_KASUMI_F8__HMAC\n");
+ cipher_key = &ctl_desc->cipherHashInfo.infoKASUMIF8HMAC.cipherKey0;
+ cipher_keylen = XLR_SEC_KASUMI_F8_KEY_LENGTH;
+ hmac_key = &ctl_desc->cipherHashInfo.infoKASUMIF8HMAC.hmacKey0;
+ hmac_keylen = sizeof(HMAC_t);
+ ctl_size = sizeof(KASUMIF8HMAC_t);
+ break;
+ case XLR_SEC_VECTOR_CIPHER_KASUMI_F8__HMAC2:
+ XLR_SEC_CMD_DIAG("XLR_SEC_VECTOR_CIPHER_KASUMI_F8__HMAC2\n");
+ cipher_key = &ctl_desc->cipherHashInfo.infoKASUMIF8HMAC2.cipherKey0;
+ cipher_keylen = XLR_SEC_KASUMI_F8_KEY_LENGTH;
+ hmac_key = &ctl_desc->cipherHashInfo.infoKASUMIF8HMAC2.hmacKey0;
+ hmac_keylen = sizeof(HMAC2_t);
+ ctl_size = sizeof(KASUMIF8HMAC2_t);
+ break;
+ case XLR_SEC_VECTOR_CIPHER_KASUMI_F8__GCM:
+ XLR_SEC_CMD_DIAG("XLR_SEC_VECTOR_CIPHER_KASUMI_F8__GCM\n");
+ cipher_key = &ctl_desc->cipherHashInfo.infoKASUMIF8GCM.cipherKey0;
+ cipher_keylen = XLR_SEC_KASUMI_F8_KEY_LENGTH;
+ hmac_key = &ctl_desc->cipherHashInfo.infoKASUMIF8GCM.GCMH0;
+ hmac_keylen = sizeof(GCM_t);
+ ctl_size = sizeof(KASUMIF8GCM_t);
+ break;
+ case XLR_SEC_VECTOR_CIPHER_KASUMI_F8__F9:
+ XLR_SEC_CMD_DIAG("XLR_SEC_VECTOR_CIPHER_KASUMI_F8__F9\n");
+ cipher_key = &ctl_desc->cipherHashInfo.infoKASUMIF8F9.cipherKey0;
+ cipher_keylen = XLR_SEC_KASUMI_F8_KEY_LENGTH;
+ hmac_key = &ctl_desc->cipherHashInfo.infoKASUMIF8F9.authKey0;
+ hmac_keylen = sizeof(F9_t);
+ ctl_size = sizeof(KASUMIF8F9_t);
+ break;
+ case XLR_SEC_VECTOR__CIPHER_DES__HMAC__MODE_ECB_CBC:
+ XLR_SEC_CMD_DIAG(" XLR_SEC_VECTOR__CIPHER_DES__HMAC__MODE_ECB_CBC \n");
+ cipher_key = &ctl_desc->cipherHashInfo.infoDESHMAC.cipherKey0;
+ hmac_key = &ctl_desc->cipherHashInfo.infoDESHMAC.hmacKey0;
+ hmac_keylen = sizeof(HMAC_t);
+ cipher_keylen = XLR_SEC_DES_KEY_LENGTH;
+ ctl_size = sizeof(DESHMAC_t);
+ break;
+ case XLR_SEC_VECTOR__CIPHER_DES__MODE_ECB_CBC:
+ XLR_SEC_CMD_DIAG("XLR_SEC_VECTOR__CIPHER_DES__MODE_ECB_CBC \n");
+ cipher_key = &ctl_desc->cipherHashInfo.infoDES.cipherKey0;
+ cipher_keylen = XLR_SEC_DES_KEY_LENGTH;
+ ctl_size = sizeof(DES_t);
+ break;
+ case XLR_SEC_VECTOR__CIPHER_3DES__HMAC__MODE_ECB_CBC:
+ XLR_SEC_CMD_DIAG("XLR_SEC_VECTOR__CIPHER_3DES__HMAC__MODE_ECB_CBC \n");
+ cipher_key = &ctl_desc->cipherHashInfo.info3DESHMAC.cipherKey0;
+ hmac_key = &ctl_desc->cipherHashInfo.info3DESHMAC.hmacKey0;
+ cipher_keylen = XLR_SEC_3DES_KEY_LENGTH;
+ hmac_keylen = sizeof(HMAC_t);
+ ctl_size = sizeof(DES3HMAC_t);
+ break;
+ case XLR_SEC_VECTOR__CIPHER_3DES__MODE_ECB_CBC:
+ XLR_SEC_CMD_DIAG("XLR_SEC_VECTOR__CIPHER_3DES__MODE_ECB_CBC \n");
+ cipher_key = &ctl_desc->cipherHashInfo.info3DES.cipherKey0;
+ cipher_keylen = XLR_SEC_3DES_KEY_LENGTH;
+ ctl_size = sizeof(DES3_t);
+ break;
+ case XLR_SEC_VECTOR__CIPHER_AES128__HMAC__MODE_CTR_CFB:
+ XLR_SEC_CMD_DIAG("XLR_SEC_VECTOR__CIPHER_AES128__HMAC__MODE_CTR_CFB \n");
+ cipher_key = &ctl_desc->cipherHashInfo.infoAES128HMAC.cipherKey0;
+ hmac_key = &ctl_desc->cipherHashInfo.infoAES128HMAC.hmacKey0;
+ cipher_keylen = XLR_SEC_AES128_KEY_LENGTH;
+ hmac_keylen = sizeof(HMAC_t);
+ ctl_size = sizeof(AES128HMAC_t);
+ break;
+ case XLR_SEC_VECTOR__CIPHER_AES128__MODE_CTR_CFB:
+ XLR_SEC_CMD_DIAG("XLR_SEC_VECTOR__CIPHER_AES128__MODE_CTR_CFB \n");
+ cipher_key = &ctl_desc->cipherHashInfo.infoAES128.cipherKey0;
+ cipher_keylen = XLR_SEC_AES128_KEY_LENGTH;
+ ctl_size = sizeof(AES128_t);
+ break;
+ case XLR_SEC_VECTOR__CIPHER_AES128__HMAC__MODE_ECB_CBC_OFB:
+ XLR_SEC_CMD_DIAG(" XLR_SEC_VECTOR__CIPHER_AES128__HMAC__MODE_ECB_CBC_OFB \n");
+ cipher_key = &ctl_desc->cipherHashInfo.infoAES128HMAC.cipherKey0;
+ hmac_key = &ctl_desc->cipherHashInfo.infoAES128HMAC.hmacKey0;
+ cipher_keylen = XLR_SEC_AES128_KEY_LENGTH;
+ hmac_keylen = sizeof(HMAC_t);
+ ctl_size = sizeof(AES128HMAC_t);
+ break;
+ case XLR_SEC_VECTOR__CIPHER_AES128__MODE_ECB_CBC_OFB:
+ XLR_SEC_CMD_DIAG("XLR_SEC_VECTOR__CIPHER_AES128__MODE_ECB_CBC_OFB \n");
+ cipher_key = &ctl_desc->cipherHashInfo.infoAES128.cipherKey0;
+ cipher_keylen = XLR_SEC_AES128_KEY_LENGTH;
+ ctl_size = sizeof(AES128_t);
+ break;
+ case XLR_SEC_VECTOR__CIPHER_AES128__HMAC__MODE_F8:
+ XLR_SEC_CMD_DIAG("XLR_SEC_VECTOR__CIPHER_AES128__HMAC__MODE_F8 \n");
+ cipher_key = &ctl_desc->cipherHashInfo.infoAES128F8HMAC.cipherKey0;
+ hmac_key = &ctl_desc->cipherHashInfo.infoAES128F8HMAC.hmacKey0;
+ cipher_keylen = XLR_SEC_AES128F8_KEY_LENGTH;
+ hmac_keylen = sizeof(HMAC_t);
+ ctl_size = sizeof(AES128F8HMAC_t);
+ break;
+ case XLR_SEC_VECTOR__CIPHER_AES128__MODE_F8:
+ XLR_SEC_CMD_DIAG("XLR_SEC_VECTOR__CIPHER_AES128__MODE_F8 \n");
+ cipher_key = &ctl_desc->cipherHashInfo.infoAES128F8.cipherKey0;
+ cipher_keylen = XLR_SEC_AES128F8_KEY_LENGTH;
+ ctl_size = sizeof(AES128F8_t);
+ break;
+ case XLR_SEC_VECTOR__CIPHER_AES192__HMAC__MODE_CTR_CFB:
+ XLR_SEC_CMD_DIAG("XLR_SEC_VECTOR__CIPHER_AES192__HMAC__MODE_CTR_CFB \n");
+ cipher_key = &ctl_desc->cipherHashInfo.infoAES192HMAC.cipherKey0;
+ hmac_key = &ctl_desc->cipherHashInfo.infoAES192HMAC.hmacKey0;
+ cipher_keylen = XLR_SEC_AES192_KEY_LENGTH;
+ hmac_keylen = sizeof(HMAC_t);
+ ctl_size = sizeof(AES192HMAC_t);
+ break;
+ case XLR_SEC_VECTOR__CIPHER_AES192__MODE_CTR_CFB:
+ XLR_SEC_CMD_DIAG("XLR_SEC_VECTOR__CIPHER_AES192__MODE_CTR_CFB \n");
+ cipher_key = &ctl_desc->cipherHashInfo.infoAES192.cipherKey0;
+ cipher_keylen = XLR_SEC_AES192_KEY_LENGTH;
+ ctl_size = sizeof(AES192_t);
+ break;
+ case XLR_SEC_VECTOR__CIPHER_AES192__HMAC__MODE_ECB_CBC_OFB:
+ XLR_SEC_CMD_DIAG("XLR_SEC_VECTOR__CIPHER_AES192__HMAC__MODE_ECB_CBC_OFB \n");
+ cipher_key = &ctl_desc->cipherHashInfo.infoAES192HMAC.cipherKey0;
+ hmac_key = &ctl_desc->cipherHashInfo.infoAES192HMAC.hmacKey0;
+ cipher_keylen = XLR_SEC_AES192_KEY_LENGTH;
+ hmac_keylen = sizeof(HMAC_t);
+ ctl_size = sizeof(AES192HMAC_t);
+ break;
+ case XLR_SEC_VECTOR__CIPHER_AES192__MODE_ECB_CBC_OFB:
+ XLR_SEC_CMD_DIAG("XLR_SEC_VECTOR__CIPHER_AES192__MODE_ECB_CBC_OFB \n");
+ cipher_key = &ctl_desc->cipherHashInfo.infoAES192.cipherKey0;
+ cipher_keylen = XLR_SEC_AES192_KEY_LENGTH;
+ ctl_size = sizeof(AES192_t);
+ break;
+ case XLR_SEC_VECTOR__CIPHER_AES192__HMAC__MODE_F8:
+ XLR_SEC_CMD_DIAG("XLR_SEC_VECTOR__CIPHER_AES192__HMAC__MODE_F8 \n");
+ cipher_key = &ctl_desc->cipherHashInfo.infoAES192F8HMAC.cipherKey0;
+ hmac_key = &ctl_desc->cipherHashInfo.infoAES192F8HMAC.hmacKey0;
+ cipher_keylen = XLR_SEC_AES192F8_KEY_LENGTH;
+ hmac_keylen = sizeof(HMAC_t);
+ ctl_size = sizeof(AES192F8HMAC_t);
+ break;
+ case XLR_SEC_VECTOR__CIPHER_AES192__MODE_F8:
+ XLR_SEC_CMD_DIAG("XLR_SEC_VECTOR__CIPHER_AES192__MODE_F8 \n");
+ cipher_key = &ctl_desc->cipherHashInfo.infoAES192F8.cipherKey0;
+ cipher_keylen = XLR_SEC_AES192F8_KEY_LENGTH;
+ ctl_size = sizeof(AES192F8_t);
+ break;
+
+ case XLR_SEC_VECTOR__CIPHER_AES256__HMAC__MODE_CTR_CFB:
+ XLR_SEC_CMD_DIAG("XLR_SEC_VECTOR__CIPHER_AES256__HMAC__MODE_CTR_CFB \n");
+ cipher_key = &ctl_desc->cipherHashInfo.infoAES256HMAC.cipherKey0;
+ hmac_key = &ctl_desc->cipherHashInfo.infoAES256HMAC.hmacKey0;
+ cipher_keylen = XLR_SEC_AES256_KEY_LENGTH;
+ hmac_keylen = sizeof(HMAC_t);
+ ctl_size = sizeof(AES256HMAC_t);
+ break;
+ case XLR_SEC_VECTOR__CIPHER_AES256__MODE_CTR_CFB:
+ XLR_SEC_CMD_DIAG("XLR_SEC_VECTOR__CIPHER_AES256__MODE_CTR_CFB \n");
+ cipher_key = &ctl_desc->cipherHashInfo.infoAES256.cipherKey0;
+ cipher_keylen = XLR_SEC_AES256_KEY_LENGTH;
+ ctl_size = sizeof(AES256_t);
+ break;
+ case XLR_SEC_VECTOR__CIPHER_AES256__HMAC__MODE_ECB_CBC_OFB:
+ XLR_SEC_CMD_DIAG("XLR_SEC_VECTOR__CIPHER_AES256__HMAC__MODE_ECB_CBC_OFB \n");
+ cipher_key = &ctl_desc->cipherHashInfo.infoAES256HMAC.cipherKey0;
+ hmac_key = &ctl_desc->cipherHashInfo.infoAES256HMAC.hmacKey0;
+ cipher_keylen = XLR_SEC_AES256_KEY_LENGTH;
+ hmac_keylen = sizeof(HMAC_t);
+ ctl_size = sizeof(AES256HMAC_t);
+ break;
+ case XLR_SEC_VECTOR__CIPHER_AES256__MODE_ECB_CBC_OFB:
+ XLR_SEC_CMD_DIAG("XLR_SEC_VECTOR__CIPHER_AES256__MODE_ECB_CBC_OFB \n");
+ cipher_key = &ctl_desc->cipherHashInfo.infoAES256.cipherKey0;
+ cipher_keylen = XLR_SEC_AES256_KEY_LENGTH;
+ ctl_size = sizeof(AES256_t);
+ break;
+ case XLR_SEC_VECTOR__CIPHER_AES256__HMAC__MODE_F8:
+ XLR_SEC_CMD_DIAG("XLR_SEC_VECTOR__CIPHER_AES256__HMAC__MODE_F8 \n");
+ cipher_key = &ctl_desc->cipherHashInfo.infoAES256F8HMAC.cipherKey0;
+ hmac_key = &ctl_desc->cipherHashInfo.infoAES256F8HMAC.hmacKey0;
+ cipher_keylen = XLR_SEC_AES256F8_KEY_LENGTH;
+ hmac_keylen = sizeof(HMAC_t);
+ ctl_size = sizeof(AES256F8HMAC_t);
+ break;
+ case XLR_SEC_VECTOR__CIPHER_AES256__MODE_F8:
+ XLR_SEC_CMD_DIAG("XLR_SEC_VECTOR__CIPHER_AES256__MODE_F8 \n");
+ cipher_key = &ctl_desc->cipherHashInfo.infoAES256F8.cipherKey0;
+ cipher_keylen = XLR_SEC_AES256F8_KEY_LENGTH;
+ ctl_size = sizeof(AES256F8_t);
+ break;
+ case XLR_SEC_VECTOR_HMAC2:
+ XLR_SEC_CMD_DIAG("XLR_SEC_VECTOR_HMAC2 \n");
+ hmac_key = &ctl_desc->cipherHashInfo.infoHMAC2.hmacKey0;
+ hmac_keylen = sizeof(HMAC2_t);
+ ctl_size = sizeof(HMAC2_t);
+ break;
+ case XLR_SEC_VECTOR_CIPHER_ARC4__HMAC2:
+ XLR_SEC_CMD_DIAG("XLR_SEC_VECTOR_CIPHER_ARC4__HMAC2\n");
+ cipher_key = &ctl_desc->cipherHashInfo.infoARC4HMAC2.cipherKey0;
+ hmac_key = &ctl_desc->cipherHashInfo.infoARC4HMAC2.hmacKey0;
+ cipher_keylen = op->rc4_key_len;
+ hmac_keylen = sizeof(HMAC2_t);
+ ctl_size = sizeof(ARC4HMAC2_t);
+ break;
+ case XLR_SEC_VECTOR_CIPHER_ARC4__HMAC2__STATE:
+ XLR_SEC_CMD_DIAG("XLR_SEC_VECTOR_CIPHER_ARC4__HMAC2__STATE\n");
+ cipher_key = &ctl_desc->cipherHashInfo.infoARC4StateHMAC2.cipherKey0;
+ cipher_state =
+ &ctl_desc->cipherHashInfo.infoARC4StateHMAC2.Arc4SboxData0;
+ hmac_key = &ctl_desc->cipherHashInfo.infoARC4StateHMAC2.hmacKey0;
+ cipher_keylen = op->rc4_key_len;
+ hmac_keylen = sizeof(HMAC2_t);
+ ctl_size = sizeof(ARC4StateHMAC2_t);
+ break;
+ case XLR_SEC_VECTOR__CIPHER_DES__HMAC2__MODE_ECB_CBC:
+ XLR_SEC_CMD_DIAG(" XLR_SEC_VECTOR__CIPHER_DES__HMAC2__MODE_ECB_CBC \n");
+ cipher_key = &ctl_desc->cipherHashInfo.infoDESHMAC2.cipherKey0;
+ hmac_key = &ctl_desc->cipherHashInfo.infoDESHMAC2.hmacKey0;
+ hmac_keylen = sizeof(HMAC2_t);
+ cipher_keylen = XLR_SEC_DES_KEY_LENGTH;
+ ctl_size = sizeof(DESHMAC2_t);
+ break;
+ case XLR_SEC_VECTOR__CIPHER_3DES__HMAC2__MODE_ECB_CBC:
+ XLR_SEC_CMD_DIAG("XLR_SEC_VECTOR__CIPHER_3DES__HMAC2__MODE_ECB_CBC \n");
+ cipher_key = &ctl_desc->cipherHashInfo.info3DESHMAC2.cipherKey0;
+ hmac_key = &ctl_desc->cipherHashInfo.info3DESHMAC2.hmacKey0;
+ cipher_keylen = XLR_SEC_3DES_KEY_LENGTH;
+ hmac_keylen = sizeof(HMAC2_t);
+ ctl_size = sizeof(DES3HMAC2_t);
+ break;
+ case XLR_SEC_VECTOR__CIPHER_AES128__HMAC2__MODE_CTR_CFB:
+ XLR_SEC_CMD_DIAG("XLR_SEC_VECTOR__CIPHER_AES128__HMAC2__MODE_CTR_CFB \n");
+ cipher_key = &ctl_desc->cipherHashInfo.infoAES128HMAC2.cipherKey0;
+ hmac_key = &ctl_desc->cipherHashInfo.infoAES128HMAC2.hmacKey0;
+ cipher_keylen = XLR_SEC_AES128_KEY_LENGTH;
+ hmac_keylen = sizeof(HMAC2_t);
+ ctl_size = sizeof(AES128HMAC2_t);
+ break;
+ case XLR_SEC_VECTOR__CIPHER_AES128__HMAC2__MODE_ECB_CBC_OFB:
+ XLR_SEC_CMD_DIAG(" XLR_SEC_VECTOR__CIPHER_AES128__HMAC2__MODE_ECB_CBC_OFB \n");
+ cipher_key = &ctl_desc->cipherHashInfo.infoAES128HMAC2.cipherKey0;
+ hmac_key = &ctl_desc->cipherHashInfo.infoAES128HMAC2.hmacKey0;
+ cipher_keylen = XLR_SEC_AES128_KEY_LENGTH;
+ hmac_keylen = sizeof(HMAC2_t);
+ ctl_size = sizeof(AES128HMAC2_t);
+ break;
+ case XLR_SEC_VECTOR__CIPHER_AES128__HMAC2__MODE_F8:
+ XLR_SEC_CMD_DIAG("XLR_SEC_VECTOR__CIPHER_AES128__HMAC2__MODE_F8 \n");
+ cipher_key = &ctl_desc->cipherHashInfo.infoAES128F8HMAC2.cipherKey0;
+ hmac_key = &ctl_desc->cipherHashInfo.infoAES128F8HMAC2.hmacKey0;
+ cipher_keylen = XLR_SEC_AES128F8_KEY_LENGTH;
+ hmac_keylen = sizeof(HMAC2_t);
+ ctl_size = sizeof(AES128F8HMAC2_t);
+ break;
+ case XLR_SEC_VECTOR__CIPHER_AES192__HMAC2__MODE_CTR_CFB:
+ XLR_SEC_CMD_DIAG("XLR_SEC_VECTOR__CIPHER_AES192__HMAC2__MODE_CTR_CFB \n");
+ cipher_key = &ctl_desc->cipherHashInfo.infoAES192HMAC2.cipherKey0;
+ hmac_key = &ctl_desc->cipherHashInfo.infoAES192HMAC2.hmacKey0;
+ cipher_keylen = XLR_SEC_AES192_KEY_LENGTH;
+ hmac_keylen = sizeof(HMAC2_t);
+ ctl_size = sizeof(AES192HMAC2_t);
+ break;
+ case XLR_SEC_VECTOR__CIPHER_AES192__HMAC2__MODE_ECB_CBC_OFB:
+ XLR_SEC_CMD_DIAG("XLR_SEC_VECTOR__CIPHER_AES192__HMAC2__MODE_ECB_CBC_OFB \n");
+ cipher_key = &ctl_desc->cipherHashInfo.infoAES192HMAC2.cipherKey0;
+ hmac_key = &ctl_desc->cipherHashInfo.infoAES192HMAC2.hmacKey0;
+ cipher_keylen = XLR_SEC_AES192_KEY_LENGTH;
+ hmac_keylen = sizeof(HMAC2_t);
+ ctl_size = sizeof(AES192HMAC2_t);
+ break;
+ case XLR_SEC_VECTOR__CIPHER_AES192__HMAC2__MODE_F8:
+ XLR_SEC_CMD_DIAG("XLR_SEC_VECTOR__CIPHER_AES192__HMAC2__MODE_F8 \n");
+ cipher_key = &ctl_desc->cipherHashInfo.infoAES192F8HMAC2.cipherKey0;
+ hmac_key = &ctl_desc->cipherHashInfo.infoAES192F8HMAC2.hmacKey0;
+ cipher_keylen = XLR_SEC_AES192F8_KEY_LENGTH;
+ hmac_keylen = sizeof(HMAC2_t);
+ ctl_size = sizeof(AES192F8HMAC2_t);
+ break;
+ case XLR_SEC_VECTOR__CIPHER_AES256__HMAC2__MODE_CTR_CFB:
+ XLR_SEC_CMD_DIAG("XLR_SEC_VECTOR__CIPHER_AES256__HMAC2__MODE_CTR_CFB \n");
+ cipher_key = &ctl_desc->cipherHashInfo.infoAES256HMAC2.cipherKey0;
+ hmac_key = &ctl_desc->cipherHashInfo.infoAES256HMAC2.hmacKey0;
+ cipher_keylen = XLR_SEC_AES256_KEY_LENGTH;
+ hmac_keylen = sizeof(HMAC2_t);
+ ctl_size = sizeof(AES256HMAC2_t);
+ break;
+ case XLR_SEC_VECTOR__CIPHER_AES256__HMAC2__MODE_ECB_CBC_OFB:
+ XLR_SEC_CMD_DIAG("XLR_SEC_VECTOR__CIPHER_AES256__HMAC2__MODE_ECB_CBC_OFB \n");
+ cipher_key = &ctl_desc->cipherHashInfo.infoAES256HMAC2.cipherKey0;
+ hmac_key = &ctl_desc->cipherHashInfo.infoAES256HMAC2.hmacKey0;
+ cipher_keylen = XLR_SEC_AES256_KEY_LENGTH;
+ hmac_keylen = sizeof(HMAC2_t);
+ ctl_size = sizeof(AES256HMAC2_t);
+ break;
+ case XLR_SEC_VECTOR__CIPHER_AES256__HMAC2__MODE_F8:
+ XLR_SEC_CMD_DIAG("XLR_SEC_VECTOR__CIPHER_AES256__HMAC2__MODE_F8 \n");
+ cipher_key = &ctl_desc->cipherHashInfo.infoAES256F8HMAC2.cipherKey0;
+ hmac_key = &ctl_desc->cipherHashInfo.infoAES256F8HMAC2.hmacKey0;
+ cipher_keylen = XLR_SEC_AES256F8_KEY_LENGTH;
+ hmac_keylen = sizeof(HMAC2_t);
+ ctl_size = sizeof(AES256F8HMAC2_t);
+ break;
+ case XLR_SEC_VECTOR_GCM:
+ XLR_SEC_CMD_DIAG("XLR_SEC_VECTOR_GCM \n");
+ hmac_key = &ctl_desc->cipherHashInfo.infoGCM.GCMH0;
+ hmac_keylen = sizeof(GCM_t);
+ ctl_size = sizeof(GCM_t);
+ break;
+ case XLR_SEC_VECTOR_CIPHER_ARC4__GCM:
+ XLR_SEC_CMD_DIAG("XLR_SEC_VECTOR_CIPHER_ARC4__GCM\n");
+ cipher_key = &ctl_desc->cipherHashInfo.infoARC4GCM.cipherKey0;
+ hmac_key = &ctl_desc->cipherHashInfo.infoARC4GCM.GCMH0;
+ cipher_keylen = op->rc4_key_len;
+ hmac_keylen = sizeof(GCM_t);
+ ctl_size = sizeof(ARC4GCM_t);
+ break;
+ case XLR_SEC_VECTOR_CIPHER_ARC4__GCM__STATE:
+ XLR_SEC_CMD_DIAG("XLR_SEC_VECTOR_CIPHER_ARC4__GCM__STATE\n");
+ cipher_key = &ctl_desc->cipherHashInfo.infoARC4StateGCM.cipherKey0;
+ cipher_state =
+ &ctl_desc->cipherHashInfo.infoARC4StateGCM.Arc4SboxData0;
+ hmac_key = &ctl_desc->cipherHashInfo.infoARC4StateGCM.GCMH0;
+ cipher_keylen = op->rc4_key_len;
+ hmac_keylen = sizeof(GCM_t);
+ ctl_size = sizeof(ARC4StateGCM_t);
+ break;
+ case XLR_SEC_VECTOR__CIPHER_DES__GCM__MODE_ECB_CBC:
+ XLR_SEC_CMD_DIAG(" XLR_SEC_VECTOR__CIPHER_DES__GCM__MODE_ECB_CBC \n");
+ cipher_key = &ctl_desc->cipherHashInfo.infoDESGCM.cipherKey0;
+ hmac_key = &ctl_desc->cipherHashInfo.infoDESGCM.GCMH0;
+ hmac_keylen = sizeof(GCM_t);
+ cipher_keylen = XLR_SEC_DES_KEY_LENGTH;
+ ctl_size = sizeof(DESGCM_t);
+ break;
+ case XLR_SEC_VECTOR__CIPHER_3DES__GCM__MODE_ECB_CBC:
+ XLR_SEC_CMD_DIAG("XLR_SEC_VECTOR__CIPHER_3DES__GCM__MODE_ECB_CBC \n");
+ cipher_key = &ctl_desc->cipherHashInfo.info3DESGCM.cipherKey0;
+ hmac_key = &ctl_desc->cipherHashInfo.info3DESGCM.GCMH0;
+ cipher_keylen = XLR_SEC_3DES_KEY_LENGTH;
+ hmac_keylen = sizeof(GCM_t);
+ ctl_size = sizeof(DES3GCM_t);
+ break;
+ case XLR_SEC_VECTOR__CIPHER_AES128__GCM__MODE_CTR_CFB:
+ XLR_SEC_CMD_DIAG("XLR_SEC_VECTOR__CIPHER_AES128__GCM__MODE_CTR_CFB \n");
+ cipher_key = &ctl_desc->cipherHashInfo.infoAES128GCM.cipherKey0;
+ hmac_key = &ctl_desc->cipherHashInfo.infoAES128GCM.GCMH0;
+ cipher_keylen = XLR_SEC_AES128_KEY_LENGTH;
+ hmac_keylen = sizeof(GCM_t);
+ ctl_size = sizeof(AES128GCM_t);
+ break;
+ case XLR_SEC_VECTOR__CIPHER_AES128__GCM__MODE_ECB_CBC_OFB:
+ XLR_SEC_CMD_DIAG(" XLR_SEC_VECTOR__CIPHER_AES128__GCM__MODE_ECB_CBC_OFB \n");
+ cipher_key = &ctl_desc->cipherHashInfo.infoAES128GCM.cipherKey0;
+ hmac_key = &ctl_desc->cipherHashInfo.infoAES128GCM.GCMH0;
+ cipher_keylen = XLR_SEC_AES128_KEY_LENGTH;
+ hmac_keylen = sizeof(GCM_t);
+ ctl_size = sizeof(AES128GCM_t);
+ break;
+ case XLR_SEC_VECTOR__CIPHER_AES128__GCM__MODE_F8:
+ XLR_SEC_CMD_DIAG("XLR_SEC_VECTOR__CIPHER_AES128__GCM__MODE_F8 \n");
+ cipher_key = &ctl_desc->cipherHashInfo.infoAES128F8GCM.cipherKey0;
+ hmac_key = &ctl_desc->cipherHashInfo.infoAES128F8GCM.GCMH0;
+ cipher_keylen = XLR_SEC_AES128F8_KEY_LENGTH;
+ hmac_keylen = sizeof(GCM_t);
+ ctl_size = sizeof(AES128F8GCM_t);
+ break;
+ case XLR_SEC_VECTOR__CIPHER_AES192__GCM__MODE_CTR_CFB:
+ XLR_SEC_CMD_DIAG("XLR_SEC_VECTOR__CIPHER_AES192__GCM__MODE_CTR_CFB \n");
+ cipher_key = &ctl_desc->cipherHashInfo.infoAES192GCM.cipherKey0;
+ hmac_key = &ctl_desc->cipherHashInfo.infoAES192GCM.GCMH0;
+ cipher_keylen = XLR_SEC_AES192_KEY_LENGTH;
+ hmac_keylen = sizeof(GCM_t);
+ ctl_size = sizeof(AES192GCM_t);
+ break;
+ case XLR_SEC_VECTOR__CIPHER_AES192__GCM__MODE_ECB_CBC_OFB:
+ XLR_SEC_CMD_DIAG("XLR_SEC_VECTOR__CIPHER_AES192__GCM__MODE_ECB_CBC_OFB \n");
+ cipher_key = &ctl_desc->cipherHashInfo.infoAES192GCM.cipherKey0;
+ hmac_key = &ctl_desc->cipherHashInfo.infoAES192GCM.GCMH0;
+ cipher_keylen = XLR_SEC_AES192_KEY_LENGTH;
+ hmac_keylen = sizeof(GCM_t);
+ ctl_size = sizeof(AES192GCM_t);
+ break;
+ case XLR_SEC_VECTOR__CIPHER_AES192__GCM__MODE_F8:
+ XLR_SEC_CMD_DIAG("XLR_SEC_VECTOR__CIPHER_AES192__GCM__MODE_F8 \n");
+ cipher_key = &ctl_desc->cipherHashInfo.infoAES192F8GCM.cipherKey0;
+ hmac_key = &ctl_desc->cipherHashInfo.infoAES192F8GCM.GCMH0;
+ cipher_keylen = XLR_SEC_AES192F8_KEY_LENGTH;
+ hmac_keylen = sizeof(GCM_t);
+ ctl_size = sizeof(AES192F8GCM_t);
+ break;
+ case XLR_SEC_VECTOR__CIPHER_AES256__GCM__MODE_CTR_CFB:
+ XLR_SEC_CMD_DIAG("XLR_SEC_VECTOR__CIPHER_AES256__GCM__MODE_CTR_CFB \n");
+ cipher_key = &ctl_desc->cipherHashInfo.infoAES256GCM.cipherKey0;
+ hmac_key = &ctl_desc->cipherHashInfo.infoAES256GCM.GCMH0;
+ cipher_keylen = XLR_SEC_AES256_KEY_LENGTH;
+ hmac_keylen = sizeof(GCM_t);
+ ctl_size = sizeof(AES256GCM_t);
+ break;
+ case XLR_SEC_VECTOR__CIPHER_AES256__GCM__MODE_ECB_CBC_OFB:
+ XLR_SEC_CMD_DIAG("XLR_SEC_VECTOR__CIPHER_AES256__GCM__MODE_ECB_CBC_OFB \n");
+ cipher_key = &ctl_desc->cipherHashInfo.infoAES256GCM.cipherKey0;
+ hmac_key = &ctl_desc->cipherHashInfo.infoAES256GCM.GCMH0;
+ cipher_keylen = XLR_SEC_AES256_KEY_LENGTH;
+ hmac_keylen = sizeof(GCM_t);
+ ctl_size = sizeof(AES256GCM_t);
+ break;
+ case XLR_SEC_VECTOR__CIPHER_AES256__GCM__MODE_F8:
+ XLR_SEC_CMD_DIAG("XLR_SEC_VECTOR__CIPHER_AES256__GCM__MODE_F8 \n");
+ cipher_key = &ctl_desc->cipherHashInfo.infoAES256F8GCM.cipherKey0;
+ hmac_key = &ctl_desc->cipherHashInfo.infoAES256F8GCM.GCMH0;
+ cipher_keylen = XLR_SEC_AES256F8_KEY_LENGTH;
+ hmac_keylen = sizeof(GCM_t);
+ ctl_size = sizeof(AES256F8GCM_t);
+ break;
+ case XLR_SEC_VECTOR_F9:
+ XLR_SEC_CMD_DIAG("XLR_SEC_VECTOR_F9 \n");
+ hmac_key = &ctl_desc->cipherHashInfo.infoF9.authKey0;
+ hmac_keylen = sizeof(F9_t);
+ ctl_size = sizeof(F9_t);
+ break;
+ case XLR_SEC_VECTOR_CIPHER_ARC4__F9:
+ XLR_SEC_CMD_DIAG("XLR_SEC_VECTOR_CIPHER_ARC4__F9\n");
+ cipher_key = &ctl_desc->cipherHashInfo.infoARC4F9.cipherKey0;
+ hmac_key = &ctl_desc->cipherHashInfo.infoARC4F9.authKey0;
+ cipher_keylen = op->rc4_key_len;
+ hmac_keylen = sizeof(F9_t);
+ ctl_size = sizeof(ARC4F9_t);
+ break;
+ case XLR_SEC_VECTOR_CIPHER_ARC4__F9__STATE:
+ XLR_SEC_CMD_DIAG("XLR_SEC_VECTOR_CIPHER_ARC4__F9__STATE\n");
+ cipher_key = &ctl_desc->cipherHashInfo.infoARC4StateF9.cipherKey0;
+ cipher_state =
+ &ctl_desc->cipherHashInfo.infoARC4StateF9.Arc4SboxData0;
+ hmac_key = &ctl_desc->cipherHashInfo.infoARC4StateF9.authKey0;
+ cipher_keylen = op->rc4_key_len;
+ hmac_keylen = sizeof(F9_t);
+ ctl_size = sizeof(ARC4StateF9_t);
+ break;
+ case XLR_SEC_VECTOR__CIPHER_DES__F9__MODE_ECB_CBC:
+ XLR_SEC_CMD_DIAG(" XLR_SEC_VECTOR__CIPHER_DES__F9__MODE_ECB_CBC \n");
+ cipher_key = &ctl_desc->cipherHashInfo.infoDESF9.cipherKey0;
+ hmac_key = &ctl_desc->cipherHashInfo.infoDESF9.authKey0;
+ hmac_keylen = sizeof(F9_t);
+ cipher_keylen = XLR_SEC_DES_KEY_LENGTH;
+ ctl_size = sizeof(DESF9_t);
+ break;
+ case XLR_SEC_VECTOR__CIPHER_3DES__F9__MODE_ECB_CBC:
+ XLR_SEC_CMD_DIAG("XLR_SEC_VECTOR__CIPHER_3DES__F9__MODE_ECB_CBC \n");
+ cipher_key = &ctl_desc->cipherHashInfo.info3DESF9.cipherKey0;
+ hmac_key = &ctl_desc->cipherHashInfo.info3DESF9.authKey0;
+ cipher_keylen = XLR_SEC_3DES_KEY_LENGTH;
+ hmac_keylen = sizeof(F9_t);
+ ctl_size = sizeof(DES3F9_t);
+ break;
+ case XLR_SEC_VECTOR__CIPHER_AES128__F9__MODE_CTR_CFB:
+ XLR_SEC_CMD_DIAG("XLR_SEC_VECTOR__CIPHER_AES128__F9__MODE_CTR_CFB \n");
+ cipher_key = &ctl_desc->cipherHashInfo.infoAES128F9.cipherKey0;
+ hmac_key = &ctl_desc->cipherHashInfo.infoAES128F9.authKey0;
+ cipher_keylen = XLR_SEC_AES128_KEY_LENGTH;
+ hmac_keylen = sizeof(F9_t);
+ ctl_size = sizeof(AES128F9_t);
+ break;
+ case XLR_SEC_VECTOR__CIPHER_AES128__F9__MODE_ECB_CBC_OFB:
+ XLR_SEC_CMD_DIAG(" XLR_SEC_VECTOR__CIPHER_AES128__F9__MODE_ECB_CBC_OFB \n");
+ cipher_key = &ctl_desc->cipherHashInfo.infoAES128F9.cipherKey0;
+ hmac_key = &ctl_desc->cipherHashInfo.infoAES128F9.authKey0;
+ cipher_keylen = XLR_SEC_AES128_KEY_LENGTH;
+ hmac_keylen = sizeof(F9_t);
+ ctl_size = sizeof(AES128F9_t);
+ break;
+ case XLR_SEC_VECTOR__CIPHER_AES128__F9__MODE_F8:
+ XLR_SEC_CMD_DIAG("XLR_SEC_VECTOR__CIPHER_AES128__F9__MODE_F8 \n");
+ cipher_key = &ctl_desc->cipherHashInfo.infoAES128F8F9.cipherKey0;
+ hmac_key = &ctl_desc->cipherHashInfo.infoAES128F8F9.authKey0;
+ cipher_keylen = XLR_SEC_AES128F8_KEY_LENGTH;
+ hmac_keylen = sizeof(F9_t);
+ ctl_size = sizeof(AES128F8F9_t);
+ break;
+ case XLR_SEC_VECTOR__CIPHER_AES192__F9__MODE_CTR_CFB:
+ XLR_SEC_CMD_DIAG("XLR_SEC_VECTOR__CIPHER_AES192__F9__MODE_CTR_CFB \n");
+ cipher_key = &ctl_desc->cipherHashInfo.infoAES192F9.cipherKey0;
+ hmac_key = &ctl_desc->cipherHashInfo.infoAES192F9.authKey0;
+ cipher_keylen = XLR_SEC_AES192_KEY_LENGTH;
+ hmac_keylen = sizeof(F9_t);
+ ctl_size = sizeof(AES192F9_t);
+ break;
+ case XLR_SEC_VECTOR__CIPHER_AES192__F9__MODE_ECB_CBC_OFB:
+ XLR_SEC_CMD_DIAG("XLR_SEC_VECTOR__CIPHER_AES192__F9__MODE_ECB_CBC_OFB \n");
+ cipher_key = &ctl_desc->cipherHashInfo.infoAES192F9.cipherKey0;
+ hmac_key = &ctl_desc->cipherHashInfo.infoAES192F9.authKey0;
+ cipher_keylen = XLR_SEC_AES192_KEY_LENGTH;
+ hmac_keylen = sizeof(F9_t);
+ ctl_size = sizeof(AES192F9_t);
+ break;
+ case XLR_SEC_VECTOR__CIPHER_AES192__F9__MODE_F8:
+ XLR_SEC_CMD_DIAG("XLR_SEC_VECTOR__CIPHER_AES192__F9__MODE_F8 \n");
+ cipher_key = &ctl_desc->cipherHashInfo.infoAES192F8F9.cipherKey0;
+ hmac_key = &ctl_desc->cipherHashInfo.infoAES192F8F9.authKey0;
+ cipher_keylen = XLR_SEC_AES192F8_KEY_LENGTH;
+ hmac_keylen = sizeof(F9_t);
+ ctl_size = sizeof(AES192F8F9_t);
+ break;
+ case XLR_SEC_VECTOR__CIPHER_AES256__F9__MODE_CTR_CFB:
+ XLR_SEC_CMD_DIAG("XLR_SEC_VECTOR__CIPHER_AES256__F9__MODE_CTR_CFB \n");
+ cipher_key = &ctl_desc->cipherHashInfo.infoAES256F9.cipherKey0;
+ hmac_key = &ctl_desc->cipherHashInfo.infoAES256F9.authKey0;
+ cipher_keylen = XLR_SEC_AES256_KEY_LENGTH;
+ hmac_keylen = sizeof(F9_t);
+ ctl_size = sizeof(AES256F9_t);
+ break;
+ case XLR_SEC_VECTOR__CIPHER_AES256__F9__MODE_ECB_CBC_OFB:
+ XLR_SEC_CMD_DIAG("XLR_SEC_VECTOR__CIPHER_AES256__F9__MODE_ECB_CBC_OFB \n");
+ cipher_key = &ctl_desc->cipherHashInfo.infoAES256F9.cipherKey0;
+ hmac_key = &ctl_desc->cipherHashInfo.infoAES256F9.authKey0;
+ cipher_keylen = XLR_SEC_AES256_KEY_LENGTH;
+ hmac_keylen = sizeof(F9_t);
+ ctl_size = sizeof(AES256F9_t);
+ break;
+ case XLR_SEC_VECTOR__CIPHER_AES256__F9__MODE_F8:
+ XLR_SEC_CMD_DIAG("XLR_SEC_VECTOR__CIPHER_AES256__F9__MODE_F8 \n");
+ cipher_key = &ctl_desc->cipherHashInfo.infoAES256F8F9.cipherKey0;
+ hmac_key = &ctl_desc->cipherHashInfo.infoAES256F8F9.authKey0;
+ cipher_keylen = XLR_SEC_AES256F8_KEY_LENGTH;
+ hmac_keylen = sizeof(F9_t);
+ ctl_size = sizeof(AES256F8F9_t);
+ break;
+
+ default:
+ XLR_SEC_CMD_DIAG("default \n");
+ return XLR_SEC_ERR_CONTROL_VECTOR;
+ }
+
+ if ((cipher_key != NULL) && !(flags & XLR_SEC_SETUP_OP_PRESERVE_CIPHER_KEY))
+ memcpy(cipher_key, &op->crypt_key[0], cipher_keylen);
+
+ if ((hmac_key != NULL) && !(flags & XLR_SEC_SETUP_OP_PRESERVE_HMAC_KEY))
+ memcpy(hmac_key, &op->mac_key[0], hmac_keylen);
+ if (cipher_state) {
+ if (op->rc4_loadstate)
+ memcpy(cipher_state, (void *)(unsigned long)op->rc4_state,
+ XLR_SEC_MAX_RC4_STATE_SIZE);
+ if (op->rc4_savestate)
+ user->aligned_state = (char *)cipher_state;
+ }
+ if (flags & XLR_SEC_SETUP_OP_FLIP_3DES_KEY) {
+ uint64_t temp;
+
+ temp = ctl_desc->cipherHashInfo.info3DES.cipherKey0;
+ ctl_desc->cipherHashInfo.info3DES.cipherKey0 =
+ ctl_desc->cipherHashInfo.info3DES.cipherKey2;
+ ctl_desc->cipherHashInfo.info3DES.cipherKey2 = temp;
+ }
+ /*
+ * Control length is the number of control cachelines to be read so
+ * user needs to round up the control length to closest integer
+ * multiple of 32 bytes.
+ */
+ ctl_size += sizeof(ctl_desc->instruction);
+ ctl_len = NUM_CHUNKS(ctl_size, 5);
+ XLR_SEC_CMD_DIAG("ctl_size in bytes: %u, in cachelines: %u\n", ctl_size, ctl_len);
+ CLEAR_SET_FIELD(*control, MSG_CMD_CTL_LEN, ctl_len);
+
+ ctl_addr = (uint64_t) vtophys(ctl_desc);
+ CLEAR_SET_FIELD(*control, MSG_CMD_CTL_ADDR, ctl_addr);
+
+ XLR_SEC_CMD_DIAG(" xlr_sec_control_setup(): ctl_desc=%p ctl_addr=%llx \n",
+ ctl_desc, (unsigned long long)ctl_addr);
+
+ CLEAR_SET_FIELD(*control, MSG_CMD_CTL_CTL, SEC_SOP);
+
+ return XLR_SEC_ERR_NONE;
+}
+
+xlr_sec_error_t
+xlr_sec_submit_op(symkey_desc_pt desc)
+{
+ struct msgrng_msg send_msg;
+
+ int rsp_dest_id, cpu, hard_cpu, hard_thread;
+ int code, retries;
+ unsigned long msgrng_flags = 0;
+
+ /* threads (0-3) are orthogonal to buckets 0-3 */
+ cpu = xlr_cpu_id();
+
+ hard_cpu = cpu >> 2;
+ hard_thread = cpu & 0x3;/* thread id */
+ rsp_dest_id = (hard_cpu << 3) + hard_thread;
+
+ desc->op_ctl.cpu = hard_cpu;
+ desc->op_ctl.flags = 0; /* called from kernel thread */
+
+ XLR_SEC_CMD_DIAG("[%s]:%d: cpu=0x%x hard_cpu=0x%x hard_thrd=0x%x id=0x%x \n",
+ __FUNCTION__, __LINE__, cpu, hard_cpu, hard_thread, rsp_dest_id);
+
+ /*
+ * Set DestId in Message Control Word. This tells the Security
+ * Engine which bucket to send the reply to for this CPU
+ */
+ CLEAR_SET_FIELD(desc->control, MSG_CMD_CTL_ID, rsp_dest_id);
+ CLEAR_SET_FIELD(desc->data, MSG_CMD_CTL_ID, rsp_dest_id);
+
+ CLEAR_SET_FIELD(desc->control, MSG_CTL_OP_TYPE, MSG0_CTL_OP_ENGINE_SYMKEY);
+ CLEAR_SET_FIELD(desc->data, MSG_CTL_OP_TYPE, MSG1_CTL_OP_SYMKEY_PIPE0);
+
+ send_msg.msg0 = desc->control | (1ULL << 53);
+ send_msg.msg1 = desc->data | (1ULL << 53) | (1ULL << 52);
+ send_msg.msg2 = send_msg.msg3 = 0;
+
+ desc->op_ctl.flags = 1;
+ //in_interrupt(); /* ipsec softirq ? */
+
+ XLR_SEC_CMD_DIAG("[%s]: IN_IRQ=%d msg0=0x%llx msg1=0x%llx \n",
+ __FUNCTION__, desc->op_ctl.flags, send_msg.msg0, send_msg.msg1);
+
+ retries = 100;
+ while (retries--) {
+ msgrng_flags = msgrng_access_enable();
+ code = message_send(SEC_MSGRING_WORDSIZE, MSGRNG_CODE_SEC,
+ desc->op_ctl.stn_id, &send_msg);
+ msgrng_restore(msgrng_flags);
+ if (code == 0)
+ break;
+ }
+ return (XLR_SEC_ERR_NONE);
+}
+
+symkey_desc_pt
+xlr_sec_allocate_desc(void *session_ptr)
+{
+ uint64_t addr;
+ symkey_desc_pt aligned, new;
+
+ new = (symkey_desc_pt) malloc(sizeof(symkey_desc_t),
+ M_DEVBUF, M_NOWAIT | M_ZERO);
+
+ if (new == NULL)
+ return (NULL);
+
+ new->ses = session_ptr;
+
+ new->user.kern_src = new->user.aligned_src =
+ (uint8_t *) contigmalloc(256 * 1024 + 1024,
+ M_DEVBUF, M_NOWAIT | M_ZERO,
+ 0, 0xffffffff, XLR_CACHELINE_SIZE, 0);
+
+ if (new->user.kern_src == NULL) {
+ printf("ERROR - malloc failed for user.kern_src\n");
+ return NULL;
+ }
+ new->user.aligned_dest = new->user.kern_dest =
+ (uint8_t *) contigmalloc(257 * 1024,
+ M_DEVBUF, M_NOWAIT | M_ZERO,
+ 0, 0xffffffff, XLR_CACHELINE_SIZE, 0);
+
+ if (new->user.aligned_dest == NULL) {
+ printf("ERROR - malloc failed for user.aligned_dest\n");
+ return NULL;
+ }
+ new->next_src_buf = (uint8_t *) contigmalloc(256 * 1024 + 1024,
+ M_DEVBUF, M_NOWAIT | M_ZERO,
+ 0, 0xffffffff, XLR_CACHELINE_SIZE, 0);
+
+ if (new->next_src_buf == NULL) {
+ printf("ERROR - malloc failed for next_src_buf\n");
+ return NULL;
+ }
+ new->next_dest_buf =
+ (uint8_t *) contigmalloc(257 * 1024,
+ M_DEVBUF, M_NOWAIT | M_ZERO,
+ 0, 0xffffffff, XLR_CACHELINE_SIZE, 0);
+
+ if (new->next_dest_buf == NULL) {
+ printf("ERROR - malloc failed for next_dest_buf\n");
+ return NULL;
+ }
+ new->user.kern_auth = new->user.user_auth = NULL;
+ new->user.aligned_auth = new->user.user_auth = NULL;
+
+ /* find cacheline alignment */
+ aligned = new;
+ addr = (uint64_t) vtophys(new);
+
+ /* save for free */
+ aligned->alloc = new;
+
+ /* setup common control info */
+ aligned->op_ctl.phys_self = addr;
+ aligned->op_ctl.stn_id = MSGRNG_STNID_SEC0;
+ aligned->op_ctl.vaddr = (uintptr_t)aligned;
+
+ return (aligned);
+}
+
+
+static void
+xlr_sec_free_desc(symkey_desc_pt desc)
+{
+ if ((desc == NULL) || (desc->alloc == NULL)) {
+ printf("%s: NULL descriptor \n", __FUNCTION__);
+ return;
+ }
+ contigfree(desc, sizeof(symkey_desc_t), M_DEVBUF);
+ return;
+}
+
+void
+print_buf(char *desc, void *data, int len)
+{
+ uint8_t *dp;
+ int i;
+
+ DPRINT("%s: ", desc); /* newline done in for-loop */
+ dp = data;
+ for (i = 0; i < len; i++, dp++) {
+ if ((i % 16) == 0)
+ DPRINT("\n");
+ DPRINT(" %c%c",
+ nib2hex[(((*dp) & 0xf0) >> 4)],
+ nib2hex[((*dp) & 0x0f)]);
+ }
+ DPRINT("\n");
+}
+
+
+#ifdef XLR_SEC_CMD_DEBUG
+static void
+decode_symkey_desc(symkey_desc_pt desc, uint32_t cfg_vector)
+{
+
+ unsigned long long word;
+
+ /* uint8_t *info; */
+ /* int i; */
+
+ DPRINT("MSG - CTL: \n");
+ DPRINT("\t CTRL = %lld \n",
+ GET_FIELD(desc->control, MSG_CMD_CTL_CTL));
+ DPRINT("\t CTRL LEN = %lld \n",
+ GET_FIELD(desc->control, MSG_CMD_CTL_LEN));
+ DPRINT("\t CTRL ADDR = %llx \n\n",
+ GET_FIELD(desc->control, MSG_CMD_CTL_ADDR));
+
+ DPRINT("MSG - DATA: \n");
+ DPRINT("\t CTRL = %lld \n",
+ GET_FIELD(desc->data, MSG_CMD_DATA_CTL));
+ DPRINT("\t DATA LEN = %lld \n",
+ GET_FIELD(desc->data, MSG_CMD_DATA_LEN));
+ DPRINT("\t DATA ADDR = %llx \n\n",
+ GET_FIELD(desc->data, MSG_CMD_DATA_ADDR));
+
+ DPRINT("CONTROL DESCRIPTOR: \n");
+ word = desc->ctl_desc.instruction;
+ DPRINT("\tINSTRUCTION: %llx\n", word);
+ DPRINT("\t\tOVERRIDE CIPH = %lld \n", GET_FIELD(word, CTL_DSC_OVERRIDECIPHER));
+ DPRINT("\t\tARC4 WAIT = %lld \n", GET_FIELD(word, CTL_DSC_ARC4_WAIT4SAVE));
+ DPRINT("\t\tARC4 SAVE = %lld \n", GET_FIELD(word, CTL_DSC_ARC4_SAVESTATE));
+ DPRINT("\t\tARC4 LOAD = %lld \n", GET_FIELD(word, CTL_DSC_ARC4_LOADSTATE));
+ DPRINT("\t\tARC4 KEYLEN = %lld \n", GET_FIELD(word, CTL_DSC_ARC4_KEYLEN));
+ DPRINT("\t\tCIPHER = %lld \n", GET_FIELD(word, CTL_DSC_CPHR));
+ DPRINT("\t\tCIPHER MODE = %lld \n", GET_FIELD(word, CTL_DSC_MODE));
+ DPRINT("\t\tINIT CIPHER = %lld \n", GET_FIELD(word, CTL_DSC_ICPHR));
+ DPRINT("\t\tHMAC = %lld \n", GET_FIELD(word, CTL_DSC_HMAC));
+ DPRINT("\t\tHASH ALG = %lld \n", GET_FIELD(word, CTL_DSC_HASH) | (GET_FIELD(word, CTL_DSC_HASHHI) << 2));
+ DPRINT("\t\tINIT HASH = %lld \n", GET_FIELD(word, CTL_DSC_IHASH));
+ DPRINT("\t\tCHKSUM = %lld \n", GET_FIELD(word, CTL_DSC_CKSUM));
+ DPRINT("\tCIPHER HASH INFO: \n");
+#if 0
+ info = (uint8_t *) & desc->ctl_desc->cipherHashInfo;
+ for (i = 0; i < sizeof(CipherHashInfo_t); i++, info++) {
+ DPRINT(" %02x", *info);
+ if (i && (i % 16) == 0)
+ DPRINT("\n");
+ }
+ DPRINT("\n\n");
+#endif
+
+ switch (cfg_vector) {
+ case XLR_SEC_VECTOR_CIPHER_ARC4:
+ DPRINT("VECTOR: XLR_SEC_VECTOR_CIPHER_ARC4 \n");
+ print_buf("ARC4 Key",
+ &desc->ctl_desc.cipherHashInfo.infoARC4.cipherKey0,
+ GET_FIELD(word, CTL_DSC_ARC4_KEYLEN));
+ break;
+ case XLR_SEC_VECTOR_CIPHER_ARC4__HMAC:
+ DPRINT("VECTOR: XLR_SEC_VECTOR_CIPHER_ARC4__HMAC \n");
+ print_buf("ARC4 Key",
+ &desc->ctl_desc.cipherHashInfo.infoARC4HMAC.cipherKey0,
+ GET_FIELD(word, CTL_DSC_ARC4_KEYLEN));
+ print_buf("HMAC Key",
+ &desc->ctl_desc.cipherHashInfo.infoARC4HMAC.hmacKey0,
+ sizeof(HMAC_t));
+ break;
+ case XLR_SEC_VECTOR_CIPHER_ARC4__STATE:
+ DPRINT("VECTOR: XLR_SEC_VECTOR_CIPHER_ARC4__STATE \n");
+ print_buf("ARC4 Key",
+ &desc->ctl_desc.cipherHashInfo.infoARC4State.cipherKey0,
+ GET_FIELD(word, CTL_DSC_ARC4_KEYLEN));
+ break;
+ case XLR_SEC_VECTOR_CIPHER_ARC4__HMAC__STATE:
+ DPRINT("VECTOR: XLR_SEC_VECTOR_CIPHER_ARC4__HMAC__STATE \n");
+ print_buf("ARC4 Key",
+ &desc->ctl_desc.cipherHashInfo.infoARC4StateHMAC.cipherKey0,
+ GET_FIELD(word, CTL_DSC_ARC4_KEYLEN));
+ print_buf("HMAC Key",
+ &desc->ctl_desc.cipherHashInfo.infoARC4StateHMAC.hmacKey0,
+ sizeof(HMAC_t));
+ break;
+ case XLR_SEC_VECTOR_CIPHER_KASUMI_F8:
+ DPRINT("VECTOR: XLR_SEC_VECTOR_CIPHER_KASUMI_F8 \n");
+ print_buf("KASUMI_F8 Key",
+ &desc->ctl_desc.cipherHashInfo.infoKASUMIF8.cipherKey0,
+ XLR_SEC_KASUMI_F8_KEY_LENGTH);
+ break;
+ case XLR_SEC_VECTOR_CIPHER_KASUMI_F8__HMAC:
+ DPRINT("XLR_SEC_VECTOR_CIPHER_KASUMI_F8__HMAC\n");
+ print_buf("KASUMI_F8 Key",
+ &desc->ctl_desc.cipherHashInfo.infoKASUMIF8HMAC.cipherKey0,
+ XLR_SEC_KASUMI_F8_KEY_LENGTH);
+ print_buf("HMAC Key",
+ &desc->ctl_desc.cipherHashInfo.infoKASUMIF8HMAC.hmacKey0,
+ sizeof(HMAC_t));
+ break;
+ case XLR_SEC_VECTOR_CIPHER_KASUMI_F8__HMAC2:
+ DPRINT("XLR_SEC_VECTOR_CIPHER_KASUMI_F8__HMAC2\n");
+ print_buf("KASUMI_F8 Key",
+ &desc->ctl_desc.cipherHashInfo.infoKASUMIF8HMAC2.cipherKey0,
+ XLR_SEC_KASUMI_F8_KEY_LENGTH);
+ print_buf("HMAC2 Key",
+ &desc->ctl_desc.cipherHashInfo.infoKASUMIF8HMAC2.hmacKey0,
+ sizeof(HMAC2_t));
+ break;
+ case XLR_SEC_VECTOR_CIPHER_KASUMI_F8__GCM:
+ DPRINT("XLR_SEC_VECTOR_CIPHER_KASUMI_F8__GCM\n");
+ print_buf("KASUMI_F8 Key",
+ &desc->ctl_desc.cipherHashInfo.infoKASUMIF8GCM.cipherKey0,
+ XLR_SEC_KASUMI_F8_KEY_LENGTH);
+ print_buf("GCM Key",
+ &desc->ctl_desc.cipherHashInfo.infoKASUMIF8GCM.GCMH0,
+ sizeof(GCM_t));
+ break;
+ case XLR_SEC_VECTOR_CIPHER_KASUMI_F8__F9:
+ DPRINT("XLR_SEC_VECTOR_CIPHER_KASUMI_F8__F9\n");
+ print_buf("KASUMI_F8 Key",
+ &desc->ctl_desc.cipherHashInfo.infoKASUMIF8F9.cipherKey0,
+ XLR_SEC_KASUMI_F8_KEY_LENGTH);
+ print_buf("F9 Key",
+ &desc->ctl_desc.cipherHashInfo.infoKASUMIF8F9.authKey0,
+ sizeof(F9_t));
+ break;
+ case XLR_SEC_VECTOR_MAC:
+ DPRINT("VECTOR: XLR_SEC_VECTOR_MAC \n");
+ DPRINT("MAC-ONLY - No Info\n");
+ break;
+ case XLR_SEC_VECTOR_HMAC:
+ DPRINT("VECTOR: XLR_SEC_VECTOR_HMAC \n");
+ print_buf("HMAC Key",
+ &desc->ctl_desc.cipherHashInfo.infoHMAC.hmacKey0,
+ sizeof(HMAC_t));
+ break;
+ case XLR_SEC_VECTOR__CIPHER_DES__HMAC__MODE_ECB_CBC:
+ DPRINT("VECTOR: XLR_SEC_VECTOR__CIPHER_DES__HMAC__MODE_ECB_CBC \n");
+ print_buf("CIPHER Key",
+ &desc->ctl_desc.cipherHashInfo.infoDESHMAC.cipherKey0,
+ XLR_SEC_DES_KEY_LENGTH);
+ print_buf("HMAC Key",
+ &desc->ctl_desc.cipherHashInfo.infoDESHMAC.hmacKey0,
+ sizeof(HMAC_t));
+ break;
+ case XLR_SEC_VECTOR__CIPHER_DES__MODE_ECB_CBC:
+ DPRINT("VECTOR: XLR_SEC_VECTOR__CIPHER_DES__MODE_ECB_CBC \n");
+ print_buf("CIPHER Key",
+ &desc->ctl_desc.cipherHashInfo.infoDES.cipherKey0,
+ XLR_SEC_DES_KEY_LENGTH);
+ break;
+ case XLR_SEC_VECTOR__CIPHER_3DES__HMAC__MODE_ECB_CBC:
+ DPRINT("VECTOR: XLR_SEC_VECTOR__CIPHER_3DES__HMAC__MODE_ECB_CBC \n");
+ print_buf("CIPHER Key",
+ &desc->ctl_desc.cipherHashInfo.info3DESHMAC.cipherKey0,
+ XLR_SEC_3DES_KEY_LENGTH);
+ print_buf("HMAC Key",
+ &desc->ctl_desc.cipherHashInfo.info3DESHMAC.hmacKey0,
+ sizeof(HMAC_t));
+ break;
+ case XLR_SEC_VECTOR__CIPHER_3DES__MODE_ECB_CBC:
+ DPRINT("VECTOR: XLR_SEC_VECTOR__CIPHER_3DES__MODE_ECB_CBC \n");
+ print_buf("CIPHER Key",
+ &desc->ctl_desc.cipherHashInfo.info3DES.cipherKey0,
+ XLR_SEC_3DES_KEY_LENGTH);
+ break;
+ case XLR_SEC_VECTOR__CIPHER_AES128__HMAC__MODE_CTR_CFB:
+ DPRINT("VECTOR: XLR_SEC_VECTOR__CIPHER_AES128__HMAC__MODE_CTR_CFB \n");
+ print_buf("CIPHER Key",
+ &desc->ctl_desc.cipherHashInfo.infoAES128HMAC.cipherKey0,
+ XLR_SEC_AES128_KEY_LENGTH);
+ print_buf("HMAC Key",
+ &desc->ctl_desc.cipherHashInfo.infoAES128HMAC.hmacKey0,
+ sizeof(HMAC_t));
+ break;
+ case XLR_SEC_VECTOR__CIPHER_AES128__MODE_CTR_CFB:
+ DPRINT("VECTOR: XLR_SEC_VECTOR__CIPHER_AES128__MODE_CTR_CFB \n");
+ print_buf("CIPHER Key",
+ &desc->ctl_desc.cipherHashInfo.infoAES128.cipherKey0,
+ XLR_SEC_AES128_KEY_LENGTH);
+ break;
+ case XLR_SEC_VECTOR__CIPHER_AES128__HMAC__MODE_ECB_CBC_OFB:
+ DPRINT("VECTOR: XLR_SEC_VECTOR__CIPHER_AES128__HMAC__MODE_ECB_CBC_OFB\n");
+ print_buf("CIPHER Key",
+ &desc->ctl_desc.cipherHashInfo.infoAES128HMAC.cipherKey0,
+ XLR_SEC_AES128_KEY_LENGTH);
+ print_buf("HMAC Key",
+ &desc->ctl_desc.cipherHashInfo.infoAES128HMAC.hmacKey0,
+ sizeof(HMAC_t));
+ break;
+ case XLR_SEC_VECTOR__CIPHER_AES128__MODE_ECB_CBC_OFB:
+ DPRINT("VECTOR: XLR_SEC_VECTOR__CIPHER_AES128__MODE_ECB_CBC_OFB \n");
+ print_buf("CIPHER Key",
+ &desc->ctl_desc.cipherHashInfo.infoAES128.cipherKey0,
+ XLR_SEC_AES128_KEY_LENGTH);
+ break;
+ case XLR_SEC_VECTOR__CIPHER_AES192__HMAC__MODE_CTR_CFB:
+ DPRINT("VECTOR: XLR_SEC_VECTOR__CIPHER_AES192__HMAC__MODE_CTR_CFB \n");
+ print_buf("CIPHER Key",
+ &desc->ctl_desc.cipherHashInfo.infoAES192HMAC.cipherKey0,
+ XLR_SEC_AES192_KEY_LENGTH);
+ print_buf("HMAC Key",
+ &desc->ctl_desc.cipherHashInfo.infoAES192HMAC.hmacKey0,
+ sizeof(HMAC_t));
+ break;
+ case XLR_SEC_VECTOR__CIPHER_AES192__MODE_CTR_CFB:
+ DPRINT("VECTOR: XLR_SEC_VECTOR__CIPHER_AES192__MODE_CTR_CFB \n");
+ print_buf("CIPHER Key",
+ &desc->ctl_desc.cipherHashInfo.infoAES192.cipherKey0,
+ XLR_SEC_AES192_KEY_LENGTH);
+ break;
+ case XLR_SEC_VECTOR__CIPHER_AES192__HMAC__MODE_ECB_CBC_OFB:
+ DPRINT("VECTOR: XLR_SEC_VECTOR__CIPHER_AES192__HMAC__MODE_ECB_CBC_OFB\n");
+ print_buf("CIPHER Key",
+ &desc->ctl_desc.cipherHashInfo.infoAES192HMAC.cipherKey0,
+ XLR_SEC_AES192_KEY_LENGTH);
+ print_buf("HMAC Key",
+ &desc->ctl_desc.cipherHashInfo.infoAES192HMAC.hmacKey0,
+ sizeof(HMAC_t));
+ break;
+ case XLR_SEC_VECTOR__CIPHER_AES192__MODE_ECB_CBC_OFB:
+ DPRINT("VECTOR: XLR_SEC_VECTOR__CIPHER_AES192__MODE_ECB_CBC_OFB \n");
+ print_buf("CIPHER Key",
+ &desc->ctl_desc.cipherHashInfo.infoAES192.cipherKey0,
+ XLR_SEC_AES192_KEY_LENGTH);
+ break;
+
+ case XLR_SEC_VECTOR__CIPHER_AES256__HMAC__MODE_CTR_CFB:
+ DPRINT("VECTOR: XLR_SEC_VECTOR__CIPHER_AES256__HMAC__MODE_CTR_CFB \n");
+ print_buf("CIPHER Key",
+ &desc->ctl_desc.cipherHashInfo.infoAES256HMAC.cipherKey0,
+ XLR_SEC_AES256_KEY_LENGTH);
+ print_buf("HMAC Key",
+ &desc->ctl_desc.cipherHashInfo.infoAES256HMAC.hmacKey0,
+ sizeof(HMAC_t));
+ break;
+ case XLR_SEC_VECTOR__CIPHER_AES256__MODE_CTR_CFB:
+ DPRINT("VECTOR: XLR_SEC_VECTOR__CIPHER_AES256__MODE_CTR_CFB \n");
+ print_buf("CIPHER Key",
+ &desc->ctl_desc.cipherHashInfo.infoAES256.cipherKey0,
+ XLR_SEC_AES256_KEY_LENGTH);
+ break;
+ case XLR_SEC_VECTOR__CIPHER_AES256__HMAC__MODE_ECB_CBC_OFB:
+ DPRINT("VECTOR: XLR_SEC_VECTOR__CIPHER_AES256__HMAC__MODE_ECB_CBC_OFB \n");
+ print_buf("CIPHER Key",
+ &desc->ctl_desc.cipherHashInfo.infoAES256HMAC.cipherKey0,
+ XLR_SEC_AES256_KEY_LENGTH);
+ print_buf("HMAC Key",
+ &desc->ctl_desc.cipherHashInfo.infoAES256HMAC.hmacKey0,
+ sizeof(HMAC_t));
+ break;
+ case XLR_SEC_VECTOR__CIPHER_AES256__MODE_ECB_CBC_OFB:
+ DPRINT("VECTOR: XLR_SEC_VECTOR__CIPHER_AES256__MODE_ECB_CBC_OFB \n");
+ print_buf("CIPHER Key",
+ &desc->ctl_desc.cipherHashInfo.infoAES256.cipherKey0,
+ XLR_SEC_AES256_KEY_LENGTH);
+ break;
+ case XLR_SEC_VECTOR_CIPHER_ARC4__HMAC2:
+ DPRINT("VECTOR: XLR_SEC_VECTOR_CIPHER_ARC4__HMAC2 \n");
+ print_buf("ARC4 Key",
+ &desc->ctl_desc.cipherHashInfo.infoARC4HMAC2.cipherKey0,
+ GET_FIELD(word, CTL_DSC_ARC4_KEYLEN));
+ print_buf("HMAC2 Key",
+ &desc->ctl_desc.cipherHashInfo.infoARC4HMAC2.hmacKey0,
+ sizeof(HMAC2_t));
+ break;
+ case XLR_SEC_VECTOR_CIPHER_ARC4__HMAC2__STATE:
+ DPRINT("VECTOR: XLR_SEC_VECTOR_CIPHER_ARC4__HMAC2__STATE \n");
+ print_buf("ARC4 Key",
+ &desc->ctl_desc.cipherHashInfo.infoARC4StateHMAC2.cipherKey0,
+ GET_FIELD(word, CTL_DSC_ARC4_KEYLEN));
+ print_buf("HMAC2 Key",
+ &desc->ctl_desc.cipherHashInfo.infoARC4StateHMAC2.hmacKey0,
+ sizeof(HMAC2_t));
+ break;
+ case XLR_SEC_VECTOR_HMAC2:
+ DPRINT("VECTOR: XLR_SEC_VECTOR_HMAC2 \n");
+ print_buf("HMAC2 Key",
+ &desc->ctl_desc.cipherHashInfo.infoHMAC2.hmacKey0,
+ sizeof(HMAC2_t));
+ break;
+ case XLR_SEC_VECTOR__CIPHER_DES__HMAC2__MODE_ECB_CBC:
+ DPRINT("VECTOR: XLR_SEC_VECTOR__CIPHER_DES__HMAC2__MODE_ECB_CBC \n");
+ print_buf("CIPHER Key",
+ &desc->ctl_desc.cipherHashInfo.infoDESHMAC2.cipherKey0,
+ XLR_SEC_DES_KEY_LENGTH);
+ print_buf("HMAC2 Key",
+ &desc->ctl_desc.cipherHashInfo.infoDESHMAC2.hmacKey0,
+ sizeof(HMAC2_t));
+ break;
+ case XLR_SEC_VECTOR__CIPHER_3DES__HMAC2__MODE_ECB_CBC:
+ DPRINT("VECTOR: XLR_SEC_VECTOR__CIPHER_3DES__HMAC2__MODE_ECB_CBC \n");
+ print_buf("CIPHER Key",
+ &desc->ctl_desc.cipherHashInfo.info3DESHMAC2.cipherKey0,
+ XLR_SEC_3DES_KEY_LENGTH);
+ print_buf("HMAC2 Key",
+ &desc->ctl_desc.cipherHashInfo.info3DESHMAC2.hmacKey0,
+ sizeof(HMAC2_t));
+ break;
+ case XLR_SEC_VECTOR__CIPHER_AES128__HMAC2__MODE_CTR_CFB:
+ DPRINT("VECTOR: XLR_SEC_VECTOR__CIPHER_AES128__HMAC2__MODE_CTR_CFB \n");
+ print_buf("CIPHER Key",
+ &desc->ctl_desc.cipherHashInfo.infoAES128HMAC2.cipherKey0,
+ XLR_SEC_AES128_KEY_LENGTH);
+ print_buf("HMAC2 Key",
+ &desc->ctl_desc.cipherHashInfo.infoAES128HMAC2.hmacKey0,
+ sizeof(HMAC2_t));
+ break;
+ case XLR_SEC_VECTOR__CIPHER_AES128__HMAC2__MODE_ECB_CBC_OFB:
+ DPRINT("VECTOR: XLR_SEC_VECTOR__CIPHER_AES128__HMAC2__MODE_ECB_CBC_OFB\n");
+ print_buf("CIPHER Key",
+ &desc->ctl_desc.cipherHashInfo.infoAES128HMAC2.cipherKey0,
+ XLR_SEC_AES128_KEY_LENGTH);
+ print_buf("HMAC2 Key",
+ &desc->ctl_desc.cipherHashInfo.infoAES128HMAC2.hmacKey0,
+ sizeof(HMAC2_t));
+ break;
+ case XLR_SEC_VECTOR__CIPHER_AES192__HMAC2__MODE_CTR_CFB:
+ DPRINT("VECTOR: XLR_SEC_VECTOR__CIPHER_AES192__HMAC2__MODE_CTR_CFB \n");
+ print_buf("CIPHER Key",
+ &desc->ctl_desc.cipherHashInfo.infoAES192HMAC2.cipherKey0,
+ XLR_SEC_AES192_KEY_LENGTH);
+ print_buf("HMAC2 Key",
+ &desc->ctl_desc.cipherHashInfo.infoAES192HMAC2.hmacKey0,
+ sizeof(HMAC2_t));
+ break;
+ case XLR_SEC_VECTOR__CIPHER_AES192__HMAC2__MODE_ECB_CBC_OFB:
+ DPRINT("VECTOR: XLR_SEC_VECTOR__CIPHER_AES192__HMAC2__MODE_ECB_CBC_OFB\n");
+ print_buf("CIPHER Key",
+ &desc->ctl_desc.cipherHashInfo.infoAES192HMAC2.cipherKey0,
+ XLR_SEC_AES192_KEY_LENGTH);
+ print_buf("HMAC2 Key",
+ &desc->ctl_desc.cipherHashInfo.infoAES192HMAC2.hmacKey0,
+ sizeof(HMAC2_t));
+ break;
+ case XLR_SEC_VECTOR__CIPHER_AES256__HMAC2__MODE_CTR_CFB:
+ DPRINT("VECTOR: XLR_SEC_VECTOR__CIPHER_AES256__HMAC2__MODE_CTR_CFB \n");
+ print_buf("CIPHER Key",
+ &desc->ctl_desc.cipherHashInfo.infoAES256HMAC2.cipherKey0,
+ XLR_SEC_AES256_KEY_LENGTH);
+ print_buf("HMAC2 Key",
+ &desc->ctl_desc.cipherHashInfo.infoAES256HMAC2.hmacKey0,
+ sizeof(HMAC2_t));
+ break;
+
+ case XLR_SEC_VECTOR__CIPHER_AES256__HMAC2__MODE_ECB_CBC_OFB:
+ DPRINT("VECTOR: XLR_SEC_VECTOR__CIPHER_AES256__HMAC2__MODE_ECB_CBC_OFB \n");
+ print_buf("CIPHER Key",
+ &desc->ctl_desc.cipherHashInfo.infoAES256HMAC2.cipherKey0,
+ XLR_SEC_AES256_KEY_LENGTH);
+ print_buf("HMAC2 Key",
+ &desc->ctl_desc.cipherHashInfo.infoAES256HMAC2.hmacKey0,
+ sizeof(HMAC2_t));
+ break;
+ case XLR_SEC_VECTOR_CIPHER_ARC4__GCM:
+ DPRINT("VECTOR: XLR_SEC_VECTOR_CIPHER_ARC4__GCM \n");
+ print_buf("ARC4 Key",
+ &desc->ctl_desc.cipherHashInfo.infoARC4GCM.cipherKey0,
+ GET_FIELD(word, CTL_DSC_ARC4_KEYLEN));
+ print_buf("GCM Key",
+ &desc->ctl_desc.cipherHashInfo.infoARC4GCM.GCMH0,
+ sizeof(GCM_t));
+ break;
+ case XLR_SEC_VECTOR_CIPHER_ARC4__GCM__STATE:
+ DPRINT("VECTOR: XLR_SEC_VECTOR_CIPHER_ARC4__GCM__STATE \n");
+ print_buf("ARC4 Key",
+ &desc->ctl_desc.cipherHashInfo.infoARC4StateGCM.cipherKey0,
+ GET_FIELD(word, CTL_DSC_ARC4_KEYLEN));
+ print_buf("GCM Key",
+ &desc->ctl_desc.cipherHashInfo.infoARC4StateGCM.GCMH0,
+ sizeof(GCM_t));
+ break;
+ case XLR_SEC_VECTOR_GCM:
+ DPRINT("VECTOR: XLR_SEC_VECTOR_GCM \n");
+ print_buf("GCM Key",
+ &desc->ctl_desc.cipherHashInfo.infoGCM.GCMH0,
+ sizeof(GCM_t));
+ break;
+ case XLR_SEC_VECTOR__CIPHER_DES__GCM__MODE_ECB_CBC:
+ DPRINT("VECTOR: XLR_SEC_VECTOR__CIPHER_DES__GCM__MODE_ECB_CBC \n");
+ print_buf("CIPHER Key",
+ &desc->ctl_desc.cipherHashInfo.infoDESGCM.cipherKey0,
+ XLR_SEC_DES_KEY_LENGTH);
+ print_buf("GCM Key",
+ &desc->ctl_desc.cipherHashInfo.infoDESGCM.GCMH0,
+ sizeof(GCM_t));
+ break;
+ case XLR_SEC_VECTOR__CIPHER_3DES__GCM__MODE_ECB_CBC:
+ DPRINT("VECTOR: XLR_SEC_VECTOR__CIPHER_3DES__GCM__MODE_ECB_CBC \n");
+ print_buf("CIPHER Key",
+ &desc->ctl_desc.cipherHashInfo.info3DESGCM.cipherKey0,
+ XLR_SEC_3DES_KEY_LENGTH);
+ print_buf("GCM Key",
+ &desc->ctl_desc.cipherHashInfo.info3DESGCM.GCMH0,
+ sizeof(GCM_t));
+ break;
+ case XLR_SEC_VECTOR__CIPHER_AES128__GCM__MODE_CTR_CFB:
+ DPRINT("VECTOR: XLR_SEC_VECTOR__CIPHER_AES128__GCM__MODE_CTR_CFB \n");
+ print_buf("CIPHER Key",
+ &desc->ctl_desc.cipherHashInfo.infoAES128GCM.cipherKey0,
+ XLR_SEC_AES128_KEY_LENGTH);
+ print_buf("GCM Key",
+ &desc->ctl_desc.cipherHashInfo.infoAES128GCM.GCMH0,
+ XLR_SEC_AES128_KEY_LENGTH);
+ break;
+ case XLR_SEC_VECTOR__CIPHER_AES128__GCM__MODE_ECB_CBC_OFB:
+ DPRINT("VECTOR: XLR_SEC_VECTOR__CIPHER_AES128__GCM__MODE_ECB_CBC_OFB\n");
+ print_buf("CIPHER Key",
+ &desc->ctl_desc.cipherHashInfo.infoAES128GCM.cipherKey0,
+ XLR_SEC_AES128_KEY_LENGTH);
+ print_buf("GCM Key",
+ &desc->ctl_desc.cipherHashInfo.infoAES128GCM.GCMH0,
+ XLR_SEC_AES128_KEY_LENGTH);
+ break;
+ case XLR_SEC_VECTOR__CIPHER_AES192__GCM__MODE_CTR_CFB:
+ DPRINT("VECTOR: XLR_SEC_VECTOR__CIPHER_AES192__GCM__MODE_CTR_CFB \n");
+ print_buf("CIPHER Key",
+ &desc->ctl_desc.cipherHashInfo.infoAES192GCM.cipherKey0,
+ XLR_SEC_AES192_KEY_LENGTH);
+ print_buf("GCM Key",
+ &desc->ctl_desc.cipherHashInfo.infoAES192GCM.GCMH0,
+ XLR_SEC_AES192_KEY_LENGTH);
+ break;
+ case XLR_SEC_VECTOR__CIPHER_AES192__GCM__MODE_ECB_CBC_OFB:
+ DPRINT("VECTOR: XLR_SEC_VECTOR__CIPHER_AES192__GCM__MODE_ECB_CBC_OFB\n");
+ print_buf("CIPHER Key",
+ &desc->ctl_desc.cipherHashInfo.infoAES192GCM.cipherKey0,
+ XLR_SEC_AES192_KEY_LENGTH);
+ print_buf("GCM Key",
+ &desc->ctl_desc.cipherHashInfo.infoAES192GCM.GCMH0,
+ XLR_SEC_AES192_KEY_LENGTH);
+ break;
+ case XLR_SEC_VECTOR__CIPHER_AES256__GCM__MODE_CTR_CFB:
+ DPRINT("VECTOR: XLR_SEC_VECTOR__CIPHER_AES256__GCM__MODE_CTR_CFB \n");
+ print_buf("CIPHER Key",
+ &desc->ctl_desc.cipherHashInfo.infoAES256GCM.cipherKey0,
+ XLR_SEC_AES256_KEY_LENGTH);
+ print_buf("GCM Key",
+ &desc->ctl_desc.cipherHashInfo.infoAES256GCM.GCMH0,
+ XLR_SEC_AES256_KEY_LENGTH);
+ break;
+ case XLR_SEC_VECTOR__CIPHER_AES256__GCM__MODE_ECB_CBC_OFB:
+ DPRINT("VECTOR: XLR_SEC_VECTOR__CIPHER_AES256__GCM__MODE_ECB_CBC_OFB \n");
+ print_buf("CIPHER Key",
+ &desc->ctl_desc.cipherHashInfo.infoAES256GCM.cipherKey0,
+ XLR_SEC_AES256_KEY_LENGTH);
+ print_buf("GCM Key",
+ &desc->ctl_desc.cipherHashInfo.infoAES256GCM.GCMH0,
+ XLR_SEC_AES256_KEY_LENGTH);
+ break;
+ case XLR_SEC_VECTOR_CIPHER_ARC4__F9:
+ DPRINT("VECTOR: XLR_SEC_VECTOR_CIPHER_ARC4__F9 \n");
+ print_buf("ARC4 Key",
+ &desc->ctl_desc.cipherHashInfo.infoARC4F9.cipherKey0,
+ GET_FIELD(word, CTL_DSC_ARC4_KEYLEN));
+ print_buf("F9 Key",
+ &desc->ctl_desc.cipherHashInfo.infoARC4F9.authKey0,
+ sizeof(F9_t));
+ break;
+ case XLR_SEC_VECTOR_CIPHER_ARC4__F9__STATE:
+ DPRINT("VECTOR: XLR_SEC_VECTOR_CIPHER_ARC4__F9__STATE \n");
+ print_buf("ARC4 Key",
+ &desc->ctl_desc.cipherHashInfo.infoARC4StateF9.cipherKey0,
+ GET_FIELD(word, CTL_DSC_ARC4_KEYLEN));
+ print_buf("F9 Key",
+ &desc->ctl_desc.cipherHashInfo.infoARC4StateF9.authKey0,
+ sizeof(F9_t));
+ break;
+ case XLR_SEC_VECTOR_F9:
+ DPRINT("VECTOR: XLR_SEC_VECTOR_F9 \n");
+ print_buf("F9 Key",
+ &desc->ctl_desc.cipherHashInfo.infoF9.authKey0,
+ sizeof(F9_t));
+ break;
+ case XLR_SEC_VECTOR__CIPHER_DES__F9__MODE_ECB_CBC:
+ DPRINT("VECTOR: XLR_SEC_VECTOR__CIPHER_DES__F9__MODE_ECB_CBC \n");
+ print_buf("CIPHER Key",
+ &desc->ctl_desc.cipherHashInfo.infoDESF9.cipherKey0,
+ XLR_SEC_DES_KEY_LENGTH);
+ print_buf("F9 Key",
+ &desc->ctl_desc.cipherHashInfo.infoDESF9.authKey0,
+ sizeof(F9_t));
+ break;
+ case XLR_SEC_VECTOR__CIPHER_3DES__F9__MODE_ECB_CBC:
+ DPRINT("VECTOR: XLR_SEC_VECTOR__CIPHER_3DES__F9__MODE_ECB_CBC \n");
+ print_buf("CIPHER Key",
+ &desc->ctl_desc.cipherHashInfo.info3DESF9.cipherKey0,
+ XLR_SEC_3DES_KEY_LENGTH);
+ print_buf("F9 Key",
+ &desc->ctl_desc.cipherHashInfo.info3DESF9.authKey0,
+ sizeof(F9_t));
+ break;
+ case XLR_SEC_VECTOR__CIPHER_AES128__F9__MODE_CTR_CFB:
+ DPRINT("VECTOR: XLR_SEC_VECTOR__CIPHER_AES128__F9__MODE_CTR_CFB \n");
+ print_buf("CIPHER Key",
+ &desc->ctl_desc.cipherHashInfo.infoAES128F9.cipherKey0,
+ XLR_SEC_AES128_KEY_LENGTH);
+ print_buf("F9 Key",
+ &desc->ctl_desc.cipherHashInfo.infoAES128F9.authKey0,
+ sizeof(F9_t));
+ break;
+ case XLR_SEC_VECTOR__CIPHER_AES128__F9__MODE_ECB_CBC_OFB:
+ DPRINT("VECTOR: XLR_SEC_VECTOR__CIPHER_AES128__F9__MODE_ECB_CBC_OFB\n");
+ print_buf("CIPHER Key",
+ &desc->ctl_desc.cipherHashInfo.infoAES128F9.cipherKey0,
+ XLR_SEC_AES128_KEY_LENGTH);
+ print_buf("F9 Key",
+ &desc->ctl_desc.cipherHashInfo.infoAES128F9.authKey0,
+ sizeof(F9_t));
+ break;
+ case XLR_SEC_VECTOR__CIPHER_AES192__F9__MODE_CTR_CFB:
+ DPRINT("VECTOR: XLR_SEC_VECTOR__CIPHER_AES192__F9__MODE_CTR_CFB \n");
+ print_buf("CIPHER Key",
+ &desc->ctl_desc.cipherHashInfo.infoAES192F9.cipherKey0,
+ XLR_SEC_AES192_KEY_LENGTH);
+ print_buf("F9 Key",
+ &desc->ctl_desc.cipherHashInfo.infoAES192F9.authKey0,
+ sizeof(F9_t));
+ break;
+ case XLR_SEC_VECTOR__CIPHER_AES192__F9__MODE_ECB_CBC_OFB:
+ DPRINT("VECTOR: XLR_SEC_VECTOR__CIPHER_AES192__F9__MODE_ECB_CBC_OFB\n");
+ print_buf("CIPHER Key",
+ &desc->ctl_desc.cipherHashInfo.infoAES192F9.cipherKey0,
+ XLR_SEC_AES192_KEY_LENGTH);
+ print_buf("F9 Key",
+ &desc->ctl_desc.cipherHashInfo.infoAES192F9.authKey0,
+ sizeof(F9_t));
+ break;
+ case XLR_SEC_VECTOR__CIPHER_AES256__F9__MODE_CTR_CFB:
+ DPRINT("VECTOR: XLR_SEC_VECTOR__CIPHER_AES256__F9__MODE_CTR_CFB \n");
+ print_buf("CIPHER Key",
+ &desc->ctl_desc.cipherHashInfo.infoAES256F9.cipherKey0,
+ XLR_SEC_AES256_KEY_LENGTH);
+ print_buf("F9 Key",
+ &desc->ctl_desc.cipherHashInfo.infoAES256F9.authKey0,
+ sizeof(F9_t));
+ break;
+ case XLR_SEC_VECTOR__CIPHER_AES256__F9__MODE_ECB_CBC_OFB:
+ DPRINT("VECTOR: XLR_SEC_VECTOR__CIPHER_AES256__F9__MODE_ECB_CBC_OFB \n");
+ print_buf("CIPHER Key",
+ &desc->ctl_desc.cipherHashInfo.infoAES256F9.cipherKey0,
+ XLR_SEC_AES256_KEY_LENGTH);
+ print_buf("F9 Key",
+ &desc->ctl_desc.cipherHashInfo.infoAES256F9.authKey0,
+ sizeof(F9_t));
+ break;
+ case XLR_SEC_VECTOR__CIPHER_AES128__HMAC__MODE_F8:
+ DPRINT("VECTOR: XLR_SEC_VECTOR__CIPHER_AES128__HMAC__MODE_F8 \n");
+ print_buf("CIPHER Key",
+ &desc->ctl_desc.cipherHashInfo.infoAES128F8HMAC.cipherKey0,
+ XLR_SEC_AES128F8_KEY_LENGTH);
+ print_buf("HMAC Key",
+ &desc->ctl_desc.cipherHashInfo.infoAES128F8HMAC.hmacKey0,
+ sizeof(HMAC_t));
+ break;
+ case XLR_SEC_VECTOR__CIPHER_AES128__MODE_F8:
+ DPRINT("VECTOR: XLR_SEC_VECTOR__CIPHER_AES128__MODE_F8 \n");
+ print_buf("CIPHER Key",
+ &desc->ctl_desc.cipherHashInfo.infoAES128F8.cipherKey0,
+ XLR_SEC_AES128F8_KEY_LENGTH);
+ break;
+ case XLR_SEC_VECTOR__CIPHER_AES192__HMAC__MODE_F8:
+ DPRINT("VECTOR: XLR_SEC_VECTOR__CIPHER_AES192__HMAC__MODE_F8 \n");
+ print_buf("CIPHER Key",
+ &desc->ctl_desc.cipherHashInfo.infoAES192F8HMAC.cipherKey0,
+ XLR_SEC_AES192F8_KEY_LENGTH);
+ print_buf("HMAC Key",
+ &desc->ctl_desc.cipherHashInfo.infoAES192F8HMAC.hmacKey0,
+ sizeof(HMAC_t));
+ break;
+ case XLR_SEC_VECTOR__CIPHER_AES192__MODE_F8:
+ DPRINT("VECTOR: XLR_SEC_VECTOR__CIPHER_AES192__MODE_F8 \n");
+ print_buf("CIPHER Key",
+ &desc->ctl_desc.cipherHashInfo.infoAES192F8.cipherKey0,
+ XLR_SEC_AES192F8_KEY_LENGTH);
+ break;
+ case XLR_SEC_VECTOR__CIPHER_AES256__HMAC__MODE_F8:
+ DPRINT("VECTOR: XLR_SEC_VECTOR__CIPHER_AES256__HMAC__MODE_F8 \n");
+ print_buf("CIPHER Key",
+ &desc->ctl_desc.cipherHashInfo.infoAES256F8HMAC.cipherKey0,
+ XLR_SEC_AES256F8_KEY_LENGTH);
+ print_buf("HMAC Key",
+ &desc->ctl_desc.cipherHashInfo.infoAES256HMAC.hmacKey0,
+ sizeof(HMAC_t));
+ break;
+ case XLR_SEC_VECTOR__CIPHER_AES256__MODE_F8:
+ DPRINT("VECTOR: XLR_SEC_VECTOR__CIPHER_AES256__MODE_F8 \n");
+ print_buf("CIPHER Key",
+ &desc->ctl_desc.cipherHashInfo.infoAES256F8.cipherKey0,
+ XLR_SEC_AES256F8_KEY_LENGTH);
+ break;
+ case XLR_SEC_VECTOR__CIPHER_AES128__HMAC2__MODE_F8:
+ DPRINT("VECTOR: XLR_SEC_VECTOR__CIPHER_AES128__HMAC2__MODE_F8 \n");
+ print_buf("CIPHER Key",
+ &desc->ctl_desc.cipherHashInfo.infoAES128F8HMAC2.cipherKey0,
+ XLR_SEC_AES128F8_KEY_LENGTH);
+ print_buf("HMAC2 Key",
+ &desc->ctl_desc.cipherHashInfo.infoAES128F8HMAC2.hmacKey0,
+ sizeof(HMAC2_t));
+ break;
+ case XLR_SEC_VECTOR__CIPHER_AES192__HMAC2__MODE_F8:
+ DPRINT("VECTOR: XLR_SEC_VECTOR__CIPHER_AES192__HMAC2__MODE_F8 \n");
+ print_buf("CIPHER Key",
+ &desc->ctl_desc.cipherHashInfo.infoAES192F8HMAC2.cipherKey0,
+ XLR_SEC_AES192F8_KEY_LENGTH);
+ print_buf("HMAC2 Key",
+ &desc->ctl_desc.cipherHashInfo.infoAES192F8HMAC2.hmacKey0,
+ sizeof(HMAC2_t));
+ break;
+ case XLR_SEC_VECTOR__CIPHER_AES256__HMAC2__MODE_F8:
+ DPRINT("VECTOR: XLR_SEC_VECTOR__CIPHER_AES256__HMAC2__MODE_F8 \n");
+ print_buf("CIPHER Key",
+ &desc->ctl_desc.cipherHashInfo.infoAES256F8HMAC2.cipherKey0,
+ XLR_SEC_AES256F8_KEY_LENGTH);
+ print_buf("HMAC2 Key",
+ &desc->ctl_desc.cipherHashInfo.infoAES256F8HMAC2.hmacKey0,
+ sizeof(HMAC2_t));
+ break;
+ case XLR_SEC_VECTOR__CIPHER_AES128__GCM__MODE_F8:
+ DPRINT("VECTOR: XLR_SEC_VECTOR__CIPHER_AES128__GCM__MODE_F8 \n");
+ print_buf("CIPHER Key",
+ &desc->ctl_desc.cipherHashInfo.infoAES128F8GCM.cipherKey0,
+ XLR_SEC_AES128F8_KEY_LENGTH);
+ print_buf("GCM Key",
+ &desc->ctl_desc.cipherHashInfo.infoAES128GCM.GCMH0,
+ XLR_SEC_AES128_KEY_LENGTH);
+ break;
+ case XLR_SEC_VECTOR__CIPHER_AES192__GCM__MODE_F8:
+ DPRINT("VECTOR: XLR_SEC_VECTOR__CIPHER_AES192__GCM__MODE_F8 \n");
+ print_buf("CIPHER Key",
+ &desc->ctl_desc.cipherHashInfo.infoAES192F8GCM.cipherKey0,
+ XLR_SEC_AES192_KEY_LENGTH);
+ print_buf("GCM Key",
+ &desc->ctl_desc.cipherHashInfo.infoAES192F8GCM.GCMH0,
+ XLR_SEC_AES192_KEY_LENGTH);
+ break;
+ case XLR_SEC_VECTOR__CIPHER_AES256__GCM__MODE_F8:
+ DPRINT("VECTOR: XLR_SEC_VECTOR__CIPHER_AES256__GCM__MODE_F8 \n");
+ print_buf("CIPHER Key",
+ &desc->ctl_desc.cipherHashInfo.infoAES256F8GCM.cipherKey0,
+ XLR_SEC_AES256F8_KEY_LENGTH);
+ print_buf("GCM Key",
+ &desc->ctl_desc.cipherHashInfo.infoAES256F8GCM.GCMH0,
+ XLR_SEC_AES256_KEY_LENGTH);
+ break;
+ case XLR_SEC_VECTOR__CIPHER_AES128__F9__MODE_F8:
+ DPRINT("VECTOR: XLR_SEC_VECTOR__CIPHER_AES128__F9__MODE_F8 \n");
+ print_buf("CIPHER Key",
+ &desc->ctl_desc.cipherHashInfo.infoAES128F8F9.cipherKey0,
+ XLR_SEC_AES128F8_KEY_LENGTH);
+ print_buf("F9 Key",
+ &desc->ctl_desc.cipherHashInfo.infoAES128F8F9.authKey0,
+ sizeof(F9_t));
+ break;
+ case XLR_SEC_VECTOR__CIPHER_AES192__F9__MODE_F8:
+ DPRINT("VECTOR: XLR_SEC_VECTOR__CIPHER_AES192__F9__MODE_F8 \n");
+ print_buf("CIPHER Key",
+ &desc->ctl_desc.cipherHashInfo.infoAES192F8F9.cipherKey0,
+ XLR_SEC_AES192F8_KEY_LENGTH);
+ print_buf("F9 Key",
+ &desc->ctl_desc.cipherHashInfo.infoAES192F8F9.authKey0,
+ sizeof(F9_t));
+ break;
+ case XLR_SEC_VECTOR__CIPHER_AES256__F9__MODE_F8:
+ DPRINT("VECTOR: XLR_SEC_VECTOR__CIPHER_AES256__F9__MODE_F8 \n");
+ print_buf("CIPHER Key",
+ &desc->ctl_desc.cipherHashInfo.infoAES256F8F9.cipherKey0,
+ XLR_SEC_AES256F8_KEY_LENGTH);
+ print_buf("F9 Key",
+ &desc->ctl_desc.cipherHashInfo.infoAES256F8F9.authKey0,
+ sizeof(F9_t));
+ break;
+
+ default:
+ DPRINT("VECTOR: ???? \n");
+ DPRINT(">>> WHAT THE HECK !!! <<< \n");
+ break;
+ }
+ DPRINT("PACKET DESCRIPTOR: \n");
+ word = 0; //desc->pkt_desc.srcLengthIVOffUseIVNext;
+ DPRINT("\tSrcLengthIVOffsetIVNext: %llx\n", word);
+ DPRINT("\t\tLoad HMAC = %lld \n",
+ GET_FIELD(word, PKT_DSC_LOADHMACKEY));
+ DPRINT("\t\tPad Hash = %lld \n",
+ GET_FIELD(word, PKT_DSC_PADHASH));
+ DPRINT("\t\tHash Byte Count = %lld \n",
+ GET_FIELD(word, PKT_DSC_HASHBYTES));
+ DPRINT("\t\tNext = %lld \n",
+ GET_FIELD(word, PKT_DSC_NEXT));
+ DPRINT("\t\tUse IV = %lld \n",
+ GET_FIELD(word, PKT_DSC_IV));
+ DPRINT("\t\tIV Offset = %lld \n",
+ GET_FIELD(word, PKT_DSC_IVOFF));
+ DPRINT("\t\tPacket Length = %lld \n",
+ GET_FIELD(word, PKT_DSC_PKTLEN));
+ DPRINT("\t\tNLHMAC = %lld \n", GET_FIELD(word, PKT_DSC_NLHMAC));
+ DPRINT("\t\tBreak = %lld \n", GET_FIELD(word, PKT_DSC_BREAK));
+ DPRINT("\t\tWait = %lld \n", GET_FIELD(word, PKT_DSC_WAIT));
+ DPRINT("\t\tSegment Src Addr = %llx \n",
+ (GET_FIELD(word, PKT_DSC_SEGADDR) << 5) & 0xffffffffffULL);
+ DPRINT("\t\tSRTCP = %lld \n", GET_FIELD(word, PKT_DSC_SRTCP));
+ DPRINT("\t\tGlobal Src Offset = %lld \n",
+ GET_FIELD(word, PKT_DSC_SEGOFFSET));
+
+ word = 0; //desc->pkt_desc.dstDataSettings;
+ DPRINT("\tdstDataSettings: %llx \n", word);
+ DPRINT("\t\tArc4 Byte Count = %lld \n", GET_FIELD(word,
+ PKT_DSC_ARC4BYTECOUNT));
+ DPRINT("\t\tSym Operation = %lld \n", GET_FIELD(word, PKT_DSC_SYM_OP));
+ DPRINT("\t\tCipher Offset = %lld \n", GET_FIELD(word, PKT_DSC_CPHROFF));
+ DPRINT("\t\tHash Offset = %lld \n", GET_FIELD(word, PKT_DSC_HASHOFF));
+ DPRINT("\t\tHash Source = %lld \n", GET_FIELD(word, PKT_DSC_HASHSRC));
+ DPRINT("\t\tChecksum Offset = %lld \n", GET_FIELD(word,
+ PKT_DSC_CKSUMOFF));
+ DPRINT("\t\tChecksum Source = %lld \n", GET_FIELD(word,
+ PKT_DSC_CKSUMSRC));
+ DPRINT("\t\tCipher Dest Addr = %llx \n", GET_FIELD(word,
+ PKT_DSC_CPHR_DST_ADDR));
+ DPRINT("\t\tCipher Dest Dword = %lld \n", GET_FIELD(word,
+ PKT_DSC_CPHR_DST_DWOFFSET));
+ DPRINT("\t\tCipher Dest Offset= %lld \n", GET_FIELD(word,
+ PKT_DSC_CPHR_DST_OFFSET));
+ word = 0; //desc->pkt_desc.authDstNonceLow;
+ DPRINT("\tauthDstNonceLow: %llx \n", word);
+ DPRINT("\t\tNonce Low 24 = %lld \n", GET_FIELD(word,
+ PKT_DSC_NONCE_LOW));
+ DPRINT("\t\tauthDst = %llx \n", GET_FIELD(word,
+ PKT_DSC_AUTH_DST_ADDR));
+ DPRINT("\t\tCipher Offset High= %lld \n", GET_FIELD(word,
+ PKT_DSC_CIPH_OFF_HI));
+ word = 0; //desc->pkt_desc.ckSumDstNonceHiCFBMaskLLWMask;
+ DPRINT("\tckSumDstNonceHiCFBMaskLLWMask: %llx \n", word);
+ DPRINT("\t\tHash Byte off = %lld \n", GET_FIELD(word, PKT_DSC_HASH_BYTE_OFF));
+ DPRINT("\t\tPacket Len bytes = %lld \n", GET_FIELD(word, PKT_DSC_PKTLEN_BYTES));
+ DPRINT("\t\tLast Long Word Mask = %lld \n", GET_FIELD(word,
+ PKT_DSC_LASTWORD));
+ DPRINT("\t\tCipher Dst Address = %llx \n", GET_FIELD(word,
+ PKT_DSC_CPHR_DST_ADDR));
+ DPRINT("\t\tGlobal Dst Offset = %lld \n", GET_FIELD(word,
+ PKT_DSC_CPHR_DST_OFFSET));
+
+ DPRINT("CFG_VECTOR = %04x\n", cfg_vector);
+ DPRINT("\n\n");
+}
+
+#endif
+
+
+
+/* This function is called from an interrupt handler */
+void
+xlr_sec_msgring_handler(int bucket, int size, int code, int stid,
+ struct msgrng_msg *msg, void *data)
+{
+ uint64_t error;
+ uint64_t addr, sec_eng, sec_pipe;
+ xlr_sec_io_pt op = NULL;
+ symkey_desc_pt desc = NULL;
+ struct xlr_sec_session *ses = NULL;
+ struct xlr_sec_command *cmd = NULL;
+ uint32_t flags;
+
+ if (code != MSGRNG_CODE_SEC) {
+ panic("xlr_sec_msgring_handler: bad code = %d,"
+ " expected code = %d\n",
+ code, MSGRNG_CODE_SEC);
+ }
+ if ((stid < MSGRNG_STNID_SEC0) || (stid > MSGRNG_STNID_PK0)) {
+ panic("xlr_sec_msgring_handler: bad stn id = %d, expect %d - %d\n",
+ stid, MSGRNG_STNID_SEC0, MSGRNG_STNID_PK0);
+ }
+ /*
+ * The Submit() operation encodes the engine and pipe in these two
+ * separate fields. This allows use to verify the result type with
+ * the submitted operation type.
+ */
+ sec_eng = GET_FIELD(msg->msg0, MSG_CTL_OP_TYPE);
+ sec_pipe = GET_FIELD(msg->msg1, MSG_CTL_OP_TYPE);
+
+ error = msg->msg0 >> 40 & 0x1ff;
+ if (error)
+ printf("ctrl error = 0x%llx\n", error);
+ error = msg->msg1 >> 40 & 0x1ff;
+ if (error)
+ printf("data error = 0x%llx\n", error);
+
+
+ XLR_SEC_CMD_DIAG("[%s]: eng=%lld pipe=%lld\n",
+ __FUNCTION__, sec_eng, sec_pipe);
+
+ /* Symmetric Key Operation ? */
+ if (sec_eng == MSG0_CTL_OP_ENGINE_SYMKEY) {
+
+ /*
+ * The data descriptor address allows us to associate the
+ * response with the submitted operation. Address is 40-bit
+ * cacheline aligned address. We need to zero bit 0-4 since
+ * they are used for the engine and pipe Id.
+ */
+ addr = GET_FIELD(msg->msg1, MSG_RSLT_DATA_DSC_ADDR);
+ addr = addr & ~((1 << 5) - 1);
+ if (!addr) {
+ panic("[%s:STNID_SEC]: NULL symkey addr!\n", __FUNCTION__);
+ }
+
+ /*
+ * The adddress points to the data descriptor. The operation
+ * descriptor is defined with the 32-byte cacheline size in
+ * mind. It allows the code to use this address to
+ * reference the symkey descriptor. (ref: xlr_sec_desc.h)
+ */
+ addr = addr - sizeof(OperationDescriptor_t);
+ flags = xlr_enable_kx();
+ desc = (symkey_desc_pt)(uintptr_t)xlr_paddr_ld(addr +
+ offsetof(OperationDescriptor_t, vaddr));
+ xlr_restore_kx(flags);
+
+ if (!desc) {
+ printf("\nerror : not getting desc back correctly \n");
+ panic("[%s:STNID_SEC]: NULL symkey data descriptor!\n", __FUNCTION__);
+ }
+ ses = (struct xlr_sec_session *)desc->ses;
+ if (!ses) {
+ printf("\n error : not getting ses back correctly \n");
+ panic("[%s:STNID_SEC]: NULL symkey data descriptor!\n", __FUNCTION__);
+ }
+ cmd = &ses->cmd;
+ if (!cmd) {
+ printf("\n error : not getting cmd back correctly \n");
+ panic("[%s:STNID_SEC]: NULL symkey data descriptor!\n", __FUNCTION__);
+ }
+ op = &cmd->op;
+ if (!op) {
+ printf("\n error : not getting op back correctly \n");
+ panic("[%s:STNID_SEC]: NULL symkey data descriptor!\n", __FUNCTION__);
+ }
+ XLR_SEC_CMD_DIAG("[%s:STNID_SEC]: addr=0x%llx desc=%p alloc=%p \n",
+ __FUNCTION__, addr, desc, desc->alloc);
+
+ XLR_SEC_CMD_DIAG("[%s:STNID_SEC]: op_ctl=%p phys_self=%llx stn_id=%d \n",
+ __FUNCTION__, &desc->op_ctl, desc->op_ctl.phys_self,
+ desc->op_ctl.stn_id);
+
+ if (addr != desc->op_ctl.phys_self) {
+ XLR_SEC_CMD_DIAG("[%s:STNID_SEC]: Control Descriptor fails Self-Verify !\n",
+ __FUNCTION__);
+ printf("[%s:STNID_SEC]: Control Descriptor fails Self-Verify !\n",
+ __FUNCTION__);
+ printf("[%s:STNID_SEC]: addr=0x%llx desc=%p alloc=%p \n",
+ __FUNCTION__, (unsigned long long)addr, desc, desc->alloc);
+ printf("[%s:STNID_SEC]: op_ctl=%p phys_self=%llx stn_id=%d \n",
+ __FUNCTION__, &desc->op_ctl, (unsigned long long)desc->op_ctl.phys_self,
+ desc->op_ctl.stn_id);
+
+ }
+ if (desc->op_ctl.stn_id != MSGRNG_STNID_SEC0 &&
+ desc->op_ctl.stn_id != MSGRNG_STNID_SEC1) {
+ XLR_SEC_CMD_DIAG("[%s:STNID_SEC]: Operation Type Mismatch !\n",
+ __FUNCTION__);
+ printf("[%s:STNID_SEC]: Operation Type Mismatch !\n",
+ __FUNCTION__);
+ printf("[%s:STNID_SEC]: addr=0x%llx desc=%p alloc=%p \n",
+ __FUNCTION__, (unsigned long long)addr, desc, desc->alloc);
+ printf("[%s:STNID_SEC]: op_ctl=%p phys_self=%llx stn_id=%d \n",
+ __FUNCTION__, &desc->op_ctl, (unsigned long long)desc->op_ctl.phys_self,
+ desc->op_ctl.stn_id);
+ }
+ desc->ctl_result = GET_FIELD(msg->msg0, MSG_RSLT_CTL_INST_ERR);
+ desc->data_result = GET_FIELD(msg->msg1, MSG_RSLT_DATA_INST_ERR);
+
+ XLR_SEC_CMD_DIAG("[%s:STNID_SEC]: cpu=%d ctl_result=0x%llx data_result=%llx\n",
+ __FUNCTION__, desc->op_ctl.cpu,
+ desc->ctl_result, desc->data_result);
+
+ }
+#if 0
+ else if (sec_eng == MSG0_CTL_OP_ENGINE_PUBKEY) {
+ pubkey_desc_pt desc;
+
+ if (sec_pipe != MSG1_CTL_OP_PUBKEY_PIPE0) {
+ /* response to uc load */
+ /*
+ * XLR_SEC_CMD_DIAG("[%s:STNID_SEC]: ecc cpu=%d
+ * ctl_result=0x%llx data_result=%llx\n",
+ * __FUNCTION__, desc->op_ctl.cpu, desc->ctl_result,
+ * desc->data_result);
+ */
+ return;
+ }
+ /*
+ * The data descriptor address allows us to associate the
+ * response with the submitted operation. Address is 40-bit
+ * cacheline aligned address. We need to zero bit 0-4 since
+ * they are used for the engine and pipe Id.
+ */
+ addr = GET_FIELD(msg->msg0, PUBKEY_RSLT_CTL_SRCADDR);
+ addr = addr & ~((1 << 5) - 1);
+ if (!addr) {
+ panic("[%s:STNID_SEC]: NULL pubkey ctrl desc!\n", __FUNCTION__);
+ }
+ /*
+ * The adddress points to the data descriptor. The operation
+ * descriptor is defined with the 32-byte cacheline size in
+ * mind. It allows the code to use this address to
+ * reference the symkey descriptor. (ref: xlr_sec_desc.h)
+ */
+ addr = addr - sizeof(OperationDescriptor_t);
+
+ /* Get pointer to pubkey Descriptor */
+ desc = (pubkey_desc_pt) (unsigned long)addr;
+ if (!desc) {
+ panic("[%s:STNID_SEC]: NULL pubkey data descriptor!\n", __FUNCTION__);
+ }
+ XLR_SEC_CMD_DIAG("[%s:STNID_PK0]: addr=0x%llx desc=%p alloc=%p \n",
+ __FUNCTION__, addr, desc, desc->alloc);
+
+ XLR_SEC_CMD_DIAG("[%s:STNID_PK0]: op_ctl=%p phys_self=%llx stn_id=%d \n",
+ __FUNCTION__, &desc->op_ctl, desc->op_ctl.phys_self,
+ desc->op_ctl.stn_id);
+
+ if (addr != desc->op_ctl.phys_self) {
+ XLR_SEC_CMD_DIAG("[%s:STNID_PK0]: Control Descriptor fails Self-Verify !\n",
+ __FUNCTION__);
+ }
+ if (desc->op_ctl.stn_id != msgrng_stnid_pk0) {
+ XLR_SEC_CMD_DIAG("[%s:STNID_PK0]: Operation Type Mismatch ! \n",
+ __FUNCTION__);
+ }
+ desc->ctl_result = GET_FIELD(msg->msg0, PUBKEY_RSLT_CTL_ERROR);
+ desc->data_result = GET_FIELD(msg->msg1, PUBKEY_RSLT_DATA_ERROR);
+
+ XLR_SEC_CMD_DIAG("[%s:STNID_PK0]: ctl_result=0x%llx data_result=%llx\n",
+ __FUNCTION__, desc->ctl_result, desc->data_result);
+
+ }
+#endif
+ else {
+ printf("[%s]: HANDLER bad id = %d\n", __FUNCTION__, stid);
+ }
+#ifdef RMI_SEC_DEBUG
+ if (ses->multi_frag_flag) {
+ int i;
+ char *ptr;
+
+ printf("\n RETURNED DATA: \n");
+
+ ptr = (char *)(unsigned long)(desc->user.aligned_dest + cmd->op.cipher_offset);
+ for (i = 0; i < SEC_MAX_FRAG_LEN; i++) {
+ printf("%c ", (char)*ptr++);
+ if ((i % 10) == 0)
+ printf("\n");
+ }
+
+ printf("second desc\n");
+ ptr = (char *)(unsigned long)(desc->next_dest_buf);
+ for (i = 0; i < desc->next_src_len; i++) {
+ printf("%c ", (char)*ptr++);
+ if ((i % 10) == 0)
+ printf("\n");
+ }
+ }
+#endif
+
+ /* Copy cipher-data to User-space */
+ if (op->cipher_type != XLR_SEC_CIPHER_TYPE_NONE) {
+ size = op->dest_buf_size;
+
+ /* DEBUG -dpk */
+ XLR_SEC_CMD_DIAG("cipher: to_addr=%p from_addr=%p size=%d \n",
+ desc->user.user_dest, desc->user.aligned_dest, size);
+
+ if (ses->multi_frag_flag) {
+ crypto_copyback(cmd->crp->crp_flags, cmd->crp->crp_buf, 0,
+ SEC_MAX_FRAG_LEN, (caddr_t)(long)desc->user.aligned_dest + op->cipher_offset);
+ crypto_copyback(cmd->crp->crp_flags, cmd->crp->crp_buf + SEC_MAX_FRAG_LEN, 0,
+ desc->next_src_len, (caddr_t)(long)desc->next_dest_buf);
+ crypto_done(cmd->crp);
+ } else {
+ crypto_copyback(cmd->crp->crp_flags, cmd->crp->crp_buf, 0,
+ cmd->op.dest_buf_size, (caddr_t)(long)desc->user.aligned_dest + op->cipher_offset);
+ crypto_done(cmd->crp);
+ }
+
+ }
+
+ /* Copy digest to User-space */
+ if (op->digest_type != XLR_SEC_DIGEST_TYPE_NONE) {
+ int offset = 0;
+
+ switch (op->digest_type) {
+ case XLR_SEC_DIGEST_TYPE_MD5:
+ size = XLR_SEC_MD5_LENGTH;
+ break;
+ case XLR_SEC_DIGEST_TYPE_SHA1:
+ size = XLR_SEC_SHA1_LENGTH;
+ break;
+ case XLR_SEC_DIGEST_TYPE_SHA256:
+ size = XLR_SEC_SHA256_LENGTH;
+ break;
+ case XLR_SEC_DIGEST_TYPE_SHA384:
+ size = XLR_SEC_SHA384_LENGTH;
+ break;
+ case XLR_SEC_DIGEST_TYPE_SHA512:
+ size = XLR_SEC_SHA512_LENGTH;
+ break;
+ case XLR_SEC_DIGEST_TYPE_GCM:
+ size = XLR_SEC_GCM_LENGTH;
+ break;
+ case XLR_SEC_DIGEST_TYPE_KASUMI_F9:
+ offset = 4;
+ size = XLR_SEC_KASUMI_F9_RESULT_LENGTH;
+ break;
+ default:
+ size = 0;
+ }
+
+ XLR_SEC_CMD_DIAG("digest: to_addr=%p from_addr=%p size=%d \n",
+ desc->user.user_auth, desc->user.aligned_auth, size);
+ memcpy(desc->user.user_auth, desc->user.aligned_auth + offset, size);
+ op->auth_dest = (uint64_t) (unsigned long)desc->user.user_auth;
+ }
+ if (op->cipher_type == XLR_SEC_CIPHER_TYPE_ARC4 &&
+ op->rc4_savestate) {
+ size = XLR_SEC_MAX_RC4_STATE_SIZE;
+
+ XLR_SEC_CMD_DIAG("state: to_addr=%p from_addr=%p size=%d \n",
+ desc->user.user_state, desc->user.aligned_state, size);
+ op->rc4_state = (uint64_t) (unsigned long)desc->user.user_state;
+ }
+ return;
+}
Property changes on: trunk/sys/mips/rmi/dev/sec/rmilib.c
___________________________________________________________________
Added: svn:eol-style
## -0,0 +1 ##
+native
\ No newline at end of property
Added: svn:keywords
## -0,0 +1 ##
+MidnightBSD=%H
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+text/plain
\ No newline at end of property
Added: trunk/sys/mips/rmi/dev/sec/rmilib.h
===================================================================
--- trunk/sys/mips/rmi/dev/sec/rmilib.h (rev 0)
+++ trunk/sys/mips/rmi/dev/sec/rmilib.h 2018-05-26 21:55:02 UTC (rev 9987)
@@ -0,0 +1,1001 @@
+/* $MidnightBSD$ */
+/*-
+ * Copyright (c) 2003-2009 RMI Corporation
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * 3. Neither the name of RMI Corporation, nor the names of its contributors,
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ * $FreeBSD: stable/10/sys/mips/rmi/dev/sec/rmilib.h 212763 2010-09-16 20:23:22Z jchandra $
+ * RMI_BSD
+ */
+
+#ifndef _RMILIB_H_
+#define _RMILIB_H_
+
+#include <sys/cdefs.h>
+#include <mips/rmi/dev/sec/desc.h>
+#include <mips/rmi/iomap.h>
+
+/* #define XLR_SEC_CMD_DEBUG */
+
+#ifdef XLR_SEC_CMD_DEBUG
+#define DPRINT printf
+#define XLR_SEC_CMD_DIAG(fmt, args...) { \
+ DPRINT(fmt, ##args); \
+ }
+#define XLR_SEC_CMD_DIAG_SYM_DESC(desc, vec) { \
+ decode_symkey_desc ((desc), (vec)); \
+ }
+#else
+#define DPRINT(fmt, args...)
+#define XLR_SEC_CMD_DIAG(fmt, args...)
+#define XLR_SEC_CMD_DIAG_SYM_DESC(desc, vec)
+#endif
+
+
+
+
+
+
+/*
+#include <mips/include/pmap.h>
+
+#define OS_ALLOC_KERNEL(size) kmalloc((size), GFP_KERNEL)
+#define virt_to_phys(x) vtophys((vm_offset_t)(x))
+*/
+/*
+ * Cryptographic parameter definitions
+ */
+#define XLR_SEC_DES_KEY_LENGTH 8 /* Bytes */
+#define XLR_SEC_3DES_KEY_LENGTH 24 /* Bytes */
+#define XLR_SEC_AES128_KEY_LENGTH 16 /* Bytes */
+#define XLR_SEC_AES192_KEY_LENGTH 24 /* Bytes */
+#define XLR_SEC_AES256_KEY_LENGTH 32 /* Bytes */
+#define XLR_SEC_AES128F8_KEY_LENGTH 32 /* Bytes */
+#define XLR_SEC_AES192F8_KEY_LENGTH 48 /* Bytes */
+#define XLR_SEC_AES256F8_KEY_LENGTH 64 /* Bytes */
+#define XLR_SEC_KASUMI_F8_KEY_LENGTH 16 /* Bytes */
+#define XLR_SEC_MAX_CRYPT_KEY_LENGTH XLR_SEC_AES256F8_KEY_LENGTH
+
+
+#define XLR_SEC_DES_IV_LENGTH 8 /* Bytes */
+#define XLR_SEC_AES_IV_LENGTH 16 /* Bytes */
+#define XLR_SEC_ARC4_IV_LENGTH 0 /* Bytes */
+#define XLR_SEC_KASUMI_F8_IV_LENGTH 16 /* Bytes */
+#define XLR_SEC_MAX_IV_LENGTH 16 /* Bytes */
+#define XLR_SEC_IV_LENGTH_BYTES 8 /* Bytes */
+
+#define XLR_SEC_AES_BLOCK_SIZE 16 /* Bytes */
+#define XLR_SEC_DES_BLOCK_SIZE 8 /* Bytes */
+#define XLR_SEC_3DES_BLOCK_SIZE 8 /* Bytes */
+
+#define XLR_SEC_MD5_BLOCK_SIZE 64 /* Bytes */
+#define XLR_SEC_SHA1_BLOCK_SIZE 64 /* Bytes */
+#define XLR_SEC_SHA256_BLOCK_SIZE 64 /* Bytes */
+#define XLR_SEC_SHA384_BLOCK_SIZE 128 /* Bytes */
+#define XLR_SEC_SHA512_BLOCK_SIZE 128 /* Bytes */
+#define XLR_SEC_GCM_BLOCK_SIZE 16 /* XXX: Bytes */
+#define XLR_SEC_KASUMI_F9_BLOCK_SIZE 16 /* XXX: Bytes */
+#define XLR_SEC_MAX_BLOCK_SIZE 64 /* Max of MD5/SHA */
+#define XLR_SEC_MD5_LENGTH 16 /* Bytes */
+#define XLR_SEC_SHA1_LENGTH 20 /* Bytes */
+#define XLR_SEC_SHA256_LENGTH 32 /* Bytes */
+#define XLR_SEC_SHA384_LENGTH 64 /* Bytes */
+#define XLR_SEC_SHA512_LENGTH 64 /* Bytes */
+#define XLR_SEC_GCM_LENGTH 16 /* Bytes */
+#define XLR_SEC_KASUMI_F9_LENGTH 16 /* Bytes */
+#define XLR_SEC_KASUMI_F9_RESULT_LENGTH 4 /* Bytes */
+#define XLR_SEC_HMAC_LENGTH 64 /* Max of MD5/SHA/SHA256 */
+#define XLR_SEC_MAX_AUTH_KEY_LENGTH XLR_SEC_SHA512_BLOCK_SIZE
+#define XLR_SEC_MAX_RC4_STATE_SIZE 264 /* char s[256], int i, int j */
+
+/* Status code is used by the SRL to indicate status */
+typedef unsigned int xlr_sec_status_t;
+
+/*
+ * Status codes
+ */
+#define XLR_SEC_STATUS_SUCCESS 0
+#define XLR_SEC_STATUS_NO_DEVICE -1
+#define XLR_SEC_STATUS_TIMEOUT -2
+#define XLR_SEC_STATUS_INVALID_PARAMETER -3
+#define XLR_SEC_STATUS_DEVICE_FAILED -4
+#define XLR_SEC_STATUS_DEVICE_BUSY -5
+#define XLR_SEC_STATUS_NO_RESOURCE -6
+#define XLR_SEC_STATUS_CANCELLED -7
+
+/*
+ * Flags
+ */
+#define XLR_SEC_FLAGS_HIGH_PRIORITY 1
+
+/* Error code is used to indicate any errors */
+typedef int xlr_sec_error_t;
+
+/*
+ */
+#define XLR_SEC_ERR_NONE 0
+#define XLR_SEC_ERR_CIPHER_OP -1
+#define XLR_SEC_ERR_CIPHER_TYPE -2
+#define XLR_SEC_ERR_CIPHER_MODE -3
+#define XLR_SEC_ERR_CIPHER_INIT -4
+#define XLR_SEC_ERR_DIGEST_TYPE -5
+#define XLR_SEC_ERR_DIGEST_INIT -6
+#define XLR_SEC_ERR_DIGEST_SRC -7
+#define XLR_SEC_ERR_CKSUM_TYPE -8
+#define XLR_SEC_ERR_CKSUM_SRC -9
+#define XLR_SEC_ERR_ALLOC -10
+#define XLR_SEC_ERR_CONTROL_VECTOR -11
+#define XLR_SEC_ERR_LOADHMACKEY_MODE -12
+#define XLR_SEC_ERR_PADHASH_MODE -13
+#define XLR_SEC_ERR_HASHBYTES_MODE -14
+#define XLR_SEC_ERR_NEXT_MODE -15
+#define XLR_SEC_ERR_PKT_IV_MODE -16
+#define XLR_SEC_ERR_LASTWORD_MODE -17
+#define XLR_SEC_ERR_PUBKEY_OP -18
+#define XLR_SEC_ERR_SYMKEY_MSGSND -19
+#define XLR_SEC_ERR_PUBKEY_MSGSND -20
+#define XLR_SEC_ERR_SYMKEY_GETSEM -21
+#define XLR_SEC_ERR_PUBKEY_GETSEM -22
+
+/*
+ * Descriptor Vector quantities
+ * (helps to identify descriptor type per operation)
+ */
+#define XLR_SEC_VECTOR_CIPHER_DES 0x0001
+#define XLR_SEC_VECTOR_CIPHER_3DES 0x0002
+#define XLR_SEC_VECTOR_CIPHER_AES128 0x0004
+#define XLR_SEC_VECTOR_CIPHER_AES192 0x0008
+#define XLR_SEC_VECTOR_CIPHER_AES256 0x0010
+#define XLR_SEC_VECTOR_CIPHER_ARC4 0x0020
+#define XLR_SEC_VECTOR_CIPHER_AES (XLR_SEC_VECTOR_CIPHER_AES128 | \
+ XLR_SEC_VECTOR_CIPHER_AES192 | \
+ XLR_SEC_VECTOR_CIPHER_AES256)
+#define XLR_SEC_VECTOR_CIPHER (XLR_SEC_VECTOR_CIPHER_DES | \
+ XLR_SEC_VECTOR_CIPHER_3DES | \
+ XLR_SEC_VECTOR_CIPHER_AES128 | \
+ XLR_SEC_VECTOR_CIPHER_AES192 | \
+ XLR_SEC_VECTOR_CIPHER_AES256 | \
+ XLR_SEC_VECTOR_CIPHER_ARC4)
+
+#define XLR_SEC_VECTOR_HMAC 0x0040
+#define XLR_SEC_VECTOR_MAC 0x0080
+#define XLR_SEC_VECTOR_MODE_CTR_CFB 0x0100
+#define XLR_SEC_VECTOR_MODE_ECB_CBC_OFB 0x0200
+#define XLR_SEC_VECTOR_MODE_ECB_CBC 0x0400
+#define XLR_SEC_VECTOR_STATE 0x0800
+#define XLR_SEC_VECTOR_CIPHER_KASUMI_F8 0x01000
+#define XLR_SEC_VECTOR_HMAC2 0x02000
+#define XLR_SEC_VECTOR_GCM 0x04000
+#define XLR_SEC_VECTOR_F9 0x08000
+#define XLR_SEC_VECTOR_MODE_F8 0x10000
+
+#define XLR_SEC_VECTOR_CIPHER_ARC4__HMAC \
+(XLR_SEC_VECTOR_CIPHER_ARC4 | XLR_SEC_VECTOR_HMAC)
+#define XLR_SEC_VECTOR_CIPHER_ARC4__STATE \
+(XLR_SEC_VECTOR_CIPHER_ARC4 | XLR_SEC_VECTOR_STATE)
+#define XLR_SEC_VECTOR_CIPHER_ARC4__HMAC__STATE \
+(XLR_SEC_VECTOR_CIPHER_ARC4 | XLR_SEC_VECTOR_HMAC | XLR_SEC_VECTOR_STATE)
+
+#define XLR_SEC_VECTOR__CIPHER_DES__HMAC__MODE_ECB_CBC \
+(XLR_SEC_VECTOR_CIPHER_DES | XLR_SEC_VECTOR_HMAC | XLR_SEC_VECTOR_MODE_ECB_CBC)
+
+#define XLR_SEC_VECTOR__CIPHER_DES__MODE_ECB_CBC \
+(XLR_SEC_VECTOR_CIPHER_DES | XLR_SEC_VECTOR_MODE_ECB_CBC)
+
+#define XLR_SEC_VECTOR__CIPHER_3DES__HMAC__MODE_ECB_CBC \
+(XLR_SEC_VECTOR_CIPHER_3DES | XLR_SEC_VECTOR_HMAC | XLR_SEC_VECTOR_MODE_ECB_CBC)
+
+#define XLR_SEC_VECTOR__CIPHER_3DES__MODE_ECB_CBC \
+(XLR_SEC_VECTOR_CIPHER_3DES | XLR_SEC_VECTOR_MODE_ECB_CBC)
+
+#define XLR_SEC_VECTOR__CIPHER_AES128__HMAC__MODE_CTR_CFB \
+(XLR_SEC_VECTOR_CIPHER_AES128 | XLR_SEC_VECTOR_HMAC | XLR_SEC_VECTOR_MODE_CTR_CFB)
+
+#define XLR_SEC_VECTOR__CIPHER_AES128__MODE_CTR_CFB \
+(XLR_SEC_VECTOR_CIPHER_AES128 | XLR_SEC_VECTOR_MODE_CTR_CFB)
+
+#define XLR_SEC_VECTOR__CIPHER_AES128__HMAC__MODE_ECB_CBC_OFB \
+(XLR_SEC_VECTOR_CIPHER_AES128 | XLR_SEC_VECTOR_HMAC | XLR_SEC_VECTOR_MODE_ECB_CBC_OFB)
+
+#define XLR_SEC_VECTOR__CIPHER_AES128__MODE_ECB_CBC_OFB \
+(XLR_SEC_VECTOR_CIPHER_AES128 | XLR_SEC_VECTOR_MODE_ECB_CBC_OFB)
+
+#define XLR_SEC_VECTOR__CIPHER_AES192__HMAC__MODE_CTR_CFB \
+(XLR_SEC_VECTOR_CIPHER_AES192 | XLR_SEC_VECTOR_HMAC | XLR_SEC_VECTOR_MODE_CTR_CFB)
+
+#define XLR_SEC_VECTOR__CIPHER_AES192__MODE_CTR_CFB \
+(XLR_SEC_VECTOR_CIPHER_AES192 | XLR_SEC_VECTOR_MODE_CTR_CFB)
+
+#define XLR_SEC_VECTOR__CIPHER_AES192__HMAC__MODE_ECB_CBC_OFB \
+(XLR_SEC_VECTOR_CIPHER_AES192 | XLR_SEC_VECTOR_HMAC | XLR_SEC_VECTOR_MODE_ECB_CBC_OFB)
+
+#define XLR_SEC_VECTOR__CIPHER_AES192__MODE_ECB_CBC_OFB \
+(XLR_SEC_VECTOR_CIPHER_AES192 | XLR_SEC_VECTOR_MODE_ECB_CBC_OFB)
+
+#define XLR_SEC_VECTOR__CIPHER_AES256__HMAC__MODE_CTR_CFB \
+(XLR_SEC_VECTOR_CIPHER_AES256 | XLR_SEC_VECTOR_HMAC | XLR_SEC_VECTOR_MODE_CTR_CFB)
+
+#define XLR_SEC_VECTOR__CIPHER_AES256__MODE_CTR_CFB \
+(XLR_SEC_VECTOR_CIPHER_AES256 | XLR_SEC_VECTOR_MODE_CTR_CFB)
+
+#define XLR_SEC_VECTOR__CIPHER_AES256__HMAC__MODE_ECB_CBC_OFB \
+(XLR_SEC_VECTOR_CIPHER_AES256 | XLR_SEC_VECTOR_HMAC | XLR_SEC_VECTOR_MODE_ECB_CBC_OFB)
+
+#define XLR_SEC_VECTOR__CIPHER_AES256__MODE_ECB_CBC_OFB \
+(XLR_SEC_VECTOR_CIPHER_AES256 | XLR_SEC_VECTOR_MODE_ECB_CBC_OFB)
+
+#define XLR_SEC_VECTOR__CIPHER_AES128__HMAC__MODE_F8 \
+(XLR_SEC_VECTOR_CIPHER_AES128 | XLR_SEC_VECTOR_HMAC | XLR_SEC_VECTOR_MODE_F8)
+
+#define XLR_SEC_VECTOR__CIPHER_AES128__MODE_F8 \
+(XLR_SEC_VECTOR_CIPHER_AES128 | XLR_SEC_VECTOR_MODE_F8)
+
+#define XLR_SEC_VECTOR__CIPHER_AES192__HMAC__MODE_F8 \
+(XLR_SEC_VECTOR_CIPHER_AES192 | XLR_SEC_VECTOR_HMAC | XLR_SEC_VECTOR_MODE_F8)
+
+#define XLR_SEC_VECTOR__CIPHER_AES192__MODE_F8 \
+(XLR_SEC_VECTOR_CIPHER_AES192 | XLR_SEC_VECTOR_MODE_F8)
+
+#define XLR_SEC_VECTOR__CIPHER_AES256__HMAC__MODE_F8 \
+(XLR_SEC_VECTOR_CIPHER_AES256 | XLR_SEC_VECTOR_HMAC | XLR_SEC_VECTOR_MODE_F8)
+
+#define XLR_SEC_VECTOR__CIPHER_AES256__MODE_F8 \
+(XLR_SEC_VECTOR_CIPHER_AES256 | XLR_SEC_VECTOR_MODE_F8)
+
+#define XLR_SEC_VECTOR_CIPHER_KASUMI_F8__F9 \
+(XLR_SEC_VECTOR_CIPHER_KASUMI_F8 | XLR_SEC_VECTOR_F9)
+
+#define XLR_SEC_VECTOR_CIPHER_KASUMI_F8__HMAC \
+(XLR_SEC_VECTOR_CIPHER_KASUMI_F8 | XLR_SEC_VECTOR_HMAC)
+
+#define XLR_SEC_VECTOR_CIPHER_KASUMI_F8__HMAC2 \
+(XLR_SEC_VECTOR_CIPHER_KASUMI_F8 | XLR_SEC_VECTOR_HMAC2)
+
+#define XLR_SEC_VECTOR_CIPHER_KASUMI_F8__GCM \
+(XLR_SEC_VECTOR_CIPHER_KASUMI_F8 | XLR_SEC_VECTOR_GCM)
+
+#define XLR_SEC_VECTOR_CIPHER_ARC4__HMAC2 \
+(XLR_SEC_VECTOR_CIPHER_ARC4 | XLR_SEC_VECTOR_HMAC2)
+
+#define XLR_SEC_VECTOR_CIPHER_ARC4__HMAC2__STATE \
+(XLR_SEC_VECTOR_CIPHER_ARC4 | XLR_SEC_VECTOR_HMAC2 | XLR_SEC_VECTOR_STATE)
+
+#define XLR_SEC_VECTOR__CIPHER_DES__HMAC2__MODE_ECB_CBC \
+(XLR_SEC_VECTOR_CIPHER_DES | XLR_SEC_VECTOR_HMAC2 | XLR_SEC_VECTOR_MODE_ECB_CBC)
+
+#define XLR_SEC_VECTOR__CIPHER_3DES__HMAC2__MODE_ECB_CBC \
+(XLR_SEC_VECTOR_CIPHER_3DES | XLR_SEC_VECTOR_HMAC2 | XLR_SEC_VECTOR_MODE_ECB_CBC)
+
+#define XLR_SEC_VECTOR__CIPHER_AES128__HMAC2__MODE_CTR_CFB \
+(XLR_SEC_VECTOR_CIPHER_AES128 | XLR_SEC_VECTOR_HMAC2 | XLR_SEC_VECTOR_MODE_CTR_CFB)
+
+#define XLR_SEC_VECTOR__CIPHER_AES128__HMAC2__MODE_ECB_CBC_OFB \
+(XLR_SEC_VECTOR_CIPHER_AES128 | XLR_SEC_VECTOR_HMAC2 | XLR_SEC_VECTOR_MODE_ECB_CBC_OFB)
+
+#define XLR_SEC_VECTOR__CIPHER_AES192__HMAC2__MODE_CTR_CFB \
+(XLR_SEC_VECTOR_CIPHER_AES192 | XLR_SEC_VECTOR_HMAC2 | XLR_SEC_VECTOR_MODE_CTR_CFB)
+
+#define XLR_SEC_VECTOR__CIPHER_AES192__HMAC2__MODE_ECB_CBC_OFB \
+(XLR_SEC_VECTOR_CIPHER_AES192 | XLR_SEC_VECTOR_HMAC2 | XLR_SEC_VECTOR_MODE_ECB_CBC_OFB)
+
+#define XLR_SEC_VECTOR__CIPHER_AES256__HMAC2__MODE_CTR_CFB \
+(XLR_SEC_VECTOR_CIPHER_AES256 | XLR_SEC_VECTOR_HMAC2 | XLR_SEC_VECTOR_MODE_CTR_CFB)
+
+#define XLR_SEC_VECTOR__CIPHER_AES256__HMAC2__MODE_ECB_CBC_OFB \
+(XLR_SEC_VECTOR_CIPHER_AES256 | XLR_SEC_VECTOR_HMAC2 | XLR_SEC_VECTOR_MODE_ECB_CBC_OFB)
+
+#define XLR_SEC_VECTOR__CIPHER_AES128__HMAC2__MODE_F8 \
+(XLR_SEC_VECTOR_CIPHER_AES128 | XLR_SEC_VECTOR_HMAC2 | XLR_SEC_VECTOR_MODE_F8)
+
+#define XLR_SEC_VECTOR__CIPHER_AES192__HMAC2__MODE_F8 \
+(XLR_SEC_VECTOR_CIPHER_AES192 | XLR_SEC_VECTOR_HMAC2 | XLR_SEC_VECTOR_MODE_F8)
+
+#define XLR_SEC_VECTOR__CIPHER_AES256__HMAC2__MODE_F8 \
+(XLR_SEC_VECTOR_CIPHER_AES256 | XLR_SEC_VECTOR_HMAC2 | XLR_SEC_VECTOR_MODE_F8)
+
+#define XLR_SEC_VECTOR_CIPHER_ARC4__GCM \
+(XLR_SEC_VECTOR_CIPHER_ARC4 | XLR_SEC_VECTOR_GCM)
+
+#define XLR_SEC_VECTOR_CIPHER_ARC4__GCM__STATE \
+(XLR_SEC_VECTOR_CIPHER_ARC4 | XLR_SEC_VECTOR_GCM | XLR_SEC_VECTOR_STATE)
+
+#define XLR_SEC_VECTOR__CIPHER_DES__GCM__MODE_ECB_CBC \
+(XLR_SEC_VECTOR_CIPHER_DES | XLR_SEC_VECTOR_GCM | XLR_SEC_VECTOR_MODE_ECB_CBC)
+
+#define XLR_SEC_VECTOR__CIPHER_3DES__GCM__MODE_ECB_CBC \
+(XLR_SEC_VECTOR_CIPHER_3DES | XLR_SEC_VECTOR_GCM | XLR_SEC_VECTOR_MODE_ECB_CBC)
+
+#define XLR_SEC_VECTOR__CIPHER_AES128__GCM__MODE_CTR_CFB \
+(XLR_SEC_VECTOR_CIPHER_AES128 | XLR_SEC_VECTOR_GCM | XLR_SEC_VECTOR_MODE_CTR_CFB)
+
+#define XLR_SEC_VECTOR__CIPHER_AES128__GCM__MODE_ECB_CBC_OFB \
+(XLR_SEC_VECTOR_CIPHER_AES128 | XLR_SEC_VECTOR_GCM | XLR_SEC_VECTOR_MODE_ECB_CBC_OFB)
+
+#define XLR_SEC_VECTOR__CIPHER_AES192__GCM__MODE_CTR_CFB \
+(XLR_SEC_VECTOR_CIPHER_AES192 | XLR_SEC_VECTOR_GCM | XLR_SEC_VECTOR_MODE_CTR_CFB)
+
+#define XLR_SEC_VECTOR__CIPHER_AES192__GCM__MODE_ECB_CBC_OFB \
+(XLR_SEC_VECTOR_CIPHER_AES192 | XLR_SEC_VECTOR_GCM | XLR_SEC_VECTOR_MODE_ECB_CBC_OFB)
+
+#define XLR_SEC_VECTOR__CIPHER_AES256__GCM__MODE_CTR_CFB \
+(XLR_SEC_VECTOR_CIPHER_AES256 | XLR_SEC_VECTOR_GCM | XLR_SEC_VECTOR_MODE_CTR_CFB)
+
+#define XLR_SEC_VECTOR__CIPHER_AES256__GCM__MODE_ECB_CBC_OFB \
+(XLR_SEC_VECTOR_CIPHER_AES256 | XLR_SEC_VECTOR_GCM | XLR_SEC_VECTOR_MODE_ECB_CBC_OFB)
+
+#define XLR_SEC_VECTOR__CIPHER_AES128__GCM__MODE_F8 \
+(XLR_SEC_VECTOR_CIPHER_AES128 | XLR_SEC_VECTOR_GCM | XLR_SEC_VECTOR_MODE_F8)
+
+#define XLR_SEC_VECTOR__CIPHER_AES192__GCM__MODE_F8 \
+(XLR_SEC_VECTOR_CIPHER_AES192 | XLR_SEC_VECTOR_GCM | XLR_SEC_VECTOR_MODE_F8)
+
+#define XLR_SEC_VECTOR__CIPHER_AES256__GCM__MODE_F8 \
+(XLR_SEC_VECTOR_CIPHER_AES256 | XLR_SEC_VECTOR_GCM | XLR_SEC_VECTOR_MODE_F8)
+
+#define XLR_SEC_VECTOR_CIPHER_ARC4__F9 \
+(XLR_SEC_VECTOR_CIPHER_ARC4 | XLR_SEC_VECTOR_F9)
+
+#define XLR_SEC_VECTOR_CIPHER_ARC4__F9__STATE \
+(XLR_SEC_VECTOR_CIPHER_ARC4 | XLR_SEC_VECTOR_F9 | XLR_SEC_VECTOR_STATE)
+
+#define XLR_SEC_VECTOR__CIPHER_DES__F9__MODE_ECB_CBC \
+(XLR_SEC_VECTOR_CIPHER_DES | XLR_SEC_VECTOR_F9 | XLR_SEC_VECTOR_MODE_ECB_CBC)
+
+#define XLR_SEC_VECTOR__CIPHER_3DES__F9__MODE_ECB_CBC \
+(XLR_SEC_VECTOR_CIPHER_3DES | XLR_SEC_VECTOR_F9 | XLR_SEC_VECTOR_MODE_ECB_CBC)
+
+#define XLR_SEC_VECTOR__CIPHER_AES128__F9__MODE_CTR_CFB \
+(XLR_SEC_VECTOR_CIPHER_AES128 | XLR_SEC_VECTOR_F9 | XLR_SEC_VECTOR_MODE_CTR_CFB)
+
+#define XLR_SEC_VECTOR__CIPHER_AES128__F9__MODE_ECB_CBC_OFB \
+(XLR_SEC_VECTOR_CIPHER_AES128 | XLR_SEC_VECTOR_F9 | XLR_SEC_VECTOR_MODE_ECB_CBC_OFB)
+
+#define XLR_SEC_VECTOR__CIPHER_AES192__F9__MODE_CTR_CFB \
+(XLR_SEC_VECTOR_CIPHER_AES192 | XLR_SEC_VECTOR_F9 | XLR_SEC_VECTOR_MODE_CTR_CFB)
+
+#define XLR_SEC_VECTOR__CIPHER_AES192__F9__MODE_ECB_CBC_OFB \
+(XLR_SEC_VECTOR_CIPHER_AES192 | XLR_SEC_VECTOR_F9 | XLR_SEC_VECTOR_MODE_ECB_CBC_OFB)
+
+#define XLR_SEC_VECTOR__CIPHER_AES256__F9__MODE_CTR_CFB \
+(XLR_SEC_VECTOR_CIPHER_AES256 | XLR_SEC_VECTOR_F9 | XLR_SEC_VECTOR_MODE_CTR_CFB)
+
+#define XLR_SEC_VECTOR__CIPHER_AES256__F9__MODE_ECB_CBC_OFB \
+(XLR_SEC_VECTOR_CIPHER_AES256 | XLR_SEC_VECTOR_F9 | XLR_SEC_VECTOR_MODE_ECB_CBC_OFB)
+
+#define XLR_SEC_VECTOR__CIPHER_AES128__F9__MODE_F8 \
+(XLR_SEC_VECTOR_CIPHER_AES128 | XLR_SEC_VECTOR_F9 | XLR_SEC_VECTOR_MODE_F8)
+
+#define XLR_SEC_VECTOR__CIPHER_AES192__F9__MODE_F8 \
+(XLR_SEC_VECTOR_CIPHER_AES192 | XLR_SEC_VECTOR_F9 | XLR_SEC_VECTOR_MODE_F8)
+
+#define XLR_SEC_VECTOR__CIPHER_AES256__F9__MODE_F8 \
+(XLR_SEC_VECTOR_CIPHER_AES256 | XLR_SEC_VECTOR_F9 | XLR_SEC_VECTOR_MODE_F8)
+
+/*
+ * Cipher Modes
+ */
+typedef enum {
+ XLR_SEC_CIPHER_MODE_NONE = 0,
+ XLR_SEC_CIPHER_MODE_PASS = 1,
+ XLR_SEC_CIPHER_MODE_ECB,
+ XLR_SEC_CIPHER_MODE_CBC,
+ XLR_SEC_CIPHER_MODE_OFB,
+ XLR_SEC_CIPHER_MODE_CTR,
+ XLR_SEC_CIPHER_MODE_CFB,
+ XLR_SEC_CIPHER_MODE_F8
+} XLR_SEC_CIPHER_MODE;
+
+typedef enum {
+ XLR_SEC_CIPHER_OP_NONE = 0,
+ XLR_SEC_CIPHER_OP_ENCRYPT = 1,
+ XLR_SEC_CIPHER_OP_DECRYPT
+} XLR_SEC_CIPHER_OP;
+
+typedef enum {
+ XLR_SEC_CIPHER_TYPE_UNSUPPORTED = -1,
+ XLR_SEC_CIPHER_TYPE_NONE = 0,
+ XLR_SEC_CIPHER_TYPE_DES,
+ XLR_SEC_CIPHER_TYPE_3DES,
+ XLR_SEC_CIPHER_TYPE_AES128,
+ XLR_SEC_CIPHER_TYPE_AES192,
+ XLR_SEC_CIPHER_TYPE_AES256,
+ XLR_SEC_CIPHER_TYPE_ARC4,
+ XLR_SEC_CIPHER_TYPE_KASUMI_F8
+} XLR_SEC_CIPHER_TYPE;
+
+typedef enum {
+ XLR_SEC_CIPHER_INIT_OK = 1, /* Preserve old Keys */
+ XLR_SEC_CIPHER_INIT_NK /* Load new Keys */
+} XLR_SEC_CIPHER_INIT;
+
+
+/*
+ * Hash Modes
+ */
+typedef enum {
+ XLR_SEC_DIGEST_TYPE_UNSUPPORTED = -1,
+ XLR_SEC_DIGEST_TYPE_NONE = 0,
+ XLR_SEC_DIGEST_TYPE_MD5,
+ XLR_SEC_DIGEST_TYPE_SHA1,
+ XLR_SEC_DIGEST_TYPE_SHA256,
+ XLR_SEC_DIGEST_TYPE_SHA384,
+ XLR_SEC_DIGEST_TYPE_SHA512,
+ XLR_SEC_DIGEST_TYPE_GCM,
+ XLR_SEC_DIGEST_TYPE_KASUMI_F9,
+ XLR_SEC_DIGEST_TYPE_HMAC_MD5,
+ XLR_SEC_DIGEST_TYPE_HMAC_SHA1,
+ XLR_SEC_DIGEST_TYPE_HMAC_SHA256,
+ XLR_SEC_DIGEST_TYPE_HMAC_SHA384,
+ XLR_SEC_DIGEST_TYPE_HMAC_SHA512,
+ XLR_SEC_DIGEST_TYPE_HMAC_AES_CBC,
+ XLR_SEC_DIGEST_TYPE_HMAC_AES_XCBC
+} XLR_SEC_DIGEST_TYPE;
+
+typedef enum {
+ XLR_SEC_DIGEST_INIT_OLDKEY = 1, /* Preserve old key HMAC key stored in
+ * ID registers (moot if HASH.HMAC ==
+ * 0) */
+ XLR_SEC_DIGEST_INIT_NEWKEY /* Load new HMAC key from memory ctrl
+ * section to ID registers */
+} XLR_SEC_DIGEST_INIT;
+
+typedef enum {
+ XLR_SEC_DIGEST_SRC_DMA = 1, /* DMA channel */
+ XLR_SEC_DIGEST_SRC_CPHR /* Cipher if word count exceeded
+ * Cipher_Offset; else DMA */
+} XLR_SEC_DIGEST_SRC;
+
+/*
+ * Checksum Modes
+ */
+typedef enum {
+ XLR_SEC_CKSUM_TYPE_NOP = 1,
+ XLR_SEC_CKSUM_TYPE_IP
+} XLR_SEC_CKSUM_TYPE;
+
+typedef enum {
+ XLR_SEC_CKSUM_SRC_DMA = 1,
+ XLR_SEC_CKSUM_SRC_CIPHER
+} XLR_SEC_CKSUM_SRC;
+
+/*
+ * Packet Modes
+ */
+typedef enum {
+ XLR_SEC_LOADHMACKEY_MODE_OLD = 1,
+ XLR_SEC_LOADHMACKEY_MODE_LOAD
+} XLR_SEC_LOADHMACKEY_MODE;
+
+typedef enum {
+ XLR_SEC_PADHASH_PADDED = 1,
+ XLR_SEC_PADHASH_PAD
+} XLR_SEC_PADHASH_MODE;
+
+typedef enum {
+ XLR_SEC_HASHBYTES_ALL8 = 1,
+ XLR_SEC_HASHBYTES_MSB,
+ XLR_SEC_HASHBYTES_MSW
+} XLR_SEC_HASHBYTES_MODE;
+
+typedef enum {
+ XLR_SEC_NEXT_FINISH = 1,
+ XLR_SEC_NEXT_DO
+} XLR_SEC_NEXT_MODE;
+
+typedef enum {
+ XLR_SEC_PKT_IV_OLD = 1,
+ XLR_SEC_PKT_IV_NEW
+} XLR_SEC_PKT_IV_MODE;
+
+typedef enum {
+ XLR_SEC_LASTWORD_128 = 1,
+ XLR_SEC_LASTWORD_96MASK,
+ XLR_SEC_LASTWORD_64MASK,
+ XLR_SEC_LASTWORD_32MASK
+} XLR_SEC_LASTWORD_MODE;
+
+typedef enum {
+ XLR_SEC_CFB_MASK_REGULAR_CTR = 0,
+ XLR_SEC_CFB_MASK_CCMP,
+ XLR_SEC_CFB_MASK_GCM_WITH_SCI,
+ XLR_SEC_CFB_MASK_GCM_WITHOUT_SCI
+} XLR_SEC_CFB_MASK_MODE;
+
+/*
+ * Public Key
+ */
+typedef enum {
+ RMIPK_BLKWIDTH_512 = 1,
+ RMIPK_BLKWIDTH_1024
+} RMIPK_BLKWIDTH_MODE;
+
+typedef enum {
+ RMIPK_LDCONST_OLD = 1,
+ RMIPK_LDCONST_NEW
+} RMIPK_LDCONST_MODE;
+
+
+typedef struct xlr_sec_io_s {
+ unsigned int command;
+ unsigned int result_status;
+ unsigned int flags;
+ unsigned int session_num;
+ unsigned int use_callback;
+ unsigned int time_us;
+ unsigned int user_context[2]; /* usable for anything by caller */
+ unsigned int command_context; /* Context (ID) of this command). */
+ unsigned char initial_vector[XLR_SEC_MAX_IV_LENGTH];
+ unsigned char crypt_key[XLR_SEC_MAX_CRYPT_KEY_LENGTH];
+ unsigned char mac_key[XLR_SEC_MAX_AUTH_KEY_LENGTH];
+
+ XLR_SEC_CIPHER_OP cipher_op;
+ XLR_SEC_CIPHER_MODE cipher_mode;
+ XLR_SEC_CIPHER_TYPE cipher_type;
+ XLR_SEC_CIPHER_INIT cipher_init;
+ unsigned int cipher_offset;
+
+ XLR_SEC_DIGEST_TYPE digest_type;
+ XLR_SEC_DIGEST_INIT digest_init;
+ XLR_SEC_DIGEST_SRC digest_src;
+ unsigned int digest_offset;
+
+ XLR_SEC_CKSUM_TYPE cksum_type;
+ XLR_SEC_CKSUM_SRC cksum_src;
+ unsigned int cksum_offset;
+
+ XLR_SEC_LOADHMACKEY_MODE pkt_hmac;
+ XLR_SEC_PADHASH_MODE pkt_hash;
+ XLR_SEC_HASHBYTES_MODE pkt_hashbytes;
+ XLR_SEC_NEXT_MODE pkt_next;
+ XLR_SEC_PKT_IV_MODE pkt_iv;
+ XLR_SEC_LASTWORD_MODE pkt_lastword;
+
+ unsigned int nonce;
+ unsigned int cfb_mask;
+
+ unsigned int iv_offset;
+ unsigned short pad_type;
+ unsigned short rc4_key_len;
+
+ unsigned int num_packets;
+ unsigned int num_fragments;
+
+ uint64_t source_buf;
+ unsigned int source_buf_size;
+ uint64_t dest_buf;
+ unsigned int dest_buf_size;
+
+ uint64_t auth_dest;
+ uint64_t cksum_dest;
+
+ unsigned short rc4_loadstate;
+ unsigned short rc4_savestate;
+ uint64_t rc4_state;
+
+} xlr_sec_io_t, *xlr_sec_io_pt;
+
+
+#define XLR_SEC_SESSION(sid) ((sid) & 0x000007ff)
+#define XLR_SEC_SID(crd,ses) (((crd) << 28) | ((ses) & 0x7ff))
+
+/*
+ * Length values for cryptography
+ */
+/*
+#define XLR_SEC_DES_KEY_LENGTH 8
+#define XLR_SEC_3DES_KEY_LENGTH 24
+#define XLR_SEC_MAX_CRYPT_KEY_LENGTH XLR_SEC_3DES_KEY_LENGTH
+#define XLR_SEC_IV_LENGTH 8
+#define XLR_SEC_AES_IV_LENGTH 16
+#define XLR_SEC_MAX_IV_LENGTH XLR_SEC_AES_IV_LENGTH
+*/
+
+#define SEC_MAX_FRAG_LEN 16000
+
+struct xlr_sec_command {
+ uint16_t session_num;
+ struct cryptop *crp;
+ struct cryptodesc *enccrd, *maccrd;
+
+ xlr_sec_io_t op;
+};
+struct xlr_sec_session {
+ uint32_t sessionid;
+ int hs_used;
+ int hs_mlen;
+ struct xlr_sec_command cmd;
+ void *desc_ptr;
+ uint8_t multi_frag_flag;
+};
+
+/*
+ * Holds data specific to rmi security accelerators
+ */
+struct xlr_sec_softc {
+ device_t sc_dev; /* device backpointer */
+ struct mtx sc_mtx; /* per-instance lock */
+
+ int32_t sc_cid;
+ struct xlr_sec_session *sc_sessions;
+ int sc_nsessions;
+ xlr_reg_t *mmio;
+};
+
+
+/*
+
+union xlr_sec_operand_t {
+ struct mbuf *m;
+ struct uio *io;
+ void *buf;
+}xlr_sec_operand;
+*/
+
+
+
+
+
+/* this is passed to packet setup to optimize */
+#define XLR_SEC_SETUP_OP_CIPHER 0x00000001
+#define XLR_SEC_SETUP_OP_HMAC 0x00000002
+#define XLR_SEC_SETUP_OP_CIPHER_HMAC (XLR_SEC_SETUP_OP_CIPHER | XLR_SEC_SETUP_OP_HMAC)
+/* this is passed to control_setup to update w/preserving existing keys */
+#define XLR_SEC_SETUP_OP_PRESERVE_HMAC_KEY 0x80000000
+#define XLR_SEC_SETUP_OP_PRESERVE_CIPHER_KEY 0x40000000
+#define XLR_SEC_SETUP_OP_UPDATE_KEYS 0x00000010
+#define XLR_SEC_SETUP_OP_FLIP_3DES_KEY 0x00000020
+
+
+
+
+
+/*
+ * Message Ring Specifics
+ */
+
+#define SEC_MSGRING_WORDSIZE 2
+
+
+/*
+ *
+ *
+ * rwR 31 30 29 27 26 24 23 21 20 18
+ * | NA | RSA0Out | Rsa0In | Pipe3Out | Pipe3In | ...
+ *
+ * 17 15 14 12 11 9 8 6 5 3 2 0
+ * | Pipe2Out | Pipe2In | Pipe1In | Pipe1In | Pipe0Out | Pipe0In |
+ *
+ * DMA CREDIT REG -
+ * NUMBER OF CREDITS PER PIPE
+ */
+
+#define SEC_DMA_CREDIT_RSA0_OUT_FOUR 0x20000000
+#define SEC_DMA_CREDIT_RSA0_OUT_TWO 0x10000000
+#define SEC_DMA_CREDIT_RSA0_OUT_ONE 0x08000000
+
+#define SEC_DMA_CREDIT_RSA0_IN_FOUR 0x04000000
+#define SEC_DMA_CREDIT_RSA0_IN_TWO 0x02000000
+#define SEC_DMA_CREDIT_RSA0_IN_ONE 0x01000000
+
+#define SEC_DMA_CREDIT_PIPE3_OUT_FOUR 0x00800000
+#define SEC_DMA_CREDIT_PIPE3_OUT_TWO 0x00400000
+#define SEC_DMA_CREDIT_PIPE3_OUT_ONE 0x00200000
+
+#define SEC_DMA_CREDIT_PIPE3_IN_FOUR 0x00100000
+#define SEC_DMA_CREDIT_PIPE3_IN_TWO 0x00080000
+#define SEC_DMA_CREDIT_PIPE3_IN_ONE 0x00040000
+
+#define SEC_DMA_CREDIT_PIPE2_OUT_FOUR 0x00020000
+#define SEC_DMA_CREDIT_PIPE2_OUT_TWO 0x00010000
+#define SEC_DMA_CREDIT_PIPE2_OUT_ONE 0x00008000
+
+#define SEC_DMA_CREDIT_PIPE2_IN_FOUR 0x00004000
+#define SEC_DMA_CREDIT_PIPE2_IN_TWO 0x00002000
+#define SEC_DMA_CREDIT_PIPE2_IN_ONE 0x00001000
+
+#define SEC_DMA_CREDIT_PIPE1_OUT_FOUR 0x00000800
+#define SEC_DMA_CREDIT_PIPE1_OUT_TWO 0x00000400
+#define SEC_DMA_CREDIT_PIPE1_OUT_ONE 0x00000200
+
+#define SEC_DMA_CREDIT_PIPE1_IN_FOUR 0x00000100
+#define SEC_DMA_CREDIT_PIPE1_IN_TWO 0x00000080
+#define SEC_DMA_CREDIT_PIPE1_IN_ONE 0x00000040
+
+#define SEC_DMA_CREDIT_PIPE0_OUT_FOUR 0x00000020
+#define SEC_DMA_CREDIT_PIPE0_OUT_TWO 0x00000010
+#define SEC_DMA_CREDIT_PIPE0_OUT_ONE 0x00000008
+
+#define SEC_DMA_CREDIT_PIPE0_IN_FOUR 0x00000004
+#define SEC_DMA_CREDIT_PIPE0_IN_TWO 0x00000002
+#define SEC_DMA_CREDIT_PIPE0_IN_ONE 0x00000001
+
+
+/*
+ * Currently, FOUR credits per PIPE
+ * 0x24924924
+ */
+#define SEC_DMA_CREDIT_CONFIG SEC_DMA_CREDIT_RSA0_OUT_FOUR | \
+ SEC_DMA_CREDIT_RSA0_IN_FOUR | \
+ SEC_DMA_CREDIT_PIPE3_OUT_FOUR | \
+ SEC_DMA_CREDIT_PIPE3_IN_FOUR | \
+ SEC_DMA_CREDIT_PIPE2_OUT_FOUR | \
+ SEC_DMA_CREDIT_PIPE2_IN_FOUR | \
+ SEC_DMA_CREDIT_PIPE1_OUT_FOUR | \
+ SEC_DMA_CREDIT_PIPE1_IN_FOUR | \
+ SEC_DMA_CREDIT_PIPE0_OUT_FOUR | \
+ SEC_DMA_CREDIT_PIPE0_IN_FOUR
+
+
+
+
+/*
+ * CONFIG2
+ * 31 5 4 3
+ * | NA | PIPE3_DEF_DBL_ISS | PIPE2_DEF_DBL_ISS | ...
+ *
+ * 2 1 0
+ * ... | PIPE1_DEF_DBL_ISS | PIPE0_DEF_DBL_ISS | ROUND_ROBIN_MODE |
+ *
+ * DBL_ISS - mode for SECENG and DMA controller which slows down transfers
+ * (to be conservativei; 0=Disable,1=Enable).
+ * ROUND_ROBIN - mode where SECENG dispatches operations to PIPE0-PIPE3
+ * and all messages are sent to PIPE0.
+ *
+ */
+
+#define SEC_CFG2_PIPE3_DBL_ISS_ON 0x00000010
+#define SEC_CFG2_PIPE3_DBL_ISS_OFF 0x00000000
+#define SEC_CFG2_PIPE2_DBL_ISS_ON 0x00000008
+#define SEC_CFG2_PIPE2_DBL_ISS_OFF 0x00000000
+#define SEC_CFG2_PIPE1_DBL_ISS_ON 0x00000004
+#define SEC_CFG2_PIPE1_DBL_ISS_OFF 0x00000000
+#define SEC_CFG2_PIPE0_DBL_ISS_ON 0x00000002
+#define SEC_CFG2_PIPE0_DBL_ISS_OFF 0x00000000
+#define SEC_CFG2_ROUND_ROBIN_ON 0x00000001
+#define SEC_CFG2_ROUND_ROBIN_OFF 0x00000000
+
+
+enum sec_pipe_config {
+
+ SEC_PIPE_CIPHER_KEY0_L0 = 0x00,
+ SEC_PIPE_CIPHER_KEY0_HI,
+ SEC_PIPE_CIPHER_KEY1_LO,
+ SEC_PIPE_CIPHER_KEY1_HI,
+ SEC_PIPE_CIPHER_KEY2_LO,
+ SEC_PIPE_CIPHER_KEY2_HI,
+ SEC_PIPE_CIPHER_KEY3_LO,
+ SEC_PIPE_CIPHER_KEY3_HI,
+ SEC_PIPE_HMAC_KEY0_LO,
+ SEC_PIPE_HMAC_KEY0_HI,
+ SEC_PIPE_HMAC_KEY1_LO,
+ SEC_PIPE_HMAC_KEY1_HI,
+ SEC_PIPE_HMAC_KEY2_LO,
+ SEC_PIPE_HMAC_KEY2_HI,
+ SEC_PIPE_HMAC_KEY3_LO,
+ SEC_PIPE_HMAC_KEY3_HI,
+ SEC_PIPE_HMAC_KEY4_LO,
+ SEC_PIPE_HMAC_KEY4_HI,
+ SEC_PIPE_HMAC_KEY5_LO,
+ SEC_PIPE_HMAC_KEY5_HI,
+ SEC_PIPE_HMAC_KEY6_LO,
+ SEC_PIPE_HMAC_KEY6_HI,
+ SEC_PIPE_HMAC_KEY7_LO,
+ SEC_PIPE_HMAC_KEY7_HI,
+ SEC_PIPE_NCFBM_LO,
+ SEC_PIPE_NCFBM_HI,
+ SEC_PIPE_INSTR_LO,
+ SEC_PIPE_INSTR_HI,
+ SEC_PIPE_RSVD0,
+ SEC_PIPE_RSVD1,
+ SEC_PIPE_RSVD2,
+ SEC_PIPE_RSVD3,
+
+ SEC_PIPE_DF_PTRS0,
+ SEC_PIPE_DF_PTRS1,
+ SEC_PIPE_DF_PTRS2,
+ SEC_PIPE_DF_PTRS3,
+ SEC_PIPE_DF_PTRS4,
+ SEC_PIPE_DF_PTRS5,
+ SEC_PIPE_DF_PTRS6,
+ SEC_PIPE_DF_PTRS7,
+
+ SEC_PIPE_DU_DATA_IN_LO,
+ SEC_PIPE_DU_DATA_IN_HI,
+ SEC_PIPE_DU_DATA_IN_CTRL,
+ SEC_PIPE_DU_DATA_OUT_LO,
+ SEC_PIPE_DU_DATA_OUT_HI,
+ SEC_PIPE_DU_DATA_OUT_CTRL,
+
+ SEC_PIPE_STATE0,
+ SEC_PIPE_STATE1,
+ SEC_PIPE_STATE2,
+ SEC_PIPE_STATE3,
+ SEC_PIPE_STATE4,
+ SEC_PIPE_INCLUDE_MASK0,
+ SEC_PIPE_INCLUDE_MASK1,
+ SEC_PIPE_INCLUDE_MASK2,
+ SEC_PIPE_INCLUDE_MASK3,
+ SEC_PIPE_INCLUDE_MASK4,
+ SEC_PIPE_EXCLUDE_MASK0,
+ SEC_PIPE_EXCLUDE_MASK1,
+ SEC_PIPE_EXCLUDE_MASK2,
+ SEC_PIPE_EXCLUDE_MASK3,
+ SEC_PIPE_EXCLUDE_MASK4,
+};
+
+
+enum sec_pipe_base_config {
+
+ SEC_PIPE0_BASE = 0x00,
+ SEC_PIPE1_BASE = 0x40,
+ SEC_PIPE2_BASE = 0x80,
+ SEC_PIPE3_BASE = 0xc0
+
+};
+
+enum sec_rsa_config {
+
+ SEC_RSA_PIPE0_DU_DATA_IN_LO = 0x100,
+ SEC_RSA_PIPE0_DU_DATA_IN_HI,
+ SEC_RSA_PIPE0_DU_DATA_IN_CTRL,
+ SEC_RSA_PIPE0_DU_DATA_OUT_LO,
+ SEC_RSA_PIPE0_DU_DATA_OUT_HI,
+ SEC_RSA_PIPE0_DU_DATA_OUT_CTRL,
+ SEC_RSA_RSVD0,
+ SEC_RSA_RSVD1,
+
+ SEC_RSA_PIPE0_STATE0,
+ SEC_RSA_PIPE0_STATE1,
+ SEC_RSA_PIPE0_STATE2,
+ SEC_RSA_PIPE0_INCLUDE_MASK0,
+ SEC_RSA_PIPE0_INCLUDE_MASK1,
+ SEC_RSA_PIPE0_INCLUDE_MASK2,
+ SEC_RSA_PIPE0_EXCLUDE_MASK0,
+ SEC_RSA_PIPE0_EXCLUDE_MASK1,
+ SEC_RSA_PIPE0_EXCLUDE_MASK2,
+ SEC_RSA_PIPE0_EVENT_CTR
+
+};
+
+
+
+
+enum sec_config {
+
+ SEC_DMA_CREDIT = 0x140,
+ SEC_CONFIG1,
+ SEC_CONFIG2,
+ SEC_CONFIG3,
+
+};
+
+
+
+enum sec_debug_config {
+
+ SEC_DW0_DESCRIPTOR0_LO = 0x180,
+ SEC_DW0_DESCRIPTOR0_HI,
+ SEC_DW0_DESCRIPTOR1_LO,
+ SEC_DW0_DESCRIPTOR1_HI,
+ SEC_DW1_DESCRIPTOR0_LO,
+ SEC_DW1_DESCRIPTOR0_HI,
+ SEC_DW1_DESCRIPTOR1_LO,
+ SEC_DW1_DESCRIPTOR1_HI,
+ SEC_DW2_DESCRIPTOR0_LO,
+ SEC_DW2_DESCRIPTOR0_HI,
+ SEC_DW2_DESCRIPTOR1_LO,
+ SEC_DW2_DESCRIPTOR1_HI,
+ SEC_DW3_DESCRIPTOR0_LO,
+ SEC_DW3_DESCRIPTOR0_HI,
+ SEC_DW3_DESCRIPTOR1_LO,
+ SEC_DW3_DESCRIPTOR1_HI,
+
+ SEC_STATE0,
+ SEC_STATE1,
+ SEC_STATE2,
+ SEC_INCLUDE_MASK0,
+ SEC_INCLUDE_MASK1,
+ SEC_INCLUDE_MASK2,
+ SEC_EXCLUDE_MASK0,
+ SEC_EXCLUDE_MASK1,
+ SEC_EXCLUDE_MASK2,
+ SEC_EVENT_CTR
+
+};
+
+
+enum sec_msgring_bucket_config {
+
+ SEC_BIU_CREDITS = 0x308,
+
+ SEC_MSG_BUCKET0_SIZE = 0x320,
+ SEC_MSG_BUCKET1_SIZE,
+ SEC_MSG_BUCKET2_SIZE,
+ SEC_MSG_BUCKET3_SIZE,
+ SEC_MSG_BUCKET4_SIZE,
+ SEC_MSG_BUCKET5_SIZE,
+ SEC_MSG_BUCKET6_SIZE,
+ SEC_MSG_BUCKET7_SIZE,
+};
+
+enum sec_msgring_credit_config {
+
+ SEC_CC_CPU0_0 = 0x380,
+ SEC_CC_CPU1_0 = 0x388,
+ SEC_CC_CPU2_0 = 0x390,
+ SEC_CC_CPU3_0 = 0x398,
+ SEC_CC_CPU4_0 = 0x3a0,
+ SEC_CC_CPU5_0 = 0x3a8,
+ SEC_CC_CPU6_0 = 0x3b0,
+ SEC_CC_CPU7_0 = 0x3b8
+
+};
+
+enum sec_engine_id {
+ SEC_PIPE0,
+ SEC_PIPE1,
+ SEC_PIPE2,
+ SEC_PIPE3,
+ SEC_RSA
+};
+
+enum sec_cipher {
+ SEC_AES256_MODE_HMAC,
+ SEC_AES256_MODE,
+ SEC_AES256_HMAC,
+ SEC_AES256,
+ SEC_AES192_MODE_HMAC,
+ SEC_AES192_MODE,
+ SEC_AES192_HMAC,
+ SEC_AES192,
+ SEC_AES128_MODE_HMAC,
+ SEC_AES128_MODE,
+ SEC_AES128_HMAC,
+ SEC_AES128,
+ SEC_DES_HMAC,
+ SEC_DES,
+ SEC_3DES,
+ SEC_3DES_HMAC,
+ SEC_HMAC
+};
+
+enum sec_msgrng_msg_ctrl_config {
+ SEC_EOP = 5,
+ SEC_SOP = 6,
+};
+
+
+
+void
+xlr_sec_init(struct xlr_sec_softc *sc);
+
+int
+xlr_sec_setup(struct xlr_sec_session *ses,
+ struct xlr_sec_command *cmd, symkey_desc_pt desc);
+
+symkey_desc_pt xlr_sec_allocate_desc(void *);
+
+#endif
Property changes on: trunk/sys/mips/rmi/dev/sec/rmilib.h
___________________________________________________________________
Added: svn:eol-style
## -0,0 +1 ##
+native
\ No newline at end of property
Added: svn:keywords
## -0,0 +1 ##
+MidnightBSD=%H
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+text/plain
\ No newline at end of property
Added: trunk/sys/mips/rmi/dev/sec/rmisec.c
===================================================================
--- trunk/sys/mips/rmi/dev/sec/rmisec.c (rev 0)
+++ trunk/sys/mips/rmi/dev/sec/rmisec.c 2018-05-26 21:55:02 UTC (rev 9987)
@@ -0,0 +1,577 @@
+/* $MidnightBSD$ */
+/*-
+ * Copyright (c) 2003-2009 RMI Corporation
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * 3. Neither the name of RMI Corporation, nor the names of its contributors,
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ * RMI_BSD
+ */
+
+#include <sys/cdefs.h>
+__FBSDID("$FreeBSD: stable/10/sys/mips/rmi/dev/sec/rmisec.c 227843 2011-11-22 21:28:20Z marius $");
+
+#include <sys/param.h>
+#include <sys/systm.h>
+#include <sys/proc.h>
+#include <sys/errno.h>
+#include <sys/malloc.h>
+#include <sys/kernel.h>
+#include <sys/module.h>
+#include <sys/mbuf.h>
+#include <sys/lock.h>
+#include <sys/mutex.h>
+#include <sys/sysctl.h>
+#include <sys/bus.h>
+#include <sys/random.h>
+#include <sys/rman.h>
+#include <sys/uio.h>
+#include <sys/kobj.h>
+#include <opencrypto/cryptodev.h>
+
+#include "cryptodev_if.h"
+
+#include <vm/vm.h>
+#include <vm/pmap.h>
+
+#include <mips/rmi/dev/sec/rmilib.h>
+
+/* #define RMI_SEC_DEBUG */
+
+void xlr_sec_print_data(struct cryptop *crp);
+
+static int xlr_sec_newsession(device_t dev, uint32_t * sidp, struct cryptoini *cri);
+static int xlr_sec_freesession(device_t dev, uint64_t tid);
+static int xlr_sec_process(device_t dev, struct cryptop *crp, int hint);
+
+static int xlr_sec_probe(device_t);
+static int xlr_sec_attach(device_t);
+static int xlr_sec_detach(device_t);
+
+
+static device_method_t xlr_sec_methods[] = {
+ /* device interface */
+ DEVMETHOD(device_probe, xlr_sec_probe),
+ DEVMETHOD(device_attach, xlr_sec_attach),
+ DEVMETHOD(device_detach, xlr_sec_detach),
+
+ /* crypto device methods */
+ DEVMETHOD(cryptodev_newsession, xlr_sec_newsession),
+ DEVMETHOD(cryptodev_freesession,xlr_sec_freesession),
+ DEVMETHOD(cryptodev_process, xlr_sec_process),
+
+ DEVMETHOD_END
+};
+
+static driver_t xlr_sec_driver = {
+ "rmisec",
+ xlr_sec_methods,
+ sizeof(struct xlr_sec_softc)
+};
+static devclass_t xlr_sec_devclass;
+
+DRIVER_MODULE(rmisec, iodi, xlr_sec_driver, xlr_sec_devclass, 0, 0);
+MODULE_DEPEND(rmisec, crypto, 1, 1, 1);
+
+static int
+xlr_sec_probe(device_t dev)
+{
+
+ device_set_desc(dev, "XLR Security Accelerator");
+ return (BUS_PROBE_DEFAULT);
+}
+
+/*
+ * Attach an interface that successfully probed.
+ */
+static int
+xlr_sec_attach(device_t dev)
+{
+ struct xlr_sec_softc *sc = device_get_softc(dev);
+
+ sc->sc_dev = dev;
+ mtx_init(&sc->sc_mtx, device_get_nameunit(dev), "rmi crypto driver",
+ MTX_DEF);
+ sc->sc_cid = crypto_get_driverid(dev, CRYPTOCAP_F_HARDWARE);
+ if (sc->sc_cid < 0) {
+ printf("xlr_sec - error : could not get the driver id\n");
+ goto error_exit;
+ }
+ if (crypto_register(sc->sc_cid, CRYPTO_DES_CBC, 0, 0) != 0)
+ printf("register failed for CRYPTO_DES_CBC\n");
+
+ if (crypto_register(sc->sc_cid, CRYPTO_3DES_CBC, 0, 0) != 0)
+ printf("register failed for CRYPTO_3DES_CBC\n");
+
+ if (crypto_register(sc->sc_cid, CRYPTO_AES_CBC, 0, 0) != 0)
+ printf("register failed for CRYPTO_AES_CBC\n");
+
+ if (crypto_register(sc->sc_cid, CRYPTO_ARC4, 0, 0) != 0)
+ printf("register failed for CRYPTO_ARC4\n");
+
+ if (crypto_register(sc->sc_cid, CRYPTO_MD5, 0, 0) != 0)
+ printf("register failed for CRYPTO_MD5\n");
+
+ if (crypto_register(sc->sc_cid, CRYPTO_SHA1, 0, 0) != 0)
+ printf("register failed for CRYPTO_SHA1\n");
+
+ if (crypto_register(sc->sc_cid, CRYPTO_MD5_HMAC, 0, 0) != 0)
+ printf("register failed for CRYPTO_MD5_HMAC\n");
+
+ if (crypto_register(sc->sc_cid, CRYPTO_SHA1_HMAC, 0, 0) != 0)
+ printf("register failed for CRYPTO_SHA1_HMAC\n");
+
+ xlr_sec_init(sc);
+ device_printf(dev, "Initialization complete!\n");
+ return (0);
+
+error_exit:
+ return (ENXIO);
+
+}
+
+/*
+ * Detach an interface that successfully probed.
+ */
+static int
+xlr_sec_detach(device_t dev)
+{
+ int sesn;
+ struct xlr_sec_softc *sc = device_get_softc(dev);
+ struct xlr_sec_session *ses = NULL;
+ symkey_desc_pt desc;
+
+ for (sesn = 0; sesn < sc->sc_nsessions; sesn++) {
+ ses = &sc->sc_sessions[sesn];
+ desc = (symkey_desc_pt) ses->desc_ptr;
+ free(desc->user.kern_src, M_DEVBUF);
+ free(desc->user.kern_dest, M_DEVBUF);
+ free(desc->next_src_buf, M_DEVBUF);
+ free(desc->next_dest_buf, M_DEVBUF);
+ free(ses->desc_ptr, M_DEVBUF);
+ }
+
+ return (0);
+}
+
+/*
+ * Allocate a new 'session' and return an encoded session id. 'sidp'
+ * contains our registration id, and should contain an encoded session
+ * id on successful allocation.
+ */
+static int
+xlr_sec_newsession(device_t dev, u_int32_t *sidp, struct cryptoini *cri)
+{
+ struct cryptoini *c;
+ struct xlr_sec_softc *sc = device_get_softc(dev);
+ int mac = 0, cry = 0, sesn;
+ struct xlr_sec_session *ses = NULL;
+
+ if (sidp == NULL || cri == NULL || sc == NULL)
+ return (EINVAL);
+
+ if (sc->sc_sessions == NULL) {
+ ses = sc->sc_sessions = (struct xlr_sec_session *)malloc(
+ sizeof(struct xlr_sec_session), M_DEVBUF, M_NOWAIT);
+ if (ses == NULL)
+ return (ENOMEM);
+ sesn = 0;
+ sc->sc_nsessions = 1;
+ } else {
+ for (sesn = 0; sesn < sc->sc_nsessions; sesn++) {
+ if (!sc->sc_sessions[sesn].hs_used) {
+ ses = &sc->sc_sessions[sesn];
+ break;
+ }
+ }
+
+ if (ses == NULL) {
+ sesn = sc->sc_nsessions;
+ ses = (struct xlr_sec_session *)malloc((sesn + 1) *
+ sizeof(struct xlr_sec_session), M_DEVBUF, M_NOWAIT);
+ if (ses == NULL)
+ return (ENOMEM);
+ bcopy(sc->sc_sessions, ses, sesn * sizeof(*ses));
+ bzero(sc->sc_sessions, sesn * sizeof(*ses));
+ free(sc->sc_sessions, M_DEVBUF);
+ sc->sc_sessions = ses;
+ ses = &sc->sc_sessions[sesn];
+ sc->sc_nsessions++;
+ }
+ }
+ bzero(ses, sizeof(*ses));
+ ses->sessionid = sesn;
+ ses->desc_ptr = xlr_sec_allocate_desc(ses);
+ if (ses->desc_ptr == NULL)
+ return (ENOMEM);
+ ses->hs_used = 1;
+
+ for (c = cri; c != NULL; c = c->cri_next) {
+ switch (c->cri_alg) {
+ case CRYPTO_MD5:
+ case CRYPTO_SHA1:
+ case CRYPTO_MD5_HMAC:
+ case CRYPTO_SHA1_HMAC:
+ if (mac)
+ return (EINVAL);
+ mac = 1;
+ ses->hs_mlen = c->cri_mlen;
+ if (ses->hs_mlen == 0) {
+ switch (c->cri_alg) {
+ case CRYPTO_MD5:
+ case CRYPTO_MD5_HMAC:
+ ses->hs_mlen = 16;
+ break;
+ case CRYPTO_SHA1:
+ case CRYPTO_SHA1_HMAC:
+ ses->hs_mlen = 20;
+ break;
+ }
+ }
+ break;
+ case CRYPTO_DES_CBC:
+ case CRYPTO_3DES_CBC:
+ case CRYPTO_AES_CBC:
+ /* XXX this may read fewer, does it matter? */
+ /*
+ * read_random(ses->hs_iv, c->cri_alg ==
+ * CRYPTO_AES_CBC ? XLR_SEC_AES_IV_LENGTH :
+ * XLR_SEC_IV_LENGTH);
+ */
+ /* FALLTHROUGH */
+ case CRYPTO_ARC4:
+ if (cry)
+ return (EINVAL);
+ cry = 1;
+ break;
+ default:
+ return (EINVAL);
+ }
+ }
+ if (mac == 0 && cry == 0)
+ return (EINVAL);
+
+ *sidp = XLR_SEC_SID(device_get_unit(sc->sc_dev), sesn);
+ return (0);
+}
+
+/*
+ * Deallocate a session.
+ * XXX this routine should run a zero'd mac/encrypt key into context ram.
+ * XXX to blow away any keys already stored there.
+ */
+static int
+xlr_sec_freesession(device_t dev, u_int64_t tid)
+{
+ struct xlr_sec_softc *sc = device_get_softc(dev);
+ int session;
+ u_int32_t sid = CRYPTO_SESID2LID(tid);
+
+ if (sc == NULL)
+ return (EINVAL);
+
+ session = XLR_SEC_SESSION(sid);
+ if (session >= sc->sc_nsessions)
+ return (EINVAL);
+
+ sc->sc_sessions[session].hs_used = 0;
+ return (0);
+}
+
+#ifdef RMI_SEC_DEBUG
+
+void
+xlr_sec_print_data(struct cryptop *crp)
+{
+ int i, key_len;
+ struct cryptodesc *crp_desc;
+
+ printf("session id = 0x%llx, crp_ilen = %d, crp_olen=%d \n",
+ crp->crp_sid, crp->crp_ilen, crp->crp_olen);
+
+ printf("crp_flags = 0x%x\n", crp->crp_flags);
+
+
+ printf("crp buf:\n");
+ for (i = 0; i < crp->crp_ilen; i++) {
+ printf("%c ", crp->crp_buf[i]);
+ if (i % 10 == 0)
+ printf("\n");
+ }
+
+ printf("\n");
+ printf("****************** desc ****************\n");
+ crp_desc = crp->crp_desc;
+ printf("crd_skip=%d, crd_len=%d, crd_flags=0x%x, crd_alg=%d\n",
+ crp_desc->crd_skip, crp_desc->crd_len, crp_desc->crd_flags, crp_desc->crd_alg);
+
+ key_len = crp_desc->crd_klen / 8;
+ printf("key(%d) :\n", key_len);
+ for (i = 0; i < key_len; i++)
+ printf("%d", crp_desc->crd_key[i]);
+ printf("\n");
+
+ printf(" IV : \n");
+ for (i = 0; i < EALG_MAX_BLOCK_LEN; i++)
+ printf("%d", crp_desc->crd_iv[i]);
+ printf("\n");
+
+ printf("crd_next=%p\n", crp_desc->crd_next);
+ return;
+}
+
+#endif
+
+static int
+xlr_sec_process(device_t dev, struct cryptop *crp, int hint)
+{
+ struct xlr_sec_softc *sc = device_get_softc(dev);
+ struct xlr_sec_command *cmd = NULL;
+ int session, err;
+ struct cryptodesc *crd1, *crd2, *maccrd, *enccrd;
+ struct xlr_sec_session *ses;
+
+ if (crp == NULL || crp->crp_callback == NULL) {
+ return (EINVAL);
+ }
+ session = XLR_SEC_SESSION(crp->crp_sid);
+ if (sc == NULL || session >= sc->sc_nsessions) {
+ err = EINVAL;
+ goto errout;
+ }
+ ses = &sc->sc_sessions[session];
+
+ cmd = &ses->cmd;
+ if (cmd == NULL) {
+ err = ENOMEM;
+ goto errout;
+ }
+ crd1 = crp->crp_desc;
+ if (crd1 == NULL) {
+ err = EINVAL;
+ goto errout;
+ }
+ crd2 = crd1->crd_next;
+
+ if (crd2 == NULL) {
+ if (crd1->crd_alg == CRYPTO_MD5_HMAC ||
+ crd1->crd_alg == CRYPTO_SHA1_HMAC ||
+ crd1->crd_alg == CRYPTO_SHA1 ||
+ crd1->crd_alg == CRYPTO_MD5) {
+ maccrd = crd1;
+ enccrd = NULL;
+ } else if (crd1->crd_alg == CRYPTO_DES_CBC ||
+ crd1->crd_alg == CRYPTO_3DES_CBC ||
+ crd1->crd_alg == CRYPTO_AES_CBC ||
+ crd1->crd_alg == CRYPTO_ARC4) {
+ maccrd = NULL;
+ enccrd = crd1;
+ } else {
+ err = EINVAL;
+ goto errout;
+ }
+ } else {
+ if ((crd1->crd_alg == CRYPTO_MD5_HMAC ||
+ crd1->crd_alg == CRYPTO_SHA1_HMAC ||
+ crd1->crd_alg == CRYPTO_MD5 ||
+ crd1->crd_alg == CRYPTO_SHA1) &&
+ (crd2->crd_alg == CRYPTO_DES_CBC ||
+ crd2->crd_alg == CRYPTO_3DES_CBC ||
+ crd2->crd_alg == CRYPTO_AES_CBC ||
+ crd2->crd_alg == CRYPTO_ARC4)) {
+ maccrd = crd1;
+ enccrd = crd2;
+ } else if ((crd1->crd_alg == CRYPTO_DES_CBC ||
+ crd1->crd_alg == CRYPTO_ARC4 ||
+ crd1->crd_alg == CRYPTO_3DES_CBC ||
+ crd1->crd_alg == CRYPTO_AES_CBC) &&
+ (crd2->crd_alg == CRYPTO_MD5_HMAC ||
+ crd2->crd_alg == CRYPTO_SHA1_HMAC ||
+ crd2->crd_alg == CRYPTO_MD5 ||
+ crd2->crd_alg == CRYPTO_SHA1) &&
+ (crd1->crd_flags & CRD_F_ENCRYPT)) {
+ enccrd = crd1;
+ maccrd = crd2;
+ } else {
+ err = EINVAL;
+ goto errout;
+ }
+ }
+
+ bzero(&cmd->op, sizeof(xlr_sec_io_t));
+
+ cmd->op.source_buf = (uint64_t) (unsigned long)crp->crp_buf;
+ cmd->op.source_buf_size = crp->crp_ilen;
+ if (crp->crp_flags & CRYPTO_F_REL) {
+ cmd->op.dest_buf = (uint64_t) (unsigned long)crp->crp_buf;
+ cmd->op.dest_buf_size = crp->crp_ilen;
+ } else {
+ cmd->op.dest_buf = (uint64_t) (unsigned long)crp->crp_buf;
+ cmd->op.dest_buf_size = crp->crp_ilen;
+ }
+ cmd->op.num_packets = 1;
+ cmd->op.num_fragments = 1;
+
+ if (cmd->op.source_buf_size > SEC_MAX_FRAG_LEN) {
+ ses->multi_frag_flag = 1;
+ } else {
+ ses->multi_frag_flag = 0;
+ }
+
+ if (maccrd) {
+ cmd->maccrd = maccrd;
+ cmd->op.cipher_op = XLR_SEC_CIPHER_MODE_PASS;
+ cmd->op.cipher_mode = XLR_SEC_CIPHER_MODE_NONE;
+ cmd->op.cipher_type = XLR_SEC_CIPHER_TYPE_NONE;
+ cmd->op.cipher_init = 0;
+ cmd->op.cipher_offset = 0;
+
+ switch (maccrd->crd_alg) {
+ case CRYPTO_MD5:
+ cmd->op.digest_type = XLR_SEC_DIGEST_TYPE_MD5;
+ cmd->op.digest_init = XLR_SEC_DIGEST_INIT_NEWKEY;
+ cmd->op.digest_src = XLR_SEC_DIGEST_SRC_DMA;
+ cmd->op.digest_offset = 0;
+
+ cmd->op.cksum_type = XLR_SEC_CKSUM_TYPE_NOP;
+ cmd->op.cksum_src = XLR_SEC_CKSUM_SRC_CIPHER;
+ cmd->op.cksum_offset = 0;
+
+ cmd->op.pkt_hmac = XLR_SEC_LOADHMACKEY_MODE_OLD;
+ cmd->op.pkt_hash = XLR_SEC_PADHASH_PAD;
+ cmd->op.pkt_hashbytes = XLR_SEC_HASHBYTES_ALL8;
+ cmd->op.pkt_next = XLR_SEC_NEXT_FINISH;
+ cmd->op.pkt_iv = XLR_SEC_PKT_IV_OLD;
+ cmd->op.pkt_lastword = XLR_SEC_LASTWORD_128;
+
+ default:
+ printf("currently not handled\n");
+ }
+ }
+ if (enccrd) {
+ cmd->enccrd = enccrd;
+
+#ifdef RMI_SEC_DEBUG
+ xlr_sec_print_data(crp);
+#endif
+
+ if (enccrd->crd_flags & CRD_F_ENCRYPT) {
+ cmd->op.cipher_op = XLR_SEC_CIPHER_OP_ENCRYPT;
+ } else
+ cmd->op.cipher_op = XLR_SEC_CIPHER_OP_DECRYPT;
+
+ switch (enccrd->crd_alg) {
+ case CRYPTO_DES_CBC:
+ case CRYPTO_3DES_CBC:
+ if (enccrd->crd_alg == CRYPTO_DES_CBC) {
+ cmd->op.cipher_type = XLR_SEC_CIPHER_TYPE_DES;
+ memcpy(&cmd->op.crypt_key[0], enccrd->crd_key, XLR_SEC_DES_KEY_LENGTH);
+ } else {
+ cmd->op.cipher_type = XLR_SEC_CIPHER_TYPE_3DES;
+ //if (enccrd->crd_flags & CRD_F_KEY_EXPLICIT)
+ {
+ memcpy(&cmd->op.crypt_key[0], enccrd->crd_key,
+ XLR_SEC_3DES_KEY_LENGTH);
+ }
+ }
+
+ cmd->op.cipher_mode = XLR_SEC_CIPHER_MODE_CBC;
+ cmd->op.cipher_init = XLR_SEC_CIPHER_INIT_NK;
+ cmd->op.cipher_offset = XLR_SEC_DES_IV_LENGTH;
+
+ cmd->op.digest_type = XLR_SEC_DIGEST_TYPE_NONE;
+ cmd->op.digest_init = XLR_SEC_DIGEST_INIT_OLDKEY;
+ cmd->op.digest_src = XLR_SEC_DIGEST_SRC_DMA;
+ cmd->op.digest_offset = 0;
+
+ cmd->op.cksum_type = XLR_SEC_CKSUM_TYPE_NOP;
+ cmd->op.cksum_src = XLR_SEC_CKSUM_SRC_CIPHER;
+ cmd->op.cksum_offset = 0;
+
+ cmd->op.pkt_hmac = XLR_SEC_LOADHMACKEY_MODE_OLD;
+ cmd->op.pkt_hash = XLR_SEC_PADHASH_PAD;
+ cmd->op.pkt_hashbytes = XLR_SEC_HASHBYTES_ALL8;
+ cmd->op.pkt_next = XLR_SEC_NEXT_FINISH;
+ cmd->op.pkt_iv = XLR_SEC_PKT_IV_NEW;
+ cmd->op.pkt_lastword = XLR_SEC_LASTWORD_128;
+
+ //if ((!(enccrd->crd_flags & CRD_F_IV_PRESENT)) &&
+ if ((enccrd->crd_flags & CRD_F_IV_EXPLICIT)) {
+ memcpy(&cmd->op.initial_vector[0], enccrd->crd_iv,
+ XLR_SEC_DES_IV_LENGTH);
+ }
+ break;
+
+ case CRYPTO_AES_CBC:
+ if (enccrd->crd_alg == CRYPTO_AES_CBC) {
+ cmd->op.cipher_type = XLR_SEC_CIPHER_TYPE_AES128;
+ //if (enccrd->crd_flags & CRD_F_KEY_EXPLICIT)
+ {
+ memcpy(&cmd->op.crypt_key[0], enccrd->crd_key,
+ XLR_SEC_AES128_KEY_LENGTH);
+ }
+ }
+ cmd->op.cipher_mode = XLR_SEC_CIPHER_MODE_CBC;
+ cmd->op.cipher_init = XLR_SEC_CIPHER_INIT_NK;
+ cmd->op.cipher_offset = XLR_SEC_AES_BLOCK_SIZE;
+
+ cmd->op.digest_type = XLR_SEC_DIGEST_TYPE_NONE;
+ cmd->op.digest_init = XLR_SEC_DIGEST_INIT_OLDKEY;
+ cmd->op.digest_src = XLR_SEC_DIGEST_SRC_DMA;
+ cmd->op.digest_offset = 0;
+
+ cmd->op.cksum_type = XLR_SEC_CKSUM_TYPE_NOP;
+ cmd->op.cksum_src = XLR_SEC_CKSUM_SRC_CIPHER;
+ cmd->op.cksum_offset = 0;
+
+ cmd->op.pkt_hmac = XLR_SEC_LOADHMACKEY_MODE_OLD;
+ cmd->op.pkt_hash = XLR_SEC_PADHASH_PAD;
+ cmd->op.pkt_hashbytes = XLR_SEC_HASHBYTES_ALL8;
+ cmd->op.pkt_next = XLR_SEC_NEXT_FINISH;
+ cmd->op.pkt_iv = XLR_SEC_PKT_IV_NEW;
+ cmd->op.pkt_lastword = XLR_SEC_LASTWORD_128;
+
+ //if (!(enccrd->crd_flags & CRD_F_IV_PRESENT)) {
+ if ((enccrd->crd_flags & CRD_F_IV_EXPLICIT)) {
+ memcpy(&cmd->op.initial_vector[0], enccrd->crd_iv,
+ XLR_SEC_AES_BLOCK_SIZE);
+ }
+ //}
+ break;
+ }
+ }
+ cmd->crp = crp;
+ cmd->session_num = session;
+ xlr_sec_setup(ses, cmd, (symkey_desc_pt) ses->desc_ptr);
+
+ return (0);
+
+errout:
+ if (cmd != NULL)
+ free(cmd, M_DEVBUF);
+ crp->crp_etype = err;
+ crypto_done(crp);
+ return (err);
+}
Property changes on: trunk/sys/mips/rmi/dev/sec/rmisec.c
___________________________________________________________________
Added: svn:eol-style
## -0,0 +1 ##
+native
\ No newline at end of property
Added: svn:keywords
## -0,0 +1 ##
+MidnightBSD=%H
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+text/plain
\ No newline at end of property
Added: trunk/sys/mips/rmi/dev/xlr/atx_cpld.h
===================================================================
--- trunk/sys/mips/rmi/dev/xlr/atx_cpld.h (rev 0)
+++ trunk/sys/mips/rmi/dev/xlr/atx_cpld.h 2018-05-26 21:55:02 UTC (rev 9987)
@@ -0,0 +1,54 @@
+/* $MidnightBSD$ */
+/*-
+ * Copyright (c) 2003-2009 RMI Corporation
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * 3. Neither the name of RMI Corporation, nor the names of its contributors,
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ * RMI_BSD */
+#ifndef _RMI_ATX_CPLD_H_
+#define _RMI_ATX_CPLD_H_
+
+/*
+ * bit_0 : xgs0 phy reset, bit_1 : xgs1 phy reset, bit_2 : HT reset, bit_3 :
+ * RTC reset, bit_4 : gmac phy soft reset, bit_5 : gmac phy hard reset, bit_6
+ * : board reset, bit_7 : reserved
+ */
+#define ATX_CPLD_RESET_1 2
+
+/*
+ * bit_0_2 : reserved, bit_3 : turn off xpak_0 tx, bit_4 : turn off xpak_1
+ * tx, bit_5 : HT stop (active low), bit_6 : flash program enable, bit_7 :
+ * compact flash io mode
+ */
+#define ATX_CPLD_MISC_CTRL 8
+
+/*
+ * bit_0 : reset tcam, bit_1 : reset xpak_0 module, bit_2 : reset xpak_1
+ * module, bit_3_7 : reserved
+ */
+#define ATX_CPLD_RESET_2 9
+
+#endif /* _RMI_ATX_CPLD_H_ */
Property changes on: trunk/sys/mips/rmi/dev/xlr/atx_cpld.h
___________________________________________________________________
Added: svn:eol-style
## -0,0 +1 ##
+native
\ No newline at end of property
Added: svn:keywords
## -0,0 +1 ##
+MidnightBSD=%H
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+text/plain
\ No newline at end of property
Added: trunk/sys/mips/rmi/dev/xlr/debug.h
===================================================================
--- trunk/sys/mips/rmi/dev/xlr/debug.h (rev 0)
+++ trunk/sys/mips/rmi/dev/xlr/debug.h 2018-05-26 21:55:02 UTC (rev 9987)
@@ -0,0 +1,106 @@
+/* $MidnightBSD$ */
+/*-
+ * Copyright (c) 2003-2009 RMI Corporation
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * 3. Neither the name of RMI Corporation, nor the names of its contributors,
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ * RMI_BSD
+ * $FreeBSD: stable/10/sys/mips/rmi/dev/xlr/debug.h 211996 2010-08-30 13:26:07Z jchandra $
+ */
+#ifndef _RMI_DEBUG_H_
+#define _RMI_DEBUG_H_
+
+#include <machine/atomic.h>
+
+enum {
+ //cacheline 0
+ MSGRNG_INT,
+ MSGRNG_PIC_INT,
+ MSGRNG_MSG,
+ MSGRNG_EXIT_STATUS,
+ MSGRNG_MSG_CYCLES,
+ //cacheline 1
+ NETIF_TX = 8,
+ NETIF_RX,
+ NETIF_TX_COMPLETE,
+ NETIF_TX_COMPLETE_TX,
+ NETIF_RX_CYCLES,
+ NETIF_TX_COMPLETE_CYCLES,
+ NETIF_TX_CYCLES,
+ NETIF_TIMER_START_Q,
+ //NETIF_REG_FRIN,
+ //NETIF_INT_REG,
+ //cacheline 2
+ REPLENISH_ENTER = 16,
+ REPLENISH_ENTER_COUNT,
+ REPLENISH_CPU,
+ REPLENISH_FRIN,
+ REPLENISH_CYCLES,
+ NETIF_STACK_TX,
+ NETIF_START_Q,
+ NETIF_STOP_Q,
+ //cacheline 3
+ USER_MAC_START = 24,
+ USER_MAC_INT = 24,
+ USER_MAC_TX_COMPLETE,
+ USER_MAC_RX,
+ USER_MAC_POLL,
+ USER_MAC_TX,
+ USER_MAC_TX_FAIL,
+ USER_MAC_TX_COUNT,
+ USER_MAC_FRIN,
+ //cacheline 4
+ USER_MAC_TX_FAIL_GMAC_CREDITS = 32,
+ USER_MAC_DO_PAGE_FAULT,
+ USER_MAC_UPDATE_TLB,
+ USER_MAC_UPDATE_BIGTLB,
+ USER_MAC_UPDATE_TLB_PFN0,
+ USER_MAC_UPDATE_TLB_PFN1,
+
+ XLR_MAX_COUNTERS = 40
+};
+extern int xlr_counters[MAXCPU][XLR_MAX_COUNTERS];
+extern __uint32_t msgrng_msg_cycles;
+
+#ifdef ENABLE_DEBUG
+#define xlr_inc_counter(x) atomic_add_int(&xlr_counters[PCPU_GET(cpuid)][(x)], 1)
+#define xlr_dec_counter(x) atomic_subtract_int(&xlr_counters[PCPU_GET(cpuid)][(x)], 1)
+#define xlr_set_counter(x, value) atomic_set_int(&xlr_counters[PCPU_GET(cpuid)][(x)], (value))
+#define xlr_get_counter(x) (&xlr_counters[0][(x)])
+
+#else /* default mode */
+
+#define xlr_inc_counter(x)
+#define xlr_dec_counter(x)
+#define xlr_set_counter(x, value)
+#define xlr_get_counter(x)
+
+#endif
+
+#define dbg_msg(fmt, args...) printf(fmt, ##args)
+#define dbg_panic(fmt, args...) panic(fmt, ##args)
+
+#endif
Property changes on: trunk/sys/mips/rmi/dev/xlr/debug.h
___________________________________________________________________
Added: svn:eol-style
## -0,0 +1 ##
+native
\ No newline at end of property
Added: svn:keywords
## -0,0 +1 ##
+MidnightBSD=%H
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+text/plain
\ No newline at end of property
Added: trunk/sys/mips/rmi/dev/xlr/rge.c
===================================================================
--- trunk/sys/mips/rmi/dev/xlr/rge.c (rev 0)
+++ trunk/sys/mips/rmi/dev/xlr/rge.c 2018-05-26 21:55:02 UTC (rev 9987)
@@ -0,0 +1,2565 @@
+/* $MidnightBSD$ */
+/*-
+ * Copyright (c) 2003-2009 RMI Corporation
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * 3. Neither the name of RMI Corporation, nor the names of its contributors,
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ * RMI_BSD
+ */
+
+#include <sys/cdefs.h>
+__FBSDID("$FreeBSD: stable/10/sys/mips/rmi/dev/xlr/rge.c 314667 2017-03-04 13:03:31Z avg $");
+
+#ifdef HAVE_KERNEL_OPTION_HEADERS
+#include "opt_device_polling.h"
+#endif
+
+#include <sys/types.h>
+#include <sys/endian.h>
+#include <sys/systm.h>
+#include <sys/sockio.h>
+#include <sys/param.h>
+#include <sys/lock.h>
+#include <sys/mutex.h>
+#include <sys/proc.h>
+#include <sys/limits.h>
+#include <sys/bus.h>
+#include <sys/mbuf.h>
+#include <sys/malloc.h>
+#include <sys/kernel.h>
+#include <sys/module.h>
+#include <sys/socket.h>
+#define __RMAN_RESOURCE_VISIBLE
+#include <sys/rman.h>
+#include <sys/taskqueue.h>
+#include <sys/smp.h>
+#include <sys/sysctl.h>
+
+#include <net/if.h>
+#include <net/if_arp.h>
+#include <net/ethernet.h>
+#include <net/if_dl.h>
+#include <net/if_media.h>
+
+#include <net/bpf.h>
+#include <net/if_types.h>
+#include <net/if_vlan_var.h>
+
+#include <netinet/in_systm.h>
+#include <netinet/in.h>
+#include <netinet/ip.h>
+
+#include <vm/vm.h>
+#include <vm/pmap.h>
+
+#include <machine/reg.h>
+#include <machine/cpu.h>
+#include <machine/mips_opcode.h>
+#include <machine/asm.h>
+
+#include <machine/param.h>
+#include <machine/intr_machdep.h>
+#include <machine/clock.h> /* for DELAY */
+#include <machine/cpuregs.h>
+#include <machine/bus.h> /* */
+#include <machine/resource.h>
+
+#include <dev/mii/mii.h>
+#include <dev/mii/miivar.h>
+#include <dev/mii/brgphyreg.h>
+
+#include <mips/rmi/interrupt.h>
+#include <mips/rmi/msgring.h>
+#include <mips/rmi/iomap.h>
+#include <mips/rmi/pic.h>
+#include <mips/rmi/rmi_mips_exts.h>
+#include <mips/rmi/rmi_boot_info.h>
+#include <mips/rmi/board.h>
+
+#include <mips/rmi/dev/xlr/debug.h>
+#include <mips/rmi/dev/xlr/atx_cpld.h>
+#include <mips/rmi/dev/xlr/xgmac_mdio.h>
+#include <mips/rmi/dev/xlr/rge.h>
+
+#include "miibus_if.h"
+
+MODULE_DEPEND(rge, ether, 1, 1, 1);
+MODULE_DEPEND(rge, miibus, 1, 1, 1);
+
+/* #define DEBUG */
+
+#define RGE_TX_THRESHOLD 1024
+#define RGE_TX_Q_SIZE 1024
+
+#ifdef DEBUG
+#undef dbg_msg
+int mac_debug = 1;
+
+#define dbg_msg(fmt, args...) \
+ do {\
+ if (mac_debug) {\
+ printf("[%s@%d|%s]: cpu_%d: " fmt, \
+ __FILE__, __LINE__, __FUNCTION__, xlr_cpu_id(), ##args);\
+ }\
+ } while(0);
+
+#define DUMP_PACKETS
+#else
+#undef dbg_msg
+#define dbg_msg(fmt, args...)
+int mac_debug = 0;
+
+#endif
+
+#define MAC_B2B_IPG 88
+
+/* frame sizes need to be cacheline aligned */
+#define MAX_FRAME_SIZE 1536
+#define MAX_FRAME_SIZE_JUMBO 9216
+
+#define MAC_SKB_BACK_PTR_SIZE SMP_CACHE_BYTES
+#define MAC_PREPAD 0
+#define BYTE_OFFSET 2
+#define XLR_RX_BUF_SIZE (MAX_FRAME_SIZE+BYTE_OFFSET+MAC_PREPAD+MAC_SKB_BACK_PTR_SIZE+SMP_CACHE_BYTES)
+#define MAC_CRC_LEN 4
+#define MAX_NUM_MSGRNG_STN_CC 128
+
+#define MAX_NUM_DESC 1024
+#define MAX_SPILL_SIZE (MAX_NUM_DESC + 128)
+
+#define MAC_FRIN_TO_BE_SENT_THRESHOLD 16
+
+#define MAX_FRIN_SPILL (MAX_SPILL_SIZE << 2)
+#define MAX_FROUT_SPILL (MAX_SPILL_SIZE << 2)
+#define MAX_CLASS_0_SPILL (MAX_SPILL_SIZE << 2)
+#define MAX_CLASS_1_SPILL (MAX_SPILL_SIZE << 2)
+#define MAX_CLASS_2_SPILL (MAX_SPILL_SIZE << 2)
+#define MAX_CLASS_3_SPILL (MAX_SPILL_SIZE << 2)
+
+/*****************************************************************
+ * Phoenix Generic Mac driver
+ *****************************************************************/
+
+extern uint32_t cpu_ltop_map[32];
+
+#ifdef ENABLED_DEBUG
+static int port_counters[4][8] __aligned(XLR_CACHELINE_SIZE);
+
+#define port_inc_counter(port, counter) atomic_add_int(&port_counters[port][(counter)], 1)
+#else
+#define port_inc_counter(port, counter) /* Nothing */
+#endif
+
+int xlr_rge_tx_prepend[MAXCPU];
+int xlr_rge_tx_done[MAXCPU];
+int xlr_rge_get_p2d_failed[MAXCPU];
+int xlr_rge_msg_snd_failed[MAXCPU];
+int xlr_rge_tx_ok_done[MAXCPU];
+int xlr_rge_rx_done[MAXCPU];
+int xlr_rge_repl_done[MAXCPU];
+
+/* #define mac_stats_add(x, val) ({(x) += (val);}) */
+#define mac_stats_add(x, val) xlr_ldaddwu(val, &x)
+
+#define XLR_MAX_CORE 8
+#define RGE_LOCK_INIT(_sc, _name) \
+ mtx_init(&(_sc)->rge_mtx, _name, MTX_NETWORK_LOCK, MTX_DEF)
+#define RGE_LOCK(_sc) mtx_lock(&(_sc)->rge_mtx)
+#define RGE_LOCK_ASSERT(_sc) mtx_assert(&(_sc)->rge_mtx, MA_OWNED)
+#define RGE_UNLOCK(_sc) mtx_unlock(&(_sc)->rge_mtx)
+#define RGE_LOCK_DESTROY(_sc) mtx_destroy(&(_sc)->rge_mtx)
+
+#define XLR_MAX_MACS 8
+#define XLR_MAX_TX_FRAGS 14
+#define MAX_P2D_DESC_PER_PORT 512
+struct p2d_tx_desc {
+ uint64_t frag[XLR_MAX_TX_FRAGS + 2];
+};
+
+#define MAX_TX_RING_SIZE (XLR_MAX_MACS * MAX_P2D_DESC_PER_PORT * sizeof(struct p2d_tx_desc))
+
+struct rge_softc *dev_mac[XLR_MAX_MACS];
+static int dev_mac_xgs0;
+static int dev_mac_gmac0;
+
+static int gmac_common_init_done;
+
+
+static int rge_probe(device_t);
+static int rge_attach(device_t);
+static int rge_detach(device_t);
+static int rge_suspend(device_t);
+static int rge_resume(device_t);
+static void rge_release_resources(struct rge_softc *);
+static void rge_rx(struct rge_softc *, vm_paddr_t paddr, int);
+static void rge_intr(void *);
+static void rge_start_locked(struct ifnet *, int);
+static void rge_start(struct ifnet *);
+static int rge_ioctl(struct ifnet *, u_long, caddr_t);
+static void rge_init(void *);
+static void rge_stop(struct rge_softc *);
+static int rge_shutdown(device_t);
+static void rge_reset(struct rge_softc *);
+
+static struct mbuf *get_mbuf(void);
+static void free_buf(vm_paddr_t paddr);
+static void *get_buf(void);
+
+static void xlr_mac_get_hwaddr(struct rge_softc *);
+static void xlr_mac_setup_hwaddr(struct driver_data *);
+static void rmi_xlr_mac_set_enable(struct driver_data *priv, int flag);
+static void rmi_xlr_xgmac_init(struct driver_data *priv);
+static void rmi_xlr_gmac_init(struct driver_data *priv);
+static void mac_common_init(void);
+static int rge_mii_write(device_t, int, int, int);
+static int rge_mii_read(device_t, int, int);
+static void rmi_xlr_mac_mii_statchg(device_t);
+static int rmi_xlr_mac_mediachange(struct ifnet *);
+static void rmi_xlr_mac_mediastatus(struct ifnet *, struct ifmediareq *);
+static void xlr_mac_set_rx_mode(struct rge_softc *sc);
+void
+rmi_xlr_mac_msgring_handler(int bucket, int size, int code,
+ int stid, struct msgrng_msg *msg,
+ void *data);
+static void mac_frin_replenish(void *);
+static int rmi_xlr_mac_open(struct rge_softc *);
+static int rmi_xlr_mac_close(struct rge_softc *);
+static int
+mac_xmit(struct mbuf *, struct rge_softc *,
+ struct driver_data *, int, struct p2d_tx_desc *);
+static int rmi_xlr_mac_xmit(struct mbuf *, struct rge_softc *, int, struct p2d_tx_desc *);
+static struct rge_softc_stats *rmi_xlr_mac_get_stats(struct rge_softc *sc);
+static void rmi_xlr_mac_set_multicast_list(struct rge_softc *sc);
+static int rmi_xlr_mac_change_mtu(struct rge_softc *sc, int new_mtu);
+static int rmi_xlr_mac_fill_rxfr(struct rge_softc *sc);
+static void rmi_xlr_config_spill_area(struct driver_data *priv);
+static int rmi_xlr_mac_set_speed(struct driver_data *s, xlr_mac_speed_t speed);
+static int
+rmi_xlr_mac_set_duplex(struct driver_data *s,
+ xlr_mac_duplex_t duplex, xlr_mac_fc_t fc);
+static void serdes_regs_init(struct driver_data *priv);
+static int rmi_xlr_gmac_reset(struct driver_data *priv);
+
+/*Statistics...*/
+static int get_p2d_desc_failed = 0;
+static int msg_snd_failed = 0;
+
+SYSCTL_INT(_hw, OID_AUTO, get_p2d_failed, CTLFLAG_RW,
+ &get_p2d_desc_failed, 0, "p2d desc failed");
+SYSCTL_INT(_hw, OID_AUTO, msg_snd_failed, CTLFLAG_RW,
+ &msg_snd_failed, 0, "msg snd failed");
+
+struct callout xlr_tx_stop_bkp;
+
+static device_method_t rge_methods[] = {
+ /* Device interface */
+ DEVMETHOD(device_probe, rge_probe),
+ DEVMETHOD(device_attach, rge_attach),
+ DEVMETHOD(device_detach, rge_detach),
+ DEVMETHOD(device_shutdown, rge_shutdown),
+ DEVMETHOD(device_suspend, rge_suspend),
+ DEVMETHOD(device_resume, rge_resume),
+
+ /* MII interface */
+ DEVMETHOD(miibus_readreg, rge_mii_read),
+ DEVMETHOD(miibus_statchg, rmi_xlr_mac_mii_statchg),
+ DEVMETHOD(miibus_writereg, rge_mii_write),
+ {0, 0}
+};
+
+static driver_t rge_driver = {
+ "rge",
+ rge_methods,
+ sizeof(struct rge_softc)
+};
+
+static devclass_t rge_devclass;
+
+DRIVER_MODULE(rge, iodi, rge_driver, rge_devclass, 0, 0);
+DRIVER_MODULE(miibus, rge, miibus_driver, miibus_devclass, 0, 0);
+
+#ifndef __STR
+#define __STR(x) #x
+#endif
+#ifndef STR
+#define STR(x) __STR(x)
+#endif
+
+void *xlr_tx_ring_mem;
+
+struct tx_desc_node {
+ struct p2d_tx_desc *ptr;
+ TAILQ_ENTRY(tx_desc_node) list;
+};
+
+#define XLR_MAX_TX_DESC_NODES (XLR_MAX_MACS * MAX_P2D_DESC_PER_PORT)
+struct tx_desc_node tx_desc_nodes[XLR_MAX_TX_DESC_NODES];
+static volatile int xlr_tot_avail_p2d[XLR_MAX_CORE];
+static int xlr_total_active_core = 0;
+
+/*
+ * This should contain the list of all free tx frag desc nodes pointing to tx
+ * p2d arrays
+ */
+static
+TAILQ_HEAD(, tx_desc_node) tx_frag_desc[XLR_MAX_CORE] =
+{
+ TAILQ_HEAD_INITIALIZER(tx_frag_desc[0]),
+ TAILQ_HEAD_INITIALIZER(tx_frag_desc[1]),
+ TAILQ_HEAD_INITIALIZER(tx_frag_desc[2]),
+ TAILQ_HEAD_INITIALIZER(tx_frag_desc[3]),
+ TAILQ_HEAD_INITIALIZER(tx_frag_desc[4]),
+ TAILQ_HEAD_INITIALIZER(tx_frag_desc[5]),
+ TAILQ_HEAD_INITIALIZER(tx_frag_desc[6]),
+ TAILQ_HEAD_INITIALIZER(tx_frag_desc[7]),
+};
+
+/* This contains a list of free tx frag node descriptors */
+static
+TAILQ_HEAD(, tx_desc_node) free_tx_frag_desc[XLR_MAX_CORE] =
+{
+ TAILQ_HEAD_INITIALIZER(free_tx_frag_desc[0]),
+ TAILQ_HEAD_INITIALIZER(free_tx_frag_desc[1]),
+ TAILQ_HEAD_INITIALIZER(free_tx_frag_desc[2]),
+ TAILQ_HEAD_INITIALIZER(free_tx_frag_desc[3]),
+ TAILQ_HEAD_INITIALIZER(free_tx_frag_desc[4]),
+ TAILQ_HEAD_INITIALIZER(free_tx_frag_desc[5]),
+ TAILQ_HEAD_INITIALIZER(free_tx_frag_desc[6]),
+ TAILQ_HEAD_INITIALIZER(free_tx_frag_desc[7]),
+};
+
+static struct mtx tx_desc_lock[XLR_MAX_CORE];
+
+static inline void
+mac_make_desc_rfr(struct msgrng_msg *msg,
+ vm_paddr_t addr)
+{
+ msg->msg0 = (uint64_t) addr & 0xffffffffe0ULL;
+ msg->msg1 = msg->msg2 = msg->msg3 = 0;
+}
+
+#define MAC_TX_DESC_ALIGNMENT (XLR_CACHELINE_SIZE - 1)
+
+static void
+init_p2d_allocation(void)
+{
+ int active_core[8] = {0};
+ int i = 0;
+ uint32_t cpumask;
+ int cpu;
+
+ cpumask = xlr_hw_thread_mask;
+
+ for (i = 0; i < 32; i++) {
+ if (cpumask & (1 << i)) {
+ cpu = i;
+ if (!active_core[cpu / 4]) {
+ active_core[cpu / 4] = 1;
+ xlr_total_active_core++;
+ }
+ }
+ }
+ for (i = 0; i < XLR_MAX_CORE; i++) {
+ if (active_core[i])
+ xlr_tot_avail_p2d[i] = XLR_MAX_TX_DESC_NODES / xlr_total_active_core;
+ }
+ printf("Total Active Core %d\n", xlr_total_active_core);
+}
+
+
+static void
+init_tx_ring(void)
+{
+ int i;
+ int j = 0;
+ struct tx_desc_node *start, *node;
+ struct p2d_tx_desc *tx_desc;
+ vm_paddr_t paddr;
+ vm_offset_t unmapped_addr;
+
+ for (i = 0; i < XLR_MAX_CORE; i++)
+ mtx_init(&tx_desc_lock[i], "xlr tx_desc", NULL, MTX_SPIN);
+
+ start = &tx_desc_nodes[0];
+ /* TODO: try to get this from KSEG0 */
+ xlr_tx_ring_mem = contigmalloc((MAX_TX_RING_SIZE + XLR_CACHELINE_SIZE),
+ M_DEVBUF, M_NOWAIT | M_ZERO, 0,
+ 0x10000000, XLR_CACHELINE_SIZE, 0);
+
+ if (xlr_tx_ring_mem == NULL) {
+ panic("TX ring memory allocation failed");
+ }
+ paddr = vtophys((vm_offset_t)xlr_tx_ring_mem);
+
+ unmapped_addr = MIPS_PHYS_TO_KSEG0(paddr);
+
+
+ tx_desc = (struct p2d_tx_desc *)unmapped_addr;
+
+ for (i = 0; i < XLR_MAX_TX_DESC_NODES; i++) {
+ node = start + i;
+ node->ptr = tx_desc;
+ tx_desc++;
+ TAILQ_INSERT_HEAD(&tx_frag_desc[j], node, list);
+ j = (i / (XLR_MAX_TX_DESC_NODES / xlr_total_active_core));
+ }
+}
+
+static inline struct p2d_tx_desc *
+get_p2d_desc(void)
+{
+ struct tx_desc_node *node;
+ struct p2d_tx_desc *tx_desc = NULL;
+ int cpu = xlr_core_id();
+
+ mtx_lock_spin(&tx_desc_lock[cpu]);
+ node = TAILQ_FIRST(&tx_frag_desc[cpu]);
+ if (node) {
+ xlr_tot_avail_p2d[cpu]--;
+ TAILQ_REMOVE(&tx_frag_desc[cpu], node, list);
+ tx_desc = node->ptr;
+ TAILQ_INSERT_HEAD(&free_tx_frag_desc[cpu], node, list);
+ } else {
+ /* Increment p2d desc fail count */
+ get_p2d_desc_failed++;
+ }
+ mtx_unlock_spin(&tx_desc_lock[cpu]);
+ return tx_desc;
+}
+static void
+free_p2d_desc(struct p2d_tx_desc *tx_desc)
+{
+ struct tx_desc_node *node;
+ int cpu = xlr_core_id();
+
+ mtx_lock_spin(&tx_desc_lock[cpu]);
+ node = TAILQ_FIRST(&free_tx_frag_desc[cpu]);
+ KASSERT((node != NULL), ("Free TX frag node list is empty\n"));
+
+ TAILQ_REMOVE(&free_tx_frag_desc[cpu], node, list);
+ node->ptr = tx_desc;
+ TAILQ_INSERT_HEAD(&tx_frag_desc[cpu], node, list);
+ xlr_tot_avail_p2d[cpu]++;
+ mtx_unlock_spin(&tx_desc_lock[cpu]);
+
+}
+
+static int
+build_frag_list(struct mbuf *m_head, struct msgrng_msg *p2p_msg, struct p2d_tx_desc *tx_desc)
+{
+ struct mbuf *m;
+ vm_paddr_t paddr;
+ uint64_t p2d_len;
+ int nfrag;
+ vm_paddr_t p1, p2;
+ uint32_t len1, len2;
+ vm_offset_t taddr;
+ uint64_t fr_stid;
+
+ fr_stid = (xlr_core_id() << 3) + xlr_thr_id() + 4;
+
+ if (tx_desc == NULL)
+ return 1;
+
+ nfrag = 0;
+ for (m = m_head; m != NULL; m = m->m_next) {
+ if ((nfrag + 1) >= XLR_MAX_TX_FRAGS) {
+ free_p2d_desc(tx_desc);
+ return 1;
+ }
+ if (m->m_len != 0) {
+ paddr = vtophys(mtod(m, vm_offset_t));
+ p1 = paddr + m->m_len;
+ p2 = vtophys(((vm_offset_t)m->m_data + m->m_len));
+ if (p1 != p2) {
+ len1 = (uint32_t)
+ (PAGE_SIZE - (paddr & PAGE_MASK));
+ tx_desc->frag[nfrag] = (127ULL << 54) |
+ ((uint64_t) len1 << 40) | paddr;
+ nfrag++;
+ taddr = (vm_offset_t)m->m_data + len1;
+ p2 = vtophys(taddr);
+ len2 = m->m_len - len1;
+ if (len2 == 0)
+ continue;
+ if (nfrag >= XLR_MAX_TX_FRAGS)
+ panic("TX frags exceeded");
+
+ tx_desc->frag[nfrag] = (127ULL << 54) |
+ ((uint64_t) len2 << 40) | p2;
+
+ taddr += len2;
+ p1 = vtophys(taddr);
+
+ if ((p2 + len2) != p1) {
+ printf("p1 = %p p2 = %p\n", (void *)p1, (void *)p2);
+ printf("len1 = %x len2 = %x\n", len1,
+ len2);
+ printf("m_data %p\n", m->m_data);
+ DELAY(1000000);
+ panic("Multiple Mbuf segment discontiguous\n");
+ }
+ } else {
+ tx_desc->frag[nfrag] = (127ULL << 54) |
+ ((uint64_t) m->m_len << 40) | paddr;
+ }
+ nfrag++;
+ }
+ }
+ /* set eop in the last tx p2d desc */
+ tx_desc->frag[nfrag - 1] |= (1ULL << 63);
+ paddr = vtophys((vm_offset_t)tx_desc);
+ tx_desc->frag[nfrag] = (1ULL << 63) | (fr_stid << 54) | paddr;
+ nfrag++;
+ tx_desc->frag[XLR_MAX_TX_FRAGS] = (uint64_t)(intptr_t)tx_desc;
+ tx_desc->frag[XLR_MAX_TX_FRAGS + 1] = (uint64_t)(intptr_t)m_head;
+
+ p2d_len = (nfrag * 8);
+ p2p_msg->msg0 = (1ULL << 63) | (1ULL << 62) | (127ULL << 54) |
+ (p2d_len << 40) | paddr;
+
+ return 0;
+}
+static void
+release_tx_desc(struct msgrng_msg *msg, int rel_buf)
+{
+ struct p2d_tx_desc *tx_desc, *chk_addr;
+ struct mbuf *m;
+
+ tx_desc = (struct p2d_tx_desc *)MIPS_PHYS_TO_KSEG0(msg->msg0);
+ chk_addr = (struct p2d_tx_desc *)(intptr_t)tx_desc->frag[XLR_MAX_TX_FRAGS];
+ if (tx_desc != chk_addr) {
+ printf("Address %p does not match with stored addr %p - we leaked a descriptor\n",
+ tx_desc, chk_addr);
+ return;
+ }
+ if (rel_buf) {
+ m = (struct mbuf *)(intptr_t)tx_desc->frag[XLR_MAX_TX_FRAGS + 1];
+ m_freem(m);
+ }
+ free_p2d_desc(tx_desc);
+}
+
+
+static struct mbuf *
+get_mbuf(void)
+{
+ struct mbuf *m_new = NULL;
+
+ if ((m_new = m_getcl(M_NOWAIT, MT_DATA, M_PKTHDR)) == NULL)
+ return NULL;
+
+ m_new->m_len = MCLBYTES;
+ m_new->m_len = m_new->m_pkthdr.len = MCLBYTES;
+ return m_new;
+}
+
+static void
+free_buf(vm_paddr_t paddr)
+{
+ struct mbuf *m;
+ uint64_t mag;
+ uint32_t sr;
+
+ sr = xlr_enable_kx();
+ m = (struct mbuf *)(intptr_t)xlr_paddr_ld(paddr - XLR_CACHELINE_SIZE);
+ mag = xlr_paddr_ld(paddr - XLR_CACHELINE_SIZE + sizeof(uint64_t));
+ xlr_restore_kx(sr);
+ if (mag != 0xf00bad) {
+ printf("Something is wrong kseg:%lx found mag:%lx not 0xf00bad\n",
+ (u_long)paddr, (u_long)mag);
+ return;
+ }
+ if (m != NULL)
+ m_freem(m);
+}
+
+static void *
+get_buf(void)
+{
+ struct mbuf *m_new = NULL;
+ uint64_t *md;
+#ifdef INVARIANTS
+ vm_paddr_t temp1, temp2;
+#endif
+
+ m_new = get_mbuf();
+ if (m_new == NULL)
+ return NULL;
+
+ m_adj(m_new, XLR_CACHELINE_SIZE - ((uintptr_t)m_new->m_data & 0x1f));
+ md = (uint64_t *)m_new->m_data;
+ md[0] = (uintptr_t)m_new; /* Back Ptr */
+ md[1] = 0xf00bad;
+ m_adj(m_new, XLR_CACHELINE_SIZE);
+
+#ifdef INVARIANTS
+ temp1 = vtophys((vm_offset_t)m_new->m_data);
+ temp2 = vtophys((vm_offset_t)m_new->m_data + 1536);
+ if ((temp1 + 1536) != temp2)
+ panic("ALLOCED BUFFER IS NOT CONTIGUOUS\n");
+#endif
+ return (void *)m_new->m_data;
+}
+
+/**********************************************************************
+ **********************************************************************/
+static void
+rmi_xlr_mac_set_enable(struct driver_data *priv, int flag)
+{
+ uint32_t regval;
+ int tx_threshold = 1518;
+
+ if (flag) {
+ regval = xlr_read_reg(priv->mmio, R_TX_CONTROL);
+ regval |= (1 << O_TX_CONTROL__TxEnable) |
+ (tx_threshold << O_TX_CONTROL__TxThreshold);
+
+ xlr_write_reg(priv->mmio, R_TX_CONTROL, regval);
+
+ regval = xlr_read_reg(priv->mmio, R_RX_CONTROL);
+ regval |= 1 << O_RX_CONTROL__RxEnable;
+ if (priv->mode == XLR_PORT0_RGMII)
+ regval |= 1 << O_RX_CONTROL__RGMII;
+ xlr_write_reg(priv->mmio, R_RX_CONTROL, regval);
+
+ regval = xlr_read_reg(priv->mmio, R_MAC_CONFIG_1);
+ regval |= (O_MAC_CONFIG_1__txen | O_MAC_CONFIG_1__rxen);
+ xlr_write_reg(priv->mmio, R_MAC_CONFIG_1, regval);
+ } else {
+ regval = xlr_read_reg(priv->mmio, R_TX_CONTROL);
+ regval &= ~((1 << O_TX_CONTROL__TxEnable) |
+ (tx_threshold << O_TX_CONTROL__TxThreshold));
+
+ xlr_write_reg(priv->mmio, R_TX_CONTROL, regval);
+
+ regval = xlr_read_reg(priv->mmio, R_RX_CONTROL);
+ regval &= ~(1 << O_RX_CONTROL__RxEnable);
+ xlr_write_reg(priv->mmio, R_RX_CONTROL, regval);
+
+ regval = xlr_read_reg(priv->mmio, R_MAC_CONFIG_1);
+ regval &= ~(O_MAC_CONFIG_1__txen | O_MAC_CONFIG_1__rxen);
+ xlr_write_reg(priv->mmio, R_MAC_CONFIG_1, regval);
+ }
+}
+
+/**********************************************************************
+ **********************************************************************/
+static __inline__ int
+xlr_mac_send_fr(struct driver_data *priv,
+ vm_paddr_t addr, int len)
+{
+ struct msgrng_msg msg;
+ int stid = priv->rfrbucket;
+ int code, ret;
+ uint32_t msgrng_flags;
+#ifdef INVARIANTS
+ int i = 0;
+#endif
+
+ mac_make_desc_rfr(&msg, addr);
+
+ /* Send the packet to MAC */
+ dbg_msg("mac_%d: Sending free packet %lx to stid %d\n",
+ priv->instance, (u_long)addr, stid);
+ if (priv->type == XLR_XGMAC)
+ code = MSGRNG_CODE_XGMAC; /* WHY? */
+ else
+ code = MSGRNG_CODE_MAC;
+
+ do {
+ msgrng_flags = msgrng_access_enable();
+ ret = message_send(1, code, stid, &msg);
+ msgrng_restore(msgrng_flags);
+ KASSERT(i++ < 100000, ("Too many credit fails\n"));
+ } while (ret != 0);
+
+ return 0;
+}
+
+/**************************************************************/
+
+static void
+xgmac_mdio_setup(volatile unsigned int *_mmio)
+{
+ int i;
+ uint32_t rd_data;
+
+ for (i = 0; i < 4; i++) {
+ rd_data = xmdio_read(_mmio, 1, 0x8000 + i);
+ rd_data = rd_data & 0xffffdfff; /* clear isolate bit */
+ xmdio_write(_mmio, 1, 0x8000 + i, rd_data);
+ }
+}
+
+/**********************************************************************
+ * Init MII interface
+ *
+ * Input parameters:
+ * s - priv structure
+ ********************************************************************* */
+#define PHY_STATUS_RETRIES 25000
+
+static void
+rmi_xlr_mac_mii_init(struct driver_data *priv)
+{
+ xlr_reg_t *mii_mmio = priv->mii_mmio;
+
+ /* use the lowest clock divisor - divisor 28 */
+ xlr_write_reg(mii_mmio, R_MII_MGMT_CONFIG, 0x07);
+}
+
+/**********************************************************************
+ * Read a PHY register.
+ *
+ * Input parameters:
+ * s - priv structure
+ * phyaddr - PHY's address
+ * regidx = index of register to read
+ *
+ * Return value:
+ * value read, or 0 if an error occurred.
+ ********************************************************************* */
+
+static int
+rge_mii_read_internal(xlr_reg_t * mii_mmio, int phyaddr, int regidx)
+{
+ int i = 0;
+
+ /* setup the phy reg to be used */
+ xlr_write_reg(mii_mmio, R_MII_MGMT_ADDRESS,
+ (phyaddr << 8) | (regidx << 0));
+ /* Issue the read command */
+ xlr_write_reg(mii_mmio, R_MII_MGMT_COMMAND,
+ (1 << O_MII_MGMT_COMMAND__rstat));
+
+ /* poll for the read cycle to complete */
+ for (i = 0; i < PHY_STATUS_RETRIES; i++) {
+ if (xlr_read_reg(mii_mmio, R_MII_MGMT_INDICATORS) == 0)
+ break;
+ }
+
+ /* clear the read cycle */
+ xlr_write_reg(mii_mmio, R_MII_MGMT_COMMAND, 0);
+
+ if (i == PHY_STATUS_RETRIES) {
+ return 0xffffffff;
+ }
+ /* Read the data back */
+ return xlr_read_reg(mii_mmio, R_MII_MGMT_STATUS);
+}
+
+static int
+rge_mii_read(device_t dev, int phyaddr, int regidx)
+{
+ struct rge_softc *sc = device_get_softc(dev);
+
+ return rge_mii_read_internal(sc->priv.mii_mmio, phyaddr, regidx);
+}
+
+/**********************************************************************
+ * Set MII hooks to newly selected media
+ *
+ * Input parameters:
+ * ifp - Interface Pointer
+ *
+ * Return value:
+ * nothing
+ ********************************************************************* */
+static int
+rmi_xlr_mac_mediachange(struct ifnet *ifp)
+{
+ struct rge_softc *sc = ifp->if_softc;
+
+ if (ifp->if_flags & IFF_UP)
+ mii_mediachg(&sc->rge_mii);
+
+ return 0;
+}
+
+/**********************************************************************
+ * Get the current interface media status
+ *
+ * Input parameters:
+ * ifp - Interface Pointer
+ * ifmr - Interface media request ptr
+ *
+ * Return value:
+ * nothing
+ ********************************************************************* */
+static void
+rmi_xlr_mac_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr)
+{
+ struct rge_softc *sc = ifp->if_softc;
+
+ /* Check whether this is interface is active or not. */
+ ifmr->ifm_status = IFM_AVALID;
+ if (sc->link_up) {
+ ifmr->ifm_status |= IFM_ACTIVE;
+ } else {
+ ifmr->ifm_active = IFM_ETHER;
+ }
+}
+
+/**********************************************************************
+ * Write a value to a PHY register.
+ *
+ * Input parameters:
+ * s - priv structure
+ * phyaddr - PHY to use
+ * regidx - register within the PHY
+ * regval - data to write to register
+ *
+ * Return value:
+ * nothing
+ ********************************************************************* */
+static void
+rge_mii_write_internal(xlr_reg_t * mii_mmio, int phyaddr, int regidx, int regval)
+{
+ int i = 0;
+
+ xlr_write_reg(mii_mmio, R_MII_MGMT_ADDRESS,
+ (phyaddr << 8) | (regidx << 0));
+
+ /* Write the data which starts the write cycle */
+ xlr_write_reg(mii_mmio, R_MII_MGMT_WRITE_DATA, regval);
+
+ /* poll for the write cycle to complete */
+ for (i = 0; i < PHY_STATUS_RETRIES; i++) {
+ if (xlr_read_reg(mii_mmio, R_MII_MGMT_INDICATORS) == 0)
+ break;
+ }
+
+ return;
+}
+
+static int
+rge_mii_write(device_t dev, int phyaddr, int regidx, int regval)
+{
+ struct rge_softc *sc = device_get_softc(dev);
+
+ rge_mii_write_internal(sc->priv.mii_mmio, phyaddr, regidx, regval);
+ return (0);
+}
+
+static void
+rmi_xlr_mac_mii_statchg(struct device *dev)
+{
+}
+
+static void
+serdes_regs_init(struct driver_data *priv)
+{
+ xlr_reg_t *mmio_gpio = (xlr_reg_t *) (xlr_io_base + XLR_IO_GPIO_OFFSET);
+
+ /* Initialize SERDES CONTROL Registers */
+ rge_mii_write_internal(priv->serdes_mmio, 26, 0, 0x6DB0);
+ rge_mii_write_internal(priv->serdes_mmio, 26, 1, 0xFFFF);
+ rge_mii_write_internal(priv->serdes_mmio, 26, 2, 0xB6D0);
+ rge_mii_write_internal(priv->serdes_mmio, 26, 3, 0x00FF);
+ rge_mii_write_internal(priv->serdes_mmio, 26, 4, 0x0000);
+ rge_mii_write_internal(priv->serdes_mmio, 26, 5, 0x0000);
+ rge_mii_write_internal(priv->serdes_mmio, 26, 6, 0x0005);
+ rge_mii_write_internal(priv->serdes_mmio, 26, 7, 0x0001);
+ rge_mii_write_internal(priv->serdes_mmio, 26, 8, 0x0000);
+ rge_mii_write_internal(priv->serdes_mmio, 26, 9, 0x0000);
+ rge_mii_write_internal(priv->serdes_mmio, 26, 10, 0x0000);
+
+ /*
+ * GPIO setting which affect the serdes - needs figuring out
+ */
+ DELAY(100);
+ xlr_write_reg(mmio_gpio, 0x20, 0x7e6802);
+ xlr_write_reg(mmio_gpio, 0x10, 0x7104);
+ DELAY(100);
+
+ /*
+ * This kludge is needed to setup serdes (?) clock correctly on some
+ * XLS boards
+ */
+ if ((xlr_boot1_info.board_major_version == RMI_XLR_BOARD_ARIZONA_XI ||
+ xlr_boot1_info.board_major_version == RMI_XLR_BOARD_ARIZONA_XII) &&
+ xlr_boot1_info.board_minor_version == 4) {
+ /* use 125 Mhz instead of 156.25Mhz ref clock */
+ DELAY(100);
+ xlr_write_reg(mmio_gpio, 0x10, 0x7103);
+ xlr_write_reg(mmio_gpio, 0x21, 0x7103);
+ DELAY(100);
+ }
+
+ return;
+}
+
+static void
+serdes_autoconfig(struct driver_data *priv)
+{
+ int delay = 100000;
+
+ /* Enable Auto negotiation in the PCS Layer */
+ rge_mii_write_internal(priv->pcs_mmio, 27, 0, 0x1000);
+ DELAY(delay);
+ rge_mii_write_internal(priv->pcs_mmio, 27, 0, 0x0200);
+ DELAY(delay);
+
+ rge_mii_write_internal(priv->pcs_mmio, 28, 0, 0x1000);
+ DELAY(delay);
+ rge_mii_write_internal(priv->pcs_mmio, 28, 0, 0x0200);
+ DELAY(delay);
+
+ rge_mii_write_internal(priv->pcs_mmio, 29, 0, 0x1000);
+ DELAY(delay);
+ rge_mii_write_internal(priv->pcs_mmio, 29, 0, 0x0200);
+ DELAY(delay);
+
+ rge_mii_write_internal(priv->pcs_mmio, 30, 0, 0x1000);
+ DELAY(delay);
+ rge_mii_write_internal(priv->pcs_mmio, 30, 0, 0x0200);
+ DELAY(delay);
+
+}
+
+/*****************************************************************
+ * Initialize GMAC
+ *****************************************************************/
+static void
+rmi_xlr_config_pde(struct driver_data *priv)
+{
+ int i = 0, cpu = 0, bucket = 0;
+ uint64_t bucket_map = 0;
+
+ /* uint32_t desc_pack_ctrl = 0; */
+ uint32_t cpumask;
+
+ cpumask = 0x1;
+#ifdef SMP
+ /*
+ * rge may be called before SMP start in a BOOTP/NFSROOT
+ * setup. we will distribute packets to other cpus only when
+ * the SMP is started.
+ */
+ if (smp_started)
+ cpumask = xlr_hw_thread_mask;
+#endif
+
+ for (i = 0; i < MAXCPU; i++) {
+ if (cpumask & (1 << i)) {
+ cpu = i;
+ bucket = ((cpu >> 2) << 3);
+ bucket_map |= (3ULL << bucket);
+ }
+ }
+ printf("rmi_xlr_config_pde: bucket_map=%jx\n", (uintmax_t)bucket_map);
+
+ /* bucket_map = 0x1; */
+ xlr_write_reg(priv->mmio, R_PDE_CLASS_0, (bucket_map & 0xffffffff));
+ xlr_write_reg(priv->mmio, R_PDE_CLASS_0 + 1,
+ ((bucket_map >> 32) & 0xffffffff));
+
+ xlr_write_reg(priv->mmio, R_PDE_CLASS_1, (bucket_map & 0xffffffff));
+ xlr_write_reg(priv->mmio, R_PDE_CLASS_1 + 1,
+ ((bucket_map >> 32) & 0xffffffff));
+
+ xlr_write_reg(priv->mmio, R_PDE_CLASS_2, (bucket_map & 0xffffffff));
+ xlr_write_reg(priv->mmio, R_PDE_CLASS_2 + 1,
+ ((bucket_map >> 32) & 0xffffffff));
+
+ xlr_write_reg(priv->mmio, R_PDE_CLASS_3, (bucket_map & 0xffffffff));
+ xlr_write_reg(priv->mmio, R_PDE_CLASS_3 + 1,
+ ((bucket_map >> 32) & 0xffffffff));
+}
+
+static void
+rge_smp_update_pde(void *dummy __unused)
+{
+ int i;
+ struct driver_data *priv;
+ struct rge_softc *sc;
+
+ printf("Updating packet distribution for SMP\n");
+ for (i = 0; i < XLR_MAX_MACS; i++) {
+ sc = dev_mac[i];
+ if (!sc)
+ continue;
+ priv = &(sc->priv);
+ rmi_xlr_mac_set_enable(priv, 0);
+ rmi_xlr_config_pde(priv);
+ rmi_xlr_mac_set_enable(priv, 1);
+ }
+}
+
+SYSINIT(rge_smp_update_pde, SI_SUB_SMP, SI_ORDER_ANY, rge_smp_update_pde, NULL);
+
+
+static void
+rmi_xlr_config_parser(struct driver_data *priv)
+{
+ /*
+ * Mark it as no classification The parser extract is gauranteed to
+ * be zero with no classfication
+ */
+ xlr_write_reg(priv->mmio, R_L2TYPE_0, 0x00);
+
+ xlr_write_reg(priv->mmio, R_L2TYPE_0, 0x01);
+
+ /* configure the parser : L2 Type is configured in the bootloader */
+ /* extract IP: src, dest protocol */
+ xlr_write_reg(priv->mmio, R_L3CTABLE,
+ (9 << 20) | (1 << 19) | (1 << 18) | (0x01 << 16) |
+ (0x0800 << 0));
+ xlr_write_reg(priv->mmio, R_L3CTABLE + 1,
+ (12 << 25) | (4 << 21) | (16 << 14) | (4 << 10));
+
+}
+
+static void
+rmi_xlr_config_classifier(struct driver_data *priv)
+{
+ int i = 0;
+
+ if (priv->type == XLR_XGMAC) {
+ /* xgmac translation table doesn't have sane values on reset */
+ for (i = 0; i < 64; i++)
+ xlr_write_reg(priv->mmio, R_TRANSLATETABLE + i, 0x0);
+
+ /*
+ * use upper 7 bits of the parser extract to index the
+ * translate table
+ */
+ xlr_write_reg(priv->mmio, R_PARSERCONFIGREG, 0x0);
+ }
+}
+
+enum {
+ SGMII_SPEED_10 = 0x00000000,
+ SGMII_SPEED_100 = 0x02000000,
+ SGMII_SPEED_1000 = 0x04000000,
+};
+
+static void
+rmi_xlr_gmac_config_speed(struct driver_data *priv)
+{
+ int phy_addr = priv->phy_addr;
+ xlr_reg_t *mmio = priv->mmio;
+ struct rge_softc *sc = priv->sc;
+
+ priv->speed = rge_mii_read_internal(priv->mii_mmio, phy_addr, 28);
+ priv->link = rge_mii_read_internal(priv->mii_mmio, phy_addr, 1) & 0x4;
+ priv->speed = (priv->speed >> 3) & 0x03;
+
+ if (priv->speed == xlr_mac_speed_10) {
+ if (priv->mode != XLR_RGMII)
+ xlr_write_reg(mmio, R_INTERFACE_CONTROL, SGMII_SPEED_10);
+ xlr_write_reg(mmio, R_MAC_CONFIG_2, 0x7117);
+ xlr_write_reg(mmio, R_CORECONTROL, 0x02);
+ printf("%s: [10Mbps]\n", device_get_nameunit(sc->rge_dev));
+ sc->rge_mii.mii_media.ifm_media = IFM_ETHER | IFM_AUTO | IFM_10_T | IFM_FDX;
+ sc->rge_mii.mii_media.ifm_cur->ifm_media = IFM_ETHER | IFM_AUTO | IFM_10_T | IFM_FDX;
+ sc->rge_mii.mii_media_active = IFM_ETHER | IFM_AUTO | IFM_10_T | IFM_FDX;
+ } else if (priv->speed == xlr_mac_speed_100) {
+ if (priv->mode != XLR_RGMII)
+ xlr_write_reg(mmio, R_INTERFACE_CONTROL, SGMII_SPEED_100);
+ xlr_write_reg(mmio, R_MAC_CONFIG_2, 0x7117);
+ xlr_write_reg(mmio, R_CORECONTROL, 0x01);
+ printf("%s: [100Mbps]\n", device_get_nameunit(sc->rge_dev));
+ sc->rge_mii.mii_media.ifm_media = IFM_ETHER | IFM_AUTO | IFM_100_TX | IFM_FDX;
+ sc->rge_mii.mii_media.ifm_cur->ifm_media = IFM_ETHER | IFM_AUTO | IFM_100_TX | IFM_FDX;
+ sc->rge_mii.mii_media_active = IFM_ETHER | IFM_AUTO | IFM_100_TX | IFM_FDX;
+ } else {
+ if (priv->speed != xlr_mac_speed_1000) {
+ if (priv->mode != XLR_RGMII)
+ xlr_write_reg(mmio, R_INTERFACE_CONTROL, SGMII_SPEED_100);
+ printf("PHY reported unknown MAC speed, defaulting to 100Mbps\n");
+ xlr_write_reg(mmio, R_MAC_CONFIG_2, 0x7117);
+ xlr_write_reg(mmio, R_CORECONTROL, 0x01);
+ sc->rge_mii.mii_media.ifm_media = IFM_ETHER | IFM_AUTO | IFM_100_TX | IFM_FDX;
+ sc->rge_mii.mii_media.ifm_cur->ifm_media = IFM_ETHER | IFM_AUTO | IFM_100_TX | IFM_FDX;
+ sc->rge_mii.mii_media_active = IFM_ETHER | IFM_AUTO | IFM_100_TX | IFM_FDX;
+ } else {
+ if (priv->mode != XLR_RGMII)
+ xlr_write_reg(mmio, R_INTERFACE_CONTROL, SGMII_SPEED_1000);
+ xlr_write_reg(mmio, R_MAC_CONFIG_2, 0x7217);
+ xlr_write_reg(mmio, R_CORECONTROL, 0x00);
+ printf("%s: [1000Mbps]\n", device_get_nameunit(sc->rge_dev));
+ sc->rge_mii.mii_media.ifm_media = IFM_ETHER | IFM_AUTO | IFM_1000_T | IFM_FDX;
+ sc->rge_mii.mii_media.ifm_cur->ifm_media = IFM_ETHER | IFM_AUTO | IFM_1000_T | IFM_FDX;
+ sc->rge_mii.mii_media_active = IFM_ETHER | IFM_AUTO | IFM_1000_T | IFM_FDX;
+ }
+ }
+
+ if (!priv->link) {
+ sc->rge_mii.mii_media.ifm_cur->ifm_media = IFM_ETHER;
+ sc->link_up = 0;
+ } else {
+ sc->link_up = 1;
+ }
+}
+
+/*****************************************************************
+ * Initialize XGMAC
+ *****************************************************************/
+static void
+rmi_xlr_xgmac_init(struct driver_data *priv)
+{
+ int i = 0;
+ xlr_reg_t *mmio = priv->mmio;
+ int id = priv->instance;
+ struct rge_softc *sc = priv->sc;
+ volatile unsigned short *cpld;
+
+ cpld = (volatile unsigned short *)0xBD840000;
+
+ xlr_write_reg(priv->mmio, R_DESC_PACK_CTRL,
+ (MAX_FRAME_SIZE << O_DESC_PACK_CTRL__RegularSize) | (4 << 20));
+ xlr_write_reg(priv->mmio, R_BYTEOFFSET0, BYTE_OFFSET);
+ rmi_xlr_config_pde(priv);
+ rmi_xlr_config_parser(priv);
+ rmi_xlr_config_classifier(priv);
+
+ xlr_write_reg(priv->mmio, R_MSG_TX_THRESHOLD, 1);
+
+ /* configure the XGMAC Registers */
+ xlr_write_reg(mmio, R_XGMAC_CONFIG_1, 0x50000026);
+
+ /* configure the XGMAC_GLUE Registers */
+ xlr_write_reg(mmio, R_DMACR0, 0xffffffff);
+ xlr_write_reg(mmio, R_DMACR1, 0xffffffff);
+ xlr_write_reg(mmio, R_DMACR2, 0xffffffff);
+ xlr_write_reg(mmio, R_DMACR3, 0xffffffff);
+ xlr_write_reg(mmio, R_STATCTRL, 0x04);
+ xlr_write_reg(mmio, R_L2ALLOCCTRL, 0xffffffff);
+
+ xlr_write_reg(mmio, R_XGMACPADCALIBRATION, 0x030);
+ xlr_write_reg(mmio, R_EGRESSFIFOCARVINGSLOTS, 0x0f);
+ xlr_write_reg(mmio, R_L2ALLOCCTRL, 0xffffffff);
+ xlr_write_reg(mmio, R_XGMAC_MIIM_CONFIG, 0x3e);
+
+ /*
+ * take XGMII phy out of reset
+ */
+ /*
+ * we are pulling everything out of reset because writing a 0 would
+ * reset other devices on the chip
+ */
+ cpld[ATX_CPLD_RESET_1] = 0xffff;
+ cpld[ATX_CPLD_MISC_CTRL] = 0xffff;
+ cpld[ATX_CPLD_RESET_2] = 0xffff;
+
+ xgmac_mdio_setup(mmio);
+
+ rmi_xlr_config_spill_area(priv);
+
+ if (id == 0) {
+ for (i = 0; i < 16; i++) {
+ xlr_write_reg(mmio, R_XGS_TX0_BUCKET_SIZE + i,
+ bucket_sizes.
+ bucket[MSGRNG_STNID_XGS0_TX + i]);
+ }
+
+ xlr_write_reg(mmio, R_XGS_JFR_BUCKET_SIZE,
+ bucket_sizes.bucket[MSGRNG_STNID_XMAC0JFR]);
+ xlr_write_reg(mmio, R_XGS_RFR_BUCKET_SIZE,
+ bucket_sizes.bucket[MSGRNG_STNID_XMAC0RFR]);
+
+ for (i = 0; i < MAX_NUM_MSGRNG_STN_CC; i++) {
+ xlr_write_reg(mmio, R_CC_CPU0_0 + i,
+ cc_table_xgs_0.
+ counters[i >> 3][i & 0x07]);
+ }
+ } else if (id == 1) {
+ for (i = 0; i < 16; i++) {
+ xlr_write_reg(mmio, R_XGS_TX0_BUCKET_SIZE + i,
+ bucket_sizes.
+ bucket[MSGRNG_STNID_XGS1_TX + i]);
+ }
+
+ xlr_write_reg(mmio, R_XGS_JFR_BUCKET_SIZE,
+ bucket_sizes.bucket[MSGRNG_STNID_XMAC1JFR]);
+ xlr_write_reg(mmio, R_XGS_RFR_BUCKET_SIZE,
+ bucket_sizes.bucket[MSGRNG_STNID_XMAC1RFR]);
+
+ for (i = 0; i < MAX_NUM_MSGRNG_STN_CC; i++) {
+ xlr_write_reg(mmio, R_CC_CPU0_0 + i,
+ cc_table_xgs_1.
+ counters[i >> 3][i & 0x07]);
+ }
+ }
+ sc->rge_mii.mii_media.ifm_media = IFM_ETHER | IFM_AUTO | IFM_10G_SR | IFM_FDX;
+ sc->rge_mii.mii_media.ifm_media |= (IFM_AVALID | IFM_ACTIVE);
+ sc->rge_mii.mii_media.ifm_cur->ifm_media = IFM_ETHER | IFM_AUTO | IFM_10G_SR | IFM_FDX;
+ sc->rge_mii.mii_media_active = IFM_ETHER | IFM_AUTO | IFM_10G_SR | IFM_FDX;
+ sc->rge_mii.mii_media.ifm_cur->ifm_media |= (IFM_AVALID | IFM_ACTIVE);
+
+ priv->init_frin_desc = 1;
+}
+
+/*******************************************************
+ * Initialization gmac
+ *******************************************************/
+static int
+rmi_xlr_gmac_reset(struct driver_data *priv)
+{
+ volatile uint32_t val;
+ xlr_reg_t *mmio = priv->mmio;
+ int i, maxloops = 100;
+
+ /* Disable MAC RX */
+ val = xlr_read_reg(mmio, R_MAC_CONFIG_1);
+ val &= ~0x4;
+ xlr_write_reg(mmio, R_MAC_CONFIG_1, val);
+
+ /* Disable Core RX */
+ val = xlr_read_reg(mmio, R_RX_CONTROL);
+ val &= ~0x1;
+ xlr_write_reg(mmio, R_RX_CONTROL, val);
+
+ /* wait for rx to halt */
+ for (i = 0; i < maxloops; i++) {
+ val = xlr_read_reg(mmio, R_RX_CONTROL);
+ if (val & 0x2)
+ break;
+ DELAY(1000);
+ }
+ if (i == maxloops)
+ return -1;
+
+ /* Issue a soft reset */
+ val = xlr_read_reg(mmio, R_RX_CONTROL);
+ val |= 0x4;
+ xlr_write_reg(mmio, R_RX_CONTROL, val);
+
+ /* wait for reset to complete */
+ for (i = 0; i < maxloops; i++) {
+ val = xlr_read_reg(mmio, R_RX_CONTROL);
+ if (val & 0x8)
+ break;
+ DELAY(1000);
+ }
+ if (i == maxloops)
+ return -1;
+
+ /* Clear the soft reset bit */
+ val = xlr_read_reg(mmio, R_RX_CONTROL);
+ val &= ~0x4;
+ xlr_write_reg(mmio, R_RX_CONTROL, val);
+ return 0;
+}
+
+static void
+rmi_xlr_gmac_init(struct driver_data *priv)
+{
+ int i = 0;
+ xlr_reg_t *mmio = priv->mmio;
+ int id = priv->instance;
+ struct stn_cc *gmac_cc_config;
+ uint32_t value = 0;
+ int blk = id / 4, port = id % 4;
+
+ rmi_xlr_mac_set_enable(priv, 0);
+
+ rmi_xlr_config_spill_area(priv);
+
+ xlr_write_reg(mmio, R_DESC_PACK_CTRL,
+ (BYTE_OFFSET << O_DESC_PACK_CTRL__ByteOffset) |
+ (1 << O_DESC_PACK_CTRL__MaxEntry) |
+ (MAX_FRAME_SIZE << O_DESC_PACK_CTRL__RegularSize));
+
+ rmi_xlr_config_pde(priv);
+ rmi_xlr_config_parser(priv);
+ rmi_xlr_config_classifier(priv);
+
+ xlr_write_reg(mmio, R_MSG_TX_THRESHOLD, 3);
+ xlr_write_reg(mmio, R_MAC_CONFIG_1, 0x35);
+ xlr_write_reg(mmio, R_RX_CONTROL, (0x7 << 6));
+
+ if (priv->mode == XLR_PORT0_RGMII) {
+ printf("Port 0 set in RGMII mode\n");
+ value = xlr_read_reg(mmio, R_RX_CONTROL);
+ value |= 1 << O_RX_CONTROL__RGMII;
+ xlr_write_reg(mmio, R_RX_CONTROL, value);
+ }
+ rmi_xlr_mac_mii_init(priv);
+
+
+#if 0
+ priv->advertising = ADVERTISED_10baseT_Full | ADVERTISED_10baseT_Half |
+ ADVERTISED_100baseT_Full | ADVERTISED_100baseT_Half |
+ ADVERTISED_1000baseT_Full | ADVERTISED_Autoneg |
+ ADVERTISED_MII;
+#endif
+
+ /*
+ * Enable all MDIO interrupts in the phy RX_ER bit seems to be get
+ * set about every 1 sec in GigE mode, ignore it for now...
+ */
+ rge_mii_write_internal(priv->mii_mmio, priv->phy_addr, 25, 0xfffffffe);
+
+ if (priv->mode != XLR_RGMII) {
+ serdes_regs_init(priv);
+ serdes_autoconfig(priv);
+ }
+ rmi_xlr_gmac_config_speed(priv);
+
+ value = xlr_read_reg(mmio, R_IPG_IFG);
+ xlr_write_reg(mmio, R_IPG_IFG, ((value & ~0x7f) | MAC_B2B_IPG));
+ xlr_write_reg(mmio, R_DMACR0, 0xffffffff);
+ xlr_write_reg(mmio, R_DMACR1, 0xffffffff);
+ xlr_write_reg(mmio, R_DMACR2, 0xffffffff);
+ xlr_write_reg(mmio, R_DMACR3, 0xffffffff);
+ xlr_write_reg(mmio, R_STATCTRL, 0x04);
+ xlr_write_reg(mmio, R_L2ALLOCCTRL, 0xffffffff);
+ xlr_write_reg(mmio, R_INTMASK, 0);
+ xlr_write_reg(mmio, R_FREEQCARVE, 0);
+
+ xlr_write_reg(mmio, R_GMAC_TX0_BUCKET_SIZE + port,
+ xlr_board_info.bucket_sizes->bucket[priv->txbucket]);
+ xlr_write_reg(mmio, R_GMAC_JFR0_BUCKET_SIZE,
+ xlr_board_info.bucket_sizes->bucket[MSGRNG_STNID_GMACJFR_0]);
+ xlr_write_reg(mmio, R_GMAC_RFR0_BUCKET_SIZE,
+ xlr_board_info.bucket_sizes->bucket[MSGRNG_STNID_GMACRFR_0]);
+ xlr_write_reg(mmio, R_GMAC_JFR1_BUCKET_SIZE,
+ xlr_board_info.bucket_sizes->bucket[MSGRNG_STNID_GMACJFR_1]);
+ xlr_write_reg(mmio, R_GMAC_RFR1_BUCKET_SIZE,
+ xlr_board_info.bucket_sizes->bucket[MSGRNG_STNID_GMACRFR_1]);
+
+ dbg_msg("Programming credit counter %d : %d -> %d\n", blk, R_GMAC_TX0_BUCKET_SIZE + port,
+ xlr_board_info.bucket_sizes->bucket[priv->txbucket]);
+
+ gmac_cc_config = xlr_board_info.gmac_block[blk].credit_config;
+ for (i = 0; i < MAX_NUM_MSGRNG_STN_CC; i++) {
+ xlr_write_reg(mmio, R_CC_CPU0_0 + i,
+ gmac_cc_config->counters[i >> 3][i & 0x07]);
+ dbg_msg("%d: %d -> %d\n", priv->instance,
+ R_CC_CPU0_0 + i, gmac_cc_config->counters[i >> 3][i & 0x07]);
+ }
+ priv->init_frin_desc = 1;
+}
+
+/**********************************************************************
+ * Set promiscuous mode
+ **********************************************************************/
+static void
+xlr_mac_set_rx_mode(struct rge_softc *sc)
+{
+ struct driver_data *priv = &(sc->priv);
+ uint32_t regval;
+
+ regval = xlr_read_reg(priv->mmio, R_MAC_FILTER_CONFIG);
+
+ if (sc->flags & IFF_PROMISC) {
+ regval |= (1 << O_MAC_FILTER_CONFIG__BROADCAST_EN) |
+ (1 << O_MAC_FILTER_CONFIG__PAUSE_FRAME_EN) |
+ (1 << O_MAC_FILTER_CONFIG__ALL_MCAST_EN) |
+ (1 << O_MAC_FILTER_CONFIG__ALL_UCAST_EN);
+ } else {
+ regval &= ~((1 << O_MAC_FILTER_CONFIG__PAUSE_FRAME_EN) |
+ (1 << O_MAC_FILTER_CONFIG__ALL_UCAST_EN));
+ }
+
+ xlr_write_reg(priv->mmio, R_MAC_FILTER_CONFIG, regval);
+}
+
+/**********************************************************************
+ * Configure LAN speed for the specified MAC.
+ ********************************************************************* */
+static int
+rmi_xlr_mac_set_speed(struct driver_data *s, xlr_mac_speed_t speed)
+{
+ return 0;
+}
+
+/**********************************************************************
+ * Set Ethernet duplex and flow control options for this MAC
+ ********************************************************************* */
+static int
+rmi_xlr_mac_set_duplex(struct driver_data *s,
+ xlr_mac_duplex_t duplex, xlr_mac_fc_t fc)
+{
+ return 0;
+}
+
+/*****************************************************************
+ * Kernel Net Stack <-> MAC Driver Interface
+ *****************************************************************/
+/**********************************************************************
+ **********************************************************************/
+#define MAC_TX_FAIL 2
+#define MAC_TX_PASS 0
+#define MAC_TX_RETRY 1
+
+int xlr_dev_queue_xmit_hack = 0;
+
+static int
+mac_xmit(struct mbuf *m, struct rge_softc *sc,
+ struct driver_data *priv, int len, struct p2d_tx_desc *tx_desc)
+{
+ struct msgrng_msg msg = {0,0,0,0};
+ int stid = priv->txbucket;
+ uint32_t tx_cycles = 0;
+ uint32_t mflags;
+ int vcpu = xlr_cpu_id();
+ int rv;
+
+ tx_cycles = mips_rd_count();
+
+ if (build_frag_list(m, &msg, tx_desc) != 0)
+ return MAC_TX_FAIL;
+
+ else {
+ mflags = msgrng_access_enable();
+ if ((rv = message_send(1, MSGRNG_CODE_MAC, stid, &msg)) != 0) {
+ msg_snd_failed++;
+ msgrng_restore(mflags);
+ release_tx_desc(&msg, 0);
+ xlr_rge_msg_snd_failed[vcpu]++;
+ dbg_msg("Failed packet to cpu %d, rv = %d, stid %d, msg0=%jx\n",
+ vcpu, rv, stid, (uintmax_t)msg.msg0);
+ return MAC_TX_FAIL;
+ }
+ msgrng_restore(mflags);
+ port_inc_counter(priv->instance, PORT_TX);
+ }
+
+ /* Send the packet to MAC */
+ dbg_msg("Sent tx packet to stid %d, msg0=%jx, msg1=%jx \n", stid,
+ (uintmax_t)msg.msg0, (uintmax_t)msg.msg1);
+#ifdef DUMP_PACKETS
+ {
+ int i = 0;
+ unsigned char *buf = (char *)m->m_data;
+
+ printf("Tx Packet: length=%d\n", len);
+ for (i = 0; i < 64; i++) {
+ if (i && (i % 16) == 0)
+ printf("\n");
+ printf("%02x ", buf[i]);
+ }
+ printf("\n");
+ }
+#endif
+ xlr_inc_counter(NETIF_TX);
+ return MAC_TX_PASS;
+}
+
+static int
+rmi_xlr_mac_xmit(struct mbuf *m, struct rge_softc *sc, int len, struct p2d_tx_desc *tx_desc)
+{
+ struct driver_data *priv = &(sc->priv);
+ int ret = -ENOSPC;
+
+ dbg_msg("IN\n");
+
+ xlr_inc_counter(NETIF_STACK_TX);
+
+retry:
+ ret = mac_xmit(m, sc, priv, len, tx_desc);
+
+ if (ret == MAC_TX_RETRY)
+ goto retry;
+
+ dbg_msg("OUT, ret = %d\n", ret);
+ if (ret == MAC_TX_FAIL) {
+ /* FULL */
+ dbg_msg("Msg Ring Full. Stopping upper layer Q\n");
+ port_inc_counter(priv->instance, PORT_STOPQ);
+ }
+ return ret;
+}
+
+static void
+mac_frin_replenish(void *args /* ignored */ )
+{
+ int cpu = xlr_core_id();
+ int done = 0;
+ int i = 0;
+
+ xlr_inc_counter(REPLENISH_ENTER);
+ /*
+ * xlr_set_counter(REPLENISH_ENTER_COUNT,
+ * atomic_read(frin_to_be_sent));
+ */
+ xlr_set_counter(REPLENISH_CPU, PCPU_GET(cpuid));
+
+ for (;;) {
+
+ done = 0;
+
+ for (i = 0; i < XLR_MAX_MACS; i++) {
+ /* int offset = 0; */
+ void *m;
+ uint32_t cycles;
+ struct rge_softc *sc;
+ struct driver_data *priv;
+ int frin_to_be_sent;
+
+ sc = dev_mac[i];
+ if (!sc)
+ goto skip;
+
+ priv = &(sc->priv);
+ frin_to_be_sent = priv->frin_to_be_sent[cpu];
+
+ /* if (atomic_read(frin_to_be_sent) < 0) */
+ if (frin_to_be_sent < 0) {
+ panic("BUG?: [%s]: gmac_%d illegal value for frin_to_be_sent=%d\n",
+ __FUNCTION__, i,
+ frin_to_be_sent);
+ }
+ /* if (!atomic_read(frin_to_be_sent)) */
+ if (!frin_to_be_sent)
+ goto skip;
+
+ cycles = mips_rd_count();
+ {
+ m = get_buf();
+ if (!m) {
+ device_printf(sc->rge_dev, "No buffer\n");
+ goto skip;
+ }
+ }
+ xlr_inc_counter(REPLENISH_FRIN);
+ if (xlr_mac_send_fr(priv, vtophys(m), MAX_FRAME_SIZE)) {
+ free_buf(vtophys(m));
+ printf("[%s]: rx free message_send failed!\n", __FUNCTION__);
+ break;
+ }
+ xlr_set_counter(REPLENISH_CYCLES,
+ (read_c0_count() - cycles));
+ atomic_subtract_int((&priv->frin_to_be_sent[cpu]), 1);
+
+ continue;
+ skip:
+ done++;
+ }
+ if (done == XLR_MAX_MACS)
+ break;
+ }
+}
+
+static volatile uint32_t g_tx_frm_tx_ok=0;
+
+static void
+rge_tx_bkp_func(void *arg, int npending)
+{
+ int i = 0;
+
+ for (i = 0; i < xlr_board_info.gmacports; i++) {
+ if (!dev_mac[i] || !dev_mac[i]->active)
+ continue;
+ rge_start_locked(dev_mac[i]->rge_ifp, RGE_TX_THRESHOLD);
+ }
+ atomic_subtract_int(&g_tx_frm_tx_ok, 1);
+}
+
+/* This function is called from an interrupt handler */
+void
+rmi_xlr_mac_msgring_handler(int bucket, int size, int code,
+ int stid, struct msgrng_msg *msg,
+ void *data /* ignored */ )
+{
+ uint64_t phys_addr = 0;
+ unsigned long addr = 0;
+ uint32_t length = 0;
+ int ctrl = 0, port = 0;
+ struct rge_softc *sc = NULL;
+ struct driver_data *priv = 0;
+ struct ifnet *ifp;
+ int vcpu = xlr_cpu_id();
+ int cpu = xlr_core_id();
+
+ dbg_msg("mac: bucket=%d, size=%d, code=%d, stid=%d, msg0=%jx msg1=%jx\n",
+ bucket, size, code, stid, (uintmax_t)msg->msg0, (uintmax_t)msg->msg1);
+
+ phys_addr = (uint64_t) (msg->msg0 & 0xffffffffe0ULL);
+ length = (msg->msg0 >> 40) & 0x3fff;
+ if (length == 0) {
+ ctrl = CTRL_REG_FREE;
+ port = (msg->msg0 >> 54) & 0x0f;
+ addr = 0;
+ } else {
+ ctrl = CTRL_SNGL;
+ length = length - BYTE_OFFSET - MAC_CRC_LEN;
+ port = msg->msg0 & 0x0f;
+ addr = 0;
+ }
+
+ if (xlr_board_info.is_xls) {
+ if (stid == MSGRNG_STNID_GMAC1)
+ port += 4;
+ sc = dev_mac[dev_mac_gmac0 + port];
+ } else {
+ if (stid == MSGRNG_STNID_XGS0FR)
+ sc = dev_mac[dev_mac_xgs0];
+ else if (stid == MSGRNG_STNID_XGS1FR)
+ sc = dev_mac[dev_mac_xgs0 + 1];
+ else
+ sc = dev_mac[dev_mac_gmac0 + port];
+ }
+ if (sc == NULL)
+ return;
+ priv = &(sc->priv);
+
+ dbg_msg("msg0 = %jx, stid = %d, port = %d, addr=%lx, length=%d, ctrl=%d\n",
+ (uintmax_t)msg->msg0, stid, port, addr, length, ctrl);
+
+ if (ctrl == CTRL_REG_FREE || ctrl == CTRL_JUMBO_FREE) {
+ xlr_rge_tx_ok_done[vcpu]++;
+ release_tx_desc(msg, 1);
+ ifp = sc->rge_ifp;
+ if (ifp->if_drv_flags & IFF_DRV_OACTIVE) {
+ ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
+ }
+ if (atomic_cmpset_int(&g_tx_frm_tx_ok, 0, 1))
+ rge_tx_bkp_func(NULL, 0);
+ xlr_set_counter(NETIF_TX_COMPLETE_CYCLES,
+ (read_c0_count() - msgrng_msg_cycles));
+ } else if (ctrl == CTRL_SNGL || ctrl == CTRL_START) {
+ /* Rx Packet */
+ /* struct mbuf *m = 0; */
+ /* int logical_cpu = 0; */
+
+ dbg_msg("Received packet, port = %d\n", port);
+ /*
+ * if num frins to be sent exceeds threshold, wake up the
+ * helper thread
+ */
+ atomic_add_int(&(priv->frin_to_be_sent[cpu]), 1);
+ if ((priv->frin_to_be_sent[cpu]) > MAC_FRIN_TO_BE_SENT_THRESHOLD) {
+ mac_frin_replenish(NULL);
+ }
+ dbg_msg("gmac_%d: rx packet: phys_addr = %jx, length = %x\n",
+ priv->instance, (uintmax_t)phys_addr, length);
+ mac_stats_add(priv->stats.rx_packets, 1);
+ mac_stats_add(priv->stats.rx_bytes, length);
+ xlr_inc_counter(NETIF_RX);
+ xlr_set_counter(NETIF_RX_CYCLES,
+ (read_c0_count() - msgrng_msg_cycles));
+ rge_rx(sc, phys_addr, length);
+ xlr_rge_rx_done[vcpu]++;
+ } else {
+ printf("[%s]: unrecognized ctrl=%d!\n", __FUNCTION__, ctrl);
+ }
+
+}
+
+/**********************************************************************
+ **********************************************************************/
+static int
+rge_probe(dev)
+ device_t dev;
+{
+ device_set_desc(dev, "RMI Gigabit Ethernet");
+
+ /* Always return 0 */
+ return 0;
+}
+
+volatile unsigned long xlr_debug_enabled;
+struct callout rge_dbg_count;
+static void
+xlr_debug_count(void *addr)
+{
+ struct driver_data *priv = &dev_mac[0]->priv;
+
+ /* uint32_t crdt; */
+ if (xlr_debug_enabled) {
+ printf("\nAvailRxIn %#x\n", xlr_read_reg(priv->mmio, 0x23e));
+ }
+ callout_reset(&rge_dbg_count, hz, xlr_debug_count, NULL);
+}
+
+
+static void
+xlr_tx_q_wakeup(void *addr)
+{
+ int i = 0;
+ int j = 0;
+
+ for (i = 0; i < xlr_board_info.gmacports; i++) {
+ if (!dev_mac[i] || !dev_mac[i]->active)
+ continue;
+ if ((dev_mac[i]->rge_ifp->if_drv_flags) & IFF_DRV_OACTIVE) {
+ for (j = 0; j < XLR_MAX_CORE; j++) {
+ if (xlr_tot_avail_p2d[j]) {
+ dev_mac[i]->rge_ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
+ break;
+ }
+ }
+ }
+ }
+ if (atomic_cmpset_int(&g_tx_frm_tx_ok, 0, 1))
+ rge_tx_bkp_func(NULL, 0);
+ callout_reset(&xlr_tx_stop_bkp, 5 * hz, xlr_tx_q_wakeup, NULL);
+}
+
+static int
+rge_attach(device_t dev)
+{
+ struct ifnet *ifp;
+ struct rge_softc *sc;
+ struct driver_data *priv = 0;
+ int ret = 0;
+ struct xlr_gmac_block_t *gmac_conf = device_get_ivars(dev);
+
+ sc = device_get_softc(dev);
+ sc->rge_dev = dev;
+
+ /* Initialize mac's */
+ sc->unit = device_get_unit(dev);
+
+ if (sc->unit > XLR_MAX_MACS) {
+ ret = ENXIO;
+ goto out;
+ }
+ RGE_LOCK_INIT(sc, device_get_nameunit(dev));
+
+ priv = &(sc->priv);
+ priv->sc = sc;
+
+ sc->flags = 0; /* TODO : fix me up later */
+
+ priv->id = sc->unit;
+ if (gmac_conf->type == XLR_GMAC) {
+ priv->instance = priv->id;
+ priv->mmio = (xlr_reg_t *) (xlr_io_base + gmac_conf->baseaddr +
+ 0x1000 * (sc->unit % 4));
+ if ((ret = rmi_xlr_gmac_reset(priv)) == -1)
+ goto out;
+ } else if (gmac_conf->type == XLR_XGMAC) {
+ priv->instance = priv->id - xlr_board_info.gmacports;
+ priv->mmio = (xlr_reg_t *) (xlr_io_base + gmac_conf->baseaddr);
+ }
+ if (xlr_boot1_info.board_major_version == RMI_XLR_BOARD_ARIZONA_VI ||
+ (xlr_boot1_info.board_major_version == RMI_XLR_BOARD_ARIZONA_XI &&
+ priv->instance >=4)) {
+ dbg_msg("Arizona board - offset 4 \n");
+ priv->mii_mmio = (xlr_reg_t *) (xlr_io_base + XLR_IO_GMAC_4_OFFSET);
+ } else
+ priv->mii_mmio = (xlr_reg_t *) (xlr_io_base + XLR_IO_GMAC_0_OFFSET);
+
+ priv->pcs_mmio = (xlr_reg_t *) (xlr_io_base + gmac_conf->baseaddr);
+ priv->serdes_mmio = (xlr_reg_t *) (xlr_io_base + XLR_IO_GMAC_0_OFFSET);
+
+ sc->base_addr = (unsigned long)priv->mmio;
+ sc->mem_end = (unsigned long)priv->mmio + XLR_IO_SIZE - 1;
+
+ sc->xmit = rge_start;
+ sc->stop = rge_stop;
+ sc->get_stats = rmi_xlr_mac_get_stats;
+ sc->ioctl = rge_ioctl;
+
+ /* Initialize the device specific driver data */
+ mtx_init(&priv->lock, "rge", NULL, MTX_SPIN);
+
+ priv->type = gmac_conf->type;
+
+ priv->mode = gmac_conf->mode;
+ if (xlr_board_info.is_xls == 0) {
+ /* TODO - check II and IIB boards */
+ if (xlr_boot1_info.board_major_version == RMI_XLR_BOARD_ARIZONA_II &&
+ xlr_boot1_info.board_minor_version != 1)
+ priv->phy_addr = priv->instance - 2;
+ else
+ priv->phy_addr = priv->instance;
+ priv->mode = XLR_RGMII;
+ } else {
+ if (gmac_conf->mode == XLR_PORT0_RGMII &&
+ priv->instance == 0) {
+ priv->mode = XLR_PORT0_RGMII;
+ priv->phy_addr = 0;
+ } else {
+ priv->mode = XLR_SGMII;
+ /* Board 11 has SGMII daughter cards with the XLS chips, in this case
+ the phy number is 0-3 for both GMAC blocks */
+ if (xlr_boot1_info.board_major_version == RMI_XLR_BOARD_ARIZONA_XI)
+ priv->phy_addr = priv->instance % 4 + 16;
+ else
+ priv->phy_addr = priv->instance + 16;
+ }
+ }
+
+ priv->txbucket = gmac_conf->station_txbase + priv->instance % 4;
+ priv->rfrbucket = gmac_conf->station_rfr;
+ priv->spill_configured = 0;
+
+ dbg_msg("priv->mmio=%p\n", priv->mmio);
+
+ /* Set up ifnet structure */
+ ifp = sc->rge_ifp = if_alloc(IFT_ETHER);
+ if (ifp == NULL) {
+ device_printf(sc->rge_dev, "failed to if_alloc()\n");
+ rge_release_resources(sc);
+ ret = ENXIO;
+ RGE_LOCK_DESTROY(sc);
+ goto out;
+ }
+ ifp->if_softc = sc;
+ if_initname(ifp, device_get_name(dev), device_get_unit(dev));
+ ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
+ ifp->if_ioctl = rge_ioctl;
+ ifp->if_start = rge_start;
+ ifp->if_init = rge_init;
+ ifp->if_mtu = ETHERMTU;
+ ifp->if_snd.ifq_drv_maxlen = RGE_TX_Q_SIZE;
+ IFQ_SET_MAXLEN(&ifp->if_snd, ifp->if_snd.ifq_drv_maxlen);
+ IFQ_SET_READY(&ifp->if_snd);
+ sc->active = 1;
+ ifp->if_hwassist = 0;
+ ifp->if_capabilities = IFCAP_TXCSUM | IFCAP_VLAN_HWTAGGING;
+ ifp->if_capenable = ifp->if_capabilities;
+
+ /* Initialize the rge_softc */
+ sc->irq = gmac_conf->baseirq + priv->instance % 4;
+
+ /* Set the IRQ into the rid field */
+ /*
+ * note this is a hack to pass the irq to the iodi interrupt setup
+ * routines
+ */
+ sc->rge_irq.__r_i = (struct resource_i *)(intptr_t)sc->irq;
+
+ ret = bus_setup_intr(dev, &sc->rge_irq, INTR_TYPE_NET | INTR_MPSAFE,
+ NULL, rge_intr, sc, &sc->rge_intrhand);
+
+ if (ret) {
+ rge_detach(dev);
+ device_printf(sc->rge_dev, "couldn't set up irq\n");
+ RGE_LOCK_DESTROY(sc);
+ goto out;
+ }
+ xlr_mac_get_hwaddr(sc);
+ xlr_mac_setup_hwaddr(priv);
+
+ dbg_msg("MMIO %08lx, MII %08lx, PCS %08lx, base %08lx PHY %d IRQ %d\n",
+ (u_long)priv->mmio, (u_long)priv->mii_mmio, (u_long)priv->pcs_mmio,
+ (u_long)sc->base_addr, priv->phy_addr, sc->irq);
+ dbg_msg("HWADDR %02x:%02x tx %d rfr %d\n", (u_int)sc->dev_addr[4],
+ (u_int)sc->dev_addr[5], priv->txbucket, priv->rfrbucket);
+
+ /*
+ * Set up ifmedia support.
+ */
+ /*
+ * Initialize MII/media info.
+ */
+ sc->rge_mii.mii_ifp = ifp;
+ sc->rge_mii.mii_readreg = rge_mii_read;
+ sc->rge_mii.mii_writereg = (mii_writereg_t) rge_mii_write;
+ sc->rge_mii.mii_statchg = rmi_xlr_mac_mii_statchg;
+ ifmedia_init(&sc->rge_mii.mii_media, 0, rmi_xlr_mac_mediachange,
+ rmi_xlr_mac_mediastatus);
+ ifmedia_add(&sc->rge_mii.mii_media, IFM_ETHER | IFM_AUTO, 0, NULL);
+ ifmedia_set(&sc->rge_mii.mii_media, IFM_ETHER | IFM_AUTO);
+ sc->rge_mii.mii_media.ifm_media = sc->rge_mii.mii_media.ifm_cur->ifm_media;
+
+ /*
+ * Call MI attach routine.
+ */
+ ether_ifattach(ifp, sc->dev_addr);
+
+ if (priv->type == XLR_GMAC) {
+ rmi_xlr_gmac_init(priv);
+ } else if (priv->type == XLR_XGMAC) {
+ rmi_xlr_xgmac_init(priv);
+ }
+ dbg_msg("rge_%d: Phoenix Mac at 0x%p (mtu=%d)\n",
+ sc->unit, priv->mmio, sc->mtu);
+ dev_mac[sc->unit] = sc;
+ if (priv->type == XLR_XGMAC && priv->instance == 0)
+ dev_mac_xgs0 = sc->unit;
+ if (priv->type == XLR_GMAC && priv->instance == 0)
+ dev_mac_gmac0 = sc->unit;
+
+ if (!gmac_common_init_done) {
+ mac_common_init();
+ gmac_common_init_done = 1;
+ callout_init(&xlr_tx_stop_bkp, 1);
+ callout_reset(&xlr_tx_stop_bkp, hz, xlr_tx_q_wakeup, NULL);
+ callout_init(&rge_dbg_count, 1);
+ //callout_reset(&rge_dbg_count, hz, xlr_debug_count, NULL);
+ }
+ if ((ret = rmi_xlr_mac_open(sc)) == -1) {
+ RGE_LOCK_DESTROY(sc);
+ goto out;
+ }
+out:
+ if (ret < 0) {
+ device_printf(dev, "error - skipping\n");
+ }
+ return ret;
+}
+
+static void
+rge_reset(struct rge_softc *sc)
+{
+}
+
+static int
+rge_detach(dev)
+ device_t dev;
+{
+#ifdef FREEBSD_MAC_NOT_YET
+ struct rge_softc *sc;
+ struct ifnet *ifp;
+
+ sc = device_get_softc(dev);
+ ifp = sc->rge_ifp;
+
+ RGE_LOCK(sc);
+ rge_stop(sc);
+ rge_reset(sc);
+ RGE_UNLOCK(sc);
+
+ ether_ifdetach(ifp);
+
+ if (sc->rge_tbi) {
+ ifmedia_removeall(&sc->rge_ifmedia);
+ } else {
+ bus_generic_detach(dev);
+ device_delete_child(dev, sc->rge_miibus);
+ }
+
+ rge_release_resources(sc);
+
+#endif /* FREEBSD_MAC_NOT_YET */
+ return (0);
+}
+static int
+rge_suspend(device_t dev)
+{
+ struct rge_softc *sc;
+
+ sc = device_get_softc(dev);
+ RGE_LOCK(sc);
+ rge_stop(sc);
+ RGE_UNLOCK(sc);
+
+ return 0;
+}
+
+static int
+rge_resume(device_t dev)
+{
+ panic("rge_resume(): unimplemented\n");
+ return 0;
+}
+
+static void
+rge_release_resources(struct rge_softc *sc)
+{
+
+ if (sc->rge_ifp != NULL)
+ if_free(sc->rge_ifp);
+
+ if (mtx_initialized(&sc->rge_mtx)) /* XXX */
+ RGE_LOCK_DESTROY(sc);
+}
+uint32_t gmac_rx_fail[32];
+uint32_t gmac_rx_pass[32];
+
+static void
+rge_rx(struct rge_softc *sc, vm_paddr_t paddr, int len)
+{
+ struct mbuf *m;
+ struct ifnet *ifp = sc->rge_ifp;
+ uint64_t mag;
+ uint32_t sr;
+ /*
+ * On 32 bit machines we use XKPHYS to get the values stores with
+ * the mbuf, need to explicitly enable KX. Disable interrupts while
+ * KX is enabled to prevent this setting leaking to other code.
+ */
+ sr = xlr_enable_kx();
+ m = (struct mbuf *)(intptr_t)xlr_paddr_ld(paddr - XLR_CACHELINE_SIZE);
+ mag = xlr_paddr_ld(paddr - XLR_CACHELINE_SIZE + sizeof(uint64_t));
+ xlr_restore_kx(sr);
+ if (mag != 0xf00bad) {
+ /* somebody else packet Error - FIXME in intialization */
+ printf("cpu %d: *ERROR* Not my packet paddr %p\n",
+ xlr_cpu_id(), (void *)paddr);
+ return;
+ }
+ /* align the data */
+ m->m_data += BYTE_OFFSET;
+ m->m_pkthdr.len = m->m_len = len;
+ m->m_pkthdr.rcvif = ifp;
+
+#ifdef DUMP_PACKETS
+ {
+ int i = 0;
+ unsigned char *buf = (char *)m->m_data;
+
+ printf("Rx Packet: length=%d\n", len);
+ for (i = 0; i < 64; i++) {
+ if (i && (i % 16) == 0)
+ printf("\n");
+ printf("%02x ", buf[i]);
+ }
+ printf("\n");
+ }
+#endif
+ ifp->if_ipackets++;
+ (*ifp->if_input) (ifp, m);
+}
+
+static void
+rge_intr(void *arg)
+{
+ struct rge_softc *sc = (struct rge_softc *)arg;
+ struct driver_data *priv = &(sc->priv);
+ xlr_reg_t *mmio = priv->mmio;
+ uint32_t intreg = xlr_read_reg(mmio, R_INTREG);
+
+ if (intreg & (1 << O_INTREG__MDInt)) {
+ uint32_t phy_int_status = 0;
+ int i = 0;
+
+ for (i = 0; i < XLR_MAX_MACS; i++) {
+ struct rge_softc *phy_dev = 0;
+ struct driver_data *phy_priv = 0;
+
+ phy_dev = dev_mac[i];
+ if (phy_dev == NULL)
+ continue;
+
+ phy_priv = &phy_dev->priv;
+
+ if (phy_priv->type == XLR_XGMAC)
+ continue;
+
+ phy_int_status = rge_mii_read_internal(phy_priv->mii_mmio,
+ phy_priv->phy_addr, 26);
+ printf("rge%d: Phy addr %d, MII MMIO %lx status %x\n", phy_priv->instance,
+ (int)phy_priv->phy_addr, (u_long)phy_priv->mii_mmio, phy_int_status);
+ rmi_xlr_gmac_config_speed(phy_priv);
+ }
+ } else {
+ printf("[%s]: mac type = %d, instance %d error "
+ "interrupt: INTREG = 0x%08x\n",
+ __FUNCTION__, priv->type, priv->instance, intreg);
+ }
+
+ /* clear all interrupts and hope to make progress */
+ xlr_write_reg(mmio, R_INTREG, 0xffffffff);
+
+ /* (not yet) on A0 and B0, xgmac interrupts are routed only to xgs_1 irq */
+ if ((xlr_revision() < 2) && (priv->type == XLR_XGMAC)) {
+ struct rge_softc *xgs0_dev = dev_mac[dev_mac_xgs0];
+ struct driver_data *xgs0_priv = &xgs0_dev->priv;
+ xlr_reg_t *xgs0_mmio = xgs0_priv->mmio;
+ uint32_t xgs0_intreg = xlr_read_reg(xgs0_mmio, R_INTREG);
+
+ if (xgs0_intreg) {
+ printf("[%s]: mac type = %d, instance %d error "
+ "interrupt: INTREG = 0x%08x\n",
+ __FUNCTION__, xgs0_priv->type, xgs0_priv->instance, xgs0_intreg);
+
+ xlr_write_reg(xgs0_mmio, R_INTREG, 0xffffffff);
+ }
+ }
+}
+
+static void
+rge_start_locked(struct ifnet *ifp, int threshold)
+{
+ struct rge_softc *sc = ifp->if_softc;
+ struct mbuf *m = NULL;
+ int prepend_pkt = 0;
+ int i = 0;
+ struct p2d_tx_desc *tx_desc = NULL;
+ int cpu = xlr_core_id();
+ uint32_t vcpu = xlr_cpu_id();
+
+ if (!(ifp->if_drv_flags & IFF_DRV_RUNNING))
+ return;
+
+ for (i = 0; i < xlr_tot_avail_p2d[cpu]; i++) {
+ if (IFQ_DRV_IS_EMPTY(&ifp->if_snd))
+ return;
+ tx_desc = get_p2d_desc();
+ if (!tx_desc) {
+ xlr_rge_get_p2d_failed[vcpu]++;
+ return;
+ }
+ /* Grab a packet off the queue. */
+ IFQ_DEQUEUE(&ifp->if_snd, m);
+ if (m == NULL) {
+ free_p2d_desc(tx_desc);
+ return;
+ }
+ prepend_pkt = rmi_xlr_mac_xmit(m, sc, 0, tx_desc);
+
+ if (prepend_pkt) {
+ xlr_rge_tx_prepend[vcpu]++;
+ IF_PREPEND(&ifp->if_snd, m);
+ ifp->if_drv_flags |= IFF_DRV_OACTIVE;
+ return;
+ } else {
+ ifp->if_opackets++;
+ xlr_rge_tx_done[vcpu]++;
+ }
+ }
+}
+
+static void
+rge_start(struct ifnet *ifp)
+{
+ rge_start_locked(ifp, RGE_TX_Q_SIZE);
+}
+
+static int
+rge_ioctl(struct ifnet *ifp, u_long command, caddr_t data)
+{
+ struct rge_softc *sc = ifp->if_softc;
+ struct ifreq *ifr = (struct ifreq *)data;
+ int mask, error = 0;
+
+ /* struct mii_data *mii; */
+ switch (command) {
+ case SIOCSIFMTU:
+ ifp->if_mtu = ifr->ifr_mtu;
+ error = rmi_xlr_mac_change_mtu(sc, ifr->ifr_mtu);
+ break;
+ case SIOCSIFFLAGS:
+
+ RGE_LOCK(sc);
+ if (ifp->if_flags & IFF_UP) {
+ /*
+ * If only the state of the PROMISC flag changed,
+ * then just use the 'set promisc mode' command
+ * instead of reinitializing the entire NIC. Doing a
+ * full re-init means reloading the firmware and
+ * waiting for it to start up, which may take a
+ * second or two. Similarly for ALLMULTI.
+ */
+ if (ifp->if_drv_flags & IFF_DRV_RUNNING &&
+ ifp->if_flags & IFF_PROMISC &&
+ !(sc->flags & IFF_PROMISC)) {
+ sc->flags |= IFF_PROMISC;
+ xlr_mac_set_rx_mode(sc);
+ } else if (ifp->if_drv_flags & IFF_DRV_RUNNING &&
+ !(ifp->if_flags & IFF_PROMISC) &&
+ sc->flags & IFF_PROMISC) {
+ sc->flags &= IFF_PROMISC;
+ xlr_mac_set_rx_mode(sc);
+ } else if (ifp->if_drv_flags & IFF_DRV_RUNNING &&
+ (ifp->if_flags ^ sc->flags) & IFF_ALLMULTI) {
+ rmi_xlr_mac_set_multicast_list(sc);
+ } else
+ xlr_mac_set_rx_mode(sc);
+ } else {
+ if (ifp->if_drv_flags & IFF_DRV_RUNNING) {
+ xlr_mac_set_rx_mode(sc);
+ }
+ }
+ sc->flags = ifp->if_flags;
+ RGE_UNLOCK(sc);
+ error = 0;
+ break;
+ case SIOCADDMULTI:
+ case SIOCDELMULTI:
+ if (ifp->if_drv_flags & IFF_DRV_RUNNING) {
+ RGE_LOCK(sc);
+ rmi_xlr_mac_set_multicast_list(sc);
+ RGE_UNLOCK(sc);
+ error = 0;
+ }
+ break;
+ case SIOCSIFMEDIA:
+ case SIOCGIFMEDIA:
+ error = ifmedia_ioctl(ifp, ifr,
+ &sc->rge_mii.mii_media, command);
+ break;
+ case SIOCSIFCAP:
+ mask = ifr->ifr_reqcap ^ ifp->if_capenable;
+ ifp->if_hwassist = 0;
+ break;
+ default:
+ error = ether_ioctl(ifp, command, data);
+ break;
+ }
+
+ return (error);
+}
+
+static void
+rge_init(void *addr)
+{
+ struct rge_softc *sc = (struct rge_softc *)addr;
+ struct ifnet *ifp;
+ struct driver_data *priv = &(sc->priv);
+
+ ifp = sc->rge_ifp;
+
+ if (ifp->if_drv_flags & IFF_DRV_RUNNING)
+ return;
+ ifp->if_drv_flags |= IFF_DRV_RUNNING;
+ ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
+
+ rmi_xlr_mac_set_enable(priv, 1);
+}
+
+static void
+rge_stop(struct rge_softc *sc)
+{
+ rmi_xlr_mac_close(sc);
+}
+
+static int
+rge_shutdown(device_t dev)
+{
+ struct rge_softc *sc;
+
+ sc = device_get_softc(dev);
+
+ RGE_LOCK(sc);
+ rge_stop(sc);
+ rge_reset(sc);
+ RGE_UNLOCK(sc);
+
+ return (0);
+}
+
+static int
+rmi_xlr_mac_open(struct rge_softc *sc)
+{
+ struct driver_data *priv = &(sc->priv);
+ int i;
+
+ dbg_msg("IN\n");
+
+ if (rmi_xlr_mac_fill_rxfr(sc)) {
+ return -1;
+ }
+ mtx_lock_spin(&priv->lock);
+
+ xlr_mac_set_rx_mode(sc);
+
+ if (sc->unit == xlr_board_info.gmacports - 1) {
+ printf("Enabling MDIO interrupts\n");
+ struct rge_softc *tmp = NULL;
+
+ for (i = 0; i < xlr_board_info.gmacports; i++) {
+ tmp = dev_mac[i];
+ if (tmp)
+ xlr_write_reg(tmp->priv.mmio, R_INTMASK,
+ ((tmp->priv.instance == 0) << O_INTMASK__MDInt));
+ }
+ }
+ /*
+ * Configure the speed, duplex, and flow control
+ */
+ rmi_xlr_mac_set_speed(priv, priv->speed);
+ rmi_xlr_mac_set_duplex(priv, priv->duplex, priv->flow_ctrl);
+ rmi_xlr_mac_set_enable(priv, 0);
+
+ mtx_unlock_spin(&priv->lock);
+
+ for (i = 0; i < 8; i++) {
+ priv->frin_to_be_sent[i] = 0;
+ }
+
+ return 0;
+}
+
+/**********************************************************************
+ **********************************************************************/
+static int
+rmi_xlr_mac_close(struct rge_softc *sc)
+{
+ struct driver_data *priv = &(sc->priv);
+
+ mtx_lock_spin(&priv->lock);
+
+ /*
+ * There may have left over mbufs in the ring as well as in free in
+ * they will be reused next time open is called
+ */
+
+ rmi_xlr_mac_set_enable(priv, 0);
+
+ xlr_inc_counter(NETIF_STOP_Q);
+ port_inc_counter(priv->instance, PORT_STOPQ);
+
+ mtx_unlock_spin(&priv->lock);
+
+ return 0;
+}
+
+/**********************************************************************
+ **********************************************************************/
+static struct rge_softc_stats *
+rmi_xlr_mac_get_stats(struct rge_softc *sc)
+{
+ struct driver_data *priv = &(sc->priv);
+
+ /* unsigned long flags; */
+
+ mtx_lock_spin(&priv->lock);
+
+ /* XXX update other stats here */
+
+ mtx_unlock_spin(&priv->lock);
+
+ return &priv->stats;
+}
+
+/**********************************************************************
+ **********************************************************************/
+static void
+rmi_xlr_mac_set_multicast_list(struct rge_softc *sc)
+{
+}
+
+/**********************************************************************
+ **********************************************************************/
+static int
+rmi_xlr_mac_change_mtu(struct rge_softc *sc, int new_mtu)
+{
+ struct driver_data *priv = &(sc->priv);
+
+ if ((new_mtu > 9500) || (new_mtu < 64)) {
+ return -EINVAL;
+ }
+ mtx_lock_spin(&priv->lock);
+
+ sc->mtu = new_mtu;
+
+ /* Disable MAC TX/RX */
+ rmi_xlr_mac_set_enable(priv, 0);
+
+ /* Flush RX FR IN */
+ /* Flush TX IN */
+ rmi_xlr_mac_set_enable(priv, 1);
+
+ mtx_unlock_spin(&priv->lock);
+ return 0;
+}
+
+/**********************************************************************
+ **********************************************************************/
+static int
+rmi_xlr_mac_fill_rxfr(struct rge_softc *sc)
+{
+ struct driver_data *priv = &(sc->priv);
+ int i;
+ int ret = 0;
+ void *ptr;
+
+ dbg_msg("\n");
+ if (!priv->init_frin_desc)
+ return ret;
+ priv->init_frin_desc = 0;
+
+ dbg_msg("\n");
+ for (i = 0; i < MAX_NUM_DESC; i++) {
+ ptr = get_buf();
+ if (!ptr) {
+ ret = -ENOMEM;
+ break;
+ }
+ /* Send the free Rx desc to the MAC */
+ xlr_mac_send_fr(priv, vtophys(ptr), MAX_FRAME_SIZE);
+ }
+
+ return ret;
+}
+
+/**********************************************************************
+ **********************************************************************/
+static __inline__ void *
+rmi_xlr_config_spill(xlr_reg_t * mmio,
+ int reg_start_0, int reg_start_1,
+ int reg_size, int size)
+{
+ uint32_t spill_size = size;
+ void *spill = NULL;
+ uint64_t phys_addr = 0;
+
+
+ spill = contigmalloc((spill_size + XLR_CACHELINE_SIZE), M_DEVBUF,
+ M_NOWAIT | M_ZERO, 0, 0xffffffff, XLR_CACHELINE_SIZE, 0);
+ if (!spill || ((vm_offset_t)spill & (XLR_CACHELINE_SIZE - 1))) {
+ panic("Unable to allocate memory for spill area!\n");
+ }
+ phys_addr = vtophys(spill);
+ dbg_msg("Allocate spill %d bytes at %jx\n", size, (uintmax_t)phys_addr);
+ xlr_write_reg(mmio, reg_start_0, (phys_addr >> 5) & 0xffffffff);
+ xlr_write_reg(mmio, reg_start_1, (phys_addr >> 37) & 0x07);
+ xlr_write_reg(mmio, reg_size, spill_size);
+
+ return spill;
+}
+
+static void
+rmi_xlr_config_spill_area(struct driver_data *priv)
+{
+ /*
+ * if driver initialization is done parallely on multiple cpus
+ * spill_configured needs synchronization
+ */
+ if (priv->spill_configured)
+ return;
+
+ if (priv->type == XLR_GMAC && priv->instance % 4 != 0) {
+ priv->spill_configured = 1;
+ return;
+ }
+ priv->spill_configured = 1;
+
+ priv->frin_spill =
+ rmi_xlr_config_spill(priv->mmio,
+ R_REG_FRIN_SPILL_MEM_START_0,
+ R_REG_FRIN_SPILL_MEM_START_1,
+ R_REG_FRIN_SPILL_MEM_SIZE,
+ MAX_FRIN_SPILL *
+ sizeof(struct fr_desc));
+
+ priv->class_0_spill =
+ rmi_xlr_config_spill(priv->mmio,
+ R_CLASS0_SPILL_MEM_START_0,
+ R_CLASS0_SPILL_MEM_START_1,
+ R_CLASS0_SPILL_MEM_SIZE,
+ MAX_CLASS_0_SPILL *
+ sizeof(union rx_tx_desc));
+ priv->class_1_spill =
+ rmi_xlr_config_spill(priv->mmio,
+ R_CLASS1_SPILL_MEM_START_0,
+ R_CLASS1_SPILL_MEM_START_1,
+ R_CLASS1_SPILL_MEM_SIZE,
+ MAX_CLASS_1_SPILL *
+ sizeof(union rx_tx_desc));
+
+ priv->frout_spill =
+ rmi_xlr_config_spill(priv->mmio, R_FROUT_SPILL_MEM_START_0,
+ R_FROUT_SPILL_MEM_START_1,
+ R_FROUT_SPILL_MEM_SIZE,
+ MAX_FROUT_SPILL *
+ sizeof(struct fr_desc));
+
+ priv->class_2_spill =
+ rmi_xlr_config_spill(priv->mmio,
+ R_CLASS2_SPILL_MEM_START_0,
+ R_CLASS2_SPILL_MEM_START_1,
+ R_CLASS2_SPILL_MEM_SIZE,
+ MAX_CLASS_2_SPILL *
+ sizeof(union rx_tx_desc));
+ priv->class_3_spill =
+ rmi_xlr_config_spill(priv->mmio,
+ R_CLASS3_SPILL_MEM_START_0,
+ R_CLASS3_SPILL_MEM_START_1,
+ R_CLASS3_SPILL_MEM_SIZE,
+ MAX_CLASS_3_SPILL *
+ sizeof(union rx_tx_desc));
+ priv->spill_configured = 1;
+}
+
+/*****************************************************************
+ * Write the MAC address to the XLR registers
+ * All 4 addresses are the same for now
+ *****************************************************************/
+static void
+xlr_mac_setup_hwaddr(struct driver_data *priv)
+{
+ struct rge_softc *sc = priv->sc;
+
+ xlr_write_reg(priv->mmio, R_MAC_ADDR0,
+ ((sc->dev_addr[5] << 24) | (sc->dev_addr[4] << 16)
+ | (sc->dev_addr[3] << 8) | (sc->dev_addr[2]))
+ );
+
+ xlr_write_reg(priv->mmio, R_MAC_ADDR0 + 1,
+ ((sc->dev_addr[1] << 24) | (sc->
+ dev_addr[0] << 16)));
+
+ xlr_write_reg(priv->mmio, R_MAC_ADDR_MASK2, 0xffffffff);
+
+ xlr_write_reg(priv->mmio, R_MAC_ADDR_MASK2 + 1, 0xffffffff);
+
+ xlr_write_reg(priv->mmio, R_MAC_ADDR_MASK3, 0xffffffff);
+
+ xlr_write_reg(priv->mmio, R_MAC_ADDR_MASK3 + 1, 0xffffffff);
+
+ xlr_write_reg(priv->mmio, R_MAC_FILTER_CONFIG,
+ (1 << O_MAC_FILTER_CONFIG__BROADCAST_EN) |
+ (1 << O_MAC_FILTER_CONFIG__ALL_MCAST_EN) |
+ (1 << O_MAC_FILTER_CONFIG__MAC_ADDR0_VALID)
+ );
+}
+
+/*****************************************************************
+ * Read the MAC address from the XLR registers
+ * All 4 addresses are the same for now
+ *****************************************************************/
+static void
+xlr_mac_get_hwaddr(struct rge_softc *sc)
+{
+ struct driver_data *priv = &(sc->priv);
+
+ sc->dev_addr[0] = (xlr_boot1_info.mac_addr >> 40) & 0xff;
+ sc->dev_addr[1] = (xlr_boot1_info.mac_addr >> 32) & 0xff;
+ sc->dev_addr[2] = (xlr_boot1_info.mac_addr >> 24) & 0xff;
+ sc->dev_addr[3] = (xlr_boot1_info.mac_addr >> 16) & 0xff;
+ sc->dev_addr[4] = (xlr_boot1_info.mac_addr >> 8) & 0xff;
+ sc->dev_addr[5] = ((xlr_boot1_info.mac_addr >> 0) & 0xff) + priv->instance;
+}
+
+/*****************************************************************
+ * Mac Module Initialization
+ *****************************************************************/
+static void
+mac_common_init(void)
+{
+ init_p2d_allocation();
+ init_tx_ring();
+
+ if (xlr_board_info.is_xls) {
+ if (register_msgring_handler(MSGRNG_STNID_GMAC,
+ MSGRNG_STNID_GMAC + 1, rmi_xlr_mac_msgring_handler,
+ NULL)) {
+ panic("Couldn't register msgring handler\n");
+ }
+ if (register_msgring_handler(MSGRNG_STNID_GMAC1,
+ MSGRNG_STNID_GMAC1 + 1, rmi_xlr_mac_msgring_handler,
+ NULL)) {
+ panic("Couldn't register msgring handler\n");
+ }
+ } else {
+ if (register_msgring_handler(MSGRNG_STNID_GMAC,
+ MSGRNG_STNID_GMAC + 1, rmi_xlr_mac_msgring_handler,
+ NULL)) {
+ panic("Couldn't register msgring handler\n");
+ }
+ }
+
+ /*
+ * Not yet if (xlr_board_atx_ii()) { if (register_msgring_handler
+ * (TX_STN_XGS_0, rmi_xlr_mac_msgring_handler, NULL)) {
+ * panic("Couldn't register msgring handler for TX_STN_XGS_0\n"); }
+ * if (register_msgring_handler (TX_STN_XGS_1,
+ * rmi_xlr_mac_msgring_handler, NULL)) { panic("Couldn't register
+ * msgring handler for TX_STN_XGS_1\n"); } }
+ */
+}
Property changes on: trunk/sys/mips/rmi/dev/xlr/rge.c
___________________________________________________________________
Added: svn:eol-style
## -0,0 +1 ##
+native
\ No newline at end of property
Added: svn:keywords
## -0,0 +1 ##
+MidnightBSD=%H
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+text/plain
\ No newline at end of property
Added: trunk/sys/mips/rmi/dev/xlr/rge.h
===================================================================
--- trunk/sys/mips/rmi/dev/xlr/rge.h (rev 0)
+++ trunk/sys/mips/rmi/dev/xlr/rge.h 2018-05-26 21:55:02 UTC (rev 9987)
@@ -0,0 +1,1099 @@
+/* $MidnightBSD$ */
+/*-
+ * Copyright (c) 2003-2009 RMI Corporation
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * 3. Neither the name of RMI Corporation, nor the names of its contributors,
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ * $FreeBSD: stable/10/sys/mips/rmi/dev/xlr/rge.h 212759 2010-09-16 19:25:24Z jchandra $
+ * RMI_BSD */
+#ifndef _RMI_RGE_H_
+#define _RMI_RGE_H_
+
+/* #define MAC_SPLIT_MODE */
+
+#define MAC_SPACING 0x400
+#define XGMAC_SPACING 0x400
+
+/* PE-MCXMAC register and bit field definitions */
+#define R_MAC_CONFIG_1 0x00
+#define O_MAC_CONFIG_1__srst 31
+#define O_MAC_CONFIG_1__simr 30
+#define O_MAC_CONFIG_1__hrrmc 18
+#define W_MAC_CONFIG_1__hrtmc 2
+#define O_MAC_CONFIG_1__hrrfn 16
+#define W_MAC_CONFIG_1__hrtfn 2
+#define O_MAC_CONFIG_1__intlb 8
+#define O_MAC_CONFIG_1__rxfc 5
+#define O_MAC_CONFIG_1__txfc 4
+#define O_MAC_CONFIG_1__srxen 3
+#define O_MAC_CONFIG_1__rxen 2
+#define O_MAC_CONFIG_1__stxen 1
+#define O_MAC_CONFIG_1__txen 0
+#define R_MAC_CONFIG_2 0x01
+#define O_MAC_CONFIG_2__prlen 12
+#define W_MAC_CONFIG_2__prlen 4
+#define O_MAC_CONFIG_2__speed 8
+#define W_MAC_CONFIG_2__speed 2
+#define O_MAC_CONFIG_2__hugen 5
+#define O_MAC_CONFIG_2__flchk 4
+#define O_MAC_CONFIG_2__crce 1
+#define O_MAC_CONFIG_2__fulld 0
+#define R_IPG_IFG 0x02
+#define O_IPG_IFG__ipgr1 24
+#define W_IPG_IFG__ipgr1 7
+#define O_IPG_IFG__ipgr2 16
+#define W_IPG_IFG__ipgr2 7
+#define O_IPG_IFG__mifg 8
+#define W_IPG_IFG__mifg 8
+#define O_IPG_IFG__ipgt 0
+#define W_IPG_IFG__ipgt 7
+#define R_HALF_DUPLEX 0x03
+#define O_HALF_DUPLEX__abebt 24
+#define W_HALF_DUPLEX__abebt 4
+#define O_HALF_DUPLEX__abebe 19
+#define O_HALF_DUPLEX__bpnb 18
+#define O_HALF_DUPLEX__nobo 17
+#define O_HALF_DUPLEX__edxsdfr 16
+#define O_HALF_DUPLEX__retry 12
+#define W_HALF_DUPLEX__retry 4
+#define O_HALF_DUPLEX__lcol 0
+#define W_HALF_DUPLEX__lcol 10
+#define R_MAXIMUM_FRAME_LENGTH 0x04
+#define O_MAXIMUM_FRAME_LENGTH__maxf 0
+#define W_MAXIMUM_FRAME_LENGTH__maxf 16
+#define R_TEST 0x07
+#define O_TEST__mbof 3
+#define O_TEST__rthdf 2
+#define O_TEST__tpause 1
+#define O_TEST__sstct 0
+#define R_MII_MGMT_CONFIG 0x08
+#define O_MII_MGMT_CONFIG__scinc 5
+#define O_MII_MGMT_CONFIG__spre 4
+#define O_MII_MGMT_CONFIG__clks 3
+#define W_MII_MGMT_CONFIG__clks 3
+#define R_MII_MGMT_COMMAND 0x09
+#define O_MII_MGMT_COMMAND__scan 1
+#define O_MII_MGMT_COMMAND__rstat 0
+#define R_MII_MGMT_ADDRESS 0x0A
+#define O_MII_MGMT_ADDRESS__fiad 8
+#define W_MII_MGMT_ADDRESS__fiad 5
+#define O_MII_MGMT_ADDRESS__fgad 5
+#define W_MII_MGMT_ADDRESS__fgad 0
+#define R_MII_MGMT_WRITE_DATA 0x0B
+#define O_MII_MGMT_WRITE_DATA__ctld 0
+#define W_MII_MGMT_WRITE_DATA__ctld 16
+#define R_MII_MGMT_STATUS 0x0C
+#define R_MII_MGMT_INDICATORS 0x0D
+#define O_MII_MGMT_INDICATORS__nvalid 2
+#define O_MII_MGMT_INDICATORS__scan 1
+#define O_MII_MGMT_INDICATORS__busy 0
+#define R_INTERFACE_CONTROL 0x0E
+#define O_INTERFACE_CONTROL__hrstint 31
+#define O_INTERFACE_CONTROL__tbimode 27
+#define O_INTERFACE_CONTROL__ghdmode 26
+#define O_INTERFACE_CONTROL__lhdmode 25
+#define O_INTERFACE_CONTROL__phymod 24
+#define O_INTERFACE_CONTROL__hrrmi 23
+#define O_INTERFACE_CONTROL__rspd 16
+#define O_INTERFACE_CONTROL__hr100 15
+#define O_INTERFACE_CONTROL__frcq 10
+#define O_INTERFACE_CONTROL__nocfr 9
+#define O_INTERFACE_CONTROL__dlfct 8
+#define O_INTERFACE_CONTROL__enjab 0
+#define R_INTERFACE_STATUS 0x0F
+#define O_INTERFACE_STATUS__xsdfr 9
+#define O_INTERFACE_STATUS__ssrr 8
+#define W_INTERFACE_STATUS__ssrr 5
+#define O_INTERFACE_STATUS__miilf 3
+#define O_INTERFACE_STATUS__locar 2
+#define O_INTERFACE_STATUS__sqerr 1
+#define O_INTERFACE_STATUS__jabber 0
+#define R_STATION_ADDRESS_LS 0x10
+#define R_STATION_ADDRESS_MS 0x11
+
+/* A-XGMAC register and bit field definitions */
+#define R_XGMAC_CONFIG_0 0x00
+#define O_XGMAC_CONFIG_0__hstmacrst 31
+#define O_XGMAC_CONFIG_0__hstrstrctl 23
+#define O_XGMAC_CONFIG_0__hstrstrfn 22
+#define O_XGMAC_CONFIG_0__hstrsttctl 18
+#define O_XGMAC_CONFIG_0__hstrsttfn 17
+#define O_XGMAC_CONFIG_0__hstrstmiim 16
+#define O_XGMAC_CONFIG_0__hstloopback 8
+#define R_XGMAC_CONFIG_1 0x01
+#define O_XGMAC_CONFIG_1__hsttctlen 31
+#define O_XGMAC_CONFIG_1__hsttfen 30
+#define O_XGMAC_CONFIG_1__hstrctlen 29
+#define O_XGMAC_CONFIG_1__hstrfen 28
+#define O_XGMAC_CONFIG_1__tfen 26
+#define O_XGMAC_CONFIG_1__rfen 24
+#define O_XGMAC_CONFIG_1__hstrctlshrtp 12
+#define O_XGMAC_CONFIG_1__hstdlyfcstx 10
+#define W_XGMAC_CONFIG_1__hstdlyfcstx 2
+#define O_XGMAC_CONFIG_1__hstdlyfcsrx 8
+#define W_XGMAC_CONFIG_1__hstdlyfcsrx 2
+#define O_XGMAC_CONFIG_1__hstppen 7
+#define O_XGMAC_CONFIG_1__hstbytswp 6
+#define O_XGMAC_CONFIG_1__hstdrplt64 5
+#define O_XGMAC_CONFIG_1__hstprmscrx 4
+#define O_XGMAC_CONFIG_1__hstlenchk 3
+#define O_XGMAC_CONFIG_1__hstgenfcs 2
+#define O_XGMAC_CONFIG_1__hstpadmode 0
+#define W_XGMAC_CONFIG_1__hstpadmode 2
+#define R_XGMAC_CONFIG_2 0x02
+#define O_XGMAC_CONFIG_2__hsttctlfrcp 31
+#define O_XGMAC_CONFIG_2__hstmlnkflth 27
+#define O_XGMAC_CONFIG_2__hstalnkflth 26
+#define O_XGMAC_CONFIG_2__rflnkflt 24
+#define W_XGMAC_CONFIG_2__rflnkflt 2
+#define O_XGMAC_CONFIG_2__hstipgextmod 16
+#define W_XGMAC_CONFIG_2__hstipgextmod 5
+#define O_XGMAC_CONFIG_2__hstrctlfrcp 15
+#define O_XGMAC_CONFIG_2__hstipgexten 5
+#define O_XGMAC_CONFIG_2__hstmipgext 0
+#define W_XGMAC_CONFIG_2__hstmipgext 5
+#define R_XGMAC_CONFIG_3 0x03
+#define O_XGMAC_CONFIG_3__hstfltrfrm 31
+#define W_XGMAC_CONFIG_3__hstfltrfrm 16
+#define O_XGMAC_CONFIG_3__hstfltrfrmdc 15
+#define W_XGMAC_CONFIG_3__hstfltrfrmdc 16
+#define R_XGMAC_STATION_ADDRESS_LS 0x04
+#define O_XGMAC_STATION_ADDRESS_LS__hstmacadr0 0
+#define W_XGMAC_STATION_ADDRESS_LS__hstmacadr0 32
+#define R_XGMAC_STATION_ADDRESS_MS 0x05
+#define R_XGMAC_MAX_FRAME_LEN 0x08
+#define O_XGMAC_MAX_FRAME_LEN__hstmxfrmwctx 16
+#define W_XGMAC_MAX_FRAME_LEN__hstmxfrmwctx 14
+#define O_XGMAC_MAX_FRAME_LEN__hstmxfrmbcrx 0
+#define W_XGMAC_MAX_FRAME_LEN__hstmxfrmbcrx 16
+#define R_XGMAC_REV_LEVEL 0x0B
+#define O_XGMAC_REV_LEVEL__revlvl 0
+#define W_XGMAC_REV_LEVEL__revlvl 15
+#define R_XGMAC_MIIM_COMMAND 0x10
+#define O_XGMAC_MIIM_COMMAND__hstldcmd 3
+#define O_XGMAC_MIIM_COMMAND__hstmiimcmd 0
+#define W_XGMAC_MIIM_COMMAND__hstmiimcmd 3
+#define R_XGMAC_MIIM_FILED 0x11
+#define O_XGMAC_MIIM_FILED__hststfield 30
+#define W_XGMAC_MIIM_FILED__hststfield 2
+#define O_XGMAC_MIIM_FILED__hstopfield 28
+#define W_XGMAC_MIIM_FILED__hstopfield 2
+#define O_XGMAC_MIIM_FILED__hstphyadx 23
+#define W_XGMAC_MIIM_FILED__hstphyadx 5
+#define O_XGMAC_MIIM_FILED__hstregadx 18
+#define W_XGMAC_MIIM_FILED__hstregadx 5
+#define O_XGMAC_MIIM_FILED__hsttafield 16
+#define W_XGMAC_MIIM_FILED__hsttafield 2
+#define O_XGMAC_MIIM_FILED__miimrddat 0
+#define W_XGMAC_MIIM_FILED__miimrddat 16
+#define R_XGMAC_MIIM_CONFIG 0x12
+#define O_XGMAC_MIIM_CONFIG__hstnopram 7
+#define O_XGMAC_MIIM_CONFIG__hstclkdiv 0
+#define W_XGMAC_MIIM_CONFIG__hstclkdiv 7
+#define R_XGMAC_MIIM_LINK_FAIL_VECTOR 0x13
+#define O_XGMAC_MIIM_LINK_FAIL_VECTOR__miimlfvec 0
+#define W_XGMAC_MIIM_LINK_FAIL_VECTOR__miimlfvec 32
+#define R_XGMAC_MIIM_INDICATOR 0x14
+#define O_XGMAC_MIIM_INDICATOR__miimphylf 4
+#define O_XGMAC_MIIM_INDICATOR__miimmoncplt 3
+#define O_XGMAC_MIIM_INDICATOR__miimmonvld 2
+#define O_XGMAC_MIIM_INDICATOR__miimmon 1
+#define O_XGMAC_MIIM_INDICATOR__miimbusy 0
+
+/* Glue logic register and bit field definitions */
+#define R_MAC_ADDR0 0x50
+#define R_MAC_ADDR1 0x52
+#define R_MAC_ADDR2 0x54
+#define R_MAC_ADDR3 0x56
+#define R_MAC_ADDR_MASK2 0x58
+#define R_MAC_ADDR_MASK3 0x5A
+#define R_MAC_FILTER_CONFIG 0x5C
+#define O_MAC_FILTER_CONFIG__BROADCAST_EN 10
+#define O_MAC_FILTER_CONFIG__PAUSE_FRAME_EN 9
+#define O_MAC_FILTER_CONFIG__ALL_MCAST_EN 8
+#define O_MAC_FILTER_CONFIG__ALL_UCAST_EN 7
+#define O_MAC_FILTER_CONFIG__HASH_MCAST_EN 6
+#define O_MAC_FILTER_CONFIG__HASH_UCAST_EN 5
+#define O_MAC_FILTER_CONFIG__ADDR_MATCH_DISC 4
+#define O_MAC_FILTER_CONFIG__MAC_ADDR3_VALID 3
+#define O_MAC_FILTER_CONFIG__MAC_ADDR2_VALID 2
+#define O_MAC_FILTER_CONFIG__MAC_ADDR1_VALID 1
+#define O_MAC_FILTER_CONFIG__MAC_ADDR0_VALID 0
+#define R_HASH_TABLE_VECTOR 0x30
+#define R_TX_CONTROL 0x0A0
+#define O_TX_CONTROL__Tx15Halt 31
+#define O_TX_CONTROL__Tx14Halt 30
+#define O_TX_CONTROL__Tx13Halt 29
+#define O_TX_CONTROL__Tx12Halt 28
+#define O_TX_CONTROL__Tx11Halt 27
+#define O_TX_CONTROL__Tx10Halt 26
+#define O_TX_CONTROL__Tx9Halt 25
+#define O_TX_CONTROL__Tx8Halt 24
+#define O_TX_CONTROL__Tx7Halt 23
+#define O_TX_CONTROL__Tx6Halt 22
+#define O_TX_CONTROL__Tx5Halt 21
+#define O_TX_CONTROL__Tx4Halt 20
+#define O_TX_CONTROL__Tx3Halt 19
+#define O_TX_CONTROL__Tx2Halt 18
+#define O_TX_CONTROL__Tx1Halt 17
+#define O_TX_CONTROL__Tx0Halt 16
+#define O_TX_CONTROL__TxIdle 15
+#define O_TX_CONTROL__TxEnable 14
+#define O_TX_CONTROL__TxThreshold 0
+#define W_TX_CONTROL__TxThreshold 14
+#define R_RX_CONTROL 0x0A1
+#define O_RX_CONTROL__RGMII 10
+#define O_RX_CONTROL__RxHalt 1
+#define O_RX_CONTROL__RxEnable 0
+#define R_DESC_PACK_CTRL 0x0A2
+#define O_DESC_PACK_CTRL__ByteOffset 17
+#define W_DESC_PACK_CTRL__ByteOffset 3
+#define O_DESC_PACK_CTRL__PrePadEnable 16
+#define O_DESC_PACK_CTRL__MaxEntry 14
+#define W_DESC_PACK_CTRL__MaxEntry 2
+#define O_DESC_PACK_CTRL__RegularSize 0
+#define W_DESC_PACK_CTRL__RegularSize 14
+#define R_STATCTRL 0x0A3
+#define O_STATCTRL__OverFlowEn 4
+#define O_STATCTRL__GIG 3
+#define O_STATCTRL__Sten 2
+#define O_STATCTRL__ClrCnt 1
+#define O_STATCTRL__AutoZ 0
+#define R_L2ALLOCCTRL 0x0A4
+#define O_L2ALLOCCTRL__TxL2Allocate 9
+#define W_L2ALLOCCTRL__TxL2Allocate 9
+#define O_L2ALLOCCTRL__RxL2Allocate 0
+#define W_L2ALLOCCTRL__RxL2Allocate 9
+#define R_INTMASK 0x0A5
+#define O_INTMASK__Spi4TxError 28
+#define O_INTMASK__Spi4RxError 27
+#define O_INTMASK__RGMIIHalfDupCollision 27
+#define O_INTMASK__Abort 26
+#define O_INTMASK__Underrun 25
+#define O_INTMASK__DiscardPacket 24
+#define O_INTMASK__AsyncFifoFull 23
+#define O_INTMASK__TagFull 22
+#define O_INTMASK__Class3Full 21
+#define O_INTMASK__C3EarlyFull 20
+#define O_INTMASK__Class2Full 19
+#define O_INTMASK__C2EarlyFull 18
+#define O_INTMASK__Class1Full 17
+#define O_INTMASK__C1EarlyFull 16
+#define O_INTMASK__Class0Full 15
+#define O_INTMASK__C0EarlyFull 14
+#define O_INTMASK__RxDataFull 13
+#define O_INTMASK__RxEarlyFull 12
+#define O_INTMASK__RFreeEmpty 9
+#define O_INTMASK__RFEarlyEmpty 8
+#define O_INTMASK__P2PSpillEcc 7
+#define O_INTMASK__FreeDescFull 5
+#define O_INTMASK__FreeEarlyFull 4
+#define O_INTMASK__TxFetchError 3
+#define O_INTMASK__StatCarry 2
+#define O_INTMASK__MDInt 1
+#define O_INTMASK__TxIllegal 0
+#define R_INTREG 0x0A6
+#define O_INTREG__Spi4TxError 28
+#define O_INTREG__Spi4RxError 27
+#define O_INTREG__RGMIIHalfDupCollision 27
+#define O_INTREG__Abort 26
+#define O_INTREG__Underrun 25
+#define O_INTREG__DiscardPacket 24
+#define O_INTREG__AsyncFifoFull 23
+#define O_INTREG__TagFull 22
+#define O_INTREG__Class3Full 21
+#define O_INTREG__C3EarlyFull 20
+#define O_INTREG__Class2Full 19
+#define O_INTREG__C2EarlyFull 18
+#define O_INTREG__Class1Full 17
+#define O_INTREG__C1EarlyFull 16
+#define O_INTREG__Class0Full 15
+#define O_INTREG__C0EarlyFull 14
+#define O_INTREG__RxDataFull 13
+#define O_INTREG__RxEarlyFull 12
+#define O_INTREG__RFreeEmpty 9
+#define O_INTREG__RFEarlyEmpty 8
+#define O_INTREG__P2PSpillEcc 7
+#define O_INTREG__FreeDescFull 5
+#define O_INTREG__FreeEarlyFull 4
+#define O_INTREG__TxFetchError 3
+#define O_INTREG__StatCarry 2
+#define O_INTREG__MDInt 1
+#define O_INTREG__TxIllegal 0
+#define R_TXRETRY 0x0A7
+#define O_TXRETRY__CollisionRetry 6
+#define O_TXRETRY__BusErrorRetry 5
+#define O_TXRETRY__UnderRunRetry 4
+#define O_TXRETRY__Retries 0
+#define W_TXRETRY__Retries 4
+#define R_CORECONTROL 0x0A8
+#define O_CORECONTROL__ErrorThread 4
+#define W_CORECONTROL__ErrorThread 7
+#define O_CORECONTROL__Shutdown 2
+#define O_CORECONTROL__Speed 0
+#define W_CORECONTROL__Speed 2
+#define R_BYTEOFFSET0 0x0A9
+#define R_BYTEOFFSET1 0x0AA
+#define R_L2TYPE_0 0x0F0
+#define O_L2TYPE__ExtraHdrProtoSize 26
+#define W_L2TYPE__ExtraHdrProtoSize 5
+#define O_L2TYPE__ExtraHdrProtoOffset 20
+#define W_L2TYPE__ExtraHdrProtoOffset 6
+#define O_L2TYPE__ExtraHeaderSize 14
+#define W_L2TYPE__ExtraHeaderSize 6
+#define O_L2TYPE__ProtoOffset 8
+#define W_L2TYPE__ProtoOffset 6
+#define O_L2TYPE__L2HdrOffset 2
+#define W_L2TYPE__L2HdrOffset 6
+#define O_L2TYPE__L2Proto 0
+#define W_L2TYPE__L2Proto 2
+#define R_L2TYPE_1 0xF0
+#define R_L2TYPE_2 0xF0
+#define R_L2TYPE_3 0xF0
+#define R_PARSERCONFIGREG 0x100
+#define O_PARSERCONFIGREG__CRCHashPoly 8
+#define W_PARSERCONFIGREG__CRCHashPoly 7
+#define O_PARSERCONFIGREG__PrePadOffset 4
+#define W_PARSERCONFIGREG__PrePadOffset 4
+#define O_PARSERCONFIGREG__UseCAM 2
+#define O_PARSERCONFIGREG__UseHASH 1
+#define O_PARSERCONFIGREG__UseProto 0
+#define R_L3CTABLE 0x140
+#define O_L3CTABLE__Offset0 25
+#define W_L3CTABLE__Offset0 7
+#define O_L3CTABLE__Len0 21
+#define W_L3CTABLE__Len0 4
+#define O_L3CTABLE__Offset1 14
+#define W_L3CTABLE__Offset1 7
+#define O_L3CTABLE__Len1 10
+#define W_L3CTABLE__Len1 4
+#define O_L3CTABLE__Offset2 4
+#define W_L3CTABLE__Offset2 6
+#define O_L3CTABLE__Len2 0
+#define W_L3CTABLE__Len2 4
+#define O_L3CTABLE__L3HdrOffset 26
+#define W_L3CTABLE__L3HdrOffset 6
+#define O_L3CTABLE__L4ProtoOffset 20
+#define W_L3CTABLE__L4ProtoOffset 6
+#define O_L3CTABLE__IPChksumCompute 19
+#define O_L3CTABLE__L4Classify 18
+#define O_L3CTABLE__L2Proto 16
+#define W_L3CTABLE__L2Proto 2
+#define O_L3CTABLE__L3ProtoKey 0
+#define W_L3CTABLE__L3ProtoKey 16
+#define R_L4CTABLE 0x160
+#define O_L4CTABLE__Offset0 21
+#define W_L4CTABLE__Offset0 6
+#define O_L4CTABLE__Len0 17
+#define W_L4CTABLE__Len0 4
+#define O_L4CTABLE__Offset1 11
+#define W_L4CTABLE__Offset1 6
+#define O_L4CTABLE__Len1 7
+#define W_L4CTABLE__Len1 4
+#define O_L4CTABLE__TCPChksumEnable 0
+#define R_CAM4X128TABLE 0x172
+#define O_CAM4X128TABLE__ClassId 7
+#define W_CAM4X128TABLE__ClassId 2
+#define O_CAM4X128TABLE__BucketId 1
+#define W_CAM4X128TABLE__BucketId 6
+#define O_CAM4X128TABLE__UseBucket 0
+#define R_CAM4X128KEY 0x180
+#define R_TRANSLATETABLE 0x1A0
+#define R_DMACR0 0x200
+#define O_DMACR0__Data0WrMaxCr 27
+#define W_DMACR0__Data0WrMaxCr 3
+#define O_DMACR0__Data0RdMaxCr 24
+#define W_DMACR0__Data0RdMaxCr 3
+#define O_DMACR0__Data1WrMaxCr 21
+#define W_DMACR0__Data1WrMaxCr 3
+#define O_DMACR0__Data1RdMaxCr 18
+#define W_DMACR0__Data1RdMaxCr 3
+#define O_DMACR0__Data2WrMaxCr 15
+#define W_DMACR0__Data2WrMaxCr 3
+#define O_DMACR0__Data2RdMaxCr 12
+#define W_DMACR0__Data2RdMaxCr 3
+#define O_DMACR0__Data3WrMaxCr 9
+#define W_DMACR0__Data3WrMaxCr 3
+#define O_DMACR0__Data3RdMaxCr 6
+#define W_DMACR0__Data3RdMaxCr 3
+#define O_DMACR0__Data4WrMaxCr 3
+#define W_DMACR0__Data4WrMaxCr 3
+#define O_DMACR0__Data4RdMaxCr 0
+#define W_DMACR0__Data4RdMaxCr 3
+#define R_DMACR1 0x201
+#define O_DMACR1__Data5WrMaxCr 27
+#define W_DMACR1__Data5WrMaxCr 3
+#define O_DMACR1__Data5RdMaxCr 24
+#define W_DMACR1__Data5RdMaxCr 3
+#define O_DMACR1__Data6WrMaxCr 21
+#define W_DMACR1__Data6WrMaxCr 3
+#define O_DMACR1__Data6RdMaxCr 18
+#define W_DMACR1__Data6RdMaxCr 3
+#define O_DMACR1__Data7WrMaxCr 15
+#define W_DMACR1__Data7WrMaxCr 3
+#define O_DMACR1__Data7RdMaxCr 12
+#define W_DMACR1__Data7RdMaxCr 3
+#define O_DMACR1__Data8WrMaxCr 9
+#define W_DMACR1__Data8WrMaxCr 3
+#define O_DMACR1__Data8RdMaxCr 6
+#define W_DMACR1__Data8RdMaxCr 3
+#define O_DMACR1__Data9WrMaxCr 3
+#define W_DMACR1__Data9WrMaxCr 3
+#define O_DMACR1__Data9RdMaxCr 0
+#define W_DMACR1__Data9RdMaxCr 3
+#define R_DMACR2 0x202
+#define O_DMACR2__Data10WrMaxCr 27
+#define W_DMACR2__Data10WrMaxCr 3
+#define O_DMACR2__Data10RdMaxCr 24
+#define W_DMACR2__Data10RdMaxCr 3
+#define O_DMACR2__Data11WrMaxCr 21
+#define W_DMACR2__Data11WrMaxCr 3
+#define O_DMACR2__Data11RdMaxCr 18
+#define W_DMACR2__Data11RdMaxCr 3
+#define O_DMACR2__Data12WrMaxCr 15
+#define W_DMACR2__Data12WrMaxCr 3
+#define O_DMACR2__Data12RdMaxCr 12
+#define W_DMACR2__Data12RdMaxCr 3
+#define O_DMACR2__Data13WrMaxCr 9
+#define W_DMACR2__Data13WrMaxCr 3
+#define O_DMACR2__Data13RdMaxCr 6
+#define W_DMACR2__Data13RdMaxCr 3
+#define O_DMACR2__Data14WrMaxCr 3
+#define W_DMACR2__Data14WrMaxCr 3
+#define O_DMACR2__Data14RdMaxCr 0
+#define W_DMACR2__Data14RdMaxCr 3
+#define R_DMACR3 0x203
+#define O_DMACR3__Data15WrMaxCr 27
+#define W_DMACR3__Data15WrMaxCr 3
+#define O_DMACR3__Data15RdMaxCr 24
+#define W_DMACR3__Data15RdMaxCr 3
+#define O_DMACR3__SpClassWrMaxCr 21
+#define W_DMACR3__SpClassWrMaxCr 3
+#define O_DMACR3__SpClassRdMaxCr 18
+#define W_DMACR3__SpClassRdMaxCr 3
+#define O_DMACR3__JumFrInWrMaxCr 15
+#define W_DMACR3__JumFrInWrMaxCr 3
+#define O_DMACR3__JumFrInRdMaxCr 12
+#define W_DMACR3__JumFrInRdMaxCr 3
+#define O_DMACR3__RegFrInWrMaxCr 9
+#define W_DMACR3__RegFrInWrMaxCr 3
+#define O_DMACR3__RegFrInRdMaxCr 6
+#define W_DMACR3__RegFrInRdMaxCr 3
+#define O_DMACR3__FrOutWrMaxCr 3
+#define W_DMACR3__FrOutWrMaxCr 3
+#define O_DMACR3__FrOutRdMaxCr 0
+#define W_DMACR3__FrOutRdMaxCr 3
+#define R_REG_FRIN_SPILL_MEM_START_0 0x204
+#define O_REG_FRIN_SPILL_MEM_START_0__RegFrInSpillMemStart0 0
+#define W_REG_FRIN_SPILL_MEM_START_0__RegFrInSpillMemStart0 32
+#define R_REG_FRIN_SPILL_MEM_START_1 0x205
+#define O_REG_FRIN_SPILL_MEM_START_1__RegFrInSpillMemStart1 0
+#define W_REG_FRIN_SPILL_MEM_START_1__RegFrInSpillMemStart1 3
+#define R_REG_FRIN_SPILL_MEM_SIZE 0x206
+#define O_REG_FRIN_SPILL_MEM_SIZE__RegFrInSpillMemSize 0
+#define W_REG_FRIN_SPILL_MEM_SIZE__RegFrInSpillMemSize 32
+#define R_FROUT_SPILL_MEM_START_0 0x207
+#define O_FROUT_SPILL_MEM_START_0__FrOutSpillMemStart0 0
+#define W_FROUT_SPILL_MEM_START_0__FrOutSpillMemStart0 32
+#define R_FROUT_SPILL_MEM_START_1 0x208
+#define O_FROUT_SPILL_MEM_START_1__FrOutSpillMemStart1 0
+#define W_FROUT_SPILL_MEM_START_1__FrOutSpillMemStart1 3
+#define R_FROUT_SPILL_MEM_SIZE 0x209
+#define O_FROUT_SPILL_MEM_SIZE__FrOutSpillMemSize 0
+#define W_FROUT_SPILL_MEM_SIZE__FrOutSpillMemSize 32
+#define R_CLASS0_SPILL_MEM_START_0 0x20A
+#define O_CLASS0_SPILL_MEM_START_0__Class0SpillMemStart0 0
+#define W_CLASS0_SPILL_MEM_START_0__Class0SpillMemStart0 32
+#define R_CLASS0_SPILL_MEM_START_1 0x20B
+#define O_CLASS0_SPILL_MEM_START_1__Class0SpillMemStart1 0
+#define W_CLASS0_SPILL_MEM_START_1__Class0SpillMemStart1 3
+#define R_CLASS0_SPILL_MEM_SIZE 0x20C
+#define O_CLASS0_SPILL_MEM_SIZE__Class0SpillMemSize 0
+#define W_CLASS0_SPILL_MEM_SIZE__Class0SpillMemSize 32
+#define R_JUMFRIN_SPILL_MEM_START_0 0x20D
+#define O_JUMFRIN_SPILL_MEM_START_0__JumFrInSpillMemStar0 0
+#define W_JUMFRIN_SPILL_MEM_START_0__JumFrInSpillMemStar0 32
+#define R_JUMFRIN_SPILL_MEM_START_1 0x20E
+#define O_JUMFRIN_SPILL_MEM_START_1__JumFrInSpillMemStart1 0
+#define W_JUMFRIN_SPILL_MEM_START_1__JumFrInSpillMemStart1 3
+#define R_JUMFRIN_SPILL_MEM_SIZE 0x20F
+#define O_JUMFRIN_SPILL_MEM_SIZE__JumFrInSpillMemSize 0
+#define W_JUMFRIN_SPILL_MEM_SIZE__JumFrInSpillMemSize 32
+#define R_CLASS1_SPILL_MEM_START_0 0x210
+#define O_CLASS1_SPILL_MEM_START_0__Class1SpillMemStart0 0
+#define W_CLASS1_SPILL_MEM_START_0__Class1SpillMemStart0 32
+#define R_CLASS1_SPILL_MEM_START_1 0x211
+#define O_CLASS1_SPILL_MEM_START_1__Class1SpillMemStart1 0
+#define W_CLASS1_SPILL_MEM_START_1__Class1SpillMemStart1 3
+#define R_CLASS1_SPILL_MEM_SIZE 0x212
+#define O_CLASS1_SPILL_MEM_SIZE__Class1SpillMemSize 0
+#define W_CLASS1_SPILL_MEM_SIZE__Class1SpillMemSize 32
+#define R_CLASS2_SPILL_MEM_START_0 0x213
+#define O_CLASS2_SPILL_MEM_START_0__Class2SpillMemStart0 0
+#define W_CLASS2_SPILL_MEM_START_0__Class2SpillMemStart0 32
+#define R_CLASS2_SPILL_MEM_START_1 0x214
+#define O_CLASS2_SPILL_MEM_START_1__Class2SpillMemStart1 0
+#define W_CLASS2_SPILL_MEM_START_1__Class2SpillMemStart1 3
+#define R_CLASS2_SPILL_MEM_SIZE 0x215
+#define O_CLASS2_SPILL_MEM_SIZE__Class2SpillMemSize 0
+#define W_CLASS2_SPILL_MEM_SIZE__Class2SpillMemSize 32
+#define R_CLASS3_SPILL_MEM_START_0 0x216
+#define O_CLASS3_SPILL_MEM_START_0__Class3SpillMemStart0 0
+#define W_CLASS3_SPILL_MEM_START_0__Class3SpillMemStart0 32
+#define R_CLASS3_SPILL_MEM_START_1 0x217
+#define O_CLASS3_SPILL_MEM_START_1__Class3SpillMemStart1 0
+#define W_CLASS3_SPILL_MEM_START_1__Class3SpillMemStart1 3
+#define R_CLASS3_SPILL_MEM_SIZE 0x218
+#define O_CLASS3_SPILL_MEM_SIZE__Class3SpillMemSize 0
+#define W_CLASS3_SPILL_MEM_SIZE__Class3SpillMemSize 32
+#define R_REG_FRIN1_SPILL_MEM_START_0 0x219
+#define R_REG_FRIN1_SPILL_MEM_START_1 0x21a
+#define R_REG_FRIN1_SPILL_MEM_SIZE 0x21b
+#define R_SPIHNGY0 0x219
+#define O_SPIHNGY0__EG_HNGY_THRESH_0 24
+#define W_SPIHNGY0__EG_HNGY_THRESH_0 7
+#define O_SPIHNGY0__EG_HNGY_THRESH_1 16
+#define W_SPIHNGY0__EG_HNGY_THRESH_1 7
+#define O_SPIHNGY0__EG_HNGY_THRESH_2 8
+#define W_SPIHNGY0__EG_HNGY_THRESH_2 7
+#define O_SPIHNGY0__EG_HNGY_THRESH_3 0
+#define W_SPIHNGY0__EG_HNGY_THRESH_3 7
+#define R_SPIHNGY1 0x21A
+#define O_SPIHNGY1__EG_HNGY_THRESH_4 24
+#define W_SPIHNGY1__EG_HNGY_THRESH_4 7
+#define O_SPIHNGY1__EG_HNGY_THRESH_5 16
+#define W_SPIHNGY1__EG_HNGY_THRESH_5 7
+#define O_SPIHNGY1__EG_HNGY_THRESH_6 8
+#define W_SPIHNGY1__EG_HNGY_THRESH_6 7
+#define O_SPIHNGY1__EG_HNGY_THRESH_7 0
+#define W_SPIHNGY1__EG_HNGY_THRESH_7 7
+#define R_SPIHNGY2 0x21B
+#define O_SPIHNGY2__EG_HNGY_THRESH_8 24
+#define W_SPIHNGY2__EG_HNGY_THRESH_8 7
+#define O_SPIHNGY2__EG_HNGY_THRESH_9 16
+#define W_SPIHNGY2__EG_HNGY_THRESH_9 7
+#define O_SPIHNGY2__EG_HNGY_THRESH_10 8
+#define W_SPIHNGY2__EG_HNGY_THRESH_10 7
+#define O_SPIHNGY2__EG_HNGY_THRESH_11 0
+#define W_SPIHNGY2__EG_HNGY_THRESH_11 7
+#define R_SPIHNGY3 0x21C
+#define O_SPIHNGY3__EG_HNGY_THRESH_12 24
+#define W_SPIHNGY3__EG_HNGY_THRESH_12 7
+#define O_SPIHNGY3__EG_HNGY_THRESH_13 16
+#define W_SPIHNGY3__EG_HNGY_THRESH_13 7
+#define O_SPIHNGY3__EG_HNGY_THRESH_14 8
+#define W_SPIHNGY3__EG_HNGY_THRESH_14 7
+#define O_SPIHNGY3__EG_HNGY_THRESH_15 0
+#define W_SPIHNGY3__EG_HNGY_THRESH_15 7
+#define R_SPISTRV0 0x21D
+#define O_SPISTRV0__EG_STRV_THRESH_0 24
+#define W_SPISTRV0__EG_STRV_THRESH_0 7
+#define O_SPISTRV0__EG_STRV_THRESH_1 16
+#define W_SPISTRV0__EG_STRV_THRESH_1 7
+#define O_SPISTRV0__EG_STRV_THRESH_2 8
+#define W_SPISTRV0__EG_STRV_THRESH_2 7
+#define O_SPISTRV0__EG_STRV_THRESH_3 0
+#define W_SPISTRV0__EG_STRV_THRESH_3 7
+#define R_SPISTRV1 0x21E
+#define O_SPISTRV1__EG_STRV_THRESH_4 24
+#define W_SPISTRV1__EG_STRV_THRESH_4 7
+#define O_SPISTRV1__EG_STRV_THRESH_5 16
+#define W_SPISTRV1__EG_STRV_THRESH_5 7
+#define O_SPISTRV1__EG_STRV_THRESH_6 8
+#define W_SPISTRV1__EG_STRV_THRESH_6 7
+#define O_SPISTRV1__EG_STRV_THRESH_7 0
+#define W_SPISTRV1__EG_STRV_THRESH_7 7
+#define R_SPISTRV2 0x21F
+#define O_SPISTRV2__EG_STRV_THRESH_8 24
+#define W_SPISTRV2__EG_STRV_THRESH_8 7
+#define O_SPISTRV2__EG_STRV_THRESH_9 16
+#define W_SPISTRV2__EG_STRV_THRESH_9 7
+#define O_SPISTRV2__EG_STRV_THRESH_10 8
+#define W_SPISTRV2__EG_STRV_THRESH_10 7
+#define O_SPISTRV2__EG_STRV_THRESH_11 0
+#define W_SPISTRV2__EG_STRV_THRESH_11 7
+#define R_SPISTRV3 0x220
+#define O_SPISTRV3__EG_STRV_THRESH_12 24
+#define W_SPISTRV3__EG_STRV_THRESH_12 7
+#define O_SPISTRV3__EG_STRV_THRESH_13 16
+#define W_SPISTRV3__EG_STRV_THRESH_13 7
+#define O_SPISTRV3__EG_STRV_THRESH_14 8
+#define W_SPISTRV3__EG_STRV_THRESH_14 7
+#define O_SPISTRV3__EG_STRV_THRESH_15 0
+#define W_SPISTRV3__EG_STRV_THRESH_15 7
+#define R_TXDATAFIFO0 0x221
+#define O_TXDATAFIFO0__Tx0DataFifoStart 24
+#define W_TXDATAFIFO0__Tx0DataFifoStart 7
+#define O_TXDATAFIFO0__Tx0DataFifoSize 16
+#define W_TXDATAFIFO0__Tx0DataFifoSize 7
+#define O_TXDATAFIFO0__Tx1DataFifoStart 8
+#define W_TXDATAFIFO0__Tx1DataFifoStart 7
+#define O_TXDATAFIFO0__Tx1DataFifoSize 0
+#define W_TXDATAFIFO0__Tx1DataFifoSize 7
+#define R_TXDATAFIFO1 0x222
+#define O_TXDATAFIFO1__Tx2DataFifoStart 24
+#define W_TXDATAFIFO1__Tx2DataFifoStart 7
+#define O_TXDATAFIFO1__Tx2DataFifoSize 16
+#define W_TXDATAFIFO1__Tx2DataFifoSize 7
+#define O_TXDATAFIFO1__Tx3DataFifoStart 8
+#define W_TXDATAFIFO1__Tx3DataFifoStart 7
+#define O_TXDATAFIFO1__Tx3DataFifoSize 0
+#define W_TXDATAFIFO1__Tx3DataFifoSize 7
+#define R_TXDATAFIFO2 0x223
+#define O_TXDATAFIFO2__Tx4DataFifoStart 24
+#define W_TXDATAFIFO2__Tx4DataFifoStart 7
+#define O_TXDATAFIFO2__Tx4DataFifoSize 16
+#define W_TXDATAFIFO2__Tx4DataFifoSize 7
+#define O_TXDATAFIFO2__Tx5DataFifoStart 8
+#define W_TXDATAFIFO2__Tx5DataFifoStart 7
+#define O_TXDATAFIFO2__Tx5DataFifoSize 0
+#define W_TXDATAFIFO2__Tx5DataFifoSize 7
+#define R_TXDATAFIFO3 0x224
+#define O_TXDATAFIFO3__Tx6DataFifoStart 24
+#define W_TXDATAFIFO3__Tx6DataFifoStart 7
+#define O_TXDATAFIFO3__Tx6DataFifoSize 16
+#define W_TXDATAFIFO3__Tx6DataFifoSize 7
+#define O_TXDATAFIFO3__Tx7DataFifoStart 8
+#define W_TXDATAFIFO3__Tx7DataFifoStart 7
+#define O_TXDATAFIFO3__Tx7DataFifoSize 0
+#define W_TXDATAFIFO3__Tx7DataFifoSize 7
+#define R_TXDATAFIFO4 0x225
+#define O_TXDATAFIFO4__Tx8DataFifoStart 24
+#define W_TXDATAFIFO4__Tx8DataFifoStart 7
+#define O_TXDATAFIFO4__Tx8DataFifoSize 16
+#define W_TXDATAFIFO4__Tx8DataFifoSize 7
+#define O_TXDATAFIFO4__Tx9DataFifoStart 8
+#define W_TXDATAFIFO4__Tx9DataFifoStart 7
+#define O_TXDATAFIFO4__Tx9DataFifoSize 0
+#define W_TXDATAFIFO4__Tx9DataFifoSize 7
+#define R_TXDATAFIFO5 0x226
+#define O_TXDATAFIFO5__Tx10DataFifoStart 24
+#define W_TXDATAFIFO5__Tx10DataFifoStart 7
+#define O_TXDATAFIFO5__Tx10DataFifoSize 16
+#define W_TXDATAFIFO5__Tx10DataFifoSize 7
+#define O_TXDATAFIFO5__Tx11DataFifoStart 8
+#define W_TXDATAFIFO5__Tx11DataFifoStart 7
+#define O_TXDATAFIFO5__Tx11DataFifoSize 0
+#define W_TXDATAFIFO5__Tx11DataFifoSize 7
+#define R_TXDATAFIFO6 0x227
+#define O_TXDATAFIFO6__Tx12DataFifoStart 24
+#define W_TXDATAFIFO6__Tx12DataFifoStart 7
+#define O_TXDATAFIFO6__Tx12DataFifoSize 16
+#define W_TXDATAFIFO6__Tx12DataFifoSize 7
+#define O_TXDATAFIFO6__Tx13DataFifoStart 8
+#define W_TXDATAFIFO6__Tx13DataFifoStart 7
+#define O_TXDATAFIFO6__Tx13DataFifoSize 0
+#define W_TXDATAFIFO6__Tx13DataFifoSize 7
+#define R_TXDATAFIFO7 0x228
+#define O_TXDATAFIFO7__Tx14DataFifoStart 24
+#define W_TXDATAFIFO7__Tx14DataFifoStart 7
+#define O_TXDATAFIFO7__Tx14DataFifoSize 16
+#define W_TXDATAFIFO7__Tx14DataFifoSize 7
+#define O_TXDATAFIFO7__Tx15DataFifoStart 8
+#define W_TXDATAFIFO7__Tx15DataFifoStart 7
+#define O_TXDATAFIFO7__Tx15DataFifoSize 0
+#define W_TXDATAFIFO7__Tx15DataFifoSize 7
+#define R_RXDATAFIFO0 0x229
+#define O_RXDATAFIFO0__Rx0DataFifoStart 24
+#define W_RXDATAFIFO0__Rx0DataFifoStart 7
+#define O_RXDATAFIFO0__Rx0DataFifoSize 16
+#define W_RXDATAFIFO0__Rx0DataFifoSize 7
+#define O_RXDATAFIFO0__Rx1DataFifoStart 8
+#define W_RXDATAFIFO0__Rx1DataFifoStart 7
+#define O_RXDATAFIFO0__Rx1DataFifoSize 0
+#define W_RXDATAFIFO0__Rx1DataFifoSize 7
+#define R_RXDATAFIFO1 0x22A
+#define O_RXDATAFIFO1__Rx2DataFifoStart 24
+#define W_RXDATAFIFO1__Rx2DataFifoStart 7
+#define O_RXDATAFIFO1__Rx2DataFifoSize 16
+#define W_RXDATAFIFO1__Rx2DataFifoSize 7
+#define O_RXDATAFIFO1__Rx3DataFifoStart 8
+#define W_RXDATAFIFO1__Rx3DataFifoStart 7
+#define O_RXDATAFIFO1__Rx3DataFifoSize 0
+#define W_RXDATAFIFO1__Rx3DataFifoSize 7
+#define R_RXDATAFIFO2 0x22B
+#define O_RXDATAFIFO2__Rx4DataFifoStart 24
+#define W_RXDATAFIFO2__Rx4DataFifoStart 7
+#define O_RXDATAFIFO2__Rx4DataFifoSize 16
+#define W_RXDATAFIFO2__Rx4DataFifoSize 7
+#define O_RXDATAFIFO2__Rx5DataFifoStart 8
+#define W_RXDATAFIFO2__Rx5DataFifoStart 7
+#define O_RXDATAFIFO2__Rx5DataFifoSize 0
+#define W_RXDATAFIFO2__Rx5DataFifoSize 7
+#define R_RXDATAFIFO3 0x22C
+#define O_RXDATAFIFO3__Rx6DataFifoStart 24
+#define W_RXDATAFIFO3__Rx6DataFifoStart 7
+#define O_RXDATAFIFO3__Rx6DataFifoSize 16
+#define W_RXDATAFIFO3__Rx6DataFifoSize 7
+#define O_RXDATAFIFO3__Rx7DataFifoStart 8
+#define W_RXDATAFIFO3__Rx7DataFifoStart 7
+#define O_RXDATAFIFO3__Rx7DataFifoSize 0
+#define W_RXDATAFIFO3__Rx7DataFifoSize 7
+#define R_RXDATAFIFO4 0x22D
+#define O_RXDATAFIFO4__Rx8DataFifoStart 24
+#define W_RXDATAFIFO4__Rx8DataFifoStart 7
+#define O_RXDATAFIFO4__Rx8DataFifoSize 16
+#define W_RXDATAFIFO4__Rx8DataFifoSize 7
+#define O_RXDATAFIFO4__Rx9DataFifoStart 8
+#define W_RXDATAFIFO4__Rx9DataFifoStart 7
+#define O_RXDATAFIFO4__Rx9DataFifoSize 0
+#define W_RXDATAFIFO4__Rx9DataFifoSize 7
+#define R_RXDATAFIFO5 0x22E
+#define O_RXDATAFIFO5__Rx10DataFifoStart 24
+#define W_RXDATAFIFO5__Rx10DataFifoStart 7
+#define O_RXDATAFIFO5__Rx10DataFifoSize 16
+#define W_RXDATAFIFO5__Rx10DataFifoSize 7
+#define O_RXDATAFIFO5__Rx11DataFifoStart 8
+#define W_RXDATAFIFO5__Rx11DataFifoStart 7
+#define O_RXDATAFIFO5__Rx11DataFifoSize 0
+#define W_RXDATAFIFO5__Rx11DataFifoSize 7
+#define R_RXDATAFIFO6 0x22F
+#define O_RXDATAFIFO6__Rx12DataFifoStart 24
+#define W_RXDATAFIFO6__Rx12DataFifoStart 7
+#define O_RXDATAFIFO6__Rx12DataFifoSize 16
+#define W_RXDATAFIFO6__Rx12DataFifoSize 7
+#define O_RXDATAFIFO6__Rx13DataFifoStart 8
+#define W_RXDATAFIFO6__Rx13DataFifoStart 7
+#define O_RXDATAFIFO6__Rx13DataFifoSize 0
+#define W_RXDATAFIFO6__Rx13DataFifoSize 7
+#define R_RXDATAFIFO7 0x230
+#define O_RXDATAFIFO7__Rx14DataFifoStart 24
+#define W_RXDATAFIFO7__Rx14DataFifoStart 7
+#define O_RXDATAFIFO7__Rx14DataFifoSize 16
+#define W_RXDATAFIFO7__Rx14DataFifoSize 7
+#define O_RXDATAFIFO7__Rx15DataFifoStart 8
+#define W_RXDATAFIFO7__Rx15DataFifoStart 7
+#define O_RXDATAFIFO7__Rx15DataFifoSize 0
+#define W_RXDATAFIFO7__Rx15DataFifoSize 7
+#define R_XGMACPADCALIBRATION 0x231
+#define R_FREEQCARVE 0x233
+#define R_SPI4STATICDELAY0 0x240
+#define O_SPI4STATICDELAY0__DataLine7 28
+#define W_SPI4STATICDELAY0__DataLine7 4
+#define O_SPI4STATICDELAY0__DataLine6 24
+#define W_SPI4STATICDELAY0__DataLine6 4
+#define O_SPI4STATICDELAY0__DataLine5 20
+#define W_SPI4STATICDELAY0__DataLine5 4
+#define O_SPI4STATICDELAY0__DataLine4 16
+#define W_SPI4STATICDELAY0__DataLine4 4
+#define O_SPI4STATICDELAY0__DataLine3 12
+#define W_SPI4STATICDELAY0__DataLine3 4
+#define O_SPI4STATICDELAY0__DataLine2 8
+#define W_SPI4STATICDELAY0__DataLine2 4
+#define O_SPI4STATICDELAY0__DataLine1 4
+#define W_SPI4STATICDELAY0__DataLine1 4
+#define O_SPI4STATICDELAY0__DataLine0 0
+#define W_SPI4STATICDELAY0__DataLine0 4
+#define R_SPI4STATICDELAY1 0x241
+#define O_SPI4STATICDELAY1__DataLine15 28
+#define W_SPI4STATICDELAY1__DataLine15 4
+#define O_SPI4STATICDELAY1__DataLine14 24
+#define W_SPI4STATICDELAY1__DataLine14 4
+#define O_SPI4STATICDELAY1__DataLine13 20
+#define W_SPI4STATICDELAY1__DataLine13 4
+#define O_SPI4STATICDELAY1__DataLine12 16
+#define W_SPI4STATICDELAY1__DataLine12 4
+#define O_SPI4STATICDELAY1__DataLine11 12
+#define W_SPI4STATICDELAY1__DataLine11 4
+#define O_SPI4STATICDELAY1__DataLine10 8
+#define W_SPI4STATICDELAY1__DataLine10 4
+#define O_SPI4STATICDELAY1__DataLine9 4
+#define W_SPI4STATICDELAY1__DataLine9 4
+#define O_SPI4STATICDELAY1__DataLine8 0
+#define W_SPI4STATICDELAY1__DataLine8 4
+#define R_SPI4STATICDELAY2 0x242
+#define O_SPI4STATICDELAY0__TxStat1 8
+#define W_SPI4STATICDELAY0__TxStat1 4
+#define O_SPI4STATICDELAY0__TxStat0 4
+#define W_SPI4STATICDELAY0__TxStat0 4
+#define O_SPI4STATICDELAY0__RxControl 0
+#define W_SPI4STATICDELAY0__RxControl 4
+#define R_SPI4CONTROL 0x243
+#define O_SPI4CONTROL__StaticDelay 2
+#define O_SPI4CONTROL__LVDS_LVTTL 1
+#define O_SPI4CONTROL__SPI4Enable 0
+#define R_CLASSWATERMARKS 0x244
+#define O_CLASSWATERMARKS__Class0Watermark 24
+#define W_CLASSWATERMARKS__Class0Watermark 5
+#define O_CLASSWATERMARKS__Class1Watermark 16
+#define W_CLASSWATERMARKS__Class1Watermark 5
+#define O_CLASSWATERMARKS__Class3Watermark 0
+#define W_CLASSWATERMARKS__Class3Watermark 5
+#define R_RXWATERMARKS1 0x245
+#define O_RXWATERMARKS__Rx0DataWatermark 24
+#define W_RXWATERMARKS__Rx0DataWatermark 7
+#define O_RXWATERMARKS__Rx1DataWatermark 16
+#define W_RXWATERMARKS__Rx1DataWatermark 7
+#define O_RXWATERMARKS__Rx3DataWatermark 0
+#define W_RXWATERMARKS__Rx3DataWatermark 7
+#define R_RXWATERMARKS2 0x246
+#define O_RXWATERMARKS__Rx4DataWatermark 24
+#define W_RXWATERMARKS__Rx4DataWatermark 7
+#define O_RXWATERMARKS__Rx5DataWatermark 16
+#define W_RXWATERMARKS__Rx5DataWatermark 7
+#define O_RXWATERMARKS__Rx6DataWatermark 8
+#define W_RXWATERMARKS__Rx6DataWatermark 7
+#define O_RXWATERMARKS__Rx7DataWatermark 0
+#define W_RXWATERMARKS__Rx7DataWatermark 7
+#define R_RXWATERMARKS3 0x247
+#define O_RXWATERMARKS__Rx8DataWatermark 24
+#define W_RXWATERMARKS__Rx8DataWatermark 7
+#define O_RXWATERMARKS__Rx9DataWatermark 16
+#define W_RXWATERMARKS__Rx9DataWatermark 7
+#define O_RXWATERMARKS__Rx10DataWatermark 8
+#define W_RXWATERMARKS__Rx10DataWatermark 7
+#define O_RXWATERMARKS__Rx11DataWatermark 0
+#define W_RXWATERMARKS__Rx11DataWatermark 7
+#define R_RXWATERMARKS4 0x248
+#define O_RXWATERMARKS__Rx12DataWatermark 24
+#define W_RXWATERMARKS__Rx12DataWatermark 7
+#define O_RXWATERMARKS__Rx13DataWatermark 16
+#define W_RXWATERMARKS__Rx13DataWatermark 7
+#define O_RXWATERMARKS__Rx14DataWatermark 8
+#define W_RXWATERMARKS__Rx14DataWatermark 7
+#define O_RXWATERMARKS__Rx15DataWatermark 0
+#define W_RXWATERMARKS__Rx15DataWatermark 7
+#define R_FREEWATERMARKS 0x249
+#define O_FREEWATERMARKS__FreeOutWatermark 16
+#define W_FREEWATERMARKS__FreeOutWatermark 16
+#define O_FREEWATERMARKS__JumFrWatermark 8
+#define W_FREEWATERMARKS__JumFrWatermark 7
+#define O_FREEWATERMARKS__RegFrWatermark 0
+#define W_FREEWATERMARKS__RegFrWatermark 7
+#define R_EGRESSFIFOCARVINGSLOTS 0x24a
+
+#define CTRL_RES0 0
+#define CTRL_RES1 1
+#define CTRL_REG_FREE 2
+#define CTRL_JUMBO_FREE 3
+#define CTRL_CONT 4
+#define CTRL_EOP 5
+#define CTRL_START 6
+#define CTRL_SNGL 7
+
+#define CTRL_B0_NOT_EOP 0
+#define CTRL_B0_EOP 1
+
+#define R_ROUND_ROBIN_TABLE 0
+#define R_PDE_CLASS_0 0x300
+#define R_PDE_CLASS_1 0x302
+#define R_PDE_CLASS_2 0x304
+#define R_PDE_CLASS_3 0x306
+
+#define R_MSG_TX_THRESHOLD 0x308
+
+#define R_GMAC_JFR0_BUCKET_SIZE 0x320
+#define R_GMAC_RFR0_BUCKET_SIZE 0x321
+#define R_GMAC_TX0_BUCKET_SIZE 0x322
+#define R_GMAC_TX1_BUCKET_SIZE 0x323
+#define R_GMAC_TX2_BUCKET_SIZE 0x324
+#define R_GMAC_TX3_BUCKET_SIZE 0x325
+#define R_GMAC_JFR1_BUCKET_SIZE 0x326
+#define R_GMAC_RFR1_BUCKET_SIZE 0x327
+
+#define R_XGS_TX0_BUCKET_SIZE 0x320
+#define R_XGS_TX1_BUCKET_SIZE 0x321
+#define R_XGS_TX2_BUCKET_SIZE 0x322
+#define R_XGS_TX3_BUCKET_SIZE 0x323
+#define R_XGS_TX4_BUCKET_SIZE 0x324
+#define R_XGS_TX5_BUCKET_SIZE 0x325
+#define R_XGS_TX6_BUCKET_SIZE 0x326
+#define R_XGS_TX7_BUCKET_SIZE 0x327
+#define R_XGS_TX8_BUCKET_SIZE 0x328
+#define R_XGS_TX9_BUCKET_SIZE 0x329
+#define R_XGS_TX10_BUCKET_SIZE 0x32A
+#define R_XGS_TX11_BUCKET_SIZE 0x32B
+#define R_XGS_TX12_BUCKET_SIZE 0x32C
+#define R_XGS_TX13_BUCKET_SIZE 0x32D
+#define R_XGS_TX14_BUCKET_SIZE 0x32E
+#define R_XGS_TX15_BUCKET_SIZE 0x32F
+#define R_XGS_JFR_BUCKET_SIZE 0x330
+#define R_XGS_RFR_BUCKET_SIZE 0x331
+
+#define R_CC_CPU0_0 0x380
+#define R_CC_CPU1_0 0x388
+#define R_CC_CPU2_0 0x390
+#define R_CC_CPU3_0 0x398
+#define R_CC_CPU4_0 0x3a0
+#define R_CC_CPU5_0 0x3a8
+#define R_CC_CPU6_0 0x3b0
+#define R_CC_CPU7_0 0x3b8
+
+typedef enum {
+ xlr_mac_speed_10, xlr_mac_speed_100,
+ xlr_mac_speed_1000, xlr_mac_speed_rsvd
+} xlr_mac_speed_t;
+
+typedef enum {
+ xlr_mac_duplex_auto, xlr_mac_duplex_half,
+ xlr_mac_duplex_full
+} xlr_mac_duplex_t;
+
+typedef enum {
+ xlr_mac_link_down,
+ xlr_mac_link_up,
+} xlr_mac_link_t;
+
+typedef enum {
+ xlr_mac_fc_auto, xlr_mac_fc_disabled, xlr_mac_fc_frame,
+ xlr_mac_fc_collision, xlr_mac_fc_carrier
+} xlr_mac_fc_t;
+
+/* static int mac_frin_to_be_sent_thr[8]; */
+
+enum {
+ PORT_TX,
+ PORT_TX_COMPLETE,
+ PORT_STARTQ,
+ PORT_STOPQ,
+ PORT_START_DEV_STATE,
+ PORT_STOP_DEV_STATE,
+};
+
+struct rge_softc_stats {
+ unsigned int rx_frames;
+ unsigned int tx_frames;
+ unsigned int rx_packets;
+ unsigned int rx_bytes;
+ unsigned int tx_packets;
+ unsigned int tx_bytes;
+};
+
+struct driver_data {
+
+ /*
+ * Let these be the first fields in this structure the structure is
+ * cacheline aligned when allocated in init_etherdev
+ */
+ struct fr_desc *frin_spill;
+ struct fr_desc *frout_spill;
+ union rx_tx_desc *class_0_spill;
+ union rx_tx_desc *class_1_spill;
+ union rx_tx_desc *class_2_spill;
+ union rx_tx_desc *class_3_spill;
+ int spill_configured;
+
+ struct rge_softc *sc; /* pointer to freebsd device soft-pointer */
+ struct rge_softc_stats stats;
+ struct mtx lock;
+
+ xlr_reg_t *mmio;
+ xlr_reg_t *mii_mmio;
+ xlr_reg_t *pcs_mmio;
+ xlr_reg_t *serdes_mmio;
+
+ int txbucket;
+ int rfrbucket;
+
+ int phy_oldbmsr;
+ int phy_oldanlpar;
+ int phy_oldk1stsr;
+ int phy_oldlinkstat;
+ unsigned char phys_addr[2];
+
+ xlr_mac_speed_t speed; /* current speed */
+ xlr_mac_duplex_t duplex;/* current duplex */
+ xlr_mac_link_t link; /* current link */
+ xlr_mac_fc_t flow_ctrl; /* current flow control setting */
+ int advertising;
+
+ int id;
+ int type;
+ int mode;
+ int instance;
+ int phy_addr;
+ int frin_to_be_sent[8];
+ int init_frin_desc;
+};
+
+struct rge_softc {
+ int unit;
+ int irq;
+ unsigned char dev_addr[6];
+ unsigned long base_addr;
+ unsigned long mem_end;
+ struct ifnet *rge_ifp; /* interface info */
+ device_t rge_dev;
+ int mtu;
+ int flags;
+ struct driver_data priv;
+ struct mtx rge_mtx;
+ device_t rge_miibus;
+ struct mii_data rge_mii;/* MII/media information */
+ bus_space_handle_t rge_bhandle;
+ bus_space_tag_t rge_btag;
+ void *rge_intrhand;
+ struct resource rge_irq;
+ struct resource *rge_res;
+ struct ifmedia rge_ifmedia; /* TBI media info */
+ int rge_if_flags;
+ int rge_link; /* link state */
+ int rge_link_evt; /* pending link event */
+ struct callout rge_stat_ch;
+ void (*xmit) (struct ifnet *);
+ void (*stop) (struct rge_softc *);
+ int (*ioctl) (struct ifnet *, u_long, caddr_t);
+ struct rge_softc_stats *(*get_stats) (struct rge_softc *);
+ int active;
+ int link_up;
+};
+
+struct size_1_desc {
+ uint64_t entry0;
+};
+
+struct size_2_desc {
+ uint64_t entry0;
+ uint64_t entry1;
+};
+
+struct size_3_desc {
+ uint64_t entry0;
+ uint64_t entry1;
+ uint64_t entry2;
+};
+
+struct size_4_desc {
+ uint64_t entry0;
+ uint64_t entry1;
+ uint64_t entry2;
+ uint64_t entry3;
+};
+
+struct fr_desc {
+ struct size_1_desc d1;
+};
+
+union rx_tx_desc {
+ struct size_2_desc d2;
+ /* struct size_3_desc d3; */
+ /* struct size_4_desc d4; */
+};
+
+
+extern unsigned char xlr_base_mac_addr[];
+
+#endif
Property changes on: trunk/sys/mips/rmi/dev/xlr/rge.h
___________________________________________________________________
Added: svn:eol-style
## -0,0 +1 ##
+native
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## -0,0 +1 ##
+MidnightBSD=%H
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## -0,0 +1 ##
+text/plain
\ No newline at end of property
Added: trunk/sys/mips/rmi/dev/xlr/xgmac_mdio.h
===================================================================
--- trunk/sys/mips/rmi/dev/xlr/xgmac_mdio.h (rev 0)
+++ trunk/sys/mips/rmi/dev/xlr/xgmac_mdio.h 2018-05-26 21:55:02 UTC (rev 9987)
@@ -0,0 +1,128 @@
+/* $MidnightBSD$ */
+/*-
+ * Copyright (c) 2003-2009 RMI Corporation
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * 3. Neither the name of RMI Corporation, nor the names of its contributors,
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ * RMI_BSD */
+/* MDIO Low level Access routines */
+/* All Phy's accessed from GMAC0 base */
+
+#ifndef _XGMAC_MDIO_H_
+#define _XGMAC_MDIO_H_
+
+static inline int
+xmdio_read(volatile unsigned int *_mmio,
+ uint32_t phy_addr, uint32_t address);
+static inline void
+xmdio_write(volatile unsigned int *_mmio,
+ uint32_t phy_addr, uint32_t address, uint32_t data);
+static inline void
+xmdio_address(volatile unsigned int *_mmio,
+ uint32_t phy_addr, uint32_t dev_ad, uint32_t address);
+
+static inline void
+xmdio_address(volatile unsigned int *_mmio,
+ uint32_t phy_addr, uint32_t dev_ad, uint32_t address)
+{
+ uint32_t st_field = 0x0;
+ uint32_t op_type = 0x0; /* address operation */
+ uint32_t ta_field = 0x2;/* ta field */
+
+ _mmio[0x11] = ((st_field & 0x3) << 30) |
+ ((op_type & 0x3) << 28) |
+ ((phy_addr & 0x1F) << 23) |
+ ((dev_ad & 0x1F) << 18) |
+ ((ta_field & 0x3) << 16) |
+ ((address & 0xffff) << 0);
+
+ _mmio[0x10] = (0x0 << 3) | 0x5;
+ _mmio[0x10] = (0x1 << 3) | 0x5;
+ _mmio[0x10] = (0x0 << 3) | 0x5;
+
+ /* wait for dev_ad cycle to complete */
+ while (_mmio[0x14] & 0x1) {
+ };
+
+}
+
+/* function prototypes */
+static inline int
+xmdio_read(volatile unsigned int *_mmio,
+ uint32_t phy_addr, uint32_t address)
+{
+ uint32_t st_field = 0x0;
+ uint32_t op_type = 0x3; /* read operation */
+ uint32_t ta_field = 0x2;/* ta field */
+ uint32_t data = 0;
+
+ xmdio_address(_mmio, phy_addr, 5, address);
+ _mmio[0x11] = ((st_field & 0x3) << 30) |
+ ((op_type & 0x3) << 28) |
+ ((phy_addr & 0x1F) << 23) |
+ ((5 & 0x1F) << 18) |
+ ((ta_field & 0x3) << 16) |
+ ((data & 0xffff) << 0);
+
+ _mmio[0x10] = (0x0 << 3) | 0x5;
+ _mmio[0x10] = (0x1 << 3) | 0x5;
+ _mmio[0x10] = (0x0 << 3) | 0x5;
+
+ /* wait for write cycle to complete */
+ while (_mmio[0x14] & 0x1) {
+ };
+
+ data = _mmio[0x11] & 0xffff;
+ return (data);
+}
+
+static inline void
+xmdio_write(volatile unsigned int *_mmio,
+ uint32_t phy_addr, uint32_t address, uint32_t data)
+{
+ uint32_t st_field = 0x0;
+ uint32_t op_type = 0x1; /* write operation */
+ uint32_t ta_field = 0x2;/* ta field */
+
+ xmdio_address(_mmio, phy_addr, 5, address);
+ _mmio[0x11] = ((st_field & 0x3) << 30) |
+ ((op_type & 0x3) << 28) |
+ ((phy_addr & 0x1F) << 23) |
+ ((5 & 0x1F) << 18) |
+ ((ta_field & 0x3) << 16) |
+ ((data & 0xffff) << 0);
+
+ _mmio[0x10] = (0x0 << 3) | 0x5;
+ _mmio[0x10] = (0x1 << 3) | 0x5;
+ _mmio[0x10] = (0x0 << 3) | 0x5;
+
+ /* wait for write cycle to complete */
+ while (_mmio[0x14] & 0x1) {
+ };
+
+}
+
+#endif
Property changes on: trunk/sys/mips/rmi/dev/xlr/xgmac_mdio.h
___________________________________________________________________
Added: svn:eol-style
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+native
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+MidnightBSD=%H
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+text/plain
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Added: trunk/sys/mips/rmi/files.xlr
===================================================================
--- trunk/sys/mips/rmi/files.xlr (rev 0)
+++ trunk/sys/mips/rmi/files.xlr 2018-05-26 21:55:02 UTC (rev 9987)
@@ -0,0 +1,27 @@
+# $FreeBSD: stable/10/sys/mips/rmi/files.xlr 216390 2010-12-12 06:00:26Z jchandra $
+#mips/rmi/xlr_boot1_console.c standard
+mips/rmi/xlr_machdep.c standard
+#mips/rmi/clock.c standard
+mips/rmi/tick.c standard
+mips/rmi/iodi.c standard
+mips/rmi/msgring.c standard
+mips/rmi/msgring_xls.c standard
+mips/rmi/board.c standard
+mips/rmi/fmn.c standard
+mips/rmi/intr_machdep.c standard
+mips/rmi/mpwait.S optional smp
+mips/rmi/xlr_i2c.c optional iic
+mips/rmi/uart_bus_xlr_iodi.c optional uart
+mips/rmi/uart_cpu_mips_xlr.c optional uart
+mips/rmi/xlr_pci.c optional pci
+mips/rmi/xlr_pcmcia.c optional ata
+mips/rmi/xls_ehci.c optional usb ehci
+mips/rmi/bus_space_rmi.c standard
+mips/rmi/bus_space_rmi_pci.c standard
+mips/rmi/dev/sec/rmisec.c optional rmisec
+mips/rmi/dev/sec/rmilib.c optional rmisec
+mips/rmi/dev/xlr/rge.c optional rge
+mips/rmi/dev/nlge/if_nlge.c optional nlge
+mips/rmi/dev/iic/ds1374u.c optional ds1374u
+mips/rmi/dev/iic/max6657.c optional max6657
+mips/rmi/dev/iic/at24co2n.c optional at24co2n
Property changes on: trunk/sys/mips/rmi/files.xlr
___________________________________________________________________
Added: mnbsd:nokeywords
## -0,0 +1 ##
+MidnightBSD=%H
\ No newline at end of property
Added: trunk/sys/mips/rmi/fmn.c
===================================================================
--- trunk/sys/mips/rmi/fmn.c (rev 0)
+++ trunk/sys/mips/rmi/fmn.c 2018-05-26 21:55:02 UTC (rev 9987)
@@ -0,0 +1,497 @@
+/* $MidnightBSD$ */
+/*-
+ * Copyright (c) 2003-2009 RMI Corporation
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * 3. Neither the name of RMI Corporation, nor the names of its contributors,
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ * RMI_BSD */
+#include <sys/cdefs.h>
+__FBSDID("$FreeBSD: stable/10/sys/mips/rmi/fmn.c 223562 2011-06-26 10:07:48Z kevlo $");
+#include <sys/types.h>
+#include <sys/systm.h>
+#include <sys/param.h>
+#include <sys/lock.h>
+#include <sys/mutex.h>
+#include <sys/proc.h>
+#include <sys/limits.h>
+#include <sys/bus.h>
+
+#include <sys/ktr.h>
+#include <sys/kernel.h>
+#include <sys/kthread.h>
+#include <sys/resourcevar.h>
+#include <sys/sched.h>
+#include <sys/unistd.h>
+#include <sys/sysctl.h>
+#include <sys/malloc.h>
+
+#include <machine/reg.h>
+#include <machine/cpu.h>
+#include <machine/hwfunc.h>
+#include <machine/mips_opcode.h>
+
+#include <machine/param.h>
+#include <machine/intr_machdep.h>
+#include <mips/rmi/interrupt.h>
+#include <mips/rmi/msgring.h>
+#include <mips/rmi/pic.h>
+#include <mips/rmi/board.h>
+
+#define MSGRNG_CC_INIT_CPU_DEST(dest, counter) \
+do { \
+ msgrng_write_cc(MSGRNG_CC_##dest##_REG, counter[dest][0], 0 ); \
+ msgrng_write_cc(MSGRNG_CC_##dest##_REG, counter[dest][1], 1 ); \
+ msgrng_write_cc(MSGRNG_CC_##dest##_REG, counter[dest][2], 2 ); \
+ msgrng_write_cc(MSGRNG_CC_##dest##_REG, counter[dest][3], 3 ); \
+ msgrng_write_cc(MSGRNG_CC_##dest##_REG, counter[dest][4], 4 ); \
+ msgrng_write_cc(MSGRNG_CC_##dest##_REG, counter[dest][5], 5 ); \
+ msgrng_write_cc(MSGRNG_CC_##dest##_REG, counter[dest][6], 6 ); \
+ msgrng_write_cc(MSGRNG_CC_##dest##_REG, counter[dest][7], 7 ); \
+} while(0)
+
+
+/*
+ * Keep track of our message ring handler threads, each core has a
+ * different message station. Ideally we will need to start a few
+ * message handling threads every core, and wake them up depending on
+ * load
+ */
+struct msgring_thread {
+ struct {
+ struct thread *thread; /* msgring handler threads */
+ int needed; /* thread needs to wake up */
+ } threads[XLR_NTHREADS];
+ int running; /* number of threads running */
+ int nthreads; /* number of threads started */
+ struct mtx lock; /* for changing running/active */
+};
+static struct msgring_thread msgring_threads[XLR_MAX_CORES];
+static struct proc *msgring_proc; /* all threads are under a proc */
+
+/*
+ * The maximum number of software message handler threads to be started
+ * per core. Default is 3 per core
+ */
+static int msgring_maxthreads = 3;
+TUNABLE_INT("hw.fmn.maxthreads", &msgring_maxthreads);
+
+/*
+ * The device drivers can register a handler for the messages sent
+ * from a station (corresponding to the device).
+ */
+struct tx_stn_handler {
+ msgring_handler action;
+ void *arg;
+};
+static struct tx_stn_handler msgmap[MSGRNG_NSTATIONS];
+static struct mtx msgmap_lock;
+
+/*
+ * Initialize the messaging subsystem.
+ *
+ * Message Stations are shared among all threads in a cpu core, this
+ * has to be called once from every core which is online.
+ */
+void
+xlr_msgring_cpu_init(void)
+{
+ struct stn_cc *cc_config;
+ struct bucket_size *bucket_sizes;
+ uint32_t flags;
+ int id;
+
+ KASSERT(xlr_thr_id() == 0,
+ ("xlr_msgring_cpu_init from non-zero thread"));
+ id = xlr_core_id();
+ bucket_sizes = xlr_board_info.bucket_sizes;
+ cc_config = xlr_board_info.credit_configs[id];
+
+ flags = msgrng_access_enable();
+
+ /*
+ * FMN messages are received in 8 buckets per core, set up
+ * the bucket sizes for each bucket
+ */
+ msgrng_write_bucksize(0, bucket_sizes->bucket[id * 8 + 0]);
+ msgrng_write_bucksize(1, bucket_sizes->bucket[id * 8 + 1]);
+ msgrng_write_bucksize(2, bucket_sizes->bucket[id * 8 + 2]);
+ msgrng_write_bucksize(3, bucket_sizes->bucket[id * 8 + 3]);
+ msgrng_write_bucksize(4, bucket_sizes->bucket[id * 8 + 4]);
+ msgrng_write_bucksize(5, bucket_sizes->bucket[id * 8 + 5]);
+ msgrng_write_bucksize(6, bucket_sizes->bucket[id * 8 + 6]);
+ msgrng_write_bucksize(7, bucket_sizes->bucket[id * 8 + 7]);
+
+ /*
+ * For sending FMN messages, we need credits on the destination
+ * bucket. Program the credits this core has on the 128 possible
+ * destination buckets.
+ * We cannot use a loop here, because the first argument has
+ * to be a constant integer value.
+ */
+ MSGRNG_CC_INIT_CPU_DEST(0, cc_config->counters);
+ MSGRNG_CC_INIT_CPU_DEST(1, cc_config->counters);
+ MSGRNG_CC_INIT_CPU_DEST(2, cc_config->counters);
+ MSGRNG_CC_INIT_CPU_DEST(3, cc_config->counters);
+ MSGRNG_CC_INIT_CPU_DEST(4, cc_config->counters);
+ MSGRNG_CC_INIT_CPU_DEST(5, cc_config->counters);
+ MSGRNG_CC_INIT_CPU_DEST(6, cc_config->counters);
+ MSGRNG_CC_INIT_CPU_DEST(7, cc_config->counters);
+ MSGRNG_CC_INIT_CPU_DEST(8, cc_config->counters);
+ MSGRNG_CC_INIT_CPU_DEST(9, cc_config->counters);
+ MSGRNG_CC_INIT_CPU_DEST(10, cc_config->counters);
+ MSGRNG_CC_INIT_CPU_DEST(11, cc_config->counters);
+ MSGRNG_CC_INIT_CPU_DEST(12, cc_config->counters);
+ MSGRNG_CC_INIT_CPU_DEST(13, cc_config->counters);
+ MSGRNG_CC_INIT_CPU_DEST(14, cc_config->counters);
+ MSGRNG_CC_INIT_CPU_DEST(15, cc_config->counters);
+ msgrng_restore(flags);
+}
+
+/*
+ * Boot time init, called only once
+ */
+void
+xlr_msgring_config(void)
+{
+ mtx_init(&msgmap_lock, "msgring", NULL, MTX_SPIN);
+
+ /* check value */
+ if (msgring_maxthreads < 0 || msgring_maxthreads > XLR_NTHREADS)
+ msgring_maxthreads = XLR_NTHREADS;
+}
+
+/*
+ * Drain out max_messages for the buckets set in the bucket mask.
+ * Use max_messages = 0 to drain out all messages.
+ */
+uint32_t
+xlr_msgring_handler(uint8_t bucket_mask, uint32_t max_messages)
+{
+ int bucket = 0;
+ int size = 0, code = 0, rx_stid = 0;
+ struct msgrng_msg msg;
+ struct tx_stn_handler *he;
+ unsigned int status = 0;
+ unsigned long mflags;
+ uint32_t n_msgs;
+ uint32_t msgbuckets;
+
+ n_msgs = 0;
+ mflags = msgrng_access_enable();
+ for (;;) {
+ msgbuckets = (~msgrng_read_status() >> 24) & bucket_mask;
+
+ /* all buckets empty, break */
+ if (msgbuckets == 0)
+ break;
+
+ for (bucket = 0; bucket < 8; bucket++) {
+ if ((msgbuckets & (1 << bucket)) == 0) /* empty */
+ continue;
+
+ status = message_receive(bucket, &size, &code,
+ &rx_stid, &msg);
+ if (status != 0)
+ continue;
+ n_msgs++;
+ he = &msgmap[rx_stid];
+ if (he->action == NULL) {
+ printf("[%s]: No Handler for message from "
+ "stn_id=%d, bucket=%d, size=%d, msg0=%jx\n",
+ __func__, rx_stid, bucket, size,
+ (uintmax_t)msg.msg0);
+ } else {
+ msgrng_restore(mflags);
+ (*he->action)(bucket, size, code, rx_stid,
+ &msg, he->arg);
+ mflags = msgrng_access_enable();
+ }
+ if (max_messages > 0 && n_msgs >= max_messages)
+ goto done;
+ }
+ }
+
+done:
+ msgrng_restore(mflags);
+ return (n_msgs);
+}
+
+/*
+ * XLR COP2 supports watermark interrupts based on the number of
+ * messages pending in all the buckets in the core. We increase
+ * the watermark until all the possible handler threads in the core
+ * are woken up.
+ */
+static void
+msgrng_setconfig(int running, int nthr)
+{
+ uint32_t config, mflags;
+ int watermark = 1; /* non zero needed */
+ int wm_intr_value;
+
+ KASSERT(nthr >= 0 && nthr <= msgring_maxthreads,
+ ("Bad value of nthr %d", nthr));
+ KASSERT(running <= nthr, ("Bad value of running %d", running));
+
+ if (running == nthr) {
+ wm_intr_value = 0;
+ } else {
+ switch (running) {
+ case 0: break; /* keep default */
+ case 1:
+ watermark = 32; break;
+ case 2:
+ watermark = 48; break;
+ case 3:
+ watermark = 56; break;
+ }
+ wm_intr_value = 0x2; /* set watermark enable interrupt */
+ }
+ mflags = msgrng_access_enable();
+ config = (watermark << 24) | (IRQ_MSGRING << 16) | (1 << 8) |
+ wm_intr_value;
+ /* clear pending interrupts, they will get re-raised if still valid */
+ write_c0_eirr64(1ULL << IRQ_MSGRING);
+ msgrng_write_config(config);
+ msgrng_restore(mflags);
+}
+
+/* Debug counters */
+static int msgring_nintr[XLR_MAX_CORES];
+static int msgring_badintr[XLR_MAX_CORES];
+static int msgring_wakeup_sleep[XLR_MAX_CORES * XLR_NTHREADS];
+static int msgring_wakeup_nosleep[XLR_MAX_CORES * XLR_NTHREADS];
+static int msgring_nmsgs[XLR_MAX_CORES * XLR_NTHREADS];
+
+static int
+msgring_process_fast_intr(void *arg)
+{
+ struct msgring_thread *mthd;
+ struct thread *td;
+ uint32_t mflags;
+ int core, nt;
+
+ core = xlr_core_id();
+ mthd = &msgring_threads[core];
+ msgring_nintr[core]++;
+ mtx_lock_spin(&mthd->lock);
+ nt = mthd->running;
+ if(nt >= mthd->nthreads) {
+ msgring_badintr[core]++;
+ mtx_unlock_spin(&mthd->lock);
+ return (FILTER_HANDLED);
+ }
+
+ td = mthd->threads[nt].thread;
+ mflags = msgrng_access_enable();
+
+ /* default value with interrupts disabled */
+ msgrng_write_config((1 << 24) | (IRQ_MSGRING << 16) | (1 << 8));
+ /* clear pending interrupts */
+ write_c0_eirr64(1ULL << IRQ_MSGRING);
+ msgrng_restore(mflags);
+ mtx_unlock_spin(&mthd->lock);
+
+ /* wake up the target thread */
+ mthd->threads[nt].needed = 1;
+ thread_lock(td);
+ if (TD_AWAITING_INTR(td)) {
+ msgring_wakeup_sleep[core*4+nt]++;
+ TD_CLR_IWAIT(td);
+ sched_add(td, SRQ_INTR);
+ } else
+ msgring_wakeup_nosleep[core*4+nt]++;
+ thread_unlock(td);
+ return (FILTER_HANDLED);
+}
+
+static void
+msgring_process(void *arg)
+{
+ struct msgring_thread *mthd;
+ struct thread *td;
+ int hwtid, tid, core;
+ int nmsgs;
+
+ hwtid = (intptr_t)arg;
+ core = hwtid / 4;
+ tid = hwtid % 4;
+ mthd = &msgring_threads[core];
+ td = mthd->threads[tid].thread;
+ KASSERT(curthread == td,
+ ("Incorrect thread core %d, thread %d", core, hwtid));
+
+ /* First bind this thread to the right CPU */
+ thread_lock(td);
+ sched_bind(td, xlr_hwtid_to_cpuid[hwtid]);
+ thread_unlock(td);
+
+ mtx_lock_spin(&mthd->lock);
+ ++mthd->nthreads; /* Active thread count */
+ mtx_unlock_spin(&mthd->lock);
+
+ /* start processing messages */
+ for(;;) {
+ mtx_lock_spin(&mthd->lock);
+ ++mthd->running;
+ msgrng_setconfig(mthd->running, mthd->nthreads);
+ mtx_unlock_spin(&mthd->lock);
+
+ atomic_store_rel_int(&mthd->threads[tid].needed, 0);
+ nmsgs = xlr_msgring_handler(0xff, 0);
+ msgring_nmsgs[hwtid] += nmsgs;
+
+ mtx_lock_spin(&mthd->lock);
+ --mthd->running;
+ msgrng_setconfig(mthd->running, mthd->nthreads);
+ mtx_unlock_spin(&mthd->lock);
+
+ /* sleep */
+ thread_lock(td);
+ if (mthd->threads[tid].needed) {
+ thread_unlock(td);
+ continue;
+ }
+ sched_class(td, PRI_ITHD);
+ TD_SET_IWAIT(td);
+ mi_switch(SW_VOL, NULL);
+ thread_unlock(td);
+ }
+}
+
+static void
+create_msgring_thread(int hwtid)
+{
+ struct msgring_thread *mthd;
+ struct thread *td;
+ int tid, core;
+ int error;
+
+ core = hwtid / 4;
+ tid = hwtid % 4;
+ mthd = &msgring_threads[core];
+ if (tid == 0) {
+ mtx_init(&mthd->lock, "msgrngcore", NULL, MTX_SPIN);
+ mthd->running = mthd->nthreads = 0;
+ }
+ error = kproc_kthread_add(msgring_process, (void *)(uintptr_t)hwtid,
+ &msgring_proc, &td, RFSTOPPED, 2, "msgrngproc",
+ "msgthr%d", hwtid);
+ if (error)
+ panic("kproc_kthread_add() failed with %d", error);
+ mthd->threads[tid].thread = td;
+
+ thread_lock(td);
+ sched_class(td, PRI_ITHD);
+ sched_add(td, SRQ_INTR);
+ thread_unlock(td);
+ CTR2(KTR_INTR, "%s: created %s", __func__, td->td_name);
+}
+
+int
+register_msgring_handler(int startb, int endb, msgring_handler action,
+ void *arg)
+{
+ void *cookie;
+ int i;
+ static int msgring_int_enabled = 0;
+
+ KASSERT(startb >= 0 && startb <= endb && endb < MSGRNG_NSTATIONS,
+ ("Invalid value for for bucket range %d,%d", startb, endb));
+
+ mtx_lock_spin(&msgmap_lock);
+ for (i = startb; i <= endb; i++) {
+ KASSERT(msgmap[i].action == NULL,
+ ("Bucket %d already used [action %p]", i, msgmap[i].action));
+ msgmap[i].action = action;
+ msgmap[i].arg = arg;
+ }
+ mtx_unlock_spin(&msgmap_lock);
+
+ if (xlr_test_and_set(&msgring_int_enabled)) {
+ create_msgring_thread(0);
+ if (msgring_maxthreads > xlr_threads_per_core)
+ msgring_maxthreads = xlr_threads_per_core;
+ cpu_establish_hardintr("msgring", msgring_process_fast_intr,
+ NULL, NULL, IRQ_MSGRING,
+ INTR_TYPE_NET, &cookie);
+ }
+ return (0);
+}
+
+/*
+ * Start message ring processing threads on other CPUs, after SMP start
+ */
+static void
+start_msgring_threads(void *arg)
+{
+ int hwt, tid;
+
+ for (hwt = 1; hwt < XLR_MAX_CORES * XLR_NTHREADS; hwt++) {
+ if ((xlr_hw_thread_mask & (1 << hwt)) == 0)
+ continue;
+ tid = hwt % XLR_NTHREADS;
+ if (tid >= msgring_maxthreads)
+ continue;
+ create_msgring_thread(hwt);
+ }
+}
+
+SYSINIT(start_msgring_threads, SI_SUB_SMP, SI_ORDER_MIDDLE,
+ start_msgring_threads, NULL);
+
+/*
+ * DEBUG support, XXX: static buffer, not locked
+ */
+static int
+sys_print_debug(SYSCTL_HANDLER_ARGS)
+{
+ int error, nb, i, fs;
+ static char xprintb[4096], *buf;
+
+ buf = xprintb;
+ fs = sizeof(xprintb);
+ nb = snprintf(buf, fs,
+ "\nID INTR ER WU-SLP WU-ERR MSGS\n");
+ buf += nb;
+ fs -= nb;
+ for (i = 0; i < 32; i++) {
+ if ((xlr_hw_thread_mask & (1 << i)) == 0)
+ continue;
+ nb = snprintf(buf, fs,
+ "%2d: %8d %4d %8d %8d %8d\n", i,
+ msgring_nintr[i/4], msgring_badintr[i/4],
+ msgring_wakeup_sleep[i], msgring_wakeup_nosleep[i],
+ msgring_nmsgs[i]);
+ buf += nb;
+ fs -= nb;
+ }
+ error = SYSCTL_OUT(req, xprintb, buf - xprintb);
+ return (error);
+}
+
+SYSCTL_PROC(_debug, OID_AUTO, msgring, CTLTYPE_STRING | CTLFLAG_RD, 0, 0,
+ sys_print_debug, "A", "msgring debug info");
Property changes on: trunk/sys/mips/rmi/fmn.c
___________________________________________________________________
Added: svn:eol-style
## -0,0 +1 ##
+native
\ No newline at end of property
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## -0,0 +1 ##
+MidnightBSD=%H
\ No newline at end of property
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## -0,0 +1 ##
+text/plain
\ No newline at end of property
Added: trunk/sys/mips/rmi/interrupt.h
===================================================================
--- trunk/sys/mips/rmi/interrupt.h (rev 0)
+++ trunk/sys/mips/rmi/interrupt.h 2018-05-26 21:55:02 UTC (rev 9987)
@@ -0,0 +1,51 @@
+/* $MidnightBSD$ */
+/*-
+ * Copyright (c) 2003-2009 RMI Corporation
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * 3. Neither the name of RMI Corporation, nor the names of its contributors,
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ * RMI_BSD
+ * $FreeBSD: stable/10/sys/mips/rmi/interrupt.h 211994 2010-08-30 13:05:21Z jchandra $
+ */
+#ifndef _RMI_INTERRUPT_H_
+#define _RMI_INTERRUPT_H_
+
+/* Defines for the IRQ numbers */
+
+#define IRQ_IPI 41 /* 8-39 are mapped by PIC intr 0-31 */
+#define IRQ_MSGRING 6
+#define IRQ_TIMER 7
+
+/*
+ * XLR needs custom pre and post handlers for PCI/PCI-e interrupts
+ * XXX: maybe follow i386 intsrc model
+ */
+void xlr_establish_intr(const char *name, driver_filter_t filt,
+ driver_intr_t handler, void *arg, int irq, int flags,
+ void **cookiep, void (*busack)(int));
+void xlr_enable_irq(int irq);
+
+#endif /* _RMI_INTERRUPT_H_ */
Property changes on: trunk/sys/mips/rmi/interrupt.h
___________________________________________________________________
Added: svn:eol-style
## -0,0 +1 ##
+native
\ No newline at end of property
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## -0,0 +1 ##
+MidnightBSD=%H
\ No newline at end of property
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## -0,0 +1 ##
+text/plain
\ No newline at end of property
Added: trunk/sys/mips/rmi/intr_machdep.c
===================================================================
--- trunk/sys/mips/rmi/intr_machdep.c (rev 0)
+++ trunk/sys/mips/rmi/intr_machdep.c 2018-05-26 21:55:02 UTC (rev 9987)
@@ -0,0 +1,250 @@
+/* $MidnightBSD$ */
+/*-
+ * Copyright (c) 2006-2009 RMI Corporation
+ * Copyright (c) 2002-2004 Juli Mallett <jmallett at FreeBSD.org>
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions, and the following disclaimer,
+ * without modification, immediately at the beginning of the file.
+ * 2. The name of the author may not be used to endorse or promote products
+ * derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ */
+
+#include <sys/cdefs.h>
+__FBSDID("$FreeBSD: stable/10/sys/mips/rmi/intr_machdep.c 212102 2010-09-01 17:35:31Z jchandra $");
+
+#include <sys/param.h>
+#include <sys/systm.h>
+#include <sys/bus.h>
+#include <sys/interrupt.h>
+#include <sys/kernel.h>
+
+#include <machine/cpu.h>
+#include <machine/cpufunc.h>
+#include <machine/cpuinfo.h>
+#include <machine/cpuregs.h>
+#include <machine/frame.h>
+#include <machine/intr_machdep.h>
+#include <machine/md_var.h>
+#include <machine/trap.h>
+#include <machine/hwfunc.h>
+
+#include <mips/rmi/rmi_mips_exts.h>
+#include <mips/rmi/interrupt.h>
+#include <mips/rmi/pic.h>
+
+struct xlr_intrsrc {
+ void (*busack)(int); /* Additional ack */
+ struct intr_event *ie; /* event corresponding to intr */
+ int irq;
+};
+
+static struct xlr_intrsrc xlr_interrupts[XLR_MAX_INTR];
+static mips_intrcnt_t mips_intr_counters[XLR_MAX_INTR];
+static int intrcnt_index;
+
+void
+xlr_enable_irq(int irq)
+{
+ uint64_t eimr;
+
+ eimr = read_c0_eimr64();
+ write_c0_eimr64(eimr | (1ULL << irq));
+}
+
+void
+cpu_establish_softintr(const char *name, driver_filter_t * filt,
+ void (*handler) (void *), void *arg, int irq, int flags,
+ void **cookiep)
+{
+
+ panic("Soft interrupts unsupported!\n");
+}
+
+void
+cpu_establish_hardintr(const char *name, driver_filter_t * filt,
+ void (*handler) (void *), void *arg, int irq, int flags,
+ void **cookiep)
+{
+
+ xlr_establish_intr(name, filt, handler, arg, irq, flags,
+ cookiep, NULL);
+}
+
+static void
+xlr_post_filter(void *source)
+{
+ struct xlr_intrsrc *src = source;
+
+ if (src->busack)
+ src->busack(src->irq);
+ pic_ack(PIC_IRQ_TO_INTR(src->irq));
+}
+
+static void
+xlr_pre_ithread(void *source)
+{
+ struct xlr_intrsrc *src = source;
+
+ if (src->busack)
+ src->busack(src->irq);
+}
+
+static void
+xlr_post_ithread(void *source)
+{
+ struct xlr_intrsrc *src = source;
+
+ pic_ack(PIC_IRQ_TO_INTR(src->irq));
+}
+
+void
+xlr_establish_intr(const char *name, driver_filter_t filt,
+ driver_intr_t handler, void *arg, int irq, int flags,
+ void **cookiep, void (*busack)(int))
+{
+ struct intr_event *ie; /* descriptor for the IRQ */
+ struct xlr_intrsrc *src = NULL;
+ int errcode;
+
+ if (irq < 0 || irq > XLR_MAX_INTR)
+ panic("%s called for unknown hard intr %d", __func__, irq);
+
+ /*
+ * FIXME locking - not needed now, because we do this only on
+ * startup from CPU0
+ */
+ src = &xlr_interrupts[irq];
+ ie = src->ie;
+ if (ie == NULL) {
+ /*
+ * PIC based interrupts need ack in PIC, and some SoC
+ * components need additional acks (e.g. PCI)
+ */
+ if (PIC_IRQ_IS_PICINTR(irq))
+ errcode = intr_event_create(&ie, src, 0, irq,
+ xlr_pre_ithread, xlr_post_ithread, xlr_post_filter,
+ NULL, "hard intr%d:", irq);
+ else {
+ if (filt == NULL)
+ panic("Not supported - non filter percpu intr");
+ errcode = intr_event_create(&ie, src, 0, irq,
+ NULL, NULL, NULL, NULL, "hard intr%d:", irq);
+ }
+ if (errcode) {
+ printf("Could not create event for intr %d\n", irq);
+ return;
+ }
+ src->irq = irq;
+ src->busack = busack;
+ src->ie = ie;
+ }
+ intr_event_add_handler(ie, name, filt, handler, arg,
+ intr_priority(flags), flags, cookiep);
+ xlr_enable_irq(irq);
+}
+
+void
+cpu_intr(struct trapframe *tf)
+{
+ struct intr_event *ie;
+ uint64_t eirr, eimr;
+ int i;
+
+ critical_enter();
+
+ /* find a list of enabled interrupts */
+ eirr = read_c0_eirr64();
+ eimr = read_c0_eimr64();
+ eirr &= eimr;
+
+ if (eirr == 0) {
+ critical_exit();
+ return;
+ }
+ /*
+ * No need to clear the EIRR here as the handler writes to
+ * compare which ACKs the interrupt.
+ */
+ if (eirr & (1 << IRQ_TIMER)) {
+ intr_event_handle(xlr_interrupts[IRQ_TIMER].ie, tf);
+ critical_exit();
+ return;
+ }
+
+ /* FIXME sched pin >? LOCK>? */
+ for (i = sizeof(eirr) * 8 - 1; i >= 0; i--) {
+ if ((eirr & (1ULL << i)) == 0)
+ continue;
+
+ ie = xlr_interrupts[i].ie;
+ /* Don't account special IRQs */
+ switch (i) {
+ case IRQ_IPI:
+ case IRQ_MSGRING:
+ break;
+ default:
+ mips_intrcnt_inc(mips_intr_counters[i]);
+ }
+
+ /* Ack the IRQ on the CPU */
+ write_c0_eirr64(1ULL << i);
+ if (intr_event_handle(ie, tf) != 0) {
+ printf("stray interrupt %d\n", i);
+ }
+ }
+ critical_exit();
+}
+
+void
+mips_intrcnt_setname(mips_intrcnt_t counter, const char *name)
+{
+ int idx = counter - intrcnt;
+
+ KASSERT(counter != NULL, ("mips_intrcnt_setname: NULL counter"));
+
+ snprintf(intrnames + (MAXCOMLEN + 1) * idx,
+ MAXCOMLEN + 1, "%-*s", MAXCOMLEN, name);
+}
+
+mips_intrcnt_t
+mips_intrcnt_create(const char* name)
+{
+ mips_intrcnt_t counter = &intrcnt[intrcnt_index++];
+
+ mips_intrcnt_setname(counter, name);
+ return counter;
+}
+
+void
+cpu_init_interrupts()
+{
+ int i;
+ char name[MAXCOMLEN + 1];
+
+ /*
+ * Initialize all available vectors so spare IRQ
+ * would show up in systat output
+ */
+ for (i = 0; i < XLR_MAX_INTR; i++) {
+ snprintf(name, MAXCOMLEN + 1, "int%d:", i);
+ mips_intr_counters[i] = mips_intrcnt_create(name);
+ }
+}
Property changes on: trunk/sys/mips/rmi/intr_machdep.c
___________________________________________________________________
Added: svn:eol-style
## -0,0 +1 ##
+native
\ No newline at end of property
Added: svn:keywords
## -0,0 +1 ##
+MidnightBSD=%H
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Added: svn:mime-type
## -0,0 +1 ##
+text/plain
\ No newline at end of property
Added: trunk/sys/mips/rmi/iodi.c
===================================================================
--- trunk/sys/mips/rmi/iodi.c (rev 0)
+++ trunk/sys/mips/rmi/iodi.c 2018-05-26 21:55:02 UTC (rev 9987)
@@ -0,0 +1,322 @@
+/* $MidnightBSD$ */
+/*-
+ * Copyright (c) 2003-2009 RMI Corporation
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * 3. Neither the name of RMI Corporation, nor the names of its contributors,
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ * RMI_BSD
+ */
+
+#include <sys/cdefs.h>
+__FBSDID("$FreeBSD: stable/10/sys/mips/rmi/iodi.c 265999 2014-05-14 01:35:43Z ian $");
+
+#define __RMAN_RESOURCE_VISIBLE
+#include <sys/param.h>
+#include <sys/systm.h>
+#include <sys/bus.h>
+#include <sys/kernel.h>
+#include <sys/lock.h>
+#include <sys/mutex.h>
+#include <sys/reboot.h>
+#include <sys/rman.h>
+#include <sys/types.h>
+#include <sys/malloc.h>
+#include <sys/interrupt.h>
+#include <sys/module.h>
+
+#include <machine/cpu.h>
+#include <machine/bus.h>
+#include <machine/param.h>
+#include <machine/intr_machdep.h>
+#include <machine/clock.h> /* for DELAY */
+#include <machine/resource.h>
+
+#include <mips/rmi/board.h>
+#include <mips/rmi/pic.h>
+#include <mips/rmi/interrupt.h>
+#include <mips/rmi/msgring.h>
+#include <mips/rmi/iomap.h>
+#include <mips/rmi/rmi_mips_exts.h>
+
+#include <mips/rmi/dev/xlr/atx_cpld.h>
+#include <mips/rmi/dev/xlr/xgmac_mdio.h>
+
+extern bus_space_tag_t uart_bus_space_mem;
+
+static struct resource *
+iodi_alloc_resource(device_t, device_t, int, int *,
+ u_long, u_long, u_long, u_int);
+
+static int
+iodi_activate_resource(device_t, device_t, int, int,
+ struct resource *);
+static int
+iodi_setup_intr(device_t, device_t, struct resource *, int,
+ driver_filter_t *, driver_intr_t *, void *, void **);
+
+struct iodi_softc *iodi_softc; /* There can be only one. */
+
+/*
+ * We will manage the Flash/PCMCIA devices in IODI for now.
+ * The NOR flash, Compact flash etc. which can be connected on
+ * various chip selects on the peripheral IO, should have a
+ * separate bus later.
+ */
+static void
+bridge_pcmcia_ack(int irq)
+{
+ xlr_reg_t *mmio = xlr_io_mmio(XLR_IO_FLASH_OFFSET);
+
+ xlr_write_reg(mmio, 0x60, 0xffffffff);
+}
+
+static int
+iodi_setup_intr(device_t dev, device_t child,
+ struct resource *ires, int flags, driver_filter_t *filt,
+ driver_intr_t *intr, void *arg, void **cookiep)
+{
+ const char *name = device_get_name(child);
+
+ if (strcmp(name, "uart") == 0) {
+ /* FIXME uart 1? */
+ cpu_establish_hardintr("uart", filt, intr, arg,
+ PIC_UART_0_IRQ, flags, cookiep);
+ pic_setup_intr(PIC_IRT_UART_0_INDEX, PIC_UART_0_IRQ, 0x1, 1);
+ } else if (strcmp(name, "rge") == 0 || strcmp(name, "nlge") == 0) {
+ int irq;
+
+ /* This is a hack to pass in the irq */
+ irq = (intptr_t)ires->__r_i;
+ cpu_establish_hardintr("rge", filt, intr, arg, irq, flags,
+ cookiep);
+ pic_setup_intr(irq - PIC_IRQ_BASE, irq, 0x1, 1);
+ } else if (strcmp(name, "ehci") == 0) {
+ cpu_establish_hardintr("ehci", filt, intr, arg, PIC_USB_IRQ, flags,
+ cookiep);
+ pic_setup_intr(PIC_USB_IRQ - PIC_IRQ_BASE, PIC_USB_IRQ, 0x1, 1);
+ } else if (strcmp(name, "ata") == 0) {
+ xlr_establish_intr("ata", filt, intr, arg, PIC_PCMCIA_IRQ, flags,
+ cookiep, bridge_pcmcia_ack);
+ pic_setup_intr(PIC_PCMCIA_IRQ - PIC_IRQ_BASE, PIC_PCMCIA_IRQ, 0x1, 1);
+ }
+ return (0);
+}
+
+static struct resource *
+iodi_alloc_resource(device_t bus, device_t child, int type, int *rid,
+ u_long start, u_long end, u_long count, u_int flags)
+{
+ struct resource *res = malloc(sizeof(*res), M_DEVBUF, M_WAITOK);
+ const char *name = device_get_name(child);
+ int unit;
+
+#ifdef DEBUG
+ switch (type) {
+ case SYS_RES_IRQ:
+ device_printf(bus, "IRQ resource - for %s %lx-%lx\n",
+ device_get_nameunit(child), start, end);
+ break;
+
+ case SYS_RES_IOPORT:
+ device_printf(bus, "IOPORT resource - for %s %lx-%lx\n",
+ device_get_nameunit(child), start, end);
+ break;
+
+ case SYS_RES_MEMORY:
+ device_printf(bus, "MEMORY resource - for %s %lx-%lx\n",
+ device_get_nameunit(child), start, end);
+ break;
+ }
+#endif
+
+ if (strcmp(name, "uart") == 0) {
+ if ((unit = device_get_unit(child)) == 0) { /* uart 0 */
+ res->r_bushandle = (xlr_io_base + XLR_IO_UART_0_OFFSET);
+ } else if (unit == 1) {
+ res->r_bushandle = (xlr_io_base + XLR_IO_UART_1_OFFSET);
+ } else
+ printf("%s: Unknown uart unit\n", __FUNCTION__);
+
+ res->r_bustag = uart_bus_space_mem;
+ } else if (strcmp(name, "ehci") == 0) {
+ res->r_bushandle = MIPS_PHYS_TO_KSEG1(0x1ef24000);
+ res->r_bustag = rmi_pci_bus_space;
+ } else if (strcmp(name, "cfi") == 0) {
+ res->r_bushandle = MIPS_PHYS_TO_KSEG1(0x1c000000);
+ res->r_bustag = 0;
+ } else if (strcmp(name, "ata") == 0) {
+ res->r_bushandle = MIPS_PHYS_TO_KSEG1(0x1d000000);
+ res->r_bustag = rmi_pci_bus_space; /* byte swapping (not really PCI) */
+ }
+ /* res->r_start = *rid; */
+ return (res);
+}
+
+static int
+iodi_activate_resource(device_t bus, device_t child, int type, int rid,
+ struct resource *r)
+{
+ return (0);
+}
+
+/* prototypes */
+static int iodi_probe(device_t);
+static int iodi_attach(device_t);
+static int iodi_detach(device_t);
+static void iodi_identify(driver_t *, device_t);
+
+int
+iodi_probe(device_t dev)
+{
+ return (BUS_PROBE_NOWILDCARD);
+}
+
+void
+iodi_identify(driver_t * driver, device_t parent)
+{
+
+ BUS_ADD_CHILD(parent, 0, "iodi", 0);
+}
+
+int
+iodi_attach(device_t dev)
+{
+ device_t tmpd;
+ int i;
+
+ /*
+ * Attach each devices
+ */
+ device_add_child(dev, "uart", 0);
+ device_add_child(dev, "xlr_i2c", 0);
+ device_add_child(dev, "xlr_i2c", 1);
+ device_add_child(dev, "pcib", 0);
+ device_add_child(dev, "rmisec", -1);
+
+ if (xlr_board_info.usb)
+ device_add_child(dev, "ehci", 0);
+
+ if (xlr_board_info.cfi)
+ device_add_child(dev, "cfi", 0);
+
+ if (xlr_board_info.ata)
+ device_add_child(dev, "ata", 0);
+
+ if (xlr_board_info.gmac_block[0].enabled) {
+ tmpd = device_add_child(dev, "rge", 0);
+ device_set_ivars(tmpd, &xlr_board_info.gmac_block[0]);
+
+ tmpd = device_add_child(dev, "rge", 1);
+ device_set_ivars(tmpd, &xlr_board_info.gmac_block[0]);
+
+ tmpd = device_add_child(dev, "rge", 2);
+ device_set_ivars(tmpd, &xlr_board_info.gmac_block[0]);
+
+ tmpd = device_add_child(dev, "rge", 3);
+ device_set_ivars(tmpd, &xlr_board_info.gmac_block[0]);
+ }
+ if (xlr_board_info.gmac_block[1].enabled) {
+ if (xlr_board_info.gmac_block[1].type == XLR_GMAC) {
+ tmpd = device_add_child(dev, "rge", 4);
+ device_set_ivars(tmpd, &xlr_board_info.gmac_block[1]);
+
+ tmpd = device_add_child(dev, "rge", 5);
+ device_set_ivars(tmpd, &xlr_board_info.gmac_block[1]);
+
+ if (xlr_board_info.gmac_block[1].enabled & 0x4) {
+ tmpd = device_add_child(dev, "rge", 6);
+ device_set_ivars(tmpd, &xlr_board_info.gmac_block[1]);
+ }
+
+ if (xlr_board_info.gmac_block[1].enabled & 0x8) {
+ tmpd = device_add_child(dev, "rge", 7);
+ device_set_ivars(tmpd, &xlr_board_info.gmac_block[1]);
+ }
+ } else if (xlr_board_info.gmac_block[1].type == XLR_XGMAC) {
+#if 0 /* XGMAC not yet */
+ tmpd = device_add_child(dev, "rge", 4);
+ device_set_ivars(tmpd, &xlr_board_info.gmac_block[1]);
+
+ tmpd = device_add_child(dev, "rge", 5);
+ device_set_ivars(tmpd, &xlr_board_info.gmac_block[1]);
+#endif
+ } else
+ device_printf(dev, "Unknown type of gmac 1\n");
+ }
+
+ /* This is to add the new GMAC driver. The above adds the old driver,
+ which has been retained for now as the new driver is stabilized.
+ The new driver is enabled with "option nlge". Make sure that only
+ one of rge or nlge is enabled in the conf file. */
+ for (i = 0; i < 3; i++) {
+ if (xlr_board_info.gmac_block[i].enabled == 0)
+ continue;
+ tmpd = device_add_child(dev, "nlna", i);
+ device_set_ivars(tmpd, &xlr_board_info.gmac_block[i]);
+ }
+ bus_generic_probe(dev);
+ bus_generic_attach(dev);
+ return 0;
+}
+
+int
+iodi_detach(device_t dev)
+{
+ device_t nlna_dev;
+ int error, i, ret;
+
+ error = 0;
+ ret = 0;
+ for (i = 0; i < 3; i++) {
+ nlna_dev = device_find_child(dev, "nlna", i);
+ if (nlna_dev != NULL)
+ error = bus_generic_detach(nlna_dev);
+ if (error)
+ ret = error;
+ }
+ return ret;
+}
+
+static device_method_t iodi_methods[] = {
+ DEVMETHOD(device_probe, iodi_probe),
+ DEVMETHOD(device_attach, iodi_attach),
+ DEVMETHOD(device_detach, iodi_detach),
+ DEVMETHOD(device_identify, iodi_identify),
+ DEVMETHOD(bus_alloc_resource, iodi_alloc_resource),
+ DEVMETHOD(bus_activate_resource, iodi_activate_resource),
+ DEVMETHOD(bus_add_child, bus_generic_add_child),
+ DEVMETHOD(bus_setup_intr, iodi_setup_intr),
+ {0, 0},
+};
+
+static driver_t iodi_driver = {
+ "iodi",
+ iodi_methods,
+ 1 /* no softc */
+};
+static devclass_t iodi_devclass;
+
+DRIVER_MODULE(iodi, nexus, iodi_driver, iodi_devclass, 0, 0);
Property changes on: trunk/sys/mips/rmi/iodi.c
___________________________________________________________________
Added: svn:eol-style
## -0,0 +1 ##
+native
\ No newline at end of property
Added: svn:keywords
## -0,0 +1 ##
+MidnightBSD=%H
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+text/plain
\ No newline at end of property
Added: trunk/sys/mips/rmi/iomap.h
===================================================================
--- trunk/sys/mips/rmi/iomap.h (rev 0)
+++ trunk/sys/mips/rmi/iomap.h 2018-05-26 21:55:02 UTC (rev 9987)
@@ -0,0 +1,116 @@
+/* $MidnightBSD$ */
+/*-
+ * Copyright (c) 2003-2009 RMI Corporation
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * 3. Neither the name of RMI Corporation, nor the names of its contributors,
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ * RMI_BSD
+ * $FreeBSD: stable/10/sys/mips/rmi/iomap.h 211994 2010-08-30 13:05:21Z jchandra $
+ */
+#ifndef _RMI_IOMAP_H_
+#define _RMI_IOMAP_H_
+
+#include <machine/endian.h>
+#define XLR_DEVICE_REGISTER_BASE 0x1EF00000
+#define DEFAULT_XLR_IO_BASE 0xffffffffbef00000ULL
+#define XLR_IO_SIZE 0x1000
+
+#define XLR_IO_BRIDGE_OFFSET 0x00000
+
+#define XLR_IO_DDR2_CHN0_OFFSET 0x01000
+#define XLR_IO_DDR2_CHN1_OFFSET 0x02000
+#define XLR_IO_DDR2_CHN2_OFFSET 0x03000
+#define XLR_IO_DDR2_CHN3_OFFSET 0x04000
+
+#define XLR_IO_RLD2_CHN0_OFFSET 0x05000
+#define XLR_IO_RLD2_CHN1_OFFSET 0x06000
+
+#define XLR_IO_SRAM_OFFSET 0x07000
+
+#define XLR_IO_PIC_OFFSET 0x08000
+#define XLR_IO_PCIX_OFFSET 0x09000
+#define XLR_IO_HT_OFFSET 0x0A000
+
+#define XLR_IO_SECURITY_OFFSET 0x0B000
+
+#define XLR_IO_GMAC_0_OFFSET 0x0C000
+#define XLR_IO_GMAC_1_OFFSET 0x0D000
+#define XLR_IO_GMAC_2_OFFSET 0x0E000
+#define XLR_IO_GMAC_3_OFFSET 0x0F000
+
+#define XLR_IO_SPI4_0_OFFSET 0x10000
+#define XLR_IO_XGMAC_0_OFFSET 0x11000
+#define XLR_IO_SPI4_1_OFFSET 0x12000
+#define XLR_IO_XGMAC_1_OFFSET 0x13000
+
+#define XLR_IO_UART_0_OFFSET 0x14000
+#define XLR_IO_UART_1_OFFSET 0x15000
+#define XLR_UART0ADDR (XLR_IO_UART_0_OFFSET+XLR_DEVICE_REGISTER_BASE)
+
+
+
+#define XLR_IO_I2C_0_OFFSET 0x16000
+#define XLR_IO_I2C_1_OFFSET 0x17000
+
+#define XLR_IO_GPIO_OFFSET 0x18000
+
+#define XLR_IO_FLASH_OFFSET 0x19000
+
+#define XLR_IO_TB_OFFSET 0x1C000
+
+#define XLR_IO_GMAC_4_OFFSET 0x20000
+#define XLR_IO_GMAC_5_OFFSET 0x21000
+#define XLR_IO_GMAC_6_OFFSET 0x22000
+#define XLR_IO_GMAC_7_OFFSET 0x23000
+
+#define XLR_IO_PCIE_0_OFFSET 0x1E000
+#define XLR_IO_PCIE_1_OFFSET 0x1F000
+
+#define XLR_IO_USB_0_OFFSET 0x24000
+#define XLR_IO_USB_1_OFFSET 0x25000
+
+#define XLR_IO_COMP_OFFSET 0x1d000
+
+/* Base Address (Virtual) of the PCI Config address space
+ * For now, choose 256M phys in kseg1 = 0xA0000000 + (1<<28)
+ * Config space spans 256 (num of buses) * 256 (num functions) * 256 bytes
+ * ie 1<<24 = 16M
+ */
+#define DEFAULT_PCI_CONFIG_BASE 0x18000000
+#define DEFAULT_HT_TYPE0_CFG_BASE 0x16000000
+#define DEFAULT_HT_TYPE1_CFG_BASE 0x17000000
+
+typedef volatile __uint32_t xlr_reg_t;
+extern unsigned long xlr_io_base;
+
+#define xlr_io_mmio(offset) ((xlr_reg_t *)(xlr_io_base+(offset)))
+
+#define xlr_read_reg(base, offset) (__ntohl((base)[(offset)]))
+#define xlr_write_reg(base, offset, value) ((base)[(offset)] = __htonl((value)))
+
+extern void on_chip_init(void);
+
+#endif /* _RMI_IOMAP_H_ */
Property changes on: trunk/sys/mips/rmi/iomap.h
___________________________________________________________________
Added: svn:eol-style
## -0,0 +1 ##
+native
\ No newline at end of property
Added: svn:keywords
## -0,0 +1 ##
+MidnightBSD=%H
\ No newline at end of property
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## -0,0 +1 ##
+text/plain
\ No newline at end of property
Added: trunk/sys/mips/rmi/mpwait.S
===================================================================
--- trunk/sys/mips/rmi/mpwait.S (rev 0)
+++ trunk/sys/mips/rmi/mpwait.S 2018-05-26 21:55:02 UTC (rev 9987)
@@ -0,0 +1,69 @@
+/* $MidnightBSD$ */
+/*-
+ * Copyright (c) 2010 RMI Technologies Ltd.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ * $FreeBSD: stable/10/sys/mips/rmi/mpwait.S 208250 2010-05-18 04:08:58Z rrs $
+ */
+
+#include <machine/asm.h>
+#include <machine/cpu.h>
+#include <machine/cpuregs.h>
+
+#include "assym.s"
+
+ .text
+ .set noat
+ .set noreorder
+
+/*
+ * On XLR the slave processors and threads will be executing boot
+ * loader code on startup. We need to make them run our code before
+ * blowing away boot loader memory.
+ */
+LEAF(mpwait)
+ PTR_LA gp, _C_LABEL(_gp)
+ PTR_LA t1, _C_LABEL(xlr_ap_release)
+ mfc0 t2, $15, 1
+ andi t2, 0x1f
+ sll t2, t2, 2
+ add t1, t2
+
+1: lw t0, 0(t1)
+ bnez t0, 2f
+ nop /* We should not busy wait in core0 threads */
+ nop /* on bootup, this will slow the cpu0 thread */
+ nop /* down - TODO - wait with IPI based wakeup */
+ nop
+ nop
+ nop
+ nop
+ nop
+ j 1b
+ nop
+2:
+ PTR_LA t1, _C_LABEL(mpentry)
+ jr t1
+ nop
+END(mpwait)
Property changes on: trunk/sys/mips/rmi/mpwait.S
___________________________________________________________________
Added: svn:eol-style
## -0,0 +1 ##
+native
\ No newline at end of property
Added: svn:keywords
## -0,0 +1 ##
+MidnightBSD=%H
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+text/plain
\ No newline at end of property
Added: trunk/sys/mips/rmi/msgring.c
===================================================================
--- trunk/sys/mips/rmi/msgring.c (rev 0)
+++ trunk/sys/mips/rmi/msgring.c 2018-05-26 21:55:02 UTC (rev 9987)
@@ -0,0 +1,318 @@
+/* $MidnightBSD$ */
+/*-
+ * Copyright (c) 2003-2009 RMI Corporation
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * 3. Neither the name of RMI Corporation, nor the names of its contributors,
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ * RMI_BSD */
+/**********************************************************
+ * -----------------DO NOT EDIT THIS FILE------------------
+ * This file has been autogenerated by the build process
+ * from "msgring.cfg"
+ **********************************************************/
+
+#include <mips/rmi/msgring.h>
+
+struct bucket_size bucket_sizes = {
+ {
+ 32, 32, 32, 32, 32, 32, 32, 32,
+ 32, 32, 32, 32, 32, 32, 32, 32,
+ 32, 32, 32, 32, 32, 32, 32, 32,
+ 32, 32, 32, 32, 32, 32, 32, 32,
+ 32, 32, 32, 32, 32, 32, 32, 32,
+ 32, 32, 32, 32, 32, 32, 32, 32,
+ 32, 32, 32, 32, 32, 32, 32, 32,
+ 32, 32, 32, 32, 32, 32, 32, 32,
+ 32, 16, 16, 16, 16, 16, 16, 16,
+ 16, 16, 16, 16, 16, 16, 16, 0,
+ 32, 16, 16, 16, 16, 16, 16, 16,
+ 16, 16, 16, 16, 16, 16, 16, 0,
+ 0, 32, 32, 32, 32, 32, 0, 32,
+ 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 32, 0, 32, 0, 0, 0, 0,
+ 128, 0, 0, 0, 128, 0, 0, 0,
+ }
+};
+
+struct stn_cc cc_table_cpu_0 = {{
+
+ {0, 0, 0, 0, 0, 0, 0, 0},
+ {0, 0, 0, 4, 0, 0, 0, 0},
+ {0, 0, 0, 0, 0, 0, 0, 0},
+ {0, 0, 0, 0, 0, 0, 0, 0},
+ {0, 0, 0, 0, 0, 0, 0, 0},
+ {0, 0, 0, 0, 0, 0, 0, 0},
+ {0, 0, 0, 0, 0, 0, 0, 0},
+ {0, 0, 0, 0, 0, 0, 0, 0},
+ {4, 2, 2, 2, 2, 2, 2, 2},
+ {2, 2, 2, 2, 2, 2, 2, 0},
+ {4, 2, 2, 2, 2, 2, 2, 2},
+ {2, 2, 2, 2, 2, 2, 2, 0},
+ {0, 2, 4, 4, 4, 4, 0, 2},
+ {0, 0, 0, 0, 0, 0, 0, 0},
+ {0, 2, 0, 2, 0, 0, 0, 0},
+ {16, 0, 0, 0, 16, 0, 0, 0},
+}};
+
+struct stn_cc cc_table_cpu_1 = {{
+
+ {0, 0, 0, 0, 0, 0, 0, 0},
+ {0, 0, 0, 0, 0, 0, 0, 0},
+ {0, 0, 0, 0, 0, 0, 0, 0},
+ {0, 0, 0, 0, 0, 0, 0, 0},
+ {0, 0, 0, 0, 0, 0, 0, 0},
+ {0, 0, 0, 0, 0, 0, 0, 0},
+ {0, 0, 0, 0, 0, 0, 0, 0},
+ {0, 0, 0, 0, 0, 0, 0, 0},
+ {4, 2, 2, 2, 2, 2, 2, 2},
+ {2, 2, 2, 2, 2, 2, 2, 0},
+ {4, 2, 2, 2, 2, 2, 2, 2},
+ {2, 2, 2, 2, 2, 2, 2, 0},
+ {0, 2, 4, 4, 4, 4, 0, 2},
+ {0, 0, 0, 0, 0, 0, 0, 0},
+ {0, 2, 0, 2, 0, 0, 0, 0},
+ {16, 0, 0, 0, 16, 0, 0, 0},
+}};
+
+struct stn_cc cc_table_cpu_2 = {{
+
+ {0, 0, 0, 0, 0, 0, 0, 0},
+ {0, 0, 0, 0, 0, 0, 0, 0},
+ {0, 0, 0, 0, 0, 0, 0, 0},
+ {0, 0, 0, 0, 0, 0, 0, 0},
+ {0, 0, 0, 0, 0, 0, 0, 0},
+ {0, 0, 0, 0, 0, 0, 0, 0},
+ {0, 0, 0, 0, 0, 0, 0, 0},
+ {0, 0, 0, 0, 0, 0, 0, 0},
+ {4, 2, 2, 2, 2, 2, 2, 2},
+ {2, 2, 2, 2, 2, 2, 2, 0},
+ {4, 2, 2, 2, 2, 2, 2, 2},
+ {2, 2, 2, 2, 2, 2, 2, 0},
+ {0, 4, 4, 4, 4, 4, 0, 4},
+ {0, 0, 0, 0, 0, 0, 0, 0},
+ {0, 4, 0, 4, 0, 0, 0, 0},
+ {16, 0, 0, 0, 16, 0, 0, 0},
+}};
+
+struct stn_cc cc_table_cpu_3 = {{
+
+ {0, 0, 0, 0, 0, 0, 0, 0},
+ {0, 0, 0, 0, 0, 0, 0, 0},
+ {0, 0, 0, 0, 0, 0, 0, 0},
+ {0, 0, 0, 0, 0, 0, 0, 0},
+ {0, 0, 0, 0, 0, 0, 0, 0},
+ {0, 0, 0, 0, 0, 0, 0, 0},
+ {0, 0, 0, 0, 0, 0, 0, 0},
+ {0, 0, 0, 0, 0, 0, 0, 0},
+ {4, 2, 2, 2, 2, 2, 2, 2},
+ {2, 2, 2, 2, 2, 2, 2, 0},
+ {4, 2, 2, 2, 2, 2, 2, 2},
+ {2, 2, 2, 2, 2, 2, 2, 0},
+ {0, 4, 4, 4, 4, 4, 0, 4},
+ {0, 0, 0, 0, 0, 0, 0, 0},
+ {0, 4, 0, 4, 0, 0, 0, 0},
+ {16, 0, 0, 0, 16, 0, 0, 0},
+}};
+
+struct stn_cc cc_table_cpu_4 = {{
+
+ {0, 0, 0, 0, 0, 0, 0, 0},
+ {0, 0, 0, 0, 0, 0, 0, 0},
+ {0, 0, 0, 0, 0, 0, 0, 0},
+ {0, 0, 0, 0, 0, 0, 0, 0},
+ {0, 0, 0, 0, 0, 0, 0, 0},
+ {0, 0, 0, 0, 0, 0, 0, 0},
+ {0, 0, 0, 0, 0, 0, 0, 0},
+ {0, 0, 0, 0, 0, 0, 0, 0},
+ {4, 2, 2, 2, 2, 2, 2, 2},
+ {2, 2, 2, 2, 2, 2, 2, 0},
+ {4, 2, 2, 2, 2, 2, 2, 2},
+ {2, 2, 2, 2, 2, 2, 2, 0},
+ {0, 4, 4, 4, 4, 4, 0, 4},
+ {0, 0, 0, 0, 0, 0, 0, 0},
+ {0, 4, 0, 4, 0, 0, 0, 0},
+ {16, 0, 0, 0, 16, 0, 0, 0},
+}};
+
+struct stn_cc cc_table_cpu_5 = {{
+
+ {0, 0, 0, 0, 0, 0, 0, 0},
+ {0, 0, 0, 0, 0, 0, 0, 0},
+ {0, 0, 0, 0, 0, 0, 0, 0},
+ {0, 0, 0, 0, 0, 0, 0, 0},
+ {0, 0, 0, 0, 0, 0, 0, 0},
+ {0, 0, 0, 0, 0, 0, 0, 0},
+ {0, 0, 0, 0, 0, 0, 0, 0},
+ {0, 0, 0, 0, 0, 0, 0, 0},
+ {4, 2, 2, 2, 2, 2, 2, 2},
+ {2, 2, 2, 2, 2, 2, 2, 0},
+ {4, 2, 2, 2, 2, 2, 2, 2},
+ {2, 2, 2, 2, 2, 2, 2, 0},
+ {0, 4, 4, 4, 4, 4, 0, 4},
+ {0, 0, 0, 0, 0, 0, 0, 0},
+ {0, 4, 0, 4, 0, 0, 0, 0},
+ {16, 0, 0, 0, 16, 0, 0, 0},
+}};
+
+struct stn_cc cc_table_cpu_6 = {{
+
+ {0, 0, 0, 0, 0, 0, 0, 0},
+ {0, 0, 0, 0, 0, 0, 0, 0},
+ {0, 0, 0, 0, 0, 0, 0, 0},
+ {0, 0, 0, 0, 0, 0, 0, 0},
+ {0, 0, 0, 0, 0, 0, 0, 0},
+ {0, 0, 0, 0, 0, 0, 0, 0},
+ {0, 0, 0, 0, 0, 0, 0, 0},
+ {0, 0, 0, 0, 0, 0, 0, 0},
+ {4, 2, 2, 2, 2, 2, 2, 2},
+ {2, 2, 2, 2, 2, 2, 2, 0},
+ {4, 2, 2, 2, 2, 2, 2, 2},
+ {2, 2, 2, 2, 2, 2, 2, 0},
+ {0, 4, 4, 4, 4, 4, 0, 4},
+ {0, 0, 0, 0, 0, 0, 0, 0},
+ {0, 4, 0, 4, 0, 0, 0, 0},
+ {16, 0, 0, 0, 16, 0, 0, 0},
+}};
+
+struct stn_cc cc_table_cpu_7 = {{
+
+ {0, 0, 0, 0, 0, 0, 0, 0},
+ {0, 0, 0, 0, 0, 0, 0, 0},
+ {0, 0, 0, 0, 0, 0, 0, 0},
+ {0, 0, 0, 0, 0, 0, 0, 0},
+ {0, 0, 0, 0, 0, 0, 0, 0},
+ {0, 0, 0, 0, 0, 0, 0, 0},
+ {0, 0, 0, 0, 0, 0, 0, 0},
+ {0, 0, 0, 0, 0, 0, 0, 0},
+ {4, 2, 2, 2, 2, 2, 2, 2},
+ {2, 2, 2, 2, 2, 2, 2, 0},
+ {4, 2, 2, 2, 2, 2, 2, 2},
+ {2, 2, 2, 2, 2, 2, 2, 0},
+ {0, 4, 4, 4, 4, 4, 0, 4},
+ {0, 0, 0, 0, 0, 0, 0, 0},
+ {0, 4, 0, 4, 0, 0, 0, 0},
+ {16, 0, 0, 0, 16, 0, 0, 0},
+}};
+
+struct stn_cc cc_table_xgs_0 = {{
+
+ {8, 8, 8, 8, 8, 8, 8, 8},
+ {8, 8, 8, 8, 8, 8, 8, 8},
+ {8, 8, 8, 8, 8, 8, 8, 8},
+ {8, 8, 8, 8, 8, 8, 8, 8},
+ {8, 8, 8, 8, 8, 8, 8, 8},
+ {8, 8, 8, 8, 8, 8, 8, 8},
+ {8, 8, 8, 8, 8, 8, 8, 8},
+ {8, 8, 8, 8, 8, 8, 8, 8},
+ {0, 0, 0, 0, 0, 0, 0, 0},
+ {0, 0, 0, 0, 0, 0, 0, 0},
+ {0, 0, 0, 0, 0, 0, 0, 0},
+ {0, 0, 0, 0, 0, 0, 0, 0},
+ {0, 0, 0, 0, 0, 0, 0, 0},
+ {0, 0, 0, 0, 0, 0, 0, 0},
+ {0, 4, 0, 0, 0, 0, 0, 0},
+ {0, 0, 0, 0, 0, 0, 0, 0},
+}};
+
+struct stn_cc cc_table_xgs_1 = {{
+
+ {8, 8, 8, 8, 8, 8, 8, 8},
+ {8, 8, 8, 8, 8, 8, 8, 8},
+ {8, 8, 8, 8, 8, 8, 8, 8},
+ {8, 8, 8, 8, 8, 8, 8, 8},
+ {8, 8, 8, 8, 8, 8, 8, 8},
+ {8, 8, 8, 8, 8, 8, 8, 8},
+ {8, 8, 8, 8, 8, 8, 8, 8},
+ {8, 8, 8, 8, 8, 8, 8, 8},
+ {0, 0, 0, 0, 0, 0, 0, 0},
+ {0, 0, 0, 0, 0, 0, 0, 0},
+ {0, 0, 0, 0, 0, 0, 0, 0},
+ {0, 0, 0, 0, 0, 0, 0, 0},
+ {0, 0, 0, 0, 0, 0, 0, 0},
+ {0, 0, 0, 0, 0, 0, 0, 0},
+ {0, 0, 0, 4, 0, 0, 0, 0},
+ {0, 0, 0, 0, 0, 0, 0, 0},
+}};
+
+struct stn_cc cc_table_gmac = {{
+
+ {8, 8, 8, 8, 16, 16, 16, 16},
+ {8, 8, 8, 8, 16, 16, 16, 16},
+ {8, 8, 8, 8, 16, 16, 16, 16},
+ {8, 8, 8, 8, 16, 16, 16, 16},
+ {8, 8, 8, 8, 16, 16, 16, 16},
+ {8, 8, 8, 8, 16, 16, 16, 16},
+ {8, 8, 8, 8, 16, 16, 16, 16},
+ {8, 8, 8, 8, 16, 16, 16, 16},
+ {0, 0, 0, 0, 0, 0, 0, 0},
+ {0, 0, 0, 0, 0, 0, 0, 0},
+ {0, 0, 0, 0, 0, 0, 0, 0},
+ {0, 0, 0, 0, 0, 0, 0, 0},
+ {0, 4, 0, 0, 0, 0, 0, 4},
+ {0, 0, 0, 0, 0, 0, 0, 0},
+ {0, 0, 0, 0, 0, 0, 0, 0},
+ {0, 0, 0, 0, 0, 0, 0, 0},
+}};
+
+struct stn_cc cc_table_dma = {{
+
+ {0, 0, 0, 0, 0, 0, 0, 0},
+ {0, 0, 0, 0, 0, 0, 0, 0},
+ {0, 0, 0, 0, 0, 0, 0, 0},
+ {0, 0, 0, 0, 0, 0, 0, 0},
+ {0, 0, 0, 0, 0, 0, 0, 0},
+ {0, 0, 0, 0, 0, 0, 0, 0},
+ {0, 0, 0, 0, 0, 0, 0, 0},
+ {0, 0, 0, 0, 0, 0, 0, 0},
+ {0, 0, 0, 0, 0, 0, 0, 0},
+ {0, 0, 0, 0, 0, 0, 0, 0},
+ {0, 0, 0, 0, 0, 0, 0, 0},
+ {0, 0, 0, 0, 0, 0, 0, 0},
+ {0, 0, 0, 0, 0, 0, 0, 0},
+ {0, 0, 0, 0, 0, 0, 0, 0},
+ {0, 0, 0, 0, 0, 0, 0, 0},
+ {0, 0, 0, 0, 0, 0, 0, 0},
+}};
+
+struct stn_cc cc_table_sec = {{
+
+ {8, 8, 8, 8, 0, 0, 0, 0},
+ {8, 8, 8, 4, 0, 0, 0, 0},
+ {8, 8, 8, 8, 0, 0, 0, 0},
+ {8, 8, 8, 8, 0, 0, 0, 0},
+ {8, 8, 8, 8, 0, 0, 0, 0},
+ {8, 8, 8, 8, 0, 0, 0, 0},
+ {8, 8, 8, 8, 0, 0, 0, 0},
+ {8, 8, 8, 8, 0, 0, 0, 0},
+ {0, 0, 0, 0, 0, 0, 0, 0},
+ {0, 0, 0, 0, 0, 0, 0, 0},
+ {0, 0, 0, 0, 0, 0, 0, 0},
+ {0, 0, 0, 0, 0, 0, 0, 0},
+ {0, 0, 0, 0, 0, 0, 0, 0},
+ {0, 0, 0, 0, 0, 0, 0, 0},
+ {0, 0, 0, 0, 0, 0, 0, 0},
+ {0, 0, 0, 0, 0, 0, 0, 0},
+}};
Property changes on: trunk/sys/mips/rmi/msgring.c
___________________________________________________________________
Added: svn:eol-style
## -0,0 +1 ##
+native
\ No newline at end of property
Added: svn:keywords
## -0,0 +1 ##
+MidnightBSD=%H
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+text/plain
\ No newline at end of property
Added: trunk/sys/mips/rmi/msgring.cfg
===================================================================
--- trunk/sys/mips/rmi/msgring.cfg (rev 0)
+++ trunk/sys/mips/rmi/msgring.cfg 2018-05-26 21:55:02 UTC (rev 9987)
@@ -0,0 +1,1182 @@
+/*-
+ * Copyright (c) 2003-2009 RMI Corporation
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * 3. Neither the name of RMI Corporation, nor the names of its contributors,
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ * RMI_BSD */
+/*
+ * This file defines the message ring configuration for phoenix-8. It tries to allow
+ * many different point-point communications between the message stations on the message ring
+ * and as result is _not_ the best configuration for performance
+ *
+ * The message ring on phoenix family of processors connects the cpus, gmacs, xgmac/spi4,
+ * security engine and the general purpose DMA engines. It provides a high bandwidth,
+ * low latency communication links. On traditional processors, this communication goes through
+ * which inherently does not scale very well with increasing number of cpus.
+ *
+ * Message ring has an in-built flow control mechanism. Every agent/station on the ring has to
+ * have software configured credits to send messages to any agent. Every receiving agent on the
+ * ring has a 256 entry FIFO that can divided into "buckets". All addressing on the ring is
+ * in terms of buckets. There are a total 128 buckets on the ring. The total number of credits
+ * across all sending agents should not exceed the bucket size.
+ *
+ * Below are the receiving agents and the max number of buckets they can have
+ * CPU 0 : 8 buckets
+ * CPU 1 : 8 buckets
+ * CPU 2 : 8 buckets
+ * CPU 3 : 8 buckets
+ * CPU 4 : 8 buckets
+ * CPU 5 : 8 buckets
+ * CPU 6 : 8 buckets
+ * CPU 7 : 8 buckets
+ *
+ * XGMAC 0 / SPI4 0
+ * TX : 16 buckets
+ * FREE : 2 buckets
+ * XGMAC 1 / SPI4 1
+ * TX : 16 buckets
+ * FREE : 2 buckets
+ *
+ * GMAC : 8 buckets
+ *
+ * SEC : 8 buckets
+ *
+ * DMA : 8 buckets
+ *
+ * The bucket size of a bucket should be aligned to the bucket's starting index in that
+ * receiving station's FIFO. For example, if sizes of bucket0 and bucket1 of a station
+ * are 32 and 32, bucket2's size has to be 64. bucket size 0 is valid.
+ *
+ * The format of the file is pretty straight forward. Each bucket definition has the size
+ * and the list of sending agents to that bucket with the number of credits to send.
+ *
+ * Undefined buckets have a size of 0 and Tx stations have 0 credits to send to that bucket.
+ *
+ * Following are the currently supported bucket names
+ * cpu_0_0
+ * cpu_0_1
+ * cpu_0_2
+ * cpu_0_3
+ * cpu_0_4
+ * cpu_0_5
+ * cpu_0_6
+ * cpu_0_7
+ *
+ * cpu_1_0
+ * cpu_1_1
+ * cpu_1_2
+ * cpu_1_3
+ * cpu_1_4
+ * cpu_1_5
+ * cpu_1_6
+ * cpu_1_7
+ *
+ * cpu_2_0
+ * cpu_2_1
+ * cpu_2_2
+ * cpu_2_3
+ * cpu_2_4
+ * cpu_2_5
+ * cpu_2_6
+ * cpu_2_7
+ *
+ * cpu_3_0
+ * cpu_3_1
+ * cpu_3_2
+ * cpu_3_3
+ * cpu_3_4
+ * cpu_3_5
+ * cpu_3_6
+ * cpu_3_7
+ *
+ * cpu_4_0
+ * cpu_4_1
+ * cpu_4_2
+ * cpu_4_3
+ * cpu_4_4
+ * cpu_4_5
+ * cpu_4_6
+ * cpu_4_7
+ *
+ * cpu_5_0
+ * cpu_5_1
+ * cpu_5_2
+ * cpu_5_3
+ * cpu_5_4
+ * cpu_5_5
+ * cpu_5_6
+ * cpu_5_7
+ *
+ * cpu_6_0
+ * cpu_6_1
+ * cpu_6_2
+ * cpu_6_3
+ * cpu_6_4
+ * cpu_6_5
+ * cpu_6_6
+ * cpu_6_7
+ *
+ * cpu_7_0
+ * cpu_7_1
+ * cpu_7_2
+ * cpu_7_3
+ * cpu_7_4
+ * cpu_7_5
+ * cpu_7_6
+ * cpu_7_7
+ *
+ * xgs_0_tx_0
+ * xgs_0_tx_1
+ * xgs_0_tx_2
+ * xgs_0_tx_3
+ * xgs_0_tx_4
+ * xgs_0_tx_5
+ * xgs_0_tx_6
+ * xgs_0_tx_7
+ * xgs_0_tx_8
+ * xgs_0_tx_9
+ * xgs_0_tx_10
+ * xgs_0_tx_11
+ * xgs_0_tx_12
+ * xgs_0_tx_13
+ * xgs_0_tx_14
+ * xgs_0_tx_15
+ *
+ * xgs_1_tx_0
+ * xgs_1_tx_1
+ * xgs_1_tx_2
+ * xgs_1_tx_3
+ * xgs_1_tx_4
+ * xgs_1_tx_5
+ * xgs_1_tx_6
+ * xgs_1_tx_7
+ * xgs_1_tx_8
+ * xgs_1_tx_9
+ * xgs_1_tx_10
+ * xgs_1_tx_11
+ * xgs_1_tx_12
+ * xgs_1_tx_13
+ * xgs_1_tx_14
+ * xgs_1_tx_15
+ *
+ * gmac_rsvd_0
+ * gmac_rfr_0
+ * gmac_tx_0
+ * gmac_tx_1
+ * gmac_tx_2
+ * gmac_tx_3
+ * gmac_rsvd_1
+ * gmac_rfr_1
+ *
+ * xgs_0_rsvd
+ * xgs_0_rfr
+ *
+ * xgs_1_rsvd
+ * xgs_1_rfr
+ *
+ * sec_pipe_0
+ * sec_pipe_1
+ * sec_pipe_2
+ * sec_pipe_3
+ * sec_rsa
+ *
+ * Following are the currently supported Tx Agent/Station names
+ *
+ * tx_stn_cpu_0
+ * tx_stn_cpu_1
+ * tx_stn_cpu_2
+ * tx_stn_cpu_3
+ * tx_stn_cpu_4
+ * tx_stn_cpu_5
+ * tx_stn_cpu_6
+ * tx_stn_cpu_7
+ *
+ * tx_stn_xgs_0
+ * tx_stn_xgs_1
+ *
+ * tx_stn_gmac
+ *
+ * tx_stn_dma
+ *
+ * tx_stn_sec
+ *
+ *
+ *
+ */
+
+/*************************************************************/
+// CPU_0 Message Station
+
+bucket "cpu_0_0" {
+ size 32;
+ "tx_stn_xgs_0" 8;
+ "tx_stn_xgs_1" 8;
+ "tx_stn_gmac" 8;
+ "tx_stn_sec" 8;
+}
+bucket "cpu_0_1" {
+ size 32;
+ "tx_stn_xgs_0" 8;
+ "tx_stn_xgs_1" 8;
+ "tx_stn_gmac" 8;
+ "tx_stn_sec" 8;
+}
+bucket "cpu_0_2" {
+ size 32;
+ "tx_stn_xgs_0" 8;
+ "tx_stn_xgs_1" 8;
+ "tx_stn_gmac" 8;
+ "tx_stn_sec" 8;
+}
+bucket "cpu_0_3" {
+ size 32;
+ "tx_stn_xgs_0" 8;
+ "tx_stn_xgs_1" 8;
+ "tx_stn_gmac" 8;
+ "tx_stn_sec" 8;
+}
+bucket "cpu_0_4" {
+ size 32;
+ "tx_stn_gmac" 16;
+ "tx_stn_xgs_0" 8;
+ "tx_stn_xgs_1" 8;
+}
+bucket "cpu_0_5" {
+ size 32;
+ "tx_stn_gmac" 16;
+ "tx_stn_xgs_0" 8;
+ "tx_stn_xgs_1" 8;
+}
+bucket "cpu_0_6" {
+ size 32;
+ "tx_stn_gmac" 16;
+ "tx_stn_xgs_0" 8;
+ "tx_stn_xgs_1" 8;
+}
+bucket "cpu_0_7" {
+ size 32;
+ "tx_stn_gmac" 16;
+ "tx_stn_xgs_0" 8;
+ "tx_stn_xgs_1" 8;
+}
+
+/*************************************************************/
+// CPU_1 Message Station
+
+bucket "cpu_1_0" {
+ size 32;
+ "tx_stn_xgs_0" 8;
+ "tx_stn_xgs_1" 8;
+ "tx_stn_gmac" 8;
+ "tx_stn_sec" 8;
+}
+bucket "cpu_1_1" {
+ size 32;
+ "tx_stn_xgs_0" 8;
+ "tx_stn_xgs_1" 8;
+ "tx_stn_gmac" 8;
+ "tx_stn_sec" 8;
+}
+bucket "cpu_1_2" {
+ size 32;
+ "tx_stn_xgs_0" 8;
+ "tx_stn_xgs_1" 8;
+ "tx_stn_gmac" 8;
+ "tx_stn_sec" 8;
+}
+bucket "cpu_1_3" {
+ size 32;
+ "tx_stn_xgs_0" 8;
+ "tx_stn_xgs_1" 8;
+ "tx_stn_gmac" 8;
+ "tx_stn_sec" 4;
+ "tx_stn_cpu_0" 4; /* NEEDED BY RMIOS IPSEC */
+}
+bucket "cpu_1_4" {
+ size 32;
+ "tx_stn_gmac" 16;
+ "tx_stn_xgs_0" 8;
+ "tx_stn_xgs_1" 8;
+}
+bucket "cpu_1_5" {
+ size 32;
+ "tx_stn_gmac" 16;
+ "tx_stn_xgs_0" 8;
+ "tx_stn_xgs_1" 8;
+}
+bucket "cpu_1_6" {
+ size 32;
+ "tx_stn_gmac" 16;
+ "tx_stn_xgs_0" 8;
+ "tx_stn_xgs_1" 8;
+}
+bucket "cpu_1_7" {
+ size 32;
+ "tx_stn_gmac" 16;
+ "tx_stn_xgs_0" 8;
+ "tx_stn_xgs_1" 8;
+}
+
+/*************************************************************/
+// CPU_2 Message Station
+
+bucket "cpu_2_0" {
+ size 32;
+ "tx_stn_xgs_0" 8;
+ "tx_stn_xgs_1" 8;
+ "tx_stn_gmac" 8;
+ "tx_stn_sec" 8;
+}
+bucket "cpu_2_1" {
+ size 32;
+ "tx_stn_xgs_0" 8;
+ "tx_stn_xgs_1" 8;
+ "tx_stn_gmac" 8;
+ "tx_stn_sec" 8;
+}
+bucket "cpu_2_2" {
+ size 32;
+ "tx_stn_xgs_0" 8;
+ "tx_stn_xgs_1" 8;
+ "tx_stn_gmac" 8;
+ "tx_stn_sec" 8;
+}
+bucket "cpu_2_3" {
+ size 32;
+ "tx_stn_xgs_0" 8;
+ "tx_stn_xgs_1" 8;
+ "tx_stn_gmac" 8;
+ "tx_stn_sec" 8;
+}
+bucket "cpu_2_4" {
+ size 32;
+ "tx_stn_gmac" 16;
+ "tx_stn_xgs_0" 8;
+ "tx_stn_xgs_1" 8;
+}
+bucket "cpu_2_5" {
+ size 32;
+ "tx_stn_gmac" 16;
+ "tx_stn_xgs_0" 8;
+ "tx_stn_xgs_1" 8;
+}
+bucket "cpu_2_6" {
+ size 32;
+ "tx_stn_gmac" 16;
+ "tx_stn_xgs_0" 8;
+ "tx_stn_xgs_1" 8;
+}
+bucket "cpu_2_7" {
+ size 32;
+ "tx_stn_gmac" 16;
+ "tx_stn_xgs_0" 8;
+ "tx_stn_xgs_1" 8;
+}
+
+/*************************************************************/
+// CPU_3 Message Station
+
+bucket "cpu_3_0" {
+ size 32;
+ "tx_stn_xgs_0" 8;
+ "tx_stn_xgs_1" 8;
+ "tx_stn_gmac" 8;
+ "tx_stn_sec" 8;
+}
+bucket "cpu_3_1" {
+ size 32;
+ "tx_stn_xgs_0" 8;
+ "tx_stn_xgs_1" 8;
+ "tx_stn_gmac" 8;
+ "tx_stn_sec" 8;
+}
+bucket "cpu_3_2" {
+ size 32;
+ "tx_stn_xgs_0" 8;
+ "tx_stn_xgs_1" 8;
+ "tx_stn_gmac" 8;
+ "tx_stn_sec" 8;
+}
+bucket "cpu_3_3" {
+ size 32;
+ "tx_stn_xgs_0" 8;
+ "tx_stn_xgs_1" 8;
+ "tx_stn_gmac" 8;
+ "tx_stn_sec" 8;
+}
+bucket "cpu_3_4" {
+ size 32;
+ "tx_stn_gmac" 16;
+ "tx_stn_xgs_0" 8;
+ "tx_stn_xgs_1" 8;
+}
+bucket "cpu_3_5" {
+ size 32;
+ "tx_stn_gmac" 16;
+ "tx_stn_xgs_0" 8;
+ "tx_stn_xgs_1" 8;
+}
+bucket "cpu_3_6" {
+ size 32;
+ "tx_stn_gmac" 16;
+ "tx_stn_xgs_0" 8;
+ "tx_stn_xgs_1" 8;
+}
+bucket "cpu_3_7" {
+ size 32;
+ "tx_stn_gmac" 16;
+ "tx_stn_xgs_0" 8;
+ "tx_stn_xgs_1" 8;
+}
+
+/*************************************************************/
+// CPU_4 Message Station
+
+bucket "cpu_4_0" {
+ size 32;
+ "tx_stn_xgs_0" 8;
+ "tx_stn_xgs_1" 8;
+ "tx_stn_gmac" 8;
+ "tx_stn_sec" 8;
+}
+bucket "cpu_4_1" {
+ size 32;
+ "tx_stn_xgs_0" 8;
+ "tx_stn_xgs_1" 8;
+ "tx_stn_gmac" 8;
+ "tx_stn_sec" 8;
+}
+bucket "cpu_4_2" {
+ size 32;
+ "tx_stn_xgs_0" 8;
+ "tx_stn_xgs_1" 8;
+ "tx_stn_gmac" 8;
+ "tx_stn_sec" 8;
+}
+bucket "cpu_4_3" {
+ size 32;
+ "tx_stn_xgs_0" 8;
+ "tx_stn_xgs_1" 8;
+ "tx_stn_gmac" 8;
+ "tx_stn_sec" 8;
+}
+bucket "cpu_4_4" {
+ size 32;
+ "tx_stn_gmac" 16;
+ "tx_stn_xgs_0" 8;
+ "tx_stn_xgs_1" 8;
+}
+bucket "cpu_4_5" {
+ size 32;
+ "tx_stn_gmac" 16;
+ "tx_stn_xgs_0" 8;
+ "tx_stn_xgs_1" 8;
+}
+bucket "cpu_4_6" {
+ size 32;
+ "tx_stn_gmac" 16;
+ "tx_stn_xgs_0" 8;
+ "tx_stn_xgs_1" 8;
+}
+bucket "cpu_4_7" {
+ size 32;
+ "tx_stn_gmac" 16;
+ "tx_stn_xgs_0" 8;
+ "tx_stn_xgs_1" 8;
+}
+
+/*************************************************************/
+// CPU_5 Message Station
+
+bucket "cpu_5_0" {
+ size 32;
+ "tx_stn_xgs_0" 8;
+ "tx_stn_xgs_1" 8;
+ "tx_stn_gmac" 8;
+ "tx_stn_sec" 8;
+}
+bucket "cpu_5_1" {
+ size 32;
+ "tx_stn_xgs_0" 8;
+ "tx_stn_xgs_1" 8;
+ "tx_stn_gmac" 8;
+ "tx_stn_sec" 8;
+}
+bucket "cpu_5_2" {
+ size 32;
+ "tx_stn_xgs_0" 8;
+ "tx_stn_xgs_1" 8;
+ "tx_stn_gmac" 8;
+ "tx_stn_sec" 8;
+}
+bucket "cpu_5_3" {
+ size 32;
+ "tx_stn_xgs_0" 8;
+ "tx_stn_xgs_1" 8;
+ "tx_stn_gmac" 8;
+ "tx_stn_sec" 8;
+}
+bucket "cpu_5_4" {
+ size 32;
+ "tx_stn_gmac" 16;
+ "tx_stn_xgs_0" 8;
+ "tx_stn_xgs_1" 8;
+}
+bucket "cpu_5_5" {
+ size 32;
+ "tx_stn_gmac" 16;
+ "tx_stn_xgs_0" 8;
+ "tx_stn_xgs_1" 8;
+}
+bucket "cpu_5_6" {
+ size 32;
+ "tx_stn_gmac" 16;
+ "tx_stn_xgs_0" 8;
+ "tx_stn_xgs_1" 8;
+}
+bucket "cpu_5_7" {
+ size 32;
+ "tx_stn_gmac" 16;
+ "tx_stn_xgs_0" 8;
+ "tx_stn_xgs_1" 8;
+}
+
+
+/*************************************************************/
+// CPU_6 Message Station
+
+bucket "cpu_6_0" {
+ size 32;
+ "tx_stn_xgs_0" 8;
+ "tx_stn_xgs_1" 8;
+ "tx_stn_gmac" 8;
+ "tx_stn_sec" 8;
+}
+bucket "cpu_6_1" {
+ size 32;
+ "tx_stn_xgs_0" 8;
+ "tx_stn_xgs_1" 8;
+ "tx_stn_gmac" 8;
+ "tx_stn_sec" 8;
+}
+bucket "cpu_6_2" {
+ size 32;
+ "tx_stn_xgs_0" 8;
+ "tx_stn_xgs_1" 8;
+ "tx_stn_gmac" 8;
+ "tx_stn_sec" 8;
+}
+bucket "cpu_6_3" {
+ size 32;
+ "tx_stn_xgs_0" 8;
+ "tx_stn_xgs_1" 8;
+ "tx_stn_gmac" 8;
+ "tx_stn_sec" 8;
+}
+bucket "cpu_6_4" {
+ size 32;
+ "tx_stn_gmac" 16;
+ "tx_stn_xgs_0" 8;
+ "tx_stn_xgs_1" 8;
+}
+bucket "cpu_6_5" {
+ size 32;
+ "tx_stn_gmac" 16;
+ "tx_stn_xgs_0" 8;
+ "tx_stn_xgs_1" 8;
+}
+bucket "cpu_6_6" {
+ size 32;
+ "tx_stn_gmac" 16;
+ "tx_stn_xgs_0" 8;
+ "tx_stn_xgs_1" 8;
+}
+bucket "cpu_6_7" {
+ size 32;
+ "tx_stn_gmac" 16;
+ "tx_stn_xgs_0" 8;
+ "tx_stn_xgs_1" 8;
+}
+
+
+/*************************************************************/
+// CPU_7 Message Station
+
+bucket "cpu_7_0" {
+ size 32;
+ "tx_stn_xgs_0" 8;
+ "tx_stn_xgs_1" 8;
+ "tx_stn_gmac" 8;
+ "tx_stn_sec" 8;
+}
+bucket "cpu_7_1" {
+ size 32;
+ "tx_stn_xgs_0" 8;
+ "tx_stn_xgs_1" 8;
+ "tx_stn_gmac" 8;
+ "tx_stn_sec" 8;
+}
+bucket "cpu_7_2" {
+ size 32;
+ "tx_stn_xgs_0" 8;
+ "tx_stn_xgs_1" 8;
+ "tx_stn_gmac" 8;
+ "tx_stn_sec" 8;
+}
+bucket "cpu_7_3" {
+ size 32;
+ "tx_stn_xgs_0" 8;
+ "tx_stn_xgs_1" 8;
+ "tx_stn_gmac" 8;
+ "tx_stn_sec" 8;
+}
+bucket "cpu_7_4" {
+ size 32;
+ "tx_stn_gmac" 16;
+ "tx_stn_xgs_0" 8;
+ "tx_stn_xgs_1" 8;
+}
+bucket "cpu_7_5" {
+ size 32;
+ "tx_stn_gmac" 16;
+ "tx_stn_xgs_0" 8;
+ "tx_stn_xgs_1" 8;
+}
+bucket "cpu_7_6" {
+ size 32;
+ "tx_stn_gmac" 16;
+ "tx_stn_xgs_0" 8;
+ "tx_stn_xgs_1" 8;
+}
+bucket "cpu_7_7" {
+ size 32;
+ "tx_stn_gmac" 16;
+ "tx_stn_xgs_0" 8;
+ "tx_stn_xgs_1" 8;
+}
+
+
+/*************************************************************/
+// GMAC Message Station
+
+bucket "gmac_rfr_0" {
+ size 32;
+ "tx_stn_cpu_0" 2;
+ "tx_stn_cpu_1" 2;
+ "tx_stn_cpu_2" 4;
+ "tx_stn_cpu_3" 4;
+ "tx_stn_cpu_4" 4;
+ "tx_stn_cpu_5" 4;
+ "tx_stn_cpu_6" 4;
+ "tx_stn_cpu_7" 4;
+ "tx_stn_gmac" 4;
+}
+
+bucket "gmac_tx_0" {
+ size 32;
+ "tx_stn_cpu_0" 4;
+ "tx_stn_cpu_1" 4;
+ "tx_stn_cpu_2" 4;
+ "tx_stn_cpu_3" 4;
+ "tx_stn_cpu_4" 4;
+ "tx_stn_cpu_5" 4;
+ "tx_stn_cpu_6" 4;
+ "tx_stn_cpu_7" 4;
+}
+
+bucket "gmac_tx_1" {
+ size 32;
+ "tx_stn_cpu_0" 4;
+ "tx_stn_cpu_1" 4;
+ "tx_stn_cpu_2" 4;
+ "tx_stn_cpu_3" 4;
+ "tx_stn_cpu_4" 4;
+ "tx_stn_cpu_5" 4;
+ "tx_stn_cpu_6" 4;
+ "tx_stn_cpu_7" 4;
+}
+
+bucket "gmac_tx_2" {
+ size 32;
+ "tx_stn_cpu_0" 4;
+ "tx_stn_cpu_1" 4;
+ "tx_stn_cpu_2" 4;
+ "tx_stn_cpu_3" 4;
+ "tx_stn_cpu_4" 4;
+ "tx_stn_cpu_5" 4;
+ "tx_stn_cpu_6" 4;
+ "tx_stn_cpu_7" 4;
+}
+
+bucket "gmac_tx_3" {
+ size 32;
+ "tx_stn_cpu_0" 4;
+ "tx_stn_cpu_1" 4;
+ "tx_stn_cpu_2" 4;
+ "tx_stn_cpu_3" 4;
+ "tx_stn_cpu_4" 4;
+ "tx_stn_cpu_5" 4;
+ "tx_stn_cpu_6" 4;
+ "tx_stn_cpu_7" 4;
+}
+
+bucket "gmac_rfr_1" {
+ size 32;
+ "tx_stn_cpu_0" 2;
+ "tx_stn_cpu_1" 2;
+ "tx_stn_cpu_2" 4;
+ "tx_stn_cpu_3" 4;
+ "tx_stn_cpu_4" 4;
+ "tx_stn_cpu_5" 4;
+ "tx_stn_cpu_6" 4;
+ "tx_stn_cpu_7" 4;
+ "tx_stn_gmac" 4;
+}
+/*********************************************/
+// xgmac
+bucket "xgs_0_rfr" {
+ size 32;
+ "tx_stn_cpu_0" 2;
+ "tx_stn_cpu_1" 2;
+ "tx_stn_cpu_2" 4;
+ "tx_stn_cpu_3" 4;
+ "tx_stn_cpu_4" 4;
+ "tx_stn_cpu_5" 4;
+ "tx_stn_cpu_6" 4;
+ "tx_stn_cpu_7" 4;
+ "tx_stn_xgs_0" 4;
+}
+
+bucket "xgs_0_tx_0" {
+ size 32;
+ "tx_stn_cpu_0" 4;
+ "tx_stn_cpu_1" 4;
+ "tx_stn_cpu_2" 4;
+ "tx_stn_cpu_3" 4;
+ "tx_stn_cpu_4" 4;
+ "tx_stn_cpu_5" 4;
+ "tx_stn_cpu_6" 4;
+ "tx_stn_cpu_7" 4;
+}
+
+bucket "xgs_0_tx_1" {
+ size 16;
+ "tx_stn_cpu_0" 2;
+ "tx_stn_cpu_1" 2;
+ "tx_stn_cpu_2" 2;
+ "tx_stn_cpu_3" 2;
+ "tx_stn_cpu_4" 2;
+ "tx_stn_cpu_5" 2;
+ "tx_stn_cpu_6" 2;
+ "tx_stn_cpu_7" 2;
+}
+
+bucket "xgs_0_tx_2" {
+ size 16;
+ "tx_stn_cpu_0" 2;
+ "tx_stn_cpu_1" 2;
+ "tx_stn_cpu_2" 2;
+ "tx_stn_cpu_3" 2;
+ "tx_stn_cpu_4" 2;
+ "tx_stn_cpu_5" 2;
+ "tx_stn_cpu_6" 2;
+ "tx_stn_cpu_7" 2;
+}
+
+bucket "xgs_0_tx_3" {
+ size 16;
+ "tx_stn_cpu_0" 2;
+ "tx_stn_cpu_1" 2;
+ "tx_stn_cpu_2" 2;
+ "tx_stn_cpu_3" 2;
+ "tx_stn_cpu_4" 2;
+ "tx_stn_cpu_5" 2;
+ "tx_stn_cpu_6" 2;
+ "tx_stn_cpu_7" 2;
+}
+
+bucket "xgs_0_tx_4" {
+ size 16;
+ "tx_stn_cpu_0" 2;
+ "tx_stn_cpu_1" 2;
+ "tx_stn_cpu_2" 2;
+ "tx_stn_cpu_3" 2;
+ "tx_stn_cpu_4" 2;
+ "tx_stn_cpu_5" 2;
+ "tx_stn_cpu_6" 2;
+ "tx_stn_cpu_7" 2;
+}
+bucket "xgs_0_tx_5" {
+ size 16;
+ "tx_stn_cpu_0" 2;
+ "tx_stn_cpu_1" 2;
+ "tx_stn_cpu_2" 2;
+ "tx_stn_cpu_3" 2;
+ "tx_stn_cpu_4" 2;
+ "tx_stn_cpu_5" 2;
+ "tx_stn_cpu_6" 2;
+ "tx_stn_cpu_7" 2;
+}
+
+bucket "xgs_0_tx_6" {
+ size 16;
+ "tx_stn_cpu_0" 2;
+ "tx_stn_cpu_1" 2;
+ "tx_stn_cpu_2" 2;
+ "tx_stn_cpu_3" 2;
+ "tx_stn_cpu_4" 2;
+ "tx_stn_cpu_5" 2;
+ "tx_stn_cpu_6" 2;
+ "tx_stn_cpu_7" 2;
+}
+
+bucket "xgs_0_tx_7" {
+ size 16;
+ "tx_stn_cpu_0" 2;
+ "tx_stn_cpu_1" 2;
+ "tx_stn_cpu_2" 2;
+ "tx_stn_cpu_3" 2;
+ "tx_stn_cpu_4" 2;
+ "tx_stn_cpu_5" 2;
+ "tx_stn_cpu_6" 2;
+ "tx_stn_cpu_7" 2;
+}
+
+bucket "xgs_0_tx_8" {
+ size 16;
+ "tx_stn_cpu_0" 2;
+ "tx_stn_cpu_1" 2;
+ "tx_stn_cpu_2" 2;
+ "tx_stn_cpu_3" 2;
+ "tx_stn_cpu_4" 2;
+ "tx_stn_cpu_5" 2;
+ "tx_stn_cpu_6" 2;
+ "tx_stn_cpu_7" 2;
+}
+
+bucket "xgs_0_tx_9" {
+ size 16;
+ "tx_stn_cpu_0" 2;
+ "tx_stn_cpu_1" 2;
+ "tx_stn_cpu_2" 2;
+ "tx_stn_cpu_3" 2;
+ "tx_stn_cpu_4" 2;
+ "tx_stn_cpu_5" 2;
+ "tx_stn_cpu_6" 2;
+ "tx_stn_cpu_7" 2;
+}
+
+bucket "xgs_0_tx_10" {
+ size 16;
+ "tx_stn_cpu_0" 2;
+ "tx_stn_cpu_1" 2;
+ "tx_stn_cpu_2" 2;
+ "tx_stn_cpu_3" 2;
+ "tx_stn_cpu_4" 2;
+ "tx_stn_cpu_5" 2;
+ "tx_stn_cpu_6" 2;
+ "tx_stn_cpu_7" 2;
+}
+
+
+bucket "xgs_0_tx_11" {
+ size 16;
+ "tx_stn_cpu_0" 2;
+ "tx_stn_cpu_1" 2;
+ "tx_stn_cpu_2" 2;
+ "tx_stn_cpu_3" 2;
+ "tx_stn_cpu_4" 2;
+ "tx_stn_cpu_5" 2;
+ "tx_stn_cpu_6" 2;
+ "tx_stn_cpu_7" 2;
+}
+
+bucket "xgs_0_tx_12" {
+ size 16;
+ "tx_stn_cpu_0" 2;
+ "tx_stn_cpu_1" 2;
+ "tx_stn_cpu_2" 2;
+ "tx_stn_cpu_3" 2;
+ "tx_stn_cpu_4" 2;
+ "tx_stn_cpu_5" 2;
+ "tx_stn_cpu_6" 2;
+ "tx_stn_cpu_7" 2;
+}
+
+bucket "xgs_0_tx_13" {
+ size 16;
+ "tx_stn_cpu_0" 2;
+ "tx_stn_cpu_1" 2;
+ "tx_stn_cpu_2" 2;
+ "tx_stn_cpu_3" 2;
+ "tx_stn_cpu_4" 2;
+ "tx_stn_cpu_5" 2;
+ "tx_stn_cpu_6" 2;
+ "tx_stn_cpu_7" 2;
+}
+
+bucket "xgs_0_tx_14" {
+ size 16;
+ "tx_stn_cpu_0" 2;
+ "tx_stn_cpu_1" 2;
+ "tx_stn_cpu_2" 2;
+ "tx_stn_cpu_3" 2;
+ "tx_stn_cpu_4" 2;
+ "tx_stn_cpu_5" 2;
+ "tx_stn_cpu_6" 2;
+ "tx_stn_cpu_7" 2;
+}
+
+
+bucket "xgs_1_rfr" {
+ size 32;
+ "tx_stn_cpu_0" 2;
+ "tx_stn_cpu_1" 2;
+ "tx_stn_cpu_2" 4;
+ "tx_stn_cpu_3" 4;
+ "tx_stn_cpu_4" 4;
+ "tx_stn_cpu_5" 4;
+ "tx_stn_cpu_6" 4;
+ "tx_stn_cpu_7" 4;
+ "tx_stn_xgs_1" 4;
+}
+
+bucket "xgs_1_tx_0" {
+ size 32;
+ "tx_stn_cpu_0" 4;
+ "tx_stn_cpu_1" 4;
+ "tx_stn_cpu_2" 4;
+ "tx_stn_cpu_3" 4;
+ "tx_stn_cpu_4" 4;
+ "tx_stn_cpu_5" 4;
+ "tx_stn_cpu_6" 4;
+ "tx_stn_cpu_7" 4;
+}
+
+
+bucket "xgs_1_tx_1" {
+ size 16;
+ "tx_stn_cpu_0" 2;
+ "tx_stn_cpu_1" 2;
+ "tx_stn_cpu_2" 2;
+ "tx_stn_cpu_3" 2;
+ "tx_stn_cpu_4" 2;
+ "tx_stn_cpu_5" 2;
+ "tx_stn_cpu_6" 2;
+ "tx_stn_cpu_7" 2;
+}
+
+bucket "xgs_1_tx_2" {
+ size 16;
+ "tx_stn_cpu_0" 2;
+ "tx_stn_cpu_1" 2;
+ "tx_stn_cpu_2" 2;
+ "tx_stn_cpu_3" 2;
+ "tx_stn_cpu_4" 2;
+ "tx_stn_cpu_5" 2;
+ "tx_stn_cpu_6" 2;
+ "tx_stn_cpu_7" 2;
+}
+
+bucket "xgs_1_tx_3" {
+ size 16;
+ "tx_stn_cpu_0" 2;
+ "tx_stn_cpu_1" 2;
+ "tx_stn_cpu_2" 2;
+ "tx_stn_cpu_3" 2;
+ "tx_stn_cpu_4" 2;
+ "tx_stn_cpu_5" 2;
+ "tx_stn_cpu_6" 2;
+ "tx_stn_cpu_7" 2;
+}
+
+bucket "xgs_1_tx_4" {
+ size 16;
+ "tx_stn_cpu_0" 2;
+ "tx_stn_cpu_1" 2;
+ "tx_stn_cpu_2" 2;
+ "tx_stn_cpu_3" 2;
+ "tx_stn_cpu_4" 2;
+ "tx_stn_cpu_5" 2;
+ "tx_stn_cpu_6" 2;
+ "tx_stn_cpu_7" 2;
+}
+
+bucket "xgs_1_tx_5" {
+ size 16;
+ "tx_stn_cpu_0" 2;
+ "tx_stn_cpu_1" 2;
+ "tx_stn_cpu_2" 2;
+ "tx_stn_cpu_3" 2;
+ "tx_stn_cpu_4" 2;
+ "tx_stn_cpu_5" 2;
+ "tx_stn_cpu_6" 2;
+ "tx_stn_cpu_7" 2;
+}
+
+bucket "xgs_1_tx_6" {
+ size 16;
+ "tx_stn_cpu_0" 2;
+ "tx_stn_cpu_1" 2;
+ "tx_stn_cpu_2" 2;
+ "tx_stn_cpu_3" 2;
+ "tx_stn_cpu_4" 2;
+ "tx_stn_cpu_5" 2;
+ "tx_stn_cpu_6" 2;
+ "tx_stn_cpu_7" 2;
+}
+
+bucket "xgs_1_tx_7" {
+ size 16;
+ "tx_stn_cpu_0" 2;
+ "tx_stn_cpu_1" 2;
+ "tx_stn_cpu_2" 2;
+ "tx_stn_cpu_3" 2;
+ "tx_stn_cpu_4" 2;
+ "tx_stn_cpu_5" 2;
+ "tx_stn_cpu_6" 2;
+ "tx_stn_cpu_7" 2;
+}
+
+
+bucket "xgs_1_tx_8" {
+ size 16;
+ "tx_stn_cpu_0" 2;
+ "tx_stn_cpu_1" 2;
+ "tx_stn_cpu_2" 2;
+ "tx_stn_cpu_3" 2;
+ "tx_stn_cpu_4" 2;
+ "tx_stn_cpu_5" 2;
+ "tx_stn_cpu_6" 2;
+ "tx_stn_cpu_7" 2;
+}
+
+
+bucket "xgs_1_tx_9" {
+ size 16;
+ "tx_stn_cpu_0" 2;
+ "tx_stn_cpu_1" 2;
+ "tx_stn_cpu_2" 2;
+ "tx_stn_cpu_3" 2;
+ "tx_stn_cpu_4" 2;
+ "tx_stn_cpu_5" 2;
+ "tx_stn_cpu_6" 2;
+ "tx_stn_cpu_7" 2;
+}
+
+
+bucket "xgs_1_tx_10" {
+ size 16;
+ "tx_stn_cpu_0" 2;
+ "tx_stn_cpu_1" 2;
+ "tx_stn_cpu_2" 2;
+ "tx_stn_cpu_3" 2;
+ "tx_stn_cpu_4" 2;
+ "tx_stn_cpu_5" 2;
+ "tx_stn_cpu_6" 2;
+ "tx_stn_cpu_7" 2;
+}
+
+bucket "xgs_1_tx_11" {
+ size 16;
+ "tx_stn_cpu_0" 2;
+ "tx_stn_cpu_1" 2;
+ "tx_stn_cpu_2" 2;
+ "tx_stn_cpu_3" 2;
+ "tx_stn_cpu_4" 2;
+ "tx_stn_cpu_5" 2;
+ "tx_stn_cpu_6" 2;
+ "tx_stn_cpu_7" 2;
+}
+
+bucket "xgs_1_tx_12" {
+ size 16;
+ "tx_stn_cpu_0" 2;
+ "tx_stn_cpu_1" 2;
+ "tx_stn_cpu_2" 2;
+ "tx_stn_cpu_3" 2;
+ "tx_stn_cpu_4" 2;
+ "tx_stn_cpu_5" 2;
+ "tx_stn_cpu_6" 2;
+ "tx_stn_cpu_7" 2;
+}
+
+bucket "xgs_1_tx_13" {
+ size 16;
+ "tx_stn_cpu_0" 2;
+ "tx_stn_cpu_1" 2;
+ "tx_stn_cpu_2" 2;
+ "tx_stn_cpu_3" 2;
+ "tx_stn_cpu_4" 2;
+ "tx_stn_cpu_5" 2;
+ "tx_stn_cpu_6" 2;
+ "tx_stn_cpu_7" 2;
+}
+
+bucket "xgs_1_tx_14" {
+ size 16;
+ "tx_stn_cpu_0" 2;
+ "tx_stn_cpu_1" 2;
+ "tx_stn_cpu_2" 2;
+ "tx_stn_cpu_3" 2;
+ "tx_stn_cpu_4" 2;
+ "tx_stn_cpu_5" 2;
+ "tx_stn_cpu_6" 2;
+ "tx_stn_cpu_7" 2;
+}
+
+
+
+
+
+
+/*************************************************************/
+// Security Message Station
+
+bucket "sec_pipe_0" {
+ size 128;
+ "tx_stn_cpu_0" 16;
+ "tx_stn_cpu_1" 16;
+ "tx_stn_cpu_2" 16;
+ "tx_stn_cpu_3" 16;
+ "tx_stn_cpu_4" 16;
+ "tx_stn_cpu_5" 16;
+ "tx_stn_cpu_6" 16;
+ "tx_stn_cpu_7" 16;
+}
+
+bucket "sec_rsa" {
+ size 128;
+ "tx_stn_cpu_0" 16;
+ "tx_stn_cpu_1" 16;
+ "tx_stn_cpu_2" 16;
+ "tx_stn_cpu_3" 16;
+ "tx_stn_cpu_4" 16;
+ "tx_stn_cpu_5" 16;
+ "tx_stn_cpu_6" 16;
+ "tx_stn_cpu_7" 16;
+}
+
Property changes on: trunk/sys/mips/rmi/msgring.cfg
___________________________________________________________________
Added: mnbsd:nokeywords
## -0,0 +1 ##
+MidnightBSD=%H
\ No newline at end of property
Added: trunk/sys/mips/rmi/msgring.h
===================================================================
--- trunk/sys/mips/rmi/msgring.h (rev 0)
+++ trunk/sys/mips/rmi/msgring.h 2018-05-26 21:55:02 UTC (rev 9987)
@@ -0,0 +1,371 @@
+/* $MidnightBSD$ */
+/*-
+ * Copyright (c) 2003-2009 RMI Corporation
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * 3. Neither the name of RMI Corporation, nor the names of its contributors,
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ * RMI_BSD
+ * $FreeBSD: stable/10/sys/mips/rmi/msgring.h 213377 2010-10-03 04:33:58Z jchandra $
+ */
+#ifndef _RMI_MSGRING_H_
+#define _RMI_MSGRING_H_
+
+#include <sys/param.h>
+#include <sys/systm.h>
+#include <sys/types.h>
+
+#include <machine/cpuregs.h>
+#include <machine/cpufunc.h>
+#include <mips/rmi/rmi_mips_exts.h>
+
+#define MSGRNG_TX_BUF_REG 0
+#define MSGRNG_RX_BUF_REG 1
+#define MSGRNG_MSG_STATUS_REG 2
+#define MSGRNG_MSG_CONFIG_REG 3
+#define MSGRNG_MSG_BUCKSIZE_REG 4
+
+#define MSGRNG_CC_0_REG 16
+#define MSGRNG_CC_1_REG 17
+#define MSGRNG_CC_2_REG 18
+#define MSGRNG_CC_3_REG 19
+#define MSGRNG_CC_4_REG 20
+#define MSGRNG_CC_5_REG 21
+#define MSGRNG_CC_6_REG 22
+#define MSGRNG_CC_7_REG 23
+#define MSGRNG_CC_8_REG 24
+#define MSGRNG_CC_9_REG 25
+#define MSGRNG_CC_10_REG 26
+#define MSGRNG_CC_11_REG 27
+#define MSGRNG_CC_12_REG 28
+#define MSGRNG_CC_13_REG 29
+#define MSGRNG_CC_14_REG 30
+#define MSGRNG_CC_15_REG 31
+
+/* Station IDs */
+#define MSGRNG_STNID_CPU0 0x00
+#define MSGRNG_STNID_CPU1 0x08
+#define MSGRNG_STNID_CPU2 0x10
+#define MSGRNG_STNID_CPU3 0x18
+#define MSGRNG_STNID_CPU4 0x20
+#define MSGRNG_STNID_CPU5 0x28
+#define MSGRNG_STNID_CPU6 0x30
+#define MSGRNG_STNID_CPU7 0x38
+#define MSGRNG_STNID_XGS0_TX 64
+#define MSGRNG_STNID_XMAC0_00_TX 64
+#define MSGRNG_STNID_XMAC0_01_TX 65
+#define MSGRNG_STNID_XMAC0_02_TX 66
+#define MSGRNG_STNID_XMAC0_03_TX 67
+#define MSGRNG_STNID_XMAC0_04_TX 68
+#define MSGRNG_STNID_XMAC0_05_TX 69
+#define MSGRNG_STNID_XMAC0_06_TX 70
+#define MSGRNG_STNID_XMAC0_07_TX 71
+#define MSGRNG_STNID_XMAC0_08_TX 72
+#define MSGRNG_STNID_XMAC0_09_TX 73
+#define MSGRNG_STNID_XMAC0_10_TX 74
+#define MSGRNG_STNID_XMAC0_11_TX 75
+#define MSGRNG_STNID_XMAC0_12_TX 76
+#define MSGRNG_STNID_XMAC0_13_TX 77
+#define MSGRNG_STNID_XMAC0_14_TX 78
+#define MSGRNG_STNID_XMAC0_15_TX 79
+
+#define MSGRNG_STNID_XGS1_TX 80
+#define MSGRNG_STNID_XMAC1_00_TX 80
+#define MSGRNG_STNID_XMAC1_01_TX 81
+#define MSGRNG_STNID_XMAC1_02_TX 82
+#define MSGRNG_STNID_XMAC1_03_TX 83
+#define MSGRNG_STNID_XMAC1_04_TX 84
+#define MSGRNG_STNID_XMAC1_05_TX 85
+#define MSGRNG_STNID_XMAC1_06_TX 86
+#define MSGRNG_STNID_XMAC1_07_TX 87
+#define MSGRNG_STNID_XMAC1_08_TX 88
+#define MSGRNG_STNID_XMAC1_09_TX 89
+#define MSGRNG_STNID_XMAC1_10_TX 90
+#define MSGRNG_STNID_XMAC1_11_TX 91
+#define MSGRNG_STNID_XMAC1_12_TX 92
+#define MSGRNG_STNID_XMAC1_13_TX 93
+#define MSGRNG_STNID_XMAC1_14_TX 94
+#define MSGRNG_STNID_XMAC1_15_TX 95
+
+#define MSGRNG_STNID_GMAC 96
+#define MSGRNG_STNID_GMACJFR_0 96
+#define MSGRNG_STNID_GMACRFR_0 97
+#define MSGRNG_STNID_GMACTX0 98
+#define MSGRNG_STNID_GMACTX1 99
+#define MSGRNG_STNID_GMACTX2 100
+#define MSGRNG_STNID_GMACTX3 101
+#define MSGRNG_STNID_GMACJFR_1 102
+#define MSGRNG_STNID_GMACRFR_1 103
+
+#define MSGRNG_STNID_DMA 104
+#define MSGRNG_STNID_DMA_0 104
+#define MSGRNG_STNID_DMA_1 105
+#define MSGRNG_STNID_DMA_2 106
+#define MSGRNG_STNID_DMA_3 107
+
+#define MSGRNG_STNID_XGS0FR 112
+#define MSGRNG_STNID_XMAC0JFR 112
+#define MSGRNG_STNID_XMAC0RFR 113
+
+#define MSGRNG_STNID_XGS1FR 114
+#define MSGRNG_STNID_XMAC1JFR 114
+#define MSGRNG_STNID_XMAC1RFR 115
+#define MSGRNG_STNID_SEC 120
+#define MSGRNG_STNID_SEC0 120
+#define MSGRNG_STNID_SEC1 121
+#define MSGRNG_STNID_SEC2 122
+#define MSGRNG_STNID_SEC3 123
+#define MSGRNG_STNID_PK0 124
+#define MSGRNG_STNID_SEC_RSA 124
+#define MSGRNG_STNID_SEC_RSVD0 125
+#define MSGRNG_STNID_SEC_RSVD1 126
+#define MSGRNG_STNID_SEC_RSVD2 127
+
+#define MSGRNG_STNID_GMAC1 80
+#define MSGRNG_STNID_GMAC1_FR_0 81
+#define MSGRNG_STNID_GMAC1_TX0 82
+#define MSGRNG_STNID_GMAC1_TX1 83
+#define MSGRNG_STNID_GMAC1_TX2 84
+#define MSGRNG_STNID_GMAC1_TX3 85
+#define MSGRNG_STNID_GMAC1_FR_1 87
+#define MSGRNG_STNID_GMAC0 96
+#define MSGRNG_STNID_GMAC0_FR_0 97
+#define MSGRNG_STNID_GMAC0_TX0 98
+#define MSGRNG_STNID_GMAC0_TX1 99
+#define MSGRNG_STNID_GMAC0_TX2 100
+#define MSGRNG_STNID_GMAC0_TX3 101
+#define MSGRNG_STNID_GMAC0_FR_1 103
+#define MSGRNG_STNID_CMP_0 108
+#define MSGRNG_STNID_CMP_1 109
+#define MSGRNG_STNID_CMP_2 110
+#define MSGRNG_STNID_CMP_3 111
+#define MSGRNG_STNID_PCIE_0 116
+#define MSGRNG_STNID_PCIE_1 117
+#define MSGRNG_STNID_PCIE_2 118
+#define MSGRNG_STNID_PCIE_3 119
+#define MSGRNG_STNID_XLS_PK0 121
+
+#define MSGRNG_CODE_MAC 0
+#define MSGRNG_CODE_XGMAC 2
+#define MSGRNG_CODE_SEC 0
+#define MSGRNG_CODE_BOOT_WAKEUP 200
+#define MSGRNG_CODE_SPI4 3
+
+#define msgrng_read_status() read_c2_register32(MSGRNG_MSG_STATUS_REG, 0)
+#define msgrng_read_config() read_c2_register32(MSGRNG_MSG_CONFIG_REG, 0)
+#define msgrng_write_config(v) write_c2_register32(MSGRNG_MSG_CONFIG_REG, 0, v)
+#define msgrng_read_bucksize(b) read_c2_register32(MSGRNG_MSG_BUCKSIZE_REG, b)
+#define msgrng_write_bucksize(b, v) write_c2_register32(MSGRNG_MSG_BUCKSIZE_REG, b, v)
+#define msgrng_read_cc(r, s) read_c2_register32(r, s)
+#define msgrng_write_cc(r, v, s) write_c2_register32(r, s, v)
+
+#define msgrng_load_rx_msg0() read_c2_register64(MSGRNG_RX_BUF_REG, 0)
+#define msgrng_load_rx_msg1() read_c2_register64(MSGRNG_RX_BUF_REG, 1)
+#define msgrng_load_rx_msg2() read_c2_register64(MSGRNG_RX_BUF_REG, 2)
+#define msgrng_load_rx_msg3() read_c2_register64(MSGRNG_RX_BUF_REG, 3)
+
+#define msgrng_load_tx_msg0(v) write_c2_register64(MSGRNG_TX_BUF_REG, 0, v)
+#define msgrng_load_tx_msg1(v) write_c2_register64(MSGRNG_TX_BUF_REG, 1, v)
+#define msgrng_load_tx_msg2(v) write_c2_register64(MSGRNG_TX_BUF_REG, 2, v)
+#define msgrng_load_tx_msg3(v) write_c2_register64(MSGRNG_TX_BUF_REG, 3, v)
+
+static __inline void
+msgrng_send(unsigned int stid)
+{
+ __asm__ volatile (
+ ".set push\n"
+ ".set noreorder\n"
+ "move $8, %0\n"
+ "c2 0x80001\n" /* msgsnd $8 */
+ ".set pop\n"
+ :: "r" (stid): "$8"
+ );
+}
+
+static __inline void
+msgrng_receive(unsigned int pri)
+{
+ __asm__ volatile (
+ ".set push\n"
+ ".set noreorder\n"
+ "move $8, %0\n"
+ "c2 0x80002\n" /* msgld $8 */
+ ".set pop\n"
+ :: "r" (pri): "$8"
+ );
+}
+
+static __inline void
+msgrng_wait(unsigned int mask)
+{
+ __asm__ volatile (
+ ".set push\n"
+ ".set noreorder\n"
+ "move $8, %0\n"
+ "c2 0x80003\n" /* msgwait $8 */
+ ".set pop\n"
+ :: "r" (mask): "$8"
+ );
+}
+
+static __inline uint32_t
+msgrng_access_enable(void)
+{
+ uint32_t sr = mips_rd_status();
+
+ mips_wr_status((sr & ~MIPS_SR_INT_IE) | MIPS_SR_COP_2_BIT);
+ return (sr);
+}
+
+static __inline void
+msgrng_restore(uint32_t sr)
+{
+
+ mips_wr_status(sr);
+}
+
+struct msgrng_msg {
+ uint64_t msg0;
+ uint64_t msg1;
+ uint64_t msg2;
+ uint64_t msg3;
+};
+
+static __inline int
+message_send(unsigned int size, unsigned int code,
+ unsigned int stid, struct msgrng_msg *msg)
+{
+ unsigned int dest = 0;
+ unsigned long long status = 0;
+ int i = 0;
+
+ /*
+ * Make sure that all the writes pending at the cpu are flushed.
+ * Any writes pending on CPU will not be see by devices. L1/L2
+ * caches are coherent with IO, so no cache flush needed.
+ */
+ __asm __volatile ("sync");
+
+ /* Load TX message buffers */
+ msgrng_load_tx_msg0(msg->msg0);
+ msgrng_load_tx_msg1(msg->msg1);
+ msgrng_load_tx_msg2(msg->msg2);
+ msgrng_load_tx_msg3(msg->msg3);
+ dest = ((size - 1) << 16) | (code << 8) | stid;
+
+ /*
+ * Retry a few times on credit fail, this should be a
+ * transient condition, unless there is a configuration
+ * failure, or the receiver is stuck.
+ */
+ for (i = 0; i < 8; i++) {
+ msgrng_send(dest);
+ status = msgrng_read_status();
+ KASSERT((status & 0x2) == 0, ("Send pending fail!"));
+ if ((status & 0x4) == 0)
+ return (0);
+ }
+
+ /* If there is a credit failure, return error */
+ return (status & 0x06);
+}
+
+static __inline int
+message_receive(int bucket, int *size, int *code, int *stid,
+ struct msgrng_msg *msg)
+{
+ uint32_t status = 0, tmp = 0;
+
+ msgrng_receive(bucket);
+
+ /* wait for load pending to clear */
+ do {
+ status = msgrng_read_status();
+ } while ((status & 0x08) != 0);
+
+ /* receive error bits */
+ tmp = status & 0x30;
+ if (tmp != 0)
+ return (tmp);
+
+ *size = ((status & 0xc0) >> 6) + 1;
+ *code = (status & 0xff00) >> 8;
+ *stid = (status & 0x7f0000) >> 16;
+ msg->msg0 = msgrng_load_rx_msg0();
+ msg->msg1 = msgrng_load_rx_msg1();
+ msg->msg2 = msgrng_load_rx_msg2();
+ msg->msg3 = msgrng_load_rx_msg3();
+ return (0);
+}
+
+#define MSGRNG_STN_RX_QSIZE 256
+#define MSGRNG_NSTATIONS 128
+#define MSGRNG_CORE_NBUCKETS 8
+
+struct stn_cc {
+ unsigned short counters[16][8];
+};
+
+struct bucket_size {
+ unsigned short bucket[MSGRNG_NSTATIONS];
+};
+
+extern struct bucket_size bucket_sizes;
+
+extern struct stn_cc cc_table_cpu_0;
+extern struct stn_cc cc_table_cpu_1;
+extern struct stn_cc cc_table_cpu_2;
+extern struct stn_cc cc_table_cpu_3;
+extern struct stn_cc cc_table_cpu_4;
+extern struct stn_cc cc_table_cpu_5;
+extern struct stn_cc cc_table_cpu_6;
+extern struct stn_cc cc_table_cpu_7;
+extern struct stn_cc cc_table_xgs_0;
+extern struct stn_cc cc_table_xgs_1;
+extern struct stn_cc cc_table_gmac;
+extern struct stn_cc cc_table_dma;
+extern struct stn_cc cc_table_sec;
+
+extern struct bucket_size xls_bucket_sizes;
+
+extern struct stn_cc xls_cc_table_cpu_0;
+extern struct stn_cc xls_cc_table_cpu_1;
+extern struct stn_cc xls_cc_table_cpu_2;
+extern struct stn_cc xls_cc_table_cpu_3;
+extern struct stn_cc xls_cc_table_gmac0;
+extern struct stn_cc xls_cc_table_gmac1;
+extern struct stn_cc xls_cc_table_cmp;
+extern struct stn_cc xls_cc_table_pcie;
+extern struct stn_cc xls_cc_table_dma;
+extern struct stn_cc xls_cc_table_sec;
+
+typedef void (*msgring_handler)(int, int, int, int, struct msgrng_msg *, void *);
+int register_msgring_handler(int startb, int endb, msgring_handler action,
+ void *arg);
+uint32_t xlr_msgring_handler(uint8_t bucket_mask, uint32_t max_messages);
+void xlr_msgring_cpu_init(void);
+void xlr_msgring_config(void);
+
+#endif
Property changes on: trunk/sys/mips/rmi/msgring.h
___________________________________________________________________
Added: svn:eol-style
## -0,0 +1 ##
+native
\ No newline at end of property
Added: svn:keywords
## -0,0 +1 ##
+MidnightBSD=%H
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+text/plain
\ No newline at end of property
Added: trunk/sys/mips/rmi/msgring_xls.c
===================================================================
--- trunk/sys/mips/rmi/msgring_xls.c (rev 0)
+++ trunk/sys/mips/rmi/msgring_xls.c 2018-05-26 21:55:02 UTC (rev 9987)
@@ -0,0 +1,218 @@
+/* $MidnightBSD$ */
+/**********************************************************
+ * -----------------DO NOT EDIT THIS FILE------------------
+ * This file has been autogenerated by the build process
+ * from "msgring_xls.cfg"
+ **********************************************************/
+
+#include <mips/rmi/msgring.h>
+
+struct bucket_size xls_bucket_sizes = {
+ {32, 32, 32, 32, 32, 32, 32, 32,
+ 32, 32, 32, 32, 32, 32, 32, 32,
+ 32, 32, 32, 32, 32, 32, 32, 32,
+ 32, 32, 32, 32, 32, 32, 32, 32,
+ 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 32, 32, 32, 32, 32, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 32, 32, 32, 32, 32, 0, 0,
+ 64, 64, 64, 64, 32, 32, 32, 32,
+ 0, 0, 0, 0, 0, 0, 0, 0,
+ 128, 128, 0, 0, 0, 0, 0, 0,
+ }
+};
+
+struct stn_cc xls_cc_table_cpu_0 = {{
+ {1, 0, 0, 0, 0, 0, 0, 0},
+ {0, 0, 0, 8, 0, 0, 0, 0},
+ {0, 0, 0, 8, 0, 0, 0, 0},
+ {0, 0, 0, 8, 0, 0, 0, 0},
+ {0, 0, 0, 0, 0, 0, 0, 0},
+ {0, 0, 0, 0, 0, 0, 0, 0},
+ {0, 0, 0, 0, 0, 0, 0, 0},
+ {0, 0, 0, 0, 0, 0, 0, 0},
+ {0, 0, 0, 0, 0, 0, 0, 0},
+ {0, 0, 0, 0, 0, 0, 0, 0},
+ {0, 4, 8, 8, 8, 8, 0, 0},
+ {0, 0, 0, 0, 0, 0, 0, 0},
+ {0, 4, 8, 8, 8, 8, 0, 0},
+ {16, 16, 16, 16, 16, 16, 16, 16},
+ {0, 0, 0, 0, 0, 0, 0, 0},
+ {32, 32, 0, 0, 0, 0, 0, 0},
+}};
+
+struct stn_cc xls_cc_table_cpu_1 = {{
+ {1, 0, 0, 0, 0, 0, 0, 0},
+ {0, 0, 0, 0, 0, 0, 0, 0},
+ {0, 0, 0, 0, 0, 0, 0, 0},
+ {0, 0, 0, 0, 0, 0, 0, 0},
+ {0, 0, 0, 0, 0, 0, 0, 0},
+ {0, 0, 0, 0, 0, 0, 0, 0},
+ {0, 0, 0, 0, 0, 0, 0, 0},
+ {0, 0, 0, 0, 0, 0, 0, 0},
+ {0, 0, 0, 0, 0, 0, 0, 0},
+ {0, 0, 0, 0, 0, 0, 0, 0},
+ {0, 4, 8, 8, 8, 8, 0, 0},
+ {0, 0, 0, 0, 0, 0, 0, 0},
+ {0, 4, 8, 8, 8, 8, 0, 0},
+ {16, 16, 16, 16, 16, 16, 16, 16},
+ {0, 0, 0, 0, 0, 0, 0, 0},
+ {32, 32, 0, 0, 0, 0, 0, 0},
+}};
+
+struct stn_cc xls_cc_table_cpu_2 = {{
+ {0, 0, 0, 0, 0, 0, 0, 0},
+ {0, 0, 0, 0, 0, 0, 0, 0},
+ {0, 0, 0, 0, 0, 0, 0, 0},
+ {0, 0, 0, 0, 0, 0, 0, 0},
+ {0, 0, 0, 0, 0, 0, 0, 0},
+ {0, 0, 0, 0, 0, 0, 0, 0},
+ {0, 0, 0, 0, 0, 0, 0, 0},
+ {0, 0, 0, 0, 0, 0, 0, 0},
+ {0, 0, 0, 0, 0, 0, 0, 0},
+ {0, 0, 0, 0, 0, 0, 0, 0},
+ {0, 4, 8, 8, 8, 8, 0, 0},
+ {0, 0, 0, 0, 0, 0, 0, 0},
+ {0, 4, 8, 8, 8, 8, 0, 0},
+ {16, 16, 16, 16, 0, 0, 0, 0},
+ {0, 0, 0, 0, 0, 0, 0, 0},
+ {32, 32, 0, 0, 0, 0, 0, 0},
+}};
+
+struct stn_cc xls_cc_table_cpu_3 = {{
+ {0, 0, 0, 0, 0, 0, 0, 0},
+ {0, 0, 0, 0, 0, 0, 0, 0},
+ {0, 0, 0, 0, 0, 0, 0, 0},
+ {0, 0, 0, 0, 0, 0, 0, 0},
+ {0, 0, 0, 0, 0, 0, 0, 0},
+ {0, 0, 0, 0, 0, 0, 0, 0},
+ {0, 0, 0, 0, 0, 0, 0, 0},
+ {0, 0, 0, 0, 0, 0, 0, 0},
+ {0, 0, 0, 0, 0, 0, 0, 0},
+ {0, 0, 0, 0, 0, 0, 0, 0},
+ {0, 4, 8, 8, 8, 8, 0, 0},
+ {0, 0, 0, 0, 0, 0, 0, 0},
+ {0, 4, 8, 8, 8, 8, 0, 0},
+ {16, 16, 16, 16, 0, 0, 0, 0},
+ {0, 0, 0, 0, 0, 0, 0, 0},
+ {32, 32, 0, 0, 0, 0, 0, 0},
+}};
+
+struct stn_cc xls_cc_table_gmac0 = {{
+ {8, 8, 8, 8, 8, 8, 8, 8},
+ {8, 8, 8, 8, 8, 8, 8, 8},
+ {8, 8, 8, 8, 8, 8, 8, 8},
+ {8, 8, 8, 8, 8, 8, 8, 8},
+ {0, 0, 0, 0, 0, 0, 0, 0},
+ {0, 0, 0, 0, 0, 0, 0, 0},
+ {0, 0, 0, 0, 0, 0, 0, 0},
+ {0, 0, 0, 0, 0, 0, 0, 0},
+ {0, 0, 0, 0, 0, 0, 0, 0},
+ {0, 0, 0, 0, 0, 0, 0, 0},
+ {0, 8, 0, 0, 0, 0, 0, 0},
+ {0, 0, 0, 0, 0, 0, 0, 0},
+ {0, 8, 0, 0, 0, 0, 0, 0},
+ {0, 0, 0, 0, 0, 0, 0, 0},
+ {0, 0, 0, 0, 0, 0, 0, 0},
+ {0, 0, 0, 0, 0, 0, 0, 0},
+}};
+
+struct stn_cc xls_cc_table_gmac1 = {{
+ {8, 8, 8, 8, 8, 8, 8, 8},
+ {8, 8, 8, 8, 8, 8, 8, 8},
+ {8, 8, 8, 8, 8, 8, 8, 8},
+ {8, 8, 8, 8, 8, 8, 8, 8},
+ {0, 0, 0, 0, 0, 0, 0, 0},
+ {0, 0, 0, 0, 0, 0, 0, 0},
+ {0, 0, 0, 0, 0, 0, 0, 0},
+ {0, 0, 0, 0, 0, 0, 0, 0},
+ {0, 0, 0, 0, 0, 0, 0, 0},
+ {0, 0, 0, 0, 0, 0, 0, 0},
+ {0, 8, 0, 0, 0, 0, 0, 0},
+ {0, 0, 0, 0, 0, 0, 0, 0},
+ {0, 8, 0, 0, 0, 0, 0, 0},
+ {0, 0, 0, 0, 0, 0, 0, 0},
+ {0, 0, 0, 0, 0, 0, 0, 0},
+ {0, 0, 0, 0, 0, 0, 0, 0},
+}};
+
+struct stn_cc xls_cc_table_dma = {{
+ {4, 4, 4, 4, 4, 4, 4, 4},
+ {4, 4, 4, 2, 4, 4, 4, 4},
+ {4, 4, 4, 2, 4, 4, 4, 4},
+ {4, 4, 4, 2, 4, 4, 4, 4},
+ {0, 0, 0, 0, 0, 0, 0, 0},
+ {0, 0, 0, 0, 0, 0, 0, 0},
+ {0, 0, 0, 0, 0, 0, 0, 0},
+ {0, 0, 0, 0, 0, 0, 0, 0},
+ {0, 0, 0, 0, 0, 0, 0, 0},
+ {0, 0, 0, 0, 0, 0, 0, 0},
+ {0, 0, 0, 0, 0, 0, 0, 0},
+ {0, 0, 0, 0, 0, 0, 0, 0},
+ {0, 0, 0, 0, 0, 0, 0, 0},
+ {0, 0, 0, 0, 0, 0, 0, 0},
+ {0, 0, 0, 0, 0, 0, 0, 0},
+ {0, 0, 0, 0, 0, 0, 0, 0},
+}};
+
+struct stn_cc xls_cc_table_cmp = {{
+ {4, 4, 4, 4, 4, 4, 4, 4},
+ {4, 4, 4, 2, 4, 4, 4, 4},
+ {4, 4, 4, 2, 4, 4, 4, 4},
+ {4, 4, 4, 2, 4, 4, 4, 4},
+ {0, 0, 0, 0, 0, 0, 0, 0},
+ {0, 0, 0, 0, 0, 0, 0, 0},
+ {0, 0, 0, 0, 0, 0, 0, 0},
+ {0, 0, 0, 0, 0, 0, 0, 0},
+ {0, 0, 0, 0, 0, 0, 0, 0},
+ {0, 0, 0, 0, 0, 0, 0, 0},
+ {0, 0, 0, 0, 0, 0, 0, 0},
+ {0, 0, 0, 0, 0, 0, 0, 0},
+ {0, 0, 0, 0, 0, 0, 0, 0},
+ {0, 0, 0, 0, 0, 0, 0, 0},
+ {0, 0, 0, 0, 0, 0, 0, 0},
+ {0, 0, 0, 0, 0, 0, 0, 0},
+}};
+
+struct stn_cc xls_cc_table_pcie = {{
+ {0, 0, 0, 0, 0, 0, 0, 0},
+ {0, 0, 0, 0, 0, 0, 0, 0},
+ {0, 0, 0, 0, 0, 0, 0, 0},
+ {0, 0, 0, 0, 0, 0, 0, 0},
+ {0, 0, 0, 0, 0, 0, 0, 0},
+ {0, 0, 0, 0, 0, 0, 0, 0},
+ {0, 0, 0, 0, 0, 0, 0, 0},
+ {0, 0, 0, 0, 0, 0, 0, 0},
+ {0, 0, 0, 0, 0, 0, 0, 0},
+ {0, 0, 0, 0, 0, 0, 0, 0},
+ {0, 0, 0, 0, 0, 0, 0, 0},
+ {0, 0, 0, 0, 0, 0, 0, 0},
+ {0, 0, 0, 0, 0, 0, 0, 0},
+ {0, 0, 0, 0, 0, 0, 0, 0},
+ {0, 0, 0, 0, 0, 0, 0, 0},
+ {0, 0, 0, 0, 0, 0, 0, 0},
+}};
+
+struct stn_cc xls_cc_table_sec = {{
+ {6, 8, 8, 8, 0, 0, 0, 0},
+ {8, 8, 8, 4, 0, 0, 0, 0},
+ {8, 8, 8, 4, 0, 0, 0, 0},
+ {8, 8, 8, 4, 0, 0, 0, 0},
+ {0, 0, 0, 0, 0, 0, 0, 0},
+ {0, 0, 0, 0, 0, 0, 0, 0},
+ {0, 0, 0, 0, 0, 0, 0, 0},
+ {0, 0, 0, 0, 0, 0, 0, 0},
+ {0, 0, 0, 0, 0, 0, 0, 0},
+ {0, 0, 0, 0, 0, 0, 0, 0},
+ {0, 0, 0, 0, 0, 0, 0, 0},
+ {0, 0, 0, 0, 0, 0, 0, 0},
+ {0, 0, 0, 0, 0, 0, 0, 0},
+ {0, 0, 0, 0, 0, 0, 0, 0},
+ {0, 0, 0, 0, 0, 0, 0, 0},
+ {0, 0, 0, 0, 0, 0, 0, 0},
+}};
Property changes on: trunk/sys/mips/rmi/msgring_xls.c
___________________________________________________________________
Added: svn:eol-style
## -0,0 +1 ##
+native
\ No newline at end of property
Added: svn:keywords
## -0,0 +1 ##
+MidnightBSD=%H
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+text/plain
\ No newline at end of property
Added: trunk/sys/mips/rmi/msgring_xls.cfg
===================================================================
--- trunk/sys/mips/rmi/msgring_xls.cfg (rev 0)
+++ trunk/sys/mips/rmi/msgring_xls.cfg 2018-05-26 21:55:02 UTC (rev 9987)
@@ -0,0 +1,563 @@
+/*********************************************************************
+ *
+ * Copyright 2003-2006 Raza Microelectronics, Inc. (RMI). All rights
+ * reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in
+ * the documentation and/or other materials provided with the
+ * distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY Raza Microelectronics, Inc. ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL RMI OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES, LOSS OF USE, DATA, OR PROFITS, OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
+ * THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * *****************************RMI_2**********************************/
+
+
+/*
+ * This file defines the message ring configuration for XLS two core. It tries to allow
+ * many different point-point communications between the message stations on the message ring
+ * and as result is _not_ the best configuration for performance
+ *
+ * The message ring on phoenix family of processors connects the cpus, gmacs, xgmac/spi4,
+ * security engine and the general purpose DMA engines. It provides a high bandwidth,
+ * low latency communication links. On traditional processors, this communication goes through
+ * which inherently does not scale very well with increasing number of cpus.
+ *
+ * Message ring has an in-built flow control mechanism. Every agent/station on the ring has to
+ * have software configured credits to send messages to any agent. Every receiving agent on the
+ * ring has a 256 entry FIFO that can divided into "buckets". All addressing on the ring is
+ * in terms of buckets. There are a total 128 buckets on the ring. The total number of credits
+ * across all sending agents should not exceed the bucket size.
+ *
+ * Below are the receiving agents and the max number of buckets they can have
+ * CPU 0 : 8 buckets
+ * CPU 1 : 8 buckets
+ *
+ * GMAC : 8 buckets
+ *
+ * SEC : 8 buckets
+ *
+ * DMA : 8 buckets
+ *
+ * CMP : Currently disabled.
+ *
+ * The bucket size of a bucket should be aligned to the bucket's starting index in that
+ * receiving station's FIFO. For example, if sizes of bucket0 and bucket1 of a station
+ * are 32 and 32, bucket2's size has to be 64. bucket size 0 is valid.
+ *
+ * The format of the file is pretty straight forward. Each bucket definition has the size
+ * and the list of sending agents to that bucket with the number of credits to send.
+ *
+ * Undefined buckets have a size of 0 and Tx stations have 0 credits to send to that bucket.
+ *
+ * Following are the currently supported bucket names
+ * cpu_0_0
+ * cpu_0_1
+ * cpu_0_2
+ * cpu_0_3
+ * cpu_0_4
+ * cpu_0_5
+ * cpu_0_6
+ * cpu_0_7
+ *
+ * cpu_1_0
+ * cpu_1_1
+ * cpu_1_2
+ * cpu_1_3
+ * cpu_1_4
+ * cpu_1_5
+ * cpu_1_6
+ * cpu_1_7
+ *
+ * enabled only for xls-b0
+ * cpu_2_0
+ * cpu_2_1
+ * cpu_2_2
+ * cpu_2_3
+ * cpu_2_4
+ * cpu_2_5
+ * cpu_2_6
+ * cpu_2_7
+ *
+ * enabled only for xls-b0
+ * cpu_3_0
+ * cpu_3_1
+ * cpu_3_2
+ * cpu_3_3
+ * cpu_3_4
+ * cpu_3_5
+ * cpu_3_6
+ * cpu_3_7
+ *
+ * gmac0_rfr
+ * gmac0_tx_0
+ * gmac0_tx_1
+ * gmac0_tx_2
+ * gmac0_tx_3
+ *
+ * gmac1_rfr
+ * gmac1_tx_0
+ * gmac1_tx_1
+ * gmac1_tx_2
+ * gmac1_tx_3
+ *
+ * sec_pipe_0
+ * sec_rsa
+ *
+ * Following are the currently supported Tx Agent/Station names
+ *
+ * tx_stn_cpu_0
+ * tx_stn_cpu_1
+ *
+ * tx_stn_gmac0
+ * tx_stn_gmac1
+ *
+ * tx_stn_dma
+ *
+ * tx_stn_sec
+ *
+ *
+ */
+
+/*************************************************************/
+// CPU_0 Message Station
+
+bucket "cpu_0_0" {
+ size 32;
+ "tx_stn_gmac0" 8;
+ "tx_stn_gmac1" 8;
+ "tx_stn_sec" 6;
+ "tx_stn_dma" 4;
+ "tx_stn_cmp" 4;
+ "tx_stn_cpu_0" 1;
+ "tx_stn_cpu_1" 1; /* NEEDED BY RMIOS IPSEC */
+}
+bucket "cpu_0_1" {
+ size 32;
+ "tx_stn_gmac0" 8;
+ "tx_stn_gmac1" 8;
+ "tx_stn_sec" 8;
+ "tx_stn_dma" 4;
+ "tx_stn_cmp" 4;
+}
+bucket "cpu_0_2" {
+ size 32;
+ "tx_stn_gmac0" 8;
+ "tx_stn_gmac1" 8;
+ "tx_stn_sec" 8;
+ "tx_stn_dma" 4;
+ "tx_stn_cmp" 4;
+}
+bucket "cpu_0_3" {
+ size 32;
+ "tx_stn_gmac0" 8;
+ "tx_stn_gmac1" 8;
+ "tx_stn_sec" 8;
+ "tx_stn_dma" 4;
+ "tx_stn_cmp" 4;
+}
+bucket "cpu_0_4" {
+ size 32;
+ "tx_stn_gmac0" 8;
+ "tx_stn_gmac1" 8;
+ "tx_stn_dma" 4;
+ "tx_stn_cmp" 4;
+}
+bucket "cpu_0_5" {
+ size 32;
+ "tx_stn_gmac0" 8;
+ "tx_stn_gmac1" 8;
+ "tx_stn_dma" 4;
+ "tx_stn_cmp" 4;
+}
+bucket "cpu_0_6" {
+ size 32;
+ "tx_stn_gmac0" 8;
+ "tx_stn_gmac1" 8;
+ "tx_stn_dma" 4;
+ "tx_stn_cmp" 4;
+}
+bucket "cpu_0_7" {
+ size 32;
+ "tx_stn_gmac0" 8;
+ "tx_stn_gmac1" 8;
+ "tx_stn_dma" 4;
+ "tx_stn_cmp" 4;
+}
+
+/*************************************************************/
+// CPU_1 Message Station
+
+bucket "cpu_1_0" {
+ size 32;
+ "tx_stn_gmac0" 8;
+ "tx_stn_gmac1" 8;
+ "tx_stn_sec" 8;
+ "tx_stn_dma" 4;
+ "tx_stn_cmp" 4;
+}
+bucket "cpu_1_1" {
+ size 32;
+ "tx_stn_gmac0" 8;
+ "tx_stn_gmac1" 8;
+ "tx_stn_sec" 8;
+ "tx_stn_dma" 4;
+ "tx_stn_cmp" 4;
+}
+bucket "cpu_1_2" {
+ size 32;
+ "tx_stn_gmac0" 8;
+ "tx_stn_gmac1" 8;
+ "tx_stn_sec" 8;
+ "tx_stn_dma" 4;
+ "tx_stn_cmp" 4;
+}
+bucket "cpu_1_3" {
+ size 32;
+ "tx_stn_gmac0" 8;
+ "tx_stn_gmac1" 8;
+ "tx_stn_sec" 4;
+ "tx_stn_cpu_0" 8; /* NEEDED BY RMIOS IPSEC */
+ "tx_stn_dma" 2;
+ "tx_stn_cmp" 2;
+}
+bucket "cpu_1_4" {
+ size 32;
+ "tx_stn_gmac0" 8;
+ "tx_stn_gmac1" 8;
+ "tx_stn_dma" 4;
+ "tx_stn_cmp" 4;
+}
+bucket "cpu_1_5" {
+ size 32;
+ "tx_stn_gmac0" 8;
+ "tx_stn_gmac1" 8;
+ "tx_stn_dma" 4;
+ "tx_stn_cmp" 4;
+}
+bucket "cpu_1_6" {
+ size 32;
+ "tx_stn_gmac0" 8;
+ "tx_stn_gmac1" 8;
+ "tx_stn_dma" 4;
+ "tx_stn_cmp" 4;
+}
+bucket "cpu_1_7" {
+ size 32;
+ "tx_stn_gmac0" 8;
+ "tx_stn_gmac1" 8;
+ "tx_stn_dma" 4;
+ "tx_stn_cmp" 4;
+}
+
+/*************************************************************/
+// CPU_2 Message Station
+
+bucket "cpu_2_0" {
+ size 32;
+ "tx_stn_gmac0" 8;
+ "tx_stn_gmac1" 8;
+ "tx_stn_sec" 8;
+ "tx_stn_dma" 4;
+ "tx_stn_cmp" 4;
+}
+bucket "cpu_2_1" {
+ size 32;
+ "tx_stn_gmac0" 8;
+ "tx_stn_gmac1" 8;
+ "tx_stn_sec" 8;
+ "tx_stn_dma" 4;
+ "tx_stn_cmp" 4;
+}
+bucket "cpu_2_2" {
+ size 32;
+ "tx_stn_gmac0" 8;
+ "tx_stn_gmac1" 8;
+ "tx_stn_sec" 8;
+ "tx_stn_dma" 4;
+ "tx_stn_cmp" 4;
+}
+bucket "cpu_2_3" {
+ size 32;
+ "tx_stn_gmac0" 8;
+ "tx_stn_gmac1" 8;
+ "tx_stn_sec" 4;
+ "tx_stn_cpu_0" 8; /* NEEDED BY RMIOS IPSEC */
+ "tx_stn_dma" 2;
+ "tx_stn_cmp" 2;
+}
+bucket "cpu_2_4" {
+ size 32;
+ "tx_stn_gmac0" 8;
+ "tx_stn_gmac1" 8;
+ "tx_stn_dma" 4;
+ "tx_stn_cmp" 4;
+}
+bucket "cpu_2_5" {
+ size 32;
+ "tx_stn_gmac0" 8;
+ "tx_stn_gmac1" 8;
+ "tx_stn_dma" 4;
+ "tx_stn_cmp" 4;
+}
+bucket "cpu_2_6" {
+ size 32;
+ "tx_stn_gmac0" 8;
+ "tx_stn_gmac1" 8;
+ "tx_stn_dma" 4;
+ "tx_stn_cmp" 4;
+}
+bucket "cpu_2_7" {
+ size 32;
+ "tx_stn_gmac0" 8;
+ "tx_stn_gmac1" 8;
+ "tx_stn_dma" 4;
+ "tx_stn_cmp" 4;
+}
+
+
+/*************************************************************/
+// CPU_3 Message Station
+bucket "cpu_3_0" {
+ size 32;
+ "tx_stn_gmac0" 8;
+ "tx_stn_gmac1" 8;
+ "tx_stn_sec" 8;
+ "tx_stn_dma" 4;
+ "tx_stn_cmp" 4;
+}
+bucket "cpu_3_1" {
+ size 32;
+ "tx_stn_gmac0" 8;
+ "tx_stn_gmac1" 8;
+ "tx_stn_sec" 8;
+ "tx_stn_dma" 4;
+ "tx_stn_cmp" 4;
+}
+bucket "cpu_3_2" {
+ size 32;
+ "tx_stn_gmac0" 8;
+ "tx_stn_gmac1" 8;
+ "tx_stn_sec" 8;
+ "tx_stn_dma" 4;
+ "tx_stn_cmp" 4;
+}
+bucket "cpu_3_3" {
+ size 32;
+ "tx_stn_gmac0" 8;
+ "tx_stn_gmac1" 8;
+ "tx_stn_sec" 4;
+ "tx_stn_cpu_0" 8; /* NEEDED BY RMIOS IPSEC */
+ "tx_stn_dma" 2;
+ "tx_stn_cmp" 2;
+}
+bucket "cpu_3_4" {
+ size 32;
+ "tx_stn_gmac0" 8;
+ "tx_stn_gmac1" 8;
+ "tx_stn_dma" 4;
+ "tx_stn_cmp" 4;
+}
+bucket "cpu_3_5" {
+ size 32;
+ "tx_stn_gmac0" 8;
+ "tx_stn_gmac1" 8;
+ "tx_stn_dma" 4;
+ "tx_stn_cmp" 4;
+}
+bucket "cpu_3_6" {
+ size 32;
+ "tx_stn_gmac0" 8;
+ "tx_stn_gmac1" 8;
+ "tx_stn_dma" 4;
+ "tx_stn_cmp" 4;
+}
+bucket "cpu_3_7" {
+ size 32;
+ "tx_stn_gmac0" 8;
+ "tx_stn_gmac1" 8;
+ "tx_stn_dma" 4;
+ "tx_stn_cmp" 4;
+}
+
+/*************************************************************/
+
+// GMAC Message Station
+
+bucket "gmac0_rfr" {
+ size 32;
+ "tx_stn_cpu_0" 4;
+ "tx_stn_cpu_1" 4;
+ "tx_stn_cpu_2" 4;
+ "tx_stn_cpu_3" 4;
+ "tx_stn_gmac0" 8;
+ "tx_stn_gmac1" 8;
+}
+
+bucket "gmac0_tx_0" {
+ size 32;
+ "tx_stn_cpu_0" 8;
+ "tx_stn_cpu_1" 8;
+ "tx_stn_cpu_2" 8;
+ "tx_stn_cpu_3" 8;
+}
+
+bucket "gmac0_tx_1" {
+ size 32;
+ "tx_stn_cpu_0" 8;
+ "tx_stn_cpu_1" 8;
+ "tx_stn_cpu_2" 8;
+ "tx_stn_cpu_3" 8;
+}
+
+bucket "gmac0_tx_2" {
+ size 32;
+ "tx_stn_cpu_0" 8;
+ "tx_stn_cpu_1" 8;
+ "tx_stn_cpu_2" 8;
+ "tx_stn_cpu_3" 8;
+}
+
+bucket "gmac0_tx_3" {
+ size 32;
+ "tx_stn_cpu_0" 8;
+ "tx_stn_cpu_1" 8;
+ "tx_stn_cpu_2" 8;
+ "tx_stn_cpu_3" 8;
+}
+
+bucket "gmac1_rfr" {
+ size 32;
+ "tx_stn_cpu_0" 4;
+ "tx_stn_cpu_1" 4;
+ "tx_stn_cpu_2" 4;
+ "tx_stn_cpu_3" 4;
+ "tx_stn_gmac0" 8;
+ "tx_stn_gmac1" 8;
+}
+
+bucket "gmac1_tx_0" {
+ size 32;
+ "tx_stn_cpu_0" 8;
+ "tx_stn_cpu_1" 8;
+ "tx_stn_cpu_2" 8;
+ "tx_stn_cpu_3" 8;
+}
+
+bucket "gmac1_tx_1" {
+ size 32;
+ "tx_stn_cpu_0" 8;
+ "tx_stn_cpu_1" 8;
+ "tx_stn_cpu_2" 8;
+ "tx_stn_cpu_3" 8;
+}
+
+bucket "gmac1_tx_2" {
+ size 32;
+ "tx_stn_cpu_0" 8;
+ "tx_stn_cpu_1" 8;
+ "tx_stn_cpu_2" 8;
+ "tx_stn_cpu_3" 8;
+}
+
+bucket "gmac1_tx_3" {
+ size 32;
+ "tx_stn_cpu_0" 8;
+ "tx_stn_cpu_1" 8;
+ "tx_stn_cpu_2" 8;
+ "tx_stn_cpu_3" 8;
+}
+
+/*************************************************************/
+// Security Message Station
+
+bucket "sec_pipe_0" {
+ size 128;
+ "tx_stn_cpu_0" 32;
+ "tx_stn_cpu_1" 32;
+ "tx_stn_cpu_2" 32;
+ "tx_stn_cpu_3" 32;
+}
+
+bucket "sec_rsa_ecc" {
+ size 128;
+ "tx_stn_cpu_0" 32;
+ "tx_stn_cpu_1" 32;
+ "tx_stn_cpu_2" 32;
+ "tx_stn_cpu_3" 32;
+}
+
+bucket "dma_rsvd_0" {
+ size 64;
+ "tx_stn_cpu_0" 16;
+ "tx_stn_cpu_1" 16;
+ "tx_stn_cpu_2" 16;
+ "tx_stn_cpu_3" 16;
+}
+bucket "dma_rsvd_1" {
+ size 64;
+ "tx_stn_cpu_0" 16;
+ "tx_stn_cpu_1" 16;
+ "tx_stn_cpu_2" 16;
+ "tx_stn_cpu_3" 16;
+}
+
+bucket "dma_rsvd_2" {
+ size 64;
+ "tx_stn_cpu_0" 16;
+ "tx_stn_cpu_1" 16;
+ "tx_stn_cpu_2" 16;
+ "tx_stn_cpu_3" 16;
+}
+
+bucket "dma_rsvd_3" {
+ size 64;
+ "tx_stn_cpu_0" 16;
+ "tx_stn_cpu_1" 16;
+ "tx_stn_cpu_2" 16;
+ "tx_stn_cpu_3" 16;
+}
+
+/*************************************************************/
+// Compression Message Station
+
+bucket "cmp_0" {
+ size 32;
+ "tx_stn_cpu_0" 16;
+ "tx_stn_cpu_1" 16;
+}
+
+bucket "cmp_1" {
+ size 32;
+ "tx_stn_cpu_0" 16;
+ "tx_stn_cpu_1" 16;
+}
+
+bucket "cmp_2" {
+ size 32;
+ "tx_stn_cpu_0" 16;
+ "tx_stn_cpu_1" 16;
+}
+
+bucket "cmp_3" {
+ size 32;
+ "tx_stn_cpu_0" 16;
+ "tx_stn_cpu_1" 16;
+}
+
Property changes on: trunk/sys/mips/rmi/msgring_xls.cfg
___________________________________________________________________
Added: mnbsd:nokeywords
## -0,0 +1 ##
+MidnightBSD=%H
\ No newline at end of property
Added: trunk/sys/mips/rmi/pcibus.h
===================================================================
--- trunk/sys/mips/rmi/pcibus.h (rev 0)
+++ trunk/sys/mips/rmi/pcibus.h 2018-05-26 21:55:02 UTC (rev 9987)
@@ -0,0 +1,36 @@
+/* $MidnightBSD$ */
+/*-
+ * Copyright (c) 1998 Doug Rabson
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ * $FreeBSD: stable/10/sys/mips/rmi/pcibus.h 204136 2010-02-20 17:19:16Z rrs $
+ */
+#define DEFAULT_PCI_CONFIG_BASE 0x18000000
+#define MSI_MIPS_ADDR_BASE 0xfee00000
+
+#define PCIE_LINK0_MSI_STATUS 0x90
+#define PCIE_LINK1_MSI_STATUS 0x94
+#define PCIE_LINK2_MSI_STATUS 0x190
+#define PCIE_LINK3_MSI_STATUS 0x194
+
Property changes on: trunk/sys/mips/rmi/pcibus.h
___________________________________________________________________
Added: svn:eol-style
## -0,0 +1 ##
+native
\ No newline at end of property
Added: svn:keywords
## -0,0 +1 ##
+MidnightBSD=%H
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+text/plain
\ No newline at end of property
Added: trunk/sys/mips/rmi/pic.h
===================================================================
--- trunk/sys/mips/rmi/pic.h (rev 0)
+++ trunk/sys/mips/rmi/pic.h 2018-05-26 21:55:02 UTC (rev 9987)
@@ -0,0 +1,273 @@
+/* $MidnightBSD$ */
+/*-
+ * Copyright (c) 2003-2009 RMI Corporation
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * 3. Neither the name of RMI Corporation, nor the names of its contributors,
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ * RMI_BSD
+ * $FreeBSD: stable/10/sys/mips/rmi/pic.h 261455 2014-02-04 03:36:42Z eadler $
+ */
+#ifndef _RMI_PIC_H_
+#define _RMI_PIC_H_
+
+#include <sys/cdefs.h>
+#include <sys/lock.h>
+#include <sys/mutex.h>
+#include <mips/rmi/iomap.h>
+
+#define PIC_IRT_WD_INDEX 0
+#define PIC_IRT_TIMER_INDEX(i) (1 + (i))
+#define PIC_IRT_UART_0_INDEX 9
+#define PIC_IRT_UART_1_INDEX 10
+#define PIC_IRT_I2C_0_INDEX 11
+#define PIC_IRT_I2C_1_INDEX 12
+#define PIC_IRT_PCMCIA_INDEX 13
+#define PIC_IRT_GPIO_INDEX 14
+#define PIC_IRT_HYPER_INDEX 15
+#define PIC_IRT_PCIX_INDEX 16
+#define PIC_IRT_GMAC0_INDEX 17
+#define PIC_IRT_GMAC1_INDEX 18
+#define PIC_IRT_GMAC2_INDEX 19
+#define PIC_IRT_GMAC3_INDEX 20
+#define PIC_IRT_XGS0_INDEX 21
+#define PIC_IRT_XGS1_INDEX 22
+#define PIC_IRT_HYPER_FATAL_INDEX 23
+#define PIC_IRT_PCIX_FATAL_INDEX 24
+#define PIC_IRT_BRIDGE_AERR_INDEX 25
+#define PIC_IRT_BRIDGE_BERR_INDEX 26
+#define PIC_IRT_BRIDGE_TB_INDEX 27
+#define PIC_IRT_BRIDGE_AERR_NMI_INDEX 28
+
+/* numbering for XLS */
+#define PIC_IRT_BRIDGE_ERR_INDEX 25
+#define PIC_IRT_PCIE_LINK0_INDEX 26
+#define PIC_IRT_PCIE_LINK1_INDEX 27
+#define PIC_IRT_PCIE_LINK2_INDEX 23
+#define PIC_IRT_PCIE_LINK3_INDEX 24
+#define PIC_IRT_PCIE_B0_LINK2_INDEX 28
+#define PIC_IRT_PCIE_B0_LINK3_INDEX 29
+#define PIC_IRT_PCIE_INT_INDEX 28
+#define PIC_IRT_PCIE_FATAL_INDEX 29
+#define PIC_IRT_GPIO_B_INDEX 30
+#define PIC_IRT_USB_INDEX 31
+#define PIC_NUM_IRTS 32
+
+#define PIC_CLOCK_TIMER 7
+
+#define PIC_CTRL 0x00
+#define PIC_IPI 0x04
+#define PIC_INT_ACK 0x06
+
+#define WD_MAX_VAL_0 0x08
+#define WD_MAX_VAL_1 0x09
+#define WD_MASK_0 0x0a
+#define WD_MASK_1 0x0b
+#define WD_HEARBEAT_0 0x0c
+#define WD_HEARBEAT_1 0x0d
+
+#define PIC_IRT_0_BASE 0x40
+#define PIC_IRT_1_BASE 0x80
+#define PIC_TIMER_MAXVAL_0_BASE 0x100
+#define PIC_TIMER_MAXVAL_1_BASE 0x110
+#define PIC_TIMER_COUNT_0_BASE 0x120
+#define PIC_TIMER_COUNT_1_BASE 0x130
+
+#define PIC_IRT_0(picintr) (PIC_IRT_0_BASE + (picintr))
+#define PIC_IRT_1(picintr) (PIC_IRT_1_BASE + (picintr))
+
+#define PIC_TIMER_MAXVAL_0(i) (PIC_TIMER_MAXVAL_0_BASE + (i))
+#define PIC_TIMER_MAXVAL_1(i) (PIC_TIMER_MAXVAL_1_BASE + (i))
+#define PIC_TIMER_COUNT_0(i) (PIC_TIMER_COUNT_0_BASE + (i))
+#define PIC_TIMER_COUNT_1(i) (PIC_TIMER_COUNT_0_BASE + (i))
+#define PIC_TIMER_HZ 66000000U
+
+/*
+ * We use a simple mapping form PIC interrupts to CPU IRQs.
+ * The PIC interrupts 0-31 are mapped to CPU irq's 8-39.
+ * this leaves the lower 0-7 for the cpu interrupts (like
+ * count/compare, msgrng) and 40-63 for IPIs
+ */
+#define PIC_IRQ_BASE 8
+#define PIC_INTR_TO_IRQ(i) (PIC_IRQ_BASE + (i))
+#define PIC_IRQ_TO_INTR(i) ((i) - PIC_IRQ_BASE)
+
+#define PIC_WD_IRQ (PIC_IRQ_BASE + PIC_IRT_WD_INDEX)
+#define PIC_TIMER_IRQ(i) (PIC_IRQ_BASE + PIC_IRT_TIMER_INDEX(i))
+#define PIC_CLOCK_IRQ PIC_TIMER_IRQ(PIC_CLOCK_TIMER)
+
+#define PIC_UART_0_IRQ (PIC_IRQ_BASE + PIC_IRT_UART_0_INDEX)
+#define PIC_UART_1_IRQ (PIC_IRQ_BASE + PIC_IRT_UART_1_INDEX)
+#define PIC_I2C_0_IRQ (PIC_IRQ_BASE + PIC_IRT_I2C_0_INDEX)
+#define PIC_I2C_1_IRQ (PIC_IRQ_BASE + PIC_IRT_I2C_1_INDEX)
+#define PIC_PCMCIA_IRQ (PIC_IRQ_BASE + PIC_IRT_PCMCIA_INDEX)
+#define PIC_GPIO_IRQ (PIC_IRQ_BASE + PIC_IRT_GPIO_INDEX)
+#define PIC_HYPER_IRQ (PIC_IRQ_BASE + PIC_IRT_HYPER_INDEX)
+#define PIC_PCIX_IRQ (PIC_IRQ_BASE + PIC_IRT_PCIX_INDEX)
+#define PIC_GMAC_0_IRQ (PIC_IRQ_BASE + PIC_IRT_GMAC0_INDEX)
+#define PIC_GMAC_1_IRQ (PIC_IRQ_BASE + PIC_IRT_GMAC1_INDEX)
+#define PIC_GMAC_2_IRQ (PIC_IRQ_BASE + PIC_IRT_GMAC2_INDEX)
+#define PIC_GMAC_3_IRQ (PIC_IRQ_BASE + PIC_IRT_GMAC3_INDEX)
+#define PIC_XGS_0_IRQ (PIC_IRQ_BASE + PIC_IRT_XGS0_INDEX)
+#define PIC_XGS_1_IRQ (PIC_IRQ_BASE + PIC_IRT_XGS1_INDEX)
+#define PIC_HYPER_FATAL_IRQ (PIC_IRQ_BASE + PIC_IRT_HYPER_FATAL_INDEX)
+#define PIC_PCIX_FATAL_IRQ (PIC_IRQ_BASE + PIC_IRT_PCIX_FATAL_INDEX)
+#define PIC_BRIDGE_AERR_IRQ (PIC_IRQ_BASE + PIC_IRT_BRIDGE_AERR_INDEX)
+#define PIC_BRIDGE_BERR_IRQ (PIC_IRQ_BASE + PIC_IRT_BRIDGE_BERR_INDEX)
+#define PIC_BRIDGE_TB_IRQ (PIC_IRQ_BASE + PIC_IRT_BRIDGE_TB_INDEX)
+#define PIC_BRIDGE_AERR_NMI_IRQ (PIC_IRQ_BASE + PIC_IRT_BRIDGE_AERR_NMI_INDEX)
+#define PIC_BRIDGE_ERR_IRQ (PIC_IRQ_BASE + PIC_IRT_BRIDGE_ERR_INDEX)
+#define PIC_PCIE_LINK0_IRQ (PIC_IRQ_BASE + PIC_IRT_PCIE_LINK0_INDEX)
+#define PIC_PCIE_LINK1_IRQ (PIC_IRQ_BASE + PIC_IRT_PCIE_LINK1_INDEX)
+#define PIC_PCIE_LINK2_IRQ (PIC_IRQ_BASE + PIC_IRT_PCIE_LINK2_INDEX)
+#define PIC_PCIE_LINK3_IRQ (PIC_IRQ_BASE + PIC_IRT_PCIE_LINK3_INDEX)
+#define PIC_PCIE_B0_LINK2_IRQ (PIC_IRQ_BASE + PIC_IRT_PCIE_B0_LINK2_INDEX)
+#define PIC_PCIE_B0_LINK3_IRQ (PIC_IRQ_BASE + PIC_IRT_PCIE_B0_LINK3_INDEX)
+#define PIC_PCIE_INT_IRQ (PIC_IRQ_BASE + PIC_IRT_PCIE_INT_INDEX)
+#define PIC_PCIE_FATAL_IRQ (PIC_IRQ_BASE + PIC_IRT_PCIE_FATAL_INDEX)
+#define PIC_GPIO_B_IRQ (PIC_IRQ_BASE + PIC_IRT_GPIO_B_INDEX)
+#define PIC_USB_IRQ (PIC_IRQ_BASE + PIC_IRT_USB_INDEX)
+
+#define PIC_IRQ_IS_PICINTR(irq) ((irq) >= PIC_IRQ_BASE && \
+ (irq) < PIC_IRQ_BASE + PIC_NUM_IRTS)
+#define PIC_IS_EDGE_TRIGGERED(i) ((i) >= PIC_IRT_TIMER_INDEX(0) && \
+ (i) <= PIC_IRT_TIMER_INDEX(7))
+
+extern struct mtx xlr_pic_lock;
+
+static __inline uint32_t
+pic_read_control(void)
+{
+ xlr_reg_t *mmio = xlr_io_mmio(XLR_IO_PIC_OFFSET);
+ uint32_t reg;
+
+ mtx_lock_spin(&xlr_pic_lock);
+ reg = xlr_read_reg(mmio, PIC_CTRL);
+ mtx_unlock_spin(&xlr_pic_lock);
+ return (reg);
+}
+
+static __inline void
+pic_write_control(uint32_t control)
+{
+ xlr_reg_t *mmio = xlr_io_mmio(XLR_IO_PIC_OFFSET);
+
+ mtx_lock_spin(&xlr_pic_lock);
+ xlr_write_reg(mmio, PIC_CTRL, control);
+ mtx_unlock_spin(&xlr_pic_lock);
+}
+
+static __inline void
+pic_update_control(uint32_t control)
+{
+ xlr_reg_t *mmio = xlr_io_mmio(XLR_IO_PIC_OFFSET);
+
+ mtx_lock_spin(&xlr_pic_lock);
+ xlr_write_reg(mmio, PIC_CTRL, (control | xlr_read_reg(mmio, PIC_CTRL)));
+ mtx_unlock_spin(&xlr_pic_lock);
+}
+
+static __inline void
+pic_ack(int picintr)
+{
+ xlr_reg_t *mmio = xlr_io_mmio(XLR_IO_PIC_OFFSET);
+
+ xlr_write_reg(mmio, PIC_INT_ACK, 1U << picintr);
+}
+
+static __inline
+void pic_send_ipi(int cpu, int ipi)
+{
+ xlr_reg_t *mmio = xlr_io_mmio(XLR_IO_PIC_OFFSET);
+ int tid, pid;
+
+ tid = cpu & 0x3;
+ pid = (cpu >> 2) & 0x7;
+ xlr_write_reg(mmio, PIC_IPI, (pid << 20) | (tid << 16) | ipi);
+}
+
+static __inline
+void pic_setup_intr(int picintr, int irq, uint32_t cpumask, int level)
+{
+ xlr_reg_t *mmio = xlr_io_mmio(XLR_IO_PIC_OFFSET);
+
+ mtx_lock_spin(&xlr_pic_lock);
+ xlr_write_reg(mmio, PIC_IRT_0(picintr), cpumask);
+ xlr_write_reg(mmio, PIC_IRT_1(picintr), ((1U << 31) | (level << 30) |
+ (1 << 6) | irq));
+ mtx_unlock_spin(&xlr_pic_lock);
+}
+
+static __inline void
+pic_init_timer(int timer)
+{
+ xlr_reg_t *mmio = xlr_io_mmio(XLR_IO_PIC_OFFSET);
+ uint32_t val;
+
+ mtx_lock_spin(&xlr_pic_lock);
+ val = xlr_read_reg(mmio, PIC_CTRL);
+ val |= (1 << (8 + timer));
+ xlr_write_reg(mmio, PIC_CTRL, val);
+ mtx_unlock_spin(&xlr_pic_lock);
+}
+
+static __inline void
+pic_set_timer(int timer, uint64_t maxval)
+{
+ xlr_reg_t *mmio = xlr_io_mmio(XLR_IO_PIC_OFFSET);
+
+ xlr_write_reg(mmio, PIC_TIMER_MAXVAL_0(timer),
+ (maxval & 0xffffffff));
+ xlr_write_reg(mmio, PIC_TIMER_MAXVAL_1(timer),
+ (maxval >> 32) & 0xffffffff);
+}
+
+static __inline uint32_t
+pic_timer_count32(int timer)
+ {
+ xlr_reg_t *mmio = xlr_io_mmio(XLR_IO_PIC_OFFSET);
+
+ return (xlr_read_reg(mmio, PIC_TIMER_COUNT_0(timer)));
+}
+
+/*
+ * The timer can wrap 32 bits between the two reads, so we
+ * need additional logic to detect that.
+ */
+static __inline uint64_t
+pic_timer_count(int timer)
+{
+ xlr_reg_t *mmio = xlr_io_mmio(XLR_IO_PIC_OFFSET);
+ uint32_t tu1, tu2, tl;
+
+ tu1 = xlr_read_reg(mmio, PIC_TIMER_COUNT_1(timer));
+ tl = xlr_read_reg(mmio, PIC_TIMER_COUNT_0(timer));
+ tu2 = xlr_read_reg(mmio, PIC_TIMER_COUNT_1(timer));
+ if (tu2 != tu1)
+ tl = xlr_read_reg(mmio, PIC_TIMER_COUNT_0(timer));
+ return (((uint64_t)tu2 << 32) | tl);
+}
+
+#endif /* _RMI_PIC_H_ */
Property changes on: trunk/sys/mips/rmi/pic.h
___________________________________________________________________
Added: svn:eol-style
## -0,0 +1 ##
+native
\ No newline at end of property
Added: svn:keywords
## -0,0 +1 ##
+MidnightBSD=%H
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+text/plain
\ No newline at end of property
Added: trunk/sys/mips/rmi/rmi_boot_info.h
===================================================================
--- trunk/sys/mips/rmi/rmi_boot_info.h (rev 0)
+++ trunk/sys/mips/rmi/rmi_boot_info.h 2018-05-26 21:55:02 UTC (rev 9987)
@@ -0,0 +1,110 @@
+/* $MidnightBSD$ */
+/*-
+ * Copyright (c) 2003-2009 RMI Corporation
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * 3. Neither the name of RMI Corporation, nor the names of its contributors,
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ * RMI_BSD
+ * $FreeBSD: stable/10/sys/mips/rmi/rmi_boot_info.h 211994 2010-08-30 13:05:21Z jchandra $
+ */
+#ifndef _SHARED_STRUCTS_H
+#define _SHARED_STRUCTS_H
+
+#define BOOT1_INFO_VERSION 0x0001
+
+struct boot1_info {
+ uint64_t boot_level;
+ uint64_t io_base;
+ uint64_t output_device;
+ uint64_t uart_print;
+ uint64_t led_output;
+ uint64_t init;
+ uint64_t exit;
+ uint64_t warm_reset;
+ uint64_t wakeup;
+ uint64_t cpu_online_map;
+ uint64_t master_reentry_sp;
+ uint64_t master_reentry_gp;
+ uint64_t master_reentry_fn;
+ uint64_t slave_reentry_fn;
+ uint64_t magic_dword;
+ uint64_t uart_putchar;
+ uint64_t size;
+ uint64_t uart_getchar;
+ uint64_t nmi_handler;
+ uint64_t psb_version;
+ uint64_t mac_addr;
+ uint64_t cpu_frequency;
+ uint64_t board_version;
+ uint64_t malloc;
+ uint64_t free;
+ uint64_t alloc_pbuf;
+ uint64_t free_pbuf;
+ uint64_t psb_os_cpu_map;
+ uint64_t userapp_cpu_map;
+ uint64_t wakeup_os;
+ uint64_t psb_mem_map;
+ uint64_t board_major_version;
+ uint64_t board_minor_version;
+ uint64_t board_manf_revision;
+ uint64_t board_serial_number;
+ uint64_t psb_physaddr_map;
+};
+
+extern struct boot1_info xlr_boot1_info;
+
+
+/* This structure is passed to all applications launched from the linux
+ loader through K0 register
+ */
+#define XLR_LOADER_INFO_MAGIC 0x600ddeed
+struct xlr_loader_info {
+ uint32_t magic;
+ /* xlr_loader_shared_struct_t for CPU 0 will start here */
+ unsigned long sh_mem_start;
+ /* Size of the shared memory b/w linux apps and rmios apps */
+ uint32_t app_sh_mem_size;
+};
+
+/* Boot loader uses the linux mips convention */
+#define BOOT1_MEMMAP_MAX 32
+
+enum xlr_phys_memmap_t {
+ BOOT1_MEM_RAM = 1, BOOT1_MEM_ROM_DATA, BOOT1_MEM_RESERVED
+};
+
+struct xlr_boot1_mem_map {
+ uint32_t num_entries;
+ struct {
+ uint64_t addr;
+ uint64_t size;
+ uint32_t type;
+ uint32_t pad;
+ } physmem_map[BOOT1_MEMMAP_MAX];
+};
+
+
+#endif
Property changes on: trunk/sys/mips/rmi/rmi_boot_info.h
___________________________________________________________________
Added: svn:eol-style
## -0,0 +1 ##
+native
\ No newline at end of property
Added: svn:keywords
## -0,0 +1 ##
+MidnightBSD=%H
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+text/plain
\ No newline at end of property
Added: trunk/sys/mips/rmi/rmi_mips_exts.h
===================================================================
--- trunk/sys/mips/rmi/rmi_mips_exts.h (rev 0)
+++ trunk/sys/mips/rmi/rmi_mips_exts.h 2018-05-26 21:55:02 UTC (rev 9987)
@@ -0,0 +1,580 @@
+/* $MidnightBSD$ */
+/*-
+ * Copyright (c) 2003-2009 RMI Corporation
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * 3. Neither the name of RMI Corporation, nor the names of its contributors,
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ * RMI_BSD
+ * $FreeBSD: stable/10/sys/mips/rmi/rmi_mips_exts.h 213441 2010-10-05 05:49:38Z jchandra $
+ */
+#ifndef __MIPS_EXTS_H__
+#define __MIPS_EXTS_H__
+
+#define CPU_BLOCKID_IFU 0
+#define CPU_BLOCKID_ICU 1
+#define CPU_BLOCKID_IEU 2
+#define CPU_BLOCKID_LSU 3
+#define CPU_BLOCKID_MMU 4
+#define CPU_BLOCKID_PRF 5
+
+#define LSU_CERRLOG_REGID 9
+
+#if defined(__mips_n64) || defined(__mips_n32)
+static __inline uint64_t
+read_xlr_ctrl_register(int block, int reg)
+{
+ uint64_t res;
+
+ __asm__ __volatile__(
+ ".set push\n\t"
+ ".set noreorder\n\t"
+ "move $9, %1\n\t"
+ ".word 0x71280018\n\t" /* mfcr $8, $9 */
+ "move %0, $8\n\t"
+ ".set pop\n"
+ : "=r" (res) : "r"((block << 8) | reg)
+ : "$8", "$9"
+ );
+ return (res);
+}
+
+static __inline void
+write_xlr_ctrl_register(int block, int reg, uint64_t value)
+{
+ __asm__ __volatile__(
+ ".set push\n\t"
+ ".set noreorder\n\t"
+ "move $8, %0\n"
+ "move $9, %1\n"
+ ".word 0x71280019\n" /* mtcr $8, $9 */
+ ".set pop\n"
+ :
+ : "r" (value), "r" ((block << 8) | reg)
+ : "$8", "$9"
+ );
+}
+
+#else /* !(defined(__mips_n64) || defined(__mips_n32)) */
+
+static __inline uint64_t
+read_xlr_ctrl_register(int block, int reg)
+{
+ uint32_t high, low;
+
+ __asm__ __volatile__(
+ ".set push\n\t"
+ ".set noreorder\n\t"
+ ".set mips64\n\t"
+ "move $9, %2\n"
+ ".word 0x71280018\n" /* "mfcr $8, $9\n" */
+ "dsra32 %0, $8, 0\n\t"
+ "sll %1, $8, 0\n\t"
+ ".set pop"
+ : "=r" (high), "=r"(low)
+ : "r" ((block << 8) | reg)
+ : "$8", "$9");
+
+ return ( (((uint64_t)high) << 32) | low);
+}
+
+static __inline void
+write_xlr_ctrl_register(int block, int reg, uint64_t value)
+{
+ uint32_t low, high;
+ high = value >> 32;
+ low = value & 0xffffffff;
+
+ __asm__ __volatile__(
+ ".set push\n\t"
+ ".set noreorder\n\t"
+ ".set mips64\n\t"
+ "dsll32 $9, %0, 0\n\t"
+ "dsll32 $8, %1, 0\n\t"
+ "dsrl32 $8, $8, 0\n\t"
+ "or $8, $9, $8\n\t"
+ "move $9, %2\n\t"
+ ".word 0x71280019\n\t" /* mtcr $8, $9 */
+ ".set pop\n"
+ : /* No outputs */
+ : "r" (high), "r" (low), "r"((block << 8) | reg)
+ : "$8", "$9");
+}
+#endif /* defined(__mips_n64) || defined(__mips_n32) */
+
+/*
+ * 32 bit read write for c0
+ */
+#define read_c0_register32(reg, sel) \
+({ \
+ uint32_t __rv; \
+ __asm__ __volatile__( \
+ ".set push\n\t" \
+ ".set mips32\n\t" \
+ "mfc0 %0, $%1, %2\n\t" \
+ ".set pop\n" \
+ : "=r" (__rv) : "i" (reg), "i" (sel) ); \
+ __rv; \
+ })
+
+#define write_c0_register32(reg, sel, value) \
+ __asm__ __volatile__( \
+ ".set push\n\t" \
+ ".set mips32\n\t" \
+ "mtc0 %0, $%1, %2\n\t" \
+ ".set pop\n" \
+ : : "r" (value), "i" (reg), "i" (sel) );
+
+#define read_c2_register32(reg, sel) \
+({ \
+ uint32_t __rv; \
+ __asm__ __volatile__( \
+ ".set push\n\t" \
+ ".set mips32\n\t" \
+ "mfc2 %0, $%1, %2\n\t" \
+ ".set pop\n" \
+ : "=r" (__rv) : "i" (reg), "i" (sel) ); \
+ __rv; \
+ })
+
+#define write_c2_register32(reg, sel, value) \
+ __asm__ __volatile__( \
+ ".set push\n\t" \
+ ".set mips32\n\t" \
+ "mtc2 %0, $%1, %2\n\t" \
+ ".set pop\n" \
+ : : "r" (value), "i" (reg), "i" (sel) );
+
+#if defined(__mips_n64) || defined(__mips_n32)
+/*
+ * On 64 bit compilation, the operations are simple
+ */
+#define read_c0_register64(reg, sel) \
+({ \
+ uint64_t __rv; \
+ __asm__ __volatile__( \
+ ".set push\n\t" \
+ ".set mips64\n\t" \
+ "dmfc0 %0, $%1, %2\n\t" \
+ ".set pop\n" \
+ : "=r" (__rv) : "i" (reg), "i" (sel) ); \
+ __rv; \
+ })
+
+#define write_c0_register64(reg, sel, value) \
+ __asm__ __volatile__( \
+ ".set push\n\t" \
+ ".set mips64\n\t" \
+ "dmtc0 %0, $%1, %2\n\t" \
+ ".set pop\n" \
+ : : "r" (value), "i" (reg), "i" (sel) );
+
+#define read_c2_register64(reg, sel) \
+({ \
+ uint64_t __rv; \
+ __asm__ __volatile__( \
+ ".set push\n\t" \
+ ".set mips64\n\t" \
+ "dmfc2 %0, $%1, %2\n\t" \
+ ".set pop\n" \
+ : "=r" (__rv) : "i" (reg), "i" (sel) ); \
+ __rv; \
+ })
+
+#define write_c2_register64(reg, sel, value) \
+ __asm__ __volatile__( \
+ ".set push\n\t" \
+ ".set mips64\n\t" \
+ "dmtc2 %0, $%1, %2\n\t" \
+ ".set pop\n" \
+ : : "r" (value), "i" (reg), "i" (sel) );
+
+#else /* ! (defined(__mips_n64) || defined(__mips_n32)) */
+
+/*
+ * 32 bit compilation, 64 bit values has to split
+ */
+#define read_c0_register64(reg, sel) \
+({ \
+ uint32_t __high, __low; \
+ __asm__ __volatile__( \
+ ".set push\n\t" \
+ ".set noreorder\n\t" \
+ ".set mips64\n\t" \
+ "dmfc0 $8, $%2, %3\n\t" \
+ "dsra32 %0, $8, 0\n\t" \
+ "sll %1, $8, 0\n\t" \
+ ".set pop\n" \
+ : "=r"(__high), "=r"(__low): "i"(reg), "i"(sel) \
+ : "$8"); \
+ ((uint64_t)__high << 32) | __low; \
+})
+
+#define write_c0_register64(reg, sel, value) \
+do { \
+ uint32_t __high = value >> 32; \
+ uint32_t __low = value & 0xffffffff; \
+ __asm__ __volatile__( \
+ ".set push\n\t" \
+ ".set noreorder\n\t" \
+ ".set mips64\n\t" \
+ "dsll32 $8, %1, 0\n\t" \
+ "dsll32 $9, %0, 0\n\t" \
+ "dsrl32 $8, $8, 0\n\t" \
+ "or $8, $8, $9\n\t" \
+ "dmtc0 $8, $%2, %3\n\t" \
+ ".set pop" \
+ :: "r"(__high), "r"(__low), "i"(reg), "i"(sel) \
+ :"$8", "$9"); \
+} while(0)
+
+#define read_c2_register64(reg, sel) \
+({ \
+ uint32_t __high, __low; \
+ __asm__ __volatile__( \
+ ".set push\n\t" \
+ ".set noreorder\n\t" \
+ ".set mips64\n\t" \
+ "dmfc2 $8, $%2, %3\n\t" \
+ "dsra32 %0, $8, 0\n\t" \
+ "sll %1, $8, 0\n\t" \
+ ".set pop\n" \
+ : "=r"(__high), "=r"(__low): "i"(reg), "i"(sel) \
+ : "$8"); \
+ ((uint64_t)__high << 32) | __low; \
+})
+
+#define write_c2_register64(reg, sel, value) \
+do { \
+ uint32_t __high = value >> 32; \
+ uint32_t __low = value & 0xffffffff; \
+ __asm__ __volatile__( \
+ ".set push\n\t" \
+ ".set noreorder\n\t" \
+ ".set mips64\n\t" \
+ "dsll32 $8, %1, 0\n\t" \
+ "dsll32 $9, %0, 0\n\t" \
+ "dsrl32 $8, $8, 0\n\t" \
+ "or $8, $8, $9\n\t" \
+ "dmtc2 $8, $%2, %3\n\t" \
+ ".set pop" \
+ :: "r"(__high), "r"(__low), "i"(reg), "i"(sel) \
+ :"$8", "$9"); \
+} while(0)
+
+#endif /* defined(__mips_n64) || defined(__mips_n32) */
+
+static __inline int
+xlr_cpu_id(void)
+{
+
+ return (read_c0_register32(15, 1) & 0x1f);
+}
+
+static __inline int
+xlr_core_id(void)
+{
+
+ return (xlr_cpu_id() / 4);
+}
+
+static __inline int
+xlr_thr_id(void)
+{
+
+ return (read_c0_register32(15, 1) & 0x3);
+}
+
+/* Additional registers on the XLR */
+#define MIPS_COP_0_OSSCRATCH 22
+#define XLR_CACHELINE_SIZE 32
+
+/* functions to write to and read from the extended
+ * cp0 registers.
+ * EIRR : Extended Interrupt Request Register
+ * cp0 register 9 sel 6
+ * bits 0...7 are same as cause register 8...15
+ * EIMR : Extended Interrupt Mask Register
+ * cp0 register 9 sel 7
+ * bits 0...7 are same as status register 8...15
+ */
+static __inline uint64_t
+read_c0_eirr64(void)
+{
+
+ return (read_c0_register64(9, 6));
+}
+
+static __inline void
+write_c0_eirr64(uint64_t val)
+{
+
+ write_c0_register64(9, 6, val);
+}
+
+static __inline uint64_t
+read_c0_eimr64(void)
+{
+
+ return (read_c0_register64(9, 7));
+}
+
+static __inline void
+write_c0_eimr64(uint64_t val)
+{
+
+ write_c0_register64(9, 7, val);
+}
+
+static __inline int
+xlr_test_and_set(int *lock)
+{
+ int oldval = 0;
+
+ __asm__ __volatile__(
+ ".set push\n"
+ ".set noreorder\n"
+ "move $9, %2\n"
+ "li $8, 1\n"
+ // "swapw $8, $9\n"
+ ".word 0x71280014\n"
+ "move %1, $8\n"
+ ".set pop\n"
+ : "+m"(*lock), "=r"(oldval)
+ : "r"((unsigned long)lock)
+ : "$8", "$9"
+ );
+
+ return (oldval == 0 ? 1 /* success */ : 0 /* failure */);
+}
+
+static __inline uint32_t
+xlr_mfcr(uint32_t reg)
+{
+ uint32_t val;
+
+ __asm__ __volatile__(
+ "move $8, %1\n"
+ ".word 0x71090018\n"
+ "move %0, $9\n"
+ : "=r"(val)
+ : "r"(reg):"$8", "$9");
+
+ return val;
+}
+
+static __inline void
+xlr_mtcr(uint32_t reg, uint32_t val)
+{
+ __asm__ __volatile__(
+ "move $8, %1\n"
+ "move $9, %0\n"
+ ".word 0x71090019\n"
+ :: "r"(val), "r"(reg)
+ : "$8", "$9");
+}
+
+/*
+ * Atomic increment a unsigned int
+ */
+static __inline unsigned int
+xlr_ldaddwu(unsigned int value, unsigned int *addr)
+{
+ __asm__ __volatile__(
+ ".set push\n"
+ ".set noreorder\n"
+ "move $8, %2\n"
+ "move $9, %3\n"
+ ".word 0x71280011\n" /* ldaddwu $8, $9 */
+ "move %0, $8\n"
+ ".set pop\n"
+ : "=&r"(value), "+m"(*addr)
+ : "0"(value), "r" ((unsigned long)addr)
+ : "$8", "$9");
+
+ return (value);
+}
+
+#if defined(__mips_n64)
+static __inline uint32_t
+xlr_paddr_lw(uint64_t paddr)
+{
+
+ paddr |= 0x9800000000000000ULL;
+ return (*(uint32_t *)(uintptr_t)paddr);
+}
+
+static __inline uint64_t
+xlr_paddr_ld(uint64_t paddr)
+{
+
+ paddr |= 0x9800000000000000ULL;
+ return (*(uint64_t *)(uintptr_t)paddr);
+}
+
+#elif defined(__mips_n32)
+static __inline uint32_t
+xlr_paddr_lw(uint64_t paddr)
+{
+ uint32_t val;
+
+ paddr |= 0x9800000000000000ULL;
+ __asm__ __volatile__(
+ ".set push \n\t"
+ ".set mips64 \n\t"
+ "lw %0, 0(%1) \n\t"
+ ".set pop \n"
+ : "=r"(val)
+ : "r"(paddr));
+
+ return (val);
+}
+
+static __inline uint64_t
+xlr_paddr_ld(uint64_t paddr)
+{
+ uint64_t val;
+
+ paddr |= 0x9800000000000000ULL;
+ __asm__ __volatile__(
+ ".set push \n\t"
+ ".set mips64 \n\t"
+ "ld %0, 0(%1) \n\t"
+ ".set pop \n"
+ : "=r"(val)
+ : "r"(paddr));
+
+ return (val);
+}
+
+#else /* o32 compilation */
+static __inline uint32_t
+xlr_paddr_lw(uint64_t paddr)
+{
+ uint32_t addrh, addrl;
+ uint32_t val;
+
+ addrh = 0x98000000 | (paddr >> 32);
+ addrl = paddr & 0xffffffff;
+
+ __asm__ __volatile__(
+ ".set push \n\t"
+ ".set mips64 \n\t"
+ "dsll32 $8, %1, 0 \n\t"
+ "dsll32 $9, %2, 0 \n\t" /* get rid of the */
+ "dsrl32 $9, $9, 0 \n\t" /* sign extend */
+ "or $9, $8, $8 \n\t"
+ "lw %0, 0($9) \n\t"
+ ".set pop \n"
+ : "=r"(val)
+ : "r"(addrh), "r"(addrl)
+ : "$8", "$9");
+
+ return (val);
+}
+
+static __inline uint64_t
+xlr_paddr_ld(uint64_t paddr)
+{
+ uint32_t addrh, addrl;
+ uint32_t valh, vall;
+
+ addrh = 0x98000000 | (paddr >> 32);
+ addrl = paddr & 0xffffffff;
+
+ __asm__ __volatile__(
+ ".set push \n\t"
+ ".set mips64 \n\t"
+ "dsll32 %0, %2, 0 \n\t"
+ "dsll32 %1, %3, 0 \n\t" /* get rid of the */
+ "dsrl32 %1, %1, 0 \n\t" /* sign extend */
+ "or %0, %0, %1 \n\t"
+ "lw %1, 4(%0) \n\t"
+ "lw %0, 0(%0) \n\t"
+ ".set pop \n"
+ : "=&r"(valh), "=&r"(vall)
+ : "r"(addrh), "r"(addrl));
+
+ return (((uint64_t)valh << 32) | vall);
+}
+#endif
+
+/*
+ * XXX: Not really needed in n32 or n64, retain for now
+ */
+#if defined(__mips_n64) || defined(__mips_n32)
+static __inline uint32_t
+xlr_enable_kx(void)
+{
+
+ return (0);
+}
+
+static __inline void
+xlr_restore_kx(uint32_t sr)
+{
+}
+
+#else /* !defined(__mips_n64) && !defined(__mips_n32) */
+/*
+ * o32 compilation, we will disable interrupts and enable
+ * the KX bit so that we can use XKPHYS to access any 40bit
+ * physical address
+ */
+static __inline uint32_t
+xlr_enable_kx(void)
+{
+ uint32_t sr = mips_rd_status();
+
+ mips_wr_status((sr & ~MIPS_SR_INT_IE) | MIPS_SR_KX);
+ return (sr);
+}
+
+static __inline void
+xlr_restore_kx(uint32_t sr)
+{
+
+ mips_wr_status(sr);
+}
+#endif /* defined(__mips_n64) || defined(__mips_n32) */
+
+/*
+ * XLR/XLS processors have maximum 8 cores, and maximum 4 threads
+ * per core
+ */
+#define XLR_MAX_CORES 8
+#define XLR_NTHREADS 4
+
+/*
+ * FreeBSD can be started with few threads and cores turned off,
+ * so have a hardware thread id to FreeBSD cpuid mapping.
+ */
+extern int xlr_ncores;
+extern int xlr_threads_per_core;
+extern uint32_t xlr_hw_thread_mask;
+extern int xlr_cpuid_to_hwtid[];
+extern int xlr_hwtid_to_cpuid[];
+
+#endif
Property changes on: trunk/sys/mips/rmi/rmi_mips_exts.h
___________________________________________________________________
Added: svn:eol-style
## -0,0 +1 ##
+native
\ No newline at end of property
Added: svn:keywords
## -0,0 +1 ##
+MidnightBSD=%H
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+text/plain
\ No newline at end of property
Added: trunk/sys/mips/rmi/rootfs_list.txt
===================================================================
--- trunk/sys/mips/rmi/rootfs_list.txt (rev 0)
+++ trunk/sys/mips/rmi/rootfs_list.txt 2018-05-26 21:55:02 UTC (rev 9987)
@@ -0,0 +1,674 @@
+# $FreeBSD: stable/10/sys/mips/rmi/rootfs_list.txt 267734 2014-06-22 16:48:21Z gavin $
+#
+# This is the list of files that
+# should be in your rootfs (copy it from
+# the build world nfsmount dir. When the rge0
+# driver gets fixed we should be able to start
+# using nfs mount... for now we need to use MD_ROOT
+./.cshrc
+./.profile
+./COPYRIGHT
+./bin
+./bin/cat
+./bin/chflags
+./bin/chio
+./bin/chmod
+./bin/cp
+./bin/csh
+./bin/tcsh
+./bin/date
+./bin/dd
+./bin/df
+./bin/domainname
+./bin/echo
+./bin/ed
+./bin/red
+./bin/expr
+./bin/getfacl
+./bin/hostname
+./bin/kenv
+./bin/kill
+./bin/ln
+./bin/link
+./bin/ls
+./bin/mkdir
+./bin/mv
+./bin/pax
+./bin/pkill
+./bin/pgrep
+./bin/ps
+./bin/pwd
+./bin/rcp
+./bin/realpath
+./bin/rm
+./bin/unlink
+./bin/rmail
+./bin/rmdir
+./bin/setfacl
+./bin/sh
+./bin/sleep
+./bin/stty
+./bin/sync
+./bin/test
+./bin/[
+./bin/uuidgen
+./etc
+./etc/bluetooth
+./etc/bluetooth/hcsecd.conf
+./etc/bluetooth/hosts
+./etc/bluetooth/protocols
+./etc/defaults
+./etc/defaults/bluetooth.device.conf
+./etc/defaults/devfs.rules
+./etc/defaults/periodic.conf
+./etc/defaults/rc.conf
+./etc/devd
+./etc/devd/asus.conf
+./etc/gss
+./etc/gss/mech
+./etc/gss/qop
+./etc/mail
+./etc/mail/mailer.conf
+./etc/mail/freebsd.mc
+./etc/mail/freebsd.cf
+./etc/mail/freebsd.submit.mc
+./etc/mail/freebsd.submit.cf
+./etc/mail/helpfile
+./etc/mail/sendmail.cf
+./etc/mail/submit.cf
+./etc/mail/Makefile
+./etc/mail/README
+./etc/mail/access.sample
+./etc/mail/virtusertable.sample
+./etc/mail/mailertable.sample
+./etc/mail/aliases
+./etc/mtree
+./etc/mtree/BSD.include.dist
+./etc/mtree/BSD.root.dist
+./etc/mtree/BSD.usr.dist
+./etc/mtree/BSD.var.dist
+./etc/mtree/BSD.sendmail.dist
+./etc/mtree/BIND.chroot.dist
+./etc/pam.d
+./etc/pam.d/README
+./etc/pam.d/atrun
+./etc/pam.d/cron
+./etc/pam.d/ftpd
+./etc/pam.d/imap
+./etc/pam.d/kde
+./etc/pam.d/login
+./etc/pam.d/other
+./etc/pam.d/passwd
+./etc/pam.d/pop3
+./etc/pam.d/rsh
+./etc/pam.d/sshd
+./etc/pam.d/su
+./etc/pam.d/system
+./etc/pam.d/telnetd
+./etc/pam.d/xdm
+./etc/pam.d/ftp
+./etc/periodic
+./etc/periodic/daily
+./etc/periodic/daily/100.clean-disks
+./etc/periodic/daily/110.clean-tmps
+./etc/periodic/daily/120.clean-preserve
+./etc/periodic/daily/200.backup-passwd
+./etc/periodic/daily/330.news
+./etc/periodic/daily/400.status-disks
+./etc/periodic/daily/404.status-zfs
+./etc/periodic/daily/405.status-ata-raid
+./etc/periodic/daily/406.status-gmirror
+./etc/periodic/daily/407.status-graid3
+./etc/periodic/daily/408.status-gstripe
+./etc/periodic/daily/409.status-gconcat
+./etc/periodic/daily/420.status-network
+./etc/periodic/daily/450.status-security
+./etc/periodic/daily/999.local
+./etc/periodic/daily/310.accounting
+./etc/periodic/daily/470.status-named
+./etc/periodic/daily/300.calendar
+./etc/periodic/daily/130.clean-msgs
+./etc/periodic/daily/480.status-ntpd
+./etc/periodic/daily/140.clean-rwho
+./etc/periodic/daily/430.status-rwho
+./etc/periodic/daily/150.clean-hoststat
+./etc/periodic/daily/210.backup-aliases
+./etc/periodic/daily/440.status-mailq
+./etc/periodic/daily/460.status-mail-rejects
+./etc/periodic/daily/500.queuerun
+./etc/periodic/monthly
+./etc/periodic/monthly/999.local
+./etc/periodic/monthly/200.accounting
+./etc/periodic/security
+./etc/periodic/security/100.chksetuid
+./etc/periodic/security/200.chkmounts
+./etc/periodic/security/300.chkuid0
+./etc/periodic/security/400.passwdless
+./etc/periodic/security/410.logincheck
+./etc/periodic/security/700.kernelmsg
+./etc/periodic/security/800.loginfail
+./etc/periodic/security/900.tcpwrap
+./etc/periodic/security/security.functions
+./etc/periodic/security/510.ipfdenied
+./etc/periodic/security/500.ipfwdenied
+./etc/periodic/security/550.ipfwlimit
+./etc/periodic/security/520.pfdenied
+./etc/periodic/weekly
+./etc/periodic/weekly/340.noid
+./etc/periodic/weekly/999.local
+./etc/periodic/weekly/310.locate
+./etc/periodic/weekly/320.whatis
+./etc/periodic/weekly/330.catman
+./etc/periodic/weekly/400.status-pkg
+./etc/ppp
+./etc/ppp/ppp.conf
+./etc/rc.d
+./etc/rc.d/DAEMON
+./etc/rc.d/FILESYSTEMS
+./etc/rc.d/LOGIN
+./etc/rc.d/NETWORKING
+./etc/rc.d/SERVERS
+./etc/rc.d/abi
+./etc/rc.d/accounting
+./etc/rc.d/addswap
+./etc/rc.d/adjkerntz
+./etc/rc.d/amd
+./etc/rc.d/apm
+./etc/rc.d/apmd
+./etc/rc.d/archdep
+./etc/rc.d/atm1
+./etc/rc.d/atm2
+./etc/rc.d/atm3
+./etc/rc.d/auditd
+./etc/rc.d/bgfsck
+./etc/rc.d/bluetooth
+./etc/rc.d/bootparams
+./etc/rc.d/bridge
+./etc/rc.d/bthidd
+./etc/rc.d/ccd
+./etc/rc.d/cleanvar
+./etc/rc.d/cleartmp
+./etc/rc.d/cron
+./etc/rc.d/ddb
+./etc/rc.d/defaultroute
+./etc/rc.d/devd
+./etc/rc.d/devfs
+./etc/rc.d/dhclient
+./etc/rc.d/dmesg
+./etc/rc.d/dumpon
+./etc/rc.d/encswap
+./etc/rc.d/faith
+./etc/rc.d/fsck
+./etc/rc.d/ftp-proxy
+./etc/rc.d/ftpd
+./etc/rc.d/gbde
+./etc/rc.d/geli
+./etc/rc.d/geli2
+./etc/rc.d/gssd
+./etc/rc.d/hcsecd
+./etc/rc.d/hostapd
+./etc/rc.d/hostid
+./etc/rc.d/hostid_save
+./etc/rc.d/hostname
+./etc/rc.d/inetd
+./etc/rc.d/initrandom
+./etc/rc.d/ip6addrctl
+./etc/rc.d/ip6fw
+./etc/rc.d/ipfilter
+./etc/rc.d/ipfs
+./etc/rc.d/ipfw
+./etc/rc.d/ipmon
+./etc/rc.d/ipnat
+./etc/rc.d/ipsec
+./etc/rc.d/ipxrouted
+./etc/rc.d/jail
+./etc/rc.d/kadmind
+./etc/rc.d/kerberos
+./etc/rc.d/keyserv
+./etc/rc.d/kldxref
+./etc/rc.d/kpasswdd
+./etc/rc.d/ldconfig
+./etc/rc.d/local
+./etc/rc.d/localpkg
+./etc/rc.d/lockd
+./etc/rc.d/lpd
+./etc/rc.d/mixer
+./etc/rc.d/motd
+./etc/rc.d/mountcritlocal
+./etc/rc.d/mountcritremote
+./etc/rc.d/mountlate
+./etc/rc.d/mdconfig
+./etc/rc.d/mdconfig2
+./etc/rc.d/mountd
+./etc/rc.d/moused
+./etc/rc.d/mroute6d
+./etc/rc.d/mrouted
+./etc/rc.d/msgs
+./etc/rc.d/named
+./etc/rc.d/natd
+./etc/rc.d/netif
+./etc/rc.d/netoptions
+./etc/rc.d/newsyslog
+./etc/rc.d/pf
+./etc/rc.d/nfscbd
+./etc/rc.d/nfsclient
+./etc/rc.d/nfsd
+./etc/rc.d/nfsserver
+./etc/rc.d/nfsuserd
+./etc/rc.d/nisdomain
+./etc/rc.d/nsswitch
+./etc/rc.d/ntpd
+./etc/rc.d/ntpdate
+./etc/rc.d/othermta
+./etc/rc.d/pflog
+./etc/rc.d/pfsync
+./etc/rc.d/powerd
+./etc/rc.d/power_profile
+./etc/rc.d/ppp
+./etc/rc.d/pppoed
+./etc/rc.d/pwcheck
+./etc/rc.d/quota
+./etc/rc.d/random
+./etc/rc.d/rarpd
+./etc/rc.d/resolv
+./etc/rc.d/rfcomm_pppd_server
+./etc/rc.d/root
+./etc/rc.d/route6d
+./etc/rc.d/routed
+./etc/rc.d/routing
+./etc/rc.d/rpcbind
+./etc/rc.d/rtadvd
+./etc/rc.d/rwho
+./etc/rc.d/savecore
+./etc/rc.d/sdpd
+./etc/rc.d/securelevel
+./etc/rc.d/sendmail
+./etc/rc.d/serial
+./etc/rc.d/sppp
+./etc/rc.d/statd
+./etc/rc.d/static_arp
+./etc/rc.d/stf
+./etc/rc.d/swap1
+./etc/rc.d/syscons
+./etc/rc.d/sysctl
+./etc/rc.d/syslogd
+./etc/rc.d/timed
+./etc/rc.d/tmp
+./etc/rc.d/ugidfw
+./etc/rc.d/var
+./etc/rc.d/virecover
+./etc/rc.d/watchdogd
+./etc/rc.d/wpa_supplicant
+./etc/rc.d/ypbind
+./etc/rc.d/yppasswdd
+./etc/rc.d/ypserv
+./etc/rc.d/ypset
+./etc/rc.d/ypupdated
+./etc/rc.d/ypxfrd
+./etc/rc.d/zfs
+./etc/rc.d/zvol
+./etc/rc.d/sshd
+./etc/rc.d/nscd
+./etc/security
+./etc/security/audit_class
+./etc/security/audit_event
+./etc/security/audit_control
+./etc/security/audit_user
+./etc/security/audit_warn
+./etc/ssh
+./etc/ssh/ssh_config
+./etc/ssh/sshd_config
+./etc/ssh/moduli
+./etc/ssl
+./etc/ssl/openssl.cnf
+./etc/crontab
+./etc/devd.conf
+./etc/devfs.conf
+./etc/ddb.conf
+./etc/dhclient.conf
+./etc/disktab
+./etc/fbtab
+./etc/ftpusers
+./etc/gettytab
+./etc/group
+./etc/hosts
+./etc/hosts.allow
+./etc/hosts.equiv
+./etc/inetd.conf
+./etc/libalias.conf
+./etc/login.access
+./etc/login.conf
+./etc/mac.conf
+./etc/motd
+./etc/netconfig
+./etc/network.subr
+./etc/networks
+./etc/newsyslog.conf
+./etc/nsswitch.conf
+./etc/phones
+./etc/profile
+./etc/protocols
+./etc/rc
+./etc/rc.bsdextended
+./etc/rc.firewall
+./etc/rc.firewall6
+./etc/rc.initdiskless
+./etc/rc.sendmail
+./etc/rc.shutdown
+./etc/rc.subr
+./etc/remote
+./etc/rpc
+./etc/services
+./etc/shells
+./etc/sysctl.conf
+./etc/syslog.conf
+./etc/ttys
+./etc/amd.map
+./etc/apmd.conf
+./etc/freebsd-update.conf
+./etc/locate.rc
+./etc/hosts.lpd
+./etc/printcap
+./etc/mail.rc
+./etc/manpath.config
+./etc/ntp.conf
+./etc/nscd.conf
+./etc/portsnap.conf
+./etc/pf.os
+./etc/csh.cshrc
+./etc/csh.login
+./etc/csh.logout
+./etc/regdomain.xml
+./etc/login.conf.db
+./etc/pwd.db
+./etc/netstart
+./etc/pccard_ether
+./etc/rc.suspend
+./etc/rc.resume
+./etc/master.passwd
+./etc/nsmb.conf
+./etc/opieaccess
+./etc/spwd.db
+./etc/passwd
+./etc/dumpdates
+./etc/fstab
+./etc/rc.conf
+./etc/resolv.conf
+./etc/termcap
+./lib
+./lib/geom
+./lib/geom/geom_cache.so
+./lib/geom/geom_concat.so
+./lib/geom/geom_eli.so
+./lib/geom/geom_journal.so
+./lib/geom/geom_label.so
+./lib/geom/geom_mirror.so
+./lib/geom/geom_multipath.so
+./lib/geom/geom_nop.so
+./lib/geom/geom_part.so
+./lib/geom/geom_raid3.so
+./lib/geom/geom_shsec.so
+./lib/geom/geom_stripe.so
+./lib/geom/geom_virstor.so
+./lib/libc.so.7
+./lib/libcrypt.so.5
+./lib/libkvm.so.5
+./lib/libm.so.5
+./lib/libmd.so.5
+./lib/libncurses.so.8
+./lib/libncursesw.so.8
+./lib/libsbuf.so.5
+./lib/libutil.so.8
+./lib/libalias.so.7
+./lib/libalias_cuseeme.so
+./lib/libalias_dummy.so
+./lib/libalias_ftp.so
+./lib/libalias_irc.so
+./lib/libalias_nbt.so
+./lib/libalias_pptp.so
+./lib/libalias_skinny.so
+./lib/libalias_smedia.so
+./lib/libbegemot.so.4
+./lib/libcam.so.5
+./lib/libdevstat.so.7
+./lib/libedit.so.7
+./lib/libbsdxml.so.4
+./lib/libgeom.so.5
+./lib/libipsec.so.4
+./lib/libipx.so.5
+./lib/libjail.so.1
+./lib/libkiconv.so.4
+./lib/libpcap.so.7
+./lib/libthr.so.3
+./lib/libufs.so.5
+./lib/libz.so.5
+./lib/libgcc_s.so.1
+./lib/libreadline.so.8
+./lib/libssp.so.0
+./lib/libcrypto.so.6
+./libexec
+./libexec/ld-elf.so.1
+./libexec/ld-elf.so.1.old
+./sbin
+./sbin/adjkerntz
+./sbin/atacontrol
+./sbin/badsect
+./sbin/bsdlabel
+./sbin/camcontrol
+./sbin/ccdconfig
+./sbin/clri
+./sbin/comcontrol
+./sbin/conscontrol
+./sbin/devd
+./sbin/devfs
+./sbin/dhclient
+./sbin/dhclient-script
+./sbin/dmesg
+./sbin/dump
+./sbin/rdump
+./sbin/dumpfs
+./sbin/dumpon
+./sbin/fdisk
+./sbin/ffsinfo
+./sbin/fsck
+./sbin/fsck_ffs
+./sbin/fsck_ufs
+./sbin/fsck_4.2bsd
+./sbin/fsdb
+./sbin/fsirand
+./sbin/gbde
+./sbin/fsck_msdosfs
+./sbin/geom
+./sbin/gcache
+./sbin/gconcat
+./sbin/geli
+./sbin/gjournal
+./sbin/glabel
+./sbin/gmirror
+./sbin/gmultipath
+./sbin/gnop
+./sbin/gpart
+./sbin/graid3
+./sbin/gshsec
+./sbin/gstripe
+./sbin/gvirstor
+./sbin/ggatec
+./sbin/ggated
+./sbin/ggatel
+./sbin/growfs
+./sbin/gvinum
+./sbin/ifconfig
+./sbin/init
+./sbin/ipf
+./sbin/ipfs
+./sbin/ipfstat
+./sbin/ipftest
+./sbin/ipmon
+./sbin/ipnat
+./sbin/ippool
+./sbin/md5
+./sbin/ipfw
+./sbin/ipresend
+./sbin/iscontrol
+./sbin/kldconfig
+./sbin/kldload
+./sbin/kldstat
+./sbin/kldunload
+./sbin/ldconfig
+./sbin/rmd160
+./sbin/sha1
+./sbin/sha256
+./sbin/mdconfig
+./sbin/mdmfs
+./sbin/mount_mfs
+./sbin/mknod
+./sbin/mksnap_ffs
+./sbin/mount
+./sbin/mount_cd9660
+./sbin/mount_msdosfs
+./sbin/mount_nfs
+./sbin/mount_newnfs
+./sbin/mount_nullfs
+./sbin/mount_udf
+./sbin/mount_unionfs
+./sbin/natd
+./sbin/ddb
+./sbin/newfs
+./sbin/newfs_msdos
+./sbin/nfsiod
+./sbin/nos-tun
+./sbin/pfctl
+./sbin/pflogd
+./sbin/ping
+./sbin/ping6
+./sbin/quotacheck
+./sbin/rcorder
+./sbin/reboot
+./sbin/nextboot
+./sbin/halt
+./sbin/fastboot
+./sbin/fasthalt
+./sbin/recoverdisk
+./sbin/restore
+./sbin/rrestore
+./sbin/route
+./sbin/routed
+./sbin/rtquery
+./sbin/rtsol
+./sbin/savecore
+./sbin/setkey
+./sbin/shutdown
+./sbin/spppcontrol
+./sbin/swapon
+./sbin/swapoff
+./sbin/swapctl
+./sbin/sysctl
+./sbin/tunefs
+./sbin/umount
+./sbin/init.bak
+./var
+./var/crash
+./var/crash/minfree
+./var/db
+./var/db/locate.database
+./var/log
+./var/log/sendmail.st
+./var/named
+./var/named/etc
+./var/named/etc/namedb
+./var/named/etc/namedb/master
+./var/named/etc/namedb/master/empty.db
+./var/named/etc/namedb/master/localhost-forward.db
+./var/named/etc/namedb/master/localhost-reverse.db
+./var/named/etc/namedb/named.conf
+./var/named/etc/namedb/named.root
+./var/yp
+./var/yp/Makefile.dist
+./var/run
+./var/cron
+./var/cron/tabs
+./root
+./root/.k5login
+./root/.profile
+./root/.cshrc
+./root/.login
+./list
+./dev
+./usr
+./usr/sbin
+./usr/sbin/newsyslog
+./usr/sbin/syslogd
+./usr/sbin/ip6addrctl
+./usr/sbin/sendmail
+./usr/sbin/cron
+./usr/lib
+./usr/lib/libpam.so.5
+./usr/lib/libpam.so
+./usr/lib/pam_opie.so.5
+./usr/lib/libbsm.so.3
+./usr/lib/libbsm.so
+./usr/lib/pam_chroot.so.5
+./usr/lib/pam_tacplus.so.5
+./usr/lib/pam_ssh.so.5
+./usr/lib/pam_self.so.5
+./usr/lib/pam_securetty.so.5
+./usr/lib/pam_rootok.so.5
+./usr/lib/pam_rhosts.so.5
+./usr/lib/pam_radius.so.5
+./usr/lib/pam_permit.so.5
+./usr/lib/pam_passwdqc.so.5
+./usr/lib/libcom_err.so.5
+./usr/lib/libcom_err.so
+./usr/lib/pam_opieaccess.so.5
+./usr/lib/pam_nologin.so.5
+./usr/lib/libc.so.7
+./usr/lib/pam_login_access.so.5
+./usr/lib/pam_lastlog.so.5
+./usr/lib/pam_ksu.so.5
+./usr/lib/pam_krb5.so.5
+./usr/lib/pam_guest.so.5
+./usr/lib/pam_group.so.5
+./usr/lib/pam_ftpusers.so.5
+./usr/lib/pam_exec.so.5
+./usr/lib/pam_echo.so.5
+./usr/lib/pam_deny.so.5
+./usr/lib/pam_unix.so.5
+./usr/lib/pam_chroot.so
+./usr/lib/libopie.so
+./usr/lib/pam_deny.so
+./usr/lib/pam_echo.so
+./usr/lib/pam_exec.so
+./usr/lib/pam_ftpusers.so
+./usr/lib/pam_group.so
+./usr/lib/pam_guest.so
+./usr/lib/pam_krb5.so
+./usr/lib/pam_ksu.so
+./usr/lib/pam_lastlog.so
+./usr/lib/pam_login_access.so
+./usr/lib/pam_nologin.so
+./usr/lib/pam_opie.so
+./usr/lib/pam_opieaccess.so
+./usr/lib/pam_passwdqc.so
+./usr/lib/pam_permit.so
+./usr/lib/pam_radius.so
+./usr/lib/pam_rhosts.so
+./usr/lib/pam_rootok.so
+./usr/lib/pam_securetty.so
+./usr/lib/pam_self.so
+./usr/lib/pam_ssh.so
+./usr/lib/pam_tacplus.so
+./usr/lib/pam_unix.so
+./usr/lib/libmd.so.5
+./usr/lib/libbz2.so.4
+./usr/lib/libgnuregex.so.5
+./usr/lib/libypclnt.so.4
+./usr/bin
+./usr/bin/mktemp
+./usr/bin/login
+./usr/bin/uname
+./usr/bin/awk
+./usr/bin/logger
+./usr/bin/grep
+./usr/bin/ftp
+./usr/libexec
+./usr/libexec/getty
Property changes on: trunk/sys/mips/rmi/rootfs_list.txt
___________________________________________________________________
Added: mnbsd:nokeywords
## -0,0 +1 ##
+MidnightBSD=%H
\ No newline at end of property
Added: svn:eol-style
## -0,0 +1 ##
+native
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+text/plain
\ No newline at end of property
Added: trunk/sys/mips/rmi/std.xlr
===================================================================
--- trunk/sys/mips/rmi/std.xlr (rev 0)
+++ trunk/sys/mips/rmi/std.xlr 2018-05-26 21:55:02 UTC (rev 9987)
@@ -0,0 +1,5 @@
+# $FreeBSD: stable/10/sys/mips/rmi/std.xlr 217636 2011-01-20 12:45:29Z jchandra $
+files "../rmi/files.xlr"
+
+cpu CPU_RMI
+option NOFPU
Property changes on: trunk/sys/mips/rmi/std.xlr
___________________________________________________________________
Added: mnbsd:nokeywords
## -0,0 +1 ##
+MidnightBSD=%H
\ No newline at end of property
Added: trunk/sys/mips/rmi/tick.c
===================================================================
--- trunk/sys/mips/rmi/tick.c (rev 0)
+++ trunk/sys/mips/rmi/tick.c 2018-05-26 21:55:02 UTC (rev 9987)
@@ -0,0 +1,378 @@
+/* $MidnightBSD$ */
+/*-
+ * Copyright (c) 2006-2007 Bruce M. Simpson.
+ * Copyright (c) 2003-2004 Juli Mallett.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ */
+
+/*
+ * Simple driver for the 32-bit interval counter built in to all
+ * MIPS32 CPUs.
+ */
+
+#include <sys/cdefs.h>
+__FBSDID("$FreeBSD: stable/10/sys/mips/rmi/tick.c 265999 2014-05-14 01:35:43Z ian $");
+
+#include <sys/param.h>
+#include <sys/systm.h>
+#include <sys/sysctl.h>
+#include <sys/bus.h>
+#include <sys/kernel.h>
+#include <sys/module.h>
+#include <sys/rman.h>
+#include <sys/power.h>
+#include <sys/smp.h>
+#include <sys/time.h>
+#include <sys/timeet.h>
+#include <sys/timetc.h>
+
+#include <machine/hwfunc.h>
+#include <machine/clock.h>
+#include <machine/locore.h>
+#include <machine/md_var.h>
+#include <machine/intr_machdep.h>
+#include <mips/rmi/interrupt.h>
+
+uint64_t counter_freq;
+
+struct timecounter *platform_timecounter;
+
+static DPCPU_DEFINE(uint32_t, cycles_per_tick);
+static uint32_t cycles_per_usec;
+
+static DPCPU_DEFINE(volatile uint32_t, counter_upper);
+static DPCPU_DEFINE(volatile uint32_t, counter_lower_last);
+static DPCPU_DEFINE(uint32_t, compare_ticks);
+static DPCPU_DEFINE(uint32_t, lost_ticks);
+
+struct clock_softc {
+ int intr_rid;
+ struct resource *intr_res;
+ void *intr_handler;
+ struct timecounter tc;
+ struct eventtimer et;
+};
+static struct clock_softc *softc;
+
+/*
+ * Device methods
+ */
+static int clock_probe(device_t);
+static void clock_identify(driver_t *, device_t);
+static int clock_attach(device_t);
+static unsigned counter_get_timecount(struct timecounter *tc);
+
+void
+mips_timer_early_init(uint64_t clock_hz)
+{
+ /* Initialize clock early so that we can use DELAY sooner */
+ counter_freq = clock_hz;
+ cycles_per_usec = (clock_hz / (1000 * 1000));
+}
+
+void
+platform_initclocks(void)
+{
+
+ if (platform_timecounter != NULL)
+ tc_init(platform_timecounter);
+}
+
+static uint64_t
+tick_ticker(void)
+{
+ uint64_t ret;
+ uint32_t ticktock;
+ uint32_t t_lower_last, t_upper;
+
+ /*
+ * Disable preemption because we are working with cpu specific data.
+ */
+ critical_enter();
+
+ /*
+ * Note that even though preemption is disabled, interrupts are
+ * still enabled. In particular there is a race with clock_intr()
+ * reading the values of 'counter_upper' and 'counter_lower_last'.
+ *
+ * XXX this depends on clock_intr() being executed periodically
+ * so that 'counter_upper' and 'counter_lower_last' are not stale.
+ */
+ do {
+ t_upper = DPCPU_GET(counter_upper);
+ t_lower_last = DPCPU_GET(counter_lower_last);
+ } while (t_upper != DPCPU_GET(counter_upper));
+
+ ticktock = mips_rd_count();
+
+ critical_exit();
+
+ /* COUNT register wrapped around */
+ if (ticktock < t_lower_last)
+ t_upper++;
+
+ ret = ((uint64_t)t_upper << 32) | ticktock;
+ return (ret);
+}
+
+void
+mips_timer_init_params(uint64_t platform_counter_freq, int double_count)
+{
+
+ /*
+ * XXX: Do not use printf here: uart code 8250 may use DELAY so this
+ * function should be called before cninit.
+ */
+ counter_freq = platform_counter_freq;
+ /*
+ * XXX: Some MIPS32 cores update the Count register only every two
+ * pipeline cycles.
+ * We know this because of status registers in CP0, make it automatic.
+ */
+ if (double_count != 0)
+ counter_freq /= 2;
+
+ cycles_per_usec = counter_freq / (1 * 1000 * 1000);
+ set_cputicker(tick_ticker, counter_freq, 1);
+}
+
+static int
+sysctl_machdep_counter_freq(SYSCTL_HANDLER_ARGS)
+{
+ int error;
+ uint64_t freq;
+
+ if (softc == NULL)
+ return (EOPNOTSUPP);
+ freq = counter_freq;
+ error = sysctl_handle_64(oidp, &freq, sizeof(freq), req);
+ if (error == 0 && req->newptr != NULL) {
+ counter_freq = freq;
+ softc->et.et_frequency = counter_freq;
+ softc->tc.tc_frequency = counter_freq;
+ }
+ return (error);
+}
+
+SYSCTL_PROC(_machdep, OID_AUTO, counter_freq, CTLTYPE_U64 | CTLFLAG_RW,
+ NULL, 0, sysctl_machdep_counter_freq, "QU",
+ "Timecounter frequency in Hz");
+
+static unsigned
+counter_get_timecount(struct timecounter *tc)
+{
+
+ return (mips_rd_count());
+}
+
+/*
+ * Wait for about n microseconds (at least!).
+ */
+void
+DELAY(int n)
+{
+ uint32_t cur, last, delta, usecs;
+
+ /*
+ * This works by polling the timer and counting the number of
+ * microseconds that go by.
+ */
+ last = mips_rd_count();
+ delta = usecs = 0;
+
+ while (n > usecs) {
+ cur = mips_rd_count();
+
+ /* Check to see if the timer has wrapped around. */
+ if (cur < last)
+ delta += cur + (0xffffffff - last) + 1;
+ else
+ delta += cur - last;
+
+ last = cur;
+
+ if (delta >= cycles_per_usec) {
+ usecs += delta / cycles_per_usec;
+ delta %= cycles_per_usec;
+ }
+ }
+}
+
+static int
+clock_start(struct eventtimer *et, sbintime_t first, sbintime_t period)
+{
+ uint32_t fdiv, div, next;
+
+ if (period != 0)
+ div = (et->et_frequency * period) >> 32;
+ else
+ div = 0;
+ if (first != 0)
+ fdiv = (et->et_frequency * first) >> 32;
+ else
+ fdiv = div;
+ DPCPU_SET(cycles_per_tick, div);
+ next = mips_rd_count() + fdiv;
+ DPCPU_SET(compare_ticks, next);
+ mips_wr_compare(next);
+ return (0);
+}
+
+static int
+clock_stop(struct eventtimer *et)
+{
+
+ DPCPU_SET(cycles_per_tick, 0);
+ mips_wr_compare(0xffffffff);
+ return (0);
+}
+
+/*
+ * Device section of file below
+ */
+static int
+clock_intr(void *arg)
+{
+ struct clock_softc *sc = (struct clock_softc *)arg;
+ uint32_t cycles_per_tick;
+ uint32_t count, compare_last, compare_next, lost_ticks;
+
+ cycles_per_tick = DPCPU_GET(cycles_per_tick);
+ /*
+ * Set next clock edge.
+ */
+ count = mips_rd_count();
+ compare_last = DPCPU_GET(compare_ticks);
+ if (cycles_per_tick > 0) {
+ compare_next = count + cycles_per_tick;
+ DPCPU_SET(compare_ticks, compare_next);
+ mips_wr_compare(compare_next);
+ } else /* In one-shot mode timer should be stopped after the event. */
+ mips_wr_compare(0xffffffff);
+
+ /* COUNT register wrapped around */
+ if (count < DPCPU_GET(counter_lower_last)) {
+ DPCPU_SET(counter_upper, DPCPU_GET(counter_upper) + 1);
+ }
+ DPCPU_SET(counter_lower_last, count);
+
+ if (cycles_per_tick > 0) {
+
+ /*
+ * Account for the "lost time" between when the timer interrupt
+ * fired and when 'clock_intr' actually started executing.
+ */
+ lost_ticks = DPCPU_GET(lost_ticks);
+ lost_ticks += count - compare_last;
+
+ /*
+ * If the COUNT and COMPARE registers are no longer in sync
+ * then make up some reasonable value for the 'lost_ticks'.
+ *
+ * This could happen, for e.g., after we resume normal
+ * operations after exiting the debugger.
+ */
+ if (lost_ticks > 2 * cycles_per_tick)
+ lost_ticks = cycles_per_tick;
+
+ while (lost_ticks >= cycles_per_tick) {
+ if (sc->et.et_active)
+ sc->et.et_event_cb(&sc->et, sc->et.et_arg);
+ lost_ticks -= cycles_per_tick;
+ }
+ DPCPU_SET(lost_ticks, lost_ticks);
+ }
+ if (sc->et.et_active)
+ sc->et.et_event_cb(&sc->et, sc->et.et_arg);
+ return (FILTER_HANDLED);
+}
+
+static int
+clock_probe(device_t dev)
+{
+
+ if (device_get_unit(dev) != 0)
+ panic("can't attach more clocks");
+
+ device_set_desc(dev, "Generic MIPS32 ticker");
+ return (BUS_PROBE_NOWILDCARD);
+}
+
+static void
+clock_identify(driver_t * drv, device_t parent)
+{
+
+ BUS_ADD_CHILD(parent, 0, "clock", 0);
+}
+
+static int
+clock_attach(device_t dev)
+{
+ struct clock_softc *sc;
+
+ softc = sc = device_get_softc(dev);
+ cpu_establish_hardintr("compare", clock_intr, NULL,
+ sc, IRQ_TIMER, INTR_TYPE_CLK, &sc->intr_handler);
+
+ sc->tc.tc_get_timecount = counter_get_timecount;
+ sc->tc.tc_counter_mask = 0xffffffff;
+ sc->tc.tc_frequency = counter_freq;
+ sc->tc.tc_name = "MIPS32";
+ sc->tc.tc_quality = 800;
+ sc->tc.tc_priv = sc;
+ tc_init(&sc->tc);
+ sc->et.et_name = "MIPS32";
+ sc->et.et_flags = ET_FLAGS_PERIODIC | ET_FLAGS_ONESHOT |
+ ET_FLAGS_PERCPU;
+ sc->et.et_quality = 800;
+ sc->et.et_frequency = counter_freq;
+ sc->et.et_min_period = 0x00004000LLU; /* To be safe. */
+ sc->et.et_max_period = (0xfffffffeLLU << 32) / sc->et.et_frequency;
+ sc->et.et_start = clock_start;
+ sc->et.et_stop = clock_stop;
+ sc->et.et_priv = sc;
+ et_register(&sc->et);
+ return (0);
+}
+
+static device_method_t clock_methods[] = {
+ /* Device interface */
+ DEVMETHOD(device_probe, clock_probe),
+ DEVMETHOD(device_identify, clock_identify),
+ DEVMETHOD(device_attach, clock_attach),
+ DEVMETHOD(device_detach, bus_generic_detach),
+ DEVMETHOD(device_shutdown, bus_generic_shutdown),
+
+ {0, 0}
+};
+
+static driver_t clock_driver = {
+ "clock",
+ clock_methods,
+ sizeof(struct clock_softc),
+};
+
+static devclass_t clock_devclass;
+
+DRIVER_MODULE(clock, nexus, clock_driver, clock_devclass, 0, 0);
Property changes on: trunk/sys/mips/rmi/tick.c
___________________________________________________________________
Added: svn:eol-style
## -0,0 +1 ##
+native
\ No newline at end of property
Added: svn:keywords
## -0,0 +1 ##
+MidnightBSD=%H
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+text/plain
\ No newline at end of property
Added: trunk/sys/mips/rmi/uart_bus_xlr_iodi.c
===================================================================
--- trunk/sys/mips/rmi/uart_bus_xlr_iodi.c (rev 0)
+++ trunk/sys/mips/rmi/uart_bus_xlr_iodi.c 2018-05-26 21:55:02 UTC (rev 9987)
@@ -0,0 +1,81 @@
+/* $MidnightBSD$ */
+/*-
+ * Copyright (c) 2006 Raza Microelectronics
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+ * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+ * IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
+ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ */
+
+#include <sys/cdefs.h>
+__FBSDID("$FreeBSD: stable/10/sys/mips/rmi/uart_bus_xlr_iodi.c 202175 2010-01-12 21:36:08Z imp $");
+
+#include <sys/param.h>
+#include <sys/systm.h>
+#include <sys/bus.h>
+#include <sys/kernel.h>
+#include <sys/module.h>
+#include <sys/lock.h>
+#include <sys/mutex.h>
+
+#include <machine/bus.h>
+#include <sys/rman.h>
+#include <machine/resource.h>
+#include <mips/rmi/iomap.h>
+#include <dev/uart/uart.h>
+#include <dev/uart/uart_bus.h>
+#include <dev/uart/uart_cpu.h>
+
+static int uart_iodi_probe(device_t dev);
+
+static device_method_t uart_iodi_methods[] = {
+ /* Device interface */
+ DEVMETHOD(device_probe, uart_iodi_probe),
+ DEVMETHOD(device_attach, uart_bus_attach),
+ DEVMETHOD(device_detach, uart_bus_detach),
+ {0, 0}
+};
+
+static driver_t uart_iodi_driver = {
+ uart_driver_name,
+ uart_iodi_methods,
+ sizeof(struct uart_softc),
+};
+
+
+extern SLIST_HEAD(uart_devinfo_list, uart_devinfo) uart_sysdevs;
+static int
+uart_iodi_probe(device_t dev)
+{
+ struct uart_softc *sc;
+ sc = device_get_softc(dev);
+ sc->sc_sysdev = SLIST_FIRST(&uart_sysdevs);
+ sc->sc_class = &uart_ns8250_class;
+ bcopy(&sc->sc_sysdev->bas, &sc->sc_bas, sizeof(sc->sc_bas));
+ sc->sc_sysdev->bas.bst = rmi_bus_space;
+ sc->sc_sysdev->bas.bsh = MIPS_PHYS_TO_KSEG1(XLR_UART0ADDR);
+ sc->sc_bas.bst = rmi_bus_space;
+ sc->sc_bas.bsh = MIPS_PHYS_TO_KSEG1(XLR_UART0ADDR);
+ /* regshft = 2, rclk = 66000000, rid = 0, chan = 0 */
+ return (uart_bus_probe(dev, 2, 66000000, 0, 0));
+}
+
+DRIVER_MODULE(uart, iodi, uart_iodi_driver, uart_devclass, 0, 0);
Property changes on: trunk/sys/mips/rmi/uart_bus_xlr_iodi.c
___________________________________________________________________
Added: svn:eol-style
## -0,0 +1 ##
+native
\ No newline at end of property
Added: svn:keywords
## -0,0 +1 ##
+MidnightBSD=%H
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+text/plain
\ No newline at end of property
Added: trunk/sys/mips/rmi/uart_cpu_mips_xlr.c
===================================================================
--- trunk/sys/mips/rmi/uart_cpu_mips_xlr.c (rev 0)
+++ trunk/sys/mips/rmi/uart_cpu_mips_xlr.c 2018-05-26 21:55:02 UTC (rev 9987)
@@ -0,0 +1,85 @@
+/* $MidnightBSD$ */
+/*-
+ * Copyright (c) 2006 Wojciech A. Koszek <wkoszek at FreeBSD.org>
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ * $Id: uart_cpu_mips_xlr.c,v 1.5 2008-07-16 20:22:39 jayachandranc Exp $
+ */
+/*
+ * Skeleton of this file was based on respective code for ARM
+ * code written by Olivier Houchard.
+ */
+/*
+ * XLRMIPS: This file is hacked from arm/...
+ */
+#include "opt_uart.h"
+
+#include <sys/cdefs.h>
+__FBSDID("$FreeBSD: stable/10/sys/mips/rmi/uart_cpu_mips_xlr.c 202175 2010-01-12 21:36:08Z imp $");
+
+#include <sys/param.h>
+#include <sys/systm.h>
+#include <sys/bus.h>
+#include <sys/cons.h>
+
+#include <machine/bus.h>
+
+#include <dev/uart/uart.h>
+#include <dev/uart/uart_cpu.h>
+#include <sys/kdb.h>
+#include <sys/kernel.h>
+#include <sys/lock.h>
+#include <sys/mutex.h>
+#include <mips/rmi/iomap.h>
+
+bus_space_tag_t uart_bus_space_io;
+bus_space_tag_t uart_bus_space_mem;
+
+int
+uart_cpu_eqres(struct uart_bas *b1, struct uart_bas *b2)
+{
+ return ((b1->bsh == b2->bsh && b1->bst == b2->bst) ? 1 : 0);
+}
+
+
+int
+uart_cpu_getdev(int devtype, struct uart_devinfo *di)
+{
+ di->ops = uart_getops(&uart_ns8250_class);
+ di->bas.chan = 0;
+ di->bas.bst = rmi_bus_space;
+ di->bas.bsh = MIPS_PHYS_TO_KSEG1(XLR_UART0ADDR);
+
+ di->bas.regshft = 2;
+ /* divisor = rclk / (baudrate * 16); */
+ di->bas.rclk = 66000000;
+ di->baudrate = 0;
+ di->databits = 8;
+ di->stopbits = 1;
+ di->parity = UART_PARITY_NONE;
+
+ uart_bus_space_io = NULL;
+ uart_bus_space_mem = rmi_bus_space;
+ return (0);
+}
Property changes on: trunk/sys/mips/rmi/uart_cpu_mips_xlr.c
___________________________________________________________________
Added: svn:eol-style
## -0,0 +1 ##
+native
\ No newline at end of property
Added: svn:keywords
## -0,0 +1 ##
+MidnightBSD=%H
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+text/plain
\ No newline at end of property
Added: trunk/sys/mips/rmi/xlr_csum_nocopy.S
===================================================================
--- trunk/sys/mips/rmi/xlr_csum_nocopy.S (rev 0)
+++ trunk/sys/mips/rmi/xlr_csum_nocopy.S 2018-05-26 21:55:02 UTC (rev 9987)
@@ -0,0 +1,218 @@
+/* $MidnightBSD$ */
+#include <machine/asm.h>
+
+
+/*
+ * a0: source address
+ * a1: length of the area to checksum
+ * a2: partial checksum
+ * a3: dst
+ */
+
+#define src a0
+#define dst a3
+#define sum v0
+
+ .text
+ .set noreorder
+
+ .macro CSUM_BIGCHUNK_AND_COPY offset
+ pref 0, (\offset+0x0)(a0)
+ ld t0, (\offset+0x00)(a0)
+ ld t1, (\offset+0x08)(a0)
+ .word 0x70481038 /*daddwc v0, v0, t0 */
+ .word 0x70491038 /*daddwc v0, v0, t1 */
+ ld t0, (\offset + 0x10)(a0)
+ ld t1, (\offset + 0x18)(a0)
+ .word 0x70481038 /* daddwc v0, v0, t0 */
+ .word 0x70491038 /*daddwc v0, v0, t1 */
+ .endm
+
+small_csumcpy: /* unknown src alignment and < 8 bytes to go */
+ move a1, t2
+
+ andi t0, a1, 4
+ beqz t0, 1f
+ andi t0, a1, 2
+
+ ulw t1, (src) /* Still a full word to go */
+ daddiu src, 4
+ .word 0x70491038 /*daddwc v0, v0, t1 */
+
+1: move t1, zero
+ beqz t0, 1f
+ andi t0, a1, 1
+
+ ulhu t1, (src) /* Still a halfword to go */
+ daddiu src, 2
+
+1: beqz t0, 1f
+ sll t1, t1, 16
+
+ lbu t2, (src)
+ nop
+
+#ifdef __MIPSEB__
+ sll t2, t2, 8
+#endif
+ or t1, t2
+
+1: .word 0x70491038 /*daddwc v0, v0, t1 */
+
+ .word 0x70461038 /*daddwc v0, v0, a2 */
+ .word 0x70401038 /*daddwc v0, v0, $0 */
+
+ /* Ideally at this point of time the status flag must be cleared */
+
+ dsll32 v1, sum, 0
+ .word 0x70431038 /*daddwc v0, v0, v1 */
+ dsrl32 sum, sum, 0
+ .word 0x70401038 /*daddwc v0, v0, zero */
+
+ /* fold the checksum */
+ sll v1, sum, 16
+ addu sum, v1
+ sltu v1, sum, v1
+ srl sum, sum, 16
+ addu sum, v1
+1:
+ .set reorder
+ jr ra
+ .set noreorder
+
+/* ------------------------------------------------------------------ */
+
+ .align 5
+LEAF(xlr_csum_partial_nocopy)
+ move sum, zero
+ move t7, zero
+
+ sltiu t8, a1, 0x8
+ bnez t8, small_csumcpy /* < 8 bytes to copy */
+ move t2, a1
+
+ beqz a1, out
+ andi t7, src, 0x1 /* odd buffer? */
+
+hword_align:
+ beqz t7, word_align
+ andi t8, src, 0x2
+
+ lbu t0, (src)
+ dsubu a1, a1, 0x1
+ .word 0x70481038 /*daddwc v0, v0, t0 */
+ daddu src, src, 0x1
+ andi t8, src, 0x2
+
+word_align:
+ beqz t8, dword_align
+ sltiu t8, a1, 56
+
+ lhu t0, (src)
+ dsubu a1, a1, 0x2
+ .word 0x70481038 /*daddwc v0, v0, t0 */
+ sltiu t8, a1, 56
+ daddu src, src, 0x2
+
+dword_align:
+ bnez t8, do_end_words
+ move t8, a1
+
+ andi t8, src, 0x4
+ beqz t8, qword_align
+ andi t8, src, 0x8
+
+ lw t0, 0x00(src)
+ dsubu a1, a1, 0x4
+ .word 0x70481038 /*daddwc v0, v0, t0 */
+ daddu src, src, 0x4
+ andi t8, src, 0x8
+
+qword_align:
+ beqz t8, oword_align
+ andi t8, src, 0x10
+
+ ld t0, 0x00(src)
+ dsubu a1, a1, 0x8
+ .word 0x70481038 /*daddwc v0, v0, t0 */
+ daddu src, src, 0x8
+ andi t8, src, 0x10
+
+oword_align:
+ beqz t8, begin_movement
+ dsrl t8, a1, 0x7
+
+ ld t3, 0x08(src)
+ ld t0, 0x00(src)
+ .word 0x704b1038 /*daddwc v0, v0, t3 */
+ .word 0x70481038 /*daddwc v0, v0, t0 */
+ dsubu a1, a1, 0x10
+ daddu src, src, 0x10
+ dsrl t8, a1, 0x7
+
+begin_movement:
+ beqz t8, 1f
+ andi t2, a1, 0x40
+
+move_128bytes:
+ pref 0, 0x20(a0)
+ pref 0, 0x40(a0)
+ pref 0, 0x60(a0)
+ CSUM_BIGCHUNK_AND_COPY(0x00)
+ CSUM_BIGCHUNK_AND_COPY(0x20)
+ CSUM_BIGCHUNK_AND_COPY(0x40)
+ CSUM_BIGCHUNK_AND_COPY(0x60)
+ dsubu t8, t8, 0x01
+ bnez t8, move_128bytes /* flag */
+ daddu src, src, 0x80
+
+1:
+ beqz t2, 1f
+ andi t2, a1, 0x20
+
+move_64bytes:
+ pref 0, 0x20(a0)
+ pref 0, 0x40(a0)
+ CSUM_BIGCHUNK_AND_COPY(0x00)
+ CSUM_BIGCHUNK_AND_COPY(0x20)
+ daddu src, src, 0x40
+
+1:
+ beqz t2, do_end_words
+ andi t8, a1, 0x1c
+
+move_32bytes:
+ pref 0, 0x20(a0)
+ CSUM_BIGCHUNK_AND_COPY(0x00)
+ andi t8, a1, 0x1c
+ daddu src, src, 0x20
+
+do_end_words:
+ beqz t8, maybe_end_cruft
+ dsrl t8, t8, 0x2
+
+end_words:
+ lw t0, (src)
+ dsubu t8, t8, 0x1
+ .word 0x70481038 /*daddwc v0, v0, t0 */
+ bnez t8, end_words
+ daddu src, src, 0x4
+
+maybe_end_cruft:
+ andi t2, a1, 0x3
+
+small_memcpy:
+ j small_csumcpy; move a1, t2
+ beqz t2, out
+ move a1, t2
+
+end_bytes:
+ lb t0, (src)
+ dsubu a1, a1, 0x1
+ bnez a2, end_bytes
+ daddu src, src, 0x1
+
+out:
+ jr ra
+ move v0, sum
+ END(xlr_csum_partial_nocopy)
Property changes on: trunk/sys/mips/rmi/xlr_csum_nocopy.S
___________________________________________________________________
Added: svn:eol-style
## -0,0 +1 ##
+native
\ No newline at end of property
Added: svn:keywords
## -0,0 +1 ##
+MidnightBSD=%H
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+text/plain
\ No newline at end of property
Added: trunk/sys/mips/rmi/xlr_i2c.c
===================================================================
--- trunk/sys/mips/rmi/xlr_i2c.c (rev 0)
+++ trunk/sys/mips/rmi/xlr_i2c.c 2018-05-26 21:55:02 UTC (rev 9987)
@@ -0,0 +1,407 @@
+/* $MidnightBSD$ */
+/*-
+ * Copyright (c) 2003-2009 RMI Corporation
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * 3. Neither the name of RMI Corporation, nor the names of its contributors,
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ * RMI_BSD */
+
+#include <sys/cdefs.h>
+__FBSDID("$FreeBSD: stable/10/sys/mips/rmi/xlr_i2c.c 241844 2012-10-22 03:00:37Z eadler $");
+
+/*
+ * I2C driver for the Palm-BK3220 I2C Host adapter on the RMI XLR.
+ */
+
+#include <sys/param.h>
+#include <sys/systm.h>
+#include <sys/kernel.h>
+#include <sys/lock.h>
+#include <sys/module.h>
+#include <sys/mutex.h>
+#include <sys/bus.h>
+#include <sys/rman.h>
+
+
+#include <dev/iicbus/iiconf.h>
+#include <dev/iicbus/iicbus.h>
+
+#include <mips/rmi/board.h>
+#include <mips/rmi/iomap.h>
+#include <mips/include/resource.h>
+
+#include "iicbus_if.h"
+
+/* XLR I2C REGISTERS */
+#define XLR_I2C_CFG 0x00
+#define XLR_I2C_CLKDIV 0x01
+#define XLR_I2C_DEVADDR 0x02
+#define XLR_I2C_ADDR 0x03
+#define XLR_I2C_DATAOUT 0x04
+#define XLR_I2C_DATAIN 0x05
+#define XLR_I2C_STATUS 0x06
+#define XLR_I2C_STARTXFR 0x07
+#define XLR_I2C_BYTECNT 0x08
+#define XLR_I2C_HDSTATIM 0x09
+
+/* XLR I2C REGISTERS FLAGS */
+#define XLR_I2C_BUS_BUSY 0x01
+#define XLR_I2C_SDOEMPTY 0x02
+#define XLR_I2C_RXRDY 0x04
+#define XLR_I2C_ACK_ERR 0x08
+#define XLR_I2C_ARB_STARTERR 0x30
+
+/* Register Programming Values!! Change as required */
+#define XLR_I2C_CFG_ADDR 0xF8 /* 8-Bit dev Addr + POR Values */
+#define XLR_I2C_CFG_NOADDR 0xFA /* 8-Bit reg Addr + POR Values : No dev addr */
+#define XLR_I2C_STARTXFR_ND 0x02 /* No data , only addr */
+#define XLR_I2C_STARTXFR_RD 0x01 /* Read */
+#define XLR_I2C_STARTXFR_WR 0x00 /* Write */
+#define XLR_I2C_CLKDIV_DEF 0x14A /* 0x00000052 */
+#define XLR_I2C_HDSTATIM_DEF 0x107 /* 0x00000000 */
+
+#define MAXTIME 0x10000
+#define ARIZONA_I2C_BUS 1
+
+static devclass_t xlr_i2c_devclass;
+
+/*
+ * Device methods
+ */
+static int xlr_i2c_probe(device_t);
+static int xlr_i2c_attach(device_t);
+static int xlr_i2c_detach(device_t);
+
+static int xlr_i2c_start(device_t dev, u_char slave, int timeout);
+static int xlr_i2c_stop(device_t dev);
+static int xlr_i2c_read(device_t dev, char *buf, int len, int *read, int last, int delay);
+static int xlr_i2c_write(device_t dev, const char *buf, int len, int *sent, int timeout);
+static int xlr_i2c_callback(device_t dev, int index, caddr_t data);
+static int xlr_i2c_repeated_start(device_t dev, u_char slave, int timeout);
+static int xlr_i2c_transfer(device_t bus, struct iic_msg *msgs, uint32_t nmsgs);
+
+struct xlr_i2c_softc {
+ device_t dev; /* Self */
+ struct resource *mem_res; /* Memory resource */
+ volatile int flags;
+ int sc_started;
+ uint8_t i2cdev_addr;
+ xlr_reg_t *iobase_i2c_regs;
+ device_t iicbus;
+ struct mtx sc_mtx;
+};
+
+static void
+set_i2c_base(device_t dev)
+{
+ struct xlr_i2c_softc *sc;
+
+ sc = device_get_softc(dev);
+ if (device_get_unit(dev) == 0)
+ sc->iobase_i2c_regs = xlr_io_mmio(XLR_IO_I2C_0_OFFSET);
+ else
+ sc->iobase_i2c_regs = xlr_io_mmio(XLR_IO_I2C_1_OFFSET);
+}
+
+static void
+xlr_i2c_dev_write(device_t dev, int reg, int value)
+{
+ struct xlr_i2c_softc *sc;
+
+ sc = device_get_softc(dev);
+ xlr_write_reg(sc->iobase_i2c_regs, reg, value);
+ return;
+}
+
+
+static int
+xlr_i2c_dev_read(device_t dev, int reg)
+{
+ uint32_t val;
+ struct xlr_i2c_softc *sc;
+
+ sc = device_get_softc(dev);
+ val = xlr_read_reg(sc->iobase_i2c_regs, reg);
+ return ((int)val);
+}
+
+
+static int
+xlr_i2c_probe(device_t dev)
+{
+ device_set_desc(dev, "XLR/XLS I2C bus controller");
+
+ return (0);
+}
+
+
+/*
+ * We add all the devices which we know about.
+ * The generic attach routine will attach them if they are alive.
+ */
+static int
+xlr_i2c_attach(device_t dev)
+{
+ int rid;
+ struct xlr_i2c_softc *sc;
+ device_t tmpd;
+
+ if(device_get_unit(dev)!=ARIZONA_I2C_BUS) {
+ device_printf(dev, "unused iicbus instance\n");
+ return 0;
+ }
+
+ sc = device_get_softc(dev);
+ set_i2c_base(dev);
+
+ mtx_init(&sc->sc_mtx, "xlr_i2c", "xlr_i2c", MTX_DEF);
+
+ sc->mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, RF_ACTIVE);
+ if (sc->mem_res == NULL) {
+ printf("not able to allocate the bus resource\n");
+ }
+ if ((sc->iicbus = device_add_child(dev, "iicbus", -1)) == NULL) {
+ printf("could not allocate iicbus instance\n");
+ return -1;
+ }
+ if(xlr_board_info.xlr_i2c_device[I2C_RTC].enabled == 1) {
+ tmpd = device_add_child(sc->iicbus, "ds1374u", 0);
+ device_set_ivars(tmpd, &xlr_board_info.xlr_i2c_device[I2C_RTC]);
+ }
+ if(xlr_board_info.xlr_i2c_device[I2C_THERMAL].enabled == 1) {
+ tmpd = device_add_child(sc->iicbus, "max6657", 0);
+ device_set_ivars(tmpd, &xlr_board_info.xlr_i2c_device[I2C_THERMAL]);
+ }
+ if(xlr_board_info.xlr_i2c_device[I2C_EEPROM].enabled == 1) {
+ tmpd = device_add_child(sc->iicbus, "at24co2n", 0);
+ device_set_ivars(tmpd, &xlr_board_info.xlr_i2c_device[I2C_EEPROM]);
+ }
+
+ bus_generic_attach(dev);
+
+ return (0);
+}
+
+static int
+xlr_i2c_detach(device_t dev)
+{
+ bus_generic_detach(dev);
+
+ return (0);
+}
+
+static int
+xlr_i2c_start(device_t dev, u_char slave, int timeout)
+{
+ int error = 0;
+ struct xlr_i2c_softc *sc;
+
+ sc = device_get_softc(dev);
+ mtx_lock(&sc->sc_mtx);
+ sc->sc_started = 1;
+ sc->i2cdev_addr = (slave >> 1);
+ return error;
+
+}
+
+static int
+xlr_i2c_stop(device_t dev)
+{
+ int error = 0;
+ struct xlr_i2c_softc *sc;
+
+ sc = device_get_softc(dev);
+ mtx_unlock(&sc->sc_mtx);
+ return error;
+
+}
+
+static int
+xlr_i2c_read(device_t dev, char *buf, int len, int *read, int last,
+ int delay)
+{
+ volatile uint32_t i2c_status = 0;
+ int pos=0;
+ int timeout = 0;
+
+ xlr_i2c_dev_write(dev, XLR_I2C_CFG, XLR_I2C_CFG_NOADDR);
+ xlr_i2c_dev_write(dev, XLR_I2C_BYTECNT, len);
+
+retry:
+ xlr_i2c_dev_write(dev, XLR_I2C_STARTXFR, XLR_I2C_STARTXFR_RD);
+
+ timeout = 0;
+ while(1) {
+ if(timeout++ > MAXTIME)
+ return -1;
+
+ i2c_status = xlr_i2c_dev_read(dev, XLR_I2C_STATUS);
+ if (i2c_status & XLR_I2C_RXRDY)
+ buf[pos++] = (uint8_t) xlr_i2c_dev_read(dev, XLR_I2C_DATAIN);
+
+ /* ACKERR -- bail */
+ if (i2c_status & XLR_I2C_ACK_ERR)
+ return -1; /* ACK_ERROR */
+
+ /* LOST ARB or STARTERR -- repeat */
+ if (i2c_status & XLR_I2C_ARB_STARTERR)
+ goto retry;
+
+ /* Wait for busy bit to go away */
+ if (i2c_status & XLR_I2C_BUS_BUSY)
+ continue;
+
+ if (pos == len)
+ break;
+ }
+ *read = pos;
+ return 0;
+
+}
+
+static int
+xlr_i2c_write(device_t dev, const char *buf, int len, int *sent, int timeout /* us */ )
+{
+ volatile uint32_t i2c_status = 0x00;
+ uint8_t devaddr, addr;
+ struct xlr_i2c_softc *sc;
+ int pos;
+
+ sc = device_get_softc(dev);
+
+ /* the first byte of write is addr (of register in device) */
+ addr = buf[0];
+ devaddr = sc->i2cdev_addr;
+ xlr_i2c_dev_write(dev, XLR_I2C_ADDR, addr);
+ xlr_i2c_dev_write(dev, XLR_I2C_DEVADDR, devaddr);
+ xlr_i2c_dev_write(dev, XLR_I2C_CFG, XLR_I2C_CFG_ADDR);
+ xlr_i2c_dev_write(dev, XLR_I2C_BYTECNT, len - 1);
+
+retry:
+ pos = 1;
+ if (len == 1) /* there is no data only address */
+ xlr_i2c_dev_write(dev, XLR_I2C_STARTXFR, XLR_I2C_STARTXFR_ND);
+ else {
+ xlr_i2c_dev_write(dev, XLR_I2C_STARTXFR, XLR_I2C_STARTXFR_WR);
+ xlr_i2c_dev_write(dev, XLR_I2C_DATAOUT, buf[pos]);
+ }
+
+ while (1) {
+ i2c_status = xlr_i2c_dev_read(dev, XLR_I2C_STATUS);
+
+ /* sdo empty send next byte */
+ if (i2c_status & XLR_I2C_SDOEMPTY) {
+ pos++;
+ xlr_i2c_dev_write(dev, XLR_I2C_DATAOUT, buf[pos]);
+ }
+
+ /* LOST ARB or STARTERR -- repeat */
+ if (i2c_status & XLR_I2C_ARB_STARTERR)
+ goto retry;
+
+ /* ACKERR -- bail */
+ if (i2c_status & XLR_I2C_ACK_ERR) {
+ printf("ACK ERR : exiting\n ");
+ return -1;
+ }
+
+ /* busy try again */
+ if (i2c_status & XLR_I2C_BUS_BUSY)
+ continue;
+
+ if (pos >= len)
+ break;
+ }
+ *sent = len - 1;
+ return 0;
+}
+
+
+
+static int
+xlr_i2c_callback(device_t dev, int index, caddr_t data)
+{
+ return 0;
+}
+
+static int
+xlr_i2c_repeated_start(device_t dev, u_char slave, int timeout)
+{
+ return 0;
+}
+
+/*
+ * I2C bus transfer for RMI boards and devices.
+ * Generic version of iicbus_transfer that calls the appropriate
+ * routines to accomplish this. See note above about acceptable
+ * buffer addresses.
+ */
+int
+xlr_i2c_transfer(device_t bus, struct iic_msg *msgs, uint32_t nmsgs)
+{
+ int i, error, lenread, lenwrote;
+ u_char addr;
+
+ addr = msgs[0].slave | LSB;
+ error = xlr_i2c_start(bus, addr, 0);
+ for (i = 0, error = 0; i < nmsgs && error == 0; i++) {
+ if (msgs[i].flags & IIC_M_RD) {
+ error = xlr_i2c_read((bus), msgs[i].buf, msgs[i].len, &lenread, IIC_LAST_READ, 0);
+ }
+ else {
+ error = xlr_i2c_write((bus), msgs[i].buf, msgs[i].len, &lenwrote, 0);
+ }
+ }
+ error = xlr_i2c_stop(bus);
+ return (error);
+}
+
+
+static device_method_t xlr_i2c_methods[] = {
+ /* device interface */
+ DEVMETHOD(device_probe, xlr_i2c_probe),
+ DEVMETHOD(device_attach, xlr_i2c_attach),
+ DEVMETHOD(device_detach, xlr_i2c_detach),
+
+ /* iicbus interface */
+ DEVMETHOD(iicbus_callback, xlr_i2c_callback),
+ DEVMETHOD(iicbus_repeated_start, xlr_i2c_repeated_start),
+ DEVMETHOD(iicbus_start, xlr_i2c_start),
+ DEVMETHOD(iicbus_stop, xlr_i2c_stop),
+ DEVMETHOD(iicbus_write, xlr_i2c_write),
+ DEVMETHOD(iicbus_read, xlr_i2c_read),
+ DEVMETHOD(iicbus_transfer, xlr_i2c_transfer),
+ {0, 0}
+};
+
+static driver_t xlr_i2c_driver = {
+ "xlr_i2c",
+ xlr_i2c_methods,
+ sizeof(struct xlr_i2c_softc),
+};
+
+DRIVER_MODULE(xlr_i2c, iodi, xlr_i2c_driver, xlr_i2c_devclass, 0, 0);
+DRIVER_MODULE(iicbus, xlr_i2c, iicbus_driver, iicbus_devclass, 0, 0);
Property changes on: trunk/sys/mips/rmi/xlr_i2c.c
___________________________________________________________________
Added: svn:eol-style
## -0,0 +1 ##
+native
\ No newline at end of property
Added: svn:keywords
## -0,0 +1 ##
+MidnightBSD=%H
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+text/plain
\ No newline at end of property
Added: trunk/sys/mips/rmi/xlr_machdep.c
===================================================================
--- trunk/sys/mips/rmi/xlr_machdep.c (rev 0)
+++ trunk/sys/mips/rmi/xlr_machdep.c 2018-05-26 21:55:02 UTC (rev 9987)
@@ -0,0 +1,618 @@
+/* $MidnightBSD$ */
+/*-
+ * Copyright (c) 2006-2009 RMI Corporation
+ * Copyright (c) 2002-2004 Juli Mallett <jmallett at FreeBSD.org>
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ */
+#include <sys/cdefs.h>
+__FBSDID("$FreeBSD: stable/10/sys/mips/rmi/xlr_machdep.c 232853 2012-03-12 07:34:15Z jmallett $");
+
+#include "opt_ddb.h"
+
+#include <sys/param.h>
+#include <sys/bus.h>
+#include <sys/conf.h>
+#include <sys/rtprio.h>
+#include <sys/systm.h>
+#include <sys/interrupt.h>
+#include <sys/limits.h>
+#include <sys/lock.h>
+#include <sys/malloc.h>
+#include <sys/mutex.h>
+#include <sys/random.h>
+
+#include <sys/cons.h> /* cinit() */
+#include <sys/kdb.h>
+#include <sys/reboot.h>
+#include <sys/queue.h>
+#include <sys/smp.h>
+#include <sys/timetc.h>
+
+#include <vm/vm.h>
+#include <vm/vm_page.h>
+
+#include <machine/cpu.h>
+#include <machine/cpufunc.h>
+#include <machine/cpuinfo.h>
+#include <machine/cpuregs.h>
+#include <machine/frame.h>
+#include <machine/hwfunc.h>
+#include <machine/md_var.h>
+#include <machine/asm.h>
+#include <machine/pmap.h>
+#include <machine/trap.h>
+#include <machine/clock.h>
+#include <machine/fls64.h>
+#include <machine/intr_machdep.h>
+#include <machine/smp.h>
+
+#include <mips/rmi/iomap.h>
+#include <mips/rmi/msgring.h>
+#include <mips/rmi/interrupt.h>
+#include <mips/rmi/pic.h>
+#include <mips/rmi/board.h>
+#include <mips/rmi/rmi_mips_exts.h>
+#include <mips/rmi/rmi_boot_info.h>
+
+void mpwait(void);
+unsigned long xlr_io_base = (unsigned long)(DEFAULT_XLR_IO_BASE);
+
+/* 4KB static data aread to keep a copy of the bootload env until
+ the dynamic kenv is setup */
+char boot1_env[4096];
+int rmi_spin_mutex_safe=0;
+struct mtx xlr_pic_lock;
+
+/*
+ * Parameters from boot loader
+ */
+struct boot1_info xlr_boot1_info;
+int xlr_run_mode;
+int xlr_argc;
+int32_t *xlr_argv, *xlr_envp;
+uint64_t cpu_mask_info;
+uint32_t xlr_online_cpumask;
+uint32_t xlr_core_cpu_mask = 0x1; /* Core 0 thread 0 is always there */
+
+int xlr_shtlb_enabled;
+int xlr_ncores;
+int xlr_threads_per_core;
+uint32_t xlr_hw_thread_mask;
+int xlr_cpuid_to_hwtid[MAXCPU];
+int xlr_hwtid_to_cpuid[MAXCPU];
+
+static void
+xlr_setup_mmu_split(void)
+{
+ uint64_t mmu_setup;
+ int val = 0;
+
+ if (xlr_threads_per_core == 4 && xlr_shtlb_enabled == 0)
+ return; /* no change from boot setup */
+
+ switch (xlr_threads_per_core) {
+ case 1:
+ val = 0; break;
+ case 2:
+ val = 2; break;
+ case 4:
+ val = 3; break;
+ }
+
+ mmu_setup = read_xlr_ctrl_register(4, 0);
+ mmu_setup = mmu_setup & ~0x06;
+ mmu_setup |= (val << 1);
+
+ /* turn on global mode */
+ if (xlr_shtlb_enabled)
+ mmu_setup |= 0x01;
+
+ write_xlr_ctrl_register(4, 0, mmu_setup);
+}
+
+static void
+xlr_parse_mmu_options(void)
+{
+#ifdef notyet
+ char *hw_env, *start, *end;
+#endif
+ uint32_t cpu_map;
+ uint8_t core0_thr_mask, core_thr_mask;
+ int i, j, k;
+
+ /* First check for the shared TLB setup */
+ xlr_shtlb_enabled = 0;
+#ifdef notyet
+ /*
+ * We don't support sharing TLB per core - TODO
+ */
+ xlr_shtlb_enabled = 0;
+ if ((hw_env = getenv("xlr.shtlb")) != NULL) {
+ start = hw_env;
+ tmp = strtoul(start, &end, 0);
+ if (start != end)
+ xlr_shtlb_enabled = (tmp != 0);
+ else
+ printf("Bad value for xlr.shtlb [%s]\n", hw_env);
+ freeenv(hw_env);
+ }
+#endif
+ /*
+ * XLR supports splitting the 64 TLB entries across one, two or four
+ * threads (split mode). XLR also allows the 64 TLB entries to be shared
+ * across all threads in the core using a global flag (shared TLB mode).
+ * We will support 1/2/4 threads in split mode or shared mode.
+ *
+ */
+ xlr_ncores = 1;
+ cpu_map = xlr_boot1_info.cpu_online_map;
+
+#ifndef SMP /* Uniprocessor! */
+ if (cpu_map != 0x1) {
+ printf("WARNING: Starting uniprocessor kernel on cpumask [0x%lx]!\n"
+ "WARNING: Other CPUs will be unused.\n", (u_long)cpu_map);
+ cpu_map = 0x1;
+ }
+#endif
+ core0_thr_mask = cpu_map & 0xf;
+ switch (core0_thr_mask) {
+ case 1:
+ xlr_threads_per_core = 1; break;
+ case 3:
+ xlr_threads_per_core = 2; break;
+ case 0xf:
+ xlr_threads_per_core = 4; break;
+ default:
+ goto unsupp;
+ }
+
+ /* Verify other cores CPU masks */
+ for (i = 1; i < XLR_MAX_CORES; i++) {
+ core_thr_mask = (cpu_map >> (i*4)) & 0xf;
+ if (core_thr_mask) {
+ if (core_thr_mask != core0_thr_mask)
+ goto unsupp;
+ xlr_ncores++;
+ }
+ }
+ xlr_hw_thread_mask = cpu_map;
+
+ /* setup hardware processor id to cpu id mapping */
+ for (i = 0; i< MAXCPU; i++)
+ xlr_cpuid_to_hwtid[i] =
+ xlr_hwtid_to_cpuid [i] = -1;
+ for (i = 0, k = 0; i < XLR_MAX_CORES; i++) {
+ if (((cpu_map >> (i*4)) & 0xf) == 0)
+ continue;
+ for (j = 0; j < xlr_threads_per_core; j++) {
+ xlr_cpuid_to_hwtid[k] = i*4 + j;
+ xlr_hwtid_to_cpuid[i*4 + j] = k;
+ k++;
+ }
+ }
+
+ /* setup for the startup core */
+ xlr_setup_mmu_split();
+ return;
+
+unsupp:
+ printf("ERROR : Unsupported CPU mask [use 1,2 or 4 threads per core].\n"
+ "\tcore0 thread mask [%lx], boot cpu mask [%lx]\n"
+ "\tUsing default, 16 TLB entries per CPU, split mode\n",
+ (u_long)core0_thr_mask, (u_long)cpu_map);
+ panic("Invalid CPU mask - halting.\n");
+ return;
+}
+
+static void
+xlr_set_boot_flags(void)
+{
+ char *p;
+
+ p = getenv("bootflags");
+ if (p == NULL)
+ p = getenv("boot_flags"); /* old style */
+ if (p == NULL)
+ return;
+
+ for (; p && *p != '\0'; p++) {
+ switch (*p) {
+ case 'd':
+ case 'D':
+ boothowto |= RB_KDB;
+ break;
+ case 'g':
+ case 'G':
+ boothowto |= RB_GDB;
+ break;
+ case 'v':
+ case 'V':
+ boothowto |= RB_VERBOSE;
+ break;
+
+ case 's': /* single-user (default, supported for sanity) */
+ case 'S':
+ boothowto |= RB_SINGLE;
+ break;
+
+ default:
+ printf("Unrecognized boot flag '%c'.\n", *p);
+ break;
+ }
+ }
+
+ freeenv(p);
+ return;
+}
+extern uint32_t _end;
+
+static void
+mips_init(void)
+{
+ init_param1();
+ init_param2(physmem);
+
+ mips_cpu_init();
+ cpuinfo.cache_coherent_dma = TRUE;
+ pmap_bootstrap();
+#ifdef DDB
+ kdb_init();
+ if (boothowto & RB_KDB) {
+ kdb_enter("Boot flags requested debugger", NULL);
+ }
+#endif
+ mips_proc0_init();
+ mutex_init();
+}
+
+u_int
+platform_get_timecount(struct timecounter *tc __unused)
+{
+
+ return (0xffffffffU - pic_timer_count32(PIC_CLOCK_TIMER));
+}
+
+static void
+xlr_pic_init(void)
+{
+ struct timecounter pic_timecounter = {
+ platform_get_timecount, /* get_timecount */
+ 0, /* no poll_pps */
+ ~0U, /* counter_mask */
+ PIC_TIMER_HZ, /* frequency */
+ "XLRPIC", /* name */
+ 2000, /* quality (adjusted in code) */
+ };
+ xlr_reg_t *mmio = xlr_io_mmio(XLR_IO_PIC_OFFSET);
+ int i, irq;
+
+ write_c0_eimr64(0ULL);
+ mtx_init(&xlr_pic_lock, "pic", NULL, MTX_SPIN);
+ xlr_write_reg(mmio, PIC_CTRL, 0);
+
+ /* Initialize all IRT entries */
+ for (i = 0; i < PIC_NUM_IRTS; i++) {
+ irq = PIC_INTR_TO_IRQ(i);
+
+ /*
+ * Disable all IRTs. Set defaults (local scheduling, high
+ * polarity, level * triggered, and CPU irq)
+ */
+ xlr_write_reg(mmio, PIC_IRT_1(i), (1 << 30) | (1 << 6) | irq);
+ /* Bind all PIC irqs to cpu 0 */
+ xlr_write_reg(mmio, PIC_IRT_0(i), 0x01);
+ }
+
+ /* Setup timer 7 of PIC as a timestamp, no interrupts */
+ pic_init_timer(PIC_CLOCK_TIMER);
+ pic_set_timer(PIC_CLOCK_TIMER, ~UINT64_C(0));
+ platform_timecounter = &pic_timecounter;
+}
+
+static void
+xlr_mem_init(void)
+{
+ struct xlr_boot1_mem_map *boot_map;
+ vm_size_t physsz = 0;
+ int i, j;
+
+ /* get physical memory info from boot loader */
+ boot_map = (struct xlr_boot1_mem_map *)
+ (unsigned long)xlr_boot1_info.psb_mem_map;
+ for (i = 0, j = 0; i < boot_map->num_entries; i++, j += 2) {
+ if (boot_map->physmem_map[i].type != BOOT1_MEM_RAM)
+ continue;
+ if (j == 14) {
+ printf("*** ERROR *** memory map too large ***\n");
+ break;
+ }
+ if (j == 0) {
+ /* start after kernel end */
+ phys_avail[0] = (vm_paddr_t)
+ MIPS_KSEG0_TO_PHYS(&_end) + 0x20000;
+ /* boot loader start */
+ /* HACK to Use bootloaders memory region */
+ if (boot_map->physmem_map[0].size == 0x0c000000) {
+ boot_map->physmem_map[0].size = 0x0ff00000;
+ }
+ phys_avail[1] = boot_map->physmem_map[0].addr +
+ boot_map->physmem_map[0].size;
+ printf("First segment: addr:%#jx -> %#jx \n",
+ (uintmax_t)phys_avail[0],
+ (uintmax_t)phys_avail[1]);
+
+ dump_avail[0] = phys_avail[0];
+ dump_avail[1] = phys_avail[1];
+ } else {
+#if !defined(__mips_n64) && !defined(__mips_n32) /* !PHYSADDR_64_BIT */
+ /*
+ * In 32 bit physical address mode we cannot use
+ * mem > 0xffffffff
+ */
+ if (boot_map->physmem_map[i].addr > 0xfffff000U) {
+ printf("Memory: start %#jx size %#jx ignored"
+ "(>4GB)\n",
+ (intmax_t)boot_map->physmem_map[i].addr,
+ (intmax_t)boot_map->physmem_map[i].size);
+ continue;
+ }
+ if (boot_map->physmem_map[i].addr +
+ boot_map->physmem_map[i].size > 0xfffff000U) {
+ boot_map->physmem_map[i].size = 0xfffff000U -
+ boot_map->physmem_map[i].addr;
+ printf("Memory: start %#jx limited to 4GB\n",
+ (intmax_t)boot_map->physmem_map[i].addr);
+ }
+#endif /* !PHYSADDR_64_BIT */
+ phys_avail[j] = (vm_paddr_t)
+ boot_map->physmem_map[i].addr;
+ phys_avail[j + 1] = phys_avail[j] +
+ boot_map->physmem_map[i].size;
+ printf("Next segment : addr:%#jx -> %#jx\n",
+ (uintmax_t)phys_avail[j],
+ (uintmax_t)phys_avail[j+1]);
+ }
+
+ dump_avail[j] = phys_avail[j];
+ dump_avail[j+1] = phys_avail[j+1];
+
+ physsz += boot_map->physmem_map[i].size;
+ }
+
+ phys_avail[j] = phys_avail[j + 1] = 0;
+ realmem = physmem = btoc(physsz);
+}
+
+void
+platform_start(__register_t a0 __unused,
+ __register_t a1 __unused,
+ __register_t a2 __unused,
+ __register_t a3 __unused)
+{
+ int i;
+#ifdef SMP
+ uint32_t tmp;
+ void (*wakeup) (void *, void *, unsigned int);
+#endif
+
+ /* Save boot loader and other stuff from scratch regs */
+ xlr_boot1_info = *(struct boot1_info *)(intptr_t)(int)read_c0_register32(MIPS_COP_0_OSSCRATCH, 0);
+ cpu_mask_info = read_c0_register64(MIPS_COP_0_OSSCRATCH, 1);
+ xlr_online_cpumask = read_c0_register32(MIPS_COP_0_OSSCRATCH, 2);
+ xlr_run_mode = read_c0_register32(MIPS_COP_0_OSSCRATCH, 3);
+ xlr_argc = read_c0_register32(MIPS_COP_0_OSSCRATCH, 4);
+ /*
+ * argv and envp are passed in array of 32bit pointers
+ */
+ xlr_argv = (int32_t *)(intptr_t)(int)read_c0_register32(MIPS_COP_0_OSSCRATCH, 5);
+ xlr_envp = (int32_t *)(intptr_t)(int)read_c0_register32(MIPS_COP_0_OSSCRATCH, 6);
+
+ /* Initialize pcpu stuff */
+ mips_pcpu0_init();
+
+ /* initialize console so that we have printf */
+ boothowto |= (RB_SERIAL | RB_MULTIPLE); /* Use multiple consoles */
+
+ /* clockrate used by delay, so initialize it here */
+ cpu_clock = xlr_boot1_info.cpu_frequency / 1000000;
+
+ /*
+ * Note the time counter on CPU0 runs not at system clock speed, but
+ * at PIC time counter speed (which is returned by
+ * platform_get_frequency(). Thus we do not use
+ * xlr_boot1_info.cpu_frequency here.
+ */
+ mips_timer_early_init(xlr_boot1_info.cpu_frequency);
+
+ /* Init console please */
+ cninit();
+ init_static_kenv(boot1_env, sizeof(boot1_env));
+ printf("Environment (from %d args):\n", xlr_argc - 1);
+ if (xlr_argc == 1)
+ printf("\tNone\n");
+ for (i = 1; i < xlr_argc; i++) {
+ char *n, *arg;
+
+ arg = (char *)(intptr_t)xlr_argv[i];
+ printf("\t%s\n", arg);
+ n = strsep(&arg, "=");
+ if (arg == NULL)
+ setenv(n, "1");
+ else
+ setenv(n, arg);
+ }
+
+ xlr_set_boot_flags();
+ xlr_parse_mmu_options();
+
+ xlr_mem_init();
+ /* Set up hz, among others. */
+ mips_init();
+
+#ifdef SMP
+ /*
+ * If thread 0 of any core is not available then mark whole core as
+ * not available
+ */
+ tmp = xlr_boot1_info.cpu_online_map;
+ for (i = 4; i < MAXCPU; i += 4) {
+ if ((tmp & (0xf << i)) && !(tmp & (0x1 << i))) {
+ /*
+ * Oops.. thread 0 is not available. Disable whole
+ * core
+ */
+ tmp = tmp & ~(0xf << i);
+ printf("WARNING: Core %d is disabled because thread 0"
+ " of this core is not enabled.\n", i / 4);
+ }
+ }
+ xlr_boot1_info.cpu_online_map = tmp;
+
+ /* Wakeup Other cpus, and put them in bsd park code. */
+ wakeup = ((void (*) (void *, void *, unsigned int))
+ (unsigned long)(xlr_boot1_info.wakeup));
+ printf("Waking up CPUs 0x%jx.\n",
+ (intmax_t)xlr_boot1_info.cpu_online_map & ~(0x1U));
+ if (xlr_boot1_info.cpu_online_map & ~(0x1U))
+ wakeup(mpwait, 0,
+ (unsigned int)xlr_boot1_info.cpu_online_map);
+#endif
+
+ /* xlr specific post initialization */
+ /* initialize other on chip stuff */
+ xlr_board_info_setup();
+ xlr_msgring_config();
+ xlr_pic_init();
+ xlr_msgring_cpu_init();
+
+ mips_timer_init_params(xlr_boot1_info.cpu_frequency, 0);
+
+ printf("Platform specific startup now completes\n");
+}
+
+void
+platform_cpu_init()
+{
+}
+
+void
+platform_reset(void)
+{
+ xlr_reg_t *mmio = xlr_io_mmio(XLR_IO_GPIO_OFFSET);
+
+ /* write 1 to GPIO software reset register */
+ xlr_write_reg(mmio, 8, 1);
+}
+
+#ifdef SMP
+int xlr_ap_release[MAXCPU];
+
+int
+platform_start_ap(int cpuid)
+{
+ int hwid = xlr_cpuid_to_hwtid[cpuid];
+
+ if (xlr_boot1_info.cpu_online_map & (1<<hwid)) {
+ /*
+ * other cpus are enabled by the boot loader and they will be
+ * already looping in mpwait, release them
+ */
+ atomic_store_rel_int(&xlr_ap_release[hwid], 1);
+ return (0);
+ } else
+ return (-1);
+}
+
+void
+platform_init_ap(int cpuid)
+{
+ uint32_t stat;
+
+ /* The first thread has to setup the core MMU split */
+ if (xlr_thr_id() == 0)
+ xlr_setup_mmu_split();
+
+ /* Setup interrupts for secondary CPUs here */
+ stat = mips_rd_status();
+ KASSERT((stat & MIPS_SR_INT_IE) == 0,
+ ("Interrupts enabled in %s!", __func__));
+ stat |= MIPS_SR_COP_2_BIT | MIPS_SR_COP_0_BIT;
+ mips_wr_status(stat);
+
+ write_c0_eimr64(0ULL);
+ xlr_enable_irq(IRQ_IPI);
+ xlr_enable_irq(IRQ_TIMER);
+ if (xlr_thr_id() == 0)
+ xlr_msgring_cpu_init();
+ xlr_enable_irq(IRQ_MSGRING);
+
+ return;
+}
+
+int
+platform_ipi_intrnum(void)
+{
+
+ return (IRQ_IPI);
+}
+
+void
+platform_ipi_send(int cpuid)
+{
+
+ pic_send_ipi(xlr_cpuid_to_hwtid[cpuid], platform_ipi_intrnum());
+}
+
+void
+platform_ipi_clear(void)
+{
+}
+
+int
+platform_processor_id(void)
+{
+
+ return (xlr_hwtid_to_cpuid[xlr_cpu_id()]);
+}
+
+void
+platform_cpu_mask(cpuset_t *mask)
+{
+ int i, s;
+
+ CPU_ZERO(mask);
+ s = xlr_ncores * xlr_threads_per_core;
+ for (i = 0; i < s; i++)
+ CPU_SET(i, mask);
+}
+
+struct cpu_group *
+platform_smp_topo()
+{
+
+ return (smp_topo_2level(CG_SHARE_L2, xlr_ncores, CG_SHARE_L1,
+ xlr_threads_per_core, CG_FLAG_THREAD));
+}
+#endif
Property changes on: trunk/sys/mips/rmi/xlr_machdep.c
___________________________________________________________________
Added: svn:eol-style
## -0,0 +1 ##
+native
\ No newline at end of property
Added: svn:keywords
## -0,0 +1 ##
+MidnightBSD=%H
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+text/plain
\ No newline at end of property
Added: trunk/sys/mips/rmi/xlr_pci.c
===================================================================
--- trunk/sys/mips/rmi/xlr_pci.c (rev 0)
+++ trunk/sys/mips/rmi/xlr_pci.c 2018-05-26 21:55:02 UTC (rev 9987)
@@ -0,0 +1,660 @@
+/* $MidnightBSD$ */
+/*-
+ * Copyright (c) 2003-2009 RMI Corporation
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * 3. Neither the name of RMI Corporation, nor the names of its contributors,
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ * RMI_BSD */
+#include <sys/cdefs.h>
+__FBSDID("$FreeBSD: stable/10/sys/mips/rmi/xlr_pci.c 227843 2011-11-22 21:28:20Z marius $");
+
+#include <sys/param.h>
+#include <sys/systm.h>
+#include <sys/types.h>
+#include <sys/kernel.h>
+#include <sys/module.h>
+#include <sys/malloc.h>
+#include <sys/bus.h>
+#include <sys/endian.h>
+#include <sys/rman.h>
+
+#include <vm/vm.h>
+#include <vm/vm_param.h>
+#include <vm/pmap.h>
+
+#include <dev/pci/pcivar.h>
+#include <dev/pci/pcireg.h>
+
+#include <machine/bus.h>
+#include <machine/md_var.h>
+#include <machine/intr_machdep.h>
+#include <machine/cpuregs.h>
+
+#include <mips/rmi/rmi_mips_exts.h>
+#include <mips/rmi/interrupt.h>
+#include <mips/rmi/iomap.h>
+#include <mips/rmi/pic.h>
+#include <mips/rmi/board.h>
+#include <mips/rmi/pcibus.h>
+
+#include "pcib_if.h"
+
+#define pci_cfg_offset(bus,slot,devfn,where) (((bus)<<16) + ((slot) << 11)+((devfn)<<8)+(where))
+#define PCIE_LINK_STATE 0x4000
+
+#define LSU_CFG0_REGID 0
+#define LSU_CERRLOG_REGID 9
+#define LSU_CERROVF_REGID 10
+#define LSU_CERRINT_REGID 11
+
+/* MSI support */
+#define MSI_MIPS_ADDR_DEST 0x000ff000
+#define MSI_MIPS_ADDR_RH 0x00000008
+#define MSI_MIPS_ADDR_RH_OFF 0x00000000
+#define MSI_MIPS_ADDR_RH_ON 0x00000008
+#define MSI_MIPS_ADDR_DM 0x00000004
+#define MSI_MIPS_ADDR_DM_PHYSICAL 0x00000000
+#define MSI_MIPS_ADDR_DM_LOGICAL 0x00000004
+
+/* Fields in data for Intel MSI messages. */
+#define MSI_MIPS_DATA_TRGRMOD 0x00008000 /* Trigger mode */
+#define MSI_MIPS_DATA_TRGREDG 0x00000000 /* edge */
+#define MSI_MIPS_DATA_TRGRLVL 0x00008000 /* level */
+
+#define MSI_MIPS_DATA_LEVEL 0x00004000 /* Polarity. */
+#define MSI_MIPS_DATA_DEASSERT 0x00000000
+#define MSI_MIPS_DATA_ASSERT 0x00004000
+
+#define MSI_MIPS_DATA_DELMOD 0x00000700 /* Delivery Mode */
+#define MSI_MIPS_DATA_DELFIXED 0x00000000 /* fixed */
+#define MSI_MIPS_DATA_DELLOPRI 0x00000100 /* lowest priority */
+
+#define MSI_MIPS_DATA_INTVEC 0x000000ff
+
+/*
+ * Build Intel MSI message and data values from a source. AMD64 systems
+ * seem to be compatible, so we use the same function for both.
+ */
+#define MIPS_MSI_ADDR(cpu) \
+ (MSI_MIPS_ADDR_BASE | (cpu) << 12 | \
+ MSI_MIPS_ADDR_RH_OFF | MSI_MIPS_ADDR_DM_PHYSICAL)
+
+#define MIPS_MSI_DATA(irq) \
+ (MSI_MIPS_DATA_TRGRLVL | MSI_MIPS_DATA_DELFIXED | \
+ MSI_MIPS_DATA_ASSERT | (irq))
+
+struct xlr_pcib_softc {
+ bus_dma_tag_t sc_pci_dmat; /* PCI DMA tag pointer */
+};
+
+static devclass_t pcib_devclass;
+static void *xlr_pci_config_base;
+static struct rman irq_rman, port_rman, mem_rman;
+
+static void
+xlr_pci_init_resources(void)
+{
+
+ irq_rman.rm_start = 0;
+ irq_rman.rm_end = 255;
+ irq_rman.rm_type = RMAN_ARRAY;
+ irq_rman.rm_descr = "PCI Mapped Interrupts";
+ if (rman_init(&irq_rman)
+ || rman_manage_region(&irq_rman, 0, 255))
+ panic("pci_init_resources irq_rman");
+
+ port_rman.rm_start = 0;
+ port_rman.rm_end = ~0ul;
+ port_rman.rm_type = RMAN_ARRAY;
+ port_rman.rm_descr = "I/O ports";
+ if (rman_init(&port_rman)
+ || rman_manage_region(&port_rman, 0x10000000, 0x1fffffff))
+ panic("pci_init_resources port_rman");
+
+ mem_rman.rm_start = 0;
+ mem_rman.rm_end = ~0ul;
+ mem_rman.rm_type = RMAN_ARRAY;
+ mem_rman.rm_descr = "I/O memory";
+ if (rman_init(&mem_rman)
+ || rman_manage_region(&mem_rman, 0xd0000000, 0xdfffffff))
+ panic("pci_init_resources mem_rman");
+}
+
+static int
+xlr_pcib_probe(device_t dev)
+{
+
+ if (xlr_board_info.is_xls)
+ device_set_desc(dev, "XLS PCIe bus");
+ else
+ device_set_desc(dev, "XLR PCI bus");
+
+ xlr_pci_init_resources();
+ xlr_pci_config_base = (void *)MIPS_PHYS_TO_KSEG1(DEFAULT_PCI_CONFIG_BASE);
+
+ return (0);
+}
+
+static int
+xlr_pcib_read_ivar(device_t dev, device_t child, int which, uintptr_t *result)
+{
+
+ switch (which) {
+ case PCIB_IVAR_DOMAIN:
+ *result = 0;
+ return (0);
+ case PCIB_IVAR_BUS:
+ *result = 0;
+ return (0);
+ }
+ return (ENOENT);
+}
+
+static int
+xlr_pcib_write_ivar(device_t dev, device_t child, int which, uintptr_t result)
+{
+ switch (which) {
+ case PCIB_IVAR_DOMAIN:
+ return (EINVAL);
+ case PCIB_IVAR_BUS:
+ return (EINVAL);
+ }
+ return (ENOENT);
+}
+
+static int
+xlr_pcib_maxslots(device_t dev)
+{
+
+ return (PCI_SLOTMAX);
+}
+
+static __inline__ void
+disable_and_clear_cache_error(void)
+{
+ uint64_t lsu_cfg0;
+
+ lsu_cfg0 = read_xlr_ctrl_register(CPU_BLOCKID_LSU, LSU_CFG0_REGID);
+ lsu_cfg0 = lsu_cfg0 & ~0x2e;
+ write_xlr_ctrl_register(CPU_BLOCKID_LSU, LSU_CFG0_REGID, lsu_cfg0);
+ /* Clear cache error log */
+ write_xlr_ctrl_register(CPU_BLOCKID_LSU, LSU_CERRLOG_REGID, 0);
+}
+
+static __inline__ void
+clear_and_enable_cache_error(void)
+{
+ uint64_t lsu_cfg0 = 0;
+
+ /* first clear the cache error logging register */
+ write_xlr_ctrl_register(CPU_BLOCKID_LSU, LSU_CERRLOG_REGID, 0);
+ write_xlr_ctrl_register(CPU_BLOCKID_LSU, LSU_CERROVF_REGID, 0);
+ write_xlr_ctrl_register(CPU_BLOCKID_LSU, LSU_CERRINT_REGID, 0);
+
+ lsu_cfg0 = read_xlr_ctrl_register(CPU_BLOCKID_LSU, LSU_CFG0_REGID);
+ lsu_cfg0 = lsu_cfg0 | 0x2e;
+ write_xlr_ctrl_register(CPU_BLOCKID_LSU, LSU_CFG0_REGID, lsu_cfg0);
+}
+
+static uint32_t
+pci_cfg_read_32bit(uint32_t addr)
+{
+ uint32_t temp = 0;
+ uint32_t *p = (uint32_t *)xlr_pci_config_base + addr / sizeof(uint32_t);
+ uint64_t cerr_cpu_log = 0;
+
+ disable_and_clear_cache_error();
+ temp = bswap32(*p);
+
+ /* Read cache err log */
+ cerr_cpu_log = read_xlr_ctrl_register(CPU_BLOCKID_LSU,
+ LSU_CERRLOG_REGID);
+ if (cerr_cpu_log) {
+ /* Device don't exist. */
+ temp = ~0x0;
+ }
+ clear_and_enable_cache_error();
+ return (temp);
+}
+
+static u_int32_t
+xlr_pcib_read_config(device_t dev, u_int b, u_int s, u_int f,
+ u_int reg, int width)
+{
+ uint32_t data = 0;
+
+ if ((width == 2) && (reg & 1))
+ return 0xFFFFFFFF;
+ else if ((width == 4) && (reg & 3))
+ return 0xFFFFFFFF;
+
+ data = pci_cfg_read_32bit(pci_cfg_offset(b, s, f, reg));
+
+ if (width == 1)
+ return ((data >> ((reg & 3) << 3)) & 0xff);
+ else if (width == 2)
+ return ((data >> ((reg & 3) << 3)) & 0xffff);
+ else
+ return (data);
+}
+
+static void
+xlr_pcib_write_config(device_t dev, u_int b, u_int s, u_int f,
+ u_int reg, u_int32_t val, int width)
+{
+ uint32_t cfgaddr = pci_cfg_offset(b, s, f, reg);
+ uint32_t data = 0, *p;
+
+ if ((width == 2) && (reg & 1))
+ return;
+ else if ((width == 4) && (reg & 3))
+ return;
+
+ if (width == 1) {
+ data = pci_cfg_read_32bit(cfgaddr);
+ data = (data & ~(0xff << ((reg & 3) << 3))) |
+ (val << ((reg & 3) << 3));
+ } else if (width == 2) {
+ data = pci_cfg_read_32bit(cfgaddr);
+ data = (data & ~(0xffff << ((reg & 3) << 3))) |
+ (val << ((reg & 3) << 3));
+ } else {
+ data = val;
+ }
+
+ p = (uint32_t *)xlr_pci_config_base + cfgaddr / sizeof(uint32_t);
+ *p = bswap32(data);
+
+ return;
+}
+
+static int
+xlr_pcib_attach(device_t dev)
+{
+ struct xlr_pcib_softc *sc;
+ sc = device_get_softc(dev);
+
+ /*
+ * XLR C revision chips cannot do DMA above 2G physical address
+ * create a parent tag with this lowaddr
+ */
+ if (xlr_is_c_revision()) {
+ if (bus_dma_tag_create(bus_get_dma_tag(dev), 1, 0,
+ 0x7fffffff, ~0, NULL, NULL, 0x7fffffff,
+ 0xff, 0x7fffffff, 0, NULL, NULL, &sc->sc_pci_dmat) != 0)
+ panic("%s: bus_dma_tag_create failed", __func__);
+ }
+ device_add_child(dev, "pci", 0);
+ bus_generic_attach(dev);
+ return (0);
+}
+
+static void
+xlr_pcib_identify(driver_t * driver, device_t parent)
+{
+
+ BUS_ADD_CHILD(parent, 0, "pcib", 0);
+}
+
+/*
+ * XLS PCIe can have upto 4 links, and each link has its on IRQ
+ * Find the link on which the device is on
+ */
+static int
+xls_pcie_link(device_t pcib, device_t dev)
+{
+ device_t parent, tmp;
+
+ /* find the lane on which the slot is connected to */
+ printf("xls_pcie_link : bus %s dev %s\n", device_get_nameunit(pcib),
+ device_get_nameunit(dev));
+ tmp = dev;
+ while (1) {
+ parent = device_get_parent(tmp);
+ if (parent == NULL || parent == pcib) {
+ device_printf(dev, "Cannot find parent bus\n");
+ return (-1);
+ }
+ if (strcmp(device_get_nameunit(parent), "pci0") == 0)
+ break;
+ tmp = parent;
+ }
+ return (pci_get_slot(tmp));
+}
+
+/*
+ * Find the IRQ for the link, each link has a different interrupt
+ * at the XLS pic
+ */
+static int
+xls_pcie_link_irq(int link)
+{
+
+ switch (link) {
+ case 0:
+ return (PIC_PCIE_LINK0_IRQ);
+ case 1:
+ return (PIC_PCIE_LINK1_IRQ);
+ case 2:
+ if (xlr_is_xls_b0())
+ return (PIC_PCIE_B0_LINK2_IRQ);
+ else
+ return (PIC_PCIE_LINK2_IRQ);
+ case 3:
+ if (xlr_is_xls_b0())
+ return (PIC_PCIE_B0_LINK3_IRQ);
+ else
+ return (PIC_PCIE_LINK3_IRQ);
+ }
+ return (-1);
+}
+
+static int
+xlr_alloc_msi(device_t pcib, device_t dev, int count, int maxcount, int *irqs)
+{
+ int i, link;
+
+ /*
+ * Each link has 32 MSIs that can be allocated, but for now
+ * we only support one device per link.
+ * msi_alloc() equivalent is needed when we start supporting
+ * bridges on the PCIe link.
+ */
+ link = xls_pcie_link(pcib, dev);
+ if (link == -1)
+ return (ENXIO);
+
+ /*
+ * encode the irq so that we know it is a MSI interrupt when we
+ * setup interrupts
+ */
+ for (i = 0; i < count; i++)
+ irqs[i] = 64 + link * 32 + i;
+
+ return (0);
+}
+
+static int
+xlr_release_msi(device_t pcib, device_t dev, int count, int *irqs)
+{
+ device_printf(dev, "%s: msi release %d\n", device_get_nameunit(pcib),
+ count);
+ return (0);
+}
+
+static int
+xlr_map_msi(device_t pcib, device_t dev, int irq, uint64_t *addr,
+ uint32_t *data)
+{
+ int msi;
+
+ if (irq >= 64) {
+ msi = irq - 64;
+ *addr = MIPS_MSI_ADDR(0);
+ *data = MIPS_MSI_DATA(msi);
+ return (0);
+ } else {
+ device_printf(dev, "%s: map_msi for irq %d - ignored",
+ device_get_nameunit(pcib), irq);
+ return (ENXIO);
+ }
+}
+
+static void
+bridge_pcix_ack(int irq)
+{
+
+ (void)xlr_read_reg(xlr_io_mmio(XLR_IO_PCIX_OFFSET), 0x140 >> 2);
+}
+
+static void
+bridge_pcie_ack(int irq)
+{
+ uint32_t reg;
+ xlr_reg_t *pcie_mmio_le = xlr_io_mmio(XLR_IO_PCIE_1_OFFSET);
+
+ switch (irq) {
+ case PIC_PCIE_LINK0_IRQ:
+ reg = PCIE_LINK0_MSI_STATUS;
+ break;
+ case PIC_PCIE_LINK1_IRQ:
+ reg = PCIE_LINK1_MSI_STATUS;
+ break;
+ case PIC_PCIE_LINK2_IRQ:
+ case PIC_PCIE_B0_LINK2_IRQ:
+ reg = PCIE_LINK2_MSI_STATUS;
+ break;
+ case PIC_PCIE_LINK3_IRQ:
+ case PIC_PCIE_B0_LINK3_IRQ:
+ reg = PCIE_LINK3_MSI_STATUS;
+ break;
+ default:
+ return;
+ }
+ xlr_write_reg(pcie_mmio_le, reg>>2, 0xffffffff);
+}
+
+static int
+mips_platform_pci_setup_intr(device_t dev, device_t child,
+ struct resource *irq, int flags, driver_filter_t *filt,
+ driver_intr_t *intr, void *arg, void **cookiep)
+{
+ int error = 0;
+ int xlrirq;
+
+ error = rman_activate_resource(irq);
+ if (error)
+ return error;
+ if (rman_get_start(irq) != rman_get_end(irq)) {
+ device_printf(dev, "Interrupt allocation %lu != %lu\n",
+ rman_get_start(irq), rman_get_end(irq));
+ return (EINVAL);
+ }
+ xlrirq = rman_get_start(irq);
+
+ if (strcmp(device_get_name(dev), "pcib") != 0)
+ return (0);
+
+ if (xlr_board_info.is_xls == 0) {
+ xlr_establish_intr(device_get_name(child), filt,
+ intr, arg, PIC_PCIX_IRQ, flags, cookiep, bridge_pcix_ack);
+ pic_setup_intr(PIC_IRT_PCIX_INDEX, PIC_PCIX_IRQ, 0x1, 1);
+ } else {
+ /*
+ * temporary hack for MSI, we support just one device per
+ * link, and assign the link interrupt to the device interrupt
+ */
+ if (xlrirq >= 64) {
+ xlrirq -= 64;
+ if (xlrirq % 32 != 0)
+ return (0);
+ xlrirq = xls_pcie_link_irq(xlrirq / 32);
+ if (xlrirq == -1)
+ return (EINVAL);
+ }
+ xlr_establish_intr(device_get_name(child), filt,
+ intr, arg, xlrirq, flags, cookiep, bridge_pcie_ack);
+ pic_setup_intr(xlrirq - PIC_IRQ_BASE, xlrirq, 0x1, 1);
+ }
+
+ return (bus_generic_setup_intr(dev, child, irq, flags, filt, intr,
+ arg, cookiep));
+}
+
+static int
+mips_platform_pci_teardown_intr(device_t dev, device_t child,
+ struct resource *irq, void *cookie)
+{
+ if (strcmp(device_get_name(child), "pci") == 0) {
+ /* if needed reprogram the pic to clear pcix related entry */
+ device_printf(dev, "teardown intr\n");
+ }
+ return (bus_generic_teardown_intr(dev, child, irq, cookie));
+}
+
+static struct resource *
+xlr_pci_alloc_resource(device_t bus, device_t child, int type, int *rid,
+ u_long start, u_long end, u_long count, u_int flags)
+{
+ struct rman *rm;
+ struct resource *rv;
+ vm_offset_t va;
+ int needactivate = flags & RF_ACTIVE;
+
+ switch (type) {
+ case SYS_RES_IRQ:
+ rm = &irq_rman;
+ break;
+
+ case SYS_RES_IOPORT:
+ rm = &port_rman;
+ break;
+
+ case SYS_RES_MEMORY:
+ rm = &mem_rman;
+ break;
+
+ default:
+ return (0);
+ }
+
+ rv = rman_reserve_resource(rm, start, end, count, flags, child);
+ if (rv == 0)
+ return (0);
+
+ rman_set_rid(rv, *rid);
+
+ if (type == SYS_RES_MEMORY || type == SYS_RES_IOPORT) {
+ va = (vm_offset_t)pmap_mapdev(start, count);
+ rman_set_bushandle(rv, va);
+ /* bushandle is same as virtual addr */
+ rman_set_virtual(rv, (void *)va);
+ rman_set_bustag(rv, rmi_pci_bus_space);
+ }
+
+ if (needactivate) {
+ if (bus_activate_resource(child, type, *rid, rv)) {
+ rman_release_resource(rv);
+ return (NULL);
+ }
+ }
+ return (rv);
+}
+
+static int
+xlr_pci_release_resource(device_t bus, device_t child, int type, int rid,
+ struct resource *r)
+{
+
+ return (rman_release_resource(r));
+}
+
+static bus_dma_tag_t
+xlr_pci_get_dma_tag(device_t bus, device_t child)
+{
+ struct xlr_pcib_softc *sc;
+
+ sc = device_get_softc(bus);
+ return (sc->sc_pci_dmat);
+}
+
+static int
+xlr_pci_activate_resource(device_t bus, device_t child, int type, int rid,
+ struct resource *r)
+{
+
+ return (rman_activate_resource(r));
+}
+
+static int
+xlr_pci_deactivate_resource(device_t bus, device_t child, int type, int rid,
+ struct resource *r)
+{
+
+ return (rman_deactivate_resource(r));
+}
+
+static int
+mips_pci_route_interrupt(device_t bus, device_t dev, int pin)
+{
+ int irq, link;
+
+ /*
+ * Validate requested pin number.
+ */
+ if ((pin < 1) || (pin > 4))
+ return (255);
+
+ if (xlr_board_info.is_xls) {
+ link = xls_pcie_link(bus, dev);
+ irq = xls_pcie_link_irq(link);
+ if (irq != -1)
+ return (irq);
+ } else {
+ if (pin == 1)
+ return (PIC_PCIX_IRQ);
+ }
+
+ return (255);
+}
+
+static device_method_t xlr_pcib_methods[] = {
+ /* Device interface */
+ DEVMETHOD(device_identify, xlr_pcib_identify),
+ DEVMETHOD(device_probe, xlr_pcib_probe),
+ DEVMETHOD(device_attach, xlr_pcib_attach),
+
+ /* Bus interface */
+ DEVMETHOD(bus_read_ivar, xlr_pcib_read_ivar),
+ DEVMETHOD(bus_write_ivar, xlr_pcib_write_ivar),
+ DEVMETHOD(bus_alloc_resource, xlr_pci_alloc_resource),
+ DEVMETHOD(bus_release_resource, xlr_pci_release_resource),
+ DEVMETHOD(bus_get_dma_tag, xlr_pci_get_dma_tag),
+ DEVMETHOD(bus_activate_resource, xlr_pci_activate_resource),
+ DEVMETHOD(bus_deactivate_resource, xlr_pci_deactivate_resource),
+ DEVMETHOD(bus_setup_intr, mips_platform_pci_setup_intr),
+ DEVMETHOD(bus_teardown_intr, mips_platform_pci_teardown_intr),
+
+ /* pcib interface */
+ DEVMETHOD(pcib_maxslots, xlr_pcib_maxslots),
+ DEVMETHOD(pcib_read_config, xlr_pcib_read_config),
+ DEVMETHOD(pcib_write_config, xlr_pcib_write_config),
+ DEVMETHOD(pcib_route_interrupt, mips_pci_route_interrupt),
+
+ DEVMETHOD(pcib_alloc_msi, xlr_alloc_msi),
+ DEVMETHOD(pcib_release_msi, xlr_release_msi),
+ DEVMETHOD(pcib_map_msi, xlr_map_msi),
+
+ DEVMETHOD_END
+};
+
+static driver_t xlr_pcib_driver = {
+ "pcib",
+ xlr_pcib_methods,
+ sizeof(struct xlr_pcib_softc),
+};
+
+DRIVER_MODULE(pcib, iodi, xlr_pcib_driver, pcib_devclass, 0, 0);
Property changes on: trunk/sys/mips/rmi/xlr_pci.c
___________________________________________________________________
Added: svn:eol-style
## -0,0 +1 ##
+native
\ No newline at end of property
Added: svn:keywords
## -0,0 +1 ##
+MidnightBSD=%H
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+text/plain
\ No newline at end of property
Added: trunk/sys/mips/rmi/xlr_pcmcia.c
===================================================================
--- trunk/sys/mips/rmi/xlr_pcmcia.c (rev 0)
+++ trunk/sys/mips/rmi/xlr_pcmcia.c 2018-05-26 21:55:02 UTC (rev 9987)
@@ -0,0 +1,150 @@
+/* $MidnightBSD$ */
+/*-
+ * Copyright (c) 2003-2009 RMI Corporation
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * 3. Neither the name of RMI Corporation, nor the names of its contributors,
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ * RMI_BSD */
+/*
+ * ATA driver for the XLR_PCMCIA Host adapter on the RMI XLR/XLS/.
+ */
+#include <sys/cdefs.h>
+__FBSDID("$FreeBSD: stable/10/sys/mips/rmi/xlr_pcmcia.c 211923 2010-08-28 07:58:10Z jchandra $");
+
+#include <sys/param.h>
+#include <sys/systm.h>
+#include <sys/kernel.h>
+#include <sys/module.h>
+#include <sys/bus.h>
+#include <sys/rman.h>
+#include <vm/uma.h>
+#include <sys/ata.h>
+#include <sys/sema.h>
+#include <sys/taskqueue.h>
+#include <sys/bus_dma.h>
+
+#include <dev/ata/ata-all.h>
+#include <mips/rmi/pic.h>
+#include <mips/rmi/iomap.h>
+#include <mips/include/resource.h>
+#include <mips/rmi/interrupt.h>
+
+#define XLR_PCMCIA_DATA_REG 0x1f0
+#define XLR_PCMCIA_ERROR_REG 0x1f1
+#define XLR_PCMCIA_SECT_CNT_REG 0x1f2
+#define XLR_PCMCIA_SECT_NUM_REG 0x1f3
+#define XLR_PCMCIA_CYLINDER_LOW_REG 0x1f4
+#define XLR_PCMCIA_CYLINDER_HIGH_REG 0x1f5
+#define XLR_PCMCIA_SECT_DRIVE_HEAD_REG 0x1f6
+#define XLR_PCMCIA_CMD_STATUS_REG 0x1f7
+#define XLR_PCMCIA_ALT_STATUS_REG 0x3f6
+#define XLR_PCMCIA_CONTROL_REG 0x3f6
+
+/*
+ * Device methods
+ */
+static int xlr_pcmcia_probe(device_t);
+static int xlr_pcmcia_attach(device_t);
+static int xlr_pcmcia_detach(device_t);
+
+static int
+xlr_pcmcia_probe(device_t dev)
+{
+ struct ata_channel *ch = device_get_softc(dev);
+
+ ch->unit = 0;
+ ch->flags |= ATA_USE_16BIT | ATA_NO_SLAVE ;
+ device_set_desc(dev, "PCMCIA ATA controller");
+
+ return (ata_probe(dev));
+}
+
+/*
+ * We add all the devices which we know about.
+ * The generic attach routine will attach them if they are alive.
+ */
+static int
+xlr_pcmcia_attach(device_t dev)
+{
+ struct ata_channel *ch = device_get_softc(dev);
+ int i;
+ int rid =0;
+ struct resource *mem_res;
+
+
+ mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, RF_ACTIVE);
+ for (i = 0; i < ATA_MAX_RES; i++)
+ ch->r_io[i].res = mem_res;
+
+ /*
+ * CF+ Specification.
+ */
+ ch->r_io[ATA_DATA].offset = XLR_PCMCIA_DATA_REG;
+ ch->r_io[ATA_FEATURE].offset = XLR_PCMCIA_ERROR_REG;
+ ch->r_io[ATA_COUNT].offset = XLR_PCMCIA_SECT_CNT_REG;
+ ch->r_io[ATA_SECTOR].offset = XLR_PCMCIA_SECT_NUM_REG;
+ ch->r_io[ATA_CYL_LSB].offset = XLR_PCMCIA_CYLINDER_LOW_REG;
+ ch->r_io[ATA_CYL_MSB].offset = XLR_PCMCIA_CYLINDER_HIGH_REG;
+ ch->r_io[ATA_DRIVE].offset = XLR_PCMCIA_SECT_DRIVE_HEAD_REG;
+ ch->r_io[ATA_COMMAND].offset = XLR_PCMCIA_CMD_STATUS_REG;
+ ch->r_io[ATA_ERROR].offset = XLR_PCMCIA_ERROR_REG;
+ ch->r_io[ATA_IREASON].offset = XLR_PCMCIA_SECT_CNT_REG;
+ ch->r_io[ATA_STATUS].offset = XLR_PCMCIA_CMD_STATUS_REG;
+ ch->r_io[ATA_ALTSTAT].offset = XLR_PCMCIA_ALT_STATUS_REG;
+ ch->r_io[ATA_CONTROL].offset = XLR_PCMCIA_CONTROL_REG;
+
+ /* Should point at the base of registers. */
+ ch->r_io[ATA_IDX_ADDR].offset = XLR_PCMCIA_DATA_REG;
+
+ ata_generic_hw(dev);
+
+ return (ata_attach(dev));
+}
+
+static int
+xlr_pcmcia_detach(device_t dev)
+{
+ bus_generic_detach(dev);
+
+ return (0);
+}
+
+static device_method_t xlr_pcmcia_methods[] = {
+ /* device interface */
+ DEVMETHOD(device_probe, xlr_pcmcia_probe),
+ DEVMETHOD(device_attach, xlr_pcmcia_attach),
+ DEVMETHOD(device_detach, xlr_pcmcia_detach),
+
+ { 0, 0 }
+};
+
+static driver_t xlr_pcmcia_driver = {
+ "ata",
+ xlr_pcmcia_methods,
+ sizeof(struct ata_channel),
+};
+
+DRIVER_MODULE(ata, iodi, xlr_pcmcia_driver, ata_devclass, 0, 0);
Property changes on: trunk/sys/mips/rmi/xlr_pcmcia.c
___________________________________________________________________
Added: svn:eol-style
## -0,0 +1 ##
+native
\ No newline at end of property
Added: svn:keywords
## -0,0 +1 ##
+MidnightBSD=%H
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+text/plain
\ No newline at end of property
Added: trunk/sys/mips/rmi/xls_ehci.c
===================================================================
--- trunk/sys/mips/rmi/xls_ehci.c (rev 0)
+++ trunk/sys/mips/rmi/xls_ehci.c 2018-05-26 21:55:02 UTC (rev 9987)
@@ -0,0 +1,221 @@
+/* $MidnightBSD$ */
+/*-
+ * Copyright (c) 1998 The NetBSD Foundation, Inc.
+ * All rights reserved.
+ *
+ * This code is derived from software contributed to The NetBSD Foundation
+ * by Lennart Augustsson (augustss at carlstedt.se) at
+ * Carlstedt Research & Technology.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
+ * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <sys/cdefs.h>
+__FBSDID("$FreeBSD: stable/10/sys/mips/rmi/xls_ehci.c 308402 2016-11-07 09:19:04Z hselasky $");
+
+#include "opt_bus.h"
+
+#include <sys/stdint.h>
+#include <sys/stddef.h>
+#include <sys/param.h>
+#include <sys/queue.h>
+#include <sys/types.h>
+#include <sys/systm.h>
+#include <sys/kernel.h>
+#include <sys/bus.h>
+#include <sys/module.h>
+#include <sys/lock.h>
+#include <sys/mutex.h>
+#include <sys/condvar.h>
+#include <sys/sysctl.h>
+#include <sys/sx.h>
+#include <sys/unistd.h>
+#include <sys/callout.h>
+#include <sys/malloc.h>
+#include <sys/priv.h>
+
+#include <sys/rman.h>
+#include <machine/resource.h>
+
+#include <dev/usb/usb.h>
+#include <dev/usb/usbdi.h>
+
+#include <dev/usb/usb_core.h>
+#include <dev/usb/usb_busdma.h>
+#include <dev/usb/usb_process.h>
+#include <dev/usb/usb_util.h>
+
+#include <dev/usb/usb_controller.h>
+#include <dev/usb/usb_bus.h>
+#include <dev/usb/controller/ehci.h>
+#include <dev/usb/controller/ehcireg.h>
+#include <mips/rmi/pic.h>
+
+static device_attach_t ehci_xls_attach;
+static device_detach_t ehci_xls_detach;
+
+static const char *xlr_usb_dev_desc = "RMI XLR USB 2.0 controller";
+static const char *xlr_vendor_desc = "RMI Corp";
+
+static int
+ehci_xls_probe(device_t self)
+{
+ /* TODO see if usb is enabled on the board */
+ device_set_desc(self, xlr_usb_dev_desc);
+ return BUS_PROBE_DEFAULT;
+}
+
+static int
+ehci_xls_attach(device_t self)
+{
+ ehci_softc_t *sc = device_get_softc(self);
+ int err;
+ int rid;
+
+ sc->sc_bus.parent = self;
+ sc->sc_bus.devices = sc->sc_devices;
+ sc->sc_bus.devices_max = EHCI_MAX_DEVICES;
+ sc->sc_bus.dma_bits = 32;
+
+ /* get all DMA memory */
+ if (usb_bus_mem_alloc_all(&sc->sc_bus,
+ USB_GET_DMA_TAG(self), &ehci_iterate_hw_softc)) {
+ return (ENOMEM);
+ }
+
+ rid = 0;
+ sc->sc_io_res = bus_alloc_resource_any(self, SYS_RES_MEMORY, &rid,
+ RF_ACTIVE);
+ if (!sc->sc_io_res) {
+ device_printf(self, "Could not map memory\n");
+ goto error;
+ }
+ sc->sc_io_tag = rman_get_bustag(sc->sc_io_res);
+ sc->sc_io_hdl = rman_get_bushandle(sc->sc_io_res);
+ printf("IO Resource tag %lx, hdl %lx, size %lx\n",
+ (u_long)sc->sc_io_tag, (u_long)sc->sc_io_hdl,
+ (u_long)sc->sc_io_size);
+
+ rid = 0;
+ sc->sc_irq_res = bus_alloc_resource(self, SYS_RES_IRQ, &rid,
+ PIC_USB_IRQ, PIC_USB_IRQ, 1, RF_SHAREABLE | RF_ACTIVE);
+ if (sc->sc_irq_res == NULL) {
+ device_printf(self, "Could not allocate irq\n");
+ goto error;
+ }
+
+ sc->sc_bus.bdev = device_add_child(self, "usbus", -1);
+ if (!sc->sc_bus.bdev) {
+ device_printf(self, "Could not add USB device\n");
+ goto error;
+ }
+ device_set_ivars(sc->sc_bus.bdev, &sc->sc_bus);
+ device_set_desc(sc->sc_bus.bdev, xlr_usb_dev_desc);
+
+ sprintf(sc->sc_vendor, xlr_vendor_desc);
+
+ err = bus_setup_intr(self, sc->sc_irq_res,
+ INTR_TYPE_BIO | INTR_MPSAFE, NULL,
+ (driver_intr_t *) ehci_interrupt, sc, &sc->sc_intr_hdl);
+ if (err) {
+ device_printf(self, "Could not setup irq, %d\n", err);
+ sc->sc_intr_hdl = NULL;
+ goto error;
+ }
+
+ err = ehci_init(sc);
+ if (err) {
+ device_printf(self, "USB init failed err=%d\n", err);
+ goto error;
+ }
+
+ err = device_probe_and_attach(sc->sc_bus.bdev);
+ if (err) {
+ device_printf(self, "USB probe and attach failed err=%d\n", err);
+ goto error;
+ }
+
+ return (0);
+
+error:
+ ehci_xls_detach(self);
+ return (ENXIO);
+}
+
+static int
+ehci_xls_detach(device_t self)
+{
+ ehci_softc_t *sc = device_get_softc(self);
+ int err;
+
+ /* during module unload there are lots of children leftover */
+ device_delete_children(self);
+
+ if (sc->sc_irq_res && sc->sc_intr_hdl) {
+ ehci_detach(sc);
+
+ err = bus_teardown_intr(self, sc->sc_irq_res, sc->sc_intr_hdl);
+ if (err)
+ device_printf(self, "Could not tear down irq, %d\n",
+ err);
+ sc->sc_intr_hdl = 0;
+ }
+
+ if (sc->sc_irq_res) {
+ bus_release_resource(self, SYS_RES_IRQ, 0, sc->sc_irq_res);
+ sc->sc_irq_res = NULL;
+ }
+ if (sc->sc_io_res) {
+ bus_release_resource(self, SYS_RES_MEMORY, 0,
+ sc->sc_io_res);
+ sc->sc_io_res = NULL;
+ sc->sc_io_tag = 0;
+ sc->sc_io_hdl = 0;
+ }
+
+ usb_bus_mem_free_all(&sc->sc_bus, &ehci_iterate_hw_softc);
+
+ return (0);
+}
+
+static device_method_t ehci_methods[] = {
+ /* Device interface */
+ DEVMETHOD(device_probe, ehci_xls_probe),
+ DEVMETHOD(device_attach, ehci_xls_attach),
+ DEVMETHOD(device_detach, ehci_xls_detach),
+ DEVMETHOD(device_suspend, bus_generic_suspend),
+ DEVMETHOD(device_resume, bus_generic_resume),
+ DEVMETHOD(device_shutdown, bus_generic_shutdown),
+
+ DEVMETHOD_END
+};
+
+static driver_t ehci_driver = {
+ .name = "ehci",
+ .methods = ehci_methods,
+ .size = sizeof(struct ehci_softc),
+};
+
+static devclass_t ehci_devclass;
+
+DRIVER_MODULE(ehci, iodi, ehci_driver, ehci_devclass, 0, 0);
+MODULE_DEPEND(ehci, usb, 1, 1, 1);
Property changes on: trunk/sys/mips/rmi/xls_ehci.c
___________________________________________________________________
Added: svn:eol-style
## -0,0 +1 ##
+native
\ No newline at end of property
Added: svn:keywords
## -0,0 +1 ##
+MidnightBSD=%H
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+text/plain
\ No newline at end of property
Added: trunk/sys/mips/rt305x/files.rt305x
===================================================================
--- trunk/sys/mips/rt305x/files.rt305x (rev 0)
+++ trunk/sys/mips/rt305x/files.rt305x 2018-05-26 21:55:02 UTC (rev 9987)
@@ -0,0 +1,14 @@
+# $FreeBSD: stable/10/sys/mips/rt305x/files.rt305x 241964 2012-10-23 19:17:43Z imp $
+
+# RT305X on-board devices
+mips/rt305x/rt305x_machdep.c standard
+mips/rt305x/obio.c standard
+mips/rt305x/rt305x_sysctl.c standard
+mips/rt305x/rt305x_ic.c standard
+mips/rt305x/rt305x_gpio.c optional gpio
+mips/rt305x/uart_bus_rt305x.c optional uart
+mips/rt305x/uart_cpu_rt305x.c optional uart
+mips/rt305x/uart_dev_rt305x.c optional uart
+mips/mips/intr_machdep.c standard
+mips/mips/tick.c standard
+dev/rt/if_rt.c optional rt
Property changes on: trunk/sys/mips/rt305x/files.rt305x
___________________________________________________________________
Added: mnbsd:nokeywords
## -0,0 +1 ##
+MidnightBSD=%H
\ No newline at end of property
Added: trunk/sys/mips/rt305x/obio.c
===================================================================
--- trunk/sys/mips/rt305x/obio.c (rev 0)
+++ trunk/sys/mips/rt305x/obio.c 2018-05-26 21:55:02 UTC (rev 9987)
@@ -0,0 +1,628 @@
+/* $MidnightBSD$ */
+/* $NetBSD: obio.c,v 1.11 2003/07/15 00:25:05 lukem Exp $ */
+
+/*-
+ * Copyright (c) 2001, 2002, 2003 Wasabi Systems, Inc.
+ * All rights reserved.
+ *
+ * Written by Jason R. Thorpe for Wasabi Systems, Inc.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <sys/cdefs.h>
+__FBSDID("$FreeBSD: stable/10/sys/mips/rt305x/obio.c 265999 2014-05-14 01:35:43Z ian $");
+
+#include <sys/param.h>
+#include <sys/systm.h>
+#include <sys/bus.h>
+#include <sys/interrupt.h>
+#include <sys/kernel.h>
+#include <sys/module.h>
+#include <sys/rman.h>
+#include <sys/malloc.h>
+
+#include <machine/bus.h>
+
+#include <mips/rt305x/rt305xreg.h>
+#include <mips/rt305x/obiovar.h>
+#include <mips/rt305x/rt305x_icvar.h>
+
+/* MIPS HW interrupts of IRQ/FIQ respectively */
+#define RT305X_INTR 0
+#define RT305X_FAST_INTR 1
+
+/* Interrupt levels */
+#define INTR_IRQ 0
+#define INTR_FIQ 1
+
+
+int irq_priorities[NIRQS] = {
+ INTR_IRQ, /* SYSCTL */
+ INTR_FIQ, /* TIMER0 */
+ INTR_FIQ, /* WDTIMER */
+ INTR_IRQ, /* Illegal Access */
+ INTR_IRQ, /* PCM */
+ INTR_IRQ, /* UART */
+ INTR_IRQ, /* GPIO */
+ INTR_FIQ, /* GDMA */
+ INTR_IRQ, /* NAND */
+ INTR_IRQ, /* Perfomance Counter */
+ INTR_IRQ, /* I2S */
+ INTR_IRQ, /* unknown */
+ INTR_IRQ, /* UARTLITE */
+ INTR_IRQ, /* unknown */
+ INTR_IRQ, /* unknown */
+ INTR_IRQ, /* unknown */
+ INTR_IRQ, /* unknown */
+ INTR_IRQ, /* EtherNet Switch */
+ INTR_FIQ, /* OTG */
+ INTR_IRQ, /* unknown */
+ INTR_IRQ, /* unknown */
+ INTR_IRQ, /* unknown */
+ INTR_IRQ, /* unknown */
+ INTR_IRQ, /* unknown */
+ INTR_IRQ, /* unknown */
+ INTR_IRQ, /* unknown */
+ INTR_IRQ, /* unknown */
+ INTR_IRQ, /* unknown */
+ INTR_IRQ, /* unknown */
+ INTR_IRQ, /* unknown */
+ INTR_IRQ, /* unknown */
+ INTR_IRQ, /* unknown */
+};
+
+
+#define REG_READ(o) *((volatile uint32_t *)MIPS_PHYS_TO_KSEG1(INTCTL_BASE + (o)))
+#define REG_WRITE(o,v) (REG_READ(o)) = (v)
+
+static int obio_activate_resource(device_t, device_t, int, int,
+ struct resource *);
+static device_t obio_add_child(device_t, u_int, const char *, int);
+static struct resource *
+ obio_alloc_resource(device_t, device_t, int, int *, u_long,
+ u_long, u_long, u_int);
+static int obio_attach(device_t);
+static int obio_deactivate_resource(device_t, device_t, int, int,
+ struct resource *);
+static struct resource_list *
+ obio_get_resource_list(device_t, device_t);
+static void obio_add_res_child(device_t, const char *, int, long, int, int);
+static void obio_hinted_child(device_t, const char *, int);
+static int obio_intr(void *);
+static int obio_probe(device_t);
+static int obio_release_resource(device_t, device_t, int, int,
+ struct resource *);
+static int obio_setup_intr(device_t, device_t, struct resource *, int,
+ driver_filter_t *, driver_intr_t *, void *, void **);
+static int obio_teardown_intr(device_t, device_t, struct resource *,
+ void *);
+
+static void
+obio_mask_irq(void *source)
+{
+ int irq;
+ uint32_t irqmask;
+
+ irq = (int)source;
+ irqmask = 1 << irq;
+
+ /* disable IRQ */
+ rt305x_ic_set(IC_INT_DIS, irqmask);
+}
+
+static void
+obio_unmask_irq(void *source)
+{
+ int irq;
+ uint32_t irqmask;
+
+ irq = (int)source;
+ irqmask = 1 << irq;
+
+ /* enable IRQ */
+ rt305x_ic_set(IC_INT_ENA, irqmask);
+
+}
+
+
+static int
+obio_probe(device_t dev)
+{
+
+ return (BUS_PROBE_NOWILDCARD);
+}
+
+static int
+obio_attach(device_t dev)
+{
+ struct obio_softc *sc = device_get_softc(dev);
+ int rid;
+
+ sc->oba_mem_rman.rm_type = RMAN_ARRAY;
+ sc->oba_mem_rman.rm_descr = "OBIO memory";
+ if (rman_init(&sc->oba_mem_rman) != 0 ||
+ rman_manage_region(&sc->oba_mem_rman, OBIO_MEM_START,
+ OBIO_MEM_END) != 0)
+ panic("obio_attach: failed to set up I/O rman");
+
+ sc->oba_irq_rman.rm_type = RMAN_ARRAY;
+ sc->oba_irq_rman.rm_descr = "OBIO IRQ";
+ if (rman_init(&sc->oba_irq_rman) != 0 ||
+ rman_manage_region(&sc->oba_irq_rman, 0, NIRQS-1) != 0)
+ panic("obio_attach: failed to set up IRQ rman");
+
+ /* Hook up our interrupt handler. */
+ if ((sc->sc_irq = bus_alloc_resource(dev, SYS_RES_IRQ, &rid,
+ RT305X_INTR, RT305X_INTR, 1,
+ RF_SHAREABLE | RF_ACTIVE)) == NULL) {
+ device_printf(dev, "unable to allocate IRQ resource\n");
+ return (ENXIO);
+ }
+
+ if ((bus_setup_intr(dev, sc->sc_irq, INTR_TYPE_MISC, obio_intr, NULL,
+ sc, &sc->sc_ih))) {
+ device_printf(dev,
+ "WARNING: unable to register interrupt handler\n");
+ return (ENXIO);
+ }
+
+ /* Hook up our FAST interrupt handler. */
+ if ((sc->sc_fast_irq = bus_alloc_resource(dev, SYS_RES_IRQ, &rid,
+ RT305X_FAST_INTR, RT305X_FAST_INTR, 1,
+ RF_SHAREABLE | RF_ACTIVE)) == NULL) {
+ device_printf(dev, "unable to allocate IRQ resource\n");
+ return (ENXIO);
+ }
+
+ if ((bus_setup_intr(dev, sc->sc_fast_irq, INTR_TYPE_MISC, obio_intr,
+ NULL, sc, &sc->sc_fast_ih))) {
+ device_printf(dev,
+ "WARNING: unable to register interrupt handler\n");
+ return (ENXIO);
+ }
+
+ /* disable all interrupts */
+ rt305x_ic_set(IC_INT_DIS, IC_INT_MASK|IC_LINE_GLOBAL);
+
+ bus_generic_probe(dev);
+
+ obio_add_res_child(dev, "rt305x_sysctl", 0,
+ SYSCTL_BASE, (SYSCTL_END - SYSCTL_BASE + 1),
+ IC_SYSCTL);
+ obio_add_res_child(dev, "rt305x_ic", 0,
+ INTCTL_BASE, (INTCTL_END - INTCTL_BASE + 1),
+ -1);
+#ifdef notyet
+ obio_add_res_child(dev, "timer",0,
+ TIMER_BASE, (TIMER_END - TIMER_BASE + 1),
+ IC_TIMER0);
+ obio_add_res_child(dev, "rt305x_memc", 0,
+ MEMCTRL_BASE, (MEMCTRL_END - MEMCTRL_BASE + 1),
+ -1);
+ obio_add_res_child(dev, "pcm", 0,
+ PCM_BASE, (PCM_END - PCM_BASE + 1),
+ IC_PCM);
+ obio_add_res_child(dev, "uart", 0,
+ UART_BASE, (UART_END - UART_BASE + 1),
+ IC_UART);
+#endif
+ obio_add_res_child(dev, "gpio", 0,
+ PIO_BASE, (PIO_END - PIO_BASE + 1),
+ IC_PIO);
+#ifdef notyet
+ obio_add_res_child(dev, "rt305x_dma", 0,
+ GDMA_BASE, (GDMA_END - GDMA_BASE + 1),
+ IC_DMA);
+ obio_add_res_child(dev, "rt305x_nandc", 0,
+ NANDFC_BASE, (NANDFC_END - NANDFC_BASE + 1),
+ IC_NAND);
+ obio_add_res_child(dev, "i2c", 0,
+ I2C_BASE, (I2C_END - I2C_BASE + 1),
+ -1);
+ obio_add_res_child(dev, "i2s", 0,
+ I2S_BASE, (I2S_END - I2S_BASE + 1),
+ IC_I2S);
+ obio_add_res_child(dev, "spi", 0,
+ SPI_BASE, (SPI_END - SPI_BASE + 1),
+ -1);
+#endif
+ obio_add_res_child(dev, "uart", 1,
+ UARTLITE_BASE, (UARTLITE_END - UARTLITE_BASE + 1),
+ IC_UARTLITE);
+ obio_add_res_child(dev, "cfi", 0,
+ FLASH_BASE, (FLASH_END - FLASH_BASE + 1),
+ -1);
+ obio_add_res_child(dev, "dotg", 0,
+ USB_OTG_BASE, (USB_OTG_END - USB_OTG_BASE + 1),
+ IC_OTG);
+ obio_add_res_child(dev, "switch", 0,
+ ETHSW_BASE, (ETHSW_END - ETHSW_BASE + 1),
+ IC_ETHSW);
+
+ bus_enumerate_hinted_children(dev);
+ bus_generic_attach(dev);
+
+ /* enable IC */
+ rt305x_ic_set(IC_INT_ENA, IC_LINE_GLOBAL);
+
+ return (0);
+}
+
+static struct resource *
+obio_alloc_resource(device_t bus, device_t child, int type, int *rid,
+ u_long start, u_long end, u_long count, u_int flags)
+{
+ struct obio_softc *sc = device_get_softc(bus);
+ struct obio_ivar *ivar = device_get_ivars(child);
+ struct resource *rv;
+ struct resource_list_entry *rle;
+ struct rman *rm;
+ int isdefault, needactivate, passthrough;
+
+ isdefault = (start == 0UL && end == ~0UL && count == 1);
+ needactivate = flags & RF_ACTIVE;
+ passthrough = (device_get_parent(child) != bus);
+ rle = NULL;
+
+ if (passthrough)
+ return (BUS_ALLOC_RESOURCE(device_get_parent(bus), child, type,
+ rid, start, end, count, flags));
+
+ /*
+ * If this is an allocation of the "default" range for a given RID,
+ * and we know what the resources for this device are (ie. they aren't
+ * maintained by a child bus), then work out the start/end values.
+ */
+ if (isdefault) {
+ rle = resource_list_find(&ivar->resources, type, *rid);
+ if (rle == NULL)
+ return (NULL);
+ if (rle->res != NULL) {
+ panic("%s: resource entry is busy", __func__);
+ }
+ start = rle->start;
+ end = rle->end;
+ count = rle->count;
+ }
+
+ switch (type) {
+ case SYS_RES_IRQ:
+ rm = &sc->oba_irq_rman;
+ break;
+ case SYS_RES_MEMORY:
+ rm = &sc->oba_mem_rman;
+ break;
+ default:
+ printf("%s: unknown resource type %d\n", __func__, type);
+ return (0);
+ }
+
+ rv = rman_reserve_resource(rm, start, end, count, flags, child);
+ if (rv == 0) {
+ printf("%s: could not reserve resource\n", __func__);
+ return (0);
+ }
+
+ rman_set_rid(rv, *rid);
+
+ if (needactivate) {
+ if (bus_activate_resource(child, type, *rid, rv)) {
+ printf("%s: could not activate resource\n", __func__);
+ rman_release_resource(rv);
+ return (0);
+ }
+ }
+
+ return (rv);
+}
+
+static int
+obio_activate_resource(device_t bus, device_t child, int type, int rid,
+ struct resource *r)
+{
+
+ /*
+ * If this is a memory resource, track the direct mapping
+ * in the uncached MIPS KSEG1 segment.
+ */
+ if (type == SYS_RES_MEMORY) {
+ void *vaddr;
+
+ vaddr = (void *)MIPS_PHYS_TO_KSEG1((intptr_t)rman_get_start(r));
+ rman_set_virtual(r, vaddr);
+ rman_set_bustag(r, mips_bus_space_generic);
+ rman_set_bushandle(r, (bus_space_handle_t)vaddr);
+ }
+
+ return (rman_activate_resource(r));
+}
+
+static int
+obio_deactivate_resource(device_t bus, device_t child, int type, int rid,
+ struct resource *r)
+{
+
+ return (rman_deactivate_resource(r));
+}
+
+static int
+obio_release_resource(device_t dev, device_t child, int type,
+ int rid, struct resource *r)
+{
+ struct resource_list *rl;
+ struct resource_list_entry *rle;
+
+ rl = obio_get_resource_list(dev, child);
+ if (rl == NULL)
+ return (EINVAL);
+ rle = resource_list_find(rl, type, rid);
+ if (rle == NULL)
+ return (EINVAL);
+ rman_release_resource(r);
+ rle->res = NULL;
+
+ return (0);
+}
+
+static int
+obio_setup_intr(device_t dev, device_t child, struct resource *ires,
+ int flags, driver_filter_t *filt, driver_intr_t *handler,
+ void *arg, void **cookiep)
+{
+ struct obio_softc *sc = device_get_softc(dev);
+ struct intr_event *event;
+ int irq, error, priority;
+ uint32_t irqmask;
+
+ irq = rman_get_start(ires);
+
+ if (irq >= NIRQS)
+ panic("%s: bad irq %d", __func__, irq);
+
+ event = sc->sc_eventstab[irq];
+ if (event == NULL) {
+ error = intr_event_create(&event, (void *)irq, 0, irq,
+ obio_mask_irq, obio_unmask_irq,
+ NULL, NULL, "obio intr%d:", irq);
+
+ sc->sc_eventstab[irq] = event;
+ }
+ else
+ panic("obio: Can't share IRQs");
+
+ intr_event_add_handler(event, device_get_nameunit(child), filt,
+ handler, arg, intr_priority(flags), flags, cookiep);
+
+ irqmask = 1 << irq;
+ priority = irq_priorities[irq];
+
+ if (priority == INTR_FIQ)
+ rt305x_ic_set(IC_INTTYPE, rt305x_ic_get(IC_INTTYPE) | irqmask);
+ else
+ rt305x_ic_set(IC_INTTYPE, rt305x_ic_get(IC_INTTYPE) & ~irqmask);
+
+ /* enable */
+ obio_unmask_irq((void*)irq);
+
+ return (0);
+}
+
+static int
+obio_teardown_intr(device_t dev, device_t child, struct resource *ires,
+ void *cookie)
+{
+ struct obio_softc *sc = device_get_softc(dev);
+ int irq, result, priority;
+ uint32_t irqmask;
+
+ irq = rman_get_start(ires);
+ if (irq >= NIRQS)
+ panic("%s: bad irq %d", __func__, irq);
+
+ if (sc->sc_eventstab[irq] == NULL)
+ panic("Trying to teardown unoccupied IRQ");
+
+ irqmask = (1 << irq);
+ priority = irq_priorities[irq];
+
+ if (priority == INTR_FIQ)
+ rt305x_ic_set(IC_INTTYPE, rt305x_ic_get(IC_INTTYPE) & ~irqmask);
+ else
+ rt305x_ic_set(IC_INTTYPE, rt305x_ic_get(IC_INTTYPE) | irqmask);
+
+ /* disable */
+ obio_mask_irq((void*)irq);
+
+ result = intr_event_remove_handler(cookie);
+ if (!result) {
+ sc->sc_eventstab[irq] = NULL;
+ }
+
+ return (result);
+}
+
+static int
+obio_intr(void *arg)
+{
+ struct obio_softc *sc = arg;
+ struct intr_event *event;
+ uint32_t irqstat;
+ int irq;
+
+ irqstat = rt305x_ic_get(IC_IRQ0STAT);
+ irqstat |= rt305x_ic_get(IC_IRQ1STAT);
+
+ irq = 0;
+ while (irqstat != 0) {
+ if ((irqstat & 1) == 1) {
+ event = sc->sc_eventstab[irq];
+ if (!event || TAILQ_EMPTY(&event->ie_handlers))
+ continue;
+
+ /* TODO: pass frame as an argument*/
+ /* TODO: log stray interrupt */
+ intr_event_handle(event, NULL);
+ }
+ irq++;
+ irqstat >>= 1;
+ }
+
+ return (FILTER_HANDLED);
+}
+
+static void
+obio_add_res_child(device_t bus, const char *dname, int dunit,
+ long maddr, int msize, int irq)
+{
+ device_t child;
+ int result;
+
+ child = BUS_ADD_CHILD(bus, 0, dname, dunit);
+
+ result = bus_set_resource(child, SYS_RES_MEMORY, 0,
+ maddr, msize);
+ if (result != 0)
+ device_printf(bus, "warning: bus_set_resource() failed\n");
+
+ if (irq != -1) {
+ result = bus_set_resource(child, SYS_RES_IRQ, 0, irq, 1);
+ if (result != 0)
+ device_printf(bus,
+ "warning: bus_set_resource() failed\n");
+ }
+}
+
+static void
+obio_hinted_child(device_t bus, const char *dname, int dunit)
+{
+ long maddr;
+ int msize;
+ int irq;
+
+ /*
+ * Set hard-wired resources for hinted child using
+ * specific RIDs.
+ */
+ resource_long_value(dname, dunit, "maddr", &maddr);
+ resource_int_value(dname, dunit, "msize", &msize);
+
+
+ if (resource_int_value(dname, dunit, "irq", &irq) == 0) irq = -1;
+
+ obio_add_res_child(bus, dname, dunit, maddr, msize, irq);
+}
+
+static device_t
+obio_add_child(device_t bus, u_int order, const char *name, int unit)
+{
+ device_t child;
+ struct obio_ivar *ivar;
+
+ ivar = malloc(sizeof(struct obio_ivar), M_DEVBUF, M_WAITOK | M_ZERO);
+ if (ivar == NULL) {
+ printf("Failed to allocate ivar\n");
+ return (0);
+ }
+ resource_list_init(&ivar->resources);
+
+ child = device_add_child_ordered(bus, order, name, unit);
+ if (child == NULL) {
+ printf("Can't add child %s%d ordered\n", name, unit);
+ return (0);
+ }
+
+ device_set_ivars(child, ivar);
+
+ return (child);
+}
+
+/*
+ * Helper routine for bus_generic_rl_get_resource/bus_generic_rl_set_resource
+ * Provides pointer to resource_list for these routines
+ */
+static struct resource_list *
+obio_get_resource_list(device_t dev, device_t child)
+{
+ struct obio_ivar *ivar;
+
+ ivar = device_get_ivars(child);
+ return (&(ivar->resources));
+}
+
+static int
+obio_print_all_resources(device_t dev)
+{
+ struct obio_ivar *ivar = device_get_ivars(dev);
+ struct resource_list *rl = &ivar->resources;
+ int retval = 0;
+
+ if (STAILQ_FIRST(rl))
+ retval += printf(" at");
+
+ retval += resource_list_print_type(rl, "mem", SYS_RES_MEMORY, "%#lx");
+ retval += resource_list_print_type(rl, "irq", SYS_RES_IRQ, "%ld");
+
+ return (retval);
+}
+
+static int
+obio_print_child(device_t bus, device_t child)
+{
+ int retval = 0;
+
+ retval += bus_print_child_header(bus, child);
+ retval += obio_print_all_resources(child);
+ if (device_get_flags(child))
+ retval += printf(" flags %#x", device_get_flags(child));
+ retval += printf(" on %s\n", device_get_nameunit(bus));
+
+ return (retval);
+}
+
+static device_method_t obio_methods[] = {
+ DEVMETHOD(bus_activate_resource, obio_activate_resource),
+ DEVMETHOD(bus_add_child, obio_add_child),
+ DEVMETHOD(bus_alloc_resource, obio_alloc_resource),
+ DEVMETHOD(bus_deactivate_resource, obio_deactivate_resource),
+ DEVMETHOD(bus_get_resource_list, obio_get_resource_list),
+ DEVMETHOD(bus_hinted_child, obio_hinted_child),
+ DEVMETHOD(bus_print_child, obio_print_child),
+ DEVMETHOD(bus_release_resource, obio_release_resource),
+ DEVMETHOD(bus_setup_intr, obio_setup_intr),
+ DEVMETHOD(bus_teardown_intr, obio_teardown_intr),
+ DEVMETHOD(device_attach, obio_attach),
+ DEVMETHOD(device_probe, obio_probe),
+ DEVMETHOD(bus_get_resource, bus_generic_rl_get_resource),
+ DEVMETHOD(bus_set_resource, bus_generic_rl_set_resource),
+
+ {0, 0},
+};
+
+static driver_t obio_driver = {
+ "obio",
+ obio_methods,
+ sizeof(struct obio_softc),
+};
+static devclass_t obio_devclass;
+
+DRIVER_MODULE(obio, nexus, obio_driver, obio_devclass, 0, 0);
Property changes on: trunk/sys/mips/rt305x/obio.c
___________________________________________________________________
Added: svn:eol-style
## -0,0 +1 ##
+native
\ No newline at end of property
Added: svn:keywords
## -0,0 +1 ##
+MidnightBSD=%H
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+text/plain
\ No newline at end of property
Added: trunk/sys/mips/rt305x/obiovar.h
===================================================================
--- trunk/sys/mips/rt305x/obiovar.h (rev 0)
+++ trunk/sys/mips/rt305x/obiovar.h 2018-05-26 21:55:02 UTC (rev 9987)
@@ -0,0 +1,59 @@
+/* $MidnightBSD$ */
+/* $NetBSD: obiovar.h,v 1.4 2003/06/16 17:40:53 thorpej Exp $ */
+
+/*-
+ * Copyright (c) 2002, 2003 Wasabi Systems, Inc.
+ * All rights reserved.
+ *
+ * Written by Jason R. Thorpe for Wasabi Systems, Inc.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * $FreeBSD: stable/10/sys/mips/rt305x/obiovar.h 220297 2011-04-03 14:39:55Z adrian $
+ *
+ */
+
+#ifndef _RT305X_OBIOVAR_H_
+#define _RT305X_OBIOVAR_H_
+
+#include <sys/rman.h>
+
+/* Number of IRQs */
+#define NIRQS 32
+
+
+struct obio_softc {
+ struct rman oba_mem_rman;
+ struct rman oba_irq_rman;
+ struct rman oba_gpio_rman;
+ struct intr_event *sc_eventstab[NIRQS]; /* IRQ events structs */
+ struct resource *sc_irq; /* IRQ resource */
+ void *sc_ih; /* interrupt cookie */
+ struct resource *sc_fast_irq; /* IRQ resource */
+ void *sc_fast_ih; /* interrupt cookie */
+};
+
+struct obio_ivar {
+ struct resource_list resources;
+};
+
+#endif /* _RT305X_OBIOVAR_H_ */
Property changes on: trunk/sys/mips/rt305x/obiovar.h
___________________________________________________________________
Added: svn:eol-style
## -0,0 +1 ##
+native
\ No newline at end of property
Added: svn:keywords
## -0,0 +1 ##
+MidnightBSD=%H
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+text/plain
\ No newline at end of property
Added: trunk/sys/mips/rt305x/rt305x_dotg.c
===================================================================
--- trunk/sys/mips/rt305x/rt305x_dotg.c (rev 0)
+++ trunk/sys/mips/rt305x/rt305x_dotg.c 2018-05-26 21:55:02 UTC (rev 9987)
@@ -0,0 +1,226 @@
+/* $MidnightBSD$ */
+#include <sys/cdefs.h>
+__FBSDID("$FreeBSD: stable/10/sys/mips/rt305x/rt305x_dotg.c 308402 2016-11-07 09:19:04Z hselasky $");
+
+/*-
+ * Copyright (c) 2010,2011 Aleksandr Rybalko. All rights reserved.
+ * Copyright (c) 2007-2008 Hans Petter Selasky. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ */
+
+#include <sys/stdint.h>
+#include <sys/stddef.h>
+#include <sys/param.h>
+#include <sys/queue.h>
+#include <sys/types.h>
+#include <sys/systm.h>
+#include <sys/kernel.h>
+#include <sys/bus.h>
+#include <sys/module.h>
+#include <sys/lock.h>
+#include <sys/mutex.h>
+#include <sys/condvar.h>
+#include <sys/sysctl.h>
+#include <sys/sx.h>
+#include <sys/unistd.h>
+#include <sys/callout.h>
+#include <sys/malloc.h>
+#include <sys/priv.h>
+#include <sys/rman.h>
+
+#include <dev/usb/usb.h>
+#include <dev/usb/usbdi.h>
+
+#include <dev/usb/usb_core.h>
+#include <dev/usb/usb_busdma.h>
+#include <dev/usb/usb_process.h>
+#include <dev/usb/usb_util.h>
+
+#include <dev/usb/usb_controller.h>
+#include <dev/usb/usb_bus.h>
+
+#include <dev/usb/controller/dotg.h>
+#include <mips/rt305x/rt305xreg.h>
+#include <mips/rt305x/rt305x_sysctlvar.h>
+
+#define MEM_RID 0
+
+static device_probe_t dotg_obio_probe;
+static device_attach_t dotg_obio_attach;
+static device_detach_t dotg_obio_detach;
+
+struct dotg_obio_softc {
+ struct dotg_softc sc_dci; /* must be first */
+};
+
+static int
+dotg_obio_probe(device_t dev)
+{
+ device_set_desc(dev, "DWC like USB OTG controller");
+ return (0);
+}
+
+static int
+dotg_obio_attach(device_t dev)
+{
+ struct dotg_obio_softc *sc = device_get_softc(dev);
+ int err;
+
+ /* setup controller interface softc */
+
+ /* initialise some bus fields */
+ sc->sc_dci.sc_dev = dev;
+ sc->sc_dci.sc_bus.parent = dev;
+ sc->sc_dci.sc_bus.devices = sc->sc_dci.sc_devices;
+ sc->sc_dci.sc_bus.devices_max = DOTG_MAX_DEVICES;
+ sc->sc_dci.sc_bus.dma_bits = 32;
+
+ /* get all DMA memory */
+ if (usb_bus_mem_alloc_all(&sc->sc_dci.sc_bus,
+ USB_GET_DMA_TAG(dev), NULL)) {
+ printf("No mem\n");
+ return (ENOMEM);
+ }
+ sc->sc_dci.sc_mem_rid = 0;
+ sc->sc_dci.sc_mem_res =
+ bus_alloc_resource_any(dev, SYS_RES_MEMORY, &sc->sc_dci.sc_irq_rid,
+ RF_ACTIVE);
+ if (!(sc->sc_dci.sc_mem_res)) {
+ printf("Can`t alloc MEM\n");
+ goto error;
+ }
+ sc->sc_dci.sc_bst = rman_get_bustag(sc->sc_dci.sc_mem_res);
+ sc->sc_dci.sc_bsh = rman_get_bushandle(sc->sc_dci.sc_mem_res);
+
+ sc->sc_dci.sc_irq_rid = 0;
+ sc->sc_dci.sc_irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ,
+ &sc->sc_dci.sc_irq_rid, RF_SHAREABLE| RF_ACTIVE);
+ if (!(sc->sc_dci.sc_irq_res)) {
+ printf("Can`t alloc IRQ\n");
+ goto error;
+ }
+
+ sc->sc_dci.sc_bus.bdev = device_add_child(dev, "usbus", -1);
+ if (!(sc->sc_dci.sc_bus.bdev)) {
+ printf("Can`t add usbus\n");
+ goto error;
+ }
+ device_set_ivars(sc->sc_dci.sc_bus.bdev, &sc->sc_dci.sc_bus);
+
+#if (__FreeBSD_version >= 700031)
+ err = bus_setup_intr(dev, sc->sc_dci.sc_irq_res,
+ INTR_TYPE_BIO | INTR_MPSAFE, NULL, (driver_intr_t *)dotg_interrupt,
+ sc, &sc->sc_dci.sc_intr_hdl);
+#else
+ err = bus_setup_intr(dev, sc->sc_dci.sc_irq_res,
+ INTR_TYPE_BIO | INTR_MPSAFE, (driver_intr_t *)dotg_interrupt,
+ sc, &sc->sc_dci.sc_intr_hdl);
+#endif
+ if (err) {
+ sc->sc_dci.sc_intr_hdl = NULL;
+ printf("Can`t set IRQ handle\n");
+ goto error;
+ }
+
+ /* Run clock for OTG core */
+ rt305x_sysctl_set(SYSCTL_CLKCFG1, rt305x_sysctl_get(SYSCTL_CLKCFG1) |
+ SYSCTL_CLKCFG1_OTG_CLK_EN);
+ rt305x_sysctl_set(SYSCTL_RSTCTRL, SYSCTL_RSTCTRL_OTG);
+ DELAY(100);
+
+ err = dotg_init(&sc->sc_dci);
+ if (err) printf("dotg_init fail\n");
+ if (!err) {
+ err = device_probe_and_attach(sc->sc_dci.sc_bus.bdev);
+ if (err) printf("device_probe_and_attach fail\n");
+ }
+ if (err) {
+ goto error;
+ }
+ return (0);
+
+error:
+ dotg_obio_detach(dev);
+ return (ENXIO);
+}
+
+static int
+dotg_obio_detach(device_t dev)
+{
+ struct dotg_obio_softc *sc = device_get_softc(dev);
+ int err;
+
+ /* during module unload there are lots of children leftover */
+ device_delete_children(dev);
+
+ if (sc->sc_dci.sc_irq_res && sc->sc_dci.sc_intr_hdl) {
+ /*
+ * only call dotg_obio_uninit() after dotg_obio_init()
+ */
+ dotg_uninit(&sc->sc_dci);
+
+ /* Stop OTG clock */
+ rt305x_sysctl_set(SYSCTL_CLKCFG1,
+ rt305x_sysctl_get(SYSCTL_CLKCFG1) &
+ ~SYSCTL_CLKCFG1_OTG_CLK_EN);
+
+ err = bus_teardown_intr(dev, sc->sc_dci.sc_irq_res,
+ sc->sc_dci.sc_intr_hdl);
+ sc->sc_dci.sc_intr_hdl = NULL;
+ }
+ if (sc->sc_dci.sc_irq_res) {
+ bus_release_resource(dev, SYS_RES_IRQ, 0,
+ sc->sc_dci.sc_irq_res);
+ sc->sc_dci.sc_irq_res = NULL;
+ }
+ if (sc->sc_dci.sc_mem_res) {
+ bus_release_resource(dev, SYS_RES_MEMORY, 0,
+ sc->sc_dci.sc_mem_res);
+ sc->sc_dci.sc_mem_res = NULL;
+ }
+ usb_bus_mem_free_all(&sc->sc_dci.sc_bus, NULL);
+
+ return (0);
+}
+
+static device_method_t dotg_obio_methods[] = {
+ /* Device interface */
+ DEVMETHOD(device_probe, dotg_obio_probe),
+ DEVMETHOD(device_attach, dotg_obio_attach),
+ DEVMETHOD(device_detach, dotg_obio_detach),
+ DEVMETHOD(device_suspend, bus_generic_suspend),
+ DEVMETHOD(device_resume, bus_generic_resume),
+ DEVMETHOD(device_shutdown, bus_generic_shutdown),
+
+ DEVMETHOD_END
+};
+
+static driver_t dotg_obio_driver = {
+ .name = "dotg",
+ .methods = dotg_obio_methods,
+ .size = sizeof(struct dotg_obio_softc),
+};
+
+static devclass_t dotg_obio_devclass;
+
+DRIVER_MODULE(dotg, obio, dotg_obio_driver, dotg_obio_devclass, 0, 0);
Property changes on: trunk/sys/mips/rt305x/rt305x_dotg.c
___________________________________________________________________
Added: svn:eol-style
## -0,0 +1 ##
+native
\ No newline at end of property
Added: svn:keywords
## -0,0 +1 ##
+MidnightBSD=%H
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+text/plain
\ No newline at end of property
Added: trunk/sys/mips/rt305x/rt305x_gpio.c
===================================================================
--- trunk/sys/mips/rt305x/rt305x_gpio.c (rev 0)
+++ trunk/sys/mips/rt305x/rt305x_gpio.c 2018-05-26 21:55:02 UTC (rev 9987)
@@ -0,0 +1,608 @@
+/* $MidnightBSD$ */
+/*-
+ * Copyright (c) 2010-2011, Aleksandr Rybalko <ray at ddteam.net>
+ * Copyright (c) 2009, Oleksandr Tymoshenko <gonzo at FreeBSD.org>
+ * Copyright (c) 2009, Luiz Otavio O Souza.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice unmodified, this list of conditions, and the following
+ * disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ */
+
+/*
+ * GPIO driver for RT305X SoC.
+ */
+
+#include <sys/cdefs.h>
+__FBSDID("$FreeBSD: stable/10/sys/mips/rt305x/rt305x_gpio.c 278786 2015-02-14 21:16:19Z loos $");
+
+#include <sys/param.h>
+#include <sys/systm.h>
+#include <sys/bus.h>
+
+#include <sys/kernel.h>
+#include <sys/module.h>
+#include <sys/rman.h>
+#include <sys/lock.h>
+#include <sys/mutex.h>
+#include <sys/gpio.h>
+
+#include <machine/bus.h>
+#include <machine/resource.h>
+#include <mips/rt305x/rt305xreg.h>
+#include <mips/rt305x/rt305x_gpio.h>
+#include <mips/rt305x/rt305x_gpiovar.h>
+#include <mips/rt305x/rt305x_sysctlvar.h>
+
+#include "gpio_if.h"
+
+#ifdef notyet
+#define DEFAULT_CAPS (GPIO_PIN_INPUT | GPIO_PIN_OUTPUT | GPIO_PIN_INVIN | \
+ GPIO_PIN_INVOUT | GPIO_PIN_REPORT )
+#else
+#define DEFAULT_CAPS (GPIO_PIN_INPUT | GPIO_PIN_OUTPUT | GPIO_PIN_INVIN | \
+ GPIO_PIN_INVOUT )
+#endif
+
+/*
+ * Helpers
+ */
+static void rt305x_gpio_pin_configure(struct rt305x_gpio_softc *sc,
+ struct gpio_pin *pin, uint32_t flags);
+
+/*
+ * Driver stuff
+ */
+static int rt305x_gpio_probe(device_t dev);
+static int rt305x_gpio_attach(device_t dev);
+static int rt305x_gpio_detach(device_t dev);
+static int rt305x_gpio_intr(void *arg);
+
+int rt305x_get_int_mask (device_t);
+void rt305x_set_int_mask (device_t, uint32_t);
+int rt305x_get_int_status(device_t);
+void rt305x_set_int_status(device_t, uint32_t);
+
+/*
+ * GPIO interface
+ */
+static int rt305x_gpio_pin_max(device_t dev, int *maxpin);
+static int rt305x_gpio_pin_getcaps(device_t dev, uint32_t pin, uint32_t *caps);
+static int rt305x_gpio_pin_getflags(device_t dev, uint32_t pin, uint32_t
+ *flags);
+static int rt305x_gpio_pin_getname(device_t dev, uint32_t pin, char *name);
+static int rt305x_gpio_pin_setflags(device_t dev, uint32_t pin, uint32_t flags);
+static int rt305x_gpio_pin_set(device_t dev, uint32_t pin, unsigned int value);
+static int rt305x_gpio_pin_get(device_t dev, uint32_t pin, unsigned int *val);
+static int rt305x_gpio_pin_toggle(device_t dev, uint32_t pin);
+
+static void
+rt305x_gpio_pin_configure(struct rt305x_gpio_softc *sc, struct gpio_pin *pin,
+ unsigned int flags)
+{
+ GPIO_LOCK(sc);
+
+ /*
+ * Manage input/output
+ */
+ if (flags & (GPIO_PIN_INPUT|GPIO_PIN_OUTPUT)) {
+ pin->gp_flags &= ~(GPIO_PIN_INPUT|GPIO_PIN_OUTPUT);
+ if (flags & GPIO_PIN_OUTPUT) {
+ pin->gp_flags |= GPIO_PIN_OUTPUT;
+ GPIO_BIT_SET(sc, pin->gp_pin, DIR);
+ }
+ else {
+ pin->gp_flags |= GPIO_PIN_INPUT;
+ GPIO_BIT_CLR(sc, pin->gp_pin, DIR);
+ }
+ }
+
+ if (flags & GPIO_PIN_INVOUT) {
+ pin->gp_flags |= GPIO_PIN_INVOUT;
+ GPIO_BIT_SET(sc, pin->gp_pin, POL);
+ }
+ else {
+ pin->gp_flags &= ~GPIO_PIN_INVOUT;
+ GPIO_BIT_CLR(sc, pin->gp_pin, POL);
+ }
+
+ if (flags & GPIO_PIN_INVIN) {
+ pin->gp_flags |= GPIO_PIN_INVIN;
+ GPIO_BIT_SET(sc, pin->gp_pin, POL);
+ }
+ else {
+ pin->gp_flags &= ~GPIO_PIN_INVIN;
+ GPIO_BIT_CLR(sc, pin->gp_pin, POL);
+ }
+
+#ifdef notyet
+ /* Enable interrupt bits for rising/falling transitions */
+ if (flags & GPIO_PIN_REPORT) {
+ pin->gp_flags |= GPIO_PIN_REPORT;
+ GPIO_BIT_SET(sc, pin->gp_pin, RENA);
+ GPIO_BIT_SET(sc, pin->gp_pin, FENA);
+ device_printf(sc->dev, "Will report interrupt on pin %d\n",
+ pin->gp_pin);
+
+ }
+ else {
+ pin->gp_flags &= ~GPIO_PIN_REPORT;
+ GPIO_BIT_CLR(sc, pin->gp_pin, RENA);
+ GPIO_BIT_CLR(sc, pin->gp_pin, FENA);
+ }
+#else
+ /* Disable generating interrupts for now */
+ GPIO_BIT_CLR(sc, pin->gp_pin, RENA);
+ GPIO_BIT_CLR(sc, pin->gp_pin, FENA);
+#endif
+
+ GPIO_UNLOCK(sc);
+}
+
+static int
+rt305x_gpio_pin_max(device_t dev, int *maxpin)
+{
+
+ *maxpin = NGPIO - 1;
+ return (0);
+}
+
+static int
+rt305x_gpio_pin_getcaps(device_t dev, uint32_t pin, uint32_t *caps)
+{
+ struct rt305x_gpio_softc *sc = device_get_softc(dev);
+ int i;
+
+ for (i = 0; i < sc->gpio_npins; i++) {
+ if (sc->gpio_pins[i].gp_pin == pin)
+ break;
+ }
+
+ if (i >= sc->gpio_npins)
+ return (EINVAL);
+
+ GPIO_LOCK(sc);
+ *caps = sc->gpio_pins[i].gp_caps;
+ GPIO_UNLOCK(sc);
+
+ return (0);
+}
+
+static int
+rt305x_gpio_pin_getflags(device_t dev, uint32_t pin, uint32_t *flags)
+{
+ struct rt305x_gpio_softc *sc = device_get_softc(dev);
+ int i;
+
+ for (i = 0; i < sc->gpio_npins; i++) {
+ if (sc->gpio_pins[i].gp_pin == pin)
+ break;
+ }
+
+ if (i >= sc->gpio_npins)
+ return (EINVAL);
+
+ GPIO_LOCK(sc);
+ *flags = sc->gpio_pins[i].gp_flags;
+ GPIO_UNLOCK(sc);
+
+ return (0);
+}
+
+static int
+rt305x_gpio_pin_getname(device_t dev, uint32_t pin, char *name)
+{
+ struct rt305x_gpio_softc *sc = device_get_softc(dev);
+ int i;
+
+ for (i = 0; i < sc->gpio_npins; i++) {
+ if (sc->gpio_pins[i].gp_pin == pin)
+ break;
+ }
+
+ if (i >= sc->gpio_npins)
+ return (EINVAL);
+
+ GPIO_LOCK(sc);
+ memcpy(name, sc->gpio_pins[i].gp_name, GPIOMAXNAME);
+ GPIO_UNLOCK(sc);
+
+ return (0);
+}
+
+static int
+rt305x_gpio_pin_setflags(device_t dev, uint32_t pin, uint32_t flags)
+{
+ int i;
+ struct rt305x_gpio_softc *sc = device_get_softc(dev);
+
+ for (i = 0; i < sc->gpio_npins; i++) {
+ if (sc->gpio_pins[i].gp_pin == pin)
+ break;
+ }
+
+ if (i >= sc->gpio_npins)
+ return (EINVAL);
+
+ rt305x_gpio_pin_configure(sc, &sc->gpio_pins[i], flags);
+
+ return (0);
+}
+
+static int
+rt305x_gpio_pin_set(device_t dev, uint32_t pin, unsigned int value)
+{
+ struct rt305x_gpio_softc *sc = device_get_softc(dev);
+ int i;
+
+ for (i = 0; i < sc->gpio_npins; i++) {
+ if (sc->gpio_pins[i].gp_pin == pin)
+ break;
+ }
+
+ if (i >= sc->gpio_npins)
+ return (EINVAL);
+
+
+ GPIO_LOCK(sc);
+ if (value) GPIO_BIT_SET(sc, i, DATA);
+ else GPIO_BIT_CLR(sc, i, DATA);
+ GPIO_UNLOCK(sc);
+
+ return (0);
+}
+
+static int
+rt305x_gpio_pin_get(device_t dev, uint32_t pin, unsigned int *val)
+{
+ struct rt305x_gpio_softc *sc = device_get_softc(dev);
+ int i;
+
+ for (i = 0; i < sc->gpio_npins; i++) {
+ if (sc->gpio_pins[i].gp_pin == pin)
+ break;
+ }
+
+ if (i >= sc->gpio_npins)
+ return (EINVAL);
+
+ GPIO_LOCK(sc);
+ *val = GPIO_BIT_GET(sc, i, DATA);
+ GPIO_UNLOCK(sc);
+
+ return (0);
+}
+
+static int
+rt305x_gpio_pin_toggle(device_t dev, uint32_t pin)
+{
+ int i;
+ struct rt305x_gpio_softc *sc = device_get_softc(dev);
+
+ for (i = 0; i < sc->gpio_npins; i++) {
+ if (sc->gpio_pins[i].gp_pin == pin)
+ break;
+ }
+
+ if (i >= sc->gpio_npins)
+ return (EINVAL);
+
+ GPIO_LOCK(sc);
+ GPIO_BIT_SET(sc, i, TOG);
+ GPIO_UNLOCK(sc);
+
+ return (0);
+}
+
+static int
+rt305x_gpio_intr(void *arg)
+{
+ struct rt305x_gpio_softc *sc = arg;
+#ifdef notyet
+ uint32_t i;
+#endif
+ uint64_t input, value;
+#ifdef notyet
+ uint64_t reset_pin;
+ char notify[16];
+ char pinname[6];
+#endif
+
+ /* Read all reported pins */
+ input = GPIO_READ_ALL(sc, INT);
+ /* Clear int status */
+ GPIO_WRITE_ALL(sc, INT, input);
+ /* Clear report for OUTs */
+ input &= ~GPIO_READ_ALL(sc, DIR);
+ value = input & GPIO_READ_ALL(sc, DATA);
+
+ if (!input) goto intr_done;
+
+#ifdef notyet
+ /* if reset_gpio and this pin is input */
+ if (sc->reset_gpio >= 0 && (input & (1 << sc->reset_gpio))) {
+ /* get reset_gpio pin value */
+ reset_pin = (value & (1 << sc->reset_gpio))?1:0;
+ if ( sc->reset_gpio_last != reset_pin ) {
+ /*
+ * if now reset is high, check how long
+ * and do reset if less than 2 seconds
+ */
+ if ( reset_pin &&
+ (time_uptime - sc->reset_gpio_ontime) < 2 )
+ shutdown_nice(0);
+
+ sc->reset_gpio_last = reset_pin;
+ sc->reset_gpio_ontime = time_uptime;
+ }
+ }
+
+ for ( i = 0; i < NGPIO; i ++ )
+ {
+ /* Next if output pin */
+ if ( !(( input >> i) & 1) ) continue;
+
+ if ( (((value & input) >> i) & 1) != sc->gpio_pins[i].gp_last )
+ {
+ /* !system=GPIO subsystem=pin7 type=PIN_HIGH period=3 */
+ snprintf(notify , sizeof(notify ), "period=%d",
+ (uint32_t)time_uptime - sc->gpio_pins[i].gp_time);
+ snprintf(pinname, sizeof(pinname), "pin%02d", i);
+ devctl_notify("GPIO", pinname,
+ (((value & input) >> i) & 1)?"PIN_HIGH":"PIN_LOW",
+ notify);
+ printf("GPIO[%s] %s %s\n", pinname,
+ (((value & input) >> i) & 1)?"PIN_HIGH":"PIN_LOW",
+ notify);
+ sc->gpio_pins[i].gp_last = ((value & input) >> i) & 1;
+ sc->gpio_pins[i].gp_time = time_uptime;
+ }
+
+ }
+#endif
+
+intr_done:
+ return (FILTER_HANDLED);
+}
+
+static int
+rt305x_gpio_probe(device_t dev)
+{
+ device_set_desc(dev, "RT305X GPIO driver");
+ return (0);
+}
+
+static uint64_t
+rt305x_gpio_init(device_t dev)
+{
+ uint64_t avl = ~0ULL;
+ uint32_t gmode = rt305x_sysctl_get(SYSCTL_GPIOMODE);
+ if (!(gmode & SYSCTL_GPIOMODE_RGMII_GPIO_MODE))
+ avl &= ~RGMII_GPIO_MODE_MASK;
+ if (!(gmode & SYSCTL_GPIOMODE_SDRAM_GPIO_MODE))
+ avl &= ~SDRAM_GPIO_MODE_MASK;
+ if (!(gmode & SYSCTL_GPIOMODE_MDIO_GPIO_MODE))
+ avl &= ~MDIO_GPIO_MODE_MASK;
+ if (!(gmode & SYSCTL_GPIOMODE_JTAG_GPIO_MODE))
+ avl &= ~JTAG_GPIO_MODE_MASK;
+ if (!(gmode & SYSCTL_GPIOMODE_UARTL_GPIO_MODE))
+ avl &= ~UARTL_GPIO_MODE_MASK;
+ if (!(gmode & SYSCTL_GPIOMODE_SPI_GPIO_MODE))
+ avl &= ~SPI_GPIO_MODE_MASK;
+ if (!(gmode & SYSCTL_GPIOMODE_I2C_GPIO_MODE))
+ avl &= ~I2C_GPIO_MODE_MASK;
+ if ((gmode & SYSCTL_GPIOMODE_UARTF_SHARE_MODE_GPIO) !=
+ SYSCTL_GPIOMODE_UARTF_SHARE_MODE_GPIO)
+ avl &= ~I2C_GPIO_MODE_MASK;
+/* D-Link DAP-1350 Board have
+ * MDIO_GPIO_MODE
+ * UARTF_GPIO_MODE
+ * SPI_GPIO_MODE
+ * I2C_GPIO_MODE
+ * So we have
+ * 00000001 10000000 01111111 11111110
+*/
+ return (avl);
+
+}
+
+#define DAP1350_RESET_GPIO 10
+
+static int
+rt305x_gpio_attach(device_t dev)
+{
+ struct rt305x_gpio_softc *sc = device_get_softc(dev);
+ int error = 0, i;
+ uint64_t avlpins = 0;
+ sc->reset_gpio = DAP1350_RESET_GPIO;
+
+ KASSERT((device_get_unit(dev) == 0),
+ ("rt305x_gpio_gpio: Only one gpio module supported"));
+
+ mtx_init(&sc->gpio_mtx, device_get_nameunit(dev), NULL, MTX_DEF);
+
+ /* Map control/status registers. */
+ sc->gpio_mem_rid = 0;
+ sc->gpio_mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY,
+ &sc->gpio_mem_rid, RF_ACTIVE);
+
+ if (sc->gpio_mem_res == NULL) {
+ device_printf(dev, "couldn't map memory\n");
+ error = ENXIO;
+ rt305x_gpio_detach(dev);
+ return(error);
+ }
+
+ if ((sc->gpio_irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ,
+ &sc->gpio_irq_rid, RF_SHAREABLE | RF_ACTIVE)) == NULL) {
+ device_printf(dev, "unable to allocate IRQ resource\n");
+ return (ENXIO);
+ }
+
+ if ((bus_setup_intr(dev, sc->gpio_irq_res, INTR_TYPE_MISC,
+ /* rt305x_gpio_filter, */
+ rt305x_gpio_intr, NULL, sc, &sc->gpio_ih))) {
+ device_printf(dev,
+ "WARNING: unable to register interrupt handler\n");
+ return (ENXIO);
+ }
+
+ sc->dev = dev;
+ avlpins = rt305x_gpio_init(dev);
+
+ /* Configure all pins as input */
+ /* disable interrupts for all pins */
+ /* TODO */
+
+ sc->gpio_npins = NGPIO;
+ resource_int_value(device_get_name(dev), device_get_unit(dev),
+ "pins", &sc->gpio_npins);
+
+ for (i = 0; i < sc->gpio_npins; i++) {
+ sc->gpio_pins[i].gp_pin = i;
+ sc->gpio_pins[i].gp_caps = DEFAULT_CAPS;
+ sc->gpio_pins[i].gp_flags = 0;
+ }
+
+ /* Setup reset pin interrupt */
+ if (TUNABLE_INT_FETCH("reset_gpio", &sc->reset_gpio)) {
+ device_printf(dev, "\tHinted reset_gpio %d\n", sc->reset_gpio);
+ }
+#ifdef notyet
+ if (sc->reset_gpio != -1) {
+ rt305x_gpio_pin_setflags(dev, sc->reset_gpio,
+ GPIO_PIN_INPUT|GPIO_PIN_INVOUT|
+ GPIO_PIN_INVOUT|GPIO_PIN_REPORT);
+ device_printf(dev, "\tUse reset_gpio %d\n", sc->reset_gpio);
+ }
+#else
+ if (sc->reset_gpio != -1) {
+ rt305x_gpio_pin_setflags(dev, sc->reset_gpio,
+ GPIO_PIN_INPUT|GPIO_PIN_INVOUT);
+ device_printf(dev, "\tUse reset_gpio %d\n", sc->reset_gpio);
+ }
+#endif
+
+ device_add_child(dev, "gpioc", -1);
+ device_add_child(dev, "gpiobus", -1);
+
+ return (bus_generic_attach(dev));
+}
+
+static int
+rt305x_gpio_detach(device_t dev)
+{
+ struct rt305x_gpio_softc *sc = device_get_softc(dev);
+
+ KASSERT(mtx_initialized(&sc->gpio_mtx), ("gpio mutex not initialized"));
+
+ bus_generic_detach(dev);
+
+ if (sc->gpio_mem_res)
+ bus_release_resource(dev, SYS_RES_MEMORY, sc->gpio_mem_rid,
+ sc->gpio_mem_res);
+
+ mtx_destroy(&sc->gpio_mtx);
+
+ return(0);
+}
+
+#ifdef notyet
+static struct resource *
+rt305x_gpio_alloc_resource(device_t bus, device_t child, int type, int *rid,
+ u_long start, u_long end, u_long count, u_int flags)
+{
+ struct obio_softc *sc = device_get_softc(bus);
+ struct resource *rv;
+ struct rman *rm;
+
+ switch (type) {
+ case SYS_RES_GPIO:
+ rm = &sc->gpio_rman;
+ break;
+ default:
+ printf("%s: unknown resource type %d\n", __func__, type);
+ return (0);
+ }
+
+ rv = rman_reserve_resource(rm, start, end, count, flags, child);
+ if (rv == 0) {
+ printf("%s: could not reserve resource\n", __func__);
+ return (0);
+ }
+
+ rman_set_rid(rv, *rid);
+
+ return (rv);
+}
+
+static int
+rt305x_gpio_activate_resource(device_t bus, device_t child, int type, int rid,
+ struct resource *r)
+{
+
+ return (rman_activate_resource(r));
+}
+
+static int
+rt305x_gpio_deactivate_resource(device_t bus, device_t child, int type, int rid,
+ struct resource *r)
+{
+
+ return (rman_deactivate_resource(r));
+}
+
+static int
+rt305x_gpio_release_resource(device_t dev, device_t child, int type,
+ int rid, struct resource *r)
+{
+ rman_release_resource(r);
+ return (0);
+}
+#endif
+
+static device_method_t rt305x_gpio_methods[] = {
+ DEVMETHOD(device_probe, rt305x_gpio_probe),
+ DEVMETHOD(device_attach, rt305x_gpio_attach),
+ DEVMETHOD(device_detach, rt305x_gpio_detach),
+
+ /* GPIO protocol */
+ DEVMETHOD(gpio_pin_max, rt305x_gpio_pin_max),
+ DEVMETHOD(gpio_pin_getname, rt305x_gpio_pin_getname),
+ DEVMETHOD(gpio_pin_getflags, rt305x_gpio_pin_getflags),
+ DEVMETHOD(gpio_pin_getcaps, rt305x_gpio_pin_getcaps),
+ DEVMETHOD(gpio_pin_setflags, rt305x_gpio_pin_setflags),
+ DEVMETHOD(gpio_pin_get, rt305x_gpio_pin_get),
+ DEVMETHOD(gpio_pin_set, rt305x_gpio_pin_set),
+ DEVMETHOD(gpio_pin_toggle, rt305x_gpio_pin_toggle),
+ {0, 0},
+};
+
+static driver_t rt305x_gpio_driver = {
+ "gpio",
+ rt305x_gpio_methods,
+ sizeof(struct rt305x_gpio_softc),
+};
+static devclass_t rt305x_gpio_devclass;
+
+DRIVER_MODULE(rt305x_gpio, obio, rt305x_gpio_driver,
+ rt305x_gpio_devclass, 0, 0);
Property changes on: trunk/sys/mips/rt305x/rt305x_gpio.c
___________________________________________________________________
Added: svn:eol-style
## -0,0 +1 ##
+native
\ No newline at end of property
Added: svn:keywords
## -0,0 +1 ##
+MidnightBSD=%H
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+text/plain
\ No newline at end of property
Added: trunk/sys/mips/rt305x/rt305x_gpio.h
===================================================================
--- trunk/sys/mips/rt305x/rt305x_gpio.h (rev 0)
+++ trunk/sys/mips/rt305x/rt305x_gpio.h 2018-05-26 21:55:02 UTC (rev 9987)
@@ -0,0 +1,112 @@
+/* $MidnightBSD$ */
+/*-
+ * Copyright (c) 2010 Aleksandr Rybalko.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ * $FreeBSD: stable/10/sys/mips/rt305x/rt305x_gpio.h 220297 2011-04-03 14:39:55Z adrian $
+ */
+#ifndef _RT305X_GPIO_H_
+#define _RT305X_GPIO_H_
+
+#define NGPIO 52
+
+#define RGMII_GPIO_MODE_MASK (0x0fffULL<<40)
+#define SDRAM_GPIO_MODE_MASK (0xffffULL<<24)
+#define MDIO_GPIO_MODE_MASK (0x0003ULL<<22)
+#define JTAG_GPIO_MODE_MASK (0x001fULL<<17)
+#define UARTL_GPIO_MODE_MASK (0x0003ULL<<15)
+#define UARTF_GPIO_MODE_MASK (0x00ffULL<<7)
+#define SPI_GPIO_MODE_MASK (0x000fULL<<3)
+#define I2C_GPIO_MODE_MASK (0x0003ULL<<1)
+
+#define GPIO23_00_INT 0x00 /* Programmed I/O Int Status */
+#define GPIO23_00_EDGE 0x04 /* Programmed I/O Edge Status */
+#define GPIO23_00_RENA 0x08 /* Programmed I/O Int on Rising */
+#define GPIO23_00_FENA 0x0C /* Programmed I/O Int on Falling */
+#define GPIO23_00_DATA 0x20 /* Programmed I/O Data */
+#define GPIO23_00_DIR 0x24 /* Programmed I/O Direction */
+#define GPIO23_00_POL 0x28 /* Programmed I/O Pin Polarity */
+#define GPIO23_00_SET 0x2C /* Set PIO Data Bit */
+#define GPIO23_00_RESET 0x30 /* Clear PIO Data bit */
+#define GPIO23_00_TOG 0x34 /* Toggle PIO Data bit */
+
+#define GPIO39_24_INT 0x38
+#define GPIO39_24_EDGE 0x3c
+#define GPIO39_24_RENA 0x40
+#define GPIO39_24_FENA 0x44
+#define GPIO39_24_DATA 0x48
+#define GPIO39_24_DIR 0x4c
+#define GPIO39_24_POL 0x50
+#define GPIO39_24_SET 0x54
+#define GPIO39_24_RESET 0x58
+#define GPIO39_24_TOG 0x5c
+
+#define GPIO51_40_INT 0x60
+#define GPIO51_40_EDGE 0x64
+#define GPIO51_40_RENA 0x68
+#define GPIO51_40_FENA 0x6C
+#define GPIO51_40_DATA 0x70
+#define GPIO51_40_DIR 0x74
+#define GPIO51_40_POL 0x78
+#define GPIO51_40_SET 0x7C
+#define GPIO51_40_RESET 0x80
+#define GPIO51_40_TOG 0x84
+
+#define GPIO_REG(g, n) \
+ ((g<24)?(GPIO23_00_##n):(g<40)?(GPIO39_24_##n):(GPIO51_40_##n))
+#define GPIO_MASK(g) \
+ ((g<24)?(1<<g):(g<40)?(1<<(g-24)):(1<<(g-40)))
+#define GPIO_BIT_SHIFT(g) ((g<24)?(g):(g<40)?(g-24):(g-40))
+
+#define GPIO_READ(r, g, n) \
+ bus_read_4(r->gpio_mem_res, GPIO_REG(g, n))
+#define GPIO_WRITE(r, g, n, v) \
+ bus_write_4(r->gpio_mem_res, GPIO_REG(g, n), v)
+#define GPIO_READ_ALL(r, n) \
+ (((uint64_t)bus_read_4(r->gpio_mem_res, GPIO23_00_##n)) | \
+ (((uint64_t)bus_read_4(r->gpio_mem_res, GPIO39_24_##n)) << 24) |\
+ (((uint64_t)bus_read_4(r->gpio_mem_res, GPIO51_40_##n)) << 40))
+#define GPIO_WRITE_ALL(r, n, v) \
+ {bus_write_4(r->gpio_mem_res,GPIO23_00_##n, v &0x00ffffff);\
+ bus_write_4(r->gpio_mem_res, GPIO39_24_##n, (v>>24)&0x0000ffff);\
+ bus_write_4(r->gpio_mem_res, GPIO51_40_##n, (v>>40)&0x00000fff);}
+
+
+#define GPIO_BIT_CLR(r, g, n) \
+ bus_write_4(r->gpio_mem_res, GPIO_REG(g, n), \
+ bus_read_4(r->gpio_mem_res, GPIO_REG(g, n)) & ~GPIO_MASK(g))
+#define GPIO_BIT_SET(r, g, n) \
+ bus_write_4(r->gpio_mem_res, GPIO_REG(g, n), \
+ bus_read_4(r->gpio_mem_res, GPIO_REG(g, n)) | GPIO_MASK(g))
+
+#define GPIO_BIT_GET(r, g, n) \
+ ((bus_read_4(r->gpio_mem_res, GPIO_REG(g, n)) >> \
+ GPIO_BIT_SHIFT(g)) & 1)
+
+#define GPIO_LOCK(_sc) mtx_lock(&(_sc)->gpio_mtx)
+#define GPIO_UNLOCK(_sc) mtx_unlock(&(_sc)->gpio_mtx)
+#define GPIO_LOCK_ASSERT(_sc) mtx_assert(&(_sc)->gpio_mtx, MA_OWNED)
+
+#endif /* _RT305X_GPIO_H_ */
+
Property changes on: trunk/sys/mips/rt305x/rt305x_gpio.h
___________________________________________________________________
Added: svn:eol-style
## -0,0 +1 ##
+native
\ No newline at end of property
Added: svn:keywords
## -0,0 +1 ##
+MidnightBSD=%H
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+text/plain
\ No newline at end of property
Added: trunk/sys/mips/rt305x/rt305x_gpiovar.h
===================================================================
--- trunk/sys/mips/rt305x/rt305x_gpiovar.h (rev 0)
+++ trunk/sys/mips/rt305x/rt305x_gpiovar.h 2018-05-26 21:55:02 UTC (rev 9987)
@@ -0,0 +1,49 @@
+/* $MidnightBSD$ */
+/*-
+ * Copyright (c) 2010 Aleksandr Rybalko.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ * $FreeBSD: stable/10/sys/mips/rt305x/rt305x_gpiovar.h 220297 2011-04-03 14:39:55Z adrian $
+ */
+#ifndef _RT305X_GPIOVAR_H_
+#define _RT305X_GPIOVAR_H_
+
+struct rt305x_gpio_softc {
+ device_t dev;
+ struct mtx gpio_mtx;
+ struct resource *gpio_mem_res;
+ int gpio_mem_rid;
+ struct resource *gpio_irq_res;
+ int gpio_irq_rid;
+ void *gpio_ih;
+ int gpio_npins;
+ struct gpio_pin gpio_pins[NGPIO];
+ int reset_gpio;
+ int reset_gpio_last;
+ time_t reset_gpio_ontime;
+};
+
+#endif /* _RT305X_GPIOVAR_H_ */
+
+
Property changes on: trunk/sys/mips/rt305x/rt305x_gpiovar.h
___________________________________________________________________
Added: svn:eol-style
## -0,0 +1 ##
+native
\ No newline at end of property
Added: svn:keywords
## -0,0 +1 ##
+MidnightBSD=%H
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+text/plain
\ No newline at end of property
Added: trunk/sys/mips/rt305x/rt305x_ic.c
===================================================================
--- trunk/sys/mips/rt305x/rt305x_ic.c (rev 0)
+++ trunk/sys/mips/rt305x/rt305x_ic.c 2018-05-26 21:55:02 UTC (rev 9987)
@@ -0,0 +1,142 @@
+/* $MidnightBSD$ */
+/*-
+ * Copyright (c) 2010 Aleksandr Rybalko.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ */
+
+#include <sys/cdefs.h>
+__FBSDID("$FreeBSD: stable/10/sys/mips/rt305x/rt305x_ic.c 220297 2011-04-03 14:39:55Z adrian $");
+
+#include <sys/param.h>
+#include <sys/systm.h>
+#include <sys/bus.h>
+#include <sys/interrupt.h>
+#include <sys/kernel.h>
+#include <sys/module.h>
+#include <sys/rman.h>
+#include <sys/malloc.h>
+
+#include <machine/bus.h>
+
+#include <mips/rt305x/rt305xreg.h>
+#include <mips/rt305x/rt305x_icvar.h>
+
+
+static int rt305x_ic_probe(device_t);
+static int rt305x_ic_attach(device_t);
+static int rt305x_ic_detach(device_t);
+
+
+static struct rt305x_ic_softc *rt305x_ic_softc = NULL;
+
+static int
+rt305x_ic_probe(device_t dev)
+{
+ device_set_desc(dev, "RT305X Interrupt Controller driver");
+ return (0);
+}
+
+static int
+rt305x_ic_attach(device_t dev)
+{
+ struct rt305x_ic_softc *sc = device_get_softc(dev);
+ int error = 0;
+
+ KASSERT((device_get_unit(dev) == 0),
+ ("rt305x_ic: Only one Interrupt Controller module supported"));
+
+ if (rt305x_ic_softc != NULL)
+ return (ENXIO);
+ rt305x_ic_softc = sc;
+
+
+ /* Map control/status registers. */
+ sc->mem_rid = 0;
+ sc->mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY,
+ &sc->mem_rid, RF_ACTIVE);
+
+ if (sc->mem_res == NULL) {
+ device_printf(dev, "couldn't map memory\n");
+ error = ENXIO;
+ rt305x_ic_detach(dev);
+ return(error);
+ }
+ return (bus_generic_attach(dev));
+}
+
+static int
+rt305x_ic_detach(device_t dev)
+{
+ struct rt305x_ic_softc *sc = device_get_softc(dev);
+
+ bus_generic_detach(dev);
+
+ if (sc->mem_res)
+ bus_release_resource(dev, SYS_RES_MEMORY, sc->mem_rid,
+ sc->mem_res);
+ return(0);
+}
+
+
+uint32_t
+rt305x_ic_get(uint32_t reg)
+{
+ struct rt305x_ic_softc *sc = rt305x_ic_softc;
+
+ if (!sc)
+ return (0);
+
+ return (bus_read_4(sc->mem_res, reg));
+}
+
+void
+rt305x_ic_set(uint32_t reg, uint32_t val)
+{
+ struct rt305x_ic_softc *sc = rt305x_ic_softc;
+
+ if (!sc)
+ return;
+
+ bus_write_4(sc->mem_res, reg, val);
+
+ return;
+}
+
+
+static device_method_t rt305x_ic_methods[] = {
+ DEVMETHOD(device_probe, rt305x_ic_probe),
+ DEVMETHOD(device_attach, rt305x_ic_attach),
+ DEVMETHOD(device_detach, rt305x_ic_detach),
+
+ {0, 0},
+};
+
+static driver_t rt305x_ic_driver = {
+ "rt305x_ic",
+ rt305x_ic_methods,
+ sizeof(struct rt305x_ic_softc),
+};
+static devclass_t rt305x_ic_devclass;
+
+DRIVER_MODULE(rt305x_ic, obio, rt305x_ic_driver, rt305x_ic_devclass, 0, 0);
Property changes on: trunk/sys/mips/rt305x/rt305x_ic.c
___________________________________________________________________
Added: svn:eol-style
## -0,0 +1 ##
+native
\ No newline at end of property
Added: svn:keywords
## -0,0 +1 ##
+MidnightBSD=%H
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+text/plain
\ No newline at end of property
Added: trunk/sys/mips/rt305x/rt305x_icvar.h
===================================================================
--- trunk/sys/mips/rt305x/rt305x_icvar.h (rev 0)
+++ trunk/sys/mips/rt305x/rt305x_icvar.h 2018-05-26 21:55:02 UTC (rev 9987)
@@ -0,0 +1,43 @@
+/* $MidnightBSD$ */
+/*-
+ * Copyright (c) 2010 Aleksandr Rybalko.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ * $FreeBSD: stable/10/sys/mips/rt305x/rt305x_icvar.h 220297 2011-04-03 14:39:55Z adrian $
+ */
+#ifndef _RT305X_ICVAR_H_
+#define _RT305X_ICVAR_H_
+
+struct rt305x_ic_softc {
+ device_t dev;
+ struct resource *mem_res;
+ int mem_rid;
+};
+
+
+uint32_t rt305x_ic_get(uint32_t);
+void rt305x_ic_set(uint32_t, uint32_t);
+
+#endif /* _RT305X_ICVAR_H_ */
+
Property changes on: trunk/sys/mips/rt305x/rt305x_icvar.h
___________________________________________________________________
Added: svn:eol-style
## -0,0 +1 ##
+native
\ No newline at end of property
Added: svn:keywords
## -0,0 +1 ##
+MidnightBSD=%H
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+text/plain
\ No newline at end of property
Added: trunk/sys/mips/rt305x/rt305x_machdep.c
===================================================================
--- trunk/sys/mips/rt305x/rt305x_machdep.c (rev 0)
+++ trunk/sys/mips/rt305x/rt305x_machdep.c 2018-05-26 21:55:02 UTC (rev 9987)
@@ -0,0 +1,192 @@
+/* $MidnightBSD$ */
+/*-
+ * Copyright (C) 2010-2011 by Aleksandr Rybalko. All rights reserved.
+ * Copyright (C) 2007 by Oleksandr Tymoshenko. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+ * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+ * IN NO EVENT SHALL THE AUTHOR OR HIS RELATIVES BE LIABLE FOR ANY DIRECT,
+ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF MIND, USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
+ * THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+#include <sys/cdefs.h>
+__FBSDID("$FreeBSD: stable/10/sys/mips/rt305x/rt305x_machdep.c 247297 2013-02-26 01:00:11Z attilio $");
+
+#include "opt_ddb.h"
+
+#include <sys/param.h>
+#include <sys/conf.h>
+#include <sys/kernel.h>
+#include <sys/systm.h>
+#include <sys/imgact.h>
+#include <sys/bio.h>
+#include <sys/buf.h>
+#include <sys/bus.h>
+#include <sys/cpu.h>
+#include <sys/cons.h>
+#include <sys/exec.h>
+#include <sys/ucontext.h>
+#include <sys/proc.h>
+#include <sys/kdb.h>
+#include <sys/ptrace.h>
+#include <sys/reboot.h>
+#include <sys/signalvar.h>
+#include <sys/sysent.h>
+#include <sys/sysproto.h>
+#include <sys/user.h>
+
+#include <vm/vm.h>
+#include <vm/vm_object.h>
+#include <vm/vm_page.h>
+
+#include <machine/cache.h>
+#include <machine/clock.h>
+#include <machine/cpu.h>
+#include <machine/cpuinfo.h>
+#include <machine/cpufunc.h>
+#include <machine/cpuregs.h>
+#include <machine/hwfunc.h>
+#include <machine/intr_machdep.h>
+#include <machine/locore.h>
+#include <machine/md_var.h>
+#include <machine/pte.h>
+#include <machine/sigframe.h>
+#include <machine/trap.h>
+#include <machine/vmparam.h>
+
+#include <mips/rt305x/rt305xreg.h>
+
+extern int *edata;
+extern int *end;
+static char boot1_env[0x1000];
+
+
+void
+platform_cpu_init()
+{
+ /* Nothing special */
+}
+
+static void
+mips_init(void)
+{
+ int i;
+
+ printf("entry: mips_init()\n");
+
+ bootverbose = 1;
+ realmem = btoc(32 << 20);
+
+ for (i = 0; i < 10; i++) {
+ phys_avail[i] = 0;
+ }
+
+ /* phys_avail regions are in bytes */
+ dump_avail[0] = phys_avail[0] = MIPS_KSEG0_TO_PHYS(kernel_kseg0_end);
+ dump_avail[1] = phys_avail[1] = ctob(realmem);
+
+ physmem = realmem;
+
+ init_param1();
+ init_param2(physmem);
+ mips_cpu_init();
+ pmap_bootstrap();
+ mips_proc0_init();
+ mutex_init();
+ kdb_init();
+#ifdef KDB
+ if (boothowto & RB_KDB)
+ kdb_enter(KDB_WHY_BOOTFLAGS, "Boot flags requested debugger");
+#endif
+}
+
+void
+platform_reset(void)
+{
+
+ __asm __volatile("li $25, 0xbf000000");
+ __asm __volatile("j $25");
+}
+
+void
+platform_start(__register_t a0 __unused, __register_t a1 __unused,
+ __register_t a2 __unused, __register_t a3 __unused)
+{
+ vm_offset_t kernend;
+ uint64_t platform_counter_freq = PLATFORM_COUNTER_FREQ;
+ int i;
+ int argc = a0;
+ char **argv = (char **)MIPS_PHYS_TO_KSEG0(a1);
+ char **envp = (char **)MIPS_PHYS_TO_KSEG0(a2);
+
+ /* clear the BSS and SBSS segments */
+ kernend = (vm_offset_t)&end;
+ memset(&edata, 0, kernend - (vm_offset_t)(&edata));
+
+ mips_postboot_fixup();
+
+ /* Initialize pcpu stuff */
+ mips_pcpu0_init();
+
+ /* initialize console so that we have printf */
+ boothowto |= (RB_SERIAL | RB_MULTIPLE); /* Use multiple consoles */
+ boothowto |= (RB_VERBOSE);
+ cninit();
+
+ init_static_kenv(boot1_env, sizeof(boot1_env));
+
+ printf("U-Boot args (from %d args):\n", argc - 1);
+
+ if (argc == 1)
+ printf("\tNone\n");
+
+ for (i = 1; i < argc; i++) {
+ char *n = "argv ", *arg;
+
+ if (i > 99)
+ break;
+
+ if (argv[i])
+ {
+ arg = (char *)(intptr_t)MIPS_PHYS_TO_KSEG0(argv[i]);
+ printf("\targv[%d] = %s\n", i, arg);
+ sprintf(n, "argv%d", i);
+ setenv(n, arg);
+ }
+ }
+
+ printf("Environment:\n");
+
+ for (i = 0; envp[i] ; i++) {
+ char *n, *arg;
+
+ arg = (char *)(intptr_t)MIPS_PHYS_TO_KSEG0(envp[i]);
+ printf("\t%s\n", arg);
+ n = strsep(&arg, "=");
+ if (arg == NULL)
+ setenv(n, "1");
+ else
+ setenv(n, arg);
+ }
+
+
+ mips_init();
+ mips_timer_init_params(platform_counter_freq, 2);
+}
Property changes on: trunk/sys/mips/rt305x/rt305x_machdep.c
___________________________________________________________________
Added: svn:eol-style
## -0,0 +1 ##
+native
\ No newline at end of property
Added: svn:keywords
## -0,0 +1 ##
+MidnightBSD=%H
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+text/plain
\ No newline at end of property
Added: trunk/sys/mips/rt305x/rt305x_sysctl.c
===================================================================
--- trunk/sys/mips/rt305x/rt305x_sysctl.c (rev 0)
+++ trunk/sys/mips/rt305x/rt305x_sysctl.c 2018-05-26 21:55:02 UTC (rev 9987)
@@ -0,0 +1,241 @@
+/* $MidnightBSD$ */
+/*-
+ * Copyright (c) 2010 Aleksandr Rybalko.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ */
+
+#include <sys/cdefs.h>
+__FBSDID("$FreeBSD: stable/10/sys/mips/rt305x/rt305x_sysctl.c 232250 2012-02-28 13:19:34Z gavin $");
+
+#include <sys/param.h>
+#include <sys/systm.h>
+#include <sys/bus.h>
+#include <sys/interrupt.h>
+#include <sys/kernel.h>
+#include <sys/module.h>
+#include <sys/rman.h>
+#include <sys/malloc.h>
+
+#include <machine/bus.h>
+
+#include <mips/rt305x/rt305xreg.h>
+#include <mips/rt305x/rt305x_sysctlvar.h>
+
+
+static int rt305x_sysctl_probe(device_t);
+static int rt305x_sysctl_attach(device_t);
+static int rt305x_sysctl_detach(device_t);
+
+
+static struct rt305x_sysctl_softc *rt305x_sysctl_softc = NULL;
+
+static void
+rt305x_sysctl_dump_config(device_t dev)
+{
+ uint32_t val;
+#define DUMPREG(r) \
+ val = rt305x_sysctl_get(r); printf(" " #r "=%#08x\n", val)
+
+ val = rt305x_sysctl_get(SYSCTL_CHIPID0_3);
+ printf("\tChip ID: \"%c%c%c%c",
+ (val >> 0 ) & 0xff,
+ (val >> 8 ) & 0xff,
+ (val >> 16) & 0xff,
+ (val >> 24) & 0xff);
+ val = rt305x_sysctl_get(SYSCTL_CHIPID4_7);
+ printf("%c%c%c%c\"\n",
+ (val >> 0 ) & 0xff,
+ (val >> 8 ) & 0xff,
+ (val >> 16) & 0xff,
+ (val >> 24) & 0xff);
+
+ DUMPREG(SYSCTL_SYSCFG);
+ if ( val & SYSCTL_SYSCFG_INIC_EE_SDRAM)
+ printf("\tGet SDRAM config from EEPROM\n");
+ if ( val & SYSCTL_SYSCFG_INIC_8MB_SDRAM)
+ printf("\tBootstrap flag is set\n");
+ printf("\tGE0 mode %u\n",
+ ((val & SYSCTL_SYSCFG_GE0_MODE_MASK) >>
+ SYSCTL_SYSCFG_GE0_MODE_SHIFT));
+ if ( val & SYSCTL_SYSCFG_BOOT_ADDR_1F00)
+ printf("\tBoot from 0x1f000000\n");
+ if ( val & SYSCTL_SYSCFG_BYPASS_PLL)
+ printf("\tBypass PLL\n");
+ if ( val & SYSCTL_SYSCFG_BIG_ENDIAN)
+ printf("\tBig Endian\n");
+ if ( val & SYSCTL_SYSCFG_CPU_CLK_SEL_384MHZ)
+ printf("\tClock is 384MHz\n");
+ printf("\tBoot from %u\n",
+ ((val & SYSCTL_SYSCFG_BOOT_FROM_MASK) >>
+ SYSCTL_SYSCFG_BOOT_FROM_SHIFT));
+ printf("\tBootstrap test code %u\n",
+ ((val & SYSCTL_SYSCFG_TEST_CODE_MASK) >>
+ SYSCTL_SYSCFG_TEST_CODE_SHIFT));
+ printf("\tSRAM_CS mode %u\n",
+ ((val & SYSCTL_SYSCFG_SRAM_CS_MODE_MASK) >>
+ SYSCTL_SYSCFG_SRAM_CS_MODE_SHIFT));
+ printf("\t%umA SDRAM_CLK driving\n",
+ (val & SYSCTL_SYSCFG_SDRAM_CLK_DRV)?12:8);
+
+ DUMPREG(SYSCTL_CLKCFG0);
+ printf("\tSDRAM_CLK_SKEW %uns\n", (val >> 30) & 0x03);
+
+ DUMPREG(SYSCTL_CLKCFG1);
+ if ( val & SYSCTL_CLKCFG1_PBUS_DIV_CLK_BY2)
+ printf("\tPbus clock is 1/2 of System clock\n");
+ if ( val & SYSCTL_CLKCFG1_OTG_CLK_EN)
+ printf("\tUSB OTG clock is enabled\n");
+ if ( val & SYSCTL_CLKCFG1_I2S_CLK_EN)
+ printf("\tI2S clock is enabled\n");
+ printf("\tI2S clock is %s\n",
+ (val & SYSCTL_CLKCFG1_I2S_CLK_SEL_EXT)?
+ "external":"internal 15.625MHz");
+ printf("\tI2S clock divider %u\n",
+ ((val & SYSCTL_CLKCFG1_I2S_CLK_DIV_MASK) >>
+ SYSCTL_CLKCFG1_I2S_CLK_DIV_SHIFT));
+ if ( val & SYSCTL_CLKCFG1_PCM_CLK_EN)
+ printf("\tPCM clock is enabled\n");
+
+ printf("\tPCM clock is %s\n",
+ (val & SYSCTL_CLKCFG1_PCM_CLK_SEL_EXT)?
+ "external":"internal 15.625MHz");
+ printf("\tPCM clock divider %u\n",
+ ((val & SYSCTL_CLKCFG1_PCM_CLK_DIV_MASK) >>
+ SYSCTL_CLKCFG1_PCM_CLK_DIV_SHIFT));
+ DUMPREG(SYSCTL_GPIOMODE);
+#undef DUMPREG
+
+ return;
+}
+
+static int
+rt305x_sysctl_probe(device_t dev)
+{
+ device_set_desc(dev, "RT305X System Control driver");
+ return (0);
+}
+
+static int
+rt305x_sysctl_attach(device_t dev)
+{
+ struct rt305x_sysctl_softc *sc = device_get_softc(dev);
+ int error = 0;
+
+ KASSERT((device_get_unit(dev) == 0),
+ ("rt305x_sysctl: Only one sysctl module supported"));
+
+ if (rt305x_sysctl_softc != NULL)
+ return (ENXIO);
+ rt305x_sysctl_softc = sc;
+
+
+ /* Map control/status registers. */
+ sc->mem_rid = 0;
+ sc->mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY,
+ &sc->mem_rid, RF_ACTIVE);
+
+ if (sc->mem_res == NULL) {
+ device_printf(dev, "couldn't map memory\n");
+ error = ENXIO;
+ rt305x_sysctl_detach(dev);
+ return(error);
+ }
+#ifdef notyet
+ sc->irq_rid = 0;
+ if ((sc->irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ,
+ &sc->irq_rid, RF_SHAREABLE | RF_ACTIVE)) == NULL) {
+ device_printf(dev, "unable to allocate IRQ resource\n");
+ return (ENXIO);
+ }
+
+ if ((bus_setup_intr(dev, sc->irq_res, INTR_TYPE_MISC,
+ rt305x_sysctl_intr, NULL, sc, &sc->sysctl_ih))) {
+ device_printf(dev,
+ "WARNING: unable to register interrupt handler\n");
+ return (ENXIO);
+ }
+#endif
+ rt305x_sysctl_dump_config(dev);
+
+ return (bus_generic_attach(dev));
+}
+
+static int
+rt305x_sysctl_detach(device_t dev)
+{
+ struct rt305x_sysctl_softc *sc = device_get_softc(dev);
+
+ bus_generic_detach(dev);
+
+ if (sc->mem_res)
+ bus_release_resource(dev, SYS_RES_MEMORY, sc->mem_rid,
+ sc->mem_res);
+#ifdef notyet
+ if (sc->irq_res)
+ bus_release_resource(dev, SYS_RES_IRQ, sc->irq_rid,
+ sc->irq_res);
+#endif
+ return(0);
+}
+
+#ifdef notyet
+static int
+rt305x_sysctl_intr(void *arg)
+{
+ return (FILTER_HANDLED);
+}
+#endif
+
+uint32_t
+rt305x_sysctl_get(uint32_t reg)
+{
+ struct rt305x_sysctl_softc *sc = rt305x_sysctl_softc;
+ return (bus_read_4(sc->mem_res, reg));
+}
+
+void
+rt305x_sysctl_set(uint32_t reg, uint32_t val)
+{
+ struct rt305x_sysctl_softc *sc = rt305x_sysctl_softc;
+ bus_write_4(sc->mem_res, reg, val);
+ return;
+}
+
+
+static device_method_t rt305x_sysctl_methods[] = {
+ DEVMETHOD(device_probe, rt305x_sysctl_probe),
+ DEVMETHOD(device_attach, rt305x_sysctl_attach),
+ DEVMETHOD(device_detach, rt305x_sysctl_detach),
+
+ {0, 0},
+};
+
+static driver_t rt305x_sysctl_driver = {
+ "rt305x_sysctl",
+ rt305x_sysctl_methods,
+ sizeof(struct rt305x_sysctl_softc),
+};
+static devclass_t rt305x_sysctl_devclass;
+
+DRIVER_MODULE(rt305x_sysctl, obio, rt305x_sysctl_driver, rt305x_sysctl_devclass, 0, 0);
Property changes on: trunk/sys/mips/rt305x/rt305x_sysctl.c
___________________________________________________________________
Added: svn:eol-style
## -0,0 +1 ##
+native
\ No newline at end of property
Added: svn:keywords
## -0,0 +1 ##
+MidnightBSD=%H
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+text/plain
\ No newline at end of property
Added: trunk/sys/mips/rt305x/rt305x_sysctlvar.h
===================================================================
--- trunk/sys/mips/rt305x/rt305x_sysctlvar.h (rev 0)
+++ trunk/sys/mips/rt305x/rt305x_sysctlvar.h 2018-05-26 21:55:02 UTC (rev 9987)
@@ -0,0 +1,46 @@
+/* $MidnightBSD$ */
+/*-
+ * Copyright (c) 2010 Aleksandr Rybalko.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ * $FreeBSD: stable/10/sys/mips/rt305x/rt305x_sysctlvar.h 220297 2011-04-03 14:39:55Z adrian $
+ */
+#ifndef _RT305X_SYSCTLVAR_H_
+#define _RT305X_SYSCTLVAR_H_
+
+struct rt305x_sysctl_softc {
+ device_t dev;
+ struct resource *mem_res;
+ int mem_rid;
+ struct resource *irq_res;
+ int irq_rid;
+ int sysctl_ih;
+};
+
+
+uint32_t rt305x_sysctl_get(uint32_t);
+void rt305x_sysctl_set(uint32_t, uint32_t);
+
+#endif /* _RT305X_SYSCTLVAR_H_ */
+
Property changes on: trunk/sys/mips/rt305x/rt305x_sysctlvar.h
___________________________________________________________________
Added: svn:eol-style
## -0,0 +1 ##
+native
\ No newline at end of property
Added: svn:keywords
## -0,0 +1 ##
+MidnightBSD=%H
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+text/plain
\ No newline at end of property
Added: trunk/sys/mips/rt305x/rt305xreg.h
===================================================================
--- trunk/sys/mips/rt305x/rt305xreg.h (rev 0)
+++ trunk/sys/mips/rt305x/rt305xreg.h 2018-05-26 21:55:02 UTC (rev 9987)
@@ -0,0 +1,369 @@
+/* $MidnightBSD$ */
+/*-
+ * Copyright (c) 2010 Aleksandr Rybalko.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ * $FreeBSD: stable/10/sys/mips/rt305x/rt305xreg.h 220297 2011-04-03 14:39:55Z adrian $
+ */
+
+#ifndef _RT305XREG_H_
+#define _RT305XREG_H_
+
+/* XXX: must move to config */
+#define RT305X 1
+#define RT305XF 1
+#define RT3052F 1
+#define __U_BOOT__ 1
+/* XXX: must move to config */
+
+#ifdef RT3052F
+#define PLATFORM_COUNTER_FREQ (384 * 1000 * 1000)
+#endif
+#ifdef RT3050F
+#define PLATFORM_COUNTER_FREQ (320 * 1000 * 1000)
+#endif
+#ifndef PLATFORM_COUNTER_FREQ
+#error "Nor RT3052F nor RT3050F defined"
+#endif
+
+#define SYSTEM_CLOCK (PLATFORM_COUNTER_FREQ/3)
+
+
+#define SDRAM_BASE 0x00000000
+#define SDRAM_END 0x03FFFFFF
+
+#define SYSCTL_BASE 0x10000000
+#define SYSCTL_END 0x100000FF
+#define TIMER_BASE 0x10000100
+#define TIMER_END 0x100001FF
+#define INTCTL_BASE 0x10000200
+#define INTCTL_END 0x100002FF
+#define MEMCTRL_BASE 0x10000300
+#define MEMCTRL_END 0x100003FF /* SDRAM & Flash/SRAM */
+#define PCM_BASE 0x10000400
+#define PCM_END 0x100004FF
+#define UART_BASE 0x10000500
+#define UART_END 0x100005FF
+#define PIO_BASE 0x10000600
+#define PIO_END 0x100006FF
+#define GDMA_BASE 0x10000700
+#define GDMA_END 0x100007FF /* Generic DMA */
+#define NANDFC_BASE 0x10000800
+#define NANDFC_END 0x100008FF /* NAND Flash Controller */
+#define I2C_BASE 0x10000900
+#define I2C_END 0x100009FF
+#define I2S_BASE 0x10000A00
+#define I2S_END 0x10000AFF
+#define SPI_BASE 0x10000B00
+#define SPI_END 0x10000BFF
+#define UARTLITE_BASE 0x10000C00
+#define UARTLITE_END 0x10000CFF
+
+#define FRENG_BASE 0x10100000
+#define FRENG_END 0x1010FFFF /* Frame Engine */
+#define ETHSW_BASE 0x10110000
+#define ETHSW_END 0x10117FFF /* Ethernet Switch */
+#define ROM_BASE 0x10118000
+#define ROM_END 0x10119FFF
+#define WLAN_BASE 0x10180000
+#define WLAN_END 0x101BFFFF /* 802.11n MAC/BBP */
+#define USB_OTG_BASE 0x101C0000
+#define USB_OTG_END 0x101FFFFF
+#define EMEM_BASE 0x1B000000
+#define EMEM_END 0x1BFFFFFF /* External SRAM/Flash */
+#define FLASH_BASE 0x1F000000
+#define FLASH_END 0x1FFFFFFF /* Flash window */
+
+#define OBIO_MEM_BASE SYSCTL_BASE
+#define OBIO_MEM_START OBIO_MEM_BASE
+#define OBIO_MEM_END FLASH_END
+
+
+
+/* System Control */
+#define SYSCTL_CHIPID0_3 0x00 /* 'R''T''3''0' */
+#define SYSCTL_CHIPID4_7 0x04 /* '5''2'' '' ' */
+#define SYSCTL_SYSCFG 0x10
+#define SYSCTL_SYSCFG_INIC_EE_SDRAM (1<<29)
+#define SYSCTL_SYSCFG_INIC_8MB_SDRAM (1<<28)
+#define SYSCTL_SYSCFG_GE0_MODE_MASK 0x03000000
+#define SYSCTL_SYSCFG_GE0_MODE_SHIFT 24
+#define SYSCTL_SYSCFG_GE0_MODE_RGMII 0 /* RGMII Mode */
+#define SYSCTL_SYSCFG_GE0_MODE_MII 1 /* MII Mode */
+#define SYSCTL_SYSCFG_GE0_MODE_REV_MII 2 /*Reversed MII Mode*/
+#define SYSCTL_SYSCFG_BOOT_ADDR_1F00 (1<<22)
+#define SYSCTL_SYSCFG_BYPASS_PLL (1<<21)
+#define SYSCTL_SYSCFG_BIG_ENDIAN (1<<20)
+#define SYSCTL_SYSCFG_CPU_CLK_SEL_384MHZ (1<<18)
+#define SYSCTL_SYSCFG_BOOT_FROM_MASK 0x00030000
+#define SYSCTL_SYSCFG_BOOT_FROM_SHIFT 16
+#define SYSCTL_SYSCFG_BOOT_FROM_FLASH16 0
+#define SYSCTL_SYSCFG_BOOT_FROM_FLASH8 1
+#define SYSCTL_SYSCFG_BOOT_FROM_NANDFLASH 2
+#define SYSCTL_SYSCFG_BOOT_FROM_ROM 3
+#define SYSCTL_SYSCFG_TEST_CODE_MASK 0x0000ff00
+#define SYSCTL_SYSCFG_TEST_CODE_SHIFT 8
+#define SYSCTL_SYSCFG_SRAM_CS_MODE_MASK 0x0000000c
+#define SYSCTL_SYSCFG_SRAM_CS_MODE_SHIFT 2
+#define SYSCTL_SYSCFG_SRAM_CS_MODE_SRAM 0
+#define SYSCTL_SYSCFG_SRAM_CS_MODE_WDOG_RST 1
+#define SYSCTL_SYSCFG_SRAM_CS_MODE_BT_COEX 2
+#define SYSCTL_SYSCFG_SDRAM_CLK_DRV (1<<0) /* 8mA/12mA */
+
+#define SYSCTL_TESTSTAT 0x18
+#define SYSCTL_TESTSTAT2 0x1C
+
+#define SYSCTL_CLKCFG0 0x2C
+#define SYSCTL_CLKCFG0_SDRAM_CLK_SKEW_MASK 0xc0000000
+#define SYSCTL_CLKCFG0_SDRAM_CLK_SKEW_SHIFT 30
+#define SYSCTL_CLKCFG0_SDRAM_CLK_SKEW_ZERO_DELAY 0
+#define SYSCTL_CLKCFG0_SDRAM_CLK_SKEW_1NS_DELAY 1
+#define SYSCTL_CLKCFG0_SDRAM_CLK_SKEW_2NS_DELAY 2
+#define SYSCTL_CLKCFG0_SDRAM_CLK_SKEW_3NS_DELAY 3
+
+#define SYSCTL_CLKCFG1 0x30
+#define SYSCTL_CLKCFG1_PBUS_DIV_CLK_BY2 (1<<30)
+#define SYSCTL_CLKCFG1_OTG_CLK_EN (1<<18)
+#define SYSCTL_CLKCFG1_I2S_CLK_EN (1<<15)
+#define SYSCTL_CLKCFG1_I2S_CLK_SEL_EXT (1<<14)
+#define SYSCTL_CLKCFG1_I2S_CLK_DIV_MASK 0x00003f00
+#define SYSCTL_CLKCFG1_I2S_CLK_DIV_SHIFT 8
+#define SYSCTL_CLKCFG1_PCM_CLK_EN (1<<7)
+#define SYSCTL_CLKCFG1_PCM_CLK_SEL_EXT (1<<6)
+#define SYSCTL_CLKCFG1_PCM_CLK_DIV_MASK 0x0000003f
+#define SYSCTL_CLKCFG1_PCM_CLK_DIV_SHIFT 0
+
+#define SYSCTL_RSTCTRL 0x34
+#define SYSCTL_RSTCTRL_ETHSW (1<<23)
+#define SYSCTL_RSTCTRL_OTG (1<<22)
+#define SYSCTL_RSTCTRL_FRENG (1<<21)
+#define SYSCTL_RSTCTRL_WLAN (1<<20)
+#define SYSCTL_RSTCTRL_UARTL (1<<19)
+#define SYSCTL_RSTCTRL_SPI (1<<18)
+#define SYSCTL_RSTCTRL_I2S (1<<17)
+#define SYSCTL_RSTCTRL_I2C (1<<16)
+#define SYSCTL_RSTCTRL_DMA (1<<14)
+#define SYSCTL_RSTCTRL_PIO (1<<13)
+#define SYSCTL_RSTCTRL_UART (1<<12)
+#define SYSCTL_RSTCTRL_PCM (1<<11)
+#define SYSCTL_RSTCTRL_MC (1<<10)
+#define SYSCTL_RSTCTRL_INTC (1<<9)
+#define SYSCTL_RSTCTRL_TIMER (1<<8)
+#define SYSCTL_RSTCTRL_SYS (1<<0)
+
+#define SYSCTL_RSTSTAT 0x38
+#define SYSCTL_RSTSTAT_SWCPURST (1<<3)
+#define SYSCTL_RSTSTAT_SWSYSRST (1<<2)
+#define SYSCTL_RSTSTAT_WDRST (1<<1)
+
+#define SYSCTL_GPIOMODE 0x60
+#define SYSCTL_GPIOMODE_RGMII_GPIO_MODE (1<<9)
+#define SYSCTL_GPIOMODE_SDRAM_GPIO_MODE (1<<8)
+#define SYSCTL_GPIOMODE_MDIO_GPIO_MODE (1<<7)
+#define SYSCTL_GPIOMODE_JTAG_GPIO_MODE (1<<6)
+#define SYSCTL_GPIOMODE_UARTL_GPIO_MODE (1<<5)
+#define SYSCTL_GPIOMODE_UARTF_SHARE_MODE_UARTF (0<<2)
+#define SYSCTL_GPIOMODE_UARTF_SHARE_MODE_PCM_UARTF (1<<2)
+#define SYSCTL_GPIOMODE_UARTF_SHARE_MODE_PCM_I2S (2<<2)
+#define SYSCTL_GPIOMODE_UARTF_SHARE_MODE_I2S_UARTF (3<<2)
+#define SYSCTL_GPIOMODE_UARTF_SHARE_MODE_PCM_GPIO (4<<2)
+#define SYSCTL_GPIOMODE_UARTF_SHARE_MODE_GPIO_UARTF (5<<2)
+#define SYSCTL_GPIOMODE_UARTF_SHARE_MODE_GPIO_I2S (6<<2)
+#define SYSCTL_GPIOMODE_UARTF_SHARE_MODE_GPIO (7<<2)
+#define SYSCTL_GPIOMODE_SPI_GPIO_MODE (1<<1)
+#define SYSCTL_GPIOMODE_I2C_GPIO_MODE (1<<0)
+
+#define SYSCTL_MEMO0 0x68
+#define SYSCTL_MEMO1 0x6C
+
+/* Timer */
+#define TIMER_TMRSTAT 0x00
+#define TIMER_TMRSTAT_TMR1RST (1<<5)
+#define TIMER_TMRSTAT_TMR0RST (1<<4)
+#define TIMER_TMRSTAT_TMR1INT (1<<1)
+#define TIMER_TMRSTAT_TMR0INT (1<<0)
+#define TIMER_TMR0LOAD 0x10
+#define TIMER_TMR0VAL 0x14
+#define TIMER_TMR0CTL 0x18
+#define TIMER_TMR1LOAD 0x20
+#define TIMER_TMR1VAL 0x24
+#define TIMER_TMR1CTL 0x28
+
+#define TIMER_TMRLOAD_TMR0LOAD_MASK 0xffff
+
+#define TIMER_TMRVAL_TMR0VAL_MASK 0xffff
+
+#define TIMER_TMRCTL_ENABLE (1<<7)
+#define TIMER_TMRCTL_MODE_MASK 0x00000030
+#define TIMER_TMRCTL_MODE_SHIFT 4
+#define TIMER_TMRCTL_MODE_FREE 0
+#define TIMER_TMRCTL_MODE_PERIODIC 1
+#define TIMER_TMRCTL_MODE_TIMOUT 2
+#define TIMER_TMRCTL_MODE_TIMOUT3 3
+#define TIMER_TMRCTL_PRESCALE_MASK 0x0000000f
+#define TIMER_TMRCTL_PRESCALE_SHIFT 0
+#define TIMER_TMRCTL_PRESCALE_NONE 0
+#define TIMER_TMRCTL_PRESCALE_BY_4 1
+#define TIMER_TMRCTL_PRESCALE_BY_8 2
+#define TIMER_TMRCTL_PRESCALE_BY_16 3
+#define TIMER_TMRCTL_PRESCALE_BY_32 4
+#define TIMER_TMRCTL_PRESCALE_BY_64 5
+#define TIMER_TMRCTL_PRESCALE_BY_128 6
+#define TIMER_TMRCTL_PRESCALE_BY_256 7
+#define TIMER_TMRCTL_PRESCALE_BY_512 8
+#define TIMER_TMRCTL_PRESCALE_BY_1K 9
+#define TIMER_TMRCTL_PRESCALE_BY_2K 10
+#define TIMER_TMRCTL_PRESCALE_BY_4K 11
+#define TIMER_TMRCTL_PRESCALE_BY_8K 12
+#define TIMER_TMRCTL_PRESCALE_BY_16K 13
+#define TIMER_TMRCTL_PRESCALE_BY_32K 14
+#define TIMER_TMRCTL_PRESCALE_BY_64K 15
+
+/* Interrupt Controller */
+#define IC_IRQ0STAT 0x00
+#define IC_IRQ1STAT 0x04
+#define IC_INTTYPE 0x20
+#define IC_INTRAW 0x30
+#define IC_INT_ENA 0x34
+#define IC_INT_DIS 0x38
+
+#define IC_OTG 18
+#define IC_ETHSW 17
+#define IC_UARTLITE 12
+#define IC_I2S 10
+#define IC_PERFC 9
+#define IC_NAND 8
+#define IC_DMA 7
+#define IC_PIO 6
+#define IC_UART 5
+#define IC_PCM 4
+#define IC_ILL_ACCESS 3
+#define IC_WDTIMER 2
+#define IC_TIMER0 1
+#define IC_SYSCTL 0
+
+#define IC_LINE_GLOBAL (1<<31) /* Only for DIS/ENA regs */
+#define IC_LINE_OTG (1<<18)
+#define IC_LINE_ETHSW (1<<17)
+#define IC_LINE_UARTLITE (1<<12)
+#define IC_LINE_I2S (1<<10)
+#define IC_LINE_PERFC (1<<9)
+#define IC_LINE_NAND (1<<8)
+#define IC_LINE_DMA (1<<7)
+#define IC_LINE_PIO (1<<6)
+#define IC_LINE_UART (1<<5)
+#define IC_LINE_PCM (1<<4)
+#define IC_LINE_ILL_ACCESS (1<<3)
+#define IC_LINE_WDTIMER (1<<2)
+#define IC_LINE_TIMER0 (1<<1)
+#define IC_LINE_SYSCTL (1<<0)
+
+#define IC_INT_MASK 0x000617ff
+
+/* GPIO */
+
+#define GPIO23_00_INT 0x00 /* Programmed I/O Int Status */
+#define GPIO23_00_EDGE 0x04 /* Programmed I/O Edge Status */
+#define GPIO23_00_RENA 0x08 /* Programmed I/O Int on Rising */
+#define GPIO23_00_FENA 0x0C /* Programmed I/O Int on Falling */
+#define GPIO23_00_DATA 0x20 /* Programmed I/O Data */
+#define GPIO23_00_DIR 0x24 /* Programmed I/O Direction */
+#define GPIO23_00_POL 0x28 /* Programmed I/O Pin Polarity */
+#define GPIO23_00_SET 0x2C /* Set PIO Data Bit */
+#define GPIO23_00_RESET 0x30 /* Clear PIO Data bit */
+#define GPIO23_00_TOG 0x34 /* Toggle PIO Data bit */
+
+#define GPIO39_24_INT 0x38
+#define GPIO39_24_EDGE 0x3c
+#define GPIO39_24_RENA 0x40
+#define GPIO39_24_FENA 0x44
+#define GPIO39_24_DATA 0x48
+#define GPIO39_24_DIR 0x4c
+#define GPIO39_24_POL 0x50
+#define GPIO39_24_SET 0x54
+#define GPIO39_24_RESET 0x58
+#define GPIO39_24_TOG 0x5c
+
+#define GPIO51_40_INT 0x60
+#define GPIO51_40_EDGE 0x64
+#define GPIO51_40_RENA 0x68
+#define GPIO51_40_FENA 0x6C
+#define GPIO51_40_DATA 0x70
+#define GPIO51_40_DIR 0x74
+#define GPIO51_40_POL 0x78
+#define GPIO51_40_SET 0x7C
+#define GPIO51_40_RESET 0x80
+#define GPIO51_40_TOG 0x84
+
+
+
+
+#define GDMA_CHANNEL_REQ0 0
+#define GDMA_CHANNEL_REQ1 1 /* (NAND-flash) */
+#define GDMA_CHANNEL_REQ2 2 /* (I2S) */
+#define GDMA_CHANNEL_REQ3 3 /* (PCM0-RX) */
+#define GDMA_CHANNEL_REQ4 4 /* (PCM1-RX) */
+#define GDMA_CHANNEL_REQ5 5 /* (PCM0-TX) */
+#define GDMA_CHANNEL_REQ6 6 /* (PCM1-TX) */
+#define GDMA_CHANNEL_REQ7 7
+#define GDMA_CHANNEL_MEM 8
+
+/* Generic DMA Controller */
+/* GDMA Channel n Source Address */
+#define GDMASA(n) (0x00 + 0x10*n)
+ /* GDMA Channel n Destination Address */
+#define GDMADA(n) (0x04 + 0x10*n)
+ /* GDMA Channel n Control Register 0 */
+#define GDMACT0(n) (0x08 + 0x10*n)
+
+#define GDMACT0_TR_COUNT_MASK 0x0fff0000
+#define GDMACT0_TR_COUNT_SHIFT 16
+#define GDMACT0_SRC_CHAN_SHIFT 12
+#define GDMACT0_SRC_CHAN_MASK 0x0000f000
+#define GDMACT0_DST_CHAN_SHIFT 8
+#define GDMACT0_DST_CHAN_MASK 0x00000f00
+#define GDMACT0_SRC_BURST_MODE (1<<7)
+#define GDMACT0_DST_BURST_MODE (1<<6)
+#define GDMACT0_BURST_SIZE_SHIFT 3
+#define GDMACT0_BURST_SIZE_MASK 0x00000038
+#define GDMACT0_BURST_SIZE_1 0
+#define GDMACT0_BURST_SIZE_2 1
+#define GDMACT0_BURST_SIZE_4 2
+#define GDMACT0_BURST_SIZE_8 3
+#define GDMACT0_BURST_SIZE_16 4
+
+#define GDMACT0_DONE_INT_EN (1<<2)
+#define GDMACT0_CHAN_EN (1<<1)
+/*
+ * In software mode, the data transfer will start when the Channel Enable bit
+ * is set.
+ * In hardware mode, the data transfer will start when the DMA Request is
+ * asserted.
+*/
+#define GDMACT0_SWMODE (1<<0)
+
+
+
+
+#endif /* _RT305XREG_H_ */
Property changes on: trunk/sys/mips/rt305x/rt305xreg.h
___________________________________________________________________
Added: svn:eol-style
## -0,0 +1 ##
+native
\ No newline at end of property
Added: svn:keywords
## -0,0 +1 ##
+MidnightBSD=%H
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+text/plain
\ No newline at end of property
Added: trunk/sys/mips/rt305x/rt_swreg.h
===================================================================
--- trunk/sys/mips/rt305x/rt_swreg.h (rev 0)
+++ trunk/sys/mips/rt305x/rt_swreg.h 2018-05-26 21:55:02 UTC (rev 9987)
@@ -0,0 +1,161 @@
+/* $MidnightBSD$ */
+/*-
+ * Copyright (c) 2010 Aleksandr Rybalko.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ * $FreeBSD: stable/10/sys/mips/rt305x/rt_swreg.h 220297 2011-04-03 14:39:55Z adrian $
+ */
+
+#ifndef _RT_SWREG_H_
+#define _RT_SWREG_H_
+
+/* XXX: must move to config */
+#define RT3052F
+
+#define RT_SW_BASE 0x10110000
+
+#define RT_SW_ISR 0x00
+
+#define WATCHDOG1_TMR_EXPIRED (1<<29)
+#define WATCHDOG0_TMR_EXPIRED (1<<28)
+#define HAS_INTRUDER (1<<27)
+#define PORT_ST_CHG (1<<26)
+#define BC_STORM (1<<25)
+#define MUST_DROP_LAN (1<<24)
+#define GLOBAL_QUE_FULL (1<<23)
+#define LAN_QUE_FULL6 (1<<20)
+#define LAN_QUE_FULL5 (1<<19)
+#define LAN_QUE_FULL4 (1<<18)
+#define LAN_QUE_FULL3 (1<<17)
+#define LAN_QUE_FULL2 (1<<16)
+#define LAN_QUE_FULL1 (1<<15)
+#define LAN_QUE_FULL0 (1<<14)
+
+#define RT_SW_IMR 0x04
+
+#define RT_SW_FCT0 0x08
+#define RT_SW_FCT1 0x0c
+#define RT_SW_PFC0 0x10
+#define RT_SW_PFC1 0x14
+#define RT_SW_PFC2 0x18
+#define RT_SW_GQS0 0x1c
+#define RT_SW_GQS1 0x20
+#define RT_SW_ATS 0x24
+#define RT_SW_ATS0 0x28
+#define RT_SW_ATS1 0x2c
+#define RT_SW_ATS2 0x30
+#define RT_SW_WMAD0 0x34
+#define RT_SW_WMAD1 0x38
+#define RT_SW_WMAD2 0x3c
+#define RT_SW_PVIDC0 0x40
+#define RT_SW_PVIDC1 0x44
+#define RT_SW_PVIDC2 0x48
+#define RT_SW_PVIDC3 0x4c
+#define RT_SW_VID0 0x50
+#define RT_SW_VID1 0x54
+#define RT_SW_VID2 0x58
+#define RT_SW_VID3 0x5c
+#define RT_SW_VID4 0x60
+#define RT_SW_VID5 0x64
+#define RT_SW_VID6 0x68
+#define RT_SW_VID7 0x6c
+#define RT_SW_VMSC0 0x70
+#define RT_SW_VMSC1 0x74
+#define RT_SW_VMSC2 0x78
+#define RT_SW_VMSC3 0x7c
+#define RT_SW_POA 0x80
+#define RT_SW_FPA 0x84
+#define RT_SW_PTS 0x88
+#define RT_SW_SOCPC 0x8c
+#define RT_SW_POC0 0x90
+#define RT_SW_POC1 0x94
+#define RT_SW_POC2 0x98
+#define RT_SW_SGC 0x9c
+#define RT_SW_STRT 0xa0
+#define RT_SW_LEDP0 0xa4
+#define RT_SW_LEDP1 0xa8
+#define RT_SW_LEDP2 0xac
+#define RT_SW_LEDP3 0xb0
+#define RT_SW_LEDP4 0xb4
+#define RT_SW_WDTR 0xb8
+#define RT_SW_DES 0xbc
+#define RT_SW_PCR0 0xc0
+#define RT_SW_PCR1 0xc4
+#define RT_SW_FPA 0xc8
+#define RT_SW_FCT2 0xcc
+#define RT_SW_QSS0 0xd0
+
+#define RT_SW_QSS1 0xd4
+#define RT_SW_DEC 0xd8
+#define BRIDGE_IPG_SHIFT 24
+#define DEBUG_SW_PORT_SEL_SHIFT 3
+#define DEBUG_SW_PORT_SEL_MASK 0x00000038
+
+#define RT_SW_MTI 0xdc
+#define SKIP_BLOCKS_SHIFT 7
+#define SKIP_BLOCKS_MASK 0x0000ff80
+#define SW_RAM_TEST_DONE (1<<6)
+#define AT_RAM_TEST_DONE (1<<5)
+#define AT_RAM_TEST_FAIL (1<<4)
+#define LK_RAM_TEST_DONE (1<<3)
+#define LK_RAM_TEST_FAIL (1<<2)
+#define DT_RAM_TEST_DONE (1<<1)
+#define DT_RAM_TEST_FAIL (1<<0)
+
+#define RT_SW_PPC 0xe0
+#define SW2FE_CNT_SHIFT 16
+#define FE2SW_CNT_SHIFT 0
+
+#define RT_SW_SGC2 0xe4
+#define FE2SW_WL_FC_EN (1<<30)
+#define LAN_PMAP_P0_IS_LAN (1<<24)
+#define LAN_PMAP_P1_IS_LAN (1<<25)
+#define LAN_PMAP_P2_IS_LAN (1<<26)
+#define LAN_PMAP_P3_IS_LAN (1<<27)
+#define LAN_PMAP_P4_IS_LAN (1<<28)
+#define LAN_PMAP_P5_IS_LAN (1<<29)
+/* Transmit CPU TPID(810x) port bit map */
+#define TX_CPU_TPID_BIT_MAP_SHIFT 16
+#define TX_CPU_TPID_BIT_MAP_MASK 0x007f0000
+#define ARBITER_LAN_EN (1<<11)
+#define CPU_TPID_EN (1<<10)
+#define P0_DOUBLE_TAG_EN (1<<0)
+#define P1_DOUBLE_TAG_EN (1<<1)
+#define P2_DOUBLE_TAG_EN (1<<2)
+#define P3_DOUBLE_TAG_EN (1<<3)
+#define P4_DOUBLE_TAG_EN (1<<4)
+#define P5_DOUBLE_TAG_EN (1<<5)
+
+#define RT_SW_P0PC 0xe8
+#define RT_SW_P1PC 0xec
+#define RT_SW_P2PC 0xf0
+#define RT_SW_P3PC 0xf4
+#define RT_SW_P4PC 0xf8
+#define RT_SW_P5PC 0xfc
+#define BAD_PCOUNT_SHIFT 16
+#define BAD_PCOUNT_MASK 0xffff0000
+#define GOOD_PCOUNT_SHIFT 0
+#define GOOD_PCOUNT_MASK 0x0000ffff
+
+#endif /* _RT_SWREG_H_ */
Property changes on: trunk/sys/mips/rt305x/rt_swreg.h
___________________________________________________________________
Added: svn:eol-style
## -0,0 +1 ##
+native
\ No newline at end of property
Added: svn:keywords
## -0,0 +1 ##
+MidnightBSD=%H
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+text/plain
\ No newline at end of property
Added: trunk/sys/mips/rt305x/std.rt305x
===================================================================
--- trunk/sys/mips/rt305x/std.rt305x (rev 0)
+++ trunk/sys/mips/rt305x/std.rt305x 2018-05-26 21:55:02 UTC (rev 9987)
@@ -0,0 +1,7 @@
+# $FreeBSD: stable/10/sys/mips/rt305x/std.rt305x 232896 2012-03-12 21:25:32Z jmallett $
+# Standard include file for RT305XF SoC
+
+files "../rt305x/files.rt305x"
+
+cpu CPU_MIPS4KC
+
Property changes on: trunk/sys/mips/rt305x/std.rt305x
___________________________________________________________________
Added: mnbsd:nokeywords
## -0,0 +1 ##
+MidnightBSD=%H
\ No newline at end of property
Added: trunk/sys/mips/rt305x/uart_bus_rt305x.c
===================================================================
--- trunk/sys/mips/rt305x/uart_bus_rt305x.c (rev 0)
+++ trunk/sys/mips/rt305x/uart_bus_rt305x.c 2018-05-26 21:55:02 UTC (rev 9987)
@@ -0,0 +1,103 @@
+/* $MidnightBSD$ */
+/*-
+ * Copyright (c) 2007 Bruce M. Simpson.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * $Id$
+ */
+/*
+ * Skeleton of this file was based on respective code for ARM
+ * code written by Olivier Houchard.
+ */
+
+/*
+ * XXXMIPS: This file is hacked from arm/... . XXXMIPS here means this file is
+ * experimental and was written for MIPS32 port.
+ */
+#include "opt_uart.h"
+
+#include <sys/cdefs.h>
+__FBSDID("$FreeBSD: stable/10/sys/mips/rt305x/uart_bus_rt305x.c 220297 2011-04-03 14:39:55Z adrian $");
+
+#include <sys/param.h>
+#include <sys/systm.h>
+#include <sys/bus.h>
+#include <sys/conf.h>
+#include <sys/kernel.h>
+#include <sys/module.h>
+#include <machine/bus.h>
+#include <sys/rman.h>
+#include <machine/resource.h>
+
+#include <dev/pci/pcivar.h>
+
+#include <dev/uart/uart.h>
+#include <dev/uart/uart_bus.h>
+#include <dev/uart/uart_cpu.h>
+
+#include <mips/rt305x/rt305xreg.h>
+
+#include "uart_if.h"
+
+static int uart_rt305x_probe(device_t dev);
+
+extern struct uart_class uart_rt305x_uart_class;
+
+static device_method_t uart_rt305x_methods[] = {
+ /* Device interface */
+ DEVMETHOD(device_probe, uart_rt305x_probe),
+ DEVMETHOD(device_attach, uart_bus_attach),
+ DEVMETHOD(device_detach, uart_bus_detach),
+ { 0, 0 }
+};
+
+static driver_t uart_rt305x_driver = {
+ uart_driver_name,
+ uart_rt305x_methods,
+ sizeof(struct uart_softc),
+};
+
+extern SLIST_HEAD(uart_devinfo_list, uart_devinfo) uart_sysdevs;
+
+static int
+uart_rt305x_probe(device_t dev)
+{
+ struct uart_softc *sc;
+
+ sc = device_get_softc(dev);
+ sc->sc_sysdev = SLIST_FIRST(&uart_sysdevs);
+ sc->sc_class = &uart_rt305x_uart_class;
+ bcopy(&sc->sc_sysdev->bas, &sc->sc_bas, sizeof(sc->sc_bas));
+ sc->sc_sysdev->bas.regshft = 2;
+ sc->sc_sysdev->bas.bst = mips_bus_space_generic;
+ sc->sc_sysdev->bas.bsh =
+ MIPS_PHYS_TO_KSEG1(device_get_unit(dev)?UARTLITE_BASE:UART_BASE);
+ sc->sc_bas.regshft = 2;
+ sc->sc_bas.bst = mips_bus_space_generic;
+ sc->sc_bas.bsh =
+ MIPS_PHYS_TO_KSEG1(device_get_unit(dev)?UARTLITE_BASE:UART_BASE);
+
+ return (uart_bus_probe(dev, 2, SYSTEM_CLOCK, 0, 0));
+}
+
+DRIVER_MODULE(uart, obio, uart_rt305x_driver, uart_devclass, 0, 0);
+
Property changes on: trunk/sys/mips/rt305x/uart_bus_rt305x.c
___________________________________________________________________
Added: svn:eol-style
## -0,0 +1 ##
+native
\ No newline at end of property
Added: svn:keywords
## -0,0 +1 ##
+MidnightBSD=%H
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+text/plain
\ No newline at end of property
Added: trunk/sys/mips/rt305x/uart_cpu_rt305x.c
===================================================================
--- trunk/sys/mips/rt305x/uart_cpu_rt305x.c (rev 0)
+++ trunk/sys/mips/rt305x/uart_cpu_rt305x.c 2018-05-26 21:55:02 UTC (rev 9987)
@@ -0,0 +1,83 @@
+/* $MidnightBSD$ */
+/*-
+ * Copyright (c) 2006 Wojciech A. Koszek <wkoszek at FreeBSD.org>
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ * $Id$
+ */
+/*
+ * Skeleton of this file was based on respective code for ARM
+ * code written by Olivier Houchard.
+ */
+/*
+ * XXXMIPS: This file is hacked from arm/... . XXXMIPS here means this file is
+ * experimental and was written for MIPS32 port.
+ */
+#include "opt_uart.h"
+
+#include <sys/cdefs.h>
+__FBSDID("$FreeBSD: stable/10/sys/mips/rt305x/uart_cpu_rt305x.c 220297 2011-04-03 14:39:55Z adrian $");
+
+#include <sys/param.h>
+#include <sys/systm.h>
+#include <sys/bus.h>
+#include <sys/cons.h>
+
+#include <machine/bus.h>
+
+#include <dev/uart/uart.h>
+#include <dev/uart/uart_cpu.h>
+
+#include <mips/rt305x/rt305xreg.h>
+
+extern struct uart_class uart_rt305x_uart_class;
+bus_space_tag_t uart_bus_space_io;
+bus_space_tag_t uart_bus_space_mem;
+
+int
+uart_cpu_eqres(struct uart_bas *b1, struct uart_bas *b2)
+{
+
+ return ((b1->bsh == b2->bsh && b1->bst == b2->bst) ? 1 : 0);
+}
+
+int
+uart_cpu_getdev(int devtype, struct uart_devinfo *di)
+{
+ di->ops = uart_getops(&uart_rt305x_uart_class);
+ di->bas.chan = 0;
+ di->bas.bst = mips_bus_space_generic;
+ di->bas.regshft = 2;
+ di->bas.rclk = SYSTEM_CLOCK;
+ di->baudrate = 115200;
+ di->databits = 8;
+ di->stopbits = 1;
+
+ di->parity = UART_PARITY_NONE;
+
+ uart_bus_space_io = NULL;
+ uart_bus_space_mem = mips_bus_space_generic;
+ di->bas.bsh = MIPS_PHYS_TO_KSEG1(UARTLITE_BASE);
+ return (0);
+}
Property changes on: trunk/sys/mips/rt305x/uart_cpu_rt305x.c
___________________________________________________________________
Added: svn:eol-style
## -0,0 +1 ##
+native
\ No newline at end of property
Added: svn:keywords
## -0,0 +1 ##
+MidnightBSD=%H
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+text/plain
\ No newline at end of property
Added: trunk/sys/mips/rt305x/uart_dev_rt305x.c
===================================================================
--- trunk/sys/mips/rt305x/uart_dev_rt305x.c (rev 0)
+++ trunk/sys/mips/rt305x/uart_dev_rt305x.c 2018-05-26 21:55:02 UTC (rev 9987)
@@ -0,0 +1,537 @@
+/* $MidnightBSD$ */
+/* $NetBSD: uart.c,v 1.2 2007/03/23 20:05:47 dogcow Exp $ */
+
+/*-
+ * Copyright (c) 2010 Aleksandr Rybalko.
+ * Copyright (c) 2007 Ruslan Ermilov and Vsevolod Lobko.
+ * Copyright (c) 2007 Oleksandr Tymoshenko.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or
+ * without modification, are permitted provided that the following
+ * conditions are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above
+ * copyright notice, this list of conditions and the following
+ * disclaimer in the documentation and/or other materials provided
+ * with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHORS ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
+ * PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHORS
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY,
+ * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
+ * TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
+ * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ */
+
+#include <sys/cdefs.h>
+__FBSDID("$FreeBSD: stable/10/sys/mips/rt305x/uart_dev_rt305x.c 262649 2014-03-01 04:16:54Z imp $");
+
+#include "opt_ddb.h"
+
+#include <sys/param.h>
+#include <sys/systm.h>
+#include <sys/bus.h>
+#include <sys/conf.h>
+#include <sys/kdb.h>
+#include <sys/reboot.h>
+#include <sys/sysctl.h>
+#include <sys/kernel.h>
+#include <machine/bus.h>
+
+#include <dev/uart/uart.h>
+#include <dev/uart/uart_cpu.h>
+#include <dev/uart/uart_bus.h>
+
+#include <mips/rt305x/uart_dev_rt305x.h>
+#include <mips/rt305x/rt305xreg.h>
+
+#include "uart_if.h"
+/*
+ * Low-level UART interface.
+ */
+static int rt305x_uart_probe(struct uart_bas *bas);
+static void rt305x_uart_init(struct uart_bas *bas, int, int, int, int);
+static void rt305x_uart_term(struct uart_bas *bas);
+static void rt305x_uart_putc(struct uart_bas *bas, int);
+static int rt305x_uart_rxready(struct uart_bas *bas);
+static int rt305x_uart_getc(struct uart_bas *bas, struct mtx *);
+
+static struct uart_ops uart_rt305x_uart_ops = {
+ .probe = rt305x_uart_probe,
+ .init = rt305x_uart_init,
+ .term = rt305x_uart_term,
+ .putc = rt305x_uart_putc,
+ .rxready = rt305x_uart_rxready,
+ .getc = rt305x_uart_getc,
+};
+
+static int uart_output = 1;
+TUNABLE_INT("kern.uart_output", &uart_output);
+SYSCTL_INT(_kern, OID_AUTO, uart_output, CTLFLAG_RW,
+ &uart_output, 0, "UART output enabled.");
+
+
+
+
+static int
+rt305x_uart_probe(struct uart_bas *bas)
+{
+
+ return (0);
+}
+
+static void
+rt305x_uart_init(struct uart_bas *bas, int baudrate, int databits,
+ int stopbits, int parity)
+{
+#ifdef notyet
+ /* CLKDIV = 384000000/ 3/ 16/ br */
+ /* for 384MHz CLKDIV = 8000000 / baudrate; */
+ switch (databits) {
+ case 5:
+ databits = UART_LCR_5B;
+ break;
+ case 6:
+ databits = UART_LCR_6B;
+ break;
+ case 7:
+ databits = UART_LCR_7B;
+ break;
+ case 8:
+ databits = UART_LCR_8B;
+ break;
+ default:
+ /* Unsupported */
+ return;
+ }
+ switch (parity) {
+ case UART_PARITY_EVEN: parity = (UART_LCR_PEN|UART_LCR_EVEN); break;
+ case UART_PARITY_NONE: parity = (UART_LCR_PEN); break;
+ case UART_PARITY_ODD: parity = 0; break;
+ /* Unsupported */
+ default: return;
+ }
+ uart_setreg(bas, UART_CDDL_REG, 8000000/baudrate);
+ uart_barrier(bas);
+ uart_setreg(bas, UART_LCR_REG, databits | (stopbits==1?0:4) | parity);
+ uart_barrier(bas);
+#endif
+}
+
+static void
+rt305x_uart_term(struct uart_bas *bas)
+{
+ uart_setreg(bas, UART_MCR_REG, 0);
+ uart_barrier(bas);
+}
+
+static void
+rt305x_uart_putc(struct uart_bas *bas, int c)
+{
+ char chr;
+ if (!uart_output) return;
+ chr = c;
+ while (!(uart_getreg(bas, UART_LSR_REG) & UART_LSR_THRE));
+ uart_setreg(bas, UART_TX_REG, c);
+ uart_barrier(bas);
+ while (!(uart_getreg(bas, UART_LSR_REG) & UART_LSR_THRE));
+}
+
+static int
+rt305x_uart_rxready(struct uart_bas *bas)
+{
+#ifdef notyet
+ if (uart_getreg(bas, UART_LSR_REG) & UART_LSR_DR)
+ return (1);
+
+ return (0);
+#else
+ return (1);
+#endif
+}
+
+static int
+rt305x_uart_getc(struct uart_bas *bas, struct mtx *hwmtx)
+{
+ int c;
+
+ uart_lock(hwmtx);
+
+ while (!(uart_getreg(bas, UART_LSR_REG) & UART_LSR_DR)) {
+ uart_unlock(hwmtx);
+ DELAY(10);
+ uart_lock(hwmtx);
+ }
+
+ c = uart_getreg(bas, UART_RX_REG);
+
+ uart_unlock(hwmtx);
+
+ return (c);
+}
+
+/*
+ * High-level UART interface.
+ */
+struct rt305x_uart_softc {
+ struct uart_softc base;
+};
+
+static int rt305x_uart_bus_attach(struct uart_softc *);
+static int rt305x_uart_bus_detach(struct uart_softc *);
+static int rt305x_uart_bus_flush(struct uart_softc *, int);
+static int rt305x_uart_bus_getsig(struct uart_softc *);
+static int rt305x_uart_bus_ioctl(struct uart_softc *, int, intptr_t);
+static int rt305x_uart_bus_ipend(struct uart_softc *);
+static int rt305x_uart_bus_param(struct uart_softc *, int, int, int, int);
+static int rt305x_uart_bus_probe(struct uart_softc *);
+static int rt305x_uart_bus_receive(struct uart_softc *);
+static int rt305x_uart_bus_setsig(struct uart_softc *, int);
+static int rt305x_uart_bus_transmit(struct uart_softc *);
+static void rt305x_uart_bus_grab(struct uart_softc *);
+static void rt305x_uart_bus_ungrab(struct uart_softc *);
+
+static kobj_method_t rt305x_uart_methods[] = {
+ KOBJMETHOD(uart_attach, rt305x_uart_bus_attach),
+ KOBJMETHOD(uart_detach, rt305x_uart_bus_detach),
+ KOBJMETHOD(uart_flush, rt305x_uart_bus_flush),
+ KOBJMETHOD(uart_getsig, rt305x_uart_bus_getsig),
+ KOBJMETHOD(uart_ioctl, rt305x_uart_bus_ioctl),
+ KOBJMETHOD(uart_ipend, rt305x_uart_bus_ipend),
+ KOBJMETHOD(uart_param, rt305x_uart_bus_param),
+ KOBJMETHOD(uart_probe, rt305x_uart_bus_probe),
+ KOBJMETHOD(uart_receive, rt305x_uart_bus_receive),
+ KOBJMETHOD(uart_setsig, rt305x_uart_bus_setsig),
+ KOBJMETHOD(uart_transmit, rt305x_uart_bus_transmit),
+ KOBJMETHOD(uart_grab, rt305x_uart_bus_grab),
+ KOBJMETHOD(uart_ungrab, rt305x_uart_bus_ungrab),
+ { 0, 0 }
+};
+
+struct uart_class uart_rt305x_uart_class = {
+ "rt305x",
+ rt305x_uart_methods,
+ sizeof(struct rt305x_uart_softc),
+ .uc_ops = &uart_rt305x_uart_ops,
+ .uc_range = 1, /* use hinted range */
+ .uc_rclk = SYSTEM_CLOCK
+};
+
+#define SIGCHG(c, i, s, d) \
+ if (c) { \
+ i |= (i & s) ? s : s | d; \
+ } else { \
+ i = (i & s) ? (i & ~s) | d : i; \
+ }
+
+/*
+ * Disable TX interrupt. uart should be locked
+ */
+static __inline void
+rt305x_uart_disable_txintr(struct uart_softc *sc)
+{
+ struct uart_bas *bas = &sc->sc_bas;
+ uint8_t cr;
+
+ cr = uart_getreg(bas, UART_IER_REG);
+ cr &= ~UART_IER_ETBEI;
+ uart_setreg(bas, UART_IER_REG, cr);
+ uart_barrier(bas);
+}
+
+/*
+ * Enable TX interrupt. uart should be locked
+ */
+static __inline void
+rt305x_uart_enable_txintr(struct uart_softc *sc)
+{
+ struct uart_bas *bas = &sc->sc_bas;
+ uint8_t cr;
+
+ cr = uart_getreg(bas, UART_IER_REG);
+ cr |= UART_IER_ETBEI;
+ uart_setreg(bas, UART_IER_REG, cr);
+ uart_barrier(bas);
+}
+
+static int
+rt305x_uart_bus_attach(struct uart_softc *sc)
+{
+ struct uart_bas *bas;
+ struct uart_devinfo *di;
+
+ bas = &sc->sc_bas;
+ if (sc->sc_sysdev != NULL) {
+ di = sc->sc_sysdev;
+ rt305x_uart_init(bas, di->baudrate, di->databits, di->stopbits,
+ di->parity);
+ } else {
+ rt305x_uart_init(bas, 115200, 8, 1, 0);
+ }
+
+ (void)rt305x_uart_bus_getsig(sc);
+
+ /* Enable FIFO */
+ uart_setreg(bas, UART_FCR_REG,
+ uart_getreg(bas, UART_FCR_REG) |
+ UART_FCR_FIFOEN | UART_FCR_TXTGR_1 | UART_FCR_RXTGR_1);
+ uart_barrier(bas);
+ /* Enable interrupts */
+ uart_setreg(bas, UART_IER_REG,
+ UART_IER_EDSSI | UART_IER_ELSI | UART_IER_ERBFI);
+ uart_barrier(bas);
+
+ return (0);
+}
+
+static int
+rt305x_uart_bus_detach(struct uart_softc *sc)
+{
+
+ return (0);
+}
+
+static int
+rt305x_uart_bus_flush(struct uart_softc *sc, int what)
+{
+ struct uart_bas *bas = &sc->sc_bas;
+ uint32_t fcr = uart_getreg(bas, UART_FCR_REG);
+ if (what & UART_FLUSH_TRANSMITTER) {
+ uart_setreg(bas, UART_FCR_REG, fcr|UART_FCR_TXRST);
+ uart_barrier(bas);
+ }
+ if (what & UART_FLUSH_RECEIVER) {
+ uart_setreg(bas, UART_FCR_REG, fcr|UART_FCR_RXRST);
+ uart_barrier(bas);
+ }
+ uart_setreg(bas, UART_FCR_REG, fcr);
+ uart_barrier(bas);
+ return (0);
+}
+
+static int
+rt305x_uart_bus_getsig(struct uart_softc *sc)
+{
+ uint32_t new, old, sig;
+ uint8_t bes;
+
+ do {
+ old = sc->sc_hwsig;
+ sig = old;
+ uart_lock(sc->sc_hwmtx);
+ bes = uart_getreg(&sc->sc_bas, UART_MSR_REG);
+ uart_unlock(sc->sc_hwmtx);
+ /* XXX: chip can show delta */
+ SIGCHG(bes & UART_MSR_CTS, sig, SER_CTS, SER_DCTS);
+ SIGCHG(bes & UART_MSR_DCD, sig, SER_DCD, SER_DDCD);
+ SIGCHG(bes & UART_MSR_DSR, sig, SER_DSR, SER_DDSR);
+ new = sig & ~SER_MASK_DELTA;
+ } while (!atomic_cmpset_32(&sc->sc_hwsig, old, new));
+
+ return (sig);
+}
+
+static int
+rt305x_uart_bus_ioctl(struct uart_softc *sc, int request, intptr_t data)
+{
+ struct uart_bas *bas;
+ int baudrate, divisor, error;
+
+ bas = &sc->sc_bas;
+ error = 0;
+ uart_lock(sc->sc_hwmtx);
+ switch (request) {
+ case UART_IOCTL_BREAK:
+ /* TODO: Send BREAK */
+ break;
+ case UART_IOCTL_BAUD:
+ divisor = uart_getreg(bas, UART_CDDL_REG);
+ baudrate = bas->rclk / (divisor * 16);
+ *(int*)data = baudrate;
+ break;
+ default:
+ error = EINVAL;
+ break;
+ }
+ uart_unlock(sc->sc_hwmtx);
+ return (error);
+}
+
+static int
+rt305x_uart_bus_ipend(struct uart_softc *sc)
+{
+ struct uart_bas *bas;
+ int ipend;
+ uint8_t iir, lsr, msr;
+
+ bas = &sc->sc_bas;
+ ipend = 0;
+
+ uart_lock(sc->sc_hwmtx);
+ iir = uart_getreg(&sc->sc_bas, UART_IIR_REG);
+ lsr = uart_getreg(&sc->sc_bas, UART_LSR_REG);
+ uart_setreg(&sc->sc_bas, UART_LSR_REG, lsr);
+ msr = uart_getreg(&sc->sc_bas, UART_MSR_REG);
+ uart_setreg(&sc->sc_bas, UART_MSR_REG, msr);
+ if (iir & UART_IIR_INTP) {
+ uart_unlock(sc->sc_hwmtx);
+ return (0);
+ }
+
+
+ switch ((iir >> 1) & 0x07) {
+ case UART_IIR_ID_THRE:
+ ipend |= SER_INT_TXIDLE;
+ break;
+ case UART_IIR_ID_DR2:
+ rt305x_uart_bus_flush(sc, UART_FLUSH_RECEIVER);
+ /* passthrough */
+ case UART_IIR_ID_DR:
+ ipend |= SER_INT_RXREADY;
+ break;
+ case UART_IIR_ID_MST:
+ case UART_IIR_ID_LINESTATUS:
+ ipend |= SER_INT_SIGCHG;
+ if (lsr & UART_LSR_BI)
+ {
+ ipend |= SER_INT_BREAK;
+#ifdef KDB
+ breakpoint();
+#endif
+ }
+ if (lsr & UART_LSR_OE)
+ ipend |= SER_INT_OVERRUN;
+ break;
+ default:
+ /* XXX: maybe return error here */
+ break;
+ }
+
+ uart_unlock(sc->sc_hwmtx);
+
+ return (ipend);
+}
+
+static int
+rt305x_uart_bus_param(struct uart_softc *sc, int baudrate, int databits,
+ int stopbits, int parity)
+{
+ uart_lock(sc->sc_hwmtx);
+ rt305x_uart_init(&sc->sc_bas, baudrate, databits, stopbits, parity);
+ uart_unlock(sc->sc_hwmtx);
+ return (0);
+}
+
+static int
+rt305x_uart_bus_probe(struct uart_softc *sc)
+{
+ char buf[80];
+ int error;
+
+ error = rt305x_uart_probe(&sc->sc_bas);
+ if (error)
+ return (error);
+
+ sc->sc_rxfifosz = 16;
+ sc->sc_txfifosz = 16;
+
+ snprintf(buf, sizeof(buf), "rt305x_uart");
+ device_set_desc_copy(sc->sc_dev, buf);
+
+ return (0);
+}
+
+static int
+rt305x_uart_bus_receive(struct uart_softc *sc)
+{
+ struct uart_bas *bas;
+ int xc;
+ uint8_t lsr;
+
+ bas = &sc->sc_bas;
+ uart_lock(sc->sc_hwmtx);
+ lsr = uart_getreg(bas, UART_LSR_REG);
+ while ((lsr & UART_LSR_DR)) {
+ if (uart_rx_full(sc)) {
+ sc->sc_rxbuf[sc->sc_rxput] = UART_STAT_OVERRUN;
+ break;
+ }
+ xc = 0;
+ xc = uart_getreg(bas, UART_RX_REG);
+ if (lsr & UART_LSR_FE)
+ xc |= UART_STAT_FRAMERR;
+ if (lsr & UART_LSR_PE)
+ xc |= UART_STAT_PARERR;
+ if (lsr & UART_LSR_OE)
+ xc |= UART_STAT_OVERRUN;
+ uart_barrier(bas);
+ uart_rx_put(sc, xc);
+ lsr = uart_getreg(bas, UART_LSR_REG);
+ }
+
+ uart_unlock(sc->sc_hwmtx);
+ return (0);
+}
+
+static int
+rt305x_uart_bus_setsig(struct uart_softc *sc, int sig)
+{
+
+ /* TODO: implement (?) */
+ return (0);
+}
+
+static int
+rt305x_uart_bus_transmit(struct uart_softc *sc)
+{
+ struct uart_bas *bas = &sc->sc_bas;
+ int i;
+
+ if (!uart_output) return (0);
+
+ bas = &sc->sc_bas;
+ uart_lock(sc->sc_hwmtx);
+ while ((uart_getreg(bas, UART_LSR_REG) & UART_LSR_THRE) == 0)
+ ;
+ rt305x_uart_enable_txintr(sc);
+ for (i = 0; i < sc->sc_txdatasz; i++) {
+ uart_setreg(bas, UART_TX_REG, sc->sc_txbuf[i]);
+ uart_barrier(bas);
+ }
+ sc->sc_txbusy = 1;
+ uart_unlock(sc->sc_hwmtx);
+ return (0);
+}
+
+static void
+rt305x_uart_bus_grab(struct uart_softc *sc)
+{
+ struct uart_bas *bas = &sc->sc_bas;
+
+ /* disable interrupts -- XXX not sure which one is RX, so kill them all */
+ uart_lock(sc->sc_hwmtx);
+ uart_setreg(bas, UART_IER_REG, 0);
+ uart_barrier(bas);
+ uart_unlock(sc->sc_hwmtx);
+}
+
+static void
+rt305x_uart_bus_ungrab(struct uart_softc *sc)
+{
+ struct uart_bas *bas = &sc->sc_bas;
+
+ /* Enable interrupts */
+ uart_lock(sc->sc_hwmtx);
+ uart_setreg(bas, UART_IER_REG,
+ UART_IER_EDSSI | UART_IER_ELSI | UART_IER_ERBFI);
+ uart_barrier(bas);
+ uart_unlock(sc->sc_hwmtx);
+}
Property changes on: trunk/sys/mips/rt305x/uart_dev_rt305x.c
___________________________________________________________________
Added: svn:eol-style
## -0,0 +1 ##
+native
\ No newline at end of property
Added: svn:keywords
## -0,0 +1 ##
+MidnightBSD=%H
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+text/plain
\ No newline at end of property
Added: trunk/sys/mips/rt305x/uart_dev_rt305x.h
===================================================================
--- trunk/sys/mips/rt305x/uart_dev_rt305x.h (rev 0)
+++ trunk/sys/mips/rt305x/uart_dev_rt305x.h 2018-05-26 21:55:02 UTC (rev 9987)
@@ -0,0 +1,127 @@
+/* $MidnightBSD$ */
+/*-
+ * Copyright (c) 2010 Aleksandr Rybalko.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or
+ * without modification, are permitted provided that the following
+ * conditions are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above
+ * copyright notice, this list of conditions and the following
+ * disclaimer in the documentation and/or other materials provided
+ * with the distribution.
+ * 3. The names of the authors may not be used to endorse or promote
+ * products derived from this software without specific prior
+ * written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHORS ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
+ * PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHORS
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY,
+ * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
+ * TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
+ * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ *
+ * $FreeBSD: stable/10/sys/mips/rt305x/uart_dev_rt305x.h 220297 2011-04-03 14:39:55Z adrian $
+ */
+#ifndef _RT305XUART_H
+#define _RT305XUART_H
+
+#undef uart_getreg
+#undef uart_setreg
+#define uart_getreg(bas, reg) \
+ bus_space_read_4((bas)->bst, (bas)->bsh, reg)
+#define uart_setreg(bas, reg, value) \
+ bus_space_write_4((bas)->bst, (bas)->bsh, reg, value)
+
+/* UART registers */
+#define UART_RX_REG 0x00
+#define UART_TX_REG 0x04
+
+#define UART_IER_REG 0x08
+#define UART_IER_EDSSI (1<<3) /* Only full UART */
+#define UART_IER_ELSI (1<<2)
+#define UART_IER_ETBEI (1<<1)
+#define UART_IER_ERBFI (1<<0)
+
+#define UART_IIR_REG 0x0c
+#define UART_IIR_RXFIFO (1<<7)
+#define UART_IIR_TXFIFO (1<<6)
+#define UART_IIR_ID_MST 0
+#define UART_IIR_ID_THRE 1
+#define UART_IIR_ID_DR 2
+#define UART_IIR_ID_LINESTATUS 3
+#define UART_IIR_ID_DR2 6
+#define UART_IIR_ID_SHIFT 1
+#define UART_IIR_ID_MASK 0x0000000e
+#define UART_IIR_INTP (1<<0)
+
+#define UART_FCR_REG 0x10
+#define UART_FCR_RXTGR_1 (0<<6)
+#define UART_FCR_RXTGR_4 (1<<6)
+#define UART_FCR_RXTGR_8 (2<<6)
+#define UART_FCR_RXTGR_12 (3<<6)
+#define UART_FCR_TXTGR_1 (0<<4)
+#define UART_FCR_TXTGR_4 (1<<4)
+#define UART_FCR_TXTGR_8 (2<<4)
+#define UART_FCR_TXTGR_12 (3<<4)
+#define UART_FCR_DMA (1<<3)
+#define UART_FCR_TXRST (1<<2)
+#define UART_FCR_RXRST (1<<1)
+#define UART_FCR_FIFOEN (1<<0)
+
+#define UART_LCR_REG 0x14
+#define UART_LCR_DLAB (1<<7)
+#define UART_LCR_BRK (1<<6)
+#define UART_LCR_FPAR (1<<5)
+#define UART_LCR_EVEN (1<<4)
+#define UART_LCR_PEN (1<<3)
+#define UART_LCR_STB_15 (1<<2)
+#define UART_LCR_5B 0
+#define UART_LCR_6B 1
+#define UART_LCR_7B 2
+#define UART_LCR_8B 3
+
+#define UART_MCR_REG 0x18
+#define UART_MCR_LOOP (1<<4)
+#define UART_MCR_OUT2_L (1<<3) /* Only full UART */
+#define UART_MCR_OUT1_L (1<<2) /* Only full UART */
+#define UART_MCR_RTS_L (1<<1) /* Only full UART */
+#define UART_MCR_DTR_L (1<<0) /* Only full UART */
+
+#define UART_LSR_REG 0x1c
+#define UART_LSR_ERINF (1<<7)
+#define UART_LSR_TEMT (1<<6)
+#define UART_LSR_THRE (1<<5)
+#define UART_LSR_BI (1<<4)
+#define UART_LSR_FE (1<<3)
+#define UART_LSR_PE (1<<2)
+#define UART_LSR_OE (1<<1)
+#define UART_LSR_DR (1<<0)
+
+#define UART_MSR_REG 0x20 /* Only full UART */
+#define UART_MSR_DCD (1<<7) /* Only full UART */
+#define UART_MSR_RI (1<<6) /* Only full UART */
+#define UART_MSR_DSR (1<<5) /* Only full UART */
+#define UART_MSR_CTS (1<<4) /* Only full UART */
+#define UART_MSR_DDCD (1<<3) /* Only full UART */
+#define UART_MSR_TERI (1<<2) /* Only full UART */
+#define UART_MSR_DDSR (1<<1) /* Only full UART */
+#define UART_MSR_DCTS (1<<0) /* Only full UART */
+
+#define UART_CDDL_REG 0x28
+#define UART_CDDLL_REG 0x2c
+#define UART_CDDLH_REG 0x30
+
+#define UART_IFCTL_REG 0x34
+#define UART_IFCTL_IFCTL (1<<0)
+
+int uart_cnattach(void);
+#endif /* _RT305XUART_H */
Property changes on: trunk/sys/mips/rt305x/uart_dev_rt305x.h
___________________________________________________________________
Added: svn:eol-style
## -0,0 +1 ##
+native
\ No newline at end of property
Added: svn:keywords
## -0,0 +1 ##
+MidnightBSD=%H
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+text/plain
\ No newline at end of property
Added: trunk/sys/mips/sentry5/files.sentry5
===================================================================
--- trunk/sys/mips/sentry5/files.sentry5 (rev 0)
+++ trunk/sys/mips/sentry5/files.sentry5 2018-05-26 21:55:02 UTC (rev 9987)
@@ -0,0 +1,9 @@
+# $FreeBSD: stable/10/sys/mips/sentry5/files.sentry5 202175 2010-01-12 21:36:08Z imp $
+
+# TODO: Add attachment elsehwere in the tree
+# for USB 1.1 OHCI, Ethernet and IPSEC cores
+# which are believed to be devices we have drivers for
+# which just need to be tweaked for attachment to an SSB system bus.
+mips/sentry5/s5_machdep.c standard
+mips/mips/intr_machdep.c standard
+mips/mips/tick.c standard
Property changes on: trunk/sys/mips/sentry5/files.sentry5
___________________________________________________________________
Added: mnbsd:nokeywords
## -0,0 +1 ##
+MidnightBSD=%H
\ No newline at end of property
Added: trunk/sys/mips/sentry5/obio.c
===================================================================
--- trunk/sys/mips/sentry5/obio.c (rev 0)
+++ trunk/sys/mips/sentry5/obio.c 2018-05-26 21:55:02 UTC (rev 9987)
@@ -0,0 +1,184 @@
+/* $MidnightBSD$ */
+/* $NetBSD: obio.c,v 1.11 2003/07/15 00:25:05 lukem Exp $ */
+
+/*-
+ * Copyright (c) 2001, 2002, 2003 Wasabi Systems, Inc.
+ * All rights reserved.
+ *
+ * Written by Jason R. Thorpe for Wasabi Systems, Inc.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * 3. All advertising materials mentioning features or use of this software
+ * must display the following acknowledgement:
+ * This product includes software developed for the NetBSD Project by
+ * Wasabi Systems, Inc.
+ * 4. The name of Wasabi Systems, Inc. may not be used to endorse
+ * or promote products derived from this software without specific prior
+ * written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/*
+ * On-board device autoconfiguration support for Broadcom Sentry5
+ * based boards.
+ * XXX This is totally bogus and is just enough to get the console hopefully
+ * running on the sentry5.
+ */
+
+#include <sys/cdefs.h>
+__FBSDID("$FreeBSD: stable/10/sys/mips/sentry5/obio.c 202175 2010-01-12 21:36:08Z imp $");
+
+#include <sys/param.h>
+#include <sys/systm.h>
+#include <sys/bus.h>
+#include <sys/kernel.h>
+#include <sys/module.h>
+#include <sys/rman.h>
+#include <sys/malloc.h>
+
+#include <machine/bus.h>
+
+#include <mips/sentry5/obiovar.h>
+#include <mips/sentry5/sentry5reg.h>
+
+int obio_probe(device_t);
+int obio_attach(device_t);
+
+/*
+ * A bit tricky and hackish. Since we need OBIO to rely
+ * on PCI we make it pseudo-pci device. But there should
+ * be only one such device, so we use this static flag
+ * to prevent false positives on every realPCI device probe.
+ */
+static int have_one = 0;
+
+int
+obio_probe(device_t dev)
+{
+ if (!have_one) {
+ have_one = 1;
+ return 0;
+ }
+ return (ENXIO);
+}
+
+int
+obio_attach(device_t dev)
+{
+ struct obio_softc *sc = device_get_softc(dev);
+
+ sc->oba_st = MIPS_BUS_SPACE_IO;
+ sc->oba_addr = MIPS_PHYS_TO_KSEG1(SENTRY5_UART1ADR);
+ sc->oba_size = 0x03FFFFFF; /* XXX sb pci bus 0 aperture size? */
+ sc->oba_rman.rm_type = RMAN_ARRAY;
+ sc->oba_rman.rm_descr = "OBIO I/O";
+ if (rman_init(&sc->oba_rman) != 0 ||
+ rman_manage_region(&sc->oba_rman,
+ sc->oba_addr, sc->oba_addr + sc->oba_size) != 0)
+ panic("obio_attach: failed to set up I/O rman");
+ sc->oba_irq_rman.rm_type = RMAN_ARRAY;
+ sc->oba_irq_rman.rm_descr = "OBIO IRQ";
+
+ /*
+ * This module is intended for UART purposes only and
+ * it's IRQ is 4
+ */
+ if (rman_init(&sc->oba_irq_rman) != 0 ||
+ rman_manage_region(&sc->oba_irq_rman, 4, 4) != 0)
+ panic("obio_attach: failed to set up IRQ rman");
+
+ device_add_child(dev, "uart", 0);
+ bus_generic_probe(dev);
+ bus_generic_attach(dev);
+
+ return (0);
+}
+
+static struct resource *
+obio_alloc_resource(device_t bus, device_t child, int type, int *rid,
+ u_long start, u_long end, u_long count, u_int flags)
+{
+ struct resource *rv;
+ struct rman *rm;
+ bus_space_handle_t bh = 0;
+ struct obio_softc *sc = device_get_softc(bus);
+
+ switch (type) {
+ case SYS_RES_IRQ:
+ rm = &sc->oba_irq_rman;
+ break;
+ case SYS_RES_MEMORY:
+ return (NULL);
+ case SYS_RES_IOPORT:
+ rm = &sc->oba_rman;
+ bh = sc->oba_addr;
+ start = bh;
+ break;
+ default:
+ return (NULL);
+ }
+
+
+ rv = rman_reserve_resource(rm, start, end, count, flags, child);
+ if (rv == NULL)
+ return (NULL);
+ if (type == SYS_RES_IRQ)
+ return (rv);
+ rman_set_rid(rv, *rid);
+ rman_set_bustag(rv, mips_bus_space_generic);
+ rman_set_bushandle(rv, bh);
+
+ if (0) {
+ if (bus_activate_resource(child, type, *rid, rv)) {
+ rman_release_resource(rv);
+ return (NULL);
+ }
+ }
+ return (rv);
+
+}
+
+static int
+obio_activate_resource(device_t bus, device_t child, int type, int rid,
+ struct resource *r)
+{
+ return (0);
+}
+static device_method_t obio_methods[] = {
+ DEVMETHOD(device_probe, obio_probe),
+ DEVMETHOD(device_attach, obio_attach),
+
+ DEVMETHOD(bus_alloc_resource, obio_alloc_resource),
+ DEVMETHOD(bus_activate_resource, obio_activate_resource),
+ DEVMETHOD(bus_setup_intr, bus_generic_setup_intr),
+ DEVMETHOD(bus_teardown_intr, bus_generic_teardown_intr),
+
+ {0, 0},
+};
+
+static driver_t obio_driver = {
+ "obio",
+ obio_methods,
+ sizeof(struct obio_softc),
+};
+static devclass_t obio_devclass;
+
+DRIVER_MODULE(obio, pci, obio_driver, obio_devclass, 0, 0);
Property changes on: trunk/sys/mips/sentry5/obio.c
___________________________________________________________________
Added: svn:eol-style
## -0,0 +1 ##
+native
\ No newline at end of property
Added: svn:keywords
## -0,0 +1 ##
+MidnightBSD=%H
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+text/plain
\ No newline at end of property
Added: trunk/sys/mips/sentry5/obiovar.h
===================================================================
--- trunk/sys/mips/sentry5/obiovar.h (rev 0)
+++ trunk/sys/mips/sentry5/obiovar.h 2018-05-26 21:55:02 UTC (rev 9987)
@@ -0,0 +1,59 @@
+/* $MidnightBSD$ */
+/* $NetBSD: obiovar.h,v 1.4 2003/06/16 17:40:53 thorpej Exp $ */
+
+/*-
+ * Copyright (c) 2002, 2003 Wasabi Systems, Inc.
+ * All rights reserved.
+ *
+ * Written by Jason R. Thorpe for Wasabi Systems, Inc.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * 3. All advertising materials mentioning features or use of this software
+ * must display the following acknowledgement:
+ * This product includes software developed for the NetBSD Project by
+ * Wasabi Systems, Inc.
+ * 4. The name of Wasabi Systems, Inc. may not be used to endorse
+ * or promote products derived from this software without specific prior
+ * written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * $FreeBSD: stable/10/sys/mips/sentry5/obiovar.h 202175 2010-01-12 21:36:08Z imp $
+ *
+ */
+
+#ifndef _SENTRY5_OBIOVAR_H_
+#define _SENTRY5_OBIOVAR_H_
+
+#include <sys/rman.h>
+
+struct obio_softc {
+ bus_space_tag_t oba_st; /* bus space tag */
+ bus_addr_t oba_addr; /* address of device */
+ bus_size_t oba_size; /* size of device */
+ int oba_width; /* bus width */
+ int oba_irq; /* XINT interrupt bit # */
+ struct rman oba_rman;
+ struct rman oba_irq_rman;
+
+};
+extern struct bus_space obio_bs_tag;
+
+#endif /* _SENTRY5_OBIOVAR_H_ */
Property changes on: trunk/sys/mips/sentry5/obiovar.h
___________________________________________________________________
Added: svn:eol-style
## -0,0 +1 ##
+native
\ No newline at end of property
Added: svn:keywords
## -0,0 +1 ##
+MidnightBSD=%H
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+text/plain
\ No newline at end of property
Added: trunk/sys/mips/sentry5/s5_machdep.c
===================================================================
--- trunk/sys/mips/sentry5/s5_machdep.c (rev 0)
+++ trunk/sys/mips/sentry5/s5_machdep.c 2018-05-26 21:55:02 UTC (rev 9987)
@@ -0,0 +1,224 @@
+/* $MidnightBSD$ */
+/*-
+ * Copyright (c) 2007 Bruce M. Simpson.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ */
+
+#include <sys/cdefs.h>
+__FBSDID("$FreeBSD: stable/10/sys/mips/sentry5/s5_machdep.c 247297 2013-02-26 01:00:11Z attilio $");
+
+#include "opt_ddb.h"
+
+#include <sys/param.h>
+#include <sys/conf.h>
+#include <sys/kernel.h>
+#include <sys/systm.h>
+#include <sys/imgact.h>
+#include <sys/bio.h>
+#include <sys/buf.h>
+#include <sys/bus.h>
+#include <sys/cpu.h>
+#include <sys/cons.h>
+#include <sys/exec.h>
+#include <sys/ucontext.h>
+#include <sys/proc.h>
+#include <sys/kdb.h>
+#include <sys/ptrace.h>
+#include <sys/reboot.h>
+#include <sys/signalvar.h>
+#include <sys/sysent.h>
+#include <sys/sysproto.h>
+#include <sys/user.h>
+
+#include <vm/vm.h>
+#include <vm/vm_object.h>
+#include <vm/vm_page.h>
+
+#include <machine/cache.h>
+#include <machine/clock.h>
+#include <machine/cpu.h>
+#include <machine/cpuinfo.h>
+#include <machine/cpufunc.h>
+#include <machine/cpuregs.h>
+#include <machine/hwfunc.h>
+#include <machine/intr_machdep.h>
+#include <machine/locore.h>
+#include <machine/md_var.h>
+#include <machine/pte.h>
+#include <machine/sigframe.h>
+#include <machine/trap.h>
+#include <machine/vmparam.h>
+
+#include <mips/sentry5/s5reg.h>
+
+#ifdef CFE
+#include <dev/cfe/cfe_api.h>
+#endif
+
+extern int *edata;
+extern int *end;
+
+void
+platform_cpu_init()
+{
+ /* Nothing special */
+}
+
+static void
+mips_init(void)
+{
+ int i, j;
+
+ printf("entry: mips_init()\n");
+
+#ifdef CFE
+ /*
+ * Query DRAM memory map from CFE.
+ */
+ physmem = 0;
+ for (i = 0; i < 10; i += 2) {
+ int result;
+ uint64_t addr, len, type;
+
+ result = cfe_enummem(i, 0, &addr, &len, &type);
+ if (result < 0) {
+ phys_avail[i] = phys_avail[i + 1] = 0;
+ break;
+ }
+ if (type != CFE_MI_AVAILABLE)
+ continue;
+
+ phys_avail[i] = addr;
+ if (i == 0 && addr == 0) {
+ /*
+ * If this is the first physical memory segment probed
+ * from CFE, omit the region at the start of physical
+ * memory where the kernel has been loaded.
+ */
+ phys_avail[i] += MIPS_KSEG0_TO_PHYS(kernel_kseg0_end);
+ }
+ phys_avail[i + 1] = addr + len;
+ physmem += len;
+ }
+
+ realmem = btoc(physmem);
+#endif
+
+ for (j = 0; j < i; j++)
+ dump_avail[j] = phys_avail[j];
+
+ physmem = realmem;
+
+ init_param1();
+ init_param2(physmem);
+ mips_cpu_init();
+ pmap_bootstrap();
+ mips_proc0_init();
+ mutex_init();
+ kdb_init();
+#ifdef KDB
+ if (boothowto & RB_KDB)
+ kdb_enter(KDB_WHY_BOOTFLAGS, "Boot flags requested debugger");
+#endif
+}
+
+void
+platform_reset(void)
+{
+
+#if defined(CFE)
+ cfe_exit(0, 0);
+#else
+ *((volatile uint8_t *)MIPS_PHYS_TO_KSEG1(SENTRY5_EXTIFADR)) = 0x80;
+#endif
+}
+
+void
+platform_start(__register_t a0, __register_t a1, __register_t a2,
+ __register_t a3)
+{
+ vm_offset_t kernend;
+ uint64_t platform_counter_freq;
+
+ /* clear the BSS and SBSS segments */
+ kernend = (vm_offset_t)&end;
+ memset(&edata, 0, kernend - (vm_offset_t)(&edata));
+
+ mips_postboot_fixup();
+
+ /* Initialize pcpu stuff */
+ mips_pcpu0_init();
+
+#ifdef CFE
+ /*
+ * Initialize CFE firmware trampolines before
+ * we initialize the low-level console.
+ *
+ * CFE passes the following values in registers:
+ * a0: firmware handle
+ * a2: firmware entry point
+ * a3: entry point seal
+ */
+ if (a3 == CFE_EPTSEAL)
+ cfe_init(a0, a2);
+#endif
+ cninit();
+
+ mips_init();
+
+# if 0
+ /*
+ * Probe the Broadcom Sentry5's on-chip PLL clock registers
+ * and discover the CPU pipeline clock and bus clock
+ * multipliers from this.
+ * XXX: Wrong place. You have to ask the ChipCommon
+ * or External Interface cores on the SiBa.
+ */
+ uint32_t busmult, cpumult, refclock, clkcfg1;
+#define S5_CLKCFG1_REFCLOCK_MASK 0x0000001F
+#define S5_CLKCFG1_BUSMULT_MASK 0x000003E0
+#define S5_CLKCFG1_BUSMULT_SHIFT 5
+#define S5_CLKCFG1_CPUMULT_MASK 0xFFFFFC00
+#define S5_CLKCFG1_CPUMULT_SHIFT 10
+
+ counter_freq = 100000000; /* XXX */
+
+ clkcfg1 = s5_rd_clkcfg1();
+ printf("clkcfg1 = 0x%08x\n", clkcfg1);
+
+ refclock = clkcfg1 & 0x1F;
+ busmult = ((clkcfg1 & 0x000003E0) >> 5) + 1;
+ cpumult = ((clkcfg1 & 0xFFFFFC00) >> 10) + 1;
+
+ printf("refclock = %u\n", refclock);
+ printf("busmult = %u\n", busmult);
+ printf("cpumult = %u\n", cpumult);
+
+ counter_freq = cpumult * refclock;
+# else
+ platform_counter_freq = 200 * 1000 * 1000; /* Sentry5 is 200MHz */
+# endif
+
+ mips_timer_init_params(platform_counter_freq, 0);
+}
Property changes on: trunk/sys/mips/sentry5/s5_machdep.c
___________________________________________________________________
Added: svn:eol-style
## -0,0 +1 ##
+native
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## -0,0 +1 ##
+MidnightBSD=%H
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## -0,0 +1 ##
+text/plain
\ No newline at end of property
Added: trunk/sys/mips/sentry5/s5reg.h
===================================================================
--- trunk/sys/mips/sentry5/s5reg.h (rev 0)
+++ trunk/sys/mips/sentry5/s5reg.h 2018-05-26 21:55:02 UTC (rev 9987)
@@ -0,0 +1,59 @@
+/* $MidnightBSD$ */
+/* $FreeBSD: stable/10/sys/mips/sentry5/s5reg.h 202175 2010-01-12 21:36:08Z imp $ */
+
+#ifndef _MIPS32_SENTRY5_SENTRY5REG_H_
+#define _MIPS32_SENTRY5_SENTRY5REG_H_
+
+#define SENTRY5_UART0ADR 0x18000300
+#define SENTRY5_UART1ADR 0x18000400
+
+/* Reset register implemented here in a PLD device. */
+#define SENTRY5_EXTIFADR 0x1F000000
+#define SENTRY5_DORESET 0x80
+
+/*
+ * Custom CP0 register macros.
+ * XXX: This really needs the mips cpuregs.h file for the barrier.
+ */
+#define S5_RDRW32_C0P0_CUST22(n,r) \
+static __inline u_int32_t \
+s5_rd_ ## n (void) \
+{ \
+ int v0; \
+ __asm __volatile ("mfc0 %[v0], $22, "__XSTRING(r)" ;" \
+ : [v0] "=&r"(v0)); \
+ /*mips_barrier();*/ \
+ return (v0); \
+} \
+static __inline void \
+s5_wr_ ## n (u_int32_t a0) \
+{ \
+ __asm __volatile ("mtc0 %[a0], $22, "__XSTRING(r)" ;" \
+ __XSTRING(COP0_SYNC)";" \
+ "nop;" \
+ "nop;" \
+ : \
+ : [a0] "r"(a0)); \
+ /*mips_barrier();*/ \
+} struct __hack
+
+/*
+ * All 5 of these sub-registers are used by Linux.
+ * There is a further custom register at 25 which is not used.
+ */
+#define S5_CP0_DIAG 0
+#define S5_CP0_CLKCFG1 1
+#define S5_CP0_CLKCFG2 2
+#define S5_CP0_SYNC 3
+#define S5_CP0_CLKCFG3 4
+#define S5_CP0_RESET 5
+
+/* s5_[rd|wr]_xxx() */
+S5_RDRW32_C0P0_CUST22(diag, S5_CP0_DIAG);
+S5_RDRW32_C0P0_CUST22(clkcfg1, S5_CP0_CLKCFG1);
+S5_RDRW32_C0P0_CUST22(clkcfg2, S5_CP0_CLKCFG2);
+S5_RDRW32_C0P0_CUST22(sync, S5_CP0_SYNC);
+S5_RDRW32_C0P0_CUST22(clkcfg3, S5_CP0_CLKCFG3);
+S5_RDRW32_C0P0_CUST22(reset, S5_CP0_RESET);
+
+#endif /* _MIPS32_SENTRY5_SENTRY5REG_H_ */
Property changes on: trunk/sys/mips/sentry5/s5reg.h
___________________________________________________________________
Added: svn:eol-style
## -0,0 +1 ##
+native
\ No newline at end of property
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## -0,0 +1 ##
+MidnightBSD=%H
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+text/plain
\ No newline at end of property
Added: trunk/sys/mips/sentry5/std.sentry5
===================================================================
--- trunk/sys/mips/sentry5/std.sentry5 (rev 0)
+++ trunk/sys/mips/sentry5/std.sentry5 2018-05-26 21:55:02 UTC (rev 9987)
@@ -0,0 +1,10 @@
+# $FreeBSD: stable/10/sys/mips/sentry5/std.sentry5 232896 2012-03-12 21:25:32Z jmallett $
+#
+
+machine mips mipsel
+
+cpu CPU_MIPS4KC
+options CPU_SENTRY5 # XXX should this be a
+ # sub-cpu option?
+files "../sentry5/files.sentry5"
+
Property changes on: trunk/sys/mips/sentry5/std.sentry5
___________________________________________________________________
Added: mnbsd:nokeywords
## -0,0 +1 ##
+MidnightBSD=%H
\ No newline at end of property
Added: trunk/sys/mips/sentry5/uart_bus_sbusart.c
===================================================================
--- trunk/sys/mips/sentry5/uart_bus_sbusart.c (rev 0)
+++ trunk/sys/mips/sentry5/uart_bus_sbusart.c 2018-05-26 21:55:02 UTC (rev 9987)
@@ -0,0 +1,96 @@
+/* $MidnightBSD$ */
+/*-
+ * Copyright (c) 2007 Bruce M. Simpson.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * $Id$
+ */
+/*
+ * Skeleton of this file was based on respective code for ARM
+ * code written by Olivier Houchard.
+ */
+
+/*
+ * XXXMIPS: This file is hacked from arm/... . XXXMIPS here means this file is
+ * experimental and was written for MIPS32 port.
+ */
+#include "opt_uart.h"
+
+#include <sys/cdefs.h>
+__FBSDID("$FreeBSD: stable/10/sys/mips/sentry5/uart_bus_sbusart.c 202175 2010-01-12 21:36:08Z imp $");
+
+#include <sys/param.h>
+#include <sys/systm.h>
+#include <sys/bus.h>
+#include <sys/conf.h>
+#include <sys/kernel.h>
+#include <sys/module.h>
+#include <machine/bus.h>
+#include <sys/rman.h>
+#include <machine/resource.h>
+
+#include <dev/pci/pcivar.h>
+
+#include <dev/uart/uart.h>
+#include <dev/uart/uart_bus.h>
+#include <dev/uart/uart_cpu.h>
+
+#include <mips/sentry5/sentry5reg.h>
+
+#include "uart_if.h"
+
+static int uart_malta_probe(device_t dev);
+
+extern struct uart_class malta_uart_class;
+
+static device_method_t uart_malta_methods[] = {
+ /* Device interface */
+ DEVMETHOD(device_probe, uart_malta_probe),
+ DEVMETHOD(device_attach, uart_bus_attach),
+ DEVMETHOD(device_detach, uart_bus_detach),
+ { 0, 0 }
+};
+
+static driver_t uart_malta_driver = {
+ uart_driver_name,
+ uart_malta_methods,
+ sizeof(struct uart_softc),
+};
+
+extern SLIST_HEAD(uart_devinfo_list, uart_devinfo) uart_sysdevs;
+static int
+uart_malta_probe(device_t dev)
+{
+ struct uart_softc *sc;
+
+ sc = device_get_softc(dev);
+ sc->sc_sysdev = SLIST_FIRST(&uart_sysdevs);
+ sc->sc_class = &uart_ns8250_class;
+ bcopy(&sc->sc_sysdev->bas, &sc->sc_bas, sizeof(sc->sc_bas));
+ sc->sc_sysdev->bas.bst = mips_bus_space_generic;
+ sc->sc_sysdev->bas.bsh = MIPS_PHYS_TO_KSEG1(SENTRY5_UART1ADR);
+ sc->sc_bas.bst = mips_bus_space_generic;
+ sc->sc_bas.bsh = MIPS_PHYS_TO_KSEG1(SENTRY5_UART1ADR);
+ return(uart_bus_probe(dev, 0, 0, 0, 0));
+}
+
+DRIVER_MODULE(uart, obio, uart_malta_driver, uart_devclass, 0, 0);
Property changes on: trunk/sys/mips/sentry5/uart_bus_sbusart.c
___________________________________________________________________
Added: svn:eol-style
## -0,0 +1 ##
+native
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## -0,0 +1 ##
+MidnightBSD=%H
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## -0,0 +1 ##
+text/plain
\ No newline at end of property
Added: trunk/sys/mips/sentry5/uart_cpu_sbusart.c
===================================================================
--- trunk/sys/mips/sentry5/uart_cpu_sbusart.c (rev 0)
+++ trunk/sys/mips/sentry5/uart_cpu_sbusart.c 2018-05-26 21:55:02 UTC (rev 9987)
@@ -0,0 +1,83 @@
+/* $MidnightBSD$ */
+/*-
+ * Copyright (c) 2006 Wojciech A. Koszek <wkoszek at FreeBSD.org>
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ * $Id$
+ */
+/*
+ * Skeleton of this file was based on respective code for ARM
+ * code written by Olivier Houchard.
+ */
+/*
+ * XXXMIPS: This file is hacked from arm/... . XXXMIPS here means this file is
+ * experimental and was written for MIPS32 port.
+ */
+#include "opt_uart.h"
+
+#include <sys/cdefs.h>
+__FBSDID("$FreeBSD: stable/10/sys/mips/sentry5/uart_cpu_sbusart.c 202175 2010-01-12 21:36:08Z imp $");
+
+#include <sys/param.h>
+#include <sys/systm.h>
+#include <sys/bus.h>
+#include <sys/cons.h>
+
+#include <machine/bus.h>
+
+#include <dev/uart/uart.h>
+#include <dev/uart/uart_cpu.h>
+
+#include <mips/sentry5/sentry5reg.h>
+
+bus_space_tag_t uart_bus_space_io;
+bus_space_tag_t uart_bus_space_mem;
+
+extern struct uart_ops malta_usart_ops;
+extern struct bus_space malta_bs_tag;
+
+int
+uart_cpu_eqres(struct uart_bas *b1, struct uart_bas *b2)
+{
+ return ((b1->bsh == b2->bsh && b1->bst == b2->bst) ? 1 : 0);
+}
+
+int
+uart_cpu_getdev(int devtype, struct uart_devinfo *di)
+{
+ di->ops = uart_getops(&uart_ns8250_class);
+ di->bas.chan = 0;
+ di->bas.bst = 0;
+ di->bas.regshft = 0;
+ di->bas.rclk = 0;
+ di->baudrate = 115200;
+ di->databits = 8;
+ di->stopbits = 1;
+ di->parity = UART_PARITY_NONE;
+
+ uart_bus_space_io = MIPS_PHYS_TO_KSEG1(SENTRY5_UART1ADR);
+ uart_bus_space_mem = mips_bus_space_generic;
+ di->bas.bsh = MIPS_PHYS_TO_KSEG1(SENTRY5_UART1ADR);
+ return (0);
+}
Property changes on: trunk/sys/mips/sentry5/uart_cpu_sbusart.c
___________________________________________________________________
Added: svn:eol-style
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+native
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## -0,0 +1 ##
+MidnightBSD=%H
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## -0,0 +1 ##
+text/plain
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Added: trunk/sys/mips/sibyte/ata_zbbus.c
===================================================================
--- trunk/sys/mips/sibyte/ata_zbbus.c (rev 0)
+++ trunk/sys/mips/sibyte/ata_zbbus.c 2018-05-26 21:55:02 UTC (rev 9987)
@@ -0,0 +1,171 @@
+/* $MidnightBSD$ */
+/*-
+ * Copyright (c) 2009 Neelkanth Natu
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ */
+
+#include <sys/param.h>
+#include <sys/kernel.h>
+#include <sys/systm.h>
+#include <sys/module.h>
+#include <sys/bus.h>
+#include <sys/rman.h>
+#include <sys/lock.h>
+#include <sys/mutex.h>
+#include <sys/sema.h>
+#include <sys/taskqueue.h>
+
+#include <machine/bus.h>
+
+#include <vm/uma.h>
+
+#include <sys/ata.h>
+#include <dev/ata/ata-all.h>
+
+#include <machine/resource.h>
+
+__FBSDID("$FreeBSD: stable/10/sys/mips/sibyte/ata_zbbus.c 195333 2009-07-04 03:05:48Z imp $");
+
+static int
+ata_zbbus_probe(device_t dev)
+{
+
+ return (ata_probe(dev));
+}
+
+static int
+ata_zbbus_attach(device_t dev)
+{
+ int i, rid, regshift, regoffset;
+ struct ata_channel *ch;
+ struct resource *io;
+
+ ch = device_get_softc(dev);
+
+ if (ch->attached)
+ return (0);
+ ch->attached = 1;
+
+ rid = 0;
+ io = bus_alloc_resource(dev, SYS_RES_MEMORY, &rid, 0, ~0, 1, RF_ACTIVE);
+ if (io == NULL)
+ return (ENXIO);
+
+ /*
+ * SWARM needs an address shift of 5 when accessing ATA registers.
+ *
+ * For e.g. an access to register 4 actually needs an address
+ * of (4 << 5) to be output on the generic bus.
+ */
+ regshift = 5;
+ resource_int_value(device_get_name(dev), device_get_unit(dev),
+ "regshift", ®shift);
+ if (regshift && bootverbose)
+ device_printf(dev, "using a register shift of %d\n", regshift);
+
+ regoffset = 0x1F0;
+ resource_int_value(device_get_name(dev), device_get_unit(dev),
+ "regoffset", ®offset);
+ if (regoffset && bootverbose) {
+ device_printf(dev, "using a register offset of 0x%0x\n",
+ regoffset);
+ }
+
+ /* setup the ata register addresses */
+ for (i = ATA_DATA; i <= ATA_COMMAND; ++i) {
+ ch->r_io[i].res = io;
+ ch->r_io[i].offset = (regoffset + i) << regshift;
+ }
+
+ ch->r_io[ATA_CONTROL].res = io;
+ ch->r_io[ATA_CONTROL].offset = (regoffset + ATA_CTLOFFSET) << regshift;
+ ch->r_io[ATA_IDX_ADDR].res = io; /* XXX what is this used for */
+ ata_default_registers(dev);
+
+ /* initialize softc for this channel */
+ ch->unit = 0;
+ ch->flags |= ATA_USE_16BIT;
+ ata_generic_hw(dev);
+
+ return (ata_attach(dev));
+}
+
+static int
+ata_zbbus_detach(device_t dev)
+{
+ int error;
+ struct ata_channel *ch = device_get_softc(dev);
+
+ if (!ch->attached)
+ return (0);
+ ch->attached = 0;
+
+ error = ata_detach(dev);
+
+ bus_release_resource(dev, SYS_RES_MEMORY, 0,
+ ch->r_io[ATA_IDX_ADDR].res);
+
+ return (error);
+}
+
+static int
+ata_zbbus_suspend(device_t dev)
+{
+ struct ata_channel *ch = device_get_softc(dev);
+
+ if (!ch->attached)
+ return (0);
+
+ return (ata_suspend(dev));
+}
+
+static int
+ata_zbbus_resume(device_t dev)
+{
+ struct ata_channel *ch = device_get_softc(dev);
+
+ if (!ch->attached)
+ return (0);
+
+ return (ata_resume(dev));
+}
+
+static device_method_t ata_zbbus_methods[] = {
+ /* device interface */
+ DEVMETHOD(device_probe, ata_zbbus_probe),
+ DEVMETHOD(device_attach, ata_zbbus_attach),
+ DEVMETHOD(device_detach, ata_zbbus_detach),
+ DEVMETHOD(device_suspend, ata_zbbus_suspend),
+ DEVMETHOD(device_resume, ata_zbbus_resume),
+
+ { 0, 0 }
+};
+
+static driver_t ata_zbbus_driver = {
+ "ata",
+ ata_zbbus_methods,
+ sizeof(struct ata_channel)
+};
+
+DRIVER_MODULE(ata, zbbus, ata_zbbus_driver, ata_devclass, 0, 0);
Property changes on: trunk/sys/mips/sibyte/ata_zbbus.c
___________________________________________________________________
Added: svn:eol-style
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+native
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+MidnightBSD=%H
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+text/plain
\ No newline at end of property
Added: trunk/sys/mips/sibyte/files.sibyte
===================================================================
--- trunk/sys/mips/sibyte/files.sibyte (rev 0)
+++ trunk/sys/mips/sibyte/files.sibyte 2018-05-26 21:55:02 UTC (rev 9987)
@@ -0,0 +1,10 @@
+# $FreeBSD: stable/10/sys/mips/sibyte/files.sibyte 202175 2010-01-12 21:36:08Z imp $
+
+mips/sibyte/sb_machdep.c standard
+mips/sibyte/sb_zbbus.c standard
+mips/sibyte/sb_zbpci.c standard
+mips/sibyte/sb_scd.c standard
+mips/sibyte/ata_zbbus.c standard
+mips/mips/intr_machdep.c standard
+mips/sibyte/sb_asm.S standard
+mips/mips/tick.c standard
Property changes on: trunk/sys/mips/sibyte/files.sibyte
___________________________________________________________________
Added: mnbsd:nokeywords
## -0,0 +1 ##
+MidnightBSD=%H
\ No newline at end of property
Added: trunk/sys/mips/sibyte/sb_asm.S
===================================================================
--- trunk/sys/mips/sibyte/sb_asm.S (rev 0)
+++ trunk/sys/mips/sibyte/sb_asm.S 2018-05-26 21:55:02 UTC (rev 9987)
@@ -0,0 +1,52 @@
+/* $MidnightBSD$ */
+/*-
+ * Copyright (c) 2009 Neelkanth Natu
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ * $FreeBSD: stable/10/sys/mips/sibyte/sb_asm.S 205675 2010-03-26 07:15:27Z neel $
+ */
+
+#include <machine/asm.h>
+#include <machine/cpuregs.h>
+
+.set mips64
+.set noat
+.set noreorder
+
+#ifdef SMP
+/*
+ * This function must be implemented in assembly because it is called early
+ * in AP boot without a valid stack.
+ *
+ * This cpu number is available in bits 25 to 27 of the coprocessor 0 PRID
+ * register. This is not documented in the BCM1250 user manual but can be
+ * gleaned from the CFE source code - see sb1250_altcpu.S
+ */
+LEAF(platform_processor_id)
+ mfc0 v0, MIPS_COP_0_PRID
+ srl v0, v0, 25
+ jr ra
+ and v0, v0, 7
+END(platform_processor_id)
+#endif /* SMP */
Property changes on: trunk/sys/mips/sibyte/sb_asm.S
___________________________________________________________________
Added: svn:eol-style
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+native
\ No newline at end of property
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## -0,0 +1 ##
+MidnightBSD=%H
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+text/plain
\ No newline at end of property
Added: trunk/sys/mips/sibyte/sb_bus_space.h
===================================================================
--- trunk/sys/mips/sibyte/sb_bus_space.h (rev 0)
+++ trunk/sys/mips/sibyte/sb_bus_space.h 2018-05-26 21:55:02 UTC (rev 9987)
@@ -0,0 +1,44 @@
+/* $MidnightBSD$ */
+/*-
+ * Copyright (c) 2010 Neelkanth Natu
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ * $FreeBSD: stable/10/sys/mips/sibyte/sb_bus_space.h 203985 2010-02-17 06:43:37Z neel $
+ */
+
+#ifndef _SB_BUS_SPACE_H_
+#define _SB_BUS_SPACE_H_
+
+#include <machine/endian.h>
+
+#if _BYTE_ORDER == _BIG_ENDIAN
+uint8_t sb_big_endian_read8(bus_addr_t addr);
+uint16_t sb_big_endian_read16(bus_addr_t addr);
+uint32_t sb_big_endian_read32(bus_addr_t addr);
+void sb_big_endian_write8(bus_addr_t addr, uint8_t val);
+void sb_big_endian_write16(bus_addr_t addr, uint16_t val);
+void sb_big_endian_write32(bus_addr_t addr, uint32_t val);
+#endif
+
+#endif
Property changes on: trunk/sys/mips/sibyte/sb_bus_space.h
___________________________________________________________________
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+native
\ No newline at end of property
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## -0,0 +1 ##
+MidnightBSD=%H
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## -0,0 +1 ##
+text/plain
\ No newline at end of property
Added: trunk/sys/mips/sibyte/sb_machdep.c
===================================================================
--- trunk/sys/mips/sibyte/sb_machdep.c (rev 0)
+++ trunk/sys/mips/sibyte/sb_machdep.c 2018-05-26 21:55:02 UTC (rev 9987)
@@ -0,0 +1,433 @@
+/* $MidnightBSD$ */
+/*-
+ * Copyright (c) 2007 Bruce M. Simpson.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ */
+
+#include <sys/cdefs.h>
+__FBSDID("$FreeBSD: stable/10/sys/mips/sibyte/sb_machdep.c 247297 2013-02-26 01:00:11Z attilio $");
+
+#include "opt_ddb.h"
+#include "opt_kdb.h"
+
+#include <sys/param.h>
+#include <sys/conf.h>
+#include <sys/kernel.h>
+#include <sys/systm.h>
+#include <sys/imgact.h>
+#include <sys/bio.h>
+#include <sys/buf.h>
+#include <sys/bus.h>
+#include <sys/cpu.h>
+#include <sys/cons.h>
+#include <sys/exec.h>
+#include <sys/ucontext.h>
+#include <sys/proc.h>
+#include <sys/kdb.h>
+#include <sys/ptrace.h>
+#include <sys/reboot.h>
+#include <sys/signalvar.h>
+#include <sys/sysent.h>
+#include <sys/sysproto.h>
+#include <sys/user.h>
+#include <sys/timetc.h>
+
+#include <vm/vm.h>
+#include <vm/vm_object.h>
+#include <vm/vm_page.h>
+
+#include <machine/cache.h>
+#include <machine/clock.h>
+#include <machine/cpu.h>
+#include <machine/cpuinfo.h>
+#include <machine/cpufunc.h>
+#include <machine/cpuregs.h>
+#include <machine/hwfunc.h>
+#include <machine/intr_machdep.h>
+#include <machine/locore.h>
+#include <machine/md_var.h>
+#include <machine/pte.h>
+#include <machine/sigframe.h>
+#include <machine/trap.h>
+#include <machine/vmparam.h>
+
+#ifdef SMP
+#include <sys/smp.h>
+#include <machine/smp.h>
+#endif
+
+#ifdef CFE
+#include <dev/cfe/cfe_api.h>
+#endif
+
+#include "sb_scd.h"
+
+#ifdef DDB
+#ifndef KDB
+#error KDB must be enabled in order for DDB to work!
+#endif
+#endif
+
+#ifdef CFE_ENV
+extern void cfe_env_init(void);
+#endif
+
+extern int *edata;
+extern int *end;
+
+extern char MipsTLBMiss[], MipsTLBMissEnd[];
+
+void
+platform_cpu_init()
+{
+ /* Nothing special */
+}
+
+static void
+sb_intr_init(int cpuid)
+{
+ int intrnum, intsrc;
+
+ /*
+ * Disable all sources to the interrupt mapper and setup the mapping
+ * between an interrupt source and the mips hard interrupt number.
+ */
+ for (intsrc = 0; intsrc < NUM_INTSRC; ++intsrc) {
+ intrnum = sb_route_intsrc(intsrc);
+ sb_disable_intsrc(cpuid, intsrc);
+ sb_write_intmap(cpuid, intsrc, intrnum);
+#ifdef SMP
+ /*
+ * Set up the mailbox interrupt mapping.
+ *
+ * The mailbox interrupt is "special" in that it is not shared
+ * with any other interrupt source.
+ */
+ if (intsrc == INTSRC_MAILBOX3) {
+ intrnum = platform_ipi_intrnum();
+ sb_write_intmap(cpuid, INTSRC_MAILBOX3, intrnum);
+ sb_enable_intsrc(cpuid, INTSRC_MAILBOX3);
+ }
+#endif
+ }
+}
+
+static void
+mips_init(void)
+{
+ int i, j, cfe_mem_idx, tmp;
+ uint64_t maxmem;
+
+#ifdef CFE_ENV
+ cfe_env_init();
+#endif
+
+ TUNABLE_INT_FETCH("boothowto", &boothowto);
+
+ if (boothowto & RB_VERBOSE)
+ bootverbose++;
+
+#ifdef MAXMEM
+ tmp = MAXMEM;
+#else
+ tmp = 0;
+#endif
+ TUNABLE_INT_FETCH("hw.physmem", &tmp);
+ maxmem = (uint64_t)tmp * 1024;
+
+ /*
+ * XXX
+ * If we used vm_paddr_t consistently in pmap, etc., we could
+ * use 64-bit page numbers on !n64 systems, too, like i386
+ * does with PAE.
+ */
+#if !defined(__mips_n64)
+ if (maxmem == 0 || maxmem > 0xffffffff)
+ maxmem = 0xffffffff;
+#endif
+
+#ifdef CFE
+ /*
+ * Query DRAM memory map from CFE.
+ */
+ physmem = 0;
+ cfe_mem_idx = 0;
+ for (i = 0; i < 10; i += 2) {
+ int result;
+ uint64_t addr, len, type;
+
+ result = cfe_enummem(cfe_mem_idx++, 0, &addr, &len, &type);
+ if (result < 0) {
+ phys_avail[i] = phys_avail[i + 1] = 0;
+ break;
+ }
+
+ KASSERT(type == CFE_MI_AVAILABLE,
+ ("CFE DRAM region is not available?"));
+
+ if (bootverbose)
+ printf("cfe_enummem: 0x%016jx/%ju.\n", addr, len);
+
+ if (maxmem != 0) {
+ if (addr >= maxmem) {
+ printf("Ignoring %ju bytes of memory at 0x%jx "
+ "that is above maxmem %dMB\n",
+ len, addr,
+ (int)(maxmem / (1024 * 1024)));
+ continue;
+ }
+
+ if (addr + len > maxmem) {
+ printf("Ignoring %ju bytes of memory "
+ "that is above maxmem %dMB\n",
+ (addr + len) - maxmem,
+ (int)(maxmem / (1024 * 1024)));
+ len = maxmem - addr;
+ }
+ }
+
+ phys_avail[i] = addr;
+ if (i == 0 && addr == 0) {
+ /*
+ * If this is the first physical memory segment probed
+ * from CFE, omit the region at the start of physical
+ * memory where the kernel has been loaded.
+ */
+ phys_avail[i] += MIPS_KSEG0_TO_PHYS(kernel_kseg0_end);
+ }
+ phys_avail[i + 1] = addr + len;
+ physmem += len;
+ }
+
+ realmem = btoc(physmem);
+#endif
+
+ for (j = 0; j < i; j++)
+ dump_avail[j] = phys_avail[j];
+
+ physmem = realmem;
+
+ init_param1();
+ init_param2(physmem);
+ mips_cpu_init();
+
+ /*
+ * Sibyte has a L1 data cache coherent with DMA. This includes
+ * on-chip network interfaces as well as PCI/HyperTransport bus
+ * masters.
+ */
+ cpuinfo.cache_coherent_dma = TRUE;
+
+ /*
+ * XXX
+ * The kernel is running in 32-bit mode but the CFE is running in
+ * 64-bit mode. So the SR_KX bit in the status register is turned
+ * on by the CFE every time we call into it - for e.g. CFE_CONSOLE.
+ *
+ * This means that if get a TLB miss for any address above 0xc0000000
+ * and the SR_KX bit is set then we will end up in the XTLB exception
+ * vector.
+ *
+ * For now work around this by copying the TLB exception handling
+ * code to the XTLB exception vector.
+ */
+ {
+ bcopy(MipsTLBMiss, (void *)MIPS_XTLB_MISS_EXC_VEC,
+ MipsTLBMissEnd - MipsTLBMiss);
+
+ mips_icache_sync_all();
+ mips_dcache_wbinv_all();
+ }
+
+ pmap_bootstrap();
+ mips_proc0_init();
+ mutex_init();
+
+ kdb_init();
+#ifdef KDB
+ if (boothowto & RB_KDB)
+ kdb_enter(KDB_WHY_BOOTFLAGS, "Boot flags requested debugger");
+#endif
+}
+
+void
+platform_reset(void)
+{
+
+ /*
+ * XXX SMP
+ * XXX flush data caches
+ */
+ sb_system_reset();
+}
+
+static void
+kseg0_map_coherent(void)
+{
+ uint32_t config;
+ const int CFG_K0_COHERENT = 5;
+
+ config = mips_rd_config();
+ config &= ~MIPS_CONFIG_K0_MASK;
+ config |= CFG_K0_COHERENT;
+ mips_wr_config(config);
+}
+
+#ifdef SMP
+void
+platform_ipi_send(int cpuid)
+{
+ KASSERT(cpuid == 0 || cpuid == 1,
+ ("platform_ipi_send: invalid cpuid %d", cpuid));
+
+ sb_set_mailbox(cpuid, 1ULL);
+}
+
+void
+platform_ipi_clear(void)
+{
+ int cpuid;
+
+ cpuid = PCPU_GET(cpuid);
+ sb_clear_mailbox(cpuid, 1ULL);
+}
+
+int
+platform_ipi_intrnum(void)
+{
+
+ return (4);
+}
+
+struct cpu_group *
+platform_smp_topo(void)
+{
+
+ return (smp_topo_none());
+}
+
+void
+platform_init_ap(int cpuid)
+{
+ int ipi_int_mask, clock_int_mask;
+
+ KASSERT(cpuid == 1, ("AP has an invalid cpu id %d", cpuid));
+
+ /*
+ * Make sure that kseg0 is mapped cacheable-coherent
+ */
+ kseg0_map_coherent();
+
+ sb_intr_init(cpuid);
+
+ /*
+ * Unmask the clock and ipi interrupts.
+ */
+ clock_int_mask = hard_int_mask(5);
+ ipi_int_mask = hard_int_mask(platform_ipi_intrnum());
+ set_intr_mask(ipi_int_mask | clock_int_mask);
+}
+
+int
+platform_start_ap(int cpuid)
+{
+#ifdef CFE
+ int error;
+
+ if ((error = cfe_cpu_start(cpuid, mpentry, 0, 0, 0))) {
+ printf("cfe_cpu_start error: %d\n", error);
+ return (-1);
+ } else {
+ return (0);
+ }
+#else
+ return (-1);
+#endif /* CFE */
+}
+#endif /* SMP */
+
+static u_int
+sb_get_timecount(struct timecounter *tc)
+{
+
+ return ((u_int)sb_zbbus_cycle_count());
+}
+
+static void
+sb_timecounter_init(void)
+{
+ static struct timecounter sb_timecounter = {
+ sb_get_timecount,
+ NULL,
+ ~0u,
+ 0,
+ "sibyte_zbbus_counter",
+ 2000
+ };
+
+ /*
+ * The ZBbus cycle counter runs at half the cpu frequency.
+ */
+ sb_timecounter.tc_frequency = sb_cpu_speed() / 2;
+ platform_timecounter = &sb_timecounter;
+}
+
+void
+platform_start(__register_t a0, __register_t a1, __register_t a2,
+ __register_t a3)
+{
+ /*
+ * Make sure that kseg0 is mapped cacheable-coherent
+ */
+ kseg0_map_coherent();
+
+ /* clear the BSS and SBSS segments */
+ memset(&edata, 0, (vm_offset_t)&end - (vm_offset_t)&edata);
+ mips_postboot_fixup();
+
+ sb_intr_init(0);
+ sb_timecounter_init();
+
+ /* Initialize pcpu stuff */
+ mips_pcpu0_init();
+
+#ifdef CFE
+ /*
+ * Initialize CFE firmware trampolines before
+ * we initialize the low-level console.
+ *
+ * CFE passes the following values in registers:
+ * a0: firmware handle
+ * a2: firmware entry point
+ * a3: entry point seal
+ */
+ if (a3 == CFE_EPTSEAL)
+ cfe_init(a0, a2);
+#endif
+ cninit();
+
+ mips_init();
+
+ mips_timer_init_params(sb_cpu_speed(), 0);
+}
Property changes on: trunk/sys/mips/sibyte/sb_machdep.c
___________________________________________________________________
Added: svn:eol-style
## -0,0 +1 ##
+native
\ No newline at end of property
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## -0,0 +1 ##
+MidnightBSD=%H
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+text/plain
\ No newline at end of property
Added: trunk/sys/mips/sibyte/sb_scd.c
===================================================================
--- trunk/sys/mips/sibyte/sb_scd.c (rev 0)
+++ trunk/sys/mips/sibyte/sb_scd.c 2018-05-26 21:55:02 UTC (rev 9987)
@@ -0,0 +1,307 @@
+/* $MidnightBSD$ */
+/*-
+ * Copyright (c) 2009 Neelkanth Natu
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ */
+
+#include <sys/cdefs.h>
+__FBSDID("$FreeBSD: stable/10/sys/mips/sibyte/sb_scd.c 222813 2011-06-07 08:46:13Z attilio $");
+
+#include <sys/param.h>
+#include <sys/kernel.h>
+#include <sys/systm.h>
+#include <sys/module.h>
+#include <sys/bus.h>
+#include <sys/cpuset.h>
+
+#include <machine/resource.h>
+#include <machine/hwfunc.h>
+
+#include "sb_scd.h"
+
+/*
+ * We compile a 32-bit kernel to run on the SB-1 processor which is a 64-bit
+ * processor. It has some registers that must be accessed using 64-bit load
+ * and store instructions.
+ *
+ * We use the mips_ld() and mips_sd() functions to do this for us.
+ */
+#define sb_store64(addr, val) mips3_sd((uint64_t *)(uintptr_t)(addr), (val))
+#define sb_load64(addr) mips3_ld((uint64_t *)(uintptr_t)(addr))
+
+/*
+ * System Control and Debug (SCD) unit on the Sibyte ZBbus.
+ */
+
+/*
+ * Extract the value starting at bit position 'b' for 'n' bits from 'x'.
+ */
+#define GET_VAL_64(x, b, n) (((x) >> (b)) & ((1ULL << (n)) - 1))
+
+#define SYSREV_ADDR MIPS_PHYS_TO_KSEG1(0x10020000)
+#define SYSREV_NUM_PROCESSORS(x) GET_VAL_64((x), 24, 4)
+
+#define SYSCFG_ADDR MIPS_PHYS_TO_KSEG1(0x10020008)
+#define SYSCFG_PLLDIV(x) GET_VAL_64((x), 7, 5)
+
+#define ZBBUS_CYCLE_COUNT_ADDR MIPS_PHYS_TO_KSEG1(0x10030000)
+
+#define INTSRC_MASK_ADDR(cpu) \
+ (MIPS_PHYS_TO_KSEG1(0x10020028) | ((cpu) << 13))
+
+#define INTSRC_MAP_ADDR(cpu, intsrc) \
+ (MIPS_PHYS_TO_KSEG1(0x10020200) | ((cpu) << 13)) + (intsrc * 8)
+
+#define MAILBOX_SET_ADDR(cpu) \
+ (MIPS_PHYS_TO_KSEG1(0x100200C8) | ((cpu) << 13))
+
+#define MAILBOX_CLEAR_ADDR(cpu) \
+ (MIPS_PHYS_TO_KSEG1(0x100200D0) | ((cpu) << 13))
+
+static uint64_t
+sb_read_syscfg(void)
+{
+
+ return (sb_load64(SYSCFG_ADDR));
+}
+
+static void
+sb_write_syscfg(uint64_t val)
+{
+
+ sb_store64(SYSCFG_ADDR, val);
+}
+
+uint64_t
+sb_zbbus_cycle_count(void)
+{
+
+ return (sb_load64(ZBBUS_CYCLE_COUNT_ADDR));
+}
+
+uint64_t
+sb_cpu_speed(void)
+{
+ int plldiv;
+ const uint64_t MHZ = 1000000;
+
+ plldiv = SYSCFG_PLLDIV(sb_read_syscfg());
+ if (plldiv == 0) {
+ printf("PLL_DIV is 0 - assuming 6 (300MHz).\n");
+ plldiv = 6;
+ }
+
+ return (plldiv * 50 * MHZ);
+}
+
+void
+sb_system_reset(void)
+{
+ uint64_t syscfg;
+
+ const uint64_t SYSTEM_RESET = 1ULL << 60;
+ const uint64_t EXT_RESET = 1ULL << 59;
+ const uint64_t SOFT_RESET = 1ULL << 58;
+
+ syscfg = sb_read_syscfg();
+ syscfg &= ~SOFT_RESET;
+ syscfg |= SYSTEM_RESET | EXT_RESET;
+ sb_write_syscfg(syscfg);
+}
+
+void
+sb_disable_intsrc(int cpu, int src)
+{
+ int regaddr;
+ uint64_t val;
+
+ regaddr = INTSRC_MASK_ADDR(cpu);
+
+ val = sb_load64(regaddr);
+ val |= 1ULL << src;
+ sb_store64(regaddr, val);
+}
+
+void
+sb_enable_intsrc(int cpu, int src)
+{
+ int regaddr;
+ uint64_t val;
+
+ regaddr = INTSRC_MASK_ADDR(cpu);
+
+ val = sb_load64(regaddr);
+ val &= ~(1ULL << src);
+ sb_store64(regaddr, val);
+}
+
+void
+sb_write_intsrc_mask(int cpu, uint64_t val)
+{
+ int regaddr;
+
+ regaddr = INTSRC_MASK_ADDR(cpu);
+ sb_store64(regaddr, val);
+}
+
+uint64_t
+sb_read_intsrc_mask(int cpu)
+{
+ int regaddr;
+ uint64_t val;
+
+ regaddr = INTSRC_MASK_ADDR(cpu);
+ val = sb_load64(regaddr);
+
+ return (val);
+}
+
+void
+sb_write_intmap(int cpu, int intsrc, int intrnum)
+{
+ int regaddr;
+
+ regaddr = INTSRC_MAP_ADDR(cpu, intsrc);
+ sb_store64(regaddr, intrnum);
+}
+
+int
+sb_read_intmap(int cpu, int intsrc)
+{
+ int regaddr;
+
+ regaddr = INTSRC_MAP_ADDR(cpu, intsrc);
+ return (sb_load64(regaddr) & 0x7);
+}
+
+int
+sb_route_intsrc(int intsrc)
+{
+ int intrnum;
+
+ KASSERT(intsrc >= 0 && intsrc < NUM_INTSRC,
+ ("Invalid interrupt source number (%d)", intsrc));
+
+ /*
+ * Interrupt 5 is used by sources internal to the CPU (e.g. timer).
+ * Use a deterministic mapping for the remaining sources.
+ */
+#ifdef SMP
+ KASSERT(platform_ipi_intrnum() == 4,
+ ("Unexpected interrupt number used for IPI"));
+ intrnum = intsrc % 4;
+#else
+ intrnum = intsrc % 5;
+#endif
+
+ return (intrnum);
+}
+
+#ifdef SMP
+static uint64_t
+sb_read_sysrev(void)
+{
+
+ return (sb_load64(SYSREV_ADDR));
+}
+
+void
+sb_set_mailbox(int cpu, uint64_t val)
+{
+ int regaddr;
+
+ regaddr = MAILBOX_SET_ADDR(cpu);
+ sb_store64(regaddr, val);
+}
+
+void
+sb_clear_mailbox(int cpu, uint64_t val)
+{
+ int regaddr;
+
+ regaddr = MAILBOX_CLEAR_ADDR(cpu);
+ sb_store64(regaddr, val);
+}
+
+void
+platform_cpu_mask(cpuset_t *mask)
+{
+ int i, s;
+
+ CPU_ZERO(mask);
+ s = SYSREV_NUM_PROCESSORS(sb_read_sysrev());
+ for (i = 0; i < s; i++)
+ CPU_SET(i, mask);
+}
+#endif /* SMP */
+
+#define SCD_PHYSADDR 0x10000000
+#define SCD_SIZE 0x00060000
+
+static int
+scd_probe(device_t dev)
+{
+
+ device_set_desc(dev, "Broadcom/Sibyte System Control and Debug");
+ return (0);
+}
+
+static int
+scd_attach(device_t dev)
+{
+ int rid;
+ struct resource *res;
+
+ if (bootverbose)
+ device_printf(dev, "attached.\n");
+
+ rid = 0;
+ res = bus_alloc_resource(dev, SYS_RES_MEMORY, &rid, SCD_PHYSADDR,
+ SCD_PHYSADDR + SCD_SIZE - 1, SCD_SIZE, 0);
+ if (res == NULL)
+ panic("Cannot allocate resource for system control and debug.");
+
+ return (0);
+}
+
+static device_method_t scd_methods[] ={
+ /* Device interface */
+ DEVMETHOD(device_probe, scd_probe),
+ DEVMETHOD(device_attach, scd_attach),
+ DEVMETHOD(device_detach, bus_generic_detach),
+ DEVMETHOD(device_shutdown, bus_generic_shutdown),
+ DEVMETHOD(device_suspend, bus_generic_suspend),
+ DEVMETHOD(device_resume, bus_generic_resume),
+
+ { 0, 0 }
+};
+
+static driver_t scd_driver = {
+ "scd",
+ scd_methods
+};
+
+static devclass_t scd_devclass;
+
+DRIVER_MODULE(scd, zbbus, scd_driver, scd_devclass, 0, 0);
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Added: trunk/sys/mips/sibyte/sb_scd.h
===================================================================
--- trunk/sys/mips/sibyte/sb_scd.h (rev 0)
+++ trunk/sys/mips/sibyte/sb_scd.h 2018-05-26 21:55:02 UTC (rev 9987)
@@ -0,0 +1,53 @@
+/* $MidnightBSD$ */
+/*-
+ * Copyright (c) 2009 Neelkanth Natu
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ * $FreeBSD: stable/10/sys/mips/sibyte/sb_scd.h 205364 2010-03-20 05:49:06Z neel $
+ */
+
+#ifndef _SB_SCD_H_
+#define _SB_SCD_H_
+
+#define NUM_INTSRC 64 /* total number of interrupt sources */
+
+uint64_t sb_zbbus_cycle_count(void);
+uint64_t sb_cpu_speed(void);
+void sb_system_reset(void);
+
+int sb_route_intsrc(int src);
+void sb_enable_intsrc(int cpu, int src);
+void sb_disable_intsrc(int cpu, int src);
+uint64_t sb_read_intsrc_mask(int cpu);
+void sb_write_intsrc_mask(int cpu, uint64_t mask);
+void sb_write_intmap(int cpu, int intsrc, int intrnum);
+int sb_read_intmap(int cpu, int intsrc);
+
+#ifdef SMP
+#define INTSRC_MAILBOX3 29
+void sb_set_mailbox(int cpuid, uint64_t val);
+void sb_clear_mailbox(int cpuid, uint64_t val);
+#endif
+
+#endif /* _SB_SCD_H_ */
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Added: trunk/sys/mips/sibyte/sb_zbbus.c
===================================================================
--- trunk/sys/mips/sibyte/sb_zbbus.c (rev 0)
+++ trunk/sys/mips/sibyte/sb_zbbus.c 2018-05-26 21:55:02 UTC (rev 9987)
@@ -0,0 +1,463 @@
+/* $MidnightBSD$ */
+/*-
+ * Copyright (c) 2009 Neelkanth Natu
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ */
+
+#include <sys/cdefs.h>
+__FBSDID("$FreeBSD: stable/10/sys/mips/sibyte/sb_zbbus.c 265999 2014-05-14 01:35:43Z ian $");
+
+#include <sys/param.h>
+#include <sys/kernel.h>
+#include <sys/systm.h>
+#include <sys/module.h>
+#include <sys/bus.h>
+#include <sys/malloc.h>
+#include <sys/rman.h>
+#include <sys/lock.h>
+#include <sys/mutex.h>
+
+#include <machine/resource.h>
+#include <machine/intr_machdep.h>
+
+#include "sb_scd.h"
+
+static MALLOC_DEFINE(M_INTMAP, "sb1250 intmap", "Sibyte 1250 Interrupt Mapper");
+
+static struct mtx zbbus_intr_mtx;
+MTX_SYSINIT(zbbus_intr_mtx, &zbbus_intr_mtx, "zbbus_intr_mask/unmask lock",
+ MTX_SPIN);
+
+/*
+ * This array holds the mapping between a MIPS hard interrupt and the
+ * interrupt sources that feed into that it.
+ */
+static uint64_t hardint_to_intsrc_mask[NHARD_IRQS];
+
+struct sb_intmap {
+ int intsrc; /* interrupt mapper register number (0 - 63) */
+ int hardint; /* cpu interrupt from 0 to NHARD_IRQS - 1 */
+
+ /*
+ * The device that the interrupt belongs to. Note that multiple
+ * devices may share an interrupt. For e.g. PCI_INT_x lines.
+ *
+ * The device 'dev' in combination with the 'rid' uniquely
+ * identify this interrupt source.
+ */
+ device_t dev;
+ int rid;
+
+ SLIST_ENTRY(sb_intmap) next;
+};
+
+static SLIST_HEAD(, sb_intmap) sb_intmap_head;
+
+static struct sb_intmap *
+sb_intmap_lookup(int intrnum, device_t dev, int rid)
+{
+ struct sb_intmap *map;
+
+ SLIST_FOREACH(map, &sb_intmap_head, next) {
+ if (dev == map->dev && rid == map->rid &&
+ intrnum == map->hardint)
+ break;
+ }
+ return (map);
+}
+
+/*
+ * Keep track of which (dev,rid,hardint) tuple is using the interrupt source.
+ *
+ * We don't actually unmask the interrupt source until the device calls
+ * a bus_setup_intr() on the resource.
+ */
+static void
+sb_intmap_add(int intrnum, device_t dev, int rid, int intsrc)
+{
+ struct sb_intmap *map;
+
+ KASSERT(intrnum >= 0 && intrnum < NHARD_IRQS,
+ ("intrnum is out of range: %d", intrnum));
+
+ map = sb_intmap_lookup(intrnum, dev, rid);
+ if (map) {
+ KASSERT(intsrc == map->intsrc,
+ ("%s%d allocating SYS_RES_IRQ resource with rid %d "
+ "with a different intsrc (%d versus %d)",
+ device_get_name(dev), device_get_unit(dev), rid,
+ intsrc, map->intsrc));
+ return;
+ }
+
+ map = malloc(sizeof(*map), M_INTMAP, M_WAITOK | M_ZERO);
+ map->intsrc = intsrc;
+ map->hardint = intrnum;
+ map->dev = dev;
+ map->rid = rid;
+
+ SLIST_INSERT_HEAD(&sb_intmap_head, map, next);
+}
+
+static void
+sb_intmap_activate(int intrnum, device_t dev, int rid)
+{
+ struct sb_intmap *map;
+
+ KASSERT(intrnum >= 0 && intrnum < NHARD_IRQS,
+ ("intrnum is out of range: %d", intrnum));
+
+ map = sb_intmap_lookup(intrnum, dev, rid);
+ if (map) {
+ /*
+ * Deliver all interrupts to CPU0.
+ */
+ mtx_lock_spin(&zbbus_intr_mtx);
+ hardint_to_intsrc_mask[intrnum] |= 1ULL << map->intsrc;
+ sb_enable_intsrc(0, map->intsrc);
+ mtx_unlock_spin(&zbbus_intr_mtx);
+ } else {
+ /*
+ * In zbbus_setup_intr() we blindly call sb_intmap_activate()
+ * for every interrupt activation that comes our way.
+ *
+ * We might end up here if we did not "hijack" the SYS_RES_IRQ
+ * resource in zbbus_alloc_resource().
+ */
+ printf("sb_intmap_activate: unable to activate interrupt %d "
+ "for device %s%d rid %d.\n", intrnum,
+ device_get_name(dev), device_get_unit(dev), rid);
+ }
+}
+
+/*
+ * Replace the default interrupt mask and unmask routines in intr_machdep.c
+ * with routines that are SMP-friendly. In contrast to the default mask/unmask
+ * routines in intr_machdep.c these routines do not change the SR.int_mask bits.
+ *
+ * Instead they use the interrupt mapper to either mask or unmask all
+ * interrupt sources feeding into a particular interrupt line of the processor.
+ *
+ * This means that these routines have an identical effect irrespective of
+ * which cpu is executing them. This is important because the ithread may
+ * be scheduled to run on either of the cpus.
+ */
+static void
+zbbus_intr_mask(void *arg)
+{
+ uint64_t mask;
+ int irq;
+
+ irq = (uintptr_t)arg;
+
+ mtx_lock_spin(&zbbus_intr_mtx);
+
+ mask = sb_read_intsrc_mask(0);
+ mask |= hardint_to_intsrc_mask[irq];
+ sb_write_intsrc_mask(0, mask);
+
+ mtx_unlock_spin(&zbbus_intr_mtx);
+}
+
+static void
+zbbus_intr_unmask(void *arg)
+{
+ uint64_t mask;
+ int irq;
+
+ irq = (uintptr_t)arg;
+
+ mtx_lock_spin(&zbbus_intr_mtx);
+
+ mask = sb_read_intsrc_mask(0);
+ mask &= ~hardint_to_intsrc_mask[irq];
+ sb_write_intsrc_mask(0, mask);
+
+ mtx_unlock_spin(&zbbus_intr_mtx);
+}
+
+struct zbbus_devinfo {
+ struct resource_list resources;
+};
+
+static MALLOC_DEFINE(M_ZBBUSDEV, "zbbusdev", "zbbusdev");
+
+static int
+zbbus_probe(device_t dev)
+{
+
+ device_set_desc(dev, "Broadcom/Sibyte ZBbus");
+ return (BUS_PROBE_NOWILDCARD);
+}
+
+static int
+zbbus_attach(device_t dev)
+{
+
+ if (bootverbose) {
+ device_printf(dev, "attached.\n");
+ }
+
+ cpu_set_hardintr_mask_func(zbbus_intr_mask);
+ cpu_set_hardintr_unmask_func(zbbus_intr_unmask);
+
+ bus_generic_probe(dev);
+ bus_enumerate_hinted_children(dev);
+ bus_generic_attach(dev);
+
+ return (0);
+}
+
+static void
+zbbus_hinted_child(device_t bus, const char *dname, int dunit)
+{
+ device_t child;
+ long maddr, msize;
+ int err, irq;
+
+ if (resource_disabled(dname, dunit))
+ return;
+
+ child = BUS_ADD_CHILD(bus, 0, dname, dunit);
+ if (child == NULL) {
+ panic("zbbus: could not add child %s unit %d\n", dname, dunit);
+ }
+
+ if (bootverbose)
+ device_printf(bus, "Adding hinted child %s%d\n", dname, dunit);
+
+ /*
+ * Assign any pre-defined resources to the child.
+ */
+ if (resource_long_value(dname, dunit, "msize", &msize) == 0 &&
+ resource_long_value(dname, dunit, "maddr", &maddr) == 0) {
+ if (bootverbose) {
+ device_printf(bus, "Assigning memory resource "
+ "0x%0lx/%ld to child %s%d\n",
+ maddr, msize, dname, dunit);
+ }
+ err = bus_set_resource(child, SYS_RES_MEMORY, 0, maddr, msize);
+ if (err) {
+ device_printf(bus, "Unable to set memory resource "
+ "0x%0lx/%ld for child %s%d: %d\n",
+ maddr, msize, dname, dunit, err);
+ }
+ }
+
+ if (resource_int_value(dname, dunit, "irq", &irq) == 0) {
+ if (bootverbose) {
+ device_printf(bus, "Assigning irq resource %d to "
+ "child %s%d\n", irq, dname, dunit);
+ }
+ err = bus_set_resource(child, SYS_RES_IRQ, 0, irq, 1);
+ if (err) {
+ device_printf(bus, "Unable to set irq resource %d"
+ "for child %s%d: %d\n",
+ irq, dname, dunit, err);
+ }
+ }
+}
+
+static struct resource *
+zbbus_alloc_resource(device_t bus, device_t child, int type, int *rid,
+ u_long start, u_long end, u_long count, u_int flags)
+{
+ struct resource *res;
+ int intrnum, intsrc, isdefault;
+ struct resource_list *rl;
+ struct resource_list_entry *rle;
+ struct zbbus_devinfo *dinfo;
+
+ isdefault = (start == 0UL && end == ~0UL && count == 1);
+
+ /*
+ * Our direct child is asking for a default resource allocation.
+ */
+ if (device_get_parent(child) == bus) {
+ dinfo = device_get_ivars(child);
+ rl = &dinfo->resources;
+ rle = resource_list_find(rl, type, *rid);
+ if (rle) {
+ if (rle->res)
+ panic("zbbus_alloc_resource: resource is busy");
+ if (isdefault) {
+ start = rle->start;
+ count = ulmax(count, rle->count);
+ end = ulmax(rle->end, start + count - 1);
+ }
+ } else {
+ if (isdefault) {
+ /*
+ * Our child is requesting a default
+ * resource allocation but we don't have the
+ * 'type/rid' tuple in the resource list.
+ *
+ * We have to fail the resource allocation.
+ */
+ return (NULL);
+ } else {
+ /*
+ * The child is requesting a non-default
+ * resource. We just pass the request up
+ * to our parent. If the resource allocation
+ * succeeds we will create a resource list
+ * entry corresponding to that resource.
+ */
+ }
+ }
+ } else {
+ rl = NULL;
+ rle = NULL;
+ }
+
+ /*
+ * nexus doesn't know about the interrupt mapper and only wants to
+ * see the hard irq numbers [0-6]. We translate from the interrupt
+ * source presented to the mapper to the interrupt number presented
+ * to the cpu.
+ */
+ if ((count == 1) && (type == SYS_RES_IRQ)) {
+ intsrc = start;
+ intrnum = sb_route_intsrc(intsrc);
+ start = end = intrnum;
+ } else {
+ intsrc = -1; /* satisfy gcc */
+ intrnum = -1;
+ }
+
+ res = bus_generic_alloc_resource(bus, child, type, rid,
+ start, end, count, flags);
+
+ /*
+ * Keep track of the input into the interrupt mapper that maps
+ * to the resource allocated by 'child' with resource id 'rid'.
+ *
+ * If we don't record the mapping here then we won't be able to
+ * locate the interrupt source when bus_setup_intr(child,rid) is
+ * called.
+ */
+ if (res != NULL && intrnum != -1)
+ sb_intmap_add(intrnum, child, rman_get_rid(res), intsrc);
+
+ /*
+ * If a non-default resource allocation by our child was successful
+ * then keep track of the resource in the resource list associated
+ * with the child.
+ */
+ if (res != NULL && rle == NULL && device_get_parent(child) == bus) {
+ resource_list_add(rl, type, *rid, start, end, count);
+ rle = resource_list_find(rl, type, *rid);
+ if (rle == NULL)
+ panic("zbbus_alloc_resource: cannot find resource");
+ }
+
+ if (rle != NULL) {
+ KASSERT(device_get_parent(child) == bus,
+ ("rle should be NULL for passthru device"));
+ rle->res = res;
+ if (rle->res) {
+ rle->start = rman_get_start(rle->res);
+ rle->end = rman_get_end(rle->res);
+ rle->count = count;
+ }
+ }
+
+ return (res);
+}
+
+static int
+zbbus_setup_intr(device_t dev, device_t child, struct resource *irq, int flags,
+ driver_filter_t *filter, driver_intr_t *intr, void *arg,
+ void **cookiep)
+{
+ int error;
+
+ error = bus_generic_setup_intr(dev, child, irq, flags,
+ filter, intr, arg, cookiep);
+ if (error == 0)
+ sb_intmap_activate(rman_get_start(irq), child,
+ rman_get_rid(irq));
+
+ return (error);
+}
+
+static device_t
+zbbus_add_child(device_t bus, u_int order, const char *name, int unit)
+{
+ device_t child;
+ struct zbbus_devinfo *dinfo;
+
+ child = device_add_child_ordered(bus, order, name, unit);
+ if (child != NULL) {
+ dinfo = malloc(sizeof(struct zbbus_devinfo), M_ZBBUSDEV,
+ M_WAITOK | M_ZERO);
+ resource_list_init(&dinfo->resources);
+ device_set_ivars(child, dinfo);
+ }
+
+ return (child);
+}
+
+static struct resource_list *
+zbbus_get_resource_list(device_t dev, device_t child)
+{
+ struct zbbus_devinfo *dinfo = device_get_ivars(child);
+
+ return (&dinfo->resources);
+}
+
+static device_method_t zbbus_methods[] ={
+ /* Device interface */
+ DEVMETHOD(device_probe, zbbus_probe),
+ DEVMETHOD(device_attach, zbbus_attach),
+ DEVMETHOD(device_detach, bus_generic_detach),
+ DEVMETHOD(device_shutdown, bus_generic_shutdown),
+ DEVMETHOD(device_suspend, bus_generic_suspend),
+ DEVMETHOD(device_resume, bus_generic_resume),
+
+ /* Bus interface */
+ DEVMETHOD(bus_alloc_resource, zbbus_alloc_resource),
+ DEVMETHOD(bus_activate_resource, bus_generic_activate_resource),
+ DEVMETHOD(bus_deactivate_resource, bus_generic_deactivate_resource),
+ DEVMETHOD(bus_release_resource, bus_generic_release_resource),
+ DEVMETHOD(bus_get_resource_list,zbbus_get_resource_list),
+ DEVMETHOD(bus_set_resource, bus_generic_rl_set_resource),
+ DEVMETHOD(bus_get_resource, bus_generic_rl_get_resource),
+ DEVMETHOD(bus_delete_resource, bus_generic_rl_delete_resource),
+ DEVMETHOD(bus_setup_intr, zbbus_setup_intr),
+ DEVMETHOD(bus_teardown_intr, bus_generic_teardown_intr),
+ DEVMETHOD(bus_add_child, zbbus_add_child),
+ DEVMETHOD(bus_hinted_child, zbbus_hinted_child),
+
+ { 0, 0 }
+};
+
+static driver_t zbbus_driver = {
+ "zbbus",
+ zbbus_methods
+};
+
+static devclass_t zbbus_devclass;
+
+DRIVER_MODULE(zbbus, nexus, zbbus_driver, zbbus_devclass, 0, 0);
Property changes on: trunk/sys/mips/sibyte/sb_zbbus.c
___________________________________________________________________
Added: svn:eol-style
## -0,0 +1 ##
+native
\ No newline at end of property
Added: svn:keywords
## -0,0 +1 ##
+MidnightBSD=%H
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+text/plain
\ No newline at end of property
Added: trunk/sys/mips/sibyte/sb_zbpci.c
===================================================================
--- trunk/sys/mips/sibyte/sb_zbpci.c (rev 0)
+++ trunk/sys/mips/sibyte/sb_zbpci.c 2018-05-26 21:55:02 UTC (rev 9987)
@@ -0,0 +1,544 @@
+/* $MidnightBSD$ */
+/*-
+ * Copyright (c) 2009 Neelkanth Natu
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ */
+
+#include <sys/param.h>
+#include <sys/types.h>
+#include <sys/kernel.h>
+#include <sys/systm.h>
+#include <sys/module.h>
+#include <sys/bus.h>
+#include <sys/rman.h>
+#include <sys/pcpu.h>
+#include <sys/smp.h>
+
+#include <vm/vm.h>
+#include <vm/vm_param.h>
+#include <vm/vm_kern.h>
+#include <vm/vm_extern.h>
+#include <vm/pmap.h>
+
+#include <dev/pci/pcireg.h>
+#include <dev/pci/pcivar.h>
+#include <dev/pci/pcib_private.h>
+
+#include <machine/pmap.h>
+#include <machine/resource.h>
+#include <machine/bus.h>
+
+#include "pcib_if.h"
+
+#include "sb_bus_space.h"
+#include "sb_scd.h"
+
+__FBSDID("$FreeBSD: stable/10/sys/mips/sibyte/sb_zbpci.c 254025 2013-08-07 06:21:20Z jeff $");
+
+static struct {
+ vm_offset_t vaddr;
+ vm_paddr_t paddr;
+} zbpci_config_space[MAXCPU];
+
+static const vm_paddr_t CFG_PADDR_BASE = 0xFE000000;
+static const u_long PCI_IOSPACE_ADDR = 0xFC000000;
+static const u_long PCI_IOSPACE_SIZE = 0x02000000;
+
+#define PCI_MATCH_BYTE_LANES_START 0x40000000
+#define PCI_MATCH_BYTE_LANES_END 0x5FFFFFFF
+#define PCI_MATCH_BYTE_LANES_SIZE 0x20000000
+
+#define PCI_MATCH_BIT_LANES_MASK (1 << 29)
+#define PCI_MATCH_BIT_LANES_START 0x60000000
+#define PCI_MATCH_BIT_LANES_END 0x7FFFFFFF
+#define PCI_MATCH_BIT_LANES_SIZE 0x20000000
+
+static struct rman port_rman;
+
+static int
+zbpci_probe(device_t dev)
+{
+
+ device_set_desc(dev, "Broadcom/Sibyte PCI I/O Bridge");
+ return (0);
+}
+
+static int
+zbpci_attach(device_t dev)
+{
+ int n, rid, size;
+ vm_offset_t va;
+ struct resource *res;
+
+ /*
+ * Reserve the physical memory window used to map PCI I/O space.
+ */
+ rid = 0;
+ res = bus_alloc_resource(dev, SYS_RES_MEMORY, &rid,
+ PCI_IOSPACE_ADDR,
+ PCI_IOSPACE_ADDR + PCI_IOSPACE_SIZE - 1,
+ PCI_IOSPACE_SIZE, 0);
+ if (res == NULL)
+ panic("Cannot allocate resource for PCI I/O space mapping.");
+
+ port_rman.rm_start = 0;
+ port_rman.rm_end = PCI_IOSPACE_SIZE - 1;
+ port_rman.rm_type = RMAN_ARRAY;
+ port_rman.rm_descr = "PCI I/O ports";
+ if (rman_init(&port_rman) != 0 ||
+ rman_manage_region(&port_rman, 0, PCI_IOSPACE_SIZE - 1) != 0)
+ panic("%s: port_rman", __func__);
+
+ /*
+ * Reserve the physical memory that is used to read/write to the
+ * pci config space but don't activate it. We are using a page worth
+ * of KVA as a window over this region.
+ */
+ rid = 1;
+ size = (PCI_BUSMAX + 1) * (PCI_SLOTMAX + 1) * (PCI_FUNCMAX + 1) * 256;
+ res = bus_alloc_resource(dev, SYS_RES_MEMORY, &rid, CFG_PADDR_BASE,
+ CFG_PADDR_BASE + size - 1, size, 0);
+ if (res == NULL)
+ panic("Cannot allocate resource for config space accesses.");
+
+ /*
+ * Allocate the entire "match bit lanes" address space.
+ */
+#if _BYTE_ORDER == _BIG_ENDIAN
+ rid = 2;
+ res = bus_alloc_resource(dev, SYS_RES_MEMORY, &rid,
+ PCI_MATCH_BIT_LANES_START,
+ PCI_MATCH_BIT_LANES_END,
+ PCI_MATCH_BIT_LANES_SIZE, 0);
+ if (res == NULL)
+ panic("Cannot allocate resource for pci match bit lanes.");
+#endif /* _BYTE_ORDER ==_BIG_ENDIAN */
+
+ /*
+ * Allocate KVA for accessing PCI config space.
+ */
+ va = kva_alloc(PAGE_SIZE * mp_ncpus);
+ if (va == 0) {
+ device_printf(dev, "Cannot allocate virtual addresses for "
+ "config space access.\n");
+ return (ENOMEM);
+ }
+
+ for (n = 0; n < mp_ncpus; ++n)
+ zbpci_config_space[n].vaddr = va + n * PAGE_SIZE;
+
+ /*
+ * Sibyte has the PCI bus hierarchy rooted at bus 0 and HT-PCI
+ * hierarchy rooted at bus 1.
+ */
+ if (device_add_child(dev, "pci", 0) == NULL)
+ panic("zbpci_attach: could not add pci bus 0.\n");
+
+ if (device_add_child(dev, "pci", 1) == NULL)
+ panic("zbpci_attach: could not add pci bus 1.\n");
+
+ if (bootverbose)
+ device_printf(dev, "attached.\n");
+
+ return (bus_generic_attach(dev));
+}
+
+static struct resource *
+zbpci_alloc_resource(device_t bus, device_t child, int type, int *rid,
+ u_long start, u_long end, u_long count, u_int flags)
+{
+ struct resource *res;
+
+ /*
+ * Handle PCI I/O port resources here and pass everything else to nexus.
+ */
+ if (type != SYS_RES_IOPORT) {
+ res = bus_generic_alloc_resource(bus, child, type, rid,
+ start, end, count, flags);
+ return (res);
+ }
+
+ res = rman_reserve_resource(&port_rman, start, end, count,
+ flags, child);
+ if (res == NULL)
+ return (NULL);
+
+ rman_set_rid(res, *rid);
+
+ /* Activate the resource is requested */
+ if (flags & RF_ACTIVE) {
+ if (bus_activate_resource(child, type, *rid, res) != 0) {
+ rman_release_resource(res);
+ return (NULL);
+ }
+ }
+
+ return (res);
+}
+
+static int
+zbpci_activate_resource(device_t bus, device_t child, int type, int rid,
+ struct resource *res)
+{
+ int error;
+ void *vaddr;
+ u_long orig_paddr, paddr, psize;
+
+ paddr = rman_get_start(res);
+ psize = rman_get_size(res);
+ orig_paddr = paddr;
+
+#if _BYTE_ORDER == _BIG_ENDIAN
+ /*
+ * The CFE allocates PCI memory resources that map to the
+ * "match byte lanes" address space. This address space works
+ * best for DMA transfers because it does not do any automatic
+ * byte swaps when data crosses the pci-cpu interface.
+ *
+ * This also makes it sub-optimal for accesses to PCI device
+ * registers because it exposes the little-endian nature of
+ * the PCI bus to the big-endian CPU. The Sibyte has another
+ * address window called the "match bit lanes" window which
+ * automatically swaps bytes when data crosses the pci-cpu
+ * interface.
+ *
+ * We "assume" that any bus_space memory accesses done by the
+ * CPU to a PCI device are register/configuration accesses and
+ * are done through the "match bit lanes" window. Any DMA
+ * transfers will continue to be through the "match byte lanes"
+ * window because the PCI BAR registers will not be changed.
+ */
+ if (type == SYS_RES_MEMORY) {
+ if (paddr >= PCI_MATCH_BYTE_LANES_START &&
+ paddr + psize - 1 <= PCI_MATCH_BYTE_LANES_END) {
+ paddr |= PCI_MATCH_BIT_LANES_MASK;
+ rman_set_start(res, paddr);
+ rman_set_end(res, paddr + psize - 1);
+ }
+ }
+#endif
+
+ if (type != SYS_RES_IOPORT) {
+ error = bus_generic_activate_resource(bus, child, type,
+ rid, res);
+#if _BYTE_ORDER == _BIG_ENDIAN
+ if (type == SYS_RES_MEMORY) {
+ rman_set_start(res, orig_paddr);
+ rman_set_end(res, orig_paddr + psize - 1);
+ }
+#endif
+ return (error);
+ }
+
+ /*
+ * Map the I/O space resource through the memory window starting
+ * at PCI_IOSPACE_ADDR.
+ */
+ vaddr = pmap_mapdev(paddr + PCI_IOSPACE_ADDR, psize);
+
+ rman_set_virtual(res, vaddr);
+ rman_set_bustag(res, mips_bus_space_generic);
+ rman_set_bushandle(res, (bus_space_handle_t)vaddr);
+
+ return (rman_activate_resource(res));
+}
+
+static int
+zbpci_release_resource(device_t bus, device_t child, int type, int rid,
+ struct resource *r)
+{
+ int error;
+
+ if (type != SYS_RES_IOPORT)
+ return (bus_generic_release_resource(bus, child, type, rid, r));
+
+ if (rman_get_flags(r) & RF_ACTIVE) {
+ error = bus_deactivate_resource(child, type, rid, r);
+ if (error)
+ return (error);
+ }
+
+ return (rman_release_resource(r));
+}
+
+static int
+zbpci_deactivate_resource(device_t bus, device_t child, int type, int rid,
+ struct resource *r)
+{
+ vm_offset_t va;
+
+ if (type != SYS_RES_IOPORT) {
+ return (bus_generic_deactivate_resource(bus, child, type,
+ rid, r));
+ }
+
+ va = (vm_offset_t)rman_get_virtual(r);
+ pmap_unmapdev(va, rman_get_size(r));
+
+ return (rman_deactivate_resource(r));
+}
+
+static int
+zbpci_read_ivar(device_t dev, device_t child, int which, uintptr_t *result)
+{
+
+ switch (which) {
+ case PCIB_IVAR_DOMAIN:
+ *result = 0; /* single PCI domain */
+ return (0);
+ case PCIB_IVAR_BUS:
+ *result = device_get_unit(child); /* PCI bus 0 or 1 */
+ return (0);
+ default:
+ return (ENOENT);
+ }
+}
+
+/*
+ * We rely on the CFE to have configured the intline correctly to point to
+ * one of PCI-A/PCI-B/PCI-C/PCI-D in the interupt mapper.
+ */
+static int
+zbpci_route_interrupt(device_t pcib, device_t dev, int pin)
+{
+
+ return (PCI_INVALID_IRQ);
+}
+
+/*
+ * This function is expected to be called in a critical section since it
+ * changes the per-cpu pci config space va-to-pa mappings.
+ */
+static vm_offset_t
+zbpci_config_space_va(int bus, int slot, int func, int reg, int bytes)
+{
+ int cpu;
+ vm_offset_t va_page;
+ vm_paddr_t pa, pa_page;
+
+ if (bus <= PCI_BUSMAX && slot <= PCI_SLOTMAX && func <= PCI_FUNCMAX &&
+ reg <= PCI_REGMAX && (bytes == 1 || bytes == 2 || bytes == 4) &&
+ ((reg & (bytes - 1)) == 0)) {
+ cpu = PCPU_GET(cpuid);
+ va_page = zbpci_config_space[cpu].vaddr;
+ pa = CFG_PADDR_BASE |
+ (bus << 16) | (slot << 11) | (func << 8) | reg;
+#if _BYTE_ORDER == _BIG_ENDIAN
+ pa = pa ^ (4 - bytes);
+#endif
+ pa_page = pa & ~(PAGE_SIZE - 1);
+ if (zbpci_config_space[cpu].paddr != pa_page) {
+ pmap_kremove(va_page);
+ pmap_kenter_attr(va_page, pa_page, PTE_C_UNCACHED);
+ zbpci_config_space[cpu].paddr = pa_page;
+ }
+ return (va_page + (pa - pa_page));
+ } else {
+ return (0);
+ }
+}
+
+static uint32_t
+zbpci_read_config(device_t dev, u_int b, u_int s, u_int f, u_int r, int w)
+{
+ uint32_t data;
+ vm_offset_t va;
+
+ critical_enter();
+
+ va = zbpci_config_space_va(b, s, f, r, w);
+ if (va == 0) {
+ panic("zbpci_read_config: invalid %d/%d/%d[%d] %d\n",
+ b, s, f, r, w);
+ }
+
+ switch (w) {
+ case 4:
+ data = *(uint32_t *)va;
+ break;
+ case 2:
+ data = *(uint16_t *)va;
+ break;
+ case 1:
+ data = *(uint8_t *)va;
+ break;
+ default:
+ panic("zbpci_read_config: invalid width %d\n", w);
+ }
+
+ critical_exit();
+
+ return (data);
+}
+
+static void
+zbpci_write_config(device_t d, u_int b, u_int s, u_int f, u_int r,
+ uint32_t data, int w)
+{
+ vm_offset_t va;
+
+ critical_enter();
+
+ va = zbpci_config_space_va(b, s, f, r, w);
+ if (va == 0) {
+ panic("zbpci_write_config: invalid %d/%d/%d[%d] %d/%d\n",
+ b, s, f, r, data, w);
+ }
+
+ switch (w) {
+ case 4:
+ *(uint32_t *)va = data;
+ break;
+ case 2:
+ *(uint16_t *)va = data;
+ break;
+ case 1:
+ *(uint8_t *)va = data;
+ break;
+ default:
+ panic("zbpci_write_config: invalid width %d\n", w);
+ }
+
+ critical_exit();
+}
+
+static device_method_t zbpci_methods[] ={
+ /* Device interface */
+ DEVMETHOD(device_probe, zbpci_probe),
+ DEVMETHOD(device_attach, zbpci_attach),
+ DEVMETHOD(device_detach, bus_generic_detach),
+ DEVMETHOD(device_shutdown, bus_generic_shutdown),
+ DEVMETHOD(device_suspend, bus_generic_suspend),
+ DEVMETHOD(device_resume, bus_generic_resume),
+
+ /* Bus interface */
+ DEVMETHOD(bus_read_ivar, zbpci_read_ivar),
+ DEVMETHOD(bus_write_ivar, bus_generic_write_ivar),
+ DEVMETHOD(bus_alloc_resource, zbpci_alloc_resource),
+ DEVMETHOD(bus_activate_resource, zbpci_activate_resource),
+ DEVMETHOD(bus_deactivate_resource, zbpci_deactivate_resource),
+ DEVMETHOD(bus_release_resource, zbpci_release_resource),
+ DEVMETHOD(bus_setup_intr, bus_generic_setup_intr),
+ DEVMETHOD(bus_teardown_intr, bus_generic_teardown_intr),
+ DEVMETHOD(bus_add_child, bus_generic_add_child),
+
+ /* pcib interface */
+ DEVMETHOD(pcib_maxslots, pcib_maxslots),
+ DEVMETHOD(pcib_read_config, zbpci_read_config),
+ DEVMETHOD(pcib_write_config, zbpci_write_config),
+ DEVMETHOD(pcib_route_interrupt, zbpci_route_interrupt),
+
+ { 0, 0 }
+};
+
+/*
+ * The "zbpci" class inherits from the "pcib" base class. Therefore in
+ * addition to drivers that belong to the "zbpci" class we will also
+ * consider drivers belonging to the "pcib" when probing children of
+ * "zbpci".
+ */
+DEFINE_CLASS_1(zbpci, zbpci_driver, zbpci_methods, 0, pcib_driver);
+
+static devclass_t zbpci_devclass;
+
+DRIVER_MODULE(zbpci, zbbus, zbpci_driver, zbpci_devclass, 0, 0);
+
+/*
+ * Big endian bus space routines
+ */
+#if _BYTE_ORDER == _BIG_ENDIAN
+
+/*
+ * The CPU correctly deals with the big-endian to little-endian swap if
+ * we are accessing 4 bytes at a time. However if we want to read 1 or 2
+ * bytes then we need to fudge the address generated by the CPU such that
+ * it generates the right byte enables on the PCI bus.
+ */
+static bus_addr_t
+sb_match_bit_lane_addr(bus_addr_t addr, int bytes)
+{
+ vm_offset_t pa;
+
+ pa = vtophys(addr);
+
+ if (pa >= PCI_MATCH_BIT_LANES_START && pa <= PCI_MATCH_BIT_LANES_END)
+ return (addr ^ (4 - bytes));
+ else
+ return (addr);
+}
+
+uint8_t
+sb_big_endian_read8(bus_addr_t addr)
+{
+ bus_addr_t addr2;
+
+ addr2 = sb_match_bit_lane_addr(addr, 1);
+ return (readb(addr2));
+}
+
+uint16_t
+sb_big_endian_read16(bus_addr_t addr)
+{
+ bus_addr_t addr2;
+
+ addr2 = sb_match_bit_lane_addr(addr, 2);
+ return (readw(addr2));
+}
+
+uint32_t
+sb_big_endian_read32(bus_addr_t addr)
+{
+ bus_addr_t addr2;
+
+ addr2 = sb_match_bit_lane_addr(addr, 4);
+ return (readl(addr2));
+}
+
+void
+sb_big_endian_write8(bus_addr_t addr, uint8_t val)
+{
+ bus_addr_t addr2;
+
+ addr2 = sb_match_bit_lane_addr(addr, 1);
+ writeb(addr2, val);
+}
+
+void
+sb_big_endian_write16(bus_addr_t addr, uint16_t val)
+{
+ bus_addr_t addr2;
+
+ addr2 = sb_match_bit_lane_addr(addr, 2);
+ writew(addr2, val);
+}
+
+void
+sb_big_endian_write32(bus_addr_t addr, uint32_t val)
+{
+ bus_addr_t addr2;
+
+ addr2 = sb_match_bit_lane_addr(addr, 4);
+ writel(addr2, val);
+}
+#endif /* _BIG_ENDIAN */
Property changes on: trunk/sys/mips/sibyte/sb_zbpci.c
___________________________________________________________________
Added: svn:eol-style
## -0,0 +1 ##
+native
\ No newline at end of property
Added: svn:keywords
## -0,0 +1 ##
+MidnightBSD=%H
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+text/plain
\ No newline at end of property
Added: trunk/sys/mips/sibyte/std.sibyte
===================================================================
--- trunk/sys/mips/sibyte/std.sibyte (rev 0)
+++ trunk/sys/mips/sibyte/std.sibyte 2018-05-26 21:55:02 UTC (rev 9987)
@@ -0,0 +1,3 @@
+# $FreeBSD: stable/10/sys/mips/sibyte/std.sibyte 215270 2010-11-13 22:34:12Z imp $
+
+files "../sibyte/files.sibyte"
Property changes on: trunk/sys/mips/sibyte/std.sibyte
___________________________________________________________________
Added: mnbsd:nokeywords
## -0,0 +1 ##
+MidnightBSD=%H
\ No newline at end of property
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