[Midnightbsd-cvs] src [10073] trunk/sys/dev/sdhci: sync sdhci
laffer1 at midnightbsd.org
laffer1 at midnightbsd.org
Sun May 27 19:15:22 EDT 2018
Revision: 10073
http://svnweb.midnightbsd.org/src/?rev=10073
Author: laffer1
Date: 2018-05-27 19:15:22 -0400 (Sun, 27 May 2018)
Log Message:
-----------
sync sdhci
Modified Paths:
--------------
trunk/sys/dev/sdhci/sdhci.c
trunk/sys/dev/sdhci/sdhci.h
Added Paths:
-----------
trunk/sys/dev/sdhci/sdhci_acpi.c
trunk/sys/dev/sdhci/sdhci_fdt.c
trunk/sys/dev/sdhci/sdhci_if.m
trunk/sys/dev/sdhci/sdhci_pci.c
Modified: trunk/sys/dev/sdhci/sdhci.c
===================================================================
--- trunk/sys/dev/sdhci/sdhci.c 2018-05-27 23:14:46 UTC (rev 10072)
+++ trunk/sys/dev/sdhci/sdhci.c 2018-05-27 23:15:22 UTC (rev 10073)
@@ -1,5 +1,7 @@
+/* $MidnightBSD$ */
/*-
* Copyright (c) 2008 Alexander Motin <mav at FreeBSD.org>
+ * Copyright (c) 2017 Marius Strobl <marius at FreeBSD.org>
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
@@ -24,14 +26,17 @@
*/
#include <sys/cdefs.h>
-__MBSDID("$MidnightBSD$");
+__FBSDID("$FreeBSD: stable/10/sys/dev/sdhci/sdhci.c 331035 2018-03-15 22:58:34Z marius $");
#include <sys/param.h>
#include <sys/systm.h>
#include <sys/bus.h>
+#include <sys/callout.h>
#include <sys/conf.h>
#include <sys/kernel.h>
+#include <sys/kobj.h>
#include <sys/lock.h>
+#include <sys/malloc.h>
#include <sys/module.h>
#include <sys/mutex.h>
#include <sys/resource.h>
@@ -39,9 +44,6 @@
#include <sys/sysctl.h>
#include <sys/taskqueue.h>
-#include <dev/pci/pcireg.h>
-#include <dev/pci/pcivar.h>
-
#include <machine/bus.h>
#include <machine/resource.h>
#include <machine/stdarg.h>
@@ -50,189 +52,92 @@
#include <dev/mmc/mmcreg.h>
#include <dev/mmc/mmcbrvar.h>
+#include <dev/sdhci/sdhci.h>
+
#include "mmcbr_if.h"
-#include "sdhci.h"
+#include "sdhci_if.h"
-#define DMA_BLOCK_SIZE 4096
-#define DMA_BOUNDARY 0 /* DMA reload every 4K */
+SYSCTL_NODE(_hw, OID_AUTO, sdhci, CTLFLAG_RD, 0, "sdhci driver");
-/* Controller doesn't honor resets unless we touch the clock register */
-#define SDHCI_QUIRK_CLOCK_BEFORE_RESET (1<<0)
-/* Controller really supports DMA */
-#define SDHCI_QUIRK_FORCE_DMA (1<<1)
-/* Controller has unusable DMA engine */
-#define SDHCI_QUIRK_BROKEN_DMA (1<<2)
-/* Controller doesn't like to be reset when there is no card inserted. */
-#define SDHCI_QUIRK_NO_CARD_NO_RESET (1<<3)
-/* Controller has flaky internal state so reset it on each ios change */
-#define SDHCI_QUIRK_RESET_ON_IOS (1<<4)
-/* Controller can only DMA chunk sizes that are a multiple of 32 bits */
-#define SDHCI_QUIRK_32BIT_DMA_SIZE (1<<5)
-/* Controller needs to be reset after each request to stay stable */
-#define SDHCI_QUIRK_RESET_AFTER_REQUEST (1<<6)
-/* Controller has an off-by-one issue with timeout value */
-#define SDHCI_QUIRK_INCR_TIMEOUT_CONTROL (1<<7)
-/* Controller has broken read timings */
-#define SDHCI_QUIRK_BROKEN_TIMINGS (1<<8)
-/* Controller needs lowered frequency */
-#define SDHCI_QUIRK_LOWER_FREQUENCY (1<<9)
+static int sdhci_debug;
+TUNABLE_INT("hw.sdhci.debug", &sdhci_debug);
+SYSCTL_INT(_hw_sdhci, OID_AUTO, debug, CTLFLAG_RWTUN, &sdhci_debug, 0,
+ "Debug level");
+u_int sdhci_quirk_clear = 0;
+SYSCTL_INT(_hw_sdhci, OID_AUTO, quirk_clear, CTLFLAG_RWTUN, &sdhci_quirk_clear,
+ 0, "Mask of quirks to clear");
+u_int sdhci_quirk_set = 0;
+SYSCTL_INT(_hw_sdhci, OID_AUTO, quirk_set, CTLFLAG_RWTUN, &sdhci_quirk_set, 0,
+ "Mask of quirks to set");
-static const struct sdhci_device {
- uint32_t model;
- uint16_t subvendor;
- char *desc;
- u_int quirks;
-} sdhci_devices[] = {
- { 0x08221180, 0xffff, "RICOH R5C822 SD",
- SDHCI_QUIRK_FORCE_DMA },
- { 0xe8221180, 0xffff, "RICOH SD",
- SDHCI_QUIRK_FORCE_DMA },
- { 0xe8231180, 0xffff, "RICOH R5CE823 SD",
- SDHCI_QUIRK_LOWER_FREQUENCY },
- { 0x8034104c, 0xffff, "TI XX21/XX11 SD",
- SDHCI_QUIRK_FORCE_DMA },
- { 0x05501524, 0xffff, "ENE CB712 SD",
- SDHCI_QUIRK_BROKEN_TIMINGS },
- { 0x05511524, 0xffff, "ENE CB712 SD 2",
- SDHCI_QUIRK_BROKEN_TIMINGS },
- { 0x07501524, 0xffff, "ENE CB714 SD",
- SDHCI_QUIRK_RESET_ON_IOS |
- SDHCI_QUIRK_BROKEN_TIMINGS },
- { 0x07511524, 0xffff, "ENE CB714 SD 2",
- SDHCI_QUIRK_RESET_ON_IOS |
- SDHCI_QUIRK_BROKEN_TIMINGS },
- { 0x410111ab, 0xffff, "Marvell CaFe SD",
- SDHCI_QUIRK_INCR_TIMEOUT_CONTROL },
- { 0x2381197B, 0xffff, "JMicron JMB38X SD",
- SDHCI_QUIRK_32BIT_DMA_SIZE |
- SDHCI_QUIRK_RESET_AFTER_REQUEST },
- { 0, 0xffff, NULL,
- 0 }
-};
+#define RD1(slot, off) SDHCI_READ_1((slot)->bus, (slot), (off))
+#define RD2(slot, off) SDHCI_READ_2((slot)->bus, (slot), (off))
+#define RD4(slot, off) SDHCI_READ_4((slot)->bus, (slot), (off))
+#define RD_MULTI_4(slot, off, ptr, count) \
+ SDHCI_READ_MULTI_4((slot)->bus, (slot), (off), (ptr), (count))
-struct sdhci_softc;
+#define WR1(slot, off, val) SDHCI_WRITE_1((slot)->bus, (slot), (off), (val))
+#define WR2(slot, off, val) SDHCI_WRITE_2((slot)->bus, (slot), (off), (val))
+#define WR4(slot, off, val) SDHCI_WRITE_4((slot)->bus, (slot), (off), (val))
+#define WR_MULTI_4(slot, off, ptr, count) \
+ SDHCI_WRITE_MULTI_4((slot)->bus, (slot), (off), (ptr), (count))
-struct sdhci_slot {
- struct sdhci_softc *sc;
- device_t dev; /* Slot device */
- u_char num; /* Slot number */
- u_char opt; /* Slot options */
-#define SDHCI_HAVE_DMA 1
- uint32_t max_clk; /* Max possible freq */
- uint32_t timeout_clk; /* Timeout freq */
- struct resource *mem_res; /* Memory resource */
- int mem_rid;
- bus_dma_tag_t dmatag;
- bus_dmamap_t dmamap;
- u_char *dmamem;
- bus_addr_t paddr; /* DMA buffer address */
- struct task card_task; /* Card presence check task */
- struct callout card_callout; /* Card insert delay callout */
- struct mmc_host host; /* Host parameters */
- struct mmc_request *req; /* Current request */
- struct mmc_command *curcmd; /* Current command of current request */
-
- uint32_t intmask; /* Current interrupt mask */
- uint32_t clock; /* Current clock freq. */
- size_t offset; /* Data buffer offset */
- uint8_t hostctrl; /* Current host control register */
- u_char power; /* Current power */
- u_char bus_busy; /* Bus busy status */
- u_char cmd_done; /* CMD command part done flag */
- u_char data_done; /* DAT command part done flag */
- u_char flags; /* Request execution flags */
-#define CMD_STARTED 1
-#define STOP_STARTED 2
-#define SDHCI_USE_DMA 4 /* Use DMA for this req. */
- struct mtx mtx; /* Slot mutex */
-};
+static void sdhci_card_poll(void *arg);
+static void sdhci_card_task(void *arg, int pending);
+static int sdhci_exec_tuning(struct sdhci_slot *slot, bool reset);
+static void sdhci_req_wakeup(struct mmc_request *req);
+static void sdhci_retune(void *arg);
+static void sdhci_set_clock(struct sdhci_slot *slot, uint32_t clock);
+static void sdhci_start(struct sdhci_slot *slot);
+static void sdhci_start_data(struct sdhci_slot *slot, struct mmc_data *data);
-struct sdhci_softc {
- device_t dev; /* Controller device */
- u_int quirks; /* Chip specific quirks */
- struct resource *irq_res; /* IRQ resource */
- int irq_rid;
- void *intrhand; /* Interrupt handle */
+/* helper routines */
+static void sdhci_dumpregs(struct sdhci_slot *slot);
+static int slot_printf(struct sdhci_slot *slot, const char * fmt, ...)
+ __printflike(2, 3);
+static uint32_t sdhci_tuning_intmask(struct sdhci_slot *slot);
- int num_slots; /* Number of slots on this controller */
- struct sdhci_slot slots[6];
-};
+#define SDHCI_LOCK(_slot) mtx_lock(&(_slot)->mtx)
+#define SDHCI_UNLOCK(_slot) mtx_unlock(&(_slot)->mtx)
+#define SDHCI_LOCK_INIT(_slot) \
+ mtx_init(&_slot->mtx, "SD slot mtx", "sdhci", MTX_DEF)
+#define SDHCI_LOCK_DESTROY(_slot) mtx_destroy(&_slot->mtx);
+#define SDHCI_ASSERT_LOCKED(_slot) mtx_assert(&_slot->mtx, MA_OWNED);
+#define SDHCI_ASSERT_UNLOCKED(_slot) mtx_assert(&_slot->mtx, MA_NOTOWNED);
-static SYSCTL_NODE(_hw, OID_AUTO, sdhci, CTLFLAG_RD, 0, "sdhci driver");
+#define SDHCI_DEFAULT_MAX_FREQ 50
-int sdhci_debug;
-TUNABLE_INT("hw.sdhci.debug", &sdhci_debug);
-SYSCTL_INT(_hw_sdhci, OID_AUTO, debug, CTLFLAG_RW, &sdhci_debug, 0, "Debug level");
+#define SDHCI_200_MAX_DIVIDER 256
+#define SDHCI_300_MAX_DIVIDER 2046
-static inline uint8_t
-RD1(struct sdhci_slot *slot, bus_size_t off)
-{
- bus_barrier(slot->mem_res, 0, 0xFF,
- BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE);
- return bus_read_1(slot->mem_res, off);
-}
+#define SDHCI_CARD_PRESENT_TICKS (hz / 5)
+#define SDHCI_INSERT_DELAY_TICKS (hz / 2)
-static inline void
-WR1(struct sdhci_slot *slot, bus_size_t off, uint8_t val)
-{
- bus_barrier(slot->mem_res, 0, 0xFF,
- BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE);
- bus_write_1(slot->mem_res, off, val);
-}
+/*
+ * Broadcom BCM577xx Controller Constants
+ */
+/* Maximum divider supported by the default clock source. */
+#define BCM577XX_DEFAULT_MAX_DIVIDER 256
+/* Alternative clock's base frequency. */
+#define BCM577XX_ALT_CLOCK_BASE 63000000
-static inline uint16_t
-RD2(struct sdhci_slot *slot, bus_size_t off)
-{
- bus_barrier(slot->mem_res, 0, 0xFF,
- BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE);
- return bus_read_2(slot->mem_res, off);
-}
+#define BCM577XX_HOST_CONTROL 0x198
+#define BCM577XX_CTRL_CLKSEL_MASK 0xFFFFCFFF
+#define BCM577XX_CTRL_CLKSEL_SHIFT 12
+#define BCM577XX_CTRL_CLKSEL_DEFAULT 0x0
+#define BCM577XX_CTRL_CLKSEL_64MHZ 0x3
-static inline void
-WR2(struct sdhci_slot *slot, bus_size_t off, uint16_t val)
+static void
+sdhci_getaddr(void *arg, bus_dma_segment_t *segs, int nsegs, int error)
{
- bus_barrier(slot->mem_res, 0, 0xFF,
- BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE);
- bus_write_2(slot->mem_res, off, val);
-}
-static inline uint32_t
-RD4(struct sdhci_slot *slot, bus_size_t off)
-{
- bus_barrier(slot->mem_res, 0, 0xFF,
- BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE);
- return bus_read_4(slot->mem_res, off);
+ if (error != 0) {
+ printf("getaddr: error %d\n", error);
+ return;
+ }
+ *(bus_addr_t *)arg = segs[0].ds_addr;
}
-static inline void
-WR4(struct sdhci_slot *slot, bus_size_t off, uint32_t val)
-{
- bus_barrier(slot->mem_res, 0, 0xFF,
- BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE);
- bus_write_4(slot->mem_res, off, val);
-}
-
-/* bus entry points */
-static int sdhci_probe(device_t dev);
-static int sdhci_attach(device_t dev);
-static int sdhci_detach(device_t dev);
-static void sdhci_intr(void *);
-
-static void sdhci_set_clock(struct sdhci_slot *slot, uint32_t clock);
-static void sdhci_start(struct sdhci_slot *slot);
-static void sdhci_start_data(struct sdhci_slot *slot, struct mmc_data *data);
-
-static void sdhci_card_task(void *, int);
-
-/* helper routines */
-#define SDHCI_LOCK(_slot) mtx_lock(&(_slot)->mtx)
-#define SDHCI_UNLOCK(_slot) mtx_unlock(&(_slot)->mtx)
-#define SDHCI_LOCK_INIT(_slot) \
- mtx_init(&_slot->mtx, "SD slot mtx", "sdhci", MTX_DEF)
-#define SDHCI_LOCK_DESTROY(_slot) mtx_destroy(&_slot->mtx);
-#define SDHCI_ASSERT_LOCKED(_slot) mtx_assert(&_slot->mtx, MA_OWNED);
-#define SDHCI_ASSERT_UNLOCKED(_slot) mtx_assert(&_slot->mtx, MA_NOTOWNED);
-
static int
slot_printf(struct sdhci_slot *slot, const char * fmt, ...)
{
@@ -239,8 +144,8 @@
va_list ap;
int retval;
- retval = printf("%s-slot%d: ",
- device_get_nameunit(slot->sc->dev), slot->num);
+ retval = printf("%s-slot%d: ",
+ device_get_nameunit(slot->bus), slot->num);
va_start(ap, fmt);
retval += vprintf(fmt, ap);
@@ -249,18 +154,9 @@
}
static void
-sdhci_getaddr(void *arg, bus_dma_segment_t *segs, int nsegs, int error)
+sdhci_dumpregs(struct sdhci_slot *slot)
{
- if (error != 0) {
- printf("getaddr: error %d\n", error);
- return;
- }
- *(bus_addr_t *)arg = segs[0].ds_addr;
-}
-static void
-sdhci_dumpregs(struct sdhci_slot *slot)
-{
slot_printf(slot,
"============== REGISTER DUMP ==============\n");
@@ -280,10 +176,14 @@
RD1(slot, SDHCI_TIMEOUT_CONTROL), RD4(slot, SDHCI_INT_STATUS));
slot_printf(slot, "Int enab: 0x%08x | Sig enab: 0x%08x\n",
RD4(slot, SDHCI_INT_ENABLE), RD4(slot, SDHCI_SIGNAL_ENABLE));
- slot_printf(slot, "AC12 err: 0x%08x | Slot int: 0x%08x\n",
- RD2(slot, SDHCI_ACMD12_ERR), RD2(slot, SDHCI_SLOT_INT_STATUS));
- slot_printf(slot, "Caps: 0x%08x | Max curr: 0x%08x\n",
- RD4(slot, SDHCI_CAPABILITIES), RD4(slot, SDHCI_MAX_CURRENT));
+ slot_printf(slot, "AC12 err: 0x%08x | Host ctl2:0x%08x\n",
+ RD2(slot, SDHCI_ACMD12_ERR), RD2(slot, SDHCI_HOST_CONTROL2));
+ slot_printf(slot, "Caps: 0x%08x | Caps2: 0x%08x\n",
+ RD4(slot, SDHCI_CAPABILITIES), RD4(slot, SDHCI_CAPABILITIES2));
+ slot_printf(slot, "Max curr: 0x%08x | ADMA err: 0x%08x\n",
+ RD4(slot, SDHCI_MAX_CURRENT), RD1(slot, SDHCI_ADMA_ERR));
+ slot_printf(slot, "ADMA addr:0x%08x | Slot int: 0x%08x\n",
+ RD4(slot, SDHCI_ADMA_ADDRESS_LO), RD2(slot, SDHCI_SLOT_INT_STATUS));
slot_printf(slot,
"===========================================\n");
@@ -293,19 +193,16 @@
sdhci_reset(struct sdhci_slot *slot, uint8_t mask)
{
int timeout;
- uint8_t res;
+ uint32_t clock;
- if (slot->sc->quirks & SDHCI_QUIRK_NO_CARD_NO_RESET) {
- if (!(RD4(slot, SDHCI_PRESENT_STATE) &
- SDHCI_CARD_PRESENT))
+ if (slot->quirks & SDHCI_QUIRK_NO_CARD_NO_RESET) {
+ if (!SDHCI_GET_CARD_PRESENT(slot->bus, slot))
return;
}
/* Some controllers need this kick or reset won't work. */
if ((mask & SDHCI_RESET_ALL) == 0 &&
- (slot->sc->quirks & SDHCI_QUIRK_CLOCK_BEFORE_RESET)) {
- uint32_t clock;
-
+ (slot->quirks & SDHCI_QUIRK_CLOCK_BEFORE_RESET)) {
/* This is to force an update */
clock = slot->clock;
slot->clock = 0;
@@ -312,29 +209,61 @@
sdhci_set_clock(slot, clock);
}
- WR1(slot, SDHCI_SOFTWARE_RESET, mask);
-
if (mask & SDHCI_RESET_ALL) {
slot->clock = 0;
slot->power = 0;
}
+ WR1(slot, SDHCI_SOFTWARE_RESET, mask);
+
+ if (slot->quirks & SDHCI_QUIRK_WAITFOR_RESET_ASSERTED) {
+ /*
+ * Resets on TI OMAPs and AM335x are incompatible with SDHCI
+ * specification. The reset bit has internal propagation delay,
+ * so a fast read after write returns 0 even if reset process is
+ * in progress. The workaround is to poll for 1 before polling
+ * for 0. In the worst case, if we miss seeing it asserted the
+ * time we spent waiting is enough to ensure the reset finishes.
+ */
+ timeout = 10000;
+ while ((RD1(slot, SDHCI_SOFTWARE_RESET) & mask) != mask) {
+ if (timeout <= 0)
+ break;
+ timeout--;
+ DELAY(1);
+ }
+ }
+
/* Wait max 100 ms */
- timeout = 100;
+ timeout = 10000;
/* Controller clears the bits when it's done */
- while ((res = RD1(slot, SDHCI_SOFTWARE_RESET)) & mask) {
- if (timeout == 0) {
- slot_printf(slot,
- "Reset 0x%x never completed - 0x%x.\n",
- (int)mask, (int)res);
+ while (RD1(slot, SDHCI_SOFTWARE_RESET) & mask) {
+ if (timeout <= 0) {
+ slot_printf(slot, "Reset 0x%x never completed.\n",
+ mask);
sdhci_dumpregs(slot);
return;
}
timeout--;
- DELAY(1000);
+ DELAY(10);
}
}
+static uint32_t
+sdhci_tuning_intmask(struct sdhci_slot *slot)
+{
+ uint32_t intmask;
+
+ intmask = 0;
+ if (slot->opt & SDHCI_TUNING_ENABLED) {
+ intmask |= SDHCI_INT_TUNEERR;
+ if (slot->retune_mode == SDHCI_RETUNE_MODE_2 ||
+ slot->retune_mode == SDHCI_RETUNE_MODE_3)
+ intmask |= SDHCI_INT_RETUNE;
+ }
+ return (intmask);
+}
+
static void
sdhci_init(struct sdhci_slot *slot)
{
@@ -345,37 +274,27 @@
slot->intmask = SDHCI_INT_BUS_POWER | SDHCI_INT_DATA_END_BIT |
SDHCI_INT_DATA_CRC | SDHCI_INT_DATA_TIMEOUT | SDHCI_INT_INDEX |
SDHCI_INT_END_BIT | SDHCI_INT_CRC | SDHCI_INT_TIMEOUT |
- SDHCI_INT_CARD_REMOVE | SDHCI_INT_CARD_INSERT |
SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL |
SDHCI_INT_DMA_END | SDHCI_INT_DATA_END | SDHCI_INT_RESPONSE |
SDHCI_INT_ACMD12ERR;
+
+ if (!(slot->quirks & SDHCI_QUIRK_POLL_CARD_PRESENT) &&
+ !(slot->opt & SDHCI_NON_REMOVABLE)) {
+ slot->intmask |= SDHCI_INT_CARD_REMOVE | SDHCI_INT_CARD_INSERT;
+ }
+
WR4(slot, SDHCI_INT_ENABLE, slot->intmask);
WR4(slot, SDHCI_SIGNAL_ENABLE, slot->intmask);
}
static void
-sdhci_lower_frequency(device_t dev)
-{
-
- /* Enable SD2.0 mode. */
- pci_write_config(dev, SDHC_PCI_MODE_KEY, 0xfc, 1);
- pci_write_config(dev, SDHC_PCI_MODE, SDHC_PCI_MODE_SD20, 1);
- pci_write_config(dev, SDHC_PCI_MODE_KEY, 0x00, 1);
-
- /*
- * Some SD/MMC cards don't work with the default base
- * clock frequency of 200MHz. Lower it to 50Hz.
- */
- pci_write_config(dev, SDHC_PCI_BASE_FREQ_KEY, 0x01, 1);
- pci_write_config(dev, SDHC_PCI_BASE_FREQ, 50, 1);
- pci_write_config(dev, SDHC_PCI_BASE_FREQ_KEY, 0x00, 1);
-}
-
-static void
sdhci_set_clock(struct sdhci_slot *slot, uint32_t clock)
{
+ uint32_t clk_base;
+ uint32_t clk_sel;
uint32_t res;
uint16_t clk;
+ uint16_t div;
int timeout;
if (clock == slot->clock)
@@ -383,21 +302,69 @@
slot->clock = clock;
/* Turn off the clock. */
- WR2(slot, SDHCI_CLOCK_CONTROL, 0);
- /* If no clock requested - left it so. */
+ clk = RD2(slot, SDHCI_CLOCK_CONTROL);
+ WR2(slot, SDHCI_CLOCK_CONTROL, clk & ~SDHCI_CLOCK_CARD_EN);
+ /* If no clock requested - leave it so. */
if (clock == 0)
return;
- /* Looking for highest freq <= clock. */
- res = slot->max_clk;
- for (clk = 1; clk < 256; clk <<= 1) {
- if (res <= clock)
- break;
- res >>= 1;
+
+ /* Determine the clock base frequency */
+ clk_base = slot->max_clk;
+ if (slot->quirks & SDHCI_QUIRK_BCM577XX_400KHZ_CLKSRC) {
+ clk_sel = RD2(slot, BCM577XX_HOST_CONTROL) &
+ BCM577XX_CTRL_CLKSEL_MASK;
+
+ /*
+ * Select clock source appropriate for the requested frequency.
+ */
+ if ((clk_base / BCM577XX_DEFAULT_MAX_DIVIDER) > clock) {
+ clk_base = BCM577XX_ALT_CLOCK_BASE;
+ clk_sel |= (BCM577XX_CTRL_CLKSEL_64MHZ <<
+ BCM577XX_CTRL_CLKSEL_SHIFT);
+ } else {
+ clk_sel |= (BCM577XX_CTRL_CLKSEL_DEFAULT <<
+ BCM577XX_CTRL_CLKSEL_SHIFT);
+ }
+
+ WR2(slot, BCM577XX_HOST_CONTROL, clk_sel);
}
- /* Divider 1:1 is 0x00, 2:1 is 0x01, 256:1 is 0x80 ... */
- clk >>= 1;
+
+ /* Recalculate timeout clock frequency based on the new sd clock. */
+ if (slot->quirks & SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK)
+ slot->timeout_clk = slot->clock / 1000;
+
+ if (slot->version < SDHCI_SPEC_300) {
+ /* Looking for highest freq <= clock. */
+ res = clk_base;
+ for (div = 1; div < SDHCI_200_MAX_DIVIDER; div <<= 1) {
+ if (res <= clock)
+ break;
+ res >>= 1;
+ }
+ /* Divider 1:1 is 0x00, 2:1 is 0x01, 256:1 is 0x80 ... */
+ div >>= 1;
+ } else {
+ /* Version 3.0 divisors are multiples of two up to 1023 * 2 */
+ if (clock >= clk_base)
+ div = 0;
+ else {
+ for (div = 2; div < SDHCI_300_MAX_DIVIDER; div += 2) {
+ if ((clk_base / div) <= clock)
+ break;
+ }
+ }
+ div >>= 1;
+ }
+
+ if (bootverbose || sdhci_debug)
+ slot_printf(slot, "Divider %d for freq %d (base %d)\n",
+ div, clock, clk_base);
+
/* Now we have got divider, set it. */
- clk <<= SDHCI_DIVIDER_SHIFT;
+ clk = (div & SDHCI_DIVIDER_MASK) << SDHCI_DIVIDER_SHIFT;
+ clk |= ((div >> SDHCI_DIVIDER_MASK_LEN) & SDHCI_DIVIDER_HI_MASK)
+ << SDHCI_DIVIDER_HI_SHIFT;
+
WR2(slot, SDHCI_CLOCK_CONTROL, clk);
/* Enable clock. */
clk |= SDHCI_CLOCK_INT_EN;
@@ -407,7 +374,7 @@
while (!((clk = RD2(slot, SDHCI_CLOCK_CONTROL))
& SDHCI_CLOCK_INT_STABLE)) {
if (timeout == 0) {
- slot_printf(slot,
+ slot_printf(slot,
"Internal clock never stabilised.\n");
sdhci_dumpregs(slot);
return;
@@ -423,16 +390,18 @@
static void
sdhci_set_power(struct sdhci_slot *slot, u_char power)
{
+ int i;
uint8_t pwr;
if (slot->power == power)
return;
+
slot->power = power;
/* Turn off the power. */
pwr = 0;
WR1(slot, SDHCI_POWER_CONTROL, pwr);
- /* If power down requested - left it so. */
+ /* If power down requested - leave it so. */
if (power == 0)
return;
/* Set voltage. */
@@ -450,9 +419,27 @@
break;
}
WR1(slot, SDHCI_POWER_CONTROL, pwr);
- /* Turn on the power. */
+ /*
+ * Turn on VDD1 power. Note that at least some Intel controllers can
+ * fail to enable bus power on the first try after transiting from D3
+ * to D0, so we give them up to 2 ms.
+ */
pwr |= SDHCI_POWER_ON;
- WR1(slot, SDHCI_POWER_CONTROL, pwr);
+ for (i = 0; i < 20; i++) {
+ WR1(slot, SDHCI_POWER_CONTROL, pwr);
+ if (RD1(slot, SDHCI_POWER_CONTROL) & SDHCI_POWER_ON)
+ break;
+ DELAY(100);
+ }
+ if (!(RD1(slot, SDHCI_POWER_CONTROL) & SDHCI_POWER_ON))
+ slot_printf(slot, "Bus power failed to enable");
+
+ if (slot->quirks & SDHCI_QUIRK_INTEL_POWER_UP_RESET) {
+ WR1(slot, SDHCI_POWER_CONTROL, pwr | 0x10);
+ DELAY(10);
+ WR1(slot, SDHCI_POWER_CONTROL, pwr);
+ DELAY(300);
+ }
}
static void
@@ -469,9 +456,9 @@
slot->offset += left;
/* If we are too fast, broken controllers return zeroes. */
- if (slot->sc->quirks & SDHCI_QUIRK_BROKEN_TIMINGS)
+ if (slot->quirks & SDHCI_QUIRK_BROKEN_TIMINGS)
DELAY(10);
- /* Handle unalligned and alligned buffer cases. */
+ /* Handle unaligned and aligned buffer cases. */
if ((intptr_t)buffer & 3) {
while (left > 3) {
data = RD4(slot, SDHCI_BUFFER);
@@ -483,7 +470,7 @@
left -= 4;
}
} else {
- bus_read_multi_stream_4(slot->mem_res, SDHCI_BUFFER,
+ RD_MULTI_4(slot, SDHCI_BUFFER,
(uint32_t *)buffer, left >> 2);
left &= 3;
}
@@ -511,7 +498,7 @@
left = min(512, slot->curcmd->data->len - slot->offset);
slot->offset += left;
- /* Handle unalligned and alligned buffer cases. */
+ /* Handle unaligned and aligned buffer cases. */
if ((intptr_t)buffer & 3) {
while (left > 3) {
data = buffer[0] +
@@ -523,7 +510,7 @@
WR4(slot, SDHCI_BUFFER, data);
}
} else {
- bus_write_multi_stream_4(slot->mem_res, SDHCI_BUFFER,
+ WR_MULTI_4(slot, SDHCI_BUFFER,
(uint32_t *)buffer, left >> 2);
left &= 3;
}
@@ -560,311 +547,557 @@
}
}
-static void
-sdhci_card_delay(void *arg)
-{
- struct sdhci_slot *slot = arg;
-
- taskqueue_enqueue(taskqueue_swi_giant, &slot->card_task);
-}
-
static void
-sdhci_card_task(void *arg, int pending)
+sdhci_card_task(void *arg, int pending __unused)
{
struct sdhci_slot *slot = arg;
+ device_t d;
SDHCI_LOCK(slot);
- if (RD4(slot, SDHCI_PRESENT_STATE) & SDHCI_CARD_PRESENT) {
+ if (SDHCI_GET_CARD_PRESENT(slot->bus, slot)) {
if (slot->dev == NULL) {
/* If card is present - attach mmc bus. */
- slot->dev = device_add_child(slot->sc->dev, "mmc", -1);
- device_set_ivars(slot->dev, slot);
+ if (bootverbose || sdhci_debug)
+ slot_printf(slot, "Card inserted\n");
+ d = slot->dev = device_add_child(slot->bus, "mmc", -1);
SDHCI_UNLOCK(slot);
- device_probe_and_attach(slot->dev);
+ if (d) {
+ device_set_ivars(d, slot);
+ (void)device_probe_and_attach(d);
+ }
} else
SDHCI_UNLOCK(slot);
} else {
if (slot->dev != NULL) {
/* If no card present - detach mmc bus. */
- device_t d = slot->dev;
+ if (bootverbose || sdhci_debug)
+ slot_printf(slot, "Card removed\n");
+ d = slot->dev;
slot->dev = NULL;
+ slot->intmask &= ~sdhci_tuning_intmask(slot);
+ WR4(slot, SDHCI_INT_ENABLE, slot->intmask);
+ WR4(slot, SDHCI_SIGNAL_ENABLE, slot->intmask);
+ slot->opt &= ~SDHCI_TUNING_ENABLED;
SDHCI_UNLOCK(slot);
- device_delete_child(slot->sc->dev, d);
+ callout_drain(&slot->retune_callout);
+ device_delete_child(slot->bus, d);
} else
SDHCI_UNLOCK(slot);
}
}
-static int
-sdhci_probe(device_t dev)
+static void
+sdhci_handle_card_present_locked(struct sdhci_slot *slot, bool is_present)
{
- uint32_t model;
- uint16_t subvendor;
- uint8_t class, subclass;
- int i, result;
-
- model = (uint32_t)pci_get_device(dev) << 16;
- model |= (uint32_t)pci_get_vendor(dev) & 0x0000ffff;
- subvendor = pci_get_subvendor(dev);
- class = pci_get_class(dev);
- subclass = pci_get_subclass(dev);
-
- result = ENXIO;
- for (i = 0; sdhci_devices[i].model != 0; i++) {
- if (sdhci_devices[i].model == model &&
- (sdhci_devices[i].subvendor == 0xffff ||
- sdhci_devices[i].subvendor == subvendor)) {
- device_set_desc(dev, sdhci_devices[i].desc);
- result = BUS_PROBE_DEFAULT;
- break;
- }
+ bool was_present;
+
+ /*
+ * If there was no card and now there is one, schedule the task to
+ * create the child device after a short delay. The delay is to
+ * debounce the card insert (sometimes the card detect pin stabilizes
+ * before the other pins have made good contact).
+ *
+ * If there was a card present and now it's gone, immediately schedule
+ * the task to delete the child device. No debouncing -- gone is gone,
+ * because once power is removed, a full card re-init is needed, and
+ * that happens by deleting and recreating the child device.
+ */
+ was_present = slot->dev != NULL;
+ if (!was_present && is_present) {
+ taskqueue_enqueue_timeout(taskqueue_swi_giant,
+ &slot->card_delayed_task, -SDHCI_INSERT_DELAY_TICKS);
+ } else if (was_present && !is_present) {
+ taskqueue_enqueue(taskqueue_swi_giant, &slot->card_task);
}
- if (result == ENXIO && class == PCIC_BASEPERIPH &&
- subclass == PCIS_BASEPERIPH_SDHC) {
- device_set_desc(dev, "Generic SD HCI");
- result = BUS_PROBE_GENERIC;
- }
-
- return (result);
}
-static int
-sdhci_attach(device_t dev)
+void
+sdhci_handle_card_present(struct sdhci_slot *slot, bool is_present)
{
- struct sdhci_softc *sc = device_get_softc(dev);
- uint32_t model;
- uint16_t subvendor;
- uint8_t class, subclass, progif;
- int err, slots, bar, i;
- sc->dev = dev;
- model = (uint32_t)pci_get_device(dev) << 16;
- model |= (uint32_t)pci_get_vendor(dev) & 0x0000ffff;
- subvendor = pci_get_subvendor(dev);
- class = pci_get_class(dev);
- subclass = pci_get_subclass(dev);
- progif = pci_get_progif(dev);
- /* Apply chip specific quirks. */
- for (i = 0; sdhci_devices[i].model != 0; i++) {
- if (sdhci_devices[i].model == model &&
- (sdhci_devices[i].subvendor == 0xffff ||
- sdhci_devices[i].subvendor == subvendor)) {
- sc->quirks = sdhci_devices[i].quirks;
- break;
- }
+ SDHCI_LOCK(slot);
+ sdhci_handle_card_present_locked(slot, is_present);
+ SDHCI_UNLOCK(slot);
+}
+
+static void
+sdhci_card_poll(void *arg)
+{
+ struct sdhci_slot *slot = arg;
+
+ sdhci_handle_card_present(slot,
+ SDHCI_GET_CARD_PRESENT(slot->bus, slot));
+ callout_reset(&slot->card_poll_callout, SDHCI_CARD_PRESENT_TICKS,
+ sdhci_card_poll, slot);
+}
+
+int
+sdhci_init_slot(device_t dev, struct sdhci_slot *slot, int num)
+{
+ kobjop_desc_t kobj_desc;
+ kobj_method_t *kobj_method;
+ uint32_t caps, caps2, freq, host_caps;
+ int err;
+
+ SDHCI_LOCK_INIT(slot);
+ slot->num = num;
+ slot->bus = dev;
+
+ /* Allocate DMA tag. */
+ err = bus_dma_tag_create(bus_get_dma_tag(dev),
+ DMA_BLOCK_SIZE, 0, BUS_SPACE_MAXADDR_32BIT,
+ BUS_SPACE_MAXADDR, NULL, NULL,
+ DMA_BLOCK_SIZE, 1, DMA_BLOCK_SIZE,
+ BUS_DMA_ALLOCNOW, NULL, NULL,
+ &slot->dmatag);
+ if (err != 0) {
+ device_printf(dev, "Can't create DMA tag\n");
+ SDHCI_LOCK_DESTROY(slot);
+ return (err);
}
- /* Some controllers need to be bumped into the right mode. */
- if (sc->quirks & SDHCI_QUIRK_LOWER_FREQUENCY)
- sdhci_lower_frequency(dev);
- /* Read slots info from PCI registers. */
- slots = pci_read_config(dev, PCI_SLOT_INFO, 1);
- bar = PCI_SLOT_INFO_FIRST_BAR(slots);
- slots = PCI_SLOT_INFO_SLOTS(slots);
- if (slots > 6 || bar > 5) {
- device_printf(dev, "Incorrect slots information (%d, %d).\n",
- slots, bar);
- return (EINVAL);
+ /* Allocate DMA memory. */
+ err = bus_dmamem_alloc(slot->dmatag, (void **)&slot->dmamem,
+ BUS_DMA_NOWAIT, &slot->dmamap);
+ if (err != 0) {
+ device_printf(dev, "Can't alloc DMA memory\n");
+ bus_dma_tag_destroy(slot->dmatag);
+ SDHCI_LOCK_DESTROY(slot);
+ return (err);
}
- /* Allocate IRQ. */
- sc->irq_rid = 0;
- sc->irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &sc->irq_rid,
- RF_SHAREABLE | RF_ACTIVE);
- if (sc->irq_res == NULL) {
- device_printf(dev, "Can't allocate IRQ\n");
- return (ENOMEM);
+ /* Map the memory. */
+ err = bus_dmamap_load(slot->dmatag, slot->dmamap,
+ (void *)slot->dmamem, DMA_BLOCK_SIZE,
+ sdhci_getaddr, &slot->paddr, 0);
+ if (err != 0 || slot->paddr == 0) {
+ device_printf(dev, "Can't load DMA memory\n");
+ bus_dmamem_free(slot->dmatag, slot->dmamem, slot->dmamap);
+ bus_dma_tag_destroy(slot->dmatag);
+ SDHCI_LOCK_DESTROY(slot);
+ if (err)
+ return (err);
+ else
+ return (EFAULT);
}
- /* Scan all slots. */
- for (i = 0; i < slots; i++) {
- struct sdhci_slot *slot = &sc->slots[sc->num_slots];
- uint32_t caps;
- SDHCI_LOCK_INIT(slot);
- slot->sc = sc;
- slot->num = sc->num_slots;
- /* Allocate memory. */
- slot->mem_rid = PCIR_BAR(bar + i);
- slot->mem_res = bus_alloc_resource(dev,
- SYS_RES_MEMORY, &slot->mem_rid, 0ul, ~0ul, 0x100, RF_ACTIVE);
- if (slot->mem_res == NULL) {
- device_printf(dev, "Can't allocate memory\n");
+ slot->version = (RD2(slot, SDHCI_HOST_VERSION)
+ >> SDHCI_SPEC_VER_SHIFT) & SDHCI_SPEC_VER_MASK;
+ if (slot->quirks & SDHCI_QUIRK_MISSING_CAPS) {
+ caps = slot->caps;
+ caps2 = slot->caps2;
+ } else {
+ caps = RD4(slot, SDHCI_CAPABILITIES);
+ if (slot->version >= SDHCI_SPEC_300)
+ caps2 = RD4(slot, SDHCI_CAPABILITIES2);
+ else
+ caps2 = 0;
+ }
+ if (slot->version >= SDHCI_SPEC_300) {
+ if ((caps & SDHCI_SLOTTYPE_MASK) != SDHCI_SLOTTYPE_REMOVABLE &&
+ (caps & SDHCI_SLOTTYPE_MASK) != SDHCI_SLOTTYPE_EMBEDDED) {
+ device_printf(dev,
+ "Driver doesn't support shared bus slots\n");
+ bus_dmamap_unload(slot->dmatag, slot->dmamap);
+ bus_dmamem_free(slot->dmatag, slot->dmamem,
+ slot->dmamap);
+ bus_dma_tag_destroy(slot->dmatag);
SDHCI_LOCK_DESTROY(slot);
- continue;
+ return (ENXIO);
+ } else if ((caps & SDHCI_SLOTTYPE_MASK) ==
+ SDHCI_SLOTTYPE_EMBEDDED) {
+ slot->opt |= SDHCI_SLOT_EMBEDDED | SDHCI_NON_REMOVABLE;
}
- /* Allocate DMA tag. */
- err = bus_dma_tag_create(bus_get_dma_tag(dev),
- DMA_BLOCK_SIZE, 0, BUS_SPACE_MAXADDR_32BIT,
- BUS_SPACE_MAXADDR, NULL, NULL,
- DMA_BLOCK_SIZE, 1, DMA_BLOCK_SIZE,
- BUS_DMA_ALLOCNOW, NULL, NULL,
- &slot->dmatag);
- if (err != 0) {
- device_printf(dev, "Can't create DMA tag\n");
- SDHCI_LOCK_DESTROY(slot);
- continue;
- }
- /* Allocate DMA memory. */
- err = bus_dmamem_alloc(slot->dmatag, (void **)&slot->dmamem,
- BUS_DMA_NOWAIT, &slot->dmamap);
- if (err != 0) {
- device_printf(dev, "Can't alloc DMA memory\n");
- SDHCI_LOCK_DESTROY(slot);
- continue;
- }
- /* Map the memory. */
- err = bus_dmamap_load(slot->dmatag, slot->dmamap,
- (void *)slot->dmamem, DMA_BLOCK_SIZE,
- sdhci_getaddr, &slot->paddr, 0);
- if (err != 0 || slot->paddr == 0) {
- device_printf(dev, "Can't load DMA memory\n");
- SDHCI_LOCK_DESTROY(slot);
- continue;
- }
- /* Initialize slot. */
- sdhci_init(slot);
- caps = RD4(slot, SDHCI_CAPABILITIES);
- /* Calculate base clock frequency. */
- slot->max_clk =
- (caps & SDHCI_CLOCK_BASE_MASK) >> SDHCI_CLOCK_BASE_SHIFT;
- if (slot->max_clk == 0) {
- device_printf(dev, "Hardware doesn't specify base clock "
- "frequency.\n");
- }
- slot->max_clk *= 1000000;
- /* Calculate timeout clock frequency. */
- slot->timeout_clk =
- (caps & SDHCI_TIMEOUT_CLK_MASK) >> SDHCI_TIMEOUT_CLK_SHIFT;
- if (slot->timeout_clk == 0) {
- device_printf(dev, "Hardware doesn't specify timeout clock "
- "frequency.\n");
- }
+ }
+ /* Calculate base clock frequency. */
+ if (slot->version >= SDHCI_SPEC_300)
+ freq = (caps & SDHCI_CLOCK_V3_BASE_MASK) >>
+ SDHCI_CLOCK_BASE_SHIFT;
+ else
+ freq = (caps & SDHCI_CLOCK_BASE_MASK) >>
+ SDHCI_CLOCK_BASE_SHIFT;
+ if (freq != 0)
+ slot->max_clk = freq * 1000000;
+ /*
+ * If the frequency wasn't in the capabilities and the hardware driver
+ * hasn't already set max_clk we're probably not going to work right
+ * with an assumption, so complain about it.
+ */
+ if (slot->max_clk == 0) {
+ slot->max_clk = SDHCI_DEFAULT_MAX_FREQ * 1000000;
+ device_printf(dev, "Hardware doesn't specify base clock "
+ "frequency, using %dMHz as default.\n",
+ SDHCI_DEFAULT_MAX_FREQ);
+ }
+ /* Calculate/set timeout clock frequency. */
+ if (slot->quirks & SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK) {
+ slot->timeout_clk = slot->max_clk / 1000;
+ } else if (slot->quirks & SDHCI_QUIRK_DATA_TIMEOUT_1MHZ) {
+ slot->timeout_clk = 1000;
+ } else {
+ slot->timeout_clk = (caps & SDHCI_TIMEOUT_CLK_MASK) >>
+ SDHCI_TIMEOUT_CLK_SHIFT;
if (caps & SDHCI_TIMEOUT_CLK_UNIT)
slot->timeout_clk *= 1000;
+ }
+ /*
+ * If the frequency wasn't in the capabilities and the hardware driver
+ * hasn't already set timeout_clk we'll probably work okay using the
+ * max timeout, but still mention it.
+ */
+ if (slot->timeout_clk == 0) {
+ device_printf(dev, "Hardware doesn't specify timeout clock "
+ "frequency, setting BROKEN_TIMEOUT quirk.\n");
+ slot->quirks |= SDHCI_QUIRK_BROKEN_TIMEOUT_VAL;
+ }
- slot->host.f_min = slot->max_clk / 256;
- slot->host.f_max = slot->max_clk;
- slot->host.host_ocr = 0;
- if (caps & SDHCI_CAN_VDD_330)
- slot->host.host_ocr |= MMC_OCR_320_330 | MMC_OCR_330_340;
- if (caps & SDHCI_CAN_VDD_300)
- slot->host.host_ocr |= MMC_OCR_290_300 | MMC_OCR_300_310;
- if (caps & SDHCI_CAN_VDD_180)
- slot->host.host_ocr |= MMC_OCR_LOW_VOLTAGE;
- if (slot->host.host_ocr == 0) {
- device_printf(dev, "Hardware doesn't report any "
- "support voltages.\n");
- }
- slot->host.caps = MMC_CAP_4_BIT_DATA;
- if (caps & SDHCI_CAN_DO_HISPD)
- slot->host.caps |= MMC_CAP_HSPEED;
- /* Decide if we have usable DMA. */
- if (caps & SDHCI_CAN_DO_DMA)
- slot->opt |= SDHCI_HAVE_DMA;
- if (class == PCIC_BASEPERIPH &&
- subclass == PCIS_BASEPERIPH_SDHC &&
- progif != PCI_SDHCI_IFDMA)
- slot->opt &= ~SDHCI_HAVE_DMA;
- if (sc->quirks & SDHCI_QUIRK_BROKEN_DMA)
- slot->opt &= ~SDHCI_HAVE_DMA;
- if (sc->quirks & SDHCI_QUIRK_FORCE_DMA)
- slot->opt |= SDHCI_HAVE_DMA;
+ slot->host.f_min = SDHCI_MIN_FREQ(slot->bus, slot);
+ slot->host.f_max = slot->max_clk;
+ slot->host.host_ocr = 0;
+ if (caps & SDHCI_CAN_VDD_330)
+ slot->host.host_ocr |= MMC_OCR_320_330 | MMC_OCR_330_340;
+ if (caps & SDHCI_CAN_VDD_300)
+ slot->host.host_ocr |= MMC_OCR_290_300 | MMC_OCR_300_310;
+ /* 1.8V VDD is not supposed to be used for removable cards. */
+ if ((caps & SDHCI_CAN_VDD_180) && (slot->opt & SDHCI_SLOT_EMBEDDED))
+ slot->host.host_ocr |= MMC_OCR_LOW_VOLTAGE;
+ if (slot->host.host_ocr == 0) {
+ device_printf(dev, "Hardware doesn't report any "
+ "support voltages.\n");
+ }
- if (bootverbose || sdhci_debug) {
- slot_printf(slot, "%uMHz%s 4bits%s%s%s %s\n",
- slot->max_clk / 1000000,
- (caps & SDHCI_CAN_DO_HISPD) ? " HS" : "",
- (caps & SDHCI_CAN_VDD_330) ? " 3.3V" : "",
- (caps & SDHCI_CAN_VDD_300) ? " 3.0V" : "",
- (caps & SDHCI_CAN_VDD_180) ? " 1.8V" : "",
- (slot->opt & SDHCI_HAVE_DMA) ? "DMA" : "PIO");
- sdhci_dumpregs(slot);
+ host_caps = MMC_CAP_4_BIT_DATA;
+ if (caps & SDHCI_CAN_DO_8BITBUS)
+ host_caps |= MMC_CAP_8_BIT_DATA;
+ if (caps & SDHCI_CAN_DO_HISPD)
+ host_caps |= MMC_CAP_HSPEED;
+ if (slot->quirks & SDHCI_QUIRK_BOOT_NOACC)
+ host_caps |= MMC_CAP_BOOT_NOACC;
+ if (slot->quirks & SDHCI_QUIRK_WAIT_WHILE_BUSY)
+ host_caps |= MMC_CAP_WAIT_WHILE_BUSY;
+
+ /* Determine supported UHS-I and eMMC modes. */
+ if (caps2 & (SDHCI_CAN_SDR50 | SDHCI_CAN_SDR104 | SDHCI_CAN_DDR50))
+ host_caps |= MMC_CAP_UHS_SDR12 | MMC_CAP_UHS_SDR25;
+ if (caps2 & SDHCI_CAN_SDR104) {
+ host_caps |= MMC_CAP_UHS_SDR104 | MMC_CAP_UHS_SDR50;
+ if (!(slot->quirks & SDHCI_QUIRK_BROKEN_MMC_HS200))
+ host_caps |= MMC_CAP_MMC_HS200;
+ } else if (caps2 & SDHCI_CAN_SDR50)
+ host_caps |= MMC_CAP_UHS_SDR50;
+ if (caps2 & SDHCI_CAN_DDR50 &&
+ !(slot->quirks & SDHCI_QUIRK_BROKEN_UHS_DDR50))
+ host_caps |= MMC_CAP_UHS_DDR50;
+ if (slot->quirks & SDHCI_QUIRK_MMC_DDR52)
+ host_caps |= MMC_CAP_MMC_DDR52;
+ if (slot->quirks & SDHCI_QUIRK_CAPS_BIT63_FOR_MMC_HS400 &&
+ caps2 & SDHCI_CAN_MMC_HS400)
+ host_caps |= MMC_CAP_MMC_HS400;
+
+ /*
+ * Disable UHS-I and eMMC modes if the set_uhs_timing method is the
+ * default NULL implementation.
+ */
+ kobj_desc = &sdhci_set_uhs_timing_desc;
+ kobj_method = kobj_lookup_method(((kobj_t)dev)->ops->cls, NULL,
+ kobj_desc);
+ if (kobj_method == &kobj_desc->deflt)
+ host_caps &= ~(MMC_CAP_UHS_SDR12 | MMC_CAP_UHS_SDR25 |
+ MMC_CAP_UHS_SDR50 | MMC_CAP_UHS_DDR50 | MMC_CAP_UHS_SDR104 |
+ MMC_CAP_MMC_DDR52 | MMC_CAP_MMC_HS200 | MMC_CAP_MMC_HS400);
+
+#define SDHCI_CAP_MODES_TUNING(caps2) \
+ (((caps2) & SDHCI_TUNE_SDR50 ? MMC_CAP_UHS_SDR50 : 0) | \
+ MMC_CAP_UHS_DDR50 | MMC_CAP_UHS_SDR104 | MMC_CAP_MMC_HS200 | \
+ MMC_CAP_MMC_HS400)
+
+ /*
+ * Disable UHS-I and eMMC modes that require (re-)tuning if either
+ * the tune or re-tune method is the default NULL implementation.
+ */
+ kobj_desc = &mmcbr_tune_desc;
+ kobj_method = kobj_lookup_method(((kobj_t)dev)->ops->cls, NULL,
+ kobj_desc);
+ if (kobj_method == &kobj_desc->deflt)
+ goto no_tuning;
+ kobj_desc = &mmcbr_retune_desc;
+ kobj_method = kobj_lookup_method(((kobj_t)dev)->ops->cls, NULL,
+ kobj_desc);
+ if (kobj_method == &kobj_desc->deflt) {
+no_tuning:
+ host_caps &= ~(SDHCI_CAP_MODES_TUNING(caps2));
+ }
+
+ /* Allocate tuning structures and determine tuning parameters. */
+ if (host_caps & SDHCI_CAP_MODES_TUNING(caps2)) {
+ slot->opt |= SDHCI_TUNING_SUPPORTED;
+ slot->tune_req = malloc(sizeof(*slot->tune_req), M_DEVBUF,
+ M_WAITOK);
+ slot->tune_cmd = malloc(sizeof(*slot->tune_cmd), M_DEVBUF,
+ M_WAITOK);
+ slot->tune_data = malloc(sizeof(*slot->tune_data), M_DEVBUF,
+ M_WAITOK);
+ if (caps2 & SDHCI_TUNE_SDR50)
+ slot->opt |= SDHCI_SDR50_NEEDS_TUNING;
+ slot->retune_mode = (caps2 & SDHCI_RETUNE_MODES_MASK) >>
+ SDHCI_RETUNE_MODES_SHIFT;
+ if (slot->retune_mode == SDHCI_RETUNE_MODE_1) {
+ slot->retune_count = (caps2 & SDHCI_RETUNE_CNT_MASK) >>
+ SDHCI_RETUNE_CNT_SHIFT;
+ if (slot->retune_count > 0xb) {
+ device_printf(dev, "Unknown re-tuning count "
+ "%x, using 1 sec\n", slot->retune_count);
+ slot->retune_count = 1;
+ } else if (slot->retune_count != 0)
+ slot->retune_count =
+ 1 << (slot->retune_count - 1);
}
-
- TASK_INIT(&slot->card_task, 0, sdhci_card_task, slot);
- callout_init(&slot->card_callout, 1);
- sc->num_slots++;
}
- device_printf(dev, "%d slot(s) allocated\n", sc->num_slots);
- /* Activate the interrupt */
- err = bus_setup_intr(dev, sc->irq_res, INTR_TYPE_MISC | INTR_MPSAFE,
- NULL, sdhci_intr, sc, &sc->intrhand);
- if (err)
- device_printf(dev, "Can't setup IRQ\n");
- pci_enable_busmaster(dev);
- /* Process cards detection. */
- for (i = 0; i < sc->num_slots; i++) {
- struct sdhci_slot *slot = &sc->slots[i];
- sdhci_card_task(slot, 0);
+#undef SDHCI_CAP_MODES_TUNING
+
+ /* Determine supported VCCQ signaling levels. */
+ host_caps |= MMC_CAP_SIGNALING_330;
+ if (host_caps & (MMC_CAP_UHS_SDR12 | MMC_CAP_UHS_SDR25 |
+ MMC_CAP_UHS_SDR50 | MMC_CAP_UHS_DDR50 | MMC_CAP_UHS_SDR104 |
+ MMC_CAP_MMC_DDR52_180 | MMC_CAP_MMC_HS200_180 |
+ MMC_CAP_MMC_HS400_180))
+ host_caps |= MMC_CAP_SIGNALING_120 | MMC_CAP_SIGNALING_180;
+
+ /*
+ * Disable 1.2 V and 1.8 V signaling if the switch_vccq method is the
+ * default NULL implementation. Disable 1.2 V support if it's the
+ * generic SDHCI implementation.
+ */
+ kobj_desc = &mmcbr_switch_vccq_desc;
+ kobj_method = kobj_lookup_method(((kobj_t)dev)->ops->cls, NULL,
+ kobj_desc);
+ if (kobj_method == &kobj_desc->deflt)
+ host_caps &= ~(MMC_CAP_SIGNALING_120 | MMC_CAP_SIGNALING_180);
+ else if (kobj_method->func == (kobjop_t)sdhci_generic_switch_vccq)
+ host_caps &= ~MMC_CAP_SIGNALING_120;
+
+ /* Determine supported driver types (type B is always mandatory). */
+ if (caps2 & SDHCI_CAN_DRIVE_TYPE_A)
+ host_caps |= MMC_CAP_DRIVER_TYPE_A;
+ if (caps2 & SDHCI_CAN_DRIVE_TYPE_C)
+ host_caps |= MMC_CAP_DRIVER_TYPE_C;
+ if (caps2 & SDHCI_CAN_DRIVE_TYPE_D)
+ host_caps |= MMC_CAP_DRIVER_TYPE_D;
+ slot->host.caps = host_caps;
+
+ /* Decide if we have usable DMA. */
+ if (caps & SDHCI_CAN_DO_DMA)
+ slot->opt |= SDHCI_HAVE_DMA;
+
+ if (slot->quirks & SDHCI_QUIRK_BROKEN_DMA)
+ slot->opt &= ~SDHCI_HAVE_DMA;
+ if (slot->quirks & SDHCI_QUIRK_FORCE_DMA)
+ slot->opt |= SDHCI_HAVE_DMA;
+ if (slot->quirks & SDHCI_QUIRK_ALL_SLOTS_NON_REMOVABLE)
+ slot->opt |= SDHCI_NON_REMOVABLE;
+
+ /*
+ * Use platform-provided transfer backend
+ * with PIO as a fallback mechanism
+ */
+ if (slot->opt & SDHCI_PLATFORM_TRANSFER)
+ slot->opt &= ~SDHCI_HAVE_DMA;
+
+ if (bootverbose || sdhci_debug) {
+ slot_printf(slot,
+ "%uMHz%s %s VDD:%s%s%s VCCQ: 3.3V%s%s DRV: B%s%s%s %s %s\n",
+ slot->max_clk / 1000000,
+ (caps & SDHCI_CAN_DO_HISPD) ? " HS" : "",
+ (host_caps & MMC_CAP_8_BIT_DATA) ? "8bits" :
+ ((host_caps & MMC_CAP_4_BIT_DATA) ? "4bits" : "1bit"),
+ (caps & SDHCI_CAN_VDD_330) ? " 3.3V" : "",
+ (caps & SDHCI_CAN_VDD_300) ? " 3.0V" : "",
+ ((caps & SDHCI_CAN_VDD_180) &&
+ (slot->opt & SDHCI_SLOT_EMBEDDED)) ? " 1.8V" : "",
+ (host_caps & MMC_CAP_SIGNALING_180) ? " 1.8V" : "",
+ (host_caps & MMC_CAP_SIGNALING_120) ? " 1.2V" : "",
+ (host_caps & MMC_CAP_DRIVER_TYPE_A) ? "A" : "",
+ (host_caps & MMC_CAP_DRIVER_TYPE_C) ? "C" : "",
+ (host_caps & MMC_CAP_DRIVER_TYPE_D) ? "D" : "",
+ (slot->opt & SDHCI_HAVE_DMA) ? "DMA" : "PIO",
+ (slot->opt & SDHCI_SLOT_EMBEDDED) ? "embedded" :
+ (slot->opt & SDHCI_NON_REMOVABLE) ? "non-removable" :
+ "removable");
+ if (host_caps & (MMC_CAP_MMC_DDR52 | MMC_CAP_MMC_HS200 |
+ MMC_CAP_MMC_HS400 | MMC_CAP_MMC_ENH_STROBE))
+ slot_printf(slot, "eMMC:%s%s%s%s\n",
+ (host_caps & MMC_CAP_MMC_DDR52) ? " DDR52" : "",
+ (host_caps & MMC_CAP_MMC_HS200) ? " HS200" : "",
+ (host_caps & MMC_CAP_MMC_HS400) ? " HS400" : "",
+ ((host_caps &
+ (MMC_CAP_MMC_HS400 | MMC_CAP_MMC_ENH_STROBE)) ==
+ (MMC_CAP_MMC_HS400 | MMC_CAP_MMC_ENH_STROBE)) ?
+ " HS400ES" : "");
+ if (host_caps & (MMC_CAP_UHS_SDR12 | MMC_CAP_UHS_SDR25 |
+ MMC_CAP_UHS_SDR50 | MMC_CAP_UHS_SDR104))
+ slot_printf(slot, "UHS-I:%s%s%s%s%s\n",
+ (host_caps & MMC_CAP_UHS_SDR12) ? " SDR12" : "",
+ (host_caps & MMC_CAP_UHS_SDR25) ? " SDR25" : "",
+ (host_caps & MMC_CAP_UHS_SDR50) ? " SDR50" : "",
+ (host_caps & MMC_CAP_UHS_SDR104) ? " SDR104" : "",
+ (host_caps & MMC_CAP_UHS_DDR50) ? " DDR50" : "");
+ if (slot->opt & SDHCI_TUNING_SUPPORTED)
+ slot_printf(slot, "Re-tuning count %d secs, mode %d\n",
+ slot->retune_count, slot->retune_mode + 1);
+ sdhci_dumpregs(slot);
}
-
+
+ slot->timeout = 10;
+ SYSCTL_ADD_INT(device_get_sysctl_ctx(slot->bus),
+ SYSCTL_CHILDREN(device_get_sysctl_tree(slot->bus)), OID_AUTO,
+ "timeout", CTLFLAG_RW, &slot->timeout, 0,
+ "Maximum timeout for SDHCI transfers (in secs)");
+ TASK_INIT(&slot->card_task, 0, sdhci_card_task, slot);
+ TIMEOUT_TASK_INIT(taskqueue_swi_giant, &slot->card_delayed_task, 0,
+ sdhci_card_task, slot);
+ callout_init(&slot->card_poll_callout, 1);
+ callout_init_mtx(&slot->timeout_callout, &slot->mtx, 0);
+ callout_init_mtx(&slot->retune_callout, &slot->mtx, 0);
+
+ if ((slot->quirks & SDHCI_QUIRK_POLL_CARD_PRESENT) &&
+ !(slot->opt & SDHCI_NON_REMOVABLE)) {
+ callout_reset(&slot->card_poll_callout,
+ SDHCI_CARD_PRESENT_TICKS, sdhci_card_poll, slot);
+ }
+
+ sdhci_init(slot);
+
return (0);
}
-static int
-sdhci_detach(device_t dev)
+void
+sdhci_start_slot(struct sdhci_slot *slot)
{
- struct sdhci_softc *sc = device_get_softc(dev);
- int i;
- bus_teardown_intr(dev, sc->irq_res, sc->intrhand);
- bus_release_resource(dev, SYS_RES_IRQ,
- sc->irq_rid, sc->irq_res);
+ sdhci_card_task(slot, 0);
+}
- for (i = 0; i < sc->num_slots; i++) {
- struct sdhci_slot *slot = &sc->slots[i];
- device_t d;
+int
+sdhci_cleanup_slot(struct sdhci_slot *slot)
+{
+ device_t d;
- callout_drain(&slot->card_callout);
- taskqueue_drain(taskqueue_swi_giant, &slot->card_task);
+ callout_drain(&slot->timeout_callout);
+ callout_drain(&slot->card_poll_callout);
+ callout_drain(&slot->retune_callout);
+ taskqueue_drain(taskqueue_swi_giant, &slot->card_task);
+ taskqueue_drain_timeout(taskqueue_swi_giant, &slot->card_delayed_task);
- SDHCI_LOCK(slot);
- d = slot->dev;
- slot->dev = NULL;
- SDHCI_UNLOCK(slot);
- if (d != NULL)
- device_delete_child(dev, d);
+ SDHCI_LOCK(slot);
+ d = slot->dev;
+ slot->dev = NULL;
+ SDHCI_UNLOCK(slot);
+ if (d != NULL)
+ device_delete_child(slot->bus, d);
- SDHCI_LOCK(slot);
- sdhci_reset(slot, SDHCI_RESET_ALL);
- SDHCI_UNLOCK(slot);
- bus_dmamap_unload(slot->dmatag, slot->dmamap);
- bus_dmamem_free(slot->dmatag, slot->dmamem, slot->dmamap);
- bus_dma_tag_destroy(slot->dmatag);
- bus_release_resource(dev, SYS_RES_MEMORY,
- slot->mem_rid, slot->mem_res);
- SDHCI_LOCK_DESTROY(slot);
+ SDHCI_LOCK(slot);
+ sdhci_reset(slot, SDHCI_RESET_ALL);
+ SDHCI_UNLOCK(slot);
+ bus_dmamap_unload(slot->dmatag, slot->dmamap);
+ bus_dmamem_free(slot->dmatag, slot->dmamem, slot->dmamap);
+ bus_dma_tag_destroy(slot->dmatag);
+ if (slot->opt & SDHCI_TUNING_SUPPORTED) {
+ free(slot->tune_req, M_DEVBUF);
+ free(slot->tune_cmd, M_DEVBUF);
+ free(slot->tune_data, M_DEVBUF);
}
+
+ SDHCI_LOCK_DESTROY(slot);
+
return (0);
}
-static int
-sdhci_suspend(device_t dev)
+int
+sdhci_generic_suspend(struct sdhci_slot *slot)
{
- struct sdhci_softc *sc = device_get_softc(dev);
- int i, err;
- err = bus_generic_suspend(dev);
- if (err)
- return (err);
- for (i = 0; i < sc->num_slots; i++)
- sdhci_reset(&sc->slots[i], SDHCI_RESET_ALL);
+ /*
+ * We expect the MMC layer to issue initial tuning after resume.
+ * Otherwise, we'd need to indicate re-tuning including circuit reset
+ * being required at least for re-tuning modes 1 and 2 ourselves.
+ */
+ callout_drain(&slot->retune_callout);
+ SDHCI_LOCK(slot);
+ slot->opt &= ~SDHCI_TUNING_ENABLED;
+ sdhci_reset(slot, SDHCI_RESET_ALL);
+ SDHCI_UNLOCK(slot);
+
return (0);
}
-static int
-sdhci_resume(device_t dev)
+int
+sdhci_generic_resume(struct sdhci_slot *slot)
{
- struct sdhci_softc *sc = device_get_softc(dev);
- int i;
- for (i = 0; i < sc->num_slots; i++)
- sdhci_init(&sc->slots[i]);
- return (bus_generic_resume(dev));
+ SDHCI_LOCK(slot);
+ sdhci_init(slot);
+ SDHCI_UNLOCK(slot);
+
+ return (0);
}
-static int
-sdhci_update_ios(device_t brdev, device_t reqdev)
+uint32_t
+sdhci_generic_min_freq(device_t brdev __unused, struct sdhci_slot *slot)
{
+
+ if (slot->version >= SDHCI_SPEC_300)
+ return (slot->max_clk / SDHCI_300_MAX_DIVIDER);
+ else
+ return (slot->max_clk / SDHCI_200_MAX_DIVIDER);
+}
+
+bool
+sdhci_generic_get_card_present(device_t brdev __unused, struct sdhci_slot *slot)
+{
+
+ if (slot->opt & SDHCI_NON_REMOVABLE)
+ return true;
+
+ return (RD4(slot, SDHCI_PRESENT_STATE) & SDHCI_CARD_PRESENT);
+}
+
+void
+sdhci_generic_set_uhs_timing(device_t brdev __unused, struct sdhci_slot *slot)
+{
+ struct mmc_ios *ios;
+ uint16_t hostctrl2;
+
+ if (slot->version < SDHCI_SPEC_300)
+ return;
+
+ SDHCI_ASSERT_LOCKED(slot);
+ ios = &slot->host.ios;
+ sdhci_set_clock(slot, 0);
+ hostctrl2 = RD2(slot, SDHCI_HOST_CONTROL2);
+ hostctrl2 &= ~SDHCI_CTRL2_UHS_MASK;
+ if (ios->clock > SD_SDR50_MAX) {
+ if (ios->timing == bus_timing_mmc_hs400 ||
+ ios->timing == bus_timing_mmc_hs400es)
+ hostctrl2 |= SDHCI_CTRL2_MMC_HS400;
+ else
+ hostctrl2 |= SDHCI_CTRL2_UHS_SDR104;
+ }
+ else if (ios->clock > SD_SDR25_MAX)
+ hostctrl2 |= SDHCI_CTRL2_UHS_SDR50;
+ else if (ios->clock > SD_SDR12_MAX) {
+ if (ios->timing == bus_timing_uhs_ddr50 ||
+ ios->timing == bus_timing_mmc_ddr52)
+ hostctrl2 |= SDHCI_CTRL2_UHS_DDR50;
+ else
+ hostctrl2 |= SDHCI_CTRL2_UHS_SDR25;
+ } else if (ios->clock > SD_MMC_CARD_ID_FREQUENCY)
+ hostctrl2 |= SDHCI_CTRL2_UHS_SDR12;
+ WR2(slot, SDHCI_HOST_CONTROL2, hostctrl2);
+ sdhci_set_clock(slot, ios->clock);
+}
+
+int
+sdhci_generic_update_ios(device_t brdev, device_t reqdev)
+{
struct sdhci_slot *slot = device_get_ivars(reqdev);
struct mmc_ios *ios = &slot->host.ios;
@@ -876,18 +1109,28 @@
}
/* Configure the bus. */
sdhci_set_clock(slot, ios->clock);
- sdhci_set_power(slot, (ios->power_mode == power_off)?0:ios->vdd);
- if (ios->bus_width == bus_width_4)
+ sdhci_set_power(slot, (ios->power_mode == power_off) ? 0 : ios->vdd);
+ if (ios->bus_width == bus_width_8) {
+ slot->hostctrl |= SDHCI_CTRL_8BITBUS;
+ slot->hostctrl &= ~SDHCI_CTRL_4BITBUS;
+ } else if (ios->bus_width == bus_width_4) {
+ slot->hostctrl &= ~SDHCI_CTRL_8BITBUS;
slot->hostctrl |= SDHCI_CTRL_4BITBUS;
- else
+ } else if (ios->bus_width == bus_width_1) {
+ slot->hostctrl &= ~SDHCI_CTRL_8BITBUS;
slot->hostctrl &= ~SDHCI_CTRL_4BITBUS;
- if (ios->timing == bus_timing_hs)
+ } else {
+ panic("Invalid bus width: %d", ios->bus_width);
+ }
+ if (ios->clock > SD_SDR12_MAX &&
+ !(slot->quirks & SDHCI_QUIRK_DONT_SET_HISPD_BIT))
slot->hostctrl |= SDHCI_CTRL_HISPD;
else
slot->hostctrl &= ~SDHCI_CTRL_HISPD;
WR1(slot, SDHCI_HOST_CONTROL, slot->hostctrl);
+ SDHCI_SET_UHS_TIMING(brdev, slot);
/* Some controllers like reset after bus changes. */
- if(slot->sc->quirks & SDHCI_QUIRK_RESET_ON_IOS)
+ if (slot->quirks & SDHCI_QUIRK_RESET_ON_IOS)
sdhci_reset(slot, SDHCI_RESET_CMD | SDHCI_RESET_DATA);
SDHCI_UNLOCK(slot);
@@ -894,10 +1137,298 @@
return (0);
}
+int
+sdhci_generic_switch_vccq(device_t brdev __unused, device_t reqdev)
+{
+ struct sdhci_slot *slot = device_get_ivars(reqdev);
+ enum mmc_vccq vccq;
+ int err;
+ uint16_t hostctrl2;
+
+ if (slot->version < SDHCI_SPEC_300)
+ return (0);
+
+ err = 0;
+ vccq = slot->host.ios.vccq;
+ SDHCI_LOCK(slot);
+ sdhci_set_clock(slot, 0);
+ hostctrl2 = RD2(slot, SDHCI_HOST_CONTROL2);
+ switch (vccq) {
+ case vccq_330:
+ if (!(hostctrl2 & SDHCI_CTRL2_S18_ENABLE))
+ goto done;
+ hostctrl2 &= ~SDHCI_CTRL2_S18_ENABLE;
+ WR2(slot, SDHCI_HOST_CONTROL2, hostctrl2);
+ DELAY(5000);
+ hostctrl2 = RD2(slot, SDHCI_HOST_CONTROL2);
+ if (!(hostctrl2 & SDHCI_CTRL2_S18_ENABLE))
+ goto done;
+ err = EAGAIN;
+ break;
+ case vccq_180:
+ if (!(slot->host.caps & MMC_CAP_SIGNALING_180)) {
+ err = EINVAL;
+ goto done;
+ }
+ if (hostctrl2 & SDHCI_CTRL2_S18_ENABLE)
+ goto done;
+ hostctrl2 |= SDHCI_CTRL2_S18_ENABLE;
+ WR2(slot, SDHCI_HOST_CONTROL2, hostctrl2);
+ DELAY(5000);
+ hostctrl2 = RD2(slot, SDHCI_HOST_CONTROL2);
+ if (hostctrl2 & SDHCI_CTRL2_S18_ENABLE)
+ goto done;
+ err = EAGAIN;
+ break;
+ default:
+ slot_printf(slot,
+ "Attempt to set unsupported signaling voltage\n");
+ err = EINVAL;
+ break;
+ }
+done:
+ sdhci_set_clock(slot, slot->host.ios.clock);
+ SDHCI_UNLOCK(slot);
+ return (err);
+}
+
+int
+sdhci_generic_tune(device_t brdev __unused, device_t reqdev, bool hs400)
+{
+ struct sdhci_slot *slot = device_get_ivars(reqdev);
+ struct mmc_ios *ios = &slot->host.ios;
+ struct mmc_command *tune_cmd;
+ struct mmc_data *tune_data;
+ uint32_t opcode;
+ int err;
+
+ if (!(slot->opt & SDHCI_TUNING_SUPPORTED))
+ return (0);
+
+ slot->retune_ticks = slot->retune_count * hz;
+ opcode = MMC_SEND_TUNING_BLOCK;
+ SDHCI_LOCK(slot);
+ switch (ios->timing) {
+ case bus_timing_mmc_hs400:
+ slot_printf(slot, "HS400 must be tuned in HS200 mode\n");
+ SDHCI_UNLOCK(slot);
+ return (EINVAL);
+ case bus_timing_mmc_hs200:
+ /*
+ * In HS400 mode, controllers use the data strobe line to
+ * latch data from the devices so periodic re-tuning isn't
+ * expected to be required.
+ */
+ if (hs400)
+ slot->retune_ticks = 0;
+ opcode = MMC_SEND_TUNING_BLOCK_HS200;
+ break;
+ case bus_timing_uhs_ddr50:
+ case bus_timing_uhs_sdr104:
+ break;
+ case bus_timing_uhs_sdr50:
+ if (slot->opt & SDHCI_SDR50_NEEDS_TUNING)
+ break;
+ /* FALLTHROUGH */
+ default:
+ SDHCI_UNLOCK(slot);
+ return (0);
+ }
+
+ tune_cmd = slot->tune_cmd;
+ memset(tune_cmd, 0, sizeof(*tune_cmd));
+ tune_cmd->opcode = opcode;
+ tune_cmd->flags = MMC_RSP_R1 | MMC_CMD_ADTC;
+ tune_data = tune_cmd->data = slot->tune_data;
+ memset(tune_data, 0, sizeof(*tune_data));
+ tune_data->len = (opcode == MMC_SEND_TUNING_BLOCK_HS200 &&
+ ios->bus_width == bus_width_8) ? MMC_TUNING_LEN_HS200 :
+ MMC_TUNING_LEN;
+ tune_data->flags = MMC_DATA_READ;
+ tune_data->mrq = tune_cmd->mrq = slot->tune_req;
+
+ slot->opt &= ~SDHCI_TUNING_ENABLED;
+ err = sdhci_exec_tuning(slot, true);
+ if (err == 0) {
+ slot->opt |= SDHCI_TUNING_ENABLED;
+ slot->intmask |= sdhci_tuning_intmask(slot);
+ WR4(slot, SDHCI_INT_ENABLE, slot->intmask);
+ WR4(slot, SDHCI_SIGNAL_ENABLE, slot->intmask);
+ if (slot->retune_ticks) {
+ callout_reset(&slot->retune_callout, slot->retune_ticks,
+ sdhci_retune, slot);
+ }
+ }
+ SDHCI_UNLOCK(slot);
+ return (err);
+}
+
+int
+sdhci_generic_retune(device_t brdev __unused, device_t reqdev, bool reset)
+{
+ struct sdhci_slot *slot = device_get_ivars(reqdev);
+ int err;
+
+ if (!(slot->opt & SDHCI_TUNING_ENABLED))
+ return (0);
+
+ /* HS400 must be tuned in HS200 mode. */
+ if (slot->host.ios.timing == bus_timing_mmc_hs400)
+ return (EINVAL);
+
+ SDHCI_LOCK(slot);
+ err = sdhci_exec_tuning(slot, reset);
+ /*
+ * There are two ways sdhci_exec_tuning() can fail:
+ * EBUSY should not actually happen when requests are only issued
+ * with the host properly acquired, and
+ * EIO re-tuning failed (but it did work initially).
+ *
+ * In both cases, we should retry at later point if periodic re-tuning
+ * is enabled. Note that due to slot->retune_req not being cleared in
+ * these failure cases, the MMC layer should trigger another attempt at
+ * re-tuning with the next request anyway, though.
+ */
+ if (slot->retune_ticks) {
+ callout_reset(&slot->retune_callout, slot->retune_ticks,
+ sdhci_retune, slot);
+ }
+ SDHCI_UNLOCK(slot);
+ return (err);
+}
+
+static int
+sdhci_exec_tuning(struct sdhci_slot *slot, bool reset)
+{
+ struct mmc_request *tune_req;
+ struct mmc_command *tune_cmd;
+ int i;
+ uint32_t intmask;
+ uint16_t hostctrl2;
+ u_char opt;
+
+ SDHCI_ASSERT_LOCKED(slot);
+ if (slot->req != NULL)
+ return (EBUSY);
+
+ /* Tuning doesn't work with DMA enabled. */
+ opt = slot->opt;
+ slot->opt = opt & ~SDHCI_HAVE_DMA;
+
+ /*
+ * Ensure that as documented, SDHCI_INT_DATA_AVAIL is the only
+ * kind of interrupt we receive in response to a tuning request.
+ */
+ intmask = slot->intmask;
+ slot->intmask = SDHCI_INT_DATA_AVAIL;
+ WR4(slot, SDHCI_INT_ENABLE, SDHCI_INT_DATA_AVAIL);
+ WR4(slot, SDHCI_SIGNAL_ENABLE, SDHCI_INT_DATA_AVAIL);
+
+ hostctrl2 = RD2(slot, SDHCI_HOST_CONTROL2);
+ if (reset)
+ hostctrl2 &= ~SDHCI_CTRL2_SAMPLING_CLOCK;
+ else
+ hostctrl2 |= SDHCI_CTRL2_SAMPLING_CLOCK;
+ WR2(slot, SDHCI_HOST_CONTROL2, hostctrl2 | SDHCI_CTRL2_EXEC_TUNING);
+
+ tune_req = slot->tune_req;
+ tune_cmd = slot->tune_cmd;
+ for (i = 0; i < MMC_TUNING_MAX; i++) {
+ memset(tune_req, 0, sizeof(*tune_req));
+ tune_req->cmd = tune_cmd;
+ tune_req->done = sdhci_req_wakeup;
+ tune_req->done_data = slot;
+ slot->req = tune_req;
+ slot->flags = 0;
+ sdhci_start(slot);
+ while (!(tune_req->flags & MMC_REQ_DONE))
+ msleep(tune_req, &slot->mtx, 0, "sdhciet", 0);
+ if (!(tune_req->flags & MMC_TUNE_DONE))
+ break;
+ hostctrl2 = RD2(slot, SDHCI_HOST_CONTROL2);
+ if (!(hostctrl2 & SDHCI_CTRL2_EXEC_TUNING))
+ break;
+ if (tune_cmd->opcode == MMC_SEND_TUNING_BLOCK)
+ DELAY(1000);
+ }
+
+ /*
+ * Restore DMA usage and interrupts.
+ * Note that the interrupt aggregation code might have cleared
+ * SDHCI_INT_DMA_END and/or SDHCI_INT_RESPONSE in slot->intmask
+ * and SDHCI_SIGNAL_ENABLE respectively so ensure SDHCI_INT_ENABLE
+ * doesn't lose these.
+ */
+ slot->opt = opt;
+ slot->intmask = intmask;
+ WR4(slot, SDHCI_INT_ENABLE, intmask | SDHCI_INT_DMA_END |
+ SDHCI_INT_RESPONSE);
+ WR4(slot, SDHCI_SIGNAL_ENABLE, intmask);
+
+ if ((hostctrl2 & (SDHCI_CTRL2_EXEC_TUNING |
+ SDHCI_CTRL2_SAMPLING_CLOCK)) == SDHCI_CTRL2_SAMPLING_CLOCK) {
+ slot->retune_req = 0;
+ return (0);
+ }
+
+ slot_printf(slot, "Tuning failed, using fixed sampling clock\n");
+ WR2(slot, SDHCI_HOST_CONTROL2, hostctrl2 & ~(SDHCI_CTRL2_EXEC_TUNING |
+ SDHCI_CTRL2_SAMPLING_CLOCK));
+ sdhci_reset(slot, SDHCI_RESET_CMD | SDHCI_RESET_DATA);
+ return (EIO);
+}
+
static void
-sdhci_set_transfer_mode(struct sdhci_slot *slot,
- struct mmc_data *data)
+sdhci_retune(void *arg)
{
+ struct sdhci_slot *slot = arg;
+
+ slot->retune_req |= SDHCI_RETUNE_REQ_NEEDED;
+}
+
+static void
+sdhci_req_done(struct sdhci_slot *slot)
+{
+ struct mmc_request *req;
+
+ if (slot->req != NULL && slot->curcmd != NULL) {
+ callout_stop(&slot->timeout_callout);
+ req = slot->req;
+ slot->req = NULL;
+ slot->curcmd = NULL;
+ req->done(req);
+ }
+}
+
+static void
+sdhci_req_wakeup(struct mmc_request *req)
+{
+ struct sdhci_slot *slot;
+
+ slot = req->done_data;
+ req->flags |= MMC_REQ_DONE;
+ wakeup(req);
+}
+
+static void
+sdhci_timeout(void *arg)
+{
+ struct sdhci_slot *slot = arg;
+
+ if (slot->curcmd != NULL) {
+ slot_printf(slot, "Controller timeout\n");
+ sdhci_dumpregs(slot);
+ sdhci_reset(slot, SDHCI_RESET_CMD | SDHCI_RESET_DATA);
+ slot->curcmd->error = MMC_ERR_TIMEOUT;
+ sdhci_req_done(slot);
+ } else {
+ slot_printf(slot, "Spurious timeout - no active command\n");
+ }
+}
+
+static void
+sdhci_set_transfer_mode(struct sdhci_slot *slot, struct mmc_data *data)
+{
uint16_t mode;
if (data == NULL)
@@ -919,9 +1450,8 @@
static void
sdhci_start_command(struct sdhci_slot *slot, struct mmc_command *cmd)
{
- struct mmc_request *req = slot->req;
int flags, timeout;
- uint32_t mask, state;
+ uint32_t mask;
slot->curcmd = cmd;
slot->cmd_done = 0;
@@ -932,23 +1462,19 @@
if ((cmd->flags & MMC_RSP_136) && (cmd->flags & MMC_RSP_BUSY)) {
slot_printf(slot, "Unsupported response type!\n");
cmd->error = MMC_ERR_FAILED;
- slot->req = NULL;
- slot->curcmd = NULL;
- req->done(req);
+ sdhci_req_done(slot);
return;
}
- /* Read controller present state. */
- state = RD4(slot, SDHCI_PRESENT_STATE);
- /* Do not issue command if there is no card, clock or power.
- * Controller will not detect timeout without clock active. */
- if ((state & SDHCI_CARD_PRESENT) == 0 ||
+ /*
+ * Do not issue command if there is no card, clock or power.
+ * Controller will not detect timeout without clock active.
+ */
+ if (!SDHCI_GET_CARD_PRESENT(slot->bus, slot) ||
slot->power == 0 ||
slot->clock == 0) {
cmd->error = MMC_ERR_FAILED;
- slot->req = NULL;
- slot->curcmd = NULL;
- req->done(req);
+ sdhci_req_done(slot);
return;
}
/* Always wait for free CMD bus. */
@@ -956,25 +1482,37 @@
/* Wait for free DAT if we have data or busy signal. */
if (cmd->data || (cmd->flags & MMC_RSP_BUSY))
mask |= SDHCI_DAT_INHIBIT;
- /* We shouldn't wait for DAT for stop commands. */
- if (cmd == slot->req->stop)
+ /*
+ * We shouldn't wait for DAT for stop commands or CMD19/CMD21. Note
+ * that these latter are also special in that SDHCI_CMD_DATA should
+ * be set below but no actual data is ever read from the controller.
+ */
+ if (cmd == slot->req->stop ||
+ __predict_false(cmd->opcode == MMC_SEND_TUNING_BLOCK ||
+ cmd->opcode == MMC_SEND_TUNING_BLOCK_HS200))
mask &= ~SDHCI_DAT_INHIBIT;
- /* Wait for bus no more then 10 ms. */
- timeout = 10;
- while (state & mask) {
+ /*
+ * Wait for bus no more then 250 ms. Typically there will be no wait
+ * here at all, but when writing a crash dump we may be bypassing the
+ * host platform's interrupt handler, and in some cases that handler
+ * may be working around hardware quirks such as not respecting r1b
+ * busy indications. In those cases, this wait-loop serves the purpose
+ * of waiting for the prior command and data transfers to be done, and
+ * SD cards are allowed to take up to 250ms for write and erase ops.
+ * (It's usually more like 20-30ms in the real world.)
+ */
+ timeout = 250;
+ while (mask & RD4(slot, SDHCI_PRESENT_STATE)) {
if (timeout == 0) {
slot_printf(slot, "Controller never released "
"inhibit bit(s).\n");
sdhci_dumpregs(slot);
cmd->error = MMC_ERR_FAILED;
- slot->req = NULL;
- slot->curcmd = NULL;
- req->done(req);
+ sdhci_req_done(slot);
return;
}
timeout--;
DELAY(1000);
- state = RD4(slot, SDHCI_PRESENT_STATE);
}
/* Prepare command flags. */
@@ -996,7 +1534,7 @@
flags |= SDHCI_CMD_TYPE_ABORT;
/* Prepare data. */
sdhci_start_data(slot, cmd->data);
- /*
+ /*
* Interrupt aggregation: To reduce total number of interrupts
* group response interrupt with data interrupt when possible.
* If there going to be data interrupt, mask response one.
@@ -1009,10 +1547,11 @@
WR4(slot, SDHCI_ARGUMENT, cmd->arg);
/* Set data transfer mode. */
sdhci_set_transfer_mode(slot, cmd->data);
- /* Set command flags. */
- WR1(slot, SDHCI_COMMAND_FLAGS, flags);
/* Start command. */
- WR1(slot, SDHCI_COMMAND, cmd->opcode);
+ WR2(slot, SDHCI_COMMAND_FLAGS, (cmd->opcode << 8) | (flags & 0xff));
+ /* Start timeout callout. */
+ callout_reset(&slot->timeout_callout, slot->timeout * hz,
+ sdhci_timeout, slot);
}
static void
@@ -1019,14 +1558,23 @@
sdhci_finish_command(struct sdhci_slot *slot)
{
int i;
+ uint32_t val;
+ uint8_t extra;
slot->cmd_done = 1;
- /* Interrupt aggregation: Restore command interrupt.
+ /*
+ * Interrupt aggregation: Restore command interrupt.
* Main restore point for the case when command interrupt
- * happened first. */
- WR4(slot, SDHCI_SIGNAL_ENABLE, slot->intmask |= SDHCI_INT_RESPONSE);
+ * happened first.
+ */
+ if (__predict_true(slot->curcmd->opcode != MMC_SEND_TUNING_BLOCK &&
+ slot->curcmd->opcode != MMC_SEND_TUNING_BLOCK_HS200))
+ WR4(slot, SDHCI_SIGNAL_ENABLE, slot->intmask |=
+ SDHCI_INT_RESPONSE);
/* In case of error - reset host and return. */
if (slot->curcmd->error) {
+ if (slot->curcmd->error == MMC_ERR_BADCRC)
+ slot->retune_req |= SDHCI_RETUNE_REQ_RESET;
sdhci_reset(slot, SDHCI_RESET_CMD);
sdhci_reset(slot, SDHCI_RESET_DATA);
sdhci_start(slot);
@@ -1036,11 +1584,17 @@
if (slot->curcmd->flags & MMC_RSP_PRESENT) {
if (slot->curcmd->flags & MMC_RSP_136) {
/* CRC is stripped so we need one byte shift. */
- uint8_t extra = 0;
+ extra = 0;
for (i = 0; i < 4; i++) {
- uint32_t val = RD4(slot, SDHCI_RESPONSE + i * 4);
- slot->curcmd->resp[3 - i] = (val << 8) + extra;
- extra = val >> 24;
+ val = RD4(slot, SDHCI_RESPONSE + i * 4);
+ if (slot->quirks &
+ SDHCI_QUIRK_DONT_SHIFT_RESPONSE)
+ slot->curcmd->resp[3 - i] = val;
+ else {
+ slot->curcmd->resp[3 - i] =
+ (val << 8) | extra;
+ extra = val >> 24;
+ }
}
} else
slot->curcmd->resp[0] = RD4(slot, SDHCI_RESPONSE);
@@ -1065,21 +1619,21 @@
/* Calculate and set data timeout.*/
/* XXX: We should have this from mmc layer, now assume 1 sec. */
- target_timeout = 1000000;
- div = 0;
- current_timeout = (1 << 13) * 1000 / slot->timeout_clk;
- while (current_timeout < target_timeout) {
- div++;
- current_timeout <<= 1;
- if (div >= 0xF)
- break;
- }
- /* Compensate for an off-by-one error in the CaFe chip.*/
- if (slot->sc->quirks & SDHCI_QUIRK_INCR_TIMEOUT_CONTROL)
- div++;
- if (div >= 0xF) {
- slot_printf(slot, "Timeout too large!\n");
+ if (slot->quirks & SDHCI_QUIRK_BROKEN_TIMEOUT_VAL) {
div = 0xE;
+ } else {
+ target_timeout = 1000000;
+ div = 0;
+ current_timeout = (1 << 13) * 1000 / slot->timeout_clk;
+ while (current_timeout < target_timeout && div < 0xE) {
+ ++div;
+ current_timeout <<= 1;
+ }
+ /* Compensate for an off-by-one error in the CaFe chip.*/
+ if (div < 0xE &&
+ (slot->quirks & SDHCI_QUIRK_INCR_TIMEOUT_CONTROL)) {
+ ++div;
+ }
}
WR1(slot, SDHCI_TIMEOUT_CONTROL, div);
@@ -1090,21 +1644,24 @@
if ((slot->opt & SDHCI_HAVE_DMA))
slot->flags |= SDHCI_USE_DMA;
/* If data is small, broken DMA may return zeroes instead of data, */
- if ((slot->sc->quirks & SDHCI_QUIRK_BROKEN_TIMINGS) &&
+ if ((slot->quirks & SDHCI_QUIRK_BROKEN_TIMINGS) &&
(data->len <= 512))
slot->flags &= ~SDHCI_USE_DMA;
/* Some controllers require even block sizes. */
- if ((slot->sc->quirks & SDHCI_QUIRK_32BIT_DMA_SIZE) &&
+ if ((slot->quirks & SDHCI_QUIRK_32BIT_DMA_SIZE) &&
((data->len) & 0x3))
slot->flags &= ~SDHCI_USE_DMA;
/* Load DMA buffer. */
if (slot->flags & SDHCI_USE_DMA) {
if (data->flags & MMC_DATA_READ)
- bus_dmamap_sync(slot->dmatag, slot->dmamap, BUS_DMASYNC_PREREAD);
+ bus_dmamap_sync(slot->dmatag, slot->dmamap,
+ BUS_DMASYNC_PREREAD);
else {
memcpy(slot->dmamem, data->data,
- (data->len < DMA_BLOCK_SIZE)?data->len:DMA_BLOCK_SIZE);
- bus_dmamap_sync(slot->dmatag, slot->dmamap, BUS_DMASYNC_PREWRITE);
+ (data->len < DMA_BLOCK_SIZE) ?
+ data->len : DMA_BLOCK_SIZE);
+ bus_dmamap_sync(slot->dmatag, slot->dmamap,
+ BUS_DMASYNC_PREWRITE);
}
WR4(slot, SDHCI_DMA_ADDRESS, slot->paddr);
/* Interrupt aggregation: Mask border interrupt
@@ -1118,20 +1675,20 @@
/* Current data offset for both PIO and DMA. */
slot->offset = 0;
/* Set block size and request IRQ on 4K border. */
- WR2(slot, SDHCI_BLOCK_SIZE,
- SDHCI_MAKE_BLKSZ(DMA_BOUNDARY, (data->len < 512)?data->len:512));
+ WR2(slot, SDHCI_BLOCK_SIZE, SDHCI_MAKE_BLKSZ(DMA_BOUNDARY,
+ (data->len < 512) ? data->len : 512));
/* Set block count. */
WR2(slot, SDHCI_BLOCK_COUNT, (data->len + 511) / 512);
}
-static void
+void
sdhci_finish_data(struct sdhci_slot *slot)
{
struct mmc_data *data = slot->curcmd->data;
+ size_t left;
- slot->data_done = 1;
/* Interrupt aggregation: Restore command interrupt.
- * Auxillary restore point for the case when data interrupt
+ * Auxiliary restore point for the case when data interrupt
* happened first. */
if (!slot->cmd_done) {
WR4(slot, SDHCI_SIGNAL_ENABLE,
@@ -1138,17 +1695,22 @@
slot->intmask |= SDHCI_INT_RESPONSE);
}
/* Unload rest of data from DMA buffer. */
- if (slot->flags & SDHCI_USE_DMA) {
+ if (!slot->data_done && (slot->flags & SDHCI_USE_DMA)) {
if (data->flags & MMC_DATA_READ) {
- size_t left = data->len - slot->offset;
- bus_dmamap_sync(slot->dmatag, slot->dmamap, BUS_DMASYNC_POSTREAD);
+ left = data->len - slot->offset;
+ bus_dmamap_sync(slot->dmatag, slot->dmamap,
+ BUS_DMASYNC_POSTREAD);
memcpy((u_char*)data->data + slot->offset, slot->dmamem,
- (left < DMA_BLOCK_SIZE)?left:DMA_BLOCK_SIZE);
+ (left < DMA_BLOCK_SIZE) ? left : DMA_BLOCK_SIZE);
} else
- bus_dmamap_sync(slot->dmatag, slot->dmamap, BUS_DMASYNC_POSTWRITE);
+ bus_dmamap_sync(slot->dmatag, slot->dmamap,
+ BUS_DMASYNC_POSTWRITE);
}
+ slot->data_done = 1;
/* If there was error - reset the host. */
if (slot->curcmd->error) {
+ if (slot->curcmd->error == MMC_ERR_BADCRC)
+ slot->retune_req |= SDHCI_RETUNE_REQ_RESET;
sdhci_reset(slot, SDHCI_RESET_CMD);
sdhci_reset(slot, SDHCI_RESET_DATA);
sdhci_start(slot);
@@ -1180,22 +1742,20 @@
return;
}
*/
- if (sdhci_debug > 1)
+ if (__predict_false(sdhci_debug > 1))
slot_printf(slot, "result: %d\n", req->cmd->error);
if (!req->cmd->error &&
- (slot->sc->quirks & SDHCI_QUIRK_RESET_AFTER_REQUEST)) {
+ (slot->quirks & SDHCI_QUIRK_RESET_AFTER_REQUEST)) {
sdhci_reset(slot, SDHCI_RESET_CMD);
sdhci_reset(slot, SDHCI_RESET_DATA);
}
- /* We must be done -- bad idea to do this while locked? */
- slot->req = NULL;
- slot->curcmd = NULL;
- req->done(req);
+ sdhci_req_done(slot);
}
-static int
-sdhci_request(device_t brdev, device_t reqdev, struct mmc_request *req)
+int
+sdhci_generic_request(device_t brdev __unused, device_t reqdev,
+ struct mmc_request *req)
{
struct sdhci_slot *slot = device_get_ivars(reqdev);
@@ -1204,10 +1764,11 @@
SDHCI_UNLOCK(slot);
return (EBUSY);
}
- if (sdhci_debug > 1) {
- slot_printf(slot, "CMD%u arg %#x flags %#x dlen %u dflags %#x\n",
- req->cmd->opcode, req->cmd->arg, req->cmd->flags,
- (req->cmd->data)?(u_int)req->cmd->data->len:0,
+ if (__predict_false(sdhci_debug > 1)) {
+ slot_printf(slot,
+ "CMD%u arg %#x flags %#x dlen %u dflags %#x\n",
+ req->cmd->opcode, req->cmd->arg, req->cmd->flags,
+ (req->cmd->data)?(u_int)req->cmd->data->len:0,
(req->cmd->data)?req->cmd->data->flags:0);
}
slot->req = req;
@@ -1216,7 +1777,7 @@
SDHCI_UNLOCK(slot);
if (dumping) {
while (slot->req != NULL) {
- sdhci_intr(slot->sc);
+ sdhci_generic_intr(slot);
DELAY(10);
}
}
@@ -1223,8 +1784,8 @@
return (0);
}
-static int
-sdhci_get_ro(device_t brdev, device_t reqdev)
+int
+sdhci_generic_get_ro(device_t brdev __unused, device_t reqdev)
{
struct sdhci_slot *slot = device_get_ivars(reqdev);
uint32_t val;
@@ -1235,8 +1796,8 @@
return (!(val & SDHCI_WRITE_PROTECT));
}
-static int
-sdhci_acquire_host(device_t brdev, device_t reqdev)
+int
+sdhci_generic_acquire_host(device_t brdev __unused, device_t reqdev)
{
struct sdhci_slot *slot = device_get_ivars(reqdev);
int err = 0;
@@ -1251,8 +1812,8 @@
return (err);
}
-static int
-sdhci_release_host(device_t brdev, device_t reqdev)
+int
+sdhci_generic_release_host(device_t brdev __unused, device_t reqdev)
{
struct sdhci_slot *slot = device_get_ivars(reqdev);
@@ -1288,6 +1849,8 @@
static void
sdhci_data_irq(struct sdhci_slot *slot, uint32_t intmask)
{
+ struct mmc_data *data;
+ size_t left;
if (!slot->curcmd) {
slot_printf(slot, "Got data interrupt 0x%08x, but "
@@ -1317,25 +1880,39 @@
}
if (slot->curcmd->error) {
/* No need to continue after any error. */
+ goto done;
+ }
+
+ /* Handle tuning completion interrupt. */
+ if (__predict_false((intmask & SDHCI_INT_DATA_AVAIL) &&
+ (slot->curcmd->opcode == MMC_SEND_TUNING_BLOCK ||
+ slot->curcmd->opcode == MMC_SEND_TUNING_BLOCK_HS200))) {
+ slot->req->flags |= MMC_TUNE_DONE;
+ sdhci_finish_command(slot);
sdhci_finish_data(slot);
return;
}
-
/* Handle PIO interrupt. */
- if (intmask & (SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL))
- sdhci_transfer_pio(slot);
+ if (intmask & (SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL)) {
+ if ((slot->opt & SDHCI_PLATFORM_TRANSFER) &&
+ SDHCI_PLATFORM_WILL_HANDLE(slot->bus, slot)) {
+ SDHCI_PLATFORM_START_TRANSFER(slot->bus, slot,
+ &intmask);
+ slot->flags |= PLATFORM_DATA_STARTED;
+ } else
+ sdhci_transfer_pio(slot);
+ }
/* Handle DMA border. */
if (intmask & SDHCI_INT_DMA_END) {
- struct mmc_data *data = slot->curcmd->data;
- size_t left;
+ data = slot->curcmd->data;
- /* Unload DMA buffer... */
+ /* Unload DMA buffer ... */
left = data->len - slot->offset;
if (data->flags & MMC_DATA_READ) {
bus_dmamap_sync(slot->dmatag, slot->dmamap,
BUS_DMASYNC_POSTREAD);
memcpy((u_char*)data->data + slot->offset, slot->dmamem,
- (left < DMA_BLOCK_SIZE)?left:DMA_BLOCK_SIZE);
+ (left < DMA_BLOCK_SIZE) ? left : DMA_BLOCK_SIZE);
} else {
bus_dmamap_sync(slot->dmatag, slot->dmamap,
BUS_DMASYNC_POSTWRITE);
@@ -1348,7 +1925,7 @@
BUS_DMASYNC_PREREAD);
} else {
memcpy(slot->dmamem, (u_char*)data->data + slot->offset,
- (left < DMA_BLOCK_SIZE)?left:DMA_BLOCK_SIZE);
+ (left < DMA_BLOCK_SIZE)? left : DMA_BLOCK_SIZE);
bus_dmamap_sync(slot->dmatag, slot->dmamap,
BUS_DMASYNC_PREWRITE);
}
@@ -1362,8 +1939,21 @@
WR4(slot, SDHCI_DMA_ADDRESS, slot->paddr);
}
/* We have got all data. */
- if (intmask & SDHCI_INT_DATA_END)
- sdhci_finish_data(slot);
+ if (intmask & SDHCI_INT_DATA_END) {
+ if (slot->flags & PLATFORM_DATA_STARTED) {
+ slot->flags &= ~PLATFORM_DATA_STARTED;
+ SDHCI_PLATFORM_FINISH_TRANSFER(slot->bus, slot);
+ } else
+ sdhci_finish_data(slot);
+ }
+done:
+ if (slot->curcmd != NULL && slot->curcmd->error != 0) {
+ if (slot->flags & PLATFORM_DATA_STARTED) {
+ slot->flags &= ~PLATFORM_DATA_STARTED;
+ SDHCI_PLATFORM_FINISH_TRANSFER(slot->bus, slot);
+ } else
+ sdhci_finish_data(slot);
+ }
}
static void
@@ -1370,7 +1960,7 @@
sdhci_acmd_irq(struct sdhci_slot *slot)
{
uint16_t err;
-
+
err = RD4(slot, SDHCI_ACMD12_ERR);
if (!slot->curcmd) {
slot_printf(slot, "Got AutoCMD12 error 0x%04x, but "
@@ -1382,85 +1972,85 @@
sdhci_reset(slot, SDHCI_RESET_CMD);
}
-static void
-sdhci_intr(void *arg)
+void
+sdhci_generic_intr(struct sdhci_slot *slot)
{
- struct sdhci_softc *sc = (struct sdhci_softc *)arg;
- int i;
+ uint32_t intmask, present;
- for (i = 0; i < sc->num_slots; i++) {
- struct sdhci_slot *slot = &sc->slots[i];
- uint32_t intmask;
-
- SDHCI_LOCK(slot);
- /* Read slot interrupt status. */
- intmask = RD4(slot, SDHCI_INT_STATUS);
- if (intmask == 0 || intmask == 0xffffffff) {
- SDHCI_UNLOCK(slot);
- continue;
- }
- if (sdhci_debug > 2)
- slot_printf(slot, "Interrupt %#x\n", intmask);
+ SDHCI_LOCK(slot);
+ /* Read slot interrupt status. */
+ intmask = RD4(slot, SDHCI_INT_STATUS);
+ if (intmask == 0 || intmask == 0xffffffff) {
+ SDHCI_UNLOCK(slot);
+ return;
+ }
+ if (__predict_false(sdhci_debug > 2))
+ slot_printf(slot, "Interrupt %#x\n", intmask);
- /* Handle card presence interrupts. */
- if (intmask & (SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE)) {
- WR4(slot, SDHCI_INT_STATUS, intmask &
- (SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE));
-
- if (intmask & SDHCI_INT_CARD_REMOVE) {
- if (bootverbose || sdhci_debug)
- slot_printf(slot, "Card removed\n");
- callout_stop(&slot->card_callout);
- taskqueue_enqueue(taskqueue_swi_giant,
- &slot->card_task);
- }
- if (intmask & SDHCI_INT_CARD_INSERT) {
- if (bootverbose || sdhci_debug)
- slot_printf(slot, "Card inserted\n");
- callout_reset(&slot->card_callout, hz / 2,
- sdhci_card_delay, slot);
- }
- intmask &= ~(SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE);
+ /* Handle tuning error interrupt. */
+ if (__predict_false(intmask & SDHCI_INT_TUNEERR)) {
+ slot_printf(slot, "Tuning error indicated\n");
+ slot->retune_req |= SDHCI_RETUNE_REQ_RESET;
+ if (slot->curcmd) {
+ slot->curcmd->error = MMC_ERR_BADCRC;
+ sdhci_finish_command(slot);
}
- /* Handle command interrupts. */
- if (intmask & SDHCI_INT_CMD_MASK) {
- WR4(slot, SDHCI_INT_STATUS, intmask & SDHCI_INT_CMD_MASK);
- sdhci_cmd_irq(slot, intmask & SDHCI_INT_CMD_MASK);
- }
- /* Handle data interrupts. */
- if (intmask & SDHCI_INT_DATA_MASK) {
- WR4(slot, SDHCI_INT_STATUS, intmask & SDHCI_INT_DATA_MASK);
+ }
+ /* Handle re-tuning interrupt. */
+ if (__predict_false(intmask & SDHCI_INT_RETUNE))
+ slot->retune_req |= SDHCI_RETUNE_REQ_NEEDED;
+ /* Handle card presence interrupts. */
+ if (intmask & (SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE)) {
+ present = (intmask & SDHCI_INT_CARD_INSERT) != 0;
+ slot->intmask &=
+ ~(SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE);
+ slot->intmask |= present ? SDHCI_INT_CARD_REMOVE :
+ SDHCI_INT_CARD_INSERT;
+ WR4(slot, SDHCI_INT_ENABLE, slot->intmask);
+ WR4(slot, SDHCI_SIGNAL_ENABLE, slot->intmask);
+ WR4(slot, SDHCI_INT_STATUS, intmask &
+ (SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE));
+ sdhci_handle_card_present_locked(slot, present);
+ }
+ /* Handle command interrupts. */
+ if (intmask & SDHCI_INT_CMD_MASK) {
+ WR4(slot, SDHCI_INT_STATUS, intmask & SDHCI_INT_CMD_MASK);
+ sdhci_cmd_irq(slot, intmask & SDHCI_INT_CMD_MASK);
+ }
+ /* Handle data interrupts. */
+ if (intmask & SDHCI_INT_DATA_MASK) {
+ WR4(slot, SDHCI_INT_STATUS, intmask & SDHCI_INT_DATA_MASK);
+ /* Don't call data_irq in case of errored command. */
+ if ((intmask & SDHCI_INT_CMD_ERROR_MASK) == 0)
sdhci_data_irq(slot, intmask & SDHCI_INT_DATA_MASK);
- }
- /* Handle AutoCMD12 error interrupt. */
- if (intmask & SDHCI_INT_ACMD12ERR) {
- WR4(slot, SDHCI_INT_STATUS, SDHCI_INT_ACMD12ERR);
- sdhci_acmd_irq(slot);
- }
- intmask &= ~(SDHCI_INT_CMD_MASK | SDHCI_INT_DATA_MASK);
- intmask &= ~SDHCI_INT_ACMD12ERR;
- intmask &= ~SDHCI_INT_ERROR;
- /* Handle bus power interrupt. */
- if (intmask & SDHCI_INT_BUS_POWER) {
- WR4(slot, SDHCI_INT_STATUS, SDHCI_INT_BUS_POWER);
- slot_printf(slot,
- "Card is consuming too much power!\n");
- intmask &= ~SDHCI_INT_BUS_POWER;
- }
- /* The rest is unknown. */
- if (intmask) {
- WR4(slot, SDHCI_INT_STATUS, intmask);
- slot_printf(slot, "Unexpected interrupt 0x%08x.\n",
- intmask);
- sdhci_dumpregs(slot);
- }
-
- SDHCI_UNLOCK(slot);
}
+ /* Handle AutoCMD12 error interrupt. */
+ if (intmask & SDHCI_INT_ACMD12ERR) {
+ WR4(slot, SDHCI_INT_STATUS, SDHCI_INT_ACMD12ERR);
+ sdhci_acmd_irq(slot);
+ }
+ /* Handle bus power interrupt. */
+ if (intmask & SDHCI_INT_BUS_POWER) {
+ WR4(slot, SDHCI_INT_STATUS, SDHCI_INT_BUS_POWER);
+ slot_printf(slot, "Card is consuming too much power!\n");
+ }
+ intmask &= ~(SDHCI_INT_ERROR | SDHCI_INT_TUNEERR | SDHCI_INT_RETUNE |
+ SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE | SDHCI_INT_CMD_MASK |
+ SDHCI_INT_DATA_MASK | SDHCI_INT_ACMD12ERR | SDHCI_INT_BUS_POWER);
+ /* The rest is unknown. */
+ if (intmask) {
+ WR4(slot, SDHCI_INT_STATUS, intmask);
+ slot_printf(slot, "Unexpected interrupt 0x%08x.\n",
+ intmask);
+ sdhci_dumpregs(slot);
+ }
+
+ SDHCI_UNLOCK(slot);
}
-static int
-sdhci_read_ivar(device_t bus, device_t child, int which, uintptr_t *result)
+int
+sdhci_generic_read_ivar(device_t bus, device_t child, int which,
+ uintptr_t *result)
{
struct sdhci_slot *slot = device_get_ivars(child);
@@ -1500,6 +2090,22 @@
case MMCBR_IVAR_VDD:
*result = slot->host.ios.vdd;
break;
+ case MMCBR_IVAR_RETUNE_REQ:
+ if (slot->opt & SDHCI_TUNING_ENABLED) {
+ if (slot->retune_req & SDHCI_RETUNE_REQ_RESET) {
+ *result = retune_req_reset;
+ break;
+ }
+ if (slot->retune_req & SDHCI_RETUNE_REQ_NEEDED) {
+ *result = retune_req_normal;
+ break;
+ }
+ }
+ *result = retune_req_none;
+ break;
+ case MMCBR_IVAR_VCCQ:
+ *result = slot->host.ios.vccq;
+ break;
case MMCBR_IVAR_CAPS:
*result = slot->host.caps;
break;
@@ -1507,16 +2113,35 @@
*result = slot->host.ios.timing;
break;
case MMCBR_IVAR_MAX_DATA:
+ /*
+ * Re-tuning modes 1 and 2 restrict the maximum data length
+ * per read/write command to 4 MiB.
+ */
+ if (slot->opt & SDHCI_TUNING_ENABLED &&
+ (slot->retune_mode == SDHCI_RETUNE_MODE_1 ||
+ slot->retune_mode == SDHCI_RETUNE_MODE_2)) {
+ *result = 4 * 1024 * 1024 / MMC_SECTOR_SIZE;
+ break;
+ }
*result = 65535;
break;
+ case MMCBR_IVAR_MAX_BUSY_TIMEOUT:
+ /*
+ * Currently, sdhci_start_data() hardcodes 1 s for all CMDs.
+ */
+ *result = 1000000;
+ break;
}
return (0);
}
-static int
-sdhci_write_ivar(device_t bus, device_t child, int which, uintptr_t value)
+int
+sdhci_generic_write_ivar(device_t bus, device_t child, int which,
+ uintptr_t value)
{
struct sdhci_slot *slot = device_get_ivars(child);
+ uint32_t clock, max_clock;
+ int i;
switch (which) {
default:
@@ -1532,14 +2157,25 @@
break;
case MMCBR_IVAR_CLOCK:
if (value > 0) {
- uint32_t clock = slot->max_clk;
- int i;
+ max_clock = slot->max_clk;
+ clock = max_clock;
- for (i = 0; i < 8; i++) {
- if (clock <= value)
- break;
- clock >>= 1;
+ if (slot->version < SDHCI_SPEC_300) {
+ for (i = 0; i < SDHCI_200_MAX_DIVIDER;
+ i <<= 1) {
+ if (clock <= value)
+ break;
+ clock >>= 1;
+ }
+ } else {
+ for (i = 0; i < SDHCI_300_MAX_DIVIDER;
+ i += 2) {
+ if (clock <= value)
+ break;
+ clock = max_clock / (i + 2);
+ }
}
+
slot->host.ios.clock = clock;
} else
slot->host.ios.clock = 0;
@@ -1556,6 +2192,9 @@
case MMCBR_IVAR_VDD:
slot->host.ios.vdd = value;
break;
+ case MMCBR_IVAR_VCCQ:
+ slot->host.ios.vccq = value;
+ break;
case MMCBR_IVAR_TIMING:
slot->host.ios.timing = value;
break;
@@ -1564,39 +2203,10 @@
case MMCBR_IVAR_F_MIN:
case MMCBR_IVAR_F_MAX:
case MMCBR_IVAR_MAX_DATA:
+ case MMCBR_IVAR_RETUNE_REQ:
return (EINVAL);
}
return (0);
}
-static device_method_t sdhci_methods[] = {
- /* device_if */
- DEVMETHOD(device_probe, sdhci_probe),
- DEVMETHOD(device_attach, sdhci_attach),
- DEVMETHOD(device_detach, sdhci_detach),
- DEVMETHOD(device_suspend, sdhci_suspend),
- DEVMETHOD(device_resume, sdhci_resume),
-
- /* Bus interface */
- DEVMETHOD(bus_read_ivar, sdhci_read_ivar),
- DEVMETHOD(bus_write_ivar, sdhci_write_ivar),
-
- /* mmcbr_if */
- DEVMETHOD(mmcbr_update_ios, sdhci_update_ios),
- DEVMETHOD(mmcbr_request, sdhci_request),
- DEVMETHOD(mmcbr_get_ro, sdhci_get_ro),
- DEVMETHOD(mmcbr_acquire_host, sdhci_acquire_host),
- DEVMETHOD(mmcbr_release_host, sdhci_release_host),
-
- {0, 0},
-};
-
-static driver_t sdhci_driver = {
- "sdhci",
- sdhci_methods,
- sizeof(struct sdhci_softc),
-};
-static devclass_t sdhci_devclass;
-
-
-DRIVER_MODULE(sdhci, pci, sdhci_driver, sdhci_devclass, 0, 0);
+MODULE_VERSION(sdhci, 1);
Modified: trunk/sys/dev/sdhci/sdhci.h
===================================================================
--- trunk/sys/dev/sdhci/sdhci.h 2018-05-27 23:14:46 UTC (rev 10072)
+++ trunk/sys/dev/sdhci/sdhci.h 2018-05-27 23:15:22 UTC (rev 10073)
@@ -1,3 +1,4 @@
+/* $MidnightBSD$ */
/*-
* Copyright (c) 2008 Alexander Motin <mav at FreeBSD.org>
* All rights reserved.
@@ -22,178 +23,399 @@
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
- * $MidnightBSD$
+ * $FreeBSD: stable/10/sys/dev/sdhci/sdhci.h 322122 2017-08-06 16:12:56Z marius $
*/
-/*
- * PCI registers
- */
+#ifndef __SDHCI_H__
+#define __SDHCI_H__
-#define PCI_SDHCI_IFPIO 0x00
-#define PCI_SDHCI_IFDMA 0x01
-#define PCI_SDHCI_IFVENDOR 0x02
+#define DMA_BLOCK_SIZE 4096
+#define DMA_BOUNDARY 0 /* DMA reload every 4K */
-#define PCI_SLOT_INFO 0x40 /* 8 bits */
-#define PCI_SLOT_INFO_SLOTS(x) (((x >> 4) & 7) + 1)
-#define PCI_SLOT_INFO_FIRST_BAR(x) ((x) & 7)
+/* Controller doesn't honor resets unless we touch the clock register */
+#define SDHCI_QUIRK_CLOCK_BEFORE_RESET (1 << 0)
+/* Controller really supports DMA */
+#define SDHCI_QUIRK_FORCE_DMA (1 << 1)
+/* Controller has unusable DMA engine */
+#define SDHCI_QUIRK_BROKEN_DMA (1 << 2)
+/* Controller doesn't like to be reset when there is no card inserted. */
+#define SDHCI_QUIRK_NO_CARD_NO_RESET (1 << 3)
+/* Controller has flaky internal state so reset it on each ios change */
+#define SDHCI_QUIRK_RESET_ON_IOS (1 << 4)
+/* Controller can only DMA chunk sizes that are a multiple of 32 bits */
+#define SDHCI_QUIRK_32BIT_DMA_SIZE (1 << 5)
+/* Controller needs to be reset after each request to stay stable */
+#define SDHCI_QUIRK_RESET_AFTER_REQUEST (1 << 6)
+/* Controller has an off-by-one issue with timeout value */
+#define SDHCI_QUIRK_INCR_TIMEOUT_CONTROL (1 << 7)
+/* Controller has broken read timings */
+#define SDHCI_QUIRK_BROKEN_TIMINGS (1 << 8)
+/* Controller needs lowered frequency */
+#define SDHCI_QUIRK_LOWER_FREQUENCY (1 << 9)
+/* Data timeout is invalid, should use SD clock */
+#define SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK (1 << 10)
+/* Timeout value is invalid, should be overriden */
+#define SDHCI_QUIRK_BROKEN_TIMEOUT_VAL (1 << 11)
+/* SDHCI_CAPABILITIES is invalid */
+#define SDHCI_QUIRK_MISSING_CAPS (1 << 12)
+/* Hardware shifts the 136-bit response, don't do it in software. */
+#define SDHCI_QUIRK_DONT_SHIFT_RESPONSE (1 << 13)
+/* Wait to see reset bit asserted before waiting for de-asserted */
+#define SDHCI_QUIRK_WAITFOR_RESET_ASSERTED (1 << 14)
+/* Leave controller in standard mode when putting card in HS mode. */
+#define SDHCI_QUIRK_DONT_SET_HISPD_BIT (1 << 15)
+/* Alternate clock source is required when supplying a 400 KHz clock. */
+#define SDHCI_QUIRK_BCM577XX_400KHZ_CLKSRC (1 << 16)
+/* Card insert/remove interrupts don't work, polling required. */
+#define SDHCI_QUIRK_POLL_CARD_PRESENT (1 << 17)
+/* All controller slots are non-removable. */
+#define SDHCI_QUIRK_ALL_SLOTS_NON_REMOVABLE (1 << 18)
+/* Issue custom Intel controller reset sequence after power-up. */
+#define SDHCI_QUIRK_INTEL_POWER_UP_RESET (1 << 19)
+/* Data timeout is invalid, use 1 MHz clock instead. */
+#define SDHCI_QUIRK_DATA_TIMEOUT_1MHZ (1 << 20)
+/* Controller doesn't allow access boot partitions. */
+#define SDHCI_QUIRK_BOOT_NOACC (1 << 21)
+/* Controller waits for busy responses. */
+#define SDHCI_QUIRK_WAIT_WHILE_BUSY (1 << 22)
+/* Controller supports eMMC DDR52 mode. */
+#define SDHCI_QUIRK_MMC_DDR52 (1 << 23)
+/* Controller support for UHS DDR50 mode is broken. */
+#define SDHCI_QUIRK_BROKEN_UHS_DDR50 (1 << 24)
+/* Controller support for eMMC HS200 mode is broken. */
+#define SDHCI_QUIRK_BROKEN_MMC_HS200 (1 << 25)
+/* Controller reports support for eMMC HS400 mode as SDHCI_CAN_MMC_HS400. */
+#define SDHCI_QUIRK_CAPS_BIT63_FOR_MMC_HS400 (1 << 26)
+/* Controller support for SDHCI_CTRL2_PRESET_VALUE is broken. */
+#define SDHCI_QUIRK_PRESET_VALUE_BROKEN (1 << 27)
/*
- * RICOH specific PCI registers
- */
-#define SDHC_PCI_MODE_KEY 0xf9
-#define SDHC_PCI_MODE 0x150
-#define SDHC_PCI_MODE_SD20 0x10
-#define SDHC_PCI_BASE_FREQ_KEY 0xfc
-#define SDHC_PCI_BASE_FREQ 0xe1
-
-/*
* Controller registers
*/
+#define SDHCI_DMA_ADDRESS 0x00
-#define SDHCI_DMA_ADDRESS 0x00
+#define SDHCI_BLOCK_SIZE 0x04
+#define SDHCI_MAKE_BLKSZ(dma, blksz) (((dma & 0x7) << 12) | (blksz & 0xFFF))
-#define SDHCI_BLOCK_SIZE 0x04
-#define SDHCI_MAKE_BLKSZ(dma, blksz) (((dma & 0x7) << 12) | (blksz & 0xFFF))
+#define SDHCI_BLOCK_COUNT 0x06
-#define SDHCI_BLOCK_COUNT 0x06
+#define SDHCI_ARGUMENT 0x08
-#define SDHCI_ARGUMENT 0x08
+#define SDHCI_TRANSFER_MODE 0x0C
+#define SDHCI_TRNS_DMA 0x01
+#define SDHCI_TRNS_BLK_CNT_EN 0x02
+#define SDHCI_TRNS_ACMD12 0x04
+#define SDHCI_TRNS_READ 0x10
+#define SDHCI_TRNS_MULTI 0x20
-#define SDHCI_TRANSFER_MODE 0x0C
-#define SDHCI_TRNS_DMA 0x01
-#define SDHCI_TRNS_BLK_CNT_EN 0x02
-#define SDHCI_TRNS_ACMD12 0x04
-#define SDHCI_TRNS_READ 0x10
-#define SDHCI_TRNS_MULTI 0x20
+#define SDHCI_COMMAND_FLAGS 0x0E
+#define SDHCI_CMD_RESP_NONE 0x00
+#define SDHCI_CMD_RESP_LONG 0x01
+#define SDHCI_CMD_RESP_SHORT 0x02
+#define SDHCI_CMD_RESP_SHORT_BUSY 0x03
+#define SDHCI_CMD_RESP_MASK 0x03
+#define SDHCI_CMD_CRC 0x08
+#define SDHCI_CMD_INDEX 0x10
+#define SDHCI_CMD_DATA 0x20
+#define SDHCI_CMD_TYPE_NORMAL 0x00
+#define SDHCI_CMD_TYPE_SUSPEND 0x40
+#define SDHCI_CMD_TYPE_RESUME 0x80
+#define SDHCI_CMD_TYPE_ABORT 0xc0
+#define SDHCI_CMD_TYPE_MASK 0xc0
-#define SDHCI_COMMAND_FLAGS 0x0E
-#define SDHCI_CMD_RESP_NONE 0x00
-#define SDHCI_CMD_RESP_LONG 0x01
-#define SDHCI_CMD_RESP_SHORT 0x02
-#define SDHCI_CMD_RESP_SHORT_BUSY 0x03
-#define SDHCI_CMD_RESP_MASK 0x03
-#define SDHCI_CMD_CRC 0x08
-#define SDHCI_CMD_INDEX 0x10
-#define SDHCI_CMD_DATA 0x20
-#define SDHCI_CMD_TYPE_NORMAL 0x00
-#define SDHCI_CMD_TYPE_SUSPEND 0x40
-#define SDHCI_CMD_TYPE_RESUME 0x80
-#define SDHCI_CMD_TYPE_ABORT 0xc0
-#define SDHCI_CMD_TYPE_MASK 0xc0
+#define SDHCI_COMMAND 0x0F
-#define SDHCI_COMMAND 0x0F
+#define SDHCI_RESPONSE 0x10
-#define SDHCI_RESPONSE 0x10
+#define SDHCI_BUFFER 0x20
-#define SDHCI_BUFFER 0x20
+#define SDHCI_PRESENT_STATE 0x24
+#define SDHCI_CMD_INHIBIT 0x00000001
+#define SDHCI_DAT_INHIBIT 0x00000002
+#define SDHCI_DAT_ACTIVE 0x00000004
+#define SDHCI_RETUNE_REQUEST 0x00000008
+#define SDHCI_DOING_WRITE 0x00000100
+#define SDHCI_DOING_READ 0x00000200
+#define SDHCI_SPACE_AVAILABLE 0x00000400
+#define SDHCI_DATA_AVAILABLE 0x00000800
+#define SDHCI_CARD_PRESENT 0x00010000
+#define SDHCI_CARD_STABLE 0x00020000
+#define SDHCI_CARD_PIN 0x00040000
+#define SDHCI_WRITE_PROTECT 0x00080000
+#define SDHCI_STATE_DAT_MASK 0x00f00000
+#define SDHCI_STATE_CMD 0x01000000
-#define SDHCI_PRESENT_STATE 0x24
-#define SDHCI_CMD_INHIBIT 0x00000001
-#define SDHCI_DAT_INHIBIT 0x00000002
-#define SDHCI_DAT_ACTIVE 0x00000004
-#define SDHCI_DOING_WRITE 0x00000100
-#define SDHCI_DOING_READ 0x00000200
-#define SDHCI_SPACE_AVAILABLE 0x00000400
-#define SDHCI_DATA_AVAILABLE 0x00000800
-#define SDHCI_CARD_PRESENT 0x00010000
-#define SDHCI_CARD_STABLE 0x00020000
-#define SDHCI_CARD_PIN 0x00040000
-#define SDHCI_WRITE_PROTECT 0x00080000
-#define SDHCI_STATE_DAT 0x00700000
-#define SDHCI_STATE_CMD 0x00800000
+#define SDHCI_HOST_CONTROL 0x28
+#define SDHCI_CTRL_LED 0x01
+#define SDHCI_CTRL_4BITBUS 0x02
+#define SDHCI_CTRL_HISPD 0x04
+#define SDHCI_CTRL_SDMA 0x08
+#define SDHCI_CTRL_ADMA2 0x10
+#define SDHCI_CTRL_ADMA264 0x18
+#define SDHCI_CTRL_DMA_MASK 0x18
+#define SDHCI_CTRL_8BITBUS 0x20
+#define SDHCI_CTRL_CARD_DET 0x40
+#define SDHCI_CTRL_FORCE_CARD 0x80
-#define SDHCI_HOST_CONTROL 0x28
-#define SDHCI_CTRL_LED 0x01
-#define SDHCI_CTRL_4BITBUS 0x02
-#define SDHCI_CTRL_HISPD 0x04
-#define SDHCI_CTRL_SDMA 0x08
-#define SDHCI_CTRL_ADMA2 0x10
-#define SDHCI_CTRL_ADMA264 0x18
-#define SDHCI_CTRL_CARD_DET 0x40
-#define SDHCI_CTRL_FORCE_CARD 0x80
+#define SDHCI_POWER_CONTROL 0x29
+#define SDHCI_POWER_ON 0x01
+#define SDHCI_POWER_180 0x0A
+#define SDHCI_POWER_300 0x0C
+#define SDHCI_POWER_330 0x0E
-#define SDHCI_POWER_CONTROL 0x29
-#define SDHCI_POWER_ON 0x01
-#define SDHCI_POWER_180 0x0A
-#define SDHCI_POWER_300 0x0C
-#define SDHCI_POWER_330 0x0E
+#define SDHCI_BLOCK_GAP_CONTROL 0x2A
-#define SDHCI_BLOCK_GAP_CONTROL 0x2A
+#define SDHCI_WAKE_UP_CONTROL 0x2B
-#define SDHCI_WAKE_UP_CONTROL 0x2B
+#define SDHCI_CLOCK_CONTROL 0x2C
+#define SDHCI_DIVIDER_MASK 0xff
+#define SDHCI_DIVIDER_MASK_LEN 8
+#define SDHCI_DIVIDER_SHIFT 8
+#define SDHCI_DIVIDER_HI_MASK 3
+#define SDHCI_DIVIDER_HI_SHIFT 6
+#define SDHCI_CLOCK_CARD_EN 0x0004
+#define SDHCI_CLOCK_INT_STABLE 0x0002
+#define SDHCI_CLOCK_INT_EN 0x0001
+#define SDHCI_DIVIDERS_MASK \
+ ((SDHCI_DIVIDER_MASK << SDHCI_DIVIDER_SHIFT) | \
+ (SDHCI_DIVIDER_HI_MASK << SDHCI_DIVIDER_HI_SHIFT))
-#define SDHCI_CLOCK_CONTROL 0x2C
-#define SDHCI_DIVIDER_SHIFT 8
-#define SDHCI_CLOCK_CARD_EN 0x0004
-#define SDHCI_CLOCK_INT_STABLE 0x0002
-#define SDHCI_CLOCK_INT_EN 0x0001
+#define SDHCI_TIMEOUT_CONTROL 0x2E
-#define SDHCI_TIMEOUT_CONTROL 0x2E
+#define SDHCI_SOFTWARE_RESET 0x2F
+#define SDHCI_RESET_ALL 0x01
+#define SDHCI_RESET_CMD 0x02
+#define SDHCI_RESET_DATA 0x04
-#define SDHCI_SOFTWARE_RESET 0x2F
-#define SDHCI_RESET_ALL 0x01
-#define SDHCI_RESET_CMD 0x02
-#define SDHCI_RESET_DATA 0x04
+#define SDHCI_INT_STATUS 0x30
+#define SDHCI_INT_ENABLE 0x34
+#define SDHCI_SIGNAL_ENABLE 0x38
+#define SDHCI_INT_RESPONSE 0x00000001
+#define SDHCI_INT_DATA_END 0x00000002
+#define SDHCI_INT_BLOCK_GAP 0x00000004
+#define SDHCI_INT_DMA_END 0x00000008
+#define SDHCI_INT_SPACE_AVAIL 0x00000010
+#define SDHCI_INT_DATA_AVAIL 0x00000020
+#define SDHCI_INT_CARD_INSERT 0x00000040
+#define SDHCI_INT_CARD_REMOVE 0x00000080
+#define SDHCI_INT_CARD_INT 0x00000100
+#define SDHCI_INT_INT_A 0x00000200
+#define SDHCI_INT_INT_B 0x00000400
+#define SDHCI_INT_INT_C 0x00000800
+#define SDHCI_INT_RETUNE 0x00001000
+#define SDHCI_INT_ERROR 0x00008000
+#define SDHCI_INT_TIMEOUT 0x00010000
+#define SDHCI_INT_CRC 0x00020000
+#define SDHCI_INT_END_BIT 0x00040000
+#define SDHCI_INT_INDEX 0x00080000
+#define SDHCI_INT_DATA_TIMEOUT 0x00100000
+#define SDHCI_INT_DATA_CRC 0x00200000
+#define SDHCI_INT_DATA_END_BIT 0x00400000
+#define SDHCI_INT_BUS_POWER 0x00800000
+#define SDHCI_INT_ACMD12ERR 0x01000000
+#define SDHCI_INT_ADMAERR 0x02000000
+#define SDHCI_INT_TUNEERR 0x04000000
-#define SDHCI_INT_STATUS 0x30
-#define SDHCI_INT_ENABLE 0x34
-#define SDHCI_SIGNAL_ENABLE 0x38
-#define SDHCI_INT_RESPONSE 0x00000001
-#define SDHCI_INT_DATA_END 0x00000002
-#define SDHCI_INT_BLOCK_GAP 0x00000004
-#define SDHCI_INT_DMA_END 0x00000008
-#define SDHCI_INT_SPACE_AVAIL 0x00000010
-#define SDHCI_INT_DATA_AVAIL 0x00000020
-#define SDHCI_INT_CARD_INSERT 0x00000040
-#define SDHCI_INT_CARD_REMOVE 0x00000080
-#define SDHCI_INT_CARD_INT 0x00000100
-#define SDHCI_INT_ERROR 0x00008000
-#define SDHCI_INT_TIMEOUT 0x00010000
-#define SDHCI_INT_CRC 0x00020000
-#define SDHCI_INT_END_BIT 0x00040000
-#define SDHCI_INT_INDEX 0x00080000
-#define SDHCI_INT_DATA_TIMEOUT 0x00100000
-#define SDHCI_INT_DATA_CRC 0x00200000
-#define SDHCI_INT_DATA_END_BIT 0x00400000
-#define SDHCI_INT_BUS_POWER 0x00800000
-#define SDHCI_INT_ACMD12ERR 0x01000000
-#define SDHCI_INT_ADMAERR 0x02000000
+#define SDHCI_INT_NORMAL_MASK 0x00007FFF
+#define SDHCI_INT_ERROR_MASK 0xFFFF8000
-#define SDHCI_INT_NORMAL_MASK 0x00007FFF
-#define SDHCI_INT_ERROR_MASK 0xFFFF8000
+#define SDHCI_INT_CMD_ERROR_MASK (SDHCI_INT_TIMEOUT | \
+ SDHCI_INT_CRC | SDHCI_INT_END_BIT | SDHCI_INT_INDEX)
-#define SDHCI_INT_CMD_MASK (SDHCI_INT_RESPONSE | SDHCI_INT_TIMEOUT | \
- SDHCI_INT_CRC | SDHCI_INT_END_BIT | SDHCI_INT_INDEX)
-#define SDHCI_INT_DATA_MASK (SDHCI_INT_DATA_END | SDHCI_INT_DMA_END | \
+#define SDHCI_INT_CMD_MASK (SDHCI_INT_RESPONSE | SDHCI_INT_CMD_ERROR_MASK)
+
+#define SDHCI_INT_DATA_MASK (SDHCI_INT_DATA_END | SDHCI_INT_DMA_END | \
SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL | \
SDHCI_INT_DATA_TIMEOUT | SDHCI_INT_DATA_CRC | \
SDHCI_INT_DATA_END_BIT)
-#define SDHCI_ACMD12_ERR 0x3C
+#define SDHCI_ACMD12_ERR 0x3C
-#define SDHCI_CAPABILITIES 0x40
-#define SDHCI_TIMEOUT_CLK_MASK 0x0000003F
-#define SDHCI_TIMEOUT_CLK_SHIFT 0
-#define SDHCI_TIMEOUT_CLK_UNIT 0x00000080
-#define SDHCI_CLOCK_BASE_MASK 0x00003F00
-#define SDHCI_CLOCK_BASE_SHIFT 8
-#define SDHCI_MAX_BLOCK_MASK 0x00030000
-#define SDHCI_MAX_BLOCK_SHIFT 16
-#define SDHCI_CAN_DO_ADMA2 0x00080000
-#define SDHCI_CAN_DO_HISPD 0x00200000
-#define SDHCI_CAN_DO_DMA 0x00400000
-#define SDHCI_CAN_DO_SUSPEND 0x00800000
-#define SDHCI_CAN_VDD_330 0x01000000
-#define SDHCI_CAN_VDD_300 0x02000000
-#define SDHCI_CAN_VDD_180 0x04000000
-#define SDHCI_CAN_DO_64BIT 0x10000000
+#define SDHCI_HOST_CONTROL2 0x3E
+#define SDHCI_CTRL2_PRESET_VALUE 0x8000
+#define SDHCI_CTRL2_ASYNC_INTR 0x4000
+#define SDHCI_CTRL2_64BIT_ENABLE 0x2000
+#define SDHCI_CTRL2_HOST_V4_ENABLE 0x1000
+#define SDHCI_CTRL2_CMD23_ENABLE 0x0800
+#define SDHCI_CTRL2_ADMA2_LENGTH_MODE 0x0400
+#define SDHCI_CTRL2_UHS2_IFACE_ENABLE 0x0100
+#define SDHCI_CTRL2_SAMPLING_CLOCK 0x0080
+#define SDHCI_CTRL2_EXEC_TUNING 0x0040
+#define SDHCI_CTRL2_DRIVER_TYPE_MASK 0x0030
+#define SDHCI_CTRL2_DRIVER_TYPE_B 0x0000
+#define SDHCI_CTRL2_DRIVER_TYPE_A 0x0010
+#define SDHCI_CTRL2_DRIVER_TYPE_C 0x0020
+#define SDHCI_CTRL2_DRIVER_TYPE_D 0x0030
+#define SDHCI_CTRL2_S18_ENABLE 0x0008
+#define SDHCI_CTRL2_UHS_MASK 0x0007
+#define SDHCI_CTRL2_UHS_SDR12 0x0000
+#define SDHCI_CTRL2_UHS_SDR25 0x0001
+#define SDHCI_CTRL2_UHS_SDR50 0x0002
+#define SDHCI_CTRL2_UHS_SDR104 0x0003
+#define SDHCI_CTRL2_UHS_DDR50 0x0004
+#define SDHCI_CTRL2_MMC_HS400 0x0005 /* non-standard */
-#define SDHCI_MAX_CURRENT 0x48
+#define SDHCI_CAPABILITIES 0x40
+#define SDHCI_TIMEOUT_CLK_MASK 0x0000003F
+#define SDHCI_TIMEOUT_CLK_SHIFT 0
+#define SDHCI_TIMEOUT_CLK_UNIT 0x00000080
+#define SDHCI_CLOCK_BASE_MASK 0x00003F00
+#define SDHCI_CLOCK_V3_BASE_MASK 0x0000FF00
+#define SDHCI_CLOCK_BASE_SHIFT 8
+#define SDHCI_MAX_BLOCK_MASK 0x00030000
+#define SDHCI_MAX_BLOCK_SHIFT 16
+#define SDHCI_CAN_DO_8BITBUS 0x00040000
+#define SDHCI_CAN_DO_ADMA2 0x00080000
+#define SDHCI_CAN_DO_HISPD 0x00200000
+#define SDHCI_CAN_DO_DMA 0x00400000
+#define SDHCI_CAN_DO_SUSPEND 0x00800000
+#define SDHCI_CAN_VDD_330 0x01000000
+#define SDHCI_CAN_VDD_300 0x02000000
+#define SDHCI_CAN_VDD_180 0x04000000
+#define SDHCI_CAN_DO_64BIT 0x10000000
+#define SDHCI_CAN_ASYNC_INTR 0x20000000
+#define SDHCI_SLOTTYPE_MASK 0xC0000000
+#define SDHCI_SLOTTYPE_REMOVABLE 0x00000000
+#define SDHCI_SLOTTYPE_EMBEDDED 0x40000000
+#define SDHCI_SLOTTYPE_SHARED 0x80000000
-#define SDHCI_SLOT_INT_STATUS 0xFC
+#define SDHCI_CAPABILITIES2 0x44
+#define SDHCI_CAN_SDR50 0x00000001
+#define SDHCI_CAN_SDR104 0x00000002
+#define SDHCI_CAN_DDR50 0x00000004
+#define SDHCI_CAN_DRIVE_TYPE_A 0x00000010
+#define SDHCI_CAN_DRIVE_TYPE_C 0x00000020
+#define SDHCI_CAN_DRIVE_TYPE_D 0x00000040
+#define SDHCI_RETUNE_CNT_MASK 0x00000F00
+#define SDHCI_RETUNE_CNT_SHIFT 8
+#define SDHCI_TUNE_SDR50 0x00002000
+#define SDHCI_RETUNE_MODES_MASK 0x0000C000
+#define SDHCI_RETUNE_MODES_SHIFT 14
+#define SDHCI_CLOCK_MULT_MASK 0x00FF0000
+#define SDHCI_CLOCK_MULT_SHIFT 16
+#define SDHCI_CAN_MMC_HS400 0x80000000 /* non-standard */
-#define SDHCI_HOST_VERSION 0xFE
-#define SDHCI_VENDOR_VER_MASK 0xFF00
-#define SDHCI_VENDOR_VER_SHIFT 8
-#define SDHCI_SPEC_VER_MASK 0x00FF
-#define SDHCI_SPEC_VER_SHIFT 0
+#define SDHCI_MAX_CURRENT 0x48
+#define SDHCI_FORCE_AUTO_EVENT 0x50
+#define SDHCI_FORCE_INTR_EVENT 0x52
+
+#define SDHCI_ADMA_ERR 0x54
+#define SDHCI_ADMA_ERR_LENGTH 0x04
+#define SDHCI_ADMA_ERR_STATE_MASK 0x03
+#define SDHCI_ADMA_ERR_STATE_STOP 0x00
+#define SDHCI_ADMA_ERR_STATE_FDS 0x01
+#define SDHCI_ADMA_ERR_STATE_TFR 0x03
+
+#define SDHCI_ADMA_ADDRESS_LO 0x58
+#define SDHCI_ADMA_ADDRESS_HI 0x5C
+
+#define SDHCI_PRESET_VALUE 0x60
+#define SDHCI_SHARED_BUS_CTRL 0xE0
+
+#define SDHCI_SLOT_INT_STATUS 0xFC
+
+#define SDHCI_HOST_VERSION 0xFE
+#define SDHCI_VENDOR_VER_MASK 0xFF00
+#define SDHCI_VENDOR_VER_SHIFT 8
+#define SDHCI_SPEC_VER_MASK 0x00FF
+#define SDHCI_SPEC_VER_SHIFT 0
+#define SDHCI_SPEC_100 0
+#define SDHCI_SPEC_200 1
+#define SDHCI_SPEC_300 2
+#define SDHCI_SPEC_400 3
+#define SDHCI_SPEC_410 4
+#define SDHCI_SPEC_420 5
+
+SYSCTL_DECL(_hw_sdhci);
+
+extern u_int sdhci_quirk_clear;
+extern u_int sdhci_quirk_set;
+
+struct sdhci_slot {
+ struct mtx mtx; /* Slot mutex */
+ u_int quirks; /* Chip specific quirks */
+ u_int caps; /* Override SDHCI_CAPABILITIES */
+ u_int caps2; /* Override SDHCI_CAPABILITIES2 */
+ device_t bus; /* Bus device */
+ device_t dev; /* Slot device */
+ u_char num; /* Slot number */
+ u_char opt; /* Slot options */
+#define SDHCI_HAVE_DMA 0x01
+#define SDHCI_PLATFORM_TRANSFER 0x02
+#define SDHCI_NON_REMOVABLE 0x04
+#define SDHCI_TUNING_SUPPORTED 0x08
+#define SDHCI_TUNING_ENABLED 0x10
+#define SDHCI_SDR50_NEEDS_TUNING 0x20
+#define SDHCI_SLOT_EMBEDDED 0x40
+ u_char version;
+ int timeout; /* Transfer timeout */
+ uint32_t max_clk; /* Max possible freq */
+ uint32_t timeout_clk; /* Timeout freq */
+ bus_dma_tag_t dmatag;
+ bus_dmamap_t dmamap;
+ u_char *dmamem;
+ bus_addr_t paddr; /* DMA buffer address */
+ struct task card_task; /* Card presence check task */
+ struct timeout_task
+ card_delayed_task;/* Card insert delayed task */
+ struct callout card_poll_callout;/* Card present polling callout */
+ struct callout timeout_callout;/* Card command/data response timeout */
+ struct callout retune_callout; /* Re-tuning mode 1 callout */
+ struct mmc_host host; /* Host parameters */
+ struct mmc_request *req; /* Current request */
+ struct mmc_command *curcmd; /* Current command of current request */
+
+ struct mmc_request *tune_req; /* Tuning request */
+ struct mmc_command *tune_cmd; /* Tuning command of tuning request */
+ struct mmc_data *tune_data; /* Tuning data of tuning command */
+ uint32_t retune_ticks; /* Re-tuning callout ticks [hz] */
+ uint32_t intmask; /* Current interrupt mask */
+ uint32_t clock; /* Current clock freq. */
+ size_t offset; /* Data buffer offset */
+ uint8_t hostctrl; /* Current host control register */
+ uint8_t retune_count; /* Controller re-tuning count [s] */
+ uint8_t retune_mode; /* Controller re-tuning mode */
+#define SDHCI_RETUNE_MODE_1 0x00
+#define SDHCI_RETUNE_MODE_2 0x01
+#define SDHCI_RETUNE_MODE_3 0x02
+ uint8_t retune_req; /* Re-tuning request status */
+#define SDHCI_RETUNE_REQ_NEEDED 0x01 /* Re-tuning w/o circuit reset needed */
+#define SDHCI_RETUNE_REQ_RESET 0x02 /* Re-tuning w/ circuit reset needed */
+ u_char power; /* Current power */
+ u_char bus_busy; /* Bus busy status */
+ u_char cmd_done; /* CMD command part done flag */
+ u_char data_done; /* DAT command part done flag */
+ u_char flags; /* Request execution flags */
+#define CMD_STARTED 1
+#define STOP_STARTED 2
+#define SDHCI_USE_DMA 4 /* Use DMA for this req. */
+#define PLATFORM_DATA_STARTED 8 /* Data xfer is handled by platform */
+};
+
+int sdhci_generic_read_ivar(device_t bus, device_t child, int which,
+ uintptr_t *result);
+int sdhci_generic_write_ivar(device_t bus, device_t child, int which,
+ uintptr_t value);
+int sdhci_init_slot(device_t dev, struct sdhci_slot *slot, int num);
+void sdhci_start_slot(struct sdhci_slot *slot);
+/* performs generic clean-up for platform transfers */
+void sdhci_finish_data(struct sdhci_slot *slot);
+int sdhci_cleanup_slot(struct sdhci_slot *slot);
+int sdhci_generic_suspend(struct sdhci_slot *slot);
+int sdhci_generic_resume(struct sdhci_slot *slot);
+int sdhci_generic_update_ios(device_t brdev, device_t reqdev);
+int sdhci_generic_tune(device_t brdev, device_t reqdev, bool hs400);
+int sdhci_generic_switch_vccq(device_t brdev, device_t reqdev);
+int sdhci_generic_retune(device_t brdev, device_t reqdev, bool reset);
+int sdhci_generic_request(device_t brdev, device_t reqdev,
+ struct mmc_request *req);
+int sdhci_generic_get_ro(device_t brdev, device_t reqdev);
+int sdhci_generic_acquire_host(device_t brdev, device_t reqdev);
+int sdhci_generic_release_host(device_t brdev, device_t reqdev);
+void sdhci_generic_intr(struct sdhci_slot *slot);
+uint32_t sdhci_generic_min_freq(device_t brdev, struct sdhci_slot *slot);
+bool sdhci_generic_get_card_present(device_t brdev, struct sdhci_slot *slot);
+void sdhci_generic_set_uhs_timing(device_t brdev, struct sdhci_slot *slot);
+void sdhci_handle_card_present(struct sdhci_slot *slot, bool is_present);
+
+#endif /* __SDHCI_H__ */
Added: trunk/sys/dev/sdhci/sdhci_acpi.c
===================================================================
--- trunk/sys/dev/sdhci/sdhci_acpi.c (rev 0)
+++ trunk/sys/dev/sdhci/sdhci_acpi.c 2018-05-27 23:15:22 UTC (rev 10073)
@@ -0,0 +1,404 @@
+/* $MidnightBSD$ */
+/*-
+ * Copyright (c) 2017 Oleksandr Tymoshenko <gonzo at FreeBSD.org>
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+ * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+ * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <sys/cdefs.h>
+__FBSDID("$FreeBSD: stable/10/sys/dev/sdhci/sdhci_acpi.c 322122 2017-08-06 16:12:56Z marius $");
+
+#include <sys/param.h>
+#include <sys/systm.h>
+#include <sys/bus.h>
+#include <sys/kernel.h>
+#include <sys/lock.h>
+#include <sys/module.h>
+#include <sys/mutex.h>
+#include <sys/resource.h>
+#include <sys/rman.h>
+#include <sys/sysctl.h>
+#include <sys/taskqueue.h>
+
+#include <machine/bus.h>
+#include <machine/resource.h>
+
+#include <contrib/dev/acpica/include/acpi.h>
+#include <dev/acpica/acpivar.h>
+
+#include <dev/mmc/bridge.h>
+
+#include <dev/sdhci/sdhci.h>
+
+#include "mmcbr_if.h"
+#include "sdhci_if.h"
+
+static const struct sdhci_acpi_device {
+ const char* hid;
+ int uid;
+ const char *desc;
+ u_int quirks;
+} sdhci_acpi_devices[] = {
+ { "80860F14", 1, "Intel Bay Trail/Braswell eMMC 4.5/4.5.1 Controller",
+ SDHCI_QUIRK_INTEL_POWER_UP_RESET |
+ SDHCI_QUIRK_WAIT_WHILE_BUSY |
+ SDHCI_QUIRK_MMC_DDR52 |
+ SDHCI_QUIRK_CAPS_BIT63_FOR_MMC_HS400 |
+ SDHCI_QUIRK_PRESET_VALUE_BROKEN },
+ { "80860F14", 3, "Intel Bay Trail/Braswell SDXC Controller",
+ SDHCI_QUIRK_WAIT_WHILE_BUSY |
+ SDHCI_QUIRK_PRESET_VALUE_BROKEN },
+ { "80860F16", 0, "Intel Bay Trail/Braswell SDXC Controller",
+ SDHCI_QUIRK_WAIT_WHILE_BUSY |
+ SDHCI_QUIRK_PRESET_VALUE_BROKEN },
+ { "80865ACA", 0, "Intel Apollo Lake SDXC Controller",
+ SDHCI_QUIRK_BROKEN_DMA | /* APL18 erratum */
+ SDHCI_QUIRK_WAIT_WHILE_BUSY |
+ SDHCI_QUIRK_PRESET_VALUE_BROKEN },
+ { "80865ACC", 0, "Intel Apollo Lake eMMC 5.0 Controller",
+ SDHCI_QUIRK_BROKEN_DMA | /* APL18 erratum */
+ SDHCI_QUIRK_INTEL_POWER_UP_RESET |
+ SDHCI_QUIRK_WAIT_WHILE_BUSY |
+ SDHCI_QUIRK_MMC_DDR52 |
+ SDHCI_QUIRK_CAPS_BIT63_FOR_MMC_HS400 |
+ SDHCI_QUIRK_PRESET_VALUE_BROKEN },
+ { NULL, 0, NULL, 0}
+};
+
+static char *sdhci_ids[] = {
+ "80860F14",
+ "80860F16",
+ "80865ACA",
+ "80865ACC",
+ NULL
+};
+
+struct sdhci_acpi_softc {
+ u_int quirks; /* Chip specific quirks */
+ struct resource *irq_res; /* IRQ resource */
+ void *intrhand; /* Interrupt handle */
+
+ struct sdhci_slot slot;
+ struct resource *mem_res; /* Memory resource */
+};
+
+static void sdhci_acpi_intr(void *arg);
+static int sdhci_acpi_detach(device_t dev);
+
+static uint8_t
+sdhci_acpi_read_1(device_t dev, struct sdhci_slot *slot __unused,
+ bus_size_t off)
+{
+ struct sdhci_acpi_softc *sc = device_get_softc(dev);
+
+ bus_barrier(sc->mem_res, 0, 0xFF,
+ BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE);
+ return bus_read_1(sc->mem_res, off);
+}
+
+static void
+sdhci_acpi_write_1(device_t dev, struct sdhci_slot *slot __unused,
+ bus_size_t off, uint8_t val)
+{
+ struct sdhci_acpi_softc *sc = device_get_softc(dev);
+
+ bus_barrier(sc->mem_res, 0, 0xFF,
+ BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE);
+ bus_write_1(sc->mem_res, off, val);
+}
+
+static uint16_t
+sdhci_acpi_read_2(device_t dev, struct sdhci_slot *slot __unused,
+ bus_size_t off)
+{
+ struct sdhci_acpi_softc *sc = device_get_softc(dev);
+
+ bus_barrier(sc->mem_res, 0, 0xFF,
+ BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE);
+ return bus_read_2(sc->mem_res, off);
+}
+
+static void
+sdhci_acpi_write_2(device_t dev, struct sdhci_slot *slot __unused,
+ bus_size_t off, uint16_t val)
+{
+ struct sdhci_acpi_softc *sc = device_get_softc(dev);
+
+ bus_barrier(sc->mem_res, 0, 0xFF,
+ BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE);
+ bus_write_2(sc->mem_res, off, val);
+}
+
+static uint32_t
+sdhci_acpi_read_4(device_t dev, struct sdhci_slot *slot __unused,
+ bus_size_t off)
+{
+ struct sdhci_acpi_softc *sc = device_get_softc(dev);
+
+ bus_barrier(sc->mem_res, 0, 0xFF,
+ BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE);
+ return bus_read_4(sc->mem_res, off);
+}
+
+static void
+sdhci_acpi_write_4(device_t dev, struct sdhci_slot *slot __unused,
+ bus_size_t off, uint32_t val)
+{
+ struct sdhci_acpi_softc *sc = device_get_softc(dev);
+
+ bus_barrier(sc->mem_res, 0, 0xFF,
+ BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE);
+ bus_write_4(sc->mem_res, off, val);
+}
+
+static void
+sdhci_acpi_read_multi_4(device_t dev, struct sdhci_slot *slot __unused,
+ bus_size_t off, uint32_t *data, bus_size_t count)
+{
+ struct sdhci_acpi_softc *sc = device_get_softc(dev);
+
+ bus_read_multi_stream_4(sc->mem_res, off, data, count);
+}
+
+static void
+sdhci_acpi_write_multi_4(device_t dev, struct sdhci_slot *slot __unused,
+ bus_size_t off, uint32_t *data, bus_size_t count)
+{
+ struct sdhci_acpi_softc *sc = device_get_softc(dev);
+
+ bus_write_multi_stream_4(sc->mem_res, off, data, count);
+}
+
+static const struct sdhci_acpi_device *
+sdhci_acpi_find_device(device_t dev)
+{
+ const char *hid;
+ int i, uid;
+ ACPI_HANDLE handle;
+ ACPI_STATUS status;
+
+ hid = ACPI_ID_PROBE(device_get_parent(dev), dev, sdhci_ids);
+ if (hid == NULL)
+ return (NULL);
+
+ handle = acpi_get_handle(dev);
+ status = acpi_GetInteger(handle, "_UID", &uid);
+ if (ACPI_FAILURE(status))
+ uid = 0;
+
+ for (i = 0; sdhci_acpi_devices[i].hid != NULL; i++) {
+ if (strcmp(sdhci_acpi_devices[i].hid, hid) != 0)
+ continue;
+ if ((sdhci_acpi_devices[i].uid != 0) &&
+ (sdhci_acpi_devices[i].uid != uid))
+ continue;
+ return (&sdhci_acpi_devices[i]);
+ }
+
+ return (NULL);
+}
+
+static int
+sdhci_acpi_probe(device_t dev)
+{
+ const struct sdhci_acpi_device *acpi_dev;
+
+ acpi_dev = sdhci_acpi_find_device(dev);
+ if (acpi_dev == NULL)
+ return (ENXIO);
+
+ device_set_desc(dev, acpi_dev->desc);
+
+ return (BUS_PROBE_DEFAULT);
+}
+
+static int
+sdhci_acpi_attach(device_t dev)
+{
+ struct sdhci_acpi_softc *sc = device_get_softc(dev);
+ int rid, err;
+ const struct sdhci_acpi_device *acpi_dev;
+
+ acpi_dev = sdhci_acpi_find_device(dev);
+ if (acpi_dev == NULL)
+ return (ENXIO);
+
+ sc->quirks = acpi_dev->quirks;
+
+ /* Allocate IRQ. */
+ rid = 0;
+ sc->irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
+ RF_ACTIVE);
+ if (sc->irq_res == NULL) {
+ device_printf(dev, "can't allocate IRQ\n");
+ return (ENOMEM);
+ }
+
+ rid = 0;
+ sc->mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY,
+ &rid, RF_ACTIVE);
+ if (sc->mem_res == NULL) {
+ device_printf(dev, "can't allocate memory resource for slot\n");
+ sdhci_acpi_detach(dev);
+ return (ENOMEM);
+ }
+
+ /* Intel Braswell eMMC 4.5.1 controller quirk */
+ if (strcmp(acpi_dev->hid, "80860F14") == 0 && acpi_dev->uid == 1 &&
+ SDHCI_READ_4(dev, &sc->slot, SDHCI_CAPABILITIES) == 0x446cc8b2 &&
+ SDHCI_READ_4(dev, &sc->slot, SDHCI_CAPABILITIES2) == 0x00000807)
+ sc->quirks |= SDHCI_QUIRK_DATA_TIMEOUT_1MHZ;
+ sc->quirks &= ~sdhci_quirk_clear;
+ sc->quirks |= sdhci_quirk_set;
+ sc->slot.quirks = sc->quirks;
+
+ err = sdhci_init_slot(dev, &sc->slot, 0);
+ if (err) {
+ device_printf(dev, "failed to init slot\n");
+ sdhci_acpi_detach(dev);
+ return (err);
+ }
+
+ /* Activate the interrupt */
+ err = bus_setup_intr(dev, sc->irq_res, INTR_TYPE_MISC | INTR_MPSAFE,
+ NULL, sdhci_acpi_intr, sc, &sc->intrhand);
+ if (err) {
+ device_printf(dev, "can't setup IRQ\n");
+ sdhci_acpi_detach(dev);
+ return (err);
+ }
+
+ /* Process cards detection. */
+ sdhci_start_slot(&sc->slot);
+
+ return (0);
+}
+
+static int
+sdhci_acpi_detach(device_t dev)
+{
+ struct sdhci_acpi_softc *sc = device_get_softc(dev);
+
+ if (sc->intrhand)
+ bus_teardown_intr(dev, sc->irq_res, sc->intrhand);
+ if (sc->irq_res)
+ bus_release_resource(dev, SYS_RES_IRQ,
+ rman_get_rid(sc->irq_res), sc->irq_res);
+
+ if (sc->mem_res) {
+ sdhci_cleanup_slot(&sc->slot);
+ bus_release_resource(dev, SYS_RES_MEMORY,
+ rman_get_rid(sc->mem_res), sc->mem_res);
+ }
+
+ return (0);
+}
+
+static int
+sdhci_acpi_shutdown(device_t dev)
+{
+
+ return (0);
+}
+
+static int
+sdhci_acpi_suspend(device_t dev)
+{
+ struct sdhci_acpi_softc *sc = device_get_softc(dev);
+ int err;
+
+ err = bus_generic_suspend(dev);
+ if (err)
+ return (err);
+ sdhci_generic_suspend(&sc->slot);
+ return (0);
+}
+
+static int
+sdhci_acpi_resume(device_t dev)
+{
+ struct sdhci_acpi_softc *sc = device_get_softc(dev);
+ int err;
+
+ sdhci_generic_resume(&sc->slot);
+ err = bus_generic_resume(dev);
+ if (err)
+ return (err);
+ return (0);
+}
+
+static void
+sdhci_acpi_intr(void *arg)
+{
+ struct sdhci_acpi_softc *sc = (struct sdhci_acpi_softc *)arg;
+
+ sdhci_generic_intr(&sc->slot);
+}
+
+static device_method_t sdhci_methods[] = {
+ /* device_if */
+ DEVMETHOD(device_probe, sdhci_acpi_probe),
+ DEVMETHOD(device_attach, sdhci_acpi_attach),
+ DEVMETHOD(device_detach, sdhci_acpi_detach),
+ DEVMETHOD(device_shutdown, sdhci_acpi_shutdown),
+ DEVMETHOD(device_suspend, sdhci_acpi_suspend),
+ DEVMETHOD(device_resume, sdhci_acpi_resume),
+
+ /* Bus interface */
+ DEVMETHOD(bus_read_ivar, sdhci_generic_read_ivar),
+ DEVMETHOD(bus_write_ivar, sdhci_generic_write_ivar),
+
+ /* mmcbr_if */
+ DEVMETHOD(mmcbr_update_ios, sdhci_generic_update_ios),
+ DEVMETHOD(mmcbr_switch_vccq, sdhci_generic_switch_vccq),
+ DEVMETHOD(mmcbr_tune, sdhci_generic_tune),
+ DEVMETHOD(mmcbr_retune, sdhci_generic_retune),
+ DEVMETHOD(mmcbr_request, sdhci_generic_request),
+ DEVMETHOD(mmcbr_get_ro, sdhci_generic_get_ro),
+ DEVMETHOD(mmcbr_acquire_host, sdhci_generic_acquire_host),
+ DEVMETHOD(mmcbr_release_host, sdhci_generic_release_host),
+
+ /* SDHCI accessors */
+ DEVMETHOD(sdhci_read_1, sdhci_acpi_read_1),
+ DEVMETHOD(sdhci_read_2, sdhci_acpi_read_2),
+ DEVMETHOD(sdhci_read_4, sdhci_acpi_read_4),
+ DEVMETHOD(sdhci_read_multi_4, sdhci_acpi_read_multi_4),
+ DEVMETHOD(sdhci_write_1, sdhci_acpi_write_1),
+ DEVMETHOD(sdhci_write_2, sdhci_acpi_write_2),
+ DEVMETHOD(sdhci_write_4, sdhci_acpi_write_4),
+ DEVMETHOD(sdhci_write_multi_4, sdhci_acpi_write_multi_4),
+ DEVMETHOD(sdhci_set_uhs_timing, sdhci_generic_set_uhs_timing),
+
+ DEVMETHOD_END
+};
+
+static driver_t sdhci_acpi_driver = {
+ "sdhci_acpi",
+ sdhci_methods,
+ sizeof(struct sdhci_acpi_softc),
+};
+static devclass_t sdhci_acpi_devclass;
+
+DRIVER_MODULE(sdhci_acpi, acpi, sdhci_acpi_driver, sdhci_acpi_devclass, NULL,
+ NULL);
+MODULE_DEPEND(sdhci_acpi, sdhci, 1, 1, 1);
+MMC_DECLARE_BRIDGE(sdhci_acpi);
Property changes on: trunk/sys/dev/sdhci/sdhci_acpi.c
___________________________________________________________________
Added: svn:eol-style
## -0,0 +1 ##
+native
\ No newline at end of property
Added: svn:keywords
## -0,0 +1 ##
+MidnightBSD=%H
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+text/plain
\ No newline at end of property
Added: trunk/sys/dev/sdhci/sdhci_fdt.c
===================================================================
--- trunk/sys/dev/sdhci/sdhci_fdt.c (rev 0)
+++ trunk/sys/dev/sdhci/sdhci_fdt.c 2018-05-27 23:15:22 UTC (rev 10073)
@@ -0,0 +1,310 @@
+/* $MidnightBSD$ */
+/*-
+ * Copyright (c) 2012 Thomas Skibo
+ * Copyright (c) 2008 Alexander Motin <mav at FreeBSD.org>
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+ * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+ * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/* Generic driver to attach sdhci controllers on simplebus.
+ * Derived mainly from sdhci_pci.c
+ */
+
+#include <sys/cdefs.h>
+__FBSDID("$FreeBSD: stable/10/sys/dev/sdhci/sdhci_fdt.c 318198 2017-05-11 21:01:02Z marius $");
+
+#include <sys/param.h>
+#include <sys/systm.h>
+#include <sys/bus.h>
+#include <sys/kernel.h>
+#include <sys/lock.h>
+#include <sys/module.h>
+#include <sys/mutex.h>
+#include <sys/resource.h>
+#include <sys/rman.h>
+#include <sys/sysctl.h>
+#include <sys/taskqueue.h>
+
+#include <machine/bus.h>
+#include <machine/resource.h>
+
+#include <dev/fdt/fdt_common.h>
+#include <dev/ofw/ofw_bus.h>
+#include <dev/ofw/ofw_bus_subr.h>
+
+#include <dev/mmc/bridge.h>
+
+#include <dev/sdhci/sdhci.h>
+
+#include "mmcbr_if.h"
+#include "sdhci_if.h"
+
+#define MAX_SLOTS 6
+
+struct sdhci_fdt_softc {
+ device_t dev; /* Controller device */
+ u_int quirks; /* Chip specific quirks */
+ u_int caps; /* If we override SDHCI_CAPABILITIES */
+ uint32_t max_clk; /* Max possible freq */
+ struct resource *irq_res; /* IRQ resource */
+ void *intrhand; /* Interrupt handle */
+
+ int num_slots; /* Number of slots on this controller*/
+ struct sdhci_slot slots[MAX_SLOTS];
+ struct resource *mem_res[MAX_SLOTS]; /* Memory resource */
+};
+
+static uint8_t
+sdhci_fdt_read_1(device_t dev, struct sdhci_slot *slot, bus_size_t off)
+{
+ struct sdhci_fdt_softc *sc = device_get_softc(dev);
+
+ return (bus_read_1(sc->mem_res[slot->num], off));
+}
+
+static void
+sdhci_fdt_write_1(device_t dev, struct sdhci_slot *slot, bus_size_t off,
+ uint8_t val)
+{
+ struct sdhci_fdt_softc *sc = device_get_softc(dev);
+
+ bus_write_1(sc->mem_res[slot->num], off, val);
+}
+
+static uint16_t
+sdhci_fdt_read_2(device_t dev, struct sdhci_slot *slot, bus_size_t off)
+{
+ struct sdhci_fdt_softc *sc = device_get_softc(dev);
+
+ return (bus_read_2(sc->mem_res[slot->num], off));
+}
+
+static void
+sdhci_fdt_write_2(device_t dev, struct sdhci_slot *slot, bus_size_t off,
+ uint16_t val)
+{
+ struct sdhci_fdt_softc *sc = device_get_softc(dev);
+
+ bus_write_2(sc->mem_res[slot->num], off, val);
+}
+
+static uint32_t
+sdhci_fdt_read_4(device_t dev, struct sdhci_slot *slot, bus_size_t off)
+{
+ struct sdhci_fdt_softc *sc = device_get_softc(dev);
+
+ return (bus_read_4(sc->mem_res[slot->num], off));
+}
+
+static void
+sdhci_fdt_write_4(device_t dev, struct sdhci_slot *slot, bus_size_t off,
+ uint32_t val)
+{
+ struct sdhci_fdt_softc *sc = device_get_softc(dev);
+
+ bus_write_4(sc->mem_res[slot->num], off, val);
+}
+
+static void
+sdhci_fdt_read_multi_4(device_t dev, struct sdhci_slot *slot,
+ bus_size_t off, uint32_t *data, bus_size_t count)
+{
+ struct sdhci_fdt_softc *sc = device_get_softc(dev);
+
+ bus_read_multi_4(sc->mem_res[slot->num], off, data, count);
+}
+
+static void
+sdhci_fdt_write_multi_4(device_t dev, struct sdhci_slot *slot,
+ bus_size_t off, uint32_t *data, bus_size_t count)
+{
+ struct sdhci_fdt_softc *sc = device_get_softc(dev);
+
+ bus_write_multi_4(sc->mem_res[slot->num], off, data, count);
+}
+
+static void
+sdhci_fdt_intr(void *arg)
+{
+ struct sdhci_fdt_softc *sc = (struct sdhci_fdt_softc *)arg;
+ int i;
+
+ for (i = 0; i < sc->num_slots; i++)
+ sdhci_generic_intr(&sc->slots[i]);
+}
+
+static int
+sdhci_fdt_probe(device_t dev)
+{
+ struct sdhci_fdt_softc *sc = device_get_softc(dev);
+ phandle_t node;
+ pcell_t cid;
+
+ sc->quirks = 0;
+ sc->num_slots = 1;
+ sc->max_clk = 0;
+
+ if (!ofw_bus_status_okay(dev))
+ return (ENXIO);
+
+ if (ofw_bus_is_compatible(dev, "sdhci_generic")) {
+ device_set_desc(dev, "generic fdt SDHCI controller");
+ } else if (ofw_bus_is_compatible(dev, "xlnx,zy7_sdhci")) {
+ sc->quirks = SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK;
+ device_set_desc(dev, "Zynq-7000 generic fdt SDHCI controller");
+ } else
+ return (ENXIO);
+
+ node = ofw_bus_get_node(dev);
+
+ /* Allow dts to patch quirks, slots, and max-frequency. */
+ if ((OF_getencprop(node, "quirks", &cid, sizeof(cid))) > 0)
+ sc->quirks = cid;
+ if ((OF_getencprop(node, "num-slots", &cid, sizeof(cid))) > 0)
+ sc->num_slots = cid;
+ if ((OF_getencprop(node, "max-frequency", &cid, sizeof(cid))) > 0)
+ sc->max_clk = cid;
+
+ return (0);
+}
+
+static int
+sdhci_fdt_attach(device_t dev)
+{
+ struct sdhci_fdt_softc *sc = device_get_softc(dev);
+ struct sdhci_slot *slot;
+ int err, slots, rid, i;
+
+ sc->dev = dev;
+
+ /* Allocate IRQ. */
+ rid = 0;
+ sc->irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
+ RF_ACTIVE);
+ if (sc->irq_res == NULL) {
+ device_printf(dev, "Can't allocate IRQ\n");
+ return (ENOMEM);
+ }
+
+ /* Scan all slots. */
+ slots = sc->num_slots; /* number of slots determined in probe(). */
+ sc->num_slots = 0;
+ for (i = 0; i < slots; i++) {
+ slot = &sc->slots[sc->num_slots];
+
+ /* Allocate memory. */
+ rid = 0;
+ sc->mem_res[i] = bus_alloc_resource_any(dev, SYS_RES_MEMORY,
+ &rid, RF_ACTIVE);
+ if (sc->mem_res[i] == NULL) {
+ device_printf(dev,
+ "Can't allocate memory for slot %d\n", i);
+ continue;
+ }
+
+ slot->quirks = sc->quirks;
+ slot->caps = sc->caps;
+ slot->max_clk = sc->max_clk;
+
+ if (sdhci_init_slot(dev, slot, i) != 0)
+ continue;
+
+ sc->num_slots++;
+ }
+ device_printf(dev, "%d slot(s) allocated\n", sc->num_slots);
+
+ /* Activate the interrupt */
+ err = bus_setup_intr(dev, sc->irq_res, INTR_TYPE_MISC | INTR_MPSAFE,
+ NULL, sdhci_fdt_intr, sc, &sc->intrhand);
+ if (err) {
+ device_printf(dev, "Cannot setup IRQ\n");
+ return (err);
+ }
+
+ /* Process cards detection. */
+ for (i = 0; i < sc->num_slots; i++)
+ sdhci_start_slot(&sc->slots[i]);
+
+ return (0);
+}
+
+static int
+sdhci_fdt_detach(device_t dev)
+{
+ struct sdhci_fdt_softc *sc = device_get_softc(dev);
+ int i;
+
+ bus_generic_detach(dev);
+ bus_teardown_intr(dev, sc->irq_res, sc->intrhand);
+ bus_release_resource(dev, SYS_RES_IRQ, rman_get_rid(sc->irq_res),
+ sc->irq_res);
+
+ for (i = 0; i < sc->num_slots; i++) {
+ sdhci_cleanup_slot(&sc->slots[i]);
+ bus_release_resource(dev, SYS_RES_MEMORY,
+ rman_get_rid(sc->mem_res[i]), sc->mem_res[i]);
+ }
+
+ return (0);
+}
+
+static device_method_t sdhci_fdt_methods[] = {
+ /* device_if */
+ DEVMETHOD(device_probe, sdhci_fdt_probe),
+ DEVMETHOD(device_attach, sdhci_fdt_attach),
+ DEVMETHOD(device_detach, sdhci_fdt_detach),
+
+ /* Bus interface */
+ DEVMETHOD(bus_read_ivar, sdhci_generic_read_ivar),
+ DEVMETHOD(bus_write_ivar, sdhci_generic_write_ivar),
+
+ /* mmcbr_if */
+ DEVMETHOD(mmcbr_update_ios, sdhci_generic_update_ios),
+ DEVMETHOD(mmcbr_request, sdhci_generic_request),
+ DEVMETHOD(mmcbr_get_ro, sdhci_generic_get_ro),
+ DEVMETHOD(mmcbr_acquire_host, sdhci_generic_acquire_host),
+ DEVMETHOD(mmcbr_release_host, sdhci_generic_release_host),
+
+ /* SDHCI registers accessors */
+ DEVMETHOD(sdhci_read_1, sdhci_fdt_read_1),
+ DEVMETHOD(sdhci_read_2, sdhci_fdt_read_2),
+ DEVMETHOD(sdhci_read_4, sdhci_fdt_read_4),
+ DEVMETHOD(sdhci_read_multi_4, sdhci_fdt_read_multi_4),
+ DEVMETHOD(sdhci_write_1, sdhci_fdt_write_1),
+ DEVMETHOD(sdhci_write_2, sdhci_fdt_write_2),
+ DEVMETHOD(sdhci_write_4, sdhci_fdt_write_4),
+ DEVMETHOD(sdhci_write_multi_4, sdhci_fdt_write_multi_4),
+
+ DEVMETHOD_END
+};
+
+static driver_t sdhci_fdt_driver = {
+ "sdhci_fdt",
+ sdhci_fdt_methods,
+ sizeof(struct sdhci_fdt_softc),
+};
+static devclass_t sdhci_fdt_devclass;
+
+DRIVER_MODULE(sdhci_fdt, simplebus, sdhci_fdt_driver, sdhci_fdt_devclass,
+ NULL, NULL);
+MODULE_DEPEND(sdhci_fdt, sdhci, 1, 1, 1);
+MMC_DECLARE_BRIDGE(sdhci_fdt);
Property changes on: trunk/sys/dev/sdhci/sdhci_fdt.c
___________________________________________________________________
Added: svn:eol-style
## -0,0 +1 ##
+native
\ No newline at end of property
Added: svn:keywords
## -0,0 +1 ##
+MidnightBSD=%H
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+text/plain
\ No newline at end of property
Added: trunk/sys/dev/sdhci/sdhci_if.m
===================================================================
--- trunk/sys/dev/sdhci/sdhci_if.m (rev 0)
+++ trunk/sys/dev/sdhci/sdhci_if.m 2018-05-27 23:15:22 UTC (rev 10073)
@@ -0,0 +1,168 @@
+/* $MidnightBSD$ */
+#-
+# Copyright (c) 2006 M. Warner Losh
+# All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions
+# are met:
+# 1. Redistributions of source code must retain the above copyright
+# notice, this list of conditions and the following disclaimer.
+# 2. Redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in the
+# documentation and/or other materials provided with the distribution.
+#
+# THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+# ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+# IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+# ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+# FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+# DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+# OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+# HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+# LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+# OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+# SUCH DAMAGE.
+#
+# Portions of this software may have been developed with reference to
+# the SD Simplified Specification. The following disclaimer may apply:
+#
+# The following conditions apply to the release of the simplified
+# specification ("Simplified Specification") by the SD Card Association and
+# the SD Group. The Simplified Specification is a subset of the complete SD
+# Specification which is owned by the SD Card Association and the SD
+# Group. This Simplified Specification is provided on a non-confidential
+# basis subject to the disclaimers below. Any implementation of the
+# Simplified Specification may require a license from the SD Card
+# Association, SD Group, SD-3C LLC or other third parties.
+#
+# Disclaimers:
+#
+# The information contained in the Simplified Specification is presented only
+# as a standard specification for SD Cards and SD Host/Ancillary products and
+# is provided "AS-IS" without any representations or warranties of any
+# kind. No responsibility is assumed by the SD Group, SD-3C LLC or the SD
+# Card Association for any damages, any infringements of patents or other
+# right of the SD Group, SD-3C LLC, the SD Card Association or any third
+# parties, which may result from its use. No license is granted by
+# implication, estoppel or otherwise under any patent or other rights of the
+# SD Group, SD-3C LLC, the SD Card Association or any third party. Nothing
+# herein shall be construed as an obligation by the SD Group, the SD-3C LLC
+# or the SD Card Association to disclose or distribute any technical
+# information, know-how or other confidential information to any third party.
+#
+# $FreeBSD: stable/10/sys/dev/sdhci/sdhci_if.m 322120 2017-08-06 16:07:34Z marius $
+#
+
+#
+# This is the set of callbacks that mmc bridges call into the bus, or
+# that mmc/sd card drivers call to make requests.
+#
+
+#include <sys/lock.h>
+#include <sys/mutex.h>
+#include <sys/types.h>
+#include <sys/sysctl.h>
+#include <sys/taskqueue.h>
+
+#include <machine/bus.h>
+
+#include <dev/mmc/bridge.h>
+#include <dev/sdhci/sdhci.h>
+
+CODE {
+ static void
+ null_set_uhs_timing(device_t brdev __unused,
+ struct sdhci_slot *slot __unused)
+ {
+
+ }
+}
+
+INTERFACE sdhci;
+
+METHOD uint8_t read_1 {
+ device_t brdev;
+ struct sdhci_slot *slot;
+ bus_size_t off;
+}
+
+METHOD uint16_t read_2 {
+ device_t brdev;
+ struct sdhci_slot *slot;
+ bus_size_t off;
+}
+
+METHOD uint32_t read_4 {
+ device_t brdev;
+ struct sdhci_slot *slot;
+ bus_size_t off;
+}
+
+METHOD void read_multi_4 {
+ device_t brdev;
+ struct sdhci_slot *slot;
+ bus_size_t off;
+ uint32_t *data;
+ bus_size_t count;
+}
+
+METHOD void write_1 {
+ device_t brdev;
+ struct sdhci_slot *slot;
+ bus_size_t off;
+ uint8_t val;
+}
+
+METHOD void write_2 {
+ device_t brdev;
+ struct sdhci_slot *slot;
+ bus_size_t off;
+ uint16_t val;
+}
+
+METHOD void write_4 {
+ device_t brdev;
+ struct sdhci_slot *slot;
+ bus_size_t off;
+ uint32_t val;
+}
+
+METHOD void write_multi_4 {
+ device_t brdev;
+ struct sdhci_slot *slot;
+ bus_size_t off;
+ uint32_t *data;
+ bus_size_t count;
+}
+
+METHOD int platform_will_handle {
+ device_t brdev;
+ struct sdhci_slot *slot;
+}
+
+METHOD void platform_start_transfer {
+ device_t brdev;
+ struct sdhci_slot *slot;
+ uint32_t *intmask;
+}
+
+METHOD void platform_finish_transfer {
+ device_t brdev;
+ struct sdhci_slot *slot;
+}
+
+METHOD uint32_t min_freq {
+ device_t brdev;
+ struct sdhci_slot *slot;
+} DEFAULT sdhci_generic_min_freq;
+
+METHOD bool get_card_present {
+ device_t brdev;
+ struct sdhci_slot *slot;
+} DEFAULT sdhci_generic_get_card_present;
+
+METHOD void set_uhs_timing {
+ device_t brdev;
+ struct sdhci_slot *slot;
+} DEFAULT null_set_uhs_timing;
Property changes on: trunk/sys/dev/sdhci/sdhci_if.m
___________________________________________________________________
Added: svn:keywords
## -0,0 +1 ##
+MidnightBSD=%H
\ No newline at end of property
Added: trunk/sys/dev/sdhci/sdhci_pci.c
===================================================================
--- trunk/sys/dev/sdhci/sdhci_pci.c (rev 0)
+++ trunk/sys/dev/sdhci/sdhci_pci.c 2018-05-27 23:15:22 UTC (rev 10073)
@@ -0,0 +1,527 @@
+/* $MidnightBSD$ */
+/*-
+ * Copyright (c) 2008 Alexander Motin <mav at FreeBSD.org>
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+ * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+ * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <sys/cdefs.h>
+__FBSDID("$FreeBSD: stable/10/sys/dev/sdhci/sdhci_pci.c 331033 2018-03-15 22:51:13Z marius $");
+
+#include <sys/param.h>
+#include <sys/systm.h>
+#include <sys/bus.h>
+#include <sys/kernel.h>
+#include <sys/lock.h>
+#include <sys/module.h>
+#include <sys/mutex.h>
+#include <sys/resource.h>
+#include <sys/rman.h>
+#include <sys/sysctl.h>
+#include <sys/taskqueue.h>
+
+#include <dev/pci/pcireg.h>
+#include <dev/pci/pcivar.h>
+
+#include <machine/bus.h>
+#include <machine/resource.h>
+
+#include <dev/mmc/bridge.h>
+
+#include <dev/sdhci/sdhci.h>
+
+#include "mmcbr_if.h"
+#include "sdhci_if.h"
+
+/*
+ * PCI registers
+ */
+#define PCI_SDHCI_IFPIO 0x00
+#define PCI_SDHCI_IFDMA 0x01
+#define PCI_SDHCI_IFVENDOR 0x02
+
+#define PCI_SLOT_INFO 0x40 /* 8 bits */
+#define PCI_SLOT_INFO_SLOTS(x) (((x >> 4) & 7) + 1)
+#define PCI_SLOT_INFO_FIRST_BAR(x) ((x) & 7)
+
+/*
+ * RICOH specific PCI registers
+ */
+#define SDHC_PCI_MODE_KEY 0xf9
+#define SDHC_PCI_MODE 0x150
+#define SDHC_PCI_MODE_SD20 0x10
+#define SDHC_PCI_BASE_FREQ_KEY 0xfc
+#define SDHC_PCI_BASE_FREQ 0xe1
+
+static const struct sdhci_device {
+ uint32_t model;
+ uint16_t subvendor;
+ const char *desc;
+ u_int quirks;
+} sdhci_devices[] = {
+ { 0x08221180, 0xffff, "RICOH R5C822 SD",
+ SDHCI_QUIRK_FORCE_DMA },
+ { 0xe8221180, 0xffff, "RICOH R5CE822 SD",
+ SDHCI_QUIRK_FORCE_DMA |
+ SDHCI_QUIRK_LOWER_FREQUENCY },
+ { 0xe8231180, 0xffff, "RICOH R5CE823 SD",
+ SDHCI_QUIRK_LOWER_FREQUENCY },
+ { 0x8034104c, 0xffff, "TI XX21/XX11 SD",
+ SDHCI_QUIRK_FORCE_DMA },
+ { 0x05501524, 0xffff, "ENE CB712 SD",
+ SDHCI_QUIRK_BROKEN_TIMINGS },
+ { 0x05511524, 0xffff, "ENE CB712 SD 2",
+ SDHCI_QUIRK_BROKEN_TIMINGS },
+ { 0x07501524, 0xffff, "ENE CB714 SD",
+ SDHCI_QUIRK_RESET_ON_IOS |
+ SDHCI_QUIRK_BROKEN_TIMINGS },
+ { 0x07511524, 0xffff, "ENE CB714 SD 2",
+ SDHCI_QUIRK_RESET_ON_IOS |
+ SDHCI_QUIRK_BROKEN_TIMINGS },
+ { 0x410111ab, 0xffff, "Marvell CaFe SD",
+ SDHCI_QUIRK_INCR_TIMEOUT_CONTROL },
+ { 0x2381197B, 0xffff, "JMicron JMB38X SD",
+ SDHCI_QUIRK_32BIT_DMA_SIZE |
+ SDHCI_QUIRK_RESET_AFTER_REQUEST },
+ { 0x16bc14e4, 0xffff, "Broadcom BCM577xx SDXC/MMC Card Reader",
+ SDHCI_QUIRK_BCM577XX_400KHZ_CLKSRC },
+ { 0x0f148086, 0xffff, "Intel Bay Trail eMMC 4.5 Controller",
+ SDHCI_QUIRK_INTEL_POWER_UP_RESET |
+ SDHCI_QUIRK_WAIT_WHILE_BUSY |
+ SDHCI_QUIRK_MMC_DDR52 |
+ SDHCI_QUIRK_CAPS_BIT63_FOR_MMC_HS400 |
+ SDHCI_QUIRK_PRESET_VALUE_BROKEN},
+ { 0x0f158086, 0xffff, "Intel Bay Trail SDXC Controller",
+ SDHCI_QUIRK_WAIT_WHILE_BUSY |
+ SDHCI_QUIRK_PRESET_VALUE_BROKEN },
+ { 0x0f508086, 0xffff, "Intel Bay Trail eMMC 4.5 Controller",
+ SDHCI_QUIRK_INTEL_POWER_UP_RESET |
+ SDHCI_QUIRK_WAIT_WHILE_BUSY |
+ SDHCI_QUIRK_MMC_DDR52 |
+ SDHCI_QUIRK_CAPS_BIT63_FOR_MMC_HS400 |
+ SDHCI_QUIRK_PRESET_VALUE_BROKEN },
+ { 0x19db8086, 0xffff, "Intel Denverton eMMC 5.0 Controller",
+ SDHCI_QUIRK_INTEL_POWER_UP_RESET |
+ SDHCI_QUIRK_WAIT_WHILE_BUSY |
+ SDHCI_QUIRK_MMC_DDR52 |
+ SDHCI_QUIRK_CAPS_BIT63_FOR_MMC_HS400 |
+ SDHCI_QUIRK_PRESET_VALUE_BROKEN },
+ { 0x22948086, 0xffff, "Intel Braswell eMMC 4.5.1 Controller",
+ SDHCI_QUIRK_DATA_TIMEOUT_1MHZ |
+ SDHCI_QUIRK_INTEL_POWER_UP_RESET |
+ SDHCI_QUIRK_WAIT_WHILE_BUSY |
+ SDHCI_QUIRK_MMC_DDR52 |
+ SDHCI_QUIRK_CAPS_BIT63_FOR_MMC_HS400 |
+ SDHCI_QUIRK_PRESET_VALUE_BROKEN },
+ { 0x22968086, 0xffff, "Intel Braswell SDXC Controller",
+ SDHCI_QUIRK_WAIT_WHILE_BUSY |
+ SDHCI_QUIRK_PRESET_VALUE_BROKEN },
+ { 0x5aca8086, 0xffff, "Intel Apollo Lake SDXC Controller",
+ SDHCI_QUIRK_BROKEN_DMA | /* APL18 erratum */
+ SDHCI_QUIRK_WAIT_WHILE_BUSY |
+ SDHCI_QUIRK_PRESET_VALUE_BROKEN },
+ { 0x5acc8086, 0xffff, "Intel Apollo Lake eMMC 5.0 Controller",
+ SDHCI_QUIRK_BROKEN_DMA | /* APL18 erratum */
+ SDHCI_QUIRK_INTEL_POWER_UP_RESET |
+ SDHCI_QUIRK_WAIT_WHILE_BUSY |
+ SDHCI_QUIRK_MMC_DDR52 |
+ SDHCI_QUIRK_CAPS_BIT63_FOR_MMC_HS400 |
+ SDHCI_QUIRK_PRESET_VALUE_BROKEN },
+ { 0, 0xffff, NULL,
+ 0 }
+};
+
+struct sdhci_pci_softc {
+ u_int quirks; /* Chip specific quirks */
+ struct resource *irq_res; /* IRQ resource */
+ void *intrhand; /* Interrupt handle */
+
+ int num_slots; /* Number of slots on this controller */
+ struct sdhci_slot slots[6];
+ struct resource *mem_res[6]; /* Memory resource */
+ uint8_t cfg_freq; /* Saved frequency */
+ uint8_t cfg_mode; /* Saved mode */
+};
+
+static int sdhci_enable_msi = 1;
+TUNABLE_INT("hw.sdhci.enable_msi", &sdhci_enable_msi);
+SYSCTL_INT(_hw_sdhci, OID_AUTO, enable_msi, CTLFLAG_RDTUN, &sdhci_enable_msi,
+ 0, "Enable MSI interrupts");
+
+static uint8_t
+sdhci_pci_read_1(device_t dev, struct sdhci_slot *slot __unused, bus_size_t off)
+{
+ struct sdhci_pci_softc *sc = device_get_softc(dev);
+
+ bus_barrier(sc->mem_res[slot->num], 0, 0xFF,
+ BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE);
+ return bus_read_1(sc->mem_res[slot->num], off);
+}
+
+static void
+sdhci_pci_write_1(device_t dev, struct sdhci_slot *slot __unused,
+ bus_size_t off, uint8_t val)
+{
+ struct sdhci_pci_softc *sc = device_get_softc(dev);
+
+ bus_barrier(sc->mem_res[slot->num], 0, 0xFF,
+ BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE);
+ bus_write_1(sc->mem_res[slot->num], off, val);
+}
+
+static uint16_t
+sdhci_pci_read_2(device_t dev, struct sdhci_slot *slot __unused, bus_size_t off)
+{
+ struct sdhci_pci_softc *sc = device_get_softc(dev);
+
+ bus_barrier(sc->mem_res[slot->num], 0, 0xFF,
+ BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE);
+ return bus_read_2(sc->mem_res[slot->num], off);
+}
+
+static void
+sdhci_pci_write_2(device_t dev, struct sdhci_slot *slot __unused,
+ bus_size_t off, uint16_t val)
+{
+ struct sdhci_pci_softc *sc = device_get_softc(dev);
+
+ bus_barrier(sc->mem_res[slot->num], 0, 0xFF,
+ BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE);
+ bus_write_2(sc->mem_res[slot->num], off, val);
+}
+
+static uint32_t
+sdhci_pci_read_4(device_t dev, struct sdhci_slot *slot __unused, bus_size_t off)
+{
+ struct sdhci_pci_softc *sc = device_get_softc(dev);
+
+ bus_barrier(sc->mem_res[slot->num], 0, 0xFF,
+ BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE);
+ return bus_read_4(sc->mem_res[slot->num], off);
+}
+
+static void
+sdhci_pci_write_4(device_t dev, struct sdhci_slot *slot __unused,
+ bus_size_t off, uint32_t val)
+{
+ struct sdhci_pci_softc *sc = device_get_softc(dev);
+
+ bus_barrier(sc->mem_res[slot->num], 0, 0xFF,
+ BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE);
+ bus_write_4(sc->mem_res[slot->num], off, val);
+}
+
+static void
+sdhci_pci_read_multi_4(device_t dev, struct sdhci_slot *slot __unused,
+ bus_size_t off, uint32_t *data, bus_size_t count)
+{
+ struct sdhci_pci_softc *sc = device_get_softc(dev);
+
+ bus_read_multi_stream_4(sc->mem_res[slot->num], off, data, count);
+}
+
+static void
+sdhci_pci_write_multi_4(device_t dev, struct sdhci_slot *slot __unused,
+ bus_size_t off, uint32_t *data, bus_size_t count)
+{
+ struct sdhci_pci_softc *sc = device_get_softc(dev);
+
+ bus_write_multi_stream_4(sc->mem_res[slot->num], off, data, count);
+}
+
+static void sdhci_pci_intr(void *arg);
+
+static void
+sdhci_lower_frequency(device_t dev)
+{
+ struct sdhci_pci_softc *sc = device_get_softc(dev);
+
+ /*
+ * Enable SD2.0 mode.
+ * NB: for RICOH R5CE823, this changes the PCI device ID to 0xe822.
+ */
+ pci_write_config(dev, SDHC_PCI_MODE_KEY, 0xfc, 1);
+ sc->cfg_mode = pci_read_config(dev, SDHC_PCI_MODE, 1);
+ pci_write_config(dev, SDHC_PCI_MODE, SDHC_PCI_MODE_SD20, 1);
+ pci_write_config(dev, SDHC_PCI_MODE_KEY, 0x00, 1);
+
+ /*
+ * Some SD/MMC cards don't work with the default base
+ * clock frequency of 200 MHz. Lower it to 50 MHz.
+ */
+ pci_write_config(dev, SDHC_PCI_BASE_FREQ_KEY, 0x01, 1);
+ sc->cfg_freq = pci_read_config(dev, SDHC_PCI_BASE_FREQ, 1);
+ pci_write_config(dev, SDHC_PCI_BASE_FREQ, 50, 1);
+ pci_write_config(dev, SDHC_PCI_BASE_FREQ_KEY, 0x00, 1);
+}
+
+static void
+sdhci_restore_frequency(device_t dev)
+{
+ struct sdhci_pci_softc *sc = device_get_softc(dev);
+
+ /* Restore mode. */
+ pci_write_config(dev, SDHC_PCI_MODE_KEY, 0xfc, 1);
+ pci_write_config(dev, SDHC_PCI_MODE, sc->cfg_mode, 1);
+ pci_write_config(dev, SDHC_PCI_MODE_KEY, 0x00, 1);
+
+ /* Restore frequency. */
+ pci_write_config(dev, SDHC_PCI_BASE_FREQ_KEY, 0x01, 1);
+ pci_write_config(dev, SDHC_PCI_BASE_FREQ, sc->cfg_freq, 1);
+ pci_write_config(dev, SDHC_PCI_BASE_FREQ_KEY, 0x00, 1);
+}
+
+static int
+sdhci_pci_probe(device_t dev)
+{
+ uint32_t model;
+ uint16_t subvendor;
+ uint8_t class, subclass;
+ int i, result;
+
+ model = (uint32_t)pci_get_device(dev) << 16;
+ model |= (uint32_t)pci_get_vendor(dev) & 0x0000ffff;
+ subvendor = pci_get_subvendor(dev);
+ class = pci_get_class(dev);
+ subclass = pci_get_subclass(dev);
+
+ result = ENXIO;
+ for (i = 0; sdhci_devices[i].model != 0; i++) {
+ if (sdhci_devices[i].model == model &&
+ (sdhci_devices[i].subvendor == 0xffff ||
+ sdhci_devices[i].subvendor == subvendor)) {
+ device_set_desc(dev, sdhci_devices[i].desc);
+ result = BUS_PROBE_DEFAULT;
+ break;
+ }
+ }
+ if (result == ENXIO && class == PCIC_BASEPERIPH &&
+ subclass == PCIS_BASEPERIPH_SDHC) {
+ device_set_desc(dev, "Generic SD HCI");
+ result = BUS_PROBE_GENERIC;
+ }
+
+ return (result);
+}
+
+static int
+sdhci_pci_attach(device_t dev)
+{
+ struct sdhci_pci_softc *sc = device_get_softc(dev);
+ struct sdhci_slot *slot;
+ uint32_t model;
+ uint16_t subvendor;
+ int bar, err, rid, slots, i;
+
+ model = (uint32_t)pci_get_device(dev) << 16;
+ model |= (uint32_t)pci_get_vendor(dev) & 0x0000ffff;
+ subvendor = pci_get_subvendor(dev);
+ /* Apply chip specific quirks. */
+ for (i = 0; sdhci_devices[i].model != 0; i++) {
+ if (sdhci_devices[i].model == model &&
+ (sdhci_devices[i].subvendor == 0xffff ||
+ sdhci_devices[i].subvendor == subvendor)) {
+ sc->quirks = sdhci_devices[i].quirks;
+ break;
+ }
+ }
+ sc->quirks &= ~sdhci_quirk_clear;
+ sc->quirks |= sdhci_quirk_set;
+
+ /* Some controllers need to be bumped into the right mode. */
+ if (sc->quirks & SDHCI_QUIRK_LOWER_FREQUENCY)
+ sdhci_lower_frequency(dev);
+ /* Read slots info from PCI registers. */
+ slots = pci_read_config(dev, PCI_SLOT_INFO, 1);
+ bar = PCI_SLOT_INFO_FIRST_BAR(slots);
+ slots = PCI_SLOT_INFO_SLOTS(slots);
+ if (slots > 6 || bar > 5) {
+ device_printf(dev, "Incorrect slots information (%d, %d).\n",
+ slots, bar);
+ return (EINVAL);
+ }
+ /* Allocate IRQ. */
+ i = 1;
+ rid = 0;
+ if (sdhci_enable_msi != 0 && pci_alloc_msi(dev, &i) == 0)
+ rid = 1;
+ sc->irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
+ RF_ACTIVE | (rid != 0 ? 0 : RF_SHAREABLE));
+ if (sc->irq_res == NULL) {
+ device_printf(dev, "Can't allocate IRQ\n");
+ pci_release_msi(dev);
+ return (ENOMEM);
+ }
+ /* Scan all slots. */
+ for (i = 0; i < slots; i++) {
+ slot = &sc->slots[sc->num_slots];
+
+ /* Allocate memory. */
+ rid = PCIR_BAR(bar + i);
+ sc->mem_res[i] = bus_alloc_resource_any(dev, SYS_RES_MEMORY,
+ &rid, RF_ACTIVE);
+ if (sc->mem_res[i] == NULL) {
+ device_printf(dev,
+ "Can't allocate memory for slot %d\n", i);
+ continue;
+ }
+
+ slot->quirks = sc->quirks;
+
+ if (sdhci_init_slot(dev, slot, i) != 0)
+ continue;
+
+ sc->num_slots++;
+ }
+ device_printf(dev, "%d slot(s) allocated\n", sc->num_slots);
+ /* Activate the interrupt */
+ err = bus_setup_intr(dev, sc->irq_res, INTR_TYPE_MISC | INTR_MPSAFE,
+ NULL, sdhci_pci_intr, sc, &sc->intrhand);
+ if (err)
+ device_printf(dev, "Can't setup IRQ\n");
+ pci_enable_busmaster(dev);
+ /* Process cards detection. */
+ for (i = 0; i < sc->num_slots; i++)
+ sdhci_start_slot(&sc->slots[i]);
+
+ return (0);
+}
+
+static int
+sdhci_pci_detach(device_t dev)
+{
+ struct sdhci_pci_softc *sc = device_get_softc(dev);
+ int i;
+
+ bus_teardown_intr(dev, sc->irq_res, sc->intrhand);
+ bus_release_resource(dev, SYS_RES_IRQ,
+ rman_get_rid(sc->irq_res), sc->irq_res);
+ pci_release_msi(dev);
+
+ for (i = 0; i < sc->num_slots; i++) {
+ sdhci_cleanup_slot(&sc->slots[i]);
+ bus_release_resource(dev, SYS_RES_MEMORY,
+ rman_get_rid(sc->mem_res[i]), sc->mem_res[i]);
+ }
+ if (sc->quirks & SDHCI_QUIRK_LOWER_FREQUENCY)
+ sdhci_restore_frequency(dev);
+ return (0);
+}
+
+static int
+sdhci_pci_shutdown(device_t dev)
+{
+ struct sdhci_pci_softc *sc = device_get_softc(dev);
+
+ if (sc->quirks & SDHCI_QUIRK_LOWER_FREQUENCY)
+ sdhci_restore_frequency(dev);
+ return (0);
+}
+
+static int
+sdhci_pci_suspend(device_t dev)
+{
+ struct sdhci_pci_softc *sc = device_get_softc(dev);
+ int i, err;
+
+ err = bus_generic_suspend(dev);
+ if (err)
+ return (err);
+ for (i = 0; i < sc->num_slots; i++)
+ sdhci_generic_suspend(&sc->slots[i]);
+ return (0);
+}
+
+static int
+sdhci_pci_resume(device_t dev)
+{
+ struct sdhci_pci_softc *sc = device_get_softc(dev);
+ int i, err;
+
+ for (i = 0; i < sc->num_slots; i++)
+ sdhci_generic_resume(&sc->slots[i]);
+ err = bus_generic_resume(dev);
+ if (err)
+ return (err);
+ if (sc->quirks & SDHCI_QUIRK_LOWER_FREQUENCY)
+ sdhci_lower_frequency(dev);
+ return (0);
+}
+
+static void
+sdhci_pci_intr(void *arg)
+{
+ struct sdhci_pci_softc *sc = (struct sdhci_pci_softc *)arg;
+ int i;
+
+ for (i = 0; i < sc->num_slots; i++)
+ sdhci_generic_intr(&sc->slots[i]);
+}
+
+static device_method_t sdhci_methods[] = {
+ /* device_if */
+ DEVMETHOD(device_probe, sdhci_pci_probe),
+ DEVMETHOD(device_attach, sdhci_pci_attach),
+ DEVMETHOD(device_detach, sdhci_pci_detach),
+ DEVMETHOD(device_shutdown, sdhci_pci_shutdown),
+ DEVMETHOD(device_suspend, sdhci_pci_suspend),
+ DEVMETHOD(device_resume, sdhci_pci_resume),
+
+ /* Bus interface */
+ DEVMETHOD(bus_read_ivar, sdhci_generic_read_ivar),
+ DEVMETHOD(bus_write_ivar, sdhci_generic_write_ivar),
+
+ /* mmcbr_if */
+ DEVMETHOD(mmcbr_update_ios, sdhci_generic_update_ios),
+ DEVMETHOD(mmcbr_switch_vccq, sdhci_generic_switch_vccq),
+ DEVMETHOD(mmcbr_tune, sdhci_generic_tune),
+ DEVMETHOD(mmcbr_retune, sdhci_generic_retune),
+ DEVMETHOD(mmcbr_request, sdhci_generic_request),
+ DEVMETHOD(mmcbr_get_ro, sdhci_generic_get_ro),
+ DEVMETHOD(mmcbr_acquire_host, sdhci_generic_acquire_host),
+ DEVMETHOD(mmcbr_release_host, sdhci_generic_release_host),
+
+ /* SDHCI accessors */
+ DEVMETHOD(sdhci_read_1, sdhci_pci_read_1),
+ DEVMETHOD(sdhci_read_2, sdhci_pci_read_2),
+ DEVMETHOD(sdhci_read_4, sdhci_pci_read_4),
+ DEVMETHOD(sdhci_read_multi_4, sdhci_pci_read_multi_4),
+ DEVMETHOD(sdhci_write_1, sdhci_pci_write_1),
+ DEVMETHOD(sdhci_write_2, sdhci_pci_write_2),
+ DEVMETHOD(sdhci_write_4, sdhci_pci_write_4),
+ DEVMETHOD(sdhci_write_multi_4, sdhci_pci_write_multi_4),
+ DEVMETHOD(sdhci_set_uhs_timing, sdhci_generic_set_uhs_timing),
+
+ DEVMETHOD_END
+};
+
+static driver_t sdhci_pci_driver = {
+ "sdhci_pci",
+ sdhci_methods,
+ sizeof(struct sdhci_pci_softc),
+};
+static devclass_t sdhci_pci_devclass;
+
+DRIVER_MODULE(sdhci_pci, pci, sdhci_pci_driver, sdhci_pci_devclass, NULL,
+ NULL);
+MODULE_DEPEND(sdhci_pci, sdhci, 1, 1, 1);
+MMC_DECLARE_BRIDGE(sdhci_pci);
Property changes on: trunk/sys/dev/sdhci/sdhci_pci.c
___________________________________________________________________
Added: svn:eol-style
## -0,0 +1 ##
+native
\ No newline at end of property
Added: svn:keywords
## -0,0 +1 ##
+MidnightBSD=%H
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+text/plain
\ No newline at end of property
More information about the Midnightbsd-cvs
mailing list