[Midnightbsd-cvs] src [10128] trunk/sys/dev: sync with freebsd
laffer1 at midnightbsd.org
laffer1 at midnightbsd.org
Sun May 27 20:27:44 EDT 2018
Revision: 10128
http://svnweb.midnightbsd.org/src/?rev=10128
Author: laffer1
Date: 2018-05-27 20:27:43 -0400 (Sun, 27 May 2018)
Log Message:
-----------
sync with freebsd
Modified Paths:
--------------
trunk/sys/dev/age/if_age.c
trunk/sys/dev/age/if_agereg.h
trunk/sys/dev/age/if_agevar.h
trunk/sys/dev/aha/aha.c
trunk/sys/dev/aha/aha_isa.c
trunk/sys/dev/aha/aha_mca.c
trunk/sys/dev/aha/ahareg.h
trunk/sys/dev/ahb/ahb.c
trunk/sys/dev/ahb/ahbreg.h
trunk/sys/dev/ahci/ahci.c
trunk/sys/dev/ahci/ahci.h
trunk/sys/dev/aic/aic.c
trunk/sys/dev/aic/aic6360reg.h
trunk/sys/dev/aic/aic_cbus.c
trunk/sys/dev/aic/aic_isa.c
trunk/sys/dev/aic/aic_pccard.c
trunk/sys/dev/aic/aicvar.h
trunk/sys/dev/aic7xxx/ahc_eisa.c
trunk/sys/dev/aic7xxx/ahc_isa.c
trunk/sys/dev/aic7xxx/ahc_pci.c
trunk/sys/dev/aic7xxx/ahd_pci.c
trunk/sys/dev/aic7xxx/aic7770.c
trunk/sys/dev/aic7xxx/aic79xx.c
trunk/sys/dev/aic7xxx/aic79xx.h
trunk/sys/dev/aic7xxx/aic79xx.reg
trunk/sys/dev/aic7xxx/aic79xx.seq
trunk/sys/dev/aic7xxx/aic79xx_inline.h
trunk/sys/dev/aic7xxx/aic79xx_osm.c
trunk/sys/dev/aic7xxx/aic79xx_osm.h
trunk/sys/dev/aic7xxx/aic79xx_pci.c
trunk/sys/dev/aic7xxx/aic7xxx.c
trunk/sys/dev/aic7xxx/aic7xxx.h
trunk/sys/dev/aic7xxx/aic7xxx.reg
trunk/sys/dev/aic7xxx/aic7xxx.seq
trunk/sys/dev/aic7xxx/aic7xxx_93cx6.c
trunk/sys/dev/aic7xxx/aic7xxx_93cx6.h
trunk/sys/dev/aic7xxx/aic7xxx_inline.h
trunk/sys/dev/aic7xxx/aic7xxx_osm.c
trunk/sys/dev/aic7xxx/aic7xxx_osm.h
trunk/sys/dev/aic7xxx/aic7xxx_pci.c
trunk/sys/dev/aic7xxx/aic7xxx_reg.h
trunk/sys/dev/aic7xxx/aic_osm_lib.c
trunk/sys/dev/aic7xxx/aic_osm_lib.h
trunk/sys/dev/aic7xxx/aicasm/Makefile
trunk/sys/dev/aic7xxx/aicasm/aicasm.c
trunk/sys/dev/aic7xxx/aicasm/aicasm.h
trunk/sys/dev/aic7xxx/aicasm/aicasm_gram.y
trunk/sys/dev/aic7xxx/aicasm/aicasm_insformat.h
trunk/sys/dev/aic7xxx/aicasm/aicasm_macro_gram.y
trunk/sys/dev/aic7xxx/aicasm/aicasm_macro_scan.l
trunk/sys/dev/aic7xxx/aicasm/aicasm_scan.l
trunk/sys/dev/aic7xxx/aicasm/aicasm_symbol.c
trunk/sys/dev/aic7xxx/aicasm/aicasm_symbol.h
trunk/sys/dev/alc/if_alc.c
trunk/sys/dev/alc/if_alcreg.h
trunk/sys/dev/alc/if_alcvar.h
trunk/sys/dev/ale/if_ale.c
trunk/sys/dev/ale/if_alereg.h
trunk/sys/dev/ale/if_alevar.h
trunk/sys/dev/amdtemp/amdtemp.c
trunk/sys/dev/amr/amr.c
trunk/sys/dev/amr/amr_cam.c
trunk/sys/dev/amr/amr_disk.c
trunk/sys/dev/amr/amr_linux.c
trunk/sys/dev/amr/amr_pci.c
trunk/sys/dev/amr/amr_tables.h
trunk/sys/dev/amr/amrio.h
trunk/sys/dev/amr/amrreg.h
trunk/sys/dev/amr/amrvar.h
trunk/sys/dev/an/if_aironet_ieee.h
trunk/sys/dev/an/if_an.c
trunk/sys/dev/an/if_an_isa.c
trunk/sys/dev/an/if_an_pccard.c
trunk/sys/dev/an/if_an_pci.c
trunk/sys/dev/an/if_anreg.h
trunk/sys/dev/arcmsr/arcmsr.c
trunk/sys/dev/arcmsr/arcmsr.h
trunk/sys/dev/asmc/asmc.c
trunk/sys/dev/asmc/asmcvar.h
trunk/sys/dev/asr/asr.c
trunk/sys/dev/asr/dptalign.h
trunk/sys/dev/asr/dptsig.h
trunk/sys/dev/asr/i2oadptr.h
trunk/sys/dev/asr/i2obscsi.h
trunk/sys/dev/asr/i2odep.h
trunk/sys/dev/asr/i2odpt.h
trunk/sys/dev/asr/i2oexec.h
trunk/sys/dev/asr/i2omsg.h
trunk/sys/dev/asr/i2otypes.h
trunk/sys/dev/asr/i2outil.h
trunk/sys/dev/asr/osd_defs.h
trunk/sys/dev/asr/osd_unix.h
trunk/sys/dev/asr/osd_util.h
trunk/sys/dev/asr/sys_info.h
trunk/sys/dev/ata/ata-all.c
trunk/sys/dev/ata/ata-all.h
trunk/sys/dev/ata/ata-card.c
trunk/sys/dev/ata/ata-cbus.c
trunk/sys/dev/ata/ata-dma.c
trunk/sys/dev/ata/ata-isa.c
trunk/sys/dev/ata/ata-lowlevel.c
trunk/sys/dev/ata/ata-pci.c
trunk/sys/dev/ata/ata-pci.h
trunk/sys/dev/ata/ata-sata.c
trunk/sys/dev/ata/ata_if.m
trunk/sys/dev/ata/chipsets/ata-acard.c
trunk/sys/dev/ata/chipsets/ata-acerlabs.c
trunk/sys/dev/ata/chipsets/ata-amd.c
trunk/sys/dev/ata/chipsets/ata-ati.c
trunk/sys/dev/ata/chipsets/ata-cenatek.c
trunk/sys/dev/ata/chipsets/ata-cypress.c
trunk/sys/dev/ata/chipsets/ata-cyrix.c
trunk/sys/dev/ata/chipsets/ata-highpoint.c
trunk/sys/dev/ata/chipsets/ata-intel.c
trunk/sys/dev/ata/chipsets/ata-ite.c
trunk/sys/dev/ata/chipsets/ata-jmicron.c
trunk/sys/dev/ata/chipsets/ata-marvell.c
trunk/sys/dev/ata/chipsets/ata-micron.c
trunk/sys/dev/ata/chipsets/ata-national.c
trunk/sys/dev/ata/chipsets/ata-netcell.c
trunk/sys/dev/ata/chipsets/ata-nvidia.c
trunk/sys/dev/ata/chipsets/ata-promise.c
trunk/sys/dev/ata/chipsets/ata-serverworks.c
trunk/sys/dev/ata/chipsets/ata-siliconimage.c
trunk/sys/dev/ata/chipsets/ata-sis.c
trunk/sys/dev/ata/chipsets/ata-via.c
Added Paths:
-----------
trunk/sys/dev/acpica/acpi_container.c
trunk/sys/dev/ahci/ahci_pci.c
trunk/sys/dev/ahci/ahciem.c
trunk/sys/dev/aic7xxx/aic79xx_reg.h
trunk/sys/dev/aic7xxx/aic79xx_reg_print.c
trunk/sys/dev/aic7xxx/aic79xx_seq.h
trunk/sys/dev/aic7xxx/aic7xxx_reg_print.c
trunk/sys/dev/aic7xxx/aic7xxx_seq.h
trunk/sys/dev/ata/chipsets/ata-fsl.c
trunk/sys/dev/ath/ath_hal/ar5416/ar5416_spectral.c
Property Changed:
----------------
trunk/sys/dev/aic7xxx/aic79xx.reg
trunk/sys/dev/aic7xxx/aic79xx.seq
trunk/sys/dev/aic7xxx/aic7xxx.reg
trunk/sys/dev/aic7xxx/aic7xxx.seq
trunk/sys/dev/aic7xxx/aicasm/aicasm_gram.y
trunk/sys/dev/aic7xxx/aicasm/aicasm_macro_gram.y
trunk/sys/dev/aic7xxx/aicasm/aicasm_macro_scan.l
trunk/sys/dev/aic7xxx/aicasm/aicasm_scan.l
trunk/sys/dev/ata/ata_if.m
Added: trunk/sys/dev/acpica/acpi_container.c
===================================================================
--- trunk/sys/dev/acpica/acpi_container.c (rev 0)
+++ trunk/sys/dev/acpica/acpi_container.c 2018-05-28 00:27:43 UTC (rev 10128)
@@ -0,0 +1,167 @@
+/* $MidnightBSD$ */
+/*-
+ * Copyright (c) 2017 Microsoft Corp.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice unmodified, this list of conditions, and the following
+ * disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+ * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+ * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <sys/cdefs.h>
+__FBSDID("$FreeBSD: stable/10/sys/dev/acpica/acpi_container.c 318393 2017-05-17 02:40:06Z sephe $");
+
+#include <sys/param.h>
+#include <sys/kernel.h>
+#include <sys/bus.h>
+#include <sys/module.h>
+
+#include <contrib/dev/acpica/include/acpi.h>
+#include <dev/acpica/acpivar.h>
+
+#include "pcib_if.h"
+
+ACPI_MODULE_NAME("CONTAINER")
+
+static int acpi_syscont_probe(device_t);
+static int acpi_syscont_attach(device_t);
+static int acpi_syscont_detach(device_t);
+static int acpi_syscont_alloc_msi(device_t, device_t,
+ int count, int maxcount, int *irqs);
+static int acpi_syscont_release_msi(device_t bus, device_t dev,
+ int count, int *irqs);
+static int acpi_syscont_alloc_msix(device_t bus, device_t dev,
+ int *irq);
+static int acpi_syscont_release_msix(device_t bus, device_t dev,
+ int irq);
+static int acpi_syscont_map_msi(device_t bus, device_t dev,
+ int irq, uint64_t *addr, uint32_t *data);
+
+static device_method_t acpi_syscont_methods[] = {
+ /* Device interface */
+ DEVMETHOD(device_probe, acpi_syscont_probe),
+ DEVMETHOD(device_attach, acpi_syscont_attach),
+ DEVMETHOD(device_detach, acpi_syscont_detach),
+
+ /* Bus interface */
+ DEVMETHOD(bus_add_child, bus_generic_add_child),
+ DEVMETHOD(bus_print_child, bus_generic_print_child),
+ DEVMETHOD(bus_alloc_resource, bus_generic_alloc_resource),
+ DEVMETHOD(bus_release_resource, bus_generic_release_resource),
+ DEVMETHOD(bus_activate_resource, bus_generic_activate_resource),
+ DEVMETHOD(bus_deactivate_resource, bus_generic_deactivate_resource),
+ DEVMETHOD(bus_setup_intr, bus_generic_setup_intr),
+ DEVMETHOD(bus_teardown_intr, bus_generic_teardown_intr),
+#if __FreeBSD_version >= 1100000
+ DEVMETHOD(bus_get_cpus, bus_generic_get_cpus),
+#endif
+
+ /* pcib interface */
+ DEVMETHOD(pcib_alloc_msi, acpi_syscont_alloc_msi),
+ DEVMETHOD(pcib_release_msi, acpi_syscont_release_msi),
+ DEVMETHOD(pcib_alloc_msix, acpi_syscont_alloc_msix),
+ DEVMETHOD(pcib_release_msix, acpi_syscont_release_msix),
+ DEVMETHOD(pcib_map_msi, acpi_syscont_map_msi),
+
+ DEVMETHOD_END
+};
+
+static driver_t acpi_syscont_driver = {
+ "acpi_syscontainer",
+ acpi_syscont_methods,
+ 0,
+};
+
+static devclass_t acpi_syscont_devclass;
+
+DRIVER_MODULE(acpi_syscontainer, acpi, acpi_syscont_driver,
+ acpi_syscont_devclass, NULL, NULL);
+MODULE_DEPEND(acpi_syscontainer, acpi, 1, 1, 1);
+
+static int
+acpi_syscont_probe(device_t dev)
+{
+ static char *syscont_ids[] = { "ACPI0004", "PNP0A05", "PNP0A06", NULL };
+
+ if (acpi_disabled("syscontainer") ||
+ ACPI_ID_PROBE(device_get_parent(dev), dev, syscont_ids) == NULL)
+ return (ENXIO);
+
+ device_set_desc(dev, "System Container");
+ return (BUS_PROBE_DEFAULT);
+}
+
+static int
+acpi_syscont_attach(device_t dev)
+{
+
+ bus_generic_probe(dev);
+ return (bus_generic_attach(dev));
+}
+
+static int
+acpi_syscont_detach(device_t dev)
+{
+
+ return (bus_generic_detach(dev));
+}
+
+static int
+acpi_syscont_alloc_msi(device_t bus, device_t dev, int count, int maxcount,
+ int *irqs)
+{
+ device_t parent = device_get_parent(bus);
+
+ return (PCIB_ALLOC_MSI(device_get_parent(parent), dev, count, maxcount,
+ irqs));
+}
+
+static int
+acpi_syscont_release_msi(device_t bus, device_t dev, int count, int *irqs)
+{
+ device_t parent = device_get_parent(bus);
+
+ return (PCIB_RELEASE_MSI(device_get_parent(parent), dev, count, irqs));
+}
+
+static int
+acpi_syscont_alloc_msix(device_t bus, device_t dev, int *irq)
+{
+ device_t parent = device_get_parent(bus);
+
+ return (PCIB_ALLOC_MSIX(device_get_parent(parent), dev, irq));
+}
+
+static int
+acpi_syscont_release_msix(device_t bus, device_t dev, int irq)
+{
+ device_t parent = device_get_parent(bus);
+
+ return (PCIB_RELEASE_MSIX(device_get_parent(parent), dev, irq));
+}
+
+static int
+acpi_syscont_map_msi(device_t bus, device_t dev, int irq, uint64_t *addr,
+ uint32_t *data)
+{
+ device_t parent = device_get_parent(bus);
+
+ return (PCIB_MAP_MSI(device_get_parent(parent), dev, irq, addr, data));
+}
Property changes on: trunk/sys/dev/acpica/acpi_container.c
___________________________________________________________________
Added: svn:eol-style
## -0,0 +1 ##
+native
\ No newline at end of property
Added: svn:keywords
## -0,0 +1 ##
+MidnightBSD=%H
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+text/plain
\ No newline at end of property
Modified: trunk/sys/dev/age/if_age.c
===================================================================
--- trunk/sys/dev/age/if_age.c 2018-05-28 00:25:20 UTC (rev 10127)
+++ trunk/sys/dev/age/if_age.c 2018-05-28 00:27:43 UTC (rev 10128)
@@ -1,3 +1,4 @@
+/* $MidnightBSD$ */
/*-
* Copyright (c) 2008, Pyun YongHyeon <yongari at FreeBSD.org>
* All rights reserved.
@@ -28,7 +29,7 @@
/* Driver for Attansic Technology Corp. L1 Gigabit Ethernet. */
#include <sys/cdefs.h>
-__MBSDID("$MidnightBSD$");
+__FBSDID("$FreeBSD: stable/10/sys/dev/age/if_age.c 312362 2017-01-18 02:16:17Z yongari $");
#include <sys/param.h>
#include <sys/systm.h>
@@ -587,7 +588,7 @@
/* Create device sysctl node. */
age_sysctl_node(sc);
- if ((error = age_dma_alloc(sc) != 0))
+ if ((error = age_dma_alloc(sc)) != 0)
goto fail;
/* Load station address. */
@@ -2478,7 +2479,7 @@
sc->age_cdata.age_rx_ring_map, BUS_DMASYNC_POSTWRITE);
for (prog = 0; rr_cons != rr_prod; prog++) {
- if (count <= 0)
+ if (count-- <= 0)
break;
rxrd = &sc->age_rdata.age_rr_ring[rr_cons];
nsegs = AGE_RX_NSEGS(le32toh(rxrd->index));
Modified: trunk/sys/dev/age/if_agereg.h
===================================================================
--- trunk/sys/dev/age/if_agereg.h 2018-05-28 00:25:20 UTC (rev 10127)
+++ trunk/sys/dev/age/if_agereg.h 2018-05-28 00:27:43 UTC (rev 10128)
@@ -1,3 +1,4 @@
+/* $MidnightBSD$ */
/*-
* Copyright (c) 2008, Pyun YongHyeon <yongari at FreeBSD.org>
* All rights reserved.
@@ -24,7 +25,7 @@
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*
- * $MidnightBSD$
+ * $FreeBSD: stable/10/sys/dev/age/if_agereg.h 190499 2009-03-28 07:39:35Z yongari $
*/
#ifndef _IF_AGEREG_H
Modified: trunk/sys/dev/age/if_agevar.h
===================================================================
--- trunk/sys/dev/age/if_agevar.h 2018-05-28 00:25:20 UTC (rev 10127)
+++ trunk/sys/dev/age/if_agevar.h 2018-05-28 00:27:43 UTC (rev 10128)
@@ -1,3 +1,4 @@
+/* $MidnightBSD$ */
/*-
* Copyright (c) 2008, Pyun YongHyeon <yongari at FreeBSD.org>
* All rights reserved.
@@ -24,7 +25,7 @@
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*
- * $MidnightBSD$
+ * $FreeBSD: stable/10/sys/dev/age/if_agevar.h 264442 2014-04-14 04:51:59Z yongari $
*/
#ifndef _IF_AGEVAR_H
@@ -42,7 +43,7 @@
#define AGE_TSO_MAXSEGSIZE 4096
#define AGE_TSO_MAXSIZE (65535 + sizeof(struct ether_vlan_header))
-#define AGE_MAXTXSEGS 32
+#define AGE_MAXTXSEGS 35
#define AGE_RX_BUF_ALIGN 8
#ifndef __NO_STRICT_ALIGNMENT
#define AGE_RX_BUF_SIZE (MCLBYTES - AGE_RX_BUF_ALIGN)
Modified: trunk/sys/dev/aha/aha.c
===================================================================
--- trunk/sys/dev/aha/aha.c 2018-05-28 00:25:20 UTC (rev 10127)
+++ trunk/sys/dev/aha/aha.c 2018-05-28 00:27:43 UTC (rev 10128)
@@ -59,7 +59,7 @@
*/
#include <sys/cdefs.h>
-__FBSDID("$FreeBSD$");
+__FBSDID("$FreeBSD: stable/10/sys/dev/aha/aha.c 315813 2017-03-23 06:41:13Z mav $");
#include <sys/param.h>
#include <sys/conf.h>
@@ -208,9 +208,9 @@
case 7:
bus_dmamap_unload(aha->ccb_dmat, aha->ccb_dmamap);
case 6:
- bus_dmamap_destroy(aha->ccb_dmat, aha->ccb_dmamap);
bus_dmamem_free(aha->ccb_dmat, aha->aha_ccb_array,
aha->ccb_dmamap);
+ bus_dmamap_destroy(aha->ccb_dmat, aha->ccb_dmamap);
case 5:
bus_dma_tag_destroy(aha->ccb_dmat);
case 4:
@@ -461,7 +461,7 @@
/* highaddr */ BUS_SPACE_MAXADDR,
/* filter */ NULL,
/* filterarg */ NULL,
- /* maxsize */ MAXBSIZE,
+ /* maxsize */ DFLTPHYS,
/* nsegments */ AHA_NSEG,
/* maxsegsz */ BUS_SPACE_MAXSIZE_24BIT,
/* flags */ BUS_DMA_ALLOCNOW,
@@ -779,6 +779,7 @@
if (ccb->ccb_h.func_code == XPT_SCSI_IO) {
struct ccb_scsiio *csio;
struct ccb_hdr *ccbh;
+ int error;
csio = &ccb->csio;
ccbh = &csio->ccb_h;
@@ -812,67 +813,22 @@
* If we have any data to send with this command,
* map it into bus space.
*/
- /* Only use S/G if there is a transfer */
- if ((ccbh->flags & CAM_DIR_MASK) != CAM_DIR_NONE) {
- if ((ccbh->flags & CAM_SCATTER_VALID) == 0) {
- /*
- * We've been given a pointer
- * to a single buffer.
- */
- if ((ccbh->flags & CAM_DATA_PHYS)==0) {
- int error;
- error = bus_dmamap_load(
- aha->buffer_dmat,
- accb->dmamap,
- csio->data_ptr,
- csio->dxfer_len,
- ahaexecuteccb,
- accb,
- /*flags*/0);
- if (error == EINPROGRESS) {
- /*
- * So as to maintain
- * ordering, freeze the
- * controller queue
- * until our mapping is
- * returned.
- */
- xpt_freeze_simq(aha->sim,
- 1);
- csio->ccb_h.status |=
- CAM_RELEASE_SIMQ;
- }
- } else {
- struct bus_dma_segment seg;
-
- /* Pointer to physical buffer */
- seg.ds_addr =
- (bus_addr_t)csio->data_ptr;
- seg.ds_len = csio->dxfer_len;
- ahaexecuteccb(accb, &seg, 1, 0);
- }
- } else {
- struct bus_dma_segment *segs;
-
- if ((ccbh->flags & CAM_DATA_PHYS) != 0)
- panic("ahaaction - Physical "
- "segment pointers "
- "unsupported");
-
- if ((ccbh->flags&CAM_SG_LIST_PHYS)==0)
- panic("ahaaction - Virtual "
- "segment addresses "
- "unsupported");
-
- /* Just use the segments provided */
- segs = (struct bus_dma_segment *)
- csio->data_ptr;
- ahaexecuteccb(accb, segs,
- csio->sglist_cnt, 0);
- }
- } else {
- ahaexecuteccb(accb, NULL, 0, 0);
+ error = bus_dmamap_load_ccb(
+ aha->buffer_dmat,
+ accb->dmamap,
+ ccb,
+ ahaexecuteccb,
+ accb,
+ /*flags*/0);
+ if (error == EINPROGRESS) {
+ /*
+ * So as to maintain ordering, freeze the
+ * controller queue until our mapping is
+ * returned.
+ */
+ xpt_freeze_simq(aha->sim, 1);
+ csio->ccb_h.status |= CAM_RELEASE_SIMQ;
}
} else {
hccb->opcode = INITIATOR_BUS_DEV_RESET;
@@ -994,9 +950,9 @@
cpi->initiator_id = aha->scsi_id;
cpi->bus_id = cam_sim_bus(sim);
cpi->base_transfer_speed = 3300;
- strncpy(cpi->sim_vid, "MidnightBSD", SIM_IDLEN);
- strncpy(cpi->hba_vid, "Adaptec", HBA_IDLEN);
- strncpy(cpi->dev_name, cam_sim_name(sim), DEV_IDLEN);
+ strlcpy(cpi->sim_vid, "FreeBSD", SIM_IDLEN);
+ strlcpy(cpi->hba_vid, "Adaptec", HBA_IDLEN);
+ strlcpy(cpi->dev_name, cam_sim_name(sim), DEV_IDLEN);
cpi->unit_number = cam_sim_unit(sim);
cpi->transport = XPORT_SPI;
cpi->transport_version = 2;
@@ -1094,8 +1050,8 @@
ccb->ccb_h.status |= CAM_SIM_QUEUED;
LIST_INSERT_HEAD(&aha->pending_ccbs, &ccb->ccb_h, sim_links.le);
- callout_reset(&accb->timer, (ccb->ccb_h.timeout * hz) / 1000,
- ahatimeout, accb);
+ callout_reset_sbt(&accb->timer, SBT_1MS * ccb->ccb_h.timeout, 0,
+ ahatimeout, accb, 0);
/* Tell the adapter about this command */
if (aha->cur_outbox->action_code != AMBO_FREE) {
@@ -1213,8 +1169,10 @@
cam_sim_path(aha->sim), accb->hccb.target,
CAM_LUN_WILDCARD);
- if (error == CAM_REQ_CMP)
+ if (error == CAM_REQ_CMP) {
xpt_async(AC_SENT_BDR, path, NULL);
+ xpt_free_path(path);
+ }
ccb_h = LIST_FIRST(&aha->pending_ccbs);
while (ccb_h != NULL) {
@@ -1226,9 +1184,9 @@
ccb_h = LIST_NEXT(ccb_h, sim_links.le);
ahadone(aha, pending_accb, AMBI_ERROR);
} else {
- callout_reset(&pending_accb->timer,
- (ccb_h->timeout * hz) / 1000,
- ahatimeout, pending_accb);
+ callout_reset_sbt(&pending_accb->timer,
+ SBT_1MS * ccb_h->timeout, 0, ahatimeout,
+ pending_accb, 0);
ccb_h = LIST_NEXT(ccb_h, sim_links.le);
}
}
Modified: trunk/sys/dev/aha/aha_isa.c
===================================================================
--- trunk/sys/dev/aha/aha_isa.c 2018-05-28 00:25:20 UTC (rev 10127)
+++ trunk/sys/dev/aha/aha_isa.c 2018-05-28 00:27:43 UTC (rev 10128)
@@ -56,7 +56,7 @@
*/
#include <sys/cdefs.h>
-__FBSDID("$FreeBSD$");
+__FBSDID("$FreeBSD: stable/10/sys/dev/aha/aha_isa.c 241603 2012-10-16 08:40:09Z glebius $");
#include <sys/param.h>
#include <sys/systm.h>
Modified: trunk/sys/dev/aha/aha_mca.c
===================================================================
--- trunk/sys/dev/aha/aha_mca.c 2018-05-28 00:25:20 UTC (rev 10127)
+++ trunk/sys/dev/aha/aha_mca.c 2018-05-28 00:27:43 UTC (rev 10128)
@@ -28,7 +28,7 @@
*/
#include <sys/cdefs.h>
-__FBSDID("$FreeBSD$");
+__FBSDID("$FreeBSD: stable/10/sys/dev/aha/aha_mca.c 241611 2012-10-16 15:25:04Z pluknet $");
#include <sys/types.h>
#include <sys/param.h>
Modified: trunk/sys/dev/aha/ahareg.h
===================================================================
--- trunk/sys/dev/aha/ahareg.h 2018-05-28 00:25:20 UTC (rev 10127)
+++ trunk/sys/dev/aha/ahareg.h 2018-05-28 00:27:43 UTC (rev 10128)
@@ -31,7 +31,7 @@
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*
- * $FreeBSD$
+ * $FreeBSD: stable/10/sys/dev/aha/ahareg.h 241603 2012-10-16 08:40:09Z glebius $
*/
#ifndef _AHAREG_H_
Modified: trunk/sys/dev/ahb/ahb.c
===================================================================
--- trunk/sys/dev/ahb/ahb.c 2018-05-28 00:25:20 UTC (rev 10127)
+++ trunk/sys/dev/ahb/ahb.c 2018-05-28 00:27:43 UTC (rev 10128)
@@ -26,7 +26,7 @@
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*
- * $FreeBSD$
+ * $FreeBSD: stable/10/sys/dev/ahb/ahb.c 315813 2017-03-23 06:41:13Z mav $
*/
#include <sys/param.h>
@@ -299,7 +299,7 @@
/* highaddr */ BUS_SPACE_MAXADDR,
/* filter */ NULL,
/* filterarg */ NULL,
- /* maxsize */ MAXBSIZE,
+ /* maxsize */ DFLTPHYS,
/* nsegments */ AHB_NSEG,
/* maxsegsz */ BUS_SPACE_MAXSIZE_32BIT,
/* flags */ BUS_DMA_ALLOCNOW,
@@ -618,9 +618,9 @@
xpt_done(ccb);
} else if (ahb->immed_ecb != NULL) {
/* Re-instate timeout */
- callout_reset(&pending_ecb->timer,
- (ccb->ccb_h.timeout * hz) / 1000,
- ahbtimeout, pending_ecb);
+ callout_reset_sbt(&pending_ecb->timer,
+ SBT_1MS * ccb->ccb_h.timeout, 0, ahbtimeout,
+ pending_ecb, 0);
}
}
@@ -987,8 +987,8 @@
/* Tell the adapter about this command */
ahbqueuembox(ahb, ecb_paddr, ATTN_STARTECB|ccb->ccb_h.target_id);
- callout_reset(&ecb->timer, (ccb->ccb_h.timeout * hz) / 1000, ahbtimeout,
- ecb);
+ callout_reset_sbt(&ecb->timer, SBT_1MS * ccb->ccb_h.timeout, 0,
+ ahbtimeout, ecb, 0);
}
static void
@@ -1007,6 +1007,7 @@
{
struct ecb *ecb;
struct hardware_ecb *hecb;
+ int error;
/*
* get an ecb to use.
@@ -1057,65 +1058,19 @@
hecb->cdb, hecb->cdb_len);
}
- /*
- * If we have any data to send with this command,
- * map it into bus space.
- */
- if ((ccb->ccb_h.flags & CAM_DIR_MASK) != CAM_DIR_NONE) {
- if ((ccb->ccb_h.flags & CAM_SCATTER_VALID) == 0) {
- /*
- * We've been given a pointer
- * to a single buffer.
- */
- if ((ccb->ccb_h.flags & CAM_DATA_PHYS)==0) {
- int error;
-
- error = bus_dmamap_load(
- ahb->buffer_dmat,
- ecb->dmamap,
- ccb->csio.data_ptr,
- ccb->csio.dxfer_len,
- ahbexecuteecb,
- ecb, /*flags*/0);
- if (error == EINPROGRESS) {
- /*
- * So as to maintain ordering,
- * freeze the controller queue
- * until our mapping is
- * returned.
- */
- xpt_freeze_simq(ahb->sim, 1);
- ccb->ccb_h.status |=
- CAM_RELEASE_SIMQ;
- }
- } else {
- struct bus_dma_segment seg;
-
- /* Pointer to physical buffer */
- seg.ds_addr =
- (bus_addr_t)ccb->csio.data_ptr;
- seg.ds_len = ccb->csio.dxfer_len;
- ahbexecuteecb(ecb, &seg, 1, 0);
- }
- } else {
- struct bus_dma_segment *segs;
-
- if ((ccb->ccb_h.flags & CAM_DATA_PHYS) != 0)
- panic("ahbaction - Physical segment "
- "pointers unsupported");
-
- if ((ccb->ccb_h.flags & CAM_SG_LIST_PHYS) == 0)
- panic("btaction - Virtual segment "
- "addresses unsupported");
-
- /* Just use the segments provided */
- segs = (struct bus_dma_segment *)
- ccb->csio.data_ptr;
- ahbexecuteecb(ecb, segs, ccb->csio.sglist_cnt,
- 0);
- }
- } else {
- ahbexecuteecb(ecb, NULL, 0, 0);
+ error = bus_dmamap_load_ccb(
+ ahb->buffer_dmat,
+ ecb->dmamap,
+ ccb,
+ ahbexecuteecb,
+ ecb, /*flags*/0);
+ if (error == EINPROGRESS) {
+ /*
+ * So as to maintain ordering, freeze the controller
+ * queue until our mapping is returned.
+ */
+ xpt_freeze_simq(ahb->sim, 1);
+ ccb->ccb_h.status |= CAM_RELEASE_SIMQ;
}
break;
}
@@ -1225,9 +1180,9 @@
cpi->initiator_id = ahb->scsi_id;
cpi->bus_id = cam_sim_bus(sim);
cpi->base_transfer_speed = 3300;
- strncpy(cpi->sim_vid, "MidnightBSD", SIM_IDLEN);
- strncpy(cpi->hba_vid, "Adaptec", HBA_IDLEN);
- strncpy(cpi->dev_name, cam_sim_name(sim), DEV_IDLEN);
+ strlcpy(cpi->sim_vid, "FreeBSD", SIM_IDLEN);
+ strlcpy(cpi->hba_vid, "Adaptec", HBA_IDLEN);
+ strlcpy(cpi->dev_name, cam_sim_name(sim), DEV_IDLEN);
cpi->unit_number = cam_sim_unit(sim);
cpi->transport = XPORT_SPI;
cpi->transport_version = 2;
Modified: trunk/sys/dev/ahb/ahbreg.h
===================================================================
--- trunk/sys/dev/ahb/ahbreg.h 2018-05-28 00:25:20 UTC (rev 10127)
+++ trunk/sys/dev/ahb/ahbreg.h 2018-05-28 00:27:43 UTC (rev 10128)
@@ -26,7 +26,7 @@
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*
- * $FreeBSD$
+ * $FreeBSD: stable/10/sys/dev/ahb/ahbreg.h 241590 2012-10-15 16:05:02Z jhb $
*/
/* Resource Constatns */
Modified: trunk/sys/dev/ahci/ahci.c
===================================================================
--- trunk/sys/dev/ahci/ahci.c 2018-05-28 00:25:20 UTC (rev 10127)
+++ trunk/sys/dev/ahci/ahci.c 2018-05-28 00:27:43 UTC (rev 10128)
@@ -1,5 +1,6 @@
+/* $MidnightBSD$ */
/*-
- * Copyright (c) 2009 Alexander Motin <mav at FreeBSD.org>
+ * Copyright (c) 2009-2012 Alexander Motin <mav at FreeBSD.org>
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
@@ -25,13 +26,12 @@
*/
#include <sys/cdefs.h>
-__MBSDID("$MidnightBSD$");
+__FBSDID("$FreeBSD: stable/10/sys/dev/ahci/ahci.c 315813 2017-03-23 06:41:13Z mav $");
#include <sys/param.h>
#include <sys/module.h>
#include <sys/systm.h>
#include <sys/kernel.h>
-#include <sys/ata.h>
#include <sys/bus.h>
#include <sys/conf.h>
#include <sys/endian.h>
@@ -38,16 +38,10 @@
#include <sys/malloc.h>
#include <sys/lock.h>
#include <sys/mutex.h>
-#include <sys/sema.h>
-#include <sys/taskqueue.h>
-#include <vm/uma.h>
#include <machine/stdarg.h>
#include <machine/resource.h>
#include <machine/bus.h>
#include <sys/rman.h>
-#include <dev/led/led.h>
-#include <dev/pci/pcivar.h>
-#include <dev/pci/pcireg.h>
#include "ahci.h"
#include <cam/cam.h>
@@ -57,46 +51,42 @@
#include <cam/cam_debug.h>
/* local prototypes */
-static int ahci_setup_interrupt(device_t dev);
static void ahci_intr(void *data);
static void ahci_intr_one(void *data);
-static int ahci_suspend(device_t dev);
-static int ahci_resume(device_t dev);
+static void ahci_intr_one_edge(void *data);
static int ahci_ch_init(device_t dev);
static int ahci_ch_deinit(device_t dev);
static int ahci_ch_suspend(device_t dev);
static int ahci_ch_resume(device_t dev);
static void ahci_ch_pm(void *arg);
-static void ahci_ch_intr_locked(void *data);
-static void ahci_ch_intr(void *data);
-static void ahci_ch_led(void *priv, int onoff);
-static int ahci_ctlr_reset(device_t dev);
-static int ahci_ctlr_setup(device_t dev);
-static void ahci_begin_transaction(device_t dev, union ccb *ccb);
+static void ahci_ch_intr(void *arg);
+static void ahci_ch_intr_direct(void *arg);
+static void ahci_ch_intr_main(struct ahci_channel *ch, uint32_t istatus);
+static void ahci_begin_transaction(struct ahci_channel *ch, union ccb *ccb);
static void ahci_dmasetprd(void *arg, bus_dma_segment_t *segs, int nsegs, int error);
static void ahci_execute_transaction(struct ahci_slot *slot);
static void ahci_timeout(struct ahci_slot *slot);
static void ahci_end_transaction(struct ahci_slot *slot, enum ahci_err_type et);
-static int ahci_setup_fis(device_t dev, struct ahci_cmd_tab *ctp, union ccb *ccb, int tag);
+static int ahci_setup_fis(struct ahci_channel *ch, struct ahci_cmd_tab *ctp, union ccb *ccb, int tag);
static void ahci_dmainit(device_t dev);
static void ahci_dmasetupc_cb(void *xsc, bus_dma_segment_t *segs, int nsegs, int error);
static void ahci_dmafini(device_t dev);
static void ahci_slotsalloc(device_t dev);
static void ahci_slotsfree(device_t dev);
-static void ahci_reset(device_t dev);
-static void ahci_start(device_t dev, int fbs);
-static void ahci_stop(device_t dev);
-static void ahci_clo(device_t dev);
-static void ahci_start_fr(device_t dev);
-static void ahci_stop_fr(device_t dev);
+static void ahci_reset(struct ahci_channel *ch);
+static void ahci_start(struct ahci_channel *ch, int fbs);
+static void ahci_stop(struct ahci_channel *ch);
+static void ahci_clo(struct ahci_channel *ch);
+static void ahci_start_fr(struct ahci_channel *ch);
+static void ahci_stop_fr(struct ahci_channel *ch);
static int ahci_sata_connect(struct ahci_channel *ch);
-static int ahci_sata_phy_reset(device_t dev);
-static int ahci_wait_ready(device_t dev, int t, int t0);
+static int ahci_sata_phy_reset(struct ahci_channel *ch);
+static int ahci_wait_ready(struct ahci_channel *ch, int t, int t0);
-static void ahci_issue_recovery(device_t dev);
-static void ahci_process_read_log(device_t dev, union ccb *ccb);
-static void ahci_process_request_sense(device_t dev, union ccb *ccb);
+static void ahci_issue_recovery(struct ahci_channel *ch);
+static void ahci_process_read_log(struct ahci_channel *ch, union ccb *ccb);
+static void ahci_process_request_sense(struct ahci_channel *ch, union ccb *ccb);
static void ahciaction(struct cam_sim *sim, union ccb *ccb);
static void ahcipoll(struct cam_sim *sim);
@@ -103,275 +93,6 @@
static MALLOC_DEFINE(M_AHCI, "AHCI driver", "AHCI driver data buffers");
-static const struct {
- uint32_t id;
- uint8_t rev;
- const char *name;
- int quirks;
-#define AHCI_Q_NOFORCE 1
-#define AHCI_Q_NOPMP 2
-#define AHCI_Q_NONCQ 4
-#define AHCI_Q_1CH 8
-#define AHCI_Q_2CH 16
-#define AHCI_Q_4CH 32
-#define AHCI_Q_EDGEIS 64
-#define AHCI_Q_SATA2 128
-#define AHCI_Q_NOBSYRES 256
-#define AHCI_Q_NOAA 512
-#define AHCI_Q_NOCOUNT 1024
-#define AHCI_Q_ALTSIG 2048
-#define AHCI_Q_NOMSI 4096
-
-#define AHCI_Q_BIT_STRING \
- "\020" \
- "\001NOFORCE" \
- "\002NOPMP" \
- "\003NONCQ" \
- "\0041CH" \
- "\0052CH" \
- "\0064CH" \
- "\007EDGEIS" \
- "\010SATA2" \
- "\011NOBSYRES" \
- "\012NOAA" \
- "\013NOCOUNT" \
- "\014ALTSIG" \
- "\015NOMSI"
-} ahci_ids[] = {
- {0x43801002, 0x00, "AMD SB600", AHCI_Q_NOMSI},
- {0x43901002, 0x00, "AMD SB7x0/SB8x0/SB9x0", 0},
- {0x43911002, 0x00, "AMD SB7x0/SB8x0/SB9x0", 0},
- {0x43921002, 0x00, "AMD SB7x0/SB8x0/SB9x0", 0},
- {0x43931002, 0x00, "AMD SB7x0/SB8x0/SB9x0", 0},
- {0x43941002, 0x00, "AMD SB7x0/SB8x0/SB9x0", 0},
- {0x43951002, 0x00, "AMD SB8x0/SB9x0", 0},
- {0x78001022, 0x00, "AMD Hudson-2", 0},
- {0x78011022, 0x00, "AMD Hudson-2", 0},
- {0x78021022, 0x00, "AMD Hudson-2", 0},
- {0x78031022, 0x00, "AMD Hudson-2", 0},
- {0x78041022, 0x00, "AMD Hudson-2", 0},
- {0x06111b21, 0x00, "ASMedia ASM2106", 0},
- {0x06121b21, 0x00, "ASMedia ASM1061", 0},
- {0x26528086, 0x00, "Intel ICH6", AHCI_Q_NOFORCE},
- {0x26538086, 0x00, "Intel ICH6M", AHCI_Q_NOFORCE},
- {0x26818086, 0x00, "Intel ESB2", 0},
- {0x26828086, 0x00, "Intel ESB2", 0},
- {0x26838086, 0x00, "Intel ESB2", 0},
- {0x27c18086, 0x00, "Intel ICH7", 0},
- {0x27c38086, 0x00, "Intel ICH7", 0},
- {0x27c58086, 0x00, "Intel ICH7M", 0},
- {0x27c68086, 0x00, "Intel ICH7M", 0},
- {0x28218086, 0x00, "Intel ICH8", 0},
- {0x28228086, 0x00, "Intel ICH8", 0},
- {0x28248086, 0x00, "Intel ICH8", 0},
- {0x28298086, 0x00, "Intel ICH8M", 0},
- {0x282a8086, 0x00, "Intel ICH8M", 0},
- {0x29228086, 0x00, "Intel ICH9", 0},
- {0x29238086, 0x00, "Intel ICH9", 0},
- {0x29248086, 0x00, "Intel ICH9", 0},
- {0x29258086, 0x00, "Intel ICH9", 0},
- {0x29278086, 0x00, "Intel ICH9", 0},
- {0x29298086, 0x00, "Intel ICH9M", 0},
- {0x292a8086, 0x00, "Intel ICH9M", 0},
- {0x292b8086, 0x00, "Intel ICH9M", 0},
- {0x292c8086, 0x00, "Intel ICH9M", 0},
- {0x292f8086, 0x00, "Intel ICH9M", 0},
- {0x294d8086, 0x00, "Intel ICH9", 0},
- {0x294e8086, 0x00, "Intel ICH9M", 0},
- {0x3a058086, 0x00, "Intel ICH10", 0},
- {0x3a228086, 0x00, "Intel ICH10", 0},
- {0x3a258086, 0x00, "Intel ICH10", 0},
- {0x3b228086, 0x00, "Intel 5 Series/3400 Series", 0},
- {0x3b238086, 0x00, "Intel 5 Series/3400 Series", 0},
- {0x3b258086, 0x00, "Intel 5 Series/3400 Series", 0},
- {0x3b298086, 0x00, "Intel 5 Series/3400 Series", 0},
- {0x3b2c8086, 0x00, "Intel 5 Series/3400 Series", 0},
- {0x3b2f8086, 0x00, "Intel 5 Series/3400 Series", 0},
- {0x1c028086, 0x00, "Intel Cougar Point", 0},
- {0x1c038086, 0x00, "Intel Cougar Point", 0},
- {0x1c048086, 0x00, "Intel Cougar Point", 0},
- {0x1c058086, 0x00, "Intel Cougar Point", 0},
- {0x1d028086, 0x00, "Intel Patsburg", 0},
- {0x1d048086, 0x00, "Intel Patsburg", 0},
- {0x1d068086, 0x00, "Intel Patsburg", 0},
- {0x28268086, 0x00, "Intel Patsburg (RAID)", 0},
- {0x1e028086, 0x00, "Intel Panther Point", 0},
- {0x1e038086, 0x00, "Intel Panther Point", 0},
- {0x1e048086, 0x00, "Intel Panther Point (RAID)", 0},
- {0x1e058086, 0x00, "Intel Panther Point (RAID)", 0},
- {0x1e068086, 0x00, "Intel Panther Point (RAID)", 0},
- {0x1e078086, 0x00, "Intel Panther Point (RAID)", 0},
- {0x1e0e8086, 0x00, "Intel Panther Point (RAID)", 0},
- {0x1e0f8086, 0x00, "Intel Panther Point (RAID)", 0},
- {0x1f228086, 0x00, "Intel Avoton", 0},
- {0x1f238086, 0x00, "Intel Avoton", 0},
- {0x1f248086, 0x00, "Intel Avoton (RAID)", 0},
- {0x1f258086, 0x00, "Intel Avoton (RAID)", 0},
- {0x1f268086, 0x00, "Intel Avoton (RAID)", 0},
- {0x1f278086, 0x00, "Intel Avoton (RAID)", 0},
- {0x1f2e8086, 0x00, "Intel Avoton (RAID)", 0},
- {0x1f2f8086, 0x00, "Intel Avoton (RAID)", 0},
- {0x1f328086, 0x00, "Intel Avoton", 0},
- {0x1f338086, 0x00, "Intel Avoton", 0},
- {0x1f348086, 0x00, "Intel Avoton (RAID)", 0},
- {0x1f358086, 0x00, "Intel Avoton (RAID)", 0},
- {0x1f368086, 0x00, "Intel Avoton (RAID)", 0},
- {0x1f378086, 0x00, "Intel Avoton (RAID)", 0},
- {0x1f3e8086, 0x00, "Intel Avoton (RAID)", 0},
- {0x1f3f8086, 0x00, "Intel Avoton (RAID)", 0},
- {0x23a38086, 0x00, "Intel Coleto Creek", 0},
- {0x28238086, 0x00, "Intel Wellsburg (RAID)", 0},
- {0x28278086, 0x00, "Intel Wellsburg (RAID)", 0},
- {0x8c028086, 0x00, "Intel Lynx Point", 0},
- {0x8c038086, 0x00, "Intel Lynx Point", 0},
- {0x8c048086, 0x00, "Intel Lynx Point (RAID)", 0},
- {0x8c058086, 0x00, "Intel Lynx Point (RAID)", 0},
- {0x8c068086, 0x00, "Intel Lynx Point (RAID)", 0},
- {0x8c078086, 0x00, "Intel Lynx Point (RAID)", 0},
- {0x8c0e8086, 0x00, "Intel Lynx Point (RAID)", 0},
- {0x8c0f8086, 0x00, "Intel Lynx Point (RAID)", 0},
- {0x8c828086, 0x00, "Intel Wildcat Point", 0},
- {0x8c838086, 0x00, "Intel Wildcat Point", 0},
- {0x8c848086, 0x00, "Intel Wildcat Point (RAID)", 0},
- {0x8c858086, 0x00, "Intel Wildcat Point (RAID)", 0},
- {0x8c868086, 0x00, "Intel Wildcat Point (RAID)", 0},
- {0x8c878086, 0x00, "Intel Wildcat Point (RAID)", 0},
- {0x8c8e8086, 0x00, "Intel Wildcat Point (RAID)", 0},
- {0x8c8f8086, 0x00, "Intel Wildcat Point (RAID)", 0},
- {0x8d028086, 0x00, "Intel Wellsburg", 0},
- {0x8d048086, 0x00, "Intel Wellsburg (RAID)", 0},
- {0x8d068086, 0x00, "Intel Wellsburg (RAID)", 0},
- {0x8d628086, 0x00, "Intel Wellsburg", 0},
- {0x8d648086, 0x00, "Intel Wellsburg (RAID)", 0},
- {0x8d668086, 0x00, "Intel Wellsburg (RAID)", 0},
- {0x8d6e8086, 0x00, "Intel Wellsburg (RAID)", 0},
- {0x9c028086, 0x00, "Intel Lynx Point-LP", 0},
- {0x9c038086, 0x00, "Intel Lynx Point-LP", 0},
- {0x9c048086, 0x00, "Intel Lynx Point-LP (RAID)", 0},
- {0x9c058086, 0x00, "Intel Lynx Point-LP (RAID)", 0},
- {0x9c068086, 0x00, "Intel Lynx Point-LP (RAID)", 0},
- {0x9c078086, 0x00, "Intel Lynx Point-LP (RAID)", 0},
- {0x9c0e8086, 0x00, "Intel Lynx Point-LP (RAID)", 0},
- {0x9c0f8086, 0x00, "Intel Lynx Point-LP (RAID)", 0},
- {0x23238086, 0x00, "Intel DH89xxCC", 0},
- {0x2360197b, 0x00, "JMicron JMB360", 0},
- {0x2361197b, 0x00, "JMicron JMB361", AHCI_Q_NOFORCE | AHCI_Q_1CH},
- {0x2362197b, 0x00, "JMicron JMB362", 0},
- {0x2363197b, 0x00, "JMicron JMB363", AHCI_Q_NOFORCE},
- {0x2365197b, 0x00, "JMicron JMB365", AHCI_Q_NOFORCE},
- {0x2366197b, 0x00, "JMicron JMB366", AHCI_Q_NOFORCE},
- {0x2368197b, 0x00, "JMicron JMB368", AHCI_Q_NOFORCE},
- {0x611111ab, 0x00, "Marvell 88SE6111", AHCI_Q_NOFORCE | AHCI_Q_1CH |
- AHCI_Q_EDGEIS},
- {0x612111ab, 0x00, "Marvell 88SE6121", AHCI_Q_NOFORCE | AHCI_Q_2CH |
- AHCI_Q_EDGEIS | AHCI_Q_NONCQ | AHCI_Q_NOCOUNT},
- {0x614111ab, 0x00, "Marvell 88SE6141", AHCI_Q_NOFORCE | AHCI_Q_4CH |
- AHCI_Q_EDGEIS | AHCI_Q_NONCQ | AHCI_Q_NOCOUNT},
- {0x614511ab, 0x00, "Marvell 88SE6145", AHCI_Q_NOFORCE | AHCI_Q_4CH |
- AHCI_Q_EDGEIS | AHCI_Q_NONCQ | AHCI_Q_NOCOUNT},
- {0x91201b4b, 0x00, "Marvell 88SE912x", AHCI_Q_EDGEIS},
- {0x91231b4b, 0x11, "Marvell 88SE912x", AHCI_Q_ALTSIG},
- {0x91231b4b, 0x00, "Marvell 88SE912x", AHCI_Q_EDGEIS|AHCI_Q_SATA2},
- {0x91251b4b, 0x00, "Marvell 88SE9125", 0},
- {0x91281b4b, 0x00, "Marvell 88SE9128", AHCI_Q_ALTSIG},
- {0x91301b4b, 0x00, "Marvell 88SE9130", AHCI_Q_ALTSIG},
- {0x91721b4b, 0x00, "Marvell 88SE9172", 0},
- {0x91821b4b, 0x00, "Marvell 88SE9182", 0},
- {0x91831b4b, 0x00, "Marvell 88SS9183", 0},
- {0x91a01b4b, 0x00, "Marvell 88SE91Ax", 0},
- {0x92151b4b, 0x00, "Marvell 88SE9215", 0},
- {0x92201b4b, 0x00, "Marvell 88SE9220", AHCI_Q_ALTSIG},
- {0x92301b4b, 0x00, "Marvell 88SE9230", AHCI_Q_ALTSIG},
- {0x92351b4b, 0x00, "Marvell 88SE9235", 0},
- {0x06201103, 0x00, "HighPoint RocketRAID 620", 0},
- {0x06201b4b, 0x00, "HighPoint RocketRAID 620", 0},
- {0x06221103, 0x00, "HighPoint RocketRAID 622", 0},
- {0x06221b4b, 0x00, "HighPoint RocketRAID 622", 0},
- {0x06401103, 0x00, "HighPoint RocketRAID 640", 0},
- {0x06401b4b, 0x00, "HighPoint RocketRAID 640", 0},
- {0x06441103, 0x00, "HighPoint RocketRAID 644", 0},
- {0x06441b4b, 0x00, "HighPoint RocketRAID 644", 0},
- {0x06411103, 0x00, "HighPoint RocketRAID 640L", 0},
- {0x06421103, 0x00, "HighPoint RocketRAID 642L", 0},
- {0x06451103, 0x00, "HighPoint RocketRAID 644L", 0},
- {0x044c10de, 0x00, "NVIDIA MCP65", AHCI_Q_NOAA},
- {0x044d10de, 0x00, "NVIDIA MCP65", AHCI_Q_NOAA},
- {0x044e10de, 0x00, "NVIDIA MCP65", AHCI_Q_NOAA},
- {0x044f10de, 0x00, "NVIDIA MCP65", AHCI_Q_NOAA},
- {0x045c10de, 0x00, "NVIDIA MCP65", AHCI_Q_NOAA},
- {0x045d10de, 0x00, "NVIDIA MCP65", AHCI_Q_NOAA},
- {0x045e10de, 0x00, "NVIDIA MCP65", AHCI_Q_NOAA},
- {0x045f10de, 0x00, "NVIDIA MCP65", AHCI_Q_NOAA},
- {0x055010de, 0x00, "NVIDIA MCP67", AHCI_Q_NOAA},
- {0x055110de, 0x00, "NVIDIA MCP67", AHCI_Q_NOAA},
- {0x055210de, 0x00, "NVIDIA MCP67", AHCI_Q_NOAA},
- {0x055310de, 0x00, "NVIDIA MCP67", AHCI_Q_NOAA},
- {0x055410de, 0x00, "NVIDIA MCP67", AHCI_Q_NOAA},
- {0x055510de, 0x00, "NVIDIA MCP67", AHCI_Q_NOAA},
- {0x055610de, 0x00, "NVIDIA MCP67", AHCI_Q_NOAA},
- {0x055710de, 0x00, "NVIDIA MCP67", AHCI_Q_NOAA},
- {0x055810de, 0x00, "NVIDIA MCP67", AHCI_Q_NOAA},
- {0x055910de, 0x00, "NVIDIA MCP67", AHCI_Q_NOAA},
- {0x055A10de, 0x00, "NVIDIA MCP67", AHCI_Q_NOAA},
- {0x055B10de, 0x00, "NVIDIA MCP67", AHCI_Q_NOAA},
- {0x058410de, 0x00, "NVIDIA MCP67", AHCI_Q_NOAA},
- {0x07f010de, 0x00, "NVIDIA MCP73", AHCI_Q_NOAA},
- {0x07f110de, 0x00, "NVIDIA MCP73", AHCI_Q_NOAA},
- {0x07f210de, 0x00, "NVIDIA MCP73", AHCI_Q_NOAA},
- {0x07f310de, 0x00, "NVIDIA MCP73", AHCI_Q_NOAA},
- {0x07f410de, 0x00, "NVIDIA MCP73", AHCI_Q_NOAA},
- {0x07f510de, 0x00, "NVIDIA MCP73", AHCI_Q_NOAA},
- {0x07f610de, 0x00, "NVIDIA MCP73", AHCI_Q_NOAA},
- {0x07f710de, 0x00, "NVIDIA MCP73", AHCI_Q_NOAA},
- {0x07f810de, 0x00, "NVIDIA MCP73", AHCI_Q_NOAA},
- {0x07f910de, 0x00, "NVIDIA MCP73", AHCI_Q_NOAA},
- {0x07fa10de, 0x00, "NVIDIA MCP73", AHCI_Q_NOAA},
- {0x07fb10de, 0x00, "NVIDIA MCP73", AHCI_Q_NOAA},
- {0x0ad010de, 0x00, "NVIDIA MCP77", AHCI_Q_NOAA},
- {0x0ad110de, 0x00, "NVIDIA MCP77", AHCI_Q_NOAA},
- {0x0ad210de, 0x00, "NVIDIA MCP77", AHCI_Q_NOAA},
- {0x0ad310de, 0x00, "NVIDIA MCP77", AHCI_Q_NOAA},
- {0x0ad410de, 0x00, "NVIDIA MCP77", AHCI_Q_NOAA},
- {0x0ad510de, 0x00, "NVIDIA MCP77", AHCI_Q_NOAA},
- {0x0ad610de, 0x00, "NVIDIA MCP77", AHCI_Q_NOAA},
- {0x0ad710de, 0x00, "NVIDIA MCP77", AHCI_Q_NOAA},
- {0x0ad810de, 0x00, "NVIDIA MCP77", AHCI_Q_NOAA},
- {0x0ad910de, 0x00, "NVIDIA MCP77", AHCI_Q_NOAA},
- {0x0ada10de, 0x00, "NVIDIA MCP77", AHCI_Q_NOAA},
- {0x0adb10de, 0x00, "NVIDIA MCP77", AHCI_Q_NOAA},
- {0x0ab410de, 0x00, "NVIDIA MCP79", AHCI_Q_NOAA},
- {0x0ab510de, 0x00, "NVIDIA MCP79", AHCI_Q_NOAA},
- {0x0ab610de, 0x00, "NVIDIA MCP79", AHCI_Q_NOAA},
- {0x0ab710de, 0x00, "NVIDIA MCP79", AHCI_Q_NOAA},
- {0x0ab810de, 0x00, "NVIDIA MCP79", AHCI_Q_NOAA},
- {0x0ab910de, 0x00, "NVIDIA MCP79", AHCI_Q_NOAA},
- {0x0aba10de, 0x00, "NVIDIA MCP79", AHCI_Q_NOAA},
- {0x0abb10de, 0x00, "NVIDIA MCP79", AHCI_Q_NOAA},
- {0x0abc10de, 0x00, "NVIDIA MCP79", AHCI_Q_NOAA},
- {0x0abd10de, 0x00, "NVIDIA MCP79", AHCI_Q_NOAA},
- {0x0abe10de, 0x00, "NVIDIA MCP79", AHCI_Q_NOAA},
- {0x0abf10de, 0x00, "NVIDIA MCP79", AHCI_Q_NOAA},
- {0x0d8410de, 0x00, "NVIDIA MCP89", AHCI_Q_NOAA},
- {0x0d8510de, 0x00, "NVIDIA MCP89", AHCI_Q_NOFORCE|AHCI_Q_NOAA},
- {0x0d8610de, 0x00, "NVIDIA MCP89", AHCI_Q_NOAA},
- {0x0d8710de, 0x00, "NVIDIA MCP89", AHCI_Q_NOAA},
- {0x0d8810de, 0x00, "NVIDIA MCP89", AHCI_Q_NOAA},
- {0x0d8910de, 0x00, "NVIDIA MCP89", AHCI_Q_NOAA},
- {0x0d8a10de, 0x00, "NVIDIA MCP89", AHCI_Q_NOAA},
- {0x0d8b10de, 0x00, "NVIDIA MCP89", AHCI_Q_NOAA},
- {0x0d8c10de, 0x00, "NVIDIA MCP89", AHCI_Q_NOAA},
- {0x0d8d10de, 0x00, "NVIDIA MCP89", AHCI_Q_NOAA},
- {0x0d8e10de, 0x00, "NVIDIA MCP89", AHCI_Q_NOAA},
- {0x0d8f10de, 0x00, "NVIDIA MCP89", AHCI_Q_NOAA},
- {0x3781105a, 0x00, "Promise TX8660", 0},
- {0x33491106, 0x00, "VIA VT8251", AHCI_Q_NOPMP|AHCI_Q_NONCQ},
- {0x62871106, 0x00, "VIA VT8251", AHCI_Q_NOPMP|AHCI_Q_NONCQ},
- {0x11841039, 0x00, "SiS 966", 0},
- {0x11851039, 0x00, "SiS 968", 0},
- {0x01861039, 0x00, "SiS 968", 0},
- {0x00000000, 0x00, NULL, 0}
-};
-
#define recovery_type spriv_field0
#define RECOVERY_NONE 0
#define RECOVERY_READ_LOG 1
@@ -378,92 +99,71 @@
#define RECOVERY_REQUEST_SENSE 2
#define recovery_slot spriv_field1
-static int force_ahci = 1;
-TUNABLE_INT("hw.ahci.force", &force_ahci);
-
-static int
-ahci_probe(device_t dev)
+int
+ahci_ctlr_setup(device_t dev)
{
- char buf[64];
- int i, valid = 0;
- uint32_t devid = pci_get_devid(dev);
- uint8_t revid = pci_get_revid(dev);
-
- /* Is this a possible AHCI candidate? */
- if (pci_get_class(dev) == PCIC_STORAGE &&
- pci_get_subclass(dev) == PCIS_STORAGE_SATA &&
- pci_get_progif(dev) == PCIP_STORAGE_SATA_AHCI_1_0)
- valid = 1;
- /* Is this a known AHCI chip? */
- for (i = 0; ahci_ids[i].id != 0; i++) {
- if (ahci_ids[i].id == devid &&
- ahci_ids[i].rev <= revid &&
- (valid || (force_ahci == 1 &&
- !(ahci_ids[i].quirks & AHCI_Q_NOFORCE)))) {
- /* Do not attach JMicrons with single PCI function. */
- if (pci_get_vendor(dev) == 0x197b &&
- (pci_read_config(dev, 0xdf, 1) & 0x40) == 0)
- return (ENXIO);
- snprintf(buf, sizeof(buf), "%s AHCI SATA controller",
- ahci_ids[i].name);
- device_set_desc_copy(dev, buf);
- return (BUS_PROBE_VENDOR);
+ struct ahci_controller *ctlr = device_get_softc(dev);
+ /* Clear interrupts */
+ ATA_OUTL(ctlr->r_mem, AHCI_IS, ATA_INL(ctlr->r_mem, AHCI_IS));
+ /* Configure CCC */
+ if (ctlr->ccc) {
+ ATA_OUTL(ctlr->r_mem, AHCI_CCCP, ATA_INL(ctlr->r_mem, AHCI_PI));
+ ATA_OUTL(ctlr->r_mem, AHCI_CCCC,
+ (ctlr->ccc << AHCI_CCCC_TV_SHIFT) |
+ (4 << AHCI_CCCC_CC_SHIFT) |
+ AHCI_CCCC_EN);
+ ctlr->cccv = (ATA_INL(ctlr->r_mem, AHCI_CCCC) &
+ AHCI_CCCC_INT_MASK) >> AHCI_CCCC_INT_SHIFT;
+ if (bootverbose) {
+ device_printf(dev,
+ "CCC with %dms/4cmd enabled on vector %d\n",
+ ctlr->ccc, ctlr->cccv);
}
}
- if (!valid)
- return (ENXIO);
- device_set_desc_copy(dev, "AHCI SATA controller");
- return (BUS_PROBE_VENDOR);
+ /* Enable AHCI interrupts */
+ ATA_OUTL(ctlr->r_mem, AHCI_GHC,
+ ATA_INL(ctlr->r_mem, AHCI_GHC) | AHCI_GHC_IE);
+ return (0);
}
-static int
-ahci_ata_probe(device_t dev)
+int
+ahci_ctlr_reset(device_t dev)
{
- char buf[64];
- int i;
- uint32_t devid = pci_get_devid(dev);
- uint8_t revid = pci_get_revid(dev);
+ struct ahci_controller *ctlr = device_get_softc(dev);
+ int timeout;
- if ((intptr_t)device_get_ivars(dev) >= 0)
+ /* Enable AHCI mode */
+ ATA_OUTL(ctlr->r_mem, AHCI_GHC, AHCI_GHC_AE);
+ /* Reset AHCI controller */
+ ATA_OUTL(ctlr->r_mem, AHCI_GHC, AHCI_GHC_AE|AHCI_GHC_HR);
+ for (timeout = 1000; timeout > 0; timeout--) {
+ DELAY(1000);
+ if ((ATA_INL(ctlr->r_mem, AHCI_GHC) & AHCI_GHC_HR) == 0)
+ break;
+ }
+ if (timeout == 0) {
+ device_printf(dev, "AHCI controller reset failure\n");
return (ENXIO);
- /* Is this a known AHCI chip? */
- for (i = 0; ahci_ids[i].id != 0; i++) {
- if (ahci_ids[i].id == devid &&
- ahci_ids[i].rev <= revid) {
- snprintf(buf, sizeof(buf), "%s AHCI SATA controller",
- ahci_ids[i].name);
- device_set_desc_copy(dev, buf);
- return (BUS_PROBE_VENDOR);
- }
}
- device_set_desc_copy(dev, "AHCI SATA controller");
- return (BUS_PROBE_VENDOR);
+ /* Reenable AHCI mode */
+ ATA_OUTL(ctlr->r_mem, AHCI_GHC, AHCI_GHC_AE);
+ return (0);
}
-static int
+
+int
ahci_attach(device_t dev)
{
struct ahci_controller *ctlr = device_get_softc(dev);
+ int error, i, speed, unit;
+ uint32_t u, version;
device_t child;
- int error, unit, speed, i;
- uint32_t devid = pci_get_devid(dev);
- uint8_t revid = pci_get_revid(dev);
- u_int32_t version;
ctlr->dev = dev;
- i = 0;
- while (ahci_ids[i].id != 0 &&
- (ahci_ids[i].id != devid ||
- ahci_ids[i].rev > revid))
- i++;
- ctlr->quirks = ahci_ids[i].quirks;
+ ctlr->ccc = 0;
resource_int_value(device_get_name(dev),
device_get_unit(dev), "ccc", &ctlr->ccc);
- /* if we have a memory BAR(5) we are likely on an AHCI part */
- ctlr->r_rid = PCIR_BAR(5);
- if (!(ctlr->r_mem = bus_alloc_resource_any(dev, SYS_RES_MEMORY,
- &ctlr->r_rid, RF_ACTIVE)))
- return ENXIO;
+
/* Setup our own memory management for channels. */
ctlr->sc_iomem.rm_start = rman_get_start(ctlr->r_mem);
ctlr->sc_iomem.rm_end = rman_get_end(ctlr->r_mem);
@@ -479,13 +179,6 @@
rman_fini(&ctlr->sc_iomem);
return (error);
}
- pci_enable_busmaster(dev);
- /* Reset controller */
- if ((error = ahci_ctlr_reset(dev)) != 0) {
- bus_release_resource(dev, SYS_RES_MEMORY, ctlr->r_rid, ctlr->r_mem);
- rman_fini(&ctlr->sc_iomem);
- return (error);
- };
/* Get the HW capabilities */
version = ATA_INL(ctlr->r_mem, AHCI_VS);
ctlr->caps = ATA_INL(ctlr->r_mem, AHCI_CAP);
@@ -522,11 +215,10 @@
ctlr->caps &= ~AHCI_CAP_SNCQ;
if ((ctlr->caps & AHCI_CAP_CCCS) == 0)
ctlr->ccc = 0;
- mtx_init(&ctlr->em_mtx, "AHCI EM lock", NULL, MTX_DEF);
ctlr->emloc = ATA_INL(ctlr->r_mem, AHCI_EM_LOC);
/* Create controller-wide DMA tag. */
- if (bus_dma_tag_create(bus_get_dma_tag(dev), 0, 0,
+ if (bus_dma_tag_create(bus_get_dma_tag(dev), 1, 0,
(ctlr->caps & AHCI_CAP_64BIT) ? BUS_SPACE_MAXADDR :
BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL,
BUS_SPACE_MAXSIZE, BUS_SPACE_UNRESTRICTED, BUS_SPACE_MAXSIZE,
@@ -534,17 +226,26 @@
bus_release_resource(dev, SYS_RES_MEMORY, ctlr->r_rid,
ctlr->r_mem);
rman_fini(&ctlr->sc_iomem);
- return ENXIO;
+ return (ENXIO);
}
ahci_ctlr_setup(dev);
+
/* Setup interrupts. */
- if (ahci_setup_interrupt(dev)) {
+ if ((error = ahci_setup_interrupt(dev)) != 0) {
bus_dma_tag_destroy(ctlr->dma_tag);
- bus_release_resource(dev, SYS_RES_MEMORY, ctlr->r_rid, ctlr->r_mem);
+ bus_release_resource(dev, SYS_RES_MEMORY, ctlr->r_rid,
+ ctlr->r_mem);
rman_fini(&ctlr->sc_iomem);
- return ENXIO;
+ return (error);
}
+
+ i = 0;
+ for (u = ctlr->ichannels; u != 0; u >>= 1)
+ i += (u & 1);
+ ctlr->direct = (ctlr->msi && (ctlr->numirqs > 1 || i <= 3));
+ resource_int_value(device_get_name(dev), device_get_unit(dev),
+ "direct", &ctlr->direct);
/* Announce HW capabilities. */
speed = (ctlr->caps & AHCI_CAP_ISS) >> AHCI_CAP_ISS_SHIFT;
device_printf(dev,
@@ -588,22 +289,14 @@
(ctlr->caps & AHCI_CAP_NPMASK) + 1);
}
if (bootverbose && version >= 0x00010200) {
- device_printf(dev, "Caps2:%s%s%s\n",
+ device_printf(dev, "Caps2:%s%s%s%s%s%s\n",
+ (ctlr->caps2 & AHCI_CAP2_DESO) ? " DESO":"",
+ (ctlr->caps2 & AHCI_CAP2_SADM) ? " SADM":"",
+ (ctlr->caps2 & AHCI_CAP2_SDS) ? " SDS":"",
(ctlr->caps2 & AHCI_CAP2_APST) ? " APST":"",
(ctlr->caps2 & AHCI_CAP2_NVMP) ? " NVMP":"",
(ctlr->caps2 & AHCI_CAP2_BOH) ? " BOH":"");
}
- if (bootverbose && (ctlr->caps & AHCI_CAP_EMS)) {
- device_printf(dev, "EM Caps:%s%s%s%s%s%s%s%s\n",
- (ctlr->capsem & AHCI_EM_PM) ? " PM":"",
- (ctlr->capsem & AHCI_EM_ALHD) ? " ALHD":"",
- (ctlr->capsem & AHCI_EM_XMT) ? " XMT":"",
- (ctlr->capsem & AHCI_EM_SMB) ? " SMB":"",
- (ctlr->capsem & AHCI_EM_SGPIO) ? " SGPIO":"",
- (ctlr->capsem & AHCI_EM_SES2) ? " SES-2":"",
- (ctlr->capsem & AHCI_EM_SAFTE) ? " SAF-TE":"",
- (ctlr->capsem & AHCI_EM_LED) ? " LED":"");
- }
/* Attach all channels on this controller */
for (unit = 0; unit < ctlr->channels; unit++) {
child = device_add_child(dev, "ahcich", -1);
@@ -615,11 +308,18 @@
if ((ctlr->ichannels & (1 << unit)) == 0)
device_disable(child);
}
+ if (ctlr->caps & AHCI_CAP_EMS) {
+ child = device_add_child(dev, "ahciem", -1);
+ if (child == NULL)
+ device_printf(dev, "failed to add enclosure device\n");
+ else
+ device_set_ivars(child, (void *)(intptr_t)-1);
+ }
bus_generic_attach(dev);
- return 0;
+ return (0);
}
-static int
+int
ahci_detach(device_t dev)
{
struct ahci_controller *ctlr = device_get_softc(dev);
@@ -637,117 +337,20 @@
ctlr->irqs[i].r_irq_rid, ctlr->irqs[i].r_irq);
}
}
- pci_release_msi(dev);
bus_dma_tag_destroy(ctlr->dma_tag);
/* Free memory. */
rman_fini(&ctlr->sc_iomem);
if (ctlr->r_mem)
bus_release_resource(dev, SYS_RES_MEMORY, ctlr->r_rid, ctlr->r_mem);
- mtx_destroy(&ctlr->em_mtx);
return (0);
}
-static int
-ahci_ctlr_reset(device_t dev)
-{
- struct ahci_controller *ctlr = device_get_softc(dev);
- int timeout;
-
- if (pci_read_config(dev, 0x00, 4) == 0x28298086 &&
- (pci_read_config(dev, 0x92, 1) & 0xfe) == 0x04)
- pci_write_config(dev, 0x92, 0x01, 1);
- /* Enable AHCI mode */
- ATA_OUTL(ctlr->r_mem, AHCI_GHC, AHCI_GHC_AE);
- /* Reset AHCI controller */
- ATA_OUTL(ctlr->r_mem, AHCI_GHC, AHCI_GHC_AE|AHCI_GHC_HR);
- for (timeout = 1000; timeout > 0; timeout--) {
- DELAY(1000);
- if ((ATA_INL(ctlr->r_mem, AHCI_GHC) & AHCI_GHC_HR) == 0)
- break;
- }
- if (timeout == 0) {
- device_printf(dev, "AHCI controller reset failure\n");
- return ENXIO;
- }
- /* Reenable AHCI mode */
- ATA_OUTL(ctlr->r_mem, AHCI_GHC, AHCI_GHC_AE);
- return (0);
-}
-
-static int
-ahci_ctlr_setup(device_t dev)
-{
- struct ahci_controller *ctlr = device_get_softc(dev);
- /* Clear interrupts */
- ATA_OUTL(ctlr->r_mem, AHCI_IS, ATA_INL(ctlr->r_mem, AHCI_IS));
- /* Configure CCC */
- if (ctlr->ccc) {
- ATA_OUTL(ctlr->r_mem, AHCI_CCCP, ATA_INL(ctlr->r_mem, AHCI_PI));
- ATA_OUTL(ctlr->r_mem, AHCI_CCCC,
- (ctlr->ccc << AHCI_CCCC_TV_SHIFT) |
- (4 << AHCI_CCCC_CC_SHIFT) |
- AHCI_CCCC_EN);
- ctlr->cccv = (ATA_INL(ctlr->r_mem, AHCI_CCCC) &
- AHCI_CCCC_INT_MASK) >> AHCI_CCCC_INT_SHIFT;
- if (bootverbose) {
- device_printf(dev,
- "CCC with %dms/4cmd enabled on vector %d\n",
- ctlr->ccc, ctlr->cccv);
- }
- }
- /* Enable AHCI interrupts */
- ATA_OUTL(ctlr->r_mem, AHCI_GHC,
- ATA_INL(ctlr->r_mem, AHCI_GHC) | AHCI_GHC_IE);
- return (0);
-}
-
-static int
-ahci_suspend(device_t dev)
-{
- struct ahci_controller *ctlr = device_get_softc(dev);
-
- bus_generic_suspend(dev);
- /* Disable interupts, so the state change(s) doesn't trigger */
- ATA_OUTL(ctlr->r_mem, AHCI_GHC,
- ATA_INL(ctlr->r_mem, AHCI_GHC) & (~AHCI_GHC_IE));
- return 0;
-}
-
-static int
-ahci_resume(device_t dev)
-{
- int res;
-
- if ((res = ahci_ctlr_reset(dev)) != 0)
- return (res);
- ahci_ctlr_setup(dev);
- return (bus_generic_resume(dev));
-}
-
-static int
+int
ahci_setup_interrupt(device_t dev)
{
struct ahci_controller *ctlr = device_get_softc(dev);
- int i, msi = 1;
+ int i;
- /* Process hints. */
- if (ctlr->quirks & AHCI_Q_NOMSI)
- msi = 0;
- resource_int_value(device_get_name(dev),
- device_get_unit(dev), "msi", &msi);
- if (msi < 0)
- msi = 0;
- else if (msi == 1)
- msi = min(1, pci_msi_count(dev));
- else if (msi > 1)
- msi = pci_msi_count(dev);
- /* Allocate MSI if needed/present. */
- if (msi && pci_alloc_msi(dev, &msi) == 0) {
- ctlr->numirqs = msi;
- } else {
- msi = 0;
- ctlr->numirqs = 1;
- }
/* Check for single MSI vector fallback. */
if (ctlr->numirqs > 1 &&
(ATA_INL(ctlr->r_mem, AHCI_GHC) & AHCI_GHC_MRSM) != 0) {
@@ -754,14 +357,25 @@
device_printf(dev, "Falling back to one MSI\n");
ctlr->numirqs = 1;
}
+
+ /* Ensure we don't overrun irqs. */
+ if (ctlr->numirqs > AHCI_MAX_IRQS) {
+ device_printf(dev, "Too many irqs %d > %d (clamping)\n",
+ ctlr->numirqs, AHCI_MAX_IRQS);
+ ctlr->numirqs = AHCI_MAX_IRQS;
+ }
+
/* Allocate all IRQs. */
for (i = 0; i < ctlr->numirqs; i++) {
ctlr->irqs[i].ctlr = ctlr;
- ctlr->irqs[i].r_irq_rid = i + (msi ? 1 : 0);
- if (ctlr->numirqs == 1 || i >= ctlr->channels ||
+ ctlr->irqs[i].r_irq_rid = i + (ctlr->msi ? 1 : 0);
+ if (ctlr->channels == 1 && !ctlr->ccc && ctlr->msi)
+ ctlr->irqs[i].mode = AHCI_IRQ_MODE_ONE;
+ else if (ctlr->numirqs == 1 || i >= ctlr->channels ||
(ctlr->ccc && i == ctlr->cccv))
ctlr->irqs[i].mode = AHCI_IRQ_MODE_ALL;
- else if (i == ctlr->numirqs - 1)
+ else if (ctlr->channels > ctlr->numirqs &&
+ i == ctlr->numirqs - 1)
ctlr->irqs[i].mode = AHCI_IRQ_MODE_AFTER;
else
ctlr->irqs[i].mode = AHCI_IRQ_MODE_ONE;
@@ -768,14 +382,16 @@
if (!(ctlr->irqs[i].r_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ,
&ctlr->irqs[i].r_irq_rid, RF_SHAREABLE | RF_ACTIVE))) {
device_printf(dev, "unable to map interrupt\n");
- return ENXIO;
+ return (ENXIO);
}
if ((bus_setup_intr(dev, ctlr->irqs[i].r_irq, ATA_INTR_FLAGS, NULL,
- (ctlr->irqs[i].mode == AHCI_IRQ_MODE_ONE) ? ahci_intr_one : ahci_intr,
+ (ctlr->irqs[i].mode != AHCI_IRQ_MODE_ONE) ? ahci_intr :
+ ((ctlr->quirks & AHCI_Q_EDGEIS) ? ahci_intr_one_edge :
+ ahci_intr_one),
&ctlr->irqs[i], &ctlr->irqs[i].handle))) {
/* SOS XXX release r_irq */
device_printf(dev, "unable to setup interrupt\n");
- return ENXIO;
+ return (ENXIO);
}
if (ctlr->numirqs > 1) {
bus_describe_intr(dev, ctlr->irqs[i].r_irq,
@@ -808,6 +424,7 @@
} else { /* AHCI_IRQ_MODE_AFTER */
unit = irq->r_irq_rid - 1;
is = ATA_INL(ctlr->r_mem, AHCI_IS);
+ is &= (0xffffffff << unit);
}
/* CCC interrupt is edge triggered. */
if (ctlr->ccc)
@@ -840,31 +457,60 @@
int unit;
unit = irq->r_irq_rid - 1;
- /* Some controllers have edge triggered IS. */
- if (ctlr->quirks & AHCI_Q_EDGEIS)
- ATA_OUTL(ctlr->r_mem, AHCI_IS, 1 << unit);
if ((arg = ctlr->interrupt[unit].argument))
ctlr->interrupt[unit].function(arg);
/* AHCI declares level triggered IS. */
- if (!(ctlr->quirks & AHCI_Q_EDGEIS))
- ATA_OUTL(ctlr->r_mem, AHCI_IS, 1 << unit);
+ ATA_OUTL(ctlr->r_mem, AHCI_IS, 1 << unit);
}
-static struct resource *
+static void
+ahci_intr_one_edge(void *data)
+{
+ struct ahci_controller_irq *irq = data;
+ struct ahci_controller *ctlr = irq->ctlr;
+ void *arg;
+ int unit;
+
+ unit = irq->r_irq_rid - 1;
+ /* Some controllers have edge triggered IS. */
+ ATA_OUTL(ctlr->r_mem, AHCI_IS, 1 << unit);
+ if ((arg = ctlr->interrupt[unit].argument))
+ ctlr->interrupt[unit].function(arg);
+}
+
+struct resource *
ahci_alloc_resource(device_t dev, device_t child, int type, int *rid,
- u_long start, u_long end, u_long count, u_int flags)
+ u_long start, u_long end, u_long count, u_int flags)
{
struct ahci_controller *ctlr = device_get_softc(dev);
- int unit = ((struct ahci_channel *)device_get_softc(child))->unit;
- struct resource *res = NULL;
- int offset = AHCI_OFFSET + (unit << 7);
+ struct resource *res;
long st;
+ int offset, size, unit;
+ unit = (intptr_t)device_get_ivars(child);
+ res = NULL;
switch (type) {
case SYS_RES_MEMORY:
+ if (unit >= 0) {
+ offset = AHCI_OFFSET + (unit << 7);
+ size = 128;
+ } else if (*rid == 0) {
+ offset = AHCI_EM_CTL;
+ size = 4;
+ } else {
+ offset = (ctlr->emloc & 0xffff0000) >> 14;
+ size = (ctlr->emloc & 0x0000ffff) << 2;
+ if (*rid != 1) {
+ if (*rid == 2 && (ctlr->capsem &
+ (AHCI_EM_XMT | AHCI_EM_SMB)) == 0)
+ offset += size;
+ else
+ break;
+ }
+ }
st = rman_get_start(ctlr->r_mem);
res = rman_reserve_resource(&ctlr->sc_iomem, st + offset,
- st + offset + 127, 128, RF_ACTIVE, child);
+ st + offset + size - 1, size, RF_ACTIVE, child);
if (res) {
bus_space_handle_t bsh;
bus_space_tag_t bst;
@@ -883,9 +529,9 @@
return (res);
}
-static int
+int
ahci_release_resource(device_t dev, device_t child, int type, int rid,
- struct resource *r)
+ struct resource *r)
{
switch (type) {
@@ -894,16 +540,16 @@
return (0);
case SYS_RES_IRQ:
if (rid != ATA_IRQ_RID)
- return ENOENT;
+ return (ENOENT);
return (0);
}
return (EINVAL);
}
-static int
+int
ahci_setup_intr(device_t dev, device_t child, struct resource *irq,
- int flags, driver_filter_t *filter, driver_intr_t *function,
- void *argument, void **cookiep)
+ int flags, driver_filter_t *filter, driver_intr_t *function,
+ void *argument, void **cookiep)
{
struct ahci_controller *ctlr = device_get_softc(dev);
int unit = (intptr_t)device_get_ivars(child);
@@ -917,9 +563,9 @@
return (0);
}
-static int
+int
ahci_teardown_intr(device_t dev, device_t child, struct resource *irq,
- void *cookie)
+ void *cookie)
{
struct ahci_controller *ctlr = device_get_softc(dev);
int unit = (intptr_t)device_get_ivars(child);
@@ -929,30 +575,32 @@
return (0);
}
-static int
+int
ahci_print_child(device_t dev, device_t child)
{
- int retval;
+ int retval, channel;
retval = bus_print_child_header(dev, child);
- retval += printf(" at channel %d",
- (int)(intptr_t)device_get_ivars(child));
+ channel = (int)(intptr_t)device_get_ivars(child);
+ if (channel >= 0)
+ retval += printf(" at channel %d", channel);
retval += bus_print_child_footer(dev, child);
-
return (retval);
}
-static int
+int
ahci_child_location_str(device_t dev, device_t child, char *buf,
size_t buflen)
{
+ int channel;
- snprintf(buf, buflen, "channel=%d",
- (int)(intptr_t)device_get_ivars(child));
+ channel = (int)(intptr_t)device_get_ivars(child);
+ if (channel >= 0)
+ snprintf(buf, buflen, "channel=%d", channel);
return (0);
}
-static bus_dma_tag_t
+bus_dma_tag_t
ahci_get_dma_tag(device_t dev, device_t child)
{
struct ahci_controller *ctlr = device_get_softc(dev);
@@ -960,57 +608,12 @@
return (ctlr->dma_tag);
}
-devclass_t ahci_devclass;
-static device_method_t ahci_methods[] = {
- DEVMETHOD(device_probe, ahci_probe),
- DEVMETHOD(device_attach, ahci_attach),
- DEVMETHOD(device_detach, ahci_detach),
- DEVMETHOD(device_suspend, ahci_suspend),
- DEVMETHOD(device_resume, ahci_resume),
- DEVMETHOD(bus_print_child, ahci_print_child),
- DEVMETHOD(bus_alloc_resource, ahci_alloc_resource),
- DEVMETHOD(bus_release_resource, ahci_release_resource),
- DEVMETHOD(bus_setup_intr, ahci_setup_intr),
- DEVMETHOD(bus_teardown_intr,ahci_teardown_intr),
- DEVMETHOD(bus_child_location_str, ahci_child_location_str),
- DEVMETHOD(bus_get_dma_tag, ahci_get_dma_tag),
- { 0, 0 }
-};
-static driver_t ahci_driver = {
- "ahci",
- ahci_methods,
- sizeof(struct ahci_controller)
-};
-DRIVER_MODULE(ahci, pci, ahci_driver, ahci_devclass, NULL, NULL);
-static device_method_t ahci_ata_methods[] = {
- DEVMETHOD(device_probe, ahci_ata_probe),
- DEVMETHOD(device_attach, ahci_attach),
- DEVMETHOD(device_detach, ahci_detach),
- DEVMETHOD(device_suspend, ahci_suspend),
- DEVMETHOD(device_resume, ahci_resume),
- DEVMETHOD(bus_print_child, ahci_print_child),
- DEVMETHOD(bus_alloc_resource, ahci_alloc_resource),
- DEVMETHOD(bus_release_resource, ahci_release_resource),
- DEVMETHOD(bus_setup_intr, ahci_setup_intr),
- DEVMETHOD(bus_teardown_intr,ahci_teardown_intr),
- DEVMETHOD(bus_child_location_str, ahci_child_location_str),
- DEVMETHOD_END
-};
-static driver_t ahci_ata_driver = {
- "ahci",
- ahci_ata_methods,
- sizeof(struct ahci_controller)
-};
-DRIVER_MODULE(ahci, atapci, ahci_ata_driver, ahci_devclass, NULL, NULL);
-MODULE_VERSION(ahci, 1);
-MODULE_DEPEND(ahci, cam, 1, 1, 1);
-
static int
ahci_ch_probe(device_t dev)
{
device_set_desc_copy(dev, "AHCI channel");
- return (0);
+ return (BUS_PROBE_DEFAULT);
}
static int
@@ -1021,7 +624,6 @@
struct cam_devq *devq;
int rid, error, i, sata_rev = 0;
u_int32_t version;
- char buf[32];
ch->dev = dev;
ch->unit = (intptr_t)device_get_ivars(dev);
@@ -1028,19 +630,21 @@
ch->caps = ctlr->caps;
ch->caps2 = ctlr->caps2;
ch->quirks = ctlr->quirks;
+ ch->vendorid = ctlr->vendorid;
+ ch->deviceid = ctlr->deviceid;
+ ch->subvendorid = ctlr->subvendorid;
+ ch->subdeviceid = ctlr->subdeviceid;
ch->numslots = ((ch->caps & AHCI_CAP_NCS) >> AHCI_CAP_NCS_SHIFT) + 1;
mtx_init(&ch->mtx, "AHCI channel lock", NULL, MTX_DEF);
+ ch->pm_level = 0;
resource_int_value(device_get_name(dev),
device_get_unit(dev), "pm_level", &ch->pm_level);
+ STAILQ_INIT(&ch->doneq);
if (ch->pm_level > 3)
callout_init_mtx(&ch->pm_timer, &ch->mtx, 0);
callout_init_mtx(&ch->reset_timer, &ch->mtx, 0);
- /* Limit speed for my onboard JMicron external port.
- * It is not eSATA really. */
- if (pci_get_devid(ctlr->dev) == 0x2363197b &&
- pci_get_subvendor(ctlr->dev) == 0x1043 &&
- pci_get_subdevice(ctlr->dev) == 0x81e4 &&
- ch->unit == 0)
+ /* JMicron external ports (0) sometimes limited */
+ if ((ctlr->quirks & AHCI_Q_SATA1_UNIT0) && ch->unit == 0)
sata_rev = 1;
if (ch->quirks & AHCI_Q_SATA2)
sata_rev = 2;
@@ -1061,14 +665,29 @@
ch->user[i].caps |= CTS_SATA_CAPS_H_DMAAA |
CTS_SATA_CAPS_H_AN;
}
- rid = ch->unit;
+ rid = 0;
if (!(ch->r_mem = bus_alloc_resource_any(dev, SYS_RES_MEMORY,
&rid, RF_ACTIVE)))
return (ENXIO);
+ ch->chcaps = ATA_INL(ch->r_mem, AHCI_P_CMD);
+ version = ATA_INL(ctlr->r_mem, AHCI_VS);
+ if (version < 0x00010200 && (ctlr->caps & AHCI_CAP_FBSS))
+ ch->chcaps |= AHCI_P_CMD_FBSCP;
+ if (ch->caps2 & AHCI_CAP2_SDS)
+ ch->chscaps = ATA_INL(ch->r_mem, AHCI_P_DEVSLP);
+ if (bootverbose) {
+ device_printf(dev, "Caps:%s%s%s%s%s%s\n",
+ (ch->chcaps & AHCI_P_CMD_HPCP) ? " HPCP":"",
+ (ch->chcaps & AHCI_P_CMD_MPSP) ? " MPSP":"",
+ (ch->chcaps & AHCI_P_CMD_CPD) ? " CPD":"",
+ (ch->chcaps & AHCI_P_CMD_ESP) ? " ESP":"",
+ (ch->chcaps & AHCI_P_CMD_FBSCP) ? " FBSCP":"",
+ (ch->chscaps & AHCI_P_DEVSLP_DSP) ? " DSP":"");
+ }
ahci_dmainit(dev);
ahci_slotsalloc(dev);
+ mtx_lock(&ch->mtx);
ahci_ch_init(dev);
- mtx_lock(&ch->mtx);
rid = ATA_IRQ_RID;
if (!(ch->r_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ,
&rid, RF_SHAREABLE | RF_ACTIVE))) {
@@ -1077,23 +696,12 @@
goto err0;
}
if ((bus_setup_intr(dev, ch->r_irq, ATA_INTR_FLAGS, NULL,
- ahci_ch_intr_locked, dev, &ch->ih))) {
+ ctlr->direct ? ahci_ch_intr_direct : ahci_ch_intr,
+ ch, &ch->ih))) {
device_printf(dev, "Unable to setup interrupt\n");
error = ENXIO;
goto err1;
}
- ch->chcaps = ATA_INL(ch->r_mem, AHCI_P_CMD);
- version = ATA_INL(ctlr->r_mem, AHCI_VS);
- if (version < 0x00010200 && (ctlr->caps & AHCI_CAP_FBSS))
- ch->chcaps |= AHCI_P_CMD_FBSCP;
- if (bootverbose) {
- device_printf(dev, "Caps:%s%s%s%s%s\n",
- (ch->chcaps & AHCI_P_CMD_HPCP) ? " HPCP":"",
- (ch->chcaps & AHCI_P_CMD_MPSP) ? " MPSP":"",
- (ch->chcaps & AHCI_P_CMD_CPD) ? " CPD":"",
- (ch->chcaps & AHCI_P_CMD_ESP) ? " ESP":"",
- (ch->chcaps & AHCI_P_CMD_FBSCP) ? " FBSCP":"");
- }
/* Create the device queue for our SIM. */
devq = cam_simq_alloc(ch->numslots);
if (devq == NULL) {
@@ -1103,8 +711,8 @@
}
/* Construct SIM entry */
ch->sim = cam_sim_alloc(ahciaction, ahcipoll, "ahcich", ch,
- device_get_unit(dev), &ch->mtx,
- min(2, ch->numslots),
+ device_get_unit(dev), (struct mtx *)&ch->mtx,
+ (ch->quirks & AHCI_Q_NOCCS) ? 1 : min(2, ch->numslots),
(ch->caps & AHCI_CAP_SNCQ) ? ch->numslots : 0,
devq);
if (ch->sim == NULL) {
@@ -1127,28 +735,9 @@
if (ch->pm_level > 3) {
callout_reset(&ch->pm_timer,
(ch->pm_level == 4) ? hz / 1000 : hz / 8,
- ahci_ch_pm, dev);
+ ahci_ch_pm, ch);
}
mtx_unlock(&ch->mtx);
- if ((ch->caps & AHCI_CAP_EMS) &&
- (ctlr->capsem & AHCI_EM_LED)) {
- for (i = 0; i < AHCI_NUM_LEDS; i++) {
- ch->leds[i].dev = dev;
- ch->leds[i].num = i;
- }
- if ((ctlr->capsem & AHCI_EM_ALHD) == 0) {
- snprintf(buf, sizeof(buf), "%s.act",
- device_get_nameunit(dev));
- ch->leds[0].led = led_create(ahci_ch_led,
- &ch->leds[0], buf);
- }
- snprintf(buf, sizeof(buf), "%s.locate",
- device_get_nameunit(dev));
- ch->leds[1].led = led_create(ahci_ch_led, &ch->leds[1], buf);
- snprintf(buf, sizeof(buf), "%s.fault",
- device_get_nameunit(dev));
- ch->leds[2].led = led_create(ahci_ch_led, &ch->leds[2], buf);
- }
return (0);
err3:
@@ -1168,12 +757,7 @@
ahci_ch_detach(device_t dev)
{
struct ahci_channel *ch = device_get_softc(dev);
- int i;
- for (i = 0; i < AHCI_NUM_LEDS; i++) {
- if (ch->leds[i].led)
- led_destroy(ch->leds[i].led);
- }
mtx_lock(&ch->mtx);
xpt_async(AC_LOST_DEVICE, ch->path, NULL);
/* Forget about reset. */
@@ -1221,8 +805,8 @@
(AHCI_P_CMD_ACTIVE | AHCI_P_CMD_POD | AHCI_P_CMD_SUD |
((ch->pm_level == 2 || ch->pm_level == 3) ? AHCI_P_CMD_ALPE : 0) |
((ch->pm_level > 2) ? AHCI_P_CMD_ASP : 0 )));
- ahci_start_fr(dev);
- ahci_start(dev, 1);
+ ahci_start_fr(ch);
+ ahci_start(ch, 1);
return (0);
}
@@ -1234,8 +818,8 @@
/* Disable port interrupts. */
ATA_OUTL(ch->r_mem, AHCI_P_IE, 0);
/* Reset command register. */
- ahci_stop(dev);
- ahci_stop_fr(dev);
+ ahci_stop(ch);
+ ahci_stop_fr(ch);
ATA_OUTL(ch->r_mem, AHCI_P_CMD, 0);
/* Allow everything, including partial and slumber modes. */
ATA_OUTL(ch->r_mem, AHCI_P_SCTL, 0);
@@ -1274,7 +858,7 @@
mtx_lock(&ch->mtx);
ahci_ch_init(dev);
- ahci_reset(dev);
+ ahci_reset(ch);
xpt_release_simq(ch->sim, TRUE);
mtx_unlock(&ch->mtx);
return (0);
@@ -1296,47 +880,6 @@
};
DRIVER_MODULE(ahcich, ahci, ahcich_driver, ahcich_devclass, NULL, NULL);
-static void
-ahci_ch_setleds(device_t dev)
-{
- struct ahci_channel *ch;
- struct ahci_controller *ctlr;
- size_t buf;
- int i, timeout;
- int16_t val;
-
- ctlr = device_get_softc(device_get_parent(dev));
- ch = device_get_softc(dev);
-
- val = 0;
- for (i = 0; i < AHCI_NUM_LEDS; i++)
- val |= ch->leds[i].state << (i * 3);
-
- buf = (ctlr->emloc & 0xffff0000) >> 14;
- mtx_lock(&ctlr->em_mtx);
- timeout = 1000;
- while (ATA_INL(ctlr->r_mem, AHCI_EM_CTL) & (AHCI_EM_TM | AHCI_EM_RST) &&
- --timeout > 0)
- DELAY(1000);
- if (timeout == 0)
- device_printf(dev, "EM timeout\n");
- ATA_OUTL(ctlr->r_mem, buf, (1 << 8) | (0 << 16) | (0 << 24));
- ATA_OUTL(ctlr->r_mem, buf + 4, ch->unit | (val << 16));
- ATA_OUTL(ctlr->r_mem, AHCI_EM_CTL, AHCI_EM_TM);
- mtx_unlock(&ctlr->em_mtx);
-}
-
-static void
-ahci_ch_led(void *priv, int onoff)
-{
- struct ahci_led *led;
-
- led = (struct ahci_led *)priv;
-
- led->state = onoff;
- ahci_ch_setleds(led->dev);
-}
-
struct ahci_dc_cb_args {
bus_addr_t maddr;
int error;
@@ -1355,7 +898,7 @@
NULL, NULL, AHCI_WORK_SIZE, 1, AHCI_WORK_SIZE,
0, NULL, NULL, &ch->dma.work_tag))
goto error;
- if (bus_dmamem_alloc(ch->dma.work_tag, (void **)&ch->dma.work,
+ if (bus_dmamem_alloc(ch->dma.work_tag, (void **)&ch->dma.work,
BUS_DMA_ZERO, &ch->dma.work_map))
goto error;
if (bus_dmamap_load(ch->dma.work_tag, ch->dma.work_map, ch->dma.work,
@@ -1421,7 +964,6 @@
bus_dmamap_unload(ch->dma.rfis_tag, ch->dma.rfis_map);
bus_dmamem_free(ch->dma.rfis_tag, ch->dma.rfis, ch->dma.rfis_map);
ch->dma.rfis_bus = 0;
- ch->dma.rfis_map = NULL;
ch->dma.rfis = NULL;
}
if (ch->dma.work_bus) {
@@ -1428,7 +970,6 @@
bus_dmamap_unload(ch->dma.work_tag, ch->dma.work_map);
bus_dmamem_free(ch->dma.work_tag, ch->dma.work, ch->dma.work_map);
ch->dma.work_bus = 0;
- ch->dma.work_map = NULL;
ch->dma.work = NULL;
}
if (ch->dma.work_tag) {
@@ -1448,7 +989,7 @@
for (i = 0; i < ch->numslots; i++) {
struct ahci_slot *slot = &ch->slot[i];
- slot->dev = dev;
+ slot->ch = ch;
slot->slot = i;
slot->state = AHCI_SLOT_EMPTY;
slot->ccb = NULL;
@@ -1478,9 +1019,8 @@
}
static int
-ahci_phy_check_events(device_t dev, u_int32_t serr)
+ahci_phy_check_events(struct ahci_channel *ch, u_int32_t serr)
{
- struct ahci_channel *ch = device_get_softc(dev);
if (((ch->pm_level == 0) && (serr & ATA_SE_PHY_CHANGED)) ||
((ch->pm_level != 0 || ch->listening) && (serr & ATA_SE_EXCHANGED))) {
@@ -1489,11 +1029,11 @@
if (bootverbose) {
if ((status & ATA_SS_DET_MASK) != ATA_SS_DET_NO_DEVICE)
- device_printf(dev, "CONNECT requested\n");
+ device_printf(ch->dev, "CONNECT requested\n");
else
- device_printf(dev, "DISCONNECT requested\n");
+ device_printf(ch->dev, "DISCONNECT requested\n");
}
- ahci_reset(dev);
+ ahci_reset(ch);
if ((ccb = xpt_alloc_ccb_nowait()) == NULL)
return (0);
if (xpt_create_path(&ccb->ccb_h.path, NULL,
@@ -1509,11 +1049,11 @@
}
static void
-ahci_cpd_check_events(device_t dev)
+ahci_cpd_check_events(struct ahci_channel *ch)
{
- struct ahci_channel *ch = device_get_softc(dev);
u_int32_t status;
union ccb *ccb;
+ device_t dev;
if (ch->pm_level == 0)
return;
@@ -1523,12 +1063,13 @@
return;
if (bootverbose) {
+ dev = ch->dev;
if (status & AHCI_P_CMD_CPS) {
device_printf(dev, "COLD CONNECT requested\n");
} else
device_printf(dev, "COLD DISCONNECT requested\n");
}
- ahci_reset(dev);
+ ahci_reset(ch);
if ((ccb = xpt_alloc_ccb_nowait()) == NULL)
return;
if (xpt_create_path(&ccb->ccb_h.path, NULL, cam_sim_path(ch->sim),
@@ -1540,9 +1081,8 @@
}
static void
-ahci_notify_events(device_t dev, u_int32_t status)
+ahci_notify_events(struct ahci_channel *ch, u_int32_t status)
{
- struct ahci_channel *ch = device_get_softc(dev);
struct cam_path *dpath;
int i;
@@ -1549,7 +1089,7 @@
if (ch->caps & AHCI_CAP_SSNTF)
ATA_OUTL(ch->r_mem, AHCI_P_SNTF, status);
if (bootverbose)
- device_printf(dev, "SNTF 0x%04x\n", status);
+ device_printf(ch->dev, "SNTF 0x%04x\n", status);
for (i = 0; i < 16; i++) {
if ((status & (1 << i)) == 0)
continue;
@@ -1562,23 +1102,64 @@
}
static void
-ahci_ch_intr_locked(void *data)
+ahci_done(struct ahci_channel *ch, union ccb *ccb)
{
- device_t dev = (device_t)data;
- struct ahci_channel *ch = device_get_softc(dev);
+ mtx_assert(&ch->mtx, MA_OWNED);
+ if ((ccb->ccb_h.func_code & XPT_FC_QUEUED) == 0 ||
+ ch->batch == 0) {
+ xpt_done(ccb);
+ return;
+ }
+
+ STAILQ_INSERT_TAIL(&ch->doneq, &ccb->ccb_h, sim_links.stqe);
+}
+
+static void
+ahci_ch_intr(void *arg)
+{
+ struct ahci_channel *ch = (struct ahci_channel *)arg;
+ uint32_t istatus;
+
+ /* Read interrupt statuses. */
+ istatus = ATA_INL(ch->r_mem, AHCI_P_IS);
+
mtx_lock(&ch->mtx);
- xpt_batch_start(ch->sim);
- ahci_ch_intr(data);
- xpt_batch_done(ch->sim);
+ ahci_ch_intr_main(ch, istatus);
mtx_unlock(&ch->mtx);
}
static void
+ahci_ch_intr_direct(void *arg)
+{
+ struct ahci_channel *ch = (struct ahci_channel *)arg;
+ struct ccb_hdr *ccb_h;
+ uint32_t istatus;
+ STAILQ_HEAD(, ccb_hdr) tmp_doneq = STAILQ_HEAD_INITIALIZER(tmp_doneq);
+
+ /* Read interrupt statuses. */
+ istatus = ATA_INL(ch->r_mem, AHCI_P_IS);
+
+ mtx_lock(&ch->mtx);
+ ch->batch = 1;
+ ahci_ch_intr_main(ch, istatus);
+ ch->batch = 0;
+ /*
+ * Prevent the possibility of issues caused by processing the queue
+ * while unlocked below by moving the contents to a local queue.
+ */
+ STAILQ_CONCAT(&tmp_doneq, &ch->doneq);
+ mtx_unlock(&ch->mtx);
+ while ((ccb_h = STAILQ_FIRST(&tmp_doneq)) != NULL) {
+ STAILQ_REMOVE_HEAD(&tmp_doneq, sim_links.stqe);
+ xpt_done_direct((union ccb *)ccb_h);
+ }
+}
+
+static void
ahci_ch_pm(void *arg)
{
- device_t dev = (device_t)arg;
- struct ahci_channel *ch = device_get_softc(dev);
+ struct ahci_channel *ch = (struct ahci_channel *)arg;
uint32_t work;
if (ch->numrslots != 0)
@@ -1592,18 +1173,13 @@
}
static void
-ahci_ch_intr(void *data)
+ahci_ch_intr_main(struct ahci_channel *ch, uint32_t istatus)
{
- device_t dev = (device_t)data;
- struct ahci_channel *ch = device_get_softc(dev);
- uint32_t istatus, cstatus, serr = 0, sntf = 0, ok, err;
+ uint32_t cstatus, serr = 0, sntf = 0, ok, err;
enum ahci_err_type et;
int i, ccs, port, reset = 0;
- /* Read and clear interrupt statuses. */
- istatus = ATA_INL(ch->r_mem, AHCI_P_IS);
- if (istatus == 0)
- return;
+ /* Clear interrupt statuses. */
ATA_OUTL(ch->r_mem, AHCI_P_IS, istatus);
/* Read command statuses. */
if (ch->numtslots != 0)
@@ -1640,17 +1216,28 @@
serr = ATA_INL(ch->r_mem, AHCI_P_SERR);
if (serr) {
ATA_OUTL(ch->r_mem, AHCI_P_SERR, serr);
- reset = ahci_phy_check_events(dev, serr);
+ reset = ahci_phy_check_events(ch, serr);
}
}
/* Process cold presence detection events */
if ((istatus & AHCI_P_IX_CPD) && !reset)
- ahci_cpd_check_events(dev);
+ ahci_cpd_check_events(ch);
/* Process command errors */
if (istatus & (AHCI_P_IX_OF | AHCI_P_IX_IF |
AHCI_P_IX_HBD | AHCI_P_IX_HBF | AHCI_P_IX_TFE)) {
- ccs = (ATA_INL(ch->r_mem, AHCI_P_CMD) & AHCI_P_CMD_CCS_MASK)
- >> AHCI_P_CMD_CCS_SHIFT;
+ if (ch->quirks & AHCI_Q_NOCCS) {
+ /*
+ * ASMedia chips sometimes report failed commands as
+ * completed. Count all running commands as failed.
+ */
+ cstatus |= ch->rslots;
+
+ /* They also report wrong CCS, so try to guess one. */
+ ccs = powerof2(cstatus) ? ffs(cstatus) - 1 : -1;
+ } else {
+ ccs = (ATA_INL(ch->r_mem, AHCI_P_CMD) &
+ AHCI_P_CMD_CCS_MASK) >> AHCI_P_CMD_CCS_SHIFT;
+ }
//device_printf(dev, "%s ERROR is %08x cs %08x ss %08x rs %08x tfd %02x serr %08x fbs %08x ccs %d\n",
// __func__, istatus, cstatus, sstatus, ch->rslots, ATA_INL(ch->r_mem, AHCI_P_TFD),
// serr, ATA_INL(ch->r_mem, AHCI_P_FBS), ccs);
@@ -1695,7 +1282,7 @@
xpt_freeze_devq(fccb->ccb_h.path, 1);
fccb->ccb_h.status |= CAM_DEV_QFRZN;
}
- xpt_done(fccb);
+ ahci_done(ch, fccb);
}
for (i = 0; i < ch->numslots; i++) {
/* XXX: reqests in loading state. */
@@ -1740,14 +1327,13 @@
}
/* Process NOTIFY events */
if (sntf)
- ahci_notify_events(dev, sntf);
+ ahci_notify_events(ch, sntf);
}
/* Must be called with channel locked. */
static int
-ahci_check_collision(device_t dev, union ccb *ccb)
+ahci_check_collision(struct ahci_channel *ch, union ccb *ccb)
{
- struct ahci_channel *ch = device_get_softc(dev);
int t = ccb->ccb_h.target_id;
if ((ccb->ccb_h.func_code == XPT_ATA_IO) &&
@@ -1796,9 +1382,8 @@
/* Must be called with channel locked. */
static void
-ahci_begin_transaction(device_t dev, union ccb *ccb)
+ahci_begin_transaction(struct ahci_channel *ch, union ccb *ccb)
{
- struct ahci_channel *ch = device_get_softc(dev);
struct ahci_slot *slot;
int tag, tags;
@@ -1807,14 +1392,14 @@
if ((ccb->ccb_h.func_code == XPT_ATA_IO) &&
(ccb->ataio.cmd.flags & CAM_ATAIO_FPDMA))
tags = ch->curr[ccb->ccb_h.target_id].tags;
- tag = ch->lastslot;
- while (1) {
- if (tag >= tags)
- tag = 0;
- if (ch->slot[tag].state == AHCI_SLOT_EMPTY)
- break;
- tag++;
- };
+ if (ch->lastslot + 1 < tags)
+ tag = ffs(~(ch->oslots >> (ch->lastslot + 1)));
+ else
+ tag = 0;
+ if (tag == 0 || tag + ch->lastslot >= tags)
+ tag = ffs(~ch->oslots) - 1;
+ else
+ tag += ch->lastslot;
ch->lastslot = tag;
/* Occupy chosen slot. */
slot = &ch->slot[tag];
@@ -1823,7 +1408,7 @@
if (ch->numrslots == 0 && ch->pm_level > 3)
callout_stop(&ch->pm_timer);
/* Update channel stats. */
- ch->oslots |= (1 << slot->slot);
+ ch->oslots |= (1 << tag);
ch->numrslots++;
ch->numrslotspd[ccb->ccb_h.target_id]++;
if ((ccb->ccb_h.func_code == XPT_ATA_IO) &&
@@ -1834,25 +1419,15 @@
}
if ((ccb->ccb_h.func_code == XPT_ATA_IO) &&
(ccb->ataio.cmd.flags & (CAM_ATAIO_CONTROL | CAM_ATAIO_NEEDRESULT)))
- ch->aslots |= (1 << slot->slot);
- slot->dma.nsegs = 0;
- /* If request moves data, setup and load SG list */
+ ch->aslots |= (1 << tag);
if ((ccb->ccb_h.flags & CAM_DIR_MASK) != CAM_DIR_NONE) {
- void *buf;
- bus_size_t size;
-
slot->state = AHCI_SLOT_LOADING;
- if (ccb->ccb_h.func_code == XPT_ATA_IO) {
- buf = ccb->ataio.data_ptr;
- size = ccb->ataio.dxfer_len;
- } else {
- buf = ccb->csio.data_ptr;
- size = ccb->csio.dxfer_len;
- }
- bus_dmamap_load(ch->dma.data_tag, slot->dma.data_map,
- buf, size, ahci_dmasetprd, slot, 0);
- } else
+ bus_dmamap_load_ccb(ch->dma.data_tag, slot->dma.data_map, ccb,
+ ahci_dmasetprd, slot, 0);
+ } else {
+ slot->dma.nsegs = 0;
ahci_execute_transaction(slot);
+ }
}
/* Locked by busdma engine. */
@@ -1860,13 +1435,13 @@
ahci_dmasetprd(void *arg, bus_dma_segment_t *segs, int nsegs, int error)
{
struct ahci_slot *slot = arg;
- struct ahci_channel *ch = device_get_softc(slot->dev);
+ struct ahci_channel *ch = slot->ch;
struct ahci_cmd_tab *ctp;
struct ahci_dma_prd *prd;
int i;
if (error) {
- device_printf(slot->dev, "DMA load error\n");
+ device_printf(ch->dev, "DMA load error\n");
ahci_end_transaction(slot, AHCI_ERR_INVALID);
return;
}
@@ -1891,8 +1466,7 @@
static void
ahci_execute_transaction(struct ahci_slot *slot)
{
- device_t dev = slot->dev;
- struct ahci_channel *ch = device_get_softc(dev);
+ struct ahci_channel *ch = slot->ch;
struct ahci_cmd_tab *ctp;
struct ahci_cmd_list *clp;
union ccb *ccb = slot->ccb;
@@ -1905,7 +1479,7 @@
ctp = (struct ahci_cmd_tab *)
(ch->dma.work + AHCI_CT_OFFSET + (AHCI_CT_SIZE * slot->slot));
/* Setup the FIS for this request */
- if (!(fis_size = ahci_setup_fis(dev, ctp, ccb, slot->slot))) {
+ if (!(fis_size = ahci_setup_fis(ch, ctp, ccb, slot->slot))) {
device_printf(ch->dev, "Setting up SATA FIS failed\n");
ahci_end_transaction(slot, AHCI_ERR_INVALID);
return;
@@ -1926,9 +1500,9 @@
if (ccb->ataio.cmd.control & ATA_A_RESET) {
softreset = 1;
/* Kick controller into sane state */
- ahci_stop(dev);
- ahci_clo(dev);
- ahci_start(dev, 0);
+ ahci_stop(ch);
+ ahci_clo(ch);
+ ahci_start(ch, 0);
clp->cmd_flags |= AHCI_CMD_RESET | AHCI_CMD_CLR_BUSY;
} else {
softreset = 2;
@@ -1981,7 +1555,7 @@
}
/* Workaround for ATI SB600/SB700 chipsets. */
if (ccb->ccb_h.target_id == 15 &&
- pci_get_vendor(device_get_parent(dev)) == 0x1002 &&
+ (ch->quirks & AHCI_Q_ATI_PMP_BUG) &&
(ATA_INL(ch->r_mem, AHCI_P_IS) & AHCI_P_IX_IPM)) {
et = AHCI_ERR_TIMEOUT;
break;
@@ -1996,6 +1570,7 @@
* this wait.
*/
if ((ch->quirks & AHCI_Q_NOBSYRES) == 0 &&
+ (ch->quirks & AHCI_Q_ATI_PMP_BUG) == 0 &&
softreset == 2 && et == AHCI_ERR_NONE) {
while ((val = fis[2]) & ATA_S_BUSY) {
DELAY(10);
@@ -2005,9 +1580,9 @@
}
if (timeout && (count >= timeout)) {
- device_printf(dev, "Poll timeout on slot %d port %d\n",
+ device_printf(ch->dev, "Poll timeout on slot %d port %d\n",
slot->slot, port);
- device_printf(dev, "is %08x cs %08x ss %08x "
+ device_printf(ch->dev, "is %08x cs %08x ss %08x "
"rs %08x tfd %02x serr %08x cmd %08x\n",
ATA_INL(ch->r_mem, AHCI_P_IS),
ATA_INL(ch->r_mem, AHCI_P_CI),
@@ -2025,16 +1600,15 @@
return;
}
/* Start command execution timeout */
- callout_reset(&slot->timeout, (int)ccb->ccb_h.timeout * hz / 2000,
- (timeout_t*)ahci_timeout, slot);
+ callout_reset_sbt(&slot->timeout, SBT_1MS * ccb->ccb_h.timeout / 2,
+ 0, (timeout_t*)ahci_timeout, slot, 0);
return;
}
/* Must be called with channel locked. */
static void
-ahci_process_timeout(device_t dev)
+ahci_process_timeout(struct ahci_channel *ch)
{
- struct ahci_channel *ch = device_get_softc(dev);
int i;
mtx_assert(&ch->mtx, MA_OWNED);
@@ -2049,9 +1623,8 @@
/* Must be called with channel locked. */
static void
-ahci_rearm_timeout(device_t dev)
+ahci_rearm_timeout(struct ahci_channel *ch)
{
- struct ahci_channel *ch = device_get_softc(dev);
int i;
mtx_assert(&ch->mtx, MA_OWNED);
@@ -2063,9 +1636,9 @@
continue;
if ((ch->toslots & (1 << i)) == 0)
continue;
- callout_reset(&slot->timeout,
- (int)slot->ccb->ccb_h.timeout * hz / 2000,
- (timeout_t*)ahci_timeout, slot);
+ callout_reset_sbt(&slot->timeout,
+ SBT_1MS * slot->ccb->ccb_h.timeout / 2, 0,
+ (timeout_t*)ahci_timeout, slot, 0);
}
}
@@ -2073,8 +1646,8 @@
static void
ahci_timeout(struct ahci_slot *slot)
{
- device_t dev = slot->dev;
- struct ahci_channel *ch = device_get_softc(dev);
+ struct ahci_channel *ch = slot->ch;
+ device_t dev = ch->dev;
uint32_t sstatus;
int ccs;
int i;
@@ -2097,9 +1670,9 @@
slot->state = AHCI_SLOT_EXECUTING;
}
- callout_reset(&slot->timeout,
- (int)slot->ccb->ccb_h.timeout * hz / 2000,
- (timeout_t*)ahci_timeout, slot);
+ callout_reset_sbt(&slot->timeout,
+ SBT_1MS * slot->ccb->ccb_h.timeout / 2, 0,
+ (timeout_t*)ahci_timeout, slot, 0);
return;
}
@@ -2121,7 +1694,7 @@
xpt_freeze_devq(fccb->ccb_h.path, 1);
fccb->ccb_h.status |= CAM_DEV_QFRZN;
}
- xpt_done(fccb);
+ ahci_done(ch, fccb);
}
if (!ch->fbs_enabled && !ch->wrongccs) {
/* Without FBS we know real timeout source. */
@@ -2141,7 +1714,7 @@
xpt_freeze_simq(ch->sim, 1);
ch->toslots |= (1 << slot->slot);
if ((ch->rslots & ~ch->toslots) == 0)
- ahci_process_timeout(dev);
+ ahci_process_timeout(ch);
else
device_printf(dev, " ... waiting for slots %08x\n",
ch->rslots & ~ch->toslots);
@@ -2152,8 +1725,7 @@
static void
ahci_end_transaction(struct ahci_slot *slot, enum ahci_err_type et)
{
- device_t dev = slot->dev;
- struct ahci_channel *ch = device_get_softc(dev);
+ struct ahci_channel *ch = slot->ch;
union ccb *ccb = slot->ccb;
struct ahci_cmd_list *clp;
int lastto;
@@ -2311,15 +1883,15 @@
(ccb->ataio.cmd.control & ATA_A_RESET) &&
et == AHCI_ERR_NONE) {
ccb->ataio.cmd.control &= ~ATA_A_RESET;
- ahci_begin_transaction(dev, ccb);
+ ahci_begin_transaction(ch, ccb);
return;
}
/* If it was our READ LOG command - process it. */
if (ccb->ccb_h.recovery_type == RECOVERY_READ_LOG) {
- ahci_process_read_log(dev, ccb);
+ ahci_process_read_log(ch, ccb);
/* If it was our REQUEST SENSE command - process it. */
} else if (ccb->ccb_h.recovery_type == RECOVERY_REQUEST_SENSE) {
- ahci_process_request_sense(dev, ccb);
+ ahci_process_request_sense(ch, ccb);
/* If it was NCQ or ATAPI command error, put result on hold. */
} else if (et == AHCI_ERR_NCQ ||
((ccb->ccb_h.status & CAM_STATUS_MASK) == CAM_SCSI_STATUS_ERROR &&
@@ -2327,32 +1899,32 @@
ch->hold[slot->slot] = ccb;
ch->numhslots++;
} else
- xpt_done(ccb);
+ ahci_done(ch, ccb);
/* If we have no other active commands, ... */
if (ch->rslots == 0) {
/* if there was fatal error - reset port. */
if (ch->toslots != 0 || ch->fatalerr) {
- ahci_reset(dev);
+ ahci_reset(ch);
} else {
/* if we have slots in error, we can reinit port. */
if (ch->eslots != 0) {
- ahci_stop(dev);
- ahci_clo(dev);
- ahci_start(dev, 1);
+ ahci_stop(ch);
+ ahci_clo(ch);
+ ahci_start(ch, 1);
}
/* if there commands on hold, we can do READ LOG. */
if (!ch->recoverycmd && ch->numhslots)
- ahci_issue_recovery(dev);
+ ahci_issue_recovery(ch);
}
/* If all the rest of commands are in timeout - give them chance. */
} else if ((ch->rslots & ~ch->toslots) == 0 &&
et != AHCI_ERR_TIMEOUT)
- ahci_rearm_timeout(dev);
+ ahci_rearm_timeout(ch);
/* Unfreeze frozen command. */
- if (ch->frozen && !ahci_check_collision(dev, ch->frozen)) {
+ if (ch->frozen && !ahci_check_collision(ch, ch->frozen)) {
union ccb *fccb = ch->frozen;
ch->frozen = NULL;
- ahci_begin_transaction(dev, fccb);
+ ahci_begin_transaction(ch, fccb);
xpt_release_simq(ch->sim, TRUE);
}
/* Start PM timer. */
@@ -2364,9 +1936,8 @@
}
static void
-ahci_issue_recovery(device_t dev)
+ahci_issue_recovery(struct ahci_channel *ch)
{
- struct ahci_channel *ch = device_get_softc(dev);
union ccb *ccb;
struct ccb_ataio *ataio;
struct ccb_scsiio *csio;
@@ -2379,7 +1950,7 @@
}
ccb = xpt_alloc_ccb_nowait();
if (ccb == NULL) {
- device_printf(dev, "Unable to allocate recovery command\n");
+ device_printf(ch->dev, "Unable to allocate recovery command\n");
completeall:
/* We can't do anything -- complete held commands. */
for (i = 0; i < ch->numslots; i++) {
@@ -2387,11 +1958,11 @@
continue;
ch->hold[i]->ccb_h.status &= ~CAM_STATUS_MASK;
ch->hold[i]->ccb_h.status |= CAM_RESRC_UNAVAIL;
- xpt_done(ch->hold[i]);
+ ahci_done(ch, ch->hold[i]);
ch->hold[i] = NULL;
ch->numhslots--;
}
- ahci_reset(dev);
+ ahci_reset(ch);
return;
}
ccb->ccb_h = ch->hold[i]->ccb_h; /* Reuse old header. */
@@ -2405,7 +1976,7 @@
ataio->data_ptr = malloc(512, M_AHCI, M_NOWAIT);
if (ataio->data_ptr == NULL) {
xpt_free_ccb(ccb);
- device_printf(dev,
+ device_printf(ch->dev,
"Unable to allocate memory for READ LOG command\n");
goto completeall;
}
@@ -2437,13 +2008,12 @@
/* Freeze SIM while doing recovery. */
ch->recoverycmd = 1;
xpt_freeze_simq(ch->sim, 1);
- ahci_begin_transaction(dev, ccb);
+ ahci_begin_transaction(ch, ccb);
}
static void
-ahci_process_read_log(device_t dev, union ccb *ccb)
+ahci_process_read_log(struct ahci_channel *ch, union ccb *ccb)
{
- struct ahci_channel *ch = device_get_softc(dev);
uint8_t *data;
struct ata_res *res;
int i;
@@ -2475,15 +2045,15 @@
ch->hold[i]->ccb_h.status &= ~CAM_STATUS_MASK;
ch->hold[i]->ccb_h.status |= CAM_REQUEUE_REQ;
}
- xpt_done(ch->hold[i]);
+ ahci_done(ch, ch->hold[i]);
ch->hold[i] = NULL;
ch->numhslots--;
}
} else {
if ((ccb->ccb_h.status & CAM_STATUS_MASK) != CAM_REQ_CMP)
- device_printf(dev, "Error while READ LOG EXT\n");
+ device_printf(ch->dev, "Error while READ LOG EXT\n");
else if ((data[0] & 0x80) == 0) {
- device_printf(dev, "Non-queued command error in READ LOG EXT\n");
+ device_printf(ch->dev, "Non-queued command error in READ LOG EXT\n");
}
for (i = 0; i < ch->numslots; i++) {
if (!ch->hold[i])
@@ -2490,7 +2060,7 @@
continue;
if (ch->hold[i]->ccb_h.func_code != XPT_ATA_IO)
continue;
- xpt_done(ch->hold[i]);
+ ahci_done(ch, ch->hold[i]);
ch->hold[i] = NULL;
ch->numhslots--;
}
@@ -2501,9 +2071,8 @@
}
static void
-ahci_process_request_sense(device_t dev, union ccb *ccb)
+ahci_process_request_sense(struct ahci_channel *ch, union ccb *ccb)
{
- struct ahci_channel *ch = device_get_softc(dev);
int i;
ch->recoverycmd = 0;
@@ -2515,7 +2084,7 @@
ch->hold[i]->ccb_h.status &= ~CAM_STATUS_MASK;
ch->hold[i]->ccb_h.status |= CAM_AUTOSENSE_FAIL;
}
- xpt_done(ch->hold[i]);
+ ahci_done(ch, ch->hold[i]);
ch->hold[i] = NULL;
ch->numhslots--;
xpt_free_ccb(ccb);
@@ -2523,9 +2092,8 @@
}
static void
-ahci_start(device_t dev, int fbs)
+ahci_start(struct ahci_channel *ch, int fbs)
{
- struct ahci_channel *ch = device_get_softc(dev);
u_int32_t cmd;
/* Clear SATA error register */
@@ -2546,9 +2114,8 @@
}
static void
-ahci_stop(device_t dev)
+ahci_stop(struct ahci_channel *ch)
{
- struct ahci_channel *ch = device_get_softc(dev);
u_int32_t cmd;
int timeout;
@@ -2560,7 +2127,7 @@
do {
DELAY(10);
if (timeout++ > 50000) {
- device_printf(dev, "stopping AHCI engine failed\n");
+ device_printf(ch->dev, "stopping AHCI engine failed\n");
break;
}
} while (ATA_INL(ch->r_mem, AHCI_P_CMD) & AHCI_P_CMD_CR);
@@ -2568,9 +2135,8 @@
}
static void
-ahci_clo(device_t dev)
+ahci_clo(struct ahci_channel *ch)
{
- struct ahci_channel *ch = device_get_softc(dev);
u_int32_t cmd;
int timeout;
@@ -2583,7 +2149,7 @@
do {
DELAY(10);
if (timeout++ > 50000) {
- device_printf(dev, "executing CLO failed\n");
+ device_printf(ch->dev, "executing CLO failed\n");
break;
}
} while (ATA_INL(ch->r_mem, AHCI_P_CMD) & AHCI_P_CMD_CLO);
@@ -2591,9 +2157,8 @@
}
static void
-ahci_stop_fr(device_t dev)
+ahci_stop_fr(struct ahci_channel *ch)
{
- struct ahci_channel *ch = device_get_softc(dev);
u_int32_t cmd;
int timeout;
@@ -2605,7 +2170,7 @@
do {
DELAY(10);
if (timeout++ > 50000) {
- device_printf(dev, "stopping AHCI FR engine failed\n");
+ device_printf(ch->dev, "stopping AHCI FR engine failed\n");
break;
}
} while (ATA_INL(ch->r_mem, AHCI_P_CMD) & AHCI_P_CMD_FR);
@@ -2612,9 +2177,8 @@
}
static void
-ahci_start_fr(device_t dev)
+ahci_start_fr(struct ahci_channel *ch)
{
- struct ahci_channel *ch = device_get_softc(dev);
u_int32_t cmd;
/* Start FIS reception on this channel */
@@ -2623,9 +2187,8 @@
}
static int
-ahci_wait_ready(device_t dev, int t, int t0)
+ahci_wait_ready(struct ahci_channel *ch, int t, int t0)
{
- struct ahci_channel *ch = device_get_softc(dev);
int timeout = 0;
uint32_t val;
@@ -2633,7 +2196,7 @@
(ATA_S_BUSY | ATA_S_DRQ)) {
if (timeout > t) {
if (t != 0) {
- device_printf(dev,
+ device_printf(ch->dev,
"AHCI reset: device not ready after %dms "
"(tfd = %08x)\n",
MAX(t, 0) + t0, val);
@@ -2644,7 +2207,7 @@
timeout++;
}
if (bootverbose)
- device_printf(dev, "AHCI reset: device ready after %dms\n",
+ device_printf(ch->dev, "AHCI reset: device ready after %dms\n",
timeout + t0);
return (0);
}
@@ -2652,22 +2215,21 @@
static void
ahci_reset_to(void *arg)
{
- device_t dev = arg;
- struct ahci_channel *ch = device_get_softc(dev);
+ struct ahci_channel *ch = arg;
if (ch->resetting == 0)
return;
ch->resetting--;
- if (ahci_wait_ready(dev, ch->resetting == 0 ? -1 : 0,
+ if (ahci_wait_ready(ch, ch->resetting == 0 ? -1 : 0,
(310 - ch->resetting) * 100) == 0) {
ch->resetting = 0;
- ahci_start(dev, 1);
+ ahci_start(ch, 1);
xpt_release_simq(ch->sim, TRUE);
return;
}
if (ch->resetting == 0) {
- ahci_clo(dev);
- ahci_start(dev, 1);
+ ahci_clo(ch);
+ ahci_start(ch, 1);
xpt_release_simq(ch->sim, TRUE);
return;
}
@@ -2675,15 +2237,14 @@
}
static void
-ahci_reset(device_t dev)
+ahci_reset(struct ahci_channel *ch)
{
- struct ahci_channel *ch = device_get_softc(dev);
- struct ahci_controller *ctlr = device_get_softc(device_get_parent(dev));
+ struct ahci_controller *ctlr = device_get_softc(device_get_parent(ch->dev));
int i;
xpt_freeze_simq(ch->sim, 1);
if (bootverbose)
- device_printf(dev, "AHCI reset...\n");
+ device_printf(ch->dev, "AHCI reset...\n");
/* Forget about previous reset. */
if (ch->resetting) {
ch->resetting = 0;
@@ -2699,10 +2260,10 @@
xpt_freeze_devq(fccb->ccb_h.path, 1);
fccb->ccb_h.status |= CAM_DEV_QFRZN;
}
- xpt_done(fccb);
+ ahci_done(ch, fccb);
}
/* Kill the engine and requeue all running commands. */
- ahci_stop(dev);
+ ahci_stop(ch);
for (i = 0; i < ch->numslots; i++) {
/* Do we have a running request on slot? */
if (ch->slot[i].state < AHCI_SLOT_RUNNING)
@@ -2713,7 +2274,7 @@
for (i = 0; i < ch->numslots; i++) {
if (!ch->hold[i])
continue;
- xpt_done(ch->hold[i]);
+ ahci_done(ch, ch->hold[i]);
ch->hold[i] = NULL;
ch->numhslots--;
}
@@ -2728,9 +2289,9 @@
/* Disable port interrupts */
ATA_OUTL(ch->r_mem, AHCI_P_IE, 0);
/* Reset and reconnect PHY, */
- if (!ahci_sata_phy_reset(dev)) {
+ if (!ahci_sata_phy_reset(ch)) {
if (bootverbose)
- device_printf(dev,
+ device_printf(ch->dev,
"AHCI reset: device not found\n");
ch->devices = 0;
/* Enable wanted port interrupts */
@@ -2741,11 +2302,11 @@
return;
}
if (bootverbose)
- device_printf(dev, "AHCI reset: device found\n");
+ device_printf(ch->dev, "AHCI reset: device found\n");
/* Wait for clearing busy status. */
- if (ahci_wait_ready(dev, dumping ? 31000 : 0, 0)) {
+ if (ahci_wait_ready(ch, dumping ? 31000 : 0, 0)) {
if (dumping)
- ahci_clo(dev);
+ ahci_clo(ch);
else
ch->resetting = 310;
}
@@ -2759,20 +2320,19 @@
AHCI_P_IX_DP | AHCI_P_IX_UF | (ctlr->ccc ? 0 : AHCI_P_IX_SDB) |
AHCI_P_IX_DS | AHCI_P_IX_PS | (ctlr->ccc ? 0 : AHCI_P_IX_DHR)));
if (ch->resetting)
- callout_reset(&ch->reset_timer, hz / 10, ahci_reset_to, dev);
+ callout_reset(&ch->reset_timer, hz / 10, ahci_reset_to, ch);
else {
- ahci_start(dev, 1);
+ ahci_start(ch, 1);
xpt_release_simq(ch->sim, TRUE);
}
}
static int
-ahci_setup_fis(device_t dev, struct ahci_cmd_tab *ctp, union ccb *ccb, int tag)
+ahci_setup_fis(struct ahci_channel *ch, struct ahci_cmd_tab *ctp, union ccb *ccb, int tag)
{
- struct ahci_channel *ch = device_get_softc(dev);
u_int8_t *fis = &ctp->cfis[0];
- bzero(ctp->cfis, 16);
+ bzero(fis, 20);
fis[0] = 0x27; /* host to device */
fis[1] = (ccb->ccb_h.target_id & 0x0f);
if (ccb->ccb_h.func_code == XPT_SCSI_IO) {
@@ -2861,9 +2421,8 @@
}
static int
-ahci_sata_phy_reset(device_t dev)
+ahci_sata_phy_reset(struct ahci_channel *ch)
{
- struct ahci_channel *ch = device_get_softc(dev);
int sata_rev;
uint32_t val;
@@ -2903,18 +2462,17 @@
}
static int
-ahci_check_ids(device_t dev, union ccb *ccb)
+ahci_check_ids(struct ahci_channel *ch, union ccb *ccb)
{
- struct ahci_channel *ch = device_get_softc(dev);
if (ccb->ccb_h.target_id > ((ch->caps & AHCI_CAP_SPM) ? 15 : 0)) {
ccb->ccb_h.status = CAM_TID_INVALID;
- xpt_done(ccb);
+ ahci_done(ch, ccb);
return (-1);
}
if (ccb->ccb_h.target_lun != 0) {
ccb->ccb_h.status = CAM_LUN_INVALID;
- xpt_done(ccb);
+ ahci_done(ch, ccb);
return (-1);
}
return (0);
@@ -2923,7 +2481,6 @@
static void
ahciaction(struct cam_sim *sim, union ccb *ccb)
{
- device_t dev, parent;
struct ahci_channel *ch;
CAM_DEBUG(ccb->ccb_h.path, CAM_DEBUG_TRACE, ("ahciaction func_code=%x\n",
@@ -2930,12 +2487,11 @@
ccb->ccb_h.func_code));
ch = (struct ahci_channel *)cam_sim_softc(sim);
- dev = ch->dev;
switch (ccb->ccb_h.func_code) {
/* Common cases first */
case XPT_ATA_IO: /* Execute the requested I/O operation */
case XPT_SCSI_IO:
- if (ahci_check_ids(dev, ccb))
+ if (ahci_check_ids(ch, ccb))
return;
if (ch->devices == 0 ||
(ch->pm_present == 0 &&
@@ -2945,7 +2501,7 @@
}
ccb->ccb_h.recovery_type = RECOVERY_NONE;
/* Check for command collision. */
- if (ahci_check_collision(dev, ccb)) {
+ if (ahci_check_collision(ch, ccb)) {
/* Freeze command. */
ch->frozen = ccb;
/* We have only one frozen slot, so freeze simq also. */
@@ -2952,7 +2508,7 @@
xpt_freeze_simq(ch->sim, 1);
return;
}
- ahci_begin_transaction(dev, ccb);
+ ahci_begin_transaction(ch, ccb);
return;
case XPT_EN_LUN: /* Enable LUN as a target */
case XPT_TARGET_IO: /* Execute target I/O request */
@@ -2967,7 +2523,7 @@
struct ccb_trans_settings *cts = &ccb->cts;
struct ahci_device *d;
- if (ahci_check_ids(dev, ccb))
+ if (ahci_check_ids(ch, ccb))
return;
if (cts->type == CTS_TYPE_CURRENT_SETTINGS)
d = &ch->curr[ccb->ccb_h.target_id];
@@ -2997,7 +2553,7 @@
struct ahci_device *d;
uint32_t status;
- if (ahci_check_ids(dev, ccb))
+ if (ahci_check_ids(ch, ccb))
return;
if (cts->type == CTS_TYPE_CURRENT_SETTINGS)
d = &ch->curr[ccb->ccb_h.target_id];
@@ -3054,7 +2610,7 @@
}
case XPT_RESET_BUS: /* Reset the specified SCSI bus */
case XPT_RESET_DEV: /* Bus Device Reset the specified SCSI device */
- ahci_reset(dev);
+ ahci_reset(ch);
ccb->ccb_h.status = CAM_REQ_CMP;
break;
case XPT_TERM_IO: /* Terminate the I/O process */
@@ -3065,7 +2621,6 @@
{
struct ccb_pathinq *cpi = &ccb->cpi;
- parent = device_get_parent(dev);
cpi->version_num = 1; /* XXX??? */
cpi->hba_inquiry = PI_SDTR_ABLE;
if (ch->caps & AHCI_CAP_SNCQ)
@@ -3073,7 +2628,7 @@
if (ch->caps & AHCI_CAP_SPM)
cpi->hba_inquiry |= PI_SATAPM;
cpi->target_sprt = 0;
- cpi->hba_misc = PIM_SEQSCAN;
+ cpi->hba_misc = PIM_SEQSCAN | PIM_UNMAPPED;
cpi->hba_eng_cnt = 0;
if (ch->caps & AHCI_CAP_SPM)
cpi->max_target = 15;
@@ -3083,9 +2638,9 @@
cpi->initiator_id = 0;
cpi->bus_id = cam_sim_bus(sim);
cpi->base_transfer_speed = 150000;
- strncpy(cpi->sim_vid, "FreeBSD", SIM_IDLEN);
- strncpy(cpi->hba_vid, "AHCI", HBA_IDLEN);
- strncpy(cpi->dev_name, cam_sim_name(sim), DEV_IDLEN);
+ strlcpy(cpi->sim_vid, "FreeBSD", SIM_IDLEN);
+ strlcpy(cpi->hba_vid, "AHCI", HBA_IDLEN);
+ strlcpy(cpi->dev_name, cam_sim_name(sim), DEV_IDLEN);
cpi->unit_number = cam_sim_unit(sim);
cpi->transport = XPORT_SATA;
cpi->transport_version = XPORT_VERSION_UNSPECIFIED;
@@ -3093,12 +2648,12 @@
cpi->protocol_version = PROTO_VERSION_UNSPECIFIED;
cpi->maxio = MAXPHYS;
/* ATI SB600 can't handle 256 sectors with FPDMA (NCQ). */
- if (pci_get_devid(parent) == 0x43801002)
+ if (ch->quirks & AHCI_Q_MAXIO_64K)
cpi->maxio = min(cpi->maxio, 128 * 512);
- cpi->hba_vendor = pci_get_vendor(parent);
- cpi->hba_device = pci_get_device(parent);
- cpi->hba_subvendor = pci_get_subvendor(parent);
- cpi->hba_subdevice = pci_get_subdevice(parent);
+ cpi->hba_vendor = ch->vendorid;
+ cpi->hba_device = ch->deviceid;
+ cpi->hba_subvendor = ch->subvendorid;
+ cpi->hba_subdevice = ch->subdeviceid;
cpi->ccb_h.status = CAM_REQ_CMP;
break;
}
@@ -3106,7 +2661,7 @@
ccb->ccb_h.status = CAM_REQ_INVALID;
break;
}
- xpt_done(ccb);
+ ahci_done(ch, ccb);
}
static void
@@ -3113,11 +2668,17 @@
ahcipoll(struct cam_sim *sim)
{
struct ahci_channel *ch = (struct ahci_channel *)cam_sim_softc(sim);
+ uint32_t istatus;
- ahci_ch_intr(ch->dev);
+ /* Read interrupt statuses and process if any. */
+ istatus = ATA_INL(ch->r_mem, AHCI_P_IS);
+ if (istatus != 0)
+ ahci_ch_intr_main(ch, istatus);
if (ch->resetting != 0 &&
(--ch->resetpolldiv <= 0 || !callout_pending(&ch->reset_timer))) {
ch->resetpolldiv = 1000;
- ahci_reset_to(ch->dev);
+ ahci_reset_to(ch);
}
}
+MODULE_VERSION(ahci, 1);
+MODULE_DEPEND(ahci, cam, 1, 1, 1);
Modified: trunk/sys/dev/ahci/ahci.h
===================================================================
--- trunk/sys/dev/ahci/ahci.h 2018-05-28 00:25:20 UTC (rev 10127)
+++ trunk/sys/dev/ahci/ahci.h 2018-05-28 00:27:43 UTC (rev 10128)
@@ -1,6 +1,7 @@
+/* $MidnightBSD$ */
/*-
- * Copyright (c) 1998 - 2008 S\xF8ren Schmidt <sos at FreeBSD.org>
- * Copyright (c) 2009 Alexander Motin <mav at FreeBSD.org>
+ * Copyright (c) 1998 - 2008 Søren Schmidt <sos at FreeBSD.org>
+ * Copyright (c) 2009-2012 Alexander Motin <mav at FreeBSD.org>
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
@@ -24,7 +25,7 @@
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
- * $MidnightBSD$
+ * $FreeBSD: stable/10/sys/dev/ahci/ahci.h 313446 2017-02-08 16:07:59Z mav $
*/
/* ATA register defines */
@@ -137,11 +138,13 @@
#define ATA_SC_IPM_NONE 0x00000000
#define ATA_SC_IPM_DIS_PARTIAL 0x00000100
#define ATA_SC_IPM_DIS_SLUMBER 0x00000200
+#define ATA_SC_IPM_DIS_DEVSLEEP 0x00000400
#define ATA_SACTIVE 16
#define AHCI_MAX_PORTS 32
#define AHCI_MAX_SLOTS 32
+#define AHCI_MAX_IRQS 16
/* SATA AHCI v1.0 register defines */
#define AHCI_CAP 0x00
@@ -286,6 +289,17 @@
#define AHCI_P_FBS_ADO_SHIFT 12
#define AHCI_P_FBS_DWE 0x000f0000
#define AHCI_P_FBS_DWE_SHIFT 16
+#define AHCI_P_DEVSLP 0x44
+#define AHCI_P_DEVSLP_ADSE 0x00000001
+#define AHCI_P_DEVSLP_DSP 0x00000002
+#define AHCI_P_DEVSLP_DETO 0x000003fc
+#define AHCI_P_DEVSLP_DETO_SHIFT 2
+#define AHCI_P_DEVSLP_MDAT 0x00007c00
+#define AHCI_P_DEVSLP_MDAT_SHIFT 10
+#define AHCI_P_DEVSLP_DITO 0x01ff8000
+#define AHCI_P_DEVSLP_DITO_SHIFT 15
+#define AHCI_P_DEVSLP_DM 0x0e000000
+#define AHCI_P_DEVSLP_DM_SHIFT 25
/* Just to be sure, if building as module. */
#if MAXPHYS < 512 * 1024
@@ -309,7 +323,7 @@
u_int32_t dbc; /* 0 based */
#define AHCI_PRD_MASK 0x003fffff /* max 4MB */
#define AHCI_PRD_MAX (AHCI_PRD_MASK + 1)
-#define AHCI_PRD_IPC (1 << 31)
+#define AHCI_PRD_IPC (1U << 31)
} __packed;
struct ahci_cmd_tab {
@@ -363,7 +377,7 @@
};
struct ahci_slot {
- device_t dev; /* Device handle */
+ struct ahci_channel *ch; /* Channel */
u_int8_t slot; /* Number of this slot */
enum ahci_slot_states state; /* Slot state */
union ccb *ccb; /* CCB occupying slot */
@@ -399,25 +413,30 @@
struct ata_dma dma; /* DMA data */
struct cam_sim *sim;
struct cam_path *path;
- struct ahci_led leds[3];
uint32_t caps; /* Controller capabilities */
uint32_t caps2; /* Controller capabilities */
uint32_t chcaps; /* Channel capabilities */
+ uint32_t chscaps; /* Channel sleep capabilities */
+ uint16_t vendorid; /* Vendor ID from the bus */
+ uint16_t deviceid; /* Device ID from the bus */
+ uint16_t subvendorid; /* Subvendor ID from the bus */
+ uint16_t subdeviceid; /* Subdevice ID from the bus */
int quirks;
int numslots; /* Number of present slots */
int pm_level; /* power management level */
-
- struct ahci_slot slot[AHCI_MAX_SLOTS];
- union ccb *hold[AHCI_MAX_SLOTS];
- struct mtx mtx; /* state lock */
int devices; /* What is present */
int pm_present; /* PM presence reported */
int fbs_enabled; /* FIS-based switching enabled */
+
+ union ccb *hold[AHCI_MAX_SLOTS];
+ struct ahci_slot slot[AHCI_MAX_SLOTS];
uint32_t oslots; /* Occupied slots */
uint32_t rslots; /* Running slots */
uint32_t aslots; /* Slots with atomic commands */
uint32_t eslots; /* Slots in error */
uint32_t toslots; /* Slots in timeout */
+ int lastslot; /* Last used slot */
+ int taggedtarget; /* Last tagged target */
int numrslots; /* Number of running slots */
int numrslotspd[16];/* Number of running slots per dev */
int numtslots; /* Number of tagged slots */
@@ -425,8 +444,6 @@
int numhslots; /* Number of held slots */
int recoverycmd; /* Our READ LOG active */
int fatalerr; /* Fatal error happend */
- int lastslot; /* Last used slot */
- int taggedtarget; /* Last tagged target */
int resetting; /* Hard-reset in progress. */
int resetpolldiv; /* Hard-reset poll divider. */
int listening; /* SUD bit is cleared. */
@@ -437,13 +454,37 @@
struct ahci_device user[16]; /* User-specified settings */
struct ahci_device curr[16]; /* Current settings */
+
+ struct mtx_padalign mtx; /* state lock */
+ STAILQ_HEAD(, ccb_hdr) doneq; /* queue of completed CCBs */
+ int batch; /* doneq is in use */
};
+struct ahci_enclosure {
+ device_t dev; /* Device handle */
+ struct resource *r_memc; /* Control register */
+ struct resource *r_memt; /* Transmit buffer */
+ struct resource *r_memr; /* Recieve buffer */
+ struct cam_sim *sim;
+ struct cam_path *path;
+ struct mtx mtx; /* state lock */
+ struct ahci_led leds[AHCI_MAX_PORTS * 3];
+ uint32_t capsem; /* Controller capabilities */
+ uint8_t status[AHCI_MAX_PORTS][4]; /* ArrayDev statuses */
+ int quirks;
+ int channels;
+ uint32_t ichannels;
+};
+
/* structure describing a AHCI controller */
struct ahci_controller {
device_t dev;
bus_dma_tag_t dma_tag;
int r_rid;
+ uint16_t vendorid; /* Vendor ID from the bus */
+ uint16_t deviceid; /* Device ID from the bus */
+ uint16_t subvendorid; /* Subvendor ID from the bus */
+ uint16_t subdeviceid; /* Subdevice ID from the bus */
struct resource *r_mem;
struct rman sc_iomem;
struct ahci_controller_irq {
@@ -455,7 +496,7 @@
#define AHCI_IRQ_MODE_ALL 0
#define AHCI_IRQ_MODE_AFTER 1
#define AHCI_IRQ_MODE_ONE 2
- } irqs[16];
+ } irqs[AHCI_MAX_IRQS];
uint32_t caps; /* Controller capabilities */
uint32_t caps2; /* Controller capabilities */
uint32_t capsem; /* Controller capabilities */
@@ -463,14 +504,15 @@
int quirks;
int numirqs;
int channels;
- int ichannels;
+ uint32_t ichannels;
int ccc; /* CCC timeout */
int cccv; /* CCC vector */
+ int direct; /* Direct command completion */
+ int msi; /* MSI interupts */
struct {
void (*function)(void *);
void *argument;
} interrupt[AHCI_MAX_PORTS];
- struct mtx em_mtx; /* EM access lock */
};
enum ahci_err_type {
@@ -513,3 +555,65 @@
bus_write_multi_4((res), (offset), (addr), (count))
#define ATA_OUTSL_STRM(res, offset, addr, count) \
bus_write_multi_stream_4((res), (offset), (addr), (count))
+
+
+#define AHCI_Q_NOFORCE 0x00000001
+#define AHCI_Q_NOPMP 0x00000002
+#define AHCI_Q_NONCQ 0x00000004
+#define AHCI_Q_1CH 0x00000008
+#define AHCI_Q_2CH 0x00000010
+#define AHCI_Q_4CH 0x00000020
+#define AHCI_Q_EDGEIS 0x00000040
+#define AHCI_Q_SATA2 0x00000080
+#define AHCI_Q_NOBSYRES 0x00000100
+#define AHCI_Q_NOAA 0x00000200
+#define AHCI_Q_NOCOUNT 0x00000400
+#define AHCI_Q_ALTSIG 0x00000800
+#define AHCI_Q_NOMSI 0x00001000
+#define AHCI_Q_ATI_PMP_BUG 0x00002000
+#define AHCI_Q_MAXIO_64K 0x00004000
+#define AHCI_Q_SATA1_UNIT0 0x00008000 /* need better method for this */
+#define AHCI_Q_ABAR0 0x00010000
+#define AHCI_Q_1MSI 0x00020000
+#define AHCI_Q_NOCCS 0x00400000
+
+#define AHCI_Q_BIT_STRING \
+ "\020" \
+ "\001NOFORCE" \
+ "\002NOPMP" \
+ "\003NONCQ" \
+ "\0041CH" \
+ "\0052CH" \
+ "\0064CH" \
+ "\007EDGEIS" \
+ "\010SATA2" \
+ "\011NOBSYRES" \
+ "\012NOAA" \
+ "\013NOCOUNT" \
+ "\014ALTSIG" \
+ "\015NOMSI" \
+ "\016ATI_PMP_BUG" \
+ "\017MAXIO_64K" \
+ "\020SATA1_UNIT0" \
+ "\021ABAR0" \
+ "\0221MSI" \
+ "\027NOCCS"
+
+int ahci_attach(device_t dev);
+int ahci_detach(device_t dev);
+int ahci_setup_interrupt(device_t dev);
+int ahci_print_child(device_t dev, device_t child);
+struct resource *ahci_alloc_resource(device_t dev, device_t child, int type, int *rid,
+ u_long start, u_long end, u_long count, u_int flags);
+int ahci_release_resource(device_t dev, device_t child, int type, int rid,
+ struct resource *r);
+int ahci_setup_intr(device_t dev, device_t child, struct resource *irq,
+ int flags, driver_filter_t *filter, driver_intr_t *function,
+ void *argument, void **cookiep);
+int ahci_teardown_intr(device_t dev, device_t child, struct resource *irq,
+ void *cookie);
+int ahci_child_location_str(device_t dev, device_t child, char *buf,
+ size_t buflen);
+bus_dma_tag_t ahci_get_dma_tag(device_t dev, device_t child);
+int ahci_ctlr_reset(device_t dev);
+int ahci_ctlr_setup(device_t dev);
Added: trunk/sys/dev/ahci/ahci_pci.c
===================================================================
--- trunk/sys/dev/ahci/ahci_pci.c (rev 0)
+++ trunk/sys/dev/ahci/ahci_pci.c 2018-05-28 00:27:43 UTC (rev 10128)
@@ -0,0 +1,544 @@
+/* $MidnightBSD$ */
+/*-
+ * Copyright (c) 2009-2012 Alexander Motin <mav at FreeBSD.org>
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer,
+ * without modification, immediately at the beginning of the file.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+ * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+ * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <sys/cdefs.h>
+__FBSDID("$FreeBSD: stable/10/sys/dev/ahci/ahci_pci.c 313446 2017-02-08 16:07:59Z mav $");
+
+#include <sys/param.h>
+#include <sys/module.h>
+#include <sys/systm.h>
+#include <sys/kernel.h>
+#include <sys/bus.h>
+#include <sys/conf.h>
+#include <sys/endian.h>
+#include <sys/malloc.h>
+#include <sys/lock.h>
+#include <sys/mutex.h>
+#include <machine/stdarg.h>
+#include <machine/resource.h>
+#include <machine/bus.h>
+#include <sys/rman.h>
+#include <dev/pci/pcivar.h>
+#include <dev/pci/pcireg.h>
+#include "ahci.h"
+
+static int force_ahci = 1;
+TUNABLE_INT("hw.ahci.force", &force_ahci);
+
+static const struct {
+ uint32_t id;
+ uint8_t rev;
+ const char *name;
+ int quirks;
+} ahci_ids[] = {
+ {0x43801002, 0x00, "AMD SB600",
+ AHCI_Q_NOMSI | AHCI_Q_ATI_PMP_BUG | AHCI_Q_MAXIO_64K},
+ {0x43901002, 0x00, "AMD SB7x0/SB8x0/SB9x0",
+ AHCI_Q_ATI_PMP_BUG | AHCI_Q_1MSI},
+ {0x43911002, 0x00, "AMD SB7x0/SB8x0/SB9x0",
+ AHCI_Q_ATI_PMP_BUG | AHCI_Q_1MSI},
+ {0x43921002, 0x00, "AMD SB7x0/SB8x0/SB9x0",
+ AHCI_Q_ATI_PMP_BUG | AHCI_Q_1MSI},
+ {0x43931002, 0x00, "AMD SB7x0/SB8x0/SB9x0",
+ AHCI_Q_ATI_PMP_BUG | AHCI_Q_1MSI},
+ {0x43941002, 0x00, "AMD SB7x0/SB8x0/SB9x0",
+ AHCI_Q_ATI_PMP_BUG | AHCI_Q_1MSI},
+ /* Not sure SB8x0/SB9x0 needs this quirk. Be conservative though */
+ {0x43951002, 0x00, "AMD SB8x0/SB9x0", AHCI_Q_ATI_PMP_BUG},
+ {0x78001022, 0x00, "AMD Hudson-2", 0},
+ {0x78011022, 0x00, "AMD Hudson-2", 0},
+ {0x78021022, 0x00, "AMD Hudson-2", 0},
+ {0x78031022, 0x00, "AMD Hudson-2", 0},
+ {0x78041022, 0x00, "AMD Hudson-2", 0},
+ {0x06011b21, 0x00, "ASMedia ASM1060", AHCI_Q_NOCCS},
+ {0x06021b21, 0x00, "ASMedia ASM1060", AHCI_Q_NOCCS},
+ {0x06111b21, 0x00, "ASMedia ASM1061", AHCI_Q_NOCCS},
+ {0x06121b21, 0x00, "ASMedia ASM1062", AHCI_Q_NOCCS},
+ {0x06201b21, 0x00, "ASMedia ASM106x", AHCI_Q_NOCCS},
+ {0x06211b21, 0x00, "ASMedia ASM106x", AHCI_Q_NOCCS},
+ {0x06221b21, 0x00, "ASMedia ASM106x", AHCI_Q_NOCCS},
+ {0x06241b21, 0x00, "ASMedia ASM106x", AHCI_Q_NOCCS},
+ {0x06251b21, 0x00, "ASMedia ASM106x", AHCI_Q_NOCCS},
+ {0x26528086, 0x00, "Intel ICH6", AHCI_Q_NOFORCE},
+ {0x26538086, 0x00, "Intel ICH6M", AHCI_Q_NOFORCE},
+ {0x26818086, 0x00, "Intel ESB2", 0},
+ {0x26828086, 0x00, "Intel ESB2", 0},
+ {0x26838086, 0x00, "Intel ESB2", 0},
+ {0x27c18086, 0x00, "Intel ICH7", 0},
+ {0x27c38086, 0x00, "Intel ICH7", 0},
+ {0x27c58086, 0x00, "Intel ICH7M", 0},
+ {0x27c68086, 0x00, "Intel ICH7M", 0},
+ {0x28218086, 0x00, "Intel ICH8", 0},
+ {0x28228086, 0x00, "Intel ICH8", 0},
+ {0x28248086, 0x00, "Intel ICH8", 0},
+ {0x28298086, 0x00, "Intel ICH8M", 0},
+ {0x282a8086, 0x00, "Intel ICH8M", 0},
+ {0x29228086, 0x00, "Intel ICH9", 0},
+ {0x29238086, 0x00, "Intel ICH9", 0},
+ {0x29248086, 0x00, "Intel ICH9", 0},
+ {0x29258086, 0x00, "Intel ICH9", 0},
+ {0x29278086, 0x00, "Intel ICH9", 0},
+ {0x29298086, 0x00, "Intel ICH9M", 0},
+ {0x292a8086, 0x00, "Intel ICH9M", 0},
+ {0x292b8086, 0x00, "Intel ICH9M", 0},
+ {0x292c8086, 0x00, "Intel ICH9M", 0},
+ {0x292f8086, 0x00, "Intel ICH9M", 0},
+ {0x294d8086, 0x00, "Intel ICH9", 0},
+ {0x294e8086, 0x00, "Intel ICH9M", 0},
+ {0x3a058086, 0x00, "Intel ICH10", 0},
+ {0x3a228086, 0x00, "Intel ICH10", 0},
+ {0x3a258086, 0x00, "Intel ICH10", 0},
+ {0x3b228086, 0x00, "Intel 5 Series/3400 Series", 0},
+ {0x3b238086, 0x00, "Intel 5 Series/3400 Series", 0},
+ {0x3b258086, 0x00, "Intel 5 Series/3400 Series", 0},
+ {0x3b298086, 0x00, "Intel 5 Series/3400 Series", 0},
+ {0x3b2c8086, 0x00, "Intel 5 Series/3400 Series", 0},
+ {0x3b2f8086, 0x00, "Intel 5 Series/3400 Series", 0},
+ {0x1c028086, 0x00, "Intel Cougar Point", 0},
+ {0x1c038086, 0x00, "Intel Cougar Point", 0},
+ {0x1c048086, 0x00, "Intel Cougar Point", 0},
+ {0x1c058086, 0x00, "Intel Cougar Point", 0},
+ {0x1d028086, 0x00, "Intel Patsburg", 0},
+ {0x1d048086, 0x00, "Intel Patsburg", 0},
+ {0x1d068086, 0x00, "Intel Patsburg", 0},
+ {0x28268086, 0x00, "Intel Patsburg (RAID)", 0},
+ {0x1e028086, 0x00, "Intel Panther Point", 0},
+ {0x1e038086, 0x00, "Intel Panther Point", 0},
+ {0x1e048086, 0x00, "Intel Panther Point (RAID)", 0},
+ {0x1e058086, 0x00, "Intel Panther Point (RAID)", 0},
+ {0x1e068086, 0x00, "Intel Panther Point (RAID)", 0},
+ {0x1e078086, 0x00, "Intel Panther Point (RAID)", 0},
+ {0x1e0e8086, 0x00, "Intel Panther Point (RAID)", 0},
+ {0x1e0f8086, 0x00, "Intel Panther Point (RAID)", 0},
+ {0x1f228086, 0x00, "Intel Avoton", 0},
+ {0x1f238086, 0x00, "Intel Avoton", 0},
+ {0x1f248086, 0x00, "Intel Avoton (RAID)", 0},
+ {0x1f258086, 0x00, "Intel Avoton (RAID)", 0},
+ {0x1f268086, 0x00, "Intel Avoton (RAID)", 0},
+ {0x1f278086, 0x00, "Intel Avoton (RAID)", 0},
+ {0x1f2e8086, 0x00, "Intel Avoton (RAID)", 0},
+ {0x1f2f8086, 0x00, "Intel Avoton (RAID)", 0},
+ {0x1f328086, 0x00, "Intel Avoton", 0},
+ {0x1f338086, 0x00, "Intel Avoton", 0},
+ {0x1f348086, 0x00, "Intel Avoton (RAID)", 0},
+ {0x1f358086, 0x00, "Intel Avoton (RAID)", 0},
+ {0x1f368086, 0x00, "Intel Avoton (RAID)", 0},
+ {0x1f378086, 0x00, "Intel Avoton (RAID)", 0},
+ {0x1f3e8086, 0x00, "Intel Avoton (RAID)", 0},
+ {0x1f3f8086, 0x00, "Intel Avoton (RAID)", 0},
+ {0x23a38086, 0x00, "Intel Coleto Creek", 0},
+ {0x28238086, 0x00, "Intel Wellsburg (RAID)", 0},
+ {0x28278086, 0x00, "Intel Wellsburg (RAID)", 0},
+ {0x8c028086, 0x00, "Intel Lynx Point", 0},
+ {0x8c038086, 0x00, "Intel Lynx Point", 0},
+ {0x8c048086, 0x00, "Intel Lynx Point (RAID)", 0},
+ {0x8c058086, 0x00, "Intel Lynx Point (RAID)", 0},
+ {0x8c068086, 0x00, "Intel Lynx Point (RAID)", 0},
+ {0x8c078086, 0x00, "Intel Lynx Point (RAID)", 0},
+ {0x8c0e8086, 0x00, "Intel Lynx Point (RAID)", 0},
+ {0x8c0f8086, 0x00, "Intel Lynx Point (RAID)", 0},
+ {0x8c828086, 0x00, "Intel Wildcat Point", 0},
+ {0x8c838086, 0x00, "Intel Wildcat Point", 0},
+ {0x8c848086, 0x00, "Intel Wildcat Point (RAID)", 0},
+ {0x8c858086, 0x00, "Intel Wildcat Point (RAID)", 0},
+ {0x8c868086, 0x00, "Intel Wildcat Point (RAID)", 0},
+ {0x8c878086, 0x00, "Intel Wildcat Point (RAID)", 0},
+ {0x8c8e8086, 0x00, "Intel Wildcat Point (RAID)", 0},
+ {0x8c8f8086, 0x00, "Intel Wildcat Point (RAID)", 0},
+ {0x8d028086, 0x00, "Intel Wellsburg", 0},
+ {0x8d048086, 0x00, "Intel Wellsburg (RAID)", 0},
+ {0x8d068086, 0x00, "Intel Wellsburg (RAID)", 0},
+ {0x8d628086, 0x00, "Intel Wellsburg", 0},
+ {0x8d648086, 0x00, "Intel Wellsburg (RAID)", 0},
+ {0x8d668086, 0x00, "Intel Wellsburg (RAID)", 0},
+ {0x8d6e8086, 0x00, "Intel Wellsburg (RAID)", 0},
+ {0x9c028086, 0x00, "Intel Lynx Point-LP", 0},
+ {0x9c038086, 0x00, "Intel Lynx Point-LP", 0},
+ {0x9c048086, 0x00, "Intel Lynx Point-LP (RAID)", 0},
+ {0x9c058086, 0x00, "Intel Lynx Point-LP (RAID)", 0},
+ {0x9c068086, 0x00, "Intel Lynx Point-LP (RAID)", 0},
+ {0x9c078086, 0x00, "Intel Lynx Point-LP (RAID)", 0},
+ {0x9c0e8086, 0x00, "Intel Lynx Point-LP (RAID)", 0},
+ {0x9c0f8086, 0x00, "Intel Lynx Point-LP (RAID)", 0},
+ {0x9d038086, 0x00, "Intel Sunrise Point-LP", 0},
+ {0x9d058086, 0x00, "Intel Sunrise Point-LP (RAID)", 0},
+ {0x9d078086, 0x00, "Intel Sunrise Point-LP (RAID)", 0},
+ {0xa1028086, 0x00, "Intel Sunrise Point", 0},
+ {0xa1038086, 0x00, "Intel Sunrise Point", 0},
+ {0xa1058086, 0x00, "Intel Sunrise Point (RAID)", 0},
+ {0xa1068086, 0x00, "Intel Sunrise Point (RAID)", 0},
+ {0xa1078086, 0x00, "Intel Sunrise Point (RAID)", 0},
+ {0xa10f8086, 0x00, "Intel Sunrise Point (RAID)", 0},
+ {0x23238086, 0x00, "Intel DH89xxCC", 0},
+ {0x2360197b, 0x00, "JMicron JMB360", 0},
+ {0x2361197b, 0x00, "JMicron JMB361", AHCI_Q_NOFORCE | AHCI_Q_1CH},
+ {0x2362197b, 0x00, "JMicron JMB362", 0},
+ {0x2363197b, 0x00, "JMicron JMB363", AHCI_Q_NOFORCE},
+ {0x2365197b, 0x00, "JMicron JMB365", AHCI_Q_NOFORCE},
+ {0x2366197b, 0x00, "JMicron JMB366", AHCI_Q_NOFORCE},
+ {0x2368197b, 0x00, "JMicron JMB368", AHCI_Q_NOFORCE},
+ {0x611111ab, 0x00, "Marvell 88SE6111", AHCI_Q_NOFORCE | AHCI_Q_NOPMP |
+ AHCI_Q_1CH | AHCI_Q_EDGEIS},
+ {0x612111ab, 0x00, "Marvell 88SE6121", AHCI_Q_NOFORCE | AHCI_Q_NOPMP |
+ AHCI_Q_2CH | AHCI_Q_EDGEIS | AHCI_Q_NONCQ | AHCI_Q_NOCOUNT},
+ {0x614111ab, 0x00, "Marvell 88SE6141", AHCI_Q_NOFORCE | AHCI_Q_NOPMP |
+ AHCI_Q_4CH | AHCI_Q_EDGEIS | AHCI_Q_NONCQ | AHCI_Q_NOCOUNT},
+ {0x614511ab, 0x00, "Marvell 88SE6145", AHCI_Q_NOFORCE | AHCI_Q_NOPMP |
+ AHCI_Q_4CH | AHCI_Q_EDGEIS | AHCI_Q_NONCQ | AHCI_Q_NOCOUNT},
+ {0x91201b4b, 0x00, "Marvell 88SE912x", AHCI_Q_EDGEIS},
+ {0x91231b4b, 0x11, "Marvell 88SE912x", AHCI_Q_ALTSIG},
+ {0x91231b4b, 0x00, "Marvell 88SE912x", AHCI_Q_EDGEIS|AHCI_Q_SATA2},
+ {0x91251b4b, 0x00, "Marvell 88SE9125", 0},
+ {0x91281b4b, 0x00, "Marvell 88SE9128", AHCI_Q_ALTSIG},
+ {0x91301b4b, 0x00, "Marvell 88SE9130", AHCI_Q_ALTSIG},
+ {0x91721b4b, 0x00, "Marvell 88SE9172", 0},
+ {0x91821b4b, 0x00, "Marvell 88SE9182", 0},
+ {0x91831b4b, 0x00, "Marvell 88SS9183", 0},
+ {0x91a01b4b, 0x00, "Marvell 88SE91Ax", 0},
+ {0x92151b4b, 0x00, "Marvell 88SE9215", 0},
+ {0x92201b4b, 0x00, "Marvell 88SE9220", AHCI_Q_ALTSIG},
+ {0x92301b4b, 0x00, "Marvell 88SE9230", AHCI_Q_ALTSIG},
+ {0x92351b4b, 0x00, "Marvell 88SE9235", 0},
+ {0x06201103, 0x00, "HighPoint RocketRAID 620", 0},
+ {0x06201b4b, 0x00, "HighPoint RocketRAID 620", 0},
+ {0x06221103, 0x00, "HighPoint RocketRAID 622", 0},
+ {0x06221b4b, 0x00, "HighPoint RocketRAID 622", 0},
+ {0x06401103, 0x00, "HighPoint RocketRAID 640", 0},
+ {0x06401b4b, 0x00, "HighPoint RocketRAID 640", 0},
+ {0x06441103, 0x00, "HighPoint RocketRAID 644", 0},
+ {0x06441b4b, 0x00, "HighPoint RocketRAID 644", 0},
+ {0x06411103, 0x00, "HighPoint RocketRAID 640L", 0},
+ {0x06421103, 0x00, "HighPoint RocketRAID 642L", 0},
+ {0x06451103, 0x00, "HighPoint RocketRAID 644L", 0},
+ {0x044c10de, 0x00, "NVIDIA MCP65", AHCI_Q_NOAA},
+ {0x044d10de, 0x00, "NVIDIA MCP65", AHCI_Q_NOAA},
+ {0x044e10de, 0x00, "NVIDIA MCP65", AHCI_Q_NOAA},
+ {0x044f10de, 0x00, "NVIDIA MCP65", AHCI_Q_NOAA},
+ {0x045c10de, 0x00, "NVIDIA MCP65", AHCI_Q_NOAA},
+ {0x045d10de, 0x00, "NVIDIA MCP65", AHCI_Q_NOAA},
+ {0x045e10de, 0x00, "NVIDIA MCP65", AHCI_Q_NOAA},
+ {0x045f10de, 0x00, "NVIDIA MCP65", AHCI_Q_NOAA},
+ {0x055010de, 0x00, "NVIDIA MCP67", AHCI_Q_NOAA},
+ {0x055110de, 0x00, "NVIDIA MCP67", AHCI_Q_NOAA},
+ {0x055210de, 0x00, "NVIDIA MCP67", AHCI_Q_NOAA},
+ {0x055310de, 0x00, "NVIDIA MCP67", AHCI_Q_NOAA},
+ {0x055410de, 0x00, "NVIDIA MCP67", AHCI_Q_NOAA},
+ {0x055510de, 0x00, "NVIDIA MCP67", AHCI_Q_NOAA},
+ {0x055610de, 0x00, "NVIDIA MCP67", AHCI_Q_NOAA},
+ {0x055710de, 0x00, "NVIDIA MCP67", AHCI_Q_NOAA},
+ {0x055810de, 0x00, "NVIDIA MCP67", AHCI_Q_NOAA},
+ {0x055910de, 0x00, "NVIDIA MCP67", AHCI_Q_NOAA},
+ {0x055A10de, 0x00, "NVIDIA MCP67", AHCI_Q_NOAA},
+ {0x055B10de, 0x00, "NVIDIA MCP67", AHCI_Q_NOAA},
+ {0x058410de, 0x00, "NVIDIA MCP67", AHCI_Q_NOAA},
+ {0x07f010de, 0x00, "NVIDIA MCP73", AHCI_Q_NOAA},
+ {0x07f110de, 0x00, "NVIDIA MCP73", AHCI_Q_NOAA},
+ {0x07f210de, 0x00, "NVIDIA MCP73", AHCI_Q_NOAA},
+ {0x07f310de, 0x00, "NVIDIA MCP73", AHCI_Q_NOAA},
+ {0x07f410de, 0x00, "NVIDIA MCP73", AHCI_Q_NOAA},
+ {0x07f510de, 0x00, "NVIDIA MCP73", AHCI_Q_NOAA},
+ {0x07f610de, 0x00, "NVIDIA MCP73", AHCI_Q_NOAA},
+ {0x07f710de, 0x00, "NVIDIA MCP73", AHCI_Q_NOAA},
+ {0x07f810de, 0x00, "NVIDIA MCP73", AHCI_Q_NOAA},
+ {0x07f910de, 0x00, "NVIDIA MCP73", AHCI_Q_NOAA},
+ {0x07fa10de, 0x00, "NVIDIA MCP73", AHCI_Q_NOAA},
+ {0x07fb10de, 0x00, "NVIDIA MCP73", AHCI_Q_NOAA},
+ {0x0ad010de, 0x00, "NVIDIA MCP77", AHCI_Q_NOAA},
+ {0x0ad110de, 0x00, "NVIDIA MCP77", AHCI_Q_NOAA},
+ {0x0ad210de, 0x00, "NVIDIA MCP77", AHCI_Q_NOAA},
+ {0x0ad310de, 0x00, "NVIDIA MCP77", AHCI_Q_NOAA},
+ {0x0ad410de, 0x00, "NVIDIA MCP77", AHCI_Q_NOAA},
+ {0x0ad510de, 0x00, "NVIDIA MCP77", AHCI_Q_NOAA},
+ {0x0ad610de, 0x00, "NVIDIA MCP77", AHCI_Q_NOAA},
+ {0x0ad710de, 0x00, "NVIDIA MCP77", AHCI_Q_NOAA},
+ {0x0ad810de, 0x00, "NVIDIA MCP77", AHCI_Q_NOAA},
+ {0x0ad910de, 0x00, "NVIDIA MCP77", AHCI_Q_NOAA},
+ {0x0ada10de, 0x00, "NVIDIA MCP77", AHCI_Q_NOAA},
+ {0x0adb10de, 0x00, "NVIDIA MCP77", AHCI_Q_NOAA},
+ {0x0ab410de, 0x00, "NVIDIA MCP79", AHCI_Q_NOAA},
+ {0x0ab510de, 0x00, "NVIDIA MCP79", AHCI_Q_NOAA},
+ {0x0ab610de, 0x00, "NVIDIA MCP79", AHCI_Q_NOAA},
+ {0x0ab710de, 0x00, "NVIDIA MCP79", AHCI_Q_NOAA},
+ {0x0ab810de, 0x00, "NVIDIA MCP79", AHCI_Q_NOAA},
+ {0x0ab910de, 0x00, "NVIDIA MCP79", AHCI_Q_NOAA},
+ {0x0aba10de, 0x00, "NVIDIA MCP79", AHCI_Q_NOAA},
+ {0x0abb10de, 0x00, "NVIDIA MCP79", AHCI_Q_NOAA},
+ {0x0abc10de, 0x00, "NVIDIA MCP79", AHCI_Q_NOAA},
+ {0x0abd10de, 0x00, "NVIDIA MCP79", AHCI_Q_NOAA},
+ {0x0abe10de, 0x00, "NVIDIA MCP79", AHCI_Q_NOAA},
+ {0x0abf10de, 0x00, "NVIDIA MCP79", AHCI_Q_NOAA},
+ {0x0d8410de, 0x00, "NVIDIA MCP89", AHCI_Q_NOAA},
+ {0x0d8510de, 0x00, "NVIDIA MCP89", AHCI_Q_NOFORCE|AHCI_Q_NOAA},
+ {0x0d8610de, 0x00, "NVIDIA MCP89", AHCI_Q_NOAA},
+ {0x0d8710de, 0x00, "NVIDIA MCP89", AHCI_Q_NOAA},
+ {0x0d8810de, 0x00, "NVIDIA MCP89", AHCI_Q_NOAA},
+ {0x0d8910de, 0x00, "NVIDIA MCP89", AHCI_Q_NOAA},
+ {0x0d8a10de, 0x00, "NVIDIA MCP89", AHCI_Q_NOAA},
+ {0x0d8b10de, 0x00, "NVIDIA MCP89", AHCI_Q_NOAA},
+ {0x0d8c10de, 0x00, "NVIDIA MCP89", AHCI_Q_NOAA},
+ {0x0d8d10de, 0x00, "NVIDIA MCP89", AHCI_Q_NOAA},
+ {0x0d8e10de, 0x00, "NVIDIA MCP89", AHCI_Q_NOAA},
+ {0x0d8f10de, 0x00, "NVIDIA MCP89", AHCI_Q_NOAA},
+ {0x3781105a, 0x00, "Promise TX8660", 0},
+ {0x33491106, 0x00, "VIA VT8251", AHCI_Q_NOPMP|AHCI_Q_NONCQ},
+ {0x62871106, 0x00, "VIA VT8251", AHCI_Q_NOPMP|AHCI_Q_NONCQ},
+ {0x11841039, 0x00, "SiS 966", 0},
+ {0x11851039, 0x00, "SiS 968", 0},
+ {0x01861039, 0x00, "SiS 968", 0},
+ {0xa01c177d, 0x00, "ThunderX", AHCI_Q_ABAR0|AHCI_Q_1MSI},
+ {0x00000000, 0x00, NULL, 0}
+};
+
+static int
+ahci_pci_ctlr_reset(device_t dev)
+{
+
+ if (pci_read_config(dev, PCIR_DEVVENDOR, 4) == 0x28298086 &&
+ (pci_read_config(dev, 0x92, 1) & 0xfe) == 0x04)
+ pci_write_config(dev, 0x92, 0x01, 1);
+ return ahci_ctlr_reset(dev);
+}
+
+static int
+ahci_probe(device_t dev)
+{
+ char buf[64];
+ int i, valid = 0;
+ uint32_t devid = pci_get_devid(dev);
+ uint8_t revid = pci_get_revid(dev);
+
+ /*
+ * Ensure it is not a PCI bridge (some vendors use
+ * the same PID and VID in PCI bridge and AHCI cards).
+ */
+ if (pci_get_class(dev) == PCIC_BRIDGE)
+ return (ENXIO);
+
+ /* Is this a possible AHCI candidate? */
+ if (pci_get_class(dev) == PCIC_STORAGE &&
+ pci_get_subclass(dev) == PCIS_STORAGE_SATA &&
+ pci_get_progif(dev) == PCIP_STORAGE_SATA_AHCI_1_0)
+ valid = 1;
+ else if (pci_get_class(dev) == PCIC_STORAGE &&
+ pci_get_subclass(dev) == PCIS_STORAGE_RAID)
+ valid = 2;
+ /* Is this a known AHCI chip? */
+ for (i = 0; ahci_ids[i].id != 0; i++) {
+ if (ahci_ids[i].id == devid &&
+ ahci_ids[i].rev <= revid &&
+ (valid || (force_ahci == 1 &&
+ !(ahci_ids[i].quirks & AHCI_Q_NOFORCE)))) {
+ /* Do not attach JMicrons with single PCI function. */
+ if (pci_get_vendor(dev) == 0x197b &&
+ (pci_read_config(dev, 0xdf, 1) & 0x40) == 0)
+ return (ENXIO);
+ snprintf(buf, sizeof(buf), "%s AHCI SATA controller",
+ ahci_ids[i].name);
+ device_set_desc_copy(dev, buf);
+ return (BUS_PROBE_DEFAULT);
+ }
+ }
+ if (valid != 1)
+ return (ENXIO);
+ device_set_desc_copy(dev, "AHCI SATA controller");
+ return (BUS_PROBE_DEFAULT);
+}
+
+static int
+ahci_ata_probe(device_t dev)
+{
+ char buf[64];
+ int i;
+ uint32_t devid = pci_get_devid(dev);
+ uint8_t revid = pci_get_revid(dev);
+
+ if ((intptr_t)device_get_ivars(dev) >= 0)
+ return (ENXIO);
+ /* Is this a known AHCI chip? */
+ for (i = 0; ahci_ids[i].id != 0; i++) {
+ if (ahci_ids[i].id == devid &&
+ ahci_ids[i].rev <= revid) {
+ snprintf(buf, sizeof(buf), "%s AHCI SATA controller",
+ ahci_ids[i].name);
+ device_set_desc_copy(dev, buf);
+ return (BUS_PROBE_DEFAULT);
+ }
+ }
+ device_set_desc_copy(dev, "AHCI SATA controller");
+ return (BUS_PROBE_DEFAULT);
+}
+
+static int
+ahci_pci_attach(device_t dev)
+{
+ struct ahci_controller *ctlr = device_get_softc(dev);
+ int error, i;
+ uint32_t devid = pci_get_devid(dev);
+ uint8_t revid = pci_get_revid(dev);
+
+ i = 0;
+ while (ahci_ids[i].id != 0 &&
+ (ahci_ids[i].id != devid ||
+ ahci_ids[i].rev > revid))
+ i++;
+ ctlr->quirks = ahci_ids[i].quirks;
+ /* Limit speed for my onboard JMicron external port.
+ * It is not eSATA really, limit to SATA 1 */
+ if (pci_get_devid(dev) == 0x2363197b &&
+ pci_get_subvendor(dev) == 0x1043 &&
+ pci_get_subdevice(dev) == 0x81e4)
+ ctlr->quirks |= AHCI_Q_SATA1_UNIT0;
+ resource_int_value(device_get_name(dev), device_get_unit(dev),
+ "quirks", &ctlr->quirks);
+ ctlr->vendorid = pci_get_vendor(dev);
+ ctlr->deviceid = pci_get_device(dev);
+ ctlr->subvendorid = pci_get_subvendor(dev);
+ ctlr->subdeviceid = pci_get_subdevice(dev);
+
+ /* Default AHCI Base Address is BAR(5), Cavium uses BAR(0) */
+ if (ctlr->quirks & AHCI_Q_ABAR0)
+ ctlr->r_rid = PCIR_BAR(0);
+ else
+ ctlr->r_rid = PCIR_BAR(5);
+ if (!(ctlr->r_mem = bus_alloc_resource_any(dev, SYS_RES_MEMORY,
+ &ctlr->r_rid, RF_ACTIVE)))
+ return ENXIO;
+ pci_enable_busmaster(dev);
+ /* Reset controller */
+ if ((error = ahci_pci_ctlr_reset(dev)) != 0) {
+ bus_release_resource(dev, SYS_RES_MEMORY, ctlr->r_rid, ctlr->r_mem);
+ return (error);
+ };
+
+ /* Setup interrupts. */
+
+ /* Setup MSI register parameters */
+ /* Process hints. */
+ if (ctlr->quirks & AHCI_Q_NOMSI)
+ ctlr->msi = 0;
+ else if (ctlr->quirks & AHCI_Q_1MSI)
+ ctlr->msi = 1;
+ else
+ ctlr->msi = 2;
+ resource_int_value(device_get_name(dev),
+ device_get_unit(dev), "msi", &ctlr->msi);
+ ctlr->numirqs = 1;
+ if (ctlr->msi < 0)
+ ctlr->msi = 0;
+ else if (ctlr->msi == 1)
+ ctlr->msi = min(1, pci_msi_count(dev));
+ else if (ctlr->msi > 1) {
+ ctlr->msi = 2;
+ ctlr->numirqs = pci_msi_count(dev);
+ }
+ /* Allocate MSI if needed/present. */
+ if (ctlr->msi && pci_alloc_msi(dev, &ctlr->numirqs) != 0) {
+ ctlr->msi = 0;
+ ctlr->numirqs = 1;
+ }
+
+ error = ahci_attach(dev);
+ if (error != 0)
+ if (ctlr->msi)
+ pci_release_msi(dev);
+ return error;
+}
+
+static int
+ahci_pci_detach(device_t dev)
+{
+
+ ahci_detach(dev);
+ pci_release_msi(dev);
+ return (0);
+}
+
+static int
+ahci_pci_suspend(device_t dev)
+{
+ struct ahci_controller *ctlr = device_get_softc(dev);
+
+ bus_generic_suspend(dev);
+ /* Disable interupts, so the state change(s) doesn't trigger */
+ ATA_OUTL(ctlr->r_mem, AHCI_GHC,
+ ATA_INL(ctlr->r_mem, AHCI_GHC) & (~AHCI_GHC_IE));
+ return 0;
+}
+
+static int
+ahci_pci_resume(device_t dev)
+{
+ int res;
+
+ if ((res = ahci_pci_ctlr_reset(dev)) != 0)
+ return (res);
+ ahci_ctlr_setup(dev);
+ return (bus_generic_resume(dev));
+}
+
+devclass_t ahci_devclass;
+static device_method_t ahci_methods[] = {
+ DEVMETHOD(device_probe, ahci_probe),
+ DEVMETHOD(device_attach, ahci_pci_attach),
+ DEVMETHOD(device_detach, ahci_pci_detach),
+ DEVMETHOD(device_suspend, ahci_pci_suspend),
+ DEVMETHOD(device_resume, ahci_pci_resume),
+ DEVMETHOD(bus_print_child, ahci_print_child),
+ DEVMETHOD(bus_alloc_resource, ahci_alloc_resource),
+ DEVMETHOD(bus_release_resource, ahci_release_resource),
+ DEVMETHOD(bus_setup_intr, ahci_setup_intr),
+ DEVMETHOD(bus_teardown_intr,ahci_teardown_intr),
+ DEVMETHOD(bus_child_location_str, ahci_child_location_str),
+ DEVMETHOD(bus_get_dma_tag, ahci_get_dma_tag),
+ DEVMETHOD_END
+};
+static driver_t ahci_driver = {
+ "ahci",
+ ahci_methods,
+ sizeof(struct ahci_controller)
+};
+DRIVER_MODULE(ahci, pci, ahci_driver, ahci_devclass, NULL, NULL);
+static device_method_t ahci_ata_methods[] = {
+ DEVMETHOD(device_probe, ahci_ata_probe),
+ DEVMETHOD(device_attach, ahci_pci_attach),
+ DEVMETHOD(device_detach, ahci_pci_detach),
+ DEVMETHOD(device_suspend, ahci_pci_suspend),
+ DEVMETHOD(device_resume, ahci_pci_resume),
+ DEVMETHOD(bus_print_child, ahci_print_child),
+ DEVMETHOD(bus_alloc_resource, ahci_alloc_resource),
+ DEVMETHOD(bus_release_resource, ahci_release_resource),
+ DEVMETHOD(bus_setup_intr, ahci_setup_intr),
+ DEVMETHOD(bus_teardown_intr,ahci_teardown_intr),
+ DEVMETHOD(bus_child_location_str, ahci_child_location_str),
+ DEVMETHOD_END
+};
+static driver_t ahci_ata_driver = {
+ "ahci",
+ ahci_ata_methods,
+ sizeof(struct ahci_controller)
+};
+DRIVER_MODULE(ahci, atapci, ahci_ata_driver, ahci_devclass, NULL, NULL);
Property changes on: trunk/sys/dev/ahci/ahci_pci.c
___________________________________________________________________
Added: svn:eol-style
## -0,0 +1 ##
+native
\ No newline at end of property
Added: svn:keywords
## -0,0 +1 ##
+MidnightBSD=%H
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+text/plain
\ No newline at end of property
Added: trunk/sys/dev/ahci/ahciem.c
===================================================================
--- trunk/sys/dev/ahci/ahciem.c (rev 0)
+++ trunk/sys/dev/ahci/ahciem.c 2018-05-28 00:27:43 UTC (rev 10128)
@@ -0,0 +1,609 @@
+/* $MidnightBSD$ */
+/*-
+ * Copyright (c) 2012 Alexander Motin <mav at FreeBSD.org>
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer,
+ * without modification, immediately at the beginning of the file.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+ * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+ * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <sys/cdefs.h>
+__FBSDID("$FreeBSD: stable/10/sys/dev/ahci/ahciem.c 315813 2017-03-23 06:41:13Z mav $");
+
+#include <sys/param.h>
+#include <sys/module.h>
+#include <sys/systm.h>
+#include <sys/kernel.h>
+#include <sys/bus.h>
+#include <sys/conf.h>
+#include <sys/endian.h>
+#include <sys/malloc.h>
+#include <sys/lock.h>
+#include <sys/mutex.h>
+#include <machine/stdarg.h>
+#include <machine/resource.h>
+#include <machine/bus.h>
+#include <sys/rman.h>
+#include <dev/led/led.h>
+#include <dev/pci/pcivar.h>
+#include <dev/pci/pcireg.h>
+#include "ahci.h"
+
+#include <cam/cam.h>
+#include <cam/cam_ccb.h>
+#include <cam/cam_sim.h>
+#include <cam/cam_xpt_sim.h>
+#include <cam/cam_debug.h>
+#include <cam/scsi/scsi_ses.h>
+
+/* local prototypes */
+static void ahciemaction(struct cam_sim *sim, union ccb *ccb);
+static void ahciempoll(struct cam_sim *sim);
+static int ahci_em_reset(device_t dev);
+static void ahci_em_led(void *priv, int onoff);
+static void ahci_em_setleds(device_t dev, int c);
+
+static int
+ahci_em_probe(device_t dev)
+{
+
+ device_set_desc_copy(dev, "AHCI enclosure management bridge");
+ return (BUS_PROBE_DEFAULT);
+}
+
+static int
+ahci_em_attach(device_t dev)
+{
+ device_t parent = device_get_parent(dev);
+ struct ahci_controller *ctlr = device_get_softc(parent);
+ struct ahci_enclosure *enc = device_get_softc(dev);
+ struct cam_devq *devq;
+ int i, c, rid, error;
+ char buf[32];
+
+ enc->dev = dev;
+ enc->quirks = ctlr->quirks;
+ enc->channels = ctlr->channels;
+ enc->ichannels = ctlr->ichannels;
+ mtx_init(&enc->mtx, "AHCI enclosure lock", NULL, MTX_DEF);
+ rid = 0;
+ if (!(enc->r_memc = bus_alloc_resource_any(dev, SYS_RES_MEMORY,
+ &rid, RF_ACTIVE))) {
+ mtx_destroy(&enc->mtx);
+ return (ENXIO);
+ }
+ enc->capsem = ATA_INL(enc->r_memc, 0);
+ rid = 1;
+ if (!(enc->r_memt = bus_alloc_resource_any(dev, SYS_RES_MEMORY,
+ &rid, RF_ACTIVE))) {
+ error = ENXIO;
+ goto err0;
+ }
+ if ((enc->capsem & (AHCI_EM_XMT | AHCI_EM_SMB)) == 0) {
+ rid = 2;
+ if (!(enc->r_memr = bus_alloc_resource_any(dev, SYS_RES_MEMORY,
+ &rid, RF_ACTIVE))) {
+ error = ENXIO;
+ goto err0;
+ }
+ } else
+ enc->r_memr = NULL;
+ mtx_lock(&enc->mtx);
+ if (ahci_em_reset(dev) != 0) {
+ error = ENXIO;
+ goto err1;
+ }
+ rid = ATA_IRQ_RID;
+ /* Create the device queue for our SIM. */
+ devq = cam_simq_alloc(1);
+ if (devq == NULL) {
+ device_printf(dev, "Unable to allocate SIM queue\n");
+ error = ENOMEM;
+ goto err1;
+ }
+ /* Construct SIM entry */
+ enc->sim = cam_sim_alloc(ahciemaction, ahciempoll, "ahciem", enc,
+ device_get_unit(dev), &enc->mtx,
+ 1, 0, devq);
+ if (enc->sim == NULL) {
+ cam_simq_free(devq);
+ device_printf(dev, "Unable to allocate SIM\n");
+ error = ENOMEM;
+ goto err1;
+ }
+ if (xpt_bus_register(enc->sim, dev, 0) != CAM_SUCCESS) {
+ device_printf(dev, "unable to register xpt bus\n");
+ error = ENXIO;
+ goto err2;
+ }
+ if (xpt_create_path(&enc->path, /*periph*/NULL, cam_sim_path(enc->sim),
+ CAM_TARGET_WILDCARD, CAM_LUN_WILDCARD) != CAM_REQ_CMP) {
+ device_printf(dev, "Unable to create path\n");
+ error = ENXIO;
+ goto err3;
+ }
+ mtx_unlock(&enc->mtx);
+ if (bootverbose) {
+ device_printf(dev, "Caps:%s%s%s%s%s%s%s%s\n",
+ (enc->capsem & AHCI_EM_PM) ? " PM":"",
+ (enc->capsem & AHCI_EM_ALHD) ? " ALHD":"",
+ (enc->capsem & AHCI_EM_XMT) ? " XMT":"",
+ (enc->capsem & AHCI_EM_SMB) ? " SMB":"",
+ (enc->capsem & AHCI_EM_SGPIO) ? " SGPIO":"",
+ (enc->capsem & AHCI_EM_SES2) ? " SES-2":"",
+ (enc->capsem & AHCI_EM_SAFTE) ? " SAF-TE":"",
+ (enc->capsem & AHCI_EM_LED) ? " LED":"");
+ }
+ if ((enc->capsem & AHCI_EM_LED)) {
+ for (c = 0; c < enc->channels; c++) {
+ if ((enc->ichannels & (1 << c)) == 0)
+ continue;
+ for (i = 0; i < AHCI_NUM_LEDS; i++) {
+ enc->leds[c * AHCI_NUM_LEDS + i].dev = dev;
+ enc->leds[c * AHCI_NUM_LEDS + i].num =
+ c * AHCI_NUM_LEDS + i;
+ }
+ if ((enc->capsem & AHCI_EM_ALHD) == 0) {
+ snprintf(buf, sizeof(buf), "%s.%d.act",
+ device_get_nameunit(parent), c);
+ enc->leds[c * AHCI_NUM_LEDS + 0].led =
+ led_create(ahci_em_led,
+ &enc->leds[c * AHCI_NUM_LEDS + 0], buf);
+ }
+ snprintf(buf, sizeof(buf), "%s.%d.locate",
+ device_get_nameunit(parent), c);
+ enc->leds[c * AHCI_NUM_LEDS + 1].led =
+ led_create(ahci_em_led,
+ &enc->leds[c * AHCI_NUM_LEDS + 1], buf);
+ snprintf(buf, sizeof(buf), "%s.%d.fault",
+ device_get_nameunit(parent), c);
+ enc->leds[c * AHCI_NUM_LEDS + 2].led =
+ led_create(ahci_em_led,
+ &enc->leds[c * AHCI_NUM_LEDS + 2], buf);
+ }
+ }
+ return (0);
+
+err3:
+ xpt_bus_deregister(cam_sim_path(enc->sim));
+err2:
+ cam_sim_free(enc->sim, /*free_devq*/TRUE);
+err1:
+ mtx_unlock(&enc->mtx);
+ if (enc->r_memr)
+ bus_release_resource(dev, SYS_RES_MEMORY, 2, enc->r_memr);
+err0:
+ if (enc->r_memt)
+ bus_release_resource(dev, SYS_RES_MEMORY, 1, enc->r_memt);
+ bus_release_resource(dev, SYS_RES_MEMORY, 0, enc->r_memc);
+ mtx_destroy(&enc->mtx);
+ return (error);
+}
+
+static int
+ahci_em_detach(device_t dev)
+{
+ struct ahci_enclosure *enc = device_get_softc(dev);
+ int i;
+
+ for (i = 0; i < enc->channels * AHCI_NUM_LEDS; i++) {
+ if (enc->leds[i].led)
+ led_destroy(enc->leds[i].led);
+ }
+ mtx_lock(&enc->mtx);
+ xpt_async(AC_LOST_DEVICE, enc->path, NULL);
+ xpt_free_path(enc->path);
+ xpt_bus_deregister(cam_sim_path(enc->sim));
+ cam_sim_free(enc->sim, /*free_devq*/TRUE);
+ mtx_unlock(&enc->mtx);
+
+ bus_release_resource(dev, SYS_RES_MEMORY, 0, enc->r_memc);
+ bus_release_resource(dev, SYS_RES_MEMORY, 1, enc->r_memt);
+ if (enc->r_memr)
+ bus_release_resource(dev, SYS_RES_MEMORY, 2, enc->r_memr);
+ mtx_destroy(&enc->mtx);
+ return (0);
+}
+
+static int
+ahci_em_reset(device_t dev)
+{
+ struct ahci_enclosure *enc;
+ int i, timeout;
+
+ enc = device_get_softc(dev);
+ ATA_OUTL(enc->r_memc, 0, AHCI_EM_RST);
+ timeout = 1000;
+ while ((ATA_INL(enc->r_memc, 0) & AHCI_EM_RST) &&
+ --timeout > 0)
+ DELAY(1000);
+ if (timeout == 0) {
+ device_printf(dev, "EM timeout\n");
+ return (1);
+ }
+ for (i = 0; i < enc->channels; i++)
+ ahci_em_setleds(dev, i);
+ return (0);
+}
+
+static int
+ahci_em_suspend(device_t dev)
+{
+ struct ahci_enclosure *enc = device_get_softc(dev);
+
+ mtx_lock(&enc->mtx);
+ xpt_freeze_simq(enc->sim, 1);
+ mtx_unlock(&enc->mtx);
+ return (0);
+}
+
+static int
+ahci_em_resume(device_t dev)
+{
+ struct ahci_enclosure *enc = device_get_softc(dev);
+
+ mtx_lock(&enc->mtx);
+ ahci_em_reset(dev);
+ xpt_release_simq(enc->sim, TRUE);
+ mtx_unlock(&enc->mtx);
+ return (0);
+}
+
+devclass_t ahciem_devclass;
+static device_method_t ahciem_methods[] = {
+ DEVMETHOD(device_probe, ahci_em_probe),
+ DEVMETHOD(device_attach, ahci_em_attach),
+ DEVMETHOD(device_detach, ahci_em_detach),
+ DEVMETHOD(device_suspend, ahci_em_suspend),
+ DEVMETHOD(device_resume, ahci_em_resume),
+ DEVMETHOD_END
+};
+static driver_t ahciem_driver = {
+ "ahciem",
+ ahciem_methods,
+ sizeof(struct ahci_enclosure)
+};
+DRIVER_MODULE(ahciem, ahci, ahciem_driver, ahciem_devclass, NULL, NULL);
+
+static void
+ahci_em_setleds(device_t dev, int c)
+{
+ struct ahci_enclosure *enc;
+ int timeout;
+ int16_t val;
+
+ enc = device_get_softc(dev);
+
+ val = 0;
+ if (enc->status[c][2] & 0x80) /* Activity */
+ val |= (1 << 0);
+ if (enc->status[c][2] & SESCTL_RQSID) /* Identification */
+ val |= (1 << 3);
+ else if (enc->status[c][3] & SESCTL_RQSFLT) /* Fault */
+ val |= (1 << 6);
+ else if (enc->status[c][1] & 0x02) /* Rebuild */
+ val |= (1 << 6) | (1 << 3);
+
+ timeout = 10000;
+ while (ATA_INL(enc->r_memc, 0) & (AHCI_EM_TM | AHCI_EM_RST) &&
+ --timeout > 0)
+ DELAY(100);
+ if (timeout == 0)
+ device_printf(dev, "Transmit timeout\n");
+ ATA_OUTL(enc->r_memt, 0, (1 << 8) | (0 << 16) | (0 << 24));
+ ATA_OUTL(enc->r_memt, 4, c | (0 << 8) | (val << 16));
+ ATA_OUTL(enc->r_memc, 0, AHCI_EM_TM);
+}
+
+static void
+ahci_em_led(void *priv, int onoff)
+{
+ struct ahci_led *led;
+ struct ahci_enclosure *enc;
+ int c, l;
+
+ led = (struct ahci_led *)priv;
+ enc = device_get_softc(led->dev);
+ c = led->num / AHCI_NUM_LEDS;
+ l = led->num % AHCI_NUM_LEDS;
+
+ if (l == 0) {
+ if (onoff)
+ enc->status[c][2] |= 0x80;
+ else
+ enc->status[c][2] &= ~0x80;
+ } else if (l == 1) {
+ if (onoff)
+ enc->status[c][2] |= SESCTL_RQSID;
+ else
+ enc->status[c][2] &= ~SESCTL_RQSID;
+ } else if (l == 2) {
+ if (onoff)
+ enc->status[c][3] |= SESCTL_RQSFLT;
+ else
+ enc->status[c][3] &= SESCTL_RQSFLT;
+ }
+ ahci_em_setleds(led->dev, c);
+}
+
+static int
+ahci_check_ids(union ccb *ccb)
+{
+
+ if (ccb->ccb_h.target_id != 0) {
+ ccb->ccb_h.status = CAM_TID_INVALID;
+ xpt_done(ccb);
+ return (-1);
+ }
+ if (ccb->ccb_h.target_lun != 0) {
+ ccb->ccb_h.status = CAM_LUN_INVALID;
+ xpt_done(ccb);
+ return (-1);
+ }
+ return (0);
+}
+
+static void
+ahci_em_emulate_ses_on_led(device_t dev, union ccb *ccb)
+{
+ struct ahci_enclosure *enc;
+ struct ses_status_page *page;
+ struct ses_status_array_dev_slot *ads, *ads0;
+ struct ses_elm_desc_hdr *elmd;
+ uint8_t *buf;
+ int i;
+
+ enc = device_get_softc(dev);
+ buf = ccb->ataio.data_ptr;
+
+ /* General request validation. */
+ if (ccb->ataio.cmd.command != ATA_SEP_ATTN ||
+ ccb->ataio.dxfer_len < ccb->ataio.cmd.sector_count * 4) {
+ ccb->ccb_h.status = CAM_REQ_INVALID;
+ goto out;
+ }
+
+ /* SEMB IDENTIFY */
+ if (ccb->ataio.cmd.features == 0xEC &&
+ ccb->ataio.cmd.sector_count >= 16) {
+ bzero(buf, ccb->ataio.dxfer_len);
+ buf[0] = 64; /* Valid bytes. */
+ buf[2] = 0x30; /* NAA Locally Assigned. */
+ strncpy(&buf[3], device_get_nameunit(dev), 7);
+ strncpy(&buf[10], "AHCI ", SID_VENDOR_SIZE);
+ strncpy(&buf[18], "SGPIO Enclosure ", SID_PRODUCT_SIZE);
+ strncpy(&buf[34], "1.00", SID_REVISION_SIZE);
+ strncpy(&buf[39], "0001", 4);
+ strncpy(&buf[43], "S-E-S ", 6);
+ strncpy(&buf[49], "2.00", 4);
+ ccb->ccb_h.status = CAM_REQ_CMP;
+ goto out;
+ }
+
+ /* SEMB RECEIVE DIAGNOSTIC RESULT (0) */
+ page = (struct ses_status_page *)buf;
+ if (ccb->ataio.cmd.lba_low == 0x02 &&
+ ccb->ataio.cmd.features == 0x00 &&
+ ccb->ataio.cmd.sector_count >= 2) {
+ bzero(buf, ccb->ataio.dxfer_len);
+ page->hdr.page_code = 0;
+ scsi_ulto2b(4, page->hdr.length);
+ buf[4] = 0;
+ buf[5] = 1;
+ buf[6] = 2;
+ buf[7] = 7;
+ ccb->ccb_h.status = CAM_REQ_CMP;
+ goto out;
+ }
+
+ /* SEMB RECEIVE DIAGNOSTIC RESULT (1) */
+ if (ccb->ataio.cmd.lba_low == 0x02 &&
+ ccb->ataio.cmd.features == 0x01 &&
+ ccb->ataio.cmd.sector_count >= 13) {
+ struct ses_enc_desc *ed;
+ struct ses_elm_type_desc *td;
+
+ bzero(buf, ccb->ataio.dxfer_len);
+ page->hdr.page_code = 0x01;
+ scsi_ulto2b(4 + 4 + 36 + 4, page->hdr.length);
+ ed = (struct ses_enc_desc *)&buf[8];
+ ed->byte0 = 0x11;
+ ed->subenc_id = 0;
+ ed->num_types = 1;
+ ed->length = 36;
+ strncpy(ed->vendor_id, "AHCI ", SID_VENDOR_SIZE);
+ strncpy(ed->product_id, "SGPIO Enclosure ", SID_PRODUCT_SIZE);
+ strncpy(ed->product_rev, " ", SID_REVISION_SIZE);
+ td = (struct ses_elm_type_desc *)ses_enc_desc_next(ed);
+ td->etype_elm_type = 0x17;
+ td->etype_maxelt = enc->channels;
+ td->etype_subenc = 0;
+ td->etype_txt_len = 0;
+ ccb->ccb_h.status = CAM_REQ_CMP;
+ goto out;
+ }
+
+ /* SEMB RECEIVE DIAGNOSTIC RESULT (2) */
+ if (ccb->ataio.cmd.lba_low == 0x02 &&
+ ccb->ataio.cmd.features == 0x02 &&
+ ccb->ataio.cmd.sector_count >= (3 + enc->channels)) {
+ bzero(buf, ccb->ataio.dxfer_len);
+ page->hdr.page_code = 0x02;
+ scsi_ulto2b(4 + 4 * (1 + enc->channels),
+ page->hdr.length);
+ for (i = 0; i < enc->channels; i++) {
+ ads = &page->elements[i + 1].array_dev_slot;
+ memcpy(ads, enc->status[i], 4);
+ ads->common.bytes[0] |=
+ (enc->ichannels & (1 << i)) ?
+ SES_OBJSTAT_UNKNOWN :
+ SES_OBJSTAT_NOTINSTALLED;
+ }
+ ccb->ccb_h.status = CAM_REQ_CMP;
+ goto out;
+ }
+
+ /* SEMB SEND DIAGNOSTIC (2) */
+ if (ccb->ataio.cmd.lba_low == 0x82 &&
+ ccb->ataio.cmd.features == 0x02 &&
+ ccb->ataio.cmd.sector_count >= (3 + enc->channels)) {
+ ads0 = &page->elements[0].array_dev_slot;
+ for (i = 0; i < enc->channels; i++) {
+ ads = &page->elements[i + 1].array_dev_slot;
+ if (ads->common.bytes[0] & SESCTL_CSEL) {
+ enc->status[i][0] = 0;
+ enc->status[i][1] =
+ ads->bytes[0] & 0x02;
+ enc->status[i][2] =
+ ads->bytes[1] & (0x80 | SESCTL_RQSID);
+ enc->status[i][3] =
+ ads->bytes[2] & SESCTL_RQSFLT;
+ ahci_em_setleds(dev, i);
+ } else if (ads0->common.bytes[0] & SESCTL_CSEL) {
+ enc->status[i][0] = 0;
+ enc->status[i][1] =
+ ads0->bytes[0] & 0x02;
+ enc->status[i][2] =
+ ads0->bytes[1] & (0x80 | SESCTL_RQSID);
+ enc->status[i][3] =
+ ads0->bytes[2] & SESCTL_RQSFLT;
+ ahci_em_setleds(dev, i);
+ }
+ }
+ ccb->ccb_h.status = CAM_REQ_CMP;
+ goto out;
+ }
+
+ /* SEMB RECEIVE DIAGNOSTIC RESULT (7) */
+ if (ccb->ataio.cmd.lba_low == 0x02 &&
+ ccb->ataio.cmd.features == 0x07 &&
+ ccb->ataio.cmd.sector_count >= (3 + 3 * enc->channels)) {
+ bzero(buf, ccb->ataio.dxfer_len);
+ page->hdr.page_code = 0x07;
+ scsi_ulto2b(4 + 4 + 12 * enc->channels,
+ page->hdr.length);
+ for (i = 0; i < enc->channels; i++) {
+ elmd = (struct ses_elm_desc_hdr *)&buf[8 + 4 + 12 * i];
+ scsi_ulto2b(8, elmd->length);
+ snprintf((char *)(elmd + 1), 9, "SLOT %03d", i);
+ }
+ ccb->ccb_h.status = CAM_REQ_CMP;
+ goto out;
+ }
+
+ ccb->ccb_h.status = CAM_REQ_INVALID;
+out:
+ xpt_done(ccb);
+}
+
+static void
+ahci_em_begin_transaction(device_t dev, union ccb *ccb)
+{
+ struct ahci_enclosure *enc;
+ struct ata_res *res;
+
+ enc = device_get_softc(dev);
+ res = &ccb->ataio.res;
+ bzero(res, sizeof(*res));
+ if ((ccb->ataio.cmd.flags & CAM_ATAIO_CONTROL) &&
+ (ccb->ataio.cmd.control & ATA_A_RESET)) {
+ res->lba_high = 0xc3;
+ res->lba_mid = 0x3c;
+ ccb->ccb_h.status = CAM_REQ_CMP;
+ xpt_done(ccb);
+ return;
+ }
+
+ if (enc->capsem & AHCI_EM_LED) {
+ ahci_em_emulate_ses_on_led(dev, ccb);
+ return;
+ } else
+ device_printf(dev, "Unsupported enclosure interface\n");
+
+ ccb->ccb_h.status = CAM_REQ_INVALID;
+ xpt_done(ccb);
+}
+
+static void
+ahciemaction(struct cam_sim *sim, union ccb *ccb)
+{
+ device_t dev, parent;
+ struct ahci_enclosure *enc;
+
+ CAM_DEBUG(ccb->ccb_h.path, CAM_DEBUG_TRACE,
+ ("ahciemaction func_code=%x\n", ccb->ccb_h.func_code));
+
+ enc = cam_sim_softc(sim);
+ dev = enc->dev;
+ switch (ccb->ccb_h.func_code) {
+ case XPT_ATA_IO: /* Execute the requested I/O operation */
+ if (ahci_check_ids(ccb))
+ return;
+ ahci_em_begin_transaction(dev, ccb);
+ return;
+ case XPT_RESET_BUS: /* Reset the specified bus */
+ case XPT_RESET_DEV: /* Bus Device Reset the specified device */
+ ahci_em_reset(dev);
+ ccb->ccb_h.status = CAM_REQ_CMP;
+ break;
+ case XPT_PATH_INQ: /* Path routing inquiry */
+ {
+ struct ccb_pathinq *cpi = &ccb->cpi;
+
+ parent = device_get_parent(dev);
+ cpi->version_num = 1; /* XXX??? */
+ cpi->hba_inquiry = PI_SDTR_ABLE;
+ cpi->target_sprt = 0;
+ cpi->hba_misc = PIM_SEQSCAN;
+ cpi->hba_eng_cnt = 0;
+ cpi->max_target = 0;
+ cpi->max_lun = 0;
+ cpi->initiator_id = 0;
+ cpi->bus_id = cam_sim_bus(sim);
+ cpi->base_transfer_speed = 150000;
+ strlcpy(cpi->sim_vid, "FreeBSD", SIM_IDLEN);
+ strlcpy(cpi->hba_vid, "AHCI", HBA_IDLEN);
+ strlcpy(cpi->dev_name, cam_sim_name(sim), DEV_IDLEN);
+ cpi->unit_number = cam_sim_unit(sim);
+ cpi->transport = XPORT_SATA;
+ cpi->transport_version = XPORT_VERSION_UNSPECIFIED;
+ cpi->protocol = PROTO_ATA;
+ cpi->protocol_version = PROTO_VERSION_UNSPECIFIED;
+ cpi->maxio = MAXPHYS;
+ cpi->hba_vendor = pci_get_vendor(parent);
+ cpi->hba_device = pci_get_device(parent);
+ cpi->hba_subvendor = pci_get_subvendor(parent);
+ cpi->hba_subdevice = pci_get_subdevice(parent);
+ cpi->ccb_h.status = CAM_REQ_CMP;
+ break;
+ }
+ default:
+ ccb->ccb_h.status = CAM_REQ_INVALID;
+ break;
+ }
+ xpt_done(ccb);
+}
+
+static void
+ahciempoll(struct cam_sim *sim)
+{
+
+}
Property changes on: trunk/sys/dev/ahci/ahciem.c
___________________________________________________________________
Added: svn:eol-style
## -0,0 +1 ##
+native
\ No newline at end of property
Added: svn:keywords
## -0,0 +1 ##
+MidnightBSD=%H
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+text/plain
\ No newline at end of property
Modified: trunk/sys/dev/aic/aic.c
===================================================================
--- trunk/sys/dev/aic/aic.c 2018-05-28 00:25:20 UTC (rev 10127)
+++ trunk/sys/dev/aic/aic.c 2018-05-28 00:27:43 UTC (rev 10128)
@@ -1,4 +1,4 @@
-/* $MidnightBSD: src/sys/dev/aic/aic.c,v 1.3 2009/01/18 19:29:04 laffer1 Exp $ */
+/* $MidnightBSD$ */
/*-
* Copyright (c) 1999 Luoqi Chen.
* All rights reserved.
@@ -26,9 +26,10 @@
*/
#include <sys/cdefs.h>
-__FBSDID("$FreeBSD$");
+__FBSDID("$FreeBSD: stable/10/sys/dev/aic/aic.c 315813 2017-03-23 06:41:13Z mav $");
#include <sys/param.h>
+#include <sys/conf.h>
#include <sys/systm.h>
#include <sys/kernel.h>
#include <sys/lock.h>
@@ -37,6 +38,7 @@
#include <sys/bus.h>
#include <machine/bus.h>
+#include <sys/rman.h>
#include <cam/cam.h>
#include <cam/cam_ccb.h>
@@ -52,6 +54,7 @@
static void aic_action(struct cam_sim *sim, union ccb *ccb);
static void aic_execute_scb(void *arg, bus_dma_segment_t *dm_segs,
int nseg, int error);
+static void aic_intr_locked(struct aic_softc *aic);
static void aic_start(struct aic_softc *aic);
static void aic_select(struct aic_softc *aic);
static void aic_selected(struct aic_softc *aic);
@@ -72,16 +75,15 @@
devclass_t aic_devclass;
-static struct aic_scb *free_scbs;
-
static struct aic_scb *
aic_get_scb(struct aic_softc *aic)
{
struct aic_scb *scb;
- int s = splcam();
- if ((scb = free_scbs) != NULL)
- free_scbs = (struct aic_scb *)free_scbs->ccb;
- splx(s);
+
+ if (!dumping)
+ mtx_assert(&aic->lock, MA_OWNED);
+ if ((scb = SLIST_FIRST(&aic->free_scbs)) != NULL)
+ SLIST_REMOVE_HEAD(&aic->free_scbs, link);
return (scb);
}
@@ -88,7 +90,9 @@
static void
aic_free_scb(struct aic_softc *aic, struct aic_scb *scb)
{
- int s = splcam();
+
+ if (!dumping)
+ mtx_assert(&aic->lock, MA_OWNED);
if ((aic->flags & AIC_RESOURCE_SHORTAGE) != 0 &&
(scb->ccb->ccb_h.status & CAM_RELEASE_SIMQ) == 0) {
scb->ccb->ccb_h.status |= CAM_RELEASE_SIMQ;
@@ -95,9 +99,7 @@
aic->flags &= ~AIC_RESOURCE_SHORTAGE;
}
scb->flags = 0;
- scb->ccb = (union ccb *)free_scbs;
- free_scbs = scb;
- splx(s);
+ SLIST_INSERT_HEAD(&aic->free_scbs, scb, link);
}
static void
@@ -104,11 +106,11 @@
aic_action(struct cam_sim *sim, union ccb *ccb)
{
struct aic_softc *aic;
- int s;
CAM_DEBUG(ccb->ccb_h.path, CAM_DEBUG_TRACE, ("aic_action\n"));
aic = (struct aic_softc *)cam_sim_softc(sim);
+ mtx_assert(&aic->lock, MA_OWNED);
switch (ccb->ccb_h.func_code) {
case XPT_SCSI_IO: /* Execute the requested I/O operation */
@@ -117,9 +119,7 @@
struct aic_scb *scb;
if ((scb = aic_get_scb(aic)) == NULL) {
- s = splcam();
aic->flags |= AIC_RESOURCE_SHORTAGE;
- splx(s);
xpt_freeze_simq(aic->sim, /*count*/1);
ccb->ccb_h.status = CAM_REQUEUE_REQ;
xpt_done(ccb);
@@ -147,8 +147,8 @@
scb->cmd_ptr = ccb->csio.cdb_io.cdb_bytes;
}
if ((ccb->ccb_h.flags & CAM_DIR_MASK) != CAM_DIR_NONE) {
- if ((ccb->ccb_h.flags & CAM_SCATTER_VALID) ||
- (ccb->ccb_h.flags & CAM_DATA_PHYS)) {
+ if ((ccb->ccb_h.flags & CAM_DATA_MASK) !=
+ CAM_DATA_VADDR) {
ccb->ccb_h.status = CAM_REQ_INVALID;
aic_free_scb(aic, scb);
xpt_done(ccb);
@@ -176,8 +176,6 @@
struct ccb_trans_settings_spi *spi =
&cts->xport_specific.spi;
- s = splcam();
-
if ((spi->valid & CTS_SPI_VALID_DISC) != 0 &&
(aic->flags & AIC_DISC_ENABLE) != 0) {
if ((spi->flags & CTS_SPI_FLAGS_DISC_ENB) != 0)
@@ -215,7 +213,6 @@
|| (ti->goal.offset != ti->current.offset))
ti->flags |= TINFO_SDTR_NEGO;
- splx(s);
ccb->ccb_h.status = CAM_REQ_CMP;
xpt_done(ccb);
break;
@@ -236,7 +233,6 @@
scsi->flags &= ~CTS_SCSI_FLAGS_TAG_ENB;
spi->flags &= ~CTS_SPI_FLAGS_DISC_ENB;
- s = splcam();
if ((ti->flags & TINFO_DISC_ENB) != 0)
spi->flags |= CTS_SPI_FLAGS_DISC_ENB;
if ((ti->flags & TINFO_TAG_ENB) != 0)
@@ -249,7 +245,6 @@
spi->sync_period = ti->user.period;
spi->sync_offset = ti->user.offset;
}
- splx(s);
spi->bus_width = MSG_EXT_WDTR_BUS_8_BIT;
spi->valid = CTS_SPI_VALID_SYNC_RATE
@@ -287,9 +282,9 @@
cpi->initiator_id = aic->initiator;
cpi->bus_id = cam_sim_bus(sim);
cpi->base_transfer_speed = 3300;
- strncpy(cpi->sim_vid, "MidnightBSD", SIM_IDLEN);
- strncpy(cpi->hba_vid, "Adaptec", HBA_IDLEN);
- strncpy(cpi->dev_name, cam_sim_name(sim), DEV_IDLEN);
+ strlcpy(cpi->sim_vid, "FreeBSD", SIM_IDLEN);
+ strlcpy(cpi->hba_vid, "Adaptec", HBA_IDLEN);
+ strlcpy(cpi->dev_name, cam_sim_name(sim), DEV_IDLEN);
cpi->unit_number = cam_sim_unit(sim);
cpi->transport = XPORT_SPI;
cpi->transport_version = 2;
@@ -312,12 +307,10 @@
struct aic_scb *scb = (struct aic_scb *)arg;
union ccb *ccb = scb->ccb;
struct aic_softc *aic = (struct aic_softc *)ccb->ccb_h.ccb_aic_ptr;
- int s;
- s = splcam();
-
+ if (!dumping)
+ mtx_assert(&aic->lock, MA_OWNED);
if (ccb->ccb_h.status != CAM_REQ_INPROG) {
- splx(s);
aic_free_scb(aic, scb);
xpt_done(ccb);
return;
@@ -327,11 +320,10 @@
ccb->ccb_h.status |= CAM_SIM_QUEUED;
TAILQ_INSERT_TAIL(&aic->pending_ccbs, &ccb->ccb_h, sim_links.tqe);
- ccb->ccb_h.timeout_ch = timeout(aic_timeout, (caddr_t)scb,
- (ccb->ccb_h.timeout * hz) / 1000);
+ callout_reset_sbt(&scb->timer, SBT_1MS * ccb->ccb_h.timeout, 0,
+ aic_timeout, scb, 0);
aic_start(aic);
- splx(s);
}
/*
@@ -1054,7 +1046,7 @@
("aic_done - ccb %p status %x resid %d\n",
ccb, ccb->ccb_h.status, ccb->csio.resid));
- untimeout(aic_timeout, (caddr_t)scb, ccb->ccb_h.timeout_ch);
+ callout_stop(&scb->timer);
if ((scb->flags & SCB_DEVICE_RESET) != 0 &&
ccb->ccb_h.func_code != XPT_RESET_DEV) {
@@ -1084,9 +1076,9 @@
&pending_scb->ccb->ccb_h, sim_links.tqe);
aic_done(aic, pending_scb);
} else {
- ccb_h->timeout_ch =
- timeout(aic_timeout, (caddr_t)pending_scb,
- (ccb_h->timeout * hz) / 1000);
+ callout_reset_sbt(&pending_scb->timer,
+ SBT_1MS * ccb_h->timeout, 0, aic_timeout,
+ pending_scb, 0);
ccb_h = TAILQ_NEXT(ccb_h, sim_links.tqe);
}
}
@@ -1103,9 +1095,9 @@
&nexus_scb->ccb->ccb_h, sim_links.tqe);
aic_done(aic, nexus_scb);
} else {
- ccb_h->timeout_ch =
- timeout(aic_timeout, (caddr_t)nexus_scb,
- (ccb_h->timeout * hz) / 1000);
+ callout_reset_sbt(&nexus_scb->timer,
+ SBT_1MS * ccb_h->timeout, 0, aic_timeout,
+ nexus_scb, 0);
ccb_h = TAILQ_NEXT(ccb_h, sim_links.tqe);
}
}
@@ -1124,7 +1116,7 @@
static void
aic_poll(struct cam_sim *sim)
{
- aic_intr(cam_sim_softc(sim));
+ aic_intr_locked(cam_sim_softc(sim));
}
static void
@@ -1133,8 +1125,8 @@
struct aic_scb *scb = (struct aic_scb *)arg;
union ccb *ccb = scb->ccb;
struct aic_softc *aic = (struct aic_softc *)ccb->ccb_h.ccb_aic_ptr;
- int s;
+ mtx_assert(&aic->lock, MA_OWNED);
xpt_print_path(ccb->ccb_h.path);
printf("ccb %p - timed out", ccb);
if (aic->nexus && aic->nexus != scb)
@@ -1141,10 +1133,7 @@
printf(", nexus %p", aic->nexus->ccb);
printf(", phase 0x%x, state %d\n", aic_inb(aic, SCSISIGI), aic->state);
- s = splcam();
-
if ((scb->flags & SCB_ACTIVE) == 0) {
- splx(s);
xpt_print_path(ccb->ccb_h.path);
printf("ccb %p - timed out already completed\n", ccb);
return;
@@ -1152,6 +1141,7 @@
if ((scb->flags & SCB_DEVICE_RESET) == 0 && aic->nexus == scb) {
struct ccb_hdr *ccb_h = &scb->ccb->ccb_h;
+ struct aic_scb *pending_scb;
if ((ccb_h->status & CAM_RELEASE_SIMQ) == 0) {
xpt_freeze_simq(aic->sim, /*count*/1);
@@ -1159,18 +1149,17 @@
}
TAILQ_FOREACH(ccb_h, &aic->pending_ccbs, sim_links.tqe) {
- untimeout(aic_timeout, (caddr_t)ccb_h->ccb_scb_ptr,
- ccb_h->timeout_ch);
+ pending_scb = ccb_h->ccb_scb_ptr;
+ callout_stop(&pending_scb->timer);
}
TAILQ_FOREACH(ccb_h, &aic->nexus_ccbs, sim_links.tqe) {
- untimeout(aic_timeout, (caddr_t)ccb_h->ccb_scb_ptr,
- ccb_h->timeout_ch);
+ pending_scb = ccb_h->ccb_scb_ptr;
+ callout_stop(&pending_scb->timer);
}
scb->flags |= SCB_DEVICE_RESET;
- ccb->ccb_h.timeout_ch =
- timeout(aic_timeout, (caddr_t)scb, 5 * hz);
+ callout_reset(&scb->timer, 5 * hz, aic_timeout, scb);
aic_sched_msgout(aic, MSG_BUS_DEV_RESET);
} else {
if (aic->nexus == scb) {
@@ -1179,8 +1168,6 @@
}
aic_reset(aic, /*initiate_reset*/TRUE);
}
-
- splx(s);
}
void
@@ -1187,6 +1174,15 @@
aic_intr(void *arg)
{
struct aic_softc *aic = (struct aic_softc *)arg;
+
+ mtx_lock(&aic->lock);
+ aic_intr_locked(aic);
+ mtx_unlock(&aic->lock);
+}
+
+void
+aic_intr_locked(struct aic_softc *aic)
+{
u_int8_t sstat0, sstat1;
union ccb *ccb;
struct aic_scb *scb;
@@ -1435,6 +1431,7 @@
TAILQ_INIT(&aic->pending_ccbs);
TAILQ_INIT(&aic->nexus_ccbs);
+ SLIST_INIT(&aic->free_scbs);
aic->nexus = NULL;
aic->state = AIC_IDLE;
aic->prev_phase = -1;
@@ -1482,10 +1479,10 @@
aic->max_period = AIC_SYNC_PERIOD;
aic->min_period = AIC_MIN_SYNC_PERIOD;
- free_scbs = NULL;
for (i = 255; i >= 0; i--) {
scb = &aic->scbs[i];
scb->tag = i;
+ callout_init_mtx(&scb->timer, &aic->lock, 0);
aic_free_scb(aic, scb);
}
@@ -1544,14 +1541,16 @@
* Construct our SIM entry
*/
aic->sim = cam_sim_alloc(aic_action, aic_poll, "aic", aic,
- aic->unit, &Giant, 2, 256, devq);
+ device_get_unit(aic->dev), &aic->lock, 2, 256, devq);
if (aic->sim == NULL) {
cam_simq_free(devq);
return (ENOMEM);
}
+ mtx_lock(&aic->lock);
if (xpt_bus_register(aic->sim, aic->dev, 0) != CAM_SUCCESS) {
cam_sim_free(aic->sim, /*free_devq*/TRUE);
+ mtx_unlock(&aic->lock);
return (ENXIO);
}
@@ -1560,12 +1559,13 @@
CAM_LUN_WILDCARD) != CAM_REQ_CMP) {
xpt_bus_deregister(cam_sim_path(aic->sim));
cam_sim_free(aic->sim, /*free_devq*/TRUE);
+ mtx_unlock(&aic->lock);
return (ENXIO);
}
aic_init(aic);
- printf("aic%d: %s", aic->unit, aic_chip_names[aic->chip_type]);
+ device_printf(aic->dev, "%s", aic_chip_names[aic->chip_type]);
if (aic->flags & AIC_DMA_ENABLE)
printf(", dma");
if (aic->flags & AIC_DISC_ENABLE)
@@ -1575,6 +1575,7 @@
if (aic->flags & AIC_FAST_ENABLE)
printf(", fast SCSI");
printf("\n");
+ mtx_unlock(&aic->lock);
return (0);
}
@@ -1581,9 +1582,18 @@
int
aic_detach(struct aic_softc *aic)
{
+ struct aic_scb *scb;
+ int i;
+
+ mtx_lock(&aic->lock);
xpt_async(AC_LOST_DEVICE, aic->path, NULL);
xpt_free_path(aic->path);
xpt_bus_deregister(cam_sim_path(aic->sim));
cam_sim_free(aic->sim, /*free_devq*/TRUE);
+ mtx_unlock(&aic->lock);
+ for (i = 255; i >= 0; i--) {
+ scb = &aic->scbs[i];
+ callout_drain(&scb->timer);
+ }
return (0);
}
Modified: trunk/sys/dev/aic/aic6360reg.h
===================================================================
--- trunk/sys/dev/aic/aic6360reg.h 2018-05-28 00:25:20 UTC (rev 10127)
+++ trunk/sys/dev/aic/aic6360reg.h 2018-05-28 00:27:43 UTC (rev 10128)
@@ -1,4 +1,4 @@
-/* $MidnightBSD: src/sys/dev/aic/aic6360reg.h,v 1.2 2008/12/02 02:24:30 laffer1 Exp $ */
+/* $MidnightBSD$ */
/*-
* Copyright (c) 1994 Charles Hannum.
* Copyright (c) 1994 Jarle Greipsland.
@@ -30,7 +30,7 @@
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
- * $FreeBSD$
+ * $FreeBSD: stable/10/sys/dev/aic/aic6360reg.h 139749 2005-01-06 01:43:34Z imp $
*/
#define SCSISEQ 0x00 /* SCSI sequence control */
Modified: trunk/sys/dev/aic/aic_cbus.c
===================================================================
--- trunk/sys/dev/aic/aic_cbus.c 2018-05-28 00:25:20 UTC (rev 10127)
+++ trunk/sys/dev/aic/aic_cbus.c 2018-05-28 00:27:43 UTC (rev 10128)
@@ -1,4 +1,4 @@
-/* $MidnightBSD: src/sys/dev/aic/aic_cbus.c,v 1.2 2008/12/02 02:24:30 laffer1 Exp $ */
+/* $MidnightBSD$ */
/*-
* Copyright (c) 1999 Luoqi Chen.
* All rights reserved.
@@ -26,11 +26,14 @@
*/
#include <sys/cdefs.h>
-__FBSDID("$FreeBSD$");
+__FBSDID("$FreeBSD: stable/10/sys/dev/aic/aic_cbus.c 241591 2012-10-15 16:09:59Z jhb $");
#include <sys/param.h>
+#include <sys/callout.h>
#include <sys/kernel.h>
+#include <sys/lock.h>
#include <sys/module.h>
+#include <sys/mutex.h>
#include <sys/bus.h>
#include <machine/bus.h>
@@ -93,7 +96,7 @@
else
bs_iat = aicport_generic;
- sc->sc_port = sc->sc_irq = sc->sc_drq = 0;
+ sc->sc_port = sc->sc_irq = sc->sc_drq = NULL;
rid = 0;
sc->sc_port = isa_alloc_resourcev(dev, SYS_RES_IOPORT, &rid,
@@ -103,6 +106,7 @@
return (ENOMEM);
}
isa_load_resourcev(sc->sc_port, bs_iat, AIC_ISA_PORTSIZE);
+ mtx_init(&sc->sc_aic.lock, "aic", NULL, MTX_DEF);
if (isa_get_irq(dev) != -1) {
rid = 0;
@@ -127,9 +131,7 @@
}
sc->sc_aic.dev = dev;
- sc->sc_aic.unit = device_get_unit(dev);
- sc->sc_aic.tag = rman_get_bustag(sc->sc_port);
- sc->sc_aic.bsh = rman_get_bushandle(sc->sc_port);
+ sc->sc_aic.res = sc->sc_port;
return (0);
}
@@ -144,7 +146,8 @@
bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sc_irq);
if (sc->sc_drq)
bus_release_resource(dev, SYS_RES_DRQ, 0, sc->sc_drq);
- sc->sc_port = sc->sc_irq = sc->sc_drq = 0;
+ sc->sc_port = sc->sc_irq = sc->sc_drq = NULL;
+ mtx_destroy(&sc->sc_aic.lock);
}
static int
@@ -173,10 +176,8 @@
continue;
if (aic_isa_alloc_resources(dev))
continue;
- if (!aic_probe(aic)) {
- aic_isa_release_resources(dev);
+ if (aic_probe(aic) == 0)
break;
- }
aic_isa_release_resources(dev);
}
@@ -184,6 +185,7 @@
return (ENXIO);
porta = aic_inb(aic, PORTA);
+ aic_isa_release_resources(dev);
if (isa_get_irq(dev) == -1)
bus_set_resource(dev, SYS_RES_IRQ, 0, PORTA_IRQ(porta), 1);
if ((aic->flags & AIC_DMA_ENABLE) && isa_get_drq(dev) == -1)
@@ -212,8 +214,8 @@
return (error);
}
- error = bus_setup_intr(dev, sc->sc_irq, INTR_TYPE_CAM|INTR_ENTROPY,
- NULL, aic_intr, aic, &sc->sc_ih);
+ error = bus_setup_intr(dev, sc->sc_irq, INTR_TYPE_CAM | INTR_ENTROPY |
+ INTR_MPSAFE, NULL, aic_intr, aic, &sc->sc_ih);
if (error) {
device_printf(dev, "failed to register interrupt handler\n");
aic_isa_release_resources(dev);
Modified: trunk/sys/dev/aic/aic_isa.c
===================================================================
--- trunk/sys/dev/aic/aic_isa.c 2018-05-28 00:25:20 UTC (rev 10127)
+++ trunk/sys/dev/aic/aic_isa.c 2018-05-28 00:27:43 UTC (rev 10128)
@@ -1,4 +1,4 @@
-/* $MidnightBSD: src/sys/dev/aic/aic_isa.c,v 1.2 2008/12/02 02:24:30 laffer1 Exp $ */
+/* $MidnightBSD$ */
/*-
* Copyright (c) 1999 Luoqi Chen.
* All rights reserved.
@@ -26,11 +26,14 @@
*/
#include <sys/cdefs.h>
-__FBSDID("$FreeBSD$");
+__FBSDID("$FreeBSD: stable/10/sys/dev/aic/aic_isa.c 241591 2012-10-15 16:09:59Z jhb $");
#include <sys/param.h>
+#include <sys/callout.h>
#include <sys/kernel.h>
+#include <sys/lock.h>
#include <sys/module.h>
+#include <sys/mutex.h>
#include <sys/bus.h>
#include <machine/bus.h>
@@ -70,7 +73,7 @@
struct aic_isa_softc *sc = device_get_softc(dev);
int rid;
- sc->sc_port = sc->sc_irq = sc->sc_drq = 0;
+ sc->sc_port = sc->sc_irq = sc->sc_drq = NULL;
rid = 0;
sc->sc_port = bus_alloc_resource(dev, SYS_RES_IOPORT, &rid,
@@ -103,9 +106,8 @@
}
sc->sc_aic.dev = dev;
- sc->sc_aic.unit = device_get_unit(dev);
- sc->sc_aic.tag = rman_get_bustag(sc->sc_port);
- sc->sc_aic.bsh = rman_get_bushandle(sc->sc_port);
+ sc->sc_aic.res = sc->sc_port;
+ mtx_init(&sc->sc_aic.lock, "aic", NULL, MTX_DEF);
return (0);
}
@@ -120,7 +122,8 @@
bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sc_irq);
if (sc->sc_drq)
bus_release_resource(dev, SYS_RES_DRQ, 0, sc->sc_drq);
- sc->sc_port = sc->sc_irq = sc->sc_drq = 0;
+ sc->sc_port = sc->sc_irq = sc->sc_drq = NULL;
+ mtx_destroy(&sc->sc_aic.lock);
}
static int
@@ -150,10 +153,8 @@
continue;
if (aic_isa_alloc_resources(dev))
continue;
- if (!aic_probe(aic)) {
- aic_isa_release_resources(dev);
+ if (aic_probe(aic) == 0)
break;
- }
aic_isa_release_resources(dev);
}
@@ -161,6 +162,7 @@
return (ENXIO);
porta = aic_inb(aic, PORTA);
+ aic_isa_release_resources(dev);
if (isa_get_irq(dev) == -1)
bus_set_resource(dev, SYS_RES_IRQ, 0, PORTA_IRQ(porta), 1);
if ((aic->flags & AIC_DMA_ENABLE) && isa_get_drq(dev) == -1)
@@ -189,8 +191,8 @@
return (error);
}
- error = bus_setup_intr(dev, sc->sc_irq, INTR_TYPE_CAM|INTR_ENTROPY,
- NULL, aic_intr, aic, &sc->sc_ih);
+ error = bus_setup_intr(dev, sc->sc_irq, INTR_TYPE_CAM | INTR_ENTROPY |
+ INTR_MPSAFE, NULL, aic_intr, aic, &sc->sc_ih);
if (error) {
device_printf(dev, "failed to register interrupt handler\n");
aic_isa_release_resources(dev);
Modified: trunk/sys/dev/aic/aic_pccard.c
===================================================================
--- trunk/sys/dev/aic/aic_pccard.c 2018-05-28 00:25:20 UTC (rev 10127)
+++ trunk/sys/dev/aic/aic_pccard.c 2018-05-28 00:27:43 UTC (rev 10128)
@@ -1,4 +1,4 @@
-/* $MidnightBSD: src/sys/dev/aic/aic_pccard.c,v 1.2 2008/12/02 02:24:30 laffer1 Exp $ */
+/* $MidnightBSD$ */
/*-
* Copyright (c) 1999 Luoqi Chen.
* All rights reserved.
@@ -26,11 +26,14 @@
*/
#include <sys/cdefs.h>
-__FBSDID("$FreeBSD$");
+__FBSDID("$FreeBSD: stable/10/sys/dev/aic/aic_pccard.c 241591 2012-10-15 16:09:59Z jhb $");
#include <sys/param.h>
+#include <sys/callout.h>
#include <sys/kernel.h>
+#include <sys/lock.h>
#include <sys/module.h>
+#include <sys/mutex.h>
#include <sys/bus.h>
#include <machine/bus.h>
@@ -72,7 +75,7 @@
struct aic_pccard_softc *sc = device_get_softc(dev);
int rid;
- sc->sc_port = sc->sc_irq = 0;
+ sc->sc_port = sc->sc_irq = NULL;
rid = 0;
sc->sc_port = bus_alloc_resource(dev, SYS_RES_IOPORT, &rid,
@@ -88,9 +91,8 @@
}
sc->sc_aic.dev = dev;
- sc->sc_aic.unit = device_get_unit(dev);
- sc->sc_aic.tag = rman_get_bustag(sc->sc_port);
- sc->sc_aic.bsh = rman_get_bushandle(sc->sc_port);
+ sc->sc_aic.res = sc->sc_port;
+ mtx_init(&sc->sc_aic.lock, "aic", NULL, MTX_DEF);
return (0);
}
@@ -103,7 +105,8 @@
bus_release_resource(dev, SYS_RES_IOPORT, 0, sc->sc_port);
if (sc->sc_irq)
bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sc_irq);
- sc->sc_port = sc->sc_irq = 0;
+ sc->sc_port = sc->sc_irq = NULL;
+ mtx_destroy(&sc->sc_aic.lock);
}
static int
@@ -115,9 +118,12 @@
sizeof(aic_pccard_products[0]), NULL)) != NULL) {
if (pp->pp_name != NULL)
device_set_desc(dev, pp->pp_name);
- return 0;
+ else
+ device_set_desc(dev,
+ "Adaptec 6260/6360 SCSI controller");
+ return (BUS_PROBE_DEFAULT);
}
- return EIO;
+ return (ENXIO);
}
static int
@@ -134,8 +140,6 @@
return (ENXIO);
}
- device_set_desc(dev, "Adaptec 6260/6360 SCSI controller");
-
error = aic_attach(aic);
if (error) {
device_printf(dev, "attach failed\n");
@@ -143,8 +147,8 @@
return (error);
}
- error = bus_setup_intr(dev, sc->sc_irq, INTR_TYPE_CAM|INTR_ENTROPY,
- NULL, aic_intr, aic, &sc->sc_ih);
+ error = bus_setup_intr(dev, sc->sc_irq, INTR_TYPE_CAM | INTR_ENTROPY |
+ INTR_MPSAFE, NULL, aic_intr, aic, &sc->sc_ih);
if (error) {
device_printf(dev, "failed to register interrupt handler\n");
aic_pccard_release_resources(dev);
Modified: trunk/sys/dev/aic/aicvar.h
===================================================================
--- trunk/sys/dev/aic/aicvar.h 2018-05-28 00:25:20 UTC (rev 10127)
+++ trunk/sys/dev/aic/aicvar.h 2018-05-28 00:27:43 UTC (rev 10128)
@@ -1,4 +1,4 @@
-/* $MidnightBSD: src/sys/dev/aic/aicvar.h,v 1.2 2008/12/02 02:24:30 laffer1 Exp $ */
+/* $MidnightBSD$ */
/*-
* Copyright (c) 1999 Luoqi Chen.
* All rights reserved.
@@ -24,7 +24,7 @@
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*
- * $FreeBSD$
+ * $FreeBSD: stable/10/sys/dev/aic/aicvar.h 241591 2012-10-15 16:09:59Z jhb $
*/
struct aic_transinfo {
@@ -48,6 +48,8 @@
struct aic_scb {
union ccb *ccb;
+ SLIST_ENTRY(aic_scb) link;
+ struct callout timer;
u_int8_t flags;
u_int8_t tag;
u_int8_t target;
@@ -71,14 +73,14 @@
struct aic_softc {
device_t dev;
- int unit;
- bus_space_tag_t tag;
- bus_space_handle_t bsh;
+ struct mtx lock;
+ struct resource *res;
bus_dma_tag_t dmat;
struct cam_sim *sim;
struct cam_path *path;
TAILQ_HEAD(,ccb_hdr) pending_ccbs, nexus_ccbs;
+ SLIST_HEAD(,aic_scb) free_scbs;
struct aic_scb *nexus;
u_int32_t flags;
@@ -128,32 +130,28 @@
#define AIC_SYNC_OFFSET 8
#define aic_inb(aic, port) \
- bus_space_read_1((aic)->tag, (aic)->bsh, (port))
+ bus_read_1((aic)->res, (port))
#define aic_outb(aic, port, value) \
- bus_space_write_1((aic)->tag, (aic)->bsh, (port), (value))
+ bus_write_1((aic)->res, (port), (value))
#define aic_insb(aic, port, addr, count) \
- bus_space_read_multi_1((aic)->tag, (aic)->bsh, (port), (addr), (count))
+ bus_read_multi_1((aic)->res, (port), (addr), (count))
#define aic_outsb(aic, port, addr, count) \
- bus_space_write_multi_1((aic)->tag, (aic)->bsh, (port), (addr), (count))
+ bus_write_multi_1((aic)->res, (port), (addr), (count))
#define aic_insw(aic, port, addr, count) \
- bus_space_read_multi_2((aic)->tag, (aic)->bsh, (port), \
- (u_int16_t *)(addr), (count))
+ bus_read_multi_2((aic)->res, (port), (u_int16_t *)(addr), (count))
#define aic_outsw(aic, port, addr, count) \
- bus_space_write_multi_2((aic)->tag, (aic)->bsh, (port), \
- (u_int16_t *)(addr), (count))
+ bus_write_multi_2((aic)->res, (port), (u_int16_t *)(addr), (count))
#define aic_insl(aic, port, addr, count) \
- bus_space_read_multi_4((aic)->tag, (aic)->bsh, (port), \
- (u_int32_t *)(addr), (count))
+ bus_read_multi_4((aic)->res, (port), (u_int32_t *)(addr), (count))
#define aic_outsl(aic, port, addr, count) \
- bus_space_write_multi_4((aic)->tag, (aic)->bsh, (port), \
- (u_int32_t *)(addr), (count))
+ bus_write_multi_4((aic)->res, (port), (u_int32_t *)(addr), (count))
extern int aic_probe(struct aic_softc *);
extern int aic_attach(struct aic_softc *);
Modified: trunk/sys/dev/aic7xxx/ahc_eisa.c
===================================================================
--- trunk/sys/dev/aic7xxx/ahc_eisa.c 2018-05-28 00:25:20 UTC (rev 10127)
+++ trunk/sys/dev/aic7xxx/ahc_eisa.c 2018-05-28 00:27:43 UTC (rev 10128)
@@ -1,3 +1,4 @@
+/* $MidnightBSD$ */
/*-
* FreeBSD, EISA product support functions
*
@@ -26,11 +27,11 @@
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*
- * $Id: ahc_eisa.c,v 1.1.1.4 2012-07-21 15:16:50 laffer1 Exp $
+ * $Id: //depot/aic7xxx/freebsd/dev/aic7xxx/ahc_eisa.c#13 $
*/
#include <sys/cdefs.h>
-__FBSDID("$FreeBSD$");
+__FBSDID("$FreeBSD: stable/10/sys/dev/aic7xxx/ahc_eisa.c 232882 2012-03-12 19:29:32Z jmallett $");
#include <dev/aic7xxx/aic7xxx_osm.h>
Modified: trunk/sys/dev/aic7xxx/ahc_isa.c
===================================================================
--- trunk/sys/dev/aic7xxx/ahc_isa.c 2018-05-28 00:25:20 UTC (rev 10127)
+++ trunk/sys/dev/aic7xxx/ahc_isa.c 2018-05-28 00:27:43 UTC (rev 10128)
@@ -1,3 +1,4 @@
+/* $MidnightBSD$ */
/*-
* FreeBSD, VLB/ISA product support functions
*
@@ -32,11 +33,11 @@
* IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGES.
*
- * $Id: ahc_isa.c,v 1.1.1.4 2012-07-21 15:16:50 laffer1 Exp $
+ * $Id$
*/
#include <sys/cdefs.h>
-__FBSDID("$FreeBSD$");
+__FBSDID("$FreeBSD: stable/10/sys/dev/aic7xxx/ahc_isa.c 249574 2013-04-17 02:33:56Z neel $");
#include <dev/aic7xxx/aic7xxx_osm.h>
@@ -98,7 +99,7 @@
RF_ACTIVE);
if (regs == NULL) {
if (bootverbose)
- printf("ahc_isa_probe %d: ioport 0x%x "
+ printf("ahc_isa_identify %d: ioport 0x%x "
"alloc failed\n", slot, iobase);
continue;
}
Modified: trunk/sys/dev/aic7xxx/ahc_pci.c
===================================================================
--- trunk/sys/dev/aic7xxx/ahc_pci.c 2018-05-28 00:25:20 UTC (rev 10127)
+++ trunk/sys/dev/aic7xxx/ahc_pci.c 2018-05-28 00:27:43 UTC (rev 10128)
@@ -1,3 +1,4 @@
+/* $MidnightBSD$ */
/*-
* FreeBSD, PCI product support functions
*
@@ -28,11 +29,11 @@
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*
- * $Id: ahc_pci.c,v 1.1.1.4 2012-07-21 15:16:50 laffer1 Exp $
+ * $Id: //depot/aic7xxx/freebsd/dev/aic7xxx/ahc_pci.c#19 $
*/
#include <sys/cdefs.h>
-__FBSDID("$FreeBSD$");
+__FBSDID("$FreeBSD: stable/10/sys/dev/aic7xxx/ahc_pci.c 254263 2013-08-12 23:30:01Z scottl $");
#include <dev/aic7xxx/aic7xxx_osm.h>
@@ -139,12 +140,10 @@
ahc_pci_map_registers(struct ahc_softc *ahc)
{
struct resource *regs;
- u_int command;
int regs_type;
int regs_id;
int allow_memio;
- command = aic_pci_read_config(ahc->dev_softc, PCIR_COMMAND, /*bytes*/1);
regs = NULL;
regs_type = 0;
regs_id = 0;
@@ -166,7 +165,7 @@
#endif
}
- if ((allow_memio != 0) && (command & PCIM_CMD_MEMEN) != 0) {
+ if (allow_memio != 0) {
regs_type = SYS_RES_MEMORY;
regs_id = AHC_PCI_MEMADDR;
@@ -190,16 +189,11 @@
bus_release_resource(ahc->dev_softc, regs_type,
regs_id, regs);
regs = NULL;
- } else {
- command &= ~PCIM_CMD_PORTEN;
- aic_pci_write_config(ahc->dev_softc,
- PCIR_COMMAND,
- command, /*bytes*/1);
}
}
}
- if (regs == NULL && (command & PCIM_CMD_PORTEN) != 0) {
+ if (regs == NULL) {
regs_type = SYS_RES_IOPORT;
regs_id = AHC_PCI_IOADDR;
regs = bus_alloc_resource_any(ahc->dev_softc, regs_type,
@@ -217,11 +211,6 @@
bus_release_resource(ahc->dev_softc, regs_type,
regs_id, regs);
regs = NULL;
- } else {
- command &= ~PCIM_CMD_MEMEN;
- aic_pci_write_config(ahc->dev_softc,
- PCIR_COMMAND,
- command, /*bytes*/1);
}
}
}
Modified: trunk/sys/dev/aic7xxx/ahd_pci.c
===================================================================
--- trunk/sys/dev/aic7xxx/ahd_pci.c 2018-05-28 00:25:20 UTC (rev 10127)
+++ trunk/sys/dev/aic7xxx/ahd_pci.c 2018-05-28 00:27:43 UTC (rev 10128)
@@ -1,3 +1,4 @@
+/* $MidnightBSD$ */
/*-
* FreeBSD, PCI product support functions
*
@@ -28,11 +29,11 @@
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*
- * $Id: ahd_pci.c,v 1.1.1.4 2012-07-21 15:16:50 laffer1 Exp $
+ * $Id: //depot/aic7xxx/freebsd/dev/aic7xxx/ahd_pci.c#17 $
*/
#include <sys/cdefs.h>
-__FBSDID("$FreeBSD$");
+__FBSDID("$FreeBSD: stable/10/sys/dev/aic7xxx/ahd_pci.c 254263 2013-08-12 23:30:01Z scottl $");
#include <dev/aic7xxx/aic79xx_osm.h>
@@ -143,13 +144,11 @@
{
struct resource *regs;
struct resource *regs2;
- u_int command;
int regs_type;
int regs_id;
int regs_id2;
int allow_memio;
- command = aic_pci_read_config(ahd->dev_softc, PCIR_COMMAND, /*bytes*/1);
regs = NULL;
regs2 = NULL;
regs_type = 0;
@@ -165,8 +164,7 @@
allow_memio = 1;
}
- if ((command & PCIM_CMD_MEMEN) != 0
- && (ahd->bugs & AHD_PCIX_MMAPIO_BUG) == 0
+ if ((ahd->bugs & AHD_PCIX_MMAPIO_BUG) == 0
&& allow_memio != 0) {
regs_type = SYS_RES_MEMORY;
@@ -199,15 +197,10 @@
regs_id, regs);
regs = NULL;
AHD_CORRECTABLE_ERROR(ahd);
- } else {
- command &= ~PCIM_CMD_PORTEN;
- aic_pci_write_config(ahd->dev_softc,
- PCIR_COMMAND,
- command, /*bytes*/1);
}
}
}
- if (regs == NULL && (command & PCIM_CMD_PORTEN) != 0) {
+ if (regs == NULL) {
regs_type = SYS_RES_IOPORT;
regs_id = AHD_PCI_IOADDR0;
regs = bus_alloc_resource_any(ahd->dev_softc, regs_type,
@@ -233,9 +226,6 @@
}
ahd->tags[1] = rman_get_bustag(regs2);
ahd->bshs[1] = rman_get_bushandle(regs2);
- command &= ~PCIM_CMD_MEMEN;
- aic_pci_write_config(ahd->dev_softc, PCIR_COMMAND,
- command, /*bytes*/1);
ahd->platform_data->regs_res_type[1] = regs_type;
ahd->platform_data->regs_res_id[1] = regs_id2;
ahd->platform_data->regs[1] = regs2;
Modified: trunk/sys/dev/aic7xxx/aic7770.c
===================================================================
--- trunk/sys/dev/aic7xxx/aic7770.c 2018-05-28 00:25:20 UTC (rev 10127)
+++ trunk/sys/dev/aic7xxx/aic7770.c 2018-05-28 00:27:43 UTC (rev 10128)
@@ -1,3 +1,4 @@
+/* $MidnightBSD$ */
/*-
* Product specific probe and attach routines for:
* 27/284X and aic7770 motherboard SCSI controllers
@@ -37,7 +38,7 @@
* IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGES.
*
- * $Id: aic7770.c,v 1.1.1.4 2012-07-21 15:16:50 laffer1 Exp $
+ * $Id: //depot/aic7xxx/aic7xxx/aic7770.c#34 $
*/
#ifdef __linux__
@@ -46,7 +47,7 @@
#include "aic7xxx_93cx6.h"
#else
#include <sys/cdefs.h>
-__FBSDID("$FreeBSD$");
+__FBSDID("$FreeBSD: stable/10/sys/dev/aic7xxx/aic7770.c 168807 2007-04-17 06:26:25Z scottl $");
#include <dev/aic7xxx/aic7xxx_osm.h>
#include <dev/aic7xxx/aic7xxx_inline.h>
#include <dev/aic7xxx/aic7xxx_93cx6.h>
Modified: trunk/sys/dev/aic7xxx/aic79xx.c
===================================================================
--- trunk/sys/dev/aic7xxx/aic79xx.c 2018-05-28 00:25:20 UTC (rev 10127)
+++ trunk/sys/dev/aic7xxx/aic79xx.c 2018-05-28 00:27:43 UTC (rev 10128)
@@ -1,3 +1,4 @@
+/* $MidnightBSD$ */
/*-
* Core routines and tables shareable across OS platforms.
*
@@ -37,9 +38,7 @@
* IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGES.
*
- * $MidnightBSD$
- * $FreeBSD: src/sys/dev/aic7xxx/aic79xx.c,v 1.40 2007/04/19 18:53:52 scottl Exp $
- * $Id: aic79xx.c,v 1.5 2012-08-06 01:19:11 laffer1 Exp $
+ * $Id: //depot/aic7xxx/aic7xxx/aic79xx.c#246 $
*/
#ifdef __linux__
@@ -48,6 +47,7 @@
#include "aicasm/aicasm_insformat.h"
#else
#include <sys/cdefs.h>
+__FBSDID("$FreeBSD: stable/10/sys/dev/aic7xxx/aic79xx.c 315140 2017-03-12 06:20:28Z mav $");
#include <dev/aic7xxx/aic79xx_osm.h>
#include <dev/aic7xxx/aic79xx_inline.h>
#include <dev/aic7xxx/aicasm/aicasm_insformat.h>
@@ -1210,7 +1210,7 @@
* that requires host assistance for completion.
* While handling the message phase(s), we will be
* notified by the sequencer after each byte is
- * transfered so we can track bus phase changes.
+ * transferred so we can track bus phase changes.
*
* If this is the first time we've seen a HOST_MSG_LOOP
* interrupt, initialize the state of the host message
@@ -1624,7 +1624,7 @@
/*
* Although the driver does not care about the
* 'Selection in Progress' status bit, the busy
- * LED does. SELINGO is only cleared by a sucessfull
+ * LED does. SELINGO is only cleared by a successful
* selection, so we must manually clear it to insure
* the LED turns off just incase no future successful
* selections occur (e.g. no devices on the bus).
@@ -2266,6 +2266,7 @@
printerror = 0;
} else if (ahd_sent_msg(ahd, AHDMSG_1B,
MSG_BUS_DEV_RESET, TRUE)) {
+#ifdef __FreeBSD__
/*
* Don't mark the user's request for this BDR
* as completing with CAM_BDR_SENT. CAM3
@@ -2277,6 +2278,7 @@
CAM_LUN_WILDCARD, SCB_LIST_NULL,
ROLE_INITIATOR))
aic_set_transaction_status(scb, CAM_REQ_CMP);
+#endif
ahd_handle_devreset(ahd, &devinfo, CAM_LUN_WILDCARD,
CAM_BDR_SENT, "Bus Device Reset",
/*verbose_level*/0);
@@ -2698,7 +2700,7 @@
ahd_outb(ahd, SEQCTL0, ahd_inb(ahd, SEQCTL0) & ~STEP);
ahd_outb(ahd, SIMODE1, simode1);
/*
- * SCSIINT seems to glitch occassionally when
+ * SCSIINT seems to glitch occasionally when
* the interrupt masks are restored. Clear SCSIINT
* one more time so that only persistent errors
* are seen as a real interrupt.
@@ -3028,7 +3030,7 @@
/*
* Update the bitmask of targets for which the controller should
- * negotiate with at the next convenient oportunity. This currently
+ * negotiate with at the next convenient opportunity. This currently
* means the next time we send the initial identify messages for
* a new transaction.
*/
@@ -3379,7 +3381,7 @@
/*
* During packetized transfers, the target will
- * give us the oportunity to send command packets
+ * give us the opportunity to send command packets
* without us asserting attention.
*/
if ((tinfo->ppr_options & MSG_EXT_PPR_IU_REQ) == 0)
@@ -4844,7 +4846,7 @@
/*
* Requeue all tagged commands for this target
- * currently in our posession so they can be
+ * currently in our possession so they can be
* converted to untagged commands.
*/
ahd_search_qinfifo(ahd, SCB_GET_TARGET(ahd, scb),
@@ -5269,11 +5271,23 @@
{
struct ahd_softc *ahd;
+#ifndef __FreeBSD__
+ ahd = malloc(sizeof(*ahd), M_DEVBUF, M_NOWAIT);
+ if (!ahd) {
+ printf("aic7xxx: cannot malloc softc!\n");
+ free(name, M_DEVBUF);
+ return NULL;
+ }
+#else
ahd = device_get_softc((device_t)platform_arg);
+#endif
memset(ahd, 0, sizeof(*ahd));
ahd->seep_config = malloc(sizeof(*ahd->seep_config),
M_DEVBUF, M_NOWAIT);
if (ahd->seep_config == NULL) {
+#ifndef __FreeBSD__
+ free(ahd, M_DEVBUF);
+#endif
free(name, M_DEVBUF);
return (NULL);
}
@@ -5459,6 +5473,9 @@
free(ahd->seep_config, M_DEVBUF);
if (ahd->saved_stack != NULL)
free(ahd->saved_stack, M_DEVBUF);
+#ifndef __FreeBSD__
+ free(ahd, M_DEVBUF);
+#endif
return;
}
@@ -5482,7 +5499,7 @@
/*
* Reset the controller and record some information about it
* that is only available just after a reset. If "reinit" is
- * non-zero, this reset occured after initial configuration
+ * non-zero, this reset occurred after initial configuration
* and the caller requests that the chip be fully reinitialized
* to a runable state. Chip interrupts are *not* enabled after
* a reinitialization. The caller must enable interrupts via
@@ -5735,7 +5752,7 @@
}
/*
- * Note that we were successfull
+ * Note that we were successful
*/
return (0);
@@ -8778,7 +8795,7 @@
cur_patch += cur_patch->skip_patch;
} else {
/* Accepted this patch. Advance to the next
- * one and wait for our intruction pointer to
+ * one and wait for our instruction pointer to
* hit this point.
*/
cur_patch++;
@@ -9657,7 +9674,7 @@
return (error);
/*
- * Write the data. If we don't get throught the loop at
+ * Write the data. If we don't get through the loop at
* least once, the arguments were invalid.
*/
retval = EINVAL;
@@ -9911,7 +9928,8 @@
u_int our_id;
our_id = ahd->our_id;
- if (ccb->ccb_h.target_id != our_id) {
+ if (ccb->ccb_h.target_id != our_id
+ && ccb->ccb_h.target_id != CAM_TARGET_WILDCARD) {
if ((ahd->features & AHD_MULTI_TID) != 0
&& (ahd->flags & AHD_INITIATORROLE) != 0) {
/*
@@ -10326,9 +10344,9 @@
/* Tag was included */
atio->tag_action = *byte++;
atio->tag_id = *byte++;
- atio->ccb_h.flags = CAM_TAG_ACTION_VALID;
+ atio->ccb_h.flags |= CAM_TAG_ACTION_VALID;
} else {
- atio->ccb_h.flags = 0;
+ atio->ccb_h.flags &= ~CAM_TAG_ACTION_VALID;
}
byte++;
Modified: trunk/sys/dev/aic7xxx/aic79xx.h
===================================================================
--- trunk/sys/dev/aic7xxx/aic79xx.h 2018-05-28 00:25:20 UTC (rev 10127)
+++ trunk/sys/dev/aic7xxx/aic79xx.h 2018-05-28 00:27:43 UTC (rev 10128)
@@ -1,3 +1,4 @@
+/* $MidnightBSD$ */
/*-
* Core definitions and data structures shareable across OS platforms.
*
@@ -37,9 +38,9 @@
* IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGES.
*
- * $Id: aic79xx.h,v 1.1.1.4 2012-07-21 15:16:50 laffer1 Exp $
+ * $Id: //depot/aic7xxx/aic7xxx/aic79xx.h#107 $
*
- * $FreeBSD$
+ * $FreeBSD: stable/10/sys/dev/aic7xxx/aic79xx.h 300060 2016-05-17 15:18:01Z pfg $
*/
#ifndef _AIC79XX_H_
@@ -478,7 +479,7 @@
* each S/G element is expired, its datacnt field is checked to see
* if the LAST_SEG flag is set. If so, SG_LIST_NULL is set in the
* residual sg ptr and the transfer is considered complete. If the
- * sequencer determines that there is a residual in the tranfer, or
+ * sequencer determines that there is a residual in the transfer, or
* there is non-zero status, it will set the SG_STATUS_VALID flag in
* sgptr and dma the scb back into host memory. To sumarize:
*
@@ -486,7 +487,7 @@
* o A residual has occurred if SG_FULL_RESID is set in sgptr,
* or residual_sgptr does not have SG_LIST_NULL set.
*
- * o We are transfering the last segment if residual_datacnt has
+ * o We are transferring the last segment if residual_datacnt has
* the SG_LAST_SEG flag set.
*
* Host:
@@ -529,7 +530,7 @@
*/
/*
- * Definition of a scatter/gather element as transfered to the controller.
+ * Definition of a scatter/gather element as transferred to the controller.
* The aic7xxx chips only support a 24bit length. We use the top byte of
* the length to store additional address bits and a flag to indicate
* that a given segment terminates the transfer. This gives us an
Modified: trunk/sys/dev/aic7xxx/aic79xx.reg
===================================================================
--- trunk/sys/dev/aic7xxx/aic79xx.reg 2018-05-28 00:25:20 UTC (rev 10127)
+++ trunk/sys/dev/aic7xxx/aic79xx.reg 2018-05-28 00:27:43 UTC (rev 10128)
@@ -37,9 +37,9 @@
* IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGES.
*
- * $FreeBSD$
+ * $FreeBSD: stable/10/sys/dev/aic7xxx/aic79xx.reg 300060 2016-05-17 15:18:01Z pfg $
*/
-VERSION = "$Id: aic79xx.reg,v 1.1.1.3 2012-07-21 15:16:50 laffer1 Exp $"
+VERSION = "$Id: //depot/aic7xxx/aic7xxx/aic79xx.reg#76 $"
/*
* This file is processed by the aic7xxx_asm utility for use in assembling
@@ -283,7 +283,7 @@
}
/*
- * Sequencer Interupt Status
+ * Sequencer Interrupt Status
*/
register SEQINTSTAT {
address 0x00C
@@ -643,7 +643,7 @@
}
/*
- * CMC Recieve Message 0
+ * CMC Receive Message 0
*/
register CMCRXMSG0 {
address 0x090
@@ -654,7 +654,7 @@
}
/*
- * Overlay Recieve Message 0
+ * Overlay Receive Message 0
*/
register OVLYRXMSG0 {
address 0x090
@@ -690,7 +690,7 @@
}
/*
- * CMC Recieve Message 1
+ * CMC Receive Message 1
*/
register CMCRXMSG1 {
address 0x091
@@ -700,7 +700,7 @@
}
/*
- * Overlay Recieve Message 1
+ * Overlay Receive Message 1
*/
register OVLYRXMSG1 {
address 0x091
@@ -735,7 +735,7 @@
}
/*
- * CMC Recieve Message 2
+ * CMC Receive Message 2
*/
register CMCRXMSG2 {
address 0x092
@@ -745,7 +745,7 @@
}
/*
- * Overlay Recieve Message 2
+ * Overlay Receive Message 2
*/
register OVLYRXMSG2 {
address 0x092
@@ -774,7 +774,7 @@
}
/*
- * CMC Recieve Message 3
+ * CMC Receive Message 3
*/
register CMCRXMSG3 {
address 0x093
@@ -784,7 +784,7 @@
}
/*
- * Overlay Recieve Message 3
+ * Overlay Receive Message 3
*/
register OVLYRXMSG3 {
address 0x093
@@ -1192,7 +1192,7 @@
/*
* LQ Packet In
- * The last LQ Packet recieved
+ * The last LQ Packet received
*/
register LQIN {
address 0x020
@@ -2424,7 +2424,7 @@
}
/*
- * Shaddow Host Address.
+ * Shadow Host Address.
*/
register SHADDR {
address 0x060
@@ -3726,7 +3726,7 @@
/*
* The maximum amount of time to wait, when interrupt coalescing
- * is enabled, before issueing a CMDCMPLT interrupt for a completed
+ * is enabled, before issuing a CMDCMPLT interrupt for a completed
* command.
*/
INT_COALESCING_TIMER {
Property changes on: trunk/sys/dev/aic7xxx/aic79xx.reg
___________________________________________________________________
Added: mnbsd:nokeywords
## -0,0 +1 ##
+MidnightBSD=%H
\ No newline at end of property
Modified: trunk/sys/dev/aic7xxx/aic79xx.seq
===================================================================
--- trunk/sys/dev/aic7xxx/aic79xx.seq 2018-05-28 00:25:20 UTC (rev 10127)
+++ trunk/sys/dev/aic7xxx/aic79xx.seq 2018-05-28 00:27:43 UTC (rev 10128)
@@ -37,10 +37,10 @@
* IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGES.
*
- * $FreeBSD$
+ * $FreeBSD: stable/10/sys/dev/aic7xxx/aic79xx.seq 300060 2016-05-17 15:18:01Z pfg $
*/
-VERSION = "$Id: aic79xx.seq,v 1.1.1.4 2012-07-21 15:16:50 laffer1 Exp $"
+VERSION = "$Id: //depot/aic7xxx/aic7xxx/aic79xx.seq#119 $"
PATCH_ARG_LIST = "struct ahd_softc *ahd"
PREFIX = "ahd_"
@@ -217,7 +217,7 @@
scbdma_tohost_done:
test CCSCBCTL, CCARREN jz fill_qoutfifo_dmadone;
/*
- * An SCB has been succesfully uploaded to the host.
+ * An SCB has been successfully uploaded to the host.
* If the SCB was uploaded for some reason other than
* bad SCSI status (currently only for underruns), we
* queue the SCB for normal completion. Otherwise, we
@@ -960,7 +960,7 @@
* This is done to allow the host to send messages outside of an identify
* sequence while protecting the seqencer from testing the MK_MESSAGE bit
* on an SCB that might not be for the current nexus. (For example, a
- * BDR message in responce to a bad reselection would leave us pointed to
+ * BDR message in response to a bad reselection would leave us pointed to
* an SCB that doesn't have anything to do with the current target).
*
* Otherwise, treat MSG_OUT as a 1 byte message to send (abort, abort tag,
@@ -1507,7 +1507,7 @@
* If the other FIFO needs loading, then it
* must not have claimed the S/G cache yet
* (SG_CACHE_AVAIL would have been cleared in
- * the orginal FIFO mode and we test this above).
+ * the original FIFO mode and we test this above).
* Return to the idle loop so we can process the
* FIFO not currently on the bus first.
*/
@@ -1551,7 +1551,7 @@
test DFSTATUS, PRELOAD_AVAIL jz return;
/*
* On the A, preloading a segment before HDMAENACK
- * comes true can clobber the shaddow address of the
+ * comes true can clobber the shadow address of the
* first segment in the S/G FIFO. Wait until it is
* safe to proceed.
*/
@@ -2004,10 +2004,10 @@
* Defer handling of this NONPACKREQ until we
* can be sure it pertains to this FIFO. SAVEPTRS
* will not be asserted if the NONPACKREQ is for us,
- * so we must simulate it if shaddow is valid. If
- * shaddow is not valid, keep running this FIFO until we
+ * so we must simulate it if shadow is valid. If
+ * shadow is not valid, keep running this FIFO until we
* have satisfied the transfer by loading segments and
- * waiting for either shaddow valid or last_seg_done.
+ * waiting for either shadow valid or last_seg_done.
*/
test MDFFSTAT, SHVALID jnz pkt_saveptrs;
pkt_service_fifo:
@@ -2171,7 +2171,7 @@
/*
* The unexpected nonpkt phase handler assumes that any
* data channel use will have a FIFO reference count. It
- * turns out that the status handler doesn't need a refernce
+ * turns out that the status handler doesn't need a references
* count since the status received flag, and thus completion
* processing, cannot be set until the handler is finished.
* We increment the count here to make the nonpkt handler
Property changes on: trunk/sys/dev/aic7xxx/aic79xx.seq
___________________________________________________________________
Added: mnbsd:nokeywords
## -0,0 +1 ##
+MidnightBSD=%H
\ No newline at end of property
Modified: trunk/sys/dev/aic7xxx/aic79xx_inline.h
===================================================================
--- trunk/sys/dev/aic7xxx/aic79xx_inline.h 2018-05-28 00:25:20 UTC (rev 10127)
+++ trunk/sys/dev/aic7xxx/aic79xx_inline.h 2018-05-28 00:27:43 UTC (rev 10128)
@@ -1,3 +1,4 @@
+/* $MidnightBSD$ */
/*-
* Inline routines shareable across OS platforms.
*
@@ -37,9 +38,9 @@
* IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGES.
*
- * $Id: aic79xx_inline.h,v 1.1.1.3 2012-07-21 15:16:50 laffer1 Exp $
+ * $Id: //depot/aic7xxx/aic7xxx/aic79xx_inline.h#57 $
*
- * $FreeBSD$
+ * $FreeBSD: stable/10/sys/dev/aic7xxx/aic79xx_inline.h 300060 2016-05-17 15:18:01Z pfg $
*/
#ifndef _AIC79XX_INLINE_H_
@@ -417,7 +418,7 @@
- (uint8_t *)ahd->qoutfifo);
}
-/*********************** Miscelaneous Support Functions ***********************/
+/********************** Miscellaneous Support Functions ***********************/
static __inline void ahd_complete_scb(struct ahd_softc *ahd,
struct scb *scb);
static __inline void ahd_update_residual(struct ahd_softc *ahd,
@@ -534,7 +535,7 @@
ahd_outw(struct ahd_softc *ahd, u_int port, u_int value)
{
/*
- * Write low byte first to accomodate registers
+ * Write low byte first to accommodate registers
* such as PRGMCNT where the order maters.
*/
ahd_outb(ahd, port, value & 0xFF);
Modified: trunk/sys/dev/aic7xxx/aic79xx_osm.c
===================================================================
--- trunk/sys/dev/aic7xxx/aic79xx_osm.c 2018-05-28 00:25:20 UTC (rev 10127)
+++ trunk/sys/dev/aic7xxx/aic79xx_osm.c 2018-05-28 00:27:43 UTC (rev 10128)
@@ -1,3 +1,4 @@
+/* $MidnightBSD$ */
/*-
* Bus independent FreeBSD shim for the aic79xx based Adaptec SCSI controllers
*
@@ -29,11 +30,11 @@
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*
- * $Id: aic79xx_osm.c,v 1.1.1.4 2012-07-21 15:16:50 laffer1 Exp $
+ * $Id: //depot/aic7xxx/freebsd/dev/aic7xxx/aic79xx_osm.c#35 $
*/
#include <sys/cdefs.h>
-__FBSDID("$FreeBSD$");
+__FBSDID("$FreeBSD: stable/10/sys/dev/aic7xxx/aic79xx_osm.c 315813 2017-03-23 06:41:13Z mav $");
#include <dev/aic7xxx/aic79xx_osm.h>
#include <dev/aic7xxx/aic79xx_inline.h>
@@ -699,9 +700,9 @@
}
cpi->bus_id = cam_sim_bus(sim);
cpi->base_transfer_speed = 3300;
- strncpy(cpi->sim_vid, "FreeBSD", SIM_IDLEN);
- strncpy(cpi->hba_vid, "Adaptec", HBA_IDLEN);
- strncpy(cpi->dev_name, cam_sim_name(sim), DEV_IDLEN);
+ strlcpy(cpi->sim_vid, "FreeBSD", SIM_IDLEN);
+ strlcpy(cpi->hba_vid, "Adaptec", HBA_IDLEN);
+ strlcpy(cpi->dev_name, cam_sim_name(sim), DEV_IDLEN);
cpi->unit_number = cam_sim_unit(sim);
cpi->protocol = PROTO_SCSI;
cpi->protocol_version = SCSI_REV_2;
@@ -1071,6 +1072,7 @@
{
struct hardware_scb *hscb;
struct ccb_hdr *ccb_h;
+ int error;
hscb = scb->hscb;
ccb_h = &csio->ccb_h;
@@ -1120,64 +1122,18 @@
}
}
- /* Only use S/G if there is a transfer */
- if ((ccb_h->flags & CAM_DIR_MASK) != CAM_DIR_NONE) {
- if ((ccb_h->flags & CAM_SCATTER_VALID) == 0) {
- /* We've been given a pointer to a single buffer */
- if ((ccb_h->flags & CAM_DATA_PHYS) == 0) {
- int s;
- int error;
-
- s = splsoftvm();
- error = bus_dmamap_load(ahd->buffer_dmat,
- scb->dmamap,
- csio->data_ptr,
- csio->dxfer_len,
- ahd_execute_scb,
- scb, /*flags*/0);
- if (error == EINPROGRESS) {
- /*
- * So as to maintain ordering,
- * freeze the controller queue
- * until our mapping is
- * returned.
- */
- xpt_freeze_simq(sim,
- /*count*/1);
- scb->io_ctx->ccb_h.status |=
- CAM_RELEASE_SIMQ;
- }
- splx(s);
- } else {
- struct bus_dma_segment seg;
-
- /* Pointer to physical buffer */
- if (csio->dxfer_len > AHD_MAXTRANSFER_SIZE)
- panic("ahd_setup_data - Transfer size "
- "larger than can device max");
-
- seg.ds_addr =
- (bus_addr_t)(vm_offset_t)csio->data_ptr;
- seg.ds_len = csio->dxfer_len;
- ahd_execute_scb(scb, &seg, 1, 0);
- }
- } else {
- struct bus_dma_segment *segs;
-
- if ((ccb_h->flags & CAM_DATA_PHYS) != 0)
- panic("ahd_setup_data - Physical segment "
- "pointers unsupported");
-
- if ((ccb_h->flags & CAM_SG_LIST_PHYS) == 0)
- panic("ahd_setup_data - Virtual segment "
- "addresses unsupported");
-
- /* Just use the segments provided */
- segs = (struct bus_dma_segment *)csio->data_ptr;
- ahd_execute_scb(scb, segs, csio->sglist_cnt, 0);
- }
- } else {
- ahd_execute_scb(scb, NULL, 0, 0);
+ error = bus_dmamap_load_ccb(ahd->buffer_dmat,
+ scb->dmamap,
+ (union ccb *)csio,
+ ahd_execute_scb,
+ scb, /*flags*/0);
+ if (error == EINPROGRESS) {
+ /*
+ * So as to maintain ordering, freeze the controller queue
+ * until our mapping is returned.
+ */
+ xpt_freeze_simq(sim, /*count*/1);
+ scb->io_ctx->ccb_h.status |= CAM_RELEASE_SIMQ;
}
}
Modified: trunk/sys/dev/aic7xxx/aic79xx_osm.h
===================================================================
--- trunk/sys/dev/aic7xxx/aic79xx_osm.h 2018-05-28 00:25:20 UTC (rev 10127)
+++ trunk/sys/dev/aic7xxx/aic79xx_osm.h 2018-05-28 00:27:43 UTC (rev 10128)
@@ -1,3 +1,4 @@
+/* $MidnightBSD$ */
/*-
* FreeBSD platform specific driver option settings, data structures,
* function declarations and includes.
@@ -30,9 +31,9 @@
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*
- * $Id: aic79xx_osm.h,v 1.5 2012-08-06 01:19:11 laffer1 Exp $
+ * $Id: //depot/aic7xxx/freebsd/dev/aic7xxx/aic79xx_osm.h#23 $
*
- * $MidnightBSD: src/sys/dev/aic7xxx/aic79xx_osm.h,v 1.4 2009/03/15 14:24:21 laffer1 Exp $
+ * $FreeBSD: stable/10/sys/dev/aic7xxx/aic79xx_osm.h 218909 2011-02-21 09:01:34Z brucec $
*/
#ifndef _AIC79XX_FREEBSD_H_
@@ -43,7 +44,9 @@
#include <sys/param.h>
#include <sys/systm.h>
#include <sys/bus.h> /* For device_t */
+#if __FreeBSD_version >= 500000
#include <sys/endian.h>
+#endif
#include <sys/eventhandler.h>
#include <sys/kernel.h>
#include <sys/malloc.h>
@@ -58,8 +61,13 @@
#include <sys/rman.h>
+#if __FreeBSD_version >= 500000
#include <dev/pci/pcireg.h>
#include <dev/pci/pcivar.h>
+#else
+#include <pci/pcireg.h>
+#include <pci/pcivar.h>
+#endif
#include <cam/cam.h>
#include <cam/cam_ccb.h>
Modified: trunk/sys/dev/aic7xxx/aic79xx_pci.c
===================================================================
--- trunk/sys/dev/aic7xxx/aic79xx_pci.c 2018-05-28 00:25:20 UTC (rev 10127)
+++ trunk/sys/dev/aic7xxx/aic79xx_pci.c 2018-05-28 00:27:43 UTC (rev 10128)
@@ -1,3 +1,4 @@
+/* $MidnightBSD$ */
/*-
* Product specific probe and attach routines for:
* aic7901 and aic7902 SCSI controllers
@@ -38,7 +39,7 @@
* IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGES.
*
- * $Id: aic79xx_pci.c,v 1.3 2012-08-06 01:19:11 laffer1 Exp $
+ * $Id: //depot/aic7xxx/aic7xxx/aic79xx_pci.c#88 $
*/
#ifdef __linux__
@@ -46,7 +47,7 @@
#include "aic79xx_inline.h"
#else
#include <sys/cdefs.h>
-__FBSDID("$FreeBSD$");
+__FBSDID("$FreeBSD: stable/10/sys/dev/aic7xxx/aic79xx_pci.c 300060 2016-05-17 15:18:01Z pfg $");
#include <dev/aic7xxx/aic79xx_osm.h>
#include <dev/aic7xxx/aic79xx_inline.h>
#endif
@@ -93,6 +94,11 @@
#define ID_AIC7902_PCI_REV_A4 0x3
#define ID_AIC7902_PCI_REV_B0 0x10
#define SUBID_HP 0x0E11
+#define DEVICE8081 0x8081
+#define DEVICE8088 0x8088
+#define DEVICE8089 0x8089
+#define ADAPTECVENDORID 0x9005
+#define SUBVENDOR9005 0x9005
#define DEVID_9005_HOSTRAID(id) ((id) & 0x80)
@@ -292,6 +298,15 @@
device = aic_pci_read_config(pci, PCIR_DEVICE, /*bytes*/2);
subvendor = aic_pci_read_config(pci, PCIR_SUBVEND_0, /*bytes*/2);
subdevice = aic_pci_read_config(pci, PCIR_SUBDEV_0, /*bytes*/2);
+
+ if ((vendor == ADAPTECVENDORID) && (subvendor == SUBVENDOR9005)) {
+ if ((device == DEVICE8081) || (device == DEVICE8088) ||
+ (device == DEVICE8089)) {
+ printf("Controller device ID conflict with PMC Adaptec HBA\n");
+ return (NULL);
+ }
+ }
+
full_id = ahd_compose_id(device,
vendor,
subdevice,
@@ -477,7 +492,7 @@
* Next create a situation where write combining
* or read prefetching could be initiated by the
* CPU or host bridge. Our device does not support
- * either, so look for data corruption and/or flaged
+ * either, so look for data corruption and/or flagged
* PCI errors. First pause without causing another
* chip reset.
*/
@@ -999,7 +1014,7 @@
| AHD_FAINT_LED_BUG;
/*
- * IO Cell paramter setup.
+ * IO Cell parameter setup.
*/
AHD_SET_PRECOMP(ahd, AHD_PRECOMP_CUTBACK_29);
@@ -1020,7 +1035,7 @@
| AHD_BUSFREEREV_BUG;
/*
- * IO Cell paramter setup.
+ * IO Cell parameter setup.
*/
AHD_SET_PRECOMP(ahd, AHD_PRECOMP_CUTBACK_29);
AHD_SET_SLEWRATE(ahd, AHD_SLEWRATE_DEF_REVB);
Added: trunk/sys/dev/aic7xxx/aic79xx_reg.h
===================================================================
--- trunk/sys/dev/aic7xxx/aic79xx_reg.h (rev 0)
+++ trunk/sys/dev/aic7xxx/aic79xx_reg.h 2018-05-28 00:27:43 UTC (rev 10128)
@@ -0,0 +1,3827 @@
+/* $MidnightBSD$ */
+/*
+ * DO NOT EDIT - This file is automatically generated
+ * from the following source files:
+ *
+ * $Id: //depot/aic7xxx/aic7xxx/aic79xx.seq#119 $
+ * $Id: //depot/aic7xxx/aic7xxx/aic79xx.reg#76 $
+ *
+ * $FreeBSD: stable/10/sys/dev/aic7xxx/aic79xx_reg.h 270284 2014-08-21 17:18:21Z ian $
+ */
+typedef int (ahd_reg_print_t)(u_int, u_int *, u_int);
+typedef struct ahd_reg_parse_entry {
+ char *name;
+ uint8_t value;
+ uint8_t mask;
+} ahd_reg_parse_entry_t;
+
+#if AIC_DEBUG_REGISTERS
+ahd_reg_print_t ahd_mode_ptr_print;
+#else
+#define ahd_mode_ptr_print(regvalue, cur_col, wrap) \
+ ahd_print_register(NULL, 0, "MODE_PTR", 0x00, regvalue, cur_col, wrap)
+#endif
+
+#if AIC_DEBUG_REGISTERS
+ahd_reg_print_t ahd_intstat_print;
+#else
+#define ahd_intstat_print(regvalue, cur_col, wrap) \
+ ahd_print_register(NULL, 0, "INTSTAT", 0x01, regvalue, cur_col, wrap)
+#endif
+
+#if AIC_DEBUG_REGISTERS
+ahd_reg_print_t ahd_seqintcode_print;
+#else
+#define ahd_seqintcode_print(regvalue, cur_col, wrap) \
+ ahd_print_register(NULL, 0, "SEQINTCODE", 0x02, regvalue, cur_col, wrap)
+#endif
+
+#if AIC_DEBUG_REGISTERS
+ahd_reg_print_t ahd_clrint_print;
+#else
+#define ahd_clrint_print(regvalue, cur_col, wrap) \
+ ahd_print_register(NULL, 0, "CLRINT", 0x03, regvalue, cur_col, wrap)
+#endif
+
+#if AIC_DEBUG_REGISTERS
+ahd_reg_print_t ahd_error_print;
+#else
+#define ahd_error_print(regvalue, cur_col, wrap) \
+ ahd_print_register(NULL, 0, "ERROR", 0x04, regvalue, cur_col, wrap)
+#endif
+
+#if AIC_DEBUG_REGISTERS
+ahd_reg_print_t ahd_clrerr_print;
+#else
+#define ahd_clrerr_print(regvalue, cur_col, wrap) \
+ ahd_print_register(NULL, 0, "CLRERR", 0x04, regvalue, cur_col, wrap)
+#endif
+
+#if AIC_DEBUG_REGISTERS
+ahd_reg_print_t ahd_hcntrl_print;
+#else
+#define ahd_hcntrl_print(regvalue, cur_col, wrap) \
+ ahd_print_register(NULL, 0, "HCNTRL", 0x05, regvalue, cur_col, wrap)
+#endif
+
+#if AIC_DEBUG_REGISTERS
+ahd_reg_print_t ahd_hnscb_qoff_print;
+#else
+#define ahd_hnscb_qoff_print(regvalue, cur_col, wrap) \
+ ahd_print_register(NULL, 0, "HNSCB_QOFF", 0x06, regvalue, cur_col, wrap)
+#endif
+
+#if AIC_DEBUG_REGISTERS
+ahd_reg_print_t ahd_hescb_qoff_print;
+#else
+#define ahd_hescb_qoff_print(regvalue, cur_col, wrap) \
+ ahd_print_register(NULL, 0, "HESCB_QOFF", 0x08, regvalue, cur_col, wrap)
+#endif
+
+#if AIC_DEBUG_REGISTERS
+ahd_reg_print_t ahd_hs_mailbox_print;
+#else
+#define ahd_hs_mailbox_print(regvalue, cur_col, wrap) \
+ ahd_print_register(NULL, 0, "HS_MAILBOX", 0x0b, regvalue, cur_col, wrap)
+#endif
+
+#if AIC_DEBUG_REGISTERS
+ahd_reg_print_t ahd_seqintstat_print;
+#else
+#define ahd_seqintstat_print(regvalue, cur_col, wrap) \
+ ahd_print_register(NULL, 0, "SEQINTSTAT", 0x0c, regvalue, cur_col, wrap)
+#endif
+
+#if AIC_DEBUG_REGISTERS
+ahd_reg_print_t ahd_clrseqintstat_print;
+#else
+#define ahd_clrseqintstat_print(regvalue, cur_col, wrap) \
+ ahd_print_register(NULL, 0, "CLRSEQINTSTAT", 0x0c, regvalue, cur_col, wrap)
+#endif
+
+#if AIC_DEBUG_REGISTERS
+ahd_reg_print_t ahd_swtimer_print;
+#else
+#define ahd_swtimer_print(regvalue, cur_col, wrap) \
+ ahd_print_register(NULL, 0, "SWTIMER", 0x0e, regvalue, cur_col, wrap)
+#endif
+
+#if AIC_DEBUG_REGISTERS
+ahd_reg_print_t ahd_snscb_qoff_print;
+#else
+#define ahd_snscb_qoff_print(regvalue, cur_col, wrap) \
+ ahd_print_register(NULL, 0, "SNSCB_QOFF", 0x10, regvalue, cur_col, wrap)
+#endif
+
+#if AIC_DEBUG_REGISTERS
+ahd_reg_print_t ahd_sescb_qoff_print;
+#else
+#define ahd_sescb_qoff_print(regvalue, cur_col, wrap) \
+ ahd_print_register(NULL, 0, "SESCB_QOFF", 0x12, regvalue, cur_col, wrap)
+#endif
+
+#if AIC_DEBUG_REGISTERS
+ahd_reg_print_t ahd_sdscb_qoff_print;
+#else
+#define ahd_sdscb_qoff_print(regvalue, cur_col, wrap) \
+ ahd_print_register(NULL, 0, "SDSCB_QOFF", 0x14, regvalue, cur_col, wrap)
+#endif
+
+#if AIC_DEBUG_REGISTERS
+ahd_reg_print_t ahd_qoff_ctlsta_print;
+#else
+#define ahd_qoff_ctlsta_print(regvalue, cur_col, wrap) \
+ ahd_print_register(NULL, 0, "QOFF_CTLSTA", 0x16, regvalue, cur_col, wrap)
+#endif
+
+#if AIC_DEBUG_REGISTERS
+ahd_reg_print_t ahd_intctl_print;
+#else
+#define ahd_intctl_print(regvalue, cur_col, wrap) \
+ ahd_print_register(NULL, 0, "INTCTL", 0x18, regvalue, cur_col, wrap)
+#endif
+
+#if AIC_DEBUG_REGISTERS
+ahd_reg_print_t ahd_dfcntrl_print;
+#else
+#define ahd_dfcntrl_print(regvalue, cur_col, wrap) \
+ ahd_print_register(NULL, 0, "DFCNTRL", 0x19, regvalue, cur_col, wrap)
+#endif
+
+#if AIC_DEBUG_REGISTERS
+ahd_reg_print_t ahd_dscommand0_print;
+#else
+#define ahd_dscommand0_print(regvalue, cur_col, wrap) \
+ ahd_print_register(NULL, 0, "DSCOMMAND0", 0x19, regvalue, cur_col, wrap)
+#endif
+
+#if AIC_DEBUG_REGISTERS
+ahd_reg_print_t ahd_dfstatus_print;
+#else
+#define ahd_dfstatus_print(regvalue, cur_col, wrap) \
+ ahd_print_register(NULL, 0, "DFSTATUS", 0x1a, regvalue, cur_col, wrap)
+#endif
+
+#if AIC_DEBUG_REGISTERS
+ahd_reg_print_t ahd_sg_cache_shadow_print;
+#else
+#define ahd_sg_cache_shadow_print(regvalue, cur_col, wrap) \
+ ahd_print_register(NULL, 0, "SG_CACHE_SHADOW", 0x1b, regvalue, cur_col, wrap)
+#endif
+
+#if AIC_DEBUG_REGISTERS
+ahd_reg_print_t ahd_sg_cache_pre_print;
+#else
+#define ahd_sg_cache_pre_print(regvalue, cur_col, wrap) \
+ ahd_print_register(NULL, 0, "SG_CACHE_PRE", 0x1b, regvalue, cur_col, wrap)
+#endif
+
+#if AIC_DEBUG_REGISTERS
+ahd_reg_print_t ahd_arbctl_print;
+#else
+#define ahd_arbctl_print(regvalue, cur_col, wrap) \
+ ahd_print_register(NULL, 0, "ARBCTL", 0x1b, regvalue, cur_col, wrap)
+#endif
+
+#if AIC_DEBUG_REGISTERS
+ahd_reg_print_t ahd_lqin_print;
+#else
+#define ahd_lqin_print(regvalue, cur_col, wrap) \
+ ahd_print_register(NULL, 0, "LQIN", 0x20, regvalue, cur_col, wrap)
+#endif
+
+#if AIC_DEBUG_REGISTERS
+ahd_reg_print_t ahd_typeptr_print;
+#else
+#define ahd_typeptr_print(regvalue, cur_col, wrap) \
+ ahd_print_register(NULL, 0, "TYPEPTR", 0x20, regvalue, cur_col, wrap)
+#endif
+
+#if AIC_DEBUG_REGISTERS
+ahd_reg_print_t ahd_tagptr_print;
+#else
+#define ahd_tagptr_print(regvalue, cur_col, wrap) \
+ ahd_print_register(NULL, 0, "TAGPTR", 0x21, regvalue, cur_col, wrap)
+#endif
+
+#if AIC_DEBUG_REGISTERS
+ahd_reg_print_t ahd_lunptr_print;
+#else
+#define ahd_lunptr_print(regvalue, cur_col, wrap) \
+ ahd_print_register(NULL, 0, "LUNPTR", 0x22, regvalue, cur_col, wrap)
+#endif
+
+#if AIC_DEBUG_REGISTERS
+ahd_reg_print_t ahd_datalenptr_print;
+#else
+#define ahd_datalenptr_print(regvalue, cur_col, wrap) \
+ ahd_print_register(NULL, 0, "DATALENPTR", 0x23, regvalue, cur_col, wrap)
+#endif
+
+#if AIC_DEBUG_REGISTERS
+ahd_reg_print_t ahd_statlenptr_print;
+#else
+#define ahd_statlenptr_print(regvalue, cur_col, wrap) \
+ ahd_print_register(NULL, 0, "STATLENPTR", 0x24, regvalue, cur_col, wrap)
+#endif
+
+#if AIC_DEBUG_REGISTERS
+ahd_reg_print_t ahd_cmdlenptr_print;
+#else
+#define ahd_cmdlenptr_print(regvalue, cur_col, wrap) \
+ ahd_print_register(NULL, 0, "CMDLENPTR", 0x25, regvalue, cur_col, wrap)
+#endif
+
+#if AIC_DEBUG_REGISTERS
+ahd_reg_print_t ahd_attrptr_print;
+#else
+#define ahd_attrptr_print(regvalue, cur_col, wrap) \
+ ahd_print_register(NULL, 0, "ATTRPTR", 0x26, regvalue, cur_col, wrap)
+#endif
+
+#if AIC_DEBUG_REGISTERS
+ahd_reg_print_t ahd_flagptr_print;
+#else
+#define ahd_flagptr_print(regvalue, cur_col, wrap) \
+ ahd_print_register(NULL, 0, "FLAGPTR", 0x27, regvalue, cur_col, wrap)
+#endif
+
+#if AIC_DEBUG_REGISTERS
+ahd_reg_print_t ahd_cmdptr_print;
+#else
+#define ahd_cmdptr_print(regvalue, cur_col, wrap) \
+ ahd_print_register(NULL, 0, "CMDPTR", 0x28, regvalue, cur_col, wrap)
+#endif
+
+#if AIC_DEBUG_REGISTERS
+ahd_reg_print_t ahd_qnextptr_print;
+#else
+#define ahd_qnextptr_print(regvalue, cur_col, wrap) \
+ ahd_print_register(NULL, 0, "QNEXTPTR", 0x29, regvalue, cur_col, wrap)
+#endif
+
+#if AIC_DEBUG_REGISTERS
+ahd_reg_print_t ahd_idptr_print;
+#else
+#define ahd_idptr_print(regvalue, cur_col, wrap) \
+ ahd_print_register(NULL, 0, "IDPTR", 0x2a, regvalue, cur_col, wrap)
+#endif
+
+#if AIC_DEBUG_REGISTERS
+ahd_reg_print_t ahd_abrtbyteptr_print;
+#else
+#define ahd_abrtbyteptr_print(regvalue, cur_col, wrap) \
+ ahd_print_register(NULL, 0, "ABRTBYTEPTR", 0x2b, regvalue, cur_col, wrap)
+#endif
+
+#if AIC_DEBUG_REGISTERS
+ahd_reg_print_t ahd_abrtbitptr_print;
+#else
+#define ahd_abrtbitptr_print(regvalue, cur_col, wrap) \
+ ahd_print_register(NULL, 0, "ABRTBITPTR", 0x2c, regvalue, cur_col, wrap)
+#endif
+
+#if AIC_DEBUG_REGISTERS
+ahd_reg_print_t ahd_maxcmdbytes_print;
+#else
+#define ahd_maxcmdbytes_print(regvalue, cur_col, wrap) \
+ ahd_print_register(NULL, 0, "MAXCMDBYTES", 0x2d, regvalue, cur_col, wrap)
+#endif
+
+#if AIC_DEBUG_REGISTERS
+ahd_reg_print_t ahd_maxcmd2rcv_print;
+#else
+#define ahd_maxcmd2rcv_print(regvalue, cur_col, wrap) \
+ ahd_print_register(NULL, 0, "MAXCMD2RCV", 0x2e, regvalue, cur_col, wrap)
+#endif
+
+#if AIC_DEBUG_REGISTERS
+ahd_reg_print_t ahd_shortthresh_print;
+#else
+#define ahd_shortthresh_print(regvalue, cur_col, wrap) \
+ ahd_print_register(NULL, 0, "SHORTTHRESH", 0x2f, regvalue, cur_col, wrap)
+#endif
+
+#if AIC_DEBUG_REGISTERS
+ahd_reg_print_t ahd_lunlen_print;
+#else
+#define ahd_lunlen_print(regvalue, cur_col, wrap) \
+ ahd_print_register(NULL, 0, "LUNLEN", 0x30, regvalue, cur_col, wrap)
+#endif
+
+#if AIC_DEBUG_REGISTERS
+ahd_reg_print_t ahd_cdblimit_print;
+#else
+#define ahd_cdblimit_print(regvalue, cur_col, wrap) \
+ ahd_print_register(NULL, 0, "CDBLIMIT", 0x31, regvalue, cur_col, wrap)
+#endif
+
+#if AIC_DEBUG_REGISTERS
+ahd_reg_print_t ahd_maxcmd_print;
+#else
+#define ahd_maxcmd_print(regvalue, cur_col, wrap) \
+ ahd_print_register(NULL, 0, "MAXCMD", 0x32, regvalue, cur_col, wrap)
+#endif
+
+#if AIC_DEBUG_REGISTERS
+ahd_reg_print_t ahd_maxcmdcnt_print;
+#else
+#define ahd_maxcmdcnt_print(regvalue, cur_col, wrap) \
+ ahd_print_register(NULL, 0, "MAXCMDCNT", 0x33, regvalue, cur_col, wrap)
+#endif
+
+#if AIC_DEBUG_REGISTERS
+ahd_reg_print_t ahd_lqrsvd01_print;
+#else
+#define ahd_lqrsvd01_print(regvalue, cur_col, wrap) \
+ ahd_print_register(NULL, 0, "LQRSVD01", 0x34, regvalue, cur_col, wrap)
+#endif
+
+#if AIC_DEBUG_REGISTERS
+ahd_reg_print_t ahd_lqrsvd16_print;
+#else
+#define ahd_lqrsvd16_print(regvalue, cur_col, wrap) \
+ ahd_print_register(NULL, 0, "LQRSVD16", 0x35, regvalue, cur_col, wrap)
+#endif
+
+#if AIC_DEBUG_REGISTERS
+ahd_reg_print_t ahd_lqrsvd17_print;
+#else
+#define ahd_lqrsvd17_print(regvalue, cur_col, wrap) \
+ ahd_print_register(NULL, 0, "LQRSVD17", 0x36, regvalue, cur_col, wrap)
+#endif
+
+#if AIC_DEBUG_REGISTERS
+ahd_reg_print_t ahd_cmdrsvd0_print;
+#else
+#define ahd_cmdrsvd0_print(regvalue, cur_col, wrap) \
+ ahd_print_register(NULL, 0, "CMDRSVD0", 0x37, regvalue, cur_col, wrap)
+#endif
+
+#if AIC_DEBUG_REGISTERS
+ahd_reg_print_t ahd_lqctl0_print;
+#else
+#define ahd_lqctl0_print(regvalue, cur_col, wrap) \
+ ahd_print_register(NULL, 0, "LQCTL0", 0x38, regvalue, cur_col, wrap)
+#endif
+
+#if AIC_DEBUG_REGISTERS
+ahd_reg_print_t ahd_lqctl1_print;
+#else
+#define ahd_lqctl1_print(regvalue, cur_col, wrap) \
+ ahd_print_register(NULL, 0, "LQCTL1", 0x38, regvalue, cur_col, wrap)
+#endif
+
+#if AIC_DEBUG_REGISTERS
+ahd_reg_print_t ahd_lqctl2_print;
+#else
+#define ahd_lqctl2_print(regvalue, cur_col, wrap) \
+ ahd_print_register(NULL, 0, "LQCTL2", 0x39, regvalue, cur_col, wrap)
+#endif
+
+#if AIC_DEBUG_REGISTERS
+ahd_reg_print_t ahd_scsbist0_print;
+#else
+#define ahd_scsbist0_print(regvalue, cur_col, wrap) \
+ ahd_print_register(NULL, 0, "SCSBIST0", 0x39, regvalue, cur_col, wrap)
+#endif
+
+#if AIC_DEBUG_REGISTERS
+ahd_reg_print_t ahd_scsiseq0_print;
+#else
+#define ahd_scsiseq0_print(regvalue, cur_col, wrap) \
+ ahd_print_register(NULL, 0, "SCSISEQ0", 0x3a, regvalue, cur_col, wrap)
+#endif
+
+#if AIC_DEBUG_REGISTERS
+ahd_reg_print_t ahd_scsbist1_print;
+#else
+#define ahd_scsbist1_print(regvalue, cur_col, wrap) \
+ ahd_print_register(NULL, 0, "SCSBIST1", 0x3a, regvalue, cur_col, wrap)
+#endif
+
+#if AIC_DEBUG_REGISTERS
+ahd_reg_print_t ahd_scsiseq1_print;
+#else
+#define ahd_scsiseq1_print(regvalue, cur_col, wrap) \
+ ahd_print_register(NULL, 0, "SCSISEQ1", 0x3b, regvalue, cur_col, wrap)
+#endif
+
+#if AIC_DEBUG_REGISTERS
+ahd_reg_print_t ahd_businitid_print;
+#else
+#define ahd_businitid_print(regvalue, cur_col, wrap) \
+ ahd_print_register(NULL, 0, "BUSINITID", 0x3c, regvalue, cur_col, wrap)
+#endif
+
+#if AIC_DEBUG_REGISTERS
+ahd_reg_print_t ahd_sxfrctl0_print;
+#else
+#define ahd_sxfrctl0_print(regvalue, cur_col, wrap) \
+ ahd_print_register(NULL, 0, "SXFRCTL0", 0x3c, regvalue, cur_col, wrap)
+#endif
+
+#if AIC_DEBUG_REGISTERS
+ahd_reg_print_t ahd_dlcount_print;
+#else
+#define ahd_dlcount_print(regvalue, cur_col, wrap) \
+ ahd_print_register(NULL, 0, "DLCOUNT", 0x3c, regvalue, cur_col, wrap)
+#endif
+
+#if AIC_DEBUG_REGISTERS
+ahd_reg_print_t ahd_sxfrctl1_print;
+#else
+#define ahd_sxfrctl1_print(regvalue, cur_col, wrap) \
+ ahd_print_register(NULL, 0, "SXFRCTL1", 0x3d, regvalue, cur_col, wrap)
+#endif
+
+#if AIC_DEBUG_REGISTERS
+ahd_reg_print_t ahd_bustargid_print;
+#else
+#define ahd_bustargid_print(regvalue, cur_col, wrap) \
+ ahd_print_register(NULL, 0, "BUSTARGID", 0x3e, regvalue, cur_col, wrap)
+#endif
+
+#if AIC_DEBUG_REGISTERS
+ahd_reg_print_t ahd_sxfrctl2_print;
+#else
+#define ahd_sxfrctl2_print(regvalue, cur_col, wrap) \
+ ahd_print_register(NULL, 0, "SXFRCTL2", 0x3e, regvalue, cur_col, wrap)
+#endif
+
+#if AIC_DEBUG_REGISTERS
+ahd_reg_print_t ahd_dffstat_print;
+#else
+#define ahd_dffstat_print(regvalue, cur_col, wrap) \
+ ahd_print_register(NULL, 0, "DFFSTAT", 0x3f, regvalue, cur_col, wrap)
+#endif
+
+#if AIC_DEBUG_REGISTERS
+ahd_reg_print_t ahd_scsisigo_print;
+#else
+#define ahd_scsisigo_print(regvalue, cur_col, wrap) \
+ ahd_print_register(NULL, 0, "SCSISIGO", 0x40, regvalue, cur_col, wrap)
+#endif
+
+#if AIC_DEBUG_REGISTERS
+ahd_reg_print_t ahd_multargid_print;
+#else
+#define ahd_multargid_print(regvalue, cur_col, wrap) \
+ ahd_print_register(NULL, 0, "MULTARGID", 0x40, regvalue, cur_col, wrap)
+#endif
+
+#if AIC_DEBUG_REGISTERS
+ahd_reg_print_t ahd_scsisigi_print;
+#else
+#define ahd_scsisigi_print(regvalue, cur_col, wrap) \
+ ahd_print_register(NULL, 0, "SCSISIGI", 0x41, regvalue, cur_col, wrap)
+#endif
+
+#if AIC_DEBUG_REGISTERS
+ahd_reg_print_t ahd_scsiphase_print;
+#else
+#define ahd_scsiphase_print(regvalue, cur_col, wrap) \
+ ahd_print_register(NULL, 0, "SCSIPHASE", 0x42, regvalue, cur_col, wrap)
+#endif
+
+#if AIC_DEBUG_REGISTERS
+ahd_reg_print_t ahd_scsidat0_img_print;
+#else
+#define ahd_scsidat0_img_print(regvalue, cur_col, wrap) \
+ ahd_print_register(NULL, 0, "SCSIDAT0_IMG", 0x43, regvalue, cur_col, wrap)
+#endif
+
+#if AIC_DEBUG_REGISTERS
+ahd_reg_print_t ahd_scsidat_print;
+#else
+#define ahd_scsidat_print(regvalue, cur_col, wrap) \
+ ahd_print_register(NULL, 0, "SCSIDAT", 0x44, regvalue, cur_col, wrap)
+#endif
+
+#if AIC_DEBUG_REGISTERS
+ahd_reg_print_t ahd_scsibus_print;
+#else
+#define ahd_scsibus_print(regvalue, cur_col, wrap) \
+ ahd_print_register(NULL, 0, "SCSIBUS", 0x46, regvalue, cur_col, wrap)
+#endif
+
+#if AIC_DEBUG_REGISTERS
+ahd_reg_print_t ahd_targidin_print;
+#else
+#define ahd_targidin_print(regvalue, cur_col, wrap) \
+ ahd_print_register(NULL, 0, "TARGIDIN", 0x48, regvalue, cur_col, wrap)
+#endif
+
+#if AIC_DEBUG_REGISTERS
+ahd_reg_print_t ahd_selid_print;
+#else
+#define ahd_selid_print(regvalue, cur_col, wrap) \
+ ahd_print_register(NULL, 0, "SELID", 0x49, regvalue, cur_col, wrap)
+#endif
+
+#if AIC_DEBUG_REGISTERS
+ahd_reg_print_t ahd_optionmode_print;
+#else
+#define ahd_optionmode_print(regvalue, cur_col, wrap) \
+ ahd_print_register(NULL, 0, "OPTIONMODE", 0x4a, regvalue, cur_col, wrap)
+#endif
+
+#if AIC_DEBUG_REGISTERS
+ahd_reg_print_t ahd_sblkctl_print;
+#else
+#define ahd_sblkctl_print(regvalue, cur_col, wrap) \
+ ahd_print_register(NULL, 0, "SBLKCTL", 0x4a, regvalue, cur_col, wrap)
+#endif
+
+#if AIC_DEBUG_REGISTERS
+ahd_reg_print_t ahd_simode0_print;
+#else
+#define ahd_simode0_print(regvalue, cur_col, wrap) \
+ ahd_print_register(NULL, 0, "SIMODE0", 0x4b, regvalue, cur_col, wrap)
+#endif
+
+#if AIC_DEBUG_REGISTERS
+ahd_reg_print_t ahd_sstat0_print;
+#else
+#define ahd_sstat0_print(regvalue, cur_col, wrap) \
+ ahd_print_register(NULL, 0, "SSTAT0", 0x4b, regvalue, cur_col, wrap)
+#endif
+
+#if AIC_DEBUG_REGISTERS
+ahd_reg_print_t ahd_clrsint0_print;
+#else
+#define ahd_clrsint0_print(regvalue, cur_col, wrap) \
+ ahd_print_register(NULL, 0, "CLRSINT0", 0x4b, regvalue, cur_col, wrap)
+#endif
+
+#if AIC_DEBUG_REGISTERS
+ahd_reg_print_t ahd_sstat1_print;
+#else
+#define ahd_sstat1_print(regvalue, cur_col, wrap) \
+ ahd_print_register(NULL, 0, "SSTAT1", 0x4c, regvalue, cur_col, wrap)
+#endif
+
+#if AIC_DEBUG_REGISTERS
+ahd_reg_print_t ahd_clrsint1_print;
+#else
+#define ahd_clrsint1_print(regvalue, cur_col, wrap) \
+ ahd_print_register(NULL, 0, "CLRSINT1", 0x4c, regvalue, cur_col, wrap)
+#endif
+
+#if AIC_DEBUG_REGISTERS
+ahd_reg_print_t ahd_sstat2_print;
+#else
+#define ahd_sstat2_print(regvalue, cur_col, wrap) \
+ ahd_print_register(NULL, 0, "SSTAT2", 0x4d, regvalue, cur_col, wrap)
+#endif
+
+#if AIC_DEBUG_REGISTERS
+ahd_reg_print_t ahd_clrsint2_print;
+#else
+#define ahd_clrsint2_print(regvalue, cur_col, wrap) \
+ ahd_print_register(NULL, 0, "CLRSINT2", 0x4d, regvalue, cur_col, wrap)
+#endif
+
+#if AIC_DEBUG_REGISTERS
+ahd_reg_print_t ahd_simode2_print;
+#else
+#define ahd_simode2_print(regvalue, cur_col, wrap) \
+ ahd_print_register(NULL, 0, "SIMODE2", 0x4d, regvalue, cur_col, wrap)
+#endif
+
+#if AIC_DEBUG_REGISTERS
+ahd_reg_print_t ahd_perrdiag_print;
+#else
+#define ahd_perrdiag_print(regvalue, cur_col, wrap) \
+ ahd_print_register(NULL, 0, "PERRDIAG", 0x4e, regvalue, cur_col, wrap)
+#endif
+
+#if AIC_DEBUG_REGISTERS
+ahd_reg_print_t ahd_lqistate_print;
+#else
+#define ahd_lqistate_print(regvalue, cur_col, wrap) \
+ ahd_print_register(NULL, 0, "LQISTATE", 0x4e, regvalue, cur_col, wrap)
+#endif
+
+#if AIC_DEBUG_REGISTERS
+ahd_reg_print_t ahd_soffcnt_print;
+#else
+#define ahd_soffcnt_print(regvalue, cur_col, wrap) \
+ ahd_print_register(NULL, 0, "SOFFCNT", 0x4f, regvalue, cur_col, wrap)
+#endif
+
+#if AIC_DEBUG_REGISTERS
+ahd_reg_print_t ahd_lqostate_print;
+#else
+#define ahd_lqostate_print(regvalue, cur_col, wrap) \
+ ahd_print_register(NULL, 0, "LQOSTATE", 0x4f, regvalue, cur_col, wrap)
+#endif
+
+#if AIC_DEBUG_REGISTERS
+ahd_reg_print_t ahd_lqistat0_print;
+#else
+#define ahd_lqistat0_print(regvalue, cur_col, wrap) \
+ ahd_print_register(NULL, 0, "LQISTAT0", 0x50, regvalue, cur_col, wrap)
+#endif
+
+#if AIC_DEBUG_REGISTERS
+ahd_reg_print_t ahd_clrlqiint0_print;
+#else
+#define ahd_clrlqiint0_print(regvalue, cur_col, wrap) \
+ ahd_print_register(NULL, 0, "CLRLQIINT0", 0x50, regvalue, cur_col, wrap)
+#endif
+
+#if AIC_DEBUG_REGISTERS
+ahd_reg_print_t ahd_lqimode0_print;
+#else
+#define ahd_lqimode0_print(regvalue, cur_col, wrap) \
+ ahd_print_register(NULL, 0, "LQIMODE0", 0x50, regvalue, cur_col, wrap)
+#endif
+
+#if AIC_DEBUG_REGISTERS
+ahd_reg_print_t ahd_lqistat1_print;
+#else
+#define ahd_lqistat1_print(regvalue, cur_col, wrap) \
+ ahd_print_register(NULL, 0, "LQISTAT1", 0x51, regvalue, cur_col, wrap)
+#endif
+
+#if AIC_DEBUG_REGISTERS
+ahd_reg_print_t ahd_clrlqiint1_print;
+#else
+#define ahd_clrlqiint1_print(regvalue, cur_col, wrap) \
+ ahd_print_register(NULL, 0, "CLRLQIINT1", 0x51, regvalue, cur_col, wrap)
+#endif
+
+#if AIC_DEBUG_REGISTERS
+ahd_reg_print_t ahd_lqimode1_print;
+#else
+#define ahd_lqimode1_print(regvalue, cur_col, wrap) \
+ ahd_print_register(NULL, 0, "LQIMODE1", 0x51, regvalue, cur_col, wrap)
+#endif
+
+#if AIC_DEBUG_REGISTERS
+ahd_reg_print_t ahd_lqistat2_print;
+#else
+#define ahd_lqistat2_print(regvalue, cur_col, wrap) \
+ ahd_print_register(NULL, 0, "LQISTAT2", 0x52, regvalue, cur_col, wrap)
+#endif
+
+#if AIC_DEBUG_REGISTERS
+ahd_reg_print_t ahd_sstat3_print;
+#else
+#define ahd_sstat3_print(regvalue, cur_col, wrap) \
+ ahd_print_register(NULL, 0, "SSTAT3", 0x53, regvalue, cur_col, wrap)
+#endif
+
+#if AIC_DEBUG_REGISTERS
+ahd_reg_print_t ahd_clrsint3_print;
+#else
+#define ahd_clrsint3_print(regvalue, cur_col, wrap) \
+ ahd_print_register(NULL, 0, "CLRSINT3", 0x53, regvalue, cur_col, wrap)
+#endif
+
+#if AIC_DEBUG_REGISTERS
+ahd_reg_print_t ahd_simode3_print;
+#else
+#define ahd_simode3_print(regvalue, cur_col, wrap) \
+ ahd_print_register(NULL, 0, "SIMODE3", 0x53, regvalue, cur_col, wrap)
+#endif
+
+#if AIC_DEBUG_REGISTERS
+ahd_reg_print_t ahd_lqomode0_print;
+#else
+#define ahd_lqomode0_print(regvalue, cur_col, wrap) \
+ ahd_print_register(NULL, 0, "LQOMODE0", 0x54, regvalue, cur_col, wrap)
+#endif
+
+#if AIC_DEBUG_REGISTERS
+ahd_reg_print_t ahd_lqostat0_print;
+#else
+#define ahd_lqostat0_print(regvalue, cur_col, wrap) \
+ ahd_print_register(NULL, 0, "LQOSTAT0", 0x54, regvalue, cur_col, wrap)
+#endif
+
+#if AIC_DEBUG_REGISTERS
+ahd_reg_print_t ahd_clrlqoint0_print;
+#else
+#define ahd_clrlqoint0_print(regvalue, cur_col, wrap) \
+ ahd_print_register(NULL, 0, "CLRLQOINT0", 0x54, regvalue, cur_col, wrap)
+#endif
+
+#if AIC_DEBUG_REGISTERS
+ahd_reg_print_t ahd_lqomode1_print;
+#else
+#define ahd_lqomode1_print(regvalue, cur_col, wrap) \
+ ahd_print_register(NULL, 0, "LQOMODE1", 0x55, regvalue, cur_col, wrap)
+#endif
+
+#if AIC_DEBUG_REGISTERS
+ahd_reg_print_t ahd_lqostat1_print;
+#else
+#define ahd_lqostat1_print(regvalue, cur_col, wrap) \
+ ahd_print_register(NULL, 0, "LQOSTAT1", 0x55, regvalue, cur_col, wrap)
+#endif
+
+#if AIC_DEBUG_REGISTERS
+ahd_reg_print_t ahd_clrlqoint1_print;
+#else
+#define ahd_clrlqoint1_print(regvalue, cur_col, wrap) \
+ ahd_print_register(NULL, 0, "CLRLQOINT1", 0x55, regvalue, cur_col, wrap)
+#endif
+
+#if AIC_DEBUG_REGISTERS
+ahd_reg_print_t ahd_os_space_cnt_print;
+#else
+#define ahd_os_space_cnt_print(regvalue, cur_col, wrap) \
+ ahd_print_register(NULL, 0, "OS_SPACE_CNT", 0x56, regvalue, cur_col, wrap)
+#endif
+
+#if AIC_DEBUG_REGISTERS
+ahd_reg_print_t ahd_lqostat2_print;
+#else
+#define ahd_lqostat2_print(regvalue, cur_col, wrap) \
+ ahd_print_register(NULL, 0, "LQOSTAT2", 0x56, regvalue, cur_col, wrap)
+#endif
+
+#if AIC_DEBUG_REGISTERS
+ahd_reg_print_t ahd_simode1_print;
+#else
+#define ahd_simode1_print(regvalue, cur_col, wrap) \
+ ahd_print_register(NULL, 0, "SIMODE1", 0x57, regvalue, cur_col, wrap)
+#endif
+
+#if AIC_DEBUG_REGISTERS
+ahd_reg_print_t ahd_gsfifo_print;
+#else
+#define ahd_gsfifo_print(regvalue, cur_col, wrap) \
+ ahd_print_register(NULL, 0, "GSFIFO", 0x58, regvalue, cur_col, wrap)
+#endif
+
+#if AIC_DEBUG_REGISTERS
+ahd_reg_print_t ahd_dffsxfrctl_print;
+#else
+#define ahd_dffsxfrctl_print(regvalue, cur_col, wrap) \
+ ahd_print_register(NULL, 0, "DFFSXFRCTL", 0x5a, regvalue, cur_col, wrap)
+#endif
+
+#if AIC_DEBUG_REGISTERS
+ahd_reg_print_t ahd_nextscb_print;
+#else
+#define ahd_nextscb_print(regvalue, cur_col, wrap) \
+ ahd_print_register(NULL, 0, "NEXTSCB", 0x5a, regvalue, cur_col, wrap)
+#endif
+
+#if AIC_DEBUG_REGISTERS
+ahd_reg_print_t ahd_lqoscsctl_print;
+#else
+#define ahd_lqoscsctl_print(regvalue, cur_col, wrap) \
+ ahd_print_register(NULL, 0, "LQOSCSCTL", 0x5a, regvalue, cur_col, wrap)
+#endif
+
+#if AIC_DEBUG_REGISTERS
+ahd_reg_print_t ahd_seqintsrc_print;
+#else
+#define ahd_seqintsrc_print(regvalue, cur_col, wrap) \
+ ahd_print_register(NULL, 0, "SEQINTSRC", 0x5b, regvalue, cur_col, wrap)
+#endif
+
+#if AIC_DEBUG_REGISTERS
+ahd_reg_print_t ahd_clrseqintsrc_print;
+#else
+#define ahd_clrseqintsrc_print(regvalue, cur_col, wrap) \
+ ahd_print_register(NULL, 0, "CLRSEQINTSRC", 0x5b, regvalue, cur_col, wrap)
+#endif
+
+#if AIC_DEBUG_REGISTERS
+ahd_reg_print_t ahd_currscb_print;
+#else
+#define ahd_currscb_print(regvalue, cur_col, wrap) \
+ ahd_print_register(NULL, 0, "CURRSCB", 0x5c, regvalue, cur_col, wrap)
+#endif
+
+#if AIC_DEBUG_REGISTERS
+ahd_reg_print_t ahd_seqimode_print;
+#else
+#define ahd_seqimode_print(regvalue, cur_col, wrap) \
+ ahd_print_register(NULL, 0, "SEQIMODE", 0x5c, regvalue, cur_col, wrap)
+#endif
+
+#if AIC_DEBUG_REGISTERS
+ahd_reg_print_t ahd_mdffstat_print;
+#else
+#define ahd_mdffstat_print(regvalue, cur_col, wrap) \
+ ahd_print_register(NULL, 0, "MDFFSTAT", 0x5d, regvalue, cur_col, wrap)
+#endif
+
+#if AIC_DEBUG_REGISTERS
+ahd_reg_print_t ahd_crccontrol_print;
+#else
+#define ahd_crccontrol_print(regvalue, cur_col, wrap) \
+ ahd_print_register(NULL, 0, "CRCCONTROL", 0x5d, regvalue, cur_col, wrap)
+#endif
+
+#if AIC_DEBUG_REGISTERS
+ahd_reg_print_t ahd_scsitest_print;
+#else
+#define ahd_scsitest_print(regvalue, cur_col, wrap) \
+ ahd_print_register(NULL, 0, "SCSITEST", 0x5e, regvalue, cur_col, wrap)
+#endif
+
+#if AIC_DEBUG_REGISTERS
+ahd_reg_print_t ahd_dfftag_print;
+#else
+#define ahd_dfftag_print(regvalue, cur_col, wrap) \
+ ahd_print_register(NULL, 0, "DFFTAG", 0x5e, regvalue, cur_col, wrap)
+#endif
+
+#if AIC_DEBUG_REGISTERS
+ahd_reg_print_t ahd_lastscb_print;
+#else
+#define ahd_lastscb_print(regvalue, cur_col, wrap) \
+ ahd_print_register(NULL, 0, "LASTSCB", 0x5e, regvalue, cur_col, wrap)
+#endif
+
+#if AIC_DEBUG_REGISTERS
+ahd_reg_print_t ahd_iopdnctl_print;
+#else
+#define ahd_iopdnctl_print(regvalue, cur_col, wrap) \
+ ahd_print_register(NULL, 0, "IOPDNCTL", 0x5f, regvalue, cur_col, wrap)
+#endif
+
+#if AIC_DEBUG_REGISTERS
+ahd_reg_print_t ahd_negoaddr_print;
+#else
+#define ahd_negoaddr_print(regvalue, cur_col, wrap) \
+ ahd_print_register(NULL, 0, "NEGOADDR", 0x60, regvalue, cur_col, wrap)
+#endif
+
+#if AIC_DEBUG_REGISTERS
+ahd_reg_print_t ahd_shaddr_print;
+#else
+#define ahd_shaddr_print(regvalue, cur_col, wrap) \
+ ahd_print_register(NULL, 0, "SHADDR", 0x60, regvalue, cur_col, wrap)
+#endif
+
+#if AIC_DEBUG_REGISTERS
+ahd_reg_print_t ahd_dgrpcrci_print;
+#else
+#define ahd_dgrpcrci_print(regvalue, cur_col, wrap) \
+ ahd_print_register(NULL, 0, "DGRPCRCI", 0x60, regvalue, cur_col, wrap)
+#endif
+
+#if AIC_DEBUG_REGISTERS
+ahd_reg_print_t ahd_negperiod_print;
+#else
+#define ahd_negperiod_print(regvalue, cur_col, wrap) \
+ ahd_print_register(NULL, 0, "NEGPERIOD", 0x61, regvalue, cur_col, wrap)
+#endif
+
+#if AIC_DEBUG_REGISTERS
+ahd_reg_print_t ahd_packcrci_print;
+#else
+#define ahd_packcrci_print(regvalue, cur_col, wrap) \
+ ahd_print_register(NULL, 0, "PACKCRCI", 0x62, regvalue, cur_col, wrap)
+#endif
+
+#if AIC_DEBUG_REGISTERS
+ahd_reg_print_t ahd_negoffset_print;
+#else
+#define ahd_negoffset_print(regvalue, cur_col, wrap) \
+ ahd_print_register(NULL, 0, "NEGOFFSET", 0x62, regvalue, cur_col, wrap)
+#endif
+
+#if AIC_DEBUG_REGISTERS
+ahd_reg_print_t ahd_negppropts_print;
+#else
+#define ahd_negppropts_print(regvalue, cur_col, wrap) \
+ ahd_print_register(NULL, 0, "NEGPPROPTS", 0x63, regvalue, cur_col, wrap)
+#endif
+
+#if AIC_DEBUG_REGISTERS
+ahd_reg_print_t ahd_negconopts_print;
+#else
+#define ahd_negconopts_print(regvalue, cur_col, wrap) \
+ ahd_print_register(NULL, 0, "NEGCONOPTS", 0x64, regvalue, cur_col, wrap)
+#endif
+
+#if AIC_DEBUG_REGISTERS
+ahd_reg_print_t ahd_annexcol_print;
+#else
+#define ahd_annexcol_print(regvalue, cur_col, wrap) \
+ ahd_print_register(NULL, 0, "ANNEXCOL", 0x65, regvalue, cur_col, wrap)
+#endif
+
+#if AIC_DEBUG_REGISTERS
+ahd_reg_print_t ahd_annexdat_print;
+#else
+#define ahd_annexdat_print(regvalue, cur_col, wrap) \
+ ahd_print_register(NULL, 0, "ANNEXDAT", 0x66, regvalue, cur_col, wrap)
+#endif
+
+#if AIC_DEBUG_REGISTERS
+ahd_reg_print_t ahd_scschkn_print;
+#else
+#define ahd_scschkn_print(regvalue, cur_col, wrap) \
+ ahd_print_register(NULL, 0, "SCSCHKN", 0x66, regvalue, cur_col, wrap)
+#endif
+
+#if AIC_DEBUG_REGISTERS
+ahd_reg_print_t ahd_iownid_print;
+#else
+#define ahd_iownid_print(regvalue, cur_col, wrap) \
+ ahd_print_register(NULL, 0, "IOWNID", 0x67, regvalue, cur_col, wrap)
+#endif
+
+#if AIC_DEBUG_REGISTERS
+ahd_reg_print_t ahd_shcnt_print;
+#else
+#define ahd_shcnt_print(regvalue, cur_col, wrap) \
+ ahd_print_register(NULL, 0, "SHCNT", 0x68, regvalue, cur_col, wrap)
+#endif
+
+#if AIC_DEBUG_REGISTERS
+ahd_reg_print_t ahd_pll960ctl0_print;
+#else
+#define ahd_pll960ctl0_print(regvalue, cur_col, wrap) \
+ ahd_print_register(NULL, 0, "PLL960CTL0", 0x68, regvalue, cur_col, wrap)
+#endif
+
+#if AIC_DEBUG_REGISTERS
+ahd_reg_print_t ahd_pll960ctl1_print;
+#else
+#define ahd_pll960ctl1_print(regvalue, cur_col, wrap) \
+ ahd_print_register(NULL, 0, "PLL960CTL1", 0x69, regvalue, cur_col, wrap)
+#endif
+
+#if AIC_DEBUG_REGISTERS
+ahd_reg_print_t ahd_townid_print;
+#else
+#define ahd_townid_print(regvalue, cur_col, wrap) \
+ ahd_print_register(NULL, 0, "TOWNID", 0x69, regvalue, cur_col, wrap)
+#endif
+
+#if AIC_DEBUG_REGISTERS
+ahd_reg_print_t ahd_xsig_print;
+#else
+#define ahd_xsig_print(regvalue, cur_col, wrap) \
+ ahd_print_register(NULL, 0, "XSIG", 0x6a, regvalue, cur_col, wrap)
+#endif
+
+#if AIC_DEBUG_REGISTERS
+ahd_reg_print_t ahd_pll960cnt0_print;
+#else
+#define ahd_pll960cnt0_print(regvalue, cur_col, wrap) \
+ ahd_print_register(NULL, 0, "PLL960CNT0", 0x6a, regvalue, cur_col, wrap)
+#endif
+
+#if AIC_DEBUG_REGISTERS
+ahd_reg_print_t ahd_seloid_print;
+#else
+#define ahd_seloid_print(regvalue, cur_col, wrap) \
+ ahd_print_register(NULL, 0, "SELOID", 0x6b, regvalue, cur_col, wrap)
+#endif
+
+#if AIC_DEBUG_REGISTERS
+ahd_reg_print_t ahd_fairness_print;
+#else
+#define ahd_fairness_print(regvalue, cur_col, wrap) \
+ ahd_print_register(NULL, 0, "FAIRNESS", 0x6c, regvalue, cur_col, wrap)
+#endif
+
+#if AIC_DEBUG_REGISTERS
+ahd_reg_print_t ahd_pll400ctl0_print;
+#else
+#define ahd_pll400ctl0_print(regvalue, cur_col, wrap) \
+ ahd_print_register(NULL, 0, "PLL400CTL0", 0x6c, regvalue, cur_col, wrap)
+#endif
+
+#if AIC_DEBUG_REGISTERS
+ahd_reg_print_t ahd_pll400ctl1_print;
+#else
+#define ahd_pll400ctl1_print(regvalue, cur_col, wrap) \
+ ahd_print_register(NULL, 0, "PLL400CTL1", 0x6d, regvalue, cur_col, wrap)
+#endif
+
+#if AIC_DEBUG_REGISTERS
+ahd_reg_print_t ahd_pll400cnt0_print;
+#else
+#define ahd_pll400cnt0_print(regvalue, cur_col, wrap) \
+ ahd_print_register(NULL, 0, "PLL400CNT0", 0x6e, regvalue, cur_col, wrap)
+#endif
+
+#if AIC_DEBUG_REGISTERS
+ahd_reg_print_t ahd_unfairness_print;
+#else
+#define ahd_unfairness_print(regvalue, cur_col, wrap) \
+ ahd_print_register(NULL, 0, "UNFAIRNESS", 0x6e, regvalue, cur_col, wrap)
+#endif
+
+#if AIC_DEBUG_REGISTERS
+ahd_reg_print_t ahd_hodmaadr_print;
+#else
+#define ahd_hodmaadr_print(regvalue, cur_col, wrap) \
+ ahd_print_register(NULL, 0, "HODMAADR", 0x70, regvalue, cur_col, wrap)
+#endif
+
+#if AIC_DEBUG_REGISTERS
+ahd_reg_print_t ahd_haddr_print;
+#else
+#define ahd_haddr_print(regvalue, cur_col, wrap) \
+ ahd_print_register(NULL, 0, "HADDR", 0x70, regvalue, cur_col, wrap)
+#endif
+
+#if AIC_DEBUG_REGISTERS
+ahd_reg_print_t ahd_plldelay_print;
+#else
+#define ahd_plldelay_print(regvalue, cur_col, wrap) \
+ ahd_print_register(NULL, 0, "PLLDELAY", 0x70, regvalue, cur_col, wrap)
+#endif
+
+#if AIC_DEBUG_REGISTERS
+ahd_reg_print_t ahd_hcnt_print;
+#else
+#define ahd_hcnt_print(regvalue, cur_col, wrap) \
+ ahd_print_register(NULL, 0, "HCNT", 0x78, regvalue, cur_col, wrap)
+#endif
+
+#if AIC_DEBUG_REGISTERS
+ahd_reg_print_t ahd_hodmacnt_print;
+#else
+#define ahd_hodmacnt_print(regvalue, cur_col, wrap) \
+ ahd_print_register(NULL, 0, "HODMACNT", 0x78, regvalue, cur_col, wrap)
+#endif
+
+#if AIC_DEBUG_REGISTERS
+ahd_reg_print_t ahd_hodmaen_print;
+#else
+#define ahd_hodmaen_print(regvalue, cur_col, wrap) \
+ ahd_print_register(NULL, 0, "HODMAEN", 0x7a, regvalue, cur_col, wrap)
+#endif
+
+#if AIC_DEBUG_REGISTERS
+ahd_reg_print_t ahd_scbhaddr_print;
+#else
+#define ahd_scbhaddr_print(regvalue, cur_col, wrap) \
+ ahd_print_register(NULL, 0, "SCBHADDR", 0x7c, regvalue, cur_col, wrap)
+#endif
+
+#if AIC_DEBUG_REGISTERS
+ahd_reg_print_t ahd_sghaddr_print;
+#else
+#define ahd_sghaddr_print(regvalue, cur_col, wrap) \
+ ahd_print_register(NULL, 0, "SGHADDR", 0x7c, regvalue, cur_col, wrap)
+#endif
+
+#if AIC_DEBUG_REGISTERS
+ahd_reg_print_t ahd_scbhcnt_print;
+#else
+#define ahd_scbhcnt_print(regvalue, cur_col, wrap) \
+ ahd_print_register(NULL, 0, "SCBHCNT", 0x84, regvalue, cur_col, wrap)
+#endif
+
+#if AIC_DEBUG_REGISTERS
+ahd_reg_print_t ahd_sghcnt_print;
+#else
+#define ahd_sghcnt_print(regvalue, cur_col, wrap) \
+ ahd_print_register(NULL, 0, "SGHCNT", 0x84, regvalue, cur_col, wrap)
+#endif
+
+#if AIC_DEBUG_REGISTERS
+ahd_reg_print_t ahd_dff_thrsh_print;
+#else
+#define ahd_dff_thrsh_print(regvalue, cur_col, wrap) \
+ ahd_print_register(NULL, 0, "DFF_THRSH", 0x88, regvalue, cur_col, wrap)
+#endif
+
+#if AIC_DEBUG_REGISTERS
+ahd_reg_print_t ahd_romaddr_print;
+#else
+#define ahd_romaddr_print(regvalue, cur_col, wrap) \
+ ahd_print_register(NULL, 0, "ROMADDR", 0x8a, regvalue, cur_col, wrap)
+#endif
+
+#if AIC_DEBUG_REGISTERS
+ahd_reg_print_t ahd_romcntrl_print;
+#else
+#define ahd_romcntrl_print(regvalue, cur_col, wrap) \
+ ahd_print_register(NULL, 0, "ROMCNTRL", 0x8d, regvalue, cur_col, wrap)
+#endif
+
+#if AIC_DEBUG_REGISTERS
+ahd_reg_print_t ahd_romdata_print;
+#else
+#define ahd_romdata_print(regvalue, cur_col, wrap) \
+ ahd_print_register(NULL, 0, "ROMDATA", 0x8e, regvalue, cur_col, wrap)
+#endif
+
+#if AIC_DEBUG_REGISTERS
+ahd_reg_print_t ahd_dchrxmsg0_print;
+#else
+#define ahd_dchrxmsg0_print(regvalue, cur_col, wrap) \
+ ahd_print_register(NULL, 0, "DCHRXMSG0", 0x90, regvalue, cur_col, wrap)
+#endif
+
+#if AIC_DEBUG_REGISTERS
+ahd_reg_print_t ahd_ovlyrxmsg0_print;
+#else
+#define ahd_ovlyrxmsg0_print(regvalue, cur_col, wrap) \
+ ahd_print_register(NULL, 0, "OVLYRXMSG0", 0x90, regvalue, cur_col, wrap)
+#endif
+
+#if AIC_DEBUG_REGISTERS
+ahd_reg_print_t ahd_cmcrxmsg0_print;
+#else
+#define ahd_cmcrxmsg0_print(regvalue, cur_col, wrap) \
+ ahd_print_register(NULL, 0, "CMCRXMSG0", 0x90, regvalue, cur_col, wrap)
+#endif
+
+#if AIC_DEBUG_REGISTERS
+ahd_reg_print_t ahd_roenable_print;
+#else
+#define ahd_roenable_print(regvalue, cur_col, wrap) \
+ ahd_print_register(NULL, 0, "ROENABLE", 0x90, regvalue, cur_col, wrap)
+#endif
+
+#if AIC_DEBUG_REGISTERS
+ahd_reg_print_t ahd_dchrxmsg1_print;
+#else
+#define ahd_dchrxmsg1_print(regvalue, cur_col, wrap) \
+ ahd_print_register(NULL, 0, "DCHRXMSG1", 0x91, regvalue, cur_col, wrap)
+#endif
+
+#if AIC_DEBUG_REGISTERS
+ahd_reg_print_t ahd_ovlyrxmsg1_print;
+#else
+#define ahd_ovlyrxmsg1_print(regvalue, cur_col, wrap) \
+ ahd_print_register(NULL, 0, "OVLYRXMSG1", 0x91, regvalue, cur_col, wrap)
+#endif
+
+#if AIC_DEBUG_REGISTERS
+ahd_reg_print_t ahd_cmcrxmsg1_print;
+#else
+#define ahd_cmcrxmsg1_print(regvalue, cur_col, wrap) \
+ ahd_print_register(NULL, 0, "CMCRXMSG1", 0x91, regvalue, cur_col, wrap)
+#endif
+
+#if AIC_DEBUG_REGISTERS
+ahd_reg_print_t ahd_nsenable_print;
+#else
+#define ahd_nsenable_print(regvalue, cur_col, wrap) \
+ ahd_print_register(NULL, 0, "NSENABLE", 0x91, regvalue, cur_col, wrap)
+#endif
+
+#if AIC_DEBUG_REGISTERS
+ahd_reg_print_t ahd_dchrxmsg2_print;
+#else
+#define ahd_dchrxmsg2_print(regvalue, cur_col, wrap) \
+ ahd_print_register(NULL, 0, "DCHRXMSG2", 0x92, regvalue, cur_col, wrap)
+#endif
+
+#if AIC_DEBUG_REGISTERS
+ahd_reg_print_t ahd_ovlyrxmsg2_print;
+#else
+#define ahd_ovlyrxmsg2_print(regvalue, cur_col, wrap) \
+ ahd_print_register(NULL, 0, "OVLYRXMSG2", 0x92, regvalue, cur_col, wrap)
+#endif
+
+#if AIC_DEBUG_REGISTERS
+ahd_reg_print_t ahd_cmcrxmsg2_print;
+#else
+#define ahd_cmcrxmsg2_print(regvalue, cur_col, wrap) \
+ ahd_print_register(NULL, 0, "CMCRXMSG2", 0x92, regvalue, cur_col, wrap)
+#endif
+
+#if AIC_DEBUG_REGISTERS
+ahd_reg_print_t ahd_ost_print;
+#else
+#define ahd_ost_print(regvalue, cur_col, wrap) \
+ ahd_print_register(NULL, 0, "OST", 0x92, regvalue, cur_col, wrap)
+#endif
+
+#if AIC_DEBUG_REGISTERS
+ahd_reg_print_t ahd_dchrxmsg3_print;
+#else
+#define ahd_dchrxmsg3_print(regvalue, cur_col, wrap) \
+ ahd_print_register(NULL, 0, "DCHRXMSG3", 0x93, regvalue, cur_col, wrap)
+#endif
+
+#if AIC_DEBUG_REGISTERS
+ahd_reg_print_t ahd_ovlyrxmsg3_print;
+#else
+#define ahd_ovlyrxmsg3_print(regvalue, cur_col, wrap) \
+ ahd_print_register(NULL, 0, "OVLYRXMSG3", 0x93, regvalue, cur_col, wrap)
+#endif
+
+#if AIC_DEBUG_REGISTERS
+ahd_reg_print_t ahd_cmcrxmsg3_print;
+#else
+#define ahd_cmcrxmsg3_print(regvalue, cur_col, wrap) \
+ ahd_print_register(NULL, 0, "CMCRXMSG3", 0x93, regvalue, cur_col, wrap)
+#endif
+
+#if AIC_DEBUG_REGISTERS
+ahd_reg_print_t ahd_pcixctl_print;
+#else
+#define ahd_pcixctl_print(regvalue, cur_col, wrap) \
+ ahd_print_register(NULL, 0, "PCIXCTL", 0x93, regvalue, cur_col, wrap)
+#endif
+
+#if AIC_DEBUG_REGISTERS
+ahd_reg_print_t ahd_cmcseqbcnt_print;
+#else
+#define ahd_cmcseqbcnt_print(regvalue, cur_col, wrap) \
+ ahd_print_register(NULL, 0, "CMCSEQBCNT", 0x94, regvalue, cur_col, wrap)
+#endif
+
+#if AIC_DEBUG_REGISTERS
+ahd_reg_print_t ahd_dchseqbcnt_print;
+#else
+#define ahd_dchseqbcnt_print(regvalue, cur_col, wrap) \
+ ahd_print_register(NULL, 0, "DCHSEQBCNT", 0x94, regvalue, cur_col, wrap)
+#endif
+
+#if AIC_DEBUG_REGISTERS
+ahd_reg_print_t ahd_ovlyseqbcnt_print;
+#else
+#define ahd_ovlyseqbcnt_print(regvalue, cur_col, wrap) \
+ ahd_print_register(NULL, 0, "OVLYSEQBCNT", 0x94, regvalue, cur_col, wrap)
+#endif
+
+#if AIC_DEBUG_REGISTERS
+ahd_reg_print_t ahd_cmcspltstat0_print;
+#else
+#define ahd_cmcspltstat0_print(regvalue, cur_col, wrap) \
+ ahd_print_register(NULL, 0, "CMCSPLTSTAT0", 0x96, regvalue, cur_col, wrap)
+#endif
+
+#if AIC_DEBUG_REGISTERS
+ahd_reg_print_t ahd_dchspltstat0_print;
+#else
+#define ahd_dchspltstat0_print(regvalue, cur_col, wrap) \
+ ahd_print_register(NULL, 0, "DCHSPLTSTAT0", 0x96, regvalue, cur_col, wrap)
+#endif
+
+#if AIC_DEBUG_REGISTERS
+ahd_reg_print_t ahd_ovlyspltstat0_print;
+#else
+#define ahd_ovlyspltstat0_print(regvalue, cur_col, wrap) \
+ ahd_print_register(NULL, 0, "OVLYSPLTSTAT0", 0x96, regvalue, cur_col, wrap)
+#endif
+
+#if AIC_DEBUG_REGISTERS
+ahd_reg_print_t ahd_cmcspltstat1_print;
+#else
+#define ahd_cmcspltstat1_print(regvalue, cur_col, wrap) \
+ ahd_print_register(NULL, 0, "CMCSPLTSTAT1", 0x97, regvalue, cur_col, wrap)
+#endif
+
+#if AIC_DEBUG_REGISTERS
+ahd_reg_print_t ahd_dchspltstat1_print;
+#else
+#define ahd_dchspltstat1_print(regvalue, cur_col, wrap) \
+ ahd_print_register(NULL, 0, "DCHSPLTSTAT1", 0x97, regvalue, cur_col, wrap)
+#endif
+
+#if AIC_DEBUG_REGISTERS
+ahd_reg_print_t ahd_ovlyspltstat1_print;
+#else
+#define ahd_ovlyspltstat1_print(regvalue, cur_col, wrap) \
+ ahd_print_register(NULL, 0, "OVLYSPLTSTAT1", 0x97, regvalue, cur_col, wrap)
+#endif
+
+#if AIC_DEBUG_REGISTERS
+ahd_reg_print_t ahd_sgrxmsg0_print;
+#else
+#define ahd_sgrxmsg0_print(regvalue, cur_col, wrap) \
+ ahd_print_register(NULL, 0, "SGRXMSG0", 0x98, regvalue, cur_col, wrap)
+#endif
+
+#if AIC_DEBUG_REGISTERS
+ahd_reg_print_t ahd_slvspltoutadr0_print;
+#else
+#define ahd_slvspltoutadr0_print(regvalue, cur_col, wrap) \
+ ahd_print_register(NULL, 0, "SLVSPLTOUTADR0", 0x98, regvalue, cur_col, wrap)
+#endif
+
+#if AIC_DEBUG_REGISTERS
+ahd_reg_print_t ahd_sgrxmsg1_print;
+#else
+#define ahd_sgrxmsg1_print(regvalue, cur_col, wrap) \
+ ahd_print_register(NULL, 0, "SGRXMSG1", 0x99, regvalue, cur_col, wrap)
+#endif
+
+#if AIC_DEBUG_REGISTERS
+ahd_reg_print_t ahd_slvspltoutadr1_print;
+#else
+#define ahd_slvspltoutadr1_print(regvalue, cur_col, wrap) \
+ ahd_print_register(NULL, 0, "SLVSPLTOUTADR1", 0x99, regvalue, cur_col, wrap)
+#endif
+
+#if AIC_DEBUG_REGISTERS
+ahd_reg_print_t ahd_sgrxmsg2_print;
+#else
+#define ahd_sgrxmsg2_print(regvalue, cur_col, wrap) \
+ ahd_print_register(NULL, 0, "SGRXMSG2", 0x9a, regvalue, cur_col, wrap)
+#endif
+
+#if AIC_DEBUG_REGISTERS
+ahd_reg_print_t ahd_slvspltoutadr2_print;
+#else
+#define ahd_slvspltoutadr2_print(regvalue, cur_col, wrap) \
+ ahd_print_register(NULL, 0, "SLVSPLTOUTADR2", 0x9a, regvalue, cur_col, wrap)
+#endif
+
+#if AIC_DEBUG_REGISTERS
+ahd_reg_print_t ahd_sgrxmsg3_print;
+#else
+#define ahd_sgrxmsg3_print(regvalue, cur_col, wrap) \
+ ahd_print_register(NULL, 0, "SGRXMSG3", 0x9b, regvalue, cur_col, wrap)
+#endif
+
+#if AIC_DEBUG_REGISTERS
+ahd_reg_print_t ahd_slvspltoutadr3_print;
+#else
+#define ahd_slvspltoutadr3_print(regvalue, cur_col, wrap) \
+ ahd_print_register(NULL, 0, "SLVSPLTOUTADR3", 0x9b, regvalue, cur_col, wrap)
+#endif
+
+#if AIC_DEBUG_REGISTERS
+ahd_reg_print_t ahd_slvspltoutattr0_print;
+#else
+#define ahd_slvspltoutattr0_print(regvalue, cur_col, wrap) \
+ ahd_print_register(NULL, 0, "SLVSPLTOUTATTR0", 0x9c, regvalue, cur_col, wrap)
+#endif
+
+#if AIC_DEBUG_REGISTERS
+ahd_reg_print_t ahd_sgseqbcnt_print;
+#else
+#define ahd_sgseqbcnt_print(regvalue, cur_col, wrap) \
+ ahd_print_register(NULL, 0, "SGSEQBCNT", 0x9c, regvalue, cur_col, wrap)
+#endif
+
+#if AIC_DEBUG_REGISTERS
+ahd_reg_print_t ahd_slvspltoutattr1_print;
+#else
+#define ahd_slvspltoutattr1_print(regvalue, cur_col, wrap) \
+ ahd_print_register(NULL, 0, "SLVSPLTOUTATTR1", 0x9d, regvalue, cur_col, wrap)
+#endif
+
+#if AIC_DEBUG_REGISTERS
+ahd_reg_print_t ahd_slvspltoutattr2_print;
+#else
+#define ahd_slvspltoutattr2_print(regvalue, cur_col, wrap) \
+ ahd_print_register(NULL, 0, "SLVSPLTOUTATTR2", 0x9e, regvalue, cur_col, wrap)
+#endif
+
+#if AIC_DEBUG_REGISTERS
+ahd_reg_print_t ahd_sgspltstat0_print;
+#else
+#define ahd_sgspltstat0_print(regvalue, cur_col, wrap) \
+ ahd_print_register(NULL, 0, "SGSPLTSTAT0", 0x9e, regvalue, cur_col, wrap)
+#endif
+
+#if AIC_DEBUG_REGISTERS
+ahd_reg_print_t ahd_sfunct_print;
+#else
+#define ahd_sfunct_print(regvalue, cur_col, wrap) \
+ ahd_print_register(NULL, 0, "SFUNCT", 0x9f, regvalue, cur_col, wrap)
+#endif
+
+#if AIC_DEBUG_REGISTERS
+ahd_reg_print_t ahd_sgspltstat1_print;
+#else
+#define ahd_sgspltstat1_print(regvalue, cur_col, wrap) \
+ ahd_print_register(NULL, 0, "SGSPLTSTAT1", 0x9f, regvalue, cur_col, wrap)
+#endif
+
+#if AIC_DEBUG_REGISTERS
+ahd_reg_print_t ahd_df0pcistat_print;
+#else
+#define ahd_df0pcistat_print(regvalue, cur_col, wrap) \
+ ahd_print_register(NULL, 0, "DF0PCISTAT", 0xa0, regvalue, cur_col, wrap)
+#endif
+
+#if AIC_DEBUG_REGISTERS
+ahd_reg_print_t ahd_reg0_print;
+#else
+#define ahd_reg0_print(regvalue, cur_col, wrap) \
+ ahd_print_register(NULL, 0, "REG0", 0xa0, regvalue, cur_col, wrap)
+#endif
+
+#if AIC_DEBUG_REGISTERS
+ahd_reg_print_t ahd_df1pcistat_print;
+#else
+#define ahd_df1pcistat_print(regvalue, cur_col, wrap) \
+ ahd_print_register(NULL, 0, "DF1PCISTAT", 0xa1, regvalue, cur_col, wrap)
+#endif
+
+#if AIC_DEBUG_REGISTERS
+ahd_reg_print_t ahd_sgpcistat_print;
+#else
+#define ahd_sgpcistat_print(regvalue, cur_col, wrap) \
+ ahd_print_register(NULL, 0, "SGPCISTAT", 0xa2, regvalue, cur_col, wrap)
+#endif
+
+#if AIC_DEBUG_REGISTERS
+ahd_reg_print_t ahd_reg1_print;
+#else
+#define ahd_reg1_print(regvalue, cur_col, wrap) \
+ ahd_print_register(NULL, 0, "REG1", 0xa2, regvalue, cur_col, wrap)
+#endif
+
+#if AIC_DEBUG_REGISTERS
+ahd_reg_print_t ahd_cmcpcistat_print;
+#else
+#define ahd_cmcpcistat_print(regvalue, cur_col, wrap) \
+ ahd_print_register(NULL, 0, "CMCPCISTAT", 0xa3, regvalue, cur_col, wrap)
+#endif
+
+#if AIC_DEBUG_REGISTERS
+ahd_reg_print_t ahd_ovlypcistat_print;
+#else
+#define ahd_ovlypcistat_print(regvalue, cur_col, wrap) \
+ ahd_print_register(NULL, 0, "OVLYPCISTAT", 0xa4, regvalue, cur_col, wrap)
+#endif
+
+#if AIC_DEBUG_REGISTERS
+ahd_reg_print_t ahd_reg_isr_print;
+#else
+#define ahd_reg_isr_print(regvalue, cur_col, wrap) \
+ ahd_print_register(NULL, 0, "REG_ISR", 0xa4, regvalue, cur_col, wrap)
+#endif
+
+#if AIC_DEBUG_REGISTERS
+ahd_reg_print_t ahd_msipcistat_print;
+#else
+#define ahd_msipcistat_print(regvalue, cur_col, wrap) \
+ ahd_print_register(NULL, 0, "MSIPCISTAT", 0xa6, regvalue, cur_col, wrap)
+#endif
+
+#if AIC_DEBUG_REGISTERS
+ahd_reg_print_t ahd_sg_state_print;
+#else
+#define ahd_sg_state_print(regvalue, cur_col, wrap) \
+ ahd_print_register(NULL, 0, "SG_STATE", 0xa6, regvalue, cur_col, wrap)
+#endif
+
+#if AIC_DEBUG_REGISTERS
+ahd_reg_print_t ahd_targpcistat_print;
+#else
+#define ahd_targpcistat_print(regvalue, cur_col, wrap) \
+ ahd_print_register(NULL, 0, "TARGPCISTAT", 0xa7, regvalue, cur_col, wrap)
+#endif
+
+#if AIC_DEBUG_REGISTERS
+ahd_reg_print_t ahd_data_count_odd_print;
+#else
+#define ahd_data_count_odd_print(regvalue, cur_col, wrap) \
+ ahd_print_register(NULL, 0, "DATA_COUNT_ODD", 0xa7, regvalue, cur_col, wrap)
+#endif
+
+#if AIC_DEBUG_REGISTERS
+ahd_reg_print_t ahd_scbptr_print;
+#else
+#define ahd_scbptr_print(regvalue, cur_col, wrap) \
+ ahd_print_register(NULL, 0, "SCBPTR", 0xa8, regvalue, cur_col, wrap)
+#endif
+
+#if AIC_DEBUG_REGISTERS
+ahd_reg_print_t ahd_ccscbacnt_print;
+#else
+#define ahd_ccscbacnt_print(regvalue, cur_col, wrap) \
+ ahd_print_register(NULL, 0, "CCSCBACNT", 0xab, regvalue, cur_col, wrap)
+#endif
+
+#if AIC_DEBUG_REGISTERS
+ahd_reg_print_t ahd_scbautoptr_print;
+#else
+#define ahd_scbautoptr_print(regvalue, cur_col, wrap) \
+ ahd_print_register(NULL, 0, "SCBAUTOPTR", 0xab, regvalue, cur_col, wrap)
+#endif
+
+#if AIC_DEBUG_REGISTERS
+ahd_reg_print_t ahd_ccscbadr_bk_print;
+#else
+#define ahd_ccscbadr_bk_print(regvalue, cur_col, wrap) \
+ ahd_print_register(NULL, 0, "CCSCBADR_BK", 0xac, regvalue, cur_col, wrap)
+#endif
+
+#if AIC_DEBUG_REGISTERS
+ahd_reg_print_t ahd_ccsgaddr_print;
+#else
+#define ahd_ccsgaddr_print(regvalue, cur_col, wrap) \
+ ahd_print_register(NULL, 0, "CCSGADDR", 0xac, regvalue, cur_col, wrap)
+#endif
+
+#if AIC_DEBUG_REGISTERS
+ahd_reg_print_t ahd_ccscbaddr_print;
+#else
+#define ahd_ccscbaddr_print(regvalue, cur_col, wrap) \
+ ahd_print_register(NULL, 0, "CCSCBADDR", 0xac, regvalue, cur_col, wrap)
+#endif
+
+#if AIC_DEBUG_REGISTERS
+ahd_reg_print_t ahd_ccscbctl_print;
+#else
+#define ahd_ccscbctl_print(regvalue, cur_col, wrap) \
+ ahd_print_register(NULL, 0, "CCSCBCTL", 0xad, regvalue, cur_col, wrap)
+#endif
+
+#if AIC_DEBUG_REGISTERS
+ahd_reg_print_t ahd_ccsgctl_print;
+#else
+#define ahd_ccsgctl_print(regvalue, cur_col, wrap) \
+ ahd_print_register(NULL, 0, "CCSGCTL", 0xad, regvalue, cur_col, wrap)
+#endif
+
+#if AIC_DEBUG_REGISTERS
+ahd_reg_print_t ahd_cmc_rambist_print;
+#else
+#define ahd_cmc_rambist_print(regvalue, cur_col, wrap) \
+ ahd_print_register(NULL, 0, "CMC_RAMBIST", 0xad, regvalue, cur_col, wrap)
+#endif
+
+#if AIC_DEBUG_REGISTERS
+ahd_reg_print_t ahd_ccsgram_print;
+#else
+#define ahd_ccsgram_print(regvalue, cur_col, wrap) \
+ ahd_print_register(NULL, 0, "CCSGRAM", 0xb0, regvalue, cur_col, wrap)
+#endif
+
+#if AIC_DEBUG_REGISTERS
+ahd_reg_print_t ahd_ccscbram_print;
+#else
+#define ahd_ccscbram_print(regvalue, cur_col, wrap) \
+ ahd_print_register(NULL, 0, "CCSCBRAM", 0xb0, regvalue, cur_col, wrap)
+#endif
+
+#if AIC_DEBUG_REGISTERS
+ahd_reg_print_t ahd_flexadr_print;
+#else
+#define ahd_flexadr_print(regvalue, cur_col, wrap) \
+ ahd_print_register(NULL, 0, "FLEXADR", 0xb0, regvalue, cur_col, wrap)
+#endif
+
+#if AIC_DEBUG_REGISTERS
+ahd_reg_print_t ahd_flexcnt_print;
+#else
+#define ahd_flexcnt_print(regvalue, cur_col, wrap) \
+ ahd_print_register(NULL, 0, "FLEXCNT", 0xb3, regvalue, cur_col, wrap)
+#endif
+
+#if AIC_DEBUG_REGISTERS
+ahd_reg_print_t ahd_flexdmastat_print;
+#else
+#define ahd_flexdmastat_print(regvalue, cur_col, wrap) \
+ ahd_print_register(NULL, 0, "FLEXDMASTAT", 0xb5, regvalue, cur_col, wrap)
+#endif
+
+#if AIC_DEBUG_REGISTERS
+ahd_reg_print_t ahd_flexdata_print;
+#else
+#define ahd_flexdata_print(regvalue, cur_col, wrap) \
+ ahd_print_register(NULL, 0, "FLEXDATA", 0xb6, regvalue, cur_col, wrap)
+#endif
+
+#if AIC_DEBUG_REGISTERS
+ahd_reg_print_t ahd_brddat_print;
+#else
+#define ahd_brddat_print(regvalue, cur_col, wrap) \
+ ahd_print_register(NULL, 0, "BRDDAT", 0xb8, regvalue, cur_col, wrap)
+#endif
+
+#if AIC_DEBUG_REGISTERS
+ahd_reg_print_t ahd_brdctl_print;
+#else
+#define ahd_brdctl_print(regvalue, cur_col, wrap) \
+ ahd_print_register(NULL, 0, "BRDCTL", 0xb9, regvalue, cur_col, wrap)
+#endif
+
+#if AIC_DEBUG_REGISTERS
+ahd_reg_print_t ahd_seeadr_print;
+#else
+#define ahd_seeadr_print(regvalue, cur_col, wrap) \
+ ahd_print_register(NULL, 0, "SEEADR", 0xba, regvalue, cur_col, wrap)
+#endif
+
+#if AIC_DEBUG_REGISTERS
+ahd_reg_print_t ahd_seedat_print;
+#else
+#define ahd_seedat_print(regvalue, cur_col, wrap) \
+ ahd_print_register(NULL, 0, "SEEDAT", 0xbc, regvalue, cur_col, wrap)
+#endif
+
+#if AIC_DEBUG_REGISTERS
+ahd_reg_print_t ahd_seectl_print;
+#else
+#define ahd_seectl_print(regvalue, cur_col, wrap) \
+ ahd_print_register(NULL, 0, "SEECTL", 0xbe, regvalue, cur_col, wrap)
+#endif
+
+#if AIC_DEBUG_REGISTERS
+ahd_reg_print_t ahd_seestat_print;
+#else
+#define ahd_seestat_print(regvalue, cur_col, wrap) \
+ ahd_print_register(NULL, 0, "SEESTAT", 0xbe, regvalue, cur_col, wrap)
+#endif
+
+#if AIC_DEBUG_REGISTERS
+ahd_reg_print_t ahd_scbcnt_print;
+#else
+#define ahd_scbcnt_print(regvalue, cur_col, wrap) \
+ ahd_print_register(NULL, 0, "SCBCNT", 0xbf, regvalue, cur_col, wrap)
+#endif
+
+#if AIC_DEBUG_REGISTERS
+ahd_reg_print_t ahd_dspfltrctl_print;
+#else
+#define ahd_dspfltrctl_print(regvalue, cur_col, wrap) \
+ ahd_print_register(NULL, 0, "DSPFLTRCTL", 0xc0, regvalue, cur_col, wrap)
+#endif
+
+#if AIC_DEBUG_REGISTERS
+ahd_reg_print_t ahd_dfwaddr_print;
+#else
+#define ahd_dfwaddr_print(regvalue, cur_col, wrap) \
+ ahd_print_register(NULL, 0, "DFWADDR", 0xc0, regvalue, cur_col, wrap)
+#endif
+
+#if AIC_DEBUG_REGISTERS
+ahd_reg_print_t ahd_dspdatactl_print;
+#else
+#define ahd_dspdatactl_print(regvalue, cur_col, wrap) \
+ ahd_print_register(NULL, 0, "DSPDATACTL", 0xc1, regvalue, cur_col, wrap)
+#endif
+
+#if AIC_DEBUG_REGISTERS
+ahd_reg_print_t ahd_dspreqctl_print;
+#else
+#define ahd_dspreqctl_print(regvalue, cur_col, wrap) \
+ ahd_print_register(NULL, 0, "DSPREQCTL", 0xc2, regvalue, cur_col, wrap)
+#endif
+
+#if AIC_DEBUG_REGISTERS
+ahd_reg_print_t ahd_dfraddr_print;
+#else
+#define ahd_dfraddr_print(regvalue, cur_col, wrap) \
+ ahd_print_register(NULL, 0, "DFRADDR", 0xc2, regvalue, cur_col, wrap)
+#endif
+
+#if AIC_DEBUG_REGISTERS
+ahd_reg_print_t ahd_dspackctl_print;
+#else
+#define ahd_dspackctl_print(regvalue, cur_col, wrap) \
+ ahd_print_register(NULL, 0, "DSPACKCTL", 0xc3, regvalue, cur_col, wrap)
+#endif
+
+#if AIC_DEBUG_REGISTERS
+ahd_reg_print_t ahd_dfdat_print;
+#else
+#define ahd_dfdat_print(regvalue, cur_col, wrap) \
+ ahd_print_register(NULL, 0, "DFDAT", 0xc4, regvalue, cur_col, wrap)
+#endif
+
+#if AIC_DEBUG_REGISTERS
+ahd_reg_print_t ahd_dspselect_print;
+#else
+#define ahd_dspselect_print(regvalue, cur_col, wrap) \
+ ahd_print_register(NULL, 0, "DSPSELECT", 0xc4, regvalue, cur_col, wrap)
+#endif
+
+#if AIC_DEBUG_REGISTERS
+ahd_reg_print_t ahd_wrtbiasctl_print;
+#else
+#define ahd_wrtbiasctl_print(regvalue, cur_col, wrap) \
+ ahd_print_register(NULL, 0, "WRTBIASCTL", 0xc5, regvalue, cur_col, wrap)
+#endif
+
+#if AIC_DEBUG_REGISTERS
+ahd_reg_print_t ahd_rcvrbiosctl_print;
+#else
+#define ahd_rcvrbiosctl_print(regvalue, cur_col, wrap) \
+ ahd_print_register(NULL, 0, "RCVRBIOSCTL", 0xc6, regvalue, cur_col, wrap)
+#endif
+
+#if AIC_DEBUG_REGISTERS
+ahd_reg_print_t ahd_wrtbiascalc_print;
+#else
+#define ahd_wrtbiascalc_print(regvalue, cur_col, wrap) \
+ ahd_print_register(NULL, 0, "WRTBIASCALC", 0xc7, regvalue, cur_col, wrap)
+#endif
+
+#if AIC_DEBUG_REGISTERS
+ahd_reg_print_t ahd_dfptrs_print;
+#else
+#define ahd_dfptrs_print(regvalue, cur_col, wrap) \
+ ahd_print_register(NULL, 0, "DFPTRS", 0xc8, regvalue, cur_col, wrap)
+#endif
+
+#if AIC_DEBUG_REGISTERS
+ahd_reg_print_t ahd_rcvrbiascalc_print;
+#else
+#define ahd_rcvrbiascalc_print(regvalue, cur_col, wrap) \
+ ahd_print_register(NULL, 0, "RCVRBIASCALC", 0xc8, regvalue, cur_col, wrap)
+#endif
+
+#if AIC_DEBUG_REGISTERS
+ahd_reg_print_t ahd_dfbkptr_print;
+#else
+#define ahd_dfbkptr_print(regvalue, cur_col, wrap) \
+ ahd_print_register(NULL, 0, "DFBKPTR", 0xc9, regvalue, cur_col, wrap)
+#endif
+
+#if AIC_DEBUG_REGISTERS
+ahd_reg_print_t ahd_skewcalc_print;
+#else
+#define ahd_skewcalc_print(regvalue, cur_col, wrap) \
+ ahd_print_register(NULL, 0, "SKEWCALC", 0xc9, regvalue, cur_col, wrap)
+#endif
+
+#if AIC_DEBUG_REGISTERS
+ahd_reg_print_t ahd_dfdbctl_print;
+#else
+#define ahd_dfdbctl_print(regvalue, cur_col, wrap) \
+ ahd_print_register(NULL, 0, "DFDBCTL", 0xcb, regvalue, cur_col, wrap)
+#endif
+
+#if AIC_DEBUG_REGISTERS
+ahd_reg_print_t ahd_dfscnt_print;
+#else
+#define ahd_dfscnt_print(regvalue, cur_col, wrap) \
+ ahd_print_register(NULL, 0, "DFSCNT", 0xcc, regvalue, cur_col, wrap)
+#endif
+
+#if AIC_DEBUG_REGISTERS
+ahd_reg_print_t ahd_dfbcnt_print;
+#else
+#define ahd_dfbcnt_print(regvalue, cur_col, wrap) \
+ ahd_print_register(NULL, 0, "DFBCNT", 0xce, regvalue, cur_col, wrap)
+#endif
+
+#if AIC_DEBUG_REGISTERS
+ahd_reg_print_t ahd_ovlyaddr_print;
+#else
+#define ahd_ovlyaddr_print(regvalue, cur_col, wrap) \
+ ahd_print_register(NULL, 0, "OVLYADDR", 0xd4, regvalue, cur_col, wrap)
+#endif
+
+#if AIC_DEBUG_REGISTERS
+ahd_reg_print_t ahd_seqctl0_print;
+#else
+#define ahd_seqctl0_print(regvalue, cur_col, wrap) \
+ ahd_print_register(NULL, 0, "SEQCTL0", 0xd6, regvalue, cur_col, wrap)
+#endif
+
+#if AIC_DEBUG_REGISTERS
+ahd_reg_print_t ahd_seqctl1_print;
+#else
+#define ahd_seqctl1_print(regvalue, cur_col, wrap) \
+ ahd_print_register(NULL, 0, "SEQCTL1", 0xd7, regvalue, cur_col, wrap)
+#endif
+
+#if AIC_DEBUG_REGISTERS
+ahd_reg_print_t ahd_flags_print;
+#else
+#define ahd_flags_print(regvalue, cur_col, wrap) \
+ ahd_print_register(NULL, 0, "FLAGS", 0xd8, regvalue, cur_col, wrap)
+#endif
+
+#if AIC_DEBUG_REGISTERS
+ahd_reg_print_t ahd_seqintctl_print;
+#else
+#define ahd_seqintctl_print(regvalue, cur_col, wrap) \
+ ahd_print_register(NULL, 0, "SEQINTCTL", 0xd9, regvalue, cur_col, wrap)
+#endif
+
+#if AIC_DEBUG_REGISTERS
+ahd_reg_print_t ahd_seqram_print;
+#else
+#define ahd_seqram_print(regvalue, cur_col, wrap) \
+ ahd_print_register(NULL, 0, "SEQRAM", 0xda, regvalue, cur_col, wrap)
+#endif
+
+#if AIC_DEBUG_REGISTERS
+ahd_reg_print_t ahd_prgmcnt_print;
+#else
+#define ahd_prgmcnt_print(regvalue, cur_col, wrap) \
+ ahd_print_register(NULL, 0, "PRGMCNT", 0xde, regvalue, cur_col, wrap)
+#endif
+
+#if AIC_DEBUG_REGISTERS
+ahd_reg_print_t ahd_accum_print;
+#else
+#define ahd_accum_print(regvalue, cur_col, wrap) \
+ ahd_print_register(NULL, 0, "ACCUM", 0xe0, regvalue, cur_col, wrap)
+#endif
+
+#if AIC_DEBUG_REGISTERS
+ahd_reg_print_t ahd_sindex_print;
+#else
+#define ahd_sindex_print(regvalue, cur_col, wrap) \
+ ahd_print_register(NULL, 0, "SINDEX", 0xe2, regvalue, cur_col, wrap)
+#endif
+
+#if AIC_DEBUG_REGISTERS
+ahd_reg_print_t ahd_dindex_print;
+#else
+#define ahd_dindex_print(regvalue, cur_col, wrap) \
+ ahd_print_register(NULL, 0, "DINDEX", 0xe4, regvalue, cur_col, wrap)
+#endif
+
+#if AIC_DEBUG_REGISTERS
+ahd_reg_print_t ahd_brkaddr1_print;
+#else
+#define ahd_brkaddr1_print(regvalue, cur_col, wrap) \
+ ahd_print_register(NULL, 0, "BRKADDR1", 0xe6, regvalue, cur_col, wrap)
+#endif
+
+#if AIC_DEBUG_REGISTERS
+ahd_reg_print_t ahd_brkaddr0_print;
+#else
+#define ahd_brkaddr0_print(regvalue, cur_col, wrap) \
+ ahd_print_register(NULL, 0, "BRKADDR0", 0xe6, regvalue, cur_col, wrap)
+#endif
+
+#if AIC_DEBUG_REGISTERS
+ahd_reg_print_t ahd_allones_print;
+#else
+#define ahd_allones_print(regvalue, cur_col, wrap) \
+ ahd_print_register(NULL, 0, "ALLONES", 0xe8, regvalue, cur_col, wrap)
+#endif
+
+#if AIC_DEBUG_REGISTERS
+ahd_reg_print_t ahd_none_print;
+#else
+#define ahd_none_print(regvalue, cur_col, wrap) \
+ ahd_print_register(NULL, 0, "NONE", 0xea, regvalue, cur_col, wrap)
+#endif
+
+#if AIC_DEBUG_REGISTERS
+ahd_reg_print_t ahd_allzeros_print;
+#else
+#define ahd_allzeros_print(regvalue, cur_col, wrap) \
+ ahd_print_register(NULL, 0, "ALLZEROS", 0xea, regvalue, cur_col, wrap)
+#endif
+
+#if AIC_DEBUG_REGISTERS
+ahd_reg_print_t ahd_sindir_print;
+#else
+#define ahd_sindir_print(regvalue, cur_col, wrap) \
+ ahd_print_register(NULL, 0, "SINDIR", 0xec, regvalue, cur_col, wrap)
+#endif
+
+#if AIC_DEBUG_REGISTERS
+ahd_reg_print_t ahd_dindir_print;
+#else
+#define ahd_dindir_print(regvalue, cur_col, wrap) \
+ ahd_print_register(NULL, 0, "DINDIR", 0xed, regvalue, cur_col, wrap)
+#endif
+
+#if AIC_DEBUG_REGISTERS
+ahd_reg_print_t ahd_function1_print;
+#else
+#define ahd_function1_print(regvalue, cur_col, wrap) \
+ ahd_print_register(NULL, 0, "FUNCTION1", 0xf0, regvalue, cur_col, wrap)
+#endif
+
+#if AIC_DEBUG_REGISTERS
+ahd_reg_print_t ahd_stack_print;
+#else
+#define ahd_stack_print(regvalue, cur_col, wrap) \
+ ahd_print_register(NULL, 0, "STACK", 0xf2, regvalue, cur_col, wrap)
+#endif
+
+#if AIC_DEBUG_REGISTERS
+ahd_reg_print_t ahd_intvec1_addr_print;
+#else
+#define ahd_intvec1_addr_print(regvalue, cur_col, wrap) \
+ ahd_print_register(NULL, 0, "INTVEC1_ADDR", 0xf4, regvalue, cur_col, wrap)
+#endif
+
+#if AIC_DEBUG_REGISTERS
+ahd_reg_print_t ahd_curaddr_print;
+#else
+#define ahd_curaddr_print(regvalue, cur_col, wrap) \
+ ahd_print_register(NULL, 0, "CURADDR", 0xf4, regvalue, cur_col, wrap)
+#endif
+
+#if AIC_DEBUG_REGISTERS
+ahd_reg_print_t ahd_intvec2_addr_print;
+#else
+#define ahd_intvec2_addr_print(regvalue, cur_col, wrap) \
+ ahd_print_register(NULL, 0, "INTVEC2_ADDR", 0xf6, regvalue, cur_col, wrap)
+#endif
+
+#if AIC_DEBUG_REGISTERS
+ahd_reg_print_t ahd_lastaddr_print;
+#else
+#define ahd_lastaddr_print(regvalue, cur_col, wrap) \
+ ahd_print_register(NULL, 0, "LASTADDR", 0xf6, regvalue, cur_col, wrap)
+#endif
+
+#if AIC_DEBUG_REGISTERS
+ahd_reg_print_t ahd_longjmp_addr_print;
+#else
+#define ahd_longjmp_addr_print(regvalue, cur_col, wrap) \
+ ahd_print_register(NULL, 0, "LONGJMP_ADDR", 0xf8, regvalue, cur_col, wrap)
+#endif
+
+#if AIC_DEBUG_REGISTERS
+ahd_reg_print_t ahd_accum_save_print;
+#else
+#define ahd_accum_save_print(regvalue, cur_col, wrap) \
+ ahd_print_register(NULL, 0, "ACCUM_SAVE", 0xfa, regvalue, cur_col, wrap)
+#endif
+
+#if AIC_DEBUG_REGISTERS
+ahd_reg_print_t ahd_sram_base_print;
+#else
+#define ahd_sram_base_print(regvalue, cur_col, wrap) \
+ ahd_print_register(NULL, 0, "SRAM_BASE", 0x100, regvalue, cur_col, wrap)
+#endif
+
+#if AIC_DEBUG_REGISTERS
+ahd_reg_print_t ahd_waiting_scb_tails_print;
+#else
+#define ahd_waiting_scb_tails_print(regvalue, cur_col, wrap) \
+ ahd_print_register(NULL, 0, "WAITING_SCB_TAILS", 0x100, regvalue, cur_col, wrap)
+#endif
+
+#if AIC_DEBUG_REGISTERS
+ahd_reg_print_t ahd_ahd_pci_config_base_print;
+#else
+#define ahd_ahd_pci_config_base_print(regvalue, cur_col, wrap) \
+ ahd_print_register(NULL, 0, "AHD_PCI_CONFIG_BASE", 0x100, regvalue, cur_col, wrap)
+#endif
+
+#if AIC_DEBUG_REGISTERS
+ahd_reg_print_t ahd_waiting_tid_head_print;
+#else
+#define ahd_waiting_tid_head_print(regvalue, cur_col, wrap) \
+ ahd_print_register(NULL, 0, "WAITING_TID_HEAD", 0x120, regvalue, cur_col, wrap)
+#endif
+
+#if AIC_DEBUG_REGISTERS
+ahd_reg_print_t ahd_waiting_tid_tail_print;
+#else
+#define ahd_waiting_tid_tail_print(regvalue, cur_col, wrap) \
+ ahd_print_register(NULL, 0, "WAITING_TID_TAIL", 0x122, regvalue, cur_col, wrap)
+#endif
+
+#if AIC_DEBUG_REGISTERS
+ahd_reg_print_t ahd_next_queued_scb_addr_print;
+#else
+#define ahd_next_queued_scb_addr_print(regvalue, cur_col, wrap) \
+ ahd_print_register(NULL, 0, "NEXT_QUEUED_SCB_ADDR", 0x124, regvalue, cur_col, wrap)
+#endif
+
+#if AIC_DEBUG_REGISTERS
+ahd_reg_print_t ahd_complete_scb_head_print;
+#else
+#define ahd_complete_scb_head_print(regvalue, cur_col, wrap) \
+ ahd_print_register(NULL, 0, "COMPLETE_SCB_HEAD", 0x128, regvalue, cur_col, wrap)
+#endif
+
+#if AIC_DEBUG_REGISTERS
+ahd_reg_print_t ahd_complete_scb_dmainprog_head_print;
+#else
+#define ahd_complete_scb_dmainprog_head_print(regvalue, cur_col, wrap) \
+ ahd_print_register(NULL, 0, "COMPLETE_SCB_DMAINPROG_HEAD", 0x12a, regvalue, cur_col, wrap)
+#endif
+
+#if AIC_DEBUG_REGISTERS
+ahd_reg_print_t ahd_complete_dma_scb_head_print;
+#else
+#define ahd_complete_dma_scb_head_print(regvalue, cur_col, wrap) \
+ ahd_print_register(NULL, 0, "COMPLETE_DMA_SCB_HEAD", 0x12c, regvalue, cur_col, wrap)
+#endif
+
+#if AIC_DEBUG_REGISTERS
+ahd_reg_print_t ahd_complete_dma_scb_tail_print;
+#else
+#define ahd_complete_dma_scb_tail_print(regvalue, cur_col, wrap) \
+ ahd_print_register(NULL, 0, "COMPLETE_DMA_SCB_TAIL", 0x12e, regvalue, cur_col, wrap)
+#endif
+
+#if AIC_DEBUG_REGISTERS
+ahd_reg_print_t ahd_complete_on_qfreeze_head_print;
+#else
+#define ahd_complete_on_qfreeze_head_print(regvalue, cur_col, wrap) \
+ ahd_print_register(NULL, 0, "COMPLETE_ON_QFREEZE_HEAD", 0x130, regvalue, cur_col, wrap)
+#endif
+
+#if AIC_DEBUG_REGISTERS
+ahd_reg_print_t ahd_qfreeze_count_print;
+#else
+#define ahd_qfreeze_count_print(regvalue, cur_col, wrap) \
+ ahd_print_register(NULL, 0, "QFREEZE_COUNT", 0x132, regvalue, cur_col, wrap)
+#endif
+
+#if AIC_DEBUG_REGISTERS
+ahd_reg_print_t ahd_kernel_qfreeze_count_print;
+#else
+#define ahd_kernel_qfreeze_count_print(regvalue, cur_col, wrap) \
+ ahd_print_register(NULL, 0, "KERNEL_QFREEZE_COUNT", 0x134, regvalue, cur_col, wrap)
+#endif
+
+#if AIC_DEBUG_REGISTERS
+ahd_reg_print_t ahd_saved_mode_print;
+#else
+#define ahd_saved_mode_print(regvalue, cur_col, wrap) \
+ ahd_print_register(NULL, 0, "SAVED_MODE", 0x136, regvalue, cur_col, wrap)
+#endif
+
+#if AIC_DEBUG_REGISTERS
+ahd_reg_print_t ahd_msg_out_print;
+#else
+#define ahd_msg_out_print(regvalue, cur_col, wrap) \
+ ahd_print_register(NULL, 0, "MSG_OUT", 0x137, regvalue, cur_col, wrap)
+#endif
+
+#if AIC_DEBUG_REGISTERS
+ahd_reg_print_t ahd_dmaparams_print;
+#else
+#define ahd_dmaparams_print(regvalue, cur_col, wrap) \
+ ahd_print_register(NULL, 0, "DMAPARAMS", 0x138, regvalue, cur_col, wrap)
+#endif
+
+#if AIC_DEBUG_REGISTERS
+ahd_reg_print_t ahd_seq_flags_print;
+#else
+#define ahd_seq_flags_print(regvalue, cur_col, wrap) \
+ ahd_print_register(NULL, 0, "SEQ_FLAGS", 0x139, regvalue, cur_col, wrap)
+#endif
+
+#if AIC_DEBUG_REGISTERS
+ahd_reg_print_t ahd_saved_scsiid_print;
+#else
+#define ahd_saved_scsiid_print(regvalue, cur_col, wrap) \
+ ahd_print_register(NULL, 0, "SAVED_SCSIID", 0x13a, regvalue, cur_col, wrap)
+#endif
+
+#if AIC_DEBUG_REGISTERS
+ahd_reg_print_t ahd_saved_lun_print;
+#else
+#define ahd_saved_lun_print(regvalue, cur_col, wrap) \
+ ahd_print_register(NULL, 0, "SAVED_LUN", 0x13b, regvalue, cur_col, wrap)
+#endif
+
+#if AIC_DEBUG_REGISTERS
+ahd_reg_print_t ahd_lastphase_print;
+#else
+#define ahd_lastphase_print(regvalue, cur_col, wrap) \
+ ahd_print_register(NULL, 0, "LASTPHASE", 0x13c, regvalue, cur_col, wrap)
+#endif
+
+#if AIC_DEBUG_REGISTERS
+ahd_reg_print_t ahd_qoutfifo_entry_valid_tag_print;
+#else
+#define ahd_qoutfifo_entry_valid_tag_print(regvalue, cur_col, wrap) \
+ ahd_print_register(NULL, 0, "QOUTFIFO_ENTRY_VALID_TAG", 0x13d, regvalue, cur_col, wrap)
+#endif
+
+#if AIC_DEBUG_REGISTERS
+ahd_reg_print_t ahd_kernel_tqinpos_print;
+#else
+#define ahd_kernel_tqinpos_print(regvalue, cur_col, wrap) \
+ ahd_print_register(NULL, 0, "KERNEL_TQINPOS", 0x13e, regvalue, cur_col, wrap)
+#endif
+
+#if AIC_DEBUG_REGISTERS
+ahd_reg_print_t ahd_tqinpos_print;
+#else
+#define ahd_tqinpos_print(regvalue, cur_col, wrap) \
+ ahd_print_register(NULL, 0, "TQINPOS", 0x13f, regvalue, cur_col, wrap)
+#endif
+
+#if AIC_DEBUG_REGISTERS
+ahd_reg_print_t ahd_shared_data_addr_print;
+#else
+#define ahd_shared_data_addr_print(regvalue, cur_col, wrap) \
+ ahd_print_register(NULL, 0, "SHARED_DATA_ADDR", 0x140, regvalue, cur_col, wrap)
+#endif
+
+#if AIC_DEBUG_REGISTERS
+ahd_reg_print_t ahd_qoutfifo_next_addr_print;
+#else
+#define ahd_qoutfifo_next_addr_print(regvalue, cur_col, wrap) \
+ ahd_print_register(NULL, 0, "QOUTFIFO_NEXT_ADDR", 0x144, regvalue, cur_col, wrap)
+#endif
+
+#if AIC_DEBUG_REGISTERS
+ahd_reg_print_t ahd_arg_1_print;
+#else
+#define ahd_arg_1_print(regvalue, cur_col, wrap) \
+ ahd_print_register(NULL, 0, "ARG_1", 0x148, regvalue, cur_col, wrap)
+#endif
+
+#if AIC_DEBUG_REGISTERS
+ahd_reg_print_t ahd_arg_2_print;
+#else
+#define ahd_arg_2_print(regvalue, cur_col, wrap) \
+ ahd_print_register(NULL, 0, "ARG_2", 0x149, regvalue, cur_col, wrap)
+#endif
+
+#if AIC_DEBUG_REGISTERS
+ahd_reg_print_t ahd_last_msg_print;
+#else
+#define ahd_last_msg_print(regvalue, cur_col, wrap) \
+ ahd_print_register(NULL, 0, "LAST_MSG", 0x14a, regvalue, cur_col, wrap)
+#endif
+
+#if AIC_DEBUG_REGISTERS
+ahd_reg_print_t ahd_scsiseq_template_print;
+#else
+#define ahd_scsiseq_template_print(regvalue, cur_col, wrap) \
+ ahd_print_register(NULL, 0, "SCSISEQ_TEMPLATE", 0x14b, regvalue, cur_col, wrap)
+#endif
+
+#if AIC_DEBUG_REGISTERS
+ahd_reg_print_t ahd_initiator_tag_print;
+#else
+#define ahd_initiator_tag_print(regvalue, cur_col, wrap) \
+ ahd_print_register(NULL, 0, "INITIATOR_TAG", 0x14c, regvalue, cur_col, wrap)
+#endif
+
+#if AIC_DEBUG_REGISTERS
+ahd_reg_print_t ahd_seq_flags2_print;
+#else
+#define ahd_seq_flags2_print(regvalue, cur_col, wrap) \
+ ahd_print_register(NULL, 0, "SEQ_FLAGS2", 0x14d, regvalue, cur_col, wrap)
+#endif
+
+#if AIC_DEBUG_REGISTERS
+ahd_reg_print_t ahd_allocfifo_scbptr_print;
+#else
+#define ahd_allocfifo_scbptr_print(regvalue, cur_col, wrap) \
+ ahd_print_register(NULL, 0, "ALLOCFIFO_SCBPTR", 0x14e, regvalue, cur_col, wrap)
+#endif
+
+#if AIC_DEBUG_REGISTERS
+ahd_reg_print_t ahd_int_coalescing_timer_print;
+#else
+#define ahd_int_coalescing_timer_print(regvalue, cur_col, wrap) \
+ ahd_print_register(NULL, 0, "INT_COALESCING_TIMER", 0x150, regvalue, cur_col, wrap)
+#endif
+
+#if AIC_DEBUG_REGISTERS
+ahd_reg_print_t ahd_int_coalescing_maxcmds_print;
+#else
+#define ahd_int_coalescing_maxcmds_print(regvalue, cur_col, wrap) \
+ ahd_print_register(NULL, 0, "INT_COALESCING_MAXCMDS", 0x152, regvalue, cur_col, wrap)
+#endif
+
+#if AIC_DEBUG_REGISTERS
+ahd_reg_print_t ahd_int_coalescing_mincmds_print;
+#else
+#define ahd_int_coalescing_mincmds_print(regvalue, cur_col, wrap) \
+ ahd_print_register(NULL, 0, "INT_COALESCING_MINCMDS", 0x153, regvalue, cur_col, wrap)
+#endif
+
+#if AIC_DEBUG_REGISTERS
+ahd_reg_print_t ahd_cmds_pending_print;
+#else
+#define ahd_cmds_pending_print(regvalue, cur_col, wrap) \
+ ahd_print_register(NULL, 0, "CMDS_PENDING", 0x154, regvalue, cur_col, wrap)
+#endif
+
+#if AIC_DEBUG_REGISTERS
+ahd_reg_print_t ahd_int_coalescing_cmdcount_print;
+#else
+#define ahd_int_coalescing_cmdcount_print(regvalue, cur_col, wrap) \
+ ahd_print_register(NULL, 0, "INT_COALESCING_CMDCOUNT", 0x156, regvalue, cur_col, wrap)
+#endif
+
+#if AIC_DEBUG_REGISTERS
+ahd_reg_print_t ahd_local_hs_mailbox_print;
+#else
+#define ahd_local_hs_mailbox_print(regvalue, cur_col, wrap) \
+ ahd_print_register(NULL, 0, "LOCAL_HS_MAILBOX", 0x157, regvalue, cur_col, wrap)
+#endif
+
+#if AIC_DEBUG_REGISTERS
+ahd_reg_print_t ahd_cmdsize_table_print;
+#else
+#define ahd_cmdsize_table_print(regvalue, cur_col, wrap) \
+ ahd_print_register(NULL, 0, "CMDSIZE_TABLE", 0x158, regvalue, cur_col, wrap)
+#endif
+
+#if AIC_DEBUG_REGISTERS
+ahd_reg_print_t ahd_mk_message_scb_print;
+#else
+#define ahd_mk_message_scb_print(regvalue, cur_col, wrap) \
+ ahd_print_register(NULL, 0, "MK_MESSAGE_SCB", 0x160, regvalue, cur_col, wrap)
+#endif
+
+#if AIC_DEBUG_REGISTERS
+ahd_reg_print_t ahd_mk_message_scsiid_print;
+#else
+#define ahd_mk_message_scsiid_print(regvalue, cur_col, wrap) \
+ ahd_print_register(NULL, 0, "MK_MESSAGE_SCSIID", 0x162, regvalue, cur_col, wrap)
+#endif
+
+#if AIC_DEBUG_REGISTERS
+ahd_reg_print_t ahd_scb_base_print;
+#else
+#define ahd_scb_base_print(regvalue, cur_col, wrap) \
+ ahd_print_register(NULL, 0, "SCB_BASE", 0x180, regvalue, cur_col, wrap)
+#endif
+
+#if AIC_DEBUG_REGISTERS
+ahd_reg_print_t ahd_scb_residual_datacnt_print;
+#else
+#define ahd_scb_residual_datacnt_print(regvalue, cur_col, wrap) \
+ ahd_print_register(NULL, 0, "SCB_RESIDUAL_DATACNT", 0x180, regvalue, cur_col, wrap)
+#endif
+
+#if AIC_DEBUG_REGISTERS
+ahd_reg_print_t ahd_scb_residual_sgptr_print;
+#else
+#define ahd_scb_residual_sgptr_print(regvalue, cur_col, wrap) \
+ ahd_print_register(NULL, 0, "SCB_RESIDUAL_SGPTR", 0x184, regvalue, cur_col, wrap)
+#endif
+
+#if AIC_DEBUG_REGISTERS
+ahd_reg_print_t ahd_scb_scsi_status_print;
+#else
+#define ahd_scb_scsi_status_print(regvalue, cur_col, wrap) \
+ ahd_print_register(NULL, 0, "SCB_SCSI_STATUS", 0x188, regvalue, cur_col, wrap)
+#endif
+
+#if AIC_DEBUG_REGISTERS
+ahd_reg_print_t ahd_scb_target_phases_print;
+#else
+#define ahd_scb_target_phases_print(regvalue, cur_col, wrap) \
+ ahd_print_register(NULL, 0, "SCB_TARGET_PHASES", 0x189, regvalue, cur_col, wrap)
+#endif
+
+#if AIC_DEBUG_REGISTERS
+ahd_reg_print_t ahd_scb_target_data_dir_print;
+#else
+#define ahd_scb_target_data_dir_print(regvalue, cur_col, wrap) \
+ ahd_print_register(NULL, 0, "SCB_TARGET_DATA_DIR", 0x18a, regvalue, cur_col, wrap)
+#endif
+
+#if AIC_DEBUG_REGISTERS
+ahd_reg_print_t ahd_scb_target_itag_print;
+#else
+#define ahd_scb_target_itag_print(regvalue, cur_col, wrap) \
+ ahd_print_register(NULL, 0, "SCB_TARGET_ITAG", 0x18b, regvalue, cur_col, wrap)
+#endif
+
+#if AIC_DEBUG_REGISTERS
+ahd_reg_print_t ahd_scb_sense_busaddr_print;
+#else
+#define ahd_scb_sense_busaddr_print(regvalue, cur_col, wrap) \
+ ahd_print_register(NULL, 0, "SCB_SENSE_BUSADDR", 0x18c, regvalue, cur_col, wrap)
+#endif
+
+#if AIC_DEBUG_REGISTERS
+ahd_reg_print_t ahd_scb_tag_print;
+#else
+#define ahd_scb_tag_print(regvalue, cur_col, wrap) \
+ ahd_print_register(NULL, 0, "SCB_TAG", 0x190, regvalue, cur_col, wrap)
+#endif
+
+#if AIC_DEBUG_REGISTERS
+ahd_reg_print_t ahd_scb_control_print;
+#else
+#define ahd_scb_control_print(regvalue, cur_col, wrap) \
+ ahd_print_register(NULL, 0, "SCB_CONTROL", 0x192, regvalue, cur_col, wrap)
+#endif
+
+#if AIC_DEBUG_REGISTERS
+ahd_reg_print_t ahd_scb_scsiid_print;
+#else
+#define ahd_scb_scsiid_print(regvalue, cur_col, wrap) \
+ ahd_print_register(NULL, 0, "SCB_SCSIID", 0x193, regvalue, cur_col, wrap)
+#endif
+
+#if AIC_DEBUG_REGISTERS
+ahd_reg_print_t ahd_scb_lun_print;
+#else
+#define ahd_scb_lun_print(regvalue, cur_col, wrap) \
+ ahd_print_register(NULL, 0, "SCB_LUN", 0x194, regvalue, cur_col, wrap)
+#endif
+
+#if AIC_DEBUG_REGISTERS
+ahd_reg_print_t ahd_scb_task_attribute_print;
+#else
+#define ahd_scb_task_attribute_print(regvalue, cur_col, wrap) \
+ ahd_print_register(NULL, 0, "SCB_TASK_ATTRIBUTE", 0x195, regvalue, cur_col, wrap)
+#endif
+
+#if AIC_DEBUG_REGISTERS
+ahd_reg_print_t ahd_scb_cdb_len_print;
+#else
+#define ahd_scb_cdb_len_print(regvalue, cur_col, wrap) \
+ ahd_print_register(NULL, 0, "SCB_CDB_LEN", 0x196, regvalue, cur_col, wrap)
+#endif
+
+#if AIC_DEBUG_REGISTERS
+ahd_reg_print_t ahd_scb_task_management_print;
+#else
+#define ahd_scb_task_management_print(regvalue, cur_col, wrap) \
+ ahd_print_register(NULL, 0, "SCB_TASK_MANAGEMENT", 0x197, regvalue, cur_col, wrap)
+#endif
+
+#if AIC_DEBUG_REGISTERS
+ahd_reg_print_t ahd_scb_dataptr_print;
+#else
+#define ahd_scb_dataptr_print(regvalue, cur_col, wrap) \
+ ahd_print_register(NULL, 0, "SCB_DATAPTR", 0x198, regvalue, cur_col, wrap)
+#endif
+
+#if AIC_DEBUG_REGISTERS
+ahd_reg_print_t ahd_scb_datacnt_print;
+#else
+#define ahd_scb_datacnt_print(regvalue, cur_col, wrap) \
+ ahd_print_register(NULL, 0, "SCB_DATACNT", 0x1a0, regvalue, cur_col, wrap)
+#endif
+
+#if AIC_DEBUG_REGISTERS
+ahd_reg_print_t ahd_scb_sgptr_print;
+#else
+#define ahd_scb_sgptr_print(regvalue, cur_col, wrap) \
+ ahd_print_register(NULL, 0, "SCB_SGPTR", 0x1a4, regvalue, cur_col, wrap)
+#endif
+
+#if AIC_DEBUG_REGISTERS
+ahd_reg_print_t ahd_scb_busaddr_print;
+#else
+#define ahd_scb_busaddr_print(regvalue, cur_col, wrap) \
+ ahd_print_register(NULL, 0, "SCB_BUSADDR", 0x1a8, regvalue, cur_col, wrap)
+#endif
+
+#if AIC_DEBUG_REGISTERS
+ahd_reg_print_t ahd_scb_next_print;
+#else
+#define ahd_scb_next_print(regvalue, cur_col, wrap) \
+ ahd_print_register(NULL, 0, "SCB_NEXT", 0x1ac, regvalue, cur_col, wrap)
+#endif
+
+#if AIC_DEBUG_REGISTERS
+ahd_reg_print_t ahd_scb_next2_print;
+#else
+#define ahd_scb_next2_print(regvalue, cur_col, wrap) \
+ ahd_print_register(NULL, 0, "SCB_NEXT2", 0x1ae, regvalue, cur_col, wrap)
+#endif
+
+#if AIC_DEBUG_REGISTERS
+ahd_reg_print_t ahd_scb_spare_print;
+#else
+#define ahd_scb_spare_print(regvalue, cur_col, wrap) \
+ ahd_print_register(NULL, 0, "SCB_SPARE", 0x1b0, regvalue, cur_col, wrap)
+#endif
+
+#if AIC_DEBUG_REGISTERS
+ahd_reg_print_t ahd_scb_disconnected_lists_print;
+#else
+#define ahd_scb_disconnected_lists_print(regvalue, cur_col, wrap) \
+ ahd_print_register(NULL, 0, "SCB_DISCONNECTED_LISTS", 0x1b8, regvalue, cur_col, wrap)
+#endif
+
+
+#define MODE_PTR 0x00
+#define DST_MODE 0x70
+#define SRC_MODE 0x07
+
+#define INTSTAT 0x01
+#define INT_PEND 0xff
+#define HWERRINT 0x80
+#define BRKADRINT 0x40
+#define SWTMINT 0x20
+#define PCIINT 0x10
+#define SCSIINT 0x08
+#define SEQINT 0x04
+#define CMDCMPLT 0x02
+#define SPLTINT 0x01
+
+#define SEQINTCODE 0x02
+#define BAD_SCB_STATUS 0x1a
+#define SAW_HWERR 0x19
+#define TRACEPOINT3 0x18
+#define TRACEPOINT2 0x17
+#define TRACEPOINT1 0x16
+#define TRACEPOINT0 0x15
+#define TASKMGMT_CMD_CMPLT_OKAY 0x14
+#define TASKMGMT_FUNC_COMPLETE 0x13
+#define ENTERING_NONPACK 0x12
+#define CFG4OVERRUN 0x11
+#define STATUS_OVERRUN 0x10
+#define CFG4ISTAT_INTR 0x0f
+#define INVALID_SEQINT 0x0e
+#define ILLEGAL_PHASE 0x0d
+#define DUMP_CARD_STATE 0x0c
+#define MISSED_BUSFREE 0x0b
+#define MKMSG_FAILED 0x0a
+#define DATA_OVERRUN 0x09
+#define BAD_STATUS 0x08
+#define HOST_MSG_LOOP 0x07
+#define PDATA_REINIT 0x06
+#define IGN_WIDE_RES 0x05
+#define NO_MATCH 0x04
+#define PROTO_VIOLATION 0x03
+#define SEND_REJECT 0x02
+#define BAD_PHASE 0x01
+#define NO_SEQINT 0x00
+
+#define CLRINT 0x03
+#define CLRHWERRINT 0x80
+#define CLRBRKADRINT 0x40
+#define CLRSWTMINT 0x20
+#define CLRPCIINT 0x10
+#define CLRSCSIINT 0x08
+#define CLRSEQINT 0x04
+#define CLRCMDINT 0x02
+#define CLRSPLTINT 0x01
+
+#define ERROR 0x04
+#define CIOPARERR 0x80
+#define CIOACCESFAIL 0x40
+#define MPARERR 0x20
+#define DPARERR 0x10
+#define SQPARERR 0x08
+#define ILLOPCODE 0x04
+#define DSCTMOUT 0x02
+
+#define CLRERR 0x04
+#define CLRCIOPARERR 0x80
+#define CLRCIOACCESFAIL 0x40
+#define CLRMPARERR 0x20
+#define CLRDPARERR 0x10
+#define CLRSQPARERR 0x08
+#define CLRILLOPCODE 0x04
+#define CLRDSCTMOUT 0x02
+
+#define HCNTRL 0x05
+#define SEQ_RESET 0x80
+#define POWRDN 0x40
+#define SWINT 0x10
+#define SWTIMER_START_B 0x08
+#define PAUSE 0x04
+#define INTEN 0x02
+#define CHIPRST 0x01
+#define CHIPRSTACK 0x01
+
+#define HNSCB_QOFF 0x06
+
+#define HESCB_QOFF 0x08
+
+#define HS_MAILBOX 0x0b
+#define HOST_TQINPOS 0x80
+#define ENINT_COALESCE 0x40
+
+#define SEQINTSTAT 0x0c
+#define SEQ_SWTMRTO 0x10
+#define SEQ_SEQINT 0x08
+#define SEQ_SCSIINT 0x04
+#define SEQ_PCIINT 0x02
+#define SEQ_SPLTINT 0x01
+
+#define CLRSEQINTSTAT 0x0c
+#define CLRSEQ_SWTMRTO 0x10
+#define CLRSEQ_SEQINT 0x08
+#define CLRSEQ_SCSIINT 0x04
+#define CLRSEQ_PCIINT 0x02
+#define CLRSEQ_SPLTINT 0x01
+
+#define SWTIMER 0x0e
+
+#define SNSCB_QOFF 0x10
+
+#define SESCB_QOFF 0x12
+
+#define SDSCB_QOFF 0x14
+
+#define QOFF_CTLSTA 0x16
+#define EMPTY_SCB_AVAIL 0x80
+#define NEW_SCB_AVAIL 0x40
+#define SDSCB_ROLLOVR 0x20
+#define HS_MAILBOX_ACT 0x10
+#define SCB_QSIZE 0x0f
+#define SCB_QSIZE_16384 0x0c
+#define SCB_QSIZE_8192 0x0b
+#define SCB_QSIZE_4096 0x0a
+#define SCB_QSIZE_2048 0x09
+#define SCB_QSIZE_1024 0x08
+#define SCB_QSIZE_512 0x07
+#define SCB_QSIZE_256 0x06
+#define SCB_QSIZE_128 0x05
+#define SCB_QSIZE_64 0x04
+#define SCB_QSIZE_32 0x03
+#define SCB_QSIZE_16 0x02
+#define SCB_QSIZE_8 0x01
+#define SCB_QSIZE_4 0x00
+
+#define INTCTL 0x18
+#define SWTMINTMASK 0x80
+#define SWTMINTEN 0x40
+#define SWTIMER_START 0x20
+#define AUTOCLRCMDINT 0x10
+#define PCIINTEN 0x08
+#define SCSIINTEN 0x04
+#define SEQINTEN 0x02
+#define SPLTINTEN 0x01
+
+#define DFCNTRL 0x19
+#define SCSIENWRDIS 0x40
+#define SCSIENACK 0x20
+#define DIRECTIONACK 0x04
+#define FIFOFLUSHACK 0x02
+#define DIRECTIONEN 0x01
+
+#define DSCOMMAND0 0x19
+#define CACHETHEN 0x80
+#define DPARCKEN 0x40
+#define MPARCKEN 0x20
+#define EXTREQLCK 0x10
+#define DISABLE_TWATE 0x02
+#define CIOPARCKEN 0x01
+
+#define DFSTATUS 0x1a
+#define PRELOAD_AVAIL 0x80
+#define PKT_PRELOAD_AVAIL 0x40
+#define MREQPEND 0x10
+#define HDONE 0x08
+#define DFTHRESH 0x04
+#define FIFOFULL 0x02
+#define FIFOEMP 0x01
+
+#define SG_CACHE_SHADOW 0x1b
+#define ODD_SEG 0x04
+#define LAST_SEG 0x02
+#define LAST_SEG_DONE 0x01
+
+#define SG_CACHE_PRE 0x1b
+
+#define ARBCTL 0x1b
+#define RESET_HARB 0x80
+#define RETRY_SWEN 0x08
+#define USE_TIME 0x07
+
+#define LQIN 0x20
+
+#define TYPEPTR 0x20
+
+#define TAGPTR 0x21
+
+#define LUNPTR 0x22
+
+#define DATALENPTR 0x23
+
+#define STATLENPTR 0x24
+
+#define CMDLENPTR 0x25
+
+#define ATTRPTR 0x26
+
+#define FLAGPTR 0x27
+
+#define CMDPTR 0x28
+
+#define QNEXTPTR 0x29
+
+#define IDPTR 0x2a
+
+#define ABRTBYTEPTR 0x2b
+
+#define ABRTBITPTR 0x2c
+
+#define MAXCMDBYTES 0x2d
+
+#define MAXCMD2RCV 0x2e
+
+#define SHORTTHRESH 0x2f
+
+#define LUNLEN 0x30
+#define TLUNLEN 0xf0
+#define ILUNLEN 0x0f
+
+#define CDBLIMIT 0x31
+
+#define MAXCMD 0x32
+
+#define MAXCMDCNT 0x33
+
+#define LQRSVD01 0x34
+
+#define LQRSVD16 0x35
+
+#define LQRSVD17 0x36
+
+#define CMDRSVD0 0x37
+
+#define LQCTL0 0x38
+#define LQITARGCLT 0xc0
+#define LQIINITGCLT 0x30
+#define LQ0TARGCLT 0x0c
+#define LQ0INITGCLT 0x03
+
+#define LQCTL1 0x38
+#define PCI2PCI 0x04
+#define SINGLECMD 0x02
+#define ABORTPENDING 0x01
+
+#define LQCTL2 0x39
+#define LQIRETRY 0x80
+#define LQICONTINUE 0x40
+#define LQITOIDLE 0x20
+#define LQIPAUSE 0x10
+#define LQORETRY 0x08
+#define LQOCONTINUE 0x04
+#define LQOTOIDLE 0x02
+#define LQOPAUSE 0x01
+
+#define SCSBIST0 0x39
+#define GSBISTERR 0x40
+#define GSBISTDONE 0x20
+#define GSBISTRUN 0x10
+#define OSBISTERR 0x04
+#define OSBISTDONE 0x02
+#define OSBISTRUN 0x01
+
+#define SCSISEQ0 0x3a
+#define TEMODEO 0x80
+#define ENSELO 0x40
+#define ENARBO 0x20
+#define FORCEBUSFREE 0x10
+#define SCSIRSTO 0x01
+
+#define SCSBIST1 0x3a
+#define NTBISTERR 0x04
+#define NTBISTDONE 0x02
+#define NTBISTRUN 0x01
+
+#define SCSISEQ1 0x3b
+
+#define BUSINITID 0x3c
+
+#define SXFRCTL0 0x3c
+#define DFON 0x80
+#define DFPEXP 0x40
+#define BIOSCANCELEN 0x10
+#define SPIOEN 0x08
+
+#define DLCOUNT 0x3c
+
+#define SXFRCTL1 0x3d
+#define BITBUCKET 0x80
+#define ENSACHK 0x40
+#define ENSPCHK 0x20
+#define STIMESEL 0x18
+#define ENSTIMER 0x04
+#define ACTNEGEN 0x02
+#define STPWEN 0x01
+
+#define BUSTARGID 0x3e
+
+#define SXFRCTL2 0x3e
+#define AUTORSTDIS 0x10
+#define CMDDMAEN 0x08
+#define ASU 0x07
+
+#define DFFSTAT 0x3f
+#define CURRFIFO 0x03
+#define FIFO1FREE 0x20
+#define FIFO0FREE 0x10
+#define CURRFIFO_NONE 0x03
+#define CURRFIFO_1 0x01
+#define CURRFIFO_0 0x00
+
+#define SCSISIGO 0x40
+#define CDO 0x80
+#define IOO 0x40
+#define MSGO 0x20
+#define ATNO 0x10
+#define SELO 0x08
+#define BSYO 0x04
+#define REQO 0x02
+#define ACKO 0x01
+
+#define MULTARGID 0x40
+
+#define SCSISIGI 0x41
+#define ATNI 0x10
+#define SELI 0x08
+#define BSYI 0x04
+#define REQI 0x02
+#define ACKI 0x01
+
+#define SCSIPHASE 0x42
+#define STATUS_PHASE 0x20
+#define COMMAND_PHASE 0x10
+#define MSG_IN_PHASE 0x08
+#define MSG_OUT_PHASE 0x04
+#define DATA_PHASE_MASK 0x03
+#define DATA_IN_PHASE 0x02
+#define DATA_OUT_PHASE 0x01
+
+#define SCSIDAT0_IMG 0x43
+
+#define SCSIDAT 0x44
+
+#define SCSIBUS 0x46
+
+#define TARGIDIN 0x48
+#define CLKOUT 0x80
+#define TARGID 0x0f
+
+#define SELID 0x49
+#define SELID_MASK 0xf0
+#define ONEBIT 0x08
+
+#define OPTIONMODE 0x4a
+#define OPTIONMODE_DEFAULTS 0x02
+#define BIOSCANCTL 0x80
+#define AUTOACKEN 0x40
+#define BIASCANCTL 0x20
+#define BUSFREEREV 0x10
+#define ENDGFORMCHK 0x04
+#define AUTO_MSGOUT_DE 0x02
+
+#define SBLKCTL 0x4a
+#define DIAGLEDEN 0x80
+#define DIAGLEDON 0x40
+#define ENAB40 0x08
+#define ENAB20 0x04
+#define SELWIDE 0x02
+
+#define SIMODE0 0x4b
+#define ENSELDO 0x40
+#define ENSELDI 0x20
+#define ENSELINGO 0x10
+#define ENIOERR 0x08
+#define ENOVERRUN 0x04
+#define ENSPIORDY 0x02
+#define ENARBDO 0x01
+
+#define SSTAT0 0x4b
+#define TARGET 0x80
+#define SELDO 0x40
+#define SELDI 0x20
+#define SELINGO 0x10
+#define IOERR 0x08
+#define OVERRUN 0x04
+#define SPIORDY 0x02
+#define ARBDO 0x01
+
+#define CLRSINT0 0x4b
+#define CLRSELDO 0x40
+#define CLRSELDI 0x20
+#define CLRSELINGO 0x10
+#define CLRIOERR 0x08
+#define CLROVERRUN 0x04
+#define CLRSPIORDY 0x02
+#define CLRARBDO 0x01
+
+#define SSTAT1 0x4c
+#define SELTO 0x80
+#define ATNTARG 0x40
+#define SCSIRSTI 0x20
+#define PHASEMIS 0x10
+#define BUSFREE 0x08
+#define SCSIPERR 0x04
+#define STRB2FAST 0x02
+#define REQINIT 0x01
+
+#define CLRSINT1 0x4c
+#define CLRSELTIMEO 0x80
+#define CLRATNO 0x40
+#define CLRSCSIRSTI 0x20
+#define CLRBUSFREE 0x08
+#define CLRSCSIPERR 0x04
+#define CLRSTRB2FAST 0x02
+#define CLRREQINIT 0x01
+
+#define SSTAT2 0x4d
+#define BUSFREETIME 0xc0
+#define NONPACKREQ 0x20
+#define EXP_ACTIVE 0x10
+#define BSYX 0x08
+#define WIDE_RES 0x04
+#define SDONE 0x02
+#define DMADONE 0x01
+#define BUSFREE_DFF1 0xc0
+#define BUSFREE_DFF0 0x80
+#define BUSFREE_LQO 0x40
+
+#define CLRSINT2 0x4d
+#define CLRNONPACKREQ 0x20
+#define CLRWIDE_RES 0x04
+#define CLRSDONE 0x02
+#define CLRDMADONE 0x01
+
+#define SIMODE2 0x4d
+#define ENWIDE_RES 0x04
+#define ENSDONE 0x02
+#define ENDMADONE 0x01
+
+#define PERRDIAG 0x4e
+#define HIZERO 0x80
+#define HIPERR 0x40
+#define PREVPHASE 0x20
+#define PARITYERR 0x10
+#define AIPERR 0x08
+#define CRCERR 0x04
+#define DGFORMERR 0x02
+#define DTERR 0x01
+
+#define LQISTATE 0x4e
+
+#define SOFFCNT 0x4f
+
+#define LQOSTATE 0x4f
+
+#define LQISTAT0 0x50
+#define LQIATNQAS 0x20
+#define LQICRCT1 0x10
+#define LQICRCT2 0x08
+#define LQIBADLQT 0x04
+#define LQIATNLQ 0x02
+#define LQIATNCMD 0x01
+
+#define CLRLQIINT0 0x50
+#define CLRLQIATNQAS 0x20
+#define CLRLQICRCT1 0x10
+#define CLRLQICRCT2 0x08
+#define CLRLQIBADLQT 0x04
+#define CLRLQIATNLQ 0x02
+#define CLRLQIATNCMD 0x01
+
+#define LQIMODE0 0x50
+#define ENLQIATNQASK 0x20
+#define ENLQICRCT1 0x10
+#define ENLQICRCT2 0x08
+#define ENLQIBADLQT 0x04
+#define ENLQIATNLQ 0x02
+#define ENLQIATNCMD 0x01
+
+#define LQISTAT1 0x51
+#define LQIPHASE_LQ 0x80
+#define LQIPHASE_NLQ 0x40
+#define LQIABORT 0x20
+#define LQICRCI_LQ 0x10
+#define LQICRCI_NLQ 0x08
+#define LQIBADLQI 0x04
+#define LQIOVERI_LQ 0x02
+#define LQIOVERI_NLQ 0x01
+
+#define CLRLQIINT1 0x51
+#define CLRLQIPHASE_LQ 0x80
+#define CLRLQIPHASE_NLQ 0x40
+#define CLRLIQABORT 0x20
+#define CLRLQICRCI_LQ 0x10
+#define CLRLQICRCI_NLQ 0x08
+#define CLRLQIBADLQI 0x04
+#define CLRLQIOVERI_LQ 0x02
+#define CLRLQIOVERI_NLQ 0x01
+
+#define LQIMODE1 0x51
+#define ENLQIPHASE_LQ 0x80
+#define ENLQIPHASE_NLQ 0x40
+#define ENLIQABORT 0x20
+#define ENLQICRCI_LQ 0x10
+#define ENLQICRCI_NLQ 0x08
+#define ENLQIBADLQI 0x04
+#define ENLQIOVERI_LQ 0x02
+#define ENLQIOVERI_NLQ 0x01
+
+#define LQISTAT2 0x52
+#define PACKETIZED 0x80
+#define LQIPHASE_OUTPKT 0x40
+#define LQIWORKONLQ 0x20
+#define LQIWAITFIFO 0x10
+#define LQISTOPPKT 0x08
+#define LQISTOPLQ 0x04
+#define LQISTOPCMD 0x02
+#define LQIGSAVAIL 0x01
+
+#define SSTAT3 0x53
+#define NTRAMPERR 0x02
+#define OSRAMPERR 0x01
+
+#define CLRSINT3 0x53
+#define CLRNTRAMPERR 0x02
+#define CLROSRAMPERR 0x01
+
+#define SIMODE3 0x53
+#define ENNTRAMPERR 0x02
+#define ENOSRAMPERR 0x01
+
+#define LQOMODE0 0x54
+#define ENLQOTARGSCBPERR 0x10
+#define ENLQOSTOPT2 0x08
+#define ENLQOATNLQ 0x04
+#define ENLQOATNPKT 0x02
+#define ENLQOTCRC 0x01
+
+#define LQOSTAT0 0x54
+#define LQOTARGSCBPERR 0x10
+#define LQOSTOPT2 0x08
+#define LQOATNLQ 0x04
+#define LQOATNPKT 0x02
+#define LQOTCRC 0x01
+
+#define CLRLQOINT0 0x54
+#define CLRLQOTARGSCBPERR 0x10
+#define CLRLQOSTOPT2 0x08
+#define CLRLQOATNLQ 0x04
+#define CLRLQOATNPKT 0x02
+#define CLRLQOTCRC 0x01
+
+#define LQOMODE1 0x55
+#define ENLQOINITSCBPERR 0x10
+#define ENLQOSTOPI2 0x08
+#define ENLQOBADQAS 0x04
+#define ENLQOBUSFREE 0x02
+#define ENLQOPHACHGINPKT 0x01
+
+#define LQOSTAT1 0x55
+#define LQOINITSCBPERR 0x10
+#define LQOSTOPI2 0x08
+#define LQOBADQAS 0x04
+#define LQOBUSFREE 0x02
+#define LQOPHACHGINPKT 0x01
+
+#define CLRLQOINT1 0x55
+#define CLRLQOINITSCBPERR 0x10
+#define CLRLQOSTOPI2 0x08
+#define CLRLQOBADQAS 0x04
+#define CLRLQOBUSFREE 0x02
+#define CLRLQOPHACHGINPKT 0x01
+
+#define OS_SPACE_CNT 0x56
+
+#define LQOSTAT2 0x56
+#define LQOPKT 0xe0
+#define LQOWAITFIFO 0x10
+#define LQOPHACHGOUTPKT 0x02
+#define LQOSTOP0 0x01
+
+#define SIMODE1 0x57
+#define ENSELTIMO 0x80
+#define ENATNTARG 0x40
+#define ENSCSIRST 0x20
+#define ENPHASEMIS 0x10
+#define ENBUSFREE 0x08
+#define ENSCSIPERR 0x04
+#define ENSTRB2FAST 0x02
+#define ENREQINIT 0x01
+
+#define GSFIFO 0x58
+
+#define DFFSXFRCTL 0x5a
+#define DFFBITBUCKET 0x08
+#define CLRSHCNT 0x04
+#define CLRCHN 0x02
+#define RSTCHN 0x01
+
+#define NEXTSCB 0x5a
+
+#define LQOSCSCTL 0x5a
+#define LQOH2A_VERSION 0x80
+#define LQONOCHKOVER 0x01
+
+#define SEQINTSRC 0x5b
+#define CTXTDONE 0x40
+#define SAVEPTRS 0x20
+#define CFG4DATA 0x10
+#define CFG4ISTAT 0x08
+#define CFG4TSTAT 0x04
+#define CFG4ICMD 0x02
+#define CFG4TCMD 0x01
+
+#define CLRSEQINTSRC 0x5b
+#define CLRCTXTDONE 0x40
+#define CLRSAVEPTRS 0x20
+#define CLRCFG4DATA 0x10
+#define CLRCFG4ISTAT 0x08
+#define CLRCFG4TSTAT 0x04
+#define CLRCFG4ICMD 0x02
+#define CLRCFG4TCMD 0x01
+
+#define CURRSCB 0x5c
+
+#define SEQIMODE 0x5c
+#define ENCTXTDONE 0x40
+#define ENSAVEPTRS 0x20
+#define ENCFG4DATA 0x10
+#define ENCFG4ISTAT 0x08
+#define ENCFG4TSTAT 0x04
+#define ENCFG4ICMD 0x02
+#define ENCFG4TCMD 0x01
+
+#define MDFFSTAT 0x5d
+#define SHCNTNEGATIVE 0x40
+#define SHCNTMINUS1 0x20
+#define LASTSDONE 0x10
+#define SHVALID 0x08
+#define DLZERO 0x04
+#define DATAINFIFO 0x02
+#define FIFOFREE 0x01
+
+#define CRCCONTROL 0x5d
+#define CRCVALCHKEN 0x40
+
+#define SCSITEST 0x5e
+#define CNTRTEST 0x08
+#define SEL_TXPLL_DEBUG 0x04
+
+#define DFFTAG 0x5e
+
+#define LASTSCB 0x5e
+
+#define IOPDNCTL 0x5f
+#define DISABLE_OE 0x80
+#define PDN_IDIST 0x04
+#define PDN_DIFFSENSE 0x01
+
+#define NEGOADDR 0x60
+
+#define SHADDR 0x60
+
+#define DGRPCRCI 0x60
+
+#define NEGPERIOD 0x61
+
+#define PACKCRCI 0x62
+
+#define NEGOFFSET 0x62
+
+#define NEGPPROPTS 0x63
+#define PPROPT_PACE 0x08
+#define PPROPT_QAS 0x04
+#define PPROPT_DT 0x02
+#define PPROPT_IUT 0x01
+
+#define NEGCONOPTS 0x64
+#define ENSNAPSHOT 0x40
+#define RTI_WRTDIS 0x20
+#define RTI_OVRDTRN 0x10
+#define ENSLOWCRC 0x08
+#define ENAUTOATNI 0x04
+#define ENAUTOATNO 0x02
+#define WIDEXFER 0x01
+
+#define ANNEXCOL 0x65
+
+#define ANNEXDAT 0x66
+
+#define SCSCHKN 0x66
+#define STSELSKIDDIS 0x40
+#define CURRFIFODEF 0x20
+#define WIDERESEN 0x10
+#define SDONEMSKDIS 0x08
+#define DFFACTCLR 0x04
+#define SHVALIDSTDIS 0x02
+#define LSTSGCLRDIS 0x01
+
+#define IOWNID 0x67
+
+#define SHCNT 0x68
+
+#define PLL960CTL0 0x68
+
+#define PLL960CTL1 0x69
+
+#define TOWNID 0x69
+
+#define XSIG 0x6a
+
+#define PLL960CNT0 0x6a
+
+#define SELOID 0x6b
+
+#define FAIRNESS 0x6c
+
+#define PLL400CTL0 0x6c
+#define PLL_VCOSEL 0x80
+#define PLL_PWDN 0x40
+#define PLL_NS 0x30
+#define PLL_ENLUD 0x08
+#define PLL_ENLPF 0x04
+#define PLL_DLPF 0x02
+#define PLL_ENFBM 0x01
+
+#define PLL400CTL1 0x6d
+#define PLL_CNTEN 0x80
+#define PLL_CNTCLR 0x40
+#define PLL_RST 0x01
+
+#define PLL400CNT0 0x6e
+
+#define UNFAIRNESS 0x6e
+
+#define HODMAADR 0x70
+
+#define HADDR 0x70
+
+#define PLLDELAY 0x70
+#define SPLIT_DROP_REQ 0x80
+
+#define HCNT 0x78
+
+#define HODMACNT 0x78
+
+#define HODMAEN 0x7a
+
+#define SCBHADDR 0x7c
+
+#define SGHADDR 0x7c
+
+#define SCBHCNT 0x84
+
+#define SGHCNT 0x84
+
+#define DFF_THRSH 0x88
+#define WR_DFTHRSH 0x70
+#define RD_DFTHRSH 0x07
+#define WR_DFTHRSH_MAX 0x70
+#define WR_DFTHRSH_90 0x60
+#define WR_DFTHRSH_85 0x50
+#define WR_DFTHRSH_75 0x40
+#define WR_DFTHRSH_63 0x30
+#define WR_DFTHRSH_50 0x20
+#define WR_DFTHRSH_25 0x10
+#define RD_DFTHRSH_MAX 0x07
+#define RD_DFTHRSH_90 0x06
+#define RD_DFTHRSH_85 0x05
+#define RD_DFTHRSH_75 0x04
+#define RD_DFTHRSH_63 0x03
+#define RD_DFTHRSH_50 0x02
+#define RD_DFTHRSH_25 0x01
+#define WR_DFTHRSH_MIN 0x00
+#define RD_DFTHRSH_MIN 0x00
+
+#define ROMADDR 0x8a
+
+#define ROMCNTRL 0x8d
+#define ROMOP 0xe0
+#define ROMSPD 0x18
+#define REPEAT 0x02
+#define RDY 0x01
+
+#define ROMDATA 0x8e
+
+#define DCHRXMSG0 0x90
+
+#define OVLYRXMSG0 0x90
+
+#define CMCRXMSG0 0x90
+
+#define ROENABLE 0x90
+#define MSIROEN 0x20
+#define OVLYROEN 0x10
+#define CMCROEN 0x08
+#define SGROEN 0x04
+#define DCH1ROEN 0x02
+#define DCH0ROEN 0x01
+
+#define DCHRXMSG1 0x91
+
+#define OVLYRXMSG1 0x91
+
+#define CMCRXMSG1 0x91
+
+#define NSENABLE 0x91
+#define MSINSEN 0x20
+#define OVLYNSEN 0x10
+#define CMCNSEN 0x08
+#define SGNSEN 0x04
+#define DCH1NSEN 0x02
+#define DCH0NSEN 0x01
+
+#define DCHRXMSG2 0x92
+
+#define OVLYRXMSG2 0x92
+
+#define CMCRXMSG2 0x92
+
+#define OST 0x92
+
+#define DCHRXMSG3 0x93
+
+#define OVLYRXMSG3 0x93
+
+#define CMCRXMSG3 0x93
+
+#define PCIXCTL 0x93
+#define SERRPULSE 0x80
+#define UNEXPSCIEN 0x20
+#define SPLTSMADIS 0x10
+#define SPLTSTADIS 0x08
+#define SRSPDPEEN 0x04
+#define TSCSERREN 0x02
+#define CMPABCDIS 0x01
+
+#define CMCSEQBCNT 0x94
+
+#define DCHSEQBCNT 0x94
+
+#define OVLYSEQBCNT 0x94
+
+#define CMCSPLTSTAT0 0x96
+
+#define DCHSPLTSTAT0 0x96
+
+#define OVLYSPLTSTAT0 0x96
+
+#define CMCSPLTSTAT1 0x97
+
+#define DCHSPLTSTAT1 0x97
+
+#define OVLYSPLTSTAT1 0x97
+
+#define SGRXMSG0 0x98
+#define CDNUM 0xf8
+#define CFNUM 0x07
+
+#define SLVSPLTOUTADR0 0x98
+#define LOWER_ADDR 0x7f
+
+#define SGRXMSG1 0x99
+#define CBNUM 0xff
+
+#define SLVSPLTOUTADR1 0x99
+#define REQ_DNUM 0xf8
+#define REQ_FNUM 0x07
+
+#define SGRXMSG2 0x9a
+#define MINDEX 0xff
+
+#define SLVSPLTOUTADR2 0x9a
+#define REQ_BNUM 0xff
+
+#define SGRXMSG3 0x9b
+#define MCLASS 0x0f
+
+#define SLVSPLTOUTADR3 0x9b
+#define TAG_NUM 0x1f
+#define RLXORD 0x10
+
+#define SLVSPLTOUTATTR0 0x9c
+#define LOWER_BCNT 0xff
+
+#define SGSEQBCNT 0x9c
+
+#define SLVSPLTOUTATTR1 0x9d
+#define CMPLT_DNUM 0xf8
+#define CMPLT_FNUM 0x07
+
+#define SLVSPLTOUTATTR2 0x9e
+#define CMPLT_BNUM 0xff
+
+#define SGSPLTSTAT0 0x9e
+#define STAETERM 0x80
+#define SCBCERR 0x40
+#define SCADERR 0x20
+#define SCDATBUCKET 0x10
+#define CNTNOTCMPLT 0x08
+#define RXOVRUN 0x04
+#define RXSCEMSG 0x02
+#define RXSPLTRSP 0x01
+
+#define SFUNCT 0x9f
+#define TEST_GROUP 0xf0
+#define TEST_NUM 0x0f
+
+#define SGSPLTSTAT1 0x9f
+#define RXDATABUCKET 0x01
+
+#define DF0PCISTAT 0xa0
+
+#define REG0 0xa0
+
+#define DF1PCISTAT 0xa1
+
+#define SGPCISTAT 0xa2
+
+#define REG1 0xa2
+
+#define CMCPCISTAT 0xa3
+
+#define OVLYPCISTAT 0xa4
+#define SCAAPERR 0x08
+#define RDPERR 0x04
+
+#define REG_ISR 0xa4
+
+#define MSIPCISTAT 0xa6
+#define RMA 0x20
+#define RTA 0x10
+#define CLRPENDMSI 0x08
+#define DPR 0x01
+
+#define SG_STATE 0xa6
+#define FETCH_INPROG 0x04
+#define LOADING_NEEDED 0x02
+#define SEGS_AVAIL 0x01
+
+#define TARGPCISTAT 0xa7
+#define DPE 0x80
+#define SSE 0x40
+#define STA 0x08
+#define TWATERR 0x02
+
+#define DATA_COUNT_ODD 0xa7
+
+#define SCBPTR 0xa8
+
+#define CCSCBACNT 0xab
+
+#define SCBAUTOPTR 0xab
+#define AUSCBPTR_EN 0x80
+#define SCBPTR_ADDR 0x38
+#define SCBPTR_OFF 0x07
+
+#define CCSCBADR_BK 0xac
+
+#define CCSGADDR 0xac
+
+#define CCSCBADDR 0xac
+
+#define CCSCBCTL 0xad
+#define CCSCBDONE 0x80
+#define ARRDONE 0x40
+#define CCARREN 0x10
+#define CCSCBEN 0x08
+#define CCSCBDIR 0x04
+#define CCSCBRESET 0x01
+
+#define CCSGCTL 0xad
+#define CCSGEN 0x0c
+#define CCSGDONE 0x80
+#define SG_CACHE_AVAIL 0x10
+#define CCSGENACK 0x08
+#define SG_FETCH_REQ 0x02
+#define CCSGRESET 0x01
+
+#define CMC_RAMBIST 0xad
+#define SG_ELEMENT_SIZE 0x80
+#define SCBRAMBIST_FAIL 0x40
+#define SG_BIST_FAIL 0x20
+#define SG_BIST_EN 0x10
+#define CMC_BUFFER_BIST_FAIL 0x02
+#define CMC_BUFFER_BIST_EN 0x01
+
+#define CCSGRAM 0xb0
+
+#define CCSCBRAM 0xb0
+
+#define FLEXADR 0xb0
+
+#define FLEXCNT 0xb3
+
+#define FLEXDMASTAT 0xb5
+#define FLEXDMAERR 0x02
+#define FLEXDMADONE 0x01
+
+#define FLEXDATA 0xb6
+
+#define BRDDAT 0xb8
+
+#define BRDCTL 0xb9
+#define FLXARBACK 0x80
+#define FLXARBREQ 0x40
+#define BRDADDR 0x38
+#define BRDEN 0x04
+#define BRDRW 0x02
+#define BRDSTB 0x01
+
+#define SEEADR 0xba
+
+#define SEEDAT 0xbc
+
+#define SEECTL 0xbe
+#define SEEOP_EWEN 0x40
+#define SEEOP_EWDS 0x40
+#define SEEOP_WALL 0x40
+#define SEEOPCODE 0x70
+#define SEERST 0x02
+#define SEESTART 0x01
+#define SEEOP_ERASE 0x70
+#define SEEOP_READ 0x60
+#define SEEOP_WRITE 0x50
+#define SEEOP_ERAL 0x40
+
+#define SEESTAT 0xbe
+#define INIT_DONE 0x80
+#define LDALTID_L 0x08
+#define SEEARBACK 0x04
+#define SEEBUSY 0x02
+
+#define SCBCNT 0xbf
+
+#define DSPFLTRCTL 0xc0
+#define FLTRDISABLE 0x20
+#define EDGESENSE 0x10
+#define DSPFCNTSEL 0x0f
+
+#define DFWADDR 0xc0
+
+#define DSPDATACTL 0xc1
+#define BYPASSENAB 0x80
+#define DESQDIS 0x10
+#define RCVROFFSTDIS 0x04
+#define XMITOFFSTDIS 0x02
+
+#define DSPREQCTL 0xc2
+#define MANREQCTL 0xc0
+#define MANREQDLY 0x3f
+
+#define DFRADDR 0xc2
+
+#define DSPACKCTL 0xc3
+#define MANACKCTL 0xc0
+#define MANACKDLY 0x3f
+
+#define DFDAT 0xc4
+
+#define DSPSELECT 0xc4
+#define AUTOINCEN 0x80
+#define DSPSEL 0x1f
+
+#define WRTBIASCTL 0xc5
+#define AUTOXBCDIS 0x80
+#define XMITMANVAL 0x3f
+
+#define RCVRBIOSCTL 0xc6
+#define AUTORBCDIS 0x80
+#define RCVRMANVAL 0x3f
+
+#define WRTBIASCALC 0xc7
+
+#define DFPTRS 0xc8
+
+#define RCVRBIASCALC 0xc8
+
+#define DFBKPTR 0xc9
+
+#define SKEWCALC 0xc9
+
+#define DFDBCTL 0xcb
+#define DFF_CIO_WR_RDY 0x20
+#define DFF_CIO_RD_RDY 0x10
+#define DFF_DIR_ERR 0x08
+#define DFF_RAMBIST_FAIL 0x04
+#define DFF_RAMBIST_DONE 0x02
+#define DFF_RAMBIST_EN 0x01
+
+#define DFSCNT 0xcc
+
+#define DFBCNT 0xce
+
+#define OVLYADDR 0xd4
+
+#define SEQCTL0 0xd6
+#define PERRORDIS 0x80
+#define PAUSEDIS 0x40
+#define FAILDIS 0x20
+#define FASTMODE 0x10
+#define BRKADRINTEN 0x08
+#define STEP 0x04
+#define SEQRESET 0x02
+#define LOADRAM 0x01
+
+#define SEQCTL1 0xd7
+#define OVRLAY_DATA_CHK 0x08
+#define RAMBIST_DONE 0x04
+#define RAMBIST_FAIL 0x02
+#define RAMBIST_EN 0x01
+
+#define FLAGS 0xd8
+#define ZERO 0x02
+#define CARRY 0x01
+
+#define SEQINTCTL 0xd9
+#define INTVEC1DSL 0x80
+#define INT1_CONTEXT 0x20
+#define SCS_SEQ_INT1M1 0x10
+#define SCS_SEQ_INT1M0 0x08
+#define INTMASK2 0x04
+#define INTMASK1 0x02
+#define IRET 0x01
+
+#define SEQRAM 0xda
+
+#define PRGMCNT 0xde
+
+#define ACCUM 0xe0
+
+#define SINDEX 0xe2
+
+#define DINDEX 0xe4
+
+#define BRKADDR1 0xe6
+#define BRKDIS 0x80
+
+#define BRKADDR0 0xe6
+
+#define ALLONES 0xe8
+
+#define NONE 0xea
+
+#define ALLZEROS 0xea
+
+#define SINDIR 0xec
+
+#define DINDIR 0xed
+
+#define FUNCTION1 0xf0
+
+#define STACK 0xf2
+
+#define INTVEC1_ADDR 0xf4
+
+#define CURADDR 0xf4
+
+#define INTVEC2_ADDR 0xf6
+
+#define LASTADDR 0xf6
+
+#define LONGJMP_ADDR 0xf8
+
+#define ACCUM_SAVE 0xfa
+
+#define SRAM_BASE 0x100
+
+#define WAITING_SCB_TAILS 0x100
+
+#define AHD_PCI_CONFIG_BASE 0x100
+
+#define WAITING_TID_HEAD 0x120
+
+#define WAITING_TID_TAIL 0x122
+
+#define NEXT_QUEUED_SCB_ADDR 0x124
+
+#define COMPLETE_SCB_HEAD 0x128
+
+#define COMPLETE_SCB_DMAINPROG_HEAD 0x12a
+
+#define COMPLETE_DMA_SCB_HEAD 0x12c
+
+#define COMPLETE_DMA_SCB_TAIL 0x12e
+
+#define COMPLETE_ON_QFREEZE_HEAD 0x130
+
+#define QFREEZE_COUNT 0x132
+
+#define KERNEL_QFREEZE_COUNT 0x134
+
+#define SAVED_MODE 0x136
+
+#define MSG_OUT 0x137
+
+#define DMAPARAMS 0x138
+#define PRELOADEN 0x80
+#define WIDEODD 0x40
+#define SCSIEN 0x20
+#define SDMAEN 0x10
+#define SDMAENACK 0x10
+#define HDMAEN 0x08
+#define HDMAENACK 0x08
+#define DIRECTION 0x04
+#define FIFOFLUSH 0x02
+#define FIFORESET 0x01
+
+#define SEQ_FLAGS 0x139
+#define NOT_IDENTIFIED 0x80
+#define NO_CDB_SENT 0x40
+#define TARGET_CMD_IS_TAGGED 0x40
+#define DPHASE 0x20
+#define TARG_CMD_PENDING 0x10
+#define CMDPHASE_PENDING 0x08
+#define DPHASE_PENDING 0x04
+#define SPHASE_PENDING 0x02
+#define NO_DISCONNECT 0x01
+
+#define SAVED_SCSIID 0x13a
+
+#define SAVED_LUN 0x13b
+
+#define LASTPHASE 0x13c
+#define PHASE_MASK 0xe0
+#define CDI 0x80
+#define IOI 0x40
+#define MSGI 0x20
+#define P_BUSFREE 0x01
+#define P_MESGIN 0xe0
+#define P_STATUS 0xc0
+#define P_MESGOUT 0xa0
+#define P_COMMAND 0x80
+#define P_DATAIN_DT 0x60
+#define P_DATAIN 0x40
+#define P_DATAOUT_DT 0x20
+#define P_DATAOUT 0x00
+
+#define QOUTFIFO_ENTRY_VALID_TAG 0x13d
+
+#define KERNEL_TQINPOS 0x13e
+
+#define TQINPOS 0x13f
+
+#define SHARED_DATA_ADDR 0x140
+
+#define QOUTFIFO_NEXT_ADDR 0x144
+
+#define ARG_1 0x148
+#define RETURN_1 0x148
+#define SEND_MSG 0x80
+#define SEND_SENSE 0x40
+#define SEND_REJ 0x20
+#define MSGOUT_PHASEMIS 0x10
+#define EXIT_MSG_LOOP 0x08
+#define CONT_MSG_LOOP_WRITE 0x04
+#define CONT_MSG_LOOP_READ 0x03
+#define CONT_MSG_LOOP_TARG 0x02
+
+#define ARG_2 0x149
+#define RETURN_2 0x149
+
+#define LAST_MSG 0x14a
+
+#define SCSISEQ_TEMPLATE 0x14b
+#define MANUALCTL 0x40
+#define ENSELI 0x20
+#define ENRSELI 0x10
+#define MANUALP 0x0c
+#define ENAUTOATNP 0x02
+#define ALTSTIM 0x01
+
+#define INITIATOR_TAG 0x14c
+
+#define SEQ_FLAGS2 0x14d
+#define SELECTOUT_QFROZEN 0x04
+#define TARGET_MSG_PENDING 0x02
+#define PENDING_MK_MESSAGE 0x01
+
+#define ALLOCFIFO_SCBPTR 0x14e
+
+#define INT_COALESCING_TIMER 0x150
+
+#define INT_COALESCING_MAXCMDS 0x152
+
+#define INT_COALESCING_MINCMDS 0x153
+
+#define CMDS_PENDING 0x154
+
+#define INT_COALESCING_CMDCOUNT 0x156
+
+#define LOCAL_HS_MAILBOX 0x157
+
+#define CMDSIZE_TABLE 0x158
+
+#define MK_MESSAGE_SCB 0x160
+
+#define MK_MESSAGE_SCSIID 0x162
+
+#define SCB_BASE 0x180
+
+#define SCB_RESIDUAL_DATACNT 0x180
+#define SCB_HOST_CDB_PTR 0x180
+#define SCB_CDB_STORE 0x180
+
+#define SCB_RESIDUAL_SGPTR 0x184
+#define SG_ADDR_MASK 0xf8
+#define SG_ADDR_BIT 0x04
+#define SG_OVERRUN_RESID 0x02
+
+#define SCB_SCSI_STATUS 0x188
+#define SCB_HOST_CDB_LEN 0x188
+
+#define SCB_TARGET_PHASES 0x189
+
+#define SCB_TARGET_DATA_DIR 0x18a
+
+#define SCB_TARGET_ITAG 0x18b
+
+#define SCB_SENSE_BUSADDR 0x18c
+#define SCB_NEXT_COMPLETE 0x18c
+
+#define SCB_TAG 0x190
+#define SCB_FIFO_USE_COUNT 0x190
+
+#define SCB_CONTROL 0x192
+#define TARGET_SCB 0x80
+#define DISCENB 0x40
+#define TAG_ENB 0x20
+#define MK_MESSAGE 0x10
+#define STATUS_RCVD 0x08
+#define DISCONNECTED 0x04
+#define SCB_TAG_TYPE 0x03
+
+#define SCB_SCSIID 0x193
+#define TID 0xf0
+#define OID 0x0f
+
+#define SCB_LUN 0x194
+#define LID 0xff
+
+#define SCB_TASK_ATTRIBUTE 0x195
+#define SCB_XFERLEN_ODD 0x01
+
+#define SCB_CDB_LEN 0x196
+#define SCB_CDB_LEN_PTR 0x80
+
+#define SCB_TASK_MANAGEMENT 0x197
+
+#define SCB_DATAPTR 0x198
+
+#define SCB_DATACNT 0x1a0
+#define SG_LAST_SEG 0x80
+#define SG_HIGH_ADDR_BITS 0x7f
+
+#define SCB_SGPTR 0x1a4
+#define SG_STATUS_VALID 0x04
+#define SG_FULL_RESID 0x02
+#define SG_LIST_NULL 0x01
+
+#define SCB_BUSADDR 0x1a8
+
+#define SCB_NEXT 0x1ac
+#define SCB_NEXT_SCB_BUSADDR 0x1ac
+
+#define SCB_NEXT2 0x1ae
+
+#define SCB_SPARE 0x1b0
+#define SCB_PKT_LUN 0x1b0
+
+#define SCB_DISCONNECTED_LISTS 0x1b8
+
+
+#define STATUS_QUEUE_FULL 0x28
+#define WRTBIASCTL_HP_DEFAULT 0x00
+#define NUMDSPS 0x14
+#define AHD_NUM_PER_DEV_ANNEXCOLS 0x04
+#define AHD_TIMER_MAX_US 0x18ffe7
+#define STIMESEL_MIN 0x18
+#define TARGET_CMD_CMPLT 0xfe
+#define SEEOP_ERAL_ADDR 0x80
+#define SRC_MODE_SHIFT 0x00
+#define SCB_TRANSFER_SIZE_1BYTE_LUN 0x30
+#define MAX_OFFSET_PACED 0xfe
+#define SEEOP_EWDS_ADDR 0x00
+#define AHD_ANNEXCOL_AMPLITUDE 0x06
+#define AHD_PRECOMP_CUTBACK_29 0x06
+#define AHD_ANNEXCOL_PER_DEV0 0x04
+#define AHD_TIMER_MAX_TICKS 0xffff
+#define STATUS_PKT_SENSE 0xff
+#define CMD_GROUP_CODE_SHIFT 0x05
+#define BUS_8_BIT 0x00
+#define CCSGRAM_MAXSEGS 0x10
+#define AHD_AMPLITUDE_DEF 0x07
+#define AHD_SLEWRATE_DEF_REVB 0x08
+#define AHD_PRECOMP_CUTBACK_37 0x07
+#define AHD_PRECOMP_SHIFT 0x00
+#define PKT_OVERRUN_BUFSIZE 0x200
+#define SCB_TRANSFER_SIZE_FULL_LUN 0x38
+#define TARGET_DATA_IN 0x01
+#define STATUS_BUSY 0x08
+#define BUS_16_BIT 0x01
+#define CCSCBADDR_MAX 0x80
+#define TID_SHIFT 0x04
+#define AHD_AMPLITUDE_SHIFT 0x00
+#define AHD_SLEWRATE_DEF_REVA 0x08
+#define AHD_SLEWRATE_MASK 0x78
+#define MAX_OFFSET_PACED_BUG 0x7f
+#define AHD_PRECOMP_CUTBACK_17 0x04
+#define AHD_PRECOMP_MASK 0x07
+#define AHD_TIMER_US_PER_TICK 0x19
+#define HOST_MSG 0xff
+#define MAX_OFFSET 0xfe
+#define BUS_32_BIT 0x02
+#define SEEOP_EWEN_ADDR 0xc0
+#define AHD_AMPLITUDE_MASK 0x07
+#define LUNLEN_SINGLE_LEVEL_LUN 0x0f
+#define DST_MODE_SHIFT 0x04
+#define STIMESEL_SHIFT 0x03
+#define SEEOP_WRAL_ADDR 0x40
+#define AHD_ANNEXCOL_PRECOMP_SLEW 0x04
+#define MAX_OFFSET_NON_PACED 0x7f
+#define NVRAM_SCB_OFFSET 0x2c
+#define AHD_SENSE_BUFSIZE 0x100
+#define STIMESEL_BUG_ADJ 0x08
+#define INVALID_ADDR 0x80
+#define CCSGADDR_MAX 0x80
+#define MK_MESSAGE_BIT_OFFSET 0x04
+#define AHD_SLEWRATE_SHIFT 0x03
+#define B_CURRFIFO_0 0x02
+
+
+/* Downloaded Constant Definitions */
+#define SG_SIZEOF 0x04
+#define CACHELINE_MASK 0x07
+#define SG_PREFETCH_ADDR_MASK 0x03
+#define SG_PREFETCH_ALIGN_MASK 0x02
+#define SCB_TRANSFER_SIZE 0x06
+#define SG_PREFETCH_CNT 0x00
+#define SG_PREFETCH_CNT_LIMIT 0x01
+#define PKT_OVERRUN_BUFOFFSET 0x05
+#define DOWNLOAD_CONST_COUNT 0x08
+
+
+/* Exported Labels */
+#define LABEL_seq_isr 0x28f
+#define LABEL_timer_isr 0x28b
Property changes on: trunk/sys/dev/aic7xxx/aic79xx_reg.h
___________________________________________________________________
Added: svn:eol-style
## -0,0 +1 ##
+native
\ No newline at end of property
Added: svn:keywords
## -0,0 +1 ##
+MidnightBSD=%H
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+text/plain
\ No newline at end of property
Added: trunk/sys/dev/aic7xxx/aic79xx_reg_print.c
===================================================================
--- trunk/sys/dev/aic7xxx/aic79xx_reg_print.c (rev 0)
+++ trunk/sys/dev/aic7xxx/aic79xx_reg_print.c 2018-05-28 00:27:43 UTC (rev 10128)
@@ -0,0 +1,3675 @@
+/* $MidnightBSD$ */
+/*
+ * DO NOT EDIT - This file is automatically generated
+ * from the following source files:
+ *
+ * $Id: //depot/aic7xxx/aic7xxx/aic79xx.seq#119 $
+ * $Id: //depot/aic7xxx/aic7xxx/aic79xx.reg#76 $
+ */
+
+#include <sys/cdefs.h>
+__FBSDID("$FreeBSD: stable/10/sys/dev/aic7xxx/aic79xx_reg_print.c 270284 2014-08-21 17:18:21Z ian $");
+#include <dev/aic7xxx/aic79xx_osm.h>
+
+static ahd_reg_parse_entry_t MODE_PTR_parse_table[] = {
+ { "SRC_MODE", 0x07, 0x07 },
+ { "DST_MODE", 0x70, 0x70 }
+};
+
+int
+ahd_mode_ptr_print(u_int regvalue, u_int *cur_col, u_int wrap)
+{
+ return (ahd_print_register(MODE_PTR_parse_table, 2, "MODE_PTR",
+ 0x00, regvalue, cur_col, wrap));
+}
+
+static ahd_reg_parse_entry_t INTSTAT_parse_table[] = {
+ { "SPLTINT", 0x01, 0x01 },
+ { "CMDCMPLT", 0x02, 0x02 },
+ { "SEQINT", 0x04, 0x04 },
+ { "SCSIINT", 0x08, 0x08 },
+ { "PCIINT", 0x10, 0x10 },
+ { "SWTMINT", 0x20, 0x20 },
+ { "BRKADRINT", 0x40, 0x40 },
+ { "HWERRINT", 0x80, 0x80 },
+ { "INT_PEND", 0xff, 0xff }
+};
+
+int
+ahd_intstat_print(u_int regvalue, u_int *cur_col, u_int wrap)
+{
+ return (ahd_print_register(INTSTAT_parse_table, 9, "INTSTAT",
+ 0x01, regvalue, cur_col, wrap));
+}
+
+static ahd_reg_parse_entry_t SEQINTCODE_parse_table[] = {
+ { "NO_SEQINT", 0x00, 0xff },
+ { "BAD_PHASE", 0x01, 0xff },
+ { "SEND_REJECT", 0x02, 0xff },
+ { "PROTO_VIOLATION", 0x03, 0xff },
+ { "NO_MATCH", 0x04, 0xff },
+ { "IGN_WIDE_RES", 0x05, 0xff },
+ { "PDATA_REINIT", 0x06, 0xff },
+ { "HOST_MSG_LOOP", 0x07, 0xff },
+ { "BAD_STATUS", 0x08, 0xff },
+ { "DATA_OVERRUN", 0x09, 0xff },
+ { "MKMSG_FAILED", 0x0a, 0xff },
+ { "MISSED_BUSFREE", 0x0b, 0xff },
+ { "DUMP_CARD_STATE", 0x0c, 0xff },
+ { "ILLEGAL_PHASE", 0x0d, 0xff },
+ { "INVALID_SEQINT", 0x0e, 0xff },
+ { "CFG4ISTAT_INTR", 0x0f, 0xff },
+ { "STATUS_OVERRUN", 0x10, 0xff },
+ { "CFG4OVERRUN", 0x11, 0xff },
+ { "ENTERING_NONPACK", 0x12, 0xff },
+ { "TASKMGMT_FUNC_COMPLETE",0x13, 0xff },
+ { "TASKMGMT_CMD_CMPLT_OKAY",0x14, 0xff },
+ { "TRACEPOINT0", 0x15, 0xff },
+ { "TRACEPOINT1", 0x16, 0xff },
+ { "TRACEPOINT2", 0x17, 0xff },
+ { "TRACEPOINT3", 0x18, 0xff },
+ { "SAW_HWERR", 0x19, 0xff },
+ { "BAD_SCB_STATUS", 0x1a, 0xff }
+};
+
+int
+ahd_seqintcode_print(u_int regvalue, u_int *cur_col, u_int wrap)
+{
+ return (ahd_print_register(SEQINTCODE_parse_table, 27, "SEQINTCODE",
+ 0x02, regvalue, cur_col, wrap));
+}
+
+static ahd_reg_parse_entry_t CLRINT_parse_table[] = {
+ { "CLRSPLTINT", 0x01, 0x01 },
+ { "CLRCMDINT", 0x02, 0x02 },
+ { "CLRSEQINT", 0x04, 0x04 },
+ { "CLRSCSIINT", 0x08, 0x08 },
+ { "CLRPCIINT", 0x10, 0x10 },
+ { "CLRSWTMINT", 0x20, 0x20 },
+ { "CLRBRKADRINT", 0x40, 0x40 },
+ { "CLRHWERRINT", 0x80, 0x80 }
+};
+
+int
+ahd_clrint_print(u_int regvalue, u_int *cur_col, u_int wrap)
+{
+ return (ahd_print_register(CLRINT_parse_table, 8, "CLRINT",
+ 0x03, regvalue, cur_col, wrap));
+}
+
+static ahd_reg_parse_entry_t ERROR_parse_table[] = {
+ { "DSCTMOUT", 0x02, 0x02 },
+ { "ILLOPCODE", 0x04, 0x04 },
+ { "SQPARERR", 0x08, 0x08 },
+ { "DPARERR", 0x10, 0x10 },
+ { "MPARERR", 0x20, 0x20 },
+ { "CIOACCESFAIL", 0x40, 0x40 },
+ { "CIOPARERR", 0x80, 0x80 }
+};
+
+int
+ahd_error_print(u_int regvalue, u_int *cur_col, u_int wrap)
+{
+ return (ahd_print_register(ERROR_parse_table, 7, "ERROR",
+ 0x04, regvalue, cur_col, wrap));
+}
+
+static ahd_reg_parse_entry_t CLRERR_parse_table[] = {
+ { "CLRDSCTMOUT", 0x02, 0x02 },
+ { "CLRILLOPCODE", 0x04, 0x04 },
+ { "CLRSQPARERR", 0x08, 0x08 },
+ { "CLRDPARERR", 0x10, 0x10 },
+ { "CLRMPARERR", 0x20, 0x20 },
+ { "CLRCIOACCESFAIL", 0x40, 0x40 },
+ { "CLRCIOPARERR", 0x80, 0x80 }
+};
+
+int
+ahd_clrerr_print(u_int regvalue, u_int *cur_col, u_int wrap)
+{
+ return (ahd_print_register(CLRERR_parse_table, 7, "CLRERR",
+ 0x04, regvalue, cur_col, wrap));
+}
+
+static ahd_reg_parse_entry_t HCNTRL_parse_table[] = {
+ { "CHIPRST", 0x01, 0x01 },
+ { "CHIPRSTACK", 0x01, 0x01 },
+ { "INTEN", 0x02, 0x02 },
+ { "PAUSE", 0x04, 0x04 },
+ { "SWTIMER_START_B", 0x08, 0x08 },
+ { "SWINT", 0x10, 0x10 },
+ { "POWRDN", 0x40, 0x40 },
+ { "SEQ_RESET", 0x80, 0x80 }
+};
+
+int
+ahd_hcntrl_print(u_int regvalue, u_int *cur_col, u_int wrap)
+{
+ return (ahd_print_register(HCNTRL_parse_table, 8, "HCNTRL",
+ 0x05, regvalue, cur_col, wrap));
+}
+
+int
+ahd_hnscb_qoff_print(u_int regvalue, u_int *cur_col, u_int wrap)
+{
+ return (ahd_print_register(NULL, 0, "HNSCB_QOFF",
+ 0x06, regvalue, cur_col, wrap));
+}
+
+int
+ahd_hescb_qoff_print(u_int regvalue, u_int *cur_col, u_int wrap)
+{
+ return (ahd_print_register(NULL, 0, "HESCB_QOFF",
+ 0x08, regvalue, cur_col, wrap));
+}
+
+static ahd_reg_parse_entry_t HS_MAILBOX_parse_table[] = {
+ { "ENINT_COALESCE", 0x40, 0x40 },
+ { "HOST_TQINPOS", 0x80, 0x80 }
+};
+
+int
+ahd_hs_mailbox_print(u_int regvalue, u_int *cur_col, u_int wrap)
+{
+ return (ahd_print_register(HS_MAILBOX_parse_table, 2, "HS_MAILBOX",
+ 0x0b, regvalue, cur_col, wrap));
+}
+
+static ahd_reg_parse_entry_t SEQINTSTAT_parse_table[] = {
+ { "SEQ_SPLTINT", 0x01, 0x01 },
+ { "SEQ_PCIINT", 0x02, 0x02 },
+ { "SEQ_SCSIINT", 0x04, 0x04 },
+ { "SEQ_SEQINT", 0x08, 0x08 },
+ { "SEQ_SWTMRTO", 0x10, 0x10 }
+};
+
+int
+ahd_seqintstat_print(u_int regvalue, u_int *cur_col, u_int wrap)
+{
+ return (ahd_print_register(SEQINTSTAT_parse_table, 5, "SEQINTSTAT",
+ 0x0c, regvalue, cur_col, wrap));
+}
+
+static ahd_reg_parse_entry_t CLRSEQINTSTAT_parse_table[] = {
+ { "CLRSEQ_SPLTINT", 0x01, 0x01 },
+ { "CLRSEQ_PCIINT", 0x02, 0x02 },
+ { "CLRSEQ_SCSIINT", 0x04, 0x04 },
+ { "CLRSEQ_SEQINT", 0x08, 0x08 },
+ { "CLRSEQ_SWTMRTO", 0x10, 0x10 }
+};
+
+int
+ahd_clrseqintstat_print(u_int regvalue, u_int *cur_col, u_int wrap)
+{
+ return (ahd_print_register(CLRSEQINTSTAT_parse_table, 5, "CLRSEQINTSTAT",
+ 0x0c, regvalue, cur_col, wrap));
+}
+
+int
+ahd_swtimer_print(u_int regvalue, u_int *cur_col, u_int wrap)
+{
+ return (ahd_print_register(NULL, 0, "SWTIMER",
+ 0x0e, regvalue, cur_col, wrap));
+}
+
+int
+ahd_snscb_qoff_print(u_int regvalue, u_int *cur_col, u_int wrap)
+{
+ return (ahd_print_register(NULL, 0, "SNSCB_QOFF",
+ 0x10, regvalue, cur_col, wrap));
+}
+
+int
+ahd_sescb_qoff_print(u_int regvalue, u_int *cur_col, u_int wrap)
+{
+ return (ahd_print_register(NULL, 0, "SESCB_QOFF",
+ 0x12, regvalue, cur_col, wrap));
+}
+
+int
+ahd_sdscb_qoff_print(u_int regvalue, u_int *cur_col, u_int wrap)
+{
+ return (ahd_print_register(NULL, 0, "SDSCB_QOFF",
+ 0x14, regvalue, cur_col, wrap));
+}
+
+static ahd_reg_parse_entry_t QOFF_CTLSTA_parse_table[] = {
+ { "SCB_QSIZE_4", 0x00, 0x0f },
+ { "SCB_QSIZE_8", 0x01, 0x0f },
+ { "SCB_QSIZE_16", 0x02, 0x0f },
+ { "SCB_QSIZE_32", 0x03, 0x0f },
+ { "SCB_QSIZE_64", 0x04, 0x0f },
+ { "SCB_QSIZE_128", 0x05, 0x0f },
+ { "SCB_QSIZE_256", 0x06, 0x0f },
+ { "SCB_QSIZE_512", 0x07, 0x0f },
+ { "SCB_QSIZE_1024", 0x08, 0x0f },
+ { "SCB_QSIZE_2048", 0x09, 0x0f },
+ { "SCB_QSIZE_4096", 0x0a, 0x0f },
+ { "SCB_QSIZE_8192", 0x0b, 0x0f },
+ { "SCB_QSIZE_16384", 0x0c, 0x0f },
+ { "SCB_QSIZE", 0x0f, 0x0f },
+ { "HS_MAILBOX_ACT", 0x10, 0x10 },
+ { "SDSCB_ROLLOVR", 0x20, 0x20 },
+ { "NEW_SCB_AVAIL", 0x40, 0x40 },
+ { "EMPTY_SCB_AVAIL", 0x80, 0x80 }
+};
+
+int
+ahd_qoff_ctlsta_print(u_int regvalue, u_int *cur_col, u_int wrap)
+{
+ return (ahd_print_register(QOFF_CTLSTA_parse_table, 18, "QOFF_CTLSTA",
+ 0x16, regvalue, cur_col, wrap));
+}
+
+static ahd_reg_parse_entry_t INTCTL_parse_table[] = {
+ { "SPLTINTEN", 0x01, 0x01 },
+ { "SEQINTEN", 0x02, 0x02 },
+ { "SCSIINTEN", 0x04, 0x04 },
+ { "PCIINTEN", 0x08, 0x08 },
+ { "AUTOCLRCMDINT", 0x10, 0x10 },
+ { "SWTIMER_START", 0x20, 0x20 },
+ { "SWTMINTEN", 0x40, 0x40 },
+ { "SWTMINTMASK", 0x80, 0x80 }
+};
+
+int
+ahd_intctl_print(u_int regvalue, u_int *cur_col, u_int wrap)
+{
+ return (ahd_print_register(INTCTL_parse_table, 8, "INTCTL",
+ 0x18, regvalue, cur_col, wrap));
+}
+
+static ahd_reg_parse_entry_t DFCNTRL_parse_table[] = {
+ { "DIRECTIONEN", 0x01, 0x01 },
+ { "FIFOFLUSH", 0x02, 0x02 },
+ { "FIFOFLUSHACK", 0x02, 0x02 },
+ { "DIRECTION", 0x04, 0x04 },
+ { "DIRECTIONACK", 0x04, 0x04 },
+ { "HDMAEN", 0x08, 0x08 },
+ { "HDMAENACK", 0x08, 0x08 },
+ { "SCSIEN", 0x20, 0x20 },
+ { "SCSIENACK", 0x20, 0x20 },
+ { "SCSIENWRDIS", 0x40, 0x40 },
+ { "PRELOADEN", 0x80, 0x80 }
+};
+
+int
+ahd_dfcntrl_print(u_int regvalue, u_int *cur_col, u_int wrap)
+{
+ return (ahd_print_register(DFCNTRL_parse_table, 11, "DFCNTRL",
+ 0x19, regvalue, cur_col, wrap));
+}
+
+static ahd_reg_parse_entry_t DSCOMMAND0_parse_table[] = {
+ { "CIOPARCKEN", 0x01, 0x01 },
+ { "DISABLE_TWATE", 0x02, 0x02 },
+ { "EXTREQLCK", 0x10, 0x10 },
+ { "MPARCKEN", 0x20, 0x20 },
+ { "DPARCKEN", 0x40, 0x40 },
+ { "CACHETHEN", 0x80, 0x80 }
+};
+
+int
+ahd_dscommand0_print(u_int regvalue, u_int *cur_col, u_int wrap)
+{
+ return (ahd_print_register(DSCOMMAND0_parse_table, 6, "DSCOMMAND0",
+ 0x19, regvalue, cur_col, wrap));
+}
+
+static ahd_reg_parse_entry_t DFSTATUS_parse_table[] = {
+ { "FIFOEMP", 0x01, 0x01 },
+ { "FIFOFULL", 0x02, 0x02 },
+ { "DFTHRESH", 0x04, 0x04 },
+ { "HDONE", 0x08, 0x08 },
+ { "MREQPEND", 0x10, 0x10 },
+ { "PKT_PRELOAD_AVAIL", 0x40, 0x40 },
+ { "PRELOAD_AVAIL", 0x80, 0x80 }
+};
+
+int
+ahd_dfstatus_print(u_int regvalue, u_int *cur_col, u_int wrap)
+{
+ return (ahd_print_register(DFSTATUS_parse_table, 7, "DFSTATUS",
+ 0x1a, regvalue, cur_col, wrap));
+}
+
+static ahd_reg_parse_entry_t SG_CACHE_SHADOW_parse_table[] = {
+ { "LAST_SEG_DONE", 0x01, 0x01 },
+ { "LAST_SEG", 0x02, 0x02 },
+ { "ODD_SEG", 0x04, 0x04 },
+ { "SG_ADDR_MASK", 0xf8, 0xf8 }
+};
+
+int
+ahd_sg_cache_shadow_print(u_int regvalue, u_int *cur_col, u_int wrap)
+{
+ return (ahd_print_register(SG_CACHE_SHADOW_parse_table, 4, "SG_CACHE_SHADOW",
+ 0x1b, regvalue, cur_col, wrap));
+}
+
+static ahd_reg_parse_entry_t SG_CACHE_PRE_parse_table[] = {
+ { "LAST_SEG", 0x02, 0x02 },
+ { "ODD_SEG", 0x04, 0x04 },
+ { "SG_ADDR_MASK", 0xf8, 0xf8 }
+};
+
+int
+ahd_sg_cache_pre_print(u_int regvalue, u_int *cur_col, u_int wrap)
+{
+ return (ahd_print_register(SG_CACHE_PRE_parse_table, 3, "SG_CACHE_PRE",
+ 0x1b, regvalue, cur_col, wrap));
+}
+
+static ahd_reg_parse_entry_t ARBCTL_parse_table[] = {
+ { "USE_TIME", 0x07, 0x07 },
+ { "RETRY_SWEN", 0x08, 0x08 },
+ { "RESET_HARB", 0x80, 0x80 }
+};
+
+int
+ahd_arbctl_print(u_int regvalue, u_int *cur_col, u_int wrap)
+{
+ return (ahd_print_register(ARBCTL_parse_table, 3, "ARBCTL",
+ 0x1b, regvalue, cur_col, wrap));
+}
+
+int
+ahd_lqin_print(u_int regvalue, u_int *cur_col, u_int wrap)
+{
+ return (ahd_print_register(NULL, 0, "LQIN",
+ 0x20, regvalue, cur_col, wrap));
+}
+
+int
+ahd_typeptr_print(u_int regvalue, u_int *cur_col, u_int wrap)
+{
+ return (ahd_print_register(NULL, 0, "TYPEPTR",
+ 0x20, regvalue, cur_col, wrap));
+}
+
+int
+ahd_tagptr_print(u_int regvalue, u_int *cur_col, u_int wrap)
+{
+ return (ahd_print_register(NULL, 0, "TAGPTR",
+ 0x21, regvalue, cur_col, wrap));
+}
+
+int
+ahd_lunptr_print(u_int regvalue, u_int *cur_col, u_int wrap)
+{
+ return (ahd_print_register(NULL, 0, "LUNPTR",
+ 0x22, regvalue, cur_col, wrap));
+}
+
+int
+ahd_datalenptr_print(u_int regvalue, u_int *cur_col, u_int wrap)
+{
+ return (ahd_print_register(NULL, 0, "DATALENPTR",
+ 0x23, regvalue, cur_col, wrap));
+}
+
+int
+ahd_statlenptr_print(u_int regvalue, u_int *cur_col, u_int wrap)
+{
+ return (ahd_print_register(NULL, 0, "STATLENPTR",
+ 0x24, regvalue, cur_col, wrap));
+}
+
+int
+ahd_cmdlenptr_print(u_int regvalue, u_int *cur_col, u_int wrap)
+{
+ return (ahd_print_register(NULL, 0, "CMDLENPTR",
+ 0x25, regvalue, cur_col, wrap));
+}
+
+int
+ahd_attrptr_print(u_int regvalue, u_int *cur_col, u_int wrap)
+{
+ return (ahd_print_register(NULL, 0, "ATTRPTR",
+ 0x26, regvalue, cur_col, wrap));
+}
+
+int
+ahd_flagptr_print(u_int regvalue, u_int *cur_col, u_int wrap)
+{
+ return (ahd_print_register(NULL, 0, "FLAGPTR",
+ 0x27, regvalue, cur_col, wrap));
+}
+
+int
+ahd_cmdptr_print(u_int regvalue, u_int *cur_col, u_int wrap)
+{
+ return (ahd_print_register(NULL, 0, "CMDPTR",
+ 0x28, regvalue, cur_col, wrap));
+}
+
+int
+ahd_qnextptr_print(u_int regvalue, u_int *cur_col, u_int wrap)
+{
+ return (ahd_print_register(NULL, 0, "QNEXTPTR",
+ 0x29, regvalue, cur_col, wrap));
+}
+
+int
+ahd_idptr_print(u_int regvalue, u_int *cur_col, u_int wrap)
+{
+ return (ahd_print_register(NULL, 0, "IDPTR",
+ 0x2a, regvalue, cur_col, wrap));
+}
+
+int
+ahd_abrtbyteptr_print(u_int regvalue, u_int *cur_col, u_int wrap)
+{
+ return (ahd_print_register(NULL, 0, "ABRTBYTEPTR",
+ 0x2b, regvalue, cur_col, wrap));
+}
+
+int
+ahd_abrtbitptr_print(u_int regvalue, u_int *cur_col, u_int wrap)
+{
+ return (ahd_print_register(NULL, 0, "ABRTBITPTR",
+ 0x2c, regvalue, cur_col, wrap));
+}
+
+int
+ahd_maxcmdbytes_print(u_int regvalue, u_int *cur_col, u_int wrap)
+{
+ return (ahd_print_register(NULL, 0, "MAXCMDBYTES",
+ 0x2d, regvalue, cur_col, wrap));
+}
+
+int
+ahd_maxcmd2rcv_print(u_int regvalue, u_int *cur_col, u_int wrap)
+{
+ return (ahd_print_register(NULL, 0, "MAXCMD2RCV",
+ 0x2e, regvalue, cur_col, wrap));
+}
+
+int
+ahd_shortthresh_print(u_int regvalue, u_int *cur_col, u_int wrap)
+{
+ return (ahd_print_register(NULL, 0, "SHORTTHRESH",
+ 0x2f, regvalue, cur_col, wrap));
+}
+
+static ahd_reg_parse_entry_t LUNLEN_parse_table[] = {
+ { "ILUNLEN", 0x0f, 0x0f },
+ { "TLUNLEN", 0xf0, 0xf0 }
+};
+
+int
+ahd_lunlen_print(u_int regvalue, u_int *cur_col, u_int wrap)
+{
+ return (ahd_print_register(LUNLEN_parse_table, 2, "LUNLEN",
+ 0x30, regvalue, cur_col, wrap));
+}
+
+int
+ahd_cdblimit_print(u_int regvalue, u_int *cur_col, u_int wrap)
+{
+ return (ahd_print_register(NULL, 0, "CDBLIMIT",
+ 0x31, regvalue, cur_col, wrap));
+}
+
+int
+ahd_maxcmd_print(u_int regvalue, u_int *cur_col, u_int wrap)
+{
+ return (ahd_print_register(NULL, 0, "MAXCMD",
+ 0x32, regvalue, cur_col, wrap));
+}
+
+int
+ahd_maxcmdcnt_print(u_int regvalue, u_int *cur_col, u_int wrap)
+{
+ return (ahd_print_register(NULL, 0, "MAXCMDCNT",
+ 0x33, regvalue, cur_col, wrap));
+}
+
+int
+ahd_lqrsvd01_print(u_int regvalue, u_int *cur_col, u_int wrap)
+{
+ return (ahd_print_register(NULL, 0, "LQRSVD01",
+ 0x34, regvalue, cur_col, wrap));
+}
+
+int
+ahd_lqrsvd16_print(u_int regvalue, u_int *cur_col, u_int wrap)
+{
+ return (ahd_print_register(NULL, 0, "LQRSVD16",
+ 0x35, regvalue, cur_col, wrap));
+}
+
+int
+ahd_lqrsvd17_print(u_int regvalue, u_int *cur_col, u_int wrap)
+{
+ return (ahd_print_register(NULL, 0, "LQRSVD17",
+ 0x36, regvalue, cur_col, wrap));
+}
+
+int
+ahd_cmdrsvd0_print(u_int regvalue, u_int *cur_col, u_int wrap)
+{
+ return (ahd_print_register(NULL, 0, "CMDRSVD0",
+ 0x37, regvalue, cur_col, wrap));
+}
+
+static ahd_reg_parse_entry_t LQCTL0_parse_table[] = {
+ { "LQ0INITGCLT", 0x03, 0x03 },
+ { "LQ0TARGCLT", 0x0c, 0x0c },
+ { "LQIINITGCLT", 0x30, 0x30 },
+ { "LQITARGCLT", 0xc0, 0xc0 }
+};
+
+int
+ahd_lqctl0_print(u_int regvalue, u_int *cur_col, u_int wrap)
+{
+ return (ahd_print_register(LQCTL0_parse_table, 4, "LQCTL0",
+ 0x38, regvalue, cur_col, wrap));
+}
+
+static ahd_reg_parse_entry_t LQCTL1_parse_table[] = {
+ { "ABORTPENDING", 0x01, 0x01 },
+ { "SINGLECMD", 0x02, 0x02 },
+ { "PCI2PCI", 0x04, 0x04 }
+};
+
+int
+ahd_lqctl1_print(u_int regvalue, u_int *cur_col, u_int wrap)
+{
+ return (ahd_print_register(LQCTL1_parse_table, 3, "LQCTL1",
+ 0x38, regvalue, cur_col, wrap));
+}
+
+static ahd_reg_parse_entry_t LQCTL2_parse_table[] = {
+ { "LQOPAUSE", 0x01, 0x01 },
+ { "LQOTOIDLE", 0x02, 0x02 },
+ { "LQOCONTINUE", 0x04, 0x04 },
+ { "LQORETRY", 0x08, 0x08 },
+ { "LQIPAUSE", 0x10, 0x10 },
+ { "LQITOIDLE", 0x20, 0x20 },
+ { "LQICONTINUE", 0x40, 0x40 },
+ { "LQIRETRY", 0x80, 0x80 }
+};
+
+int
+ahd_lqctl2_print(u_int regvalue, u_int *cur_col, u_int wrap)
+{
+ return (ahd_print_register(LQCTL2_parse_table, 8, "LQCTL2",
+ 0x39, regvalue, cur_col, wrap));
+}
+
+static ahd_reg_parse_entry_t SCSBIST0_parse_table[] = {
+ { "OSBISTRUN", 0x01, 0x01 },
+ { "OSBISTDONE", 0x02, 0x02 },
+ { "OSBISTERR", 0x04, 0x04 },
+ { "GSBISTRUN", 0x10, 0x10 },
+ { "GSBISTDONE", 0x20, 0x20 },
+ { "GSBISTERR", 0x40, 0x40 }
+};
+
+int
+ahd_scsbist0_print(u_int regvalue, u_int *cur_col, u_int wrap)
+{
+ return (ahd_print_register(SCSBIST0_parse_table, 6, "SCSBIST0",
+ 0x39, regvalue, cur_col, wrap));
+}
+
+static ahd_reg_parse_entry_t SCSISEQ0_parse_table[] = {
+ { "SCSIRSTO", 0x01, 0x01 },
+ { "FORCEBUSFREE", 0x10, 0x10 },
+ { "ENARBO", 0x20, 0x20 },
+ { "ENSELO", 0x40, 0x40 },
+ { "TEMODEO", 0x80, 0x80 }
+};
+
+int
+ahd_scsiseq0_print(u_int regvalue, u_int *cur_col, u_int wrap)
+{
+ return (ahd_print_register(SCSISEQ0_parse_table, 5, "SCSISEQ0",
+ 0x3a, regvalue, cur_col, wrap));
+}
+
+static ahd_reg_parse_entry_t SCSBIST1_parse_table[] = {
+ { "NTBISTRUN", 0x01, 0x01 },
+ { "NTBISTDONE", 0x02, 0x02 },
+ { "NTBISTERR", 0x04, 0x04 }
+};
+
+int
+ahd_scsbist1_print(u_int regvalue, u_int *cur_col, u_int wrap)
+{
+ return (ahd_print_register(SCSBIST1_parse_table, 3, "SCSBIST1",
+ 0x3a, regvalue, cur_col, wrap));
+}
+
+static ahd_reg_parse_entry_t SCSISEQ1_parse_table[] = {
+ { "ALTSTIM", 0x01, 0x01 },
+ { "ENAUTOATNP", 0x02, 0x02 },
+ { "MANUALP", 0x0c, 0x0c },
+ { "ENRSELI", 0x10, 0x10 },
+ { "ENSELI", 0x20, 0x20 },
+ { "MANUALCTL", 0x40, 0x40 }
+};
+
+int
+ahd_scsiseq1_print(u_int regvalue, u_int *cur_col, u_int wrap)
+{
+ return (ahd_print_register(SCSISEQ1_parse_table, 6, "SCSISEQ1",
+ 0x3b, regvalue, cur_col, wrap));
+}
+
+int
+ahd_businitid_print(u_int regvalue, u_int *cur_col, u_int wrap)
+{
+ return (ahd_print_register(NULL, 0, "BUSINITID",
+ 0x3c, regvalue, cur_col, wrap));
+}
+
+static ahd_reg_parse_entry_t SXFRCTL0_parse_table[] = {
+ { "SPIOEN", 0x08, 0x08 },
+ { "BIOSCANCELEN", 0x10, 0x10 },
+ { "DFPEXP", 0x40, 0x40 },
+ { "DFON", 0x80, 0x80 }
+};
+
+int
+ahd_sxfrctl0_print(u_int regvalue, u_int *cur_col, u_int wrap)
+{
+ return (ahd_print_register(SXFRCTL0_parse_table, 4, "SXFRCTL0",
+ 0x3c, regvalue, cur_col, wrap));
+}
+
+int
+ahd_dlcount_print(u_int regvalue, u_int *cur_col, u_int wrap)
+{
+ return (ahd_print_register(NULL, 0, "DLCOUNT",
+ 0x3c, regvalue, cur_col, wrap));
+}
+
+static ahd_reg_parse_entry_t SXFRCTL1_parse_table[] = {
+ { "STPWEN", 0x01, 0x01 },
+ { "ACTNEGEN", 0x02, 0x02 },
+ { "ENSTIMER", 0x04, 0x04 },
+ { "STIMESEL", 0x18, 0x18 },
+ { "ENSPCHK", 0x20, 0x20 },
+ { "ENSACHK", 0x40, 0x40 },
+ { "BITBUCKET", 0x80, 0x80 }
+};
+
+int
+ahd_sxfrctl1_print(u_int regvalue, u_int *cur_col, u_int wrap)
+{
+ return (ahd_print_register(SXFRCTL1_parse_table, 7, "SXFRCTL1",
+ 0x3d, regvalue, cur_col, wrap));
+}
+
+int
+ahd_bustargid_print(u_int regvalue, u_int *cur_col, u_int wrap)
+{
+ return (ahd_print_register(NULL, 0, "BUSTARGID",
+ 0x3e, regvalue, cur_col, wrap));
+}
+
+static ahd_reg_parse_entry_t SXFRCTL2_parse_table[] = {
+ { "ASU", 0x07, 0x07 },
+ { "CMDDMAEN", 0x08, 0x08 },
+ { "AUTORSTDIS", 0x10, 0x10 }
+};
+
+int
+ahd_sxfrctl2_print(u_int regvalue, u_int *cur_col, u_int wrap)
+{
+ return (ahd_print_register(SXFRCTL2_parse_table, 3, "SXFRCTL2",
+ 0x3e, regvalue, cur_col, wrap));
+}
+
+static ahd_reg_parse_entry_t DFFSTAT_parse_table[] = {
+ { "CURRFIFO_0", 0x00, 0x03 },
+ { "CURRFIFO_1", 0x01, 0x03 },
+ { "CURRFIFO_NONE", 0x03, 0x03 },
+ { "FIFO0FREE", 0x10, 0x10 },
+ { "FIFO1FREE", 0x20, 0x20 },
+ { "CURRFIFO", 0x03, 0x03 }
+};
+
+int
+ahd_dffstat_print(u_int regvalue, u_int *cur_col, u_int wrap)
+{
+ return (ahd_print_register(DFFSTAT_parse_table, 6, "DFFSTAT",
+ 0x3f, regvalue, cur_col, wrap));
+}
+
+static ahd_reg_parse_entry_t SCSISIGO_parse_table[] = {
+ { "P_DATAOUT", 0x00, 0xe0 },
+ { "P_DATAOUT_DT", 0x20, 0xe0 },
+ { "P_DATAIN", 0x40, 0xe0 },
+ { "P_DATAIN_DT", 0x60, 0xe0 },
+ { "P_COMMAND", 0x80, 0xe0 },
+ { "P_MESGOUT", 0xa0, 0xe0 },
+ { "P_STATUS", 0xc0, 0xe0 },
+ { "P_MESGIN", 0xe0, 0xe0 },
+ { "ACKO", 0x01, 0x01 },
+ { "REQO", 0x02, 0x02 },
+ { "BSYO", 0x04, 0x04 },
+ { "SELO", 0x08, 0x08 },
+ { "ATNO", 0x10, 0x10 },
+ { "MSGO", 0x20, 0x20 },
+ { "IOO", 0x40, 0x40 },
+ { "CDO", 0x80, 0x80 },
+ { "PHASE_MASK", 0xe0, 0xe0 }
+};
+
+int
+ahd_scsisigo_print(u_int regvalue, u_int *cur_col, u_int wrap)
+{
+ return (ahd_print_register(SCSISIGO_parse_table, 17, "SCSISIGO",
+ 0x40, regvalue, cur_col, wrap));
+}
+
+int
+ahd_multargid_print(u_int regvalue, u_int *cur_col, u_int wrap)
+{
+ return (ahd_print_register(NULL, 0, "MULTARGID",
+ 0x40, regvalue, cur_col, wrap));
+}
+
+static ahd_reg_parse_entry_t SCSISIGI_parse_table[] = {
+ { "P_DATAOUT", 0x00, 0xe0 },
+ { "P_DATAOUT_DT", 0x20, 0xe0 },
+ { "P_DATAIN", 0x40, 0xe0 },
+ { "P_DATAIN_DT", 0x60, 0xe0 },
+ { "P_COMMAND", 0x80, 0xe0 },
+ { "P_MESGOUT", 0xa0, 0xe0 },
+ { "P_STATUS", 0xc0, 0xe0 },
+ { "P_MESGIN", 0xe0, 0xe0 },
+ { "ACKI", 0x01, 0x01 },
+ { "REQI", 0x02, 0x02 },
+ { "BSYI", 0x04, 0x04 },
+ { "SELI", 0x08, 0x08 },
+ { "ATNI", 0x10, 0x10 },
+ { "MSGI", 0x20, 0x20 },
+ { "IOI", 0x40, 0x40 },
+ { "CDI", 0x80, 0x80 },
+ { "PHASE_MASK", 0xe0, 0xe0 }
+};
+
+int
+ahd_scsisigi_print(u_int regvalue, u_int *cur_col, u_int wrap)
+{
+ return (ahd_print_register(SCSISIGI_parse_table, 17, "SCSISIGI",
+ 0x41, regvalue, cur_col, wrap));
+}
+
+static ahd_reg_parse_entry_t SCSIPHASE_parse_table[] = {
+ { "DATA_OUT_PHASE", 0x01, 0x03 },
+ { "DATA_IN_PHASE", 0x02, 0x03 },
+ { "DATA_PHASE_MASK", 0x03, 0x03 },
+ { "MSG_OUT_PHASE", 0x04, 0x04 },
+ { "MSG_IN_PHASE", 0x08, 0x08 },
+ { "COMMAND_PHASE", 0x10, 0x10 },
+ { "STATUS_PHASE", 0x20, 0x20 }
+};
+
+int
+ahd_scsiphase_print(u_int regvalue, u_int *cur_col, u_int wrap)
+{
+ return (ahd_print_register(SCSIPHASE_parse_table, 7, "SCSIPHASE",
+ 0x42, regvalue, cur_col, wrap));
+}
+
+int
+ahd_scsidat0_img_print(u_int regvalue, u_int *cur_col, u_int wrap)
+{
+ return (ahd_print_register(NULL, 0, "SCSIDAT0_IMG",
+ 0x43, regvalue, cur_col, wrap));
+}
+
+int
+ahd_scsidat_print(u_int regvalue, u_int *cur_col, u_int wrap)
+{
+ return (ahd_print_register(NULL, 0, "SCSIDAT",
+ 0x44, regvalue, cur_col, wrap));
+}
+
+int
+ahd_scsibus_print(u_int regvalue, u_int *cur_col, u_int wrap)
+{
+ return (ahd_print_register(NULL, 0, "SCSIBUS",
+ 0x46, regvalue, cur_col, wrap));
+}
+
+static ahd_reg_parse_entry_t TARGIDIN_parse_table[] = {
+ { "TARGID", 0x0f, 0x0f },
+ { "CLKOUT", 0x80, 0x80 }
+};
+
+int
+ahd_targidin_print(u_int regvalue, u_int *cur_col, u_int wrap)
+{
+ return (ahd_print_register(TARGIDIN_parse_table, 2, "TARGIDIN",
+ 0x48, regvalue, cur_col, wrap));
+}
+
+static ahd_reg_parse_entry_t SELID_parse_table[] = {
+ { "ONEBIT", 0x08, 0x08 },
+ { "SELID_MASK", 0xf0, 0xf0 }
+};
+
+int
+ahd_selid_print(u_int regvalue, u_int *cur_col, u_int wrap)
+{
+ return (ahd_print_register(SELID_parse_table, 2, "SELID",
+ 0x49, regvalue, cur_col, wrap));
+}
+
+static ahd_reg_parse_entry_t OPTIONMODE_parse_table[] = {
+ { "AUTO_MSGOUT_DE", 0x02, 0x02 },
+ { "ENDGFORMCHK", 0x04, 0x04 },
+ { "BUSFREEREV", 0x10, 0x10 },
+ { "BIASCANCTL", 0x20, 0x20 },
+ { "AUTOACKEN", 0x40, 0x40 },
+ { "BIOSCANCTL", 0x80, 0x80 },
+ { "OPTIONMODE_DEFAULTS",0x02, 0x02 }
+};
+
+int
+ahd_optionmode_print(u_int regvalue, u_int *cur_col, u_int wrap)
+{
+ return (ahd_print_register(OPTIONMODE_parse_table, 7, "OPTIONMODE",
+ 0x4a, regvalue, cur_col, wrap));
+}
+
+static ahd_reg_parse_entry_t SBLKCTL_parse_table[] = {
+ { "SELWIDE", 0x02, 0x02 },
+ { "ENAB20", 0x04, 0x04 },
+ { "ENAB40", 0x08, 0x08 },
+ { "DIAGLEDON", 0x40, 0x40 },
+ { "DIAGLEDEN", 0x80, 0x80 }
+};
+
+int
+ahd_sblkctl_print(u_int regvalue, u_int *cur_col, u_int wrap)
+{
+ return (ahd_print_register(SBLKCTL_parse_table, 5, "SBLKCTL",
+ 0x4a, regvalue, cur_col, wrap));
+}
+
+static ahd_reg_parse_entry_t SIMODE0_parse_table[] = {
+ { "ENARBDO", 0x01, 0x01 },
+ { "ENSPIORDY", 0x02, 0x02 },
+ { "ENOVERRUN", 0x04, 0x04 },
+ { "ENIOERR", 0x08, 0x08 },
+ { "ENSELINGO", 0x10, 0x10 },
+ { "ENSELDI", 0x20, 0x20 },
+ { "ENSELDO", 0x40, 0x40 }
+};
+
+int
+ahd_simode0_print(u_int regvalue, u_int *cur_col, u_int wrap)
+{
+ return (ahd_print_register(SIMODE0_parse_table, 7, "SIMODE0",
+ 0x4b, regvalue, cur_col, wrap));
+}
+
+static ahd_reg_parse_entry_t SSTAT0_parse_table[] = {
+ { "ARBDO", 0x01, 0x01 },
+ { "SPIORDY", 0x02, 0x02 },
+ { "OVERRUN", 0x04, 0x04 },
+ { "IOERR", 0x08, 0x08 },
+ { "SELINGO", 0x10, 0x10 },
+ { "SELDI", 0x20, 0x20 },
+ { "SELDO", 0x40, 0x40 },
+ { "TARGET", 0x80, 0x80 }
+};
+
+int
+ahd_sstat0_print(u_int regvalue, u_int *cur_col, u_int wrap)
+{
+ return (ahd_print_register(SSTAT0_parse_table, 8, "SSTAT0",
+ 0x4b, regvalue, cur_col, wrap));
+}
+
+static ahd_reg_parse_entry_t CLRSINT0_parse_table[] = {
+ { "CLRARBDO", 0x01, 0x01 },
+ { "CLRSPIORDY", 0x02, 0x02 },
+ { "CLROVERRUN", 0x04, 0x04 },
+ { "CLRIOERR", 0x08, 0x08 },
+ { "CLRSELINGO", 0x10, 0x10 },
+ { "CLRSELDI", 0x20, 0x20 },
+ { "CLRSELDO", 0x40, 0x40 }
+};
+
+int
+ahd_clrsint0_print(u_int regvalue, u_int *cur_col, u_int wrap)
+{
+ return (ahd_print_register(CLRSINT0_parse_table, 7, "CLRSINT0",
+ 0x4b, regvalue, cur_col, wrap));
+}
+
+static ahd_reg_parse_entry_t SSTAT1_parse_table[] = {
+ { "REQINIT", 0x01, 0x01 },
+ { "STRB2FAST", 0x02, 0x02 },
+ { "SCSIPERR", 0x04, 0x04 },
+ { "BUSFREE", 0x08, 0x08 },
+ { "PHASEMIS", 0x10, 0x10 },
+ { "SCSIRSTI", 0x20, 0x20 },
+ { "ATNTARG", 0x40, 0x40 },
+ { "SELTO", 0x80, 0x80 }
+};
+
+int
+ahd_sstat1_print(u_int regvalue, u_int *cur_col, u_int wrap)
+{
+ return (ahd_print_register(SSTAT1_parse_table, 8, "SSTAT1",
+ 0x4c, regvalue, cur_col, wrap));
+}
+
+static ahd_reg_parse_entry_t CLRSINT1_parse_table[] = {
+ { "CLRREQINIT", 0x01, 0x01 },
+ { "CLRSTRB2FAST", 0x02, 0x02 },
+ { "CLRSCSIPERR", 0x04, 0x04 },
+ { "CLRBUSFREE", 0x08, 0x08 },
+ { "CLRSCSIRSTI", 0x20, 0x20 },
+ { "CLRATNO", 0x40, 0x40 },
+ { "CLRSELTIMEO", 0x80, 0x80 }
+};
+
+int
+ahd_clrsint1_print(u_int regvalue, u_int *cur_col, u_int wrap)
+{
+ return (ahd_print_register(CLRSINT1_parse_table, 7, "CLRSINT1",
+ 0x4c, regvalue, cur_col, wrap));
+}
+
+static ahd_reg_parse_entry_t SSTAT2_parse_table[] = {
+ { "BUSFREE_LQO", 0x40, 0xc0 },
+ { "BUSFREE_DFF0", 0x80, 0xc0 },
+ { "BUSFREE_DFF1", 0xc0, 0xc0 },
+ { "DMADONE", 0x01, 0x01 },
+ { "SDONE", 0x02, 0x02 },
+ { "WIDE_RES", 0x04, 0x04 },
+ { "BSYX", 0x08, 0x08 },
+ { "EXP_ACTIVE", 0x10, 0x10 },
+ { "NONPACKREQ", 0x20, 0x20 },
+ { "BUSFREETIME", 0xc0, 0xc0 }
+};
+
+int
+ahd_sstat2_print(u_int regvalue, u_int *cur_col, u_int wrap)
+{
+ return (ahd_print_register(SSTAT2_parse_table, 10, "SSTAT2",
+ 0x4d, regvalue, cur_col, wrap));
+}
+
+static ahd_reg_parse_entry_t CLRSINT2_parse_table[] = {
+ { "CLRDMADONE", 0x01, 0x01 },
+ { "CLRSDONE", 0x02, 0x02 },
+ { "CLRWIDE_RES", 0x04, 0x04 },
+ { "CLRNONPACKREQ", 0x20, 0x20 }
+};
+
+int
+ahd_clrsint2_print(u_int regvalue, u_int *cur_col, u_int wrap)
+{
+ return (ahd_print_register(CLRSINT2_parse_table, 4, "CLRSINT2",
+ 0x4d, regvalue, cur_col, wrap));
+}
+
+static ahd_reg_parse_entry_t SIMODE2_parse_table[] = {
+ { "ENDMADONE", 0x01, 0x01 },
+ { "ENSDONE", 0x02, 0x02 },
+ { "ENWIDE_RES", 0x04, 0x04 }
+};
+
+int
+ahd_simode2_print(u_int regvalue, u_int *cur_col, u_int wrap)
+{
+ return (ahd_print_register(SIMODE2_parse_table, 3, "SIMODE2",
+ 0x4d, regvalue, cur_col, wrap));
+}
+
+static ahd_reg_parse_entry_t PERRDIAG_parse_table[] = {
+ { "DTERR", 0x01, 0x01 },
+ { "DGFORMERR", 0x02, 0x02 },
+ { "CRCERR", 0x04, 0x04 },
+ { "AIPERR", 0x08, 0x08 },
+ { "PARITYERR", 0x10, 0x10 },
+ { "PREVPHASE", 0x20, 0x20 },
+ { "HIPERR", 0x40, 0x40 },
+ { "HIZERO", 0x80, 0x80 }
+};
+
+int
+ahd_perrdiag_print(u_int regvalue, u_int *cur_col, u_int wrap)
+{
+ return (ahd_print_register(PERRDIAG_parse_table, 8, "PERRDIAG",
+ 0x4e, regvalue, cur_col, wrap));
+}
+
+int
+ahd_lqistate_print(u_int regvalue, u_int *cur_col, u_int wrap)
+{
+ return (ahd_print_register(NULL, 0, "LQISTATE",
+ 0x4e, regvalue, cur_col, wrap));
+}
+
+int
+ahd_soffcnt_print(u_int regvalue, u_int *cur_col, u_int wrap)
+{
+ return (ahd_print_register(NULL, 0, "SOFFCNT",
+ 0x4f, regvalue, cur_col, wrap));
+}
+
+int
+ahd_lqostate_print(u_int regvalue, u_int *cur_col, u_int wrap)
+{
+ return (ahd_print_register(NULL, 0, "LQOSTATE",
+ 0x4f, regvalue, cur_col, wrap));
+}
+
+static ahd_reg_parse_entry_t LQISTAT0_parse_table[] = {
+ { "LQIATNCMD", 0x01, 0x01 },
+ { "LQIATNLQ", 0x02, 0x02 },
+ { "LQIBADLQT", 0x04, 0x04 },
+ { "LQICRCT2", 0x08, 0x08 },
+ { "LQICRCT1", 0x10, 0x10 },
+ { "LQIATNQAS", 0x20, 0x20 }
+};
+
+int
+ahd_lqistat0_print(u_int regvalue, u_int *cur_col, u_int wrap)
+{
+ return (ahd_print_register(LQISTAT0_parse_table, 6, "LQISTAT0",
+ 0x50, regvalue, cur_col, wrap));
+}
+
+static ahd_reg_parse_entry_t CLRLQIINT0_parse_table[] = {
+ { "CLRLQIATNCMD", 0x01, 0x01 },
+ { "CLRLQIATNLQ", 0x02, 0x02 },
+ { "CLRLQIBADLQT", 0x04, 0x04 },
+ { "CLRLQICRCT2", 0x08, 0x08 },
+ { "CLRLQICRCT1", 0x10, 0x10 },
+ { "CLRLQIATNQAS", 0x20, 0x20 }
+};
+
+int
+ahd_clrlqiint0_print(u_int regvalue, u_int *cur_col, u_int wrap)
+{
+ return (ahd_print_register(CLRLQIINT0_parse_table, 6, "CLRLQIINT0",
+ 0x50, regvalue, cur_col, wrap));
+}
+
+static ahd_reg_parse_entry_t LQIMODE0_parse_table[] = {
+ { "ENLQIATNCMD", 0x01, 0x01 },
+ { "ENLQIATNLQ", 0x02, 0x02 },
+ { "ENLQIBADLQT", 0x04, 0x04 },
+ { "ENLQICRCT2", 0x08, 0x08 },
+ { "ENLQICRCT1", 0x10, 0x10 },
+ { "ENLQIATNQASK", 0x20, 0x20 }
+};
+
+int
+ahd_lqimode0_print(u_int regvalue, u_int *cur_col, u_int wrap)
+{
+ return (ahd_print_register(LQIMODE0_parse_table, 6, "LQIMODE0",
+ 0x50, regvalue, cur_col, wrap));
+}
+
+static ahd_reg_parse_entry_t LQISTAT1_parse_table[] = {
+ { "LQIOVERI_NLQ", 0x01, 0x01 },
+ { "LQIOVERI_LQ", 0x02, 0x02 },
+ { "LQIBADLQI", 0x04, 0x04 },
+ { "LQICRCI_NLQ", 0x08, 0x08 },
+ { "LQICRCI_LQ", 0x10, 0x10 },
+ { "LQIABORT", 0x20, 0x20 },
+ { "LQIPHASE_NLQ", 0x40, 0x40 },
+ { "LQIPHASE_LQ", 0x80, 0x80 }
+};
+
+int
+ahd_lqistat1_print(u_int regvalue, u_int *cur_col, u_int wrap)
+{
+ return (ahd_print_register(LQISTAT1_parse_table, 8, "LQISTAT1",
+ 0x51, regvalue, cur_col, wrap));
+}
+
+static ahd_reg_parse_entry_t CLRLQIINT1_parse_table[] = {
+ { "CLRLQIOVERI_NLQ", 0x01, 0x01 },
+ { "CLRLQIOVERI_LQ", 0x02, 0x02 },
+ { "CLRLQIBADLQI", 0x04, 0x04 },
+ { "CLRLQICRCI_NLQ", 0x08, 0x08 },
+ { "CLRLQICRCI_LQ", 0x10, 0x10 },
+ { "CLRLIQABORT", 0x20, 0x20 },
+ { "CLRLQIPHASE_NLQ", 0x40, 0x40 },
+ { "CLRLQIPHASE_LQ", 0x80, 0x80 }
+};
+
+int
+ahd_clrlqiint1_print(u_int regvalue, u_int *cur_col, u_int wrap)
+{
+ return (ahd_print_register(CLRLQIINT1_parse_table, 8, "CLRLQIINT1",
+ 0x51, regvalue, cur_col, wrap));
+}
+
+static ahd_reg_parse_entry_t LQIMODE1_parse_table[] = {
+ { "ENLQIOVERI_NLQ", 0x01, 0x01 },
+ { "ENLQIOVERI_LQ", 0x02, 0x02 },
+ { "ENLQIBADLQI", 0x04, 0x04 },
+ { "ENLQICRCI_NLQ", 0x08, 0x08 },
+ { "ENLQICRCI_LQ", 0x10, 0x10 },
+ { "ENLIQABORT", 0x20, 0x20 },
+ { "ENLQIPHASE_NLQ", 0x40, 0x40 },
+ { "ENLQIPHASE_LQ", 0x80, 0x80 }
+};
+
+int
+ahd_lqimode1_print(u_int regvalue, u_int *cur_col, u_int wrap)
+{
+ return (ahd_print_register(LQIMODE1_parse_table, 8, "LQIMODE1",
+ 0x51, regvalue, cur_col, wrap));
+}
+
+static ahd_reg_parse_entry_t LQISTAT2_parse_table[] = {
+ { "LQIGSAVAIL", 0x01, 0x01 },
+ { "LQISTOPCMD", 0x02, 0x02 },
+ { "LQISTOPLQ", 0x04, 0x04 },
+ { "LQISTOPPKT", 0x08, 0x08 },
+ { "LQIWAITFIFO", 0x10, 0x10 },
+ { "LQIWORKONLQ", 0x20, 0x20 },
+ { "LQIPHASE_OUTPKT", 0x40, 0x40 },
+ { "PACKETIZED", 0x80, 0x80 }
+};
+
+int
+ahd_lqistat2_print(u_int regvalue, u_int *cur_col, u_int wrap)
+{
+ return (ahd_print_register(LQISTAT2_parse_table, 8, "LQISTAT2",
+ 0x52, regvalue, cur_col, wrap));
+}
+
+static ahd_reg_parse_entry_t SSTAT3_parse_table[] = {
+ { "OSRAMPERR", 0x01, 0x01 },
+ { "NTRAMPERR", 0x02, 0x02 }
+};
+
+int
+ahd_sstat3_print(u_int regvalue, u_int *cur_col, u_int wrap)
+{
+ return (ahd_print_register(SSTAT3_parse_table, 2, "SSTAT3",
+ 0x53, regvalue, cur_col, wrap));
+}
+
+static ahd_reg_parse_entry_t CLRSINT3_parse_table[] = {
+ { "CLROSRAMPERR", 0x01, 0x01 },
+ { "CLRNTRAMPERR", 0x02, 0x02 }
+};
+
+int
+ahd_clrsint3_print(u_int regvalue, u_int *cur_col, u_int wrap)
+{
+ return (ahd_print_register(CLRSINT3_parse_table, 2, "CLRSINT3",
+ 0x53, regvalue, cur_col, wrap));
+}
+
+static ahd_reg_parse_entry_t SIMODE3_parse_table[] = {
+ { "ENOSRAMPERR", 0x01, 0x01 },
+ { "ENNTRAMPERR", 0x02, 0x02 }
+};
+
+int
+ahd_simode3_print(u_int regvalue, u_int *cur_col, u_int wrap)
+{
+ return (ahd_print_register(SIMODE3_parse_table, 2, "SIMODE3",
+ 0x53, regvalue, cur_col, wrap));
+}
+
+static ahd_reg_parse_entry_t LQOMODE0_parse_table[] = {
+ { "ENLQOTCRC", 0x01, 0x01 },
+ { "ENLQOATNPKT", 0x02, 0x02 },
+ { "ENLQOATNLQ", 0x04, 0x04 },
+ { "ENLQOSTOPT2", 0x08, 0x08 },
+ { "ENLQOTARGSCBPERR", 0x10, 0x10 }
+};
+
+int
+ahd_lqomode0_print(u_int regvalue, u_int *cur_col, u_int wrap)
+{
+ return (ahd_print_register(LQOMODE0_parse_table, 5, "LQOMODE0",
+ 0x54, regvalue, cur_col, wrap));
+}
+
+static ahd_reg_parse_entry_t LQOSTAT0_parse_table[] = {
+ { "LQOTCRC", 0x01, 0x01 },
+ { "LQOATNPKT", 0x02, 0x02 },
+ { "LQOATNLQ", 0x04, 0x04 },
+ { "LQOSTOPT2", 0x08, 0x08 },
+ { "LQOTARGSCBPERR", 0x10, 0x10 }
+};
+
+int
+ahd_lqostat0_print(u_int regvalue, u_int *cur_col, u_int wrap)
+{
+ return (ahd_print_register(LQOSTAT0_parse_table, 5, "LQOSTAT0",
+ 0x54, regvalue, cur_col, wrap));
+}
+
+static ahd_reg_parse_entry_t CLRLQOINT0_parse_table[] = {
+ { "CLRLQOTCRC", 0x01, 0x01 },
+ { "CLRLQOATNPKT", 0x02, 0x02 },
+ { "CLRLQOATNLQ", 0x04, 0x04 },
+ { "CLRLQOSTOPT2", 0x08, 0x08 },
+ { "CLRLQOTARGSCBPERR", 0x10, 0x10 }
+};
+
+int
+ahd_clrlqoint0_print(u_int regvalue, u_int *cur_col, u_int wrap)
+{
+ return (ahd_print_register(CLRLQOINT0_parse_table, 5, "CLRLQOINT0",
+ 0x54, regvalue, cur_col, wrap));
+}
+
+static ahd_reg_parse_entry_t LQOMODE1_parse_table[] = {
+ { "ENLQOPHACHGINPKT", 0x01, 0x01 },
+ { "ENLQOBUSFREE", 0x02, 0x02 },
+ { "ENLQOBADQAS", 0x04, 0x04 },
+ { "ENLQOSTOPI2", 0x08, 0x08 },
+ { "ENLQOINITSCBPERR", 0x10, 0x10 }
+};
+
+int
+ahd_lqomode1_print(u_int regvalue, u_int *cur_col, u_int wrap)
+{
+ return (ahd_print_register(LQOMODE1_parse_table, 5, "LQOMODE1",
+ 0x55, regvalue, cur_col, wrap));
+}
+
+static ahd_reg_parse_entry_t LQOSTAT1_parse_table[] = {
+ { "LQOPHACHGINPKT", 0x01, 0x01 },
+ { "LQOBUSFREE", 0x02, 0x02 },
+ { "LQOBADQAS", 0x04, 0x04 },
+ { "LQOSTOPI2", 0x08, 0x08 },
+ { "LQOINITSCBPERR", 0x10, 0x10 }
+};
+
+int
+ahd_lqostat1_print(u_int regvalue, u_int *cur_col, u_int wrap)
+{
+ return (ahd_print_register(LQOSTAT1_parse_table, 5, "LQOSTAT1",
+ 0x55, regvalue, cur_col, wrap));
+}
+
+static ahd_reg_parse_entry_t CLRLQOINT1_parse_table[] = {
+ { "CLRLQOPHACHGINPKT", 0x01, 0x01 },
+ { "CLRLQOBUSFREE", 0x02, 0x02 },
+ { "CLRLQOBADQAS", 0x04, 0x04 },
+ { "CLRLQOSTOPI2", 0x08, 0x08 },
+ { "CLRLQOINITSCBPERR", 0x10, 0x10 }
+};
+
+int
+ahd_clrlqoint1_print(u_int regvalue, u_int *cur_col, u_int wrap)
+{
+ return (ahd_print_register(CLRLQOINT1_parse_table, 5, "CLRLQOINT1",
+ 0x55, regvalue, cur_col, wrap));
+}
+
+int
+ahd_os_space_cnt_print(u_int regvalue, u_int *cur_col, u_int wrap)
+{
+ return (ahd_print_register(NULL, 0, "OS_SPACE_CNT",
+ 0x56, regvalue, cur_col, wrap));
+}
+
+static ahd_reg_parse_entry_t LQOSTAT2_parse_table[] = {
+ { "LQOSTOP0", 0x01, 0x01 },
+ { "LQOPHACHGOUTPKT", 0x02, 0x02 },
+ { "LQOWAITFIFO", 0x10, 0x10 },
+ { "LQOPKT", 0xe0, 0xe0 }
+};
+
+int
+ahd_lqostat2_print(u_int regvalue, u_int *cur_col, u_int wrap)
+{
+ return (ahd_print_register(LQOSTAT2_parse_table, 4, "LQOSTAT2",
+ 0x56, regvalue, cur_col, wrap));
+}
+
+static ahd_reg_parse_entry_t SIMODE1_parse_table[] = {
+ { "ENREQINIT", 0x01, 0x01 },
+ { "ENSTRB2FAST", 0x02, 0x02 },
+ { "ENSCSIPERR", 0x04, 0x04 },
+ { "ENBUSFREE", 0x08, 0x08 },
+ { "ENPHASEMIS", 0x10, 0x10 },
+ { "ENSCSIRST", 0x20, 0x20 },
+ { "ENATNTARG", 0x40, 0x40 },
+ { "ENSELTIMO", 0x80, 0x80 }
+};
+
+int
+ahd_simode1_print(u_int regvalue, u_int *cur_col, u_int wrap)
+{
+ return (ahd_print_register(SIMODE1_parse_table, 8, "SIMODE1",
+ 0x57, regvalue, cur_col, wrap));
+}
+
+int
+ahd_gsfifo_print(u_int regvalue, u_int *cur_col, u_int wrap)
+{
+ return (ahd_print_register(NULL, 0, "GSFIFO",
+ 0x58, regvalue, cur_col, wrap));
+}
+
+static ahd_reg_parse_entry_t DFFSXFRCTL_parse_table[] = {
+ { "RSTCHN", 0x01, 0x01 },
+ { "CLRCHN", 0x02, 0x02 },
+ { "CLRSHCNT", 0x04, 0x04 },
+ { "DFFBITBUCKET", 0x08, 0x08 }
+};
+
+int
+ahd_dffsxfrctl_print(u_int regvalue, u_int *cur_col, u_int wrap)
+{
+ return (ahd_print_register(DFFSXFRCTL_parse_table, 4, "DFFSXFRCTL",
+ 0x5a, regvalue, cur_col, wrap));
+}
+
+int
+ahd_nextscb_print(u_int regvalue, u_int *cur_col, u_int wrap)
+{
+ return (ahd_print_register(NULL, 0, "NEXTSCB",
+ 0x5a, regvalue, cur_col, wrap));
+}
+
+static ahd_reg_parse_entry_t LQOSCSCTL_parse_table[] = {
+ { "LQONOCHKOVER", 0x01, 0x01 },
+ { "LQOH2A_VERSION", 0x80, 0x80 }
+};
+
+int
+ahd_lqoscsctl_print(u_int regvalue, u_int *cur_col, u_int wrap)
+{
+ return (ahd_print_register(LQOSCSCTL_parse_table, 2, "LQOSCSCTL",
+ 0x5a, regvalue, cur_col, wrap));
+}
+
+static ahd_reg_parse_entry_t SEQINTSRC_parse_table[] = {
+ { "CFG4TCMD", 0x01, 0x01 },
+ { "CFG4ICMD", 0x02, 0x02 },
+ { "CFG4TSTAT", 0x04, 0x04 },
+ { "CFG4ISTAT", 0x08, 0x08 },
+ { "CFG4DATA", 0x10, 0x10 },
+ { "SAVEPTRS", 0x20, 0x20 },
+ { "CTXTDONE", 0x40, 0x40 }
+};
+
+int
+ahd_seqintsrc_print(u_int regvalue, u_int *cur_col, u_int wrap)
+{
+ return (ahd_print_register(SEQINTSRC_parse_table, 7, "SEQINTSRC",
+ 0x5b, regvalue, cur_col, wrap));
+}
+
+static ahd_reg_parse_entry_t CLRSEQINTSRC_parse_table[] = {
+ { "CLRCFG4TCMD", 0x01, 0x01 },
+ { "CLRCFG4ICMD", 0x02, 0x02 },
+ { "CLRCFG4TSTAT", 0x04, 0x04 },
+ { "CLRCFG4ISTAT", 0x08, 0x08 },
+ { "CLRCFG4DATA", 0x10, 0x10 },
+ { "CLRSAVEPTRS", 0x20, 0x20 },
+ { "CLRCTXTDONE", 0x40, 0x40 }
+};
+
+int
+ahd_clrseqintsrc_print(u_int regvalue, u_int *cur_col, u_int wrap)
+{
+ return (ahd_print_register(CLRSEQINTSRC_parse_table, 7, "CLRSEQINTSRC",
+ 0x5b, regvalue, cur_col, wrap));
+}
+
+int
+ahd_currscb_print(u_int regvalue, u_int *cur_col, u_int wrap)
+{
+ return (ahd_print_register(NULL, 0, "CURRSCB",
+ 0x5c, regvalue, cur_col, wrap));
+}
+
+static ahd_reg_parse_entry_t SEQIMODE_parse_table[] = {
+ { "ENCFG4TCMD", 0x01, 0x01 },
+ { "ENCFG4ICMD", 0x02, 0x02 },
+ { "ENCFG4TSTAT", 0x04, 0x04 },
+ { "ENCFG4ISTAT", 0x08, 0x08 },
+ { "ENCFG4DATA", 0x10, 0x10 },
+ { "ENSAVEPTRS", 0x20, 0x20 },
+ { "ENCTXTDONE", 0x40, 0x40 }
+};
+
+int
+ahd_seqimode_print(u_int regvalue, u_int *cur_col, u_int wrap)
+{
+ return (ahd_print_register(SEQIMODE_parse_table, 7, "SEQIMODE",
+ 0x5c, regvalue, cur_col, wrap));
+}
+
+static ahd_reg_parse_entry_t MDFFSTAT_parse_table[] = {
+ { "FIFOFREE", 0x01, 0x01 },
+ { "DATAINFIFO", 0x02, 0x02 },
+ { "DLZERO", 0x04, 0x04 },
+ { "SHVALID", 0x08, 0x08 },
+ { "LASTSDONE", 0x10, 0x10 },
+ { "SHCNTMINUS1", 0x20, 0x20 },
+ { "SHCNTNEGATIVE", 0x40, 0x40 }
+};
+
+int
+ahd_mdffstat_print(u_int regvalue, u_int *cur_col, u_int wrap)
+{
+ return (ahd_print_register(MDFFSTAT_parse_table, 7, "MDFFSTAT",
+ 0x5d, regvalue, cur_col, wrap));
+}
+
+static ahd_reg_parse_entry_t CRCCONTROL_parse_table[] = {
+ { "CRCVALCHKEN", 0x40, 0x40 }
+};
+
+int
+ahd_crccontrol_print(u_int regvalue, u_int *cur_col, u_int wrap)
+{
+ return (ahd_print_register(CRCCONTROL_parse_table, 1, "CRCCONTROL",
+ 0x5d, regvalue, cur_col, wrap));
+}
+
+static ahd_reg_parse_entry_t SCSITEST_parse_table[] = {
+ { "SEL_TXPLL_DEBUG", 0x04, 0x04 },
+ { "CNTRTEST", 0x08, 0x08 }
+};
+
+int
+ahd_scsitest_print(u_int regvalue, u_int *cur_col, u_int wrap)
+{
+ return (ahd_print_register(SCSITEST_parse_table, 2, "SCSITEST",
+ 0x5e, regvalue, cur_col, wrap));
+}
+
+int
+ahd_dfftag_print(u_int regvalue, u_int *cur_col, u_int wrap)
+{
+ return (ahd_print_register(NULL, 0, "DFFTAG",
+ 0x5e, regvalue, cur_col, wrap));
+}
+
+int
+ahd_lastscb_print(u_int regvalue, u_int *cur_col, u_int wrap)
+{
+ return (ahd_print_register(NULL, 0, "LASTSCB",
+ 0x5e, regvalue, cur_col, wrap));
+}
+
+static ahd_reg_parse_entry_t IOPDNCTL_parse_table[] = {
+ { "PDN_DIFFSENSE", 0x01, 0x01 },
+ { "PDN_IDIST", 0x04, 0x04 },
+ { "DISABLE_OE", 0x80, 0x80 }
+};
+
+int
+ahd_iopdnctl_print(u_int regvalue, u_int *cur_col, u_int wrap)
+{
+ return (ahd_print_register(IOPDNCTL_parse_table, 3, "IOPDNCTL",
+ 0x5f, regvalue, cur_col, wrap));
+}
+
+int
+ahd_negoaddr_print(u_int regvalue, u_int *cur_col, u_int wrap)
+{
+ return (ahd_print_register(NULL, 0, "NEGOADDR",
+ 0x60, regvalue, cur_col, wrap));
+}
+
+int
+ahd_shaddr_print(u_int regvalue, u_int *cur_col, u_int wrap)
+{
+ return (ahd_print_register(NULL, 0, "SHADDR",
+ 0x60, regvalue, cur_col, wrap));
+}
+
+int
+ahd_dgrpcrci_print(u_int regvalue, u_int *cur_col, u_int wrap)
+{
+ return (ahd_print_register(NULL, 0, "DGRPCRCI",
+ 0x60, regvalue, cur_col, wrap));
+}
+
+int
+ahd_negperiod_print(u_int regvalue, u_int *cur_col, u_int wrap)
+{
+ return (ahd_print_register(NULL, 0, "NEGPERIOD",
+ 0x61, regvalue, cur_col, wrap));
+}
+
+int
+ahd_packcrci_print(u_int regvalue, u_int *cur_col, u_int wrap)
+{
+ return (ahd_print_register(NULL, 0, "PACKCRCI",
+ 0x62, regvalue, cur_col, wrap));
+}
+
+int
+ahd_negoffset_print(u_int regvalue, u_int *cur_col, u_int wrap)
+{
+ return (ahd_print_register(NULL, 0, "NEGOFFSET",
+ 0x62, regvalue, cur_col, wrap));
+}
+
+static ahd_reg_parse_entry_t NEGPPROPTS_parse_table[] = {
+ { "PPROPT_IUT", 0x01, 0x01 },
+ { "PPROPT_DT", 0x02, 0x02 },
+ { "PPROPT_QAS", 0x04, 0x04 },
+ { "PPROPT_PACE", 0x08, 0x08 }
+};
+
+int
+ahd_negppropts_print(u_int regvalue, u_int *cur_col, u_int wrap)
+{
+ return (ahd_print_register(NEGPPROPTS_parse_table, 4, "NEGPPROPTS",
+ 0x63, regvalue, cur_col, wrap));
+}
+
+static ahd_reg_parse_entry_t NEGCONOPTS_parse_table[] = {
+ { "WIDEXFER", 0x01, 0x01 },
+ { "ENAUTOATNO", 0x02, 0x02 },
+ { "ENAUTOATNI", 0x04, 0x04 },
+ { "ENSLOWCRC", 0x08, 0x08 },
+ { "RTI_OVRDTRN", 0x10, 0x10 },
+ { "RTI_WRTDIS", 0x20, 0x20 },
+ { "ENSNAPSHOT", 0x40, 0x40 }
+};
+
+int
+ahd_negconopts_print(u_int regvalue, u_int *cur_col, u_int wrap)
+{
+ return (ahd_print_register(NEGCONOPTS_parse_table, 7, "NEGCONOPTS",
+ 0x64, regvalue, cur_col, wrap));
+}
+
+int
+ahd_annexcol_print(u_int regvalue, u_int *cur_col, u_int wrap)
+{
+ return (ahd_print_register(NULL, 0, "ANNEXCOL",
+ 0x65, regvalue, cur_col, wrap));
+}
+
+int
+ahd_annexdat_print(u_int regvalue, u_int *cur_col, u_int wrap)
+{
+ return (ahd_print_register(NULL, 0, "ANNEXDAT",
+ 0x66, regvalue, cur_col, wrap));
+}
+
+static ahd_reg_parse_entry_t SCSCHKN_parse_table[] = {
+ { "LSTSGCLRDIS", 0x01, 0x01 },
+ { "SHVALIDSTDIS", 0x02, 0x02 },
+ { "DFFACTCLR", 0x04, 0x04 },
+ { "SDONEMSKDIS", 0x08, 0x08 },
+ { "WIDERESEN", 0x10, 0x10 },
+ { "CURRFIFODEF", 0x20, 0x20 },
+ { "STSELSKIDDIS", 0x40, 0x40 }
+};
+
+int
+ahd_scschkn_print(u_int regvalue, u_int *cur_col, u_int wrap)
+{
+ return (ahd_print_register(SCSCHKN_parse_table, 7, "SCSCHKN",
+ 0x66, regvalue, cur_col, wrap));
+}
+
+int
+ahd_iownid_print(u_int regvalue, u_int *cur_col, u_int wrap)
+{
+ return (ahd_print_register(NULL, 0, "IOWNID",
+ 0x67, regvalue, cur_col, wrap));
+}
+
+int
+ahd_shcnt_print(u_int regvalue, u_int *cur_col, u_int wrap)
+{
+ return (ahd_print_register(NULL, 0, "SHCNT",
+ 0x68, regvalue, cur_col, wrap));
+}
+
+static ahd_reg_parse_entry_t PLL960CTL0_parse_table[] = {
+ { "PLL_ENFBM", 0x01, 0x01 },
+ { "PLL_DLPF", 0x02, 0x02 },
+ { "PLL_ENLPF", 0x04, 0x04 },
+ { "PLL_ENLUD", 0x08, 0x08 },
+ { "PLL_NS", 0x30, 0x30 },
+ { "PLL_PWDN", 0x40, 0x40 },
+ { "PLL_VCOSEL", 0x80, 0x80 }
+};
+
+int
+ahd_pll960ctl0_print(u_int regvalue, u_int *cur_col, u_int wrap)
+{
+ return (ahd_print_register(PLL960CTL0_parse_table, 7, "PLL960CTL0",
+ 0x68, regvalue, cur_col, wrap));
+}
+
+static ahd_reg_parse_entry_t PLL960CTL1_parse_table[] = {
+ { "PLL_RST", 0x01, 0x01 },
+ { "PLL_CNTCLR", 0x40, 0x40 },
+ { "PLL_CNTEN", 0x80, 0x80 }
+};
+
+int
+ahd_pll960ctl1_print(u_int regvalue, u_int *cur_col, u_int wrap)
+{
+ return (ahd_print_register(PLL960CTL1_parse_table, 3, "PLL960CTL1",
+ 0x69, regvalue, cur_col, wrap));
+}
+
+int
+ahd_townid_print(u_int regvalue, u_int *cur_col, u_int wrap)
+{
+ return (ahd_print_register(NULL, 0, "TOWNID",
+ 0x69, regvalue, cur_col, wrap));
+}
+
+int
+ahd_xsig_print(u_int regvalue, u_int *cur_col, u_int wrap)
+{
+ return (ahd_print_register(NULL, 0, "XSIG",
+ 0x6a, regvalue, cur_col, wrap));
+}
+
+int
+ahd_pll960cnt0_print(u_int regvalue, u_int *cur_col, u_int wrap)
+{
+ return (ahd_print_register(NULL, 0, "PLL960CNT0",
+ 0x6a, regvalue, cur_col, wrap));
+}
+
+int
+ahd_seloid_print(u_int regvalue, u_int *cur_col, u_int wrap)
+{
+ return (ahd_print_register(NULL, 0, "SELOID",
+ 0x6b, regvalue, cur_col, wrap));
+}
+
+int
+ahd_fairness_print(u_int regvalue, u_int *cur_col, u_int wrap)
+{
+ return (ahd_print_register(NULL, 0, "FAIRNESS",
+ 0x6c, regvalue, cur_col, wrap));
+}
+
+static ahd_reg_parse_entry_t PLL400CTL0_parse_table[] = {
+ { "PLL_ENFBM", 0x01, 0x01 },
+ { "PLL_DLPF", 0x02, 0x02 },
+ { "PLL_ENLPF", 0x04, 0x04 },
+ { "PLL_ENLUD", 0x08, 0x08 },
+ { "PLL_NS", 0x30, 0x30 },
+ { "PLL_PWDN", 0x40, 0x40 },
+ { "PLL_VCOSEL", 0x80, 0x80 }
+};
+
+int
+ahd_pll400ctl0_print(u_int regvalue, u_int *cur_col, u_int wrap)
+{
+ return (ahd_print_register(PLL400CTL0_parse_table, 7, "PLL400CTL0",
+ 0x6c, regvalue, cur_col, wrap));
+}
+
+static ahd_reg_parse_entry_t PLL400CTL1_parse_table[] = {
+ { "PLL_RST", 0x01, 0x01 },
+ { "PLL_CNTCLR", 0x40, 0x40 },
+ { "PLL_CNTEN", 0x80, 0x80 }
+};
+
+int
+ahd_pll400ctl1_print(u_int regvalue, u_int *cur_col, u_int wrap)
+{
+ return (ahd_print_register(PLL400CTL1_parse_table, 3, "PLL400CTL1",
+ 0x6d, regvalue, cur_col, wrap));
+}
+
+int
+ahd_pll400cnt0_print(u_int regvalue, u_int *cur_col, u_int wrap)
+{
+ return (ahd_print_register(NULL, 0, "PLL400CNT0",
+ 0x6e, regvalue, cur_col, wrap));
+}
+
+int
+ahd_unfairness_print(u_int regvalue, u_int *cur_col, u_int wrap)
+{
+ return (ahd_print_register(NULL, 0, "UNFAIRNESS",
+ 0x6e, regvalue, cur_col, wrap));
+}
+
+int
+ahd_hodmaadr_print(u_int regvalue, u_int *cur_col, u_int wrap)
+{
+ return (ahd_print_register(NULL, 0, "HODMAADR",
+ 0x70, regvalue, cur_col, wrap));
+}
+
+int
+ahd_haddr_print(u_int regvalue, u_int *cur_col, u_int wrap)
+{
+ return (ahd_print_register(NULL, 0, "HADDR",
+ 0x70, regvalue, cur_col, wrap));
+}
+
+static ahd_reg_parse_entry_t PLLDELAY_parse_table[] = {
+ { "SPLIT_DROP_REQ", 0x80, 0x80 }
+};
+
+int
+ahd_plldelay_print(u_int regvalue, u_int *cur_col, u_int wrap)
+{
+ return (ahd_print_register(PLLDELAY_parse_table, 1, "PLLDELAY",
+ 0x70, regvalue, cur_col, wrap));
+}
+
+int
+ahd_hcnt_print(u_int regvalue, u_int *cur_col, u_int wrap)
+{
+ return (ahd_print_register(NULL, 0, "HCNT",
+ 0x78, regvalue, cur_col, wrap));
+}
+
+int
+ahd_hodmacnt_print(u_int regvalue, u_int *cur_col, u_int wrap)
+{
+ return (ahd_print_register(NULL, 0, "HODMACNT",
+ 0x78, regvalue, cur_col, wrap));
+}
+
+int
+ahd_hodmaen_print(u_int regvalue, u_int *cur_col, u_int wrap)
+{
+ return (ahd_print_register(NULL, 0, "HODMAEN",
+ 0x7a, regvalue, cur_col, wrap));
+}
+
+int
+ahd_scbhaddr_print(u_int regvalue, u_int *cur_col, u_int wrap)
+{
+ return (ahd_print_register(NULL, 0, "SCBHADDR",
+ 0x7c, regvalue, cur_col, wrap));
+}
+
+int
+ahd_sghaddr_print(u_int regvalue, u_int *cur_col, u_int wrap)
+{
+ return (ahd_print_register(NULL, 0, "SGHADDR",
+ 0x7c, regvalue, cur_col, wrap));
+}
+
+int
+ahd_scbhcnt_print(u_int regvalue, u_int *cur_col, u_int wrap)
+{
+ return (ahd_print_register(NULL, 0, "SCBHCNT",
+ 0x84, regvalue, cur_col, wrap));
+}
+
+int
+ahd_sghcnt_print(u_int regvalue, u_int *cur_col, u_int wrap)
+{
+ return (ahd_print_register(NULL, 0, "SGHCNT",
+ 0x84, regvalue, cur_col, wrap));
+}
+
+static ahd_reg_parse_entry_t DFF_THRSH_parse_table[] = {
+ { "WR_DFTHRSH_MIN", 0x00, 0x70 },
+ { "RD_DFTHRSH_MIN", 0x00, 0x07 },
+ { "RD_DFTHRSH_25", 0x01, 0x07 },
+ { "RD_DFTHRSH_50", 0x02, 0x07 },
+ { "RD_DFTHRSH_63", 0x03, 0x07 },
+ { "RD_DFTHRSH_75", 0x04, 0x07 },
+ { "RD_DFTHRSH_85", 0x05, 0x07 },
+ { "RD_DFTHRSH_90", 0x06, 0x07 },
+ { "RD_DFTHRSH_MAX", 0x07, 0x07 },
+ { "WR_DFTHRSH_25", 0x10, 0x70 },
+ { "WR_DFTHRSH_50", 0x20, 0x70 },
+ { "WR_DFTHRSH_63", 0x30, 0x70 },
+ { "WR_DFTHRSH_75", 0x40, 0x70 },
+ { "WR_DFTHRSH_85", 0x50, 0x70 },
+ { "WR_DFTHRSH_90", 0x60, 0x70 },
+ { "WR_DFTHRSH_MAX", 0x70, 0x70 },
+ { "RD_DFTHRSH", 0x07, 0x07 },
+ { "WR_DFTHRSH", 0x70, 0x70 }
+};
+
+int
+ahd_dff_thrsh_print(u_int regvalue, u_int *cur_col, u_int wrap)
+{
+ return (ahd_print_register(DFF_THRSH_parse_table, 18, "DFF_THRSH",
+ 0x88, regvalue, cur_col, wrap));
+}
+
+int
+ahd_romaddr_print(u_int regvalue, u_int *cur_col, u_int wrap)
+{
+ return (ahd_print_register(NULL, 0, "ROMADDR",
+ 0x8a, regvalue, cur_col, wrap));
+}
+
+static ahd_reg_parse_entry_t ROMCNTRL_parse_table[] = {
+ { "RDY", 0x01, 0x01 },
+ { "REPEAT", 0x02, 0x02 },
+ { "ROMSPD", 0x18, 0x18 },
+ { "ROMOP", 0xe0, 0xe0 }
+};
+
+int
+ahd_romcntrl_print(u_int regvalue, u_int *cur_col, u_int wrap)
+{
+ return (ahd_print_register(ROMCNTRL_parse_table, 4, "ROMCNTRL",
+ 0x8d, regvalue, cur_col, wrap));
+}
+
+int
+ahd_romdata_print(u_int regvalue, u_int *cur_col, u_int wrap)
+{
+ return (ahd_print_register(NULL, 0, "ROMDATA",
+ 0x8e, regvalue, cur_col, wrap));
+}
+
+static ahd_reg_parse_entry_t DCHRXMSG0_parse_table[] = {
+ { "CFNUM", 0x07, 0x07 },
+ { "CDNUM", 0xf8, 0xf8 }
+};
+
+int
+ahd_dchrxmsg0_print(u_int regvalue, u_int *cur_col, u_int wrap)
+{
+ return (ahd_print_register(DCHRXMSG0_parse_table, 2, "DCHRXMSG0",
+ 0x90, regvalue, cur_col, wrap));
+}
+
+static ahd_reg_parse_entry_t OVLYRXMSG0_parse_table[] = {
+ { "CFNUM", 0x07, 0x07 },
+ { "CDNUM", 0xf8, 0xf8 }
+};
+
+int
+ahd_ovlyrxmsg0_print(u_int regvalue, u_int *cur_col, u_int wrap)
+{
+ return (ahd_print_register(OVLYRXMSG0_parse_table, 2, "OVLYRXMSG0",
+ 0x90, regvalue, cur_col, wrap));
+}
+
+static ahd_reg_parse_entry_t CMCRXMSG0_parse_table[] = {
+ { "CFNUM", 0x07, 0x07 },
+ { "CDNUM", 0xf8, 0xf8 }
+};
+
+int
+ahd_cmcrxmsg0_print(u_int regvalue, u_int *cur_col, u_int wrap)
+{
+ return (ahd_print_register(CMCRXMSG0_parse_table, 2, "CMCRXMSG0",
+ 0x90, regvalue, cur_col, wrap));
+}
+
+static ahd_reg_parse_entry_t ROENABLE_parse_table[] = {
+ { "DCH0ROEN", 0x01, 0x01 },
+ { "DCH1ROEN", 0x02, 0x02 },
+ { "SGROEN", 0x04, 0x04 },
+ { "CMCROEN", 0x08, 0x08 },
+ { "OVLYROEN", 0x10, 0x10 },
+ { "MSIROEN", 0x20, 0x20 }
+};
+
+int
+ahd_roenable_print(u_int regvalue, u_int *cur_col, u_int wrap)
+{
+ return (ahd_print_register(ROENABLE_parse_table, 6, "ROENABLE",
+ 0x90, regvalue, cur_col, wrap));
+}
+
+static ahd_reg_parse_entry_t DCHRXMSG1_parse_table[] = {
+ { "CBNUM", 0xff, 0xff }
+};
+
+int
+ahd_dchrxmsg1_print(u_int regvalue, u_int *cur_col, u_int wrap)
+{
+ return (ahd_print_register(DCHRXMSG1_parse_table, 1, "DCHRXMSG1",
+ 0x91, regvalue, cur_col, wrap));
+}
+
+static ahd_reg_parse_entry_t OVLYRXMSG1_parse_table[] = {
+ { "CBNUM", 0xff, 0xff }
+};
+
+int
+ahd_ovlyrxmsg1_print(u_int regvalue, u_int *cur_col, u_int wrap)
+{
+ return (ahd_print_register(OVLYRXMSG1_parse_table, 1, "OVLYRXMSG1",
+ 0x91, regvalue, cur_col, wrap));
+}
+
+static ahd_reg_parse_entry_t CMCRXMSG1_parse_table[] = {
+ { "CBNUM", 0xff, 0xff }
+};
+
+int
+ahd_cmcrxmsg1_print(u_int regvalue, u_int *cur_col, u_int wrap)
+{
+ return (ahd_print_register(CMCRXMSG1_parse_table, 1, "CMCRXMSG1",
+ 0x91, regvalue, cur_col, wrap));
+}
+
+static ahd_reg_parse_entry_t NSENABLE_parse_table[] = {
+ { "DCH0NSEN", 0x01, 0x01 },
+ { "DCH1NSEN", 0x02, 0x02 },
+ { "SGNSEN", 0x04, 0x04 },
+ { "CMCNSEN", 0x08, 0x08 },
+ { "OVLYNSEN", 0x10, 0x10 },
+ { "MSINSEN", 0x20, 0x20 }
+};
+
+int
+ahd_nsenable_print(u_int regvalue, u_int *cur_col, u_int wrap)
+{
+ return (ahd_print_register(NSENABLE_parse_table, 6, "NSENABLE",
+ 0x91, regvalue, cur_col, wrap));
+}
+
+static ahd_reg_parse_entry_t DCHRXMSG2_parse_table[] = {
+ { "MINDEX", 0xff, 0xff }
+};
+
+int
+ahd_dchrxmsg2_print(u_int regvalue, u_int *cur_col, u_int wrap)
+{
+ return (ahd_print_register(DCHRXMSG2_parse_table, 1, "DCHRXMSG2",
+ 0x92, regvalue, cur_col, wrap));
+}
+
+static ahd_reg_parse_entry_t OVLYRXMSG2_parse_table[] = {
+ { "MINDEX", 0xff, 0xff }
+};
+
+int
+ahd_ovlyrxmsg2_print(u_int regvalue, u_int *cur_col, u_int wrap)
+{
+ return (ahd_print_register(OVLYRXMSG2_parse_table, 1, "OVLYRXMSG2",
+ 0x92, regvalue, cur_col, wrap));
+}
+
+static ahd_reg_parse_entry_t CMCRXMSG2_parse_table[] = {
+ { "MINDEX", 0xff, 0xff }
+};
+
+int
+ahd_cmcrxmsg2_print(u_int regvalue, u_int *cur_col, u_int wrap)
+{
+ return (ahd_print_register(CMCRXMSG2_parse_table, 1, "CMCRXMSG2",
+ 0x92, regvalue, cur_col, wrap));
+}
+
+int
+ahd_ost_print(u_int regvalue, u_int *cur_col, u_int wrap)
+{
+ return (ahd_print_register(NULL, 0, "OST",
+ 0x92, regvalue, cur_col, wrap));
+}
+
+static ahd_reg_parse_entry_t DCHRXMSG3_parse_table[] = {
+ { "MCLASS", 0x0f, 0x0f }
+};
+
+int
+ahd_dchrxmsg3_print(u_int regvalue, u_int *cur_col, u_int wrap)
+{
+ return (ahd_print_register(DCHRXMSG3_parse_table, 1, "DCHRXMSG3",
+ 0x93, regvalue, cur_col, wrap));
+}
+
+static ahd_reg_parse_entry_t OVLYRXMSG3_parse_table[] = {
+ { "MCLASS", 0x0f, 0x0f }
+};
+
+int
+ahd_ovlyrxmsg3_print(u_int regvalue, u_int *cur_col, u_int wrap)
+{
+ return (ahd_print_register(OVLYRXMSG3_parse_table, 1, "OVLYRXMSG3",
+ 0x93, regvalue, cur_col, wrap));
+}
+
+static ahd_reg_parse_entry_t CMCRXMSG3_parse_table[] = {
+ { "MCLASS", 0x0f, 0x0f }
+};
+
+int
+ahd_cmcrxmsg3_print(u_int regvalue, u_int *cur_col, u_int wrap)
+{
+ return (ahd_print_register(CMCRXMSG3_parse_table, 1, "CMCRXMSG3",
+ 0x93, regvalue, cur_col, wrap));
+}
+
+static ahd_reg_parse_entry_t PCIXCTL_parse_table[] = {
+ { "CMPABCDIS", 0x01, 0x01 },
+ { "TSCSERREN", 0x02, 0x02 },
+ { "SRSPDPEEN", 0x04, 0x04 },
+ { "SPLTSTADIS", 0x08, 0x08 },
+ { "SPLTSMADIS", 0x10, 0x10 },
+ { "UNEXPSCIEN", 0x20, 0x20 },
+ { "SERRPULSE", 0x80, 0x80 }
+};
+
+int
+ahd_pcixctl_print(u_int regvalue, u_int *cur_col, u_int wrap)
+{
+ return (ahd_print_register(PCIXCTL_parse_table, 7, "PCIXCTL",
+ 0x93, regvalue, cur_col, wrap));
+}
+
+int
+ahd_cmcseqbcnt_print(u_int regvalue, u_int *cur_col, u_int wrap)
+{
+ return (ahd_print_register(NULL, 0, "CMCSEQBCNT",
+ 0x94, regvalue, cur_col, wrap));
+}
+
+int
+ahd_dchseqbcnt_print(u_int regvalue, u_int *cur_col, u_int wrap)
+{
+ return (ahd_print_register(NULL, 0, "DCHSEQBCNT",
+ 0x94, regvalue, cur_col, wrap));
+}
+
+int
+ahd_ovlyseqbcnt_print(u_int regvalue, u_int *cur_col, u_int wrap)
+{
+ return (ahd_print_register(NULL, 0, "OVLYSEQBCNT",
+ 0x94, regvalue, cur_col, wrap));
+}
+
+static ahd_reg_parse_entry_t CMCSPLTSTAT0_parse_table[] = {
+ { "RXSPLTRSP", 0x01, 0x01 },
+ { "RXSCEMSG", 0x02, 0x02 },
+ { "RXOVRUN", 0x04, 0x04 },
+ { "CNTNOTCMPLT", 0x08, 0x08 },
+ { "SCDATBUCKET", 0x10, 0x10 },
+ { "SCADERR", 0x20, 0x20 },
+ { "SCBCERR", 0x40, 0x40 },
+ { "STAETERM", 0x80, 0x80 }
+};
+
+int
+ahd_cmcspltstat0_print(u_int regvalue, u_int *cur_col, u_int wrap)
+{
+ return (ahd_print_register(CMCSPLTSTAT0_parse_table, 8, "CMCSPLTSTAT0",
+ 0x96, regvalue, cur_col, wrap));
+}
+
+static ahd_reg_parse_entry_t DCHSPLTSTAT0_parse_table[] = {
+ { "RXSPLTRSP", 0x01, 0x01 },
+ { "RXSCEMSG", 0x02, 0x02 },
+ { "RXOVRUN", 0x04, 0x04 },
+ { "CNTNOTCMPLT", 0x08, 0x08 },
+ { "SCDATBUCKET", 0x10, 0x10 },
+ { "SCADERR", 0x20, 0x20 },
+ { "SCBCERR", 0x40, 0x40 },
+ { "STAETERM", 0x80, 0x80 }
+};
+
+int
+ahd_dchspltstat0_print(u_int regvalue, u_int *cur_col, u_int wrap)
+{
+ return (ahd_print_register(DCHSPLTSTAT0_parse_table, 8, "DCHSPLTSTAT0",
+ 0x96, regvalue, cur_col, wrap));
+}
+
+static ahd_reg_parse_entry_t OVLYSPLTSTAT0_parse_table[] = {
+ { "RXSPLTRSP", 0x01, 0x01 },
+ { "RXSCEMSG", 0x02, 0x02 },
+ { "RXOVRUN", 0x04, 0x04 },
+ { "CNTNOTCMPLT", 0x08, 0x08 },
+ { "SCDATBUCKET", 0x10, 0x10 },
+ { "SCADERR", 0x20, 0x20 },
+ { "SCBCERR", 0x40, 0x40 },
+ { "STAETERM", 0x80, 0x80 }
+};
+
+int
+ahd_ovlyspltstat0_print(u_int regvalue, u_int *cur_col, u_int wrap)
+{
+ return (ahd_print_register(OVLYSPLTSTAT0_parse_table, 8, "OVLYSPLTSTAT0",
+ 0x96, regvalue, cur_col, wrap));
+}
+
+static ahd_reg_parse_entry_t CMCSPLTSTAT1_parse_table[] = {
+ { "RXDATABUCKET", 0x01, 0x01 }
+};
+
+int
+ahd_cmcspltstat1_print(u_int regvalue, u_int *cur_col, u_int wrap)
+{
+ return (ahd_print_register(CMCSPLTSTAT1_parse_table, 1, "CMCSPLTSTAT1",
+ 0x97, regvalue, cur_col, wrap));
+}
+
+static ahd_reg_parse_entry_t DCHSPLTSTAT1_parse_table[] = {
+ { "RXDATABUCKET", 0x01, 0x01 }
+};
+
+int
+ahd_dchspltstat1_print(u_int regvalue, u_int *cur_col, u_int wrap)
+{
+ return (ahd_print_register(DCHSPLTSTAT1_parse_table, 1, "DCHSPLTSTAT1",
+ 0x97, regvalue, cur_col, wrap));
+}
+
+static ahd_reg_parse_entry_t OVLYSPLTSTAT1_parse_table[] = {
+ { "RXDATABUCKET", 0x01, 0x01 }
+};
+
+int
+ahd_ovlyspltstat1_print(u_int regvalue, u_int *cur_col, u_int wrap)
+{
+ return (ahd_print_register(OVLYSPLTSTAT1_parse_table, 1, "OVLYSPLTSTAT1",
+ 0x97, regvalue, cur_col, wrap));
+}
+
+static ahd_reg_parse_entry_t SGRXMSG0_parse_table[] = {
+ { "CFNUM", 0x07, 0x07 },
+ { "CDNUM", 0xf8, 0xf8 }
+};
+
+int
+ahd_sgrxmsg0_print(u_int regvalue, u_int *cur_col, u_int wrap)
+{
+ return (ahd_print_register(SGRXMSG0_parse_table, 2, "SGRXMSG0",
+ 0x98, regvalue, cur_col, wrap));
+}
+
+static ahd_reg_parse_entry_t SLVSPLTOUTADR0_parse_table[] = {
+ { "LOWER_ADDR", 0x7f, 0x7f }
+};
+
+int
+ahd_slvspltoutadr0_print(u_int regvalue, u_int *cur_col, u_int wrap)
+{
+ return (ahd_print_register(SLVSPLTOUTADR0_parse_table, 1, "SLVSPLTOUTADR0",
+ 0x98, regvalue, cur_col, wrap));
+}
+
+static ahd_reg_parse_entry_t SGRXMSG1_parse_table[] = {
+ { "CBNUM", 0xff, 0xff }
+};
+
+int
+ahd_sgrxmsg1_print(u_int regvalue, u_int *cur_col, u_int wrap)
+{
+ return (ahd_print_register(SGRXMSG1_parse_table, 1, "SGRXMSG1",
+ 0x99, regvalue, cur_col, wrap));
+}
+
+static ahd_reg_parse_entry_t SLVSPLTOUTADR1_parse_table[] = {
+ { "REQ_FNUM", 0x07, 0x07 },
+ { "REQ_DNUM", 0xf8, 0xf8 }
+};
+
+int
+ahd_slvspltoutadr1_print(u_int regvalue, u_int *cur_col, u_int wrap)
+{
+ return (ahd_print_register(SLVSPLTOUTADR1_parse_table, 2, "SLVSPLTOUTADR1",
+ 0x99, regvalue, cur_col, wrap));
+}
+
+static ahd_reg_parse_entry_t SGRXMSG2_parse_table[] = {
+ { "MINDEX", 0xff, 0xff }
+};
+
+int
+ahd_sgrxmsg2_print(u_int regvalue, u_int *cur_col, u_int wrap)
+{
+ return (ahd_print_register(SGRXMSG2_parse_table, 1, "SGRXMSG2",
+ 0x9a, regvalue, cur_col, wrap));
+}
+
+static ahd_reg_parse_entry_t SLVSPLTOUTADR2_parse_table[] = {
+ { "REQ_BNUM", 0xff, 0xff }
+};
+
+int
+ahd_slvspltoutadr2_print(u_int regvalue, u_int *cur_col, u_int wrap)
+{
+ return (ahd_print_register(SLVSPLTOUTADR2_parse_table, 1, "SLVSPLTOUTADR2",
+ 0x9a, regvalue, cur_col, wrap));
+}
+
+static ahd_reg_parse_entry_t SGRXMSG3_parse_table[] = {
+ { "MCLASS", 0x0f, 0x0f }
+};
+
+int
+ahd_sgrxmsg3_print(u_int regvalue, u_int *cur_col, u_int wrap)
+{
+ return (ahd_print_register(SGRXMSG3_parse_table, 1, "SGRXMSG3",
+ 0x9b, regvalue, cur_col, wrap));
+}
+
+static ahd_reg_parse_entry_t SLVSPLTOUTADR3_parse_table[] = {
+ { "RLXORD", 0x10, 0x10 },
+ { "TAG_NUM", 0x1f, 0x1f }
+};
+
+int
+ahd_slvspltoutadr3_print(u_int regvalue, u_int *cur_col, u_int wrap)
+{
+ return (ahd_print_register(SLVSPLTOUTADR3_parse_table, 2, "SLVSPLTOUTADR3",
+ 0x9b, regvalue, cur_col, wrap));
+}
+
+static ahd_reg_parse_entry_t SLVSPLTOUTATTR0_parse_table[] = {
+ { "LOWER_BCNT", 0xff, 0xff }
+};
+
+int
+ahd_slvspltoutattr0_print(u_int regvalue, u_int *cur_col, u_int wrap)
+{
+ return (ahd_print_register(SLVSPLTOUTATTR0_parse_table, 1, "SLVSPLTOUTATTR0",
+ 0x9c, regvalue, cur_col, wrap));
+}
+
+int
+ahd_sgseqbcnt_print(u_int regvalue, u_int *cur_col, u_int wrap)
+{
+ return (ahd_print_register(NULL, 0, "SGSEQBCNT",
+ 0x9c, regvalue, cur_col, wrap));
+}
+
+static ahd_reg_parse_entry_t SLVSPLTOUTATTR1_parse_table[] = {
+ { "CMPLT_FNUM", 0x07, 0x07 },
+ { "CMPLT_DNUM", 0xf8, 0xf8 }
+};
+
+int
+ahd_slvspltoutattr1_print(u_int regvalue, u_int *cur_col, u_int wrap)
+{
+ return (ahd_print_register(SLVSPLTOUTATTR1_parse_table, 2, "SLVSPLTOUTATTR1",
+ 0x9d, regvalue, cur_col, wrap));
+}
+
+static ahd_reg_parse_entry_t SLVSPLTOUTATTR2_parse_table[] = {
+ { "CMPLT_BNUM", 0xff, 0xff }
+};
+
+int
+ahd_slvspltoutattr2_print(u_int regvalue, u_int *cur_col, u_int wrap)
+{
+ return (ahd_print_register(SLVSPLTOUTATTR2_parse_table, 1, "SLVSPLTOUTATTR2",
+ 0x9e, regvalue, cur_col, wrap));
+}
+
+static ahd_reg_parse_entry_t SGSPLTSTAT0_parse_table[] = {
+ { "RXSPLTRSP", 0x01, 0x01 },
+ { "RXSCEMSG", 0x02, 0x02 },
+ { "RXOVRUN", 0x04, 0x04 },
+ { "CNTNOTCMPLT", 0x08, 0x08 },
+ { "SCDATBUCKET", 0x10, 0x10 },
+ { "SCADERR", 0x20, 0x20 },
+ { "SCBCERR", 0x40, 0x40 },
+ { "STAETERM", 0x80, 0x80 }
+};
+
+int
+ahd_sgspltstat0_print(u_int regvalue, u_int *cur_col, u_int wrap)
+{
+ return (ahd_print_register(SGSPLTSTAT0_parse_table, 8, "SGSPLTSTAT0",
+ 0x9e, regvalue, cur_col, wrap));
+}
+
+static ahd_reg_parse_entry_t SFUNCT_parse_table[] = {
+ { "TEST_NUM", 0x0f, 0x0f },
+ { "TEST_GROUP", 0xf0, 0xf0 }
+};
+
+int
+ahd_sfunct_print(u_int regvalue, u_int *cur_col, u_int wrap)
+{
+ return (ahd_print_register(SFUNCT_parse_table, 2, "SFUNCT",
+ 0x9f, regvalue, cur_col, wrap));
+}
+
+static ahd_reg_parse_entry_t SGSPLTSTAT1_parse_table[] = {
+ { "RXDATABUCKET", 0x01, 0x01 }
+};
+
+int
+ahd_sgspltstat1_print(u_int regvalue, u_int *cur_col, u_int wrap)
+{
+ return (ahd_print_register(SGSPLTSTAT1_parse_table, 1, "SGSPLTSTAT1",
+ 0x9f, regvalue, cur_col, wrap));
+}
+
+static ahd_reg_parse_entry_t DF0PCISTAT_parse_table[] = {
+ { "DPR", 0x01, 0x01 },
+ { "TWATERR", 0x02, 0x02 },
+ { "RDPERR", 0x04, 0x04 },
+ { "SCAAPERR", 0x08, 0x08 },
+ { "RTA", 0x10, 0x10 },
+ { "RMA", 0x20, 0x20 },
+ { "SSE", 0x40, 0x40 },
+ { "DPE", 0x80, 0x80 }
+};
+
+int
+ahd_df0pcistat_print(u_int regvalue, u_int *cur_col, u_int wrap)
+{
+ return (ahd_print_register(DF0PCISTAT_parse_table, 8, "DF0PCISTAT",
+ 0xa0, regvalue, cur_col, wrap));
+}
+
+int
+ahd_reg0_print(u_int regvalue, u_int *cur_col, u_int wrap)
+{
+ return (ahd_print_register(NULL, 0, "REG0",
+ 0xa0, regvalue, cur_col, wrap));
+}
+
+static ahd_reg_parse_entry_t DF1PCISTAT_parse_table[] = {
+ { "DPR", 0x01, 0x01 },
+ { "TWATERR", 0x02, 0x02 },
+ { "RDPERR", 0x04, 0x04 },
+ { "SCAAPERR", 0x08, 0x08 },
+ { "RTA", 0x10, 0x10 },
+ { "RMA", 0x20, 0x20 },
+ { "SSE", 0x40, 0x40 },
+ { "DPE", 0x80, 0x80 }
+};
+
+int
+ahd_df1pcistat_print(u_int regvalue, u_int *cur_col, u_int wrap)
+{
+ return (ahd_print_register(DF1PCISTAT_parse_table, 8, "DF1PCISTAT",
+ 0xa1, regvalue, cur_col, wrap));
+}
+
+static ahd_reg_parse_entry_t SGPCISTAT_parse_table[] = {
+ { "DPR", 0x01, 0x01 },
+ { "RDPERR", 0x04, 0x04 },
+ { "SCAAPERR", 0x08, 0x08 },
+ { "RTA", 0x10, 0x10 },
+ { "RMA", 0x20, 0x20 },
+ { "SSE", 0x40, 0x40 },
+ { "DPE", 0x80, 0x80 }
+};
+
+int
+ahd_sgpcistat_print(u_int regvalue, u_int *cur_col, u_int wrap)
+{
+ return (ahd_print_register(SGPCISTAT_parse_table, 7, "SGPCISTAT",
+ 0xa2, regvalue, cur_col, wrap));
+}
+
+int
+ahd_reg1_print(u_int regvalue, u_int *cur_col, u_int wrap)
+{
+ return (ahd_print_register(NULL, 0, "REG1",
+ 0xa2, regvalue, cur_col, wrap));
+}
+
+static ahd_reg_parse_entry_t CMCPCISTAT_parse_table[] = {
+ { "DPR", 0x01, 0x01 },
+ { "TWATERR", 0x02, 0x02 },
+ { "RDPERR", 0x04, 0x04 },
+ { "SCAAPERR", 0x08, 0x08 },
+ { "RTA", 0x10, 0x10 },
+ { "RMA", 0x20, 0x20 },
+ { "SSE", 0x40, 0x40 },
+ { "DPE", 0x80, 0x80 }
+};
+
+int
+ahd_cmcpcistat_print(u_int regvalue, u_int *cur_col, u_int wrap)
+{
+ return (ahd_print_register(CMCPCISTAT_parse_table, 8, "CMCPCISTAT",
+ 0xa3, regvalue, cur_col, wrap));
+}
+
+static ahd_reg_parse_entry_t OVLYPCISTAT_parse_table[] = {
+ { "DPR", 0x01, 0x01 },
+ { "RDPERR", 0x04, 0x04 },
+ { "SCAAPERR", 0x08, 0x08 },
+ { "RTA", 0x10, 0x10 },
+ { "RMA", 0x20, 0x20 },
+ { "SSE", 0x40, 0x40 },
+ { "DPE", 0x80, 0x80 }
+};
+
+int
+ahd_ovlypcistat_print(u_int regvalue, u_int *cur_col, u_int wrap)
+{
+ return (ahd_print_register(OVLYPCISTAT_parse_table, 7, "OVLYPCISTAT",
+ 0xa4, regvalue, cur_col, wrap));
+}
+
+int
+ahd_reg_isr_print(u_int regvalue, u_int *cur_col, u_int wrap)
+{
+ return (ahd_print_register(NULL, 0, "REG_ISR",
+ 0xa4, regvalue, cur_col, wrap));
+}
+
+static ahd_reg_parse_entry_t MSIPCISTAT_parse_table[] = {
+ { "DPR", 0x01, 0x01 },
+ { "TWATERR", 0x02, 0x02 },
+ { "CLRPENDMSI", 0x08, 0x08 },
+ { "RTA", 0x10, 0x10 },
+ { "RMA", 0x20, 0x20 },
+ { "SSE", 0x40, 0x40 }
+};
+
+int
+ahd_msipcistat_print(u_int regvalue, u_int *cur_col, u_int wrap)
+{
+ return (ahd_print_register(MSIPCISTAT_parse_table, 6, "MSIPCISTAT",
+ 0xa6, regvalue, cur_col, wrap));
+}
+
+static ahd_reg_parse_entry_t SG_STATE_parse_table[] = {
+ { "SEGS_AVAIL", 0x01, 0x01 },
+ { "LOADING_NEEDED", 0x02, 0x02 },
+ { "FETCH_INPROG", 0x04, 0x04 }
+};
+
+int
+ahd_sg_state_print(u_int regvalue, u_int *cur_col, u_int wrap)
+{
+ return (ahd_print_register(SG_STATE_parse_table, 3, "SG_STATE",
+ 0xa6, regvalue, cur_col, wrap));
+}
+
+static ahd_reg_parse_entry_t TARGPCISTAT_parse_table[] = {
+ { "TWATERR", 0x02, 0x02 },
+ { "STA", 0x08, 0x08 },
+ { "SSE", 0x40, 0x40 },
+ { "DPE", 0x80, 0x80 }
+};
+
+int
+ahd_targpcistat_print(u_int regvalue, u_int *cur_col, u_int wrap)
+{
+ return (ahd_print_register(TARGPCISTAT_parse_table, 4, "TARGPCISTAT",
+ 0xa7, regvalue, cur_col, wrap));
+}
+
+int
+ahd_data_count_odd_print(u_int regvalue, u_int *cur_col, u_int wrap)
+{
+ return (ahd_print_register(NULL, 0, "DATA_COUNT_ODD",
+ 0xa7, regvalue, cur_col, wrap));
+}
+
+int
+ahd_scbptr_print(u_int regvalue, u_int *cur_col, u_int wrap)
+{
+ return (ahd_print_register(NULL, 0, "SCBPTR",
+ 0xa8, regvalue, cur_col, wrap));
+}
+
+int
+ahd_ccscbacnt_print(u_int regvalue, u_int *cur_col, u_int wrap)
+{
+ return (ahd_print_register(NULL, 0, "CCSCBACNT",
+ 0xab, regvalue, cur_col, wrap));
+}
+
+static ahd_reg_parse_entry_t SCBAUTOPTR_parse_table[] = {
+ { "SCBPTR_OFF", 0x07, 0x07 },
+ { "SCBPTR_ADDR", 0x38, 0x38 },
+ { "AUSCBPTR_EN", 0x80, 0x80 }
+};
+
+int
+ahd_scbautoptr_print(u_int regvalue, u_int *cur_col, u_int wrap)
+{
+ return (ahd_print_register(SCBAUTOPTR_parse_table, 3, "SCBAUTOPTR",
+ 0xab, regvalue, cur_col, wrap));
+}
+
+int
+ahd_ccscbadr_bk_print(u_int regvalue, u_int *cur_col, u_int wrap)
+{
+ return (ahd_print_register(NULL, 0, "CCSCBADR_BK",
+ 0xac, regvalue, cur_col, wrap));
+}
+
+int
+ahd_ccsgaddr_print(u_int regvalue, u_int *cur_col, u_int wrap)
+{
+ return (ahd_print_register(NULL, 0, "CCSGADDR",
+ 0xac, regvalue, cur_col, wrap));
+}
+
+int
+ahd_ccscbaddr_print(u_int regvalue, u_int *cur_col, u_int wrap)
+{
+ return (ahd_print_register(NULL, 0, "CCSCBADDR",
+ 0xac, regvalue, cur_col, wrap));
+}
+
+static ahd_reg_parse_entry_t CCSCBCTL_parse_table[] = {
+ { "CCSCBRESET", 0x01, 0x01 },
+ { "CCSCBDIR", 0x04, 0x04 },
+ { "CCSCBEN", 0x08, 0x08 },
+ { "CCARREN", 0x10, 0x10 },
+ { "ARRDONE", 0x40, 0x40 },
+ { "CCSCBDONE", 0x80, 0x80 }
+};
+
+int
+ahd_ccscbctl_print(u_int regvalue, u_int *cur_col, u_int wrap)
+{
+ return (ahd_print_register(CCSCBCTL_parse_table, 6, "CCSCBCTL",
+ 0xad, regvalue, cur_col, wrap));
+}
+
+static ahd_reg_parse_entry_t CCSGCTL_parse_table[] = {
+ { "CCSGRESET", 0x01, 0x01 },
+ { "SG_FETCH_REQ", 0x02, 0x02 },
+ { "CCSGENACK", 0x08, 0x08 },
+ { "SG_CACHE_AVAIL", 0x10, 0x10 },
+ { "CCSGDONE", 0x80, 0x80 },
+ { "CCSGEN", 0x0c, 0x0c }
+};
+
+int
+ahd_ccsgctl_print(u_int regvalue, u_int *cur_col, u_int wrap)
+{
+ return (ahd_print_register(CCSGCTL_parse_table, 6, "CCSGCTL",
+ 0xad, regvalue, cur_col, wrap));
+}
+
+static ahd_reg_parse_entry_t CMC_RAMBIST_parse_table[] = {
+ { "CMC_BUFFER_BIST_EN", 0x01, 0x01 },
+ { "CMC_BUFFER_BIST_FAIL",0x02, 0x02 },
+ { "SG_BIST_EN", 0x10, 0x10 },
+ { "SG_BIST_FAIL", 0x20, 0x20 },
+ { "SCBRAMBIST_FAIL", 0x40, 0x40 },
+ { "SG_ELEMENT_SIZE", 0x80, 0x80 }
+};
+
+int
+ahd_cmc_rambist_print(u_int regvalue, u_int *cur_col, u_int wrap)
+{
+ return (ahd_print_register(CMC_RAMBIST_parse_table, 6, "CMC_RAMBIST",
+ 0xad, regvalue, cur_col, wrap));
+}
+
+int
+ahd_ccsgram_print(u_int regvalue, u_int *cur_col, u_int wrap)
+{
+ return (ahd_print_register(NULL, 0, "CCSGRAM",
+ 0xb0, regvalue, cur_col, wrap));
+}
+
+int
+ahd_ccscbram_print(u_int regvalue, u_int *cur_col, u_int wrap)
+{
+ return (ahd_print_register(NULL, 0, "CCSCBRAM",
+ 0xb0, regvalue, cur_col, wrap));
+}
+
+int
+ahd_flexadr_print(u_int regvalue, u_int *cur_col, u_int wrap)
+{
+ return (ahd_print_register(NULL, 0, "FLEXADR",
+ 0xb0, regvalue, cur_col, wrap));
+}
+
+int
+ahd_flexcnt_print(u_int regvalue, u_int *cur_col, u_int wrap)
+{
+ return (ahd_print_register(NULL, 0, "FLEXCNT",
+ 0xb3, regvalue, cur_col, wrap));
+}
+
+static ahd_reg_parse_entry_t FLEXDMASTAT_parse_table[] = {
+ { "FLEXDMADONE", 0x01, 0x01 },
+ { "FLEXDMAERR", 0x02, 0x02 }
+};
+
+int
+ahd_flexdmastat_print(u_int regvalue, u_int *cur_col, u_int wrap)
+{
+ return (ahd_print_register(FLEXDMASTAT_parse_table, 2, "FLEXDMASTAT",
+ 0xb5, regvalue, cur_col, wrap));
+}
+
+int
+ahd_flexdata_print(u_int regvalue, u_int *cur_col, u_int wrap)
+{
+ return (ahd_print_register(NULL, 0, "FLEXDATA",
+ 0xb6, regvalue, cur_col, wrap));
+}
+
+int
+ahd_brddat_print(u_int regvalue, u_int *cur_col, u_int wrap)
+{
+ return (ahd_print_register(NULL, 0, "BRDDAT",
+ 0xb8, regvalue, cur_col, wrap));
+}
+
+static ahd_reg_parse_entry_t BRDCTL_parse_table[] = {
+ { "BRDSTB", 0x01, 0x01 },
+ { "BRDRW", 0x02, 0x02 },
+ { "BRDEN", 0x04, 0x04 },
+ { "BRDADDR", 0x38, 0x38 },
+ { "FLXARBREQ", 0x40, 0x40 },
+ { "FLXARBACK", 0x80, 0x80 }
+};
+
+int
+ahd_brdctl_print(u_int regvalue, u_int *cur_col, u_int wrap)
+{
+ return (ahd_print_register(BRDCTL_parse_table, 6, "BRDCTL",
+ 0xb9, regvalue, cur_col, wrap));
+}
+
+int
+ahd_seeadr_print(u_int regvalue, u_int *cur_col, u_int wrap)
+{
+ return (ahd_print_register(NULL, 0, "SEEADR",
+ 0xba, regvalue, cur_col, wrap));
+}
+
+int
+ahd_seedat_print(u_int regvalue, u_int *cur_col, u_int wrap)
+{
+ return (ahd_print_register(NULL, 0, "SEEDAT",
+ 0xbc, regvalue, cur_col, wrap));
+}
+
+static ahd_reg_parse_entry_t SEECTL_parse_table[] = {
+ { "SEEOP_ERAL", 0x40, 0x70 },
+ { "SEEOP_WRITE", 0x50, 0x70 },
+ { "SEEOP_READ", 0x60, 0x70 },
+ { "SEEOP_ERASE", 0x70, 0x70 },
+ { "SEESTART", 0x01, 0x01 },
+ { "SEERST", 0x02, 0x02 },
+ { "SEEOPCODE", 0x70, 0x70 },
+ { "SEEOP_EWEN", 0x40, 0x40 },
+ { "SEEOP_WALL", 0x40, 0x40 },
+ { "SEEOP_EWDS", 0x40, 0x40 }
+};
+
+int
+ahd_seectl_print(u_int regvalue, u_int *cur_col, u_int wrap)
+{
+ return (ahd_print_register(SEECTL_parse_table, 10, "SEECTL",
+ 0xbe, regvalue, cur_col, wrap));
+}
+
+static ahd_reg_parse_entry_t SEESTAT_parse_table[] = {
+ { "SEESTART", 0x01, 0x01 },
+ { "SEEBUSY", 0x02, 0x02 },
+ { "SEEARBACK", 0x04, 0x04 },
+ { "LDALTID_L", 0x08, 0x08 },
+ { "SEEOPCODE", 0x70, 0x70 },
+ { "INIT_DONE", 0x80, 0x80 }
+};
+
+int
+ahd_seestat_print(u_int regvalue, u_int *cur_col, u_int wrap)
+{
+ return (ahd_print_register(SEESTAT_parse_table, 6, "SEESTAT",
+ 0xbe, regvalue, cur_col, wrap));
+}
+
+int
+ahd_scbcnt_print(u_int regvalue, u_int *cur_col, u_int wrap)
+{
+ return (ahd_print_register(NULL, 0, "SCBCNT",
+ 0xbf, regvalue, cur_col, wrap));
+}
+
+static ahd_reg_parse_entry_t DSPFLTRCTL_parse_table[] = {
+ { "DSPFCNTSEL", 0x0f, 0x0f },
+ { "EDGESENSE", 0x10, 0x10 },
+ { "FLTRDISABLE", 0x20, 0x20 }
+};
+
+int
+ahd_dspfltrctl_print(u_int regvalue, u_int *cur_col, u_int wrap)
+{
+ return (ahd_print_register(DSPFLTRCTL_parse_table, 3, "DSPFLTRCTL",
+ 0xc0, regvalue, cur_col, wrap));
+}
+
+int
+ahd_dfwaddr_print(u_int regvalue, u_int *cur_col, u_int wrap)
+{
+ return (ahd_print_register(NULL, 0, "DFWADDR",
+ 0xc0, regvalue, cur_col, wrap));
+}
+
+static ahd_reg_parse_entry_t DSPDATACTL_parse_table[] = {
+ { "XMITOFFSTDIS", 0x02, 0x02 },
+ { "RCVROFFSTDIS", 0x04, 0x04 },
+ { "DESQDIS", 0x10, 0x10 },
+ { "BYPASSENAB", 0x80, 0x80 }
+};
+
+int
+ahd_dspdatactl_print(u_int regvalue, u_int *cur_col, u_int wrap)
+{
+ return (ahd_print_register(DSPDATACTL_parse_table, 4, "DSPDATACTL",
+ 0xc1, regvalue, cur_col, wrap));
+}
+
+static ahd_reg_parse_entry_t DSPREQCTL_parse_table[] = {
+ { "MANREQDLY", 0x3f, 0x3f },
+ { "MANREQCTL", 0xc0, 0xc0 }
+};
+
+int
+ahd_dspreqctl_print(u_int regvalue, u_int *cur_col, u_int wrap)
+{
+ return (ahd_print_register(DSPREQCTL_parse_table, 2, "DSPREQCTL",
+ 0xc2, regvalue, cur_col, wrap));
+}
+
+int
+ahd_dfraddr_print(u_int regvalue, u_int *cur_col, u_int wrap)
+{
+ return (ahd_print_register(NULL, 0, "DFRADDR",
+ 0xc2, regvalue, cur_col, wrap));
+}
+
+static ahd_reg_parse_entry_t DSPACKCTL_parse_table[] = {
+ { "MANACKDLY", 0x3f, 0x3f },
+ { "MANACKCTL", 0xc0, 0xc0 }
+};
+
+int
+ahd_dspackctl_print(u_int regvalue, u_int *cur_col, u_int wrap)
+{
+ return (ahd_print_register(DSPACKCTL_parse_table, 2, "DSPACKCTL",
+ 0xc3, regvalue, cur_col, wrap));
+}
+
+int
+ahd_dfdat_print(u_int regvalue, u_int *cur_col, u_int wrap)
+{
+ return (ahd_print_register(NULL, 0, "DFDAT",
+ 0xc4, regvalue, cur_col, wrap));
+}
+
+static ahd_reg_parse_entry_t DSPSELECT_parse_table[] = {
+ { "DSPSEL", 0x1f, 0x1f },
+ { "AUTOINCEN", 0x80, 0x80 }
+};
+
+int
+ahd_dspselect_print(u_int regvalue, u_int *cur_col, u_int wrap)
+{
+ return (ahd_print_register(DSPSELECT_parse_table, 2, "DSPSELECT",
+ 0xc4, regvalue, cur_col, wrap));
+}
+
+static ahd_reg_parse_entry_t WRTBIASCTL_parse_table[] = {
+ { "XMITMANVAL", 0x3f, 0x3f },
+ { "AUTOXBCDIS", 0x80, 0x80 }
+};
+
+int
+ahd_wrtbiasctl_print(u_int regvalue, u_int *cur_col, u_int wrap)
+{
+ return (ahd_print_register(WRTBIASCTL_parse_table, 2, "WRTBIASCTL",
+ 0xc5, regvalue, cur_col, wrap));
+}
+
+static ahd_reg_parse_entry_t RCVRBIOSCTL_parse_table[] = {
+ { "RCVRMANVAL", 0x3f, 0x3f },
+ { "AUTORBCDIS", 0x80, 0x80 }
+};
+
+int
+ahd_rcvrbiosctl_print(u_int regvalue, u_int *cur_col, u_int wrap)
+{
+ return (ahd_print_register(RCVRBIOSCTL_parse_table, 2, "RCVRBIOSCTL",
+ 0xc6, regvalue, cur_col, wrap));
+}
+
+int
+ahd_wrtbiascalc_print(u_int regvalue, u_int *cur_col, u_int wrap)
+{
+ return (ahd_print_register(NULL, 0, "WRTBIASCALC",
+ 0xc7, regvalue, cur_col, wrap));
+}
+
+int
+ahd_dfptrs_print(u_int regvalue, u_int *cur_col, u_int wrap)
+{
+ return (ahd_print_register(NULL, 0, "DFPTRS",
+ 0xc8, regvalue, cur_col, wrap));
+}
+
+int
+ahd_rcvrbiascalc_print(u_int regvalue, u_int *cur_col, u_int wrap)
+{
+ return (ahd_print_register(NULL, 0, "RCVRBIASCALC",
+ 0xc8, regvalue, cur_col, wrap));
+}
+
+int
+ahd_dfbkptr_print(u_int regvalue, u_int *cur_col, u_int wrap)
+{
+ return (ahd_print_register(NULL, 0, "DFBKPTR",
+ 0xc9, regvalue, cur_col, wrap));
+}
+
+int
+ahd_skewcalc_print(u_int regvalue, u_int *cur_col, u_int wrap)
+{
+ return (ahd_print_register(NULL, 0, "SKEWCALC",
+ 0xc9, regvalue, cur_col, wrap));
+}
+
+static ahd_reg_parse_entry_t DFDBCTL_parse_table[] = {
+ { "DFF_RAMBIST_EN", 0x01, 0x01 },
+ { "DFF_RAMBIST_DONE", 0x02, 0x02 },
+ { "DFF_RAMBIST_FAIL", 0x04, 0x04 },
+ { "DFF_DIR_ERR", 0x08, 0x08 },
+ { "DFF_CIO_RD_RDY", 0x10, 0x10 },
+ { "DFF_CIO_WR_RDY", 0x20, 0x20 }
+};
+
+int
+ahd_dfdbctl_print(u_int regvalue, u_int *cur_col, u_int wrap)
+{
+ return (ahd_print_register(DFDBCTL_parse_table, 6, "DFDBCTL",
+ 0xcb, regvalue, cur_col, wrap));
+}
+
+int
+ahd_dfscnt_print(u_int regvalue, u_int *cur_col, u_int wrap)
+{
+ return (ahd_print_register(NULL, 0, "DFSCNT",
+ 0xcc, regvalue, cur_col, wrap));
+}
+
+int
+ahd_dfbcnt_print(u_int regvalue, u_int *cur_col, u_int wrap)
+{
+ return (ahd_print_register(NULL, 0, "DFBCNT",
+ 0xce, regvalue, cur_col, wrap));
+}
+
+int
+ahd_ovlyaddr_print(u_int regvalue, u_int *cur_col, u_int wrap)
+{
+ return (ahd_print_register(NULL, 0, "OVLYADDR",
+ 0xd4, regvalue, cur_col, wrap));
+}
+
+static ahd_reg_parse_entry_t SEQCTL0_parse_table[] = {
+ { "LOADRAM", 0x01, 0x01 },
+ { "SEQRESET", 0x02, 0x02 },
+ { "STEP", 0x04, 0x04 },
+ { "BRKADRINTEN", 0x08, 0x08 },
+ { "FASTMODE", 0x10, 0x10 },
+ { "FAILDIS", 0x20, 0x20 },
+ { "PAUSEDIS", 0x40, 0x40 },
+ { "PERRORDIS", 0x80, 0x80 }
+};
+
+int
+ahd_seqctl0_print(u_int regvalue, u_int *cur_col, u_int wrap)
+{
+ return (ahd_print_register(SEQCTL0_parse_table, 8, "SEQCTL0",
+ 0xd6, regvalue, cur_col, wrap));
+}
+
+static ahd_reg_parse_entry_t SEQCTL1_parse_table[] = {
+ { "RAMBIST_EN", 0x01, 0x01 },
+ { "RAMBIST_FAIL", 0x02, 0x02 },
+ { "RAMBIST_DONE", 0x04, 0x04 },
+ { "OVRLAY_DATA_CHK", 0x08, 0x08 }
+};
+
+int
+ahd_seqctl1_print(u_int regvalue, u_int *cur_col, u_int wrap)
+{
+ return (ahd_print_register(SEQCTL1_parse_table, 4, "SEQCTL1",
+ 0xd7, regvalue, cur_col, wrap));
+}
+
+static ahd_reg_parse_entry_t FLAGS_parse_table[] = {
+ { "CARRY", 0x01, 0x01 },
+ { "ZERO", 0x02, 0x02 }
+};
+
+int
+ahd_flags_print(u_int regvalue, u_int *cur_col, u_int wrap)
+{
+ return (ahd_print_register(FLAGS_parse_table, 2, "FLAGS",
+ 0xd8, regvalue, cur_col, wrap));
+}
+
+static ahd_reg_parse_entry_t SEQINTCTL_parse_table[] = {
+ { "IRET", 0x01, 0x01 },
+ { "INTMASK1", 0x02, 0x02 },
+ { "INTMASK2", 0x04, 0x04 },
+ { "SCS_SEQ_INT1M0", 0x08, 0x08 },
+ { "SCS_SEQ_INT1M1", 0x10, 0x10 },
+ { "INT1_CONTEXT", 0x20, 0x20 },
+ { "INTVEC1DSL", 0x80, 0x80 }
+};
+
+int
+ahd_seqintctl_print(u_int regvalue, u_int *cur_col, u_int wrap)
+{
+ return (ahd_print_register(SEQINTCTL_parse_table, 7, "SEQINTCTL",
+ 0xd9, regvalue, cur_col, wrap));
+}
+
+int
+ahd_seqram_print(u_int regvalue, u_int *cur_col, u_int wrap)
+{
+ return (ahd_print_register(NULL, 0, "SEQRAM",
+ 0xda, regvalue, cur_col, wrap));
+}
+
+int
+ahd_prgmcnt_print(u_int regvalue, u_int *cur_col, u_int wrap)
+{
+ return (ahd_print_register(NULL, 0, "PRGMCNT",
+ 0xde, regvalue, cur_col, wrap));
+}
+
+int
+ahd_accum_print(u_int regvalue, u_int *cur_col, u_int wrap)
+{
+ return (ahd_print_register(NULL, 0, "ACCUM",
+ 0xe0, regvalue, cur_col, wrap));
+}
+
+int
+ahd_sindex_print(u_int regvalue, u_int *cur_col, u_int wrap)
+{
+ return (ahd_print_register(NULL, 0, "SINDEX",
+ 0xe2, regvalue, cur_col, wrap));
+}
+
+int
+ahd_dindex_print(u_int regvalue, u_int *cur_col, u_int wrap)
+{
+ return (ahd_print_register(NULL, 0, "DINDEX",
+ 0xe4, regvalue, cur_col, wrap));
+}
+
+static ahd_reg_parse_entry_t BRKADDR1_parse_table[] = {
+ { "BRKDIS", 0x80, 0x80 }
+};
+
+int
+ahd_brkaddr1_print(u_int regvalue, u_int *cur_col, u_int wrap)
+{
+ return (ahd_print_register(BRKADDR1_parse_table, 1, "BRKADDR1",
+ 0xe6, regvalue, cur_col, wrap));
+}
+
+int
+ahd_brkaddr0_print(u_int regvalue, u_int *cur_col, u_int wrap)
+{
+ return (ahd_print_register(NULL, 0, "BRKADDR0",
+ 0xe6, regvalue, cur_col, wrap));
+}
+
+int
+ahd_allones_print(u_int regvalue, u_int *cur_col, u_int wrap)
+{
+ return (ahd_print_register(NULL, 0, "ALLONES",
+ 0xe8, regvalue, cur_col, wrap));
+}
+
+int
+ahd_none_print(u_int regvalue, u_int *cur_col, u_int wrap)
+{
+ return (ahd_print_register(NULL, 0, "NONE",
+ 0xea, regvalue, cur_col, wrap));
+}
+
+int
+ahd_allzeros_print(u_int regvalue, u_int *cur_col, u_int wrap)
+{
+ return (ahd_print_register(NULL, 0, "ALLZEROS",
+ 0xea, regvalue, cur_col, wrap));
+}
+
+int
+ahd_sindir_print(u_int regvalue, u_int *cur_col, u_int wrap)
+{
+ return (ahd_print_register(NULL, 0, "SINDIR",
+ 0xec, regvalue, cur_col, wrap));
+}
+
+int
+ahd_dindir_print(u_int regvalue, u_int *cur_col, u_int wrap)
+{
+ return (ahd_print_register(NULL, 0, "DINDIR",
+ 0xed, regvalue, cur_col, wrap));
+}
+
+int
+ahd_function1_print(u_int regvalue, u_int *cur_col, u_int wrap)
+{
+ return (ahd_print_register(NULL, 0, "FUNCTION1",
+ 0xf0, regvalue, cur_col, wrap));
+}
+
+int
+ahd_stack_print(u_int regvalue, u_int *cur_col, u_int wrap)
+{
+ return (ahd_print_register(NULL, 0, "STACK",
+ 0xf2, regvalue, cur_col, wrap));
+}
+
+int
+ahd_intvec1_addr_print(u_int regvalue, u_int *cur_col, u_int wrap)
+{
+ return (ahd_print_register(NULL, 0, "INTVEC1_ADDR",
+ 0xf4, regvalue, cur_col, wrap));
+}
+
+int
+ahd_curaddr_print(u_int regvalue, u_int *cur_col, u_int wrap)
+{
+ return (ahd_print_register(NULL, 0, "CURADDR",
+ 0xf4, regvalue, cur_col, wrap));
+}
+
+int
+ahd_intvec2_addr_print(u_int regvalue, u_int *cur_col, u_int wrap)
+{
+ return (ahd_print_register(NULL, 0, "INTVEC2_ADDR",
+ 0xf6, regvalue, cur_col, wrap));
+}
+
+int
+ahd_lastaddr_print(u_int regvalue, u_int *cur_col, u_int wrap)
+{
+ return (ahd_print_register(NULL, 0, "LASTADDR",
+ 0xf6, regvalue, cur_col, wrap));
+}
+
+int
+ahd_longjmp_addr_print(u_int regvalue, u_int *cur_col, u_int wrap)
+{
+ return (ahd_print_register(NULL, 0, "LONGJMP_ADDR",
+ 0xf8, regvalue, cur_col, wrap));
+}
+
+int
+ahd_accum_save_print(u_int regvalue, u_int *cur_col, u_int wrap)
+{
+ return (ahd_print_register(NULL, 0, "ACCUM_SAVE",
+ 0xfa, regvalue, cur_col, wrap));
+}
+
+int
+ahd_sram_base_print(u_int regvalue, u_int *cur_col, u_int wrap)
+{
+ return (ahd_print_register(NULL, 0, "SRAM_BASE",
+ 0x100, regvalue, cur_col, wrap));
+}
+
+int
+ahd_waiting_scb_tails_print(u_int regvalue, u_int *cur_col, u_int wrap)
+{
+ return (ahd_print_register(NULL, 0, "WAITING_SCB_TAILS",
+ 0x100, regvalue, cur_col, wrap));
+}
+
+int
+ahd_ahd_pci_config_base_print(u_int regvalue, u_int *cur_col, u_int wrap)
+{
+ return (ahd_print_register(NULL, 0, "AHD_PCI_CONFIG_BASE",
+ 0x100, regvalue, cur_col, wrap));
+}
+
+int
+ahd_waiting_tid_head_print(u_int regvalue, u_int *cur_col, u_int wrap)
+{
+ return (ahd_print_register(NULL, 0, "WAITING_TID_HEAD",
+ 0x120, regvalue, cur_col, wrap));
+}
+
+int
+ahd_waiting_tid_tail_print(u_int regvalue, u_int *cur_col, u_int wrap)
+{
+ return (ahd_print_register(NULL, 0, "WAITING_TID_TAIL",
+ 0x122, regvalue, cur_col, wrap));
+}
+
+int
+ahd_next_queued_scb_addr_print(u_int regvalue, u_int *cur_col, u_int wrap)
+{
+ return (ahd_print_register(NULL, 0, "NEXT_QUEUED_SCB_ADDR",
+ 0x124, regvalue, cur_col, wrap));
+}
+
+int
+ahd_complete_scb_head_print(u_int regvalue, u_int *cur_col, u_int wrap)
+{
+ return (ahd_print_register(NULL, 0, "COMPLETE_SCB_HEAD",
+ 0x128, regvalue, cur_col, wrap));
+}
+
+int
+ahd_complete_scb_dmainprog_head_print(u_int regvalue, u_int *cur_col, u_int wrap)
+{
+ return (ahd_print_register(NULL, 0, "COMPLETE_SCB_DMAINPROG_HEAD",
+ 0x12a, regvalue, cur_col, wrap));
+}
+
+int
+ahd_complete_dma_scb_head_print(u_int regvalue, u_int *cur_col, u_int wrap)
+{
+ return (ahd_print_register(NULL, 0, "COMPLETE_DMA_SCB_HEAD",
+ 0x12c, regvalue, cur_col, wrap));
+}
+
+int
+ahd_complete_dma_scb_tail_print(u_int regvalue, u_int *cur_col, u_int wrap)
+{
+ return (ahd_print_register(NULL, 0, "COMPLETE_DMA_SCB_TAIL",
+ 0x12e, regvalue, cur_col, wrap));
+}
+
+int
+ahd_complete_on_qfreeze_head_print(u_int regvalue, u_int *cur_col, u_int wrap)
+{
+ return (ahd_print_register(NULL, 0, "COMPLETE_ON_QFREEZE_HEAD",
+ 0x130, regvalue, cur_col, wrap));
+}
+
+int
+ahd_qfreeze_count_print(u_int regvalue, u_int *cur_col, u_int wrap)
+{
+ return (ahd_print_register(NULL, 0, "QFREEZE_COUNT",
+ 0x132, regvalue, cur_col, wrap));
+}
+
+int
+ahd_kernel_qfreeze_count_print(u_int regvalue, u_int *cur_col, u_int wrap)
+{
+ return (ahd_print_register(NULL, 0, "KERNEL_QFREEZE_COUNT",
+ 0x134, regvalue, cur_col, wrap));
+}
+
+int
+ahd_saved_mode_print(u_int regvalue, u_int *cur_col, u_int wrap)
+{
+ return (ahd_print_register(NULL, 0, "SAVED_MODE",
+ 0x136, regvalue, cur_col, wrap));
+}
+
+int
+ahd_msg_out_print(u_int regvalue, u_int *cur_col, u_int wrap)
+{
+ return (ahd_print_register(NULL, 0, "MSG_OUT",
+ 0x137, regvalue, cur_col, wrap));
+}
+
+static ahd_reg_parse_entry_t DMAPARAMS_parse_table[] = {
+ { "FIFORESET", 0x01, 0x01 },
+ { "FIFOFLUSH", 0x02, 0x02 },
+ { "DIRECTION", 0x04, 0x04 },
+ { "HDMAEN", 0x08, 0x08 },
+ { "HDMAENACK", 0x08, 0x08 },
+ { "SDMAEN", 0x10, 0x10 },
+ { "SDMAENACK", 0x10, 0x10 },
+ { "SCSIEN", 0x20, 0x20 },
+ { "WIDEODD", 0x40, 0x40 },
+ { "PRELOADEN", 0x80, 0x80 }
+};
+
+int
+ahd_dmaparams_print(u_int regvalue, u_int *cur_col, u_int wrap)
+{
+ return (ahd_print_register(DMAPARAMS_parse_table, 10, "DMAPARAMS",
+ 0x138, regvalue, cur_col, wrap));
+}
+
+static ahd_reg_parse_entry_t SEQ_FLAGS_parse_table[] = {
+ { "NO_DISCONNECT", 0x01, 0x01 },
+ { "SPHASE_PENDING", 0x02, 0x02 },
+ { "DPHASE_PENDING", 0x04, 0x04 },
+ { "CMDPHASE_PENDING", 0x08, 0x08 },
+ { "TARG_CMD_PENDING", 0x10, 0x10 },
+ { "DPHASE", 0x20, 0x20 },
+ { "NO_CDB_SENT", 0x40, 0x40 },
+ { "TARGET_CMD_IS_TAGGED",0x40, 0x40 },
+ { "NOT_IDENTIFIED", 0x80, 0x80 }
+};
+
+int
+ahd_seq_flags_print(u_int regvalue, u_int *cur_col, u_int wrap)
+{
+ return (ahd_print_register(SEQ_FLAGS_parse_table, 9, "SEQ_FLAGS",
+ 0x139, regvalue, cur_col, wrap));
+}
+
+int
+ahd_saved_scsiid_print(u_int regvalue, u_int *cur_col, u_int wrap)
+{
+ return (ahd_print_register(NULL, 0, "SAVED_SCSIID",
+ 0x13a, regvalue, cur_col, wrap));
+}
+
+int
+ahd_saved_lun_print(u_int regvalue, u_int *cur_col, u_int wrap)
+{
+ return (ahd_print_register(NULL, 0, "SAVED_LUN",
+ 0x13b, regvalue, cur_col, wrap));
+}
+
+static ahd_reg_parse_entry_t LASTPHASE_parse_table[] = {
+ { "P_DATAOUT", 0x00, 0xe0 },
+ { "P_DATAOUT_DT", 0x20, 0xe0 },
+ { "P_DATAIN", 0x40, 0xe0 },
+ { "P_DATAIN_DT", 0x60, 0xe0 },
+ { "P_COMMAND", 0x80, 0xe0 },
+ { "P_MESGOUT", 0xa0, 0xe0 },
+ { "P_STATUS", 0xc0, 0xe0 },
+ { "P_MESGIN", 0xe0, 0xe0 },
+ { "P_BUSFREE", 0x01, 0x01 },
+ { "MSGI", 0x20, 0x20 },
+ { "IOI", 0x40, 0x40 },
+ { "CDI", 0x80, 0x80 },
+ { "PHASE_MASK", 0xe0, 0xe0 }
+};
+
+int
+ahd_lastphase_print(u_int regvalue, u_int *cur_col, u_int wrap)
+{
+ return (ahd_print_register(LASTPHASE_parse_table, 13, "LASTPHASE",
+ 0x13c, regvalue, cur_col, wrap));
+}
+
+int
+ahd_qoutfifo_entry_valid_tag_print(u_int regvalue, u_int *cur_col, u_int wrap)
+{
+ return (ahd_print_register(NULL, 0, "QOUTFIFO_ENTRY_VALID_TAG",
+ 0x13d, regvalue, cur_col, wrap));
+}
+
+int
+ahd_kernel_tqinpos_print(u_int regvalue, u_int *cur_col, u_int wrap)
+{
+ return (ahd_print_register(NULL, 0, "KERNEL_TQINPOS",
+ 0x13e, regvalue, cur_col, wrap));
+}
+
+int
+ahd_tqinpos_print(u_int regvalue, u_int *cur_col, u_int wrap)
+{
+ return (ahd_print_register(NULL, 0, "TQINPOS",
+ 0x13f, regvalue, cur_col, wrap));
+}
+
+int
+ahd_shared_data_addr_print(u_int regvalue, u_int *cur_col, u_int wrap)
+{
+ return (ahd_print_register(NULL, 0, "SHARED_DATA_ADDR",
+ 0x140, regvalue, cur_col, wrap));
+}
+
+int
+ahd_qoutfifo_next_addr_print(u_int regvalue, u_int *cur_col, u_int wrap)
+{
+ return (ahd_print_register(NULL, 0, "QOUTFIFO_NEXT_ADDR",
+ 0x144, regvalue, cur_col, wrap));
+}
+
+static ahd_reg_parse_entry_t ARG_1_parse_table[] = {
+ { "CONT_MSG_LOOP_TARG", 0x02, 0x02 },
+ { "CONT_MSG_LOOP_READ", 0x03, 0x03 },
+ { "CONT_MSG_LOOP_WRITE",0x04, 0x04 },
+ { "EXIT_MSG_LOOP", 0x08, 0x08 },
+ { "MSGOUT_PHASEMIS", 0x10, 0x10 },
+ { "SEND_REJ", 0x20, 0x20 },
+ { "SEND_SENSE", 0x40, 0x40 },
+ { "SEND_MSG", 0x80, 0x80 }
+};
+
+int
+ahd_arg_1_print(u_int regvalue, u_int *cur_col, u_int wrap)
+{
+ return (ahd_print_register(ARG_1_parse_table, 8, "ARG_1",
+ 0x148, regvalue, cur_col, wrap));
+}
+
+int
+ahd_arg_2_print(u_int regvalue, u_int *cur_col, u_int wrap)
+{
+ return (ahd_print_register(NULL, 0, "ARG_2",
+ 0x149, regvalue, cur_col, wrap));
+}
+
+int
+ahd_last_msg_print(u_int regvalue, u_int *cur_col, u_int wrap)
+{
+ return (ahd_print_register(NULL, 0, "LAST_MSG",
+ 0x14a, regvalue, cur_col, wrap));
+}
+
+static ahd_reg_parse_entry_t SCSISEQ_TEMPLATE_parse_table[] = {
+ { "ALTSTIM", 0x01, 0x01 },
+ { "ENAUTOATNP", 0x02, 0x02 },
+ { "MANUALP", 0x0c, 0x0c },
+ { "ENRSELI", 0x10, 0x10 },
+ { "ENSELI", 0x20, 0x20 },
+ { "MANUALCTL", 0x40, 0x40 }
+};
+
+int
+ahd_scsiseq_template_print(u_int regvalue, u_int *cur_col, u_int wrap)
+{
+ return (ahd_print_register(SCSISEQ_TEMPLATE_parse_table, 6, "SCSISEQ_TEMPLATE",
+ 0x14b, regvalue, cur_col, wrap));
+}
+
+int
+ahd_initiator_tag_print(u_int regvalue, u_int *cur_col, u_int wrap)
+{
+ return (ahd_print_register(NULL, 0, "INITIATOR_TAG",
+ 0x14c, regvalue, cur_col, wrap));
+}
+
+static ahd_reg_parse_entry_t SEQ_FLAGS2_parse_table[] = {
+ { "PENDING_MK_MESSAGE", 0x01, 0x01 },
+ { "TARGET_MSG_PENDING", 0x02, 0x02 },
+ { "SELECTOUT_QFROZEN", 0x04, 0x04 }
+};
+
+int
+ahd_seq_flags2_print(u_int regvalue, u_int *cur_col, u_int wrap)
+{
+ return (ahd_print_register(SEQ_FLAGS2_parse_table, 3, "SEQ_FLAGS2",
+ 0x14d, regvalue, cur_col, wrap));
+}
+
+int
+ahd_allocfifo_scbptr_print(u_int regvalue, u_int *cur_col, u_int wrap)
+{
+ return (ahd_print_register(NULL, 0, "ALLOCFIFO_SCBPTR",
+ 0x14e, regvalue, cur_col, wrap));
+}
+
+int
+ahd_int_coalescing_timer_print(u_int regvalue, u_int *cur_col, u_int wrap)
+{
+ return (ahd_print_register(NULL, 0, "INT_COALESCING_TIMER",
+ 0x150, regvalue, cur_col, wrap));
+}
+
+int
+ahd_int_coalescing_maxcmds_print(u_int regvalue, u_int *cur_col, u_int wrap)
+{
+ return (ahd_print_register(NULL, 0, "INT_COALESCING_MAXCMDS",
+ 0x152, regvalue, cur_col, wrap));
+}
+
+int
+ahd_int_coalescing_mincmds_print(u_int regvalue, u_int *cur_col, u_int wrap)
+{
+ return (ahd_print_register(NULL, 0, "INT_COALESCING_MINCMDS",
+ 0x153, regvalue, cur_col, wrap));
+}
+
+int
+ahd_cmds_pending_print(u_int regvalue, u_int *cur_col, u_int wrap)
+{
+ return (ahd_print_register(NULL, 0, "CMDS_PENDING",
+ 0x154, regvalue, cur_col, wrap));
+}
+
+int
+ahd_int_coalescing_cmdcount_print(u_int regvalue, u_int *cur_col, u_int wrap)
+{
+ return (ahd_print_register(NULL, 0, "INT_COALESCING_CMDCOUNT",
+ 0x156, regvalue, cur_col, wrap));
+}
+
+int
+ahd_local_hs_mailbox_print(u_int regvalue, u_int *cur_col, u_int wrap)
+{
+ return (ahd_print_register(NULL, 0, "LOCAL_HS_MAILBOX",
+ 0x157, regvalue, cur_col, wrap));
+}
+
+int
+ahd_cmdsize_table_print(u_int regvalue, u_int *cur_col, u_int wrap)
+{
+ return (ahd_print_register(NULL, 0, "CMDSIZE_TABLE",
+ 0x158, regvalue, cur_col, wrap));
+}
+
+int
+ahd_mk_message_scb_print(u_int regvalue, u_int *cur_col, u_int wrap)
+{
+ return (ahd_print_register(NULL, 0, "MK_MESSAGE_SCB",
+ 0x160, regvalue, cur_col, wrap));
+}
+
+int
+ahd_mk_message_scsiid_print(u_int regvalue, u_int *cur_col, u_int wrap)
+{
+ return (ahd_print_register(NULL, 0, "MK_MESSAGE_SCSIID",
+ 0x162, regvalue, cur_col, wrap));
+}
+
+int
+ahd_scb_base_print(u_int regvalue, u_int *cur_col, u_int wrap)
+{
+ return (ahd_print_register(NULL, 0, "SCB_BASE",
+ 0x180, regvalue, cur_col, wrap));
+}
+
+int
+ahd_scb_residual_datacnt_print(u_int regvalue, u_int *cur_col, u_int wrap)
+{
+ return (ahd_print_register(NULL, 0, "SCB_RESIDUAL_DATACNT",
+ 0x180, regvalue, cur_col, wrap));
+}
+
+static ahd_reg_parse_entry_t SCB_RESIDUAL_SGPTR_parse_table[] = {
+ { "SG_LIST_NULL", 0x01, 0x01 },
+ { "SG_OVERRUN_RESID", 0x02, 0x02 },
+ { "SG_ADDR_BIT", 0x04, 0x04 },
+ { "SG_ADDR_MASK", 0xf8, 0xf8 }
+};
+
+int
+ahd_scb_residual_sgptr_print(u_int regvalue, u_int *cur_col, u_int wrap)
+{
+ return (ahd_print_register(SCB_RESIDUAL_SGPTR_parse_table, 4, "SCB_RESIDUAL_SGPTR",
+ 0x184, regvalue, cur_col, wrap));
+}
+
+int
+ahd_scb_scsi_status_print(u_int regvalue, u_int *cur_col, u_int wrap)
+{
+ return (ahd_print_register(NULL, 0, "SCB_SCSI_STATUS",
+ 0x188, regvalue, cur_col, wrap));
+}
+
+int
+ahd_scb_target_phases_print(u_int regvalue, u_int *cur_col, u_int wrap)
+{
+ return (ahd_print_register(NULL, 0, "SCB_TARGET_PHASES",
+ 0x189, regvalue, cur_col, wrap));
+}
+
+int
+ahd_scb_target_data_dir_print(u_int regvalue, u_int *cur_col, u_int wrap)
+{
+ return (ahd_print_register(NULL, 0, "SCB_TARGET_DATA_DIR",
+ 0x18a, regvalue, cur_col, wrap));
+}
+
+int
+ahd_scb_target_itag_print(u_int regvalue, u_int *cur_col, u_int wrap)
+{
+ return (ahd_print_register(NULL, 0, "SCB_TARGET_ITAG",
+ 0x18b, regvalue, cur_col, wrap));
+}
+
+int
+ahd_scb_sense_busaddr_print(u_int regvalue, u_int *cur_col, u_int wrap)
+{
+ return (ahd_print_register(NULL, 0, "SCB_SENSE_BUSADDR",
+ 0x18c, regvalue, cur_col, wrap));
+}
+
+int
+ahd_scb_tag_print(u_int regvalue, u_int *cur_col, u_int wrap)
+{
+ return (ahd_print_register(NULL, 0, "SCB_TAG",
+ 0x190, regvalue, cur_col, wrap));
+}
+
+static ahd_reg_parse_entry_t SCB_CONTROL_parse_table[] = {
+ { "SCB_TAG_TYPE", 0x03, 0x03 },
+ { "DISCONNECTED", 0x04, 0x04 },
+ { "STATUS_RCVD", 0x08, 0x08 },
+ { "MK_MESSAGE", 0x10, 0x10 },
+ { "TAG_ENB", 0x20, 0x20 },
+ { "DISCENB", 0x40, 0x40 },
+ { "TARGET_SCB", 0x80, 0x80 }
+};
+
+int
+ahd_scb_control_print(u_int regvalue, u_int *cur_col, u_int wrap)
+{
+ return (ahd_print_register(SCB_CONTROL_parse_table, 7, "SCB_CONTROL",
+ 0x192, regvalue, cur_col, wrap));
+}
+
+static ahd_reg_parse_entry_t SCB_SCSIID_parse_table[] = {
+ { "OID", 0x0f, 0x0f },
+ { "TID", 0xf0, 0xf0 }
+};
+
+int
+ahd_scb_scsiid_print(u_int regvalue, u_int *cur_col, u_int wrap)
+{
+ return (ahd_print_register(SCB_SCSIID_parse_table, 2, "SCB_SCSIID",
+ 0x193, regvalue, cur_col, wrap));
+}
+
+static ahd_reg_parse_entry_t SCB_LUN_parse_table[] = {
+ { "LID", 0xff, 0xff }
+};
+
+int
+ahd_scb_lun_print(u_int regvalue, u_int *cur_col, u_int wrap)
+{
+ return (ahd_print_register(SCB_LUN_parse_table, 1, "SCB_LUN",
+ 0x194, regvalue, cur_col, wrap));
+}
+
+static ahd_reg_parse_entry_t SCB_TASK_ATTRIBUTE_parse_table[] = {
+ { "SCB_XFERLEN_ODD", 0x01, 0x01 }
+};
+
+int
+ahd_scb_task_attribute_print(u_int regvalue, u_int *cur_col, u_int wrap)
+{
+ return (ahd_print_register(SCB_TASK_ATTRIBUTE_parse_table, 1, "SCB_TASK_ATTRIBUTE",
+ 0x195, regvalue, cur_col, wrap));
+}
+
+static ahd_reg_parse_entry_t SCB_CDB_LEN_parse_table[] = {
+ { "SCB_CDB_LEN_PTR", 0x80, 0x80 }
+};
+
+int
+ahd_scb_cdb_len_print(u_int regvalue, u_int *cur_col, u_int wrap)
+{
+ return (ahd_print_register(SCB_CDB_LEN_parse_table, 1, "SCB_CDB_LEN",
+ 0x196, regvalue, cur_col, wrap));
+}
+
+int
+ahd_scb_task_management_print(u_int regvalue, u_int *cur_col, u_int wrap)
+{
+ return (ahd_print_register(NULL, 0, "SCB_TASK_MANAGEMENT",
+ 0x197, regvalue, cur_col, wrap));
+}
+
+int
+ahd_scb_dataptr_print(u_int regvalue, u_int *cur_col, u_int wrap)
+{
+ return (ahd_print_register(NULL, 0, "SCB_DATAPTR",
+ 0x198, regvalue, cur_col, wrap));
+}
+
+static ahd_reg_parse_entry_t SCB_DATACNT_parse_table[] = {
+ { "SG_HIGH_ADDR_BITS", 0x7f, 0x7f },
+ { "SG_LAST_SEG", 0x80, 0x80 }
+};
+
+int
+ahd_scb_datacnt_print(u_int regvalue, u_int *cur_col, u_int wrap)
+{
+ return (ahd_print_register(SCB_DATACNT_parse_table, 2, "SCB_DATACNT",
+ 0x1a0, regvalue, cur_col, wrap));
+}
+
+static ahd_reg_parse_entry_t SCB_SGPTR_parse_table[] = {
+ { "SG_LIST_NULL", 0x01, 0x01 },
+ { "SG_FULL_RESID", 0x02, 0x02 },
+ { "SG_STATUS_VALID", 0x04, 0x04 }
+};
+
+int
+ahd_scb_sgptr_print(u_int regvalue, u_int *cur_col, u_int wrap)
+{
+ return (ahd_print_register(SCB_SGPTR_parse_table, 3, "SCB_SGPTR",
+ 0x1a4, regvalue, cur_col, wrap));
+}
+
+int
+ahd_scb_busaddr_print(u_int regvalue, u_int *cur_col, u_int wrap)
+{
+ return (ahd_print_register(NULL, 0, "SCB_BUSADDR",
+ 0x1a8, regvalue, cur_col, wrap));
+}
+
+int
+ahd_scb_next_print(u_int regvalue, u_int *cur_col, u_int wrap)
+{
+ return (ahd_print_register(NULL, 0, "SCB_NEXT",
+ 0x1ac, regvalue, cur_col, wrap));
+}
+
+int
+ahd_scb_next2_print(u_int regvalue, u_int *cur_col, u_int wrap)
+{
+ return (ahd_print_register(NULL, 0, "SCB_NEXT2",
+ 0x1ae, regvalue, cur_col, wrap));
+}
+
+int
+ahd_scb_spare_print(u_int regvalue, u_int *cur_col, u_int wrap)
+{
+ return (ahd_print_register(NULL, 0, "SCB_SPARE",
+ 0x1b0, regvalue, cur_col, wrap));
+}
+
+int
+ahd_scb_disconnected_lists_print(u_int regvalue, u_int *cur_col, u_int wrap)
+{
+ return (ahd_print_register(NULL, 0, "SCB_DISCONNECTED_LISTS",
+ 0x1b8, regvalue, cur_col, wrap));
+}
+
Property changes on: trunk/sys/dev/aic7xxx/aic79xx_reg_print.c
___________________________________________________________________
Added: svn:eol-style
## -0,0 +1 ##
+native
\ No newline at end of property
Added: svn:keywords
## -0,0 +1 ##
+MidnightBSD=%H
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+text/plain
\ No newline at end of property
Added: trunk/sys/dev/aic7xxx/aic79xx_seq.h
===================================================================
--- trunk/sys/dev/aic7xxx/aic79xx_seq.h (rev 0)
+++ trunk/sys/dev/aic7xxx/aic79xx_seq.h 2018-05-28 00:27:43 UTC (rev 10128)
@@ -0,0 +1,1193 @@
+/* $MidnightBSD$ */
+/*
+ * DO NOT EDIT - This file is automatically generated
+ * from the following source files:
+ *
+ * $Id: //depot/aic7xxx/aic7xxx/aic79xx.seq#119 $
+ * $Id: //depot/aic7xxx/aic7xxx/aic79xx.reg#76 $
+ *
+ * $FreeBSD: stable/10/sys/dev/aic7xxx/aic79xx_seq.h 270284 2014-08-21 17:18:21Z ian $
+ */
+static uint8_t seqprog[] = {
+ 0xff, 0x02, 0x06, 0x78,
+ 0x00, 0xea, 0x6e, 0x59,
+ 0x01, 0xea, 0x04, 0x30,
+ 0xff, 0x04, 0x0c, 0x78,
+ 0x19, 0xea, 0x6e, 0x59,
+ 0x19, 0xea, 0x04, 0x00,
+ 0x33, 0xea, 0x68, 0x59,
+ 0x33, 0xea, 0x00, 0x00,
+ 0x60, 0x3a, 0x3a, 0x68,
+ 0x04, 0x4d, 0x35, 0x78,
+ 0x01, 0x34, 0xc1, 0x31,
+ 0x00, 0x32, 0x21, 0x60,
+ 0x01, 0x35, 0xc1, 0x31,
+ 0x00, 0x33, 0x21, 0x60,
+ 0xfb, 0x4d, 0x9b, 0x0a,
+ 0x00, 0xe2, 0x34, 0x40,
+ 0x50, 0x4b, 0x3a, 0x68,
+ 0xff, 0x31, 0x3b, 0x70,
+ 0x02, 0x30, 0x51, 0x31,
+ 0xff, 0x8d, 0x2d, 0x70,
+ 0x02, 0x8c, 0x51, 0x31,
+ 0xff, 0x8d, 0x29, 0x60,
+ 0x02, 0x28, 0x19, 0x33,
+ 0x02, 0x30, 0x51, 0x32,
+ 0xff, 0xea, 0x62, 0x02,
+ 0x00, 0xe2, 0x3a, 0x40,
+ 0xff, 0x21, 0x3b, 0x70,
+ 0x40, 0x4b, 0xb4, 0x69,
+ 0x00, 0xe2, 0x72, 0x59,
+ 0x40, 0x4b, 0xb4, 0x69,
+ 0x20, 0x4b, 0xa0, 0x69,
+ 0xfc, 0x42, 0x44, 0x78,
+ 0x10, 0x40, 0x44, 0x78,
+ 0x00, 0xe2, 0x10, 0x5e,
+ 0x20, 0x4d, 0x48, 0x78,
+ 0x00, 0xe2, 0x10, 0x5e,
+ 0x30, 0x3f, 0xc0, 0x09,
+ 0x30, 0xe0, 0x50, 0x60,
+ 0x7f, 0x4a, 0x94, 0x08,
+ 0x00, 0xe2, 0x52, 0x40,
+ 0xc0, 0x4a, 0x94, 0x00,
+ 0x00, 0xe2, 0x5e, 0x58,
+ 0x00, 0xe2, 0x76, 0x58,
+ 0x00, 0xe2, 0x86, 0x58,
+ 0x00, 0xe2, 0x06, 0x40,
+ 0x33, 0xea, 0x68, 0x59,
+ 0x33, 0xea, 0x00, 0x00,
+ 0x01, 0x52, 0x84, 0x78,
+ 0x02, 0x58, 0x50, 0x31,
+ 0xff, 0xea, 0x10, 0x0b,
+ 0xff, 0x97, 0x6f, 0x78,
+ 0x50, 0x4b, 0x6a, 0x68,
+ 0xbf, 0x3a, 0x74, 0x08,
+ 0x14, 0xea, 0x6e, 0x59,
+ 0x14, 0xea, 0x04, 0x00,
+ 0x08, 0x92, 0x25, 0x03,
+ 0xff, 0x90, 0x5f, 0x68,
+ 0x00, 0xe2, 0x8a, 0x5b,
+ 0x00, 0xe2, 0x5e, 0x40,
+ 0x00, 0xea, 0x68, 0x59,
+ 0x01, 0xea, 0x00, 0x30,
+ 0x80, 0xf9, 0x7e, 0x68,
+ 0x00, 0xe2, 0x66, 0x59,
+ 0x11, 0xea, 0x68, 0x59,
+ 0x11, 0xea, 0x00, 0x00,
+ 0x80, 0xf9, 0x66, 0x79,
+ 0xff, 0xea, 0xd4, 0x0d,
+ 0x22, 0xea, 0x68, 0x59,
+ 0x22, 0xea, 0x00, 0x00,
+ 0x10, 0x16, 0x90, 0x78,
+ 0x10, 0x16, 0x2c, 0x00,
+ 0x01, 0x0b, 0xae, 0x32,
+ 0x18, 0xad, 0x1c, 0x79,
+ 0x04, 0xad, 0xdc, 0x68,
+ 0x80, 0xad, 0x84, 0x78,
+ 0x10, 0xad, 0xaa, 0x78,
+ 0xe7, 0xad, 0x5a, 0x09,
+ 0x02, 0x8c, 0x59, 0x32,
+ 0xff, 0x8d, 0xa1, 0x60,
+ 0xff, 0xea, 0x5e, 0x02,
+ 0xff, 0x88, 0xa7, 0x78,
+ 0x02, 0x30, 0x19, 0x33,
+ 0x02, 0xa8, 0x60, 0x36,
+ 0x02, 0x28, 0x19, 0x33,
+ 0x02, 0xa8, 0x50, 0x36,
+ 0xe7, 0xad, 0x5a, 0x09,
+ 0x00, 0xe2, 0xb8, 0x58,
+ 0xff, 0xea, 0x56, 0x02,
+ 0x04, 0x7c, 0x88, 0x32,
+ 0x20, 0x16, 0x84, 0x78,
+ 0x04, 0x40, 0x89, 0x32,
+ 0x80, 0x3d, 0x7b, 0x16,
+ 0xff, 0x2d, 0xc7, 0x60,
+ 0xff, 0x29, 0xc7, 0x60,
+ 0x40, 0x57, 0xd7, 0x78,
+ 0xff, 0x55, 0xc7, 0x68,
+ 0xff, 0x53, 0xc1, 0x19,
+ 0x00, 0x54, 0xd5, 0x19,
+ 0x00, 0xe2, 0xd6, 0x50,
+ 0x01, 0x52, 0xc1, 0x31,
+ 0x00, 0x56, 0xd5, 0x19,
+ 0x00, 0xe2, 0xd6, 0x48,
+ 0x80, 0x18, 0x84, 0x78,
+ 0x02, 0x50, 0x1d, 0x30,
+ 0x10, 0xea, 0x18, 0x00,
+ 0x60, 0x18, 0x30, 0x00,
+ 0x7f, 0x18, 0x30, 0x0c,
+ 0x02, 0xea, 0x02, 0x00,
+ 0xff, 0xea, 0xac, 0x0a,
+ 0x80, 0x18, 0x30, 0x04,
+ 0x40, 0xad, 0x84, 0x78,
+ 0xe7, 0xad, 0x5a, 0x09,
+ 0xff, 0xea, 0xc0, 0x09,
+ 0x01, 0x54, 0xa9, 0x1a,
+ 0x00, 0x55, 0xab, 0x22,
+ 0x01, 0x94, 0x6d, 0x33,
+ 0xff, 0xea, 0x20, 0x0b,
+ 0x04, 0xac, 0x49, 0x32,
+ 0xff, 0xea, 0x5a, 0x03,
+ 0xff, 0xea, 0x5e, 0x03,
+ 0x01, 0x10, 0xd4, 0x31,
+ 0x02, 0xa8, 0x40, 0x31,
+ 0x01, 0x92, 0xc1, 0x31,
+ 0x3d, 0x93, 0xc5, 0x29,
+ 0xfe, 0xe2, 0xc4, 0x09,
+ 0x01, 0xea, 0xc6, 0x01,
+ 0x02, 0xe2, 0xc8, 0x31,
+ 0x02, 0xec, 0x50, 0x31,
+ 0x02, 0xa0, 0xda, 0x31,
+ 0xff, 0xa9, 0x10, 0x71,
+ 0x10, 0xe0, 0x0e, 0x79,
+ 0x10, 0x92, 0x0f, 0x79,
+ 0x01, 0x4d, 0x9b, 0x02,
+ 0x02, 0xa0, 0xc0, 0x32,
+ 0x01, 0x93, 0xc5, 0x36,
+ 0x02, 0xa0, 0x58, 0x37,
+ 0xff, 0x21, 0x19, 0x71,
+ 0x02, 0x22, 0x51, 0x31,
+ 0x02, 0xa0, 0x5c, 0x33,
+ 0x02, 0xa0, 0x44, 0x36,
+ 0x02, 0xa0, 0x40, 0x32,
+ 0x02, 0xa0, 0x44, 0x36,
+ 0x05, 0x4d, 0x21, 0x69,
+ 0x40, 0x16, 0x52, 0x69,
+ 0xff, 0x2d, 0x57, 0x61,
+ 0xff, 0x29, 0x85, 0x70,
+ 0x02, 0x28, 0x55, 0x32,
+ 0x01, 0xea, 0x5a, 0x01,
+ 0x04, 0x44, 0xf9, 0x30,
+ 0x01, 0x44, 0xc1, 0x31,
+ 0x02, 0x28, 0x51, 0x31,
+ 0x02, 0xa8, 0x60, 0x31,
+ 0x01, 0xa4, 0x61, 0x31,
+ 0x01, 0x3d, 0x61, 0x31,
+ 0x01, 0x14, 0xd4, 0x31,
+ 0x01, 0x56, 0xad, 0x1a,
+ 0xff, 0x54, 0xa9, 0x1a,
+ 0xff, 0x55, 0xab, 0x22,
+ 0xff, 0x8d, 0x4b, 0x71,
+ 0x80, 0xac, 0x4a, 0x71,
+ 0x20, 0x16, 0x4a, 0x69,
+ 0x00, 0xac, 0xc4, 0x19,
+ 0x07, 0xe2, 0x4a, 0xf9,
+ 0x02, 0x8c, 0x51, 0x31,
+ 0x00, 0xe2, 0x2e, 0x41,
+ 0x01, 0xac, 0x08, 0x31,
+ 0x09, 0xea, 0x5a, 0x01,
+ 0x02, 0x8c, 0x51, 0x32,
+ 0xff, 0xea, 0x1a, 0x07,
+ 0x04, 0x24, 0xf9, 0x30,
+ 0x1d, 0xea, 0x5c, 0x41,
+ 0x02, 0x2c, 0x51, 0x31,
+ 0x04, 0xa8, 0xf9, 0x30,
+ 0x19, 0xea, 0x5c, 0x41,
+ 0x06, 0xea, 0x08, 0x81,
+ 0x01, 0xe2, 0x5a, 0x35,
+ 0x02, 0xf2, 0xf0, 0x31,
+ 0xff, 0xea, 0xd4, 0x0d,
+ 0x02, 0xf2, 0xf0, 0x31,
+ 0x02, 0xf8, 0xe4, 0x35,
+ 0x80, 0xea, 0xb2, 0x01,
+ 0x01, 0xe2, 0x00, 0x30,
+ 0xff, 0xea, 0xb2, 0x0d,
+ 0x01, 0xe2, 0x04, 0x30,
+ 0x01, 0xea, 0x04, 0x34,
+ 0x02, 0x20, 0xbd, 0x30,
+ 0x02, 0x20, 0xb9, 0x30,
+ 0x02, 0x20, 0x51, 0x31,
+ 0x4c, 0x93, 0xd7, 0x28,
+ 0x10, 0x92, 0x81, 0x79,
+ 0x01, 0x6b, 0xc0, 0x30,
+ 0x02, 0x64, 0xc8, 0x00,
+ 0x40, 0x3a, 0x74, 0x04,
+ 0x00, 0xe2, 0x76, 0x58,
+ 0x33, 0xea, 0x68, 0x59,
+ 0x33, 0xea, 0x00, 0x00,
+ 0x30, 0x3f, 0xc0, 0x09,
+ 0x30, 0xe0, 0x82, 0x61,
+ 0x20, 0x3f, 0x98, 0x69,
+ 0x10, 0x3f, 0x82, 0x79,
+ 0x02, 0xea, 0x7e, 0x00,
+ 0x00, 0xea, 0x68, 0x59,
+ 0x01, 0xea, 0x00, 0x30,
+ 0x02, 0x4e, 0x51, 0x35,
+ 0x01, 0xea, 0x7e, 0x00,
+ 0x11, 0xea, 0x68, 0x59,
+ 0x11, 0xea, 0x00, 0x00,
+ 0x02, 0x4e, 0x51, 0x35,
+ 0xc0, 0x4a, 0x94, 0x00,
+ 0x04, 0x41, 0xa6, 0x79,
+ 0x08, 0xea, 0x98, 0x00,
+ 0x08, 0x57, 0xae, 0x00,
+ 0x08, 0x3c, 0x78, 0x00,
+ 0xf0, 0x49, 0x74, 0x0a,
+ 0x0f, 0x67, 0xc0, 0x09,
+ 0x00, 0x3a, 0x75, 0x02,
+ 0x20, 0xea, 0x96, 0x00,
+ 0x00, 0xe2, 0x28, 0x42,
+ 0xc0, 0x4a, 0x94, 0x00,
+ 0x40, 0x3a, 0xd2, 0x69,
+ 0x02, 0x55, 0x06, 0x68,
+ 0x02, 0x56, 0xd2, 0x69,
+ 0xff, 0x5b, 0xd2, 0x61,
+ 0x02, 0x20, 0x51, 0x31,
+ 0x80, 0xea, 0xb2, 0x01,
+ 0x44, 0xea, 0x00, 0x00,
+ 0x01, 0x33, 0xc0, 0x31,
+ 0x33, 0xea, 0x00, 0x00,
+ 0xff, 0xea, 0xb2, 0x09,
+ 0xff, 0xe0, 0xc0, 0x19,
+ 0xff, 0xe0, 0xd4, 0x79,
+ 0x02, 0xac, 0x51, 0x31,
+ 0x00, 0xe2, 0xca, 0x41,
+ 0x02, 0x5e, 0x50, 0x31,
+ 0x02, 0xa8, 0xb8, 0x30,
+ 0x02, 0x5c, 0x50, 0x31,
+ 0xff, 0xad, 0xe5, 0x71,
+ 0x02, 0xac, 0x41, 0x31,
+ 0x02, 0x22, 0x51, 0x31,
+ 0x02, 0xa0, 0x5c, 0x33,
+ 0x02, 0xa0, 0x44, 0x32,
+ 0x00, 0xe2, 0xf8, 0x41,
+ 0x01, 0x4d, 0xf1, 0x79,
+ 0x01, 0x62, 0xc1, 0x31,
+ 0x00, 0x93, 0xf1, 0x61,
+ 0xfe, 0x4d, 0x9b, 0x0a,
+ 0x02, 0x60, 0x41, 0x31,
+ 0x00, 0xe2, 0xdc, 0x41,
+ 0x3d, 0x93, 0xc9, 0x29,
+ 0x01, 0xe4, 0xc8, 0x01,
+ 0x01, 0xea, 0xca, 0x01,
+ 0xff, 0xea, 0xda, 0x01,
+ 0x02, 0x20, 0x51, 0x31,
+ 0x02, 0xae, 0x41, 0x32,
+ 0xff, 0x21, 0x01, 0x62,
+ 0xff, 0xea, 0x46, 0x02,
+ 0x02, 0x5c, 0x50, 0x31,
+ 0x40, 0xea, 0x96, 0x00,
+ 0x02, 0x56, 0x20, 0x6e,
+ 0x01, 0x55, 0x20, 0x6e,
+ 0x10, 0x92, 0x0d, 0x7a,
+ 0x10, 0x40, 0x16, 0x6a,
+ 0x01, 0x56, 0x16, 0x7a,
+ 0xff, 0x97, 0x07, 0x78,
+ 0x13, 0xea, 0x6e, 0x59,
+ 0x13, 0xea, 0x04, 0x00,
+ 0x00, 0xe2, 0x06, 0x40,
+ 0xbf, 0x3a, 0x74, 0x08,
+ 0x04, 0x41, 0x1c, 0x7a,
+ 0x08, 0xea, 0x98, 0x00,
+ 0x08, 0x57, 0xae, 0x00,
+ 0x01, 0x93, 0x75, 0x32,
+ 0x01, 0x94, 0x77, 0x32,
+ 0x40, 0xea, 0x72, 0x02,
+ 0x08, 0x3c, 0x78, 0x00,
+ 0x80, 0xea, 0x6e, 0x02,
+ 0x00, 0xe2, 0xf6, 0x5b,
+ 0x01, 0x3c, 0xc1, 0x31,
+ 0x9f, 0xe0, 0x98, 0x7c,
+ 0x80, 0xe0, 0x3c, 0x72,
+ 0xa0, 0xe0, 0x78, 0x72,
+ 0xc0, 0xe0, 0x6e, 0x72,
+ 0xe0, 0xe0, 0xa8, 0x72,
+ 0x01, 0xea, 0x6e, 0x59,
+ 0x01, 0xea, 0x04, 0x00,
+ 0x00, 0xe2, 0x28, 0x42,
+ 0x80, 0x39, 0x43, 0x7a,
+ 0x03, 0xea, 0x6e, 0x59,
+ 0x03, 0xea, 0x04, 0x00,
+ 0xee, 0x00, 0x4a, 0x6a,
+ 0x05, 0xea, 0xb4, 0x00,
+ 0x33, 0xea, 0x68, 0x59,
+ 0x33, 0xea, 0x00, 0x00,
+ 0x02, 0xa8, 0x9c, 0x32,
+ 0x00, 0xe2, 0x88, 0x59,
+ 0xef, 0x96, 0xd5, 0x19,
+ 0x00, 0xe2, 0x5a, 0x52,
+ 0x09, 0x80, 0xe1, 0x30,
+ 0x02, 0xea, 0x36, 0x00,
+ 0xa8, 0xea, 0x32, 0x00,
+ 0x00, 0xe2, 0x60, 0x42,
+ 0x01, 0x96, 0xd1, 0x30,
+ 0x10, 0x80, 0x89, 0x31,
+ 0x20, 0xea, 0x32, 0x00,
+ 0xbf, 0x39, 0x73, 0x0a,
+ 0x10, 0x4c, 0x6a, 0x6a,
+ 0x20, 0x19, 0x62, 0x6a,
+ 0x20, 0x19, 0x66, 0x6a,
+ 0x02, 0x4d, 0x28, 0x6a,
+ 0x40, 0x39, 0x73, 0x02,
+ 0x00, 0xe2, 0x28, 0x42,
+ 0x80, 0x39, 0xe9, 0x6a,
+ 0x01, 0x44, 0x10, 0x33,
+ 0x08, 0x92, 0x25, 0x03,
+ 0x00, 0xe2, 0x28, 0x42,
+ 0x10, 0xea, 0x80, 0x00,
+ 0x01, 0x37, 0xc5, 0x31,
+ 0x80, 0xe2, 0x94, 0x62,
+ 0x10, 0x92, 0xb9, 0x6a,
+ 0xc0, 0x94, 0xc5, 0x01,
+ 0x40, 0x92, 0x85, 0x6a,
+ 0xbf, 0xe2, 0xc4, 0x09,
+ 0x20, 0x92, 0x99, 0x7a,
+ 0x01, 0xe2, 0x88, 0x30,
+ 0x00, 0xe2, 0xf6, 0x5b,
+ 0xa0, 0x3c, 0xa1, 0x62,
+ 0x23, 0x92, 0x89, 0x08,
+ 0x00, 0xe2, 0xf6, 0x5b,
+ 0xa0, 0x3c, 0xa1, 0x62,
+ 0x00, 0xa8, 0x98, 0x42,
+ 0xff, 0xe2, 0x98, 0x62,
+ 0x00, 0xe2, 0xb8, 0x42,
+ 0x40, 0xea, 0x98, 0x00,
+ 0x01, 0xe2, 0x88, 0x30,
+ 0x00, 0xe2, 0xf6, 0x5b,
+ 0xa0, 0x3c, 0x77, 0x72,
+ 0x40, 0xea, 0x98, 0x00,
+ 0x01, 0x37, 0x95, 0x32,
+ 0x08, 0xea, 0x6e, 0x02,
+ 0x00, 0xe2, 0x28, 0x42,
+ 0xe0, 0xea, 0x12, 0x5c,
+ 0x80, 0xe0, 0xf4, 0x6a,
+ 0x04, 0xe0, 0xa6, 0x73,
+ 0x02, 0xe0, 0xd8, 0x73,
+ 0x00, 0xea, 0x52, 0x73,
+ 0x03, 0xe0, 0xe8, 0x73,
+ 0x23, 0xe0, 0xca, 0x72,
+ 0x08, 0xe0, 0xf0, 0x72,
+ 0x00, 0xe2, 0xf6, 0x5b,
+ 0x07, 0xea, 0x6e, 0x59,
+ 0x07, 0xea, 0x04, 0x00,
+ 0x08, 0x48, 0x29, 0x72,
+ 0x04, 0x48, 0xc7, 0x62,
+ 0x01, 0x49, 0x89, 0x30,
+ 0x00, 0xe2, 0xb8, 0x42,
+ 0x01, 0x44, 0xd4, 0x31,
+ 0x00, 0xe2, 0xb8, 0x42,
+ 0x01, 0x00, 0x6c, 0x32,
+ 0x33, 0xea, 0x68, 0x59,
+ 0x33, 0xea, 0x00, 0x00,
+ 0x4c, 0x3a, 0xc1, 0x28,
+ 0x01, 0x64, 0xc0, 0x31,
+ 0x00, 0x36, 0x69, 0x59,
+ 0x01, 0x36, 0x01, 0x30,
+ 0x01, 0xe0, 0xee, 0x7a,
+ 0xa0, 0xea, 0x08, 0x5c,
+ 0x01, 0xa0, 0xee, 0x62,
+ 0x01, 0x84, 0xe3, 0x7a,
+ 0x01, 0x95, 0xf1, 0x6a,
+ 0x05, 0xea, 0x6e, 0x59,
+ 0x05, 0xea, 0x04, 0x00,
+ 0x00, 0xe2, 0xf0, 0x42,
+ 0x03, 0xea, 0x6e, 0x59,
+ 0x03, 0xea, 0x04, 0x00,
+ 0x00, 0xe2, 0xf0, 0x42,
+ 0x07, 0xea, 0x1a, 0x5c,
+ 0x01, 0x44, 0xd4, 0x31,
+ 0x00, 0xe2, 0x28, 0x42,
+ 0x3f, 0xe0, 0x76, 0x0a,
+ 0xc0, 0x3a, 0xc1, 0x09,
+ 0x00, 0x3b, 0x51, 0x01,
+ 0xff, 0xea, 0x52, 0x09,
+ 0x30, 0x3a, 0xc5, 0x09,
+ 0x3d, 0xe2, 0xc4, 0x29,
+ 0xb8, 0xe2, 0xc4, 0x19,
+ 0x01, 0xea, 0xc6, 0x01,
+ 0x02, 0xe2, 0xc8, 0x31,
+ 0x02, 0xec, 0x40, 0x31,
+ 0xff, 0xa1, 0x10, 0x73,
+ 0x02, 0xe8, 0xda, 0x31,
+ 0x02, 0xa0, 0x50, 0x31,
+ 0x00, 0xe2, 0x32, 0x43,
+ 0x80, 0x39, 0x73, 0x02,
+ 0x01, 0x44, 0xd4, 0x31,
+ 0x00, 0xe2, 0xf6, 0x5b,
+ 0x01, 0x39, 0x73, 0x02,
+ 0xe0, 0x3c, 0x4d, 0x63,
+ 0x02, 0x39, 0x73, 0x02,
+ 0x20, 0x46, 0x46, 0x63,
+ 0xff, 0xea, 0x52, 0x09,
+ 0xa8, 0xea, 0x08, 0x5c,
+ 0x04, 0x92, 0x2d, 0x7b,
+ 0x01, 0x3a, 0xc1, 0x31,
+ 0x00, 0x93, 0x2d, 0x63,
+ 0x01, 0x3b, 0xc1, 0x31,
+ 0x00, 0x94, 0x37, 0x73,
+ 0x01, 0xa9, 0x52, 0x11,
+ 0xff, 0xa9, 0x22, 0x6b,
+ 0x00, 0xe2, 0x46, 0x43,
+ 0x10, 0x39, 0x73, 0x02,
+ 0x04, 0x92, 0x47, 0x7b,
+ 0xfb, 0x92, 0x25, 0x0b,
+ 0xff, 0xea, 0x72, 0x0a,
+ 0x01, 0xa4, 0x41, 0x6b,
+ 0x02, 0xa8, 0x9c, 0x32,
+ 0x00, 0xe2, 0x88, 0x59,
+ 0x10, 0x92, 0xf1, 0x7a,
+ 0xff, 0xea, 0x1a, 0x5c,
+ 0x00, 0xe2, 0xf0, 0x42,
+ 0x04, 0xea, 0x6e, 0x59,
+ 0x04, 0xea, 0x04, 0x00,
+ 0x00, 0xe2, 0xf0, 0x42,
+ 0x04, 0xea, 0x6e, 0x59,
+ 0x04, 0xea, 0x04, 0x00,
+ 0x00, 0xe2, 0x28, 0x42,
+ 0x08, 0x92, 0xe9, 0x7a,
+ 0xc0, 0x39, 0x5d, 0x7b,
+ 0x80, 0x39, 0xe9, 0x6a,
+ 0xff, 0x88, 0x5d, 0x6b,
+ 0x40, 0x39, 0xe9, 0x6a,
+ 0x10, 0x92, 0x63, 0x7b,
+ 0x0a, 0xea, 0x6e, 0x59,
+ 0x0a, 0xea, 0x04, 0x00,
+ 0x00, 0xe2, 0x82, 0x5b,
+ 0x00, 0xe2, 0xc2, 0x43,
+ 0x50, 0x4b, 0x6a, 0x6b,
+ 0xbf, 0x3a, 0x74, 0x08,
+ 0x01, 0xe0, 0xf4, 0x31,
+ 0xff, 0xea, 0xc0, 0x09,
+ 0x01, 0x32, 0x65, 0x1a,
+ 0x00, 0x33, 0x67, 0x22,
+ 0x04, 0x4d, 0x9b, 0x02,
+ 0x01, 0xfa, 0xc0, 0x35,
+ 0x02, 0xa8, 0x90, 0x32,
+ 0x02, 0xea, 0xb4, 0x00,
+ 0x33, 0xea, 0x68, 0x59,
+ 0x33, 0xea, 0x00, 0x00,
+ 0x02, 0x48, 0x51, 0x31,
+ 0xff, 0x90, 0x85, 0x68,
+ 0xff, 0x88, 0x8f, 0x6b,
+ 0x01, 0xa4, 0x8b, 0x6b,
+ 0x02, 0xa4, 0x93, 0x6b,
+ 0x01, 0x84, 0x93, 0x7b,
+ 0x02, 0x28, 0x19, 0x33,
+ 0x02, 0xa8, 0x50, 0x36,
+ 0xff, 0x88, 0x93, 0x73,
+ 0x00, 0xe2, 0x66, 0x5b,
+ 0x02, 0xa8, 0x20, 0x33,
+ 0x04, 0xa4, 0x49, 0x03,
+ 0xff, 0xea, 0x1a, 0x03,
+ 0xff, 0x2d, 0x9f, 0x63,
+ 0x02, 0xa8, 0x58, 0x32,
+ 0x02, 0xa8, 0x5c, 0x36,
+ 0x02, 0xa8, 0x40, 0x31,
+ 0x02, 0x2e, 0x51, 0x31,
+ 0x02, 0xa0, 0x18, 0x33,
+ 0x02, 0xa0, 0x5c, 0x36,
+ 0xc0, 0x39, 0xe9, 0x6a,
+ 0x04, 0x92, 0x25, 0x03,
+ 0x20, 0x92, 0xc3, 0x6b,
+ 0x02, 0xa8, 0x40, 0x31,
+ 0xc0, 0x3a, 0xc1, 0x09,
+ 0x00, 0x3b, 0x51, 0x01,
+ 0xff, 0xea, 0x52, 0x09,
+ 0x30, 0x3a, 0xc5, 0x09,
+ 0x3d, 0xe2, 0xc4, 0x29,
+ 0xb8, 0xe2, 0xc4, 0x19,
+ 0x01, 0xea, 0xc6, 0x01,
+ 0x02, 0xe2, 0xc8, 0x31,
+ 0x02, 0xa0, 0xda, 0x31,
+ 0x02, 0xa0, 0x50, 0x31,
+ 0xf7, 0x57, 0xae, 0x08,
+ 0x08, 0xea, 0x98, 0x00,
+ 0x01, 0x44, 0xd4, 0x31,
+ 0xee, 0x00, 0xcc, 0x6b,
+ 0x02, 0xea, 0xb4, 0x00,
+ 0xc0, 0xea, 0x72, 0x02,
+ 0x09, 0x4c, 0xce, 0x7b,
+ 0x01, 0xea, 0x78, 0x02,
+ 0x08, 0x4c, 0x06, 0x68,
+ 0x0b, 0xea, 0x6e, 0x59,
+ 0x0b, 0xea, 0x04, 0x00,
+ 0x01, 0x44, 0xd4, 0x31,
+ 0x20, 0x39, 0x29, 0x7a,
+ 0x00, 0xe2, 0xe0, 0x5b,
+ 0x00, 0xe2, 0x28, 0x42,
+ 0x01, 0x84, 0xe5, 0x7b,
+ 0x01, 0xa4, 0x49, 0x07,
+ 0x08, 0x60, 0x30, 0x33,
+ 0x08, 0x80, 0x41, 0x37,
+ 0xdf, 0x39, 0x73, 0x0a,
+ 0xee, 0x00, 0xf2, 0x6b,
+ 0x05, 0xea, 0xb4, 0x00,
+ 0x33, 0xea, 0x68, 0x59,
+ 0x33, 0xea, 0x00, 0x00,
+ 0x00, 0xe2, 0x88, 0x59,
+ 0x00, 0xe2, 0xf0, 0x42,
+ 0xff, 0x42, 0x02, 0x6c,
+ 0x01, 0x41, 0xf6, 0x6b,
+ 0x02, 0x41, 0xf6, 0x7b,
+ 0xff, 0x42, 0x02, 0x6c,
+ 0x01, 0x41, 0xf6, 0x6b,
+ 0x02, 0x41, 0xf6, 0x7b,
+ 0xff, 0x42, 0x02, 0x7c,
+ 0x04, 0x4c, 0xf6, 0x6b,
+ 0xe0, 0x41, 0x78, 0x0e,
+ 0x01, 0x44, 0xd4, 0x31,
+ 0xff, 0x42, 0x0a, 0x7c,
+ 0x04, 0x4c, 0x0a, 0x6c,
+ 0xe0, 0x41, 0x78, 0x0a,
+ 0xe0, 0x3c, 0x29, 0x62,
+ 0xff, 0xea, 0xca, 0x09,
+ 0x01, 0xe2, 0xc8, 0x31,
+ 0x01, 0x46, 0xda, 0x35,
+ 0x01, 0x44, 0xd4, 0x35,
+ 0x10, 0xea, 0x80, 0x00,
+ 0x01, 0xe2, 0x6e, 0x36,
+ 0x04, 0xa6, 0x22, 0x7c,
+ 0xff, 0xea, 0x5a, 0x09,
+ 0xff, 0xea, 0x4c, 0x0d,
+ 0x01, 0xa6, 0x4e, 0x6c,
+ 0x10, 0xad, 0x84, 0x78,
+ 0x80, 0xad, 0x46, 0x6c,
+ 0x08, 0xad, 0x84, 0x68,
+ 0x20, 0x19, 0x3a, 0x7c,
+ 0x80, 0xea, 0xb2, 0x01,
+ 0x11, 0x00, 0x00, 0x10,
+ 0x02, 0xa6, 0x36, 0x7c,
+ 0xff, 0xea, 0xb2, 0x0d,
+ 0x11, 0x00, 0x00, 0x10,
+ 0xff, 0xea, 0xb2, 0x09,
+ 0x04, 0x84, 0xf9, 0x30,
+ 0x00, 0xea, 0x08, 0x81,
+ 0xff, 0xea, 0xd4, 0x09,
+ 0x02, 0x84, 0xf9, 0x88,
+ 0x0d, 0xea, 0x5a, 0x01,
+ 0x04, 0xa6, 0x4c, 0x05,
+ 0x04, 0xa6, 0x84, 0x78,
+ 0xff, 0xea, 0x5a, 0x09,
+ 0x03, 0x84, 0x59, 0x89,
+ 0x03, 0xea, 0x4c, 0x01,
+ 0x80, 0x1a, 0x84, 0x78,
+ 0x08, 0x19, 0x84, 0x78,
+ 0x08, 0xb0, 0xe0, 0x30,
+ 0x04, 0xb0, 0xe0, 0x30,
+ 0x03, 0xb0, 0xf0, 0x30,
+ 0x01, 0xb0, 0x06, 0x33,
+ 0x7f, 0x83, 0xe9, 0x08,
+ 0x04, 0xac, 0x58, 0x19,
+ 0xff, 0xea, 0xc0, 0x09,
+ 0x04, 0x84, 0x09, 0x9b,
+ 0x00, 0x85, 0x0b, 0x23,
+ 0x00, 0x86, 0x0d, 0x23,
+ 0x00, 0x87, 0x0f, 0x23,
+ 0x01, 0x84, 0xc5, 0x31,
+ 0x80, 0x83, 0x71, 0x7c,
+ 0x02, 0xe2, 0xc4, 0x01,
+ 0xff, 0xea, 0x4c, 0x09,
+ 0x01, 0xe2, 0x36, 0x30,
+ 0xc8, 0x19, 0x32, 0x00,
+ 0x88, 0x19, 0x32, 0x00,
+ 0x01, 0xac, 0xd4, 0x99,
+ 0x00, 0xe2, 0x84, 0x50,
+ 0xfe, 0xa6, 0x4c, 0x0d,
+ 0x0b, 0x98, 0xe1, 0x30,
+ 0xfd, 0xa4, 0x49, 0x09,
+ 0x80, 0xa3, 0x85, 0x7c,
+ 0x02, 0xa4, 0x48, 0x01,
+ 0x01, 0xa4, 0x36, 0x30,
+ 0xa8, 0xea, 0x32, 0x00,
+ 0xfd, 0xa4, 0x49, 0x0b,
+ 0x05, 0xa3, 0x07, 0x33,
+ 0x80, 0x83, 0x91, 0x6c,
+ 0x02, 0xea, 0x4c, 0x05,
+ 0xff, 0xea, 0x4c, 0x0d,
+ 0x00, 0xe2, 0x60, 0x59,
+ 0x02, 0xa6, 0x24, 0x6c,
+ 0x80, 0xf9, 0xf2, 0x05,
+ 0xc0, 0x39, 0x9f, 0x7c,
+ 0x03, 0xea, 0x6e, 0x59,
+ 0x03, 0xea, 0x04, 0x00,
+ 0x20, 0x39, 0xc3, 0x7c,
+ 0x01, 0x84, 0xa9, 0x6c,
+ 0x06, 0xea, 0x6e, 0x59,
+ 0x06, 0xea, 0x04, 0x00,
+ 0x00, 0xe2, 0xc6, 0x44,
+ 0x01, 0x00, 0x6c, 0x32,
+ 0xee, 0x00, 0xb2, 0x6c,
+ 0x05, 0xea, 0xb4, 0x00,
+ 0x33, 0xea, 0x68, 0x59,
+ 0x33, 0xea, 0x00, 0x00,
+ 0x80, 0x3d, 0x7a, 0x00,
+ 0xfc, 0x42, 0xb4, 0x7c,
+ 0x7f, 0x3d, 0x7a, 0x08,
+ 0x00, 0x36, 0x69, 0x59,
+ 0x01, 0x36, 0x01, 0x30,
+ 0x09, 0xea, 0x6e, 0x59,
+ 0x09, 0xea, 0x04, 0x00,
+ 0x00, 0xe2, 0x28, 0x42,
+ 0x01, 0xa4, 0xa9, 0x6c,
+ 0x00, 0xe2, 0x7c, 0x5c,
+ 0x20, 0x39, 0x73, 0x02,
+ 0x01, 0x00, 0x6c, 0x32,
+ 0x02, 0xa6, 0xce, 0x7c,
+ 0x00, 0xe2, 0x92, 0x5c,
+ 0x00, 0xe2, 0x76, 0x58,
+ 0x00, 0xe2, 0x86, 0x58,
+ 0x00, 0xe2, 0x5a, 0x58,
+ 0x00, 0x36, 0x69, 0x59,
+ 0x01, 0x36, 0x01, 0x30,
+ 0x20, 0x19, 0xce, 0x6c,
+ 0x00, 0xe2, 0xfe, 0x5c,
+ 0x04, 0x19, 0xe8, 0x6c,
+ 0x02, 0x19, 0x32, 0x00,
+ 0x01, 0x84, 0xe9, 0x7c,
+ 0x01, 0x1b, 0xe2, 0x7c,
+ 0x01, 0x1a, 0xe8, 0x6c,
+ 0x00, 0xe2, 0x98, 0x44,
+ 0x80, 0x4b, 0xee, 0x6c,
+ 0x01, 0x4c, 0xea, 0x7c,
+ 0x03, 0x42, 0x98, 0x6c,
+ 0x00, 0xe2, 0x1e, 0x5c,
+ 0x80, 0xf9, 0xf2, 0x01,
+ 0x04, 0x39, 0x29, 0x7a,
+ 0x00, 0xe2, 0x28, 0x42,
+ 0x08, 0x5d, 0x06, 0x6d,
+ 0x00, 0xe2, 0x76, 0x58,
+ 0x00, 0x36, 0x69, 0x59,
+ 0x01, 0x36, 0x01, 0x30,
+ 0x02, 0x1b, 0xf6, 0x7c,
+ 0x08, 0x5d, 0x04, 0x7d,
+ 0x03, 0x68, 0x00, 0x37,
+ 0x01, 0x84, 0x09, 0x07,
+ 0x80, 0x1b, 0x10, 0x7d,
+ 0x80, 0x84, 0x11, 0x6d,
+ 0xff, 0x85, 0x0b, 0x1b,
+ 0xff, 0x86, 0x0d, 0x23,
+ 0xff, 0x87, 0x0f, 0x23,
+ 0xf8, 0x1b, 0x08, 0x0b,
+ 0xff, 0xea, 0x06, 0x0b,
+ 0x03, 0x68, 0x00, 0x37,
+ 0x00, 0xe2, 0xd6, 0x58,
+ 0x10, 0xea, 0x18, 0x00,
+ 0xf9, 0xd9, 0xb2, 0x0d,
+ 0x01, 0xd9, 0xb2, 0x05,
+ 0x01, 0x52, 0x48, 0x31,
+ 0x20, 0xa4, 0x3a, 0x7d,
+ 0x20, 0x5b, 0x3a, 0x7d,
+ 0x80, 0xf9, 0x48, 0x7d,
+ 0x02, 0xea, 0xb4, 0x00,
+ 0x11, 0x00, 0x00, 0x10,
+ 0x04, 0x19, 0x54, 0x7d,
+ 0xdf, 0x19, 0x32, 0x08,
+ 0x60, 0x5b, 0x54, 0x6d,
+ 0x01, 0x4c, 0x2e, 0x7d,
+ 0x20, 0x19, 0x32, 0x00,
+ 0x01, 0xd9, 0xb2, 0x05,
+ 0x02, 0xea, 0xb4, 0x00,
+ 0x01, 0xd9, 0xb2, 0x05,
+ 0x10, 0x5b, 0x4c, 0x6d,
+ 0x08, 0x5b, 0x56, 0x6d,
+ 0x20, 0x5b, 0x46, 0x6d,
+ 0x02, 0x5b, 0x76, 0x6d,
+ 0x0e, 0xea, 0x6e, 0x59,
+ 0x0e, 0xea, 0x04, 0x00,
+ 0x80, 0xf9, 0x36, 0x6d,
+ 0xdf, 0x5c, 0xb8, 0x08,
+ 0x01, 0xd9, 0xb2, 0x05,
+ 0x01, 0xa4, 0x37, 0x6e,
+ 0x00, 0xe2, 0x7c, 0x5c,
+ 0x00, 0xe2, 0x80, 0x5d,
+ 0x01, 0x90, 0x21, 0x1b,
+ 0x01, 0xd9, 0xb2, 0x05,
+ 0x00, 0xe2, 0x66, 0x5b,
+ 0xf3, 0x96, 0xd5, 0x19,
+ 0x00, 0xe2, 0x64, 0x55,
+ 0x80, 0x96, 0x65, 0x6d,
+ 0x0f, 0xea, 0x6e, 0x59,
+ 0x0f, 0xea, 0x04, 0x00,
+ 0x00, 0xe2, 0x6c, 0x45,
+ 0x04, 0x8c, 0xe1, 0x30,
+ 0x01, 0xea, 0xf2, 0x00,
+ 0x02, 0xea, 0x36, 0x00,
+ 0xa8, 0xea, 0x32, 0x00,
+ 0xff, 0x97, 0x73, 0x7d,
+ 0x14, 0xea, 0x6e, 0x59,
+ 0x14, 0xea, 0x04, 0x00,
+ 0x00, 0xe2, 0xe2, 0x5d,
+ 0x01, 0xd9, 0xb2, 0x05,
+ 0x09, 0x80, 0xe1, 0x30,
+ 0x02, 0xea, 0x36, 0x00,
+ 0xa8, 0xea, 0x32, 0x00,
+ 0x00, 0xe2, 0xda, 0x5d,
+ 0x01, 0xd9, 0xb2, 0x05,
+ 0x02, 0xa6, 0x90, 0x7d,
+ 0x00, 0xe2, 0x60, 0x59,
+ 0x20, 0x5b, 0x9e, 0x6d,
+ 0xfc, 0x42, 0x8a, 0x7d,
+ 0x10, 0x40, 0x8c, 0x6d,
+ 0x20, 0x4d, 0x8e, 0x7d,
+ 0x08, 0x5d, 0x9e, 0x6d,
+ 0x02, 0xa6, 0x24, 0x6c,
+ 0x00, 0xe2, 0x60, 0x59,
+ 0x20, 0x5b, 0x9e, 0x6d,
+ 0x01, 0x1b, 0xbe, 0x6d,
+ 0xfc, 0x42, 0x9a, 0x7d,
+ 0x10, 0x40, 0x9c, 0x6d,
+ 0x20, 0x4d, 0x84, 0x78,
+ 0x08, 0x5d, 0x84, 0x78,
+ 0x02, 0x19, 0x32, 0x00,
+ 0x01, 0x5b, 0x40, 0x31,
+ 0x00, 0xe2, 0xfe, 0x5c,
+ 0x00, 0xe2, 0xe0, 0x5b,
+ 0x20, 0xea, 0xb6, 0x00,
+ 0x00, 0xe2, 0x1e, 0x5c,
+ 0x20, 0x5c, 0xb8, 0x00,
+ 0x04, 0x19, 0xb4, 0x6d,
+ 0x01, 0x1a, 0xb4, 0x6d,
+ 0x00, 0xe2, 0x60, 0x59,
+ 0x01, 0x1a, 0x84, 0x78,
+ 0x80, 0xf9, 0xf2, 0x01,
+ 0x20, 0xa0, 0x18, 0x7e,
+ 0xff, 0x90, 0x21, 0x1b,
+ 0x08, 0x92, 0x77, 0x6b,
+ 0x02, 0xea, 0xb4, 0x04,
+ 0x01, 0xa4, 0x49, 0x03,
+ 0x40, 0x5b, 0xce, 0x6d,
+ 0x00, 0xe2, 0x60, 0x59,
+ 0x40, 0x5b, 0xce, 0x6d,
+ 0x04, 0x5d, 0x38, 0x7e,
+ 0x01, 0x1a, 0x38, 0x7e,
+ 0x20, 0x4d, 0x84, 0x78,
+ 0x40, 0x5b, 0x18, 0x7e,
+ 0x04, 0x5d, 0x38, 0x7e,
+ 0x01, 0x1a, 0x38, 0x7e,
+ 0x80, 0xf9, 0xf2, 0x01,
+ 0xff, 0x90, 0x21, 0x1b,
+ 0x08, 0x92, 0x77, 0x6b,
+ 0x02, 0xea, 0xb4, 0x04,
+ 0x00, 0xe2, 0x60, 0x59,
+ 0x01, 0x1b, 0x84, 0x78,
+ 0x80, 0xf9, 0xf2, 0x01,
+ 0x02, 0xea, 0xb4, 0x04,
+ 0x00, 0xe2, 0x60, 0x59,
+ 0x01, 0x1b, 0xf6, 0x6d,
+ 0x40, 0x5b, 0x04, 0x7e,
+ 0x01, 0x1b, 0xf6, 0x6d,
+ 0x02, 0x19, 0x32, 0x00,
+ 0x01, 0x1a, 0x84, 0x78,
+ 0x80, 0xf9, 0xf2, 0x01,
+ 0xff, 0xea, 0x10, 0x03,
+ 0x08, 0x92, 0x25, 0x03,
+ 0x00, 0xe2, 0x76, 0x43,
+ 0x01, 0x1a, 0x00, 0x7e,
+ 0x40, 0x5b, 0xfc, 0x7d,
+ 0x01, 0x1a, 0xea, 0x6d,
+ 0xfc, 0x42, 0x84, 0x78,
+ 0x01, 0x1a, 0x04, 0x6e,
+ 0x10, 0xea, 0x6e, 0x59,
+ 0x10, 0xea, 0x04, 0x00,
+ 0xfc, 0x42, 0x84, 0x78,
+ 0x10, 0x40, 0x0a, 0x6e,
+ 0x20, 0x4d, 0x84, 0x78,
+ 0x40, 0x5b, 0xea, 0x6d,
+ 0x01, 0x1a, 0x84, 0x78,
+ 0x01, 0x90, 0x21, 0x1b,
+ 0x30, 0x3f, 0xc0, 0x09,
+ 0x30, 0xe0, 0x84, 0x60,
+ 0x40, 0x4b, 0x84, 0x68,
+ 0xff, 0xea, 0x52, 0x01,
+ 0xee, 0x00, 0x20, 0x6e,
+ 0x80, 0xf9, 0xf2, 0x01,
+ 0xff, 0x90, 0x21, 0x1b,
+ 0x02, 0xea, 0xb4, 0x00,
+ 0x20, 0xea, 0x9a, 0x00,
+ 0x04, 0x41, 0x26, 0x7e,
+ 0x08, 0xea, 0x98, 0x00,
+ 0x08, 0x57, 0xae, 0x00,
+ 0xf3, 0x42, 0x30, 0x6e,
+ 0x12, 0xea, 0x6e, 0x59,
+ 0x12, 0xea, 0x04, 0x00,
+ 0x00, 0xe2, 0x28, 0x42,
+ 0x0d, 0xea, 0x6e, 0x59,
+ 0x0d, 0xea, 0x04, 0x00,
+ 0x00, 0xe2, 0x28, 0x42,
+ 0x01, 0x90, 0x21, 0x1b,
+ 0x11, 0xea, 0x6e, 0x59,
+ 0x11, 0xea, 0x04, 0x00,
+ 0x00, 0xe2, 0x66, 0x5b,
+ 0x08, 0x5a, 0xb4, 0x00,
+ 0x00, 0xe2, 0x5e, 0x5e,
+ 0xa8, 0xea, 0x32, 0x00,
+ 0x00, 0xe2, 0x60, 0x59,
+ 0x80, 0x1a, 0x4c, 0x7e,
+ 0x00, 0xe2, 0x5e, 0x5e,
+ 0x80, 0x19, 0x32, 0x00,
+ 0x40, 0x5b, 0x52, 0x6e,
+ 0x08, 0x5a, 0x52, 0x7e,
+ 0x20, 0x4d, 0x84, 0x78,
+ 0x02, 0x84, 0x09, 0x03,
+ 0x40, 0x5b, 0x18, 0x7e,
+ 0xff, 0x90, 0x21, 0x1b,
+ 0x80, 0xf9, 0xf2, 0x01,
+ 0x08, 0x92, 0x77, 0x6b,
+ 0x02, 0xea, 0xb4, 0x04,
+ 0x01, 0x40, 0xe1, 0x30,
+ 0x05, 0x41, 0xe3, 0x98,
+ 0x01, 0xe0, 0xf4, 0x31,
+ 0xff, 0xea, 0xc0, 0x09,
+ 0x00, 0x42, 0xe5, 0x20,
+ 0x00, 0x43, 0xe7, 0x20,
+ 0x01, 0xfa, 0xc0, 0x31,
+ 0x04, 0xea, 0xe8, 0x30,
+ 0xff, 0xea, 0xf0, 0x08,
+ 0x02, 0xea, 0xf2, 0x00,
+ 0xff, 0xea, 0xf4, 0x0c
+};
+
+typedef int ahd_patch_func_t (struct ahd_softc *ahd);
+static ahd_patch_func_t ahd_patch23_func;
+
+static int
+ahd_patch23_func(struct ahd_softc *ahd)
+{
+ return ((ahd->bugs & AHD_PKT_BITBUCKET_BUG) != 0);
+}
+
+static ahd_patch_func_t ahd_patch22_func;
+
+static int
+ahd_patch22_func(struct ahd_softc *ahd)
+{
+ return ((ahd->bugs & AHD_PKT_BITBUCKET_BUG) == 0);
+}
+
+static ahd_patch_func_t ahd_patch21_func;
+
+static int
+ahd_patch21_func(struct ahd_softc *ahd)
+{
+ return ((ahd->flags & AHD_INITIATORROLE) != 0);
+}
+
+static ahd_patch_func_t ahd_patch20_func;
+
+static int
+ahd_patch20_func(struct ahd_softc *ahd)
+{
+ return ((ahd->flags & AHD_TARGETROLE) != 0);
+}
+
+static ahd_patch_func_t ahd_patch19_func;
+
+static int
+ahd_patch19_func(struct ahd_softc *ahd)
+{
+ return ((ahd->bugs & AHD_AUTOFLUSH_BUG) != 0);
+}
+
+static ahd_patch_func_t ahd_patch18_func;
+
+static int
+ahd_patch18_func(struct ahd_softc *ahd)
+{
+ return ((ahd->features & AHD_NEW_DFCNTRL_OPTS) != 0);
+}
+
+static ahd_patch_func_t ahd_patch17_func;
+
+static int
+ahd_patch17_func(struct ahd_softc *ahd)
+{
+ return ((ahd->flags & AHD_39BIT_ADDRESSING) != 0);
+}
+
+static ahd_patch_func_t ahd_patch16_func;
+
+static int
+ahd_patch16_func(struct ahd_softc *ahd)
+{
+ return ((ahd->flags & AHD_64BIT_ADDRESSING) != 0);
+}
+
+static ahd_patch_func_t ahd_patch15_func;
+
+static int
+ahd_patch15_func(struct ahd_softc *ahd)
+{
+ return ((ahd->features & AHD_NEW_DFCNTRL_OPTS) == 0);
+}
+
+static ahd_patch_func_t ahd_patch14_func;
+
+static int
+ahd_patch14_func(struct ahd_softc *ahd)
+{
+ return ((ahd->bugs & AHD_REG_SLOW_SETTLE_BUG) != 0);
+}
+
+static ahd_patch_func_t ahd_patch13_func;
+
+static int
+ahd_patch13_func(struct ahd_softc *ahd)
+{
+ return ((ahd->features & AHD_RTI) == 0);
+}
+
+static ahd_patch_func_t ahd_patch12_func;
+
+static int
+ahd_patch12_func(struct ahd_softc *ahd)
+{
+ return ((ahd->bugs & AHD_EARLY_REQ_BUG) != 0);
+}
+
+static ahd_patch_func_t ahd_patch11_func;
+
+static int
+ahd_patch11_func(struct ahd_softc *ahd)
+{
+ return ((ahd->bugs & AHD_BUSFREEREV_BUG) == 0);
+}
+
+static ahd_patch_func_t ahd_patch10_func;
+
+static int
+ahd_patch10_func(struct ahd_softc *ahd)
+{
+ return ((ahd->flags & AHD_SEQUENCER_DEBUG) != 0);
+}
+
+static ahd_patch_func_t ahd_patch9_func;
+
+static int
+ahd_patch9_func(struct ahd_softc *ahd)
+{
+ return ((ahd->features & AHD_FAST_CDB_DELIVERY) != 0);
+}
+
+static ahd_patch_func_t ahd_patch8_func;
+
+static int
+ahd_patch8_func(struct ahd_softc *ahd)
+{
+ return ((ahd->bugs & AHD_LQO_ATNO_BUG) != 0);
+}
+
+static ahd_patch_func_t ahd_patch7_func;
+
+static int
+ahd_patch7_func(struct ahd_softc *ahd)
+{
+ return ((ahd->bugs & AHD_BUSFREEREV_BUG) != 0);
+}
+
+static ahd_patch_func_t ahd_patch6_func;
+
+static int
+ahd_patch6_func(struct ahd_softc *ahd)
+{
+ return ((ahd->bugs & AHD_NONPACKFIFO_BUG) != 0);
+}
+
+static ahd_patch_func_t ahd_patch5_func;
+
+static int
+ahd_patch5_func(struct ahd_softc *ahd)
+{
+ return ((ahd->bugs & AHD_SENT_SCB_UPDATE_BUG) != 0);
+}
+
+static ahd_patch_func_t ahd_patch4_func;
+
+static int
+ahd_patch4_func(struct ahd_softc *ahd)
+{
+ return ((ahd->bugs & AHD_PKT_LUN_BUG) != 0);
+}
+
+static ahd_patch_func_t ahd_patch3_func;
+
+static int
+ahd_patch3_func(struct ahd_softc *ahd)
+{
+ return ((ahd->bugs & AHD_FAINT_LED_BUG) != 0);
+}
+
+static ahd_patch_func_t ahd_patch2_func;
+
+static int
+ahd_patch2_func(struct ahd_softc *ahd)
+{
+ return ((ahd->bugs & AHD_SET_MODE_BUG) != 0);
+}
+
+static ahd_patch_func_t ahd_patch1_func;
+
+static int
+ahd_patch1_func(struct ahd_softc *ahd)
+{
+ return ((ahd->bugs & AHD_INTCOLLISION_BUG) != 0);
+}
+
+static ahd_patch_func_t ahd_patch0_func;
+
+static int
+ahd_patch0_func(struct ahd_softc *ahd)
+{
+ return (0);
+}
+
+static struct patch {
+ ahd_patch_func_t *patch_func;
+ uint32_t begin :10,
+ skip_instr :10,
+ skip_patch :12;
+} patches[] = {
+ { ahd_patch1_func, 0, 3, 3 },
+ { ahd_patch1_func, 1, 1, 2 },
+ { ahd_patch0_func, 2, 1, 1 },
+ { ahd_patch1_func, 3, 3, 3 },
+ { ahd_patch1_func, 4, 1, 2 },
+ { ahd_patch0_func, 5, 1, 1 },
+ { ahd_patch2_func, 6, 1, 2 },
+ { ahd_patch0_func, 7, 1, 1 },
+ { ahd_patch3_func, 36, 5, 1 },
+ { ahd_patch2_func, 45, 1, 2 },
+ { ahd_patch0_func, 46, 1, 1 },
+ { ahd_patch1_func, 53, 1, 2 },
+ { ahd_patch0_func, 54, 1, 1 },
+ { ahd_patch2_func, 59, 1, 2 },
+ { ahd_patch0_func, 60, 1, 1 },
+ { ahd_patch2_func, 63, 1, 2 },
+ { ahd_patch0_func, 64, 1, 1 },
+ { ahd_patch2_func, 67, 1, 2 },
+ { ahd_patch0_func, 68, 1, 1 },
+ { ahd_patch4_func, 115, 1, 1 },
+ { ahd_patch2_func, 180, 3, 1 },
+ { ahd_patch1_func, 183, 2, 1 },
+ { ahd_patch5_func, 185, 1, 1 },
+ { ahd_patch2_func, 194, 1, 2 },
+ { ahd_patch0_func, 195, 1, 1 },
+ { ahd_patch6_func, 196, 2, 2 },
+ { ahd_patch0_func, 198, 6, 3 },
+ { ahd_patch2_func, 201, 1, 2 },
+ { ahd_patch0_func, 202, 1, 1 },
+ { ahd_patch2_func, 205, 1, 2 },
+ { ahd_patch0_func, 206, 1, 1 },
+ { ahd_patch3_func, 208, 1, 1 },
+ { ahd_patch7_func, 209, 3, 1 },
+ { ahd_patch3_func, 218, 1, 1 },
+ { ahd_patch5_func, 219, 16, 2 },
+ { ahd_patch0_func, 235, 1, 1 },
+ { ahd_patch8_func, 260, 2, 1 },
+ { ahd_patch1_func, 264, 1, 2 },
+ { ahd_patch0_func, 265, 1, 1 },
+ { ahd_patch7_func, 268, 3, 1 },
+ { ahd_patch1_func, 283, 1, 2 },
+ { ahd_patch0_func, 284, 1, 1 },
+ { ahd_patch1_func, 287, 1, 2 },
+ { ahd_patch0_func, 288, 1, 1 },
+ { ahd_patch2_func, 291, 1, 2 },
+ { ahd_patch0_func, 292, 1, 1 },
+ { ahd_patch9_func, 305, 2, 2 },
+ { ahd_patch0_func, 307, 1, 1 },
+ { ahd_patch1_func, 349, 1, 2 },
+ { ahd_patch0_func, 350, 1, 1 },
+ { ahd_patch2_func, 358, 1, 2 },
+ { ahd_patch0_func, 359, 1, 1 },
+ { ahd_patch2_func, 362, 1, 2 },
+ { ahd_patch0_func, 363, 1, 1 },
+ { ahd_patch1_func, 369, 1, 2 },
+ { ahd_patch0_func, 370, 1, 1 },
+ { ahd_patch1_func, 372, 1, 2 },
+ { ahd_patch0_func, 373, 1, 1 },
+ { ahd_patch10_func, 392, 1, 1 },
+ { ahd_patch10_func, 395, 1, 1 },
+ { ahd_patch10_func, 397, 1, 1 },
+ { ahd_patch10_func, 409, 1, 1 },
+ { ahd_patch1_func, 419, 1, 2 },
+ { ahd_patch0_func, 420, 1, 1 },
+ { ahd_patch1_func, 422, 1, 2 },
+ { ahd_patch0_func, 423, 1, 1 },
+ { ahd_patch1_func, 431, 1, 2 },
+ { ahd_patch0_func, 432, 1, 1 },
+ { ahd_patch2_func, 445, 1, 2 },
+ { ahd_patch0_func, 446, 1, 1 },
+ { ahd_patch11_func, 482, 1, 1 },
+ { ahd_patch1_func, 490, 1, 2 },
+ { ahd_patch0_func, 491, 1, 1 },
+ { ahd_patch2_func, 503, 1, 2 },
+ { ahd_patch0_func, 504, 1, 1 },
+ { ahd_patch12_func, 507, 6, 2 },
+ { ahd_patch0_func, 513, 1, 1 },
+ { ahd_patch13_func, 534, 7, 1 },
+ { ahd_patch14_func, 543, 1, 1 },
+ { ahd_patch15_func, 552, 1, 1 },
+ { ahd_patch16_func, 553, 1, 2 },
+ { ahd_patch0_func, 554, 1, 1 },
+ { ahd_patch17_func, 557, 1, 1 },
+ { ahd_patch16_func, 558, 1, 1 },
+ { ahd_patch18_func, 569, 1, 2 },
+ { ahd_patch0_func, 570, 1, 1 },
+ { ahd_patch1_func, 589, 1, 2 },
+ { ahd_patch0_func, 590, 1, 1 },
+ { ahd_patch1_func, 593, 1, 2 },
+ { ahd_patch0_func, 594, 1, 1 },
+ { ahd_patch2_func, 599, 1, 2 },
+ { ahd_patch0_func, 600, 1, 1 },
+ { ahd_patch2_func, 604, 1, 2 },
+ { ahd_patch0_func, 605, 1, 1 },
+ { ahd_patch1_func, 606, 1, 2 },
+ { ahd_patch0_func, 607, 1, 1 },
+ { ahd_patch2_func, 618, 1, 2 },
+ { ahd_patch0_func, 619, 1, 1 },
+ { ahd_patch19_func, 623, 1, 1 },
+ { ahd_patch20_func, 628, 1, 1 },
+ { ahd_patch21_func, 629, 2, 1 },
+ { ahd_patch20_func, 633, 1, 2 },
+ { ahd_patch0_func, 634, 1, 1 },
+ { ahd_patch2_func, 637, 1, 2 },
+ { ahd_patch0_func, 638, 1, 1 },
+ { ahd_patch2_func, 653, 1, 2 },
+ { ahd_patch0_func, 654, 1, 1 },
+ { ahd_patch13_func, 655, 14, 1 },
+ { ahd_patch1_func, 673, 1, 2 },
+ { ahd_patch0_func, 674, 1, 1 },
+ { ahd_patch13_func, 675, 1, 1 },
+ { ahd_patch1_func, 687, 1, 2 },
+ { ahd_patch0_func, 688, 1, 1 },
+ { ahd_patch1_func, 695, 1, 2 },
+ { ahd_patch0_func, 696, 1, 1 },
+ { ahd_patch19_func, 719, 1, 1 },
+ { ahd_patch19_func, 757, 1, 1 },
+ { ahd_patch1_func, 768, 1, 2 },
+ { ahd_patch0_func, 769, 1, 1 },
+ { ahd_patch7_func, 785, 3, 1 },
+ { ahd_patch1_func, 789, 1, 2 },
+ { ahd_patch0_func, 790, 1, 1 },
+ { ahd_patch1_func, 792, 1, 2 },
+ { ahd_patch0_func, 793, 1, 1 },
+ { ahd_patch1_func, 796, 1, 2 },
+ { ahd_patch0_func, 797, 1, 1 },
+ { ahd_patch22_func, 799, 1, 2 },
+ { ahd_patch0_func, 800, 2, 1 },
+ { ahd_patch23_func, 803, 4, 2 },
+ { ahd_patch0_func, 807, 1, 1 },
+ { ahd_patch23_func, 815, 11, 1 }
+};
+
+static struct cs {
+ uint16_t begin;
+ uint16_t end;
+} critical_sections[] = {
+ { 17, 30 },
+ { 47, 58 },
+ { 61, 63 },
+ { 65, 66 },
+ { 72, 92 },
+ { 110, 142 },
+ { 143, 180 },
+ { 185, 193 },
+ { 218, 274 },
+ { 435, 443 },
+ { 453, 455 },
+ { 458, 467 },
+ { 719, 749 },
+ { 759, 763 }
+};
+
+static const int num_critical_sections = sizeof(critical_sections)
+ / sizeof(*critical_sections);
Property changes on: trunk/sys/dev/aic7xxx/aic79xx_seq.h
___________________________________________________________________
Added: svn:eol-style
## -0,0 +1 ##
+native
\ No newline at end of property
Added: svn:keywords
## -0,0 +1 ##
+MidnightBSD=%H
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+text/plain
\ No newline at end of property
Modified: trunk/sys/dev/aic7xxx/aic7xxx.c
===================================================================
--- trunk/sys/dev/aic7xxx/aic7xxx.c 2018-05-28 00:25:20 UTC (rev 10127)
+++ trunk/sys/dev/aic7xxx/aic7xxx.c 2018-05-28 00:27:43 UTC (rev 10128)
@@ -1,3 +1,4 @@
+/* $MidnightBSD$ */
/*-
* Core routines and tables shareable across OS platforms.
*
@@ -37,8 +38,7 @@
* IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGES.
*
- * $MidnightBSD$
- * $Id: aic7xxx.c,v 1.5 2012-08-06 01:19:11 laffer1 Exp $
+ * $Id: //depot/aic7xxx/aic7xxx/aic7xxx.c#155 $
*/
#ifdef __linux__
@@ -47,6 +47,7 @@
#include "aicasm/aicasm_insformat.h"
#else
#include <sys/cdefs.h>
+__FBSDID("$FreeBSD: stable/10/sys/dev/aic7xxx/aic7xxx.c 315140 2017-03-12 06:20:28Z mav $");
#include <dev/aic7xxx/aic7xxx_osm.h>
#include <dev/aic7xxx/aic7xxx_inline.h>
#include <dev/aic7xxx/aicasm/aicasm_insformat.h>
@@ -116,7 +117,7 @@
/*
* Valid SCSIRATE values. (p. 3-17)
- * Provides a mapping of tranfer periods in ns to the proper value to
+ * Provides a mapping of transfer periods in ns to the proper value to
* stick in the scsixfer reg.
*/
static struct ahc_syncrate ahc_syncrates[] =
@@ -682,7 +683,7 @@
* that requires host assistance for completion.
* While handling the message phase(s), we will be
* notified by the sequencer after each byte is
- * transfered so we can track bus phase changes.
+ * transferred so we can track bus phase changes.
*
* If this is the first time we've seen a HOST_MSG_LOOP
* interrupt, initialize the state of the host message
@@ -925,7 +926,7 @@
scbptr, ahc_inb(ahc, ARG_1),
ahc->scb_data->hscbs[scbptr].tag);
ahc_dump_card_state(ahc);
- panic("for saftey");
+ panic("for safety");
break;
}
case OUT_OF_RANGE:
@@ -1171,7 +1172,7 @@
/*
* Although the driver does not care about the
* 'Selection in Progress' status bit, the busy
- * LED does. SELINGO is only cleared by a sucessfull
+ * LED does. SELINGO is only cleared by a successful
* selection, so we must manually clear it to insure
* the LED turns off just incase no future successful
* selections occur (e.g. no devices on the bus).
@@ -1279,6 +1280,7 @@
printerror = 0;
} else if (ahc_sent_msg(ahc, AHCMSG_1B,
MSG_BUS_DEV_RESET, TRUE)) {
+#ifdef __FreeBSD__
/*
* Don't mark the user's request for this BDR
* as completing with CAM_BDR_SENT. CAM3
@@ -1292,6 +1294,7 @@
ROLE_INITIATOR)) {
aic_set_transaction_status(scb, CAM_REQ_CMP);
}
+#endif
ahc_compile_devinfo(&devinfo,
initiator_role_id,
target,
@@ -1379,7 +1382,7 @@
if (lastphase != P_BUSFREE) {
/*
* Renegotiate with this device at the
- * next oportunity just in case this busfree
+ * next opportunity just in case this busfree
* is due to a negotiation mismatch with the
* device.
*/
@@ -1855,7 +1858,7 @@
/*
* Update the bitmask of targets for which the controller should
- * negotiate with at the next convenient oportunity. This currently
+ * negotiate with at the next convenient opportunity. This currently
* means the next time we send the initial identify messages for
* a new transaction.
*/
@@ -3625,7 +3628,7 @@
/*
* Requeue all tagged commands for this target
- * currently in our posession so they can be
+ * currently in our possession so they can be
* converted to untagged commands.
*/
ahc_search_qinfifo(ahc, SCB_GET_TARGET(ahc, scb),
@@ -3900,11 +3903,23 @@
struct ahc_softc *ahc;
int i;
+#ifndef __FreeBSD__
+ ahc = malloc(sizeof(*ahc), M_DEVBUF, M_NOWAIT);
+ if (!ahc) {
+ printf("aic7xxx: cannot malloc softc!\n");
+ free(name, M_DEVBUF);
+ return NULL;
+ }
+#else
ahc = device_get_softc((device_t)platform_arg);
+#endif
memset(ahc, 0, sizeof(*ahc));
ahc->seep_config = malloc(sizeof(*ahc->seep_config),
M_DEVBUF, M_NOWAIT);
if (ahc->seep_config == NULL) {
+#ifndef __FreeBSD__
+ free(ahc, M_DEVBUF);
+#endif
free(name, M_DEVBUF);
return (NULL);
}
@@ -4097,6 +4112,9 @@
free(ahc->name, M_DEVBUF);
if (ahc->seep_config != NULL)
free(ahc->seep_config, M_DEVBUF);
+#ifndef __FreeBSD__
+ free(ahc, M_DEVBUF);
+#endif
return;
}
@@ -4121,7 +4139,7 @@
/*
* Reset the controller and record some information about it
* that is only available just after a reset. If "reinit" is
- * non-zero, this reset occured after initial configuration
+ * non-zero, this reset occurred after initial configuration
* and the caller requests that the chip be fully reinitialized
* to a runable state. Chip interrupts are *not* enabled after
* a reinitialization. The caller must enable interrupts via
@@ -4443,7 +4461,7 @@
ahc->next_queued_scb = ahc_get_scb(ahc);
/*
- * Note that we were successfull
+ * Note that we were successful
*/
return (0);
@@ -6532,7 +6550,7 @@
cur_patch += cur_patch->skip_patch;
} else {
/* Accepted this patch. Advance to the next
- * one and wait for our intruction pointer to
+ * one and wait for our instruction pointer to
* hit this point.
*/
cur_patch++;
@@ -7236,7 +7254,7 @@
ahc_outb(ahc, SCBPTR, saved_scbptr);
aic_scb_timer_reset(scb, 2 * 1000);
} else {
- /* Go "immediatly" to the bus reset */
+ /* Go "immediately" to the bus reset */
/* This shouldn't happen */
ahc_set_recoveryscb(ahc, scb);
ahc_print_path(ahc, scb);
@@ -7336,7 +7354,8 @@
else
our_id = ahc->our_id_b;
- if (ccb->ccb_h.target_id != our_id) {
+ if (ccb->ccb_h.target_id != our_id
+ && ccb->ccb_h.target_id != CAM_TARGET_WILDCARD) {
/*
* our_id represents our initiator ID, or
* the ID of the first target to have an
@@ -7825,9 +7844,9 @@
/* Tag was included */
atio->tag_action = *byte++;
atio->tag_id = *byte++;
- atio->ccb_h.flags = CAM_TAG_ACTION_VALID;
+ atio->ccb_h.flags |= CAM_TAG_ACTION_VALID;
} else {
- atio->ccb_h.flags = 0;
+ atio->ccb_h.flags &= ~CAM_TAG_ACTION_VALID;
}
byte++;
Modified: trunk/sys/dev/aic7xxx/aic7xxx.h
===================================================================
--- trunk/sys/dev/aic7xxx/aic7xxx.h 2018-05-28 00:25:20 UTC (rev 10127)
+++ trunk/sys/dev/aic7xxx/aic7xxx.h 2018-05-28 00:27:43 UTC (rev 10128)
@@ -1,3 +1,4 @@
+/* $MidnightBSD$ */
/*-
* Core definitions and data structures shareable across OS platforms.
*
@@ -37,9 +38,9 @@
* IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGES.
*
- * $Id: aic7xxx.h,v 1.1.1.4 2012-07-21 15:16:50 laffer1 Exp $
+ * $Id: //depot/aic7xxx/aic7xxx/aic7xxx.h#85 $
*
- * $FreeBSD$
+ * $FreeBSD: stable/10/sys/dev/aic7xxx/aic7xxx.h 300060 2016-05-17 15:18:01Z pfg $
*/
#ifndef _AIC7XXX_H_
@@ -448,7 +449,7 @@
* each S/G element is expired, its datacnt field is checked to see
* if the LAST_SEG flag is set. If so, SG_LIST_NULL is set in the
* residual sg ptr and the transfer is considered complete. If the
- * sequencer determines that there is a residual in the tranfer, it
+ * sequencer determines that there is a residual in the transfer, it
* will set the SG_RESID_VALID flag in sgptr and dma the scb back into
* host memory. To sumarize:
*
@@ -456,7 +457,7 @@
* o A residual has occurred if SG_FULL_RESID is set in sgptr,
* or residual_sgptr does not have SG_LIST_NULL set.
*
- * o We are transfering the last segment if residual_datacnt has
+ * o We are transferring the last segment if residual_datacnt has
* the SG_LAST_SEG flag set.
*
* Host:
@@ -510,7 +511,7 @@
*/
/*
- * Definition of a scatter/gather element as transfered to the controller.
+ * Definition of a scatter/gather element as transferred to the controller.
* The aic7xxx chips only support a 24bit length. We use the top byte of
* the length to store additional address bits and a flag to indicate
* that a given segment terminates the transfer. This gives us an
@@ -768,7 +769,7 @@
#define AHC_ULTRA2_XFER_PERIOD 0x0a
/*
- * Indexes into our table of syncronous transfer rates.
+ * Indexes into our table of synchronous transfer rates.
*/
#define AHC_SYNCRATE_DT 0
#define AHC_SYNCRATE_ULTRA2 1
Modified: trunk/sys/dev/aic7xxx/aic7xxx.reg
===================================================================
--- trunk/sys/dev/aic7xxx/aic7xxx.reg 2018-05-28 00:25:20 UTC (rev 10127)
+++ trunk/sys/dev/aic7xxx/aic7xxx.reg 2018-05-28 00:27:43 UTC (rev 10128)
@@ -37,9 +37,9 @@
* IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGES.
*
- * $FreeBSD$
+ * $FreeBSD: stable/10/sys/dev/aic7xxx/aic7xxx.reg 300060 2016-05-17 15:18:01Z pfg $
*/
-VERSION = "$Id: aic7xxx.reg,v 1.1.1.3 2012-07-21 15:16:50 laffer1 Exp $"
+VERSION = "$Id: //depot/aic7xxx/aic7xxx/aic7xxx.reg#40 $"
/*
* This file is processed by the aic7xxx_asm utility for use in assembling
@@ -329,7 +329,7 @@
address 0x00d
access_mode RO
field OVERRUN 0x80
- field SHVALID 0x40 /* Shaddow Layer non-zero */
+ field SHVALID 0x40 /* Shadow Layer non-zero */
field EXP_ACTIVE 0x10 /* SCSI Expander Active */
field CRCVALERR 0x08 /* CRC doesn't match (U3 only) */
field CRCENDERR 0x04 /* No terminal CRC packet (U3 only) */
Property changes on: trunk/sys/dev/aic7xxx/aic7xxx.reg
___________________________________________________________________
Added: mnbsd:nokeywords
## -0,0 +1 ##
+MidnightBSD=%H
\ No newline at end of property
Modified: trunk/sys/dev/aic7xxx/aic7xxx.seq
===================================================================
--- trunk/sys/dev/aic7xxx/aic7xxx.seq 2018-05-28 00:25:20 UTC (rev 10127)
+++ trunk/sys/dev/aic7xxx/aic7xxx.seq 2018-05-28 00:27:43 UTC (rev 10128)
@@ -37,10 +37,10 @@
* IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGES.
*
- * $FreeBSD$
+ * $FreeBSD: stable/10/sys/dev/aic7xxx/aic7xxx.seq 300060 2016-05-17 15:18:01Z pfg $
*/
-VERSION = "$Id: aic7xxx.seq,v 1.1.1.4 2012-07-21 15:16:50 laffer1 Exp $"
+VERSION = "$Id: //depot/aic7xxx/aic7xxx/aic7xxx.seq#58 $"
PATCH_ARG_LIST = "struct ahc_softc *ahc"
PREFIX = "ahc_"
@@ -60,7 +60,7 @@
* use byte 27 of the SCB as a psuedo-next pointer and to thread a list
* of SCBs that are awaiting selection. Since 0-0xfe are valid SCB indexes,
* SCB_LIST_NULL is 0xff which is out of range. An entry is also added to
- * this list everytime a request sense occurs or after completing a non-tagged
+ * this list every time a request sense occurs or after completing a non-tagged
* command for which a second SCB has been queued. The sequencer will
* automatically consume the entries.
*/
@@ -1489,7 +1489,7 @@
* This is done to allow the host to send messages outside of an identify
* sequence while protecting the seqencer from testing the MK_MESSAGE bit
* on an SCB that might not be for the current nexus. (For example, a
- * BDR message in responce to a bad reselection would leave us pointed to
+ * BDR message in response to a bad reselection would leave us pointed to
* an SCB that doesn't have anything to do with the current target).
*
* Otherwise, treat MSG_OUT as a 1 byte message to send (abort, abort tag,
Property changes on: trunk/sys/dev/aic7xxx/aic7xxx.seq
___________________________________________________________________
Added: mnbsd:nokeywords
## -0,0 +1 ##
+MidnightBSD=%H
\ No newline at end of property
Modified: trunk/sys/dev/aic7xxx/aic7xxx_93cx6.c
===================================================================
--- trunk/sys/dev/aic7xxx/aic7xxx_93cx6.c 2018-05-28 00:25:20 UTC (rev 10127)
+++ trunk/sys/dev/aic7xxx/aic7xxx_93cx6.c 2018-05-28 00:27:43 UTC (rev 10128)
@@ -1,3 +1,4 @@
+/* $MidnightBSD$ */
/*-
* Interface for the 93C66/56/46/26/06 serial eeprom parts.
*
@@ -28,7 +29,7 @@
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*
- * $Id: aic7xxx_93cx6.c,v 1.1.1.3 2012-07-21 15:16:50 laffer1 Exp $
+ * $Id: //depot/aic7xxx/aic7xxx/aic7xxx_93cx6.c#19 $
*/
/*
@@ -70,7 +71,7 @@
#include "aic7xxx_93cx6.h"
#else
#include <sys/cdefs.h>
-__FBSDID("$FreeBSD$");
+__FBSDID("$FreeBSD: stable/10/sys/dev/aic7xxx/aic7xxx_93cx6.c 139757 2005-01-06 05:30:44Z scottl $");
#include <dev/aic7xxx/aic7xxx_osm.h>
#include <dev/aic7xxx/aic7xxx_inline.h>
#include <dev/aic7xxx/aic7xxx_93cx6.h>
Modified: trunk/sys/dev/aic7xxx/aic7xxx_93cx6.h
===================================================================
--- trunk/sys/dev/aic7xxx/aic7xxx_93cx6.h 2018-05-28 00:25:20 UTC (rev 10127)
+++ trunk/sys/dev/aic7xxx/aic7xxx_93cx6.h 2018-05-28 00:27:43 UTC (rev 10128)
@@ -1,3 +1,4 @@
+/* $MidnightBSD$ */
/*-
* Interface to the 93C46/56 serial EEPROM that is used to store BIOS
* settings for the aic7xxx based adaptec SCSI controllers. It can
@@ -38,9 +39,9 @@
* IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGES.
*
- * $Id: aic7xxx_93cx6.h,v 1.1.1.3 2012-07-21 15:16:50 laffer1 Exp $
+ * $Id: //depot/aic7xxx/aic7xxx/aic7xxx_93cx6.h#12 $
*
- * $FreeBSD$
+ * $FreeBSD: stable/10/sys/dev/aic7xxx/aic7xxx_93cx6.h 139749 2005-01-06 01:43:34Z imp $
*/
#ifndef _AIC7XXX_93CX6_H_
#define _AIC7XXX_93CX6_H_
Modified: trunk/sys/dev/aic7xxx/aic7xxx_inline.h
===================================================================
--- trunk/sys/dev/aic7xxx/aic7xxx_inline.h 2018-05-28 00:25:20 UTC (rev 10127)
+++ trunk/sys/dev/aic7xxx/aic7xxx_inline.h 2018-05-28 00:27:43 UTC (rev 10128)
@@ -1,3 +1,4 @@
+/* $MidnightBSD$ */
/*-
* Inline routines shareable across OS platforms.
*
@@ -37,9 +38,9 @@
* IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGES.
*
- * $Id: aic7xxx_inline.h,v 1.1.1.4 2012-07-21 15:16:50 laffer1 Exp $
+ * $Id: //depot/aic7xxx/aic7xxx/aic7xxx_inline.h#47 $
*
- * $FreeBSD$
+ * $FreeBSD: stable/10/sys/dev/aic7xxx/aic7xxx_inline.h 300060 2016-05-17 15:18:01Z pfg $
*/
#ifndef _AIC7XXX_INLINE_H_
@@ -229,7 +230,7 @@
return (ahc->name);
}
-/*********************** Miscelaneous Support Functions ***********************/
+/********************** Miscellaneous Support Functions ***********************/
static __inline void ahc_update_residual(struct ahc_softc *ahc,
struct scb *scb);
Modified: trunk/sys/dev/aic7xxx/aic7xxx_osm.c
===================================================================
--- trunk/sys/dev/aic7xxx/aic7xxx_osm.c 2018-05-28 00:25:20 UTC (rev 10127)
+++ trunk/sys/dev/aic7xxx/aic7xxx_osm.c 2018-05-28 00:27:43 UTC (rev 10128)
@@ -1,3 +1,4 @@
+/* $MidnightBSD$ */
/*-
* Bus independent FreeBSD shim for the aic7xxx based Adaptec SCSI controllers
*
@@ -28,11 +29,11 @@
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*
- * $Id: aic7xxx_osm.c,v 1.1.1.4 2012-07-21 15:16:50 laffer1 Exp $
+ * $Id: //depot/aic7xxx/freebsd/dev/aic7xxx/aic7xxx_osm.c#20 $
*/
#include <sys/cdefs.h>
-__FBSDID("$FreeBSD$");
+__FBSDID("$FreeBSD: stable/10/sys/dev/aic7xxx/aic7xxx_osm.c 315813 2017-03-23 06:41:13Z mav $");
#include <dev/aic7xxx/aic7xxx_osm.h>
#include <dev/aic7xxx/aic7xxx_inline.h>
@@ -130,7 +131,7 @@
return ENOMEM;
}
ahc->platform_data->regs_res_type = SYS_RES_IOPORT;
- ahc->platform_data->regs_res_id = rid,
+ ahc->platform_data->regs_res_id = rid;
ahc->platform_data->regs = regs;
ahc->tag = rman_get_bustag(regs);
ahc->bsh = rman_get_bushandle(regs);
@@ -797,9 +798,9 @@
}
cpi->bus_id = cam_sim_bus(sim);
cpi->base_transfer_speed = 3300;
- strncpy(cpi->sim_vid, "FreeBSD", SIM_IDLEN);
- strncpy(cpi->hba_vid, "Adaptec", HBA_IDLEN);
- strncpy(cpi->dev_name, cam_sim_name(sim), DEV_IDLEN);
+ strlcpy(cpi->sim_vid, "FreeBSD", SIM_IDLEN);
+ strlcpy(cpi->hba_vid, "Adaptec", HBA_IDLEN);
+ strlcpy(cpi->dev_name, cam_sim_name(sim), DEV_IDLEN);
cpi->unit_number = cam_sim_unit(sim);
cpi->protocol = PROTO_SCSI;
cpi->protocol_version = SCSI_REV_2;
@@ -1138,6 +1139,7 @@
{
struct hardware_scb *hscb;
struct ccb_hdr *ccb_h;
+ int error;
hscb = scb->hscb;
ccb_h = &csio->ccb_h;
@@ -1179,64 +1181,21 @@
}
}
- /* Only use S/G if there is a transfer */
- if ((ccb_h->flags & CAM_DIR_MASK) != CAM_DIR_NONE) {
- if ((ccb_h->flags & CAM_SCATTER_VALID) == 0) {
- /* We've been given a pointer to a single buffer */
- if ((ccb_h->flags & CAM_DATA_PHYS) == 0) {
- int s;
- int error;
-
- s = splsoftvm();
- error = bus_dmamap_load(ahc->buffer_dmat,
- scb->dmamap,
- csio->data_ptr,
- csio->dxfer_len,
- ahc_execute_scb,
- scb, /*flags*/0);
- if (error == EINPROGRESS) {
- /*
- * So as to maintain ordering,
- * freeze the controller queue
- * until our mapping is
- * returned.
- */
- xpt_freeze_simq(sim,
- /*count*/1);
- scb->io_ctx->ccb_h.status |=
- CAM_RELEASE_SIMQ;
- }
- splx(s);
- } else {
- struct bus_dma_segment seg;
-
- /* Pointer to physical buffer */
- if (csio->dxfer_len > AHC_MAXTRANSFER_SIZE)
- panic("ahc_setup_data - Transfer size "
- "larger than can device max");
-
- seg.ds_addr =
- (bus_addr_t)(vm_offset_t)csio->data_ptr;
- seg.ds_len = csio->dxfer_len;
- ahc_execute_scb(scb, &seg, 1, 0);
- }
- } else {
- struct bus_dma_segment *segs;
-
- if ((ccb_h->flags & CAM_DATA_PHYS) != 0)
- panic("ahc_setup_data - Physical segment "
- "pointers unsupported");
-
- if ((ccb_h->flags & CAM_SG_LIST_PHYS) == 0)
- panic("ahc_setup_data - Virtual segment "
- "addresses unsupported");
-
- /* Just use the segments provided */
- segs = (struct bus_dma_segment *)csio->data_ptr;
- ahc_execute_scb(scb, segs, csio->sglist_cnt, 0);
- }
- } else {
- ahc_execute_scb(scb, NULL, 0, 0);
+ error = bus_dmamap_load_ccb(ahc->buffer_dmat,
+ scb->dmamap,
+ (union ccb *)csio,
+ ahc_execute_scb,
+ scb,
+ 0);
+ if (error == EINPROGRESS) {
+ /*
+ * So as to maintain ordering,
+ * freeze the controller queue
+ * until our mapping is
+ * returned.
+ */
+ xpt_freeze_simq(sim, /*count*/1);
+ scb->io_ctx->ccb_h.status |= CAM_RELEASE_SIMQ;
}
}
Modified: trunk/sys/dev/aic7xxx/aic7xxx_osm.h
===================================================================
--- trunk/sys/dev/aic7xxx/aic7xxx_osm.h 2018-05-28 00:25:20 UTC (rev 10127)
+++ trunk/sys/dev/aic7xxx/aic7xxx_osm.h 2018-05-28 00:27:43 UTC (rev 10128)
@@ -1,3 +1,4 @@
+/* $MidnightBSD$ */
/*-
* FreeBSD platform specific driver option settings, data structures,
* function declarations and includes.
@@ -29,9 +30,9 @@
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*
- * $Id: aic7xxx_osm.h,v 1.5 2012-08-06 01:19:11 laffer1 Exp $
+ * $Id: //depot/aic7xxx/freebsd/dev/aic7xxx/aic7xxx_osm.h#18 $
*
- * $MidnightBSD: src/sys/dev/aic7xxx/aic7xxx_osm.h,v 1.4 2009/03/15 14:24:21 laffer1 Exp $
+ * $FreeBSD: stable/10/sys/dev/aic7xxx/aic7xxx_osm.h 218909 2011-02-21 09:01:34Z brucec $
*/
#ifndef _AIC7XXX_FREEBSD_H_
@@ -42,7 +43,9 @@
#include <sys/param.h>
#include <sys/systm.h>
#include <sys/bus.h> /* For device_t */
+#if __FreeBSD_version >= 500000
#include <sys/endian.h>
+#endif
#include <sys/eventhandler.h>
#include <sys/kernel.h>
#include <sys/malloc.h>
@@ -49,7 +52,11 @@
#include <sys/module.h>
#include <sys/queue.h>
+#if __FreeBSD_version < 500000
+#include <pci.h>
+#else
#define NPCI 1
+#endif
#if NPCI > 0
#define AIC_PCI_CONFIG 1
@@ -61,9 +68,14 @@
#include <sys/rman.h>
#if NPCI > 0
+#if __FreeBSD_version >= 500000
#include <dev/pci/pcireg.h>
#include <dev/pci/pcivar.h>
+#else
+#include <pci/pcireg.h>
+#include <pci/pcivar.h>
#endif
+#endif
#include <cam/cam.h>
#include <cam/cam_ccb.h>
Modified: trunk/sys/dev/aic7xxx/aic7xxx_pci.c
===================================================================
--- trunk/sys/dev/aic7xxx/aic7xxx_pci.c 2018-05-28 00:25:20 UTC (rev 10127)
+++ trunk/sys/dev/aic7xxx/aic7xxx_pci.c 2018-05-28 00:27:43 UTC (rev 10128)
@@ -1,3 +1,4 @@
+/* $MidnightBSD$ */
/*-
* Product specific probe and attach routines for:
* 3940, 2940, aic7895, aic7890, aic7880,
@@ -39,7 +40,7 @@
* IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGES.
*
- * $Id: aic7xxx_pci.c,v 1.1.1.4 2012-07-21 15:16:50 laffer1 Exp $
+ * $Id: //depot/aic7xxx/aic7xxx/aic7xxx_pci.c#78 $
*/
#ifdef __linux__
@@ -48,7 +49,7 @@
#include "aic7xxx_93cx6.h"
#else
#include <sys/cdefs.h>
-__FBSDID("$FreeBSD$");
+__FBSDID("$FreeBSD: stable/10/sys/dev/aic7xxx/aic7xxx_pci.c 300060 2016-05-17 15:18:01Z pfg $");
#include <dev/aic7xxx/aic7xxx_osm.h>
#include <dev/aic7xxx/aic7xxx_inline.h>
#include <dev/aic7xxx/aic7xxx_93cx6.h>
@@ -673,8 +674,8 @@
#define STA 0x08
#define DPR 0x01
-static int ahc_9005_subdevinfo_valid(uint16_t vendor, uint16_t device,
- uint16_t subvendor, uint16_t subdevice);
+static int ahc_9005_subdevinfo_valid(uint16_t device, uint16_t vendor,
+ uint16_t subdevice, uint16_t subvendor);
static int ahc_ext_scbram_present(struct ahc_softc *ahc);
static void ahc_scbram_config(struct ahc_softc *ahc, int enable,
int pcheck, int fast, int large);
@@ -766,7 +767,7 @@
* ID as valid.
*/
if (aic_get_pci_function(pci) > 0
- && ahc_9005_subdevinfo_valid(vendor, device, subvendor, subdevice)
+ && ahc_9005_subdevinfo_valid(device, vendor, subdevice, subvendor)
&& SUBID_9005_MFUNCENB(subdevice) == 0)
return (NULL);
@@ -865,7 +866,7 @@
ahc->bus_suspend = ahc_pci_suspend;
ahc->bus_resume = ahc_pci_resume;
- /* Remeber how the card was setup in case there is no SEEPROM */
+ /* Remember how the card was setup in case there is no SEEPROM */
if ((ahc_inb(ahc, HCNTRL) & POWRDN) == 0) {
ahc_pause(ahc);
if ((ahc->features & AHC_ULTRA2) != 0)
@@ -936,7 +937,7 @@
}
/*
- * We cannot perform ULTRA speeds without the presense
+ * We cannot perform ULTRA speeds without the presence
* of the external precision resistor.
*/
if ((ahc->features & AHC_ULTRA) != 0) {
@@ -1054,7 +1055,7 @@
}
/*
- * Test for the presense of external sram in an
+ * Test for the presence of external sram in an
* "unshared" configuration.
*/
static int
Modified: trunk/sys/dev/aic7xxx/aic7xxx_reg.h
===================================================================
--- trunk/sys/dev/aic7xxx/aic7xxx_reg.h 2018-05-28 00:25:20 UTC (rev 10127)
+++ trunk/sys/dev/aic7xxx/aic7xxx_reg.h 2018-05-28 00:27:43 UTC (rev 10128)
@@ -1,3 +1,4 @@
+/* $MidnightBSD$ */
/*
* DO NOT EDIT - This file is automatically generated
* from the following source files:
Added: trunk/sys/dev/aic7xxx/aic7xxx_reg_print.c
===================================================================
--- trunk/sys/dev/aic7xxx/aic7xxx_reg_print.c (rev 0)
+++ trunk/sys/dev/aic7xxx/aic7xxx_reg_print.c 2018-05-28 00:27:43 UTC (rev 10128)
@@ -0,0 +1,1685 @@
+/* $MidnightBSD$ */
+/*
+ * DO NOT EDIT - This file is automatically generated
+ * from the following source files:
+ *
+ * $Id: //depot/aic7xxx/aic7xxx/aic7xxx.seq#58 $
+ * $Id: //depot/aic7xxx/aic7xxx/aic7xxx.reg#40 $
+ */
+
+#include <sys/cdefs.h>
+__FBSDID("$FreeBSD: stable/10/sys/dev/aic7xxx/aic7xxx_reg_print.c 270284 2014-08-21 17:18:21Z ian $");
+#include <dev/aic7xxx/aic7xxx_osm.h>
+
+static ahc_reg_parse_entry_t SCSISEQ_parse_table[] = {
+ { "SCSIRSTO", 0x01, 0x01 },
+ { "ENAUTOATNP", 0x02, 0x02 },
+ { "ENAUTOATNI", 0x04, 0x04 },
+ { "ENAUTOATNO", 0x08, 0x08 },
+ { "ENRSELI", 0x10, 0x10 },
+ { "ENSELI", 0x20, 0x20 },
+ { "ENSELO", 0x40, 0x40 },
+ { "TEMODE", 0x80, 0x80 }
+};
+
+int
+ahc_scsiseq_print(u_int regvalue, u_int *cur_col, u_int wrap)
+{
+ return (ahc_print_register(SCSISEQ_parse_table, 8, "SCSISEQ",
+ 0x00, regvalue, cur_col, wrap));
+}
+
+static ahc_reg_parse_entry_t SXFRCTL0_parse_table[] = {
+ { "CLRCHN", 0x02, 0x02 },
+ { "SCAMEN", 0x04, 0x04 },
+ { "SPIOEN", 0x08, 0x08 },
+ { "CLRSTCNT", 0x10, 0x10 },
+ { "FAST20", 0x20, 0x20 },
+ { "DFPEXP", 0x40, 0x40 },
+ { "DFON", 0x80, 0x80 }
+};
+
+int
+ahc_sxfrctl0_print(u_int regvalue, u_int *cur_col, u_int wrap)
+{
+ return (ahc_print_register(SXFRCTL0_parse_table, 7, "SXFRCTL0",
+ 0x01, regvalue, cur_col, wrap));
+}
+
+static ahc_reg_parse_entry_t SXFRCTL1_parse_table[] = {
+ { "STPWEN", 0x01, 0x01 },
+ { "ACTNEGEN", 0x02, 0x02 },
+ { "ENSTIMER", 0x04, 0x04 },
+ { "ENSPCHK", 0x20, 0x20 },
+ { "SWRAPEN", 0x40, 0x40 },
+ { "BITBUCKET", 0x80, 0x80 },
+ { "STIMESEL", 0x18, 0x18 }
+};
+
+int
+ahc_sxfrctl1_print(u_int regvalue, u_int *cur_col, u_int wrap)
+{
+ return (ahc_print_register(SXFRCTL1_parse_table, 7, "SXFRCTL1",
+ 0x02, regvalue, cur_col, wrap));
+}
+
+static ahc_reg_parse_entry_t SCSISIGI_parse_table[] = {
+ { "ACKI", 0x01, 0x01 },
+ { "REQI", 0x02, 0x02 },
+ { "BSYI", 0x04, 0x04 },
+ { "SELI", 0x08, 0x08 },
+ { "ATNI", 0x10, 0x10 },
+ { "MSGI", 0x20, 0x20 },
+ { "IOI", 0x40, 0x40 },
+ { "CDI", 0x80, 0x80 },
+ { "P_DATAOUT", 0x00, 0x00 },
+ { "P_DATAOUT_DT", 0x20, 0x20 },
+ { "P_DATAIN", 0x40, 0x40 },
+ { "P_DATAIN_DT", 0x60, 0x60 },
+ { "P_COMMAND", 0x80, 0x80 },
+ { "P_MESGOUT", 0xa0, 0xa0 },
+ { "P_STATUS", 0xc0, 0xc0 },
+ { "PHASE_MASK", 0xe0, 0xe0 },
+ { "P_MESGIN", 0xe0, 0xe0 }
+};
+
+int
+ahc_scsisigi_print(u_int regvalue, u_int *cur_col, u_int wrap)
+{
+ return (ahc_print_register(SCSISIGI_parse_table, 17, "SCSISIGI",
+ 0x03, regvalue, cur_col, wrap));
+}
+
+static ahc_reg_parse_entry_t SCSISIGO_parse_table[] = {
+ { "ACKO", 0x01, 0x01 },
+ { "REQO", 0x02, 0x02 },
+ { "BSYO", 0x04, 0x04 },
+ { "SELO", 0x08, 0x08 },
+ { "ATNO", 0x10, 0x10 },
+ { "MSGO", 0x20, 0x20 },
+ { "IOO", 0x40, 0x40 },
+ { "CDO", 0x80, 0x80 },
+ { "P_DATAOUT", 0x00, 0x00 },
+ { "P_DATAIN", 0x40, 0x40 },
+ { "P_COMMAND", 0x80, 0x80 },
+ { "P_MESGOUT", 0xa0, 0xa0 },
+ { "P_STATUS", 0xc0, 0xc0 },
+ { "PHASE_MASK", 0xe0, 0xe0 },
+ { "P_MESGIN", 0xe0, 0xe0 }
+};
+
+int
+ahc_scsisigo_print(u_int regvalue, u_int *cur_col, u_int wrap)
+{
+ return (ahc_print_register(SCSISIGO_parse_table, 15, "SCSISIGO",
+ 0x03, regvalue, cur_col, wrap));
+}
+
+static ahc_reg_parse_entry_t SCSIRATE_parse_table[] = {
+ { "SINGLE_EDGE", 0x10, 0x10 },
+ { "ENABLE_CRC", 0x40, 0x40 },
+ { "WIDEXFER", 0x80, 0x80 },
+ { "SXFR_ULTRA2", 0x0f, 0x0f },
+ { "SOFS", 0x0f, 0x0f },
+ { "SXFR", 0x70, 0x70 }
+};
+
+int
+ahc_scsirate_print(u_int regvalue, u_int *cur_col, u_int wrap)
+{
+ return (ahc_print_register(SCSIRATE_parse_table, 6, "SCSIRATE",
+ 0x04, regvalue, cur_col, wrap));
+}
+
+static ahc_reg_parse_entry_t SCSIID_parse_table[] = {
+ { "TWIN_CHNLB", 0x80, 0x80 },
+ { "OID", 0x0f, 0x0f },
+ { "TWIN_TID", 0x70, 0x70 },
+ { "SOFS_ULTRA2", 0x7f, 0x7f },
+ { "TID", 0xf0, 0xf0 }
+};
+
+int
+ahc_scsiid_print(u_int regvalue, u_int *cur_col, u_int wrap)
+{
+ return (ahc_print_register(SCSIID_parse_table, 5, "SCSIID",
+ 0x05, regvalue, cur_col, wrap));
+}
+
+int
+ahc_scsidatl_print(u_int regvalue, u_int *cur_col, u_int wrap)
+{
+ return (ahc_print_register(NULL, 0, "SCSIDATL",
+ 0x06, regvalue, cur_col, wrap));
+}
+
+int
+ahc_scsidath_print(u_int regvalue, u_int *cur_col, u_int wrap)
+{
+ return (ahc_print_register(NULL, 0, "SCSIDATH",
+ 0x07, regvalue, cur_col, wrap));
+}
+
+static ahc_reg_parse_entry_t OPTIONMODE_parse_table[] = {
+ { "DIS_MSGIN_DUALEDGE", 0x01, 0x01 },
+ { "AUTO_MSGOUT_DE", 0x02, 0x02 },
+ { "SCSIDATL_IMGEN", 0x04, 0x04 },
+ { "EXPPHASEDIS", 0x08, 0x08 },
+ { "BUSFREEREV", 0x10, 0x10 },
+ { "ATNMGMNTEN", 0x20, 0x20 },
+ { "AUTOACKEN", 0x40, 0x40 },
+ { "AUTORATEEN", 0x80, 0x80 },
+ { "OPTIONMODE_DEFAULTS",0x03, 0x03 }
+};
+
+int
+ahc_optionmode_print(u_int regvalue, u_int *cur_col, u_int wrap)
+{
+ return (ahc_print_register(OPTIONMODE_parse_table, 9, "OPTIONMODE",
+ 0x08, regvalue, cur_col, wrap));
+}
+
+int
+ahc_stcnt_print(u_int regvalue, u_int *cur_col, u_int wrap)
+{
+ return (ahc_print_register(NULL, 0, "STCNT",
+ 0x08, regvalue, cur_col, wrap));
+}
+
+int
+ahc_targcrccnt_print(u_int regvalue, u_int *cur_col, u_int wrap)
+{
+ return (ahc_print_register(NULL, 0, "TARGCRCCNT",
+ 0x0a, regvalue, cur_col, wrap));
+}
+
+static ahc_reg_parse_entry_t CLRSINT0_parse_table[] = {
+ { "CLRSPIORDY", 0x02, 0x02 },
+ { "CLRSWRAP", 0x08, 0x08 },
+ { "CLRIOERR", 0x08, 0x08 },
+ { "CLRSELINGO", 0x10, 0x10 },
+ { "CLRSELDI", 0x20, 0x20 },
+ { "CLRSELDO", 0x40, 0x40 }
+};
+
+int
+ahc_clrsint0_print(u_int regvalue, u_int *cur_col, u_int wrap)
+{
+ return (ahc_print_register(CLRSINT0_parse_table, 6, "CLRSINT0",
+ 0x0b, regvalue, cur_col, wrap));
+}
+
+static ahc_reg_parse_entry_t SSTAT0_parse_table[] = {
+ { "DMADONE", 0x01, 0x01 },
+ { "SPIORDY", 0x02, 0x02 },
+ { "SDONE", 0x04, 0x04 },
+ { "SWRAP", 0x08, 0x08 },
+ { "IOERR", 0x08, 0x08 },
+ { "SELINGO", 0x10, 0x10 },
+ { "SELDI", 0x20, 0x20 },
+ { "SELDO", 0x40, 0x40 },
+ { "TARGET", 0x80, 0x80 }
+};
+
+int
+ahc_sstat0_print(u_int regvalue, u_int *cur_col, u_int wrap)
+{
+ return (ahc_print_register(SSTAT0_parse_table, 9, "SSTAT0",
+ 0x0b, regvalue, cur_col, wrap));
+}
+
+static ahc_reg_parse_entry_t CLRSINT1_parse_table[] = {
+ { "CLRREQINIT", 0x01, 0x01 },
+ { "CLRPHASECHG", 0x02, 0x02 },
+ { "CLRSCSIPERR", 0x04, 0x04 },
+ { "CLRBUSFREE", 0x08, 0x08 },
+ { "CLRSCSIRSTI", 0x20, 0x20 },
+ { "CLRATNO", 0x40, 0x40 },
+ { "CLRSELTIMEO", 0x80, 0x80 }
+};
+
+int
+ahc_clrsint1_print(u_int regvalue, u_int *cur_col, u_int wrap)
+{
+ return (ahc_print_register(CLRSINT1_parse_table, 7, "CLRSINT1",
+ 0x0c, regvalue, cur_col, wrap));
+}
+
+static ahc_reg_parse_entry_t SSTAT1_parse_table[] = {
+ { "REQINIT", 0x01, 0x01 },
+ { "PHASECHG", 0x02, 0x02 },
+ { "SCSIPERR", 0x04, 0x04 },
+ { "BUSFREE", 0x08, 0x08 },
+ { "PHASEMIS", 0x10, 0x10 },
+ { "SCSIRSTI", 0x20, 0x20 },
+ { "ATNTARG", 0x40, 0x40 },
+ { "SELTO", 0x80, 0x80 }
+};
+
+int
+ahc_sstat1_print(u_int regvalue, u_int *cur_col, u_int wrap)
+{
+ return (ahc_print_register(SSTAT1_parse_table, 8, "SSTAT1",
+ 0x0c, regvalue, cur_col, wrap));
+}
+
+static ahc_reg_parse_entry_t SSTAT2_parse_table[] = {
+ { "DUAL_EDGE_ERR", 0x01, 0x01 },
+ { "CRCREQERR", 0x02, 0x02 },
+ { "CRCENDERR", 0x04, 0x04 },
+ { "CRCVALERR", 0x08, 0x08 },
+ { "EXP_ACTIVE", 0x10, 0x10 },
+ { "SHVALID", 0x40, 0x40 },
+ { "OVERRUN", 0x80, 0x80 },
+ { "SFCNT", 0x1f, 0x1f }
+};
+
+int
+ahc_sstat2_print(u_int regvalue, u_int *cur_col, u_int wrap)
+{
+ return (ahc_print_register(SSTAT2_parse_table, 8, "SSTAT2",
+ 0x0d, regvalue, cur_col, wrap));
+}
+
+static ahc_reg_parse_entry_t SSTAT3_parse_table[] = {
+ { "OFFCNT", 0x0f, 0x0f },
+ { "U2OFFCNT", 0x7f, 0x7f },
+ { "SCSICNT", 0xf0, 0xf0 }
+};
+
+int
+ahc_sstat3_print(u_int regvalue, u_int *cur_col, u_int wrap)
+{
+ return (ahc_print_register(SSTAT3_parse_table, 3, "SSTAT3",
+ 0x0e, regvalue, cur_col, wrap));
+}
+
+static ahc_reg_parse_entry_t SCSIID_ULTRA2_parse_table[] = {
+ { "OID", 0x0f, 0x0f },
+ { "TID", 0xf0, 0xf0 }
+};
+
+int
+ahc_scsiid_ultra2_print(u_int regvalue, u_int *cur_col, u_int wrap)
+{
+ return (ahc_print_register(SCSIID_ULTRA2_parse_table, 2, "SCSIID_ULTRA2",
+ 0x0f, regvalue, cur_col, wrap));
+}
+
+static ahc_reg_parse_entry_t SIMODE0_parse_table[] = {
+ { "ENDMADONE", 0x01, 0x01 },
+ { "ENSPIORDY", 0x02, 0x02 },
+ { "ENSDONE", 0x04, 0x04 },
+ { "ENSWRAP", 0x08, 0x08 },
+ { "ENIOERR", 0x08, 0x08 },
+ { "ENSELINGO", 0x10, 0x10 },
+ { "ENSELDI", 0x20, 0x20 },
+ { "ENSELDO", 0x40, 0x40 }
+};
+
+int
+ahc_simode0_print(u_int regvalue, u_int *cur_col, u_int wrap)
+{
+ return (ahc_print_register(SIMODE0_parse_table, 8, "SIMODE0",
+ 0x10, regvalue, cur_col, wrap));
+}
+
+static ahc_reg_parse_entry_t SIMODE1_parse_table[] = {
+ { "ENREQINIT", 0x01, 0x01 },
+ { "ENPHASECHG", 0x02, 0x02 },
+ { "ENSCSIPERR", 0x04, 0x04 },
+ { "ENBUSFREE", 0x08, 0x08 },
+ { "ENPHASEMIS", 0x10, 0x10 },
+ { "ENSCSIRST", 0x20, 0x20 },
+ { "ENATNTARG", 0x40, 0x40 },
+ { "ENSELTIMO", 0x80, 0x80 }
+};
+
+int
+ahc_simode1_print(u_int regvalue, u_int *cur_col, u_int wrap)
+{
+ return (ahc_print_register(SIMODE1_parse_table, 8, "SIMODE1",
+ 0x11, regvalue, cur_col, wrap));
+}
+
+int
+ahc_scsibusl_print(u_int regvalue, u_int *cur_col, u_int wrap)
+{
+ return (ahc_print_register(NULL, 0, "SCSIBUSL",
+ 0x12, regvalue, cur_col, wrap));
+}
+
+static ahc_reg_parse_entry_t SXFRCTL2_parse_table[] = {
+ { "CMDDMAEN", 0x08, 0x08 },
+ { "AUTORSTDIS", 0x10, 0x10 },
+ { "ASYNC_SETUP", 0x07, 0x07 }
+};
+
+int
+ahc_sxfrctl2_print(u_int regvalue, u_int *cur_col, u_int wrap)
+{
+ return (ahc_print_register(SXFRCTL2_parse_table, 3, "SXFRCTL2",
+ 0x13, regvalue, cur_col, wrap));
+}
+
+int
+ahc_scsibush_print(u_int regvalue, u_int *cur_col, u_int wrap)
+{
+ return (ahc_print_register(NULL, 0, "SCSIBUSH",
+ 0x13, regvalue, cur_col, wrap));
+}
+
+int
+ahc_shaddr_print(u_int regvalue, u_int *cur_col, u_int wrap)
+{
+ return (ahc_print_register(NULL, 0, "SHADDR",
+ 0x14, regvalue, cur_col, wrap));
+}
+
+static ahc_reg_parse_entry_t SELTIMER_parse_table[] = {
+ { "STAGE1", 0x01, 0x01 },
+ { "STAGE2", 0x02, 0x02 },
+ { "STAGE3", 0x04, 0x04 },
+ { "STAGE4", 0x08, 0x08 },
+ { "STAGE5", 0x10, 0x10 },
+ { "STAGE6", 0x20, 0x20 }
+};
+
+int
+ahc_seltimer_print(u_int regvalue, u_int *cur_col, u_int wrap)
+{
+ return (ahc_print_register(SELTIMER_parse_table, 6, "SELTIMER",
+ 0x18, regvalue, cur_col, wrap));
+}
+
+static ahc_reg_parse_entry_t SELID_parse_table[] = {
+ { "ONEBIT", 0x08, 0x08 },
+ { "SELID_MASK", 0xf0, 0xf0 }
+};
+
+int
+ahc_selid_print(u_int regvalue, u_int *cur_col, u_int wrap)
+{
+ return (ahc_print_register(SELID_parse_table, 2, "SELID",
+ 0x19, regvalue, cur_col, wrap));
+}
+
+static ahc_reg_parse_entry_t SCAMCTL_parse_table[] = {
+ { "DFLTTID", 0x10, 0x10 },
+ { "ALTSTIM", 0x20, 0x20 },
+ { "CLRSCAMSELID", 0x40, 0x40 },
+ { "ENSCAMSELO", 0x80, 0x80 },
+ { "SCAMLVL", 0x03, 0x03 }
+};
+
+int
+ahc_scamctl_print(u_int regvalue, u_int *cur_col, u_int wrap)
+{
+ return (ahc_print_register(SCAMCTL_parse_table, 5, "SCAMCTL",
+ 0x1a, regvalue, cur_col, wrap));
+}
+
+int
+ahc_targid_print(u_int regvalue, u_int *cur_col, u_int wrap)
+{
+ return (ahc_print_register(NULL, 0, "TARGID",
+ 0x1b, regvalue, cur_col, wrap));
+}
+
+static ahc_reg_parse_entry_t SPIOCAP_parse_table[] = {
+ { "SSPIOCPS", 0x01, 0x01 },
+ { "ROM", 0x02, 0x02 },
+ { "EEPROM", 0x04, 0x04 },
+ { "SEEPROM", 0x08, 0x08 },
+ { "EXT_BRDCTL", 0x10, 0x10 },
+ { "SOFTCMDEN", 0x20, 0x20 },
+ { "SOFT0", 0x40, 0x40 },
+ { "SOFT1", 0x80, 0x80 }
+};
+
+int
+ahc_spiocap_print(u_int regvalue, u_int *cur_col, u_int wrap)
+{
+ return (ahc_print_register(SPIOCAP_parse_table, 8, "SPIOCAP",
+ 0x1b, regvalue, cur_col, wrap));
+}
+
+static ahc_reg_parse_entry_t BRDCTL_parse_table[] = {
+ { "BRDCTL0", 0x01, 0x01 },
+ { "BRDSTB_ULTRA2", 0x01, 0x01 },
+ { "BRDCTL1", 0x02, 0x02 },
+ { "BRDRW_ULTRA2", 0x02, 0x02 },
+ { "BRDRW", 0x04, 0x04 },
+ { "BRDDAT2", 0x04, 0x04 },
+ { "BRDCS", 0x08, 0x08 },
+ { "BRDDAT3", 0x08, 0x08 },
+ { "BRDSTB", 0x10, 0x10 },
+ { "BRDDAT4", 0x10, 0x10 },
+ { "BRDDAT5", 0x20, 0x20 },
+ { "BRDDAT6", 0x40, 0x40 },
+ { "BRDDAT7", 0x80, 0x80 }
+};
+
+int
+ahc_brdctl_print(u_int regvalue, u_int *cur_col, u_int wrap)
+{
+ return (ahc_print_register(BRDCTL_parse_table, 13, "BRDCTL",
+ 0x1d, regvalue, cur_col, wrap));
+}
+
+static ahc_reg_parse_entry_t SEECTL_parse_table[] = {
+ { "SEEDI", 0x01, 0x01 },
+ { "SEEDO", 0x02, 0x02 },
+ { "SEECK", 0x04, 0x04 },
+ { "SEECS", 0x08, 0x08 },
+ { "SEERDY", 0x10, 0x10 },
+ { "SEEMS", 0x20, 0x20 },
+ { "EXTARBREQ", 0x40, 0x40 },
+ { "EXTARBACK", 0x80, 0x80 }
+};
+
+int
+ahc_seectl_print(u_int regvalue, u_int *cur_col, u_int wrap)
+{
+ return (ahc_print_register(SEECTL_parse_table, 8, "SEECTL",
+ 0x1e, regvalue, cur_col, wrap));
+}
+
+static ahc_reg_parse_entry_t SBLKCTL_parse_table[] = {
+ { "XCVR", 0x01, 0x01 },
+ { "SELWIDE", 0x02, 0x02 },
+ { "ENAB20", 0x04, 0x04 },
+ { "SELBUSB", 0x08, 0x08 },
+ { "ENAB40", 0x08, 0x08 },
+ { "AUTOFLUSHDIS", 0x20, 0x20 },
+ { "DIAGLEDON", 0x40, 0x40 },
+ { "DIAGLEDEN", 0x80, 0x80 }
+};
+
+int
+ahc_sblkctl_print(u_int regvalue, u_int *cur_col, u_int wrap)
+{
+ return (ahc_print_register(SBLKCTL_parse_table, 8, "SBLKCTL",
+ 0x1f, regvalue, cur_col, wrap));
+}
+
+int
+ahc_busy_targets_print(u_int regvalue, u_int *cur_col, u_int wrap)
+{
+ return (ahc_print_register(NULL, 0, "BUSY_TARGETS",
+ 0x20, regvalue, cur_col, wrap));
+}
+
+int
+ahc_ultra_enb_print(u_int regvalue, u_int *cur_col, u_int wrap)
+{
+ return (ahc_print_register(NULL, 0, "ULTRA_ENB",
+ 0x30, regvalue, cur_col, wrap));
+}
+
+int
+ahc_disc_dsb_print(u_int regvalue, u_int *cur_col, u_int wrap)
+{
+ return (ahc_print_register(NULL, 0, "DISC_DSB",
+ 0x32, regvalue, cur_col, wrap));
+}
+
+int
+ahc_cmdsize_table_tail_print(u_int regvalue, u_int *cur_col, u_int wrap)
+{
+ return (ahc_print_register(NULL, 0, "CMDSIZE_TABLE_TAIL",
+ 0x34, regvalue, cur_col, wrap));
+}
+
+int
+ahc_mwi_residual_print(u_int regvalue, u_int *cur_col, u_int wrap)
+{
+ return (ahc_print_register(NULL, 0, "MWI_RESIDUAL",
+ 0x38, regvalue, cur_col, wrap));
+}
+
+int
+ahc_next_queued_scb_print(u_int regvalue, u_int *cur_col, u_int wrap)
+{
+ return (ahc_print_register(NULL, 0, "NEXT_QUEUED_SCB",
+ 0x39, regvalue, cur_col, wrap));
+}
+
+int
+ahc_msg_out_print(u_int regvalue, u_int *cur_col, u_int wrap)
+{
+ return (ahc_print_register(NULL, 0, "MSG_OUT",
+ 0x3a, regvalue, cur_col, wrap));
+}
+
+static ahc_reg_parse_entry_t DMAPARAMS_parse_table[] = {
+ { "FIFORESET", 0x01, 0x01 },
+ { "FIFOFLUSH", 0x02, 0x02 },
+ { "DIRECTION", 0x04, 0x04 },
+ { "HDMAEN", 0x08, 0x08 },
+ { "HDMAENACK", 0x08, 0x08 },
+ { "SDMAEN", 0x10, 0x10 },
+ { "SDMAENACK", 0x10, 0x10 },
+ { "SCSIEN", 0x20, 0x20 },
+ { "WIDEODD", 0x40, 0x40 },
+ { "PRELOADEN", 0x80, 0x80 }
+};
+
+int
+ahc_dmaparams_print(u_int regvalue, u_int *cur_col, u_int wrap)
+{
+ return (ahc_print_register(DMAPARAMS_parse_table, 10, "DMAPARAMS",
+ 0x3b, regvalue, cur_col, wrap));
+}
+
+static ahc_reg_parse_entry_t SEQ_FLAGS_parse_table[] = {
+ { "NO_DISCONNECT", 0x01, 0x01 },
+ { "SPHASE_PENDING", 0x02, 0x02 },
+ { "DPHASE_PENDING", 0x04, 0x04 },
+ { "CMDPHASE_PENDING", 0x08, 0x08 },
+ { "TARG_CMD_PENDING", 0x10, 0x10 },
+ { "DPHASE", 0x20, 0x20 },
+ { "NO_CDB_SENT", 0x40, 0x40 },
+ { "TARGET_CMD_IS_TAGGED",0x40, 0x40 },
+ { "NOT_IDENTIFIED", 0x80, 0x80 }
+};
+
+int
+ahc_seq_flags_print(u_int regvalue, u_int *cur_col, u_int wrap)
+{
+ return (ahc_print_register(SEQ_FLAGS_parse_table, 9, "SEQ_FLAGS",
+ 0x3c, regvalue, cur_col, wrap));
+}
+
+int
+ahc_saved_scsiid_print(u_int regvalue, u_int *cur_col, u_int wrap)
+{
+ return (ahc_print_register(NULL, 0, "SAVED_SCSIID",
+ 0x3d, regvalue, cur_col, wrap));
+}
+
+int
+ahc_saved_lun_print(u_int regvalue, u_int *cur_col, u_int wrap)
+{
+ return (ahc_print_register(NULL, 0, "SAVED_LUN",
+ 0x3e, regvalue, cur_col, wrap));
+}
+
+static ahc_reg_parse_entry_t LASTPHASE_parse_table[] = {
+ { "MSGI", 0x20, 0x20 },
+ { "IOI", 0x40, 0x40 },
+ { "CDI", 0x80, 0x80 },
+ { "P_DATAOUT", 0x00, 0x00 },
+ { "P_BUSFREE", 0x01, 0x01 },
+ { "P_DATAIN", 0x40, 0x40 },
+ { "P_COMMAND", 0x80, 0x80 },
+ { "P_MESGOUT", 0xa0, 0xa0 },
+ { "P_STATUS", 0xc0, 0xc0 },
+ { "PHASE_MASK", 0xe0, 0xe0 },
+ { "P_MESGIN", 0xe0, 0xe0 }
+};
+
+int
+ahc_lastphase_print(u_int regvalue, u_int *cur_col, u_int wrap)
+{
+ return (ahc_print_register(LASTPHASE_parse_table, 11, "LASTPHASE",
+ 0x3f, regvalue, cur_col, wrap));
+}
+
+int
+ahc_waiting_scbh_print(u_int regvalue, u_int *cur_col, u_int wrap)
+{
+ return (ahc_print_register(NULL, 0, "WAITING_SCBH",
+ 0x40, regvalue, cur_col, wrap));
+}
+
+int
+ahc_disconnected_scbh_print(u_int regvalue, u_int *cur_col, u_int wrap)
+{
+ return (ahc_print_register(NULL, 0, "DISCONNECTED_SCBH",
+ 0x41, regvalue, cur_col, wrap));
+}
+
+int
+ahc_free_scbh_print(u_int regvalue, u_int *cur_col, u_int wrap)
+{
+ return (ahc_print_register(NULL, 0, "FREE_SCBH",
+ 0x42, regvalue, cur_col, wrap));
+}
+
+int
+ahc_complete_scbh_print(u_int regvalue, u_int *cur_col, u_int wrap)
+{
+ return (ahc_print_register(NULL, 0, "COMPLETE_SCBH",
+ 0x43, regvalue, cur_col, wrap));
+}
+
+int
+ahc_hscb_addr_print(u_int regvalue, u_int *cur_col, u_int wrap)
+{
+ return (ahc_print_register(NULL, 0, "HSCB_ADDR",
+ 0x44, regvalue, cur_col, wrap));
+}
+
+int
+ahc_shared_data_addr_print(u_int regvalue, u_int *cur_col, u_int wrap)
+{
+ return (ahc_print_register(NULL, 0, "SHARED_DATA_ADDR",
+ 0x48, regvalue, cur_col, wrap));
+}
+
+int
+ahc_kernel_qinpos_print(u_int regvalue, u_int *cur_col, u_int wrap)
+{
+ return (ahc_print_register(NULL, 0, "KERNEL_QINPOS",
+ 0x4c, regvalue, cur_col, wrap));
+}
+
+int
+ahc_qinpos_print(u_int regvalue, u_int *cur_col, u_int wrap)
+{
+ return (ahc_print_register(NULL, 0, "QINPOS",
+ 0x4d, regvalue, cur_col, wrap));
+}
+
+int
+ahc_qoutpos_print(u_int regvalue, u_int *cur_col, u_int wrap)
+{
+ return (ahc_print_register(NULL, 0, "QOUTPOS",
+ 0x4e, regvalue, cur_col, wrap));
+}
+
+int
+ahc_kernel_tqinpos_print(u_int regvalue, u_int *cur_col, u_int wrap)
+{
+ return (ahc_print_register(NULL, 0, "KERNEL_TQINPOS",
+ 0x4f, regvalue, cur_col, wrap));
+}
+
+int
+ahc_tqinpos_print(u_int regvalue, u_int *cur_col, u_int wrap)
+{
+ return (ahc_print_register(NULL, 0, "TQINPOS",
+ 0x50, regvalue, cur_col, wrap));
+}
+
+static ahc_reg_parse_entry_t ARG_1_parse_table[] = {
+ { "SPARE", 0x01, 0x01 },
+ { "CONT_TARG_SESSION", 0x02, 0x02 },
+ { "CONT_MSG_LOOP", 0x04, 0x04 },
+ { "EXIT_MSG_LOOP", 0x08, 0x08 },
+ { "MSGOUT_PHASEMIS", 0x10, 0x10 },
+ { "SEND_REJ", 0x20, 0x20 },
+ { "SEND_SENSE", 0x40, 0x40 },
+ { "SEND_MSG", 0x80, 0x80 }
+};
+
+int
+ahc_arg_1_print(u_int regvalue, u_int *cur_col, u_int wrap)
+{
+ return (ahc_print_register(ARG_1_parse_table, 8, "ARG_1",
+ 0x51, regvalue, cur_col, wrap));
+}
+
+int
+ahc_arg_2_print(u_int regvalue, u_int *cur_col, u_int wrap)
+{
+ return (ahc_print_register(NULL, 0, "ARG_2",
+ 0x52, regvalue, cur_col, wrap));
+}
+
+int
+ahc_last_msg_print(u_int regvalue, u_int *cur_col, u_int wrap)
+{
+ return (ahc_print_register(NULL, 0, "LAST_MSG",
+ 0x53, regvalue, cur_col, wrap));
+}
+
+static ahc_reg_parse_entry_t SCSISEQ_TEMPLATE_parse_table[] = {
+ { "ENAUTOATNP", 0x02, 0x02 },
+ { "ENAUTOATNI", 0x04, 0x04 },
+ { "ENAUTOATNO", 0x08, 0x08 },
+ { "ENRSELI", 0x10, 0x10 },
+ { "ENSELI", 0x20, 0x20 },
+ { "ENSELO", 0x40, 0x40 }
+};
+
+int
+ahc_scsiseq_template_print(u_int regvalue, u_int *cur_col, u_int wrap)
+{
+ return (ahc_print_register(SCSISEQ_TEMPLATE_parse_table, 6, "SCSISEQ_TEMPLATE",
+ 0x54, regvalue, cur_col, wrap));
+}
+
+static ahc_reg_parse_entry_t HA_274_BIOSGLOBAL_parse_table[] = {
+ { "HA_274_EXTENDED_TRANS",0x01, 0x01 }
+};
+
+int
+ahc_ha_274_biosglobal_print(u_int regvalue, u_int *cur_col, u_int wrap)
+{
+ return (ahc_print_register(HA_274_BIOSGLOBAL_parse_table, 1, "HA_274_BIOSGLOBAL",
+ 0x56, regvalue, cur_col, wrap));
+}
+
+static ahc_reg_parse_entry_t SEQ_FLAGS2_parse_table[] = {
+ { "SCB_DMA", 0x01, 0x01 },
+ { "TARGET_MSG_PENDING", 0x02, 0x02 }
+};
+
+int
+ahc_seq_flags2_print(u_int regvalue, u_int *cur_col, u_int wrap)
+{
+ return (ahc_print_register(SEQ_FLAGS2_parse_table, 2, "SEQ_FLAGS2",
+ 0x57, regvalue, cur_col, wrap));
+}
+
+static ahc_reg_parse_entry_t SCSICONF_parse_table[] = {
+ { "ENSPCHK", 0x20, 0x20 },
+ { "RESET_SCSI", 0x40, 0x40 },
+ { "TERM_ENB", 0x80, 0x80 },
+ { "HSCSIID", 0x07, 0x07 },
+ { "HWSCSIID", 0x0f, 0x0f }
+};
+
+int
+ahc_scsiconf_print(u_int regvalue, u_int *cur_col, u_int wrap)
+{
+ return (ahc_print_register(SCSICONF_parse_table, 5, "SCSICONF",
+ 0x5a, regvalue, cur_col, wrap));
+}
+
+static ahc_reg_parse_entry_t INTDEF_parse_table[] = {
+ { "EDGE_TRIG", 0x80, 0x80 },
+ { "VECTOR", 0x0f, 0x0f }
+};
+
+int
+ahc_intdef_print(u_int regvalue, u_int *cur_col, u_int wrap)
+{
+ return (ahc_print_register(INTDEF_parse_table, 2, "INTDEF",
+ 0x5c, regvalue, cur_col, wrap));
+}
+
+int
+ahc_hostconf_print(u_int regvalue, u_int *cur_col, u_int wrap)
+{
+ return (ahc_print_register(NULL, 0, "HOSTCONF",
+ 0x5d, regvalue, cur_col, wrap));
+}
+
+static ahc_reg_parse_entry_t HA_274_BIOSCTRL_parse_table[] = {
+ { "CHANNEL_B_PRIMARY", 0x08, 0x08 },
+ { "BIOSMODE", 0x30, 0x30 },
+ { "BIOSDISABLED", 0x30, 0x30 }
+};
+
+int
+ahc_ha_274_biosctrl_print(u_int regvalue, u_int *cur_col, u_int wrap)
+{
+ return (ahc_print_register(HA_274_BIOSCTRL_parse_table, 3, "HA_274_BIOSCTRL",
+ 0x5f, regvalue, cur_col, wrap));
+}
+
+static ahc_reg_parse_entry_t SEQCTL_parse_table[] = {
+ { "LOADRAM", 0x01, 0x01 },
+ { "SEQRESET", 0x02, 0x02 },
+ { "STEP", 0x04, 0x04 },
+ { "BRKADRINTEN", 0x08, 0x08 },
+ { "FASTMODE", 0x10, 0x10 },
+ { "FAILDIS", 0x20, 0x20 },
+ { "PAUSEDIS", 0x40, 0x40 },
+ { "PERRORDIS", 0x80, 0x80 }
+};
+
+int
+ahc_seqctl_print(u_int regvalue, u_int *cur_col, u_int wrap)
+{
+ return (ahc_print_register(SEQCTL_parse_table, 8, "SEQCTL",
+ 0x60, regvalue, cur_col, wrap));
+}
+
+int
+ahc_seqram_print(u_int regvalue, u_int *cur_col, u_int wrap)
+{
+ return (ahc_print_register(NULL, 0, "SEQRAM",
+ 0x61, regvalue, cur_col, wrap));
+}
+
+int
+ahc_seqaddr0_print(u_int regvalue, u_int *cur_col, u_int wrap)
+{
+ return (ahc_print_register(NULL, 0, "SEQADDR0",
+ 0x62, regvalue, cur_col, wrap));
+}
+
+static ahc_reg_parse_entry_t SEQADDR1_parse_table[] = {
+ { "SEQADDR1_MASK", 0x01, 0x01 }
+};
+
+int
+ahc_seqaddr1_print(u_int regvalue, u_int *cur_col, u_int wrap)
+{
+ return (ahc_print_register(SEQADDR1_parse_table, 1, "SEQADDR1",
+ 0x63, regvalue, cur_col, wrap));
+}
+
+int
+ahc_accum_print(u_int regvalue, u_int *cur_col, u_int wrap)
+{
+ return (ahc_print_register(NULL, 0, "ACCUM",
+ 0x64, regvalue, cur_col, wrap));
+}
+
+int
+ahc_sindex_print(u_int regvalue, u_int *cur_col, u_int wrap)
+{
+ return (ahc_print_register(NULL, 0, "SINDEX",
+ 0x65, regvalue, cur_col, wrap));
+}
+
+int
+ahc_dindex_print(u_int regvalue, u_int *cur_col, u_int wrap)
+{
+ return (ahc_print_register(NULL, 0, "DINDEX",
+ 0x66, regvalue, cur_col, wrap));
+}
+
+int
+ahc_allones_print(u_int regvalue, u_int *cur_col, u_int wrap)
+{
+ return (ahc_print_register(NULL, 0, "ALLONES",
+ 0x69, regvalue, cur_col, wrap));
+}
+
+int
+ahc_none_print(u_int regvalue, u_int *cur_col, u_int wrap)
+{
+ return (ahc_print_register(NULL, 0, "NONE",
+ 0x6a, regvalue, cur_col, wrap));
+}
+
+int
+ahc_allzeros_print(u_int regvalue, u_int *cur_col, u_int wrap)
+{
+ return (ahc_print_register(NULL, 0, "ALLZEROS",
+ 0x6a, regvalue, cur_col, wrap));
+}
+
+static ahc_reg_parse_entry_t FLAGS_parse_table[] = {
+ { "CARRY", 0x01, 0x01 },
+ { "ZERO", 0x02, 0x02 }
+};
+
+int
+ahc_flags_print(u_int regvalue, u_int *cur_col, u_int wrap)
+{
+ return (ahc_print_register(FLAGS_parse_table, 2, "FLAGS",
+ 0x6b, regvalue, cur_col, wrap));
+}
+
+int
+ahc_sindir_print(u_int regvalue, u_int *cur_col, u_int wrap)
+{
+ return (ahc_print_register(NULL, 0, "SINDIR",
+ 0x6c, regvalue, cur_col, wrap));
+}
+
+int
+ahc_dindir_print(u_int regvalue, u_int *cur_col, u_int wrap)
+{
+ return (ahc_print_register(NULL, 0, "DINDIR",
+ 0x6d, regvalue, cur_col, wrap));
+}
+
+int
+ahc_function1_print(u_int regvalue, u_int *cur_col, u_int wrap)
+{
+ return (ahc_print_register(NULL, 0, "FUNCTION1",
+ 0x6e, regvalue, cur_col, wrap));
+}
+
+int
+ahc_stack_print(u_int regvalue, u_int *cur_col, u_int wrap)
+{
+ return (ahc_print_register(NULL, 0, "STACK",
+ 0x6f, regvalue, cur_col, wrap));
+}
+
+int
+ahc_targ_offset_print(u_int regvalue, u_int *cur_col, u_int wrap)
+{
+ return (ahc_print_register(NULL, 0, "TARG_OFFSET",
+ 0x70, regvalue, cur_col, wrap));
+}
+
+int
+ahc_sram_base_print(u_int regvalue, u_int *cur_col, u_int wrap)
+{
+ return (ahc_print_register(NULL, 0, "SRAM_BASE",
+ 0x70, regvalue, cur_col, wrap));
+}
+
+static ahc_reg_parse_entry_t DSCOMMAND0_parse_table[] = {
+ { "CIOPARCKEN", 0x01, 0x01 },
+ { "USCBSIZE32", 0x02, 0x02 },
+ { "RAMPS", 0x04, 0x04 },
+ { "INTSCBRAMSEL", 0x08, 0x08 },
+ { "EXTREQLCK", 0x10, 0x10 },
+ { "MPARCKEN", 0x20, 0x20 },
+ { "DPARCKEN", 0x40, 0x40 },
+ { "CACHETHEN", 0x80, 0x80 }
+};
+
+int
+ahc_dscommand0_print(u_int regvalue, u_int *cur_col, u_int wrap)
+{
+ return (ahc_print_register(DSCOMMAND0_parse_table, 8, "DSCOMMAND0",
+ 0x84, regvalue, cur_col, wrap));
+}
+
+static ahc_reg_parse_entry_t BCTL_parse_table[] = {
+ { "ENABLE", 0x01, 0x01 },
+ { "ACE", 0x08, 0x08 }
+};
+
+int
+ahc_bctl_print(u_int regvalue, u_int *cur_col, u_int wrap)
+{
+ return (ahc_print_register(BCTL_parse_table, 2, "BCTL",
+ 0x84, regvalue, cur_col, wrap));
+}
+
+static ahc_reg_parse_entry_t BUSTIME_parse_table[] = {
+ { "BON", 0x0f, 0x0f },
+ { "BOFF", 0xf0, 0xf0 }
+};
+
+int
+ahc_bustime_print(u_int regvalue, u_int *cur_col, u_int wrap)
+{
+ return (ahc_print_register(BUSTIME_parse_table, 2, "BUSTIME",
+ 0x85, regvalue, cur_col, wrap));
+}
+
+static ahc_reg_parse_entry_t DSCOMMAND1_parse_table[] = {
+ { "HADDLDSEL0", 0x01, 0x01 },
+ { "HADDLDSEL1", 0x02, 0x02 },
+ { "DSLATT", 0xfc, 0xfc }
+};
+
+int
+ahc_dscommand1_print(u_int regvalue, u_int *cur_col, u_int wrap)
+{
+ return (ahc_print_register(DSCOMMAND1_parse_table, 3, "DSCOMMAND1",
+ 0x85, regvalue, cur_col, wrap));
+}
+
+static ahc_reg_parse_entry_t BUSSPD_parse_table[] = {
+ { "STBON", 0x07, 0x07 },
+ { "STBOFF", 0x38, 0x38 },
+ { "DFTHRSH_75", 0x80, 0x80 },
+ { "DFTHRSH", 0xc0, 0xc0 },
+ { "DFTHRSH_100", 0xc0, 0xc0 }
+};
+
+int
+ahc_busspd_print(u_int regvalue, u_int *cur_col, u_int wrap)
+{
+ return (ahc_print_register(BUSSPD_parse_table, 5, "BUSSPD",
+ 0x86, regvalue, cur_col, wrap));
+}
+
+static ahc_reg_parse_entry_t HS_MAILBOX_parse_table[] = {
+ { "SEQ_MAILBOX", 0x0f, 0x0f },
+ { "HOST_TQINPOS", 0x80, 0x80 },
+ { "HOST_MAILBOX", 0xf0, 0xf0 }
+};
+
+int
+ahc_hs_mailbox_print(u_int regvalue, u_int *cur_col, u_int wrap)
+{
+ return (ahc_print_register(HS_MAILBOX_parse_table, 3, "HS_MAILBOX",
+ 0x86, regvalue, cur_col, wrap));
+}
+
+static ahc_reg_parse_entry_t DSPCISTATUS_parse_table[] = {
+ { "DFTHRSH_100", 0xc0, 0xc0 }
+};
+
+int
+ahc_dspcistatus_print(u_int regvalue, u_int *cur_col, u_int wrap)
+{
+ return (ahc_print_register(DSPCISTATUS_parse_table, 1, "DSPCISTATUS",
+ 0x86, regvalue, cur_col, wrap));
+}
+
+static ahc_reg_parse_entry_t HCNTRL_parse_table[] = {
+ { "CHIPRST", 0x01, 0x01 },
+ { "CHIPRSTACK", 0x01, 0x01 },
+ { "INTEN", 0x02, 0x02 },
+ { "PAUSE", 0x04, 0x04 },
+ { "IRQMS", 0x08, 0x08 },
+ { "SWINT", 0x10, 0x10 },
+ { "POWRDN", 0x40, 0x40 }
+};
+
+int
+ahc_hcntrl_print(u_int regvalue, u_int *cur_col, u_int wrap)
+{
+ return (ahc_print_register(HCNTRL_parse_table, 7, "HCNTRL",
+ 0x87, regvalue, cur_col, wrap));
+}
+
+int
+ahc_haddr_print(u_int regvalue, u_int *cur_col, u_int wrap)
+{
+ return (ahc_print_register(NULL, 0, "HADDR",
+ 0x88, regvalue, cur_col, wrap));
+}
+
+int
+ahc_hcnt_print(u_int regvalue, u_int *cur_col, u_int wrap)
+{
+ return (ahc_print_register(NULL, 0, "HCNT",
+ 0x8c, regvalue, cur_col, wrap));
+}
+
+int
+ahc_scbptr_print(u_int regvalue, u_int *cur_col, u_int wrap)
+{
+ return (ahc_print_register(NULL, 0, "SCBPTR",
+ 0x90, regvalue, cur_col, wrap));
+}
+
+static ahc_reg_parse_entry_t INTSTAT_parse_table[] = {
+ { "SEQINT", 0x01, 0x01 },
+ { "CMDCMPLT", 0x02, 0x02 },
+ { "SCSIINT", 0x04, 0x04 },
+ { "BRKADRINT", 0x08, 0x08 },
+ { "BAD_PHASE", 0x01, 0x01 },
+ { "INT_PEND", 0x0f, 0x0f },
+ { "SEND_REJECT", 0x11, 0x11 },
+ { "PROTO_VIOLATION", 0x21, 0x21 },
+ { "NO_MATCH", 0x31, 0x31 },
+ { "IGN_WIDE_RES", 0x41, 0x41 },
+ { "PDATA_REINIT", 0x51, 0x51 },
+ { "HOST_MSG_LOOP", 0x61, 0x61 },
+ { "BAD_STATUS", 0x71, 0x71 },
+ { "PERR_DETECTED", 0x81, 0x81 },
+ { "DATA_OVERRUN", 0x91, 0x91 },
+ { "MKMSG_FAILED", 0xa1, 0xa1 },
+ { "MISSED_BUSFREE", 0xb1, 0xb1 },
+ { "SCB_MISMATCH", 0xc1, 0xc1 },
+ { "NO_FREE_SCB", 0xd1, 0xd1 },
+ { "OUT_OF_RANGE", 0xe1, 0xe1 },
+ { "SEQINT_MASK", 0xf1, 0xf1 }
+};
+
+int
+ahc_intstat_print(u_int regvalue, u_int *cur_col, u_int wrap)
+{
+ return (ahc_print_register(INTSTAT_parse_table, 21, "INTSTAT",
+ 0x91, regvalue, cur_col, wrap));
+}
+
+static ahc_reg_parse_entry_t ERROR_parse_table[] = {
+ { "ILLHADDR", 0x01, 0x01 },
+ { "ILLSADDR", 0x02, 0x02 },
+ { "ILLOPCODE", 0x04, 0x04 },
+ { "SQPARERR", 0x08, 0x08 },
+ { "DPARERR", 0x10, 0x10 },
+ { "MPARERR", 0x20, 0x20 },
+ { "PCIERRSTAT", 0x40, 0x40 },
+ { "CIOPARERR", 0x80, 0x80 }
+};
+
+int
+ahc_error_print(u_int regvalue, u_int *cur_col, u_int wrap)
+{
+ return (ahc_print_register(ERROR_parse_table, 8, "ERROR",
+ 0x92, regvalue, cur_col, wrap));
+}
+
+static ahc_reg_parse_entry_t CLRINT_parse_table[] = {
+ { "CLRSEQINT", 0x01, 0x01 },
+ { "CLRCMDINT", 0x02, 0x02 },
+ { "CLRSCSIINT", 0x04, 0x04 },
+ { "CLRBRKADRINT", 0x08, 0x08 },
+ { "CLRPARERR", 0x10, 0x10 }
+};
+
+int
+ahc_clrint_print(u_int regvalue, u_int *cur_col, u_int wrap)
+{
+ return (ahc_print_register(CLRINT_parse_table, 5, "CLRINT",
+ 0x92, regvalue, cur_col, wrap));
+}
+
+static ahc_reg_parse_entry_t DFCNTRL_parse_table[] = {
+ { "FIFORESET", 0x01, 0x01 },
+ { "FIFOFLUSH", 0x02, 0x02 },
+ { "DIRECTION", 0x04, 0x04 },
+ { "HDMAEN", 0x08, 0x08 },
+ { "HDMAENACK", 0x08, 0x08 },
+ { "SDMAEN", 0x10, 0x10 },
+ { "SDMAENACK", 0x10, 0x10 },
+ { "SCSIEN", 0x20, 0x20 },
+ { "WIDEODD", 0x40, 0x40 },
+ { "PRELOADEN", 0x80, 0x80 }
+};
+
+int
+ahc_dfcntrl_print(u_int regvalue, u_int *cur_col, u_int wrap)
+{
+ return (ahc_print_register(DFCNTRL_parse_table, 10, "DFCNTRL",
+ 0x93, regvalue, cur_col, wrap));
+}
+
+static ahc_reg_parse_entry_t DFSTATUS_parse_table[] = {
+ { "FIFOEMP", 0x01, 0x01 },
+ { "FIFOFULL", 0x02, 0x02 },
+ { "DFTHRESH", 0x04, 0x04 },
+ { "HDONE", 0x08, 0x08 },
+ { "MREQPEND", 0x10, 0x10 },
+ { "FIFOQWDEMP", 0x20, 0x20 },
+ { "DFCACHETH", 0x40, 0x40 },
+ { "PRELOAD_AVAIL", 0x80, 0x80 }
+};
+
+int
+ahc_dfstatus_print(u_int regvalue, u_int *cur_col, u_int wrap)
+{
+ return (ahc_print_register(DFSTATUS_parse_table, 8, "DFSTATUS",
+ 0x94, regvalue, cur_col, wrap));
+}
+
+int
+ahc_dfwaddr_print(u_int regvalue, u_int *cur_col, u_int wrap)
+{
+ return (ahc_print_register(NULL, 0, "DFWADDR",
+ 0x95, regvalue, cur_col, wrap));
+}
+
+int
+ahc_dfraddr_print(u_int regvalue, u_int *cur_col, u_int wrap)
+{
+ return (ahc_print_register(NULL, 0, "DFRADDR",
+ 0x97, regvalue, cur_col, wrap));
+}
+
+int
+ahc_dfdat_print(u_int regvalue, u_int *cur_col, u_int wrap)
+{
+ return (ahc_print_register(NULL, 0, "DFDAT",
+ 0x99, regvalue, cur_col, wrap));
+}
+
+static ahc_reg_parse_entry_t SCBCNT_parse_table[] = {
+ { "SCBAUTO", 0x80, 0x80 },
+ { "SCBCNT_MASK", 0x1f, 0x1f }
+};
+
+int
+ahc_scbcnt_print(u_int regvalue, u_int *cur_col, u_int wrap)
+{
+ return (ahc_print_register(SCBCNT_parse_table, 2, "SCBCNT",
+ 0x9a, regvalue, cur_col, wrap));
+}
+
+int
+ahc_qinfifo_print(u_int regvalue, u_int *cur_col, u_int wrap)
+{
+ return (ahc_print_register(NULL, 0, "QINFIFO",
+ 0x9b, regvalue, cur_col, wrap));
+}
+
+int
+ahc_qincnt_print(u_int regvalue, u_int *cur_col, u_int wrap)
+{
+ return (ahc_print_register(NULL, 0, "QINCNT",
+ 0x9c, regvalue, cur_col, wrap));
+}
+
+static ahc_reg_parse_entry_t CRCCONTROL1_parse_table[] = {
+ { "TARGCRCCNTEN", 0x04, 0x04 },
+ { "TARGCRCENDEN", 0x08, 0x08 },
+ { "CRCREQCHKEN", 0x10, 0x10 },
+ { "CRCENDCHKEN", 0x20, 0x20 },
+ { "CRCVALCHKEN", 0x40, 0x40 },
+ { "CRCONSEEN", 0x80, 0x80 }
+};
+
+int
+ahc_crccontrol1_print(u_int regvalue, u_int *cur_col, u_int wrap)
+{
+ return (ahc_print_register(CRCCONTROL1_parse_table, 6, "CRCCONTROL1",
+ 0x9d, regvalue, cur_col, wrap));
+}
+
+int
+ahc_qoutfifo_print(u_int regvalue, u_int *cur_col, u_int wrap)
+{
+ return (ahc_print_register(NULL, 0, "QOUTFIFO",
+ 0x9d, regvalue, cur_col, wrap));
+}
+
+int
+ahc_qoutcnt_print(u_int regvalue, u_int *cur_col, u_int wrap)
+{
+ return (ahc_print_register(NULL, 0, "QOUTCNT",
+ 0x9e, regvalue, cur_col, wrap));
+}
+
+static ahc_reg_parse_entry_t SCSIPHASE_parse_table[] = {
+ { "DATA_OUT_PHASE", 0x01, 0x01 },
+ { "DATA_IN_PHASE", 0x02, 0x02 },
+ { "MSG_OUT_PHASE", 0x04, 0x04 },
+ { "MSG_IN_PHASE", 0x08, 0x08 },
+ { "COMMAND_PHASE", 0x10, 0x10 },
+ { "STATUS_PHASE", 0x20, 0x20 },
+ { "DATA_PHASE_MASK", 0x03, 0x03 }
+};
+
+int
+ahc_scsiphase_print(u_int regvalue, u_int *cur_col, u_int wrap)
+{
+ return (ahc_print_register(SCSIPHASE_parse_table, 7, "SCSIPHASE",
+ 0x9e, regvalue, cur_col, wrap));
+}
+
+static ahc_reg_parse_entry_t SFUNCT_parse_table[] = {
+ { "ALT_MODE", 0x80, 0x80 }
+};
+
+int
+ahc_sfunct_print(u_int regvalue, u_int *cur_col, u_int wrap)
+{
+ return (ahc_print_register(SFUNCT_parse_table, 1, "SFUNCT",
+ 0x9f, regvalue, cur_col, wrap));
+}
+
+int
+ahc_scb_base_print(u_int regvalue, u_int *cur_col, u_int wrap)
+{
+ return (ahc_print_register(NULL, 0, "SCB_BASE",
+ 0xa0, regvalue, cur_col, wrap));
+}
+
+int
+ahc_scb_cdb_ptr_print(u_int regvalue, u_int *cur_col, u_int wrap)
+{
+ return (ahc_print_register(NULL, 0, "SCB_CDB_PTR",
+ 0xa0, regvalue, cur_col, wrap));
+}
+
+int
+ahc_scb_residual_sgptr_print(u_int regvalue, u_int *cur_col, u_int wrap)
+{
+ return (ahc_print_register(NULL, 0, "SCB_RESIDUAL_SGPTR",
+ 0xa4, regvalue, cur_col, wrap));
+}
+
+int
+ahc_scb_scsi_status_print(u_int regvalue, u_int *cur_col, u_int wrap)
+{
+ return (ahc_print_register(NULL, 0, "SCB_SCSI_STATUS",
+ 0xa8, regvalue, cur_col, wrap));
+}
+
+int
+ahc_scb_target_phases_print(u_int regvalue, u_int *cur_col, u_int wrap)
+{
+ return (ahc_print_register(NULL, 0, "SCB_TARGET_PHASES",
+ 0xa9, regvalue, cur_col, wrap));
+}
+
+int
+ahc_scb_target_data_dir_print(u_int regvalue, u_int *cur_col, u_int wrap)
+{
+ return (ahc_print_register(NULL, 0, "SCB_TARGET_DATA_DIR",
+ 0xaa, regvalue, cur_col, wrap));
+}
+
+int
+ahc_scb_target_itag_print(u_int regvalue, u_int *cur_col, u_int wrap)
+{
+ return (ahc_print_register(NULL, 0, "SCB_TARGET_ITAG",
+ 0xab, regvalue, cur_col, wrap));
+}
+
+int
+ahc_scb_dataptr_print(u_int regvalue, u_int *cur_col, u_int wrap)
+{
+ return (ahc_print_register(NULL, 0, "SCB_DATAPTR",
+ 0xac, regvalue, cur_col, wrap));
+}
+
+static ahc_reg_parse_entry_t SCB_DATACNT_parse_table[] = {
+ { "SG_LAST_SEG", 0x80, 0x80 },
+ { "SG_HIGH_ADDR_BITS", 0x7f, 0x7f }
+};
+
+int
+ahc_scb_datacnt_print(u_int regvalue, u_int *cur_col, u_int wrap)
+{
+ return (ahc_print_register(SCB_DATACNT_parse_table, 2, "SCB_DATACNT",
+ 0xb0, regvalue, cur_col, wrap));
+}
+
+static ahc_reg_parse_entry_t SCB_SGPTR_parse_table[] = {
+ { "SG_LIST_NULL", 0x01, 0x01 },
+ { "SG_FULL_RESID", 0x02, 0x02 },
+ { "SG_RESID_VALID", 0x04, 0x04 }
+};
+
+int
+ahc_scb_sgptr_print(u_int regvalue, u_int *cur_col, u_int wrap)
+{
+ return (ahc_print_register(SCB_SGPTR_parse_table, 3, "SCB_SGPTR",
+ 0xb4, regvalue, cur_col, wrap));
+}
+
+static ahc_reg_parse_entry_t SCB_CONTROL_parse_table[] = {
+ { "DISCONNECTED", 0x04, 0x04 },
+ { "ULTRAENB", 0x08, 0x08 },
+ { "MK_MESSAGE", 0x10, 0x10 },
+ { "TAG_ENB", 0x20, 0x20 },
+ { "DISCENB", 0x40, 0x40 },
+ { "TARGET_SCB", 0x80, 0x80 },
+ { "STATUS_RCVD", 0x80, 0x80 },
+ { "SCB_TAG_TYPE", 0x03, 0x03 }
+};
+
+int
+ahc_scb_control_print(u_int regvalue, u_int *cur_col, u_int wrap)
+{
+ return (ahc_print_register(SCB_CONTROL_parse_table, 8, "SCB_CONTROL",
+ 0xb8, regvalue, cur_col, wrap));
+}
+
+static ahc_reg_parse_entry_t SCB_SCSIID_parse_table[] = {
+ { "TWIN_CHNLB", 0x80, 0x80 },
+ { "OID", 0x0f, 0x0f },
+ { "TWIN_TID", 0x70, 0x70 },
+ { "TID", 0xf0, 0xf0 }
+};
+
+int
+ahc_scb_scsiid_print(u_int regvalue, u_int *cur_col, u_int wrap)
+{
+ return (ahc_print_register(SCB_SCSIID_parse_table, 4, "SCB_SCSIID",
+ 0xb9, regvalue, cur_col, wrap));
+}
+
+static ahc_reg_parse_entry_t SCB_LUN_parse_table[] = {
+ { "SCB_XFERLEN_ODD", 0x80, 0x80 },
+ { "LID", 0x3f, 0x3f }
+};
+
+int
+ahc_scb_lun_print(u_int regvalue, u_int *cur_col, u_int wrap)
+{
+ return (ahc_print_register(SCB_LUN_parse_table, 2, "SCB_LUN",
+ 0xba, regvalue, cur_col, wrap));
+}
+
+int
+ahc_scb_tag_print(u_int regvalue, u_int *cur_col, u_int wrap)
+{
+ return (ahc_print_register(NULL, 0, "SCB_TAG",
+ 0xbb, regvalue, cur_col, wrap));
+}
+
+int
+ahc_scb_cdb_len_print(u_int regvalue, u_int *cur_col, u_int wrap)
+{
+ return (ahc_print_register(NULL, 0, "SCB_CDB_LEN",
+ 0xbc, regvalue, cur_col, wrap));
+}
+
+int
+ahc_scb_scsirate_print(u_int regvalue, u_int *cur_col, u_int wrap)
+{
+ return (ahc_print_register(NULL, 0, "SCB_SCSIRATE",
+ 0xbd, regvalue, cur_col, wrap));
+}
+
+int
+ahc_scb_scsioffset_print(u_int regvalue, u_int *cur_col, u_int wrap)
+{
+ return (ahc_print_register(NULL, 0, "SCB_SCSIOFFSET",
+ 0xbe, regvalue, cur_col, wrap));
+}
+
+int
+ahc_scb_next_print(u_int regvalue, u_int *cur_col, u_int wrap)
+{
+ return (ahc_print_register(NULL, 0, "SCB_NEXT",
+ 0xbf, regvalue, cur_col, wrap));
+}
+
+int
+ahc_scb_64_spare_print(u_int regvalue, u_int *cur_col, u_int wrap)
+{
+ return (ahc_print_register(NULL, 0, "SCB_64_SPARE",
+ 0xc0, regvalue, cur_col, wrap));
+}
+
+static ahc_reg_parse_entry_t SEECTL_2840_parse_table[] = {
+ { "DO_2840", 0x01, 0x01 },
+ { "CK_2840", 0x02, 0x02 },
+ { "CS_2840", 0x04, 0x04 }
+};
+
+int
+ahc_seectl_2840_print(u_int regvalue, u_int *cur_col, u_int wrap)
+{
+ return (ahc_print_register(SEECTL_2840_parse_table, 3, "SEECTL_2840",
+ 0xc0, regvalue, cur_col, wrap));
+}
+
+static ahc_reg_parse_entry_t STATUS_2840_parse_table[] = {
+ { "DI_2840", 0x01, 0x01 },
+ { "EEPROM_TF", 0x80, 0x80 },
+ { "ADSEL", 0x1e, 0x1e },
+ { "BIOS_SEL", 0x60, 0x60 }
+};
+
+int
+ahc_status_2840_print(u_int regvalue, u_int *cur_col, u_int wrap)
+{
+ return (ahc_print_register(STATUS_2840_parse_table, 4, "STATUS_2840",
+ 0xc1, regvalue, cur_col, wrap));
+}
+
+int
+ahc_scb_64_btt_print(u_int regvalue, u_int *cur_col, u_int wrap)
+{
+ return (ahc_print_register(NULL, 0, "SCB_64_BTT",
+ 0xd0, regvalue, cur_col, wrap));
+}
+
+int
+ahc_cchaddr_print(u_int regvalue, u_int *cur_col, u_int wrap)
+{
+ return (ahc_print_register(NULL, 0, "CCHADDR",
+ 0xe0, regvalue, cur_col, wrap));
+}
+
+int
+ahc_cchcnt_print(u_int regvalue, u_int *cur_col, u_int wrap)
+{
+ return (ahc_print_register(NULL, 0, "CCHCNT",
+ 0xe8, regvalue, cur_col, wrap));
+}
+
+int
+ahc_ccsgram_print(u_int regvalue, u_int *cur_col, u_int wrap)
+{
+ return (ahc_print_register(NULL, 0, "CCSGRAM",
+ 0xe9, regvalue, cur_col, wrap));
+}
+
+int
+ahc_ccsgaddr_print(u_int regvalue, u_int *cur_col, u_int wrap)
+{
+ return (ahc_print_register(NULL, 0, "CCSGADDR",
+ 0xea, regvalue, cur_col, wrap));
+}
+
+static ahc_reg_parse_entry_t CCSGCTL_parse_table[] = {
+ { "CCSGRESET", 0x01, 0x01 },
+ { "SG_FETCH_NEEDED", 0x02, 0x02 },
+ { "CCSGEN", 0x08, 0x08 },
+ { "CCSGDONE", 0x80, 0x80 }
+};
+
+int
+ahc_ccsgctl_print(u_int regvalue, u_int *cur_col, u_int wrap)
+{
+ return (ahc_print_register(CCSGCTL_parse_table, 4, "CCSGCTL",
+ 0xeb, regvalue, cur_col, wrap));
+}
+
+int
+ahc_ccscbram_print(u_int regvalue, u_int *cur_col, u_int wrap)
+{
+ return (ahc_print_register(NULL, 0, "CCSCBRAM",
+ 0xec, regvalue, cur_col, wrap));
+}
+
+int
+ahc_ccscbaddr_print(u_int regvalue, u_int *cur_col, u_int wrap)
+{
+ return (ahc_print_register(NULL, 0, "CCSCBADDR",
+ 0xed, regvalue, cur_col, wrap));
+}
+
+static ahc_reg_parse_entry_t CCSCBCTL_parse_table[] = {
+ { "CCSCBRESET", 0x01, 0x01 },
+ { "CCSCBDIR", 0x04, 0x04 },
+ { "CCSCBEN", 0x08, 0x08 },
+ { "CCARREN", 0x10, 0x10 },
+ { "ARRDONE", 0x40, 0x40 },
+ { "CCSCBDONE", 0x80, 0x80 }
+};
+
+int
+ahc_ccscbctl_print(u_int regvalue, u_int *cur_col, u_int wrap)
+{
+ return (ahc_print_register(CCSCBCTL_parse_table, 6, "CCSCBCTL",
+ 0xee, regvalue, cur_col, wrap));
+}
+
+int
+ahc_ccscbcnt_print(u_int regvalue, u_int *cur_col, u_int wrap)
+{
+ return (ahc_print_register(NULL, 0, "CCSCBCNT",
+ 0xef, regvalue, cur_col, wrap));
+}
+
+int
+ahc_scbbaddr_print(u_int regvalue, u_int *cur_col, u_int wrap)
+{
+ return (ahc_print_register(NULL, 0, "SCBBADDR",
+ 0xf0, regvalue, cur_col, wrap));
+}
+
+int
+ahc_ccscbptr_print(u_int regvalue, u_int *cur_col, u_int wrap)
+{
+ return (ahc_print_register(NULL, 0, "CCSCBPTR",
+ 0xf1, regvalue, cur_col, wrap));
+}
+
+int
+ahc_hnscb_qoff_print(u_int regvalue, u_int *cur_col, u_int wrap)
+{
+ return (ahc_print_register(NULL, 0, "HNSCB_QOFF",
+ 0xf4, regvalue, cur_col, wrap));
+}
+
+int
+ahc_snscb_qoff_print(u_int regvalue, u_int *cur_col, u_int wrap)
+{
+ return (ahc_print_register(NULL, 0, "SNSCB_QOFF",
+ 0xf6, regvalue, cur_col, wrap));
+}
+
+int
+ahc_sdscb_qoff_print(u_int regvalue, u_int *cur_col, u_int wrap)
+{
+ return (ahc_print_register(NULL, 0, "SDSCB_QOFF",
+ 0xf8, regvalue, cur_col, wrap));
+}
+
+static ahc_reg_parse_entry_t QOFF_CTLSTA_parse_table[] = {
+ { "SDSCB_ROLLOVER", 0x10, 0x10 },
+ { "SNSCB_ROLLOVER", 0x20, 0x20 },
+ { "SCB_AVAIL", 0x40, 0x40 },
+ { "SCB_QSIZE_256", 0x06, 0x06 },
+ { "SCB_QSIZE", 0x07, 0x07 }
+};
+
+int
+ahc_qoff_ctlsta_print(u_int regvalue, u_int *cur_col, u_int wrap)
+{
+ return (ahc_print_register(QOFF_CTLSTA_parse_table, 5, "QOFF_CTLSTA",
+ 0xfa, regvalue, cur_col, wrap));
+}
+
+static ahc_reg_parse_entry_t DFF_THRSH_parse_table[] = {
+ { "RD_DFTHRSH_MIN", 0x00, 0x00 },
+ { "WR_DFTHRSH_MIN", 0x00, 0x00 },
+ { "RD_DFTHRSH_25", 0x01, 0x01 },
+ { "RD_DFTHRSH_50", 0x02, 0x02 },
+ { "RD_DFTHRSH_63", 0x03, 0x03 },
+ { "RD_DFTHRSH_75", 0x04, 0x04 },
+ { "RD_DFTHRSH_85", 0x05, 0x05 },
+ { "RD_DFTHRSH_90", 0x06, 0x06 },
+ { "RD_DFTHRSH", 0x07, 0x07 },
+ { "RD_DFTHRSH_MAX", 0x07, 0x07 },
+ { "WR_DFTHRSH_25", 0x10, 0x10 },
+ { "WR_DFTHRSH_50", 0x20, 0x20 },
+ { "WR_DFTHRSH_63", 0x30, 0x30 },
+ { "WR_DFTHRSH_75", 0x40, 0x40 },
+ { "WR_DFTHRSH_85", 0x50, 0x50 },
+ { "WR_DFTHRSH_90", 0x60, 0x60 },
+ { "WR_DFTHRSH", 0x70, 0x70 },
+ { "WR_DFTHRSH_MAX", 0x70, 0x70 }
+};
+
+int
+ahc_dff_thrsh_print(u_int regvalue, u_int *cur_col, u_int wrap)
+{
+ return (ahc_print_register(DFF_THRSH_parse_table, 18, "DFF_THRSH",
+ 0xfb, regvalue, cur_col, wrap));
+}
+
+static ahc_reg_parse_entry_t SG_CACHE_SHADOW_parse_table[] = {
+ { "LAST_SEG_DONE", 0x01, 0x01 },
+ { "LAST_SEG", 0x02, 0x02 },
+ { "SG_ADDR_MASK", 0xf8, 0xf8 }
+};
+
+int
+ahc_sg_cache_shadow_print(u_int regvalue, u_int *cur_col, u_int wrap)
+{
+ return (ahc_print_register(SG_CACHE_SHADOW_parse_table, 3, "SG_CACHE_SHADOW",
+ 0xfc, regvalue, cur_col, wrap));
+}
+
+static ahc_reg_parse_entry_t SG_CACHE_PRE_parse_table[] = {
+ { "LAST_SEG_DONE", 0x01, 0x01 },
+ { "LAST_SEG", 0x02, 0x02 },
+ { "SG_ADDR_MASK", 0xf8, 0xf8 }
+};
+
+int
+ahc_sg_cache_pre_print(u_int regvalue, u_int *cur_col, u_int wrap)
+{
+ return (ahc_print_register(SG_CACHE_PRE_parse_table, 3, "SG_CACHE_PRE",
+ 0xfc, regvalue, cur_col, wrap));
+}
+
Property changes on: trunk/sys/dev/aic7xxx/aic7xxx_reg_print.c
___________________________________________________________________
Added: svn:eol-style
## -0,0 +1 ##
+native
\ No newline at end of property
Added: svn:keywords
## -0,0 +1 ##
+MidnightBSD=%H
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+text/plain
\ No newline at end of property
Added: trunk/sys/dev/aic7xxx/aic7xxx_seq.h
===================================================================
--- trunk/sys/dev/aic7xxx/aic7xxx_seq.h (rev 0)
+++ trunk/sys/dev/aic7xxx/aic7xxx_seq.h 2018-05-28 00:27:43 UTC (rev 10128)
@@ -0,0 +1,1313 @@
+/* $MidnightBSD$ */
+/*
+ * DO NOT EDIT - This file is automatically generated
+ * from the following source files:
+ *
+ * $Id: //depot/aic7xxx/aic7xxx/aic7xxx.seq#58 $
+ * $Id: //depot/aic7xxx/aic7xxx/aic7xxx.reg#40 $
+ *
+ * $FreeBSD: stable/10/sys/dev/aic7xxx/aic7xxx_seq.h 270284 2014-08-21 17:18:21Z ian $
+ */
+static uint8_t seqprog[] = {
+ 0xb2, 0x00, 0x00, 0x08,
+ 0xf7, 0x11, 0x22, 0x08,
+ 0x00, 0x65, 0xee, 0x59,
+ 0xf7, 0x01, 0x02, 0x08,
+ 0xff, 0x6a, 0x24, 0x08,
+ 0x40, 0x00, 0x40, 0x68,
+ 0x08, 0x1f, 0x3e, 0x10,
+ 0x40, 0x00, 0x40, 0x68,
+ 0xff, 0x40, 0x3c, 0x60,
+ 0x08, 0x1f, 0x3e, 0x10,
+ 0x60, 0x0b, 0x42, 0x68,
+ 0x40, 0xfa, 0x12, 0x78,
+ 0x01, 0x4d, 0xc8, 0x30,
+ 0x00, 0x4c, 0x12, 0x70,
+ 0x01, 0x39, 0xa2, 0x30,
+ 0x00, 0x6a, 0xc2, 0x5e,
+ 0x01, 0x51, 0x20, 0x31,
+ 0x01, 0x57, 0xae, 0x00,
+ 0x0d, 0x6a, 0x76, 0x00,
+ 0x00, 0x51, 0x14, 0x5e,
+ 0x01, 0x51, 0xc8, 0x30,
+ 0x00, 0x39, 0xc8, 0x60,
+ 0x00, 0xbb, 0x30, 0x70,
+ 0xc1, 0x6a, 0xda, 0x5e,
+ 0x01, 0xbf, 0x72, 0x30,
+ 0x01, 0x40, 0x7e, 0x31,
+ 0x01, 0x90, 0x80, 0x30,
+ 0x01, 0xf6, 0xd4, 0x30,
+ 0x01, 0x4d, 0x9a, 0x18,
+ 0xfe, 0x57, 0xae, 0x08,
+ 0x01, 0x40, 0x20, 0x31,
+ 0x00, 0x65, 0xcc, 0x58,
+ 0x60, 0x0b, 0x40, 0x78,
+ 0x08, 0x6a, 0x18, 0x00,
+ 0x08, 0x11, 0x22, 0x00,
+ 0x60, 0x0b, 0x00, 0x78,
+ 0x40, 0x0b, 0xfa, 0x68,
+ 0x80, 0x0b, 0xb6, 0x78,
+ 0x20, 0x6a, 0x16, 0x00,
+ 0xa4, 0x6a, 0x06, 0x00,
+ 0x08, 0x6a, 0x78, 0x00,
+ 0x01, 0x50, 0xc8, 0x30,
+ 0xe0, 0x6a, 0xcc, 0x00,
+ 0x48, 0x6a, 0xfe, 0x5d,
+ 0x01, 0x6a, 0xdc, 0x01,
+ 0x88, 0x6a, 0xcc, 0x00,
+ 0x48, 0x6a, 0xfe, 0x5d,
+ 0x01, 0x6a, 0x26, 0x01,
+ 0xf0, 0x19, 0x7a, 0x08,
+ 0x0f, 0x18, 0xc8, 0x08,
+ 0x0f, 0x0f, 0xc8, 0x08,
+ 0x0f, 0x05, 0xc8, 0x08,
+ 0x00, 0x3d, 0x7a, 0x00,
+ 0x08, 0x1f, 0x6e, 0x78,
+ 0x80, 0x3d, 0x7a, 0x00,
+ 0x01, 0x3d, 0xd8, 0x31,
+ 0x01, 0x3d, 0x32, 0x31,
+ 0x10, 0x03, 0x4e, 0x79,
+ 0x00, 0x65, 0xf2, 0x58,
+ 0x80, 0x66, 0xae, 0x78,
+ 0x01, 0x66, 0xd8, 0x31,
+ 0x01, 0x66, 0x32, 0x31,
+ 0x3f, 0x66, 0x7c, 0x08,
+ 0x40, 0x66, 0x82, 0x68,
+ 0x01, 0x3c, 0x78, 0x00,
+ 0x10, 0x03, 0x9e, 0x78,
+ 0x00, 0x65, 0xf2, 0x58,
+ 0xe0, 0x66, 0xc8, 0x18,
+ 0x00, 0x65, 0xaa, 0x50,
+ 0xdd, 0x66, 0xc8, 0x18,
+ 0x00, 0x65, 0xaa, 0x48,
+ 0x01, 0x66, 0xd8, 0x31,
+ 0x01, 0x66, 0x32, 0x31,
+ 0x10, 0x03, 0x4e, 0x79,
+ 0x00, 0x65, 0xf2, 0x58,
+ 0x01, 0x66, 0xd8, 0x31,
+ 0x01, 0x66, 0x32, 0x31,
+ 0x01, 0x66, 0xac, 0x30,
+ 0x40, 0x3c, 0x78, 0x00,
+ 0xff, 0x6a, 0xd8, 0x01,
+ 0xff, 0x6a, 0x32, 0x01,
+ 0x10, 0x3c, 0x78, 0x00,
+ 0x02, 0x57, 0x40, 0x69,
+ 0x10, 0x03, 0x3e, 0x69,
+ 0x00, 0x65, 0x20, 0x41,
+ 0x02, 0x57, 0xae, 0x00,
+ 0x00, 0x65, 0x9e, 0x40,
+ 0x61, 0x6a, 0xda, 0x5e,
+ 0x08, 0x51, 0x20, 0x71,
+ 0x02, 0x0b, 0xb2, 0x78,
+ 0x00, 0x65, 0xae, 0x40,
+ 0x1a, 0x01, 0x02, 0x00,
+ 0xf0, 0x19, 0x7a, 0x08,
+ 0x0f, 0x0f, 0xc8, 0x08,
+ 0x0f, 0x05, 0xc8, 0x08,
+ 0x00, 0x3d, 0x7a, 0x00,
+ 0x08, 0x1f, 0xc4, 0x78,
+ 0x80, 0x3d, 0x7a, 0x00,
+ 0x20, 0x6a, 0x16, 0x00,
+ 0x00, 0x65, 0xcc, 0x41,
+ 0x00, 0x65, 0xb4, 0x5e,
+ 0x00, 0x65, 0x12, 0x40,
+ 0x20, 0x11, 0xd2, 0x68,
+ 0x20, 0x6a, 0x18, 0x00,
+ 0x20, 0x11, 0x22, 0x00,
+ 0xf7, 0x1f, 0xca, 0x08,
+ 0x80, 0xb9, 0xd8, 0x78,
+ 0x08, 0x65, 0xca, 0x00,
+ 0x01, 0x65, 0x3e, 0x30,
+ 0x01, 0xb9, 0x1e, 0x30,
+ 0x7f, 0xb9, 0x0a, 0x08,
+ 0x01, 0xb9, 0x0a, 0x30,
+ 0x01, 0x54, 0xca, 0x30,
+ 0x80, 0xb8, 0xe6, 0x78,
+ 0x80, 0x65, 0xca, 0x00,
+ 0x01, 0x65, 0x00, 0x34,
+ 0x01, 0x54, 0x00, 0x34,
+ 0x08, 0xb8, 0xee, 0x78,
+ 0x20, 0x01, 0x02, 0x00,
+ 0x02, 0xbd, 0x08, 0x34,
+ 0x01, 0xbd, 0x08, 0x34,
+ 0x08, 0x01, 0x02, 0x00,
+ 0x02, 0x0b, 0xf4, 0x78,
+ 0xf7, 0x01, 0x02, 0x08,
+ 0x01, 0x06, 0xcc, 0x34,
+ 0xb2, 0x00, 0x00, 0x08,
+ 0x01, 0x40, 0x20, 0x31,
+ 0x01, 0xbf, 0x80, 0x30,
+ 0x01, 0xb9, 0x7a, 0x30,
+ 0x3f, 0xba, 0x7c, 0x08,
+ 0x00, 0x65, 0xea, 0x58,
+ 0x80, 0x0b, 0xc4, 0x79,
+ 0x12, 0x01, 0x02, 0x00,
+ 0x01, 0xab, 0xac, 0x30,
+ 0xe4, 0x6a, 0x70, 0x5d,
+ 0x40, 0x6a, 0x16, 0x00,
+ 0x80, 0x3e, 0x86, 0x5d,
+ 0x20, 0xb8, 0x18, 0x79,
+ 0x20, 0x6a, 0x86, 0x5d,
+ 0x00, 0xab, 0x86, 0x5d,
+ 0x01, 0xa9, 0x78, 0x30,
+ 0x10, 0xb8, 0x20, 0x79,
+ 0xe4, 0x6a, 0x70, 0x5d,
+ 0x00, 0x65, 0xae, 0x40,
+ 0x10, 0x03, 0x3c, 0x69,
+ 0x08, 0x3c, 0x5a, 0x69,
+ 0x04, 0x3c, 0x92, 0x69,
+ 0x02, 0x3c, 0x98, 0x69,
+ 0x01, 0x3c, 0x44, 0x79,
+ 0xff, 0x6a, 0xa6, 0x00,
+ 0x00, 0x65, 0xa4, 0x59,
+ 0x00, 0x6a, 0xc2, 0x5e,
+ 0xff, 0x53, 0x30, 0x71,
+ 0x0d, 0x6a, 0x76, 0x00,
+ 0x00, 0x53, 0x14, 0x5e,
+ 0x00, 0x65, 0xea, 0x58,
+ 0x12, 0x01, 0x02, 0x00,
+ 0x00, 0x65, 0x18, 0x41,
+ 0xa4, 0x6a, 0x06, 0x00,
+ 0x00, 0x65, 0xf2, 0x58,
+ 0xfd, 0x57, 0xae, 0x08,
+ 0x00, 0x65, 0xae, 0x40,
+ 0xe4, 0x6a, 0x70, 0x5d,
+ 0x20, 0x3c, 0x4a, 0x79,
+ 0x02, 0x6a, 0x86, 0x5d,
+ 0x04, 0x6a, 0x86, 0x5d,
+ 0x01, 0x03, 0x4c, 0x69,
+ 0xf7, 0x11, 0x22, 0x08,
+ 0xff, 0x6a, 0x24, 0x08,
+ 0xff, 0x6a, 0x06, 0x08,
+ 0x01, 0x6a, 0x7e, 0x00,
+ 0x00, 0x65, 0xa4, 0x59,
+ 0x00, 0x65, 0x04, 0x40,
+ 0x80, 0x86, 0xc8, 0x08,
+ 0x01, 0x4f, 0xc8, 0x30,
+ 0x00, 0x50, 0x6c, 0x61,
+ 0xc4, 0x6a, 0x70, 0x5d,
+ 0x40, 0x3c, 0x68, 0x79,
+ 0x28, 0x6a, 0x86, 0x5d,
+ 0x00, 0x65, 0x4c, 0x41,
+ 0x08, 0x6a, 0x86, 0x5d,
+ 0x00, 0x65, 0x4c, 0x41,
+ 0x84, 0x6a, 0x70, 0x5d,
+ 0x00, 0x65, 0xf2, 0x58,
+ 0x01, 0x66, 0xc8, 0x30,
+ 0x01, 0x64, 0xd8, 0x31,
+ 0x01, 0x64, 0x32, 0x31,
+ 0x5b, 0x64, 0xc8, 0x28,
+ 0x30, 0x64, 0xca, 0x18,
+ 0x01, 0x6c, 0xc8, 0x30,
+ 0xff, 0x64, 0x8e, 0x79,
+ 0x08, 0x01, 0x02, 0x00,
+ 0x02, 0x0b, 0x80, 0x79,
+ 0x01, 0x64, 0x86, 0x61,
+ 0xf7, 0x01, 0x02, 0x08,
+ 0x01, 0x06, 0xd8, 0x31,
+ 0x01, 0x06, 0x32, 0x31,
+ 0xff, 0x64, 0xc8, 0x18,
+ 0xff, 0x64, 0x80, 0x69,
+ 0xf7, 0x3c, 0x78, 0x08,
+ 0x00, 0x65, 0x20, 0x41,
+ 0x40, 0xaa, 0x7e, 0x10,
+ 0x04, 0xaa, 0x70, 0x5d,
+ 0x00, 0x65, 0x58, 0x42,
+ 0xc4, 0x6a, 0x70, 0x5d,
+ 0xc0, 0x6a, 0x7e, 0x00,
+ 0x00, 0xa8, 0x86, 0x5d,
+ 0xe4, 0x6a, 0x06, 0x00,
+ 0x00, 0x6a, 0x86, 0x5d,
+ 0x00, 0x65, 0x4c, 0x41,
+ 0x10, 0x3c, 0xa8, 0x69,
+ 0x00, 0xbb, 0x8c, 0x44,
+ 0x18, 0x6a, 0xda, 0x01,
+ 0x01, 0x69, 0xd8, 0x31,
+ 0x1c, 0x6a, 0xd0, 0x01,
+ 0x09, 0xee, 0xdc, 0x01,
+ 0x80, 0xee, 0xb0, 0x79,
+ 0xff, 0x6a, 0xdc, 0x09,
+ 0x01, 0x93, 0x26, 0x01,
+ 0x03, 0x6a, 0x2a, 0x01,
+ 0x01, 0x69, 0x32, 0x31,
+ 0x1c, 0x6a, 0xe2, 0x5d,
+ 0x0a, 0x93, 0x26, 0x01,
+ 0x00, 0x65, 0xaa, 0x5e,
+ 0x01, 0x50, 0xa0, 0x18,
+ 0x02, 0x6a, 0x22, 0x05,
+ 0x1a, 0x01, 0x02, 0x00,
+ 0x80, 0x6a, 0x74, 0x00,
+ 0x40, 0x6a, 0x78, 0x00,
+ 0x40, 0x6a, 0x16, 0x00,
+ 0x00, 0x65, 0xda, 0x5d,
+ 0x01, 0x3f, 0xc8, 0x30,
+ 0xbf, 0x64, 0x58, 0x7a,
+ 0x80, 0x64, 0xa0, 0x73,
+ 0xa0, 0x64, 0x02, 0x74,
+ 0xc0, 0x64, 0xf6, 0x73,
+ 0xe0, 0x64, 0x32, 0x74,
+ 0x01, 0x6a, 0xda, 0x5e,
+ 0x00, 0x65, 0xcc, 0x41,
+ 0xf7, 0x11, 0x22, 0x08,
+ 0x01, 0x06, 0xd4, 0x30,
+ 0xff, 0x6a, 0x24, 0x08,
+ 0xf7, 0x01, 0x02, 0x08,
+ 0xc0, 0x6a, 0x78, 0x00,
+ 0x09, 0x0c, 0xe8, 0x79,
+ 0x08, 0x0c, 0x04, 0x68,
+ 0xb1, 0x6a, 0xda, 0x5e,
+ 0xff, 0x6a, 0x26, 0x09,
+ 0x12, 0x01, 0x02, 0x00,
+ 0x02, 0x6a, 0x08, 0x30,
+ 0xff, 0x6a, 0x08, 0x08,
+ 0xdf, 0x01, 0x02, 0x08,
+ 0x01, 0x6a, 0x7e, 0x00,
+ 0xc0, 0x6a, 0x78, 0x04,
+ 0xff, 0x6a, 0xc8, 0x08,
+ 0x08, 0xa4, 0x48, 0x19,
+ 0x00, 0xa5, 0x4a, 0x21,
+ 0x00, 0xa6, 0x4c, 0x21,
+ 0x00, 0xa7, 0x4e, 0x25,
+ 0x08, 0xeb, 0xde, 0x7e,
+ 0x80, 0xeb, 0x08, 0x7a,
+ 0xff, 0x6a, 0xd6, 0x09,
+ 0x08, 0xeb, 0x0c, 0x6a,
+ 0xff, 0x6a, 0xd4, 0x0c,
+ 0x80, 0xa3, 0xde, 0x6e,
+ 0x88, 0xeb, 0x22, 0x72,
+ 0x08, 0xeb, 0xde, 0x6e,
+ 0x04, 0xea, 0x26, 0xe2,
+ 0x08, 0xee, 0xde, 0x6e,
+ 0x04, 0x6a, 0xd0, 0x81,
+ 0x05, 0xa4, 0xc0, 0x89,
+ 0x03, 0xa5, 0xc2, 0x31,
+ 0x09, 0x6a, 0xd6, 0x05,
+ 0x00, 0x65, 0x0a, 0x5a,
+ 0x06, 0xa4, 0xd4, 0x89,
+ 0x80, 0x94, 0xde, 0x7e,
+ 0x07, 0xe9, 0x10, 0x31,
+ 0x01, 0xe9, 0x46, 0x31,
+ 0x00, 0xa3, 0xbc, 0x5e,
+ 0x00, 0x65, 0xfc, 0x59,
+ 0x01, 0xa4, 0xca, 0x30,
+ 0x80, 0xa3, 0x36, 0x7a,
+ 0x02, 0x65, 0xca, 0x00,
+ 0x01, 0x65, 0xf8, 0x31,
+ 0x80, 0x93, 0x26, 0x01,
+ 0xff, 0x6a, 0xd4, 0x0c,
+ 0x01, 0x8c, 0xc8, 0x30,
+ 0x00, 0x88, 0xc8, 0x18,
+ 0x02, 0x64, 0xc8, 0x88,
+ 0xff, 0x64, 0xde, 0x7e,
+ 0xff, 0x8d, 0x4c, 0x6a,
+ 0xff, 0x8e, 0x4c, 0x6a,
+ 0x03, 0x8c, 0xd4, 0x98,
+ 0x00, 0x65, 0xde, 0x56,
+ 0x01, 0x64, 0x70, 0x30,
+ 0xff, 0x64, 0xc8, 0x10,
+ 0x01, 0x64, 0xc8, 0x18,
+ 0x00, 0x8c, 0x18, 0x19,
+ 0xff, 0x8d, 0x1a, 0x21,
+ 0xff, 0x8e, 0x1c, 0x25,
+ 0xc0, 0x3c, 0x5c, 0x7a,
+ 0x21, 0x6a, 0xda, 0x5e,
+ 0xa8, 0x6a, 0x76, 0x00,
+ 0x79, 0x6a, 0x76, 0x00,
+ 0x40, 0x3f, 0x64, 0x6a,
+ 0x04, 0x3b, 0x76, 0x00,
+ 0x04, 0x6a, 0xd4, 0x81,
+ 0x20, 0x3c, 0x6c, 0x7a,
+ 0x51, 0x6a, 0xda, 0x5e,
+ 0x00, 0x65, 0x84, 0x42,
+ 0x20, 0x3c, 0x78, 0x00,
+ 0x00, 0xb3, 0xbc, 0x5e,
+ 0x07, 0xac, 0x10, 0x31,
+ 0x05, 0xb3, 0x46, 0x31,
+ 0x88, 0x6a, 0xcc, 0x00,
+ 0xac, 0x6a, 0xf0, 0x5d,
+ 0xa3, 0x6a, 0xcc, 0x00,
+ 0xb3, 0x6a, 0xf4, 0x5d,
+ 0x00, 0x65, 0x3c, 0x5a,
+ 0xfd, 0xa4, 0x48, 0x09,
+ 0x03, 0x8c, 0x10, 0x30,
+ 0x00, 0x65, 0xe8, 0x5d,
+ 0x01, 0xa4, 0x96, 0x7a,
+ 0x04, 0x3b, 0x76, 0x08,
+ 0x01, 0x3b, 0x26, 0x31,
+ 0x80, 0x02, 0x04, 0x00,
+ 0x10, 0x0c, 0x8c, 0x7a,
+ 0x03, 0x9e, 0x8e, 0x6a,
+ 0x7f, 0x02, 0x04, 0x08,
+ 0x91, 0x6a, 0xda, 0x5e,
+ 0x00, 0x65, 0xcc, 0x41,
+ 0x01, 0xa4, 0xca, 0x30,
+ 0x80, 0xa3, 0x9c, 0x7a,
+ 0x02, 0x65, 0xca, 0x00,
+ 0x01, 0x65, 0xf8, 0x31,
+ 0x01, 0x3b, 0x26, 0x31,
+ 0x00, 0x65, 0x10, 0x5a,
+ 0x01, 0xfc, 0xaa, 0x6a,
+ 0x80, 0x0b, 0xa0, 0x6a,
+ 0x10, 0x0c, 0xa0, 0x7a,
+ 0x20, 0x93, 0xa0, 0x6a,
+ 0x02, 0x93, 0x26, 0x01,
+ 0x02, 0xfc, 0xb4, 0x7a,
+ 0x40, 0x0d, 0xc8, 0x6a,
+ 0x01, 0xa4, 0x48, 0x01,
+ 0x00, 0x65, 0xc8, 0x42,
+ 0x40, 0x0d, 0xba, 0x6a,
+ 0x00, 0x65, 0x10, 0x5a,
+ 0x00, 0x65, 0xac, 0x42,
+ 0x80, 0xfc, 0xc4, 0x7a,
+ 0x80, 0xa4, 0xc4, 0x6a,
+ 0xff, 0xa5, 0x4a, 0x19,
+ 0xff, 0xa6, 0x4c, 0x21,
+ 0xff, 0xa7, 0x4e, 0x21,
+ 0xf8, 0xfc, 0x48, 0x09,
+ 0x7f, 0xa3, 0x46, 0x09,
+ 0x04, 0x3b, 0xe4, 0x6a,
+ 0x02, 0x93, 0x26, 0x01,
+ 0x01, 0x94, 0xca, 0x7a,
+ 0x01, 0x94, 0xca, 0x7a,
+ 0x01, 0x94, 0xca, 0x7a,
+ 0x01, 0x94, 0xca, 0x7a,
+ 0x01, 0x94, 0xca, 0x7a,
+ 0x01, 0xa4, 0xe2, 0x7a,
+ 0x01, 0xfc, 0xd8, 0x7a,
+ 0x01, 0x94, 0xe4, 0x6a,
+ 0x01, 0x94, 0xe4, 0x6a,
+ 0x01, 0x94, 0xe4, 0x6a,
+ 0x00, 0x65, 0x84, 0x42,
+ 0x01, 0x94, 0xe2, 0x7a,
+ 0x10, 0x94, 0xe4, 0x6a,
+ 0xd7, 0x93, 0x26, 0x09,
+ 0x28, 0x93, 0xe8, 0x6a,
+ 0x01, 0x85, 0x0a, 0x01,
+ 0x02, 0xfc, 0xf0, 0x6a,
+ 0x01, 0x14, 0x46, 0x31,
+ 0xff, 0x6a, 0x10, 0x09,
+ 0xfe, 0x85, 0x0a, 0x09,
+ 0xff, 0x38, 0xfe, 0x6a,
+ 0x80, 0xa3, 0xfe, 0x7a,
+ 0x80, 0x0b, 0xfc, 0x7a,
+ 0x04, 0x3b, 0xfe, 0x7a,
+ 0xbf, 0x3b, 0x76, 0x08,
+ 0x01, 0x3b, 0x26, 0x31,
+ 0x00, 0x65, 0x10, 0x5a,
+ 0x01, 0x0b, 0x0c, 0x6b,
+ 0x10, 0x0c, 0x00, 0x7b,
+ 0x04, 0x93, 0x0a, 0x6b,
+ 0x01, 0x94, 0x08, 0x7b,
+ 0x10, 0x94, 0x0a, 0x6b,
+ 0xc7, 0x93, 0x26, 0x09,
+ 0x01, 0x99, 0xd4, 0x30,
+ 0x38, 0x93, 0x0e, 0x6b,
+ 0xff, 0x08, 0x5c, 0x6b,
+ 0xff, 0x09, 0x5c, 0x6b,
+ 0xff, 0x0a, 0x5c, 0x6b,
+ 0xff, 0x38, 0x2a, 0x7b,
+ 0x04, 0x14, 0x10, 0x31,
+ 0x01, 0x38, 0x18, 0x31,
+ 0x02, 0x6a, 0x1a, 0x31,
+ 0x88, 0x6a, 0xcc, 0x00,
+ 0x14, 0x6a, 0xf6, 0x5d,
+ 0x00, 0x38, 0xe2, 0x5d,
+ 0xff, 0x6a, 0x70, 0x08,
+ 0x00, 0x65, 0x56, 0x43,
+ 0x80, 0xa3, 0x30, 0x7b,
+ 0x01, 0xa4, 0x48, 0x01,
+ 0x00, 0x65, 0x5c, 0x43,
+ 0x08, 0xeb, 0x36, 0x7b,
+ 0x00, 0x65, 0x10, 0x5a,
+ 0x08, 0xeb, 0x32, 0x6b,
+ 0x07, 0xe9, 0x10, 0x31,
+ 0x01, 0xe9, 0xca, 0x30,
+ 0x01, 0x65, 0x46, 0x31,
+ 0x00, 0x6a, 0xbc, 0x5e,
+ 0x88, 0x6a, 0xcc, 0x00,
+ 0xa4, 0x6a, 0xf6, 0x5d,
+ 0x08, 0x6a, 0xe2, 0x5d,
+ 0x0d, 0x93, 0x26, 0x01,
+ 0x00, 0x65, 0xaa, 0x5e,
+ 0x88, 0x6a, 0xcc, 0x00,
+ 0x00, 0x65, 0x8c, 0x5e,
+ 0x01, 0x99, 0x46, 0x31,
+ 0x00, 0xa3, 0xbc, 0x5e,
+ 0x01, 0x88, 0x10, 0x31,
+ 0x00, 0x65, 0x3c, 0x5a,
+ 0x00, 0x65, 0xfc, 0x59,
+ 0x03, 0x8c, 0x10, 0x30,
+ 0x00, 0x65, 0xe8, 0x5d,
+ 0x80, 0x0b, 0x84, 0x6a,
+ 0x80, 0x0b, 0x64, 0x6b,
+ 0x01, 0x0c, 0x5e, 0x7b,
+ 0x10, 0x0c, 0x84, 0x7a,
+ 0x03, 0x9e, 0x84, 0x6a,
+ 0x00, 0x65, 0x06, 0x5a,
+ 0x00, 0x6a, 0xbc, 0x5e,
+ 0x01, 0xa4, 0x84, 0x6b,
+ 0xff, 0x38, 0x7a, 0x7b,
+ 0x01, 0x38, 0xc8, 0x30,
+ 0x00, 0x08, 0x40, 0x19,
+ 0xff, 0x6a, 0xc8, 0x08,
+ 0x00, 0x09, 0x42, 0x21,
+ 0x00, 0x0a, 0x44, 0x21,
+ 0xff, 0x6a, 0x70, 0x08,
+ 0x00, 0x65, 0x7c, 0x43,
+ 0x03, 0x08, 0x40, 0x31,
+ 0x03, 0x08, 0x40, 0x31,
+ 0x01, 0x08, 0x40, 0x31,
+ 0x01, 0x09, 0x42, 0x31,
+ 0x01, 0x0a, 0x44, 0x31,
+ 0xfd, 0xb4, 0x68, 0x09,
+ 0x12, 0x01, 0x02, 0x00,
+ 0x12, 0x01, 0x02, 0x00,
+ 0x04, 0x3c, 0xcc, 0x79,
+ 0xfb, 0x3c, 0x78, 0x08,
+ 0x04, 0x93, 0x20, 0x79,
+ 0x01, 0x0c, 0x90, 0x6b,
+ 0x80, 0xba, 0x20, 0x79,
+ 0x80, 0x04, 0x20, 0x79,
+ 0xe4, 0x6a, 0x70, 0x5d,
+ 0x23, 0x6a, 0x86, 0x5d,
+ 0x01, 0x6a, 0x86, 0x5d,
+ 0x00, 0x65, 0x20, 0x41,
+ 0x00, 0x65, 0xcc, 0x41,
+ 0x80, 0x3c, 0xa4, 0x7b,
+ 0x21, 0x6a, 0xda, 0x5e,
+ 0x01, 0xbc, 0x18, 0x31,
+ 0x02, 0x6a, 0x1a, 0x31,
+ 0x02, 0x6a, 0xf8, 0x01,
+ 0x01, 0xbc, 0x10, 0x30,
+ 0x02, 0x6a, 0x12, 0x30,
+ 0x01, 0xbc, 0x10, 0x30,
+ 0xff, 0x6a, 0x12, 0x08,
+ 0xff, 0x6a, 0x14, 0x08,
+ 0xf3, 0xbc, 0xd4, 0x18,
+ 0xa0, 0x6a, 0xca, 0x53,
+ 0x04, 0xa0, 0x10, 0x31,
+ 0xac, 0x6a, 0x26, 0x01,
+ 0x04, 0xa0, 0x10, 0x31,
+ 0x03, 0x08, 0x18, 0x31,
+ 0x88, 0x6a, 0xcc, 0x00,
+ 0xa0, 0x6a, 0xf6, 0x5d,
+ 0x00, 0xbc, 0xe2, 0x5d,
+ 0x3d, 0x6a, 0x26, 0x01,
+ 0x00, 0x65, 0xe2, 0x43,
+ 0xff, 0x6a, 0x10, 0x09,
+ 0xa4, 0x6a, 0x26, 0x01,
+ 0x0c, 0xa0, 0x32, 0x31,
+ 0x05, 0x6a, 0x26, 0x01,
+ 0x35, 0x6a, 0x26, 0x01,
+ 0x0c, 0xa0, 0x32, 0x31,
+ 0x36, 0x6a, 0x26, 0x01,
+ 0x02, 0x93, 0x26, 0x01,
+ 0x35, 0x6a, 0x26, 0x01,
+ 0x00, 0x65, 0x9e, 0x5e,
+ 0x00, 0x65, 0x9e, 0x5e,
+ 0x02, 0x93, 0x26, 0x01,
+ 0xbf, 0x3c, 0x78, 0x08,
+ 0x04, 0x0b, 0xe8, 0x6b,
+ 0x10, 0x0c, 0xe4, 0x7b,
+ 0x01, 0x03, 0xe8, 0x6b,
+ 0x20, 0x93, 0xea, 0x6b,
+ 0x04, 0x0b, 0xf0, 0x6b,
+ 0x40, 0x3c, 0x78, 0x00,
+ 0xc7, 0x93, 0x26, 0x09,
+ 0x38, 0x93, 0xf2, 0x6b,
+ 0x00, 0x65, 0xcc, 0x41,
+ 0x80, 0x3c, 0x58, 0x6c,
+ 0x01, 0x06, 0x50, 0x31,
+ 0x80, 0xb8, 0x70, 0x01,
+ 0x00, 0x65, 0xcc, 0x41,
+ 0x10, 0x3f, 0x06, 0x00,
+ 0x10, 0x6a, 0x06, 0x00,
+ 0x01, 0x3a, 0xca, 0x30,
+ 0x80, 0x65, 0x1e, 0x64,
+ 0x10, 0xb8, 0x42, 0x6c,
+ 0xc0, 0x3e, 0xca, 0x00,
+ 0x40, 0xb8, 0x0e, 0x6c,
+ 0xbf, 0x65, 0xca, 0x08,
+ 0x20, 0xb8, 0x22, 0x7c,
+ 0x01, 0x65, 0x0c, 0x30,
+ 0x00, 0x65, 0xda, 0x5d,
+ 0xa0, 0x3f, 0x2a, 0x64,
+ 0x23, 0xb8, 0x0c, 0x08,
+ 0x00, 0x65, 0xda, 0x5d,
+ 0xa0, 0x3f, 0x2a, 0x64,
+ 0x00, 0xbb, 0x22, 0x44,
+ 0xff, 0x65, 0x22, 0x64,
+ 0x00, 0x65, 0x42, 0x44,
+ 0x40, 0x6a, 0x18, 0x00,
+ 0x01, 0x65, 0x0c, 0x30,
+ 0x00, 0x65, 0xda, 0x5d,
+ 0xa0, 0x3f, 0xfe, 0x73,
+ 0x40, 0x6a, 0x18, 0x00,
+ 0x01, 0x3a, 0xa6, 0x30,
+ 0x08, 0x6a, 0x74, 0x00,
+ 0x00, 0x65, 0xcc, 0x41,
+ 0x64, 0x6a, 0x6a, 0x5d,
+ 0x80, 0x64, 0xda, 0x6c,
+ 0x04, 0x64, 0x9c, 0x74,
+ 0x02, 0x64, 0xac, 0x74,
+ 0x00, 0x6a, 0x62, 0x74,
+ 0x03, 0x64, 0xca, 0x74,
+ 0x23, 0x64, 0x4a, 0x74,
+ 0x08, 0x64, 0x5e, 0x74,
+ 0x61, 0x6a, 0xda, 0x5e,
+ 0x00, 0x65, 0xda, 0x5d,
+ 0x08, 0x51, 0xce, 0x71,
+ 0x00, 0x65, 0x42, 0x44,
+ 0x80, 0x04, 0x5c, 0x7c,
+ 0x51, 0x6a, 0x60, 0x5d,
+ 0x01, 0x51, 0x5c, 0x64,
+ 0x01, 0xa4, 0x54, 0x7c,
+ 0x80, 0xba, 0x5e, 0x6c,
+ 0x41, 0x6a, 0xda, 0x5e,
+ 0x00, 0x65, 0x5e, 0x44,
+ 0x21, 0x6a, 0xda, 0x5e,
+ 0x00, 0x65, 0x5e, 0x44,
+ 0x07, 0x6a, 0x56, 0x5d,
+ 0x01, 0x06, 0xd4, 0x30,
+ 0x00, 0x65, 0xcc, 0x41,
+ 0x80, 0xb8, 0x58, 0x7c,
+ 0xc0, 0x3c, 0x6c, 0x7c,
+ 0x80, 0x3c, 0x58, 0x6c,
+ 0xff, 0xa8, 0x6c, 0x6c,
+ 0x40, 0x3c, 0x58, 0x6c,
+ 0x10, 0xb8, 0x70, 0x7c,
+ 0xa1, 0x6a, 0xda, 0x5e,
+ 0x01, 0xb4, 0x76, 0x6c,
+ 0x02, 0xb4, 0x78, 0x6c,
+ 0x01, 0xa4, 0x78, 0x7c,
+ 0xff, 0xa8, 0x88, 0x7c,
+ 0x04, 0xb4, 0x68, 0x01,
+ 0x01, 0x6a, 0x76, 0x00,
+ 0x00, 0xbb, 0x14, 0x5e,
+ 0xff, 0xa8, 0x88, 0x7c,
+ 0x71, 0x6a, 0xda, 0x5e,
+ 0x40, 0x51, 0x88, 0x64,
+ 0x00, 0x65, 0xb4, 0x5e,
+ 0x00, 0x65, 0xde, 0x41,
+ 0x00, 0xbb, 0x8c, 0x5c,
+ 0x00, 0x65, 0xde, 0x41,
+ 0x00, 0x65, 0xb4, 0x5e,
+ 0x01, 0x65, 0xa2, 0x30,
+ 0x01, 0xf8, 0xc8, 0x30,
+ 0x01, 0x4e, 0xc8, 0x30,
+ 0x00, 0x6a, 0xb8, 0xdd,
+ 0x00, 0x51, 0xca, 0x5d,
+ 0x01, 0x4e, 0x9c, 0x18,
+ 0x02, 0x6a, 0x22, 0x05,
+ 0xc0, 0x3c, 0x58, 0x6c,
+ 0x04, 0xb8, 0x70, 0x01,
+ 0x00, 0x65, 0xd6, 0x5e,
+ 0x20, 0xb8, 0xde, 0x69,
+ 0x01, 0xbb, 0xa2, 0x30,
+ 0x3f, 0xba, 0x7c, 0x08,
+ 0x00, 0xb9, 0xd0, 0x5c,
+ 0x00, 0x65, 0xde, 0x41,
+ 0x01, 0x06, 0xd4, 0x30,
+ 0x20, 0x3c, 0xcc, 0x79,
+ 0x20, 0x3c, 0x5e, 0x7c,
+ 0x01, 0xa4, 0xba, 0x7c,
+ 0x01, 0xb4, 0x68, 0x01,
+ 0x00, 0x65, 0xcc, 0x41,
+ 0x00, 0x65, 0x5e, 0x44,
+ 0x04, 0x14, 0x58, 0x31,
+ 0x01, 0x06, 0xd4, 0x30,
+ 0x08, 0xa0, 0x60, 0x31,
+ 0xac, 0x6a, 0xcc, 0x00,
+ 0x14, 0x6a, 0xf6, 0x5d,
+ 0x01, 0x06, 0xd4, 0x30,
+ 0xa0, 0x6a, 0xee, 0x5d,
+ 0x00, 0x65, 0xcc, 0x41,
+ 0xdf, 0x3c, 0x78, 0x08,
+ 0x12, 0x01, 0x02, 0x00,
+ 0x00, 0x65, 0x5e, 0x44,
+ 0x4c, 0x65, 0xcc, 0x28,
+ 0x01, 0x3e, 0x20, 0x31,
+ 0xd0, 0x66, 0xcc, 0x18,
+ 0x20, 0x66, 0xcc, 0x18,
+ 0x01, 0x51, 0xda, 0x34,
+ 0x4c, 0x3d, 0xca, 0x28,
+ 0x3f, 0x64, 0x7c, 0x08,
+ 0xd0, 0x65, 0xca, 0x18,
+ 0x01, 0x3e, 0x20, 0x31,
+ 0x30, 0x65, 0xd4, 0x18,
+ 0x00, 0x65, 0xe8, 0x4c,
+ 0xe1, 0x6a, 0x22, 0x01,
+ 0xff, 0x6a, 0xd4, 0x08,
+ 0x20, 0x65, 0xd4, 0x18,
+ 0x00, 0x65, 0xf0, 0x54,
+ 0xe1, 0x6a, 0x22, 0x01,
+ 0xff, 0x6a, 0xd4, 0x08,
+ 0x20, 0x65, 0xca, 0x18,
+ 0xe0, 0x65, 0xd4, 0x18,
+ 0x00, 0x65, 0xfa, 0x4c,
+ 0xe1, 0x6a, 0x22, 0x01,
+ 0xff, 0x6a, 0xd4, 0x08,
+ 0xd0, 0x65, 0xd4, 0x18,
+ 0x00, 0x65, 0x02, 0x55,
+ 0xe1, 0x6a, 0x22, 0x01,
+ 0xff, 0x6a, 0xd4, 0x08,
+ 0x01, 0x6c, 0xa2, 0x30,
+ 0xff, 0x51, 0x14, 0x75,
+ 0x00, 0x51, 0x90, 0x5d,
+ 0x01, 0x51, 0x20, 0x31,
+ 0x00, 0x65, 0x36, 0x45,
+ 0x3f, 0xba, 0xc8, 0x08,
+ 0x00, 0x3e, 0x36, 0x75,
+ 0x00, 0x65, 0xb2, 0x5e,
+ 0x80, 0x3c, 0x78, 0x00,
+ 0x01, 0x06, 0xd4, 0x30,
+ 0x00, 0x65, 0xda, 0x5d,
+ 0x01, 0x3c, 0x78, 0x00,
+ 0xe0, 0x3f, 0x52, 0x65,
+ 0x02, 0x3c, 0x78, 0x00,
+ 0x20, 0x12, 0x52, 0x65,
+ 0x51, 0x6a, 0x60, 0x5d,
+ 0x00, 0x51, 0x90, 0x5d,
+ 0x51, 0x6a, 0x60, 0x5d,
+ 0x01, 0x51, 0x20, 0x31,
+ 0x04, 0x3c, 0x78, 0x00,
+ 0x01, 0xb9, 0xc8, 0x30,
+ 0x00, 0x3d, 0x50, 0x65,
+ 0x08, 0x3c, 0x78, 0x00,
+ 0x3f, 0xba, 0xc8, 0x08,
+ 0x00, 0x3e, 0x50, 0x65,
+ 0x10, 0x3c, 0x78, 0x00,
+ 0x04, 0xb8, 0x50, 0x7d,
+ 0xfb, 0xb8, 0x70, 0x09,
+ 0x20, 0xb8, 0x46, 0x6d,
+ 0x01, 0x90, 0xc8, 0x30,
+ 0xff, 0x6a, 0xa2, 0x00,
+ 0x00, 0x3d, 0xd0, 0x5c,
+ 0x01, 0x64, 0x20, 0x31,
+ 0xff, 0x6a, 0x78, 0x08,
+ 0x00, 0x65, 0xea, 0x58,
+ 0x10, 0xb8, 0x5e, 0x7c,
+ 0xff, 0x6a, 0x56, 0x5d,
+ 0x00, 0x65, 0x5e, 0x44,
+ 0x00, 0x65, 0xb2, 0x5e,
+ 0x31, 0x6a, 0xda, 0x5e,
+ 0x00, 0x65, 0x5e, 0x44,
+ 0x10, 0x3f, 0x06, 0x00,
+ 0x10, 0x6a, 0x06, 0x00,
+ 0x01, 0x65, 0x74, 0x34,
+ 0x81, 0x6a, 0xda, 0x5e,
+ 0x00, 0x65, 0x62, 0x45,
+ 0x01, 0x06, 0xd4, 0x30,
+ 0x01, 0x0c, 0x62, 0x7d,
+ 0x04, 0x0c, 0x5c, 0x6d,
+ 0xe0, 0x03, 0x7e, 0x08,
+ 0xe0, 0x3f, 0xcc, 0x61,
+ 0x01, 0x65, 0xcc, 0x30,
+ 0x01, 0x12, 0xda, 0x34,
+ 0x01, 0x06, 0xd4, 0x34,
+ 0x01, 0x03, 0x70, 0x6d,
+ 0x40, 0x03, 0xcc, 0x08,
+ 0x01, 0x65, 0x06, 0x30,
+ 0x40, 0x65, 0xc8, 0x08,
+ 0x00, 0x66, 0x7e, 0x75,
+ 0x40, 0x65, 0x7e, 0x7d,
+ 0x00, 0x65, 0x7e, 0x5d,
+ 0xff, 0x6a, 0xd4, 0x08,
+ 0xff, 0x6a, 0xd4, 0x08,
+ 0xff, 0x6a, 0xd4, 0x08,
+ 0xff, 0x6a, 0xd4, 0x0c,
+ 0x08, 0x01, 0x02, 0x00,
+ 0x02, 0x0b, 0x88, 0x7d,
+ 0x01, 0x65, 0x0c, 0x30,
+ 0x02, 0x0b, 0x8c, 0x7d,
+ 0xf7, 0x01, 0x02, 0x0c,
+ 0x01, 0x65, 0xc8, 0x30,
+ 0xff, 0x41, 0xb0, 0x75,
+ 0x01, 0x41, 0x20, 0x31,
+ 0xff, 0x6a, 0xa4, 0x00,
+ 0x00, 0x65, 0xa0, 0x45,
+ 0xff, 0xbf, 0xb0, 0x75,
+ 0x01, 0x90, 0xa4, 0x30,
+ 0x01, 0xbf, 0x20, 0x31,
+ 0x00, 0xbb, 0x9a, 0x65,
+ 0xff, 0x52, 0xae, 0x75,
+ 0x01, 0xbf, 0xcc, 0x30,
+ 0x01, 0x90, 0xca, 0x30,
+ 0x01, 0x52, 0x20, 0x31,
+ 0x01, 0x66, 0x7e, 0x31,
+ 0x01, 0x65, 0x20, 0x35,
+ 0x01, 0xbf, 0x82, 0x34,
+ 0x01, 0x64, 0xa2, 0x30,
+ 0x00, 0x6a, 0xc2, 0x5e,
+ 0x0d, 0x6a, 0x76, 0x00,
+ 0x00, 0x51, 0x14, 0x46,
+ 0x01, 0x65, 0xa4, 0x30,
+ 0xe0, 0x6a, 0xcc, 0x00,
+ 0x48, 0x6a, 0x08, 0x5e,
+ 0x01, 0x6a, 0xd0, 0x01,
+ 0x01, 0x6a, 0xdc, 0x05,
+ 0x88, 0x6a, 0xcc, 0x00,
+ 0x48, 0x6a, 0x08, 0x5e,
+ 0x01, 0x6a, 0xe2, 0x5d,
+ 0x01, 0x6a, 0x26, 0x05,
+ 0x01, 0x65, 0xd8, 0x31,
+ 0x09, 0xee, 0xdc, 0x01,
+ 0x80, 0xee, 0xce, 0x7d,
+ 0xff, 0x6a, 0xdc, 0x0d,
+ 0x01, 0x65, 0x32, 0x31,
+ 0x0a, 0x93, 0x26, 0x01,
+ 0x00, 0x65, 0xaa, 0x46,
+ 0x81, 0x6a, 0xda, 0x5e,
+ 0x01, 0x0c, 0xda, 0x7d,
+ 0x04, 0x0c, 0xd8, 0x6d,
+ 0xe0, 0x03, 0x06, 0x08,
+ 0xe0, 0x03, 0x7e, 0x0c,
+ 0x01, 0x65, 0x18, 0x31,
+ 0xff, 0x6a, 0x1a, 0x09,
+ 0xff, 0x6a, 0x1c, 0x0d,
+ 0x01, 0x8c, 0x10, 0x30,
+ 0x01, 0x8d, 0x12, 0x30,
+ 0x01, 0x8e, 0x14, 0x34,
+ 0x01, 0x6c, 0xda, 0x30,
+ 0x01, 0x6c, 0xda, 0x30,
+ 0x01, 0x6c, 0xda, 0x30,
+ 0x01, 0x6c, 0xda, 0x30,
+ 0x01, 0x6c, 0xda, 0x30,
+ 0x01, 0x6c, 0xda, 0x30,
+ 0x01, 0x6c, 0xda, 0x30,
+ 0x01, 0x6c, 0xda, 0x34,
+ 0x3d, 0x64, 0xa4, 0x28,
+ 0x55, 0x64, 0xc8, 0x28,
+ 0x00, 0x65, 0x08, 0x46,
+ 0x2e, 0x64, 0xa4, 0x28,
+ 0x66, 0x64, 0xc8, 0x28,
+ 0x00, 0x6c, 0xda, 0x18,
+ 0x01, 0x52, 0xc8, 0x30,
+ 0x00, 0x6c, 0xda, 0x20,
+ 0xff, 0x6a, 0xc8, 0x08,
+ 0x00, 0x6c, 0xda, 0x20,
+ 0x00, 0x6c, 0xda, 0x24,
+ 0x01, 0x65, 0xc8, 0x30,
+ 0xe0, 0x6a, 0xcc, 0x00,
+ 0x44, 0x6a, 0x04, 0x5e,
+ 0x01, 0x90, 0xe2, 0x31,
+ 0x04, 0x3b, 0x28, 0x7e,
+ 0x30, 0x6a, 0xd0, 0x01,
+ 0x20, 0x6a, 0xd0, 0x01,
+ 0x1d, 0x6a, 0xdc, 0x01,
+ 0xdc, 0xee, 0x24, 0x66,
+ 0x00, 0x65, 0x40, 0x46,
+ 0x20, 0x6a, 0xd0, 0x01,
+ 0x01, 0x6a, 0xdc, 0x01,
+ 0x20, 0xa0, 0xd8, 0x31,
+ 0x09, 0xee, 0xdc, 0x01,
+ 0x80, 0xee, 0x30, 0x7e,
+ 0x11, 0x6a, 0xdc, 0x01,
+ 0x50, 0xee, 0x34, 0x66,
+ 0x20, 0x6a, 0xd0, 0x01,
+ 0x09, 0x6a, 0xdc, 0x01,
+ 0x88, 0xee, 0x3a, 0x66,
+ 0x19, 0x6a, 0xdc, 0x01,
+ 0xd8, 0xee, 0x3e, 0x66,
+ 0xff, 0x6a, 0xdc, 0x09,
+ 0x18, 0xee, 0x42, 0x6e,
+ 0xff, 0x6a, 0xd4, 0x0c,
+ 0x88, 0x6a, 0xcc, 0x00,
+ 0x44, 0x6a, 0x04, 0x5e,
+ 0x20, 0x6a, 0xe2, 0x5d,
+ 0x01, 0x3b, 0x26, 0x31,
+ 0x04, 0x3b, 0x5c, 0x6e,
+ 0xa0, 0x6a, 0xca, 0x00,
+ 0x20, 0x65, 0xc8, 0x18,
+ 0x00, 0x65, 0x9a, 0x5e,
+ 0x00, 0x65, 0x54, 0x66,
+ 0x0a, 0x93, 0x26, 0x01,
+ 0x00, 0x65, 0xaa, 0x46,
+ 0xa0, 0x6a, 0xcc, 0x00,
+ 0xff, 0x6a, 0xc8, 0x08,
+ 0x20, 0x94, 0x60, 0x6e,
+ 0x10, 0x94, 0x62, 0x6e,
+ 0x08, 0x94, 0x7c, 0x6e,
+ 0x08, 0x94, 0x7c, 0x6e,
+ 0x08, 0x94, 0x7c, 0x6e,
+ 0xff, 0x8c, 0xc8, 0x10,
+ 0xc1, 0x64, 0xc8, 0x18,
+ 0xf8, 0x64, 0xc8, 0x08,
+ 0x01, 0x99, 0xda, 0x30,
+ 0x00, 0x66, 0x70, 0x66,
+ 0xc0, 0x66, 0xac, 0x76,
+ 0x60, 0x66, 0xc8, 0x18,
+ 0x3d, 0x64, 0xc8, 0x28,
+ 0x00, 0x65, 0x60, 0x46,
+ 0xf7, 0x93, 0x26, 0x09,
+ 0x08, 0x93, 0x7e, 0x6e,
+ 0x00, 0x62, 0xc4, 0x18,
+ 0x00, 0x65, 0xaa, 0x5e,
+ 0x00, 0x65, 0x8a, 0x5e,
+ 0x00, 0x65, 0x8a, 0x5e,
+ 0x00, 0x65, 0x8a, 0x5e,
+ 0x01, 0x99, 0xda, 0x30,
+ 0x01, 0x99, 0xda, 0x30,
+ 0x01, 0x99, 0xda, 0x30,
+ 0x01, 0x99, 0xda, 0x30,
+ 0x01, 0x99, 0xda, 0x30,
+ 0x01, 0x99, 0xda, 0x30,
+ 0x01, 0x99, 0xda, 0x30,
+ 0x01, 0x99, 0xda, 0x34,
+ 0x01, 0x6c, 0x32, 0x31,
+ 0x01, 0x6c, 0x32, 0x31,
+ 0x01, 0x6c, 0x32, 0x31,
+ 0x01, 0x6c, 0x32, 0x31,
+ 0x01, 0x6c, 0x32, 0x31,
+ 0x01, 0x6c, 0x32, 0x31,
+ 0x01, 0x6c, 0x32, 0x31,
+ 0x01, 0x6c, 0x32, 0x35,
+ 0x08, 0x94, 0xaa, 0x7e,
+ 0xf7, 0x93, 0x26, 0x09,
+ 0x08, 0x93, 0xae, 0x6e,
+ 0xff, 0x6a, 0xd4, 0x0c,
+ 0x04, 0xb8, 0xd6, 0x6e,
+ 0x01, 0x42, 0x7e, 0x31,
+ 0xff, 0x6a, 0x76, 0x01,
+ 0x01, 0x90, 0x84, 0x34,
+ 0xff, 0x6a, 0x76, 0x05,
+ 0x01, 0x85, 0x0a, 0x01,
+ 0x7f, 0x65, 0x10, 0x09,
+ 0xfe, 0x85, 0x0a, 0x0d,
+ 0xff, 0x42, 0xd2, 0x66,
+ 0xff, 0x41, 0xca, 0x66,
+ 0xd1, 0x6a, 0xda, 0x5e,
+ 0xff, 0x6a, 0xca, 0x04,
+ 0x01, 0x41, 0x20, 0x31,
+ 0x01, 0xbf, 0x82, 0x30,
+ 0x01, 0x6a, 0x76, 0x00,
+ 0x00, 0xbb, 0x14, 0x46,
+ 0x01, 0x42, 0x20, 0x31,
+ 0x01, 0xbf, 0x84, 0x34,
+ 0x01, 0x41, 0x7e, 0x31,
+ 0x01, 0x90, 0x82, 0x34,
+ 0x01, 0x65, 0x22, 0x31,
+ 0xff, 0x6a, 0xd4, 0x08,
+ 0xff, 0x6a, 0xd4, 0x0c
+};
+
+typedef int ahc_patch_func_t (struct ahc_softc *ahc);
+static ahc_patch_func_t ahc_patch23_func;
+
+static int
+ahc_patch23_func(struct ahc_softc *ahc)
+{
+ return ((ahc->bugs & AHC_SCBCHAN_UPLOAD_BUG) != 0);
+}
+
+static ahc_patch_func_t ahc_patch22_func;
+
+static int
+ahc_patch22_func(struct ahc_softc *ahc)
+{
+ return ((ahc->features & AHC_CMD_CHAN) == 0);
+}
+
+static ahc_patch_func_t ahc_patch21_func;
+
+static int
+ahc_patch21_func(struct ahc_softc *ahc)
+{
+ return ((ahc->features & AHC_QUEUE_REGS) == 0);
+}
+
+static ahc_patch_func_t ahc_patch20_func;
+
+static int
+ahc_patch20_func(struct ahc_softc *ahc)
+{
+ return ((ahc->features & AHC_WIDE) != 0);
+}
+
+static ahc_patch_func_t ahc_patch19_func;
+
+static int
+ahc_patch19_func(struct ahc_softc *ahc)
+{
+ return ((ahc->flags & AHC_SCB_BTT) != 0);
+}
+
+static ahc_patch_func_t ahc_patch18_func;
+
+static int
+ahc_patch18_func(struct ahc_softc *ahc)
+{
+ return ((ahc->bugs & AHC_PCI_2_1_RETRY_BUG) != 0);
+}
+
+static ahc_patch_func_t ahc_patch17_func;
+
+static int
+ahc_patch17_func(struct ahc_softc *ahc)
+{
+ return ((ahc->bugs & AHC_TMODE_WIDEODD_BUG) != 0);
+}
+
+static ahc_patch_func_t ahc_patch16_func;
+
+static int
+ahc_patch16_func(struct ahc_softc *ahc)
+{
+ return ((ahc->bugs & AHC_AUTOFLUSH_BUG) != 0);
+}
+
+static ahc_patch_func_t ahc_patch15_func;
+
+static int
+ahc_patch15_func(struct ahc_softc *ahc)
+{
+ return ((ahc->features & AHC_ULTRA2) == 0);
+}
+
+static ahc_patch_func_t ahc_patch14_func;
+
+static int
+ahc_patch14_func(struct ahc_softc *ahc)
+{
+ return ((ahc->bugs & AHC_PCI_MWI_BUG) != 0 && ahc->pci_cachesize != 0);
+}
+
+static ahc_patch_func_t ahc_patch13_func;
+
+static int
+ahc_patch13_func(struct ahc_softc *ahc)
+{
+ return ((ahc->flags & AHC_39BIT_ADDRESSING) != 0);
+}
+
+static ahc_patch_func_t ahc_patch12_func;
+
+static int
+ahc_patch12_func(struct ahc_softc *ahc)
+{
+ return ((ahc->features & AHC_HS_MAILBOX) != 0);
+}
+
+static ahc_patch_func_t ahc_patch11_func;
+
+static int
+ahc_patch11_func(struct ahc_softc *ahc)
+{
+ return ((ahc->features & AHC_ULTRA) != 0);
+}
+
+static ahc_patch_func_t ahc_patch10_func;
+
+static int
+ahc_patch10_func(struct ahc_softc *ahc)
+{
+ return ((ahc->features & AHC_MULTI_TID) != 0);
+}
+
+static ahc_patch_func_t ahc_patch9_func;
+
+static int
+ahc_patch9_func(struct ahc_softc *ahc)
+{
+ return ((ahc->features & AHC_CMD_CHAN) != 0);
+}
+
+static ahc_patch_func_t ahc_patch8_func;
+
+static int
+ahc_patch8_func(struct ahc_softc *ahc)
+{
+ return ((ahc->flags & AHC_INITIATORROLE) != 0);
+}
+
+static ahc_patch_func_t ahc_patch7_func;
+
+static int
+ahc_patch7_func(struct ahc_softc *ahc)
+{
+ return ((ahc->flags & AHC_TARGETROLE) != 0);
+}
+
+static ahc_patch_func_t ahc_patch6_func;
+
+static int
+ahc_patch6_func(struct ahc_softc *ahc)
+{
+ return ((ahc->features & AHC_DT) == 0);
+}
+
+static ahc_patch_func_t ahc_patch5_func;
+
+static int
+ahc_patch5_func(struct ahc_softc *ahc)
+{
+ return ((ahc->flags & AHC_SEQUENCER_DEBUG) != 0);
+}
+
+static ahc_patch_func_t ahc_patch4_func;
+
+static int
+ahc_patch4_func(struct ahc_softc *ahc)
+{
+ return ((ahc->flags & AHC_PAGESCBS) != 0);
+}
+
+static ahc_patch_func_t ahc_patch3_func;
+
+static int
+ahc_patch3_func(struct ahc_softc *ahc)
+{
+ return ((ahc->features & AHC_QUEUE_REGS) != 0);
+}
+
+static ahc_patch_func_t ahc_patch2_func;
+
+static int
+ahc_patch2_func(struct ahc_softc *ahc)
+{
+ return ((ahc->features & AHC_TWIN) != 0);
+}
+
+static ahc_patch_func_t ahc_patch1_func;
+
+static int
+ahc_patch1_func(struct ahc_softc *ahc)
+{
+ return ((ahc->features & AHC_ULTRA2) != 0);
+}
+
+static ahc_patch_func_t ahc_patch0_func;
+
+static int
+ahc_patch0_func(struct ahc_softc *ahc)
+{
+ return (0);
+}
+
+static struct patch {
+ ahc_patch_func_t *patch_func;
+ uint32_t begin :10,
+ skip_instr :10,
+ skip_patch :12;
+} patches[] = {
+ { ahc_patch1_func, 4, 1, 1 },
+ { ahc_patch2_func, 6, 2, 1 },
+ { ahc_patch2_func, 9, 1, 1 },
+ { ahc_patch3_func, 11, 1, 2 },
+ { ahc_patch0_func, 12, 2, 1 },
+ { ahc_patch4_func, 15, 1, 2 },
+ { ahc_patch0_func, 16, 1, 1 },
+ { ahc_patch5_func, 22, 2, 1 },
+ { ahc_patch3_func, 27, 1, 2 },
+ { ahc_patch0_func, 28, 1, 1 },
+ { ahc_patch6_func, 34, 1, 1 },
+ { ahc_patch7_func, 37, 54, 19 },
+ { ahc_patch8_func, 37, 1, 1 },
+ { ahc_patch9_func, 42, 3, 2 },
+ { ahc_patch0_func, 45, 3, 1 },
+ { ahc_patch10_func, 49, 1, 2 },
+ { ahc_patch0_func, 50, 2, 3 },
+ { ahc_patch1_func, 50, 1, 2 },
+ { ahc_patch0_func, 51, 1, 1 },
+ { ahc_patch2_func, 53, 2, 1 },
+ { ahc_patch9_func, 55, 1, 2 },
+ { ahc_patch0_func, 56, 1, 1 },
+ { ahc_patch9_func, 60, 1, 2 },
+ { ahc_patch0_func, 61, 1, 1 },
+ { ahc_patch9_func, 71, 1, 2 },
+ { ahc_patch0_func, 72, 1, 1 },
+ { ahc_patch9_func, 75, 1, 2 },
+ { ahc_patch0_func, 76, 1, 1 },
+ { ahc_patch9_func, 79, 1, 2 },
+ { ahc_patch0_func, 80, 1, 1 },
+ { ahc_patch8_func, 91, 9, 4 },
+ { ahc_patch1_func, 93, 1, 2 },
+ { ahc_patch0_func, 94, 1, 1 },
+ { ahc_patch2_func, 96, 2, 1 },
+ { ahc_patch2_func, 105, 4, 1 },
+ { ahc_patch1_func, 109, 1, 2 },
+ { ahc_patch0_func, 110, 2, 3 },
+ { ahc_patch2_func, 110, 1, 2 },
+ { ahc_patch0_func, 111, 1, 1 },
+ { ahc_patch7_func, 112, 4, 2 },
+ { ahc_patch0_func, 116, 1, 1 },
+ { ahc_patch11_func, 117, 2, 1 },
+ { ahc_patch1_func, 119, 1, 2 },
+ { ahc_patch0_func, 120, 1, 1 },
+ { ahc_patch7_func, 121, 4, 1 },
+ { ahc_patch7_func, 131, 95, 11 },
+ { ahc_patch4_func, 151, 1, 1 },
+ { ahc_patch1_func, 168, 1, 1 },
+ { ahc_patch12_func, 173, 1, 2 },
+ { ahc_patch0_func, 174, 1, 1 },
+ { ahc_patch9_func, 185, 1, 2 },
+ { ahc_patch0_func, 186, 1, 1 },
+ { ahc_patch9_func, 195, 1, 2 },
+ { ahc_patch0_func, 196, 1, 1 },
+ { ahc_patch9_func, 212, 6, 2 },
+ { ahc_patch0_func, 218, 6, 1 },
+ { ahc_patch8_func, 226, 21, 2 },
+ { ahc_patch1_func, 241, 1, 1 },
+ { ahc_patch1_func, 249, 1, 2 },
+ { ahc_patch0_func, 250, 2, 2 },
+ { ahc_patch11_func, 251, 1, 1 },
+ { ahc_patch9_func, 259, 27, 3 },
+ { ahc_patch1_func, 275, 10, 2 },
+ { ahc_patch13_func, 278, 1, 1 },
+ { ahc_patch14_func, 286, 14, 1 },
+ { ahc_patch1_func, 302, 1, 2 },
+ { ahc_patch0_func, 303, 1, 1 },
+ { ahc_patch9_func, 306, 1, 1 },
+ { ahc_patch13_func, 311, 1, 1 },
+ { ahc_patch9_func, 312, 2, 2 },
+ { ahc_patch0_func, 314, 4, 1 },
+ { ahc_patch14_func, 318, 1, 1 },
+ { ahc_patch15_func, 320, 2, 3 },
+ { ahc_patch9_func, 320, 1, 2 },
+ { ahc_patch0_func, 321, 1, 1 },
+ { ahc_patch6_func, 326, 1, 2 },
+ { ahc_patch0_func, 327, 1, 1 },
+ { ahc_patch1_func, 331, 47, 11 },
+ { ahc_patch6_func, 338, 2, 4 },
+ { ahc_patch7_func, 338, 1, 1 },
+ { ahc_patch8_func, 339, 1, 1 },
+ { ahc_patch0_func, 340, 1, 1 },
+ { ahc_patch16_func, 341, 1, 1 },
+ { ahc_patch6_func, 357, 6, 3 },
+ { ahc_patch16_func, 357, 5, 1 },
+ { ahc_patch0_func, 363, 7, 1 },
+ { ahc_patch13_func, 373, 5, 1 },
+ { ahc_patch0_func, 378, 52, 17 },
+ { ahc_patch14_func, 378, 1, 1 },
+ { ahc_patch7_func, 380, 2, 2 },
+ { ahc_patch17_func, 381, 1, 1 },
+ { ahc_patch9_func, 384, 1, 1 },
+ { ahc_patch18_func, 391, 1, 1 },
+ { ahc_patch14_func, 396, 9, 3 },
+ { ahc_patch9_func, 397, 3, 2 },
+ { ahc_patch0_func, 400, 3, 1 },
+ { ahc_patch9_func, 408, 6, 2 },
+ { ahc_patch0_func, 414, 9, 2 },
+ { ahc_patch13_func, 414, 1, 1 },
+ { ahc_patch13_func, 423, 2, 1 },
+ { ahc_patch14_func, 425, 1, 1 },
+ { ahc_patch9_func, 427, 1, 2 },
+ { ahc_patch0_func, 428, 1, 1 },
+ { ahc_patch7_func, 429, 1, 1 },
+ { ahc_patch7_func, 430, 1, 1 },
+ { ahc_patch8_func, 431, 3, 3 },
+ { ahc_patch6_func, 432, 1, 2 },
+ { ahc_patch0_func, 433, 1, 1 },
+ { ahc_patch9_func, 434, 1, 1 },
+ { ahc_patch15_func, 435, 1, 2 },
+ { ahc_patch13_func, 435, 1, 1 },
+ { ahc_patch14_func, 437, 9, 4 },
+ { ahc_patch9_func, 437, 1, 1 },
+ { ahc_patch9_func, 444, 2, 1 },
+ { ahc_patch0_func, 446, 4, 3 },
+ { ahc_patch9_func, 446, 1, 2 },
+ { ahc_patch0_func, 447, 3, 1 },
+ { ahc_patch1_func, 451, 2, 1 },
+ { ahc_patch7_func, 453, 10, 2 },
+ { ahc_patch0_func, 463, 1, 1 },
+ { ahc_patch8_func, 464, 118, 22 },
+ { ahc_patch1_func, 466, 3, 2 },
+ { ahc_patch0_func, 469, 5, 3 },
+ { ahc_patch9_func, 469, 2, 2 },
+ { ahc_patch0_func, 471, 3, 1 },
+ { ahc_patch1_func, 476, 2, 2 },
+ { ahc_patch0_func, 478, 6, 3 },
+ { ahc_patch9_func, 478, 2, 2 },
+ { ahc_patch0_func, 480, 3, 1 },
+ { ahc_patch1_func, 486, 2, 2 },
+ { ahc_patch0_func, 488, 9, 7 },
+ { ahc_patch9_func, 488, 5, 6 },
+ { ahc_patch19_func, 488, 1, 2 },
+ { ahc_patch0_func, 489, 1, 1 },
+ { ahc_patch19_func, 491, 1, 2 },
+ { ahc_patch0_func, 492, 1, 1 },
+ { ahc_patch0_func, 493, 4, 1 },
+ { ahc_patch6_func, 498, 3, 2 },
+ { ahc_patch0_func, 501, 1, 1 },
+ { ahc_patch6_func, 511, 1, 2 },
+ { ahc_patch0_func, 512, 1, 1 },
+ { ahc_patch20_func, 549, 7, 1 },
+ { ahc_patch3_func, 584, 1, 2 },
+ { ahc_patch0_func, 585, 1, 1 },
+ { ahc_patch21_func, 588, 1, 1 },
+ { ahc_patch8_func, 590, 106, 33 },
+ { ahc_patch4_func, 592, 1, 1 },
+ { ahc_patch1_func, 598, 2, 2 },
+ { ahc_patch0_func, 600, 1, 1 },
+ { ahc_patch1_func, 603, 1, 2 },
+ { ahc_patch0_func, 604, 1, 1 },
+ { ahc_patch9_func, 605, 3, 3 },
+ { ahc_patch15_func, 606, 1, 1 },
+ { ahc_patch0_func, 608, 4, 1 },
+ { ahc_patch19_func, 617, 2, 2 },
+ { ahc_patch0_func, 619, 1, 1 },
+ { ahc_patch19_func, 623, 10, 3 },
+ { ahc_patch5_func, 625, 8, 1 },
+ { ahc_patch0_func, 633, 9, 2 },
+ { ahc_patch5_func, 634, 8, 1 },
+ { ahc_patch4_func, 644, 1, 2 },
+ { ahc_patch0_func, 645, 1, 1 },
+ { ahc_patch19_func, 646, 1, 2 },
+ { ahc_patch0_func, 647, 3, 2 },
+ { ahc_patch4_func, 649, 1, 1 },
+ { ahc_patch5_func, 650, 1, 1 },
+ { ahc_patch5_func, 653, 1, 1 },
+ { ahc_patch5_func, 655, 1, 1 },
+ { ahc_patch4_func, 657, 2, 2 },
+ { ahc_patch0_func, 659, 2, 1 },
+ { ahc_patch5_func, 661, 1, 1 },
+ { ahc_patch5_func, 664, 1, 1 },
+ { ahc_patch5_func, 667, 1, 1 },
+ { ahc_patch19_func, 671, 1, 1 },
+ { ahc_patch19_func, 674, 1, 1 },
+ { ahc_patch4_func, 680, 1, 1 },
+ { ahc_patch6_func, 683, 1, 2 },
+ { ahc_patch0_func, 684, 1, 1 },
+ { ahc_patch7_func, 696, 16, 1 },
+ { ahc_patch4_func, 712, 20, 1 },
+ { ahc_patch9_func, 733, 4, 2 },
+ { ahc_patch0_func, 737, 4, 1 },
+ { ahc_patch9_func, 741, 4, 2 },
+ { ahc_patch0_func, 745, 3, 1 },
+ { ahc_patch6_func, 751, 1, 1 },
+ { ahc_patch22_func, 753, 14, 1 },
+ { ahc_patch7_func, 767, 3, 1 },
+ { ahc_patch9_func, 779, 24, 8 },
+ { ahc_patch19_func, 783, 1, 2 },
+ { ahc_patch0_func, 784, 1, 1 },
+ { ahc_patch15_func, 789, 4, 2 },
+ { ahc_patch0_func, 793, 7, 3 },
+ { ahc_patch23_func, 793, 5, 2 },
+ { ahc_patch0_func, 798, 2, 1 },
+ { ahc_patch0_func, 803, 42, 3 },
+ { ahc_patch18_func, 815, 18, 2 },
+ { ahc_patch0_func, 833, 1, 1 },
+ { ahc_patch4_func, 857, 1, 1 },
+ { ahc_patch4_func, 858, 3, 2 },
+ { ahc_patch0_func, 861, 1, 1 },
+ { ahc_patch13_func, 862, 3, 1 },
+ { ahc_patch4_func, 865, 12, 1 }
+};
+
+static struct cs {
+ uint16_t begin;
+ uint16_t end;
+} critical_sections[] = {
+ { 8, 9 },
+ { 11, 18 },
+ { 21, 32 },
+ { 102, 117 },
+ { 712, 728 },
+ { 858, 861 },
+ { 865, 871 },
+ { 873, 875 },
+ { 875, 877 }
+};
+
+static const int num_critical_sections = sizeof(critical_sections)
+ / sizeof(*critical_sections);
Property changes on: trunk/sys/dev/aic7xxx/aic7xxx_seq.h
___________________________________________________________________
Added: svn:eol-style
## -0,0 +1 ##
+native
\ No newline at end of property
Added: svn:keywords
## -0,0 +1 ##
+MidnightBSD=%H
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+text/plain
\ No newline at end of property
Modified: trunk/sys/dev/aic7xxx/aic_osm_lib.c
===================================================================
--- trunk/sys/dev/aic7xxx/aic_osm_lib.c 2018-05-28 00:25:20 UTC (rev 10127)
+++ trunk/sys/dev/aic7xxx/aic_osm_lib.c 2018-05-28 00:27:43 UTC (rev 10128)
@@ -1,3 +1,4 @@
+/* $MidnightBSD$ */
/*-
* FreeBSD OSM Library for the aic7xxx aic79xx based Adaptec SCSI controllers
*
@@ -29,11 +30,11 @@
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*
- * $MidnightBSD: src/sys/dev/aic7xxx/aic_osm_lib.c,v 1.4 2009/03/15 14:24:21 laffer1 Exp $
- * $Id: aic_osm_lib.c,v 1.5 2012-08-06 01:19:11 laffer1 Exp $
+ * $Id: //depot/aic7xxx/freebsd/dev/aic7xxx/aic_osm_lib.c#5 $
*/
#include <sys/cdefs.h>
+__FBSDID("$FreeBSD: stable/10/sys/dev/aic7xxx/aic_osm_lib.c 239047 2012-08-05 08:08:34Z eadler $");
static void aic_recovery_thread(void *arg);
@@ -54,9 +55,6 @@
* them after we've successfully fixed this problem.
*/
LIST_FOREACH(list_scb, &aic->pending_scbs, pending_links) {
- union ccb *ccb;
-
- ccb = list_scb->io_ctx;
callout_stop(&scb->io_timer);
}
}
@@ -131,6 +129,23 @@
void
aic_calc_geometry(struct ccb_calc_geometry *ccg, int extended)
{
+#if __FreeBSD_version >= 500000
cam_calc_geometry(ccg, extended);
+#else
+ uint32_t size_mb;
+ uint32_t secs_per_cylinder;
+
+ size_mb = ccg->volume_size / ((1024L * 1024L) / ccg->block_size);
+ if (size_mb > 1024 && extended) {
+ ccg->heads = 255;
+ ccg->secs_per_track = 63;
+ } else {
+ ccg->heads = 64;
+ ccg->secs_per_track = 32;
+ }
+ secs_per_cylinder = ccg->heads * ccg->secs_per_track;
+ ccg->cylinders = ccg->volume_size / secs_per_cylinder;
+ ccg->ccb_h.status = CAM_REQ_CMP;
+#endif
}
Modified: trunk/sys/dev/aic7xxx/aic_osm_lib.h
===================================================================
--- trunk/sys/dev/aic7xxx/aic_osm_lib.h 2018-05-28 00:25:20 UTC (rev 10127)
+++ trunk/sys/dev/aic7xxx/aic_osm_lib.h 2018-05-28 00:27:43 UTC (rev 10128)
@@ -1,3 +1,4 @@
+/* $MidnightBSD$ */
/*-
* FreeBSD platform specific, shared driver option settings, data structures,
* function declarations and includes.
@@ -30,13 +31,15 @@
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*
- * $Id: aic_osm_lib.h,v 1.5 2012-08-06 01:19:11 laffer1 Exp $
+ * $Id: //depot/aic7xxx/freebsd/dev/aic7xxx/aic_osm_lib.h#5 $
*
- * $MidnightBSD: src/sys/dev/aic7xxx/aic_osm_lib.h,v 1.4 2009/03/15 14:24:21 laffer1 Exp $
+ * $FreeBSD: stable/10/sys/dev/aic7xxx/aic_osm_lib.h 172842 2007-10-21 04:11:13Z julian $
*/
/******************************** OS Includes *********************************/
+#if __FreeBSD_version >= 500000
#include <sys/mutex.h>
+#endif
/*************************** Library Symbol Mapping ***************************/
#define AIC_LIB_ENTRY_CONCAT(x, prefix) prefix ## x
@@ -69,6 +72,7 @@
#define AIC_SHUTDOWN_RECOVERY AIC_CONST_ENTRY(_SHUTDOWN_RECOVERY)
/********************************* Byte Order *********************************/
+#if __FreeBSD_version >= 500000
#define aic_htobe16(x) htobe16(x)
#define aic_htobe32(x) htobe32(x)
#define aic_htobe64(x) htobe64(x)
@@ -82,7 +86,22 @@
#define aic_le16toh(x) le16toh(x)
#define aic_le32toh(x) le32toh(x)
#define aic_le64toh(x) le64toh(x)
+#else
+#define aic_htobe16(x) (x)
+#define aic_htobe32(x) (x)
+#define aic_htobe64(x) (x)
+#define aic_htole16(x) (x)
+#define aic_htole32(x) (x)
+#define aic_htole64(x) (x)
+#define aic_be16toh(x) (x)
+#define aic_be32toh(x) (x)
+#define aic_be64toh(x) (x)
+#define aic_le16toh(x) (x)
+#define aic_le32toh(x) (x)
+#define aic_le64toh(x) (x)
+#endif
+
/************************* Forward Declarations *******************************/
typedef device_t aic_dev_softc_t;
typedef union ccb *aic_io_ctx_t;
@@ -107,11 +126,22 @@
}
/****************************** Kernel Threads ********************************/
+#if __FreeBSD_version > 500005
+#if __FreeBSD_version > 800001
#define aic_kthread_create(func, farg, proc_ptr, flags, stackpgs, fmtstr, arg) \
kproc_create(func, farg, proc_ptr, flags, stackpgs, fmtstr, arg)
+#else
+#define aic_kthread_create(func, farg, proc_ptr, flags, stackpgs, fmtstr, arg) \
+ kthread_create(func, farg, proc_ptr, flags, stackpgs, fmtstr, arg)
+#endif
+#else
+#define aic_kthread_create(func, farg, proc_ptr, flags, stackpgs, fmtstr, arg) \
+ kthread_create(func, farg, proc_ptr, fmtstr, arg)
+#endif
/******************************* Bus Space/DMA ********************************/
+#if __FreeBSD_version >= 501102
#define aic_dma_tag_create(aic, parent_tag, alignment, boundary, \
lowaddr, highaddr, filter, filterarg, \
maxsize, nsegments, maxsegsz, flags, \
@@ -121,6 +151,16 @@
maxsize, nsegments, maxsegsz, flags, \
busdma_lock_mutex, &aic->platform_data->mtx, \
dma_tagp)
+#else
+#define aic_dma_tag_create(aic, parent_tag, alignment, boundary, \
+ lowaddr, highaddr, filter, filterarg, \
+ maxsize, nsegments, maxsegsz, flags, \
+ dma_tagp) \
+ bus_dma_tag_create(parent_tag, alignment, boundary, \
+ lowaddr, highaddr, filter, filterarg, \
+ maxsize, nsegments, maxsegsz, flags, \
+ dma_tagp)
+#endif
#define aic_dma_tag_destroy(aic, tag) \
bus_dma_tag_destroy(tag)
@@ -152,7 +192,11 @@
#include AIC_CORE_INCLUDE
/***************************** Timer Facilities *******************************/
+#if __FreeBSD_version >= 500000
#define aic_timer_init(timer) callout_init(timer, /*mpsafe*/1)
+#else
+#define aic_timer_init callout_init
+#endif
#define aic_timer_stop callout_stop
static __inline void aic_timer_reset(aic_timer_t *, u_int,
Modified: trunk/sys/dev/aic7xxx/aicasm/Makefile
===================================================================
--- trunk/sys/dev/aic7xxx/aicasm/Makefile 2018-05-28 00:25:20 UTC (rev 10127)
+++ trunk/sys/dev/aic7xxx/aicasm/Makefile 2018-05-28 00:27:43 UTC (rev 10128)
@@ -1,7 +1,8 @@
+# $MidnightBSD$
#
-# $Id: Makefile,v 1.1.1.4 2012-07-21 15:16:50 laffer1 Exp $
+# $Id: //depot/aic7xxx/freebsd/dev/aic7xxx/aicasm/Makefile#2 $
#
-# $FreeBSD$
+# $FreeBSD: stable/10/sys/dev/aic7xxx/aicasm/Makefile 276486 2014-12-31 23:25:37Z ngie $
PROG= aicasm
@@ -15,7 +16,7 @@
CLEANFILES+= ${GENHDRS} ${YSRCS:R:C/(.*)/\1.output/g}
DPADD= ${LIBL}
LDADD= -ll
-WARNS?= 5
+WARNS?= 0
# Correct path for kernel builds
# Don't rely on the kernel's .depend file
@@ -24,11 +25,11 @@
DEPENDFILE= .depend_aicasm
.endif
-CFLAGS+= -I.
+CFLAGS+= -I${.CURDIR}
.ifdef MAKESRCPATH
CFLAGS+= -I${MAKESRCPATH}
.endif
-NO_MAN=
+MAN=
YFLAGS= -b ${.TARGET:R} ${.TARGET:M*macro*:S/$(.TARGET)/-p mm/} -d
LFLAGS+= ${.TARGET:M*macro*:S/$(.TARGET)/-Pmm/}
@@ -38,4 +39,9 @@
LFLAGS+= -d
.endif
+BINDIR=/usr/bin
+
+build-tools: ${PROG}
+
.include <bsd.prog.mk>
+CFLAGS+= -Wno-missing-prototypes
Modified: trunk/sys/dev/aic7xxx/aicasm/aicasm.c
===================================================================
--- trunk/sys/dev/aic7xxx/aicasm/aicasm.c 2018-05-28 00:25:20 UTC (rev 10127)
+++ trunk/sys/dev/aic7xxx/aicasm/aicasm.c 2018-05-28 00:27:43 UTC (rev 10128)
@@ -1,3 +1,4 @@
+/* $MidnightBSD$ */
/*-
* Aic7xxx SCSI host adapter firmware asssembler
*
@@ -37,9 +38,9 @@
* IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGES.
*
- * $Id: aicasm.c,v 1.3 2012-08-06 01:19:11 laffer1 Exp $
+ * $Id: //depot/aic7xxx/aic7xxx/aicasm/aicasm.c#23 $
*
- * $FreeBSD$
+ * $FreeBSD: stable/10/sys/dev/aic7xxx/aicasm/aicasm.c 300060 2016-05-17 15:18:01Z pfg $
*/
#include <sys/types.h>
#include <sys/mman.h>
@@ -668,7 +669,7 @@
cur_patch = STAILQ_NEXT(cur_patch, links);
} else {
/* Accepted this patch. Advance to the next
- * one and wait for our intruction pointer to
+ * one and wait for our instruction pointer to
* hit this point.
*/
cur_patch = STAILQ_NEXT(cur_patch, links);
Modified: trunk/sys/dev/aic7xxx/aicasm/aicasm.h
===================================================================
--- trunk/sys/dev/aic7xxx/aicasm/aicasm.h 2018-05-28 00:25:20 UTC (rev 10127)
+++ trunk/sys/dev/aic7xxx/aicasm/aicasm.h 2018-05-28 00:27:43 UTC (rev 10128)
@@ -1,3 +1,4 @@
+/* $MidnightBSD$ */
/*-
* Assembler for the sequencer program downloaded to Aic7xxx SCSI host adapters
*
@@ -37,9 +38,9 @@
* IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGES.
*
- * $Id: aicasm.h,v 1.1.1.3 2012-07-21 15:16:50 laffer1 Exp $
+ * $Id: //depot/aic7xxx/aic7xxx/aicasm/aicasm.h#14 $
*
- * $FreeBSD$
+ * $FreeBSD: stable/10/sys/dev/aic7xxx/aicasm/aicasm.h 224046 2011-07-15 00:36:47Z emaste $
*/
#include <sys/queue.h>
Modified: trunk/sys/dev/aic7xxx/aicasm/aicasm_gram.y
===================================================================
--- trunk/sys/dev/aic7xxx/aicasm/aicasm_gram.y 2018-05-28 00:25:20 UTC (rev 10127)
+++ trunk/sys/dev/aic7xxx/aicasm/aicasm_gram.y 2018-05-28 00:27:43 UTC (rev 10128)
@@ -1,3 +1,4 @@
+/* $MidnightBSD$ */
%{
/*-
* Parser for the Aic7xxx SCSI Host adapter sequencer assembler.
@@ -38,9 +39,9 @@
* IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGES.
*
- * $Id: aicasm_gram.y,v 1.1.1.4 2012-07-21 15:16:50 laffer1 Exp $
+ * $Id: //depot/aic7xxx/aic7xxx/aicasm/aicasm_gram.y#29 $
*
- * $FreeBSD$
+ * $FreeBSD: stable/10/sys/dev/aic7xxx/aicasm/aicasm_gram.y 300060 2016-05-17 15:18:01Z pfg $
*/
#include <sys/types.h>
@@ -103,7 +104,6 @@
static int is_download_const(expression_t *immed);
extern int yylex (void);
-extern int yyparse (void);
#define SRAM_SYMNAME "SRAM_BASE"
#define SCB_SYMNAME "SCB_BASE"
@@ -1287,8 +1287,8 @@
;
/*
- * This grammer differs from the one in the aic7xxx
- * reference manual since the grammer listed there is
+ * This grammar differs from the one in the aic7xxx
+ * reference manual since the grammar listed there is
* ambiguous and causes a shift/reduce conflict.
* It also seems more logical as the "immediate"
* argument is listed as the second arg like the
@@ -1754,7 +1754,7 @@
instr = seq_alloc();
f3_instr = &instr->format.format3;
if (address->symbol == NULL) {
- /* 'dot' referrence. Use the current instruction pointer */
+ /* 'dot' reference. Use the current instruction pointer */
addr = instruction_ptr + address->offset;
} else if (address->symbol->type == UNINITIALIZED) {
/* forward reference */
Property changes on: trunk/sys/dev/aic7xxx/aicasm/aicasm_gram.y
___________________________________________________________________
Added: mnbsd:nokeywords
## -0,0 +1 ##
+MidnightBSD=%H
\ No newline at end of property
Modified: trunk/sys/dev/aic7xxx/aicasm/aicasm_insformat.h
===================================================================
--- trunk/sys/dev/aic7xxx/aicasm/aicasm_insformat.h 2018-05-28 00:25:20 UTC (rev 10127)
+++ trunk/sys/dev/aic7xxx/aicasm/aicasm_insformat.h 2018-05-28 00:27:43 UTC (rev 10128)
@@ -1,3 +1,4 @@
+/* $MidnightBSD$ */
/*-
* Instruction formats for the sequencer program downloaded to
* Aic7xxx SCSI host adapters
@@ -37,9 +38,9 @@
* IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGES.
*
- * $Id: aicasm_insformat.h,v 1.1.1.3 2012-07-21 15:16:50 laffer1 Exp $
+ * $Id: //depot/aic7xxx/aic7xxx/aicasm/aicasm_insformat.h#11 $
*
- * $FreeBSD$
+ * $FreeBSD: stable/10/sys/dev/aic7xxx/aicasm/aicasm_insformat.h 139749 2005-01-06 01:43:34Z imp $
*/
struct ins_format1 {
Modified: trunk/sys/dev/aic7xxx/aicasm/aicasm_macro_gram.y
===================================================================
--- trunk/sys/dev/aic7xxx/aicasm/aicasm_macro_gram.y 2018-05-28 00:25:20 UTC (rev 10127)
+++ trunk/sys/dev/aic7xxx/aicasm/aicasm_macro_gram.y 2018-05-28 00:27:43 UTC (rev 10128)
@@ -1,3 +1,4 @@
+/* $MidnightBSD$ */
%{
/*-
* Sub-parser for macro invocation in the Aic7xxx SCSI
@@ -38,9 +39,9 @@
* IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGES.
*
- * $Id: aicasm_macro_gram.y,v 1.1.1.4 2012-07-21 15:16:50 laffer1 Exp $
+ * $Id: //depot/aic7xxx/aic7xxx/aicasm/aicasm_macro_gram.y#5 $
*
- * $FreeBSD$
+ * $FreeBSD: stable/10/sys/dev/aic7xxx/aicasm/aicasm_macro_gram.y 224046 2011-07-15 00:36:47Z emaste $
*/
#include <sys/types.h>
Property changes on: trunk/sys/dev/aic7xxx/aicasm/aicasm_macro_gram.y
___________________________________________________________________
Added: mnbsd:nokeywords
## -0,0 +1 ##
+MidnightBSD=%H
\ No newline at end of property
Modified: trunk/sys/dev/aic7xxx/aicasm/aicasm_macro_scan.l
===================================================================
--- trunk/sys/dev/aic7xxx/aicasm/aicasm_macro_scan.l 2018-05-28 00:25:20 UTC (rev 10127)
+++ trunk/sys/dev/aic7xxx/aicasm/aicasm_macro_scan.l 2018-05-28 00:27:43 UTC (rev 10128)
@@ -1,3 +1,4 @@
+/* $MidnightBSD$ */
%{
/*-
* Sub-Lexical Analyzer for macro invokation in
@@ -38,9 +39,9 @@
* IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGES.
*
- * $Id: aicasm_macro_scan.l,v 1.1.1.3 2012-07-21 15:16:50 laffer1 Exp $
+ * $Id: //depot/aic7xxx/aic7xxx/aicasm/aicasm_macro_scan.l#8 $
*
- * $FreeBSD$
+ * $FreeBSD: stable/10/sys/dev/aic7xxx/aicasm/aicasm_macro_scan.l 228556 2011-12-16 00:04:28Z dim $
*/
#include <sys/types.h>
Property changes on: trunk/sys/dev/aic7xxx/aicasm/aicasm_macro_scan.l
___________________________________________________________________
Added: mnbsd:nokeywords
## -0,0 +1 ##
+MidnightBSD=%H
\ No newline at end of property
Modified: trunk/sys/dev/aic7xxx/aicasm/aicasm_scan.l
===================================================================
--- trunk/sys/dev/aic7xxx/aicasm/aicasm_scan.l 2018-05-28 00:25:20 UTC (rev 10127)
+++ trunk/sys/dev/aic7xxx/aicasm/aicasm_scan.l 2018-05-28 00:27:43 UTC (rev 10128)
@@ -1,3 +1,4 @@
+/* $MidnightBSD$ */
%{
/*-
* Lexical Analyzer for the Aic7xxx SCSI Host adapter sequencer assembler.
@@ -38,9 +39,9 @@
* IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGES.
*
- * $Id: aicasm_scan.l,v 1.1.1.3 2012-07-21 15:16:50 laffer1 Exp $
+ * $Id: //depot/aic7xxx/aic7xxx/aicasm/aicasm_scan.l#19 $
*
- * $FreeBSD$
+ * $FreeBSD: stable/10/sys/dev/aic7xxx/aicasm/aicasm_scan.l 228556 2011-12-16 00:04:28Z dim $
*/
#include <sys/types.h>
Property changes on: trunk/sys/dev/aic7xxx/aicasm/aicasm_scan.l
___________________________________________________________________
Added: mnbsd:nokeywords
## -0,0 +1 ##
+MidnightBSD=%H
\ No newline at end of property
Modified: trunk/sys/dev/aic7xxx/aicasm/aicasm_symbol.c
===================================================================
--- trunk/sys/dev/aic7xxx/aicasm/aicasm_symbol.c 2018-05-28 00:25:20 UTC (rev 10127)
+++ trunk/sys/dev/aic7xxx/aicasm/aicasm_symbol.c 2018-05-28 00:27:43 UTC (rev 10128)
@@ -1,3 +1,4 @@
+/* $MidnightBSD$ */
/*-
* Aic7xxx SCSI host adapter firmware asssembler symbol table implementation
*
@@ -37,14 +38,14 @@
* IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGES.
*
- * $Id: aicasm_symbol.c,v 1.3 2012-08-06 01:19:11 laffer1 Exp $
+ * $Id: //depot/aic7xxx/aic7xxx/aicasm/aicasm_symbol.c#24 $
*
- * $FreeBSD$
+ * $FreeBSD: stable/10/sys/dev/aic7xxx/aicasm/aicasm_symbol.c 233479 2012-03-25 21:54:36Z rmh $
*/
#include <sys/types.h>
#include <sys/param.h>
-#ifdef BSD
+#if defined(BSD) && !defined(__GNU__)
#include <db.h>
#else
#include <db_185.h>
Modified: trunk/sys/dev/aic7xxx/aicasm/aicasm_symbol.h
===================================================================
--- trunk/sys/dev/aic7xxx/aicasm/aicasm_symbol.h 2018-05-28 00:25:20 UTC (rev 10127)
+++ trunk/sys/dev/aic7xxx/aicasm/aicasm_symbol.h 2018-05-28 00:27:43 UTC (rev 10128)
@@ -1,3 +1,4 @@
+/* $MidnightBSD$ */
/*-
* Aic7xxx SCSI host adapter firmware asssembler symbol table definitions
*
@@ -37,9 +38,9 @@
* IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGES.
*
- * $Id: aicasm_symbol.h,v 1.1.1.3 2012-07-21 15:16:50 laffer1 Exp $
+ * $Id: //depot/aic7xxx/aic7xxx/aicasm/aicasm_symbol.h#17 $
*
- * $FreeBSD$
+ * $FreeBSD: stable/10/sys/dev/aic7xxx/aicasm/aicasm_symbol.h 224046 2011-07-15 00:36:47Z emaste $
*/
#include <sys/queue.h>
Modified: trunk/sys/dev/alc/if_alc.c
===================================================================
--- trunk/sys/dev/alc/if_alc.c 2018-05-28 00:25:20 UTC (rev 10127)
+++ trunk/sys/dev/alc/if_alc.c 2018-05-28 00:27:43 UTC (rev 10128)
@@ -1,3 +1,4 @@
+/* $MidnightBSD$ */
/*-
* Copyright (c) 2009, Pyun YongHyeon <yongari at FreeBSD.org>
* All rights reserved.
@@ -28,7 +29,7 @@
/* Driver for Atheros AR813x/AR815x PCIe Ethernet. */
#include <sys/cdefs.h>
-__MBSDID("$MidnightBSD$");
+__FBSDID("$FreeBSD: stable/10/sys/dev/alc/if_alc.c 314019 2017-02-21 03:27:59Z sephe $");
#include <sys/param.h>
#include <sys/systm.h>
@@ -110,17 +111,35 @@
"Atheros AR8152 v1.1 PCIe Fast Ethernet" },
{ VENDORID_ATHEROS, DEVICEID_ATHEROS_AR8152_B2, 6 * 1024,
"Atheros AR8152 v2.0 PCIe Fast Ethernet" },
+ { VENDORID_ATHEROS, DEVICEID_ATHEROS_AR8161, 9 * 1024,
+ "Atheros AR8161 PCIe Gigabit Ethernet" },
+ { VENDORID_ATHEROS, DEVICEID_ATHEROS_AR8162, 9 * 1024,
+ "Atheros AR8162 PCIe Fast Ethernet" },
+ { VENDORID_ATHEROS, DEVICEID_ATHEROS_AR8171, 9 * 1024,
+ "Atheros AR8171 PCIe Gigabit Ethernet" },
+ { VENDORID_ATHEROS, DEVICEID_ATHEROS_AR8172, 9 * 1024,
+ "Atheros AR8172 PCIe Fast Ethernet" },
+ { VENDORID_ATHEROS, DEVICEID_ATHEROS_E2200, 9 * 1024,
+ "Killer E2200 Gigabit Ethernet" },
+ { VENDORID_ATHEROS, DEVICEID_ATHEROS_E2400, 9 * 1024,
+ "Killer E2400 Gigabit Ethernet" },
+ { VENDORID_ATHEROS, DEVICEID_ATHEROS_E2500, 9 * 1024,
+ "Killer E2500 Gigabit Ethernet" },
{ 0, 0, 0, NULL}
};
-static void alc_aspm(struct alc_softc *, int);
+static void alc_aspm(struct alc_softc *, int, int);
+static void alc_aspm_813x(struct alc_softc *, int);
+static void alc_aspm_816x(struct alc_softc *, int);
static int alc_attach(device_t);
static int alc_check_boundary(struct alc_softc *);
+static void alc_config_msi(struct alc_softc *);
static int alc_detach(device_t);
static void alc_disable_l0s_l1(struct alc_softc *);
static int alc_dma_alloc(struct alc_softc *);
static void alc_dma_free(struct alc_softc *);
static void alc_dmamap_cb(void *, bus_dma_segment_t *, int, int);
+static void alc_dsp_fixup(struct alc_softc *, int);
static int alc_encap(struct alc_softc *, struct mbuf **);
static struct alc_ident *
alc_find_ident(device_t);
@@ -129,6 +148,9 @@
alc_fixup_rx(struct ifnet *, struct mbuf *);
#endif
static void alc_get_macaddr(struct alc_softc *);
+static void alc_get_macaddr_813x(struct alc_softc *);
+static void alc_get_macaddr_816x(struct alc_softc *);
+static void alc_get_macaddr_par(struct alc_softc *);
static void alc_init(void *);
static void alc_init_cmb(struct alc_softc *);
static void alc_init_locked(struct alc_softc *);
@@ -140,14 +162,26 @@
static int alc_intr(void *);
static int alc_ioctl(struct ifnet *, u_long, caddr_t);
static void alc_mac_config(struct alc_softc *);
+static uint32_t alc_mii_readreg_813x(struct alc_softc *, int, int);
+static uint32_t alc_mii_readreg_816x(struct alc_softc *, int, int);
+static uint32_t alc_mii_writereg_813x(struct alc_softc *, int, int, int);
+static uint32_t alc_mii_writereg_816x(struct alc_softc *, int, int, int);
static int alc_miibus_readreg(device_t, int, int);
static void alc_miibus_statchg(device_t);
static int alc_miibus_writereg(device_t, int, int, int);
+static uint32_t alc_miidbg_readreg(struct alc_softc *, int);
+static uint32_t alc_miidbg_writereg(struct alc_softc *, int, int);
+static uint32_t alc_miiext_readreg(struct alc_softc *, int, int);
+static uint32_t alc_miiext_writereg(struct alc_softc *, int, int, int);
static int alc_mediachange(struct ifnet *);
+static int alc_mediachange_locked(struct alc_softc *);
static void alc_mediastatus(struct ifnet *, struct ifmediareq *);
static int alc_newbuf(struct alc_softc *, struct alc_rxdesc *);
+static void alc_osc_reset(struct alc_softc *);
static void alc_phy_down(struct alc_softc *);
static void alc_phy_reset(struct alc_softc *);
+static void alc_phy_reset_813x(struct alc_softc *);
+static void alc_phy_reset_816x(struct alc_softc *);
static int alc_probe(device_t);
static void alc_reset(struct alc_softc *);
static int alc_resume(device_t);
@@ -157,6 +191,8 @@
static void alc_rxvlan(struct alc_softc *);
static void alc_setlinkspeed(struct alc_softc *);
static void alc_setwol(struct alc_softc *);
+static void alc_setwol_813x(struct alc_softc *);
+static void alc_setwol_816x(struct alc_softc *);
static int alc_shutdown(device_t);
static void alc_start(struct ifnet *);
static void alc_start_locked(struct ifnet *);
@@ -223,17 +259,28 @@
{ -1, 0, 0 }
};
-static uint32_t alc_dma_burst[] = { 128, 256, 512, 1024, 2048, 4096, 0 };
+static uint32_t alc_dma_burst[] = { 128, 256, 512, 1024, 2048, 4096, 0, 0 };
static int
alc_miibus_readreg(device_t dev, int phy, int reg)
{
struct alc_softc *sc;
+ int v;
+
+ sc = device_get_softc(dev);
+ if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0)
+ v = alc_mii_readreg_816x(sc, phy, reg);
+ else
+ v = alc_mii_readreg_813x(sc, phy, reg);
+ return (v);
+}
+
+static uint32_t
+alc_mii_readreg_813x(struct alc_softc *sc, int phy, int reg)
+{
uint32_t v;
int i;
- sc = device_get_softc(dev);
-
/*
* For AR8132 fast ethernet controller, do not report 1000baseT
* capability to mii(4). Even though AR8132 uses the same
@@ -261,15 +308,53 @@
return ((v & MDIO_DATA_MASK) >> MDIO_DATA_SHIFT);
}
+static uint32_t
+alc_mii_readreg_816x(struct alc_softc *sc, int phy, int reg)
+{
+ uint32_t clk, v;
+ int i;
+
+ if ((sc->alc_flags & ALC_FLAG_LINK) != 0)
+ clk = MDIO_CLK_25_128;
+ else
+ clk = MDIO_CLK_25_4;
+ CSR_WRITE_4(sc, ALC_MDIO, MDIO_OP_EXECUTE | MDIO_OP_READ |
+ MDIO_SUP_PREAMBLE | clk | MDIO_REG_ADDR(reg));
+ for (i = ALC_PHY_TIMEOUT; i > 0; i--) {
+ DELAY(5);
+ v = CSR_READ_4(sc, ALC_MDIO);
+ if ((v & MDIO_OP_BUSY) == 0)
+ break;
+ }
+
+ if (i == 0) {
+ device_printf(sc->alc_dev, "phy read timeout : %d\n", reg);
+ return (0);
+ }
+
+ return ((v & MDIO_DATA_MASK) >> MDIO_DATA_SHIFT);
+}
+
static int
alc_miibus_writereg(device_t dev, int phy, int reg, int val)
{
struct alc_softc *sc;
+ int v;
+
+ sc = device_get_softc(dev);
+ if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0)
+ v = alc_mii_writereg_816x(sc, phy, reg, val);
+ else
+ v = alc_mii_writereg_813x(sc, phy, reg, val);
+ return (v);
+}
+
+static uint32_t
+alc_mii_writereg_813x(struct alc_softc *sc, int phy, int reg, int val)
+{
uint32_t v;
int i;
- sc = device_get_softc(dev);
-
CSR_WRITE_4(sc, ALC_MDIO, MDIO_OP_EXECUTE | MDIO_OP_WRITE |
(val & MDIO_DATA_MASK) << MDIO_DATA_SHIFT |
MDIO_SUP_PREAMBLE | MDIO_CLK_25_4 | MDIO_REG_ADDR(reg));
@@ -286,6 +371,32 @@
return (0);
}
+static uint32_t
+alc_mii_writereg_816x(struct alc_softc *sc, int phy, int reg, int val)
+{
+ uint32_t clk, v;
+ int i;
+
+ if ((sc->alc_flags & ALC_FLAG_LINK) != 0)
+ clk = MDIO_CLK_25_128;
+ else
+ clk = MDIO_CLK_25_4;
+ CSR_WRITE_4(sc, ALC_MDIO, MDIO_OP_EXECUTE | MDIO_OP_WRITE |
+ ((val & MDIO_DATA_MASK) << MDIO_DATA_SHIFT) | MDIO_REG_ADDR(reg) |
+ MDIO_SUP_PREAMBLE | clk);
+ for (i = ALC_PHY_TIMEOUT; i > 0; i--) {
+ DELAY(5);
+ v = CSR_READ_4(sc, ALC_MDIO);
+ if ((v & MDIO_OP_BUSY) == 0)
+ break;
+ }
+
+ if (i == 0)
+ device_printf(sc->alc_dev, "phy write timeout : %d\n", reg);
+
+ return (0);
+}
+
static void
alc_miibus_statchg(device_t dev)
{
@@ -318,7 +429,6 @@
break;
}
}
- alc_stop_queue(sc);
/* Stop Rx/Tx MACs. */
alc_stop_mac(sc);
@@ -330,11 +440,163 @@
reg = CSR_READ_4(sc, ALC_MAC_CFG);
reg |= MAC_CFG_TX_ENB | MAC_CFG_RX_ENB;
CSR_WRITE_4(sc, ALC_MAC_CFG, reg);
- alc_aspm(sc, IFM_SUBTYPE(mii->mii_media_active));
}
+ alc_aspm(sc, 0, IFM_SUBTYPE(mii->mii_media_active));
+ alc_dsp_fixup(sc, IFM_SUBTYPE(mii->mii_media_active));
}
+static uint32_t
+alc_miidbg_readreg(struct alc_softc *sc, int reg)
+{
+
+ alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, ALC_MII_DBG_ADDR,
+ reg);
+ return (alc_miibus_readreg(sc->alc_dev, sc->alc_phyaddr,
+ ALC_MII_DBG_DATA));
+}
+
+static uint32_t
+alc_miidbg_writereg(struct alc_softc *sc, int reg, int val)
+{
+
+ alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, ALC_MII_DBG_ADDR,
+ reg);
+ return (alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr,
+ ALC_MII_DBG_DATA, val));
+}
+
+static uint32_t
+alc_miiext_readreg(struct alc_softc *sc, int devaddr, int reg)
+{
+ uint32_t clk, v;
+ int i;
+
+ CSR_WRITE_4(sc, ALC_EXT_MDIO, EXT_MDIO_REG(reg) |
+ EXT_MDIO_DEVADDR(devaddr));
+ if ((sc->alc_flags & ALC_FLAG_LINK) != 0)
+ clk = MDIO_CLK_25_128;
+ else
+ clk = MDIO_CLK_25_4;
+ CSR_WRITE_4(sc, ALC_MDIO, MDIO_OP_EXECUTE | MDIO_OP_READ |
+ MDIO_SUP_PREAMBLE | clk | MDIO_MODE_EXT);
+ for (i = ALC_PHY_TIMEOUT; i > 0; i--) {
+ DELAY(5);
+ v = CSR_READ_4(sc, ALC_MDIO);
+ if ((v & MDIO_OP_BUSY) == 0)
+ break;
+ }
+
+ if (i == 0) {
+ device_printf(sc->alc_dev, "phy ext read timeout : %d, %d\n",
+ devaddr, reg);
+ return (0);
+ }
+
+ return ((v & MDIO_DATA_MASK) >> MDIO_DATA_SHIFT);
+}
+
+static uint32_t
+alc_miiext_writereg(struct alc_softc *sc, int devaddr, int reg, int val)
+{
+ uint32_t clk, v;
+ int i;
+
+ CSR_WRITE_4(sc, ALC_EXT_MDIO, EXT_MDIO_REG(reg) |
+ EXT_MDIO_DEVADDR(devaddr));
+ if ((sc->alc_flags & ALC_FLAG_LINK) != 0)
+ clk = MDIO_CLK_25_128;
+ else
+ clk = MDIO_CLK_25_4;
+ CSR_WRITE_4(sc, ALC_MDIO, MDIO_OP_EXECUTE | MDIO_OP_WRITE |
+ ((val & MDIO_DATA_MASK) << MDIO_DATA_SHIFT) |
+ MDIO_SUP_PREAMBLE | clk | MDIO_MODE_EXT);
+ for (i = ALC_PHY_TIMEOUT; i > 0; i--) {
+ DELAY(5);
+ v = CSR_READ_4(sc, ALC_MDIO);
+ if ((v & MDIO_OP_BUSY) == 0)
+ break;
+ }
+
+ if (i == 0)
+ device_printf(sc->alc_dev, "phy ext write timeout : %d, %d\n",
+ devaddr, reg);
+
+ return (0);
+}
+
static void
+alc_dsp_fixup(struct alc_softc *sc, int media)
+{
+ uint16_t agc, len, val;
+
+ if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0)
+ return;
+ if (AR816X_REV(sc->alc_rev) >= AR816X_REV_C0)
+ return;
+
+ /*
+ * Vendor PHY magic.
+ * 1000BT/AZ, wrong cable length
+ */
+ if ((sc->alc_flags & ALC_FLAG_LINK) != 0) {
+ len = alc_miiext_readreg(sc, MII_EXT_PCS, MII_EXT_CLDCTL6);
+ len = (len >> EXT_CLDCTL6_CAB_LEN_SHIFT) &
+ EXT_CLDCTL6_CAB_LEN_MASK;
+ agc = alc_miidbg_readreg(sc, MII_DBG_AGC);
+ agc = (agc >> DBG_AGC_2_VGA_SHIFT) & DBG_AGC_2_VGA_MASK;
+ if ((media == IFM_1000_T && len > EXT_CLDCTL6_CAB_LEN_SHORT1G &&
+ agc > DBG_AGC_LONG1G_LIMT) ||
+ (media == IFM_100_TX && len > DBG_AGC_LONG100M_LIMT &&
+ agc > DBG_AGC_LONG1G_LIMT)) {
+ alc_miidbg_writereg(sc, MII_DBG_AZ_ANADECT,
+ DBG_AZ_ANADECT_LONG);
+ val = alc_miiext_readreg(sc, MII_EXT_ANEG,
+ MII_EXT_ANEG_AFE);
+ val |= ANEG_AFEE_10BT_100M_TH;
+ alc_miiext_writereg(sc, MII_EXT_ANEG, MII_EXT_ANEG_AFE,
+ val);
+ } else {
+ alc_miidbg_writereg(sc, MII_DBG_AZ_ANADECT,
+ DBG_AZ_ANADECT_DEFAULT);
+ val = alc_miiext_readreg(sc, MII_EXT_ANEG,
+ MII_EXT_ANEG_AFE);
+ val &= ~ANEG_AFEE_10BT_100M_TH;
+ alc_miiext_writereg(sc, MII_EXT_ANEG, MII_EXT_ANEG_AFE,
+ val);
+ }
+ if ((sc->alc_flags & ALC_FLAG_LINK_WAR) != 0 &&
+ AR816X_REV(sc->alc_rev) == AR816X_REV_B0) {
+ if (media == IFM_1000_T) {
+ /*
+ * Giga link threshold, raise the tolerance of
+ * noise 50%.
+ */
+ val = alc_miidbg_readreg(sc, MII_DBG_MSE20DB);
+ val &= ~DBG_MSE20DB_TH_MASK;
+ val |= (DBG_MSE20DB_TH_HI <<
+ DBG_MSE20DB_TH_SHIFT);
+ alc_miidbg_writereg(sc, MII_DBG_MSE20DB, val);
+ } else if (media == IFM_100_TX)
+ alc_miidbg_writereg(sc, MII_DBG_MSE16DB,
+ DBG_MSE16DB_UP);
+ }
+ } else {
+ val = alc_miiext_readreg(sc, MII_EXT_ANEG, MII_EXT_ANEG_AFE);
+ val &= ~ANEG_AFEE_10BT_100M_TH;
+ alc_miiext_writereg(sc, MII_EXT_ANEG, MII_EXT_ANEG_AFE, val);
+ if ((sc->alc_flags & ALC_FLAG_LINK_WAR) != 0 &&
+ AR816X_REV(sc->alc_rev) == AR816X_REV_B0) {
+ alc_miidbg_writereg(sc, MII_DBG_MSE16DB,
+ DBG_MSE16DB_DOWN);
+ val = alc_miidbg_readreg(sc, MII_DBG_MSE20DB);
+ val &= ~DBG_MSE20DB_TH_MASK;
+ val |= (DBG_MSE20DB_TH_DEFAULT << DBG_MSE20DB_TH_SHIFT);
+ alc_miidbg_writereg(sc, MII_DBG_MSE20DB, val);
+ }
+ }
+}
+
+static void
alc_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr)
{
struct alc_softc *sc;
@@ -358,17 +620,29 @@
alc_mediachange(struct ifnet *ifp)
{
struct alc_softc *sc;
+ int error;
+
+ sc = ifp->if_softc;
+ ALC_LOCK(sc);
+ error = alc_mediachange_locked(sc);
+ ALC_UNLOCK(sc);
+
+ return (error);
+}
+
+static int
+alc_mediachange_locked(struct alc_softc *sc)
+{
struct mii_data *mii;
struct mii_softc *miisc;
int error;
- sc = ifp->if_softc;
- ALC_LOCK(sc);
+ ALC_LOCK_ASSERT(sc);
+
mii = device_get_softc(sc->alc_miibus);
LIST_FOREACH(miisc, &mii->mii_phys, mii_list)
PHY_RESET(miisc);
error = mii_mediachg(mii);
- ALC_UNLOCK(sc);
return (error);
}
@@ -406,7 +680,17 @@
static void
alc_get_macaddr(struct alc_softc *sc)
{
- uint32_t ea[2], opt;
+
+ if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0)
+ alc_get_macaddr_816x(sc);
+ else
+ alc_get_macaddr_813x(sc);
+}
+
+static void
+alc_get_macaddr_813x(struct alc_softc *sc)
+{
+ uint32_t opt;
uint16_t val;
int eeprom, i;
@@ -501,6 +785,73 @@
}
}
+ alc_get_macaddr_par(sc);
+}
+
+static void
+alc_get_macaddr_816x(struct alc_softc *sc)
+{
+ uint32_t reg;
+ int i, reloaded;
+
+ reloaded = 0;
+ /* Try to reload station address via TWSI. */
+ for (i = 100; i > 0; i--) {
+ reg = CSR_READ_4(sc, ALC_SLD);
+ if ((reg & (SLD_PROGRESS | SLD_START)) == 0)
+ break;
+ DELAY(1000);
+ }
+ if (i != 0) {
+ CSR_WRITE_4(sc, ALC_SLD, reg | SLD_START);
+ for (i = 100; i > 0; i--) {
+ DELAY(1000);
+ reg = CSR_READ_4(sc, ALC_SLD);
+ if ((reg & SLD_START) == 0)
+ break;
+ }
+ if (i != 0)
+ reloaded++;
+ else if (bootverbose)
+ device_printf(sc->alc_dev,
+ "reloading station address via TWSI timed out!\n");
+ }
+
+ /* Try to reload station address from EEPROM or FLASH. */
+ if (reloaded == 0) {
+ reg = CSR_READ_4(sc, ALC_EEPROM_LD);
+ if ((reg & (EEPROM_LD_EEPROM_EXIST |
+ EEPROM_LD_FLASH_EXIST)) != 0) {
+ for (i = 100; i > 0; i--) {
+ reg = CSR_READ_4(sc, ALC_EEPROM_LD);
+ if ((reg & (EEPROM_LD_PROGRESS |
+ EEPROM_LD_START)) == 0)
+ break;
+ DELAY(1000);
+ }
+ if (i != 0) {
+ CSR_WRITE_4(sc, ALC_EEPROM_LD, reg |
+ EEPROM_LD_START);
+ for (i = 100; i > 0; i--) {
+ DELAY(1000);
+ reg = CSR_READ_4(sc, ALC_EEPROM_LD);
+ if ((reg & EEPROM_LD_START) == 0)
+ break;
+ }
+ } else if (bootverbose)
+ device_printf(sc->alc_dev,
+ "reloading EEPROM/FLASH timed out!\n");
+ }
+ }
+
+ alc_get_macaddr_par(sc);
+}
+
+static void
+alc_get_macaddr_par(struct alc_softc *sc)
+{
+ uint32_t ea[2];
+
ea[0] = CSR_READ_4(sc, ALC_PAR0);
ea[1] = CSR_READ_4(sc, ALC_PAR1);
sc->alc_eaddr[0] = (ea[1] >> 8) & 0xFF;
@@ -516,19 +867,31 @@
{
uint32_t pmcfg;
- /* Another magic from vendor. */
- pmcfg = CSR_READ_4(sc, ALC_PM_CFG);
- pmcfg &= ~(PM_CFG_L1_ENTRY_TIMER_MASK | PM_CFG_CLK_SWH_L1 |
- PM_CFG_ASPM_L0S_ENB | PM_CFG_ASPM_L1_ENB | PM_CFG_MAC_ASPM_CHK |
- PM_CFG_SERDES_PD_EX_L1);
- pmcfg |= PM_CFG_SERDES_BUDS_RX_L1_ENB | PM_CFG_SERDES_PLL_L1_ENB |
- PM_CFG_SERDES_L1_ENB;
- CSR_WRITE_4(sc, ALC_PM_CFG, pmcfg);
+ if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) == 0) {
+ /* Another magic from vendor. */
+ pmcfg = CSR_READ_4(sc, ALC_PM_CFG);
+ pmcfg &= ~(PM_CFG_L1_ENTRY_TIMER_MASK | PM_CFG_CLK_SWH_L1 |
+ PM_CFG_ASPM_L0S_ENB | PM_CFG_ASPM_L1_ENB |
+ PM_CFG_MAC_ASPM_CHK | PM_CFG_SERDES_PD_EX_L1);
+ pmcfg |= PM_CFG_SERDES_BUDS_RX_L1_ENB |
+ PM_CFG_SERDES_PLL_L1_ENB | PM_CFG_SERDES_L1_ENB;
+ CSR_WRITE_4(sc, ALC_PM_CFG, pmcfg);
+ }
}
static void
alc_phy_reset(struct alc_softc *sc)
{
+
+ if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0)
+ alc_phy_reset_816x(sc);
+ else
+ alc_phy_reset_813x(sc);
+}
+
+static void
+alc_phy_reset_813x(struct alc_softc *sc)
+{
uint16_t data;
/* Reset magic from Linux. */
@@ -641,12 +1004,103 @@
}
static void
+alc_phy_reset_816x(struct alc_softc *sc)
+{
+ uint32_t val;
+
+ val = CSR_READ_4(sc, ALC_GPHY_CFG);
+ val &= ~(GPHY_CFG_EXT_RESET | GPHY_CFG_LED_MODE |
+ GPHY_CFG_GATE_25M_ENB | GPHY_CFG_PHY_IDDQ | GPHY_CFG_PHY_PLL_ON |
+ GPHY_CFG_PWDOWN_HW | GPHY_CFG_100AB_ENB);
+ val |= GPHY_CFG_SEL_ANA_RESET;
+#ifdef notyet
+ val |= GPHY_CFG_HIB_PULSE | GPHY_CFG_HIB_EN | GPHY_CFG_SEL_ANA_RESET;
+#else
+ /* Disable PHY hibernation. */
+ val &= ~(GPHY_CFG_HIB_PULSE | GPHY_CFG_HIB_EN);
+#endif
+ CSR_WRITE_4(sc, ALC_GPHY_CFG, val);
+ DELAY(10);
+ CSR_WRITE_4(sc, ALC_GPHY_CFG, val | GPHY_CFG_EXT_RESET);
+ DELAY(800);
+
+ /* Vendor PHY magic. */
+#ifdef notyet
+ alc_miidbg_writereg(sc, MII_DBG_LEGCYPS, DBG_LEGCYPS_DEFAULT);
+ alc_miidbg_writereg(sc, MII_DBG_SYSMODCTL, DBG_SYSMODCTL_DEFAULT);
+ alc_miiext_writereg(sc, MII_EXT_PCS, MII_EXT_VDRVBIAS,
+ EXT_VDRVBIAS_DEFAULT);
+#else
+ /* Disable PHY hibernation. */
+ alc_miidbg_writereg(sc, MII_DBG_LEGCYPS,
+ DBG_LEGCYPS_DEFAULT & ~DBG_LEGCYPS_ENB);
+ alc_miidbg_writereg(sc, MII_DBG_HIBNEG,
+ DBG_HIBNEG_DEFAULT & ~(DBG_HIBNEG_PSHIB_EN | DBG_HIBNEG_HIB_PULSE));
+ alc_miidbg_writereg(sc, MII_DBG_GREENCFG, DBG_GREENCFG_DEFAULT);
+#endif
+
+ /* XXX Disable EEE. */
+ val = CSR_READ_4(sc, ALC_LPI_CTL);
+ val &= ~LPI_CTL_ENB;
+ CSR_WRITE_4(sc, ALC_LPI_CTL, val);
+ alc_miiext_writereg(sc, MII_EXT_ANEG, MII_EXT_ANEG_LOCAL_EEEADV, 0);
+
+ /* PHY power saving. */
+ alc_miidbg_writereg(sc, MII_DBG_TST10BTCFG, DBG_TST10BTCFG_DEFAULT);
+ alc_miidbg_writereg(sc, MII_DBG_SRDSYSMOD, DBG_SRDSYSMOD_DEFAULT);
+ alc_miidbg_writereg(sc, MII_DBG_TST100BTCFG, DBG_TST100BTCFG_DEFAULT);
+ alc_miidbg_writereg(sc, MII_DBG_ANACTL, DBG_ANACTL_DEFAULT);
+ val = alc_miidbg_readreg(sc, MII_DBG_GREENCFG2);
+ val &= ~DBG_GREENCFG2_GATE_DFSE_EN;
+ alc_miidbg_writereg(sc, MII_DBG_GREENCFG2, val);
+
+ /* RTL8139C, 120m issue. */
+ alc_miiext_writereg(sc, MII_EXT_ANEG, MII_EXT_ANEG_NLP78,
+ ANEG_NLP78_120M_DEFAULT);
+ alc_miiext_writereg(sc, MII_EXT_ANEG, MII_EXT_ANEG_S3DIG10,
+ ANEG_S3DIG10_DEFAULT);
+
+ if ((sc->alc_flags & ALC_FLAG_LINK_WAR) != 0) {
+ /* Turn off half amplitude. */
+ val = alc_miiext_readreg(sc, MII_EXT_PCS, MII_EXT_CLDCTL3);
+ val |= EXT_CLDCTL3_BP_CABLE1TH_DET_GT;
+ alc_miiext_writereg(sc, MII_EXT_PCS, MII_EXT_CLDCTL3, val);
+ /* Turn off Green feature. */
+ val = alc_miidbg_readreg(sc, MII_DBG_GREENCFG2);
+ val |= DBG_GREENCFG2_BP_GREEN;
+ alc_miidbg_writereg(sc, MII_DBG_GREENCFG2, val);
+ /* Turn off half bias. */
+ val = alc_miiext_readreg(sc, MII_EXT_PCS, MII_EXT_CLDCTL5);
+ val |= EXT_CLDCTL5_BP_VD_HLFBIAS;
+ alc_miiext_writereg(sc, MII_EXT_PCS, MII_EXT_CLDCTL5, val);
+ }
+}
+
+static void
alc_phy_down(struct alc_softc *sc)
{
+ uint32_t gphy;
switch (sc->alc_ident->deviceid) {
+ case DEVICEID_ATHEROS_AR8161:
+ case DEVICEID_ATHEROS_E2200:
+ case DEVICEID_ATHEROS_E2400:
+ case DEVICEID_ATHEROS_E2500:
+ case DEVICEID_ATHEROS_AR8162:
+ case DEVICEID_ATHEROS_AR8171:
+ case DEVICEID_ATHEROS_AR8172:
+ gphy = CSR_READ_4(sc, ALC_GPHY_CFG);
+ gphy &= ~(GPHY_CFG_EXT_RESET | GPHY_CFG_LED_MODE |
+ GPHY_CFG_100AB_ENB | GPHY_CFG_PHY_PLL_ON);
+ gphy |= GPHY_CFG_HIB_EN | GPHY_CFG_HIB_PULSE |
+ GPHY_CFG_SEL_ANA_RESET;
+ gphy |= GPHY_CFG_PHY_IDDQ | GPHY_CFG_PWDOWN_HW;
+ CSR_WRITE_4(sc, ALC_GPHY_CFG, gphy);
+ break;
case DEVICEID_ATHEROS_AR8151:
case DEVICEID_ATHEROS_AR8151_V2:
+ case DEVICEID_ATHEROS_AR8152_B:
+ case DEVICEID_ATHEROS_AR8152_B2:
/*
* GPHY power down caused more problems on AR8151 v2.0.
* When driver is reloaded after GPHY power down,
@@ -672,12 +1126,23 @@
}
static void
-alc_aspm(struct alc_softc *sc, int media)
+alc_aspm(struct alc_softc *sc, int init, int media)
{
+
+ if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0)
+ alc_aspm_816x(sc, init);
+ else
+ alc_aspm_813x(sc, media);
+}
+
+static void
+alc_aspm_813x(struct alc_softc *sc, int media)
+{
uint32_t pmcfg;
uint16_t linkcfg;
- ALC_LOCK_ASSERT(sc);
+ if ((sc->alc_flags & ALC_FLAG_LINK) == 0)
+ return;
pmcfg = CSR_READ_4(sc, ALC_PM_CFG);
if ((sc->alc_flags & (ALC_FLAG_APS | ALC_FLAG_PCIE)) ==
@@ -694,10 +1159,10 @@
if ((sc->alc_flags & ALC_FLAG_APS) != 0) {
/* Disable extended sync except AR8152 B v1.0 */
- linkcfg &= ~0x80;
+ linkcfg &= ~PCIEM_LINK_CTL_EXTENDED_SYNC;
if (sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8152_B &&
sc->alc_rev == ATHEROS_AR8152_B_V10)
- linkcfg |= 0x80;
+ linkcfg |= PCIEM_LINK_CTL_EXTENDED_SYNC;
CSR_WRITE_2(sc, sc->alc_expcap + PCIER_LINK_CTL,
linkcfg);
pmcfg &= ~(PM_CFG_EN_BUFS_RX_L0S | PM_CFG_SA_DLY_ENB |
@@ -758,64 +1223,54 @@
CSR_WRITE_4(sc, ALC_PM_CFG, pmcfg);
}
-static int
-alc_attach(device_t dev)
+static void
+alc_aspm_816x(struct alc_softc *sc, int init)
{
- struct alc_softc *sc;
- struct ifnet *ifp;
- char *aspm_state[] = { "L0s/L1", "L0s", "L1", "L0s/L1" };
- uint16_t burst;
- int base, error, i, msic, msixc, state;
- uint32_t cap, ctl, val;
+ uint32_t pmcfg;
- error = 0;
- sc = device_get_softc(dev);
- sc->alc_dev = dev;
+ pmcfg = CSR_READ_4(sc, ALC_PM_CFG);
+ pmcfg &= ~PM_CFG_L1_ENTRY_TIMER_816X_MASK;
+ pmcfg |= PM_CFG_L1_ENTRY_TIMER_816X_DEFAULT;
+ pmcfg &= ~PM_CFG_PM_REQ_TIMER_MASK;
+ pmcfg |= PM_CFG_PM_REQ_TIMER_816X_DEFAULT;
+ pmcfg &= ~PM_CFG_LCKDET_TIMER_MASK;
+ pmcfg |= PM_CFG_LCKDET_TIMER_DEFAULT;
+ pmcfg |= PM_CFG_SERDES_PD_EX_L1 | PM_CFG_CLK_SWH_L1 | PM_CFG_PCIE_RECV;
+ pmcfg &= ~(PM_CFG_RX_L1_AFTER_L0S | PM_CFG_TX_L1_AFTER_L0S |
+ PM_CFG_ASPM_L1_ENB | PM_CFG_ASPM_L0S_ENB |
+ PM_CFG_SERDES_L1_ENB | PM_CFG_SERDES_PLL_L1_ENB |
+ PM_CFG_SERDES_BUDS_RX_L1_ENB | PM_CFG_SA_DLY_ENB |
+ PM_CFG_MAC_ASPM_CHK | PM_CFG_HOTRST);
+ if (AR816X_REV(sc->alc_rev) <= AR816X_REV_A1 &&
+ (sc->alc_rev & 0x01) != 0)
+ pmcfg |= PM_CFG_SERDES_L1_ENB | PM_CFG_SERDES_PLL_L1_ENB;
+ if ((sc->alc_flags & ALC_FLAG_LINK) != 0) {
+ /* Link up, enable both L0s, L1s. */
+ pmcfg |= PM_CFG_ASPM_L0S_ENB | PM_CFG_ASPM_L1_ENB |
+ PM_CFG_MAC_ASPM_CHK;
+ } else {
+ if (init != 0)
+ pmcfg |= PM_CFG_ASPM_L0S_ENB | PM_CFG_ASPM_L1_ENB |
+ PM_CFG_MAC_ASPM_CHK;
+ else if ((sc->alc_ifp->if_drv_flags & IFF_DRV_RUNNING) != 0)
+ pmcfg |= PM_CFG_ASPM_L1_ENB | PM_CFG_MAC_ASPM_CHK;
+ }
+ CSR_WRITE_4(sc, ALC_PM_CFG, pmcfg);
+}
- mtx_init(&sc->alc_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK,
- MTX_DEF);
- callout_init_mtx(&sc->alc_tick_ch, &sc->alc_mtx, 0);
- TASK_INIT(&sc->alc_int_task, 0, alc_int_task, sc);
- sc->alc_ident = alc_find_ident(dev);
+static void
+alc_init_pcie(struct alc_softc *sc)
+{
+ const char *aspm_state[] = { "L0s/L1", "L0s", "L1", "L0s/L1" };
+ uint32_t cap, ctl, val;
+ int state;
- /* Map the device. */
- pci_enable_busmaster(dev);
- sc->alc_res_spec = alc_res_spec_mem;
- sc->alc_irq_spec = alc_irq_spec_legacy;
- error = bus_alloc_resources(dev, sc->alc_res_spec, sc->alc_res);
- if (error != 0) {
- device_printf(dev, "cannot allocate memory resources.\n");
- goto fail;
- }
+ /* Clear data link and flow-control protocol error. */
+ val = CSR_READ_4(sc, ALC_PEX_UNC_ERR_SEV);
+ val &= ~(PEX_UNC_ERR_SEV_DLP | PEX_UNC_ERR_SEV_FCP);
+ CSR_WRITE_4(sc, ALC_PEX_UNC_ERR_SEV, val);
- /* Set PHY address. */
- sc->alc_phyaddr = ALC_PHY_ADDR;
-
- /* Initialize DMA parameters. */
- sc->alc_dma_rd_burst = 0;
- sc->alc_dma_wr_burst = 0;
- sc->alc_rcb = DMA_CFG_RCB_64;
- if (pci_find_cap(dev, PCIY_EXPRESS, &base) == 0) {
- sc->alc_flags |= ALC_FLAG_PCIE;
- sc->alc_expcap = base;
- burst = CSR_READ_2(sc, base + PCIER_DEVICE_CTL);
- sc->alc_dma_rd_burst =
- (burst & PCIEM_CTL_MAX_READ_REQUEST) >> 12;
- sc->alc_dma_wr_burst = (burst & PCIEM_CTL_MAX_PAYLOAD) >> 5;
- if (bootverbose) {
- device_printf(dev, "Read request size : %u bytes.\n",
- alc_dma_burst[sc->alc_dma_rd_burst]);
- device_printf(dev, "TLP payload size : %u bytes.\n",
- alc_dma_burst[sc->alc_dma_wr_burst]);
- }
- if (alc_dma_burst[sc->alc_dma_rd_burst] > 1024)
- sc->alc_dma_rd_burst = 3;
- if (alc_dma_burst[sc->alc_dma_wr_burst] > 1024)
- sc->alc_dma_wr_burst = 3;
- /* Clear data link and flow-control protocol error. */
- val = CSR_READ_4(sc, ALC_PEX_UNC_ERR_SEV);
- val &= ~(PEX_UNC_ERR_SEV_DLP | PEX_UNC_ERR_SEV_FCP);
- CSR_WRITE_4(sc, ALC_PEX_UNC_ERR_SEV, val);
+ if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) == 0) {
CSR_WRITE_4(sc, ALC_LTSSM_ID_CFG,
CSR_READ_4(sc, ALC_LTSSM_ID_CFG) & ~LTSSM_ID_WRO_ENB);
CSR_WRITE_4(sc, ALC_PCIE_PHYMISC,
@@ -822,7 +1277,7 @@
CSR_READ_4(sc, ALC_PCIE_PHYMISC) |
PCIE_PHYMISC_FORCE_RCV_DET);
if (sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8152_B &&
- pci_get_revid(dev) == ATHEROS_AR8152_B_V10) {
+ sc->alc_rev == ATHEROS_AR8152_B_V10) {
val = CSR_READ_4(sc, ALC_PCIE_PHYMISC2);
val &= ~(PCIE_PHYMISC2_SERDES_CDR_MASK |
PCIE_PHYMISC2_SERDES_TH_MASK);
@@ -831,18 +1286,18 @@
CSR_WRITE_4(sc, ALC_PCIE_PHYMISC2, val);
}
/* Disable ASPM L0S and L1. */
- cap = CSR_READ_2(sc, base + PCIER_LINK_CAP);
+ cap = CSR_READ_2(sc, sc->alc_expcap + PCIER_LINK_CAP);
if ((cap & PCIEM_LINK_CAP_ASPM) != 0) {
- ctl = CSR_READ_2(sc, base + PCIER_LINK_CTL);
- if ((ctl & 0x08) != 0)
+ ctl = CSR_READ_2(sc, sc->alc_expcap + PCIER_LINK_CTL);
+ if ((ctl & PCIEM_LINK_CTL_RCB) != 0)
sc->alc_rcb = DMA_CFG_RCB_128;
if (bootverbose)
- device_printf(dev, "RCB %u bytes\n",
+ device_printf(sc->alc_dev, "RCB %u bytes\n",
sc->alc_rcb == DMA_CFG_RCB_64 ? 64 : 128);
- state = ctl & 0x03;
- if (state & 0x01)
+ state = ctl & PCIEM_LINK_CTL_ASPMC;
+ if (state & PCIEM_LINK_CTL_ASPMC_L0S)
sc->alc_flags |= ALC_FLAG_L0S;
- if (state & 0x02)
+ if (state & PCIEM_LINK_CTL_ASPMC_L1)
sc->alc_flags |= ALC_FLAG_L1S;
if (bootverbose)
device_printf(sc->alc_dev, "ASPM %s %s\n",
@@ -854,14 +1309,92 @@
device_printf(sc->alc_dev,
"no ASPM support\n");
}
+ } else {
+ val = CSR_READ_4(sc, ALC_PDLL_TRNS1);
+ val &= ~PDLL_TRNS1_D3PLLOFF_ENB;
+ CSR_WRITE_4(sc, ALC_PDLL_TRNS1, val);
+ val = CSR_READ_4(sc, ALC_MASTER_CFG);
+ if (AR816X_REV(sc->alc_rev) <= AR816X_REV_A1 &&
+ (sc->alc_rev & 0x01) != 0) {
+ if ((val & MASTER_WAKEN_25M) == 0 ||
+ (val & MASTER_CLK_SEL_DIS) == 0) {
+ val |= MASTER_WAKEN_25M | MASTER_CLK_SEL_DIS;
+ CSR_WRITE_4(sc, ALC_MASTER_CFG, val);
+ }
+ } else {
+ if ((val & MASTER_WAKEN_25M) == 0 ||
+ (val & MASTER_CLK_SEL_DIS) != 0) {
+ val |= MASTER_WAKEN_25M;
+ val &= ~MASTER_CLK_SEL_DIS;
+ CSR_WRITE_4(sc, ALC_MASTER_CFG, val);
+ }
+ }
}
+ alc_aspm(sc, 1, IFM_UNKNOWN);
+}
- /* Reset PHY. */
- alc_phy_reset(sc);
+static void
+alc_config_msi(struct alc_softc *sc)
+{
+ uint32_t ctl, mod;
- /* Reset the ethernet controller. */
- alc_reset(sc);
+ if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0) {
+ /*
+ * It seems interrupt moderation is controlled by
+ * ALC_MSI_RETRANS_TIMER register if MSI/MSIX is active.
+ * Driver uses RX interrupt moderation parameter to
+ * program ALC_MSI_RETRANS_TIMER register.
+ */
+ ctl = CSR_READ_4(sc, ALC_MSI_RETRANS_TIMER);
+ ctl &= ~MSI_RETRANS_TIMER_MASK;
+ ctl &= ~MSI_RETRANS_MASK_SEL_LINE;
+ mod = ALC_USECS(sc->alc_int_rx_mod);
+ if (mod == 0)
+ mod = 1;
+ ctl |= mod;
+ if ((sc->alc_flags & ALC_FLAG_MSIX) != 0)
+ CSR_WRITE_4(sc, ALC_MSI_RETRANS_TIMER, ctl |
+ MSI_RETRANS_MASK_SEL_STD);
+ else if ((sc->alc_flags & ALC_FLAG_MSI) != 0)
+ CSR_WRITE_4(sc, ALC_MSI_RETRANS_TIMER, ctl |
+ MSI_RETRANS_MASK_SEL_LINE);
+ else
+ CSR_WRITE_4(sc, ALC_MSI_RETRANS_TIMER, 0);
+ }
+}
+static int
+alc_attach(device_t dev)
+{
+ struct alc_softc *sc;
+ struct ifnet *ifp;
+ int base, error, i, msic, msixc;
+ uint16_t burst;
+
+ error = 0;
+ sc = device_get_softc(dev);
+ sc->alc_dev = dev;
+ sc->alc_rev = pci_get_revid(dev);
+
+ mtx_init(&sc->alc_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK,
+ MTX_DEF);
+ callout_init_mtx(&sc->alc_tick_ch, &sc->alc_mtx, 0);
+ TASK_INIT(&sc->alc_int_task, 0, alc_int_task, sc);
+ sc->alc_ident = alc_find_ident(dev);
+
+ /* Map the device. */
+ pci_enable_busmaster(dev);
+ sc->alc_res_spec = alc_res_spec_mem;
+ sc->alc_irq_spec = alc_irq_spec_legacy;
+ error = bus_alloc_resources(dev, sc->alc_res_spec, sc->alc_res);
+ if (error != 0) {
+ device_printf(dev, "cannot allocate memory resources.\n");
+ goto fail;
+ }
+
+ /* Set PHY address. */
+ sc->alc_phyaddr = ALC_PHY_ADDR;
+
/*
* One odd thing is AR8132 uses the same PHY hardware(F1
* gigabit PHY) of AR8131. So atphy(4) of AR8132 reports
@@ -870,6 +1403,23 @@
* shows the same PHY model/revision number of AR8131.
*/
switch (sc->alc_ident->deviceid) {
+ case DEVICEID_ATHEROS_E2200:
+ case DEVICEID_ATHEROS_E2400:
+ case DEVICEID_ATHEROS_E2500:
+ sc->alc_flags |= ALC_FLAG_E2X00;
+ /* FALLTHROUGH */
+ case DEVICEID_ATHEROS_AR8161:
+ if (pci_get_subvendor(dev) == VENDORID_ATHEROS &&
+ pci_get_subdevice(dev) == 0x0091 && sc->alc_rev == 0)
+ sc->alc_flags |= ALC_FLAG_LINK_WAR;
+ /* FALLTHROUGH */
+ case DEVICEID_ATHEROS_AR8171:
+ sc->alc_flags |= ALC_FLAG_AR816X_FAMILY;
+ break;
+ case DEVICEID_ATHEROS_AR8162:
+ case DEVICEID_ATHEROS_AR8172:
+ sc->alc_flags |= ALC_FLAG_FASTETHER | ALC_FLAG_AR816X_FAMILY;
+ break;
case DEVICEID_ATHEROS_AR8152_B:
case DEVICEID_ATHEROS_AR8152_B2:
sc->alc_flags |= ALC_FLAG_APS;
@@ -884,7 +1434,7 @@
default:
break;
}
- sc->alc_flags |= ALC_FLAG_ASPM_MON | ALC_FLAG_JUMBO;
+ sc->alc_flags |= ALC_FLAG_JUMBO;
/*
* It seems that AR813x/AR815x has silicon bug for SMB. In
@@ -897,7 +1447,6 @@
* Don't use Tx CMB. It is known to have silicon bug.
*/
sc->alc_flags |= ALC_FLAG_CMB_BUG;
- sc->alc_rev = pci_get_revid(dev);
sc->alc_chip_rev = CSR_READ_4(sc, ALC_MASTER_CFG) >>
MASTER_CHIP_REV_SHIFT;
if (bootverbose) {
@@ -905,11 +1454,52 @@
sc->alc_rev);
device_printf(dev, "Chip id/revision : 0x%04x\n",
sc->alc_chip_rev);
+ if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0)
+ device_printf(dev, "AR816x revision : 0x%x\n",
+ AR816X_REV(sc->alc_rev));
}
device_printf(dev, "%u Tx FIFO, %u Rx FIFO\n",
CSR_READ_4(sc, ALC_SRAM_TX_FIFO_LEN) * 8,
CSR_READ_4(sc, ALC_SRAM_RX_FIFO_LEN) * 8);
+ /* Initialize DMA parameters. */
+ sc->alc_dma_rd_burst = 0;
+ sc->alc_dma_wr_burst = 0;
+ sc->alc_rcb = DMA_CFG_RCB_64;
+ if (pci_find_cap(dev, PCIY_EXPRESS, &base) == 0) {
+ sc->alc_flags |= ALC_FLAG_PCIE;
+ sc->alc_expcap = base;
+ burst = CSR_READ_2(sc, base + PCIER_DEVICE_CTL);
+ sc->alc_dma_rd_burst =
+ (burst & PCIEM_CTL_MAX_READ_REQUEST) >> 12;
+ sc->alc_dma_wr_burst = (burst & PCIEM_CTL_MAX_PAYLOAD) >> 5;
+ if (bootverbose) {
+ device_printf(dev, "Read request size : %u bytes.\n",
+ alc_dma_burst[sc->alc_dma_rd_burst]);
+ device_printf(dev, "TLP payload size : %u bytes.\n",
+ alc_dma_burst[sc->alc_dma_wr_burst]);
+ }
+ if (alc_dma_burst[sc->alc_dma_rd_burst] > 1024)
+ sc->alc_dma_rd_burst = 3;
+ if (alc_dma_burst[sc->alc_dma_wr_burst] > 1024)
+ sc->alc_dma_wr_burst = 3;
+ /*
+ * Force maximum payload size to 128 bytes for
+ * E2200/E2400/E2500.
+ * Otherwise it triggers DMA write error.
+ */
+ if ((sc->alc_flags & ALC_FLAG_E2X00) != 0)
+ sc->alc_dma_wr_burst = 0;
+ alc_init_pcie(sc);
+ }
+
+ /* Reset PHY. */
+ alc_phy_reset(sc);
+
+ /* Reset the ethernet controller. */
+ alc_stop_mac(sc);
+ alc_reset(sc);
+
/* Allocate IRQ resources. */
msixc = pci_msix_count(dev);
msic = pci_msi_count(dev);
@@ -917,11 +1507,20 @@
device_printf(dev, "MSIX count : %d\n", msixc);
device_printf(dev, "MSI count : %d\n", msic);
}
- /* Prefer MSIX over MSI. */
+ if (msixc > 1)
+ msixc = 1;
+ if (msic > 1)
+ msic = 1;
+ /*
+ * Prefer MSIX over MSI.
+ * AR816x controller has a silicon bug that MSI interrupt
+ * does not assert if PCIM_CMD_INTxDIS bit of command
+ * register is set. pci(4) was taught to handle that case.
+ */
if (msix_disable == 0 || msi_disable == 0) {
- if (msix_disable == 0 && msixc == ALC_MSIX_MESSAGES &&
+ if (msix_disable == 0 && msixc > 0 &&
pci_alloc_msix(dev, &msixc) == 0) {
- if (msic == ALC_MSIX_MESSAGES) {
+ if (msic == 1) {
device_printf(dev,
"Using %d MSIX message(s).\n", msixc);
sc->alc_flags |= ALC_FLAG_MSIX;
@@ -930,9 +1529,8 @@
pci_release_msi(dev);
}
if (msi_disable == 0 && (sc->alc_flags & ALC_FLAG_MSIX) == 0 &&
- msic == ALC_MSI_MESSAGES &&
- pci_alloc_msi(dev, &msic) == 0) {
- if (msic == ALC_MSI_MESSAGES) {
+ msic > 0 && pci_alloc_msi(dev, &msic) == 0) {
+ if (msic == 1) {
device_printf(dev,
"Using %d MSI message(s).\n", msic);
sc->alc_flags |= ALC_FLAG_MSI;
@@ -951,7 +1549,7 @@
/* Create device sysctl node. */
alc_sysctl_node(sc);
- if ((error = alc_dma_alloc(sc) != 0))
+ if ((error = alc_dma_alloc(sc)) != 0)
goto fail;
/* Load station address. */
@@ -1006,9 +1604,13 @@
* sample boards. To safety, don't enable Tx checksum offloading
* by default but give chance to users to toggle it if they know
* their controllers work without problems.
+ * Fortunately, Tx checksum offloading for AR816x family
+ * seems to work.
*/
- ifp->if_capenable &= ~IFCAP_TXCSUM;
- ifp->if_hwassist &= ~ALC_CSUM_FEATURES;
+ if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) == 0) {
+ ifp->if_capenable &= ~IFCAP_TXCSUM;
+ ifp->if_hwassist &= ~ALC_CSUM_FEATURES;
+ }
/* Tell the upper layer(s) we support long frames. */
ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header);
@@ -1025,6 +1627,7 @@
taskqueue_start_threads(&sc->alc_tq, 1, PI_NET, "%s taskq",
device_get_nameunit(sc->alc_dev));
+ alc_config_msi(sc);
if ((sc->alc_flags & ALC_FLAG_MSIX) != 0)
msic = ALC_MSIX_MESSAGES;
else if ((sc->alc_flags & ALC_FLAG_MSI) != 0)
@@ -1286,8 +1889,6 @@
&stats->tx_late_colls, "Late collisions");
ALC_SYSCTL_STAT_ADD32(ctx, child, "excess_colls",
&stats->tx_excess_colls, "Excessive collisions");
- ALC_SYSCTL_STAT_ADD32(ctx, child, "abort",
- &stats->tx_abort, "Aborted frames due to Excessive collisions");
ALC_SYSCTL_STAT_ADD32(ctx, child, "underruns",
&stats->tx_underrun, "FIFO underruns");
ALC_SYSCTL_STAT_ADD32(ctx, child, "desc_underruns",
@@ -1599,7 +2200,7 @@
/*
* Create Tx buffer parent tag.
- * AR813x/AR815x allows 64bit DMA addressing of Tx/Rx buffers
+ * AR81[3567]x allows 64bit DMA addressing of Tx/Rx buffers
* so it needs separate parent DMA tag as parent DMA address
* space could be restricted to be within 32bit address space
* by 4GB boundary crossing.
@@ -1906,6 +2507,16 @@
static void
alc_setwol(struct alc_softc *sc)
{
+
+ if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0)
+ alc_setwol_816x(sc);
+ else
+ alc_setwol_813x(sc);
+}
+
+static void
+alc_setwol_813x(struct alc_softc *sc)
+{
struct ifnet *ifp;
uint32_t reg, pmcs;
uint16_t pmstat;
@@ -1966,6 +2577,72 @@
sc->alc_pmcap + PCIR_POWER_STATUS, pmstat, 2);
}
+static void
+alc_setwol_816x(struct alc_softc *sc)
+{
+ struct ifnet *ifp;
+ uint32_t gphy, mac, master, pmcs, reg;
+ uint16_t pmstat;
+
+ ALC_LOCK_ASSERT(sc);
+
+ ifp = sc->alc_ifp;
+ master = CSR_READ_4(sc, ALC_MASTER_CFG);
+ master &= ~MASTER_CLK_SEL_DIS;
+ gphy = CSR_READ_4(sc, ALC_GPHY_CFG);
+ gphy &= ~(GPHY_CFG_EXT_RESET | GPHY_CFG_LED_MODE | GPHY_CFG_100AB_ENB |
+ GPHY_CFG_PHY_PLL_ON);
+ gphy |= GPHY_CFG_HIB_EN | GPHY_CFG_HIB_PULSE | GPHY_CFG_SEL_ANA_RESET;
+ if ((sc->alc_flags & ALC_FLAG_PM) == 0) {
+ CSR_WRITE_4(sc, ALC_WOL_CFG, 0);
+ gphy |= GPHY_CFG_PHY_IDDQ | GPHY_CFG_PWDOWN_HW;
+ mac = CSR_READ_4(sc, ALC_MAC_CFG);
+ } else {
+ if ((ifp->if_capenable & IFCAP_WOL) != 0) {
+ gphy |= GPHY_CFG_EXT_RESET;
+ if ((sc->alc_flags & ALC_FLAG_FASTETHER) == 0)
+ alc_setlinkspeed(sc);
+ }
+ pmcs = 0;
+ if ((ifp->if_capenable & IFCAP_WOL_MAGIC) != 0)
+ pmcs |= WOL_CFG_MAGIC | WOL_CFG_MAGIC_ENB;
+ CSR_WRITE_4(sc, ALC_WOL_CFG, pmcs);
+ mac = CSR_READ_4(sc, ALC_MAC_CFG);
+ mac &= ~(MAC_CFG_DBG | MAC_CFG_PROMISC | MAC_CFG_ALLMULTI |
+ MAC_CFG_BCAST);
+ if ((ifp->if_capenable & IFCAP_WOL_MCAST) != 0)
+ mac |= MAC_CFG_ALLMULTI | MAC_CFG_BCAST;
+ if ((ifp->if_capenable & IFCAP_WOL) != 0)
+ mac |= MAC_CFG_RX_ENB;
+ alc_miiext_writereg(sc, MII_EXT_ANEG, MII_EXT_ANEG_S3DIG10,
+ ANEG_S3DIG10_SL);
+ }
+
+ /* Enable OSC. */
+ reg = CSR_READ_4(sc, ALC_MISC);
+ reg &= ~MISC_INTNLOSC_OPEN;
+ CSR_WRITE_4(sc, ALC_MISC, reg);
+ reg |= MISC_INTNLOSC_OPEN;
+ CSR_WRITE_4(sc, ALC_MISC, reg);
+ CSR_WRITE_4(sc, ALC_MASTER_CFG, master);
+ CSR_WRITE_4(sc, ALC_MAC_CFG, mac);
+ CSR_WRITE_4(sc, ALC_GPHY_CFG, gphy);
+ reg = CSR_READ_4(sc, ALC_PDLL_TRNS1);
+ reg |= PDLL_TRNS1_D3PLLOFF_ENB;
+ CSR_WRITE_4(sc, ALC_PDLL_TRNS1, reg);
+
+ if ((sc->alc_flags & ALC_FLAG_PM) != 0) {
+ /* Request PME. */
+ pmstat = pci_read_config(sc->alc_dev,
+ sc->alc_pmcap + PCIR_POWER_STATUS, 2);
+ pmstat &= ~(PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE);
+ if ((ifp->if_capenable & IFCAP_WOL) != 0)
+ pmstat |= PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE;
+ pci_write_config(sc->alc_dev,
+ sc->alc_pmcap + PCIR_POWER_STATUS, pmstat, 2);
+ }
+}
+
static int
alc_suspend(device_t dev)
{
@@ -2036,7 +2713,7 @@
ip_off = poff = 0;
if ((m->m_pkthdr.csum_flags & (ALC_CSUM_FEATURES | CSUM_TSO)) != 0) {
/*
- * AR813x/AR815x requires offset of TCP/UDP header in its
+ * AR81[3567]x requires offset of TCP/UDP header in its
* Tx descriptor to perform Tx checksum offloading. TSO
* also requires TCP header offset and modification of
* IP/TCP header. This kind of operation takes many CPU
@@ -2174,7 +2851,7 @@
cflags |= (poff << TD_TCPHDR_OFFSET_SHIFT) &
TD_TCPHDR_OFFSET_MASK;
/*
- * AR813x/AR815x requires the first buffer should
+ * AR81[3567]x requires the first buffer should
* only hold IP/TCP header data. Payload should
* be handled in other descriptors.
*/
@@ -2305,10 +2982,14 @@
bus_dmamap_sync(sc->alc_cdata.alc_tx_ring_tag,
sc->alc_cdata.alc_tx_ring_map, BUS_DMASYNC_PREWRITE);
/* Kick. Assume we're using normal Tx priority queue. */
- CSR_WRITE_4(sc, ALC_MBOX_TD_PROD_IDX,
- (sc->alc_cdata.alc_tx_prod <<
- MBOX_TD_PROD_LO_IDX_SHIFT) &
- MBOX_TD_PROD_LO_IDX_MASK);
+ if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0)
+ CSR_WRITE_2(sc, ALC_MBOX_TD_PRI0_PROD_IDX,
+ (uint16_t)sc->alc_cdata.alc_tx_prod);
+ else
+ CSR_WRITE_4(sc, ALC_MBOX_TD_PROD_IDX,
+ (sc->alc_cdata.alc_tx_prod <<
+ MBOX_TD_PROD_LO_IDX_SHIFT) &
+ MBOX_TD_PROD_LO_IDX_MASK);
/* Set a timeout in case the chip goes out to lunch. */
sc->alc_watchdog_timer = ALC_TX_TIMEOUT;
}
@@ -2362,7 +3043,7 @@
else if (ifp->if_mtu != ifr->ifr_mtu) {
ALC_LOCK(sc);
ifp->if_mtu = ifr->ifr_mtu;
- /* AR813x/AR815x has 13 bits MSS field. */
+ /* AR81[3567]x has 13 bits MSS field. */
if (ifp->if_mtu > ALC_TSO_MTU &&
(ifp->if_capenable & IFCAP_TSO4) != 0) {
ifp->if_capenable &= ~IFCAP_TSO4;
@@ -2413,7 +3094,7 @@
(ifp->if_capabilities & IFCAP_TSO4) != 0) {
ifp->if_capenable ^= IFCAP_TSO4;
if ((ifp->if_capenable & IFCAP_TSO4) != 0) {
- /* AR813x/AR815x has 13 bits MSS field. */
+ /* AR81[3567]x has 13 bits MSS field. */
if (ifp->if_mtu > ALC_TSO_MTU) {
ifp->if_capenable &= ~IFCAP_TSO4;
ifp->if_hwassist &= ~CSUM_TSO;
@@ -2465,7 +3146,8 @@
reg = CSR_READ_4(sc, ALC_MAC_CFG);
reg &= ~(MAC_CFG_FULL_DUPLEX | MAC_CFG_TX_FC | MAC_CFG_RX_FC |
MAC_CFG_SPEED_MASK);
- if (sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8151 ||
+ if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0 ||
+ sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8151 ||
sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8151_V2 ||
sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8152_B2)
reg |= MAC_CFG_HASH_ALG_CRC32 | MAC_CFG_SPEED_MODE_SW;
@@ -2603,7 +3285,6 @@
stat->tx_multi_colls += smb->tx_multi_colls;
stat->tx_late_colls += smb->tx_late_colls;
stat->tx_excess_colls += smb->tx_excess_colls;
- stat->tx_abort += smb->tx_abort;
stat->tx_underrun += smb->tx_underrun;
stat->tx_desc_underrun += smb->tx_desc_underrun;
stat->tx_lenerrs += smb->tx_lenerrs;
@@ -2616,7 +3297,7 @@
ifp->if_collisions += smb->tx_single_colls +
smb->tx_multi_colls * 2 + smb->tx_late_colls +
- smb->tx_abort * HDPX_CFG_RETRY_DEFAULT;
+ smb->tx_excess_colls * HDPX_CFG_RETRY_DEFAULT;
/*
* XXX
@@ -2625,8 +3306,8 @@
* the counter name is not correct one so I've removed the
* counter in output errors.
*/
- ifp->if_oerrors += smb->tx_abort + smb->tx_late_colls +
- smb->tx_underrun;
+ ifp->if_oerrors += smb->tx_late_colls + smb->tx_excess_colls +
+ smb->tx_underrun + smb->tx_pkts_truncated;
ifp->if_ipackets += smb->rx_frames;
@@ -2754,11 +3435,16 @@
bus_dmamap_sync(sc->alc_cdata.alc_cmb_tag,
sc->alc_cdata.alc_cmb_map, BUS_DMASYNC_POSTREAD);
prod = sc->alc_rdata.alc_cmb->cons;
- } else
- prod = CSR_READ_4(sc, ALC_MBOX_TD_CONS_IDX);
- /* Assume we're using normal Tx priority queue. */
- prod = (prod & MBOX_TD_CONS_LO_IDX_MASK) >>
- MBOX_TD_CONS_LO_IDX_SHIFT;
+ } else {
+ if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0)
+ prod = CSR_READ_2(sc, ALC_MBOX_TD_PRI0_CONS_IDX);
+ else {
+ prod = CSR_READ_4(sc, ALC_MBOX_TD_CONS_IDX);
+ /* Assume we're using normal Tx priority queue. */
+ prod = (prod & MBOX_TD_CONS_LO_IDX_MASK) >>
+ MBOX_TD_CONS_LO_IDX_SHIFT;
+ }
+ }
cons = sc->alc_cdata.alc_tx_cons;
/*
* Go through our Tx list and free mbufs for those
@@ -2894,8 +3580,12 @@
* it still seems that pre-fetching needs more
* experimentation.
*/
- CSR_WRITE_4(sc, ALC_MBOX_RD0_PROD_IDX,
- sc->alc_cdata.alc_rx_cons);
+ if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0)
+ CSR_WRITE_2(sc, ALC_MBOX_RD0_PROD_IDX,
+ (uint16_t)sc->alc_cdata.alc_rx_cons);
+ else
+ CSR_WRITE_4(sc, ALC_MBOX_RD0_PROD_IDX,
+ sc->alc_cdata.alc_rx_cons);
}
return (count > 0 ? 0 : EAGAIN);
@@ -3087,14 +3777,78 @@
}
static void
+alc_osc_reset(struct alc_softc *sc)
+{
+ uint32_t reg;
+
+ reg = CSR_READ_4(sc, ALC_MISC3);
+ reg &= ~MISC3_25M_BY_SW;
+ reg |= MISC3_25M_NOTO_INTNL;
+ CSR_WRITE_4(sc, ALC_MISC3, reg);
+
+ reg = CSR_READ_4(sc, ALC_MISC);
+ if (AR816X_REV(sc->alc_rev) >= AR816X_REV_B0) {
+ /*
+ * Restore over-current protection default value.
+ * This value could be reset by MAC reset.
+ */
+ reg &= ~MISC_PSW_OCP_MASK;
+ reg |= (MISC_PSW_OCP_DEFAULT << MISC_PSW_OCP_SHIFT);
+ reg &= ~MISC_INTNLOSC_OPEN;
+ CSR_WRITE_4(sc, ALC_MISC, reg);
+ CSR_WRITE_4(sc, ALC_MISC, reg | MISC_INTNLOSC_OPEN);
+ reg = CSR_READ_4(sc, ALC_MISC2);
+ reg &= ~MISC2_CALB_START;
+ CSR_WRITE_4(sc, ALC_MISC2, reg);
+ CSR_WRITE_4(sc, ALC_MISC2, reg | MISC2_CALB_START);
+
+ } else {
+ reg &= ~MISC_INTNLOSC_OPEN;
+ /* Disable isolate for revision A devices. */
+ if (AR816X_REV(sc->alc_rev) <= AR816X_REV_A1)
+ reg &= ~MISC_ISO_ENB;
+ CSR_WRITE_4(sc, ALC_MISC, reg | MISC_INTNLOSC_OPEN);
+ CSR_WRITE_4(sc, ALC_MISC, reg);
+ }
+
+ DELAY(20);
+}
+
+static void
alc_reset(struct alc_softc *sc)
{
- uint32_t reg;
+ uint32_t pmcfg, reg;
int i;
- reg = CSR_READ_4(sc, ALC_MASTER_CFG) & 0xFFFF;
+ pmcfg = 0;
+ if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0) {
+ /* Reset workaround. */
+ CSR_WRITE_4(sc, ALC_MBOX_RD0_PROD_IDX, 1);
+ if (AR816X_REV(sc->alc_rev) <= AR816X_REV_A1 &&
+ (sc->alc_rev & 0x01) != 0) {
+ /* Disable L0s/L1s before reset. */
+ pmcfg = CSR_READ_4(sc, ALC_PM_CFG);
+ if ((pmcfg & (PM_CFG_ASPM_L0S_ENB | PM_CFG_ASPM_L1_ENB))
+ != 0) {
+ pmcfg &= ~(PM_CFG_ASPM_L0S_ENB |
+ PM_CFG_ASPM_L1_ENB);
+ CSR_WRITE_4(sc, ALC_PM_CFG, pmcfg);
+ }
+ }
+ }
+ reg = CSR_READ_4(sc, ALC_MASTER_CFG);
reg |= MASTER_OOB_DIS_OFF | MASTER_RESET;
CSR_WRITE_4(sc, ALC_MASTER_CFG, reg);
+
+ if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0) {
+ for (i = ALC_RESET_TIMEOUT; i > 0; i--) {
+ DELAY(10);
+ if (CSR_READ_4(sc, ALC_MBOX_RD0_PROD_IDX) == 0)
+ break;
+ }
+ if (i == 0)
+ device_printf(sc->alc_dev, "MAC reset timeout!\n");
+ }
for (i = ALC_RESET_TIMEOUT; i > 0; i--) {
DELAY(10);
if ((CSR_READ_4(sc, ALC_MASTER_CFG) & MASTER_RESET) == 0)
@@ -3104,13 +3858,45 @@
device_printf(sc->alc_dev, "master reset timeout!\n");
for (i = ALC_RESET_TIMEOUT; i > 0; i--) {
- if ((reg = CSR_READ_4(sc, ALC_IDLE_STATUS)) == 0)
+ reg = CSR_READ_4(sc, ALC_IDLE_STATUS);
+ if ((reg & (IDLE_STATUS_RXMAC | IDLE_STATUS_TXMAC |
+ IDLE_STATUS_RXQ | IDLE_STATUS_TXQ)) == 0)
break;
DELAY(10);
}
-
if (i == 0)
device_printf(sc->alc_dev, "reset timeout(0x%08x)!\n", reg);
+
+ if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0) {
+ if (AR816X_REV(sc->alc_rev) <= AR816X_REV_A1 &&
+ (sc->alc_rev & 0x01) != 0) {
+ reg = CSR_READ_4(sc, ALC_MASTER_CFG);
+ reg |= MASTER_CLK_SEL_DIS;
+ CSR_WRITE_4(sc, ALC_MASTER_CFG, reg);
+ /* Restore L0s/L1s config. */
+ if ((pmcfg & (PM_CFG_ASPM_L0S_ENB | PM_CFG_ASPM_L1_ENB))
+ != 0)
+ CSR_WRITE_4(sc, ALC_PM_CFG, pmcfg);
+ }
+
+ alc_osc_reset(sc);
+ reg = CSR_READ_4(sc, ALC_MISC3);
+ reg &= ~MISC3_25M_BY_SW;
+ reg |= MISC3_25M_NOTO_INTNL;
+ CSR_WRITE_4(sc, ALC_MISC3, reg);
+ reg = CSR_READ_4(sc, ALC_MISC);
+ reg &= ~MISC_INTNLOSC_OPEN;
+ if (AR816X_REV(sc->alc_rev) <= AR816X_REV_A1)
+ reg &= ~MISC_ISO_ENB;
+ CSR_WRITE_4(sc, ALC_MISC, reg);
+ DELAY(20);
+ }
+ if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0 ||
+ sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8152_B ||
+ sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8151_V2)
+ CSR_WRITE_4(sc, ALC_SERDES_LOCK,
+ CSR_READ_4(sc, ALC_SERDES_LOCK) | SERDES_MAC_CLK_SLOWDOWN |
+ SERDES_PHY_CLK_SLOWDOWN);
}
static void
@@ -3161,7 +3947,16 @@
alc_init_smb(sc);
/* Enable all clocks. */
- CSR_WRITE_4(sc, ALC_CLK_GATING_CFG, 0);
+ if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0) {
+ CSR_WRITE_4(sc, ALC_CLK_GATING_CFG, CLK_GATING_DMAW_ENB |
+ CLK_GATING_DMAR_ENB | CLK_GATING_TXQ_ENB |
+ CLK_GATING_RXQ_ENB | CLK_GATING_TXMAC_ENB |
+ CLK_GATING_RXMAC_ENB);
+ if (AR816X_REV(sc->alc_rev) >= AR816X_REV_B0)
+ CSR_WRITE_4(sc, ALC_IDLE_DECISN_TIMER,
+ IDLE_DECISN_TIMER_DEFAULT_1MS);
+ } else
+ CSR_WRITE_4(sc, ALC_CLK_GATING_CFG, 0);
/* Reprogram the station address. */
bcopy(IF_LLADDR(ifp), eaddr, ETHER_ADDR_LEN);
@@ -3187,10 +3982,12 @@
paddr = sc->alc_rdata.alc_rx_ring_paddr;
CSR_WRITE_4(sc, ALC_RX_BASE_ADDR_HI, ALC_ADDR_HI(paddr));
CSR_WRITE_4(sc, ALC_RD0_HEAD_ADDR_LO, ALC_ADDR_LO(paddr));
- /* We use one Rx ring. */
- CSR_WRITE_4(sc, ALC_RD1_HEAD_ADDR_LO, 0);
- CSR_WRITE_4(sc, ALC_RD2_HEAD_ADDR_LO, 0);
- CSR_WRITE_4(sc, ALC_RD3_HEAD_ADDR_LO, 0);
+ if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) == 0) {
+ /* We use one Rx ring. */
+ CSR_WRITE_4(sc, ALC_RD1_HEAD_ADDR_LO, 0);
+ CSR_WRITE_4(sc, ALC_RD2_HEAD_ADDR_LO, 0);
+ CSR_WRITE_4(sc, ALC_RD3_HEAD_ADDR_LO, 0);
+ }
/* Set Rx descriptor counter. */
CSR_WRITE_4(sc, ALC_RD_RING_CNT,
(ALC_RX_RING_CNT << RD_RING_CNT_SHIFT) & RD_RING_CNT_MASK);
@@ -3215,10 +4012,12 @@
paddr = sc->alc_rdata.alc_rr_ring_paddr;
/* Set Rx return descriptor base addresses. */
CSR_WRITE_4(sc, ALC_RRD0_HEAD_ADDR_LO, ALC_ADDR_LO(paddr));
- /* We use one Rx return ring. */
- CSR_WRITE_4(sc, ALC_RRD1_HEAD_ADDR_LO, 0);
- CSR_WRITE_4(sc, ALC_RRD2_HEAD_ADDR_LO, 0);
- CSR_WRITE_4(sc, ALC_RRD3_HEAD_ADDR_LO, 0);
+ if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) == 0) {
+ /* We use one Rx return ring. */
+ CSR_WRITE_4(sc, ALC_RRD1_HEAD_ADDR_LO, 0);
+ CSR_WRITE_4(sc, ALC_RRD2_HEAD_ADDR_LO, 0);
+ CSR_WRITE_4(sc, ALC_RRD3_HEAD_ADDR_LO, 0);
+ }
/* Set Rx return descriptor counter. */
CSR_WRITE_4(sc, ALC_RRD_RING_CNT,
(ALC_RR_RING_CNT << RRD_RING_CNT_SHIFT) & RRD_RING_CNT_MASK);
@@ -3245,16 +4044,20 @@
/* Configure interrupt moderation timer. */
reg = ALC_USECS(sc->alc_int_rx_mod) << IM_TIMER_RX_SHIFT;
- reg |= ALC_USECS(sc->alc_int_tx_mod) << IM_TIMER_TX_SHIFT;
+ if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) == 0)
+ reg |= ALC_USECS(sc->alc_int_tx_mod) << IM_TIMER_TX_SHIFT;
CSR_WRITE_4(sc, ALC_IM_TIMER, reg);
/*
* We don't want to automatic interrupt clear as task queue
* for the interrupt should know interrupt status.
*/
- reg = MASTER_SA_TIMER_ENB;
+ reg = CSR_READ_4(sc, ALC_MASTER_CFG);
+ reg &= ~(MASTER_IM_RX_TIMER_ENB | MASTER_IM_TX_TIMER_ENB);
+ reg |= MASTER_SA_TIMER_ENB;
if (ALC_USECS(sc->alc_int_rx_mod) != 0)
reg |= MASTER_IM_RX_TIMER_ENB;
- if (ALC_USECS(sc->alc_int_tx_mod) != 0)
+ if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) == 0 &&
+ ALC_USECS(sc->alc_int_tx_mod) != 0)
reg |= MASTER_IM_TX_TIMER_ENB;
CSR_WRITE_4(sc, ALC_MASTER_CFG, reg);
/*
@@ -3263,11 +4066,17 @@
*/
CSR_WRITE_4(sc, ALC_INTR_RETRIG_TIMER, ALC_USECS(0));
/* Configure CMB. */
- if ((sc->alc_flags & ALC_FLAG_CMB_BUG) == 0) {
- CSR_WRITE_4(sc, ALC_CMB_TD_THRESH, 4);
- CSR_WRITE_4(sc, ALC_CMB_TX_TIMER, ALC_USECS(5000));
- } else
- CSR_WRITE_4(sc, ALC_CMB_TX_TIMER, ALC_USECS(0));
+ if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0) {
+ CSR_WRITE_4(sc, ALC_CMB_TD_THRESH, ALC_TX_RING_CNT / 3);
+ CSR_WRITE_4(sc, ALC_CMB_TX_TIMER,
+ ALC_USECS(sc->alc_int_tx_mod));
+ } else {
+ if ((sc->alc_flags & ALC_FLAG_CMB_BUG) == 0) {
+ CSR_WRITE_4(sc, ALC_CMB_TD_THRESH, 4);
+ CSR_WRITE_4(sc, ALC_CMB_TX_TIMER, ALC_USECS(5000));
+ } else
+ CSR_WRITE_4(sc, ALC_CMB_TX_TIMER, ALC_USECS(0));
+ }
/*
* Hardware can be configured to issue SMB interrupt based
* on programmed interval. Since there is a callout that is
@@ -3294,33 +4103,42 @@
*/
CSR_WRITE_4(sc, ALC_FRAME_SIZE, sc->alc_ident->max_framelen);
- /* Disable header split(?) */
- CSR_WRITE_4(sc, ALC_HDS_CFG, 0);
+ if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) == 0) {
+ /* Disable header split(?) */
+ CSR_WRITE_4(sc, ALC_HDS_CFG, 0);
- /* Configure IPG/IFG parameters. */
- CSR_WRITE_4(sc, ALC_IPG_IFG_CFG,
- ((IPG_IFG_IPGT_DEFAULT << IPG_IFG_IPGT_SHIFT) & IPG_IFG_IPGT_MASK) |
- ((IPG_IFG_MIFG_DEFAULT << IPG_IFG_MIFG_SHIFT) & IPG_IFG_MIFG_MASK) |
- ((IPG_IFG_IPG1_DEFAULT << IPG_IFG_IPG1_SHIFT) & IPG_IFG_IPG1_MASK) |
- ((IPG_IFG_IPG2_DEFAULT << IPG_IFG_IPG2_SHIFT) & IPG_IFG_IPG2_MASK));
- /* Set parameters for half-duplex media. */
- CSR_WRITE_4(sc, ALC_HDPX_CFG,
- ((HDPX_CFG_LCOL_DEFAULT << HDPX_CFG_LCOL_SHIFT) &
- HDPX_CFG_LCOL_MASK) |
- ((HDPX_CFG_RETRY_DEFAULT << HDPX_CFG_RETRY_SHIFT) &
- HDPX_CFG_RETRY_MASK) | HDPX_CFG_EXC_DEF_EN |
- ((HDPX_CFG_ABEBT_DEFAULT << HDPX_CFG_ABEBT_SHIFT) &
- HDPX_CFG_ABEBT_MASK) |
- ((HDPX_CFG_JAMIPG_DEFAULT << HDPX_CFG_JAMIPG_SHIFT) &
- HDPX_CFG_JAMIPG_MASK));
+ /* Configure IPG/IFG parameters. */
+ CSR_WRITE_4(sc, ALC_IPG_IFG_CFG,
+ ((IPG_IFG_IPGT_DEFAULT << IPG_IFG_IPGT_SHIFT) &
+ IPG_IFG_IPGT_MASK) |
+ ((IPG_IFG_MIFG_DEFAULT << IPG_IFG_MIFG_SHIFT) &
+ IPG_IFG_MIFG_MASK) |
+ ((IPG_IFG_IPG1_DEFAULT << IPG_IFG_IPG1_SHIFT) &
+ IPG_IFG_IPG1_MASK) |
+ ((IPG_IFG_IPG2_DEFAULT << IPG_IFG_IPG2_SHIFT) &
+ IPG_IFG_IPG2_MASK));
+ /* Set parameters for half-duplex media. */
+ CSR_WRITE_4(sc, ALC_HDPX_CFG,
+ ((HDPX_CFG_LCOL_DEFAULT << HDPX_CFG_LCOL_SHIFT) &
+ HDPX_CFG_LCOL_MASK) |
+ ((HDPX_CFG_RETRY_DEFAULT << HDPX_CFG_RETRY_SHIFT) &
+ HDPX_CFG_RETRY_MASK) | HDPX_CFG_EXC_DEF_EN |
+ ((HDPX_CFG_ABEBT_DEFAULT << HDPX_CFG_ABEBT_SHIFT) &
+ HDPX_CFG_ABEBT_MASK) |
+ ((HDPX_CFG_JAMIPG_DEFAULT << HDPX_CFG_JAMIPG_SHIFT) &
+ HDPX_CFG_JAMIPG_MASK));
+ }
+
/*
* Set TSO/checksum offload threshold. For frames that is
* larger than this threshold, hardware wouldn't do
* TSO/checksum offloading.
*/
- CSR_WRITE_4(sc, ALC_TSO_OFFLOAD_THRESH,
- (sc->alc_ident->max_framelen >> TSO_OFFLOAD_THRESH_UNIT_SHIFT) &
- TSO_OFFLOAD_THRESH_MASK);
+ reg = (sc->alc_ident->max_framelen >> TSO_OFFLOAD_THRESH_UNIT_SHIFT) &
+ TSO_OFFLOAD_THRESH_MASK;
+ if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0)
+ reg |= TSO_OFFLOAD_ERRLGPKT_DROP_ENB;
+ CSR_WRITE_4(sc, ALC_TSO_OFFLOAD_THRESH, reg);
/* Configure TxQ. */
reg = (alc_dma_burst[sc->alc_dma_rd_burst] <<
TXQ_CFG_TX_FIFO_BURST_SHIFT) & TXQ_CFG_TX_FIFO_BURST_MASK;
@@ -3329,21 +4147,50 @@
reg >>= 1;
reg |= (TXQ_CFG_TD_BURST_DEFAULT << TXQ_CFG_TD_BURST_SHIFT) &
TXQ_CFG_TD_BURST_MASK;
+ reg |= TXQ_CFG_IP_OPTION_ENB | TXQ_CFG_8023_ENB;
CSR_WRITE_4(sc, ALC_TXQ_CFG, reg | TXQ_CFG_ENHANCED_MODE);
+ if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0) {
+ reg = (TXQ_CFG_TD_BURST_DEFAULT << HQTD_CFG_Q1_BURST_SHIFT |
+ TXQ_CFG_TD_BURST_DEFAULT << HQTD_CFG_Q2_BURST_SHIFT |
+ TXQ_CFG_TD_BURST_DEFAULT << HQTD_CFG_Q3_BURST_SHIFT |
+ HQTD_CFG_BURST_ENB);
+ CSR_WRITE_4(sc, ALC_HQTD_CFG, reg);
+ reg = WRR_PRI_RESTRICT_NONE;
+ reg |= (WRR_PRI_DEFAULT << WRR_PRI0_SHIFT |
+ WRR_PRI_DEFAULT << WRR_PRI1_SHIFT |
+ WRR_PRI_DEFAULT << WRR_PRI2_SHIFT |
+ WRR_PRI_DEFAULT << WRR_PRI3_SHIFT);
+ CSR_WRITE_4(sc, ALC_WRR, reg);
+ } else {
+ /* Configure Rx free descriptor pre-fetching. */
+ CSR_WRITE_4(sc, ALC_RX_RD_FREE_THRESH,
+ ((RX_RD_FREE_THRESH_HI_DEFAULT <<
+ RX_RD_FREE_THRESH_HI_SHIFT) & RX_RD_FREE_THRESH_HI_MASK) |
+ ((RX_RD_FREE_THRESH_LO_DEFAULT <<
+ RX_RD_FREE_THRESH_LO_SHIFT) & RX_RD_FREE_THRESH_LO_MASK));
+ }
- /* Configure Rx free descriptor pre-fetching. */
- CSR_WRITE_4(sc, ALC_RX_RD_FREE_THRESH,
- ((RX_RD_FREE_THRESH_HI_DEFAULT << RX_RD_FREE_THRESH_HI_SHIFT) &
- RX_RD_FREE_THRESH_HI_MASK) |
- ((RX_RD_FREE_THRESH_LO_DEFAULT << RX_RD_FREE_THRESH_LO_SHIFT) &
- RX_RD_FREE_THRESH_LO_MASK));
-
/*
* Configure flow control parameters.
* XON : 80% of Rx FIFO
* XOFF : 30% of Rx FIFO
*/
- if (sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8131 ||
+ if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0) {
+ reg = CSR_READ_4(sc, ALC_SRAM_RX_FIFO_LEN);
+ reg &= SRAM_RX_FIFO_LEN_MASK;
+ reg *= 8;
+ if (reg > 8 * 1024)
+ reg -= RX_FIFO_PAUSE_816X_RSVD;
+ else
+ reg -= RX_BUF_SIZE_MAX;
+ reg /= 8;
+ CSR_WRITE_4(sc, ALC_RX_FIFO_PAUSE_THRESH,
+ ((reg << RX_FIFO_PAUSE_THRESH_LO_SHIFT) &
+ RX_FIFO_PAUSE_THRESH_LO_MASK) |
+ (((RX_FIFO_PAUSE_816X_RSVD / 8) <<
+ RX_FIFO_PAUSE_THRESH_HI_SHIFT) &
+ RX_FIFO_PAUSE_THRESH_HI_MASK));
+ } else if (sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8131 ||
sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8132) {
reg = CSR_READ_4(sc, ALC_SRAM_RX_FIFO_LEN);
rxf_hi = (reg * 8) / 10;
@@ -3355,22 +4202,27 @@
RX_FIFO_PAUSE_THRESH_HI_MASK));
}
- if (sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8152_B ||
- sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8151_V2)
- CSR_WRITE_4(sc, ALC_SERDES_LOCK,
- CSR_READ_4(sc, ALC_SERDES_LOCK) | SERDES_MAC_CLK_SLOWDOWN |
- SERDES_PHY_CLK_SLOWDOWN);
+ if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) == 0) {
+ /* Disable RSS until I understand L1C/L2C's RSS logic. */
+ CSR_WRITE_4(sc, ALC_RSS_IDT_TABLE0, 0);
+ CSR_WRITE_4(sc, ALC_RSS_CPU, 0);
+ }
- /* Disable RSS until I understand L1C/L2C's RSS logic. */
- CSR_WRITE_4(sc, ALC_RSS_IDT_TABLE0, 0);
- CSR_WRITE_4(sc, ALC_RSS_CPU, 0);
-
/* Configure RxQ. */
reg = (RXQ_CFG_RD_BURST_DEFAULT << RXQ_CFG_RD_BURST_SHIFT) &
RXQ_CFG_RD_BURST_MASK;
reg |= RXQ_CFG_RSS_MODE_DIS;
- if ((sc->alc_flags & ALC_FLAG_ASPM_MON) != 0)
- reg |= RXQ_CFG_ASPM_THROUGHPUT_LIMIT_1M;
+ if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0) {
+ reg |= (RXQ_CFG_816X_IDT_TBL_SIZE_DEFAULT <<
+ RXQ_CFG_816X_IDT_TBL_SIZE_SHIFT) &
+ RXQ_CFG_816X_IDT_TBL_SIZE_MASK;
+ if ((sc->alc_flags & ALC_FLAG_FASTETHER) == 0)
+ reg |= RXQ_CFG_ASPM_THROUGHPUT_LIMIT_100M;
+ } else {
+ if ((sc->alc_flags & ALC_FLAG_FASTETHER) == 0 &&
+ sc->alc_ident->deviceid != DEVICEID_ATHEROS_AR8151_V2)
+ reg |= RXQ_CFG_ASPM_THROUGHPUT_LIMIT_100M;
+ }
CSR_WRITE_4(sc, ALC_RXQ_CFG, reg);
/* Configure DMA parameters. */
@@ -3390,6 +4242,19 @@
DMA_CFG_RD_DELAY_CNT_MASK;
reg |= (DMA_CFG_WR_DELAY_CNT_DEFAULT << DMA_CFG_WR_DELAY_CNT_SHIFT) &
DMA_CFG_WR_DELAY_CNT_MASK;
+ if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0) {
+ switch (AR816X_REV(sc->alc_rev)) {
+ case AR816X_REV_A0:
+ case AR816X_REV_A1:
+ reg |= DMA_CFG_RD_CHNL_SEL_2;
+ break;
+ case AR816X_REV_B0:
+ /* FALLTHROUGH */
+ default:
+ reg |= DMA_CFG_RD_CHNL_SEL_4;
+ break;
+ }
+ }
CSR_WRITE_4(sc, ALC_DMA_CFG, reg);
/*
@@ -3408,7 +4273,8 @@
reg = MAC_CFG_TX_CRC_ENB | MAC_CFG_TX_AUTO_PAD | MAC_CFG_FULL_DUPLEX |
((MAC_CFG_PREAMBLE_DEFAULT << MAC_CFG_PREAMBLE_SHIFT) &
MAC_CFG_PREAMBLE_MASK);
- if (sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8151 ||
+ if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0 ||
+ sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8151 ||
sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8151_V2 ||
sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8152_B2)
reg |= MAC_CFG_HASH_ALG_CRC32 | MAC_CFG_SPEED_MODE_SW;
@@ -3427,14 +4293,14 @@
CSR_WRITE_4(sc, ALC_INTR_STATUS, 0xFFFFFFFF);
CSR_WRITE_4(sc, ALC_INTR_STATUS, 0);
+ ifp->if_drv_flags |= IFF_DRV_RUNNING;
+ ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
+
sc->alc_flags &= ~ALC_FLAG_LINK;
/* Switch to the current media. */
- mii_mediachg(mii);
+ alc_mediachange_locked(sc);
callout_reset(&sc->alc_tick_ch, hz, alc_tick, sc);
-
- ifp->if_drv_flags |= IFF_DRV_RUNNING;
- ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
}
static void
@@ -3459,7 +4325,6 @@
/* Disable interrupts. */
CSR_WRITE_4(sc, ALC_INTR_MASK, 0);
CSR_WRITE_4(sc, ALC_INTR_STATUS, 0xFFFFFFFF);
- alc_stop_queue(sc);
/* Disable DMA. */
reg = CSR_READ_4(sc, ALC_DMA_CFG);
reg &= ~(DMA_CFG_CMB_ENB | DMA_CFG_SMB_ENB);
@@ -3470,7 +4335,8 @@
alc_stop_mac(sc);
/* Disable interrupts which might be touched in taskq handler. */
CSR_WRITE_4(sc, ALC_INTR_STATUS, 0xFFFFFFFF);
-
+ /* Disable L0s/L1s */
+ alc_aspm(sc, 0, IFM_UNKNOWN);
/* Reclaim Rx buffers that have been processed. */
if (sc->alc_cdata.alc_rxhead != NULL)
m_freem(sc->alc_cdata.alc_rxhead);
@@ -3508,8 +4374,7 @@
uint32_t reg;
int i;
- ALC_LOCK_ASSERT(sc);
-
+ alc_stop_queue(sc);
/* Disable Rx/Tx MAC. */
reg = CSR_READ_4(sc, ALC_MAC_CFG);
if ((reg & (MAC_CFG_TX_ENB | MAC_CFG_RX_ENB)) != 0) {
@@ -3518,7 +4383,7 @@
}
for (i = ALC_TIMEOUT; i > 0; i--) {
reg = CSR_READ_4(sc, ALC_IDLE_STATUS);
- if (reg == 0)
+ if ((reg & (IDLE_STATUS_RXMAC | IDLE_STATUS_TXMAC)) == 0)
break;
DELAY(10);
}
@@ -3543,8 +4408,11 @@
/* Enable RxQ. */
cfg = CSR_READ_4(sc, ALC_RXQ_CFG);
- cfg &= ~RXQ_CFG_ENB;
- cfg |= qcfg[1];
+ if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) == 0) {
+ cfg &= ~RXQ_CFG_ENB;
+ cfg |= qcfg[1];
+ } else
+ cfg |= RXQ_CFG_QUEUE0_ENB;
CSR_WRITE_4(sc, ALC_RXQ_CFG, cfg);
/* Enable TxQ. */
cfg = CSR_READ_4(sc, ALC_TXQ_CFG);
@@ -3558,13 +4426,18 @@
uint32_t reg;
int i;
- ALC_LOCK_ASSERT(sc);
-
/* Disable RxQ. */
reg = CSR_READ_4(sc, ALC_RXQ_CFG);
- if ((reg & RXQ_CFG_ENB) != 0) {
- reg &= ~RXQ_CFG_ENB;
- CSR_WRITE_4(sc, ALC_RXQ_CFG, reg);
+ if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) == 0) {
+ if ((reg & RXQ_CFG_ENB) != 0) {
+ reg &= ~RXQ_CFG_ENB;
+ CSR_WRITE_4(sc, ALC_RXQ_CFG, reg);
+ }
+ } else {
+ if ((reg & RXQ_CFG_QUEUE0_ENB) != 0) {
+ reg &= ~RXQ_CFG_QUEUE0_ENB;
+ CSR_WRITE_4(sc, ALC_RXQ_CFG, reg);
+ }
}
/* Disable TxQ. */
reg = CSR_READ_4(sc, ALC_TXQ_CFG);
@@ -3572,6 +4445,7 @@
reg &= ~TXQ_CFG_ENB;
CSR_WRITE_4(sc, ALC_TXQ_CFG, reg);
}
+ DELAY(40);
for (i = ALC_TIMEOUT; i > 0; i--) {
reg = CSR_READ_4(sc, ALC_IDLE_STATUS);
if ((reg & (IDLE_STATUS_RXQ | IDLE_STATUS_TXQ)) == 0)
Modified: trunk/sys/dev/alc/if_alcreg.h
===================================================================
--- trunk/sys/dev/alc/if_alcreg.h 2018-05-28 00:25:20 UTC (rev 10127)
+++ trunk/sys/dev/alc/if_alcreg.h 2018-05-28 00:27:43 UTC (rev 10128)
@@ -1,3 +1,4 @@
+/* $MidnightBSD$ */
/*-
* Copyright (c) 2009, Pyun YongHyeon <yongari at FreeBSD.org>
* All rights reserved.
@@ -24,7 +25,7 @@
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*
- * $MidnightBSD$
+ * $FreeBSD: stable/10/sys/dev/alc/if_alcreg.h 314019 2017-02-21 03:27:59Z sephe $
*/
#ifndef _IF_ALCREG_H
@@ -44,10 +45,28 @@
#define DEVICEID_ATHEROS_AR8151_V2 0x1083 /* L1D V2.0 */
#define DEVICEID_ATHEROS_AR8152_B 0x2060 /* L2C V1.1 */
#define DEVICEID_ATHEROS_AR8152_B2 0x2062 /* L2C V2.0 */
+#define DEVICEID_ATHEROS_AR8161 0x1091
+#define DEVICEID_ATHEROS_AR8162 0x1090
+#define DEVICEID_ATHEROS_AR8171 0x10A1
+#define DEVICEID_ATHEROS_AR8172 0x10A0
+#define DEVICEID_ATHEROS_E2200 0xE091
+#define DEVICEID_ATHEROS_E2400 0xE0A1
+#define DEVICEID_ATHEROS_E2500 0xE0B1
#define ATHEROS_AR8152_B_V10 0xC0
#define ATHEROS_AR8152_B_V11 0xC1
+/*
+ * Atheros AR816x/AR817x revisions
+ */
+#define AR816X_REV_A0 0
+#define AR816X_REV_A1 1
+#define AR816X_REV_B0 2
+#define AR816X_REV_C0 3
+
+#define AR816X_REV_SHIFT 3
+#define AR816X_REV(x) ((x) >> AR816X_REV_SHIFT)
+
/* 0x0000 - 0x02FF : PCIe configuration space */
#define ALC_PEX_UNC_ERR_SEV 0x10C
@@ -63,11 +82,34 @@
#define PEX_UNC_ERR_SEV_ECRC 0x00080000
#define PEX_UNC_ERR_SEV_UR 0x00100000
+#define ALC_EEPROM_LD 0x204 /* AR816x */
+#define EEPROM_LD_START 0x00000001
+#define EEPROM_LD_IDLE 0x00000010
+#define EEPROM_LD_DONE 0x00000000
+#define EEPROM_LD_PROGRESS 0x00000020
+#define EEPROM_LD_EXIST 0x00000100
+#define EEPROM_LD_EEPROM_EXIST 0x00000200
+#define EEPROM_LD_FLASH_EXIST 0x00000400
+#define EEPROM_LD_FLASH_END_ADDR_MASK 0x03FF0000
+#define EEPROM_LD_FLASH_END_ADDR_SHIFT 16
+
#define ALC_TWSI_CFG 0x218
#define TWSI_CFG_SW_LD_START 0x00000800
#define TWSI_CFG_HW_LD_START 0x00001000
#define TWSI_CFG_LD_EXIST 0x00400000
+#define ALC_SLD 0x218 /* AR816x */
+#define SLD_START 0x00000800
+#define SLD_PROGRESS 0x00001000
+#define SLD_IDLE 0x00002000
+#define SLD_SLVADDR_MASK 0x007F0000
+#define SLD_EXIST 0x00800000
+#define SLD_FREQ_MASK 0x03000000
+#define SLD_FREQ_100K 0x00000000
+#define SLD_FREQ_200K 0x01000000
+#define SLD_FREQ_300K 0x02000000
+#define SLD_FREQ_400K 0x03000000
+
#define ALC_PCIE_PHYMISC 0x1000
#define PCIE_PHYMISC_FORCE_RCV_DET 0x00000004
@@ -77,6 +119,9 @@
#define PCIE_PHYMISC2_SERDES_CDR_SHIFT 16
#define PCIE_PHYMISC2_SERDES_TH_SHIFT 18
+#define ALC_PDLL_TRNS1 0x1104
+#define PDLL_TRNS1_D3PLLOFF_ENB 0x00000800
+
#define ALC_TWSI_DEBUG 0x1108
#define TWSI_DEBUG_DEV_EXIST 0x20000000
@@ -103,11 +148,14 @@
#define PM_CFG_SERDES_PD_EX_L1 0x00000040
#define PM_CFG_SERDES_BUDS_RX_L1_ENB 0x00000080
#define PM_CFG_L0S_ENTRY_TIMER_MASK 0x00000F00
+#define PM_CFG_RX_L1_AFTER_L0S 0x00000800
#define PM_CFG_ASPM_L0S_ENB 0x00001000
#define PM_CFG_CLK_SWH_L1 0x00002000
#define PM_CFG_CLK_PWM_VER1_1 0x00004000
#define PM_CFG_PCIE_RECV 0x00008000
#define PM_CFG_L1_ENTRY_TIMER_MASK 0x000F0000
+#define PM_CFG_L1_ENTRY_TIMER_816X_MASK 0x00070000
+#define PM_CFG_TX_L1_AFTER_L0S 0x00080000
#define PM_CFG_PM_REQ_TIMER_MASK 0x00F00000
#define PM_CFG_LCKDET_TIMER_MASK 0x0F000000
#define PM_CFG_EN_BUFS_RX_L0S 0x10000000
@@ -121,8 +169,10 @@
#define PM_CFG_L0S_ENTRY_TIMER_DEFAULT 6
#define PM_CFG_L1_ENTRY_TIMER_DEFAULT 1
+#define PM_CFG_L1_ENTRY_TIMER_816X_DEFAULT 4
#define PM_CFG_LCKDET_TIMER_DEFAULT 12
#define PM_CFG_PM_REQ_TIMER_DEFAULT 12
+#define PM_CFG_PM_REQ_TIMER_816X_DEFAULT 15
#define ALC_LTSSM_ID_CFG 0x12FC
#define LTSSM_ID_WRO_ENB 0x00001000
@@ -131,6 +181,7 @@
#define MASTER_RESET 0x00000001
#define MASTER_TEST_MODE_MASK 0x0000000C
#define MASTER_BERT_START 0x00000010
+#define MASTER_WAKEN_25M 0x00000020
#define MASTER_OOB_DIS_OFF 0x00000040
#define MASTER_SA_TIMER_ENB 0x00000080
#define MASTER_MTIMER_ENB 0x00000100
@@ -171,7 +222,7 @@
*/
#define ALC_IM_TX_TIMER_DEFAULT 1000 /* 1ms */
-#define ALC_GPHY_CFG 0x140C /* 16bits */
+#define ALC_GPHY_CFG 0x140C /* 16 bits, 32 bits on AR816x */
#define GPHY_CFG_EXT_RESET 0x0001
#define GPHY_CFG_RTL_MODE 0x0002
#define GPHY_CFG_LED_MODE 0x0004
@@ -188,6 +239,7 @@
#define GPHY_CFG_PHY_PLL_ON 0x2000
#define GPHY_CFG_PWDOWN_HW 0x4000
#define GPHY_CFG_PHY_PLL_BYPASS 0x8000
+#define GPHY_CFG_100AB_ENB 0x00020000
#define ALC_IDLE_STATUS 0x1410
#define IDLE_STATUS_RXMAC 0x00000001
@@ -212,9 +264,10 @@
#define MDIO_CLK_25_10 0x04000000
#define MDIO_CLK_25_14 0x05000000
#define MDIO_CLK_25_20 0x06000000
-#define MDIO_CLK_25_28 0x07000000
+#define MDIO_CLK_25_128 0x07000000
#define MDIO_OP_BUSY 0x08000000
#define MDIO_AP_ENB 0x10000000
+#define MDIO_MODE_EXT 0x40000000
#define MDIO_DATA_SHIFT 0
#define MDIO_REG_ADDR_SHIFT 16
@@ -248,6 +301,23 @@
#define SERDES_MAC_CLK_SLOWDOWN 0x00020000
#define SERDES_PHY_CLK_SLOWDOWN 0x00040000
+#define ALC_LPI_CTL 0x1440
+#define LPI_CTL_ENB 0x00000001
+
+#define ALC_EXT_MDIO 0x1448
+#define EXT_MDIO_REG_MASK 0x0000FFFF
+#define EXT_MDIO_DEVADDR_MASK 0x001F0000
+#define EXT_MDIO_REG_SHIFT 0
+#define EXT_MDIO_DEVADDR_SHIFT 16
+
+#define EXT_MDIO_REG(x) \
+ (((x) << EXT_MDIO_REG_SHIFT) & EXT_MDIO_REG_MASK)
+#define EXT_MDIO_DEVADDR(x) \
+ (((x) << EXT_MDIO_DEVADDR_SHIFT) & EXT_MDIO_DEVADDR_MASK)
+
+#define ALC_IDLE_DECISN_TIMER 0x1474
+#define IDLE_DECISN_TIMER_DEFAULT_1MS 0x400
+
#define ALC_MAC_CFG 0x1480
#define MAC_CFG_TX_ENB 0x00000001
#define MAC_CFG_RX_ENB 0x00000002
@@ -278,6 +348,7 @@
#define MAC_CFG_SINGLE_PAUSE_ENB 0x10000000
#define MAC_CFG_HASH_ALG_CRC32 0x20000000
#define MAC_CFG_SPEED_MODE_SW 0x40000000
+#define MAC_CFG_FAST_PAUSE 0x80000000
#define MAC_CFG_PREAMBLE_SHIFT 10
#define MAC_CFG_PREAMBLE_DEFAULT 7
@@ -378,8 +449,12 @@
#define ALC_RSS_IDT_TABLE0 0x14E0
+#define ALC_TD_PRI2_HEAD_ADDR_LO 0x14E0 /* AR816x */
+
#define ALC_RSS_IDT_TABLE1 0x14E4
+#define ALC_TD_PRI3_HEAD_ADDR_LO 0x14E4 /* AR816x */
+
#define ALC_RSS_IDT_TABLE2 0x14E8
#define ALC_RSS_IDT_TABLE3 0x14EC
@@ -422,6 +497,8 @@
#define ALC_SRAM_RX_FIFO_ADDR 0x1520
#define ALC_SRAM_RX_FIFO_LEN 0x1524
+#define SRAM_RX_FIFO_LEN_MASK 0x00000FFF
+#define SRAM_RX_FIFO_LEN_SHIFT 0
#define ALC_SRAM_TX_FIFO_ADDR 0x1528
@@ -478,8 +555,12 @@
#define ALC_TDH_HEAD_ADDR_LO 0x157C
+#define ALC_TD_PRI1_HEAD_ADDR_LO 0x157C /* AR816x */
+
#define ALC_TDL_HEAD_ADDR_LO 0x1580
+#define ALC_TD_PRI0_HEAD_ADDR_LO 0x1580 /* AR816x */
+
#define ALC_TD_RING_CNT 0x1584
#define TD_RING_CNT_MASK 0x0000FFFF
#define TD_RING_CNT_SHIFT 0
@@ -499,6 +580,7 @@
#define ALC_TSO_OFFLOAD_THRESH 0x1594 /* 8 bytes unit */
#define TSO_OFFLOAD_THRESH_MASK 0x000007FF
+#define TSO_OFFLOAD_ERRLGPKT_DROP_ENB 0x00000800
#define TSO_OFFLOAD_THRESH_SHIFT 0
#define TSO_OFFLOAD_THRESH_UNIT 8
#define TSO_OFFLOAD_THRESH_UNIT_SHIFT 3
@@ -546,6 +628,17 @@
(RXQ_CFG_QUEUE0_ENB | RXQ_CFG_QUEUE1_ENB | \
RXQ_CFG_QUEUE2_ENB | RXQ_CFG_QUEUE3_ENB)
+/* AR816x specific bits */
+#define RXQ_CFG_816X_RSS_HASH_IPV4 0x00000004
+#define RXQ_CFG_816X_RSS_HASH_IPV4_TCP 0x00000008
+#define RXQ_CFG_816X_RSS_HASH_IPV6 0x00000010
+#define RXQ_CFG_816X_RSS_HASH_IPV6_TCP 0x00000020
+#define RXQ_CFG_816X_RSS_HASH_MASK 0x0000003C
+#define RXQ_CFG_816X_IPV6_PARSE_ENB 0x00000080
+#define RXQ_CFG_816X_IDT_TBL_SIZE_MASK 0x0001FF00
+#define RXQ_CFG_816X_IDT_TBL_SIZE_SHIFT 8
+#define RXQ_CFG_816X_IDT_TBL_SIZE_DEFAULT 0x100
+
#define ALC_RX_RD_FREE_THRESH 0x15A4 /* 8 bytes unit. */
#define RX_RD_FREE_THRESH_HI_MASK 0x0000003F
#define RX_RD_FREE_THRESH_LO_MASK 0x00000FC0
@@ -559,6 +652,12 @@
#define RX_FIFO_PAUSE_THRESH_HI_MASK 0x0FFF0000
#define RX_FIFO_PAUSE_THRESH_LO_SHIFT 0
#define RX_FIFO_PAUSE_THRESH_HI_SHIFT 16
+/*
+ * Size = tx-packet(1522) + IPG(12) + SOF(8) + 64(Pause) + IPG(12) + SOF(8) +
+ * rx-packet(1522) + delay-of-link(64)
+ * = 3212.
+ */
+#define RX_FIFO_PAUSE_816X_RSVD 3212
#define ALC_RD_DMA_CFG 0x15AC
#define RD_DMA_CFG_THRESH_MASK 0x00000FFF /* 8 bytes unit */
@@ -582,6 +681,7 @@
#define DMA_CFG_OUT_ORDER 0x00000004
#define DMA_CFG_RCB_64 0x00000000
#define DMA_CFG_RCB_128 0x00000008
+#define DMA_CFG_PEND_AUTO_RST 0x00000008
#define DMA_CFG_RD_BURST_128 0x00000000
#define DMA_CFG_RD_BURST_256 0x00000010
#define DMA_CFG_RD_BURST_512 0x00000020
@@ -601,6 +701,14 @@
#define DMA_CFG_SMB_ENB 0x00200000
#define DMA_CFG_CMB_NOW 0x00400000
#define DMA_CFG_SMB_DIS 0x01000000
+#define DMA_CFG_RD_CHNL_SEL_MASK 0x0C000000
+#define DMA_CFG_RD_CHNL_SEL_1 0x00000000
+#define DMA_CFG_RD_CHNL_SEL_2 0x04000000
+#define DMA_CFG_RD_CHNL_SEL_3 0x08000000
+#define DMA_CFG_RD_CHNL_SEL_4 0x0C000000
+#define DMA_CFG_WSRAM_RDCTL 0x10000000
+#define DMA_CFG_RD_PEND_CLR 0x20000000
+#define DMA_CFG_WR_PEND_CLR 0x40000000
#define DMA_CFG_SMB_NOW 0x80000000
#define DMA_CFG_RD_BURST_MASK 0x07
#define DMA_CFG_RD_BURST_SHIFT 4
@@ -623,6 +731,12 @@
#define CMB_TX_TIMER_MASK 0x0000FFFF
#define CMB_TX_TIMER_SHIFT 0
+#define ALC_MSI_MAP_TBL1 0x15D0
+
+#define ALC_MSI_ID_MAP 0x15D4
+
+#define ALC_MSI_MAP_TBL2 0x15D8
+
#define ALC_MBOX_RD0_PROD_IDX 0x15E0
#define ALC_MBOX_RD1_PROD_IDX 0x15E4
@@ -640,6 +754,10 @@
#define MBOX_TD_PROD_HI_IDX_SHIFT 0
#define MBOX_TD_PROD_LO_IDX_SHIFT 16
+#define ALC_MBOX_TD_PRI1_PROD_IDX 0x15F0 /* 16 bits AR816x */
+
+#define ALC_MBOX_TD_PRI0_PROD_IDX 0x15F2 /* 16 bits AR816x */
+
#define ALC_MBOX_TD_CONS_IDX 0x15F4
#define MBOX_TD_CONS_HI_IDX_MASK 0x0000FFFF
#define MBOX_TD_CONS_LO_IDX_MASK 0xFFFF0000
@@ -646,6 +764,10 @@
#define MBOX_TD_CONS_HI_IDX_SHIFT 0
#define MBOX_TD_CONS_LO_IDX_SHIFT 16
+#define ALC_MBOX_TD_PRI1_CONS_IDX 0x15F4 /* 16 bits AR816x */
+
+#define ALC_MBOX_TD_PRI0_CONS_IDX 0x15F6 /* 16 bits AR816x */
+
#define ALC_MBOX_RD01_CONS_IDX 0x15F8
#define MBOX_RD0_CONS_IDX_MASK 0x0000FFFF
#define MBOX_RD1_CONS_IDX_MASK 0xFFFF0000
@@ -674,7 +796,7 @@
#define INTR_GPHY 0x00001000
#define INTR_GPHY_LOW_PW 0x00002000
#define INTR_TXQ_TO_RST 0x00004000
-#define INTR_TX_PKT 0x00008000
+#define INTR_TX_PKT0 0x00008000
#define INTR_RX_PKT0 0x00010000
#define INTR_RX_PKT1 0x00020000
#define INTR_RX_PKT2 0x00040000
@@ -688,6 +810,15 @@
#define INTR_PHY_LINK_DOWN 0x04000000
#define INTR_DIS_INT 0x80000000
+/* INTR status for AR816x/AR817x 4 TX queues, 8 RX queues */
+#define INTR_TX_PKT1 0x00000020
+#define INTR_TX_PKT2 0x00000040
+#define INTR_TX_PKT3 0x00000080
+#define INTR_RX_PKT4 0x08000000
+#define INTR_RX_PKT5 0x10000000
+#define INTR_RX_PKT6 0x20000000
+#define INTR_RX_PKT7 0x40000000
+
/* Interrupt Mask Register */
#define ALC_INTR_MASK 0x1604
@@ -699,6 +830,7 @@
(INTR_RD0_UNDERRUN | INTR_RD1_UNDERRUN | \
INTR_RD2_UNDERRUN | INTR_RD3_UNDERRUN)
#else
+#define INTR_TX_PKT INTR_TX_PKT0
#define INTR_RX_PKT INTR_RX_PKT0
#define INTR_RD_UNDERRUN INTR_RD0_UNDERRUN
#endif
@@ -720,11 +852,54 @@
#define HDS_CFG_BACKFILLSIZE_SHIFT 8
#define HDS_CFG_MAX_HDRSIZE_SHIFT 20
+#define ALC_MBOX_TD_PRI3_PROD_IDX 0x1618 /* 16 bits AR816x */
+
+#define ALC_MBOX_TD_PRI2_PROD_IDX 0x161A /* 16 bits AR816x */
+
+#define ALC_MBOX_TD_PRI3_CONS_IDX 0x161C /* 16 bits AR816x */
+
+#define ALC_MBOX_TD_PRI2_CONS_IDX 0x161E /* 16 bits AR816x */
+
/* AR813x/AR815x registers for MAC statistics */
#define ALC_RX_MIB_BASE 0x1700
#define ALC_TX_MIB_BASE 0x1760
+#define ALC_DRV 0x1804 /* AR816x */
+#define DRV_ASPM_SPD10LMT_1M 0x00000000
+#define DRV_ASPM_SPD10LMT_10M 0x00000001
+#define DRV_ASPM_SPD10LMT_100M 0x00000002
+#define DRV_ASPM_SPD10LMT_NO 0x00000003
+#define DRV_ASPM_SPD10LMT_MASK 0x00000003
+#define DRV_ASPM_SPD100LMT_1M 0x00000000
+#define DRV_ASPM_SPD100LMT_10M 0x00000004
+#define DRV_ASPM_SPD100LMT_100M 0x00000008
+#define DRV_ASPM_SPD100LMT_NO 0x0000000C
+#define DRV_ASPM_SPD100LMT_MASK 0x0000000C
+#define DRV_ASPM_SPD1000LMT_100M 0x00000000
+#define DRV_ASPM_SPD1000LMT_NO 0x00000010
+#define DRV_ASPM_SPD1000LMT_1M 0x00000020
+#define DRV_ASPM_SPD1000LMT_10M 0x00000030
+#define DRV_ASPM_SPD1000LMT_MASK 0x00000000
+#define DRV_WOLCAP_BIOS_EN 0x00000100
+#define DRV_WOLMAGIC_EN 0x00000200
+#define DRV_WOLLINKUP_EN 0x00000400
+#define DRV_WOLPATTERN_EN 0x00000800
+#define DRV_AZ_EN 0x00001000
+#define DRV_WOLS5_BIOS_EN 0x00010000
+#define DRV_WOLS5_EN 0x00020000
+#define DRV_DISABLE 0x00040000
+#define DRV_PHY_MASK 0x1FE00000
+#define DRV_PHY_EEE 0x00200000
+#define DRV_PHY_APAUSE 0x00400000
+#define DRV_PHY_PAUSE 0x00800000
+#define DRV_PHY_DUPLEX 0x01000000
+#define DRV_PHY_10 0x02000000
+#define DRV_PHY_100 0x04000000
+#define DRV_PHY_1000 0x08000000
+#define DRV_PHY_AUTO 0x10000000
+#define DRV_PHY_SHIFT 21
+
#define ALC_CLK_GATING_CFG 0x1814
#define CLK_GATING_DMAW_ENB 0x0001
#define CLK_GATING_DMAR_ENB 0x0002
@@ -737,6 +912,52 @@
#define ALC_DEBUG_DATA1 0x1904
+#define ALC_MSI_RETRANS_TIMER 0x1920
+#define MSI_RETRANS_TIMER_MASK 0x0000FFFF
+#define MSI_RETRANS_MASK_SEL_STD 0x00000000
+#define MSI_RETRANS_MASK_SEL_LINE 0x00010000
+#define MSI_RETRANS_TIMER_SHIFT 0
+
+#define ALC_WRR 0x1938
+#define WRR_PRI0_MASK 0x0000001F
+#define WRR_PRI1_MASK 0x00001F00
+#define WRR_PRI2_MASK 0x001F0000
+#define WRR_PRI3_MASK 0x1F000000
+#define WRR_PRI_RESTRICT_MASK 0x60000000
+#define WRR_PRI_RESTRICT_ALL 0x00000000
+#define WRR_PRI_RESTRICT_HI 0x20000000
+#define WRR_PRI_RESTRICT_HI2 0x40000000
+#define WRR_PRI_RESTRICT_NONE 0x60000000
+#define WRR_PRI0_SHIFT 0
+#define WRR_PRI1_SHIFT 8
+#define WRR_PRI2_SHIFT 16
+#define WRR_PRI3_SHIFT 24
+#define WRR_PRI_DEFAULT 4
+#define WRR_PRI_RESTRICT_SHIFT 29
+
+#define ALC_HQTD_CFG 0x193C
+#define HQTD_CFG_Q1_BURST_MASK 0x0000000F
+#define HQTD_CFG_Q2_BURST_MASK 0x000000F0
+#define HQTD_CFG_Q3_BURST_MASK 0x00000F00
+#define HQTD_CFG_BURST_ENB 0x80000000
+#define HQTD_CFG_Q1_BURST_SHIFT 0
+#define HQTD_CFG_Q2_BURST_SHIFT 4
+#define HQTD_CFG_Q3_BURST_SHIFT 8
+
+#define ALC_MISC 0x19C0
+#define MISC_INTNLOSC_OPEN 0x00000008
+#define MISC_ISO_ENB 0x00001000
+#define MISC_PSW_OCP_MASK 0x00E00000
+#define MISC_PSW_OCP_SHIFT 21
+#define MISC_PSW_OCP_DEFAULT 7
+
+#define ALC_MISC2 0x19C8
+#define MISC2_CALB_START 0x00000001
+
+#define ALC_MISC3 0x19CC
+#define MISC3_25M_NOTO_INTNL 0x00000001
+#define MISC3_25M_BY_SW 0x00000002
+
#define ALC_MII_DBG_ADDR 0x1D
#define ALC_MII_DBG_DATA 0x1E
@@ -756,6 +977,9 @@
#define ANA_SEL_CLK125M_DSP 0x8000
#define ANA_MANUL_SWICH_ON_SHIFT 1
+#define MII_DBG_ANACTL 0x00
+#define DBG_ANACTL_DEFAULT 0x02EF
+
#define MII_ANA_CFG4 0x04
#define ANA_IECHO_ADJ_MASK 0x0F
#define ANA_IECHO_ADJ_3_MASK 0x000F
@@ -767,6 +991,9 @@
#define ANA_IECHO_ADJ_1_SHIFT 8
#define ANA_IECHO_ADJ_0_SHIFT 12
+#define MII_DBG_SYSMODCTL 0x04
+#define DBG_SYSMODCTL_DEFAULT 0xBB8B
+
#define MII_ANA_CFG5 0x05
#define ANA_SERDES_CDR_BW_MASK 0x0003
#define ANA_MS_PAD_DBG 0x0004
@@ -783,9 +1010,17 @@
#define ANA_SERDES_CDR_BW_SHIFT 0
#define ANA_SERDES_TH_LOS_SHIFT 4
+#define MII_DBG_SRDSYSMOD 0x05
+#define DBG_SRDSYSMOD_DEFAULT 0x2C46
+
#define MII_ANA_CFG11 0x0B
#define ANA_PS_HIB_EN 0x8000
+#define MII_DBG_HIBNEG 0x0B
+#define DBG_HIBNEG_HIB_PULSE 0x1000
+#define DBG_HIBNEG_PSHIB_EN 0x8000
+#define DBG_HIBNEG_DEFAULT 0xBC40
+
#define MII_ANA_CFG18 0x12
#define ANA_TEST_MODE_10BT_01MASK 0x0003
#define ANA_LOOP_SEL_10BT 0x0004
@@ -800,9 +1035,36 @@
#define ANA_TRIGGER_SEL_TIMER_SHIFT 12
#define ANA_INTERVAL_SEL_TIMER_SHIFT 14
+#define MII_DBG_TST10BTCFG 0x12
+#define DBG_TST10BTCFG_DEFAULT 0x4C04
+
+#define MII_DBG_AZ_ANADECT 0x15
+#define DBG_AZ_ANADECT_DEFAULT 0x3220
+#define DBG_AZ_ANADECT_LONG 0x3210
+
+#define MII_DBG_MSE16DB 0x18
+#define DBG_MSE16DB_UP 0x05EA
+#define DBG_MSE16DB_DOWN 0x02EA
+
+#define MII_DBG_MSE20DB 0x1C
+#define DBG_MSE20DB_TH_MASK 0x01FC
+#define DBG_MSE20DB_TH_DEFAULT 0x2E
+#define DBG_MSE20DB_TH_HI 0x54
+#define DBG_MSE20DB_TH_SHIFT 2
+
+#define MII_DBG_AGC 0x23
+#define DBG_AGC_2_VGA_MASK 0x3F00
+#define DBG_AGC_2_VGA_SHIFT 8
+#define DBG_AGC_LONG1G_LIMT 40
+#define DBG_AGC_LONG100M_LIMT 44
+
#define MII_ANA_CFG41 0x29
#define ANA_TOP_PS_EN 0x8000
+#define MII_DBG_LEGCYPS 0x29
+#define DBG_LEGCYPS_ENB 0x8000
+#define DBG_LEGCYPS_DEFAULT 0x129D
+
#define MII_ANA_CFG54 0x36
#define ANA_LONG_CABLE_TH_100_MASK 0x003F
#define ANA_DESERVED 0x0040
@@ -813,6 +1075,51 @@
#define ANA_LONG_CABLE_TH_100_SHIFT 0
#define ANA_SHORT_CABLE_TH_100_SHIFT 8
+#define MII_DBG_TST100BTCFG 0x36
+#define DBG_TST100BTCFG_DEFAULT 0xE12C
+
+#define MII_DBG_GREENCFG 0x3B
+#define DBG_GREENCFG_DEFAULT 0x7078
+
+#define MII_DBG_GREENCFG2 0x3D
+#define DBG_GREENCFG2_GATE_DFSE_EN 0x0080
+#define DBG_GREENCFG2_BP_GREEN 0x8000
+
+/* Device addr 3 */
+#define MII_EXT_PCS 3
+
+#define MII_EXT_CLDCTL3 0x8003
+#define EXT_CLDCTL3_BP_CABLE1TH_DET_GT 0x8000
+
+#define MII_EXT_CLDCTL5 0x8005
+#define EXT_CLDCTL5_BP_VD_HLFBIAS 0x4000
+
+#define MII_EXT_CLDCTL6 0x8006
+#define EXT_CLDCTL6_CAB_LEN_MASK 0x00FF
+#define EXT_CLDCTL6_CAB_LEN_SHIFT 0
+#define EXT_CLDCTL6_CAB_LEN_SHORT1G 116
+#define EXT_CLDCTL6_CAB_LEN_SHORT100M 152
+
+#define MII_EXT_VDRVBIAS 0x8062
+#define EXT_VDRVBIAS_DEFAULT 3
+
+/* Device addr 7 */
+#define MII_EXT_ANEG 7
+
+#define MII_EXT_ANEG_LOCAL_EEEADV 0x3C
+#define ANEG_LOCA_EEEADV_100BT 0x0002
+#define ANEG_LOCA_EEEADV_1000BT 0x0004
+
+#define MII_EXT_ANEG_AFE 0x801A
+#define ANEG_AFEE_10BT_100M_TH 0x0040
+
+#define MII_EXT_ANEG_S3DIG10 0x8023
+#define ANEG_S3DIG10_SL 0x0001
+#define ANEG_S3DIG10_DEFAULT 0
+
+#define MII_EXT_ANEG_NLP78 0x8027
+#define ANEG_NLP78_120M_DEFAULT 0x8A05
+
/* Statistics counters collected by the MAC. */
struct smb {
/* Rx stats. */
@@ -860,7 +1167,6 @@
uint32_t tx_multi_colls;
uint32_t tx_late_colls;
uint32_t tx_excess_colls;
- uint32_t tx_abort;
uint32_t tx_underrun;
uint32_t tx_desc_underrun;
uint32_t tx_lenerrs;
Modified: trunk/sys/dev/alc/if_alcvar.h
===================================================================
--- trunk/sys/dev/alc/if_alcvar.h 2018-05-28 00:25:20 UTC (rev 10127)
+++ trunk/sys/dev/alc/if_alcvar.h 2018-05-28 00:27:43 UTC (rev 10128)
@@ -1,3 +1,4 @@
+/* $MidnightBSD$ */
/*-
* Copyright (c) 2009, Pyun YongHyeon <yongari at FreeBSD.org>
* All rights reserved.
@@ -24,7 +25,7 @@
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*
- * $MidnightBSD$
+ * $FreeBSD: stable/10/sys/dev/alc/if_alcvar.h 312359 2017-01-18 01:53:07Z yongari $
*/
#ifndef _IF_ALCVAR_H
@@ -42,7 +43,7 @@
#define ALC_TSO_MAXSEGSIZE 4096
#define ALC_TSO_MAXSIZE (65535 + sizeof(struct ether_vlan_header))
-#define ALC_MAXTXSEGS 32
+#define ALC_MAXTXSEGS 35
#define ALC_ADDR_LO(x) ((uint64_t) (x) & 0xFFFFFFFF)
#define ALC_ADDR_HI(x) ((uint64_t) (x) >> 32)
@@ -52,6 +53,10 @@
/* Water mark to kick reclaiming Tx buffers. */
#define ALC_TX_DESC_HIWAT ((ALC_TX_RING_CNT * 6) / 10)
+/*
+ * AR816x controllers support up to 16 messages but this driver
+ * uses single message.
+ */
#define ALC_MSI_MESSAGES 1
#define ALC_MSIX_MESSAGES 1
@@ -224,13 +229,15 @@
#define ALC_FLAG_PM 0x0010
#define ALC_FLAG_FASTETHER 0x0020
#define ALC_FLAG_JUMBO 0x0040
-#define ALC_FLAG_ASPM_MON 0x0080
#define ALC_FLAG_CMB_BUG 0x0100
#define ALC_FLAG_SMB_BUG 0x0200
#define ALC_FLAG_L0S 0x0400
#define ALC_FLAG_L1S 0x0800
#define ALC_FLAG_APS 0x1000
-#define ALC_FLAG_LINK 0x8000
+#define ALC_FLAG_AR816X_FAMILY 0x2000
+#define ALC_FLAG_LINK_WAR 0x4000
+#define ALC_FLAG_E2X00 0x8000
+#define ALC_FLAG_LINK 0x10000
struct callout alc_tick_ch;
struct alc_hw_stats alc_stats;
Modified: trunk/sys/dev/ale/if_ale.c
===================================================================
--- trunk/sys/dev/ale/if_ale.c 2018-05-28 00:25:20 UTC (rev 10127)
+++ trunk/sys/dev/ale/if_ale.c 2018-05-28 00:27:43 UTC (rev 10128)
@@ -1,3 +1,4 @@
+/* $MidnightBSD$ */
/*-
* Copyright (c) 2008, Pyun YongHyeon <yongari at FreeBSD.org>
* All rights reserved.
@@ -28,7 +29,7 @@
/* Driver for Atheros AR8121/AR8113/AR8114 PCIe Ethernet. */
#include <sys/cdefs.h>
-__MBSDID("$MidnightBSD$");
+__FBSDID("$FreeBSD: stable/10/sys/dev/ale/if_ale.c 312362 2017-01-18 02:16:17Z yongari $");
#include <sys/param.h>
#include <sys/systm.h>
@@ -602,7 +603,7 @@
/* Create device sysctl node. */
ale_sysctl_node(sc);
- if ((error = ale_dma_alloc(sc) != 0))
+ if ((error = ale_dma_alloc(sc)) != 0)
goto fail;
/* Load station address. */
@@ -945,8 +946,6 @@
&stats->tx_late_colls, "Late collisions");
ALE_SYSCTL_STAT_ADD32(ctx, child, "excess_colls",
&stats->tx_excess_colls, "Excessive collisions");
- ALE_SYSCTL_STAT_ADD32(ctx, child, "abort",
- &stats->tx_abort, "Aborted frames due to Excessive collisions");
ALE_SYSCTL_STAT_ADD32(ctx, child, "underruns",
&stats->tx_underrun, "FIFO underruns");
ALE_SYSCTL_STAT_ADD32(ctx, child, "desc_underruns",
@@ -1659,6 +1658,7 @@
(mtod(m, intptr_t) & 3) != 0) {
m = m_defrag(*m_head, M_NOWAIT);
if (m == NULL) {
+ m_freem(*m_head);
*m_head = NULL;
return (ENOBUFS);
}
@@ -2199,7 +2199,6 @@
stat->tx_multi_colls += smb->tx_multi_colls;
stat->tx_late_colls += smb->tx_late_colls;
stat->tx_excess_colls += smb->tx_excess_colls;
- stat->tx_abort += smb->tx_abort;
stat->tx_underrun += smb->tx_underrun;
stat->tx_desc_underrun += smb->tx_desc_underrun;
stat->tx_lenerrs += smb->tx_lenerrs;
@@ -2212,17 +2211,10 @@
ifp->if_collisions += smb->tx_single_colls +
smb->tx_multi_colls * 2 + smb->tx_late_colls +
- smb->tx_abort * HDPX_CFG_RETRY_DEFAULT;
+ smb->tx_excess_colls * HDPX_CFG_RETRY_DEFAULT;
- /*
- * XXX
- * tx_pkts_truncated counter looks suspicious. It constantly
- * increments with no sign of Tx errors. This may indicate
- * the counter name is not correct one so I've removed the
- * counter in output errors.
- */
- ifp->if_oerrors += smb->tx_abort + smb->tx_late_colls +
- smb->tx_underrun;
+ ifp->if_oerrors += smb->tx_late_colls + smb->tx_excess_colls +
+ smb->tx_underrun + smb->tx_pkts_truncated;
ifp->if_ipackets += smb->rx_frames;
Modified: trunk/sys/dev/ale/if_alereg.h
===================================================================
--- trunk/sys/dev/ale/if_alereg.h 2018-05-28 00:25:20 UTC (rev 10127)
+++ trunk/sys/dev/ale/if_alereg.h 2018-05-28 00:27:43 UTC (rev 10128)
@@ -1,3 +1,4 @@
+/* $MidnightBSD$ */
/*-
* Copyright (c) 2008, Pyun YongHyeon <yongari at FreeBSD.org>
* All rights reserved.
@@ -24,7 +25,7 @@
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*
- * $MidnightBSD$
+ * $FreeBSD: stable/10/sys/dev/ale/if_alereg.h 273357 2014-10-21 01:14:56Z yongari $
*/
#ifndef _IF_ALEREG_H
@@ -605,7 +606,6 @@
uint32_t tx_multi_colls;
uint32_t tx_late_colls;
uint32_t tx_excess_colls;
- uint32_t tx_abort;
uint32_t tx_underrun;
uint32_t tx_desc_underrun;
uint32_t tx_lenerrs;
Modified: trunk/sys/dev/ale/if_alevar.h
===================================================================
--- trunk/sys/dev/ale/if_alevar.h 2018-05-28 00:25:20 UTC (rev 10127)
+++ trunk/sys/dev/ale/if_alevar.h 2018-05-28 00:27:43 UTC (rev 10128)
@@ -1,3 +1,4 @@
+/* $MidnightBSD$ */
/*-
* Copyright (c) 2008, Pyun YongHyeon <yongari at FreeBSD.org>
* All rights reserved.
@@ -24,7 +25,7 @@
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*
- * $MidnightBSD$
+ * $FreeBSD: stable/10/sys/dev/ale/if_alevar.h 264442 2014-04-14 04:51:59Z yongari $
*/
#ifndef _IF_ALEVAR_H
@@ -40,7 +41,7 @@
#define ALE_TSO_MAXSEGSIZE 4096
#define ALE_TSO_MAXSIZE (65535 + sizeof(struct ether_vlan_header))
-#define ALE_MAXTXSEGS 32
+#define ALE_MAXTXSEGS 35
#define ALE_ADDR_LO(x) ((uint64_t) (x) & 0xFFFFFFFF)
#define ALE_ADDR_HI(x) ((uint64_t) (x) >> 32)
Modified: trunk/sys/dev/amdtemp/amdtemp.c
===================================================================
--- trunk/sys/dev/amdtemp/amdtemp.c 2018-05-28 00:25:20 UTC (rev 10127)
+++ trunk/sys/dev/amdtemp/amdtemp.c 2018-05-28 00:27:43 UTC (rev 10128)
@@ -1,3 +1,4 @@
+/* $MidnightBSD$ */
/*-
* Copyright (c) 2008, 2009 Rui Paulo <rpaulo at FreeBSD.org>
* Copyright (c) 2009 Norikatsu Shigemura <nork at FreeBSD.org>
@@ -32,7 +33,7 @@
*/
#include <sys/cdefs.h>
-__FBSDID("$FreeBSD: stable/11/sys/dev/amdtemp/amdtemp.c 300421 2016-05-22 13:58:32Z loos $");
+__FBSDID("$FreeBSD: stable/10/sys/dev/amdtemp/amdtemp.c 300520 2016-05-23 16:37:04Z loos $");
#include <sys/param.h>
#include <sys/bus.h>
@@ -505,7 +506,7 @@
return (error);
}
-#define AMDTEMP_ZERO_C_TO_K 2731
+#define AMDTEMP_ZERO_C_TO_K 2732
static int32_t
amdtemp_gettemp0f(device_t dev, amdsensor_t sensor)
Modified: trunk/sys/dev/amr/amr.c
===================================================================
--- trunk/sys/dev/amr/amr.c 2018-05-28 00:25:20 UTC (rev 10127)
+++ trunk/sys/dev/amr/amr.c 2018-05-28 00:27:43 UTC (rev 10128)
@@ -1,3 +1,4 @@
+/* $MidnightBSD$ */
/*-
* Copyright (c) 1999,2000 Michael Smith
* Copyright (c) 2000 BSDi
@@ -56,7 +57,7 @@
*/
#include <sys/cdefs.h>
-__MBSDID("$MidnightBSD$");
+__FBSDID("$FreeBSD: stable/10/sys/dev/amr/amr.c 241228 2012-10-05 15:52:31Z jhb $");
/*
* Driver for the AMI MegaRaid family of controllers.
@@ -139,11 +140,6 @@
static void amr_abort_load(struct amr_command *ac);
/*
- * Status monitoring
- */
-static void amr_periodic(void *data);
-
-/*
* Interface-specific shims
*/
static int amr_quartz_submit_command(struct amr_command *ac);
@@ -348,11 +344,6 @@
/* interrupts will be enabled before we do anything more */
sc->amr_state |= AMR_STATE_INTEN;
- /*
- * Start the timeout routine.
- */
-/* sc->amr_timeout = timeout(amr_periodic, sc, hz);*/
-
return;
}
@@ -391,9 +382,6 @@
if (sc->amr_pass != NULL)
device_delete_child(sc->amr_dev, sc->amr_pass);
- /* cancel status timeout */
- untimeout(amr_periodic, sc, sc->amr_timeout);
-
/* throw away any command buffers */
while ((acc = TAILQ_FIRST(&sc->amr_cmd_clusters)) != NULL) {
TAILQ_REMOVE(&sc->amr_cmd_clusters, acc, acc_link);
@@ -961,31 +949,6 @@
/********************************************************************************
********************************************************************************
- Status Monitoring
- ********************************************************************************
- ********************************************************************************/
-
-/********************************************************************************
- * Perform a periodic check of the controller status
- */
-static void
-amr_periodic(void *data)
-{
- struct amr_softc *sc = (struct amr_softc *)data;
-
- debug_called(2);
-
- /* XXX perform periodic status checks here */
-
- /* compensate for missed interrupts */
- amr_done(sc);
-
- /* reschedule */
- sc->amr_timeout = timeout(amr_periodic, sc, hz);
-}
-
-/********************************************************************************
- ********************************************************************************
Command Wrappers
********************************************************************************
********************************************************************************/
Modified: trunk/sys/dev/amr/amr_cam.c
===================================================================
--- trunk/sys/dev/amr/amr_cam.c 2018-05-28 00:25:20 UTC (rev 10127)
+++ trunk/sys/dev/amr/amr_cam.c 2018-05-28 00:27:43 UTC (rev 10128)
@@ -1,3 +1,4 @@
+/* $MidnightBSD$ */
/*-
* Copyright (c) 2000 Michael Smith
* Copyright (c) 2000 BSDi
@@ -55,7 +56,7 @@
*/
#include <sys/cdefs.h>
-__MBSDID("$MidnightBSD$");
+__FBSDID("$FreeBSD: stable/10/sys/dev/amr/amr_cam.c 315813 2017-03-23 06:41:13Z mav $");
#include <sys/param.h>
#include <sys/systm.h>
@@ -274,12 +275,9 @@
* address
*/
if ((ccbh->flags & CAM_DIR_MASK) != CAM_DIR_NONE) {
- if (ccbh->flags & CAM_DATA_PHYS)
+ if ((ccbh->flags & CAM_DATA_MASK) != CAM_DATA_VADDR)
/* we can't map it */
ccbh->status = CAM_REQ_INVALID;
- if (ccbh->flags & CAM_SCATTER_VALID)
- /* we want to do the s/g setup */
- ccbh->status = CAM_REQ_INVALID;
}
/*
@@ -326,9 +324,9 @@
cpi->max_target = AMR_MAX_TARGETS;
cpi->max_lun = 0 /* AMR_MAX_LUNS*/;
cpi->initiator_id = 7; /* XXX variable? */
- strncpy(cpi->sim_vid, "FreeBSD", SIM_IDLEN);
- strncpy(cpi->hba_vid, "LSI", HBA_IDLEN);
- strncpy(cpi->dev_name, cam_sim_name(sim), DEV_IDLEN);
+ strlcpy(cpi->sim_vid, "FreeBSD", SIM_IDLEN);
+ strlcpy(cpi->hba_vid, "LSI", HBA_IDLEN);
+ strlcpy(cpi->dev_name, cam_sim_name(sim), DEV_IDLEN);
cpi->unit_number = cam_sim_unit(sim);
cpi->bus_id = cam_sim_bus(sim);
cpi->base_transfer_speed = 132 * 1024; /* XXX */
Modified: trunk/sys/dev/amr/amr_disk.c
===================================================================
--- trunk/sys/dev/amr/amr_disk.c 2018-05-28 00:25:20 UTC (rev 10127)
+++ trunk/sys/dev/amr/amr_disk.c 2018-05-28 00:27:43 UTC (rev 10128)
@@ -1,3 +1,4 @@
+/* $MidnightBSD$ */
/*-
* Copyright (c) 1999 Jonathan Lemon
* Copyright (c) 1999, 2000 Michael Smith
@@ -56,7 +57,7 @@
*/
#include <sys/cdefs.h>
-__MBSDID("$MidnightBSD$");
+__FBSDID("$FreeBSD: stable/10/sys/dev/amr/amr_disk.c 163834 2006-10-31 21:19:25Z pjd $");
/*
* Disk driver for AMI MegaRaid controllers
Modified: trunk/sys/dev/amr/amr_linux.c
===================================================================
--- trunk/sys/dev/amr/amr_linux.c 2018-05-28 00:25:20 UTC (rev 10127)
+++ trunk/sys/dev/amr/amr_linux.c 2018-05-28 00:27:43 UTC (rev 10128)
@@ -1,3 +1,4 @@
+/* $MidnightBSD$ */
/*-
* Copyright (c) 2005 Paul Saab
* All rights reserved.
@@ -26,11 +27,11 @@
*/
#include <sys/cdefs.h>
-__MBSDID("$MidnightBSD$");
+__FBSDID("$FreeBSD: stable/10/sys/dev/amr/amr_linux.c 280258 2015-03-19 13:37:36Z rwatson $");
#include <sys/param.h>
#include <sys/systm.h>
-#include <sys/capability.h>
+#include <sys/capsicum.h>
#include <sys/conf.h>
#include <sys/kernel.h>
#include <sys/module.h>
@@ -72,10 +73,12 @@
static int
amr_linux_ioctl(struct thread *p, struct linux_ioctl_args *args)
{
+ cap_rights_t rights;
struct file *fp;
int error;
- if ((error = fget(p, args->fd, CAP_IOCTL, &fp)) != 0)
+ error = fget(p, args->fd, cap_rights_init(&rights, CAP_IOCTL), &fp);
+ if (error != 0)
return (error);
error = fo_ioctl(fp, args->cmd, (caddr_t)args->arg, p->td_ucred, p);
fdrop(fp, p);
Modified: trunk/sys/dev/amr/amr_pci.c
===================================================================
--- trunk/sys/dev/amr/amr_pci.c 2018-05-28 00:25:20 UTC (rev 10127)
+++ trunk/sys/dev/amr/amr_pci.c 2018-05-28 00:27:43 UTC (rev 10128)
@@ -1,3 +1,4 @@
+/* $MidnightBSD$ */
/*-
* Copyright (c) 1999,2000 Michael Smith
* Copyright (c) 2000 BSDi
@@ -55,7 +56,7 @@
*/
#include <sys/cdefs.h>
-__MBSDID("$MidnightBSD$");
+__FBSDID("$FreeBSD: stable/10/sys/dev/amr/amr_pci.c 281826 2015-04-21 11:27:50Z mav $");
#include <sys/param.h>
#include <sys/systm.h>
@@ -184,7 +185,6 @@
struct amr_softc *sc;
struct amr_ident *id;
int rid, rtype, error;
- u_int32_t command;
debug_called(1);
@@ -204,24 +204,8 @@
if ((id = amr_find_ident(dev)) == NULL)
return (ENXIO);
- command = pci_read_config(dev, PCIR_COMMAND, 1);
if (id->flags & AMR_ID_QUARTZ) {
- /*
- * Make sure we are going to be able to talk to this board.
- */
- if ((command & PCIM_CMD_MEMEN) == 0) {
- device_printf(dev, "memory window not available\n");
- return (ENXIO);
- }
sc->amr_type |= AMR_TYPE_QUARTZ;
- } else {
- /*
- * Make sure we are going to be able to talk to this board.
- */
- if ((command & PCIM_CMD_PORTEN) == 0) {
- device_printf(dev, "I/O window not available\n");
- return (ENXIO);
- }
}
if ((amr_force_sg32 == 0) && (id->flags & AMR_ID_DO_SG64) &&
@@ -231,11 +215,7 @@
}
/* force the busmaster enable bit on */
- if (!(command & PCIM_CMD_BUSMASTEREN)) {
- device_printf(dev, "busmaster bit not set, enabling\n");
- command |= PCIM_CMD_BUSMASTEREN;
- pci_write_config(dev, PCIR_COMMAND, command, 2);
- }
+ pci_enable_busmaster(dev);
/*
* Allocate the PCI register window.
@@ -282,7 +262,8 @@
BUS_SPACE_MAXADDR_32BIT, /* lowaddr */
BUS_SPACE_MAXADDR, /* highaddr */
NULL, NULL, /* filter, filterarg */
- MAXBSIZE, AMR_NSEG, /* maxsize, nsegments */
+ BUS_SPACE_MAXSIZE, /* maxsize */
+ BUS_SPACE_UNRESTRICTED, /* nsegments */
BUS_SPACE_MAXSIZE_32BIT, /* maxsegsize */
0, /* flags */
NULL, NULL, /* lockfunc, lockarg */
@@ -299,8 +280,9 @@
BUS_SPACE_MAXADDR_32BIT, /* lowaddr */
BUS_SPACE_MAXADDR, /* highaddr */
NULL, NULL, /* filter, filterarg */
- MAXBSIZE, AMR_NSEG, /* maxsize, nsegments */
- MAXBSIZE, /* maxsegsize */
+ DFLTPHYS, /* maxsize */
+ AMR_NSEG, /* nsegments */
+ BUS_SPACE_MAXSIZE_32BIT, /* maxsegsize */
0, /* flags */
busdma_lock_mutex, /* lockfunc */
&sc->amr_list_lock, /* lockarg */
@@ -314,8 +296,9 @@
BUS_SPACE_MAXADDR, /* lowaddr */
BUS_SPACE_MAXADDR, /* highaddr */
NULL, NULL, /* filter, filterarg */
- MAXBSIZE, AMR_NSEG, /* maxsize, nsegments */
- MAXBSIZE, /* maxsegsize */
+ DFLTPHYS, /* maxsize */
+ AMR_NSEG, /* nsegments */
+ BUS_SPACE_MAXSIZE_32BIT, /* maxsegsize */
0, /* flags */
busdma_lock_mutex, /* lockfunc */
&sc->amr_list_lock, /* lockarg */
@@ -339,11 +322,11 @@
/*
* Build the scatter/gather buffers.
*/
- if (amr_sglist_map(sc))
+ if ((error = amr_sglist_map(sc)) != 0)
goto out;
debug(2, "s/g list mapped");
- if (amr_ccb_map(sc))
+ if ((error = amr_ccb_map(sc)) != 0)
goto out;
debug(2, "ccb mapped");
Modified: trunk/sys/dev/amr/amr_tables.h
===================================================================
--- trunk/sys/dev/amr/amr_tables.h 2018-05-28 00:25:20 UTC (rev 10127)
+++ trunk/sys/dev/amr/amr_tables.h 2018-05-28 00:27:43 UTC (rev 10128)
@@ -1,3 +1,4 @@
+/* $MidnightBSD$ */
/*-
* Copyright (c) 2000 Michael Smith
* Copyright (c) 2000 BSDi
@@ -53,7 +54,7 @@
* SUCH DAMAGE.
*
*
- * $MidnightBSD$
+ * $FreeBSD: stable/10/sys/dev/amr/amr_tables.h 106225 2002-10-30 22:00:11Z emoore $
*/
/*
Modified: trunk/sys/dev/amr/amrio.h
===================================================================
--- trunk/sys/dev/amr/amrio.h 2018-05-28 00:25:20 UTC (rev 10127)
+++ trunk/sys/dev/amr/amrio.h 2018-05-28 00:27:43 UTC (rev 10128)
@@ -1,3 +1,4 @@
+/* $MidnightBSD$ */
/*-
* Copyright (c) 1999 Michael Smith
* All rights reserved.
@@ -52,7 +53,7 @@
* SUCH DAMAGE.
*
*
- * $MidnightBSD$
+ * $FreeBSD: stable/10/sys/dev/amr/amrio.h 153409 2005-12-14 03:26:49Z scottl $
*/
/*
Modified: trunk/sys/dev/amr/amrreg.h
===================================================================
--- trunk/sys/dev/amr/amrreg.h 2018-05-28 00:25:20 UTC (rev 10127)
+++ trunk/sys/dev/amr/amrreg.h 2018-05-28 00:27:43 UTC (rev 10128)
@@ -1,3 +1,4 @@
+/* $MidnightBSD$ */
/*-
* Copyright (c) 1999,2000 Michael Smith
* Copyright (c) 2000 BSDi
@@ -53,7 +54,7 @@
* SUCH DAMAGE.
*
*
- * $MidnightBSD$
+ * $FreeBSD: stable/10/sys/dev/amr/amrreg.h 176041 2008-02-06 14:26:31Z scottl $
*/
/********************************************************************************
Modified: trunk/sys/dev/amr/amrvar.h
===================================================================
--- trunk/sys/dev/amr/amrvar.h 2018-05-28 00:25:20 UTC (rev 10127)
+++ trunk/sys/dev/amr/amrvar.h 2018-05-28 00:27:43 UTC (rev 10128)
@@ -1,3 +1,4 @@
+/* $MidnightBSD$ */
/*-
* Copyright (c) 1999,2000 Michael Smith
* Copyright (c) 2000 BSDi
@@ -53,7 +54,7 @@
* SUCH DAMAGE.
*
*
- * $MidnightBSD$
+ * $FreeBSD: stable/10/sys/dev/amr/amrvar.h 239939 2012-08-31 09:42:46Z scottl $
*/
#include <geom/geom_disk.h>
@@ -256,7 +257,6 @@
device_t amr_pass;
int (*amr_cam_command)(struct amr_softc *sc, struct amr_command **acp);
struct intr_config_hook amr_ich; /* wait-for-interrupts probe hook */
- struct callout_handle amr_timeout; /* periodic status check */
int amr_allow_vol_config;
int amr_linux_no_adapters;
int amr_ld_del_supported;
Modified: trunk/sys/dev/an/if_aironet_ieee.h
===================================================================
--- trunk/sys/dev/an/if_aironet_ieee.h 2018-05-28 00:25:20 UTC (rev 10127)
+++ trunk/sys/dev/an/if_aironet_ieee.h 2018-05-28 00:27:43 UTC (rev 10128)
@@ -1,4 +1,4 @@
-/* $MidnightBSD: src/sys/dev/an/if_aironet_ieee.h,v 1.2 2008/12/02 02:24:31 laffer1 Exp $ */
+/* $MidnightBSD$ */
/*-
* Copyright (c) 1997, 1998, 1999
* Bill Paul <wpaul at ctr.columbia.edu>. All rights reserved.
@@ -30,7 +30,7 @@
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
* THE POSSIBILITY OF SUCH DAMAGE.
*
- * $FreeBSD$
+ * $FreeBSD: stable/10/sys/dev/an/if_aironet_ieee.h 139749 2005-01-06 01:43:34Z imp $
*/
#ifndef _IF_AIRONET_IEEE_H
Modified: trunk/sys/dev/an/if_an.c
===================================================================
--- trunk/sys/dev/an/if_an.c 2018-05-28 00:25:20 UTC (rev 10127)
+++ trunk/sys/dev/an/if_an.c 2018-05-28 00:27:43 UTC (rev 10128)
@@ -39,7 +39,7 @@
*/
#include <sys/cdefs.h>
-__FBSDID("$FreeBSD$");
+__FBSDID("$FreeBSD: stable/10/sys/dev/an/if_an.c 303177 2016-07-22 03:26:01Z sbruno $");
/*
* The Aironet 4500/4800 series cards come in PCMCIA, ISA and PCI form.
@@ -358,6 +358,7 @@
CSR_WRITE_2(sc, AN_INT_EN(sc->mpi350), 0);
CSR_WRITE_2(sc, AN_EVENT_ACK(sc->mpi350), 0xFFFF);
+ sc->an_dev = dev;
mtx_init(&sc->an_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK,
MTX_DEF);
AN_LOCK(sc);
@@ -686,6 +687,9 @@
device_printf(sc->an_dev, "can not if_alloc()\n");
goto fail;
}
+ ifp->if_softc = sc;
+ if_initname(ifp, device_get_name(sc->an_dev),
+ device_get_unit(sc->an_dev));
sc->an_gone = 0;
sc->an_associated = 0;
@@ -759,10 +763,6 @@
#endif
AN_UNLOCK(sc);
- ifp->if_softc = sc;
- if_initname(ifp, device_get_name(sc->an_dev),
- device_get_unit(sc->an_dev));
- ifp->if_mtu = ETHERMTU;
ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
ifp->if_ioctl = an_ioctl;
ifp->if_start = an_start;
@@ -1389,7 +1389,7 @@
an_cmd(sc, AN_CMD_NOOP2, 0);
if (an_cmd(sc, AN_CMD_FORCE_SYNCLOSS, 0) == ETIMEDOUT)
- if_printf(sc->an_ifp, "reset failed\n");
+ device_printf(sc->an_dev, "reset failed\n");
an_cmd(sc, AN_CMD_DISABLE, 0);
@@ -3778,6 +3778,9 @@
return ENOBUFS;
break;
case AIROFLSHGCHR: /* Get char from aux */
+ if (l_ioctl->len > sizeof(sc->areq)) {
+ return -EINVAL;
+ }
AN_UNLOCK(sc);
status = copyin(l_ioctl->data, &sc->areq, l_ioctl->len);
AN_LOCK(sc);
@@ -3789,6 +3792,9 @@
else
return -1;
case AIROFLSHPCHR: /* Send char to card. */
+ if (l_ioctl->len > sizeof(sc->areq)) {
+ return -EINVAL;
+ }
AN_UNLOCK(sc);
status = copyin(l_ioctl->data, &sc->areq, l_ioctl->len);
AN_LOCK(sc);
Modified: trunk/sys/dev/an/if_an_isa.c
===================================================================
--- trunk/sys/dev/an/if_an_isa.c 2018-05-28 00:25:20 UTC (rev 10127)
+++ trunk/sys/dev/an/if_an_isa.c 2018-05-28 00:27:43 UTC (rev 10128)
@@ -1,4 +1,4 @@
-/* $MidnightBSD: src/sys/dev/an/if_an_isa.c,v 1.2 2008/12/02 02:24:31 laffer1 Exp $ */
+/* $MidnightBSD$ */
/*-
* Copyright (c) 1997, 1998, 1999
* Bill Paul <wpaul at ctr.columbia.edu>. All rights reserved.
@@ -39,7 +39,7 @@
*/
#include <sys/cdefs.h>
-__FBSDID("$FreeBSD$");
+__FBSDID("$FreeBSD: stable/10/sys/dev/an/if_an_isa.c 199756 2009-11-24 16:54:54Z jhb $");
#include "opt_inet.h"
Modified: trunk/sys/dev/an/if_an_pccard.c
===================================================================
--- trunk/sys/dev/an/if_an_pccard.c 2018-05-28 00:25:20 UTC (rev 10127)
+++ trunk/sys/dev/an/if_an_pccard.c 2018-05-28 00:27:43 UTC (rev 10128)
@@ -1,4 +1,4 @@
-/* $MidnightBSD: src/sys/dev/an/if_an_pccard.c,v 1.2 2008/12/02 02:24:31 laffer1 Exp $ */
+/* $MidnightBSD$ */
/*-
* Copyright (c) 1997, 1998, 1999
* Bill Paul <wpaul at ctr.columbia.edu>. All rights reserved.
@@ -39,7 +39,7 @@
*/
#include <sys/cdefs.h>
-__FBSDID("$FreeBSD$");
+__FBSDID("$FreeBSD: stable/10/sys/dev/an/if_an_pccard.c 265614 2014-05-07 21:38:33Z gavin $");
#include "opt_inet.h"
@@ -142,8 +142,6 @@
an_alloc_irq(dev, sc->irq_rid, 0);
- sc->an_dev = dev;
-
error = an_attach(sc, flags);
if (error)
goto fail;
Modified: trunk/sys/dev/an/if_an_pci.c
===================================================================
--- trunk/sys/dev/an/if_an_pci.c 2018-05-28 00:25:20 UTC (rev 10127)
+++ trunk/sys/dev/an/if_an_pci.c 2018-05-28 00:27:43 UTC (rev 10128)
@@ -1,4 +1,4 @@
-/* $MidnightBSD: src/sys/dev/an/if_an_pci.c,v 1.2 2008/12/02 02:24:31 laffer1 Exp $ */
+/* $MidnightBSD$ */
/*-
* Copyright (c) 1997, 1998, 1999
* Bill Paul <wpaul at ctr.columbia.edu>. All rights reserved.
@@ -32,7 +32,7 @@
*/
#include <sys/cdefs.h>
-__FBSDID("$FreeBSD$");
+__FBSDID("$FreeBSD: stable/10/sys/dev/an/if_an_pci.c 254263 2013-08-12 23:30:01Z scottl $");
/*
* This is a PCI shim for the Aironet PC4500/4800 wireless network
@@ -142,7 +142,6 @@
an_attach_pci(dev)
device_t dev;
{
- u_int32_t command;
struct an_softc *sc;
int flags, error = 0;
@@ -154,19 +153,6 @@
sc->mpi350 = 1;
sc->port_rid = PCIR_BAR(0);
} else {
- /*
- * Map control/status registers.
- */
- command = pci_read_config(dev, PCIR_COMMAND, 4);
- command |= PCIM_CMD_PORTEN;
- pci_write_config(dev, PCIR_COMMAND, command, 4);
- command = pci_read_config(dev, PCIR_COMMAND, 4);
-
- if (!(command & PCIM_CMD_PORTEN)) {
- device_printf(dev, "failed to enable I/O ports!\n");
- error = ENXIO;
- goto fail;
- }
sc->port_rid = AN_PCI_LOIO;
}
error = an_alloc_port(dev, sc->port_rid, 1);
Modified: trunk/sys/dev/an/if_anreg.h
===================================================================
--- trunk/sys/dev/an/if_anreg.h 2018-05-28 00:25:20 UTC (rev 10127)
+++ trunk/sys/dev/an/if_anreg.h 2018-05-28 00:27:43 UTC (rev 10128)
@@ -1,4 +1,4 @@
-/* $MidnightBSD: src/sys/dev/an/if_anreg.h,v 1.2 2008/12/02 02:24:31 laffer1 Exp $ */
+/* $MidnightBSD$ */
/*-
* Copyright (c) 1997, 1998, 1999
* Bill Paul <wpaul at ctr.columbia.edu>. All rights reserved.
@@ -30,7 +30,7 @@
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
* THE POSSIBILITY OF SUCH DAMAGE.
*
- * $FreeBSD$
+ * $FreeBSD: stable/10/sys/dev/an/if_anreg.h 199757 2009-11-24 16:57:35Z jhb $
*/
#define AN_TIMEOUT 65536
Modified: trunk/sys/dev/arcmsr/arcmsr.c
===================================================================
--- trunk/sys/dev/arcmsr/arcmsr.c 2018-05-28 00:25:20 UTC (rev 10127)
+++ trunk/sys/dev/arcmsr/arcmsr.c 2018-05-28 00:27:43 UTC (rev 10128)
@@ -1,3 +1,4 @@
+/* $MidnightBSD$ */
/*
********************************************************************************
** OS : FreeBSD
@@ -35,49 +36,55 @@
********************************************************************************
** History
**
-** REV# DATE NAME DESCRIPTION
-** 1.00.00.00 03/31/2004 Erich Chen First release
-** 1.20.00.02 11/29/2004 Erich Chen bug fix with arcmsr_bus_reset when PHY error
-** 1.20.00.03 04/19/2005 Erich Chen add SATA 24 Ports adapter type support
-** clean unused function
-** 1.20.00.12 09/12/2005 Erich Chen bug fix with abort command handling,
-** firmware version check
-** and firmware update notify for hardware bug fix
-** handling if none zero high part physical address
-** of srb resource
-** 1.20.00.13 08/18/2006 Erich Chen remove pending srb and report busy
-** add iop message xfer
-** with scsi pass-through command
-** add new device id of sas raid adapters
-** code fit for SPARC64 & PPC
-** 1.20.00.14 02/05/2007 Erich Chen bug fix for incorrect ccb_h.status report
-** and cause g_vfs_done() read write error
-** 1.20.00.15 10/10/2007 Erich Chen support new RAID adapter type ARC120x
-** 1.20.00.16 10/10/2009 Erich Chen Bug fix for RAID adapter type ARC120x
-** bus_dmamem_alloc() with BUS_DMA_ZERO
-** 1.20.00.17 07/15/2010 Ching Huang Added support ARC1880
-** report CAM_DEV_NOT_THERE instead of CAM_SEL_TIMEOUT when device failed,
-** prevent cam_periph_error removing all LUN devices of one Target id
-** for any one LUN device failed
-** 1.20.00.18 10/14/2010 Ching Huang Fixed "inquiry data fails comparion at DV1 step"
-** 10/25/2010 Ching Huang Fixed bad range input in bus_alloc_resource for ADAPTER_TYPE_B
-** 1.20.00.19 11/11/2010 Ching Huang Fixed arcmsr driver prevent arcsas support for Areca SAS HBA ARC13x0
-** 1.20.00.20 12/08/2010 Ching Huang Avoid calling atomic_set_int function
-** 1.20.00.21 02/08/2011 Ching Huang Implement I/O request timeout
-** 02/14/2011 Ching Huang Modified pktRequestCount
-** 1.20.00.21 03/03/2011 Ching Huang if a command timeout, then wait its ccb back before free it
-** 1.20.00.22 07/04/2011 Ching Huang Fixed multiple MTX panic
-** 1.20.00.23 10/28/2011 Ching Huang Added TIMEOUT_DELAY in case of too many HDDs need to start
-** 1.20.00.23 11/08/2011 Ching Huang Added report device transfer speed
-** 1.20.00.23 01/30/2012 Ching Huang Fixed Request requeued and Retrying command
-** 1.20.00.24 06/11/2012 Ching Huang Fixed return sense data condition
-** 1.20.00.25 08/17/2012 Ching Huang Fixed hotplug device no function on type A adapter
-** 1.20.00.26 12/14/2012 Ching Huang Added support ARC1214,1224
+** REV# DATE NAME DESCRIPTION
+** 1.00.00.00 03/31/2004 Erich Chen First release
+** 1.20.00.02 11/29/2004 Erich Chen bug fix with arcmsr_bus_reset when PHY error
+** 1.20.00.03 04/19/2005 Erich Chen add SATA 24 Ports adapter type support
+** clean unused function
+** 1.20.00.12 09/12/2005 Erich Chen bug fix with abort command handling,
+** firmware version check
+** and firmware update notify for hardware bug fix
+** handling if none zero high part physical address
+** of srb resource
+** 1.20.00.13 08/18/2006 Erich Chen remove pending srb and report busy
+** add iop message xfer
+** with scsi pass-through command
+** add new device id of sas raid adapters
+** code fit for SPARC64 & PPC
+** 1.20.00.14 02/05/2007 Erich Chen bug fix for incorrect ccb_h.status report
+** and cause g_vfs_done() read write error
+** 1.20.00.15 10/10/2007 Erich Chen support new RAID adapter type ARC120x
+** 1.20.00.16 10/10/2009 Erich Chen Bug fix for RAID adapter type ARC120x
+** bus_dmamem_alloc() with BUS_DMA_ZERO
+** 1.20.00.17 07/15/2010 Ching Huang Added support ARC1880
+** report CAM_DEV_NOT_THERE instead of CAM_SEL_TIMEOUT when device failed,
+** prevent cam_periph_error removing all LUN devices of one Target id
+** for any one LUN device failed
+** 1.20.00.18 10/14/2010 Ching Huang Fixed "inquiry data fails comparion at DV1 step"
+** 10/25/2010 Ching Huang Fixed bad range input in bus_alloc_resource for ADAPTER_TYPE_B
+** 1.20.00.19 11/11/2010 Ching Huang Fixed arcmsr driver prevent arcsas support for Areca SAS HBA ARC13x0
+** 1.20.00.20 12/08/2010 Ching Huang Avoid calling atomic_set_int function
+** 1.20.00.21 02/08/2011 Ching Huang Implement I/O request timeout
+** 02/14/2011 Ching Huang Modified pktRequestCount
+** 1.20.00.21 03/03/2011 Ching Huang if a command timeout, then wait its ccb back before free it
+** 1.20.00.22 07/04/2011 Ching Huang Fixed multiple MTX panic
+** 1.20.00.23 10/28/2011 Ching Huang Added TIMEOUT_DELAY in case of too many HDDs need to start
+** 1.20.00.23 11/08/2011 Ching Huang Added report device transfer speed
+** 1.20.00.23 01/30/2012 Ching Huang Fixed Request requeued and Retrying command
+** 1.20.00.24 06/11/2012 Ching Huang Fixed return sense data condition
+** 1.20.00.25 08/17/2012 Ching Huang Fixed hotplug device no function on type A adapter
+** 1.20.00.26 12/14/2012 Ching Huang Added support ARC1214,1224,1264,1284
+** 1.20.00.27 05/06/2013 Ching Huang Fixed out standing cmd full on ARC-12x4
+** 1.20.00.28 09/13/2013 Ching Huang Removed recursive mutex in arcmsr_abort_dr_ccbs
+** 1.20.00.29 12/18/2013 Ching Huang Change simq allocation number, support ARC1883
+** 1.30.00.00 11/30/2015 Ching Huang Added support ARC1203
+** 1.40.00.00 07/11/2017 Ching Huang Added support ARC1884
+** 1.40.00.01 10/30/2017 Ching Huang Fixed release memory resource
******************************************************************************************
*/
#include <sys/cdefs.h>
-__MBSDID("$MidnightBSD$");
+__FBSDID("$FreeBSD: stable/10/sys/dev/arcmsr/arcmsr.c 326088 2017-11-22 06:36:55Z delphij $");
#if 0
#define ARCMSR_DEBUG1 1
@@ -123,15 +130,15 @@
**************************************************************************
*/
#if __FreeBSD_version >= 500005
- #include <sys/selinfo.h>
- #include <sys/mutex.h>
- #include <sys/endian.h>
- #include <dev/pci/pcivar.h>
- #include <dev/pci/pcireg.h>
+ #include <sys/selinfo.h>
+ #include <sys/mutex.h>
+ #include <sys/endian.h>
+ #include <dev/pci/pcivar.h>
+ #include <dev/pci/pcireg.h>
#else
- #include <sys/select.h>
- #include <pci/pcivar.h>
- #include <pci/pcireg.h>
+ #include <sys/select.h>
+ #include <pci/pcivar.h>
+ #include <pci/pcireg.h>
#endif
#if !defined(CAM_NEW_TRAN_CODE) && __FreeBSD_version >= 700025
@@ -144,7 +151,7 @@
#define arcmsr_callout_init(a) callout_init(a);
#endif
-#define ARCMSR_DRIVER_VERSION "Driver Version 1.20.00.26 2013-01-08"
+#define ARCMSR_DRIVER_VERSION "arcmsr version 1.40.00.01 2017-10-30"
#include <dev/arcmsr/arcmsr.h>
/*
**************************************************************************
@@ -178,9 +185,11 @@
static int arcmsr_resume(device_t dev);
static int arcmsr_suspend(device_t dev);
static void arcmsr_rescanLun_cb(struct cam_periph *periph, union ccb *ccb);
-static void arcmsr_polling_devmap(void *arg);
-static void arcmsr_srb_timeout(void *arg);
+static void arcmsr_polling_devmap(void *arg);
+static void arcmsr_srb_timeout(void *arg);
static void arcmsr_hbd_postqueue_isr(struct AdapterControlBlock *acb);
+static void arcmsr_hbe_postqueue_isr(struct AdapterControlBlock *acb);
+static void arcmsr_teardown_intr(device_t dev, struct AdapterControlBlock *acb);
#ifdef ARCMSR_DEBUG1
static void arcmsr_dump_data(struct AdapterControlBlock *acb);
#endif
@@ -217,11 +226,11 @@
{ 0, 0 }
#endif
};
-
+
static driver_t arcmsr_driver={
"arcmsr", arcmsr_methods, sizeof(struct AdapterControlBlock)
};
-
+
static devclass_t arcmsr_devclass;
DRIVER_MODULE(arcmsr, pci, arcmsr_driver, arcmsr_devclass, 0, 0);
MODULE_DEPEND(arcmsr, pci, 1, 1, 1);
@@ -244,21 +253,21 @@
};
#else
#define ARCMSR_CDEV_MAJOR 180
-
+
static struct cdevsw arcmsr_cdevsw = {
- arcmsr_open, /* open */
- arcmsr_close, /* close */
- noread, /* read */
- nowrite, /* write */
- arcmsr_ioctl, /* ioctl */
- nopoll, /* poll */
- nommap, /* mmap */
- nostrategy, /* strategy */
- "arcmsr", /* name */
- ARCMSR_CDEV_MAJOR, /* major */
- nodump, /* dump */
- nopsize, /* psize */
- 0 /* flags */
+ arcmsr_open, /* open */
+ arcmsr_close, /* close */
+ noread, /* read */
+ nowrite, /* write */
+ arcmsr_ioctl, /* ioctl */
+ nopoll, /* poll */
+ nommap, /* mmap */
+ nostrategy, /* strategy */
+ "arcmsr", /* name */
+ ARCMSR_CDEV_MAJOR, /* major */
+ nodump, /* dump */
+ nopsize, /* psize */
+ 0 /* flags */
};
#endif
/*
@@ -265,10 +274,10 @@
**************************************************************************
**************************************************************************
*/
-#if __FreeBSD_version < 500005
+#if __FreeBSD_version < 500005
static int arcmsr_open(dev_t dev, int flags, int fmt, struct proc *proc)
#else
- #if __FreeBSD_version < 503000
+ #if __FreeBSD_version < 503000
static int arcmsr_open(dev_t dev, int flags, int fmt, struct thread *proc)
#else
static int arcmsr_open(struct cdev *dev, int flags, int fmt, struct thread *proc)
@@ -275,7 +284,7 @@
#endif
#endif
{
- #if __FreeBSD_version < 503000
+ #if __FreeBSD_version < 503000
struct AdapterControlBlock *acb = dev->si_drv1;
#else
int unit = dev2unit(dev);
@@ -290,10 +299,10 @@
**************************************************************************
**************************************************************************
*/
-#if __FreeBSD_version < 500005
+#if __FreeBSD_version < 500005
static int arcmsr_close(dev_t dev, int flags, int fmt, struct proc *proc)
#else
- #if __FreeBSD_version < 503000
+ #if __FreeBSD_version < 503000
static int arcmsr_close(dev_t dev, int flags, int fmt, struct thread *proc)
#else
static int arcmsr_close(struct cdev *dev, int flags, int fmt, struct thread *proc)
@@ -300,7 +309,7 @@
#endif
#endif
{
- #if __FreeBSD_version < 503000
+ #if __FreeBSD_version < 503000
struct AdapterControlBlock *acb = dev->si_drv1;
#else
int unit = dev2unit(dev);
@@ -315,10 +324,10 @@
**************************************************************************
**************************************************************************
*/
-#if __FreeBSD_version < 500005
+#if __FreeBSD_version < 500005
static int arcmsr_ioctl(dev_t dev, u_long ioctl_cmd, caddr_t arg, int flags, struct proc *proc)
#else
- #if __FreeBSD_version < 503000
+ #if __FreeBSD_version < 503000
static int arcmsr_ioctl(dev_t dev, u_long ioctl_cmd, caddr_t arg, int flags, struct thread *proc)
#else
static int arcmsr_ioctl(struct cdev *dev, u_long ioctl_cmd, caddr_t arg, int flags, struct thread *proc)
@@ -325,7 +334,7 @@
#endif
#endif
{
- #if __FreeBSD_version < 503000
+ #if __FreeBSD_version < 503000
struct AdapterControlBlock *acb = dev->si_drv1;
#else
int unit = dev2unit(dev);
@@ -344,7 +353,7 @@
static u_int32_t arcmsr_disable_allintr( struct AdapterControlBlock *acb)
{
u_int32_t intmask_org = 0;
-
+
switch (acb->adapter_type) {
case ACB_ADAPTER_TYPE_A: {
/* disable all outbound interrupt */
@@ -353,10 +362,11 @@
}
break;
case ACB_ADAPTER_TYPE_B: {
+ struct HBB_MessageUnit *phbbmu = (struct HBB_MessageUnit *)acb->pmu;
/* disable all outbound interrupt */
- intmask_org = CHIP_REG_READ32(HBB_DOORBELL,
- 0, iop2drv_doorbell_mask) & (~ARCMSR_IOP2DRV_MESSAGE_CMD_DONE); /* disable outbound message0 int */
- CHIP_REG_WRITE32(HBB_DOORBELL, 0, iop2drv_doorbell_mask, 0); /* disable all interrupt */
+ intmask_org = READ_CHIP_REG32(0, phbbmu->iop2drv_doorbell_mask)
+ & (~ARCMSR_IOP2DRV_MESSAGE_CMD_DONE); /* disable outbound message0 int */
+ WRITE_CHIP_REG32(0, phbbmu->iop2drv_doorbell_mask, 0); /* disable all interrupt */
}
break;
case ACB_ADAPTER_TYPE_C: {
@@ -371,6 +381,12 @@
CHIP_REG_WRITE32(HBD_MessageUnit, 0, pcief0_int_enable, ARCMSR_HBDMU_ALL_INT_DISABLE);
}
break;
+ case ACB_ADAPTER_TYPE_E: {
+ /* disable all outbound interrupt */
+ intmask_org = CHIP_REG_READ32(HBC_MessageUnit, 0, host_int_mask) ; /* disable outbound message0 int */
+ CHIP_REG_WRITE32(HBE_MessageUnit, 0, host_int_mask, intmask_org | ARCMSR_HBEMU_ALL_INTMASKENABLE);
+ }
+ break;
}
return (intmask_org);
}
@@ -381,7 +397,7 @@
static void arcmsr_enable_allintr( struct AdapterControlBlock *acb, u_int32_t intmask_org)
{
u_int32_t mask;
-
+
switch (acb->adapter_type) {
case ACB_ADAPTER_TYPE_A: {
/* enable outbound Post Queue, outbound doorbell Interrupt */
@@ -391,9 +407,10 @@
}
break;
case ACB_ADAPTER_TYPE_B: {
+ struct HBB_MessageUnit *phbbmu = (struct HBB_MessageUnit *)acb->pmu;
/* enable ARCMSR_IOP2DRV_MESSAGE_CMD_DONE */
mask = (ARCMSR_IOP2DRV_DATA_WRITE_OK|ARCMSR_IOP2DRV_DATA_READ_OK|ARCMSR_IOP2DRV_CDB_DONE|ARCMSR_IOP2DRV_MESSAGE_CMD_DONE);
- CHIP_REG_WRITE32(HBB_DOORBELL, 0, iop2drv_doorbell_mask, intmask_org | mask); /*1=interrupt enable, 0=interrupt disable*/
+ WRITE_CHIP_REG32(0, phbbmu->iop2drv_doorbell_mask, intmask_org | mask); /*1=interrupt enable, 0=interrupt disable*/
acb->outbound_int_enable = (intmask_org | mask) & 0x0000000f;
}
break;
@@ -412,6 +429,13 @@
acb->outbound_int_enable = mask;
}
break;
+ case ACB_ADAPTER_TYPE_E: {
+ /* enable outbound Post Queue, outbound doorbell Interrupt */
+ mask = ~(ARCMSR_HBEMU_OUTBOUND_DOORBELL_ISR | ARCMSR_HBEMU_OUTBOUND_POSTQUEUE_ISR);
+ CHIP_REG_WRITE32(HBE_MessageUnit, 0, host_int_mask, intmask_org & mask);
+ acb->outbound_int_enable = ~(intmask_org & mask) & 0x0000000f;
+ }
+ break;
}
}
/*
@@ -422,7 +446,7 @@
{
u_int32_t Index;
u_int8_t Retries = 0x00;
-
+
do {
for(Index=0; Index < 100; Index++) {
if(CHIP_REG_READ32(HBA_MessageUnit, 0, outbound_intstatus) & ARCMSR_MU_OUTBOUND_MESSAGE0_INT) {
@@ -442,12 +466,13 @@
{
u_int32_t Index;
u_int8_t Retries = 0x00;
-
+ struct HBB_MessageUnit *phbbmu = (struct HBB_MessageUnit *)acb->pmu;
+
do {
for(Index=0; Index < 100; Index++) {
- if(CHIP_REG_READ32(HBB_DOORBELL, 0, iop2drv_doorbell) & ARCMSR_IOP2DRV_MESSAGE_CMD_DONE) {
- CHIP_REG_WRITE32(HBB_DOORBELL, 0, iop2drv_doorbell, ARCMSR_MESSAGE_INT_CLEAR_PATTERN);/*clear interrupt*/
- CHIP_REG_WRITE32(HBB_DOORBELL, 0, drv2iop_doorbell, ARCMSR_DRV2IOP_END_OF_INTERRUPT);
+ if(READ_CHIP_REG32(0, phbbmu->iop2drv_doorbell) & ARCMSR_IOP2DRV_MESSAGE_CMD_DONE) {
+ WRITE_CHIP_REG32(0, phbbmu->iop2drv_doorbell, ARCMSR_MESSAGE_INT_CLEAR_PATTERN);/*clear interrupt*/
+ WRITE_CHIP_REG32(0, phbbmu->drv2iop_doorbell, ARCMSR_DRV2IOP_END_OF_INTERRUPT);
return TRUE;
}
UDELAY(10000);
@@ -463,7 +488,7 @@
{
u_int32_t Index;
u_int8_t Retries = 0x00;
-
+
do {
for(Index=0; Index < 100; Index++) {
if(CHIP_REG_READ32(HBC_MessageUnit, 0, outbound_doorbell) & ARCMSR_HBCMU_IOP2DRV_MESSAGE_CMD_DONE) {
@@ -483,7 +508,7 @@
{
u_int32_t Index;
u_int8_t Retries = 0x00;
-
+
do {
for(Index=0; Index < 100; Index++) {
if(CHIP_REG_READ32(HBD_MessageUnit, 0, outbound_doorbell) & ARCMSR_HBDMU_IOP2DRV_MESSAGE_CMD_DONE) {
@@ -496,6 +521,28 @@
return (FALSE);
}
/*
+**********************************************************************
+**********************************************************************
+*/
+static u_int8_t arcmsr_hbe_wait_msgint_ready(struct AdapterControlBlock *acb)
+{
+ u_int32_t Index, read_doorbell;
+ u_int8_t Retries = 0x00;
+
+ do {
+ for(Index=0; Index < 100; Index++) {
+ read_doorbell = CHIP_REG_READ32(HBE_MessageUnit, 0, iobound_doorbell);
+ if((read_doorbell ^ acb->in_doorbell) & ARCMSR_HBEMU_IOP2DRV_MESSAGE_CMD_DONE) {
+ CHIP_REG_WRITE32(HBE_MessageUnit, 0, host_int_status, 0);/*clear interrupt*/
+ acb->in_doorbell = read_doorbell;
+ return TRUE;
+ }
+ UDELAY(10000);
+ }/*max 1 seconds*/
+ }while(Retries++ < 20);/*max 20 sec*/
+ return (FALSE);
+}
+/*
************************************************************************
************************************************************************
*/
@@ -502,7 +549,7 @@
static void arcmsr_flush_hba_cache(struct AdapterControlBlock *acb)
{
int retry_count = 30;/* enlarge wait flush adapter cache time: 10 minute */
-
+
CHIP_REG_WRITE32(HBA_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_FLUSH_CACHE);
do {
if(arcmsr_hba_wait_msgint_ready(acb)) {
@@ -519,9 +566,9 @@
static void arcmsr_flush_hbb_cache(struct AdapterControlBlock *acb)
{
int retry_count = 30;/* enlarge wait flush adapter cache time: 10 minute */
-
- CHIP_REG_WRITE32(HBB_DOORBELL,
- 0, drv2iop_doorbell, ARCMSR_MESSAGE_FLUSH_CACHE);
+ struct HBB_MessageUnit *phbbmu = (struct HBB_MessageUnit *)acb->pmu;
+
+ WRITE_CHIP_REG32(0, phbbmu->drv2iop_doorbell, ARCMSR_MESSAGE_FLUSH_CACHE);
do {
if(arcmsr_hbb_wait_msgint_ready(acb)) {
break;
@@ -537,7 +584,7 @@
static void arcmsr_flush_hbc_cache(struct AdapterControlBlock *acb)
{
int retry_count = 30;/* enlarge wait flush adapter cache time: 10 minute */
-
+
CHIP_REG_WRITE32(HBC_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_FLUSH_CACHE);
CHIP_REG_WRITE32(HBC_MessageUnit, 0, inbound_doorbell, ARCMSR_HBCMU_DRV2IOP_MESSAGE_CMD_DONE);
do {
@@ -555,7 +602,7 @@
static void arcmsr_flush_hbd_cache(struct AdapterControlBlock *acb)
{
int retry_count = 30; /* enlarge wait flush adapter cache time: 10 minute */
-
+
CHIP_REG_WRITE32(HBD_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_FLUSH_CACHE);
do {
if(arcmsr_hbd_wait_msgint_ready(acb)) {
@@ -569,6 +616,25 @@
************************************************************************
************************************************************************
*/
+static void arcmsr_flush_hbe_cache(struct AdapterControlBlock *acb)
+{
+ int retry_count = 30;/* enlarge wait flush adapter cache time: 10 minute */
+
+ CHIP_REG_WRITE32(HBE_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_FLUSH_CACHE);
+ acb->out_doorbell ^= ARCMSR_HBEMU_DRV2IOP_MESSAGE_CMD_DONE;
+ CHIP_REG_WRITE32(HBE_MessageUnit, 0, iobound_doorbell, acb->out_doorbell);
+ do {
+ if(arcmsr_hbe_wait_msgint_ready(acb)) {
+ break;
+ } else {
+ retry_count--;
+ }
+ }while(retry_count != 0);
+}
+/*
+************************************************************************
+************************************************************************
+*/
static void arcmsr_flush_adapter_cache(struct AdapterControlBlock *acb)
{
switch (acb->adapter_type) {
@@ -588,6 +654,10 @@
arcmsr_flush_hbd_cache(acb);
}
break;
+ case ACB_ADAPTER_TYPE_E: {
+ arcmsr_flush_hbe_cache(acb);
+ }
+ break;
}
}
/*
@@ -597,7 +667,7 @@
static int arcmsr_suspend(device_t dev)
{
struct AdapterControlBlock *acb = device_get_softc(dev);
-
+
/* flush controller */
arcmsr_iop_parking(acb);
/* disable all outbound interrupt */
@@ -611,7 +681,7 @@
static int arcmsr_resume(device_t dev)
{
struct AdapterControlBlock *acb = device_get_softc(dev);
-
+
arcmsr_iop_init(acb);
return(0);
}
@@ -624,7 +694,7 @@
struct AdapterControlBlock *acb;
u_int8_t target_id, target_lun;
struct cam_sim *sim;
-
+
sim = (struct cam_sim *) cb_arg;
acb =(struct AdapterControlBlock *) cam_sim_softc(sim);
switch (code) {
@@ -647,7 +717,7 @@
static void arcmsr_report_sense_info(struct CommandControlBlock *srb)
{
union ccb *pccb = srb->pccb;
-
+
pccb->ccb_h.status |= CAM_SCSI_STATUS_ERROR;
pccb->csio.scsi_status = SCSI_STATUS_CHECK_COND;
if(pccb->csio.sense_len) {
@@ -675,7 +745,8 @@
*/
static void arcmsr_abort_hbb_allcmd(struct AdapterControlBlock *acb)
{
- CHIP_REG_WRITE32(HBB_DOORBELL, 0, drv2iop_doorbell, ARCMSR_MESSAGE_ABORT_CMD);
+ struct HBB_MessageUnit *phbbmu = (struct HBB_MessageUnit *)acb->pmu;
+ WRITE_CHIP_REG32(0, phbbmu->drv2iop_doorbell, ARCMSR_MESSAGE_ABORT_CMD);
if(!arcmsr_hbb_wait_msgint_ready(acb)) {
printf("arcmsr%d: wait 'abort all outstanding command' timeout \n", acb->pci_unit);
}
@@ -707,6 +778,19 @@
*********************************************************************
*********************************************************************
*/
+static void arcmsr_abort_hbe_allcmd(struct AdapterControlBlock *acb)
+{
+ CHIP_REG_WRITE32(HBE_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_ABORT_CMD);
+ acb->out_doorbell ^= ARCMSR_HBEMU_DRV2IOP_MESSAGE_CMD_DONE;
+ CHIP_REG_WRITE32(HBE_MessageUnit, 0, iobound_doorbell, acb->out_doorbell);
+ if(!arcmsr_hbe_wait_msgint_ready(acb)) {
+ printf("arcmsr%d: wait 'abort all outstanding command' timeout \n", acb->pci_unit);
+ }
+}
+/*
+*********************************************************************
+*********************************************************************
+*/
static void arcmsr_abort_allcmd(struct AdapterControlBlock *acb)
{
switch (acb->adapter_type) {
@@ -726,6 +810,10 @@
arcmsr_abort_hbd_allcmd(acb);
}
break;
+ case ACB_ADAPTER_TYPE_E: {
+ arcmsr_abort_hbe_allcmd(acb);
+ }
+ break;
}
}
/*
@@ -736,12 +824,12 @@
{
struct AdapterControlBlock *acb = srb->acb;
union ccb *pccb = srb->pccb;
-
+
if(srb->srb_flags & SRB_FLAG_TIMER_START)
callout_stop(&srb->ccb_callout);
if((pccb->ccb_h.flags & CAM_DIR_MASK) != CAM_DIR_NONE) {
bus_dmasync_op_t op;
-
+
if((pccb->ccb_h.flags & CAM_DIR_MASK) == CAM_DIR_IN) {
op = BUS_DMASYNC_POSTREAD;
} else {
@@ -753,7 +841,7 @@
if(stand_flag == 1) {
atomic_subtract_int(&acb->srboutstandingcount, 1);
if((acb->acb_flags & ACB_F_CAM_DEV_QFRZN) && (
- acb->srboutstandingcount < (acb->firm_numbers_queue -10))) {
+ acb->srboutstandingcount < (acb->maxOutstanding -10))) {
acb->acb_flags &= ~ACB_F_CAM_DEV_QFRZN;
pccb->ccb_h.status |= CAM_RELEASE_SIMQ;
}
@@ -770,7 +858,7 @@
static void arcmsr_report_srb_state(struct AdapterControlBlock *acb, struct CommandControlBlock *srb, u_int16_t error)
{
int target, lun;
-
+
target = srb->pccb->ccb_h.target_id;
lun = srb->pccb->ccb_h.target_lun;
if(error == FALSE) {
@@ -804,11 +892,11 @@
}
break;
default:
- printf("arcmsr%d: scsi id=%d lun=%d isr got command error done,but got unknow DeviceStatus=0x%x \n"
+ printf("arcmsr%d: scsi id=%d lun=%d isr got command error done,but got unknown DeviceStatus=0x%x \n"
, acb->pci_unit, target, lun ,srb->arcmsr_cdb.DeviceStatus);
acb->devstate[target][lun] = ARECA_RAID_GONE;
srb->pccb->ccb_h.status |= CAM_UNCOR_PARITY;
- /*unknow error or crc error just for retry*/
+ /*unknown error or crc error just for retry*/
arcmsr_srb_complete(srb, 1);
break;
}
@@ -821,15 +909,20 @@
static void arcmsr_drain_donequeue(struct AdapterControlBlock *acb, u_int32_t flag_srb, u_int16_t error)
{
struct CommandControlBlock *srb;
-
+
/* check if command done with no error*/
switch (acb->adapter_type) {
+ case ACB_ADAPTER_TYPE_A:
+ case ACB_ADAPTER_TYPE_B:
+ srb = (struct CommandControlBlock *)(acb->vir2phy_offset+(flag_srb << 5));/*frame must be 32 bytes aligned*/
+ break;
case ACB_ADAPTER_TYPE_C:
case ACB_ADAPTER_TYPE_D:
srb = (struct CommandControlBlock *)(acb->vir2phy_offset+(flag_srb & 0xFFFFFFE0)); /*frame must be 32 bytes aligned*/
break;
- case ACB_ADAPTER_TYPE_A:
- case ACB_ADAPTER_TYPE_B:
+ case ACB_ADAPTER_TYPE_E:
+ srb = acb->psrb_pool[flag_srb];
+ break;
default:
srb = (struct CommandControlBlock *)(acb->vir2phy_offset+(flag_srb << 5));/*frame must be 32 bytes aligned*/
break;
@@ -857,7 +950,7 @@
struct AdapterControlBlock *acb;
int target, lun;
u_int8_t cmd;
-
+
target = srb->pccb->ccb_h.target_id;
lun = srb->pccb->ccb_h.target_lun;
acb = srb->acb;
@@ -864,7 +957,7 @@
ARCMSR_LOCK_ACQUIRE(&acb->isr_lock);
if(srb->srb_state == ARCMSR_SRB_START)
{
- cmd = srb->pccb->csio.cdb_io.cdb_bytes[0];
+ cmd = scsiio_cdb_ptr(&srb->pccb->csio)[0];
srb->srb_state = ARCMSR_SRB_TIMEOUT;
srb->pccb->ccb_h.status |= CAM_CMD_TIMEOUT;
arcmsr_srb_complete(srb, 1);
@@ -873,7 +966,7 @@
}
ARCMSR_LOCK_RELEASE(&acb->isr_lock);
#ifdef ARCMSR_DEBUG1
- arcmsr_dump_data(acb);
+ arcmsr_dump_data(acb);
#endif
}
@@ -886,16 +979,16 @@
int i=0;
u_int32_t flag_srb;
u_int16_t error;
-
+
switch (acb->adapter_type) {
case ACB_ADAPTER_TYPE_A: {
u_int32_t outbound_intstatus;
-
+
/*clear and abort all outbound posted Q*/
outbound_intstatus = CHIP_REG_READ32(HBA_MessageUnit, 0, outbound_intstatus) & acb->outbound_int_enable;
CHIP_REG_WRITE32(HBA_MessageUnit, 0, outbound_intstatus, outbound_intstatus);/*clear interrupt*/
while(((flag_srb=CHIP_REG_READ32(HBA_MessageUnit, 0, outbound_queueport)) != 0xFFFFFFFF) && (i++ < ARCMSR_MAX_OUTSTANDING_CMD)) {
- error = (flag_srb & ARCMSR_SRBREPLY_FLAG_ERROR_MODE0)?TRUE:FALSE;
+ error = (flag_srb & ARCMSR_SRBREPLY_FLAG_ERROR_MODE0)?TRUE:FALSE;
arcmsr_drain_donequeue(acb, flag_srb, error);
}
}
@@ -902,13 +995,13 @@
break;
case ACB_ADAPTER_TYPE_B: {
struct HBB_MessageUnit *phbbmu=(struct HBB_MessageUnit *)acb->pmu;
-
+
/*clear all outbound posted Q*/
- CHIP_REG_WRITE32(HBB_DOORBELL, 0, iop2drv_doorbell, ARCMSR_DOORBELL_INT_CLEAR_PATTERN); /* clear doorbell interrupt */
+ WRITE_CHIP_REG32(0, phbbmu->iop2drv_doorbell, ARCMSR_DOORBELL_INT_CLEAR_PATTERN); /* clear doorbell interrupt */
for(i=0; i < ARCMSR_MAX_HBB_POSTQUEUE; i++) {
if((flag_srb = phbbmu->done_qbuffer[i]) != 0) {
phbbmu->done_qbuffer[i] = 0;
- error = (flag_srb & ARCMSR_SRBREPLY_FLAG_ERROR_MODE0)?TRUE:FALSE;
+ error = (flag_srb & ARCMSR_SRBREPLY_FLAG_ERROR_MODE0)?TRUE:FALSE;
arcmsr_drain_donequeue(acb, flag_srb, error);
}
phbbmu->post_qbuffer[i] = 0;
@@ -918,10 +1011,10 @@
}
break;
case ACB_ADAPTER_TYPE_C: {
-
+
while((CHIP_REG_READ32(HBC_MessageUnit, 0, host_int_status) & ARCMSR_HBCMU_OUTBOUND_POSTQUEUE_ISR) && (i++ < ARCMSR_MAX_OUTSTANDING_CMD)) {
flag_srb = CHIP_REG_READ32(HBC_MessageUnit, 0, outbound_queueport_low);
- error = (flag_srb & ARCMSR_SRBREPLY_FLAG_ERROR_MODE1) ? TRUE : FALSE;
+ error = (flag_srb & ARCMSR_SRBREPLY_FLAG_ERROR_MODE1) ? TRUE : FALSE;
arcmsr_drain_donequeue(acb, flag_srb, error);
}
}
@@ -930,6 +1023,10 @@
arcmsr_hbd_postqueue_isr(acb);
}
break;
+ case ACB_ADAPTER_TYPE_E: {
+ arcmsr_hbe_postqueue_isr(acb);
+ }
+ break;
}
}
/*
@@ -941,7 +1038,7 @@
struct CommandControlBlock *srb;
u_int32_t intmask_org;
u_int32_t i=0;
-
+
if(acb->srboutstandingcount>0) {
/* disable all outbound interrupt */
intmask_org = arcmsr_disable_allintr(acb);
@@ -955,9 +1052,9 @@
srb->srb_state = ARCMSR_SRB_ABORTED;
srb->pccb->ccb_h.status |= CAM_REQ_ABORTED;
arcmsr_srb_complete(srb, 1);
- printf("arcmsr%d: scsi id=%d lun=%d srb='%p' aborted\n"
+ printf("arcmsr%d: scsi id=%d lun=%jx srb='%p' aborted\n"
, acb->pci_unit, srb->pccb->ccb_h.target_id
- , srb->pccb->ccb_h.target_lun, srb);
+ , (uintmax_t)srb->pccb->ccb_h.target_lun, srb);
}
}
/* enable all outbound interrupt */
@@ -982,7 +1079,7 @@
union ccb *pccb = srb->pccb;
struct ccb_scsiio *pcsio = &pccb->csio;
u_int32_t arccdbsize = 0x30;
-
+
memset(arcmsr_cdb, 0, sizeof(struct ARCMSR_CDB));
arcmsr_cdb->Bus = 0;
arcmsr_cdb->TargetID = pccb->ccb_h.target_id;
@@ -989,12 +1086,12 @@
arcmsr_cdb->LUN = pccb->ccb_h.target_lun;
arcmsr_cdb->Function = 1;
arcmsr_cdb->CdbLength = (u_int8_t)pcsio->cdb_len;
- bcopy(pcsio->cdb_io.cdb_bytes, arcmsr_cdb->Cdb, pcsio->cdb_len);
+ bcopy(scsiio_cdb_ptr(pcsio), arcmsr_cdb->Cdb, pcsio->cdb_len);
if(nseg != 0) {
struct AdapterControlBlock *acb = srb->acb;
bus_dmasync_op_t op;
u_int32_t length, i, cdb_sgcount = 0;
-
+
if((pccb->ccb_h.flags & CAM_DIR_MASK) == CAM_DIR_IN) {
op = BUS_DMASYNC_PREREAD;
} else {
@@ -1016,11 +1113,11 @@
arccdbsize += sizeof(struct SG32ENTRY);
} else {
u_int32_t sg64s_size = 0, tmplength = length;
-
+
while(1) {
u_int64_t span4G, length0;
struct SG64ENTRY *pdma_sg = (struct SG64ENTRY *)psge;
-
+
span4G = (u_int64_t)address_lo + tmplength;
pdma_sg->addresshigh = address_hi;
pdma_sg->address = address_lo;
@@ -1053,8 +1150,8 @@
} else {
arcmsr_cdb->DataLength = 0;
}
- srb->arc_cdb_size = arccdbsize;
- arcmsr_cdb->msgPages = (arccdbsize/256) + ((arccdbsize % 256) ? 1 : 0);
+ srb->arc_cdb_size = arccdbsize;
+ arcmsr_cdb->msgPages = (arccdbsize/256) + ((arccdbsize % 256) ? 1 : 0);
}
/*
**************************************************************************
@@ -1064,7 +1161,7 @@
{
u_int32_t cdb_phyaddr_low = (u_int32_t) srb->cdb_phyaddr_low;
struct ARCMSR_CDB *arcmsr_cdb = (struct ARCMSR_CDB *)&srb->arcmsr_cdb;
-
+
bus_dmamap_sync(acb->srb_dmat, acb->srb_dmamap, (srb->srb_flags & SRB_FLAG_WRITE) ? BUS_DMASYNC_POSTWRITE:BUS_DMASYNC_POSTREAD);
atomic_add_int(&acb->srboutstandingcount, 1);
srb->srb_state = ARCMSR_SRB_START;
@@ -1081,7 +1178,7 @@
case ACB_ADAPTER_TYPE_B: {
struct HBB_MessageUnit *phbbmu = (struct HBB_MessageUnit *)acb->pmu;
int ending_index, index;
-
+
index = phbbmu->postq_index;
ending_index = ((index+1) % ARCMSR_MAX_HBB_POSTQUEUE);
phbbmu->post_qbuffer[ending_index] = 0;
@@ -1093,26 +1190,26 @@
index++;
index %= ARCMSR_MAX_HBB_POSTQUEUE; /*if last index number set it to 0 */
phbbmu->postq_index = index;
- CHIP_REG_WRITE32(HBB_DOORBELL, 0, drv2iop_doorbell, ARCMSR_DRV2IOP_CDB_POSTED);
+ WRITE_CHIP_REG32(0, phbbmu->drv2iop_doorbell, ARCMSR_DRV2IOP_CDB_POSTED);
}
break;
- case ACB_ADAPTER_TYPE_C: {
- u_int32_t ccb_post_stamp, arc_cdb_size, cdb_phyaddr_hi32;
+ case ACB_ADAPTER_TYPE_C: {
+ u_int32_t ccb_post_stamp, arc_cdb_size, cdb_phyaddr_hi32;
- arc_cdb_size = (srb->arc_cdb_size > 0x300) ? 0x300 : srb->arc_cdb_size;
- ccb_post_stamp = (cdb_phyaddr_low | ((arc_cdb_size-1) >> 6) | 1);
+ arc_cdb_size = (srb->arc_cdb_size > 0x300) ? 0x300 : srb->arc_cdb_size;
+ ccb_post_stamp = (cdb_phyaddr_low | ((arc_cdb_size-1) >> 6) | 1);
cdb_phyaddr_hi32 = acb->srb_phyaddr.B.phyadd_high;
- if(cdb_phyaddr_hi32)
- {
- CHIP_REG_WRITE32(HBC_MessageUnit,0,inbound_queueport_high, cdb_phyaddr_hi32);
- CHIP_REG_WRITE32(HBC_MessageUnit,0,inbound_queueport_low, ccb_post_stamp);
- }
- else
- {
- CHIP_REG_WRITE32(HBC_MessageUnit,0,inbound_queueport_low, ccb_post_stamp);
- }
- }
- break;
+ if(cdb_phyaddr_hi32)
+ {
+ CHIP_REG_WRITE32(HBC_MessageUnit,0,inbound_queueport_high, cdb_phyaddr_hi32);
+ CHIP_REG_WRITE32(HBC_MessageUnit,0,inbound_queueport_low, ccb_post_stamp);
+ }
+ else
+ {
+ CHIP_REG_WRITE32(HBC_MessageUnit,0,inbound_queueport_low, ccb_post_stamp);
+ }
+ }
+ break;
case ACB_ADAPTER_TYPE_D: {
struct HBD_MessageUnit0 *phbdmu = (struct HBD_MessageUnit0 *)acb->pmu;
u_int16_t index_stripped;
@@ -1141,6 +1238,15 @@
ARCMSR_LOCK_RELEASE(&acb->postDone_lock);
}
break;
+ case ACB_ADAPTER_TYPE_E: {
+ u_int32_t ccb_post_stamp, arc_cdb_size;
+
+ arc_cdb_size = (srb->arc_cdb_size > 0x300) ? 0x300 : srb->arc_cdb_size;
+ ccb_post_stamp = (srb->smid | ((arc_cdb_size-1) >> 6));
+ CHIP_REG_WRITE32(HBE_MessageUnit, 0, inbound_queueport_high, 0);
+ CHIP_REG_WRITE32(HBE_MessageUnit, 0, inbound_queueport_low, ccb_post_stamp);
+ }
+ break;
}
}
/*
@@ -1150,32 +1256,38 @@
static struct QBUFFER *arcmsr_get_iop_rqbuffer( struct AdapterControlBlock *acb)
{
struct QBUFFER *qbuffer=NULL;
-
+
switch (acb->adapter_type) {
case ACB_ADAPTER_TYPE_A: {
struct HBA_MessageUnit *phbamu = (struct HBA_MessageUnit *)acb->pmu;
-
+
qbuffer = (struct QBUFFER *)&phbamu->message_rbuffer;
}
break;
case ACB_ADAPTER_TYPE_B: {
struct HBB_MessageUnit *phbbmu = (struct HBB_MessageUnit *)acb->pmu;
-
+
qbuffer = (struct QBUFFER *)&phbbmu->hbb_rwbuffer->message_rbuffer;
}
break;
case ACB_ADAPTER_TYPE_C: {
struct HBC_MessageUnit *phbcmu = (struct HBC_MessageUnit *)acb->pmu;
-
+
qbuffer = (struct QBUFFER *)&phbcmu->message_rbuffer;
}
break;
case ACB_ADAPTER_TYPE_D: {
struct HBD_MessageUnit0 *phbdmu = (struct HBD_MessageUnit0 *)acb->pmu;
-
+
qbuffer = (struct QBUFFER *)&phbdmu->phbdmu->message_rbuffer;
}
break;
+ case ACB_ADAPTER_TYPE_E: {
+ struct HBE_MessageUnit *phbcmu = (struct HBE_MessageUnit *)acb->pmu;
+
+ qbuffer = (struct QBUFFER *)&phbcmu->message_rbuffer;
+ }
+ break;
}
return(qbuffer);
}
@@ -1186,32 +1298,38 @@
static struct QBUFFER *arcmsr_get_iop_wqbuffer( struct AdapterControlBlock *acb)
{
struct QBUFFER *qbuffer = NULL;
-
+
switch (acb->adapter_type) {
case ACB_ADAPTER_TYPE_A: {
struct HBA_MessageUnit *phbamu = (struct HBA_MessageUnit *)acb->pmu;
-
+
qbuffer = (struct QBUFFER *)&phbamu->message_wbuffer;
}
break;
case ACB_ADAPTER_TYPE_B: {
struct HBB_MessageUnit *phbbmu = (struct HBB_MessageUnit *)acb->pmu;
-
+
qbuffer = (struct QBUFFER *)&phbbmu->hbb_rwbuffer->message_wbuffer;
}
break;
case ACB_ADAPTER_TYPE_C: {
struct HBC_MessageUnit *phbcmu = (struct HBC_MessageUnit *)acb->pmu;
-
+
qbuffer = (struct QBUFFER *)&phbcmu->message_wbuffer;
}
break;
case ACB_ADAPTER_TYPE_D: {
struct HBD_MessageUnit0 *phbdmu = (struct HBD_MessageUnit0 *)acb->pmu;
-
+
qbuffer = (struct QBUFFER *)&phbdmu->phbdmu->message_wbuffer;
}
break;
+ case ACB_ADAPTER_TYPE_E: {
+ struct HBE_MessageUnit *phbcmu = (struct HBE_MessageUnit *)acb->pmu;
+
+ qbuffer = (struct QBUFFER *)&phbcmu->message_wbuffer;
+ }
+ break;
}
return(qbuffer);
}
@@ -1228,8 +1346,9 @@
}
break;
case ACB_ADAPTER_TYPE_B: {
+ struct HBB_MessageUnit *phbbmu = (struct HBB_MessageUnit *)acb->pmu;
/* let IOP know data has been read */
- CHIP_REG_WRITE32(HBB_DOORBELL, 0, drv2iop_doorbell, ARCMSR_DRV2IOP_DATA_READ_OK);
+ WRITE_CHIP_REG32(0, phbbmu->drv2iop_doorbell, ARCMSR_DRV2IOP_DATA_READ_OK);
}
break;
case ACB_ADAPTER_TYPE_C: {
@@ -1242,6 +1361,12 @@
CHIP_REG_WRITE32(HBD_MessageUnit, 0, inbound_doorbell, ARCMSR_HBDMU_DRV2IOP_DATA_OUT_READ);
}
break;
+ case ACB_ADAPTER_TYPE_E: {
+ /* let IOP know data has been read */
+ acb->out_doorbell ^= ARCMSR_HBEMU_DRV2IOP_DATA_READ_OK;
+ CHIP_REG_WRITE32(HBE_MessageUnit, 0, iobound_doorbell, acb->out_doorbell);
+ }
+ break;
}
}
/*
@@ -1260,11 +1385,12 @@
}
break;
case ACB_ADAPTER_TYPE_B: {
+ struct HBB_MessageUnit *phbbmu = (struct HBB_MessageUnit *)acb->pmu;
/*
** push inbound doorbell tell iop, driver data write ok
** and wait reply on next hwinterrupt for next Qbuffer post
*/
- CHIP_REG_WRITE32(HBB_DOORBELL, 0, drv2iop_doorbell, ARCMSR_DRV2IOP_DATA_WRITE_OK);
+ WRITE_CHIP_REG32(0, phbbmu->drv2iop_doorbell, ARCMSR_DRV2IOP_DATA_WRITE_OK);
}
break;
case ACB_ADAPTER_TYPE_C: {
@@ -1283,6 +1409,15 @@
CHIP_REG_WRITE32(HBD_MessageUnit, 0, inbound_doorbell, ARCMSR_HBDMU_DRV2IOP_DATA_IN_READY);
}
break;
+ case ACB_ADAPTER_TYPE_E: {
+ /*
+ ** push inbound doorbell tell iop, driver data write ok
+ ** and wait reply on next hwinterrupt for next Qbuffer post
+ */
+ acb->out_doorbell ^= ARCMSR_HBEMU_DRV2IOP_DATA_WRITE_OK;
+ CHIP_REG_WRITE32(HBE_MessageUnit, 0, iobound_doorbell, acb->out_doorbell);
+ }
+ break;
}
}
/*
@@ -1293,7 +1428,7 @@
{
acb->acb_flags &= ~ACB_F_MSG_START_BGRB;
CHIP_REG_WRITE32(HBA_MessageUnit,
- 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_STOP_BGRB);
+ 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_STOP_BGRB);
if(!arcmsr_hba_wait_msgint_ready(acb)) {
printf("arcmsr%d: wait 'stop adapter background rebulid' timeout \n"
, acb->pci_unit);
@@ -1305,9 +1440,9 @@
*/
static void arcmsr_stop_hbb_bgrb(struct AdapterControlBlock *acb)
{
+ struct HBB_MessageUnit *phbbmu = (struct HBB_MessageUnit *)acb->pmu;
acb->acb_flags &= ~ACB_F_MSG_START_BGRB;
- CHIP_REG_WRITE32(HBB_DOORBELL,
- 0, drv2iop_doorbell, ARCMSR_MESSAGE_STOP_BGRB);
+ WRITE_CHIP_REG32(0, phbbmu->drv2iop_doorbell, ARCMSR_MESSAGE_STOP_BGRB);
if(!arcmsr_hbb_wait_msgint_ready(acb)) {
printf( "arcmsr%d: wait 'stop adapter background rebulid' timeout \n"
, acb->pci_unit);
@@ -1342,6 +1477,20 @@
************************************************************************
************************************************************************
*/
+static void arcmsr_stop_hbe_bgrb(struct AdapterControlBlock *acb)
+{
+ acb->acb_flags &= ~ACB_F_MSG_START_BGRB;
+ CHIP_REG_WRITE32(HBE_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_STOP_BGRB);
+ acb->out_doorbell ^= ARCMSR_HBEMU_DRV2IOP_MESSAGE_CMD_DONE;
+ CHIP_REG_WRITE32(HBE_MessageUnit, 0, iobound_doorbell, acb->out_doorbell);
+ if(!arcmsr_hbe_wait_msgint_ready(acb)) {
+ printf("arcmsr%d: wait 'stop adapter background rebulid' timeout \n", acb->pci_unit);
+ }
+}
+/*
+************************************************************************
+************************************************************************
+*/
static void arcmsr_stop_adapter_bgrb(struct AdapterControlBlock *acb)
{
switch (acb->adapter_type) {
@@ -1361,6 +1510,10 @@
arcmsr_stop_hbd_bgrb(acb);
}
break;
+ case ACB_ADAPTER_TYPE_E: {
+ arcmsr_stop_hbe_bgrb(acb);
+ }
+ break;
}
}
/*
@@ -1385,11 +1538,11 @@
**************************************************************************
*/
static u_int32_t arcmsr_Read_iop_rqbuffer_data_D(struct AdapterControlBlock *acb,
- struct QBUFFER *prbuffer) {
+ struct QBUFFER *prbuffer) {
u_int8_t *pQbuffer;
- u_int8_t *buf1 = 0;
- u_int32_t *iop_data, *buf2 = 0;
+ u_int8_t *buf1 = NULL;
+ u_int32_t *iop_data, *buf2 = NULL;
u_int32_t iop_len, data_len;
iop_data = (u_int32_t *)prbuffer->data;
@@ -1430,13 +1583,13 @@
**************************************************************************
*/
static u_int32_t arcmsr_Read_iop_rqbuffer_data(struct AdapterControlBlock *acb,
- struct QBUFFER *prbuffer) {
+ struct QBUFFER *prbuffer) {
u_int8_t *pQbuffer;
u_int8_t *iop_data;
u_int32_t iop_len;
- if(acb->adapter_type == ACB_ADAPTER_TYPE_D) {
+ if(acb->adapter_type >= ACB_ADAPTER_TYPE_B) {
return(arcmsr_Read_iop_rqbuffer_data_D(acb, prbuffer));
}
iop_data = (u_int8_t *)prbuffer->data;
@@ -1462,12 +1615,12 @@
{
struct QBUFFER *prbuffer;
int my_empty_len;
-
+
/*check this iop data if overflow my rqbuffer*/
ARCMSR_LOCK_ACQUIRE(&acb->qbuffer_lock);
prbuffer = arcmsr_get_iop_rqbuffer(acb);
my_empty_len = (acb->rqbuf_lastindex - acb->rqbuf_firstindex - 1) &
- (ARCMSR_MAX_QBUFFER-1);
+ (ARCMSR_MAX_QBUFFER-1);
if(my_empty_len >= prbuffer->data_len) {
if(arcmsr_Read_iop_rqbuffer_data(acb, prbuffer) == 0)
acb->acb_flags |= ACB_F_IOPDATA_OVERFLOW;
@@ -1484,10 +1637,10 @@
{
u_int8_t *pQbuffer;
struct QBUFFER *pwbuffer;
- u_int8_t *buf1 = 0;
- u_int32_t *iop_data, *buf2 = 0;
+ u_int8_t *buf1 = NULL;
+ u_int32_t *iop_data, *buf2 = NULL;
u_int32_t allxfer_len = 0, data_len;
-
+
if(acb->acb_flags & ACB_F_MESSAGE_WQBUFFER_READ) {
buf1 = malloc(128, M_DEVBUF, M_NOWAIT | M_ZERO);
buf2 = (u_int32_t *)buf1;
@@ -1530,8 +1683,8 @@
struct QBUFFER *pwbuffer;
u_int8_t *iop_data;
int32_t allxfer_len=0;
-
- if(acb->adapter_type == ACB_ADAPTER_TYPE_D) {
+
+ if(acb->adapter_type >= ACB_ADAPTER_TYPE_B) {
arcmsr_Write_data_2iop_wqbuffer_D(acb);
return;
}
@@ -1583,8 +1736,8 @@
/*
if (ccb->ccb_h.status != CAM_REQ_CMP)
printf("arcmsr_rescanLun_cb: Rescan Target=%x, lun=%x,"
- "failure status=%x\n", ccb->ccb_h.target_id,
- ccb->ccb_h.target_lun, ccb->ccb_h.status);
+ "failure status=%x\n", ccb->ccb_h.target_id,
+ ccb->ccb_h.target_lun, ccb->ccb_h.status);
else
printf("arcmsr_rescanLun_cb: Rescan lun successfully!\n");
*/
@@ -1598,8 +1751,8 @@
union ccb *ccb;
if ((ccb = (union ccb *)xpt_alloc_ccb_nowait()) == NULL)
- return;
- if (xpt_create_path(&path, xpt_periph, cam_sim_path(acb->psim), target, lun) != CAM_REQ_CMP)
+ return;
+ if (xpt_create_path(&path, NULL, cam_sim_path(acb->psim), target, lun) != CAM_REQ_CMP)
{
xpt_free_ccb(ccb);
return;
@@ -1616,11 +1769,10 @@
static void arcmsr_abort_dr_ccbs(struct AdapterControlBlock *acb, int target, int lun)
{
- struct CommandControlBlock *srb;
+ struct CommandControlBlock *srb;
u_int32_t intmask_org;
- int i;
+ int i;
- ARCMSR_LOCK_ACQUIRE(&acb->isr_lock);
/* disable all outbound interrupts */
intmask_org = arcmsr_disable_allintr(acb);
for (i = 0; i < ARCMSR_MAX_FREESRB_NUM; i++)
@@ -1628,18 +1780,17 @@
srb = acb->psrb_pool[i];
if (srb->srb_state == ARCMSR_SRB_START)
{
- if((target == srb->pccb->ccb_h.target_id) && (lun == srb->pccb->ccb_h.target_lun))
- {
- srb->srb_state = ARCMSR_SRB_ABORTED;
+ if((target == srb->pccb->ccb_h.target_id) && (lun == srb->pccb->ccb_h.target_lun))
+ {
+ srb->srb_state = ARCMSR_SRB_ABORTED;
srb->pccb->ccb_h.status |= CAM_REQ_ABORTED;
- arcmsr_srb_complete(srb, 1);
+ arcmsr_srb_complete(srb, 1);
printf("arcmsr%d: abort scsi id %d lun %d srb=%p \n", acb->pci_unit, target, lun, srb);
- }
+ }
}
}
/* enable outbound Post Queue, outbound doorbell Interrupt */
arcmsr_enable_allintr(acb, intmask_org);
- ARCMSR_LOCK_RELEASE(&acb->isr_lock);
}
/*
**************************************************************************
@@ -1648,87 +1799,95 @@
static void arcmsr_dr_handle(struct AdapterControlBlock *acb) {
u_int32_t devicemap;
u_int32_t target, lun;
- u_int32_t deviceMapCurrent[4]={0};
- u_int8_t *pDevMap;
+ u_int32_t deviceMapCurrent[4]={0};
+ u_int8_t *pDevMap;
switch (acb->adapter_type) {
case ACB_ADAPTER_TYPE_A:
- devicemap = offsetof(struct HBA_MessageUnit, msgcode_rwbuffer[ARCMSR_FW_DEVMAP_OFFSET]);
- for (target = 0; target < 4; target++)
- {
- deviceMapCurrent[target]=bus_space_read_4(acb->btag[0], acb->bhandle[0], devicemap);
- devicemap += 4;
- }
- break;
+ devicemap = offsetof(struct HBA_MessageUnit, msgcode_rwbuffer[ARCMSR_FW_DEVMAP_OFFSET]);
+ for (target = 0; target < 4; target++)
+ {
+ deviceMapCurrent[target]=bus_space_read_4(acb->btag[0], acb->bhandle[0], devicemap);
+ devicemap += 4;
+ }
+ break;
case ACB_ADAPTER_TYPE_B:
- devicemap = offsetof(struct HBB_RWBUFFER, msgcode_rwbuffer[ARCMSR_FW_DEVMAP_OFFSET]);
- for (target = 0; target < 4; target++)
- {
- deviceMapCurrent[target]=bus_space_read_4(acb->btag[1], acb->bhandle[1], devicemap);
- devicemap += 4;
- }
- break;
+ devicemap = offsetof(struct HBB_RWBUFFER, msgcode_rwbuffer[ARCMSR_FW_DEVMAP_OFFSET]);
+ for (target = 0; target < 4; target++)
+ {
+ deviceMapCurrent[target]=bus_space_read_4(acb->btag[1], acb->bhandle[1], devicemap);
+ devicemap += 4;
+ }
+ break;
case ACB_ADAPTER_TYPE_C:
- devicemap = offsetof(struct HBC_MessageUnit, msgcode_rwbuffer[ARCMSR_FW_DEVMAP_OFFSET]);
- for (target = 0; target < 4; target++)
- {
- deviceMapCurrent[target]=bus_space_read_4(acb->btag[0], acb->bhandle[0], devicemap);
- devicemap += 4;
- }
- break;
+ devicemap = offsetof(struct HBC_MessageUnit, msgcode_rwbuffer[ARCMSR_FW_DEVMAP_OFFSET]);
+ for (target = 0; target < 4; target++)
+ {
+ deviceMapCurrent[target]=bus_space_read_4(acb->btag[0], acb->bhandle[0], devicemap);
+ devicemap += 4;
+ }
+ break;
case ACB_ADAPTER_TYPE_D:
- devicemap = offsetof(struct HBD_MessageUnit, msgcode_rwbuffer[ARCMSR_FW_DEVMAP_OFFSET]);
- for (target = 0; target < 4; target++)
- {
- deviceMapCurrent[target]=bus_space_read_4(acb->btag[0], acb->bhandle[0], devicemap);
- devicemap += 4;
- }
- break;
+ devicemap = offsetof(struct HBD_MessageUnit, msgcode_rwbuffer[ARCMSR_FW_DEVMAP_OFFSET]);
+ for (target = 0; target < 4; target++)
+ {
+ deviceMapCurrent[target]=bus_space_read_4(acb->btag[0], acb->bhandle[0], devicemap);
+ devicemap += 4;
+ }
+ break;
+ case ACB_ADAPTER_TYPE_E:
+ devicemap = offsetof(struct HBE_MessageUnit, msgcode_rwbuffer[ARCMSR_FW_DEVMAP_OFFSET]);
+ for (target = 0; target < 4; target++)
+ {
+ deviceMapCurrent[target]=bus_space_read_4(acb->btag[0], acb->bhandle[0], devicemap);
+ devicemap += 4;
+ }
+ break;
}
- if(acb->acb_flags & ACB_F_BUS_HANG_ON)
+ if(acb->acb_flags & ACB_F_BUS_HANG_ON)
+ {
+ acb->acb_flags &= ~ACB_F_BUS_HANG_ON;
+ }
+ /*
+ ** adapter posted CONFIG message
+ ** copy the new map, note if there are differences with the current map
+ */
+ pDevMap = (u_int8_t *)&deviceMapCurrent[0];
+ for (target = 0; target < ARCMSR_MAX_TARGETID - 1; target++)
+ {
+ if (*pDevMap != acb->device_map[target])
{
- acb->acb_flags &= ~ACB_F_BUS_HANG_ON;
- }
- /*
- ** adapter posted CONFIG message
- ** copy the new map, note if there are differences with the current map
- */
- pDevMap = (u_int8_t *)&deviceMapCurrent[0];
- for (target = 0; target < ARCMSR_MAX_TARGETID - 1; target++)
- {
- if (*pDevMap != acb->device_map[target])
+ u_int8_t difference, bit_check;
+
+ difference = *pDevMap ^ acb->device_map[target];
+ for(lun=0; lun < ARCMSR_MAX_TARGETLUN; lun++)
{
- u_int8_t difference, bit_check;
-
- difference = *pDevMap ^ acb->device_map[target];
- for(lun=0; lun < ARCMSR_MAX_TARGETLUN; lun++)
- {
- bit_check = (1 << lun); /*check bit from 0....31*/
- if(difference & bit_check)
- {
- if(acb->device_map[target] & bit_check)
- {/* unit departed */
- printf("arcmsr_dr_handle: Target=%x, lun=%x, GONE!!!\n",target,lun);
- arcmsr_abort_dr_ccbs(acb, target, lun);
- arcmsr_rescan_lun(acb, target, lun);
- acb->devstate[target][lun] = ARECA_RAID_GONE;
- }
- else
- {/* unit arrived */
- printf("arcmsr_dr_handle: Target=%x, lun=%x, Plug-IN!!!\n",target,lun);
- arcmsr_rescan_lun(acb, target, lun);
- acb->devstate[target][lun] = ARECA_RAID_GOOD;
- }
- }
- }
-/* printf("arcmsr_dr_handle: acb->device_map[%x]=0x%x, deviceMapCurrent[%x]=%x\n",target,acb->device_map[target],target,*pDevMap); */
- acb->device_map[target] = *pDevMap;
+ bit_check = (1 << lun); /*check bit from 0....31*/
+ if(difference & bit_check)
+ {
+ if(acb->device_map[target] & bit_check)
+ {/* unit departed */
+ printf("arcmsr_dr_handle: Target=%x, lun=%x, GONE!!!\n",target,lun);
+ arcmsr_abort_dr_ccbs(acb, target, lun);
+ arcmsr_rescan_lun(acb, target, lun);
+ acb->devstate[target][lun] = ARECA_RAID_GONE;
+ }
+ else
+ {/* unit arrived */
+ printf("arcmsr_dr_handle: Target=%x, lun=%x, Plug-IN!!!\n",target,lun);
+ arcmsr_rescan_lun(acb, target, lun);
+ acb->devstate[target][lun] = ARECA_RAID_GOOD;
+ }
+ }
}
- pDevMap++;
+/* printf("arcmsr_dr_handle: acb->device_map[%x]=0x%x, deviceMapCurrent[%x]=%x\n",target,acb->device_map[target],target,*pDevMap); */
+ acb->device_map[target] = *pDevMap;
}
+ pDevMap++;
+ }
}
/*
**************************************************************************
@@ -1748,9 +1907,10 @@
*/
static void arcmsr_hbb_message_isr(struct AdapterControlBlock *acb) {
u_int32_t outbound_message;
+ struct HBB_MessageUnit *phbbmu = (struct HBB_MessageUnit *)acb->pmu;
/* clear interrupts */
- CHIP_REG_WRITE32(HBB_DOORBELL, 0, iop2drv_doorbell, ARCMSR_MESSAGE_INT_CLEAR_PATTERN);
+ WRITE_CHIP_REG32(0, phbbmu->iop2drv_doorbell, ARCMSR_MESSAGE_INT_CLEAR_PATTERN);
outbound_message = CHIP_REG_READ32(HBB_RWBUFFER, 1, msgcode_rwbuffer[0]);
if (outbound_message == ARCMSR_SIGNATURE_GET_CONFIG)
arcmsr_dr_handle( acb );
@@ -1783,10 +1943,22 @@
**************************************************************************
**************************************************************************
*/
+static void arcmsr_hbe_message_isr(struct AdapterControlBlock *acb) {
+ u_int32_t outbound_message;
+
+ CHIP_REG_WRITE32(HBE_MessageUnit, 0, host_int_status, 0);
+ outbound_message = CHIP_REG_READ32(HBE_MessageUnit, 0, msgcode_rwbuffer[0]);
+ if (outbound_message == ARCMSR_SIGNATURE_GET_CONFIG)
+ arcmsr_dr_handle( acb );
+}
+/*
+**************************************************************************
+**************************************************************************
+*/
static void arcmsr_hba_doorbell_isr(struct AdapterControlBlock *acb)
{
- u_int32_t outbound_doorbell;
-
+ u_int32_t doorbell_status;
+
/*
*******************************************************************
** Maybe here we need to check wrqbuffer_lock is lock or not
@@ -1794,14 +1966,12 @@
** check if there are any mail need to pack from firmware
*******************************************************************
*/
- outbound_doorbell = CHIP_REG_READ32(HBA_MessageUnit,
- 0, outbound_doorbell);
- CHIP_REG_WRITE32(HBA_MessageUnit,
- 0, outbound_doorbell, outbound_doorbell); /* clear doorbell interrupt */
- if(outbound_doorbell & ARCMSR_OUTBOUND_IOP331_DATA_WRITE_OK) {
+ doorbell_status = CHIP_REG_READ32(HBA_MessageUnit, 0, outbound_doorbell);
+ CHIP_REG_WRITE32(HBA_MessageUnit, 0, outbound_doorbell, doorbell_status); /* clear doorbell interrupt */
+ if(doorbell_status & ARCMSR_OUTBOUND_IOP331_DATA_WRITE_OK) {
arcmsr_iop2drv_data_wrote_handle(acb);
}
- if(outbound_doorbell & ARCMSR_OUTBOUND_IOP331_DATA_READ_OK) {
+ if(doorbell_status & ARCMSR_OUTBOUND_IOP331_DATA_READ_OK) {
arcmsr_iop2drv_data_read_handle(acb);
}
}
@@ -1811,8 +1981,8 @@
*/
static void arcmsr_hbc_doorbell_isr(struct AdapterControlBlock *acb)
{
- u_int32_t outbound_doorbell;
-
+ u_int32_t doorbell_status;
+
/*
*******************************************************************
** Maybe here we need to check wrqbuffer_lock is lock or not
@@ -1820,15 +1990,15 @@
** check if there are any mail need to pack from firmware
*******************************************************************
*/
- outbound_doorbell = CHIP_REG_READ32(HBC_MessageUnit, 0, outbound_doorbell);
- CHIP_REG_WRITE32(HBC_MessageUnit, 0, outbound_doorbell_clear, outbound_doorbell); /* clear doorbell interrupt */
- if(outbound_doorbell & ARCMSR_HBCMU_IOP2DRV_DATA_WRITE_OK) {
+ doorbell_status = CHIP_REG_READ32(HBC_MessageUnit, 0, outbound_doorbell);
+ CHIP_REG_WRITE32(HBC_MessageUnit, 0, outbound_doorbell_clear, doorbell_status); /* clear doorbell interrupt */
+ if(doorbell_status & ARCMSR_HBCMU_IOP2DRV_DATA_WRITE_OK) {
arcmsr_iop2drv_data_wrote_handle(acb);
}
- if(outbound_doorbell & ARCMSR_HBCMU_IOP2DRV_DATA_READ_OK) {
+ if(doorbell_status & ARCMSR_HBCMU_IOP2DRV_DATA_READ_OK) {
arcmsr_iop2drv_data_read_handle(acb);
}
- if(outbound_doorbell & ARCMSR_HBCMU_IOP2DRV_MESSAGE_CMD_DONE) {
+ if(doorbell_status & ARCMSR_HBCMU_IOP2DRV_MESSAGE_CMD_DONE) {
arcmsr_hbc_message_isr(acb); /* messenger of "driver to iop commands" */
}
}
@@ -1838,8 +2008,8 @@
*/
static void arcmsr_hbd_doorbell_isr(struct AdapterControlBlock *acb)
{
- u_int32_t outbound_Doorbell;
-
+ u_int32_t doorbell_status;
+
/*
*******************************************************************
** Maybe here we need to check wrqbuffer_lock is lock or not
@@ -1847,22 +2017,22 @@
** check if there are any mail need to pack from firmware
*******************************************************************
*/
- outbound_Doorbell = CHIP_REG_READ32(HBD_MessageUnit, 0, outbound_doorbell) & ARCMSR_HBDMU_F0_DOORBELL_CAUSE;
- if(outbound_Doorbell)
- CHIP_REG_WRITE32(HBD_MessageUnit, 0, outbound_doorbell, outbound_Doorbell); /* clear doorbell interrupt */
- while( outbound_Doorbell & ARCMSR_HBDMU_F0_DOORBELL_CAUSE ) {
- if(outbound_Doorbell & ARCMSR_HBDMU_IOP2DRV_DATA_WRITE_OK) {
+ doorbell_status = CHIP_REG_READ32(HBD_MessageUnit, 0, outbound_doorbell) & ARCMSR_HBDMU_F0_DOORBELL_CAUSE;
+ if(doorbell_status)
+ CHIP_REG_WRITE32(HBD_MessageUnit, 0, outbound_doorbell, doorbell_status); /* clear doorbell interrupt */
+ while( doorbell_status & ARCMSR_HBDMU_F0_DOORBELL_CAUSE ) {
+ if(doorbell_status & ARCMSR_HBDMU_IOP2DRV_DATA_WRITE_OK) {
arcmsr_iop2drv_data_wrote_handle(acb);
}
- if(outbound_Doorbell & ARCMSR_HBDMU_IOP2DRV_DATA_READ_OK) {
+ if(doorbell_status & ARCMSR_HBDMU_IOP2DRV_DATA_READ_OK) {
arcmsr_iop2drv_data_read_handle(acb);
}
- if(outbound_Doorbell & ARCMSR_HBDMU_IOP2DRV_MESSAGE_CMD_DONE) {
+ if(doorbell_status & ARCMSR_HBDMU_IOP2DRV_MESSAGE_CMD_DONE) {
arcmsr_hbd_message_isr(acb); /* messenger of "driver to iop commands" */
}
- outbound_Doorbell = CHIP_REG_READ32(HBD_MessageUnit, 0, outbound_doorbell) & ARCMSR_HBDMU_F0_DOORBELL_CAUSE;
- if(outbound_Doorbell)
- CHIP_REG_WRITE32(HBD_MessageUnit, 0, outbound_doorbell, outbound_Doorbell); /* clear doorbell interrupt */
+ doorbell_status = CHIP_REG_READ32(HBD_MessageUnit, 0, outbound_doorbell) & ARCMSR_HBDMU_F0_DOORBELL_CAUSE;
+ if(doorbell_status)
+ CHIP_REG_WRITE32(HBD_MessageUnit, 0, outbound_doorbell, doorbell_status); /* clear doorbell interrupt */
}
}
/*
@@ -1869,11 +2039,40 @@
**************************************************************************
**************************************************************************
*/
+static void arcmsr_hbe_doorbell_isr(struct AdapterControlBlock *acb)
+{
+ u_int32_t doorbell_status, in_doorbell;
+
+ /*
+ *******************************************************************
+ ** Maybe here we need to check wrqbuffer_lock is lock or not
+ ** DOORBELL: din! don!
+ ** check if there are any mail need to pack from firmware
+ *******************************************************************
+ */
+ in_doorbell = CHIP_REG_READ32(HBE_MessageUnit, 0, iobound_doorbell);
+ CHIP_REG_WRITE32(HBE_MessageUnit, 0, host_int_status, 0); /* clear doorbell interrupt */
+ doorbell_status = in_doorbell ^ acb->in_doorbell;
+ if(doorbell_status & ARCMSR_HBEMU_IOP2DRV_DATA_WRITE_OK) {
+ arcmsr_iop2drv_data_wrote_handle(acb);
+ }
+ if(doorbell_status & ARCMSR_HBEMU_IOP2DRV_DATA_READ_OK) {
+ arcmsr_iop2drv_data_read_handle(acb);
+ }
+ if(doorbell_status & ARCMSR_HBEMU_IOP2DRV_MESSAGE_CMD_DONE) {
+ arcmsr_hbe_message_isr(acb); /* messenger of "driver to iop commands" */
+ }
+ acb->in_doorbell = in_doorbell;
+}
+/*
+**************************************************************************
+**************************************************************************
+*/
static void arcmsr_hba_postqueue_isr(struct AdapterControlBlock *acb)
{
u_int32_t flag_srb;
u_int16_t error;
-
+
/*
*****************************************************************************
** areca cdb command done
@@ -1884,7 +2083,7 @@
while((flag_srb = CHIP_REG_READ32(HBA_MessageUnit,
0, outbound_queueport)) != 0xFFFFFFFF) {
/* check if command done with no error*/
- error = (flag_srb & ARCMSR_SRBREPLY_FLAG_ERROR_MODE0) ? TRUE : FALSE;
+ error = (flag_srb & ARCMSR_SRBREPLY_FLAG_ERROR_MODE0) ? TRUE : FALSE;
arcmsr_drain_donequeue(acb, flag_srb, error);
} /*drain reply FIFO*/
}
@@ -1913,7 +2112,7 @@
index %= ARCMSR_MAX_HBB_POSTQUEUE; /*if last index number set it to 0 */
phbbmu->doneq_index = index;
/* check if command done with no error*/
- error = (flag_srb & ARCMSR_SRBREPLY_FLAG_ERROR_MODE0)?TRUE:FALSE;
+ error = (flag_srb & ARCMSR_SRBREPLY_FLAG_ERROR_MODE0)?TRUE:FALSE;
arcmsr_drain_donequeue(acb, flag_srb, error);
} /*drain reply FIFO*/
}
@@ -1925,7 +2124,7 @@
{
u_int32_t flag_srb,throttling = 0;
u_int16_t error;
-
+
/*
*****************************************************************************
** areca cdb command done
@@ -1932,19 +2131,19 @@
*****************************************************************************
*/
bus_dmamap_sync(acb->srb_dmat, acb->srb_dmamap, BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE);
-
- while(CHIP_REG_READ32(HBC_MessageUnit, 0, host_int_status) & ARCMSR_HBCMU_OUTBOUND_POSTQUEUE_ISR) {
-
+ do {
flag_srb = CHIP_REG_READ32(HBC_MessageUnit, 0, outbound_queueport_low);
+ if (flag_srb == 0xFFFFFFFF)
+ break;
/* check if command done with no error*/
- error = (flag_srb & ARCMSR_SRBREPLY_FLAG_ERROR_MODE1)?TRUE:FALSE;
+ error = (flag_srb & ARCMSR_SRBREPLY_FLAG_ERROR_MODE1)?TRUE:FALSE;
arcmsr_drain_donequeue(acb, flag_srb, error);
- if(throttling == ARCMSR_HBC_ISR_THROTTLING_LEVEL) {
- CHIP_REG_WRITE32(HBC_MessageUnit, 0, inbound_doorbell,ARCMSR_HBCMU_DRV2IOP_POSTQUEUE_THROTTLING);
- break;
- }
- throttling++;
- } /*drain reply FIFO*/
+ throttling++;
+ if(throttling == ARCMSR_HBC_ISR_THROTTLING_LEVEL) {
+ CHIP_REG_WRITE32(HBC_MessageUnit, 0, inbound_doorbell,ARCMSR_HBCMU_DRV2IOP_POSTQUEUE_THROTTLING);
+ throttling = 0;
+ }
+ } while(CHIP_REG_READ32(HBC_MessageUnit, 0, host_int_status) & ARCMSR_HBCMU_OUTBOUND_POSTQUEUE_ISR);
}
/*
**********************************************************************
@@ -1988,8 +2187,8 @@
*****************************************************************************
*/
if((CHIP_REG_READ32(HBD_MessageUnit, 0, outboundlist_interrupt_cause) &
- ARCMSR_HBDMU_OUTBOUND_LIST_INTERRUPT) == 0)
- return;
+ ARCMSR_HBDMU_OUTBOUND_LIST_INTERRUPT) == 0)
+ return;
bus_dmamap_sync(acb->srb_dmat, acb->srb_dmamap,
BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
outbound_write_pointer = phbdmu->done_qbuffer[0].addressLow;
@@ -2006,6 +2205,34 @@
CHIP_REG_READ32(HBD_MessageUnit, 0, outboundlist_interrupt_cause); /*Dummy ioread32 to force pci flush */
}
/*
+**************************************************************************
+**************************************************************************
+*/
+static void arcmsr_hbe_postqueue_isr(struct AdapterControlBlock *acb)
+{
+ u_int16_t error;
+ uint32_t doneq_index;
+ uint16_t cmdSMID;
+
+ /*
+ *****************************************************************************
+ ** areca cdb command done
+ *****************************************************************************
+ */
+ bus_dmamap_sync(acb->srb_dmat, acb->srb_dmamap, BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
+ doneq_index = acb->doneq_index;
+ while ((CHIP_REG_READ32(HBE_MessageUnit, 0, reply_post_producer_index) & 0xFFFF) != doneq_index) {
+ cmdSMID = acb->pCompletionQ[doneq_index].cmdSMID;
+ error = (acb->pCompletionQ[doneq_index].cmdFlag & ARCMSR_SRBREPLY_FLAG_ERROR_MODE1) ? TRUE : FALSE;
+ arcmsr_drain_donequeue(acb, (u_int32_t)cmdSMID, error);
+ doneq_index++;
+ if (doneq_index >= acb->completionQ_entry)
+ doneq_index = 0;
+ }
+ acb->doneq_index = doneq_index;
+ CHIP_REG_WRITE32(HBE_MessageUnit, 0, reply_post_consumer_index, doneq_index);
+}
+/*
**********************************************************************
**********************************************************************
*/
@@ -2042,19 +2269,20 @@
static void arcmsr_handle_hbb_isr( struct AdapterControlBlock *acb)
{
u_int32_t outbound_doorbell;
+ struct HBB_MessageUnit *phbbmu = (struct HBB_MessageUnit *)acb->pmu;
/*
*********************************************
** check outbound intstatus
*********************************************
*/
- outbound_doorbell = CHIP_REG_READ32(HBB_DOORBELL, 0, iop2drv_doorbell) & acb->outbound_int_enable;
+ outbound_doorbell = READ_CHIP_REG32(0, phbbmu->iop2drv_doorbell) & acb->outbound_int_enable;
if(!outbound_doorbell) {
/*it must be share irq*/
return;
}
- CHIP_REG_WRITE32(HBB_DOORBELL, 0, iop2drv_doorbell, ~outbound_doorbell); /* clear doorbell interrupt */
- CHIP_REG_READ32(HBB_DOORBELL, 0, iop2drv_doorbell);
- CHIP_REG_WRITE32(HBB_DOORBELL, 0, drv2iop_doorbell, ARCMSR_DRV2IOP_END_OF_INTERRUPT);
+ WRITE_CHIP_REG32(0, phbbmu->iop2drv_doorbell, ~outbound_doorbell); /* clear doorbell interrupt */
+ READ_CHIP_REG32(0, phbbmu->iop2drv_doorbell);
+ WRITE_CHIP_REG32(0, phbbmu->drv2iop_doorbell, ARCMSR_DRV2IOP_END_OF_INTERRUPT);
/* MU ioctl transfer doorbell interrupts*/
if(outbound_doorbell & ARCMSR_IOP2DRV_DATA_WRITE_OK) {
arcmsr_iop2drv_data_wrote_handle(acb);
@@ -2082,19 +2310,24 @@
** check outbound intstatus
*********************************************
*/
- host_interrupt_status = CHIP_REG_READ32(HBC_MessageUnit, 0, host_int_status);
+ host_interrupt_status = CHIP_REG_READ32(HBC_MessageUnit, 0, host_int_status) &
+ (ARCMSR_HBCMU_OUTBOUND_POSTQUEUE_ISR |
+ ARCMSR_HBCMU_OUTBOUND_DOORBELL_ISR);
if(!host_interrupt_status) {
/*it must be share irq*/
return;
}
- /* MU doorbell interrupts*/
- if(host_interrupt_status & ARCMSR_HBCMU_OUTBOUND_DOORBELL_ISR) {
- arcmsr_hbc_doorbell_isr(acb);
- }
- /* MU post queue interrupts*/
- if(host_interrupt_status & ARCMSR_HBCMU_OUTBOUND_POSTQUEUE_ISR) {
- arcmsr_hbc_postqueue_isr(acb);
- }
+ do {
+ /* MU doorbell interrupts*/
+ if(host_interrupt_status & ARCMSR_HBCMU_OUTBOUND_DOORBELL_ISR) {
+ arcmsr_hbc_doorbell_isr(acb);
+ }
+ /* MU post queue interrupts*/
+ if(host_interrupt_status & ARCMSR_HBCMU_OUTBOUND_POSTQUEUE_ISR) {
+ arcmsr_hbc_postqueue_isr(acb);
+ }
+ host_interrupt_status = CHIP_REG_READ32(HBC_MessageUnit, 0, host_int_status);
+ } while (host_interrupt_status & (ARCMSR_HBCMU_OUTBOUND_POSTQUEUE_ISR | ARCMSR_HBCMU_OUTBOUND_DOORBELL_ISR));
}
/*
**********************************************************************
@@ -2130,6 +2363,37 @@
// CHIP_REG_READ32(HBD_MessageUnit, 0, pcief0_int_enable);
}
/*
+**********************************************************************
+**********************************************************************
+*/
+static void arcmsr_handle_hbe_isr( struct AdapterControlBlock *acb)
+{
+ u_int32_t host_interrupt_status;
+ /*
+ *********************************************
+ ** check outbound intstatus
+ *********************************************
+ */
+ host_interrupt_status = CHIP_REG_READ32(HBE_MessageUnit, 0, host_int_status) &
+ (ARCMSR_HBEMU_OUTBOUND_POSTQUEUE_ISR |
+ ARCMSR_HBEMU_OUTBOUND_DOORBELL_ISR);
+ if(!host_interrupt_status) {
+ /*it must be share irq*/
+ return;
+ }
+ do {
+ /* MU doorbell interrupts*/
+ if(host_interrupt_status & ARCMSR_HBEMU_OUTBOUND_DOORBELL_ISR) {
+ arcmsr_hbe_doorbell_isr(acb);
+ }
+ /* MU post queue interrupts*/
+ if(host_interrupt_status & ARCMSR_HBEMU_OUTBOUND_POSTQUEUE_ISR) {
+ arcmsr_hbe_postqueue_isr(acb);
+ }
+ host_interrupt_status = CHIP_REG_READ32(HBE_MessageUnit, 0, host_int_status);
+ } while (host_interrupt_status & (ARCMSR_HBEMU_OUTBOUND_POSTQUEUE_ISR | ARCMSR_HBEMU_OUTBOUND_DOORBELL_ISR));
+}
+/*
******************************************************************************
******************************************************************************
*/
@@ -2148,9 +2412,12 @@
case ACB_ADAPTER_TYPE_D:
arcmsr_handle_hbd_isr(acb);
break;
+ case ACB_ADAPTER_TYPE_E:
+ arcmsr_handle_hbe_isr(acb);
+ break;
default:
printf("arcmsr%d: interrupt service,"
- " unknow adapter type =%d\n", acb->pci_unit, acb->adapter_type);
+ " unknown adapter type =%d\n", acb->pci_unit, acb->adapter_type);
break;
}
}
@@ -2161,7 +2428,7 @@
static void arcmsr_intr_handler(void *arg)
{
struct AdapterControlBlock *acb = (struct AdapterControlBlock *)arg;
-
+
ARCMSR_LOCK_ACQUIRE(&acb->isr_lock);
arcmsr_interrupt(acb);
ARCMSR_LOCK_RELEASE(&acb->isr_lock);
@@ -2174,21 +2441,29 @@
{
struct AdapterControlBlock *acb = (struct AdapterControlBlock *)arg;
switch (acb->adapter_type) {
- case ACB_ADAPTER_TYPE_A:
- CHIP_REG_WRITE32(HBA_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_GET_CONFIG);
- break;
+ case ACB_ADAPTER_TYPE_A:
+ CHIP_REG_WRITE32(HBA_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_GET_CONFIG);
+ break;
- case ACB_ADAPTER_TYPE_B:
- CHIP_REG_WRITE32(HBB_DOORBELL, 0, drv2iop_doorbell, ARCMSR_MESSAGE_GET_CONFIG);
- break;
+ case ACB_ADAPTER_TYPE_B: {
+ struct HBB_MessageUnit *phbbmu = (struct HBB_MessageUnit *)acb->pmu;
+ WRITE_CHIP_REG32(0, phbbmu->drv2iop_doorbell, ARCMSR_MESSAGE_GET_CONFIG);
+ }
+ break;
- case ACB_ADAPTER_TYPE_C:
- CHIP_REG_WRITE32(HBC_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_GET_CONFIG);
- CHIP_REG_WRITE32(HBC_MessageUnit, 0, inbound_doorbell, ARCMSR_HBCMU_DRV2IOP_MESSAGE_CMD_DONE);
- break;
+ case ACB_ADAPTER_TYPE_C:
+ CHIP_REG_WRITE32(HBC_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_GET_CONFIG);
+ CHIP_REG_WRITE32(HBC_MessageUnit, 0, inbound_doorbell, ARCMSR_HBCMU_DRV2IOP_MESSAGE_CMD_DONE);
+ break;
- case ACB_ADAPTER_TYPE_D:
- CHIP_REG_WRITE32(HBD_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_GET_CONFIG);
+ case ACB_ADAPTER_TYPE_D:
+ CHIP_REG_WRITE32(HBD_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_GET_CONFIG);
+ break;
+
+ case ACB_ADAPTER_TYPE_E:
+ CHIP_REG_WRITE32(HBE_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_GET_CONFIG);
+ acb->out_doorbell ^= ARCMSR_HBEMU_DRV2IOP_MESSAGE_CMD_DONE;
+ CHIP_REG_WRITE32(HBE_MessageUnit, 0, iobound_doorbell, acb->out_doorbell);
break;
}
@@ -2222,11 +2497,11 @@
**
************************************************************************
*/
-u_int32_t arcmsr_iop_ioctlcmd(struct AdapterControlBlock *acb, u_int32_t ioctl_cmd, caddr_t arg)
+static u_int32_t arcmsr_iop_ioctlcmd(struct AdapterControlBlock *acb, u_int32_t ioctl_cmd, caddr_t arg)
{
struct CMD_MESSAGE_FIELD *pcmdmessagefld;
u_int32_t retvalue = EINVAL;
-
+
pcmdmessagefld = (struct CMD_MESSAGE_FIELD *) arg;
if(memcmp(pcmdmessagefld->cmdmessage.Signature, "ARCMSR", 6)!=0) {
return retvalue;
@@ -2237,7 +2512,7 @@
u_int8_t *pQbuffer;
u_int8_t *ptmpQbuffer = pcmdmessagefld->messagedatabuffer;
u_int32_t allxfer_len=0;
-
+
while((acb->rqbuf_firstindex != acb->rqbuf_lastindex)
&& (allxfer_len < 1031)) {
/*copy READ QBUFFER to srb*/
@@ -2251,7 +2526,7 @@
}
if(acb->acb_flags & ACB_F_IOPDATA_OVERFLOW) {
struct QBUFFER *prbuffer;
-
+
acb->acb_flags &= ~ACB_F_IOPDATA_OVERFLOW;
prbuffer = arcmsr_get_iop_rqbuffer(acb);
if(arcmsr_Read_iop_rqbuffer_data(acb, prbuffer) == 0)
@@ -2266,7 +2541,7 @@
u_int32_t my_empty_len, user_len, wqbuf_firstindex, wqbuf_lastindex;
u_int8_t *pQbuffer;
u_int8_t *ptmpuserbuffer = pcmdmessagefld->messagedatabuffer;
-
+
user_len = pcmdmessagefld->cmdmessage.Length;
/*check if data xfer length of this request will overflow my array qbuffer */
wqbuf_lastindex = acb->wqbuf_lastindex;
@@ -2276,7 +2551,7 @@
pcmdmessagefld->cmdmessage.ReturnCode = ARCMSR_MESSAGE_RETURNCODE_ERROR;
} else {
my_empty_len = (wqbuf_firstindex - wqbuf_lastindex - 1) &
- (ARCMSR_MAX_QBUFFER - 1);
+ (ARCMSR_MAX_QBUFFER - 1);
if(my_empty_len >= user_len) {
while(user_len > 0) {
/*copy srb data to wqbuffer*/
@@ -2303,7 +2578,7 @@
break;
case ARCMSR_MESSAGE_CLEAR_RQBUFFER: {
u_int8_t *pQbuffer = acb->rqbuffer;
-
+
if(acb->acb_flags & ACB_F_IOPDATA_OVERFLOW) {
acb->acb_flags &= ~ACB_F_IOPDATA_OVERFLOW;
arcmsr_iop_message_read(acb);
@@ -2320,10 +2595,10 @@
case ARCMSR_MESSAGE_CLEAR_WQBUFFER:
{
u_int8_t *pQbuffer = acb->wqbuffer;
-
+
if(acb->acb_flags & ACB_F_IOPDATA_OVERFLOW) {
acb->acb_flags &= ~ACB_F_IOPDATA_OVERFLOW;
- arcmsr_iop_message_read(acb);
+ arcmsr_iop_message_read(acb);
/*signature, let IOP know data has been readed */
}
acb->acb_flags |= (ACB_F_MESSAGE_WQBUFFER_CLEARED|ACB_F_MESSAGE_WQBUFFER_READ);
@@ -2336,10 +2611,10 @@
break;
case ARCMSR_MESSAGE_CLEAR_ALLQBUFFER: {
u_int8_t *pQbuffer;
-
+
if(acb->acb_flags & ACB_F_IOPDATA_OVERFLOW) {
acb->acb_flags &= ~ACB_F_IOPDATA_OVERFLOW;
- arcmsr_iop_message_read(acb);
+ arcmsr_iop_message_read(acb);
/*signature, let IOP know data has been readed */
}
acb->acb_flags |= (ACB_F_MESSAGE_WQBUFFER_CLEARED
@@ -2365,7 +2640,7 @@
case ARCMSR_MESSAGE_SAY_HELLO: {
u_int8_t *hello_string = "Hello! I am ARCMSR";
u_int8_t *puserbuffer = (u_int8_t *)pcmdmessagefld->messagedatabuffer;
-
+
if(memcpy(puserbuffer, hello_string, (int16_t)strlen(hello_string))) {
pcmdmessagefld->cmdmessage.ReturnCode = ARCMSR_MESSAGE_RETURNCODE_ERROR;
ARCMSR_LOCK_RELEASE(&acb->qbuffer_lock);
@@ -2396,7 +2671,7 @@
static void arcmsr_free_srb(struct CommandControlBlock *srb)
{
struct AdapterControlBlock *acb;
-
+
acb = srb->acb;
ARCMSR_LOCK_ACQUIRE(&acb->srb_lock);
srb->srb_state = ARCMSR_SRB_DONE;
@@ -2410,7 +2685,7 @@
**************************************************************************
**************************************************************************
*/
-struct CommandControlBlock *arcmsr_get_freesrb(struct AdapterControlBlock *acb)
+static struct CommandControlBlock *arcmsr_get_freesrb(struct AdapterControlBlock *acb)
{
struct CommandControlBlock *srb = NULL;
u_int32_t workingsrb_startindex, workingsrb_doneindex;
@@ -2438,12 +2713,13 @@
struct CMD_MESSAGE_FIELD *pcmdmessagefld;
int retvalue = 0, transfer_len = 0;
char *buffer;
- u_int32_t controlcode = (u_int32_t ) pccb->csio.cdb_io.cdb_bytes[5] << 24 |
- (u_int32_t ) pccb->csio.cdb_io.cdb_bytes[6] << 16 |
- (u_int32_t ) pccb->csio.cdb_io.cdb_bytes[7] << 8 |
- (u_int32_t ) pccb->csio.cdb_io.cdb_bytes[8];
+ uint8_t *ptr = scsiio_cdb_ptr(&pccb->csio);
+ u_int32_t controlcode = (u_int32_t ) ptr[5] << 24 |
+ (u_int32_t ) ptr[6] << 16 |
+ (u_int32_t ) ptr[7] << 8 |
+ (u_int32_t ) ptr[8];
/* 4 bytes: Areca io control code */
- if((pccb->ccb_h.flags & CAM_SCATTER_VALID) == 0) {
+ if ((pccb->ccb_h.flags & CAM_DATA_MASK) == CAM_DATA_VADDR) {
buffer = pccb->csio.data_ptr;
transfer_len = pccb->csio.dxfer_len;
} else {
@@ -2460,7 +2736,7 @@
u_int8_t *pQbuffer;
u_int8_t *ptmpQbuffer = pcmdmessagefld->messagedatabuffer;
int32_t allxfer_len = 0;
-
+
ARCMSR_LOCK_ACQUIRE(&acb->qbuffer_lock);
while ((acb->rqbuf_firstindex != acb->rqbuf_lastindex)
&& (allxfer_len < 1031)) {
@@ -2473,7 +2749,7 @@
}
if (acb->acb_flags & ACB_F_IOPDATA_OVERFLOW) {
struct QBUFFER *prbuffer;
-
+
acb->acb_flags &= ~ACB_F_IOPDATA_OVERFLOW;
prbuffer = arcmsr_get_iop_rqbuffer(acb);
if(arcmsr_Read_iop_rqbuffer_data(acb, prbuffer) == 0)
@@ -2489,7 +2765,7 @@
int32_t my_empty_len, user_len, wqbuf_firstindex, wqbuf_lastindex;
u_int8_t *pQbuffer;
u_int8_t *ptmpuserbuffer = pcmdmessagefld->messagedatabuffer;
-
+
user_len = pcmdmessagefld->cmdmessage.Length;
ARCMSR_LOCK_ACQUIRE(&acb->qbuffer_lock);
wqbuf_lastindex = acb->wqbuf_lastindex;
@@ -2497,7 +2773,7 @@
if (wqbuf_lastindex != wqbuf_firstindex) {
arcmsr_Write_data_2iop_wqbuffer(acb);
/* has error report sensedata */
- if(pccb->csio.sense_len) {
+ if(pccb->csio.sense_len) {
((u_int8_t *)&pccb->csio.sense_data)[0] = (0x1 << 7 | 0x70);
/* Valid,ErrorCode */
((u_int8_t *)&pccb->csio.sense_data)[2] = 0x05;
@@ -2545,7 +2821,7 @@
break;
case ARCMSR_MESSAGE_CLEAR_RQBUFFER: {
u_int8_t *pQbuffer = acb->rqbuffer;
-
+
ARCMSR_LOCK_ACQUIRE(&acb->qbuffer_lock);
if (acb->acb_flags & ACB_F_IOPDATA_OVERFLOW) {
acb->acb_flags &= ~ACB_F_IOPDATA_OVERFLOW;
@@ -2562,7 +2838,7 @@
break;
case ARCMSR_MESSAGE_CLEAR_WQBUFFER: {
u_int8_t *pQbuffer = acb->wqbuffer;
-
+
ARCMSR_LOCK_ACQUIRE(&acb->qbuffer_lock);
if (acb->acb_flags & ACB_F_IOPDATA_OVERFLOW) {
acb->acb_flags &= ~ACB_F_IOPDATA_OVERFLOW;
@@ -2581,7 +2857,7 @@
break;
case ARCMSR_MESSAGE_CLEAR_ALLQBUFFER: {
u_int8_t *pQbuffer;
-
+
ARCMSR_LOCK_ACQUIRE(&acb->qbuffer_lock);
if (acb->acb_flags & ACB_F_IOPDATA_OVERFLOW) {
acb->acb_flags &= ~ACB_F_IOPDATA_OVERFLOW;
@@ -2609,7 +2885,7 @@
break;
case ARCMSR_MESSAGE_SAY_HELLO: {
int8_t *hello_string = "Hello! I am ARCMSR";
-
+
memcpy(pcmdmessagefld->messagedatabuffer, hello_string
, (int16_t)strlen(hello_string));
pcmdmessagefld->cmdmessage.ReturnCode = ARCMSR_MESSAGE_RETURNCODE_OK;
@@ -2637,7 +2913,7 @@
struct AdapterControlBlock *acb = (struct AdapterControlBlock *)srb->acb;
union ccb *pccb;
int target, lun;
-
+
pccb = srb->pccb;
target = pccb->ccb_h.target_id;
lun = pccb->ccb_h.target_lun;
@@ -2668,7 +2944,7 @@
if(acb->devstate[target][lun] == ARECA_RAID_GONE) {
u_int8_t block_cmd, cmd;
- cmd = pccb->csio.cdb_io.cdb_bytes[0];
+ cmd = scsiio_cdb_ptr(&pccb->csio)[0];
block_cmd = cmd & 0x0f;
if(block_cmd == 0x08 || block_cmd == 0x0a) {
printf("arcmsr%d:block 'read/write' command "
@@ -2686,7 +2962,7 @@
arcmsr_srb_complete(srb, 0);
return;
}
- if(acb->srboutstandingcount >= acb->firm_numbers_queue) {
+ if(acb->srboutstandingcount >= acb->maxOutstanding) {
if((acb->acb_flags & ACB_F_CAM_DEV_QFRZN) == 0)
{
xpt_freeze_simq(acb->psim, 1);
@@ -2703,7 +2979,9 @@
if (pccb->ccb_h.timeout != CAM_TIME_INFINITY)
{
arcmsr_callout_init(&srb->ccb_callout);
- callout_reset(&srb->ccb_callout, ((pccb->ccb_h.timeout + (ARCMSR_TIMEOUT_DELAY * 1000)) * hz) / 1000, arcmsr_srb_timeout, srb);
+ callout_reset_sbt(&srb->ccb_callout, SBT_1MS *
+ (pccb->ccb_h.timeout + (ARCMSR_TIMEOUT_DELAY * 1000)), 0,
+ arcmsr_srb_timeout, srb, 0);
srb->srb_flags |= SRB_FLAG_TIMER_START;
}
}
@@ -2717,7 +2995,7 @@
struct AdapterControlBlock *acb = (struct AdapterControlBlock *) abortccb->ccb_h.arcmsr_ccbacb_ptr;
u_int32_t intmask_org;
int i = 0;
-
+
acb->num_aborts++;
/*
***************************************************************************
@@ -2736,10 +3014,10 @@
if(srb->srb_state == ARCMSR_SRB_START) {
if(srb->pccb == abortccb) {
srb->srb_state = ARCMSR_SRB_ABORTED;
- printf("arcmsr%d:scsi id=%d lun=%d abort srb '%p'"
+ printf("arcmsr%d:scsi id=%d lun=%jx abort srb '%p'"
"outstanding command \n"
, acb->pci_unit, abortccb->ccb_h.target_id
- , abortccb->ccb_h.target_lun, srb);
+ , (uintmax_t)abortccb->ccb_h.target_lun, srb);
arcmsr_polling_srbdone(acb, srb);
/* enable outbound Post Queue, outbound doorbell Interrupt */
arcmsr_enable_allintr(acb, intmask_org);
@@ -2759,7 +3037,7 @@
static void arcmsr_bus_reset(struct AdapterControlBlock *acb)
{
int retry = 0;
-
+
acb->num_resets++;
acb->acb_flags |= ACB_F_BUS_RESET;
while(acb->srboutstandingcount != 0 && retry < 400) {
@@ -2783,16 +3061,16 @@
return;
}
pccb->ccb_h.status |= CAM_REQ_CMP;
- switch (pccb->csio.cdb_io.cdb_bytes[0]) {
+ switch (scsiio_cdb_ptr(&pccb->csio)[0]) {
case INQUIRY: {
unsigned char inqdata[36];
char *buffer = pccb->csio.data_ptr;
inqdata[0] = T_PROCESSOR; /* Periph Qualifier & Periph Dev Type */
- inqdata[1] = 0; /* rem media bit & Dev Type Modifier */
- inqdata[2] = 0; /* ISO, ECMA, & ANSI versions */
+ inqdata[1] = 0; /* rem media bit & Dev Type Modifier */
+ inqdata[2] = 0; /* ISO, ECMA, & ANSI versions */
inqdata[3] = 0;
- inqdata[4] = 31; /* length of additional data */
+ inqdata[4] = 31; /* length of additional data */
inqdata[5] = 0;
inqdata[6] = 0;
inqdata[7] = 0;
@@ -2823,7 +3101,7 @@
static void arcmsr_action(struct cam_sim *psim, union ccb *pccb)
{
struct AdapterControlBlock *acb;
-
+
acb = (struct AdapterControlBlock *) cam_sim_softc(psim);
if(acb == NULL) {
pccb->ccb_h.status |= CAM_REQ_INVALID;
@@ -2834,7 +3112,14 @@
case XPT_SCSI_IO: {
struct CommandControlBlock *srb;
int target = pccb->ccb_h.target_id;
-
+ int error;
+
+ if (pccb->ccb_h.flags & CAM_CDB_PHYS) {
+ pccb->ccb_h.status = CAM_REQ_INVALID;
+ xpt_done(pccb);
+ return;
+ }
+
if(target == 16) {
/* virtual device for iop message transfer */
arcmsr_handle_virtual_command(acb, pccb);
@@ -2848,61 +3133,16 @@
pccb->ccb_h.arcmsr_ccbsrb_ptr = srb;
pccb->ccb_h.arcmsr_ccbacb_ptr = acb;
srb->pccb = pccb;
- if((pccb->ccb_h.flags & CAM_DIR_MASK) != CAM_DIR_NONE) {
- if(!(pccb->ccb_h.flags & CAM_SCATTER_VALID)) {
- /* Single buffer */
- if(!(pccb->ccb_h.flags & CAM_DATA_PHYS)) {
- /* Buffer is virtual */
- u_int32_t error, s;
-
- s = splsoftvm();
- error = bus_dmamap_load(acb->dm_segs_dmat
- , srb->dm_segs_dmamap
- , pccb->csio.data_ptr
- , pccb->csio.dxfer_len
- , arcmsr_execute_srb, srb, /*flags*/0);
- if(error == EINPROGRESS) {
- xpt_freeze_simq(acb->psim, 1);
- pccb->ccb_h.status |= CAM_RELEASE_SIMQ;
- }
- splx(s);
- }
- else { /* Buffer is physical */
-#ifdef PAE
- panic("arcmsr: CAM_DATA_PHYS not supported");
-#else
- struct bus_dma_segment seg;
-
- seg.ds_addr = (bus_addr_t)pccb->csio.data_ptr;
- seg.ds_len = pccb->csio.dxfer_len;
- arcmsr_execute_srb(srb, &seg, 1, 0);
-#endif
- }
- } else {
- /* Scatter/gather list */
- struct bus_dma_segment *segs;
-
- if((pccb->ccb_h.flags & CAM_SG_LIST_PHYS) == 0
- || (pccb->ccb_h.flags & CAM_DATA_PHYS) != 0) {
- pccb->ccb_h.status |= CAM_PROVIDE_FAIL;
- xpt_done(pccb);
- free(srb, M_DEVBUF);
- return;
- }
- segs = (struct bus_dma_segment *)pccb->csio.data_ptr;
- arcmsr_execute_srb(srb, segs, pccb->csio.sglist_cnt, 0);
- }
- } else {
- arcmsr_execute_srb(srb, NULL, 0, 0);
+ error = bus_dmamap_load_ccb(acb->dm_segs_dmat
+ , srb->dm_segs_dmamap
+ , pccb
+ , arcmsr_execute_srb, srb, /*flags*/0);
+ if(error == EINPROGRESS) {
+ xpt_freeze_simq(acb->psim, 1);
+ pccb->ccb_h.status |= CAM_RELEASE_SIMQ;
}
break;
}
- case XPT_TARGET_IO: {
- /* target mode not yet support vendor specific commands. */
- pccb->ccb_h.status |= CAM_REQ_CMP;
- xpt_done(pccb);
- break;
- }
case XPT_PATH_INQ: {
struct ccb_pathinq *cpi = &pccb->cpi;
@@ -2915,16 +3155,19 @@
cpi->max_lun = ARCMSR_MAX_TARGETLUN; /* 0-7 */
cpi->initiator_id = ARCMSR_SCSI_INITIATOR_ID; /* 255 */
cpi->bus_id = cam_sim_bus(psim);
- strncpy(cpi->sim_vid, "FreeBSD", SIM_IDLEN);
- strncpy(cpi->hba_vid, "ARCMSR", HBA_IDLEN);
- strncpy(cpi->dev_name, cam_sim_name(psim), DEV_IDLEN);
+ strlcpy(cpi->sim_vid, "FreeBSD", SIM_IDLEN);
+ strlcpy(cpi->hba_vid, "ARCMSR", HBA_IDLEN);
+ strlcpy(cpi->dev_name, cam_sim_name(psim), DEV_IDLEN);
cpi->unit_number = cam_sim_unit(psim);
#ifdef CAM_NEW_TRAN_CODE
- if(acb->adapter_bus_speed == ACB_BUS_SPEED_6G)
+ if(acb->adapter_bus_speed == ACB_BUS_SPEED_12G)
+ cpi->base_transfer_speed = 1200000;
+ else if(acb->adapter_bus_speed == ACB_BUS_SPEED_6G)
cpi->base_transfer_speed = 600000;
else
cpi->base_transfer_speed = 300000;
if((acb->vendor_device_id == PCIDevVenIDARC1880) ||
+ (acb->vendor_device_id == PCIDevVenIDARC1884) ||
(acb->vendor_device_id == PCIDevVenIDARC1680) ||
(acb->vendor_device_id == PCIDevVenIDARC1214))
{
@@ -2950,7 +3193,6 @@
pabort_ccb = pccb->cab.abort_ccb;
switch (pabort_ccb->ccb_h.func_code) {
case XPT_ACCEPT_TARGET_IO:
- case XPT_IMMED_NOTIFY:
case XPT_CONT_TARGET_IO:
if(arcmsr_seek_cmd2abort(pabort_ccb)==TRUE) {
pabort_ccb->ccb_h.status |= CAM_REQ_ABORTED;
@@ -2974,8 +3216,8 @@
}
case XPT_RESET_BUS:
case XPT_RESET_DEV: {
- u_int32_t i;
-
+ u_int32_t i;
+
arcmsr_bus_reset(acb);
for (i=0; i < 500; i++) {
DELAY(1000);
@@ -2991,7 +3233,7 @@
}
case XPT_GET_TRAN_SETTINGS: {
struct ccb_trans_settings *cts;
-
+
if(pccb->ccb_h.target_id == 16) {
pccb->ccb_h.status |= CAM_FUNC_NOTAVAIL;
xpt_done(pccb);
@@ -3003,7 +3245,7 @@
struct ccb_trans_settings_scsi *scsi;
struct ccb_trans_settings_spi *spi;
struct ccb_trans_settings_sas *sas;
-
+
scsi = &cts->proto_specific.scsi;
scsi->flags = CTS_SCSI_FLAGS_TAG_ENB;
scsi->valid = CTS_SCSI_VALID_TQ;
@@ -3010,6 +3252,7 @@
cts->protocol = PROTO_SCSI;
if((acb->vendor_device_id == PCIDevVenIDARC1880) ||
+ (acb->vendor_device_id == PCIDevVenIDARC1884) ||
(acb->vendor_device_id == PCIDevVenIDARC1680) ||
(acb->vendor_device_id == PCIDevVenIDARC1214))
{
@@ -3018,10 +3261,11 @@
cts->transport = XPORT_SAS;
sas = &cts->xport_specific.sas;
sas->valid = CTS_SAS_VALID_SPEED;
- if((acb->vendor_device_id == PCIDevVenIDARC1880) ||
- (acb->vendor_device_id == PCIDevVenIDARC1214))
+ if (acb->adapter_bus_speed == ACB_BUS_SPEED_12G)
+ sas->bitrate = 1200000;
+ else if(acb->adapter_bus_speed == ACB_BUS_SPEED_6G)
sas->bitrate = 600000;
- else if(acb->vendor_device_id == PCIDevVenIDARC1680)
+ else if(acb->adapter_bus_speed == ACB_BUS_SPEED_3G)
sas->bitrate = 300000;
}
else
@@ -3031,7 +3275,10 @@
cts->transport = XPORT_SPI;
spi = &cts->xport_specific.spi;
spi->flags = CTS_SPI_FLAGS_DISC_ENB;
- spi->sync_period = 2;
+ if (acb->adapter_bus_speed == ACB_BUS_SPEED_6G)
+ spi->sync_period = 1;
+ else
+ spi->sync_period = 2;
spi->sync_offset = 32;
spi->bus_width = MSG_EXT_WDTR_BUS_16_BIT;
spi->valid = CTS_SPI_VALID_DISC
@@ -3043,7 +3290,10 @@
#else
{
cts->flags = (CCB_TRANS_DISC_ENB | CCB_TRANS_TAG_ENB);
- cts->sync_period = 2;
+ if (acb->adapter_bus_speed == ACB_BUS_SPEED_6G)
+ cts->sync_period = 1;
+ else
+ cts->sync_period = 2;
cts->sync_offset = 32;
cts->bus_width = MSG_EXT_WDTR_BUS_16_BIT;
cts->valid = CCB_TRANS_SYNC_RATE_VALID |
@@ -3126,8 +3376,9 @@
*/
static void arcmsr_start_hbb_bgrb(struct AdapterControlBlock *acb)
{
+ struct HBB_MessageUnit *phbbmu = (struct HBB_MessageUnit *)acb->pmu;
acb->acb_flags |= ACB_F_MSG_START_BGRB;
- CHIP_REG_WRITE32(HBB_DOORBELL, 0, drv2iop_doorbell, ARCMSR_MESSAGE_START_BGRB);
+ WRITE_CHIP_REG32(0, phbbmu->drv2iop_doorbell, ARCMSR_MESSAGE_START_BGRB);
if(!arcmsr_hbb_wait_msgint_ready(acb)) {
printf( "arcmsr%d: wait 'start adapter background rebulid' timeout \n", acb->pci_unit);
}
@@ -3161,6 +3412,20 @@
**********************************************************************
**********************************************************************
*/
+static void arcmsr_start_hbe_bgrb(struct AdapterControlBlock *acb)
+{
+ acb->acb_flags |= ACB_F_MSG_START_BGRB;
+ CHIP_REG_WRITE32(HBE_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_START_BGRB);
+ acb->out_doorbell ^= ARCMSR_HBEMU_DRV2IOP_MESSAGE_CMD_DONE;
+ CHIP_REG_WRITE32(HBE_MessageUnit, 0, iobound_doorbell, acb->out_doorbell);
+ if(!arcmsr_hbe_wait_msgint_ready(acb)) {
+ printf("arcmsr%d: wait 'start adapter background rebulid' timeout \n", acb->pci_unit);
+ }
+}
+/*
+**********************************************************************
+**********************************************************************
+*/
static void arcmsr_start_adapter_bgrb(struct AdapterControlBlock *acb)
{
switch (acb->adapter_type) {
@@ -3176,6 +3441,9 @@
case ACB_ADAPTER_TYPE_D:
arcmsr_start_hbd_bgrb(acb);
break;
+ case ACB_ADAPTER_TYPE_E:
+ arcmsr_start_hbe_bgrb(acb);
+ break;
}
}
/*
@@ -3188,7 +3456,7 @@
struct CommandControlBlock *srb;
u_int32_t flag_srb, outbound_intstatus, poll_srb_done=0, poll_count=0;
u_int16_t error;
-
+
polling_ccb_retry:
poll_count++;
outbound_intstatus=CHIP_REG_READ32(HBA_MessageUnit, 0, outbound_intstatus) & acb->outbound_int_enable;
@@ -3210,15 +3478,15 @@
/* check if command done with no error*/
srb = (struct CommandControlBlock *)
(acb->vir2phy_offset+(flag_srb << 5));/*frame must be 32 bytes aligned*/
- error = (flag_srb & ARCMSR_SRBREPLY_FLAG_ERROR_MODE0)?TRUE:FALSE;
+ error = (flag_srb & ARCMSR_SRBREPLY_FLAG_ERROR_MODE0)?TRUE:FALSE;
poll_srb_done = (srb == poll_srb) ? 1:0;
if((srb->acb != acb) || (srb->srb_state != ARCMSR_SRB_START)) {
if(srb->srb_state == ARCMSR_SRB_ABORTED) {
- printf("arcmsr%d: scsi id=%d lun=%d srb='%p'"
+ printf("arcmsr%d: scsi id=%d lun=%jx srb='%p'"
"poll command abort successfully \n"
, acb->pci_unit
, srb->pccb->ccb_h.target_id
- , srb->pccb->ccb_h.target_lun, srb);
+ , (uintmax_t)srb->pccb->ccb_h.target_lun, srb);
srb->pccb->ccb_h.status |= CAM_REQ_ABORTED;
arcmsr_srb_complete(srb, 1);
continue;
@@ -3244,11 +3512,10 @@
u_int32_t flag_srb, poll_srb_done=0, poll_count=0;
int index;
u_int16_t error;
-
+
polling_ccb_retry:
poll_count++;
- CHIP_REG_WRITE32(HBB_DOORBELL,
- 0, iop2drv_doorbell, ARCMSR_DOORBELL_INT_CLEAR_PATTERN); /* clear doorbell interrupt */
+ WRITE_CHIP_REG32(0, phbbmu->iop2drv_doorbell, ARCMSR_DOORBELL_INT_CLEAR_PATTERN); /* clear doorbell interrupt */
bus_dmamap_sync(acb->srb_dmat, acb->srb_dmamap, BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE);
while(1) {
index = phbbmu->doneq_index;
@@ -3257,7 +3524,7 @@
break;/*chip FIFO no ccb for completion already*/
} else {
UDELAY(25000);
- if ((poll_count > 100) && (poll_srb != NULL)) {
+ if ((poll_count > 100) && (poll_srb != NULL)) {
break;
}
goto polling_ccb_retry;
@@ -3270,15 +3537,15 @@
/* check if command done with no error*/
srb = (struct CommandControlBlock *)
(acb->vir2phy_offset+(flag_srb << 5));/*frame must be 32 bytes aligned*/
- error = (flag_srb & ARCMSR_SRBREPLY_FLAG_ERROR_MODE0)?TRUE:FALSE;
+ error = (flag_srb & ARCMSR_SRBREPLY_FLAG_ERROR_MODE0)?TRUE:FALSE;
poll_srb_done = (srb == poll_srb) ? 1:0;
if((srb->acb != acb) || (srb->srb_state != ARCMSR_SRB_START)) {
if(srb->srb_state == ARCMSR_SRB_ABORTED) {
- printf("arcmsr%d: scsi id=%d lun=%d srb='%p'"
+ printf("arcmsr%d: scsi id=%d lun=%jx srb='%p'"
"poll command abort successfully \n"
, acb->pci_unit
, srb->pccb->ccb_h.target_id
- , srb->pccb->ccb_h.target_lun, srb);
+ , (uintmax_t)srb->pccb->ccb_h.target_lun, srb);
srb->pccb->ccb_h.status |= CAM_REQ_ABORTED;
arcmsr_srb_complete(srb, 1);
continue;
@@ -3302,7 +3569,7 @@
struct CommandControlBlock *srb;
u_int32_t flag_srb, poll_srb_done=0, poll_count=0;
u_int16_t error;
-
+
polling_ccb_retry:
poll_count++;
bus_dmamap_sync(acb->srb_dmat, acb->srb_dmamap, BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE);
@@ -3312,12 +3579,12 @@
break;/*chip FIFO no ccb for completion already*/
} else {
UDELAY(25000);
- if ((poll_count > 100) && (poll_srb != NULL)) {
+ if ((poll_count > 100) && (poll_srb != NULL)) {
break;
}
- if (acb->srboutstandingcount == 0) {
+ if (acb->srboutstandingcount == 0) {
break;
- }
+ }
goto polling_ccb_retry;
}
}
@@ -3324,13 +3591,13 @@
flag_srb = CHIP_REG_READ32(HBC_MessageUnit, 0, outbound_queueport_low);
/* check if command done with no error*/
srb = (struct CommandControlBlock *)(acb->vir2phy_offset+(flag_srb & 0xFFFFFFE0));/*frame must be 32 bytes aligned*/
- error = (flag_srb & ARCMSR_SRBREPLY_FLAG_ERROR_MODE1)?TRUE:FALSE;
+ error = (flag_srb & ARCMSR_SRBREPLY_FLAG_ERROR_MODE1)?TRUE:FALSE;
if (poll_srb != NULL)
poll_srb_done = (srb == poll_srb) ? 1:0;
if((srb->acb != acb) || (srb->srb_state != ARCMSR_SRB_START)) {
if(srb->srb_state == ARCMSR_SRB_ABORTED) {
- printf("arcmsr%d: scsi id=%d lun=%d srb='%p'poll command abort successfully \n"
- , acb->pci_unit, srb->pccb->ccb_h.target_id, srb->pccb->ccb_h.target_lun, srb);
+ printf("arcmsr%d: scsi id=%d lun=%jx srb='%p'poll command abort successfully \n"
+ , acb->pci_unit, srb->pccb->ccb_h.target_id, (uintmax_t)srb->pccb->ccb_h.target_lun, srb);
srb->pccb->ccb_h.status |= CAM_REQ_ABORTED;
arcmsr_srb_complete(srb, 1);
continue;
@@ -3354,7 +3621,7 @@
u_int32_t flag_srb, poll_srb_done=0, poll_count=0;
u_int32_t outbound_write_pointer;
u_int16_t error, doneq_index;
-
+
polling_ccb_retry:
poll_count++;
bus_dmamap_sync(acb->srb_dmat, acb->srb_dmamap, BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE);
@@ -3366,12 +3633,12 @@
break;/*chip FIFO no ccb for completion already*/
} else {
UDELAY(25000);
- if ((poll_count > 100) && (poll_srb != NULL)) {
+ if ((poll_count > 100) && (poll_srb != NULL)) {
break;
}
- if (acb->srboutstandingcount == 0) {
- break;
- }
+ if (acb->srboutstandingcount == 0) {
+ break;
+ }
goto polling_ccb_retry;
}
}
@@ -3379,14 +3646,14 @@
flag_srb = phbdmu->done_qbuffer[(doneq_index & 0xFF)+1].addressLow;
/* check if command done with no error*/
srb = (struct CommandControlBlock *)(acb->vir2phy_offset+(flag_srb & 0xFFFFFFE0));/*frame must be 32 bytes aligned*/
- error = (flag_srb & ARCMSR_SRBREPLY_FLAG_ERROR_MODE1) ? TRUE : FALSE;
+ error = (flag_srb & ARCMSR_SRBREPLY_FLAG_ERROR_MODE1) ? TRUE : FALSE;
CHIP_REG_WRITE32(HBD_MessageUnit, 0, outboundlist_read_pointer, doneq_index);
if (poll_srb != NULL)
poll_srb_done = (srb == poll_srb) ? 1:0;
if((srb->acb != acb) || (srb->srb_state != ARCMSR_SRB_START)) {
if(srb->srb_state == ARCMSR_SRB_ABORTED) {
- printf("arcmsr%d: scsi id=%d lun=%d srb='%p'poll command abort successfully \n"
- , acb->pci_unit, srb->pccb->ccb_h.target_id, srb->pccb->ccb_h.target_lun, srb);
+ printf("arcmsr%d: scsi id=%d lun=%jx srb='%p'poll command abort successfully \n"
+ , acb->pci_unit, srb->pccb->ccb_h.target_id, (uintmax_t)srb->pccb->ccb_h.target_lun, srb);
srb->pccb->ccb_h.status |= CAM_REQ_ABORTED;
arcmsr_srb_complete(srb, 1);
continue;
@@ -3400,8 +3667,63 @@
}
/*
**********************************************************************
+**
**********************************************************************
*/
+static void arcmsr_polling_hbe_srbdone(struct AdapterControlBlock *acb, struct CommandControlBlock *poll_srb)
+{
+ struct CommandControlBlock *srb;
+ u_int32_t poll_srb_done=0, poll_count=0, doneq_index;
+ u_int16_t error, cmdSMID;
+
+polling_ccb_retry:
+ poll_count++;
+ bus_dmamap_sync(acb->srb_dmat, acb->srb_dmamap, BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE);
+ while(1) {
+ doneq_index = acb->doneq_index;
+ if((CHIP_REG_READ32(HBE_MessageUnit, 0, reply_post_producer_index) & 0xFFFF) == doneq_index) {
+ if(poll_srb_done) {
+ break;/*chip FIFO no ccb for completion already*/
+ } else {
+ UDELAY(25000);
+ if ((poll_count > 100) && (poll_srb != NULL)) {
+ break;
+ }
+ if (acb->srboutstandingcount == 0) {
+ break;
+ }
+ goto polling_ccb_retry;
+ }
+ }
+ cmdSMID = acb->pCompletionQ[doneq_index].cmdSMID;
+ doneq_index++;
+ if (doneq_index >= acb->completionQ_entry)
+ doneq_index = 0;
+ acb->doneq_index = doneq_index;
+ srb = acb->psrb_pool[cmdSMID];
+ error = (acb->pCompletionQ[doneq_index].cmdFlag & ARCMSR_SRBREPLY_FLAG_ERROR_MODE1) ? TRUE : FALSE;
+ if (poll_srb != NULL)
+ poll_srb_done = (srb == poll_srb) ? 1:0;
+ if((srb->acb != acb) || (srb->srb_state != ARCMSR_SRB_START)) {
+ if(srb->srb_state == ARCMSR_SRB_ABORTED) {
+ printf("arcmsr%d: scsi id=%d lun=%jx srb='%p'poll command abort successfully \n"
+ , acb->pci_unit, srb->pccb->ccb_h.target_id, (uintmax_t)srb->pccb->ccb_h.target_lun, srb);
+ srb->pccb->ccb_h.status |= CAM_REQ_ABORTED;
+ arcmsr_srb_complete(srb, 1);
+ continue;
+ }
+ printf("arcmsr%d: polling get an illegal srb command done srb='%p'srboutstandingcount=%d \n"
+ , acb->pci_unit, srb, acb->srboutstandingcount);
+ continue;
+ }
+ arcmsr_report_srb_state(acb, srb, error);
+ } /*drain reply FIFO*/
+ CHIP_REG_WRITE32(HBE_MessageUnit, 0, reply_post_producer_index, doneq_index);
+}
+/*
+**********************************************************************
+**********************************************************************
+*/
static void arcmsr_polling_srbdone(struct AdapterControlBlock *acb, struct CommandControlBlock *poll_srb)
{
switch (acb->adapter_type) {
@@ -3421,6 +3743,10 @@
arcmsr_polling_hbd_srbdone(acb, poll_srb);
}
break;
+ case ACB_ADAPTER_TYPE_E: {
+ arcmsr_polling_hbe_srbdone(acb, poll_srb);
+ }
+ break;
}
}
/*
@@ -3436,7 +3762,7 @@
size_t iop_firm_version = offsetof(struct HBA_MessageUnit,msgcode_rwbuffer[ARCMSR_FW_VERS_OFFSET]); /*firm_version,17,68-83*/
size_t iop_device_map = offsetof(struct HBA_MessageUnit,msgcode_rwbuffer[ARCMSR_FW_DEVMAP_OFFSET]);
int i;
-
+
CHIP_REG_WRITE32(HBA_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_GET_CONFIG);
if(!arcmsr_hba_wait_msgint_ready(acb)) {
printf("arcmsr%d: wait 'get adapter firmware miscellaneous data' timeout \n", acb->pci_unit);
@@ -3461,13 +3787,16 @@
acb_device_map++;
i++;
}
- printf("ARECA RAID ADAPTER%d: %s \n", acb->pci_unit, ARCMSR_DRIVER_VERSION);
- printf("ARECA RAID ADAPTER%d: FIRMWARE VERSION %s \n", acb->pci_unit, acb->firm_version);
+ printf("Areca RAID adapter%d: %s F/W version %s \n", acb->pci_unit, acb->firm_model, acb->firm_version);
acb->firm_request_len = CHIP_REG_READ32(HBA_MessageUnit, 0, msgcode_rwbuffer[1]); /*firm_request_len, 1, 04-07*/
acb->firm_numbers_queue = CHIP_REG_READ32(HBA_MessageUnit, 0, msgcode_rwbuffer[2]); /*firm_numbers_queue, 2, 08-11*/
acb->firm_sdram_size = CHIP_REG_READ32(HBA_MessageUnit, 0, msgcode_rwbuffer[3]); /*firm_sdram_size, 3, 12-15*/
acb->firm_ide_channels = CHIP_REG_READ32(HBA_MessageUnit, 0, msgcode_rwbuffer[4]); /*firm_ide_channels, 4, 16-19*/
acb->firm_cfg_version = CHIP_REG_READ32(HBA_MessageUnit, 0, msgcode_rwbuffer[ARCMSR_FW_CFGVER_OFFSET]); /*firm_cfg_version, 25, */
+ if(acb->firm_numbers_queue > ARCMSR_MAX_OUTSTANDING_CMD)
+ acb->maxOutstanding = ARCMSR_MAX_OUTSTANDING_CMD - 1;
+ else
+ acb->maxOutstanding = acb->firm_numbers_queue - 1;
}
/*
**********************************************************************
@@ -3475,6 +3804,7 @@
*/
static void arcmsr_get_hbb_config(struct AdapterControlBlock *acb)
{
+ struct HBB_MessageUnit *phbbmu = (struct HBB_MessageUnit *)acb->pmu;
char *acb_firm_model = acb->firm_model;
char *acb_firm_version = acb->firm_version;
char *acb_device_map = acb->device_map;
@@ -3482,8 +3812,8 @@
size_t iop_firm_version = offsetof(struct HBB_RWBUFFER, msgcode_rwbuffer[ARCMSR_FW_VERS_OFFSET]); /*firm_version,17,68-83*/
size_t iop_device_map = offsetof(struct HBB_RWBUFFER, msgcode_rwbuffer[ARCMSR_FW_DEVMAP_OFFSET]);
int i;
-
- CHIP_REG_WRITE32(HBB_DOORBELL, 0, drv2iop_doorbell, ARCMSR_MESSAGE_GET_CONFIG);
+
+ WRITE_CHIP_REG32(0, phbbmu->drv2iop_doorbell, ARCMSR_MESSAGE_GET_CONFIG);
if(!arcmsr_hbb_wait_msgint_ready(acb)) {
printf( "arcmsr%d: wait" "'get adapter firmware miscellaneous data' timeout \n", acb->pci_unit);
}
@@ -3507,13 +3837,16 @@
acb_device_map++;
i++;
}
- printf("ARECA RAID ADAPTER%d: %s \n", acb->pci_unit, ARCMSR_DRIVER_VERSION);
- printf("ARECA RAID ADAPTER%d: FIRMWARE VERSION %s \n", acb->pci_unit, acb->firm_version);
+ printf("Areca RAID adapter%d: %s F/W version %s \n", acb->pci_unit, acb->firm_model, acb->firm_version);
acb->firm_request_len = CHIP_REG_READ32(HBB_RWBUFFER, 1, msgcode_rwbuffer[1]); /*firm_request_len, 1, 04-07*/
acb->firm_numbers_queue = CHIP_REG_READ32(HBB_RWBUFFER, 1, msgcode_rwbuffer[2]); /*firm_numbers_queue, 2, 08-11*/
acb->firm_sdram_size = CHIP_REG_READ32(HBB_RWBUFFER, 1, msgcode_rwbuffer[3]); /*firm_sdram_size, 3, 12-15*/
acb->firm_ide_channels = CHIP_REG_READ32(HBB_RWBUFFER, 1, msgcode_rwbuffer[4]); /*firm_ide_channels, 4, 16-19*/
acb->firm_cfg_version = CHIP_REG_READ32(HBB_RWBUFFER, 1, msgcode_rwbuffer[ARCMSR_FW_CFGVER_OFFSET]); /*firm_cfg_version, 25, */
+ if(acb->firm_numbers_queue > ARCMSR_MAX_HBB_POSTQUEUE)
+ acb->maxOutstanding = ARCMSR_MAX_HBB_POSTQUEUE - 1;
+ else
+ acb->maxOutstanding = acb->firm_numbers_queue - 1;
}
/*
**********************************************************************
@@ -3528,7 +3861,7 @@
size_t iop_firm_version = offsetof(struct HBC_MessageUnit,msgcode_rwbuffer[ARCMSR_FW_VERS_OFFSET]); /*firm_version,17,68-83*/
size_t iop_device_map = offsetof(struct HBC_MessageUnit,msgcode_rwbuffer[ARCMSR_FW_DEVMAP_OFFSET]);
int i;
-
+
CHIP_REG_WRITE32(HBC_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_GET_CONFIG);
CHIP_REG_WRITE32(HBC_MessageUnit, 0, inbound_doorbell, ARCMSR_HBCMU_DRV2IOP_MESSAGE_CMD_DONE);
if(!arcmsr_hbc_wait_msgint_ready(acb)) {
@@ -3554,13 +3887,16 @@
acb_device_map++;
i++;
}
- printf("ARECA RAID ADAPTER%d: %s \n", acb->pci_unit, ARCMSR_DRIVER_VERSION);
- printf("ARECA RAID ADAPTER%d: FIRMWARE VERSION %s \n", acb->pci_unit, acb->firm_version);
+ printf("Areca RAID adapter%d: %s F/W version %s \n", acb->pci_unit, acb->firm_model, acb->firm_version);
acb->firm_request_len = CHIP_REG_READ32(HBC_MessageUnit, 0, msgcode_rwbuffer[1]); /*firm_request_len, 1, 04-07*/
acb->firm_numbers_queue = CHIP_REG_READ32(HBC_MessageUnit, 0, msgcode_rwbuffer[2]); /*firm_numbers_queue, 2, 08-11*/
acb->firm_sdram_size = CHIP_REG_READ32(HBC_MessageUnit, 0, msgcode_rwbuffer[3]); /*firm_sdram_size, 3, 12-15*/
acb->firm_ide_channels = CHIP_REG_READ32(HBC_MessageUnit, 0, msgcode_rwbuffer[4]); /*firm_ide_channels, 4, 16-19*/
acb->firm_cfg_version = CHIP_REG_READ32(HBC_MessageUnit, 0, msgcode_rwbuffer[ARCMSR_FW_CFGVER_OFFSET]); /*firm_cfg_version, 25, */
+ if(acb->firm_numbers_queue > ARCMSR_MAX_OUTSTANDING_CMD)
+ acb->maxOutstanding = ARCMSR_MAX_OUTSTANDING_CMD - 1;
+ else
+ acb->maxOutstanding = acb->firm_numbers_queue - 1;
}
/*
**********************************************************************
@@ -3575,7 +3911,7 @@
size_t iop_firm_version = offsetof(struct HBD_MessageUnit, msgcode_rwbuffer[ARCMSR_FW_VERS_OFFSET]); /*firm_version,17,68-83*/
size_t iop_device_map = offsetof(struct HBD_MessageUnit, msgcode_rwbuffer[ARCMSR_FW_DEVMAP_OFFSET]);
int i;
-
+
if(CHIP_REG_READ32(HBD_MessageUnit, 0, outbound_doorbell) & ARCMSR_HBDMU_IOP2DRV_MESSAGE_CMD_DONE)
CHIP_REG_WRITE32(HBD_MessageUnit, 0, outbound_doorbell, ARCMSR_HBDMU_IOP2DRV_MESSAGE_CMD_DONE_CLEAR);
CHIP_REG_WRITE32(HBD_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_GET_CONFIG);
@@ -3602,18 +3938,73 @@
acb_device_map++;
i++;
}
- printf("ARECA RAID ADAPTER%d: %s \n", acb->pci_unit, ARCMSR_DRIVER_VERSION);
- printf("ARECA RAID ADAPTER%d: FIRMWARE VERSION %s \n", acb->pci_unit, acb->firm_version);
- acb->firm_request_len = CHIP_REG_READ32(HBD_MessageUnit, 0, msgcode_rwbuffer[2]); /*firm_request_len, 1, 04-07*/
- acb->firm_numbers_queue = CHIP_REG_READ32(HBD_MessageUnit, 0, msgcode_rwbuffer[3]); /*firm_numbers_queue, 2, 08-11*/
- acb->firm_sdram_size = CHIP_REG_READ32(HBD_MessageUnit, 0, msgcode_rwbuffer[4]); /*firm_sdram_size, 3, 12-15*/
- acb->firm_ide_channels = CHIP_REG_READ32(HBD_MessageUnit, 0, msgcode_rwbuffer[5]); /*firm_ide_channels, 4, 16-19*/
+ printf("Areca RAID adapter%d: %s F/W version %s \n", acb->pci_unit, acb->firm_model, acb->firm_version);
+ acb->firm_request_len = CHIP_REG_READ32(HBD_MessageUnit, 0, msgcode_rwbuffer[1]); /*firm_request_len, 1, 04-07*/
+ acb->firm_numbers_queue = CHIP_REG_READ32(HBD_MessageUnit, 0, msgcode_rwbuffer[2]); /*firm_numbers_queue, 2, 08-11*/
+ acb->firm_sdram_size = CHIP_REG_READ32(HBD_MessageUnit, 0, msgcode_rwbuffer[3]); /*firm_sdram_size, 3, 12-15*/
+ acb->firm_ide_channels = CHIP_REG_READ32(HBD_MessageUnit, 0, msgcode_rwbuffer[4]); /*firm_ide_channels, 4, 16-19*/
acb->firm_cfg_version = CHIP_REG_READ32(HBD_MessageUnit, 0, msgcode_rwbuffer[ARCMSR_FW_CFGVER_OFFSET]); /*firm_cfg_version, 25, */
+ if(acb->firm_numbers_queue > ARCMSR_MAX_HBD_POSTQUEUE)
+ acb->maxOutstanding = ARCMSR_MAX_HBD_POSTQUEUE - 1;
+ else
+ acb->maxOutstanding = acb->firm_numbers_queue - 1;
}
/*
**********************************************************************
**********************************************************************
*/
+static void arcmsr_get_hbe_config(struct AdapterControlBlock *acb)
+{
+ char *acb_firm_model = acb->firm_model;
+ char *acb_firm_version = acb->firm_version;
+ char *acb_device_map = acb->device_map;
+ size_t iop_firm_model = offsetof(struct HBE_MessageUnit,msgcode_rwbuffer[ARCMSR_FW_MODEL_OFFSET]); /*firm_model,15,60-67*/
+ size_t iop_firm_version = offsetof(struct HBE_MessageUnit,msgcode_rwbuffer[ARCMSR_FW_VERS_OFFSET]); /*firm_version,17,68-83*/
+ size_t iop_device_map = offsetof(struct HBE_MessageUnit,msgcode_rwbuffer[ARCMSR_FW_DEVMAP_OFFSET]);
+ int i;
+
+ CHIP_REG_WRITE32(HBE_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_GET_CONFIG);
+ acb->out_doorbell ^= ARCMSR_HBEMU_DRV2IOP_MESSAGE_CMD_DONE;
+ CHIP_REG_WRITE32(HBE_MessageUnit, 0, iobound_doorbell, acb->out_doorbell);
+ if(!arcmsr_hbe_wait_msgint_ready(acb)) {
+ printf("arcmsr%d: wait 'get adapter firmware miscellaneous data' timeout \n", acb->pci_unit);
+ }
+
+ i = 0;
+ while(i < 8) {
+ *acb_firm_model = bus_space_read_1(acb->btag[0], acb->bhandle[0], iop_firm_model+i);
+ /* 8 bytes firm_model, 15, 60-67*/
+ acb_firm_model++;
+ i++;
+ }
+ i = 0;
+ while(i < 16) {
+ *acb_firm_version = bus_space_read_1(acb->btag[0], acb->bhandle[0], iop_firm_version+i);
+ /* 16 bytes firm_version, 17, 68-83*/
+ acb_firm_version++;
+ i++;
+ }
+ i = 0;
+ while(i < 16) {
+ *acb_device_map = bus_space_read_1(acb->btag[0], acb->bhandle[0], iop_device_map+i);
+ acb_device_map++;
+ i++;
+ }
+ printf("Areca RAID adapter%d: %s F/W version %s \n", acb->pci_unit, acb->firm_model, acb->firm_version);
+ acb->firm_request_len = CHIP_REG_READ32(HBE_MessageUnit, 0, msgcode_rwbuffer[1]); /*firm_request_len, 1, 04-07*/
+ acb->firm_numbers_queue = CHIP_REG_READ32(HBE_MessageUnit, 0, msgcode_rwbuffer[2]); /*firm_numbers_queue, 2, 08-11*/
+ acb->firm_sdram_size = CHIP_REG_READ32(HBE_MessageUnit, 0, msgcode_rwbuffer[3]); /*firm_sdram_size, 3, 12-15*/
+ acb->firm_ide_channels = CHIP_REG_READ32(HBE_MessageUnit, 0, msgcode_rwbuffer[4]); /*firm_ide_channels, 4, 16-19*/
+ acb->firm_cfg_version = CHIP_REG_READ32(HBE_MessageUnit, 0, msgcode_rwbuffer[ARCMSR_FW_CFGVER_OFFSET]); /*firm_cfg_version, 25, */
+ if(acb->firm_numbers_queue > ARCMSR_MAX_OUTSTANDING_CMD)
+ acb->maxOutstanding = ARCMSR_MAX_OUTSTANDING_CMD - 1;
+ else
+ acb->maxOutstanding = acb->firm_numbers_queue - 1;
+}
+/*
+**********************************************************************
+**********************************************************************
+*/
static void arcmsr_get_firmware_spec(struct AdapterControlBlock *acb)
{
switch (acb->adapter_type) {
@@ -3633,6 +4024,10 @@
arcmsr_get_hbd_config(acb);
}
break;
+ case ACB_ADAPTER_TYPE_E: {
+ arcmsr_get_hbe_config(acb);
+ }
+ break;
}
}
/*
@@ -3642,7 +4037,7 @@
static void arcmsr_wait_firmware_ready( struct AdapterControlBlock *acb)
{
int timeout=0;
-
+
switch (acb->adapter_type) {
case ACB_ADAPTER_TYPE_A: {
while ((CHIP_REG_READ32(HBA_MessageUnit, 0, outbound_msgaddr1) & ARCMSR_OUTBOUND_MESG1_FIRMWARE_OK) == 0)
@@ -3657,7 +4052,8 @@
}
break;
case ACB_ADAPTER_TYPE_B: {
- while ((CHIP_REG_READ32(HBB_DOORBELL, 0, iop2drv_doorbell) & ARCMSR_MESSAGE_FIRMWARE_OK) == 0)
+ struct HBB_MessageUnit *phbbmu = (struct HBB_MessageUnit *)acb->pmu;
+ while ((READ_CHIP_REG32(0, phbbmu->iop2drv_doorbell) & ARCMSR_MESSAGE_FIRMWARE_OK) == 0)
{
if (timeout++ > 2000) /* (2000*15)/1000 = 30 sec */
{
@@ -3666,7 +4062,7 @@
}
UDELAY(15000); /* wait 15 milli-seconds */
}
- CHIP_REG_WRITE32(HBB_DOORBELL, 0, drv2iop_doorbell, ARCMSR_DRV2IOP_END_OF_INTERRUPT);
+ WRITE_CHIP_REG32(0, phbbmu->drv2iop_doorbell, ARCMSR_DRV2IOP_END_OF_INTERRUPT);
}
break;
case ACB_ADAPTER_TYPE_C: {
@@ -3693,6 +4089,18 @@
}
}
break;
+ case ACB_ADAPTER_TYPE_E: {
+ while ((CHIP_REG_READ32(HBE_MessageUnit, 0, outbound_msgaddr1) & ARCMSR_HBEMU_MESSAGE_FIRMWARE_OK) == 0)
+ {
+ if (timeout++ > 4000) /* (4000*15)/1000 = 60 sec */
+ {
+ printf( "arcmsr%d:timed out waiting for firmware ready\n", acb->pci_unit);
+ return;
+ }
+ UDELAY(15000); /* wait 15 milli-seconds */
+ }
+ }
+ break;
}
}
/*
@@ -3709,12 +4117,12 @@
outbound_doorbell = CHIP_REG_READ32(HBA_MessageUnit, 0, outbound_doorbell);
CHIP_REG_WRITE32(HBA_MessageUnit, 0, outbound_doorbell, outbound_doorbell); /*clear doorbell interrupt */
CHIP_REG_WRITE32(HBA_MessageUnit, 0, inbound_doorbell, ARCMSR_INBOUND_DRIVER_DATA_READ_OK);
-
}
break;
case ACB_ADAPTER_TYPE_B: {
- CHIP_REG_WRITE32(HBB_DOORBELL, 0, iop2drv_doorbell, ARCMSR_MESSAGE_INT_CLEAR_PATTERN);/*clear interrupt and message state*/
- CHIP_REG_WRITE32(HBB_DOORBELL, 0, drv2iop_doorbell, ARCMSR_DRV2IOP_DATA_READ_OK);
+ struct HBB_MessageUnit *phbbmu = (struct HBB_MessageUnit *)acb->pmu;
+ WRITE_CHIP_REG32(0, phbbmu->iop2drv_doorbell, ARCMSR_DOORBELL_INT_CLEAR_PATTERN);/*clear interrupt and message state*/
+ WRITE_CHIP_REG32(0, phbbmu->drv2iop_doorbell, ARCMSR_DRV2IOP_DATA_READ_OK);
/* let IOP know data has been read */
}
break;
@@ -3732,9 +4140,16 @@
outbound_doorbell = CHIP_REG_READ32(HBD_MessageUnit, 0, outbound_doorbell);
CHIP_REG_WRITE32(HBD_MessageUnit, 0, outbound_doorbell, outbound_doorbell); /*clear doorbell interrupt */
CHIP_REG_WRITE32(HBD_MessageUnit, 0, inbound_doorbell, ARCMSR_HBDMU_DRV2IOP_DATA_OUT_READ);
-
}
break;
+ case ACB_ADAPTER_TYPE_E: {
+ /* empty doorbell Qbuffer if door bell ringed */
+ acb->in_doorbell = CHIP_REG_READ32(HBE_MessageUnit, 0, iobound_doorbell);
+ CHIP_REG_WRITE32(HBE_MessageUnit, 0, host_int_status, 0); /*clear doorbell interrupt */
+ acb->out_doorbell ^= ARCMSR_HBEMU_DRV2IOP_DATA_READ_OK;
+ CHIP_REG_WRITE32(HBE_MessageUnit, 0, iobound_doorbell, acb->out_doorbell);
+ }
+ break;
}
}
/*
@@ -3746,7 +4161,7 @@
unsigned long srb_phyaddr;
u_int32_t srb_phyaddr_hi32;
u_int32_t srb_phyaddr_lo32;
-
+
/*
********************************************************************
** here we need to tell iop 331 our freesrb.HighPart
@@ -3777,11 +4192,11 @@
case ACB_ADAPTER_TYPE_B: {
u_int32_t post_queue_phyaddr;
struct HBB_MessageUnit *phbbmu;
-
+
phbbmu = (struct HBB_MessageUnit *)acb->pmu;
phbbmu->postq_index = 0;
phbbmu->doneq_index = 0;
- CHIP_REG_WRITE32(HBB_DOORBELL, 0, drv2iop_doorbell, ARCMSR_MESSAGE_SET_POST_WINDOW);
+ WRITE_CHIP_REG32(0, phbbmu->drv2iop_doorbell, ARCMSR_MESSAGE_SET_POST_WINDOW);
if(!arcmsr_hbb_wait_msgint_ready(acb)) {
printf( "arcmsr%d: 'set window of post command Q' timeout\n", acb->pci_unit);
return FALSE;
@@ -3793,12 +4208,12 @@
CHIP_REG_WRITE32(HBB_RWBUFFER, 1, msgcode_rwbuffer[2], post_queue_phyaddr); /* postQ size (256+8)*4 */
CHIP_REG_WRITE32(HBB_RWBUFFER, 1, msgcode_rwbuffer[3], post_queue_phyaddr+1056); /* doneQ size (256+8)*4 */
CHIP_REG_WRITE32(HBB_RWBUFFER, 1, msgcode_rwbuffer[4], 1056); /* srb maxQ size must be --> [(256+8)*4] */
- CHIP_REG_WRITE32(HBB_DOORBELL, 0, drv2iop_doorbell, ARCMSR_MESSAGE_SET_CONFIG);
+ WRITE_CHIP_REG32(0, phbbmu->drv2iop_doorbell, ARCMSR_MESSAGE_SET_CONFIG);
if(!arcmsr_hbb_wait_msgint_ready(acb)) {
printf( "arcmsr%d: 'set command Q window' timeout \n", acb->pci_unit);
return FALSE;
}
- CHIP_REG_WRITE32(HBB_DOORBELL, 0, drv2iop_doorbell, ARCMSR_MESSAGE_START_DRIVER_MODE);
+ WRITE_CHIP_REG32(0, phbbmu->drv2iop_doorbell, ARCMSR_MESSAGE_START_DRIVER_MODE);
if(!arcmsr_hbb_wait_msgint_ready(acb)) {
printf( "arcmsr%d: 'start diver mode' timeout \n", acb->pci_unit);
return FALSE;
@@ -3821,7 +4236,7 @@
case ACB_ADAPTER_TYPE_D: {
u_int32_t post_queue_phyaddr, done_queue_phyaddr;
struct HBD_MessageUnit0 *phbdmu;
-
+
phbdmu = (struct HBD_MessageUnit0 *)acb->pmu;
phbdmu->postq_index = 0;
phbdmu->doneq_index = 0x40FF;
@@ -3841,6 +4256,27 @@
}
}
break;
+ case ACB_ADAPTER_TYPE_E: {
+ u_int32_t cdb_phyaddr_lo32;
+ cdb_phyaddr_lo32 = srb_phyaddr_lo32 + offsetof(struct CommandControlBlock, arcmsr_cdb);
+ CHIP_REG_WRITE32(HBE_MessageUnit, 0, msgcode_rwbuffer[0], ARCMSR_SIGNATURE_SET_CONFIG);
+ CHIP_REG_WRITE32(HBE_MessageUnit, 0, msgcode_rwbuffer[1], ARCMSR_SIGNATURE_1884);
+ CHIP_REG_WRITE32(HBE_MessageUnit, 0, msgcode_rwbuffer[2], cdb_phyaddr_lo32);
+ CHIP_REG_WRITE32(HBE_MessageUnit, 0, msgcode_rwbuffer[3], srb_phyaddr_hi32);
+ CHIP_REG_WRITE32(HBE_MessageUnit, 0, msgcode_rwbuffer[4], SRB_SIZE);
+ cdb_phyaddr_lo32 = srb_phyaddr_lo32 + ARCMSR_SRBS_POOL_SIZE;
+ CHIP_REG_WRITE32(HBE_MessageUnit, 0, msgcode_rwbuffer[5], cdb_phyaddr_lo32);
+ CHIP_REG_WRITE32(HBE_MessageUnit, 0, msgcode_rwbuffer[6], srb_phyaddr_hi32);
+ CHIP_REG_WRITE32(HBE_MessageUnit, 0, msgcode_rwbuffer[7], COMPLETION_Q_POOL_SIZE);
+ CHIP_REG_WRITE32(HBE_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_SET_CONFIG);
+ acb->out_doorbell ^= ARCMSR_HBEMU_DRV2IOP_MESSAGE_CMD_DONE;
+ CHIP_REG_WRITE32(HBE_MessageUnit, 0, iobound_doorbell, acb->out_doorbell);
+ if(!arcmsr_hbe_wait_msgint_ready(acb)) {
+ printf( "arcmsr%d: 'set srb high part physical address' timeout \n", acb->pci_unit);
+ return FALSE;
+ }
+ }
+ break;
}
return (TRUE);
}
@@ -3850,20 +4286,14 @@
*/
static void arcmsr_enable_eoi_mode(struct AdapterControlBlock *acb)
{
- switch (acb->adapter_type)
+ if (acb->adapter_type == ACB_ADAPTER_TYPE_B)
{
- case ACB_ADAPTER_TYPE_A:
- case ACB_ADAPTER_TYPE_C:
- case ACB_ADAPTER_TYPE_D:
- break;
- case ACB_ADAPTER_TYPE_B: {
- CHIP_REG_WRITE32(HBB_DOORBELL, 0, drv2iop_doorbell,ARCMSR_MESSAGE_ACTIVE_EOI_MODE);
- if(!arcmsr_hbb_wait_msgint_ready(acb)) {
- printf( "arcmsr%d: 'iop enable eoi mode' timeout \n", acb->pci_unit);
- return;
- }
+ struct HBB_MessageUnit *phbbmu = (struct HBB_MessageUnit *)acb->pmu;
+ WRITE_CHIP_REG32(0, phbbmu->drv2iop_doorbell, ARCMSR_MESSAGE_ACTIVE_EOI_MODE);
+ if(!arcmsr_hbb_wait_msgint_ready(acb)) {
+ printf( "arcmsr%d: 'iop enable eoi mode' timeout \n", acb->pci_unit);
+ return;
}
- break;
}
}
/*
@@ -3873,7 +4303,7 @@
static void arcmsr_iop_init(struct AdapterControlBlock *acb)
{
u_int32_t intmask_org;
-
+
/* disable all outbound interrupt */
intmask_org = arcmsr_disable_allintr(acb);
arcmsr_wait_firmware_ready(acb);
@@ -3898,7 +4328,7 @@
struct CommandControlBlock *srb_tmp;
u_int32_t i;
unsigned long srb_phyaddr = (unsigned long)segs->ds_addr;
-
+
acb->srb_phyaddr.phyaddr = srb_phyaddr;
srb_tmp = (struct CommandControlBlock *)acb->uncacheptr;
for(i=0; i < ARCMSR_MAX_FREESRB_NUM; i++) {
@@ -3909,7 +4339,8 @@
" srb dmamap bus_dmamap_create error\n", acb->pci_unit);
return;
}
- if((acb->adapter_type == ACB_ADAPTER_TYPE_C) || (acb->adapter_type == ACB_ADAPTER_TYPE_D))
+ if((acb->adapter_type == ACB_ADAPTER_TYPE_C) || (acb->adapter_type == ACB_ADAPTER_TYPE_D)
+ || (acb->adapter_type == ACB_ADAPTER_TYPE_E))
{
srb_tmp->cdb_phyaddr_low = srb_phyaddr;
srb_tmp->cdb_phyaddr_high = (u_int32_t)((srb_phyaddr >> 16) >> 16);
@@ -3917,10 +4348,13 @@
else
srb_tmp->cdb_phyaddr_low = srb_phyaddr >> 5;
srb_tmp->acb = acb;
+ srb_tmp->smid = i << 16;
acb->srbworkingQ[i] = acb->psrb_pool[i] = srb_tmp;
srb_phyaddr = srb_phyaddr + SRB_SIZE;
srb_tmp = (struct CommandControlBlock *)((unsigned long)srb_tmp + SRB_SIZE);
}
+ if (acb->adapter_type == ACB_ADAPTER_TYPE_E)
+ acb->pCompletionQ = (pCompletion_Q)srb_tmp;
acb->vir2phy_offset = (unsigned long)srb_tmp - (unsigned long)srb_phyaddr;
}
/*
@@ -3974,6 +4408,7 @@
vendor_dev_id = pci_get_devid(dev);
acb->vendor_device_id = vendor_dev_id;
+ acb->sub_device_id = pci_read_config(dev, PCIR_SUBDEV_0, 2);
switch (vendor_dev_id) {
case PCIDevVenIDARC1880:
case PCIDevVenIDARC1882:
@@ -3980,10 +4415,21 @@
case PCIDevVenIDARC1213:
case PCIDevVenIDARC1223: {
acb->adapter_type = ACB_ADAPTER_TYPE_C;
- acb->adapter_bus_speed = ACB_BUS_SPEED_6G;
+ if ((acb->sub_device_id == ARECA_SUB_DEV_ID_1883) ||
+ (acb->sub_device_id == ARECA_SUB_DEV_ID_1216) ||
+ (acb->sub_device_id == ARECA_SUB_DEV_ID_1226))
+ acb->adapter_bus_speed = ACB_BUS_SPEED_12G;
+ else
+ acb->adapter_bus_speed = ACB_BUS_SPEED_6G;
max_coherent_size = ARCMSR_SRBS_POOL_SIZE;
}
break;
+ case PCIDevVenIDARC1884:
+ acb->adapter_type = ACB_ADAPTER_TYPE_E;
+ acb->adapter_bus_speed = ACB_BUS_SPEED_12G;
+ max_coherent_size = ARCMSR_SRBS_POOL_SIZE + COMPLETION_Q_POOL_SIZE;
+ acb->completionQ_entry = COMPLETION_Q_POOL_SIZE / sizeof(struct deliver_completeQ);
+ break;
case PCIDevVenIDARC1214: {
acb->adapter_type = ACB_ADAPTER_TYPE_D;
acb->adapter_bus_speed = ACB_BUS_SPEED_6G;
@@ -3997,6 +4443,12 @@
max_coherent_size = ARCMSR_SRBS_POOL_SIZE + (sizeof(struct HBB_MessageUnit));
}
break;
+ case PCIDevVenIDARC1203: {
+ acb->adapter_type = ACB_ADAPTER_TYPE_B;
+ acb->adapter_bus_speed = ACB_BUS_SPEED_6G;
+ max_coherent_size = ARCMSR_SRBS_POOL_SIZE + (sizeof(struct HBB_MessageUnit));
+ }
+ break;
case PCIDevVenIDARC1110:
case PCIDevVenIDARC1120:
case PCIDevVenIDARC1130:
@@ -4032,21 +4484,21 @@
#else
if(bus_dma_tag_create( /*PCI parent*/ NULL,
#endif
- /*alignemnt*/ 1,
- /*boundary*/ 0,
- /*lowaddr*/ BUS_SPACE_MAXADDR,
- /*highaddr*/ BUS_SPACE_MAXADDR,
- /*filter*/ NULL,
- /*filterarg*/ NULL,
- /*maxsize*/ BUS_SPACE_MAXSIZE_32BIT,
- /*nsegments*/ BUS_SPACE_UNRESTRICTED,
- /*maxsegsz*/ BUS_SPACE_MAXSIZE_32BIT,
- /*flags*/ 0,
+ /*alignemnt*/ 1,
+ /*boundary*/ 0,
+ /*lowaddr*/ BUS_SPACE_MAXADDR,
+ /*highaddr*/ BUS_SPACE_MAXADDR,
+ /*filter*/ NULL,
+ /*filterarg*/ NULL,
+ /*maxsize*/ BUS_SPACE_MAXSIZE_32BIT,
+ /*nsegments*/ BUS_SPACE_UNRESTRICTED,
+ /*maxsegsz*/ BUS_SPACE_MAXSIZE_32BIT,
+ /*flags*/ 0,
#if __FreeBSD_version >= 501102
- /*lockfunc*/ NULL,
- /*lockarg*/ NULL,
+ /*lockfunc*/ NULL,
+ /*lockarg*/ NULL,
#endif
- &acb->parent_dmat) != 0)
+ &acb->parent_dmat) != 0)
{
printf("arcmsr%d: parent_dmat bus_dma_tag_create failure!\n", device_get_unit(dev));
return ENOMEM;
@@ -4053,26 +4505,26 @@
}
/* Create a single tag describing a region large enough to hold all of the s/g lists we will need. */
- if(bus_dma_tag_create( /*parent_dmat*/ acb->parent_dmat,
- /*alignment*/ 1,
- /*boundary*/ 0,
+ if(bus_dma_tag_create( /*parent_dmat*/ acb->parent_dmat,
+ /*alignment*/ 1,
+ /*boundary*/ 0,
#ifdef PAE
- /*lowaddr*/ BUS_SPACE_MAXADDR_32BIT,
+ /*lowaddr*/ BUS_SPACE_MAXADDR_32BIT,
#else
- /*lowaddr*/ BUS_SPACE_MAXADDR,
+ /*lowaddr*/ BUS_SPACE_MAXADDR,
#endif
- /*highaddr*/ BUS_SPACE_MAXADDR,
- /*filter*/ NULL,
- /*filterarg*/ NULL,
- /*maxsize*/ ARCMSR_MAX_SG_ENTRIES * PAGE_SIZE * ARCMSR_MAX_FREESRB_NUM,
- /*nsegments*/ ARCMSR_MAX_SG_ENTRIES,
- /*maxsegsz*/ BUS_SPACE_MAXSIZE_32BIT,
- /*flags*/ 0,
+ /*highaddr*/ BUS_SPACE_MAXADDR,
+ /*filter*/ NULL,
+ /*filterarg*/ NULL,
+ /*maxsize*/ ARCMSR_MAX_SG_ENTRIES * PAGE_SIZE * ARCMSR_MAX_FREESRB_NUM,
+ /*nsegments*/ ARCMSR_MAX_SG_ENTRIES,
+ /*maxsegsz*/ BUS_SPACE_MAXSIZE_32BIT,
+ /*flags*/ 0,
#if __FreeBSD_version >= 501102
- /*lockfunc*/ busdma_lock_mutex,
- /*lockarg*/ &acb->isr_lock,
+ /*lockfunc*/ busdma_lock_mutex,
+ /*lockarg*/ &acb->isr_lock,
#endif
- &acb->dm_segs_dmat) != 0)
+ &acb->dm_segs_dmat) != 0)
{
bus_dma_tag_destroy(acb->parent_dmat);
printf("arcmsr%d: dm_segs_dmat bus_dma_tag_create failure!\n", device_get_unit(dev));
@@ -4080,22 +4532,22 @@
}
/* DMA tag for our srb structures.... Allocate the freesrb memory */
- if(bus_dma_tag_create( /*parent_dmat*/ acb->parent_dmat,
- /*alignment*/ 0x20,
- /*boundary*/ 0,
- /*lowaddr*/ BUS_SPACE_MAXADDR_32BIT,
- /*highaddr*/ BUS_SPACE_MAXADDR,
- /*filter*/ NULL,
- /*filterarg*/ NULL,
- /*maxsize*/ max_coherent_size,
- /*nsegments*/ 1,
- /*maxsegsz*/ BUS_SPACE_MAXSIZE_32BIT,
- /*flags*/ 0,
+ if(bus_dma_tag_create( /*parent_dmat*/ acb->parent_dmat,
+ /*alignment*/ 0x20,
+ /*boundary*/ 0,
+ /*lowaddr*/ BUS_SPACE_MAXADDR_32BIT,
+ /*highaddr*/ BUS_SPACE_MAXADDR,
+ /*filter*/ NULL,
+ /*filterarg*/ NULL,
+ /*maxsize*/ max_coherent_size,
+ /*nsegments*/ 1,
+ /*maxsegsz*/ BUS_SPACE_MAXSIZE_32BIT,
+ /*flags*/ 0,
#if __FreeBSD_version >= 501102
- /*lockfunc*/ NULL,
- /*lockarg*/ NULL,
+ /*lockfunc*/ NULL,
+ /*lockarg*/ NULL,
#endif
- &acb->srb_dmat) != 0)
+ &acb->srb_dmat) != 0)
{
bus_dma_tag_destroy(acb->dm_segs_dmat);
bus_dma_tag_destroy(acb->parent_dmat);
@@ -4122,130 +4574,171 @@
pci_command |= PCIM_CMD_BUSMASTEREN;
pci_command |= PCIM_CMD_PERRESPEN;
pci_command |= PCIM_CMD_MWRICEN;
- /* Enable Busmaster/Mem */
- pci_command |= PCIM_CMD_MEMEN;
+ /* Enable Busmaster */
pci_write_config(dev, PCIR_COMMAND, pci_command, 2);
switch(acb->adapter_type) {
case ACB_ADAPTER_TYPE_A: {
- u_int32_t rid0 = PCIR_BAR(0);
- vm_offset_t mem_base0;
+ u_int32_t rid0 = PCIR_BAR(0);
+ vm_offset_t mem_base0;
- acb->sys_res_arcmsr[0] = bus_alloc_resource(dev,SYS_RES_MEMORY, &rid0, 0ul, ~0ul, 0x1000, RF_ACTIVE);
- if(acb->sys_res_arcmsr[0] == NULL) {
+ acb->sys_res_arcmsr[0] = bus_alloc_resource_any(dev,SYS_RES_MEMORY, &rid0, RF_ACTIVE);
+ if(acb->sys_res_arcmsr[0] == NULL) {
+ arcmsr_free_resource(acb);
+ printf("arcmsr%d: bus_alloc_resource failure!\n", device_get_unit(dev));
+ return ENOMEM;
+ }
+ if(rman_get_start(acb->sys_res_arcmsr[0]) <= 0) {
+ arcmsr_free_resource(acb);
+ printf("arcmsr%d: rman_get_start failure!\n", device_get_unit(dev));
+ return ENXIO;
+ }
+ mem_base0 = (vm_offset_t) rman_get_virtual(acb->sys_res_arcmsr[0]);
+ if(mem_base0 == 0) {
+ arcmsr_free_resource(acb);
+ printf("arcmsr%d: rman_get_virtual failure!\n", device_get_unit(dev));
+ return ENXIO;
+ }
+ acb->btag[0] = rman_get_bustag(acb->sys_res_arcmsr[0]);
+ acb->bhandle[0] = rman_get_bushandle(acb->sys_res_arcmsr[0]);
+ acb->pmu = (struct MessageUnit_UNION *)mem_base0;
+ acb->rid[0] = rid0;
+ }
+ break;
+ case ACB_ADAPTER_TYPE_B: {
+ struct HBB_MessageUnit *phbbmu;
+ struct CommandControlBlock *freesrb;
+ u_int32_t rid[]={ PCIR_BAR(0), PCIR_BAR(2) };
+ vm_offset_t mem_base[]={0,0};
+ for(i=0; i < 2; i++) {
+ acb->sys_res_arcmsr[i] = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid[i], RF_ACTIVE);
+ if(acb->sys_res_arcmsr[i] == NULL) {
arcmsr_free_resource(acb);
- printf("arcmsr%d: bus_alloc_resource failure!\n", device_get_unit(dev));
+ printf("arcmsr%d: bus_alloc_resource %d failure!\n", device_get_unit(dev), i);
return ENOMEM;
}
- if(rman_get_start(acb->sys_res_arcmsr[0]) <= 0) {
+ if(rman_get_start(acb->sys_res_arcmsr[i]) <= 0) {
arcmsr_free_resource(acb);
- printf("arcmsr%d: rman_get_start failure!\n", device_get_unit(dev));
+ printf("arcmsr%d: rman_get_start %d failure!\n", device_get_unit(dev), i);
return ENXIO;
}
- mem_base0 = (vm_offset_t) rman_get_virtual(acb->sys_res_arcmsr[0]);
- if(mem_base0 == 0) {
+ mem_base[i] = (vm_offset_t) rman_get_virtual(acb->sys_res_arcmsr[i]);
+ if(mem_base[i] == 0) {
arcmsr_free_resource(acb);
- printf("arcmsr%d: rman_get_virtual failure!\n", device_get_unit(dev));
+ printf("arcmsr%d: rman_get_virtual %d failure!\n", device_get_unit(dev), i);
return ENXIO;
}
- acb->btag[0] = rman_get_bustag(acb->sys_res_arcmsr[0]);
- acb->bhandle[0] = rman_get_bushandle(acb->sys_res_arcmsr[0]);
- acb->pmu = (struct MessageUnit_UNION *)mem_base0;
+ acb->btag[i] = rman_get_bustag(acb->sys_res_arcmsr[i]);
+ acb->bhandle[i] = rman_get_bushandle(acb->sys_res_arcmsr[i]);
}
- break;
- case ACB_ADAPTER_TYPE_B: {
- struct HBB_MessageUnit *phbbmu;
- struct CommandControlBlock *freesrb;
- u_int32_t rid[]={ PCIR_BAR(0), PCIR_BAR(2) };
- vm_offset_t mem_base[]={0,0};
- for(i=0; i < 2; i++) {
- if(i == 0) {
- acb->sys_res_arcmsr[i] = bus_alloc_resource(dev,SYS_RES_MEMORY, &rid[i],
- 0ul, ~0ul, sizeof(struct HBB_DOORBELL), RF_ACTIVE);
- } else {
- acb->sys_res_arcmsr[i] = bus_alloc_resource(dev, SYS_RES_MEMORY, &rid[i],
- 0ul, ~0ul, sizeof(struct HBB_RWBUFFER), RF_ACTIVE);
- }
- if(acb->sys_res_arcmsr[i] == NULL) {
- arcmsr_free_resource(acb);
- printf("arcmsr%d: bus_alloc_resource %d failure!\n", device_get_unit(dev), i);
- return ENOMEM;
- }
- if(rman_get_start(acb->sys_res_arcmsr[i]) <= 0) {
- arcmsr_free_resource(acb);
- printf("arcmsr%d: rman_get_start %d failure!\n", device_get_unit(dev), i);
- return ENXIO;
- }
- mem_base[i] = (vm_offset_t) rman_get_virtual(acb->sys_res_arcmsr[i]);
- if(mem_base[i] == 0) {
- arcmsr_free_resource(acb);
- printf("arcmsr%d: rman_get_virtual %d failure!\n", device_get_unit(dev), i);
- return ENXIO;
- }
- acb->btag[i] = rman_get_bustag(acb->sys_res_arcmsr[i]);
- acb->bhandle[i] = rman_get_bushandle(acb->sys_res_arcmsr[i]);
- }
- freesrb = (struct CommandControlBlock *)acb->uncacheptr;
- acb->pmu = (struct MessageUnit_UNION *)((unsigned long)freesrb+ARCMSR_SRBS_POOL_SIZE);
- phbbmu = (struct HBB_MessageUnit *)acb->pmu;
- phbbmu->hbb_doorbell = (struct HBB_DOORBELL *)mem_base[0];
- phbbmu->hbb_rwbuffer = (struct HBB_RWBUFFER *)mem_base[1];
+ freesrb = (struct CommandControlBlock *)acb->uncacheptr;
+ acb->pmu = (struct MessageUnit_UNION *)((unsigned long)freesrb+ARCMSR_SRBS_POOL_SIZE);
+ phbbmu = (struct HBB_MessageUnit *)acb->pmu;
+ phbbmu->hbb_doorbell = (struct HBB_DOORBELL *)mem_base[0];
+ phbbmu->hbb_rwbuffer = (struct HBB_RWBUFFER *)mem_base[1];
+ if (vendor_dev_id == PCIDevVenIDARC1203) {
+ phbbmu->drv2iop_doorbell = offsetof(struct HBB_DOORBELL_1203, drv2iop_doorbell);
+ phbbmu->drv2iop_doorbell_mask = offsetof(struct HBB_DOORBELL_1203, drv2iop_doorbell_mask);
+ phbbmu->iop2drv_doorbell = offsetof(struct HBB_DOORBELL_1203, iop2drv_doorbell);
+ phbbmu->iop2drv_doorbell_mask = offsetof(struct HBB_DOORBELL_1203, iop2drv_doorbell_mask);
+ } else {
+ phbbmu->drv2iop_doorbell = offsetof(struct HBB_DOORBELL, drv2iop_doorbell);
+ phbbmu->drv2iop_doorbell_mask = offsetof(struct HBB_DOORBELL, drv2iop_doorbell_mask);
+ phbbmu->iop2drv_doorbell = offsetof(struct HBB_DOORBELL, iop2drv_doorbell);
+ phbbmu->iop2drv_doorbell_mask = offsetof(struct HBB_DOORBELL, iop2drv_doorbell_mask);
}
+ acb->rid[0] = rid[0];
+ acb->rid[1] = rid[1];
+ }
break;
case ACB_ADAPTER_TYPE_C: {
- u_int32_t rid0 = PCIR_BAR(1);
- vm_offset_t mem_base0;
+ u_int32_t rid0 = PCIR_BAR(1);
+ vm_offset_t mem_base0;
- acb->sys_res_arcmsr[0] = bus_alloc_resource(dev,SYS_RES_MEMORY, &rid0, 0ul, ~0ul, sizeof(struct HBC_MessageUnit), RF_ACTIVE);
- if(acb->sys_res_arcmsr[0] == NULL) {
- arcmsr_free_resource(acb);
- printf("arcmsr%d: bus_alloc_resource failure!\n", device_get_unit(dev));
- return ENOMEM;
- }
- if(rman_get_start(acb->sys_res_arcmsr[0]) <= 0) {
- arcmsr_free_resource(acb);
- printf("arcmsr%d: rman_get_start failure!\n", device_get_unit(dev));
- return ENXIO;
- }
- mem_base0 = (vm_offset_t) rman_get_virtual(acb->sys_res_arcmsr[0]);
- if(mem_base0 == 0) {
- arcmsr_free_resource(acb);
- printf("arcmsr%d: rman_get_virtual failure!\n", device_get_unit(dev));
- return ENXIO;
- }
- acb->btag[0] = rman_get_bustag(acb->sys_res_arcmsr[0]);
- acb->bhandle[0] = rman_get_bushandle(acb->sys_res_arcmsr[0]);
- acb->pmu = (struct MessageUnit_UNION *)mem_base0;
+ acb->sys_res_arcmsr[0] = bus_alloc_resource_any(dev,SYS_RES_MEMORY, &rid0, RF_ACTIVE);
+ if(acb->sys_res_arcmsr[0] == NULL) {
+ arcmsr_free_resource(acb);
+ printf("arcmsr%d: bus_alloc_resource failure!\n", device_get_unit(dev));
+ return ENOMEM;
}
+ if(rman_get_start(acb->sys_res_arcmsr[0]) <= 0) {
+ arcmsr_free_resource(acb);
+ printf("arcmsr%d: rman_get_start failure!\n", device_get_unit(dev));
+ return ENXIO;
+ }
+ mem_base0 = (vm_offset_t) rman_get_virtual(acb->sys_res_arcmsr[0]);
+ if(mem_base0 == 0) {
+ arcmsr_free_resource(acb);
+ printf("arcmsr%d: rman_get_virtual failure!\n", device_get_unit(dev));
+ return ENXIO;
+ }
+ acb->btag[0] = rman_get_bustag(acb->sys_res_arcmsr[0]);
+ acb->bhandle[0] = rman_get_bushandle(acb->sys_res_arcmsr[0]);
+ acb->pmu = (struct MessageUnit_UNION *)mem_base0;
+ acb->rid[0] = rid0;
+ }
break;
case ACB_ADAPTER_TYPE_D: {
- struct HBD_MessageUnit0 *phbdmu;
- u_int32_t rid0 = PCIR_BAR(0);
- vm_offset_t mem_base0;
+ struct HBD_MessageUnit0 *phbdmu;
+ u_int32_t rid0 = PCIR_BAR(0);
+ vm_offset_t mem_base0;
- acb->sys_res_arcmsr[0] = bus_alloc_resource(dev,SYS_RES_MEMORY, &rid0, 0ul, ~0ul, sizeof(struct HBD_MessageUnit), RF_ACTIVE);
- if(acb->sys_res_arcmsr[0] == NULL) {
- arcmsr_free_resource(acb);
- printf("arcmsr%d: bus_alloc_resource failure!\n", device_get_unit(dev));
- return ENOMEM;
- }
- if(rman_get_start(acb->sys_res_arcmsr[0]) <= 0) {
- arcmsr_free_resource(acb);
- printf("arcmsr%d: rman_get_start failure!\n", device_get_unit(dev));
- return ENXIO;
- }
- mem_base0 = (vm_offset_t) rman_get_virtual(acb->sys_res_arcmsr[0]);
- if(mem_base0 == 0) {
- arcmsr_free_resource(acb);
- printf("arcmsr%d: rman_get_virtual failure!\n", device_get_unit(dev));
- return ENXIO;
- }
- acb->btag[0] = rman_get_bustag(acb->sys_res_arcmsr[0]);
- acb->bhandle[0] = rman_get_bushandle(acb->sys_res_arcmsr[0]);
- acb->pmu = (struct MessageUnit_UNION *)((unsigned long)acb->uncacheptr+ARCMSR_SRBS_POOL_SIZE);
- phbdmu = (struct HBD_MessageUnit0 *)acb->pmu;
- phbdmu->phbdmu = (struct HBD_MessageUnit *)mem_base0;
+ acb->sys_res_arcmsr[0] = bus_alloc_resource_any(dev,SYS_RES_MEMORY, &rid0, RF_ACTIVE);
+ if(acb->sys_res_arcmsr[0] == NULL) {
+ arcmsr_free_resource(acb);
+ printf("arcmsr%d: bus_alloc_resource failure!\n", device_get_unit(dev));
+ return ENOMEM;
}
+ if(rman_get_start(acb->sys_res_arcmsr[0]) <= 0) {
+ arcmsr_free_resource(acb);
+ printf("arcmsr%d: rman_get_start failure!\n", device_get_unit(dev));
+ return ENXIO;
+ }
+ mem_base0 = (vm_offset_t) rman_get_virtual(acb->sys_res_arcmsr[0]);
+ if(mem_base0 == 0) {
+ arcmsr_free_resource(acb);
+ printf("arcmsr%d: rman_get_virtual failure!\n", device_get_unit(dev));
+ return ENXIO;
+ }
+ acb->btag[0] = rman_get_bustag(acb->sys_res_arcmsr[0]);
+ acb->bhandle[0] = rman_get_bushandle(acb->sys_res_arcmsr[0]);
+ acb->pmu = (struct MessageUnit_UNION *)((unsigned long)acb->uncacheptr+ARCMSR_SRBS_POOL_SIZE);
+ phbdmu = (struct HBD_MessageUnit0 *)acb->pmu;
+ phbdmu->phbdmu = (struct HBD_MessageUnit *)mem_base0;
+ acb->rid[0] = rid0;
+ }
break;
+ case ACB_ADAPTER_TYPE_E: {
+ u_int32_t rid0 = PCIR_BAR(1);
+ vm_offset_t mem_base0;
+
+ acb->sys_res_arcmsr[0] = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid0, RF_ACTIVE);
+ if(acb->sys_res_arcmsr[0] == NULL) {
+ arcmsr_free_resource(acb);
+ printf("arcmsr%d: bus_alloc_resource failure!\n", device_get_unit(dev));
+ return ENOMEM;
+ }
+ if(rman_get_start(acb->sys_res_arcmsr[0]) <= 0) {
+ arcmsr_free_resource(acb);
+ printf("arcmsr%d: rman_get_start failure!\n", device_get_unit(dev));
+ return ENXIO;
+ }
+ mem_base0 = (vm_offset_t) rman_get_virtual(acb->sys_res_arcmsr[0]);
+ if(mem_base0 == 0) {
+ arcmsr_free_resource(acb);
+ printf("arcmsr%d: rman_get_virtual failure!\n", device_get_unit(dev));
+ return ENXIO;
+ }
+ acb->btag[0] = rman_get_bustag(acb->sys_res_arcmsr[0]);
+ acb->bhandle[0] = rman_get_bushandle(acb->sys_res_arcmsr[0]);
+ acb->pmu = (struct MessageUnit_UNION *)mem_base0;
+ acb->doneq_index = 0;
+ acb->in_doorbell = 0;
+ acb->out_doorbell = 0;
+ acb->rid[0] = rid0;
+ CHIP_REG_WRITE32(HBE_MessageUnit, 0, host_int_status, 0); /*clear interrupt*/
+ CHIP_REG_WRITE32(HBE_MessageUnit, 0, iobound_doorbell, ARCMSR_HBEMU_DOORBELL_SYNC); /* synchronize doorbell to 0 */
+ }
+ break;
}
if(acb->acb_flags & ACB_F_MAPFREESRB_FAILD) {
arcmsr_free_resource(acb);
@@ -4267,6 +4760,35 @@
arcmsr_iop_init(acb);
return(0);
}
+
+static int arcmsr_setup_msix(struct AdapterControlBlock *acb)
+{
+ int i;
+
+ for (i = 0; i < acb->msix_vectors; i++) {
+ acb->irq_id[i] = 1 + i;
+ acb->irqres[i] = bus_alloc_resource_any(acb->pci_dev,
+ SYS_RES_IRQ, &acb->irq_id[i], RF_ACTIVE);
+ if (acb->irqres[i] == NULL) {
+ printf("arcmsr: Can't allocate MSI-X resource\n");
+ goto irq_alloc_failed;
+ }
+ if (bus_setup_intr(acb->pci_dev, acb->irqres[i],
+ INTR_MPSAFE | INTR_TYPE_CAM, NULL, arcmsr_intr_handler,
+ acb, &acb->ih[i])) {
+ printf("arcmsr: Cannot set up MSI-X interrupt handler\n");
+ goto irq_alloc_failed;
+ }
+ }
+ printf("arcmsr: MSI-X INT enabled\n");
+ acb->acb_flags |= ACB_F_MSIX_ENABLED;
+ return TRUE;
+
+irq_alloc_failed:
+ arcmsr_teardown_intr(acb->pci_dev, acb);
+ return FALSE;
+}
+
/*
************************************************************************
************************************************************************
@@ -4278,35 +4800,37 @@
struct ccb_setasync csa;
struct cam_devq *devq; /* Device Queue to use for this SIM */
struct resource *irqres;
- int rid;
-
+
if(acb == NULL) {
printf("arcmsr%d: cannot allocate softc\n", unit);
return (ENOMEM);
}
arcmsr_mutex_init(acb);
+ acb->pci_dev = dev;
+ acb->pci_unit = unit;
if(arcmsr_initialize(dev)) {
printf("arcmsr%d: initialize failure!\n", unit);
- arcmsr_mutex_destroy(acb);
- return ENXIO;
+ goto initialize_failed;
}
/* After setting up the adapter, map our interrupt */
- rid = 0;
- irqres = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 0ul, ~0ul, 1, RF_SHAREABLE | RF_ACTIVE);
+ acb->msix_vectors = ARCMSR_NUM_MSIX_VECTORS;
+ if (pci_alloc_msix(dev, &acb->msix_vectors) == 0) {
+ if (arcmsr_setup_msix(acb) == TRUE)
+ goto irqx;
+ }
+ acb->irq_id[0] = 0;
+ irqres = bus_alloc_resource_any(dev, SYS_RES_IRQ, &acb->irq_id[0], RF_SHAREABLE | RF_ACTIVE);
if(irqres == NULL ||
#if __FreeBSD_version >= 700025
- bus_setup_intr(dev, irqres, INTR_TYPE_CAM|INTR_ENTROPY|INTR_MPSAFE, NULL, arcmsr_intr_handler, acb, &acb->ih)) {
+ bus_setup_intr(dev, irqres, INTR_TYPE_CAM|INTR_ENTROPY|INTR_MPSAFE, NULL, arcmsr_intr_handler, acb, &acb->ih[0])) {
#else
- bus_setup_intr(dev, irqres, INTR_TYPE_CAM|INTR_ENTROPY|INTR_MPSAFE, arcmsr_intr_handler, acb, &acb->ih)) {
+ bus_setup_intr(dev, irqres, INTR_TYPE_CAM|INTR_ENTROPY|INTR_MPSAFE, arcmsr_intr_handler, acb, &acb->ih[0])) {
#endif
- arcmsr_free_resource(acb);
- arcmsr_mutex_destroy(acb);
printf("arcmsr%d: unable to register interrupt handler!\n", unit);
- return ENXIO;
+ goto setup_intr_failed;
}
- acb->irqres = irqres;
- acb->pci_dev = dev;
- acb->pci_unit = unit;
+ acb->irqres[0] = irqres;
+irqx:
/*
* Now let the CAM generic SCSI layer find the SCSI devices on
* the bus * start queue to reset to the idle loop. *
@@ -4313,13 +4837,10 @@
* Create device queue of SIM(s) * (MAX_START_JOB - 1) :
* max_sim_transactions
*/
- devq = cam_simq_alloc(ARCMSR_MAX_START_JOB);
+ devq = cam_simq_alloc(acb->maxOutstanding);
if(devq == NULL) {
- arcmsr_free_resource(acb);
- bus_release_resource(dev, SYS_RES_IRQ, 0, acb->irqres);
- arcmsr_mutex_destroy(acb);
printf("arcmsr%d: cam_simq_alloc failure!\n", unit);
- return ENXIO;
+ goto simq_alloc_failed;
}
#if __FreeBSD_version >= 700025
acb->psim = cam_sim_alloc(arcmsr_action, arcmsr_poll, "arcmsr", acb, unit, &acb->isr_lock, 1, ARCMSR_MAX_OUTSTANDING_CMD, devq);
@@ -4327,12 +4848,8 @@
acb->psim = cam_sim_alloc(arcmsr_action, arcmsr_poll, "arcmsr", acb, unit, 1, ARCMSR_MAX_OUTSTANDING_CMD, devq);
#endif
if(acb->psim == NULL) {
- arcmsr_free_resource(acb);
- bus_release_resource(dev, SYS_RES_IRQ, 0, acb->irqres);
- cam_simq_free(devq);
- arcmsr_mutex_destroy(acb);
printf("arcmsr%d: cam_sim_alloc failure!\n", unit);
- return ENXIO;
+ goto sim_alloc_failed;
}
ARCMSR_LOCK_ACQUIRE(&acb->isr_lock);
#if __FreeBSD_version >= 700044
@@ -4340,21 +4857,12 @@
#else
if(xpt_bus_register(acb->psim, 0) != CAM_SUCCESS) {
#endif
- arcmsr_free_resource(acb);
- bus_release_resource(dev, SYS_RES_IRQ, 0, acb->irqres);
- cam_sim_free(acb->psim, /*free_devq*/TRUE);
- arcmsr_mutex_destroy(acb);
printf("arcmsr%d: xpt_bus_register failure!\n", unit);
- return ENXIO;
+ goto xpt_bus_failed;
}
if(xpt_create_path(&acb->ppath, /* periph */ NULL, cam_sim_path(acb->psim), CAM_TARGET_WILDCARD, CAM_LUN_WILDCARD) != CAM_REQ_CMP) {
- arcmsr_free_resource(acb);
- bus_release_resource(dev, SYS_RES_IRQ, 0, acb->irqres);
- xpt_bus_deregister(cam_sim_path(acb->psim));
- cam_sim_free(acb->psim, /* free_simq */ TRUE);
- arcmsr_mutex_destroy(acb);
printf("arcmsr%d: xpt_create_path failure!\n", unit);
- return ENXIO;
+ goto xpt_path_failed;
}
/*
****************************************************
@@ -4378,6 +4886,19 @@
arcmsr_callout_init(&acb->devmap_callout);
callout_reset(&acb->devmap_callout, 60 * hz, arcmsr_polling_devmap, acb);
return (0);
+xpt_path_failed:
+ xpt_bus_deregister(cam_sim_path(acb->psim));
+xpt_bus_failed:
+ cam_sim_free(acb->psim, /* free_simq */ TRUE);
+sim_alloc_failed:
+ cam_simq_free(devq);
+simq_alloc_failed:
+ arcmsr_teardown_intr(dev, acb);
+setup_intr_failed:
+ arcmsr_free_resource(acb);
+initialize_failed:
+ arcmsr_mutex_destroy(acb);
+ return ENXIO;
}
/*
@@ -4387,14 +4908,16 @@
static int arcmsr_probe(device_t dev)
{
u_int32_t id;
+ u_int16_t sub_device_id;
static char buf[256];
- char x_type[]={"X-TYPE"};
+ char x_type[]={"unknown"};
char *type;
int raid6 = 1;
-
+
if (pci_get_vendor(dev) != PCI_VENDOR_ID_ARECA) {
return (ENXIO);
}
+ sub_device_id = pci_read_config(dev, PCIR_SUBDEV_0, 2);
switch(id = pci_get_devid(dev)) {
case PCIDevVenIDARC1110:
case PCIDevVenIDARC1200:
@@ -4427,20 +4950,31 @@
case PCIDevVenIDARC1882:
case PCIDevVenIDARC1213:
case PCIDevVenIDARC1223:
- type = "SAS 6G";
+ if ((sub_device_id == ARECA_SUB_DEV_ID_1883) ||
+ (sub_device_id == ARECA_SUB_DEV_ID_1216) ||
+ (sub_device_id == ARECA_SUB_DEV_ID_1226))
+ type = "SAS 12G";
+ else
+ type = "SAS 6G";
break;
+ case PCIDevVenIDARC1884:
+ type = "SAS 12G";
+ break;
case PCIDevVenIDARC1214:
+ case PCIDevVenIDARC1203:
type = "SATA 6G";
break;
default:
type = x_type;
+ raid6 = 0;
break;
}
if(type == x_type)
return(ENXIO);
- sprintf(buf, "Areca %s Host Adapter RAID Controller %s\n", type, raid6 ? "(RAID6 capable)" : "");
+ sprintf(buf, "Areca %s Host Adapter RAID Controller %s\n%s\n",
+ type, raid6 ? "(RAID6 capable)" : "", ARCMSR_DRIVER_VERSION);
device_set_desc_copy(dev, buf);
- return 0;
+ return (BUS_PROBE_DEFAULT);
}
/*
************************************************************************
@@ -4452,7 +4986,7 @@
u_int32_t intmask_org;
struct CommandControlBlock *srb;
struct AdapterControlBlock *acb=(struct AdapterControlBlock *)device_get_softc(dev);
-
+
/* stop adapter background rebuild */
ARCMSR_LOCK_ACQUIRE(&acb->isr_lock);
/* disable all outbound interrupt */
@@ -4488,19 +5022,47 @@
************************************************************************
************************************************************************
*/
+static void arcmsr_teardown_intr(device_t dev, struct AdapterControlBlock *acb)
+{
+ int i;
+
+ if (acb->acb_flags & ACB_F_MSIX_ENABLED) {
+ for (i = 0; i < acb->msix_vectors; i++) {
+ if (acb->ih[i])
+ bus_teardown_intr(dev, acb->irqres[i], acb->ih[i]);
+ if (acb->irqres[i] != NULL)
+ bus_release_resource(dev, SYS_RES_IRQ,
+ acb->irq_id[i], acb->irqres[i]);
+
+ acb->ih[i] = NULL;
+ }
+ pci_release_msi(dev);
+ } else {
+ if (acb->ih[0])
+ bus_teardown_intr(dev, acb->irqres[0], acb->ih[0]);
+ if (acb->irqres[0] != NULL)
+ bus_release_resource(dev, SYS_RES_IRQ,
+ acb->irq_id[0], acb->irqres[0]);
+ acb->ih[0] = NULL;
+ }
+
+}
+/*
+************************************************************************
+************************************************************************
+*/
static int arcmsr_detach(device_t dev)
{
struct AdapterControlBlock *acb=(struct AdapterControlBlock *)device_get_softc(dev);
int i;
-
+
callout_stop(&acb->devmap_callout);
- bus_teardown_intr(dev, acb->irqres, acb->ih);
+ arcmsr_teardown_intr(dev, acb);
arcmsr_shutdown(dev);
arcmsr_free_resource(acb);
for(i=0; (acb->sys_res_arcmsr[i]!=NULL) && (i<2); i++) {
- bus_release_resource(dev, SYS_RES_MEMORY, PCIR_BAR(i), acb->sys_res_arcmsr[i]);
+ bus_release_resource(dev, SYS_RES_MEMORY, acb->rid[i], acb->sys_res_arcmsr[i]);
}
- bus_release_resource(dev, SYS_RES_IRQ, 0, acb->irqres);
ARCMSR_LOCK_ACQUIRE(&acb->isr_lock);
xpt_async(AC_LOST_DEVICE, acb->ppath, NULL);
xpt_free_path(acb->ppath);
@@ -4522,4 +5084,3 @@
printf("Queued Command Count =0x%x\n",acb->srboutstandingcount);
}
#endif
-
Modified: trunk/sys/dev/arcmsr/arcmsr.h
===================================================================
--- trunk/sys/dev/arcmsr/arcmsr.h 2018-05-28 00:25:20 UTC (rev 10127)
+++ trunk/sys/dev/arcmsr/arcmsr.h 2018-05-28 00:27:43 UTC (rev 10128)
@@ -1,3 +1,4 @@
+/* $MidnightBSD$ */
/*
********************************************************************************
** OS : FreeBSD
@@ -32,25 +33,26 @@
**(INCLUDING NEGLIGENCE OR OTHERWISE)ARISING IN ANY WAY OUT OF THE USE OF
** THIS SOFTWARE,EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
**************************************************************************
-* $MidnightBSD$
+* $FreeBSD: stable/10/sys/dev/arcmsr/arcmsr.h 326088 2017-11-22 06:36:55Z delphij $
*/
-#define ARCMSR_SCSI_INITIATOR_ID 255
-#define ARCMSR_DEV_SECTOR_SIZE 512
-#define ARCMSR_MAX_XFER_SECTORS 4096
-#define ARCMSR_MAX_TARGETID 17 /*16 max target id + 1*/
-#define ARCMSR_MAX_TARGETLUN 8 /*8*/
-#define ARCMSR_MAX_CHIPTYPE_NUM 4
-#define ARCMSR_MAX_OUTSTANDING_CMD 256
-#define ARCMSR_MAX_START_JOB 256
-#define ARCMSR_MAX_CMD_PERLUN ARCMSR_MAX_OUTSTANDING_CMD
-#define ARCMSR_MAX_FREESRB_NUM 384
-#define ARCMSR_MAX_QBUFFER 4096 /* ioctl QBUFFER */
-#define ARCMSR_MAX_SG_ENTRIES 38 /* max 38*/
-#define ARCMSR_MAX_ADAPTER 4
-#define ARCMSR_RELEASE_SIMQ_LEVEL 230
-#define ARCMSR_MAX_HBB_POSTQUEUE 264 /* (ARCMSR_MAX_OUTSTANDING_CMD+8) */
-#define ARCMSR_MAX_HBD_POSTQUEUE 256
-#define ARCMSR_TIMEOUT_DELAY 60 /* in sec */
+#define ARCMSR_SCSI_INITIATOR_ID 255
+#define ARCMSR_DEV_SECTOR_SIZE 512
+#define ARCMSR_MAX_XFER_SECTORS 4096
+#define ARCMSR_MAX_TARGETID 17 /*16 max target id + 1*/
+#define ARCMSR_MAX_TARGETLUN 8 /*8*/
+#define ARCMSR_MAX_CHIPTYPE_NUM 4
+#define ARCMSR_MAX_OUTSTANDING_CMD 256
+#define ARCMSR_MAX_START_JOB 256
+#define ARCMSR_MAX_CMD_PERLUN ARCMSR_MAX_OUTSTANDING_CMD
+#define ARCMSR_MAX_FREESRB_NUM 384
+#define ARCMSR_MAX_QBUFFER 4096 /* ioctl QBUFFER */
+#define ARCMSR_MAX_SG_ENTRIES 38 /* max 38*/
+#define ARCMSR_MAX_ADAPTER 4
+#define ARCMSR_RELEASE_SIMQ_LEVEL 230
+#define ARCMSR_MAX_HBB_POSTQUEUE 264 /* (ARCMSR_MAX_OUTSTANDING_CMD+8) */
+#define ARCMSR_MAX_HBD_POSTQUEUE 256
+#define ARCMSR_TIMEOUT_DELAY 60 /* in sec */
+#define ARCMSR_NUM_MSIX_VECTORS 4
/*
*********************************************************************
*/
@@ -75,7 +77,7 @@
#define ARCMSR_LOCK_RELEASE(l) mtx_unlock(l)
#define ARCMSR_LOCK_TRY(l) mtx_trylock(l)
#define arcmsr_htole32(x) htole32(x)
- typedef struct mtx arcmsr_lock_t;
+ typedef struct mtx arcmsr_lock_t;
#else
#define ARCMSR_LOCK_INIT(l, s) simple_lock_init(l)
#define ARCMSR_LOCK_DESTROY(l)
@@ -91,7 +93,7 @@
**
**********************************************************************************
*/
-#define PCI_VENDOR_ID_ARECA 0x17D3 /* Vendor ID */
+#define PCI_VENDOR_ID_ARECA 0x17D3 /* Vendor ID */
#define PCI_DEVICE_ID_ARECA_1110 0x1110 /* Device ID */
#define PCI_DEVICE_ID_ARECA_1120 0x1120 /* Device ID */
#define PCI_DEVICE_ID_ARECA_1130 0x1130 /* Device ID */
@@ -99,6 +101,7 @@
#define PCI_DEVICE_ID_ARECA_1170 0x1170 /* Device ID */
#define PCI_DEVICE_ID_ARECA_1200 0x1200 /* Device ID */
#define PCI_DEVICE_ID_ARECA_1201 0x1201 /* Device ID */
+#define PCI_DEVICE_ID_ARECA_1203 0x1203 /* Device ID */
#define PCI_DEVICE_ID_ARECA_1210 0x1210 /* Device ID */
#define PCI_DEVICE_ID_ARECA_1212 0x1212 /* Device ID */
#define PCI_DEVICE_ID_ARECA_1214 0x1214 /* Device ID */
@@ -115,13 +118,18 @@
#define PCI_DEVICE_ID_ARECA_1680 0x1680 /* Device ID */
#define PCI_DEVICE_ID_ARECA_1681 0x1681 /* Device ID */
#define PCI_DEVICE_ID_ARECA_1880 0x1880 /* Device ID */
+#define PCI_DEVICE_ID_ARECA_1884 0x1884 /* Device ID */
#define ARECA_SUB_DEV_ID_1880 0x1880 /* Subsystem Device ID */
#define ARECA_SUB_DEV_ID_1882 0x1882 /* Subsystem Device ID */
+#define ARECA_SUB_DEV_ID_1883 0x1883 /* Subsystem Device ID */
+#define ARECA_SUB_DEV_ID_1884 0x1884 /* Subsystem Device ID */
#define ARECA_SUB_DEV_ID_1212 0x1212 /* Subsystem Device ID */
#define ARECA_SUB_DEV_ID_1213 0x1213 /* Subsystem Device ID */
+#define ARECA_SUB_DEV_ID_1216 0x1216 /* Subsystem Device ID */
#define ARECA_SUB_DEV_ID_1222 0x1222 /* Subsystem Device ID */
#define ARECA_SUB_DEV_ID_1223 0x1223 /* Subsystem Device ID */
+#define ARECA_SUB_DEV_ID_1226 0x1226 /* Subsystem Device ID */
#define PCIDevVenIDARC1110 0x111017D3 /* Vendor Device ID */
#define PCIDevVenIDARC1120 0x112017D3 /* Vendor Device ID */
@@ -130,13 +138,14 @@
#define PCIDevVenIDARC1170 0x117017D3 /* Vendor Device ID */
#define PCIDevVenIDARC1200 0x120017D3 /* Vendor Device ID */
#define PCIDevVenIDARC1201 0x120117D3 /* Vendor Device ID */
+#define PCIDevVenIDARC1203 0x120317D3 /* Vendor Device ID */
#define PCIDevVenIDARC1210 0x121017D3 /* Vendor Device ID */
#define PCIDevVenIDARC1212 0x121217D3 /* Vendor Device ID */
-#define PCIDevVenIDARC1213 0x121317D3 /* Vendor Device ID */
-#define PCIDevVenIDARC1214 0x121417D3 /* Vendor Device ID */
+#define PCIDevVenIDARC1213 0x121317D3 /* Vendor Device ID */
+#define PCIDevVenIDARC1214 0x121417D3 /* Vendor Device ID */
#define PCIDevVenIDARC1220 0x122017D3 /* Vendor Device ID */
#define PCIDevVenIDARC1222 0x122217D3 /* Vendor Device ID */
-#define PCIDevVenIDARC1223 0x122317D3 /* Vendor Device ID */
+#define PCIDevVenIDARC1223 0x122317D3 /* Vendor Device ID */
#define PCIDevVenIDARC1230 0x123017D3 /* Vendor Device ID */
#define PCIDevVenIDARC1231 0x123117D3 /* Vendor Device ID */
#define PCIDevVenIDARC1260 0x126017D3 /* Vendor Device ID */
@@ -148,7 +157,8 @@
#define PCIDevVenIDARC1680 0x168017D3 /* Vendor Device ID */
#define PCIDevVenIDARC1681 0x168117D3 /* Vendor Device ID */
#define PCIDevVenIDARC1880 0x188017D3 /* Vendor Device ID */
-#define PCIDevVenIDARC1882 0x188217D3 /* Vendor Device ID */
+#define PCIDevVenIDARC1882 0x188217D3 /* Vendor Device ID */
+#define PCIDevVenIDARC1884 0x188417D3 /* Vendor Device ID */
#ifndef PCIR_BARS
#define PCIR_BARS 0x10
@@ -175,18 +185,20 @@
**
**********************************************************************************
*/
-#define arcmsr_ccbsrb_ptr spriv_ptr0
-#define arcmsr_ccbacb_ptr spriv_ptr1
-#define dma_addr_hi32(addr) (u_int32_t) ((addr>>16)>>16)
-#define dma_addr_lo32(addr) (u_int32_t) (addr & 0xffffffff)
-#define get_min(x,y) ((x) < (y) ? (x) : (y))
-#define get_max(x,y) ((x) < (y) ? (y) : (x))
+#define arcmsr_ccbsrb_ptr spriv_ptr0
+#define arcmsr_ccbacb_ptr spriv_ptr1
+#define dma_addr_hi32(addr) (u_int32_t) ((addr>>16)>>16)
+#define dma_addr_lo32(addr) (u_int32_t) (addr & 0xffffffff)
+#define get_min(x,y) ((x) < (y) ? (x) : (y))
+#define get_max(x,y) ((x) < (y) ? (y) : (x))
/*
**************************************************************************
**************************************************************************
*/
-#define CHIP_REG_READ32(s, b, r) bus_space_read_4(acb->btag[b], acb->bhandle[b], offsetof(struct s, r))
+#define CHIP_REG_READ32(s, b, r) bus_space_read_4(acb->btag[b], acb->bhandle[b], offsetof(struct s, r))
#define CHIP_REG_WRITE32(s, b, r, d) bus_space_write_4(acb->btag[b], acb->bhandle[b], offsetof(struct s, r), d)
+#define READ_CHIP_REG32(b, r) bus_space_read_4(acb->btag[b], acb->bhandle[b], r)
+#define WRITE_CHIP_REG32(b, r, d) bus_space_write_4(acb->btag[b], acb->bhandle[b], r, d)
/*
**********************************************************************************
** IOCTL CONTROL Mail Box
@@ -209,17 +221,17 @@
/************************************************************************/
/************************************************************************/
-#define ARCMSR_IOP_ERROR_ILLEGALPCI 0x0001
-#define ARCMSR_IOP_ERROR_VENDORID 0x0002
-#define ARCMSR_IOP_ERROR_DEVICEID 0x0002
-#define ARCMSR_IOP_ERROR_ILLEGALCDB 0x0003
-#define ARCMSR_IOP_ERROR_UNKNOW_CDBERR 0x0004
-#define ARCMSR_SYS_ERROR_MEMORY_ALLOCATE 0x0005
-#define ARCMSR_SYS_ERROR_MEMORY_CROSS4G 0x0006
-#define ARCMSR_SYS_ERROR_MEMORY_LACK 0x0007
-#define ARCMSR_SYS_ERROR_MEMORY_RANGE 0x0008
-#define ARCMSR_SYS_ERROR_DEVICE_BASE 0x0009
-#define ARCMSR_SYS_ERROR_PORT_VALIDATE 0x000A
+#define ARCMSR_IOP_ERROR_ILLEGALPCI 0x0001
+#define ARCMSR_IOP_ERROR_VENDORID 0x0002
+#define ARCMSR_IOP_ERROR_DEVICEID 0x0002
+#define ARCMSR_IOP_ERROR_ILLEGALCDB 0x0003
+#define ARCMSR_IOP_ERROR_UNKNOW_CDBERR 0x0004
+#define ARCMSR_SYS_ERROR_MEMORY_ALLOCATE 0x0005
+#define ARCMSR_SYS_ERROR_MEMORY_CROSS4G 0x0006
+#define ARCMSR_SYS_ERROR_MEMORY_LACK 0x0007
+#define ARCMSR_SYS_ERROR_MEMORY_RANGE 0x0008
+#define ARCMSR_SYS_ERROR_DEVICE_BASE 0x0009
+#define ARCMSR_SYS_ERROR_PORT_VALIDATE 0x000A
/*DeviceType*/
#define ARECA_SATA_RAID 0x90000000
@@ -251,10 +263,10 @@
#define ARCMSR_MESSAGE_FLUSH_ADAPTER_CACHE _IOWR('F', FUNCTION_FLUSH_ADAPTER_CACHE, struct CMD_MESSAGE_FIELD)
/* ARECA IOCTL ReturnCode */
-#define ARCMSR_MESSAGE_RETURNCODE_OK 0x00000001
-#define ARCMSR_MESSAGE_RETURNCODE_ERROR 0x00000006
-#define ARCMSR_MESSAGE_RETURNCODE_3F 0x0000003F
-#define ARCMSR_IOCTL_RETURNCODE_BUS_HANG_ON 0x00000088
+#define ARCMSR_MESSAGE_RETURNCODE_OK 0x00000001
+#define ARCMSR_MESSAGE_RETURNCODE_ERROR 0x00000006
+#define ARCMSR_MESSAGE_RETURNCODE_3F 0x0000003F
+#define ARCMSR_IOCTL_RETURNCODE_BUS_HANG_ON 0x00000088
/*
************************************************************************
** SPEC. for Areca HBA adapter
@@ -261,34 +273,34 @@
************************************************************************
*/
/* signature of set and get firmware config */
-#define ARCMSR_SIGNATURE_GET_CONFIG 0x87974060
-#define ARCMSR_SIGNATURE_SET_CONFIG 0x87974063
+#define ARCMSR_SIGNATURE_GET_CONFIG 0x87974060
+#define ARCMSR_SIGNATURE_SET_CONFIG 0x87974063
/* message code of inbound message register */
-#define ARCMSR_INBOUND_MESG0_NOP 0x00000000
-#define ARCMSR_INBOUND_MESG0_GET_CONFIG 0x00000001
-#define ARCMSR_INBOUND_MESG0_SET_CONFIG 0x00000002
-#define ARCMSR_INBOUND_MESG0_ABORT_CMD 0x00000003
-#define ARCMSR_INBOUND_MESG0_STOP_BGRB 0x00000004
-#define ARCMSR_INBOUND_MESG0_FLUSH_CACHE 0x00000005
-#define ARCMSR_INBOUND_MESG0_START_BGRB 0x00000006
-#define ARCMSR_INBOUND_MESG0_CHK331PENDING 0x00000007
-#define ARCMSR_INBOUND_MESG0_SYNC_TIMER 0x00000008
+#define ARCMSR_INBOUND_MESG0_NOP 0x00000000
+#define ARCMSR_INBOUND_MESG0_GET_CONFIG 0x00000001
+#define ARCMSR_INBOUND_MESG0_SET_CONFIG 0x00000002
+#define ARCMSR_INBOUND_MESG0_ABORT_CMD 0x00000003
+#define ARCMSR_INBOUND_MESG0_STOP_BGRB 0x00000004
+#define ARCMSR_INBOUND_MESG0_FLUSH_CACHE 0x00000005
+#define ARCMSR_INBOUND_MESG0_START_BGRB 0x00000006
+#define ARCMSR_INBOUND_MESG0_CHK331PENDING 0x00000007
+#define ARCMSR_INBOUND_MESG0_SYNC_TIMER 0x00000008
/* doorbell interrupt generator */
-#define ARCMSR_INBOUND_DRIVER_DATA_WRITE_OK 0x00000001
-#define ARCMSR_INBOUND_DRIVER_DATA_READ_OK 0x00000002
-#define ARCMSR_OUTBOUND_IOP331_DATA_WRITE_OK 0x00000001
-#define ARCMSR_OUTBOUND_IOP331_DATA_READ_OK 0x00000002
+#define ARCMSR_INBOUND_DRIVER_DATA_WRITE_OK 0x00000001
+#define ARCMSR_INBOUND_DRIVER_DATA_READ_OK 0x00000002
+#define ARCMSR_OUTBOUND_IOP331_DATA_WRITE_OK 0x00000001
+#define ARCMSR_OUTBOUND_IOP331_DATA_READ_OK 0x00000002
/* srb areca cdb flag */
-#define ARCMSR_SRBPOST_FLAG_SGL_BSIZE 0x80000000
-#define ARCMSR_SRBPOST_FLAG_IAM_BIOS 0x40000000
-#define ARCMSR_SRBREPLY_FLAG_IAM_BIOS 0x40000000
-#define ARCMSR_SRBREPLY_FLAG_ERROR 0x10000000
-#define ARCMSR_SRBREPLY_FLAG_ERROR_MODE0 0x10000000
-#define ARCMSR_SRBREPLY_FLAG_ERROR_MODE1 0x00000001
+#define ARCMSR_SRBPOST_FLAG_SGL_BSIZE 0x80000000
+#define ARCMSR_SRBPOST_FLAG_IAM_BIOS 0x40000000
+#define ARCMSR_SRBREPLY_FLAG_IAM_BIOS 0x40000000
+#define ARCMSR_SRBREPLY_FLAG_ERROR 0x10000000
+#define ARCMSR_SRBREPLY_FLAG_ERROR_MODE0 0x10000000
+#define ARCMSR_SRBREPLY_FLAG_ERROR_MODE1 0x00000001
/* outbound firmware ok */
-#define ARCMSR_OUTBOUND_MESG1_FIRMWARE_OK 0x80000000
+#define ARCMSR_OUTBOUND_MESG1_FIRMWARE_OK 0x80000000
-#define ARCMSR_ARC1680_BUS_RESET 0x00000003
+#define ARCMSR_ARC1680_BUS_RESET 0x00000003
/*
************************************************************************
** SPEC. for Areca HBB adapter
@@ -300,6 +312,11 @@
#define ARCMSR_IOP2DRV_DOORBELL 0x00020408 /* window of "instruction flags" from iop to driver */
#define ARCMSR_IOP2DRV_DOORBELL_MASK 0x0002040C
+#define ARCMSR_IOP2DRV_DOORBELL_1203 0x00021870 /* window of "instruction flags" from iop to driver */
+#define ARCMSR_IOP2DRV_DOORBELL_MASK_1203 0x00021874
+#define ARCMSR_DRV2IOP_DOORBELL_1203 0x00021878 /* window of "instruction flags" from driver to iop */
+#define ARCMSR_DRV2IOP_DOORBELL_MASK_1203 0x0002187C
+
/* ARECA FLAG LANGUAGE */
#define ARCMSR_IOP2DRV_DATA_WRITE_OK 0x00000001 /* ioctl transfer */
#define ARCMSR_IOP2DRV_DATA_READ_OK 0x00000002 /* ioctl transfer */
@@ -306,20 +323,20 @@
#define ARCMSR_IOP2DRV_CDB_DONE 0x00000004
#define ARCMSR_IOP2DRV_MESSAGE_CMD_DONE 0x00000008
-#define ARCMSR_DOORBELL_HANDLE_INT 0x0000000F
+#define ARCMSR_DOORBELL_HANDLE_INT 0x0000000F
#define ARCMSR_DOORBELL_INT_CLEAR_PATTERN 0xFF00FFF0
#define ARCMSR_MESSAGE_INT_CLEAR_PATTERN 0xFF00FFF7
-#define ARCMSR_MESSAGE_GET_CONFIG 0x00010008 /* (ARCMSR_INBOUND_MESG0_GET_CONFIG<<16)|ARCMSR_DRV2IOP_MESSAGE_CMD_POSTED) */
-#define ARCMSR_MESSAGE_SET_CONFIG 0x00020008 /* (ARCMSR_INBOUND_MESG0_SET_CONFIG<<16)|ARCMSR_DRV2IOP_MESSAGE_CMD_POSTED) */
-#define ARCMSR_MESSAGE_ABORT_CMD 0x00030008 /* (ARCMSR_INBOUND_MESG0_ABORT_CMD<<16)|ARCMSR_DRV2IOP_MESSAGE_CMD_POSTED) */
-#define ARCMSR_MESSAGE_STOP_BGRB 0x00040008 /* (ARCMSR_INBOUND_MESG0_STOP_BGRB<<16)|ARCMSR_DRV2IOP_MESSAGE_CMD_POSTED) */
+#define ARCMSR_MESSAGE_GET_CONFIG 0x00010008 /* (ARCMSR_INBOUND_MESG0_GET_CONFIG<<16)|ARCMSR_DRV2IOP_MESSAGE_CMD_POSTED) */
+#define ARCMSR_MESSAGE_SET_CONFIG 0x00020008 /* (ARCMSR_INBOUND_MESG0_SET_CONFIG<<16)|ARCMSR_DRV2IOP_MESSAGE_CMD_POSTED) */
+#define ARCMSR_MESSAGE_ABORT_CMD 0x00030008 /* (ARCMSR_INBOUND_MESG0_ABORT_CMD<<16)|ARCMSR_DRV2IOP_MESSAGE_CMD_POSTED) */
+#define ARCMSR_MESSAGE_STOP_BGRB 0x00040008 /* (ARCMSR_INBOUND_MESG0_STOP_BGRB<<16)|ARCMSR_DRV2IOP_MESSAGE_CMD_POSTED) */
#define ARCMSR_MESSAGE_FLUSH_CACHE 0x00050008 /* (ARCMSR_INBOUND_MESG0_FLUSH_CACHE<<16)|ARCMSR_DRV2IOP_MESSAGE_CMD_POSTED) */
-#define ARCMSR_MESSAGE_START_BGRB 0x00060008 /* (ARCMSR_INBOUND_MESG0_START_BGRB<<16)|ARCMSR_DRV2IOP_MESSAGE_CMD_POSTED) */
-#define ARCMSR_MESSAGE_START_DRIVER_MODE 0x000E0008
-#define ARCMSR_MESSAGE_SET_POST_WINDOW 0x000F0008
-#define ARCMSR_MESSAGE_ACTIVE_EOI_MODE 0x00100008
-#define ARCMSR_MESSAGE_FIRMWARE_OK 0x80000000 /* ARCMSR_OUTBOUND_MESG1_FIRMWARE_OK */
+#define ARCMSR_MESSAGE_START_BGRB 0x00060008 /* (ARCMSR_INBOUND_MESG0_START_BGRB<<16)|ARCMSR_DRV2IOP_MESSAGE_CMD_POSTED) */
+#define ARCMSR_MESSAGE_START_DRIVER_MODE 0x000E0008
+#define ARCMSR_MESSAGE_SET_POST_WINDOW 0x000F0008
+#define ARCMSR_MESSAGE_ACTIVE_EOI_MODE 0x00100008
+#define ARCMSR_MESSAGE_FIRMWARE_OK 0x80000000 /* ARCMSR_OUTBOUND_MESG1_FIRMWARE_OK */
#define ARCMSR_DRV2IOP_DATA_WRITE_OK 0x00000001 /* ioctl transfer */
#define ARCMSR_DRV2IOP_DATA_READ_OK 0x00000002 /* ioctl transfer */
@@ -328,13 +345,13 @@
#define ARCMSR_DRV2IOP_END_OF_INTERRUPT 0x00000010 /* */
/* data tunnel buffer between user space program and its firmware */
-#define ARCMSR_MSGCODE_RWBUFFER 0x0000fa00 /* iop msgcode_rwbuffer for message command */
-#define ARCMSR_IOCTL_WBUFFER 0x0000fe00 /* user space data to iop 128bytes */
-#define ARCMSR_IOCTL_RBUFFER 0x0000ff00 /* iop data to user space 128bytes */
-#define ARCMSR_HBB_BASE0_OFFSET 0x00000010
-#define ARCMSR_HBB_BASE1_OFFSET 0x00000018
-#define ARCMSR_HBB_BASE0_LEN 0x00021000
-#define ARCMSR_HBB_BASE1_LEN 0x00010000
+#define ARCMSR_MSGCODE_RWBUFFER 0x0000fa00 /* iop msgcode_rwbuffer for message command */
+#define ARCMSR_IOCTL_WBUFFER 0x0000fe00 /* user space data to iop 128bytes */
+#define ARCMSR_IOCTL_RBUFFER 0x0000ff00 /* iop data to user space 128bytes */
+#define ARCMSR_HBB_BASE0_OFFSET 0x00000010
+#define ARCMSR_HBB_BASE1_OFFSET 0x00000018
+#define ARCMSR_HBB_BASE0_LEN 0x00021000
+#define ARCMSR_HBB_BASE1_LEN 0x00010000
/*
************************************************************************
** SPEC. for Areca HBC adapter
@@ -382,9 +399,9 @@
#define ARCMSR_HBCMU_IOP2DRV_DATA_READ_DOORBELL_CLEAR 0x00000004/*outbound DATA READ isr door bell clear*/
#define ARCMSR_HBCMU_IOP2DRV_MESSAGE_CMD_DONE 0x00000008/*outbound message 0 ready*/
#define ARCMSR_HBCMU_IOP2DRV_MESSAGE_CMD_DONE_DOORBELL_CLEAR 0x00000008/*outbound message cmd isr door bell clear*/
-#define ARCMSR_HBCMU_MESSAGE_FIRMWARE_OK 0x80000000/*ARCMSR_HBCMU_MESSAGE_FIRMWARE_OK*/
+#define ARCMSR_HBCMU_MESSAGE_FIRMWARE_OK 0x80000000/*ARCMSR_HBCMU_MESSAGE_FIRMWARE_OK*/
#define ARCMSR_HBCMU_RESET_ADAPTER 0x00000024
-#define ARCMSR_HBCMU_DiagWrite_ENABLE 0x00000080
+#define ARCMSR_HBCMU_DiagWrite_ENABLE 0x00000080
/*
************************************************************************
@@ -391,22 +408,22 @@
** SPEC. for Areca HBD adapter
************************************************************************
*/
-#define ARCMSR_HBDMU_CHIP_ID 0x00004
+#define ARCMSR_HBDMU_CHIP_ID 0x00004
#define ARCMSR_HBDMU_CPU_MEMORY_CONFIGURATION 0x00008
-#define ARCMSR_HBDMU_I2_HOST_INTERRUPT_MASK 0x00034
-#define ARCMSR_HBDMU_MAIN_INTERRUPT_STATUS 0x00200
+#define ARCMSR_HBDMU_I2_HOST_INTERRUPT_MASK 0x00034
+#define ARCMSR_HBDMU_MAIN_INTERRUPT_STATUS 0x00200
#define ARCMSR_HBDMU_PCIE_F0_INTERRUPT_ENABLE 0x0020C
-#define ARCMSR_HBDMU_INBOUND_MESSAGE0 0x00400
-#define ARCMSR_HBDMU_INBOUND_MESSAGE1 0x00404
-#define ARCMSR_HBDMU_OUTBOUND_MESSAGE0 0x00420
-#define ARCMSR_HBDMU_OUTBOUND_MESSAGE1 0x00424
-#define ARCMSR_HBDMU_INBOUND_DOORBELL 0x00460
-#define ARCMSR_HBDMU_OUTBOUND_DOORBELL 0x00480
+#define ARCMSR_HBDMU_INBOUND_MESSAGE0 0x00400
+#define ARCMSR_HBDMU_INBOUND_MESSAGE1 0x00404
+#define ARCMSR_HBDMU_OUTBOUND_MESSAGE0 0x00420
+#define ARCMSR_HBDMU_OUTBOUND_MESSAGE1 0x00424
+#define ARCMSR_HBDMU_INBOUND_DOORBELL 0x00460
+#define ARCMSR_HBDMU_OUTBOUND_DOORBELL 0x00480
#define ARCMSR_HBDMU_OUTBOUND_DOORBELL_ENABLE 0x00484
-#define ARCMSR_HBDMU_INBOUND_LIST_BASE_LOW 0x01000
-#define ARCMSR_HBDMU_INBOUND_LIST_BASE_HIGH 0x01004
+#define ARCMSR_HBDMU_INBOUND_LIST_BASE_LOW 0x01000
+#define ARCMSR_HBDMU_INBOUND_LIST_BASE_HIGH 0x01004
#define ARCMSR_HBDMU_INBOUND_LIST_WRITE_POINTER 0x01018
-#define ARCMSR_HBDMU_OUTBOUND_LIST_BASE_LOW 0x01060
+#define ARCMSR_HBDMU_OUTBOUND_LIST_BASE_LOW 0x01060
#define ARCMSR_HBDMU_OUTBOUND_LIST_BASE_HIGH 0x01064
#define ARCMSR_HBDMU_OUTBOUND_LIST_COPY_POINTER 0x0106C
#define ARCMSR_HBDMU_OUTBOUND_LIST_READ_POINTER 0x01070
@@ -413,33 +430,33 @@
#define ARCMSR_HBDMU_OUTBOUND_INTERRUPT_CAUSE 0x01088
#define ARCMSR_HBDMU_OUTBOUND_INTERRUPT_ENABLE 0x0108C
-#define ARCMSR_HBDMU_MESSAGE_WBUFFER 0x02000
-#define ARCMSR_HBDMU_MESSAGE_RBUFFER 0x02100
-#define ARCMSR_HBDMU_MESSAGE_RWBUFFER 0x02200
+#define ARCMSR_HBDMU_MESSAGE_WBUFFER 0x02000
+#define ARCMSR_HBDMU_MESSAGE_RBUFFER 0x02100
+#define ARCMSR_HBDMU_MESSAGE_RWBUFFER 0x02200
-#define ARCMSR_HBDMU_ISR_THROTTLING_LEVEL 16
-#define ARCMSR_HBDMU_ISR_MAX_DONE_QUEUE 20
+#define ARCMSR_HBDMU_ISR_THROTTLING_LEVEL 16
+#define ARCMSR_HBDMU_ISR_MAX_DONE_QUEUE 20
/* Host Interrupt Mask */
-#define ARCMSR_HBDMU_ALL_INT_ENABLE 0x00001010 /* enable all ISR */
-#define ARCMSR_HBDMU_ALL_INT_DISABLE 0x00000000 /* disable all ISR */
+#define ARCMSR_HBDMU_ALL_INT_ENABLE 0x00001010 /* enable all ISR */
+#define ARCMSR_HBDMU_ALL_INT_DISABLE 0x00000000 /* disable all ISR */
/* Host Interrupt Status */
-#define ARCMSR_HBDMU_OUTBOUND_INT 0x00001010
-#define ARCMSR_HBDMU_OUTBOUND_DOORBELL_INT 0x00001000
-#define ARCMSR_HBDMU_OUTBOUND_POSTQUEUE_INT 0x00000010
+#define ARCMSR_HBDMU_OUTBOUND_INT 0x00001010
+#define ARCMSR_HBDMU_OUTBOUND_DOORBELL_INT 0x00001000
+#define ARCMSR_HBDMU_OUTBOUND_POSTQUEUE_INT 0x00000010
/* DoorBell*/
-#define ARCMSR_HBDMU_DRV2IOP_DATA_IN_READY 0x00000001
-#define ARCMSR_HBDMU_DRV2IOP_DATA_OUT_READ 0x00000002
+#define ARCMSR_HBDMU_DRV2IOP_DATA_IN_READY 0x00000001
+#define ARCMSR_HBDMU_DRV2IOP_DATA_OUT_READ 0x00000002
-#define ARCMSR_HBDMU_IOP2DRV_DATA_WRITE_OK 0x00000001
-#define ARCMSR_HBDMU_IOP2DRV_DATA_READ_OK 0x00000002
+#define ARCMSR_HBDMU_IOP2DRV_DATA_WRITE_OK 0x00000001
+#define ARCMSR_HBDMU_IOP2DRV_DATA_READ_OK 0x00000002
/*outbound message 0 ready*/
#define ARCMSR_HBDMU_IOP2DRV_MESSAGE_CMD_DONE 0x02000000
-#define ARCMSR_HBDMU_F0_DOORBELL_CAUSE 0x02000003
+#define ARCMSR_HBDMU_F0_DOORBELL_CAUSE 0x02000003
/*outbound message cmd isr door bell clear*/
#define ARCMSR_HBDMU_IOP2DRV_MESSAGE_CMD_DONE_CLEAR 0x02000000
@@ -449,7 +466,27 @@
#define ARCMSR_HBDMU_OUTBOUND_LIST_INTERRUPT_CLEAR 0x00000001
/*ARCMSR_HBAMU_MESSAGE_FIRMWARE_OK*/
-#define ARCMSR_HBDMU_MESSAGE_FIRMWARE_OK 0x80000000
+#define ARCMSR_HBDMU_MESSAGE_FIRMWARE_OK 0x80000000
+/*
+*******************************************************************************
+** SPEC. for Areca HBE adapter
+*******************************************************************************
+*/
+#define ARCMSR_SIGNATURE_1884 0x188417D3
+#define ARCMSR_HBEMU_OUTBOUND_DOORBELL_ISR 0x00000001
+#define ARCMSR_HBEMU_OUTBOUND_POSTQUEUE_ISR 0x00000008
+#define ARCMSR_HBEMU_ALL_INTMASKENABLE 0x00000009 /* disable all ISR */
+
+#define ARCMSR_HBEMU_DRV2IOP_DATA_WRITE_OK 0x00000002
+#define ARCMSR_HBEMU_DRV2IOP_DATA_READ_OK 0x00000004
+#define ARCMSR_HBEMU_DRV2IOP_MESSAGE_CMD_DONE 0x00000008 /* inbound message 0 ready */
+#define ARCMSR_HBEMU_IOP2DRV_DATA_WRITE_OK 0x00000002
+#define ARCMSR_HBEMU_IOP2DRV_DATA_READ_OK 0x00000004
+#define ARCMSR_HBEMU_IOP2DRV_MESSAGE_CMD_DONE 0x00000008 /* outbound message 0 ready */
+#define ARCMSR_HBEMU_MESSAGE_FIRMWARE_OK 0x80000000 /* ARCMSR_HBCMU_MESSAGE_FIRMWARE_OK */
+/* ARC-1884 doorbell sync */
+#define ARCMSR_HBEMU_DOORBELL_SYNC 0x100
+#define ARCMSR_ARC188X_RESET_ADAPTER 0x00000004
/*
*********************************************************************
** Message Unit structure
@@ -457,28 +494,28 @@
*/
struct HBA_MessageUnit
{
- u_int32_t resrved0[4]; /*0000 000F*/
- u_int32_t inbound_msgaddr0; /*0010 0013*/
- u_int32_t inbound_msgaddr1; /*0014 0017*/
- u_int32_t outbound_msgaddr0; /*0018 001B*/
- u_int32_t outbound_msgaddr1; /*001C 001F*/
- u_int32_t inbound_doorbell; /*0020 0023*/
- u_int32_t inbound_intstatus; /*0024 0027*/
- u_int32_t inbound_intmask; /*0028 002B*/
- u_int32_t outbound_doorbell; /*002C 002F*/
- u_int32_t outbound_intstatus; /*0030 0033*/
- u_int32_t outbound_intmask; /*0034 0037*/
- u_int32_t reserved1[2]; /*0038 003F*/
- u_int32_t inbound_queueport; /*0040 0043*/
- u_int32_t outbound_queueport; /*0044 0047*/
- u_int32_t reserved2[2]; /*0048 004F*/
- u_int32_t reserved3[492]; /*0050 07FF ......local_buffer 492*/
- u_int32_t reserved4[128]; /*0800 09FF 128*/
- u_int32_t msgcode_rwbuffer[256]; /*0a00 0DFF 256*/
- u_int32_t message_wbuffer[32]; /*0E00 0E7F 32*/
- u_int32_t reserved5[32]; /*0E80 0EFF 32*/
- u_int32_t message_rbuffer[32]; /*0F00 0F7F 32*/
- u_int32_t reserved6[32]; /*0F80 0FFF 32*/
+ u_int32_t resrved0[4]; /*0000 000F*/
+ u_int32_t inbound_msgaddr0; /*0010 0013*/
+ u_int32_t inbound_msgaddr1; /*0014 0017*/
+ u_int32_t outbound_msgaddr0; /*0018 001B*/
+ u_int32_t outbound_msgaddr1; /*001C 001F*/
+ u_int32_t inbound_doorbell; /*0020 0023*/
+ u_int32_t inbound_intstatus; /*0024 0027*/
+ u_int32_t inbound_intmask; /*0028 002B*/
+ u_int32_t outbound_doorbell; /*002C 002F*/
+ u_int32_t outbound_intstatus; /*0030 0033*/
+ u_int32_t outbound_intmask; /*0034 0037*/
+ u_int32_t reserved1[2]; /*0038 003F*/
+ u_int32_t inbound_queueport; /*0040 0043*/
+ u_int32_t outbound_queueport; /*0044 0047*/
+ u_int32_t reserved2[2]; /*0048 004F*/
+ u_int32_t reserved3[492]; /*0050 07FF ......local_buffer 492*/
+ u_int32_t reserved4[128]; /*0800 09FF 128*/
+ u_int32_t msgcode_rwbuffer[256]; /*0a00 0DFF 256*/
+ u_int32_t message_wbuffer[32]; /*0E00 0E7F 32*/
+ u_int32_t reserved5[32]; /*0E80 0EFF 32*/
+ u_int32_t message_rbuffer[32]; /*0F00 0F7F 32*/
+ u_int32_t reserved6[32]; /*0F80 0FFF 32*/
};
/*
*********************************************************************
@@ -485,13 +522,21 @@
**
*********************************************************************
*/
+struct HBB_DOORBELL_1203
+{
+ u_int8_t doorbell_reserved[ARCMSR_IOP2DRV_DOORBELL_1203]; /*reserved */
+ u_int32_t iop2drv_doorbell; /*offset 0x00021870:00,01,02,03: window of "instruction flags" from iop to driver */
+ u_int32_t iop2drv_doorbell_mask; /* 04,05,06,07: doorbell mask */
+ u_int32_t drv2iop_doorbell; /* 08,09,10,11: window of "instruction flags" from driver to iop */
+ u_int32_t drv2iop_doorbell_mask; /* 12,13,14,15: doorbell mask */
+};
struct HBB_DOORBELL
{
- u_int8_t doorbell_reserved[ARCMSR_DRV2IOP_DOORBELL]; /*reserved */
- u_int32_t drv2iop_doorbell; /*offset 0x00020400:00,01,02,03: window of "instruction flags" from driver to iop */
- u_int32_t drv2iop_doorbell_mask; /* 04,05,06,07: doorbell mask */
- u_int32_t iop2drv_doorbell; /* 08,09,10,11: window of "instruction flags" from iop to driver */
- u_int32_t iop2drv_doorbell_mask; /* 12,13,14,15: doorbell mask */
+ u_int8_t doorbell_reserved[ARCMSR_DRV2IOP_DOORBELL]; /*reserved */
+ u_int32_t drv2iop_doorbell; /*offset 0x00020400:00,01,02,03: window of "instruction flags" from driver to iop */
+ u_int32_t drv2iop_doorbell_mask; /* 04,05,06,07: doorbell mask */
+ u_int32_t iop2drv_doorbell; /* 08,09,10,11: window of "instruction flags" from iop to driver */
+ u_int32_t iop2drv_doorbell_mask; /* 12,13,14,15: doorbell mask */
};
/*
*********************************************************************
@@ -500,11 +545,11 @@
*/
struct HBB_RWBUFFER
{
- u_int8_t message_reserved0[ARCMSR_MSGCODE_RWBUFFER]; /*reserved */
- u_int32_t msgcode_rwbuffer[256]; /*offset 0x0000fa00: 0, 1, 2, 3,...,1023: message code read write 1024bytes */
- u_int32_t message_wbuffer[32]; /*offset 0x0000fe00:1024,1025,1026,1027,...,1151: user space data to iop 128bytes */
- u_int32_t message_reserved1[32]; /* 1152,1153,1154,1155,...,1279: message reserved*/
- u_int32_t message_rbuffer[32]; /*offset 0x0000ff00:1280,1281,1282,1283,...,1407: iop data to user space 128bytes */
+ u_int8_t message_reserved0[ARCMSR_MSGCODE_RWBUFFER]; /*reserved */
+ u_int32_t msgcode_rwbuffer[256]; /*offset 0x0000fa00: 0, 1, 2, 3,...,1023: message code read write 1024bytes */
+ u_int32_t message_wbuffer[32]; /*offset 0x0000fe00:1024,1025,1026,1027,...,1151: user space data to iop 128bytes */
+ u_int32_t message_reserved1[32]; /* 1152,1153,1154,1155,...,1279: message reserved*/
+ u_int32_t message_rbuffer[32]; /*offset 0x0000ff00:1280,1281,1282,1283,...,1407: iop data to user space 128bytes */
};
/*
*********************************************************************
@@ -513,12 +558,16 @@
*/
struct HBB_MessageUnit
{
- u_int32_t post_qbuffer[ARCMSR_MAX_HBB_POSTQUEUE]; /* post queue buffer for iop */
- u_int32_t done_qbuffer[ARCMSR_MAX_HBB_POSTQUEUE]; /* done queue buffer for iop */
- int32_t postq_index; /* post queue index */
- int32_t doneq_index; /* done queue index */
+ u_int32_t post_qbuffer[ARCMSR_MAX_HBB_POSTQUEUE]; /* post queue buffer for iop */
+ u_int32_t done_qbuffer[ARCMSR_MAX_HBB_POSTQUEUE]; /* done queue buffer for iop */
+ int32_t postq_index; /* post queue index */
+ int32_t doneq_index; /* done queue index */
struct HBB_DOORBELL *hbb_doorbell;
struct HBB_RWBUFFER *hbb_rwbuffer;
+ bus_size_t drv2iop_doorbell; /* window of "instruction flags" from driver to iop */
+ bus_size_t drv2iop_doorbell_mask; /* doorbell mask */
+ bus_size_t iop2drv_doorbell; /* window of "instruction flags" from iop to driver */
+ bus_size_t iop2drv_doorbell_mask; /* doorbell mask */
};
/*
@@ -530,71 +579,71 @@
u_int32_t message_unit_status; /*0000 0003*/
u_int32_t slave_error_attribute; /*0004 0007*/
u_int32_t slave_error_address; /*0008 000B*/
- u_int32_t posted_outbound_doorbell; /*000C 000F*/
+ u_int32_t posted_outbound_doorbell; /*000C 000F*/
u_int32_t master_error_attribute; /*0010 0013*/
- u_int32_t master_error_address_low; /*0014 0017*/
- u_int32_t master_error_address_high; /*0018 001B*/
+ u_int32_t master_error_address_low; /*0014 0017*/
+ u_int32_t master_error_address_high; /*0018 001B*/
u_int32_t hcb_size; /*001C 001F size of the PCIe window used for HCB_Mode accesses*/
- u_int32_t inbound_doorbell; /*0020 0023*/
- u_int32_t diagnostic_rw_data; /*0024 0027*/
- u_int32_t diagnostic_rw_address_low; /*0028 002B*/
- u_int32_t diagnostic_rw_address_high; /*002C 002F*/
- u_int32_t host_int_status; /*0030 0033 host interrupt status*/
- u_int32_t host_int_mask; /*0034 0037 host interrupt mask*/
- u_int32_t dcr_data; /*0038 003B*/
- u_int32_t dcr_address; /*003C 003F*/
- u_int32_t inbound_queueport; /*0040 0043 port32 host inbound queue port*/
- u_int32_t outbound_queueport; /*0044 0047 port32 host outbound queue port*/
- u_int32_t hcb_pci_address_low; /*0048 004B*/
- u_int32_t hcb_pci_address_high; /*004C 004F*/
- u_int32_t iop_int_status; /*0050 0053*/
- u_int32_t iop_int_mask; /*0054 0057*/
- u_int32_t iop_inbound_queue_port; /*0058 005B*/
- u_int32_t iop_outbound_queue_port; /*005C 005F*/
- u_int32_t inbound_free_list_index; /*0060 0063 inbound free list producer consumer index*/
- u_int32_t inbound_post_list_index; /*0064 0067 inbound post list producer consumer index*/
- u_int32_t outbound_free_list_index; /*0068 006B outbound free list producer consumer index*/
- u_int32_t outbound_post_list_index; /*006C 006F outbound post list producer consumer index*/
- u_int32_t inbound_doorbell_clear; /*0070 0073*/
- u_int32_t i2o_message_unit_control; /*0074 0077*/
- u_int32_t last_used_message_source_address_low; /*0078 007B*/
- u_int32_t last_used_message_source_address_high; /*007C 007F*/
- u_int32_t pull_mode_data_byte_count[4]; /*0080 008F pull mode data byte count0..count7*/
- u_int32_t message_dest_address_index; /*0090 0093*/
- u_int32_t done_queue_not_empty_int_counter_timer; /*0094 0097*/
- u_int32_t utility_A_int_counter_timer; /*0098 009B*/
- u_int32_t outbound_doorbell; /*009C 009F*/
- u_int32_t outbound_doorbell_clear; /*00A0 00A3*/
- u_int32_t message_source_address_index; /*00A4 00A7 message accelerator source address consumer producer index*/
- u_int32_t message_done_queue_index; /*00A8 00AB message accelerator completion queue consumer producer index*/
- u_int32_t reserved0; /*00AC 00AF*/
- u_int32_t inbound_msgaddr0; /*00B0 00B3 scratchpad0*/
- u_int32_t inbound_msgaddr1; /*00B4 00B7 scratchpad1*/
- u_int32_t outbound_msgaddr0; /*00B8 00BB scratchpad2*/
- u_int32_t outbound_msgaddr1; /*00BC 00BF scratchpad3*/
- u_int32_t inbound_queueport_low; /*00C0 00C3 port64 host inbound queue port low*/
- u_int32_t inbound_queueport_high; /*00C4 00C7 port64 host inbound queue port high*/
- u_int32_t outbound_queueport_low; /*00C8 00CB port64 host outbound queue port low*/
- u_int32_t outbound_queueport_high; /*00CC 00CF port64 host outbound queue port high*/
- u_int32_t iop_inbound_queue_port_low; /*00D0 00D3*/
- u_int32_t iop_inbound_queue_port_high; /*00D4 00D7*/
- u_int32_t iop_outbound_queue_port_low; /*00D8 00DB*/
- u_int32_t iop_outbound_queue_port_high; /*00DC 00DF*/
- u_int32_t message_dest_queue_port_low; /*00E0 00E3 message accelerator destination queue port low*/
- u_int32_t message_dest_queue_port_high; /*00E4 00E7 message accelerator destination queue port high*/
- u_int32_t last_used_message_dest_address_low; /*00E8 00EB last used message accelerator destination address low*/
- u_int32_t last_used_message_dest_address_high; /*00EC 00EF last used message accelerator destination address high*/
- u_int32_t message_done_queue_base_address_low; /*00F0 00F3 message accelerator completion queue base address low*/
- u_int32_t message_done_queue_base_address_high; /*00F4 00F7 message accelerator completion queue base address high*/
- u_int32_t host_diagnostic; /*00F8 00FB*/
- u_int32_t write_sequence; /*00FC 00FF*/
- u_int32_t reserved1[34]; /*0100 0187*/
- u_int32_t reserved2[1950]; /*0188 1FFF*/
- u_int32_t message_wbuffer[32]; /*2000 207F*/
- u_int32_t reserved3[32]; /*2080 20FF*/
- u_int32_t message_rbuffer[32]; /*2100 217F*/
- u_int32_t reserved4[32]; /*2180 21FF*/
- u_int32_t msgcode_rwbuffer[256]; /*2200 23FF*/
+ u_int32_t inbound_doorbell; /*0020 0023*/
+ u_int32_t diagnostic_rw_data; /*0024 0027*/
+ u_int32_t diagnostic_rw_address_low; /*0028 002B*/
+ u_int32_t diagnostic_rw_address_high; /*002C 002F*/
+ u_int32_t host_int_status; /*0030 0033 host interrupt status*/
+ u_int32_t host_int_mask; /*0034 0037 host interrupt mask*/
+ u_int32_t dcr_data; /*0038 003B*/
+ u_int32_t dcr_address; /*003C 003F*/
+ u_int32_t inbound_queueport; /*0040 0043 port32 host inbound queue port*/
+ u_int32_t outbound_queueport; /*0044 0047 port32 host outbound queue port*/
+ u_int32_t hcb_pci_address_low; /*0048 004B*/
+ u_int32_t hcb_pci_address_high; /*004C 004F*/
+ u_int32_t iop_int_status; /*0050 0053*/
+ u_int32_t iop_int_mask; /*0054 0057*/
+ u_int32_t iop_inbound_queue_port; /*0058 005B*/
+ u_int32_t iop_outbound_queue_port; /*005C 005F*/
+ u_int32_t inbound_free_list_index; /*0060 0063 inbound free list producer consumer index*/
+ u_int32_t inbound_post_list_index; /*0064 0067 inbound post list producer consumer index*/
+ u_int32_t outbound_free_list_index; /*0068 006B outbound free list producer consumer index*/
+ u_int32_t outbound_post_list_index; /*006C 006F outbound post list producer consumer index*/
+ u_int32_t inbound_doorbell_clear; /*0070 0073*/
+ u_int32_t i2o_message_unit_control; /*0074 0077*/
+ u_int32_t last_used_message_source_address_low; /*0078 007B*/
+ u_int32_t last_used_message_source_address_high; /*007C 007F*/
+ u_int32_t pull_mode_data_byte_count[4]; /*0080 008F pull mode data byte count0..count7*/
+ u_int32_t message_dest_address_index; /*0090 0093*/
+ u_int32_t done_queue_not_empty_int_counter_timer; /*0094 0097*/
+ u_int32_t utility_A_int_counter_timer; /*0098 009B*/
+ u_int32_t outbound_doorbell; /*009C 009F*/
+ u_int32_t outbound_doorbell_clear; /*00A0 00A3*/
+ u_int32_t message_source_address_index; /*00A4 00A7 message accelerator source address consumer producer index*/
+ u_int32_t message_done_queue_index; /*00A8 00AB message accelerator completion queue consumer producer index*/
+ u_int32_t reserved0; /*00AC 00AF*/
+ u_int32_t inbound_msgaddr0; /*00B0 00B3 scratchpad0*/
+ u_int32_t inbound_msgaddr1; /*00B4 00B7 scratchpad1*/
+ u_int32_t outbound_msgaddr0; /*00B8 00BB scratchpad2*/
+ u_int32_t outbound_msgaddr1; /*00BC 00BF scratchpad3*/
+ u_int32_t inbound_queueport_low; /*00C0 00C3 port64 host inbound queue port low*/
+ u_int32_t inbound_queueport_high; /*00C4 00C7 port64 host inbound queue port high*/
+ u_int32_t outbound_queueport_low; /*00C8 00CB port64 host outbound queue port low*/
+ u_int32_t outbound_queueport_high; /*00CC 00CF port64 host outbound queue port high*/
+ u_int32_t iop_inbound_queue_port_low; /*00D0 00D3*/
+ u_int32_t iop_inbound_queue_port_high; /*00D4 00D7*/
+ u_int32_t iop_outbound_queue_port_low; /*00D8 00DB*/
+ u_int32_t iop_outbound_queue_port_high; /*00DC 00DF*/
+ u_int32_t message_dest_queue_port_low; /*00E0 00E3 message accelerator destination queue port low*/
+ u_int32_t message_dest_queue_port_high; /*00E4 00E7 message accelerator destination queue port high*/
+ u_int32_t last_used_message_dest_address_low; /*00E8 00EB last used message accelerator destination address low*/
+ u_int32_t last_used_message_dest_address_high; /*00EC 00EF last used message accelerator destination address high*/
+ u_int32_t message_done_queue_base_address_low; /*00F0 00F3 message accelerator completion queue base address low*/
+ u_int32_t message_done_queue_base_address_high; /*00F4 00F7 message accelerator completion queue base address high*/
+ u_int32_t host_diagnostic; /*00F8 00FB*/
+ u_int32_t write_sequence; /*00FC 00FF*/
+ u_int32_t reserved1[34]; /*0100 0187*/
+ u_int32_t reserved2[1950]; /*0188 1FFF*/
+ u_int32_t message_wbuffer[32]; /*2000 207F*/
+ u_int32_t reserved3[32]; /*2080 20FF*/
+ u_int32_t message_rbuffer[32]; /*2100 217F*/
+ u_int32_t reserved4[32]; /*2180 21FF*/
+ u_int32_t msgcode_rwbuffer[256]; /*2200 23FF*/
};
/*
*********************************************************************
@@ -616,46 +665,46 @@
struct HBD_MessageUnit {
uint32_t reserved0;
uint32_t chip_id; //0x0004
- uint32_t cpu_mem_config; //0x0008
- uint32_t reserved1[10]; //0x000C
+ uint32_t cpu_mem_config; //0x0008
+ uint32_t reserved1[10]; //0x000C
uint32_t i2o_host_interrupt_mask; //0x0034
- uint32_t reserved2[114]; //0x0038
- uint32_t host_int_status; //0x0200
- uint32_t host_int_enable; //0x0204
- uint32_t reserved3[1]; //0x0208
- uint32_t pcief0_int_enable; //0x020C
- uint32_t reserved4[124]; //0x0210
- uint32_t inbound_msgaddr0; //0x0400
- uint32_t inbound_msgaddr1; //0x0404
- uint32_t reserved5[6]; //0x0408
- uint32_t outbound_msgaddr0; //0x0420
- uint32_t outbound_msgaddr1; //0x0424
- uint32_t reserved6[14]; //0x0428
- uint32_t inbound_doorbell; //0x0460
- uint32_t reserved7[7]; //0x0464
- uint32_t outbound_doorbell; //0x0480
+ uint32_t reserved2[114]; //0x0038
+ uint32_t host_int_status; //0x0200
+ uint32_t host_int_enable; //0x0204
+ uint32_t reserved3[1]; //0x0208
+ uint32_t pcief0_int_enable; //0x020C
+ uint32_t reserved4[124]; //0x0210
+ uint32_t inbound_msgaddr0; //0x0400
+ uint32_t inbound_msgaddr1; //0x0404
+ uint32_t reserved5[6]; //0x0408
+ uint32_t outbound_msgaddr0; //0x0420
+ uint32_t outbound_msgaddr1; //0x0424
+ uint32_t reserved6[14]; //0x0428
+ uint32_t inbound_doorbell; //0x0460
+ uint32_t reserved7[7]; //0x0464
+ uint32_t outbound_doorbell; //0x0480
uint32_t outbound_doorbell_enable; //0x0484
uint32_t reserved8[734]; //0x0488
- uint32_t inboundlist_base_low; //0x1000
- uint32_t inboundlist_base_high; //0x1004
- uint32_t reserved9[4]; //0x1008
+ uint32_t inboundlist_base_low; //0x1000
+ uint32_t inboundlist_base_high; //0x1004
+ uint32_t reserved9[4]; //0x1008
uint32_t inboundlist_write_pointer; //0x1018
uint32_t inboundlist_read_pointer; //0x101C
uint32_t reserved10[16]; //0x1020
- uint32_t outboundlist_base_low; //0x1060
+ uint32_t outboundlist_base_low; //0x1060
uint32_t outboundlist_base_high; //0x1064
- uint32_t reserved11; //0x1068
+ uint32_t reserved11; //0x1068
uint32_t outboundlist_copy_pointer; //0x106C
uint32_t outboundlist_read_pointer; //0x1070 0x1072
- uint32_t reserved12[5]; //0x1074
+ uint32_t reserved12[5]; //0x1074
uint32_t outboundlist_interrupt_cause; //0x1088
uint32_t outboundlist_interrupt_enable; //0x108C
uint32_t reserved13[988]; //0x1090
- uint32_t message_wbuffer[32]; //0x2000
+ uint32_t message_wbuffer[32]; //0x2000
uint32_t reserved14[32]; //0x2080
- uint32_t message_rbuffer[32]; //0x2100
+ uint32_t message_rbuffer[32]; //0x2100
uint32_t reserved15[32]; //0x2180
- uint32_t msgcode_rwbuffer[256]; //0x2200
+ uint32_t msgcode_rwbuffer[256]; //0x2200
};
struct HBD_MessageUnit0 {
@@ -665,7 +714,93 @@
uint16_t doneq_index;
struct HBD_MessageUnit *phbdmu;
};
+/*
+*********************************************************************
+**
+*********************************************************************
+*/
+struct HBE_MessageUnit {
+ u_int32_t iobound_doorbell; /*0000 0003*/
+ u_int32_t write_sequence_3xxx; /*0004 0007*/
+ u_int32_t host_diagnostic_3xxx; /*0008 000B*/
+ u_int32_t posted_outbound_doorbell; /*000C 000F*/
+ u_int32_t master_error_attribute; /*0010 0013*/
+ u_int32_t master_error_address_low; /*0014 0017*/
+ u_int32_t master_error_address_high; /*0018 001B*/
+ u_int32_t hcb_size; /*001C 001F*/
+ u_int32_t inbound_doorbell; /*0020 0023*/
+ u_int32_t diagnostic_rw_data; /*0024 0027*/
+ u_int32_t diagnostic_rw_address_low; /*0028 002B*/
+ u_int32_t diagnostic_rw_address_high; /*002C 002F*/
+ u_int32_t host_int_status; /*0030 0033 host interrupt status*/
+ u_int32_t host_int_mask; /*0034 0037 host interrupt mask*/
+ u_int32_t dcr_data; /*0038 003B*/
+ u_int32_t dcr_address; /*003C 003F*/
+ u_int32_t inbound_queueport; /*0040 0043 port32 host inbound queue port*/
+ u_int32_t outbound_queueport; /*0044 0047 port32 host outbound queue port*/
+ u_int32_t hcb_pci_address_low; /*0048 004B*/
+ u_int32_t hcb_pci_address_high; /*004C 004F*/
+ u_int32_t iop_int_status; /*0050 0053*/
+ u_int32_t iop_int_mask; /*0054 0057*/
+ u_int32_t iop_inbound_queue_port; /*0058 005B*/
+ u_int32_t iop_outbound_queue_port; /*005C 005F*/
+ u_int32_t inbound_free_list_index; /*0060 0063*/
+ u_int32_t inbound_post_list_index; /*0064 0067*/
+ u_int32_t outbound_free_list_index; /*0068 006B*/
+ u_int32_t outbound_post_list_index; /*006C 006F*/
+ u_int32_t inbound_doorbell_clear; /*0070 0073*/
+ u_int32_t i2o_message_unit_control; /*0074 0077*/
+ u_int32_t last_used_message_source_address_low; /*0078 007B*/
+ u_int32_t last_used_message_source_address_high; /*007C 007F*/
+ u_int32_t pull_mode_data_byte_count[4]; /*0080 008F*/
+ u_int32_t message_dest_address_index; /*0090 0093*/
+ u_int32_t done_queue_not_empty_int_counter_timer; /*0094 0097*/
+ u_int32_t utility_A_int_counter_timer; /*0098 009B*/
+ u_int32_t outbound_doorbell; /*009C 009F*/
+ u_int32_t outbound_doorbell_clear; /*00A0 00A3*/
+ u_int32_t message_source_address_index; /*00A4 00A7*/
+ u_int32_t message_done_queue_index; /*00A8 00AB*/
+ u_int32_t reserved0; /*00AC 00AF*/
+ u_int32_t inbound_msgaddr0; /*00B0 00B3 scratchpad0*/
+ u_int32_t inbound_msgaddr1; /*00B4 00B7 scratchpad1*/
+ u_int32_t outbound_msgaddr0; /*00B8 00BB scratchpad2*/
+ u_int32_t outbound_msgaddr1; /*00BC 00BF scratchpad3*/
+ u_int32_t inbound_queueport_low; /*00C0 00C3 port64 host inbound queue port low*/
+ u_int32_t inbound_queueport_high; /*00C4 00C7 port64 host inbound queue port high*/
+ u_int32_t outbound_queueport_low; /*00C8 00CB port64 host outbound queue port low*/
+ u_int32_t outbound_queueport_high; /*00CC 00CF port64 host outbound queue port high*/
+ u_int32_t iop_inbound_queue_port_low; /*00D0 00D3*/
+ u_int32_t iop_inbound_queue_port_high; /*00D4 00D7*/
+ u_int32_t iop_outbound_queue_port_low; /*00D8 00DB*/
+ u_int32_t iop_outbound_queue_port_high; /*00DC 00DF*/
+ u_int32_t message_dest_queue_port_low; /*00E0 00E3*/
+ u_int32_t message_dest_queue_port_high; /*00E4 00E7*/
+ u_int32_t last_used_message_dest_address_low; /*00E8 00EB*/
+ u_int32_t last_used_message_dest_address_high; /*00EC 00EF*/
+ u_int32_t message_done_queue_base_address_low; /*00F0 00F3*/
+ u_int32_t message_done_queue_base_address_high; /*00F4 00F7*/
+ u_int32_t host_diagnostic; /*00F8 00FB*/
+ u_int32_t write_sequence; /*00FC 00FF*/
+ u_int32_t reserved1[46]; /*0100 01B7*/
+ u_int32_t reply_post_producer_index; /*01B8 01BB*/
+ u_int32_t reply_post_consumer_index; /*01BC 01BF*/
+ u_int32_t reserved2[1936]; /*01C0 1FFF*/
+ u_int32_t message_wbuffer[32]; /*2000 207F*/
+ u_int32_t reserved3[32]; /*2080 20FF*/
+ u_int32_t message_rbuffer[32]; /*2100 217F*/
+ u_int32_t reserved4[32]; /*2180 21FF*/
+ u_int32_t msgcode_rwbuffer[256]; /*2200 23FF*/
+};
+typedef struct deliver_completeQ {
+ u_int16_t cmdFlag;
+ u_int16_t cmdSMID;
+ u_int16_t cmdLMID; // reserved (0)
+ u_int16_t cmdFlag2; // reserved (0)
+} DeliverQ, CompletionQ, *pDeliver_Q, *pCompletion_Q;
+
+#define COMPLETION_Q_POOL_SIZE (sizeof(struct deliver_completeQ) * 512 + 128)
+
/*
*********************************************************************
**
@@ -674,10 +809,11 @@
struct MessageUnit_UNION
{
union {
- struct HBA_MessageUnit hbamu;
- struct HBB_MessageUnit hbbmu;
- struct HBC_MessageUnit hbcmu;
- struct HBD_MessageUnit0 hbdmu;
+ struct HBA_MessageUnit hbamu;
+ struct HBB_MessageUnit hbbmu;
+ struct HBC_MessageUnit hbcmu;
+ struct HBD_MessageUnit0 hbdmu;
+ struct HBE_MessageUnit hbemu;
} muu;
};
/*
@@ -685,7 +821,7 @@
** structure for holding DMA address data
*************************************************************
*/
-#define IS_SG64_ADDR 0x01000000 /* bit24 */
+#define IS_SG64_ADDR 0x01000000 /* bit24 */
/*
************************************************************************************************
** ARECA FIRMWARE SPEC
@@ -694,10 +830,10 @@
** (All In/Out is in IOP331's view)
** 1. Message 0 --> InitThread message and retrun code
** 2. Doorbell is used for RS-232 emulation
-** inDoorBell : bit0 -- data in ready (DRIVER DATA WRITE OK)
-** bit1 -- data out has been read (DRIVER DATA READ OK)
-** outDooeBell: bit0 -- data out ready (IOP331 DATA WRITE OK)
-** bit1 -- data in has been read (IOP331 DATA READ OK)
+** inDoorBell : bit0 -- data in ready (DRIVER DATA WRITE OK)
+** bit1 -- data out has been read (DRIVER DATA READ OK)
+** outDooeBell: bit0 -- data out ready (IOP331 DATA WRITE OK)
+** bit1 -- data in has been read (IOP331 DATA READ OK)
** 3. Index Memory Usage
** offset 0xf00 : for RS232 out (request buffer)
** offset 0xe00 : for RS232 in (scratch buffer)
@@ -710,52 +846,52 @@
** 5. PostQ
** All SCSI Command must be sent through postQ:
** (inbound queue port) Request frame must be 32 bytes aligned
-** # bit27--bit31 => flag for post ccb
-** # bit0--bit26 => real address (bit27--bit31) of post arcmsr_cdb
-** bit31 : 0 : 256 bytes frame
-** 1 : 512 bytes frame
-** bit30 : 0 : normal request
-** 1 : BIOS request
-** bit29 : reserved
-** bit28 : reserved
-** bit27 : reserved
+** # bit27--bit31 => flag for post ccb
+** # bit0--bit26 => real address (bit27--bit31) of post arcmsr_cdb
+** bit31 : 0 : 256 bytes frame
+** 1 : 512 bytes frame
+** bit30 : 0 : normal request
+** 1 : BIOS request
+** bit29 : reserved
+** bit28 : reserved
+** bit27 : reserved
** -------------------------------------------------------------------------------
** (outbount queue port) Request reply
-** # bit27--bit31 => flag for reply
-** # bit0--bit26 => real address (bit27--bit31) of reply arcmsr_cdb
-** bit31 : must be 0 (for this type of reply)
-** bit30 : reserved for BIOS handshake
-** bit29 : reserved
-** bit28 : 0 : no error, ignore AdapStatus/DevStatus/SenseData
-** 1 : Error, error code in AdapStatus/DevStatus/SenseData
-** bit27 : reserved
+** # bit27--bit31 => flag for reply
+** # bit0--bit26 => real address (bit27--bit31) of reply arcmsr_cdb
+** bit31 : must be 0 (for this type of reply)
+** bit30 : reserved for BIOS handshake
+** bit29 : reserved
+** bit28 : 0 : no error, ignore AdapStatus/DevStatus/SenseData
+** 1 : Error, error code in AdapStatus/DevStatus/SenseData
+** bit27 : reserved
** 6. BIOS request
** All BIOS request is the same with request from PostQ
** Except :
** Request frame is sent from configuration space
-** offset: 0x78 : Request Frame (bit30 == 1)
-** offset: 0x18 : writeonly to generate IRQ to IOP331
+** offset: 0x78 : Request Frame (bit30 == 1)
+** offset: 0x18 : writeonly to generate IRQ to IOP331
** Completion of request:
-** (bit30 == 0, bit28==err flag)
+** (bit30 == 0, bit28==err flag)
** 7. Definition of SGL entry (structure)
** 8. Message1 Out - Diag Status Code (????)
** 9. Message0 message code :
** 0x00 : NOP
** 0x01 : Get Config ->offset 0xa00 :for outbound message code msgcode_rwbuffer (IOP331 send to driver)
-** Signature 0x87974060(4)
-** Request len 0x00000200(4)
-** numbers of queue 0x00000100(4)
-** SDRAM Size 0x00000100(4)-->256 MB
-** IDE Channels 0x00000008(4)
-** vendor 40 bytes char
-** model 8 bytes char
-** FirmVer 16 bytes char
-** Device Map 16 bytes char
+** Signature 0x87974060(4)
+** Request len 0x00000200(4)
+** numbers of queue 0x00000100(4)
+** SDRAM Size 0x00000100(4)-->256 MB
+** IDE Channels 0x00000008(4)
+** vendor 40 bytes char
+** model 8 bytes char
+** FirmVer 16 bytes char
+** Device Map 16 bytes char
**
** FirmwareVersion DWORD <== Added for checking of new firmware capability
** 0x02 : Set Config ->offset 0xa00 : for inbound message code msgcode_rwbuffer (driver send to IOP331)
-** Signature 0x87974063(4)
-** UPPER32 of Request Frame (4)-->Driver Only
+** Signature 0x87974063(4)
+** UPPER32 of Request Frame (4)-->Driver Only
** 0x03 : Reset (Abort all queued Command)
** 0x04 : Stop Background Activity
** 0x05 : Flush Cache
@@ -762,14 +898,14 @@
** 0x06 : Start Background Activity (re-start if background is halted)
** 0x07 : Check If Host Command Pending (Novell May Need This Function)
** 0x08 : Set controller time ->offset 0xa00 : for inbound message code msgcode_rwbuffer (driver to IOP331)
-** byte 0 : 0xaa <-- signature
-** byte 1 : 0x55 <-- signature
-** byte 2 : year (04)
-** byte 3 : month (1..12)
-** byte 4 : date (1..31)
-** byte 5 : hour (0..23)
-** byte 6 : minute (0..59)
-** byte 7 : second (0..59)
+** byte 0 : 0xaa <-- signature
+** byte 1 : 0x55 <-- signature
+** byte 2 : year (04)
+** byte 3 : month (1..12)
+** byte 4 : date (1..31)
+** byte 5 : hour (0..23)
+** byte 6 : minute (0..59)
+** byte 7 : second (0..59)
** *********************************************************************************
** Porting Of LSI2108/2116 Based PCIE SAS/6G host raid adapter
** ==> Difference from IOP348
@@ -788,19 +924,19 @@
** b. Message0: message code
** 0x00 : NOP
** 0x01 : Get Config ->offset 0xB8 :for outbound message code msgcode_rwbuffer (IOP send to driver)
-** Signature 0x87974060(4)
-** Request len 0x00000200(4)
-** numbers of queue 0x00000100(4)
-** SDRAM Size 0x00000100(4)-->256 MB
-** IDE Channels 0x00000008(4)
-** vendor 40 bytes char
-** model 8 bytes char
-** FirmVer 16 bytes char
-** Device Map 16 bytes char
-** cfgVersion ULONG <== Added for checking of new firmware capability
+** Signature 0x87974060(4)
+** Request len 0x00000200(4)
+** numbers of queue 0x00000100(4)
+** SDRAM Size 0x00000100(4)-->256 MB
+** IDE Channels 0x00000008(4)
+** vendor 40 bytes char
+** model 8 bytes char
+** FirmVer 16 bytes char
+** Device Map 16 bytes char
+** cfgVersion ULONG <== Added for checking of new firmware capability
** 0x02 : Set Config ->offset 0xB0 :for inbound message code msgcode_rwbuffer (driver send to IOP)
-** Signature 0x87974063(4)
-** UPPER32 of Request Frame (4)-->Driver Only
+** Signature 0x87974063(4)
+** UPPER32 of Request Frame (4)-->Driver Only
** 0x03 : Reset (Abort all queued Command)
** 0x04 : Stop Background Activity
** 0x05 : Flush Cache
@@ -807,14 +943,14 @@
** 0x06 : Start Background Activity (re-start if background is halted)
** 0x07 : Check If Host Command Pending (Novell May Need This Function)
** 0x08 : Set controller time ->offset 0xB0 : for inbound message code msgcode_rwbuffer (driver to IOP)
-** byte 0 : 0xaa <-- signature
-** byte 1 : 0x55 <-- signature
-** byte 2 : year (04)
-** byte 3 : month (1..12)
-** byte 4 : date (1..31)
-** byte 5 : hour (0..23)
-** byte 6 : minute (0..59)
-** byte 7 : second (0..59)
+** byte 0 : 0xaa <-- signature
+** byte 1 : 0x55 <-- signature
+** byte 2 : year (04)
+** byte 3 : month (1..12)
+** byte 4 : date (1..31)
+** byte 5 : hour (0..23)
+** byte 6 : minute (0..59)
+** byte 7 : second (0..59)
**
** <2> Doorbell Register is used for RS-232 emulation
** <A> different clear register
@@ -907,21 +1043,21 @@
*/
/* size 8 bytes */
/* 32bit Scatter-Gather list */
-struct SG32ENTRY { /* length bit 24 == 0 */
- u_int32_t length; /* high 8 bit == flag,low 24 bit == length */
- u_int32_t address;
+struct SG32ENTRY { /* length bit 24 == 0 */
+ u_int32_t length; /* high 8 bit == flag,low 24 bit == length */
+ u_int32_t address;
};
/* size 12 bytes */
/* 64bit Scatter-Gather list */
-struct SG64ENTRY { /* length bit 24 == 1 */
- u_int32_t length; /* high 8 bit == flag,low 24 bit == length */
- u_int32_t address;
- u_int32_t addresshigh;
+struct SG64ENTRY { /* length bit 24 == 1 */
+ u_int32_t length; /* high 8 bit == flag,low 24 bit == length */
+ u_int32_t address;
+ u_int32_t addresshigh;
};
struct SGENTRY_UNION {
union {
- struct SG32ENTRY sg32entry; /* 30h Scatter gather address */
- struct SG64ENTRY sg64entry; /* 30h */
+ struct SG32ENTRY sg32entry; /* 30h Scatter gather address */
+ struct SG64ENTRY sg64entry; /* 30h */
}u;
};
/*
@@ -931,14 +1067,14 @@
*/
struct QBUFFER {
u_int32_t data_len;
- u_int8_t data[124];
+ u_int8_t data[124];
};
/*
**********************************
*/
typedef struct PHYS_ADDR64 {
- u_int32_t phyadd_low;
- u_int32_t phyadd_high;
+ u_int32_t phyadd_low;
+ u_int32_t phyadd_high;
}PHYSADDR64;
/*
************************************************************************************************
@@ -958,11 +1094,11 @@
u_int32_t ide_channels; /*4,16-19*/
char vendor[40]; /*5,20-59*/
char model[8]; /*15,60-67*/
- char firmware_ver[16]; /*17,68-83*/
+ char firmware_ver[16]; /*17,68-83*/
char device_map[16]; /*21,84-99*/
- u_int32_t cfgVersion; /*25,100-103 Added for checking of new firmware capability*/
- char cfgSerial[16]; /*26,104-119*/
- u_int32_t cfgPicStatus; /*30,120-123*/
+ u_int32_t cfgVersion; /*25,100-103 Added for checking of new firmware capability*/
+ char cfgSerial[16]; /*26,104-119*/
+ u_int32_t cfgPicStatus; /*30,120-123*/
};
/* (A) For cfgVersion in FIRMWARE_INFO
** if low BYTE (byte#0) >= 3 (version 3)
@@ -1022,8 +1158,8 @@
u_int8_t SenseData[15]; /* 21h output */
union {
- struct SG32ENTRY sg32entry[ARCMSR_MAX_SG_ENTRIES]; /* 30h Scatter gather address */
- struct SG64ENTRY sg64entry[ARCMSR_MAX_SG_ENTRIES]; /* 30h */
+ struct SG32ENTRY sg32entry[ARCMSR_MAX_SG_ENTRIES]; /* 30h Scatter gather address */
+ struct SG64ENTRY sg64entry[ARCMSR_MAX_SG_ENTRIES]; /* 30h */
} u;
};
/* CDB flag */
@@ -1044,9 +1180,9 @@
#define SCSISTAT_COMMAND_TERMINATED 0x22
#define SCSISTAT_QUEUE_FULL 0x28
/* DeviceStatus */
-#define ARCMSR_DEV_SELECT_TIMEOUT 0xF0
-#define ARCMSR_DEV_ABORTED 0xF1
-#define ARCMSR_DEV_INIT_FAIL 0xF2
+#define ARCMSR_DEV_SELECT_TIMEOUT 0xF0
+#define ARCMSR_DEV_ABORTED 0xF1
+#define ARCMSR_DEV_INIT_FAIL 0xF2
/*
*********************************************************************
** Command Control Block (SrbExtension)
@@ -1056,40 +1192,41 @@
*********************************************************************
*/
struct CommandControlBlock {
- struct ARCMSR_CDB arcmsr_cdb; /* 0 -503 (size of CDB=504): arcmsr messenger scsi command descriptor size 504 bytes */
- u_int32_t cdb_phyaddr_low; /* 504-507 */
- u_int32_t arc_cdb_size; /* 508-511 */
+ struct ARCMSR_CDB arcmsr_cdb; /* 0 -503 (size of CDB=504): arcmsr messenger scsi command descriptor size 504 bytes */
+ u_int32_t cdb_phyaddr_low; /* 504-507 */
+ u_int32_t arc_cdb_size; /* 508-511 */
/* ======================512+32 bytes============================ */
- union ccb *pccb; /* 512-515 516-519 pointer of freebsd scsi command */
- struct AdapterControlBlock *acb; /* 520-523 524-527 */
- bus_dmamap_t dm_segs_dmamap; /* 528-531 532-535 */
- u_int16_t srb_flags; /* 536-537 */
- u_int16_t srb_state; /* 538-539 */
- u_int32_t cdb_phyaddr_high; /* 540-543 */
- struct callout ccb_callout;
+ union ccb *pccb; /* 512-515 516-519 pointer of freebsd scsi command */
+ struct AdapterControlBlock *acb; /* 520-523 524-527 */
+ bus_dmamap_t dm_segs_dmamap; /* 528-531 532-535 */
+ u_int16_t srb_flags; /* 536-537 */
+ u_int16_t srb_state; /* 538-539 */
+ u_int32_t cdb_phyaddr_high; /* 540-543 */
+ struct callout ccb_callout;
+ u_int32_t smid;
/* ========================================================== */
};
/* srb_flags */
-#define SRB_FLAG_READ 0x0000
-#define SRB_FLAG_WRITE 0x0001
-#define SRB_FLAG_ERROR 0x0002
-#define SRB_FLAG_FLUSHCACHE 0x0004
+#define SRB_FLAG_READ 0x0000
+#define SRB_FLAG_WRITE 0x0001
+#define SRB_FLAG_ERROR 0x0002
+#define SRB_FLAG_FLUSHCACHE 0x0004
#define SRB_FLAG_MASTER_ABORTED 0x0008
-#define SRB_FLAG_DMAVALID 0x0010
+#define SRB_FLAG_DMAVALID 0x0010
#define SRB_FLAG_DMACONSISTENT 0x0020
-#define SRB_FLAG_DMAWRITE 0x0040
-#define SRB_FLAG_PKTBIND 0x0080
+#define SRB_FLAG_DMAWRITE 0x0040
+#define SRB_FLAG_PKTBIND 0x0080
#define SRB_FLAG_TIMER_START 0x0080
/* srb_state */
-#define ARCMSR_SRB_DONE 0x0000
-#define ARCMSR_SRB_UNBUILD 0x0000
-#define ARCMSR_SRB_TIMEOUT 0x1111
-#define ARCMSR_SRB_RETRY 0x2222
-#define ARCMSR_SRB_START 0x55AA
-#define ARCMSR_SRB_PENDING 0xAA55
-#define ARCMSR_SRB_RESET 0xA5A5
-#define ARCMSR_SRB_ABORTED 0x5A5A
-#define ARCMSR_SRB_ILLEGAL 0xFFFF
+#define ARCMSR_SRB_DONE 0x0000
+#define ARCMSR_SRB_UNBUILD 0x0000
+#define ARCMSR_SRB_TIMEOUT 0x1111
+#define ARCMSR_SRB_RETRY 0x2222
+#define ARCMSR_SRB_START 0x55AA
+#define ARCMSR_SRB_PENDING 0xAA55
+#define ARCMSR_SRB_RESET 0xA5A5
+#define ARCMSR_SRB_ABORTED 0x5A5A
+#define ARCMSR_SRB_ILLEGAL 0xFFFF
#define SRB_SIZE ((sizeof(struct CommandControlBlock)+0x1f) & 0xffe0)
#define ARCMSR_SRBS_POOL_SIZE (SRB_SIZE * ARCMSR_MAX_FREESRB_NUM)
@@ -1099,107 +1236,119 @@
** Adapter Control Block
*********************************************************************
*/
-#define ACB_ADAPTER_TYPE_A 0x00000001 /* hba I IOP */
-#define ACB_ADAPTER_TYPE_B 0x00000002 /* hbb M IOP */
-#define ACB_ADAPTER_TYPE_C 0x00000004 /* hbc L IOP */
-#define ACB_ADAPTER_TYPE_D 0x00000008 /* hbd M IOP */
+#define ACB_ADAPTER_TYPE_A 0x00000000 /* hba I IOP */
+#define ACB_ADAPTER_TYPE_B 0x00000001 /* hbb M IOP */
+#define ACB_ADAPTER_TYPE_C 0x00000002 /* hbc L IOP */
+#define ACB_ADAPTER_TYPE_D 0x00000003 /* hbd M IOP */
+#define ACB_ADAPTER_TYPE_E 0x00000004 /* hbd L IOP */
struct AdapterControlBlock {
- u_int32_t adapter_type; /* adapter A,B..... */
+ u_int32_t adapter_type; /* adapter A,B..... */
- bus_space_tag_t btag[2];
- bus_space_handle_t bhandle[2];
- bus_dma_tag_t parent_dmat;
- bus_dma_tag_t dm_segs_dmat; /* dmat for buffer I/O */
- bus_dma_tag_t srb_dmat; /* dmat for freesrb */
- bus_dmamap_t srb_dmamap;
- device_t pci_dev;
+ bus_space_tag_t btag[2];
+ bus_space_handle_t bhandle[2];
+ bus_dma_tag_t parent_dmat;
+ bus_dma_tag_t dm_segs_dmat; /* dmat for buffer I/O */
+ bus_dma_tag_t srb_dmat; /* dmat for freesrb */
+ bus_dmamap_t srb_dmamap;
+ device_t pci_dev;
#if __FreeBSD_version < 503000
- dev_t ioctl_dev;
+ dev_t ioctl_dev;
#else
- struct cdev *ioctl_dev;
+ struct cdev *ioctl_dev;
#endif
- int pci_unit;
+ int pci_unit;
- struct resource *sys_res_arcmsr[2];
- struct resource *irqres;
- void *ih; /* interrupt handle */
+ struct resource *sys_res_arcmsr[2];
+ struct resource *irqres[ARCMSR_NUM_MSIX_VECTORS];
+ void *ih[ARCMSR_NUM_MSIX_VECTORS]; /* interrupt handle */
+ int irq_id[ARCMSR_NUM_MSIX_VECTORS];
/* Hooks into the CAM XPT */
- struct cam_sim *psim;
- struct cam_path *ppath;
- u_int8_t *uncacheptr;
- unsigned long vir2phy_offset;
+ struct cam_sim *psim;
+ struct cam_path *ppath;
+ u_int8_t *uncacheptr;
+ unsigned long vir2phy_offset;
union {
- unsigned long phyaddr;
+ unsigned long phyaddr;
struct {
- u_int32_t phyadd_low;
- u_int32_t phyadd_high;
+ u_int32_t phyadd_low;
+ u_int32_t phyadd_high;
}B;
- } srb_phyaddr;
+ }srb_phyaddr;
// unsigned long srb_phyaddr;
/* Offset is used in making arc cdb physical to virtual calculations */
- u_int32_t outbound_int_enable;
+ u_int32_t outbound_int_enable;
- struct MessageUnit_UNION *pmu; /* message unit ATU inbound base address0 */
+ struct MessageUnit_UNION *pmu; /* message unit ATU inbound base address0 */
- u_int8_t adapter_index; /* */
- u_int8_t irq;
- u_int16_t acb_flags; /* */
+ u_int8_t adapter_index;
+ u_int8_t irq;
+ u_int16_t acb_flags;
struct CommandControlBlock *psrb_pool[ARCMSR_MAX_FREESRB_NUM]; /* serial srb pointer array */
struct CommandControlBlock *srbworkingQ[ARCMSR_MAX_FREESRB_NUM]; /* working srb pointer array */
- int32_t workingsrb_doneindex; /* done srb array index */
- int32_t workingsrb_startindex; /* start srb array index */
- int32_t srboutstandingcount;
+ int32_t workingsrb_doneindex; /* done srb array index */
+ int32_t workingsrb_startindex; /* start srb array index */
+ int32_t srboutstandingcount;
- u_int8_t rqbuffer[ARCMSR_MAX_QBUFFER]; /* data collection buffer for read from 80331 */
- u_int32_t rqbuf_firstindex; /* first of read buffer */
- u_int32_t rqbuf_lastindex; /* last of read buffer */
+ u_int8_t rqbuffer[ARCMSR_MAX_QBUFFER]; /* data collection buffer for read from 80331 */
+ u_int32_t rqbuf_firstindex; /* first of read buffer */
+ u_int32_t rqbuf_lastindex; /* last of read buffer */
- u_int8_t wqbuffer[ARCMSR_MAX_QBUFFER]; /* data collection buffer for write to 80331 */
- u_int32_t wqbuf_firstindex; /* first of write buffer */
- u_int32_t wqbuf_lastindex; /* last of write buffer */
+ u_int8_t wqbuffer[ARCMSR_MAX_QBUFFER]; /* data collection buffer for write to 80331 */
+ u_int32_t wqbuf_firstindex; /* first of write buffer */
+ u_int32_t wqbuf_lastindex; /* last of write buffer */
- arcmsr_lock_t isr_lock;
- arcmsr_lock_t srb_lock;
- arcmsr_lock_t postDone_lock;
- arcmsr_lock_t qbuffer_lock;
+ arcmsr_lock_t isr_lock;
+ arcmsr_lock_t srb_lock;
+ arcmsr_lock_t postDone_lock;
+ arcmsr_lock_t qbuffer_lock;
- u_int8_t devstate[ARCMSR_MAX_TARGETID][ARCMSR_MAX_TARGETLUN]; /* id0 ..... id15,lun0...lun7 */
- u_int32_t num_resets;
- u_int32_t num_aborts;
- u_int32_t firm_request_len; /*1,04-07*/
- u_int32_t firm_numbers_queue; /*2,08-11*/
- u_int32_t firm_sdram_size; /*3,12-15*/
- u_int32_t firm_ide_channels; /*4,16-19*/
- u_int32_t firm_cfg_version;
- char firm_model[12]; /*15,60-67*/
- char firm_version[20]; /*17,68-83*/
- char device_map[20]; /*21,84-99 */
- struct callout devmap_callout;
- u_int32_t pktRequestCount;
- u_int32_t pktReturnCount;
- u_int32_t vendor_device_id;
- u_int32_t adapter_bus_speed;
+ u_int8_t devstate[ARCMSR_MAX_TARGETID][ARCMSR_MAX_TARGETLUN]; /* id0 ..... id15,lun0...lun7 */
+ u_int32_t num_resets;
+ u_int32_t num_aborts;
+ u_int32_t firm_request_len; /*1,04-07*/
+ u_int32_t firm_numbers_queue; /*2,08-11*/
+ u_int32_t firm_sdram_size; /*3,12-15*/
+ u_int32_t firm_ide_channels; /*4,16-19*/
+ u_int32_t firm_cfg_version;
+ char firm_model[12]; /*15,60-67*/
+ char firm_version[20]; /*17,68-83*/
+ char device_map[20]; /*21,84-99 */
+ struct callout devmap_callout;
+ u_int32_t pktRequestCount;
+ u_int32_t pktReturnCount;
+ u_int32_t vendor_device_id;
+ u_int32_t adapter_bus_speed;
+ u_int32_t maxOutstanding;
+ u_int16_t sub_device_id;
+ u_int32_t doneq_index;
+ u_int32_t in_doorbell;
+ u_int32_t out_doorbell;
+ u_int32_t completionQ_entry;
+ pCompletion_Q pCompletionQ;
+ int msix_vectors;
+ int rid[2];
};/* HW_DEVICE_EXTENSION */
/* acb_flags */
#define ACB_F_SCSISTOPADAPTER 0x0001
-#define ACB_F_MSG_STOP_BGRB 0x0002 /* stop RAID background rebuild */
-#define ACB_F_MSG_START_BGRB 0x0004 /* stop RAID background rebuild */
-#define ACB_F_IOPDATA_OVERFLOW 0x0008 /* iop ioctl data rqbuffer overflow */
-#define ACB_F_MESSAGE_WQBUFFER_CLEARED 0x0010 /* ioctl clear wqbuffer */
-#define ACB_F_MESSAGE_RQBUFFER_CLEARED 0x0020 /* ioctl clear rqbuffer */
+#define ACB_F_MSG_STOP_BGRB 0x0002 /* stop RAID background rebuild */
+#define ACB_F_MSG_START_BGRB 0x0004 /* stop RAID background rebuild */
+#define ACB_F_IOPDATA_OVERFLOW 0x0008 /* iop ioctl data rqbuffer overflow */
+#define ACB_F_MESSAGE_WQBUFFER_CLEARED 0x0010 /* ioctl clear wqbuffer */
+#define ACB_F_MESSAGE_RQBUFFER_CLEARED 0x0020 /* ioctl clear rqbuffer */
#define ACB_F_MESSAGE_WQBUFFER_READ 0x0040
#define ACB_F_BUS_RESET 0x0080
-#define ACB_F_IOP_INITED 0x0100 /* iop init */
-#define ACB_F_MAPFREESRB_FAILD 0x0200 /* arcmsr_map_freesrb faild */
+#define ACB_F_IOP_INITED 0x0100 /* iop init */
+#define ACB_F_MAPFREESRB_FAILD 0x0200 /* arcmsr_map_freesrb faild */
#define ACB_F_CAM_DEV_QFRZN 0x0400
-#define ACB_F_BUS_HANG_ON 0x0800 /* need hardware reset bus */
+#define ACB_F_BUS_HANG_ON 0x0800 /* need hardware reset bus */
#define ACB_F_SRB_FUNCTION_POWER 0x1000
+#define ACB_F_MSIX_ENABLED 0x2000
/* devstate */
-#define ARECA_RAID_GONE 0x55
-#define ARECA_RAID_GOOD 0xaa
+#define ARECA_RAID_GONE 0x55
+#define ARECA_RAID_GOOD 0xaa
/* adapter_bus_speed */
#define ACB_BUS_SPEED_3G 0
#define ACB_BUS_SPEED_6G 1
@@ -1230,17 +1379,17 @@
** Peripheral Device Type definitions
**********************************
*/
-#define SCSI_DASD 0x00 /* Direct-access Device */
+#define SCSI_DASD 0x00 /* Direct-access Device */
#define SCSI_SEQACESS 0x01 /* Sequential-access device */
#define SCSI_PRINTER 0x02 /* Printer device */
#define SCSI_PROCESSOR 0x03 /* Processor device */
#define SCSI_WRITEONCE 0x04 /* Write-once device */
-#define SCSI_CDROM 0x05 /* CD-ROM device */
+#define SCSI_CDROM 0x05 /* CD-ROM device */
#define SCSI_SCANNER 0x06 /* Scanner device */
#define SCSI_OPTICAL 0x07 /* Optical memory device */
#define SCSI_MEDCHGR 0x08 /* Medium changer device */
-#define SCSI_COMM 0x09 /* Communications device */
-#define SCSI_NODEV 0x1F /* Unknown or no device type */
+#define SCSI_COMM 0x09 /* Communications device */
+#define SCSI_NODEV 0x1F /* Unknown or no device type */
/*
************************************************************************************************************
** @@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
Modified: trunk/sys/dev/asmc/asmc.c
===================================================================
--- trunk/sys/dev/asmc/asmc.c 2018-05-28 00:25:20 UTC (rev 10127)
+++ trunk/sys/dev/asmc/asmc.c 2018-05-28 00:27:43 UTC (rev 10128)
@@ -1,3 +1,4 @@
+/* $MidnightBSD$ */
/*-
* Copyright (c) 2007, 2008 Rui Paulo <rpaulo at FreeBSD.org>
* All rights reserved.
@@ -33,7 +34,7 @@
*/
#include <sys/cdefs.h>
-__MBSDID("$MidnightBSD$");
+__FBSDID("$FreeBSD: stable/10/sys/dev/asmc/asmc.c 273847 2014-10-30 08:04:48Z hselasky $");
#include <sys/param.h>
#include <sys/bus.h>
@@ -77,6 +78,7 @@
uint8_t);
static int asmc_fan_count(device_t dev);
static int asmc_fan_getvalue(device_t dev, const char *key, int fan);
+static int asmc_fan_setvalue(device_t dev, const char *key, int fan, int speed);
static int asmc_temp_getvalue(device_t dev, const char *key);
static int asmc_sms_read(device_t, const char *key, int16_t *val);
static void asmc_sms_calibrate(device_t dev);
@@ -94,6 +96,7 @@
/*
* Model functions.
*/
+static int asmc_mb_sysctl_fanid(SYSCTL_HANDLER_ARGS);
static int asmc_mb_sysctl_fanspeed(SYSCTL_HANDLER_ARGS);
static int asmc_mb_sysctl_fansafespeed(SYSCTL_HANDLER_ARGS);
static int asmc_mb_sysctl_fanminspeed(SYSCTL_HANDLER_ARGS);
@@ -115,6 +118,7 @@
int (*smc_sms_x)(SYSCTL_HANDLER_ARGS);
int (*smc_sms_y)(SYSCTL_HANDLER_ARGS);
int (*smc_sms_z)(SYSCTL_HANDLER_ARGS);
+ int (*smc_fan_id)(SYSCTL_HANDLER_ARGS);
int (*smc_fan_speed)(SYSCTL_HANDLER_ARGS);
int (*smc_fan_safespeed)(SYSCTL_HANDLER_ARGS);
int (*smc_fan_minspeed)(SYSCTL_HANDLER_ARGS);
@@ -134,7 +138,7 @@
#define ASMC_SMS_FUNCS asmc_mb_sysctl_sms_x, asmc_mb_sysctl_sms_y, \
asmc_mb_sysctl_sms_z
-#define ASMC_FAN_FUNCS asmc_mb_sysctl_fanspeed, asmc_mb_sysctl_fansafespeed, \
+#define ASMC_FAN_FUNCS asmc_mb_sysctl_fanid, asmc_mb_sysctl_fanspeed, asmc_mb_sysctl_fansafespeed, \
asmc_mb_sysctl_fanminspeed, \
asmc_mb_sysctl_fanmaxspeed, \
asmc_mb_sysctl_fantargetspeed
@@ -196,6 +200,18 @@
ASMC_SMS_FUNCS, ASMC_FAN_FUNCS, ASMC_LIGHT_FUNCS,
ASMC_MBP4_TEMPS, ASMC_MBP4_TEMPNAMES, ASMC_MBP4_TEMPDESCS
},
+
+ {
+ "MacBookPro8,2", "Apple SMC MacBook Pro (early 2011)",
+ ASMC_SMS_FUNCS, ASMC_FAN_FUNCS, ASMC_LIGHT_FUNCS,
+ ASMC_MBP8_TEMPS, ASMC_MBP8_TEMPNAMES, ASMC_MBP8_TEMPDESCS
+ },
+
+ {
+ "MacBookPro11,3", "Apple SMC MacBook Pro Retina Core i7 (2013/2014)",
+ ASMC_SMS_FUNCS, ASMC_FAN_FUNCS, ASMC_LIGHT_FUNCS,
+ ASMC_MBP11_TEMPS, ASMC_MBP11_TEMPNAMES, ASMC_MBP11_TEMPDESCS
+ },
/* The Mac Mini has no SMS */
{
@@ -206,6 +222,15 @@
ASMC_MM_TEMPS, ASMC_MM_TEMPNAMES, ASMC_MM_TEMPDESCS
},
+ /* The Mac Mini 3,1 has no SMS */
+ {
+ "Macmini3,1", "Apple SMC Mac Mini 3,1",
+ NULL, NULL, NULL,
+ ASMC_FAN_FUNCS,
+ NULL, NULL, NULL,
+ ASMC_MM31_TEMPS, ASMC_MM31_TEMPNAMES, ASMC_MM31_TEMPDESCS
+ },
+
/* Idem for the MacPro */
{
"MacPro2", "Apple SMC Mac Pro (8-core)",
@@ -215,12 +240,27 @@
ASMC_MP_TEMPS, ASMC_MP_TEMPNAMES, ASMC_MP_TEMPDESCS
},
+ /* Idem for the MacPro 2010*/
{
+ "MacPro5,1", "Apple SMC MacPro (2010)",
+ NULL, NULL, NULL,
+ ASMC_FAN_FUNCS,
+ NULL, NULL, NULL,
+ ASMC_MP5_TEMPS, ASMC_MP5_TEMPNAMES, ASMC_MP5_TEMPDESCS
+ },
+
+ {
"MacBookAir1,1", "Apple SMC MacBook Air",
ASMC_SMS_FUNCS, ASMC_FAN_FUNCS, NULL, NULL, NULL,
ASMC_MBA_TEMPS, ASMC_MBA_TEMPNAMES, ASMC_MBA_TEMPDESCS
},
+ {
+ "MacBookAir3,1", "Apple SMC MacBook Air Core 2 Duo (Late 2010)",
+ ASMC_SMS_FUNCS, ASMC_FAN_FUNCS, NULL, NULL, NULL,
+ ASMC_MBA3_TEMPS, ASMC_MBA3_TEMPNAMES, ASMC_MBA3_TEMPDESCS
+ },
+
{ NULL, NULL }
};
@@ -352,6 +392,12 @@
SYSCTL_ADD_PROC(sysctlctx,
SYSCTL_CHILDREN(sc->sc_fan_tree[i]),
+ OID_AUTO, "id", CTLTYPE_STRING | CTLFLAG_RD,
+ dev, j, model->smc_fan_id, "I",
+ "Fan ID");
+
+ SYSCTL_ADD_PROC(sysctlctx,
+ SYSCTL_CHILDREN(sc->sc_fan_tree[i]),
OID_AUTO, "speed", CTLTYPE_INT | CTLFLAG_RD,
dev, j, model->smc_fan_speed, "I",
"Fan speed in RPM");
@@ -366,7 +412,7 @@
SYSCTL_ADD_PROC(sysctlctx,
SYSCTL_CHILDREN(sc->sc_fan_tree[i]),
OID_AUTO, "minspeed",
- CTLTYPE_INT | CTLFLAG_RD,
+ CTLTYPE_INT | CTLFLAG_RW,
dev, j, model->smc_fan_minspeed, "I",
"Fan minimum speed in RPM");
@@ -373,7 +419,7 @@
SYSCTL_ADD_PROC(sysctlctx,
SYSCTL_CHILDREN(sc->sc_fan_tree[i]),
OID_AUTO, "maxspeed",
- CTLTYPE_INT | CTLFLAG_RD,
+ CTLTYPE_INT | CTLFLAG_RW,
dev, j, model->smc_fan_maxspeed, "I",
"Fan maximum speed in RPM");
@@ -380,7 +426,7 @@
SYSCTL_ADD_PROC(sysctlctx,
SYSCTL_CHILDREN(sc->sc_fan_tree[i]),
OID_AUTO, "targetspeed",
- CTLTYPE_INT | CTLFLAG_RD,
+ CTLTYPE_INT | CTLFLAG_RW,
dev, j, model->smc_fan_targetspeed, "I",
"Fan target speed in RPM");
}
@@ -632,11 +678,10 @@
if (bootverbose) {
/*
- * XXX: The number of keys is a 32 bit buffer, but
- * right now Apple only uses the last 8 bit.
+ * The number of keys is a 32 bit buffer
*/
asmc_key_read(dev, ASMC_NKEYS, buf, 4);
- device_printf(dev, "number of keys: %d\n", buf[3]);
+ device_printf(dev, "number of keys: %d\n", ntohl(*(uint32_t*)buf));
}
#ifdef DEBUG
@@ -839,7 +884,7 @@
strlcat(buf, buf2, sizeof(buf));
}
strlcat(buf, " \n", sizeof(buf));
- device_printf(dev, buf);
+ device_printf(dev, "%s", buf);
}
return (error);
@@ -897,7 +942,7 @@
{
uint8_t buf[1];
- if (asmc_key_read(dev, ASMC_KEY_FANCOUNT, buf, 1) < 0)
+ if (asmc_key_read(dev, ASMC_KEY_FANCOUNT, buf, sizeof buf) < 0)
return (-1);
return (buf[0]);
@@ -911,7 +956,7 @@
char fankey[5];
snprintf(fankey, sizeof(fankey), key, fan);
- if (asmc_key_read(dev, fankey, buf, 2) < 0)
+ if (asmc_key_read(dev, fankey, buf, sizeof buf) < 0)
return (-1);
speed = (buf[0] << 6) | (buf[1] >> 2);
@@ -918,7 +963,40 @@
return (speed);
}
+static char*
+asmc_fan_getstring(device_t dev, const char *key, int fan)
+{
+ uint8_t buf[16];
+ char fankey[5];
+ char* desc;
+
+ snprintf(fankey, sizeof(fankey), key, fan);
+ if (asmc_key_read(dev, fankey, buf, sizeof buf) < 0)
+ return (NULL);
+ desc = buf+4;
+
+ return (desc);
+}
+
static int
+asmc_fan_setvalue(device_t dev, const char *key, int fan, int speed)
+{
+ uint8_t buf[2];
+ char fankey[5];
+
+ speed *= 4;
+
+ buf[0] = speed>>8;
+ buf[1] = speed;
+
+ snprintf(fankey, sizeof(fankey), key, fan);
+ if (asmc_key_write(dev, fankey, buf, sizeof buf) < 0)
+ return (-1);
+
+ return (0);
+}
+
+static int
asmc_mb_sysctl_fanspeed(SYSCTL_HANDLER_ARGS)
{
device_t dev = (device_t) arg1;
@@ -933,6 +1011,22 @@
}
static int
+asmc_mb_sysctl_fanid(SYSCTL_HANDLER_ARGS)
+{
+ device_t dev = (device_t) arg1;
+ int fan = arg2;
+ int error = true;
+ char* desc;
+
+ desc = asmc_fan_getstring(dev, ASMC_KEY_FANID, fan);
+
+ if (desc != NULL)
+ error = sysctl_handle_string(oidp, desc, 0, req);
+
+ return (error);
+}
+
+static int
asmc_mb_sysctl_fansafespeed(SYSCTL_HANDLER_ARGS)
{
device_t dev = (device_t) arg1;
@@ -958,6 +1052,11 @@
v = asmc_fan_getvalue(dev, ASMC_KEY_FANMINSPEED, fan);
error = sysctl_handle_int(oidp, &v, 0, req);
+ if (error == 0 && req->newptr != NULL) {
+ unsigned int newspeed = v;
+ asmc_fan_setvalue(dev, ASMC_KEY_FANMINSPEED, fan, newspeed);
+ }
+
return (error);
}
@@ -972,6 +1071,11 @@
v = asmc_fan_getvalue(dev, ASMC_KEY_FANMAXSPEED, fan);
error = sysctl_handle_int(oidp, &v, 0, req);
+ if (error == 0 && req->newptr != NULL) {
+ unsigned int newspeed = v;
+ asmc_fan_setvalue(dev, ASMC_KEY_FANMAXSPEED, fan, newspeed);
+ }
+
return (error);
}
@@ -986,6 +1090,11 @@
v = asmc_fan_getvalue(dev, ASMC_KEY_FANTARGETSPEED, fan);
error = sysctl_handle_int(oidp, &v, 0, req);
+ if (error == 0 && req->newptr != NULL) {
+ unsigned int newspeed = v;
+ asmc_fan_setvalue(dev, ASMC_KEY_FANTARGETSPEED, fan, newspeed);
+ }
+
return (error);
}
@@ -1000,7 +1109,7 @@
/*
* Check for invalid temperatures.
*/
- if (asmc_key_read(dev, key, buf, 2) < 0)
+ if (asmc_key_read(dev, key, buf, sizeof buf) < 0)
return (-1);
return (buf[0]);
@@ -1033,7 +1142,7 @@
case 'X':
case 'Y':
case 'Z':
- error = asmc_key_read(dev, key, buf, 2);
+ error = asmc_key_read(dev, key, buf, sizeof buf);
break;
default:
device_printf(dev, "%s called with invalid argument %s\n",
@@ -1175,7 +1284,7 @@
asmc_sms_read(dev, ASMC_KEY_SMS_Z, &val);
v = (int32_t) val;
- error = sysctl_handle_int(oidp, &v, sizeof(v), req);
+ error = sysctl_handle_int(oidp, &v, 0, req);
return (error);
}
@@ -1188,9 +1297,9 @@
int error;
int32_t v;
- asmc_key_read(dev, ASMC_KEY_LIGHTLEFT, buf, 6);
+ asmc_key_read(dev, ASMC_KEY_LIGHTLEFT, buf, sizeof buf);
v = buf[2];
- error = sysctl_handle_int(oidp, &v, sizeof(v), req);
+ error = sysctl_handle_int(oidp, &v, 0, req);
return (error);
}
@@ -1203,9 +1312,9 @@
int error;
int32_t v;
- asmc_key_read(dev, ASMC_KEY_LIGHTRIGHT, buf, 6);
+ asmc_key_read(dev, ASMC_KEY_LIGHTRIGHT, buf, sizeof buf);
v = buf[2];
- error = sysctl_handle_int(oidp, &v, sizeof(v), req);
+ error = sysctl_handle_int(oidp, &v, 0, req);
return (error);
}
@@ -1216,19 +1325,19 @@
device_t dev = (device_t) arg1;
uint8_t buf[2];
int error;
- unsigned int level;
- static int32_t v;
-
- error = sysctl_handle_int(oidp, &v, sizeof(v), req);
+ static unsigned int level;
+ int v;
+
+ v = level;
+ error = sysctl_handle_int(oidp, &v, 0, req);
+
if (error == 0 && req->newptr != NULL) {
- level = *(unsigned int *)req->newptr;
- if (level > 255)
+ if (v < 0 || v > 255)
return (EINVAL);
- v = level;
+ level = v;
buf[0] = level;
buf[1] = 0x00;
- asmc_key_write(dev, ASMC_KEY_LIGHTVALUE, buf, 2);
+ asmc_key_write(dev, ASMC_KEY_LIGHTVALUE, buf, sizeof buf);
}
-
return (error);
}
Modified: trunk/sys/dev/asmc/asmcvar.h
===================================================================
--- trunk/sys/dev/asmc/asmcvar.h 2018-05-28 00:25:20 UTC (rev 10127)
+++ trunk/sys/dev/asmc/asmcvar.h 2018-05-28 00:27:43 UTC (rev 10128)
@@ -1,3 +1,4 @@
+/* $MidnightBSD$ */
/*-
* Copyright (c) 2007, 2008 Rui Paulo <rpaulo at FreeBSD.org>
* All rights reserved.
@@ -23,11 +24,11 @@
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
- * $MidnightBSD$
+ * $FreeBSD: stable/10/sys/dev/asmc/asmcvar.h 330961 2018-03-15 00:44:34Z emaste $
*
*/
-#define ASMC_MAXFANS 2
+#define ASMC_MAXFANS 6
struct asmc_softc {
device_t sc_dev;
@@ -83,6 +84,7 @@
*/
#define ASMC_KEY_FANCOUNT "FNum" /* RO; 1 byte */
#define ASMC_KEY_FANMANUAL "FS! " /* RW; 2 bytes */
+#define ASMC_KEY_FANID "F%dID" /* RO; 16 bytes */
#define ASMC_KEY_FANSPEED "F%dAc" /* RO; 2 bytes */
#define ASMC_KEY_FANMINSPEED "F%dMn" /* RO; 2 bytes */
#define ASMC_KEY_FANMAXSPEED "F%dMx" /* RO; 2 bytes */
@@ -132,7 +134,7 @@
*
*/
/* maximum array size for temperatures including the last NULL */
-#define ASMC_TEMP_MAX 36
+#define ASMC_TEMP_MAX 80
#define ASMC_MB_TEMPS { "TB0T", "TN0P", "TN1P", "Th0H", "Th1H", \
"TM0P", NULL }
#define ASMC_MB_TEMPNAMES { "enclosure", "northbridge1", \
@@ -175,11 +177,81 @@
"Unknown", "Unknown", \
"Wireless Module", }
+#define ASMC_MBP8_TEMPS { "TB0T", "TB1T", "TB2T", "TC0C", "TC0D", \
+ "TC0E", "TC0F", "TC0P", "TC1C", "TC2C", \
+ "TC3C", "TC4C", "TCFC", "TCGC", "TCSA", \
+ "TCTD", "TG0D", "TG0P", "THSP", "TM0S", \
+ "TMBS", "TP0P", "TPCD", "TW0P", "Th1H", \
+ "Th2H", "Tm0P", "Ts0P", "Ts0S", NULL }
+
+#define ASMC_MBP8_TEMPNAMES { "enclosure", "TB1T", "TB2T", "TC0C", "TC0D", \
+ "TC0E", "TC0F", "TC0P", "TC1C", "TC2C", \
+ "TC3C", "TC4C", "TCFC", "TCGC", "TCSA", \
+ "TCTD", "graphics", "TG0P", "THSP", "TM0S", \
+ "TMBS", "TP0P", "TPCD", "wireless", "Th1H", \
+ "Th2H", "memory", "Ts0P", "Ts0S" }
+
+#define ASMC_MBP8_TEMPDESCS { "Enclosure Bottomside", "TB1T", "TB2T", "TC0C", "TC0D", \
+ "TC0E", "TC0F", "TC0P", "TC1C", "TC2C", \
+ "TC3C", "TC4C", "TCFC", "TCGC", "TCSA", \
+ "TCTD", "TG0D", "TG0P", "THSP", "TM0S", \
+ "TMBS", "TP0P", "TPCD", "TW0P", "Th1H", \
+ "Th2H", "Tm0P", "Ts0P", "Ts0S" }
+
+#define ASMC_MBP11_TEMPS { "TB0T", "TB1T", "TB2T", "TBXT", "TC0E", \
+ "TC0F", "TC0P", "TC1C", "TC2C", "TC3C", \
+ "TC4C", "TCFC", "TCGC", "TCSA", "TCTD", \
+ "TCXC", "TG0D", "TG0P", "TG1D", "TG1F", \
+ "TG1d", "TH0A", "TH0B", "TH0F", "TH0R", \
+ "TH0V", "TH0a", "TH0b", "TH0c", "TM0P", \
+ "TM0S", "TP0P", "TPCD", "TW0P", "Ta0P", \
+ "TaSP", "Th1H", "Th2H", "Ts0P", "Ts0S", \
+ "Ts1S", NULL }
+
+#define ASMC_MBP11_TEMPNAMES { "TB0T", "TB1T", "TB2T", "TBXT", "TC0E", \
+ "TC0F", "TC0P", "TC1C", "TC2C", "TC3C", \
+ "TC4C", "TCFC", "TCGC", "TCSA", "TCTD", \
+ "TCXC", "TG0D", "TG0P", "TG1D", "TG1F", \
+ "TG1d", "TH0A", "TH0B", "TH0F", "TH0R", \
+ "TH0V", "TH0a", "TH0b", "TH0c", "TM0P", \
+ "TM0S", "TP0P", "TPCD", "TW0P", "Ta0P", \
+ "TaSP", "Th1H", "Th2H", "Ts0P", "Ts0S", \
+ "Ts1S" }
+
+#define ASMC_MBP11_TEMPDESCS { "TB0T", "TB1T", "TB2T", "TBXT", "TC0E", \
+ "TC0F", "TC0P", "TC1C", "TC2C", "TC3C", \
+ "TC4C", "TCFC", "TCGC", "TCSA", "TCTD", \
+ "TCXC", "TG0D", "TG0P", "TG1D", "TG1F", \
+ "TG1d", "TH0A", "TH0B", "TH0F", "TH0R", \
+ "TH0V", "TH0a", "TH0b", "TH0c", "TM0P", \
+ "TM0S", "TP0P", "TPCD", "TW0P", "Ta0P", \
+ "TaSP", "Th1H", "Th2H", "Ts0P", "Ts0S", \
+ "Ts1S" }
+
#define ASMC_MM_TEMPS { "TN0P", "TN1P", NULL }
#define ASMC_MM_TEMPNAMES { "northbridge1", "northbridge2" }
#define ASMC_MM_TEMPDESCS { "Northbridge Point 1", \
"Northbridge Point 2" }
+#define ASMC_MM31_TEMPS { "TC0D", "TC0H", \
+ "TC0P", "TH0P", \
+ "TN0D", "TN0P", \
+ "TW0P", NULL }
+
+#define ASMC_MM31_TEMPNAMES { "cpu0_die", "cpu0_heatsink", \
+ "cpu0_proximity", "hdd_bay", \
+ "northbridge_die", \
+ "northbridge_proximity", \
+ "wireless_proximity", }
+
+#define ASMC_MM31_TEMPDESCS { "CPU0 Die Core Temperature", \
+ "CPU0 Heatsink Temperature", \
+ "CPU0 Proximity Temperature", \
+ "HDD Bay Temperature", \
+ "Northbridge Die Core Temperature", \
+ "Northbridge Proximity Temperature", \
+ "Wireless Module Proximity Temperature", }
+
#define ASMC_MP_TEMPS { "TA0P", "TCAG", "TCAH", "TCBG", "TCBH", \
"TC0C", "TC0D", "TC0P", "TC1C", "TC1D", \
"TC2C", "TC2D", "TC3C", "TC3D", "THTG", \
@@ -195,8 +267,7 @@
"TH0P", "TH1P", "TH2P", "TH3P", "TMAP", \
"TMAS", "TMBS", "TM0P", "TM0S", "TM1P", \
"TM1S", "TM2P", "TM2S", "TM3S", "TM8P", \
- "TM8S", "TM9P", "TM9S", "TN0H", "TS0C", \
- NULL }
+ "TM8S", "TM9P", "TM9S", "TN0H", "TS0C", }
#define ASMC_MP_TEMPDESCS { "TA0P", "TCAG", "TCAH", "TCBG", "TCBH", \
"TC0C", "TC0D", "TC0P", "TC1C", "TC1D", \
@@ -204,9 +275,66 @@
"TH0P", "TH1P", "TH2P", "TH3P", "TMAP", \
"TMAS", "TMBS", "TM0P", "TM0S", "TM1P", \
"TM1S", "TM2P", "TM2S", "TM3S", "TM8P", \
- "TM8S", "TM9P", "TM9S", "TN0H", "TS0C", \
+ "TM8S", "TM9P", "TM9S", "TN0H", "TS0C", }
+
+#define ASMC_MP5_TEMPS { "TA0P", "TCAC", "TCAD", "TCAG", "TCAH", \
+ "TCAS", "TCBC", "TCBD", "TCBG", "TCBH", \
+ "TCBS", "TH1F", "TH1P", "TH1V", "TH2F", \
+ "TH2P", "TH2V", "TH3F", "TH3P", "TH3V", \
+ "TH4F", "TH4P", "TH4V", "THPS", "THTG", \
+ "TM1P", "TM2P", "TM2V", "TM3P", "TM3V", \
+ "TM4P", "TM5P", "TM6P", "TM6V", "TM7P", \
+ "TM7V", "TM8P", "TM8V", "TM9V", "TMA1", \
+ "TMA2", "TMA3", "TMA4", "TMB1", "TMB2", \
+ "TMB3", "TMB4", "TMHS", "TMLS", "TMPS", \
+ "TMPV", "TMTG", "TN0D", "TN0H", "TNTG", \
+ "Te1F", "Te1P", "Te1S", "Te2F", "Te2S", \
+ "Te3F", "Te3S", "Te4F", "Te4S", "Te5F", \
+ "Te5S", "TeGG", "TeGP", "TeRG", "TeRP", \
+ "TeRV", "Tp0C", "Tp1C", "TpPS", "TpTG", \
NULL }
+#define ASMC_MP5_TEMPNAMES { "ambient", "TCAC", "TCAD", "TCAG", "TCAH", \
+ "TCAS", "TCBC", "TCBD", "TCBG", "TCBH", \
+ "TCBS", "TH1F", "TH1P", "TH1V", "TH2F", \
+ "TH2P", "TH2V", "TH3F", "TH3P", "TH3V", \
+ "TH4F", "TH4P", "TH4V", "THPS", "THTG", \
+ "TM1P", "TM2P", "TM2V", "TM3P", "TM3V", \
+ "TM4P", "TM5P", "TM6P", "TM6V", "TM7P", \
+ "TM7V", "TM8P", "TM8V", "TM9V", "ram_a1", \
+ "ram_a2", "ram_a3", "ram_a4", "ram_b1", "ram_b2", \
+ "ram_b3", "ram_b4", "TMHS", "TMLS", "TMPS", \
+ "TMPV", "TMTG", "TN0D", "TN0H", "TNTG", \
+ "Te1F", "Te1P", "Te1S", "Te2F", "Te2S", \
+ "Te3F", "Te3S", "Te4F", "Te4S", "Te5F", \
+ "Te5S", "TeGG", "TeGP", "TeRG", "TeRP", \
+ "TeRV", "Tp0C", "Tp1C", "TpPS", "TpTG", }
+
+#define ASMC_MP5_TEMPDESCS { "TA0P", "TCAC", "TCAD", "TCAG", "TCAH", \
+ "TCAS", "TCBC", "TCBD", "TCBG", "TCBH", \
+ "TCBS", "TH1F", "TH1P", "TH1V", "TH2F", \
+ "TH2P", "TH2V", "TH3F", "TH3P", "TH3V", \
+ "TH4F", "TH4P", "TH4V", "THPS", "THTG", \
+ "TM1P", "TM2P", "TM2V", "TM3P", "TM3V", \
+ "TM4P", "TM5P", "TM6P", "TM6V", "TM7P", \
+ "TM7V", "TM8P", "TM8V", "TM9V", "TMA1", \
+ "TMA2", "TMA3", "TMA4", "TMB1", "TMB2", \
+ "TMB3", "TMB4", "TMHS", "TMLS", "TMPS", \
+ "TMPV", "TMTG", "TN0D", "TN0H", "TNTG", \
+ "Te1F", "Te1P", "Te1S", "Te2F", "Te2S", \
+ "Te3F", "Te3S", "Te4F", "Te4S", "Te5F", \
+ "Te5S", "TeGG", "TeGP", "TeRG", "TeRP", \
+ "TeRV", "Tp0C", "Tp1C", "TpPS", "TpTG", }
+
#define ASMC_MBA_TEMPS { "TB0T", NULL }
#define ASMC_MBA_TEMPNAMES { "enclosure" }
#define ASMC_MBA_TEMPDESCS { "Enclosure Bottom" }
+
+#define ASMC_MBA3_TEMPS { "TB0T", "TB1T", "TB2T", \
+ "TC0D", "TC0E", "TC0P", NULL }
+
+#define ASMC_MBA3_TEMPNAMES { "enclosure", "TB1T", "TB2T", \
+ "TC0D", "TC0E", "TC0P" }
+
+#define ASMC_MBA3_TEMPDESCS { "Enclosure Bottom", "TB1T", "TB2T", \
+ "TC0D", "TC0E", "TC0P" }
Modified: trunk/sys/dev/asr/asr.c
===================================================================
--- trunk/sys/dev/asr/asr.c 2018-05-28 00:25:20 UTC (rev 10127)
+++ trunk/sys/dev/asr/asr.c 2018-05-28 00:27:43 UTC (rev 10128)
@@ -1,4 +1,4 @@
-/* $MidnightBSD: src/sys/dev/asr/asr.c,v 1.3 2012/04/12 01:48:58 laffer1 Exp $ */
+/* $MidnightBSD$ */
/*-
* Copyright (c) 1996-2000 Distributed Processing Technology Corporation
* Copyright (c) 2000-2001 Adaptec Corporation
@@ -161,7 +161,7 @@
#include <dev/asr/sys_info.h>
-__FBSDID("$FreeBSD$");
+__FBSDID("$FreeBSD: stable/10/sys/dev/asr/asr.c 275982 2014-12-21 03:06:11Z smh $");
#define ASR_VERSION 1
#define ASR_REVISION '1'
@@ -385,7 +385,6 @@
static STAILQ_HEAD(, Asr_softc) Asr_softc_list =
STAILQ_HEAD_INITIALIZER(Asr_softc_list);
-
/*
* Prototypes of the routines we have in this object.
*/
@@ -408,6 +407,25 @@
static void asr_poll(struct cam_sim *sim);
static int ASR_queue(Asr_softc_t *sc, PI2O_MESSAGE_FRAME Message);
+static __inline void
+set_ccb_timeout_ch(union asr_ccb *ccb)
+{
+ struct callout_handle ch;
+
+ ch = timeout(asr_timeout, (caddr_t)ccb,
+ (int)((u_int64_t)(ccb->ccb_h.timeout) * (u_int32_t)hz / 1000));
+ ccb->ccb_h.sim_priv.entries[0].ptr = ch.callout;
+}
+
+static __inline struct callout_handle
+get_ccb_timeout_ch(union asr_ccb *ccb)
+{
+ struct callout_handle ch;
+
+ ch.callout = ccb->ccb_h.sim_priv.entries[0].ptr;
+ return ch;
+}
+
/*
* Here is the auto-probe structure used to nest our tests appropriately
* during the startup phase of the operating system.
@@ -798,8 +816,7 @@
*/
ccb->ccb_h.timeout = 6 * 60 * 1000;
}
- ccb->ccb_h.timeout_ch = timeout(asr_timeout, (caddr_t)ccb,
- (ccb->ccb_h.timeout * hz) / 1000);
+ set_ccb_timeout_ch(ccb);
}
splx(s);
} /* ASR_ccbAdd */
@@ -813,7 +830,7 @@
int s;
s = splcam();
- untimeout(asr_timeout, (caddr_t)ccb, ccb->ccb_h.timeout_ch);
+ untimeout(asr_timeout, (caddr_t)ccb, get_ccb_timeout_ch(ccb));
LIST_REMOVE(&(ccb->ccb_h), sim_links.le);
splx(s);
} /* ASR_ccbRemove */
@@ -1323,9 +1340,7 @@
cam_sim_unit(xpt_path_sim(ccb->ccb_h.path)), s);
if (ASR_reset (sc) == ENXIO) {
/* Try again later */
- ccb->ccb_h.timeout_ch = timeout(asr_timeout,
- (caddr_t)ccb,
- (ccb->ccb_h.timeout * hz) / 1000);
+ set_ccb_timeout_ch(ccb);
}
return;
}
@@ -1339,9 +1354,7 @@
if ((ccb->ccb_h.status & CAM_STATUS_MASK) == CAM_CMD_TIMEOUT) {
debug_asr_printf (" AGAIN\nreinitializing adapter\n");
if (ASR_reset (sc) == ENXIO) {
- ccb->ccb_h.timeout_ch = timeout(asr_timeout,
- (caddr_t)ccb,
- (ccb->ccb_h.timeout * hz) / 1000);
+ set_ccb_timeout_ch(ccb);
}
splx(s);
return;
@@ -1350,8 +1363,7 @@
/* If the BUS reset does not take, then an adapter reset is next! */
ccb->ccb_h.status &= ~CAM_STATUS_MASK;
ccb->ccb_h.status |= CAM_CMD_TIMEOUT;
- ccb->ccb_h.timeout_ch = timeout(asr_timeout, (caddr_t)ccb,
- (ccb->ccb_h.timeout * hz) / 1000);
+ set_ccb_timeout_ch(ccb);
ASR_resetBus (sc, cam_sim_bus(xpt_path_sim(ccb->ccb_h.path)));
xpt_async (AC_BUS_RESET, ccb->ccb_h.path, NULL);
splx(s);
@@ -2429,9 +2441,7 @@
return(ENXIO);
}
/* Enable if not formerly enabled */
- pci_write_config(dev, PCIR_COMMAND,
- pci_read_config(dev, PCIR_COMMAND, sizeof(char)) |
- PCIM_CMD_MEMEN | PCIM_CMD_BUSMASTEREN, sizeof(char));
+ pci_enable_busmaster(dev);
sc->ha_pciBusNum = pci_get_bus(dev);
sc->ha_pciDeviceNum = (pci_get_slot(dev) << 3) | pci_get_function(dev);
Modified: trunk/sys/dev/asr/dptalign.h
===================================================================
--- trunk/sys/dev/asr/dptalign.h 2018-05-28 00:25:20 UTC (rev 10127)
+++ trunk/sys/dev/asr/dptalign.h 2018-05-28 00:27:43 UTC (rev 10128)
@@ -1,4 +1,4 @@
-/* $MidnightBSD: src/sys/dev/asr/dptalign.h,v 1.2 2008/12/02 02:24:33 laffer1 Exp $ */
+/* $MidnightBSD$ */
/*-
* Copyright (c) 1996-1999 Distributed Processing Technology Corporation
* All rights reserved.
@@ -21,7 +21,7 @@
*
* DPT Alignment Description File
*
- * $FreeBSD$
+ * $FreeBSD: stable/10/sys/dev/asr/dptalign.h 139749 2005-01-06 01:43:34Z imp $
*/
#if (!defined(__DPTALIGN_H))
#define __DPTALIGN_H
Modified: trunk/sys/dev/asr/dptsig.h
===================================================================
--- trunk/sys/dev/asr/dptsig.h 2018-05-28 00:25:20 UTC (rev 10127)
+++ trunk/sys/dev/asr/dptsig.h 2018-05-28 00:27:43 UTC (rev 10128)
@@ -1,4 +1,4 @@
-/* $MidnightBSD: src/sys/dev/asr/dptsig.h,v 1.2 2008/12/02 02:24:33 laffer1 Exp $ */
+/* $MidnightBSD$ */
/*-
* Copyright (c) 1996-2000 Distributed Processing Technology Corporation
* Copyright (c) 2000-2001 Adaptec Corporation.
@@ -20,7 +20,7 @@
* arising in any way out of the use of this driver software, even if advised
* of the possibility of such damage.
*
- * $FreeBSD$
+ * $FreeBSD: stable/10/sys/dev/asr/dptsig.h 153084 2005-12-04 10:06:06Z ru $
*/
#ifndef __DPTSIG_H_
Modified: trunk/sys/dev/asr/i2oadptr.h
===================================================================
--- trunk/sys/dev/asr/i2oadptr.h 2018-05-28 00:25:20 UTC (rev 10127)
+++ trunk/sys/dev/asr/i2oadptr.h 2018-05-28 00:27:43 UTC (rev 10128)
@@ -1,4 +1,4 @@
-/* $MidnightBSD: src/sys/dev/asr/i2oadptr.h,v 1.2 2008/12/02 02:24:33 laffer1 Exp $ */
+/* $MidnightBSD$ */
/*-
****************************************************************
* Copyright (c) 1996-2000 Distributed Processing Technology Corporation
@@ -78,7 +78,7 @@
* Developer of the I2O SIG, sign up at the Web site or call 415.750.8352
* (United States).
*
- * $FreeBSD$
+ * $FreeBSD: stable/10/sys/dev/asr/i2oadptr.h 139749 2005-01-06 01:43:34Z imp $
*
****************************************************************/
Modified: trunk/sys/dev/asr/i2obscsi.h
===================================================================
--- trunk/sys/dev/asr/i2obscsi.h 2018-05-28 00:25:20 UTC (rev 10127)
+++ trunk/sys/dev/asr/i2obscsi.h 2018-05-28 00:27:43 UTC (rev 10128)
@@ -1,4 +1,4 @@
-/* $MidnightBSD: src/sys/dev/asr/i2obscsi.h,v 1.2 2008/12/02 02:24:33 laffer1 Exp $ */
+/* $MidnightBSD$ */
/*-
****************************************************************
* Copyright (c) 1996-2000 Distributed Processing Technology Corporation
@@ -78,7 +78,7 @@
* Developer of the I2O SIG, sign up at the Web site or call 415.750.8352
* (United States).
*
- * $FreeBSD$
+ * $FreeBSD: stable/10/sys/dev/asr/i2obscsi.h 139749 2005-01-06 01:43:34Z imp $
*
****************************************************************/
Modified: trunk/sys/dev/asr/i2odep.h
===================================================================
--- trunk/sys/dev/asr/i2odep.h 2018-05-28 00:25:20 UTC (rev 10127)
+++ trunk/sys/dev/asr/i2odep.h 2018-05-28 00:27:43 UTC (rev 10128)
@@ -1,4 +1,4 @@
-/* $MidnightBSD: src/sys/dev/asr/i2odep.h,v 1.2 2008/12/02 02:24:33 laffer1 Exp $ */
+/* $MidnightBSD$ */
/*-
****************************************************************************
*
@@ -47,7 +47,7 @@
* become a "Registered Developer" of the I2O SIG. This can be done by calling
* 415-750-8352 in the US, or via http://www.i2osig.org.
*
- * $FreeBSD$
+ * $FreeBSD: stable/10/sys/dev/asr/i2odep.h 155278 2006-02-04 08:01:49Z scottl $
*
**************************************************************************/
Modified: trunk/sys/dev/asr/i2odpt.h
===================================================================
--- trunk/sys/dev/asr/i2odpt.h 2018-05-28 00:25:20 UTC (rev 10127)
+++ trunk/sys/dev/asr/i2odpt.h 2018-05-28 00:27:43 UTC (rev 10128)
@@ -1,4 +1,4 @@
-/* $MidnightBSD: src/sys/dev/asr/i2odpt.h,v 1.2 2008/12/02 02:24:33 laffer1 Exp $ */
+/* $MidnightBSD$ */
/*-
*****************************************************************
* Copyright (c) 1996-2000 Distributed Processing Technology Corporation
@@ -5,7 +5,7 @@
* Copyright (c) 2000 Adaptec Corporation.
* All rights reserved.
*
- * $FreeBSD$
+ * $FreeBSD: stable/10/sys/dev/asr/i2odpt.h 139749 2005-01-06 01:43:34Z imp $
*
****************************************************************/
Modified: trunk/sys/dev/asr/i2oexec.h
===================================================================
--- trunk/sys/dev/asr/i2oexec.h 2018-05-28 00:25:20 UTC (rev 10127)
+++ trunk/sys/dev/asr/i2oexec.h 2018-05-28 00:27:43 UTC (rev 10128)
@@ -1,4 +1,4 @@
-/* $MidnightBSD: src/sys/dev/asr/i2oexec.h,v 1.2 2008/12/02 02:24:33 laffer1 Exp $ */
+/* $MidnightBSD$ */
/*-
****************************************************************
* Copyright (c) 1996-2000 Distributed Processing Technology Corporation
@@ -78,7 +78,7 @@
* Developer of the I2O SIG, sign up at the Web site or call 415.750.8352
* (United States).
*
- * $FreeBSD$
+ * $FreeBSD: stable/10/sys/dev/asr/i2oexec.h 139749 2005-01-06 01:43:34Z imp $
*
****************************************************************/
Modified: trunk/sys/dev/asr/i2omsg.h
===================================================================
--- trunk/sys/dev/asr/i2omsg.h 2018-05-28 00:25:20 UTC (rev 10127)
+++ trunk/sys/dev/asr/i2omsg.h 2018-05-28 00:27:43 UTC (rev 10128)
@@ -1,4 +1,4 @@
-/* $MidnightBSD: src/sys/dev/asr/i2omsg.h,v 1.2 2008/12/02 02:24:33 laffer1 Exp $ */
+/* $MidnightBSD$ */
/*-
****************************************************************
* Copyright (c) 1996-2000 Distributed Processing Technology Corporation
@@ -78,7 +78,7 @@
* Developer of the I2O SIG, sign up at the Web site or call 415.750.8352
* (United States).
*
- * $FreeBSD$
+ * $FreeBSD: stable/10/sys/dev/asr/i2omsg.h 218909 2011-02-21 09:01:34Z brucec $
*
****************************************************************/
Modified: trunk/sys/dev/asr/i2otypes.h
===================================================================
--- trunk/sys/dev/asr/i2otypes.h 2018-05-28 00:25:20 UTC (rev 10127)
+++ trunk/sys/dev/asr/i2otypes.h 2018-05-28 00:27:43 UTC (rev 10128)
@@ -1,4 +1,4 @@
-/* $MidnightBSD: src/sys/dev/asr/i2otypes.h,v 1.2 2008/12/02 02:24:33 laffer1 Exp $ */
+/* $MidnightBSD$ */
/*-
****************************************************************
* Copyright (c) 1996-2000 Distributed Processing Technology Corporation
@@ -78,7 +78,7 @@
* Developer of the I2O SIG, sign up at the Web site or call 415.750.8352
* (United States).
*
- * $FreeBSD$
+ * $FreeBSD: stable/10/sys/dev/asr/i2otypes.h 139749 2005-01-06 01:43:34Z imp $
*
****************************************************************/
Modified: trunk/sys/dev/asr/i2outil.h
===================================================================
--- trunk/sys/dev/asr/i2outil.h 2018-05-28 00:25:20 UTC (rev 10127)
+++ trunk/sys/dev/asr/i2outil.h 2018-05-28 00:27:43 UTC (rev 10128)
@@ -1,4 +1,4 @@
-/* $MidnightBSD: src/sys/dev/asr/i2outil.h,v 1.2 2008/12/02 02:24:33 laffer1 Exp $ */
+/* $MidnightBSD$ */
/*-
****************************************************************
* Copyright (c) 1996-2000 Distributed Processing Technology Corporation
@@ -78,7 +78,7 @@
* Developer of the I2O SIG, sign up at the Web site or call 415.750.8352
* (United States).
*
- * $FreeBSD$
+ * $FreeBSD: stable/10/sys/dev/asr/i2outil.h 139749 2005-01-06 01:43:34Z imp $
*
****************************************************************/
Modified: trunk/sys/dev/asr/osd_defs.h
===================================================================
--- trunk/sys/dev/asr/osd_defs.h 2018-05-28 00:25:20 UTC (rev 10127)
+++ trunk/sys/dev/asr/osd_defs.h 2018-05-28 00:27:43 UTC (rev 10128)
@@ -1,4 +1,4 @@
-/* $MidnightBSD: src/sys/dev/asr/osd_defs.h,v 1.2 2008/12/02 02:24:33 laffer1 Exp $ */
+/* $MidnightBSD$ */
/*-
* Copyright (c) 1996-1999 Distributed Processing Technology Corporation
* All rights reserved.
@@ -19,7 +19,7 @@
* arising in any way out of the use of this driver software, even if advised
* of the possibility of such damage.
*
- * $FreeBSD$
+ * $FreeBSD: stable/10/sys/dev/asr/osd_defs.h 139749 2005-01-06 01:43:34Z imp $
*/
#ifndef _OSD_DEFS_H
Modified: trunk/sys/dev/asr/osd_unix.h
===================================================================
--- trunk/sys/dev/asr/osd_unix.h 2018-05-28 00:25:20 UTC (rev 10127)
+++ trunk/sys/dev/asr/osd_unix.h 2018-05-28 00:27:43 UTC (rev 10128)
@@ -1,4 +1,4 @@
-/* $MidnightBSD: src/sys/dev/asr/osd_unix.h,v 1.2 2008/12/02 02:24:33 laffer1 Exp $ */
+/* $MidnightBSD$ */
/*-
* Copyright (c) 1996-1999 Distributed Processing Technology Corporation
* All rights reserved.
@@ -19,7 +19,7 @@
* arising in any way out of the use of this driver software, even if advised
* of the possibility of such damage.
*
- * $FreeBSD$
+ * $FreeBSD: stable/10/sys/dev/asr/osd_unix.h 139749 2005-01-06 01:43:34Z imp $
*/
#ifndef __OSD_UNIX_H
Modified: trunk/sys/dev/asr/osd_util.h
===================================================================
--- trunk/sys/dev/asr/osd_util.h 2018-05-28 00:25:20 UTC (rev 10127)
+++ trunk/sys/dev/asr/osd_util.h 2018-05-28 00:27:43 UTC (rev 10128)
@@ -1,4 +1,4 @@
-/* $MidnightBSD: src/sys/dev/asr/osd_util.h,v 1.2 2008/12/02 02:24:33 laffer1 Exp $ */
+/* $MidnightBSD$ */
/*-
* Copyright (c) 1996-1999 Distributed Processing Technology Corporation
* All rights reserved.
@@ -19,7 +19,7 @@
* arising in any way out of the use of this driver software, even if advised
* of the possibility of such damage.
*
- * $FreeBSD$
+ * $FreeBSD: stable/10/sys/dev/asr/osd_util.h 139749 2005-01-06 01:43:34Z imp $
*/
#ifndef __OSD_UTIL_H
Modified: trunk/sys/dev/asr/sys_info.h
===================================================================
--- trunk/sys/dev/asr/sys_info.h 2018-05-28 00:25:20 UTC (rev 10127)
+++ trunk/sys/dev/asr/sys_info.h 2018-05-28 00:27:43 UTC (rev 10128)
@@ -1,4 +1,4 @@
-/* $MidnightBSD: src/sys/dev/asr/sys_info.h,v 1.2 2008/12/02 02:24:33 laffer1 Exp $ */
+/* $MidnightBSD$ */
/*-
* Copyright (c) 1996-1999 Distributed Processing Technology Corporation
* All rights reserved.
@@ -19,7 +19,7 @@
* arising in any way out of the use of this driver software, even if advised
* of the possibility of such damage.
*
- * $FreeBSD$
+ * $FreeBSD: stable/10/sys/dev/asr/sys_info.h 139749 2005-01-06 01:43:34Z imp $
*/
#ifndef __SYS_INFO_H
Modified: trunk/sys/dev/ata/ata-all.c
===================================================================
--- trunk/sys/dev/ata/ata-all.c 2018-05-28 00:25:20 UTC (rev 10127)
+++ trunk/sys/dev/ata/ata-all.c 2018-05-28 00:27:43 UTC (rev 10128)
@@ -1,5 +1,6 @@
+/* $MidnightBSD$ */
/*-
- * Copyright (c) 1998 - 2008 S\xF8ren Schmidt <sos at FreeBSD.org>
+ * Copyright (c) 1998 - 2008 Søren Schmidt <sos at FreeBSD.org>
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
@@ -25,9 +26,8 @@
*/
#include <sys/cdefs.h>
-__MBSDID("$MidnightBSD$");
+__FBSDID("$FreeBSD: stable/10/sys/dev/ata/ata-all.c 315813 2017-03-23 06:41:13Z mav $");
-#include "opt_ata.h"
#include <sys/param.h>
#include <sys/systm.h>
#include <sys/ata.h>
@@ -51,33 +51,13 @@
#include <dev/pci/pcivar.h>
#include <ata_if.h>
-#ifdef ATA_CAM
#include <cam/cam.h>
#include <cam/cam_ccb.h>
#include <cam/cam_sim.h>
#include <cam/cam_xpt_sim.h>
#include <cam/cam_debug.h>
-#endif
-#ifndef ATA_CAM
-/* device structure */
-static d_ioctl_t ata_ioctl;
-static struct cdevsw ata_cdevsw = {
- .d_version = D_VERSION,
- .d_flags = D_NEEDGIANT, /* we need this as newbus isn't mpsafe */
- .d_ioctl = ata_ioctl,
- .d_name = "ata",
-};
-#endif
-
/* prototypes */
-#ifndef ATA_CAM
-static void bswap(int8_t *, int);
-static void btrim(int8_t *, int);
-static void bpack(int8_t *, int8_t *, int);
-static void ata_boot_attach(void);
-static device_t ata_add_child(device_t, struct ata_device *, int);
-#else
static void ataaction(struct cam_sim *sim, union ccb *ccb);
static void atapoll(struct cam_sim *sim);
static void ata_cam_begin_transaction(device_t dev, union ccb *ccb);
@@ -84,61 +64,25 @@
static void ata_cam_end_transaction(device_t dev, struct ata_request *request);
static void ata_cam_request_sense(device_t dev, struct ata_request *request);
static int ata_check_ids(device_t dev, union ccb *ccb);
-static void ata_periodic_poll(void *data);
-#endif
-static void ata_conn_event(void *, int);
-static void ata_init(void);
+static void ata_conn_event(void *context, int dummy);
static void ata_interrupt_locked(void *data);
static int ata_module_event_handler(module_t mod, int what, void *arg);
+static void ata_periodic_poll(void *data);
static int ata_str2mode(const char *str);
-static void ata_uninit(void);
/* global vars */
MALLOC_DEFINE(M_ATA, "ata_generic", "ATA driver generic layer");
int (*ata_raid_ioctl_func)(u_long cmd, caddr_t data) = NULL;
-#ifndef ATA_CAM
-struct intr_config_hook *ata_delayed_attach = NULL;
-#endif
devclass_t ata_devclass;
-uma_zone_t ata_request_zone;
-uma_zone_t ata_composite_zone;
-#ifndef ATA_CAM
-int ata_wc = 1;
-int ata_setmax = 0;
-#endif
int ata_dma_check_80pin = 1;
-/* local vars */
-#ifndef ATA_CAM
-static int ata_dma = 1;
-static int atapi_dma = 1;
-#endif
-
/* sysctl vars */
static SYSCTL_NODE(_hw, OID_AUTO, ata, CTLFLAG_RD, 0, "ATA driver parameters");
-#ifndef ATA_CAM
-TUNABLE_INT("hw.ata.ata_dma", &ata_dma);
-SYSCTL_INT(_hw_ata, OID_AUTO, ata_dma, CTLFLAG_RDTUN, &ata_dma, 0,
- "ATA disk DMA mode control");
-#endif
TUNABLE_INT("hw.ata.ata_dma_check_80pin", &ata_dma_check_80pin);
SYSCTL_INT(_hw_ata, OID_AUTO, ata_dma_check_80pin,
CTLFLAG_RW, &ata_dma_check_80pin, 1,
"Check for 80pin cable before setting ATA DMA mode");
-#ifndef ATA_CAM
-TUNABLE_INT("hw.ata.atapi_dma", &atapi_dma);
-SYSCTL_INT(_hw_ata, OID_AUTO, atapi_dma, CTLFLAG_RDTUN, &atapi_dma, 0,
- "ATAPI device DMA mode control");
-TUNABLE_INT("hw.ata.wc", &ata_wc);
-SYSCTL_INT(_hw_ata, OID_AUTO, wc, CTLFLAG_RDTUN, &ata_wc, 0,
- "ATA disk write caching");
-TUNABLE_INT("hw.ata.setmax", &ata_setmax);
-SYSCTL_INT(_hw_ata, OID_AUTO, setmax, CTLFLAG_RDTUN, &ata_setmax, 0,
- "ATA disk set max native address");
-#endif
-#ifdef ATA_CAM
FEATURE(ata_cam, "ATA devices are accessed through the cam(4) driver");
-#endif
/*
* newbus device interface related functions
@@ -146,7 +90,7 @@
int
ata_probe(device_t dev)
{
- return 0;
+ return (BUS_PROBE_LOW_PRIORITY);
}
int
@@ -154,12 +98,10 @@
{
struct ata_channel *ch = device_get_softc(dev);
int error, rid;
-#ifdef ATA_CAM
struct cam_devq *devq;
const char *res;
char buf[64];
int i, mode;
-#endif
/* check that we have a virgin channel to attach */
if (ch->r_irq)
@@ -170,13 +112,7 @@
ch->state = ATA_IDLE;
bzero(&ch->state_mtx, sizeof(struct mtx));
mtx_init(&ch->state_mtx, "ATA state lock", NULL, MTX_DEF);
-#ifndef ATA_CAM
- bzero(&ch->queue_mtx, sizeof(struct mtx));
- mtx_init(&ch->queue_mtx, "ATA queue lock", NULL, MTX_DEF);
- TAILQ_INIT(&ch->ata_queue);
-#endif
TASK_INIT(&ch->conntask, 0, ata_conn_event, dev);
-#ifdef ATA_CAM
for (i = 0; i < 16; i++) {
ch->user[i].revision = 0;
snprintf(buf, sizeof(buf), "dev%d.sata_rev", i);
@@ -216,16 +152,7 @@
}
}
callout_init(&ch->poll_callout, 1);
-#endif
-#ifndef ATA_CAM
- /* reset the controller HW, the channel and device(s) */
- while (ATA_LOCKING(dev, ATA_LF_LOCK) != ch->unit)
- pause("ataatch", 1);
- ATA_RESET(dev);
- ATA_LOCKING(dev, ATA_LF_UNLOCK);
-#endif
-
/* allocate DMA resources if DMA HW present*/
if (ch->dma.alloc)
ch->dma.alloc(dev);
@@ -245,12 +172,6 @@
return error;
}
-#ifndef ATA_CAM
- /* probe and attach devices on this channel unless we are in early boot */
- if (!ata_delayed_attach)
- ata_identify(dev);
- return (0);
-#else
if (ch->flags & ATA_PERIODIC_POLL)
callout_reset(&ch->poll_callout, hz, ata_periodic_poll, ch);
mtx_lock(&ch->state_mtx);
@@ -295,7 +216,6 @@
if (ch->flags & ATA_PERIODIC_POLL)
callout_drain(&ch->poll_callout);
return (error);
-#endif
}
int
@@ -302,10 +222,6 @@
ata_detach(device_t dev)
{
struct ata_channel *ch = device_get_softc(dev);
-#ifndef ATA_CAM
- device_t *children;
- int nchildren, i;
-#endif
/* check that we have a valid channel to detach */
if (!ch->r_irq)
@@ -315,23 +231,11 @@
mtx_lock(&ch->state_mtx);
ch->state |= ATA_STALL_QUEUE;
mtx_unlock(&ch->state_mtx);
-#ifdef ATA_CAM
if (ch->flags & ATA_PERIODIC_POLL)
callout_drain(&ch->poll_callout);
-#endif
-#ifndef ATA_CAM
- /* detach & delete all children */
- if (!device_get_children(dev, &children, &nchildren)) {
- for (i = 0; i < nchildren; i++)
- if (children[i])
- device_delete_child(dev, children[i]);
- free(children, M_TEMP);
- }
-#endif
taskqueue_drain(taskqueue_thread, &ch->conntask);
-#ifdef ATA_CAM
mtx_lock(&ch->state_mtx);
xpt_async(AC_LOST_DEVICE, ch->path, NULL);
xpt_free_path(ch->path);
@@ -339,7 +243,6 @@
cam_sim_free(ch->sim, /*free_devq*/TRUE);
ch->sim = NULL;
mtx_unlock(&ch->state_mtx);
-#endif
/* release resources */
bus_teardown_intr(dev, ch->r_irq, ch->ih);
@@ -351,9 +254,6 @@
ch->dma.free(dev);
mtx_destroy(&ch->state_mtx);
-#ifndef ATA_CAM
- mtx_destroy(&ch->queue_mtx);
-#endif
return 0;
}
@@ -361,7 +261,6 @@
ata_conn_event(void *context, int dummy)
{
device_t dev = (device_t)context;
-#ifdef ATA_CAM
struct ata_channel *ch = device_get_softc(dev);
union ccb *ccb;
@@ -381,9 +280,6 @@
}
xpt_rescan(ccb);
mtx_unlock(&ch->state_mtx);
-#else
- ata_reinit(dev);
-#endif
}
int
@@ -391,94 +287,7 @@
{
struct ata_channel *ch = device_get_softc(dev);
struct ata_request *request;
-#ifndef ATA_CAM
- device_t *children;
- int nchildren, i;
- /* check that we have a valid channel to reinit */
- if (!ch || !ch->r_irq)
- return ENXIO;
-
- if (bootverbose)
- device_printf(dev, "reiniting channel ..\n");
-
- /* poll for locking the channel */
- while (ATA_LOCKING(dev, ATA_LF_LOCK) != ch->unit)
- pause("atarini", 1);
-
- /* catch eventual request in ch->running */
- mtx_lock(&ch->state_mtx);
- if (ch->state & ATA_STALL_QUEUE) {
- /* Recursive reinits and reinits during detach prohobited. */
- mtx_unlock(&ch->state_mtx);
- return (ENXIO);
- }
- if ((request = ch->running))
- callout_stop(&request->callout);
- ch->running = NULL;
-
- /* unconditionally grap the channel lock */
- ch->state |= ATA_STALL_QUEUE;
- mtx_unlock(&ch->state_mtx);
-
- /* reset the controller HW, the channel and device(s) */
- ATA_RESET(dev);
-
- /* reinit the children and delete any that fails */
- if (!device_get_children(dev, &children, &nchildren)) {
- mtx_lock(&Giant); /* newbus suckage it needs Giant */
- for (i = 0; i < nchildren; i++) {
- /* did any children go missing ? */
- if (children[i] && device_is_attached(children[i]) &&
- ATA_REINIT(children[i])) {
- /*
- * if we had a running request and its device matches
- * this child we need to inform the request that the
- * device is gone.
- */
- if (request && request->dev == children[i]) {
- request->result = ENXIO;
- device_printf(request->dev, "FAILURE - device detached\n");
-
- /* if not timeout finish request here */
- if (!(request->flags & ATA_R_TIMEOUT))
- ata_finish(request);
- request = NULL;
- }
- device_delete_child(dev, children[i]);
- }
- }
- free(children, M_TEMP);
- mtx_unlock(&Giant); /* newbus suckage dealt with, release Giant */
- }
-
- /* if we still have a good request put it on the queue again */
- if (request && !(request->flags & ATA_R_TIMEOUT)) {
- device_printf(request->dev,
- "WARNING - %s requeued due to channel reset",
- ata_cmd2str(request));
- if (!(request->flags & (ATA_R_ATAPI | ATA_R_CONTROL)))
- printf(" LBA=%ju", request->u.ata.lba);
- printf("\n");
- request->flags |= ATA_R_REQUEUE;
- ata_queue_request(request);
- }
-
- /* we're done release the channel for new work */
- mtx_lock(&ch->state_mtx);
- ch->state = ATA_IDLE;
- mtx_unlock(&ch->state_mtx);
- ATA_LOCKING(dev, ATA_LF_UNLOCK);
-
- /* Add new children. */
-/* ata_identify(dev); */
-
- if (bootverbose)
- device_printf(dev, "reinit done ..\n");
-
- /* kick off requests on the queue */
- ata_start(dev);
-#else
xpt_freeze_simq(ch->sim, 1);
if ((request = ch->running)) {
ch->running = NULL;
@@ -495,7 +304,6 @@
/* Tell the XPT about the event */
xpt_async(AC_BUS_RESET, ch->path, NULL);
xpt_release_simq(ch->sim, TRUE);
-#endif
return(0);
}
@@ -508,7 +316,6 @@
if (!dev || !(ch = device_get_softc(dev)))
return ENXIO;
-#ifdef ATA_CAM
if (ch->flags & ATA_PERIODIC_POLL)
callout_drain(&ch->poll_callout);
mtx_lock(&ch->state_mtx);
@@ -516,20 +323,6 @@
while (ch->state != ATA_IDLE)
msleep(ch, &ch->state_mtx, PRIBIO, "atasusp", hz/100);
mtx_unlock(&ch->state_mtx);
-#else
- /* wait for the channel to be IDLE or detached before suspending */
- while (ch->r_irq) {
- mtx_lock(&ch->state_mtx);
- if (ch->state == ATA_IDLE) {
- ch->state = ATA_ACTIVE;
- mtx_unlock(&ch->state_mtx);
- break;
- }
- mtx_unlock(&ch->state_mtx);
- tsleep(ch, PRIBIO, "atasusp", hz/10);
- }
- ATA_LOCKING(dev, ATA_LF_UNLOCK);
-#endif
return(0);
}
@@ -543,7 +336,6 @@
if (!dev || !(ch = device_get_softc(dev)))
return ENXIO;
-#ifdef ATA_CAM
mtx_lock(&ch->state_mtx);
error = ata_reinit(dev);
xpt_release_simq(ch->sim, TRUE);
@@ -550,12 +342,6 @@
mtx_unlock(&ch->state_mtx);
if (ch->flags & ATA_PERIODIC_POLL)
callout_reset(&ch->poll_callout, hz, ata_periodic_poll, ch);
-#else
- /* reinit the devices, we dont know what mode/state they are in */
- error = ata_reinit(dev);
- /* kick off requests on the queue */
- ata_start(dev);
-#endif
return error;
}
@@ -562,43 +348,33 @@
void
ata_interrupt(void *data)
{
-#ifdef ATA_CAM
struct ata_channel *ch = (struct ata_channel *)data;
mtx_lock(&ch->state_mtx);
- xpt_batch_start(ch->sim);
-#endif
ata_interrupt_locked(data);
-#ifdef ATA_CAM
- xpt_batch_done(ch->sim);
mtx_unlock(&ch->state_mtx);
-#endif
}
static void
ata_interrupt_locked(void *data)
{
- struct ata_channel *ch = (struct ata_channel *)data;
- struct ata_request *request;
+ struct ata_channel *ch = (struct ata_channel *)data;
+ struct ata_request *request;
-#ifndef ATA_CAM
- mtx_lock(&ch->state_mtx);
-#endif
- do {
/* ignore interrupt if its not for us */
if (ch->hw.status && !ch->hw.status(ch->dev))
- break;
+ return;
/* do we have a running request */
if (!(request = ch->running))
- break;
+ return;
ATA_DEBUG_RQ(request, "interrupt");
/* safetycheck for the right state */
if (ch->state == ATA_IDLE) {
- device_printf(request->dev, "interrupt on idle channel ignored\n");
- break;
+ device_printf(request->dev, "interrupt on idle channel ignored\n");
+ return;
}
/*
@@ -606,25 +382,14 @@
* if it finishes immediately otherwise wait for next interrupt
*/
if (ch->hw.end_transaction(request) == ATA_OP_FINISHED) {
- ch->running = NULL;
- if (ch->state == ATA_ACTIVE)
- ch->state = ATA_IDLE;
-#ifdef ATA_CAM
- ata_cam_end_transaction(ch->dev, request);
-#else
- mtx_unlock(&ch->state_mtx);
- ATA_LOCKING(ch->dev, ATA_LF_UNLOCK);
- ata_finish(request);
-#endif
- return;
+ ch->running = NULL;
+ if (ch->state == ATA_ACTIVE)
+ ch->state = ATA_IDLE;
+ ata_cam_end_transaction(ch->dev, request);
+ return;
}
- } while (0);
-#ifndef ATA_CAM
- mtx_unlock(&ch->state_mtx);
-#endif
}
-#ifdef ATA_CAM
static void
ata_periodic_poll(void *data)
{
@@ -633,7 +398,6 @@
callout_reset(&ch->poll_callout, hz, ata_periodic_poll, ch);
ata_interrupt(ch);
}
-#endif
void
ata_print_cable(device_t dev, u_int8_t *who)
@@ -642,468 +406,9 @@
"DMA limited to UDMA33, %s found non-ATA66 cable\n", who);
}
-#ifndef ATA_CAM
-int
-ata_check_80pin(device_t dev, int mode)
-{
- struct ata_device *atadev = device_get_softc(dev);
-
- if (!ata_dma_check_80pin) {
- if (bootverbose)
- device_printf(dev, "Skipping 80pin cable check\n");
- return mode;
- }
-
- if (mode > ATA_UDMA2 && !(atadev->param.hwres & ATA_CABLE_ID)) {
- ata_print_cable(dev, "device");
- mode = ATA_UDMA2;
- }
- return mode;
-}
-#endif
-
-#ifndef ATA_CAM
-void
-ata_setmode(device_t dev)
-{
- struct ata_channel *ch = device_get_softc(device_get_parent(dev));
- struct ata_device *atadev = device_get_softc(dev);
- int error, mode, pmode;
-
- mode = atadev->mode;
- do {
- pmode = mode = ata_limit_mode(dev, mode, ATA_DMA_MAX);
- mode = ATA_SETMODE(device_get_parent(dev), atadev->unit, mode);
- if ((ch->flags & (ATA_CHECKS_CABLE | ATA_SATA)) == 0)
- mode = ata_check_80pin(dev, mode);
- } while (pmode != mode); /* Interate till successfull negotiation. */
- error = ata_controlcmd(dev, ATA_SETFEATURES, ATA_SF_SETXFER, 0, mode);
- if (bootverbose)
- device_printf(dev, "%ssetting %s\n",
- (error) ? "FAILURE " : "", ata_mode2str(mode));
- atadev->mode = mode;
-}
-#endif
-
/*
- * device related interfaces
- */
-#ifndef ATA_CAM
-static int
-ata_ioctl(struct cdev *dev, u_long cmd, caddr_t data,
- int32_t flag, struct thread *td)
-{
- device_t device, *children;
- struct ata_ioc_devices *devices = (struct ata_ioc_devices *)data;
- int *value = (int *)data;
- int i, nchildren, error = ENOTTY;
-
- switch (cmd) {
- case IOCATAGMAXCHANNEL:
- /* In case we have channel 0..n this will return n+1. */
- *value = devclass_get_maxunit(ata_devclass);
- error = 0;
- break;
-
- case IOCATAREINIT:
- if (*value >= devclass_get_maxunit(ata_devclass) ||
- !(device = devclass_get_device(ata_devclass, *value)) ||
- !device_is_attached(device))
- return ENXIO;
- error = ata_reinit(device);
- break;
-
- case IOCATAATTACH:
- if (*value >= devclass_get_maxunit(ata_devclass) ||
- !(device = devclass_get_device(ata_devclass, *value)) ||
- !device_is_attached(device))
- return ENXIO;
- error = DEVICE_ATTACH(device);
- break;
-
- case IOCATADETACH:
- if (*value >= devclass_get_maxunit(ata_devclass) ||
- !(device = devclass_get_device(ata_devclass, *value)) ||
- !device_is_attached(device))
- return ENXIO;
- error = DEVICE_DETACH(device);
- break;
-
- case IOCATADEVICES:
- if (devices->channel >= devclass_get_maxunit(ata_devclass) ||
- !(device = devclass_get_device(ata_devclass, devices->channel)) ||
- !device_is_attached(device))
- return ENXIO;
- bzero(devices->name[0], 32);
- bzero(&devices->params[0], sizeof(struct ata_params));
- bzero(devices->name[1], 32);
- bzero(&devices->params[1], sizeof(struct ata_params));
- if (!device_get_children(device, &children, &nchildren)) {
- for (i = 0; i < nchildren; i++) {
- if (children[i] && device_is_attached(children[i])) {
- struct ata_device *atadev = device_get_softc(children[i]);
-
- if (atadev->unit == ATA_MASTER) { /* XXX SOS PM */
- strncpy(devices->name[0],
- device_get_nameunit(children[i]), 32);
- bcopy(&atadev->param, &devices->params[0],
- sizeof(struct ata_params));
- }
- if (atadev->unit == ATA_SLAVE) { /* XXX SOS PM */
- strncpy(devices->name[1],
- device_get_nameunit(children[i]), 32);
- bcopy(&atadev->param, &devices->params[1],
- sizeof(struct ata_params));
- }
- }
- }
- free(children, M_TEMP);
- error = 0;
- }
- else
- error = ENODEV;
- break;
-
- default:
- if (ata_raid_ioctl_func)
- error = ata_raid_ioctl_func(cmd, data);
- }
- return error;
-}
-#endif
-
-#ifndef ATA_CAM
-int
-ata_device_ioctl(device_t dev, u_long cmd, caddr_t data)
-{
- struct ata_device *atadev = device_get_softc(dev);
- struct ata_channel *ch = device_get_softc(device_get_parent(dev));
- struct ata_ioc_request *ioc_request = (struct ata_ioc_request *)data;
- struct ata_params *params = (struct ata_params *)data;
- int *mode = (int *)data;
- struct ata_request *request;
- caddr_t buf;
- int error;
-
- switch (cmd) {
- case IOCATAREQUEST:
- if (ioc_request->count >
- (ch->dma.max_iosize ? ch->dma.max_iosize : DFLTPHYS)) {
- return (EFBIG);
- }
- if (!(buf = malloc(ioc_request->count, M_ATA, M_NOWAIT))) {
- return ENOMEM;
- }
- if (!(request = ata_alloc_request())) {
- free(buf, M_ATA);
- return ENOMEM;
- }
- request->dev = atadev->dev;
- if (ioc_request->flags & ATA_CMD_WRITE) {
- error = copyin(ioc_request->data, buf, ioc_request->count);
- if (error) {
- free(buf, M_ATA);
- ata_free_request(request);
- return error;
- }
- }
- if (ioc_request->flags & ATA_CMD_ATAPI) {
- request->flags = ATA_R_ATAPI;
- bcopy(ioc_request->u.atapi.ccb, request->u.atapi.ccb, 16);
- }
- else {
- request->u.ata.command = ioc_request->u.ata.command;
- request->u.ata.feature = ioc_request->u.ata.feature;
- request->u.ata.lba = ioc_request->u.ata.lba;
- request->u.ata.count = ioc_request->u.ata.count;
- }
- request->timeout = ioc_request->timeout;
- request->data = buf;
- request->bytecount = ioc_request->count;
- request->transfersize = request->bytecount;
- if (ioc_request->flags & ATA_CMD_CONTROL)
- request->flags |= ATA_R_CONTROL;
- if (ioc_request->flags & ATA_CMD_READ)
- request->flags |= ATA_R_READ;
- if (ioc_request->flags & ATA_CMD_WRITE)
- request->flags |= ATA_R_WRITE;
- ata_queue_request(request);
- if (request->flags & ATA_R_ATAPI) {
- bcopy(&request->u.atapi.sense, &ioc_request->u.atapi.sense,
- sizeof(struct atapi_sense));
- }
- else {
- ioc_request->u.ata.command = request->u.ata.command;
- ioc_request->u.ata.feature = request->u.ata.feature;
- ioc_request->u.ata.lba = request->u.ata.lba;
- ioc_request->u.ata.count = request->u.ata.count;
- }
- ioc_request->error = request->result;
- if (ioc_request->flags & ATA_CMD_READ)
- error = copyout(buf, ioc_request->data, ioc_request->count);
- else
- error = 0;
- free(buf, M_ATA);
- ata_free_request(request);
- return error;
-
- case IOCATAGPARM:
- ata_getparam(atadev, 0);
- bcopy(&atadev->param, params, sizeof(struct ata_params));
- return 0;
-
- case IOCATASMODE:
- atadev->mode = *mode;
- ata_setmode(dev);
- return 0;
-
- case IOCATAGMODE:
- *mode = atadev->mode |
- (ATA_GETREV(device_get_parent(dev), atadev->unit) << 8);
- return 0;
- case IOCATASSPINDOWN:
- atadev->spindown = *mode;
- return 0;
- case IOCATAGSPINDOWN:
- *mode = atadev->spindown;
- return 0;
- default:
- return ENOTTY;
- }
-}
-#endif
-
-#ifndef ATA_CAM
-static void
-ata_boot_attach(void)
-{
- struct ata_channel *ch;
- int ctlr;
-
- mtx_lock(&Giant); /* newbus suckage it needs Giant */
-
- /* kick off probe and attach on all channels */
- for (ctlr = 0; ctlr < devclass_get_maxunit(ata_devclass); ctlr++) {
- if ((ch = devclass_get_softc(ata_devclass, ctlr))) {
- ata_identify(ch->dev);
- }
- }
-
- /* release the hook that got us here, we are only needed once during boot */
- if (ata_delayed_attach) {
- config_intrhook_disestablish(ata_delayed_attach);
- free(ata_delayed_attach, M_TEMP);
- ata_delayed_attach = NULL;
- }
-
- mtx_unlock(&Giant); /* newbus suckage dealt with, release Giant */
-}
-#endif
-
-/*
* misc support functions
*/
-#ifndef ATA_CAM
-static device_t
-ata_add_child(device_t parent, struct ata_device *atadev, int unit)
-{
- device_t child;
-
- if ((child = device_add_child(parent, (unit < 0) ? NULL : "ad", unit))) {
- device_set_softc(child, atadev);
- device_quiet(child);
- atadev->dev = child;
- atadev->max_iosize = DEV_BSIZE;
- atadev->mode = ATA_PIO_MAX;
- }
- return child;
-}
-#endif
-
-#ifndef ATA_CAM
-int
-ata_getparam(struct ata_device *atadev, int init)
-{
- struct ata_channel *ch = device_get_softc(device_get_parent(atadev->dev));
- struct ata_request *request;
- const char *res;
- char buf[64];
- u_int8_t command = 0;
- int error = ENOMEM, retries = 2, mode = -1;
-
- if (ch->devices & (ATA_ATA_MASTER << atadev->unit))
- command = ATA_ATA_IDENTIFY;
- if (ch->devices & (ATA_ATAPI_MASTER << atadev->unit))
- command = ATA_ATAPI_IDENTIFY;
- if (!command)
- return ENXIO;
-
- while (retries-- > 0 && error) {
- if (!(request = ata_alloc_request()))
- break;
- request->dev = atadev->dev;
- request->timeout = 1;
- request->retries = 0;
- request->u.ata.command = command;
- request->flags = (ATA_R_READ|ATA_R_AT_HEAD|ATA_R_DIRECT);
- if (!bootverbose)
- request->flags |= ATA_R_QUIET;
- request->data = (void *)&atadev->param;
- request->bytecount = sizeof(struct ata_params);
- request->donecount = 0;
- request->transfersize = DEV_BSIZE;
- ata_queue_request(request);
- error = request->result;
- ata_free_request(request);
- }
-
- if (!error && (isprint(atadev->param.model[0]) ||
- isprint(atadev->param.model[1]))) {
- struct ata_params *atacap = &atadev->param;
- int16_t *ptr;
-
- for (ptr = (int16_t *)atacap;
- ptr < (int16_t *)atacap + sizeof(struct ata_params)/2; ptr++) {
- *ptr = le16toh(*ptr);
- }
- if (!(!strncmp(atacap->model, "FX", 2) ||
- !strncmp(atacap->model, "NEC", 3) ||
- !strncmp(atacap->model, "Pioneer", 7) ||
- !strncmp(atacap->model, "SHARP", 5))) {
- bswap(atacap->model, sizeof(atacap->model));
- bswap(atacap->revision, sizeof(atacap->revision));
- bswap(atacap->serial, sizeof(atacap->serial));
- }
- btrim(atacap->model, sizeof(atacap->model));
- bpack(atacap->model, atacap->model, sizeof(atacap->model));
- btrim(atacap->revision, sizeof(atacap->revision));
- bpack(atacap->revision, atacap->revision, sizeof(atacap->revision));
- btrim(atacap->serial, sizeof(atacap->serial));
- bpack(atacap->serial, atacap->serial, sizeof(atacap->serial));
-
- if (bootverbose)
- printf("ata%d-%s: pio=%s wdma=%s udma=%s cable=%s wire\n",
- device_get_unit(ch->dev),
- ata_unit2str(atadev),
- ata_mode2str(ata_pmode(atacap)),
- ata_mode2str(ata_wmode(atacap)),
- ata_mode2str(ata_umode(atacap)),
- (atacap->hwres & ATA_CABLE_ID) ? "80":"40");
-
- if (init) {
- char buffer[64];
-
- sprintf(buffer, "%.40s/%.8s", atacap->model, atacap->revision);
- device_set_desc_copy(atadev->dev, buffer);
- if ((atadev->param.config & ATA_PROTO_ATAPI) &&
- (atadev->param.config != ATA_CFA_MAGIC1) &&
- (atadev->param.config != ATA_CFA_MAGIC2)) {
- if (atapi_dma &&
- (atadev->param.config & ATA_DRQ_MASK) != ATA_DRQ_INTR &&
- ata_umode(&atadev->param) >= ATA_UDMA2)
- atadev->mode = ATA_DMA_MAX;
- }
- else {
- if (ata_dma &&
- (ata_umode(&atadev->param) > 0 ||
- ata_wmode(&atadev->param) > 0))
- atadev->mode = ATA_DMA_MAX;
- }
- snprintf(buf, sizeof(buf), "dev%d.mode", atadev->unit);
- if (resource_string_value(device_get_name(ch->dev),
- device_get_unit(ch->dev), buf, &res) == 0)
- mode = ata_str2mode(res);
- else if (resource_string_value(device_get_name(ch->dev),
- device_get_unit(ch->dev), "mode", &res) == 0)
- mode = ata_str2mode(res);
- if (mode >= 0)
- atadev->mode = mode;
- }
- }
- else {
- if (!error)
- error = ENXIO;
- }
- return error;
-}
-#endif
-
-#ifndef ATA_CAM
-int
-ata_identify(device_t dev)
-{
- struct ata_channel *ch = device_get_softc(dev);
- struct ata_device *atadev;
- device_t *children;
- device_t child, master = NULL;
- int nchildren, i, n = ch->devices;
-
- if (bootverbose)
- device_printf(dev, "Identifying devices: %08x\n", ch->devices);
-
- mtx_lock(&Giant);
- /* Skip existing devices. */
- if (!device_get_children(dev, &children, &nchildren)) {
- for (i = 0; i < nchildren; i++) {
- if (children[i] && (atadev = device_get_softc(children[i])))
- n &= ~((ATA_ATA_MASTER | ATA_ATAPI_MASTER) << atadev->unit);
- }
- free(children, M_TEMP);
- }
- /* Create new devices. */
- if (bootverbose)
- device_printf(dev, "New devices: %08x\n", n);
- if (n == 0) {
- mtx_unlock(&Giant);
- return (0);
- }
- for (i = 0; i < ATA_PM; ++i) {
- if (n & (((ATA_ATA_MASTER | ATA_ATAPI_MASTER) << i))) {
- int unit = -1;
-
- if (!(atadev = malloc(sizeof(struct ata_device),
- M_ATA, M_NOWAIT | M_ZERO))) {
- device_printf(dev, "out of memory\n");
- return ENOMEM;
- }
- atadev->unit = i;
-#ifdef ATA_STATIC_ID
- if (n & (ATA_ATA_MASTER << i))
- unit = (device_get_unit(dev) << 1) + i;
-#endif
- if ((child = ata_add_child(dev, atadev, unit))) {
- /*
- * PATA slave should be identified first, to allow
- * device cable detection on master to work properly.
- */
- if (i == 0 && (n & ATA_PORTMULTIPLIER) == 0 &&
- (n & ((ATA_ATA_MASTER | ATA_ATAPI_MASTER) << 1)) != 0) {
- master = child;
- continue;
- }
- if (ata_getparam(atadev, 1)) {
- device_delete_child(dev, child);
- free(atadev, M_ATA);
- }
- }
- else
- free(atadev, M_ATA);
- }
- }
- if (master) {
- atadev = device_get_softc(master);
- if (ata_getparam(atadev, 1)) {
- device_delete_child(dev, master);
- free(atadev, M_ATA);
- }
- }
- bus_generic_probe(dev);
- bus_generic_attach(dev);
- mtx_unlock(&Giant);
- return 0;
-}
-#endif
-
void
ata_default_registers(device_t dev)
{
@@ -1120,111 +425,7 @@
ch->r_io[ATA_ALTSTAT].offset = ch->r_io[ATA_CONTROL].offset;
}
-#ifndef ATA_CAM
void
-ata_modify_if_48bit(struct ata_request *request)
-{
- struct ata_channel *ch = device_get_softc(request->parent);
- struct ata_device *atadev = device_get_softc(request->dev);
-
- request->flags &= ~ATA_R_48BIT;
-
- if (((request->u.ata.lba + request->u.ata.count) >= ATA_MAX_28BIT_LBA ||
- request->u.ata.count > 256) &&
- atadev->param.support.command2 & ATA_SUPPORT_ADDRESS48) {
-
- /* translate command into 48bit version */
- switch (request->u.ata.command) {
- case ATA_READ:
- request->u.ata.command = ATA_READ48;
- break;
- case ATA_READ_MUL:
- request->u.ata.command = ATA_READ_MUL48;
- break;
- case ATA_READ_DMA:
- if (ch->flags & ATA_NO_48BIT_DMA) {
- if (request->transfersize > DEV_BSIZE)
- request->u.ata.command = ATA_READ_MUL48;
- else
- request->u.ata.command = ATA_READ48;
- request->flags &= ~ATA_R_DMA;
- }
- else
- request->u.ata.command = ATA_READ_DMA48;
- break;
- case ATA_READ_DMA_QUEUED:
- if (ch->flags & ATA_NO_48BIT_DMA) {
- if (request->transfersize > DEV_BSIZE)
- request->u.ata.command = ATA_READ_MUL48;
- else
- request->u.ata.command = ATA_READ48;
- request->flags &= ~ATA_R_DMA;
- }
- else
- request->u.ata.command = ATA_READ_DMA_QUEUED48;
- break;
- case ATA_WRITE:
- request->u.ata.command = ATA_WRITE48;
- break;
- case ATA_WRITE_MUL:
- request->u.ata.command = ATA_WRITE_MUL48;
- break;
- case ATA_WRITE_DMA:
- if (ch->flags & ATA_NO_48BIT_DMA) {
- if (request->transfersize > DEV_BSIZE)
- request->u.ata.command = ATA_WRITE_MUL48;
- else
- request->u.ata.command = ATA_WRITE48;
- request->flags &= ~ATA_R_DMA;
- }
- else
- request->u.ata.command = ATA_WRITE_DMA48;
- break;
- case ATA_WRITE_DMA_QUEUED:
- if (ch->flags & ATA_NO_48BIT_DMA) {
- if (request->transfersize > DEV_BSIZE)
- request->u.ata.command = ATA_WRITE_MUL48;
- else
- request->u.ata.command = ATA_WRITE48;
- request->u.ata.command = ATA_WRITE48;
- request->flags &= ~ATA_R_DMA;
- }
- else
- request->u.ata.command = ATA_WRITE_DMA_QUEUED48;
- break;
- case ATA_FLUSHCACHE:
- request->u.ata.command = ATA_FLUSHCACHE48;
- break;
- case ATA_SET_MAX_ADDRESS:
- request->u.ata.command = ATA_SET_MAX_ADDRESS48;
- break;
- default:
- return;
- }
- request->flags |= ATA_R_48BIT;
- }
- else if (atadev->param.support.command2 & ATA_SUPPORT_ADDRESS48) {
-
- /* translate command into 48bit version */
- switch (request->u.ata.command) {
- case ATA_FLUSHCACHE:
- request->u.ata.command = ATA_FLUSHCACHE48;
- break;
- case ATA_READ_NATIVE_MAX_ADDRESS:
- request->u.ata.command = ATA_READ_NATIVE_MAX_ADDRESS48;
- break;
- case ATA_SET_MAX_ADDRESS:
- request->u.ata.command = ATA_SET_MAX_ADDRESS48;
- break;
- default:
- return;
- }
- request->flags |= ATA_R_48BIT;
- }
-}
-#endif
-
-void
ata_udelay(int interval)
{
/* for now just use DELAY, the timer/sleep subsytems are not there yet */
@@ -1234,22 +435,7 @@
pause("ataslp", interval/(1000000/hz));
}
-#ifndef ATA_CAM
const char *
-ata_unit2str(struct ata_device *atadev)
-{
- struct ata_channel *ch = device_get_softc(device_get_parent(atadev->dev));
- static char str[8];
-
- if (ch->devices & ATA_PORTMULTIPLIER)
- sprintf(str, "port%d", atadev->unit);
- else
- sprintf(str, "%s", atadev->unit == ATA_MASTER ? "master" : "slave");
- return str;
-}
-#endif
-
-const char *
ata_cmd2str(struct ata_request *request)
{
static char buffer[20];
@@ -1312,7 +498,18 @@
}
} else {
switch (request->u.ata.command) {
- case 0x00: return ("NOP");
+ case 0x00:
+ switch (request->u.ata.feature) {
+ case 0x00: return ("NOP FLUSHQUEUE");
+ case 0x01: return ("NOP AUTOPOLL");
+ }
+ return ("NOP");
+ case 0x03: return ("CFA_REQUEST_EXTENDED_ERROR");
+ case 0x06:
+ switch (request->u.ata.feature) {
+ case 0x01: return ("DSM TRIM");
+ }
+ return "DSM";
case 0x08: return ("DEVICE_RESET");
case 0x20: return ("READ");
case 0x24: return ("READ48");
@@ -1320,6 +517,9 @@
case 0x26: return ("READ_DMA_QUEUED48");
case 0x27: return ("READ_NATIVE_MAX_ADDRESS48");
case 0x29: return ("READ_MUL48");
+ case 0x2a: return ("READ_STREAM_DMA48");
+ case 0x2b: return ("READ_STREAM48");
+ case 0x2f: return ("READ_LOG_EXT");
case 0x30: return ("WRITE");
case 0x34: return ("WRITE48");
case 0x35: return ("WRITE_DMA48");
@@ -1326,12 +526,56 @@
case 0x36: return ("WRITE_DMA_QUEUED48");
case 0x37: return ("SET_MAX_ADDRESS48");
case 0x39: return ("WRITE_MUL48");
+ case 0x3a: return ("WRITE_STREAM_DMA48");
+ case 0x3b: return ("WRITE_STREAM48");
+ case 0x3d: return ("WRITE_DMA_FUA48");
+ case 0x3e: return ("WRITE_DMA_QUEUED_FUA48");
+ case 0x3f: return ("WRITE_LOG_EXT");
+ case 0x40: return ("READ_VERIFY");
+ case 0x42: return ("READ_VERIFY48");
+ case 0x45:
+ switch (request->u.ata.feature) {
+ case 0x55: return ("WRITE_UNCORRECTABLE48 PSEUDO");
+ case 0xaa: return ("WRITE_UNCORRECTABLE48 FLAGGED");
+ }
+ return "WRITE_UNCORRECTABLE48";
+ case 0x51: return ("CONFIGURE_STREAM");
+ case 0x60: return ("READ_FPDMA_QUEUED");
+ case 0x61: return ("WRITE_FPDMA_QUEUED");
+ case 0x63: return ("NCQ_NON_DATA");
+ case 0x64: return ("SEND_FPDMA_QUEUED");
+ case 0x65: return ("RECEIVE_FPDMA_QUEUED");
+ case 0x67:
+ if (request->u.ata.feature == 0xec)
+ return ("SEP_ATTN IDENTIFY");
+ switch (request->u.ata.lba) {
+ case 0x00: return ("SEP_ATTN READ BUFFER");
+ case 0x02: return ("SEP_ATTN RECEIVE DIAGNOSTIC RESULTS");
+ case 0x80: return ("SEP_ATTN WRITE BUFFER");
+ case 0x82: return ("SEP_ATTN SEND DIAGNOSTIC");
+ }
+ return ("SEP_ATTN");
case 0x70: return ("SEEK");
- case 0xa0: return ("PACKET_CMD");
+ case 0x87: return ("CFA_TRANSLATE_SECTOR");
+ case 0x90: return ("EXECUTE_DEVICE_DIAGNOSTIC");
+ case 0x92: return ("DOWNLOAD_MICROCODE");
+ case 0xa0: return ("PACKET");
case 0xa1: return ("ATAPI_IDENTIFY");
case 0xa2: return ("SERVICE");
- case 0xb0: return ("SMART");
- case 0xc0: return ("CFA ERASE");
+ case 0xb0:
+ switch(request->u.ata.feature) {
+ case 0xd0: return ("SMART READ ATTR VALUES");
+ case 0xd1: return ("SMART READ ATTR THRESHOLDS");
+ case 0xd3: return ("SMART SAVE ATTR VALUES");
+ case 0xd4: return ("SMART EXECUTE OFFLINE IMMEDIATE");
+ case 0xd5: return ("SMART READ LOG DATA");
+ case 0xd8: return ("SMART ENABLE OPERATION");
+ case 0xd9: return ("SMART DISABLE OPERATION");
+ case 0xda: return ("SMART RETURN STATUS");
+ }
+ return ("SMART");
+ case 0xb1: return ("DEVICE CONFIGURATION");
+ case 0xc0: return ("CFA_ERASE");
case 0xc4: return ("READ_MUL");
case 0xc5: return ("WRITE_MUL");
case 0xc6: return ("SET_MULTI");
@@ -1339,22 +583,48 @@
case 0xc8: return ("READ_DMA");
case 0xca: return ("WRITE_DMA");
case 0xcc: return ("WRITE_DMA_QUEUED");
+ case 0xcd: return ("CFA_WRITE_MULTIPLE_WITHOUT_ERASE");
+ case 0xce: return ("WRITE_MUL_FUA48");
+ case 0xd1: return ("CHECK_MEDIA_CARD_TYPE");
+ case 0xda: return ("GET_MEDIA_STATUS");
+ case 0xde: return ("MEDIA_LOCK");
+ case 0xdf: return ("MEDIA_UNLOCK");
+ case 0xe0: return ("STANDBY_IMMEDIATE");
+ case 0xe1: return ("IDLE_IMMEDIATE");
+ case 0xe2: return ("STANDBY");
+ case 0xe3: return ("IDLE");
+ case 0xe4: return ("READ_BUFFER/PM");
+ case 0xe5: return ("CHECK_POWER_MODE");
case 0xe6: return ("SLEEP");
case 0xe7: return ("FLUSHCACHE");
+ case 0xe8: return ("WRITE_PM");
case 0xea: return ("FLUSHCACHE48");
case 0xec: return ("ATA_IDENTIFY");
+ case 0xed: return ("MEDIA_EJECT");
case 0xef:
switch (request->u.ata.feature) {
case 0x03: return ("SETFEATURES SET TRANSFER MODE");
case 0x02: return ("SETFEATURES ENABLE WCACHE");
case 0x82: return ("SETFEATURES DISABLE WCACHE");
+ case 0x06: return ("SETFEATURES ENABLE PUIS");
+ case 0x86: return ("SETFEATURES DISABLE PUIS");
+ case 0x07: return ("SETFEATURES SPIN-UP");
+ case 0x10: return ("SETFEATURES ENABLE SATA FEATURE");
+ case 0x90: return ("SETFEATURES DISABLE SATA FEATURE");
case 0xaa: return ("SETFEATURES ENABLE RCACHE");
case 0x55: return ("SETFEATURES DISABLE RCACHE");
+ case 0x5d: return ("SETFEATURES ENABLE RELIRQ");
+ case 0xdd: return ("SETFEATURES DISABLE RELIRQ");
+ case 0x5e: return ("SETFEATURES ENABLE SRVIRQ");
+ case 0xde: return ("SETFEATURES DISABLE SRVIRQ");
}
- sprintf(buffer, "SETFEATURES 0x%02x",
- request->u.ata.feature);
- return (buffer);
- case 0xf5: return ("SECURITY_FREE_LOCK");
+ return "SETFEATURES";
+ case 0xf1: return ("SECURITY_SET_PASSWORD");
+ case 0xf2: return ("SECURITY_UNLOCK");
+ case 0xf3: return ("SECURITY_ERASE_PREPARE");
+ case 0xf4: return ("SECURITY_ERASE_UNIT");
+ case 0xf5: return ("SECURITY_FREEZE_LOCK");
+ case 0xf6: return ("SECURITY_DISABLE_PASSWORD");
case 0xf8: return ("READ_NATIVE_MAX_ADDRESS");
case 0xf9: return ("SET_MAX_ADDRESS");
}
@@ -1385,6 +655,7 @@
case ATA_UDMA6: return "UDMA133";
case ATA_SA150: return "SATA150";
case ATA_SA300: return "SATA300";
+ case ATA_SA600: return "SATA600";
default:
if (mode & ATA_DMA_MASK)
return "BIOSDMA";
@@ -1422,21 +693,6 @@
return (-1);
}
-#ifndef ATA_CAM
-const char *
-ata_satarev2str(int rev)
-{
- switch (rev) {
- case 0: return "";
- case 1: return "SATA 1.5Gb/s";
- case 2: return "SATA 3Gb/s";
- case 3: return "SATA 6Gb/s";
- case 0xff: return "SATA";
- default: return "???";
- }
-}
-#endif
-
int
ata_atapi(device_t dev, int target)
{
@@ -1445,142 +701,6 @@
return (ch->devices & (ATA_ATAPI_MASTER << target));
}
-#ifndef ATA_CAM
-int
-ata_pmode(struct ata_params *ap)
-{
- if (ap->atavalid & ATA_FLAG_64_70) {
- if (ap->apiomodes & 0x02)
- return ATA_PIO4;
- if (ap->apiomodes & 0x01)
- return ATA_PIO3;
- }
- if (ap->mwdmamodes & 0x04)
- return ATA_PIO4;
- if (ap->mwdmamodes & 0x02)
- return ATA_PIO3;
- if (ap->mwdmamodes & 0x01)
- return ATA_PIO2;
- if ((ap->retired_piomode & ATA_RETIRED_PIO_MASK) == 0x200)
- return ATA_PIO2;
- if ((ap->retired_piomode & ATA_RETIRED_PIO_MASK) == 0x100)
- return ATA_PIO1;
- if ((ap->retired_piomode & ATA_RETIRED_PIO_MASK) == 0x000)
- return ATA_PIO0;
- return ATA_PIO0;
-}
-#endif
-
-#ifndef ATA_CAM
-int
-ata_wmode(struct ata_params *ap)
-{
- if (ap->mwdmamodes & 0x04)
- return ATA_WDMA2;
- if (ap->mwdmamodes & 0x02)
- return ATA_WDMA1;
- if (ap->mwdmamodes & 0x01)
- return ATA_WDMA0;
- return -1;
-}
-#endif
-
-#ifndef ATA_CAM
-int
-ata_umode(struct ata_params *ap)
-{
- if (ap->atavalid & ATA_FLAG_88) {
- if (ap->udmamodes & 0x40)
- return ATA_UDMA6;
- if (ap->udmamodes & 0x20)
- return ATA_UDMA5;
- if (ap->udmamodes & 0x10)
- return ATA_UDMA4;
- if (ap->udmamodes & 0x08)
- return ATA_UDMA3;
- if (ap->udmamodes & 0x04)
- return ATA_UDMA2;
- if (ap->udmamodes & 0x02)
- return ATA_UDMA1;
- if (ap->udmamodes & 0x01)
- return ATA_UDMA0;
- }
- return -1;
-}
-#endif
-
-#ifndef ATA_CAM
-int
-ata_limit_mode(device_t dev, int mode, int maxmode)
-{
- struct ata_device *atadev = device_get_softc(dev);
-
- if (maxmode && mode > maxmode)
- mode = maxmode;
-
- if (mode >= ATA_UDMA0 && ata_umode(&atadev->param) > 0)
- return min(mode, ata_umode(&atadev->param));
-
- if (mode >= ATA_WDMA0 && ata_wmode(&atadev->param) > 0)
- return min(mode, ata_wmode(&atadev->param));
-
- if (mode > ata_pmode(&atadev->param))
- return min(mode, ata_pmode(&atadev->param));
-
- return mode;
-}
-#endif
-
-#ifndef ATA_CAM
-static void
-bswap(int8_t *buf, int len)
-{
- u_int16_t *ptr = (u_int16_t*)(buf + len);
-
- while (--ptr >= (u_int16_t*)buf)
- *ptr = ntohs(*ptr);
-}
-#endif
-
-#ifndef ATA_CAM
-static void
-btrim(int8_t *buf, int len)
-{
- int8_t *ptr;
-
- for (ptr = buf; ptr < buf+len; ++ptr)
- if (!*ptr || *ptr == '_')
- *ptr = ' ';
- for (ptr = buf + len - 1; ptr >= buf && *ptr == ' '; --ptr)
- *ptr = 0;
-}
-#endif
-
-#ifndef ATA_CAM
-static void
-bpack(int8_t *src, int8_t *dst, int len)
-{
- int i, j, blank;
-
- for (i = j = blank = 0 ; i < len; i++) {
- if (blank && src[i] == ' ') continue;
- if (blank && src[i] != ' ') {
- dst[j++] = src[i];
- blank = 0;
- continue;
- }
- if (src[i] == ' ') {
- blank = 1;
- if (i == 0)
- continue;
- }
- dst[j++] = src[i];
- }
- if (j < len)
- dst[j] = 0x00;
-}
-#endif
-
void
ata_timeout(struct ata_request *request)
{
@@ -1592,8 +712,7 @@
/*
* If we have an ATA_ACTIVE request running, we flag the request
- * ATA_R_TIMEOUT so ata_cam_end_transaction()/ata_finish() will handle
- * it correctly.
+ * ATA_R_TIMEOUT so ata_cam_end_transaction() will handle it correctly.
* Also, NULL out the running request so we wont loose the race with
* an eventual interrupt arriving late.
*/
@@ -1603,19 +722,11 @@
ch->dma.unload(request);
ch->running = NULL;
ch->state = ATA_IDLE;
-#ifdef ATA_CAM
ata_cam_end_transaction(ch->dev, request);
-#endif
- mtx_unlock(&ch->state_mtx);
-#ifndef ATA_CAM
- ATA_LOCKING(ch->dev, ATA_LF_UNLOCK);
- ata_finish(request);
-#endif
- } else
- mtx_unlock(&ch->state_mtx);
+ }
+ mtx_unlock(&ch->state_mtx);
}
-#ifdef ATA_CAM
static void
ata_cam_begin_transaction(device_t dev, union ccb *ccb)
{
@@ -1622,12 +733,7 @@
struct ata_channel *ch = device_get_softc(dev);
struct ata_request *request;
- if (!(request = ata_alloc_request())) {
- device_printf(dev, "FAILURE - out of memory in start\n");
- ccb->ccb_h.status = CAM_REQ_INVALID;
- xpt_done(ccb);
- return;
- }
+ request = &ch->request;
bzero(request, sizeof(*request));
/* setup request */
@@ -1695,6 +801,7 @@
request->timeout = (ccb->ccb_h.timeout + 999) / 1000;
callout_init_mtx(&request->callout, &ch->state_mtx, CALLOUT_RETURNUNLOCKED);
request->ccb = ccb;
+ request->flags |= ATA_R_DATA_IN_CCB;
ch->running = request;
ch->state = ATA_ACTIVE;
@@ -1765,7 +872,6 @@
ccb->ccb_h.status |= CAM_AUTOSENSE_FAIL;
}
- ata_free_request(request);
xpt_done(ccb);
/* Do error recovery if needed. */
if (fatalerr)
@@ -1836,10 +942,8 @@
if ((ccb->ccb_h.status & CAM_STATUS_MASK) == CAM_SCSI_STATUS_ERROR &&
(ccb->ccb_h.flags & CAM_DIS_AUTOSENSE) == 0)
ata_cam_request_sense(dev, request);
- else {
- ata_free_request(request);
+ else
xpt_done(ccb);
- }
/* Do error recovery if needed. */
if (fatalerr)
ata_reinit(dev);
@@ -2059,9 +1163,9 @@
cpi->base_transfer_speed = 150000;
else
cpi->base_transfer_speed = 3300;
- strncpy(cpi->sim_vid, "FreeBSD", SIM_IDLEN);
- strncpy(cpi->hba_vid, "ATA", HBA_IDLEN);
- strncpy(cpi->dev_name, cam_sim_name(sim), DEV_IDLEN);
+ strlcpy(cpi->sim_vid, "FreeBSD", SIM_IDLEN);
+ strlcpy(cpi->hba_vid, "ATA", HBA_IDLEN);
+ strlcpy(cpi->dev_name, cam_sim_name(sim), DEV_IDLEN);
cpi->unit_number = cam_sim_unit(sim);
if (ch->flags & ATA_SATA)
cpi->transport = XPORT_SATA;
@@ -2095,7 +1199,6 @@
ata_interrupt_locked(ch);
}
-#endif
/*
* module handeling
@@ -2103,38 +1206,12 @@
static int
ata_module_event_handler(module_t mod, int what, void *arg)
{
-#ifndef ATA_CAM
- static struct cdev *atacdev;
-#endif
switch (what) {
case MOD_LOAD:
-#ifndef ATA_CAM
- /* register controlling device */
- atacdev = make_dev(&ata_cdevsw, 0, UID_ROOT, GID_OPERATOR, 0600, "ata");
-
- if (cold) {
- /* register boot attach to be run when interrupts are enabled */
- if (!(ata_delayed_attach = (struct intr_config_hook *)
- malloc(sizeof(struct intr_config_hook),
- M_TEMP, M_NOWAIT | M_ZERO))) {
- printf("ata: malloc of delayed attach hook failed\n");
- return EIO;
- }
- ata_delayed_attach->ich_func = (void*)ata_boot_attach;
- if (config_intrhook_establish(ata_delayed_attach) != 0) {
- printf("ata: config_intrhook_establish failed\n");
- free(ata_delayed_attach, M_TEMP);
- }
- }
-#endif
return 0;
case MOD_UNLOAD:
-#ifndef ATA_CAM
- /* deregister controlling device */
- destroy_dev(atacdev);
-#endif
return 0;
default:
@@ -2145,25 +1222,4 @@
static moduledata_t ata_moduledata = { "ata", ata_module_event_handler, NULL };
DECLARE_MODULE(ata, ata_moduledata, SI_SUB_CONFIGURE, SI_ORDER_SECOND);
MODULE_VERSION(ata, 1);
-#ifdef ATA_CAM
MODULE_DEPEND(ata, cam, 1, 1, 1);
-#endif
-
-static void
-ata_init(void)
-{
- ata_request_zone = uma_zcreate("ata_request", sizeof(struct ata_request),
- NULL, NULL, NULL, NULL, 0, 0);
- ata_composite_zone = uma_zcreate("ata_composite",
- sizeof(struct ata_composite),
- NULL, NULL, NULL, NULL, 0, 0);
-}
-SYSINIT(ata_register, SI_SUB_DRIVERS, SI_ORDER_SECOND, ata_init, NULL);
-
-static void
-ata_uninit(void)
-{
- uma_zdestroy(ata_composite_zone);
- uma_zdestroy(ata_request_zone);
-}
-SYSUNINIT(ata_unregister, SI_SUB_DRIVERS, SI_ORDER_SECOND, ata_uninit, NULL);
Modified: trunk/sys/dev/ata/ata-all.h
===================================================================
--- trunk/sys/dev/ata/ata-all.h 2018-05-28 00:25:20 UTC (rev 10127)
+++ trunk/sys/dev/ata/ata-all.h 2018-05-28 00:27:43 UTC (rev 10128)
@@ -1,5 +1,6 @@
+/* $MidnightBSD$ */
/*-
- * Copyright (c) 1998 - 2008 S\xF8ren Schmidt <sos at FreeBSD.org>
+ * Copyright (c) 1998 - 2008 Søren Schmidt <sos at FreeBSD.org>
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
@@ -23,11 +24,9 @@
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
- * $MidnightBSD$
+ * $FreeBSD: stable/10/sys/dev/ata/ata-all.h 287285 2015-08-29 10:52:16Z mav $
*/
-#include "opt_ata.h"
-
#if 0
#define ATA_LEGACY_SUPPORT /* Enable obsolete features that break
* some modern devices */
@@ -152,139 +151,6 @@
#define ATA_SACTIVE 16
-/* SATA AHCI v1.0 register defines */
-#define ATA_AHCI_CAP 0x00
-#define ATA_AHCI_CAP_NPMASK 0x0000001f
-#define ATA_AHCI_CAP_SXS 0x00000020
-#define ATA_AHCI_CAP_EMS 0x00000040
-#define ATA_AHCI_CAP_CCCS 0x00000080
-#define ATA_AHCI_CAP_NCS 0x00001F00
-#define ATA_AHCI_CAP_NCS_SHIFT 8
-#define ATA_AHCI_CAP_PSC 0x00002000
-#define ATA_AHCI_CAP_SSC 0x00004000
-#define ATA_AHCI_CAP_PMD 0x00008000
-#define ATA_AHCI_CAP_FBSS 0x00010000
-#define ATA_AHCI_CAP_SPM 0x00020000
-#define ATA_AHCI_CAP_SAM 0x00080000
-#define ATA_AHCI_CAP_ISS 0x00F00000
-#define ATA_AHCI_CAP_ISS_SHIFT 20
-#define ATA_AHCI_CAP_SCLO 0x01000000
-#define ATA_AHCI_CAP_SAL 0x02000000
-#define ATA_AHCI_CAP_SALP 0x04000000
-#define ATA_AHCI_CAP_SSS 0x08000000
-#define ATA_AHCI_CAP_SMPS 0x10000000
-#define ATA_AHCI_CAP_SSNTF 0x20000000
-#define ATA_AHCI_CAP_SNCQ 0x40000000
-#define ATA_AHCI_CAP_64BIT 0x80000000
-
-#define ATA_AHCI_GHC 0x04
-#define ATA_AHCI_GHC_AE 0x80000000
-#define ATA_AHCI_GHC_IE 0x00000002
-#define ATA_AHCI_GHC_HR 0x00000001
-
-#define ATA_AHCI_IS 0x08
-#define ATA_AHCI_PI 0x0c
-#define ATA_AHCI_VS 0x10
-
-#define ATA_AHCI_OFFSET 0x80
-
-#define ATA_AHCI_P_CLB 0x100
-#define ATA_AHCI_P_CLBU 0x104
-#define ATA_AHCI_P_FB 0x108
-#define ATA_AHCI_P_FBU 0x10c
-#define ATA_AHCI_P_IS 0x110
-#define ATA_AHCI_P_IE 0x114
-#define ATA_AHCI_P_IX_DHR 0x00000001
-#define ATA_AHCI_P_IX_PS 0x00000002
-#define ATA_AHCI_P_IX_DS 0x00000004
-#define ATA_AHCI_P_IX_SDB 0x00000008
-#define ATA_AHCI_P_IX_UF 0x00000010
-#define ATA_AHCI_P_IX_DP 0x00000020
-#define ATA_AHCI_P_IX_PC 0x00000040
-#define ATA_AHCI_P_IX_DI 0x00000080
-
-#define ATA_AHCI_P_IX_PRC 0x00400000
-#define ATA_AHCI_P_IX_IPM 0x00800000
-#define ATA_AHCI_P_IX_OF 0x01000000
-#define ATA_AHCI_P_IX_INF 0x04000000
-#define ATA_AHCI_P_IX_IF 0x08000000
-#define ATA_AHCI_P_IX_HBD 0x10000000
-#define ATA_AHCI_P_IX_HBF 0x20000000
-#define ATA_AHCI_P_IX_TFE 0x40000000
-#define ATA_AHCI_P_IX_CPD 0x80000000
-
-#define ATA_AHCI_P_CMD 0x118
-#define ATA_AHCI_P_CMD_ST 0x00000001
-#define ATA_AHCI_P_CMD_SUD 0x00000002
-#define ATA_AHCI_P_CMD_POD 0x00000004
-#define ATA_AHCI_P_CMD_CLO 0x00000008
-#define ATA_AHCI_P_CMD_FRE 0x00000010
-#define ATA_AHCI_P_CMD_CCS_MASK 0x00001f00
-#define ATA_AHCI_P_CMD_ISS 0x00002000
-#define ATA_AHCI_P_CMD_FR 0x00004000
-#define ATA_AHCI_P_CMD_CR 0x00008000
-#define ATA_AHCI_P_CMD_CPS 0x00010000
-#define ATA_AHCI_P_CMD_PMA 0x00020000
-#define ATA_AHCI_P_CMD_HPCP 0x00040000
-#define ATA_AHCI_P_CMD_ISP 0x00080000
-#define ATA_AHCI_P_CMD_CPD 0x00100000
-#define ATA_AHCI_P_CMD_ATAPI 0x01000000
-#define ATA_AHCI_P_CMD_DLAE 0x02000000
-#define ATA_AHCI_P_CMD_ALPE 0x04000000
-#define ATA_AHCI_P_CMD_ASP 0x08000000
-#define ATA_AHCI_P_CMD_ICC_MASK 0xf0000000
-#define ATA_AHCI_P_CMD_NOOP 0x00000000
-#define ATA_AHCI_P_CMD_ACTIVE 0x10000000
-#define ATA_AHCI_P_CMD_PARTIAL 0x20000000
-#define ATA_AHCI_P_CMD_SLUMBER 0x60000000
-
-#define ATA_AHCI_P_TFD 0x120
-#define ATA_AHCI_P_SIG 0x124
-#define ATA_AHCI_P_SSTS 0x128
-#define ATA_AHCI_P_SCTL 0x12c
-#define ATA_AHCI_P_SERR 0x130
-#define ATA_AHCI_P_SACT 0x134
-#define ATA_AHCI_P_CI 0x138
-#define ATA_AHCI_P_SNTF 0x13C
-#define ATA_AHCI_P_FBS 0x140
-
-#define ATA_AHCI_CL_SIZE 32
-#define ATA_AHCI_CL_OFFSET 0
-#define ATA_AHCI_FB_OFFSET (ATA_AHCI_CL_SIZE * 32)
-#define ATA_AHCI_CT_OFFSET (ATA_AHCI_FB_OFFSET + 4096)
-#define ATA_AHCI_CT_SIZE (2176 + 128)
-
-struct ata_ahci_dma_prd {
- u_int64_t dba;
- u_int32_t reserved;
- u_int32_t dbc; /* 0 based */
-#define ATA_AHCI_PRD_MASK 0x003fffff /* max 4MB */
-#define ATA_AHCI_PRD_IPC (1<<31)
-} __packed;
-
-struct ata_ahci_cmd_tab {
- u_int8_t cfis[64];
- u_int8_t acmd[32];
- u_int8_t reserved[32];
-#define ATA_AHCI_DMA_ENTRIES 129
- struct ata_ahci_dma_prd prd_tab[ATA_AHCI_DMA_ENTRIES];
-} __packed;
-
-struct ata_ahci_cmd_list {
- u_int16_t cmd_flags;
-#define ATA_AHCI_CMD_ATAPI 0x0020
-#define ATA_AHCI_CMD_WRITE 0x0040
-#define ATA_AHCI_CMD_PREFETCH 0x0080
-#define ATA_AHCI_CMD_RESET 0x0100
-#define ATA_AHCI_CMD_BIST 0x0200
-#define ATA_AHCI_CMD_CLR_BUSY 0x0400
-
- u_int16_t prd_length; /* PRD entries */
- u_int32_t bytecount;
- u_int64_t cmd_table_phys; /* 128byte aligned */
-} __packed;
-
-
/* DMA register defines */
#define ATA_DMA_ENTRIES 256
#define ATA_DMA_EOT 0x80000000
@@ -399,6 +265,7 @@
#define ATA_R_THREAD 0x00000800
#define ATA_R_DIRECT 0x00001000
#define ATA_R_NEEDRESULT 0x00002000
+#define ATA_R_DATA_IN_CCB 0x00004000
#define ATA_R_ATAPI16 0x00010000
#define ATA_R_ATAPI_INTR 0x00020000
@@ -423,9 +290,7 @@
struct ata_composite *composite; /* for composite atomic ops */
void *driver; /* driver specific */
TAILQ_ENTRY(ata_request) chain; /* list management */
-#ifdef ATA_CAM
union ccb *ccb;
-#endif
};
/* define this for debugging request processing */
@@ -532,7 +397,6 @@
int offset;
};
-#ifdef ATA_CAM
struct ata_cam_device {
u_int revision;
int mode;
@@ -540,7 +404,6 @@
u_int atapi;
u_int caps;
};
-#endif
/* structure describing an ATA channel */
struct ata_channel {
@@ -580,21 +443,15 @@
#define ATA_ACTIVE 0x0001
#define ATA_STALL_QUEUE 0x0002
-#ifndef ATA_CAM
- struct mtx queue_mtx; /* queue lock */
- TAILQ_HEAD(, ata_request) ata_queue; /* head of ATA queue */
- struct ata_request *freezepoint; /* composite freezepoint */
-#endif
struct ata_request *running; /* currently running request */
struct task conntask; /* PHY events handling task */
-#ifdef ATA_CAM
struct cam_sim *sim;
struct cam_path *path;
struct ata_cam_device user[16]; /* User-specified settings */
struct ata_cam_device curr[16]; /* Current settings */
int requestsense; /* CCB waiting for SENSE. */
-#endif
struct callout poll_callout; /* Periodic status poll. */
+ struct ata_request request;
};
/* disk bay/enclosure related */
@@ -621,38 +478,16 @@
int ata_suspend(device_t dev);
int ata_resume(device_t dev);
void ata_interrupt(void *data);
-int ata_device_ioctl(device_t dev, u_long cmd, caddr_t data);
int ata_getparam(struct ata_device *atadev, int init);
void ata_default_registers(device_t dev);
void ata_udelay(int interval);
-const char *ata_unit2str(struct ata_device *atadev);
const char *ata_cmd2str(struct ata_request *request);
const char *ata_mode2str(int mode);
void ata_setmode(device_t dev);
void ata_print_cable(device_t dev, u_int8_t *who);
-const char *ata_satarev2str(int rev);
int ata_atapi(device_t dev, int target);
void ata_timeout(struct ata_request *);
-#ifndef ATA_CAM
-int ata_identify(device_t dev);
-void ata_modify_if_48bit(struct ata_request *request);
-int ata_pmode(struct ata_params *ap);
-int ata_wmode(struct ata_params *ap);
-int ata_umode(struct ata_params *ap);
-int ata_limit_mode(device_t dev, int mode, int maxmode);
-int ata_check_80pin(device_t dev, int mode);
-#endif
-/* ata-queue.c: */
-int ata_controlcmd(device_t dev, u_int8_t command, u_int16_t feature, u_int64_t lba, u_int16_t count);
-int ata_atapicmd(device_t dev, u_int8_t *ccb, caddr_t data, int count, int flags, int timeout);
-void ata_queue_request(struct ata_request *request);
-void ata_start(device_t dev);
-void ata_finish(struct ata_request *request);
-void ata_catch_inflight(device_t dev);
-void ata_fail_requests(device_t dev);
-void ata_drop_requests(device_t dev);
-
/* ata-lowlevel.c: */
void ata_generic_hw(device_t dev);
int ata_begin_transaction(struct ata_request *);
@@ -674,19 +509,6 @@
int ata_request2fis_h2d(struct ata_request *request, u_int8_t *fis);
void ata_pm_identify(device_t dev);
-/* macros for alloc/free of struct ata_request */
-extern uma_zone_t ata_request_zone;
-#define ata_alloc_request() uma_zalloc(ata_request_zone, M_NOWAIT | M_ZERO)
-#define ata_free_request(request) { \
- if (!(request->flags & ATA_R_DANGER2)) \
- uma_zfree(ata_request_zone, request); \
- }
-
-/* macros for alloc/free of struct ata_composite */
-extern uma_zone_t ata_composite_zone;
-#define ata_alloc_composite() uma_zalloc(ata_composite_zone, M_NOWAIT | M_ZERO)
-#define ata_free_composite(composite) uma_zfree(ata_composite_zone, composite)
-
MALLOC_DECLARE(M_ATA);
/* misc newbus defines */
Modified: trunk/sys/dev/ata/ata-card.c
===================================================================
--- trunk/sys/dev/ata/ata-card.c 2018-05-28 00:25:20 UTC (rev 10127)
+++ trunk/sys/dev/ata/ata-card.c 2018-05-28 00:27:43 UTC (rev 10128)
@@ -1,5 +1,6 @@
+/* $MidnightBSD$ */
/*-
- * Copyright (c) 1998 - 2008 S\xF8ren Schmidt <sos at FreeBSD.org>
+ * Copyright (c) 1998 - 2008 Søren Schmidt <sos at FreeBSD.org>
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
@@ -25,7 +26,7 @@
*/
#include <sys/cdefs.h>
-__MBSDID("$MidnightBSD$");
+__FBSDID("$FreeBSD: stable/10/sys/dev/ata/ata-card.c 256326 2013-10-11 18:27:12Z grehan $");
#include <sys/param.h>
#include <sys/systm.h>
@@ -140,7 +141,7 @@
ch-> flags |= ATA_NO_SLAVE;
ata_generic_hw(dev);
err = ata_probe(dev);
- if (err)
+ if (err > 0)
return (err);
return (ata_attach(dev));
}
Modified: trunk/sys/dev/ata/ata-cbus.c
===================================================================
--- trunk/sys/dev/ata/ata-cbus.c 2018-05-28 00:25:20 UTC (rev 10127)
+++ trunk/sys/dev/ata/ata-cbus.c 2018-05-28 00:27:43 UTC (rev 10128)
@@ -1,5 +1,6 @@
+/* $MidnightBSD$ */
/*-
- * Copyright (c) 2002 - 2008 S\xF8ren Schmidt <sos at FreeBSD.org>
+ * Copyright (c) 2002 - 2008 Søren Schmidt <sos at FreeBSD.org>
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
@@ -25,9 +26,8 @@
*/
#include <sys/cdefs.h>
-__MBSDID("$MidnightBSD$");
+__FBSDID("$FreeBSD: stable/10/sys/dev/ata/ata-cbus.c 249213 2013-04-06 19:12:49Z marius $");
-#include "opt_ata.h"
#include <sys/param.h>
#include <sys/systm.h>
#include <sys/kernel.h>
@@ -53,12 +53,6 @@
struct resource *bankio;
struct resource *irq;
void *ih;
-#ifndef ATA_CAM
- struct mtx bank_mtx;
- int locked_bank;
- int restart_bank;
- int hardware_bank;
-#endif
int channels;
struct {
void (*function)(void *);
@@ -68,9 +62,6 @@
/* local prototypes */
static void ata_cbus_intr(void *);
-#ifndef ATA_CAM
-static int ata_cbuschannel_banking(device_t dev, int flags);
-#endif
static int
ata_cbus_probe(device_t dev)
@@ -160,17 +151,9 @@
return ENXIO;
}
-#ifndef ATA_CAM
- ctlr->channels = 2;
- mtx_init(&ctlr->bank_mtx, "ATA cbus bank lock", NULL, MTX_DEF);
- ctlr->hardware_bank = -1;
- ctlr->locked_bank = -1;
- ctlr->restart_bank = -1;
-#else
/* Work around the lack of channel serialization in ATA_CAM. */
ctlr->channels = 1;
device_printf(dev, "second channel ignored\n");
-#endif
for (unit = 0; unit < ctlr->channels; unit++) {
child = device_add_child(dev, "ata", unit);
@@ -244,10 +227,7 @@
for (unit = 0; unit < ctlr->channels; unit++) {
if (!(ch = ctlr->interrupt[unit].argument))
continue;
-#ifndef ATA_CAM
- if (ata_cbuschannel_banking(ch->dev, ATA_LF_WHICH) == unit)
-#endif
- ctlr->interrupt[unit].function(ch);
+ ctlr->interrupt[unit].function(ch);
}
}
@@ -349,50 +329,6 @@
return ata_resume(dev);
}
-#ifndef ATA_CAM
-static int
-ata_cbuschannel_banking(device_t dev, int flags)
-{
- struct ata_cbus_controller *ctlr = device_get_softc(device_get_parent(dev));
- struct ata_channel *ch = device_get_softc(dev);
- int res;
-
- mtx_lock(&ctlr->bank_mtx);
- switch (flags) {
- case ATA_LF_LOCK:
- if (ctlr->locked_bank == -1)
- ctlr->locked_bank = ch->unit;
- if (ctlr->locked_bank == ch->unit) {
- ctlr->hardware_bank = ch->unit;
- ATA_OUTB(ctlr->bankio, 0, ch->unit);
- }
- else
- ctlr->restart_bank = ch->unit;
- break;
-
- case ATA_LF_UNLOCK:
- if (ctlr->locked_bank == ch->unit) {
- ctlr->locked_bank = -1;
- if (ctlr->restart_bank != -1) {
- if ((ch = ctlr->interrupt[ctlr->restart_bank].argument)) {
- ctlr->restart_bank = -1;
- mtx_unlock(&ctlr->bank_mtx);
- ata_start(ch->dev);
- return -1;
- }
- }
- }
- break;
-
- case ATA_LF_WHICH:
- break;
- }
- res = ctlr->locked_bank;
- mtx_unlock(&ctlr->bank_mtx);
- return res;
-}
-#endif
-
static device_method_t ata_cbuschannel_methods[] = {
/* device interface */
DEVMETHOD(device_probe, ata_cbuschannel_probe),
@@ -400,11 +336,6 @@
DEVMETHOD(device_detach, ata_cbuschannel_detach),
DEVMETHOD(device_suspend, ata_cbuschannel_suspend),
DEVMETHOD(device_resume, ata_cbuschannel_resume),
-
-#ifndef ATA_CAM
- /* ATA methods */
- DEVMETHOD(ata_locking, ata_cbuschannel_banking),
-#endif
DEVMETHOD_END
};
Modified: trunk/sys/dev/ata/ata-dma.c
===================================================================
--- trunk/sys/dev/ata/ata-dma.c 2018-05-28 00:25:20 UTC (rev 10127)
+++ trunk/sys/dev/ata/ata-dma.c 2018-05-28 00:27:43 UTC (rev 10128)
@@ -1,5 +1,6 @@
+/* $MidnightBSD$ */
/*-
- * Copyright (c) 1998 - 2008 S\xF8ren Schmidt <sos at FreeBSD.org>
+ * Copyright (c) 1998 - 2008 Søren Schmidt <sos at FreeBSD.org>
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
@@ -25,7 +26,7 @@
*/
#include <sys/cdefs.h>
-__MBSDID("$MidnightBSD$");
+__FBSDID("$FreeBSD: stable/10/sys/dev/ata/ata-dma.c 249083 2013-04-04 07:12:24Z mav $");
#include <sys/param.h>
#include <sys/systm.h>
@@ -304,10 +305,15 @@
else
dspa.dmatab = request->dma->sg;
- if ((error = bus_dmamap_load(request->dma->data_tag, request->dma->data_map,
- request->data, request->bytecount,
- ch->dma.setprd, &dspa, BUS_DMA_NOWAIT)) ||
- (error = dspa.error)) {
+ if (request->flags & ATA_R_DATA_IN_CCB)
+ error = bus_dmamap_load_ccb(request->dma->data_tag,
+ request->dma->data_map, request->ccb,
+ ch->dma.setprd, &dspa, BUS_DMA_NOWAIT);
+ else
+ error = bus_dmamap_load(request->dma->data_tag, request->dma->data_map,
+ request->data, request->bytecount,
+ ch->dma.setprd, &dspa, BUS_DMA_NOWAIT);
+ if (error || (error = dspa.error)) {
device_printf(request->parent, "FAILURE - load data\n");
goto error;
}
Modified: trunk/sys/dev/ata/ata-isa.c
===================================================================
--- trunk/sys/dev/ata/ata-isa.c 2018-05-28 00:25:20 UTC (rev 10127)
+++ trunk/sys/dev/ata/ata-isa.c 2018-05-28 00:27:43 UTC (rev 10128)
@@ -1,5 +1,6 @@
+/* $MidnightBSD$ */
/*-
- * Copyright (c) 1998 - 2008 S\xF8ren Schmidt <sos at FreeBSD.org>
+ * Copyright (c) 1998 - 2008 Søren Schmidt <sos at FreeBSD.org>
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
@@ -25,9 +26,8 @@
*/
#include <sys/cdefs.h>
-__MBSDID("$MidnightBSD$");
+__FBSDID("$FreeBSD: stable/10/sys/dev/ata/ata-isa.c 249213 2013-04-06 19:12:49Z marius $");
-#include "opt_ata.h"
#include <sys/param.h>
#include <sys/systm.h>
#include <sys/ata.h>
Modified: trunk/sys/dev/ata/ata-lowlevel.c
===================================================================
--- trunk/sys/dev/ata/ata-lowlevel.c 2018-05-28 00:25:20 UTC (rev 10127)
+++ trunk/sys/dev/ata/ata-lowlevel.c 2018-05-28 00:27:43 UTC (rev 10128)
@@ -1,5 +1,6 @@
+/* $MidnightBSD$ */
/*-
- * Copyright (c) 1998 - 2008 S\xF8ren Schmidt <sos at FreeBSD.org>
+ * Copyright (c) 1998 - 2008 Søren Schmidt <sos at FreeBSD.org>
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
@@ -25,9 +26,8 @@
*/
#include <sys/cdefs.h>
-__MBSDID("$MidnightBSD$");
+__FBSDID("$FreeBSD: stable/10/sys/dev/ata/ata-lowlevel.c 250576 2013-05-12 16:43:26Z eadler $");
-#include "opt_ata.h"
#include <sys/param.h>
#include <sys/systm.h>
#include <sys/kernel.h>
@@ -378,7 +378,6 @@
"%s trying to write on read buffer\n",
ata_cmd2str(request));
goto end_finished;
- break;
}
ata_pio_write(request, length);
request->donecount += length;
@@ -505,7 +504,7 @@
mask, ostat0, ostat1);
/* if nothing showed up there is no need to get any further */
- /* XXX SOS is that too strong?, we just might loose devices here */
+ /* XXX SOS is that too strong?, we just might lose devices here */
ch->devices = 0;
if (!mask)
return;
@@ -784,9 +783,6 @@
ata_tf_write(struct ata_request *request)
{
struct ata_channel *ch = device_get_softc(request->parent);
-#ifndef ATA_CAM
- struct ata_device *atadev = device_get_softc(request->dev);
-#endif
if (request->flags & ATA_R_48BIT) {
ATA_IDX_OUTB(ch, ATA_FEATURE, request->u.ata.feature >> 8);
@@ -804,30 +800,6 @@
else {
ATA_IDX_OUTB(ch, ATA_FEATURE, request->u.ata.feature);
ATA_IDX_OUTB(ch, ATA_COUNT, request->u.ata.count);
-#ifndef ATA_CAM
- if (atadev->flags & ATA_D_USE_CHS) {
- int heads, sectors;
-
- if (atadev->param.atavalid & ATA_FLAG_54_58) {
- heads = atadev->param.current_heads;
- sectors = atadev->param.current_sectors;
- }
- else {
- heads = atadev->param.heads;
- sectors = atadev->param.sectors;
- }
-
- ATA_IDX_OUTB(ch, ATA_SECTOR, (request->u.ata.lba % sectors)+1);
- ATA_IDX_OUTB(ch, ATA_CYL_LSB,
- (request->u.ata.lba / (sectors * heads)));
- ATA_IDX_OUTB(ch, ATA_CYL_MSB,
- (request->u.ata.lba / (sectors * heads)) >> 8);
- ATA_IDX_OUTB(ch, ATA_DRIVE, ATA_D_IBM | ATA_DEV(request->unit) |
- (((request->u.ata.lba% (sectors * heads)) /
- sectors) & 0xf));
- }
- else {
-#endif
ATA_IDX_OUTB(ch, ATA_SECTOR, request->u.ata.lba);
ATA_IDX_OUTB(ch, ATA_CYL_LSB, request->u.ata.lba >> 8);
ATA_IDX_OUTB(ch, ATA_CYL_MSB, request->u.ata.lba >> 16);
@@ -834,9 +806,6 @@
ATA_IDX_OUTB(ch, ATA_DRIVE,
ATA_D_IBM | ATA_D_LBA | ATA_DEV(request->unit) |
((request->u.ata.lba >> 24) & 0x0f));
-#ifndef ATA_CAM
- }
-#endif
}
}
Modified: trunk/sys/dev/ata/ata-pci.c
===================================================================
--- trunk/sys/dev/ata/ata-pci.c 2018-05-28 00:25:20 UTC (rev 10127)
+++ trunk/sys/dev/ata/ata-pci.c 2018-05-28 00:27:43 UTC (rev 10128)
@@ -1,5 +1,6 @@
+/* $MidnightBSD$ */
/*-
- * Copyright (c) 1998 - 2008 S\xF8ren Schmidt <sos at FreeBSD.org>
+ * Copyright (c) 1998 - 2008 Søren Schmidt <sos at FreeBSD.org>
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
@@ -25,9 +26,8 @@
*/
#include <sys/cdefs.h>
-__MBSDID("$MidnightBSD$");
+__FBSDID("$FreeBSD: stable/10/sys/dev/ata/ata-pci.c 254263 2013-08-12 23:30:01Z scottl $");
-#include "opt_ata.h"
#include <sys/param.h>
#include <sys/systm.h>
#include <sys/kernel.h>
@@ -99,11 +99,8 @@
ctlr->dev = dev;
/* if needed try to enable busmastering */
+ pci_enable_busmaster(dev);
cmd = pci_read_config(dev, PCIR_COMMAND, 2);
- if (!(cmd & PCIM_CMD_BUSMASTEREN)) {
- pci_write_config(dev, PCIR_COMMAND, cmd | PCIM_CMD_BUSMASTEREN, 2);
- cmd = pci_read_config(dev, PCIR_COMMAND, 2);
- }
/* if busmastering mode "stuck" use it */
if ((cmd & PCIM_CMD_BUSMASTEREN) == PCIM_CMD_BUSMASTEREN) {
@@ -706,21 +703,6 @@
return ata_resume(dev);
}
-
-#ifndef ATA_CAM
-static int
-ata_pcichannel_locking(device_t dev, int mode)
-{
- struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
- struct ata_channel *ch = device_get_softc(dev);
-
- if (ctlr->locking)
- return ctlr->locking(dev, mode);
- else
- return ch->unit;
-}
-#endif
-
static void
ata_pcichannel_reset(device_t dev)
{
@@ -776,9 +758,6 @@
/* ATA methods */
DEVMETHOD(ata_setmode, ata_pcichannel_setmode),
DEVMETHOD(ata_getrev, ata_pcichannel_getrev),
-#ifndef ATA_CAM
- DEVMETHOD(ata_locking, ata_pcichannel_locking),
-#endif
DEVMETHOD(ata_reset, ata_pcichannel_reset),
DEVMETHOD_END
Modified: trunk/sys/dev/ata/ata-pci.h
===================================================================
--- trunk/sys/dev/ata/ata-pci.h 2018-05-28 00:25:20 UTC (rev 10127)
+++ trunk/sys/dev/ata/ata-pci.h 2018-05-28 00:27:43 UTC (rev 10128)
@@ -1,5 +1,6 @@
+/* $MidnightBSD$ */
/*-
- * Copyright (c) 2003 - 2008 S\xF8ren Schmidt <sos at FreeBSD.org>
+ * Copyright (c) 2003 - 2008 Søren Schmidt <sos at FreeBSD.org>
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
@@ -23,7 +24,7 @@
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
- * $MidnightBSD$
+ * $FreeBSD: stable/10/sys/dev/ata/ata-pci.h 287016 2015-08-22 07:32:47Z mav $
*/
/* structure holding chipset config info */
@@ -62,9 +63,6 @@
int (*ch_detach)(device_t);
int (*ch_suspend)(device_t);
int (*ch_resume)(device_t);
-#ifndef ATA_CAM
- int (*locking)(device_t, int);
-#endif
void (*reset)(device_t);
int (*setmode)(device_t, int, int);
int (*getrev)(device_t, int);
@@ -172,9 +170,6 @@
#define ATA_I6300ESB_R1 0x25b08086
#define ATA_I63XXESB2 0x269e8086
#define ATA_I63XXESB2_S1 0x26808086
-#define ATA_I63XXESB2_S2 0x26818086
-#define ATA_I63XXESB2_R1 0x26828086
-#define ATA_I63XXESB2_R2 0x26838086
#define ATA_I82801FB 0x266f8086
#define ATA_I82801FB_S1 0x26518086
#define ATA_I82801FB_R1 0x26528086
@@ -181,102 +176,75 @@
#define ATA_I82801FBM 0x26538086
#define ATA_I82801GB 0x27df8086
#define ATA_I82801GB_S1 0x27c08086
-#define ATA_I82801GB_AH 0x27c18086
-#define ATA_I82801GB_R1 0x27c38086
#define ATA_I82801GBM_S1 0x27c48086
-#define ATA_I82801GBM_AH 0x27c58086
-#define ATA_I82801GBM_R1 0x27c68086
#define ATA_I82801HB_S1 0x28208086
-#define ATA_I82801HB_AH6 0x28218086
-#define ATA_I82801HB_R1 0x28228086
-#define ATA_I82801HB_AH4 0x28248086
#define ATA_I82801HB_S2 0x28258086
#define ATA_I82801HBM 0x28508086
#define ATA_I82801HBM_S1 0x28288086
-#define ATA_I82801HBM_S2 0x28298086
-#define ATA_I82801HBM_S3 0x282a8086
#define ATA_I82801IB_S1 0x29208086
#define ATA_I82801IB_S3 0x29218086
-#define ATA_I82801IB_AH6 0x29228086
-#define ATA_I82801IB_AH4 0x29238086
#define ATA_I82801IB_R1 0x29258086
#define ATA_I82801IB_S2 0x29268086
#define ATA_I82801IBM_S1 0x29288086
-#define ATA_I82801IBM_AH 0x29298086
-#define ATA_I82801IBM_R1 0x292a8086
#define ATA_I82801IBM_S2 0x292d8086
#define ATA_I82801JIB_S1 0x3a208086
-#define ATA_I82801JIB_AH 0x3a228086
-#define ATA_I82801JIB_R1 0x3a258086
#define ATA_I82801JIB_S2 0x3a268086
#define ATA_I82801JD_S1 0x3a008086
-#define ATA_I82801JD_AH 0x3a028086
-#define ATA_I82801JD_R1 0x3a058086
#define ATA_I82801JD_S2 0x3a068086
#define ATA_I82801JI_S1 0x3a208086
-#define ATA_I82801JI_AH 0x3a228086
-#define ATA_I82801JI_R1 0x3a258086
#define ATA_I82801JI_S2 0x3a268086
#define ATA_5Series_S1 0x3b208086
#define ATA_5Series_S2 0x3b218086
-#define ATA_5Series_AH1 0x3b228086
-#define ATA_5Series_AH2 0x3b238086
-#define ATA_5Series_R1 0x3b258086
#define ATA_5Series_S3 0x3b268086
#define ATA_5Series_S4 0x3b288086
-#define ATA_5Series_AH3 0x3b298086
-#define ATA_5Series_R2 0x3b2c8086
#define ATA_5Series_S5 0x3b2d8086
#define ATA_5Series_S6 0x3b2e8086
-#define ATA_5Series_AH4 0x3b2f8086
#define ATA_CPT_S1 0x1c008086
#define ATA_CPT_S2 0x1c018086
-#define ATA_CPT_AH1 0x1c028086
-#define ATA_CPT_AH2 0x1c038086
-#define ATA_CPT_R1 0x1c048086
-#define ATA_CPT_R2 0x1c058086
#define ATA_CPT_S3 0x1c088086
#define ATA_CPT_S4 0x1c098086
#define ATA_PBG_S1 0x1d008086
-#define ATA_PBG_AH1 0x1d028086
-#define ATA_PBG_R1 0x1d048086
-#define ATA_PBG_R2 0x1d068086
-#define ATA_PBG_R3 0x28268086
#define ATA_PBG_S2 0x1d088086
#define ATA_PPT_S1 0x1e008086
#define ATA_PPT_S2 0x1e018086
-#define ATA_PPT_AH1 0x1e028086
-#define ATA_PPT_AH2 0x1e038086
-#define ATA_PPT_R1 0x1e048086
-#define ATA_PPT_R2 0x1e058086
-#define ATA_PPT_R3 0x1e068086
-#define ATA_PPT_R4 0x1e078086
#define ATA_PPT_S3 0x1e088086
#define ATA_PPT_S4 0x1e098086
-#define ATA_PPT_R5 0x1e0e8086
-#define ATA_PPT_R6 0x1e0f8086
+#define ATA_AVOTON_S1 0x1f208086
+#define ATA_AVOTON_S2 0x1f218086
+#define ATA_AVOTON_S3 0x1f308086
+#define ATA_AVOTON_S4 0x1f318086
+
#define ATA_LPT_S1 0x8c008086
#define ATA_LPT_S2 0x8c018086
-#define ATA_LPT_AH1 0x8c028086
-#define ATA_LPT_AH2 0x8c038086
-#define ATA_LPT_R1 0x8c048086
-#define ATA_LPT_R2 0x8c058086
-#define ATA_LPT_R3 0x8c068086
-#define ATA_LPT_R4 0x8c078086
#define ATA_LPT_S3 0x8c088086
#define ATA_LPT_S4 0x8c098086
-#define ATA_LPT_R5 0x8c0e8086
-#define ATA_LPT_R6 0x8c0f8086
+#define ATA_WCPT_S1 0x8c808086
+#define ATA_WCPT_S2 0x8c818086
+#define ATA_WCPT_S3 0x8c888086
+#define ATA_WCPT_S4 0x8c898086
+
+#define ATA_WELLS_S1 0x8d008086
+#define ATA_WELLS_S2 0x8d088086
+#define ATA_WELLS_S3 0x8d608086
+#define ATA_WELLS_S4 0x8d688086
+
+#define ATA_LPTLP_S1 0x9c008086
+#define ATA_LPTLP_S2 0x9c018086
+#define ATA_LPTLP_S3 0x9c088086
+#define ATA_LPTLP_S4 0x9c098086
+
#define ATA_I31244 0x32008086
#define ATA_ISCH 0x811a8086
-#define ATA_DH89XXCC 0x23238086
+#define ATA_COLETOCRK_S1 0x23a18086
+#define ATA_COLETOCRK_S2 0x23a68086
+
#define ATA_ITE_ID 0x1283
#define ATA_IT8211F 0x82111283
#define ATA_IT8212F 0x82121283
@@ -290,16 +258,9 @@
#define ATA_JMB365 0x2365197b
#define ATA_JMB366 0x2366197b
#define ATA_JMB368 0x2368197b
+#define ATA_JMB368_2 0x0368197b
#define ATA_MARVELL_ID 0x11ab
-#define ATA_M88SX5040 0x504011ab
-#define ATA_M88SX5041 0x504111ab
-#define ATA_M88SX5080 0x508011ab
-#define ATA_M88SX5081 0x508111ab
-#define ATA_M88SX6041 0x604111ab
-#define ATA_M88SX6042 0x604211ab
-#define ATA_M88SX6081 0x608111ab
-#define ATA_M88SX7042 0x704211ab
#define ATA_M88SE6101 0x610111ab
#define ATA_M88SE6102 0x610211ab
#define ATA_M88SE6111 0x611111ab
@@ -475,10 +436,6 @@
#define ATA_SII3512 0x35121095
#define ATA_SII3112 0x31121095
#define ATA_SII3112_1 0x02401095
-#define ATA_SII3124 0x31241095
-#define ATA_SII3132 0x31321095
-#define ATA_SII3132_1 0x02421095
-#define ATA_SII3132_2 0x02441095
#define ATA_SII0680 0x06801095
#define ATA_CMD646 0x06461095
#define ATA_CMD648 0x06481095
@@ -601,8 +558,6 @@
int ata_mode2idx(int mode);
/* global prototypes from chipsets/ata-*.c */
-int ata_ahci_chipinit(device_t);
-int ata_marvell_edma_chipinit(device_t);
int ata_sii_chipinit(device_t);
/* externs */
Modified: trunk/sys/dev/ata/ata-sata.c
===================================================================
--- trunk/sys/dev/ata/ata-sata.c 2018-05-28 00:25:20 UTC (rev 10127)
+++ trunk/sys/dev/ata/ata-sata.c 2018-05-28 00:27:43 UTC (rev 10128)
@@ -1,5 +1,6 @@
+/* $MidnightBSD$ */
/*-
- * Copyright (c) 1998 - 2008 S\xF8ren Schmidt <sos at FreeBSD.org>
+ * Copyright (c) 1998 - 2008 Søren Schmidt <sos at FreeBSD.org>
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
@@ -25,9 +26,8 @@
*/
#include <sys/cdefs.h>
-__MBSDID("$MidnightBSD$");
+__FBSDID("$FreeBSD: stable/10/sys/dev/ata/ata-sata.c 249213 2013-04-06 19:12:49Z marius $");
-#include "opt_ata.h"
#include <sys/param.h>
#include <sys/systm.h>
#include <sys/kernel.h>
@@ -157,13 +157,9 @@
int loop, retry, sata_rev;
uint32_t val, val1;
-#ifdef ATA_CAM
sata_rev = ch->user[port < 0 ? 0 : port].revision;
if (sata_rev > 0)
quick = 0;
-#else
- sata_rev = 0;
-#endif
if (quick) {
if (ata_sata_scr_read(ch, port, ATA_SCONTROL, &val))
Modified: trunk/sys/dev/ata/ata_if.m
===================================================================
--- trunk/sys/dev/ata/ata_if.m 2018-05-28 00:25:20 UTC (rev 10127)
+++ trunk/sys/dev/ata/ata_if.m 2018-05-28 00:27:43 UTC (rev 10128)
@@ -1,4 +1,5 @@
-# Copyright (c) 2004 - 2008 S\xF8ren Schmidt <sos at FreeBSD.org>
+/* $MidnightBSD$ */
+# Copyright (c) 2004 - 2008 Søren Schmidt <sos at FreeBSD.org>
# All rights reserved.
#
# Redistribution and use in source and binary forms, with or without
@@ -22,7 +23,7 @@
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
# THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
#
-# $MidnightBSD$
+# $FreeBSD: stable/10/sys/dev/ata/ata_if.m 249083 2013-04-04 07:12:24Z mav $
#include <sys/bus.h>
#include <sys/kernel.h>
@@ -39,24 +40,6 @@
INTERFACE ata;
CODE {
- static int ata_null_locking(device_t dev, int mode)
- {
- struct ata_channel *ch = device_get_softc(dev);
-
- return ch->unit;
- }
-};
-METHOD int locking {
- device_t channel;
- int mode;
-} DEFAULT ata_null_locking;
-HEADER {
-#define ATA_LF_LOCK 0x0001
-#define ATA_LF_UNLOCK 0x0002
-#define ATA_LF_WHICH 0x0004
-};
-
-CODE {
static int ata_null_setmode(device_t dev, int target, int mode)
{
Property changes on: trunk/sys/dev/ata/ata_if.m
___________________________________________________________________
Added: svn:keywords
## -0,0 +1 ##
+MidnightBSD=%H
\ No newline at end of property
Modified: trunk/sys/dev/ata/chipsets/ata-acard.c
===================================================================
--- trunk/sys/dev/ata/chipsets/ata-acard.c 2018-05-28 00:25:20 UTC (rev 10127)
+++ trunk/sys/dev/ata/chipsets/ata-acard.c 2018-05-28 00:27:43 UTC (rev 10128)
@@ -1,5 +1,6 @@
+/* $MidnightBSD$ */
/*-
- * Copyright (c) 1998 - 2008 S\xF8ren Schmidt <sos at FreeBSD.org>
+ * Copyright (c) 1998 - 2008 Søren Schmidt <sos at FreeBSD.org>
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
@@ -25,9 +26,8 @@
*/
#include <sys/cdefs.h>
-__MBSDID("$MidnightBSD$");
+__FBSDID("$FreeBSD: stable/10/sys/dev/ata/chipsets/ata-acard.c 281140 2015-04-06 08:23:06Z mav $");
-#include "opt_ata.h"
#include <sys/param.h>
#include <sys/module.h>
#include <sys/systm.h>
@@ -51,14 +51,6 @@
#include <dev/ata/ata-pci.h>
#include <ata_if.h>
-#ifndef ATA_CAM
-struct ata_serialize {
- struct mtx locked_mtx;
- int locked_ch;
- int restart_ch;
-};
-#endif
-
/* local prototypes */
static int ata_acard_chipinit(device_t dev);
static int ata_acard_ch_attach(device_t dev);
@@ -65,11 +57,6 @@
static int ata_acard_status(device_t dev);
static int ata_acard_850_setmode(device_t dev, int target, int mode);
static int ata_acard_86X_setmode(device_t dev, int target, int mode);
-#ifndef ATA_CAM
-static int ata_acard_chipdeinit(device_t dev);
-static int ata_serialize(device_t dev, int flags);
-static void ata_serialize_init(struct ata_serialize *serial);
-#endif
/* misc defines */
#define ATP_OLD 1
@@ -97,10 +84,7 @@
ata_set_desc(dev);
ctlr->chipinit = ata_acard_chipinit;
-#ifndef ATA_CAM
- ctlr->chipdeinit = ata_acard_chipdeinit;
-#endif
- return (BUS_PROBE_DEFAULT);
+ return (BUS_PROBE_LOW_PRIORITY);
}
static int
@@ -107,9 +91,6 @@
ata_acard_chipinit(device_t dev)
{
struct ata_pci_controller *ctlr = device_get_softc(dev);
-#ifndef ATA_CAM
- struct ata_serialize *serial;
-#endif
if (ata_setup_interrupt(dev, ata_generic_intr))
return ENXIO;
@@ -118,17 +99,9 @@
ctlr->ch_detach = ata_pci_ch_detach;
if (ctlr->chip->cfg1 == ATP_OLD) {
ctlr->setmode = ata_acard_850_setmode;
-#ifndef ATA_CAM
- ctlr->locking = ata_serialize;
- serial = malloc(sizeof(struct ata_serialize),
- M_ATAPCI, M_WAITOK | M_ZERO);
- ata_serialize_init(serial);
- ctlr->chipset_data = serial;
-#else
/* Work around the lack of channel serialization in ATA_CAM. */
ctlr->channels = 1;
device_printf(dev, "second channel ignored\n");
-#endif
}
else
ctlr->setmode = ata_acard_86X_setmode;
@@ -135,24 +108,7 @@
return 0;
}
-#ifndef ATA_CAM
static int
-ata_acard_chipdeinit(device_t dev)
-{
- struct ata_pci_controller *ctlr = device_get_softc(dev);
- struct ata_serialize *serial;
-
- if (ctlr->chip->cfg1 == ATP_OLD) {
- serial = ctlr->chipset_data;
- mtx_destroy(&serial->locked_mtx);
- free(serial, M_ATAPCI);
- ctlr->chipset_data = NULL;
- }
- return (0);
-}
-#endif
-
-static int
ata_acard_ch_attach(device_t dev)
{
struct ata_channel *ch = device_get_softc(dev);
@@ -169,12 +125,8 @@
static int
ata_acard_status(device_t dev)
{
- struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
struct ata_channel *ch = device_get_softc(dev);
- if (ctlr->chip->cfg1 == ATP_OLD &&
- ATA_LOCKING(dev, ATA_LF_WHICH) != ch->unit)
- return 0;
if (ch->dma.flags & ATA_DMA_ACTIVE) {
int bmstat = ATA_IDX_INB(ch, ATA_BMSTAT_PORT) & ATA_BMSTAT_MASK;
@@ -243,56 +195,4 @@
return (mode);
}
-#ifndef ATA_CAM
-static void
-ata_serialize_init(struct ata_serialize *serial)
-{
-
- mtx_init(&serial->locked_mtx, "ATA serialize lock", NULL, MTX_DEF);
- serial->locked_ch = -1;
- serial->restart_ch = -1;
-}
-
-static int
-ata_serialize(device_t dev, int flags)
-{
- struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
- struct ata_channel *ch = device_get_softc(dev);
- struct ata_serialize *serial;
- int res;
-
- serial = ctlr->chipset_data;
-
- mtx_lock(&serial->locked_mtx);
- switch (flags) {
- case ATA_LF_LOCK:
- if (serial->locked_ch == -1)
- serial->locked_ch = ch->unit;
- if (serial->locked_ch != ch->unit)
- serial->restart_ch = ch->unit;
- break;
-
- case ATA_LF_UNLOCK:
- if (serial->locked_ch == ch->unit) {
- serial->locked_ch = -1;
- if (serial->restart_ch != -1) {
- if ((ch = ctlr->interrupt[serial->restart_ch].argument)) {
- serial->restart_ch = -1;
- mtx_unlock(&serial->locked_mtx);
- ata_start(dev);
- return -1;
- }
- }
- }
- break;
-
- case ATA_LF_WHICH:
- break;
- }
- res = serial->locked_ch;
- mtx_unlock(&serial->locked_mtx);
- return res;
-}
-#endif
-
ATA_DECLARE_DRIVER(ata_acard);
Modified: trunk/sys/dev/ata/chipsets/ata-acerlabs.c
===================================================================
--- trunk/sys/dev/ata/chipsets/ata-acerlabs.c 2018-05-28 00:25:20 UTC (rev 10127)
+++ trunk/sys/dev/ata/chipsets/ata-acerlabs.c 2018-05-28 00:27:43 UTC (rev 10128)
@@ -1,5 +1,6 @@
+/* $MidnightBSD$ */
/*-
- * Copyright (c) 1998 - 2008 S\xF8ren Schmidt <sos at FreeBSD.org>
+ * Copyright (c) 1998 - 2008 Søren Schmidt <sos at FreeBSD.org>
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
@@ -25,9 +26,8 @@
*/
#include <sys/cdefs.h>
-__MBSDID("$MidnightBSD$");
+__FBSDID("$FreeBSD: stable/10/sys/dev/ata/chipsets/ata-acerlabs.c 287016 2015-08-22 07:32:47Z mav $");
-#include "opt_ata.h"
#include <sys/param.h>
#include <sys/module.h>
#include <sys/systm.h>
@@ -97,7 +97,7 @@
ata_set_desc(dev);
ctlr->chipinit = ata_ali_chipinit;
ctlr->chipdeinit = ata_ali_chipdeinit;
- return (BUS_PROBE_DEFAULT);
+ return (BUS_PROBE_LOW_PRIORITY);
}
static int
@@ -118,11 +118,6 @@
ctlr->setmode = ata_sata_setmode;
ctlr->getrev = ata_sata_getrev;
- /* AHCI mode is correctly supported only on the ALi 5288. */
- if ((ctlr->chip->chipid == ATA_ALI_5288) &&
- (ata_ahci_chipinit(dev) != ENXIO))
- return 0;
-
/* Allocate resources for later use by channel attach routines. */
res = malloc(sizeof(struct ali_sata_resources), M_ATAPCI, M_WAITOK);
for (i = 0; i < 4; i++) {
@@ -134,7 +129,7 @@
for (i--; i >=0; i--)
bus_release_resource(dev, SYS_RES_IOPORT,
PCIR_BAR(i), res->bars[i]);
- free(res, M_TEMP);
+ free(res, M_ATAPCI);
return ENXIO;
}
}
@@ -213,10 +208,8 @@
if (ch->dma.max_iosize > 256 * 512)
ch->dma.max_iosize = 256 * 512;
}
-#ifdef ATA_CAM
if (ctlr->chip->cfg2 & ALI_NEW)
ch->flags |= ATA_NO_ATAPI_DMA;
-#endif
return 0;
}
@@ -350,4 +343,3 @@
}
ATA_DECLARE_DRIVER(ata_ali);
-MODULE_DEPEND(ata_ali, ata_ahci, 1, 1, 1);
Modified: trunk/sys/dev/ata/chipsets/ata-amd.c
===================================================================
--- trunk/sys/dev/ata/chipsets/ata-amd.c 2018-05-28 00:25:20 UTC (rev 10127)
+++ trunk/sys/dev/ata/chipsets/ata-amd.c 2018-05-28 00:27:43 UTC (rev 10128)
@@ -1,5 +1,6 @@
+/* $MidnightBSD$ */
/*-
- * Copyright (c) 1998 - 2008 S\xF8ren Schmidt <sos at FreeBSD.org>
+ * Copyright (c) 1998 - 2008 Søren Schmidt <sos at FreeBSD.org>
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
@@ -25,9 +26,8 @@
*/
#include <sys/cdefs.h>
-__MBSDID("$MidnightBSD$");
+__FBSDID("$FreeBSD: stable/10/sys/dev/ata/chipsets/ata-amd.c 281140 2015-04-06 08:23:06Z mav $");
-#include "opt_ata.h"
#include <sys/param.h>
#include <sys/module.h>
#include <sys/systm.h>
@@ -83,7 +83,7 @@
ata_set_desc(dev);
ctlr->chipinit = ata_amd_chipinit;
- return (BUS_PROBE_DEFAULT);
+ return (BUS_PROBE_LOW_PRIORITY);
}
static int
Modified: trunk/sys/dev/ata/chipsets/ata-ati.c
===================================================================
--- trunk/sys/dev/ata/chipsets/ata-ati.c 2018-05-28 00:25:20 UTC (rev 10127)
+++ trunk/sys/dev/ata/chipsets/ata-ati.c 2018-05-28 00:27:43 UTC (rev 10128)
@@ -1,5 +1,6 @@
+/* $MidnightBSD$ */
/*-
- * Copyright (c) 1998 - 2008 S\xF8ren Schmidt <sos at FreeBSD.org>
+ * Copyright (c) 1998 - 2008 Søren Schmidt <sos at FreeBSD.org>
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
@@ -25,9 +26,8 @@
*/
#include <sys/cdefs.h>
-__MBSDID("$MidnightBSD$");
+__FBSDID("$FreeBSD: stable/10/sys/dev/ata/chipsets/ata-ati.c 287016 2015-08-22 07:32:47Z mav $");
-#include "opt_ata.h"
#include <sys/param.h>
#include <sys/module.h>
#include <sys/systm.h>
@@ -65,9 +65,6 @@
#define ATI_PATA 0x02
#define ATI_AHCI 0x04
-static int force_ahci = 1;
-TUNABLE_INT("hw.ahci.force", &force_ahci);
-
/*
* ATI chipset support functions
*/
@@ -99,14 +96,12 @@
{ ATA_AMD_HUDSON2_S5, 0x00, ATI_AHCI, 0, ATA_SA300, "Hudson-2" },
{ 0, 0, 0, 0, 0, 0}};
- if (pci_get_vendor(dev) != ATA_ATI_ID)
+ if (pci_get_vendor(dev) != ATA_AMD_ID && pci_get_vendor(dev) != ATA_ATI_ID)
return ENXIO;
if (!(ctlr->chip = ata_match_chip(dev, ids)))
return ENXIO;
- ata_set_desc(dev);
-
switch (ctlr->chip->cfg1) {
case ATI_PATA:
ctlr->chipinit = ata_ati_chipinit;
@@ -118,13 +113,14 @@
ctlr->chipinit = ata_sii_chipinit;
break;
case ATI_AHCI:
- if (force_ahci == 1 || pci_get_subclass(dev) != PCIS_STORAGE_IDE)
- ctlr->chipinit = ata_ahci_chipinit;
- else
- ctlr->chipinit = ata_ati_chipinit;
+ if (pci_get_subclass(dev) != PCIS_STORAGE_IDE)
+ return (ENXIO);
+ ctlr->chipinit = ata_ati_chipinit;
break;
}
- return (BUS_PROBE_DEFAULT);
+
+ ata_set_desc(dev);
+ return (BUS_PROBE_LOW_PRIORITY);
}
static int
@@ -265,5 +261,4 @@
}
ATA_DECLARE_DRIVER(ata_ati);
-MODULE_DEPEND(ata_ati, ata_ahci, 1, 1, 1);
MODULE_DEPEND(ata_ati, ata_sii, 1, 1, 1);
Modified: trunk/sys/dev/ata/chipsets/ata-cenatek.c
===================================================================
--- trunk/sys/dev/ata/chipsets/ata-cenatek.c 2018-05-28 00:25:20 UTC (rev 10127)
+++ trunk/sys/dev/ata/chipsets/ata-cenatek.c 2018-05-28 00:27:43 UTC (rev 10128)
@@ -1,5 +1,6 @@
+/* $MidnightBSD$ */
/*-
- * Copyright (c) 1998 - 2008 S\xF8ren Schmidt <sos at FreeBSD.org>
+ * Copyright (c) 1998 - 2008 Søren Schmidt <sos at FreeBSD.org>
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
@@ -25,9 +26,8 @@
*/
#include <sys/cdefs.h>
-__MBSDID("$MidnightBSD$");
+__FBSDID("$FreeBSD: stable/10/sys/dev/ata/chipsets/ata-cenatek.c 281140 2015-04-06 08:23:06Z mav $");
-#include "opt_ata.h"
#include <sys/param.h>
#include <sys/module.h>
#include <sys/systm.h>
@@ -64,7 +64,7 @@
ctlr->chipinit = ata_generic_chipinit;
device_set_desc(dev, "Cenatek Rocket Drive controller");
- return (BUS_PROBE_DEFAULT);
+ return (BUS_PROBE_LOW_PRIORITY);
}
ATA_DECLARE_DRIVER(ata_cenatek);
Modified: trunk/sys/dev/ata/chipsets/ata-cypress.c
===================================================================
--- trunk/sys/dev/ata/chipsets/ata-cypress.c 2018-05-28 00:25:20 UTC (rev 10127)
+++ trunk/sys/dev/ata/chipsets/ata-cypress.c 2018-05-28 00:27:43 UTC (rev 10128)
@@ -1,5 +1,6 @@
+/* $MidnightBSD$ */
/*-
- * Copyright (c) 1998 - 2008 S\xF8ren Schmidt <sos at FreeBSD.org>
+ * Copyright (c) 1998 - 2008 Søren Schmidt <sos at FreeBSD.org>
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
@@ -25,9 +26,8 @@
*/
#include <sys/cdefs.h>
-__MBSDID("$MidnightBSD$");
+__FBSDID("$FreeBSD: stable/10/sys/dev/ata/chipsets/ata-cypress.c 281140 2015-04-06 08:23:06Z mav $");
-#include "opt_ata.h"
#include <sys/param.h>
#include <sys/module.h>
#include <sys/systm.h>
@@ -76,7 +76,7 @@
pci_get_subclass(dev) == PCIS_STORAGE_IDE) {
device_set_desc(dev, "Cypress 82C693 ATA controller");
ctlr->chipinit = ata_cypress_chipinit;
- return (BUS_PROBE_DEFAULT);
+ return (BUS_PROBE_LOW_PRIORITY);
}
return ENXIO;
}
Modified: trunk/sys/dev/ata/chipsets/ata-cyrix.c
===================================================================
--- trunk/sys/dev/ata/chipsets/ata-cyrix.c 2018-05-28 00:25:20 UTC (rev 10127)
+++ trunk/sys/dev/ata/chipsets/ata-cyrix.c 2018-05-28 00:27:43 UTC (rev 10128)
@@ -1,5 +1,6 @@
+/* $MidnightBSD$ */
/*-
- * Copyright (c) 1998 - 2008 S\xF8ren Schmidt <sos at FreeBSD.org>
+ * Copyright (c) 1998 - 2008 Søren Schmidt <sos at FreeBSD.org>
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
@@ -25,9 +26,8 @@
*/
#include <sys/cdefs.h>
-__MBSDID("$MidnightBSD$");
+__FBSDID("$FreeBSD: stable/10/sys/dev/ata/chipsets/ata-cyrix.c 281140 2015-04-06 08:23:06Z mav $");
-#include "opt_ata.h"
#include <sys/param.h>
#include <sys/module.h>
#include <sys/systm.h>
@@ -67,7 +67,7 @@
if (pci_get_devid(dev) == ATA_CYRIX_5530) {
device_set_desc(dev, "Cyrix 5530 ATA33 controller");
ctlr->chipinit = ata_cyrix_chipinit;
- return (BUS_PROBE_DEFAULT);
+ return (BUS_PROBE_LOW_PRIORITY);
}
return ENXIO;
}
Added: trunk/sys/dev/ata/chipsets/ata-fsl.c
===================================================================
--- trunk/sys/dev/ata/chipsets/ata-fsl.c (rev 0)
+++ trunk/sys/dev/ata/chipsets/ata-fsl.c 2018-05-28 00:27:43 UTC (rev 10128)
@@ -0,0 +1,242 @@
+/* $MidnightBSD$ */
+/*-
+ * Copyright (c) 2012 The FreeBSD Foundation
+ * All rights reserved.
+ *
+ * This software was developed by Oleksandr Rybalko under sponsorship
+ * from the FreeBSD Foundation.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ */
+
+#include <sys/cdefs.h>
+__FBSDID("$FreeBSD: stable/10/sys/dev/ata/chipsets/ata-fsl.c 281140 2015-04-06 08:23:06Z mav $");
+
+#include <sys/param.h>
+#include <sys/module.h>
+#include <sys/systm.h>
+#include <sys/kernel.h>
+#include <sys/ata.h>
+#include <sys/bus.h>
+#include <sys/endian.h>
+#include <sys/malloc.h>
+#include <sys/lock.h>
+#include <sys/mutex.h>
+#include <sys/sema.h>
+#include <sys/taskqueue.h>
+#include <vm/uma.h>
+#include <machine/stdarg.h>
+#include <machine/resource.h>
+#include <machine/bus.h>
+#include <sys/rman.h>
+#include <dev/pci/pcivar.h>
+#include <dev/pci/pcireg.h>
+#include <dev/ata/ata-all.h>
+#include <dev/ata/ata-pci.h>
+#include <ata_if.h>
+
+#include <dev/fdt/fdt_common.h>
+#include <dev/ofw/openfirm.h>
+#include <dev/ofw/ofw_bus.h>
+#include <dev/ofw/ofw_bus_subr.h>
+
+#include <machine/fdt.h>
+
+/* local prototypes */
+static int imx_ata_ch_attach(device_t dev);
+static int imx_ata_setmode(device_t dev, int target, int mode);
+
+static int
+imx_ata_probe(device_t dev)
+{
+ struct ata_pci_controller *ctrl;
+
+ if (!ofw_bus_status_okay(dev))
+ return (ENXIO);
+
+ if (!ofw_bus_is_compatible(dev, "fsl,imx51-ata") &&
+ !ofw_bus_is_compatible(dev, "fsl,imx53-ata"))
+ return (ENXIO);
+
+ ctrl = device_get_softc(dev);
+
+ device_set_desc(dev, "Freescale Integrated PATA Controller");
+ return (BUS_PROBE_LOW_PRIORITY);
+}
+
+static void
+imx_ata_intr(void *data)
+{
+ struct ata_pci_controller *ctrl = data;
+
+ bus_write_2(ctrl->r_res1, 0x28, bus_read_2(ctrl->r_res1, 0x28));
+ ctrl->interrupt[0].function(ctrl->interrupt[0].argument);
+}
+
+static int
+imx_ata_attach(device_t dev)
+{
+ struct ata_pci_controller *ctrl;
+ device_t child;
+ int unit;
+
+ ctrl = device_get_softc(dev);
+ /* do chipset specific setups only needed once */
+ ctrl->legacy = ata_legacy(dev);
+ ctrl->channels = 1;
+ ctrl->ichannels = -1;
+ ctrl->ch_attach = ata_pci_ch_attach;
+ ctrl->ch_detach = ata_pci_ch_detach;
+ ctrl->dev = dev;
+
+ ctrl->r_type1 = SYS_RES_MEMORY;
+ ctrl->r_rid1 = 0;
+ ctrl->r_res1 = bus_alloc_resource_any(dev, ctrl->r_type1,
+ &ctrl->r_rid1, RF_ACTIVE);
+
+ if (ata_setup_interrupt(dev, imx_ata_intr)) {
+ device_printf(dev, "failed to setup interrupt\n");
+ return ENXIO;
+ }
+
+ ctrl->channels = 1;
+
+ ctrl->ch_attach = imx_ata_ch_attach;
+ ctrl->setmode = imx_ata_setmode;
+
+ /* attach all channels on this controller */
+ unit = 0;
+ child = device_add_child(dev, "ata", ((unit == 0) && ctrl->legacy) ?
+ unit : devclass_find_free_unit(ata_devclass, 2));
+ if (child == NULL)
+ device_printf(dev, "failed to add ata child device\n");
+ else
+ device_set_ivars(child, (void *)(intptr_t)unit);
+
+ bus_generic_attach(dev);
+ return 0;
+}
+
+static int
+imx_ata_ch_attach(device_t dev)
+{
+ struct ata_pci_controller *ctrl;
+ struct ata_channel *ch;
+ int i;
+
+ ctrl = device_get_softc(device_get_parent(dev));
+ ch = device_get_softc(dev);
+ for (i = ATA_DATA; i < ATA_MAX_RES; i++)
+ ch->r_io[i].res = ctrl->r_res1;
+
+ bus_write_2(ctrl->r_res1, 0x24, 0x80);
+ DELAY(100);
+ bus_write_2(ctrl->r_res1, 0x24, 0xc0);
+ DELAY(100);
+
+
+ /* Write TIME_OFF/ON/1/2W */
+ bus_write_1(ctrl->r_res1, 0x00, 3);
+ bus_write_1(ctrl->r_res1, 0x01, 3);
+ bus_write_1(ctrl->r_res1, 0x02, (25 + 15) / 15);
+ bus_write_1(ctrl->r_res1, 0x03, (70 + 15) / 15);
+
+ /* Write TIME_2R/AX/RDX/4 */
+ bus_write_1(ctrl->r_res1, 0x04, (70 + 15) / 15);
+ bus_write_1(ctrl->r_res1, 0x05, (50 + 15) / 15 + 2);
+ bus_write_1(ctrl->r_res1, 0x06, 1);
+ bus_write_1(ctrl->r_res1, 0x07, (10 + 15) / 15);
+
+ /* Write TIME_9 ; the rest of timing registers is irrelevant for PIO */
+ bus_write_1(ctrl->r_res1, 0x08, (10 + 15) / 15);
+
+ bus_write_2(ctrl->r_res1, 0x24, 0xc1);
+ DELAY(30000);
+
+ /* setup ATA registers */
+ ch->r_io[ATA_DATA ].offset = 0xa0;
+ ch->r_io[ATA_FEATURE].offset = 0xa4;
+ ch->r_io[ATA_ERROR ].offset = 0xa4;
+ ch->r_io[ATA_COUNT ].offset = 0xa8;
+ ch->r_io[ATA_SECTOR ].offset = 0xac;
+ ch->r_io[ATA_CYL_LSB].offset = 0xb0;
+ ch->r_io[ATA_CYL_MSB].offset = 0xb4;
+ ch->r_io[ATA_DRIVE ].offset = 0xb8;
+ ch->r_io[ATA_COMMAND].offset = 0xbc;
+
+ ch->r_io[ATA_STATUS ].offset = 0xbc;
+ ch->r_io[ATA_ALTSTAT].offset = 0xd8;
+ ch->r_io[ATA_CONTROL].offset = 0xd8;
+
+ ata_pci_hw(dev);
+
+ ch->flags |= ATA_NO_SLAVE;
+ ch->flags |= ATA_USE_16BIT;
+ ch->flags |= ATA_CHECKS_CABLE;
+ ch->flags |= ATA_KNOWN_PRESENCE;
+
+ /* Clear pending interrupts. */
+ bus_write_2(ctrl->r_res1, 0x28, 0xf8);
+ /* Enable all, but Idle interrupts. */
+ bus_write_2(ctrl->r_res1, 0x2c, 0x88);
+
+ return 0;
+}
+
+static int
+imx_ata_setmode(device_t dev, int target, int mode)
+{
+
+ return (min(mode, ATA_PIO4));
+}
+
+static device_method_t imx_ata_methods[] = {
+ DEVMETHOD(device_probe, imx_ata_probe),
+ DEVMETHOD(device_attach, imx_ata_attach),
+ DEVMETHOD(device_detach, ata_pci_detach),
+ DEVMETHOD(device_suspend, ata_pci_suspend),
+ DEVMETHOD(device_resume, ata_pci_resume),
+ DEVMETHOD(device_shutdown, bus_generic_shutdown),
+ DEVMETHOD(bus_read_ivar, ata_pci_read_ivar),
+ DEVMETHOD(bus_write_ivar, ata_pci_write_ivar),
+ DEVMETHOD(bus_alloc_resource, ata_pci_alloc_resource),
+ DEVMETHOD(bus_release_resource, ata_pci_release_resource),
+ DEVMETHOD(bus_activate_resource, bus_generic_activate_resource),
+ DEVMETHOD(bus_deactivate_resource, bus_generic_deactivate_resource),
+ DEVMETHOD(bus_setup_intr, ata_pci_setup_intr),
+ DEVMETHOD(bus_teardown_intr, ata_pci_teardown_intr),
+ DEVMETHOD(pci_read_config, ata_pci_read_config),
+ DEVMETHOD(pci_write_config, ata_pci_write_config),
+ DEVMETHOD(bus_print_child, ata_pci_print_child),
+ DEVMETHOD(bus_child_location_str, ata_pci_child_location_str),
+ DEVMETHOD_END
+};
+static driver_t imx_ata_driver = {
+ "atapci",
+ imx_ata_methods,
+ sizeof(struct ata_pci_controller)
+};
+DRIVER_MODULE(imx_ata, simplebus, imx_ata_driver, ata_pci_devclass, NULL,
+ NULL);
+MODULE_VERSION(imx_ata, 1);
+MODULE_DEPEND(imx_ata, ata, 1, 1, 1);
+MODULE_DEPEND(imx_ata, atapci, 1, 1, 1);
Property changes on: trunk/sys/dev/ata/chipsets/ata-fsl.c
___________________________________________________________________
Added: svn:eol-style
## -0,0 +1 ##
+native
\ No newline at end of property
Added: svn:keywords
## -0,0 +1 ##
+MidnightBSD=%H
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+text/plain
\ No newline at end of property
Modified: trunk/sys/dev/ata/chipsets/ata-highpoint.c
===================================================================
--- trunk/sys/dev/ata/chipsets/ata-highpoint.c 2018-05-28 00:25:20 UTC (rev 10127)
+++ trunk/sys/dev/ata/chipsets/ata-highpoint.c 2018-05-28 00:27:43 UTC (rev 10128)
@@ -1,5 +1,6 @@
+/* $MidnightBSD$ */
/*-
- * Copyright (c) 1998 - 2008 S\xF8ren Schmidt <sos at FreeBSD.org>
+ * Copyright (c) 1998 - 2008 Søren Schmidt <sos at FreeBSD.org>
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
@@ -25,9 +26,8 @@
*/
#include <sys/cdefs.h>
-__MBSDID("$MidnightBSD$");
+__FBSDID("$FreeBSD: stable/10/sys/dev/ata/chipsets/ata-highpoint.c 281140 2015-04-06 08:23:06Z mav $");
-#include "opt_ata.h"
#include <sys/param.h>
#include <sys/module.h>
#include <sys/systm.h>
@@ -104,7 +104,7 @@
device_set_desc_copy(dev, buffer);
ctlr->chip = idx;
ctlr->chipinit = ata_highpoint_chipinit;
- return (BUS_PROBE_DEFAULT);
+ return (BUS_PROBE_LOW_PRIORITY);
}
static int
Modified: trunk/sys/dev/ata/chipsets/ata-intel.c
===================================================================
--- trunk/sys/dev/ata/chipsets/ata-intel.c 2018-05-28 00:25:20 UTC (rev 10127)
+++ trunk/sys/dev/ata/chipsets/ata-intel.c 2018-05-28 00:27:43 UTC (rev 10128)
@@ -1,5 +1,6 @@
+/* $MidnightBSD$ */
/*-
- * Copyright (c) 1998 - 2008 S\xF8ren Schmidt <sos at FreeBSD.org>
+ * Copyright (c) 1998 - 2008 Søren Schmidt <sos at FreeBSD.org>
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
@@ -25,9 +26,8 @@
*/
#include <sys/cdefs.h>
-__MBSDID("$MidnightBSD$");
+__FBSDID("$FreeBSD: stable/10/sys/dev/ata/chipsets/ata-intel.c 291456 2015-11-29 17:14:05Z mav $");
-#include "opt_ata.h"
#include <sys/param.h>
#include <sys/module.h>
#include <sys/systm.h>
@@ -81,7 +81,6 @@
static void ata_intel_31244_reset(device_t dev);
/* misc defines */
-#define INTEL_AHCI 1
#define INTEL_ICH5 2
#define INTEL_6CH 4
#define INTEL_6CH2 8
@@ -128,105 +127,69 @@
{ ATA_I6300ESB_S1, 0, INTEL_ICH5, 2, ATA_SA150, "6300ESB" },
{ ATA_I6300ESB_R1, 0, INTEL_ICH5, 2, ATA_SA150, "6300ESB" },
{ ATA_I82801FB, 0, 0, 2, ATA_UDMA5, "ICH6" },
- { ATA_I82801FB_S1, 0, INTEL_AHCI, 0, ATA_SA150, "ICH6" },
- { ATA_I82801FB_R1, 0, INTEL_AHCI, 0, ATA_SA150, "ICH6" },
- { ATA_I82801FBM, 0, INTEL_AHCI, 0, ATA_SA150, "ICH6M" },
+ { ATA_I82801FB_S1, 0, 0, 0, ATA_SA150, "ICH6" },
+ { ATA_I82801FB_R1, 0, 0, 0, ATA_SA150, "ICH6" },
+ { ATA_I82801FBM, 0, 0, 0, ATA_SA150, "ICH6M" },
{ ATA_I82801GB, 0, 0, 1, ATA_UDMA5, "ICH7" },
{ ATA_I82801GB_S1, 0, INTEL_ICH7, 0, ATA_SA300, "ICH7" },
- { ATA_I82801GB_R1, 0, INTEL_AHCI, 0, ATA_SA300, "ICH7" },
- { ATA_I82801GB_AH, 0, INTEL_AHCI, 0, ATA_SA300, "ICH7" },
{ ATA_I82801GBM_S1, 0, INTEL_ICH7, 0, ATA_SA150, "ICH7M" },
- { ATA_I82801GBM_R1, 0, INTEL_AHCI, 0, ATA_SA150, "ICH7M" },
- { ATA_I82801GBM_AH, 0, INTEL_AHCI, 0, ATA_SA150, "ICH7M" },
{ ATA_I63XXESB2, 0, 0, 1, ATA_UDMA5, "63XXESB2" },
{ ATA_I63XXESB2_S1, 0, 0, 0, ATA_SA300, "63XXESB2" },
- { ATA_I63XXESB2_S2, 0, INTEL_AHCI, 0, ATA_SA300, "63XXESB2" },
- { ATA_I63XXESB2_R1, 0, INTEL_AHCI, 0, ATA_SA300, "63XXESB2" },
- { ATA_I63XXESB2_R2, 0, INTEL_AHCI, 0, ATA_SA300, "63XXESB2" },
{ ATA_I82801HB_S1, 0, INTEL_6CH, 0, ATA_SA300, "ICH8" },
{ ATA_I82801HB_S2, 0, INTEL_6CH2, 0, ATA_SA300, "ICH8" },
- { ATA_I82801HB_R1, 0, INTEL_AHCI, 0, ATA_SA300, "ICH8" },
- { ATA_I82801HB_AH4, 0, INTEL_AHCI, 0, ATA_SA300, "ICH8" },
- { ATA_I82801HB_AH6, 0, INTEL_AHCI, 0, ATA_SA300, "ICH8" },
{ ATA_I82801HBM, 0, 0, 1, ATA_UDMA5, "ICH8M" },
{ ATA_I82801HBM_S1, 0, INTEL_6CH, 0, ATA_SA300, "ICH8M" },
- { ATA_I82801HBM_S2, 0, INTEL_AHCI, 0, ATA_SA300, "ICH8M" },
- { ATA_I82801HBM_S3, 0, INTEL_AHCI, 0, ATA_SA300, "ICH8M" },
{ ATA_I82801IB_S1, 0, INTEL_6CH, 0, ATA_SA300, "ICH9" },
{ ATA_I82801IB_S2, 0, INTEL_6CH2, 0, ATA_SA300, "ICH9" },
{ ATA_I82801IB_S3, 0, INTEL_6CH2, 0, ATA_SA300, "ICH9" },
- { ATA_I82801IB_AH4, 0, INTEL_AHCI, 0, ATA_SA300, "ICH9" },
- { ATA_I82801IB_AH6, 0, INTEL_AHCI, 0, ATA_SA300, "ICH9" },
- { ATA_I82801IB_R1, 0, INTEL_AHCI, 0, ATA_SA300, "ICH9" },
{ ATA_I82801IBM_S1, 0, INTEL_6CH2, 0, ATA_SA300, "ICH9M" },
- { ATA_I82801IBM_AH, 0, INTEL_AHCI, 0, ATA_SA300, "ICH9M" },
- { ATA_I82801IBM_R1, 0, INTEL_AHCI, 0, ATA_SA300, "ICH9M" },
{ ATA_I82801IBM_S2, 0, INTEL_6CH2, 0, ATA_SA300, "ICH9M" },
{ ATA_I82801JIB_S1, 0, INTEL_6CH, 0, ATA_SA300, "ICH10" },
- { ATA_I82801JIB_AH, 0, INTEL_AHCI, 0, ATA_SA300, "ICH10" },
- { ATA_I82801JIB_R1, 0, INTEL_AHCI, 0, ATA_SA300, "ICH10" },
{ ATA_I82801JIB_S2, 0, INTEL_6CH2, 0, ATA_SA300, "ICH10" },
{ ATA_I82801JD_S1, 0, INTEL_6CH, 0, ATA_SA300, "ICH10" },
- { ATA_I82801JD_AH, 0, INTEL_AHCI, 0, ATA_SA300, "ICH10" },
- { ATA_I82801JD_R1, 0, INTEL_AHCI, 0, ATA_SA300, "ICH10" },
{ ATA_I82801JD_S2, 0, INTEL_6CH2, 0, ATA_SA300, "ICH10" },
{ ATA_I82801JI_S1, 0, INTEL_6CH, 0, ATA_SA300, "ICH10" },
- { ATA_I82801JI_AH, 0, INTEL_AHCI, 0, ATA_SA300, "ICH10" },
- { ATA_I82801JI_R1, 0, INTEL_AHCI, 0, ATA_SA300, "ICH10" },
{ ATA_I82801JI_S2, 0, INTEL_6CH2, 0, ATA_SA300, "ICH10" },
{ ATA_5Series_S1, 0, INTEL_6CH, 0, ATA_SA300, "5 Series/3400 Series PCH" },
{ ATA_5Series_S2, 0, INTEL_6CH2, 0, ATA_SA300, "5 Series/3400 Series PCH" },
- { ATA_5Series_AH1, 0, INTEL_AHCI, 0, ATA_SA300, "5 Series/3400 Series PCH" },
- { ATA_5Series_AH2, 0, INTEL_AHCI, 0, ATA_SA300, "5 Series/3400 Series PCH" },
- { ATA_5Series_R1, 0, INTEL_AHCI, 0, ATA_SA300, "5 Series/3400 Series PCH" },
{ ATA_5Series_S3, 0, INTEL_6CH2, 0, ATA_SA300, "5 Series/3400 Series PCH" },
{ ATA_5Series_S4, 0, INTEL_6CH, 0, ATA_SA300, "5 Series/3400 Series PCH" },
- { ATA_5Series_AH3, 0, INTEL_AHCI, 0, ATA_SA300, "5 Series/3400 Series PCH" },
- { ATA_5Series_R2, 0, INTEL_AHCI, 0, ATA_SA300, "5 Series/3400 Series PCH" },
{ ATA_5Series_S5, 0, INTEL_6CH2, 0, ATA_SA300, "5 Series/3400 Series PCH" },
{ ATA_5Series_S6, 0, INTEL_6CH, 0, ATA_SA300, "5 Series/3400 Series PCH" },
- { ATA_5Series_AH4, 0, INTEL_AHCI, 0, ATA_SA300, "5 Series/3400 Series PCH" },
- { ATA_CPT_S1, 0, INTEL_6CH, 0, ATA_SA300, "Cougar Point" },
- { ATA_CPT_S2, 0, INTEL_6CH, 0, ATA_SA300, "Cougar Point" },
- { ATA_CPT_AH1, 0, INTEL_AHCI, 0, ATA_SA300, "Cougar Point" },
- { ATA_CPT_AH2, 0, INTEL_AHCI, 0, ATA_SA300, "Cougar Point" },
- { ATA_CPT_R1, 0, INTEL_AHCI, 0, ATA_SA300, "Cougar Point" },
- { ATA_CPT_R2, 0, INTEL_AHCI, 0, ATA_SA300, "Cougar Point" },
+ { ATA_CPT_S1, 0, INTEL_6CH, 0, ATA_SA600, "Cougar Point" },
+ { ATA_CPT_S2, 0, INTEL_6CH, 0, ATA_SA600, "Cougar Point" },
{ ATA_CPT_S3, 0, INTEL_6CH2, 0, ATA_SA300, "Cougar Point" },
{ ATA_CPT_S4, 0, INTEL_6CH2, 0, ATA_SA300, "Cougar Point" },
- { ATA_PBG_S1, 0, INTEL_6CH, 0, ATA_SA300, "Patsburg" },
- { ATA_PBG_AH1, 0, INTEL_AHCI, 0, ATA_SA300, "Patsburg" },
- { ATA_PBG_R1, 0, INTEL_AHCI, 0, ATA_SA300, "Patsburg" },
- { ATA_PBG_R2, 0, INTEL_AHCI, 0, ATA_SA300, "Patsburg" },
- { ATA_PBG_R3, 0, INTEL_AHCI, 0, ATA_SA300, "Patsburg" },
+ { ATA_PBG_S1, 0, INTEL_6CH, 0, ATA_SA600, "Patsburg" },
{ ATA_PBG_S2, 0, INTEL_6CH2, 0, ATA_SA300, "Patsburg" },
- { ATA_PPT_S1, 0, INTEL_6CH, 0, ATA_SA300, "Panther Point" },
- { ATA_PPT_S2, 0, INTEL_6CH, 0, ATA_SA300, "Panther Point" },
- { ATA_PPT_AH1, 0, INTEL_AHCI, 0, ATA_SA300, "Panther Point" },
- { ATA_PPT_AH2, 0, INTEL_AHCI, 0, ATA_SA300, "Panther Point" },
- { ATA_PPT_R1, 0, INTEL_AHCI, 0, ATA_SA300, "Panther Point" },
- { ATA_PPT_R2, 0, INTEL_AHCI, 0, ATA_SA300, "Panther Point" },
- { ATA_PPT_R3, 0, INTEL_AHCI, 0, ATA_SA300, "Panther Point" },
- { ATA_PPT_R4, 0, INTEL_AHCI, 0, ATA_SA300, "Panther Point" },
+ { ATA_PPT_S1, 0, INTEL_6CH, 0, ATA_SA600, "Panther Point" },
+ { ATA_PPT_S2, 0, INTEL_6CH, 0, ATA_SA600, "Panther Point" },
{ ATA_PPT_S3, 0, INTEL_6CH2, 0, ATA_SA300, "Panther Point" },
{ ATA_PPT_S4, 0, INTEL_6CH2, 0, ATA_SA300, "Panther Point" },
- { ATA_PPT_R5, 0, INTEL_AHCI, 0, ATA_SA300, "Panther Point" },
- { ATA_PPT_R6, 0, INTEL_AHCI, 0, ATA_SA300, "Panther Point" },
- { ATA_LPT_S1, 0, INTEL_6CH, 0, ATA_SA300, "Lynx Point" },
- { ATA_LPT_S2, 0, INTEL_6CH, 0, ATA_SA300, "Lynx Point" },
- { ATA_LPT_AH1, 0, INTEL_AHCI, 0, ATA_SA300, "Lynx Point" },
- { ATA_LPT_AH2, 0, INTEL_AHCI, 0, ATA_SA300, "Lynx Point" },
- { ATA_LPT_R1, 0, INTEL_AHCI, 0, ATA_SA300, "Lynx Point" },
- { ATA_LPT_R2, 0, INTEL_AHCI, 0, ATA_SA300, "Lynx Point" },
- { ATA_LPT_R3, 0, INTEL_AHCI, 0, ATA_SA300, "Lynx Point" },
- { ATA_LPT_R4, 0, INTEL_AHCI, 0, ATA_SA300, "Lynx Point" },
- { ATA_LPT_S3, 0, INTEL_6CH2, 0, ATA_SA300, "Lynx Point" },
- { ATA_LPT_S4, 0, INTEL_6CH2, 0, ATA_SA300, "Lynx Point" },
- { ATA_LPT_R5, 0, INTEL_AHCI, 0, ATA_SA300, "Lynx Point" },
- { ATA_LPT_R6, 0, INTEL_AHCI, 0, ATA_SA300, "Lynx Point" },
+ { ATA_AVOTON_S1, 0, INTEL_6CH, 0, ATA_SA600, "Avoton" },
+ { ATA_AVOTON_S2, 0, INTEL_6CH, 0, ATA_SA600, "Avoton" },
+ { ATA_AVOTON_S3, 0, INTEL_6CH2, 0, ATA_SA300, "Avoton" },
+ { ATA_AVOTON_S4, 0, INTEL_6CH2, 0, ATA_SA300, "Avoton" },
+ { ATA_LPT_S1, 0, INTEL_6CH, 0, ATA_SA600, "Lynx Point" },
+ { ATA_LPT_S2, 0, INTEL_6CH, 0, ATA_SA600, "Lynx Point" },
+ { ATA_LPT_S3, 0, INTEL_6CH2, 0, ATA_SA600, "Lynx Point" },
+ { ATA_LPT_S4, 0, INTEL_6CH2, 0, ATA_SA600, "Lynx Point" },
+ { ATA_WCPT_S1, 0, INTEL_6CH, 0, ATA_SA600, "Wildcat Point" },
+ { ATA_WCPT_S2, 0, INTEL_6CH, 0, ATA_SA600, "Wildcat Point" },
+ { ATA_WCPT_S3, 0, INTEL_6CH2, 0, ATA_SA600, "Wildcat Point" },
+ { ATA_WCPT_S4, 0, INTEL_6CH2, 0, ATA_SA600, "Wildcat Point" },
+ { ATA_WELLS_S1, 0, INTEL_6CH, 0, ATA_SA600, "Wellsburg" },
+ { ATA_WELLS_S2, 0, INTEL_6CH2, 0, ATA_SA600, "Wellsburg" },
+ { ATA_WELLS_S3, 0, INTEL_6CH, 0, ATA_SA600, "Wellsburg" },
+ { ATA_WELLS_S4, 0, INTEL_6CH2, 0, ATA_SA600, "Wellsburg" },
+ { ATA_LPTLP_S1, 0, INTEL_6CH, 0, ATA_SA600, "Lynx Point-LP" },
+ { ATA_LPTLP_S2, 0, INTEL_6CH, 0, ATA_SA600, "Lynx Point-LP" },
+ { ATA_LPTLP_S3, 0, INTEL_6CH2, 0, ATA_SA300, "Lynx Point-LP" },
+ { ATA_LPTLP_S4, 0, INTEL_6CH2, 0, ATA_SA300, "Lynx Point-LP" },
{ ATA_I31244, 0, 0, 2, ATA_SA150, "31244" },
{ ATA_ISCH, 0, 0, 1, ATA_UDMA5, "SCH" },
- { ATA_DH89XXCC, 0, INTEL_AHCI, 0, ATA_SA300, "DH89xxCC" },
+ { ATA_COLETOCRK_S1, 0, INTEL_6CH2, 0, ATA_SA300, "COLETOCRK" },
+ { ATA_COLETOCRK_S2, 0, INTEL_6CH2, 0, ATA_SA300, "COLETOCRK" },
{ 0, 0, 0, 0, 0, 0}};
if (pci_get_vendor(dev) != ATA_INTEL_ID)
@@ -238,7 +201,7 @@
ata_set_desc(dev);
ctlr->chipinit = ata_intel_chipinit;
ctlr->chipdeinit = ata_intel_chipdeinit;
- return (BUS_PROBE_DEFAULT);
+ return (BUS_PROBE_LOW_PRIORITY);
}
static int
@@ -300,15 +263,6 @@
ctlr->ch_detach = ata_pci_ch_detach;
ctlr->reset = ata_intel_reset;
- /*
- * if we have AHCI capability and AHCI or RAID mode enabled
- * in BIOS we try for AHCI mode
- */
- if ((ctlr->chip->cfg1 & INTEL_AHCI) &&
- (pci_read_config(dev, 0x90, 1) & 0xc0) &&
- (ata_ahci_chipinit(dev) != ENXIO))
- return 0;
-
/* BAR(5) may point to SATA interface registers */
if ((ctlr->chip->cfg1 & INTEL_ICH7)) {
ctlr->r_type2 = SYS_RES_MEMORY;
@@ -441,6 +395,8 @@
}
} else
ctlr->setmode = ata_intel_new_setmode;
+ if (ctlr->chip->max_dma >= ATA_SA600)
+ ch->flags |= ATA_USE_16BIT;
} else if (ctlr->chip->chipid != ATA_ISCH)
ch->flags |= ATA_CHECKS_CABLE;
return (0);
@@ -467,7 +423,7 @@
mask |= (1 << smap[1]);
pci_write_config(parent, 0x92,
pci_read_config(parent, 0x92, 2) & ~mask, 2);
- DELAY(10);
+ DELAY(100);
pci_write_config(parent, 0x92,
pci_read_config(parent, 0x92, 2) | mask, 2);
@@ -933,9 +889,6 @@
ata_intel_31244_tf_write(struct ata_request *request)
{
struct ata_channel *ch = device_get_softc(request->parent);
-#ifndef ATA_CAM
- struct ata_device *atadev = device_get_softc(request->dev);
-#endif
if (request->flags & ATA_R_48BIT) {
ATA_IDX_OUTW(ch, ATA_FEATURE, request->u.ata.feature);
@@ -951,29 +904,6 @@
else {
ATA_IDX_OUTB(ch, ATA_FEATURE, request->u.ata.feature);
ATA_IDX_OUTB(ch, ATA_COUNT, request->u.ata.count);
-#ifndef ATA_CAM
- if (atadev->flags & ATA_D_USE_CHS) {
- int heads, sectors;
-
- if (atadev->param.atavalid & ATA_FLAG_54_58) {
- heads = atadev->param.current_heads;
- sectors = atadev->param.current_sectors;
- }
- else {
- heads = atadev->param.heads;
- sectors = atadev->param.sectors;
- }
- ATA_IDX_OUTB(ch, ATA_SECTOR, (request->u.ata.lba % sectors)+1);
- ATA_IDX_OUTB(ch, ATA_CYL_LSB,
- (request->u.ata.lba / (sectors * heads)));
- ATA_IDX_OUTB(ch, ATA_CYL_MSB,
- (request->u.ata.lba / (sectors * heads)) >> 8);
- ATA_IDX_OUTB(ch, ATA_DRIVE, ATA_D_IBM | ATA_DEV(request->unit) |
- (((request->u.ata.lba% (sectors * heads)) /
- sectors) & 0xf));
- }
- else {
-#endif
ATA_IDX_OUTB(ch, ATA_SECTOR, request->u.ata.lba);
ATA_IDX_OUTB(ch, ATA_CYL_LSB, request->u.ata.lba >> 8);
ATA_IDX_OUTB(ch, ATA_CYL_MSB, request->u.ata.lba >> 16);
@@ -980,9 +910,6 @@
ATA_IDX_OUTB(ch, ATA_DRIVE,
ATA_D_IBM | ATA_D_LBA | ATA_DEV(request->unit) |
((request->u.ata.lba >> 24) & 0x0f));
-#ifndef ATA_CAM
- }
-#endif
}
}
@@ -998,4 +925,3 @@
}
ATA_DECLARE_DRIVER(ata_intel);
-MODULE_DEPEND(ata_intel, ata_ahci, 1, 1, 1);
Modified: trunk/sys/dev/ata/chipsets/ata-ite.c
===================================================================
--- trunk/sys/dev/ata/chipsets/ata-ite.c 2018-05-28 00:25:20 UTC (rev 10127)
+++ trunk/sys/dev/ata/chipsets/ata-ite.c 2018-05-28 00:27:43 UTC (rev 10128)
@@ -1,5 +1,6 @@
+/* $MidnightBSD$ */
/*-
- * Copyright (c) 1998 - 2008 S\xF8ren Schmidt <sos at FreeBSD.org>
+ * Copyright (c) 1998 - 2008 Søren Schmidt <sos at FreeBSD.org>
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
@@ -25,9 +26,8 @@
*/
#include <sys/cdefs.h>
-__MBSDID("$MidnightBSD$");
+__FBSDID("$FreeBSD: stable/10/sys/dev/ata/chipsets/ata-ite.c 281140 2015-04-06 08:23:06Z mav $");
-#include "opt_ata.h"
#include <sys/param.h>
#include <sys/module.h>
#include <sys/systm.h>
@@ -78,7 +78,7 @@
ata_set_desc(dev);
ctlr->chipinit = ata_ite_chipinit;
- return (BUS_PROBE_DEFAULT);
+ return (BUS_PROBE_LOW_PRIORITY);
}
static int
@@ -119,9 +119,7 @@
error = ata_pci_ch_attach(dev);
ch->flags |= ATA_CHECKS_CABLE;
-#ifdef ATA_CAM
ch->flags |= ATA_NO_ATAPI_DMA;
-#endif
return (error);
}
Modified: trunk/sys/dev/ata/chipsets/ata-jmicron.c
===================================================================
--- trunk/sys/dev/ata/chipsets/ata-jmicron.c 2018-05-28 00:25:20 UTC (rev 10127)
+++ trunk/sys/dev/ata/chipsets/ata-jmicron.c 2018-05-28 00:27:43 UTC (rev 10128)
@@ -1,5 +1,6 @@
+/* $MidnightBSD$ */
/*-
- * Copyright (c) 1998 - 2008 S\xF8ren Schmidt <sos at FreeBSD.org>
+ * Copyright (c) 1998 - 2008 Søren Schmidt <sos at FreeBSD.org>
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
@@ -25,9 +26,8 @@
*/
#include <sys/cdefs.h>
-__MBSDID("$MidnightBSD$");
+__FBSDID("$FreeBSD: stable/10/sys/dev/ata/chipsets/ata-jmicron.c 287016 2015-08-22 07:32:47Z mav $");
-#include "opt_ata.h"
#include <sys/param.h>
#include <sys/module.h>
#include <sys/systm.h>
@@ -72,6 +72,7 @@
{ ATA_JMB365, 0, 1, 2, ATA_UDMA6, "JMB365" },
{ ATA_JMB366, 0, 2, 2, ATA_UDMA6, "JMB366" },
{ ATA_JMB368, 0, 0, 1, ATA_UDMA6, "JMB368" },
+ { ATA_JMB368_2, 0, 0, 1, ATA_UDMA6, "JMB368" },
{ 0, 0, 0, 0, 0, 0}};
char buffer[64];
@@ -86,7 +87,7 @@
device_set_desc_copy(dev, buffer);
ctlr->chip = idx;
ctlr->chipinit = ata_jmicron_chipinit;
- return (BUS_PROBE_DEFAULT);
+ return (BUS_PROBE_LOW_PRIORITY);
}
static int
@@ -100,11 +101,7 @@
/* do we have multiple PCI functions ? */
if (pci_read_config(dev, 0xdf, 1) & 0x40) {
- /* are we on the AHCI part ? */
- if (ata_ahci_chipinit(dev) != ENXIO)
- return 0;
-
- /* otherwise we are on the PATA part */
+ /* If this was not claimed by AHCI, then we are on the PATA part */
ctlr->ch_attach = ata_jmicron_ch_attach;
ctlr->ch_detach = ata_pci_ch_detach;
ctlr->reset = ata_generic_reset;
@@ -160,4 +157,3 @@
}
ATA_DECLARE_DRIVER(ata_jmicron);
-MODULE_DEPEND(ata_jmicron, ata_ahci, 1, 1, 1);
Modified: trunk/sys/dev/ata/chipsets/ata-marvell.c
===================================================================
--- trunk/sys/dev/ata/chipsets/ata-marvell.c 2018-05-28 00:25:20 UTC (rev 10127)
+++ trunk/sys/dev/ata/chipsets/ata-marvell.c 2018-05-28 00:27:43 UTC (rev 10128)
@@ -1,5 +1,6 @@
+/* $MidnightBSD$ */
/*-
- * Copyright (c) 1998 - 2008 S\xF8ren Schmidt <sos at FreeBSD.org>
+ * Copyright (c) 1998 - 2008 Søren Schmidt <sos at FreeBSD.org>
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
@@ -25,9 +26,8 @@
*/
#include <sys/cdefs.h>
-__MBSDID("$MidnightBSD$");
+__FBSDID("$FreeBSD: stable/10/sys/dev/ata/chipsets/ata-marvell.c 287016 2015-08-22 07:32:47Z mav $");
-#include "opt_ata.h"
#include <sys/param.h>
#include <sys/module.h>
#include <sys/systm.h>
@@ -56,20 +56,8 @@
static int ata_marvell_ch_attach(device_t dev);
static int ata_marvell_setmode(device_t dev, int target, int mode);
static int ata_marvell_dummy_chipinit(device_t dev);
-static int ata_marvell_edma_ch_attach(device_t dev);
-static int ata_marvell_edma_ch_detach(device_t dev);
-static int ata_marvell_edma_status(device_t dev);
-static int ata_marvell_edma_begin_transaction(struct ata_request *request);
-static int ata_marvell_edma_end_transaction(struct ata_request *request);
-static void ata_marvell_edma_reset(device_t dev);
-static void ata_marvell_edma_dmasetprd(void *xsc, bus_dma_segment_t *segs, int nsegs, int error);
-static void ata_marvell_edma_dmainit(device_t dev);
/* misc defines */
-#define MV_50XX 50
-#define MV_60XX 60
-#define MV_6042 62
-#define MV_7042 72
#define MV_61XX 61
#define MV_91XX 91
@@ -100,15 +88,7 @@
{
struct ata_pci_controller *ctlr = device_get_softc(dev);
static const struct ata_chip_id ids[] =
- {{ ATA_M88SX5040, 0, 4, MV_50XX, ATA_SA150, "88SX5040" },
- { ATA_M88SX5041, 0, 4, MV_50XX, ATA_SA150, "88SX5041" },
- { ATA_M88SX5080, 0, 8, MV_50XX, ATA_SA150, "88SX5080" },
- { ATA_M88SX5081, 0, 8, MV_50XX, ATA_SA150, "88SX5081" },
- { ATA_M88SX6041, 0, 4, MV_60XX, ATA_SA300, "88SX6041" },
- { ATA_M88SX6042, 0, 4, MV_6042, ATA_SA300, "88SX6042" },
- { ATA_M88SX6081, 0, 8, MV_60XX, ATA_SA300, "88SX6081" },
- { ATA_M88SX7042, 0, 4, MV_7042, ATA_SA300, "88SX7042" },
- { ATA_M88SE6101, 0, 0, MV_61XX, ATA_UDMA6, "88SE6101" },
+ {{ ATA_M88SE6101, 0, 0, MV_61XX, ATA_UDMA6, "88SE6101" },
{ ATA_M88SE6102, 0, 0, MV_61XX, ATA_UDMA6, "88SE6102" },
{ ATA_M88SE6111, 0, 1, MV_61XX, ATA_UDMA6, "88SE6111" },
{ ATA_M88SE6121, 0, 2, MV_61XX, ATA_UDMA6, "88SE6121" },
@@ -127,12 +107,6 @@
ata_set_desc(dev);
switch (ctlr->chip->cfg2) {
- case MV_50XX:
- case MV_60XX:
- case MV_6042:
- case MV_7042:
- ctlr->chipinit = ata_marvell_edma_chipinit;
- break;
case MV_61XX:
ctlr->chipinit = ata_marvell_chipinit;
break;
@@ -140,7 +114,7 @@
ctlr->chipinit = ata_marvell_dummy_chipinit;
break;
}
- return (BUS_PROBE_DEFAULT);
+ return (BUS_PROBE_LOW_PRIORITY);
}
static int
@@ -206,425 +180,4 @@
return (0);
}
-int
-ata_marvell_edma_chipinit(device_t dev)
-{
- struct ata_pci_controller *ctlr = device_get_softc(dev);
-
- if (ata_setup_interrupt(dev, ata_generic_intr))
- return ENXIO;
-
- ctlr->r_type1 = SYS_RES_MEMORY;
- ctlr->r_rid1 = PCIR_BAR(0);
- if (!(ctlr->r_res1 = bus_alloc_resource_any(dev, ctlr->r_type1,
- &ctlr->r_rid1, RF_ACTIVE)))
- return ENXIO;
-
- /* mask all host controller interrupts */
- ATA_OUTL(ctlr->r_res1, 0x01d64, 0x00000000);
-
- /* mask all PCI interrupts */
- ATA_OUTL(ctlr->r_res1, 0x01d5c, 0x00000000);
-
- ctlr->ch_attach = ata_marvell_edma_ch_attach;
- ctlr->ch_detach = ata_marvell_edma_ch_detach;
- ctlr->reset = ata_marvell_edma_reset;
- ctlr->setmode = ata_sata_setmode;
- ctlr->getrev = ata_sata_getrev;
- ctlr->channels = ctlr->chip->cfg1;
-
- /* clear host controller interrupts */
- ATA_OUTL(ctlr->r_res1, 0x20014, 0x00000000);
- if (ctlr->chip->cfg1 > 4)
- ATA_OUTL(ctlr->r_res1, 0x30014, 0x00000000);
-
- /* clear PCI interrupts */
- ATA_OUTL(ctlr->r_res1, 0x01d58, 0x00000000);
-
- /* unmask PCI interrupts we want */
- ATA_OUTL(ctlr->r_res1, 0x01d5c, 0x007fffff);
-
- /* unmask host controller interrupts we want */
- ATA_OUTL(ctlr->r_res1, 0x01d64, 0x000000ff/*HC0*/ | 0x0001fe00/*HC1*/ |
- /*(1<<19) | (1<<20) | (1<<21) |*/(1<<22) | (1<<24) | (0x7f << 25));
-
- return 0;
-}
-
-static int
-ata_marvell_edma_ch_attach(device_t dev)
-{
- struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
- struct ata_channel *ch = device_get_softc(dev);
- u_int64_t work;
- int i;
-
- ata_marvell_edma_dmainit(dev);
- work = ch->dma.work_bus;
- /* clear work area */
- bzero(ch->dma.work, 1024+256);
- bus_dmamap_sync(ch->dma.work_tag, ch->dma.work_map,
- BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
-
- /* set legacy ATA resources */
- for (i = ATA_DATA; i <= ATA_COMMAND; i++) {
- ch->r_io[i].res = ctlr->r_res1;
- ch->r_io[i].offset = 0x02100 + (i << 2) + ATA_MV_EDMA_BASE(ch);
- }
- ch->r_io[ATA_CONTROL].res = ctlr->r_res1;
- ch->r_io[ATA_CONTROL].offset = 0x02120 + ATA_MV_EDMA_BASE(ch);
- ch->r_io[ATA_IDX_ADDR].res = ctlr->r_res1;
- ata_default_registers(dev);
-
- /* set SATA resources */
- switch (ctlr->chip->cfg2) {
- case MV_50XX:
- ch->r_io[ATA_SSTATUS].res = ctlr->r_res1;
- ch->r_io[ATA_SSTATUS].offset = 0x00100 + ATA_MV_HOST_BASE(ch);
- ch->r_io[ATA_SERROR].res = ctlr->r_res1;
- ch->r_io[ATA_SERROR].offset = 0x00104 + ATA_MV_HOST_BASE(ch);
- ch->r_io[ATA_SCONTROL].res = ctlr->r_res1;
- ch->r_io[ATA_SCONTROL].offset = 0x00108 + ATA_MV_HOST_BASE(ch);
- break;
- case MV_60XX:
- case MV_6042:
- case MV_7042:
- ch->r_io[ATA_SSTATUS].res = ctlr->r_res1;
- ch->r_io[ATA_SSTATUS].offset = 0x02300 + ATA_MV_EDMA_BASE(ch);
- ch->r_io[ATA_SERROR].res = ctlr->r_res1;
- ch->r_io[ATA_SERROR].offset = 0x02304 + ATA_MV_EDMA_BASE(ch);
- ch->r_io[ATA_SCONTROL].res = ctlr->r_res1;
- ch->r_io[ATA_SCONTROL].offset = 0x02308 + ATA_MV_EDMA_BASE(ch);
- ch->r_io[ATA_SACTIVE].res = ctlr->r_res1;
- ch->r_io[ATA_SACTIVE].offset = 0x02350 + ATA_MV_EDMA_BASE(ch);
- break;
- }
-
- ch->flags |= ATA_NO_SLAVE;
- ch->flags |= ATA_USE_16BIT; /* XXX SOS needed ? */
- ch->flags |= ATA_SATA;
- ata_generic_hw(dev);
- ch->hw.begin_transaction = ata_marvell_edma_begin_transaction;
- ch->hw.end_transaction = ata_marvell_edma_end_transaction;
- ch->hw.status = ata_marvell_edma_status;
-
- /* disable the EDMA machinery */
- ATA_OUTL(ctlr->r_res1, 0x02028 + ATA_MV_EDMA_BASE(ch), 0x00000002);
- DELAY(100000); /* SOS should poll for disabled */
-
- /* set configuration to non-queued 128b read transfers stop on error */
- ATA_OUTL(ctlr->r_res1, 0x02000 + ATA_MV_EDMA_BASE(ch), (1<<11) | (1<<13));
-
- /* request queue base high */
- ATA_OUTL(ctlr->r_res1, 0x02010 + ATA_MV_EDMA_BASE(ch), work >> 32);
-
- /* request queue in ptr */
- ATA_OUTL(ctlr->r_res1, 0x02014 + ATA_MV_EDMA_BASE(ch), work & 0xffffffff);
-
- /* request queue out ptr */
- ATA_OUTL(ctlr->r_res1, 0x02018 + ATA_MV_EDMA_BASE(ch), 0x0);
-
- /* response queue base high */
- work += 1024;
- ATA_OUTL(ctlr->r_res1, 0x0201c + ATA_MV_EDMA_BASE(ch), work >> 32);
-
- /* response queue in ptr */
- ATA_OUTL(ctlr->r_res1, 0x02020 + ATA_MV_EDMA_BASE(ch), 0x0);
-
- /* response queue out ptr */
- ATA_OUTL(ctlr->r_res1, 0x02024 + ATA_MV_EDMA_BASE(ch), work & 0xffffffff);
-
- /* clear SATA error register */
- ATA_IDX_OUTL(ch, ATA_SERROR, ATA_IDX_INL(ch, ATA_SERROR));
-
- /* clear any outstanding error interrupts */
- ATA_OUTL(ctlr->r_res1, 0x02008 + ATA_MV_EDMA_BASE(ch), 0x0);
-
- /* unmask all error interrupts */
- ATA_OUTL(ctlr->r_res1, 0x0200c + ATA_MV_EDMA_BASE(ch), ~0x0);
-
- /* enable EDMA machinery */
- ATA_OUTL(ctlr->r_res1, 0x02028 + ATA_MV_EDMA_BASE(ch), 0x00000001);
- return 0;
-}
-
-static int
-ata_marvell_edma_ch_detach(device_t dev)
-{
- struct ata_channel *ch = device_get_softc(dev);
-
- if (ch->dma.work_tag && ch->dma.work_map)
- bus_dmamap_sync(ch->dma.work_tag, ch->dma.work_map,
- BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
- ata_dmafini(dev);
- return (0);
-}
-
-static int
-ata_marvell_edma_status(device_t dev)
-{
- struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
- struct ata_channel *ch = device_get_softc(dev);
- u_int32_t cause = ATA_INL(ctlr->r_res1, 0x01d60);
- int shift = (ch->unit << 1) + (ch->unit > 3);
-
- if (cause & (1 << shift)) {
-
- /* clear interrupt(s) */
- ATA_OUTL(ctlr->r_res1, 0x02008 + ATA_MV_EDMA_BASE(ch), 0x0);
-
- /* do we have any PHY events ? */
- ata_sata_phy_check_events(dev, -1);
- }
-
- /* do we have any device action ? */
- return (cause & (2 << shift));
-}
-
-/* must be called with ATA channel locked and state_mtx held */
-static int
-ata_marvell_edma_begin_transaction(struct ata_request *request)
-{
- struct ata_pci_controller *ctlr=device_get_softc(device_get_parent(request->parent));
- struct ata_channel *ch = device_get_softc(request->parent);
- u_int32_t req_in;
- u_int8_t *bytep;
- int i;
- int error, slot;
-
- /* only DMA R/W goes through the EMDA machine */
- if (request->u.ata.command != ATA_READ_DMA &&
- request->u.ata.command != ATA_WRITE_DMA &&
- request->u.ata.command != ATA_READ_DMA48 &&
- request->u.ata.command != ATA_WRITE_DMA48) {
-
- /* disable the EDMA machinery */
- if (ATA_INL(ctlr->r_res1, 0x02028 + ATA_MV_EDMA_BASE(ch)) & 0x00000001)
- ATA_OUTL(ctlr->r_res1, 0x02028 + ATA_MV_EDMA_BASE(ch), 0x00000002);
- return ata_begin_transaction(request);
- }
-
- /* check sanity, setup SG list and DMA engine */
- if ((error = ch->dma.load(request, NULL, NULL))) {
- device_printf(request->parent, "setting up DMA failed\n");
- request->result = error;
- return ATA_OP_FINISHED;
- }
-
- /* get next free request queue slot */
- req_in = ATA_INL(ctlr->r_res1, 0x02014 + ATA_MV_EDMA_BASE(ch));
- slot = (((req_in & ~0xfffffc00) >> 5) + 0) & 0x1f;
- bytep = (u_int8_t *)(ch->dma.work);
- bytep += (slot << 5);
-
- /* fill in this request */
- le32enc(bytep + 0 * sizeof(u_int32_t),
- request->dma->sg_bus & 0xffffffff);
- le32enc(bytep + 1 * sizeof(u_int32_t),
- (u_int64_t)request->dma->sg_bus >> 32);
- if (ctlr->chip->cfg2 != MV_6042 && ctlr->chip->cfg2 != MV_7042) {
- le16enc(bytep + 4 * sizeof(u_int16_t),
- (request->flags & ATA_R_READ ? 0x01 : 0x00) | (request->tag << 1));
-
- i = 10;
- bytep[i++] = (request->u.ata.count >> 8) & 0xff;
- bytep[i++] = 0x10 | ATA_COUNT;
- bytep[i++] = request->u.ata.count & 0xff;
- bytep[i++] = 0x10 | ATA_COUNT;
-
- bytep[i++] = (request->u.ata.lba >> 24) & 0xff;
- bytep[i++] = 0x10 | ATA_SECTOR;
- bytep[i++] = request->u.ata.lba & 0xff;
- bytep[i++] = 0x10 | ATA_SECTOR;
-
- bytep[i++] = (request->u.ata.lba >> 32) & 0xff;
- bytep[i++] = 0x10 | ATA_CYL_LSB;
- bytep[i++] = (request->u.ata.lba >> 8) & 0xff;
- bytep[i++] = 0x10 | ATA_CYL_LSB;
-
- bytep[i++] = (request->u.ata.lba >> 40) & 0xff;
- bytep[i++] = 0x10 | ATA_CYL_MSB;
- bytep[i++] = (request->u.ata.lba >> 16) & 0xff;
- bytep[i++] = 0x10 | ATA_CYL_MSB;
-
- bytep[i++] = ATA_D_LBA | ATA_D_IBM | ((request->u.ata.lba >> 24) & 0xf);
- bytep[i++] = 0x10 | ATA_DRIVE;
-
- bytep[i++] = request->u.ata.command;
- bytep[i++] = 0x90 | ATA_COMMAND;
- } else {
- le32enc(bytep + 2 * sizeof(u_int32_t),
- (request->flags & ATA_R_READ ? 0x01 : 0x00) | (request->tag << 1));
-
- i = 16;
- bytep[i++] = 0;
- bytep[i++] = 0;
- bytep[i++] = request->u.ata.command;
- bytep[i++] = request->u.ata.feature & 0xff;
-
- bytep[i++] = request->u.ata.lba & 0xff;
- bytep[i++] = (request->u.ata.lba >> 8) & 0xff;
- bytep[i++] = (request->u.ata.lba >> 16) & 0xff;
- bytep[i++] = ATA_D_LBA | ATA_D_IBM | ((request->u.ata.lba >> 24) & 0x0f);
-
- bytep[i++] = (request->u.ata.lba >> 24) & 0xff;
- bytep[i++] = (request->u.ata.lba >> 32) & 0xff;
- bytep[i++] = (request->u.ata.lba >> 40) & 0xff;
- bytep[i++] = (request->u.ata.feature >> 8) & 0xff;
-
- bytep[i++] = request->u.ata.count & 0xff;
- bytep[i++] = (request->u.ata.count >> 8) & 0xff;
- bytep[i++] = 0;
- bytep[i++] = 0;
- }
-
- bus_dmamap_sync(ch->dma.work_tag, ch->dma.work_map,
- BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
-
- /* enable EDMA machinery if needed */
- if (!(ATA_INL(ctlr->r_res1, 0x02028 + ATA_MV_EDMA_BASE(ch)) & 0x00000001)) {
- ATA_OUTL(ctlr->r_res1, 0x02028 + ATA_MV_EDMA_BASE(ch), 0x00000001);
- while (!(ATA_INL(ctlr->r_res1,
- 0x02028 + ATA_MV_EDMA_BASE(ch)) & 0x00000001))
- DELAY(10);
- }
-
- /* tell EDMA it has a new request */
- slot = (((req_in & ~0xfffffc00) >> 5) + 1) & 0x1f;
- req_in &= 0xfffffc00;
- req_in += (slot << 5);
- ATA_OUTL(ctlr->r_res1, 0x02014 + ATA_MV_EDMA_BASE(ch), req_in);
-
- return ATA_OP_CONTINUES;
-}
-
-/* must be called with ATA channel locked and state_mtx held */
-static int
-ata_marvell_edma_end_transaction(struct ata_request *request)
-{
- struct ata_pci_controller *ctlr=device_get_softc(device_get_parent(request->parent));
- struct ata_channel *ch = device_get_softc(request->parent);
- int offset = (ch->unit > 3 ? 0x30014 : 0x20014);
- u_int32_t icr = ATA_INL(ctlr->r_res1, offset);
- int res;
-
- /* EDMA interrupt */
- if ((icr & (0x0001 << (ch->unit & 3)))) {
- struct ata_marvell_response *response;
- u_int32_t rsp_in, rsp_out;
- int slot;
-
- /* stop timeout */
- callout_stop(&request->callout);
-
- /* get response ptr's */
- rsp_in = ATA_INL(ctlr->r_res1, 0x02020 + ATA_MV_EDMA_BASE(ch));
- rsp_out = ATA_INL(ctlr->r_res1, 0x02024 + ATA_MV_EDMA_BASE(ch));
- slot = (((rsp_in & ~0xffffff00) >> 3)) & 0x1f;
- rsp_out &= 0xffffff00;
- rsp_out += (slot << 3);
- bus_dmamap_sync(ch->dma.work_tag, ch->dma.work_map,
- BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
- response = (struct ata_marvell_response *)
- (ch->dma.work + 1024 + (slot << 3));
-
- /* record status for this request */
- request->status = response->dev_status;
- request->error = 0;
-
- /* ack response */
- ATA_OUTL(ctlr->r_res1, 0x02024 + ATA_MV_EDMA_BASE(ch), rsp_out);
-
- /* update progress */
- if (!(request->status & ATA_S_ERROR) &&
- !(request->flags & ATA_R_TIMEOUT))
- request->donecount = request->bytecount;
-
- /* unload SG list */
- ch->dma.unload(request);
-
- res = ATA_OP_FINISHED;
- }
-
- /* legacy ATA interrupt */
- else {
- res = ata_end_transaction(request);
- }
-
- /* ack interrupt */
- ATA_OUTL(ctlr->r_res1, offset, ~(icr & (0x0101 << (ch->unit & 3))));
- return res;
-}
-
-static void
-ata_marvell_edma_reset(device_t dev)
-{
- struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
- struct ata_channel *ch = device_get_softc(dev);
-
- /* disable the EDMA machinery */
- ATA_OUTL(ctlr->r_res1, 0x02028 + ATA_MV_EDMA_BASE(ch), 0x00000002);
- while ((ATA_INL(ctlr->r_res1, 0x02028 + ATA_MV_EDMA_BASE(ch)) & 0x00000001))
- DELAY(10);
-
- /* clear SATA error register */
- ATA_IDX_OUTL(ch, ATA_SERROR, ATA_IDX_INL(ch, ATA_SERROR));
-
- /* clear any outstanding error interrupts */
- ATA_OUTL(ctlr->r_res1, 0x02008 + ATA_MV_EDMA_BASE(ch), 0x0);
-
- /* unmask all error interrupts */
- ATA_OUTL(ctlr->r_res1, 0x0200c + ATA_MV_EDMA_BASE(ch), ~0x0);
-
- /* enable channel and test for devices */
- if (ata_sata_phy_reset(dev, -1, 1))
- ata_generic_reset(dev);
- else
- ch->devices = 0;
-
- /* enable EDMA machinery */
- ATA_OUTL(ctlr->r_res1, 0x02028 + ATA_MV_EDMA_BASE(ch), 0x00000001);
-}
-
-static void
-ata_marvell_edma_dmasetprd(void *xsc, bus_dma_segment_t *segs, int nsegs,
- int error)
-{
- struct ata_dmasetprd_args *args = xsc;
- struct ata_marvell_dma_prdentry *prd = args->dmatab;
- int i;
-
- if ((args->error = error))
- return;
-
- for (i = 0; i < nsegs; i++) {
- prd[i].addrlo = htole32(segs[i].ds_addr);
- prd[i].count = htole32(segs[i].ds_len);
- prd[i].addrhi = htole32((u_int64_t)segs[i].ds_addr >> 32);
- prd[i].reserved = 0;
- }
- prd[i - 1].count |= htole32(ATA_DMA_EOT);
- KASSERT(nsegs <= ATA_DMA_ENTRIES, ("too many DMA segment entries\n"));
- args->nsegs = nsegs;
-}
-
-static void
-ata_marvell_edma_dmainit(device_t dev)
-{
- struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
- struct ata_channel *ch = device_get_softc(dev);
-
- /* note start and stop are not used here */
- ch->dma.setprd = ata_marvell_edma_dmasetprd;
-
- /* if 64bit support present adjust max address used */
- if (ATA_INL(ctlr->r_res1, 0x00d00) & 0x00000004)
- ch->dma.max_address = BUS_SPACE_MAXADDR;
-
- /* chip does not reliably do 64K DMA transfers */
- if (ctlr->chip->cfg2 == MV_50XX || ctlr->chip->cfg2 == MV_60XX)
- ch->dma.max_iosize = 64 * DEV_BSIZE;
- ata_dmainit(dev);
-}
-
ATA_DECLARE_DRIVER(ata_marvell);
Modified: trunk/sys/dev/ata/chipsets/ata-micron.c
===================================================================
--- trunk/sys/dev/ata/chipsets/ata-micron.c 2018-05-28 00:25:20 UTC (rev 10127)
+++ trunk/sys/dev/ata/chipsets/ata-micron.c 2018-05-28 00:27:43 UTC (rev 10128)
@@ -1,5 +1,6 @@
+/* $MidnightBSD$ */
/*-
- * Copyright (c) 1998 - 2008 S\xF8ren Schmidt <sos at FreeBSD.org>
+ * Copyright (c) 1998 - 2008 Søren Schmidt <sos at FreeBSD.org>
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
@@ -25,9 +26,8 @@
*/
#include <sys/cdefs.h>
-__MBSDID("$MidnightBSD$");
+__FBSDID("$FreeBSD: stable/10/sys/dev/ata/chipsets/ata-micron.c 281140 2015-04-06 08:23:06Z mav $");
-#include "opt_ata.h"
#include <sys/param.h>
#include <sys/module.h>
#include <sys/systm.h>
@@ -64,7 +64,7 @@
device_set_desc(dev,
"RZ 100? ATA controller !WARNING! data loss/corruption risk");
ctlr->chipinit = ata_generic_chipinit;
- return (BUS_PROBE_DEFAULT);
+ return (BUS_PROBE_LOW_PRIORITY);
}
return (ENXIO);
}
Modified: trunk/sys/dev/ata/chipsets/ata-national.c
===================================================================
--- trunk/sys/dev/ata/chipsets/ata-national.c 2018-05-28 00:25:20 UTC (rev 10127)
+++ trunk/sys/dev/ata/chipsets/ata-national.c 2018-05-28 00:27:43 UTC (rev 10128)
@@ -1,5 +1,6 @@
+/* $MidnightBSD$ */
/*-
- * Copyright (c) 1998 - 2008 S\xF8ren Schmidt <sos at FreeBSD.org>
+ * Copyright (c) 1998 - 2008 Søren Schmidt <sos at FreeBSD.org>
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
@@ -25,9 +26,8 @@
*/
#include <sys/cdefs.h>
-__MBSDID("$MidnightBSD$");
+__FBSDID("$FreeBSD: stable/10/sys/dev/ata/chipsets/ata-national.c 281140 2015-04-06 08:23:06Z mav $");
-#include "opt_ata.h"
#include <sys/param.h>
#include <sys/module.h>
#include <sys/systm.h>
@@ -68,7 +68,7 @@
if (pci_get_devid(dev) == ATA_SC1100) {
device_set_desc(dev, "National Geode SC1100 ATA33 controller");
ctlr->chipinit = ata_national_chipinit;
- return (BUS_PROBE_DEFAULT);
+ return (BUS_PROBE_LOW_PRIORITY);
}
return ENXIO;
}
Modified: trunk/sys/dev/ata/chipsets/ata-netcell.c
===================================================================
--- trunk/sys/dev/ata/chipsets/ata-netcell.c 2018-05-28 00:25:20 UTC (rev 10127)
+++ trunk/sys/dev/ata/chipsets/ata-netcell.c 2018-05-28 00:27:43 UTC (rev 10128)
@@ -1,5 +1,6 @@
+/* $MidnightBSD$ */
/*-
- * Copyright (c) 1998 - 2008 S\xF8ren Schmidt <sos at FreeBSD.org>
+ * Copyright (c) 1998 - 2008 Søren Schmidt <sos at FreeBSD.org>
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
@@ -25,9 +26,8 @@
*/
#include <sys/cdefs.h>
-__MBSDID("$MidnightBSD$");
+__FBSDID("$FreeBSD: stable/10/sys/dev/ata/chipsets/ata-netcell.c 281140 2015-04-06 08:23:06Z mav $");
-#include "opt_ata.h"
#include <sys/param.h>
#include <sys/module.h>
#include <sys/systm.h>
@@ -67,7 +67,7 @@
if (pci_get_devid(dev) == ATA_NETCELL_SR) {
device_set_desc(dev, "Netcell SyncRAID SR3000/5000 RAID Controller");
ctlr->chipinit = ata_netcell_chipinit;
- return (BUS_PROBE_DEFAULT);
+ return (BUS_PROBE_LOW_PRIORITY);
}
return ENXIO;
}
Modified: trunk/sys/dev/ata/chipsets/ata-nvidia.c
===================================================================
--- trunk/sys/dev/ata/chipsets/ata-nvidia.c 2018-05-28 00:25:20 UTC (rev 10127)
+++ trunk/sys/dev/ata/chipsets/ata-nvidia.c 2018-05-28 00:27:43 UTC (rev 10128)
@@ -1,5 +1,6 @@
+/* $MidnightBSD$ */
/*-
- * Copyright (c) 1998 - 2008 S\xF8ren Schmidt <sos at FreeBSD.org>
+ * Copyright (c) 1998 - 2008 Søren Schmidt <sos at FreeBSD.org>
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
@@ -25,9 +26,8 @@
*/
#include <sys/cdefs.h>
-__MBSDID("$MidnightBSD$");
+__FBSDID("$FreeBSD: stable/10/sys/dev/ata/chipsets/ata-nvidia.c 287016 2015-08-22 07:32:47Z mav $");
-#include "opt_ata.h"
#include <sys/param.h>
#include <sys/module.h>
#include <sys/systm.h>
@@ -63,11 +63,7 @@
#define NV4 0x01
#define NVQ 0x02
#define NVAHCI 0x04
-#define NVNOFORCE 0x08
-static int force_ahci = 1;
-TUNABLE_INT("hw.ahci.force", &force_ahci);
-
/*
* nVidia chipset support functions
*/
@@ -162,7 +158,7 @@
{ ATA_NFORCE_MCP79_AA, 0, NVAHCI, 0, ATA_SA300, "nForce MCP79" },
{ ATA_NFORCE_MCP79_AB, 0, NVAHCI, 0, ATA_SA300, "nForce MCP79" },
{ ATA_NFORCE_MCP89_A0, 0, NVAHCI, 0, ATA_SA300, "nForce MCP89" },
- { ATA_NFORCE_MCP89_A1, 0, NVAHCI|NVNOFORCE, 0, ATA_SA300, "nForce MCP89" },
+ { ATA_NFORCE_MCP89_A1, 0, NVAHCI, 0, ATA_SA300, "nForce MCP89" },
{ ATA_NFORCE_MCP89_A2, 0, NVAHCI, 0, ATA_SA300, "nForce MCP89" },
{ ATA_NFORCE_MCP89_A3, 0, NVAHCI, 0, ATA_SA300, "nForce MCP89" },
{ ATA_NFORCE_MCP89_A4, 0, NVAHCI, 0, ATA_SA300, "nForce MCP89" },
@@ -181,14 +177,13 @@
if (!(ctlr->chip = ata_match_chip(dev, ids)))
return ENXIO;
+ if ((ctlr->chip->cfg1 & NVAHCI) &&
+ pci_get_subclass(dev) != PCIS_STORAGE_IDE)
+ return (ENXIO);
+
ata_set_desc(dev);
- if ((ctlr->chip->cfg1 & NVAHCI) &&
- ((force_ahci == 1 && (ctlr->chip->cfg1 & NVNOFORCE) == 0) ||
- pci_get_subclass(dev) != PCIS_STORAGE_IDE))
- ctlr->chipinit = ata_ahci_chipinit;
- else
- ctlr->chipinit = ata_nvidia_chipinit;
- return (BUS_PROBE_DEFAULT);
+ ctlr->chipinit = ata_nvidia_chipinit;
+ return (BUS_PROBE_LOW_PRIORITY);
}
static int
@@ -352,4 +347,3 @@
}
ATA_DECLARE_DRIVER(ata_nvidia);
-MODULE_DEPEND(ata_nvidia, ata_ahci, 1, 1, 1);
Modified: trunk/sys/dev/ata/chipsets/ata-promise.c
===================================================================
--- trunk/sys/dev/ata/chipsets/ata-promise.c 2018-05-28 00:25:20 UTC (rev 10127)
+++ trunk/sys/dev/ata/chipsets/ata-promise.c 2018-05-28 00:27:43 UTC (rev 10128)
@@ -1,5 +1,6 @@
+/* $MidnightBSD$ */
/*-
- * Copyright (c) 1998 - 2008 S\xF8ren Schmidt <sos at FreeBSD.org>
+ * Copyright (c) 1998 - 2008 Søren Schmidt <sos at FreeBSD.org>
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
@@ -25,9 +26,8 @@
*/
#include <sys/cdefs.h>
-__MBSDID("$MidnightBSD$");
+__FBSDID("$FreeBSD: stable/10/sys/dev/ata/chipsets/ata-promise.c 281140 2015-04-06 08:23:06Z mav $");
-#include "opt_ata.h"
#include <sys/param.h>
#include <sys/module.h>
#include <sys/systm.h>
@@ -210,7 +210,7 @@
device_set_desc_copy(dev, buffer);
ctlr->chip = idx;
ctlr->chipinit = ata_promise_chipinit;
- return (BUS_PROBE_DEFAULT);
+ return (BUS_PROBE_LOW_PRIORITY);
}
static int
@@ -288,6 +288,10 @@
/* setup host packet controls */
hpkt = malloc(sizeof(struct ata_promise_sx4),
M_ATAPCI, M_NOWAIT | M_ZERO);
+ if (hpkt == NULL) {
+ device_printf(dev, "Cannot allocate HPKT\n");
+ goto failnfree;
+ }
mtx_init(&hpkt->mtx, "ATA promise HPKT lock", NULL, MTX_DEF);
TAILQ_INIT(&hpkt->queue);
hpkt->busy = 0;
Modified: trunk/sys/dev/ata/chipsets/ata-serverworks.c
===================================================================
--- trunk/sys/dev/ata/chipsets/ata-serverworks.c 2018-05-28 00:25:20 UTC (rev 10127)
+++ trunk/sys/dev/ata/chipsets/ata-serverworks.c 2018-05-28 00:27:43 UTC (rev 10128)
@@ -1,5 +1,6 @@
+/* $MidnightBSD$ */
/*-
- * Copyright (c) 1998 - 2008 S\xF8ren Schmidt <sos at FreeBSD.org>
+ * Copyright (c) 1998 - 2008 Søren Schmidt <sos at FreeBSD.org>
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
@@ -25,9 +26,8 @@
*/
#include <sys/cdefs.h>
-__MBSDID("$MidnightBSD$");
+__FBSDID("$FreeBSD: stable/10/sys/dev/ata/chipsets/ata-serverworks.c 281140 2015-04-06 08:23:06Z mav $");
-#include "opt_ata.h"
#include <sys/param.h>
#include <sys/module.h>
#include <sys/systm.h>
@@ -97,7 +97,7 @@
ata_set_desc(dev);
ctlr->chipinit = ata_serverworks_chipinit;
- return (BUS_PROBE_DEFAULT);
+ return (BUS_PROBE_LOW_PRIORITY);
}
static int
@@ -288,9 +288,6 @@
ata_serverworks_tf_write(struct ata_request *request)
{
struct ata_channel *ch = device_get_softc(request->parent);
-#ifndef ATA_CAM
- struct ata_device *atadev = device_get_softc(request->dev);
-#endif
if (request->flags & ATA_R_48BIT) {
ATA_IDX_OUTW(ch, ATA_FEATURE, request->u.ata.feature);
@@ -306,29 +303,6 @@
else {
ATA_IDX_OUTW(ch, ATA_FEATURE, request->u.ata.feature);
ATA_IDX_OUTW(ch, ATA_COUNT, request->u.ata.count);
-#ifndef ATA_CAM
- if (atadev->flags & ATA_D_USE_CHS) {
- int heads, sectors;
-
- if (atadev->param.atavalid & ATA_FLAG_54_58) {
- heads = atadev->param.current_heads;
- sectors = atadev->param.current_sectors;
- }
- else {
- heads = atadev->param.heads;
- sectors = atadev->param.sectors;
- }
- ATA_IDX_OUTW(ch, ATA_SECTOR, (request->u.ata.lba % sectors)+1);
- ATA_IDX_OUTW(ch, ATA_CYL_LSB,
- (request->u.ata.lba / (sectors * heads)));
- ATA_IDX_OUTW(ch, ATA_CYL_MSB,
- (request->u.ata.lba / (sectors * heads)) >> 8);
- ATA_IDX_OUTW(ch, ATA_DRIVE, ATA_D_IBM | ATA_DEV(request->unit) |
- (((request->u.ata.lba% (sectors * heads)) /
- sectors) & 0xf));
- }
- else {
-#endif
ATA_IDX_OUTW(ch, ATA_SECTOR, request->u.ata.lba);
ATA_IDX_OUTW(ch, ATA_CYL_LSB, request->u.ata.lba >> 8);
ATA_IDX_OUTW(ch, ATA_CYL_MSB, request->u.ata.lba >> 16);
@@ -335,9 +309,6 @@
ATA_IDX_OUTW(ch, ATA_DRIVE,
ATA_D_IBM | ATA_D_LBA | ATA_DEV(request->unit) |
((request->u.ata.lba >> 24) & 0x0f));
-#ifndef ATA_CAM
- }
-#endif
}
}
Modified: trunk/sys/dev/ata/chipsets/ata-siliconimage.c
===================================================================
--- trunk/sys/dev/ata/chipsets/ata-siliconimage.c 2018-05-28 00:25:20 UTC (rev 10127)
+++ trunk/sys/dev/ata/chipsets/ata-siliconimage.c 2018-05-28 00:27:43 UTC (rev 10128)
@@ -1,5 +1,6 @@
+/* $MidnightBSD$ */
/*-
- * Copyright (c) 1998 - 2008 S\xF8ren Schmidt <sos at FreeBSD.org>
+ * Copyright (c) 1998 - 2008 Søren Schmidt <sos at FreeBSD.org>
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
@@ -25,9 +26,8 @@
*/
#include <sys/cdefs.h>
-__MBSDID("$MidnightBSD$");
+__FBSDID("$FreeBSD: stable/10/sys/dev/ata/chipsets/ata-siliconimage.c 287016 2015-08-22 07:32:47Z mav $");
-#include "opt_ata.h"
#include <sys/param.h>
#include <sys/module.h>
#include <sys/systm.h>
@@ -60,21 +60,9 @@
static int ata_sii_status(device_t dev);
static void ata_sii_reset(device_t dev);
static int ata_sii_setmode(device_t dev, int target, int mode);
-static int ata_siiprb_ch_attach(device_t dev);
-static int ata_siiprb_ch_detach(device_t dev);
-static int ata_siiprb_status(device_t dev);
-static int ata_siiprb_begin_transaction(struct ata_request *request);
-static int ata_siiprb_end_transaction(struct ata_request *request);
-static int ata_siiprb_pm_read(device_t dev, int port, int reg, u_int32_t *result);
-static int ata_siiprb_pm_write(device_t dev, int port, int reg, u_int32_t result);
-static u_int32_t ata_siiprb_softreset(device_t dev, int port);
-static void ata_siiprb_reset(device_t dev);
-static void ata_siiprb_dmasetprd(void *xsc, bus_dma_segment_t *segs, int nsegs, int error);
-static void ata_siiprb_dmainit(device_t dev);
/* misc defines */
#define SII_MEMIO 1
-#define SII_PRBIO 2
#define SII_INTR 0x01
#define SII_SETCLK 0x02
#define SII_BUG 0x04
@@ -95,10 +83,6 @@
{ ATA_SII3512, 0x00, SII_MEMIO, SII_BUG, ATA_SA150, "3512" },
{ ATA_SII3112, 0x00, SII_MEMIO, SII_BUG, ATA_SA150, "3112" },
{ ATA_SII3112_1, 0x00, SII_MEMIO, SII_BUG, ATA_SA150, "3112" },
- { ATA_SII3124, 0x00, SII_PRBIO, SII_4CH, ATA_SA300, "3124" },
- { ATA_SII3132, 0x00, SII_PRBIO, 0, ATA_SA300, "3132" },
- { ATA_SII3132_1, 0x00, SII_PRBIO, 0, ATA_SA300, "3132" },
- { ATA_SII3132_2, 0x00, SII_PRBIO, 0, ATA_SA300, "3132" },
{ ATA_SII0680, 0x00, SII_MEMIO, SII_SETCLK, ATA_UDMA6, "680" },
{ ATA_CMD649, 0x00, 0, SII_INTR, ATA_UDMA5, "(CMD) 649" },
{ ATA_CMD648, 0x00, 0, SII_INTR, ATA_UDMA4, "(CMD) 648" },
@@ -114,7 +98,7 @@
ata_set_desc(dev);
ctlr->chipinit = ata_sii_chipinit;
- return (BUS_PROBE_DEFAULT);
+ return (BUS_PROBE_LOW_PRIORITY);
}
int
@@ -126,44 +110,6 @@
return ENXIO;
switch (ctlr->chip->cfg1) {
- case SII_PRBIO:
- ctlr->r_type1 = SYS_RES_MEMORY;
- ctlr->r_rid1 = PCIR_BAR(0);
- if (!(ctlr->r_res1 = bus_alloc_resource_any(dev, ctlr->r_type1,
- &ctlr->r_rid1, RF_ACTIVE)))
- return ENXIO;
-
- ctlr->r_rid2 = PCIR_BAR(2);
- ctlr->r_type2 = SYS_RES_MEMORY;
- if (!(ctlr->r_res2 = bus_alloc_resource_any(dev, ctlr->r_type2,
- &ctlr->r_rid2, RF_ACTIVE))){
- bus_release_resource(dev, ctlr->r_type1, ctlr->r_rid1,ctlr->r_res1);
- return ENXIO;
- }
-#ifdef __sparc64__
- if (!bus_space_map(rman_get_bustag(ctlr->r_res2),
- rman_get_bushandle(ctlr->r_res2), rman_get_size(ctlr->r_res2),
- BUS_SPACE_MAP_LINEAR, NULL)) {
- bus_release_resource(dev, ctlr->r_type1, ctlr->r_rid1,
- ctlr->r_res1);
- bus_release_resource(dev, ctlr->r_type2, ctlr->r_rid2,
- ctlr->r_res2);
- return (ENXIO);
- }
-#endif
- ctlr->ch_attach = ata_siiprb_ch_attach;
- ctlr->ch_detach = ata_siiprb_ch_detach;
- ctlr->reset = ata_siiprb_reset;
- ctlr->setmode = ata_sata_setmode;
- ctlr->getrev = ata_sata_getrev;
- ctlr->channels = (ctlr->chip->cfg2 == SII_4CH) ? 4 : 2;
-
- /* reset controller */
- ATA_OUTL(ctlr->r_res1, 0x0040, 0x80000000);
- DELAY(10000);
- ATA_OUTL(ctlr->r_res1, 0x0040, 0x0000000f);
- break;
-
case SII_MEMIO:
ctlr->r_type2 = SYS_RES_MEMORY;
ctlr->r_rid2 = PCIR_BAR(5);
@@ -240,9 +186,7 @@
if (ctlr->chip->cfg2 & SII_INTR)
ch->hw.status = ata_cmd_status;
-#ifdef ATA_CAM
ch->flags |= ATA_NO_ATAPI_DMA;
-#endif
return 0;
}
@@ -449,509 +393,4 @@
return (mode);
}
-struct ata_siiprb_dma_prdentry {
- u_int64_t addr;
- u_int32_t count;
- u_int32_t control;
-} __packed;
-
-#define ATA_SIIPRB_DMA_ENTRIES 129
-struct ata_siiprb_ata_command {
- struct ata_siiprb_dma_prdentry prd[ATA_SIIPRB_DMA_ENTRIES];
-} __packed;
-
-struct ata_siiprb_atapi_command {
- u_int8_t ccb[16];
- struct ata_siiprb_dma_prdentry prd[ATA_SIIPRB_DMA_ENTRIES];
-} __packed;
-
-struct ata_siiprb_command {
- u_int16_t control;
- u_int16_t protocol_override;
- u_int32_t transfer_count;
- u_int8_t fis[24];
- union {
- struct ata_siiprb_ata_command ata;
- struct ata_siiprb_atapi_command atapi;
- } u;
-} __packed;
-
-static int
-ata_siiprb_ch_attach(device_t dev)
-{
- struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
- struct ata_channel *ch = device_get_softc(dev);
- int offset = ch->unit * 0x2000;
-
- ata_siiprb_dmainit(dev);
-
- /* set the SATA resources */
- ch->r_io[ATA_SSTATUS].res = ctlr->r_res2;
- ch->r_io[ATA_SSTATUS].offset = 0x1f04 + offset;
- ch->r_io[ATA_SERROR].res = ctlr->r_res2;
- ch->r_io[ATA_SERROR].offset = 0x1f08 + offset;
- ch->r_io[ATA_SCONTROL].res = ctlr->r_res2;
- ch->r_io[ATA_SCONTROL].offset = 0x1f00 + offset;
- ch->r_io[ATA_SACTIVE].res = ctlr->r_res2;
- ch->r_io[ATA_SACTIVE].offset = 0x1f0c + offset;
-
- ch->hw.status = ata_siiprb_status;
- ch->hw.begin_transaction = ata_siiprb_begin_transaction;
- ch->hw.end_transaction = ata_siiprb_end_transaction;
- ch->hw.command = NULL; /* not used here */
- ch->hw.softreset = ata_siiprb_softreset;
- ch->hw.pm_read = ata_siiprb_pm_read;
- ch->hw.pm_write = ata_siiprb_pm_write;
- ch->flags |= ATA_NO_SLAVE;
- ch->flags |= ATA_SATA;
- return 0;
-}
-
-static int
-ata_siiprb_ch_detach(device_t dev)
-{
- struct ata_channel *ch = device_get_softc(dev);
-
- if (ch->dma.work_tag && ch->dma.work_map)
- bus_dmamap_sync(ch->dma.work_tag, ch->dma.work_map,
- BUS_DMASYNC_POSTWRITE);
- ata_dmafini(dev);
- return 0;
-}
-
-static int
-ata_siiprb_status(device_t dev)
-{
- struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
- struct ata_channel *ch = device_get_softc(dev);
- u_int32_t action = ATA_INL(ctlr->r_res1, 0x0044);
- int offset = ch->unit * 0x2000;
-
- if (action & (1 << ch->unit)) {
- u_int32_t istatus = ATA_INL(ctlr->r_res2, 0x1008 + offset);
-
- /* do we have any PHY events ? */
- ata_sata_phy_check_events(dev, -1);
-
- /* clear interrupt(s) */
- ATA_OUTL(ctlr->r_res2, 0x1008 + offset, istatus);
-
- /* do we have any device action ? */
- return (istatus & 0x00000003);
- }
- return 0;
-}
-
-static int
-ata_siiprb_begin_transaction(struct ata_request *request)
-{
- struct ata_pci_controller *ctlr=device_get_softc(device_get_parent(request->parent));
- struct ata_channel *ch = device_get_softc(request->parent);
- struct ata_siiprb_command *prb;
- struct ata_siiprb_dma_prdentry *prd;
- int offset = ch->unit * 0x2000;
- u_int64_t prb_bus;
-
- /* SOS XXX */
- if (request->u.ata.command == ATA_DEVICE_RESET) {
- request->result = 0;
- return ATA_OP_FINISHED;
- }
-
- /* get a piece of the workspace for this request */
- prb = (struct ata_siiprb_command *)ch->dma.work;
-
- /* clear the prb structure */
- bzero(prb, sizeof(struct ata_siiprb_command));
-
- /* setup the FIS for this request */
- if (!ata_request2fis_h2d(request, &prb->fis[0])) {
- device_printf(request->parent, "setting up SATA FIS failed\n");
- request->result = EIO;
- return ATA_OP_FINISHED;
- }
-
- /* setup transfer type */
- if (request->flags & ATA_R_ATAPI) {
- bcopy(request->u.atapi.ccb, prb->u.atapi.ccb, 16);
- if (request->flags & ATA_R_ATAPI16)
- ATA_OUTL(ctlr->r_res2, 0x1000 + offset, 0x00000020);
- else
- ATA_OUTL(ctlr->r_res2, 0x1004 + offset, 0x00000020);
- if (request->flags & ATA_R_READ)
- prb->control = htole16(0x0010);
- if (request->flags & ATA_R_WRITE)
- prb->control = htole16(0x0020);
- prd = &prb->u.atapi.prd[0];
- }
- else
- prd = &prb->u.ata.prd[0];
-
- /* if request moves data setup and load SG list */
- if (request->flags & (ATA_R_READ | ATA_R_WRITE)) {
- if (ch->dma.load(request, prd, NULL)) {
- device_printf(request->parent, "setting up DMA failed\n");
- request->result = EIO;
- return ATA_OP_FINISHED;
- }
- }
-
- bus_dmamap_sync(ch->dma.work_tag, ch->dma.work_map, BUS_DMASYNC_PREWRITE);
-
- /* activate the prb */
- prb_bus = ch->dma.work_bus;
- ATA_OUTL(ctlr->r_res2, 0x1c00 + offset, prb_bus);
- ATA_OUTL(ctlr->r_res2, 0x1c04 + offset, prb_bus>>32);
-
- /* start the timeout */
- callout_reset(&request->callout, request->timeout * hz,
- (timeout_t*)ata_timeout, request);
- return ATA_OP_CONTINUES;
-}
-
-static int
-ata_siiprb_end_transaction(struct ata_request *request)
-{
- struct ata_pci_controller *ctlr=device_get_softc(device_get_parent(request->parent));
- struct ata_channel *ch = device_get_softc(request->parent);
- struct ata_siiprb_command *prb;
- int offset = ch->unit * 0x2000;
- int error, timeout;
-
- /* kill the timeout */
- callout_stop(&request->callout);
-
- bus_dmamap_sync(ch->dma.work_tag, ch->dma.work_map, BUS_DMASYNC_POSTWRITE);
-
- prb = (struct ata_siiprb_command *)
- ((u_int8_t *)rman_get_virtual(ctlr->r_res2) + offset);
-
- /* any controller errors flagged ? */
- if ((error = ATA_INL(ctlr->r_res2, 0x1024 + offset))) {
- if (bootverbose)
- printf("ata_siiprb_end_transaction %s error=%08x\n",
- ata_cmd2str(request), error);
-
- /* if device error status get details */
- if (error == 1 || error == 2) {
- request->status = prb->fis[2];
- if (request->status & ATA_S_ERROR)
- request->error = prb->fis[3];
- }
-
- /* SOS XXX handle other controller errors here */
-
- /* initialize port */
- ATA_OUTL(ctlr->r_res2, 0x1000 + offset, 0x00000004);
-
- /* poll for port ready */
- for (timeout = 0; timeout < 1000; timeout++) {
- DELAY(1000);
- if (ATA_INL(ctlr->r_res2, 0x1008 + offset) & 0x00040000)
- break;
- }
- if (bootverbose) {
- if (timeout >= 1000)
- device_printf(ch->dev, "port initialize timeout\n");
- else
- device_printf(ch->dev, "port initialize time=%dms\n", timeout);
- }
- }
-
- /* Read back registers to the request struct. */
- if ((request->flags & ATA_R_ATAPI) == 0 &&
- ((request->status & ATA_S_ERROR) ||
- (request->flags & (ATA_R_CONTROL | ATA_R_NEEDRESULT)))) {
- request->u.ata.count = prb->fis[12] | ((u_int16_t)prb->fis[13] << 8);
- request->u.ata.lba = prb->fis[4] | ((u_int64_t)prb->fis[5] << 8) |
- ((u_int64_t)prb->fis[6] << 16);
- if (request->flags & ATA_R_48BIT)
- request->u.ata.lba |= ((u_int64_t)prb->fis[8] << 24) |
- ((u_int64_t)prb->fis[9] << 32) |
- ((u_int64_t)prb->fis[10] << 40);
- else
- request->u.ata.lba |= ((u_int64_t)(prb->fis[7] & 0x0f) << 24);
- }
-
- /* update progress */
- if (!(request->status & ATA_S_ERROR) && !(request->flags & ATA_R_TIMEOUT)) {
- if (request->flags & ATA_R_READ)
- request->donecount = le32toh(prb->transfer_count);
- else
- request->donecount = request->bytecount;
- }
-
- /* release SG list etc */
- ch->dma.unload(request);
-
- return ATA_OP_FINISHED;
-}
-
-static int
-ata_siiprb_issue_cmd(device_t dev)
-{
- struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
- struct ata_channel *ch = device_get_softc(dev);
- u_int64_t prb_bus = ch->dma.work_bus;
- u_int32_t status;
- int offset = ch->unit * 0x2000;
- int timeout;
-
- bus_dmamap_sync(ch->dma.work_tag, ch->dma.work_map, BUS_DMASYNC_PREWRITE);
-
- /* issue command to chip */
- ATA_OUTL(ctlr->r_res2, 0x1c00 + offset, prb_bus);
- ATA_OUTL(ctlr->r_res2, 0x1c04 + offset, prb_bus >> 32);
-
- /* poll for command finished */
- for (timeout = 0; timeout < 10000; timeout++) {
- DELAY(1000);
- if ((status = ATA_INL(ctlr->r_res2, 0x1008 + offset)) & 0x00010000)
- break;
- }
-
- bus_dmamap_sync(ch->dma.work_tag, ch->dma.work_map, BUS_DMASYNC_POSTWRITE);
-
- // SOS XXX ATA_OUTL(ctlr->r_res2, 0x1008 + offset, 0x00010000);
- ATA_OUTL(ctlr->r_res2, 0x1008 + offset, 0x08ff08ff);
-
- if (timeout >= 1000)
- return EIO;
-
- if (bootverbose)
- device_printf(dev, "siiprb_issue_cmd time=%dms status=%08x\n",
- timeout, status);
- return 0;
-}
-
-static int
-ata_siiprb_pm_read(device_t dev, int port, int reg, u_int32_t *result)
-{
- struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
- struct ata_channel *ch = device_get_softc(dev);
- struct ata_siiprb_command *prb = (struct ata_siiprb_command *)ch->dma.work;
- int offset = ch->unit * 0x2000;
-
- if (port < 0) {
- *result = ATA_IDX_INL(ch, reg);
- return (0);
- }
- if (port < ATA_PM) {
- switch (reg) {
- case ATA_SSTATUS:
- reg = 0;
- break;
- case ATA_SERROR:
- reg = 1;
- break;
- case ATA_SCONTROL:
- reg = 2;
- break;
- default:
- return (EINVAL);
- }
- }
- bzero(prb, sizeof(struct ata_siiprb_command));
- prb->fis[0] = 0x27; /* host to device */
- prb->fis[1] = 0x8f; /* command FIS to PM port */
- prb->fis[2] = ATA_READ_PM;
- prb->fis[3] = reg;
- prb->fis[7] = port;
- if (ata_siiprb_issue_cmd(dev)) {
- device_printf(dev, "error reading PM port\n");
- return EIO;
- }
- prb = (struct ata_siiprb_command *)
- ((u_int8_t *)rman_get_virtual(ctlr->r_res2) + offset);
- *result = prb->fis[12]|(prb->fis[4]<<8)|(prb->fis[5]<<16)|(prb->fis[6]<<24);
- return 0;
-}
-
-static int
-ata_siiprb_pm_write(device_t dev, int port, int reg, u_int32_t value)
-{
- struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
- struct ata_channel *ch = device_get_softc(dev);
- struct ata_siiprb_command *prb = (struct ata_siiprb_command *)ch->dma.work;
- int offset = ch->unit * 0x2000;
-
- if (port < 0) {
- ATA_IDX_OUTL(ch, reg, value);
- return (0);
- }
- if (port < ATA_PM) {
- switch (reg) {
- case ATA_SSTATUS:
- reg = 0;
- break;
- case ATA_SERROR:
- reg = 1;
- break;
- case ATA_SCONTROL:
- reg = 2;
- break;
- default:
- return (EINVAL);
- }
- }
- bzero(prb, sizeof(struct ata_siiprb_command));
- prb->fis[0] = 0x27; /* host to device */
- prb->fis[1] = 0x8f; /* command FIS to PM port */
- prb->fis[2] = ATA_WRITE_PM;
- prb->fis[3] = reg;
- prb->fis[7] = port;
- prb->fis[12] = value & 0xff;
- prb->fis[4] = (value >> 8) & 0xff;
- prb->fis[5] = (value >> 16) & 0xff;
- prb->fis[6] = (value >> 24) & 0xff;
- if (ata_siiprb_issue_cmd(dev)) {
- device_printf(dev, "error writing PM port\n");
- return ATA_E_ABORT;
- }
- prb = (struct ata_siiprb_command *)
- ((u_int8_t *)rman_get_virtual(ctlr->r_res2) + offset);
- return prb->fis[3];
-}
-
-static u_int32_t
-ata_siiprb_softreset(device_t dev, int port)
-{
- struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
- struct ata_channel *ch = device_get_softc(dev);
- struct ata_siiprb_command *prb = (struct ata_siiprb_command *)ch->dma.work;
- u_int32_t signature;
- int offset = ch->unit * 0x2000;
-
- /* setup the workspace for a soft reset command */
- bzero(prb, sizeof(struct ata_siiprb_command));
- prb->control = htole16(0x0080);
- prb->fis[1] = port & 0x0f;
-
- /* issue soft reset */
- if (ata_siiprb_issue_cmd(dev))
- return -1;
-
- ata_udelay(150000);
-
- /* get possible signature */
- prb = (struct ata_siiprb_command *)
- ((u_int8_t *)rman_get_virtual(ctlr->r_res2) + offset);
- signature=prb->fis[12]|(prb->fis[4]<<8)|(prb->fis[5]<<16)|(prb->fis[6]<<24);
-
- /* clear error bits/interrupt */
- ATA_IDX_OUTL(ch, ATA_SERROR, 0xffffffff);
-
- return signature;
-}
-
-static void
-ata_siiprb_reset(device_t dev)
-{
- struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
- struct ata_channel *ch = device_get_softc(dev);
- int offset = ch->unit * 0x2000;
- u_int32_t status, signature;
- int timeout;
-
- /* disable interrupts */
- ATA_OUTL(ctlr->r_res2, 0x1014 + offset, 0x000000ff);
-
- /* reset channel HW */
- ATA_OUTL(ctlr->r_res2, 0x1000 + offset, 0x00000001);
- DELAY(1000);
- ATA_OUTL(ctlr->r_res2, 0x1004 + offset, 0x00000001);
- DELAY(10000);
-
- /* poll for channel ready */
- for (timeout = 0; timeout < 1000; timeout++) {
- if ((status = ATA_INL(ctlr->r_res2, 0x1008 + offset)) & 0x00040000)
- break;
- DELAY(1000);
- }
-
- if (bootverbose) {
- if (timeout >= 1000)
- device_printf(dev, "channel HW reset timeout\n");
- else
- device_printf(dev, "channel HW reset time=%dms\n", timeout);
- }
-
- /* reset phy */
- if (!ata_sata_phy_reset(dev, -1, 1)) {
- if (bootverbose)
- device_printf(dev, "phy reset found no device\n");
- ch->devices = 0;
- goto finish;
- }
-
- /* issue soft reset */
- signature = ata_siiprb_softreset(dev, ATA_PM);
- if (bootverbose)
- device_printf(dev, "SIGNATURE=%08x\n", signature);
-
- /* figure out whats there */
- switch (signature >> 16) {
- case 0x0000:
- ch->devices = ATA_ATA_MASTER;
- break;
- case 0x9669:
- ch->devices = ATA_PORTMULTIPLIER;
- ATA_OUTL(ctlr->r_res2, 0x1000 + offset, 0x2000); /* enable PM support */
- //SOS XXX need to clear all PM status and interrupts!!!!
- ata_pm_identify(dev);
- break;
- case 0xeb14:
- ch->devices = ATA_ATAPI_MASTER;
- break;
- default:
- ch->devices = 0;
- }
- if (bootverbose)
- device_printf(dev, "siiprb_reset devices=%08x\n", ch->devices);
-
-finish:
- /* clear interrupt(s) */
- ATA_OUTL(ctlr->r_res2, 0x1008 + offset, 0x000008ff);
-
- /* require explicit interrupt ack */
- ATA_OUTL(ctlr->r_res2, 0x1000 + offset, 0x00000008);
-
- /* 64bit mode */
- ATA_OUTL(ctlr->r_res2, 0x1004 + offset, 0x00000400);
-
- /* enable interrupts wanted */
- ATA_OUTL(ctlr->r_res2, 0x1010 + offset, 0x000000ff);
-}
-
-static void
-ata_siiprb_dmasetprd(void *xsc, bus_dma_segment_t *segs, int nsegs, int error)
-{
- struct ata_dmasetprd_args *args = xsc;
- struct ata_siiprb_dma_prdentry *prd = args->dmatab;
- int i;
-
- if ((args->error = error))
- return;
-
- for (i = 0; i < nsegs; i++) {
- prd[i].addr = htole64(segs[i].ds_addr);
- prd[i].count = htole32(segs[i].ds_len);
- }
- prd[i - 1].control = htole32(ATA_DMA_EOT);
- KASSERT(nsegs <= ATA_SIIPRB_DMA_ENTRIES,("too many DMA segment entries\n"));
- args->nsegs = nsegs;
-}
-
-static void
-ata_siiprb_dmainit(device_t dev)
-{
- struct ata_channel *ch = device_get_softc(dev);
-
- /* note start and stop are not used here */
- ch->dma.setprd = ata_siiprb_dmasetprd;
- ch->dma.max_address = BUS_SPACE_MAXADDR;
- ch->dma.max_iosize = (ATA_SIIPRB_DMA_ENTRIES - 1) * PAGE_SIZE;
- ata_dmainit(dev);
-}
-
ATA_DECLARE_DRIVER(ata_sii);
Modified: trunk/sys/dev/ata/chipsets/ata-sis.c
===================================================================
--- trunk/sys/dev/ata/chipsets/ata-sis.c 2018-05-28 00:25:20 UTC (rev 10127)
+++ trunk/sys/dev/ata/chipsets/ata-sis.c 2018-05-28 00:27:43 UTC (rev 10128)
@@ -1,5 +1,6 @@
+/* $MidnightBSD$ */
/*-
- * Copyright (c) 1998 - 2008 S\xF8ren Schmidt <sos at FreeBSD.org>
+ * Copyright (c) 1998 - 2008 Søren Schmidt <sos at FreeBSD.org>
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
@@ -25,9 +26,8 @@
*/
#include <sys/cdefs.h>
-__MBSDID("$MidnightBSD$");
+__FBSDID("$FreeBSD: stable/10/sys/dev/ata/chipsets/ata-sis.c 281140 2015-04-06 08:23:06Z mav $");
-#include "opt_ata.h"
#include <sys/param.h>
#include <sys/module.h>
#include <sys/systm.h>
@@ -155,7 +155,7 @@
device_set_desc_copy(dev, buffer);
ctlr->chip = idx;
ctlr->chipinit = ata_sis_chipinit;
- return (BUS_PROBE_DEFAULT);
+ return (BUS_PROBE_LOW_PRIORITY);
}
static int
Modified: trunk/sys/dev/ata/chipsets/ata-via.c
===================================================================
--- trunk/sys/dev/ata/chipsets/ata-via.c 2018-05-28 00:25:20 UTC (rev 10127)
+++ trunk/sys/dev/ata/chipsets/ata-via.c 2018-05-28 00:27:43 UTC (rev 10128)
@@ -1,5 +1,6 @@
+/* $MidnightBSD$ */
/*-
- * Copyright (c) 1998 - 2008 S\xF8ren Schmidt <sos at FreeBSD.org>
+ * Copyright (c) 1998 - 2008 Søren Schmidt <sos at FreeBSD.org>
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
@@ -25,9 +26,8 @@
*/
#include <sys/cdefs.h>
-__MBSDID("$MidnightBSD$");
+__FBSDID("$FreeBSD: stable/10/sys/dev/ata/chipsets/ata-via.c 287016 2015-08-22 07:32:47Z mav $");
-#include "opt_ata.h"
#include <sys/param.h>
#include <sys/module.h>
#include <sys/systm.h>
@@ -79,7 +79,6 @@
#define VIACLK 0x01
#define VIABUG 0x02
#define VIABAR 0x04
-#define VIAAHCI 0x08
#define VIASATA 0x10
/*
@@ -121,7 +120,6 @@
{ ATA_VIA8237S, 0x00, 7, 0x00, ATA_SA150, "8237S" },
{ ATA_VIA8237_5372, 0x00, 7, 0x00, ATA_SA300, "8237" },
{ ATA_VIA8237_7372, 0x00, 7, 0x00, ATA_SA300, "8237" },
- { ATA_VIA8251, 0x00, 0, VIAAHCI, ATA_SA300, "8251" },
{ 0, 0, 0, 0, 0, 0 }};
if (pci_get_vendor(dev) != ATA_VIA_ID)
@@ -142,7 +140,7 @@
ata_set_desc(dev);
ctlr->chipinit = ata_via_chipinit;
- return (BUS_PROBE_DEFAULT);
+ return (BUS_PROBE_LOW_PRIORITY);
}
static int
@@ -153,11 +151,6 @@
if (ata_setup_interrupt(dev, ata_generic_intr))
return ENXIO;
- /* AHCI SATA */
- if (ctlr->chip->cfg2 & VIAAHCI) {
- if (ata_ahci_chipinit(dev) != ENXIO)
- return (0);
- }
/* 2 SATA with "SATA registers" at PCI config space + PATA on secondary */
if (ctlr->chip->cfg2 & VIASATA) {
ctlr->ch_attach = ata_via_sata_ch_attach;
@@ -555,4 +548,3 @@
}
ATA_DECLARE_DRIVER(ata_via);
-MODULE_DEPEND(ata_via, ata_ahci, 1, 1, 1);
Added: trunk/sys/dev/ath/ath_hal/ar5416/ar5416_spectral.c
===================================================================
--- trunk/sys/dev/ath/ath_hal/ar5416/ar5416_spectral.c (rev 0)
+++ trunk/sys/dev/ath/ath_hal/ar5416/ar5416_spectral.c 2018-05-28 00:27:43 UTC (rev 10128)
@@ -0,0 +1,245 @@
+/* $MidnightBSD$ */
+/*
+ * Copyright (c) 2012 Qualcomm Atheros, All Rights Reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ *
+ * $FreeBSD: stable/10/sys/dev/ath/ath_hal/ar5416/ar5416_spectral.c 244950 2013-01-02 03:56:20Z adrian $
+ */
+#include "opt_ah.h"
+
+#include "ah.h"
+#include "ah_internal.h"
+#include "ah_devid.h"
+#include "ah_desc.h" /* NB: for HAL_PHYERR* */
+
+#include "ar5416/ar5416.h"
+#include "ar5416/ar5416reg.h"
+#include "ar5416/ar5416phy.h"
+
+/*
+ * Default AR9280 spectral scan parameters
+ */
+#define AR5416_SPECTRAL_SCAN_ENA 0
+#define AR5416_SPECTRAL_SCAN_ACTIVE 0
+#define AR5416_SPECTRAL_SCAN_FFT_PERIOD 8
+#define AR5416_SPECTRAL_SCAN_PERIOD 1
+#define AR5416_SPECTRAL_SCAN_COUNT 16 //used to be 128
+#define AR5416_SPECTRAL_SCAN_SHORT_REPEAT 1
+
+/* constants */
+#define MAX_RADAR_RSSI_THRESH 0x3f
+#define MAX_RADAR_HEIGHT 0x3f
+#define ENABLE_ALL_PHYERR 0xffffffff
+
+static void ar5416DisableRadar(struct ath_hal *ah);
+static void ar5416PrepSpectralScan(struct ath_hal *ah);
+
+static void
+ar5416DisableRadar(struct ath_hal *ah)
+{
+ uint32_t val;
+
+ // Enable radar FFT
+ val = OS_REG_READ(ah, AR_PHY_RADAR_0);
+ val |= AR_PHY_RADAR_0_FFT_ENA;
+
+ // set radar detect thresholds to max to effectively disable radar
+ val &= ~AR_PHY_RADAR_0_RRSSI;
+ val |= SM(MAX_RADAR_RSSI_THRESH, AR_PHY_RADAR_0_RRSSI);
+
+ val &= ~AR_PHY_RADAR_0_HEIGHT;
+ val |= SM(MAX_RADAR_HEIGHT, AR_PHY_RADAR_0_HEIGHT);
+
+ val &= ~(AR_PHY_RADAR_0_ENA);
+ OS_REG_WRITE(ah, AR_PHY_RADAR_0, val);
+
+ // disable extension radar detect
+ val = OS_REG_READ(ah, AR_PHY_RADAR_EXT);
+ OS_REG_WRITE(ah, AR_PHY_RADAR_EXT, val & ~AR_PHY_RADAR_EXT_ENA);
+
+ val = OS_REG_READ(ah, AR_RX_FILTER);
+ val |= (1<<13);
+ OS_REG_WRITE(ah, AR_RX_FILTER, val);
+}
+
+static void
+ar5416PrepSpectralScan(struct ath_hal *ah)
+{
+
+ ar5416DisableRadar(ah);
+ OS_REG_WRITE(ah, AR_PHY_ERR, ENABLE_ALL_PHYERR);
+}
+
+void
+ar5416ConfigureSpectralScan(struct ath_hal *ah, HAL_SPECTRAL_PARAM *ss)
+{
+ uint32_t val;
+
+ ar5416PrepSpectralScan(ah);
+
+ val = OS_REG_READ(ah, AR_PHY_SPECTRAL_SCAN);
+
+ if (ss->ss_fft_period != HAL_SPECTRAL_PARAM_NOVAL) {
+ val &= ~AR_PHY_SPECTRAL_SCAN_FFT_PERIOD;
+ val |= SM(ss->ss_fft_period, AR_PHY_SPECTRAL_SCAN_FFT_PERIOD);
+ }
+
+ if (ss->ss_period != HAL_SPECTRAL_PARAM_NOVAL) {
+ val &= ~AR_PHY_SPECTRAL_SCAN_PERIOD;
+ val |= SM(ss->ss_period, AR_PHY_SPECTRAL_SCAN_PERIOD);
+ }
+
+ if (ss->ss_period != HAL_SPECTRAL_PARAM_NOVAL) {
+ val &= ~AR_PHY_SPECTRAL_SCAN_PERIOD;
+ val |= SM(ss->ss_period, AR_PHY_SPECTRAL_SCAN_PERIOD);
+ }
+
+ /* This section is different for Kiwi and Merlin */
+ if (AR_SREV_MERLIN(ah) ) {
+ if (ss->ss_count != HAL_SPECTRAL_PARAM_NOVAL) {
+ val &= ~AR_PHY_SPECTRAL_SCAN_COUNT;
+ val |= SM(ss->ss_count, AR_PHY_SPECTRAL_SCAN_COUNT);
+ }
+
+ if (ss->ss_short_report == AH_TRUE) {
+ val |= AR_PHY_SPECTRAL_SCAN_SHORT_REPEAT;
+ } else if (ss->ss_short_report != HAL_SPECTRAL_PARAM_NOVAL) {
+ val &= ~AR_PHY_SPECTRAL_SCAN_SHORT_REPEAT;
+ }
+ } else {
+ if (ss->ss_count != HAL_SPECTRAL_PARAM_NOVAL) {
+ /*
+ * In Merlin, for continous scan, scan_count = 128.
+ * In case of Kiwi, this value should be 0
+ */
+ if (ss->ss_count == 128)
+ ss->ss_count = 0;
+ val &= ~AR_PHY_SPECTRAL_SCAN_COUNT_KIWI;
+ val |= SM(ss->ss_count, AR_PHY_SPECTRAL_SCAN_COUNT_KIWI);
+ }
+
+ if (ss->ss_short_report == AH_TRUE) {
+ val |= AR_PHY_SPECTRAL_SCAN_SHORT_REPEAT_KIWI;
+ } else if (ss->ss_short_report != HAL_SPECTRAL_PARAM_NOVAL) {
+ val &= ~AR_PHY_SPECTRAL_SCAN_SHORT_REPEAT_KIWI;
+ }
+
+ //Select the mask to be same as before
+ val |= AR_PHY_SPECTRAL_SCAN_PHYERR_MASK_SELECT_KIWI;
+ }
+ // Enable spectral scan
+ OS_REG_WRITE(ah, AR_PHY_SPECTRAL_SCAN, val | AR_PHY_SPECTRAL_SCAN_ENA);
+
+ ar5416GetSpectralParams(ah, ss);
+}
+
+/*
+ * Get the spectral parameter values and return them in the pe
+ * structure
+ */
+void
+ar5416GetSpectralParams(struct ath_hal *ah, HAL_SPECTRAL_PARAM *ss)
+{
+ uint32_t val;
+
+ val = OS_REG_READ(ah, AR_PHY_SPECTRAL_SCAN);
+
+ ss->ss_fft_period = MS(val, AR_PHY_SPECTRAL_SCAN_FFT_PERIOD);
+ ss->ss_period = MS(val, AR_PHY_SPECTRAL_SCAN_PERIOD);
+ if (AR_SREV_MERLIN(ah) ) {
+ ss->ss_count = MS(val, AR_PHY_SPECTRAL_SCAN_COUNT);
+ ss->ss_short_report = MS(val, AR_PHY_SPECTRAL_SCAN_SHORT_REPEAT);
+ } else {
+ ss->ss_count = MS(val, AR_PHY_SPECTRAL_SCAN_COUNT_KIWI);
+ ss->ss_short_report = MS(val, AR_PHY_SPECTRAL_SCAN_SHORT_REPEAT_KIWI);
+ }
+ val = OS_REG_READ(ah, AR_PHY_RADAR_1);
+ ss->radar_bin_thresh_sel = MS(val, AR_PHY_RADAR_1_BIN_THRESH_SELECT);
+}
+
+HAL_BOOL
+ar5416IsSpectralActive(struct ath_hal *ah)
+{
+ uint32_t val;
+
+ val = OS_REG_READ(ah, AR_PHY_SPECTRAL_SCAN);
+ return MS(val, AR_PHY_SPECTRAL_SCAN_ACTIVE);
+}
+
+HAL_BOOL
+ar5416IsSpectralEnabled(struct ath_hal *ah)
+{
+ uint32_t val;
+
+ val = OS_REG_READ(ah, AR_PHY_SPECTRAL_SCAN);
+ return MS(val,AR_PHY_SPECTRAL_SCAN_ENA);
+}
+
+void
+ar5416StartSpectralScan(struct ath_hal *ah)
+{
+ uint32_t val;
+
+ ar5416PrepSpectralScan(ah);
+
+ // Activate spectral scan
+ val = OS_REG_READ(ah, AR_PHY_SPECTRAL_SCAN);
+ val |= AR_PHY_SPECTRAL_SCAN_ENA;
+ val |= AR_PHY_SPECTRAL_SCAN_ACTIVE;
+ OS_REG_WRITE(ah, AR_PHY_SPECTRAL_SCAN, val);
+ val = OS_REG_READ(ah, AR_PHY_SPECTRAL_SCAN);
+ val = OS_REG_READ(ah, AR_PHY_ERR_MASK_REG);
+ OS_REG_WRITE(ah, AR_PHY_ERR_MASK_REG, val | AR_PHY_ERR_RADAR);
+}
+
+void
+ar5416StopSpectralScan(struct ath_hal *ah)
+{
+ uint32_t val;
+ val = OS_REG_READ(ah, AR_PHY_SPECTRAL_SCAN);
+
+ // Deactivate spectral scan
+ val &= ~AR_PHY_SPECTRAL_SCAN_ENA;
+ val &= ~AR_PHY_SPECTRAL_SCAN_ACTIVE;
+ OS_REG_WRITE(ah, AR_PHY_SPECTRAL_SCAN, val);
+ val = OS_REG_READ(ah, AR_PHY_SPECTRAL_SCAN);
+ val = OS_REG_READ(ah, AR_PHY_ERR_MASK_REG) & (~AR_PHY_ERR_RADAR);
+ OS_REG_WRITE(ah, AR_PHY_ERR_MASK_REG, val);
+}
+
+uint32_t
+ar5416GetSpectralConfig(struct ath_hal *ah)
+{
+ uint32_t val;
+
+ val = OS_REG_READ(ah, AR_PHY_SPECTRAL_SCAN);
+ return val;
+}
+
+void
+ar5416RestoreSpectralConfig(struct ath_hal *ah, uint32_t restoreval)
+{
+ uint32_t curval;
+
+ ar5416PrepSpectralScan(ah);
+
+ curval = OS_REG_READ(ah, AR_PHY_SPECTRAL_SCAN);
+
+ if (restoreval != curval) {
+ restoreval |= AR_PHY_SPECTRAL_SCAN_SHORT_REPEAT;
+ OS_REG_WRITE(ah, AR_PHY_SPECTRAL_SCAN, restoreval);
+ }
+ return;
+}
+
Property changes on: trunk/sys/dev/ath/ath_hal/ar5416/ar5416_spectral.c
___________________________________________________________________
Added: svn:eol-style
## -0,0 +1 ##
+native
\ No newline at end of property
Added: svn:keywords
## -0,0 +1 ##
+MidnightBSD=%H
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+text/plain
\ No newline at end of property
More information about the Midnightbsd-cvs
mailing list