[Midnightbsd-cvs] src [10173] trunk/sys/amd64/pci/pci_cfgreg.c: sync with freebsd 10 stable

[laffer1 at midnightbsd.org]

Revision: 10173
          http://svnweb.midnightbsd.org/src/?rev=10173
Author:   laffer1
Date:     2018-06-01 18:54:48 -0400 (Fri, 01 Jun 2018)
Log Message:
-----------
 sync with freebsd 10 stable

Modified Paths:
--------------
    trunk/sys/amd64/pci/pci_cfgreg.c

Modified: trunk/sys/amd64/pci/pci_cfgreg.c
===================================================================
--- trunk/sys/amd64/pci/pci_cfgreg.c	2018-06-01 22:54:07 UTC (rev 10172)
+++ trunk/sys/amd64/pci/pci_cfgreg.c	2018-06-01 22:54:48 UTC (rev 10173)
@@ -1,3 +1,4 @@
+/* $MidnightBSD$ */
 /*-
  * Copyright (c) 1997, Stefan Esser <se at freebsd.org>
  * Copyright (c) 2000, Michael Smith <msmith at freebsd.org>
@@ -27,7 +28,7 @@
  */
 
 #include <sys/cdefs.h>
-__MBSDID("$MidnightBSD$");
+__FBSDID("$FreeBSD: stable/10/sys/amd64/pci/pci_cfgreg.c 318208 2017-05-12 03:44:20Z sephe $");
 
 #include <sys/param.h>
 #include <sys/systm.h>
@@ -64,6 +65,7 @@
 static int pcie_minbus, pcie_maxbus;
 static uint32_t pcie_badslots;
 static struct mtx pcicfg_mtx;
+MTX_SYSINIT(pcicfg_mtx, &pcicfg_mtx, "pcicfg_mtx", MTX_SPIN);
 static int mcfg_enable = 1;
 TUNABLE_INT("hw.pci.mcfg", &mcfg_enable);
 SYSCTL_INT(_hw_pci, OID_AUTO, mcfg, CTLFLAG_RDTUN, &mcfg_enable, 0,
@@ -75,15 +77,9 @@
 int
 pci_cfgregopen(void)
 {
-	static int once = 0;
 	uint64_t pciebar;
 	uint16_t did, vid;
 
-	if (!once) {
-		mtx_init(&pcicfg_mtx, "pcicfg", NULL, MTX_SPIN);
-		once = 1;
-	}
-
 	if (cfgmech != CFGMECH_NONE)
 		return (1);
 	cfgmech = CFGMECH_1;
@@ -139,6 +135,9 @@
 {
 	uint32_t line;
 
+	if (cfgmech == CFGMECH_NONE)
+		return (0xffffffff);
+
 	/*
 	 * Some BIOS writers seem to want to ignore the spec and put
 	 * 0 in the intline rather than 255 to indicate none.  Some use
@@ -163,6 +162,9 @@
 pci_cfgregwrite(int bus, int slot, int func, int reg, u_int32_t data, int bytes)
 {
 
+	if (cfgmech == CFGMECH_NONE)
+		return;
+
 	if (cfgmech == CFGMECH_PCIE &&
 	    (bus >= pcie_minbus && bus <= pcie_maxbus) &&
 	    (bus != 0 || !(1 << slot & pcie_badslots)))
@@ -184,7 +186,7 @@
 	if (bus <= PCI_BUSMAX && slot <= PCI_SLOTMAX && func <= PCI_FUNCMAX &&
 	    (unsigned)reg <= PCI_REGMAX && bytes != 3 &&
 	    (unsigned)bytes <= 4 && (reg & (bytes - 1)) == 0) {
-		outl(CONF1_ADDR_PORT, (1 << 31) | (bus << 16) | (slot << 11) 
+		outl(CONF1_ADDR_PORT, (1U << 31) | (bus << 16) | (slot << 11) 
 		    | (func << 8) | (reg & ~0x03));
 		dataport = CONF1_DATA_PORT + (reg & 0x03);
 	}
@@ -295,6 +297,13 @@
 	return (1);
 }
 
+#define PCIE_VADDR(base, reg, bus, slot, func)	\
+	((base)				+	\
+	((((bus) & 0xff) << 20)		|	\
+	(((slot) & 0x1f) << 15)		|	\
+	(((func) & 0x7) << 12)		|	\
+	((reg) & 0xfff)))
+
 /*
  * AMD BIOS And Kernel Developer's Guides for CPU families starting with 10h
  * have a requirement that all accesses to the memory mapped PCI configuration
@@ -302,18 +311,12 @@
  * Since other vendors do not currently have any contradicting requirements
  * the AMD access pattern is applied universally.
  */
-#define PCIE_VADDR(base, reg, bus, slot, func)	\
-	((base)				+	\
-	((((bus) & 0xff) << 20)		|	\
-	(((slot) & 0x1f) << 15)		|	\
-	(((func) & 0x7) << 12)		|	\
-	((reg) & 0xfff)))
 
 static int
 pciereg_cfgread(int bus, unsigned slot, unsigned func, unsigned reg,
     unsigned bytes)
 {
-	volatile vm_offset_t va;
+	vm_offset_t va;
 	int data = -1;
 
 	if (bus < pcie_minbus || bus > pcie_maxbus || slot > PCI_SLOTMAX ||
@@ -324,16 +327,16 @@
 
 	switch (bytes) {
 	case 4:
-		__asm __volatile("mov %1, %%eax" : "=a" (data)
-		    : "m" (*(uint32_t *)va));
+		__asm("movl %1, %0" : "=a" (data)
+		    : "m" (*(volatile uint32_t *)va));
 		break;
 	case 2:
-		__asm __volatile("movzwl %1, %%eax" : "=a" (data)
-		    : "m" (*(uint16_t *)va));
+		__asm("movzwl %1, %0" : "=a" (data)
+		    : "m" (*(volatile uint16_t *)va));
 		break;
 	case 1:
-		__asm __volatile("movzbl %1, %%eax" : "=a" (data)
-		    : "m" (*(uint8_t *)va));
+		__asm("movzbl %1, %0" : "=a" (data)
+		    : "m" (*(volatile uint8_t *)va));
 		break;
 	}
 
@@ -344,7 +347,7 @@
 pciereg_cfgwrite(int bus, unsigned slot, unsigned func, unsigned reg, int data,
     unsigned bytes)
 {
-	volatile vm_offset_t va;
+	vm_offset_t va;
 
 	if (bus < pcie_minbus || bus > pcie_maxbus || slot > PCI_SLOTMAX ||
 	    func > PCI_FUNCMAX || reg > PCIE_REGMAX)
@@ -354,16 +357,16 @@
 
 	switch (bytes) {
 	case 4:
-		__asm __volatile("mov %%eax, %0" : "=m" (*(uint32_t *)va)
+		__asm("movl %1, %0" : "=m" (*(volatile uint32_t *)va)
 		    : "a" (data));
 		break;
 	case 2:
-		__asm __volatile("mov %%ax, %0" : "=m" (*(uint16_t *)va)
-		    : "a" (data));
+		__asm("movw %1, %0" : "=m" (*(volatile uint16_t *)va)
+		    : "a" ((uint16_t)data));
 		break;
 	case 1:
-		__asm __volatile("mov %%al, %0" : "=m" (*(uint8_t *)va)
-		    : "a" (data));
+		__asm("movb %1, %0" : "=m" (*(volatile uint8_t *)va)
+		    : "a" ((uint8_t)data));
 		break;
 	}
 }