[Midnightbsd-cvs] src [10205] trunk/sys/boot/fdt: sync with freebsd
laffer1 at midnightbsd.org
laffer1 at midnightbsd.org
Sat Jun 2 08:34:50 EDT 2018
Revision: 10205
http://svnweb.midnightbsd.org/src/?rev=10205
Author: laffer1
Date: 2018-06-02 08:34:49 -0400 (Sat, 02 Jun 2018)
Log Message:
-----------
sync with freebsd
Modified Paths:
--------------
trunk/sys/boot/fdt/Makefile
trunk/sys/boot/fdt/dts/bindings-gpio.txt
trunk/sys/boot/fdt/dts/bindings-mpp.txt
trunk/sys/boot/fdt/dts/db78100.dts
trunk/sys/boot/fdt/dts/db88f5182.dts
trunk/sys/boot/fdt/dts/db88f5281.dts
trunk/sys/boot/fdt/dts/db88f6281.dts
trunk/sys/boot/fdt/dts/dockstar.dts
trunk/sys/boot/fdt/dts/mpc8555cds.dts
trunk/sys/boot/fdt/dts/mpc8572ds.dts
trunk/sys/boot/fdt/dts/sheevaplug.dts
trunk/sys/boot/fdt/dts/ts7800.dts
trunk/sys/boot/fdt/fdt_loader_cmd.c
Added Paths:
-----------
trunk/sys/boot/fdt/dts/arm/
trunk/sys/boot/fdt/dts/arm/am335x-evm.dts
trunk/sys/boot/fdt/dts/arm/am335x.dtsi
trunk/sys/boot/fdt/dts/arm/apalis-imx6.dts
trunk/sys/boot/fdt/dts/arm/bcm2835.dtsi
trunk/sys/boot/fdt/dts/arm/beaglebone-black.dts
trunk/sys/boot/fdt/dts/arm/beaglebone.dts
trunk/sys/boot/fdt/dts/arm/cubieboard.dts
trunk/sys/boot/fdt/dts/arm/cubieboard2.dts
trunk/sys/boot/fdt/dts/arm/db78100.dts
trunk/sys/boot/fdt/dts/arm/db78460.dts
trunk/sys/boot/fdt/dts/arm/db88f5182.dts
trunk/sys/boot/fdt/dts/arm/db88f5281.dts
trunk/sys/boot/fdt/dts/arm/db88f6281.dts
trunk/sys/boot/fdt/dts/arm/digi-ccwmx53.dts
trunk/sys/boot/fdt/dts/arm/dockstar.dts
trunk/sys/boot/fdt/dts/arm/dreamplug-1001.dts
trunk/sys/boot/fdt/dts/arm/dreamplug-1001N.dts
trunk/sys/boot/fdt/dts/arm/ea3250.dts
trunk/sys/boot/fdt/dts/arm/efikamx.dts
trunk/sys/boot/fdt/dts/arm/exynos5.dtsi
trunk/sys/boot/fdt/dts/arm/exynos5250-arndale.dts
trunk/sys/boot/fdt/dts/arm/exynos5250-chromebook.dts
trunk/sys/boot/fdt/dts/arm/exynos5250.dtsi
trunk/sys/boot/fdt/dts/arm/exynos5420-arndale-octa.dts
trunk/sys/boot/fdt/dts/arm/exynos5420.dtsi
trunk/sys/boot/fdt/dts/arm/hl201.dts
trunk/sys/boot/fdt/dts/arm/imx51x.dtsi
trunk/sys/boot/fdt/dts/arm/imx53-qsb.dts
trunk/sys/boot/fdt/dts/arm/imx53x.dtsi
trunk/sys/boot/fdt/dts/arm/imx6.dtsi
trunk/sys/boot/fdt/dts/arm/p2041rdb.dts
trunk/sys/boot/fdt/dts/arm/p3041ds.dts
trunk/sys/boot/fdt/dts/arm/p5020ds.dts
trunk/sys/boot/fdt/dts/arm/pandaboard.dts
trunk/sys/boot/fdt/dts/arm/rk3188-radxa.dts
trunk/sys/boot/fdt/dts/arm/rk3188.dtsi
trunk/sys/boot/fdt/dts/arm/rpi.dts
trunk/sys/boot/fdt/dts/arm/sheevaplug.dts
trunk/sys/boot/fdt/dts/arm/sun4i-a10.dtsi
trunk/sys/boot/fdt/dts/arm/sun7i-a20.dtsi
trunk/sys/boot/fdt/dts/arm/tegra20-paz00.dts
trunk/sys/boot/fdt/dts/arm/tegra20.dtsi
trunk/sys/boot/fdt/dts/arm/trimslice.dts
trunk/sys/boot/fdt/dts/arm/ts7800.dts
trunk/sys/boot/fdt/dts/arm/versatilepb.dts
trunk/sys/boot/fdt/dts/arm/vybrid-colibri-vf50.dts
trunk/sys/boot/fdt/dts/arm/vybrid-cosmic.dts
trunk/sys/boot/fdt/dts/arm/vybrid-quartz.dts
trunk/sys/boot/fdt/dts/arm/vybrid.dtsi
trunk/sys/boot/fdt/dts/arm/wandboard-dual.dts
trunk/sys/boot/fdt/dts/arm/wandboard-quad.dts
trunk/sys/boot/fdt/dts/arm/wandboard-solo.dts
trunk/sys/boot/fdt/dts/arm/zedboard.dts
trunk/sys/boot/fdt/dts/bindings-localbus.txt
trunk/sys/boot/fdt/dts/mips/
trunk/sys/boot/fdt/dts/mips/beri-netfpga.dts
trunk/sys/boot/fdt/dts/mips/beri-sim.dts
trunk/sys/boot/fdt/dts/mips/beripad-de4.dts
trunk/sys/boot/fdt/dts/mips/xlp-basic.dts
trunk/sys/boot/fdt/dts/powerpc/
trunk/sys/boot/fdt/dts/powerpc/mpc8555cds.dts
trunk/sys/boot/fdt/dts/powerpc/mpc8572ds.dts
trunk/sys/boot/fdt/dts/powerpc/p1020rdb.dts
trunk/sys/boot/fdt/dts/powerpc/p2020ds.dts
trunk/sys/boot/fdt/dts/powerpc/p2041si.dtsi
trunk/sys/boot/fdt/dts/powerpc/p3041si.dtsi
trunk/sys/boot/fdt/dts/powerpc/p5020si.dtsi
trunk/sys/boot/fdt/fdt_platform.h
trunk/sys/boot/fdt/help.fdt
Modified: trunk/sys/boot/fdt/Makefile
===================================================================
--- trunk/sys/boot/fdt/Makefile 2018-06-02 00:06:07 UTC (rev 10204)
+++ trunk/sys/boot/fdt/Makefile 2018-06-02 12:34:49 UTC (rev 10205)
@@ -1,5 +1,5 @@
# $MidnightBSD$
-# $FreeBSD$
+# $FreeBSD: stable/10/sys/boot/fdt/Makefile 275763 2014-12-14 15:33:45Z andrew $
.PATH: ${.CURDIR}/../../contrib/libfdt/
@@ -12,8 +12,7 @@
# Loader's fdt commands extension sources.
SRCS+= fdt_loader_cmd.c
-CFLAGS+= -I${.CURDIR}/../../contrib/libfdt/ -I${.CURDIR}/../common/ \
- -I${.CURDIR}/../uboot/lib
+CFLAGS+= -I${.CURDIR}/../../contrib/libfdt/ -I${.CURDIR}/../common/
CFLAGS+= -ffreestanding
Added: trunk/sys/boot/fdt/dts/arm/am335x-evm.dts
===================================================================
--- trunk/sys/boot/fdt/dts/arm/am335x-evm.dts (rev 0)
+++ trunk/sys/boot/fdt/dts/arm/am335x-evm.dts 2018-06-02 12:34:49 UTC (rev 10205)
@@ -0,0 +1,184 @@
+/* $MidnightBSD$ */
+/*-
+ * Copyright (c) 2012 Damjan Marion <dmarion at Freebsd.org>
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ * $FreeBSD: stable/10/sys/boot/fdt/dts/arm/am335x-evm.dts 262614 2014-02-28 18:29:09Z imp $
+ */
+
+/dts-v1/;
+
+/include/ "am335x.dtsi"
+
+/ {
+ model = "TMDXEVM3358";
+ compatible = "ti,am335x";
+
+ aliases {
+ soc = &SOC;
+ uart0 = &uart0;
+ };
+
+ memory {
+ device_type = "memory";
+ reg = < 0x80000000 0x10000000 >; /* 256MB RAM */
+ };
+
+ am335x {
+ scm at 44e10000 {
+ /* Set of triplets < padname, muxname, padstate> */
+ scm-pad-config =
+ /* I2C0 */
+ "I2C0_SDA", "I2C0_SDA","i2c",
+ "I2C0_SCL", "I2C0_SCL","i2c",
+ /* Ethernet */
+ "MII1_RX_ER", "gmii1_rxerr", "input_pulldown",
+ "MII1_TX_EN", "gmii1_txen", "output",
+ "MII1_RX_DV", "gmii1_rxdv", "input_pulldown",
+ "MII1_TXD3", "gmii1_txd3", "output",
+ "MII1_TXD2", "gmii1_txd2", "output",
+ "MII1_TXD1", "gmii1_txd1", "output",
+ "MII1_TXD0", "gmii1_txd0", "output",
+ "MII1_TX_CLK", "gmii1_txclk", "input_pulldown",
+ "MII1_RX_CLK", "gmii1_rxclk", "input_pulldown",
+ "MII1_RXD3", "gmii1_rxd3", "input_pulldown",
+ "MII1_RXD2", "gmii1_rxd2", "input_pulldown",
+ "MII1_RXD1", "gmii1_rxd1", "input_pulldown",
+ "MII1_RXD0", "gmii1_rxd0", "input_pulldown",
+ "MDIO", "mdio_data", "input_pullup",
+ "MDC", "mdio_clk", "output_pullup",
+ /* MMCSD0 */
+ "MMC0_CMD", "mmc0_cmd", "input_pullup",
+ "MMC0_CLK", "mmc0_clk", "input_pullup",
+ "MMC0_DAT0", "mmc0_dat0", "input_pullup",
+ "MMC0_DAT1", "mmc0_dat1", "input_pullup",
+ "MMC0_DAT2", "mmc0_dat2", "input_pullup",
+ "MMC0_DAT3", "mmc0_dat3", "input_pullup",
+ /* GPIO */
+ "GPMC_AD10", "gpio0_26", "input_pulldown",
+ "GPMC_AD11", "gpio0_27", "input_pulldown",
+ "GPMC_AD0", "gpio1_0", "input_pulldown",
+ "GPMC_AD1", "gpio1_1", "input_pulldown",
+ "GPMC_AD2", "gpio1_2", "input_pulldown",
+ "GPMC_AD3", "gpio1_3", "input_pulldown",
+ "GPMC_AD4", "gpio1_4", "input_pulldown",
+ "GPMC_AD5", "gpio1_5", "input_pulldown",
+ "GPMC_AD6", "gpio1_6", "input_pulldown",
+ "GPMC_AD7", "gpio1_7", "input_pulldown",
+ "GPMC_AD12", "gpio1_12", "input_pulldown",
+ "GPMC_AD13", "gpio1_13", "input_pulldown",
+ "GPMC_AD14", "gpio1_14", "input_pulldown",
+ "GPMC_AD15", "gpio1_15", "input_pulldown",
+ "GPMC_A0", "gpio1_16", "input_pulldown",
+ "GPMC_A1", "gpio1_17", "input_pulldown",
+ "GPMC_A5", "gpio1_21", "output", /* User LED 1 */
+ "GPMC_A6", "gpio1_22", "output", /* User LED 2 */
+ "GPMC_A7", "gpio1_23", "output", /* User LED 3 */
+ "GPMC_A8", "gpio1_24", "output", /* User LED 4 */
+ "GPMC_BEn1", "gpio1_28", "input_pulldown",
+ "GPMC_CSn0", "gpio1_29", "input_pulldown",
+ "GPMC_CSn1", "gpio1_30", "input_pulldown",
+ "GPMC_CSn2", "gpio1_31", "input_pulldown",
+ "MCASP0_FSR", "gpio3_19", "input_pulldown",
+ "MCASP0_AHCLKX", "gpio3_21", "input_pulldown",
+ /* TIMERs */
+ "GPMC_ADVn_ALE", "timer4", "output",
+ "GPMC_BEn0_CLE", "timer5", "output",
+ "GPMC_WEn", "timer6", "output",
+ "GPMC_OEn_REn", "timer7", "output",
+ /* USB0 and USB1 */
+ "USB0_DRVVBUS", "USB0_DRVVBUS", "output",
+ "USB1_DRVVBUS", "USB1_DRVVBUS", "output",
+ /* LCD */
+ "GPMC_AD8", "lcd_data23", "output",
+ "GPMC_AD9", "lcd_data22", "output",
+ "GPMC_AD10", "lcd_data21", "output",
+ "GPMC_AD11", "lcd_data20", "output",
+ "GPMC_AD12", "lcd_data19", "output",
+ "GPMC_AD13", "lcd_data18", "output",
+ "GPMC_AD14", "lcd_data17", "output",
+ "GPMC_AD15", "lcd_data16", "output",
+ "GPMC_CLK", "lcd_memory_clk", "output",
+ "LCD_DATA0", "lcd_data0", "output",
+ "LCD_DATA1", "lcd_data1", "output",
+ "LCD_DATA2", "lcd_data2", "output",
+ "LCD_DATA3", "lcd_data3", "output",
+ "LCD_DATA4", "lcd_data4", "output",
+ "LCD_DATA5", "lcd_data5", "output",
+ "LCD_DATA6", "lcd_data6", "output",
+ "LCD_DATA7", "lcd_data7", "output",
+ "LCD_DATA8", "lcd_data8", "output",
+ "LCD_DATA9", "lcd_data9", "output",
+ "LCD_DATA10", "lcd_data10", "output",
+ "LCD_DATA11", "lcd_data11", "output",
+ "LCD_DATA12", "lcd_data12", "output",
+ "LCD_DATA13", "lcd_data13", "output",
+ "LCD_DATA14", "lcd_data14", "output",
+ "LCD_DATA15", "lcd_data15", "output",
+ "LCD_VSYNC", "lcd_vsync", "output",
+ "LCD_HSYNC", "lcd_hsync", "output",
+ "LCD_PCLK", "lcd_pclk", "output",
+ "LCD_AC_BIAS_EN", "lcd_ac_bias_en", "output",
+ "ECAP0_IN_PWM0_OUT", "eCAP0_in_PWM0_out", "output";
+
+ };
+
+ lcd at 4830e000 {
+ panel_name = "TFC_S9700RTWV35TR_01B";
+ panel_width = <800>;
+ panel_height = <480>;
+ panel_hfp = <39>;
+ panel_hbp = <39>;
+ panel_hsw = <47>;
+ panel_vfp = <13>;
+ panel_vbp = <29>;
+ panel_vsw = <2>;
+ panel_pxl_clk = <30000000>;
+ panel_invert_pxl_clk = <0>;
+ panel_type = <1>; /* Active or passive, compatibility */
+ panel_max_bpp = <32>; /* compatibility */
+ panel_min_bpp = <32>; /* compatibility */
+ panel_shade = <1>; /* compatibility */
+ ac_bias = <255>;
+ ac_bias_intrpt = <0>;
+ dma_burst_sz = <16>;
+ bpp = <32>;
+ fdd = <128>;
+ tft_alt_mode = <0>; /* compatiblity */
+ stn_565_mode = <0>; /* compatibility */
+ mono_8bit_mode = <0>; /* compatibilty */
+ invert_line_clock = <1>;
+ invert_frm_clock = <1>;
+ sync_edge = <0>;
+ sync_ctrl = <1>;
+ raster_order = <0>; /* compatibity */
+ };
+
+ };
+
+ chosen {
+ stdin = "uart0";
+ stdout = "uart0";
+ };
+};
Property changes on: trunk/sys/boot/fdt/dts/arm/am335x-evm.dts
___________________________________________________________________
Added: svn:eol-style
## -0,0 +1 ##
+native
\ No newline at end of property
Added: svn:keywords
## -0,0 +1 ##
+MidnightBSD=%H
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+text/plain
\ No newline at end of property
Added: trunk/sys/boot/fdt/dts/arm/am335x.dtsi
===================================================================
--- trunk/sys/boot/fdt/dts/arm/am335x.dtsi (rev 0)
+++ trunk/sys/boot/fdt/dts/arm/am335x.dtsi 2018-06-02 12:34:49 UTC (rev 10205)
@@ -0,0 +1,343 @@
+/* $MidnightBSD$ */
+/*-
+ * Copyright (c) 2012 Damjan Marion <dmarion at Freebsd.org>
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ * $FreeBSD: stable/10/sys/boot/fdt/dts/arm/am335x.dtsi 278079 2015-02-02 12:48:13Z loos $
+ */
+
+/ {
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ interrupt-parent = <&AINTC>;
+
+ SOC: am335x {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "simple-bus";
+ ranges;
+ bus-frequency = <0>;
+
+ AINTC: interrupt-controller at 48200000 {
+ compatible = "ti,aintc";
+ interrupt-controller;
+ #address-cells = <0>;
+ #interrupt-cells = <1>;
+ reg = < 0x48200000 0x1000 >;
+ };
+
+ scm at 44e10000 {
+ compatible = "ti,scm";
+ reg = < 0x44e10000 0x2000 >;
+ };
+
+ prcm at 44E00000 {
+ compatible = "am335x,prcm";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ reg = < 0x44E00000 0x1300 >;
+ };
+
+ dmtimers at 44E05000 {
+ compatible = "ti,am335x-dmtimer";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ reg = < 0x44E05000 0x1000
+ 0x44E31000 0x1000
+ 0x48040000 0x1000
+ 0x48042000 0x1000
+ 0x48044000 0x1000
+ 0x48046000 0x1000
+ 0x48048000 0x1000
+ 0x4804A000 0x1000 >;
+ interrupts = < 66 67 68 69 92 93 94 95 >;
+ interrupt-parent = <&AINTC>;
+ };
+
+ rtc: rtc at 44E3E000 {
+ compatible = "ti,da830-rtc";
+ reg = <0x44E3E000 0x1000>;
+ interrupts = < 75 76 >;
+ interrupt-parent = <&AINTC>;
+ };
+
+ adc0: adc at 44E0D000 {
+ compatible = "ti,adc";
+ reg = <0x44E0D000 0x2000>;
+ interrupts = < 16 >;
+ interrupt-parent = <&AINTC>;
+ };
+
+ wdt1 at 44E35000 {
+ compatible = "ti,omap3-wdt";
+ reg = <0x44E35000 0x1000>;
+ interrupts = <91>;
+ interrupt-parent = <&AINTC>;
+ };
+
+ GPIO: gpio {
+ #gpio-cells = <3>;
+ compatible = "ti,gpio";
+ gpio-controller;
+ reg =< 0x44E07000 0x1000
+ 0x4804C000 0x1000
+ 0x481AC000 0x1000
+ 0x481AE000 0x1000 >;
+ interrupts = < 96 97 98 99 32 33 62 63 >;
+ interrupt-parent = <&AINTC>;
+ };
+
+ uart0: serial at 44E09000 {
+ compatible = "ti,ns16550";
+ reg = <0x44E09000 0x1000>;
+ reg-shift = <2>;
+ interrupts = < 72 >;
+ interrupt-parent = <&AINTC>;
+ clock-frequency = < 48000000 >;
+ uart-device-id = < 0 >;
+ };
+
+ uart1: serial at 48022000 {
+ compatible = "ti,ns16550";
+ reg = <0x48022000 0x1000>;
+ reg-shift = <2>;
+ interrupts = < 73 >;
+ interrupt-parent = <&AINTC>;
+ clock-frequency = < 48000000 >;
+ uart-device-id = < 1 >;
+ status = "disabled";
+ };
+
+ uart2: serial at 48024000 {
+ compatible = "ti,ns16550";
+ reg = <0x48024000 0x1000>;
+ reg-shift = <2>;
+ interrupts = < 74 >;
+ interrupt-parent = <&AINTC>;
+ clock-frequency = < 48000000 >;
+ uart-device-id = < 2 >;
+ status = "disabled";
+ };
+
+ uart3: serial at 481a6000 {
+ compatible = "ti,ns16550";
+ reg = <0x481A6000 0x1000>;
+ reg-shift = <2>;
+ interrupts = < 44 >;
+ interrupt-parent = <&AINTC>;
+ clock-frequency = < 48000000 >;
+ uart-device-id = < 3 >;
+ status = "disabled";
+ };
+
+ uart4: serial at 481a8000 {
+ compatible = "ti,ns16550";
+ reg = <0x481A8000 0x1000>;
+ reg-shift = <2>;
+ interrupts = < 45 >;
+ interrupt-parent = <&AINTC>;
+ clock-frequency = < 48000000 >;
+ uart-device-id = < 4 >;
+ status = "disabled";
+ };
+
+ uart5: serial at 481aa000 {
+ compatible = "ti,ns16550";
+ reg = <0x481AA000 0x1000>;
+ reg-shift = <2>;
+ interrupts = < 46 >;
+ interrupt-parent = <&AINTC>;
+ clock-frequency = < 48000000 >;
+ uart-device-id = < 5 >;
+ status = "disabled";
+ };
+
+ edma3 at 49000000 {
+ compatible = "ti,edma3";
+ reg =< 0x49000000 0x100000 /* Channel Controller Regs */
+ 0x49800000 0x100000 /* Transfer Controller 0 Regs */
+ 0x49900000 0x100000 /* Transfer Controller 1 Regs */
+ 0x49a00000 0x100000 >; /* Transfer Controller 2 Regs */
+ interrupts = <12 13 14>;
+ interrupt-parent = <&AINTC>;
+ };
+
+ mmchs0 at 48060000 {
+ compatible = "ti,omap3-hsmmc", "ti,mmchs";
+ reg =<0x48060000 0x1000 >;
+ interrupts = <64>;
+ interrupt-parent = <&AINTC>;
+ mmchs-device-id = <0>;
+ mmchs-wp-gpio-pin = <0xffffffff>;
+ ti,dual-volt;
+ };
+
+ mmchs1 at 481D8000 {
+ compatible = "ti,omap3-hsmmc", "ti,mmchs";
+ reg =<0x481D8000 0x1000 >;
+ interrupts = <28>;
+ interrupt-parent = <&AINTC>;
+ mmchs-device-id = <1>;
+ mmchs-wp-gpio-pin = <0xffffffff>;
+ status = "disabled";
+ };
+
+ enet0: ethernet at 4A100000 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "ti,cpsw";
+ reg = <0x4A100000 0x4000>;
+ interrupts = <40 41 42 43>;
+ interrupt-parent = <&AINTC>;
+ phy-handle = <&phy0>;
+ mdio at 0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "ti,cpsw-mdio";
+ phy0: ethernet-phy at 0 {
+ reg = <0x0>;
+ };
+ };
+ };
+
+ i2c0: i2c at 44e0b000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "ti,i2c";
+ reg =< 0x44e0b000 0x1000 >;
+ interrupts = <70>;
+ interrupt-parent = <&AINTC>;
+ i2c-device-id = <0>;
+ };
+
+ i2c1: i2c at 4802a000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "ti,i2c";
+ reg =< 0x4802a000 0x1000 >;
+ interrupts = <71>;
+ interrupt-parent = <&AINTC>;
+ i2c-device-id = <1>;
+ };
+
+ i2c2: i2c at 4819c000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "ti,i2c";
+ reg =< 0x4819c000 0x1000 >;
+ interrupts = <30>;
+ interrupt-parent = <&AINTC>;
+ i2c-device-id = <2>;
+ };
+
+ pwm at 48300000 {
+ compatible = "ti,am335x-pwm";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ reg = < 0x48300000 0x100 /* PWMSS0 */
+ 0x48300100 0x80 /* eCAP0 */
+ 0x48300180 0x80 /* eQEP0 */
+ 0x48300200 0x60 /* ePWM0 */
+ >;
+ interrupts = <86 58>; /* ePWM0INT, ePWM0_TZINT */
+ interrupt-parent = <&AINTC>;
+ pwm-device-id = <0>;
+ };
+
+ pwm at 48302000 {
+ compatible = "ti,am335x-pwm";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ reg = < 0x48302000 0x100 /* PWMSS1 */
+ 0x48302100 0x80 /* eCAP1 */
+ 0x48302180 0x80 /* eQEP1 */
+ 0x48302200 0x60 /* ePWM1 */
+ >;
+ interrupts = <87 59>; /* ePWM1INT, ePWM1_TZINT */
+ interrupt-parent = <&AINTC>;
+ pwm-device-id = <1>;
+ };
+
+ pwm at 48304000 {
+ compatible = "ti,am335x-pwm";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ reg = < 0x48304000 0x100 /* PWMSS2 */
+ 0x48304100 0x80 /* eCAP2 */
+ 0x48304180 0x80 /* eQEP2 */
+ 0x48304200 0x60 /* ePWM2 */
+ >;
+ interrupts = <88 60>; /* ePWM2INT, ePWM2_TZINT */
+ interrupt-parent = <&AINTC>;
+ pwm-device-id = <2>;
+ };
+
+ lcd: lcd at 4830e000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "ti,am335x-lcd";
+ reg =< 0x4830e000 0x1000 >;
+ interrupts = <36>;
+ interrupt-parent = <&AINTC>;
+ };
+
+ usb at 47400000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "ti,musb-am33xx";
+ reg =< 0x47400000 0x1000 /* USBSS */
+ 0x47401000 0x300 /* USB0 */
+ 0x47401300 0x100 /* USB0_PHY */
+ 0x47401400 0x400 /* USB0_CORE */
+ 0x47401800 0x300 /* USB1 */
+ 0x47401B00 0x100 /* USB1_PHY */
+ 0x47401C00 0x400 /* USB1_CORE */
+ >;
+ interrupts = <17 18 19>;
+ interrupt-parent = <&AINTC>;
+ /* 1 - Host Mode, 0 - Device Mode */
+ modemask = <2>;
+ };
+
+ mbox0 at 480C8000 {
+ compatible = "am335x,system-mbox";
+ reg = < 0x480C8000 0x1000 >;
+ interrupts = <77>;
+ interrupt-parent = <&AINTC>;
+ };
+
+ spinlock0 at 480CA000 {
+ compatible = "am335x,spinlock";
+ reg = < 0x480CA000 0x1000 >;
+ };
+
+ pruss at 4A300000 {
+ compatible = "ti,pruss-v2";
+ reg = <0x4A300000 0x80000>;
+ interrupt-parent = <&AINTC>;
+ interrupts = <20 21 22 23 24 25 26 27>;
+ };
+ };
+};
Property changes on: trunk/sys/boot/fdt/dts/arm/am335x.dtsi
___________________________________________________________________
Added: svn:eol-style
## -0,0 +1 ##
+native
\ No newline at end of property
Added: svn:keywords
## -0,0 +1 ##
+MidnightBSD=%H
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+text/plain
\ No newline at end of property
Added: trunk/sys/boot/fdt/dts/arm/apalis-imx6.dts
===================================================================
--- trunk/sys/boot/fdt/dts/arm/apalis-imx6.dts (rev 0)
+++ trunk/sys/boot/fdt/dts/arm/apalis-imx6.dts 2018-06-02 12:34:49 UTC (rev 10205)
@@ -0,0 +1,103 @@
+/* $MidnightBSD$ */
+/*
+ * Copyright (c) 2014-2015 Ruslan Bukin <br at bsdpad.com>
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ * $FreeBSD: stable/10/sys/boot/fdt/dts/arm/apalis-imx6.dts 283500 2015-05-24 18:59:45Z ian $
+ */
+
+#include "imx6q-pinfunc.h"
+
+/dts-v1/;
+/include/ "imx6.dtsi"
+
+/ {
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ model = "Toradex Apalis i.MX6";
+ compatible = "toradex,imx6q-apalis", "fsl,imx6q";
+
+ memory {
+ reg = <0x10000000 0x40000000>; /* RAM 1GB */
+ };
+
+ SOC: soc at 00000000 {
+ aips at 02000000 { /* AIPS1 */
+ iomux at 020e0000 {
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pins_ssi>;
+ pins_ssi: ssi {
+ fsl,pins = <
+ MX6QDL_PAD_DISP0_DAT16__AUD5_TXC 0x130b0
+ MX6QDL_PAD_DISP0_DAT17__AUD5_TXD 0x110b0
+ MX6QDL_PAD_DISP0_DAT18__AUD5_TXFS 0x130b0
+ MX6QDL_PAD_DISP0_DAT19__AUD5_RXD 0x130b0
+ MX6QDL_PAD_GPIO_19__CCM_CLKO1 0x130b0
+ >;
+ };
+ };
+ gpio at 0209c000 { status = "okay"; };
+ gpio at 020a0000 { status = "okay"; };
+ gpio at 020a4000 { status = "okay"; };
+ gpio at 020a8000 { status = "okay"; };
+ gpio at 020ac000 { status = "okay"; };
+ gpio at 020b0000 { status = "okay"; };
+ gpio at 020b4000 { status = "okay"; };
+ console:serial at 02020000 { status = "okay"; };
+ serial at 021e8000 { status = "disabled"; };
+ serial at 021ec000 { status = "disabled"; };
+ serial at 021f0000 { status = "disabled"; };
+ serial at 021f4000 { status = "disabled"; };
+ usbphy at 020c9000 { status = "okay"; };
+ usbphy at 020ca000 { status = "okay"; };
+ ecspi at 02008000 { status = "okay"; };
+ ssi at 02028000 { status = "okay"; };
+ sdma at 020ec000 { status = "okay"; };
+ };
+ aips at 02100000 { /* AIPS2 */
+ ethernet at 02188000 {
+ status = "okay";
+ phy-mode = "rgmii";
+ phy-disable-preamble;
+ };
+ usb at 02184000 { status = "okay"; };
+ usb at 02184200 { status = "okay"; };
+ usb at 02184400 { status = "disabled"; };
+ usb at 02184600 { status = "disabled"; };
+ usdhc at 02190000 { status = "disabled"; };
+ usdhc at 02194000 { status = "okay"; };
+ usdhc at 02198000 { status = "disabled"; };
+ usdhc at 0219c000 { status = "disabled"; };
+ audmux at 021d8000 { status = "okay"; };
+ i2c at 021a0000 { status = "okay"; };
+ };
+ };
+
+ chosen {
+ stdin = &console;
+ stdout = &console;
+ };
+};
Property changes on: trunk/sys/boot/fdt/dts/arm/apalis-imx6.dts
___________________________________________________________________
Added: svn:eol-style
## -0,0 +1 ##
+native
\ No newline at end of property
Added: svn:keywords
## -0,0 +1 ##
+MidnightBSD=%H
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+text/plain
\ No newline at end of property
Added: trunk/sys/boot/fdt/dts/arm/bcm2835.dtsi
===================================================================
--- trunk/sys/boot/fdt/dts/arm/bcm2835.dtsi (rev 0)
+++ trunk/sys/boot/fdt/dts/arm/bcm2835.dtsi 2018-06-02 12:34:49 UTC (rev 10205)
@@ -0,0 +1,497 @@
+/* $MidnightBSD$ */
+/*
+ * Copyright (c) 2012 Oleksandr Tymoshenko <gonzo at bluezbox.com>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ * $FreeBSD: stable/10/sys/boot/fdt/dts/arm/bcm2835.dtsi 279565 2015-03-03 17:03:41Z loos $
+ */
+
+/ {
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ cpus {
+ cpu at 0 {
+ compatible = "arm,1176jzf-s";
+ };
+ };
+
+
+ SOC: axi {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ reg = <0x20000000 0x01000000>;
+ ranges = <0 0x20000000 0x01000000>;
+
+ intc: interrupt-controller {
+ compatible = "broadcom,bcm2835-armctrl-ic",
+ "broadcom,bcm2708-armctrl-ic";
+ reg = <0xB200 0x200>;
+
+ interrupt-controller;
+ #interrupt-cells = <1>;
+
+ /* Bank 0
+ * 0: ARM_TIMER
+ * 1: ARM_MAILBOX
+ * 2: ARM_DOORBELL_0
+ * 3: ARM_DOORBELL_1
+ * 4: VPU0_HALTED
+ * 5: VPU1_HALTED
+ * 6: ILLEGAL_TYPE0
+ * 7: ILLEGAL_TYPE1
+ */
+
+ /* Bank 1
+ * 0: TIMER0 16: DMA0
+ * 1: TIMER1 17: DMA1
+ * 2: TIMER2 18: VC_DMA2
+ * 3: TIMER3 19: VC_DMA3
+ * 4: CODEC0 20: DMA4
+ * 5: CODEC1 21: DMA5
+ * 6: CODEC2 22: DMA6
+ * 7: VC_JPEG 23: DMA7
+ * 8: ISP 24: DMA8
+ * 9: VC_USB 25: DMA9
+ * 10: VC_3D 26: DMA10
+ * 11: TRANSPOSER 27: DMA11
+ * 12: MULTICORESYNC0 28: DMA12
+ * 13: MULTICORESYNC1 29: AUX
+ * 14: MULTICORESYNC2 30: ARM
+ * 15: MULTICORESYNC3 31: VPUDMA
+ */
+
+ /* Bank 2
+ * 0: HOSTPORT 16: SMI
+ * 1: VIDEOSCALER 17: GPIO0
+ * 2: CCP2TX 18: GPIO1
+ * 3: SDC 19: GPIO2
+ * 4: DSI0 20: GPIO3
+ * 5: AVE 21: VC_I2C
+ * 6: CAM0 22: VC_SPI
+ * 7: CAM1 23: VC_I2SPCM
+ * 8: HDMI0 24: VC_SDIO
+ * 9: HDMI1 25: VC_UART
+ * 10: PIXELVALVE1 26: SLIMBUS
+ * 11: I2CSPISLV 27: VEC
+ * 12: DSI1 28: CPG
+ * 13: PWA0 29: RNG
+ * 14: PWA1 30: VC_ARASANSDIO
+ * 15: CPR 31: AVSPMON
+ */
+ };
+
+ timer {
+ compatible = "broadcom,bcm2835-system-timer",
+ "broadcom,bcm2708-system-timer";
+ reg = <0x3000 0x1000>;
+ interrupts = <8 9 10 11>;
+ interrupt-parent = <&intc>;
+
+ clock-frequency = <1000000>;
+ };
+
+ armtimer {
+ /* Not AMBA compatible */
+ compatible = "broadcom,bcm2835-sp804", "arm,sp804";
+ reg = <0xB400 0x24>;
+ interrupts = <0>;
+ interrupt-parent = <&intc>;
+ };
+
+ watchdog0 {
+ compatible = "broadcom,bcm2835-wdt",
+ "broadcom,bcm2708-wdt";
+ reg = <0x10001c 0x0c>; /* 0x1c, 0x20, 0x24 */
+ };
+
+ gpio: gpio {
+ compatible = "broadcom,bcm2835-gpio",
+ "broadcom,bcm2708-gpio";
+ reg = <0x200000 0xb0>;
+
+ /* Unusual arrangement of interrupts
+ * (determined by testing)
+ * 17: Bank 0 (GPIOs 0-31)
+ * 19: Bank 1 (GPIOs 32-53)
+ * 18: Bank 2
+ * 20: All banks (GPIOs 0-53)
+ */
+ interrupts = <57 59 58 60>;
+ interrupt-parent = <&intc>;
+
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <1>;
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&pins_reserved>;
+
+ /* Pins that can short 3.3V to GND in output mode: 46-47
+ * Pins used by VideoCore: 48-53
+ */
+ broadcom,read-only = <46>, <47>, <48>, <49>, <50>,
+ <51>, <52>, <53>;
+
+ /* BSC0 */
+ pins_bsc0_a: bsc0_a {
+ broadcom,pins = <0>, <1>;
+ };
+
+ pins_bsc0_b: bsc0_b {
+ broadcom,pins = <28>, <29>;
+ };
+
+ pins_bsc0_c: bsc0_c {
+ broadcom,pins = <44>, <45>;
+ };
+
+ /* BSC1 */
+ pins_bsc1_a: bsc1_a {
+ broadcom,pins = <2>, <3>;
+ };
+
+ pins_bsc1_b: bsc1_b {
+ broadcom,pins = <44>, <45>;
+ };
+
+ /* GPCLK0 */
+ pins_gpclk0_a: gpclk0_a {
+ broadcom,pins = <4>;
+ };
+
+ pins_gpclk0_b: gpclk0_b {
+ broadcom,pins = <20>;
+ };
+
+ pins_gpclk0_c: gpclk0_c {
+ broadcom,pins = <32>;
+ };
+
+ pins_gpclk0_d: gpclk0_d {
+ broadcom,pins = <34>;
+ };
+
+ /* GPCLK1 */
+ pins_gpclk1_a: gpclk1_a {
+ broadcom,pins = <5>;
+ };
+
+ pins_gpclk1_b: gpclk1_b {
+ broadcom,pins = <21>;
+ };
+
+ pins_gpclk1_c: gpclk1_c {
+ broadcom,pins = <42>;
+ };
+
+ pins_gpclk1_d: gpclk1_d {
+ broadcom,pins = <44>;
+ };
+
+ /* GPCLK2 */
+ pins_gpclk2_a: gpclk2_a {
+ broadcom,pins = <6>;
+ };
+
+ pins_gpclk2_b: gpclk2_b {
+ broadcom,pins = <43>;
+ };
+
+ /* SPI0 */
+ pins_spi0_a: spi0_a {
+ broadcom,pins = <7>, <8>, <9>, <10>, <11>;
+ };
+
+ pins_spi0_b: spi0_b {
+ broadcom,pins = <35>, <36>, <37>, <38>, <39>;
+ };
+
+ /* PWM */
+ pins_pwm0_a: pwm0_a {
+ broadcom,pins = <12>;
+ };
+
+ pins_pwm0_b: pwm0_b {
+ broadcom,pins = <18>;
+ };
+
+ pins_pwm0_c: pwm0_c {
+ broadcom,pins = <40>;
+ };
+
+ pins_pwm1_a: pwm1_a {
+ broadcom,pins = <13>;
+ };
+
+ pins_pwm1_b: pwm1_b {
+ broadcom,pins = <19>;
+ };
+
+ pins_pwm1_c: pwm1_c {
+ broadcom,pins = <41>;
+ };
+
+ pins_pwm1_d: pwm1_d {
+ broadcom,pins = <45>;
+ };
+
+ /* UART0 */
+ pins_uart0_a: uart0_a {
+ broadcom,pins = <14>, <15>;
+ };
+
+ pins_uart0_b: uart0_b {
+ broadcom,pins = <32>, <33>;
+ };
+
+ pins_uart0_c: uart0_c {
+ broadcom,pins = <36>, <37>;
+ };
+
+ pins_uart0_fc_a: uart0_fc_a {
+ broadcom,pins = <16>, <17>;
+ };
+
+ pins_uart0_fc_b: uart0_fc_b {
+ broadcom,pins = <30>, <31>;
+ };
+
+ pins_uart0_fc_c: uart0_fc_c {
+ broadcom,pins = <39>, <38>;
+ };
+
+ /* PCM */
+ pins_pcm_a: pcm_a {
+ broadcom,pins = <18>, <19>, <20>, <21>;
+ };
+
+ pins_pcm_b: pcm_b {
+ broadcom,pins = <28>, <29>, <30>, <31>;
+ };
+
+ /* Secondary Address Bus */
+ pins_sm_addr_a: sm_addr_a {
+ broadcom,pins = <5>, <4>, <3>, <2>, <1>, <0>;
+ };
+
+ pins_sm_addr_b: sm_addr_b {
+ broadcom,pins = <33>, <32>, <31>, <30>, <29>,
+ <28>;
+ };
+
+ pins_sm_ctl_a: sm_ctl_a {
+ broadcom,pins = <6>, <7>;
+ };
+
+ pins_sm_ctl_b: sm_ctl_b {
+ broadcom,pins = <34>, <35>;
+ };
+
+ pins_sm_data_8bit_a: sm_data_8bit_a {
+ broadcom,pins = <8>, <9>, <10>, <11>, <12>,
+ <13>, <14>, <15>;
+ };
+
+ pins_sm_data_8bit_b: sm_data_8bit_b {
+ broadcom,pins = <36>, <37>, <38>, <39>, <40>,
+ <41>, <42>, <43>;
+ };
+
+ pins_sm_data_16bit: sm_data_16bit {
+ broadcom,pins = <16>, <17>, <18>, <19>, <20>,
+ <21>, <22>, <23>;
+ };
+
+ pins_sm_data_18bit: sm_data_18bit {
+ broadcom,pins = <24>, <25>;
+ };
+
+ /* BSCSL */
+ pins_bscsl: bscsl {
+ broadcom,pins = <18>, <19>;
+ };
+
+ /* SPISL */
+ pins_spisl: spisl {
+ broadcom,pins = <18>, <19>, <20>, <21>;
+ };
+
+ /* SPI1 */
+ pins_spi1: spi1 {
+ broadcom,pins = <16>, <17>, <18>, <19>, <20>,
+ <21>;
+ };
+
+ /* UART1 */
+ pins_uart1_a: uart1_a {
+ broadcom,pins = <14>, <15>;
+ };
+
+ pins_uart1_b: uart1_b {
+ broadcom,pins = <32>, <33>;
+ };
+
+ pins_uart1_c: uart1_c {
+ broadcom,pins = <40>, <41>;
+ };
+
+ pins_uart1_fc_a: uart1_fc_a {
+ broadcom,pins = <16>, <17>;
+ };
+
+ pins_uart1_fc_b: uart1_fc_b {
+ broadcom,pins = <30>, <31>;
+ };
+
+ pins_uart1_fc_c: uart1_fc_c {
+ broadcom,pins = <43>, <42>;
+ };
+
+ /* SPI2 */
+ pins_spi2: spi2 {
+ broadcom,pins = <40>, <41>, <42>, <43>, <44>,
+ <45>;
+ };
+
+ /* ARM JTAG */
+ pins_arm_jtag_trst: arm_jtag_trst {
+ broadcom,pins = <22>;
+ };
+
+ pins_arm_jtag_a: arm_jtag_a {
+ broadcom,pins = <4>, <5>, <6>, <12>, <13>;
+ };
+
+ pins_arm_jtag_b: arm_jtag_b {
+ broadcom,pins = <23>, <24>, <25>, <26>, <27>;
+ };
+
+ /* Reserved */
+ pins_reserved: reserved {
+ broadcom,pins = <48>, <49>, <50>, <51>, <52>,
+ <53>;
+ };
+ };
+
+ bsc0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "broadcom,bcm2835-bsc",
+ "broadcom,bcm2708-bsc";
+ reg = <0x205000 0x20>;
+ interrupts = <61>;
+ interrupt-parent = <&intc>;
+ };
+
+ bsc1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "broadcom,bcm2835-bsc",
+ "broadcom,bcm2708-bsc";
+ reg = <0x804000 0x20>;
+ interrupts = <61>;
+ interrupt-parent = <&intc>;
+ };
+
+ spi0 {
+ compatible = "broadcom,bcm2835-spi",
+ "broadcom,bcm2708-spi";
+ reg = <0x204000 0x20>;
+ interrupts = <62>;
+ interrupt-parent = <&intc>;
+ };
+
+ dma: dma {
+ compatible = "broadcom,bcm2835-dma",
+ "broadcom,bcm2708-dma";
+ reg = <0x7000 0x1000>, <0xE05000 0x1000>;
+ interrupts = <24 25 26 27 28 29 30 31 32 33 34 35 36>;
+ interrupt-parent = <&intc>;
+
+ broadcom,channels = <0>; /* Set by VideoCore */
+ };
+
+ vc_mbox: mbox {
+ compatible = "broadcom,bcm2835-mbox",
+ "broadcom,bcm2708-mbox";
+ reg = <0xB880 0x40>;
+ interrupts = <1>;
+ interrupt-parent = <&intc>;
+
+ /* Channels
+ * 0: Power
+ * 1: Frame buffer
+ * 2: Virtual UART
+ * 3: VCHIQ
+ * 4: LEDs
+ * 5: Buttons
+ * 6: Touch screen
+ */
+ };
+
+ sdhci {
+ compatible = "broadcom,bcm2835-sdhci",
+ "broadcom,bcm2708-sdhci";
+ reg = <0x300000 0x100>;
+ interrupts = <70>;
+ interrupt-parent = <&intc>;
+
+ clock-frequency = <50000000>; /* Set by VideoCore */
+ };
+
+ uart0: uart0 {
+ compatible = "broadcom,bcm2835-uart",
+ "broadcom,bcm2708-uart", "arm,pl011",
+ "arm,primecell";
+ reg = <0x201000 0x1000>;
+ interrupts = <65>;
+ interrupt-parent = <&intc>;
+
+ clock-frequency = <3000000>; /* Set by VideoCore */
+ reg-shift = <2>;
+ };
+
+ vchiq {
+ compatible = "broadcom,bcm2835-vchiq";
+ reg = <0xB800 0x50>;
+ interrupts = <2>;
+ interrupt-parent = <&intc>;
+ };
+
+ usb {
+ compatible = "broadcom,bcm2835-usb",
+ "broadcom,bcm2708-usb",
+ "synopsys,designware-hs-otg2";
+ reg = <0x980000 0x20000>;
+ interrupts = <17>;
+ interrupt-parent = <&intc>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ };
+};
Property changes on: trunk/sys/boot/fdt/dts/arm/bcm2835.dtsi
___________________________________________________________________
Added: svn:eol-style
## -0,0 +1 ##
+native
\ No newline at end of property
Added: svn:keywords
## -0,0 +1 ##
+MidnightBSD=%H
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+text/plain
\ No newline at end of property
Added: trunk/sys/boot/fdt/dts/arm/beaglebone-black.dts
===================================================================
--- trunk/sys/boot/fdt/dts/arm/beaglebone-black.dts (rev 0)
+++ trunk/sys/boot/fdt/dts/arm/beaglebone-black.dts 2018-06-02 12:34:49 UTC (rev 10205)
@@ -0,0 +1,185 @@
+/* $MidnightBSD$ */
+/*-
+ * Copyright (c) 2012 Damjan Marion <dmarion at Freebsd.org>
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ * $FreeBSD: stable/10/sys/boot/fdt/dts/arm/beaglebone-black.dts 294672 2016-01-24 18:50:37Z ian $
+ */
+
+/dts-v1/;
+
+/include/ "am335x.dtsi"
+
+/ {
+ model = "beaglebone-black";
+ compatible = "beaglebone-black", "beaglebone", "ti,am335x";
+
+
+ aliases {
+ soc = &SOC;
+ uart0 = &uart0;
+ };
+
+ memory {
+ device_type = "memory";
+ reg = < 0x80000000 0x20000000 >; /* 512MB RAM */
+ };
+
+ am335x {
+ scm at 44e10000 {
+ /* Set of triplets < padname, muxname, padstate> */
+ scm-pad-config =
+ /* I2C0 */
+ "I2C0_SDA", "I2C0_SDA","i2c",
+ "I2C0_SCL", "I2C0_SCL","i2c",
+ /* I2C1 */
+ "SPI0_D1", "I2C1_SDA", "i2c",
+ "SPI0_CS0", "I2C1_SCL", "i2c",
+ /* I2C2 */
+ "UART1_CTSn", "I2C2_SDA", "i2c",
+ "UART1_RTSn", "I2C2_SCL", "i2c",
+ /* Ethernet */
+ "MII1_RX_ER", "gmii1_rxerr", "input_pulldown",
+ "MII1_TX_EN", "gmii1_txen", "output",
+ "MII1_RX_DV", "gmii1_rxdv", "input_pulldown",
+ "MII1_TXD3", "gmii1_txd3", "output",
+ "MII1_TXD2", "gmii1_txd2", "output",
+ "MII1_TXD1", "gmii1_txd1", "output",
+ "MII1_TXD0", "gmii1_txd0", "output",
+ "MII1_TX_CLK", "gmii1_txclk", "input_pulldown",
+ "MII1_RX_CLK", "gmii1_rxclk", "input_pulldown",
+ "MII1_RXD3", "gmii1_rxd3", "input_pulldown",
+ "MII1_RXD2", "gmii1_rxd2", "input_pulldown",
+ "MII1_RXD1", "gmii1_rxd1", "input_pulldown",
+ "MII1_RXD0", "gmii1_rxd0", "input_pulldown",
+ "MDIO", "mdio_data", "input_pullup",
+ "MDC", "mdio_clk", "output_pullup",
+ /* MMCSD0 */
+ "MMC0_CMD", "mmc0_cmd", "input_pullup",
+ "MMC0_CLK", "mmc0_clk", "input_pullup",
+ "MMC0_DAT0", "mmc0_dat0", "input_pullup",
+ "MMC0_DAT1", "mmc0_dat1", "input_pullup",
+ "MMC0_DAT2", "mmc0_dat2", "input_pullup",
+ "MMC0_DAT3", "mmc0_dat3", "input_pullup",
+ /* MMC1 */
+ "GPMC_CSn1", "mmc1_clk", "input_pullup",
+ "GPMC_CSn2", "mmc1_cmd", "input_pullup",
+ "GPMC_CSn3", "gpio2_0", "output_pullup", /* Reset */
+ "GPMC_AD0", "mmc1_dat0", "input_pullup",
+ "GPMC_AD1", "mmc1_dat1", "input_pullup",
+ "GPMC_AD2", "mmc1_dat2", "input_pullup",
+ "GPMC_AD3", "mmc1_dat3", "input_pullup",
+ "GPMC_AD4", "mmc1_dat4", "input_pullup",
+ "GPMC_AD5", "mmc1_dat5", "input_pullup",
+ "GPMC_AD6", "mmc1_dat6", "input_pullup",
+ "GPMC_AD7", "mmc1_dat7", "input_pullup",
+ /* GPIO */
+ "ECAP0_IN_PWM0_OUT", "gpio0_7", "input_pulldown",
+ "GPMC_AD10", "gpio0_26", "input_pulldown",
+ "GPMC_AD11", "gpio0_27", "input_pulldown",
+ "GPMC_AD12", "gpio1_12", "input_pulldown",
+ "GPMC_AD13", "gpio1_13", "input_pulldown",
+ "GPMC_AD14", "gpio1_14", "input_pulldown",
+ "GPMC_AD15", "gpio1_15", "input_pulldown",
+ "GPMC_A0", "gpio1_16", "input_pulldown",
+ "GPMC_A1", "gpio1_17", "input_pulldown",
+ "GPMC_A5", "gpio1_21", "output", /* User LED 1 */
+ "GPMC_A6", "gpio1_22", "output", /* User LED 2 */
+ "GPMC_A7", "gpio1_23", "output", /* User LED 3 */
+ "GPMC_A8", "gpio1_24", "output", /* User LED 4 */
+ "GPMC_BEn1", "gpio1_28", "input_pulldown",
+ "GPMC_CSn0", "gpio1_29", "input_pulldown",
+ "GPMC_CLK", "gpio2_1", "input_pulldown",
+ "LCD_DATA0", "gpio2_6", "input_pulldown",
+ "LCD_DATA1", "gpio2_7", "input_pulldown",
+ "LCD_DATA2", "gpio2_8", "input_pulldown",
+ "LCD_DATA3", "gpio2_9", "input_pulldown",
+ "LCD_DATA4", "gpio2_10", "input_pulldown",
+ "LCD_DATA5", "gpio2_11", "input_pulldown",
+ "LCD_DATA6", "gpio2_12", "input_pulldown",
+ "LCD_DATA7", "gpio2_13", "input_pulldown",
+ "LCD_VSYNC", "gpio2_22", "input_pulldown",
+ "LCD_HSYNC", "gpio2_23", "input_pulldown",
+ "LCD_PCLK", "gpio2_24", "input_pulldown",
+ "LCD_AC_BIAS_EN", "gpio2_25", "input_pulldown",
+ "MCASP0_FSR", "gpio3_19", "input_pulldown",
+ "MCASP0_AHCLKX", "gpio3_21", "input_pulldown",
+ /* TIMERs */
+ "GPMC_ADVn_ALE", "timer4", "output",
+ "GPMC_BEn0_CLE", "timer5", "output",
+ "GPMC_WEn", "timer6", "output",
+ "GPMC_OEn_REn", "timer7", "output",
+ /* USB0 and USB1 */
+ "USB0_DRVVBUS", "USB0_DRVVBUS", "output",
+ "USB1_DRVVBUS", "USB1_DRVVBUS", "output",
+ /* PWM */
+ "GPMC_A2", "ehrpwm1A", "output",
+ "GPMC_A3", "ehrpwm1B", "output",
+ "GPMC_AD8", "ehrpwm2A", "output",
+ "GPMC_AD9", "ehrpwm2B", "output";
+ };
+
+ mmchs1 at 481D8000 {
+ bus-width = <8>;
+ status = "okay";
+ non-removable;
+ };
+
+ i2c at 44e0b000 {
+ pmic at 24 {
+ compatible = "ti,am335x-pmic";
+ reg = <0x24>;
+ };
+ };
+ };
+
+ leds {
+ compatible = "gpio-leds";
+
+ led1 {
+ gpios = <&GPIO 53 2 0>;
+ name = "led1";
+ };
+
+ led2 {
+ gpios = <&GPIO 54 2 0>;
+ name = "led2";
+ };
+
+ led3 {
+ gpios = <&GPIO 55 2 0>;
+ name = "led3";
+ };
+
+ led4 {
+ gpios = <&GPIO 56 2 0>;
+ name = "led4";
+ };
+ };
+
+ chosen {
+ stdin = "uart0";
+ stdout = "uart0";
+ };
+};
Property changes on: trunk/sys/boot/fdt/dts/arm/beaglebone-black.dts
___________________________________________________________________
Added: svn:eol-style
## -0,0 +1 ##
+native
\ No newline at end of property
Added: svn:keywords
## -0,0 +1 ##
+MidnightBSD=%H
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+text/plain
\ No newline at end of property
Added: trunk/sys/boot/fdt/dts/arm/beaglebone.dts
===================================================================
--- trunk/sys/boot/fdt/dts/arm/beaglebone.dts (rev 0)
+++ trunk/sys/boot/fdt/dts/arm/beaglebone.dts 2018-06-02 12:34:49 UTC (rev 10205)
@@ -0,0 +1,146 @@
+/* $MidnightBSD$ */
+/*-
+ * Copyright (c) 2012 Damjan Marion <dmarion at Freebsd.org>
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ * $FreeBSD: stable/10/sys/boot/fdt/dts/arm/beaglebone.dts 294672 2016-01-24 18:50:37Z ian $
+ */
+
+/dts-v1/;
+
+/include/ "am335x.dtsi"
+
+/ {
+ model = "beaglebone";
+ compatible = "beaglebone", "ti,am335x";
+
+ aliases {
+ soc = &SOC;
+ uart0 = &uart0;
+ };
+
+ memory {
+ device_type = "memory";
+ reg = < 0x80000000 0x10000000 >; /* 256MB RAM */
+ };
+
+ am335x {
+ scm at 44e10000 {
+ /* Set of triplets < padname, muxname, padstate> */
+ scm-pad-config =
+ /* I2C0 */
+ "I2C0_SDA", "I2C0_SDA","i2c",
+ "I2C0_SCL", "I2C0_SCL","i2c",
+ /* Ethernet */
+ "MII1_RX_ER", "gmii1_rxerr", "input_pulldown",
+ "MII1_TX_EN", "gmii1_txen", "output",
+ "MII1_RX_DV", "gmii1_rxdv", "input_pulldown",
+ "MII1_TXD3", "gmii1_txd3", "output",
+ "MII1_TXD2", "gmii1_txd2", "output",
+ "MII1_TXD1", "gmii1_txd1", "output",
+ "MII1_TXD0", "gmii1_txd0", "output",
+ "MII1_TX_CLK", "gmii1_txclk", "input_pulldown",
+ "MII1_RX_CLK", "gmii1_rxclk", "input_pulldown",
+ "MII1_RXD3", "gmii1_rxd3", "input_pulldown",
+ "MII1_RXD2", "gmii1_rxd2", "input_pulldown",
+ "MII1_RXD1", "gmii1_rxd1", "input_pulldown",
+ "MII1_RXD0", "gmii1_rxd0", "input_pulldown",
+ "MDIO", "mdio_data", "input_pullup",
+ "MDC", "mdio_clk", "output_pullup",
+ /* MMCSD0 */
+ "MMC0_CMD", "mmc0_cmd", "input_pullup",
+ "MMC0_CLK", "mmc0_clk", "input_pullup",
+ "MMC0_DAT0", "mmc0_dat0", "input_pullup",
+ "MMC0_DAT1", "mmc0_dat1", "input_pullup",
+ "MMC0_DAT2", "mmc0_dat2", "input_pullup",
+ "MMC0_DAT3", "mmc0_dat3", "input_pullup",
+ /* USB0 and USB1 */
+ "USB0_DRVVBUS", "USB0_DRVVBUS", "output",
+ "USB1_DRVVBUS", "USB1_DRVVBUS", "output",
+ /* GPIO */
+ "ECAP0_IN_PWM0_OUT", "gpio0_7", "input_pulldown",
+ "GPMC_AD10", "gpio0_26", "input_pulldown",
+ "GPMC_AD11", "gpio0_27", "input_pulldown",
+ "GPMC_AD0", "gpio1_0", "input_pulldown",
+ "GPMC_AD1", "gpio1_1", "input_pulldown",
+ "GPMC_AD2", "gpio1_2", "input_pulldown",
+ "GPMC_AD3", "gpio1_3", "input_pulldown",
+ "GPMC_AD4", "gpio1_4", "input_pulldown",
+ "GPMC_AD5", "gpio1_5", "input_pulldown",
+ "GPMC_AD6", "gpio1_6", "input_pulldown",
+ "GPMC_AD7", "gpio1_7", "input_pulldown",
+ "GPMC_AD12", "gpio1_12", "input_pulldown",
+ "GPMC_AD13", "gpio1_13", "input_pulldown",
+ "GPMC_AD14", "gpio1_14", "input_pulldown",
+ "GPMC_AD15", "gpio1_15", "input_pulldown",
+ "GPMC_A0", "gpio1_16", "input_pulldown",
+ "GPMC_A1", "gpio1_17", "input_pulldown",
+ "GPMC_A5", "gpio1_21", "output", /* User LED 1 */
+ "GPMC_A6", "gpio1_22", "output", /* User LED 2 */
+ "GPMC_A7", "gpio1_23", "output", /* User LED 3 */
+ "GPMC_A8", "gpio1_24", "output", /* User LED 4 */
+ "GPMC_BEn1", "gpio1_28", "input_pulldown",
+ "GPMC_CSn0", "gpio1_29", "input_pulldown",
+ "GPMC_CSn1", "gpio1_30", "input_pulldown",
+ "GPMC_CSn2", "gpio1_31", "input_pulldown",
+ "GPMC_CLK", "gpio2_1", "input_pulldown",
+ "LCD_DATA0", "gpio2_6", "input_pulldown",
+ "LCD_DATA1", "gpio2_7", "input_pulldown",
+ "LCD_DATA2", "gpio2_8", "input_pulldown",
+ "LCD_DATA3", "gpio2_9", "input_pulldown",
+ "LCD_DATA4", "gpio2_10", "input_pulldown",
+ "LCD_DATA5", "gpio2_11", "input_pulldown",
+ "LCD_DATA6", "gpio2_12", "input_pulldown",
+ "LCD_DATA7", "gpio2_13", "input_pulldown",
+ "LCD_VSYNC", "gpio2_22", "input_pulldown",
+ "LCD_HSYNC", "gpio2_23", "input_pulldown",
+ "LCD_PCLK", "gpio2_24", "input_pulldown",
+ "LCD_AC_BIAS_EN", "gpio2_25", "input_pulldown",
+ "MCASP0_FSR", "gpio3_19", "input_pulldown",
+ "MCASP0_AHCLKX", "gpio3_21", "input_pulldown",
+ /* TIMERs */
+ "GPMC_ADVn_ALE", "timer4", "output",
+ "GPMC_BEn0_CLE", "timer5", "output",
+ "GPMC_WEn", "timer6", "output",
+ "GPMC_OEn_REn", "timer7", "output",
+ /* PWM */
+ "GPMC_A2", "ehrpwm1A", "output",
+ "GPMC_A3", "ehrpwm1B", "output",
+ "GPMC_AD8", "ehrpwm2A", "output",
+ "GPMC_AD9", "ehrpwm2B", "output";
+ };
+
+ i2c at 44e0b000 {
+ pmic at 24 {
+ compatible = "ti,am335x-pmic";
+ reg = <0x24>;
+ };
+ };
+ };
+
+ chosen {
+ stdin = "uart0";
+ stdout = "uart0";
+ };
+};
Property changes on: trunk/sys/boot/fdt/dts/arm/beaglebone.dts
___________________________________________________________________
Added: svn:eol-style
## -0,0 +1 ##
+native
\ No newline at end of property
Added: svn:keywords
## -0,0 +1 ##
+MidnightBSD=%H
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+text/plain
\ No newline at end of property
Added: trunk/sys/boot/fdt/dts/arm/cubieboard.dts
===================================================================
--- trunk/sys/boot/fdt/dts/arm/cubieboard.dts (rev 0)
+++ trunk/sys/boot/fdt/dts/arm/cubieboard.dts 2018-06-02 12:34:49 UTC (rev 10205)
@@ -0,0 +1,72 @@
+/* $MidnightBSD$ */
+/*-
+ * Copyright (c) 2012 Ganbold Tsagaankhuu <ganbold at freebsd.org>
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ * $FreeBSD: stable/10/sys/boot/fdt/dts/arm/cubieboard.dts 266376 2014-05-17 23:16:18Z ian $
+ */
+
+/dts-v1/;
+
+/include/ "sun4i-a10.dtsi"
+
+/ {
+ model = "Cubietech Cubieboard";
+
+ memory {
+ device_type = "memory";
+ reg = < 0x40000000 0x40000000 >; /* 1GB RAM */
+ };
+
+ aliases {
+ soc = &SOC;
+ UART0 = &UART0;
+ };
+
+ SOC: a10 {
+
+ usb1: usb at 01c14000 {
+ status = "okay";
+ };
+
+ usb2: usb at 01c1c000 {
+ status = "okay";
+ };
+
+ UART0: serial at 01c28000 {
+ status = "okay";
+ };
+
+ emac at 01c0b000 {
+ status = "okay";
+ };
+ };
+
+ chosen {
+ bootargs = "-v";
+ stdin = "UART0";
+ stdout = "UART0";
+ };
+};
+
Property changes on: trunk/sys/boot/fdt/dts/arm/cubieboard.dts
___________________________________________________________________
Added: svn:eol-style
## -0,0 +1 ##
+native
\ No newline at end of property
Added: svn:keywords
## -0,0 +1 ##
+MidnightBSD=%H
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+text/plain
\ No newline at end of property
Added: trunk/sys/boot/fdt/dts/arm/cubieboard2.dts
===================================================================
--- trunk/sys/boot/fdt/dts/arm/cubieboard2.dts (rev 0)
+++ trunk/sys/boot/fdt/dts/arm/cubieboard2.dts 2018-06-02 12:34:49 UTC (rev 10205)
@@ -0,0 +1,72 @@
+/* $MidnightBSD$ */
+/*-
+ * Copyright (c) 2013 Ganbold Tsagaankhuu <ganbold at freebsd.org>
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ * $FreeBSD: stable/10/sys/boot/fdt/dts/arm/cubieboard2.dts 266376 2014-05-17 23:16:18Z ian $
+ */
+
+/dts-v1/;
+
+/include/ "sun7i-a20.dtsi"
+
+/ {
+ model = "Cubietech Cubieboard2";
+
+ memory {
+ device_type = "memory";
+ reg = < 0x40000000 0x40000000 >; /* 1GB RAM */
+ };
+
+ aliases {
+ soc = &SOC;
+ UART0 = &UART0;
+ };
+
+ SOC: a20 {
+
+ usb1: usb at 01c14000 {
+ status = "okay";
+ };
+
+ usb2: usb at 01c1c000 {
+ status = "okay";
+ };
+
+ UART0: serial at 01c28000 {
+ status = "okay";
+ };
+
+ emac at 01c0b000 {
+ status = "okay";
+ };
+ };
+
+ chosen {
+ bootargs = "-v";
+ stdin = "UART0";
+ stdout = "UART0";
+ };
+};
+
Property changes on: trunk/sys/boot/fdt/dts/arm/cubieboard2.dts
___________________________________________________________________
Added: svn:eol-style
## -0,0 +1 ##
+native
\ No newline at end of property
Added: svn:keywords
## -0,0 +1 ##
+MidnightBSD=%H
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+text/plain
\ No newline at end of property
Added: trunk/sys/boot/fdt/dts/arm/db78100.dts
===================================================================
--- trunk/sys/boot/fdt/dts/arm/db78100.dts (rev 0)
+++ trunk/sys/boot/fdt/dts/arm/db78100.dts 2018-06-02 12:34:49 UTC (rev 10205)
@@ -0,0 +1,332 @@
+/* $MidnightBSD$ */
+/*
+ * Copyright (c) 2010 The FreeBSD Foundation
+ * All rights reserved.
+ *
+ * This software was developed by Semihalf under sponsorship from
+ * the FreeBSD Foundation.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ * Marvell DB-78100 Device Tree Source.
+ *
+ * $FreeBSD: stable/10/sys/boot/fdt/dts/arm/db78100.dts 262614 2014-02-28 18:29:09Z imp $
+ */
+
+/dts-v1/;
+
+/ {
+ model = "mrvl,DB-78100";
+ compatible = "DB-78100-BP", "DB-78100-BP-A";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ aliases {
+ ethernet0 = &enet0;
+ serial0 = &serial0;
+ serial1 = &serial1;
+ mpp = &MPP;
+ };
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cpu at 0 {
+ device_type = "cpu";
+ compatible = "ARM,88FR571";
+ reg = <0x0>;
+ d-cache-line-size = <32>; // 32 bytes
+ i-cache-line-size = <32>; // 32 bytes
+ d-cache-size = <0x4000>; // L1, 16K
+ i-cache-size = <0x4000>; // L1, 16K
+ timebase-frequency = <0>;
+ bus-frequency = <0>;
+ clock-frequency = <0>;
+ };
+ };
+
+ memory {
+ device_type = "memory";
+ reg = <0x0 0x20000000>; // 512M at 0x0
+ };
+
+ localbus at 0 {
+ #address-cells = <2>;
+ #size-cells = <1>;
+ compatible = "mrvl,lbc";
+ bank-count = <5>;
+
+ /* This reflects CPU decode windows setup. */
+ ranges = <0x0 0x2f 0xf9300000 0x00100000
+ 0x1 0x3e 0xf9400000 0x00100000
+ 0x2 0x3d 0xf9500000 0x02000000
+ 0x3 0x3b 0xfb500000 0x00100000>;
+
+ nor at 0,0 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "cfi-flash";
+ reg = <0x0 0x0 0x00100000>;
+ };
+
+ led at 1,0 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "led";
+ reg = <0x1 0x0 0x00100000>;
+ };
+
+ nor at 2,0 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "cfi-flash";
+ reg = <0x2 0x0 0x02000000>;
+ };
+
+ nand at 3,0 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "mrvl,nfc";
+ reg = <0x3 0x0 0x00100000>;
+ };
+ };
+
+ soc78100 at f1000000 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "simple-bus";
+ ranges = <0x0 0xf1000000 0x00100000>;
+ bus-frequency = <0>;
+
+ PIC: pic at 20200 {
+ interrupt-controller;
+ #address-cells = <0>;
+ #interrupt-cells = <1>;
+ reg = <0x20200 0x3c>;
+ compatible = "mrvl,pic";
+ };
+
+ timer at 20300 {
+ compatible = "mrvl,timer";
+ reg = <0x20300 0x30>;
+ interrupts = <8>;
+ interrupt-parent = <&PIC>;
+ mrvl,has-wdt;
+ };
+
+ MPP: mpp at 10000 {
+ #pin-cells = <2>;
+ compatible = "mrvl,mpp";
+ reg = <0x10000 0x34>;
+ pin-count = <50>;
+ pin-map = <
+ 0 2 /* MPP[0]: GE1_TXCLK */
+ 1 2 /* MPP[1]: GE1_TXCTL */
+ 2 2 /* MPP[2]: GE1_RXCTL */
+ 3 2 /* MPP[3]: GE1_RXCLK */
+ 4 2 /* MPP[4]: GE1_TXD[0] */
+ 5 2 /* MPP[5]: GE1_TXD[1] */
+ 6 2 /* MPP[6]: GE1_TXD[2] */
+ 7 2 /* MPP[7]: GE1_TXD[3] */
+ 8 2 /* MPP[8]: GE1_RXD[0] */
+ 9 2 /* MPP[9]: GE1_RXD[1] */
+ 10 2 /* MPP[10]: GE1_RXD[2] */
+ 11 2 /* MPP[11]: GE1_RXD[3] */
+ 13 3 /* MPP[13]: SYSRST_OUTn */
+ 14 3 /* MPP[14]: SATA1_ACTn */
+ 15 3 /* MPP[15]: SATA0_ACTn */
+ 16 4 /* MPP[16]: UA2_TXD */
+ 17 4 /* MPP[17]: UA2_RXD */
+ 18 3 /* MPP[18]: <UNKNOWN> */
+ 19 3 /* MPP[19]: <UNKNOWN> */
+ 20 3 /* MPP[20]: <UNKNOWN> */
+ 21 3 /* MPP[21]: <UNKNOWN> */
+ 22 4 /* MPP[22]: UA3_TXD */
+ 23 4 >; /* MPP[21]: UA3_RXD */
+ };
+
+ GPIO: gpio at 10100 {
+ #gpio-cells = <3>;
+ compatible = "mrvl,gpio";
+ reg = <0x10100 0x20>;
+ gpio-controller;
+ interrupts = <56 57 58 59>;
+ interrupt-parent = <&PIC>;
+ };
+
+ rtc at 10300 {
+ compatible = "mrvl,rtc";
+ reg = <0x10300 0x08>;
+ };
+
+ twsi at 11000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "mrvl,twsi";
+ reg = <0x11000 0x20>;
+ interrupts = <2>;
+ interrupt-parent = <&PIC>;
+ };
+
+ twsi at 11100 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "mrvl,twsi";
+ reg = <0x11100 0x20>;
+ interrupts = <3>;
+ interrupt-parent = <&PIC>;
+ };
+
+ enet0: ethernet at 72000 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ model = "V2";
+ compatible = "mrvl,ge";
+ reg = <0x72000 0x2000>;
+ ranges = <0x0 0x72000 0x2000>;
+ local-mac-address = [ 00 00 00 00 00 00 ];
+ interrupts = <41 42 43 40 70>;
+ interrupt-parent = <&PIC>;
+ phy-handle = <&phy0>;
+
+ mdio at 0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "mrvl,mdio";
+
+ phy0: ethernet-phy at 0 {
+ reg = <0x8>;
+ };
+ phy1: ethernet-phy at 1 {
+ reg = <0x9>;
+ };
+ };
+ };
+
+ enet1: ethernet at 76000 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ model = "V2";
+ compatible = "mrvl,ge";
+ reg = <0x76000 0x2000>;
+ ranges = <0x0 0x76000 0x2000>;
+ local-mac-address = [ 00 00 00 00 00 00 ];
+ interrupts = <45 46 47 44 70>;
+ interrupt-parent = <&PIC>;
+ phy-handle = <&phy1>;
+ };
+
+ serial0: serial at 12000 {
+ compatible = "ns16550";
+ reg = <0x12000 0x20>;
+ reg-shift = <2>;
+ clock-frequency = <0>;
+ interrupts = <12>;
+ interrupt-parent = <&PIC>;
+ };
+
+ serial1: serial at 12100 {
+ compatible = "ns16550";
+ reg = <0x12100 0x20>;
+ reg-shift = <2>;
+ clock-frequency = <0>;
+ interrupts = <13>;
+ interrupt-parent = <&PIC>;
+ };
+
+ usb at 50000 {
+ compatible = "mrvl,usb-ehci", "usb-ehci";
+ reg = <0x50000 0x1000>;
+ interrupts = <72 16>;
+ interrupt-parent = <&PIC>;
+ };
+
+ usb at 51000 {
+ compatible = "mrvl,usb-ehci", "usb-ehci";
+ reg = <0x51000 0x1000>;
+ interrupts = <72 17>;
+ interrupt-parent = <&PIC>;
+ };
+
+ usb at 52000 {
+ compatible = "mrvl,usb-ehci", "usb-ehci";
+ reg = <0x52000 0x1000>;
+ interrupts = <72 18>;
+ interrupt-parent = <&PIC>;
+ };
+
+ xor at 60000 {
+ compatible = "mrvl,xor";
+ reg = <0x60000 0x1000>;
+ interrupts = <22 23>;
+ interrupt-parent = <&PIC>;
+ };
+
+ crypto at 90000 {
+ compatible = "mrvl,cesa";
+ reg = <0x90000 0x10000>;
+ interrupts = <19>;
+ interrupt-parent = <&PIC>;
+ };
+
+ sata at a0000 {
+ compatible = "mrvl,sata";
+ reg = <0xa0000 0x6000>;
+ interrupts = <26>;
+ interrupt-parent = <&PIC>;
+ };
+ };
+
+ pci0: pcie at f1040000 {
+ compatible = "mrvl,pcie";
+ device_type = "pci";
+ #interrupt-cells = <1>;
+ #size-cells = <2>;
+ #address-cells = <3>;
+ reg = <0xf1040000 0x2000>;
+ bus-range = <0 255>;
+ ranges = <0x02000000 0x0 0xf2000000 0xf2000000 0x0 0x04000000
+ 0x01000000 0x0 0x00000000 0xf1100000 0x0 0x00100000>;
+ clock-frequency = <33333333>;
+ interrupt-parent = <&PIC>;
+ interrupts = <68>;
+ interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
+ interrupt-map = <
+ /* IDSEL 0x1 */
+ 0x0800 0x0 0x0 0x1 &PIC 0x20
+ 0x0800 0x0 0x0 0x2 &PIC 0x21
+ 0x0800 0x0 0x0 0x3 &PIC 0x22
+ 0x0800 0x0 0x0 0x4 &PIC 0x23
+ >;
+ };
+
+ sram at fd000000 {
+ compatible = "mrvl,cesa-sram";
+ reg = <0xfd000000 0x00100000>;
+ };
+
+ chosen {
+ stdin = "serial0";
+ stdout = "serial0";
+ };
+};
Property changes on: trunk/sys/boot/fdt/dts/arm/db78100.dts
___________________________________________________________________
Added: svn:eol-style
## -0,0 +1 ##
+native
\ No newline at end of property
Added: svn:keywords
## -0,0 +1 ##
+MidnightBSD=%H
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+text/plain
\ No newline at end of property
Added: trunk/sys/boot/fdt/dts/arm/db78460.dts
===================================================================
--- trunk/sys/boot/fdt/dts/arm/db78460.dts (rev 0)
+++ trunk/sys/boot/fdt/dts/arm/db78460.dts 2018-06-02 12:34:49 UTC (rev 10205)
@@ -0,0 +1,328 @@
+/* $MidnightBSD$ */
+/*
+ * Copyright (c) 2010 The FreeBSD Foundation
+ * Copyright (c) 2010-2011 Semihalf
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ * Marvell DB-78460 Device Tree Source.
+ *
+ * $FreeBSD: stable/10/sys/boot/fdt/dts/arm/db78460.dts 262614 2014-02-28 18:29:09Z imp $
+ */
+
+/dts-v1/;
+
+/ {
+ model = "mrvl,DB-78460";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ aliases {
+ serial0 = &serial0;
+ };
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cpu at 0 {
+ device_type = "cpu";
+ compatible = "ARM,88VS584";
+ reg = <0x0>;
+ d-cache-line-size = <32>; // 32 bytes
+ i-cache-line-size = <32>; // 32 bytes
+ d-cache-size = <0x8000>; // L1, 32K
+ i-cache-size = <0x8000>; // L1, 32K
+ timebase-frequency = <0>;
+ bus-frequency = <200000000>;
+ clock-frequency = <0>;
+ };
+ };
+
+ memory {
+ device_type = "memory";
+ reg = <0x0 0x80000000>; // 2G at 0x0
+ };
+
+ soc78460 at d0000000 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "simple-bus";
+ ranges = <0x0 0xd0000000 0x00100000>;
+ bus-frequency = <0>;
+
+
+ MPIC: mpic at 20a00 {
+ interrupt-controller;
+ #address-cells = <0>;
+ #interrupt-cells = <1>;
+ reg = <0x20a00 0x500 0x21000 0x800 0x20400 0x100>;
+ compatible = "mrvl,mpic";
+ };
+
+ rtc at 10300 {
+ compatible = "mrvl,rtc";
+ reg = <0x10300 0x08>;
+ };
+
+ timer at 21840 {
+ compatible = "mrvl,timer";
+ reg = <0x21840 0x30>;
+ interrupts = <5>;
+ interrupt-parent = <&MPIC>;
+ mrvl,has-wdt;
+ };
+
+ twsi at 11000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "mrvl,twsi";
+ reg = <0x11000 0x20>;
+ interrupts = <31>;
+ interrupt-parent = <&MPIC>;
+ };
+
+ twsi at 11100 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "mrvl,twsi";
+ reg = <0x11100 0x20>;
+ interrupts = <32>;
+ interrupt-parent = <&MPIC>;
+ };
+
+ serial0: serial at 12000 {
+ compatible = "ns16550";
+ reg = <0x12000 0x20>;
+ reg-shift = <2>;
+ current-speed = <115200>;
+ clock-frequency = <0>;
+ busy-detect = <1>;
+ interrupts = <41>;
+ interrupt-parent = <&MPIC>;
+ };
+
+ serial1: serial at 12100 {
+ compatible = "ns16550";
+ reg = <0x12100 0x20>;
+ reg-shift = <2>;
+ current-speed = <115200>;
+ clock-frequency = <0>;
+ busy-detect = <1>;
+ interrupts = <42>;
+ interrupt-parent = <&MPIC>;
+ };
+
+ serial2: serial at 12200 {
+ compatible = "ns16550";
+ reg = <0x12200 0x20>;
+ reg-shift = <2>;
+ current-speed = <115200>;
+ clock-frequency = <0>;
+ busy-detect = <1>;
+ interrupts = <43>;
+ interrupt-parent = <&MPIC>;
+ };
+
+ serial3: serial at 12300 {
+ compatible = "ns16550";
+ reg = <0x12300 0x20>;
+ reg-shift = <2>;
+ current-speed = <115200>;
+ clock-frequency = <0>;
+ busy-detect = <1>;
+ interrupts = <44>;
+ interrupt-parent = <&MPIC>;
+ };
+
+ MPP: mpp at 10000 {
+ #pin-cells = <2>;
+ compatible = "mrvl,mpp";
+ reg = <0x18000 0x34>;
+ pin-count = <68>;
+ pin-map = <
+ 0 1 /* MPP[0]: GE1_TXCLK */
+ 1 1 /* MPP[1]: GE1_TXCTL */
+ 2 1 /* MPP[2]: GE1_RXCTL */
+ 3 1 /* MPP[3]: GE1_RXCLK */
+ 4 1 /* MPP[4]: GE1_TXD[0] */
+ 5 1 /* MPP[5]: GE1_TXD[1] */
+ 6 1 /* MPP[6]: GE1_TXD[2] */
+ 7 1 /* MPP[7]: GE1_TXD[3] */
+ 8 1 /* MPP[8]: GE1_RXD[0] */
+ 9 1 /* MPP[9]: GE1_RXD[1] */
+ 10 1 /* MPP[10]: GE1_RXD[2] */
+ 11 1 /* MPP[11]: GE1_RXD[3] */
+ 12 2 /* MPP[13]: SYSRST_OUTn */
+ 13 2 /* MPP[13]: SYSRST_OUTn */
+ 14 2 /* MPP[14]: SATA1_ACTn */
+ 15 2 /* MPP[15]: SATA0_ACTn */
+ 16 2 /* MPP[16]: UA2_TXD */
+ 17 2 /* MPP[17]: UA2_RXD */
+ 18 2 /* MPP[18]: <UNKNOWN> */
+ 19 2 /* MPP[19]: <UNKNOWN> */
+ 20 2 /* MPP[20]: <UNKNOWN> */
+ 21 2 /* MPP[21]: <UNKNOWN> */
+ 22 2 /* MPP[22]: UA3_TXD */
+ 23 2
+ 24 0
+ 25 0
+ 26 0
+ 27 0
+ 28 4
+ 29 0
+ 30 1
+ 31 1
+ 32 1
+ 33 1
+ 34 1
+ 35 1
+ 36 1
+ 37 1
+ 38 1
+ 39 1
+ 40 0
+ 41 3
+ 42 1
+ 43 1
+ 44 2
+ 45 2
+ 46 4
+ 47 3
+ 48 0
+ 49 1
+ 50 1
+ 51 1
+ 52 1
+ 53 1
+ 54 1
+ 55 1
+ 56 1
+ 57 0
+ 58 1
+ 59 1
+ 60 1
+ 61 1
+ 62 1
+ 63 1
+ 64 1
+ 65 1
+ 66 1
+ 67 2 >;
+ };
+
+ usb at 50000 {
+ compatible = "mrvl,usb-ehci", "usb-ehci";
+ reg = <0x50000 0x1000>;
+ interrupts = <124 45>;
+ interrupt-parent = <&MPIC>;
+ };
+
+ usb at 51000 {
+ compatible = "mrvl,usb-ehci", "usb-ehci";
+ reg = <0x51000 0x1000>;
+ interrupts = <124 46>;
+ interrupt-parent = <&MPIC>;
+ };
+
+ usb at 52000 {
+ compatible = "mrvl,usb-ehci", "usb-ehci";
+ reg = <0x52000 0x1000>;
+ interrupts = <124 47>;
+ interrupt-parent = <&MPIC>;
+ };
+
+ enet0: ethernet at 72000 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ model = "V2";
+ compatible = "mrvl,ge";
+ reg = <0x72000 0x2000>;
+ ranges = <0x0 0x72000 0x2000>;
+ local-mac-address = [ 00 04 01 07 84 60 ];
+ interrupts = <67 68 122 >;
+ interrupt-parent = <&MPIC>;
+ phy-handle = <&phy0>;
+ has-neta;
+
+ mdio at 0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "mrvl,mdio";
+
+ phy0: ethernet-phy at 0 {
+ reg = <0x0>;
+ };
+ phy1: ethernet-phy at 1 {
+ reg = <0x1>;
+ };
+ phy2: ethernet-phy at 2 {
+ reg = <0x19>;
+ };
+ phy3: ethernet-phy at 3 {
+ reg = <0x1b>;
+ };
+ };
+ };
+
+ sata at A0000 {
+ compatible = "mrvl,sata";
+ reg = <0xA0000 0x6000>;
+ interrupts = <55>;
+ interrupt-parent = <&MPIC>;
+ };
+ };
+
+ pci0: pcie at d0040000 {
+ compatible = "mrvl,pcie";
+ device_type = "pci";
+ #interrupt-cells = <1>;
+ #size-cells = <2>;
+ #address-cells = <3>;
+ reg = <0xd0040000 0x2000>;
+ bus-range = <0 255>;
+ ranges = <0x02000000 0x0 0x80000000 0x80000000 0x0 0x20000000
+ 0x01000000 0x0 0x00000000 0xa0000000 0x0 0x08000000>;
+ clock-frequency = <33333333>;
+ interrupt-parent = <&MPIC>;
+ interrupts = <120>;
+ interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
+ interrupt-map = <
+ 0x0800 0x0 0x0 0x1 &MPIC 0x3A
+ 0x0800 0x0 0x0 0x2 &MPIC 0x3A
+ 0x0800 0x0 0x0 0x3 &MPIC 0x3A
+ 0x0800 0x0 0x0 0x4 &MPIC 0x3A
+ >;
+ };
+
+ sram at ffff0000 {
+ compatible = "mrvl,cesa-sram";
+ reg = <0xffff0000 0x00010000>;
+ };
+
+ chosen {
+ stdin = "serial0";
+ stdout = "serial0";
+ stddbg = "serial0";
+ };
+};
Property changes on: trunk/sys/boot/fdt/dts/arm/db78460.dts
___________________________________________________________________
Added: svn:eol-style
## -0,0 +1 ##
+native
\ No newline at end of property
Added: svn:keywords
## -0,0 +1 ##
+MidnightBSD=%H
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+text/plain
\ No newline at end of property
Added: trunk/sys/boot/fdt/dts/arm/db88f5182.dts
===================================================================
--- trunk/sys/boot/fdt/dts/arm/db88f5182.dts (rev 0)
+++ trunk/sys/boot/fdt/dts/arm/db88f5182.dts 2018-06-02 12:34:49 UTC (rev 10205)
@@ -0,0 +1,224 @@
+/* $MidnightBSD$ */
+/*
+ * Copyright (c) 2010 The FreeBSD Foundation
+ * All rights reserved.
+ *
+ * This software was developed by Semihalf under sponsorship from
+ * the FreeBSD Foundation.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ * Marvell DB-88F5182 Device Tree Source.
+ *
+ * $FreeBSD: stable/10/sys/boot/fdt/dts/arm/db88f5182.dts 262614 2014-02-28 18:29:09Z imp $
+ */
+
+/dts-v1/;
+
+/ {
+ model = "mrvl,DB-88F5182";
+ compatible = "DB-88F5182-BP", "DB-88F5182-BP-A";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ aliases {
+ ethernet0 = &enet0;
+ serial0 = &serial0;
+ serial1 = &serial1;
+ mpp = &MPP;
+ };
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cpu at 0 {
+ device_type = "cpu";
+ compatible = "ARM,88FR531";
+ reg = <0x0>;
+ d-cache-line-size = <32>; // 32 bytes
+ i-cache-line-size = <32>; // 32 bytes
+ d-cache-size = <0x8000>; // L1, 32K
+ i-cache-size = <0x8000>; // L1, 32K
+ timebase-frequency = <0>;
+ bus-frequency = <0>;
+ clock-frequency = <0>;
+ };
+ };
+
+ memory {
+ device_type = "memory";
+ reg = <0x0 0x08000000>; // 128M at 0x0
+ };
+
+ localbus at f1000000 {
+ #address-cells = <2>;
+ #size-cells = <1>;
+ compatible = "mrvl,lbc";
+
+ /* This reflects CPU decode windows setup. */
+ ranges = <0x0 0x0f 0xf9300000 0x00100000
+ 0x1 0x1e 0xfa000000 0x00100000
+ 0x2 0x1d 0xfa100000 0x02000000>;
+
+ nor at 0,0 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "cfi-flash";
+ reg = <0x0 0x0 0x00100000>;
+ bank-width = <2>;
+ device-width = <1>;
+ };
+
+ led at 1,0 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "led";
+ reg = <0x1 0x0 0x00100000>;
+ };
+
+ nor at 2,0 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "cfi-flash";
+ reg = <0x2 0x0 0x02000000>;
+ bank-width = <2>;
+ device-width = <1>;
+ };
+ };
+
+ soc88f5182 at f1000000 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "simple-bus";
+ ranges = <0x0 0xf1000000 0x00100000>;
+ bus-frequency = <0>;
+
+ PIC: pic at 20200 {
+ interrupt-controller;
+ #address-cells = <0>;
+ #interrupt-cells = <1>;
+ reg = <0x20200 0x3c>;
+ compatible = "mrvl,pic";
+ };
+
+ timer at 20300 {
+ compatible = "mrvl,timer";
+ reg = <0x20300 0x30>;
+ interrupts = <0>;
+ interrupt-parent = <&PIC>;
+ mrvl,has-wdt;
+ };
+
+ MPP: mpp at 10000 {
+ #pin-cells = <2>;
+ compatible = "mrvl,mpp";
+ reg = <0x10000 0x54>;
+ pin-count = <20>;
+ pin-map = <
+ 0 3 /* MPP[0]: GPIO[0] */
+ 2 2 /* MPP[2]: PCI_REQn[3] */
+ 3 2 /* MPP[3]: PCI_GNTn[3] */
+ 4 2 /* MPP[4]: PCI_REQn[4] */
+ 5 2 /* MPP[5]: PCI_GNTn[4] */
+ 6 5 /* MPP[6]: SATA0_ACT */
+ 7 5 /* MPP[7]: SATA1_ACT */
+ 12 5 /* MPP[12]: SATA0_PRESENT */
+ 13 5 /* MPP[13]: SATA1_PRESENT */
+ 14 4 /* MPP[14]: NAND Flash REn[2] */
+ 15 4 /* MPP[15]: NAND Flash WEn[2] */
+ 16 0 /* MPP[16]: UA1_RXD */
+ 17 0 /* MPP[17]: UA1_TXD */
+ 18 0 /* MPP[18]: UA1_CTS */
+ 19 0 >; /* MPP[19]: UA1_RTS */
+ };
+
+ GPIO: gpio at 10100 {
+ #gpio-cells = <3>;
+ compatible = "mrvl,gpio";
+ reg = <0x10100 0x20>;
+ gpio-controller;
+ interrupts = <6 7 8 9>;
+ interrupt-parent = <&PIC>;
+ };
+
+ twsi at 11000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "mrvl,twsi";
+ reg = <0x11000 0x20>;
+ interrupts = <43>;
+ interrupt-parent = <&PIC>;
+ };
+
+ enet0: ethernet at 72000 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ model = "V1";
+ compatible = "mrvl,ge";
+ reg = <0x72000 0x2000>;
+ ranges = <0x0 0x72000 0x2000>;
+ local-mac-address = [ 00 00 00 00 00 00 ];
+ interrupts = <18 19 20 21 22>;
+ interrupt-parent = <&PIC>;
+ };
+
+ serial0: serial at 12000 {
+ compatible = "ns16550";
+ reg = <0x12000 0x20>;
+ reg-shift = <2>;
+ clock-frequency = <0>;
+ interrupts = <3>;
+ interrupt-parent = <&PIC>;
+ };
+
+ serial1: serial at 12100 {
+ compatible = "ns16550";
+ reg = <0x12100 0x20>;
+ reg-shift = <2>;
+ clock-frequency = <0>;
+ interrupts = <4>;
+ interrupt-parent = <&PIC>;
+ };
+
+ usb at 50000 {
+ compatible = "mrvl,usb-ehci", "usb-ehci";
+ reg = <0x50000 0x1000>;
+ interrupts = <17 16>;
+ interrupt-parent = <&PIC>;
+ };
+
+ idma at 60000 {
+ compatible = "mrvl,idma";
+ reg = <0x60000 0x1000>;
+ interrupts = <24 25 26 27 23>;
+ interrupt-parent = <&PIC>;
+ };
+
+ sata at 80000 {
+ compatible = "mrvl,sata";
+ reg = <0x80000 0x6000>;
+ interrupts = <29>;
+ interrupt-parent = <&PIC>;
+ };
+ };
+};
Property changes on: trunk/sys/boot/fdt/dts/arm/db88f5182.dts
___________________________________________________________________
Added: svn:eol-style
## -0,0 +1 ##
+native
\ No newline at end of property
Added: svn:keywords
## -0,0 +1 ##
+MidnightBSD=%H
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+text/plain
\ No newline at end of property
Added: trunk/sys/boot/fdt/dts/arm/db88f5281.dts
===================================================================
--- trunk/sys/boot/fdt/dts/arm/db88f5281.dts (rev 0)
+++ trunk/sys/boot/fdt/dts/arm/db88f5281.dts 2018-06-02 12:34:49 UTC (rev 10205)
@@ -0,0 +1,228 @@
+/* $MidnightBSD$ */
+/*
+ * Copyright (c) 2010 The FreeBSD Foundation
+ * All rights reserved.
+ *
+ * This software was developed by Semihalf under sponsorship from
+ * the FreeBSD Foundation.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ * Marvell DB-88F5281 Device Tree Source.
+ *
+ * $FreeBSD: stable/10/sys/boot/fdt/dts/arm/db88f5281.dts 262614 2014-02-28 18:29:09Z imp $
+ */
+
+/dts-v1/;
+
+/ {
+ model = "mrvl,DB-88F5281";
+ compatible = "DB-88F5281-BP", "DB-88F5281-BP-A";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ aliases {
+ ethernet0 = &enet0;
+ serial0 = &serial0;
+ serial1 = &serial1;
+ mpp = &MPP;
+ };
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cpu at 0 {
+ device_type = "cpu";
+ compatible = "ARM,88FR531";
+ reg = <0x0>;
+ d-cache-line-size = <32>; // 32 bytes
+ i-cache-line-size = <32>; // 32 bytes
+ d-cache-size = <0x8000>; // L1, 32K
+ i-cache-size = <0x8000>; // L1, 32K
+ timebase-frequency = <0>;
+ bus-frequency = <0>;
+ clock-frequency = <0>;
+ };
+ };
+
+ memory {
+ device_type = "memory";
+ reg = <0x0 0x08000000>; // 128M at 0x0
+ };
+
+ localbus at f1000000 {
+ #address-cells = <2>;
+ #size-cells = <1>;
+ compatible = "mrvl,lbc";
+
+ /* This reflects CPU decode windows setup. */
+ ranges = <0x0 0x0f 0xf9300000 0x00100000
+ 0x1 0x1e 0xfa000000 0x00100000
+ 0x2 0x1d 0xfa100000 0x02000000>;
+
+ nor at 0,0 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "cfi-flash";
+ reg = <0x0 0x0 0x00100000>;
+ bank-width = <2>;
+ device-width = <1>;
+ };
+
+ led at 1,0 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "led";
+ reg = <0x1 0x0 0x00100000>;
+ };
+
+ nor at 2,0 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "cfi-flash";
+ reg = <0x2 0x0 0x02000000>;
+ bank-width = <2>;
+ device-width = <1>;
+ };
+ };
+
+ soc88f5281 at f1000000 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "simple-bus";
+ ranges = <0x0 0xf1000000 0x00100000>;
+ bus-frequency = <0>;
+
+ PIC: pic at 20200 {
+ interrupt-controller;
+ #address-cells = <0>;
+ #interrupt-cells = <1>;
+ reg = <0x20200 0x3c>;
+ compatible = "mrvl,pic";
+ };
+
+ timer at 20300 {
+ compatible = "mrvl,timer";
+ reg = <0x20300 0x30>;
+ interrupts = <0>;
+ interrupt-parent = <&PIC>;
+ mrvl,has-wdt;
+ };
+
+ MPP: mpp at 10000 {
+ #pin-cells = <2>;
+ compatible = "mrvl,mpp";
+ reg = <0x10000 0x54>;
+ pin-count = <20>;
+ pin-map = <
+ 0 3 /* MPP[0]: GPIO[0] */
+ 2 2 /* MPP[2]: PCI_REQn[3] */
+ 3 2 /* MPP[3]: PCI_GNTn[3] */
+ 4 2 /* MPP[4]: PCI_REQn[4] */
+ 5 2 /* MPP[5]: PCI_GNTn[4] */
+ 6 3 /* MPP[6]: <UNKNOWN> */
+ 7 3 /* MPP[7]: <UNKNOWN> */
+ 8 3 /* MPP[8]: <UNKNOWN> */
+ 9 3 /* MPP[9]: <UNKNOWN> */
+ 14 4 /* MPP[14]: NAND Flash REn[2] */
+ 15 4 /* MPP[15]: NAND Flash WEn[2] */
+ 16 0 /* MPP[16]: UA1_RXD */
+ 17 0 /* MPP[17]: UA1_TXD */
+ 18 0 /* MPP[18]: UA1_CTS */
+ 19 0 >; /* MPP[19]: UA1_RTS */
+ };
+
+ GPIO: gpio at 10100 {
+ #gpio-cells = <3>;
+ compatible = "mrvl,gpio";
+ reg = <0x10100 0x20>;
+ gpio-controller;
+ interrupts = <6 7 8 9>;
+ interrupt-parent = <&PIC>;
+ };
+
+ twsi at 11000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "mrvl,twsi";
+ reg = <0x11000 0x20>;
+ interrupts = <43>;
+ interrupt-parent = <&PIC>;
+ };
+
+ enet0: ethernet at 72000 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ model = "V1";
+ compatible = "mrvl,ge";
+ reg = <0x72000 0x2000>;
+ ranges = <0x0 0x72000 0x2000>;
+ local-mac-address = [ 00 00 00 00 00 00 ];
+ interrupts = <18 19 20 21 22>;
+ interrupt-parent = <&PIC>;
+ phy-handle = <&phy0>;
+
+ mdio at 0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "mrvl,mdio";
+
+ phy0: ethernet-phy at 0 {
+ reg = <0x8>;
+ };
+ };
+ };
+
+ serial0: serial at 12000 {
+ compatible = "ns16550";
+ reg = <0x12000 0x20>;
+ reg-shift = <2>;
+ clock-frequency = <0>;
+ interrupts = <3>;
+ interrupt-parent = <&PIC>;
+ };
+
+ serial1: serial at 12100 {
+ compatible = "ns16550";
+ reg = <0x12100 0x20>;
+ reg-shift = <2>;
+ clock-frequency = <0>;
+ interrupts = <4>;
+ interrupt-parent = <&PIC>;
+ };
+
+ usb at 50000 {
+ compatible = "mrvl,usb-ehci", "usb-ehci";
+ reg = <0x50000 0x1000>;
+ interrupts = <17 16>;
+ interrupt-parent = <&PIC>;
+ };
+
+ idma at 60000 {
+ compatible = "mrvl,idma";
+ reg = <0x60000 0x1000>;
+ interrupts = <24 25 26 27 23>;
+ interrupt-parent = <&PIC>;
+ };
+ };
+};
Property changes on: trunk/sys/boot/fdt/dts/arm/db88f5281.dts
___________________________________________________________________
Added: svn:eol-style
## -0,0 +1 ##
+native
\ No newline at end of property
Added: svn:keywords
## -0,0 +1 ##
+MidnightBSD=%H
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+text/plain
\ No newline at end of property
Added: trunk/sys/boot/fdt/dts/arm/db88f6281.dts
===================================================================
--- trunk/sys/boot/fdt/dts/arm/db88f6281.dts (rev 0)
+++ trunk/sys/boot/fdt/dts/arm/db88f6281.dts 2018-06-02 12:34:49 UTC (rev 10205)
@@ -0,0 +1,299 @@
+/* $MidnightBSD$ */
+/*
+ * Copyright (c) 2009-2010 The FreeBSD Foundation
+ * All rights reserved.
+ *
+ * This software was developed by Semihalf under sponsorship from
+ * the FreeBSD Foundation.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ * Marvell DB-88F6281 Device Tree Source.
+ *
+ * $FreeBSD: stable/10/sys/boot/fdt/dts/arm/db88f6281.dts 262614 2014-02-28 18:29:09Z imp $
+ */
+
+/dts-v1/;
+
+/ {
+ model = "mrvl,DB-88F6281";
+ compatible = "DB-88F6281-BP", "DB-88F6281-BP-A";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ aliases {
+ ethernet0 = &enet0;
+ mpp = &MPP;
+ pci0 = &pci0;
+ serial0 = &serial0;
+ serial1 = &serial1;
+ soc = &SOC;
+ sram = &SRAM;
+ };
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cpu at 0 {
+ device_type = "cpu";
+ compatible = "ARM,88FR131";
+ reg = <0x0>;
+ d-cache-line-size = <32>; // 32 bytes
+ i-cache-line-size = <32>; // 32 bytes
+ d-cache-size = <0x4000>; // L1, 16K
+ i-cache-size = <0x4000>; // L1, 16K
+ timebase-frequency = <0>;
+ bus-frequency = <0>;
+ clock-frequency = <0>;
+ };
+ };
+
+ memory {
+ device_type = "memory";
+ reg = <0x0 0x20000000>; // 512M at 0x0
+ };
+
+ localbus at 0 {
+ #address-cells = <2>;
+ #size-cells = <1>;
+ compatible = "mrvl,lbc";
+ bank-count = <3>;
+
+ /* This reflects CPU decode windows setup. */
+ ranges = <0x0 0x2f 0xf9300000 0x00100000>;
+
+ nand at 0,0 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "mrvl,nfc";
+ reg = <0x0 0x0 0x00100000>;
+ bank-width = <2>;
+ device-width = <1>;
+
+ slice at 0 {
+ reg = <0x0 0x200000>;
+ label = "u-boot";
+ read-only;
+ };
+
+ slice at 200000 {
+ reg = <0x200000 0x7e00000>;
+ label = "root";
+ };
+ };
+ };
+
+ SOC: soc88f6281 at f1000000 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "simple-bus";
+ ranges = <0x0 0xf1000000 0x00100000>;
+ bus-frequency = <0>;
+
+ PIC: pic at 20200 {
+ interrupt-controller;
+ #address-cells = <0>;
+ #interrupt-cells = <1>;
+ reg = <0x20200 0x3c>;
+ compatible = "mrvl,pic";
+ };
+
+ timer at 20300 {
+ compatible = "mrvl,timer";
+ reg = <0x20300 0x30>;
+ interrupts = <1>;
+ interrupt-parent = <&PIC>;
+ mrvl,has-wdt;
+ };
+
+ MPP: mpp at 10000 {
+ #pin-cells = <2>;
+ compatible = "mrvl,mpp";
+ reg = <0x10000 0x34>;
+ pin-count = <50>;
+ pin-map = <
+ 0 1 /* MPP[0]: NF_IO[2] */
+ 1 1 /* MPP[1]: NF_IO[3] */
+ 2 1 /* MPP[2]: NF_IO[4] */
+ 3 1 /* MPP[3]: NF_IO[5] */
+ 4 1 /* MPP[4]: NF_IO[6] */
+ 5 1 /* MPP[5]: NF_IO[7] */
+ 6 1 /* MPP[6]: SYSRST_OUTn */
+ 7 2 /* MPP[7]: SPI_SCn */
+ 8 1 /* MPP[8]: TW_SDA */
+ 9 1 /* MPP[9]: TW_SCK */
+ 10 3 /* MPP[10]: UA0_TXD */
+ 11 3 /* MPP[11]: UA0_RXD */
+ 12 1 /* MPP[12]: SD_CLK */
+ 13 1 /* MPP[13]: SD_CMD */
+ 14 1 /* MPP[14]: SD_D[0] */
+ 15 1 /* MPP[15]: SD_D[1] */
+ 16 1 /* MPP[16]: SD_D[2] */
+ 17 1 /* MPP[17]: SD_D[3] */
+ 18 1 /* MPP[18]: NF_IO[0] */
+ 19 1 /* MPP[19]: NF_IO[1] */
+ 20 5 /* MPP[20]: SATA1_AC */
+ 21 5 >; /* MPP[21]: SATA0_AC */
+ };
+
+ GPIO: gpio at 10100 {
+ #gpio-cells = <3>;
+ compatible = "mrvl,gpio";
+ reg = <0x10100 0x20>;
+ gpio-controller;
+ interrupts = <35 36 37 38 39 40 41>;
+ interrupt-parent = <&PIC>;
+ };
+
+ rtc at 10300 {
+ compatible = "mrvl,rtc";
+ reg = <0x10300 0x08>;
+ };
+
+ twsi at 11000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "mrvl,twsi";
+ reg = <0x11000 0x20>;
+ interrupts = <43>;
+ interrupt-parent = <&PIC>;
+ };
+
+ enet0: ethernet at 72000 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ model = "V2";
+ compatible = "mrvl,ge";
+ reg = <0x72000 0x2000>;
+ ranges = <0x0 0x72000 0x2000>;
+ local-mac-address = [ 00 00 00 00 00 00 ];
+ interrupts = <12 13 14 11 46>;
+ interrupt-parent = <&PIC>;
+ phy-handle = <&phy0>;
+
+ mdio at 0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "mrvl,mdio";
+
+ phy0: ethernet-phy at 0 {
+ reg = <0x8>;
+ };
+ };
+ };
+
+ serial0: serial at 12000 {
+ compatible = "ns16550";
+ reg = <0x12000 0x20>;
+ reg-shift = <2>;
+ clock-frequency = <0>;
+ interrupts = <33>;
+ interrupt-parent = <&PIC>;
+ };
+
+ serial1: serial at 12100 {
+ compatible = "ns16550";
+ reg = <0x12100 0x20>;
+ reg-shift = <2>;
+ clock-frequency = <0>;
+ interrupts = <34>;
+ interrupt-parent = <&PIC>;
+ };
+
+ crypto at 30000 {
+ compatible = "mrvl,cesa";
+ reg = <0x30000 0x10000>;
+ interrupts = <22>;
+ interrupt-parent = <&PIC>;
+
+ sram-handle = <&SRAM>;
+ };
+
+ usb at 50000 {
+ compatible = "mrvl,usb-ehci", "usb-ehci";
+ reg = <0x50000 0x1000>;
+ interrupts = <48 19>;
+ interrupt-parent = <&PIC>;
+ };
+
+ xor at 60000 {
+ compatible = "mrvl,xor";
+ reg = <0x60000 0x1000>;
+ interrupts = <5 6 7 8>;
+ interrupt-parent = <&PIC>;
+ };
+
+ sata at 80000 {
+ compatible = "mrvl,sata";
+ reg = <0x80000 0x6000>;
+ interrupts = <21>;
+ interrupt-parent = <&PIC>;
+ };
+ };
+
+ SRAM: sram at fd000000 {
+ compatible = "mrvl,cesa-sram";
+ reg = <0xfd000000 0x00100000>;
+ };
+
+ pci0: pcie at f1040000 {
+ compatible = "mrvl,pcie";
+ device_type = "pci";
+ #interrupt-cells = <1>;
+ #size-cells = <2>;
+ #address-cells = <3>;
+ reg = <0xf1040000 0x2000>;
+ bus-range = <0 255>;
+ ranges = <0x02000000 0x0 0xf1300000 0xf1300000 0x0 0x04000000
+ 0x01000000 0x0 0x00000000 0xf1100000 0x0 0x00100000>;
+ clock-frequency = <33333333>;
+ interrupt-parent = <&PIC>;
+ interrupts = <44>;
+ interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
+ interrupt-map = <
+ /* IDSEL 0x1 */
+ 0x0800 0x0 0x0 0x1 &PIC 0x9
+ 0x0800 0x0 0x0 0x2 &PIC 0x9
+ 0x0800 0x0 0x0 0x3 &PIC 0x9
+ 0x0800 0x0 0x0 0x4 &PIC 0x9
+ >;
+ pcie at 0 {
+ reg = <0x0 0x0 0x0 0x0 0x0>;
+ #size-cells = <2>;
+ #address-cells = <3>;
+ device_type = "pci";
+ ranges = <0x02000000 0x0 0xf1300000
+ 0x02000000 0x0 0xf1300000
+ 0x0 0x04000000
+
+ 0x01000000 0x0 0x0
+ 0x01000000 0x0 0x0
+ 0x0 0x00100000>;
+ };
+ };
+
+ chosen {
+ stdin = "serial0";
+ stdout = "serial0";
+ };
+};
Property changes on: trunk/sys/boot/fdt/dts/arm/db88f6281.dts
___________________________________________________________________
Added: svn:eol-style
## -0,0 +1 ##
+native
\ No newline at end of property
Added: svn:keywords
## -0,0 +1 ##
+MidnightBSD=%H
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+text/plain
\ No newline at end of property
Added: trunk/sys/boot/fdt/dts/arm/digi-ccwmx53.dts
===================================================================
--- trunk/sys/boot/fdt/dts/arm/digi-ccwmx53.dts (rev 0)
+++ trunk/sys/boot/fdt/dts/arm/digi-ccwmx53.dts 2018-06-02 12:34:49 UTC (rev 10205)
@@ -0,0 +1,154 @@
+/* $MidnightBSD$ */
+/*
+ * Copyright (c) 2012 The FreeBSD Foundation
+ * Copyright (c) 2013 Rui Paulo
+ * All rights reserved.
+ *
+ * This software was developed by Semihalf under sponsorship from
+ * the FreeBSD Foundation.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ * Digi ConnectCore Wi-i.MX53
+ *
+ * $FreeBSD: stable/10/sys/boot/fdt/dts/arm/digi-ccwmx53.dts 266367 2014-05-17 22:02:26Z ian $
+ */
+
+/dts-v1/;
+/include/ "imx53x.dtsi"
+
+/ {
+ model = "Digi ConnectCore Wi-i.MX53";
+ compatible = "digi,imx53-ccwm53";
+
+ memory {
+ /* RAM 512M */
+ reg = <0x70000000 0x10000000
+ 0xB0000000 0x10000000>;
+ };
+
+ localbus at 10000000 {
+ sata at 10000000 {
+ status = "okay";
+ };
+ ipu3 at 1E000000 {
+ status = "okay";
+ };
+ };
+
+ soc at 50000000 {
+ aips at 50000000 {
+ spba at 50000000 {
+ esdhc at 50004000 {
+ clock-frequency = <216000000>;
+ status = "okay";
+ };
+ esdhc at 50008000 {
+ clock-frequency = <216000000>;
+ status = "okay";
+ };
+ SSI2: ssi at 50014000 {
+ status = "okay";
+ };
+ };
+ timer at 53fa0000 {
+ status = "okay";
+ };
+ /* UART1, console */
+ console: serial at 53fbc000 {
+ status = "okay";
+ clock-frequency = <0>; /* won't load w/o this */
+ };
+ serial at 53fc0000 {
+ status = "okay";
+ clock-frequency = <0>; /* won't load w/o this */
+ };
+ serial at 53ff0000 {
+ status = "okay";
+ clock-frequency = <0>; /* won't load w/o this */
+ };
+ clock at 53fd4000 {
+ status = "okay";
+ };
+ gpio at 53f84000 {
+ status = "okay";
+ };
+ gpio at 53f88000 {
+ status = "okay";
+ };
+ gpio at 53f8c000 {
+ status = "okay";
+ };
+ gpio at 53f90000 {
+ status = "okay";
+ };
+ usb at 53f80000 /* OTG */ {
+ status = "okay";
+ };
+ usb at 53f80200 /* Host 1 */ {
+ status = "okay";
+ };
+ wdog at 53f98000 {
+ status = "okay";
+ };
+ i2c at 53fec000 {
+ status = "okay";
+ rtc at 68 {
+ compatible = "dialog,ds9052";
+ reg = <0x48>;
+ interrupts = <0x1 0x1 0 0>;
+ };
+ };
+ };
+ aips at 60000000 {
+ ethernet at 63fec000 {
+ status = "okay";
+ phy-mode = "rmii";
+ };
+ i2c at 63fc4000 {
+ status = "okay";
+ };
+ i2c at 63fc8000 {
+ status = "okay";
+ };
+ audmux at 63fd4000 {
+ status = "okay";
+ };
+ ide at 63fe0000 {
+ status = "okay";
+ };
+ serial at 63f90000 {
+ status = "okay";
+ };
+ };
+ };
+
+ aliases {
+ SSI2 = &SSI2;
+ };
+
+ chosen {
+ bootargs = "-v";
+ stdin = &console;
+ stdout = &console;
+ };
+};
Property changes on: trunk/sys/boot/fdt/dts/arm/digi-ccwmx53.dts
___________________________________________________________________
Added: svn:eol-style
## -0,0 +1 ##
+native
\ No newline at end of property
Added: svn:keywords
## -0,0 +1 ##
+MidnightBSD=%H
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+text/plain
\ No newline at end of property
Added: trunk/sys/boot/fdt/dts/arm/dockstar.dts
===================================================================
--- trunk/sys/boot/fdt/dts/arm/dockstar.dts (rev 0)
+++ trunk/sys/boot/fdt/dts/arm/dockstar.dts 2018-06-02 12:34:49 UTC (rev 10205)
@@ -0,0 +1,241 @@
+/* $MidnightBSD$ */
+/*
+ * Copyright (c) 2010 The FreeBSD Foundation
+ * All rights reserved.
+ *
+ * This software was developed by Semihalf under sponsorship from
+ * the FreeBSD Foundation.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ * Seagate DockStar (Marvell SheevaPlug based) Device Tree Source.
+ *
+ * $FreeBSD: stable/10/sys/boot/fdt/dts/arm/dockstar.dts 262614 2014-02-28 18:29:09Z imp $
+ */
+
+/dts-v1/;
+
+/ {
+ model = "seagate,DockStar";
+ compatible = "DockStar";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ aliases {
+ ethernet0 = &enet0;
+ mpp = &MPP;
+ serial0 = &serial0;
+ serial1 = &serial1;
+ soc = &SOC;
+ sram = &SRAM;
+ };
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cpu at 0 {
+ device_type = "cpu";
+ compatible = "ARM,88FR131";
+ reg = <0x0>;
+ d-cache-line-size = <32>; // 32 bytes
+ i-cache-line-size = <32>; // 32 bytes
+ d-cache-size = <0x4000>; // L1, 16K
+ i-cache-size = <0x4000>; // L1, 16K
+ timebase-frequency = <0>;
+ bus-frequency = <0>;
+ clock-frequency = <0>;
+ };
+ };
+
+ memory {
+ device_type = "memory";
+ reg = <0x0 0x8000000>; // 128M at 0x0
+ };
+
+ localbus at f1000000 {
+ #address-cells = <2>;
+ #size-cells = <1>;
+ compatible = "mrvl,lbc";
+
+ /* This reflects CPU decode windows setup for NAND access. */
+ ranges = <0x0 0x2f 0xf9300000 0x00100000>;
+
+ nand at 0,0 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "mrvl,nfc";
+ reg = <0x0 0x0 0x00100000>;
+ bank-width = <2>;
+ device-width = <1>;
+ };
+ };
+
+ SOC: soc88f6281 at f1000000 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "simple-bus";
+ ranges = <0x0 0xf1000000 0x00100000>;
+ bus-frequency = <0>;
+
+ PIC: pic at 20200 {
+ interrupt-controller;
+ #address-cells = <0>;
+ #interrupt-cells = <1>;
+ reg = <0x20200 0x3c>;
+ compatible = "mrvl,pic";
+ };
+
+ timer at 20300 {
+ compatible = "mrvl,timer";
+ reg = <0x20300 0x30>;
+ interrupts = <1>;
+ interrupt-parent = <&PIC>;
+ mrvl,has-wdt;
+ };
+
+ MPP: mpp at 10000 {
+ #pin-cells = <2>;
+ compatible = "mrvl,mpp";
+ reg = <0x10000 0x34>;
+ pin-count = <50>;
+ pin-map = <
+ 0 1 /* MPP[0]: NF_IO[2] */
+ 1 1 /* MPP[1]: NF_IO[3] */
+ 2 1 /* MPP[2]: NF_IO[4] */
+ 3 1 /* MPP[3]: NF_IO[5] */
+ 4 1 /* MPP[4]: NF_IO[6] */
+ 5 1 /* MPP[5]: NF_IO[7] */
+ 6 1 /* MPP[6]: SYSRST_OUTn */
+ 8 2 /* MPP[8]: UA0_RTS */
+ 9 2 /* MPP[9]: UA0_CTS */
+ 10 3 /* MPP[10]: UA0_TXD */
+ 11 3 /* MPP[11]: UA0_RXD */
+ 12 1 /* MPP[12]: SD_CLK */
+ 13 1 /* MPP[13]: SD_CMD */
+ 14 1 /* MPP[14]: SD_D[0] */
+ 15 1 /* MPP[15]: SD_D[1] */
+ 16 1 /* MPP[16]: SD_D[2] */
+ 17 1 /* MPP[17]: SD_D[3] */
+ 18 1 /* MPP[18]: NF_IO[0] */
+ 19 1 /* MPP[19]: NF_IO[1] */
+ 29 1 >; /* MPP[29]: TSMP[9] */
+ };
+
+ GPIO: gpio at 10100 {
+ #gpio-cells = <3>;
+ compatible = "mrvl,gpio";
+ reg = <0x10100 0x20>;
+ gpio-controller;
+ interrupts = <35 36 37 38 39 40 41>;
+ interrupt-parent = <&PIC>;
+ };
+
+ rtc at 10300 {
+ compatible = "mrvl,rtc";
+ reg = <0x10300 0x08>;
+ };
+
+ twsi at 11000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "mrvl,twsi";
+ reg = <0x11000 0x20>;
+ interrupts = <43>;
+ interrupt-parent = <&PIC>;
+ };
+
+ enet0: ethernet at 72000 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ model = "V2";
+ compatible = "mrvl,ge";
+ reg = <0x72000 0x2000>;
+ ranges = <0x0 0x72000 0x2000>;
+ local-mac-address = [ 00 00 00 00 00 00 ];
+ interrupts = <12 13 14 11 46>;
+ interrupt-parent = <&PIC>;
+ phy-handle = <&phy0>;
+
+ mdio at 0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "mrvl,mdio";
+
+ phy0: ethernet-phy at 0 {
+ reg = <0x0>;
+ };
+ };
+ };
+
+ serial0: serial at 12000 {
+ compatible = "ns16550";
+ reg = <0x12000 0x20>;
+ reg-shift = <2>;
+ clock-frequency = <0>;
+ interrupts = <33>;
+ interrupt-parent = <&PIC>;
+ };
+
+ serial1: serial at 12100 {
+ compatible = "ns16550";
+ reg = <0x12100 0x20>;
+ reg-shift = <2>;
+ clock-frequency = <0>;
+ interrupts = <34>;
+ interrupt-parent = <&PIC>;
+ };
+
+ crypto at 30000 {
+ compatible = "mrvl,cesa";
+ reg = <0x30000 0x10000>;
+ interrupts = <22>;
+ interrupt-parent = <&PIC>;
+
+ sram-handle = <&SRAM>;
+ };
+
+ usb at 50000 {
+ compatible = "mrvl,usb-ehci", "usb-ehci";
+ reg = <0x50000 0x1000>;
+ interrupts = <48 19>;
+ interrupt-parent = <&PIC>;
+ };
+
+ xor at 60000 {
+ compatible = "mrvl,xor";
+ reg = <0x60000 0x1000>;
+ interrupts = <5 6 7 8>;
+ interrupt-parent = <&PIC>;
+ };
+ };
+
+ SRAM: sram at fd000000 {
+ compatible = "mrvl,cesa-sram";
+ reg = <0xfd000000 0x00100000>;
+ };
+
+ chosen {
+ stdin = "serial0";
+ stdout = "serial0";
+ };
+};
Property changes on: trunk/sys/boot/fdt/dts/arm/dockstar.dts
___________________________________________________________________
Added: svn:eol-style
## -0,0 +1 ##
+native
\ No newline at end of property
Added: svn:keywords
## -0,0 +1 ##
+MidnightBSD=%H
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+text/plain
\ No newline at end of property
Added: trunk/sys/boot/fdt/dts/arm/dreamplug-1001.dts
===================================================================
--- trunk/sys/boot/fdt/dts/arm/dreamplug-1001.dts (rev 0)
+++ trunk/sys/boot/fdt/dts/arm/dreamplug-1001.dts 2018-06-02 12:34:49 UTC (rev 10205)
@@ -0,0 +1,320 @@
+/* $MidnightBSD$ */
+/*
+ * Copyright (c) 2013 Ian Lepore
+ * Copyright (c) 2010 The FreeBSD Foundation
+ * All rights reserved.
+ *
+ * This software substantially based on work developed by Semihalf
+ * under sponsorship from the FreeBSD Foundation.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ * GlobalScale Technologies DreamPlug Device Tree Source.
+ *
+ * This source is for version 10 revision 01 units with NOR SPI flash.
+ * These units are marked "1001" on the serial number label.
+ *
+ * $FreeBSD: stable/10/sys/boot/fdt/dts/arm/dreamplug-1001.dts 262614 2014-02-28 18:29:09Z imp $
+ */
+
+/dts-v1/;
+
+/ {
+ model = "GlobalScale Technologies Dreamplug v1001";
+ compatible = "globalscale,dreamplug-003-ds2001", "globalscale,dreamplug", "marvell,kirkwood-88f6281", "marvell,kirkwood";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ aliases {
+ ethernet0 = &enet0;
+ ethernet1 = &enet1;
+ mpp = &MPP;
+ serial0 = &serial0;
+ serial1 = &serial1;
+ soc = &SOC;
+ sram = &SRAM;
+ };
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cpu at 0 {
+ device_type = "cpu";
+ compatible = "ARM,88FR131";
+ reg = <0x0>;
+ d-cache-line-size = <32>; // 32 bytes
+ i-cache-line-size = <32>; // 32 bytes
+ d-cache-size = <0x4000>; // L1, 16K
+ i-cache-size = <0x4000>; // L1, 16K
+ timebase-frequency = <0>;
+ bus-frequency = <0>;
+ clock-frequency = <0>;
+ };
+
+ };
+
+ memory {
+ device_type = "memory";
+ reg = <0x0 0x20000000>; // 512M at 0x0
+ };
+
+ localbus at 0 {
+ #address-cells = <2>;
+ #size-cells = <1>;
+ compatible = "mrvl,lbc";
+ bank-count = <1>;
+
+ /* This reflects CPU decode windows setup. */
+ ranges = <0x0 0x1e 0xfa000000 0x00100000>;
+
+ nor at 0,0 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "cfi-flash";
+ reg = <0x0 0x0 0x00100000>;
+ bank-width = <2>;
+ device-width = <1>;
+ };
+ };
+
+ SOC: soc88f6281 at f1000000 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "simple-bus";
+ ranges = <0x0 0xf1000000 0x00100000>;
+ bus-frequency = <0>;
+
+ PIC: pic at 20200 {
+ interrupt-controller;
+ #address-cells = <0>;
+ #interrupt-cells = <1>;
+ reg = <0x20200 0x3c>;
+ compatible = "mrvl,pic";
+ };
+
+ timer at 20300 {
+ compatible = "mrvl,timer";
+ reg = <0x20300 0x30>;
+ interrupts = <1>;
+ interrupt-parent = <&PIC>;
+ mrvl,has-wdt;
+ };
+
+ MPP: mpp at 10000 {
+ #pin-cells = <2>;
+ compatible = "mrvl,mpp";
+ reg = <0x10000 0x34>;
+ pin-count = <50>;
+ pin-map = <
+ 0 2 /* MPP[ 0]: SPI_SCn */
+ 1 2 /* MPP[ 1]: SPI_MOSI */
+ 2 2 /* MPP[ 2]: SPI_SCK */
+ 3 2 /* MPP[ 3]: SPI_MISO */
+ 4 1 /* MPP[ 4]: NF_IO[6] */
+ 5 1 /* MPP[ 5]: NF_IO[7] */
+ 6 1 /* MPP[ 6]: SYSRST_OUTn */
+ 7 0 /* MPP[ 7]: GPO[7] */
+ 8 1 /* MPP[ 8]: TW_SDA */
+ 9 1 /* MPP[ 9]: TW_SCK */
+ 10 3 /* MPP[10]: UA0_TXD */
+ 11 3 /* MPP[11]: US0_RXD */
+ 12 1 /* MPP[12]: SD_CLK */
+ 13 1 /* MPP[13]: SD_CMD */
+ 14 1 /* MPP[14]: SD_D[0] */
+ 15 1 /* MPP[15]: SD_D[1] */
+ 16 1 /* MPP[16]: SD_D[2] */
+ 17 1 /* MPP[17]: SD_D[3] */
+ 18 1 /* MPP[18]: NF_IO[0] */
+ 19 1 /* MPP[19]: NF_IO[1] */
+ 20 3 /* MPP[20]: GE1[ 0] */
+ 21 3 /* MPP[21]: GE1[ 1] */
+ 22 3 /* MPP[22]: GE1[ 2] */
+ 23 3 /* MPP[23]: GE1[ 3] */
+ 24 3 /* MPP[24]: GE1[ 4] */
+ 25 3 /* MPP[25]: GE1[ 5] */
+ 26 3 /* MPP[26]: GE1[ 6] */
+ 27 3 /* MPP[27]: GE1[ 7] */
+ 28 3 /* MPP[28]: GE1[ 8] */
+ 29 3 /* MPP[29]: GE1[ 9] */
+ 30 3 /* MPP[30]: GE1[10] */
+ 31 3 /* MPP[31]: GE1[11] */
+ 32 3 /* MPP[32]: GE1[12] */
+ 33 3 /* MPP[33]: GE1[13] */
+ 34 3 /* MPP[34]: GE1[14] */
+ 35 3 /* MPP[35]: GE1[15] */
+ 36 0 /* MPP[36]: GPIO[36] */
+ 37 0 /* MPP[37]: GPIO[37] */
+ 38 0 /* MPP[38]: GPIO[38] */
+ 39 0 /* MPP[39]: GPIO[39] */
+ 40 2 /* MPP[40]: TDM_SPI_SCK */
+ 41 2 /* MPP[41]: TDM_SPI_MISO */
+ 42 2 /* MPP[42]: TDM_SPI_MOSI */
+ 43 0 /* MPP[43]: GPIO[43] */
+ 44 0 /* MPP[44]: GPIO[44] */
+ 45 0 /* MPP[45]: GPIO[45] */
+ 46 0 /* MPP[46]: GPIO[46] */
+ 47 0 /* MPP[47]: GPIO[47] */
+ 48 0 /* MPP[48]: GPIO[48] */
+ 49 0 /* MPP[49]: GPIO[49] */
+ >;
+ };
+
+ GPIO: gpio at 10100 {
+ #gpio-cells = <3>;
+ compatible = "mrvl,gpio";
+ reg = <0x10100 0x20>;
+ gpio-controller;
+ interrupts = <35 36 37 38 39 40 41>;
+ interrupt-parent = <&PIC>;
+ pin-count = <50>;
+ };
+
+ gpioled at 0 {
+ compatible = "mrvl,gpioled";
+
+ gpios = <&GPIO 47 2 0 /* GPIO[47] BT LED: OUT */
+ &GPIO 48 2 0 /* GPIO[48] WLAN LED: OUT */
+ &GPIO 49 2 0>; /* GPIO[49] WLAN AP LED: OUT */
+ };
+
+ rtc at 10300 {
+ compatible = "mrvl,rtc";
+ reg = <0x10300 0x08>;
+ };
+
+ twsi at 11000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "mrvl,twsi";
+ reg = <0x11000 0x20>;
+ interrupts = <43>;
+ interrupt-parent = <&PIC>;
+ };
+
+ enet0: ethernet at 72000 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ model = "V2";
+ compatible = "mrvl,ge";
+ reg = <0x72000 0x2000>;
+ ranges = <0x0 0x72000 0x2000>;
+ local-mac-address = [ 00 00 00 00 00 00 ];
+ interrupts = <12 13 14 11 46>;
+ interrupt-parent = <&PIC>;
+ phy-handle = <&phy0>;
+
+ mdio at 0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "mrvl,mdio";
+
+ phy0: ethernet-phy at 0 {
+ reg = <0x0>;
+ };
+
+ phy1: ethernet-phy at 1 {
+ reg = <0x1>;
+ };
+ };
+ };
+
+ enet1: ethernet at 76000 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ model = "V2";
+ compatible = "mrvl,ge";
+ reg = <0x76000 0x02000>;
+ ranges = <0x0 0x76000 0x2000>;
+ local-mac-address = [ 00 00 00 00 00 00 ];
+ interrupts = <16 17 18 15 47>;
+ interrupt-parent = <&PIC>;
+ phy-handle = <&phy1>;
+ };
+
+ serial0: serial at 12000 {
+ compatible = "ns16550";
+ reg = <0x12000 0x20>;
+ reg-shift = <2>;
+ clock-frequency = <0>;
+ interrupts = <33>;
+ interrupt-parent = <&PIC>;
+ };
+
+ serial1: serial at 12100 {
+ compatible = "ns16550";
+ reg = <0x12100 0x20>;
+ reg-shift = <2>;
+ clock-frequency = <0>;
+ interrupts = <34>;
+ interrupt-parent = <&PIC>;
+ };
+
+ crypto at 30000 {
+ compatible = "mrvl,cesa";
+ reg = <0x30000 0x10000>;
+ interrupts = <22>;
+ interrupt-parent = <&PIC>;
+
+ sram-handle = <&SRAM>;
+ };
+
+ usb at 50000 {
+ compatible = "mrvl,usb-ehci", "usb-ehci";
+ reg = <0x50000 0x1000>;
+ interrupts = <48 19>;
+ interrupt-parent = <&PIC>;
+ };
+
+ xor at 60000 {
+ compatible = "mrvl,xor";
+ reg = <0x60000 0x1000>;
+ interrupts = <5 6 7 8>;
+ interrupt-parent = <&PIC>;
+ };
+
+ sata at 80000 {
+ compatible = "mrvl,sata";
+ reg = <0x80000 0x6000>;
+ interrupts = <21>;
+ interrupt-parent = <&PIC>;
+ };
+
+ sdio at 90000 {
+ compatible = "mrvl,sdio";
+ reg = <0x90000 0x134>;
+ interrupts = <28>;
+ interrupt-parent = <&PIC>;
+ };
+ };
+
+ SRAM: sram at fd000000 {
+ compatible = "mrvl,cesa-sram";
+ reg = <0xfd000000 0x00100000>;
+ };
+
+ chosen {
+ stdin = "serial0";
+ stdout = "serial0";
+ };
+
+};
Property changes on: trunk/sys/boot/fdt/dts/arm/dreamplug-1001.dts
___________________________________________________________________
Added: svn:eol-style
## -0,0 +1 ##
+native
\ No newline at end of property
Added: svn:keywords
## -0,0 +1 ##
+MidnightBSD=%H
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+text/plain
\ No newline at end of property
Added: trunk/sys/boot/fdt/dts/arm/dreamplug-1001N.dts
===================================================================
--- trunk/sys/boot/fdt/dts/arm/dreamplug-1001N.dts (rev 0)
+++ trunk/sys/boot/fdt/dts/arm/dreamplug-1001N.dts 2018-06-02 12:34:49 UTC (rev 10205)
@@ -0,0 +1,341 @@
+/* $MidnightBSD$ */
+/*
+ * Copyright (c) 2013 Ian Lepore
+ * Copyright (c) 2010 The FreeBSD Foundation
+ * All rights reserved.
+ *
+ * This software substantially based on work developed by Semihalf
+ * under sponsorship from the FreeBSD Foundation.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ * GlobalScale Technologies DreamPlug Device Tree Source.
+ *
+ * This source is for version 10 revision 01 units with NAND flash.
+ * These units are marked "1001N" on the serial number label.
+ *
+ * $FreeBSD: stable/10/sys/boot/fdt/dts/arm/dreamplug-1001N.dts 262614 2014-02-28 18:29:09Z imp $
+ */
+
+/dts-v1/;
+
+/ {
+ model = "GlobalScale Technologies Dreamplug v1001N";
+ compatible = "globalscale,dreamplug-003-ds2001", "globalscale,dreamplug", "marvell,kirkwood-88f6281", "marvell,kirkwood";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ aliases {
+ ethernet0 = &enet0;
+ ethernet1 = &enet1;
+ mpp = &MPP;
+ serial0 = &serial0;
+ serial1 = &serial1;
+ soc = &SOC;
+ sram = &SRAM;
+ };
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cpu at 0 {
+ device_type = "cpu";
+ compatible = "ARM,88FR131";
+ reg = <0x0>;
+ d-cache-line-size = <32>; // 32 bytes
+ i-cache-line-size = <32>; // 32 bytes
+ d-cache-size = <0x4000>; // L1, 16K
+ i-cache-size = <0x4000>; // L1, 16K
+ timebase-frequency = <0>;
+ bus-frequency = <0>;
+ clock-frequency = <0>;
+ };
+
+ };
+
+ memory {
+ device_type = "memory";
+ reg = <0x0 0x20000000>; // 512M at 0x0
+ };
+
+ localbus at 0 {
+ #address-cells = <2>;
+ #size-cells = <1>;
+ compatible = "mrvl,lbc";
+ bank-count = <1>;
+
+ /* This reflects CPU decode windows setup. */
+ ranges = <0x0 0x2f 0xf9300000 0x00100000>;
+
+ nand at 0,0 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "mrvl,nfc";
+ reg = <0x0 0x0 0x00100000>;
+ bank-width = <2>;
+ device-width = <1>;
+
+ // Slice info reported by builtin linux when it boots...
+ //[ 11.161328] 0x00000000-0x00100000 : "u-boot"
+ //[ 11.167431] 0x00100000-0x00500000 : "uImage"
+ //[ 11.173471] 0x00500000-0x20000000 : "root"
+
+ slice at 0 {
+ reg = <0x0 0x100000>;
+ label = "u-boot";
+ read-only;
+ };
+
+ slice at 200000 {
+ reg = <0x100000 0x40000>;
+ label = "uImage";
+ };
+
+ slice at 500000 {
+ reg = <0x500000 0x1FB00000>;
+ label = "root";
+ };
+ };
+ };
+
+ SOC: soc88f6281 at f1000000 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "simple-bus";
+ ranges = <0x0 0xf1000000 0x00100000>;
+ bus-frequency = <0>;
+
+ PIC: pic at 20200 {
+ interrupt-controller;
+ #address-cells = <0>;
+ #interrupt-cells = <1>;
+ reg = <0x20200 0x3c>;
+ compatible = "mrvl,pic";
+ };
+
+ timer at 20300 {
+ compatible = "mrvl,timer";
+ reg = <0x20300 0x30>;
+ interrupts = <1>;
+ interrupt-parent = <&PIC>;
+ mrvl,has-wdt;
+ };
+
+ MPP: mpp at 10000 {
+ #pin-cells = <2>;
+ compatible = "mrvl,mpp";
+ reg = <0x10000 0x34>;
+ pin-count = <50>;
+ pin-map = <
+ 0 1 /* MPP[ 0]: NF_IO[2] */
+ 1 1 /* MPP[ 1]: NF_IO[3] */
+ 2 1 /* MPP[ 2]: NF_IO[4] */
+ 3 1 /* MPP[ 3]: NF_IO[5] */
+ 4 1 /* MPP[ 4]: NF_IO[6] */
+ 5 1 /* MPP[ 5]: NF_IO[7] */
+ 6 1 /* MPP[ 6]: SYSRST_OUTn */
+ 7 0 /* MPP[ 7]: GPO[7] */
+ 8 1 /* MPP[ 8]: TW_SDA */
+ 9 1 /* MPP[ 9]: TW_SCK */
+ 10 3 /* MPP[10]: UA0_TXD */
+ 11 3 /* MPP[11]: US0_RXD */
+ 12 1 /* MPP[12]: SD_CLK */
+ 13 1 /* MPP[13]: SD_CMD */
+ 14 1 /* MPP[14]: SD_D[0] */
+ 15 1 /* MPP[15]: SD_D[1] */
+ 16 1 /* MPP[16]: SD_D[2] */
+ 17 1 /* MPP[17]: SD_D[3] */
+ 18 1 /* MPP[18]: NF_IO[0] */
+ 19 1 /* MPP[19]: NF_IO[1] */
+ 20 3 /* MPP[20]: GE1[ 0] */
+ 21 3 /* MPP[21]: GE1[ 1] */
+ 22 3 /* MPP[22]: GE1[ 2] */
+ 23 3 /* MPP[23]: GE1[ 3] */
+ 24 3 /* MPP[24]: GE1[ 4] */
+ 25 3 /* MPP[25]: GE1[ 5] */
+ 26 3 /* MPP[26]: GE1[ 6] */
+ 27 3 /* MPP[27]: GE1[ 7] */
+ 28 3 /* MPP[28]: GE1[ 8] */
+ 29 3 /* MPP[29]: GE1[ 9] */
+ 30 3 /* MPP[30]: GE1[10] */
+ 31 3 /* MPP[31]: GE1[11] */
+ 32 3 /* MPP[32]: GE1[12] */
+ 33 3 /* MPP[33]: GE1[13] */
+ 34 3 /* MPP[34]: GE1[14] */
+ 35 3 /* MPP[35]: GE1[15] */
+ 36 0 /* MPP[36]: GPIO[36] */
+ 37 0 /* MPP[37]: GPIO[37] */
+ 38 0 /* MPP[38]: GPIO[38] */
+ 39 0 /* MPP[39]: GPIO[39] */
+ 40 2 /* MPP[40]: TDM_SPI_SCK */
+ 41 2 /* MPP[41]: TDM_SPI_MISO */
+ 42 2 /* MPP[42]: TDM_SPI_MOSI */
+ 43 0 /* MPP[43]: GPIO[43] */
+ 44 0 /* MPP[44]: GPIO[44] */
+ 45 0 /* MPP[45]: GPIO[45] */
+ 46 0 /* MPP[46]: GPIO[46] */
+ 47 0 /* MPP[47]: GPIO[47] */
+ 48 0 /* MPP[48]: GPIO[48] */
+ 49 0 /* MPP[49]: GPIO[49] */
+ >;
+ };
+
+ GPIO: gpio at 10100 {
+ #gpio-cells = <3>;
+ compatible = "mrvl,gpio";
+ reg = <0x10100 0x20>;
+ gpio-controller;
+ interrupts = <35 36 37 38 39 40 41>;
+ interrupt-parent = <&PIC>;
+ pin-count = <50>;
+ };
+
+ gpioled at 0 {
+ compatible = "mrvl,gpioled";
+
+ gpios = <&GPIO 47 2 0 /* GPIO[47] BT LED: OUT */
+ &GPIO 48 2 0 /* GPIO[48] WLAN LED: OUT */
+ &GPIO 49 2 0>; /* GPIO[49] WLAN AP LED: OUT */
+ };
+
+ rtc at 10300 {
+ compatible = "mrvl,rtc";
+ reg = <0x10300 0x08>;
+ };
+
+ twsi at 11000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "mrvl,twsi";
+ reg = <0x11000 0x20>;
+ interrupts = <43>;
+ interrupt-parent = <&PIC>;
+ };
+
+ enet0: ethernet at 72000 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ model = "V2";
+ compatible = "mrvl,ge";
+ reg = <0x72000 0x2000>;
+ ranges = <0x0 0x72000 0x2000>;
+ local-mac-address = [ 00 00 00 00 00 00 ];
+ interrupts = <12 13 14 11 46>;
+ interrupt-parent = <&PIC>;
+ phy-handle = <&phy0>;
+
+ mdio at 0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "mrvl,mdio";
+
+ phy0: ethernet-phy at 0 {
+ reg = <0x0>;
+ };
+
+ phy1: ethernet-phy at 1 {
+ reg = <0x1>;
+ };
+ };
+ };
+
+ enet1: ethernet at 76000 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ model = "V2";
+ compatible = "mrvl,ge";
+ reg = <0x76000 0x02000>;
+ ranges = <0x0 0x76000 0x2000>;
+ local-mac-address = [ 00 00 00 00 00 00 ];
+ interrupts = <16 17 18 15 47>;
+ interrupt-parent = <&PIC>;
+ phy-handle = <&phy1>;
+ };
+
+ serial0: serial at 12000 {
+ compatible = "ns16550";
+ reg = <0x12000 0x20>;
+ reg-shift = <2>;
+ clock-frequency = <0>;
+ interrupts = <33>;
+ interrupt-parent = <&PIC>;
+ };
+
+ serial1: serial at 12100 {
+ compatible = "ns16550";
+ reg = <0x12100 0x20>;
+ reg-shift = <2>;
+ clock-frequency = <0>;
+ interrupts = <34>;
+ interrupt-parent = <&PIC>;
+ };
+
+ crypto at 30000 {
+ compatible = "mrvl,cesa";
+ reg = <0x30000 0x10000>;
+ interrupts = <22>;
+ interrupt-parent = <&PIC>;
+
+ sram-handle = <&SRAM>;
+ };
+
+ usb at 50000 {
+ compatible = "mrvl,usb-ehci", "usb-ehci";
+ reg = <0x50000 0x1000>;
+ interrupts = <48 19>;
+ interrupt-parent = <&PIC>;
+ };
+
+ xor at 60000 {
+ compatible = "mrvl,xor";
+ reg = <0x60000 0x1000>;
+ interrupts = <5 6 7 8>;
+ interrupt-parent = <&PIC>;
+ };
+
+ sata at 80000 {
+ compatible = "mrvl,sata";
+ reg = <0x80000 0x6000>;
+ interrupts = <21>;
+ interrupt-parent = <&PIC>;
+ };
+
+ sdio at 90000 {
+ compatible = "mrvl,sdio";
+ reg = <0x90000 0x134>;
+ interrupts = <28>;
+ interrupt-parent = <&PIC>;
+ };
+ };
+
+ SRAM: sram at fd000000 {
+ compatible = "mrvl,cesa-sram";
+ reg = <0xfd000000 0x00100000>;
+ };
+
+ chosen {
+ stdin = "serial0";
+ stdout = "serial0";
+ };
+
+};
Property changes on: trunk/sys/boot/fdt/dts/arm/dreamplug-1001N.dts
___________________________________________________________________
Added: svn:eol-style
## -0,0 +1 ##
+native
\ No newline at end of property
Added: svn:keywords
## -0,0 +1 ##
+MidnightBSD=%H
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+text/plain
\ No newline at end of property
Added: trunk/sys/boot/fdt/dts/arm/ea3250.dts
===================================================================
--- trunk/sys/boot/fdt/dts/arm/ea3250.dts (rev 0)
+++ trunk/sys/boot/fdt/dts/arm/ea3250.dts 2018-06-02 12:34:49 UTC (rev 10205)
@@ -0,0 +1,271 @@
+/* $MidnightBSD$ */
+/*
+ * Copyright (c) 2011 Jakub Klama <jceel at FreeBSD.org>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ * Embedded Artists LPC3250-Kit Device Tree Source.
+ *
+ * $FreeBSD: stable/10/sys/boot/fdt/dts/arm/ea3250.dts 262614 2014-02-28 18:29:09Z imp $
+ */
+
+/dts-v1/;
+
+/ {
+ model = "ea,LPC3250-KIT";
+ compatible = "LPC3250-KIT";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ aliases {
+ soc = &soc;
+ serial4 = &serial4;
+ };
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cpu at 0 {
+ device_type = "cpu";
+ compatible = "ARM,926EJ-S";
+ reg = <0x0>;
+ d-cache-line-size = <32>; // 32 bytes
+ i-cache-line-size = <32>; // 32 bytes
+ d-cache-size = <0x4000>; // L1, 16K
+ i-cache-size = <0x4000>; // L1, 16K
+ timebase-frequency = <0>;
+ bus-frequency = <0>;
+ clock-frequency = <0>;
+ };
+ };
+
+ memory {
+ device_type = "memory";
+ reg = <0x80000000 0x4000000>; // 64M at 0x80000000
+ };
+
+ soc: ahb7 at 40000000 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "simple-bus";
+ ranges = <0x0 0x40000000 0x10000000>;
+ bus-frequency = <13000000>;
+
+ pwr at 4000 {
+ compatible = "lpc,pwr";
+ reg = <0x4000 0x4000>;
+ };
+
+ PIC: pic at 8000 {
+ interrupt-controller;
+ #address-cells = <0>;
+ #interrupt-cells = <1>;
+ reg = <0x8000 0xc000>;
+ compatible = "lpc,pic";
+ };
+
+ timer at 44000 {
+ compatible = "lpc,timer";
+ reg = <0x44000 0x4000
+ 0x4c000 0x4000>;
+ interrupts = <16 17>;
+ interrupt-parent = <&PIC>;
+ };
+
+ rtc at 24000 {
+ compatible = "lpc,rtc";
+ reg = <0x24000 0x4000>;
+ interrupts = <52>;
+ interrupt-parent = <&PIC>;
+ };
+
+ serial0: serial at 14000 {
+ compatible = "lpc,hsuart";
+ status = "disabled";
+ reg = <0x14000 0x20>;
+ reg-shift = <2>;
+ clock-frequency = <0>;
+ interrupts = <26>;
+ interrupt-parent = <&PIC>;
+ };
+
+ serial1: serial at 18000 {
+ compatible = "lpc,hsuart";
+ status = "disabled";
+ reg = <0x18000 0x20>;
+ reg-shift = <2>;
+ clock-frequency = <0>;
+ interrupts = <25>;
+ interrupt-parent = <&PIC>;
+ };
+
+ serial2: serial at 80000 {
+ compatible = "lpc,uart";
+ status = "disabled";
+ reg = <0x80000 0x20>;
+ reg-shift = <2>;
+ clock-frequency = <13000000>;
+ interrupts = <7>;
+ interrupt-parent = <&PIC>;
+ };
+
+ serial3: serial at 88000 {
+ compatible = "lpc,uart";
+ status = "disabled";
+ reg = <0x88000 0x20>;
+ reg-shift = <2>;
+ clock-frequency = <13000000>;
+ interrupts = <8>;
+ interrupt-parent = <&PIC>;
+ };
+
+ serial4: serial at 90000 {
+ compatible = "lpc,uart";
+ reg = <0x90000 0x20>;
+ reg-shift = <2>;
+ clock-frequency = <13000000>;
+ current-speed = <115200>;
+ interrupts = <9>;
+ interrupt-parent = <&PIC>;
+ };
+
+ serial5: serial at 98000 {
+ compatible = "lpc,uart";
+ status = "disabled";
+ reg = <0x98000 0x20>;
+ reg-shift = <2>;
+ clock-frequency = <13000000>;
+ interrupts = <10>;
+ interrupt-parent = <&PIC>;
+ };
+
+ serial6: serial at 1c000 {
+ compatible = "lpc,uart";
+ status = "disabled";
+ reg = <0x1c000 0x20>;
+ reg-shift = <2>;
+ clock-frequency = <0>;
+ interrupts = <24>;
+ interrupt-parent = <&PIC>;
+ };
+
+ gpio at 28000 {
+ compatible = "lpc,gpio";
+ reg = <0x28000 0x4000>;
+ };
+ };
+
+ ahb6 at 30000000 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "simple-bus";
+ ranges = <0x0 0x30000000 0x10000000>;
+
+ dmac at 1000000 {
+ compatible = "lpc,dmac";
+ reg = <0x1000000 0x20000>;
+ interrupts = <28>;
+ interrupt-parent = <&PIC>;
+ };
+
+ usb at 1020000 {
+ compatible = "lpc,usb-ohci", "usb-ohci";
+ reg = <0x1020000 0x20000>;
+ interrupts = <59>;
+ interrupt-parent = <&PIC>;
+ };
+
+ lpcfb at 1040000 {
+ compatible = "lpc,fb";
+ reg = <0x1040000 0x20000>;
+ interrupts = <14>;
+ interrupt-parent = <&PIC>;
+
+ /* Screen parameters: */
+ is-tft = <1>;
+ horizontal-resolution = <240>;
+ vertical-resolution = <320>;
+ bits-per-pixel = <16>;
+ pixel-clock = <121654>;
+ left-margin = <28>;
+ right-margin = <10>;
+ upper-margin = <2>;
+ lower-margin = <2>;
+ hsync-len = <3>;
+ vsync-len = <2>;
+ };
+
+ lpe at 1060000 {
+ compatible = "lpc,ethernet";
+ reg = <0x1060000 0x20000>;
+ interrupts = <29>;
+ interrupt-parent = <&PIC>;
+ local-mac-address = [ 00 1a f1 01 1f 23 ];
+
+ mdio at 0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "lpc,mdio";
+
+ phy0: ethernet-phy at 0 {
+ reg = <0x0>;
+ };
+ };
+
+ };
+ };
+
+ ahb5 at 20000000 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "simple-bus";
+ ranges = <0x0 0x20000000 0x10000000>;
+
+ spi0 at 84000 {
+ compatible = "lpc,spi";
+ reg = <0x84000 0x4000>;
+ interrupts = <20>;
+ interrupt-parent = <&PIC>;
+ };
+
+ spi1 at 8c000 {
+ compatible = "lpc,spi";
+ status = "disabled";
+ reg = <0x8c000 0x4000>;
+ interrupts = <21>;
+ interrupt-parent = <&PIC>;
+ };
+
+ lpcmmc at 98000 {
+ compatible = "lpc,mmc";
+ reg = <0x98000 0x4000>;
+ interrupts = <15 13>;
+ interrupt-parent = <&PIC>;
+ };
+ };
+
+ chosen {
+ stdin = "serial4";
+ stdout = "serial4";
+ };
+};
Property changes on: trunk/sys/boot/fdt/dts/arm/ea3250.dts
___________________________________________________________________
Added: svn:eol-style
## -0,0 +1 ##
+native
\ No newline at end of property
Added: svn:keywords
## -0,0 +1 ##
+MidnightBSD=%H
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+text/plain
\ No newline at end of property
Added: trunk/sys/boot/fdt/dts/arm/efikamx.dts
===================================================================
--- trunk/sys/boot/fdt/dts/arm/efikamx.dts (rev 0)
+++ trunk/sys/boot/fdt/dts/arm/efikamx.dts 2018-06-02 12:34:49 UTC (rev 10205)
@@ -0,0 +1,129 @@
+/* $MidnightBSD$ */
+/*
+ * Copyright (c) 2012 The FreeBSD Foundation
+ * All rights reserved.
+ *
+ * This software was developed by Semihalf under sponsorship from
+ * the FreeBSD Foundation.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ * Freescale i.MX515 Device Tree Source.
+ *
+ * $FreeBSD: stable/10/sys/boot/fdt/dts/arm/efikamx.dts 262614 2014-02-28 18:29:09Z imp $
+ */
+
+/dts-v1/;
+/include/ "imx51x.dtsi"
+
+/ {
+ model = "Genesi Efika MX";
+ compatible = "genesi,imx51-efikamx";
+
+ memory {
+ /* RAM 512M */
+ reg = <0x90000000 0x20000000>;
+ };
+
+ localbus at 5e000000 {
+ ipu3 at 5e000000 {
+ status = "okay";
+ };
+ };
+
+ soc at 70000000 {
+ aips at 70000000 {
+ spba at 70000000 {
+ esdhc at 70004000 {
+ clock-frequency = <216000000>;
+ status = "okay";
+ };
+ esdhc at 70008000 {
+ clock-frequency = <216000000>;
+ status = "okay";
+ };
+ SSI2: ssi at 70014000 {
+ status = "okay";
+ };
+ };
+ timer at 73fa0000 {
+ status = "okay";
+ };
+
+ /* UART1, console */
+ UART1: serial at 73fbc000 {
+ status = "okay";
+ clock-frequency = <3000000>; /* XXX */
+ };
+
+ clock at 73fd4000 {
+ status = "okay";
+ };
+ gpio at 73f84000 {
+ status = "okay";
+ };
+ gpio at 73f88000 {
+ status = "okay";
+ };
+ gpio at 73f8c000 {
+ status = "okay";
+ };
+ gpio at 73f90000 {
+ status = "okay";
+ };
+ usb at 73f80000 /* OTG */ {
+ status = "okay";
+ };
+ usb at 73f80200 /* Host 1 */ {
+ status = "okay";
+ };
+ wdog at 73f98000 {
+ status = "okay";
+ };
+ };
+ aips at 80000000 {
+ i2c at 83fc4000 {
+ status = "okay";
+ };
+ i2c at 83fc8000 {
+ status = "okay";
+ };
+ audmux at 83fd4000 {
+ status = "okay";
+ };
+ ide at 83fe0000 {
+ status = "okay";
+ };
+ };
+ };
+
+ aliases {
+ UART1 = &UART1;
+ SSI2 = &SSI2;
+ };
+
+ chosen {
+ bootargs = "-v";
+ stdin = "UART1";
+ stdout = "UART1";
+ };
+};
Property changes on: trunk/sys/boot/fdt/dts/arm/efikamx.dts
___________________________________________________________________
Added: svn:eol-style
## -0,0 +1 ##
+native
\ No newline at end of property
Added: svn:keywords
## -0,0 +1 ##
+MidnightBSD=%H
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+text/plain
\ No newline at end of property
Added: trunk/sys/boot/fdt/dts/arm/exynos5.dtsi
===================================================================
--- trunk/sys/boot/fdt/dts/arm/exynos5.dtsi (rev 0)
+++ trunk/sys/boot/fdt/dts/arm/exynos5.dtsi 2018-06-02 12:34:49 UTC (rev 10205)
@@ -0,0 +1,285 @@
+/* $MidnightBSD$ */
+/*-
+ * Copyright (c) 2013-2014 Ruslan Bukin <br at bsdpad.com>
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ * $FreeBSD: stable/10/sys/boot/fdt/dts/arm/exynos5.dtsi 278599 2015-02-11 22:35:32Z ian $
+ */
+
+/ {
+ compatible = "samsung,exynos5";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ interrupt-parent = <&GIC>;
+
+ aliases {
+ soc = &SOC;
+ serial0 = &serial0;
+ serial1 = &serial1;
+ serial2 = &serial2;
+ serial3 = &serial3;
+ clk0 = &clk0;
+ dp0 = &dp0;
+ fimd0 = &fimd0;
+ };
+
+ SOC: Exynos5 at 0 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "simple-bus";
+ ranges;
+ bus-frequency = <0>;
+
+ GIC: interrupt-controller at 10481000 {
+ compatible = "arm,gic";
+ reg = < 0x10481000 0x1000 >, /* Distributor Registers */
+ < 0x10482000 0x2000 >; /* CPU Interface Registers */
+ interrupt-controller;
+ #address-cells = <0>;
+ #interrupt-cells = <1>;
+ };
+
+ combiner: interrupt-controller at 10440000 {
+ compatible = "exynos,combiner";
+ reg = <0x10440000 0x1000>;
+ interrupts = < 32 33 34 35 36 37 38 39
+ 40 41 42 43 44 45 46 47
+ 48 49 50 51 52 53 54 55
+ 56 57 58 59 60 61 62 63 >;
+ interrupt-parent = <&GIC>;
+ };
+
+ clk0: clk at 10010000 {
+ compatible = "exynos,clk";
+ reg = < 0x10020000 0x20000 >;
+ };
+
+ mct {
+ compatible = "exynos,mct";
+ reg = < 0x101C0000 0x1000 >;
+ clock-frequency = <24000000>;
+ };
+
+ generic_timer {
+ compatible = "arm,armv7-timer";
+ clock-frequency = <24000000>;
+ interrupts = < 29 30 27 26 >;
+ interrupt-parent = <&GIC>;
+ };
+
+ pwm {
+ compatible = "samsung,s3c24x0-timer";
+ reg = <0x12DD0000 0x1000>;
+ interrupts = < 71 >;
+ interrupt-parent = <&GIC>;
+ clock-frequency = <24000000>;
+ };
+
+ pad0: pad at 11400000 {
+ compatible = "exynos,pad";
+ status = "disabled";
+ reg = <0x11400000 0x1000>, /* gpio left */
+ <0x13400000 0x1000>, /* gpio right */
+ <0x10D10000 0x1000>, /* gpio c2c */
+ <0x03860000 0x1000>;
+ interrupts = < 78 77 82 79 >;
+ interrupt-parent = <&GIC>;
+ };
+
+ usb at 12110000 {
+ compatible = "exynos,usb-ehci", "usb-ehci";
+ reg = <0x12110000 0x1000>, /* EHCI */
+ <0x12130000 0x1000>, /* EHCI host ctrl */
+ <0x10040000 0x1000>, /* Power */
+ <0x10050230 0x10>; /* Sysreg */
+ interrupts = < 103 >;
+ interrupt-parent = <&GIC>;
+ };
+
+ usb at 12120000 {
+ compatible = "exynos,usb-ohci", "usb-ohci";
+ status = "disabled";
+ reg = <0x12120000 0x10000>;
+ interrupts = < 103 >;
+ interrupt-parent = <&GIC>;
+ };
+
+ sdhci at 12200000 {
+ compatible = "sdhci_generic";
+ status = "disabled";
+ reg = <0x12200000 0x1000>;
+ interrupts = <107>;
+ interrupt-parent = <&GIC>;
+ max-frequency = <24000000>; /* TODO: verify freq */
+ };
+
+ sdhci at 12210000 {
+ compatible = "sdhci_generic";
+ status = "disabled";
+ reg = <0x12210000 0x1000>;
+ interrupts = <108>;
+ interrupt-parent = <&GIC>;
+ max-frequency = <24000000>;
+ };
+
+ sdhci at 12220000 {
+ compatible = "sdhci_generic";
+ status = "disabled";
+ reg = <0x12220000 0x1000>;
+ interrupts = <109>;
+ interrupt-parent = <&GIC>;
+ max-frequency = <24000000>;
+ };
+
+ sdhci at 12230000 {
+ compatible = "sdhci_generic";
+ status = "disabled";
+ reg = <0x12230000 0x1000>;
+ interrupts = <110>;
+ interrupt-parent = <&GIC>;
+ max-frequency = <24000000>;
+ };
+
+ serial0: serial at 12C00000 {
+ compatible = "exynos";
+ status = "disabled";
+ reg = <0x12C00000 0x100>;
+ interrupts = < 83 >;
+ interrupt-parent = <&GIC>;
+ clock-frequency = < 100000000 >;
+ current-speed = <115200>;
+ };
+
+ serial1: serial at 12C10000 {
+ compatible = "exynos";
+ status = "disabled";
+ reg = <0x12C10000 0x100>;
+ interrupts = < 84 >;
+ interrupt-parent = <&GIC>;
+ clock-frequency = < 100000000 >;
+ current-speed = <115200>;
+ };
+
+ serial2: serial at 12C20000 {
+ compatible = "exynos";
+ status = "disabled";
+ reg = <0x12C20000 0x100>;
+ interrupts = < 85 >;
+ interrupt-parent = <&GIC>;
+ clock-frequency = < 100000000 >;
+ current-speed = <115200>;
+ };
+
+ serial3: serial at 12C30000 {
+ compatible = "exynos";
+ status = "disabled";
+ reg = <0x12C30000 0x100>;
+ interrupts = < 86 >;
+ interrupt-parent = <&GIC>;
+ clock-frequency = < 100000000 >;
+ current-speed = <115200>;
+ };
+
+ i2c0: i2c at 12C60000 {
+ compatible = "exynos,i2c";
+ status = "disabled";
+ reg = <0x12C60000 0x10000>;
+ interrupts = < 88 >;
+ interrupt-parent = <&GIC>;
+ };
+
+ i2c1: i2c at 12C70000 {
+ compatible = "exynos,i2c";
+ status = "disabled";
+ reg = <0x12C70000 0x10000>;
+ interrupts = < 89 >;
+ interrupt-parent = <&GIC>;
+ };
+
+ i2c2: i2c at 12C80000 {
+ compatible = "exynos,i2c";
+ status = "disabled";
+ reg = <0x12C80000 0x10000>;
+ interrupts = < 90 >;
+ interrupt-parent = <&GIC>;
+ };
+
+ i2c3: i2c at 12C90000 {
+ compatible = "exynos,i2c";
+ status = "disabled";
+ reg = <0x12C90000 0x10000>;
+ interrupts = < 91 >;
+ interrupt-parent = <&GIC>;
+ };
+
+ i2c4: i2c at 12CA0000 {
+ compatible = "exynos,i2c";
+ status = "disabled";
+ reg = <0x12CA0000 0x10000>;
+ interrupts = < 92 >;
+ interrupt-parent = <&GIC>;
+ };
+
+ i2c5: i2c at 12CB0000 {
+ compatible = "exynos,i2c";
+ status = "disabled";
+ reg = <0x12CB0000 0x10000>;
+ interrupts = < 93 >;
+ interrupt-parent = <&GIC>;
+ };
+
+ i2c6: i2c at 12CC0000 {
+ compatible = "exynos,i2c";
+ status = "disabled";
+ reg = <0x12CC0000 0x10000>;
+ interrupts = < 94 >;
+ interrupt-parent = <&GIC>;
+ };
+
+ i2c7: i2c at 12CD0000 {
+ compatible = "exynos,i2c";
+ status = "disabled";
+ reg = <0x12CD0000 0x10000>;
+ interrupts = < 95 >;
+ interrupt-parent = <&GIC>;
+ };
+
+ fimd0: fimd at 14400000 {
+ compatible = "exynos,fimd";
+ status = "disabled";
+ reg = < 0x14400000 0x10000 >, /* fimd */
+ < 0x14420000 0x10000 >, /* disp */
+ < 0x10050000 0x220 >; /* sysreg */
+ interrupt-parent = <&GIC>;
+ };
+
+ dp0: dp at 145B0000 {
+ compatible = "exynos,dp";
+ status = "disabled";
+ reg = < 0x145B0000 0x10000 >,
+ < 0x10040720 0x10 >; /* PHY */
+ interrupt-parent = <&GIC>;
+ };
+ };
+};
Property changes on: trunk/sys/boot/fdt/dts/arm/exynos5.dtsi
___________________________________________________________________
Added: svn:eol-style
## -0,0 +1 ##
+native
\ No newline at end of property
Added: svn:keywords
## -0,0 +1 ##
+MidnightBSD=%H
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+text/plain
\ No newline at end of property
Added: trunk/sys/boot/fdt/dts/arm/exynos5250-arndale.dts
===================================================================
--- trunk/sys/boot/fdt/dts/arm/exynos5250-arndale.dts (rev 0)
+++ trunk/sys/boot/fdt/dts/arm/exynos5250-arndale.dts 2018-06-02 12:34:49 UTC (rev 10205)
@@ -0,0 +1,58 @@
+/* $MidnightBSD$ */
+/*-
+ * Copyright (c) 2013 Ruslan Bukin <br at bsdpad.com>
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ * $FreeBSD: stable/10/sys/boot/fdt/dts/arm/exynos5250-arndale.dts 278599 2015-02-11 22:35:32Z ian $
+ */
+
+/dts-v1/;
+
+/include/ "exynos5250.dtsi"
+
+/ {
+ model = "Arndale Board";
+
+ memory {
+ device_type = "memory";
+ reg = < 0x40000000 0x80000000 >; /* 2G */
+ };
+
+ SOC: Exynos5 at 0 {
+
+ pad0: pad at 11400000 {
+ status = "okay";
+ };
+
+ serial2: serial at 12C20000 {
+ status = "okay";
+ };
+
+ };
+
+ chosen {
+ stdin = &serial2;
+ stdout = &serial2;
+ };
+};
Property changes on: trunk/sys/boot/fdt/dts/arm/exynos5250-arndale.dts
___________________________________________________________________
Added: svn:eol-style
## -0,0 +1 ##
+native
\ No newline at end of property
Added: svn:keywords
## -0,0 +1 ##
+MidnightBSD=%H
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+text/plain
\ No newline at end of property
Added: trunk/sys/boot/fdt/dts/arm/exynos5250-chromebook.dts
===================================================================
--- trunk/sys/boot/fdt/dts/arm/exynos5250-chromebook.dts (rev 0)
+++ trunk/sys/boot/fdt/dts/arm/exynos5250-chromebook.dts 2018-06-02 12:34:49 UTC (rev 10205)
@@ -0,0 +1,73 @@
+/* $MidnightBSD$ */
+/*-
+ * Copyright (c) 2014 Ruslan Bukin <br at bsdpad.com>
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ * $FreeBSD: stable/10/sys/boot/fdt/dts/arm/exynos5250-chromebook.dts 266341 2014-05-17 19:37:04Z ian $
+ */
+
+/dts-v1/;
+
+/include/ "exynos5250.dtsi"
+
+/ {
+ model = "Samsung Chromebook";
+
+ memory {
+ device_type = "memory";
+ reg = < 0x40000000 0x80000000 >; /* 2G */
+ };
+
+ SOC: Exynos5 at 0 {
+
+ pad0: pad at 11400000 {
+ status = "okay";
+ };
+
+ fimd0: fimd at 14400000 {
+ status = "okay";
+
+ panel-size = < 1366 768 >;
+ panel-hsync = < 80 32 48 >;
+ panel-vsync = < 14 5 3 >;
+ panel-clk-div = < 17 >;
+ panel-backlight-pin = < 25 >;
+ };
+
+ i2c4: i2c at 12CA0000 {
+ status = "okay";
+ };
+
+ keyboard-controller {
+ compatible = "google,cros-ec-keyb";
+ keypad,num-rows = <8>;
+ keypad,num-columns = <13>;
+ };
+ };
+
+ chosen {
+ stdin = &serial2;
+ stdout = &serial2;
+ };
+};
Property changes on: trunk/sys/boot/fdt/dts/arm/exynos5250-chromebook.dts
___________________________________________________________________
Added: svn:eol-style
## -0,0 +1 ##
+native
\ No newline at end of property
Added: svn:keywords
## -0,0 +1 ##
+MidnightBSD=%H
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+text/plain
\ No newline at end of property
Added: trunk/sys/boot/fdt/dts/arm/exynos5250.dtsi
===================================================================
--- trunk/sys/boot/fdt/dts/arm/exynos5250.dtsi (rev 0)
+++ trunk/sys/boot/fdt/dts/arm/exynos5250.dtsi 2018-06-02 12:34:49 UTC (rev 10205)
@@ -0,0 +1,53 @@
+/* $MidnightBSD$ */
+/*-
+ * Copyright (c) 2013-2014 Ruslan Bukin <br at bsdpad.com>
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ * $FreeBSD: stable/10/sys/boot/fdt/dts/arm/exynos5250.dtsi 278599 2015-02-11 22:35:32Z ian $
+ */
+
+/include/ "exynos5.dtsi"
+
+/ {
+ compatible = "samsung,exynos5250", "samsung,exynos5";
+
+ SOC: Exynos5 at 0 {
+
+ serial0: serial at 12C00000 {
+ clock-frequency = < 100000000 >;
+ };
+
+ serial1: serial at 12C10000 {
+ clock-frequency = < 100000000 >;
+ };
+
+ serial2: serial at 12C20000 {
+ clock-frequency = < 100000000 >;
+ };
+
+ serial3: serial at 12C30000 {
+ clock-frequency = < 100000000 >;
+ };
+ };
+};
Property changes on: trunk/sys/boot/fdt/dts/arm/exynos5250.dtsi
___________________________________________________________________
Added: svn:eol-style
## -0,0 +1 ##
+native
\ No newline at end of property
Added: svn:keywords
## -0,0 +1 ##
+MidnightBSD=%H
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+text/plain
\ No newline at end of property
Added: trunk/sys/boot/fdt/dts/arm/exynos5420-arndale-octa.dts
===================================================================
--- trunk/sys/boot/fdt/dts/arm/exynos5420-arndale-octa.dts (rev 0)
+++ trunk/sys/boot/fdt/dts/arm/exynos5420-arndale-octa.dts 2018-06-02 12:34:49 UTC (rev 10205)
@@ -0,0 +1,52 @@
+/* $MidnightBSD$ */
+/*-
+ * Copyright (c) 2014 Ruslan Bukin <br at bsdpad.com>
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ * $FreeBSD: stable/10/sys/boot/fdt/dts/arm/exynos5420-arndale-octa.dts 278599 2015-02-11 22:35:32Z ian $
+ */
+
+/dts-v1/;
+
+/include/ "exynos5420.dtsi"
+
+/ {
+ model = "Arndale Octa Board";
+
+ memory {
+ device_type = "memory";
+ reg = < 0x20000000 0x40000000 >; /* 1G */
+ };
+
+ SOC: Exynos5 at 0 {
+ serial3: serial at 12C30000 {
+ status = "okay";
+ };
+ };
+
+ chosen {
+ stdin = &serial3;
+ stdout = &serial3;
+ };
+};
Property changes on: trunk/sys/boot/fdt/dts/arm/exynos5420-arndale-octa.dts
___________________________________________________________________
Added: svn:eol-style
## -0,0 +1 ##
+native
\ No newline at end of property
Added: svn:keywords
## -0,0 +1 ##
+MidnightBSD=%H
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+text/plain
\ No newline at end of property
Added: trunk/sys/boot/fdt/dts/arm/exynos5420.dtsi
===================================================================
--- trunk/sys/boot/fdt/dts/arm/exynos5420.dtsi (rev 0)
+++ trunk/sys/boot/fdt/dts/arm/exynos5420.dtsi 2018-06-02 12:34:49 UTC (rev 10205)
@@ -0,0 +1,53 @@
+/* $MidnightBSD$ */
+/*-
+ * Copyright (c) 2014 Ruslan Bukin <br at bsdpad.com>
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ * $FreeBSD: stable/10/sys/boot/fdt/dts/arm/exynos5420.dtsi 278599 2015-02-11 22:35:32Z ian $
+ */
+
+/include/ "exynos5.dtsi"
+
+/ {
+ compatible = "samsung,exynos5420", "samsung,exynos5";
+
+ SOC: Exynos5 at 0 {
+
+ serial0: serial at 12C00000 {
+ clock-frequency = < 50000000 >;
+ };
+
+ serial1: serial at 12C10000 {
+ clock-frequency = < 50000000 >;
+ };
+
+ serial2: serial at 12C20000 {
+ clock-frequency = < 50000000 >;
+ };
+
+ serial3: serial at 12C30000 {
+ clock-frequency = < 50000000 >;
+ };
+ };
+};
Property changes on: trunk/sys/boot/fdt/dts/arm/exynos5420.dtsi
___________________________________________________________________
Added: svn:eol-style
## -0,0 +1 ##
+native
\ No newline at end of property
Added: svn:keywords
## -0,0 +1 ##
+MidnightBSD=%H
\ No newline at end of property
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## -0,0 +1 ##
+text/plain
\ No newline at end of property
Added: trunk/sys/boot/fdt/dts/arm/hl201.dts
===================================================================
--- trunk/sys/boot/fdt/dts/arm/hl201.dts (rev 0)
+++ trunk/sys/boot/fdt/dts/arm/hl201.dts 2018-06-02 12:34:49 UTC (rev 10205)
@@ -0,0 +1,45 @@
+/* $MidnightBSD$ */
+/*
+ * Hot-e HL-201 - Warner Losh public domain
+ *
+ * $FreeBSD: stable/10/sys/boot/fdt/dts/arm/hl201.dts 266277 2014-05-17 00:53:12Z ian $
+ */
+/dts-v1/;
+
+/*
+ * The following is a white lie. The HL-201 is a stripped down version of
+ * the SAM9G20EK board with a video output chip.
+ */
+#include "at91sam9g20ek_common.dtsi"
+
+/ {
+ model = "Thinlinx HL201";
+ compatible = "thinlinx,hl201", "atmel,at91sam9g20ek", "atmel,at91sam9g20", "atmel,at91sam9";
+
+ leds {
+ compatible = "gpio-leds";
+
+ ds1 {
+ label = "ds1";
+ gpios = <&pioA 9 0>;
+ linux,default-trigger = "heartbeat";
+ };
+
+ ds5 {
+ label = "ds5";
+ gpios = <&pioA 6 1>;
+ };
+ };
+
+ /* Missing: one wire serial number, video chip */
+
+ aliases {
+ dbgu = &dbgu;
+ };
+
+
+ chosen {
+ stdin = "dbgu";
+ stdout = "dbgu";
+ };
+};
Property changes on: trunk/sys/boot/fdt/dts/arm/hl201.dts
___________________________________________________________________
Added: svn:eol-style
## -0,0 +1 ##
+native
\ No newline at end of property
Added: svn:keywords
## -0,0 +1 ##
+MidnightBSD=%H
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+text/plain
\ No newline at end of property
Added: trunk/sys/boot/fdt/dts/arm/imx51x.dtsi
===================================================================
--- trunk/sys/boot/fdt/dts/arm/imx51x.dtsi (rev 0)
+++ trunk/sys/boot/fdt/dts/arm/imx51x.dtsi 2018-06-02 12:34:49 UTC (rev 10205)
@@ -0,0 +1,623 @@
+/* $MidnightBSD$ */
+/*
+ * Copyright (c) 2012 The FreeBSD Foundation
+ * All rights reserved.
+ *
+ * This software was developed by Semihalf under sponsorship from
+ * the FreeBSD Foundation.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ * Freescale i.MX515 Device Tree Source.
+ *
+ * $FreeBSD: stable/10/sys/boot/fdt/dts/arm/imx51x.dtsi 262614 2014-02-28 18:29:09Z imp $
+ */
+
+/ {
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ aliases {
+ soc = &SOC;
+ };
+
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cpu at 0 {
+ device_type = "cpu";
+ compatible = "ARM,MCIMX515";
+ reg = <0x0>;
+ d-cache-line-size = <32>;
+ i-cache-line-size = <32>;
+ d-cache-size = <0x8000>;
+ i-cache-size = <0x8000>;
+ /* TODO: describe L2 cache also */
+ timebase-frequency = <0>;
+ bus-frequency = <0>;
+ clock-frequency = <0>;
+ };
+ };
+
+ localbus at e0000000 {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ /* This reflects CPU decode windows setup. */
+ ranges;
+
+ tzic: tz-interrupt-controller at e0000000 {
+ compatible = "fsl,imx51-tzic", "fsl,tzic";
+ interrupt-controller;
+ #interrupt-cells = <1>;
+ reg = <0xe0000000 0x00004000>;
+ };
+ /*
+ * 60000000 60000FFF 4K Debug ROM
+ * 60001000 60001FFF 4K ETB
+ * 60002000 60002FFF 4K ETM
+ * 60003000 60003FFF 4K TPIU
+ * 60004000 60004FFF 4K CTI0
+ * 60005000 60005FFF 4K CTI1
+ * 60006000 60006FFF 4K CTI2
+ * 60007000 60007FFF 4K CTI3
+ * 60008000 60008FFF 4K Cortex Debug Unit
+ *
+ * E0000000 E0003FFF 0x4000 TZIC
+ */
+ };
+
+ SOC: soc at 70000000 {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ interrupt-parent = <&tzic>;
+ ranges = <0x70000000 0x70000000 0x14000000>;
+
+ aips at 70000000 { /* AIPS1 */
+ compatible = "fsl,aips-bus", "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ interrupt-parent = <&tzic>;
+ ranges;
+
+ /* Required by many devices, so better to stay first */
+ /* 73FD4000 0x4000 CCM */
+ clock at 73fd4000 {
+ compatible = "fsl,imx51-ccm";
+ /* 83F80000 0x4000 DPLLIP1 */
+ /* 83F84000 0x4000 DPLLIP2 */
+ /* 83F88000 0x4000 DPLLIP3 */
+ reg = <0x73fd4000 0x4000
+ 0x83F80000 0x4000
+ 0x83F84000 0x4000
+ 0x83F88000 0x4000>;
+ interrupt-parent = <&tzic>;
+ interrupts = <71 72>;
+ status = "disabled";
+ };
+
+ /*
+ * GPIO modules moved up - to have it attached for
+ * drivers which rely on GPIO
+ */
+ /* 73F84000 0x4000 GPIO1 */
+ gpio1: gpio at 73f84000 {
+ compatible = "fsl,imx51-gpio", "fsl,imx31-gpio";
+ reg = <0x73f84000 0x4000>;
+ interrupt-parent = <&tzic>;
+ interrupts = <50 51 42 43 44 45 46 47 48 49>;
+ /* TODO: use <> also */
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <1>;
+ };
+
+ /* 73F88000 0x4000 GPIO2 */
+ gpio2: gpio at 73f88000 {
+ compatible = "fsl,imx51-gpio", "fsl,imx31-gpio";
+ reg = <0x73f88000 0x4000>;
+ interrupt-parent = <&tzic>;
+ interrupts = <52 53>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <1>;
+ };
+
+ /* 73F8C000 0x4000 GPIO3 */
+ gpio3: gpio at 73f8c000 {
+ compatible = "fsl,imx51-gpio", "fsl,imx31-gpio";
+ reg = <0x73f8c000 0x4000>;
+ interrupt-parent = <&tzic>;
+ interrupts = <54 55>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <1>;
+ };
+
+ /* 73F90000 0x4000 GPIO4 */
+ gpio4: gpio at 73f90000 {
+ compatible = "fsl,imx51-gpio", "fsl,imx31-gpio";
+ reg = <0x73f90000 0x4000>;
+ interrupt-parent = <&tzic>;
+ interrupts = <56 57>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <1>;
+ };
+
+ spba at 70000000 {
+ compatible = "fsl,spba-bus", "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ interrupt-parent = <&tzic>;
+ ranges;
+
+ /* 70004000 0x4000 ESDHC 1 */
+ esdhc at 70004000 {
+ compatible = "fsl,imx51-esdhc";
+ reg = <0x70004000 0x4000>;
+ interrupt-parent = <&tzic>; interrupts = <1>;
+ status = "disabled";
+ };
+
+ /* 70008000 0x4000 ESDHC 2 */
+ esdhc at 70008000 {
+ compatible = "fsl,imx51-esdhc";
+ reg = <0x70008000 0x4000>;
+ interrupt-parent = <&tzic>; interrupts = <2>;
+ status = "disabled";
+ };
+
+ /* 7000C000 0x4000 UART 3 */
+ uart3: serial at 7000c000 {
+ compatible = "fsl,imx51-uart", "fsl,imx-uart";
+ reg = <0x7000c000 0x4000>;
+ interrupt-parent = <&tzic>; interrupts = <33>;
+ status = "disabled";
+ };
+
+ /* 70010000 0x4000 eCSPI1 */
+ ecspi at 70010000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "fsl,imx51-ecspi";
+ reg = <0x70010000 0x4000>;
+ interrupt-parent = <&tzic>; interrupts = <36>;
+ status = "disabled";
+ };
+
+ /* 70014000 0x4000 SSI2 irq30 */
+ SSI2: ssi at 70014000 {
+ compatible = "fsl,imx51-ssi";
+ reg = <0x70014000 0x4000>;
+ interrupt-parent = <&tzic>; interrupts = <30>;
+ status = "disabled";
+ };
+
+ /* 70020000 0x4000 ESDHC 3 */
+ esdhc at 70020000 {
+ compatible = "fsl,imx51-esdhc";
+ reg = <0x70020000 0x4000>;
+ interrupt-parent = <&tzic>; interrupts = <3>;
+ status = "disabled";
+ };
+
+ /* 70024000 0x4000 ESDHC 4 */
+ esdhc at 70024000 {
+ compatible = "fsl,imx51-esdhc";
+ reg = <0x70024000 0x4000>;
+ interrupt-parent = <&tzic>; interrupts = <4>;
+ status = "disabled";
+ };
+
+ /* 70028000 0x4000 SPDIF */
+ /* 91 SPDIF */
+
+ /* 70030000 0x4000 PATA (PORT UDMA) irq70 */
+
+ /* 70034000 0x4000 SLM */
+ /* 70038000 0x4000 HSI2C */ /* 64 HS-I2C */
+ /* 7003C000 0x4000 SPBA */
+ };
+
+ usbphy0: usbphy at 0 {
+ compatible = "usb-nop-xceiv";
+ status = "okay";
+ };
+
+ usbotg: usb at 73f80000 {
+ compatible = "fsl,imx51-usb", "fsl,imx27-usb";
+ reg = <0x73f80000 0x0200>;
+ interrupts = <18>;
+ fsl,usbmisc = <&usbmisc 0>;
+ fsl,usbphy = <&usbphy0>;
+ status = "disabled";
+ };
+
+ usbh1: usb at 73f80200 {
+ compatible = "fsl,imx51-usb", "fsl,imx27-usb";
+ reg = <0x73f80200 0x0200>;
+ interrupts = <14>;
+ fsl,usbmisc = <&usbmisc 1>;
+ status = "disabled";
+ };
+
+ usbh2: usb at 73f80400 {
+ compatible = "fsl,imx51-usb", "fsl,imx27-usb";
+ reg = <0x73f80400 0x0200>;
+ interrupts = <16>;
+ fsl,usbmisc = <&usbmisc 2>;
+ status = "disabled";
+ };
+
+ usbh3: usb at 73f80600 {
+ compatible = "fsl,imx51-usb", "fsl,imx27-usb";
+ reg = <0x73f80600 0x0200>;
+ interrupts = <17>;
+ fsl,usbmisc = <&usbmisc 3>;
+ status = "disabled";
+ };
+
+ usbmisc: usbmisc at 73f80800 {
+ #index-cells = <1>;
+ compatible = "fsl,imx51-usbmisc";
+ reg = <0x73f80800 0x200>;
+ };
+
+ /* 73F98000 0x4000 WDOG1 */
+ wdog at 73f98000 {
+ compatible = "fsl,imx51-wdt", "fsl,imx21-wdt";
+ reg = <0x73f98000 0x4000>;
+ interrupt-parent = <&tzic>; interrupts = <58>;
+ status = "disabled";
+ };
+
+ /* 73F9C000 0x4000 WDOG2 (TZ) */
+ wdog at 73f9c000 {
+ compatible = "fsl,imx51-wdt", "fsl,imx21-wdt";
+ reg = <0x73f9c000 0x4000>;
+ interrupt-parent = <&tzic>; interrupts = <59>;
+ status = "disabled";
+ };
+
+ /* 73F94000 0x4000 KPP */
+ keyboard at 73f94000 {
+ compatible = "fsl,imx51-kpp";
+ reg = <0x73f94000 0x4000>;
+ interrupt-parent = <&tzic>; interrupts = <60>;
+ status = "disabled";
+ };
+
+ /* 73FA0000 0x4000 GPT */
+ timer at 73fa0000 {
+ compatible = "fsl,imx51-gpt";
+ reg = <0x73fa0000 0x4000>;
+ interrupt-parent = <&tzic>; interrupts = <39>;
+ status = "disabled";
+ };
+
+ /* 73FA4000 0x4000 SRTC */
+
+ rtc at 73fa4000 {
+ compatible = "fsl,imx51-srtc";
+ reg = <0x73fa4000 0x4000>;
+ interrupt-parent = <&tzic>; interrupts = <24 25>;
+ status = "disabled";
+ };
+
+ /* 73FA8000 0x4000 IOMUXC */
+ iomux at 73fa8000 {
+ compatible = "fsl,imx51-iomux";
+ reg = <0x73fa8000 0x4000>;
+ interrupt-parent = <&tzic>; interrupts = <7>;
+ };
+
+ /* 73FAC000 0x4000 EPIT1 */
+ epit1: timer at 73fac000 {
+ compatible = "fsl,imx51-epit";
+ reg = <0x73fac000 0x4000>;
+ interrupt-parent = <&tzic>; interrupts = <40>;
+ status = "disabled";
+ };
+
+ /* 73FB0000 0x4000 EPIT2 */
+ epit2: timer at 73fb0000 {
+ compatible = "fsl,imx51-epit";
+ reg = <0x73fb0000 0x4000>;
+ interrupt-parent = <&tzic>; interrupts = <41>;
+ status = "disabled";
+ };
+
+ /* 73FB4000 0x4000 PWM1 */
+ pwm at 73fb4000 {
+ compatible = "fsl,imx51-pwm";
+ reg = <0x73fb4000 0x4000>;
+ interrupt-parent = <&tzic>; interrupts = <61>;
+ status = "disabled";
+ };
+
+ /* 73FB8000 0x4000 PWM2 */
+ pwm at 73fb8000 {
+ compatible = "fsl,imx51-pwm";
+ reg = <0x73fb8000 0x4000>;
+ interrupt-parent = <&tzic>; interrupts = <94>;
+ status = "disabled";
+ };
+
+ /* 73FBC000 0x4000 UART 1 */
+ uart1: serial at 73fbc000 {
+ compatible = "fsl,imx51-uart", "fsl,imx-uart";
+ reg = <0x73fbc000 0x4000>;
+ interrupt-parent = <&tzic>; interrupts = <31>;
+ status = "disabled";
+ };
+
+ /* 73FC0000 0x4000 UART 2 */
+ uart2: serial at 73fc0000 {
+ compatible = "fsl,imx51-uart", "fsl,imx-uart";
+ reg = <0x73fc0000 0x4000>;
+ interrupt-parent = <&tzic>; interrupts = <32>;
+ status = "disabled";
+ };
+
+ /* 73FC4000 0x4000 USBOH3 */
+ /* NOTYET
+ usb at 73fc4000 {
+ compatible = "fsl,imx51-otg";
+ reg = <0x73fc4000 0x4000>;
+ interrupt-parent = <&tzic>; interrupts = <>;
+ status = "disabled";
+ };
+ */
+ /* 73FD0000 0x4000 SRC */
+ reset at 73fd0000 {
+ compatible = "fsl,imx51-src";
+ reg = <0x73fd0000 0x4000>;
+ interrupt-parent = <&tzic>; interrupts = <75>;
+ status = "disabled";
+ };
+ /* 73FD8000 0x4000 GPC */
+ power at 73fd8000 {
+ compatible = "fsl,imx51-gpc";
+ reg = <0x73fd8000 0x4000>;
+ interrupt-parent = <&tzic>; interrupts = <73 74>;
+ status = "disabled";
+ };
+
+ };
+
+ aips at 80000000 { /* AIPS2 */
+ compatible = "fsl,aips-bus", "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ interrupt-parent = <&tzic>;
+ ranges;
+
+ /* 83F94000 0x4000 AHBMAX */
+ /* 83F98000 0x4000 IIM */
+ /*
+ * 69 IIM Interrupt request to the processor.
+ * Indicates to the processor that program or
+ * explicit.
+ */
+ /* 83F9C000 0x4000 CSU */
+ /*
+ * 27 CSU Interrupt Request 1. Indicates to the
+ * processor that one or more alarm inputs were.
+ */
+
+ /* 83FA0000 0x4000 TIGERP_PLATFORM_NE_32K_256K */
+ /* irq76 Neon Monitor Interrupt */
+ /* irq77 Performance Unit Interrupt */
+ /* irq78 CTI IRQ */
+ /* irq79 Debug Interrupt, Cross-Trigger Interface 1 */
+ /* irq80 Debug Interrupt, Cross-Trigger Interface 1 */
+ /* irq89 Debug Interrupt, Cross-Trigger Interface 2 */
+ /* irq98 Debug Interrupt, Cross-Trigger Interface 3 */
+
+ /* 83FA4000 0x4000 OWIRE irq88 */
+ /* 83FA8000 0x4000 FIRI irq93 */
+ /* 83FAC000 0x4000 eCSPI2 */
+ ecspi at 83fac000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "fsl,imx51-ecspi";
+ reg = <0x83fac000 0x4000>;
+ interrupt-parent = <&tzic>; interrupts = <37>;
+ status = "disabled";
+ };
+
+ /* 83FB0000 0x4000 SDMA */
+ sdma at 83fb0000 {
+ compatible = "fsl,imx51-sdma", "fsl,imx35-sdma";
+ reg = <0x83fb0000 0x4000>;
+ interrupt-parent = <&tzic>; interrupts = <6>;
+ };
+
+ /* 83FB4000 0x4000 SCC */
+ /* 21 SCC Security Monitor High Priority Interrupt. */
+ /* 22 SCC Secure (TrustZone) Interrupt. */
+ /* 23 SCC Regular (Non-Secure) Interrupt. */
+
+ /* 83FB8000 0x4000 ROMCP */
+ /* 83FBC000 0x4000 RTIC */
+ /*
+ * 26 RTIC RTIC (Trust Zone) Interrupt Request.
+ * Indicates that the RTIC has completed hashing the
+ */
+
+ /* 83FC0000 0x4000 CSPI */
+ cspi at 83fc0000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "fsl,imx51-cspi", "fsl,imx35-cspi";
+ reg = <0x83fc0000 0x4000>;
+ interrupt-parent = <&tzic>; interrupts = <38>;
+ status = "disabled";
+ };
+
+ /* 83FC4000 0x4000 I2C2 */
+ i2c at 83fc4000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "fsl,imx51-i2c", "fsl,imx1-i2c", "fsl,imx-i2c";
+ reg = <0x83fc4000 0x4000>;
+ interrupt-parent = <&tzic>; interrupts = <63>;
+ status = "disabled";
+ };
+
+ /* 83FC8000 0x4000 I2C1 */
+ i2c at 83fc8000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "fsl,imx51-i2c", "fsl,imx1-i2c", "fsl,imx-i2c";
+ reg = <0x83fc8000 0x4000>;
+ interrupt-parent = <&tzic>; interrupts = <62>;
+ status = "disabled";
+ };
+
+ /* 83FCC000 0x4000 SSI1 */
+ /* 29 SSI1 SSI-1 Interrupt Request */
+ SSI1: ssi at 83fcc000 {
+ compatible = "fsl,imx51-ssi";
+ reg = <0x83fcc000 0x4000>;
+ interrupt-parent = <&tzic>; interrupts = <29>;
+ status = "disabled";
+ };
+
+ /* 83FD0000 0x4000 AUDMUX */
+ audmux at 83fd4000 {
+ compatible = "fsl,imx51-audmux";
+ reg = <0x83fd4000 0x4000>;
+ status = "disabled";
+ };
+
+ /* 83FD8000 0x4000 EMI1 */
+ /* 8 EMI (NFC) */
+ /* 15 EMI */
+ /* 97 EMI Boot sequence completed interrupt */
+ /*
+ * 101 EMI Indicates all pages have been transferred
+ * to NFC during an auto program operation.
+ */
+
+ /* 83FE0000 0x4000 PATA (PORT PIO) */
+ /* 70 PATA Parallel ATA host controller interrupt */
+ ide at 83fe0000 {
+ compatible = "fsl,imx51-ata";
+ reg = <0x83fe0000 0x4000>;
+ interrupt-parent = <&tzic>;
+ interrupts = <70>;
+ status = "disabled";
+ };
+
+ /* 83FE4000 0x4000 SIM */
+ /* 67 SIM intr composed of oef, xte, sdi1, and sdi0 */
+ /* 68 SIM intr composed of tc, etc, tfe, and rdrf */
+
+ /* 83FE8000 0x4000 SSI3 */
+ /* 96 SSI3 SSI-3 Interrupt Request */
+ SSI3: ssi at 83fe8000 {
+ compatible = "fsl,imx51-ssi";
+ reg = <0x83fe8000 0x4000>;
+ interrupt-parent = <&tzic>; interrupts = <96>;
+ status = "disabled";
+ };
+
+ /* 83FEC000 0x4000 FEC */
+ ethernet at 83fec000 {
+ compatible = "fsl,imx51-fec";
+ reg = <0x83fec000 0x4000>;
+ interrupt-parent = <&tzic>; interrupts = <87>;
+ status = "disabled";
+ };
+
+ /* 83FF0000 0x4000 TVE */
+ /* 92 TVE */
+ /* 83FF4000 0x4000 VPU */
+ /* 9 VPU */
+ /* 100 VPU Idle interrupt from VPU */
+
+ /* 83FF8000 0x4000 SAHARA Lite */
+ /* 19 SAHARA SAHARA host 0 (TrustZone) Intr Lite */
+ /* 20 SAHARA SAHARA host 1 (non-TrustZone) Intr Lite */
+ };
+ };
+
+ localbus at 5e000000 {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ ranges;
+
+ vga: ipu3 at 5e000000 {
+ compatible = "fsl,ipu3";
+ reg = <
+ 0x5e000000 0x08000 /* CM */
+ 0x5e008000 0x08000 /* IDMAC */
+ 0x5e018000 0x08000 /* DP */
+ 0x5e020000 0x08000 /* IC */
+ 0x5e028000 0x08000 /* IRT */
+ 0x5e030000 0x08000 /* CSI0 */
+ 0x5e038000 0x08000 /* CSI1 */
+ 0x5e040000 0x08000 /* DI0 */
+ 0x5e048000 0x08000 /* DI1 */
+ 0x5e050000 0x08000 /* SMFC */
+ 0x5e058000 0x08000 /* DC */
+ 0x5e060000 0x08000 /* DMFC */
+ 0x5e068000 0x08000 /* VDI */
+ 0x5f000000 0x20000 /* CPMEM */
+ 0x5f020000 0x20000 /* LUT */
+ 0x5f040000 0x20000 /* SRM */
+ 0x5f060000 0x20000 /* TPM */
+ 0x5f080000 0x20000 /* DCTMPL */
+ >;
+ interrupt-parent = <&tzic>;
+ interrupts = <
+ 10 /* IPUEX Error */
+ 11 /* IPUEX Sync */
+ >;
+ status = "disabled";
+ };
+ };
+};
+
+/*
+
+TODO: Not mapped interrupts
+
+5 DAP
+84 GPU2D (OpenVG) general interrupt
+85 GPU2D (OpenVG) busy signal (for S/W power gating feasibility)
+12 GPU3D
+102 GPU3D Idle interrupt from GPU3D (for S/W power gating)
+90 SJC
+*/
Property changes on: trunk/sys/boot/fdt/dts/arm/imx51x.dtsi
___________________________________________________________________
Added: svn:eol-style
## -0,0 +1 ##
+native
\ No newline at end of property
Added: svn:keywords
## -0,0 +1 ##
+MidnightBSD=%H
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+text/plain
\ No newline at end of property
Added: trunk/sys/boot/fdt/dts/arm/imx53-qsb.dts
===================================================================
--- trunk/sys/boot/fdt/dts/arm/imx53-qsb.dts (rev 0)
+++ trunk/sys/boot/fdt/dts/arm/imx53-qsb.dts 2018-06-02 12:34:49 UTC (rev 10205)
@@ -0,0 +1,135 @@
+/* $MidnightBSD$ */
+/*
+ * Copyright (c) 2012 The FreeBSD Foundation
+ * Copyright (c) 2013 Rui Paulo
+ * All rights reserved.
+ *
+ * This software was developed by Semihalf under sponsorship from
+ * the FreeBSD Foundation.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ * Freescale i.MX53 Quick Start Board
+ * In u-boot, this board is known as "MX53LOCO" for some reason.
+ *
+ * $FreeBSD: stable/10/sys/boot/fdt/dts/arm/imx53-qsb.dts 266365 2014-05-17 22:00:10Z ian $
+ */
+
+/dts-v1/;
+/include/ "imx53x.dtsi"
+
+/ {
+ model = "Freescale i.MX53 Quick Start Board";
+ compatible = "fsl,imx53-qsb", "fsl,imx53";
+
+ memory {
+ /* RAM is 2 banks of 512M each. */
+ reg = <0x70000000 0x20000000
+ 0xb0000000 0x20000000>;
+ };
+
+ localbus at 18000000 {
+ ipu3 at 1E000000 {
+ status = "okay";
+ };
+ };
+
+ soc at 50000000 {
+ aips at 50000000 {
+ spba at 50000000 {
+ esdhc at 50004000 {
+ clock-frequency = <216000000>;
+ status = "okay";
+ };
+ esdhc at 50008000 {
+ clock-frequency = <216000000>;
+ status = "okay";
+ };
+ SSI2: ssi at 50014000 {
+ status = "okay";
+ };
+ };
+ timer at 53fa0000 {
+ status = "okay";
+ };
+
+ /* UART1, console */
+ console: serial at 53fbc000 {
+ status = "okay";
+ clock-frequency = <0>; /* won't load w/o this */
+ };
+
+ clock at 53fd4000 {
+ status = "okay";
+ };
+ gpio at 53f84000 {
+ status = "okay";
+ };
+ gpio at 53f88000 {
+ status = "okay";
+ };
+ gpio at 53f8c000 {
+ status = "okay";
+ };
+ gpio at 53f90000 {
+ status = "okay";
+ };
+ usb at 53f80000 /* OTG */ {
+ status = "okay";
+ };
+ usb at 53f80200 /* Host 1 */ {
+ status = "okay";
+ };
+ wdog at 53f98000 {
+ status = "okay";
+ };
+ };
+ aips at 60000000 {
+ ethernet at 63fec000 {
+ status = "okay";
+ phy-mode = "rmii";
+ };
+ i2c at 63fc4000 {
+ status = "okay";
+ };
+ i2c at 63fc8000 {
+ status = "okay";
+ };
+ audmux at 63fd4000 {
+ status = "okay";
+ };
+ ide at 63fe0000 {
+ status = "okay";
+ };
+ };
+ };
+
+ aliases {
+ SSI2 = &SSI2;
+ };
+
+ chosen {
+ bootargs = "-v";
+ stdin = &console;
+ stdout = &console;
+ };
+};
Property changes on: trunk/sys/boot/fdt/dts/arm/imx53-qsb.dts
___________________________________________________________________
Added: svn:eol-style
## -0,0 +1 ##
+native
\ No newline at end of property
Added: svn:keywords
## -0,0 +1 ##
+MidnightBSD=%H
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+text/plain
\ No newline at end of property
Added: trunk/sys/boot/fdt/dts/arm/imx53x.dtsi
===================================================================
--- trunk/sys/boot/fdt/dts/arm/imx53x.dtsi (rev 0)
+++ trunk/sys/boot/fdt/dts/arm/imx53x.dtsi 2018-06-02 12:34:49 UTC (rev 10205)
@@ -0,0 +1,715 @@
+/* $MidnightBSD$ */
+/*
+ * Copyright (c) 2012 The FreeBSD Foundation
+ * Copyright (c) 2013 Rui Paulo
+ * All rights reserved.
+ *
+ * This software was developed by Semihalf under sponsorship from
+ * the FreeBSD Foundation.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ * Freescale i.MX535 Device Tree Source.
+ *
+ * $FreeBSD: stable/10/sys/boot/fdt/dts/arm/imx53x.dtsi 266367 2014-05-17 22:02:26Z ian $
+ */
+
+/ {
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ aliases {
+ soc = &SOC;
+ };
+
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cpu at 0 {
+ device_type = "cpu";
+ compatible = "ARM,MCIMX535";
+ reg = <0x0>;
+ d-cache-line-size = <32>;
+ i-cache-line-size = <32>;
+ d-cache-size = <0x8000>;
+ i-cache-size = <0x8000>;
+ l2-cache-line-size = <32>;
+ l2-cache-line = <0x40000>;
+ timebase-frequency = <0>;
+ bus-frequency = <0>;
+ clock-frequency = <0>;
+ };
+ };
+
+ localbus at 0fffc000 {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ /* This reflects CPU decode windows setup. */
+ ranges;
+
+ tzic: tz-interrupt-controller at 0fffc000 {
+ compatible = "fsl,imx53-tzic", "fsl,tzic";
+ interrupt-controller;
+ #interrupt-cells = <1>;
+ reg = <0x0fffc000 0x00004000>;
+ };
+ /*
+ * 40000000 40000FFF 4K Debug ROM
+ * 40001000 40001FFF 4K ETB
+ * 40002000 40002FFF 4K ETM
+ * 40003000 40003FFF 4K TPIU
+ * 40004000 40004FFF 4K CTI0
+ * 40005000 40005FFF 4K CTI1
+ * 40006000 40006FFF 4K CTI2
+ * 40007000 40007FFF 4K CTI3
+ * 40008000 40008FFF 4K ARM Debug Unit
+ *
+ * 0FFFC000 0FFFCFFF 0x4000 TZIC
+ */
+ };
+
+ SOC: soc at 50000000 {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ interrupt-parent = <&tzic>;
+ ranges;
+
+ aips at 50000000 { /* AIPS1 */
+ compatible = "fsl,aips-bus", "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ interrupt-parent = <&tzic>;
+ ranges;
+
+ /* Required by many devices, so better to stay first */
+ /* 53FD4000 0x4000 CCM */
+ clock at 53fd4000 {
+ compatible = "fsl,imx53-ccm";
+ /* 63F80000 0x4000 DPLLIP1 */
+ /* 63F84000 0x4000 DPLLIP2 */
+ /* 63F88000 0x4000 DPLLIP3 */
+ reg = <0x53fd4000 0x4000
+ 0x63F80000 0x4000
+ 0x63F84000 0x4000
+ 0x63F88000 0x4000>;
+ interrupt-parent = <&tzic>;
+ interrupts = <71 72>;
+ status = "disabled";
+ };
+
+ /*
+ * GPIO modules moved up - to have it attached for
+ * drivers which rely on GPIO
+ */
+ /* 53F84000 0x4000 GPIO1 */
+ gpio1: gpio at 53f84000 {
+ compatible = "fsl,imx53-gpio";
+ reg = <0x53f84000 0x4000>;
+ interrupt-parent = <&tzic>;
+ interrupts = <50 51 42 43 44 45 46 47 48 49>;
+ /* TODO: use <> also */
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <1>;
+ };
+
+ /* 53F88000 0x4000 GPIO2 */
+ gpio2: gpio at 53f88000 {
+ compatible = "fsl,imx53-gpio";
+ reg = <0x53f88000 0x4000>;
+ interrupt-parent = <&tzic>;
+ interrupts = <52 53>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <1>;
+ };
+
+ /* 53F8C000 0x4000 GPIO3 */
+ gpio3: gpio at 53f8c000 {
+ compatible = "fsl,imx53-gpio";
+ reg = <0x53f8c000 0x4000>;
+ interrupt-parent = <&tzic>;
+ interrupts = <54 55>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <1>;
+ };
+
+ /* 53F90000 0x4000 GPIO4 */
+ gpio4: gpio at 53f90000 {
+ compatible = "fsl,imx53-gpio";
+ reg = <0x53f90000 0x4000>;
+ interrupt-parent = <&tzic>;
+ interrupts = <56 57>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <1>;
+ };
+
+ /* 53FDC000 0x4000 GPIO5 */
+ gpio5: gpio at 53fdc000 {
+ compatible = "fsl,imx53-gpio";
+ reg = <0x53fdc000 0x4000>;
+ interrupt-parent = <&tzic>;
+ interrupts = <103 104>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <1>;
+ };
+
+ /* 53FE0000 0x4000 GPIO6 */
+ gpio6: gpio at 53fe0000 {
+ compatible = "fsl,imx53-gpio";
+ reg = <0x53fe0000 0x4000>;
+ interrupt-parent = <&tzic>;
+ interrupts = <105 106>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <1>;
+ };
+
+ /* 53FE4000 0x4000 GPIO5 */
+ gpio7: gpio at 53fe4000 {
+ compatible = "fsl,imx53-gpio";
+ reg = <0x53fe4000 0x4000>;
+ interrupt-parent = <&tzic>;
+ interrupts = <107 108>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <1>;
+ };
+
+ spba at 50000000 {
+ compatible = "fsl,spba-bus", "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ interrupt-parent = <&tzic>;
+ ranges;
+
+ /* 50004000 0x4000 ESDHC 1 */
+ esdhc at 50004000 {
+ compatible = "fsl,imx53-esdhc";
+ reg = <0x50004000 0x4000>;
+ interrupt-parent = <&tzic>; interrupts = <1>;
+ status = "disabled";
+ };
+
+ /* 50008000 0x4000 ESDHC 2 */
+ esdhc at 50008000 {
+ compatible = "fsl,imx53-esdhc";
+ reg = <0x50008000 0x4000>;
+ interrupt-parent = <&tzic>; interrupts = <2>;
+ status = "disabled";
+ };
+
+ /* 5000C000 0x4000 UART 3 */
+ uart3: serial at 5000c000 {
+ compatible = "fsl,imx53-uart", "fsl,imx-uart";
+ reg = <0x5000c000 0x4000>;
+ interrupt-parent = <&tzic>;
+ interrupts = <33>;
+ status = "disabled";
+ };
+
+ /* 50010000 0x4000 eCSPI1 */
+ ecspi at 50010000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "fsl,imx53-ecspi";
+ reg = <0x50010000 0x4000>;
+ interrupt-parent = <&tzic>;
+ interrupts = <36>;
+ status = "disabled";
+ };
+
+ /* 50014000 0x4000 SSI2 irq30 */
+ SSI2: ssi at 50014000 {
+ compatible = "fsl,imx53-ssi";
+ reg = <0x50014000 0x4000>;
+ interrupt-parent = <&tzic>;
+ interrupts = <30>;
+ status = "disabled";
+ };
+
+ /* 50020000 0x4000 ESDHC 3 */
+ esdhc at 50020000 {
+ compatible = "fsl,imx53-esdhc";
+ reg = <0x50020000 0x4000>;
+ interrupt-parent = <&tzic>;
+ interrupts = <3>;
+ status = "disabled";
+ };
+
+ /* 50024000 0x4000 ESDHC 4 */
+ esdhc at 50024000 {
+ compatible = "fsl,imx53-esdhc";
+ reg = <0x50024000 0x4000>;
+ interrupt-parent = <&tzic>;
+ interrupts = <4>;
+ status = "disabled";
+ };
+
+ /* 50028000 0x4000 SPDIF */
+ /* 91 SPDIF */
+
+ pata at 50030000 {
+ compatible = "fsl,imx53-ata";
+ reg = <0x50030000 0x4000>;
+ interrupt-parent = <&tzic>;
+ interrupts = <70>;
+ status = "disabled";
+ };
+
+ /* 50034000 0x4000 SLM */
+ /* 50038000 0x4000 HSI2C */
+ /* 64 HS-I2C */
+ /* 5003C000 0x4000 SPBA */
+ };
+
+ usbphy0: usbphy at 0 {
+ compatible = "usb-nop-xceiv";
+ status = "okay";
+ };
+
+ usbphy1: usbphy at 1 {
+ compatible = "usb-nop-xceiv";
+ status = "okay";
+ };
+
+ usbotg: usb at 53f80000 {
+ compatible = "fsl,imx53-usb", "fsl,imx27-usb";
+ reg = <0x53f80000 0x0200>;
+ interrupts = <18>;
+ fsl,usbphy = <&usbphy0>;
+ status = "disabled";
+ };
+
+ usbh1: usb at 53f80200 {
+ compatible = "fsl,imx53-usb", "fsl,imx27-usb";
+ reg = <0x53f80200 0x0200>;
+ interrupts = <14>;
+ fsl,usbphy = <&usbphy1>;
+ status = "disabled";
+ };
+
+ usbh2: usb at 53f80400 {
+ compatible = "fsl,imx53-usb", "fsl,imx27-usb";
+ reg = <0x53f80400 0x0200>;
+ interrupts = <16>;
+ status = "disabled";
+ };
+
+ usbh3: usb at 53f80600 {
+ compatible = "fsl,imx53-usb", "fsl,imx27-usb";
+ reg = <0x53f80600 0x0200>;
+ interrupts = <17>;
+ status = "disabled";
+ };
+
+ usbmisc: usbmisc at 53f80800 {
+ #index-cells = <1>;
+ compatible = "fsl,imx53-usbmisc";
+ reg = <0x53f80800 0x200>;
+ };
+
+ /* 53F98000 0x4000 WDOG1 */
+ wdog at 53f98000 {
+ compatible = "fsl,imx53-wdt";
+ reg = <0x53f98000 0x4000>;
+ interrupt-parent = <&tzic>;
+ interrupts = <58>;
+ status = "disabled";
+ };
+
+ /* 53F9C000 0x4000 WDOG2 (TZ) */
+ wdog at 53f9c000 {
+ compatible = "fsl,imx53-wdt";
+ reg = <0x53f9c000 0x4000>;
+ interrupt-parent = <&tzic>;
+ interrupts = <59>;
+ status = "disabled";
+ };
+
+ /* 53F94000 0x4000 KPP */
+ keyboard at 53f94000 {
+ compatible = "fsl,imx53-kpp";
+ reg = <0x53f94000 0x4000>;
+ interrupt-parent = <&tzic>;
+ interrupts = <60>;
+ status = "disabled";
+ };
+
+ /* 53FA0000 0x4000 GPT */
+ timer at 53fa0000 {
+ compatible = "fsl,imx53-gpt";
+ reg = <0x53fa0000 0x4000>;
+ interrupt-parent = <&tzic>;
+ interrupts = <39>;
+ status = "disabled";
+ };
+
+ /* 53FA4000 0x4000 SRTC */
+
+ rtc at 53fa4000 {
+ compatible = "fsl,imx53-srtc";
+ reg = <0x53fa4000 0x4000>;
+ interrupt-parent = <&tzic>;
+ interrupts = <24 25>;
+ status = "disabled";
+ };
+
+ /* 53FA8000 0x4000 IOMUXC */
+ iomux at 53fa8000 {
+ compatible = "fsl,imx53-iomux";
+ reg = <0x53fa8000 0x4000>;
+ interrupt-parent = <&tzic>;
+ interrupts = <7>;
+ };
+
+ /* 53FAC000 0x4000 EPIT1 */
+ epit1: timer at 53fac000 {
+ compatible = "fsl,imx53-epit";
+ reg = <0x53fac000 0x4000>;
+ interrupt-parent = <&tzic>;
+ interrupts = <40>;
+ status = "disabled";
+ };
+
+ /* 53FB0000 0x4000 EPIT2 */
+ epit2: timer at 53fb0000 {
+ compatible = "fsl,imx53-epit";
+ reg = <0x53fb0000 0x4000>;
+ interrupt-parent = <&tzic>;
+ interrupts = <41>;
+ status = "disabled";
+ };
+
+ /* 53FB4000 0x4000 PWM1 */
+ pwm at 53fb4000 {
+ compatible = "fsl,imx53-pwm";
+ reg = <0x53fb4000 0x4000>;
+ interrupt-parent = <&tzic>;
+ interrupts = <61>;
+ status = "disabled";
+ };
+
+ /* 53FB8000 0x4000 PWM2 */
+ pwm at 53fb8000 {
+ compatible = "fsl,imx53-pwm";
+ reg = <0x53fb8000 0x4000>;
+ interrupt-parent = <&tzic>;
+ interrupts = <94>;
+ status = "disabled";
+ };
+
+ /* 53FBC000 0x4000 UART 1 */
+ uart1: serial at 53fbc000 {
+ compatible = "fsl,imx53-uart", "fsl,imx-uart";
+ reg = <0x53fbc000 0x4000>;
+ interrupt-parent = <&tzic>;
+ interrupts = <31>;
+ status = "disabled";
+ };
+
+ /* 53FC0000 0x4000 UART 2 */
+ uart2: serial at 53fc0000 {
+ compatible = "fsl,imx53-uart", "fsl,imx-uart";
+ reg = <0x53fc0000 0x4000>;
+ interrupt-parent = <&tzic>;
+ interrupts = <32>;
+ status = "disabled";
+ };
+
+ /* 53FF0000 0x4000 UART 4 */
+ uart4: serial at 53ff0000 {
+ compatible = "fsl,imx53-uart", "fsl,imx-uart";
+ reg = <0x53ff0000 0x4000>;
+ interrupt-parent = <&tzic>;
+ interrupts = <13>;
+ status = "disabled";
+ };
+
+ /* 53FD0000 0x4000 SRC */
+ reset at 53fd0000 {
+ compatible = "fsl,imx53-src";
+ reg = <0x53fd0000 0x4000>;
+ interrupt-parent = <&tzic>;
+ interrupts = <75>;
+ status = "disabled";
+ };
+ /* 53FD8000 0x4000 GPC */
+ power at 53fd8000 {
+ compatible = "fsl,imx53-gpc";
+ reg = <0x53fd8000 0x4000>;
+ interrupt-parent = <&tzic>;
+ interrupts = <73 74>;
+ status = "disabled";
+ };
+ i2c at 53fec000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "fsl,imx53-i2c", "fsl,imx1-i2c",
+ "fsl,imx-i2c";
+ reg = <0x53fec000 0x4000>;
+ interrupt-parent = <&tzic>;
+ interrupts = <64>;
+ status = "disabled";
+ };
+ };
+
+ aips at 60000000 { /* AIPS2 */
+ compatible = "fsl,aips-bus", "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ interrupt-parent = <&tzic>;
+ ranges;
+
+ /* 63F90000 0x4000 UART 5 */
+ uart5: serial at 63f90000 {
+ compatible = "fsl,imx53-uart", "fsl,imx-uart";
+ reg = <0x63f90000 0x4000>;
+ interrupt-parent = <&tzic>;
+ interrupts = <32>;
+ status = "disabled";
+ };
+
+ /* 63F94000 0x4000 AHBMAX */
+ /* 63F98000 0x4000 IIM */
+ /*
+ * 69 IIM Interrupt request to the processor.
+ * Indicates to the processor that program or
+ * explicit.
+ */
+ /* 63F9C000 0x4000 CSU */
+ /*
+ * 27 CSU Interrupt Request 1. Indicates to the
+ * processor that one or more alarm inputs were.
+ */
+
+ /* 63FA0000 0x4000 TIGERP_PLATFORM_NE_32K_256K */
+ /* irq76 Neon Monitor Interrupt */
+ /* irq77 Performance Unit Interrupt */
+ /* irq78 CTI IRQ */
+ /* irq79 Debug Interrupt, Cross-Trigger Interface 1 */
+ /* irq80 Debug Interrupt, Cross-Trigger Interface 1 */
+ /* irq89 Debug Interrupt, Cross-Trigger Interface 2 */
+ /* irq98 Debug Interrupt, Cross-Trigger Interface 3 */
+
+ /* 63FA4000 0x4000 OWIRE irq88 */
+ /* 63FA8000 0x4000 FIRI irq93 */
+ /* 63FAC000 0x4000 eCSPI2 */
+ ecspi at 63fac000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "fsl,imx53-ecspi";
+ reg = <0x63fac000 0x4000>;
+ interrupt-parent = <&tzic>;
+ interrupts = <37>;
+ status = "disabled";
+ };
+
+ /* 63FB0000 0x4000 SDMA */
+ sdma at 63fb0000 {
+ compatible = "fsl,imx53-sdma";
+ reg = <0x63fb0000 0x4000>;
+ interrupt-parent = <&tzic>;
+ interrupts = <6>;
+ };
+
+ /* 63FB4000 0x4000 SCC */
+ /* 21 SCC Security Monitor High Priority Interrupt. */
+ /* 22 SCC Secure (TrustZone) Interrupt. */
+ /* 23 SCC Regular (Non-Secure) Interrupt. */
+
+ /* 63FB8000 0x4000 ROMCP */
+ /* 63FBC000 0x4000 RTIC */
+ /*
+ * 26 RTIC RTIC (Trust Zone) Interrupt Request.
+ * Indicates that the RTIC has completed hashing the
+ */
+
+ /* 63FC0000 0x4000 CSPI */
+ cspi at 63fc0000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "fsl,imx53-cspi";
+ reg = <0x63fc0000 0x4000>;
+ interrupt-parent = <&tzic>;
+ interrupts = <38>;
+ status = "disabled";
+ };
+
+ /* 63FC4000 0x4000 I2C2 */
+ i2c at 63fc4000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "fsl,imx53-i2c", "fsl,imx1-i2c", "fsl,imx-i2c";
+ reg = <0x63fc4000 0x4000>;
+ interrupt-parent = <&tzic>;
+ interrupts = <63>;
+ status = "disabled";
+ };
+
+ /* 63FC8000 0x4000 I2C1 */
+ i2c at 63fc8000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "fsl,imx53-i2c", "fsl,imx1-i2c", "fsl,imx-i2c";
+ reg = <0x63fc8000 0x4000>;
+ interrupt-parent = <&tzic>;
+ interrupts = <62>;
+ status = "disabled";
+ };
+
+ /* 63FCC000 0x4000 SSI1 */
+ /* 29 SSI1 SSI-1 Interrupt Request */
+ SSI1: ssi at 63fcc000 {
+ compatible = "fsl,imx53-ssi";
+ reg = <0x63fcc000 0x4000>;
+ interrupt-parent = <&tzic>;
+ interrupts = <29>;
+ status = "disabled";
+ };
+
+ /* 63FD0000 0x4000 AUDMUX */
+ audmux at 63fd4000 {
+ compatible = "fsl,imx53-audmux";
+ reg = <0x63fd4000 0x4000>;
+ status = "disabled";
+ };
+
+ /* 63FD8000 0x4000 EXTMC */
+ /* 8 EXTMC (NFC) */
+ /* 15 EXTMC */
+ /* 97 EXTMC Boot sequence completed interrupt */
+ /*
+ * 101 EMI Indicates all pages have been transferred
+ * to NFC during an auto program operation.
+ */
+
+ /* 83FE4000 0x4000 SIM */
+ /* 67 SIM intr composed of oef, xte, sdi1, and sdi0 */
+ /* 68 SIM intr composed of tc, etc, tfe, and rdrf */
+
+ /* 63FD_C000 0x4000 apb2ip_pl301_2x2 */
+ /* 63FE_0000 0x4000 apb2ip_pl301_4x1 */
+ /* 63FE4000 0x4000 MLB */
+ /* 63FE8000 0x4000 SSI3 */
+ /* 96 SSI3 SSI-3 Interrupt Request */
+ SSI3: ssi at 63fe8000 {
+ compatible = "fsl,imx51-ssi";
+ reg = <0x63fe8000 0x4000>;
+ interrupt-parent = <&tzic>;
+ interrupts = <96>;
+ status = "disabled";
+ };
+
+ /* 63FEC000 0x4000 FEC */
+ ethernet at 63fec000 {
+ compatible = "fsl,imx53-fec";
+ reg = <0x63fec000 0x4000>;
+ interrupt-parent = <&tzic>;
+ interrupts = <87>;
+ status = "disabled";
+ };
+
+ /* 63FF0000 0x4000 TVE */
+ /* 92 TVE */
+ /* 63FF4000 0x4000 VPU */
+ /* 9 VPU */
+ /* 100 VPU Idle interrupt from VPU */
+
+ /* 63FF8000 0x4000 SAHARA */
+ /* 19 SAHARA SAHARA host 0 (TrustZone) Intr */
+ /* 20 SAHARA SAHARA host 1 (non-TrustZone) Intr */
+ };
+ };
+
+ localbus at 10000000 {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+
+ sata at 10000000 {
+ compatible = "fsl,imx53-ata";
+ reg = <0x10000000 0x4000>;
+ interrupt-parent = <&tzic>;
+ interrupts = <28>;
+ status = "disabled";
+ };
+
+ vga: ipu3 at 1E000000 {
+ compatible = "fsl,ipu3";
+ reg = <
+ 0x1E000000 0x08000 /* CM */
+ 0x1E008000 0x08000 /* IDMAC */
+ 0x1E018000 0x08000 /* DP */
+ 0x1E020000 0x08000 /* IC */
+ 0x1E028000 0x08000 /* IRT */
+ 0x1E030000 0x08000 /* CSI0 */
+ 0x1E038000 0x08000 /* CSI1 */
+ 0x1E040000 0x08000 /* DI0 */
+ 0x1E048000 0x08000 /* DI1 */
+ 0x1E050000 0x08000 /* SMFC */
+ 0x1E058000 0x08000 /* DC */
+ 0x1E060000 0x08000 /* DMFC */
+ 0x1E068000 0x08000 /* VDI */
+ 0x1F000000 0x20000 /* CPMEM */
+ 0x1F020000 0x20000 /* LUT */
+ 0x1F040000 0x20000 /* SRM */
+ 0x1F060000 0x20000 /* TPM */
+ 0x1F080000 0x20000 /* DCTMPL */
+ >;
+ interrupt-parent = <&tzic>;
+ interrupts = <
+ 10 /* IPUEX Error */
+ 11 /* IPUEX Sync */
+ >;
+ status = "disabled";
+ };
+ };
+};
+
+/*
+
+TODO: Not mapped interrupts
+
+5 DAP
+84 GPU2D (OpenVG) general interrupt
+85 GPU2D (OpenVG) busy signal (for S/W power gating feasibility)
+12 GPU3D
+102 GPU3D Idle interrupt from GPU3D (for S/W power gating)
+90 SJC
+*/
Property changes on: trunk/sys/boot/fdt/dts/arm/imx53x.dtsi
___________________________________________________________________
Added: svn:eol-style
## -0,0 +1 ##
+native
\ No newline at end of property
Added: svn:keywords
## -0,0 +1 ##
+MidnightBSD=%H
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+text/plain
\ No newline at end of property
Added: trunk/sys/boot/fdt/dts/arm/imx6.dtsi
===================================================================
--- trunk/sys/boot/fdt/dts/arm/imx6.dtsi (rev 0)
+++ trunk/sys/boot/fdt/dts/arm/imx6.dtsi 2018-06-02 12:34:49 UTC (rev 10205)
@@ -0,0 +1,465 @@
+/* $MidnightBSD$ */
+/*
+ * Copyright (c) 2013 Ian Lepore
+ * Copyright (c) 2012 The FreeBSD Foundation
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ * Freescale i.MX6 Common Device Tree Source.
+ * There are enough differences between the Solo, Dual, Quad, and *-lite
+ * flavors of this SoC that eventually we will need a finer-grained breakdown
+ * of some of this stuff. For now this file works for all of them. I think.
+ *
+ * $FreeBSD: stable/10/sys/boot/fdt/dts/arm/imx6.dtsi 283500 2015-05-24 18:59:45Z ian $
+ */
+
+/ {
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cpu at 0 {
+ device_type = "cpu";
+ compatible = "ARM,MCIMX6";
+ reg = <0x0>;
+ d-cache-line-size = <32>;
+ i-cache-line-size = <32>;
+ d-cache-size = <0x8000>;
+ i-cache-size = <0x8000>;
+ /* TODO: describe L2 cache also */
+ timebase-frequency = <0>;
+ bus-frequency = <0>;
+ clock-frequency = <0>;
+ };
+ };
+
+ aliases {
+ soc = &SOC;
+ };
+
+ SOC: soc at 00000000 {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ interrupt-parent = <&gic>;
+ ranges = <0x00000000 0x00000000 0x10000000>;
+
+ gic: generic-interrupt-controller at 00a00100 {
+ compatible = "arm,gic";
+ interrupt-controller;
+ #interrupt-cells = <1>;
+ reg = <0x00a01000 0x00001000
+ 0x00a00100 0x00000100>;
+ };
+
+ mp_tmr0 at 00a00200 {
+ compatible = "arm,mpcore-timers";
+ reg = <0x00a00200 0x100
+ 0x00a00600 0x100>;
+ interrupts = <27 29>;
+ interrupt-parent = <&gic>;
+ };
+
+ l2-cache at 00a02000 {
+ compatible = "arm,pl310-cache", "arm,pl310";
+ reg = <0xa02000 0x1000>;
+ interrupts = <124>;
+ cache-level = <0x2>;
+ interrupt-parent = < &gic >;
+ };
+
+ aips at 02000000 { /* AIPS1 */
+ compatible = "fsl,aips-bus", "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ interrupt-parent = <&gic>;
+ reg = <0x02000000 0x00100000>;
+ ranges;
+
+ /* Required by many devices, so better to stay first */
+ clks: ccm at 020c4000 {
+ compatible = "fsl,imx6q-ccm";
+ reg = <0x020c4000 0x4000>;
+ interrupts = <119 120>;
+ };
+
+ /* System Reset Controller */
+ src: src at 4006E000 {
+ compatible = "fsl,imx6-src";
+ reg = <0x020D8000 0x100>;
+ };
+
+ sdma: sdma at 020ec000 {
+ compatible = "fsl,imx6q-sdma";
+ reg = <0x020ec000 0x4000>;
+ interrupt-parent = <&gic>;
+ interrupts = <34>;
+ status = "disabled";
+ };
+
+ anatop: anatop at 020c8000 {
+ compatible = "fsl,imx6q-anatop";
+ reg = <0x020c8000 0x1000>;
+ interrupt-parent = <&gic>;
+ interrupts = <49>;
+ };
+
+ gpt: timer at 02098000 {
+ compatible = "fsl,imx6q-gpt", "fsl,imx51-gpt";
+ reg = <0x02098000 0x4000>;
+ interrupt-parent = <&gic>;
+ interrupts = <87>;
+ };
+
+ iomux at 020e0000 {
+ compatible = "fsl,imx6q-iomuxc";
+ reg = <0x020e0000 0x4000>;
+ interrupt-parent = <&gic>;
+ interrupts = <32>;
+ };
+
+ gpio1: gpio at 0209c000 {
+ compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
+ reg = <0x0209c000 0x4000>;
+ interrupts = < 98 99 >;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ status = "disabled";
+ };
+
+ gpio2: gpio at 020a0000 {
+ compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
+ reg = <0x020a0000 0x4000>;
+ interrupts = < 100 101 >;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ status = "disabled";
+ };
+
+ gpio3: gpio at 020a4000 {
+ compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
+ reg = <0x020a4000 0x4000>;
+ interrupts = < 102 103 >;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ status = "disabled";
+ };
+
+ gpio4: gpio at 020a8000 {
+ compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
+ reg = <0x020a8000 0x4000>;
+ interrupts = < 104 105 >;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ status = "disabled";
+ };
+
+ gpio5: gpio at 020ac000 {
+ compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
+ reg = <0x020ac000 0x4000>;
+ interrupts = < 106 107 >;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ status = "disabled";
+ };
+
+ gpio6: gpio at 020b0000 {
+ compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
+ reg = <0x020b0000 0x4000>;
+ interrupts = < 108 109 >;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ status = "disabled";
+ };
+
+ gpio7: gpio at 020b4000 {
+ compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
+ reg = <0x020b4000 0x4000>;
+ interrupts = < 110 111 >;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ status = "disabled";
+ };
+
+ uart1: serial at 02020000 {
+ compatible = "fsl,imx6q-uart";
+ reg = <0x02020000 0x4000>;
+ interrupt-parent = <&gic>;
+ interrupts = <58>;
+ clock-frequency = <80000000>;
+ status = "disabled";
+ };
+
+ uart2: serial at 021e8000 {
+ compatible = "fsl,imx6q-uart";
+ reg = <0x021e8000 0x4000>;
+ interrupt-parent = <&gic>;
+ interrupts = <59>;
+ clock-frequency = <80000000>;
+ status = "disabled";
+ };
+
+ uart3: serial at 021ec000 {
+ compatible = "fsl,imx6q-uart";
+ reg = <0x021ec000 0x4000>;
+ interrupt-parent = <&gic>;
+ interrupts = <60>;
+ clock-frequency = <80000000>;
+ status = "disabled";
+ };
+
+ uart4: serial at 021f0000 {
+ compatible = "fsl,imx6q-uart";
+ reg = <0x021f0000 0x4000>;
+ interrupt-parent = <&gic>;
+ interrupts = <61>;
+ clock-frequency = <80000000>;
+ status = "disabled";
+ };
+
+ uart5: serial at 021f4000 {
+ compatible = "fsl,imx6q-uart";
+ reg = <0x021f4000 0x4000>;
+ interrupt-parent = <&gic>;
+ interrupts = <62>;
+ clock-frequency = <80000000>;
+ status = "disabled";
+ };
+
+ usbphy1: usbphy at 020c9000 {
+ compatible = "fsl,imx6q-usbphy", "fsl,imx23-usbphy";
+ reg = <0x020c9000 0x1000>;
+ interrupts = <44>;
+ status = "disabled";
+ };
+
+ usbphy2: usbphy at 020ca000 {
+ compatible = "fsl,imx6q-usbphy", "fsl,imx23-usbphy";
+ reg = <0x020ca000 0x1000>;
+ interrupts = <45>;
+ status = "disabled";
+ };
+
+ ecspi1: ecspi at 02008000 {
+ compatible = "fsl,imx6q-ecspi";
+ reg = <0x02008000 0x4000>;
+ interrupts = < 63 >;
+ status = "disabled";
+ };
+
+ ecspi2: ecspi at 0200C000 {
+ compatible = "fsl,imx6q-ecspi";
+ reg = <0x0200C000 0x4000>;
+ interrupts = < 64 >;
+ status = "disabled";
+ };
+
+ ecspi3: ecspi at 02010000 {
+ compatible = "fsl,imx6q-ecspi";
+ reg = <0x02010000 0x4000>;
+ interrupts = < 65 >;
+ status = "disabled";
+ };
+
+ ecspi4: ecspi at 02014000 {
+ compatible = "fsl,imx6q-ecspi";
+ reg = <0x02014000 0x4000>;
+ interrupts = < 66 >;
+ status = "disabled";
+ };
+
+ ecspi5: ecspi at 02018000 {
+ compatible = "fsl,imx6q-ecspi";
+ reg = <0x02018000 0x4000>;
+ interrupts = < 67 >;
+ status = "disabled";
+ };
+
+ ssi1: ssi at 02028000 {
+ compatible = "fsl,imx6q-ssi";
+ reg = <0x02028000 0x4000>;
+ interrupts = < 78 >;
+ dmas = <&sdma 37 1 0>,
+ <&sdma 38 1 0>;
+ dma-names = "rx", "tx";
+ status = "disabled";
+ };
+
+ ssi2: ssi at 0202C000 {
+ compatible = "fsl,imx6q-ssi";
+ reg = <0x0202C000 0x4000>;
+ interrupts = < 79 >;
+ status = "disabled";
+ };
+
+ ssi3: ssi at 02030000 {
+ compatible = "fsl,imx6q-ssi";
+ reg = <0x02030000 0x4000>;
+ interrupts = < 80 >;
+ status = "disabled";
+ };
+ };
+
+ aips at 02100000 { /* AIPS2 */
+ compatible = "fsl,aips-bus", "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ interrupt-parent = <&gic>;
+ reg = <0x02100000 0x00100000>;
+ ranges;
+
+ i2c1: i2c at 021a0000 {
+ compatible = "fsl,imx6q-i2c";
+ reg = <0x021a0000 0x4000>;
+ interrupts = < 68 >;
+ status = "disabled";
+ };
+
+ i2c2: i2c at 021a4000 {
+ compatible = "fsl,imx6q-i2c";
+ reg = <0x021a4000 0x4000>;
+ interrupts = < 69 >;
+ status = "disabled";
+ };
+
+ i2c3: i2c at 021ac000 {
+ compatible = "fsl,imx6q-i2c";
+ reg = <0x021a8000 0x4000>;
+ interrupts = < 70 >;
+ status = "disabled";
+ };
+
+ fec1: ethernet at 02188000 {
+ compatible = "fsl,imx6q-fec";
+ reg = <0x02188000 0x4000>;
+ interrupts = <150 151>;
+ status = "disabled";
+ };
+
+ usbotg1: usb at 02184000 {
+ compatible = "fsl,imx6q-usb", "fsl,imx27-usb";
+ reg = <0x02184000 0x200>;
+ interrupts = <75>;
+ fsl,usbphy = <&usbphy1>;
+ fsl,usbmisc = <&usbmisc 0>;
+ status = "disabled";
+ };
+
+ usbh1: usb at 02184200 {
+ compatible = "fsl,imx6q-usb", "fsl,imx27-usb";
+ reg = <0x02184200 0x200>;
+ interrupts = <72>;
+ fsl,usbphy = <&usbphy2>;
+ fsl,usbmisc = <&usbmisc 1>;
+ status = "disabled";
+ };
+
+ usbh2: usb at 02184400 {
+ compatible = "fsl,imx6q-usb", "fsl,imx27-usb";
+ reg = <0x02184400 0x200>;
+ interrupts = <73>;
+ fsl,usbmisc = <&usbmisc 2>;
+ status = "disabled";
+ };
+
+ usbh3: usb at 02184600 {
+ compatible = "fsl,imx6q-usb", "fsl,imx27-usb";
+ reg = <0x02184600 0x200>;
+ interrupts = <74>;
+ fsl,usbmisc = <&usbmisc 3>;
+ status = "disabled";
+ };
+
+ usbmisc: usbmisc at 02184800 {
+ #index-cells = <1>;
+ compatible = "fsl,imx6q-usbmisc";
+ reg = <0x02184800 0x200>;
+ // Not disabled on purpose.
+ };
+
+ usdhc1: usdhc at 02190000 {
+ compatible = "fsl,imx6q-usdhc";
+ reg = <0x02190000 0x4000>;
+ interrupt-parent = <&gic>;
+ interrupts = <54>;
+ cd-gpios = <&gpio1 2 0>;
+ bus-width = <0x4>;
+ status ="disabled";
+ };
+
+ usdhc2: usdhc at 02194000 {
+ compatible = "fsl,imx6q-usdhc";
+ reg = <0x02194000 0x4000>;
+ interrupt-parent = <&gic>;
+ interrupts = <55>;
+ non-removable;
+ bus-width = <0x4>;
+ status ="disabled";
+ };
+
+ usdhc3: usdhc at 02198000 {
+ compatible = "fsl,imx6q-usdhc";
+ reg = <0x02198000 0x4000>;
+ interrupt-parent = <&gic>;
+ interrupts = <56>;
+ cd-gpios = <&gpio3 9 0>;
+ bus-width = <0x4>;
+ status ="disabled";
+ };
+
+ usdhc4: usdhc at 0219c000 {
+ compatible = "fsl,imx6q-usdhc";
+ reg = <0x0219c000 0x4000>;
+ interrupt-parent = <&gic>;
+ interrupts = <57>;
+ bus-width = <0x4>;
+ status ="disabled";
+ };
+
+ ocotp0: ocotp at 021bc000 {
+ compatible = "fsl,imx6q-ocotp";
+ reg = <0x021bc000 0x4000>;
+ };
+
+ audmux: audmux at 021d8000 {
+ compatible = "fsl,imx6q-audmux";
+ reg = <0x021d8000 0x4000>;
+ status = "disabled";
+ };
+ };
+ };
+};
Property changes on: trunk/sys/boot/fdt/dts/arm/imx6.dtsi
___________________________________________________________________
Added: svn:eol-style
## -0,0 +1 ##
+native
\ No newline at end of property
Added: svn:keywords
## -0,0 +1 ##
+MidnightBSD=%H
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+text/plain
\ No newline at end of property
Added: trunk/sys/boot/fdt/dts/arm/p2041rdb.dts
===================================================================
--- trunk/sys/boot/fdt/dts/arm/p2041rdb.dts (rev 0)
+++ trunk/sys/boot/fdt/dts/arm/p2041rdb.dts 2018-06-02 12:34:49 UTC (rev 10205)
@@ -0,0 +1,491 @@
+/* $MidnightBSD$ */
+/*
+ * P2041RDB Device Tree Source
+ *
+ * Copyright 2011 Freescale Semiconductor Inc.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * * Neither the name of Freescale Semiconductor nor the
+ * names of its contributors may be used to endorse or promote products
+ * derived from this software without specific prior written permission.
+ *
+ *
+ * ALTERNATIVELY, this software may be distributed under the terms of the
+ * GNU General Public License ("GPL") as published by the Free Software
+ * Foundation, either version 2 of that License or (at your option) any
+ * later version.
+ *
+ * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+/* $FreeBSD: stable/10/sys/boot/fdt/dts/arm/p2041rdb.dts 262614 2014-02-28 18:29:09Z imp $ */
+
+/include/ "p2041si.dtsi"
+
+/ {
+ model = "fsl,P2041RDB";
+ compatible = "fsl,P2041RDB";
+ #address-cells = <2>;
+ #size-cells = <2>;
+ interrupt-parent = <&mpic>;
+
+ aliases {
+ phy_rgmii_0 = &phy_rgmii_0;
+ phy_rgmii_1 = &phy_rgmii_1;
+ phy_sgmii_2 = &phy_sgmii_2;
+ phy_sgmii_3 = &phy_sgmii_3;
+ phy_sgmii_4 = &phy_sgmii_4;
+ phy_sgmii_1c = &phy_sgmii_1c;
+ phy_sgmii_1d = &phy_sgmii_1d;
+ phy_sgmii_1e = &phy_sgmii_1e;
+ phy_sgmii_1f = &phy_sgmii_1f;
+ phy_xgmii_2 = &phy_xgmii_2;
+ };
+
+ memory {
+ device_type = "memory";
+ reg = <0x00000000 0x00000000 0x00000000 0x80000000>;
+ };
+
+ dcsr: dcsr at f00000000 {
+ ranges = <0x00000000 0xf 0x00000000 0x01008000>;
+ };
+
+ bman-portals at ff4000000 {
+ bman-portal at 0 {
+ cpu-handle = <&cpu0>;
+ };
+ bman-portal at 4000 {
+ cpu-handle = <&cpu1>;
+ };
+ bman-portal at 8000 {
+ cpu-handle = <&cpu2>;
+ };
+ bman-portal at c000 {
+ cpu-handle = <&cpu3>;
+ };
+ bman-portal at 10000 {
+ };
+ bman-portal at 14000 {
+ };
+ bman-portal at 18000 {
+ };
+ bman-portal at 1c000 {
+ };
+ bman-portal at 20000 {
+ };
+ bman-portal at 24000 {
+ };
+
+ buffer-pool at 0 {
+ compatible = "fsl,p2041-bpool", "fsl,bpool";
+ fsl,bpid = <0>;
+ fsl,bpool-cfg = <0 0x100 0 1 0 0x100>;
+ };
+ };
+
+ qman-portals at ff4200000 {
+ qportal0: qman-portal at 0 {
+ cpu-handle = <&cpu0>;
+ fsl,qman-pool-channels = <&qpool1 &qpool2 &qpool3
+ &qpool4 &qpool5 &qpool6
+ &qpool7 &qpool8 &qpool9
+ &qpool10 &qpool11 &qpool12
+ &qpool13 &qpool14 &qpool15>;
+ };
+
+ qportal1: qman-portal at 4000 {
+ cpu-handle = <&cpu1>;
+ fsl,qman-pool-channels = <&qpool1 &qpool2 &qpool3
+ &qpool4 &qpool5 &qpool6
+ &qpool7 &qpool8 &qpool9
+ &qpool10 &qpool11 &qpool12
+ &qpool13 &qpool14 &qpool15>;
+ };
+
+ qportal2: qman-portal at 8000 {
+ cpu-handle = <&cpu2>;
+ fsl,qman-pool-channels = <&qpool1 &qpool2 &qpool3
+ &qpool4 &qpool5 &qpool6
+ &qpool7 &qpool8 &qpool9
+ &qpool10 &qpool11 &qpool12
+ &qpool13 &qpool14 &qpool15>;
+ };
+
+ qportal3: qman-portal at c000 {
+ cpu-handle = <&cpu3>;
+ fsl,qman-pool-channels = <&qpool1 &qpool2 &qpool3
+ &qpool4 &qpool5 &qpool6
+ &qpool7 &qpool8 &qpool9
+ &qpool10 &qpool11 &qpool12
+ &qpool13 &qpool14 &qpool15>;
+ };
+
+ qportal4: qman-portal at 10000 {
+ fsl,qman-pool-channels = <&qpool1 &qpool2 &qpool3
+ &qpool4 &qpool5 &qpool6
+ &qpool7 &qpool8 &qpool9
+ &qpool10 &qpool11 &qpool12
+ &qpool13 &qpool14 &qpool15>;
+ };
+
+ qportal5: qman-portal at 14000 {
+ fsl,qman-pool-channels = <&qpool1 &qpool2 &qpool3
+ &qpool4 &qpool5 &qpool6
+ &qpool7 &qpool8 &qpool9
+ &qpool10 &qpool11 &qpool12
+ &qpool13 &qpool14 &qpool15>;
+ };
+
+ qportal6: qman-portal at 18000 {
+ fsl,qman-pool-channels = <&qpool1 &qpool2 &qpool3
+ &qpool4 &qpool5 &qpool6
+ &qpool7 &qpool8 &qpool9
+ &qpool10 &qpool11 &qpool12
+ &qpool13 &qpool14 &qpool15>;
+ };
+
+ qportal7: qman-portal at 1c000 {
+ fsl,qman-pool-channels = <&qpool1 &qpool2 &qpool3
+ &qpool4 &qpool5 &qpool6
+ &qpool7 &qpool8 &qpool9
+ &qpool10 &qpool11 &qpool12
+ &qpool13 &qpool14 &qpool15>;
+ };
+
+ qportal8: qman-portal at 20000 {
+ fsl,qman-pool-channels = <&qpool1 &qpool2 &qpool3
+ &qpool4 &qpool5 &qpool6
+ &qpool7 &qpool8 &qpool9
+ &qpool10 &qpool11 &qpool12
+ &qpool13 &qpool14 &qpool15>;
+ };
+
+ qportal9: qman-portal at 24000 {
+ fsl,qman-pool-channels = <&qpool1 &qpool2 &qpool3
+ &qpool4 &qpool5 &qpool6
+ &qpool7 &qpool8 &qpool9
+ &qpool10 &qpool11 &qpool12
+ &qpool13 &qpool14 &qpool15>;
+ };
+ };
+
+ soc: soc at ffe000000 {
+ spi at 110000 {
+ flash at 0 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "spansion,s25sl12801";
+ reg = <0>;
+ spi-max-frequency = <40000000>; /* input clock */
+ partition at u-boot {
+ label = "u-boot";
+ reg = <0x00000000 0x00100000>;
+ read-only;
+ };
+ partition at kernel {
+ label = "kernel";
+ reg = <0x00100000 0x00500000>;
+ read-only;
+ };
+ partition at dtb {
+ label = "dtb";
+ reg = <0x00600000 0x00100000>;
+ read-only;
+ };
+ partition at fs {
+ label = "file system";
+ reg = <0x00700000 0x00900000>;
+ };
+ };
+ };
+
+ i2c at 118000 {
+ lm75b at 48 {
+ compatible = "nxp,lm75a";
+ reg = <0x48>;
+ };
+ eeprom at 50 {
+ compatible = "at24,24c256";
+ reg = <0x50>;
+ };
+ rtc at 68 {
+ compatible = "pericom,pt7c4338";
+ reg = <0x68>;
+ };
+ };
+
+ i2c at 118100 {
+ eeprom at 50 {
+ compatible = "at24,24c256";
+ reg = <0x50>;
+ };
+ };
+
+ usb1: usb at 211000 {
+ dr_mode = "host";
+ };
+
+ pme: pme at 316000 {
+ /* Commented out, use default allocation */
+ /* fsl,pme-pdsr = <0x0 0x23000000 0x0 0x01000000>; */
+ /* fsl,pme-sre = <0x0 0x24000000 0x0 0x00a00000>; */
+ };
+
+ qman: qman at 318000 {
+ /* Commented out, use default allocation */
+ /* fsl,qman-fqd = <0x0 0x20000000 0x0 0x01000000>; */
+ /* fsl,qman-pfdr = <0x0 0x21000000 0x0 0x01000000>; */
+ };
+
+ bman: bman at 31a000 {
+ /* Same as fsl,qman-*, use default allocation */
+ /* fsl,bman-fbpr = <0x0 0x22000000 0x0 0x01000000>; */
+ };
+
+ fman0: fman at 400000 {
+ enet0: ethernet at e0000 {
+ tbi-handle = <&tbi0>;
+ phy-handle = <&phy_sgmii_2>;
+ phy-connection-type = "sgmii";
+ };
+
+ mdio0: mdio at e1120 {
+ tbi0: tbi-phy at 8 {
+ reg = <0x8>;
+ device_type = "tbi-phy";
+ };
+
+ phy_rgmii_0: ethernet-phy at 0 {
+ reg = <0x0>;
+ };
+ phy_rgmii_1: ethernet-phy at 1 {
+ reg = <0x1>;
+ };
+ phy_sgmii_2: ethernet-phy at 2 {
+ reg = <0x2>;
+ };
+ phy_sgmii_3: ethernet-phy at 3 {
+ reg = <0x3>;
+ };
+ phy_sgmii_4: ethernet-phy at 4 {
+ reg = <0x4>;
+ };
+ phy_sgmii_1c: ethernet-phy at 1c {
+ reg = <0x1c>;
+ };
+ phy_sgmii_1d: ethernet-phy at 1d {
+ reg = <0x1d>;
+ };
+ phy_sgmii_1e: ethernet-phy at 1e {
+ reg = <0x1e>;
+ };
+ phy_sgmii_1f: ethernet-phy at 1f {
+ reg = <0x1f>;
+ };
+ };
+
+ enet1: ethernet at e2000 {
+ tbi-handle = <&tbi1>;
+ phy-handle = <&phy_sgmii_3>;
+ phy-connection-type = "sgmii";
+ };
+
+ mdio at e3120 {
+ tbi1: tbi-phy at 8 {
+ reg = <8>;
+ device_type = "tbi-phy";
+ };
+ };
+
+ enet2: ethernet at e4000 {
+ tbi-handle = <&tbi2>;
+ phy-handle = <&phy_sgmii_4>;
+ phy-connection-type = "sgmii";
+ };
+
+ mdio at e5120 {
+ tbi2: tbi-phy at 8 {
+ reg = <8>;
+ device_type = "tbi-phy";
+ };
+ };
+
+ enet3: ethernet at e6000 {
+ tbi-handle = <&tbi3>;
+ phy-handle = <&phy_rgmii_1>;
+ phy-connection-type = "rgmii";
+ };
+
+ mdio at e7120 {
+ tbi3: tbi-phy at 8 {
+ reg = <8>;
+ device_type = "tbi-phy";
+ };
+ };
+
+ enet4: ethernet at e8000 {
+ tbi-handle = <&tbi4>;
+ phy-handle = <&phy_rgmii_0>;
+ phy-connection-type = "rgmii";
+ };
+
+ mdio at e9120 {
+ tbi4: tbi-phy at 8 {
+ reg = <8>;
+ device_type = "tbi-phy";
+ };
+ };
+
+ enet5: ethernet at f0000 {
+ /*
+ * phy-handle will be updated by U-Boot to
+ * reflect the actual slot the XAUI card is in.
+ */
+ phy-handle = <&phy_xgmii_2>;
+ phy-connection-type = "xgmii";
+ };
+
+ mdio at f1000 {
+ /* XAUI card in slot 2 */
+ phy_xgmii_2: ethernet-phy at 0 {
+ reg = <0x0>;
+ };
+ };
+ };
+ };
+
+ rapidio at ffe0c0000 {
+ reg = <0xf 0xfe0c0000 0 0x11000>;
+
+ port1 {
+ ranges = <0 0 0xc 0x20000000 0 0x10000000>;
+ };
+ port2 {
+ ranges = <0 0 0xc 0x30000000 0 0x10000000>;
+ };
+ };
+
+ localbus at ffe124000 {
+ reg = <0xf 0xfe124000 0 0x1000>;
+ ranges = <0 0 0xf 0xb8000000 0x04000000>;
+
+ flash at 0,0 {
+ compatible = "cfi-flash";
+ /*
+ * Map 64Mb of 128MB NOR flash memory. Since highest
+ * line of address of NOR flash memory are set by
+ * FPGA, memory are divided into two pages equal to
+ * 64MB. One of the pages can be accessed at once.
+ */
+ reg = <0 0 0x04000000>;
+ bank-width = <2>;
+ device-width = <2>;
+ };
+ };
+
+ pci0: pcie at ffe200000 {
+ reg = <0xf 0xfe200000 0 0x1000>;
+ ranges = <0x02000000 0 0x80000000 0x0 0x80000000 0x0 0x10000000
+ 0x01000000 0 0x00000000 0x0 0xff000000 0x0 0x00010000>;
+ pcie at 0 {
+ ranges = <0x02000000 0 0x80000000
+ 0x02000000 0 0x80000000
+ 0 0x10000000
+
+ 0x01000000 0 0x00000000
+ 0x01000000 0 0xff000000
+ 0 0x00010000>;
+ };
+ };
+
+ pci1: pcie at ffe201000 {
+ reg = <0xf 0xfe201000 0 0x1000>;
+ ranges = <0x02000000 0x0 0x90000000 0x0 0x90000000 0x0 0x10000000
+ 0x01000000 0x0 0x00000000 0x0 0xff010000 0x0 0x00010000>;
+ pcie at 0 {
+ ranges = <0x02000000 0 0x90000000
+ 0x02000000 0 0x90000000
+ 0 0x10000000
+
+ 0x01000000 0 0x00000000
+ 0x01000000 0 0xff010000
+ 0 0x00010000>;
+ };
+ };
+
+ pci2: pcie at ffe202000 {
+ reg = <0xf 0xfe202000 0 0x1000>;
+ ranges = <0x02000000 0 0xa0000000 0x0 0xa0000000 0 0x10000000
+ 0x01000000 0 0x00000000 0x0 0xff020000 0 0x00010000>;
+ pcie at 0 {
+ ranges = <0x02000000 0 0xa0000000
+ 0x02000000 0 0xa0000000
+ 0 0x10000000
+
+ 0x01000000 0 0x00000000
+ 0x01000000 0 0xff020000
+ 0 0x00010000>;
+ };
+ };
+
+ fsl,dpaa {
+ compatible = "fsl,p2041-dpaa", "fsl,dpaa";
+
+ ethernet at 0 {
+ compatible = "fsl,p2041-dpa-ethernet", "fsl,dpa-ethernet";
+ fsl,qman-channel = <&qpool1>;
+ fsl,fman-mac = <&enet0>;
+ status = "okay";
+ };
+ ethernet at 1 {
+ compatible = "fsl,p2041-dpa-ethernet", "fsl,dpa-ethernet";
+ fsl,qman-channel = <&qpool1>;
+ fsl,fman-mac = <&enet1>;
+ status = "okay";
+ };
+ ethernet at 2 {
+ compatible = "fsl,p2041-dpa-ethernet", "fsl,dpa-ethernet";
+ fsl,qman-channel = <&qpool1>;
+ fsl,fman-mac = <&enet2>;
+ status = "okay";
+ };
+ ethernet at 3 {
+ compatible = "fsl,p2041-dpa-ethernet", "fsl,dpa-ethernet";
+ fsl,qman-channel = <&qpool1>;
+ fsl,fman-mac = <&enet3>;
+ status = "okay";
+ };
+ ethernet at 4 {
+ compatible = "fsl,p2041-dpa-ethernet", "fsl,dpa-ethernet";
+ fsl,qman-channel = <&qpool1>;
+ fsl,fman-mac = <&enet4>;
+ status = "okay";
+ };
+ ethernet at 5 {
+ compatible = "fsl,p2041-dpa-ethernet", "fsl,dpa-ethernet";
+ fsl,qman-channel = <&qpool1>;
+ fsl,fman-mac = <&enet5>;
+ status = "okay";
+ };
+ };
+
+ chosen {
+ stdin = "serial0";
+ stdout = "serial0";
+ };
+};
Property changes on: trunk/sys/boot/fdt/dts/arm/p2041rdb.dts
___________________________________________________________________
Added: svn:eol-style
## -0,0 +1 ##
+native
\ No newline at end of property
Added: svn:keywords
## -0,0 +1 ##
+MidnightBSD=%H
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+text/plain
\ No newline at end of property
Added: trunk/sys/boot/fdt/dts/arm/p3041ds.dts
===================================================================
--- trunk/sys/boot/fdt/dts/arm/p3041ds.dts (rev 0)
+++ trunk/sys/boot/fdt/dts/arm/p3041ds.dts 2018-06-02 12:34:49 UTC (rev 10205)
@@ -0,0 +1,588 @@
+/* $MidnightBSD$ */
+/*
+ * P3041DS Device Tree Source
+ *
+ * Copyright 2010-2011 Freescale Semiconductor Inc.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * * Neither the name of Freescale Semiconductor nor the
+ * names of its contributors may be used to endorse or promote products
+ * derived from this software without specific prior written permission.
+ *
+ *
+ * ALTERNATIVELY, this software may be distributed under the terms of the
+ * GNU General Public License ("GPL") as published by the Free Software
+ * Foundation, either version 2 of that License or (at your option) any
+ * later version.
+ *
+ * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+/* $FreeBSD: stable/10/sys/boot/fdt/dts/arm/p3041ds.dts 262614 2014-02-28 18:29:09Z imp $ */
+
+/include/ "p3041si.dtsi"
+
+/ {
+ model = "fsl,P3041DS";
+ compatible = "fsl,P3041DS";
+ #address-cells = <2>;
+ #size-cells = <2>;
+ interrupt-parent = <&mpic>;
+
+ aliases {
+ phy_rgmii_0 = &phy_rgmii_0;
+ phy_rgmii_1 = &phy_rgmii_1;
+ phy_sgmii_1c = &phy_sgmii_1c;
+ phy_sgmii_1d = &phy_sgmii_1d;
+ phy_sgmii_1e = &phy_sgmii_1e;
+ phy_sgmii_1f = &phy_sgmii_1f;
+ phy_xgmii_1 = &phy_xgmii_1;
+ phy_xgmii_2 = &phy_xgmii_2;
+ emi1_rgmii = &hydra_mdio_rgmii;
+ emi1_sgmii = &hydra_mdio_sgmii;
+ emi2_xgmii = &hydra_mdio_xgmii;
+ };
+
+ memory {
+ device_type = "memory";
+ reg = <0x00000000 0x00000000 0x00000000 0x80000000>;
+ };
+
+ dcsr: dcsr at f00000000 {
+ ranges = <0x00000000 0xf 0x00000000 0x01008000>;
+ };
+
+ bman-portals at ff4000000 {
+ bman-portal at 0 {
+ cpu-handle = <&cpu0>;
+ };
+ bman-portal at 4000 {
+ cpu-handle = <&cpu1>;
+ };
+ bman-portal at 8000 {
+ cpu-handle = <&cpu2>;
+ };
+ bman-portal at c000 {
+ cpu-handle = <&cpu3>;
+ };
+ bman-portal at 10000 {
+ };
+ bman-portal at 14000 {
+ };
+ bman-portal at 18000 {
+ };
+ bman-portal at 1c000 {
+ };
+ bman-portal at 20000 {
+ };
+ bman-portal at 24000 {
+ };
+
+ buffer-pool at 0 {
+ compatible = "fsl,p3041-bpool", "fsl,bpool";
+ fsl,bpid = <0>;
+ fsl,bpool-cfg = <0 0x100 0 1 0 0x100>;
+ };
+ };
+
+ qman-portals at ff4200000 {
+ qportal0: qman-portal at 0 {
+ cpu-handle = <&cpu0>;
+ fsl,qman-pool-channels = <&qpool1 &qpool2 &qpool3
+ &qpool4 &qpool5 &qpool6
+ &qpool7 &qpool8 &qpool9
+ &qpool10 &qpool11 &qpool12
+ &qpool13 &qpool14 &qpool15>;
+ };
+
+ qportal1: qman-portal at 4000 {
+ cpu-handle = <&cpu1>;
+ fsl,qman-pool-channels = <&qpool1 &qpool2 &qpool3
+ &qpool4 &qpool5 &qpool6
+ &qpool7 &qpool8 &qpool9
+ &qpool10 &qpool11 &qpool12
+ &qpool13 &qpool14 &qpool15>;
+ };
+
+ qportal2: qman-portal at 8000 {
+ cpu-handle = <&cpu2>;
+ fsl,qman-pool-channels = <&qpool1 &qpool2 &qpool3
+ &qpool4 &qpool5 &qpool6
+ &qpool7 &qpool8 &qpool9
+ &qpool10 &qpool11 &qpool12
+ &qpool13 &qpool14 &qpool15>;
+ };
+
+ qportal3: qman-portal at c000 {
+ cpu-handle = <&cpu3>;
+ fsl,qman-pool-channels = <&qpool1 &qpool2 &qpool3
+ &qpool4 &qpool5 &qpool6
+ &qpool7 &qpool8 &qpool9
+ &qpool10 &qpool11 &qpool12
+ &qpool13 &qpool14 &qpool15>;
+ };
+
+ qportal4: qman-portal at 10000 {
+ fsl,qman-pool-channels = <&qpool1 &qpool2 &qpool3
+ &qpool4 &qpool5 &qpool6
+ &qpool7 &qpool8 &qpool9
+ &qpool10 &qpool11 &qpool12
+ &qpool13 &qpool14 &qpool15>;
+ };
+
+ qportal5: qman-portal at 14000 {
+ fsl,qman-pool-channels = <&qpool1 &qpool2 &qpool3
+ &qpool4 &qpool5 &qpool6
+ &qpool7 &qpool8 &qpool9
+ &qpool10 &qpool11 &qpool12
+ &qpool13 &qpool14 &qpool15>;
+ };
+
+ qportal6: qman-portal at 18000 {
+ fsl,qman-pool-channels = <&qpool1 &qpool2 &qpool3
+ &qpool4 &qpool5 &qpool6
+ &qpool7 &qpool8 &qpool9
+ &qpool10 &qpool11 &qpool12
+ &qpool13 &qpool14 &qpool15>;
+ };
+
+ qportal7: qman-portal at 1c000 {
+ fsl,qman-pool-channels = <&qpool1 &qpool2 &qpool3
+ &qpool4 &qpool5 &qpool6
+ &qpool7 &qpool8 &qpool9
+ &qpool10 &qpool11 &qpool12
+ &qpool13 &qpool14 &qpool15>;
+ };
+
+ qportal8: qman-portal at 20000 {
+ fsl,qman-pool-channels = <&qpool1 &qpool2 &qpool3
+ &qpool4 &qpool5 &qpool6
+ &qpool7 &qpool8 &qpool9
+ &qpool10 &qpool11 &qpool12
+ &qpool13 &qpool14 &qpool15>;
+ };
+
+ qportal9: qman-portal at 24000 {
+ fsl,qman-pool-channels = <&qpool1 &qpool2 &qpool3
+ &qpool4 &qpool5 &qpool6
+ &qpool7 &qpool8 &qpool9
+ &qpool10 &qpool11 &qpool12
+ &qpool13 &qpool14 &qpool15>;
+ };
+ };
+
+ soc: soc at ffe000000 {
+ spi at 110000 {
+ flash at 0 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "spansion,s25sl12801";
+ reg = <0>;
+ spi-max-frequency = <35000000>; /* input clock */
+ partition at u-boot {
+ label = "u-boot";
+ reg = <0x00000000 0x00100000>;
+ read-only;
+ };
+ partition at kernel {
+ label = "kernel";
+ reg = <0x00100000 0x00500000>;
+ read-only;
+ };
+ partition at dtb {
+ label = "dtb";
+ reg = <0x00600000 0x00100000>;
+ read-only;
+ };
+ partition at fs {
+ label = "file system";
+ reg = <0x00700000 0x00900000>;
+ };
+ };
+ };
+
+ i2c at 118100 {
+ eeprom at 51 {
+ compatible = "at24,24c256";
+ reg = <0x51>;
+ };
+ eeprom at 52 {
+ compatible = "at24,24c256";
+ reg = <0x52>;
+ };
+ };
+
+ i2c at 119100 {
+ rtc at 68 {
+ compatible = "dallas,ds3232";
+ reg = <0x68>;
+ interrupts = <0x1 0x1 0 0>;
+ };
+ };
+
+ pme: pme at 316000 {
+ /* Commented out, use default allocation */
+ /* fsl,pme-pdsr = <0x0 0x23000000 0x0 0x01000000>; */
+ /* fsl,pme-sre = <0x0 0x24000000 0x0 0x00a00000>; */
+ };
+
+ qman: qman at 318000 {
+ /* Commented out, use default allocation */
+ /* fsl,qman-fqd = <0x0 0x20000000 0x0 0x01000000>; */
+ /* fsl,qman-pfdr = <0x0 0x21000000 0x0 0x01000000>; */
+ };
+
+ bman: bman at 31a000 {
+ /* Same as fsl,qman-*, use default allocation */
+ /* fsl,bman-fbpr = <0x0 0x22000000 0x0 0x01000000>; */
+ };
+
+ fman0: fman at 400000 {
+ enet0: ethernet at e0000 {
+ tbi-handle = <&tbi0>;
+ phy-handle = <&phy_rgmii_0>;
+ phy-connection-type = "rgmii";
+ };
+
+ mdio0: mdio at e1120 {
+ tbi0: tbi-phy at 8 {
+ reg = <0x8>;
+ device_type = "tbi-phy";
+ };
+
+ /*
+ * Virtual MDIO for the two on-board RGMII
+ * ports. The fsl,hydra-mdio-muxval property
+ * is already correct.
+ */
+ hydra_mdio_rgmii: hydra-mdio-rgmii {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "fsl,hydra-mdio";
+ fsl,mdio-handle = <&mdio0>;
+ fsl,hydra-mdio-muxval = <0x00>;
+ status = "disabled";
+
+ phy_rgmii_0: ethernet-phy at 0 {
+ reg = <0x0>;
+ };
+ phy_rgmii_1: ethernet-phy at 1 {
+ reg = <0x1>;
+ };
+ };
+
+ /*
+ * Virtual MDIO for the four-port SGMII card.
+ * The fsl,hydra-mdio-muxval property will be
+ * fixed-up by U-Boot based on the slot that
+ * the SGMII card is in.
+ *
+ * Note: we do not support DTSEC5 connected to
+ * SGMII, so this is the only SGMII node.
+ */
+ hydra_mdio_sgmii: hydra-mdio-sgmii {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "fsl,hydra-mdio";
+ fsl,mdio-handle = <&mdio0>;
+ fsl,hydra-mdio-muxval = <0x00>;
+ status = "disabled";
+
+ phy_sgmii_1c: ethernet-phy at 1c {
+ reg = <0x1c>;
+ };
+ phy_sgmii_1d: ethernet-phy at 1d {
+ reg = <0x1d>;
+ };
+ phy_sgmii_1e: ethernet-phy at 1e {
+ reg = <0x1e>;
+ };
+ phy_sgmii_1f: ethernet-phy at 1f {
+ reg = <0x1f>;
+ };
+ };
+ };
+
+ enet1: ethernet at e2000 {
+ tbi-handle = <&tbi1>;
+ phy-handle = <&phy_sgmii_1d>;
+ phy-connection-type = "sgmii";
+ };
+
+ mdio at e3120 {
+ tbi1: tbi-phy at 8 {
+ reg = <8>;
+ device_type = "tbi-phy";
+ };
+ };
+
+ enet2: ethernet at e4000 {
+ tbi-handle = <&tbi2>;
+ phy-handle = <&phy_sgmii_1e>;
+ phy-connection-type = "sgmii";
+ };
+
+ mdio at e5120 {
+ tbi2: tbi-phy at 8 {
+ reg = <8>;
+ device_type = "tbi-phy";
+ };
+ };
+
+ enet3: ethernet at e6000 {
+ tbi-handle = <&tbi3>;
+ phy-handle = <&phy_sgmii_1f>;
+ phy-connection-type = "sgmii";
+ };
+
+ mdio at e7120 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "fsl,fman-tbi";
+ reg = <0xe7120 0xee0>;
+ interrupts = <100 1 0 0>;
+
+ tbi3: tbi-phy at 8 {
+ reg = <8>;
+ device_type = "tbi-phy";
+ };
+ };
+
+ enet4: ethernet at e8000 {
+ tbi-handle = <&tbi4>;
+ phy-handle = <&phy_rgmii_1>;
+ phy-connection-type = "rgmii";
+ };
+
+ mdio at e9120 {
+ tbi4: tbi-phy at 8 {
+ reg = <8>;
+ device_type = "tbi-phy";
+ };
+ };
+
+ enet5: ethernet at f0000 {
+ /*
+ * phy-handle will be updated by U-Boot to
+ * reflect the actual slot the XAUI card is in.
+ */
+ phy-handle = <&phy_xgmii_1>;
+ phy-connection-type = "xgmii";
+ };
+
+ /*
+ * We only support one XAUI card, so the MDIO muxing
+ * is set by U-Boot, and Linux never touches it.
+ * Therefore, we don't need a virtual MDIO node.
+ * However, the phy address depends on the slot, so
+ * only one of the ethernet-phy nodes below will be
+ * used.
+ */
+ hydra_mdio_xgmii: mdio at f1000 {
+ status = "disabled";
+
+ /* XAUI card in slot 1 */
+ phy_xgmii_1: ethernet-phy at 4 {
+ reg = <0x4>;
+ };
+
+ /* XAUI card in slot 2 */
+ phy_xgmii_2: ethernet-phy at 0 {
+ reg = <0x0>;
+ };
+ };
+ };
+ };
+
+ rapidio at ffe0c0000 {
+ reg = <0xf 0xfe0c0000 0 0x11000>;
+
+ port1 {
+ ranges = <0 0 0xc 0x20000000 0 0x10000000>;
+ };
+ port2 {
+ ranges = <0 0 0xc 0x30000000 0 0x10000000>;
+ };
+ };
+
+ localbus at ffe124000 {
+ reg = <0xf 0xfe124000 0 0x1000>;
+ ranges = <0 0 0xf 0xb8000000 0x04000000>;
+
+ flash at 0,0 {
+ compatible = "cfi-flash";
+ /*
+ * Map 64Mb of 128MB NOR flash memory. Since highest
+ * line of address of NOR flash memory are set by
+ * FPGA, memory are divided into two pages equal to
+ * 64MB. One of the pages can be accessed at once.
+ */
+ reg = <0 0 0x04000000>;
+ bank-width = <2>;
+ device-width = <2>;
+ };
+
+ nand at 2,0 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "fsl,elbc-fcm-nand";
+ reg = <0x2 0x0 0x40000>;
+
+ partition at 0 {
+ label = "NAND U-Boot Image";
+ reg = <0x0 0x02000000>;
+ read-only;
+ };
+
+ partition at 2000000 {
+ label = "NAND Root File System";
+ reg = <0x02000000 0x10000000>;
+ };
+
+ partition at 12000000 {
+ label = "NAND Compressed RFS Image";
+ reg = <0x12000000 0x08000000>;
+ };
+
+ partition at 1a000000 {
+ label = "NAND Linux Kernel Image";
+ reg = <0x1a000000 0x04000000>;
+ };
+
+ partition at 1e000000 {
+ label = "NAND DTB Image";
+ reg = <0x1e000000 0x01000000>;
+ };
+
+ partition at 1f000000 {
+ label = "NAND Writable User area";
+ reg = <0x1f000000 0x21000000>;
+ };
+ };
+
+ board-control at 3,0 {
+ compatible = "fsl,p3041ds-fpga", "fsl,fpga-ngpixis";
+ reg = <3 0 0x30>;
+ };
+ };
+
+ pci0: pcie at ffe200000 {
+ reg = <0xf 0xfe200000 0 0x1000>;
+ ranges = <0x02000000 0 0x80000000 0x0 0x80000000 0x0 0x10000000
+ 0x01000000 0 0x00000000 0x0 0xff000000 0x0 0x00010000>;
+ pcie at 0 {
+ ranges = <0x02000000 0 0x80000000
+ 0x02000000 0 0x80000000
+ 0 0x10000000
+
+ 0x01000000 0 0x00000000
+ 0x01000000 0 0xff000000
+ 0 0x00010000>;
+ };
+ };
+
+ pci1: pcie at ffe201000 {
+ reg = <0xf 0xfe201000 0 0x1000>;
+ ranges = <0x02000000 0x0 0x90000000 0x0 0x90000000 0x0 0x10000000
+ 0x01000000 0x0 0x00000000 0x0 0xff010000 0x0 0x00010000>;
+ pcie at 0 {
+ ranges = <0x02000000 0 0x90000000
+ 0x02000000 0 0x90000000
+ 0 0x10000000
+
+ 0x01000000 0 0x00000000
+ 0x01000000 0 0xff010000
+ 0 0x00010000>;
+ };
+ };
+
+ pci2: pcie at ffe202000 {
+ reg = <0xf 0xfe202000 0 0x1000>;
+ ranges = <0x02000000 0 0xa0000000 0x0 0xa0000000 0 0x10000000
+ 0x01000000 0 0x00000000 0x0 0xff020000 0 0x00010000>;
+ pcie at 0 {
+ ranges = <0x02000000 0 0xa0000000
+ 0x02000000 0 0xa0000000
+ 0 0x10000000
+
+ 0x01000000 0 0x00000000
+ 0x01000000 0 0xff020000
+ 0 0x00010000>;
+ };
+ };
+
+ pci3: pcie at ffe203000 {
+ reg = <0xf 0xfe203000 0 0x1000>;
+ ranges = <0x02000000 0 0xb0000000 0x0 0xb0000000 0 0x08000000
+ 0x01000000 0 0x00000000 0x0 0xff030000 0 0x00010000>;
+ pcie at 0 {
+ ranges = <0x02000000 0 0xb0000000
+ 0x02000000 0 0xb0000000
+ 0 0x08000000
+
+ 0x01000000 0 0x00000000
+ 0x01000000 0 0xff030000
+ 0 0x00010000>;
+ };
+ };
+
+ fsl,dpaa {
+ compatible = "fsl,p3041-dpaa", "fsl,dpaa";
+
+ ethernet at 0 {
+ compatible = "fsl,p3041-dpa-ethernet", "fsl,dpa-ethernet";
+ fsl,qman-channel = <&qpool1>;
+ fsl,fman-mac = <&enet0>;
+ status="okay";
+ };
+ ethernet at 1 {
+ compatible = "fsl,p3041-dpa-ethernet", "fsl,dpa-ethernet";
+ fsl,qman-channel = <&qpool1>;
+ fsl,fman-mac = <&enet1>;
+ status = "disabled";
+ };
+ ethernet at 2 {
+ compatible = "fsl,p3041-dpa-ethernet", "fsl,dpa-ethernet";
+ fsl,qman-channel = <&qpool1>;
+ fsl,fman-mac = <&enet2>;
+ status = "disabled";
+ };
+ ethernet at 3 {
+ compatible = "fsl,p3041-dpa-ethernet", "fsl,dpa-ethernet";
+ fsl,qman-channel = <&qpool1>;
+ fsl,fman-mac = <&enet3>;
+ status = "disabled";
+ };
+ ethernet at 4 {
+ compatible = "fsl,p3041-dpa-ethernet", "fsl,dpa-ethernet";
+ fsl,qman-channel = <&qpool1>;
+ fsl,fman-mac = <&enet4>;
+ status = "okay";
+ };
+ ethernet at 5 {
+ compatible = "fsl,p3041-dpa-ethernet", "fsl,dpa-ethernet";
+ fsl,qman-channel = <&qpool1>;
+ fsl,fman-mac = <&enet5>;
+ status = "disabled";
+ };
+ };
+
+ chosen {
+ stdin = "serial0";
+ stdout = "serial0";
+ };
+};
Property changes on: trunk/sys/boot/fdt/dts/arm/p3041ds.dts
___________________________________________________________________
Added: svn:eol-style
## -0,0 +1 ##
+native
\ No newline at end of property
Added: svn:keywords
## -0,0 +1 ##
+MidnightBSD=%H
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+text/plain
\ No newline at end of property
Added: trunk/sys/boot/fdt/dts/arm/p5020ds.dts
===================================================================
--- trunk/sys/boot/fdt/dts/arm/p5020ds.dts (rev 0)
+++ trunk/sys/boot/fdt/dts/arm/p5020ds.dts 2018-06-02 12:34:49 UTC (rev 10205)
@@ -0,0 +1,584 @@
+/* $MidnightBSD$ */
+/*
+ * P5020DS Device Tree Source
+ *
+ * Copyright 2010-2011 Freescale Semiconductor Inc.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * * Neither the name of Freescale Semiconductor nor the
+ * names of its contributors may be used to endorse or promote products
+ * derived from this software without specific prior written permission.
+ *
+ *
+ * ALTERNATIVELY, this software may be distributed under the terms of the
+ * GNU General Public License ("GPL") as published by the Free Software
+ * Foundation, either version 2 of that License or (at your option) any
+ * later version.
+ *
+ * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+/* $FreeBSD: stable/10/sys/boot/fdt/dts/arm/p5020ds.dts 262614 2014-02-28 18:29:09Z imp $ */
+
+/include/ "p5020si.dtsi"
+
+/ {
+ model = "fsl,P5020DS";
+ compatible = "fsl,P5020DS";
+ #address-cells = <2>;
+ #size-cells = <2>;
+ interrupt-parent = <&mpic>;
+
+ aliases {
+ phy_rgmii_0 = &phy_rgmii_0;
+ phy_rgmii_1 = &phy_rgmii_1;
+ phy_sgmii_1c = &phy_sgmii_1c;
+ phy_sgmii_1d = &phy_sgmii_1d;
+ phy_sgmii_1e = &phy_sgmii_1e;
+ phy_sgmii_1f = &phy_sgmii_1f;
+ phy_xgmii_1 = &phy_xgmii_1;
+ phy_xgmii_2 = &phy_xgmii_2;
+ emi1_rgmii = &hydra_mdio_rgmii;
+ emi1_sgmii = &hydra_mdio_sgmii;
+ emi2_xgmii = &hydra_mdio_xgmii;
+ };
+
+ memory {
+ device_type = "memory";
+ reg = <0x00000000 0x00000000 0x00000000 0x80000000>;
+ };
+
+ dcsr: dcsr at f00000000 {
+ ranges = <0x00000000 0xf 0x00000000 0x01008000>;
+ };
+
+ bman-portals at ff4000000 {
+ bman-portal at 0 {
+ cpu-handle = <&cpu0>;
+ };
+ bman-portal at 4000 {
+ cpu-handle = <&cpu1>;
+ };
+ bman-portal at 8000 {
+ };
+ bman-portal at c000 {
+ };
+ bman-portal at 10000 {
+ };
+ bman-portal at 14000 {
+ };
+ bman-portal at 18000 {
+ };
+ bman-portal at 1c000 {
+ };
+ bman-portal at 20000 {
+ };
+ bman-portal at 24000 {
+ };
+
+ buffer-pool at 0 {
+ compatible = "fsl,p5020-bpool", "fsl,bpool";
+ fsl,bpid = <0>;
+ fsl,bpool-cfg = <0 0x100 0 1 0 0x100>;
+ };
+ };
+
+ qman-portals at ff4200000 {
+ qportal0: qman-portal at 0 {
+ cpu-handle = <&cpu0>;
+ fsl,qman-pool-channels = <&qpool1 &qpool2 &qpool3
+ &qpool4 &qpool5 &qpool6
+ &qpool7 &qpool8 &qpool9
+ &qpool10 &qpool11 &qpool12
+ &qpool13 &qpool14 &qpool15>;
+ };
+
+ qportal1: qman-portal at 4000 {
+ cpu-handle = <&cpu1>;
+ fsl,qman-pool-channels = <&qpool1 &qpool2 &qpool3
+ &qpool4 &qpool5 &qpool6
+ &qpool7 &qpool8 &qpool9
+ &qpool10 &qpool11 &qpool12
+ &qpool13 &qpool14 &qpool15>;
+ };
+
+ qportal2: qman-portal at 8000 {
+ fsl,qman-pool-channels = <&qpool1 &qpool2 &qpool3
+ &qpool4 &qpool5 &qpool6
+ &qpool7 &qpool8 &qpool9
+ &qpool10 &qpool11 &qpool12
+ &qpool13 &qpool14 &qpool15>;
+ };
+
+ qportal3: qman-portal at c000 {
+ fsl,qman-pool-channels = <&qpool1 &qpool2 &qpool3
+ &qpool4 &qpool5 &qpool6
+ &qpool7 &qpool8 &qpool9
+ &qpool10 &qpool11 &qpool12
+ &qpool13 &qpool14 &qpool15>;
+ };
+
+ qportal4: qman-portal at 10000 {
+ fsl,qman-pool-channels = <&qpool1 &qpool2 &qpool3
+ &qpool4 &qpool5 &qpool6
+ &qpool7 &qpool8 &qpool9
+ &qpool10 &qpool11 &qpool12
+ &qpool13 &qpool14 &qpool15>;
+ };
+
+ qportal5: qman-portal at 14000 {
+ fsl,qman-pool-channels = <&qpool1 &qpool2 &qpool3
+ &qpool4 &qpool5 &qpool6
+ &qpool7 &qpool8 &qpool9
+ &qpool10 &qpool11 &qpool12
+ &qpool13 &qpool14 &qpool15>;
+ };
+
+ qportal6: qman-portal at 18000 {
+ fsl,qman-pool-channels = <&qpool1 &qpool2 &qpool3
+ &qpool4 &qpool5 &qpool6
+ &qpool7 &qpool8 &qpool9
+ &qpool10 &qpool11 &qpool12
+ &qpool13 &qpool14 &qpool15>;
+ };
+
+ qportal7: qman-portal at 1c000 {
+ fsl,qman-pool-channels = <&qpool1 &qpool2 &qpool3
+ &qpool4 &qpool5 &qpool6
+ &qpool7 &qpool8 &qpool9
+ &qpool10 &qpool11 &qpool12
+ &qpool13 &qpool14 &qpool15>;
+ };
+
+ qportal8: qman-portal at 20000 {
+ fsl,qman-pool-channels = <&qpool1 &qpool2 &qpool3
+ &qpool4 &qpool5 &qpool6
+ &qpool7 &qpool8 &qpool9
+ &qpool10 &qpool11 &qpool12
+ &qpool13 &qpool14 &qpool15>;
+ };
+
+ qportal9: qman-portal at 24000 {
+ fsl,qman-pool-channels = <&qpool1 &qpool2 &qpool3
+ &qpool4 &qpool5 &qpool6
+ &qpool7 &qpool8 &qpool9
+ &qpool10 &qpool11 &qpool12
+ &qpool13 &qpool14 &qpool15>;
+ };
+ };
+
+ soc: soc at ffe000000 {
+ spi at 110000 {
+ flash at 0 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "spansion,s25sl12801";
+ reg = <0>;
+ spi-max-frequency = <40000000>; /* input clock */
+ partition at u-boot {
+ label = "u-boot";
+ reg = <0x00000000 0x00100000>;
+ read-only;
+ };
+ partition at kernel {
+ label = "kernel";
+ reg = <0x00100000 0x00500000>;
+ read-only;
+ };
+ partition at dtb {
+ label = "dtb";
+ reg = <0x00600000 0x00100000>;
+ read-only;
+ };
+ partition at fs {
+ label = "file system";
+ reg = <0x00700000 0x00900000>;
+ };
+ };
+ };
+
+ i2c at 118100 {
+ eeprom at 51 {
+ compatible = "at24,24c256";
+ reg = <0x51>;
+ };
+ eeprom at 52 {
+ compatible = "at24,24c256";
+ reg = <0x52>;
+ };
+ };
+
+ i2c at 119100 {
+ rtc at 68 {
+ compatible = "dallas,ds3232";
+ reg = <0x68>;
+ interrupts = <0x1 0x1 0 0>;
+ };
+ };
+
+ pme: pme at 316000 {
+ /* Commented out, use default allocation */
+ /* fsl,pme-pdsr = <0x0 0x23000000 0x0 0x01000000>; */
+ /* fsl,pme-sre = <0x0 0x24000000 0x0 0x00a00000>; */
+ };
+
+ qman: qman at 318000 {
+ /* Commented out, use default allocation */
+ /* fsl,qman-fqd = <0x0 0x20000000 0x0 0x01000000>; */
+ /* fsl,qman-pfdr = <0x0 0x21000000 0x0 0x01000000>; */
+ };
+
+ bman: bman at 31a000 {
+ /* Same as fsl,qman-*, use default allocation */
+ /* fsl,bman-fbpr = <0x0 0x22000000 0x0 0x01000000>; */
+ };
+
+ fman0: fman at 400000 {
+ enet0: ethernet at e0000 {
+ tbi-handle = <&tbi0>;
+ phy-handle = <&phy_rgmii_0>;
+ phy-connection-type = "rgmii";
+ };
+
+ mdio0: mdio at e1120 {
+ tbi0: tbi-phy at 8 {
+ reg = <0x8>;
+ device_type = "tbi-phy";
+ };
+
+ /*
+ * Virtual MDIO for the two on-board RGMII
+ * ports. The fsl,hydra-mdio-muxval property
+ * is already correct.
+ */
+ hydra_mdio_rgmii: hydra-mdio-rgmii {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "fsl,hydra-mdio";
+ fsl,mdio-handle = <&mdio0>;
+ fsl,hydra-mdio-muxval = <0x00>;
+ status = "disabled";
+
+ phy_rgmii_0: ethernet-phy at 0 {
+ reg = <0x0>;
+ };
+ phy_rgmii_1: ethernet-phy at 1 {
+ reg = <0x1>;
+ };
+ };
+
+ /*
+ * Virtual MDIO for the four-port SGMII card.
+ * The fsl,hydra-mdio-muxval property will be
+ * fixed-up by U-Boot based on the slot that
+ * the SGMII card is in.
+ *
+ * Note: we do not support DTSEC5 connected to
+ * SGMII, so this is the only SGMII node.
+ */
+ hydra_mdio_sgmii: hydra-mdio-sgmii {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "fsl,hydra-mdio";
+ fsl,mdio-handle = <&mdio0>;
+ fsl,hydra-mdio-muxval = <0x00>;
+ status = "disabled";
+
+ phy_sgmii_1c: ethernet-phy at 1c {
+ reg = <0x1c>;
+ };
+ phy_sgmii_1d: ethernet-phy at 1d {
+ reg = <0x1d>;
+ };
+ phy_sgmii_1e: ethernet-phy at 1e {
+ reg = <0x1e>;
+ };
+ phy_sgmii_1f: ethernet-phy at 1f {
+ reg = <0x1f>;
+ };
+ };
+ };
+
+ enet1: ethernet at e2000 {
+ tbi-handle = <&tbi1>;
+ phy-handle = <&phy_sgmii_1d>;
+ phy-connection-type = "sgmii";
+ };
+
+ mdio at e3120 {
+ tbi1: tbi-phy at 8 {
+ reg = <8>;
+ device_type = "tbi-phy";
+ };
+ };
+
+ enet2: ethernet at e4000 {
+ tbi-handle = <&tbi2>;
+ phy-handle = <&phy_sgmii_1e>;
+ phy-connection-type = "sgmii";
+ };
+
+ mdio at e5120 {
+ tbi2: tbi-phy at 8 {
+ reg = <8>;
+ device_type = "tbi-phy";
+ };
+ };
+
+ enet3: ethernet at e6000 {
+ tbi-handle = <&tbi3>;
+ phy-handle = <&phy_sgmii_1f>;
+ phy-connection-type = "sgmii";
+ };
+
+ mdio at e7120 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "fsl,fman-tbi";
+ reg = <0xe7120 0xee0>;
+ interrupts = <100 1 0 0>;
+
+ tbi3: tbi-phy at 8 {
+ reg = <8>;
+ device_type = "tbi-phy";
+ };
+ };
+
+ enet4: ethernet at e8000 {
+ tbi-handle = <&tbi4>;
+ phy-handle = <&phy_rgmii_1>;
+ phy-connection-type = "rgmii";
+ };
+
+ mdio at e9120 {
+ tbi4: tbi-phy at 8 {
+ reg = <8>;
+ device_type = "tbi-phy";
+ };
+ };
+
+ enet5: ethernet at f0000 {
+ /*
+ * phy-handle will be updated by U-Boot to
+ * reflect the actual slot the XAUI card is in.
+ */
+ phy-handle = <&phy_xgmii_1>;
+ phy-connection-type = "xgmii";
+ };
+
+ /*
+ * We only support one XAUI card, so the MDIO muxing
+ * is set by U-Boot, and Linux never touches it.
+ * Therefore, we don't need a virtual MDIO node.
+ * However, the phy address depends on the slot, so
+ * only one of the ethernet-phy nodes below will be
+ * used.
+ */
+ hydra_mdio_xgmii: mdio at f1000 {
+ status = "disabled";
+
+ /* XAUI card in slot 1 */
+ phy_xgmii_1: ethernet-phy at 4 {
+ reg = <0x4>;
+ };
+
+ /* XAUI card in slot 2 */
+ phy_xgmii_2: ethernet-phy at 0 {
+ reg = <0x0>;
+ };
+ };
+ };
+ };
+
+ rapidio at ffe0c0000 {
+ reg = <0xf 0xfe0c0000 0 0x11000>;
+
+ port1 {
+ ranges = <0 0 0xc 0x20000000 0 0x10000000>;
+ };
+ port2 {
+ ranges = <0 0 0xc 0x30000000 0 0x10000000>;
+ };
+ };
+
+ localbus at ffe124000 {
+ reg = <0xf 0xfe124000 0 0x1000>;
+ ranges = <0 0 0xf 0xb8000000 0x04000000>;
+
+ flash at 0,0 {
+ compatible = "cfi-flash";
+ /*
+ * Map 64Mb of 128MB NOR flash memory. Since highest
+ * line of address of NOR flash memory are set by
+ * FPGA, memory are divided into two pages equal to
+ * 64MB. One of the pages can be accessed at once.
+ */
+ reg = <0 0 0x04000000>;
+ bank-width = <2>;
+ device-width = <2>;
+ };
+
+ nand at 2,0 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "fsl,elbc-fcm-nand";
+ reg = <0x2 0x0 0x40000>;
+
+ partition at 0 {
+ label = "NAND U-Boot Image";
+ reg = <0x0 0x02000000>;
+ read-only;
+ };
+
+ partition at 2000000 {
+ label = "NAND Root File System";
+ reg = <0x02000000 0x10000000>;
+ };
+
+ partition at 12000000 {
+ label = "NAND Compressed RFS Image";
+ reg = <0x12000000 0x08000000>;
+ };
+
+ partition at 1a000000 {
+ label = "NAND Linux Kernel Image";
+ reg = <0x1a000000 0x04000000>;
+ };
+
+ partition at 1e000000 {
+ label = "NAND DTB Image";
+ reg = <0x1e000000 0x01000000>;
+ };
+
+ partition at 1f000000 {
+ label = "NAND Writable User area";
+ reg = <0x1f000000 0x21000000>;
+ };
+ };
+
+ board-control at 3,0 {
+ compatible = "fsl,p5020ds-fpga", "fsl,fpga-ngpixis";
+ reg = <3 0 0x30>;
+ };
+ };
+
+ pci0: pcie at ffe200000 {
+ reg = <0xf 0xfe200000 0 0x1000>;
+ ranges = <0x02000000 0 0x80000000 0x0 0x80000000 0x0 0x10000000
+ 0x01000000 0 0x00000000 0x0 0xff000000 0x0 0x00010000>;
+ pcie at 0 {
+ ranges = <0x02000000 0 0x80000000
+ 0x02000000 0 0x80000000
+ 0 0x10000000
+
+ 0x01000000 0 0x00000000
+ 0x01000000 0 0xff000000
+ 0 0x00010000>;
+ };
+ };
+
+ pci1: pcie at ffe201000 {
+ reg = <0xf 0xfe201000 0 0x1000>;
+ ranges = <0x02000000 0x0 0x90000000 0x0 0x90000000 0x0 0x10000000
+ 0x01000000 0x0 0x00000000 0x0 0xff010000 0x0 0x00010000>;
+ pcie at 0 {
+ ranges = <0x02000000 0 0x90000000
+ 0x02000000 0 0x90000000
+ 0 0x10000000
+
+ 0x01000000 0 0x00000000
+ 0x01000000 0 0xff010000
+ 0 0x00010000>;
+ };
+ };
+
+ pci2: pcie at ffe202000 {
+ reg = <0xf 0xfe202000 0 0x1000>;
+ ranges = <0x02000000 0 0xa0000000 0x0 0xa0000000 0 0x10000000
+ 0x01000000 0 0x00000000 0x0 0xff020000 0 0x00010000>;
+ pcie at 0 {
+ ranges = <0x02000000 0 0xa0000000
+ 0x02000000 0 0xa0000000
+ 0 0x10000000
+
+ 0x01000000 0 0x00000000
+ 0x01000000 0 0xff020000
+ 0 0x00010000>;
+ };
+ };
+
+ pci3: pcie at ffe203000 {
+ reg = <0xf 0xfe203000 0 0x1000>;
+ ranges = <0x02000000 0 0xb0000000 0x0 0xb0000000 0 0x08000000
+ 0x01000000 0 0x00000000 0x0 0xff030000 0 0x00010000>;
+ pcie at 0 {
+ ranges = <0x02000000 0 0xb0000000
+ 0x02000000 0 0xb0000000
+ 0 0x08000000
+
+ 0x01000000 0 0x00000000
+ 0x01000000 0 0xff030000
+ 0 0x00010000>;
+ };
+ };
+
+ fsl,dpaa {
+ compatible = "fsl,p5020-dpaa", "fsl,dpaa";
+
+ ethernet at 0 {
+ compatible = "fsl,p5020-dpa-ethernet", "fsl,dpa-ethernet";
+ fsl,qman-channel = <&qpool1>;
+ fsl,fman-mac = <&enet0>;
+ status = "okay";
+ };
+ ethernet at 1 {
+ compatible = "fsl,p5020-dpa-ethernet", "fsl,dpa-ethernet";
+ fsl,qman-channel = <&qpool1>;
+ fsl,fman-mac = <&enet1>;
+ status = "disabled";
+ };
+ ethernet at 2 {
+ compatible = "fsl,p5020-dpa-ethernet", "fsl,dpa-ethernet";
+ fsl,qman-channel = <&qpool1>;
+ fsl,fman-mac = <&enet2>;
+ status = "disabled";
+ };
+ ethernet at 3 {
+ compatible = "fsl,p5020-dpa-ethernet", "fsl,dpa-ethernet";
+ fsl,qman-channel = <&qpool1>;
+ fsl,fman-mac = <&enet3>;
+ status = "disabled";
+ };
+ ethernet at 4 {
+ compatible = "fsl,p5020-dpa-ethernet", "fsl,dpa-ethernet";
+ fsl,qman-channel = <&qpool1>;
+ fsl,fman-mac = <&enet4>;
+ status = "okay";
+ };
+ ethernet at 5 {
+ compatible = "fsl,p5020-dpa-ethernet", "fsl,dpa-ethernet";
+ fsl,qman-channel = <&qpool1>;
+ fsl,fman-mac = <&enet5>;
+ status = "disabled";
+ };
+ };
+
+ chosen {
+ stdin = "serial0";
+ stdout = "serial0";
+ };
+};
Property changes on: trunk/sys/boot/fdt/dts/arm/p5020ds.dts
___________________________________________________________________
Added: svn:eol-style
## -0,0 +1 ##
+native
\ No newline at end of property
Added: svn:keywords
## -0,0 +1 ##
+MidnightBSD=%H
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+text/plain
\ No newline at end of property
Added: trunk/sys/boot/fdt/dts/arm/pandaboard.dts
===================================================================
--- trunk/sys/boot/fdt/dts/arm/pandaboard.dts (rev 0)
+++ trunk/sys/boot/fdt/dts/arm/pandaboard.dts 2018-06-02 12:34:49 UTC (rev 10205)
@@ -0,0 +1,187 @@
+/* $MidnightBSD$ */
+/*-
+ * Copyright (c) 2011 The FreeBSD Foundation
+ * All rights reserved.
+ *
+ * Developed by Damjan Marion <damjan.marion at gmail.com>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ * $FreeBSD: stable/10/sys/boot/fdt/dts/arm/pandaboard.dts 266751 2014-05-27 15:30:24Z ian $
+ */
+
+/dts-v1/;
+
+/ {
+ model = "pandaboard";
+ compatible = "pandaboard", "ti,omap4430";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ interrupt-parent = <&GIC>;
+
+ aliases {
+ soc = &SOC;
+ uart3 = &uart3;
+ };
+
+ memory {
+ device_type = "memory";
+ reg = < 0x80000000 0x40000000 >; /* 1GB RAM at 0x0 */
+ };
+
+ SOC: omap4430 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "simple-bus";
+ ranges;
+ bus-frequency = <0>;
+
+ GIC: interrupt-controller at 48241000 {
+ compatible = "arm,gic";
+ interrupt-controller;
+ #address-cells = <0>;
+ #interrupt-cells = <1>;
+ reg = < 0x48241000 0x1000 >, /* Distributor Registers */
+ < 0x48240100 0x0100 >; /* CPU Interface Registers */
+ };
+
+ omap4_prcm at 4a306000 {
+ compatible = "ti,omap4_prcm";
+ reg =< 0x4a306000 0x2000
+ 0x4a004000 0x1000
+ 0x4a008000 0x8000>;
+ };
+
+ pl310 at 48242000 {
+ compatible = "arm,pl310";
+ reg = < 0x48242000 0x1000 >;
+ interrupts = < 32 >;
+ interrupt-parent = < &GIC >;
+ };
+ mp_tmr at 48240200 {
+ compatible = "arm,mpcore-timers";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = < 0x48240200 0x100 >, /* Global Timer Registers */
+ < 0x48240600 0x100 >; /* Private Timer Registers */
+ interrupts = < 27 29 >;
+ interrupt-parent = < &GIC >;
+ };
+
+ uart3: serial at 48020000 {
+ compatible = "ns16550";
+ reg = <0x48020000 0x1000>;
+ reg-shift = <2>;
+ interrupts = < 106 >;
+ interrupt-parent = <&GIC>;
+ clock-frequency = < 48000000 >; /* 48Mhz clock for all uarts */
+ /* (techref 17.3.1.1) */
+ };
+
+ scm at 4a100000 {
+ compatible = "ti,scm";
+ reg = < 0x4a100000 0x1000 >;
+ /* Set of triplets < padname, muxname, padstate> */
+ scm-pad-config =
+ "ag19", "usbb1_ulpiphy_stp", "output",
+ "ae18", "usbb1_ulpiphy_clk", "input_pulldown",
+ "af19", "usbb1_ulpiphy_dir", "input_pulldown",
+ "ae19", "usbb1_ulpiphy_nxt", "input_pulldown",
+ "af18", "usbb1_ulpiphy_dat0", "input_pulldown",
+ "ag18", "usbb1_ulpiphy_dat1", "input_pulldown",
+ "ae17", "usbb1_ulpiphy_dat2", "input_pulldown",
+ "af17", "usbb1_ulpiphy_dat3", "input_pulldown",
+ "ah17", "usbb1_ulpiphy_dat4", "input_pulldown",
+ "ae16", "usbb1_ulpiphy_dat5", "input_pulldown",
+ "af16", "usbb1_ulpiphy_dat6", "input_pulldown",
+ "ag16", "usbb1_ulpiphy_dat7", "input_pulldown";
+ };
+
+ GPIO: gpio {
+ #gpio-cells = <3>;
+ compatible = "ti,gpio";
+ gpio-controller;
+ reg =< 0x4a310000 0x1000
+ 0x48055000 0x1000
+ 0x48057000 0x1000
+ 0x48059000 0x1000
+ 0x4805b000 0x1000
+ 0x4805d000 0x1000>;
+ interrupts = <61 62 63 64 65 66>;
+ interrupt-parent = <&GIC>;
+ };
+
+ ehci {
+ compatible = "ti,usb-ehci", "usb-ehci";
+ /*
+ * USB port PHY configuration is a tuple: <mode, reset, gpio_pin>
+ * mode is one of the following values:
+ * 0 - unknown
+ * 1 - PHY
+ * 2 - TLL
+ * 3 - HSIC
+ *
+ * reset indicates (if non-zero) if port reset is required
+ * gpio_pin - GPIO pin that is used to perform reset
+ */
+ phy-config = < 1 0 0
+ 0 0 0
+ 0 0 0>;
+ reg = < 0x4a064c00 0x100 /* EHCI regs */
+ 0x4a064000 0x700 /* UHH regs */
+ 0x4a062000 0x1000>; /* TLL regs */
+ interrupts = <109>;
+ interrupt-parent = <&GIC>;
+ };
+
+ I2C1: i2c at x48070000 {
+ compatible = "ti,i2c";
+ reg =< 0x48070000 0x100 >;
+ interrupts = <88>;
+ interrupt-parent = <&GIC>;
+ i2c-device-id = <1>;
+ };
+
+ sdma at x48070000 {
+ compatible = "ti,sdma";
+ reg =< 0x4A056000 0x1000 >;
+ interrupts = <44 45 46 47>;
+ interrupt-parent = <&GIC>;
+ };
+
+ mmc at x4809C000 {
+ compatible = "ti,mmchs";
+ reg =<0x4809C000 0x1000 >;
+ interrupts = <115>;
+ interrupt-parent = <&GIC>;
+ mmchs-device-id = <1>;
+ non-removable; /* XXX need real solution */
+ };
+
+ };
+
+ chosen {
+ stdin = "uart3";
+ stdout = "uart3";
+ };
+};
Property changes on: trunk/sys/boot/fdt/dts/arm/pandaboard.dts
___________________________________________________________________
Added: svn:eol-style
## -0,0 +1 ##
+native
\ No newline at end of property
Added: svn:keywords
## -0,0 +1 ##
+MidnightBSD=%H
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+text/plain
\ No newline at end of property
Added: trunk/sys/boot/fdt/dts/arm/rk3188-radxa.dts
===================================================================
--- trunk/sys/boot/fdt/dts/arm/rk3188-radxa.dts (rev 0)
+++ trunk/sys/boot/fdt/dts/arm/rk3188-radxa.dts 2018-06-02 12:34:49 UTC (rev 10205)
@@ -0,0 +1,60 @@
+/* $MidnightBSD$ */
+/*-
+ * Copyright (c) 2013 Ganbold Tsagaankhuu <ganbold at freebsd.org>
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ * $FreeBSD: stable/10/sys/boot/fdt/dts/arm/rk3188-radxa.dts 266337 2014-05-17 18:53:36Z ian $
+ */
+
+/dts-v1/;
+
+/include/ "rk3188.dtsi"
+
+/ {
+ model = "Radxa RadxaRock";
+
+ memory {
+ device_type = "memory";
+ reg = < 0x60000000 0x80000000 >; /* 2GB RAM */
+ };
+
+ aliases {
+ soc = &SOC;
+ };
+
+ SOC: rk3188 {
+
+ uart2: serial at 20064000 {
+ status = "okay";
+ };
+
+ };
+
+ chosen {
+ bootargs = "-v";
+ stdin = &uart2;
+ stdout = &uart2;
+ };
+};
+
Property changes on: trunk/sys/boot/fdt/dts/arm/rk3188-radxa.dts
___________________________________________________________________
Added: svn:eol-style
## -0,0 +1 ##
+native
\ No newline at end of property
Added: svn:keywords
## -0,0 +1 ##
+MidnightBSD=%H
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+text/plain
\ No newline at end of property
Added: trunk/sys/boot/fdt/dts/arm/rk3188.dtsi
===================================================================
--- trunk/sys/boot/fdt/dts/arm/rk3188.dtsi (rev 0)
+++ trunk/sys/boot/fdt/dts/arm/rk3188.dtsi 2018-06-02 12:34:49 UTC (rev 10205)
@@ -0,0 +1,255 @@
+/* $MidnightBSD$ */
+/*-
+ * Copyright (c) 2013 Ganbold Tsagaankhuu <ganbold at freebsd.org>
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ * $FreeBSD: stable/10/sys/boot/fdt/dts/arm/rk3188.dtsi 266397 2014-05-18 13:05:07Z ian $
+ */
+
+/ {
+ compatible = "rockchip,rk3188";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ interrupt-parent = <&GIC>;
+
+ aliases {
+ soc = &SOC;
+ };
+
+ SOC: rk3188 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "simple-bus";
+ ranges;
+ bus-frequency = <0>;
+
+ GIC: interrupt-controller at 1013d000 {
+ compatible = "arm,gic";
+ reg = <0x1013d000 0x1000>, /* Distributor Registers */
+ <0x1013c100 0x0100>; /* CPU Interface Registers */
+ interrupt-controller;
+ #interrupt-cells = <1>;
+ };
+
+ pmu at 20004000 {
+ compatible = "rockchip,rk30xx-pmu";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ reg = <0x20004000 0x100>;
+ };
+
+ grf at 20008000 {
+ compatible = "rockchip,rk30xx-grf";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ reg = < 0x20008000 0x2000 >;
+ };
+
+ mp_tmr at 1013c600 {
+ compatible = "arm,mpcore-timers";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clock-frequency = < 148500000 >;
+ reg = <0x1013c200 0x100>, /* Global Timer Regs */
+ <0x1013c600 0x20>; /* Private Timer Regs */
+ interrupts = < 27 29 >;
+ interrupt-parent = <&GIC>;
+ };
+
+ timer at 20038000 {
+ compatible = "rockchip,rk30xx-timer";
+ reg = <0x20038000 0x20>;
+ interrupts = <76>;
+ clock-frequency = <24000000>;
+ status = "disabled";
+ };
+
+ timer at 20038020 {
+ compatible = "rockchip,rk30xx-timer";
+ reg = <0x20038020 0x20>;
+ interrupts = <77>;
+ clock-frequency = <24000000>;
+ status = "disabled";
+ };
+
+ timer at 20038060 {
+ compatible = "rockchip,rk30xx-timer";
+ reg = <0x20038060 0x20>;
+ interrupts = <91>;
+ clock-frequency = <24000000>;
+ status = "disabled";
+ };
+
+ timer at 20038080 {
+ compatible = "rockchip,rk30xx-timer";
+ reg = <0x20038080 0x20>;
+ interrupts = <92>;
+ clock-frequency = <24000000>;
+ status = "disabled";
+ };
+
+ timer at 200380a0 {
+ compatible = "rockchip,rk30xx-timer";
+ reg = <0x200380a0 0x20>;
+ interrupts = <96>;
+ clock-frequency = <24000000>;
+ status = "disabled";
+ };
+
+ watchdog at 2004c000 {
+ compatible = "rockchip,rk30xx-wdt";
+ reg = <0x2004c000 0x100>;
+ clock-frequency = < 66000000 >;
+ };
+
+ gpio0: gpio at 2000a000 {
+ compatible = "rockchip,rk30xx-gpio";
+ gpio-controller;
+ #gpio-cells = <2>;
+ reg = <0x2000a000 0x100>;
+ interrupts = <86>;
+ interrupt-parent = <&GIC>;
+ };
+
+ gpio1: gpio at 2003c000 {
+ compatible = "rockchip,rk30xx-gpio";
+ gpio-controller;
+ #gpio-cells = <2>;
+ reg = <0x2003c000 0x100>;
+ interrupts = <87>;
+ interrupt-parent = <&GIC>;
+ };
+
+ gpio2: gpio at 2003e000 {
+ compatible = "rockchip,rk30xx-gpio";
+ gpio-controller;
+ #gpio-cells = <2>;
+ reg = <0x2003e000 0x100>;
+ interrupts = <88>;
+ interrupt-parent = <&GIC>;
+ };
+
+ gpio3: gpio at 20080000 {
+ compatible = "rockchip,rk30xx-gpio";
+ gpio-controller;
+ #gpio-cells = <2>;
+ reg = <0x20080000 0x100>;
+ interrupts = <89>;
+ interrupt-parent = <&GIC>;
+ };
+
+ usb0: usb at 10180000 {
+ compatible = "synopsys,designware-hs-otg2";
+ reg = <0x10180000 0x40000>;
+ interrupts = <48>;
+ interrupt-parent = <&GIC>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ usb1: usb at 101c0000 {
+ compatible = "synopsys,designware-hs-otg2";
+ reg = <0x101c0000 0x40000>;
+ interrupts = < 49 >;
+ interrupt-parent = <&GIC>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ gpios = <&gpio0 3 2 2>;
+ };
+
+ uart0: serial at 10124000 {
+ compatible = "ns16550";
+ reg = <0x10124000 0x400>;
+ reg-shift = <2>;
+ interrupts = <66>;
+ interrupt-parent = <&GIC>;
+ current-speed = <115200>;
+ clock-frequency = < 24000000 >;
+ busy-detect = <1>;
+ broken-txfifo = <1>;
+ status = "disabled";
+ };
+
+ uart1: serial at 10126000 {
+ compatible = "ns16550";
+ reg = <0x10126000 0x400>;
+ reg-shift = <2>;
+ interrupts = <67>;
+ interrupt-parent = <&GIC>;
+ current-speed = <115200>;
+ clock-frequency = < 24000000 >;
+ busy-detect = <1>;
+ broken-txfifo = <1>;
+ status = "disabled";
+ };
+
+ uart2: serial at 20064000 {
+ compatible = "ns16550";
+ reg = <0x20064000 0x400>;
+ reg-shift = <2>;
+ interrupts = <68>;
+ interrupt-parent = <&GIC>;
+ current-speed = <115200>;
+ clock-frequency = < 24000000 >;
+ busy-detect = <1>;
+ broken-txfifo = <1>;
+ status = "disabled";
+ };
+
+ uart3: serial at 20068000 {
+ compatible = "ns16550";
+ reg = <0x20068000 0x400>;
+ reg-shift = <2>;
+ interrupts = <69>;
+ interrupt-parent = <&GIC>;
+ current-speed = <115200>;
+ clock-frequency = < 24000000 >;
+ busy-detect = <1>;
+ broken-txfifo = <1>;
+ status = "disabled";
+ };
+
+ mmc at 10214000 {
+ compatible = "rockchip,rk30xx-mmc";
+ reg = <0x10214000 0x1000>;
+ interrupts = <55>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clock-frequency = <24000000>; /* TODO: verify freq */
+ status = "disabled";
+ };
+
+ mmc at 10218000 {
+ compatible = "rockchip,rk30xx-mmc";
+ reg = <0x10218000 0x1000>;
+ interrupts = <56>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clock-frequency = <24000000>; /* TODO: verify freq */
+ status = "disabled";
+ };
+ };
+};
+
Property changes on: trunk/sys/boot/fdt/dts/arm/rk3188.dtsi
___________________________________________________________________
Added: svn:eol-style
## -0,0 +1 ##
+native
\ No newline at end of property
Added: svn:keywords
## -0,0 +1 ##
+MidnightBSD=%H
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+text/plain
\ No newline at end of property
Added: trunk/sys/boot/fdt/dts/arm/rpi.dts
===================================================================
--- trunk/sys/boot/fdt/dts/arm/rpi.dts (rev 0)
+++ trunk/sys/boot/fdt/dts/arm/rpi.dts 2018-06-02 12:34:49 UTC (rev 10205)
@@ -0,0 +1,393 @@
+/* $MidnightBSD$ */
+/*
+ * Copyright (c) 2012 Oleksandr Tymoshenko <gonzo at bluezbox.com>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ * $FreeBSD: stable/10/sys/boot/fdt/dts/arm/rpi.dts 278608 2015-02-12 00:25:33Z ian $
+ */
+/dts-v1/;
+
+/include/ "bcm2835.dtsi"
+
+/ {
+ model = "Raspberry Pi (BCM2835)";
+ compatible = "raspberrypi,model-a", "raspberrypi,model-b",
+ "broadcom,bcm2835-vc", "broadcom,bcm2708-vc";
+
+ memreserve = <0x08000000 0x08000000>; /* Set by VideoCore */
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ cpu at 0 {
+ compatible = "arm,1176jzf-s";
+ device_type = "cpu";
+ reg = <0>; /* CPU ID=0 */
+ clock-frequency = <700000000>; /* 700MHz */
+ };
+ };
+
+ memory {
+ device_type = "memory";
+ reg = <0 0x8000000>; /* 128MB, Set by VideoCore */
+
+ };
+
+ system {
+ revision = <0>; /* Set by VideoCore */
+ serial = <0 0>; /* Set by VideoCore */
+ };
+
+ axi {
+ gpio: gpio {
+ /* BSC0 */
+ pins_bsc0_a: bsc0_a {
+ broadcom,function = "ALT0";
+ };
+
+ pins_bsc0_b: bsc0_b {
+ broadcom,function = "ALT0";
+ };
+
+ pins_bsc0_c: bsc0_c {
+ broadcom,function = "ALT1";
+ };
+
+ /* BSC1 */
+ pins_bsc1_a: bsc1_a {
+ broadcom,function = "ALT0";
+ };
+
+ pins_bsc1_b: bsc1_b {
+ broadcom,function = "ALT2";
+ };
+
+ /* GPCLK0 */
+ pins_gpclk0_a: gpclk0_a {
+ broadcom,function = "ALT0";
+ };
+
+ pins_gpclk0_b: gpclk0_b {
+ broadcom,function = "ALT5";
+ };
+
+ pins_gpclk0_c: gpclk0_c {
+ broadcom,function = "ALT0";
+ };
+
+ pins_gpclk0_d: gpclk0_d {
+ broadcom,function = "ALT0";
+ };
+
+ /* GPCLK1 */
+ pins_gpclk1_a: gpclk1_a {
+ broadcom,function = "ALT0";
+ };
+
+ pins_gpclk1_b: gpclk1_b {
+ broadcom,function = "ALT5";
+ };
+
+ pins_gpclk1_c: gpclk1_c {
+ broadcom,function = "ALT0";
+ };
+
+ pins_gpclk1_d: gpclk1_d {
+ broadcom,function = "ALT0";
+ };
+
+ /* GPCLK2 */
+ pins_gpclk2_a: gpclk2_a {
+ broadcom,function = "ALT0";
+ };
+
+ pins_gpclk2_b: gpclk2_b {
+ broadcom,function = "ALT0";
+ };
+
+ /* SPI0 */
+ pins_spi0_a: spi0_a {
+ broadcom,function = "ALT0";
+ };
+
+ pins_spi0_b: spi0_b {
+ broadcom,function = "ALT0";
+ };
+
+ /* PWM */
+ pins_pwm0_a: pwm0_a {
+ broadcom,function = "ALT0";
+ };
+
+ pins_pwm0_b: pwm0_b {
+ broadcom,function = "ALT5";
+ };
+
+ pins_pwm0_c: pwm0_c {
+ broadcom,function = "ALT0";
+ };
+
+ pins_pwm1_a: pwm1_a {
+ broadcom,function = "ALT0";
+ };
+
+ pins_pwm1_b: pwm1_b {
+ broadcom,function = "ALT5";
+ };
+
+ pins_pwm1_c: pwm1_c {
+ broadcom,function = "ALT0";
+ };
+
+ pins_pwm1_d: pwm1_d {
+ broadcom,function = "ALT0";
+ };
+
+ /* UART0 */
+ pins_uart0_a: uart0_a {
+ broadcom,function = "ALT0";
+ };
+
+ pins_uart0_b: uart0_b {
+ broadcom,function = "ALT3";
+ };
+
+ pins_uart0_c: uart0_c {
+ broadcom,function = "ALT2";
+ };
+
+ pins_uart0_fc_a: uart0_fc_a {
+ broadcom,function = "ALT3";
+ };
+
+ pins_uart0_fc_b: uart0_fc_b {
+ broadcom,function = "ALT3";
+ };
+
+ pins_uart0_fc_c: uart0_fc_c {
+ broadcom,function = "ALT2";
+ };
+
+ /* PCM */
+ pins_pcm_a: pcm_a {
+ broadcom,function = "ALT0";
+ };
+
+ pins_pcm_b: pcm_b {
+ broadcom,function = "ALT2";
+ };
+
+ /* Secondary Address Bus */
+ pins_sm_addr_a: sm_addr_a {
+ broadcom,function = "ALT1";
+ };
+
+ pins_sm_addr_b: sm_addr_b {
+ broadcom,function = "ALT1";
+ };
+
+ pins_sm_ctl_a: sm_ctl_a {
+ broadcom,function = "ALT1";
+ };
+
+ pins_sm_ctl_b: sm_ctl_b {
+ broadcom,function = "ALT1";
+ };
+
+ pins_sm_data_8bit_a: sm_data_8bit_a {
+ broadcom,function = "ALT1";
+ };
+
+ pins_sm_data_8bit_b: sm_data_8bit_b {
+ broadcom,function = "ALT1";
+ };
+
+ pins_sm_data_16bit: sm_data_16bit {
+ broadcom,function = "ALT1";
+ };
+
+ pins_sm_data_18bit: sm_data_18bit {
+ broadcom,function = "ALT1";
+ };
+
+ /* BSCSL */
+ pins_bscsl: bscsl {
+ broadcom,function = "ALT3";
+ };
+
+ /* SPISL */
+ pins_spisl: spisl {
+ broadcom,function = "ALT3";
+ };
+
+ /* SPI1 */
+ pins_spi1: spi1 {
+ broadcom,function = "ALT4";
+ };
+
+ /* UART1 */
+ pins_uart1_a: uart1_a {
+ broadcom,function = "ALT5";
+ };
+
+ pins_uart1_b: uart1_b {
+ broadcom,function = "ALT5";
+ };
+
+ pins_uart1_c: uart1_c {
+ broadcom,function = "ALT5";
+ };
+
+ pins_uart1_fc_a: uart1_fc_a {
+ broadcom,function = "ALT5";
+ };
+
+ pins_uart1_fc_b: uart1_fc_b {
+ broadcom,function = "ALT5";
+ };
+
+ pins_uart1_fc_c: uart1_fc_c {
+ broadcom,function = "ALT5";
+ };
+
+ /* SPI2 */
+ pins_spi2: spi2 {
+ broadcom,function = "ALT4";
+ };
+
+ /* ARM JTAG */
+ pins_arm_jtag_trst: arm_jtag_trst {
+ broadcom,function = "ALT4";
+ };
+
+ pins_arm_jtag_a: arm_jtag_a {
+ broadcom,function = "ALT5";
+ };
+
+ pins_arm_jtag_b: arm_jtag_b {
+ broadcom,function = "ALT4";
+ };
+
+ /* Reserved */
+ pins_reserved: reserved {
+ broadcom,function = "ALT3";
+ };
+ };
+ usb {
+ hub {
+ compatible = "usb,hub", "usb,device";
+ reg = <0x00000001>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ ethernet {
+ compatible = "net,ethernet",
+ "usb,device";
+ reg = <0x00000001>;
+ mac-address = [00 00 00 00 00 00];
+ };
+ };
+
+ };
+
+
+ };
+
+ display {
+ compatible = "broadcom,bcm2835-fb", "broadcom,bcm2708-fb";
+
+ broadcom,vc-mailbox = <&vc_mbox>;
+ broadcom,vc-channel = <1>;
+
+ broadcom,width = <0>; /* Set by VideoCore */
+ broadcom,height = <0>; /* Set by VideoCore */
+ broadcom,depth = <0>; /* Set by VideoCore */
+ };
+
+ leds {
+ compatible = "gpio-leds";
+
+ ok {
+ label = "ok";
+ gpios = <&gpio 16 1>;
+
+ /* Don't change this - it configures
+ * how the led driver determines if
+ * the led is on or off when it loads.
+ */
+ default-state = "keep";
+
+ /* This is the real default state. */
+ linux,default-trigger = "default-on";
+ };
+ };
+
+ power: regulator {
+ compatible = "broadcom,bcm2835-power-mgr",
+ "broadcom,bcm2708-power-mgr",
+ "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ broadcom,vc-mailbox = <&vc_mbox>;
+ broadcom,vc-channel = <0>;
+
+ regulator-name = "VideoCore";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ regulator-always-on = <1>;
+
+ sd_card_power: regulator at 0 {
+ compatible = "broadcom,bcm2835-power-dev",
+ "broadcom,bcm2708-power-dev";
+ reg = <0>;
+
+ vin-supply = <&power>;
+ regulator-name = "SD Card";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ };
+
+ /* This is for the controller itself, not the root port */
+ usb_hcd_power: regulator at 3 {
+ compatible = "broadcom,bcm2835-power-dev",
+ "broadcom,bcm2708-power-dev";
+ reg = <3>;
+
+ vin-supply = <&power>;
+ regulator-name = "USB HCD";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ };
+ };
+
+ aliases {
+ uart0 = &uart0;
+ };
+
+ chosen {
+ bootargs = ""; /* Set by VideoCore */
+ stdin = "uart0";
+ stdout = "uart0";
+ };
+
+};
Property changes on: trunk/sys/boot/fdt/dts/arm/rpi.dts
___________________________________________________________________
Added: svn:eol-style
## -0,0 +1 ##
+native
\ No newline at end of property
Added: svn:keywords
## -0,0 +1 ##
+MidnightBSD=%H
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+text/plain
\ No newline at end of property
Added: trunk/sys/boot/fdt/dts/arm/sheevaplug.dts
===================================================================
--- trunk/sys/boot/fdt/dts/arm/sheevaplug.dts (rev 0)
+++ trunk/sys/boot/fdt/dts/arm/sheevaplug.dts 2018-06-02 12:34:49 UTC (rev 10205)
@@ -0,0 +1,253 @@
+/* $MidnightBSD$ */
+/*
+ * Copyright (c) 2010 The FreeBSD Foundation
+ * All rights reserved.
+ *
+ * This software was developed by Semihalf under sponsorship from
+ * the FreeBSD Foundation.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ * Marvell SheevaPlug Device Tree Source.
+ *
+ * $FreeBSD: stable/10/sys/boot/fdt/dts/arm/sheevaplug.dts 262614 2014-02-28 18:29:09Z imp $
+ */
+
+/dts-v1/;
+
+/ {
+ model = "mrvl,SheevaPlug";
+ compatible = "SheevaPlug";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ aliases {
+ ethernet0 = &enet0;
+ mpp = &MPP;
+ serial0 = &serial0;
+ serial1 = &serial1;
+ soc = &SOC;
+ sram = &SRAM;
+ };
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cpu at 0 {
+ device_type = "cpu";
+ compatible = "ARM,88FR131";
+ reg = <0x0>;
+ d-cache-line-size = <32>; // 32 bytes
+ i-cache-line-size = <32>; // 32 bytes
+ d-cache-size = <0x4000>; // L1, 16K
+ i-cache-size = <0x4000>; // L1, 16K
+ timebase-frequency = <0>;
+ bus-frequency = <0>;
+ clock-frequency = <0>;
+ };
+ };
+
+ memory {
+ device_type = "memory";
+ reg = <0x0 0x20000000>; // 512M at 0x0
+ };
+
+ localbus at 0 {
+ #address-cells = <2>;
+ #size-cells = <1>;
+ compatible = "mrvl,lbc";
+ bank-count = <3>;
+
+ /* This reflects CPU decode windows setup. */
+ ranges = <0x0 0x2f 0xf9300000 0x00100000>;
+
+ nand at 0,0 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "mrvl,nfc";
+ reg = <0x0 0x0 0x00100000>;
+ bank-width = <2>;
+ device-width = <1>;
+
+ slice at 0 {
+ reg = <0x0 0x200000>;
+ label = "u-boot";
+ read-only;
+ };
+
+ slice at 200000 {
+ reg = <0x200000 0x1fe00000>;
+ label = "root";
+ };
+ };
+ };
+
+ SOC: soc88f6281 at f1000000 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "simple-bus";
+ ranges = <0x0 0xf1000000 0x00100000>;
+ bus-frequency = <0>;
+
+ PIC: pic at 20200 {
+ interrupt-controller;
+ #address-cells = <0>;
+ #interrupt-cells = <1>;
+ reg = <0x20200 0x3c>;
+ compatible = "mrvl,pic";
+ };
+
+ timer at 20300 {
+ compatible = "mrvl,timer";
+ reg = <0x20300 0x30>;
+ interrupts = <1>;
+ interrupt-parent = <&PIC>;
+ mrvl,has-wdt;
+ };
+
+ MPP: mpp at 10000 {
+ #pin-cells = <2>;
+ compatible = "mrvl,mpp";
+ reg = <0x10000 0x34>;
+ pin-count = <50>;
+ pin-map = <
+ 0 1 /* MPP[0]: NF_IO[2] */
+ 1 1 /* MPP[1]: NF_IO[3] */
+ 2 1 /* MPP[2]: NF_IO[4] */
+ 3 1 /* MPP[3]: NF_IO[5] */
+ 4 1 /* MPP[4]: NF_IO[6] */
+ 5 1 /* MPP[5]: NF_IO[7] */
+ 6 1 /* MPP[6]: SYSRST_OUTn */
+ 8 2 /* MPP[8]: UA0_RTS */
+ 9 2 /* MPP[9]: UA0_CTS */
+ 10 3 /* MPP[10]: UA0_TXD */
+ 11 3 /* MPP[11]: UA0_RXD */
+ 12 1 /* MPP[12]: SD_CLK */
+ 13 1 /* MPP[13]: SD_CMD */
+ 14 1 /* MPP[14]: SD_D[0] */
+ 15 1 /* MPP[15]: SD_D[1] */
+ 16 1 /* MPP[16]: SD_D[2] */
+ 17 1 /* MPP[17]: SD_D[3] */
+ 18 1 /* MPP[18]: NF_IO[0] */
+ 19 1 /* MPP[19]: NF_IO[1] */
+ 29 1 >; /* MPP[29]: TSMP[9] */
+ };
+
+ GPIO: gpio at 10100 {
+ #gpio-cells = <3>;
+ compatible = "mrvl,gpio";
+ reg = <0x10100 0x20>;
+ gpio-controller;
+ interrupts = <35 36 37 38 39 40 41>;
+ interrupt-parent = <&PIC>;
+ };
+
+ rtc at 10300 {
+ compatible = "mrvl,rtc";
+ reg = <0x10300 0x08>;
+ };
+
+ twsi at 11000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "mrvl,twsi";
+ reg = <0x11000 0x20>;
+ interrupts = <43>;
+ interrupt-parent = <&PIC>;
+ };
+
+ enet0: ethernet at 72000 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ model = "V2";
+ compatible = "mrvl,ge";
+ reg = <0x72000 0x2000>;
+ ranges = <0x0 0x72000 0x2000>;
+ local-mac-address = [ 00 00 00 00 00 00 ];
+ interrupts = <12 13 14 11 46>;
+ interrupt-parent = <&PIC>;
+ phy-handle = <&phy0>;
+
+ mdio at 0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "mrvl,mdio";
+
+ phy0: ethernet-phy at 0 {
+ reg = <0x0>;
+ };
+ };
+ };
+
+ serial0: serial at 12000 {
+ compatible = "ns16550";
+ reg = <0x12000 0x20>;
+ reg-shift = <2>;
+ clock-frequency = <0>;
+ interrupts = <33>;
+ interrupt-parent = <&PIC>;
+ };
+
+ serial1: serial at 12100 {
+ compatible = "ns16550";
+ reg = <0x12100 0x20>;
+ reg-shift = <2>;
+ clock-frequency = <0>;
+ interrupts = <34>;
+ interrupt-parent = <&PIC>;
+ };
+
+ crypto at 30000 {
+ compatible = "mrvl,cesa";
+ reg = <0x30000 0x10000>;
+ interrupts = <22>;
+ interrupt-parent = <&PIC>;
+
+ sram-handle = <&SRAM>;
+ };
+
+ usb at 50000 {
+ compatible = "mrvl,usb-ehci", "usb-ehci";
+ reg = <0x50000 0x1000>;
+ interrupts = <48 19>;
+ interrupt-parent = <&PIC>;
+ };
+
+ xor at 60000 {
+ compatible = "mrvl,xor";
+ reg = <0x60000 0x1000>;
+ interrupts = <5 6 7 8>;
+ interrupt-parent = <&PIC>;
+ };
+ };
+
+ SRAM: sram at fd000000 {
+ compatible = "mrvl,cesa-sram";
+ reg = <0xfd000000 0x00100000>;
+ };
+
+ chosen {
+ stdin = "serial0";
+ stdout = "serial0";
+ };
+};
Property changes on: trunk/sys/boot/fdt/dts/arm/sheevaplug.dts
___________________________________________________________________
Added: svn:eol-style
## -0,0 +1 ##
+native
\ No newline at end of property
Added: svn:keywords
## -0,0 +1 ##
+MidnightBSD=%H
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+text/plain
\ No newline at end of property
Added: trunk/sys/boot/fdt/dts/arm/sun4i-a10.dtsi
===================================================================
--- trunk/sys/boot/fdt/dts/arm/sun4i-a10.dtsi (rev 0)
+++ trunk/sys/boot/fdt/dts/arm/sun4i-a10.dtsi 2018-06-02 12:34:49 UTC (rev 10205)
@@ -0,0 +1,134 @@
+/* $MidnightBSD$ */
+/*-
+ * Copyright (c) 2014 Ganbold Tsagaankhuu <ganbold at freebsd.org>
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ * $FreeBSD: stable/10/sys/boot/fdt/dts/arm/sun4i-a10.dtsi 266376 2014-05-17 23:16:18Z ian $
+ */
+
+/ {
+ compatible = "allwinner,sun4i-a10";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ interrupt-parent = <&AINTC>;
+
+ aliases {
+ soc = &SOC;
+ };
+
+ SOC: a10 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "simple-bus";
+ ranges;
+ bus-frequency = <0>;
+
+ AINTC: interrupt-controller at 01c20400 {
+ compatible = "allwinner,sun4i-ic";
+ interrupt-controller;
+ #address-cells = <0>;
+ #interrupt-cells = <1>;
+ reg = < 0x01c20400 0x400 >;
+ };
+
+ sramc at 01c00000 {
+ compatible = "allwinner,sun4i-sramc";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ reg = < 0x01c00000 0x1000 >;
+ };
+
+ ccm at 01c20000 {
+ compatible = "allwinner,sun4i-ccm";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ reg = < 0x01c20000 0x400 >;
+ };
+
+ timer at 01c20c00 {
+ compatible = "allwinner,sun4i-timer";
+ reg = <0x01c20c00 0x90>;
+ interrupts = < 22 >;
+ interrupt-parent = <&AINTC>;
+ clock-frequency = < 24000000 >;
+ };
+
+ watchdog at 01c20c90 {
+ compatible = "allwinner,sun4i-wdt";
+ reg = <0x01c20c90 0x08>;
+ };
+
+
+ GPIO: gpio at 01c20800 {
+ #gpio-cells = <3>;
+ compatible = "allwinner,sun4i-gpio";
+ gpio-controller;
+ reg =< 0x01c20800 0x400 >;
+ interrupts = < 28 >;
+ interrupt-parent = <&AINTC>;
+ };
+
+ usb1: usb at 01c14000 {
+ compatible = "allwinner,usb-ehci", "usb-ehci";
+ reg = <0x01c14000 0x1000>;
+ interrupts = < 39 >;
+ interrupt-parent = <&AINTC>;
+ };
+
+ usb2: usb at 01c1c000 {
+ compatible = "allwinner,usb-ehci", "usb-ehci";
+ reg = <0x01c1c000 0x1000>;
+ interrupts = < 40 >;
+ interrupt-parent = <&AINTC>;
+ };
+
+ sata at 01c18000 {
+ compatible = "allwinner,ahci";
+ reg = <0x01c18000 0x1000>;
+ interrupts = <56>;
+ interrupt-parent = <&AINTC>;
+ };
+
+ UART0: serial at 01c28000 {
+ compatible = "ns16550";
+ reg = <0x01c28000 0x400>;
+ reg-shift = <2>;
+ interrupts = <1>;
+ interrupt-parent = <&AINTC>;
+ current-speed = <115200>;
+ clock-frequency = < 24000000 >;
+ busy-detect = <1>;
+ broken-txfifo = <1>;
+ };
+
+ emac at 01c0b000 {
+ compatible = "allwinner,sun4i-emac";
+ reg = <0x01c0b000 0x1000>;
+ interrupts = <55>;
+ interrupt-parent = <&AINTC>;
+ };
+ };
+};
+
Property changes on: trunk/sys/boot/fdt/dts/arm/sun4i-a10.dtsi
___________________________________________________________________
Added: svn:eol-style
## -0,0 +1 ##
+native
\ No newline at end of property
Added: svn:keywords
## -0,0 +1 ##
+MidnightBSD=%H
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+text/plain
\ No newline at end of property
Added: trunk/sys/boot/fdt/dts/arm/sun7i-a20.dtsi
===================================================================
--- trunk/sys/boot/fdt/dts/arm/sun7i-a20.dtsi (rev 0)
+++ trunk/sys/boot/fdt/dts/arm/sun7i-a20.dtsi 2018-06-02 12:34:49 UTC (rev 10205)
@@ -0,0 +1,140 @@
+/* $MidnightBSD$ */
+/*-
+ * Copyright (c) 2014 Ganbold Tsagaankhuu <ganbold at freebsd.org>
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ * $FreeBSD: stable/10/sys/boot/fdt/dts/arm/sun7i-a20.dtsi 266376 2014-05-17 23:16:18Z ian $
+ */
+
+/ {
+ compatible = "allwinner,sun7i-a20";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ interrupt-parent = <&GIC>;
+
+ aliases {
+ soc = &SOC;
+ };
+
+ SOC: a20 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "simple-bus";
+ ranges;
+ bus-frequency = <0>;
+
+ GIC: interrupt-controller at 01c81000 {
+ compatible = "arm,gic";
+ reg = <0x01c81000 0x1000>, /* Distributor Registers */
+ <0x01c82000 0x0100>; /* CPU Interface Registers */
+ interrupt-controller;
+ #interrupt-cells = <1>;
+ };
+
+ sramc at 01c00000 {
+ compatible = "allwinner,sun4i-sramc";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ reg = < 0x01c00000 0x1000 >;
+ };
+
+ cpu-cfg at 01c25c00 {
+ compatible = "allwinner,sun7i-cpu-cfg";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ reg = < 0x01c25c00 0x400 >;
+ };
+
+ ccm at 01c20000 {
+ compatible = "allwinner,sun4i-ccm";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ reg = < 0x01c20000 0x400 >;
+ };
+
+ timer at 01c20c00 {
+ compatible = "allwinner,sun7i-timer";
+ reg = <0x01c20c00 0x90>;
+ interrupts = < 22 >;
+ interrupt-parent = <&GIC>;
+ clock-frequency = < 24000000 >;
+ };
+
+ watchdog at 01c20c90 {
+ compatible = "allwinner,sun4i-wdt";
+ reg = <0x01c20c90 0x10>;
+ };
+
+ GPIO: gpio at 01c20800 {
+ #gpio-cells = <3>;
+ compatible = "allwinner,sun4i-gpio";
+ gpio-controller;
+ reg =< 0x01c20800 0x400 >;
+ interrupts = < 28 >;
+ interrupt-parent = <&GIC>;
+ };
+
+ usb1: usb at 01c14000 {
+ compatible = "allwinner,usb-ehci", "usb-ehci";
+ reg = <0x01c14000 0x1000>;
+ interrupts = < 39 >;
+ interrupt-parent = <&GIC>;
+ };
+
+ usb2: usb at 01c1c000 {
+ compatible = "allwinner,usb-ehci", "usb-ehci";
+ reg = <0x01c1c000 0x1000>;
+ interrupts = < 40 >;
+ interrupt-parent = <&GIC>;
+ };
+
+ sata at 01c18000 {
+ compatible = "allwinner,ahci";
+ reg = <0x01c18000 0x1000>;
+ interrupts = <56>;
+ interrupt-parent = <&GIC>;
+ };
+
+ UART0: serial at 01c28000 {
+ compatible = "ns16550";
+ reg = <0x01c28000 0x400>;
+ reg-shift = <2>;
+ interrupts = <1>;
+ interrupt-parent = <&GIC>;
+ current-speed = <115200>;
+ clock-frequency = < 24000000 >;
+ busy-detect = <1>;
+ broken-txfifo = <1>;
+ };
+
+ emac at 01c0b000 {
+ compatible = "allwinner,sun4i-emac";
+ reg = <0x01c0b000 0x1000>;
+ interrupts = <55>;
+ interrupt-parent = <&GIC>;
+ };
+ };
+};
+
Property changes on: trunk/sys/boot/fdt/dts/arm/sun7i-a20.dtsi
___________________________________________________________________
Added: svn:eol-style
## -0,0 +1 ##
+native
\ No newline at end of property
Added: svn:keywords
## -0,0 +1 ##
+MidnightBSD=%H
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+text/plain
\ No newline at end of property
Added: trunk/sys/boot/fdt/dts/arm/tegra20-paz00.dts
===================================================================
--- trunk/sys/boot/fdt/dts/arm/tegra20-paz00.dts (rev 0)
+++ trunk/sys/boot/fdt/dts/arm/tegra20-paz00.dts 2018-06-02 12:34:49 UTC (rev 10205)
@@ -0,0 +1,59 @@
+/* $MidnightBSD$ */
+/*-
+ * Copyright (c) 2011 The FreeBSD Foundation
+ * Copyright (c) 2012 Andrew Turner
+ * All rights reserved.
+ *
+ * Developed by Damjan Marion <damjan.marion at gmail.com>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ * $FreeBSD: stable/10/sys/boot/fdt/dts/arm/tegra20-paz00.dts 262614 2014-02-28 18:29:09Z imp $
+ */
+/dts-v1/;
+
+/include/ "tegra20.dtsi"
+
+/ {
+ model = "Toshiba AC100 / Dynabook AZ";
+
+ aliases {
+ serial0 = &serial0;
+ soc = &SOC;
+ };
+
+ memory {
+ device_type = "memory";
+ reg = < 0x00000000 0x20000000 >; /* 512MB RAM at 0x0 */
+ };
+
+ chosen {
+ stdin = "serial0";
+ stdout = "serial0";
+ };
+
+ SOC: tegra20 at 0 {
+ serial0: serial at 70006000 {
+ };
+ };
+};
+
Property changes on: trunk/sys/boot/fdt/dts/arm/tegra20-paz00.dts
___________________________________________________________________
Added: svn:eol-style
## -0,0 +1 ##
+native
\ No newline at end of property
Added: svn:keywords
## -0,0 +1 ##
+MidnightBSD=%H
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+text/plain
\ No newline at end of property
Added: trunk/sys/boot/fdt/dts/arm/tegra20.dtsi
===================================================================
--- trunk/sys/boot/fdt/dts/arm/tegra20.dtsi (rev 0)
+++ trunk/sys/boot/fdt/dts/arm/tegra20.dtsi 2018-06-02 12:34:49 UTC (rev 10205)
@@ -0,0 +1,75 @@
+/* $MidnightBSD$ */
+/*-
+ * Copyright (c) 2011 The FreeBSD Foundation
+ * Copyright (c) 2012 Andrew Turner
+ * All rights reserved.
+ *
+ * Developed by Damjan Marion <damjan.marion at gmail.com>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ * $FreeBSD: stable/10/sys/boot/fdt/dts/arm/tegra20.dtsi 262614 2014-02-28 18:29:09Z imp $
+ */
+
+/ {
+ compatible = "compal,paz00", "nvidia,tegra20";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ interrupt-parent = <&GIC>;
+
+ SOC: tegra20 at 0 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "simple-bus";
+ ranges;
+ bus-frequency = <0>;
+
+ GIC: interrupt-controller at 50041000 {
+ compatible = "arm,gic";
+ reg = < 0x50041000 0x1000 >, /* Distributor Registers */
+ < 0x50040100 0x0100 >; /* CPU Interface Registers */
+ interrupt-controller;
+ #interrupt-cells = <1>;
+ };
+
+ mp_tmr at 50040200 {
+ compatible = "arm,mpcore-timers";
+ clock-frequency = < 50040200 >;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = < 0x50040200 0x100 >, /* Global Timer Registers */
+ < 0x50040600 0x100 >; /* Private Timer Registers */
+ interrupts = < 27 29 >;
+ interrupt-parent = <&GIC>;
+ };
+
+ serial at 70006000 {
+ compatible = "ns16550";
+ reg = <0x70006000 0x40>;
+ reg-shift = <2>;
+ interrupts = < 68 >;
+ interrupt-parent = <&GIC>;
+ clock-frequency = < 215654400 >;
+ };
+ };
+};
+
Property changes on: trunk/sys/boot/fdt/dts/arm/tegra20.dtsi
___________________________________________________________________
Added: svn:eol-style
## -0,0 +1 ##
+native
\ No newline at end of property
Added: svn:keywords
## -0,0 +1 ##
+MidnightBSD=%H
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+text/plain
\ No newline at end of property
Added: trunk/sys/boot/fdt/dts/arm/trimslice.dts
===================================================================
--- trunk/sys/boot/fdt/dts/arm/trimslice.dts (rev 0)
+++ trunk/sys/boot/fdt/dts/arm/trimslice.dts 2018-06-02 12:34:49 UTC (rev 10205)
@@ -0,0 +1,144 @@
+/* $MidnightBSD$ */
+/*-
+ * Copyright (c) 2011 The FreeBSD Foundation
+ * All rights reserved.
+ *
+ * Developed by Damjan Marion <damjan.marion at gmail.com>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ * $FreeBSD: stable/10/sys/boot/fdt/dts/arm/trimslice.dts 262614 2014-02-28 18:29:09Z imp $
+ */
+
+/dts-v1/;
+
+/ {
+ model = "CompuLab TrimSlice";
+ compatible = "compulab,trimslice", "nvidia,tegra20";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ interrupt-parent = <&GIC>;
+
+ aliases {
+ serial0 = &serial0;
+ soc = &SOC;
+ };
+
+ memory {
+ device_type = "memory";
+ reg = < 0x00000000 0x40000000 >; /* 1GB RAM at 0x0 */
+ };
+
+
+ SOC: tegra20 at 0 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "simple-bus";
+ ranges;
+ bus-frequency = <0>;
+
+ GIC: interrupt-controller at 50041000 {
+ compatible = "arm,gic";
+ interrupt-controller;
+ #address-cells = <0>;
+ #interrupt-cells = <1>;
+ reg = < 0x50041000 0x1000 >, /* Distributor Registers */
+ < 0x50040100 0x0100 >; /* CPU Interface Registers */
+ };
+ mp_tmr at 50040200 {
+ compatible = "arm,mpcore-timers";
+ clock-frequency = < 50040200 >;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = < 0x50040200 0x100 >, /* Global Timer Registers */
+ < 0x50040600 0x100 >; /* Private Timer Registers */
+ interrupts = < 27 29 >;
+ interrupt-parent = < &GIC >;
+ };
+
+ tmr1 at 60005000 {
+ compatible = "nvidia,tegra2-timer";
+ reg = <0x60005000 0x8>;
+ interrupts = < 32 >;
+ interrupt-parent = <&GIC>;
+ };
+
+ tmr2 at 60005008 {
+ compatible = "nvidia,tegra2-timer";
+ reg = <0x60005008 0x8>;
+ interrupts = < 33 >;
+ interrupt-parent = <&GIC>;
+ };
+
+ tmrus at 60005010 {
+ compatible = "nvidia,tegra2-timestamp";
+ reg = <0x60005010 0x8>;
+ };
+
+ tmr3 at 60005050 {
+ compatible = "nvidia,tegra2-timer";
+ reg = <0x60005050 0x8>;
+ interrupts = < 73 >;
+ interrupt-parent = <&GIC>;
+ };
+
+ tmr4 at 60005058 {
+ compatible = "nvidia,tegra2-timer";
+ reg = <0x60005058 0x8>;
+ interrupts = < 74 >;
+ interrupt-parent = <&GIC>;
+ };
+
+ serial0: serial at 70006000 {
+ compatible = "ns16550";
+ reg = <0x70006000 0x40>;
+ reg-shift = <2>;
+ interrupts = < 68 >;
+ interrupt-parent = <&GIC>;
+ clock-frequency = < 215654400 >;
+ };
+
+ serial1: serial at 70006040 {
+ compatible = "ns16550";
+ reg = <0x70006040 0x40>;
+ reg-shift = <2>;
+ interrupts = < 69 >;
+ interrupt-parent = <&GIC>;
+ clock-frequency = < 215654400 >;
+ };
+
+ serial2: serial at 70006200 {
+ compatible = "ns16550";
+ reg = <0x70006200 0x100>;
+ reg-shift = <2>;
+ interrupts = < 78 >;
+ interrupt-parent = <&GIC>;
+ clock-frequency = < 215654400 >;
+ };
+ };
+
+ chosen {
+ stdin = "serial0";
+ stdout = "serial0";
+ };
+};
Property changes on: trunk/sys/boot/fdt/dts/arm/trimslice.dts
___________________________________________________________________
Added: svn:eol-style
## -0,0 +1 ##
+native
\ No newline at end of property
Added: svn:keywords
## -0,0 +1 ##
+MidnightBSD=%H
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+text/plain
\ No newline at end of property
Added: trunk/sys/boot/fdt/dts/arm/ts7800.dts
===================================================================
--- trunk/sys/boot/fdt/dts/arm/ts7800.dts (rev 0)
+++ trunk/sys/boot/fdt/dts/arm/ts7800.dts 2018-06-02 12:34:49 UTC (rev 10205)
@@ -0,0 +1,162 @@
+/* $MidnightBSD$ */
+/*
+ * Copyright (c) 2010 The FreeBSD Foundation
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ * Technologic Systems TS-7800 Device Tree Source.
+ *
+ * $FreeBSD: stable/10/sys/boot/fdt/dts/arm/ts7800.dts 262614 2014-02-28 18:29:09Z imp $
+ */
+
+/dts-v1/;
+
+/ {
+ model = "mrvl,TS-7800";
+ compatible = "DB-88F5182-BP", "DB-88F5182-BP-A";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ aliases {
+ ethernet0 = &mge0;
+ serial0 = &serial0;
+ serial1 = &serial1;
+ mpp = &MPP;
+ };
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cpu at 0 {
+ device_type = "cpu";
+ compatible = "ARM,88FR531";
+ reg = <0x0>;
+ d-cache-line-size = <32>; // 32 bytes
+ i-cache-line-size = <32>; // 32 bytes
+ d-cache-size = <0x8000>; // L1, 32K
+ i-cache-size = <0x8000>; // L1, 32K
+ timebase-frequency = <0>;
+ bus-frequency = <0>;
+ clock-frequency = <0>;
+ };
+ };
+
+ memory {
+ device_type = "memory";
+ reg = <0x0 0x08000000>; // 128M at 0x0
+ };
+
+ localbus at f1000000 {
+ #address-cells = <2>;
+ #size-cells = <1>;
+ compatible = "mrvl,lbc";
+
+ /* This reflects CPU decode windows setup. */
+ ranges = <0x0 0x0f 0xf9300000 0x00100000
+ 0x1 0x1e 0xfa000000 0x00100000
+ 0x2 0x1d 0xfa100000 0x02000000>;
+ };
+
+ soc88f5182 at f1000000 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "simple-bus";
+ ranges = <0x0 0xf1000000 0x00100000>;
+ bus-frequency = <0>;
+
+ PIC: pic at 20200 {
+ interrupt-controller;
+ #address-cells = <0>;
+ #interrupt-cells = <1>;
+ reg = <0x20200 0x3c>;
+ compatible = "mrvl,pic";
+ };
+
+ timer at 20300 {
+ compatible = "mrvl,timer";
+ reg = <0x20300 0x30>;
+ interrupts = <0>;
+ interrupt-parent = <&PIC>;
+ mrvl,has-wdt;
+ };
+
+ MPP: mpp at 10000 {
+ #pin-cells = <2>;
+ compatible = "mrvl,mpp";
+ reg = <0x10000 0x54>;
+ pin-count = <20>;
+ pin-map = <
+ 16 0 /* MPP[16]: UA1_RXD */
+ 17 0 /* MPP[17]: UA1_TXD */
+ 19 0 >; /* MPP[19]: UA1_RTS */
+ };
+
+ mge0: ethernet at 72000 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ model = "V1";
+ compatible = "mrvl,ge";
+ reg = <0x72000 0x2000>;
+ ranges = <0x0 0x72000 0x2000>;
+ local-mac-address = [ 00 00 00 00 00 00 ];
+ interrupts = <18 19 20 21 22>;
+ interrupt-parent = <&PIC>;
+
+ phy-handle = <&phy0>;
+
+ mdio at 0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "mrvl,mdio";
+
+ phy0: ethernet-phy at 0 {
+ reg = <0x0>;
+ };
+ };
+ };
+
+ serial0: serial at 12000 {
+ compatible = "ns16550";
+ reg = <0x12000 0x20>;
+ reg-shift = <2>;
+ clock-frequency = <0>;
+ interrupts = <3>;
+ interrupt-parent = <&PIC>;
+ };
+
+ serial1: serial at 12100 {
+ compatible = "ns16550";
+ reg = <0x12100 0x20>;
+ reg-shift = <2>;
+ clock-frequency = <0>;
+ interrupts = <4>;
+ interrupt-parent = <&PIC>;
+ };
+ };
+
+ chosen {
+ stdin = "serial0";
+ stdout = "serial0";
+ };
+};
Property changes on: trunk/sys/boot/fdt/dts/arm/ts7800.dts
___________________________________________________________________
Added: svn:eol-style
## -0,0 +1 ##
+native
\ No newline at end of property
Added: svn:keywords
## -0,0 +1 ##
+MidnightBSD=%H
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+text/plain
\ No newline at end of property
Added: trunk/sys/boot/fdt/dts/arm/versatilepb.dts
===================================================================
--- trunk/sys/boot/fdt/dts/arm/versatilepb.dts (rev 0)
+++ trunk/sys/boot/fdt/dts/arm/versatilepb.dts 2018-06-02 12:34:49 UTC (rev 10205)
@@ -0,0 +1,119 @@
+/* $MidnightBSD$ */
+/*
+ * $FreeBSD: stable/10/sys/boot/fdt/dts/arm/versatilepb.dts 262614 2014-02-28 18:29:09Z imp $
+ */
+/dts-v1/;
+
+/ {
+ model = "ARM Versatile PB";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "arm,versatile-pb";
+
+ amba {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+
+ intc: interrupt-controller {
+ compatible = "arm,versatile-vic";
+ reg = <0x10140000 0x1000>;
+
+ interrupt-controller;
+ #interrupt-cells = <1>;
+ };
+
+ sic: secondary-interrupt-controller {
+ compatible = "arm,versatile-sic";
+ reg = <0x10003000 0x28>;
+
+ interrupt-controller;
+ #interrupt-cells = <1>;
+ };
+
+ uart0: uart0 {
+ compatible = "arm,pl011", "arm,primecell";
+ reg = <0x101f1000 0x1000>;
+ interrupts = <12>;
+ interrupt-parent = <&intc>;
+ clock-frequency = <3000000>;
+ reg-shift = <2>;
+ };
+
+ uart1: uart1 {
+ compatible = "arm,pl011", "arm,primecell";
+ reg = <0x101f2000 0x1000>;
+ interrupts = <13>;
+ interrupt-parent = <&intc>;
+ clock-frequency = <3000000>;
+ reg-shift = <2>;
+ };
+
+ uart2: uart2 {
+ compatible = "arm,pl011", "arm,primecell";
+ reg = <0x101f3000 0x1000>;
+ interrupts = <14>;
+ interrupt-parent = <&intc>;
+ clock-frequency = <3000000>;
+ reg-shift = <2>;
+ };
+
+ timer0 {
+ compatible = "arm,sp804", "arm,primecell";
+ reg = <0x101e2000 0x40>;
+ interrupts = <4>;
+ interrupt-parent = <&intc>;
+ };
+
+ pci0 {
+
+ compatible = "versatile,pci";
+ reg = <0x10000044 0x4
+ 0x10001000 0x1000
+ 0x41000000 0x01000000
+ 0x42000000 0x02000000>;
+ };
+
+ net {
+ compatible = "smsc,lan91c111";
+ reg = <0x10010000 0x10000>;
+ interrupts = <25>;
+ interrupt-parent = <&intc>;
+ };
+
+ display {
+ compatible = "arm,pl110", "arm,primecell";
+ reg = <0x10000050 4
+ 0x10120000 0x1000>;
+ interrupts = <16>;
+ interrupt-parent = <&intc>;
+ };
+
+ /*
+ * Cut corner here: we do not have proper interrupt
+ * controllers cascading so just hardwire SIC IRQ 3
+ * to VIC IRQ31
+ */
+ kmi {
+ compatible = "arm,pl050", "arm,primecell";
+ reg = <0x10006000 0x1000>;
+ interrupt-parent = <&intc>;
+ interrupts = <31>;
+ };
+ };
+
+ memory {
+ device_type = "memory";
+ reg = <0 0x08000000>; /* 128MB */
+ };
+
+ aliases {
+ uart0 = &uart0;
+ };
+
+ chosen {
+ stdin = "uart0";
+ stdout = "uart0";
+ };
+};
Property changes on: trunk/sys/boot/fdt/dts/arm/versatilepb.dts
___________________________________________________________________
Added: svn:eol-style
## -0,0 +1 ##
+native
\ No newline at end of property
Added: svn:keywords
## -0,0 +1 ##
+MidnightBSD=%H
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+text/plain
\ No newline at end of property
Added: trunk/sys/boot/fdt/dts/arm/vybrid-colibri-vf50.dts
===================================================================
--- trunk/sys/boot/fdt/dts/arm/vybrid-colibri-vf50.dts (rev 0)
+++ trunk/sys/boot/fdt/dts/arm/vybrid-colibri-vf50.dts 2018-06-02 12:34:49 UTC (rev 10205)
@@ -0,0 +1,83 @@
+/* $MidnightBSD$ */
+/*-
+ * Copyright (c) 2014 Ruslan Bukin <br at bsdpad.com>
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ * $FreeBSD: stable/10/sys/boot/fdt/dts/arm/vybrid-colibri-vf50.dts 262614 2014-02-28 18:29:09Z imp $
+ */
+
+/dts-v1/;
+
+/include/ "vybrid.dtsi"
+
+/ {
+ model = "Toradex Colibri VF50";
+
+ memory {
+ device_type = "memory";
+ reg = < 0x80000000 0x08000000 >; /* 128MB RAM */
+ };
+
+ SOC: vybrid {
+ serial0: serial at 40027000 {
+ status = "okay";
+ };
+
+ fec1: ethernet at 400D1000 {
+ status = "okay";
+ iomux_config = < 54 0x103192
+ 55 0x103193
+ 56 0x103191
+ 57 0x103191
+ 58 0x103191
+ 59 0x103191
+ 60 0x103192
+ 61 0x103192
+ 62 0x103192
+ 0 0x103191 >;
+ };
+
+ sai3: sai at 40032000 {
+ status = "okay";
+ };
+
+ i2c0: i2c at 40066000 {
+ status = "okay";
+ };
+
+ adc0: adc at 4003B000 {
+ status = "okay";
+ };
+
+ edma1: edma at 40098000 {
+ status = "okay";
+ };
+ };
+
+ chosen {
+ bootargs = "-v";
+ stdin = "serial0";
+ stdout = "serial0";
+ };
+};
Property changes on: trunk/sys/boot/fdt/dts/arm/vybrid-colibri-vf50.dts
___________________________________________________________________
Added: svn:eol-style
## -0,0 +1 ##
+native
\ No newline at end of property
Added: svn:keywords
## -0,0 +1 ##
+MidnightBSD=%H
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+text/plain
\ No newline at end of property
Added: trunk/sys/boot/fdt/dts/arm/vybrid-cosmic.dts
===================================================================
--- trunk/sys/boot/fdt/dts/arm/vybrid-cosmic.dts (rev 0)
+++ trunk/sys/boot/fdt/dts/arm/vybrid-cosmic.dts 2018-06-02 12:34:49 UTC (rev 10205)
@@ -0,0 +1,87 @@
+/* $MidnightBSD$ */
+/*-
+ * Copyright (c) 2013-2014 Ruslan Bukin <br at bsdpad.com>
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ * $FreeBSD: stable/10/sys/boot/fdt/dts/arm/vybrid-cosmic.dts 262614 2014-02-28 18:29:09Z imp $
+ */
+
+/dts-v1/;
+
+/include/ "vybrid.dtsi"
+
+/ {
+ model = "Cosmic Board";
+
+ memory {
+ device_type = "memory";
+ reg = < 0x80000000 0x10000000 >; /* 256MB RAM */
+ };
+
+ SOC: vybrid {
+ serial1: serial at 40028000 {
+ status = "okay";
+ };
+
+ fec1: ethernet at 400D1000 {
+ status = "okay";
+ iomux_config = < 54 0x103192
+ 55 0x103193
+ 56 0x103191
+ 57 0x103191
+ 58 0x103191
+ 59 0x103191
+ 60 0x103192
+ 61 0x103192
+ 62 0x103192
+ 0 0x203191 >;
+ };
+
+ esai: esai at 40062000 {
+ status = "okay";
+ };
+
+ edma1: edma at 40098000 {
+ status = "okay";
+ };
+
+ tcon0: tcon at 4003D000 {
+ status = "okay";
+ };
+
+ dcu0: dcu4 at 40058000 {
+ status = "okay";
+ };
+
+ adc0: adc at 4003B000 {
+ status = "okay";
+ };
+ };
+
+ chosen {
+ bootargs = "-v";
+ stdin = "serial1";
+ stdout = "serial1";
+ };
+};
Property changes on: trunk/sys/boot/fdt/dts/arm/vybrid-cosmic.dts
___________________________________________________________________
Added: svn:eol-style
## -0,0 +1 ##
+native
\ No newline at end of property
Added: svn:keywords
## -0,0 +1 ##
+MidnightBSD=%H
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+text/plain
\ No newline at end of property
Added: trunk/sys/boot/fdt/dts/arm/vybrid-quartz.dts
===================================================================
--- trunk/sys/boot/fdt/dts/arm/vybrid-quartz.dts (rev 0)
+++ trunk/sys/boot/fdt/dts/arm/vybrid-quartz.dts 2018-06-02 12:34:49 UTC (rev 10205)
@@ -0,0 +1,116 @@
+/* $MidnightBSD$ */
+/*-
+ * Copyright (c) 2014 Ruslan Bukin <br at bsdpad.com>
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ * $FreeBSD: stable/10/sys/boot/fdt/dts/arm/vybrid-quartz.dts 266274 2014-05-16 23:27:18Z ian $
+ */
+
+/dts-v1/;
+
+/include/ "vybrid.dtsi"
+
+/ {
+ model = "Device Solutions Quartz Module";
+
+ memory {
+ device_type = "memory";
+ reg = < 0x80000000 0x10000000 >; /* 256MB RAM */
+ };
+
+ SOC: vybrid {
+ serial0: serial at 40027000 {
+ status = "okay";
+ };
+
+ fec1: ethernet at 400D1000 {
+ status = "okay";
+ iomux_config = < 54 0x103192
+ 55 0x103193
+ 56 0x103191
+ 57 0x103191
+ 58 0x103191
+ 59 0x103191
+ 60 0x103192
+ 61 0x103192
+ 62 0x103192
+ 0 0x203191 >;
+ };
+
+ edma1: edma at 40098000 {
+ status = "okay";
+ };
+
+ dcu0: dcu4 at 40058000 {
+ status = "okay";
+
+ panel-size = < 800 480 >;
+ panel-hsync = < 40 48 40 >;
+ panel-vsync = < 29 3 13 >;
+ panel-clk-div = < 17 >;
+ panel-backlight-pin = < 25 >;
+
+ iomux_config = < 105 0x1001c4 /* hsync */
+ 106 0x1001c4 /* vsync */
+ 107 0x1001e0 /* pclk */
+ 108 0x1001e0
+ 109 0x1001be /* de */
+ 110 0x1001e0 /* r0 */
+ 111 0x1001e0
+ 112 0x1001e0
+ 113 0x1001e0
+ 114 0x1001e0
+ 115 0x1001e0
+ 116 0x1001e0
+ 117 0x1001e0
+ 118 0x1001e0 /* g0 */
+ 119 0x1001e0
+ 120 0x1001e0
+ 121 0x1001e0
+ 122 0x1001e0
+ 123 0x1001e0
+ 124 0x1001e0
+ 125 0x1001e0
+ 126 0x1001e0 /* b0 */
+ 127 0x1001e0
+ 128 0x1001e0
+ 129 0x1001e0
+ 130 0x1001e0
+ 131 0x1001e0
+ 132 0x1001e0
+ 133 0x1001e0
+ 25 0x0001be >; /* led */
+ };
+
+ tcon0: tcon at 4003D000 {
+ status = "okay";
+ };
+ };
+
+ chosen {
+ bootargs = "-v";
+ stdin = "serial0";
+ stdout = "serial0";
+ };
+};
Property changes on: trunk/sys/boot/fdt/dts/arm/vybrid-quartz.dts
___________________________________________________________________
Added: svn:eol-style
## -0,0 +1 ##
+native
\ No newline at end of property
Added: svn:keywords
## -0,0 +1 ##
+MidnightBSD=%H
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+text/plain
\ No newline at end of property
Added: trunk/sys/boot/fdt/dts/arm/vybrid.dtsi
===================================================================
--- trunk/sys/boot/fdt/dts/arm/vybrid.dtsi (rev 0)
+++ trunk/sys/boot/fdt/dts/arm/vybrid.dtsi 2018-06-02 12:34:49 UTC (rev 10205)
@@ -0,0 +1,498 @@
+/* $MidnightBSD$ */
+/*-
+ * Copyright (c) 2013-2014 Ruslan Bukin <br at bsdpad.com>
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ * $FreeBSD: stable/10/sys/boot/fdt/dts/arm/vybrid.dtsi 266274 2014-05-16 23:27:18Z ian $
+ */
+
+/ {
+ model = "Freescale Vybrid Family";
+ compatible = "freescale,vybrid", "fsl,mvf";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ interrupt-parent = <&GIC>;
+
+ aliases {
+ soc = &SOC;
+ serial0 = &serial0;
+ serial1 = &serial1;
+ sai0 = &sai0;
+ sai1 = &sai1;
+ sai2 = &sai2;
+ sai3 = &sai3;
+ esai = &esai;
+ adc0 = &adc0;
+ adc1 = &adc1;
+ edma0 = &edma0;
+ edma1 = &edma1;
+ src = &SRC;
+ };
+
+ SOC: vybrid {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "simple-bus";
+ ranges;
+ bus-frequency = <0>;
+
+ SRC: src at 4006E000 {
+ compatible = "fsl,mvf600-src";
+ reg = <0x4006E000 0x100>;
+ };
+
+ mscm at 40001000 {
+ compatible = "fsl,mvf600-mscm";
+ reg = <0x40001000 0x1000>;
+ };
+
+ GIC: interrupt-controller at 01c81000 {
+ compatible = "arm,gic";
+ reg = <0x40003000 0x1000>, /* Distributor Registers */
+ <0x40002100 0x100>; /* CPU Interface Registers */
+ interrupt-controller;
+ #interrupt-cells = <1>;
+ };
+
+ anadig at 40050000 {
+ compatible = "fsl,mvf600-anadig";
+ reg = <0x40050000 0x300>;
+ };
+
+ ccm at 4006b000 {
+ compatible = "fsl,mvf600-ccm";
+ reg = <0x4006b000 0x1000>;
+ clock_names = "pll4";
+ };
+
+ mp_tmr at 40002100 {
+ compatible = "arm,mpcore-timers";
+ clock-frequency = <133000000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = < 0x40002200 0x100 >, /* Global Timer Registers */
+ < 0x40002600 0x100 >; /* Private Timer Registers */
+ interrupts = < 27 29 >;
+ interrupt-parent = < &GIC >;
+ };
+
+ dmamux at 40024000 {
+ compatible = "fsl,mvf600-dmamux";
+ reg = <0x40024000 0x100>,
+ <0x40025000 0x100>,
+ <0x400A1000 0x100>,
+ <0x400A2000 0x100>;
+ };
+
+ edma0: edma at 40018000 {
+ compatible = "fsl,mvf600-edma";
+ reg = <0x40018000 0x1000>,
+ <0x40019000 0x1000>; /* TCD */
+ interrupts = < 40 41 >;
+ interrupt-parent = <&GIC>;
+ device-id = < 0 >;
+ status = "disabled";
+ };
+
+ edma1: edma at 40098000 {
+ compatible = "fsl,mvf600-edma";
+ reg = <0x40098000 0x1000>,
+ <0x40099000 0x1000>; /* TCD */
+ interrupts = < 42 43 >;
+ interrupt-parent = <&GIC>;
+ device-id = < 1 >;
+ status = "disabled";
+ };
+
+ pit at 40037000 {
+ compatible = "fsl,mvf600-pit";
+ reg = <0x40037000 0x1000>;
+ interrupts = < 71 >;
+ interrupt-parent = <&GIC>;
+ clock-frequency = < 24000000 >;
+ };
+
+ lptmr at 40040000 {
+ compatible = "fsl,mvf600-lptmr";
+ reg = <0x40040000 0x1000>;
+ interrupts = < 72 >;
+ interrupt-parent = <&GIC>;
+ clock-frequency = < 24000000 >;
+ };
+
+ iomuxc at 40048000 {
+ compatible = "fsl,mvf600-iomuxc";
+ reg = <0x40048000 0x1000>;
+ };
+
+ port at 40049000 {
+ compatible = "fsl,mvf600-port";
+ reg = <0x40049000 0x5000>;
+ interrupts = < 139 140 141 142 143 >;
+ interrupt-parent = <&GIC>;
+ };
+
+ gpio at 400FF000 {
+ compatible = "fsl,mvf600-gpio";
+ reg = <0x400FF000 0x200>;
+ #gpio-cells = <3>;
+ gpio-controller;
+ };
+
+ nand at 400E0000 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "fsl,mvf600-nand";
+ reg = <0x400E0000 0x10000>;
+ interrupts = < 115 >;
+ interrupt-parent = <&GIC>;
+ clock_names = "nand";
+ status = "disabled";
+
+ partition at 40000 {
+ reg = <0x40000 0x200000>; /* 2MB */
+ label = "u-boot";
+ read-only;
+ };
+
+ partition at 240000 {
+ reg = <0x240000 0x200000>; /* 2MB */
+ label = "test";
+ };
+
+ partition at 440000 {
+ reg = <0x440000 0xa00000>; /* 10MB */
+ label = "kernel";
+ };
+
+ partition at e40000 {
+ reg = <0xe40000 0x1e000000>; /* 480MB */
+ label = "root";
+ };
+ };
+
+ sdhci0: sdhci at 400B1000 {
+ compatible = "fsl,mvf600-sdhci";
+ reg = <0x400B1000 0x1000>;
+ interrupts = < 59 >;
+ interrupt-parent = <&GIC>;
+ clock-frequency = <50000000>;
+ status = "disabled";
+ clock_names = "esdhc0";
+ };
+
+ sdhci1: sdhci at 400B2000 {
+ compatible = "fsl,mvf600-sdhci";
+ reg = <0x400B2000 0x1000>;
+ interrupts = < 60 >;
+ interrupt-parent = <&GIC>;
+ clock-frequency = <50000000>;
+ status = "disabled";
+ clock_names = "esdhc1";
+ iomux_config = < 14 0x500060
+ 15 0x500060
+ 16 0x500060
+ 17 0x500060
+ 18 0x500060
+ 19 0x500060 >;
+ };
+
+ serial0: serial at 40027000 {
+ compatible = "fsl,mvf600-uart";
+ reg = <0x40027000 0x1000>;
+ interrupts = <93>;
+ interrupt-parent = <&GIC>;
+ current-speed = <115200>;
+ clock-frequency = < 24000000 >;
+ status = "disabled";
+ };
+
+ serial1: serial at 40028000 {
+ compatible = "fsl,mvf600-uart";
+ reg = <0x40028000 0x1000>;
+ interrupts = <94>;
+ interrupt-parent = <&GIC>;
+ current-speed = <115200>;
+ clock-frequency = < 24000000 >;
+ status = "disabled";
+ };
+
+ usb at 40034000 {
+ compatible = "fsl,mvf600-usb-ehci", "usb-ehci";
+ reg = < 0x40034000 0x1000 >, /* ehci */
+ < 0x40035000 0x1000 >, /* usbc */
+ < 0x40050800 0x100 >; /* phy */
+ interrupts = < 107 >;
+ interrupt-parent = <&GIC>;
+ iomux_config = < 134 0x0001be
+ 7 0x200060 >;
+ };
+
+ usb at 400b4000 {
+ compatible = "fsl,mvf600-usb-ehci", "usb-ehci";
+ reg = < 0x400b4000 0x1000 >, /* ehci */
+ < 0x400b5000 0x1000 >, /* usbc */
+ < 0x40050C00 0x100 >; /* phy */
+ interrupts = < 108 >;
+ interrupt-parent = <&GIC>;
+ iomux_config = < 134 0x0001be
+ 7 0x200060 >;
+ };
+
+ fec0: ethernet at 400D0000 {
+ compatible = "fsl,mvf600-fec";
+ reg = <0x400D0000 0x1000>;
+ interrupts = < 110 >;
+ interrupt-parent = <&GIC>;
+ phy-mode = "rmii";
+ phy-disable-preamble;
+ status = "disabled";
+ clock_names = "enet";
+ iomux_config = < 45 0x100061
+ 46 0x100061
+ 47 0x100061
+ 48 0x100060
+ 49 0x100060
+ 50 0x100060
+ 51 0x100060
+ 52 0x100060
+ 53 0x100060 >;
+ };
+
+ fec1: ethernet at 400D1000 {
+ compatible = "fsl,mvf600-fec";
+ reg = <0x400D1000 0x1000>;
+ interrupts = < 111 >;
+ interrupt-parent = <&GIC>;
+ phy-mode = "rmii";
+ phy-disable-preamble;
+ status = "disabled";
+ clock_names = "enet";
+ iomux_config = < 54 0x103192
+ 55 0x103193
+ 56 0x103191
+ 57 0x103191
+ 58 0x103191
+ 59 0x103191
+ 60 0x103192
+ 61 0x103192
+ 62 0x103192 >;
+ };
+
+ sai0: sai at 4002F000 {
+ compatible = "fsl,mvf600-sai";
+ reg = <0x4002F000 0x1000>;
+ interrupts = < 116 >;
+ interrupt-parent = <&GIC>;
+ status = "disabled";
+ };
+
+ sai1: sai at 40030000 {
+ compatible = "fsl,mvf600-sai";
+ reg = <0x40030000 0x1000>;
+ interrupts = < 117 >;
+ interrupt-parent = <&GIC>;
+ status = "disabled";
+ };
+
+ sai2: sai at 40031000 {
+ compatible = "fsl,mvf600-sai";
+ reg = <0x40031000 0x1000>;
+ interrupts = < 118 >;
+ interrupt-parent = <&GIC>;
+ status = "disabled";
+ };
+
+ sai3: sai at 40032000 {
+ compatible = "fsl,mvf600-sai";
+ reg = <0x40032000 0x1000>;
+ interrupts = < 119 >;
+ interrupt-parent = <&GIC>;
+ status = "disabled";
+ edma-controller = <&edma1>;
+ edma-src-receive = < 8 >;
+ edma-src-transmit = < 9 >;
+ edma-mux-group = < 1 >;
+ clock_names = "sai3", "cko1";
+ iomux_config = < 16 0x200060
+ 19 0x200060
+ 21 0x200060
+ 40 0x400061 >; /* CKO1 */
+ };
+
+ esai: esai at 40062000 {
+ compatible = "fsl,mvf600-esai";
+ reg = <0x40062000 0x1000>;
+ interrupts = < 120 >;
+ interrupt-parent = <&GIC>;
+ status = "disabled";
+ clock_names = "esai";
+ iomux_config = < 45 0x400061
+ 46 0x400061
+ 47 0x400061
+ 48 0x400060
+ 49 0x400060
+ 50 0x400060
+ 51 0x400060
+ 52 0x400060
+ 78 0x3038df
+ 40 0x400061 >;
+ };
+
+ spi0: spi at 4002C000 {
+ compatible = "fsl,mvf600-spi";
+ reg = <0x4002C000 0x1000>;
+ interrupts = < 99 >;
+ interrupt-parent = <&GIC>;
+ status = "disabled";
+ iomux_config = < 40 0x100061
+ 41 0x100061
+ 42 0x100060
+ 43 0x100060
+ 44 0x100061 >;
+ };
+
+ spi1: spi at 4002D000 {
+ compatible = "fsl,mvf600-spi";
+ reg = <0x4002D000 0x1000>;
+ interrupts = < 100 >;
+ interrupt-parent = <&GIC>;
+ status = "disabled";
+ };
+
+ spi2: spi at 400AC000 {
+ compatible = "fsl,mvf600-spi";
+ reg = <0x400AC000 0x1000>;
+ interrupts = < 101 >;
+ interrupt-parent = <&GIC>;
+ status = "disabled";
+ };
+
+ spi3: spi at 400AD000 {
+ compatible = "fsl,mvf600-spi";
+ reg = <0x400AD000 0x1000>;
+ interrupts = < 102 >;
+ interrupt-parent = <&GIC>;
+ status = "disabled";
+ };
+
+ i2c0: i2c at 40066000 {
+ compatible = "fsl,mvf600-i2c";
+ reg = <0x40066000 0x1000>;
+ interrupts = < 103 >;
+ interrupt-parent = <&GIC>;
+ status = "disabled";
+ clock_names = "ipg";
+ iomux_config = < 36 0x2034d3
+ 37 0x2034d3
+ 207 0x1
+ 208 0x1 >;
+ };
+
+ i2c1: i2c at 40067000 {
+ compatible = "fsl,mvf600-i2c";
+ reg = <0x40067000 0x1000>;
+ interrupts = < 104 >;
+ interrupt-parent = <&GIC>;
+ status = "disabled";
+ };
+
+ i2c2: i2c at 400E6000 {
+ compatible = "fsl,mvf600-i2c";
+ reg = <0x400E6000 0x1000>;
+ interrupts = < 105 >;
+ interrupt-parent = <&GIC>;
+ status = "disabled";
+ };
+
+ i2c3: i2c at 400E7000 {
+ compatible = "fsl,mvf600-i2c";
+ reg = <0x400E7000 0x1000>;
+ interrupts = < 106 >;
+ interrupt-parent = <&GIC>;
+ status = "disabled";
+ };
+
+ adc0: adc at 4003B000 {
+ compatible = "fsl,mvf600-adc";
+ reg = <0x4003B000 0x1000>;
+ interrupts = < 85 >;
+ interrupt-parent = <&GIC>;
+ status = "disabled";
+ };
+
+ adc1: adc at 400BB000 {
+ compatible = "fsl,mvf600-adc";
+ reg = <0x400BB000 0x1000>;
+ interrupts = < 86 >;
+ interrupt-parent = <&GIC>;
+ status = "disabled";
+ };
+
+ tcon0: tcon at 4003D000 {
+ compatible = "fsl,mvf600-tcon";
+ reg = <0x4003D000 0x1000>;
+ status = "disabled";
+ };
+
+ dcu0: dcu4 at 40058000 {
+ compatible = "fsl,mvf600-dcu4";
+ reg = <0x40058000 0x7000>;
+ interrupts = < 62 >;
+ interrupt-parent = <&GIC>;
+ status = "disabled";
+ clock_names = "dcu0";
+ iomux_config = < 105 0x100044
+ 106 0x100044
+ 107 0x100060
+ 108 0x100060
+ 109 0x100060
+ 110 0x100060
+ 111 0x100060
+ 112 0x100060
+ 113 0x100060
+ 114 0x100060
+ 115 0x100060
+ 116 0x100060
+ 117 0x100060
+ 118 0x100060
+ 119 0x100060
+ 120 0x100060
+ 121 0x100060
+ 122 0x100060
+ 123 0x100060
+ 124 0x100060
+ 125 0x100060
+ 126 0x100060
+ 127 0x100060
+ 128 0x100060
+ 129 0x100060
+ 130 0x100060
+ 131 0x100060
+ 132 0x100060
+ 133 0x100060 >;
+ };
+ };
+};
Property changes on: trunk/sys/boot/fdt/dts/arm/vybrid.dtsi
___________________________________________________________________
Added: svn:eol-style
## -0,0 +1 ##
+native
\ No newline at end of property
Added: svn:keywords
## -0,0 +1 ##
+MidnightBSD=%H
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+text/plain
\ No newline at end of property
Added: trunk/sys/boot/fdt/dts/arm/wandboard-dual.dts
===================================================================
--- trunk/sys/boot/fdt/dts/arm/wandboard-dual.dts (rev 0)
+++ trunk/sys/boot/fdt/dts/arm/wandboard-dual.dts 2018-06-02 12:34:49 UTC (rev 10205)
@@ -0,0 +1,84 @@
+/* $MidnightBSD$ */
+/*
+ * Copyright (c) 2013 Ian Lepore
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ * Wandboard Dual.
+ *
+ * $FreeBSD: stable/10/sys/boot/fdt/dts/arm/wandboard-dual.dts 274269 2014-11-08 04:18:33Z ian $
+ */
+
+/dts-v1/;
+/include/ "imx6.dtsi"
+
+/ {
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ model = "Wandboard Dual";
+ compatible = "wand,imx6d-wandboard", "fsl,imx6d";
+
+ memory {
+ reg = <0x10000000 0x40000000>; /* RAM 1GB */
+ };
+
+ SOC: soc at 00000000 {
+ aips at 02000000 { /* AIPS1 */
+ gpio at 0209c000 { status = "okay"; };
+ gpio at 020a0000 { status = "okay"; };
+ gpio at 020a4000 { status = "okay"; };
+ gpio at 020a8000 { status = "okay"; };
+ gpio at 020ac000 { status = "okay"; };
+ gpio at 020b0000 { status = "okay"; };
+ gpio at 020b4000 { status = "okay"; };
+ console:serial at 02020000 { status = "okay"; };
+ serial at 021e8000 { status = "disabled"; };
+ serial at 021ec000 { status = "disabled"; };
+ serial at 021f0000 { status = "disabled"; };
+ serial at 021f4000 { status = "disabled"; };
+ usbphy at 020c9000 { status = "okay"; };
+ usbphy at 020ca000 { status = "okay"; };
+ };
+ aips at 02100000 { /* AIPS2 */
+ ethernet at 02188000 {
+ status = "okay";
+ phy-mode = "rgmii";
+ phy-disable-preamble;
+ };
+ usb at 02184000 { status = "okay"; };
+ usb at 02184200 { status = "okay"; };
+ usb at 02184400 { status = "disabled"; };
+ usb at 02184600 { status = "disabled"; };
+ usdhc at 02190000 { status = "okay"; };
+ usdhc at 02194000 { status = "disabled"; };
+ usdhc at 02198000 { status = "okay"; };
+ usdhc at 0219c000 { status = "disabled"; };
+ };
+ };
+
+ chosen {
+ stdin = &console;
+ stdout = &console;
+ };
+};
Property changes on: trunk/sys/boot/fdt/dts/arm/wandboard-dual.dts
___________________________________________________________________
Added: svn:eol-style
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+native
\ No newline at end of property
Added: svn:keywords
## -0,0 +1 ##
+MidnightBSD=%H
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+text/plain
\ No newline at end of property
Added: trunk/sys/boot/fdt/dts/arm/wandboard-quad.dts
===================================================================
--- trunk/sys/boot/fdt/dts/arm/wandboard-quad.dts (rev 0)
+++ trunk/sys/boot/fdt/dts/arm/wandboard-quad.dts 2018-06-02 12:34:49 UTC (rev 10205)
@@ -0,0 +1,84 @@
+/* $MidnightBSD$ */
+/*
+ * Copyright (c) 2013 Ian Lepore
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ * Wandboard Quad.
+ *
+ * $FreeBSD: stable/10/sys/boot/fdt/dts/arm/wandboard-quad.dts 274269 2014-11-08 04:18:33Z ian $
+ */
+
+/dts-v1/;
+/include/ "imx6.dtsi"
+
+/ {
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ model = "Wandboard Quad";
+ compatible = "wand,imx6q-wandboard", "fsl,imx6q";
+
+ memory {
+ reg = <0x10000000 0x80000000>; /* RAM 2GB */
+ };
+
+ SOC: soc at 00000000 {
+ aips at 02000000 { /* AIPS1 */
+ gpio at 0209c000 { status = "okay"; };
+ gpio at 020a0000 { status = "okay"; };
+ gpio at 020a4000 { status = "okay"; };
+ gpio at 020a8000 { status = "okay"; };
+ gpio at 020ac000 { status = "okay"; };
+ gpio at 020b0000 { status = "okay"; };
+ gpio at 020b4000 { status = "okay"; };
+ console:serial at 02020000 { status = "okay"; };
+ serial at 021e8000 { status = "disabled"; };
+ serial at 021ec000 { status = "disabled"; };
+ serial at 021f0000 { status = "disabled"; };
+ serial at 021f4000 { status = "disabled"; };
+ usbphy at 020c9000 { status = "okay"; };
+ usbphy at 020ca000 { status = "okay"; };
+ };
+ aips at 02100000 { /* AIPS2 */
+ ethernet at 02188000 {
+ status = "okay";
+ phy-mode = "rgmii";
+ phy-disable-preamble;
+ };
+ usb at 02184000 { status = "okay"; };
+ usb at 02184200 { status = "okay"; };
+ usb at 02184400 { status = "disabled"; };
+ usb at 02184600 { status = "disabled"; };
+ usdhc at 02190000 { status = "okay"; };
+ usdhc at 02194000 { status = "disabled"; };
+ usdhc at 02198000 { status = "okay"; };
+ usdhc at 0219c000 { status = "disabled"; };
+ };
+ };
+
+ chosen {
+ stdin = &console;
+ stdout = &console;
+ };
+};
Property changes on: trunk/sys/boot/fdt/dts/arm/wandboard-quad.dts
___________________________________________________________________
Added: svn:eol-style
## -0,0 +1 ##
+native
\ No newline at end of property
Added: svn:keywords
## -0,0 +1 ##
+MidnightBSD=%H
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+text/plain
\ No newline at end of property
Added: trunk/sys/boot/fdt/dts/arm/wandboard-solo.dts
===================================================================
--- trunk/sys/boot/fdt/dts/arm/wandboard-solo.dts (rev 0)
+++ trunk/sys/boot/fdt/dts/arm/wandboard-solo.dts 2018-06-02 12:34:49 UTC (rev 10205)
@@ -0,0 +1,84 @@
+/* $MidnightBSD$ */
+/*
+ * Copyright (c) 2013 Ian Lepore
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ * Wandboard Solo.
+ *
+ * $FreeBSD: stable/10/sys/boot/fdt/dts/arm/wandboard-solo.dts 274269 2014-11-08 04:18:33Z ian $
+ */
+
+/dts-v1/;
+/include/ "imx6.dtsi"
+
+/ {
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ model = "Wandboard Solo";
+ compatible = "wand,imx6s-wandboard", "fsl,imx6s";
+
+ memory {
+ reg = <0x10000000 0x20000000>; /* RAM 512M */
+ };
+
+ SOC: soc at 00000000 {
+ aips at 02000000 { /* AIPS1 */
+ gpio at 0209c000 { status = "okay"; };
+ gpio at 020a0000 { status = "okay"; };
+ gpio at 020a4000 { status = "okay"; };
+ gpio at 020a8000 { status = "okay"; };
+ gpio at 020ac000 { status = "okay"; };
+ gpio at 020b0000 { status = "okay"; };
+ gpio at 020b4000 { status = "okay"; };
+ console:serial at 02020000 { status = "okay"; };
+ serial at 021e8000 { status = "disabled"; };
+ serial at 021ec000 { status = "disabled"; };
+ serial at 021f0000 { status = "disabled"; };
+ serial at 021f4000 { status = "disabled"; };
+ usbphy at 020c9000 { status = "okay"; };
+ usbphy at 020ca000 { status = "okay"; };
+ };
+ aips at 02100000 { /* AIPS2 */
+ ethernet at 02188000 {
+ status = "okay";
+ phy-mode = "rgmii";
+ phy-disable-preamble;
+ };
+ usb at 02184000 { status = "okay"; };
+ usb at 02184200 { status = "okay"; };
+ usb at 02184400 { status = "disabled"; };
+ usb at 02184600 { status = "disabled"; };
+ usdhc at 02190000 { status = "okay"; };
+ usdhc at 02194000 { status = "disabled"; };
+ usdhc at 02198000 { status = "okay"; };
+ usdhc at 0219c000 { status = "disabled"; };
+ };
+ };
+
+ chosen {
+ stdin = &console;
+ stdout = &console;
+ };
+};
Property changes on: trunk/sys/boot/fdt/dts/arm/wandboard-solo.dts
___________________________________________________________________
Added: svn:eol-style
## -0,0 +1 ##
+native
\ No newline at end of property
Added: svn:keywords
## -0,0 +1 ##
+MidnightBSD=%H
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Added: svn:mime-type
## -0,0 +1 ##
+text/plain
\ No newline at end of property
Added: trunk/sys/boot/fdt/dts/arm/zedboard.dts
===================================================================
--- trunk/sys/boot/fdt/dts/arm/zedboard.dts (rev 0)
+++ trunk/sys/boot/fdt/dts/arm/zedboard.dts 2018-06-02 12:34:49 UTC (rev 10205)
@@ -0,0 +1,218 @@
+/* $MidnightBSD$ */
+/*-
+ * Copyright (c) 2012 The FreeBSD Foundation
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ * $FreeBSD: stable/10/sys/boot/fdt/dts/arm/zedboard.dts 273645 2014-10-25 20:34:10Z ian $
+ */
+
+/dts-v1/;
+
+/ {
+ model = "zedboard";
+ compatible = "digilent,zedboard";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ interrupt-parent = <&GIC>;
+
+ // cpus {
+ // #address-cells = <1>;
+ // #size-cells = <0>;
+ // cpu at 0 {
+ // device-type = "cpu";
+ // model = "ARM Cortex-A9";
+ // };
+ // };
+
+ memory {
+ // First megabyte isn't accessible by all interconnect masters.
+ device_type = "memory";
+ reg = <0x100000 0x1ff00000>; /* 511MB RAM at 0x100000 */
+ };
+
+ // Zynq PS System registers.
+ //
+ ps7sys at f8000000 {
+ device_type = "soc";
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0xf8000000 0xf10000>;
+
+ // SLCR block
+ slcr: slcr at 7000 {
+ compatible = "xlnx,zy7_slcr";
+ reg = <0x0 0x1000>;
+ clock-frequency = <33333333>; // 33Mhz PS_CLK
+ };
+
+ // Interrupt controller
+ GIC: gic {
+ compatible = "arm,gic";
+ interrupt-controller;
+ #address-cells = <0>;
+ #interrupt-cells = <1>;
+ reg = <0xf01000 0x1000>, // distributer registers
+ <0xf00100 0x0100>; // CPU if registers
+ };
+
+ // L2 cache controller
+ pl310 at f02000 {
+ compatible = "arm,pl310";
+ reg = <0xf02000 0x1000>;
+ interrupts = <34>;
+ interrupt-parent = <&GIC>;
+ };
+
+ // Device Config
+ devcfg: devcfg at 7000 {
+ compatible = "xlnx,zy7_devcfg";
+ reg = <0x7000 0x1000>;
+ interrupts = <40>;
+ interrupt-parent = <&GIC>;
+ };
+
+ // triple timer counters0,1
+ ttc0: ttc at 1000 {
+ compatible = "xlnx,ttc";
+ reg = <0x1000 0x1000>;
+ };
+ ttc1: ttc at 2000 {
+ compatible = "xlnx,ttc";
+ reg = <0x2000 0x1000>;
+ };
+
+ // ARM Cortex A9 TWD Timer
+ timer at f00600 {
+ compatible = "arm,mpcore-timers";
+ clock-frequency = <333333333>; // 333Mhz
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0xf00200 0x100>, // Global Timer Regs
+ <0xf00600 0x20>; // Private Timer Regs
+ interrupts = < 27 29 >;
+ interrupt-parent = <&GIC>;
+ };
+
+ // system watch-dog timer
+ swdt at 5000 {
+ device_type = "watchdog";
+ compatible = "xlnx,zy7_wdt";
+ reg = <0x5000 0x1000>;
+ interrupts = <41>;
+ interrupt-parent = <&GIC>;
+ };
+
+ scuwdt at f00620 {
+ device_type = "watchdog";
+ compatible = "arm,mpcore_wdt";
+ reg = <0xf00620 0x20>;
+ interrupts = <30>;
+ interrupt-parent = <&GIC>;
+ reset = <1>;
+ };
+ }; // pssys at f8000000
+
+ // Zynq PS I/O Peripheral registers.
+ //
+ ps7io at e0000000 {
+ device_type = "soc";
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0xe0000000 0x300000>;
+
+ // uart0: uart at 0000 {
+ // device_type = "serial";
+ // compatible = "cadence,uart";
+ // reg = <0x0000 0x1000>;
+ // interrupts = <59>;
+ // interrupt-parent = <&GIC>;
+ // clock-frequency = <50000000>;
+ // };
+
+ uart1: uart at 1000 {
+ device_type = "serial";
+ compatible = "cadence,uart";
+ reg = <0x1000 0x1000>;
+ interrupts = <82>;
+ interrupt-parent = <&GIC>;
+ clock-frequency = <50000000>;
+ current-speed = <115200>;
+ };
+
+ gpio: gpio at a000 {
+ compatible = "xlnx,zy7_gpio";
+ reg = <0xa000 0x1000>;
+ interrupts = <52>;
+ interrupt-parent = <&GIC>;
+ };
+
+ // GigE
+ eth0: eth at b000 {
+ // device_type = "network";
+
+ compatible = "cadence,gem";
+ reg = <0xb000 0x1000>;
+ interrupts = <54 55>;
+ interrupt-parent = <&GIC>;
+ ref-clock-num = <0>;
+ };
+
+ // SDIO
+ sdhci0: sdhci at 100000 {
+ compatible = "xlnx,zy7_sdhci";
+ reg = <0x100000 0x1000>;
+ interrupts = <56>;
+ interrupt-parent = <&GIC>;
+ max-frequency = <50000000>;
+ };
+
+ // QSPI
+ qspi0: qspi at d000 {
+ compatible = "xlnx,zy7_qspi";
+ reg = <0xd000 0x1000>;
+ interrupts = <51>;
+ interrupt-parent = <&GIC>;
+ spi-clock = <50000000>;
+ ref-clock = <190476000>;
+ };
+
+ // USB
+ ehci0: ehci at 2000 {
+ compatible = "xlnx,zy7_ehci";
+ reg = <0x2000 0x1000>;
+ interrupts = <53>;
+ interrupt-parent = <&GIC>;
+ phy_vbus_ext;
+ };
+
+ }; // ps7io at e0000000
+
+ chosen {
+ stdin = &uart1;
+ stdout = &uart1;
+ };
+};
+
Property changes on: trunk/sys/boot/fdt/dts/arm/zedboard.dts
___________________________________________________________________
Added: svn:eol-style
## -0,0 +1 ##
+native
\ No newline at end of property
Added: svn:keywords
## -0,0 +1 ##
+MidnightBSD=%H
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+text/plain
\ No newline at end of property
Modified: trunk/sys/boot/fdt/dts/bindings-gpio.txt
===================================================================
--- trunk/sys/boot/fdt/dts/bindings-gpio.txt 2018-06-02 00:06:07 UTC (rev 10204)
+++ trunk/sys/boot/fdt/dts/bindings-gpio.txt 2018-06-02 12:34:49 UTC (rev 10205)
@@ -1,4 +1,5 @@
$MidnightBSD$
+$FreeBSD: stable/10/sys/boot/fdt/dts/bindings-gpio.txt 266105 2014-05-15 01:27:53Z loos $
GPIO configuration.
===================
@@ -82,7 +83,7 @@
flags:
0x0000---- IN_NONE
- 0x0001---- IN_POL_LOW Polarity low (inverted input value.
+ 0x0001---- IN_POL_LOW Polarity low (active-low).
0x0002---- IN_IRQ_EDGE Interrupt, edge triggered.
0x0004---- IN_IRQ_LEVEL Interrupt, level triggered.
Added: trunk/sys/boot/fdt/dts/bindings-localbus.txt
===================================================================
--- trunk/sys/boot/fdt/dts/bindings-localbus.txt (rev 0)
+++ trunk/sys/boot/fdt/dts/bindings-localbus.txt 2018-06-02 12:34:49 UTC (rev 10205)
@@ -0,0 +1,84 @@
+$MidnightBSD$
+$FreeBSD: stable/10/sys/boot/fdt/dts/bindings-localbus.txt 235609 2012-05-18 14:41:14Z gber $
+
+Marvell Device bus (localbus) configuration.
+============================================
+
+1. Properties for localbus nodes
+
+1.1 ranges
+
+Property: ranges
+
+Value type: <prop-encoded-array> encoded as arbitrary number of localbus
+ nodes specifiers.
+
+Description: ranges property defines values used for mapping devices
+ connected to localbus, in Marvell devices it is used also for
+ setting decoding windows.
+
+ a) child node address-cells:
+ - first cell: number of bank (chip select)
+ - second cell: (Marvell devices) Target ID for decoding
+ windows setup
+
+ b) parent node address cells:
+ - address offset: used with parent's node base address to
+ specify base address of mapped device
+
+ c) child node size-cells:
+ - size: defines amount of memory that should be reserved for
+ device
+
+1.2 bank-count
+
+Property: bank-count
+
+Value type: <u32>
+
+Description: The bank_count property defines maximum number of banks on
+ localbus node. Bank is most often interpreted as device chip
+ select, but may also describe another device (e.g. SPI flash).
+
+1.3 Example
+
+ localbus at 0 {
+ #address-cells = <2>;
+ #size-cells = <1>;
+ compatible = "mrvl,lbc";
+ bank-count = <5>;
+
+ /* This reflects CPU decode windows setup. */
+ ranges = <0x0 0x2f 0xb2200000 0x00100000
+ 0x1 0x3e 0xb2100000 0x00100000
+ 0x2 0x3d 0xb0000000 0x02000000
+ 0x3 0x3b 0xb2000000 0x00100000>;
+ };
+
+2. Properties for localbus consumer nodes:
+
+2.1 reg
+
+Property: reg
+
+Value type: <prop-encoded-array>
+
+Description: A standard property required for localbus child nodes. Defines
+ the device memory region.
+
+ a) first cell: number of bank (chip select)
+
+ b) address offset: used with address offset from parent's ranges
+ for corresponding bank to specify base address of
+ the device
+
+ c) size: defines size of the device memory region
+
+2.2 Example
+
+ nor at 0,0 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "cfi-flash";
+ reg = <0x0 0x0 0x00100000>;
+ };
Property changes on: trunk/sys/boot/fdt/dts/bindings-localbus.txt
___________________________________________________________________
Added: svn:eol-style
## -0,0 +1 ##
+native
\ No newline at end of property
Added: svn:keywords
## -0,0 +1 ##
+MidnightBSD=%H
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+text/plain
\ No newline at end of property
Modified: trunk/sys/boot/fdt/dts/bindings-mpp.txt
===================================================================
--- trunk/sys/boot/fdt/dts/bindings-mpp.txt 2018-06-02 00:06:07 UTC (rev 10204)
+++ trunk/sys/boot/fdt/dts/bindings-mpp.txt 2018-06-02 12:34:49 UTC (rev 10205)
@@ -1,4 +1,5 @@
-$FreeBSD$
+$MidnightBSD$
+$FreeBSD: stable/10/sys/boot/fdt/dts/bindings-mpp.txt 208561 2010-05-26 09:50:09Z raj $
* Multi purpose pin (MPP) configuration.
Modified: trunk/sys/boot/fdt/dts/db78100.dts
===================================================================
--- trunk/sys/boot/fdt/dts/db78100.dts 2018-06-02 00:06:07 UTC (rev 10204)
+++ trunk/sys/boot/fdt/dts/db78100.dts 2018-06-02 12:34:49 UTC (rev 10205)
@@ -1,3 +1,4 @@
+/* $MidnightBSD$ */
/*
* Copyright (c) 2010 The FreeBSD Foundation
* All rights reserved.
Modified: trunk/sys/boot/fdt/dts/db88f5182.dts
===================================================================
--- trunk/sys/boot/fdt/dts/db88f5182.dts 2018-06-02 00:06:07 UTC (rev 10204)
+++ trunk/sys/boot/fdt/dts/db88f5182.dts 2018-06-02 12:34:49 UTC (rev 10205)
@@ -1,3 +1,4 @@
+/* $MidnightBSD$ */
/*
* Copyright (c) 2010 The FreeBSD Foundation
* All rights reserved.
Modified: trunk/sys/boot/fdt/dts/db88f5281.dts
===================================================================
--- trunk/sys/boot/fdt/dts/db88f5281.dts 2018-06-02 00:06:07 UTC (rev 10204)
+++ trunk/sys/boot/fdt/dts/db88f5281.dts 2018-06-02 12:34:49 UTC (rev 10205)
@@ -1,3 +1,4 @@
+/* $MidnightBSD$ */
/*
* Copyright (c) 2010 The FreeBSD Foundation
* All rights reserved.
Modified: trunk/sys/boot/fdt/dts/db88f6281.dts
===================================================================
--- trunk/sys/boot/fdt/dts/db88f6281.dts 2018-06-02 00:06:07 UTC (rev 10204)
+++ trunk/sys/boot/fdt/dts/db88f6281.dts 2018-06-02 12:34:49 UTC (rev 10205)
@@ -1,3 +1,4 @@
+/* $MidnightBSD$ */
/*
* Copyright (c) 2009-2010 The FreeBSD Foundation
* All rights reserved.
Modified: trunk/sys/boot/fdt/dts/dockstar.dts
===================================================================
--- trunk/sys/boot/fdt/dts/dockstar.dts 2018-06-02 00:06:07 UTC (rev 10204)
+++ trunk/sys/boot/fdt/dts/dockstar.dts 2018-06-02 12:34:49 UTC (rev 10205)
@@ -1,3 +1,4 @@
+/* $MidnightBSD$ */
/*
* Copyright (c) 2010 The FreeBSD Foundation
* All rights reserved.
Added: trunk/sys/boot/fdt/dts/mips/beri-netfpga.dts
===================================================================
--- trunk/sys/boot/fdt/dts/mips/beri-netfpga.dts (rev 0)
+++ trunk/sys/boot/fdt/dts/mips/beri-netfpga.dts 2018-06-02 12:34:49 UTC (rev 10205)
@@ -0,0 +1,157 @@
+/* $MidnightBSD$ */
+/*-
+ * Copyright (c) 2012-2013 Robert N. M. Watson
+ * Copyright (c) 2013 SRI International
+ * Copyright (c) 2013-2014 Bjoern A. Zeeb
+ * All rights reserved.
+ *
+ * This software was developed by SRI International and the University of
+ * Cambridge Computer Laboratory under DARPA/AFRL contract (FA8750-10-C-0237)
+ * ("CTSRD"), as part of the DARPA CRASH research programme.
+ *
+ * This software was developed by SRI International and the University of
+ * Cambridge Computer Laboratory under DARPA/AFRL contract (FA8750-11-C-0249)
+ * ("MRC2"), as part of the DARPA MRC research programme.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ * $FreeBSD: stable/10/sys/boot/fdt/dts/mips/beri-netfpga.dts 270061 2014-08-16 14:30:46Z bz $
+ */
+
+/dts-v1/;
+
+/*
+ * Device names here have been largely made up on the spot, especially for the
+ * "compatible" strings, and might want to be revised.
+ */
+
+/ {
+ model = "SRI/Cambridge Beri (NetFPGA)";
+ compatible = "sri-cambridge,beri-netfpga";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ /*
+ * Secondary CPUs all start disabled and use the
+ * spin-table enable method. cpu-release-addr must be
+ * specified for each cpu other than cpu at 0. Values of
+ * cpu-release-addr grow down from 0x100000 (kernel).
+ */
+ status = "disabled";
+ enable-method = "spin-table";
+
+ cpu at 0 {
+ device-type = "cpu";
+ compatible = "sri-cambridge,beri";
+
+ reg = <0 1>;
+ status = "okay";
+ };
+
+/*
+ cpu at 1 {
+ device-type = "cpu";
+ compatible = "sri-cambridge,beri";
+
+ reg = <1 1>;
+ // XXX: should we need cached prefix?
+ cpu-release-addr = <0xffffffff 0x800fffe0>;
+ };
+*/
+ };
+
+ soc {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ #interrupt-cells = <1>;
+
+ /*
+ * Declare mips,mips4k since BERI doesn't (yet) have a PIC, so
+ * we use mips4k coprocessor 0 interrupt management directly.
+ */
+ compatible = "simple-bus", "mips,mips4k";
+ ranges = <>;
+
+ memory {
+ device_type = "memory";
+ reg = <0x0 0x0FFFFFFF>; // ~256M at 0x0
+ };
+
+ beripic: beripic at 7f804000 {
+ compatible = "sri-cambridge,beri-pic";
+ interrupt-controller;
+ #address-cells = <0>;
+ #interrupt-cells = <1>;
+ reg = <0x7f804000 0x400
+ 0x7f806000 0x10
+ 0x7f806080 0x10
+ 0x7f806100 0x10>;
+ interrupts = <0 1 2 3 4>;
+ hard-interrupt-sources = <64>;
+ soft-interrupt-sources = <64>;
+ };
+
+ serial0: serial at 7f000000 {
+ compatible = "altera,jtag_uart-11_0";
+ reg = <0x7f000000 0x40>;
+ interrupts = <0>;
+ interrupt-parent = <&beripic>;
+ };
+
+/*
+ serial0: serial at 7f002100 {
+ compatible = "ns16550";
+ reg = <0x7f002100 0x20>;
+ reg-shift = <2>;
+ clock-frequency = <100000000>;
+ interrupts = <8>;
+ interrupt-parent = <&beripic>;
+ };
+*/
+
+ ethernet at 7f005000 {
+ compatible = "netfpag10g,nf10bmac";
+ // LOOP, TX, RX, INTR
+ reg = <0x7f005000 0x20
+ 0x7f005020 0x30
+ 0x7f005050 0x30
+ 0x7f005100 0x10>;
+ // RX
+ interrupts = <1>;
+ interrupt-parent = <&beripic>;
+ };
+ };
+
+ aliases {
+ serial0 = &serial0;
+ };
+
+ chosen {
+ stdin = "serial0";
+ stdout = "serial0";
+ bootargs = "-v";
+ };
+};
Property changes on: trunk/sys/boot/fdt/dts/mips/beri-netfpga.dts
___________________________________________________________________
Added: svn:eol-style
## -0,0 +1 ##
+native
\ No newline at end of property
Added: svn:keywords
## -0,0 +1 ##
+MidnightBSD=%H
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+text/plain
\ No newline at end of property
Added: trunk/sys/boot/fdt/dts/mips/beri-sim.dts
===================================================================
--- trunk/sys/boot/fdt/dts/mips/beri-sim.dts (rev 0)
+++ trunk/sys/boot/fdt/dts/mips/beri-sim.dts 2018-06-02 12:34:49 UTC (rev 10205)
@@ -0,0 +1,145 @@
+/* $MidnightBSD$ */
+/*-
+ * Copyright (c) 2012-2013 Robert N. M. Watson
+ * Copyright (c) 2013 SRI International
+ * All rights reserved.
+ *
+ * This software was developed by SRI International and the University of
+ * Cambridge Computer Laboratory under DARPA/AFRL contract (FA8750-10-C-0237)
+ * ("CTSRD"), as part of the DARPA CRASH research programme.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ * $FreeBSD: stable/10/sys/boot/fdt/dts/mips/beri-sim.dts 275426 2014-12-02 20:28:05Z brooks $
+ */
+
+/dts-v1/;
+
+/*
+ * Device names here have been largely made up on the spot, especially for the
+ * "compatible" strings, and might want to be revised.
+ *
+ * For now, use 32-bit addressing as our Avalon bus is 32-bit. However, in
+ * the future, we should likely change to 64-bit.
+ */
+
+/ {
+ model = "SRI/Cambridge BERI simulation";
+ compatible = "sri-cambridge,beri-sim";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ /*
+ * Secondary CPUs all start disabled and use the
+ * spin-table enable method. cpu-release-addr must be
+ * specified for each cpu other than cpu at 0. Values of
+ * cpu-release-addr grow down from 0x100000 (kernel).
+ */
+ status = "disabled";
+ enable-method = "spin-table";
+
+ cpu at 0 {
+ device-type = "cpu";
+ compatible = "sri-cambridge,beri";
+
+ reg = <0 1>;
+ status = "okay";
+ };
+
+/*
+ cpu at 1 {
+ device-type = "cpu";
+ compatible = "sri-cambridge,beri";
+
+ reg = <1 1>;
+ // XXX: should we need cached prefix?
+ cpu-release-addr = <0xffffffff 0x800fffe0>;
+ };
+*/
+ };
+
+ soc {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ #interrupt-cells = <1>;
+
+ /*
+ * Declare mips,mips4k since BERI doesn't (yet) have a PIC, so
+ * we use mips4k coprocessor 0 interrupt management directly.
+ */
+ compatible = "simple-bus", "mips,mips4k";
+ ranges = <>;
+
+ memory {
+ device_type = "memory";
+ reg = <0x0 0x4000000>; // 64M at 0x0
+ };
+
+ beripic0: beripic at 7f804000 {
+ compatible = "sri-cambridge,beri-pic";
+ interrupt-controller;
+ #address-cells = <0>;
+ #interrupt-cells = <1>;
+ reg = <0x7f804000 0x400
+ 0x7f806000 0x10
+ 0x7f806080 0x10
+ 0x7f806100 0x10>;
+ interrupts = <0 1 2 3 4>;
+ hard-interrupt-sources = <64>;
+ soft-interrupt-sources = <64>;
+ };
+
+ serial at 7f000000 {
+ compatible = "altera,jtag_uart-11_0";
+ reg = <0x7f000000 0x40>;
+ interrupts = <0>;
+ interrupt-parent = <&beripic0>;
+ };
+
+ serial at 7f001000 {
+ compatible = "altera,jtag_uart-11_0";
+ reg = <0x7f001000 0x40>;
+ };
+
+ serial at 7f002000 {
+ compatible = "altera,jtag_uart-11_0";
+ reg = <0x7f002000 0x40>;
+ };
+
+ sdcard at 7f008000 {
+ compatible = "altera,sdcard_11_2011";
+ reg = <0x7f008000 0x400>;
+ };
+
+ avgen at 0x7f00a000 {
+ compatible = "sri-cambridge,avgen";
+ reg = <0x7f00a000 0x14>;
+ sri-cambridge,width = <4>;
+ sri-cambridge,fileio = "rw";
+ sri-cambridge,devname = "berirom";
+ };
+ };
+};
Property changes on: trunk/sys/boot/fdt/dts/mips/beri-sim.dts
___________________________________________________________________
Added: svn:eol-style
## -0,0 +1 ##
+native
\ No newline at end of property
Added: svn:keywords
## -0,0 +1 ##
+MidnightBSD=%H
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+text/plain
\ No newline at end of property
Added: trunk/sys/boot/fdt/dts/mips/beripad-de4.dts
===================================================================
--- trunk/sys/boot/fdt/dts/mips/beripad-de4.dts (rev 0)
+++ trunk/sys/boot/fdt/dts/mips/beripad-de4.dts 2018-06-02 12:34:49 UTC (rev 10205)
@@ -0,0 +1,267 @@
+/* $MidnightBSD$ */
+/*-
+ * Copyright (c) 2012-2013 Robert N. M. Watson
+ * Copyright (c) 2013 SRI International
+ * All rights reserved.
+ *
+ * This software was developed by SRI International and the University of
+ * Cambridge Computer Laboratory under DARPA/AFRL contract (FA8750-10-C-0237)
+ * ("CTSRD"), as part of the DARPA CRASH research programme.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ * $FreeBSD: stable/10/sys/boot/fdt/dts/mips/beripad-de4.dts 275426 2014-12-02 20:28:05Z brooks $
+ */
+
+/dts-v1/;
+
+/*
+ * Device names here have been largely made up on the spot, especially for the
+ * "compatible" strings, and might want to be revised.
+ *
+ * For now, use 32-bit addressing as our Avalon bus is 32-bit. However, in
+ * the future, we should likely change to 64-bit.
+ */
+
+/ {
+ model = "SRI/Cambridge BeriPad (DE4)";
+ compatible = "sri-cambridge,beripad-de4";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ /*
+ * Secondary CPUs all start disabled and use the
+ * spin-table enable method. cpu-release-addr must be
+ * specified for each cpu other than cpu at 0. Values of
+ * cpu-release-addr grow down from 0x100000 (kernel).
+ */
+ status = "disabled";
+ enable-method = "spin-table";
+
+ cpu at 0 {
+ device-type = "cpu";
+ compatible = "sri-cambridge,beri";
+
+ reg = <0 1>;
+ status = "okay";
+ };
+
+/*
+ cpu at 1 {
+ device-type = "cpu";
+ compatible = "sri-cambridge,beri";
+
+ reg = <1 1>;
+ // XXX: should we need cached prefix?
+ cpu-release-addr = <0xffffffff 0x800fffe0>;
+ };
+*/
+ };
+
+ soc {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ #interrupt-cells = <1>;
+
+ /*
+ * Declare mips,mips4k since BERI doesn't (yet) have a PIC, so
+ * we use mips4k coprocessor 0 interrupt management directly.
+ */
+ compatible = "simple-bus", "mips,mips4k";
+ ranges = <>;
+
+ memory {
+ device_type = "memory";
+ reg = <0x0 0x40000000>; // 1G at 0x0
+ };
+
+ beripic0: beripic at 7f804000 {
+ compatible = "sri-cambridge,beri-pic";
+ interrupt-controller;
+ #address-cells = <0>;
+ #interrupt-cells = <1>;
+ reg = <0x7f804000 0x400
+ 0x7f806000 0x10
+ 0x7f806080 0x10
+ 0x7f806100 0x10>;
+ interrupts = <0 1 2 3 4>;
+ hard-interrupt-sources = <64>;
+ soft-interrupt-sources = <64>;
+ };
+
+ serial at 7f002100 {
+ compatible = "ns16550";
+ reg = <0x7f002100 0x20>;
+ reg-shift = <2>;
+ clock-frequency = <50000000>;
+ interrupts = <6>;
+ interrupt-parent = <&beripic0>;
+ };
+
+ serial at 7f000000 {
+ compatible = "altera,jtag_uart-11_0";
+ reg = <0x7f000000 0x40>;
+ interrupts = <0>;
+ interrupt-parent = <&beripic0>;
+ };
+
+ serial at 7f001000 {
+ compatible = "altera,jtag_uart-11_0";
+ reg = <0x7f001000 0x40>;
+ };
+
+ serial at 7f002000 {
+ compatible = "altera,jtag_uart-11_0";
+ reg = <0x7f002000 0x40>;
+ };
+
+ sdcard at 7f008000 {
+ compatible = "altera,sdcard_11_2011";
+ reg = <0x7f008000 0x400>;
+ };
+
+ led at 7f006000 {
+ compatible = "sri-cambridge,de4led";
+ reg = <0x7f006000 0x1>;
+ };
+
+ /*
+ * XXX-BZ keep flash before ethernet so that atse can read the
+ * Ethernet addresses for now.
+ */
+ flash at 74000000 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "cfi-flash";
+ reg = <0x74000000 0x4000000>;
+
+ /* Board configuration */
+ partition at 0 {
+ reg = <0x0 0x20000>;
+ label = "config";
+ };
+
+ /* Power up FPGA image */
+ partition at 20000 {
+ reg = <0x20000 0xc00000>;
+ label = "fpga0";
+ };
+
+ /* Secondary FPGA image (on RE_CONFIGn button) */
+ partition at C20000 {
+ reg = <0xc20000 0xc00000>;
+ label = "fpga1";
+ };
+
+ /* Space for operating system use */
+ partition at 1820000 {
+ reg = <0x1820000 0x027c0000>;
+ label = "os";
+ };
+
+ /* Second stage bootloader */
+ parition at 3fe0000 {
+ reg = <0x3fe0000 0x20000>;
+ label = "boot";
+ };
+ };
+
+ ethernet at 7f007000 {
+ compatible = "altera,atse";
+ // MAC, RX+RXC, TX+TXC.
+ reg = <0x7f007000 0x400
+ 0x7f007500 0x8
+ 0x7f007520 0x20
+ 0x7f007400 0x8
+ 0x7f007420 0x20>;
+ // RX, TX
+ interrupts = <1 2>;
+ interrupt-parent = <&beripic0>;
+ };
+
+ ethernet at 7f005000 {
+ compatible = "altera,atse";
+ // MAC, RX+RXC, TX+TXC.
+ reg = <0x7f005000 0x400
+ 0x7f005500 0x8
+ 0x7f005520 0x20
+ 0x7f005400 0x8
+ 0x7f005420 0x20>;
+ // RX, TX
+ interrupts = <11 12>;
+ interrupt-parent = <&beripic0>;
+ };
+
+ touchscreen at 70400000 {
+ compatible = "sri-cambridge,mtl";
+ reg = <0x70400000 0x1000
+ 0x70000000 0x177000
+ 0x70177000 0x2000>;
+ };
+
+ usb at 0x7f100000 {
+ compatible = "philips,isp1761";
+ reg = <0x7f100000 0x40000
+ 0x7f140000 0x4>;
+ // IRQ 4 is DC, IRQ 5 is HC.
+ interrupts = <4 5>;
+ interrupt-parent = <&beripic0>;
+ };
+
+ avgen at 0x7f009000 {
+ compatible = "sri-cambridge,avgen";
+ reg = <0x7f009000 0x2>;
+ sri-cambridge,width = <1>;
+ sri-cambridge,fileio = "r";
+ sri-cambridge,devname = "de4bsw";
+ };
+
+ avgen at 0x7f00a000 {
+ compatible = "sri-cambridge,avgen";
+ reg = <0x7f00a000 0x14>;
+ sri-cambridge,width = <4>;
+ sri-cambridge,fileio = "rw";
+ sri-cambridge,devname = "berirom";
+ };
+
+ avgen at 0x7f00c000 {
+ compatible = "sri-cambridge,avgen";
+ reg = <0x7f00c000 0x8>;
+ sri-cambridge,width = <4>;
+ sri-cambridge,fileio = "rw";
+ sri-cambridge,devname = "de4tempfan";
+ };
+
+ avgen at 0x7f100000 {
+ compatible = "sri-cambridge,avgen";
+ reg = <0x7f100000 0x40000>;
+ sri-cambridge,width = <4>;
+ sri-cambridge,fileio = "r";
+ sri-cambridge,devname = "usbmem";
+ };
+
+ };
+};
Property changes on: trunk/sys/boot/fdt/dts/mips/beripad-de4.dts
___________________________________________________________________
Added: svn:eol-style
## -0,0 +1 ##
+native
\ No newline at end of property
Added: svn:keywords
## -0,0 +1 ##
+MidnightBSD=%H
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+text/plain
\ No newline at end of property
Added: trunk/sys/boot/fdt/dts/mips/xlp-basic.dts
===================================================================
--- trunk/sys/boot/fdt/dts/mips/xlp-basic.dts (rev 0)
+++ trunk/sys/boot/fdt/dts/mips/xlp-basic.dts 2018-06-02 12:34:49 UTC (rev 10205)
@@ -0,0 +1,68 @@
+/* $MidnightBSD$ */
+/*
+ * Copyright (c) 2010 The FreeBSD Foundation
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ * Netlogic Microsystems XLP8xx Device Tree Source.
+ *
+ * $FreeBSD: stable/10/sys/boot/fdt/dts/mips/xlp-basic.dts 262614 2014-02-28 18:29:09Z imp $
+ */
+
+/dts-v1/;
+
+/ {
+ model = "netl,XLP8XX";
+ compatible = "XLP8XX";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ aliases {
+ serial0 = &serial0;
+ };
+
+ soc {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "simple-bus";
+ ranges = <0x0 0x18000000 0x04000000>;
+ bus-frequency = <0>;
+
+ serial0: serial at 30100 {
+ compatible = "ns16550";
+ reg = <0x30100 0x200>;
+ reg-shift = <2>;
+ current-speed = <115200>;
+ clock-frequency = <133000000>;
+ interrupts = <9>;
+ };
+
+ };
+
+ chosen {
+ stdin = "serial0";
+ stdout = "serial0";
+ cpumask = <0xffffffff>;
+ bootargs = "-v";
+ };
+};
Property changes on: trunk/sys/boot/fdt/dts/mips/xlp-basic.dts
___________________________________________________________________
Added: svn:eol-style
## -0,0 +1 ##
+native
\ No newline at end of property
Added: svn:keywords
## -0,0 +1 ##
+MidnightBSD=%H
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+text/plain
\ No newline at end of property
Modified: trunk/sys/boot/fdt/dts/mpc8555cds.dts
===================================================================
--- trunk/sys/boot/fdt/dts/mpc8555cds.dts 2018-06-02 00:06:07 UTC (rev 10204)
+++ trunk/sys/boot/fdt/dts/mpc8555cds.dts 2018-06-02 12:34:49 UTC (rev 10205)
@@ -1,3 +1,4 @@
+/* $MidnightBSD$ */
/*
* MPC8555 CDS Device Tree Source
*
Modified: trunk/sys/boot/fdt/dts/mpc8572ds.dts
===================================================================
--- trunk/sys/boot/fdt/dts/mpc8572ds.dts 2018-06-02 00:06:07 UTC (rev 10204)
+++ trunk/sys/boot/fdt/dts/mpc8572ds.dts 2018-06-02 12:34:49 UTC (rev 10205)
@@ -1,3 +1,4 @@
+/* $MidnightBSD$ */
/*
* MPC8572 DS Device Tree Source
*
Added: trunk/sys/boot/fdt/dts/powerpc/mpc8555cds.dts
===================================================================
--- trunk/sys/boot/fdt/dts/powerpc/mpc8555cds.dts (rev 0)
+++ trunk/sys/boot/fdt/dts/powerpc/mpc8555cds.dts 2018-06-02 12:34:49 UTC (rev 10205)
@@ -0,0 +1,444 @@
+/* $MidnightBSD$ */
+/*
+ * MPC8555 CDS Device Tree Source
+ *
+ * Copyright 2006, 2008 Freescale Semiconductor Inc. All rights reserved
+ *
+ * Neither the name of Freescale Semiconductor, Inc nor the names of
+ * its contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * Freescale hereby publishes it under the following licenses:
+ *
+ * BSD License
+ *
+ * Redistribution and use in source and binary forms, with or
+ * without modification, are permitted provided that the following
+ * conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in
+ * the documentation and/or other materials provided with the
+ * distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND
+ * CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
+ * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED
+ * TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * GNU General Public License, version 2
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA 02110-1301, USA.
+ *
+ * You may select the license of your choice.
+ *------------------------------------------------------------------
+ *
+ * $FreeBSD: stable/10/sys/boot/fdt/dts/powerpc/mpc8555cds.dts 262614 2014-02-28 18:29:09Z imp $
+ */
+
+/dts-v1/;
+
+/ {
+ model = "MPC8555CDS";
+ compatible = "MPC8555CDS", "MPC85xxCDS";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ aliases {
+ ethernet0 = &enet0;
+ ethernet1 = &enet1;
+ serial0 = &serial0;
+ serial1 = &serial1;
+ pci0 = &pci0;
+ pci1 = &pci1;
+ };
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ PowerPC,8555 at 0 {
+ device_type = "cpu";
+ reg = <0x0>;
+ d-cache-line-size = <32>; // 32 bytes
+ i-cache-line-size = <32>; // 32 bytes
+ d-cache-size = <0x8000>; // L1, 32K
+ i-cache-size = <0x8000>; // L1, 32K
+ timebase-frequency = <0>; // 33 MHz, from uboot
+ bus-frequency = <0>; // 166 MHz
+ clock-frequency = <0>; // 825 MHz, from uboot
+ next-level-cache = <&L2>;
+ };
+ };
+
+ memory {
+ device_type = "memory";
+ reg = <0x0 0x10000000>; // 256M at 0x0
+ };
+
+ localbus at e0005000 {
+ #address-cells = <2>;
+ #size-cells = <1>;
+ compatible = "fsl,lbc", "fsl,elbc";
+ reg = <0xe0005000 0x1000>;
+ interrupts = <19 2>;
+ interrupt-parent = <&mpic>;
+
+ ranges = <0x0 0x0 0xff800000 0x00800000
+ 0x1 0x0 0xff000000 0x00800000
+ 0x2 0x0 0xf8000000 0x00008000>;
+
+ nor at 0,0 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "cfi-flash";
+ reg = <0x0 0x0 0x00800000>;
+ bank-width = <2>;
+ device-width = <1>;
+ };
+
+ nor at 1,0 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "cfi-flash";
+ reg = <0x1 0x0 0x00800000>;
+ bank-width = <2>;
+ device-width = <1>;
+ };
+
+ rtc at 2,0 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "dallas,ds1553";
+ reg = <0x2 0x0 0x00008000>;
+ bank-width = <1>;
+ device-width = <1>;
+ };
+ };
+
+ soc8555 at e0000000 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ device_type = "soc";
+ compatible = "simple-bus";
+ ranges = <0x0 0xe0000000 0x100000>;
+ bus-frequency = <0>;
+
+ ecm-law at 0 {
+ compatible = "fsl,ecm-law";
+ reg = <0x0 0x1000>;
+ fsl,num-laws = <8>;
+ };
+
+ ecm at 1000 {
+ compatible = "fsl,mpc8555-ecm", "fsl,ecm";
+ reg = <0x1000 0x1000>;
+ interrupts = <17 2>;
+ interrupt-parent = <&mpic>;
+ };
+
+ memory-controller at 2000 {
+ compatible = "fsl,8555-memory-controller";
+ reg = <0x2000 0x1000>;
+ interrupt-parent = <&mpic>;
+ interrupts = <18 2>;
+ };
+
+ L2: l2-cache-controller at 20000 {
+ compatible = "fsl,8555-l2-cache-controller";
+ reg = <0x20000 0x1000>;
+ cache-line-size = <32>; // 32 bytes
+ cache-size = <0x40000>; // L2, 256K
+ interrupt-parent = <&mpic>;
+ interrupts = <16 2>;
+ };
+
+ i2c at 3000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ cell-index = <0>;
+ compatible = "fsl-i2c";
+ reg = <0x3000 0x100>;
+ interrupts = <43 2>;
+ interrupt-parent = <&mpic>;
+ dfsrr;
+ };
+
+ dma at 21300 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "fsl,mpc8555-dma", "fsl,eloplus-dma";
+ reg = <0x21300 0x4>;
+ ranges = <0x0 0x21100 0x200>;
+ cell-index = <0>;
+ dma-channel at 0 {
+ compatible = "fsl,mpc8555-dma-channel",
+ "fsl,eloplus-dma-channel";
+ reg = <0x0 0x80>;
+ cell-index = <0>;
+ interrupt-parent = <&mpic>;
+ interrupts = <20 2>;
+ };
+ dma-channel at 80 {
+ compatible = "fsl,mpc8555-dma-channel",
+ "fsl,eloplus-dma-channel";
+ reg = <0x80 0x80>;
+ cell-index = <1>;
+ interrupt-parent = <&mpic>;
+ interrupts = <21 2>;
+ };
+ dma-channel at 100 {
+ compatible = "fsl,mpc8555-dma-channel",
+ "fsl,eloplus-dma-channel";
+ reg = <0x100 0x80>;
+ cell-index = <2>;
+ interrupt-parent = <&mpic>;
+ interrupts = <22 2>;
+ };
+ dma-channel at 180 {
+ compatible = "fsl,mpc8555-dma-channel",
+ "fsl,eloplus-dma-channel";
+ reg = <0x180 0x80>;
+ cell-index = <3>;
+ interrupt-parent = <&mpic>;
+ interrupts = <23 2>;
+ };
+ };
+
+ enet0: ethernet at 24000 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ cell-index = <0>;
+ device_type = "network";
+ model = "TSEC";
+ compatible = "gianfar";
+ reg = <0x24000 0x1000>;
+ ranges = <0x0 0x24000 0x1000>;
+ local-mac-address = [ 00 00 00 00 00 00 ];
+ interrupts = <29 2 30 2 34 2>;
+ interrupt-parent = <&mpic>;
+ tbi-handle = <&tbi0>;
+ phy-handle = <&phy0>;
+
+ mdio at 520 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "fsl,gianfar-mdio";
+ reg = <0x520 0x20>;
+
+ phy0: ethernet-phy at 0 {
+ interrupt-parent = <&mpic>;
+ interrupts = <5 1>;
+ reg = <0x0>;
+ device_type = "ethernet-phy";
+ };
+ phy1: ethernet-phy at 1 {
+ interrupt-parent = <&mpic>;
+ interrupts = <5 1>;
+ reg = <0x1>;
+ device_type = "ethernet-phy";
+ };
+ tbi0: tbi-phy at 11 {
+ reg = <0x11>;
+ device_type = "tbi-phy";
+ };
+ };
+ };
+
+ enet1: ethernet at 25000 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ cell-index = <1>;
+ device_type = "network";
+ model = "TSEC";
+ compatible = "gianfar";
+ reg = <0x25000 0x1000>;
+ ranges = <0x0 0x25000 0x1000>;
+ local-mac-address = [ 00 00 00 00 00 00 ];
+ interrupts = <35 2 36 2 40 2>;
+ interrupt-parent = <&mpic>;
+ tbi-handle = <&tbi1>;
+ phy-handle = <&phy1>;
+
+ mdio at 520 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "fsl,gianfar-tbi";
+ reg = <0x520 0x20>;
+
+ tbi1: tbi-phy at 11 {
+ reg = <0x11>;
+ device_type = "tbi-phy";
+ };
+ };
+ };
+
+ serial0: serial at 4500 {
+ cell-index = <0>;
+ device_type = "serial";
+ compatible = "ns16550";
+ reg = <0x4500 0x100>; // reg base, size
+ clock-frequency = <0>; // should we fill in in uboot?
+ interrupts = <42 2>;
+ interrupt-parent = <&mpic>;
+ };
+
+ serial1: serial at 4600 {
+ cell-index = <1>;
+ device_type = "serial";
+ compatible = "ns16550";
+ reg = <0x4600 0x100>; // reg base, size
+ clock-frequency = <0>; // should we fill in in uboot?
+ interrupts = <42 2>;
+ interrupt-parent = <&mpic>;
+ };
+
+ crypto at 30000 {
+ compatible = "fsl,sec2.0";
+ reg = <0x30000 0x10000>;
+ interrupts = <45 2>;
+ interrupt-parent = <&mpic>;
+ fsl,num-channels = <4>;
+ fsl,channel-fifo-len = <24>;
+ fsl,exec-units-mask = <0x7e>;
+ fsl,descriptor-types-mask = <0x01010ebf>;
+ };
+
+ mpic: pic at 40000 {
+ interrupt-controller;
+ #address-cells = <0>;
+ #interrupt-cells = <2>;
+ reg = <0x40000 0x40000>;
+ compatible = "chrp,open-pic";
+ device_type = "open-pic";
+ };
+
+ cpm at 80000 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "fsl,mpc8555-cpm", "fsl,cpm2";
+ reg = <0x80000 0x20000>;
+ interrupts = <46 2>;
+ interrupt-parent = <&mpic>;
+ };
+ };
+
+ pci0: pci at e0008000 {
+ interrupt-map-mask = <0x1f800 0x0 0x0 0x7>;
+ interrupt-map = <
+
+ /* IDSEL 0x10 */
+ 0x8000 0x0 0x0 0x1 &mpic 0x0 0x1
+ 0x8000 0x0 0x0 0x2 &mpic 0x1 0x1
+ 0x8000 0x0 0x0 0x3 &mpic 0x2 0x1
+ 0x8000 0x0 0x0 0x4 &mpic 0x3 0x1
+
+ /* IDSEL 0x11 */
+ 0x8800 0x0 0x0 0x1 &mpic 0x0 0x1
+ 0x8800 0x0 0x0 0x2 &mpic 0x1 0x1
+ 0x8800 0x0 0x0 0x3 &mpic 0x2 0x1
+ 0x8800 0x0 0x0 0x4 &mpic 0x3 0x1
+
+ /* IDSEL 0x12 (Slot 1) */
+ 0x9000 0x0 0x0 0x1 &mpic 0x0 0x1
+ 0x9000 0x0 0x0 0x2 &mpic 0x1 0x1
+ 0x9000 0x0 0x0 0x3 &mpic 0x2 0x1
+ 0x9000 0x0 0x0 0x4 &mpic 0x3 0x1
+
+ /* IDSEL 0x13 (Slot 2) */
+ 0x9800 0x0 0x0 0x1 &mpic 0x1 0x1
+ 0x9800 0x0 0x0 0x2 &mpic 0x2 0x1
+ 0x9800 0x0 0x0 0x3 &mpic 0x3 0x1
+ 0x9800 0x0 0x0 0x4 &mpic 0x0 0x1
+
+ /* IDSEL 0x14 (Slot 3) */
+ 0xa000 0x0 0x0 0x1 &mpic 0x2 0x1
+ 0xa000 0x0 0x0 0x2 &mpic 0x3 0x1
+ 0xa000 0x0 0x0 0x3 &mpic 0x0 0x1
+ 0xa000 0x0 0x0 0x4 &mpic 0x1 0x1
+
+ /* IDSEL 0x15 (Slot 4) */
+ 0xa800 0x0 0x0 0x1 &mpic 0x3 0x1
+ 0xa800 0x0 0x0 0x2 &mpic 0x0 0x1
+ 0xa800 0x0 0x0 0x3 &mpic 0x1 0x1
+ 0xa800 0x0 0x0 0x4 &mpic 0x2 0x1
+
+ /* Bus 1 (Tundra Bridge) */
+ /* IDSEL 0x12 (ISA bridge) */
+ 0x19000 0x0 0x0 0x1 &mpic 0x0 0x1
+ 0x19000 0x0 0x0 0x2 &mpic 0x1 0x1
+ 0x19000 0x0 0x0 0x3 &mpic 0x2 0x1
+ 0x19000 0x0 0x0 0x4 &mpic 0x3 0x1>;
+ interrupt-parent = <&mpic>;
+ interrupts = <24 2>;
+ bus-range = <0 0>;
+ ranges = <0x2000000 0x0 0x80000000 0x80000000 0x0 0x10000000
+ 0x1000000 0x0 0x0 0xfee00000 0x0 0x00010000>;
+ clock-frequency = <66666666>;
+ #interrupt-cells = <1>;
+ #size-cells = <2>;
+ #address-cells = <3>;
+ reg = <0xe0008000 0x1000>;
+ compatible = "fsl,mpc8540-pci";
+ device_type = "pci";
+
+ i8259 at 19000 {
+ interrupt-controller;
+ device_type = "interrupt-controller";
+ reg = <0x19000 0x0 0x0 0x0 0x1>;
+ #address-cells = <0>;
+ #interrupt-cells = <2>;
+ compatible = "chrp,iic";
+ interrupts = <1>;
+ interrupt-parent = <&pci0>;
+ };
+ };
+
+ pci1: pci at e0009000 {
+ interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
+ interrupt-map = <
+
+ /* IDSEL 0x15 */
+ 0xa800 0x0 0x0 0x1 &mpic 0xb 0x1
+ 0xa800 0x0 0x0 0x2 &mpic 0xb 0x1
+ 0xa800 0x0 0x0 0x3 &mpic 0xb 0x1
+ 0xa800 0x0 0x0 0x4 &mpic 0xb 0x1>;
+ interrupt-parent = <&mpic>;
+ interrupts = <25 2>;
+ bus-range = <0 0>;
+ ranges = <0x2000000 0x0 0x90000000 0x90000000 0x0 0x10000000
+ 0x1000000 0x0 0x0 0xfee10000 0x0 0x00010000>;
+ clock-frequency = <66666666>;
+ #interrupt-cells = <1>;
+ #size-cells = <2>;
+ #address-cells = <3>;
+ reg = <0xe0009000 0x1000>;
+ compatible = "fsl,mpc8540-pci";
+ device_type = "pci";
+ };
+};
Property changes on: trunk/sys/boot/fdt/dts/powerpc/mpc8555cds.dts
___________________________________________________________________
Added: svn:eol-style
## -0,0 +1 ##
+native
\ No newline at end of property
Added: svn:keywords
## -0,0 +1 ##
+MidnightBSD=%H
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+text/plain
\ No newline at end of property
Added: trunk/sys/boot/fdt/dts/powerpc/mpc8572ds.dts
===================================================================
--- trunk/sys/boot/fdt/dts/powerpc/mpc8572ds.dts (rev 0)
+++ trunk/sys/boot/fdt/dts/powerpc/mpc8572ds.dts 2018-06-02 12:34:49 UTC (rev 10205)
@@ -0,0 +1,896 @@
+/* $MidnightBSD$ */
+/*
+ * MPC8572 DS Device Tree Source
+ *
+ * Copyright 2007-2009 Freescale Semiconductor Inc. All rights reserved
+ *
+ * Neither the name of Freescale Semiconductor, Inc nor the names of
+ * its contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * Freescale hereby publishes it under the following licenses:
+ *
+ * BSD License
+ *
+ * Redistribution and use in source and binary forms, with or
+ * without modification, are permitted provided that the following
+ * conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in
+ * the documentation and/or other materials provided with the
+ * distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND
+ * CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
+ * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED
+ * TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * GNU General Public License, version 2
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA 02110-1301, USA.
+ *
+ * You may select the license of your choice.
+ *------------------------------------------------------------------
+ *
+ * $FreeBSD: stable/10/sys/boot/fdt/dts/powerpc/mpc8572ds.dts 262614 2014-02-28 18:29:09Z imp $
+ */
+
+/dts-v1/;
+/ {
+ model = "fsl,MPC8572DS";
+ compatible = "fsl,MPC8572DS";
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ aliases {
+ ethernet0 = &enet0;
+ ethernet1 = &enet1;
+ ethernet2 = &enet2;
+ ethernet3 = &enet3;
+ serial0 = &serial0;
+ serial1 = &serial1;
+ pci0 = &pci0;
+ pci1 = &pci1;
+ pci2 = &pci2;
+ };
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ PowerPC,8572 at 0 {
+ device_type = "cpu";
+ reg = <0x0>;
+ d-cache-line-size = <32>; // 32 bytes
+ i-cache-line-size = <32>; // 32 bytes
+ d-cache-size = <0x8000>; // L1, 32K
+ i-cache-size = <0x8000>; // L1, 32K
+ timebase-frequency = <0>;
+ bus-frequency = <0>;
+ clock-frequency = <0>;
+ next-level-cache = <&L2>;
+ };
+
+ PowerPC,8572 at 1 {
+ device_type = "cpu";
+ reg = <0x1>;
+ d-cache-line-size = <32>; // 32 bytes
+ i-cache-line-size = <32>; // 32 bytes
+ d-cache-size = <0x8000>; // L1, 32K
+ i-cache-size = <0x8000>; // L1, 32K
+ timebase-frequency = <0>;
+ bus-frequency = <0>;
+ clock-frequency = <0>;
+ next-level-cache = <&L2>;
+ };
+ };
+
+ memory {
+ device_type = "memory";
+ };
+
+ localbus at ffe05000 {
+ #address-cells = <2>;
+ #size-cells = <1>;
+ compatible = "fsl,mpc8572-elbc", "fsl,elbc", "simple-bus";
+ reg = <0 0xffe05000 0 0x1000>;
+ interrupts = <19 2>;
+ interrupt-parent = <&mpic>;
+
+ ranges = <0x0 0x0 0x0 0xe8000000 0x08000000>;
+
+ nor at 0,0 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "cfi-flash";
+ reg = <0x0 0x0 0x8000000>;
+ bank-width = <2>;
+ device-width = <1>;
+
+ partition at 0 {
+ reg = <0x0 0x03000000>;
+ label = "ramdisk-nor";
+ read-only;
+ };
+
+ partition at 3000000 {
+ reg = <0x03000000 0x00e00000>;
+ label = "diagnostic-nor";
+ read-only;
+ };
+
+ partition at 3e00000 {
+ reg = <0x03e00000 0x00200000>;
+ label = "dink-nor";
+ read-only;
+ };
+
+ partition at 4000000 {
+ reg = <0x04000000 0x00400000>;
+ label = "kernel-nor";
+ read-only;
+ };
+
+ partition at 4400000 {
+ reg = <0x04400000 0x03b00000>;
+ label = "jffs2-nor";
+ };
+
+ partition at 7f00000 {
+ reg = <0x07f00000 0x00080000>;
+ label = "dtb-nor";
+ read-only;
+ };
+
+ partition at 7f80000 {
+ reg = <0x07f80000 0x00080000>;
+ label = "u-boot-nor";
+ read-only;
+ };
+ };
+
+ nand at 2,0 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "fsl,mpc8572-fcm-nand",
+ "fsl,elbc-fcm-nand";
+ reg = <0x2 0x0 0x40000>;
+
+ partition at 0 {
+ reg = <0x0 0x02000000>;
+ label = "u-boot-nand";
+ read-only;
+ };
+
+ partition at 2000000 {
+ reg = <0x02000000 0x10000000>;
+ label = "jffs2-nand";
+ };
+
+ partition at 12000000 {
+ reg = <0x12000000 0x08000000>;
+ label = "ramdisk-nand";
+ read-only;
+ };
+
+ partition at 1a000000 {
+ reg = <0x1a000000 0x04000000>;
+ label = "kernel-nand";
+ };
+
+ partition at 1e000000 {
+ reg = <0x1e000000 0x01000000>;
+ label = "dtb-nand";
+ read-only;
+ };
+
+ partition at 1f000000 {
+ reg = <0x1f000000 0x21000000>;
+ label = "reserved-nand";
+ };
+ };
+
+ nand at 4,0 {
+ compatible = "fsl,mpc8572-fcm-nand",
+ "fsl,elbc-fcm-nand";
+ reg = <0x4 0x0 0x40000>;
+ };
+
+ nand at 5,0 {
+ compatible = "fsl,mpc8572-fcm-nand",
+ "fsl,elbc-fcm-nand";
+ reg = <0x5 0x0 0x40000>;
+ };
+
+ nand at 6,0 {
+ compatible = "fsl,mpc8572-fcm-nand",
+ "fsl,elbc-fcm-nand";
+ reg = <0x6 0x0 0x40000>;
+ };
+ };
+
+ soc8572 at ffe00000 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ device_type = "soc";
+ compatible = "simple-bus";
+ ranges = <0x0 0 0xffe00000 0x100000>;
+ bus-frequency = <0>; // Filled out by uboot.
+
+ ecm-law at 0 {
+ compatible = "fsl,ecm-law";
+ reg = <0x0 0x1000>;
+ fsl,num-laws = <12>;
+ };
+
+ ecm at 1000 {
+ compatible = "fsl,mpc8572-ecm", "fsl,ecm";
+ reg = <0x1000 0x1000>;
+ interrupts = <17 2>;
+ interrupt-parent = <&mpic>;
+ };
+
+ memory-controller at 2000 {
+ compatible = "fsl,mpc8572-memory-controller";
+ reg = <0x2000 0x1000>;
+ interrupt-parent = <&mpic>;
+ interrupts = <18 2>;
+ };
+
+ memory-controller at 6000 {
+ compatible = "fsl,mpc8572-memory-controller";
+ reg = <0x6000 0x1000>;
+ interrupt-parent = <&mpic>;
+ interrupts = <18 2>;
+ };
+
+ L2: l2-cache-controller at 20000 {
+ compatible = "fsl,mpc8572-l2-cache-controller";
+ reg = <0x20000 0x1000>;
+ cache-line-size = <32>; // 32 bytes
+ cache-size = <0x100000>; // L2, 1M
+ interrupt-parent = <&mpic>;
+ interrupts = <16 2>;
+ };
+
+ i2c at 3000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ cell-index = <0>;
+ compatible = "fsl-i2c";
+ reg = <0x3000 0x100>;
+ interrupts = <43 2>;
+ interrupt-parent = <&mpic>;
+ dfsrr;
+ };
+
+ i2c at 3100 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ cell-index = <1>;
+ compatible = "fsl-i2c";
+ reg = <0x3100 0x100>;
+ interrupts = <43 2>;
+ interrupt-parent = <&mpic>;
+ dfsrr;
+ };
+
+ dma at c300 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "fsl,mpc8572-dma", "fsl,eloplus-dma";
+ reg = <0xc300 0x4>;
+ ranges = <0x0 0xc100 0x200>;
+ cell-index = <1>;
+ dma-channel at 0 {
+ compatible = "fsl,mpc8572-dma-channel",
+ "fsl,eloplus-dma-channel";
+ reg = <0x0 0x80>;
+ cell-index = <0>;
+ interrupt-parent = <&mpic>;
+ interrupts = <76 2>;
+ };
+ dma-channel at 80 {
+ compatible = "fsl,mpc8572-dma-channel",
+ "fsl,eloplus-dma-channel";
+ reg = <0x80 0x80>;
+ cell-index = <1>;
+ interrupt-parent = <&mpic>;
+ interrupts = <77 2>;
+ };
+ dma-channel at 100 {
+ compatible = "fsl,mpc8572-dma-channel",
+ "fsl,eloplus-dma-channel";
+ reg = <0x100 0x80>;
+ cell-index = <2>;
+ interrupt-parent = <&mpic>;
+ interrupts = <78 2>;
+ };
+ dma-channel at 180 {
+ compatible = "fsl,mpc8572-dma-channel",
+ "fsl,eloplus-dma-channel";
+ reg = <0x180 0x80>;
+ cell-index = <3>;
+ interrupt-parent = <&mpic>;
+ interrupts = <79 2>;
+ };
+ };
+
+ dma at 21300 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "fsl,mpc8572-dma", "fsl,eloplus-dma";
+ reg = <0x21300 0x4>;
+ ranges = <0x0 0x21100 0x200>;
+ cell-index = <0>;
+ dma-channel at 0 {
+ compatible = "fsl,mpc8572-dma-channel",
+ "fsl,eloplus-dma-channel";
+ reg = <0x0 0x80>;
+ cell-index = <0>;
+ interrupt-parent = <&mpic>;
+ interrupts = <20 2>;
+ };
+ dma-channel at 80 {
+ compatible = "fsl,mpc8572-dma-channel",
+ "fsl,eloplus-dma-channel";
+ reg = <0x80 0x80>;
+ cell-index = <1>;
+ interrupt-parent = <&mpic>;
+ interrupts = <21 2>;
+ };
+ dma-channel at 100 {
+ compatible = "fsl,mpc8572-dma-channel",
+ "fsl,eloplus-dma-channel";
+ reg = <0x100 0x80>;
+ cell-index = <2>;
+ interrupt-parent = <&mpic>;
+ interrupts = <22 2>;
+ };
+ dma-channel at 180 {
+ compatible = "fsl,mpc8572-dma-channel",
+ "fsl,eloplus-dma-channel";
+ reg = <0x180 0x80>;
+ cell-index = <3>;
+ interrupt-parent = <&mpic>;
+ interrupts = <23 2>;
+ };
+ };
+
+ ptp_timer: ptimer at 24e00 {
+ compatible = "fsl,gianfar-ptp-timer";
+ reg = <0x24e00 0xb0>;
+ };
+
+ enet0: ethernet at 24000 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ cell-index = <0>;
+ device_type = "network";
+ model = "eTSEC";
+ compatible = "gianfar";
+ reg = <0x24000 0x1000>;
+ ranges = <0x0 0x24000 0x1000>;
+ local-mac-address = [ 00 00 00 00 00 00 ];
+ interrupts = <29 2 30 2 34 2>;
+ interrupt-parent = <&mpic>;
+ tbi-handle = <&tbi0>;
+ phy-handle = <&phy0>;
+ ptimer-handle = < &ptp_timer >;
+ phy-connection-type = "rgmii-id";
+
+ mdio at 520 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "fsl,gianfar-mdio";
+ reg = <0x520 0x20>;
+
+ phy0: ethernet-phy at 0 {
+ interrupt-parent = <&mpic>;
+ interrupts = <10 1>;
+ reg = <0x0>;
+ };
+ phy1: ethernet-phy at 1 {
+ interrupt-parent = <&mpic>;
+ interrupts = <10 1>;
+ reg = <0x1>;
+ };
+ phy2: ethernet-phy at 2 {
+ interrupt-parent = <&mpic>;
+ interrupts = <10 1>;
+ reg = <0x2>;
+ };
+ phy3: ethernet-phy at 3 {
+ interrupt-parent = <&mpic>;
+ interrupts = <10 1>;
+ reg = <0x3>;
+ };
+
+ tbi0: tbi-phy at 11 {
+ reg = <0x11>;
+ device_type = "tbi-phy";
+ };
+ };
+ };
+
+ enet1: ethernet at 25000 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ cell-index = <1>;
+ device_type = "network";
+ model = "eTSEC";
+ compatible = "gianfar";
+ reg = <0x25000 0x1000>;
+ ranges = <0x0 0x25000 0x1000>;
+ local-mac-address = [ 00 00 00 00 00 00 ];
+ interrupts = <35 2 36 2 40 2>;
+ interrupt-parent = <&mpic>;
+ tbi-handle = <&tbi1>;
+ phy-handle = <&phy1>;
+ ptimer-handle = < &ptp_timer >;
+ phy-connection-type = "rgmii-id";
+
+ mdio at 520 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "fsl,gianfar-tbi";
+ reg = <0x520 0x20>;
+
+ tbi1: tbi-phy at 11 {
+ reg = <0x11>;
+ device_type = "tbi-phy";
+ };
+ };
+ };
+
+ enet2: ethernet at 26000 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ cell-index = <2>;
+ device_type = "network";
+ model = "eTSEC";
+ compatible = "gianfar";
+ reg = <0x26000 0x1000>;
+ ranges = <0x0 0x26000 0x1000>;
+ local-mac-address = [ 00 00 00 00 00 00 ];
+ interrupts = <31 2 32 2 33 2>;
+ interrupt-parent = <&mpic>;
+ tbi-handle = <&tbi2>;
+ phy-handle = <&phy2>;
+ ptimer-handle = < &ptp_timer >;
+ phy-connection-type = "rgmii-id";
+
+ mdio at 520 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "fsl,gianfar-tbi";
+ reg = <0x520 0x20>;
+
+ tbi2: tbi-phy at 11 {
+ reg = <0x11>;
+ device_type = "tbi-phy";
+ };
+ };
+ };
+
+ enet3: ethernet at 27000 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ cell-index = <3>;
+ device_type = "network";
+ model = "eTSEC";
+ compatible = "gianfar";
+ reg = <0x27000 0x1000>;
+ ranges = <0x0 0x27000 0x1000>;
+ local-mac-address = [ 00 00 00 00 00 00 ];
+ interrupts = <37 2 38 2 39 2>;
+ interrupt-parent = <&mpic>;
+ tbi-handle = <&tbi3>;
+ phy-handle = <&phy3>;
+ phy-connection-type = "rgmii-id";
+
+ mdio at 520 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "fsl,gianfar-tbi";
+ reg = <0x520 0x20>;
+
+ tbi3: tbi-phy at 11 {
+ reg = <0x11>;
+ device_type = "tbi-phy";
+ };
+ };
+ };
+
+ serial0: serial at 4500 {
+ cell-index = <0>;
+ device_type = "serial";
+ compatible = "ns16550";
+ reg = <0x4500 0x100>;
+ clock-frequency = <0>;
+ interrupts = <42 2>;
+ interrupt-parent = <&mpic>;
+ };
+
+ serial1: serial at 4600 {
+ cell-index = <1>;
+ device_type = "serial";
+ compatible = "ns16550";
+ reg = <0x4600 0x100>;
+ clock-frequency = <0>;
+ interrupts = <42 2>;
+ interrupt-parent = <&mpic>;
+ };
+
+ global-utilities at e0000 { //global utilities block
+ compatible = "fsl,mpc8572-guts";
+ reg = <0xe0000 0x1000>;
+ fsl,has-rstcr;
+ };
+
+ power at e0070{
+ compatible = "fsl,mpc8548-pmc";
+ reg = <0xe0070 0x14>;
+ };
+
+ timer at 41100 {
+ compatible = "fsl,mpic-global-timer";
+ reg = <0x41100 0x204>;
+ interrupts = <0xf7 0x2>;
+ interrupt-parent = <&mpic>;
+ };
+
+ msi at 41600 {
+ compatible = "fsl,mpc8572-msi", "fsl,mpic-msi";
+ reg = <0x41600 0x80>;
+ msi-available-ranges = <0 0x100>;
+ interrupts = <
+ 0xe0 0
+ 0xe1 0
+ 0xe2 0
+ 0xe3 0
+ 0xe4 0
+ 0xe5 0
+ 0xe6 0
+ 0xe7 0>;
+ interrupt-parent = <&mpic>;
+ };
+
+ crypto at 30000 {
+ compatible = "fsl,sec3.0", "fsl,sec2.4", "fsl,sec2.2",
+ "fsl,sec2.1", "fsl,sec2.0";
+ reg = <0x30000 0x10000>;
+ interrupts = <45 2 58 2>;
+ interrupt-parent = <&mpic>;
+ fsl,num-channels = <4>;
+ fsl,channel-fifo-len = <24>;
+ fsl,exec-units-mask = <0x9fe>;
+ fsl,descriptor-types-mask = <0x3ab0ebf>;
+ };
+
+ /* PME (pattern-matcher) */
+ pme at 10000 {
+ device_type = "pme";
+ compatible = "pme8572";
+ reg = <0x10000 0x5000>;
+ interrupts = <0x39 0x2 0x40 0x2 0x41 0x2 0x42 0x2 0x43 0x2>;
+ interrupt-parent = <&mpic>;
+ };
+
+ mpic: pic at 40000 {
+ interrupt-controller;
+ #address-cells = <0>;
+ #interrupt-cells = <2>;
+ reg = <0x40000 0x40000>;
+ compatible = "chrp,open-pic";
+ device_type = "open-pic";
+ };
+ };
+
+ pci0: pcie at ffe08000 {
+ compatible = "fsl,mpc8548-pcie";
+ device_type = "pci";
+ #interrupt-cells = <1>;
+ #size-cells = <2>;
+ #address-cells = <3>;
+ reg = <0 0xffe08000 0 0x1000>;
+ bus-range = <0 255>;
+ ranges = <0x2000000 0x0 0xa0000000 0 0xa0000000 0x0 0x10000000
+ 0x1000000 0x0 0x00000000 0 0xfee20000 0x0 0x00010000>;
+ clock-frequency = <33333333>;
+ interrupt-parent = <&mpic>;
+ interrupts = <24 2>;
+ interrupt-map-mask = <0xff00 0x0 0x0 0x7>;
+ interrupt-map = <
+ /* IDSEL 0x11 func 0 - PCI slot 1 */
+ 0x8800 0x0 0x0 0x1 &mpic 0x2 0x1
+ 0x8800 0x0 0x0 0x2 &mpic 0x3 0x1
+ 0x8800 0x0 0x0 0x3 &mpic 0x4 0x1
+ 0x8800 0x0 0x0 0x4 &mpic 0x1 0x1
+
+ /* IDSEL 0x11 func 1 - PCI slot 1 */
+ 0x8900 0x0 0x0 0x1 &mpic 0x2 0x1
+ 0x8900 0x0 0x0 0x2 &mpic 0x3 0x1
+ 0x8900 0x0 0x0 0x3 &mpic 0x4 0x1
+ 0x8900 0x0 0x0 0x4 &mpic 0x1 0x1
+
+ /* IDSEL 0x11 func 2 - PCI slot 1 */
+ 0x8a00 0x0 0x0 0x1 &mpic 0x2 0x1
+ 0x8a00 0x0 0x0 0x2 &mpic 0x3 0x1
+ 0x8a00 0x0 0x0 0x3 &mpic 0x4 0x1
+ 0x8a00 0x0 0x0 0x4 &mpic 0x1 0x1
+
+ /* IDSEL 0x11 func 3 - PCI slot 1 */
+ 0x8b00 0x0 0x0 0x1 &mpic 0x2 0x1
+ 0x8b00 0x0 0x0 0x2 &mpic 0x3 0x1
+ 0x8b00 0x0 0x0 0x3 &mpic 0x4 0x1
+ 0x8b00 0x0 0x0 0x4 &mpic 0x1 0x1
+
+ /* IDSEL 0x11 func 4 - PCI slot 1 */
+ 0x8c00 0x0 0x0 0x1 &mpic 0x2 0x1
+ 0x8c00 0x0 0x0 0x2 &mpic 0x3 0x1
+ 0x8c00 0x0 0x0 0x3 &mpic 0x4 0x1
+ 0x8c00 0x0 0x0 0x4 &mpic 0x1 0x1
+
+ /* IDSEL 0x11 func 5 - PCI slot 1 */
+ 0x8d00 0x0 0x0 0x1 &mpic 0x2 0x1
+ 0x8d00 0x0 0x0 0x2 &mpic 0x3 0x1
+ 0x8d00 0x0 0x0 0x3 &mpic 0x4 0x1
+ 0x8d00 0x0 0x0 0x4 &mpic 0x1 0x1
+
+ /* IDSEL 0x11 func 6 - PCI slot 1 */
+ 0x8e00 0x0 0x0 0x1 &mpic 0x2 0x1
+ 0x8e00 0x0 0x0 0x2 &mpic 0x3 0x1
+ 0x8e00 0x0 0x0 0x3 &mpic 0x4 0x1
+ 0x8e00 0x0 0x0 0x4 &mpic 0x1 0x1
+
+ /* IDSEL 0x11 func 7 - PCI slot 1 */
+ 0x8f00 0x0 0x0 0x1 &mpic 0x2 0x1
+ 0x8f00 0x0 0x0 0x2 &mpic 0x3 0x1
+ 0x8f00 0x0 0x0 0x3 &mpic 0x4 0x1
+ 0x8f00 0x0 0x0 0x4 &mpic 0x1 0x1
+
+ /* IDSEL 0x12 func 0 - PCI slot 2 */
+ 0x9000 0x0 0x0 0x1 &mpic 0x3 0x1
+ 0x9000 0x0 0x0 0x2 &mpic 0x4 0x1
+ 0x9000 0x0 0x0 0x3 &mpic 0x1 0x1
+ 0x9000 0x0 0x0 0x4 &mpic 0x2 0x1
+
+ /* IDSEL 0x12 func 1 - PCI slot 2 */
+ 0x9100 0x0 0x0 0x1 &mpic 0x3 0x1
+ 0x9100 0x0 0x0 0x2 &mpic 0x4 0x1
+ 0x9100 0x0 0x0 0x3 &mpic 0x1 0x1
+ 0x9100 0x0 0x0 0x4 &mpic 0x2 0x1
+
+ /* IDSEL 0x12 func 2 - PCI slot 2 */
+ 0x9200 0x0 0x0 0x1 &mpic 0x3 0x1
+ 0x9200 0x0 0x0 0x2 &mpic 0x4 0x1
+ 0x9200 0x0 0x0 0x3 &mpic 0x1 0x1
+ 0x9200 0x0 0x0 0x4 &mpic 0x2 0x1
+
+ /* IDSEL 0x12 func 3 - PCI slot 2 */
+ 0x9300 0x0 0x0 0x1 &mpic 0x3 0x1
+ 0x9300 0x0 0x0 0x2 &mpic 0x4 0x1
+ 0x9300 0x0 0x0 0x3 &mpic 0x1 0x1
+ 0x9300 0x0 0x0 0x4 &mpic 0x2 0x1
+
+ /* IDSEL 0x12 func 4 - PCI slot 2 */
+ 0x9400 0x0 0x0 0x1 &mpic 0x3 0x1
+ 0x9400 0x0 0x0 0x2 &mpic 0x4 0x1
+ 0x9400 0x0 0x0 0x3 &mpic 0x1 0x1
+ 0x9400 0x0 0x0 0x4 &mpic 0x2 0x1
+
+ /* IDSEL 0x12 func 5 - PCI slot 2 */
+ 0x9500 0x0 0x0 0x1 &mpic 0x3 0x1
+ 0x9500 0x0 0x0 0x2 &mpic 0x4 0x1
+ 0x9500 0x0 0x0 0x3 &mpic 0x1 0x1
+ 0x9500 0x0 0x0 0x4 &mpic 0x2 0x1
+
+ /* IDSEL 0x12 func 6 - PCI slot 2 */
+ 0x9600 0x0 0x0 0x1 &mpic 0x3 0x1
+ 0x9600 0x0 0x0 0x2 &mpic 0x4 0x1
+ 0x9600 0x0 0x0 0x3 &mpic 0x1 0x1
+ 0x9600 0x0 0x0 0x4 &mpic 0x2 0x1
+
+ /* IDSEL 0x12 func 7 - PCI slot 2 */
+ 0x9700 0x0 0x0 0x1 &mpic 0x3 0x1
+ 0x9700 0x0 0x0 0x2 &mpic 0x4 0x1
+ 0x9700 0x0 0x0 0x3 &mpic 0x1 0x1
+ 0x9700 0x0 0x0 0x4 &mpic 0x2 0x1
+
+ // IDSEL 0x1c USB
+ 0xe000 0x0 0x0 0x1 &i8259 0xc 0x2
+ 0xe100 0x0 0x0 0x2 &i8259 0x9 0x2
+ 0xe200 0x0 0x0 0x3 &i8259 0xa 0x2
+ 0xe300 0x0 0x0 0x4 &i8259 0xb 0x2
+
+ // IDSEL 0x1d Audio
+ 0xe800 0x0 0x0 0x1 &i8259 0x6 0x2
+
+ // IDSEL 0x1e Legacy
+ 0xf000 0x0 0x0 0x1 &i8259 0x7 0x2
+ 0xf100 0x0 0x0 0x1 &i8259 0x7 0x2
+
+ // IDSEL 0x1f IDE/SATA
+ 0xf800 0x0 0x0 0x1 &i8259 0xe 0x2
+ 0xf900 0x0 0x0 0x1 &i8259 0x5 0x2
+
+ >;
+
+ pcie at 0 {
+ reg = <0x0 0x0 0x0 0x0 0x0>;
+ #size-cells = <2>;
+ #address-cells = <3>;
+ device_type = "pci";
+ ranges = <0x2000000 0x0 0xa0000000
+ 0x2000000 0x0 0xa0000000
+ 0x0 0x10000000
+
+ 0x1000000 0x0 0x0
+ 0x1000000 0x0 0x0
+ 0x0 0x10000>;
+ uli1575 at 0 {
+ reg = <0x0 0x0 0x0 0x0 0x0>;
+ #size-cells = <2>;
+ #address-cells = <3>;
+ ranges = <0x2000000 0x0 0xa0000000
+ 0x2000000 0x0 0xa0000000
+ 0x0 0x10000000
+
+ 0x1000000 0x0 0x0
+ 0x1000000 0x0 0x0
+ 0x0 0x10000>;
+ isa at 1e {
+ device_type = "isa";
+ #interrupt-cells = <2>;
+ #size-cells = <1>;
+ #address-cells = <2>;
+ reg = <0xf000 0x0 0x0 0x0 0x0>;
+ ranges = <0x1 0x0 0x1000000 0x0 0x0
+ 0x1000>;
+ interrupt-parent = <&i8259>;
+
+ i8259: interrupt-controller at 20 {
+ reg = <0x1 0x20 0x2
+ 0x1 0xa0 0x2
+ 0x1 0x4d0 0x2>;
+ interrupt-controller;
+ device_type = "interrupt-controller";
+ #address-cells = <0>;
+ #interrupt-cells = <2>;
+ compatible = "chrp,iic";
+ interrupts = <9 2>;
+ interrupt-parent = <&mpic>;
+ };
+
+ i8042 at 60 {
+ #size-cells = <0>;
+ #address-cells = <1>;
+ reg = <0x1 0x60 0x1 0x1 0x64 0x1>;
+ interrupts = <1 3 12 3>;
+ interrupt-parent =
+ <&i8259>;
+
+ keyboard at 0 {
+ reg = <0x0>;
+ compatible = "pnpPNP,303";
+ };
+
+ mouse at 1 {
+ reg = <0x1>;
+ compatible = "pnpPNP,f03";
+ };
+ };
+
+ rtc at 70 {
+ compatible = "pnpPNP,b00";
+ reg = <0x1 0x70 0x2>;
+ };
+
+ gpio at 400 {
+ reg = <0x1 0x400 0x80>;
+ };
+ };
+ };
+ };
+
+ };
+
+ pci1: pcie at ffe09000 {
+ compatible = "fsl,mpc8548-pcie";
+ device_type = "pci";
+ #interrupt-cells = <1>;
+ #size-cells = <2>;
+ #address-cells = <3>;
+ reg = <0 0xffe09000 0 0x1000>;
+ bus-range = <0 255>;
+ ranges = <0x2000000 0x0 0x90000000 0 0x90000000 0x0 0x10000000
+ 0x1000000 0x0 0x00000000 0 0xfee10000 0x0 0x00010000>;
+ clock-frequency = <33333333>;
+ interrupt-parent = <&mpic>;
+ interrupts = <25 2>;
+ interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
+ interrupt-map = <
+ /* IDSEL 0x0 */
+ 0000 0x0 0x0 0x1 &mpic 0x4 0x1
+ 0000 0x0 0x0 0x2 &mpic 0x5 0x1
+ 0000 0x0 0x0 0x3 &mpic 0x6 0x1
+ 0000 0x0 0x0 0x4 &mpic 0x7 0x1
+ >;
+ pcie at 0 {
+ reg = <0x0 0x0 0x0 0x0 0x0>;
+ #size-cells = <2>;
+ #address-cells = <3>;
+ device_type = "pci";
+ ranges = <0x2000000 0x0 0x90000000
+ 0x2000000 0x0 0x90000000
+ 0x0 0x10000000
+
+ 0x1000000 0x0 0x0
+ 0x1000000 0x0 0x0
+ 0x0 0x10000>;
+ };
+ };
+
+ pci2: pcie at ffe0a000 {
+ compatible = "fsl,mpc8548-pcie";
+ device_type = "pci";
+ #interrupt-cells = <1>;
+ #size-cells = <2>;
+ #address-cells = <3>;
+ reg = <0 0xffe0a000 0 0x1000>;
+ bus-range = <0 255>;
+ ranges = <0x2000000 0x0 0x80000000 0 0x80000000 0x0 0x10000000
+ 0x1000000 0x0 0x00000000 0 0xfee00000 0x0 0x00010000>;
+ clock-frequency = <33333333>;
+ interrupt-parent = <&mpic>;
+ interrupts = <26 2>;
+ interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
+ interrupt-map = <
+ /* IDSEL 0x0 */
+ 0000 0x0 0x0 0x1 &mpic 0x0 0x1
+ 0000 0x0 0x0 0x2 &mpic 0x1 0x1
+ 0000 0x0 0x0 0x3 &mpic 0x2 0x1
+ 0000 0x0 0x0 0x4 &mpic 0x3 0x1
+ >;
+ pcie at 0 {
+ reg = <0x0 0x0 0x0 0x0 0x0>;
+ #size-cells = <2>;
+ #address-cells = <3>;
+ device_type = "pci";
+ ranges = <0x2000000 0x0 0x80000000
+ 0x2000000 0x0 0x80000000
+ 0x0 0x10000000
+
+ 0x1000000 0x0 0x0
+ 0x1000000 0x0 0x0
+ 0x0 0x10000>;
+ };
+ };
+};
Property changes on: trunk/sys/boot/fdt/dts/powerpc/mpc8572ds.dts
___________________________________________________________________
Added: svn:eol-style
## -0,0 +1 ##
+native
\ No newline at end of property
Added: svn:keywords
## -0,0 +1 ##
+MidnightBSD=%H
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+text/plain
\ No newline at end of property
Added: trunk/sys/boot/fdt/dts/powerpc/p1020rdb.dts
===================================================================
--- trunk/sys/boot/fdt/dts/powerpc/p1020rdb.dts (rev 0)
+++ trunk/sys/boot/fdt/dts/powerpc/p1020rdb.dts 2018-06-02 12:34:49 UTC (rev 10205)
@@ -0,0 +1,628 @@
+/* $MidnightBSD$ */
+/*
+ * P1020 RDB Device Tree Source
+ *
+ * Copyright 2009 Freescale Semiconductor Inc.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * * Neither the name of Freescale Semiconductor nor the
+ * names of its contributors may be used to endorse or promote products
+ * derived from this software without specific prior written permission.
+ *
+ *
+ * ALTERNATIVELY, this software may be distributed under the terms of the
+ * GNU General Public License ("GPL") as published by the Free Software
+ * Foundation, either version 2 of that License or (at your option) any
+ * later version.
+ *
+ * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+/* $FreeBSD: stable/10/sys/boot/fdt/dts/powerpc/p1020rdb.dts 266364 2014-05-17 21:55:00Z ian $ */
+
+/dts-v1/;
+
+/ {
+ model = "fsl,P1020";
+ compatible = "fsl,P1020RDB";
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ aliases {
+ serial0 = &serial0;
+ serial1 = &serial1;
+ ethernet0 = &enet0;
+ ethernet1 = &enet1;
+ ethernet2 = &enet2;
+ pci0 = &pci0;
+ pci1 = &pci1;
+ };
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ PowerPC,P1020 at 0 {
+ device_type = "cpu";
+ reg = <0x0>;
+ next-level-cache = <&L2>;
+ };
+
+ PowerPC,P1020 at 1 {
+ device_type = "cpu";
+ reg = <0x1>;
+ next-level-cache = <&L2>;
+ };
+ };
+
+ memory {
+ device_type = "memory";
+ };
+
+ localbus at ffe05000 {
+ #address-cells = <2>;
+ #size-cells = <1>;
+ compatible = "fsl,p1020-elbc", "fsl,elbc", "simple-bus";
+ reg = <0 0xffe05000 0 0x1000>;
+ interrupts = <19 2>;
+ interrupt-parent = <&mpic>;
+
+ /* NOR, NAND Flashes and Vitesse 5 port L2 switch */
+ ranges = <0x0 0x0 0x0 0xef000000 0x01000000
+ 0x1 0x0 0x0 0xffa00000 0x00040000
+ 0x2 0x0 0x0 0xffb00000 0x00020000>;
+
+ nor at 0,0 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "cfi-flash";
+ reg = <0x0 0x0 0x1000000>;
+ bank-width = <2>;
+ device-width = <1>;
+
+ partition at 0 {
+ /* This location must not be altered */
+ /* 256KB for Vitesse 7385 Switch firmware */
+ reg = <0x0 0x00040000>;
+ label = "NOR (RO) Vitesse-7385 Firmware";
+ read-only;
+ };
+
+ partition at 40000 {
+ /* 256KB for DTB Image */
+ reg = <0x00040000 0x00040000>;
+ label = "NOR (RO) DTB Image";
+ read-only;
+ };
+
+ partition at 80000 {
+ /* 3.5 MB for Linux Kernel Image */
+ reg = <0x00080000 0x00380000>;
+ label = "NOR (RO) Linux Kernel Image";
+ read-only;
+ };
+
+ partition at 400000 {
+ /* 11MB for JFFS2 based Root file System */
+ reg = <0x00400000 0x00b00000>;
+ label = "NOR (RW) JFFS2 Root File System";
+ };
+
+ partition at f00000 {
+ /* This location must not be altered */
+ /* 512KB for u-boot Bootloader Image */
+ /* 512KB for u-boot Environment Variables */
+ reg = <0x00f00000 0x00100000>;
+ label = "NOR (RO) U-Boot Image";
+ read-only;
+ };
+ };
+
+ nand at 1,0 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "fsl,p1020-fcm-nand",
+ "fsl,elbc-fcm-nand";
+ reg = <0x1 0x0 0x40000>;
+
+ partition at 0 {
+ /* This location must not be altered */
+ /* 1MB for u-boot Bootloader Image */
+ reg = <0x0 0x00100000>;
+ label = "NAND (RO) U-Boot Image";
+ read-only;
+ };
+
+ partition at 100000 {
+ /* 1MB for DTB Image */
+ reg = <0x00100000 0x00100000>;
+ label = "NAND (RO) DTB Image";
+ read-only;
+ };
+
+ partition at 200000 {
+ /* 4MB for Linux Kernel Image */
+ reg = <0x00200000 0x00400000>;
+ label = "NAND (RO) Linux Kernel Image";
+ read-only;
+ };
+
+ partition at 600000 {
+ /* 4MB for Compressed Root file System Image */
+ reg = <0x00600000 0x00400000>;
+ label = "NAND (RO) Compressed RFS Image";
+ read-only;
+ };
+
+ partition at a00000 {
+ /* 7MB for JFFS2 based Root file System */
+ reg = <0x00a00000 0x00700000>;
+ label = "NAND (RW) JFFS2 Root File System";
+ };
+
+ partition at 1100000 {
+ /* 15MB for JFFS2 based Root file System */
+ reg = <0x01100000 0x00f00000>;
+ label = "NAND (RW) Writable User area";
+ };
+ };
+
+ L2switch at 2,0 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "vitesse-7385";
+ reg = <0x2 0x0 0x20000>;
+ };
+
+ };
+
+ soc at ffe00000 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ device_type = "soc";
+ compatible = "fsl,p1020-immr", "simple-bus";
+ ranges = <0x0 0x0 0xffe00000 0x100000>;
+ bus-frequency = <0>; // Filled out by uboot.
+
+ ecm-law at 0 {
+ compatible = "fsl,ecm-law";
+ reg = <0x0 0x1000>;
+ fsl,num-laws = <12>;
+ };
+
+ ecm at 1000 {
+ compatible = "fsl,p1020-ecm", "fsl,ecm";
+ reg = <0x1000 0x1000>;
+ interrupts = <16 2>;
+ interrupt-parent = <&mpic>;
+ };
+
+ memory-controller at 2000 {
+ compatible = "fsl,p1020-memory-controller";
+ reg = <0x2000 0x1000>;
+ interrupt-parent = <&mpic>;
+ interrupts = <16 2>;
+ };
+
+ i2c at 3000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ cell-index = <0>;
+ compatible = "fsl-i2c";
+ reg = <0x3000 0x100>;
+ interrupts = <43 2>;
+ interrupt-parent = <&mpic>;
+ dfsrr;
+ rtc at 68 {
+ compatible = "dallas,ds1339";
+ reg = <0x68>;
+ };
+ };
+
+ i2c at 3100 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ cell-index = <1>;
+ compatible = "fsl-i2c";
+ reg = <0x3100 0x100>;
+ interrupts = <43 2>;
+ interrupt-parent = <&mpic>;
+ dfsrr;
+ };
+
+ serial0: serial at 4500 {
+ cell-index = <0>;
+ device_type = "serial";
+ compatible = "ns16550";
+ reg = <0x4500 0x100>;
+ clock-frequency = <0>;
+ interrupts = <42 2>;
+ interrupt-parent = <&mpic>;
+ };
+
+ serial1: serial at 4600 {
+ cell-index = <1>;
+ device_type = "serial";
+ compatible = "ns16550";
+ reg = <0x4600 0x100>;
+ clock-frequency = <0>;
+ interrupts = <42 2>;
+ interrupt-parent = <&mpic>;
+ };
+
+ spi at 7000 {
+ cell-index = <0>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "fsl,espi";
+ reg = <0x7000 0x1000>;
+ interrupts = <59 0x2>;
+ interrupt-parent = <&mpic>;
+ mode = "cpu";
+
+ fsl_m25p80 at 0 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "fsl,espi-flash";
+ reg = <0>;
+ linux,modalias = "fsl_m25p80";
+ modal = "s25sl128b";
+ spi-max-frequency = <50000000>;
+ mode = <0>;
+
+ partition at 0 {
+ /* 512KB for u-boot Bootloader Image */
+ reg = <0x0 0x00080000>;
+ label = "SPI (RO) U-Boot Image";
+ read-only;
+ };
+
+ partition at 80000 {
+ /* 512KB for DTB Image */
+ reg = <0x00080000 0x00080000>;
+ label = "SPI (RO) DTB Image";
+ read-only;
+ };
+
+ partition at 100000 {
+ /* 4MB for Linux Kernel Image */
+ reg = <0x00100000 0x00400000>;
+ label = "SPI (RO) Linux Kernel Image";
+ read-only;
+ };
+
+ partition at 500000 {
+ /* 4MB for Compressed RFS Image */
+ reg = <0x00500000 0x00400000>;
+ label = "SPI (RO) Compressed RFS Image";
+ read-only;
+ };
+
+ partition at 900000 {
+ /* 7MB for JFFS2 based RFS */
+ reg = <0x00900000 0x00700000>;
+ label = "SPI (RW) JFFS2 RFS";
+ };
+ };
+ };
+
+ gpio: gpio-controller at f000 {
+ #gpio-cells = <2>;
+ compatible = "fsl,mpc8572-gpio";
+ reg = <0xf000 0x100>;
+ interrupts = <47 0x2>;
+ interrupt-parent = <&mpic>;
+ gpio-controller;
+ };
+
+ L2: l2-cache-controller at 20000 {
+ compatible = "fsl,p1020-l2-cache-controller";
+ reg = <0x20000 0x1000>;
+ cache-line-size = <32>; // 32 bytes
+ cache-size = <0x40000>; // L2,256K
+ interrupt-parent = <&mpic>;
+ interrupts = <16 2>;
+ };
+
+ dma at 21300 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "fsl,eloplus-dma";
+ reg = <0x21300 0x4>;
+ ranges = <0x0 0x21100 0x200>;
+ cell-index = <0>;
+ dma-channel at 0 {
+ compatible = "fsl,eloplus-dma-channel";
+ reg = <0x0 0x80>;
+ cell-index = <0>;
+ interrupt-parent = <&mpic>;
+ interrupts = <20 2>;
+ };
+ dma-channel at 80 {
+ compatible = "fsl,eloplus-dma-channel";
+ reg = <0x80 0x80>;
+ cell-index = <1>;
+ interrupt-parent = <&mpic>;
+ interrupts = <21 2>;
+ };
+ dma-channel at 100 {
+ compatible = "fsl,eloplus-dma-channel";
+ reg = <0x100 0x80>;
+ cell-index = <2>;
+ interrupt-parent = <&mpic>;
+ interrupts = <22 2>;
+ };
+ dma-channel at 180 {
+ compatible = "fsl,eloplus-dma-channel";
+ reg = <0x180 0x80>;
+ cell-index = <3>;
+ interrupt-parent = <&mpic>;
+ interrupts = <23 2>;
+ };
+ };
+
+ mdio at 24000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "fsl,etsec2-mdio";
+ reg = <0x24000 0x1000 0xb0030 0x4>;
+
+ phy0: ethernet-phy at 0 {
+ interrupt-parent = <&mpic>;
+ interrupts = <3 1>;
+ reg = <0x0>;
+ };
+
+ phy1: ethernet-phy at 1 {
+ interrupt-parent = <&mpic>;
+ interrupts = <2 1>;
+ reg = <0x1>;
+ };
+ };
+
+ mdio at 25000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "fsl,etsec2-tbi";
+ reg = <0x25000 0x1000 0xb1030 0x4>;
+
+ tbi0: tbi-phy at 11 {
+ reg = <0x11>;
+ device_type = "tbi-phy";
+ };
+ };
+
+ enet0: ethernet at b0000 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ device_type = "network";
+ model = "eTSEC";
+ compatible = "fsl,etsec2";
+ fsl,num_rx_queues = <0x8>;
+ fsl,num_tx_queues = <0x8>;
+ local-mac-address = [ 00 00 00 00 00 00 ];
+ interrupt-parent = <&mpic>;
+ fixed-link = <1 1 1000 0 0>;
+ phy-connection-type = "rgmii-id";
+
+ queue-group at 0 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ reg = <0xb0000 0x1000>;
+ interrupts = <29 2 30 2 34 2>;
+ };
+
+ queue-group at 1 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ reg = <0xb4000 0x1000>;
+ interrupts = <17 2 18 2 24 2>;
+ };
+ };
+
+ enet1: ethernet at b1000 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ device_type = "network";
+ model = "eTSEC";
+ compatible = "fsl,etsec2";
+ fsl,num_rx_queues = <0x8>;
+ fsl,num_tx_queues = <0x8>;
+ local-mac-address = [ 00 00 00 00 00 00 ];
+ interrupt-parent = <&mpic>;
+ phy-handle = <&phy0>;
+ tbi-handle = <&tbi0>;
+ phy-connection-type = "sgmii";
+
+ queue-group at 0 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ reg = <0xb1000 0x1000>;
+ interrupts = <35 2 36 2 40 2>;
+ };
+
+ queue-group at 1 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ reg = <0xb5000 0x1000>;
+ interrupts = <51 2 52 2 67 2>;
+ };
+ };
+
+ enet2: ethernet at b2000 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ device_type = "network";
+ model = "eTSEC";
+ compatible = "fsl,etsec2";
+ fsl,num_rx_queues = <0x8>;
+ fsl,num_tx_queues = <0x8>;
+ local-mac-address = [ 00 00 00 00 00 00 ];
+ interrupt-parent = <&mpic>;
+ phy-handle = <&phy1>;
+ phy-connection-type = "rgmii-id";
+
+ queue-group at 0 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ reg = <0xb2000 0x1000>;
+ interrupts = <31 2 32 2 33 2>;
+ };
+
+ queue-group at 1 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ reg = <0xb6000 0x1000>;
+ interrupts = <25 2 26 2 27 2>;
+ };
+ };
+
+ usb at 22000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "fsl-usb2-dr";
+ reg = <0x22000 0x1000>;
+ interrupt-parent = <&mpic>;
+ interrupts = <28 0x2>;
+ phy_type = "ulpi";
+ };
+
+ /* USB2 is shared with localbus, so it must be disabled
+ by default. We can't put 'status = "disabled";' here
+ since U-Boot doesn't clear the status property when
+ it enables USB2. OTOH, U-Boot does create a new node
+ when there isn't any. So, just comment it out.
+ usb at 23000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "fsl-usb2-dr";
+ reg = <0x23000 0x1000>;
+ interrupt-parent = <&mpic>;
+ interrupts = <46 0x2>;
+ phy_type = "ulpi";
+ };
+ */
+
+ sdhci at 2e000 {
+ compatible = "fsl,p1020-esdhc", "fsl,esdhc";
+ reg = <0x2e000 0x1000>;
+ interrupts = <72 0x2>;
+ interrupt-parent = <&mpic>;
+ /* Filled in by U-Boot */
+ clock-frequency = <0>;
+ };
+
+ crypto at 30000 {
+ compatible = "fsl,sec3.1", "fsl,sec3.0", "fsl,sec2.4",
+ "fsl,sec2.2", "fsl,sec2.1", "fsl,sec2.0";
+ reg = <0x30000 0x10000>;
+ interrupts = <45 2 58 2>;
+ interrupt-parent = <&mpic>;
+ fsl,num-channels = <4>;
+ fsl,channel-fifo-len = <24>;
+ fsl,exec-units-mask = <0xbfe>;
+ fsl,descriptor-types-mask = <0x3ab0ebf>;
+ };
+
+ mpic: pic at 40000 {
+ interrupt-controller;
+ #address-cells = <0>;
+ #interrupt-cells = <2>;
+ reg = <0x40000 0x40000>;
+ compatible = "chrp,open-pic";
+ device_type = "open-pic";
+ };
+
+ msi at 41600 {
+ compatible = "fsl,p1020-msi", "fsl,mpic-msi";
+ reg = <0x41600 0x80>;
+ msi-available-ranges = <0 0x100>;
+ interrupts = <
+ 0xe0 0
+ 0xe1 0
+ 0xe2 0
+ 0xe3 0
+ 0xe4 0
+ 0xe5 0
+ 0xe6 0
+ 0xe7 0>;
+ interrupt-parent = <&mpic>;
+ };
+
+ global-utilities at e0000 { //global utilities block
+ compatible = "fsl,p1020-guts";
+ reg = <0xe0000 0x1000>;
+ fsl,has-rstcr;
+ };
+ };
+
+ pci0: pcie at ffe09000 {
+ compatible = "fsl,mpc8548-pcie";
+ device_type = "pci";
+ #interrupt-cells = <1>;
+ #size-cells = <2>;
+ #address-cells = <3>;
+ reg = <0 0xffe09000 0 0x1000>;
+ bus-range = <0 255>;
+ ranges = <0x2000000 0x0 0xa0000000 0 0xa0000000 0x0 0x20000000
+ 0x1000000 0x0 0x00000000 0 0xffc30000 0x0 0x10000>;
+ clock-frequency = <33333333>;
+ interrupt-parent = <&mpic>;
+ interrupts = <16 2>;
+ pcie at 0 {
+ reg = <0x0 0x0 0x0 0x0 0x0>;
+ #size-cells = <2>;
+ #address-cells = <3>;
+ device_type = "pci";
+ ranges = <0x2000000 0x0 0xa0000000
+ 0x2000000 0x0 0xa0000000
+ 0x0 0x20000000
+
+ 0x1000000 0x0 0x0
+ 0x1000000 0x0 0x0
+ 0x0 0x100000>;
+ };
+ };
+
+ pci1: pcie at ffe0a000 {
+ compatible = "fsl,mpc8548-pcie";
+ device_type = "pci";
+ #interrupt-cells = <1>;
+ #size-cells = <2>;
+ #address-cells = <3>;
+ reg = <0 0xffe0a000 0 0x1000>;
+ bus-range = <0 255>;
+ ranges = <0x2000000 0x0 0xc0000000 0 0xc0000000 0x0 0x20000000
+ 0x1000000 0x0 0x00000000 0 0xffc20000 0x0 0x10000>;
+ clock-frequency = <33333333>;
+ interrupt-parent = <&mpic>;
+ interrupts = <16 2>;
+ pcie at 0 {
+ reg = <0x0 0x0 0x0 0x0 0x0>;
+ #size-cells = <2>;
+ #address-cells = <3>;
+ device_type = "pci";
+ ranges = <0x2000000 0x0 0xc0000000
+ 0x2000000 0x0 0xc0000000
+ 0x0 0x20000000
+
+ 0x1000000 0x0 0x0
+ 0x1000000 0x0 0x0
+ 0x0 0x100000>;
+ };
+ };
+};
Property changes on: trunk/sys/boot/fdt/dts/powerpc/p1020rdb.dts
___________________________________________________________________
Added: svn:eol-style
## -0,0 +1 ##
+native
\ No newline at end of property
Added: svn:keywords
## -0,0 +1 ##
+MidnightBSD=%H
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+text/plain
\ No newline at end of property
Added: trunk/sys/boot/fdt/dts/powerpc/p2020ds.dts
===================================================================
--- trunk/sys/boot/fdt/dts/powerpc/p2020ds.dts (rev 0)
+++ trunk/sys/boot/fdt/dts/powerpc/p2020ds.dts 2018-06-02 12:34:49 UTC (rev 10205)
@@ -0,0 +1,755 @@
+/* $MidnightBSD$ */
+/*
+ * P2020 DS Device Tree Source
+ *
+ * Copyright 2009 Freescale Semiconductor Inc.
+ *
+ * Neither the name of Freescale Semiconductor, Inc nor the names of
+ * its contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * Freescale hereby publishes it under the following licenses:
+ *
+ * BSD License
+ *
+ * Redistribution and use in source and binary forms, with or
+ * without modification, are permitted provided that the following
+ * conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in
+ * the documentation and/or other materials provided with the
+ * distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND
+ * CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
+ * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED
+ * TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * GNU General Public License, version 2
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA 02110-1301, USA.
+ *
+ * You may select the license of your choice.
+ *------------------------------------------------------------------
+ */
+/* $FreeBSD: stable/10/sys/boot/fdt/dts/powerpc/p2020ds.dts 266364 2014-05-17 21:55:00Z ian $ */
+
+/dts-v1/;
+/ {
+ model = "fsl,P2020";
+ compatible = "fsl,P2020DS";
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ aliases {
+ ethernet0 = &enet0;
+ ethernet1 = &enet1;
+ ethernet2 = &enet2;
+ serial0 = &serial0;
+ serial1 = &serial1;
+ pci0 = &pci0;
+ pci1 = &pci1;
+ pci2 = &pci2;
+ };
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ PowerPC,P2020 at 0 {
+ device_type = "cpu";
+ reg = <0x0>;
+ next-level-cache = <&L2>;
+ };
+
+ PowerPC,P2020 at 1 {
+ device_type = "cpu";
+ reg = <0x1>;
+ next-level-cache = <&L2>;
+ };
+ };
+
+ memory {
+ device_type = "memory";
+ };
+
+ localbus at ffe05000 {
+ #address-cells = <2>;
+ #size-cells = <1>;
+ compatible = "fsl,elbc", "simple-bus";
+ reg = <0 0xffe05000 0 0x1000>;
+ interrupts = <19 2>;
+ interrupt-parent = <&mpic>;
+
+ ranges = <0x0 0x0 0x0 0xe8000000 0x08000000
+ 0x1 0x0 0x0 0xe0000000 0x08000000
+ 0x2 0x0 0x0 0xffa00000 0x00040000
+ 0x3 0x0 0x0 0xffdf0000 0x00008000
+ 0x4 0x0 0x0 0xffa40000 0x00040000
+ 0x5 0x0 0x0 0xffa80000 0x00040000
+ 0x6 0x0 0x0 0xffac0000 0x00040000>;
+
+ nor at 0,0 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "cfi-flash";
+ reg = <0x0 0x0 0x8000000>;
+ bank-width = <2>;
+ device-width = <1>;
+
+ ramdisk at 0 {
+ reg = <0x0 0x03000000>;
+ read-only;
+ };
+
+ diagnostic at 3000000 {
+ reg = <0x03000000 0x00e00000>;
+ read-only;
+ };
+
+ dink at 3e00000 {
+ reg = <0x03e00000 0x00200000>;
+ read-only;
+ };
+
+ kernel at 4000000 {
+ reg = <0x04000000 0x00400000>;
+ read-only;
+ };
+
+ jffs2 at 4400000 {
+ reg = <0x04400000 0x03b00000>;
+ };
+
+ dtb at 7f00000 {
+ reg = <0x07f00000 0x00080000>;
+ read-only;
+ };
+
+ u-boot at 7f80000 {
+ reg = <0x07f80000 0x00080000>;
+ read-only;
+ };
+ };
+
+ nand at 2,0 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "fsl,elbc-fcm-nand";
+ reg = <0x2 0x0 0x40000>;
+
+ u-boot at 0 {
+ reg = <0x0 0x02000000>;
+ read-only;
+ };
+
+ jffs2 at 2000000 {
+ reg = <0x02000000 0x10000000>;
+ };
+
+ ramdisk at 12000000 {
+ reg = <0x12000000 0x08000000>;
+ read-only;
+ };
+
+ kernel at 1a000000 {
+ reg = <0x1a000000 0x04000000>;
+ };
+
+ dtb at 1e000000 {
+ reg = <0x1e000000 0x01000000>;
+ read-only;
+ };
+
+ empty at 1f000000 {
+ reg = <0x1f000000 0x21000000>;
+ };
+ };
+
+ nand at 4,0 {
+ compatible = "fsl,elbc-fcm-nand";
+ reg = <0x4 0x0 0x40000>;
+ };
+
+ nand at 5,0 {
+ compatible = "fsl,elbc-fcm-nand";
+ reg = <0x5 0x0 0x40000>;
+ };
+
+ nand at 6,0 {
+ compatible = "fsl,elbc-fcm-nand";
+ reg = <0x6 0x0 0x40000>;
+ };
+ };
+
+ soc at ffe00000 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ device_type = "soc";
+ compatible = "fsl,p2020-immr", "simple-bus";
+ ranges = <0x0 0 0xffe00000 0x100000>;
+ bus-frequency = <0>; // Filled out by uboot.
+
+ ecm-law at 0 {
+ compatible = "fsl,ecm-law";
+ reg = <0x0 0x1000>;
+ fsl,num-laws = <12>;
+ };
+
+ ecm at 1000 {
+ compatible = "fsl,p2020-ecm", "fsl,ecm";
+ reg = <0x1000 0x1000>;
+ interrupts = <17 2>;
+ interrupt-parent = <&mpic>;
+ };
+
+ memory-controller at 2000 {
+ compatible = "fsl,p2020-memory-controller";
+ reg = <0x2000 0x1000>;
+ interrupt-parent = <&mpic>;
+ interrupts = <18 2>;
+ };
+
+ i2c at 3000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ cell-index = <0>;
+ compatible = "fsl-i2c";
+ reg = <0x3000 0x100>;
+ interrupts = <43 2>;
+ interrupt-parent = <&mpic>;
+ dfsrr;
+ };
+
+ i2c at 3100 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ cell-index = <1>;
+ compatible = "fsl-i2c";
+ reg = <0x3100 0x100>;
+ interrupts = <43 2>;
+ interrupt-parent = <&mpic>;
+ dfsrr;
+ };
+
+ serial0: serial at 4500 {
+ cell-index = <0>;
+ device_type = "serial";
+ compatible = "ns16550";
+ reg = <0x4500 0x100>;
+ clock-frequency = <0>;
+ interrupts = <42 2>;
+ interrupt-parent = <&mpic>;
+ };
+
+ serial1: serial at 4600 {
+ cell-index = <1>;
+ device_type = "serial";
+ compatible = "ns16550";
+ reg = <0x4600 0x100>;
+ clock-frequency = <0>;
+ interrupts = <42 2>;
+ interrupt-parent = <&mpic>;
+ };
+
+ spi at 7000 {
+ compatible = "fsl,espi";
+ reg = <0x7000 0x1000>;
+ interrupts = <59 0x2>;
+ interrupt-parent = <&mpic>;
+ };
+
+ dma at c300 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "fsl,eloplus-dma";
+ reg = <0xc300 0x4>;
+ ranges = <0x0 0xc100 0x200>;
+ cell-index = <1>;
+ dma-channel at 0 {
+ compatible = "fsl,eloplus-dma-channel";
+ reg = <0x0 0x80>;
+ cell-index = <0>;
+ interrupt-parent = <&mpic>;
+ interrupts = <76 2>;
+ };
+ dma-channel at 80 {
+ compatible = "fsl,eloplus-dma-channel";
+ reg = <0x80 0x80>;
+ cell-index = <1>;
+ interrupt-parent = <&mpic>;
+ interrupts = <77 2>;
+ };
+ dma-channel at 100 {
+ compatible = "fsl,eloplus-dma-channel";
+ reg = <0x100 0x80>;
+ cell-index = <2>;
+ interrupt-parent = <&mpic>;
+ interrupts = <78 2>;
+ };
+ dma-channel at 180 {
+ compatible = "fsl,eloplus-dma-channel";
+ reg = <0x180 0x80>;
+ cell-index = <3>;
+ interrupt-parent = <&mpic>;
+ interrupts = <79 2>;
+ };
+ };
+
+ gpio: gpio-controller at f000 {
+ #gpio-cells = <2>;
+ compatible = "fsl,mpc8572-gpio";
+ reg = <0xf000 0x100>;
+ interrupts = <47 0x2>;
+ interrupt-parent = <&mpic>;
+ gpio-controller;
+ };
+
+ L2: l2-cache-controller at 20000 {
+ compatible = "fsl,p2020-l2-cache-controller";
+ reg = <0x20000 0x1000>;
+ cache-line-size = <32>; // 32 bytes
+ cache-size = <0x80000>; // L2, 512k
+ interrupt-parent = <&mpic>;
+ interrupts = <16 2>;
+ };
+
+ dma at 21300 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "fsl,eloplus-dma";
+ reg = <0x21300 0x4>;
+ ranges = <0x0 0x21100 0x200>;
+ cell-index = <0>;
+ dma-channel at 0 {
+ compatible = "fsl,eloplus-dma-channel";
+ reg = <0x0 0x80>;
+ cell-index = <0>;
+ interrupt-parent = <&mpic>;
+ interrupts = <20 2>;
+ };
+ dma-channel at 80 {
+ compatible = "fsl,eloplus-dma-channel";
+ reg = <0x80 0x80>;
+ cell-index = <1>;
+ interrupt-parent = <&mpic>;
+ interrupts = <21 2>;
+ };
+ dma-channel at 100 {
+ compatible = "fsl,eloplus-dma-channel";
+ reg = <0x100 0x80>;
+ cell-index = <2>;
+ interrupt-parent = <&mpic>;
+ interrupts = <22 2>;
+ };
+ dma-channel at 180 {
+ compatible = "fsl,eloplus-dma-channel";
+ reg = <0x180 0x80>;
+ cell-index = <3>;
+ interrupt-parent = <&mpic>;
+ interrupts = <23 2>;
+ };
+ };
+
+ usb at 22000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "fsl-usb2-dr";
+ reg = <0x22000 0x1000>;
+ interrupt-parent = <&mpic>;
+ interrupts = <28 0x2>;
+ phy_type = "ulpi";
+ };
+
+ enet0: ethernet at 24000 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ cell-index = <0>;
+ device_type = "network";
+ model = "eTSEC";
+ compatible = "gianfar";
+ reg = <0x24000 0x1000>;
+ ranges = <0x0 0x24000 0x1000>;
+ local-mac-address = [ 00 00 00 00 00 00 ];
+ interrupts = <29 2 30 2 34 2>;
+ interrupt-parent = <&mpic>;
+ tbi-handle = <&tbi0>;
+ phy-handle = <&phy0>;
+ phy-connection-type = "rgmii-id";
+
+ mdio at 520 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "fsl,gianfar-mdio";
+ reg = <0x520 0x20>;
+
+ phy0: ethernet-phy at 0 {
+ interrupt-parent = <&mpic>;
+ interrupts = <3 1>;
+ reg = <0x0>;
+ };
+ phy1: ethernet-phy at 1 {
+ interrupt-parent = <&mpic>;
+ interrupts = <3 1>;
+ reg = <0x1>;
+ };
+ phy2: ethernet-phy at 2 {
+ interrupt-parent = <&mpic>;
+ interrupts = <3 1>;
+ reg = <0x2>;
+ };
+ tbi0: tbi-phy at 11 {
+ reg = <0x11>;
+ device_type = "tbi-phy";
+ };
+ };
+ };
+
+ enet1: ethernet at 25000 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ cell-index = <1>;
+ device_type = "network";
+ model = "eTSEC";
+ compatible = "gianfar";
+ reg = <0x25000 0x1000>;
+ ranges = <0x0 0x25000 0x1000>;
+ local-mac-address = [ 00 00 00 00 00 00 ];
+ interrupts = <35 2 36 2 40 2>;
+ interrupt-parent = <&mpic>;
+ tbi-handle = <&tbi1>;
+ phy-handle = <&phy1>;
+ phy-connection-type = "rgmii-id";
+
+ mdio at 520 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "fsl,gianfar-tbi";
+ reg = <0x520 0x20>;
+
+ tbi1: tbi-phy at 11 {
+ reg = <0x11>;
+ device_type = "tbi-phy";
+ };
+ };
+ };
+
+ enet2: ethernet at 26000 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ cell-index = <2>;
+ device_type = "network";
+ model = "eTSEC";
+ compatible = "gianfar";
+ reg = <0x26000 0x1000>;
+ ranges = <0x0 0x26000 0x1000>;
+ local-mac-address = [ 00 00 00 00 00 00 ];
+ interrupts = <31 2 32 2 33 2>;
+ interrupt-parent = <&mpic>;
+ tbi-handle = <&tbi2>;
+ phy-handle = <&phy2>;
+ phy-connection-type = "rgmii-id";
+
+ mdio at 520 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "fsl,gianfar-tbi";
+ reg = <0x520 0x20>;
+
+ tbi2: tbi-phy at 11 {
+ reg = <0x11>;
+ device_type = "tbi-phy";
+ };
+ };
+ };
+
+ sdhci at 2e000 {
+ compatible = "fsl,p2020-esdhc", "fsl,esdhc";
+ reg = <0x2e000 0x1000>;
+ interrupts = <72 0x2>;
+ interrupt-parent = <&mpic>;
+ /* Filled in by U-Boot */
+ clock-frequency = <0>;
+ };
+
+ crypto at 30000 {
+ compatible = "fsl,sec3.1", "fsl,sec3.0", "fsl,sec2.4",
+ "fsl,sec2.2", "fsl,sec2.1", "fsl,sec2.0";
+ reg = <0x30000 0x10000>;
+ interrupts = <45 2 58 2>;
+ interrupt-parent = <&mpic>;
+ fsl,num-channels = <4>;
+ fsl,channel-fifo-len = <24>;
+ fsl,exec-units-mask = <0xbfe>;
+ fsl,descriptor-types-mask = <0x3ab0ebf>;
+ };
+
+ mpic: pic at 40000 {
+ interrupt-controller;
+ #address-cells = <0>;
+ #interrupt-cells = <2>;
+ reg = <0x40000 0x40000>;
+ compatible = "chrp,open-pic";
+ device_type = "open-pic";
+ };
+
+ msi at 41600 {
+ compatible = "fsl,mpic-msi";
+ reg = <0x41600 0x80>;
+ msi-available-ranges = <0 0x100>;
+ interrupts = <
+ 0xe0 0
+ 0xe1 0
+ 0xe2 0
+ 0xe3 0
+ 0xe4 0
+ 0xe5 0
+ 0xe6 0
+ 0xe7 0>;
+ interrupt-parent = <&mpic>;
+ };
+
+ global-utilities at e0000 { //global utilities block
+ compatible = "fsl,p2020-guts";
+ reg = <0xe0000 0x1000>;
+ fsl,has-rstcr;
+ };
+ };
+
+ pci0: pcie at ffe08000 {
+ compatible = "fsl,mpc8548-pcie";
+ device_type = "pci";
+ #interrupt-cells = <1>;
+ #size-cells = <2>;
+ #address-cells = <3>;
+ reg = <0 0xffe08000 0 0x1000>;
+ bus-range = <0 255>;
+ ranges = <0x2000000 0x0 0x80000000 0 0x80000000 0x0 0x20000000
+ 0x1000000 0x0 0x00000000 0 0xffc00000 0x0 0x10000>;
+ clock-frequency = <33333333>;
+ interrupt-parent = <&mpic>;
+ interrupts = <24 2>;
+ interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
+ interrupt-map = <
+ /* IDSEL 0x0 */
+ 0000 0x0 0x0 0x1 &mpic 0x8 0x1
+ 0000 0x0 0x0 0x2 &mpic 0x9 0x1
+ 0000 0x0 0x0 0x3 &mpic 0xa 0x1
+ 0000 0x0 0x0 0x4 &mpic 0xb 0x1
+ >;
+ pcie at 0 {
+ reg = <0x0 0x0 0x0 0x0 0x0>;
+ #size-cells = <2>;
+ #address-cells = <3>;
+ device_type = "pci";
+ ranges = <0x2000000 0x0 0x80000000
+ 0x2000000 0x0 0x80000000
+ 0x0 0x20000000
+
+ 0x1000000 0x0 0x0
+ 0x1000000 0x0 0x0
+ 0x0 0x10000>;
+ };
+ };
+
+ pci1: pcie at ffe09000 {
+ compatible = "fsl,mpc8548-pcie";
+ device_type = "pci";
+ #interrupt-cells = <1>;
+ #size-cells = <2>;
+ #address-cells = <3>;
+ reg = <0 0xffe09000 0 0x1000>;
+ bus-range = <0 255>;
+ ranges = <0x2000000 0x0 0xa0000000 0 0xa0000000 0x0 0x20000000
+ 0x1000000 0x0 0x00000000 0 0xffc10000 0x0 0x10000>;
+ clock-frequency = <33333333>;
+ interrupt-parent = <&mpic>;
+ interrupts = <25 2>;
+ interrupt-map-mask = <0xff00 0x0 0x0 0x7>;
+ interrupt-map = <
+
+ // IDSEL 0x11 func 0 - PCI slot 1
+ 0x8800 0x0 0x0 0x1 &i8259 0x9 0x2
+ 0x8800 0x0 0x0 0x2 &i8259 0xa 0x2
+
+ // IDSEL 0x11 func 1 - PCI slot 1
+ 0x8900 0x0 0x0 0x1 &i8259 0x9 0x2
+ 0x8900 0x0 0x0 0x2 &i8259 0xa 0x2
+
+ // IDSEL 0x11 func 2 - PCI slot 1
+ 0x8a00 0x0 0x0 0x1 &i8259 0x9 0x2
+ 0x8a00 0x0 0x0 0x2 &i8259 0xa 0x2
+
+ // IDSEL 0x11 func 3 - PCI slot 1
+ 0x8b00 0x0 0x0 0x1 &i8259 0x9 0x2
+ 0x8b00 0x0 0x0 0x2 &i8259 0xa 0x2
+
+ // IDSEL 0x11 func 4 - PCI slot 1
+ 0x8c00 0x0 0x0 0x1 &i8259 0x9 0x2
+ 0x8c00 0x0 0x0 0x2 &i8259 0xa 0x2
+
+ // IDSEL 0x11 func 5 - PCI slot 1
+ 0x8d00 0x0 0x0 0x1 &i8259 0x9 0x2
+ 0x8d00 0x0 0x0 0x2 &i8259 0xa 0x2
+
+ // IDSEL 0x11 func 6 - PCI slot 1
+ 0x8e00 0x0 0x0 0x1 &i8259 0x9 0x2
+ 0x8e00 0x0 0x0 0x2 &i8259 0xa 0x2
+
+ // IDSEL 0x11 func 7 - PCI slot 1
+ 0x8f00 0x0 0x0 0x1 &i8259 0x9 0x2
+ 0x8f00 0x0 0x0 0x2 &i8259 0xa 0x2
+
+ // IDSEL 0x1d Audio
+ 0xe800 0x0 0x0 0x1 &i8259 0x6 0x2
+
+ // IDSEL 0x1e Legacy
+ 0xf000 0x0 0x0 0x1 &i8259 0x7 0x2
+ 0xf100 0x0 0x0 0x1 &i8259 0x7 0x2
+
+ // IDSEL 0x1f IDE/SATA
+ 0xf800 0x0 0x0 0x1 &i8259 0xe 0x2
+ 0xf900 0x0 0x0 0x1 &i8259 0x5 0x2
+ >;
+
+ pcie at 0 {
+ reg = <0x0 0x0 0x0 0x0 0x0>;
+ #size-cells = <2>;
+ #address-cells = <3>;
+ device_type = "pci";
+ ranges = <0x2000000 0x0 0xa0000000
+ 0x2000000 0x0 0xa0000000
+ 0x0 0x20000000
+
+ 0x1000000 0x0 0x0
+ 0x1000000 0x0 0x0
+ 0x0 0x10000>;
+ uli1575 at 0 {
+ reg = <0x0 0x0 0x0 0x0 0x0>;
+ #size-cells = <2>;
+ #address-cells = <3>;
+ ranges = <0x2000000 0x0 0xa0000000
+ 0x2000000 0x0 0xa0000000
+ 0x0 0x20000000
+
+ 0x1000000 0x0 0x0
+ 0x1000000 0x0 0x0
+ 0x0 0x10000>;
+ isa at 1e {
+ device_type = "isa";
+ #interrupt-cells = <2>;
+ #size-cells = <1>;
+ #address-cells = <2>;
+ reg = <0xf000 0x0 0x0 0x0 0x0>;
+ ranges = <0x1 0x0 0x1000000 0x0 0x0
+ 0x1000>;
+ interrupt-parent = <&i8259>;
+
+ i8259: interrupt-controller at 20 {
+ reg = <0x1 0x20 0x2
+ 0x1 0xa0 0x2
+ 0x1 0x4d0 0x2>;
+ interrupt-controller;
+ device_type = "interrupt-controller";
+ #address-cells = <0>;
+ #interrupt-cells = <2>;
+ compatible = "chrp,iic";
+ interrupts = <4 1>;
+ interrupt-parent = <&mpic>;
+ };
+
+ i8042 at 60 {
+ #size-cells = <0>;
+ #address-cells = <1>;
+ reg = <0x1 0x60 0x1 0x1 0x64 0x1>;
+ interrupts = <1 3 12 3>;
+ interrupt-parent =
+ <&i8259>;
+
+ keyboard at 0 {
+ reg = <0x0>;
+ compatible = "pnpPNP,303";
+ };
+
+ mouse at 1 {
+ reg = <0x1>;
+ compatible = "pnpPNP,f03";
+ };
+ };
+
+ rtc at 70 {
+ compatible = "pnpPNP,b00";
+ reg = <0x1 0x70 0x2>;
+ };
+
+ gpio at 400 {
+ reg = <0x1 0x400 0x80>;
+ };
+ };
+ };
+ };
+
+ };
+
+ pci2: pcie at ffe0a000 {
+ compatible = "fsl,mpc8548-pcie";
+ device_type = "pci";
+ #interrupt-cells = <1>;
+ #size-cells = <2>;
+ #address-cells = <3>;
+ reg = <0 0xffe0a000 0 0x1000>;
+ bus-range = <0 255>;
+ ranges = <0x2000000 0x0 0xc0000000 0 0xc0000000 0x0 0x20000000
+ 0x1000000 0x0 0x00000000 0 0xffc20000 0x0 0x10000>;
+ clock-frequency = <33333333>;
+ interrupt-parent = <&mpic>;
+ interrupts = <26 2>;
+ interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
+ interrupt-map = <
+ /* IDSEL 0x0 */
+ 0000 0x0 0x0 0x1 &mpic 0x0 0x1
+ 0000 0x0 0x0 0x2 &mpic 0x1 0x1
+ 0000 0x0 0x0 0x3 &mpic 0x2 0x1
+ 0000 0x0 0x0 0x4 &mpic 0x3 0x1
+ >;
+ pcie at 0 {
+ reg = <0x0 0x0 0x0 0x0 0x0>;
+ #size-cells = <2>;
+ #address-cells = <3>;
+ device_type = "pci";
+ ranges = <0x2000000 0x0 0xc0000000
+ 0x2000000 0x0 0xc0000000
+ 0x0 0x20000000
+
+ 0x1000000 0x0 0x0
+ 0x1000000 0x0 0x0
+ 0x0 0x10000>;
+ };
+ };
+};
Property changes on: trunk/sys/boot/fdt/dts/powerpc/p2020ds.dts
___________________________________________________________________
Added: svn:eol-style
## -0,0 +1 ##
+native
\ No newline at end of property
Added: svn:keywords
## -0,0 +1 ##
+MidnightBSD=%H
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+text/plain
\ No newline at end of property
Added: trunk/sys/boot/fdt/dts/powerpc/p2041si.dtsi
===================================================================
--- trunk/sys/boot/fdt/dts/powerpc/p2041si.dtsi (rev 0)
+++ trunk/sys/boot/fdt/dts/powerpc/p2041si.dtsi 2018-06-02 12:34:49 UTC (rev 10205)
@@ -0,0 +1,1297 @@
+/* $MidnightBSD$ */
+/*
+ * P2041 Silicon Device Tree Source
+ *
+ * Copyright 2011 Freescale Semiconductor Inc.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * * Neither the name of Freescale Semiconductor nor the
+ * names of its contributors may be used to endorse or promote products
+ * derived from this software without specific prior written permission.
+ *
+ *
+ * ALTERNATIVELY, this software may be distributed under the terms of the
+ * GNU General Public License ("GPL") as published by the Free Software
+ * Foundation, either version 2 of that License or (at your option) any
+ * later version.
+ *
+ * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+/* $FreeBSD: stable/10/sys/boot/fdt/dts/powerpc/p2041si.dtsi 266364 2014-05-17 21:55:00Z ian $ */
+
+/dts-v1/;
+
+/ {
+ compatible = "fsl,P2041";
+ #address-cells = <2>;
+ #size-cells = <2>;
+ interrupt-parent = <&mpic>;
+
+ aliases {
+ ccsr = &soc;
+ dcsr = &dcsr;
+
+ ethernet0 = &enet0;
+ ethernet1 = &enet1;
+ ethernet2 = &enet2;
+ ethernet3 = &enet3;
+ ethernet4 = &enet4;
+ ethernet5 = &enet5;
+ serial0 = &serial0;
+ serial1 = &serial1;
+ serial2 = &serial2;
+ serial3 = &serial3;
+ pci0 = &pci0;
+ pci1 = &pci1;
+ pci2 = &pci2;
+ usb0 = &usb0;
+ usb1 = &usb1;
+ dma0 = &dma0;
+ dma1 = &dma1;
+ bman = &bman;
+ qman = &qman;
+ pme = &pme;
+ rman = &rman;
+ sdhc = &sdhc;
+ msi0 = &msi0;
+ msi1 = &msi1;
+ msi2 = &msi2;
+
+ crypto = &crypto;
+ sec_jr0 = &sec_jr0;
+ sec_jr1 = &sec_jr1;
+ sec_jr2 = &sec_jr2;
+ sec_jr3 = &sec_jr3;
+ rtic_a = &rtic_a;
+ rtic_b = &rtic_b;
+ rtic_c = &rtic_c;
+ rtic_d = &rtic_d;
+ sec_mon = &sec_mon;
+
+ fman0 = &fman0;
+ fman0_oh0 = &fman0_oh0;
+ fman0_oh1 = &fman0_oh1;
+ fman0_oh2 = &fman0_oh2;
+ fman0_oh3 = &fman0_oh3;
+ fman0_oh4 = &fman0_oh4;
+ fman0_oh5 = &fman0_oh5;
+ fman0_oh6 = &fman0_oh6;
+ fman0_rx0 = &fman0_rx0;
+ fman0_rx1 = &fman0_rx1;
+ fman0_rx2 = &fman0_rx2;
+ fman0_rx3 = &fman0_rx3;
+ fman0_rx4 = &fman0_rx4;
+ fman0_rx5 = &fman0_rx5;
+ };
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cpu0: PowerPC,e500mc at 0 {
+ device_type = "cpu";
+ reg = <0>;
+ bus-frequency = <749999996>;
+ next-level-cache = <&L2_0>;
+ L2_0: l2-cache {
+ next-level-cache = <&cpc>;
+ };
+ };
+ cpu1: PowerPC,e500mc at 1 {
+ device_type = "cpu";
+ reg = <1>;
+ next-level-cache = <&L2_1>;
+ L2_1: l2-cache {
+ next-level-cache = <&cpc>;
+ };
+ };
+ cpu2: PowerPC,e500mc at 2 {
+ device_type = "cpu";
+ reg = <2>;
+ next-level-cache = <&L2_2>;
+ L2_2: l2-cache {
+ next-level-cache = <&cpc>;
+ };
+ };
+ cpu3: PowerPC,e500mc at 3 {
+ device_type = "cpu";
+ reg = <3>;
+ next-level-cache = <&L2_3>;
+ L2_3: l2-cache {
+ next-level-cache = <&cpc>;
+ };
+ };
+ };
+
+ dcsr: dcsr at f00000000 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "fsl,dcsr", "simple-bus";
+
+ dcsr-epu at 0 {
+ compatible = "fsl,dcsr-epu";
+ interrupts = <52 2 0 0
+ 84 2 0 0
+ 85 2 0 0>;
+ interrupt-parent = <&mpic>;
+ reg = <0x0 0x1000>;
+ };
+ dcsr-npc {
+ compatible = "fsl,dcsr-npc";
+ reg = <0x1000 0x1000 0x1000000 0x8000>;
+ };
+ dcsr-nxc at 2000 {
+ compatible = "fsl,dcsr-nxc";
+ reg = <0x2000 0x1000>;
+ };
+ dcsr-corenet {
+ compatible = "fsl,dcsr-corenet";
+ reg = <0x8000 0x1000 0xB0000 0x1000>;
+ };
+ dcsr-dpaa at 9000 {
+ compatible = "fsl,p2041-dcsr-dpaa", "fsl,dcsr-dpaa";
+ reg = <0x9000 0x1000>;
+ };
+ dcsr-ocn at 11000 {
+ compatible = "fsl,p2041-dcsr-ocn", "fsl,dcsr-ocn";
+ reg = <0x11000 0x1000>;
+ };
+ dcsr-ddr at 12000 {
+ compatible = "fsl,dcsr-ddr";
+ dev-handle = <&ddr>;
+ reg = <0x12000 0x1000>;
+ };
+ dcsr-nal at 18000 {
+ compatible = "fsl,p2041-dcsr-nal", "fsl,dcsr-nal";
+ reg = <0x18000 0x1000>;
+ };
+ dcsr-rcpm at 22000 {
+ compatible = "fsl,p2041-dcsr-rcpm", "fsl,dcsr-rcpm";
+ reg = <0x22000 0x1000>;
+ };
+ dcsr-cpu-sb-proxy at 40000 {
+ compatible = "fsl,dcsr-e500mc-sb-proxy", "fsl,dcsr-cpu-sb-proxy";
+ cpu-handle = <&cpu0>;
+ reg = <0x40000 0x1000>;
+ };
+ dcsr-cpu-sb-proxy at 41000 {
+ compatible = "fsl,dcsr-e500mc-sb-proxy", "fsl,dcsr-cpu-sb-proxy";
+ cpu-handle = <&cpu1>;
+ reg = <0x41000 0x1000>;
+ };
+ dcsr-cpu-sb-proxy at 42000 {
+ compatible = "fsl,dcsr-e500mc-sb-proxy", "fsl,dcsr-cpu-sb-proxy";
+ cpu-handle = <&cpu2>;
+ reg = <0x42000 0x1000>;
+ };
+ dcsr-cpu-sb-proxy at 43000 {
+ compatible = "fsl,dcsr-e500mc-sb-proxy", "fsl,dcsr-cpu-sb-proxy";
+ cpu-handle = <&cpu3>;
+ reg = <0x43000 0x1000>;
+ };
+ };
+
+ bman-portals at ff4000000 {
+ #address-cells = <0x1>;
+ #size-cells = <0x1>;
+ compatible = "bman-portals";
+ ranges = <0x0 0xf 0xfde00000 0x200000>;
+ bman-portal at 0 {
+ cell-index = <0x0>;
+ compatible = "fsl,p2041-bman-portal", "fsl,bman-portal";
+ reg = <0x0 0x4000 0x100000 0x1000>;
+ interrupts = <105 2 0 0>;
+ };
+ bman-portal at 4000 {
+ cell-index = <0x1>;
+ compatible = "fsl,p2041-bman-portal", "fsl,bman-portal";
+ reg = <0x4000 0x4000 0x101000 0x1000>;
+ interrupts = <107 2 0 0>;
+ };
+ bman-portal at 8000 {
+ cell-index = <2>;
+ compatible = "fsl,p2041-bman-portal", "fsl,bman-portal";
+ reg = <0x8000 0x4000 0x102000 0x1000>;
+ interrupts = <109 2 0 0>;
+ };
+ bman-portal at c000 {
+ cell-index = <0x3>;
+ compatible = "fsl,p2041-bman-portal", "fsl,bman-portal";
+ reg = <0xc000 0x4000 0x103000 0x1000>;
+ interrupts = <111 2 0 0>;
+ };
+ bman-portal at 10000 {
+ cell-index = <0x4>;
+ compatible = "fsl,p2041-bman-portal", "fsl,bman-portal";
+ reg = <0x10000 0x4000 0x104000 0x1000>;
+ interrupts = <113 2 0 0>;
+ };
+ bman-portal at 14000 {
+ cell-index = <0x5>;
+ compatible = "fsl,p2041-bman-portal", "fsl,bman-portal";
+ reg = <0x14000 0x4000 0x105000 0x1000>;
+ interrupts = <115 2 0 0>;
+ };
+ bman-portal at 18000 {
+ cell-index = <0x6>;
+ compatible = "fsl,p2041-bman-portal", "fsl,bman-portal";
+ reg = <0x18000 0x4000 0x106000 0x1000>;
+ interrupts = <117 2 0 0>;
+ };
+ bman-portal at 1c000 {
+ cell-index = <0x7>;
+ compatible = "fsl,p2041-bman-portal", "fsl,bman-portal";
+ reg = <0x1c000 0x4000 0x107000 0x1000>;
+ interrupts = <119 2 0 0>;
+ };
+ bman-portal at 20000 {
+ cell-index = <0x8>;
+ compatible = "fsl,p2041-bman-portal", "fsl,bman-portal";
+ reg = <0x20000 0x4000 0x108000 0x1000>;
+ interrupts = <121 2 0 0>;
+ };
+ bman-portal at 24000 {
+ cell-index = <0x9>;
+ compatible = "fsl,p2041-bman-portal", "fsl,bman-portal";
+ reg = <0x24000 0x4000 0x109000 0x1000>;
+ interrupts = <123 2 0 0>;
+ };
+
+ buffer-pool at 0 {
+ compatible = "fsl,p2041-bpool", "fsl,bpool";
+ fsl,bpid = <0>;
+ fsl,bpool-cfg = <0 0x100 0 1 0 0x100>;
+ };
+ };
+
+ qman-portals at ff4200000 {
+ #address-cells = <0x1>;
+ #size-cells = <0x1>;
+ compatible = "qman-portals";
+ ranges = <0x0 0xf 0xfdc00000 0x200000>;
+ qportal0: qman-portal at 0 {
+ cell-index = <0x0>;
+ compatible = "fsl,p2041-qman-portal", "fsl,qman-portal";
+ reg = <0x0 0x4000 0x100000 0x1000>;
+ interrupts = <104 0x2 0 0>;
+ fsl,qman-channel-id = <0x0>;
+ };
+
+ qportal1: qman-portal at 4000 {
+ cell-index = <0x1>;
+ compatible = "fsl,p2041-qman-portal", "fsl,qman-portal";
+ reg = <0x4000 0x4000 0x101000 0x1000>;
+ interrupts = <106 0x2 0 0>;
+ fsl,qman-channel-id = <0x1>;
+ };
+
+ qportal2: qman-portal at 8000 {
+ cell-index = <0x2>;
+ compatible = "fsl,p2041-qman-portal", "fsl,qman-portal";
+ reg = <0x8000 0x4000 0x102000 0x1000>;
+ interrupts = <108 0x2 0 0>;
+ fsl,qman-channel-id = <0x2>;
+ };
+
+ qportal3: qman-portal at c000 {
+ cell-index = <0x3>;
+ compatible = "fsl,p2041-qman-portal", "fsl,qman-portal";
+ reg = <0xc000 0x4000 0x103000 0x1000>;
+ interrupts = <110 0x2 0 0>;
+ fsl,qman-channel-id = <0x3>;
+ };
+
+ qportal4: qman-portal at 10000 {
+ cell-index = <0x4>;
+ compatible = "fsl,p2041-qman-portal", "fsl,qman-portal";
+ reg = <0x10000 0x4000 0x104000 0x1000>;
+ interrupts = <112 0x2 0 0>;
+ fsl,qman-channel-id = <0x4>;
+ };
+
+ qportal5: qman-portal at 14000 {
+ cell-index = <0x5>;
+ compatible = "fsl,p2041-qman-portal", "fsl,qman-portal";
+ reg = <0x14000 0x4000 0x105000 0x1000>;
+ interrupts = <114 0x2 0 0>;
+ fsl,qman-channel-id = <0x5>;
+ };
+
+ qportal6: qman-portal at 18000 {
+ cell-index = <0x6>;
+ compatible = "fsl,p2041-qman-portal", "fsl,qman-portal";
+ reg = <0x18000 0x4000 0x106000 0x1000>;
+ interrupts = <116 0x2 0 0>;
+ fsl,qman-channel-id = <0x6>;
+ };
+
+ qportal7: qman-portal at 1c000 {
+ cell-index = <0x7>;
+ compatible = "fsl,p2041-qman-portal", "fsl,qman-portal";
+ reg = <0x1c000 0x4000 0x107000 0x1000>;
+ interrupts = <118 0x2 0 0>;
+ fsl,qman-channel-id = <0x7>;
+ };
+
+ qportal8: qman-portal at 20000 {
+ cell-index = <0x8>;
+ compatible = "fsl,p2041-qman-portal", "fsl,qman-portal";
+ reg = <0x20000 0x4000 0x108000 0x1000>;
+ interrupts = <120 0x2 0 0>;
+ fsl,qman-channel-id = <0x8>;
+ };
+
+ qportal9: qman-portal at 24000 {
+ cell-index = <0x9>;
+ compatible = "fsl,p2041-qman-portal", "fsl,qman-portal";
+ reg = <0x24000 0x4000 0x109000 0x1000>;
+ interrupts = <122 0x2 0 0>;
+ fsl,qman-channel-id = <0x9>;
+ };
+
+ qpool1: qman-pool at 1 {
+ cell-index = <1>;
+ compatible = "fsl,p2041-qman-pool-channel", "fsl,qman-pool-channel";
+ fsl,qman-channel-id = <0x21>;
+ };
+
+ qpool2: qman-pool at 2 {
+ cell-index = <2>;
+ compatible = "fsl,p2041-qman-pool-channel", "fsl,qman-pool-channel";
+ fsl,qman-channel-id = <0x22>;
+ };
+
+ qpool3: qman-pool at 3 {
+ cell-index = <3>;
+ compatible = "fsl,p2041-qman-pool-channel", "fsl,qman-pool-channel";
+ fsl,qman-channel-id = <0x23>;
+ };
+
+ qpool4: qman-pool at 4 {
+ cell-index = <4>;
+ compatible = "fsl,p2041-qman-pool-channel", "fsl,qman-pool-channel";
+ fsl,qman-channel-id = <0x24>;
+ };
+
+ qpool5: qman-pool at 5 {
+ cell-index = <5>;
+ compatible = "fsl,p2041-qman-pool-channel", "fsl,qman-pool-channel";
+ fsl,qman-channel-id = <0x25>;
+ };
+
+ qpool6: qman-pool at 6 {
+ cell-index = <6>;
+ compatible = "fsl,p2041-qman-pool-channel", "fsl,qman-pool-channel";
+ fsl,qman-channel-id = <0x26>;
+ };
+
+ qpool7: qman-pool at 7 {
+ cell-index = <7>;
+ compatible = "fsl,p2041-qman-pool-channel", "fsl,qman-pool-channel";
+ fsl,qman-channel-id = <0x27>;
+ };
+
+ qpool8: qman-pool at 8 {
+ cell-index = <8>;
+ compatible = "fsl,p2041-qman-pool-channel", "fsl,qman-pool-channel";
+ fsl,qman-channel-id = <0x28>;
+ };
+
+ qpool9: qman-pool at 9 {
+ cell-index = <9>;
+ compatible = "fsl,p2041-qman-pool-channel", "fsl,qman-pool-channel";
+ fsl,qman-channel-id = <0x29>;
+ };
+
+ qpool10: qman-pool at 10 {
+ cell-index = <10>;
+ compatible = "fsl,p2041-qman-pool-channel", "fsl,qman-pool-channel";
+ fsl,qman-channel-id = <0x2a>;
+ };
+
+ qpool11: qman-pool at 11 {
+ cell-index = <11>;
+ compatible = "fsl,p2041-qman-pool-channel", "fsl,qman-pool-channel";
+ fsl,qman-channel-id = <0x2b>;
+ };
+
+ qpool12: qman-pool at 12 {
+ cell-index = <12>;
+ compatible = "fsl,p2041-qman-pool-channel", "fsl,qman-pool-channel";
+ fsl,qman-channel-id = <0x2c>;
+ };
+
+ qpool13: qman-pool at 13 {
+ cell-index = <13>;
+ compatible = "fsl,p2041-qman-pool-channel", "fsl,qman-pool-channel";
+ fsl,qman-channel-id = <0x2d>;
+ };
+
+ qpool14: qman-pool at 14 {
+ cell-index = <14>;
+ compatible = "fsl,p2041-qman-pool-channel", "fsl,qman-pool-channel";
+ fsl,qman-channel-id = <0x2e>;
+ };
+
+ qpool15: qman-pool at 15 {
+ cell-index = <15>;
+ compatible = "fsl,p2041-qman-pool-channel", "fsl,qman-pool-channel";
+ fsl,qman-channel-id = <0x2f>;
+ };
+ };
+
+ soc: soc at ffe000000 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ device_type = "soc";
+ compatible = "simple-bus";
+
+ bus-frequency = <0>; // Filled out by kernel.
+
+ ranges = <0x00000000 0xf 0xfe000000 0x1000000>;
+ reg = <0xf 0xfe000000 0 0x00001000>;
+
+ soc-sram-error {
+ compatible = "fsl,soc-sram-error";
+ interrupts = <16 2 1 29>;
+ };
+
+ corenet-law at 0 {
+ compatible = "fsl,corenet-law";
+ reg = <0x0 0x1000>;
+ fsl,num-laws = <32>;
+ };
+
+ ddr: memory-controller at 8000 {
+ compatible = "fsl,qoriq-memory-controller-v4.5", "fsl,qoriq-memory-controller";
+ reg = <0x8000 0x1000>;
+ interrupts = <16 2 1 23>;
+ };
+
+ cpc: l3-cache-controller at 10000 {
+ compatible = "fsl,p2041-l3-cache-controller", "fsl,p4080-l3-cache-controller", "cache";
+ reg = <0x10000 0x1000>;
+ interrupts = <16 2 1 27>;
+ };
+
+ corenet-cf at 18000 {
+ compatible = "fsl,corenet-cf";
+ reg = <0x18000 0x1000>;
+ interrupts = <16 2 1 31>;
+ fsl,ccf-num-csdids = <32>;
+ fsl,ccf-num-snoopids = <32>;
+ };
+
+ iommu at 20000 {
+ compatible = "fsl,pamu-v1.0", "fsl,pamu";
+ reg = <0x20000 0x4000>;
+ interrupts = <
+ 24 2 0 0
+ 16 2 1 30>;
+ };
+
+ mpic: pic at 40000 {
+ clock-frequency = <0>;
+ interrupt-controller;
+ #address-cells = <0>;
+ #interrupt-cells = <4>;
+ reg = <0x40000 0x40000>;
+ compatible = "fsl,mpic", "chrp,open-pic";
+ device_type = "open-pic";
+ };
+
+ msi0: msi at 41600 {
+ compatible = "fsl,mpic-msi";
+ reg = <0x41600 0x200>;
+ msi-available-ranges = <0 0x100>;
+ interrupts = <
+ 0xe0 0 0 0
+ 0xe1 0 0 0
+ 0xe2 0 0 0
+ 0xe3 0 0 0
+ 0xe4 0 0 0
+ 0xe5 0 0 0
+ 0xe6 0 0 0
+ 0xe7 0 0 0>;
+ };
+
+ msi1: msi at 41800 {
+ compatible = "fsl,mpic-msi";
+ reg = <0x41800 0x200>;
+ msi-available-ranges = <0 0x100>;
+ interrupts = <
+ 0xe8 0 0 0
+ 0xe9 0 0 0
+ 0xea 0 0 0
+ 0xeb 0 0 0
+ 0xec 0 0 0
+ 0xed 0 0 0
+ 0xee 0 0 0
+ 0xef 0 0 0>;
+ };
+
+ msi2: msi at 41a00 {
+ compatible = "fsl,mpic-msi";
+ reg = <0x41a00 0x200>;
+ msi-available-ranges = <0 0x100>;
+ interrupts = <
+ 0xf0 0 0 0
+ 0xf1 0 0 0
+ 0xf2 0 0 0
+ 0xf3 0 0 0
+ 0xf4 0 0 0
+ 0xf5 0 0 0
+ 0xf6 0 0 0
+ 0xf7 0 0 0>;
+ };
+
+ guts: global-utilities at e0000 {
+ compatible = "fsl,qoriq-device-config-1.0";
+ reg = <0xe0000 0xe00>;
+ fsl,has-rstcr;
+ #sleep-cells = <1>;
+ fsl,liodn-bits = <12>;
+ };
+
+ pins: global-utilities at e0e00 {
+ compatible = "fsl,qoriq-pin-control-1.0";
+ reg = <0xe0e00 0x200>;
+ #sleep-cells = <2>;
+ };
+
+ clockgen: global-utilities at e1000 {
+ compatible = "fsl,p2041-clockgen", "fsl,qoriq-clockgen-1.0";
+ reg = <0xe1000 0x1000>;
+ clock-frequency = <0>;
+ };
+
+ rcpm: global-utilities at e2000 {
+ compatible = "fsl,qoriq-rcpm-1.0";
+ reg = <0xe2000 0x1000>;
+ #sleep-cells = <1>;
+ };
+
+ sfp: sfp at e8000 {
+ compatible = "fsl,p2041-sfp", "fsl,qoriq-sfp-1.0";
+ reg = <0xe8000 0x1000>;
+ };
+
+ serdes: serdes at ea000 {
+ compatible = "fsl,p2041-serdes";
+ reg = <0xea000 0x1000>;
+ };
+
+ dma0: dma at 100300 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "fsl,p2041-dma", "fsl,eloplus-dma";
+ reg = <0x100300 0x4>;
+ ranges = <0x0 0x100100 0x200>;
+ cell-index = <0>;
+ dma-channel at 0 {
+ compatible = "fsl,p2041-dma-channel",
+ "fsl,eloplus-dma-channel";
+ reg = <0x0 0x80>;
+ cell-index = <0>;
+ interrupts = <28 2 0 0>;
+ };
+ dma-channel at 80 {
+ compatible = "fsl,p2041-dma-channel",
+ "fsl,eloplus-dma-channel";
+ reg = <0x80 0x80>;
+ cell-index = <1>;
+ interrupts = <29 2 0 0>;
+ };
+ dma-channel at 100 {
+ compatible = "fsl,p2041-dma-channel",
+ "fsl,eloplus-dma-channel";
+ reg = <0x100 0x80>;
+ cell-index = <2>;
+ interrupts = <30 2 0 0>;
+ };
+ dma-channel at 180 {
+ compatible = "fsl,p2041-dma-channel",
+ "fsl,eloplus-dma-channel";
+ reg = <0x180 0x80>;
+ cell-index = <3>;
+ interrupts = <31 2 0 0>;
+ };
+ };
+
+ dma1: dma at 101300 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "fsl,p2041-dma", "fsl,eloplus-dma";
+ reg = <0x101300 0x4>;
+ ranges = <0x0 0x101100 0x200>;
+ cell-index = <1>;
+ dma-channel at 0 {
+ compatible = "fsl,p2041-dma-channel",
+ "fsl,eloplus-dma-channel";
+ reg = <0x0 0x80>;
+ cell-index = <0>;
+ interrupts = <32 2 0 0>;
+ };
+ dma-channel at 80 {
+ compatible = "fsl,p2041-dma-channel",
+ "fsl,eloplus-dma-channel";
+ reg = <0x80 0x80>;
+ cell-index = <1>;
+ interrupts = <33 2 0 0>;
+ };
+ dma-channel at 100 {
+ compatible = "fsl,p2041-dma-channel",
+ "fsl,eloplus-dma-channel";
+ reg = <0x100 0x80>;
+ cell-index = <2>;
+ interrupts = <34 2 0 0>;
+ };
+ dma-channel at 180 {
+ compatible = "fsl,p2041-dma-channel",
+ "fsl,eloplus-dma-channel";
+ reg = <0x180 0x80>;
+ cell-index = <3>;
+ interrupts = <35 2 0 0>;
+ };
+ };
+
+ spi at 110000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "fsl,p2041-espi", "fsl,mpc8536-espi";
+ reg = <0x110000 0x1000>;
+ interrupts = <53 0x2 0 0>;
+ fsl,espi-num-chipselects = <4>;
+ };
+
+ sdhc: sdhc at 114000 {
+ compatible = "fsl,p2041-esdhc", "fsl,esdhc";
+ reg = <0x114000 0x1000>;
+ interrupts = <48 2 0 0>;
+ sdhci,auto-cmd12;
+ clock-frequency = <0>;
+ };
+
+ i2c at 118000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ cell-index = <0>;
+ compatible = "fsl-i2c";
+ reg = <0x118000 0x100>;
+ interrupts = <38 2 0 0>;
+ dfsrr;
+ };
+
+ i2c at 118100 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ cell-index = <1>;
+ compatible = "fsl-i2c";
+ reg = <0x118100 0x100>;
+ interrupts = <38 2 0 0>;
+ dfsrr;
+ };
+
+ i2c at 119000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ cell-index = <2>;
+ compatible = "fsl-i2c";
+ reg = <0x119000 0x100>;
+ interrupts = <39 2 0 0>;
+ dfsrr;
+ };
+
+ i2c at 119100 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ cell-index = <3>;
+ compatible = "fsl-i2c";
+ reg = <0x119100 0x100>;
+ interrupts = <39 2 0 0>;
+ dfsrr;
+ };
+
+ serial0: serial at 11c500 {
+ cell-index = <0>;
+ device_type = "serial";
+ compatible = "ns16550";
+ reg = <0x11c500 0x100>;
+ clock-frequency = <0>;
+ interrupts = <36 2 0 0>;
+ };
+
+ serial1: serial at 11c600 {
+ cell-index = <1>;
+ device_type = "serial";
+ compatible = "ns16550";
+ reg = <0x11c600 0x100>;
+ clock-frequency = <0>;
+ interrupts = <36 2 0 0>;
+ };
+
+ serial2: serial at 11d500 {
+ cell-index = <2>;
+ device_type = "serial";
+ compatible = "ns16550";
+ reg = <0x11d500 0x100>;
+ clock-frequency = <0>;
+ interrupts = <37 2 0 0>;
+ };
+
+ serial3: serial at 11d600 {
+ cell-index = <3>;
+ device_type = "serial";
+ compatible = "ns16550";
+ reg = <0x11d600 0x100>;
+ clock-frequency = <0>;
+ interrupts = <37 2 0 0>;
+ };
+
+ gpio0: gpio at 130000 {
+ compatible = "fsl,p2041-gpio", "fsl,qoriq-gpio";
+ reg = <0x130000 0x1000>;
+ interrupts = <55 2 0 0>;
+ #gpio-cells = <2>;
+ gpio-controller;
+ };
+
+ rman: rman at 1e0000 {
+ compatible = "fsl,rman";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x1e0000 0x20000>;
+ reg = <0x1e0000 0x20000>;
+ interrupts = <16 2 1 11>; /* err_irq */
+ fsl,qman-channels-id = <0x62 0x63>;
+
+ inbound-block at 0 {
+ compatible = "fsl,rman-inbound-block";
+ reg = <0x0 0x800>;
+ };
+ global-cfg at b00 {
+ compatible = "fsl,rman-global-cfg";
+ reg = <0xb00 0x500>;
+ };
+ inbound-block at 1000 {
+ compatible = "fsl,rman-inbound-block";
+ reg = <0x1000 0x800>;
+ };
+ inbound-block at 2000 {
+ compatible = "fsl,rman-inbound-block";
+ reg = <0x2000 0x800>;
+ };
+ inbound-block at 3000 {
+ compatible = "fsl,rman-inbound-block";
+ reg = <0x3000 0x800>;
+ };
+ };
+
+ usb0: usb at 210000 {
+ compatible = "fsl,p2041-usb2-mph",
+ "fsl,mpc85xx-usb2-mph", "fsl-usb2-mph";
+ reg = <0x210000 0x1000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interrupts = <44 0x2 0 0>;
+ phy_type = "utmi";
+ port0;
+ };
+
+ usb1: usb at 211000 {
+ compatible = "fsl,p2041-usb2-dr",
+ "fsl,mpc85xx-usb2-dr", "fsl-usb2-dr";
+ reg = <0x211000 0x1000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interrupts = <45 0x2 0 0>;
+ phy_type = "utmi";
+ };
+
+ sata at 220000 {
+ compatible = "fsl,p2041-sata", "fsl,pq-sata-v2";
+ reg = <0x220000 0x1000>;
+ interrupts = <68 0x2 0 0>;
+ };
+
+ sata at 221000 {
+ compatible = "fsl,p2041-sata", "fsl,pq-sata-v2";
+ reg = <0x221000 0x1000>;
+ interrupts = <69 0x2 0 0>;
+ };
+
+ crypto: crypto at 300000 {
+ compatible = "fsl,sec-v4.2", "fsl,sec-v4.0";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ reg = <0x300000 0x10000>;
+ ranges = <0 0x300000 0x10000>;
+ interrupts = <92 2 0 0>;
+
+ sec_jr0: jr at 1000 {
+ compatible = "fsl,sec-v4.2-job-ring",
+ "fsl,sec-v4.0-job-ring";
+ reg = <0x1000 0x1000>;
+ interrupts = <88 2 0 0>;
+ };
+
+ sec_jr1: jr at 2000 {
+ compatible = "fsl,sec-v4.2-job-ring",
+ "fsl,sec-v4.0-job-ring";
+ reg = <0x2000 0x1000>;
+ interrupts = <89 2 0 0>;
+ };
+
+ sec_jr2: jr at 3000 {
+ compatible = "fsl,sec-v4.2-job-ring",
+ "fsl,sec-v4.0-job-ring";
+ reg = <0x3000 0x1000>;
+ interrupts = <90 2 0 0>;
+ };
+
+ sec_jr3: jr at 4000 {
+ compatible = "fsl,sec-v4.2-job-ring",
+ "fsl,sec-v4.0-job-ring";
+ reg = <0x4000 0x1000>;
+ interrupts = <91 2 0 0>;
+ };
+
+ rtic at 6000 {
+ compatible = "fsl,sec-v4.2-rtic",
+ "fsl,sec-v4.0-rtic";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ reg = <0x6000 0x100>;
+ ranges = <0x0 0x6100 0xe00>;
+
+ rtic_a: rtic-a at 0 {
+ compatible = "fsl,sec-v4.2-rtic-memory",
+ "fsl,sec-v4.0-rtic-memory";
+ reg = <0x00 0x20 0x100 0x80>;
+ };
+
+ rtic_b: rtic-b at 20 {
+ compatible = "fsl,sec-v4.2-rtic-memory",
+ "fsl,sec-v4.0-rtic-memory";
+ reg = <0x20 0x20 0x200 0x80>;
+ };
+
+ rtic_c: rtic-c at 40 {
+ compatible = "fsl,sec-v4.2-rtic-memory",
+ "fsl,sec-v4.0-rtic-memory";
+ reg = <0x40 0x20 0x300 0x80>;
+ };
+
+ rtic_d: rtic-d at 60 {
+ compatible = "fsl,sec-v4.2-rtic-memory",
+ "fsl,sec-v4.0-rtic-memory";
+ reg = <0x60 0x20 0x500 0x80>;
+ };
+ };
+ };
+
+ sec_mon: sec_mon at 314000 {
+ compatible = "fsl,sec-v4.2-mon", "fsl,sec-v4.0-mon";
+ reg = <0x314000 0x1000>;
+ interrupts = <93 2 0 0>;
+ };
+
+ pme: pme at 316000 {
+ compatible = "fsl,pme";
+ reg = <0x316000 0x10000>;
+ /* fsl,pme-pdsr = <0x0 0x23000000 0x0 0x01000000>; */
+ /* fsl,pme-sre = <0x0 0x24000000 0x0 0x00a00000>; */
+ interrupts = <16 2 1 5>;
+ };
+
+ qman: qman at 318000 {
+ compatible = "fsl,p2041-qman", "fsl,qman";
+ reg = <0x318000 0x1000>;
+ interrupts = <16 2 1 3>;
+ /* Commented out, use default allocation */
+ /* fsl,qman-fqd = <0x0 0x20000000 0x0 0x01000000>; */
+ /* fsl,qman-pfdr = <0x0 0x21000000 0x0 0x01000000>; */
+ };
+
+ bman: bman at 31a000 {
+ compatible = "fsl,p2041-bman", "fsl,bman";
+ reg = <0x31a000 0x1000>;
+ interrupts = <16 2 1 2>;
+ /* Same as fsl,qman-*, use default allocation */
+ /* fsl,bman-fbpr = <0x0 0x22000000 0x0 0x01000000>; */
+ };
+
+ fman0: fman at 400000 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ cell-index = <0>;
+ compatible = "fsl,p2041-fman", "fsl,fman", "simple-bus";
+ ranges = <0 0x400000 0x100000>;
+ reg = <0x400000 0x100000>;
+ clock-frequency = <0>;
+ interrupts = <
+ 96 2 0 0
+ 16 2 1 1>;
+
+ cc at 0 {
+ compatible = "fsl,p2041-fman-cc", "fsl,fman-cc";
+ };
+
+ parser at c7000 {
+ compatible = "fsl,p2041-fman-parser", "fsl,fman-parser";
+ reg = <0xc7000 0x1000>;
+ };
+
+ keygen at c1000 {
+ compatible = "fsl,p2041-fman-keygen", "fsl,fman-keygen";
+ reg = <0xc1000 0x1000>;
+ };
+
+ policer at c0000 {
+ compatible = "fsl,p2041-fman-policer", "fsl,fman-policer";
+ reg = <0xc0000 0x1000>;
+ };
+
+ muram at 0 {
+ compatible = "fsl,p2041-fman-muram", "fsl,fman-muram";
+ reg = <0x0 0x28000>;
+ };
+
+ bmi at 80000 {
+ compatible = "fsl,p2041-fman-bmi", "fsl,fman-bmi";
+ reg = <0x80000 0x400>;
+ };
+
+ qmi at 80400 {
+ compatible = "fsl,p2041-fman-qmi", "fsl,fman-qmi";
+ reg = <0x80400 0x400>;
+ };
+
+ fman0_rx0: port at 88000 {
+ cell-index = <0>;
+ compatible = "fsl,p2041-fman-port-1g-rx", "fsl,fman-port-1g-rx";
+ reg = <0x88000 0x1000>;
+ };
+ fman0_rx1: port at 89000 {
+ cell-index = <1>;
+ compatible = "fsl,p2041-fman-port-1g-rx", "fsl,fman-port-1g-rx";
+ reg = <0x89000 0x1000>;
+ };
+ fman0_rx2: port at 8a000 {
+ cell-index = <2>;
+ compatible = "fsl,p2041-fman-port-1g-rx", "fsl,fman-port-1g-rx";
+ reg = <0x8a000 0x1000>;
+ };
+ fman0_rx3: port at 8b000 {
+ cell-index = <3>;
+ compatible = "fsl,p2041-fman-port-1g-rx", "fsl,fman-port-1g-rx";
+ reg = <0x8b000 0x1000>;
+ };
+ fman0_rx4: port at 8c000 {
+ cell-index = <4>;
+ compatible = "fsl,p2041-fman-port-1g-rx", "fsl,fman-port-1g-rx";
+ reg = <0x8c000 0x1000>;
+ };
+ fman0_rx5: port at 90000 {
+ cell-index = <0>;
+ compatible = "fsl,p2041-fman-port-10g-rx", "fsl,fman-port-10g-rx";
+ reg = <0x90000 0x1000>;
+ };
+
+ fman0_tx5: port at b0000 {
+ cell-index = <0>;
+ compatible = "fsl,p2041-fman-port-10g-tx", "fsl,fman-port-10g-tx";
+ reg = <0xb0000 0x1000>;
+ fsl,qman-channel-id = <0x40>;
+ };
+ fman0_tx0: port at a8000 {
+ cell-index = <0>;
+ compatible = "fsl,p2041-fman-port-1g-tx", "fsl,fman-port-1g-tx";
+ reg = <0xa8000 0x1000>;
+ fsl,qman-channel-id = <0x41>;
+ };
+ fman0_tx1: port at a9000 {
+ cell-index = <1>;
+ compatible = "fsl,p2041-fman-port-1g-tx", "fsl,fman-port-1g-tx";
+ reg = <0xa9000 0x1000>;
+ fsl,qman-channel-id = <0x42>;
+ };
+ fman0_tx2: port at aa000 {
+ cell-index = <2>;
+ compatible = "fsl,p2041-fman-port-1g-tx", "fsl,fman-port-1g-tx";
+ reg = <0xaa000 0x1000>;
+ fsl,qman-channel-id = <0x43>;
+ };
+ fman0_tx3: port at ab000 {
+ cell-index = <3>;
+ compatible = "fsl,p2041-fman-port-1g-tx", "fsl,fman-port-1g-tx";
+ reg = <0xab000 0x1000>;
+ fsl,qman-channel-id = <0x44>;
+ };
+ fman0_tx4: port at ac000 {
+ cell-index = <4>;
+ compatible = "fsl,p2041-fman-port-1g-tx", "fsl,fman-port-1g-tx";
+ reg = <0xac000 0x1000>;
+ fsl,qman-channel-id = <0x45>;
+ };
+
+ fman0_oh0: port at 81000 {
+ cell-index = <0>;
+ compatible = "fsl,p2041-fman-port-oh", "fsl,fman-port-oh";
+ reg = <0x81000 0x1000>;
+ fsl,qman-channel-id = <0x46>;
+ };
+ fman0_oh1: port at 82000 {
+ cell-index = <1>;
+ compatible = "fsl,p2041-fman-port-oh", "fsl,fman-port-oh";
+ reg = <0x82000 0x1000>;
+ fsl,qman-channel-id = <0x47>;
+ };
+ fman0_oh2: port at 83000 {
+ cell-index = <2>;
+ compatible = "fsl,p2041-fman-port-oh", "fsl,fman-port-oh";
+ reg = <0x83000 0x1000>;
+ fsl,qman-channel-id = <0x48>;
+ };
+ fman0_oh3: port at 84000 {
+ cell-index = <3>;
+ compatible = "fsl,p2041-fman-port-oh", "fsl,fman-port-oh";
+ reg = <0x84000 0x1000>;
+ fsl,qman-channel-id = <0x49>;
+ };
+ fman0_oh4: port at 85000 {
+ cell-index = <4>;
+ compatible = "fsl,p2041-fman-port-oh", "fsl,fman-port-oh";
+ reg = <0x85000 0x1000>;
+ fsl,qman-channel-id = <0x4a>;
+ };
+ fman0_oh5: port at 86000 {
+ cell-index = <5>;
+ compatible = "fsl,p2041-fman-port-oh", "fsl,fman-port-oh";
+ reg = <0x86000 0x1000>;
+ fsl,qman-channel-id = <0x4b>;
+ };
+ fman0_oh6: port at 87000 {
+ cell-index = <6>;
+ compatible = "fsl,p2041-fman-port-oh", "fsl,fman-port-oh";
+ reg = <0x87000 0x1000>;
+ };
+
+ enet0: ethernet at e0000 {
+ cell-index = <0>;
+ compatible = "fsl,p2041-fman-1g-mac", "fsl,fman-1g-mac";
+ reg = <0xe0000 0x1000>;
+ fsl,port-handles = <&fman0_rx0 &fman0_tx0>;
+ };
+
+ mdio0: mdio at e1120 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "fsl,fman-mdio";
+ reg = <0xe1120 0xee0>;
+ interrupts = <100 1 0 0>;
+ };
+
+ enet1: ethernet at e2000 {
+ cell-index = <1>;
+ compatible = "fsl,p2041-fman-1g-mac", "fsl,fman-1g-mac";
+ reg = <0xe2000 0x1000>;
+ fsl,port-handles = <&fman0_rx1 &fman0_tx1>;
+ };
+
+ mdio at e3120 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "fsl,fman-tbi";
+ reg = <0xe3120 0xee0>;
+ interrupts = <100 1 0 0>;
+ };
+
+ enet2: ethernet at e4000 {
+ cell-index = <2>;
+ compatible = "fsl,p2041-fman-1g-mac", "fsl,fman-1g-mac";
+ reg = <0xe4000 0x1000>;
+ fsl,port-handles = <&fman0_rx2 &fman0_tx2>;
+ };
+
+ mdio at e5120 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "fsl,fman-tbi";
+ reg = <0xe5120 0xee0>;
+ interrupts = <100 1 0 0>;
+ };
+
+ enet3: ethernet at e6000 {
+ cell-index = <3>;
+ compatible = "fsl,p2041-fman-1g-mac", "fsl,fman-1g-mac";
+ reg = <0xe6000 0x1000>;
+ fsl,port-handles = <&fman0_rx3 &fman0_tx3>;
+ };
+
+ mdio at e7120 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "fsl,fman-tbi";
+ reg = <0xe7120 0xee0>;
+ interrupts = <100 1 0 0>;
+ };
+
+ enet4: ethernet at e8000 {
+ cell-index = <4>;
+ compatible = "fsl,p2041-fman-1g-mac", "fsl,fman-1g-mac";
+ reg = <0xe8000 0x1000>;
+ fsl,port-handles = <&fman0_rx4 &fman0_tx4>;
+ };
+
+ mdio at e9120 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "fsl,fman-tbi";
+ reg = <0xe9120 0xee0>;
+ interrupts = <100 1 0 0>;
+ };
+
+ enet5: ethernet at f0000 {
+ cell-index = <0>;
+ compatible = "fsl,p2041-fman-10g-mac", "fsl,fman-10g-mac";
+ reg = <0xf0000 0x1000>;
+ fsl,port-handles = <&fman0_rx5 &fman0_tx5>;
+ };
+
+ mdio at f1000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "fsl,fman-xmdio";
+ reg = <0xf1000 0x1000>;
+ interrupts = <100 1 0 0>;
+ };
+ };
+ };
+
+ rapidio at ffe0c0000 {
+ compatible = "fsl,srio";
+ interrupts = <16 2 1 11>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ port1 {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ cell-index = <1>;
+ };
+
+ port2 {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ cell-index = <2>;
+ };
+ };
+
+ localbus at ffe124000 {
+ compatible = "fsl,p2041-elbc", "fsl,elbc", "simple-bus";
+ interrupts = <25 2 0 0>;
+ #address-cells = <2>;
+ #size-cells = <1>;
+ };
+
+ pci0: pcie at ffe200000 {
+ compatible = "fsl,p2041-pcie", "fsl,qoriq-pcie-v2.2";
+ device_type = "pci";
+ status = "disabled";
+ #size-cells = <2>;
+ #address-cells = <3>;
+ bus-range = <0x0 0xff>;
+ clock-frequency = <33333333>;
+ fsl,msi = <&msi0>;
+ interrupts = <16 2 1 15>;
+ pcie at 0 {
+ reg = <0 0 0 0 0>;
+ #interrupt-cells = <1>;
+ #size-cells = <2>;
+ #address-cells = <3>;
+ device_type = "pci";
+ interrupts = <16 2 1 15>;
+ interrupt-map-mask = <0xf800 0 0 7>;
+ interrupt-map = <
+ /* IDSEL 0x0 */
+ 0000 0 0 1 &mpic 40 1 0 0
+ 0000 0 0 2 &mpic 1 1 0 0
+ 0000 0 0 3 &mpic 2 1 0 0
+ 0000 0 0 4 &mpic 3 1 0 0
+ >;
+ };
+ };
+
+ pci1: pcie at ffe201000 {
+ compatible = "fsl,p2041-pcie", "fsl,qoriq-pcie-v2.2";
+ device_type = "pci";
+ status = "okay";
+ #size-cells = <2>;
+ #address-cells = <3>;
+ bus-range = <0 0xff>;
+ clock-frequency = <33333333>;
+ fsl,msi = <&msi1>;
+ interrupts = <16 2 1 14>;
+ pcie at 0 {
+ reg = <0 0 0 0 0>;
+ #interrupt-cells = <1>;
+ #size-cells = <2>;
+ #address-cells = <3>;
+ device_type = "pci";
+ interrupts = <16 2 1 14>;
+ interrupt-map-mask = <0xf800 0 0 7>;
+ interrupt-map = <
+ /* IDSEL 0x0 */
+ 0000 0 0 1 &mpic 41 1 0 0
+ 0000 0 0 2 &mpic 5 1 0 0
+ 0000 0 0 3 &mpic 6 1 0 0
+ 0000 0 0 4 &mpic 7 1 0 0
+ >;
+ };
+ };
+
+ pci2: pcie at ffe202000 {
+ compatible = "fsl,p2041-pcie", "fsl,qoriq-pcie-v2.2";
+ device_type = "pci";
+ status = "disabled";
+ #size-cells = <2>;
+ #address-cells = <3>;
+ bus-range = <0x0 0xff>;
+ clock-frequency = <33333333>;
+ fsl,msi = <&msi2>;
+ interrupts = <16 2 1 13>;
+ pcie at 0 {
+ reg = <0 0 0 0 0>;
+ #interrupt-cells = <1>;
+ #size-cells = <2>;
+ #address-cells = <3>;
+ device_type = "pci";
+ interrupts = <16 2 1 13>;
+ interrupt-map-mask = <0xf800 0 0 7>;
+ interrupt-map = <
+ /* IDSEL 0x0 */
+ 0000 0 0 1 &mpic 42 1 0 0
+ 0000 0 0 2 &mpic 9 1 0 0
+ 0000 0 0 3 &mpic 10 1 0 0
+ 0000 0 0 4 &mpic 11 1 0 0
+ >;
+ };
+ };
+};
Property changes on: trunk/sys/boot/fdt/dts/powerpc/p2041si.dtsi
___________________________________________________________________
Added: svn:eol-style
## -0,0 +1 ##
+native
\ No newline at end of property
Added: svn:keywords
## -0,0 +1 ##
+MidnightBSD=%H
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+text/plain
\ No newline at end of property
Added: trunk/sys/boot/fdt/dts/powerpc/p3041si.dtsi
===================================================================
--- trunk/sys/boot/fdt/dts/powerpc/p3041si.dtsi (rev 0)
+++ trunk/sys/boot/fdt/dts/powerpc/p3041si.dtsi 2018-06-02 12:34:49 UTC (rev 10205)
@@ -0,0 +1,1340 @@
+/* $MidnightBSD$ */
+/*
+ * P3041 Silicon Device Tree Source
+ *
+ * Copyright 2010-2011 Freescale Semiconductor Inc.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * * Neither the name of Freescale Semiconductor nor the
+ * names of its contributors may be used to endorse or promote products
+ * derived from this software without specific prior written permission.
+ *
+ *
+ * ALTERNATIVELY, this software may be distributed under the terms of the
+ * GNU General Public License ("GPL") as published by the Free Software
+ * Foundation, either version 2 of that License or (at your option) any
+ * later version.
+ *
+ * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+/* $FreeBSD: stable/10/sys/boot/fdt/dts/powerpc/p3041si.dtsi 266364 2014-05-17 21:55:00Z ian $ */
+
+/dts-v1/;
+
+/ {
+ compatible = "fsl,P3041";
+ #address-cells = <2>;
+ #size-cells = <2>;
+ interrupt-parent = <&mpic>;
+
+ aliases {
+ ccsr = &soc;
+ dcsr = &dcsr;
+
+ ethernet0 = &enet0;
+ ethernet1 = &enet1;
+ ethernet2 = &enet2;
+ ethernet3 = &enet3;
+ ethernet4 = &enet4;
+ ethernet5 = &enet5;
+ serial0 = &serial0;
+ serial1 = &serial1;
+ serial2 = &serial2;
+ serial3 = &serial3;
+ pci0 = &pci0;
+ pci1 = &pci1;
+ pci2 = &pci2;
+ pci3 = &pci3;
+ usb0 = &usb0;
+ usb1 = &usb1;
+ dma0 = &dma0;
+ dma1 = &dma1;
+ bman = &bman;
+ qman = &qman;
+ pme = &pme;
+ rman = &rman;
+ sdhc = &sdhc;
+ msi0 = &msi0;
+ msi1 = &msi1;
+ msi2 = &msi2;
+
+ crypto = &crypto;
+ sec_jr0 = &sec_jr0;
+ sec_jr1 = &sec_jr1;
+ sec_jr2 = &sec_jr2;
+ sec_jr3 = &sec_jr3;
+ rtic_a = &rtic_a;
+ rtic_b = &rtic_b;
+ rtic_c = &rtic_c;
+ rtic_d = &rtic_d;
+ sec_mon = &sec_mon;
+
+ fman0 = &fman0;
+ fman0_oh0 = &fman0_oh0;
+ fman0_oh1 = &fman0_oh1;
+ fman0_oh2 = &fman0_oh2;
+ fman0_oh3 = &fman0_oh3;
+ fman0_oh4 = &fman0_oh4;
+ fman0_oh5 = &fman0_oh5;
+ fman0_oh6 = &fman0_oh6;
+ fman0_rx0 = &fman0_rx0;
+ fman0_rx1 = &fman0_rx1;
+ fman0_rx2 = &fman0_rx2;
+ fman0_rx3 = &fman0_rx3;
+ fman0_rx4 = &fman0_rx4;
+ fman0_rx5 = &fman0_rx5;
+ };
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cpu0: PowerPC,e500mc at 0 {
+ device_type = "cpu";
+ reg = <0>;
+ bus-frequency = <749999996>;
+ next-level-cache = <&L2_0>;
+ L2_0: l2-cache {
+ next-level-cache = <&cpc>;
+ };
+ };
+ cpu1: PowerPC,e500mc at 1 {
+ device_type = "cpu";
+ reg = <1>;
+ next-level-cache = <&L2_1>;
+ L2_1: l2-cache {
+ next-level-cache = <&cpc>;
+ };
+ };
+ cpu2: PowerPC,e500mc at 2 {
+ device_type = "cpu";
+ reg = <2>;
+ next-level-cache = <&L2_2>;
+ L2_2: l2-cache {
+ next-level-cache = <&cpc>;
+ };
+ };
+ cpu3: PowerPC,e500mc at 3 {
+ device_type = "cpu";
+ reg = <3>;
+ next-level-cache = <&L2_3>;
+ L2_3: l2-cache {
+ next-level-cache = <&cpc>;
+ };
+ };
+ };
+
+ dcsr: dcsr at f00000000 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "fsl,dcsr", "simple-bus";
+
+ dcsr-epu at 0 {
+ compatible = "fsl,dcsr-epu";
+ interrupts = <52 2 0 0
+ 84 2 0 0
+ 85 2 0 0>;
+ interrupt-parent = <&mpic>;
+ reg = <0x0 0x1000>;
+ };
+ dcsr-npc {
+ compatible = "fsl,dcsr-npc";
+ reg = <0x1000 0x1000 0x1000000 0x8000>;
+ };
+ dcsr-nxc at 2000 {
+ compatible = "fsl,dcsr-nxc";
+ reg = <0x2000 0x1000>;
+ };
+ dcsr-corenet {
+ compatible = "fsl,dcsr-corenet";
+ reg = <0x8000 0x1000 0xB0000 0x1000>;
+ };
+ dcsr-dpaa at 9000 {
+ compatible = "fsl,p43041-dcsr-dpaa", "fsl,dcsr-dpaa";
+ reg = <0x9000 0x1000>;
+ };
+ dcsr-ocn at 11000 {
+ compatible = "fsl,p43041-dcsr-ocn", "fsl,dcsr-ocn";
+ reg = <0x11000 0x1000>;
+ };
+ dcsr-ddr at 12000 {
+ compatible = "fsl,dcsr-ddr";
+ dev-handle = <&ddr>;
+ reg = <0x12000 0x1000>;
+ };
+ dcsr-nal at 18000 {
+ compatible = "fsl,p43041-dcsr-nal", "fsl,dcsr-nal";
+ reg = <0x18000 0x1000>;
+ };
+ dcsr-rcpm at 22000 {
+ compatible = "fsl,p43041-dcsr-rcpm", "fsl,dcsr-rcpm";
+ reg = <0x22000 0x1000>;
+ };
+ dcsr-cpu-sb-proxy at 40000 {
+ compatible = "fsl,dcsr-e500mc-sb-proxy", "fsl,dcsr-cpu-sb-proxy";
+ cpu-handle = <&cpu0>;
+ reg = <0x40000 0x1000>;
+ };
+ dcsr-cpu-sb-proxy at 41000 {
+ compatible = "fsl,dcsr-e500mc-sb-proxy", "fsl,dcsr-cpu-sb-proxy";
+ cpu-handle = <&cpu1>;
+ reg = <0x41000 0x1000>;
+ };
+ dcsr-cpu-sb-proxy at 42000 {
+ compatible = "fsl,dcsr-e500mc-sb-proxy", "fsl,dcsr-cpu-sb-proxy";
+ cpu-handle = <&cpu2>;
+ reg = <0x42000 0x1000>;
+ };
+ dcsr-cpu-sb-proxy at 43000 {
+ compatible = "fsl,dcsr-e500mc-sb-proxy", "fsl,dcsr-cpu-sb-proxy";
+ cpu-handle = <&cpu3>;
+ reg = <0x43000 0x1000>;
+ };
+ };
+
+ bman-portals at ff4000000 {
+ #address-cells = <0x1>;
+ #size-cells = <0x1>;
+ compatible = "bman-portals";
+ ranges = <0x0 0xf 0xfde00000 0x200000>;
+ bman-portal at 0 {
+ cell-index = <0x0>;
+ compatible = "fsl,p3041-bman-portal", "fsl,bman-portal";
+ reg = <0x0 0x4000 0x100000 0x1000>;
+ interrupts = <105 2 0 0>;
+ };
+ bman-portal at 4000 {
+ cell-index = <0x1>;
+ compatible = "fsl,p3041-bman-portal", "fsl,bman-portal";
+ reg = <0x4000 0x4000 0x101000 0x1000>;
+ interrupts = <107 2 0 0>;
+ };
+ bman-portal at 8000 {
+ cell-index = <2>;
+ compatible = "fsl,p3041-bman-portal", "fsl,bman-portal";
+ reg = <0x8000 0x4000 0x102000 0x1000>;
+ interrupts = <109 2 0 0>;
+ };
+ bman-portal at c000 {
+ cell-index = <0x3>;
+ compatible = "fsl,p3041-bman-portal", "fsl,bman-portal";
+ reg = <0xc000 0x4000 0x103000 0x1000>;
+ interrupts = <111 2 0 0>;
+ };
+ bman-portal at 10000 {
+ cell-index = <0x4>;
+ compatible = "fsl,p3041-bman-portal", "fsl,bman-portal";
+ reg = <0x10000 0x4000 0x104000 0x1000>;
+ interrupts = <113 2 0 0>;
+ };
+ bman-portal at 14000 {
+ cell-index = <0x5>;
+ compatible = "fsl,p3041-bman-portal", "fsl,bman-portal";
+ reg = <0x14000 0x4000 0x105000 0x1000>;
+ interrupts = <115 2 0 0>;
+ };
+ bman-portal at 18000 {
+ cell-index = <0x6>;
+ compatible = "fsl,p3041-bman-portal", "fsl,bman-portal";
+ reg = <0x18000 0x4000 0x106000 0x1000>;
+ interrupts = <117 2 0 0>;
+ };
+ bman-portal at 1c000 {
+ cell-index = <0x7>;
+ compatible = "fsl,p3041-bman-portal", "fsl,bman-portal";
+ reg = <0x1c000 0x4000 0x107000 0x1000>;
+ interrupts = <119 2 0 0>;
+ };
+ bman-portal at 20000 {
+ cell-index = <0x8>;
+ compatible = "fsl,p3041-bman-portal", "fsl,bman-portal";
+ reg = <0x20000 0x4000 0x108000 0x1000>;
+ interrupts = <121 2 0 0>;
+ };
+ bman-portal at 24000 {
+ cell-index = <0x9>;
+ compatible = "fsl,p3041-bman-portal", "fsl,bman-portal";
+ reg = <0x24000 0x4000 0x109000 0x1000>;
+ interrupts = <123 2 0 0>;
+ };
+
+ buffer-pool at 0 {
+ compatible = "fsl,p3041-bpool", "fsl,bpool";
+ fsl,bpid = <0>;
+ fsl,bpool-cfg = <0 0x100 0 1 0 0x100>;
+ };
+ };
+
+ qman-portals at ff4200000 {
+ #address-cells = <0x1>;
+ #size-cells = <0x1>;
+ compatible = "qman-portals";
+ ranges = <0x0 0xf 0xfdc00000 0x200000>;
+ qportal0: qman-portal at 0 {
+ cell-index = <0x0>;
+ compatible = "fsl,p3041-qman-portal", "fsl,qman-portal";
+ reg = <0x0 0x4000 0x100000 0x1000>;
+ interrupts = <104 0x2 0 0>;
+ fsl,qman-channel-id = <0x0>;
+ };
+
+ qportal1: qman-portal at 4000 {
+ cell-index = <0x1>;
+ compatible = "fsl,p3041-qman-portal", "fsl,qman-portal";
+ reg = <0x4000 0x4000 0x101000 0x1000>;
+ interrupts = <106 0x2 0 0>;
+ fsl,qman-channel-id = <0x1>;
+ };
+
+ qportal2: qman-portal at 8000 {
+ cell-index = <0x2>;
+ compatible = "fsl,p3041-qman-portal", "fsl,qman-portal";
+ reg = <0x8000 0x4000 0x102000 0x1000>;
+ interrupts = <108 0x2 0 0>;
+ fsl,qman-channel-id = <0x2>;
+ };
+
+ qportal3: qman-portal at c000 {
+ cell-index = <0x3>;
+ compatible = "fsl,p3041-qman-portal", "fsl,qman-portal";
+ reg = <0xc000 0x4000 0x103000 0x1000>;
+ interrupts = <110 0x2 0 0>;
+ fsl,qman-channel-id = <0x3>;
+ };
+
+ qportal4: qman-portal at 10000 {
+ cell-index = <0x4>;
+ compatible = "fsl,p3041-qman-portal", "fsl,qman-portal";
+ reg = <0x10000 0x4000 0x104000 0x1000>;
+ interrupts = <112 0x2 0 0>;
+ fsl,qman-channel-id = <0x4>;
+ };
+
+ qportal5: qman-portal at 14000 {
+ cell-index = <0x5>;
+ compatible = "fsl,p3041-qman-portal", "fsl,qman-portal";
+ reg = <0x14000 0x4000 0x105000 0x1000>;
+ interrupts = <114 0x2 0 0>;
+ fsl,qman-channel-id = <0x5>;
+ };
+
+ qportal6: qman-portal at 18000 {
+ cell-index = <0x6>;
+ compatible = "fsl,p3041-qman-portal", "fsl,qman-portal";
+ reg = <0x18000 0x4000 0x106000 0x1000>;
+ interrupts = <116 0x2 0 0>;
+ fsl,qman-channel-id = <0x6>;
+ };
+
+ qportal7: qman-portal at 1c000 {
+ cell-index = <0x7>;
+ compatible = "fsl,p3041-qman-portal", "fsl,qman-portal";
+ reg = <0x1c000 0x4000 0x107000 0x1000>;
+ interrupts = <118 0x2 0 0>;
+ fsl,qman-channel-id = <0x7>;
+ };
+
+ qportal8: qman-portal at 20000 {
+ cell-index = <0x8>;
+ compatible = "fsl,p3041-qman-portal", "fsl,qman-portal";
+ reg = <0x20000 0x4000 0x108000 0x1000>;
+ interrupts = <120 0x2 0 0>;
+ fsl,qman-channel-id = <0x8>;
+ };
+
+ qportal9: qman-portal at 24000 {
+ cell-index = <0x9>;
+ compatible = "fsl,p3041-qman-portal", "fsl,qman-portal";
+ reg = <0x24000 0x4000 0x109000 0x1000>;
+ interrupts = <122 0x2 0 0>;
+ fsl,qman-channel-id = <0x9>;
+ };
+
+ qpool1: qman-pool at 1 {
+ cell-index = <1>;
+ compatible = "fsl,p3041-qman-pool-channel", "fsl,qman-pool-channel";
+ fsl,qman-channel-id = <0x21>;
+ };
+
+ qpool2: qman-pool at 2 {
+ cell-index = <2>;
+ compatible = "fsl,p3041-qman-pool-channel", "fsl,qman-pool-channel";
+ fsl,qman-channel-id = <0x22>;
+ };
+
+ qpool3: qman-pool at 3 {
+ cell-index = <3>;
+ compatible = "fsl,p3041-qman-pool-channel", "fsl,qman-pool-channel";
+ fsl,qman-channel-id = <0x23>;
+ };
+
+ qpool4: qman-pool at 4 {
+ cell-index = <4>;
+ compatible = "fsl,p3041-qman-pool-channel", "fsl,qman-pool-channel";
+ fsl,qman-channel-id = <0x24>;
+ };
+
+ qpool5: qman-pool at 5 {
+ cell-index = <5>;
+ compatible = "fsl,p3041-qman-pool-channel", "fsl,qman-pool-channel";
+ fsl,qman-channel-id = <0x25>;
+ };
+
+ qpool6: qman-pool at 6 {
+ cell-index = <6>;
+ compatible = "fsl,p3041-qman-pool-channel", "fsl,qman-pool-channel";
+ fsl,qman-channel-id = <0x26>;
+ };
+
+ qpool7: qman-pool at 7 {
+ cell-index = <7>;
+ compatible = "fsl,p3041-qman-pool-channel", "fsl,qman-pool-channel";
+ fsl,qman-channel-id = <0x27>;
+ };
+
+ qpool8: qman-pool at 8 {
+ cell-index = <8>;
+ compatible = "fsl,p3041-qman-pool-channel", "fsl,qman-pool-channel";
+ fsl,qman-channel-id = <0x28>;
+ };
+
+ qpool9: qman-pool at 9 {
+ cell-index = <9>;
+ compatible = "fsl,p3041-qman-pool-channel", "fsl,qman-pool-channel";
+ fsl,qman-channel-id = <0x29>;
+ };
+
+ qpool10: qman-pool at 10 {
+ cell-index = <10>;
+ compatible = "fsl,p3041-qman-pool-channel", "fsl,qman-pool-channel";
+ fsl,qman-channel-id = <0x2a>;
+ };
+
+ qpool11: qman-pool at 11 {
+ cell-index = <11>;
+ compatible = "fsl,p3041-qman-pool-channel", "fsl,qman-pool-channel";
+ fsl,qman-channel-id = <0x2b>;
+ };
+
+ qpool12: qman-pool at 12 {
+ cell-index = <12>;
+ compatible = "fsl,p3041-qman-pool-channel", "fsl,qman-pool-channel";
+ fsl,qman-channel-id = <0x2c>;
+ };
+
+ qpool13: qman-pool at 13 {
+ cell-index = <13>;
+ compatible = "fsl,p3041-qman-pool-channel", "fsl,qman-pool-channel";
+ fsl,qman-channel-id = <0x2d>;
+ };
+
+ qpool14: qman-pool at 14 {
+ cell-index = <14>;
+ compatible = "fsl,p3041-qman-pool-channel", "fsl,qman-pool-channel";
+ fsl,qman-channel-id = <0x2e>;
+ };
+
+ qpool15: qman-pool at 15 {
+ cell-index = <15>;
+ compatible = "fsl,p3041-qman-pool-channel", "fsl,qman-pool-channel";
+ fsl,qman-channel-id = <0x2f>;
+ };
+ };
+
+ soc: soc at ffe000000 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ device_type = "soc";
+ compatible = "simple-bus";
+
+ bus-frequency = <0>; // Filled out by kernel.
+
+ ranges = <0x00000000 0xf 0xfe000000 0x1000000>;
+ reg = <0xf 0xfe000000 0 0x00001000>;
+
+ soc-sram-error {
+ compatible = "fsl,soc-sram-error";
+ interrupts = <16 2 1 29>;
+ };
+
+ corenet-law at 0 {
+ compatible = "fsl,corenet-law";
+ reg = <0x0 0x1000>;
+ fsl,num-laws = <32>;
+ };
+
+ ddr: memory-controller at 8000 {
+ compatible = "fsl,qoriq-memory-controller-v4.5", "fsl,qoriq-memory-controller";
+ reg = <0x8000 0x1000>;
+ interrupts = <16 2 1 23>;
+ };
+
+ cpc: l3-cache-controller at 10000 {
+ compatible = "fsl,p3041-l3-cache-controller", "fsl,p4080-l3-cache-controller", "cache";
+ reg = <0x10000 0x1000>;
+ interrupts = <16 2 1 27>;
+ };
+
+ corenet-cf at 18000 {
+ compatible = "fsl,corenet-cf";
+ reg = <0x18000 0x1000>;
+ interrupts = <16 2 1 31>;
+ fsl,ccf-num-csdids = <32>;
+ fsl,ccf-num-snoopids = <32>;
+ };
+
+ iommu at 20000 {
+ compatible = "fsl,pamu-v1.0", "fsl,pamu";
+ reg = <0x20000 0x4000>;
+ interrupts = <
+ 24 2 0 0
+ 16 2 1 30>;
+ };
+
+ mpic: pic at 40000 {
+ clock-frequency = <0>;
+ interrupt-controller;
+ #address-cells = <0>;
+ #interrupt-cells = <4>;
+ reg = <0x40000 0x40000>;
+ compatible = "fsl,mpic", "chrp,open-pic";
+ device_type = "open-pic";
+ };
+
+ msi0: msi at 41600 {
+ compatible = "fsl,mpic-msi";
+ reg = <0x41600 0x200>;
+ msi-available-ranges = <0 0x100>;
+ interrupts = <
+ 0xe0 0 0 0
+ 0xe1 0 0 0
+ 0xe2 0 0 0
+ 0xe3 0 0 0
+ 0xe4 0 0 0
+ 0xe5 0 0 0
+ 0xe6 0 0 0
+ 0xe7 0 0 0>;
+ };
+
+ msi1: msi at 41800 {
+ compatible = "fsl,mpic-msi";
+ reg = <0x41800 0x200>;
+ msi-available-ranges = <0 0x100>;
+ interrupts = <
+ 0xe8 0 0 0
+ 0xe9 0 0 0
+ 0xea 0 0 0
+ 0xeb 0 0 0
+ 0xec 0 0 0
+ 0xed 0 0 0
+ 0xee 0 0 0
+ 0xef 0 0 0>;
+ };
+
+ msi2: msi at 41a00 {
+ compatible = "fsl,mpic-msi";
+ reg = <0x41a00 0x200>;
+ msi-available-ranges = <0 0x100>;
+ interrupts = <
+ 0xf0 0 0 0
+ 0xf1 0 0 0
+ 0xf2 0 0 0
+ 0xf3 0 0 0
+ 0xf4 0 0 0
+ 0xf5 0 0 0
+ 0xf6 0 0 0
+ 0xf7 0 0 0>;
+ };
+
+ guts: global-utilities at e0000 {
+ compatible = "fsl,qoriq-device-config-1.0";
+ reg = <0xe0000 0xe00>;
+ fsl,has-rstcr;
+ #sleep-cells = <1>;
+ fsl,liodn-bits = <12>;
+ };
+
+ pins: global-utilities at e0e00 {
+ compatible = "fsl,qoriq-pin-control-1.0";
+ reg = <0xe0e00 0x200>;
+ #sleep-cells = <2>;
+ };
+
+ clockgen: global-utilities at e1000 {
+ compatible = "fsl,p3041-clockgen", "fsl,qoriq-clockgen-1.0";
+ reg = <0xe1000 0x1000>;
+ clock-frequency = <0>;
+ };
+
+ rcpm: global-utilities at e2000 {
+ compatible = "fsl,qoriq-rcpm-1.0";
+ reg = <0xe2000 0x1000>;
+ #sleep-cells = <1>;
+ };
+
+ sfp: sfp at e8000 {
+ compatible = "fsl,p3041-sfp", "fsl,qoriq-sfp-1.0";
+ reg = <0xe8000 0x1000>;
+ };
+
+ serdes: serdes at ea000 {
+ compatible = "fsl,p3041-serdes";
+ reg = <0xea000 0x1000>;
+ };
+
+ dma0: dma at 100300 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "fsl,p3041-dma", "fsl,eloplus-dma";
+ reg = <0x100300 0x4>;
+ ranges = <0x0 0x100100 0x200>;
+ cell-index = <0>;
+ dma-channel at 0 {
+ compatible = "fsl,p3041-dma-channel",
+ "fsl,eloplus-dma-channel";
+ reg = <0x0 0x80>;
+ cell-index = <0>;
+ interrupts = <28 2 0 0>;
+ };
+ dma-channel at 80 {
+ compatible = "fsl,p3041-dma-channel",
+ "fsl,eloplus-dma-channel";
+ reg = <0x80 0x80>;
+ cell-index = <1>;
+ interrupts = <29 2 0 0>;
+ };
+ dma-channel at 100 {
+ compatible = "fsl,p3041-dma-channel",
+ "fsl,eloplus-dma-channel";
+ reg = <0x100 0x80>;
+ cell-index = <2>;
+ interrupts = <30 2 0 0>;
+ };
+ dma-channel at 180 {
+ compatible = "fsl,p3041-dma-channel",
+ "fsl,eloplus-dma-channel";
+ reg = <0x180 0x80>;
+ cell-index = <3>;
+ interrupts = <31 2 0 0>;
+ };
+ };
+
+ dma1: dma at 101300 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "fsl,p3041-dma", "fsl,eloplus-dma";
+ reg = <0x101300 0x4>;
+ ranges = <0x0 0x101100 0x200>;
+ cell-index = <1>;
+ dma-channel at 0 {
+ compatible = "fsl,p3041-dma-channel",
+ "fsl,eloplus-dma-channel";
+ reg = <0x0 0x80>;
+ cell-index = <0>;
+ interrupts = <32 2 0 0>;
+ };
+ dma-channel at 80 {
+ compatible = "fsl,p3041-dma-channel",
+ "fsl,eloplus-dma-channel";
+ reg = <0x80 0x80>;
+ cell-index = <1>;
+ interrupts = <33 2 0 0>;
+ };
+ dma-channel at 100 {
+ compatible = "fsl,p3041-dma-channel",
+ "fsl,eloplus-dma-channel";
+ reg = <0x100 0x80>;
+ cell-index = <2>;
+ interrupts = <34 2 0 0>;
+ };
+ dma-channel at 180 {
+ compatible = "fsl,p3041-dma-channel",
+ "fsl,eloplus-dma-channel";
+ reg = <0x180 0x80>;
+ cell-index = <3>;
+ interrupts = <35 2 0 0>;
+ };
+ };
+
+ spi at 110000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "fsl,p3041-espi", "fsl,mpc8536-espi";
+ reg = <0x110000 0x1000>;
+ interrupts = <53 0x2 0 0>;
+ fsl,espi-num-chipselects = <4>;
+ };
+
+ sdhc: sdhc at 114000 {
+ compatible = "fsl,p3041-esdhc", "fsl,esdhc";
+ reg = <0x114000 0x1000>;
+ interrupts = <48 2 0 0>;
+ sdhci,auto-cmd12;
+ clock-frequency = <0>;
+ };
+
+ i2c at 118000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ cell-index = <0>;
+ compatible = "fsl-i2c";
+ reg = <0x118000 0x100>;
+ interrupts = <38 2 0 0>;
+ dfsrr;
+ };
+
+ i2c at 118100 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ cell-index = <1>;
+ compatible = "fsl-i2c";
+ reg = <0x118100 0x100>;
+ interrupts = <38 2 0 0>;
+ dfsrr;
+ };
+
+ i2c at 119000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ cell-index = <2>;
+ compatible = "fsl-i2c";
+ reg = <0x119000 0x100>;
+ interrupts = <39 2 0 0>;
+ dfsrr;
+ };
+
+ i2c at 119100 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ cell-index = <3>;
+ compatible = "fsl-i2c";
+ reg = <0x119100 0x100>;
+ interrupts = <39 2 0 0>;
+ dfsrr;
+ };
+
+ serial0: serial at 11c500 {
+ cell-index = <0>;
+ device_type = "serial";
+ compatible = "ns16550";
+ reg = <0x11c500 0x100>;
+ clock-frequency = <0>;
+ interrupts = <36 2 0 0>;
+ };
+
+ serial1: serial at 11c600 {
+ cell-index = <1>;
+ device_type = "serial";
+ compatible = "ns16550";
+ reg = <0x11c600 0x100>;
+ clock-frequency = <0>;
+ interrupts = <36 2 0 0>;
+ };
+
+ serial2: serial at 11d500 {
+ cell-index = <2>;
+ device_type = "serial";
+ compatible = "ns16550";
+ reg = <0x11d500 0x100>;
+ clock-frequency = <0>;
+ interrupts = <37 2 0 0>;
+ };
+
+ serial3: serial at 11d600 {
+ cell-index = <3>;
+ device_type = "serial";
+ compatible = "ns16550";
+ reg = <0x11d600 0x100>;
+ clock-frequency = <0>;
+ interrupts = <37 2 0 0>;
+ };
+
+ gpio0: gpio at 130000 {
+ compatible = "fsl,p3041-gpio", "fsl,qoriq-gpio";
+ reg = <0x130000 0x1000>;
+ interrupts = <55 2 0 0>;
+ #gpio-cells = <2>;
+ gpio-controller;
+ };
+
+ rman: rman at 1e0000 {
+ compatible = "fsl,rman";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x1e0000 0x20000>;
+ reg = <0x1e0000 0x20000>;
+ interrupts = <16 2 1 11>; /* err_irq */
+ fsl,qman-channels-id = <0x62 0x63>;
+
+ inbound-block at 0 {
+ compatible = "fsl,rman-inbound-block";
+ reg = <0x0 0x800>;
+ };
+ global-cfg at b00 {
+ compatible = "fsl,rman-global-cfg";
+ reg = <0xb00 0x500>;
+ };
+ inbound-block at 1000 {
+ compatible = "fsl,rman-inbound-block";
+ reg = <0x1000 0x800>;
+ };
+ inbound-block at 2000 {
+ compatible = "fsl,rman-inbound-block";
+ reg = <0x2000 0x800>;
+ };
+ inbound-block at 3000 {
+ compatible = "fsl,rman-inbound-block";
+ reg = <0x3000 0x800>;
+ };
+ };
+
+ usb0: usb at 210000 {
+ compatible = "fsl,p3041-usb2-mph",
+ "fsl,mpc85xx-usb2-mph", "fsl-usb2-mph";
+ reg = <0x210000 0x1000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interrupts = <44 0x2 0 0>;
+ phy_type = "utmi";
+ port0;
+ };
+
+ usb1: usb at 211000 {
+ compatible = "fsl,p3041-usb2-dr",
+ "fsl,mpc85xx-usb2-dr", "fsl-usb2-dr";
+ reg = <0x211000 0x1000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interrupts = <45 0x2 0 0>;
+ dr_mode = "host";
+ phy_type = "utmi";
+ };
+
+ sata at 220000 {
+ compatible = "fsl,p3041-sata", "fsl,pq-sata-v2";
+ reg = <0x220000 0x1000>;
+ interrupts = <68 0x2 0 0>;
+ };
+
+ sata at 221000 {
+ compatible = "fsl,p3041-sata", "fsl,pq-sata-v2";
+ reg = <0x221000 0x1000>;
+ interrupts = <69 0x2 0 0>;
+ };
+
+ crypto: crypto at 300000 {
+ compatible = "fsl,sec-v4.2", "fsl,sec-v4.0";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ reg = <0x300000 0x10000>;
+ ranges = <0 0x300000 0x10000>;
+ interrupts = <92 2 0 0>;
+
+ sec_jr0: jr at 1000 {
+ compatible = "fsl,sec-v4.2-job-ring",
+ "fsl,sec-v4.0-job-ring";
+ reg = <0x1000 0x1000>;
+ interrupts = <88 2 0 0>;
+ };
+
+ sec_jr1: jr at 2000 {
+ compatible = "fsl,sec-v4.2-job-ring",
+ "fsl,sec-v4.0-job-ring";
+ reg = <0x2000 0x1000>;
+ interrupts = <89 2 0 0>;
+ };
+
+ sec_jr2: jr at 3000 {
+ compatible = "fsl,sec-v4.2-job-ring",
+ "fsl,sec-v4.0-job-ring";
+ reg = <0x3000 0x1000>;
+ interrupts = <90 2 0 0>;
+ };
+
+ sec_jr3: jr at 4000 {
+ compatible = "fsl,sec-v4.2-job-ring",
+ "fsl,sec-v4.0-job-ring";
+ reg = <0x4000 0x1000>;
+ interrupts = <91 2 0 0>;
+ };
+
+ rtic at 6000 {
+ compatible = "fsl,sec-v4.2-rtic",
+ "fsl,sec-v4.0-rtic";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ reg = <0x6000 0x100>;
+ ranges = <0x0 0x6100 0xe00>;
+
+ rtic_a: rtic-a at 0 {
+ compatible = "fsl,sec-v4.2-rtic-memory",
+ "fsl,sec-v4.0-rtic-memory";
+ reg = <0x00 0x20 0x100 0x80>;
+ };
+
+ rtic_b: rtic-b at 20 {
+ compatible = "fsl,sec-v4.2-rtic-memory",
+ "fsl,sec-v4.0-rtic-memory";
+ reg = <0x20 0x20 0x200 0x80>;
+ };
+
+ rtic_c: rtic-c at 40 {
+ compatible = "fsl,sec-v4.2-rtic-memory",
+ "fsl,sec-v4.0-rtic-memory";
+ reg = <0x40 0x20 0x300 0x80>;
+ };
+
+ rtic_d: rtic-d at 60 {
+ compatible = "fsl,sec-v4.2-rtic-memory",
+ "fsl,sec-v4.0-rtic-memory";
+ reg = <0x60 0x20 0x500 0x80>;
+ };
+ };
+ };
+
+ sec_mon: sec_mon at 314000 {
+ compatible = "fsl,sec-v4.2-mon", "fsl,sec-v4.0-mon";
+ reg = <0x314000 0x1000>;
+ interrupts = <93 2 0 0>;
+ };
+
+ pme: pme at 316000 {
+ compatible = "fsl,pme";
+ reg = <0x316000 0x10000>;
+ /* fsl,pme-pdsr = <0x0 0x23000000 0x0 0x01000000>; */
+ /* fsl,pme-sre = <0x0 0x24000000 0x0 0x00a00000>; */
+ interrupts = <16 2 1 5>;
+ };
+
+ qman: qman at 318000 {
+ compatible = "fsl,p3041-qman", "fsl,qman";
+ reg = <0x318000 0x1000>;
+ interrupts = <16 2 1 3>;
+ /* Commented out, use default allocation */
+ /* fsl,qman-fqd = <0x0 0x20000000 0x0 0x01000000>; */
+ /* fsl,qman-pfdr = <0x0 0x21000000 0x0 0x01000000>; */
+ };
+
+ bman: bman at 31a000 {
+ compatible = "fsl,p3041-bman", "fsl,bman";
+ reg = <0x31a000 0x1000>;
+ interrupts = <16 2 1 2>;
+ /* Same as fsl,qman-*, use default allocation */
+ /* fsl,bman-fbpr = <0x0 0x22000000 0x0 0x01000000>; */
+ };
+
+ fman0: fman at 400000 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ cell-index = <0>;
+ compatible = "fsl,p3041-fman", "fsl,fman", "simple-bus";
+ ranges = <0 0x400000 0x100000>;
+ reg = <0x400000 0x100000>;
+ clock-frequency = <0>;
+ interrupts = <
+ 96 2 0 0
+ 16 2 1 1>;
+
+ cc at 0 {
+ compatible = "fsl,p3041-fman-cc", "fsl,fman-cc";
+ };
+
+ parser at c7000 {
+ compatible = "fsl,p3041-fman-parser", "fsl,fman-parser";
+ reg = <0xc7000 0x1000>;
+ };
+
+ keygen at c1000 {
+ compatible = "fsl,p3041-fman-keygen", "fsl,fman-keygen";
+ reg = <0xc1000 0x1000>;
+ };
+
+ policer at c0000 {
+ compatible = "fsl,p3041-fman-policer", "fsl,fman-policer";
+ reg = <0xc0000 0x1000>;
+ };
+
+ muram at 0 {
+ compatible = "fsl,p3041-fman-muram", "fsl,fman-muram";
+ reg = <0x0 0x28000>;
+ };
+
+ bmi at 80000 {
+ compatible = "fsl,p3041-fman-bmi", "fsl,fman-bmi";
+ reg = <0x80000 0x400>;
+ };
+
+ qmi at 80400 {
+ compatible = "fsl,p3041-fman-qmi", "fsl,fman-qmi";
+ reg = <0x80400 0x400>;
+ };
+
+ fman0_rx0: port at 88000 {
+ cell-index = <0>;
+ compatible = "fsl,p3041-fman-port-1g-rx", "fsl,fman-port-1g-rx";
+ reg = <0x88000 0x1000>;
+ };
+ fman0_rx1: port at 89000 {
+ cell-index = <1>;
+ compatible = "fsl,p3041-fman-port-1g-rx", "fsl,fman-port-1g-rx";
+ reg = <0x89000 0x1000>;
+ };
+ fman0_rx2: port at 8a000 {
+ cell-index = <2>;
+ compatible = "fsl,p3041-fman-port-1g-rx", "fsl,fman-port-1g-rx";
+ reg = <0x8a000 0x1000>;
+ };
+ fman0_rx3: port at 8b000 {
+ cell-index = <3>;
+ compatible = "fsl,p3041-fman-port-1g-rx", "fsl,fman-port-1g-rx";
+ reg = <0x8b000 0x1000>;
+ };
+ fman0_rx4: port at 8c000 {
+ cell-index = <4>;
+ compatible = "fsl,p3041-fman-port-1g-rx", "fsl,fman-port-1g-rx";
+ reg = <0x8c000 0x1000>;
+ };
+ fman0_rx5: port at 90000 {
+ cell-index = <0>;
+ compatible = "fsl,p3041-fman-port-10g-rx", "fsl,fman-port-10g-rx";
+ reg = <0x90000 0x1000>;
+ };
+
+ fman0_tx5: port at b0000 {
+ cell-index = <0>;
+ compatible = "fsl,p3041-fman-port-10g-tx", "fsl,fman-port-10g-tx";
+ reg = <0xb0000 0x1000>;
+ fsl,qman-channel-id = <0x40>;
+ };
+ fman0_tx0: port at a8000 {
+ cell-index = <0>;
+ compatible = "fsl,p3041-fman-port-1g-tx", "fsl,fman-port-1g-tx";
+ reg = <0xa8000 0x1000>;
+ fsl,qman-channel-id = <0x41>;
+ };
+ fman0_tx1: port at a9000 {
+ cell-index = <1>;
+ compatible = "fsl,p3041-fman-port-1g-tx", "fsl,fman-port-1g-tx";
+ reg = <0xa9000 0x1000>;
+ fsl,qman-channel-id = <0x42>;
+ };
+ fman0_tx2: port at aa000 {
+ cell-index = <2>;
+ compatible = "fsl,p3041-fman-port-1g-tx", "fsl,fman-port-1g-tx";
+ reg = <0xaa000 0x1000>;
+ fsl,qman-channel-id = <0x43>;
+ };
+ fman0_tx3: port at ab000 {
+ cell-index = <3>;
+ compatible = "fsl,p3041-fman-port-1g-tx", "fsl,fman-port-1g-tx";
+ reg = <0xab000 0x1000>;
+ fsl,qman-channel-id = <0x44>;
+ };
+ fman0_tx4: port at ac000 {
+ cell-index = <4>;
+ compatible = "fsl,p3041-fman-port-1g-tx", "fsl,fman-port-1g-tx";
+ reg = <0xac000 0x1000>;
+ fsl,qman-channel-id = <0x45>;
+ };
+
+ fman0_oh0: port at 81000 {
+ cell-index = <0>;
+ compatible = "fsl,p3041-fman-port-oh", "fsl,fman-port-oh";
+ reg = <0x81000 0x1000>;
+ fsl,qman-channel-id = <0x46>;
+ };
+ fman0_oh1: port at 82000 {
+ cell-index = <1>;
+ compatible = "fsl,p3041-fman-port-oh", "fsl,fman-port-oh";
+ reg = <0x82000 0x1000>;
+ fsl,qman-channel-id = <0x47>;
+ };
+ fman0_oh2: port at 83000 {
+ cell-index = <2>;
+ compatible = "fsl,p3041-fman-port-oh", "fsl,fman-port-oh";
+ reg = <0x83000 0x1000>;
+ fsl,qman-channel-id = <0x48>;
+ };
+ fman0_oh3: port at 84000 {
+ cell-index = <3>;
+ compatible = "fsl,p3041-fman-port-oh", "fsl,fman-port-oh";
+ reg = <0x84000 0x1000>;
+ fsl,qman-channel-id = <0x49>;
+ };
+ fman0_oh4: port at 85000 {
+ cell-index = <4>;
+ compatible = "fsl,p3041-fman-port-oh", "fsl,fman-port-oh";
+ reg = <0x85000 0x1000>;
+ fsl,qman-channel-id = <0x4a>;
+ };
+ fman0_oh5: port at 86000 {
+ cell-index = <5>;
+ compatible = "fsl,p3041-fman-port-oh", "fsl,fman-port-oh";
+ reg = <0x86000 0x1000>;
+ fsl,qman-channel-id = <0x4b>;
+ };
+ fman0_oh6: port at 87000 {
+ cell-index = <6>;
+ compatible = "fsl,p3041-fman-port-oh", "fsl,fman-port-oh";
+ reg = <0x87000 0x1000>;
+ };
+
+ enet0: ethernet at e0000 {
+ cell-index = <0>;
+ compatible = "fsl,p3041-fman-1g-mac", "fsl,fman-1g-mac";
+ reg = <0xe0000 0x1000>;
+ fsl,port-handles = <&fman0_rx0 &fman0_tx0>;
+ ptimer-handle = <&ptp_timer0>;
+ };
+
+ mdio0: mdio at e1120 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "fsl,fman-mdio";
+ reg = <0xe1120 0xee0>;
+ interrupts = <100 1 0 0>;
+ };
+
+ enet1: ethernet at e2000 {
+ cell-index = <1>;
+ compatible = "fsl,p3041-fman-1g-mac", "fsl,fman-1g-mac";
+ reg = <0xe2000 0x1000>;
+ fsl,port-handles = <&fman0_rx1 &fman0_tx1>;
+ ptimer-handle = <&ptp_timer0>;
+ };
+
+ mdio at e3120 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "fsl,fman-tbi";
+ reg = <0xe3120 0xee0>;
+ interrupts = <100 1 0 0>;
+ };
+
+ enet2: ethernet at e4000 {
+ cell-index = <2>;
+ compatible = "fsl,p3041-fman-1g-mac", "fsl,fman-1g-mac";
+ reg = <0xe4000 0x1000>;
+ fsl,port-handles = <&fman0_rx2 &fman0_tx2>;
+ ptimer-handle = <&ptp_timer0>;
+ };
+
+ mdio at e5120 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "fsl,fman-tbi";
+ reg = <0xe5120 0xee0>;
+ interrupts = <100 1 0 0>;
+ };
+
+ enet3: ethernet at e6000 {
+ cell-index = <3>;
+ compatible = "fsl,p3041-fman-1g-mac", "fsl,fman-1g-mac";
+ reg = <0xe6000 0x1000>;
+ fsl,port-handles = <&fman0_rx3 &fman0_tx3>;
+ };
+
+ mdio at e7120 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "fsl,fman-tbi";
+ reg = <0xe7120 0xee0>;
+ interrupts = <100 1 0 0>;
+ };
+
+ enet4: ethernet at e8000 {
+ cell-index = <4>;
+ compatible = "fsl,p3041-fman-1g-mac", "fsl,fman-1g-mac";
+ reg = <0xe8000 0x1000>;
+ fsl,port-handles = <&fman0_rx4 &fman0_tx4>;
+ ptimer-handle = <&ptp_timer0>;
+ };
+
+ mdio at e9120 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "fsl,fman-tbi";
+ reg = <0xe9120 0xee0>;
+ interrupts = <100 1 0 0>;
+ };
+
+ enet5: ethernet at f0000 {
+ cell-index = <0>;
+ compatible = "fsl,p3041-fman-10g-mac", "fsl,fman-10g-mac";
+ reg = <0xf0000 0x1000>;
+ fsl,port-handles = <&fman0_rx5 &fman0_tx5>;
+ };
+
+ mdio at f1000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "fsl,fman-xmdio";
+ reg = <0xf1000 0x1000>;
+ interrupts = <100 1 0 0>;
+ };
+
+ ptp_timer0: rtc at fe000 {
+ compatible = "fsl,fman-rtc";
+ reg = <0xfe000 0x1000>;
+ };
+ };
+ };
+
+ rapidio at ffe0c0000 {
+ compatible = "fsl,srio";
+ interrupts = <16 2 1 11>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ port1 {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ cell-index = <1>;
+ };
+
+ port2 {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ cell-index = <2>;
+ };
+ };
+
+ localbus at ffe124000 {
+ compatible = "fsl,p3041-rev1.0-elbc", "simple-bus", "fsl,elbc";
+ interrupts = <
+ 25 2 0 0
+ 16 2 1 19
+ >;
+ #address-cells = <2>;
+ #size-cells = <1>;
+ };
+
+ pci0: pcie at ffe200000 {
+ compatible = "fsl,p3041-pcie", "fsl,qoriq-pcie-v2.2";
+ device_type = "pci";
+ status = "okay";
+ #size-cells = <2>;
+ #address-cells = <3>;
+ bus-range = <0x0 0xff>;
+ clock-frequency = <0x1fca055>;
+ fsl,msi = <&msi0>;
+ interrupts = <16 2 1 15>;
+
+ pcie at 0 {
+ reg = <0 0 0 0 0>;
+ #interrupt-cells = <1>;
+ #size-cells = <2>;
+ #address-cells = <3>;
+ device_type = "pci";
+ interrupts = <16 2 1 15>;
+ interrupt-map-mask = <0xf800 0 0 7>;
+ interrupt-map = <
+ /* IDSEL 0x0 */
+ 0000 0 0 1 &mpic 40 1 0 0
+ 0000 0 0 2 &mpic 1 1 0 0
+ 0000 0 0 3 &mpic 2 1 0 0
+ 0000 0 0 4 &mpic 3 1 0 0
+ >;
+ };
+ };
+
+ pci1: pcie at ffe201000 {
+ compatible = "fsl,p3041-pcie", "fsl,qoriq-pcie-v2.2";
+ device_type = "pci";
+ status = "disabled";
+ #size-cells = <2>;
+ #address-cells = <3>;
+ bus-range = <0 0xff>;
+ clock-frequency = <0x1fca055>;
+ fsl,msi = <&msi1>;
+ interrupts = <16 2 1 14>;
+ pcie at 0 {
+ reg = <0 0 0 0 0>;
+ #interrupt-cells = <1>;
+ #size-cells = <2>;
+ #address-cells = <3>;
+ device_type = "pci";
+ interrupts = <16 2 1 14>;
+ interrupt-map-mask = <0xf800 0 0 7>;
+ interrupt-map = <
+ /* IDSEL 0x0 */
+ 0000 0 0 1 &mpic 41 1 0 0
+ 0000 0 0 2 &mpic 5 1 0 0
+ 0000 0 0 3 &mpic 6 1 0 0
+ 0000 0 0 4 &mpic 7 1 0 0
+ >;
+ };
+ };
+
+ pci2: pcie at ffe202000 {
+ compatible = "fsl,p3041-pcie", "fsl,qoriq-pcie-v2.2";
+ device_type = "pci";
+ status = "okay";
+ #size-cells = <2>;
+ #address-cells = <3>;
+ bus-range = <0x0 0xff>;
+ clock-frequency = <0x1fca055>;
+ fsl,msi = <&msi2>;
+ interrupts = <16 2 1 13>;
+ pcie at 0 {
+ reg = <0 0 0 0 0>;
+ #interrupt-cells = <1>;
+ #size-cells = <2>;
+ #address-cells = <3>;
+ device_type = "pci";
+ interrupts = <16 2 1 13>;
+ interrupt-map-mask = <0xf800 0 0 7>;
+ interrupt-map = <
+ /* IDSEL 0x0 */
+ 0000 0 0 1 &mpic 42 1 0 0
+ 0000 0 0 2 &mpic 9 1 0 0
+ 0000 0 0 3 &mpic 10 1 0 0
+ 0000 0 0 4 &mpic 11 1 0 0
+ >;
+ };
+ };
+
+ pci3: pcie at ffe203000 {
+ compatible = "fsl,p3041-pcie", "fsl,qoriq-pcie-v2.2";
+ device_type = "pci";
+ status = "disabled";
+ #size-cells = <2>;
+ #address-cells = <3>;
+ bus-range = <0x0 0xff>;
+ clock-frequency = <0x1fca055>;
+ fsl,msi = <&msi2>;
+ interrupts = <16 2 1 12>;
+ pcie at 0 {
+ reg = <0 0 0 0 0>;
+ #interrupt-cells = <1>;
+ #size-cells = <2>;
+ #address-cells = <3>;
+ device_type = "pci";
+ interrupts = <16 2 1 12>;
+ interrupt-map-mask = <0xf800 0 0 7>;
+ interrupt-map = <
+ /* IDSEL 0x0 */
+ 0000 0 0 1 &mpic 43 1 0 0
+ 0000 0 0 2 &mpic 0 1 0 0
+ 0000 0 0 3 &mpic 4 1 0 0
+ 0000 0 0 4 &mpic 8 1 0 0
+ >;
+ };
+ };
+};
Property changes on: trunk/sys/boot/fdt/dts/powerpc/p3041si.dtsi
___________________________________________________________________
Added: svn:eol-style
## -0,0 +1 ##
+native
\ No newline at end of property
Added: svn:keywords
## -0,0 +1 ##
+MidnightBSD=%H
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+text/plain
\ No newline at end of property
Added: trunk/sys/boot/fdt/dts/powerpc/p5020si.dtsi
===================================================================
--- trunk/sys/boot/fdt/dts/powerpc/p5020si.dtsi (rev 0)
+++ trunk/sys/boot/fdt/dts/powerpc/p5020si.dtsi 2018-06-02 12:34:49 UTC (rev 10205)
@@ -0,0 +1,1390 @@
+/* $MidnightBSD$ */
+/*
+ * P5020 Silicon Device Tree Source
+ *
+ * Copyright 2010-2011 Freescale Semiconductor Inc.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * * Neither the name of Freescale Semiconductor nor the
+ * names of its contributors may be used to endorse or promote products
+ * derived from this software without specific prior written permission.
+ *
+ *
+ * ALTERNATIVELY, this software may be distributed under the terms of the
+ * GNU General Public License ("GPL") as published by the Free Software
+ * Foundation, either version 2 of that License or (at your option) any
+ * later version.
+ *
+ * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+/* $FreeBSD: stable/10/sys/boot/fdt/dts/powerpc/p5020si.dtsi 266364 2014-05-17 21:55:00Z ian $ */
+
+/dts-v1/;
+
+/ {
+ compatible = "fsl,P5020";
+ #address-cells = <2>;
+ #size-cells = <2>;
+ interrupt-parent = <&mpic>;
+
+ aliases {
+ ccsr = &soc;
+ dcsr = &dcsr;
+
+ ethernet0 = &enet0;
+ ethernet1 = &enet1;
+ ethernet2 = &enet2;
+ ethernet3 = &enet3;
+ ethernet4 = &enet4;
+ ethernet5 = &enet5;
+ serial0 = &serial0;
+ serial1 = &serial1;
+ serial2 = &serial2;
+ serial3 = &serial3;
+ pci0 = &pci0;
+ pci1 = &pci1;
+ pci2 = &pci2;
+ pci3 = &pci3;
+ usb0 = &usb0;
+ usb1 = &usb1;
+ dma0 = &dma0;
+ dma1 = &dma1;
+ bman = &bman;
+ qman = &qman;
+ pme = &pme;
+ rman = &rman;
+ sdhc = &sdhc;
+ msi0 = &msi0;
+ msi1 = &msi1;
+ msi2 = &msi2;
+
+ crypto = &crypto;
+ sec_jr0 = &sec_jr0;
+ sec_jr1 = &sec_jr1;
+ sec_jr2 = &sec_jr2;
+ sec_jr3 = &sec_jr3;
+ rtic_a = &rtic_a;
+ rtic_b = &rtic_b;
+ rtic_c = &rtic_c;
+ rtic_d = &rtic_d;
+ sec_mon = &sec_mon;
+
+ raideng = &raideng;
+ raideng_jr0 = &raideng_jr0;
+ raideng_jr1 = &raideng_jr1;
+ raideng_jr2 = &raideng_jr2;
+ raideng_jr3 = &raideng_jr3;
+
+ fman0 = &fman0;
+ fman0_oh0 = &fman0_oh0;
+ fman0_oh1 = &fman0_oh1;
+ fman0_oh2 = &fman0_oh2;
+ fman0_oh3 = &fman0_oh3;
+ fman0_oh4 = &fman0_oh4;
+ fman0_oh5 = &fman0_oh5;
+ fman0_oh6 = &fman0_oh6;
+ fman0_rx0 = &fman0_rx0;
+ fman0_rx1 = &fman0_rx1;
+ fman0_rx2 = &fman0_rx2;
+ fman0_rx3 = &fman0_rx3;
+ fman0_rx4 = &fman0_rx4;
+ fman0_rx5 = &fman0_rx5;
+ };
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cpu0: PowerPC,e5500 at 0 {
+ device_type = "cpu";
+ reg = <0>;
+ bus-frequency = <799999998>;
+ next-level-cache = <&L2_0>;
+ L2_0: l2-cache {
+ next-level-cache = <&cpc>;
+ };
+ };
+ cpu1: PowerPC,e5500 at 1 {
+ device_type = "cpu";
+ reg = <1>;
+ next-level-cache = <&L2_1>;
+ L2_1: l2-cache {
+ next-level-cache = <&cpc>;
+ };
+ };
+ };
+
+ dcsr: dcsr at f00000000 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "fsl,dcsr", "simple-bus";
+
+ dcsr-epu at 0 {
+ compatible = "fsl,dcsr-epu";
+ interrupts = <52 2 0 0
+ 84 2 0 0
+ 85 2 0 0>;
+ interrupt-parent = <&mpic>;
+ reg = <0x0 0x1000>;
+ };
+ dcsr-npc {
+ compatible = "fsl,dcsr-npc";
+ reg = <0x1000 0x1000 0x1000000 0x8000>;
+ };
+ dcsr-nxc at 2000 {
+ compatible = "fsl,dcsr-nxc";
+ reg = <0x2000 0x1000>;
+ };
+ dcsr-corenet {
+ compatible = "fsl,dcsr-corenet";
+ reg = <0x8000 0x1000 0xB0000 0x1000>;
+ };
+ dcsr-dpaa at 9000 {
+ compatible = "fsl,p5020-dcsr-dpaa", "fsl,dcsr-dpaa";
+ reg = <0x9000 0x1000>;
+ };
+ dcsr-ocn at 11000 {
+ compatible = "fsl,p5020-dcsr-ocn", "fsl,dcsr-ocn";
+ reg = <0x11000 0x1000>;
+ };
+ dcsr-ddr at 12000 {
+ compatible = "fsl,dcsr-ddr";
+ dev-handle = <&ddr1>;
+ reg = <0x12000 0x1000>;
+ };
+ dcsr-ddr at 13000 {
+ compatible = "fsl,dcsr-ddr";
+ dev-handle = <&ddr2>;
+ reg = <0x13000 0x1000>;
+ };
+ dcsr-nal at 18000 {
+ compatible = "fsl,p5020-dcsr-nal", "fsl,dcsr-nal";
+ reg = <0x18000 0x1000>;
+ };
+ dcsr-rcpm at 22000 {
+ compatible = "fsl,p5020-dcsr-rcpm", "fsl,dcsr-rcpm";
+ reg = <0x22000 0x1000>;
+ };
+ dcsr-cpu-sb-proxy at 40000 {
+ compatible = "fsl,dcsr-e5500-sb-proxy", "fsl,dcsr-cpu-sb-proxy";
+ cpu-handle = <&cpu0>;
+ reg = <0x40000 0x1000>;
+ };
+ dcsr-cpu-sb-proxy at 41000 {
+ compatible = "fsl,dcsr-e5500-sb-proxy", "fsl,dcsr-cpu-sb-proxy";
+ cpu-handle = <&cpu1>;
+ reg = <0x41000 0x1000>;
+ };
+ };
+
+ bman-portals at ff4000000 {
+ #address-cells = <0x1>;
+ #size-cells = <0x1>;
+ compatible = "bman-portals";
+ ranges = <0x0 0xf 0xfde00000 0x200000>;
+ bman-portal at 0 {
+ cell-index = <0x0>;
+ compatible = "fsl,p5020-bman-portal", "fsl,bman-portal";
+ reg = <0x0 0x4000 0x100000 0x1000>;
+ interrupts = <105 2 0 0>;
+ };
+ bman-portal at 4000 {
+ cell-index = <0x1>;
+ compatible = "fsl,p5020-bman-portal", "fsl,bman-portal";
+ reg = <0x4000 0x4000 0x101000 0x1000>;
+ interrupts = <107 2 0 0>;
+ };
+ bman-portal at 8000 {
+ cell-index = <2>;
+ compatible = "fsl,p5020-bman-portal", "fsl,bman-portal";
+ reg = <0x8000 0x4000 0x102000 0x1000>;
+ interrupts = <109 2 0 0>;
+ };
+ bman-portal at c000 {
+ cell-index = <0x3>;
+ compatible = "fsl,p5020-bman-portal", "fsl,bman-portal";
+ reg = <0xc000 0x4000 0x103000 0x1000>;
+ interrupts = <111 2 0 0>;
+ };
+ bman-portal at 10000 {
+ cell-index = <0x4>;
+ compatible = "fsl,p5020-bman-portal", "fsl,bman-portal";
+ reg = <0x10000 0x4000 0x104000 0x1000>;
+ interrupts = <113 2 0 0>;
+ };
+ bman-portal at 14000 {
+ cell-index = <0x5>;
+ compatible = "fsl,p5020-bman-portal", "fsl,bman-portal";
+ reg = <0x14000 0x4000 0x105000 0x1000>;
+ interrupts = <115 2 0 0>;
+ };
+ bman-portal at 18000 {
+ cell-index = <0x6>;
+ compatible = "fsl,p5020-bman-portal", "fsl,bman-portal";
+ reg = <0x18000 0x4000 0x106000 0x1000>;
+ interrupts = <117 2 0 0>;
+ };
+ bman-portal at 1c000 {
+ cell-index = <0x7>;
+ compatible = "fsl,p5020-bman-portal", "fsl,bman-portal";
+ reg = <0x1c000 0x4000 0x107000 0x1000>;
+ interrupts = <119 2 0 0>;
+ };
+ bman-portal at 20000 {
+ cell-index = <0x8>;
+ compatible = "fsl,p5020-bman-portal", "fsl,bman-portal";
+ reg = <0x20000 0x4000 0x108000 0x1000>;
+ interrupts = <121 2 0 0>;
+ };
+ bman-portal at 24000 {
+ cell-index = <0x9>;
+ compatible = "fsl,p5020-bman-portal", "fsl,bman-portal";
+ reg = <0x24000 0x4000 0x109000 0x1000>;
+ interrupts = <123 2 0 0>;
+ };
+
+ buffer-pool at 0 {
+ compatible = "fsl,p5020-bpool", "fsl,bpool";
+ fsl,bpid = <0>;
+ fsl,bpool-cfg = <0 0x100 0 1 0 0x100>;
+ };
+ };
+
+ qman-portals at ff4200000 {
+ #address-cells = <0x1>;
+ #size-cells = <0x1>;
+ compatible = "qman-portals";
+ ranges = <0x0 0xf 0xfdc00000 0x200000>;
+ qportal0: qman-portal at 0 {
+ cell-index = <0x0>;
+ compatible = "fsl,p5020-qman-portal", "fsl,qman-portal";
+ reg = <0x0 0x4000 0x100000 0x1000>;
+ interrupts = <104 0x2 0 0>;
+ fsl,qman-channel-id = <0x0>;
+ };
+
+ qportal1: qman-portal at 4000 {
+ cell-index = <0x1>;
+ compatible = "fsl,p5020-qman-portal", "fsl,qman-portal";
+ reg = <0x4000 0x4000 0x101000 0x1000>;
+ interrupts = <106 0x2 0 0>;
+ fsl,qman-channel-id = <0x1>;
+ };
+
+ qportal2: qman-portal at 8000 {
+ cell-index = <0x2>;
+ compatible = "fsl,p5020-qman-portal", "fsl,qman-portal";
+ reg = <0x8000 0x4000 0x102000 0x1000>;
+ interrupts = <108 0x2 0 0>;
+ fsl,qman-channel-id = <0x2>;
+ };
+
+ qportal3: qman-portal at c000 {
+ cell-index = <0x3>;
+ compatible = "fsl,p5020-qman-portal", "fsl,qman-portal";
+ reg = <0xc000 0x4000 0x103000 0x1000>;
+ interrupts = <110 0x2 0 0>;
+ fsl,qman-channel-id = <0x3>;
+ };
+
+ qportal4: qman-portal at 10000 {
+ cell-index = <0x4>;
+ compatible = "fsl,p5020-qman-portal", "fsl,qman-portal";
+ reg = <0x10000 0x4000 0x104000 0x1000>;
+ interrupts = <112 0x2 0 0>;
+ fsl,qman-channel-id = <0x4>;
+ };
+
+ qportal5: qman-portal at 14000 {
+ cell-index = <0x5>;
+ compatible = "fsl,p5020-qman-portal", "fsl,qman-portal";
+ reg = <0x14000 0x4000 0x105000 0x1000>;
+ interrupts = <114 0x2 0 0>;
+ fsl,qman-channel-id = <0x5>;
+ };
+
+ qportal6: qman-portal at 18000 {
+ cell-index = <0x6>;
+ compatible = "fsl,p5020-qman-portal", "fsl,qman-portal";
+ reg = <0x18000 0x4000 0x106000 0x1000>;
+ interrupts = <116 0x2 0 0>;
+ fsl,qman-channel-id = <0x6>;
+ };
+
+ qportal7: qman-portal at 1c000 {
+ cell-index = <0x7>;
+ compatible = "fsl,p5020-qman-portal", "fsl,qman-portal";
+ reg = <0x1c000 0x4000 0x107000 0x1000>;
+ interrupts = <118 0x2 0 0>;
+ fsl,qman-channel-id = <0x7>;
+ };
+
+ qportal8: qman-portal at 20000 {
+ cell-index = <0x8>;
+ compatible = "fsl,p5020-qman-portal", "fsl,qman-portal";
+ reg = <0x20000 0x4000 0x108000 0x1000>;
+ interrupts = <120 0x2 0 0>;
+ fsl,qman-channel-id = <0x8>;
+ };
+
+ qportal9: qman-portal at 24000 {
+ cell-index = <0x9>;
+ compatible = "fsl,p5020-qman-portal", "fsl,qman-portal";
+ reg = <0x24000 0x4000 0x109000 0x1000>;
+ interrupts = <122 0x2 0 0>;
+ fsl,qman-channel-id = <0x9>;
+ };
+
+ qpool1: qman-pool at 1 {
+ cell-index = <1>;
+ compatible = "fsl,p5020-qman-pool-channel", "fsl,qman-pool-channel";
+ fsl,qman-channel-id = <0x21>;
+ };
+
+ qpool2: qman-pool at 2 {
+ cell-index = <2>;
+ compatible = "fsl,p5020-qman-pool-channel", "fsl,qman-pool-channel";
+ fsl,qman-channel-id = <0x22>;
+ };
+
+ qpool3: qman-pool at 3 {
+ cell-index = <3>;
+ compatible = "fsl,p5020-qman-pool-channel", "fsl,qman-pool-channel";
+ fsl,qman-channel-id = <0x23>;
+ };
+
+ qpool4: qman-pool at 4 {
+ cell-index = <4>;
+ compatible = "fsl,p5020-qman-pool-channel", "fsl,qman-pool-channel";
+ fsl,qman-channel-id = <0x24>;
+ };
+
+ qpool5: qman-pool at 5 {
+ cell-index = <5>;
+ compatible = "fsl,p5020-qman-pool-channel", "fsl,qman-pool-channel";
+ fsl,qman-channel-id = <0x25>;
+ };
+
+ qpool6: qman-pool at 6 {
+ cell-index = <6>;
+ compatible = "fsl,p5020-qman-pool-channel", "fsl,qman-pool-channel";
+ fsl,qman-channel-id = <0x26>;
+ };
+
+ qpool7: qman-pool at 7 {
+ cell-index = <7>;
+ compatible = "fsl,p5020-qman-pool-channel", "fsl,qman-pool-channel";
+ fsl,qman-channel-id = <0x27>;
+ };
+
+ qpool8: qman-pool at 8 {
+ cell-index = <8>;
+ compatible = "fsl,p5020-qman-pool-channel", "fsl,qman-pool-channel";
+ fsl,qman-channel-id = <0x28>;
+ };
+
+ qpool9: qman-pool at 9 {
+ cell-index = <9>;
+ compatible = "fsl,p5020-qman-pool-channel", "fsl,qman-pool-channel";
+ fsl,qman-channel-id = <0x29>;
+ };
+
+ qpool10: qman-pool at 10 {
+ cell-index = <10>;
+ compatible = "fsl,p5020-qman-pool-channel", "fsl,qman-pool-channel";
+ fsl,qman-channel-id = <0x2a>;
+ };
+
+ qpool11: qman-pool at 11 {
+ cell-index = <11>;
+ compatible = "fsl,p5020-qman-pool-channel", "fsl,qman-pool-channel";
+ fsl,qman-channel-id = <0x2b>;
+ };
+
+ qpool12: qman-pool at 12 {
+ cell-index = <12>;
+ compatible = "fsl,p5020-qman-pool-channel", "fsl,qman-pool-channel";
+ fsl,qman-channel-id = <0x2c>;
+ };
+
+ qpool13: qman-pool at 13 {
+ cell-index = <13>;
+ compatible = "fsl,p5020-qman-pool-channel", "fsl,qman-pool-channel";
+ fsl,qman-channel-id = <0x2d>;
+ };
+
+ qpool14: qman-pool at 14 {
+ cell-index = <14>;
+ compatible = "fsl,p5020-qman-pool-channel", "fsl,qman-pool-channel";
+ fsl,qman-channel-id = <0x2e>;
+ };
+
+ qpool15: qman-pool at 15 {
+ cell-index = <15>;
+ compatible = "fsl,p5020-qman-pool-channel", "fsl,qman-pool-channel";
+ fsl,qman-channel-id = <0x2f>;
+ };
+ };
+
+ soc: soc at ffe000000 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ device_type = "soc";
+ compatible = "simple-bus";
+
+ bus-frequency = <0>; // Filled out by kernel.
+
+ ranges = <0x00000000 0xf 0xfe000000 0x1000000>;
+ reg = <0xf 0xfe000000 0 0x00001000>;
+
+ soc-sram-error {
+ compatible = "fsl,soc-sram-error";
+ interrupts = <16 2 1 29>;
+ };
+
+ corenet-law at 0 {
+ compatible = "fsl,corenet-law";
+ reg = <0x0 0x1000>;
+ fsl,num-laws = <32>;
+ };
+
+ ddr1: memory-controller at 8000 {
+ compatible = "fsl,qoriq-memory-controller-v4.5", "fsl,qoriq-memory-controller";
+ reg = <0x8000 0x1000>;
+ interrupts = <16 2 1 23>;
+ };
+
+ ddr2: memory-controller at 9000 {
+ compatible = "fsl,qoriq-memory-controller-v4.5", "fsl,qoriq-memory-controller";
+ reg = <0x9000 0x1000>;
+ interrupts = <16 2 1 22>;
+ };
+
+ cpc: l3-cache-controller at 10000 {
+ compatible = "fsl,p5020-l3-cache-controller", "fsl,p4080-l3-cache-controller", "cache";
+ reg = <0x10000 0x1000
+ 0x11000 0x1000>;
+ interrupts = <16 2 1 27
+ 16 2 1 26>;
+ };
+
+ corenet-cf at 18000 {
+ compatible = "fsl,corenet-cf";
+ reg = <0x18000 0x1000>;
+ interrupts = <16 2 1 31>;
+ fsl,ccf-num-csdids = <32>;
+ fsl,ccf-num-snoopids = <32>;
+ };
+
+ iommu at 20000 {
+ compatible = "fsl,pamu-v1.0", "fsl,pamu";
+ reg = <0x20000 0x4000>;
+ interrupts = <
+ 24 2 0 0
+ 16 2 1 30>;
+ };
+
+ mpic: pic at 40000 {
+ clock-frequency = <0>;
+ interrupt-controller;
+ #address-cells = <0>;
+ #interrupt-cells = <4>;
+ reg = <0x40000 0x40000>;
+ compatible = "fsl,mpic", "chrp,open-pic";
+ device_type = "open-pic";
+ };
+
+ msi0: msi at 41600 {
+ compatible = "fsl,mpic-msi";
+ reg = <0x41600 0x200>;
+ msi-available-ranges = <0 0x100>;
+ interrupts = <
+ 0xe0 0 0 0
+ 0xe1 0 0 0
+ 0xe2 0 0 0
+ 0xe3 0 0 0
+ 0xe4 0 0 0
+ 0xe5 0 0 0
+ 0xe6 0 0 0
+ 0xe7 0 0 0>;
+ };
+
+ msi1: msi at 41800 {
+ compatible = "fsl,mpic-msi";
+ reg = <0x41800 0x200>;
+ msi-available-ranges = <0 0x100>;
+ interrupts = <
+ 0xe8 0 0 0
+ 0xe9 0 0 0
+ 0xea 0 0 0
+ 0xeb 0 0 0
+ 0xec 0 0 0
+ 0xed 0 0 0
+ 0xee 0 0 0
+ 0xef 0 0 0>;
+ };
+
+ msi2: msi at 41a00 {
+ compatible = "fsl,mpic-msi";
+ reg = <0x41a00 0x200>;
+ msi-available-ranges = <0 0x100>;
+ interrupts = <
+ 0xf0 0 0 0
+ 0xf1 0 0 0
+ 0xf2 0 0 0
+ 0xf3 0 0 0
+ 0xf4 0 0 0
+ 0xf5 0 0 0
+ 0xf6 0 0 0
+ 0xf7 0 0 0>;
+ };
+
+ guts: global-utilities at e0000 {
+ compatible = "fsl,qoriq-device-config-1.0";
+ reg = <0xe0000 0xe00>;
+ fsl,has-rstcr;
+ #sleep-cells = <1>;
+ fsl,liodn-bits = <12>;
+ };
+
+ pins: global-utilities at e0e00 {
+ compatible = "fsl,qoriq-pin-control-1.0";
+ reg = <0xe0e00 0x200>;
+ #sleep-cells = <2>;
+ };
+
+ clockgen: global-utilities at e1000 {
+ compatible = "fsl,p5020-clockgen", "fsl,qoriq-clockgen-1.0";
+ reg = <0xe1000 0x1000>;
+ clock-frequency = <0>;
+ };
+
+ rcpm: global-utilities at e2000 {
+ compatible = "fsl,qoriq-rcpm-1.0";
+ reg = <0xe2000 0x1000>;
+ #sleep-cells = <1>;
+ };
+
+ sfp: sfp at e8000 {
+ compatible = "fsl,p5020-sfp", "fsl,qoriq-sfp-1.0";
+ reg = <0xe8000 0x1000>;
+ };
+
+ serdes: serdes at ea000 {
+ compatible = "fsl,p5020-serdes";
+ reg = <0xea000 0x1000>;
+ };
+
+ dma0: dma at 100300 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "fsl,p5020-dma", "fsl,eloplus-dma";
+ reg = <0x100300 0x4>;
+ ranges = <0x0 0x100100 0x200>;
+ cell-index = <0>;
+ dma-channel at 0 {
+ compatible = "fsl,p5020-dma-channel",
+ "fsl,eloplus-dma-channel";
+ reg = <0x0 0x80>;
+ cell-index = <0>;
+ interrupts = <28 2 0 0>;
+ };
+ dma-channel at 80 {
+ compatible = "fsl,p5020-dma-channel",
+ "fsl,eloplus-dma-channel";
+ reg = <0x80 0x80>;
+ cell-index = <1>;
+ interrupts = <29 2 0 0>;
+ };
+ dma-channel at 100 {
+ compatible = "fsl,p5020-dma-channel",
+ "fsl,eloplus-dma-channel";
+ reg = <0x100 0x80>;
+ cell-index = <2>;
+ interrupts = <30 2 0 0>;
+ };
+ dma-channel at 180 {
+ compatible = "fsl,p5020-dma-channel",
+ "fsl,eloplus-dma-channel";
+ reg = <0x180 0x80>;
+ cell-index = <3>;
+ interrupts = <31 2 0 0>;
+ };
+ };
+
+ dma1: dma at 101300 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "fsl,p5020-dma", "fsl,eloplus-dma";
+ reg = <0x101300 0x4>;
+ ranges = <0x0 0x101100 0x200>;
+ cell-index = <1>;
+ dma-channel at 0 {
+ compatible = "fsl,p5020-dma-channel",
+ "fsl,eloplus-dma-channel";
+ reg = <0x0 0x80>;
+ cell-index = <0>;
+ interrupts = <32 2 0 0>;
+ };
+ dma-channel at 80 {
+ compatible = "fsl,p5020-dma-channel",
+ "fsl,eloplus-dma-channel";
+ reg = <0x80 0x80>;
+ cell-index = <1>;
+ interrupts = <33 2 0 0>;
+ };
+ dma-channel at 100 {
+ compatible = "fsl,p5020-dma-channel",
+ "fsl,eloplus-dma-channel";
+ reg = <0x100 0x80>;
+ cell-index = <2>;
+ interrupts = <34 2 0 0>;
+ };
+ dma-channel at 180 {
+ compatible = "fsl,p5020-dma-channel",
+ "fsl,eloplus-dma-channel";
+ reg = <0x180 0x80>;
+ cell-index = <3>;
+ interrupts = <35 2 0 0>;
+ };
+ };
+
+ spi at 110000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "fsl,p5020-espi", "fsl,mpc8536-espi";
+ reg = <0x110000 0x1000>;
+ interrupts = <53 0x2 0 0>;
+ fsl,espi-num-chipselects = <4>;
+ };
+
+ sdhc: sdhc at 114000 {
+ compatible = "fsl,p5020-esdhc", "fsl,esdhc";
+ reg = <0x114000 0x1000>;
+ interrupts = <48 2 0 0>;
+ sdhci,auto-cmd12;
+ clock-frequency = <0>;
+ };
+
+ i2c at 118000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ cell-index = <0>;
+ compatible = "fsl-i2c";
+ reg = <0x118000 0x100>;
+ interrupts = <38 2 0 0>;
+ dfsrr;
+ };
+
+ i2c at 118100 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ cell-index = <1>;
+ compatible = "fsl-i2c";
+ reg = <0x118100 0x100>;
+ interrupts = <38 2 0 0>;
+ dfsrr;
+ };
+
+ i2c at 119000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ cell-index = <2>;
+ compatible = "fsl-i2c";
+ reg = <0x119000 0x100>;
+ interrupts = <39 2 0 0>;
+ dfsrr;
+ };
+
+ i2c at 119100 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ cell-index = <3>;
+ compatible = "fsl-i2c";
+ reg = <0x119100 0x100>;
+ interrupts = <39 2 0 0>;
+ dfsrr;
+ };
+
+ serial0: serial at 11c500 {
+ cell-index = <0>;
+ device_type = "serial";
+ compatible = "ns16550";
+ reg = <0x11c500 0x100>;
+ clock-frequency = <0>;
+ interrupts = <36 2 0 0>;
+ };
+
+ serial1: serial at 11c600 {
+ cell-index = <1>;
+ device_type = "serial";
+ compatible = "ns16550";
+ reg = <0x11c600 0x100>;
+ clock-frequency = <0>;
+ interrupts = <36 2 0 0>;
+ };
+
+ serial2: serial at 11d500 {
+ cell-index = <2>;
+ device_type = "serial";
+ compatible = "ns16550";
+ reg = <0x11d500 0x100>;
+ clock-frequency = <0>;
+ interrupts = <37 2 0 0>;
+ };
+
+ serial3: serial at 11d600 {
+ cell-index = <3>;
+ device_type = "serial";
+ compatible = "ns16550";
+ reg = <0x11d600 0x100>;
+ clock-frequency = <0>;
+ interrupts = <37 2 0 0>;
+ };
+
+ gpio0: gpio at 130000 {
+ compatible = "fsl,p5020-gpio", "fsl,qoriq-gpio";
+ reg = <0x130000 0x1000>;
+ interrupts = <55 2 0 0>;
+ #gpio-cells = <2>;
+ gpio-controller;
+ };
+
+ rman: rman at 1e0000 {
+ compatible = "fsl,rman";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x1e0000 0x20000>;
+ reg = <0x1e0000 0x20000>;
+ interrupts = <16 2 1 11>; /* err_irq */
+ fsl,qman-channels-id = <0x62 0x63>;
+
+ inbound-block at 0 {
+ compatible = "fsl,rman-inbound-block";
+ reg = <0x0 0x800>;
+ };
+ global-cfg at b00 {
+ compatible = "fsl,rman-global-cfg";
+ reg = <0xb00 0x500>;
+ };
+ inbound-block at 1000 {
+ compatible = "fsl,rman-inbound-block";
+ reg = <0x1000 0x800>;
+ };
+ inbound-block at 2000 {
+ compatible = "fsl,rman-inbound-block";
+ reg = <0x2000 0x800>;
+ };
+ inbound-block at 3000 {
+ compatible = "fsl,rman-inbound-block";
+ reg = <0x3000 0x800>;
+ };
+ };
+
+ usb0: usb at 210000 {
+ compatible = "fsl,p5020-usb2-mph",
+ "fsl,mpc85xx-usb2-mph", "fsl-usb2-mph";
+ reg = <0x210000 0x1000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interrupts = <44 0x2 0 0>;
+ phy_type = "utmi";
+ port0;
+ };
+
+ usb1: usb at 211000 {
+ compatible = "fsl,p5020-usb2-dr",
+ "fsl,mpc85xx-usb2-dr", "fsl-usb2-dr";
+ reg = <0x211000 0x1000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interrupts = <45 0x2 0 0>;
+ dr_mode = "host";
+ phy_type = "utmi";
+ };
+
+ sata at 220000 {
+ compatible = "fsl,p5020-sata", "fsl,pq-sata-v2";
+ reg = <0x220000 0x1000>;
+ interrupts = <68 0x2 0 0>;
+ };
+
+ sata at 221000 {
+ compatible = "fsl,p5020-sata", "fsl,pq-sata-v2";
+ reg = <0x221000 0x1000>;
+ interrupts = <69 0x2 0 0>;
+ };
+
+ crypto: crypto at 300000 {
+ compatible = "fsl,sec-v4.2", "fsl,sec-v4.0";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ reg = <0x300000 0x10000>;
+ ranges = <0 0x300000 0x10000>;
+ interrupts = <92 2 0 0>;
+
+ sec_jr0: jr at 1000 {
+ compatible = "fsl,sec-v4.2-job-ring",
+ "fsl,sec-v4.0-job-ring";
+ reg = <0x1000 0x1000>;
+ interrupts = <88 2 0 0>;
+ };
+
+ sec_jr1: jr at 2000 {
+ compatible = "fsl,sec-v4.2-job-ring",
+ "fsl,sec-v4.0-job-ring";
+ reg = <0x2000 0x1000>;
+ interrupts = <89 2 0 0>;
+ };
+
+ sec_jr2: jr at 3000 {
+ compatible = "fsl,sec-v4.2-job-ring",
+ "fsl,sec-v4.0-job-ring";
+ reg = <0x3000 0x1000>;
+ interrupts = <90 2 0 0>;
+ };
+
+ sec_jr3: jr at 4000 {
+ compatible = "fsl,sec-v4.2-job-ring",
+ "fsl,sec-v4.0-job-ring";
+ reg = <0x4000 0x1000>;
+ interrupts = <91 2 0 0>;
+ };
+
+ rtic at 6000 {
+ compatible = "fsl,sec-v4.2-rtic",
+ "fsl,sec-v4.0-rtic";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ reg = <0x6000 0x100>;
+ ranges = <0x0 0x6100 0xe00>;
+
+ rtic_a: rtic-a at 0 {
+ compatible = "fsl,sec-v4.2-rtic-memory",
+ "fsl,sec-v4.0-rtic-memory";
+ reg = <0x00 0x20 0x100 0x80>;
+ };
+
+ rtic_b: rtic-b at 20 {
+ compatible = "fsl,sec-v4.2-rtic-memory",
+ "fsl,sec-v4.0-rtic-memory";
+ reg = <0x20 0x20 0x200 0x80>;
+ };
+
+ rtic_c: rtic-c at 40 {
+ compatible = "fsl,sec-v4.2-rtic-memory",
+ "fsl,sec-v4.0-rtic-memory";
+ reg = <0x40 0x20 0x300 0x80>;
+ };
+
+ rtic_d: rtic-d at 60 {
+ compatible = "fsl,sec-v4.2-rtic-memory",
+ "fsl,sec-v4.0-rtic-memory";
+ reg = <0x60 0x20 0x500 0x80>;
+ };
+ };
+ };
+
+ sec_mon: sec_mon at 314000 {
+ compatible = "fsl,sec-v4.2-mon", "fsl,sec-v4.0-mon";
+ reg = <0x314000 0x1000>;
+ interrupts = <93 2 0 0>;
+ };
+
+ raideng: raideng at 320000 {
+ compatible = "fsl,raideng-v1.0";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ reg = <0x320000 0x10000>;
+ ranges = <0 0x320000 0x10000>;
+
+ raideng_jq0 at 1000 {
+ compatible = "fsl,raideng-v1.0-job-queue";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ reg = <0x1000 0x1000>;
+ ranges = <0x0 0x1000 0x1000>;
+
+ raideng_jr0: jr at 0 {
+ compatible = "fsl,raideng-v1.0-job-ring", "fsl,raideng-v1.0-hp-ring";
+ reg = <0x0 0x400>;
+ interrupts = <139 2 0 0>;
+ interrupt-parent = <&mpic>;
+ };
+
+ raideng_jr1: jr at 400 {
+ compatible = "fsl,raideng-v1.0-job-ring", "fsl,raideng-v1.0-lp-ring";
+ reg = <0x400 0x400>;
+ interrupts = <140 2 0 0>;
+ interrupt-parent = <&mpic>;
+ };
+ };
+
+ raideng_jq1 at 2000 {
+ compatible = "fsl,raideng-v1.0-job-queue";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ reg = <0x2000 0x1000>;
+ ranges = <0x0 0x2000 0x1000>;
+
+ raideng_jr2: jr at 0 {
+ compatible = "fsl,raideng-v1.0-job-ring", "fsl,raideng-v1.0-hp-ring";
+ reg = <0x0 0x400>;
+ interrupts = <141 2 0 0>;
+ interrupt-parent = <&mpic>;
+ };
+
+ raideng_jr3: jr at 400 {
+ compatible = "fsl,raideng-v1.0-job-ring", "fsl,raideng-v1.0-lp-ring";
+ reg = <0x400 0x400>;
+ interrupts = <142 2 0 0>;
+ interrupt-parent = <&mpic>;
+ };
+ };
+ };
+
+ pme: pme at 316000 {
+ compatible = "fsl,pme";
+ reg = <0x316000 0x10000>;
+ /* fsl,pme-pdsr = <0x0 0x23000000 0x0 0x01000000>; */
+ /* fsl,pme-sre = <0x0 0x24000000 0x0 0x00a00000>; */
+ interrupts = <16 2 1 5>;
+ };
+
+ qman: qman at 318000 {
+ compatible = "fsl,p5020-qman", "fsl,qman";
+ reg = <0x318000 0x1000>;
+ interrupts = <16 2 1 3>;
+ /* Commented out, use default allocation */
+ /* fsl,qman-fqd = <0x0 0x20000000 0x0 0x01000000>; */
+ /* fsl,qman-pfdr = <0x0 0x21000000 0x0 0x01000000>; */
+ };
+
+ bman: bman at 31a000 {
+ compatible = "fsl,p5020-bman", "fsl,bman";
+ reg = <0x31a000 0x1000>;
+ interrupts = <16 2 1 2>;
+ /* Same as fsl,qman-*, use default allocation */
+ /* fsl,bman-fbpr = <0x0 0x22000000 0x0 0x01000000>; */
+ };
+
+ fman0: fman at 400000 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ cell-index = <0>;
+ compatible = "fsl,p5020-fman", "fsl,fman", "simple-bus";
+ ranges = <0 0x400000 0x100000>;
+ reg = <0x400000 0x100000>;
+ clock-frequency = <0>;
+ interrupts = <
+ 96 2 0 0
+ 16 2 1 1>;
+
+ cc at 0 {
+ compatible = "fsl,p5020-fman-cc", "fsl,fman-cc";
+ };
+
+ parser at c7000 {
+ compatible = "fsl,p5020-fman-parser", "fsl,fman-parser";
+ reg = <0xc7000 0x1000>;
+ };
+
+ keygen at c1000 {
+ compatible = "fsl,p5020-fman-keygen", "fsl,fman-keygen";
+ reg = <0xc1000 0x1000>;
+ };
+
+ policer at c0000 {
+ compatible = "fsl,p5020-fman-policer", "fsl,fman-policer";
+ reg = <0xc0000 0x1000>;
+ };
+
+ muram at 0 {
+ compatible = "fsl,p5020-fman-muram", "fsl,fman-muram";
+ reg = <0x0 0x28000>;
+ };
+
+ bmi at 80000 {
+ compatible = "fsl,p5020-fman-bmi", "fsl,fman-bmi";
+ reg = <0x80000 0x400>;
+ };
+
+ qmi at 80400 {
+ compatible = "fsl,p5020-fman-qmi", "fsl,fman-qmi";
+ reg = <0x80400 0x400>;
+ };
+
+ fman0_rx0: port at 88000 {
+ cell-index = <0>;
+ compatible = "fsl,p5020-fman-port-1g-rx", "fsl,fman-port-1g-rx";
+ reg = <0x88000 0x1000>;
+ };
+ fman0_rx1: port at 89000 {
+ cell-index = <1>;
+ compatible = "fsl,p5020-fman-port-1g-rx", "fsl,fman-port-1g-rx";
+ reg = <0x89000 0x1000>;
+ };
+ fman0_rx2: port at 8a000 {
+ cell-index = <2>;
+ compatible = "fsl,p5020-fman-port-1g-rx", "fsl,fman-port-1g-rx";
+ reg = <0x8a000 0x1000>;
+ };
+ fman0_rx3: port at 8b000 {
+ cell-index = <3>;
+ compatible = "fsl,p5020-fman-port-1g-rx", "fsl,fman-port-1g-rx";
+ reg = <0x8b000 0x1000>;
+ };
+ fman0_rx4: port at 8c000 {
+ cell-index = <4>;
+ compatible = "fsl,p5020-fman-port-1g-rx", "fsl,fman-port-1g-rx";
+ reg = <0x8c000 0x1000>;
+ };
+ fman0_rx5: port at 90000 {
+ cell-index = <0>;
+ compatible = "fsl,p5020-fman-port-10g-rx", "fsl,fman-port-10g-rx";
+ reg = <0x90000 0x1000>;
+ };
+
+ fman0_tx5: port at b0000 {
+ cell-index = <0>;
+ compatible = "fsl,p5020-fman-port-10g-tx", "fsl,fman-port-10g-tx";
+ reg = <0xb0000 0x1000>;
+ fsl,qman-channel-id = <0x40>;
+ };
+ fman0_tx0: port at a8000 {
+ cell-index = <0>;
+ compatible = "fsl,p5020-fman-port-1g-tx", "fsl,fman-port-1g-tx";
+ reg = <0xa8000 0x1000>;
+ fsl,qman-channel-id = <0x41>;
+ };
+ fman0_tx1: port at a9000 {
+ cell-index = <1>;
+ compatible = "fsl,p5020-fman-port-1g-tx", "fsl,fman-port-1g-tx";
+ reg = <0xa9000 0x1000>;
+ fsl,qman-channel-id = <0x42>;
+ };
+ fman0_tx2: port at aa000 {
+ cell-index = <2>;
+ compatible = "fsl,p5020-fman-port-1g-tx", "fsl,fman-port-1g-tx";
+ reg = <0xaa000 0x1000>;
+ fsl,qman-channel-id = <0x43>;
+ };
+ fman0_tx3: port at ab000 {
+ cell-index = <3>;
+ compatible = "fsl,p5020-fman-port-1g-tx", "fsl,fman-port-1g-tx";
+ reg = <0xab000 0x1000>;
+ fsl,qman-channel-id = <0x44>;
+ };
+ fman0_tx4: port at ac000 {
+ cell-index = <4>;
+ compatible = "fsl,p5020-fman-port-1g-tx", "fsl,fman-port-1g-tx";
+ reg = <0xac000 0x1000>;
+ fsl,qman-channel-id = <0x45>;
+ };
+
+ fman0_oh0: port at 81000 {
+ cell-index = <0>;
+ compatible = "fsl,p5020-fman-port-oh", "fsl,fman-port-oh";
+ reg = <0x81000 0x1000>;
+ fsl,qman-channel-id = <0x46>;
+ };
+ fman0_oh1: port at 82000 {
+ cell-index = <1>;
+ compatible = "fsl,p5020-fman-port-oh", "fsl,fman-port-oh";
+ reg = <0x82000 0x1000>;
+ fsl,qman-channel-id = <0x47>;
+ };
+ fman0_oh2: port at 83000 {
+ cell-index = <2>;
+ compatible = "fsl,p5020-fman-port-oh", "fsl,fman-port-oh";
+ reg = <0x83000 0x1000>;
+ fsl,qman-channel-id = <0x48>;
+ };
+ fman0_oh3: port at 84000 {
+ cell-index = <3>;
+ compatible = "fsl,p5020-fman-port-oh", "fsl,fman-port-oh";
+ reg = <0x84000 0x1000>;
+ fsl,qman-channel-id = <0x49>;
+ };
+ fman0_oh4: port at 85000 {
+ cell-index = <4>;
+ compatible = "fsl,p5020-fman-port-oh", "fsl,fman-port-oh";
+ reg = <0x85000 0x1000>;
+ fsl,qman-channel-id = <0x4a>;
+ };
+ fman0_oh5: port at 86000 {
+ cell-index = <5>;
+ compatible = "fsl,p5020-fman-port-oh", "fsl,fman-port-oh";
+ reg = <0x86000 0x1000>;
+ fsl,qman-channel-id = <0x4b>;
+ };
+ fman0_oh6: port at 87000 {
+ cell-index = <6>;
+ compatible = "fsl,p5020-fman-port-oh", "fsl,fman-port-oh";
+ reg = <0x87000 0x1000>;
+ };
+
+ enet0: ethernet at e0000 {
+ cell-index = <0>;
+ compatible = "fsl,p5020-fman-1g-mac", "fsl,fman-1g-mac";
+ reg = <0xe0000 0x1000>;
+ fsl,port-handles = <&fman0_rx0 &fman0_tx0>;
+ ptimer-handle = <&ptp_timer0>;
+ };
+
+ mdio0: mdio at e1120 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "fsl,fman-mdio";
+ reg = <0xe1120 0xee0>;
+ interrupts = <100 1 0 0>;
+ };
+
+ enet1: ethernet at e2000 {
+ cell-index = <1>;
+ compatible = "fsl,p5020-fman-1g-mac", "fsl,fman-1g-mac";
+ reg = <0xe2000 0x1000>;
+ fsl,port-handles = <&fman0_rx1 &fman0_tx1>;
+ ptimer-handle = <&ptp_timer0>;
+ };
+
+ mdio at e3120 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "fsl,fman-tbi";
+ reg = <0xe3120 0xee0>;
+ interrupts = <100 1 0 0>;
+ };
+
+ enet2: ethernet at e4000 {
+ cell-index = <2>;
+ compatible = "fsl,p5020-fman-1g-mac", "fsl,fman-1g-mac";
+ reg = <0xe4000 0x1000>;
+ fsl,port-handles = <&fman0_rx2 &fman0_tx2>;
+ ptimer-handle = <&ptp_timer0>;
+ };
+
+ mdio at e5120 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "fsl,fman-tbi";
+ reg = <0xe5120 0xee0>;
+ interrupts = <100 1 0 0>;
+ };
+
+ enet3: ethernet at e6000 {
+ cell-index = <3>;
+ compatible = "fsl,p5020-fman-1g-mac", "fsl,fman-1g-mac";
+ reg = <0xe6000 0x1000>;
+ fsl,port-handles = <&fman0_rx3 &fman0_tx3>;
+ ptimer-handle = <&ptp_timer0>;
+ };
+
+ mdio at e7120 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "fsl,fman-tbi";
+ reg = <0xe7120 0xee0>;
+ interrupts = <100 1 0 0>;
+ };
+
+ enet4: ethernet at e8000 {
+ cell-index = <4>;
+ compatible = "fsl,p5020-fman-1g-mac", "fsl,fman-1g-mac";
+ reg = <0xe8000 0x1000>;
+ fsl,port-handles = <&fman0_rx4 &fman0_tx4>;
+ ptimer-handle = <&ptp_timer0>;
+ };
+
+ mdio at e9120 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "fsl,fman-tbi";
+ reg = <0xe9120 0xee0>;
+ interrupts = <100 1 0 0>;
+ };
+
+ enet5: ethernet at f0000 {
+ cell-index = <0>;
+ compatible = "fsl,p5020-fman-10g-mac", "fsl,fman-10g-mac";
+ reg = <0xf0000 0x1000>;
+ fsl,port-handles = <&fman0_rx5 &fman0_tx5>;
+ };
+
+ mdio at f1000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "fsl,fman-xmdio";
+ reg = <0xf1000 0x1000>;
+ interrupts = <100 1 0 0>;
+ };
+
+ ptp_timer0: rtc at fe000 {
+ compatible = "fsl,fman-rtc";
+ reg = <0xfe000 0x1000>;
+ };
+ };
+ };
+
+ rapidio at ffe0c0000 {
+ compatible = "fsl,srio";
+ interrupts = <16 2 1 11>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ port1 {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ cell-index = <1>;
+ };
+
+ port2 {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ cell-index = <2>;
+ };
+ };
+
+ localbus at ffe124000 {
+ compatible = "fsl,p5020-rev1.0-elbc", "simple-bus", "fsl,elbc";
+ interrupts = <
+ 25 2 0 0
+ 16 2 1 19
+ >;
+ #address-cells = <2>;
+ #size-cells = <1>;
+ };
+
+ pci0: pcie at ffe200000 {
+ compatible = "fsl,p5020-pcie", "fsl,qoriq-pcie-v2.2";
+ device_type = "pci";
+ status = "okay";
+ #size-cells = <2>;
+ #address-cells = <3>;
+ cell-index = <0>;
+ bus-range = <0x0 0xff>;
+ clock-frequency = <0x1fca055>;
+ fsl,msi = <&msi0>;
+ interrupts = <16 2 1 15>;
+
+ pcie at 0 {
+ reg = <0 0 0 0 0>;
+ #interrupt-cells = <1>;
+ #size-cells = <2>;
+ #address-cells = <3>;
+ device_type = "pci";
+ interrupts = <16 2 1 15>;
+ interrupt-map-mask = <0xf800 0 0 7>;
+ interrupt-map = <
+ /* IDSEL 0x0 */
+ 0000 0 0 1 &mpic 40 1 0 0
+ 0000 0 0 2 &mpic 1 1 0 0
+ 0000 0 0 3 &mpic 2 1 0 0
+ 0000 0 0 4 &mpic 3 1 0 0
+ >;
+ };
+ };
+
+ pci1: pcie at ffe201000 {
+ compatible = "fsl,p5020-pcie", "fsl,qoriq-pcie-v2.2";
+ device_type = "pci";
+ status = "disabled";
+ #size-cells = <2>;
+ #address-cells = <3>;
+ cell-index = <1>;
+ bus-range = <0 0xff>;
+ clock-frequency = <0x1fca055>;
+ fsl,msi = <&msi1>;
+ interrupts = <16 2 1 14>;
+ pcie at 0 {
+ reg = <0 0 0 0 0>;
+ #interrupt-cells = <1>;
+ #size-cells = <2>;
+ #address-cells = <3>;
+ device_type = "pci";
+ interrupts = <16 2 1 14>;
+ interrupt-map-mask = <0xf800 0 0 7>;
+ interrupt-map = <
+ /* IDSEL 0x0 */
+ 0000 0 0 1 &mpic 41 1 0 0
+ 0000 0 0 2 &mpic 5 1 0 0
+ 0000 0 0 3 &mpic 6 1 0 0
+ 0000 0 0 4 &mpic 7 1 0 0
+ >;
+ };
+ };
+
+ pci2: pcie at ffe202000 {
+ compatible = "fsl,p5020-pcie", "fsl,qoriq-pcie-v2.2";
+ device_type = "pci";
+ status = "okay";
+ #size-cells = <2>;
+ #address-cells = <3>;
+ cell-index = <2>;
+ bus-range = <0x0 0xff>;
+ clock-frequency = <0x1fca055>;
+ fsl,msi = <&msi2>;
+ interrupts = <16 2 1 13>;
+ pcie at 0 {
+ reg = <0 0 0 0 0>;
+ #interrupt-cells = <1>;
+ #size-cells = <2>;
+ #address-cells = <3>;
+ device_type = "pci";
+ interrupts = <16 2 1 13>;
+ interrupt-map-mask = <0xf800 0 0 7>;
+ interrupt-map = <
+ /* IDSEL 0x0 */
+ 0000 0 0 1 &mpic 42 1 0 0
+ 0000 0 0 2 &mpic 9 1 0 0
+ 0000 0 0 3 &mpic 10 1 0 0
+ 0000 0 0 4 &mpic 11 1 0 0
+ >;
+ };
+ };
+
+ pci3: pcie at ffe203000 {
+ compatible = "fsl,p5020-pcie", "fsl,qoriq-pcie-v2.2";
+ device_type = "pci";
+ status = "disabled";
+ #size-cells = <2>;
+ #address-cells = <3>;
+ cell-index = <3>;
+ bus-range = <0x0 0xff>;
+ clock-frequency = <0x1fca055>;
+ fsl,msi = <&msi2>;
+ interrupts = <16 2 1 12>;
+ pcie at 0 {
+ reg = <0 0 0 0 0>;
+ #interrupt-cells = <1>;
+ #size-cells = <2>;
+ #address-cells = <3>;
+ device_type = "pci";
+ interrupts = <16 2 1 12>;
+ interrupt-map-mask = <0xf800 0 0 7>;
+ interrupt-map = <
+ /* IDSEL 0x0 */
+ 0000 0 0 1 &mpic 43 1 0 0
+ 0000 0 0 2 &mpic 0 1 0 0
+ 0000 0 0 3 &mpic 4 1 0 0
+ 0000 0 0 4 &mpic 8 1 0 0
+ >;
+ };
+ };
+};
Property changes on: trunk/sys/boot/fdt/dts/powerpc/p5020si.dtsi
___________________________________________________________________
Added: svn:eol-style
## -0,0 +1 ##
+native
\ No newline at end of property
Added: svn:keywords
## -0,0 +1 ##
+MidnightBSD=%H
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+text/plain
\ No newline at end of property
Modified: trunk/sys/boot/fdt/dts/sheevaplug.dts
===================================================================
--- trunk/sys/boot/fdt/dts/sheevaplug.dts 2018-06-02 00:06:07 UTC (rev 10204)
+++ trunk/sys/boot/fdt/dts/sheevaplug.dts 2018-06-02 12:34:49 UTC (rev 10205)
@@ -1,3 +1,4 @@
+/* $MidnightBSD$ */
/*
* Copyright (c) 2010 The FreeBSD Foundation
* All rights reserved.
Modified: trunk/sys/boot/fdt/dts/ts7800.dts
===================================================================
--- trunk/sys/boot/fdt/dts/ts7800.dts 2018-06-02 00:06:07 UTC (rev 10204)
+++ trunk/sys/boot/fdt/dts/ts7800.dts 2018-06-02 12:34:49 UTC (rev 10205)
@@ -1,3 +1,4 @@
+/* $MidnightBSD$ */
/*
* Copyright (c) 2010 The FreeBSD Foundation
* All rights reserved.
Modified: trunk/sys/boot/fdt/fdt_loader_cmd.c
===================================================================
--- trunk/sys/boot/fdt/fdt_loader_cmd.c 2018-06-02 00:06:07 UTC (rev 10204)
+++ trunk/sys/boot/fdt/fdt_loader_cmd.c 2018-06-02 12:34:49 UTC (rev 10205)
@@ -29,7 +29,7 @@
*/
#include <sys/cdefs.h>
-__FBSDID("$FreeBSD$");
+__FBSDID("$FreeBSD: stable/10/sys/boot/fdt/fdt_loader_cmd.c 294981 2016-01-28 12:11:42Z smh $");
#include <stand.h>
#include <fdt.h>
@@ -39,10 +39,8 @@
#include <machine/elf.h>
#include "bootstrap.h"
-#include "glue.h"
+#include "fdt_platform.h"
-#define DEBUG
-
#ifdef DEBUG
#define debugf(fmt, args...) do { printf("%s(): ", __func__); \
printf(fmt,##args); } while (0)
@@ -55,17 +53,31 @@
#define FDT_PROP_SEP " = "
-#define STR(number) #number
-#define STRINGIFY(number) STR(number)
+#define COPYOUT(s,d,l) archsw.arch_copyout(s, d, l)
+#define COPYIN(s,d,l) archsw.arch_copyin(s, d, l)
-#define COPYOUT(s,d,l) archsw.arch_copyout((vm_offset_t)(s), d, l)
-
#define FDT_STATIC_DTB_SYMBOL "fdt_static_dtb"
+#define CMD_REQUIRES_BLOB 0x01
+
+/* Location of FDT yet to be loaded. */
+/* This may be in read-only memory, so can't be manipulated directly. */
+static struct fdt_header *fdt_to_load = NULL;
+/* Location of FDT on heap. */
+/* This is the copy we actually manipulate. */
static struct fdt_header *fdtp = NULL;
+/* Size of FDT blob */
+static size_t fdtp_size = 0;
+/* Location of FDT in kernel or module. */
+/* This won't be set if FDT is loaded from disk or memory. */
+/* If it is set, we'll update it when fdt_copy() gets called. */
+static vm_offset_t fdtp_va = 0;
+static int fdt_load_dtb(vm_offset_t va);
+
static int fdt_cmd_nyi(int argc, char *argv[]);
+static int fdt_cmd_addr(int argc, char *argv[]);
static int fdt_cmd_mkprop(int argc, char *argv[]);
static int fdt_cmd_cd(int argc, char *argv[]);
static int fdt_cmd_hdr(int argc, char *argv[]);
@@ -74,25 +86,28 @@
static int fdt_cmd_pwd(int argc, char *argv[]);
static int fdt_cmd_rm(int argc, char *argv[]);
static int fdt_cmd_mknode(int argc, char *argv[]);
+static int fdt_cmd_mres(int argc, char *argv[]);
typedef int cmdf_t(int, char *[]);
struct cmdtab {
- char *name;
- cmdf_t *handler;
+ const char *name;
+ cmdf_t *handler;
+ int flags;
};
static const struct cmdtab commands[] = {
- { "alias", &fdt_cmd_nyi },
- { "cd", &fdt_cmd_cd },
- { "header", &fdt_cmd_hdr },
- { "ls", &fdt_cmd_ls },
- { "mknode", &fdt_cmd_mknode },
- { "mkprop", &fdt_cmd_mkprop },
- { "mres", &fdt_cmd_nyi },
- { "prop", &fdt_cmd_prop },
- { "pwd", &fdt_cmd_pwd },
- { "rm", &fdt_cmd_rm },
+ { "addr", &fdt_cmd_addr, 0 },
+ { "alias", &fdt_cmd_nyi, 0 },
+ { "cd", &fdt_cmd_cd, CMD_REQUIRES_BLOB },
+ { "header", &fdt_cmd_hdr, CMD_REQUIRES_BLOB },
+ { "ls", &fdt_cmd_ls, CMD_REQUIRES_BLOB },
+ { "mknode", &fdt_cmd_mknode, CMD_REQUIRES_BLOB },
+ { "mkprop", &fdt_cmd_mkprop, CMD_REQUIRES_BLOB },
+ { "mres", &fdt_cmd_mres, CMD_REQUIRES_BLOB },
+ { "prop", &fdt_cmd_prop, CMD_REQUIRES_BLOB },
+ { "pwd", &fdt_cmd_pwd, CMD_REQUIRES_BLOB },
+ { "rm", &fdt_cmd_rm, CMD_REQUIRES_BLOB },
{ NULL, NULL }
};
@@ -99,22 +114,23 @@
static char cwd[FDT_CWD_LEN] = "/";
static vm_offset_t
-fdt_find_static_dtb(void)
+fdt_find_static_dtb()
{
+ Elf_Ehdr *ehdr;
+ Elf_Shdr *shdr;
Elf_Sym sym;
- vm_offset_t dyntab, esym;
+ vm_offset_t strtab, symtab, fdt_start;
uint64_t offs;
struct preloaded_file *kfp;
struct file_metadata *md;
- Elf_Sym *symtab;
- Elf_Dyn *dyn;
- char *strtab, *strp;
+ char *strp;
int i, sym_count;
- symtab = NULL;
- dyntab = esym = 0;
- strtab = strp = NULL;
+ debugf("fdt_find_static_dtb()\n");
+ sym_count = symtab = strtab = 0;
+ strp = NULL;
+
offs = __elfN(relocation_offset);
kfp = file_findfile(NULL, NULL);
@@ -121,41 +137,26 @@
if (kfp == NULL)
return (0);
- md = file_findmetadata(kfp, MODINFOMD_ESYM);
+ /* Locate the dynamic symbols and strtab. */
+ md = file_findmetadata(kfp, MODINFOMD_ELFHDR);
if (md == NULL)
return (0);
- COPYOUT(md->md_data, &esym, sizeof(esym));
+ ehdr = (Elf_Ehdr *)md->md_data;
- md = file_findmetadata(kfp, MODINFOMD_DYNAMIC);
+ md = file_findmetadata(kfp, MODINFOMD_SHDR);
if (md == NULL)
return (0);
- COPYOUT(md->md_data, &dyntab, sizeof(dyntab));
+ shdr = (Elf_Shdr *)md->md_data;
- dyntab += offs;
-
- /* Locate STRTAB and DYNTAB */
- for (dyn = (Elf_Dyn *)dyntab; dyn->d_tag != DT_NULL; dyn++) {
- if (dyn->d_tag == DT_STRTAB) {
- strtab = (char *)(uintptr_t)(dyn->d_un.d_ptr + offs);
- continue;
- } else if (dyn->d_tag == DT_SYMTAB) {
- symtab = (Elf_Sym *)(uintptr_t)
- (dyn->d_un.d_ptr + offs);
- continue;
+ for (i = 0; i < ehdr->e_shnum; ++i) {
+ if (shdr[i].sh_type == SHT_DYNSYM && symtab == 0) {
+ symtab = shdr[i].sh_addr + offs;
+ sym_count = shdr[i].sh_size / sizeof(Elf_Sym);
+ } else if (shdr[i].sh_type == SHT_STRTAB && strtab == 0) {
+ strtab = shdr[i].sh_addr + offs;
}
}
- if (symtab == NULL || strtab == NULL) {
- /*
- * No symtab? No strtab? That should not happen here,
- * and should have been verified during __elfN(loadimage).
- * This must be some kind of a bug.
- */
- return (0);
- }
-
- sym_count = (int)((Elf_Sym *)esym - symtab) / sizeof(Elf_Sym);
-
/*
* The most efficent way to find a symbol would be to calculate a
* hash, find proper bucket and chain, and thus find a symbol.
@@ -166,47 +167,32 @@
* we are eliminating symbols type of which is not STT_NOTYPE, or(and)
* those which binding attribute is not STB_GLOBAL.
*/
- for (i = 0; i < sym_count; i++) {
- COPYOUT(symtab + i, &sym, sizeof(sym));
+ fdt_start = 0;
+ while (sym_count > 0 && fdt_start == 0) {
+ COPYOUT(symtab, &sym, sizeof(sym));
+ symtab += sizeof(sym);
+ --sym_count;
if (ELF_ST_BIND(sym.st_info) != STB_GLOBAL ||
ELF_ST_TYPE(sym.st_info) != STT_NOTYPE)
continue;
-
- strp = strdupout((vm_offset_t)(strtab + sym.st_name));
- if (strcmp(strp, FDT_STATIC_DTB_SYMBOL) == 0) {
- /* Found a match ! */
- free(strp);
- return ((vm_offset_t)(sym.st_value + offs));
- }
+ strp = strdupout(strtab + sym.st_name);
+ if (strcmp(strp, FDT_STATIC_DTB_SYMBOL) == 0)
+ fdt_start = (vm_offset_t)sym.st_value + offs;
free(strp);
}
- return (0);
+ return (fdt_start);
}
static int
-fdt_setup_fdtp()
+fdt_load_dtb(vm_offset_t va)
{
- struct preloaded_file *bfp;
+ struct fdt_header header;
int err;
- /*
- * Find the device tree blob.
- */
- bfp = file_findfile(NULL, "dtb");
- if (bfp == NULL) {
- if ((fdtp = (struct fdt_header *)fdt_find_static_dtb()) == 0) {
- command_errmsg = "no device tree blob found!";
- return (CMD_ERROR);
- }
- } else {
- /* Dynamic blob has precedence over static. */
- fdtp = (struct fdt_header *)bfp->f_addr;
- }
+ debugf("fdt_load_dtb(0x%08jx)\n", (uintmax_t)va);
- /*
- * Validate the blob.
- */
- err = fdt_check_header(fdtp);
+ COPYOUT(va, &header, sizeof(header));
+ err = fdt_check_header(&header);
if (err < 0) {
if (err == -FDT_ERR_BADVERSION)
sprintf(command_errbuf,
@@ -216,11 +202,122 @@
else
sprintf(command_errbuf, "error validating blob: %s",
fdt_strerror(err));
- return (CMD_ERROR);
+ return (1);
}
- return (CMD_OK);
+
+ /*
+ * Release previous blob
+ */
+ if (fdtp)
+ free(fdtp);
+
+ fdtp_size = fdt_totalsize(&header);
+ fdtp = malloc(fdtp_size);
+
+ if (fdtp == NULL) {
+ command_errmsg = "can't allocate memory for device tree copy";
+ return (1);
+ }
+
+ fdtp_va = va;
+ COPYOUT(va, fdtp, fdtp_size);
+ debugf("DTB blob found at 0x%jx, size: 0x%jx\n", (uintmax_t)va, (uintmax_t)fdtp_size);
+
+ return (0);
}
+int
+fdt_load_dtb_addr(struct fdt_header *header)
+{
+ int err;
+
+ debugf("fdt_load_dtb_addr(0x%p)\n", header);
+
+ fdtp_size = fdt_totalsize(header);
+ err = fdt_check_header(header);
+ if (err < 0) {
+ sprintf(command_errbuf, "error validating blob: %s",
+ fdt_strerror(err));
+ return (err);
+ }
+ free(fdtp);
+ if ((fdtp = malloc(fdtp_size)) == NULL) {
+ command_errmsg = "can't allocate memory for device tree copy";
+ return (1);
+ }
+
+ fdtp_va = 0; // Don't write this back into module or kernel.
+ bcopy(header, fdtp, fdtp_size);
+ return (0);
+}
+
+int
+fdt_load_dtb_file(const char * filename)
+{
+ struct preloaded_file *bfp, *oldbfp;
+ int err;
+
+ debugf("fdt_load_dtb_file(%s)\n", filename);
+
+ oldbfp = file_findfile(NULL, "dtb");
+
+ /* Attempt to load and validate a new dtb from a file. */
+ if ((bfp = file_loadraw(filename, "dtb", 1)) == NULL) {
+ sprintf(command_errbuf, "failed to load file '%s'", filename);
+ return (1);
+ }
+ if ((err = fdt_load_dtb(bfp->f_addr)) != 0) {
+ file_discard(bfp);
+ return (err);
+ }
+
+ /* A new dtb was validated, discard any previous file. */
+ if (oldbfp)
+ file_discard(oldbfp);
+ return (0);
+}
+
+int
+fdt_setup_fdtp()
+{
+ struct preloaded_file *bfp;
+ vm_offset_t va;
+
+ debugf("fdt_setup_fdtp()\n");
+
+ /* If we already loaded a file, use it. */
+ if ((bfp = file_findfile(NULL, "dtb")) != NULL) {
+ if (fdt_load_dtb(bfp->f_addr) == 0) {
+ printf("Using DTB from loaded file '%s'.\n",
+ bfp->f_name);
+ return (0);
+ }
+ }
+
+ /* If we were given the address of a valid blob in memory, use it. */
+ if (fdt_to_load != NULL) {
+ if (fdt_load_dtb_addr(fdt_to_load) == 0) {
+ printf("Using DTB from memory address 0x%08X.\n",
+ (unsigned int)fdt_to_load);
+ return (0);
+ }
+ }
+
+ if (fdt_platform_load_dtb() == 0)
+ return (0);
+
+ /* If there is a dtb compiled into the kernel, use it. */
+ if ((va = fdt_find_static_dtb()) != 0) {
+ if (fdt_load_dtb(va) == 0) {
+ printf("Using DTB compiled into kernel.\n");
+ return (0);
+ }
+ }
+
+ command_errmsg = "No device tree blob found!\n";
+ return (1);
+}
+
#define fdt_strtovect(str, cellbuf, lim, cellsize) _fdt_strtovect((str), \
(cellbuf), (lim), (cellsize), 0);
@@ -229,11 +326,11 @@
(cellbuf), (lim), (cellsize), 16);
static int
-_fdt_strtovect(char *str, void *cellbuf, int lim, unsigned char cellsize,
+_fdt_strtovect(const char *str, void *cellbuf, int lim, unsigned char cellsize,
uint8_t base)
{
- char *buf = str;
- char *end = str + strlen(str) - 2;
+ const char *buf = str;
+ const char *end = str + strlen(str) - 2;
uint32_t *u32buf = NULL;
uint8_t *u8buf = NULL;
int cnt = 0;
@@ -271,47 +368,20 @@
return (cnt);
}
-#define TMP_MAX_ETH 8
-
void
-fixup_ethernet(const char *env, char *ethstr, int *eth_no, int len)
+fdt_fixup_ethernet(const char *str, char *ethstr, int len)
{
- char *end, *str;
uint8_t tmp_addr[6];
- int i, n;
- /* Extract interface number */
- i = strtol(env + 3, &end, 10);
- if (end == (env + 3))
- /* 'ethaddr' means interface 0 address */
- n = 0;
- else
- n = i;
-
- if (n > TMP_MAX_ETH)
- return;
-
- str = ub_env_get(env);
-
/* Convert macaddr string into a vector of uints */
fdt_strtovectx(str, &tmp_addr, 6, sizeof(uint8_t));
- if (n != 0) {
- i = strlen(env) - 7;
- strncpy(ethstr + 8, env + 3, i);
- }
/* Set actual property to a value from vect */
fdt_setprop(fdtp, fdt_path_offset(fdtp, ethstr),
"local-mac-address", &tmp_addr, 6 * sizeof(uint8_t));
-
- /* Clear ethernet..XXXX.. string */
- bzero(ethstr + 8, len - 8);
-
- if (n + 1 > *eth_no)
- *eth_no = n + 1;
}
void
-fixup_cpubusfreqs(unsigned long cpufreq, unsigned long busfreq)
+fdt_fixup_cpubusfreqs(unsigned long cpufreq, unsigned long busfreq)
{
int lo, o = 0, o2, maxo = 0, depth;
const uint32_t zero = 0;
@@ -318,6 +388,8 @@
/* We want to modify every subnode of /cpus */
o = fdt_path_offset(fdtp, "/cpus");
+ if (o < 0)
+ return;
/* maxo should contain offset of node next to /cpus */
depth = 0;
@@ -356,7 +428,7 @@
}
}
-int
+static int
fdt_reg_valid(uint32_t *reg, int len, int addr_cells, int size_cells)
{
int cells_in_tuple, i, tuples, tuple_size;
@@ -389,13 +461,16 @@
}
void
-fixup_memory(struct sys_info *si)
+fdt_fixup_memory(struct fdt_mem_region *region, size_t num)
{
- struct mem_region *curmr;
+ struct fdt_mem_region *curmr;
uint32_t addr_cells, size_cells;
- uint32_t *addr_cellsp, *reg, *size_cellsp;
- int err, i, len, memory, realmrno, root;
+ uint32_t *addr_cellsp, *size_cellsp;
+ int err, i, len, memory, root;
+ size_t realmrno;
uint8_t *buf, *sb;
+ uint64_t rstart, rsize;
+ int reserved;
root = fdt_path_offset(fdtp, "/");
if (root < 0) {
@@ -435,10 +510,55 @@
addr_cells = fdt32_to_cpu(*addr_cellsp);
size_cells = fdt32_to_cpu(*size_cellsp);
+ /*
+ * Convert memreserve data to memreserve property
+ * Check if property already exists
+ */
+ reserved = fdt_num_mem_rsv(fdtp);
+ if (reserved &&
+ (fdt_getprop(fdtp, root, "memreserve", NULL) == NULL)) {
+ len = (addr_cells + size_cells) * reserved * sizeof(uint32_t);
+ sb = buf = (uint8_t *)malloc(len);
+ if (!buf)
+ return;
+
+ bzero(buf, len);
+
+ for (i = 0; i < reserved; i++) {
+ if (fdt_get_mem_rsv(fdtp, i, &rstart, &rsize))
+ break;
+ if (rsize) {
+ /* Ensure endianess, and put cells into a buffer */
+ if (addr_cells == 2)
+ *(uint64_t *)buf =
+ cpu_to_fdt64(rstart);
+ else
+ *(uint32_t *)buf =
+ cpu_to_fdt32(rstart);
+
+ buf += sizeof(uint32_t) * addr_cells;
+ if (size_cells == 2)
+ *(uint64_t *)buf =
+ cpu_to_fdt64(rsize);
+ else
+ *(uint32_t *)buf =
+ cpu_to_fdt32(rsize);
+
+ buf += sizeof(uint32_t) * size_cells;
+ }
+ }
+
+ /* Set property */
+ if ((err = fdt_setprop(fdtp, root, "memreserve", sb, len)) < 0)
+ printf("Could not fixup 'memreserve' property.\n");
+
+ free(sb);
+ }
+
/* Count valid memory regions entries in sysinfo. */
- realmrno = si->mr_no;
- for (i = 0; i < si->mr_no; i++)
- if (si->mr[i].start == 0 && si->mr[i].size == 0)
+ realmrno = num;
+ for (i = 0; i < num; i++)
+ if (region[i].start == 0 && region[i].size == 0)
realmrno--;
if (realmrno == 0) {
@@ -447,17 +567,6 @@
return;
}
- if ((reg = (uint32_t *)fdt_getprop(fdtp, memory, "reg",
- &len)) != NULL) {
-
- if (fdt_reg_valid(reg, len, addr_cells, size_cells) == 0)
- /*
- * Do not apply fixup if existing 'reg' property
- * seems to be valid.
- */
- return;
- }
-
len = (addr_cells + size_cells) * realmrno * sizeof(uint32_t);
sb = buf = (uint8_t *)malloc(len);
if (!buf)
@@ -465,8 +574,8 @@
bzero(buf, len);
- for (i = 0; i < si->mr_no; i++) {
- curmr = &si->mr[i];
+ for (i = 0; i < num; i++) {
+ curmr = ®ion[i];
if (curmr->size != 0) {
/* Ensure endianess, and put cells into a buffer */
if (addr_cells == 2)
@@ -491,12 +600,13 @@
/* Set property */
if ((err = fdt_setprop(fdtp, memory, "reg", sb, len)) < 0)
sprintf(command_errbuf, "Could not fixup '/memory' node.\n");
+
+ free(sb);
}
void
-fixup_stdout(const char *env)
+fdt_fixup_stdout(const char *str)
{
- const char *str;
char *ptr;
int serialno;
int len, no, sero;
@@ -503,7 +613,6 @@
const struct fdt_property *prop;
char *tmp[10];
- str = ub_env_get(env);
ptr = (char *)str + strlen(str) - 1;
while (ptr > str && isdigit(*(str - 1)))
str--;
@@ -546,25 +655,18 @@
/*
* Locate the blob, fix it up and return its location.
*/
-void *
+static int
fdt_fixup(void)
{
- const char *env;
- char *ethstr;
- int chosen, err, eth_no, len;
- struct sys_info *si;
+ int chosen, len;
- env = NULL;
- eth_no = 0;
- ethstr = NULL;
len = 0;
- err = fdt_setup_fdtp();
- if (err) {
- sprintf(command_errbuf, "No valid device tree blob found!");
- return (NULL);
- }
+ debugf("fdt_fixup()\n");
+ if (fdtp == NULL && fdt_setup_fdtp() != 0)
+ return (0);
+
/* Create /chosen node (if not exists) */
if ((chosen = fdt_subnode_offset(fdtp, 0, "chosen")) ==
-FDT_ERR_NOTFOUND)
@@ -572,58 +674,49 @@
/* Value assigned to fixup-applied does not matter. */
if (fdt_getprop(fdtp, chosen, "fixup-applied", NULL))
- goto success;
+ return (1);
- /* Acquire sys_info */
- si = ub_get_sys_info();
+ fdt_platform_fixups();
- while ((env = ub_env_enum(env)) != NULL) {
- if (strncmp(env, "eth", 3) == 0 &&
- strncmp(env + (strlen(env) - 4), "addr", 4) == 0) {
- /*
- * Handle Ethernet addrs: parse uboot env eth%daddr
- */
+ fdt_setprop(fdtp, chosen, "fixup-applied", NULL, 0);
+ return (1);
+}
- if (!eth_no) {
- /*
- * Check how many chars we will need to store
- * maximal eth iface number.
- */
- len = strlen(STRINGIFY(TMP_MAX_ETH)) +
- strlen("ethernet");
+/*
+ * Copy DTB blob to specified location and return size
+ */
+int
+fdt_copy(vm_offset_t va)
+{
+ int err;
+ debugf("fdt_copy va 0x%08x\n", va);
+ if (fdtp == NULL) {
+ err = fdt_setup_fdtp();
+ if (err) {
+ printf("No valid device tree blob found!\n");
+ return (0);
+ }
+ }
- /*
- * Reserve mem for string "ethernet" and len
- * chars for iface no.
- */
- ethstr = (char *)malloc(len * sizeof(char));
- bzero(ethstr, len * sizeof(char));
- strcpy(ethstr, "ethernet0");
- }
+ if (fdt_fixup() == 0)
+ return (0);
- /* Modify blob */
- fixup_ethernet(env, ethstr, ð_no, len);
-
- } else if (strcmp(env, "consoledev") == 0)
- fixup_stdout(env);
+ if (fdtp_va != 0) {
+ /* Overwrite the FDT with the fixed version. */
+ /* XXX Is this really appropriate? */
+ COPYIN(fdtp, fdtp_va, fdtp_size);
}
+ COPYIN(fdtp, va, fdtp_size);
+ return (fdtp_size);
+}
- /* Modify cpu(s) and bus clock frequenties in /cpus node [Hz] */
- fixup_cpubusfreqs(si->clk_cpu, si->clk_bus);
- /* Fixup memory regions */
- fixup_memory(si);
- fdt_setprop(fdtp, chosen, "fixup-applied", NULL, 0);
-
-success:
- return (fdtp);
-}
-
int
command_fdt_internal(int argc, char *argv[])
{
cmdf_t *cmdh;
+ int flags;
char *cmd;
int i, err;
@@ -633,12 +726,6 @@
}
/*
- * Check if uboot env vars were parsed already. If not, do it now.
- */
- if (fdt_fixup() == NULL)
- return (CMD_ERROR);
-
- /*
* Validate fdt <command>.
*/
cmd = strdup(argv[1]);
@@ -648,6 +735,7 @@
if (strcmp(cmd, commands[i].name) == 0) {
/* found it */
cmdh = commands[i].handler;
+ flags = commands[i].flags;
break;
}
i++;
@@ -657,6 +745,14 @@
return (CMD_ERROR);
}
+ if (flags & CMD_REQUIRES_BLOB) {
+ /*
+ * Check if uboot env vars were parsed already. If not, do it now.
+ */
+ if (fdt_fixup() == 0)
+ return (CMD_ERROR);
+ }
+
/*
* Call command handler.
*/
@@ -666,6 +762,37 @@
}
static int
+fdt_cmd_addr(int argc, char *argv[])
+{
+ struct preloaded_file *fp;
+ struct fdt_header *hdr;
+ const char *addr;
+ char *cp;
+
+ fdt_to_load = NULL;
+
+ if (argc > 2)
+ addr = argv[2];
+ else {
+ sprintf(command_errbuf, "no address specified");
+ return (CMD_ERROR);
+ }
+
+ hdr = (struct fdt_header *)strtoul(addr, &cp, 16);
+ if (cp == addr) {
+ sprintf(command_errbuf, "Invalid address: %s", addr);
+ return (CMD_ERROR);
+ }
+
+ while ((fp = file_findfile(NULL, "dtb")) != NULL) {
+ file_discard(fp);
+ }
+
+ fdt_to_load = hdr;
+ return (CMD_OK);
+}
+
+static int
fdt_cmd_cd(int argc, char *argv[])
{
char *path;
@@ -1098,7 +1225,7 @@
fdt_modprop(int nodeoff, char *propname, void *value, char mode)
{
uint32_t cells[100];
- char *buf;
+ const char *buf;
int len, rv;
const struct fdt_property *p;
@@ -1116,7 +1243,7 @@
}
len = strlen(value);
rv = 0;
- buf = (char *)value;
+ buf = value;
switch (*buf) {
case '&':
@@ -1173,13 +1300,12 @@
sz += argc - start;
buf = (char *)malloc(sizeof(char) * sz);
- bzero(buf, sizeof(char) * sz);
-
if (buf == NULL) {
sprintf(command_errbuf, "could not allocate space "
"for string");
return (1);
}
+ bzero(buf, sizeof(char) * sz);
idx = 0;
for (i = start, idx = 0; i < argc; i++) {
@@ -1419,6 +1545,30 @@
}
static int
+fdt_cmd_mres(int argc, char *argv[])
+{
+ uint64_t start, size;
+ int i, total;
+ char line[80];
+
+ pager_open();
+ total = fdt_num_mem_rsv(fdtp);
+ if (total > 0) {
+ pager_output("Reserved memory regions:\n");
+ for (i = 0; i < total; i++) {
+ fdt_get_mem_rsv(fdtp, i, &start, &size);
+ sprintf(line, "reg#%d: (start: 0x%jx, size: 0x%jx)\n",
+ i, start, size);
+ pager_output(line);
+ }
+ } else
+ pager_output("No reserved memory regions\n");
+ pager_close();
+
+ return (CMD_OK);
+}
+
+static int
fdt_cmd_nyi(int argc, char *argv[])
{
Added: trunk/sys/boot/fdt/fdt_platform.h
===================================================================
--- trunk/sys/boot/fdt/fdt_platform.h (rev 0)
+++ trunk/sys/boot/fdt/fdt_platform.h 2018-06-02 12:34:49 UTC (rev 10205)
@@ -0,0 +1,55 @@
+/* $MidnightBSD$ */
+/*-
+ * Copyright (c) 2014 Andrew Turner <andrew at FreeBSD.org>
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ * $FreeBSD: stable/10/sys/boot/fdt/fdt_platform.h 275763 2014-12-14 15:33:45Z andrew $
+ */
+
+#ifndef FDT_PLATFORM_H
+#define FDT_PLATFORM_H
+
+struct fdt_header;
+
+struct fdt_mem_region {
+ unsigned long start;
+ unsigned long size;
+};
+
+#define TMP_MAX_ETH 8
+
+int fdt_copy(vm_offset_t);
+void fdt_fixup_cpubusfreqs(unsigned long, unsigned long);
+void fdt_fixup_ethernet(const char *, char *, int);
+void fdt_fixup_memory(struct fdt_mem_region *, size_t);
+void fdt_fixup_stdout(const char *);
+int fdt_load_dtb_addr(struct fdt_header *);
+int fdt_load_dtb_file(const char *);
+int fdt_setup_fdtp(void);
+
+/* The platform library needs to implement these functions */
+int fdt_platform_load_dtb(void);
+void fdt_platform_fixups(void);
+
+#endif /* FDT_PLATFORM_H */
Property changes on: trunk/sys/boot/fdt/fdt_platform.h
___________________________________________________________________
Added: svn:eol-style
## -0,0 +1 ##
+native
\ No newline at end of property
Added: svn:keywords
## -0,0 +1 ##
+MidnightBSD=%H
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+text/plain
\ No newline at end of property
Added: trunk/sys/boot/fdt/help.fdt
===================================================================
--- trunk/sys/boot/fdt/help.fdt (rev 0)
+++ trunk/sys/boot/fdt/help.fdt 2018-06-02 12:34:49 UTC (rev 10205)
@@ -0,0 +1,93 @@
+$MidnightBSD$
+###############################################################################
+# Tfdt Dfdt manipulation commands
+
+ fdt <subcommand> <arguments>
+
+ Facilities for loading and manipulating device tree data.
+
+###############################################################################
+# Tfdt Saddr Dload fdt from an address in memory
+
+ fdt addr <address>
+
+ Copies compiled device tree from a particular location
+ in memory.
+
+###############################################################################
+# Tfdt Salias DXXX
+
+ fdt alias <address>
+
+ Not Yet Implemented
+
+###############################################################################
+# Tfdt Scd DSelect a particular node for future commands
+
+ fdt cd <path>
+
+ Changes the current node to the node specified by the path.
+ Path elements are separated by '/'; a leading '/' represents
+ the root node.
+
+###############################################################################
+# Tfdt Sheader DDump the header of the compiled device tree
+
+ fdt header
+
+ Dumps DTB size, format and other key values.
+
+###############################################################################
+# Tfdt Sls DList subnodes of the current node
+
+ fdt ls <path>
+
+ Lists the nodes under the specified path.
+ If no path is specified, lists nodes under the current path.
+
+###############################################################################
+# Tfdt Smknode DCreate a new node in the device tree
+
+ fdt mknode <name>
+
+ Creates a new node with the specified name.
+
+###############################################################################
+# Tfdt Smkprop DAdd a new property to the current node
+
+ fdt mkprop <name> <value> ...
+
+ Creates a new property with the specified name and values.
+ Multiple values can be specified and will be concatenated.
+
+###############################################################################
+# Tfdt Smres DXXX
+
+ fdt mres
+
+ Dumps the list of reserved memory regions.
+
+###############################################################################
+# Tfdt Sprop DDump value of a particular property
+
+ fdt prop <name> <value> ...
+
+ If value is specified, set the given property to the indicated value.
+ Otherwise, print the value of the property.
+
+###############################################################################
+# Tfdt Spwd DPrint path to current node in device tree
+
+ fdt pwd
+
+ Print path to the current node in the device tree.
+ The current node can be changed with "fdt cd".
+
+###############################################################################
+# Tfdt Srm DRemove node or property from device tree
+
+ fdt rm <name>
+
+ The named node or property will be removed from the device tree.
+
+###############################################################################
Property changes on: trunk/sys/boot/fdt/help.fdt
___________________________________________________________________
Added: svn:keywords
## -0,0 +1 ##
+MidnightBSD=%H
\ No newline at end of property
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