[Midnightbsd-cvs] src [10415] trunk/sys/amd64: restore ryzen workaround from rev 9534

[laffer1 at midnightbsd.org]

Revision: 10415
          http://svnweb.midnightbsd.org/src/?rev=10415
Author:   laffer1
Date:     2018-06-05 17:39:13 -0400 (Tue, 05 Jun 2018)
Log Message:
-----------
restore ryzen workaround from rev 9534

Revision Links:
--------------
    http://svnweb.midnightbsd.org/src/?rev=9534

Modified Paths:
--------------
    trunk/sys/amd64/amd64/elf_machdep.c
    trunk/sys/amd64/amd64/initcpu.c
    trunk/sys/amd64/include/md_var.h

Modified: trunk/sys/amd64/amd64/elf_machdep.c
===================================================================
--- trunk/sys/amd64/amd64/elf_machdep.c	2018-06-05 21:24:33 UTC (rev 10414)
+++ trunk/sys/amd64/amd64/elf_machdep.c	2018-06-05 21:39:13 UTC (rev 10415)
@@ -88,6 +88,25 @@
 };
 INIT_SYSENTVEC(elf64_sysvec, &elf64_freebsd_sysvec);
 
+void
+amd64_lower_shared_page(struct sysentvec *sv)
+{
+	if (hw_lower_amd64_sharedpage != 0) {
+		sv->sv_maxuser -= PAGE_SIZE;
+		sv->sv_shared_page_base -= PAGE_SIZE;
+		sv->sv_usrstack -= PAGE_SIZE;
+		sv->sv_psstrings -= PAGE_SIZE;
+	}
+}
+
+/*
+ * Do this fixup before INIT_SYSENTVEC (SI_ORDER_ANY) because the latter
+ * uses the value of sv_shared_page_base.
+ */
+SYSINIT(elf64_sysvec_fixup, SI_SUB_EXEC, SI_ORDER_FIRST,
+	(sysinit_cfunc_t) amd64_lower_shared_page,
+	&elf64_freebsd_sysvec);
+
 static Elf64_Brandinfo freebsd_brand_info = {
 	.brand		= ELFOSABI_FREEBSD,
 	.machine	= EM_X86_64,

Modified: trunk/sys/amd64/amd64/initcpu.c
===================================================================
--- trunk/sys/amd64/amd64/initcpu.c	2018-06-05 21:24:33 UTC (rev 10414)
+++ trunk/sys/amd64/amd64/initcpu.c	2018-06-05 21:39:13 UTC (rev 10415)
@@ -49,6 +49,11 @@
 static int	hw_instruction_sse;
 SYSCTL_INT(_hw, OID_AUTO, instruction_sse, CTLFLAG_RD,
     &hw_instruction_sse, 0, "SIMD/MMX2 instructions available in CPU");
+static int	lower_sharedpage_init;
+int		hw_lower_amd64_sharedpage;
+SYSCTL_INT(_hw, OID_AUTO, lower_amd64_sharedpage, CTLFLAG_RDTUN,
+    &hw_lower_amd64_sharedpage, 0,
+   "Lower sharedpage to work around Ryzen issue with executing code near the top of user memory");
 /*
  * -1: automatic (default)
  *  0: keep enable CLFLUSH
@@ -234,6 +239,28 @@
 		init_via();
 		break;
 	}
+
+	/*
+	 * Work around a problem on Ryzen that is triggered by executing
+	 * code near the top of user memory, in our case the signal
+	 * trampoline code in the shared page on amd64.
+	 *
+	 * This function is executed once for the BSP before tunables take
+	 * effect so the value determined here can be overridden by the
+	 * tunable.  This function is then executed again for each AP and
+	 * also on resume.  Set a flag the first time so that value set by
+	 * the tunable is not overwritten.
+	 *
+	 * The stepping and/or microcode versions should be checked after
+	 * this issue is fixed by AMD so that we don't use this mode if not
+	 * needed.
+	 */
+	if (lower_sharedpage_init == 0) {
+		lower_sharedpage_init = 1;
+		if (CPUID_TO_FAMILY(cpu_id) == 0x17) {
+			hw_lower_amd64_sharedpage = 1;
+		}
+	}
 }
 
 void

Modified: trunk/sys/amd64/include/md_var.h
===================================================================
--- trunk/sys/amd64/include/md_var.h	2018-06-05 21:24:33 UTC (rev 10414)
+++ trunk/sys/amd64/include/md_var.h	2018-06-05 21:39:13 UTC (rev 10415)
@@ -71,6 +71,7 @@
 extern	char	sigcode[];
 extern	int	szsigcode;
 extern	uint64_t *vm_page_dump;
+extern	int	hw_lower_amd64_sharedpage;
 extern	int	vm_page_dump_size;
 extern	int	workaround_erratum383;
 extern	int	_udatasel;
@@ -84,6 +85,7 @@
 typedef void alias_for_inthand_t(u_int cs, u_int ef, u_int esp, u_int ss);
 struct	pcb;
 struct	savefpu;
+struct	sysentvec;
 struct	thread;
 struct	reg;
 struct	fpreg;
@@ -141,5 +143,6 @@
 struct savefpu *get_pcb_user_save_pcb(struct pcb *pcb);
 struct pcb *get_pcb_td(struct thread *td);
 void	amd64_db_resume_dbreg(void);
+void	amd64_lower_shared_page(struct sysentvec *);
 
 #endif /* !_MACHINE_MD_VAR_H_ */