[Midnightbsd-cvs] src [10653] trunk/lib: sync with freebsd
laffer1 at midnightbsd.org
laffer1 at midnightbsd.org
Sat Jun 9 15:23:11 EDT 2018
Revision: 10653
http://svnweb.midnightbsd.org/src/?rev=10653
Author: laffer1
Date: 2018-06-09 15:23:10 -0400 (Sat, 09 Jun 2018)
Log Message:
-----------
sync with freebsd
Modified Paths:
--------------
trunk/lib/libpmc/Makefile
trunk/lib/libpmc/libpmc.c
trunk/lib/libpmc/libpmcinternal.h
trunk/lib/libpmc/pmc.3
trunk/lib/libpmc/pmc.atom.3
trunk/lib/libpmc/pmc.core.3
trunk/lib/libpmc/pmc.core2.3
trunk/lib/libpmc/pmc.corei7.3
trunk/lib/libpmc/pmc.corei7uc.3
trunk/lib/libpmc/pmc.h
trunk/lib/libpmc/pmc.haswell.3
trunk/lib/libpmc/pmc.haswelluc.3
trunk/lib/libpmc/pmc.iaf.3
trunk/lib/libpmc/pmc.ivybridge.3
trunk/lib/libpmc/pmc.ivybridgexeon.3
trunk/lib/libpmc/pmc.k7.3
trunk/lib/libpmc/pmc.k8.3
trunk/lib/libpmc/pmc.mips.3
trunk/lib/libpmc/pmc.p4.3
trunk/lib/libpmc/pmc.p5.3
trunk/lib/libpmc/pmc.p6.3
trunk/lib/libpmc/pmc.sandybridge.3
trunk/lib/libpmc/pmc.sandybridgeuc.3
trunk/lib/libpmc/pmc.sandybridgexeon.3
trunk/lib/libpmc/pmc.soft.3
trunk/lib/libpmc/pmc.tsc.3
trunk/lib/libpmc/pmc.ucf.3
trunk/lib/libpmc/pmc.westmere.3
trunk/lib/libpmc/pmc.westmereuc.3
trunk/lib/libpmc/pmc_allocate.3
trunk/lib/libpmc/pmc_attach.3
trunk/lib/libpmc/pmc_capabilities.3
trunk/lib/libpmc/pmc_configure_logfile.3
trunk/lib/libpmc/pmc_disable.3
trunk/lib/libpmc/pmc_event_names_of_class.3
trunk/lib/libpmc/pmc_get_driver_stats.3
trunk/lib/libpmc/pmc_get_msr.3
trunk/lib/libpmc/pmc_init.3
trunk/lib/libpmc/pmc_name_of_capability.3
trunk/lib/libpmc/pmc_read.3
trunk/lib/libpmc/pmc_set.3
trunk/lib/libpmc/pmc_start.3
trunk/lib/libpmc/pmclog.3
trunk/lib/libpmc/pmclog.c
trunk/lib/libpmc/pmclog.h
trunk/lib/libproc/Makefile
trunk/lib/libproc/_libproc.h
trunk/lib/libproc/libproc.h
trunk/lib/libproc/proc_bkpt.c
trunk/lib/libproc/proc_create.c
trunk/lib/libproc/proc_regs.c
trunk/lib/libproc/proc_rtld.c
trunk/lib/libproc/proc_sym.c
trunk/lib/libproc/proc_util.c
trunk/lib/libproc/test/Makefile
trunk/lib/libproc/test/t1-bkpt/Makefile
trunk/lib/libproc/test/t1-bkpt/t1-bkpt.c
trunk/lib/libproc/test/t2-name2map/Makefile
trunk/lib/libproc/test/t2-name2map/t2-name2map.c
trunk/lib/libproc/test/t3-name2sym/Makefile
trunk/lib/libproc/test/t3-name2sym/t3-name2sym.c
Added Paths:
-----------
trunk/lib/libpmc/pmc.atomsilvermont.3
trunk/lib/libpmc/pmc.haswellxeon.3
trunk/lib/libpmc/pmc.mips24k.3
trunk/lib/libpmc/pmc.octeon.3
trunk/lib/libpmc/pmc.xscale.3
Property Changed:
----------------
trunk/lib/libpmc/pmc.3
trunk/lib/libpmc/pmc.atom.3
trunk/lib/libpmc/pmc.core.3
trunk/lib/libpmc/pmc.core2.3
trunk/lib/libpmc/pmc.corei7.3
trunk/lib/libpmc/pmc.corei7uc.3
trunk/lib/libpmc/pmc.iaf.3
trunk/lib/libpmc/pmc.k7.3
trunk/lib/libpmc/pmc.k8.3
trunk/lib/libpmc/pmc.mips.3
trunk/lib/libpmc/pmc.p4.3
trunk/lib/libpmc/pmc.p5.3
trunk/lib/libpmc/pmc.p6.3
trunk/lib/libpmc/pmc.sandybridge.3
trunk/lib/libpmc/pmc.sandybridgeuc.3
trunk/lib/libpmc/pmc.soft.3
trunk/lib/libpmc/pmc.tsc.3
trunk/lib/libpmc/pmc.ucf.3
trunk/lib/libpmc/pmc.westmere.3
trunk/lib/libpmc/pmc.westmereuc.3
trunk/lib/libpmc/pmc_allocate.3
trunk/lib/libpmc/pmc_attach.3
trunk/lib/libpmc/pmc_capabilities.3
trunk/lib/libpmc/pmc_configure_logfile.3
trunk/lib/libpmc/pmc_disable.3
trunk/lib/libpmc/pmc_event_names_of_class.3
trunk/lib/libpmc/pmc_get_driver_stats.3
trunk/lib/libpmc/pmc_get_msr.3
trunk/lib/libpmc/pmc_init.3
trunk/lib/libpmc/pmc_name_of_capability.3
trunk/lib/libpmc/pmc_read.3
trunk/lib/libpmc/pmc_set.3
trunk/lib/libpmc/pmc_start.3
trunk/lib/libpmc/pmclog.3
Modified: trunk/lib/libpmc/Makefile
===================================================================
--- trunk/lib/libpmc/Makefile 2018-06-09 19:22:04 UTC (rev 10652)
+++ trunk/lib/libpmc/Makefile 2018-06-09 19:23:10 UTC (rev 10653)
@@ -1,5 +1,5 @@
# $MidnightBSD$
-# $FreeBSD: release/9.2.0/lib/libpmc/Makefile 249655 2013-04-19 19:28:48Z hiren $
+# $FreeBSD: stable/10/lib/libpmc/Makefile 266911 2014-05-31 00:40:13Z hiren $
LIB= pmc
@@ -6,8 +6,6 @@
SRCS= libpmc.c pmclog.c
INCS= pmc.h pmclog.h
-WARNS=3
-
MAN= pmc.3
MAN+= pmc_allocate.3
MAN+= pmc_attach.3
@@ -27,27 +25,31 @@
# PMC-dependent manual pages
MAN+= pmc.atom.3
+MAN+= pmc.atomsilvermont.3
MAN+= pmc.core.3
MAN+= pmc.core2.3
+MAN+= pmc.corei7.3
+MAN+= pmc.corei7uc.3
MAN+= pmc.haswell.3
MAN+= pmc.haswelluc.3
MAN+= pmc.iaf.3
MAN+= pmc.ivybridge.3
MAN+= pmc.ivybridgexeon.3
-MAN+= pmc.ucf.3
MAN+= pmc.k7.3
MAN+= pmc.k8.3
+MAN+= pmc.mips24k.3
+MAN+= pmc.octeon.3
MAN+= pmc.p4.3
MAN+= pmc.p5.3
MAN+= pmc.p6.3
-MAN+= pmc.corei7.3
-MAN+= pmc.corei7uc.3
MAN+= pmc.sandybridge.3
-MAN+= pmc.sandybridgeuc.3
-MAN+= pmc.sandybridgexeon.3
+MAN+= pmc.sandybridgeuc.3
+MAN+= pmc.sandybridgexeon.3
+MAN+= pmc.tsc.3
+MAN+= pmc.ucf.3
MAN+= pmc.westmere.3
MAN+= pmc.westmereuc.3
-MAN+= pmc.tsc.3
+MAN+= pmc.xscale.3
MLINKS+= \
pmc_allocate.3 pmc_release.3 \
Modified: trunk/lib/libpmc/libpmc.c
===================================================================
--- trunk/lib/libpmc/libpmc.c 2018-06-09 19:22:04 UTC (rev 10652)
+++ trunk/lib/libpmc/libpmc.c 2018-06-09 19:23:10 UTC (rev 10653)
@@ -26,9 +26,10 @@
*/
#include <sys/cdefs.h>
-__FBSDID("$FreeBSD: release/9.2.0/lib/libpmc/libpmc.c 249655 2013-04-19 19:28:48Z hiren $");
+__FBSDID("$FreeBSD: stable/10/lib/libpmc/libpmc.c 320137 2017-06-20 08:01:13Z avg $");
#include <sys/types.h>
+#include <sys/param.h>
#include <sys/module.h>
#include <sys/pmc.h>
#include <sys/syscall.h>
@@ -79,7 +80,7 @@
struct pmc_op_pmcallocate *_pmc_config);
#endif
#if defined(__mips__)
-static int mips24k_allocate_pmc(enum pmc_event _pe, char* ctrspec,
+static int mips_allocate_pmc(enum pmc_event _pe, char* ctrspec,
struct pmc_op_pmcallocate *_pmc_config);
#endif /* __mips__ */
static int soft_allocate_pmc(enum pmc_event _pe, char *_ctrspec,
@@ -86,7 +87,7 @@
struct pmc_op_pmcallocate *_pmc_config);
#if defined(__powerpc__)
-static int ppc7450_allocate_pmc(enum pmc_event _pe, char* ctrspec,
+static int powerpc_allocate_pmc(enum pmc_event _pe, char* ctrspec,
struct pmc_op_pmcallocate *_pmc_config);
#endif /* __powerpc__ */
@@ -154,8 +155,10 @@
PMC_CLASSDEP_TABLE(p6, P6);
PMC_CLASSDEP_TABLE(xscale, XSCALE);
PMC_CLASSDEP_TABLE(mips24k, MIPS24K);
+PMC_CLASSDEP_TABLE(octeon, OCTEON);
PMC_CLASSDEP_TABLE(ucf, UCF);
PMC_CLASSDEP_TABLE(ppc7450, PPC7450);
+PMC_CLASSDEP_TABLE(ppc970, PPC970);
static struct pmc_event_descr soft_event_table[PMC_EV_DYN_COUNT];
@@ -167,6 +170,11 @@
__PMC_EV_ALIAS_ATOM()
};
+static const struct pmc_event_descr atom_silvermont_event_table[] =
+{
+ __PMC_EV_ALIAS_ATOM_SILVERMONT()
+};
+
static const struct pmc_event_descr core_event_table[] =
{
__PMC_EV_ALIAS_CORE()
@@ -183,11 +191,36 @@
__PMC_EV_ALIAS_COREI7()
};
+static const struct pmc_event_descr nehalem_ex_event_table[] =
+{
+ __PMC_EV_ALIAS_COREI7()
+};
+
static const struct pmc_event_descr haswell_event_table[] =
{
__PMC_EV_ALIAS_HASWELL()
};
+static const struct pmc_event_descr haswell_xeon_event_table[] =
+{
+ __PMC_EV_ALIAS_HASWELL_XEON()
+};
+
+static const struct pmc_event_descr broadwell_event_table[] =
+{
+ __PMC_EV_ALIAS_BROADWELL()
+};
+
+static const struct pmc_event_descr broadwell_xeon_event_table[] =
+{
+ __PMC_EV_ALIAS_BROADWELL_XEON()
+};
+
+static const struct pmc_event_descr skylake_event_table[] =
+{
+ __PMC_EV_ALIAS_SKYLAKE()
+};
+
static const struct pmc_event_descr ivybridge_event_table[] =
{
__PMC_EV_ALIAS_IVYBRIDGE()
@@ -213,6 +246,11 @@
__PMC_EV_ALIAS_WESTMERE()
};
+static const struct pmc_event_descr westmere_ex_event_table[] =
+{
+ __PMC_EV_ALIAS_WESTMERE()
+};
+
static const struct pmc_event_descr corei7uc_event_table[] =
{
__PMC_EV_ALIAS_COREI7UC()
@@ -223,6 +261,11 @@
__PMC_EV_ALIAS_HASWELLUC()
};
+static const struct pmc_event_descr broadwelluc_event_table[] =
+{
+ __PMC_EV_ALIAS_BROADWELLUC()
+};
+
static const struct pmc_event_descr sandybridgeuc_event_table[] =
{
__PMC_EV_ALIAS_SANDYBRIDGEUC()
@@ -244,15 +287,22 @@
}
PMC_MDEP_TABLE(atom, IAP, PMC_CLASS_SOFT, PMC_CLASS_IAF, PMC_CLASS_TSC);
+PMC_MDEP_TABLE(atom_silvermont, IAP, PMC_CLASS_SOFT, PMC_CLASS_IAF, PMC_CLASS_TSC);
PMC_MDEP_TABLE(core, IAP, PMC_CLASS_SOFT, PMC_CLASS_TSC);
PMC_MDEP_TABLE(core2, IAP, PMC_CLASS_SOFT, PMC_CLASS_IAF, PMC_CLASS_TSC);
PMC_MDEP_TABLE(corei7, IAP, PMC_CLASS_SOFT, PMC_CLASS_IAF, PMC_CLASS_TSC, PMC_CLASS_UCF, PMC_CLASS_UCP);
+PMC_MDEP_TABLE(nehalem_ex, IAP, PMC_CLASS_SOFT, PMC_CLASS_IAF, PMC_CLASS_TSC);
PMC_MDEP_TABLE(haswell, IAP, PMC_CLASS_SOFT, PMC_CLASS_IAF, PMC_CLASS_TSC, PMC_CLASS_UCF, PMC_CLASS_UCP);
+PMC_MDEP_TABLE(haswell_xeon, IAP, PMC_CLASS_SOFT, PMC_CLASS_IAF, PMC_CLASS_TSC, PMC_CLASS_UCF, PMC_CLASS_UCP);
+PMC_MDEP_TABLE(broadwell, IAP, PMC_CLASS_SOFT, PMC_CLASS_IAF, PMC_CLASS_TSC, PMC_CLASS_UCF, PMC_CLASS_UCP);
+PMC_MDEP_TABLE(broadwell_xeon, IAP, PMC_CLASS_SOFT, PMC_CLASS_IAF, PMC_CLASS_TSC, PMC_CLASS_UCF, PMC_CLASS_UCP);
+PMC_MDEP_TABLE(skylake, IAP, PMC_CLASS_SOFT, PMC_CLASS_IAF, PMC_CLASS_TSC, PMC_CLASS_UCF, PMC_CLASS_UCP);
PMC_MDEP_TABLE(ivybridge, IAP, PMC_CLASS_SOFT, PMC_CLASS_IAF, PMC_CLASS_TSC);
PMC_MDEP_TABLE(ivybridge_xeon, IAP, PMC_CLASS_SOFT, PMC_CLASS_IAF, PMC_CLASS_TSC);
PMC_MDEP_TABLE(sandybridge, IAP, PMC_CLASS_SOFT, PMC_CLASS_IAF, PMC_CLASS_TSC, PMC_CLASS_UCF, PMC_CLASS_UCP);
PMC_MDEP_TABLE(sandybridge_xeon, IAP, PMC_CLASS_SOFT, PMC_CLASS_IAF, PMC_CLASS_TSC);
PMC_MDEP_TABLE(westmere, IAP, PMC_CLASS_SOFT, PMC_CLASS_IAF, PMC_CLASS_TSC, PMC_CLASS_UCF, PMC_CLASS_UCP);
+PMC_MDEP_TABLE(westmere_ex, IAP, PMC_CLASS_SOFT, PMC_CLASS_IAF, PMC_CLASS_TSC);
PMC_MDEP_TABLE(k7, K7, PMC_CLASS_SOFT, PMC_CLASS_TSC);
PMC_MDEP_TABLE(k8, K8, PMC_CLASS_SOFT, PMC_CLASS_TSC);
PMC_MDEP_TABLE(p4, P4, PMC_CLASS_SOFT, PMC_CLASS_TSC);
@@ -260,7 +310,9 @@
PMC_MDEP_TABLE(p6, P6, PMC_CLASS_SOFT, PMC_CLASS_TSC);
PMC_MDEP_TABLE(xscale, XSCALE, PMC_CLASS_SOFT, PMC_CLASS_XSCALE);
PMC_MDEP_TABLE(mips24k, MIPS24K, PMC_CLASS_SOFT, PMC_CLASS_MIPS24K);
+PMC_MDEP_TABLE(octeon, OCTEON, PMC_CLASS_SOFT, PMC_CLASS_OCTEON);
PMC_MDEP_TABLE(ppc7450, PPC7450, PMC_CLASS_SOFT, PMC_CLASS_PPC7450);
+PMC_MDEP_TABLE(ppc970, PPC970, PMC_CLASS_SOFT, PMC_CLASS_PPC970);
PMC_MDEP_TABLE(generic, SOFT, PMC_CLASS_SOFT);
static const struct pmc_event_descr tsc_event_table[] =
@@ -284,18 +336,26 @@
#if defined(__i386__) || defined(__amd64__)
PMC_CLASS_TABLE_DESC(iaf, IAF, iaf, iaf);
PMC_CLASS_TABLE_DESC(atom, IAP, atom, iap);
+PMC_CLASS_TABLE_DESC(atom_silvermont, IAP, atom_silvermont, iap);
PMC_CLASS_TABLE_DESC(core, IAP, core, iap);
PMC_CLASS_TABLE_DESC(core2, IAP, core2, iap);
PMC_CLASS_TABLE_DESC(corei7, IAP, corei7, iap);
+PMC_CLASS_TABLE_DESC(nehalem_ex, IAP, nehalem_ex, iap);
PMC_CLASS_TABLE_DESC(haswell, IAP, haswell, iap);
+PMC_CLASS_TABLE_DESC(haswell_xeon, IAP, haswell_xeon, iap);
+PMC_CLASS_TABLE_DESC(broadwell, IAP, broadwell, iap);
+PMC_CLASS_TABLE_DESC(broadwell_xeon, IAP, broadwell_xeon, iap);
+PMC_CLASS_TABLE_DESC(skylake, IAP, skylake, iap);
PMC_CLASS_TABLE_DESC(ivybridge, IAP, ivybridge, iap);
PMC_CLASS_TABLE_DESC(ivybridge_xeon, IAP, ivybridge_xeon, iap);
PMC_CLASS_TABLE_DESC(sandybridge, IAP, sandybridge, iap);
PMC_CLASS_TABLE_DESC(sandybridge_xeon, IAP, sandybridge_xeon, iap);
PMC_CLASS_TABLE_DESC(westmere, IAP, westmere, iap);
+PMC_CLASS_TABLE_DESC(westmere_ex, IAP, westmere_ex, iap);
PMC_CLASS_TABLE_DESC(ucf, UCF, ucf, ucf);
PMC_CLASS_TABLE_DESC(corei7uc, UCP, corei7uc, ucp);
PMC_CLASS_TABLE_DESC(haswelluc, UCP, haswelluc, ucp);
+PMC_CLASS_TABLE_DESC(broadwelluc, UCP, broadwelluc, ucp);
PMC_CLASS_TABLE_DESC(sandybridgeuc, UCP, sandybridgeuc, ucp);
PMC_CLASS_TABLE_DESC(westmereuc, UCP, westmereuc, ucp);
#endif
@@ -317,10 +377,12 @@
PMC_CLASS_TABLE_DESC(xscale, XSCALE, xscale, xscale);
#endif
#if defined(__mips__)
-PMC_CLASS_TABLE_DESC(mips24k, MIPS24K, mips24k, mips24k);
+PMC_CLASS_TABLE_DESC(mips24k, MIPS24K, mips24k, mips);
+PMC_CLASS_TABLE_DESC(octeon, OCTEON, octeon, mips);
#endif /* __mips__ */
#if defined(__powerpc__)
-PMC_CLASS_TABLE_DESC(ppc7450, PPC7450, ppc7450, ppc7450);
+PMC_CLASS_TABLE_DESC(ppc7450, PPC7450, ppc7450, powerpc);
+PMC_CLASS_TABLE_DESC(ppc970, PPC970, ppc970, powerpc);
#endif
static struct pmc_class_descr soft_class_table_descr =
@@ -591,10 +653,22 @@
#define atom_aliases core2_aliases
#define atom_aliases_without_iaf core2_aliases_without_iaf
+#define atom_silvermont_aliases core2_aliases
+#define atom_silvermont_aliases_without_iaf core2_aliases_without_iaf
#define corei7_aliases core2_aliases
#define corei7_aliases_without_iaf core2_aliases_without_iaf
+#define nehalem_ex_aliases core2_aliases
+#define nehalem_ex_aliases_without_iaf core2_aliases_without_iaf
#define haswell_aliases core2_aliases
#define haswell_aliases_without_iaf core2_aliases_without_iaf
+#define haswell_xeon_aliases core2_aliases
+#define haswell_xeon_aliases_without_iaf core2_aliases_without_iaf
+#define broadwell_aliases core2_aliases
+#define broadwell_aliases_without_iaf core2_aliases_without_iaf
+#define broadwell_xeon_aliases core2_aliases
+#define broadwell_xeon_aliases_without_iaf core2_aliases_without_iaf
+#define skylake_aliases core2_aliases
+#define skylake_aliases_without_iaf core2_aliases_without_iaf
#define ivybridge_aliases core2_aliases
#define ivybridge_aliases_without_iaf core2_aliases_without_iaf
#define ivybridge_xeon_aliases core2_aliases
@@ -605,6 +679,8 @@
#define sandybridge_xeon_aliases_without_iaf core2_aliases_without_iaf
#define westmere_aliases core2_aliases
#define westmere_aliases_without_iaf core2_aliases_without_iaf
+#define westmere_ex_aliases core2_aliases
+#define westmere_ex_aliases_without_iaf core2_aliases_without_iaf
#define IAF_KW_OS "os"
#define IAF_KW_USR "usr"
@@ -753,6 +829,7 @@
NULLMASK
};
+/* Broadwell is defined to use the same mask as Haswell */
static struct pmc_masks iap_rsp_mask_haswell[] = {
PMCMASK(REQ_DMND_DATA_RD, (1ULL << 0)),
PMCMASK(REQ_DMND_RFO, (1ULL << 1)),
@@ -768,6 +845,10 @@
PMCMASK(RES_SUPPLIER_LLC_HITS, (1ULL << 20)),
PMCMASK(RES_SUPPLIER_LLC_HITF, (1ULL << 21)),
PMCMASK(RES_SUPPLIER_LOCAL, (1ULL << 22)),
+ /*
+ * For processor type 06_45H 22 is L4_HIT_LOCAL_L4
+ * and 23, 24 and 25 are also defined.
+ */
PMCMASK(RES_SNOOP_SNP_NONE, (1ULL << 31)),
PMCMASK(RES_SNOOP_SNP_NO_NEEDED,(1ULL << 32)),
PMCMASK(RES_SNOOP_SNP_MISS, (1ULL << 33)),
@@ -778,6 +859,33 @@
NULLMASK
};
+static struct pmc_masks iap_rsp_mask_skylake[] = {
+ PMCMASK(REQ_DMND_DATA_RD, (1ULL << 0)),
+ PMCMASK(REQ_DMND_RFO, (1ULL << 1)),
+ PMCMASK(REQ_DMND_IFETCH, (1ULL << 2)),
+ PMCMASK(REQ_PF_DATA_RD, (1ULL << 7)),
+ PMCMASK(REQ_PF_RFO, (1ULL << 8)),
+ PMCMASK(REQ_STRM_ST, (1ULL << 11)),
+ PMCMASK(REQ_OTHER, (1ULL << 15)),
+ PMCMASK(RES_ANY, (1ULL << 16)),
+ PMCMASK(RES_SUPPLIER_SUPP, (1ULL << 17)),
+ PMCMASK(RES_SUPPLIER_LLC_HITM, (1ULL << 18)),
+ PMCMASK(RES_SUPPLIER_LLC_HITE, (1ULL << 19)),
+ PMCMASK(RES_SUPPLIER_LLC_HITS, (1ULL << 20)),
+ PMCMASK(RES_SUPPLIER_L4_HIT, (1ULL << 22)),
+ PMCMASK(RES_SUPPLIER_DRAM, (1ULL << 26)),
+ PMCMASK(RES_SUPPLIER_SPL_HIT, (1ULL << 30)),
+ PMCMASK(RES_SNOOP_SNP_NONE, (1ULL << 31)),
+ PMCMASK(RES_SNOOP_SNP_NO_NEEDED,(1ULL << 32)),
+ PMCMASK(RES_SNOOP_SNP_MISS, (1ULL << 33)),
+ PMCMASK(RES_SNOOP_HIT_NO_FWD, (1ULL << 34)),
+ PMCMASK(RES_SNOOP_HIT_FWD, (1ULL << 35)),
+ PMCMASK(RES_SNOOP_HITM, (1ULL << 36)),
+ PMCMASK(RES_NON_DRAM, (1ULL << 37)),
+ NULLMASK
+};
+
+
static int
iap_allocate_pmc(enum pmc_event pe, char *ctrspec,
struct pmc_op_pmcallocate *pmc_config)
@@ -836,6 +944,7 @@
if (n != 1)
return (-1);
} else if (cpu_info.pm_cputype == PMC_CPU_INTEL_ATOM ||
+ cpu_info.pm_cputype == PMC_CPU_INTEL_ATOM_SILVERMONT ||
cpu_info.pm_cputype == PMC_CPU_INTEL_CORE2 ||
cpu_info.pm_cputype == PMC_CPU_INTEL_CORE2EXTREME) {
if (KWPREFIXMATCH(p, IAP_KW_SNOOPRESPONSE "=")) {
@@ -847,7 +956,9 @@
} else
return (-1);
} else if (cpu_info.pm_cputype == PMC_CPU_INTEL_COREI7 ||
- cpu_info.pm_cputype == PMC_CPU_INTEL_WESTMERE) {
+ cpu_info.pm_cputype == PMC_CPU_INTEL_WESTMERE ||
+ cpu_info.pm_cputype == PMC_CPU_INTEL_NEHALEM_EX ||
+ cpu_info.pm_cputype == PMC_CPU_INTEL_WESTMERE_EX) {
if (KWPREFIXMATCH(p, IAP_KW_RSP "=")) {
n = pmc_parse_mask(iap_rsp_mask_i7_wm, p, &rsp);
} else
@@ -860,11 +971,26 @@
n = pmc_parse_mask(iap_rsp_mask_sb_sbx_ib, p, &rsp);
} else
return (-1);
- } else if (cpu_info.pm_cputype == PMC_CPU_INTEL_HASWELL) {
+ } else if (cpu_info.pm_cputype == PMC_CPU_INTEL_HASWELL ||
+ cpu_info.pm_cputype == PMC_CPU_INTEL_HASWELL_XEON) {
if (KWPREFIXMATCH(p, IAP_KW_RSP "=")) {
n = pmc_parse_mask(iap_rsp_mask_haswell, p, &rsp);
} else
return (-1);
+ } else if (cpu_info.pm_cputype == PMC_CPU_INTEL_BROADWELL ||
+ cpu_info.pm_cputype == PMC_CPU_INTEL_BROADWELL_XEON) {
+ /* Broadwell is defined to use same mask as haswell */
+ if (KWPREFIXMATCH(p, IAP_KW_RSP "=")) {
+ n = pmc_parse_mask(iap_rsp_mask_haswell, p, &rsp);
+ } else
+ return (-1);
+
+ } else if (cpu_info.pm_cputype == PMC_CPU_INTEL_SKYLAKE) {
+ if (KWPREFIXMATCH(p, IAP_KW_RSP "=")) {
+ n = pmc_parse_mask(iap_rsp_mask_skylake, p, &rsp);
+ } else
+ return (-1);
+
} else
return (-1);
@@ -2356,12 +2482,19 @@
EV_ALIAS(NULL, NULL)
};
-#define MIPS24K_KW_OS "os"
-#define MIPS24K_KW_USR "usr"
-#define MIPS24K_KW_ANYTHREAD "anythread"
+static struct pmc_event_alias octeon_aliases[] = {
+ EV_ALIAS("instructions", "RET"),
+ EV_ALIAS("branches", "BR"),
+ EV_ALIAS("branch-mispredicts", "BRMIS"),
+ EV_ALIAS(NULL, NULL)
+};
+#define MIPS_KW_OS "os"
+#define MIPS_KW_USR "usr"
+#define MIPS_KW_ANYTHREAD "anythread"
+
static int
-mips24k_allocate_pmc(enum pmc_event pe, char *ctrspec __unused,
+mips_allocate_pmc(enum pmc_event pe, char *ctrspec __unused,
struct pmc_op_pmcallocate *pmc_config __unused)
{
char *p;
@@ -2371,11 +2504,11 @@
pmc_config->pm_caps |= (PMC_CAP_READ | PMC_CAP_WRITE);
while ((p = strsep(&ctrspec, ",")) != NULL) {
- if (KWMATCH(p, MIPS24K_KW_OS))
+ if (KWMATCH(p, MIPS_KW_OS))
pmc_config->pm_caps |= PMC_CAP_SYSTEM;
- else if (KWMATCH(p, MIPS24K_KW_USR))
+ else if (KWMATCH(p, MIPS_KW_USR))
pmc_config->pm_caps |= PMC_CAP_USER;
- else if (KWMATCH(p, MIPS24K_KW_ANYTHREAD))
+ else if (KWMATCH(p, MIPS_KW_ANYTHREAD))
pmc_config->pm_caps |= (PMC_CAP_USER | PMC_CAP_SYSTEM);
else
return (-1);
@@ -2383,6 +2516,7 @@
return (0);
}
+
#endif /* __mips__ */
#if defined(__powerpc__)
@@ -2394,13 +2528,19 @@
EV_ALIAS(NULL, NULL)
};
-#define PPC7450_KW_OS "os"
-#define PPC7450_KW_USR "usr"
-#define PPC7450_KW_ANYTHREAD "anythread"
+static struct pmc_event_alias ppc970_aliases[] = {
+ EV_ALIAS("instructions", "INSTR_COMPLETED"),
+ EV_ALIAS("cycles", "CYCLES"),
+ EV_ALIAS(NULL, NULL)
+};
+#define POWERPC_KW_OS "os"
+#define POWERPC_KW_USR "usr"
+#define POWERPC_KW_ANYTHREAD "anythread"
+
static int
-ppc7450_allocate_pmc(enum pmc_event pe, char *ctrspec __unused,
- struct pmc_op_pmcallocate *pmc_config __unused)
+powerpc_allocate_pmc(enum pmc_event pe, char *ctrspec __unused,
+ struct pmc_op_pmcallocate *pmc_config __unused)
{
char *p;
@@ -2409,11 +2549,11 @@
pmc_config->pm_caps |= (PMC_CAP_READ | PMC_CAP_WRITE);
while ((p = strsep(&ctrspec, ",")) != NULL) {
- if (KWMATCH(p, PPC7450_KW_OS))
+ if (KWMATCH(p, POWERPC_KW_OS))
pmc_config->pm_caps |= PMC_CAP_SYSTEM;
- else if (KWMATCH(p, PPC7450_KW_USR))
+ else if (KWMATCH(p, POWERPC_KW_USR))
pmc_config->pm_caps |= PMC_CAP_USER;
- else if (KWMATCH(p, PPC7450_KW_ANYTHREAD))
+ else if (KWMATCH(p, POWERPC_KW_ANYTHREAD))
pmc_config->pm_caps |= (PMC_CAP_USER | PMC_CAP_SYSTEM);
else
return (-1);
@@ -2421,6 +2561,7 @@
return (0);
}
+
#endif /* __powerpc__ */
@@ -2712,6 +2853,10 @@
ev = atom_event_table;
count = PMC_EVENT_TABLE_SIZE(atom);
break;
+ case PMC_CPU_INTEL_ATOM_SILVERMONT:
+ ev = atom_silvermont_event_table;
+ count = PMC_EVENT_TABLE_SIZE(atom_silvermont);
+ break;
case PMC_CPU_INTEL_CORE:
ev = core_event_table;
count = PMC_EVENT_TABLE_SIZE(core);
@@ -2725,10 +2870,30 @@
ev = corei7_event_table;
count = PMC_EVENT_TABLE_SIZE(corei7);
break;
+ case PMC_CPU_INTEL_NEHALEM_EX:
+ ev = nehalem_ex_event_table;
+ count = PMC_EVENT_TABLE_SIZE(nehalem_ex);
+ break;
case PMC_CPU_INTEL_HASWELL:
ev = haswell_event_table;
count = PMC_EVENT_TABLE_SIZE(haswell);
break;
+ case PMC_CPU_INTEL_HASWELL_XEON:
+ ev = haswell_xeon_event_table;
+ count = PMC_EVENT_TABLE_SIZE(haswell_xeon);
+ break;
+ case PMC_CPU_INTEL_BROADWELL:
+ ev = broadwell_event_table;
+ count = PMC_EVENT_TABLE_SIZE(broadwell);
+ break;
+ case PMC_CPU_INTEL_BROADWELL_XEON:
+ ev = broadwell_xeon_event_table;
+ count = PMC_EVENT_TABLE_SIZE(broadwell_xeon);
+ break;
+ case PMC_CPU_INTEL_SKYLAKE:
+ ev = skylake_event_table;
+ count = PMC_EVENT_TABLE_SIZE(skylake);
+ break;
case PMC_CPU_INTEL_IVYBRIDGE:
ev = ivybridge_event_table;
count = PMC_EVENT_TABLE_SIZE(ivybridge);
@@ -2749,6 +2914,10 @@
ev = westmere_event_table;
count = PMC_EVENT_TABLE_SIZE(westmere);
break;
+ case PMC_CPU_INTEL_WESTMERE_EX:
+ ev = westmere_ex_event_table;
+ count = PMC_EVENT_TABLE_SIZE(westmere_ex);
+ break;
}
break;
case PMC_CLASS_UCF:
@@ -2770,6 +2939,10 @@
ev = haswelluc_event_table;
count = PMC_EVENT_TABLE_SIZE(haswelluc);
break;
+ case PMC_CPU_INTEL_BROADWELL:
+ ev = broadwelluc_event_table;
+ count = PMC_EVENT_TABLE_SIZE(broadwelluc);
+ break;
case PMC_CPU_INTEL_SANDYBRIDGE:
ev = sandybridgeuc_event_table;
count = PMC_EVENT_TABLE_SIZE(sandybridgeuc);
@@ -2812,10 +2985,18 @@
ev = mips24k_event_table;
count = PMC_EVENT_TABLE_SIZE(mips24k);
break;
+ case PMC_CLASS_OCTEON:
+ ev = octeon_event_table;
+ count = PMC_EVENT_TABLE_SIZE(octeon);
+ break;
case PMC_CLASS_PPC7450:
ev = ppc7450_event_table;
count = PMC_EVENT_TABLE_SIZE(ppc7450);
break;
+ case PMC_CLASS_PPC970:
+ ev = ppc970_event_table;
+ count = PMC_EVENT_TABLE_SIZE(ppc970);
+ break;
case PMC_CLASS_SOFT:
ev = soft_event_table;
count = soft_event_info.pm_nevent;
@@ -3020,6 +3201,9 @@
case PMC_CPU_INTEL_ATOM:
PMC_MDEP_INIT_INTEL_V2(atom);
break;
+ case PMC_CPU_INTEL_ATOM_SILVERMONT:
+ PMC_MDEP_INIT_INTEL_V2(atom_silvermont);
+ break;
case PMC_CPU_INTEL_CORE:
PMC_MDEP_INIT(core);
pmc_class_table[n] = &core_class_table_descr;
@@ -3033,11 +3217,28 @@
pmc_class_table[n++] = &corei7uc_class_table_descr;
PMC_MDEP_INIT_INTEL_V2(corei7);
break;
+ case PMC_CPU_INTEL_NEHALEM_EX:
+ PMC_MDEP_INIT_INTEL_V2(nehalem_ex);
+ break;
case PMC_CPU_INTEL_HASWELL:
pmc_class_table[n++] = &ucf_class_table_descr;
pmc_class_table[n++] = &haswelluc_class_table_descr;
PMC_MDEP_INIT_INTEL_V2(haswell);
break;
+ case PMC_CPU_INTEL_HASWELL_XEON:
+ PMC_MDEP_INIT_INTEL_V2(haswell_xeon);
+ break;
+ case PMC_CPU_INTEL_BROADWELL:
+ pmc_class_table[n++] = &ucf_class_table_descr;
+ pmc_class_table[n++] = &broadwelluc_class_table_descr;
+ PMC_MDEP_INIT_INTEL_V2(broadwell);
+ break;
+ case PMC_CPU_INTEL_BROADWELL_XEON:
+ PMC_MDEP_INIT_INTEL_V2(broadwell_xeon);
+ break;
+ case PMC_CPU_INTEL_SKYLAKE:
+ PMC_MDEP_INIT_INTEL_V2(skylake);
+ break;
case PMC_CPU_INTEL_IVYBRIDGE:
PMC_MDEP_INIT_INTEL_V2(ivybridge);
break;
@@ -3057,6 +3258,9 @@
pmc_class_table[n++] = &westmereuc_class_table_descr;
PMC_MDEP_INIT_INTEL_V2(westmere);
break;
+ case PMC_CPU_INTEL_WESTMERE_EX:
+ PMC_MDEP_INIT_INTEL_V2(westmere_ex);
+ break;
case PMC_CPU_INTEL_PIV:
PMC_MDEP_INIT(p4);
pmc_class_table[n] = &p4_class_table_descr;
@@ -3076,6 +3280,10 @@
PMC_MDEP_INIT(mips24k);
pmc_class_table[n] = &mips24k_class_table_descr;
break;
+ case PMC_CPU_MIPS_OCTEON:
+ PMC_MDEP_INIT(octeon);
+ pmc_class_table[n] = &octeon_class_table_descr;
+ break;
#endif /* __mips__ */
#if defined(__powerpc__)
case PMC_CPU_PPC_7450:
@@ -3082,6 +3290,10 @@
PMC_MDEP_INIT(ppc7450);
pmc_class_table[n] = &ppc7450_class_table_descr;
break;
+ case PMC_CPU_PPC_970:
+ PMC_MDEP_INIT(ppc970);
+ pmc_class_table[n] = &ppc970_class_table_descr;
+ break;
#endif
default:
/*
@@ -3165,6 +3377,11 @@
ev = atom_event_table;
evfence = atom_event_table + PMC_EVENT_TABLE_SIZE(atom);
break;
+ case PMC_CPU_INTEL_ATOM_SILVERMONT:
+ ev = atom_silvermont_event_table;
+ evfence = atom_silvermont_event_table +
+ PMC_EVENT_TABLE_SIZE(atom_silvermont);
+ break;
case PMC_CPU_INTEL_CORE:
ev = core_event_table;
evfence = core_event_table + PMC_EVENT_TABLE_SIZE(core);
@@ -3178,10 +3395,31 @@
ev = corei7_event_table;
evfence = corei7_event_table + PMC_EVENT_TABLE_SIZE(corei7);
break;
+ case PMC_CPU_INTEL_NEHALEM_EX:
+ ev = nehalem_ex_event_table;
+ evfence = nehalem_ex_event_table +
+ PMC_EVENT_TABLE_SIZE(nehalem_ex);
+ break;
case PMC_CPU_INTEL_HASWELL:
ev = haswell_event_table;
evfence = haswell_event_table + PMC_EVENT_TABLE_SIZE(haswell);
break;
+ case PMC_CPU_INTEL_HASWELL_XEON:
+ ev = haswell_xeon_event_table;
+ evfence = haswell_xeon_event_table + PMC_EVENT_TABLE_SIZE(haswell_xeon);
+ break;
+ case PMC_CPU_INTEL_BROADWELL:
+ ev = broadwell_event_table;
+ evfence = broadwell_event_table + PMC_EVENT_TABLE_SIZE(broadwell);
+ break;
+ case PMC_CPU_INTEL_BROADWELL_XEON:
+ ev = broadwell_xeon_event_table;
+ evfence = broadwell_xeon_event_table + PMC_EVENT_TABLE_SIZE(broadwell_xeon);
+ break;
+ case PMC_CPU_INTEL_SKYLAKE:
+ ev = skylake_event_table;
+ evfence = skylake_event_table + PMC_EVENT_TABLE_SIZE(skylake);
+ break;
case PMC_CPU_INTEL_IVYBRIDGE:
ev = ivybridge_event_table;
evfence = ivybridge_event_table + PMC_EVENT_TABLE_SIZE(ivybridge);
@@ -3202,6 +3440,11 @@
ev = westmere_event_table;
evfence = westmere_event_table + PMC_EVENT_TABLE_SIZE(westmere);
break;
+ case PMC_CPU_INTEL_WESTMERE_EX:
+ ev = westmere_ex_event_table;
+ evfence = westmere_ex_event_table +
+ PMC_EVENT_TABLE_SIZE(westmere_ex);
+ break;
default: /* Unknown CPU type. */
break;
}
@@ -3246,9 +3489,15 @@
} else if (pe >= PMC_EV_MIPS24K_FIRST && pe <= PMC_EV_MIPS24K_LAST) {
ev = mips24k_event_table;
evfence = mips24k_event_table + PMC_EVENT_TABLE_SIZE(mips24k);
+ } else if (pe >= PMC_EV_OCTEON_FIRST && pe <= PMC_EV_OCTEON_LAST) {
+ ev = octeon_event_table;
+ evfence = octeon_event_table + PMC_EVENT_TABLE_SIZE(octeon);
} else if (pe >= PMC_EV_PPC7450_FIRST && pe <= PMC_EV_PPC7450_LAST) {
ev = ppc7450_event_table;
evfence = ppc7450_event_table + PMC_EVENT_TABLE_SIZE(ppc7450);
+ } else if (pe >= PMC_EV_PPC970_FIRST && pe <= PMC_EV_PPC970_LAST) {
+ ev = ppc970_event_table;
+ evfence = ppc970_event_table + PMC_EVENT_TABLE_SIZE(ppc970);
} else if (pe == PMC_EV_TSC_TSC) {
ev = tsc_event_table;
evfence = tsc_event_table + PMC_EVENT_TABLE_SIZE(tsc);
Modified: trunk/lib/libpmc/libpmcinternal.h
===================================================================
--- trunk/lib/libpmc/libpmcinternal.h 2018-06-09 19:22:04 UTC (rev 10652)
+++ trunk/lib/libpmc/libpmcinternal.h 2018-06-09 19:23:10 UTC (rev 10653)
@@ -24,7 +24,7 @@
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*
- * $FreeBSD: release/9.2.0/lib/libpmc/libpmcinternal.h 185363 2008-11-27 09:00:47Z jkoshy $
+ * $FreeBSD: stable/10/lib/libpmc/libpmcinternal.h 185363 2008-11-27 09:00:47Z jkoshy $
*/
#ifndef LIBPMC_INTERNAL_H
Modified: trunk/lib/libpmc/pmc.3
===================================================================
--- trunk/lib/libpmc/pmc.3 2018-06-09 19:22:04 UTC (rev 10652)
+++ trunk/lib/libpmc/pmc.3 2018-06-09 19:23:10 UTC (rev 10653)
@@ -1,3 +1,4 @@
+.\" $MidnightBSD$
.\" Copyright (c) 2003-2008 Joseph Koshy. All rights reserved.
.\"
.\" Redistribution and use in source and binary forms, with or without
@@ -21,9 +22,9 @@
.\" OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
.\" SUCH DAMAGE.
.\"
-.\" $FreeBSD: release/9.2.0/lib/libpmc/pmc.3 236238 2012-05-29 14:50:21Z fabient $
+.\" $FreeBSD: stable/10/lib/libpmc/pmc.3 321223 2017-07-19 18:22:55Z ngie $
.\"
-.Dd November 24, 2008
+.Dd April 6, 2017
.Dt PMC 3
.Os
.Sh NAME
@@ -111,7 +112,7 @@
Certain kinds of PMCs require that a log file be configured before
they may be started.
These include:
-.Bl -bullet -compact
+.Bl -bullet
.It
System scope sampling PMCs.
.It
@@ -120,6 +121,7 @@
Process scope counting PMCs that have been configured to report PMC
readings on process context switches or process exits.
.El
+.Pp
Up to one log file may be configured per owner process.
Events logged to a log file may be subsequently analyzed using the
.Xr pmclog 3
@@ -129,6 +131,7 @@
.Vt "enum pmc_cputype"
enumeration.
Supported CPUs include:
+.Pp
.Bl -tag -width "Li PMC_CPU_INTEL_CORE2" -compact
.It Li PMC_CPU_AMD_K7
.Tn "AMD Athlon"
@@ -185,6 +188,7 @@
.Vt enum pmc_class
enumeration.
Supported PMC kinds include:
+.Pp
.Bl -tag -width "Li PMC_CLASS_IAF" -compact
.It Li PMC_CLASS_IAF
Fixed function hardware counters presents in CPUs conforming to the
@@ -227,12 +231,12 @@
Software events.
.El
.Ss PMC Capabilities
-.Pp
Capabilities of performance monitoring hardware are denoted using
the
.Vt "enum pmc_caps"
enumeration.
Supported capabilities include:
+.Pp
.Bl -tag -width "Li PMC_CAP_INTERRUPT" -compact
.It Li PMC_CAP_CASCADE
The ability to cascade counters.
@@ -274,9 +278,9 @@
This section contains a brief overview of the available functionality
in the PMC library.
Each function listed here is described further in its own manual page.
-.Bl -tag -width indent
+.Bl -tag -width 2n
.It Administration
-.Bl -tag -compact
+.Bl -tag -width 6n -compact
.It Fn pmc_disable , Fn pmc_enable
Administratively disable (enable) specific performance monitoring
counter hardware.
@@ -284,7 +288,7 @@
use.
.El
.It "Convenience Functions"
-.Bl -tag -compact
+.Bl -tag -width 6n -compact
.It Fn pmc_event_names_of_class
Returns a list of event names supported by a given PMC type.
.It Fn pmc_name_of_capability
@@ -309,13 +313,13 @@
Return a human-readable string describing a PMC's current state.
.El
.It "Library Initialization"
-.Bl -tag -compact
+.Bl -tag -width 6n -compact
.It Fn pmc_init
Initialize the library.
This function must be called before any other library function.
.El
.It "Log File Handling"
-.Bl -tag -compact
+.Bl -tag -width 6n -compact
.It Fn pmc_configure_logfile
Configure a log file for
.Xr hwpmc 4
@@ -332,7 +336,7 @@
Append arbitrary user data to the current log file.
.El
.It "PMC Management"
-.Bl -tag -compact
+.Bl -tag -width 6n -compact
.It Fn pmc_allocate , Fn pmc_release
Allocate (free) a PMC.
.It Fn pmc_attach , Fn pmc_detach
@@ -345,7 +349,7 @@
Set the reload value for a sampling PMC.
.El
.It "Queries"
-.Bl -tag -compact
+.Bl -tag -width 6n -compact
.It Fn pmc_capabilities
Retrieve the capabilities for a given PMC.
.It Fn pmc_cpuinfo
@@ -364,7 +368,7 @@
Determine the width of a hardware counter in bits.
.El
.It "x86 Architecture Specific API"
-.Bl -tag -compact
+.Bl -tag -width 6n -compact
.It Fn pmc_get_msr
Returns the processor model specific register number
associated with
@@ -522,6 +526,7 @@
.Xr pmc.atom 3 ,
.Xr pmc.core 3 ,
.Xr pmc.core2 3 ,
+.Xr pmc.haswellxeon 3 ,
.Xr pmc.iaf 3 ,
.Xr pmc.k7 3 ,
.Xr pmc.k8 3 ,
@@ -530,6 +535,19 @@
.Xr pmc.p6 3 ,
.Xr pmc.soft 3 ,
.Xr pmc.tsc 3 ,
+.Xr pmc_allocate 3 ,
+.Xr pmc_attach 3 ,
+.Xr pmc_capabilities 3 ,
+.Xr pmc_configure_logfile 3 ,
+.Xr pmc_disable 3 ,
+.Xr pmc_event_names_of_class 3 ,
+.Xr pmc_get_driver_stats 3 ,
+.Xr pmc_get_msr 3 ,
+.Xr pmc_init 3 ,
+.Xr pmc_name_of_capability 3 ,
+.Xr pmc_read 3 ,
+.Xr pmc_set 3 ,
+.Xr pmc_start 3 ,
.Xr pmclog 3 ,
.Xr hwpmc 4 ,
.Xr pmccontrol 8 ,
Property changes on: trunk/lib/libpmc/pmc.3
___________________________________________________________________
Added: svn:keywords
## -0,0 +1 ##
+MidnightBSD=%H
\ No newline at end of property
Modified: trunk/lib/libpmc/pmc.atom.3
===================================================================
--- trunk/lib/libpmc/pmc.atom.3 2018-06-09 19:22:04 UTC (rev 10652)
+++ trunk/lib/libpmc/pmc.atom.3 2018-06-09 19:23:10 UTC (rev 10653)
@@ -1,3 +1,4 @@
+.\" $MidnightBSD$
.\" Copyright (c) 2008 Joseph Koshy. All rights reserved.
.\"
.\" Redistribution and use in source and binary forms, with or without
@@ -21,9 +22,9 @@
.\" OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
.\" SUCH DAMAGE.
.\"
-.\" $FreeBSD: release/9.2.0/lib/libpmc/pmc.atom.3 236238 2012-05-29 14:50:21Z fabient $
+.\" $FreeBSD: stable/10/lib/libpmc/pmc.atom.3 266911 2014-05-31 00:40:13Z hiren $
.\"
-.Dd November 12, 2008
+.Dd March 20, 2014
.Dt PMC.ATOM 3
.Os
.Sh NAME
@@ -1168,6 +1169,7 @@
.El
.Sh SEE ALSO
.Xr pmc 3 ,
+.Xr pmc.atomsilvermont 3 ,
.Xr pmc.core 3 ,
.Xr pmc.core2 3 ,
.Xr pmc.iaf 3 ,
Property changes on: trunk/lib/libpmc/pmc.atom.3
___________________________________________________________________
Added: svn:keywords
## -0,0 +1 ##
+MidnightBSD=%H
\ No newline at end of property
Added: trunk/lib/libpmc/pmc.atomsilvermont.3
===================================================================
--- trunk/lib/libpmc/pmc.atomsilvermont.3 (rev 0)
+++ trunk/lib/libpmc/pmc.atomsilvermont.3 2018-06-09 19:23:10 UTC (rev 10653)
@@ -0,0 +1,538 @@
+.\" $MidnightBSD$
+.\" Copyright (c) 2014 Hiren Panchasara <hiren at FreeBSD.org>
+.\" All rights reserved.
+.\"
+.\" Redistribution and use in source and binary forms, with or without
+.\" modification, are permitted provided that the following conditions
+.\" are met:
+.\" 1. Redistributions of source code must retain the above copyright
+.\" notice, this list of conditions and the following disclaimer.
+.\" 2. Redistributions in binary form must reproduce the above copyright
+.\" notice, this list of conditions and the following disclaimer in the
+.\" documentation and/or other materials provided with the distribution.
+.\"
+.\" THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+.\" ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+.\" IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+.\" ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+.\" FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+.\" DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+.\" OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+.\" HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+.\" LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+.\" OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+.\" SUCH DAMAGE.
+.\"
+.\" $FreeBSD: stable/10/lib/libpmc/pmc.atomsilvermont.3 321225 2017-07-19 18:23:49Z ngie $
+.\"
+.Dd April 6, 2017
+.Dt PMC.ATOMSILVERMONT 3
+.Os
+.Sh NAME
+.Nm pmc.atomsilvermont
+.Nd measurement events for
+.Tn Intel
+.Tn Atom Silvermont
+family CPUs
+.Sh LIBRARY
+.Lb libpmc
+.Sh SYNOPSIS
+.In pmc.h
+.Sh DESCRIPTION
+.Tn Intel
+.Tn Atom Silvermont
+CPUs contain PMCs conforming to version 3 of the
+.Tn Intel
+performance measurement architecture.
+These CPUs contains two classes of PMCs:
+.Bl -tag -width "Li PMC_CLASS_IAP"
+.It Li PMC_CLASS_IAF
+Fixed-function counters that count only one hardware event per counter.
+.It Li PMC_CLASS_IAP
+Programmable counters that may be configured to count one of a defined
+set of hardware events.
+.El
+.Pp
+The number of PMCs available in each class and their widths need to be
+determined at run time by calling
+.Xr pmc_cpuinfo 3 .
+.Pp
+Intel Atom Silvermont PMCs are documented in
+.Rs
+.%B "Intel 64 and IA-32 Intel(R) Architecture Software Developer's Manual"
+.%T "Combined Volumes"
+.%N "Order Number 325462-050US"
+.%D February 2014
+.%Q "Intel Corporation"
+.Re
+.Ss ATOM SILVERMONT FIXED FUNCTION PMCS
+These PMCs and their supported events are documented in
+.Xr pmc.iaf 3 .
+.Ss ATOM SILVERMONT PROGRAMMABLE PMCS
+The programmable PMCs support the following capabilities:
+.Bl -column "PMC_CAP_INTERRUPT" "Support"
+.It Em Capability Ta Em Support
+.It PMC_CAP_CASCADE Ta \&No
+.It PMC_CAP_EDGE Ta Yes
+.It PMC_CAP_INTERRUPT Ta Yes
+.It PMC_CAP_INVERT Ta Yes
+.It PMC_CAP_READ Ta Yes
+.It PMC_CAP_PRECISE Ta \&No
+.It PMC_CAP_SYSTEM Ta Yes
+.It PMC_CAP_TAGGING Ta \&No
+.It PMC_CAP_THRESHOLD Ta Yes
+.It PMC_CAP_USER Ta Yes
+.It PMC_CAP_WRITE Ta Yes
+.El
+.Ss Event Qualifiers
+Event specifiers for these PMCs support the following common
+qualifiers:
+.Bl -tag -width indent
+.It Li any
+Count matching events seen on any logical processor in a package.
+.It Li cmask= Ns Ar value
+Configure the PMC to increment only if the number of configured
+events measured in a cycle is greater than or equal to
+.Ar value .
+.It Li edge
+Configure the PMC to count the number of de-asserted to asserted
+transitions of the conditions expressed by the other qualifiers.
+If specified, the counter will increment only once whenever a
+condition becomes true, irrespective of the number of clocks during
+which the condition remains true.
+.It Li inv
+Invert the sense of comparison when the
+.Dq Li cmask
+qualifier is present, making the counter increment when the number of
+events per cycle is less than the value specified by the
+.Dq Li cmask
+qualifier.
+.It Li os
+Configure the PMC to count events happening at processor privilege
+level 0.
+.It Li usr
+Configure the PMC to count events occurring at privilege levels 1, 2
+or 3.
+.El
+.Pp
+If neither of the
+.Dq Li os
+or
+.Dq Li usr
+qualifiers are specified, the default is to enable both.
+.Pp
+Events that require core-specificity to be specified use a
+additional qualifier
+.Dq Li core= Ns Ar core ,
+where argument
+.Ar core
+is one of:
+.Bl -tag -width indent
+.It Li all
+Measure event conditions on all cores.
+.It Li this
+Measure event conditions on this core.
+.El
+.Pp
+The default is
+.Dq Li this .
+.Pp
+Events that require an agent qualifier to be specified use an
+additional qualifier
+.Dq Li agent= Ns agent ,
+where argument
+.Ar agent
+is one of:
+.Bl -tag -width indent
+.It Li this
+Measure events associated with this bus agent.
+.It Li any
+Measure events caused by any bus agent.
+.El
+.Pp
+The default is
+.Dq Li this .
+.Pp
+Events that require a hardware prefetch qualifier to be specified use an
+additional qualifier
+.Dq Li prefetch= Ns Ar prefetch ,
+where argument
+.Ar prefetch
+is one of:
+.Bl -tag -width "exclude"
+.It Li both
+Include all prefetches.
+.It Li only
+Only count hardware prefetches.
+.It Li exclude
+Exclude hardware prefetches.
+.El
+.Pp
+The default is
+.Dq Li both .
+.Pp
+Events that require a cache coherence qualifier to be specified use an
+additional qualifier
+.Dq Li cachestate= Ns Ar state ,
+where argument
+.Ar state
+contains one or more of the following letters:
+.Bl -tag -width indent
+.It Li e
+Count cache lines in the exclusive state.
+.It Li i
+Count cache lines in the invalid state.
+.It Li m
+Count cache lines in the modified state.
+.It Li s
+Count cache lines in the shared state.
+.El
+.Pp
+The default is
+.Dq Li eims .
+.Pp
+Events that require a snoop response qualifier to be specified use an
+additional qualifier
+.Dq Li snoopresponse= Ns Ar response ,
+where argument
+.Ar response
+comprises of the following keywords separated by
+.Dq +
+signs:
+.Bl -tag -width indent
+.It Li clean
+Measure CLEAN responses.
+.It Li hit
+Measure HIT responses.
+.It Li hitm
+Measure HITM responses.
+.El
+.Pp
+The default is to measure all the above responses.
+.Pp
+Events that require a snoop type qualifier use an additional qualifier
+.Dq Li snooptype= Ns Ar type ,
+where argument
+.Ar type
+comprises the one of the following keywords:
+.Bl -tag -width indent
+.It Li cmp2i
+Measure CMP2I snoops.
+.It Li cmp2s
+Measure CMP2S snoops.
+.El
+.Pp
+The default is to measure both snoops.
+.Ss Event Specifiers (Programmable PMCs)
+Atom Silvermont programmable PMCs support the following events:
+.Bl -tag -width indent
+.It Li REHABQ.LD_BLOCK_ST_FORWARD
+.Pq Event 03H , Umask 01H
+The number of retired loads that were
+prohibited from receiving forwarded data from the store
+because of address mismatch.
+.It Li REHABQ.LD_BLOCK_STD_NOTREADY
+.Pq Event 03H , Umask 02H
+The cases where a forward was technically possible,
+but did not occur because the store data was not available
+at the right time.
+.It Li REHABQ.ST_SPLITS
+.Pq Event 03H , Umask 04H
+The number of retire stores that experienced.
+cache line boundary splits.
+.It Li REHABQ.LD_SPLITS
+.Pq Event 03H , Umask 08H
+The number of retire loads that experienced.
+cache line boundary splits.
+.It Li REHABQ.LOCK
+.Pq Event 03H , Umask 10H
+The number of retired memory operations with lock semantics.
+These are either implicit locked instructions such as the
+XCHG instruction or instructions with an explicit LOCK
+prefix (0xF0).
+.It Li REHABQ.STA_FULL
+.Pq Event 03H , Umask 20H
+The number of retired stores that are delayed
+because there is not a store address buffer available.
+.It Li REHABQ.ANY_LD
+.Pq Event 03H , Umask 40H
+The number of load uops reissued from Rehabq.
+.It Li REHABQ.ANY_ST
+.Pq Event 03H , Umask 80H
+The number of store uops reissued from Rehabq.
+.It Li MEM_UOPS_RETIRED.L1_MISS_LOADS
+.Pq Event 04H , Umask 01H
+The number of load ops retired that miss in L1
+Data cache.
+Note that prefetch misses will not be counted.
+.It Li MEM_UOPS_RETIRED.L2_HIT_LOADS
+.Pq Event 04H , Umask 02H
+The number of load micro-ops retired that hit L2.
+.It Li MEM_UOPS_RETIRED.L2_MISS_LOADS
+.Pq Event 04H , Umask 04H
+The number of load micro-ops retired that missed L2.
+.It Li MEM_UOPS_RETIRED.DTLB_MISS_LOADS
+.Pq Event 04H , Umask 08H
+The number of load ops retired that had DTLB miss.
+.It Li MEM_UOPS_RETIRED.UTLB_MISS
+.Pq Event 04H , Umask 10H
+The number of load ops retired that had UTLB miss.
+.It Li MEM_UOPS_RETIRED.HITM
+.Pq Event 04H , Umask 20H
+The number of load ops retired that got data
+from the other core or from the other module.
+.It Li MEM_UOPS_RETIRED.ALL_LOADS
+.Pq Event 04H , Umask 40H
+The number of load ops retired.
+.It Li MEM_UOP_RETIRED.ALL_STORES
+.Pq Event 04H , Umask 80H
+The number of store ops retired.
+.It Li PAGE_WALKS.D_SIDE_CYCLES
+.Pq Event 05H , Umask 01H
+Every cycle when a D-side (walks due to a load) page walk is in progress.
+Page walk duration divided by number of page walks is the average duration of
+page-walks.
+Edge trigger bit must be cleared.
+Set Edge to count the number of page walks.
+.It Li PAGE_WALKS.I_SIDE_CYCLES
+.Pq Event 05H , Umask 02H
+Every cycle when a I-side (walks due to an instruction fetch) page walk is in
+progress.
+Page walk duration divided by number of page walks is the average duration of
+page-walks.
+.It Li PAGE_WALKS.WALKS
+.Pq Event 05H , Umask 03H
+The number of times a data (D) page walk or an instruction (I) page walk is
+completed or started.
+Since a page walk implies a TLB miss, the number of TLB misses can be counted
+by counting the number of pagewalks.
+.It Li LONGEST_LAT_CACHE.MISS
+.Pq Event 2EH , Umask 41H
+the total number of L2 cache references and the number of L2 cache misses
+respectively.
+L3 is not supported in Silvermont microarchitecture.
+.It Li LONGEST_LAT_CACHE.REFERENCE
+.Pq Event 2EH , Umask 4FH
+The number of requests originating from the core that
+references a cache line in the L2 cache.
+L3 is not supported in Silvermont microarchitecture.
+.It Li L2_REJECT_XQ.ALL
+.Pq Event 30H , Umask 00H
+The number of demand and prefetch
+transactions that the L2 XQ rejects due to a full or near full
+condition which likely indicates back pressure from the IDI link.
+The XQ may reject transactions from the L2Q (non-cacheable
+requests), BBS (L2 misses) and WOB (L2 write-back victims)
+.It Li CORE_REJECT_L2Q.ALL
+.Pq Event 31H , Umask 00H
+The number of demand and L1 prefetcher
+requests rejected by the L2Q due to a full or nearly full condition which
+likely indicates back pressure from L2Q.
+It also counts requests that would have gone directly to the XQ, but are
+rejected due to a full or nearly full condition, indicating back pressure from
+the IDI link.
+The L2Q may also reject transactions from a core to insure fairness between
+cores, or to delay a core's dirty eviction when the address conflicts incoming
+external snoops.
+(Note that L2 prefetcher requests that are dropped are not counted by this
+event).
+.It Li CPU_CLK_UNHALTED.CORE_P
+.Pq Event 3CH , Umask 00H
+The number of core cycles while the core is not in a halt state.
+The core enters the halt state when it is running the HLT instruction.
+In mobile systems the core frequency may change from time to time.
+For this reason this event may have a changing ratio with regards to time.
+.It Li CPU_CLK_UNHALTED.REF_P
+.Pq Event 3CH , Umask 01H
+The number of reference cycles that the core is not in a halt state.
+The core enters the halt state when it is running the HLT instruction.
+In mobile systems the core frequency may change from time.
+This event is not affected by core frequency changes but counts as if the core
+is running at the maximum frequency all the time.
+.It Li ICACHE.HIT
+.Pq Event 80H , Umask 01H
+The number of instruction fetches from the instruction cache.
+.It Li ICACHE.MISSES
+.Pq Event 80H , Umask 02H
+The number of instruction fetches that miss the Instruction cache or produce
+memory requests.
+This includes uncacheable fetches.
+An instruction fetch miss is counted only once and not once for every cycle
+it is outstanding.
+.It Li ICACHE.ACCESSES
+.Pq Event 80H , Umask 03H
+The number of instruction fetches, including uncacheable fetches.
+.It Li NIP_STALL.ICACHE_MISS
+.Pq Event B6H , Umask 04H
+The number of cycles the NIP stalls because of an icache miss.
+This is a cumulative count of cycles the NIP stalled for all
+icache misses.
+.It Li OFFCORE_RESPONSE_0
+.Pq Event B7H , Umask 01H
+Requires MSR_OFFCORE_RESP0 to specify request type and response.
+.It Li OFFCORE_RESPONSE_1
+.Pq Event B7H , Umask 02H
+Requires MSR_OFFCORE_RESP to specify request type and response.
+.It Li INST_RETIRED.ANY_P
+.Pq Event C0H , Umask 00H
+The number of instructions that retire execution.
+For instructions that consist of multiple micro-ops, this event counts the
+retirement of the last micro-op of the instruction.
+The counter continues counting during hardware interrupts, traps, and inside
+interrupt handlers.
+.It Li UOPS_RETIRED.MS
+.Pq Event C2H , Umask 01H
+The number of micro-ops retired that were supplied from MSROM.
+.It Li UOPS_RETIRED.ALL
+.Pq Event C2H , Umask 10H
+The number of micro-ops retired.
+.It Li MACHINE_CLEARS.SMC
+.Pq Event C3H , Umask 01H
+The number of times that a program writes to a code section.
+Self-modifying code causes a severe penalty in all Intel
+architecture processors.
+.It Li MACHINE_CLEARS.MEMORY_ORDERING
+.Pq Event C3H , Umask 02H
+The number of times that pipeline was cleared due to memory
+ordering issues.
+.It Li MACHINE_CLEARS.FP_ASSIST
+.Pq Event C3H , Umask 04H
+The number of times that pipeline stalled due to FP operations
+needing assists.
+.It Li MACHINE_CLEARS.ALL
+.Pq Event C3H , Umask 08H
+The number of times that pipeline stalled due to due to any causes
+(including SMC, MO, FP assist, etc).
+.It Li BR_INST_RETIRED.ALL_BRANCHES
+.Pq Event C4H , Umask 00H
+The number of branch instructions retired.
+.It Li BR_INST_RETIRED.JCC
+.Pq Event C4H , Umask 7EH
+The number of branch instructions retired that were conditional
+jumps.
+.It Li BR_INST_RETIRED.FAR_BRANCH
+.Pq Event C4H , Umask BFH
+The number of far branch instructions retired.
+.It Li BR_INST_RETIRED.NON_RETURN_IND
+.Pq Event C4H , Umask EBH
+The number of branch instructions retired that were near indirect
+call or near indirect jmp.
+.It Li BR_INST_RETIRED.RETURN
+.Pq Event C4H , Umask F7H
+The number of near RET branch instructions retired.
+.It Li BR_INST_RETIRED.CALL
+.Pq Event C4H , Umask F9H
+The number of near CALL branch instructions retired.
+.It Li BR_INST_RETIRED.IND_CALL
+.Pq Event C4H , Umask FBH
+The number of near indirect CALL branch instructions retired.
+.It Li BR_INST_RETIRED.REL_CALL
+.Pq Event C4H , Umask FDH
+The number of near relative CALL branch instructions retired.
+.It Li BR_INST_RETIRED.TAKEN_JCC
+.Pq Event C4H , Umask FEH
+The number of branch instructions retired that were conditional
+jumps and predicted taken.
+.It Li BR_MISP_RETIRED.ALL_BRANCHES
+.Pq Event C5H , Umask 00H
+The number of mispredicted branch instructions retired.
+.It Li BR_MISP_RETIRED.JCC
+.Pq Event C5H , Umask 7EH
+The number of mispredicted branch instructions retired that were
+conditional jumps.
+.It Li BR_MISP_RETIRED.FAR
+.Pq Event C5H , Umask BFH
+The number of mispredicted far branch instructions retired.
+.It Li BR_MISP_RETIRED.NON_RETURN_IND
+.Pq Event C5H , Umask EBH
+The number of mispredicted branch instructions retired that were
+near indirect call or near indirect jmp.
+.It Li BR_MISP_RETIRED.RETURN
+.Pq Event C5H , Umask F7H
+The number of mispredicted near RET branch instructions retired.
+.It Li BR_MISP_RETIRED.CALL
+.Pq Event C5H , Umask F9H
+The number of mispredicted near CALL branch instructions retired.
+.It Li BR_MISP_RETIRED.IND_CALL
+.Pq Event C5H , Umask FBH
+The number of mispredicted near indirect CALL branch instructions
+retired.
+.It Li BR_MISP_RETIRED.REL_CALL
+.Pq Event C5H , Umask FDH
+The number of mispredicted near relative CALL branch instructions
+retired.
+.It Li BR_MISP_RETIRED.TAKEN_JCC
+.Pq Event C5H , Umask FEH
+The number of mispredicted branch instructions retired that were
+conditional jumps and predicted taken.
+.It Li NO_ALLOC_CYCLES.ROB_FULL
+.Pq Event CAH , Umask 01H
+The number of cycles when no uops are allocated and the ROB is full
+(less than 2 entries available).
+.It Li NO_ALLOC_CYCLES.RAT_STALL
+.Pq Event CAH , Umask 20H
+The number of cycles when no uops are allocated and a RATstall is
+asserted.
+.It Li NO_ALLOC_CYCLES.ALL
+.Pq Event CAH , Umask 3FH
+The number of cycles when the front-end does not provide any
+instructions to be allocated for any reason.
+.It Li NO_ALLOC_CYCLES.NOT_DELIVERED
+.Pq Event CAH , Umask 50H
+The number of cycles when the front-end does not provide any
+instructions to be allocated but the back end is not stalled.
+.It Li RS_FULL_STALL.MEC
+.Pq Event CBH , Umask 01H
+The number of cycles the allocation pipe line stalled due to
+the RS for the MEC cluster is full.
+.It Li RS_FULL_STALL.ALL
+.Pq Event CBH , Umask 1FH
+The number of cycles that the allocation pipe line stalled due
+to any one of the RS is full.
+.It Li CYCLES_DIV_BUSY.ANY
+.Pq Event CDH , Umask 01H
+The number of cycles the divider is busy.
+.It Li BACLEARS.ALL
+.Pq Event E6H , Umask 01H
+The number of baclears for any type of branch.
+.It Li BACLEARS.RETURN
+.Pq Event E6H , Umask 08H
+The number of baclears for return branches.
+.It Li BACLEARS.COND
+.Pq Event E6H , Umask 10H
+The number of baclears for conditional branches.
+.It Li MS_DECODED.MS_ENTRY
+.Pq Event E7H , Umask 01H)
+The number of times the MSROM starts a flow of UOPS.
+.El
+.Sh SEE ALSO
+.Xr pmc 3 ,
+.Xr pmc.atom 3 ,
+.Xr pmc.core 3 ,
+.Xr pmc.core2 3 ,
+.Xr pmc.iaf 3 ,
+.Xr pmc.k7 3 ,
+.Xr pmc.k8 3 ,
+.Xr pmc.p4 3 ,
+.Xr pmc.p5 3 ,
+.Xr pmc.p6 3 ,
+.Xr pmc.soft 3 ,
+.Xr pmc.tsc 3 ,
+.Xr pmc_cpuinfo 3 ,
+.Xr pmclog 3 ,
+.Xr hwpmc 4
+.Sh HISTORY
+The
+.Nm pmc
+library first appeared in
+.Fx 6.0 .
+.Sh AUTHORS
+The
+.Lb libpmc
+library was written by
+.An "Joseph Koshy"
+.Aq jkoshy at FreeBSD.org .
+The support for the Atom Silvermont
+microarchitecture was written by
+.An "Hiren Panchasara"
+.Aq hiren at FreeBSD.org .
Property changes on: trunk/lib/libpmc/pmc.atomsilvermont.3
___________________________________________________________________
Added: svn:eol-style
## -0,0 +1 ##
+native
\ No newline at end of property
Added: svn:keywords
## -0,0 +1 ##
+MidnightBSD=%H
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+text/plain
\ No newline at end of property
Modified: trunk/lib/libpmc/pmc.core.3
===================================================================
--- trunk/lib/libpmc/pmc.core.3 2018-06-09 19:22:04 UTC (rev 10652)
+++ trunk/lib/libpmc/pmc.core.3 2018-06-09 19:23:10 UTC (rev 10653)
@@ -1,3 +1,4 @@
+.\" $MidnightBSD$
.\" Copyright (c) 2008 Joseph Koshy. All rights reserved.
.\"
.\" Redistribution and use in source and binary forms, with or without
@@ -21,7 +22,7 @@
.\" OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
.\" SUCH DAMAGE.
.\"
-.\" $FreeBSD: release/9.2.0/lib/libpmc/pmc.core.3 236238 2012-05-29 14:50:21Z fabient $
+.\" $FreeBSD: stable/10/lib/libpmc/pmc.core.3 233648 2012-03-29 05:02:12Z eadler $
.\"
.Dd November 12, 2008
.Dt PMC.CORE 3
@@ -180,7 +181,7 @@
The following event names are case insensitive.
Whitespace, hyphens and underscore characters in these names are
ignored.
-.Pp
+.Pp
Core PMCs support the following events:
.Bl -tag -width indent
.It Li BAClears
@@ -193,7 +194,7 @@
.It Li Br_BAC_Missp_Exec
.Pq Event 8AH , Umask 00H
The number of branch instructions executed that were mispredicted at
-the front end.
+the front end.
.It Li Br_Bogus
.Pq Event E4H , Umask 00H
The number of bogus branches.
Property changes on: trunk/lib/libpmc/pmc.core.3
___________________________________________________________________
Added: svn:keywords
## -0,0 +1 ##
+MidnightBSD=%H
\ No newline at end of property
Modified: trunk/lib/libpmc/pmc.core2.3
===================================================================
--- trunk/lib/libpmc/pmc.core2.3 2018-06-09 19:22:04 UTC (rev 10652)
+++ trunk/lib/libpmc/pmc.core2.3 2018-06-09 19:23:10 UTC (rev 10653)
@@ -1,3 +1,4 @@
+.\" $MidnightBSD$
.\" Copyright (c) 2008,2009 Joseph Koshy. All rights reserved.
.\"
.\" Redistribution and use in source and binary forms, with or without
@@ -21,7 +22,7 @@
.\" OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
.\" SUCH DAMAGE.
.\"
-.\" $FreeBSD: release/9.2.0/lib/libpmc/pmc.core2.3 236238 2012-05-29 14:50:21Z fabient $
+.\" $FreeBSD: stable/10/lib/libpmc/pmc.core2.3 233628 2012-03-28 20:58:30Z fabient $
.\"
.Dd June 8, 2009
.Dt PMC.CORE2 3
Property changes on: trunk/lib/libpmc/pmc.core2.3
___________________________________________________________________
Added: svn:keywords
## -0,0 +1 ##
+MidnightBSD=%H
\ No newline at end of property
Modified: trunk/lib/libpmc/pmc.corei7.3
===================================================================
--- trunk/lib/libpmc/pmc.corei7.3 2018-06-09 19:22:04 UTC (rev 10652)
+++ trunk/lib/libpmc/pmc.corei7.3 2018-06-09 19:23:10 UTC (rev 10653)
@@ -1,3 +1,4 @@
+.\" $MidnightBSD$
.\" Copyright (c) 2010 Fabien Thomas. All rights reserved.
.\"
.\" Redistribution and use in source and binary forms, with or without
@@ -21,7 +22,7 @@
.\" OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
.\" SUCH DAMAGE.
.\"
-.\" $FreeBSD: release/9.2.0/lib/libpmc/pmc.corei7.3 236238 2012-05-29 14:50:21Z fabient $
+.\" $FreeBSD: stable/10/lib/libpmc/pmc.corei7.3 233628 2012-03-28 20:58:30Z fabient $
.\"
.Dd March 24, 2010
.Dt PMC.COREI7 3
Property changes on: trunk/lib/libpmc/pmc.corei7.3
___________________________________________________________________
Added: svn:keywords
## -0,0 +1 ##
+MidnightBSD=%H
\ No newline at end of property
Modified: trunk/lib/libpmc/pmc.corei7uc.3
===================================================================
--- trunk/lib/libpmc/pmc.corei7uc.3 2018-06-09 19:22:04 UTC (rev 10652)
+++ trunk/lib/libpmc/pmc.corei7uc.3 2018-06-09 19:23:10 UTC (rev 10653)
@@ -1,3 +1,4 @@
+.\" $MidnightBSD$
.\" Copyright (c) 2010 Fabien Thomas. All rights reserved.
.\"
.\" Redistribution and use in source and binary forms, with or without
@@ -21,7 +22,7 @@
.\" OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
.\" SUCH DAMAGE.
.\"
-.\" $FreeBSD: release/9.2.0/lib/libpmc/pmc.corei7uc.3 236238 2012-05-29 14:50:21Z fabient $
+.\" $FreeBSD: stable/10/lib/libpmc/pmc.corei7uc.3 233628 2012-03-28 20:58:30Z fabient $
.\"
.Dd March 24, 2010
.Dt PMC.COREI7UC 3
Property changes on: trunk/lib/libpmc/pmc.corei7uc.3
___________________________________________________________________
Added: svn:keywords
## -0,0 +1 ##
+MidnightBSD=%H
\ No newline at end of property
Modified: trunk/lib/libpmc/pmc.h
===================================================================
--- trunk/lib/libpmc/pmc.h 2018-06-09 19:22:04 UTC (rev 10652)
+++ trunk/lib/libpmc/pmc.h 2018-06-09 19:23:10 UTC (rev 10653)
@@ -24,7 +24,7 @@
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*
- * $FreeBSD: release/9.2.0/lib/libpmc/pmc.h 229392 2012-01-03 16:35:00Z fabient $
+ * $FreeBSD: stable/10/lib/libpmc/pmc.h 294046 2016-01-14 22:02:21Z jtl $
*/
#ifndef _PMC_H_
@@ -37,14 +37,15 @@
* Driver statistics.
*/
struct pmc_driverstats {
- int pm_intr_ignored; /* #interrupts ignored */
- int pm_intr_processed; /* #interrupts processed */
- int pm_intr_bufferfull; /* #interrupts with ENOSPC */
- int pm_syscalls; /* #syscalls */
- int pm_syscall_errors; /* #syscalls with errors */
- int pm_buffer_requests; /* #buffer requests */
- int pm_buffer_requests_failed; /* #failed buffer requests */
- int pm_log_sweeps; /* #sample buffer processing passes */
+ unsigned int pm_intr_ignored; /* #interrupts ignored */
+ unsigned int pm_intr_processed; /* #interrupts processed */
+ unsigned int pm_intr_bufferfull; /* #interrupts with ENOSPC */
+ unsigned int pm_syscalls; /* #syscalls */
+ unsigned int pm_syscall_errors; /* #syscalls with errors */
+ unsigned int pm_buffer_requests; /* #buffer requests */
+ unsigned int pm_buffer_requests_failed; /* #failed buffer requests */
+ unsigned int pm_log_sweeps; /* #sample buffer processing
+ passes */
};
/*
@@ -99,7 +100,7 @@
int pmc_cpuinfo(const struct pmc_cpuinfo **_cpu_info);
int pmc_pmcinfo(int _cpu, struct pmc_pmcinfo **_pmc_info);
-const char *pmc_name_of_capability(uint32_t _c);
+const char *pmc_name_of_capability(enum pmc_caps _c);
const char *pmc_name_of_class(enum pmc_class _pc);
const char *pmc_name_of_cputype(enum pmc_cputype _cp);
const char *pmc_name_of_disposition(enum pmc_disp _pd);
Modified: trunk/lib/libpmc/pmc.haswell.3
===================================================================
--- trunk/lib/libpmc/pmc.haswell.3 2018-06-09 19:22:04 UTC (rev 10652)
+++ trunk/lib/libpmc/pmc.haswell.3 2018-06-09 19:23:10 UTC (rev 10653)
@@ -1,3 +1,4 @@
+.\" $MidnightBSD$
.\" Copyright (c) 2013 Hiren Panchasara <hiren.panchasara at gmail.com>
.\" All rights reserved.
.\"
@@ -22,7 +23,7 @@
.\" OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
.\" SUCH DAMAGE.
.\"
-.\" $FreeBSD: release/9.2.0/lib/libpmc/pmc.haswell.3 249655 2013-04-19 19:28:48Z hiren $
+.\" $FreeBSD: stable/10/lib/libpmc/pmc.haswell.3 320109 2017-06-19 15:20:30Z avg $
.\"
.Dd March 22, 2013
.Dt PMC.HASWELL 3
@@ -201,60 +202,60 @@
.Bl -tag -width indent
.It Li LD_BLOCKS.STORE_FORWARD
.Pq Event 03H , Umask 02H
-Loads blocked by overlapping with store buffer that
-cannot be forwarded.
+Loads blocked by overlapping with store buffer that
+cannot be forwarded.
.It Li MISALIGN_MEM_REF.LOADS
.Pq Event 05H , Umask 01H
-Speculative cache-line split load uops dispatched to
-L1D.
+Speculative cache-line split load uops dispatched to
+L1D.
.It Li MISALIGN_MEM_REF.STORES
.Pq Event 05H , Umask 02H
-Speculative cache-line split Store-address uops
-dispatched to L1D.
+Speculative cache-line split Store-address uops
+dispatched to L1D.
.It Li LD_BLOCKS_PARTIAL.ADDRESS_ALIAS
.Pq Event 07H , Umask 01H
-False dependencies in MOB due to partial compare
-on address.
+False dependencies in MOB due to partial compare
+on address.
.It Li DTLB_LOAD_MISSES.MISS_CAUSES_A_WALK
.Pq Event 08H , Umask 01H
-Misses in all TLB levels that cause a page walk of any
-page size.
+Misses in all TLB levels that cause a page walk of any
+page size.
.It Li DTLB_LOAD_MISSES.WALK_COMPLETED_4K
.Pq Event 08H , Umask 02H
-Completed page walks due to demand load misses
-that caused 4K page walks in any TLB levels.
+Completed page walks due to demand load misses
+that caused 4K page walks in any TLB levels.
.It Li DTLB_LOAD_MISSES.WALK_COMPLETED_2M_4K
.Pq Event 08H , Umask 02H
-Completed page walks due to demand load misses
-that caused 2M/4M page walks in any TLB levels.
+Completed page walks due to demand load misses
+that caused 2M/4M page walks in any TLB levels.
.It Li DTLB_LOAD_MISSES.WALK_COMPLETED
.Pq Event 08H , Umask 0EH
-Completed page walks in any TLB of any page size
-due to demand load misses
+Completed page walks in any TLB of any page size
+due to demand load misses
.It Li DTLB_LOAD_MISSES.WALK_DURATION
.Pq Event 08H , Umask 10H
-Cycle PMH is busy with a walk.
+Cycle PMH is busy with a walk.
.It Li DTLB_LOAD_MISSES.STLB_HIT_4K
.Pq Event 08H , Umask 20H
-Load misses that missed DTLB but hit STLB (4K).
+Load misses that missed DTLB but hit STLB (4K).
.It Li DTLB_LOAD_MISSES.STLB_HIT_2M
.Pq Event 08H , Umask 40H
-Load misses that missed DTLB but hit STLB (2M).
+Load misses that missed DTLB but hit STLB (2M).
.It Li DTLB_LOAD_MISSES.STLB_HIT
.Pq Event 08H , Umask 60H
Number of cache load STLB hits. No page walk.
.It Li DTLB_LOAD_MISSES.PDE_CACHE_MISS
.Pq Event 08H , Umask 80H
-DTLB demand load misses with low part of linear-to-
-physical address translation missed
+DTLB demand load misses with low part of linear-to-
+physical address translation missed
.It Li INT_MISC.RECOVERY_CYCLES
.Pq Event 0DH , Umask 03H
-Cycles waiting to recover after Machine Clears
-except JEClear. Set Cmask= 1.
+Cycles waiting to recover after Machine Clears
+except JEClear. Set Cmask= 1.
.It Li UOPS_ISSUED.ANY
.Pq Event 0EH , Umask 01H
-ncrements each cycle the # of Uops issued by the
-RAT to RS.
+ncrements each cycle the # of Uops issued by the
+RAT to RS.
Set Cmask = 1, Inv = 1, Any= 1to count stalled cycles
of this core.
.It Li UOPS_ISSUED.FLAGS_MERGE
@@ -278,7 +279,7 @@
.Pq Event 24H , Umask 41H
Demand Data Read requests that hit L2 cache.
.It Li L2_RQSTS.ALL_DEMAND_DATA_RD
-.Pq Event 24H , Umask E1H
+.Pq Event 24H , Umask E1H
Counts any demand and L1 HW prefetch data load
requests to L2.
.It Li L2_RQSTS.RFO_HIT
@@ -348,9 +349,9 @@
when not halted.
.It Li L1D_PEND_MISS.PENDING
.Pq Event 48H , Umask 01H
-Increments the number of outstanding L1D misses
-every cycle. Set Cmaks = 1 and Edge =1 to count
-occurrences.
+Increments the number of outstanding L1D misses
+every cycle. Set Cmaks = 1 and Edge =1 to count
+occurrences.
.It Li DTLB_STORE_MISSES.MISS_CAUSES_A_WALK
.Pq Event 49H , Umask 01H
Miss in all TLB levels causes an page walk of any
@@ -422,15 +423,15 @@
Cycles the RS is empty for the thread.
.It Li OFFCORE_REQUESTS_OUTSTANDING.DEMAND_DATA_RD
.Pq Event 60H , Umask 01H
-Offcore outstanding Demand Data Read transactions
+Offcore outstanding Demand Data Read transactions
in SQ to uncore. Set Cmask=1 to count cycles.
.It Li OFFCORE_REQUESTS_OUTSTANDING.DEMAND_CORE_RD
.Pq Event 60H , Umask 02H
-Offcore outstanding Demand code Read transactions
+Offcore outstanding Demand code Read transactions
in SQ to uncore. Set Cmask=1 to count cycles.
.It Li OFFCORE_REQUESTS_OUTSTANDING.DEMAND_RFO
.Pq Event 60H , Umask 04H
-Offcore outstanding RFO store transactions in SQ to
+Offcore outstanding RFO store transactions in SQ to
uncore. Set Cmask=1 to count cycles.
.It Li OFFCORE_REQUESTS_OUTSTANDING.ALL_DATA_RD
.Pq Event 60H , Umask 08H
@@ -449,7 +450,7 @@
Counts cycles the IDQ is empty.
.It Li IDQ.MITE_UOPS
.Pq Event 79H , Umask 04H
-Increment each cycle # of uops delivered to IDQ from
+Increment each cycle # of uops delivered to IDQ from
MITE path.
Set Cmask = 1 to count cycles.
.It Li IDQ.DSB_UOPS
@@ -459,14 +460,14 @@
Set Cmask = 1 to count cycles.
.It Li IDQ.MS_DSB_UOPS
.Pq Event 79H , Umask 10H
-Increment each cycle # of uops delivered to IDQ
-when MS_busy by DSB. Set Cmask = 1 to count
-cycles. Add Edge=1 to count # of delivery.
+Increment each cycle # of uops delivered to IDQ
+when MS_busy by DSB. Set Cmask = 1 to count
+cycles. Add Edge=1 to count # of delivery.
.It Li IDQ.MS_MITE_UOPS
.Pq Event 79H , Umask 20H
-ncrement each cycle # of uops delivered to IDQ
-when MS_busy by MITE. Set Cmask = 1 to count
-cycles.
+ncrement each cycle # of uops delivered to IDQ
+when MS_busy by MITE. Set Cmask = 1 to count
+cycles.
.It Li IDQ.MS_UOPS
.Pq Event 79H , Umask 30H
Increment each cycle # of uops delivered to IDQ from
@@ -474,163 +475,150 @@
cycles.
.It Li IDQ.ALL_DSB_CYCLES_ANY_UOPS
.Pq Event 79H , Umask 18H
-Counts cycles DSB is delivered at least one uops. Set
-Cmask = 1.
+Counts cycles DSB is delivered at least one uops. Set
+Cmask = 1.
.It Li IDQ.ALL_DSB_CYCLES_4_UOPS
.Pq Event 79H , Umask 18H
-Counts cycles DSB is delivered four uops. Set Cmask
+Counts cycles DSB is delivered four uops. Set Cmask
=4.
.It Li IDQ.ALL_MITE_CYCLES_ANY_UOPS
.Pq Event 79H , Umask 24H
-Counts cycles MITE is delivered at least one uops. Set
-Cmask = 1.
+Counts cycles MITE is delivered at least one uops. Set
+Cmask = 1.
.It Li IDQ.ALL_MITE_CYCLES_4_UOPS
.Pq Event 79H , Umask 24H
-Counts cycles MITE is delivered four uops. Set Cmask
+Counts cycles MITE is delivered four uops. Set Cmask
=4.
.It Li IDQ.MITE_ALL_UOPS
.Pq Event 79H , Umask 3CH
-# of uops delivered to IDQ from any path.
+# of uops delivered to IDQ from any path.
.It Li ICACHE.MISSES
.Pq Event 80H , Umask 02H
-Number of Instruction Cache, Streaming Buffer and
-Victim Cache Misses. Includes UC accesses.
+Number of Instruction Cache, Streaming Buffer and
+Victim Cache Misses. Includes UC accesses.
.It Li ITLB_MISSES.MISS_CAUSES_A_WALK
.Pq Event 85H , Umask 01H
-Misses in ITLB that causes a page walk of any page
-size.
+Misses in ITLB that causes a page walk of any page
+size.
.It Li ITLB_MISSES.WALK_COMPLETED_4K
.Pq Event 85H , Umask 02H
-Completed page walks due to misses in ITLB 4K page
-entries.
+Completed page walks due to misses in ITLB 4K page
+entries.
.It Li TLB_MISSES.WALK_COMPLETED_2M_4M
.Pq Event 85H , Umask 04H
-Completed page walks due to misses in ITLB 2M/4M
+Completed page walks due to misses in ITLB 2M/4M
page entries.
.It Li ITLB_MISSES.WALK_COMPLETED
.Pq Event 85H , Umask 0EH
-Completed page walks in ITLB of any page size.
+Completed page walks in ITLB of any page size.
.It Li ITLB_MISSES.WALK_DURATION
.Pq Event 85H , Umask 10H
-Cycle PMH is busy with a walk.
+Cycle PMH is busy with a walk.
.It Li ITLB_MISSES.STLB_HIT_4K
.Pq Event 85H , Umask 20H
-ITLB misses that hit STLB (4K).
+ITLB misses that hit STLB (4K).
.It Li ITLB_MISSES.STLB_HIT_2M
.Pq Event 85H , Umask 40H
-ITLB misses that hit STLB (2K).
+ITLB misses that hit STLB (2K).
.It Li ITLB_MISSES.STLB_HIT
.Pq Event 85H , Umask 60H
-TLB misses that hit STLB. No page walk.
+TLB misses that hit STLB. No page walk.
.It Li ILD_STALL.LCP
.Pq Event 87H , Umask 01H
-Stalls caused by changing prefix length of the
+Stalls caused by changing prefix length of the
instruction.
.It Li ILD_STALL.IQ_FULL
.Pq Event 87H , Umask 04H
-Stall cycles due to IQ is full.
-.It Li BR_INST_EXEC.COND
-.Pq Event 88H , Umask 01H
-Qualify conditional near branch instructions
-executed, but not necessarily retired.
+Stall cycles due to IQ is full.
+.It Li BR_INST_EXEC.NONTAKEN_COND
+.Pq Event 88H , Umask 41H
+Count conditional near branch instructions that were executed (but not
+necessarily retired) and not taken.
+.It Li BR_INST_EXEC.TAKEN_COND
+.Pq Event 88H , Umask 81H
+Count conditional near branch instructions that were executed (but not
+necessarily retired) and taken.
.It Li BR_INST_EXEC.DIRECT_JMP
-.Pq Event 88H , Umask 02H
-Qualify all unconditional near branch instructions
-excluding calls and indirect branches.
+.Pq Event 88H , Umask 82H
+Count all unconditional near branch instructions excluding calls and
+indirect branches.
.It Li BR_INST_EXEC.INDIRECT_JMP_NON_CALL_RET
-.Pq Event 88H , Umask 04H
-Qualify executed indirect near branch instructions
-that are not calls nor returns.
+.Pq Event 88H , Umask 84H
+Count executed indirect near branch instructions that are not calls nor
+returns.
.It Li BR_INST_EXEC.RETURN_NEAR
-.Pq Event 88H , Umask 08H
-Qualify indirect near branches that have a return
-mnemonic.
+.Pq Event 88H , Umask 88H
+Count indirect near branches that have a return mnemonic.
.It Li BR_INST_EXEC.DIRECT_NEAR_CALL
-.Pq Event 88H , Umask 10H
-Qualify unconditional near call branch instructions,
-excluding non call branch, executed.
+.Pq Event 88H , Umask 90H
+Count unconditional near call branch instructions, excluding non call
+branch, executed.
.It Li BR_INST_EXEC.INDIRECT_NEAR_CALL
-.Pq Event 88H , Umask 20H
-Qualify indirect near calls, including both register and
-memory indirect, executed.
-.It Li BR_INST_EXEC.NONTAKEN
-.Pq Event 88H , Umask 40H
-Qualify non-taken near branches executed.
-.It Li BR_INST_EXEC.TAKEN
-.Pq Event 88H , Umask 80H
-Qualify taken near branches executed. Must combine
-with 01H,02H, 04H, 08H, 10H, 20H.
+.Pq Event 88H , Umask A0H
+Count indirect near calls, including both register and memory indirect,
+executed.
.It Li BR_INST_EXEC.ALL_BRANCHES
.Pq Event 88H , Umask FFH
-Counts all near executed branches (not necessarily
-retired).
-.It Li BR_MISP_EXEC.COND
-.Pq Event 89H , Umask 01H
-Qualify conditional near branch instructions
-mispredicted.
+Counts all near executed branches (not necessarily retired).
+.It Li BR_MISP_EXEC.NONTAKEN_COND
+.Pq Event 89H , Umask 41H
+Count conditional near branch instructions mispredicted as nontaken.
+.It Li BR_MISP_EXEC.TAKEN_COND
+.Pq Event 89H , Umask 81H
+Count conditional near branch instructions mispredicted as taken.
.It Li BR_MISP_EXEC.INDIRECT_JMP_NON_CALL_RET
-.Pq Event 89H , Umask 04H
-Qualify mispredicted indirect near branch
-instructions that are not calls nor returns.
+.Pq Event 89H , Umask 84H
+Count mispredicted indirect near branch instructions that are not calls
+nor returns.
.It Li BR_MISP_EXEC.RETURN_NEAR
-.Pq Event 89H , Umask 08H
-Qualify mispredicted indirect near branches that
-have a return mnemonic.
+.Pq Event 89H , Umask 88H
+Count mispredicted indirect near branches that have a return mnemonic.
.It Li BR_MISP_EXEC.DIRECT_NEAR_CALL
-.Pq Event 89H , Umask 10H
-Qualify mispredicted unconditional near call branch
-instructions, excluding non call branch, executed.
+.Pq Event 89H , Umask 90H
+Count mispredicted unconditional near call branch instructions, excluding
+non call branch, executed.
.It Li BR_MISP_EXEC.INDIRECT_NEAR_CALL
-.Pq Event 89H , Umask 20H
-Qualify mispredicted indirect near calls, including
-both register and memory indirect, executed.
-.It Li BR_MISP_EXEC.NONTAKEN
-.Pq Event 89H , Umask 40H
-Qualify mispredicted non-taken near branches
-executed.
-.It Li BR_MISP_EXEC.TAKEN
-.Pq Event 89H , Umask 80H
-Qualify mispredicted taken near branches executed.
-Must combine with 01H,02H, 04H, 08H, 10H, 20H.
+.Pq Event 89H , Umask A0H
+Count mispredicted indirect near calls, including both register and memory
+indirect, executed.
.It Li BR_MISP_EXEC.ALL_BRANCHES
.Pq Event 89H , Umask FFH
-Counts all near executed branches (not necessarily
-retired).
+Counts all mispredicted near executed branches (not necessarily retired).
.It Li IDQ_UOPS_NOT_DELIVERED.CORE
.Pq Event 9CH , Umask 01H
-Count number of non-delivered uops to RAT per
-thread.
+Count number of non-delivered uops to RAT per
+thread.
.It Li UOPS_EXECUTED_PORT.PORT_0
.Pq Event A1H , Umask 01H
-Cycles which a Uop is dispatched on port 0 in this
-thread.
+Cycles which a Uop is dispatched on port 0 in this
+thread.
.It Li UOPS_EXECUTED_PORT.PORT_1
.Pq Event A1H , Umask 02H
-Cycles which a Uop is dispatched on port 1 in this
+Cycles which a Uop is dispatched on port 1 in this
thread.
.It Li UOPS_EXECUTED_PORT.PORT_2
.Pq Event A1H , Umask 04H
-Cycles which a Uop is dispatched on port 2 in this
+Cycles which a Uop is dispatched on port 2 in this
thread.
.It Li UOPS_EXECUTED_PORT.PORT_3
.Pq Event A1H , Umask 08H
-Cycles which a Uop is dispatched on port 3 in this
+Cycles which a Uop is dispatched on port 3 in this
thread.
.It Li UOPS_EXECUTED_PORT.PORT_4
.Pq Event A1H , Umask 10H
-Cycles which a Uop is dispatched on port 4 in this
+Cycles which a Uop is dispatched on port 4 in this
thread.
.It Li UOPS_EXECUTED_PORT.PORT_5
.Pq Event A1H , Umask 20H
-Cycles which a Uop is dispatched on port 5 in this
+Cycles which a Uop is dispatched on port 5 in this
thread.
.It Li UOPS_EXECUTED_PORT.PORT_6
.Pq Event A1H , Umask 40H
-Cycles which a Uop is dispatched on port 6 in this
+Cycles which a Uop is dispatched on port 6 in this
thread.
.It Li UOPS_EXECUTED_PORT.PORT_7
.Pq Event A1H , Umask 80H
-Cycles which a Uop is dispatched on port 7 in this
+Cycles which a Uop is dispatched on port 7 in this
thread.
.It Li RESOURCE_STALLS.ANY
.Pq Event A2H , Umask 01H
@@ -673,7 +661,7 @@
Demand code read requests sent to uncore.
.It Li OFFCORE_REQUESTS.DEMAND_RFO
.Pq Event B0H , Umask 04H
-Demand RFO read requests sent to uncore, including
+Demand RFO read requests sent to uncore, including
regular RFOs, locks, ItoM.
.It Li OFFCORE_REQUESTS.ALL_DATA_RD
.Pq Event B0H , Umask 08H
@@ -723,48 +711,48 @@
Count number of STLB flush attempts.
.It Li INST_RETIRED.ANY_P
.Pq Event C0H , Umask 00H
-Number of instructions at retirement.
+Number of instructions at retirement.
.It Li INST_RETIRED.ALL
.Pq Event C0H , Umask 01H
-Precise instruction retired event with HW to reduce
-effect of PEBS shadow in IP distribution.
+Precise instruction retired event with HW to reduce
+effect of PEBS shadow in IP distribution.
.It Li OTHER_ASSISTS.AVX_TO_SSE
.Pq Event C1H , Umask 08H
-Number of transitions from AVX-256 to legacy SSE
-when penalty applicable.
+Number of transitions from AVX-256 to legacy SSE
+when penalty applicable.
.It Li OTHER_ASSISTS.SSE_TO_AVX
.Pq Event C1H , Umask 10H
-Number of transitions from SSE to AVX-256 when
-penalty applicable.
+Number of transitions from SSE to AVX-256 when
+penalty applicable.
.It Li OTHER_ASSISTS.ANY_WB_ASSIST
.Pq Event C1H , Umask 40H
-Number of microcode assists invoked by HW upon
-uop writeback.
+Number of microcode assists invoked by HW upon
+uop writeback.
.It Li UOPS_RETIRED.ALL
.Pq Event C2H , Umask 01H
-Counts the number of micro-ops retired, Use
-cmask=1 and invert to count active cycles or stalled
-cycles.
+Counts the number of micro-ops retired, Use
+cmask=1 and invert to count active cycles or stalled
+cycles.
.It Li UOPS_RETIRED.RETIRE_SLOTS
.Pq Event C2H , Umask 02H
-Counts the number of retirement slots used each
+Counts the number of retirement slots used each
cycle.
.It Li MACHINE_CLEARS.MEMORY_ORDERING
.Pq Event C3H , Umask 02H
-Counts the number of machine clears due to memory
-order conflicts.
+Counts the number of machine clears due to memory
+order conflicts.
.It Li MACHINE_CLEARS.SMC
.Pq Event C3H , Umask 04H
-Number of self-modifying-code machine clears
+Number of self-modifying-code machine clears
detected.
.It Li MACHINE_CLEARS.MASKMOV
.Pq Event C3H , Umask 20H
-Counts the number of executed AVX masked load
-operations that refer to an illegal address range with
-the mask bits set to 0.
+Counts the number of executed AVX masked load
+operations that refer to an illegal address range with
+the mask bits set to 0.
.It Li BR_INST_RETIRED.ALL_BRANCHES
.Pq Event C4H , Umask 00H
-Branch instructions at retirement.
+Branch instructions at retirement.
.It Li BR_INST_RETIRED.CONDITIONAL
.Pq Event C4H , Umask 01H
Counts the number of conditional branch instructions Supports PEBS
@@ -771,18 +759,18 @@
retired.
.It Li BR_INST_RETIRED.NEAR_CALL
.Pq Event C4H , Umask 02H
-Direct and indirect near call instructions retired.
+Direct and indirect near call instructions retired.
.It Li BR_INST_RETIRED.ALL_BRANCHES
.Pq Event C4H , Umask 04H
-Counts the number of branch instructions retired.
+Counts the number of branch instructions retired.
.It Li BR_INST_RETIRED.NEAR_RETURN
.Pq Event C4H , Umask 08H
-Counts the number of near return instructions
-retired.
+Counts the number of near return instructions
+retired.
.It Li BR_INST_RETIRED.NOT_TAKEN
.Pq Event C4H , Umask 10H
-Counts the number of not taken branch instructions
-retired.
+Counts the number of not taken branch instructions
+retired.
It Li BR_INST_RETIRED.NEAR_TAKEN
.Pq Event C4H , Umask 20H
Number of near taken branches retired.
@@ -821,36 +809,30 @@
Randomly sampled loads whose latency is above a
user defined threshold. A small fraction of the overall
loads are sampled due to randomization.
-.It Li MEM_UOP_RETIRED.LOADS
-.Pq Event D0H , Umask 01H
-Qualify retired memory uops that are loads. Combine Supports PEBS and
-with umask 10H, 20H, 40H, 80H.
-.It Li MEM_UOP_RETIRED.STORES
-.Pq Event D0H , Umask 02H
-Qualify retired memory uops that are stores.
-Combine with umask 10H, 20H, 40H, 80H.
-.It Li MEM_UOP_RETIRED.STLB_MISS
-.Pq Event D0H , Umask 10H
-Qualify retired memory uops with STLB miss. Must
-combine with umask 01H, 02H, to produce counts.
-.It Li MEM_UOP_RETIRED.LOCK
-.Pq Event D0H , Umask 20H
-Qualify retired memory uops with lock. Must combine Supports PEBS and
-with umask 01H, 02H, to produce counts.
-.It Li MEM_UOP_RETIRED.SPLIT
-.Pq Event D0H , Umask 40H
-Qualify retired memory uops with line split. Must
-combine with umask 01H, 02H, to produce counts.
-.It Li MEM_UOP_RETIRED.ALL
-.Pq Event D0H , Umask 80H
-Qualify any retired memory uops. Must combine with Supports PEBS and
-umask 01H, 02H, to produce counts.
+.It Li MEM_UOPS_RETIRED.STLB_MISS_LOADS
+.Pq Event D0H , Umask 11H
+Count retired load uops that missed the STLB.
+.It Li MEM_UOPS_RETIRED.STLB_MISS_STORES
+.Pq Event D0H , Umask 12H
+Count retired store uops that missed the STLB.
+.It Li MEM_UOPS_RETIRED.SPLIT_LOADS
+.Pq Event D0H , Umask 41H
+Count retired load uops that were split across a cache line.
+.It Li MEM_UOPS_RETIRED.SPLIT_STORES
+.Pq Event D0H , Umask 42H
+Count retired store uops that were split across a cache line.
+.It Li MEM_UOPS_RETIRED.ALL_LOADS
+.Pq Event D0H , Umask 81H
+Count all retired load uops.
+.It Li MEM_UOPS_RETIRED.ALL_STORES
+.Pq Event D0H , Umask 82H
+Count all retired store uops.
.It Li MEM_LOAD_UOPS_RETIRED.L1_HIT
.Pq Event D1H , Umask 01H
-Retired load uops with L1 cache hits as data sources.
+Retired load uops with L1 cache hits as data sources.
.It Li MEM_LOAD_UOPS_RETIRED.L2_HIT
.Pq Event D1H , Umask 02H
-Retired load uops with L2 cache hits as data sources.
+Retired load uops with L2 cache hits as data sources.
.It Li MEM_LOAD_UOPS_RETIRED.LLC_HIT
.Pq Event D1H , Umask 04H
Retired load uops with LLC cache hits as data
@@ -870,64 +852,64 @@
and cross-core snoop missed in on-pkg core cache.
.It Li MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_HIT
.Pq Event D2H , Umask 02H
-Retired load uops which data sources were LLC and
-cross-core snoop hits in on-pkg core cache.
+Retired load uops which data sources were LLC and
+cross-core snoop hits in on-pkg core cache.
.It Li MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_HITM
.Pq Event D2H , Umask 04H
-Retired load uops which data sources were HitM
-responses from shared LLC.
+Retired load uops which data sources were HitM
+responses from shared LLC.
.It Li MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_NONE
.Pq Event D2H , Umask 08H
-Retired load uops which data sources were hits in
-LLC without snoops required.
+Retired load uops which data sources were hits in
+LLC without snoops required.
.It Li MEM_LOAD_UOPS_LLC_MISS_RETIRED.LOCAL_DRAM
.Pq Event D3H , Umask 01H
-Retired load uops which data sources missed LLC but
+Retired load uops which data sources missed LLC but
serviced from local dram.
.It Li BACLEARS.ANY
.Pq Event E6H , Umask 1FH
-Number of front end re-steers due to BPU
-misprediction.
+Number of front end re-steers due to BPU
+misprediction.
.It Li L2_TRANS.DEMAND_DATA_RD
.Pq Event F0H , Umask 01H
-Demand Data Read requests that access L2 cache.
+Demand Data Read requests that access L2 cache.
.It Li L2_TRANS.RFO
.Pq Event F0H , Umask 02H
-RFO requests that access L2 cache.
+RFO requests that access L2 cache.
.It Li L2_TRANS.CODE_RD
.Pq Event F0H , Umask 04H
-L2 cache accesses when fetching instructions.
+L2 cache accesses when fetching instructions.
.It Li L2_TRANS.ALL_PF
.Pq Event F0H , Umask 08H
-Any MLC or LLC HW prefetch accessing L2, including
-rejects.
+Any MLC or LLC HW prefetch accessing L2, including
+rejects.
.It Li L2_TRANS.L1D_WB
.Pq Event F0H , Umask 10H
-L1D writebacks that access L2 cache.
+L1D writebacks that access L2 cache.
.It Li L2_TRANS.L2_FILL
.Pq Event F0H , Umask 20H
-L2 fill requests that access L2 cache.
+L2 fill requests that access L2 cache.
.It Li L2_TRANS.L2_WB
.Pq Event F0H , Umask 40H
-L2 writebacks that access L2 cache.
+L2 writebacks that access L2 cache.
.It Li L2_TRANS.ALL_REQUESTS
.Pq Event F0H , Umask 80H
-Transactions accessing L2 pipe.
+Transactions accessing L2 pipe.
.It Li L2_LINES_IN.I
.Pq Event F1H , Umask 01H
-L2 cache lines in I state filling L2.
+L2 cache lines in I state filling L2.
.It Li L2_LINES_IN.S
.Pq Event F1H , Umask 02H
-L2 cache lines in S state filling L2.
+L2 cache lines in S state filling L2.
.It Li L2_LINES_IN.E
.Pq Event F1H , Umask 04H
-L2 cache lines in E state filling L2.
+L2 cache lines in E state filling L2.
.It Li L2_LINES_IN.ALL
.Pq Event F1H , Umask 07H
-L2 cache lines filling L2.
+L2 cache lines filling L2.
.It Li L2_LINES_OUT.DEMAND_CLEAN
.Pq Event F2H , Umask 05H
-Clean L2 cache lines evicted by demand.
+Clean L2 cache lines evicted by demand.
.It Li L2_LINES_OUT.DEMAND_DIRTY
.Pq Event F2H , Umask 06H
Dirty L2 cache lines evicted by demand.
Modified: trunk/lib/libpmc/pmc.haswelluc.3
===================================================================
--- trunk/lib/libpmc/pmc.haswelluc.3 2018-06-09 19:22:04 UTC (rev 10652)
+++ trunk/lib/libpmc/pmc.haswelluc.3 2018-06-09 19:23:10 UTC (rev 10653)
@@ -1,4 +1,5 @@
-.\" Copyright (c) 2013 Hiren Panchasara <hiren.panchasara at gmail.com>
+.\" $MidnightBSD$
+.\" Copyright (c) 2013 Hiren Panchasara <hiren.panchasara at gmail.com>
.\" All rights reserved.
.\"
.\" Redistribution and use in source and binary forms, with or without
@@ -22,7 +23,7 @@
.\" OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
.\" SUCH DAMAGE.
.\"
-.\" $FreeBSD: release/9.2.0/lib/libpmc/pmc.haswelluc.3 249655 2013-04-19 19:28:48Z hiren $
+.\" $FreeBSD: stable/10/lib/libpmc/pmc.haswelluc.3 248871 2013-03-29 08:32:49Z joel $
.\"
.Dd March 22, 2013
.Dt PMC.HASWELLUC 3
@@ -141,7 +142,7 @@
to LLC eviction.
.It Li UNC_CBO_CACHE_LOOKUP.M
.Pq Event 34H , Umask 01H
-LLC lookup request that access cache and found line in
+LLC lookup request that access cache and found line in
M-state.
.It Li UNC_CBO_CACHE_LOOKUP.ES
.Pq Event 34H , Umask 06H
@@ -231,7 +232,7 @@
library was written by
.An "Joseph Koshy"
.Aq jkoshy at FreeBSD.org .
-The support for the Haswell
+The support for the Haswell
microarchitecture was added by
.An "Hiren Panchasara"
.Aq hiren.panchasara at gmail.com .
Added: trunk/lib/libpmc/pmc.haswellxeon.3
===================================================================
--- trunk/lib/libpmc/pmc.haswellxeon.3 (rev 0)
+++ trunk/lib/libpmc/pmc.haswellxeon.3 2018-06-09 19:23:10 UTC (rev 10653)
@@ -0,0 +1,957 @@
+.\" $MidnightBSD$
+.\"
+.\" Copyright (c) 2013 Hiren Panchasara <hiren.panchasara at gmail.com>
+.\" All rights reserved.
+.\"
+.\" Redistribution and use in source and binary forms, with or without
+.\" modification, are permitted provided that the following conditions
+.\" are met:
+.\" 1. Redistributions of source code must retain the above copyright
+.\" notice, this list of conditions and the following disclaimer.
+.\" 2. Redistributions in binary form must reproduce the above copyright
+.\" notice, this list of conditions and the following disclaimer in the
+.\" documentation and/or other materials provided with the distribution.
+.\"
+.\" THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+.\" ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+.\" IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+.\" ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+.\" FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+.\" DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+.\" OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+.\" HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+.\" LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+.\" OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+.\" SUCH DAMAGE.
+.\"
+.\" $FreeBSD: stable/10/lib/libpmc/pmc.haswellxeon.3 320109 2017-06-19 15:20:30Z avg $
+.\"
+.Dd 21 November, 2014
+.Dt PMC.HASWELLXEON 3
+.Os
+.Sh NAME
+.Nm pmc.haswellxeon
+.Nd measurement events for
+.Tn Intel
+.Tn Haswell Xeon
+family CPUs
+.Sh LIBRARY
+.Lb libpmc
+.Sh SYNOPSIS
+.In pmc.h
+.Sh DESCRIPTION
+.Tn Intel
+.Tn "Haswell"
+CPUs contain PMCs conforming to version 2 of the
+.Tn Intel
+performance measurement architecture.
+These CPUs may contain up to two classes of PMCs:
+.Bl -tag -width "Li PMC_CLASS_IAP"
+.It Li PMC_CLASS_IAF
+Fixed-function counters that count only one hardware event per counter.
+.It Li PMC_CLASS_IAP
+Programmable counters that may be configured to count one of a defined
+set of hardware events.
+.El
+.Pp
+The number of PMCs available in each class and their widths need to be
+determined at run time by calling
+.Xr pmc_cpuinfo 3 .
+.Pp
+Intel Haswell Xeon PMCs are documented in
+.Rs
+.%B "Intel(R) 64 and IA-32 Architectures Software Developer's Manual"
+.%T "Combined Volumes: 1, 2A, 2B, 2C, 3A, 3B and 3C"
+.%N "Order Number: 325462-052US"
+.%D September 2014
+.%Q "Intel Corporation"
+.Re
+.Ss HASWELL FIXED FUNCTION PMCS
+These PMCs and their supported events are documented in
+.Xr pmc.iaf 3 .
+.Ss HASWELL PROGRAMMABLE PMCS
+The programmable PMCs support the following capabilities:
+.Bl -column "PMC_CAP_INTERRUPT" "Support"
+.It Em Capability Ta Em Support
+.It PMC_CAP_CASCADE Ta \&No
+.It PMC_CAP_EDGE Ta Yes
+.It PMC_CAP_INTERRUPT Ta Yes
+.It PMC_CAP_INVERT Ta Yes
+.It PMC_CAP_READ Ta Yes
+.It PMC_CAP_PRECISE Ta \&No
+.It PMC_CAP_SYSTEM Ta Yes
+.It PMC_CAP_TAGGING Ta \&No
+.It PMC_CAP_THRESHOLD Ta Yes
+.It PMC_CAP_USER Ta Yes
+.It PMC_CAP_WRITE Ta Yes
+.El
+.Ss Event Qualifiers
+Event specifiers for these PMCs support the following common
+qualifiers:
+.Bl -tag -width indent
+.It Li rsp= Ns Ar value
+Configure the Off-core Response bits.
+.Bl -tag -width indent
+.It Li DMND_DATA_RD
+Counts the number of demand and DCU prefetch data reads of full
+and partial cachelines as well as demand data page table entry
+cacheline reads. Does not count L2 data read prefetches or
+instruction fetches.
+.It Li REQ_DMND_RFO
+Counts the number of demand and DCU prefetch reads for ownership (RFO)
+requests generated by a write to data cacheline. Does not count L2 RFO
+prefetches.
+.It Li REQ_DMND_IFETCH
+Counts the number of demand and DCU prefetch instruction cacheline reads.
+Does not count L2 code read prefetches.
+.It Li REQ_WB
+Counts the number of writeback (modified to exclusive) transactions.
+.It Li REQ_PF_DATA_RD
+Counts the number of data cacheline reads generated by L2 prefetchers.
+.It Li REQ_PF_RFO
+Counts the number of RFO requests generated by L2 prefetchers.
+.It Li REQ_PF_IFETCH
+Counts the number of code reads generated by L2 prefetchers.
+.It Li REQ_PF_LLC_DATA_RD
+L2 prefetcher to L3 for loads.
+.It Li REQ_PF_LLC_RFO
+RFO requests generated by L2 prefetcher
+.It Li REQ_PF_LLC_IFETCH
+L2 prefetcher to L3 for instruction fetches.
+.It Li REQ_BUS_LOCKS
+Bus lock and split lock requests.
+.It Li REQ_STRM_ST
+Streaming store requests.
+.It Li REQ_OTHER
+Any other request that crosses IDI, including I/O.
+.It Li RES_ANY
+Catch all value for any response types.
+.It Li RES_SUPPLIER_NO_SUPP
+No Supplier Information available.
+.It Li RES_SUPPLIER_LLC_HITM
+M-state initial lookup stat in L3.
+.It Li RES_SUPPLIER_LLC_HITE
+E-state.
+.It Li RES_SUPPLIER_LLC_HITS
+S-state.
+.It Li RES_SUPPLIER_LLC_HITF
+F-state.
+.It Li RES_SUPPLIER_LOCAL
+Local DRAM Controller.
+.It Li RES_SNOOP_SNP_NONE
+No details on snoop-related information.
+.It Li RES_SNOOP_SNP_NO_NEEDED
+No snoop was needed to satisfy the request.
+.It Li RES_SNOOP_SNP_MISS
+A snoop was needed and it missed all snooped caches:
+-For LLC Hit, ReslHitl was returned by all cores
+-For LLC Miss, Rspl was returned by all sockets and data was returned from
+DRAM.
+.It Li RES_SNOOP_HIT_NO_FWD
+A snoop was needed and it hits in at least one snooped cache. Hit denotes a
+cache-line was valid before snoop effect. This includes:
+-Snoop Hit w/ Invalidation (LLC Hit, RFO)
+-Snoop Hit, Left Shared (LLC Hit/Miss, IFetch/Data_RD)
+-Snoop Hit w/ Invalidation and No Forward (LLC Miss, RFO Hit S)
+In the LLC Miss case, data is returned from DRAM.
+.It Li RES_SNOOP_HIT_FWD
+A snoop was needed and data was forwarded from a remote socket.
+This includes:
+-Snoop Forward Clean, Left Shared (LLC Hit/Miss, IFetch/Data_RD/RFT).
+.It Li RES_SNOOP_HITM
+A snoop was needed and it HitM-ed in local or remote cache. HitM denotes a
+cache-line was in modified state before effect as a results of snoop. This
+includes:
+-Snoop HitM w/ WB (LLC miss, IFetch/Data_RD)
+-Snoop Forward Modified w/ Invalidation (LLC Hit/Miss, RFO)
+-Snoop MtoS (LLC Hit, IFetch/Data_RD).
+.It Li RES_NON_DRAM
+Target was non-DRAM system address. This includes MMIO transactions.
+.El
+.It Li cmask= Ns Ar value
+Configure the PMC to increment only if the number of configured
+events measured in a cycle is greater than or equal to
+.Ar value .
+.It Li edge
+Configure the PMC to count the number of de-asserted to asserted
+transitions of the conditions expressed by the other qualifiers.
+If specified, the counter will increment only once whenever a
+condition becomes true, irrespective of the number of clocks during
+which the condition remains true.
+.It Li inv
+Invert the sense of comparison when the
+.Dq Li cmask
+qualifier is present, making the counter increment when the number of
+events per cycle is less than the value specified by the
+.Dq Li cmask
+qualifier.
+.It Li os
+Configure the PMC to count events happening at processor privilege
+level 0.
+.It Li usr
+Configure the PMC to count events occurring at privilege levels 1, 2
+or 3.
+.El
+.Pp
+If neither of the
+.Dq Li os
+or
+.Dq Li usr
+qualifiers are specified, the default is to enable both.
+.Ss Event Specifiers (Programmable PMCs)
+Haswell programmable PMCs support the following events:
+.Bl -tag -width indent
+.It Li LD_BLOCKS.STORE_FORWARD
+.Pq Event 03H , Umask 02H
+Loads blocked by overlapping with store buffer that
+cannot be forwarded.
+.It Li MISALIGN_MEM_REF.LOADS
+.Pq Event 05H , Umask 01H
+Speculative cache-line split load uops dispatched to
+L1D.
+.It Li MISALIGN_MEM_REF.STORES
+.Pq Event 05H , Umask 02H
+Speculative cache-line split Store-address uops
+dispatched to L1D.
+.It Li LD_BLOCKS_PARTIAL.ADDRESS_ALIAS
+.Pq Event 07H , Umask 01H
+False dependencies in MOB due to partial compare
+on address.
+.It Li DTLB_LOAD_MISSES.MISS_CAUSES_A_WALK
+.Pq Event 08H , Umask 01H
+Misses in all TLB levels that cause a page walk of any
+page size.
+.It Li DTLB_LOAD_MISSES.WALK_COMPLETED_4K
+.Pq Event 08H , Umask 02H
+Completed page walks due to demand load misses
+that caused 4K page walks in any TLB levels.
+.It Li DTLB_LOAD_MISSES.WALK_COMPLETED_2M_4K
+.Pq Event 08H , Umask 02H
+Completed page walks due to demand load misses
+that caused 2M/4M page walks in any TLB levels.
+.It Li DTLB_LOAD_MISSES.WALK_COMPLETED
+.Pq Event 08H , Umask 0EH
+Completed page walks in any TLB of any page size
+due to demand load misses
+.It Li DTLB_LOAD_MISSES.WALK_DURATION
+.Pq Event 08H , Umask 10H
+Cycle PMH is busy with a walk.
+.It Li DTLB_LOAD_MISSES.STLB_HIT_4K
+.Pq Event 08H , Umask 20H
+Load misses that missed DTLB but hit STLB (4K).
+.It Li DTLB_LOAD_MISSES.STLB_HIT_2M
+.Pq Event 08H , Umask 40H
+Load misses that missed DTLB but hit STLB (2M).
+.It Li DTLB_LOAD_MISSES.STLB_HIT
+.Pq Event 08H , Umask 60H
+Number of cache load STLB hits. No page walk.
+.It Li DTLB_LOAD_MISSES.PDE_CACHE_MISS
+.Pq Event 08H , Umask 80H
+DTLB demand load misses with low part of linear-to-
+physical address translation missed
+.It Li INT_MISC.RECOVERY_CYCLES
+.Pq Event 0DH , Umask 03H
+Cycles waiting to recover after Machine Clears
+except JEClear. Set Cmask= 1.
+.It Li UOPS_ISSUED.ANY
+.Pq Event 0EH , Umask 01H
+ncrements each cycle the # of Uops issued by the
+RAT to RS.
+Set Cmask = 1, Inv = 1, Any= 1to count stalled cycles
+of this core.
+.It Li UOPS_ISSUED.FLAGS_MERGE
+.Pq Event 0EH , Umask 10H
+Number of flags-merge uops allocated. Such uops
+adds delay.
+.It Li UOPS_ISSUED.SLOW_LEA
+.Pq Event 0EH , Umask 20H
+Number of slow LEA or similar uops allocated. Such
+uop has 3 sources (e.g. 2 sources + immediate)
+regardless if as a result of LEA instruction or not.
+.It Li UOPS_ISSUED.SiNGLE_MUL
+.Pq Event 0EH , Umask 40H
+Number of multiply packed/scalar single precision
+uops allocated.
+.It Li L2_RQSTS.DEMAND_DATA_RD_MISS
+.Pq Event 24H , Umask 21H
+Demand Data Read requests that missed L2, no
+rejects.
+.It Li L2_RQSTS.DEMAND_DATA_RD_HIT
+.Pq Event 24H , Umask 41H
+Demand Data Read requests that hit L2 cache.
+.It Li L2_RQSTS.ALL_DEMAND_DATA_RD
+.Pq Event 24H , Umask E1H
+Counts any demand and L1 HW prefetch data load
+requests to L2.
+.It Li L2_RQSTS.RFO_HIT
+.Pq Event 24H , Umask 42H
+Counts the number of store RFO requests that hit
+the L2 cache.
+.It Li L2_RQSTS.RFO_MISS
+.Pq Event 24H , Umask 22H
+Counts the number of store RFO requests that miss
+the L2 cache.
+.It Li L2_RQSTS.ALL_RFO
+.Pq Event 24H , Umask E2H
+Counts all L2 store RFO requests.
+.It Li L2_RQSTS.CODE_RD_HIT
+.Pq Event 24H , Umask 44H
+Number of instruction fetches that hit the L2 cache.
+.It Li L2_RQSTS.CODE_RD_MISS
+.Pq Event 24H , Umask 24H
+Number of instruction fetches that missed the L2
+cache.
+.It Li L2_RQSTS.ALL_DEMAND_MISS
+.Pq Event 24H , Umask 27H
+Demand requests that miss L2 cache.
+.It Li L2_RQSTS.ALL_DEMAND_REFERENCES
+.Pq Event 24H , Umask E7H
+Demand requests to L2 cache.
+.It Li L2_RQSTS.ALL_CODE_RD
+.Pq Event 24H , Umask E4H
+Counts all L2 code requests.
+.It Li L2_RQSTS.L2_PF_HIT
+.Pq Event 24H , Umask 50H
+Counts all L2 HW prefetcher requests that hit L2.
+.It Li L2_RQSTS.L2_PF_MISS
+.Pq Event 24H , Umask 30H
+Counts all L2 HW prefetcher requests that missed
+L2.
+.It Li L2_RQSTS.ALL_PF
+.Pq Event 24H , Umask F8H
+Counts all L2 HW prefetcher requests.
+.It Li L2_RQSTS.MISS
+.Pq Event 24H , Umask 3FH
+All requests that missed L2.
+.It Li L2_RQSTS.REFERENCES
+.Pq Event 24H , Umask FFH
+All requests to L2 cache.
+.It Li L2_DEMAND_RQSTS.WB_HIT
+.Pq Event 27H , Umask 50H
+Not rejected writebacks that hit L2 cache
+.It Li LONGEST_LAT_CACHE.REFERENCE
+.Pq Event 2EH , Umask 4FH
+This event counts requests originating from the core
+that reference a cache line in the last level cache.
+.It Li LONGEST_LAT_CACHE.MISS
+.Pq Event 2EH , Umask 41H
+This event counts each cache miss condition for
+references to the last level cache.
+.It Li CPU_CLK_UNHALTED.THREAD_P
+.Pq Event 3CH , Umask 00H
+Counts the number of thread cycles while the thread
+is not in a halt state. The thread enters the halt state
+when it is running the HLT instruction. The core
+frequency may change from time to time due to
+power or thermal throttling.
+.It Li CPU_CLK_THREAD_UNHALTED.REF_XCLK
+.Pq Event 3CH , Umask 01H
+Increments at the frequency of XCLK (100 MHz)
+when not halted.
+.It Li L1D_PEND_MISS.PENDING
+.Pq Event 48H , Umask 01H
+Increments the number of outstanding L1D misses
+every cycle. Set Cmaks = 1 and Edge =1 to count
+occurrences.
+.It Li DTLB_STORE_MISSES.MISS_CAUSES_A_WALK
+.Pq Event 49H , Umask 01H
+Miss in all TLB levels causes an page walk of any
+page size (4K/2M/4M/1G).
+.It Li DTLB_STORE_MISSES.WALK_COMPLETED_4K
+.Pq Event 49H , Umask 02H
+Completed page walks due to store misses in one or
+more TLB levels of 4K page structure.
+.It Li DTLB_STORE_MISSES.WALK_COMPLETED_2M_4M
+.Pq Event 49H , Umask 04H
+Completed page walks due to store misses in one or
+more TLB levels of 2M/4M page structure.
+.It Li DTLB_STORE_MISSES.WALK_COMPLETED
+.Pq Event 49H , Umask 0EH
+Completed page walks due to store miss in any TLB
+levels of any page size (4K/2M/4M/1G).
+.It Li DTLB_STORE_MISSES.WALK_DURATION
+.Pq Event 49H , Umask 10H
+Cycles PMH is busy with this walk.
+.It Li DTLB_STORE_MISSES.STLB_HIT_4K
+.Pq Event 49H , Umask 20H
+Store misses that missed DTLB but hit STLB (4K).
+.It Li DTLB_STORE_MISSES.STLB_HIT_2M
+.Pq Event 49H , Umask 40H
+Store misses that missed DTLB but hit STLB (2M).
+.It Li DTLB_STORE_MISSES.STLB_HIT
+.Pq Event 49H , Umask 60H
+Store operations that miss the first TLB level but hit
+the second and do not cause page walks.
+.It Li DTLB_STORE_MISSES.PDE_CACHE_MISS
+.Pq Event 49H , Umask 80H
+DTLB store misses with low part of linear-to-physical
+address translation missed.
+.It Li LOAD_HIT_PRE.SW_PF
+.Pq Event 4CH , Umask 01H
+Non-SW-prefetch load dispatches that hit fill buffer
+allocated for S/W prefetch.
+.It Li LOAD_HIT_PRE.HW_PF
+.Pq Event 4CH , Umask 02H
+Non-SW-prefetch load dispatches that hit fill buffer
+allocated for H/W prefetch.
+.It Li L1D.REPLACEMENT
+.Pq Event 51H , Umask 01H
+Counts the number of lines brought into the L1 data
+cache.
+.It Li MOVE_ELIMINATION.INT_NOT_ELIMINATED
+.Pq Event 58H , Umask 04H
+Number of integer Move Elimination candidate uops
+that were not eliminated.
+.It Li MOVE_ELIMINATION.SMID_NOT_ELIMINATED
+.Pq Event 58H , Umask 08H
+Number of SIMD Move Elimination candidate uops
+that were not eliminated.
+.It Li MOVE_ELIMINATION.INT_ELIMINATED
+.Pq Event 58H , Umask 01H
+Unhalted core cycles when the thread is in ring 0.
+.It Li MOVE_ELIMINATION.SMID_ELIMINATED
+.Pq Event 58H , Umask 02H
+Number of SIMD Move Elimination candidate uops
+that were eliminated.
+.It Li CPL_CYCLES.RING0
+.Pq Event 5CH , Umask 02H
+Unhalted core cycles when the thread is in ring 0.
+.It Li CPL_CYCLES.RING123
+.Pq Event 5CH , Umask 01H
+Unhalted core cycles when the thread is not in ring 0.
+.It Li RS_EVENTS.EMPTY_CYCLES
+.Pq Event 5EH , Umask 01H
+Cycles the RS is empty for the thread.
+.It Li OFFCORE_REQUESTS_OUTSTANDING.DEMAND_DATA_RD
+.Pq Event 60H , Umask 01H
+Offcore outstanding Demand Data Read transactions
+in SQ to uncore. Set Cmask=1 to count cycles.
+.It Li OFFCORE_REQUESTS_OUTSTANDING.DEMAND_CORE_RD
+.Pq Event 60H , Umask 02H
+Offcore outstanding Demand code Read transactions
+in SQ to uncore. Set Cmask=1 to count cycles.
+.It Li OFFCORE_REQUESTS_OUTSTANDING.DEMAND_RFO
+.Pq Event 60H , Umask 04H
+Offcore outstanding RFO store transactions in SQ to
+uncore. Set Cmask=1 to count cycles.
+.It Li OFFCORE_REQUESTS_OUTSTANDING.ALL_DATA_RD
+.Pq Event 60H , Umask 08H
+Offcore outstanding cacheable data read
+transactions in SQ to uncore. Set Cmask=1 to count
+cycles.
+.It Li LOCK_CYCLES.SPLIT_LOCK_UC_LOCK_DURATION
+.Pq Event 63H , Umask 01H
+Cycles in which the L1D and L2 are locked, due to a
+UC lock or split lock.
+.It Li LOCK_CYCLES.CACHE_LOCK_DURATION
+.Pq Event 63H , Umask 02H
+Cycles in which the L1D is locked.
+.It Li IDQ.EMPTY
+.Pq Event 79H , Umask 02H
+Counts cycles the IDQ is empty.
+.It Li IDQ.MITE_UOPS
+.Pq Event 79H , Umask 04H
+Increment each cycle # of uops delivered to IDQ from
+MITE path.
+Set Cmask = 1 to count cycles.
+.It Li IDQ.DSB_UOPS
+.Pq Event 79H , Umask 08H
+Increment each cycle. # of uops delivered to IDQ
+from DSB path.
+Set Cmask = 1 to count cycles.
+.It Li IDQ.MS_DSB_UOPS
+.Pq Event 79H , Umask 10H
+Increment each cycle # of uops delivered to IDQ
+when MS_busy by DSB. Set Cmask = 1 to count
+cycles. Add Edge=1 to count # of delivery.
+.It Li IDQ.MS_MITE_UOPS
+.Pq Event 79H , Umask 20H
+ncrement each cycle # of uops delivered to IDQ
+when MS_busy by MITE. Set Cmask = 1 to count
+cycles.
+.It Li IDQ.MS_UOPS
+.Pq Event 79H , Umask 30H
+Increment each cycle # of uops delivered to IDQ from
+MS by either DSB or MITE. Set Cmask = 1 to count
+cycles.
+.It Li IDQ.ALL_DSB_CYCLES_ANY_UOPS
+.Pq Event 79H , Umask 18H
+Counts cycles DSB is delivered at least one uops. Set
+Cmask = 1.
+.It Li IDQ.ALL_DSB_CYCLES_4_UOPS
+.Pq Event 79H , Umask 18H
+Counts cycles DSB is delivered four uops. Set Cmask
+=4.
+.It Li IDQ.ALL_MITE_CYCLES_ANY_UOPS
+.Pq Event 79H , Umask 24H
+Counts cycles MITE is delivered at least one uops. Set
+Cmask = 1.
+.It Li IDQ.ALL_MITE_CYCLES_4_UOPS
+.Pq Event 79H , Umask 24H
+Counts cycles MITE is delivered four uops. Set Cmask
+=4.
+.It Li IDQ.MITE_ALL_UOPS
+.Pq Event 79H , Umask 3CH
+# of uops delivered to IDQ from any path.
+.It Li ICACHE.MISSES
+.Pq Event 80H , Umask 02H
+Number of Instruction Cache, Streaming Buffer and
+Victim Cache Misses. Includes UC accesses.
+.It Li ITLB_MISSES.MISS_CAUSES_A_WALK
+.Pq Event 85H , Umask 01H
+Misses in ITLB that causes a page walk of any page
+size.
+.It Li ITLB_MISSES.WALK_COMPLETED_4K
+.Pq Event 85H , Umask 02H
+Completed page walks due to misses in ITLB 4K page
+entries.
+.It Li TLB_MISSES.WALK_COMPLETED_2M_4M
+.Pq Event 85H , Umask 04H
+Completed page walks due to misses in ITLB 2M/4M
+page entries.
+.It Li ITLB_MISSES.WALK_COMPLETED
+.Pq Event 85H , Umask 0EH
+Completed page walks in ITLB of any page size.
+.It Li ITLB_MISSES.WALK_DURATION
+.Pq Event 85H , Umask 10H
+Cycle PMH is busy with a walk.
+.It Li ITLB_MISSES.STLB_HIT_4K
+.Pq Event 85H , Umask 20H
+ITLB misses that hit STLB (4K).
+.It Li ITLB_MISSES.STLB_HIT_2M
+.Pq Event 85H , Umask 40H
+ITLB misses that hit STLB (2K).
+.It Li ITLB_MISSES.STLB_HIT
+.Pq Event 85H , Umask 60H
+TLB misses that hit STLB. No page walk.
+.It Li ILD_STALL.LCP
+.Pq Event 87H , Umask 01H
+Stalls caused by changing prefix length of the
+instruction.
+.It Li ILD_STALL.IQ_FULL
+.Pq Event 87H , Umask 04H
+Stall cycles due to IQ is full.
+.It Li BR_INST_EXEC.NONTAKEN_COND
+.Pq Event 88H , Umask 41H
+Count conditional near branch instructions that were executed (but not
+necessarily retired) and not taken.
+.It Li BR_INST_EXEC.TAKEN_COND
+.Pq Event 88H , Umask 81H
+Count conditional near branch instructions that were executed (but not
+necessarily retired) and taken.
+.It Li BR_INST_EXEC.DIRECT_JMP
+.Pq Event 88H , Umask 82H
+Count all unconditional near branch instructions excluding calls and
+indirect branches.
+.It Li BR_INST_EXEC.INDIRECT_JMP_NON_CALL_RET
+.Pq Event 88H , Umask 84H
+Count executed indirect near branch instructions that are not calls nor
+returns.
+.It Li BR_INST_EXEC.RETURN_NEAR
+.Pq Event 88H , Umask 88H
+Count indirect near branches that have a return mnemonic.
+.It Li BR_INST_EXEC.DIRECT_NEAR_CALL
+.Pq Event 88H , Umask 90H
+Count unconditional near call branch instructions, excluding non call
+branch, executed.
+.It Li BR_INST_EXEC.INDIRECT_NEAR_CALL
+.Pq Event 88H , Umask A0H
+Count indirect near calls, including both register and memory indirect,
+executed.
+.It Li BR_INST_EXEC.ALL_BRANCHES
+.Pq Event 88H , Umask FFH
+Counts all near executed branches (not necessarily retired).
+.It Li BR_MISP_EXEC.NONTAKEN_COND
+.Pq Event 89H , Umask 41H
+Count conditional near branch instructions mispredicted as nontaken.
+.It Li BR_MISP_EXEC.TAKEN_COND
+.Pq Event 89H , Umask 81H
+Count conditional near branch instructions mispredicted as taken.
+.It Li BR_MISP_EXEC.INDIRECT_JMP_NON_CALL_RET
+.Pq Event 89H , Umask 84H
+Count mispredicted indirect near branch instructions that are not calls
+nor returns.
+.It Li BR_MISP_EXEC.RETURN_NEAR
+.Pq Event 89H , Umask 88H
+Count mispredicted indirect near branches that have a return mnemonic.
+.It Li BR_MISP_EXEC.DIRECT_NEAR_CALL
+.Pq Event 89H , Umask 90H
+Count mispredicted unconditional near call branch instructions, excluding
+non call branch, executed.
+.It Li BR_MISP_EXEC.INDIRECT_NEAR_CALL
+.Pq Event 89H , Umask A0H
+Count mispredicted indirect near calls, including both register and memory
+indirect, executed.
+.It Li BR_MISP_EXEC.ALL_BRANCHES
+.Pq Event 89H , Umask FFH
+Counts all mispredicted near executed branches (not necessarily retired).
+.It Li IDQ_UOPS_NOT_DELIVERED.CORE
+.Pq Event 9CH , Umask 01H
+Count number of non-delivered uops to RAT per
+thread.
+.It Li UOPS_EXECUTED_PORT.PORT_0
+.Pq Event A1H , Umask 01H
+Cycles which a Uop is dispatched on port 0 in this
+thread.
+.It Li UOPS_EXECUTED_PORT.PORT_1
+.Pq Event A1H , Umask 02H
+Cycles which a Uop is dispatched on port 1 in this
+thread.
+.It Li UOPS_EXECUTED_PORT.PORT_2
+.Pq Event A1H , Umask 04H
+Cycles which a Uop is dispatched on port 2 in this
+thread.
+.It Li UOPS_EXECUTED_PORT.PORT_3
+.Pq Event A1H , Umask 08H
+Cycles which a Uop is dispatched on port 3 in this
+thread.
+.It Li UOPS_EXECUTED_PORT.PORT_4
+.Pq Event A1H , Umask 10H
+Cycles which a Uop is dispatched on port 4 in this
+thread.
+.It Li UOPS_EXECUTED_PORT.PORT_5
+.Pq Event A1H , Umask 20H
+Cycles which a Uop is dispatched on port 5 in this
+thread.
+.It Li UOPS_EXECUTED_PORT.PORT_6
+.Pq Event A1H , Umask 40H
+Cycles which a Uop is dispatched on port 6 in this
+thread.
+.It Li UOPS_EXECUTED_PORT.PORT_7
+.Pq Event A1H , Umask 80H
+Cycles which a Uop is dispatched on port 7 in this
+thread.
+.It Li RESOURCE_STALLS.ANY
+.Pq Event A2H , Umask 01H
+Cycles Allocation is stalled due to Resource Related
+reason.
+.It Li RESOURCE_STALLS.RS
+.Pq Event A2H , Umask 04H
+Cycles stalled due to no eligible RS entry available.
+.It Li RESOURCE_STALLS.SB
+.Pq Event A2H , Umask 08H
+Cycles stalled due to no store buffers available (not
+including draining form sync).
+.It Li RESOURCE_STALLS.ROB
+.Pq Event A2H , Umask 10H
+Cycles stalled due to re-order buffer full.
+.It Li CYCLE_ACTIVITY.CYCLES_L2_PENDING
+.Pq Event A3H , Umask 01H
+Cycles with pending L2 miss loads. Set Cmask=2 to
+count cycle.
+.It Li CYCLE_ACTIVITY.CYCLES_LDM_PENDING
+.Pq Event A3H , Umask 02H
+Cycles with pending memory loads. Set Cmask=2 to
+count cycle.
+.It Li CYCLE_ACTIVITY.STALLS_L2_PENDING
+.Pq Event A3H , Umask 05H
+Number of loads missed L2.
+.It Li CYCLE_ACTIVITY.CYCLES_L1D_PENDING
+.Pq Event A3H , Umask 08H
+Cycles with pending L1 cache miss loads. Set
+Cmask=8 to count cycle.
+.It Li ITLB.ITLB_FLUSH
+.Pq Event AEH , Umask 01H
+Counts the number of ITLB flushes, includes
+4k/2M/4M pages.
+.It Li OFFCORE_REQUESTS.DEMAND_DATA_RD
+.Pq Event B0H , Umask 01H
+Demand data read requests sent to uncore.
+.It Li OFFCORE_REQUESTS.DEMAND_CODE_RD
+.Pq Event B0H , Umask 02H
+Demand code read requests sent to uncore.
+.It Li OFFCORE_REQUESTS.DEMAND_RFO
+.Pq Event B0H , Umask 04H
+Demand RFO read requests sent to uncore, including
+regular RFOs, locks, ItoM.
+.It Li OFFCORE_REQUESTS.ALL_DATA_RD
+.Pq Event B0H , Umask 08H
+Data read requests sent to uncore (demand and
+prefetch).
+.It Li UOPS_EXECUTED.CORE
+.Pq Event B1H , Umask 02H
+Counts total number of uops to be executed per-core
+each cycle.
+.It Li OFF_CORE_RESPONSE_0
+.Pq Event B7H , Umask 01H
+Requires MSR 01A6H
+.It Li OFF_CORE_RESPONSE_1
+.Pq Event BBH , Umask 01H
+Requires MSR 01A7H
+.It Li PAGE_WALKER_LOADS.DTLB_L1
+.Pq Event BCH , Umask 11H
+Number of DTLB page walker loads that hit in the
+L1+FB.
+.It Li PAGE_WALKER_LOADS.ITLB_L1
+.Pq Event BCH , Umask 21H
+Number of ITLB page walker loads that hit in the
+L1+FB.
+.It Li PAGE_WALKER_LOADS.DTLB_L2
+.Pq Event BCH , Umask 12H
+Number of DTLB page walker loads that hit in the L2.
+.It Li PAGE_WALKER_LOADS.ITLB_L2
+.Pq Event BCH , Umask 22H
+Number of ITLB page walker loads that hit in the L2.
+.It Li PAGE_WALKER_LOADS.DTLB_L3
+.Pq Event BCH , Umask 14H
+Number of DTLB page walker loads that hit in the L3.
+.It Li PAGE_WALKER_LOADS.ITLB_L3
+.Pq Event BCH , Umask 24H
+Number of ITLB page walker loads that hit in the L3.
+.It Li PAGE_WALKER_LOADS.DTLB_MEMORY
+.Pq Event BCH , Umask 18H
+Number of DTLB page walker loads from memory.
+.It Li PAGE_WALKER_LOADS.ITLB_MEMORY
+.Pq Event BCH , Umask 28H
+Number of ITLB page walker loads from memory.
+.It Li TLB_FLUSH.DTLB_THREAD
+.Pq Event BDH , Umask 01H
+DTLB flush attempts of the thread-specific entries.
+.It Li TLB_FLUSH.STLB_ANY
+.Pq Event BDH , Umask 20H
+Count number of STLB flush attempts.
+.It Li INST_RETIRED.ANY_P
+.Pq Event C0H , Umask 00H
+Number of instructions at retirement.
+.It Li INST_RETIRED.ALL
+.Pq Event C0H , Umask 01H
+Precise instruction retired event with HW to reduce
+effect of PEBS shadow in IP distribution.
+.It Li OTHER_ASSISTS.AVX_TO_SSE
+.Pq Event C1H , Umask 08H
+Number of transitions from AVX-256 to legacy SSE
+when penalty applicable.
+.It Li OTHER_ASSISTS.SSE_TO_AVX
+.Pq Event C1H , Umask 10H
+Number of transitions from SSE to AVX-256 when
+penalty applicable.
+.It Li OTHER_ASSISTS.ANY_WB_ASSIST
+.Pq Event C1H , Umask 40H
+Number of microcode assists invoked by HW upon
+uop writeback.
+.It Li UOPS_RETIRED.ALL
+.Pq Event C2H , Umask 01H
+Counts the number of micro-ops retired, Use
+cmask=1 and invert to count active cycles or stalled
+cycles.
+.It Li UOPS_RETIRED.RETIRE_SLOTS
+.Pq Event C2H , Umask 02H
+Counts the number of retirement slots used each
+cycle.
+.It Li MACHINE_CLEARS.MEMORY_ORDERING
+.Pq Event C3H , Umask 02H
+Counts the number of machine clears due to memory
+order conflicts.
+.It Li MACHINE_CLEARS.SMC
+.Pq Event C3H , Umask 04H
+Number of self-modifying-code machine clears
+detected.
+.It Li MACHINE_CLEARS.MASKMOV
+.Pq Event C3H , Umask 20H
+Counts the number of executed AVX masked load
+operations that refer to an illegal address range with
+the mask bits set to 0.
+.It Li BR_INST_RETIRED.ALL_BRANCHES
+.Pq Event C4H , Umask 00H
+Branch instructions at retirement.
+.It Li BR_INST_RETIRED.CONDITIONAL
+.Pq Event C4H , Umask 01H
+Counts the number of conditional branch instructions Supports PEBS
+retired.
+.It Li BR_INST_RETIRED.NEAR_CALL
+.Pq Event C4H , Umask 02H
+Direct and indirect near call instructions retired.
+.It Li BR_INST_RETIRED.ALL_BRANCHES
+.Pq Event C4H , Umask 04H
+Counts the number of branch instructions retired.
+.It Li BR_INST_RETIRED.NEAR_RETURN
+.Pq Event C4H , Umask 08H
+Counts the number of near return instructions
+retired.
+.It Li BR_INST_RETIRED.NOT_TAKEN
+.Pq Event C4H , Umask 10H
+Counts the number of not taken branch instructions
+retired.
+ It Li BR_INST_RETIRED.NEAR_TAKEN
+.Pq Event C4H , Umask 20H
+Number of near taken branches retired.
+.It Li BR_INST_RETIRED.FAR_BRANCH
+.Pq Event C4H , Umask 40H
+Number of far branches retired.
+.It Li BR_MISP_RETIRED.ALL_BRANCHES
+.Pq Event C5H , Umask 00H
+Mispredicted branch instructions at retirement
+.It Li BR_MISP_RETIRED.CONDITIONAL
+.Pq Event C5H , Umask 01H
+Mispredicted conditional branch instructions retired.
+.It Li BR_MISP_RETIRED.CONDITIONAL
+.Pq Event C5H , Umask 04H
+Mispredicted macro branch instructions retired.
+.It Li FP_ASSIST.X87_OUTPUT
+.Pq Event CAH , Umask 02H
+Number of X87 FP assists due to Output values.
+.It Li FP_ASSIST.X87_INPUT
+.Pq Event CAH , Umask 04H
+Number of X87 FP assists due to input values.
+.It Li FP_ASSIST.SIMD_OUTPUT
+.Pq Event CAH , Umask 08H
+Number of SIMD FP assists due to Output values.
+.It Li FP_ASSIST.SIMD_INPUT
+.Pq Event CAH , Umask 10H
+Number of SIMD FP assists due to input values.
+.It Li FP_ASSIST.ANY
+.Pq Event CAH , Umask 1EH
+Cycles with any input/output SSE* or FP assists.
+.It Li ROB_MISC_EVENTS.LBR_INSERTS
+.Pq Event CCH , Umask 20H
+Count cases of saving new LBR records by hardware.
+.It Li MEM_TRANS_RETIRED.LOAD_LATENCY
+.Pq Event CDH , Umask 01H
+Randomly sampled loads whose latency is above a
+user defined threshold. A small fraction of the overall
+loads are sampled due to randomization.
+.It Li MEM_UOPS_RETIRED.STLB_MISS_LOADS
+.Pq Event D0H , Umask 11H
+Count retired load uops that missed the STLB.
+.It Li MEM_UOPS_RETIRED.STLB_MISS_STORES
+.Pq Event D0H , Umask 12H
+Count retired store uops that missed the STLB.
+.It Li MEM_UOPS_RETIRED.SPLIT_LOADS
+.Pq Event D0H , Umask 41H
+Count retired load uops that were split across a cache line.
+.It Li MEM_UOPS_RETIRED.SPLIT_STORES
+.Pq Event D0H , Umask 42H
+Count retired store uops that were split across a cache line.
+.It Li MEM_UOPS_RETIRED.ALL_LOADS
+.Pq Event D0H , Umask 81H
+Count all retired load uops.
+.It Li MEM_UOPS_RETIRED.ALL_STORES
+.Pq Event D0H , Umask 82H
+Count all retired store uops.
+.It Li MEM_LOAD_UOPS_RETIRED.L1_HIT
+.Pq Event D1H , Umask 01H
+Retired load uops with L1 cache hits as data sources.
+.It Li MEM_LOAD_UOPS_RETIRED.L2_HIT
+.Pq Event D1H , Umask 02H
+Retired load uops with L2 cache hits as data sources.
+.It Li MEM_LOAD_UOPS_RETIRED.LLC_HIT
+.Pq Event D1H , Umask 04H
+Retired load uops with LLC cache hits as data
+sources.
+.It Li MEM_LOAD_UOPS_RETIRED.L2_MISS
+.Pq Event D1H , Umask 10H
+Retired load uops missed L2. Unknown data source
+excluded.
+.It Li MEM_LOAD_UOPS_RETIRED.HIT_LFB
+.Pq Event D1H , Umask 40H
+Retired load uops which data sources were load uops
+missed L1 but hit FB due to preceding miss to the
+same cache line with data not ready.
+.It Li MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_MISS
+.Pq Event D2H , Umask 01H
+Retired load uops which data sources were LLC hit
+and cross-core snoop missed in on-pkg core cache.
+.It Li MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_HIT
+.Pq Event D2H , Umask 02H
+Retired load uops which data sources were LLC and
+cross-core snoop hits in on-pkg core cache.
+.It Li MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_HITM
+.Pq Event D2H , Umask 04H
+Retired load uops which data sources were HitM
+responses from shared LLC.
+.It Li MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_NONE
+.Pq Event D2H , Umask 08H
+Retired load uops which data sources were hits in
+LLC without snoops required.
+.It Li MEM_LOAD_UOPS_LLC_MISS_RETIRED.LOCAL_DRAM
+.Pq Event D3H , Umask 01H
+Retired load uops which data sources missed LLC but
+serviced from local dram.
+.It Li BACLEARS.ANY
+.Pq Event E6H , Umask 1FH
+Number of front end re-steers due to BPU
+misprediction.
+.It Li L2_TRANS.DEMAND_DATA_RD
+.Pq Event F0H , Umask 01H
+Demand Data Read requests that access L2 cache.
+.It Li L2_TRANS.RFO
+.Pq Event F0H , Umask 02H
+RFO requests that access L2 cache.
+.It Li L2_TRANS.CODE_RD
+.Pq Event F0H , Umask 04H
+L2 cache accesses when fetching instructions.
+.It Li L2_TRANS.ALL_PF
+.Pq Event F0H , Umask 08H
+Any MLC or LLC HW prefetch accessing L2, including
+rejects.
+.It Li L2_TRANS.L1D_WB
+.Pq Event F0H , Umask 10H
+L1D writebacks that access L2 cache.
+.It Li L2_TRANS.L2_FILL
+.Pq Event F0H , Umask 20H
+L2 fill requests that access L2 cache.
+.It Li L2_TRANS.L2_WB
+.Pq Event F0H , Umask 40H
+L2 writebacks that access L2 cache.
+.It Li L2_TRANS.ALL_REQUESTS
+.Pq Event F0H , Umask 80H
+Transactions accessing L2 pipe.
+.It Li L2_LINES_IN.I
+.Pq Event F1H , Umask 01H
+L2 cache lines in I state filling L2.
+.It Li L2_LINES_IN.S
+.Pq Event F1H , Umask 02H
+L2 cache lines in S state filling L2.
+.It Li L2_LINES_IN.E
+.Pq Event F1H , Umask 04H
+L2 cache lines in E state filling L2.
+.It Li L2_LINES_IN.ALL
+.Pq Event F1H , Umask 07H
+L2 cache lines filling L2.
+.It Li L2_LINES_OUT.DEMAND_CLEAN
+.Pq Event F2H , Umask 05H
+Clean L2 cache lines evicted by demand.
+.It Li L2_LINES_OUT.DEMAND_DIRTY
+.Pq Event F2H , Umask 06H
+Dirty L2 cache lines evicted by demand.
+.El
+.Sh SEE ALSO
+.Xr pmc 3 ,
+.Xr pmc.atom 3 ,
+.Xr pmc.core 3 ,
+.Xr pmc.iaf 3 ,
+.Xr pmc.ucf 3 ,
+.Xr pmc.k7 3 ,
+.Xr pmc.k8 3 ,
+.Xr pmc.p4 3 ,
+.Xr pmc.p5 3 ,
+.Xr pmc.p6 3 ,
+.Xr pmc.corei7 3 ,
+.Xr pmc.corei7uc 3 ,
+.Xr pmc.haswell 3 ,
+.Xr pmc.haswelluc 3 ,
+.Xr pmc.ivybridge 3 ,
+.Xr pmc.ivybridgexeon 3 ,
+.Xr pmc.sandybridge 3 ,
+.Xr pmc.sandybridgeuc 3 ,
+.Xr pmc.sandybridgexeon 3 ,
+.Xr pmc.westmere 3 ,
+.Xr pmc.westmereuc 3 ,
+.Xr pmc.soft 3 ,
+.Xr pmc.tsc 3 ,
+.Xr pmc_cpuinfo 3 ,
+.Xr pmclog 3 ,
+.Xr hwpmc 4
+.Sh HISTORY
+Support for the Haswell Xeon microarchitecture first appeared in
+.Fx 10.2 .
+.Sh AUTHORS
+The
+.Lb libpmc
+library was written by
+.An "Joseph Koshy"
+.Aq jkoshy at FreeBSD.org .
+The support for the Haswell Xeon
+microarchitecture was written by
+.An "Randall Stewart"
+.Aq rrs at FreeBSD.org .
Property changes on: trunk/lib/libpmc/pmc.haswellxeon.3
___________________________________________________________________
Added: svn:eol-style
## -0,0 +1 ##
+native
\ No newline at end of property
Added: svn:keywords
## -0,0 +1 ##
+MidnightBSD=%H
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+text/plain
\ No newline at end of property
Modified: trunk/lib/libpmc/pmc.iaf.3
===================================================================
--- trunk/lib/libpmc/pmc.iaf.3 2018-06-09 19:22:04 UTC (rev 10652)
+++ trunk/lib/libpmc/pmc.iaf.3 2018-06-09 19:23:10 UTC (rev 10653)
@@ -1,3 +1,4 @@
+.\" $MidnightBSD$
.\" Copyright (c) 2008 Joseph Koshy. All rights reserved.
.\"
.\" Redistribution and use in source and binary forms, with or without
@@ -21,7 +22,7 @@
.\" OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
.\" SUCH DAMAGE.
.\"
-.\" $FreeBSD: release/9.2.0/lib/libpmc/pmc.iaf.3 236238 2012-05-29 14:50:21Z fabient $
+.\" $FreeBSD: stable/10/lib/libpmc/pmc.iaf.3 233628 2012-03-28 20:58:30Z fabient $
.\"
.Dd November 14, 2008
.Dt PMC.IAF 3
Property changes on: trunk/lib/libpmc/pmc.iaf.3
___________________________________________________________________
Added: svn:keywords
## -0,0 +1 ##
+MidnightBSD=%H
\ No newline at end of property
Modified: trunk/lib/libpmc/pmc.ivybridge.3
===================================================================
--- trunk/lib/libpmc/pmc.ivybridge.3 2018-06-09 19:22:04 UTC (rev 10652)
+++ trunk/lib/libpmc/pmc.ivybridge.3 2018-06-09 19:23:10 UTC (rev 10653)
@@ -1,3 +1,4 @@
+.\" $MidnightBSD$
.\" Copyright (c) 2012 Fabien Thomas. All rights reserved.
.\"
.\" Redistribution and use in source and binary forms, with or without
@@ -21,7 +22,7 @@
.\" OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
.\" SUCH DAMAGE.
.\"
-.\" $FreeBSD: release/9.2.0/lib/libpmc/pmc.ivybridge.3 249492 2013-04-15 03:09:59Z hiren $
+.\" $FreeBSD: stable/10/lib/libpmc/pmc.ivybridge.3 320109 2017-06-19 15:20:30Z avg $
.\"
.Dd October 19, 2012
.Dt PMC.IVYBRIDGE 3
@@ -58,7 +59,6 @@
Intel Ivy Bridge PMCs are documented in
.Rs
.%B "Intel(R) 64 and IA-32 Architectures Software Developer's Manual"
-Intel(R) 64 and IA-32 Architectures Software Developers Manual"
.%T "Volume 3B: System Programming Guide, Part 2"
.%N "Order Number: 253669-043US"
.%D May 2012
@@ -200,33 +200,33 @@
.Bl -tag -width indent
.It Li LD_BLOCKS.STORE_FORWARD
.Pq Event 03H , Umask 02H
-loads blocked by overlapping with store buffer that cannot be forwarded .
+loads blocked by overlapping with store buffer that cannot be forwarded .
.It Li MISALIGN_MEM_REF.LOADS
.Pq Event 05H , Umask 01H
-Speculative cache-line split load uops dispatched to L1D.
+Speculative cache-line split load uops dispatched to L1D.
.It Li MISALIGN_MEM_REF.STORES
.Pq Event 05H , Umask 02H
-Speculative cache-line split Store- address uops dispatched to L1D.
+Speculative cache-line split Store- address uops dispatched to L1D.
.It Li LD_BLOCKS_PARTIAL.ADDRESS_ALIAS
.Pq Event 07H , Umask 01H
-False dependencies in MOB due to partial compare on address.
+False dependencies in MOB due to partial compare on address.
.It Li DTLB_LOAD_MISSES.DEMAND_LD_MISS_CAUSES_A_WALK
.Pq Event 08H , Umask 81H
-Misses in all TLB levels that cause a page walk of any page size from demand loads.
+Misses in all TLB levels that cause a page walk of any page size from demand loads.
.It Li DTLB_LOAD_MISSES.DEMAND_LD_WALK_COMPLETED
.Pq Event 08H , Umask 82H
-Misses in all TLB levels that caused page walk completed of any size by demand loads.
+Misses in all TLB levels that caused page walk completed of any size by demand loads.
.It Li DTLB_LOAD_MISSES.DEMAND_LD_WALK_DURATION
.Pq Event 08H , Umask 84H
-Cycle PMH is busy with a walk due to demand loads.
+Cycle PMH is busy with a walk due to demand loads.
.It Li UOPS_ISSUED.ANY
.Pq Event 0EH , Umask 01H
-Increments each cycle the # of Uops issued by the RAT to RS.
+Increments each cycle the # of Uops issued by the RAT to RS.
Set Cmask = 1, Inv = 1to count stalled cycles.
-Set Cmask = 1, Inv = 1, Any= 1to count stalled cycles of this core.
+Set Cmask = 1, Inv = 1, Any= 1to count stalled cycles of this core.
.It Li UOPS_ISSUED.FLAGS_MERGE
.Pq Event 0EH , Umask 10H
-Number of flags-merge uops allocated. Such uops adds delay.
+Number of flags-merge uops allocated. Such uops adds delay.
.It Li UOPS_ISSUED.SLOW_LEA
.Pq Event 0EH , Umask 20H
Number of slow LEA or similar uops allocated. Such uop has 3 sources (e.g. 2
@@ -233,7 +233,7 @@
sources + immediate) regardless if as a result of LEA instruction or not.
.It Li UOPS_ISSUED.SINGLE_MUL
.Pq Event 0EH , Umask 40H
-Number of multiply packed/scalar single precision uops allocated.
+Number of multiply packed/scalar single precision uops allocated.
.It Li ARITH.FPU_DIV_ACTIVE
.Pq Event 14H , Umask 01H
Cycles that the divider is active, includes INT and FP. Set 'edge =1,
@@ -246,31 +246,31 @@
Counts any demand and L1 HW prefetch data load requests to L2.
.It Li L2_RQSTS.RFO_HITS
.Pq Event 24H , Umask 04H
-Counts the number of store RFO requests that hit the L2 cache.
+Counts the number of store RFO requests that hit the L2 cache.
.It Li L2_RQSTS.RFO_MISS
.Pq Event 24H , Umask 08H
-Counts the number of store RFO requests that miss the L2 cache.
+Counts the number of store RFO requests that miss the L2 cache.
.It Li L2_RQSTS.ALL_RFO
.Pq Event 24H , Umask 0CH
-Counts all L2 store RFO requests.
+Counts all L2 store RFO requests.
.It Li L2_RQSTS.CODE_RD_HIT
.Pq Event 24H , Umask 10H
-Number of instruction fetches that hit the L2 cache.
+Number of instruction fetches that hit the L2 cache.
.It Li L2_RQSTS.CODE_RD_MISS
.Pq Event 24H , Umask 20H
-Number of instruction fetches that missed the L2 cache.
+Number of instruction fetches that missed the L2 cache.
.It Li L2_RQSTS.ALL_CODE_RD
.Pq Event 24H , Umask 30H
-Counts all L2 code requests.
+Counts all L2 code requests.
.It Li L2_RQSTS.PF_HIT
.Pq Event 24H , Umask 40H
-Counts all L2 HW prefetcher requests that hit L2.
+Counts all L2 HW prefetcher requests that hit L2.
.It Li L2_RQSTS.PF_MISS
.Pq Event 24H , Umask 80H
-Counts all L2 HW prefetcher requests that missed L2.
+Counts all L2 HW prefetcher requests that missed L2.
.It Li L2_RQSTS.ALL_PF
.Pq Event 24H , Umask C0H
-Counts all L2 HW prefetcher requests.
+Counts all L2 HW prefetcher requests.
.It Li L2_STORE_LOCK_RQSTS.MISS
.Pq Event 27H , Umask 01H
RFOs that miss cache lines.
@@ -308,13 +308,13 @@
throttling.
.It Li CPU_CLK_THREAD_UNHALTED.REF_XCLK
.Pq Event 3CH , Umask 01H
-Increments at the frequency of XCLK (100 MHz) when not halted.
+Increments at the frequency of XCLK (100 MHz) when not halted.
.It Li L1D_PEND_MISS.PENDING
.Pq Event 48H , Umask 01H
Increments the number of outstanding L1D misses every cycle. Set Cmaks = 1
and Edge =1 to count occurrences.
Counter 2 only.
-Set Cmask = 1 to count cycles.
+Set Cmask = 1 to count cycles.
.It Li DTLB_STORE_MISSES.MISS_CAUSES_A_WALK
.Pq Event 49H , Umask 01H
Miss in all TLB levels causes an page walk of any page size (4K/2M/4M/1G).
@@ -340,16 +340,16 @@
Counts the number of lines brought into the L1 data cache.
.It Li MOVE_ELIMINATION.INT_NOT_ELIMINATED
.Pq Event 58H , Umask 01H
-Number of integer Move Elimination candidate uops that were not eliminated.
+Number of integer Move Elimination candidate uops that were not eliminated.
.It Li MOVE_ELIMINATION.SIMD_NOT_ELIMINATED
.Pq Event 58H , Umask 02H
-Number of SIMD Move Elimination candidate uops that were not eliminated.
+Number of SIMD Move Elimination candidate uops that were not eliminated.
.It Li MOVE_ELIMINATION.INT_ELIMINATED
.Pq Event 58H , Umask 04H
-Number of integer Move Elimination candidate uops that were eliminated.
+Number of integer Move Elimination candidate uops that were eliminated.
.It Li MOVE_ELIMINATION.SIMD_ELIMINATED
.Pq Event 58H , Umask 08H
-Number of SIMD Move Elimination candidate uops that were eliminated.
+Number of SIMD Move Elimination candidate uops that were eliminated.
.It Li CPL_CYCLES.RING0
.Pq Event 5CH , Umask 01H
Unhalted core cycles when the thread is in ring 0.
@@ -390,14 +390,14 @@
Counts cycles the IDQ is empty.
.It Li IDQ.MITE_UOPS
.Pq Event 79H , Umask 04H
-Increment each cycle # of uops delivered to IDQ from MITE path.
+Increment each cycle # of uops delivered to IDQ from MITE path.
Can combine Umask 04H and 20H.
-Set Cmask = 1 to count cycles.
+Set Cmask = 1 to count cycles.
.It Li IDQ.DSB_UOPS
.Pq Event 79H , Umask 08H
-Increment each cycle. # of uops delivered to IDQ from DSB path.
-Can combine Umask 08H and 10H
-Set Cmask = 1 to count cycles.
+Increment each cycle. # of uops delivered to IDQ from DSB path.
+Can combine Umask 08H and 10H
+Set Cmask = 1 to count cycles.
.It Li IDQ.MS_DSB_UOPS
.Pq Event 79H , Umask 10H
Increment each cycle # of uops delivered to IDQ when MS_busy by DSB. Set
@@ -450,80 +450,60 @@
.It Li ILD_STALL.IQ_FULL
.Pq Event 87H , Umask 04H
Stall cycles due to IQ is full.
-.It Li BR_INST_EXEC.COND
-.Pq Event 88H , Umask 01H
-Qualify conditional near branch instructions executed, but not necessarily
-retired.
-Must combine with umask 40H, 80H.
+.It Li BR_INST_EXEC.NONTAKEN_COND
+.Pq Event 88H , Umask 41H
+Count conditional near branch instructions that were executed (but not
+necessarily retired) and not taken.
+.It Li BR_INST_EXEC.TAKEN_COND
+.Pq Event 88H , Umask 81H
+Count conditional near branch instructions that were executed (but not
+necessarily retired) and taken.
.It Li BR_INST_EXEC.DIRECT_JMP
-.Pq Event 88H , Umask 02H
-Qualify all unconditional near branch instructions excluding calls and
+.Pq Event 88H , Umask 82H
+Count all unconditional near branch instructions excluding calls and
indirect branches.
-Must combine with umask 80H.
.It Li BR_INST_EXEC.INDIRECT_JMP_NON_CALL_RET
-.Pq Event 88H , Umask 04H
-Qualify executed indirect near branch instructions that are not calls nor
+.Pq Event 88H , Umask 84H
+Count executed indirect near branch instructions that are not calls nor
returns.
-Must combine with umask 80H.
.It Li BR_INST_EXEC.RETURN_NEAR
-.Pq Event 88H , Umask 08H
-Qualify indirect near branches that have a return mnemonic.
-Must combine with umask 80H.
+.Pq Event 88H , Umask 88H
+Count indirect near branches that have a return mnemonic.
.It Li BR_INST_EXEC.DIRECT_NEAR_CALL
-.Pq Event 88H , Umask 10H
-Qualify unconditional near call branch instructions, excluding non call
+.Pq Event 88H , Umask 90H
+Count unconditional near call branch instructions, excluding non call
branch, executed.
-Must combine with umask 80H.
.It Li BR_INST_EXEC.INDIRECT_NEAR_CALL
-.Pq Event 88H , Umask 20H
-Qualify indirect near calls, including both register and memory indirect,
+.Pq Event 88H , Umask A0H
+Count indirect near calls, including both register and memory indirect,
executed.
-Must combine with umask 80H.
-.It Li BR_INST_EXEC.NONTAKEN
-.Pq Event 88H , Umask 40H
-Qualify non-taken near branches executed.
-Applicable to umask 01H only.
-.It Li BR_INST_EXEC.TAKEN
-.Pq Event 88H , Umask 80H
-Qualify taken near branches executed. Must combine with 01H,02H, 04H, 08H,
-10H, 20H.
.It Li BR_INST_EXEC.ALL_BRANCHES
.Pq Event 88H , Umask FFH
Counts all near executed branches (not necessarily retired).
-.It Li BR_MISP_EXEC.COND
-.Pq Event 89H , Umask 01H
-Qualify conditional near branch instructions mispredicted.
-Must combine with umask 40H, 80H.
+.It Li BR_MISP_EXEC.NONTAKEN_COND
+.Pq Event 89H , Umask 41H
+Count conditional near branch instructions mispredicted as nontaken.
+.It Li BR_MISP_EXEC.TAKEN_COND
+.Pq Event 89H , Umask 81H
+Count conditional near branch instructions mispredicted as taken.
.It Li BR_MISP_EXEC.INDIRECT_JMP_NON_CALL_RET
-.Pq Event 89H , Umask 04H
-Qualify mispredicted indirect near branch instructions that are not calls
+.Pq Event 89H , Umask 84H
+Count mispredicted indirect near branch instructions that are not calls
nor returns.
-Must combine with umask 80H.
.It Li BR_MISP_EXEC.RETURN_NEAR
-.Pq Event 89H , Umask 08H
-Qualify mispredicted indirect near branches that have a return mnemonic.
-Must combine with umask 80H.
+.Pq Event 89H , Umask 88H
+Count mispredicted indirect near branches that have a return mnemonic.
.It Li BR_MISP_EXEC.DIRECT_NEAR_CALL
-.Pq Event 89H , Umask 10H
-Qualify mispredicted unconditional near call branch instructions, excluding
+.Pq Event 89H , Umask 90H
+Count mispredicted unconditional near call branch instructions, excluding
non call branch, executed.
-Must combine with umask 80H.
.It Li BR_MISP_EXEC.INDIRECT_NEAR_CALL
-.Pq Event 89H , Umask 20H
-Qualify mispredicted indirect near calls, including both register and memory
+.Pq Event 89H , Umask A0H
+Count mispredicted indirect near calls, including both register and memory
indirect, executed.
-Must combine with umask 80H.
-.It Li BR_MISP_EXEC.NONTAKEN
-.Pq Event 89H , Umask 40H
-Qualify mispredicted non-taken near branches executed.
-Applicable to umask 01H only.
-.It Li BR_MISP_EXEC.TAKEN
-.Pq Event 89H , Umask 80H
-Qualify mispredicted taken near branches executed. Must combine with
-01H,02H, 04H, 08H, 10H, 20H.
.It Li BR_MISP_EXEC.ALL_BRANCHES
.Pq Event 89H , Umask FFH
-Counts all near executed branches (not necessarily retired).
+Counts all mispredicted near executed branches (not necessarily retired).
.It Li IDQ_UOPS_NOT_DELIVERED.CORE
.Pq Event 9CH , Umask 01H
Count number of non-delivered uops to RAT per thread.
@@ -545,7 +525,7 @@
Cycles which a Uop is dispatched on port 2.
.It Li UOPS_DISPATCHED_PORT.PORT_3_LD
.Pq Event A1H , Umask 10H
-Cycles which a load uop is dispatched on port 3.
+Cycles which a load uop is dispatched on port 3.
.It Li UOPS_DISPATCHED_PORT.PORT_3_STA
.Pq Event A1H , Umask 20H
Cycles which a store address uop is dispatched on port 3.
@@ -622,7 +602,7 @@
Count number of STLB flush attempts.
.It Li INST_RETIRED.ANY_P
.Pq Event C0H , Umask 00H
-Number of instructions at retirement.
+Number of instructions at retirement.
.It Li INST_RETIRED.ALL
.Pq Event C0H , Umask 01H
Precise instruction retired event with HW to reduce effect of PEBS shadow in
@@ -631,7 +611,7 @@
Must quiesce other PMCs.
.It Li OTHER_ASSISTS.AVX_STORE
.Pq Event C1H , Umask 08H
-Number of assists associated with 256-bit AVX store operations.
+Number of assists associated with 256-bit AVX store operations.
.It Li OTHER_ASSISTS.AVX_TO_SSE
.Pq Event C1H , Umask 10H
Number of transitions from AVX- 256 to legacy SSE when penalty applicable.
@@ -726,32 +706,25 @@
.It Li MEM_TRANS_RETIRED.PRECISE_STORE
.Pq Event CDH , Umask 02H
Sample stores and collect precise store operation via PEBS record.
-PMC3 only.
-.It Li MEM_UOP_RETIRED.LOADS
-.Pq Event D0H , Umask 01H
-Qualify retired memory uops that are loads. Combine with umask 10H, 20H,
-40H, 80H.
-Supports PEBS.
-.It Li MEM_UOP_RETIRED.STORES
-.Pq Event D0H , Umask 02H
-Qualify retired memory uops that are stores. Combine with umask 10H, 20H,
-40H, 80H.
-.It Li MEM_UOP_RETIRED.STLB_MISS
-.Pq Event D0H , Umask 10H
-Qualify retired memory uops with STLB miss. Must combine with umask 01H,
-02H, to produce counts.
-.It Li MEM_UOP_RETIRED.LOCK
-.Pq Event D0H , Umask 20H
-Qualify retired memory uops with lock. Must combine with umask 01H, 02H, to
-produce counts.
-.It Li MEM_UOP_RETIRED.SPLIT
-.Pq Event D0H , Umask 40H
-Qualify retired memory uops with line split. Must combine with umask 01H,
-02H, to produce counts.
-.It Li MEM_UOP_RETIRED.ALL
-.Pq Event D0H , Umask 80H
-Qualify any retired memory uops. Must combine with umask 01H, 02H, to
-produce counts.
+PMC3 only.
+.It Li MEM_UOPS_RETIRED.STLB_MISS_LOADS
+.Pq Event D0H , Umask 11H
+Count retired load uops that missed the STLB.
+.It Li MEM_UOPS_RETIRED.STLB_MISS_STORES
+.Pq Event D0H , Umask 12H
+Count retired store uops that missed the STLB.
+.It Li MEM_UOPS_RETIRED.SPLIT_LOADS
+.Pq Event D0H , Umask 41H
+Count retired load uops that were split across a cache line.
+.It Li MEM_UOPS_RETIRED.SPLIT_STORES
+.Pq Event D0H , Umask 42H
+Count retired store uops that were split across a cache line.
+.It Li MEM_UOPS_RETIRED.ALL_LOADS
+.Pq Event D0H , Umask 81H
+Count all retired load uops.
+.It Li MEM_UOPS_RETIRED.ALL_STORES
+.Pq Event D0H , Umask 82H
+Count all retired store uops.
.It Li MEM_LOAD_UOPS_RETIRED.L1_HIT
.Pq Event D1H , Umask 01H
Retired load uops with L1 cache hits as data sources.
@@ -799,47 +772,47 @@
L2 cache accesses when fetching instructions.
.It Li L2_TRANS.ALL_PF
.Pq Event F0H , Umask 08H
-Any MLC or LLC HW prefetch accessing L2, including rejects.
+Any MLC or LLC HW prefetch accessing L2, including rejects.
.It Li L2_TRANS.L1D_WB
.Pq Event F0H , Umask 10H
-L1D writebacks that access L2 cache.
+L1D writebacks that access L2 cache.
.It Li L2_TRANS.L2_FILL
.Pq Event F0H , Umask 20H
-L2 fill requests that access L2 cache.
+L2 fill requests that access L2 cache.
.It Li L2_TRANS.L2_WB
.Pq Event F0H , Umask 40H
-L2 writebacks that access L2 cache.
+L2 writebacks that access L2 cache.
.It Li L2_TRANS.ALL_REQUESTS
.Pq Event F0H , Umask 80H
-Transactions accessing L2 pipe.
+Transactions accessing L2 pipe.
.It Li L2_LINES_IN.I
.Pq Event F1H , Umask 01H
-L2 cache lines in I state filling L2.
-Counting does not cover rejects.
+L2 cache lines in I state filling L2.
+Counting does not cover rejects.
.It Li L2_LINES_IN.S
.Pq Event F1H , Umask 02H
-L2 cache lines in S state filling L2.
-Counting does not cover rejects.
+L2 cache lines in S state filling L2.
+Counting does not cover rejects.
.It Li L2_LINES_IN.E
.Pq Event F1H , Umask 04H
-L2 cache lines in E state filling L2.
-Counting does not cover rejects.
+L2 cache lines in E state filling L2.
+Counting does not cover rejects.
.It Li L2_LINES_IN.ALL
.Pq Event F1H , Umask 07H
-L2 cache lines filling L2.
-Counting does not cover rejects.
+L2 cache lines filling L2.
+Counting does not cover rejects.
.It Li L2_LINES_OUT.DEMAND_CLEAN
.Pq Event F2H , Umask 01H
-Clean L2 cache lines evicted by demand.
+Clean L2 cache lines evicted by demand.
.It Li L2_LINES_OUT.DEMAND_DIRTY
.Pq Event F2H , Umask 02H
-Dirty L2 cache lines evicted by demand.
+Dirty L2 cache lines evicted by demand.
.It Li L2_LINES_OUT.PF_CLEAN
.Pq Event F2H , Umask 04H
-Clean L2 cache lines evicted by the MLC prefetcher.
+Clean L2 cache lines evicted by the MLC prefetcher.
.It Li L2_LINES_OUT.PF_DIRTY
.Pq Event F2H , Umask 08H
-Dirty L2 cache lines evicted by the MLC prefetcher.
+Dirty L2 cache lines evicted by the MLC prefetcher.
.El
.Sh SEE ALSO
.Xr pmc 3 ,
Modified: trunk/lib/libpmc/pmc.ivybridgexeon.3
===================================================================
--- trunk/lib/libpmc/pmc.ivybridgexeon.3 2018-06-09 19:22:04 UTC (rev 10652)
+++ trunk/lib/libpmc/pmc.ivybridgexeon.3 2018-06-09 19:23:10 UTC (rev 10653)
@@ -1,3 +1,4 @@
+.\" $MidnightBSD$
.\" Copyright (c) 2013 Hiren Panchasara <hiren.panchasara at gmail.com>
.\" All rights reserved.
.\"
@@ -22,7 +23,7 @@
.\" OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
.\" SUCH DAMAGE.
.\"
-.\" $FreeBSD: release/9.2.0/lib/libpmc/pmc.ivybridgexeon.3 249492 2013-04-15 03:09:59Z hiren $
+.\" $FreeBSD: stable/10/lib/libpmc/pmc.ivybridgexeon.3 320109 2017-06-19 15:20:30Z avg $
.\"
.Dd Jan 25, 2013
.Dt PMC.IVYBRIDGEXEON 3
@@ -449,80 +450,60 @@
.It Li ILD_STALL.IQ_FULL
.Pq Event 87H , Umask 04H
Stall cycles due to IQ is full.
-.It Li BR_INST_EXEC.COND
-.Pq Event 88H , Umask 01H
-Qualify conditional near branch instructions executed, but not necessarily
-retired.
-Must combine with umask 40H, 80H.
+.It Li BR_INST_EXEC.NONTAKEN_COND
+.Pq Event 88H , Umask 41H
+Count conditional near branch instructions that were executed (but not
+necessarily retired) and not taken.
+.It Li BR_INST_EXEC.TAKEN_COND
+.Pq Event 88H , Umask 81H
+Count conditional near branch instructions that were executed (but not
+necessarily retired) and taken.
.It Li BR_INST_EXEC.DIRECT_JMP
-.Pq Event 88H , Umask 02H
-Qualify all unconditional near branch instructions excluding calls and
+.Pq Event 88H , Umask 82H
+Count all unconditional near branch instructions excluding calls and
indirect branches.
-Must combine with umask 80H.
.It Li BR_INST_EXEC.INDIRECT_JMP_NON_CALL_RET
-.Pq Event 88H , Umask 04H
-Qualify executed indirect near branch instructions that are not calls nor
+.Pq Event 88H , Umask 84H
+Count executed indirect near branch instructions that are not calls nor
returns.
-Must combine with umask 80H.
.It Li BR_INST_EXEC.RETURN_NEAR
-.Pq Event 88H , Umask 08H
-Qualify indirect near branches that have a return mnemonic.
-Must combine with umask 80H.
+.Pq Event 88H , Umask 88H
+Count indirect near branches that have a return mnemonic.
.It Li BR_INST_EXEC.DIRECT_NEAR_CALL
-.Pq Event 88H , Umask 10H
-Qualify unconditional near call branch instructions, excluding non call
+.Pq Event 88H , Umask 90H
+Count unconditional near call branch instructions, excluding non call
branch, executed.
-Must combine with umask 80H.
.It Li BR_INST_EXEC.INDIRECT_NEAR_CALL
-.Pq Event 88H , Umask 20H
-Qualify indirect near calls, including both register and memory indirect,
+.Pq Event 88H , Umask A0H
+Count indirect near calls, including both register and memory indirect,
executed.
-Must combine with umask 80H.
-.It Li BR_INST_EXEC.NONTAKEN
-.Pq Event 88H , Umask 40H
-Qualify non-taken near branches executed.
-Applicable to umask 01H only.
-.It Li BR_INST_EXEC.TAKEN
-.Pq Event 88H , Umask 80H
-Qualify taken near branches executed. Must combine with 01H,02H, 04H, 08H,
-10H, 20H.
.It Li BR_INST_EXEC.ALL_BRANCHES
.Pq Event 88H , Umask FFH
Counts all near executed branches (not necessarily retired).
-.It Li BR_MISP_EXEC.COND
-.Pq Event 89H , Umask 01H
-Qualify conditional near branch instructions mispredicted.
-Must combine with umask 40H, 80H.
+.It Li BR_MISP_EXEC.NONTAKEN_COND
+.Pq Event 89H , Umask 41H
+Count conditional near branch instructions mispredicted as nontaken.
+.It Li BR_MISP_EXEC.TAKEN_COND
+.Pq Event 89H , Umask 81H
+Count conditional near branch instructions mispredicted as taken.
.It Li BR_MISP_EXEC.INDIRECT_JMP_NON_CALL_RET
-.Pq Event 89H , Umask 04H
-Qualify mispredicted indirect near branch instructions that are not calls
+.Pq Event 89H , Umask 84H
+Count mispredicted indirect near branch instructions that are not calls
nor returns.
-Must combine with umask 80H.
.It Li BR_MISP_EXEC.RETURN_NEAR
-.Pq Event 89H , Umask 08H
-Qualify mispredicted indirect near branches that have a return mnemonic.
-Must combine with umask 80H.
+.Pq Event 89H , Umask 88H
+Count mispredicted indirect near branches that have a return mnemonic.
.It Li BR_MISP_EXEC.DIRECT_NEAR_CALL
-.Pq Event 89H , Umask 10H
-Qualify mispredicted unconditional near call branch instructions, excluding
+.Pq Event 89H , Umask 90H
+Count mispredicted unconditional near call branch instructions, excluding
non call branch, executed.
-Must combine with umask 80H.
.It Li BR_MISP_EXEC.INDIRECT_NEAR_CALL
-.Pq Event 89H , Umask 20H
-Qualify mispredicted indirect near calls, including both register and memory
+.Pq Event 89H , Umask A0H
+Count mispredicted indirect near calls, including both register and memory
indirect, executed.
-Must combine with umask 80H.
-.It Li BR_MISP_EXEC.NONTAKEN
-.Pq Event 89H , Umask 40H
-Qualify mispredicted non-taken near branches executed.
-Applicable to umask 01H only.
-.It Li BR_MISP_EXEC.TAKEN
-.Pq Event 89H , Umask 80H
-Qualify mispredicted taken near branches executed. Must combine with
-01H,02H, 04H, 08H, 10H, 20H.
.It Li BR_MISP_EXEC.ALL_BRANCHES
.Pq Event 89H , Umask FFH
-Counts all near executed branches (not necessarily retired).
+Counts all mispredicted near executed branches (not necessarily retired).
.It Li IDQ_UOPS_NOT_DELIVERED.CORE
.Pq Event 9CH , Umask 01H
Count number of non-delivered uops to RAT per thread.
@@ -738,31 +719,24 @@
.Pq Event CDH , Umask 02H
Sample stores and collect precise store operation via PEBS record.
PMC3 only.
-.It Li MEM_UOP_RETIRED.LOADS
-.Pq Event D0H , Umask 01H
-Qualify retired memory uops that are loads. Combine with umask 10H, 20H,
-40H, 80H.
-Supports PEBS.
-.It Li MEM_UOP_RETIRED.STORES
-.Pq Event D0H , Umask 02H
-Qualify retired memory uops that are stores. Combine with umask 10H, 20H,
-40H, 80H.
-.It Li MEM_UOP_RETIRED.STLB_MISS
-.Pq Event D0H , Umask 10H
-Qualify retired memory uops with STLB miss. Must combine with umask 01H,
-02H, to produce counts.
-.It Li MEM_UOP_RETIRED.LOCK
-.Pq Event D0H , Umask 20H
-Qualify retired memory uops with lock. Must combine with umask 01H, 02H, to
-produce counts.
-.It Li MEM_UOP_RETIRED.SPLIT
-.Pq Event D0H , Umask 40H
-Qualify retired memory uops with line split. Must combine with umask 01H,
-02H, to produce counts.
-.It Li MEM_UOP_RETIRED.ALL
-.Pq Event D0H , Umask 80H
-Qualify any retired memory uops. Must combine with umask 01H, 02H, to
-produce counts.
+.It Li MEM_UOPS_RETIRED.STLB_MISS_LOADS
+.Pq Event D0H , Umask 11H
+Count retired load uops that missed the STLB.
+.It Li MEM_UOPS_RETIRED.STLB_MISS_STORES
+.Pq Event D0H , Umask 12H
+Count retired store uops that missed the STLB.
+.It Li MEM_UOPS_RETIRED.SPLIT_LOADS
+.Pq Event D0H , Umask 41H
+Count retired load uops that were split across a cache line.
+.It Li MEM_UOPS_RETIRED.SPLIT_STORES
+.Pq Event D0H , Umask 42H
+Count retired store uops that were split across a cache line.
+.It Li MEM_UOPS_RETIRED.ALL_LOADS
+.Pq Event D0H , Umask 81H
+Count all retired load uops.
+.It Li MEM_UOPS_RETIRED.ALL_STORES
+.Pq Event D0H , Umask 82H
+Count all retired store uops.
.It Li MEM_LOAD_UOPS_RETIRED.L1_HIT
.Pq Event D1H , Umask 01H
Retired load uops with L1 cache hits as data sources.
Modified: trunk/lib/libpmc/pmc.k7.3
===================================================================
--- trunk/lib/libpmc/pmc.k7.3 2018-06-09 19:22:04 UTC (rev 10652)
+++ trunk/lib/libpmc/pmc.k7.3 2018-06-09 19:23:10 UTC (rev 10653)
@@ -1,3 +1,4 @@
+.\" $MidnightBSD$
.\" Copyright (c) 2003-2008 Joseph Koshy. All rights reserved.
.\"
.\" Redistribution and use in source and binary forms, with or without
@@ -21,7 +22,7 @@
.\" OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
.\" SUCH DAMAGE.
.\"
-.\" $FreeBSD: release/9.2.0/lib/libpmc/pmc.k7.3 236238 2012-05-29 14:50:21Z fabient $
+.\" $FreeBSD: stable/10/lib/libpmc/pmc.k7.3 233628 2012-03-28 20:58:30Z fabient $
.\"
.Dd October 4, 2008
.Dt PMC.K7 3
@@ -64,7 +65,6 @@
.It PMC_CAP_WRITE Ta Yes
.El
.Ss Event Qualifiers
-.Pp
Event specifiers for AMD K7 PMCs can have the following optional
qualifiers:
.Bl -tag -width indent
Property changes on: trunk/lib/libpmc/pmc.k7.3
___________________________________________________________________
Added: svn:keywords
## -0,0 +1 ##
+MidnightBSD=%H
\ No newline at end of property
Modified: trunk/lib/libpmc/pmc.k8.3
===================================================================
--- trunk/lib/libpmc/pmc.k8.3 2018-06-09 19:22:04 UTC (rev 10652)
+++ trunk/lib/libpmc/pmc.k8.3 2018-06-09 19:23:10 UTC (rev 10653)
@@ -1,3 +1,4 @@
+.\" $MidnightBSD$
.\" Copyright (c) 2003-2008 Joseph Koshy. All rights reserved.
.\"
.\" Redistribution and use in source and binary forms, with or without
@@ -21,7 +22,7 @@
.\" OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
.\" SUCH DAMAGE.
.\"
-.\" $FreeBSD: release/9.2.0/lib/libpmc/pmc.k8.3 236238 2012-05-29 14:50:21Z fabient $
+.\" $FreeBSD: stable/10/lib/libpmc/pmc.k8.3 233628 2012-03-28 20:58:30Z fabient $
.\"
.Dd October 4, 2008
.Dt PMC.K8 3
@@ -67,7 +68,6 @@
.It PMC_CAP_WRITE Ta Yes
.El
.Ss Event Qualifiers
-.Pp
Event specifiers for AMD K8 PMCs can have the following optional
qualifiers:
.Bl -tag -width indent
Property changes on: trunk/lib/libpmc/pmc.k8.3
___________________________________________________________________
Added: svn:keywords
## -0,0 +1 ##
+MidnightBSD=%H
\ No newline at end of property
Modified: trunk/lib/libpmc/pmc.mips.3
===================================================================
--- trunk/lib/libpmc/pmc.mips.3 2018-06-09 19:22:04 UTC (rev 10652)
+++ trunk/lib/libpmc/pmc.mips.3 2018-06-09 19:23:10 UTC (rev 10653)
@@ -1,3 +1,4 @@
+.\" $MidnightBSD$
.\" Copyright (c) 2010 George Neville-Neil. All rights reserved.
.\"
.\" Redistribution and use in source and binary forms, with or without
Property changes on: trunk/lib/libpmc/pmc.mips.3
___________________________________________________________________
Added: svn:keywords
## -0,0 +1 ##
+MidnightBSD=%H
\ No newline at end of property
Added: trunk/lib/libpmc/pmc.mips24k.3
===================================================================
--- trunk/lib/libpmc/pmc.mips24k.3 (rev 0)
+++ trunk/lib/libpmc/pmc.mips24k.3 2018-06-09 19:23:10 UTC (rev 10653)
@@ -0,0 +1,414 @@
+.\" $MidnightBSD$
+.\" Copyright (c) 2010 George Neville-Neil. All rights reserved.
+.\"
+.\" Redistribution and use in source and binary forms, with or without
+.\" modification, are permitted provided that the following conditions
+.\" are met:
+.\" 1. Redistributions of source code must retain the above copyright
+.\" notice, this list of conditions and the following disclaimer.
+.\" 2. Redistributions in binary form must reproduce the above copyright
+.\" notice, this list of conditions and the following disclaimer in the
+.\" documentation and/or other materials provided with the distribution.
+.\"
+.\" THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+.\" ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+.\" IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+.\" ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+.\" FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+.\" DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+.\" OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+.\" HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+.\" LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+.\" OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+.\" SUCH DAMAGE.
+.\"
+.\" $FreeBSD: stable/10/lib/libpmc/pmc.mips24k.3 233628 2012-03-28 20:58:30Z fabient $
+.\"
+.Dd March 24, 2012
+.Dt PMC.MIPS24K 3
+.Os
+.Sh NAME
+.Nm pmc.mips24k
+.Nd measurement events for
+.Tn MIPS24K
+family CPUs
+.Sh LIBRARY
+.Lb libpmc
+.Sh SYNOPSIS
+.In pmc.h
+.Sh DESCRIPTION
+MIPS PMCs are present in MIPS
+.Tn "24k"
+and other processors in the MIPS family.
+.Pp
+There are two counters supported by the hardware and each is 32 bits
+wide.
+.Pp
+MIPS PMCs are documented in
+.Rs
+.%B "MIPS32 24K Processor Core Family Software User's Manual"
+.%D December 2008
+.%Q "MIPS Technologies Inc."
+.Re
+.Ss Event Specifiers (Programmable PMCs)
+MIPS programmable PMCs support the following events:
+.Bl -tag -width indent
+.It Li CYCLE
+.Pq Event 0, Counter 0/1
+Total number of cycles.
+The performance counters are clocked by the
+top-level gated clock.
+If the core is built with that clock gater
+present, none of the counters will increment while the clock is
+stopped - due to a WAIT instruction.
+.It Li INSTR_EXECUTED
+.Pq Event 1, Counter 0/1
+Total number of instructions completed.
+.It Li BRANCH_COMPLETED
+.Pq Event 2, Counter 0
+Total number of branch instructions completed.
+.It Li BRANCH_MISPRED
+.Pq Event 2, Counter 1
+Counts all branch instructions which completed, but were mispredicted.
+.It Li RETURN
+.Pq Event 3, Counter 0
+Counts all JR R31 instructions completed.
+.It Li RETURN_MISPRED
+.Pq Event 3, Counter 1
+Counts all JR $31 instructions which completed, used the RPS for a prediction, but were mispredicted.
+.It Li RETURN_NOT_31
+.Pq Event 4, Counter 0
+Counts all JR $xx (not $31) and JALR instructions (indirect jumps).
+.It Li RETURN_NOTPRED
+.Pq Event 4, Counter 1
+If RPS use is disabled, JR $31 will not be predicted.
+.It Li ITLB_ACCESS
+.Pq Event 5, Counter 0
+Counts ITLB accesses that are due to fetches showing up in the
+instruction fetch stage of the pipeline and which do not use a fixed
+mapping or are not in unmapped space.
+If an address is fetched twice from the pipe (as in the case of a
+cache miss), that instruction willcount as 2 ITLB accesses.
+Since each fetch gets us 2 instructions,there is one access marked per double
+word.
+.It Li ITLB_MISS
+.Pq Event 5, Counter 1
+Counts all misses in the ITLB except ones that are on the back of another
+miss.
+We cannot process back to back misses and thus those are
+ignored.
+They are also ignored if there is some form of address error.
+.It Li DTLB_ACCESS
+.Pq Event 6, Counter 0
+Counts DTLB access including those in unmapped address spaces.
+.It Li DTLB_MISS
+.Pq Event 6, Counter 1
+Counts DTLB misses.
+Back to back misses that result in only one DTLB
+entry getting refilled are counted as a single miss.
+.It Li JTLB_IACCESS
+.Pq Event 7, Counter 0
+Instruction JTLB accesses are counted exactly the same as ITLB misses.
+.It Li JTLB_IMISS
+.Pq Event 7, Counter 1
+Counts instruction JTLB accesses that result in no match or a match on
+an invalid translation.
+.It Li JTLB_DACCESS
+.Pq Event 8, Counter 0
+Data JTLB accesses.
+.It Li JTLB_DMISS
+.Pq Event 8, Counter 1
+Counts data JTLB accesses that result in no match or a match on an invalid translation.
+.It Li IC_FETCH
+.Pq Event 9, Counter 0
+Counts every time the instruction cache is accessed.
+All replays,
+wasted fetches etc. are counted.
+For example, following a branch, even though the prediction is taken,
+the fall through access is counted.
+.It Li IC_MISS
+.Pq Event 9, Counter 1
+Counts all instruction cache misses that result in a bus request.
+.It Li DC_LOADSTORE
+.Pq Event 10, Counter 0
+Counts cached loads and stores.
+.It Li DC_WRITEBACK
+.Pq Event 10, Counter 1
+Counts cache lines written back to memory due to replacement or cacheops.
+.It Li DC_MISS
+.Pq Event 11, Counter 0/1
+Counts loads and stores that miss in the cache
+.It Li LOAD_MISS
+.Pq Event 13, Counter 0
+Counts number of cacheable loads that miss in the cache.
+.It Li STORE_MISS
+.Pq Event 13, Counter 1
+Counts number of cacheable stores that miss in the cache.
+.It Li INTEGER_COMPLETED
+.Pq Event 14, Counter 0
+Non-floating point, non-Coprocessor 2 instructions.
+.It Li FP_COMPLETED
+.Pq Event 14, Counter 1
+Floating point instructions completed.
+.It Li LOAD_COMPLETED
+.Pq Event 15, Counter 0
+Integer and co-processor loads completed.
+.It Li STORE_COMPLETED
+.Pq Event 15, Counter 1
+Integer and co-processor stores completed.
+.It Li BARRIER_COMPLETED
+.Pq Event 16, Counter 0
+Direct jump (and link) instructions completed.
+.It Li MIPS16_COMPLETED
+.Pq Event 16, Counter 1
+MIPS16c instructions completed.
+.It Li NOP_COMPLETED
+.Pq Event 17, Counter 0
+NOPs completed.
+This includes all instructions that normally write to a general
+purpose register, but where the destination register was set to r0.
+.It Li INTEGER_MULDIV_COMPLETED
+.Pq Event 17, Counter 1
+Integer multiply and divide instructions completed. (MULxx, DIVx, MADDx, MSUBx).
+.It Li RF_STALL
+.Pq Event 18, Counter 0
+Counts the total number of cycles where no instructions are issued
+from the IFU to ALU (the RF stage does not advance) which includes
+both of the previous two events.
+The RT_STALL is different than the sum of them though because cycles
+when both stalls are active will only be counted once.
+.It Li INSTR_REFETCH
+.Pq Event 18, Counter 1
+replay traps (other than uTLB)
+.It Li STORE_COND_COMPLETED
+.Pq Event 19, Counter 0
+Conditional stores completed.
+Counts all events, including failed stores.
+.It Li STORE_COND_FAILED
+.Pq Event 19, Counter 1
+Conditional store instruction that did not update memory.
+Note: While this event and the SC instruction count event can be configured to
+count in specific operating modes, the timing of the events is much
+different and the observed operating mode could change between them,
+causing some inaccuracy in the measured ratio.
+.It Li ICACHE_REQUESTS
+.Pq Event 20, Counter 0
+Note that this only counts PREFs that are actually attempted.
+PREFs to uncached addresses or ones with translation errors are not counted
+.It Li ICACHE_HIT
+.Pq Event 20, Counter 1
+Counts PREF instructions that hit in the cache
+.It Li L2_WRITEBACK
+.Pq Event 21, Counter 0
+Counts cache lines written back to memory due to replacement or cacheops.
+.It Li L2_ACCESS
+.Pq Event 21, Counter 1
+Number of accesses to L2 Cache.
+.It Li L2_MISS
+.Pq Event 22, Counter 0
+Number of accesses that missed in the L2 cache.
+.It Li L2_ERR_CORRECTED
+.Pq Event 22, Counter 1
+Single bit errors in L2 Cache that were detected and corrected.
+.It Li EXCEPTIONS
+.Pq Event 23, Counter 0
+Any type of exception taken.
+.It Li RF_CYCLES_STALLED
+.Pq Event 24, Counter 0
+Counts cycles where the LSU is in fixup and cannot accept a new
+instruction from the ALU.
+Fixups are replays within the LSU that occur when an instruction needs
+to re-access the cache or the DTLB.
+.It Li IFU_CYCLES_STALLED
+.Pq Event 25, Counter 0
+Counts the number of cycles where the fetch unit is not providing a
+valid instruction to the ALU.
+.It Li ALU_CYCLES_STALLED
+.Pq Event 25, Counter 1
+Counts the number of cycles where the ALU pipeline cannot advance.
+.It Li UNCACHED_LOAD
+.Pq Event 33, Counter 0
+Counts uncached and uncached accelerated loads.
+.It Li UNCACHED_STORE
+.Pq Event 33, Counter 1
+Counts uncached and uncached accelerated stores.
+.It Li CP2_REG_TO_REG_COMPLETED
+.Pq Event 35, Counter 0
+Co-processor 2 register to register instructions completed.
+.It Li MFTC_COMPLETED
+.Pq Event 35, Counter 1
+Co-processor 2 move to and from instructions as well as loads and stores.
+.It Li IC_BLOCKED_CYCLES
+.Pq Event 37, Counter 0
+Cycles when IFU stalls because an instruction miss caused the IFU not
+to have any runnable instructions.
+Ignores the stalls due to ITLB misses as well as the 4 cycles
+following a redirect.
+.It Li DC_BLOCKED_CYCLES
+.Pq Event 37, Counter 1
+Counts all cycles where integer pipeline waits on Load return data due
+to a D-cache miss.
+The LSU can signal a "long stall" on a D-cache misses, in which case
+the waiting TC might be rescheduled so other TCs can execute
+instructions till the data returns.
+.It Li L2_IMISS_STALL_CYCLES
+.Pq Event 38, Counter 0
+Cycles where the main pipeline is stalled waiting for a SYNC to complete.
+.It Li L2_DMISS_STALL_CYCLES
+.Pq Event 38, Counter 1
+Cycles where the main pipeline is stalled because of an index conflict
+in the Fill Store Buffer.
+.It Li DMISS_CYCLES
+.Pq Event 39, Counter 0
+Data miss is outstanding, but not necessarily stalling the pipeline.
+The difference between this and D$ miss stall cycles can show the gain
+from non-blocking cache misses.
+.It Li L2_MISS_CYCLES
+.Pq Event 39, Counter 1
+L2 miss is outstanding, but not necessarily stalling the pipeline.
+.It Li UNCACHED_BLOCK_CYCLES
+.Pq Event 40, Counter 0
+Cycles where the processor is stalled on an uncached fetch, load, or store.
+.It Li MDU_STALL_CYCLES
+.Pq Event 41, Counter 0
+Cycles where the processor is stalled on an uncached fetch, load, or store.
+.It Li FPU_STALL_CYCLES
+.Pq Event 41, Counter 1
+Counts all cycles where integer pipeline waits on FPU return data.
+.It Li CP2_STALL_CYCLES
+.Pq Event 42, Counter 0
+Counts all cycles where integer pipeline waits on CP2 return data.
+.It Li COREXTEND_STALL_CYCLES
+.Pq Event 42, Counter 1
+Counts all cycles where integer pipeline waits on CorExtend return data.
+.It Li ISPRAM_STALL_CYCLES
+.Pq Event 43, Counter 0
+Count all pipeline bubbles that are a result of multicycle ISPRAM
+access.
+Pipeline bubbles are defined as all cycles that IFU doesn't present an
+instruction to ALU.
+The four cycles after a redirect are not counted.
+.It Li DSPRAM_STALL_CYCLES
+.Pq Event 43, Counter 1
+Counts stall cycles created by an instruction waiting for access to DSPRAM.
+.It Li CACHE_STALL_CYCLES
+.Pq Event 44, Counter 0
+Counts all cycles the where pipeline is stalled due to CACHE
+instructions.
+Includes cycles where CACHE instructions themselves are
+stalled in the ALU, and cycles where CACHE instructions cause
+subsequent instructions to be stalled.
+.It Li LOAD_TO_USE_STALLS
+.Pq Event 45, Counter 0
+Counts all cycles where integer pipeline waits on Load return data.
+.It Li BASE_MISPRED_STALLS
+.Pq Event 45, Counter 1
+Counts stall cycles due to skewed ALU where the bypass to the address
+generation takes an extra cycle.
+.It Li CPO_READ_STALLS
+.Pq Event 46, Counter 0
+Counts all cycles where integer pipeline waits on return data from
+MFC0, RDHWR instructions.
+.It Li BRANCH_MISPRED_CYCLES
+.Pq Event 46, Counter 1
+This counts the number of cycles from a mispredicted branch until the
+next non-delay slot instruction executes.
+.It Li IFETCH_BUFFER_FULL
+.Pq Event 48, Counter 0
+Counts the number of times an instruction cache miss was detected, but
+both fill buffers were already allocated.
+.It Li FETCH_BUFFER_ALLOCATED
+.Pq Event 48, Counter 1
+Number of cycles where at least one of the IFU fill buffers is
+allocated (miss pending).
+.It Li EJTAG_ITRIGGER
+.Pq Event 49, Counter 0
+Number of times an EJTAG Instruction Trigger Point condition matched.
+.It Li EJTAG_DTRIGGER
+.Pq Event 49, Counter 1
+Number of times an EJTAG Data Trigger Point condition matched.
+.It Li FSB_LT_QUARTER
+.Pq Event 50, Counter 0
+Fill store buffer less than one quarter full.
+.It Li FSB_QUARTER_TO_HALF
+.Pq Event 50, Counter 1
+Fill store buffer between one quarter and one half full.
+.It Li FSB_GT_HALF
+.Pq Event 51, Counter 0
+Fill store buffer more than half full.
+.It Li FSB_FULL_PIPELINE_STALLS
+.Pq Event 51, Counter 1
+Cycles where the pipeline is stalled because the Fill-Store Buffer in LSU is full.
+.It Li LDQ_LT_QUARTER
+.Pq Event 52, Counter 0
+Load data queue less than one quarter full.
+.It Li LDQ_QUARTER_TO_HALF
+.Pq Event 52, Counter 1
+Load data queue between one quarter and one half full.
+.It Li LDQ_GT_HALF
+.Pq Event 53, Counter 0
+Load data queue more than one half full.
+.It Li LDQ_FULL_PIPELINE_STALLS
+.Pq Event 53, Counter 1
+Cycles where the pipeline is stalled because the Load Data Queue in the LSU is full.
+.It Li WBB_LT_QUARTER
+.Pq Event 54, Counter 0
+Write back buffer less than one quarter full.
+.It Li WBB_QUARTER_TO_HALF
+.Pq Event 54, Counter 1
+Write back buffer between one quarter and one half full.
+.It Li WBB_GT_HALF
+.Pq Event 55, Counter 0
+Write back buffer more than one half full.
+.It Li WBB_FULL_PIPELINE_STALLS
+.Pq Event 55 Counter 1
+Cycles where the pipeline is stalled because the Load Data Queue in the LSU is full.
+.It Li REQUEST_LATENCY
+.Pq Event 61, Counter 0
+Measures latency from miss detection until critical dword of response
+is returned, Only counts for cacheable reads.
+.It Li REQUEST_COUNT
+.Pq Event 61, Counter 1
+Counts number of cacheable read requests used for previous latency counter.
+.El
+.Ss Event Name Aliases
+The following table shows the mapping between the PMC-independent
+aliases supported by
+.Lb libpmc
+and the underlying hardware events used.
+.Bl -column "branch-mispredicts" "cpu_clk_unhalted.core_p"
+.It Em Alias Ta Em Event
+.It Li instructions Ta Li INSTR_EXECUTED
+.It Li branches Ta Li BRANCH_COMPLETED
+.It Li branch-mispredicts Ta Li BRANCH_MISPRED
+.El
+.Sh SEE ALSO
+.Xr pmc 3 ,
+.Xr pmc.atom 3 ,
+.Xr pmc.core 3 ,
+.Xr pmc.iaf 3 ,
+.Xr pmc.k7 3 ,
+.Xr pmc.k8 3 ,
+.Xr pmc.octeon 3 ,
+.Xr pmc.p4 3 ,
+.Xr pmc.p5 3 ,
+.Xr pmc.p6 3 ,
+.Xr pmc.soft 3 ,
+.Xr pmc.tsc 3 ,
+.Xr pmc_cpuinfo 3 ,
+.Xr pmclog 3 ,
+.Xr hwpmc 4
+.Sh HISTORY
+The
+.Nm pmc
+library first appeared in
+.Fx 6.0 .
+.Sh AUTHORS
+The
+.Lb libpmc
+library was written by
+.An "Joseph Koshy"
+.Aq jkoshy at FreeBSD.org .
+MIPS support was added by
+.An "George Neville-Neil"
+.Aq gnn at FreeBSD.org .
Property changes on: trunk/lib/libpmc/pmc.mips24k.3
___________________________________________________________________
Added: svn:eol-style
## -0,0 +1 ##
+native
\ No newline at end of property
Added: svn:keywords
## -0,0 +1 ##
+MidnightBSD=%H
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+text/plain
\ No newline at end of property
Added: trunk/lib/libpmc/pmc.octeon.3
===================================================================
--- trunk/lib/libpmc/pmc.octeon.3 (rev 0)
+++ trunk/lib/libpmc/pmc.octeon.3 2018-06-09 19:23:10 UTC (rev 10653)
@@ -0,0 +1,254 @@
+.\" $MidnightBSD$
+.\" Copyright (c) 2010 George Neville-Neil. All rights reserved.
+.\"
+.\" Redistribution and use in source and binary forms, with or without
+.\" modification, are permitted provided that the following conditions
+.\" are met:
+.\" 1. Redistributions of source code must retain the above copyright
+.\" notice, this list of conditions and the following disclaimer.
+.\" 2. Redistributions in binary form must reproduce the above copyright
+.\" notice, this list of conditions and the following disclaimer in the
+.\" documentation and/or other materials provided with the distribution.
+.\"
+.\" THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+.\" ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+.\" IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+.\" ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+.\" FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+.\" DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+.\" OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+.\" HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+.\" LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+.\" OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+.\" SUCH DAMAGE.
+.\"
+.\" $FreeBSD: stable/10/lib/libpmc/pmc.octeon.3 233628 2012-03-28 20:58:30Z fabient $
+.\"
+.Dd March 24, 2012
+.Dt PMC.OCTEON 3
+.Os
+.Sh NAME
+.Nm pmc.octeon
+.Nd measurement events for
+.Tn Octeon
+family CPUs
+.Sh LIBRARY
+.Lb libpmc
+.Sh SYNOPSIS
+.In pmc.h
+.Sh DESCRIPTION
+There are two counters per core supported by the hardware and each is 64 bits
+wide.
+.Ss Event Specifiers (Programmable PMCs)
+MIPS programmable PMCs support the following events:
+.Bl -tag -width indent
+.It Li CLK
+.Pq Event 1
+Conditionally clocked cycles (as opposed to count/cvm_count which count even with no clocks)
+.It Li ISSUE
+.Pq Event 2
+Instructions issued but not retired
+.It Li RET
+.Pq Event 3
+Instructions retired
+.It Li NISSUE
+.Pq Event 4
+Cycles no issue
+.It Li SISSUE
+.Pq Event 5
+Cycles single issue
+.It Li DISSUE
+.Pq Event 6
+Cycles dual issue
+.It Li IFI
+.Pq Event 7
+Cycle ifetch issued (but not necessarily commit to pp_mem)
+.It Li BR
+.Pq Event 8
+Branches retired
+.It Li BRMIS
+.Pq Event 9
+Branch mispredicts
+.It Li J
+.Pq Event 10
+Jumps retired
+.It Li JMIS
+.Pq Event 11
+Jumps mispredicted
+.It Li REPLAY
+.Pq Event 12
+Mem Replays
+.It Li IUNA
+.Pq Event 13
+Cycles idle due to unaligned_replays
+.It Li TRAP
+.Pq Event 14
+trap_6a signal
+.It Li UULOAD
+.Pq Event 16
+Unexpected unaligned loads (REPUN=1)
+.It Li UUSTORE
+.Pq Event 17
+Unexpected unaligned store (REPUN=1)
+.It Li ULOAD
+.Pq Event 18
+Unaligned loads (REPUN=1 or USEUN=1)
+.It Li USTORE
+.Pq Event 19
+Unaligned store (REPUN=1 or USEUN=1)
+.It Li EC
+.Pq Event 20
+Exec clocks(must set CvmCtl[DISCE] for accurate timing)
+.It Li MC
+.Pq Event 21
+Mul clocks(must set CvmCtl[DISCE] for accurate timing)
+.It Li CC
+.Pq Event 22
+Crypto clocks(must set CvmCtl[DISCE] for accurate timing)
+.It Li CSRC
+.Pq Event 23
+Issue_csr clocks(must set CvmCtl[DISCE] for accurate timing)
+.It Li CFETCH
+.Pq Event 24
+Icache committed fetches (demand+prefetch)
+.It Li CPREF
+.Pq Event 25
+Icache committed prefetches
+.It Li ICA
+.Pq Event 26
+Icache aliases
+.It Li II
+.Pq Event 27
+Icache invalidates
+.It Li IP
+.Pq Event 28
+Icache parity error
+.It Li CIMISS
+.Pq Event 29
+Cycles idle due to imiss (must set CvmCtl[DISCE] for accurate timing)
+.It Li WBUF
+.Pq Event 32
+Number of write buffer entries created
+.It Li WDAT
+.Pq Event 33
+Number of write buffer data cycles used (may need to set CvmCtl[DISCE] for accurate counts)
+.It Li WBUFLD
+.Pq Event 34
+Number of write buffer entries forced out by loads
+.It Li WBUFFL
+.Pq Event 35
+Number of cycles that there was no available write buffer entry (may need to set CvmCtl[DISCE] and CvmMemCtl[MCLK] for accurate counts)
+.It Li WBUFTR
+.Pq Event 36
+Number of stores that found no available write buffer entries
+.It Li BADD
+.Pq Event 37
+Number of address bus cycles used (may need to set CvmCtl[DISCE] for accurate counts)
+.It Li BADDL2
+.Pq Event 38
+Number of address bus cycles not reflected (i.e. destined for L2) (may need to set CvmCtl[DISCE] for accurate counts)
+.It Li BFILL
+.Pq Event 39
+Number of fill bus cycles used (may need to set CvmCtl[DISCE] for accurate counts)
+.It Li DDIDS
+.Pq Event 40
+Number of Dstream DIDs created
+.It Li IDIDS
+.Pq Event 41
+Number of Istream DIDs created
+.It Li DIDNA
+.Pq Event 42
+Number of cycles that no DIDs were available (may need to set CvmCtl[DISCE] and CvmMemCtl[MCLK] for accurate counts)
+.It Li LDS
+.Pq Event 43
+Number of load issues
+.It Li LMLDS
+.Pq Event 44
+Number of local memory load
+.It Li IOLDS
+.Pq Event 45
+Number of I/O load issues
+.It Li DMLDS
+.Pq Event 46
+Number of loads that were not prefetches and missed in the cache
+.It Li STS
+.Pq Event 48
+Number of store issues
+.It Li LMSTS
+.Pq Event 49
+Number of local memory store issues
+.It Li IOSTS
+.Pq Event 50
+Number of I/O store issues
+.It Li IOBDMA
+.Pq Event 51
+Number of IOBDMAs
+.It Li DTLB
+.Pq Event 53
+Number of dstream TLB refill, invalid, or modified exceptions
+.It Li DTLBAD
+.Pq Event 54
+Number of dstream TLB address errors
+.It Li ITLB
+.Pq Event 55
+Number of istream TLB refill, invalid, or address error exceptions
+.It Li SYNC
+.Pq Event 56
+Number of SYNC stall cycles (may need to set CvmCtl[DISCE] for accurate counts)
+.It Li SYNCIOB
+.Pq Event 57
+Number of SYNCIOBDMA stall cycles (may need to set CvmCtl[DISCE] for accurate counts)
+.It Li SYNCW
+.Pq Event 58
+Number of SYNCWs
+.It Li ERETMIS
+.Pq Event 64
+D/eret mispredicts (CN63XX specific)
+.It Li LIKMIS
+.Pq Event 65
+Branch likely mispredicts (CN63XX specific)
+.It Li HAZTR
+.Pq Event 66
+Hazard traps due to *MTC0 to CvmCtl, Perf counter control, EntryHi, or CvmMemCtl registers (CN63XX specific)
+.El
+.Ss Event Name Aliases
+The following table shows the mapping between the PMC-independent
+aliases supported by
+.Lb libpmc
+and the underlying hardware events used.
+.Bl -column "branch-mispredicts" "cpu_clk_unhalted.core_p"
+.It Em Alias Ta Em Event
+.It Li instructions Ta Li RET
+.It Li branches Ta Li BR
+.It Li branch-mispredicts Ta Li BS
+.El
+.Sh SEE ALSO
+.Xr pmc 3 ,
+.Xr pmc.atom 3 ,
+.Xr pmc.core 3 ,
+.Xr pmc.iaf 3 ,
+.Xr pmc.k7 3 ,
+.Xr pmc.k8 3 ,
+.Xr pmc.mips24k 3 ,
+.Xr pmc.p4 3 ,
+.Xr pmc.p5 3 ,
+.Xr pmc.p6 3 ,
+.Xr pmc.soft 3 ,
+.Xr pmc.tsc 3 ,
+.Xr pmc_cpuinfo 3 ,
+.Xr pmclog 3 ,
+.Xr hwpmc 4
+.Sh HISTORY
+The
+.Nm pmc
+library first appeared in
+.Fx 6.0 .
+.Sh AUTHORS
+The
+.Lb libpmc
+library was written by
+.An "Joseph Koshy"
+.Aq jkoshy at FreeBSD.org .
+MIPS support was added by
+.An "George Neville-Neil"
+.Aq gnn at FreeBSD.org .
Property changes on: trunk/lib/libpmc/pmc.octeon.3
___________________________________________________________________
Added: svn:eol-style
## -0,0 +1 ##
+native
\ No newline at end of property
Added: svn:keywords
## -0,0 +1 ##
+MidnightBSD=%H
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+text/plain
\ No newline at end of property
Modified: trunk/lib/libpmc/pmc.p4.3
===================================================================
--- trunk/lib/libpmc/pmc.p4.3 2018-06-09 19:22:04 UTC (rev 10652)
+++ trunk/lib/libpmc/pmc.p4.3 2018-06-09 19:23:10 UTC (rev 10653)
@@ -1,3 +1,4 @@
+.\" $MidnightBSD$
.\" Copyright (c) 2003-2008 Joseph Koshy. All rights reserved.
.\"
.\" Redistribution and use in source and binary forms, with or without
@@ -21,7 +22,7 @@
.\" OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
.\" SUCH DAMAGE.
.\"
-.\" $FreeBSD: release/9.2.0/lib/libpmc/pmc.p4.3 236238 2012-05-29 14:50:21Z fabient $
+.\" $FreeBSD: stable/10/lib/libpmc/pmc.p4.3 233628 2012-03-28 20:58:30Z fabient $
.\"
.Dd October 4, 2008
.Dt PMC.P4 3
@@ -90,7 +91,6 @@
.It PMC_CAP_WRITE Ta Yes
.El
.Ss Event Qualifiers
-.Pp
Event specifiers for Intel P4 PMCs can have the following common
qualifiers:
.Bl -tag -width indent
Property changes on: trunk/lib/libpmc/pmc.p4.3
___________________________________________________________________
Added: svn:keywords
## -0,0 +1 ##
+MidnightBSD=%H
\ No newline at end of property
Modified: trunk/lib/libpmc/pmc.p5.3
===================================================================
--- trunk/lib/libpmc/pmc.p5.3 2018-06-09 19:22:04 UTC (rev 10652)
+++ trunk/lib/libpmc/pmc.p5.3 2018-06-09 19:23:10 UTC (rev 10653)
@@ -1,3 +1,4 @@
+.\" $MidnightBSD$
.\" Copyright (c) 2003-2008 Joseph Koshy. All rights reserved.
.\"
.\" Redistribution and use in source and binary forms, with or without
@@ -21,7 +22,7 @@
.\" OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
.\" SUCH DAMAGE.
.\"
-.\" $FreeBSD: release/9.2.0/lib/libpmc/pmc.p5.3 236238 2012-05-29 14:50:21Z fabient $
+.\" $FreeBSD: stable/10/lib/libpmc/pmc.p5.3 233628 2012-03-28 20:58:30Z fabient $
.\"
.Dd October 4, 2008
.Dt PMC 3
Property changes on: trunk/lib/libpmc/pmc.p5.3
___________________________________________________________________
Added: svn:keywords
## -0,0 +1 ##
+MidnightBSD=%H
\ No newline at end of property
Modified: trunk/lib/libpmc/pmc.p6.3
===================================================================
--- trunk/lib/libpmc/pmc.p6.3 2018-06-09 19:22:04 UTC (rev 10652)
+++ trunk/lib/libpmc/pmc.p6.3 2018-06-09 19:23:10 UTC (rev 10653)
@@ -1,3 +1,4 @@
+.\" $MidnightBSD$
.\" Copyright (c) 2003-2008 Joseph Koshy. All rights reserved.
.\"
.\" Redistribution and use in source and binary forms, with or without
@@ -21,7 +22,7 @@
.\" OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
.\" SUCH DAMAGE.
.\"
-.\" $FreeBSD: release/9.2.0/lib/libpmc/pmc.p6.3 236238 2012-05-29 14:50:21Z fabient $
+.\" $FreeBSD: stable/10/lib/libpmc/pmc.p6.3 233628 2012-03-28 20:58:30Z fabient $
.\"
.Dd October 4, 2008
.Dt PMC.P6 3
Property changes on: trunk/lib/libpmc/pmc.p6.3
___________________________________________________________________
Added: svn:keywords
## -0,0 +1 ##
+MidnightBSD=%H
\ No newline at end of property
Modified: trunk/lib/libpmc/pmc.sandybridge.3
===================================================================
--- trunk/lib/libpmc/pmc.sandybridge.3 2018-06-09 19:22:04 UTC (rev 10652)
+++ trunk/lib/libpmc/pmc.sandybridge.3 2018-06-09 19:23:10 UTC (rev 10653)
@@ -1,3 +1,4 @@
+.\" $MidnightBSD$
.\" Copyright (c) 2012 Davide Italiano <davide at FreeBSD.org>
.\" All rights reserved.
.\"
@@ -22,7 +23,7 @@
.\" OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
.\" SUCH DAMAGE.
.\"
-.\" $FreeBSD: release/9.2.0/lib/libpmc/pmc.sandybridge.3 249492 2013-04-15 03:09:59Z hiren $
+.\" $FreeBSD: stable/10/lib/libpmc/pmc.sandybridge.3 320106 2017-06-19 15:13:20Z avg $
.\"
.Dd October 19, 2012
.Dt PMC.SANDYBRIDGE 3
@@ -497,80 +498,60 @@
.It Li ILD_STALL.IQ_FULL
.Pq Event 87H, Umask 04H
Stall cycles due to IQ is full.
-.It Li BR_INST_EXEC.COND
-.Pq Event 88H, Umask 01H
-Qualify conditional near branch instructions executed, but not necessarily
-retired.
-Must combine with umask 40H, 80H
+.It Li BR_INST_EXEC.NONTAKEN_COND
+.Pq Event 88H , Umask 41H
+Count conditional near branch instructions that were executed (but not
+necessarily retired) and not taken.
+.It Li BR_INST_EXEC.TAKEN_COND
+.Pq Event 88H , Umask 81H
+Count conditional near branch instructions that were executed (but not
+necessarily retired) and taken.
.It Li BR_INST_EXEC.DIRECT_JMP
-.Pq Event 88H, Umask 02H
-Qualify all unconditional near branch instructions excluding calls and indirect
-branches.
-Must combine with umask 80H
+.Pq Event 88H , Umask 82H
+Count all unconditional near branch instructions excluding calls and
+indirect branches.
.It Li BR_INST_EXEC.INDIRECT_JMP_NON_CALL_RET
-.Pq Event 88H, Umask 04H
-Qualify executed indirect near branch instructions that are not calls nor
+.Pq Event 88H , Umask 84H
+Count executed indirect near branch instructions that are not calls nor
returns.
-Must combine with umask 80H
.It Li BR_INST_EXEC.RETURN_NEAR
-.Pq Event 88H, Umask 08H
-Qualify indirect near branches that have a return mnemonic.
-Must combine with umask 80H
+.Pq Event 88H , Umask 88H
+Count indirect near branches that have a return mnemonic.
.It Li BR_INST_EXEC.DIRECT_NEAR_CALL
-.Pq Event 88H, Umask 10H
-Qualify unconditional near call branch instructions, excluding non call branch,
-executed.
-Must combine with umask 80H
+.Pq Event 88H , Umask 90H
+Count unconditional near call branch instructions, excluding non call
+branch, executed.
.It Li BR_INST_EXEC.INDIRECT_NEAR_CALL
-.Pq Event 88H, Umask 20H
-Qualify indirect near calls, including both register and memory indirect,
+.Pq Event 88H , Umask A0H
+Count indirect near calls, including both register and memory indirect,
executed.
-Must combine with umask 80H
-.It Li BR_INST_EXEC.NONTAKEN
-.Pq Event 88H, Umask 40H
-Qualify non-taken near branches executed.
-Applicable to umask 01H only
-.It Li BR_INST_EXEC.TAKEN
-.Pq Event 88H, Umask 80H
-Qualify taken near branches executed.
-Must combine with 01H,02H, 04H, 08H, 10H, 20H
-.It Li BR_INST_EXE.ALL_BRANCHES
-.Pq Event 88H, Umask FFH
+.It Li BR_INST_EXEC.ALL_BRANCHES
+.Pq Event 88H , Umask FFH
Counts all near executed branches (not necessarily retired).
-.It Li BR_MISP_EXEC.COND
-.Pq Event 89H, Umask 01H
-Qualify conditional near branch instructions mispredicted.
-Must combine with umask 40H, 80H
+.It Li BR_MISP_EXEC.NONTAKEN_COND
+.Pq Event 89H , Umask 41H
+Count conditional near branch instructions mispredicted as nontaken.
+.It Li BR_MISP_EXEC.TAKEN_COND
+.Pq Event 89H , Umask 81H
+Count conditional near branch instructions mispredicted as taken.
.It Li BR_MISP_EXEC.INDIRECT_JMP_NON_CALL_RET
-.Pq Event 89H, Umask 04H
-Qualify mispredicted indirect near branch instructions that are not calls nor
-returns.
-Must combine with umask 80H
+.Pq Event 89H , Umask 84H
+Count mispredicted indirect near branch instructions that are not calls
+nor returns.
.It Li BR_MISP_EXEC.RETURN_NEAR
-.Pq Event 89H, Umask 08H
-Qualify mispredicted indirect near branches that have a return mnemonic.
-Must combine with umask 80H
+.Pq Event 89H , Umask 88H
+Count mispredicted indirect near branches that have a return mnemonic.
.It Li BR_MISP_EXEC.DIRECT_NEAR_CALL
-.Pq Event 89H, Umask 10H
-Qualify mispredicted unconditional near call branch instructions, excluding non
-call branch, executed.
-Must combine with umask 80H
+.Pq Event 89H , Umask 90H
+Count mispredicted unconditional near call branch instructions, excluding
+non call branch, executed.
.It Li BR_MISP_EXEC.INDIRECT_NEAR_CALL
-.Pq Event 89H, Umask 20H
-Qualify mispredicted indirect near calls, including both register and memory
+.Pq Event 89H , Umask A0H
+Count mispredicted indirect near calls, including both register and memory
indirect, executed.
-Must combine with umask 80H
-.It Li BR_MISP_EXEC.NONTAKEN
-.Pq Event 89H, Umask 40H
-Qualify mispredicted non-taken near branches executed.
-Applicable to umask 01H only
-.It Li BR_MISP_EXEC.TAKEN
-.Pq Event 89H, Umask 80H
-Qualify mispredicted taken near branches executed.
-Must combine with 01H,02H, 04H, 08H, 10H, 20H
.It Li BR_MISP_EXEC.ALL_BRANCHES
-.Pq Event 89H, Umask FFH
-Counts all near executed branches (not necessarily retired).
+.Pq Event 89H , Umask FFH
+Counts all mispredicted near executed branches (not necessarily retired).
.It Li IDQ_UOPS_NOT_DELIVERED.CORE
.Pq Event 9CH, Umask 01H
Count number of non-delivered uops to RAT per thread.
Property changes on: trunk/lib/libpmc/pmc.sandybridge.3
___________________________________________________________________
Added: svn:keywords
## -0,0 +1 ##
+MidnightBSD=%H
\ No newline at end of property
Modified: trunk/lib/libpmc/pmc.sandybridgeuc.3
===================================================================
--- trunk/lib/libpmc/pmc.sandybridgeuc.3 2018-06-09 19:22:04 UTC (rev 10652)
+++ trunk/lib/libpmc/pmc.sandybridgeuc.3 2018-06-09 19:23:10 UTC (rev 10653)
@@ -1,3 +1,4 @@
+.\" $MidnightBSD$
.\" Copyright (c) 2012 Davide Italiano <davide at FreeBSD.org>
.\" All rights reserved.
.\"
@@ -22,7 +23,7 @@
.\" OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
.\" SUCH DAMAGE.
.\"
-.\" $FreeBSD: release/9.2.0/lib/libpmc/pmc.sandybridgeuc.3 242594 2012-11-05 01:05:14Z sbruno $
+.\" $FreeBSD: stable/10/lib/libpmc/pmc.sandybridgeuc.3 241741 2012-10-19 17:21:10Z sbruno $
.\"
.Dd October 19, 2012
.Dt PMC.SANDYBRIDGEUC 3
@@ -111,7 +112,7 @@
.Bl -tag -width indent
.It Li CBO_XSNP_RESPONSE.RSPIHITI
.Pq Event 22H, Umask 01H
-Snoop responses received from processor cores to requests initiated by this
+Snoop responses received from processor cores to requests initiated by this
Cbox.
Must combine with one of the umask values of 20H, 40H, 80H
.It Li CBO_XSNP_RESPONSE.RSPIHITFSE
@@ -126,15 +127,15 @@
.Pq Event 22H, Umask 01H
.It Li CBO_XSNP_RESPONSE.AND_EXTERNAL
.Pq Event 22H, Umask 20H
-Filter on cross-core snoops resulted in external snoop request.
+Filter on cross-core snoops resulted in external snoop request.
Must combine with at least one of 01H, 02H, 04H, 08H, 10H
.It Li CBO_XSNP_RESPONSE.AND_XCORE
.Pq Event 22H, Umask 40H
-Filter on cross-core snoops resulted in core request.
+Filter on cross-core snoops resulted in core request.
Must combine with at least one of 01H, 02H, 04H, 08H, 10H
.It Li CBO_XSNP_RESPONSE.AND_XCORE
.Pq Event 22H, Umask 80H
-Filter on cross-core snoops resulted in LLC evictions.
+Filter on cross-core snoops resulted in LLC evictions.
Must combine with at least one of 01H, 02H, 04H, 08H, 10H
.It Li CBO_CACHE_LOOKUP.M
.Pq Event 34H, Umask 01H
@@ -141,47 +142,47 @@
LLC lookup request that access cache and found line in M-state.
Must combine with one of the umask values of 10H, 20H, 40H, 80H
.It Li CBO_CACHE_LOOKUP.E
-.Pq Event 34H, Umask 02H
+.Pq Event 34H, Umask 02H
LLC lookup request that access cache and found line in E-state.
Must combine with one of the umask values of 10H, 20H, 40H, 80H
.It Li CBO_CACHE_LOOKUP.S
-.Pq Event 34H, Umask 04H
+.Pq Event 34H, Umask 04H
LLC lookup request that access cache and found line in S-state.
Must combine with one of the umask values of 10H, 20H, 40H, 80H
.It Li CBO_CACHE_LOOKUP.I
-.Pq Event 34H, Umask 08H
+.Pq Event 34H, Umask 08H
LLC lookup request that access cache and found line in I-state.
Must combine with one of the umask values of 10H, 20H, 40H, 80H
.It Li CBO_CACHE_LOOKUP.AND_READ
.Pq Event 34H, Umask 10H
-Filter on processor core initiated cacheable read requests.
+Filter on processor core initiated cacheable read requests.
Must combine with at least one of 01H, 02H, 04H, 08H
.It Li CBO_CACHE_LOOKUP_AND_READ2
.Pq Event 34H, Umask 20H
-Filter on processor core initiated cacheable write requests.
+Filter on processor core initiated cacheable write requests.
Must combine with at least one of 01H, 02H, 04H, 08H
.It Li CBO_CACHE_LOOKUP.AND_EXTSNP
.Pq Event 34H, Umask 40H
-Filter on external snoop requests.
+Filter on external snoop requests.
Must combine with at least one of 01H, 02H, 04H, 08H
.It Li CBO_CACHE_LOOKUP.AND_ANY
.Pq Event 34H, Umask 80H
-Filter on any IRQ or IPQ initiated requests including uncacheable,
-noncoherent requests.
+Filter on any IRQ or IPQ initiated requests including uncacheable,
+noncoherent requests.
Must combine with at least one of 01H, 02H, 04H, 08H
.It Li IMPH_CBO_TRK_OCCUPANCY.ALL
.Pq Event 80H, Umask 01H
-Counts cycles weighted by the number of core-outgoing valid entries.
-Valid entries are between allocation to the first of IDIO or DRSO messages.
+Counts cycles weighted by the number of core-outgoing valid entries.
+Valid entries are between allocation to the first of IDIO or DRSO messages.
Accounts for coherent and incoherent traffic.
Counter 0 only
.It Li IMPH_CBO_TRK_REQUEST.ALL
.Pq Event 81H, Umask 01H
-Counts the number of core-outgoing entries.
+Counts the number of core-outgoing entries.
Accounts for coherent and incoherent traffic.
.It Li IMPH_CBO_TRK_REQUEST.WRITES
.Pq Event 81H, Umask 20H
-Counts the number of allocated write entries, include full, partial, and
+Counts the number of allocated write entries, include full, partial, and
evictions.
.It Li IMPH_CBO_TRK_REQUEST.EVICTIONS
.Pq Event 81H, Umask 80H
@@ -228,8 +229,7 @@
library was written by
.An "Joseph Koshy"
.Aq jkoshy at FreeBSD.org .
-The support for the
-.Lb Sandy Bridge
+The support for the Sandy Bridge
microarchitecture was added by
.An "Davide Italiano"
.Aq davide at FreeBSD.org .
Property changes on: trunk/lib/libpmc/pmc.sandybridgeuc.3
___________________________________________________________________
Added: svn:keywords
## -0,0 +1 ##
+MidnightBSD=%H
\ No newline at end of property
Modified: trunk/lib/libpmc/pmc.sandybridgexeon.3
===================================================================
--- trunk/lib/libpmc/pmc.sandybridgexeon.3 2018-06-09 19:22:04 UTC (rev 10652)
+++ trunk/lib/libpmc/pmc.sandybridgexeon.3 2018-06-09 19:23:10 UTC (rev 10653)
@@ -1,3 +1,4 @@
+.\" $MidnightBSD$
.\" Copyright (c) 2012 Hiren Panchasara <hiren.panchasara at gmail.com>
.\" All rights reserved.
.\"
@@ -22,7 +23,7 @@
.\" OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
.\" SUCH DAMAGE.
.\"
-.\" $FreeBSD: release/9.2.0/lib/libpmc/pmc.sandybridgexeon.3 249964 2013-04-27 01:48:09Z bryanv $
+.\" $FreeBSD: stable/10/lib/libpmc/pmc.sandybridgexeon.3 320106 2017-06-19 15:13:20Z avg $
.\"
.Dd October 18, 2012
.Dt PMC.SANDYBRIDGEXEON 3
@@ -543,73 +544,60 @@
.It Li ILD_STALL.IQ_FULL
.Pq Event 87H , Umask 04H
Stall cycles due to IQ is full.
-.It Li BR_INST_EXEC.COND
-.Pq Event 88H , Umask 01H
-Qualify conditional near branch instructions
-executed, but not necessarily retired.
+.It Li BR_INST_EXEC.NONTAKEN_COND
+.Pq Event 88H , Umask 41H
+Count conditional near branch instructions that were executed (but not
+necessarily retired) and not taken.
+.It Li BR_INST_EXEC.TAKEN_COND
+.Pq Event 88H , Umask 81H
+Count conditional near branch instructions that were executed (but not
+necessarily retired) and taken.
.It Li BR_INST_EXEC.DIRECT_JMP
-.Pq Event 88H , Umask 02H
-Qualify all unconditional near branch instructions
-excluding calls and indirect branches.
+.Pq Event 88H , Umask 82H
+Count all unconditional near branch instructions excluding calls and
+indirect branches.
.It Li BR_INST_EXEC.INDIRECT_JMP_NON_CALL_RET
-.Pq Event 88H , Umask 04H
-Qualify executed indirect near branch instructions
-that are not calls nor returns.
+.Pq Event 88H , Umask 84H
+Count executed indirect near branch instructions that are not calls nor
+returns.
.It Li BR_INST_EXEC.RETURN_NEAR
-.Pq Event 88H , Umask 08H
-Qualify indirect near branches that have a return
-mnemonic.
+.Pq Event 88H , Umask 88H
+Count indirect near branches that have a return mnemonic.
.It Li BR_INST_EXEC.DIRECT_NEAR_CALL
-.Pq Event 88H , Umask 10H
-Qualify unconditional near call branch instructions,
-excluding non call branch, executed.
+.Pq Event 88H , Umask 90H
+Count unconditional near call branch instructions, excluding non call
+branch, executed.
.It Li BR_INST_EXEC.INDIRECT_NEAR_CALL
-.Pq Event 88H , Umask 20H
-Qualify indirect near calls, including both register
-and memory indirect, executed.
-.It Li BR_INST_EXEC.NONTAKEN
-.Pq Event 88H , Umask 40H
-Qualify non-taken near branches executed.
-.It Li BR_INST_EXEC.TAKEN
-.Pq Event 88H , Umask 80H
-Qualify taken near branches executed. Must
-combine with 01H,02H, 04H, 08H, 10H, 20H.
-.It Li BR_INST_EXE.ALL_BRANCHES
+.Pq Event 88H , Umask A0H
+Count indirect near calls, including both register and memory indirect,
+executed.
+.It Li BR_INST_EXEC.ALL_BRANCHES
.Pq Event 88H , Umask FFH
-Counts all near executed branches (not necessarily
-retired).
-.It Li BR_MISP_EXEC.COND
-.Pq Event 89H , Umask 01H
-Qualify conditional near branch instructions
-mispredicted.
+Counts all near executed branches (not necessarily retired).
+.It Li BR_MISP_EXEC.NONTAKEN_COND
+.Pq Event 89H , Umask 41H
+Count conditional near branch instructions mispredicted as nontaken.
+.It Li BR_MISP_EXEC.TAKEN_COND
+.Pq Event 89H , Umask 81H
+Count conditional near branch instructions mispredicted as taken.
.It Li BR_MISP_EXEC.INDIRECT_JMP_NON_CALL_RET
-.Pq Event 89H , Umask 04H
-Qualify mispredicted indirect near branch
-instructions that are not calls nor returns.
+.Pq Event 89H , Umask 84H
+Count mispredicted indirect near branch instructions that are not calls
+nor returns.
.It Li BR_MISP_EXEC.RETURN_NEAR
-.Pq Event 89H , Umask 08H
-Qualify mispredicted indirect near branches that
-have a return mnemonic.
+.Pq Event 89H , Umask 88H
+Count mispredicted indirect near branches that have a return mnemonic.
.It Li BR_MISP_EXEC.DIRECT_NEAR_CALL
-.Pq Event 89H , Umask 10H
-Qualify mispredicted unconditional near call branch
-instructions, excluding non call branch, executed.
+.Pq Event 89H , Umask 90H
+Count mispredicted unconditional near call branch instructions, excluding
+non call branch, executed.
.It Li BR_MISP_EXEC.INDIRECT_NEAR_CALL
-.Pq Event 89H , Umask 20H
-Qualify mispredicted indirect near calls, including
-both register and memory indirect, executed.
-.It Li BR_MISP_EXEC.NONTAKEN
-.Pq Event 89H , Umask 40H
-Qualify mispredicted non-taken near branches
-executed,.
-.It Li BR_MISP_EXEC.TAKEN
-.Pq Event 89H , Umask 80H
-Qualify mispredicted taken near branches executed.
-Must combine with 01H,02H, 04H, 08H, 10H, 20H
+.Pq Event 89H , Umask A0H
+Count mispredicted indirect near calls, including both register and memory
+indirect, executed.
.It Li BR_MISP_EXEC.ALL_BRANCHES
.Pq Event 89H , Umask FFH
-Counts all near executed branches (not necessarily
-retired).
+Counts all mispredicted near executed branches (not necessarily retired).
.It Li IDQ_UOPS_NOT_DELIVERED.CORE
.Pq Event 9CH , Umask 01H
Count number of non-delivered uops to RAT per
Modified: trunk/lib/libpmc/pmc.soft.3
===================================================================
--- trunk/lib/libpmc/pmc.soft.3 2018-06-09 19:22:04 UTC (rev 10652)
+++ trunk/lib/libpmc/pmc.soft.3 2018-06-09 19:23:10 UTC (rev 10653)
@@ -1,3 +1,4 @@
+.\" $MidnightBSD$
.\" Copyright (c) 2012 Fabien Thomas. All rights reserved.
.\"
.\" Redistribution and use in source and binary forms, with or without
@@ -21,11 +22,11 @@
.\" OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
.\" SUCH DAMAGE.
.\"
-.\" $FreeBSD: release/9.2.0/lib/libpmc/pmc.soft.3 250600 2013-05-13 15:18:36Z fabient $
+.\" $FreeBSD: stable/10/lib/libpmc/pmc.soft.3 247329 2013-02-26 18:13:42Z mav $
.\"
.Dd February 26, 2013
+.Dt PMC.SOFT 3
.Os
-.Dt PMC.SOFT 3
.Sh NAME
.Nm pmc.soft
.Nd measurements using software based events
Property changes on: trunk/lib/libpmc/pmc.soft.3
___________________________________________________________________
Added: svn:keywords
## -0,0 +1 ##
+MidnightBSD=%H
\ No newline at end of property
Modified: trunk/lib/libpmc/pmc.tsc.3
===================================================================
--- trunk/lib/libpmc/pmc.tsc.3 2018-06-09 19:22:04 UTC (rev 10652)
+++ trunk/lib/libpmc/pmc.tsc.3 2018-06-09 19:23:10 UTC (rev 10653)
@@ -1,3 +1,4 @@
+.\" $MidnightBSD$
.\" Copyright (c) 2003-2008 Joseph Koshy. All rights reserved.
.\"
.\" Redistribution and use in source and binary forms, with or without
@@ -21,7 +22,7 @@
.\" OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
.\" SUCH DAMAGE.
.\"
-.\" $FreeBSD: release/9.2.0/lib/libpmc/pmc.tsc.3 236238 2012-05-29 14:50:21Z fabient $
+.\" $FreeBSD: stable/10/lib/libpmc/pmc.tsc.3 233628 2012-03-28 20:58:30Z fabient $
.\"
.Dd October 4, 2008
.Dt PMC.TSC 3
Property changes on: trunk/lib/libpmc/pmc.tsc.3
___________________________________________________________________
Added: svn:keywords
## -0,0 +1 ##
+MidnightBSD=%H
\ No newline at end of property
Modified: trunk/lib/libpmc/pmc.ucf.3
===================================================================
--- trunk/lib/libpmc/pmc.ucf.3 2018-06-09 19:22:04 UTC (rev 10652)
+++ trunk/lib/libpmc/pmc.ucf.3 2018-06-09 19:23:10 UTC (rev 10653)
@@ -1,3 +1,4 @@
+.\" $MidnightBSD$
.\" Copyright (c) 2010 Fabien Thomas. All rights reserved.
.\"
.\" Redistribution and use in source and binary forms, with or without
@@ -21,7 +22,7 @@
.\" OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
.\" SUCH DAMAGE.
.\"
-.\" $FreeBSD: release/9.2.0/lib/libpmc/pmc.ucf.3 236238 2012-05-29 14:50:21Z fabient $
+.\" $FreeBSD: stable/10/lib/libpmc/pmc.ucf.3 233628 2012-03-28 20:58:30Z fabient $
.\"
.Dd March 30, 2010
.Dt PMC.UCF 3
Property changes on: trunk/lib/libpmc/pmc.ucf.3
___________________________________________________________________
Added: svn:keywords
## -0,0 +1 ##
+MidnightBSD=%H
\ No newline at end of property
Modified: trunk/lib/libpmc/pmc.westmere.3
===================================================================
--- trunk/lib/libpmc/pmc.westmere.3 2018-06-09 19:22:04 UTC (rev 10652)
+++ trunk/lib/libpmc/pmc.westmere.3 2018-06-09 19:23:10 UTC (rev 10653)
@@ -1,3 +1,4 @@
+.\" $MidnightBSD$
.\" Copyright (c) 2010 Fabien Thomas. All rights reserved.
.\"
.\" Redistribution and use in source and binary forms, with or without
@@ -21,7 +22,7 @@
.\" OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
.\" SUCH DAMAGE.
.\"
-.\" $FreeBSD: release/9.2.0/lib/libpmc/pmc.westmere.3 236238 2012-05-29 14:50:21Z fabient $
+.\" $FreeBSD: stable/10/lib/libpmc/pmc.westmere.3 233628 2012-03-28 20:58:30Z fabient $
.\"
.Dd February 25, 2012
.Dt PMC.WESTMERE 3
Property changes on: trunk/lib/libpmc/pmc.westmere.3
___________________________________________________________________
Added: svn:keywords
## -0,0 +1 ##
+MidnightBSD=%H
\ No newline at end of property
Modified: trunk/lib/libpmc/pmc.westmereuc.3
===================================================================
--- trunk/lib/libpmc/pmc.westmereuc.3 2018-06-09 19:22:04 UTC (rev 10652)
+++ trunk/lib/libpmc/pmc.westmereuc.3 2018-06-09 19:23:10 UTC (rev 10653)
@@ -1,3 +1,4 @@
+.\" $MidnightBSD$
.\" Copyright (c) 2010 Fabien Thomas. All rights reserved.
.\"
.\" Redistribution and use in source and binary forms, with or without
@@ -21,7 +22,7 @@
.\" OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
.\" SUCH DAMAGE.
.\"
-.\" $FreeBSD: release/9.2.0/lib/libpmc/pmc.westmereuc.3 236238 2012-05-29 14:50:21Z fabient $
+.\" $FreeBSD: stable/10/lib/libpmc/pmc.westmereuc.3 233628 2012-03-28 20:58:30Z fabient $
.\"
.Dd March 24, 2010
.Dt PMC.WESTMEREUC 3
Property changes on: trunk/lib/libpmc/pmc.westmereuc.3
___________________________________________________________________
Added: svn:keywords
## -0,0 +1 ##
+MidnightBSD=%H
\ No newline at end of property
Added: trunk/lib/libpmc/pmc.xscale.3
===================================================================
--- trunk/lib/libpmc/pmc.xscale.3 (rev 0)
+++ trunk/lib/libpmc/pmc.xscale.3 2018-06-09 19:23:10 UTC (rev 10653)
@@ -0,0 +1,158 @@
+.\" $MidnightBSD$
+.\" Copyright (c) 2009, 2010 Rui Paulo. All rights reserved.
+.\"
+.\" Redistribution and use in source and binary forms, with or without
+.\" modification, are permitted provided that the following conditions
+.\" are met:
+.\" 1. Redistributions of source code must retain the above copyright
+.\" notice, this list of conditions and the following disclaimer.
+.\" 2. Redistributions in binary form must reproduce the above copyright
+.\" notice, this list of conditions and the following disclaimer in the
+.\" documentation and/or other materials provided with the distribution.
+.\"
+.\" THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+.\" ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+.\" IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+.\" ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+.\" FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+.\" DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+.\" OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+.\" HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+.\" LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+.\" OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+.\" SUCH DAMAGE.
+.\"
+.\" $FreeBSD: stable/10/lib/libpmc/pmc.xscale.3 233648 2012-03-29 05:02:12Z eadler $
+.\"
+.Dd December 23, 2009
+.Dt PMC.XSCALE 3
+.Os
+.Sh NAME
+.Nm pmc.xscale
+.Nd measurement events for
+.Tn Intel
+.Tn XScale
+family CPUs
+.Sh LIBRARY
+.Lb libpmc
+.Sh SYNOPSIS
+.In pmc.h
+.Sh DESCRIPTION
+.Tn Intel XScale
+CPUs are ARM CPUs based on the ARMv5e core.
+.Pp
+Second generation cores have 2 counters, while third generation cores
+have 4 counters.
+Third generation cores also have an increased number of PMC events.
+.Pp
+.Tn Intel XScale
+PMCs are documented in
+.Rs
+.%B "3rd Generation Intel XScale Microarchitecture Developer's Manual"
+.%D May 2007
+.Re
+.Ss Event Specifiers (Programmable PMCs)
+.Tn Intel XScale
+programmable PMCs support the following events:
+.Bl -tag -width indent
+.It Li IC_FETCH
+External memory fetch due to L1 instruction cache miss.
+.It Li IC_MISS
+Instruction cache or TLB miss.
+.It Li DATA_DEPENDENCY_STALLED
+A data dependency stalled
+.It Li ITLB_MISS
+Instruction TLB miss.
+.It Li DTLB_MISS
+Data TLB miss.
+.It Li BRANCH_RETIRED
+Branch instruction retired (executed).
+.It Li BRANCH_MISPRED
+Branch mispredicted.
+.It Li INSTR_RETIRED
+Instructions retired (executed).
+.It Li DC_FULL_CYCLE
+L1 data cache buffer full stall.
+Event occurs on every cycle the
+condition is present.
+.It Li DC_FULL_CONTIG
+L1 data cache buffer full stall.
+Event occurs once for each contiguous sequence of this type of stall.
+.It Li DC_ACCESS
+L1 data cache access, not including cache operations.
+.It Li DC_MISS
+L1 data cache miss, not including cache operations.
+.It Li DC_WRITEBACK
+L1 data cache write-back.
+Occurs for each cache line that's written back from the cache.
+.It Li PC_CHANGE
+Software changed the program counter.
+.It Li BRANCH_RETIRED_ALL
+Branch instruction retired (executed).
+This event counts all branch instructions, indirect or direct.
+.It Li INSTR_CYCLE
+Count the number of microarchitecture cycles each instruction requires
+to issue.
+.It Li CP_STALL
+Coprocessor stalled the instruction pipeline.
+.It Li PC_CHANGE_ALL
+Software changed the program counter (includes exceptions).
+.It Li PIPELINE_FLUSH
+Pipeline flushes due to mispredictions or exceptions.
+.It Li BACKEND_STALL
+Backend stalled the instruction pipeline.
+.It Li MULTIPLIER_USE
+Multiplier used.
+.It Li MULTIPLIER_STALLED
+Multiplier stalled the instruction pipeline.
+.It Li DATA_CACHE_STALLED
+Data cache stalled the instruction pipeline.
+.It Li L2_CACHE_REQ
+L2 cache request, not including cache operations.
+.It Li L2_CACHE_MISS
+L2 cache miss, not including cache operations.
+.It Li ADDRESS_BUS_TRANS
+Address bus transaction.
+.It Li SELF_ADDRESS_BUS_TRANS
+Self initiated address bus transaction.
+.It Li DATA_BUS_TRANS
+Data bus transaction.
+.El
+.Ss Event Name Aliases
+The following table shows the mapping between the PMC-independent
+aliases supported by
+.Lb libpmc
+and the underlying hardware events used.
+.Bl -column "branch-mispredicts" "BRANCH_MISPRED"
+.It Em Alias Ta Em Event
+.It Li branches Ta Li BRANCH_RETIRED
+.It Li branch-mispredicts Ta Li BRANCH_MISPRED
+.It Li dc-misses Ta Li DC_MISS
+.It Li ic-misses Ta Li IC_MISS
+.It Li instructions Ta Li INSTR_RETIRED
+.El
+.Sh SEE ALSO
+.Xr pmc 3 ,
+.Xr pmc_cpuinfo 3 ,
+.Xr pmclog 3 ,
+.Xr pmc.soft 3 ,
+.Xr hwpmc 4
+.Sh HISTORY
+The
+.Nm pmc
+library first appeared in
+.Fx 6.0 .
+Intel XScale support first appeared in
+.Fx 9.0 .
+.Sh AUTHORS
+The
+.Lb libpmc
+library was written by
+.An "Joseph Koshy"
+.Aq jkoshy at FreeBSD.org .
+.Pp
+Intel XScale support was added by
+.An "Rui Paulo"
+.Aq rpaulo at FreeBSD.org .
+.Sh CAVEATS
+The Intel XScale code does not yet support sampling.
Property changes on: trunk/lib/libpmc/pmc.xscale.3
___________________________________________________________________
Added: svn:eol-style
## -0,0 +1 ##
+native
\ No newline at end of property
Added: svn:keywords
## -0,0 +1 ##
+MidnightBSD=%H
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+text/plain
\ No newline at end of property
Modified: trunk/lib/libpmc/pmc_allocate.3
===================================================================
--- trunk/lib/libpmc/pmc_allocate.3 2018-06-09 19:22:04 UTC (rev 10652)
+++ trunk/lib/libpmc/pmc_allocate.3 2018-06-09 19:23:10 UTC (rev 10653)
@@ -1,3 +1,4 @@
+.\" $MidnightBSD$
.\" Copyright (c) 2007-2008 Joseph Koshy. All rights reserved.
.\"
.\" Redistribution and use in source and binary forms, with or without
@@ -21,7 +22,7 @@
.\" OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
.\" SUCH DAMAGE.
.\"
-.\" $FreeBSD: release/9.2.0/lib/libpmc/pmc_allocate.3 232151 2012-02-25 10:10:43Z brueffer $
+.\" $FreeBSD: stable/10/lib/libpmc/pmc_allocate.3 231871 2012-02-17 11:09:51Z brueffer $
.\"
.Dd September 22, 2008
.Dt PMC_ALLOCATE 3
Property changes on: trunk/lib/libpmc/pmc_allocate.3
___________________________________________________________________
Added: svn:keywords
## -0,0 +1 ##
+MidnightBSD=%H
\ No newline at end of property
Modified: trunk/lib/libpmc/pmc_attach.3
===================================================================
--- trunk/lib/libpmc/pmc_attach.3 2018-06-09 19:22:04 UTC (rev 10652)
+++ trunk/lib/libpmc/pmc_attach.3 2018-06-09 19:23:10 UTC (rev 10653)
@@ -1,3 +1,4 @@
+.\" $MidnightBSD$
.\" Copyright (c) 2007 Joseph Koshy. All rights reserved.
.\"
.\" Redistribution and use in source and binary forms, with or without
@@ -21,7 +22,7 @@
.\" OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
.\" SUCH DAMAGE.
.\"
-.\" $FreeBSD: release/9.2.0/lib/libpmc/pmc_attach.3 232151 2012-02-25 10:10:43Z brueffer $
+.\" $FreeBSD: stable/10/lib/libpmc/pmc_attach.3 231871 2012-02-17 11:09:51Z brueffer $
.\"
.Dd November 25, 2007
.Dt PMC_ATTACH 3
Property changes on: trunk/lib/libpmc/pmc_attach.3
___________________________________________________________________
Added: svn:keywords
## -0,0 +1 ##
+MidnightBSD=%H
\ No newline at end of property
Modified: trunk/lib/libpmc/pmc_capabilities.3
===================================================================
--- trunk/lib/libpmc/pmc_capabilities.3 2018-06-09 19:22:04 UTC (rev 10652)
+++ trunk/lib/libpmc/pmc_capabilities.3 2018-06-09 19:23:10 UTC (rev 10653)
@@ -1,3 +1,4 @@
+.\" $MidnightBSD$
.\" Copyright (c) 2007-2008 Joseph Koshy. All rights reserved.
.\"
.\" Redistribution and use in source and binary forms, with or without
@@ -21,7 +22,7 @@
.\" OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
.\" SUCH DAMAGE.
.\"
-.\" $FreeBSD: release/9.2.0/lib/libpmc/pmc_capabilities.3 232151 2012-02-25 10:10:43Z brueffer $
+.\" $FreeBSD: stable/10/lib/libpmc/pmc_capabilities.3 233648 2012-03-29 05:02:12Z eadler $
.\"
.Dd September 22, 2008
.Dt PMC_CAPABILITIES 3
@@ -51,7 +52,7 @@
.Ft int
.Fn pmc_width "pmc_id_t pmc" "uint32_t *width"
.Sh DESCRIPTION
-These functions retrieve information about performance monitoring
+These functions retrieve information about performance monitoring
hardware.
.Pp
Function
Property changes on: trunk/lib/libpmc/pmc_capabilities.3
___________________________________________________________________
Added: svn:keywords
## -0,0 +1 ##
+MidnightBSD=%H
\ No newline at end of property
Modified: trunk/lib/libpmc/pmc_configure_logfile.3
===================================================================
--- trunk/lib/libpmc/pmc_configure_logfile.3 2018-06-09 19:22:04 UTC (rev 10652)
+++ trunk/lib/libpmc/pmc_configure_logfile.3 2018-06-09 19:23:10 UTC (rev 10653)
@@ -1,3 +1,4 @@
+.\" $MidnightBSD$
.\" Copyright (c) 2007 Joseph Koshy. All rights reserved.
.\"
.\" Redistribution and use in source and binary forms, with or without
@@ -21,7 +22,7 @@
.\" OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
.\" SUCH DAMAGE.
.\"
-.\" $FreeBSD: release/9.2.0/lib/libpmc/pmc_configure_logfile.3 232151 2012-02-25 10:10:43Z brueffer $
+.\" $FreeBSD: stable/10/lib/libpmc/pmc_configure_logfile.3 231871 2012-02-17 11:09:51Z brueffer $
.\"
.Dd November 24, 2007
.Dt PMC_CONFIGURE_LOGFILE 3
Property changes on: trunk/lib/libpmc/pmc_configure_logfile.3
___________________________________________________________________
Added: svn:keywords
## -0,0 +1 ##
+MidnightBSD=%H
\ No newline at end of property
Modified: trunk/lib/libpmc/pmc_disable.3
===================================================================
--- trunk/lib/libpmc/pmc_disable.3 2018-06-09 19:22:04 UTC (rev 10652)
+++ trunk/lib/libpmc/pmc_disable.3 2018-06-09 19:23:10 UTC (rev 10653)
@@ -1,3 +1,4 @@
+.\" $MidnightBSD$
.\" Copyright (c) 2007-2008 Joseph Koshy. All rights reserved.
.\"
.\" Redistribution and use in source and binary forms, with or without
@@ -21,7 +22,7 @@
.\" OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
.\" SUCH DAMAGE.
.\"
-.\" $FreeBSD: release/9.2.0/lib/libpmc/pmc_disable.3 232151 2012-02-25 10:10:43Z brueffer $
+.\" $FreeBSD: stable/10/lib/libpmc/pmc_disable.3 231871 2012-02-17 11:09:51Z brueffer $
.\"
.Dd September 22, 2008
.Dt PMC_ENABLE 3
Property changes on: trunk/lib/libpmc/pmc_disable.3
___________________________________________________________________
Added: svn:keywords
## -0,0 +1 ##
+MidnightBSD=%H
\ No newline at end of property
Modified: trunk/lib/libpmc/pmc_event_names_of_class.3
===================================================================
--- trunk/lib/libpmc/pmc_event_names_of_class.3 2018-06-09 19:22:04 UTC (rev 10652)
+++ trunk/lib/libpmc/pmc_event_names_of_class.3 2018-06-09 19:23:10 UTC (rev 10653)
@@ -1,3 +1,4 @@
+.\" $MidnightBSD$
.\" Copyright (c) 2007 Joseph Koshy. All rights reserved.
.\"
.\" Redistribution and use in source and binary forms, with or without
@@ -21,7 +22,7 @@
.\" OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
.\" SUCH DAMAGE.
.\"
-.\" $FreeBSD: release/9.2.0/lib/libpmc/pmc_event_names_of_class.3 232151 2012-02-25 10:10:43Z brueffer $
+.\" $FreeBSD: stable/10/lib/libpmc/pmc_event_names_of_class.3 231871 2012-02-17 11:09:51Z brueffer $
.\"
.Dd November 23, 2007
.Dt PMC_EVENT_NAMES_OF_CLASS 3
Property changes on: trunk/lib/libpmc/pmc_event_names_of_class.3
___________________________________________________________________
Added: svn:keywords
## -0,0 +1 ##
+MidnightBSD=%H
\ No newline at end of property
Modified: trunk/lib/libpmc/pmc_get_driver_stats.3
===================================================================
--- trunk/lib/libpmc/pmc_get_driver_stats.3 2018-06-09 19:22:04 UTC (rev 10652)
+++ trunk/lib/libpmc/pmc_get_driver_stats.3 2018-06-09 19:23:10 UTC (rev 10653)
@@ -1,3 +1,4 @@
+.\" $MidnightBSD$
.\" Copyright (c) 2007 Joseph Koshy. All rights reserved.
.\"
.\" Redistribution and use in source and binary forms, with or without
@@ -21,7 +22,7 @@
.\" OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
.\" SUCH DAMAGE.
.\"
-.\" $FreeBSD: release/9.2.0/lib/libpmc/pmc_get_driver_stats.3 232151 2012-02-25 10:10:43Z brueffer $
+.\" $FreeBSD: stable/10/lib/libpmc/pmc_get_driver_stats.3 231871 2012-02-17 11:09:51Z brueffer $
.\"
.Dd November 25, 2007
.Dt PMC_GET_DRIVER_STATS 3
Property changes on: trunk/lib/libpmc/pmc_get_driver_stats.3
___________________________________________________________________
Added: svn:keywords
## -0,0 +1 ##
+MidnightBSD=%H
\ No newline at end of property
Modified: trunk/lib/libpmc/pmc_get_msr.3
===================================================================
--- trunk/lib/libpmc/pmc_get_msr.3 2018-06-09 19:22:04 UTC (rev 10652)
+++ trunk/lib/libpmc/pmc_get_msr.3 2018-06-09 19:23:10 UTC (rev 10653)
@@ -1,3 +1,4 @@
+.\" $MidnightBSD$
.\" Copyright (c) 2007 Joseph Koshy. All rights reserved.
.\"
.\" Redistribution and use in source and binary forms, with or without
@@ -21,7 +22,7 @@
.\" OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
.\" SUCH DAMAGE.
.\"
-.\" $FreeBSD: release/9.2.0/lib/libpmc/pmc_get_msr.3 232151 2012-02-25 10:10:43Z brueffer $
+.\" $FreeBSD: stable/10/lib/libpmc/pmc_get_msr.3 231871 2012-02-17 11:09:51Z brueffer $
.\"
.Dd November 25, 2007
.Dt PMC_GET_MSR 3
Property changes on: trunk/lib/libpmc/pmc_get_msr.3
___________________________________________________________________
Added: svn:keywords
## -0,0 +1 ##
+MidnightBSD=%H
\ No newline at end of property
Modified: trunk/lib/libpmc/pmc_init.3
===================================================================
--- trunk/lib/libpmc/pmc_init.3 2018-06-09 19:22:04 UTC (rev 10652)
+++ trunk/lib/libpmc/pmc_init.3 2018-06-09 19:23:10 UTC (rev 10653)
@@ -1,3 +1,4 @@
+.\" $MidnightBSD$
.\" Copyright (c) 2007 Joseph Koshy. All rights reserved.
.\"
.\" Redistribution and use in source and binary forms, with or without
@@ -21,7 +22,7 @@
.\" OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
.\" SUCH DAMAGE.
.\"
-.\" $FreeBSD: release/9.2.0/lib/libpmc/pmc_init.3 232151 2012-02-25 10:10:43Z brueffer $
+.\" $FreeBSD: stable/10/lib/libpmc/pmc_init.3 231871 2012-02-17 11:09:51Z brueffer $
.\"
.Dd November 24, 2007
.Dt PMC_INIT 3
Property changes on: trunk/lib/libpmc/pmc_init.3
___________________________________________________________________
Added: svn:keywords
## -0,0 +1 ##
+MidnightBSD=%H
\ No newline at end of property
Modified: trunk/lib/libpmc/pmc_name_of_capability.3
===================================================================
--- trunk/lib/libpmc/pmc_name_of_capability.3 2018-06-09 19:22:04 UTC (rev 10652)
+++ trunk/lib/libpmc/pmc_name_of_capability.3 2018-06-09 19:23:10 UTC (rev 10653)
@@ -1,3 +1,4 @@
+.\" $MidnightBSD$
.\" Copyright (c) 2007 Joseph Koshy. All rights reserved.
.\"
.\" Redistribution and use in source and binary forms, with or without
@@ -21,7 +22,7 @@
.\" OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
.\" SUCH DAMAGE.
.\"
-.\" $FreeBSD: release/9.2.0/lib/libpmc/pmc_name_of_capability.3 232151 2012-02-25 10:10:43Z brueffer $
+.\" $FreeBSD: stable/10/lib/libpmc/pmc_name_of_capability.3 231871 2012-02-17 11:09:51Z brueffer $
.\"
.Dd November 24, 2007
.Dt PMC_NAME_OF_CAPABILITY 3
Property changes on: trunk/lib/libpmc/pmc_name_of_capability.3
___________________________________________________________________
Added: svn:keywords
## -0,0 +1 ##
+MidnightBSD=%H
\ No newline at end of property
Modified: trunk/lib/libpmc/pmc_read.3
===================================================================
--- trunk/lib/libpmc/pmc_read.3 2018-06-09 19:22:04 UTC (rev 10652)
+++ trunk/lib/libpmc/pmc_read.3 2018-06-09 19:23:10 UTC (rev 10653)
@@ -1,3 +1,4 @@
+.\" $MidnightBSD$
.\" Copyright (c) 2007 Joseph Koshy. All rights reserved.
.\"
.\" Redistribution and use in source and binary forms, with or without
@@ -21,7 +22,7 @@
.\" OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
.\" SUCH DAMAGE.
.\"
-.\" $FreeBSD: release/9.2.0/lib/libpmc/pmc_read.3 232151 2012-02-25 10:10:43Z brueffer $
+.\" $FreeBSD: stable/10/lib/libpmc/pmc_read.3 321220 2017-07-19 18:19:11Z ngie $
.\"
.Dd November 25, 2007
.Dt PMC_READ 3
@@ -29,7 +30,7 @@
.Sh NAME
.Nm pmc_read ,
.Nm pmc_rw ,
-.Nm pmc_write ,
+.Nm pmc_write
.Nd read and write hardware performance counters
.Sh LIBRARY
.Lb libpmc
Property changes on: trunk/lib/libpmc/pmc_read.3
___________________________________________________________________
Added: svn:keywords
## -0,0 +1 ##
+MidnightBSD=%H
\ No newline at end of property
Modified: trunk/lib/libpmc/pmc_set.3
===================================================================
--- trunk/lib/libpmc/pmc_set.3 2018-06-09 19:22:04 UTC (rev 10652)
+++ trunk/lib/libpmc/pmc_set.3 2018-06-09 19:23:10 UTC (rev 10653)
@@ -1,3 +1,4 @@
+.\" $MidnightBSD$
.\" Copyright (c) 2007 Joseph Koshy. All rights reserved.
.\"
.\" Redistribution and use in source and binary forms, with or without
@@ -21,7 +22,7 @@
.\" OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
.\" SUCH DAMAGE.
.\"
-.\" $FreeBSD: release/9.2.0/lib/libpmc/pmc_set.3 232151 2012-02-25 10:10:43Z brueffer $
+.\" $FreeBSD: stable/10/lib/libpmc/pmc_set.3 231871 2012-02-17 11:09:51Z brueffer $
.\"
.Dd November 25, 2007
.Dt PMC_SET 3
Property changes on: trunk/lib/libpmc/pmc_set.3
___________________________________________________________________
Added: svn:keywords
## -0,0 +1 ##
+MidnightBSD=%H
\ No newline at end of property
Modified: trunk/lib/libpmc/pmc_start.3
===================================================================
--- trunk/lib/libpmc/pmc_start.3 2018-06-09 19:22:04 UTC (rev 10652)
+++ trunk/lib/libpmc/pmc_start.3 2018-06-09 19:23:10 UTC (rev 10653)
@@ -1,3 +1,4 @@
+.\" $MidnightBSD$
.\" Copyright (c) 2007-2008 Joseph Koshy. All rights reserved.
.\"
.\" Redistribution and use in source and binary forms, with or without
@@ -21,7 +22,7 @@
.\" OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
.\" SUCH DAMAGE.
.\"
-.\" $FreeBSD: release/9.2.0/lib/libpmc/pmc_start.3 232151 2012-02-25 10:10:43Z brueffer $
+.\" $FreeBSD: stable/10/lib/libpmc/pmc_start.3 231871 2012-02-17 11:09:51Z brueffer $
.\"
.Dd September 22, 2008
.Dt PMC_START 3
Property changes on: trunk/lib/libpmc/pmc_start.3
___________________________________________________________________
Added: svn:keywords
## -0,0 +1 ##
+MidnightBSD=%H
\ No newline at end of property
Modified: trunk/lib/libpmc/pmclog.3
===================================================================
--- trunk/lib/libpmc/pmclog.3 2018-06-09 19:22:04 UTC (rev 10652)
+++ trunk/lib/libpmc/pmclog.3 2018-06-09 19:23:10 UTC (rev 10653)
@@ -1,3 +1,4 @@
+.\" $MidnightBSD$
.\" Copyright (c) 2005-2006 Joseph Koshy. All rights reserved.
.\"
.\" Redistribution and use in source and binary forms, with or without
@@ -21,7 +22,7 @@
.\" OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
.\" SUCH DAMAGE.
.\"
-.\" $FreeBSD: release/9.2.0/lib/libpmc/pmclog.3 232151 2012-02-25 10:10:43Z brueffer $
+.\" $FreeBSD: stable/10/lib/libpmc/pmclog.3 231871 2012-02-17 11:09:51Z brueffer $
.\"
.Dd March 26, 2006
.Dt PMCLOG 3
Property changes on: trunk/lib/libpmc/pmclog.3
___________________________________________________________________
Added: svn:keywords
## -0,0 +1 ##
+MidnightBSD=%H
\ No newline at end of property
Modified: trunk/lib/libpmc/pmclog.c
===================================================================
--- trunk/lib/libpmc/pmclog.c 2018-06-09 19:22:04 UTC (rev 10652)
+++ trunk/lib/libpmc/pmclog.c 2018-06-09 19:23:10 UTC (rev 10653)
@@ -30,7 +30,7 @@
*/
#include <sys/cdefs.h>
-__FBSDID("$FreeBSD: release/9.2.0/lib/libpmc/pmclog.c 236238 2012-05-29 14:50:21Z fabient $");
+__FBSDID("$FreeBSD: stable/10/lib/libpmc/pmclog.c 233628 2012-03-28 20:58:30Z fabient $");
#include <sys/param.h>
#include <sys/pmc.h>
Modified: trunk/lib/libpmc/pmclog.h
===================================================================
--- trunk/lib/libpmc/pmclog.h 2018-06-09 19:22:04 UTC (rev 10652)
+++ trunk/lib/libpmc/pmclog.h 2018-06-09 19:23:10 UTC (rev 10653)
@@ -28,7 +28,7 @@
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*
- * $FreeBSD: release/9.2.0/lib/libpmc/pmclog.h 236238 2012-05-29 14:50:21Z fabient $
+ * $FreeBSD: stable/10/lib/libpmc/pmclog.h 233628 2012-03-28 20:58:30Z fabient $
*/
#ifndef _PMCLOG_H_
Modified: trunk/lib/libproc/Makefile
===================================================================
--- trunk/lib/libproc/Makefile 2018-06-09 19:22:04 UTC (rev 10652)
+++ trunk/lib/libproc/Makefile 2018-06-09 19:23:10 UTC (rev 10653)
@@ -1,5 +1,8 @@
# $MidnightBSD$
+# $FreeBSD: stable/10/lib/libproc/Makefile 276486 2014-12-31 23:25:37Z ngie $
+.include <bsd.own.mk>
+
LIB= proc
SRCS= proc_bkpt.c \
@@ -13,8 +16,18 @@
CFLAGS+= -I${.CURDIR}
+.if ${MK_LIBCPLUSPLUS} != "no"
+LDADD+= -lcxxrt
+DPADD+= ${LIBCXXRT}
+.elif ${MK_GNUCXX} != "no"
+LDADD+= -lsupc++
+DPADD+= ${LIBSTDCPLUSPLUS}
+.else
+CFLAGS+= -DNO_CXA_DEMANGLE
+.endif
+
SHLIB_MAJOR= 2
-WITHOUT_MAN=
+MAN=
.include <bsd.lib.mk>
Modified: trunk/lib/libproc/_libproc.h
===================================================================
--- trunk/lib/libproc/_libproc.h 2018-06-09 19:22:04 UTC (rev 10652)
+++ trunk/lib/libproc/_libproc.h 2018-06-09 19:23:10 UTC (rev 10653)
@@ -1,3 +1,4 @@
+/* $MidnightBSD$ */
/*-
* Copyright (c) 2008 John Birrell (jb at freebsd.org)
* All rights reserved.
@@ -23,7 +24,7 @@
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*
- * $MidnightBSD$
+ * $FreeBSD: stable/10/lib/libproc/_libproc.h 270731 2014-08-27 19:51:42Z markj $
*/
#include <sys/cdefs.h>
@@ -46,10 +47,14 @@
size_t rdobjsz;
size_t nobjs;
struct lwpstatus lwps;
+ rd_loadobj_t *rdexec; /* rdobj index of program executable. */
+ char execname[MAXPATHLEN]; /* Path to program executable. */
};
#ifdef DEBUG
-#define DPRINTF(fmt, ...) warn(fmt, __VA_ARGS__)
+#define DPRINTF(...) warn(__VA_ARGS__)
+#define DPRINTFX(...) warnx(__VA_ARGS__)
#else
-#define DPRINTF(fmt, ...)
+#define DPRINTF(...) do { } while (0)
+#define DPRINTFX(...) do { } while (0)
#endif
Modified: trunk/lib/libproc/libproc.h
===================================================================
--- trunk/lib/libproc/libproc.h 2018-06-09 19:22:04 UTC (rev 10652)
+++ trunk/lib/libproc/libproc.h 2018-06-09 19:23:10 UTC (rev 10653)
@@ -1,3 +1,4 @@
+/* $MidnightBSD$ */
/*-
* Copyright (c) 2010 The FreeBSD Foundation
* Copyright (c) 2008 John Birrell (jb at freebsd.org)
@@ -27,7 +28,7 @@
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*
- * $MidnightBSD$
+ * $FreeBSD: stable/10/lib/libproc/libproc.h 269754 2014-08-09 15:00:03Z markj $
*/
#ifndef _LIBPROC_H_
@@ -102,6 +103,7 @@
#define PR_FAULTED 2
#define PR_SYSENTRY 3
#define PR_SYSEXIT 4
+#define PR_SIGNALLED 5
int pr_what;
#define FLTBPT -1
} lwpstatus_t;
Modified: trunk/lib/libproc/proc_bkpt.c
===================================================================
--- trunk/lib/libproc/proc_bkpt.c 2018-06-09 19:22:04 UTC (rev 10652)
+++ trunk/lib/libproc/proc_bkpt.c 2018-06-09 19:23:10 UTC (rev 10653)
@@ -1,3 +1,4 @@
+/* $MidnightBSD$ */
/*
* Copyright (c) 2010 The FreeBSD Foundation
* All rights reserved.
@@ -28,7 +29,7 @@
*/
#include <sys/cdefs.h>
-__MBSDID("$MidnightBSD$");
+__FBSDID("$FreeBSD: stable/10/lib/libproc/proc_bkpt.c 269754 2014-08-09 15:00:03Z markj $");
#include <sys/types.h>
#include <sys/ptrace.h>
@@ -37,17 +38,43 @@
#include <assert.h>
#include <err.h>
+#include <errno.h>
+#include <signal.h>
#include <stdio.h>
-#include <errno.h>
#include "_libproc.h"
#if defined(__i386__) || defined(__amd64__)
#define BREAKPOINT_INSTR 0xcc /* int 0x3 */
#define BREAKPOINT_INSTR_SZ 1
+#elif defined(__mips__)
+#define BREAKPOINT_INSTR 0xd /* break */
+#define BREAKPOINT_INSTR_SZ 4
+#elif defined(__powerpc__)
+#define BREAKPOINT_INSTR 0x7fe00008 /* trap */
+#define BREAKPOINT_INSTR_SZ 4
#else
#error "Add support for your architecture"
#endif
+static int
+proc_stop(struct proc_handle *phdl)
+{
+ int status;
+
+ if (kill(proc_getpid(phdl), SIGSTOP) == -1) {
+ DPRINTF("kill %d", proc_getpid(phdl));
+ return (-1);
+ } else if (waitpid(proc_getpid(phdl), &status, WSTOPPED) == -1) {
+ DPRINTF("waitpid %d", proc_getpid(phdl));
+ return (-1);
+ } else if (!WIFSTOPPED(status)) {
+ DPRINTFX("waitpid: unexpected status 0x%x", status);
+ return (-1);
+ }
+
+ return (0);
+}
+
int
proc_bkptset(struct proc_handle *phdl, uintptr_t address,
unsigned long *saved)
@@ -54,6 +81,7 @@
{
struct ptrace_io_desc piod;
unsigned long paddr, caddr;
+ int ret = 0, stopped;
*saved = 0;
if (phdl->status == PS_DEAD || phdl->status == PS_UNDEAD ||
@@ -62,6 +90,15 @@
return (-1);
}
+ DPRINTFX("adding breakpoint at 0x%lx", address);
+
+ stopped = 0;
+ if (phdl->status != PS_STOP) {
+ if (proc_stop(phdl) != 0)
+ return (-1);
+ stopped = 1;
+ }
+
/*
* Read the original instruction.
*/
@@ -72,9 +109,10 @@
piod.piod_addr = &paddr;
piod.piod_len = BREAKPOINT_INSTR_SZ;
if (ptrace(PT_IO, proc_getpid(phdl), (caddr_t)&piod, 0) < 0) {
- DPRINTF("ERROR: couldn't read instruction at address 0x%" PRIuPTR,
- address);
- return (-1);
+ DPRINTF("ERROR: couldn't read instruction at address 0x%"
+ PRIuPTR, address);
+ ret = -1;
+ goto done;
}
*saved = paddr;
/*
@@ -87,12 +125,18 @@
piod.piod_addr = &paddr;
piod.piod_len = BREAKPOINT_INSTR_SZ;
if (ptrace(PT_IO, proc_getpid(phdl), (caddr_t)&piod, 0) < 0) {
- warn("ERROR: couldn't write instruction at address 0x%" PRIuPTR,
- address);
- return (-1);
+ DPRINTF("ERROR: couldn't write instruction at address 0x%"
+ PRIuPTR, address);
+ ret = -1;
+ goto done;
}
- return (0);
+done:
+ if (stopped)
+ /* Restart the process if we had to stop it. */
+ proc_continue(phdl);
+
+ return (ret);
}
int
@@ -101,6 +145,7 @@
{
struct ptrace_io_desc piod;
unsigned long paddr, caddr;
+ int ret = 0, stopped;
if (phdl->status == PS_DEAD || phdl->status == PS_UNDEAD ||
phdl->status == PS_IDLE) {
@@ -107,7 +152,16 @@
errno = ENOENT;
return (-1);
}
- DPRINTF("removing breakpoint at 0x%lx\n", address);
+
+ DPRINTFX("removing breakpoint at 0x%lx", address);
+
+ stopped = 0;
+ if (phdl->status != PS_STOP) {
+ if (proc_stop(phdl) != 0)
+ return (-1);
+ stopped = 1;
+ }
+
/*
* Overwrite the breakpoint instruction that we setup previously.
*/
@@ -118,12 +172,16 @@
piod.piod_addr = &paddr;
piod.piod_len = BREAKPOINT_INSTR_SZ;
if (ptrace(PT_IO, proc_getpid(phdl), (caddr_t)&piod, 0) < 0) {
- DPRINTF("ERROR: couldn't write instruction at address 0x%" PRIuPTR,
- address);
- return (-1);
+ DPRINTF("ERROR: couldn't write instruction at address 0x%"
+ PRIuPTR, address);
+ ret = -1;
}
+
+ if (stopped)
+ /* Restart the process if we had to stop it. */
+ proc_continue(phdl);
- return (0);
+ return (ret);
}
/*
@@ -147,12 +205,12 @@
int status;
if (proc_regget(phdl, REG_PC, &pc) < 0) {
- warn("ERROR: couldn't get PC register");
+ DPRINTFX("ERROR: couldn't get PC register");
return (-1);
}
proc_bkptregadj(&pc);
if (proc_bkptdel(phdl, pc, saved) < 0) {
- warn("ERROR: couldn't delete breakpoint");
+ DPRINTFX("ERROR: couldn't delete breakpoint");
return (-1);
}
/*
@@ -161,13 +219,13 @@
*/
proc_regset(phdl, REG_PC, pc);
if (ptrace(PT_STEP, proc_getpid(phdl), (caddr_t)1, 0) < 0) {
- warn("ERROR: ptrace step failed");
+ DPRINTFX("ERROR: ptrace step failed");
return (-1);
}
proc_wstatus(phdl);
status = proc_getwstat(phdl);
if (!WIFSTOPPED(status)) {
- warn("ERROR: don't know why process stopped");
+ DPRINTFX("ERROR: don't know why process stopped");
return (-1);
}
/*
@@ -175,7 +233,7 @@
* the same as the one that we were passed in.
*/
if (proc_bkptset(phdl, pc, &samesaved) < 0) {
- warn("ERROR: couldn't restore breakpoint");
+ DPRINTFX("ERROR: couldn't restore breakpoint");
return (-1);
}
assert(samesaved == saved);
Modified: trunk/lib/libproc/proc_create.c
===================================================================
--- trunk/lib/libproc/proc_create.c 2018-06-09 19:22:04 UTC (rev 10652)
+++ trunk/lib/libproc/proc_create.c 2018-06-09 19:23:10 UTC (rev 10653)
@@ -1,3 +1,4 @@
+/* $MidnightBSD$ */
/*-
* Copyright (c) 2008 John Birrell (jb at freebsd.org)
* All rights reserved.
@@ -23,11 +24,13 @@
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*
- * $MidnightBSD$
+ * $FreeBSD: stable/10/lib/libproc/proc_create.c 270731 2014-08-27 19:51:42Z markj $
*/
-#include "_libproc.h"
-#include <stdio.h>
+#include <sys/types.h>
+#include <sys/sysctl.h>
+#include <sys/wait.h>
+
#include <err.h>
#include <errno.h>
#include <fcntl.h>
@@ -35,8 +38,38 @@
#include <stdlib.h>
#include <string.h>
#include <unistd.h>
-#include <sys/wait.h>
+#include "_libproc.h"
+
+static int proc_init(pid_t, int, int, struct proc_handle *);
+
+static int
+proc_init(pid_t pid, int flags, int status, struct proc_handle *phdl)
+{
+ int mib[4], error;
+ size_t len;
+
+ memset(phdl, 0, sizeof(*phdl));
+ phdl->pid = pid;
+ phdl->flags = flags;
+ phdl->status = status;
+
+ mib[0] = CTL_KERN;
+ mib[1] = KERN_PROC;
+ mib[2] = KERN_PROC_PATHNAME;
+ mib[3] = pid;
+ len = sizeof(phdl->execname);
+ if (sysctl(mib, 4, phdl->execname, &len, NULL, 0) != 0) {
+ error = errno;
+ DPRINTF("ERROR: cannot get pathname for child process %d", pid);
+ return (error);
+ }
+ if (len == 0)
+ phdl->execname[0] = '\0';
+
+ return (0);
+}
+
int
proc_attach(pid_t pid, int flags, struct proc_handle **pphdl)
{
@@ -54,12 +87,12 @@
if ((phdl = malloc(sizeof(struct proc_handle))) == NULL)
return (ENOMEM);
- memset(phdl, 0, sizeof(struct proc_handle));
- phdl->pid = pid;
- phdl->flags = flags;
- phdl->status = PS_RUN;
elf_version(EV_CURRENT);
+ error = proc_init(pid, flags, PS_RUN, phdl);
+ if (error != 0)
+ goto out;
+
if (ptrace(PT_ATTACH, phdl->pid, 0, 0) != 0) {
error = errno;
DPRINTF("ERROR: cannot ptrace child process %d", pid);
@@ -75,7 +108,7 @@
/* Check for an unexpected status. */
if (WIFSTOPPED(status) == 0)
- DPRINTF("ERROR: child process %d status 0x%x", pid, status);
+ DPRINTFX("ERROR: child process %d status 0x%x", pid, status);
else
phdl->status = PS_STOP;
@@ -123,14 +156,14 @@
_exit(2);
} else {
/* The parent owns the process handle. */
- memset(phdl, 0, sizeof(struct proc_handle));
- phdl->pid = pid;
- phdl->status = PS_IDLE;
+ error = proc_init(pid, 0, PS_IDLE, phdl);
+ if (error != 0)
+ goto bad;
/* Wait for the child process to stop. */
if (waitpid(pid, &status, WUNTRACED) == -1) {
error = errno;
- DPRINTF("ERROR: child process %d didn't stop as expected", pid);
+ DPRINTF("ERROR: child process %d didn't stop as expected", pid);
goto bad;
}
@@ -137,7 +170,7 @@
/* Check for an unexpected status. */
if (WIFSTOPPED(status) == 0) {
error = errno;
- DPRINTF("ERROR: child process %d status 0x%x", pid, status);
+ DPRINTFX("ERROR: child process %d status 0x%x", pid, status);
goto bad;
} else
phdl->status = PS_STOP;
Modified: trunk/lib/libproc/proc_regs.c
===================================================================
--- trunk/lib/libproc/proc_regs.c 2018-06-09 19:22:04 UTC (rev 10652)
+++ trunk/lib/libproc/proc_regs.c 2018-06-09 19:23:10 UTC (rev 10653)
@@ -1,3 +1,4 @@
+/* $MidnightBSD$ */
/*
* Copyright (c) 2010 The FreeBSD Foundation
* All rights reserved.
@@ -28,7 +29,7 @@
*/
#include <sys/cdefs.h>
-__MBSDID("$MidnightBSD$");
+__FBSDID("$FreeBSD: stable/10/lib/libproc/proc_regs.c 259895 2013-12-25 22:36:27Z markj $");
#include <sys/types.h>
#include <sys/ptrace.h>
@@ -58,6 +59,10 @@
*regvalue = regs.r_rip;
#elif defined(__i386__)
*regvalue = regs.r_eip;
+#elif defined(__mips__)
+ *regvalue = regs.r_regs[PC];
+#elif defined(__powerpc__)
+ *regvalue = regs.pc;
#endif
break;
case REG_SP:
@@ -65,10 +70,14 @@
*regvalue = regs.r_rsp;
#elif defined(__i386__)
*regvalue = regs.r_esp;
+#elif defined(__mips__)
+ *regvalue = regs.r_regs[SP];
+#elif defined(__powerpc__)
+ *regvalue = regs.fixreg[1];
#endif
break;
default:
- warn("ERROR: no support for reg number %d", reg);
+ DPRINTFX("ERROR: no support for reg number %d", reg);
return (-1);
}
@@ -93,6 +102,10 @@
regs.r_rip = regvalue;
#elif defined(__i386__)
regs.r_eip = regvalue;
+#elif defined(__mips__)
+ regs.r_regs[PC] = regvalue;
+#elif defined(__powerpc__)
+ regs.pc = regvalue;
#endif
break;
case REG_SP:
@@ -100,10 +113,14 @@
regs.r_rsp = regvalue;
#elif defined(__i386__)
regs.r_esp = regvalue;
+#elif defined(__mips__)
+ regs.r_regs[PC] = regvalue;
+#elif defined(__powerpc__)
+ regs.fixreg[1] = regvalue;
#endif
break;
default:
- warn("ERROR: no support for reg number %d", reg);
+ DPRINTFX("ERROR: no support for reg number %d", reg);
return (-1);
}
if (ptrace(PT_SETREGS, proc_getpid(phdl), (caddr_t)®s, 0) < 0)
Modified: trunk/lib/libproc/proc_rtld.c
===================================================================
--- trunk/lib/libproc/proc_rtld.c 2018-06-09 19:22:04 UTC (rev 10652)
+++ trunk/lib/libproc/proc_rtld.c 2018-06-09 19:23:10 UTC (rev 10653)
@@ -1,3 +1,4 @@
+/* $MidnightBSD$ */
/*
* Copyright (c) 2010 The FreeBSD Foundation
* All rights reserved.
@@ -28,7 +29,7 @@
*/
#include <sys/cdefs.h>
-__MBSDID("$MidnightBSD$");
+__FBSDID("$FreeBSD: stable/10/lib/libproc/proc_rtld.c 270731 2014-08-27 19:51:42Z markj $");
#include <stdio.h>
#include <string.h>
@@ -49,6 +50,9 @@
if (phdl->rdobjs == NULL)
return (-1);
}
+ if (strcmp(lop->rdl_path, phdl->execname) == 0 &&
+ (lop->rdl_prot & RD_RDL_X) != 0)
+ phdl->rdexec = &phdl->rdobjs[phdl->nobjs];
memcpy(&phdl->rdobjs[phdl->nobjs++], lop, sizeof(*lop));
return (0);
Modified: trunk/lib/libproc/proc_sym.c
===================================================================
--- trunk/lib/libproc/proc_sym.c 2018-06-09 19:22:04 UTC (rev 10652)
+++ trunk/lib/libproc/proc_sym.c 2018-06-09 19:23:10 UTC (rev 10653)
@@ -1,3 +1,4 @@
+/* $MidnightBSD$ */
/*-
* Copyright (c) 2010 The FreeBSD Foundation
* Copyright (c) 2008 John Birrell (jb at freebsd.org)
@@ -27,7 +28,7 @@
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*
- * $MidnightBSD$
+ * $FreeBSD: stable/10/lib/libproc/proc_sym.c 279082 2015-02-20 20:02:47Z rpaulo $
*/
#include <sys/types.h>
@@ -46,9 +47,47 @@
#include "_libproc.h"
+#ifndef NO_CXA_DEMANGLE
+extern char *__cxa_demangle(const char *, char *, size_t *, int *);
+#endif /* NO_CXA_DEMANGLE */
+
static void proc_rdl2prmap(rd_loadobj_t *, prmap_t *);
static void
+demangle(const char *symbol, char *buf, size_t len)
+{
+#ifndef NO_CXA_DEMANGLE
+ char *dembuf;
+
+ if (symbol[0] == '_' && symbol[1] == 'Z' && symbol[2]) {
+ dembuf = __cxa_demangle(symbol, NULL, NULL, NULL);
+ if (!dembuf)
+ goto fail;
+ strlcpy(buf, dembuf, len);
+ free(dembuf);
+ return;
+ }
+fail:
+#endif /* NO_CXA_DEMANGLE */
+ strlcpy(buf, symbol, len);
+}
+
+static int
+find_dbg_obj(const char *path)
+{
+ int fd;
+ char dbg_path[PATH_MAX];
+
+ snprintf(dbg_path, sizeof(dbg_path),
+ "/usr/lib/debug/%s.debug", path);
+ fd = open(dbg_path, O_RDONLY);
+ if (fd > 0)
+ return (fd);
+ else
+ return (open(path, O_RDONLY));
+}
+
+static void
proc_rdl2prmap(rd_loadobj_t *rdl, prmap_t *map)
{
map->pr_vaddr = rdl->rdl_saddr;
@@ -74,7 +113,7 @@
for (i = 0; i < p->nobjs; i++) {
rdl = &p->rdobjs[i];
- if (addr >= rdl->rdl_saddr && addr <= rdl->rdl_eaddr) {
+ if (addr >= rdl->rdl_saddr && addr < rdl->rdl_eaddr) {
strlcpy(objname, rdl->rdl_path, objnamesz);
return (objname);
}
@@ -90,17 +129,25 @@
rd_loadobj_t *rdl;
char path[MAXPATHLEN];
+ rdl = NULL;
for (i = 0; i < p->nobjs; i++) {
- rdl = &p->rdobjs[i];
- basename_r(rdl->rdl_path, path);
+ basename_r(p->rdobjs[i].rdl_path, path);
if (strcmp(path, objname) == 0) {
- if ((map = malloc(sizeof(*map))) == NULL)
- return (NULL);
- proc_rdl2prmap(rdl, map);
- return (map);
+ rdl = &p->rdobjs[i];
+ break;
}
}
- return (NULL);
+ if (rdl == NULL) {
+ if (strcmp(objname, "a.out") == 0 && p->rdexec != NULL)
+ rdl = p->rdexec;
+ else
+ return (NULL);
+ }
+
+ if ((map = malloc(sizeof(*map))) == NULL)
+ return (NULL);
+ proc_rdl2prmap(rdl, map);
+ return (map);
}
int
@@ -154,7 +201,7 @@
kve = kves + i;
if (kve->kve_type == KVME_TYPE_VNODE)
lastvn = i;
- if (addr >= kve->kve_start && addr <= kve->kve_end) {
+ if (addr >= kve->kve_start && addr < kve->kve_end) {
if ((map = malloc(sizeof(*map))) == NULL) {
free(kves);
return (NULL);
@@ -187,7 +234,7 @@
for (i = 0; i < p->nobjs; i++) {
rdl = &p->rdobjs[i];
- if (addr >= rdl->rdl_saddr && addr <= rdl->rdl_eaddr) {
+ if (addr >= rdl->rdl_saddr && addr < rdl->rdl_eaddr) {
if ((map = malloc(sizeof(*map))) == NULL)
return (NULL);
proc_rdl2prmap(rdl, map);
@@ -216,16 +263,16 @@
if ((map = proc_addr2map(p, addr)) == NULL)
return (-1);
- if (!map->pr_mapname || (fd = open(map->pr_mapname, O_RDONLY, 0)) < 0) {
- warn("ERROR: open %s failed", map->pr_mapname);
+ if ((fd = find_dbg_obj(map->pr_mapname)) < 0) {
+ DPRINTF("ERROR: open %s failed", map->pr_mapname);
goto err0;
}
if ((e = elf_begin(fd, ELF_C_READ, NULL)) == NULL) {
- warn("ERROR: elf_begin() failed");
+ DPRINTFX("ERROR: elf_begin() failed: %s", elf_errmsg(-1));
goto err1;
}
if (gelf_getehdr(e, &ehdr) == NULL) {
- warn("ERROR: gelf_getehdr() failed");
+ DPRINTFX("ERROR: gelf_getehdr() failed: %s", elf_errmsg(-1));
goto err2;
}
/*
@@ -253,8 +300,8 @@
* Then look up the string name in STRTAB (.dynstr)
*/
if ((data = elf_getdata(dynsymscn, NULL)) == NULL) {
- DPRINTF("ERROR: elf_getdata() failed");
- goto err2;
+ DPRINTFX("ERROR: elf_getdata() failed: %s", elf_errmsg(-1));
+ goto symtab;
}
i = 0;
while (gelf_getsym(data, i++, &sym) != NULL) {
@@ -262,11 +309,14 @@
* Calculate the address mapped to the virtual memory
* by rtld.
*/
- rsym = map->pr_vaddr + sym.st_value;
- if (addr >= rsym && addr <= (rsym + sym.st_size)) {
+ if (ehdr.e_type != ET_EXEC)
+ rsym = map->pr_vaddr + sym.st_value;
+ else
+ rsym = sym.st_value;
+ if (addr >= rsym && addr < rsym + sym.st_size) {
s = elf_strptr(e, dynsymstridx, sym.st_name);
if (s) {
- strlcpy(name, s, namesz);
+ demangle(s, name, namesz);
memcpy(symcopy, &sym, sizeof(sym));
/*
* DTrace expects the st_value to contain
@@ -279,14 +329,13 @@
}
}
}
+symtab:
/*
* Iterate over the Symbols Table to find the symbol.
* Then look up the string name in STRTAB (.dynstr)
*/
- if (symtabscn == NULL)
- goto err2;
if ((data = elf_getdata(symtabscn, NULL)) == NULL) {
- DPRINTF("ERROR: elf_getdata() failed");
+ DPRINTFX("ERROR: elf_getdata() failed: %s", elf_errmsg(-1));
goto err2;
}
i = 0;
@@ -299,10 +348,10 @@
rsym = map->pr_vaddr + sym.st_value;
else
rsym = sym.st_value;
- if (addr >= rsym && addr <= (rsym + sym.st_size)) {
+ if (addr >= rsym && addr < rsym + sym.st_size) {
s = elf_strptr(e, symtabstridx, sym.st_name);
if (s) {
- strlcpy(name, s, namesz);
+ demangle(s, name, namesz);
memcpy(symcopy, &sym, sizeof(sym));
/*
* DTrace expects the st_value to contain
@@ -356,8 +405,9 @@
free(kves);
return (NULL);
}
- if (name == NULL || strcmp(name, "a.out") == 0) {
- map = proc_addr2map(p, p->rdobjs[0].rdl_saddr);
+ if ((name == NULL || strcmp(name, "a.out") == 0) &&
+ p->rdexec != NULL) {
+ map = proc_addr2map(p, p->rdexec->rdl_saddr);
return (map);
}
for (i = 0; i < p->nobjs; i++) {
@@ -391,19 +441,19 @@
unsigned long symtabstridx = 0, dynsymstridx = 0;
if ((map = proc_name2map(p, object)) == NULL) {
- DPRINTF("ERROR: couldn't find object %s", object);
+ DPRINTFX("ERROR: couldn't find object %s", object);
goto err0;
}
- if ((fd = open(map->pr_mapname, O_RDONLY, 0)) < 0) {
+ if ((fd = find_dbg_obj(map->pr_mapname)) < 0) {
DPRINTF("ERROR: open %s failed", map->pr_mapname);
goto err0;
}
if ((e = elf_begin(fd, ELF_C_READ, NULL)) == NULL) {
- warn("ERROR: elf_begin() failed");
+ DPRINTFX("ERROR: elf_begin() failed: %s", elf_errmsg(-1));
goto err1;
}
if (gelf_getehdr(e, &ehdr) == NULL) {
- warn("ERROR: gelf_getehdr() failed");
+ DPRINTFX("ERROR: gelf_getehdr() failed: %s", elf_errmsg(-1));
goto err2;
}
/*
@@ -430,18 +480,17 @@
* Iterate over the Dynamic Symbols table to find the symbol.
* Then look up the string name in STRTAB (.dynstr)
*/
- if ((data = elf_getdata(dynsymscn, NULL)) == NULL) {
- DPRINTF("ERROR: elf_getdata() failed");
- goto err2;
- }
- i = 0;
- while (gelf_getsym(data, i++, &sym) != NULL) {
- s = elf_strptr(e, dynsymstridx, sym.st_name);
- if (s && strcmp(s, symbol) == 0) {
- memcpy(symcopy, &sym, sizeof(sym));
- symcopy->st_value = map->pr_vaddr + sym.st_value;
- error = 0;
- goto out;
+ if ((data = elf_getdata(dynsymscn, NULL))) {
+ i = 0;
+ while (gelf_getsym(data, i++, &sym) != NULL) {
+ s = elf_strptr(e, dynsymstridx, sym.st_name);
+ if (s && strcmp(s, symbol) == 0) {
+ memcpy(symcopy, &sym, sizeof(sym));
+ if (ehdr.e_type != ET_EXEC)
+ symcopy->st_value += map->pr_vaddr;
+ error = 0;
+ goto out;
+ }
}
}
/*
@@ -448,22 +497,21 @@
* Iterate over the Symbols Table to find the symbol.
* Then look up the string name in STRTAB (.dynstr)
*/
- if (symtabscn == NULL)
- goto err2;
- if ((data = elf_getdata(symtabscn, NULL)) == NULL) {
- DPRINTF("ERROR: elf_getdata() failed");
- goto err2;
- }
- i = 0;
- while (gelf_getsym(data, i++, &sym) != NULL) {
- s = elf_strptr(e, symtabstridx, sym.st_name);
- if (s && strcmp(s, symbol) == 0) {
- memcpy(symcopy, &sym, sizeof(sym));
- error = 0;
- goto out;
+ if ((data = elf_getdata(symtabscn, NULL))) {
+ i = 0;
+ while (gelf_getsym(data, i++, &sym) != NULL) {
+ s = elf_strptr(e, symtabstridx, sym.st_name);
+ if (s && strcmp(s, symbol) == 0) {
+ memcpy(symcopy, &sym, sizeof(sym));
+ if (ehdr.e_type != ET_EXEC)
+ symcopy->st_value += map->pr_vaddr;
+ error = 0;
+ goto out;
+ }
}
}
out:
+ DPRINTFX("found addr 0x%lx for %s", symcopy->st_value, symbol);
err2:
elf_end(e);
err1:
@@ -484,6 +532,7 @@
prmap_t *map;
Elf_Scn *scn, *foundscn = NULL;
Elf_Data *data;
+ GElf_Ehdr ehdr;
GElf_Shdr shdr;
GElf_Sym sym;
unsigned long stridx = -1;
@@ -492,14 +541,18 @@
if ((map = proc_name2map(p, object)) == NULL)
return (-1);
- if ((fd = open(map->pr_mapname, O_RDONLY)) < 0) {
- warn("ERROR: open %s failed", map->pr_mapname);
+ if ((fd = find_dbg_obj(map->pr_mapname)) < 0) {
+ DPRINTF("ERROR: open %s failed", map->pr_mapname);
goto err0;
}
if ((e = elf_begin(fd, ELF_C_READ, NULL)) == NULL) {
- warn("ERROR: elf_begin() failed");
+ DPRINTFX("ERROR: elf_begin() failed: %s", elf_errmsg(-1));
goto err1;
}
+ if (gelf_getehdr(e, &ehdr) == NULL) {
+ DPRINTFX("ERROR: gelf_getehdr() failed: %s", elf_errmsg(-1));
+ goto err2;
+ }
/*
* Find the section we are looking for.
*/
@@ -520,7 +573,7 @@
return (-1);
stridx = shdr.sh_link;
if ((data = elf_getdata(foundscn, NULL)) == NULL) {
- DPRINTF("ERROR: elf_getdata() failed");
+ DPRINTFX("ERROR: elf_getdata() failed: %s", elf_errmsg(-1));
goto err2;
}
i = 0;
@@ -550,7 +603,8 @@
(mask & TYPE_FILE) == 0)
continue;
s = elf_strptr(e, stridx, sym.st_name);
- sym.st_value += map->pr_vaddr;
+ if (ehdr.e_type != ET_EXEC)
+ sym.st_value += map->pr_vaddr;
(*func)(cd, &sym, s);
}
error = 0;
Modified: trunk/lib/libproc/proc_util.c
===================================================================
--- trunk/lib/libproc/proc_util.c 2018-06-09 19:22:04 UTC (rev 10652)
+++ trunk/lib/libproc/proc_util.c 2018-06-09 19:23:10 UTC (rev 10653)
@@ -1,3 +1,4 @@
+/* $MidnightBSD$ */
/*-
* Copyright (c) 2010 The FreeBSD Foundation
* Copyright (c) 2008 John Birrell (jb at freebsd.org)
@@ -27,7 +28,7 @@
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*
- * $MidnightBSD$
+ * $FreeBSD: stable/10/lib/libproc/proc_util.c 269754 2014-08-09 15:00:03Z markj $
*/
#include <sys/types.h>
@@ -35,10 +36,9 @@
#include <sys/wait.h>
#include <err.h>
#include <errno.h>
-#include <unistd.h>
-#include <stdio.h>
#include <signal.h>
#include <string.h>
+#include <unistd.h>
#include "_libproc.h"
int
@@ -59,11 +59,14 @@
int
proc_continue(struct proc_handle *phdl)
{
+ int pending = 0;
if (phdl == NULL)
return (-1);
- if (ptrace(PT_CONTINUE, phdl->pid, (caddr_t)(uintptr_t) 1, 0) != 0)
+ if (phdl->status == PS_STOP && WSTOPSIG(phdl->wstat) != SIGTRAP)
+ pending = WSTOPSIG(phdl->wstat);
+ if (ptrace(PT_CONTINUE, phdl->pid, (caddr_t)(uintptr_t)1, pending) != 0)
return (-1);
phdl->status = PS_RUN;
@@ -146,7 +149,7 @@
return (-1);
if (waitpid(phdl->pid, &status, WUNTRACED) < 0) {
if (errno != EINTR)
- warn("waitpid");
+ DPRINTF("waitpid");
return (-1);
}
if (WIFSTOPPED(status))
@@ -208,12 +211,16 @@
return (NULL);
siginfo = &lwpinfo.pl_siginfo;
if (lwpinfo.pl_event == PL_EVENT_SIGNAL &&
- (lwpinfo.pl_flags & PL_FLAG_SI) &&
- siginfo->si_signo == SIGTRAP &&
- (siginfo->si_code == TRAP_BRKPT ||
- siginfo->si_code == TRAP_TRACE)) {
- psp->pr_why = PR_FAULTED;
- psp->pr_what = FLTBPT;
+ (lwpinfo.pl_flags & PL_FLAG_SI) != 0) {
+ if (siginfo->si_signo == SIGTRAP &&
+ (siginfo->si_code == TRAP_BRKPT ||
+ siginfo->si_code == TRAP_TRACE)) {
+ psp->pr_why = PR_FAULTED;
+ psp->pr_what = FLTBPT;
+ } else {
+ psp->pr_why = PR_SIGNALLED;
+ psp->pr_what = siginfo->si_signo;
+ }
} else if (lwpinfo.pl_flags & PL_FLAG_SCE) {
psp->pr_why = PR_SYSENTRY;
} else if (lwpinfo.pl_flags & PL_FLAG_SCX) {
Modified: trunk/lib/libproc/test/Makefile
===================================================================
--- trunk/lib/libproc/test/Makefile 2018-06-09 19:22:04 UTC (rev 10652)
+++ trunk/lib/libproc/test/Makefile 2018-06-09 19:23:10 UTC (rev 10653)
@@ -1,4 +1,5 @@
# $MidnightBSD$
+# $FreeBSD: stable/10/lib/libproc/test/Makefile 210688 2010-07-31 16:10:20Z rpaulo $
SUBDIR= t1-bkpt t2-name2map t3-name2sym
Modified: trunk/lib/libproc/test/t1-bkpt/Makefile
===================================================================
--- trunk/lib/libproc/test/t1-bkpt/Makefile 2018-06-09 19:22:04 UTC (rev 10652)
+++ trunk/lib/libproc/test/t1-bkpt/Makefile 2018-06-09 19:23:10 UTC (rev 10653)
@@ -1,4 +1,5 @@
# $MidnightBSD$
+# $FreeBSD: stable/10/lib/libproc/test/t1-bkpt/Makefile 276486 2014-12-31 23:25:37Z ngie $
PROG= t1-bkpt
@@ -7,6 +8,6 @@
LDADD= -lproc -lelf -lrtld_db -lutil
DPADD= ${LIBPROC} ${LIBELF}
-WITHOUT_MAN=
+MAN=
.include <bsd.prog.mk>
Modified: trunk/lib/libproc/test/t1-bkpt/t1-bkpt.c
===================================================================
--- trunk/lib/libproc/test/t1-bkpt/t1-bkpt.c 2018-06-09 19:22:04 UTC (rev 10652)
+++ trunk/lib/libproc/test/t1-bkpt/t1-bkpt.c 2018-06-09 19:23:10 UTC (rev 10653)
@@ -1,3 +1,4 @@
+/* $MidnightBSD$ */
/*
* Copyright (c) 2010 The FreeBSD Foundation
* All rights reserved.
@@ -26,7 +27,7 @@
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*
- * $MidnightBSD$
+ * $FreeBSD: stable/10/lib/libproc/test/t1-bkpt/t1-bkpt.c 244692 2012-12-26 05:11:48Z pluknet $
*/
#include <sys/types.h>
#include <sys/wait.h>
@@ -36,7 +37,7 @@
#include <string.h>
#include <libproc.h>
-int
+int __noinline
t1_bkpt_t()
{
printf("TEST OK\n");
@@ -50,12 +51,12 @@
unsigned long saved;
proc_create("./t1-bkpt", targv, NULL, NULL, &phdl);
- proc_bkptset(phdl, (uintptr_t)t1_bkpt_t, &saved);
+ assert(proc_bkptset(phdl, (uintptr_t)t1_bkpt_t, &saved) == 0);
proc_continue(phdl);
- assert(WIFSTOPPED(proc_wstatus(phdl)));
+ assert(proc_wstatus(phdl) == PS_STOP);
proc_bkptexec(phdl, saved);
proc_continue(phdl);
- proc_wait(phdl);
+ proc_wstatus(phdl);
proc_free(phdl);
}
Modified: trunk/lib/libproc/test/t2-name2map/Makefile
===================================================================
--- trunk/lib/libproc/test/t2-name2map/Makefile 2018-06-09 19:22:04 UTC (rev 10652)
+++ trunk/lib/libproc/test/t2-name2map/Makefile 2018-06-09 19:23:10 UTC (rev 10653)
@@ -1,4 +1,5 @@
# $MidnightBSD$
+# $FreeBSD: stable/10/lib/libproc/test/t2-name2map/Makefile 276486 2014-12-31 23:25:37Z ngie $
PROG= t2-name2map
@@ -7,6 +8,6 @@
LDADD= -lproc -lelf -lrtld_db -lutil
DPADD= ${LIBPROC} ${LIBELF}
-WITHOUT_MAN=
+MAN=
.include <bsd.prog.mk>
Modified: trunk/lib/libproc/test/t2-name2map/t2-name2map.c
===================================================================
--- trunk/lib/libproc/test/t2-name2map/t2-name2map.c 2018-06-09 19:22:04 UTC (rev 10652)
+++ trunk/lib/libproc/test/t2-name2map/t2-name2map.c 2018-06-09 19:23:10 UTC (rev 10653)
@@ -1,3 +1,4 @@
+/* $MidnightBSD$ */
/*
* Copyright (c) 2010 The FreeBSD Foundation
* All rights reserved.
@@ -26,7 +27,7 @@
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*
- * $MidnightBSD$
+ * $FreeBSD: stable/10/lib/libproc/test/t2-name2map/t2-name2map.c 210688 2010-07-31 16:10:20Z rpaulo $
*/
#include <sys/types.h>
Modified: trunk/lib/libproc/test/t3-name2sym/Makefile
===================================================================
--- trunk/lib/libproc/test/t3-name2sym/Makefile 2018-06-09 19:22:04 UTC (rev 10652)
+++ trunk/lib/libproc/test/t3-name2sym/Makefile 2018-06-09 19:23:10 UTC (rev 10653)
@@ -1,4 +1,5 @@
# $MidnightBSD$
+# $FreeBSD: stable/10/lib/libproc/test/t3-name2sym/Makefile 276486 2014-12-31 23:25:37Z ngie $
PROG= t3-name2sym
@@ -7,6 +8,6 @@
LDADD= -lproc -lelf -lrtld_db -lutil
DPADD= ${LIBPROC} ${LIBELF}
-WITHOUT_MAN=
+MAN=
.include <bsd.prog.mk>
Modified: trunk/lib/libproc/test/t3-name2sym/t3-name2sym.c
===================================================================
--- trunk/lib/libproc/test/t3-name2sym/t3-name2sym.c 2018-06-09 19:22:04 UTC (rev 10652)
+++ trunk/lib/libproc/test/t3-name2sym/t3-name2sym.c 2018-06-09 19:23:10 UTC (rev 10653)
@@ -1,3 +1,4 @@
+/* $MidnightBSD$ */
/*
* Copyright (c) 2010 The FreeBSD Foundation
* All rights reserved.
@@ -26,7 +27,7 @@
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*
- * $MidnightBSD$
+ * $FreeBSD: stable/10/lib/libproc/test/t3-name2sym/t3-name2sym.c 240154 2012-09-06 01:24:18Z rpaulo $
*/
#include <sys/types.h>
#include <assert.h>
@@ -33,6 +34,7 @@
#include <stdio.h>
#include <libproc.h>
#include <gelf.h>
+#include <string.h>
int
main(int argc, char *argv[])
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