[Midnightbsd-cvs] src [12311] trunk/sys/x86/include: sync with FreeBSD 11-stable
laffer1 at midnightbsd.org
laffer1 at midnightbsd.org
Sat Feb 8 14:33:28 EST 2020
Revision: 12311
http://svnweb.midnightbsd.org/src/?rev=12311
Author: laffer1
Date: 2020-02-08 14:33:27 -0500 (Sat, 08 Feb 2020)
Log Message:
-----------
sync with FreeBSD 11-stable
Modified Paths:
--------------
trunk/sys/x86/include/_align.h
trunk/sys/x86/include/_inttypes.h
trunk/sys/x86/include/_limits.h
trunk/sys/x86/include/_stdint.h
trunk/sys/x86/include/_types.h
trunk/sys/x86/include/acpica_machdep.h
trunk/sys/x86/include/apicreg.h
trunk/sys/x86/include/apm_bios.h
trunk/sys/x86/include/bus.h
trunk/sys/x86/include/busdma_impl.h
trunk/sys/x86/include/elf.h
trunk/sys/x86/include/endian.h
trunk/sys/x86/include/fdt.h
trunk/sys/x86/include/float.h
trunk/sys/x86/include/fpu.h
trunk/sys/x86/include/frame.h
trunk/sys/x86/include/legacyvar.h
trunk/sys/x86/include/mca.h
trunk/sys/x86/include/metadata.h
trunk/sys/x86/include/mptable.h
trunk/sys/x86/include/ofw_machdep.h
trunk/sys/x86/include/pci_cfgreg.h
trunk/sys/x86/include/psl.h
trunk/sys/x86/include/ptrace.h
trunk/sys/x86/include/reg.h
trunk/sys/x86/include/segments.h
trunk/sys/x86/include/setjmp.h
trunk/sys/x86/include/sigframe.h
trunk/sys/x86/include/signal.h
trunk/sys/x86/include/specialreg.h
trunk/sys/x86/include/stdarg.h
trunk/sys/x86/include/sysarch.h
trunk/sys/x86/include/trap.h
trunk/sys/x86/include/ucontext.h
trunk/sys/x86/include/vdso.h
trunk/sys/x86/include/vmware.h
Added Paths:
-----------
trunk/sys/x86/include/apicvar.h
trunk/sys/x86/include/cputypes.h
trunk/sys/x86/include/dump.h
trunk/sys/x86/include/ifunc.h
trunk/sys/x86/include/init.h
trunk/sys/x86/include/intr_machdep.h
trunk/sys/x86/include/pvclock.h
trunk/sys/x86/include/stack.h
trunk/sys/x86/include/ucode.h
trunk/sys/x86/include/x86_smp.h
trunk/sys/x86/include/x86_var.h
trunk/sys/x86/include/xen/
trunk/sys/x86/include/xen/xen-os.h
Modified: trunk/sys/x86/include/_align.h
===================================================================
--- trunk/sys/x86/include/_align.h 2020-02-08 19:32:41 UTC (rev 12310)
+++ trunk/sys/x86/include/_align.h 2020-02-08 19:33:27 UTC (rev 12311)
@@ -36,7 +36,7 @@
* SUCH DAMAGE.
*
* from: @(#)param.h 5.8 (Berkeley) 6/28/91
- * $FreeBSD: stable/10/sys/x86/include/_align.h 215856 2010-11-26 10:59:20Z tijl $
+ * $FreeBSD: stable/11/sys/x86/include/_align.h 331722 2018-03-29 02:50:57Z eadler $
*/
#ifndef _X86_INCLUDE__ALIGN_H_
@@ -47,7 +47,7 @@
* for all data types (int, long, ...). The result is unsigned int
* and must be cast to any desired pointer type.
*/
-#define _ALIGNBYTES (sizeof(register_t) - 1)
-#define _ALIGN(p) (((uintptr_t)(p) + _ALIGNBYTES) & ~_ALIGNBYTES)
+#define _ALIGNBYTES (sizeof(__register_t) - 1)
+#define _ALIGN(p) (((__uintptr_t)(p) + _ALIGNBYTES) & ~_ALIGNBYTES)
#endif /* !_X86_INCLUDE__ALIGN_H_ */
Modified: trunk/sys/x86/include/_inttypes.h
===================================================================
--- trunk/sys/x86/include/_inttypes.h 2020-02-08 19:32:41 UTC (rev 12310)
+++ trunk/sys/x86/include/_inttypes.h 2020-02-08 19:33:27 UTC (rev 12311)
@@ -28,7 +28,7 @@
* POSSIBILITY OF SUCH DAMAGE.
*
* From: $NetBSD: int_fmtio.h,v 1.2 2001/04/26 16:25:21 kleink Exp $
- * $FreeBSD: stable/10/sys/x86/include/_inttypes.h 217157 2011-01-08 18:09:48Z tijl $
+ * $FreeBSD: stable/11/sys/x86/include/_inttypes.h 217157 2011-01-08 18:09:48Z tijl $
*/
#ifndef _MACHINE_INTTYPES_H_
Modified: trunk/sys/x86/include/_limits.h
===================================================================
--- trunk/sys/x86/include/_limits.h 2020-02-08 19:32:41 UTC (rev 12310)
+++ trunk/sys/x86/include/_limits.h 2020-02-08 19:33:27 UTC (rev 12311)
@@ -28,7 +28,7 @@
* SUCH DAMAGE.
*
* @(#)limits.h 8.3 (Berkeley) 1/4/94
- * $FreeBSD: stable/10/sys/x86/include/_limits.h 235939 2012-05-24 21:44:46Z obrien $
+ * $FreeBSD: stable/11/sys/x86/include/_limits.h 331722 2018-03-29 02:50:57Z eadler $
*/
#ifndef _MACHINE__LIMITS_H_
Modified: trunk/sys/x86/include/_stdint.h
===================================================================
--- trunk/sys/x86/include/_stdint.h 2020-02-08 19:32:41 UTC (rev 12310)
+++ trunk/sys/x86/include/_stdint.h 2020-02-08 19:33:27 UTC (rev 12311)
@@ -35,12 +35,14 @@
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
- * $FreeBSD: stable/10/sys/x86/include/_stdint.h 237517 2012-06-24 04:15:58Z andrew $
+ * $FreeBSD: stable/11/sys/x86/include/_stdint.h 301030 2016-05-31 08:38:24Z ed $
*/
#ifndef _MACHINE__STDINT_H_
#define _MACHINE__STDINT_H_
+#include <machine/_limits.h>
+
#if !defined(__cplusplus) || defined(__STDC_CONSTANT_MACROS)
#define INT8_C(c) (c)
@@ -168,8 +170,8 @@
#define PTRDIFF_MAX INT64_MAX
/* Limits of sig_atomic_t. */
-#define SIG_ATOMIC_MIN LONG_MIN
-#define SIG_ATOMIC_MAX LONG_MAX
+#define SIG_ATOMIC_MIN __LONG_MIN
+#define SIG_ATOMIC_MAX __LONG_MAX
/* Limit of size_t. */
#define SIZE_MAX UINT64_MAX
Modified: trunk/sys/x86/include/_types.h
===================================================================
--- trunk/sys/x86/include/_types.h 2020-02-08 19:32:41 UTC (rev 12310)
+++ trunk/sys/x86/include/_types.h 2020-02-08 19:33:27 UTC (rev 12311)
@@ -34,7 +34,7 @@
*
* From: @(#)ansi.h 8.2 (Berkeley) 1/4/94
* From: @(#)types.h 8.3 (Berkeley) 1/5/94
- * $FreeBSD: stable/10/sys/x86/include/_types.h 287139 2015-08-25 19:18:38Z jkim $
+ * $FreeBSD: stable/11/sys/x86/include/_types.h 332135 2018-04-06 19:17:59Z kevans $
*/
#ifndef _MACHINE__TYPES_H_
@@ -44,6 +44,8 @@
#error this file needs sys/cdefs.h as a prerequisite
#endif
+#include <machine/_limits.h>
+
#define __NO_STRICT_ALIGNMENT
/*
@@ -77,15 +79,19 @@
#ifdef __LP64__
typedef __int32_t __clock_t; /* clock()... */
typedef __int64_t __critical_t;
+#ifndef _STANDALONE
typedef double __double_t;
typedef float __float_t;
+#endif
typedef __int64_t __intfptr_t;
typedef __int64_t __intptr_t;
#else
typedef unsigned long __clock_t;
typedef __int32_t __critical_t;
+#ifndef _STANDALONE
typedef long double __double_t;
typedef long double __float_t;
+#endif
typedef __int32_t __intfptr_t;
typedef __int32_t __intptr_t;
#endif
@@ -141,8 +147,6 @@
#endif
typedef __uint32_t __vm_size_t;
#endif
-typedef __int64_t __vm_ooffset_t;
-typedef __uint64_t __vm_pindex_t;
typedef int ___wchar_t;
#define __WCHAR_MIN __INT_MIN /* min value for a wchar_t */
Modified: trunk/sys/x86/include/acpica_machdep.h
===================================================================
--- trunk/sys/x86/include/acpica_machdep.h 2020-02-08 19:32:41 UTC (rev 12310)
+++ trunk/sys/x86/include/acpica_machdep.h 2020-02-08 19:33:27 UTC (rev 12311)
@@ -24,7 +24,7 @@
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*
- * $FreeBSD: stable/10/sys/x86/include/acpica_machdep.h 259073 2013-12-07 18:23:29Z peter $
+ * $FreeBSD: stable/11/sys/x86/include/acpica_machdep.h 298094 2016-04-16 03:44:50Z gjb $
*/
/******************************************************************************
@@ -70,12 +70,20 @@
(Acq) = acpi_release_global_lock(&((GLptr)->GlobalLock)); \
} while (0)
+enum intr_trigger;
+enum intr_polarity;
+
void acpi_SetDefaultIntrModel(int model);
void acpi_cpu_c1(void);
+void acpi_cpu_idle_mwait(uint32_t mwait_hint);
void *acpi_map_table(vm_paddr_t pa, const char *sig);
void acpi_unmap_table(void *table);
vm_paddr_t acpi_find_table(const char *sig);
+void madt_parse_interrupt_values(void *entry,
+ enum intr_trigger *trig, enum intr_polarity *pol);
+extern int madt_found_sci_override;
+
#endif /* _KERNEL */
#endif /* __ACPICA_MACHDEP_H__ */
Modified: trunk/sys/x86/include/apicreg.h
===================================================================
--- trunk/sys/x86/include/apicreg.h 2020-02-08 19:32:41 UTC (rev 12310)
+++ trunk/sys/x86/include/apicreg.h 2020-02-08 19:33:27 UTC (rev 12311)
@@ -23,7 +23,7 @@
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*
- * $FreeBSD: stable/10/sys/x86/include/apicreg.h 262141 2014-02-18 01:15:32Z jhb $
+ * $FreeBSD: stable/11/sys/x86/include/apicreg.h 323608 2017-09-15 09:00:45Z kib $
*/
#ifndef _X86_APICREG_H_
@@ -194,6 +194,81 @@
typedef struct LAPIC lapic_t;
+enum LAPIC_REGISTERS {
+ LAPIC_ID = 0x2,
+ LAPIC_VERSION = 0x3,
+ LAPIC_TPR = 0x8,
+ LAPIC_APR = 0x9,
+ LAPIC_PPR = 0xa,
+ LAPIC_EOI = 0xb,
+ LAPIC_LDR = 0xd,
+ LAPIC_DFR = 0xe, /* Not in x2APIC */
+ LAPIC_SVR = 0xf,
+ LAPIC_ISR0 = 0x10,
+ LAPIC_ISR1 = 0x11,
+ LAPIC_ISR2 = 0x12,
+ LAPIC_ISR3 = 0x13,
+ LAPIC_ISR4 = 0x14,
+ LAPIC_ISR5 = 0x15,
+ LAPIC_ISR6 = 0x16,
+ LAPIC_ISR7 = 0x17,
+ LAPIC_TMR0 = 0x18,
+ LAPIC_TMR1 = 0x19,
+ LAPIC_TMR2 = 0x1a,
+ LAPIC_TMR3 = 0x1b,
+ LAPIC_TMR4 = 0x1c,
+ LAPIC_TMR5 = 0x1d,
+ LAPIC_TMR6 = 0x1e,
+ LAPIC_TMR7 = 0x1f,
+ LAPIC_IRR0 = 0x20,
+ LAPIC_IRR1 = 0x21,
+ LAPIC_IRR2 = 0x22,
+ LAPIC_IRR3 = 0x23,
+ LAPIC_IRR4 = 0x24,
+ LAPIC_IRR5 = 0x25,
+ LAPIC_IRR6 = 0x26,
+ LAPIC_IRR7 = 0x27,
+ LAPIC_ESR = 0x28,
+ LAPIC_LVT_CMCI = 0x2f,
+ LAPIC_ICR_LO = 0x30,
+ LAPIC_ICR_HI = 0x31, /* Not in x2APIC */
+ LAPIC_LVT_TIMER = 0x32,
+ LAPIC_LVT_THERMAL = 0x33,
+ LAPIC_LVT_PCINT = 0x34,
+ LAPIC_LVT_LINT0 = 0x35,
+ LAPIC_LVT_LINT1 = 0x36,
+ LAPIC_LVT_ERROR = 0x37,
+ LAPIC_ICR_TIMER = 0x38,
+ LAPIC_CCR_TIMER = 0x39,
+ LAPIC_DCR_TIMER = 0x3e,
+ LAPIC_SELF_IPI = 0x3f, /* Only in x2APIC */
+ LAPIC_EXT_FEATURES = 0x40, /* AMD */
+ LAPIC_EXT_CTRL = 0x41, /* AMD */
+ LAPIC_EXT_SEOI = 0x42, /* AMD */
+ LAPIC_EXT_IER0 = 0x48, /* AMD */
+ LAPIC_EXT_IER1 = 0x49, /* AMD */
+ LAPIC_EXT_IER2 = 0x4a, /* AMD */
+ LAPIC_EXT_IER3 = 0x4b, /* AMD */
+ LAPIC_EXT_IER4 = 0x4c, /* AMD */
+ LAPIC_EXT_IER5 = 0x4d, /* AMD */
+ LAPIC_EXT_IER6 = 0x4e, /* AMD */
+ LAPIC_EXT_IER7 = 0x4f, /* AMD */
+ LAPIC_EXT_LVT0 = 0x50, /* AMD */
+ LAPIC_EXT_LVT1 = 0x51, /* AMD */
+ LAPIC_EXT_LVT2 = 0x52, /* AMD */
+ LAPIC_EXT_LVT3 = 0x53, /* AMD */
+};
+
+#define LAPIC_MEM_MUL 0x10
+
+/*
+ * Although some registers are available on AMD processors only,
+ * it's not a big waste to reserve them on all platforms.
+ * However, we need to watch out for this space being assigned for
+ * non-APIC purposes in the future processor models.
+ */
+#define LAPIC_MEM_REGION ((LAPIC_EXT_LVT3 + 1) * LAPIC_MEM_MUL)
+
/******************************************************************************
* I/O APIC structure
*/
@@ -236,6 +311,7 @@
#define APIC_VER_MAXLVT 0x00ff0000
#define MAXLVTSHIFT 16
#define APIC_VER_EOI_SUPPRESSION 0x01000000
+#define APIC_VER_AMD_EXT_SPACE 0x80000000
/* fields in LDR */
#define APIC_LDR_RESERVED 0x00ffffff
@@ -340,11 +416,12 @@
#define APIC_LVTT_VECTOR 0x000000ff
#define APIC_LVTT_DS 0x00001000
#define APIC_LVTT_M 0x00010000
-#define APIC_LVTT_TM 0x00020000
+#define APIC_LVTT_TM 0x00060000
# define APIC_LVTT_TM_ONE_SHOT 0x00000000
# define APIC_LVTT_TM_PERIODIC 0x00020000
+# define APIC_LVTT_TM_TSCDLT 0x00040000
+# define APIC_LVTT_TM_RSRV 0x00060000
-
/* APIC timer current count */
#define APIC_TIMER_MAX_COUNT 0xffffffff
@@ -358,6 +435,13 @@
#define APIC_TDCR_128 0x0a
#define APIC_TDCR_1 0x0b
+/* Constants related to AMD Extended APIC Features Register */
+#define APIC_EXTF_ELVT_MASK 0x00ff0000
+#define APIC_EXTF_ELVT_SHIFT 16
+#define APIC_EXTF_EXTID_CAP 0x00000004
+#define APIC_EXTF_SEIO_CAP 0x00000002
+#define APIC_EXTF_IER_CAP 0x00000001
+
/* LVT table indices */
#define APIC_LVT_LINT0 0
#define APIC_LVT_LINT1 1
@@ -368,6 +452,13 @@
#define APIC_LVT_CMCI 6
#define APIC_LVT_MAX APIC_LVT_CMCI
+/* AMD extended LVT constants, seem to be assigned by fiat */
+#define APIC_ELVT_IBS 0 /* Instruction based sampling */
+#define APIC_ELVT_MCA 1 /* MCE thresholding */
+#define APIC_ELVT_DEI 2 /* Deferred error interrupt */
+#define APIC_ELVT_SBI 3 /* Sideband interface */
+#define APIC_ELVT_MAX APIC_ELVT_SBI
+
/******************************************************************************
* I/O APIC defines
*/
@@ -379,6 +470,8 @@
#define IOAPIC_WINDOW 0x10
#define IOAPIC_EOIR 0x40
+#define IOAPIC_WND_SIZE 0x50
+
/* indexes into IO APIC */
#define IOAPIC_ID 0x00
#define IOAPIC_VER 0x01
Added: trunk/sys/x86/include/apicvar.h
===================================================================
--- trunk/sys/x86/include/apicvar.h (rev 0)
+++ trunk/sys/x86/include/apicvar.h 2020-02-08 19:33:27 UTC (rev 12311)
@@ -0,0 +1,487 @@
+/* $MidnightBSD$ */
+/*-
+ * Copyright (c) 2003 John Baldwin <jhb at FreeBSD.org>
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ * $FreeBSD: stable/11/sys/x86/include/apicvar.h 346817 2019-04-28 13:21:01Z dchagin $
+ */
+
+#ifndef _X86_APICVAR_H_
+#define _X86_APICVAR_H_
+
+/*
+ * Local && I/O APIC variable definitions.
+ */
+
+/*
+ * Layout of local APIC interrupt vectors:
+ *
+ * 0xff (255) +-------------+
+ * | | 15 (Spurious / IPIs / Local Interrupts)
+ * 0xf0 (240) +-------------+
+ * | | 14 (I/O Interrupts / Timer)
+ * 0xe0 (224) +-------------+
+ * | | 13 (I/O Interrupts)
+ * 0xd0 (208) +-------------+
+ * | | 12 (I/O Interrupts)
+ * 0xc0 (192) +-------------+
+ * | | 11 (I/O Interrupts)
+ * 0xb0 (176) +-------------+
+ * | | 10 (I/O Interrupts)
+ * 0xa0 (160) +-------------+
+ * | | 9 (I/O Interrupts)
+ * 0x90 (144) +-------------+
+ * | | 8 (I/O Interrupts / System Calls)
+ * 0x80 (128) +-------------+
+ * | | 7 (I/O Interrupts)
+ * 0x70 (112) +-------------+
+ * | | 6 (I/O Interrupts)
+ * 0x60 (96) +-------------+
+ * | | 5 (I/O Interrupts)
+ * 0x50 (80) +-------------+
+ * | | 4 (I/O Interrupts)
+ * 0x40 (64) +-------------+
+ * | | 3 (I/O Interrupts)
+ * 0x30 (48) +-------------+
+ * | | 2 (ATPIC Interrupts)
+ * 0x20 (32) +-------------+
+ * | | 1 (Exceptions, traps, faults, etc.)
+ * 0x10 (16) +-------------+
+ * | | 0 (Exceptions, traps, faults, etc.)
+ * 0x00 (0) +-------------+
+ *
+ * Note: 0x80 needs to be handled specially and not allocated to an
+ * I/O device!
+ */
+
+#define MAX_APIC_ID 0xfe
+#define APIC_ID_ALL 0xff
+
+/* I/O Interrupts are used for external devices such as ISA, PCI, etc. */
+#define APIC_IO_INTS (IDT_IO_INTS + 16)
+#define APIC_NUM_IOINTS 191
+
+/* The timer interrupt is used for clock handling and drives hardclock, etc. */
+#define APIC_TIMER_INT (APIC_IO_INTS + APIC_NUM_IOINTS)
+
+/*
+ ********************* !!! WARNING !!! ******************************
+ * Each local apic has an interrupt receive fifo that is two entries deep
+ * for each interrupt priority class (higher 4 bits of interrupt vector).
+ * Once the fifo is full the APIC can no longer receive interrupts for this
+ * class and sending IPIs from other CPUs will be blocked.
+ * To avoid deadlocks there should be no more than two IPI interrupts
+ * pending at the same time.
+ * Currently this is guaranteed by dividing the IPIs in two groups that have
+ * each at most one IPI interrupt pending. The first group is protected by the
+ * smp_ipi_mtx and waits for the completion of the IPI (Only one IPI user
+ * at a time) The second group uses a single interrupt and a bitmap to avoid
+ * redundant IPI interrupts.
+ */
+
+/* Interrupts for local APIC LVT entries other than the timer. */
+#define APIC_LOCAL_INTS 240
+#define APIC_ERROR_INT APIC_LOCAL_INTS
+#define APIC_THERMAL_INT (APIC_LOCAL_INTS + 1)
+#define APIC_CMC_INT (APIC_LOCAL_INTS + 2)
+#define APIC_IPI_INTS (APIC_LOCAL_INTS + 3)
+
+#define IPI_RENDEZVOUS (APIC_IPI_INTS) /* Inter-CPU rendezvous. */
+#define IPI_INVLTLB (APIC_IPI_INTS + 1) /* TLB Shootdown IPIs */
+#define IPI_INVLPG (APIC_IPI_INTS + 2)
+#define IPI_INVLRNG (APIC_IPI_INTS + 3)
+#define IPI_INVLCACHE (APIC_IPI_INTS + 4)
+/* Vector to handle bitmap based IPIs */
+#define IPI_BITMAP_VECTOR (APIC_IPI_INTS + 5)
+
+/* IPIs handled by IPI_BITMAP_VECTOR */
+#define IPI_AST 0 /* Generate software trap. */
+#define IPI_PREEMPT 1
+#define IPI_HARDCLOCK 2
+#define IPI_BITMAP_LAST IPI_HARDCLOCK
+#define IPI_IS_BITMAPED(x) ((x) <= IPI_BITMAP_LAST)
+
+#define IPI_STOP (APIC_IPI_INTS + 6) /* Stop CPU until restarted. */
+#define IPI_SUSPEND (APIC_IPI_INTS + 7) /* Suspend CPU until restarted. */
+#define IPI_DYN_FIRST (APIC_IPI_INTS + 8)
+#define IPI_DYN_LAST (253) /* IPIs allocated at runtime */
+
+/*
+ * IPI_STOP_HARD does not need to occupy a slot in the IPI vector space since
+ * it is delivered using an NMI anyways.
+ */
+#define IPI_NMI_FIRST 254
+#define IPI_TRACE 254 /* Interrupt for tracing. */
+#define IPI_STOP_HARD 255 /* Stop CPU with a NMI. */
+
+/*
+ * The spurious interrupt can share the priority class with the IPIs since
+ * it is not a normal interrupt. (Does not use the APIC's interrupt fifo)
+ */
+#define APIC_SPURIOUS_INT 255
+
+#ifndef LOCORE
+
+#define APIC_IPI_DEST_SELF -1
+#define APIC_IPI_DEST_ALL -2
+#define APIC_IPI_DEST_OTHERS -3
+
+#define APIC_BUS_UNKNOWN -1
+#define APIC_BUS_ISA 0
+#define APIC_BUS_EISA 1
+#define APIC_BUS_PCI 2
+#define APIC_BUS_MAX APIC_BUS_PCI
+
+#define IRQ_EXTINT -1
+#define IRQ_NMI -2
+#define IRQ_SMI -3
+#define IRQ_DISABLED -4
+
+/*
+ * An APIC enumerator is a pseudo bus driver that enumerates APIC's including
+ * CPU's and I/O APIC's.
+ */
+struct apic_enumerator {
+ const char *apic_name;
+ int (*apic_probe)(void);
+ int (*apic_probe_cpus)(void);
+ int (*apic_setup_local)(void);
+ int (*apic_setup_io)(void);
+ SLIST_ENTRY(apic_enumerator) apic_next;
+};
+
+inthand_t
+ IDTVEC(apic_isr1), IDTVEC(apic_isr2), IDTVEC(apic_isr3),
+ IDTVEC(apic_isr4), IDTVEC(apic_isr5), IDTVEC(apic_isr6),
+ IDTVEC(apic_isr7), IDTVEC(cmcint), IDTVEC(errorint),
+ IDTVEC(spuriousint), IDTVEC(timerint),
+ IDTVEC(apic_isr1_pti), IDTVEC(apic_isr2_pti), IDTVEC(apic_isr3_pti),
+ IDTVEC(apic_isr4_pti), IDTVEC(apic_isr5_pti), IDTVEC(apic_isr6_pti),
+ IDTVEC(apic_isr7_pti), IDTVEC(cmcint_pti), IDTVEC(errorint_pti),
+ IDTVEC(spuriousint_pti), IDTVEC(timerint_pti);
+
+extern vm_paddr_t lapic_paddr;
+extern int apic_cpuids[];
+
+void apic_register_enumerator(struct apic_enumerator *enumerator);
+void *ioapic_create(vm_paddr_t addr, int32_t apic_id, int intbase);
+int ioapic_disable_pin(void *cookie, u_int pin);
+int ioapic_get_vector(void *cookie, u_int pin);
+void ioapic_register(void *cookie);
+int ioapic_remap_vector(void *cookie, u_int pin, int vector);
+int ioapic_set_bus(void *cookie, u_int pin, int bus_type);
+int ioapic_set_extint(void *cookie, u_int pin);
+int ioapic_set_nmi(void *cookie, u_int pin);
+int ioapic_set_polarity(void *cookie, u_int pin, enum intr_polarity pol);
+int ioapic_set_triggermode(void *cookie, u_int pin,
+ enum intr_trigger trigger);
+int ioapic_set_smi(void *cookie, u_int pin);
+
+/*
+ * Struct containing pointers to APIC functions whose
+ * implementation is run time selectable.
+ */
+struct apic_ops {
+ void (*create)(u_int, int);
+ void (*init)(vm_paddr_t);
+ void (*xapic_mode)(void);
+ bool (*is_x2apic)(void);
+ void (*setup)(int);
+ void (*dump)(const char *);
+ void (*disable)(void);
+ void (*eoi)(void);
+ int (*id)(void);
+ int (*intr_pending)(u_int);
+ void (*set_logical_id)(u_int, u_int, u_int);
+ u_int (*cpuid)(u_int);
+
+ /* Vectors */
+ u_int (*alloc_vector)(u_int, u_int);
+ u_int (*alloc_vectors)(u_int, u_int *, u_int, u_int);
+ void (*enable_vector)(u_int, u_int);
+ void (*disable_vector)(u_int, u_int);
+ void (*free_vector)(u_int, u_int, u_int);
+
+
+ /* PMC */
+ int (*enable_pmc)(void);
+ void (*disable_pmc)(void);
+ void (*reenable_pmc)(void);
+
+ /* CMC */
+ void (*enable_cmc)(void);
+
+ /* AMD ELVT */
+ int (*enable_mca_elvt)(void);
+
+ /* IPI */
+ void (*ipi_raw)(register_t, u_int);
+ void (*ipi_vectored)(u_int, int);
+ int (*ipi_wait)(int);
+ int (*ipi_alloc)(inthand_t *ipifunc);
+ void (*ipi_free)(int vector);
+
+ /* LVT */
+ int (*set_lvt_mask)(u_int, u_int, u_char);
+ int (*set_lvt_mode)(u_int, u_int, u_int32_t);
+ int (*set_lvt_polarity)(u_int, u_int, enum intr_polarity);
+ int (*set_lvt_triggermode)(u_int, u_int, enum intr_trigger);
+};
+
+extern struct apic_ops apic_ops;
+
+static inline void
+lapic_create(u_int apic_id, int boot_cpu)
+{
+
+ apic_ops.create(apic_id, boot_cpu);
+}
+
+static inline void
+lapic_init(vm_paddr_t addr)
+{
+
+ apic_ops.init(addr);
+}
+
+static inline void
+lapic_xapic_mode(void)
+{
+
+ apic_ops.xapic_mode();
+}
+
+static inline bool
+lapic_is_x2apic(void)
+{
+
+ return (apic_ops.is_x2apic());
+}
+
+static inline void
+lapic_setup(int boot)
+{
+
+ apic_ops.setup(boot);
+}
+
+static inline void
+lapic_dump(const char *str)
+{
+
+ apic_ops.dump(str);
+}
+
+static inline void
+lapic_disable(void)
+{
+
+ apic_ops.disable();
+}
+
+static inline void
+lapic_eoi(void)
+{
+
+ apic_ops.eoi();
+}
+
+static inline int
+lapic_id(void)
+{
+
+ return (apic_ops.id());
+}
+
+static inline int
+lapic_intr_pending(u_int vector)
+{
+
+ return (apic_ops.intr_pending(vector));
+}
+
+/* XXX: UNUSED */
+static inline void
+lapic_set_logical_id(u_int apic_id, u_int cluster, u_int cluster_id)
+{
+
+ apic_ops.set_logical_id(apic_id, cluster, cluster_id);
+}
+
+static inline u_int
+apic_cpuid(u_int apic_id)
+{
+
+ return (apic_ops.cpuid(apic_id));
+}
+
+static inline u_int
+apic_alloc_vector(u_int apic_id, u_int irq)
+{
+
+ return (apic_ops.alloc_vector(apic_id, irq));
+}
+
+static inline u_int
+apic_alloc_vectors(u_int apic_id, u_int *irqs, u_int count, u_int align)
+{
+
+ return (apic_ops.alloc_vectors(apic_id, irqs, count, align));
+}
+
+static inline void
+apic_enable_vector(u_int apic_id, u_int vector)
+{
+
+ apic_ops.enable_vector(apic_id, vector);
+}
+
+static inline void
+apic_disable_vector(u_int apic_id, u_int vector)
+{
+
+ apic_ops.disable_vector(apic_id, vector);
+}
+
+static inline void
+apic_free_vector(u_int apic_id, u_int vector, u_int irq)
+{
+
+ apic_ops.free_vector(apic_id, vector, irq);
+}
+
+static inline int
+lapic_enable_pmc(void)
+{
+
+ return (apic_ops.enable_pmc());
+}
+
+static inline void
+lapic_disable_pmc(void)
+{
+
+ apic_ops.disable_pmc();
+}
+
+static inline void
+lapic_reenable_pmc(void)
+{
+
+ apic_ops.reenable_pmc();
+}
+
+static inline void
+lapic_enable_cmc(void)
+{
+
+ apic_ops.enable_cmc();
+}
+
+static inline int
+lapic_enable_mca_elvt(void)
+{
+
+ return (apic_ops.enable_mca_elvt());
+}
+
+static inline void
+lapic_ipi_raw(register_t icrlo, u_int dest)
+{
+
+ apic_ops.ipi_raw(icrlo, dest);
+}
+
+static inline void
+lapic_ipi_vectored(u_int vector, int dest)
+{
+
+ apic_ops.ipi_vectored(vector, dest);
+}
+
+static inline int
+lapic_ipi_wait(int delay)
+{
+
+ return (apic_ops.ipi_wait(delay));
+}
+
+static inline int
+lapic_ipi_alloc(inthand_t *ipifunc)
+{
+
+ return (apic_ops.ipi_alloc(ipifunc));
+}
+
+static inline void
+lapic_ipi_free(int vector)
+{
+
+ return (apic_ops.ipi_free(vector));
+}
+
+static inline int
+lapic_set_lvt_mask(u_int apic_id, u_int lvt, u_char masked)
+{
+
+ return (apic_ops.set_lvt_mask(apic_id, lvt, masked));
+}
+
+static inline int
+lapic_set_lvt_mode(u_int apic_id, u_int lvt, u_int32_t mode)
+{
+
+ return (apic_ops.set_lvt_mode(apic_id, lvt, mode));
+}
+
+static inline int
+lapic_set_lvt_polarity(u_int apic_id, u_int lvt, enum intr_polarity pol)
+{
+
+ return (apic_ops.set_lvt_polarity(apic_id, lvt, pol));
+}
+
+static inline int
+lapic_set_lvt_triggermode(u_int apic_id, u_int lvt, enum intr_trigger trigger)
+{
+
+ return (apic_ops.set_lvt_triggermode(apic_id, lvt, trigger));
+}
+
+void lapic_handle_cmc(void);
+void lapic_handle_error(void);
+void lapic_handle_intr(int vector, struct trapframe *frame);
+void lapic_handle_timer(struct trapframe *frame);
+
+int ioapic_get_rid(u_int apic_id, uint16_t *ridp);
+
+extern int x2apic_mode;
+extern int lapic_eoi_suppression;
+
+#ifdef _SYS_SYSCTL_H_
+SYSCTL_DECL(_hw_apic);
+#endif
+
+#endif /* !LOCORE */
+#endif /* _X86_APICVAR_H_ */
Property changes on: trunk/sys/x86/include/apicvar.h
___________________________________________________________________
Added: svn:eol-style
## -0,0 +1 ##
+native
\ No newline at end of property
Added: svn:keywords
## -0,0 +1 ##
+MidnightBSD=%H
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+text/plain
\ No newline at end of property
Modified: trunk/sys/x86/include/apm_bios.h
===================================================================
--- trunk/sys/x86/include/apm_bios.h 2020-02-08 19:32:41 UTC (rev 12310)
+++ trunk/sys/x86/include/apm_bios.h 2020-02-08 19:33:27 UTC (rev 12311)
@@ -13,7 +13,7 @@
*
* Aug, 1994 Implemented on FreeBSD 1.1.5.1R (Toshiba AVS001WD)
*
- * $FreeBSD: stable/10/sys/x86/include/apm_bios.h 215140 2010-11-11 19:36:21Z jkim $
+ * $FreeBSD: stable/11/sys/x86/include/apm_bios.h 215140 2010-11-11 19:36:21Z jkim $
*/
#ifndef _X86_APM_BIOS_H_
Modified: trunk/sys/x86/include/bus.h
===================================================================
--- trunk/sys/x86/include/bus.h 2020-02-08 19:32:41 UTC (rev 12310)
+++ trunk/sys/x86/include/bus.h 2020-02-08 19:33:27 UTC (rev 12311)
@@ -29,7 +29,7 @@
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
- * $FreeBSD: stable/10/sys/x86/include/bus.h 287126 2015-08-25 14:39:40Z marcel $
+ * $FreeBSD: stable/11/sys/x86/include/bus.h 286667 2015-08-12 15:26:32Z marcel $
*/
/* $NetBSD: bus.h,v 1.12 1997/10/01 08:25:15 fvdl Exp $ */
Modified: trunk/sys/x86/include/busdma_impl.h
===================================================================
--- trunk/sys/x86/include/busdma_impl.h 2020-02-08 19:32:41 UTC (rev 12310)
+++ trunk/sys/x86/include/busdma_impl.h 2020-02-08 19:33:27 UTC (rev 12311)
@@ -27,7 +27,7 @@
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*
- * $FreeBSD: stable/10/sys/x86/include/busdma_impl.h 259512 2013-12-17 13:49:35Z kib $
+ * $FreeBSD: stable/11/sys/x86/include/busdma_impl.h 257308 2013-10-29 07:25:54Z kib $
*/
#ifndef __X86_BUSDMA_IMPL_H
Added: trunk/sys/x86/include/cputypes.h
===================================================================
--- trunk/sys/x86/include/cputypes.h (rev 0)
+++ trunk/sys/x86/include/cputypes.h 2020-02-08 19:33:27 UTC (rev 12311)
@@ -0,0 +1,50 @@
+/* $MidnightBSD$ */
+/*-
+ * Copyright (c) 1993 Christopher G. Demetriou
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ * derived from this software without specific prior written permission
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+ * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+ * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * $FreeBSD: stable/11/sys/x86/include/cputypes.h 308433 2016-11-08 06:13:22Z jhb $
+ */
+
+#ifndef _X86_CPUTYPES_H_
+#define _X86_CPUTYPES_H_
+
+/*
+ * Vendors of processor.
+ */
+#define CPU_VENDOR_NSC 0x100b /* NSC */
+#define CPU_VENDOR_IBM 0x1014 /* IBM */
+#define CPU_VENDOR_AMD 0x1022 /* AMD */
+#define CPU_VENDOR_SIS 0x1039 /* SiS */
+#define CPU_VENDOR_UMC 0x1060 /* UMC */
+#define CPU_VENDOR_NEXGEN 0x1074 /* Nexgen */
+#define CPU_VENDOR_CYRIX 0x1078 /* Cyrix */
+#define CPU_VENDOR_IDT 0x111d /* Centaur/IDT/VIA */
+#define CPU_VENDOR_TRANSMETA 0x1279 /* Transmeta */
+#define CPU_VENDOR_INTEL 0x8086 /* Intel */
+#define CPU_VENDOR_RISE 0xdead2bad /* Rise */
+#define CPU_VENDOR_CENTAUR CPU_VENDOR_IDT
+
+#endif /* !_X86_CPUTYPES_H_ */
Property changes on: trunk/sys/x86/include/cputypes.h
___________________________________________________________________
Added: svn:eol-style
## -0,0 +1 ##
+native
\ No newline at end of property
Added: svn:keywords
## -0,0 +1 ##
+MidnightBSD=%H
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+text/plain
\ No newline at end of property
Added: trunk/sys/x86/include/dump.h
===================================================================
--- trunk/sys/x86/include/dump.h (rev 0)
+++ trunk/sys/x86/include/dump.h 2020-02-08 19:33:27 UTC (rev 12311)
@@ -0,0 +1,88 @@
+/* $MidnightBSD$ */
+/*-
+ * Copyright (c) 2014 EMC Corp.
+ * Author: Conrad Meyer <conrad.meyer at isilon.com>
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ * $FreeBSD: stable/11/sys/x86/include/dump.h 276772 2015-01-07 01:01:39Z markj $
+ */
+
+#ifndef _MACHINE_DUMP_H_
+#define _MACHINE_DUMP_H_
+
+#ifdef __amd64__
+#define KERNELDUMP_ARCH_VERSION KERNELDUMP_AMD64_VERSION
+#define EM_VALUE EM_X86_64
+#else
+#define KERNELDUMP_ARCH_VERSION KERNELDUMP_I386_VERSION
+#define EM_VALUE EM_386
+#endif
+
+/* 20 phys_avail entry pairs correspond to 10 pa's */
+#define DUMPSYS_MD_PA_NPAIRS 10
+#define DUMPSYS_NUM_AUX_HDRS 0
+
+static inline void
+dumpsys_pa_init(void)
+{
+
+ dumpsys_gen_pa_init();
+}
+
+static inline struct dump_pa *
+dumpsys_pa_next(struct dump_pa *p)
+{
+
+ return (dumpsys_gen_pa_next(p));
+}
+
+static inline void
+dumpsys_wbinv_all(void)
+{
+
+ dumpsys_gen_wbinv_all();
+}
+
+static inline void
+dumpsys_unmap_chunk(vm_paddr_t pa, size_t s, void *va)
+{
+
+ dumpsys_gen_unmap_chunk(pa, s, va);
+}
+
+static inline int
+dumpsys_write_aux_headers(struct dumperinfo *di)
+{
+
+ return (dumpsys_gen_write_aux_headers(di));
+}
+
+static inline int
+dumpsys(struct dumperinfo *di)
+{
+
+ return (dumpsys_generic(di));
+}
+
+#endif /* !_MACHINE_DUMP_H_ */
Property changes on: trunk/sys/x86/include/dump.h
___________________________________________________________________
Added: svn:eol-style
## -0,0 +1 ##
+native
\ No newline at end of property
Added: svn:keywords
## -0,0 +1 ##
+MidnightBSD=%H
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+text/plain
\ No newline at end of property
Modified: trunk/sys/x86/include/elf.h
===================================================================
--- trunk/sys/x86/include/elf.h 2020-02-08 19:32:41 UTC (rev 12310)
+++ trunk/sys/x86/include/elf.h 2020-02-08 19:33:27 UTC (rev 12311)
@@ -24,7 +24,7 @@
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*
- * $FreeBSD: stable/10/sys/x86/include/elf.h 247047 2013-02-20 17:39:52Z kib $
+ * $FreeBSD: stable/11/sys/x86/include/elf.h 325810 2017-11-14 16:03:07Z jhb $
*/
#ifndef _MACHINE_ELF_H_
@@ -101,8 +101,11 @@
#define AT_PAGESIZESLEN 21 /* Number of pagesizes. */
#define AT_TIMEKEEP 22 /* Pointer to timehands. */
#define AT_STACKPROT 23 /* Initial stack protection. */
+#define AT_EHDRFLAGS 24 /* e_flags field from elf hdr */
+#define AT_HWCAP 25 /* CPU feature flags. */
+#define AT_HWCAP2 26 /* CPU feature flags 2. */
-#define AT_COUNT 24 /* Count of defined aux entry types. */
+#define AT_COUNT 27 /* Count of defined aux entry types. */
/*
* Relocation types.
@@ -186,8 +189,11 @@
#define AT_PAGESIZESLEN 21 /* Number of pagesizes. */
#define AT_TIMEKEEP 22 /* Pointer to timehands. */
#define AT_STACKPROT 23 /* Initial stack protection. */
+#define AT_EHDRFLAGS 24 /* e_flags field from elf hdr */
+#define AT_HWCAP 25 /* CPU feature flags. */
+#define AT_HWCAP2 26 /* CPU feature flags 2. */
-#define AT_COUNT 24 /* Count of defined aux entry types. */
+#define AT_COUNT 27 /* Count of defined aux entry types. */
/*
* Relocation types.
Modified: trunk/sys/x86/include/endian.h
===================================================================
--- trunk/sys/x86/include/endian.h 2020-02-08 19:32:41 UTC (rev 12310)
+++ trunk/sys/x86/include/endian.h 2020-02-08 19:33:27 UTC (rev 12311)
@@ -28,7 +28,7 @@
* SUCH DAMAGE.
*
* @(#)endian.h 7.8 (Berkeley) 4/3/91
- * $FreeBSD: stable/10/sys/x86/include/endian.h 233684 2012-03-29 23:31:48Z dim $
+ * $FreeBSD: stable/11/sys/x86/include/endian.h 331722 2018-03-29 02:50:57Z eadler $
*/
#ifndef _MACHINE_ENDIAN_H_
Modified: trunk/sys/x86/include/fdt.h
===================================================================
--- trunk/sys/x86/include/fdt.h 2020-02-08 19:32:41 UTC (rev 12310)
+++ trunk/sys/x86/include/fdt.h 2020-02-08 19:33:27 UTC (rev 12311)
@@ -24,7 +24,7 @@
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*
- * $FreeBSD: stable/10/sys/x86/include/fdt.h 266084 2014-05-14 19:18:58Z ian $
+ * $FreeBSD: stable/11/sys/x86/include/fdt.h 260327 2014-01-05 18:46:58Z nwhitehorn $
*/
#ifndef _MACHINE_FDT_H_
Modified: trunk/sys/x86/include/float.h
===================================================================
--- trunk/sys/x86/include/float.h 2020-02-08 19:32:41 UTC (rev 12310)
+++ trunk/sys/x86/include/float.h 2020-02-08 19:33:27 UTC (rev 12311)
@@ -11,7 +11,7 @@
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
- * 4. Neither the name of the University nor the names of its contributors
+ * 3. Neither the name of the University nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
@@ -28,7 +28,7 @@
* SUCH DAMAGE.
*
* from: @(#)float.h 7.1 (Berkeley) 5/8/90
- * $FreeBSD: stable/10/sys/x86/include/float.h 235939 2012-05-24 21:44:46Z obrien $
+ * $FreeBSD: stable/11/sys/x86/include/float.h 331722 2018-03-29 02:50:57Z eadler $
*/
#ifndef _MACHINE_FLOAT_H_
Modified: trunk/sys/x86/include/fpu.h
===================================================================
--- trunk/sys/x86/include/fpu.h 2020-02-08 19:32:41 UTC (rev 12310)
+++ trunk/sys/x86/include/fpu.h 2020-02-08 19:33:27 UTC (rev 12311)
@@ -31,7 +31,7 @@
* SUCH DAMAGE.
*
* from: @(#)npx.h 5.3 (Berkeley) 1/18/91
- * $FreeBSD: stable/10/sys/x86/include/fpu.h 279211 2015-02-23 18:38:41Z jhb $
+ * $FreeBSD: stable/11/sys/x86/include/fpu.h 274817 2014-11-21 20:53:17Z jhb $
*/
/*
Modified: trunk/sys/x86/include/frame.h
===================================================================
--- trunk/sys/x86/include/frame.h 2020-02-08 19:32:41 UTC (rev 12310)
+++ trunk/sys/x86/include/frame.h 2020-02-08 19:33:27 UTC (rev 12311)
@@ -32,7 +32,7 @@
* SUCH DAMAGE.
*
* from: @(#)frame.h 5.2 (Berkeley) 1/18/91
- * $FreeBSD: stable/10/sys/x86/include/frame.h 247047 2013-02-20 17:39:52Z kib $
+ * $FreeBSD: stable/11/sys/x86/include/frame.h 331722 2018-03-29 02:50:57Z eadler $
*/
#ifndef _MACHINE_FRAME_H_
@@ -65,7 +65,7 @@
int tf_eip;
int tf_cs;
int tf_eflags;
- /* below only when crossing rings (e.g. user to kernel) */
+ /* below only when crossing rings (user to kernel) */
int tf_esp;
int tf_ss;
};
@@ -90,15 +90,24 @@
int tf_eip;
int tf_cs;
int tf_eflags;
- /* below only when crossing rings (e.g. user to kernel) */
+ /* below only when crossing rings (user (including vm86) to kernel) */
int tf_esp;
int tf_ss;
- /* below only when switching out of VM86 mode */
+ /* below only when crossing from vm86 mode to kernel */
int tf_vm86_es;
int tf_vm86_ds;
int tf_vm86_fs;
int tf_vm86_gs;
};
+
+/*
+ * This alias for the MI TRAPF_USERMODE() should be used when we don't
+ * care about user mode itself, but need to know if a frame has stack
+ * registers. The difference is only logical, but on i386 the logic
+ * for using TRAPF_USERMODE() is complicated by sometimes treating vm86
+ * bioscall mode (which is a special ring 3 user mode) as kernel mode.
+ */
+#define TF_HAS_STACKREGS(tf) TRAPF_USERMODE(tf)
#endif /* __i386__ */
#ifdef __amd64__
@@ -137,6 +146,7 @@
register_t tf_rip;
register_t tf_cs;
register_t tf_rflags;
+ /* the amd64 frame always has the stack registers */
register_t tf_rsp;
register_t tf_ss;
};
Added: trunk/sys/x86/include/ifunc.h
===================================================================
--- trunk/sys/x86/include/ifunc.h (rev 0)
+++ trunk/sys/x86/include/ifunc.h 2020-02-08 19:33:27 UTC (rev 12311)
@@ -0,0 +1,51 @@
+/* $MidnightBSD$ */
+/*-
+ * Copyright (c) 2015-2018 The FreeBSD Foundation
+ * All rights reserved.
+ *
+ * This software was developed by Konstantin Belousov <kib at FreeBSD.org>
+ * under sponsorship from the FreeBSD Foundation.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ * $FreeBSD: stable/11/sys/x86/include/ifunc.h 339217 2018-10-07 00:40:56Z kib $
+ */
+
+#ifndef __X86_IFUNC_H
+#define __X86_IFUNC_H
+
+#define DEFINE_IFUNC(qual, ret_type, name, args, resolver_qual) \
+ resolver_qual ret_type (*name##_resolver(void))args __used; \
+ qual ret_type name args __attribute__((ifunc(#name "_resolver"))); \
+ resolver_qual ret_type (*name##_resolver(void))args
+
+#define DEFINE_UIFUNC(qual, ret_type, name, args, resolver_qual) \
+ resolver_qual ret_type (*name##_resolver(uint32_t, uint32_t, \
+ uint32_t, uint32_t))args __used; \
+ qual ret_type name args __attribute__((ifunc(#name "_resolver"))); \
+ resolver_qual ret_type (*name##_resolver( \
+ uint32_t cpu_feature __unused, \
+ uint32_t cpu_feature2 __unused, \
+ uint32_t cpu_stdext_feature __unused, \
+ uint32_t cpu_stdext_feature2 __unused))args
+
+#endif
Property changes on: trunk/sys/x86/include/ifunc.h
___________________________________________________________________
Added: svn:eol-style
## -0,0 +1 ##
+native
\ No newline at end of property
Added: svn:keywords
## -0,0 +1 ##
+MidnightBSD=%H
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+text/plain
\ No newline at end of property
Added: trunk/sys/x86/include/init.h
===================================================================
--- trunk/sys/x86/include/init.h (rev 0)
+++ trunk/sys/x86/include/init.h 2020-02-08 19:33:27 UTC (rev 12311)
@@ -0,0 +1,59 @@
+/* $MidnightBSD$ */
+/*-
+ * Copyright (c) 2013 Roger Pau Monné <roger.pau at citrix.com>
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ * $FreeBSD: stable/11/sys/x86/include/init.h 272310 2014-09-30 16:46:45Z royger $
+ */
+
+#ifndef __X86_INIT_H__
+#define __X86_INIT_H__
+/*
+ * Struct containing pointers to init functions whose
+ * implementation is run time selectable. Selection can be made,
+ * for example, based on detection of a BIOS variant or
+ * hypervisor environment.
+ */
+struct init_ops {
+ caddr_t (*parse_preload_data)(u_int64_t);
+ void (*early_clock_source_init)(void);
+ void (*early_delay)(int);
+ void (*parse_memmap)(caddr_t, vm_paddr_t *, int *);
+ u_int (*mp_bootaddress)(u_int);
+ int (*start_all_aps)(void);
+ void (*msi_init)(void);
+};
+
+extern struct init_ops init_ops;
+
+/* Knob to disable acpi_cpu devices */
+extern bool acpi_cpu_disabled;
+
+/* Knob to disable acpi_hpet device */
+extern bool acpi_hpet_disabled;
+
+/* Knob to disable acpi_timer device */
+extern bool acpi_timer_disabled;
+
+#endif /* __X86_INIT_H__ */
Property changes on: trunk/sys/x86/include/init.h
___________________________________________________________________
Added: svn:eol-style
## -0,0 +1 ##
+native
\ No newline at end of property
Added: svn:keywords
## -0,0 +1 ##
+MidnightBSD=%H
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+text/plain
\ No newline at end of property
Added: trunk/sys/x86/include/intr_machdep.h
===================================================================
--- trunk/sys/x86/include/intr_machdep.h (rev 0)
+++ trunk/sys/x86/include/intr_machdep.h 2020-02-08 19:33:27 UTC (rev 12311)
@@ -0,0 +1,177 @@
+/* $MidnightBSD$ */
+/*-
+ * Copyright (c) 2003 John Baldwin <jhb at FreeBSD.org>
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ * $FreeBSD: stable/11/sys/x86/include/intr_machdep.h 342656 2018-12-31 22:09:08Z jhb $
+ */
+
+#ifndef __X86_INTR_MACHDEP_H__
+#define __X86_INTR_MACHDEP_H__
+
+#ifdef _KERNEL
+
+/*
+ * Values used in determining the allocation of IRQ values among
+ * different types of I/O interrupts. These values are used as
+ * indices into a interrupt source array to map I/O interrupts to a
+ * device interrupt source whether it be a pin on an interrupt
+ * controller or an MSI interrupt. The 16 ISA IRQs are assigned fixed
+ * IDT vectors, but all other device interrupts allocate IDT vectors
+ * on demand. Currently we have 191 IDT vectors available for device
+ * interrupts on each CPU. On many systems with I/O APICs, a lot of
+ * the IRQs are not used, so the total number of IRQ values reserved
+ * can exceed the number of available IDT slots.
+ *
+ * The first 16 IRQs (0 - 15) are reserved for ISA IRQs. Interrupt
+ * pins on I/O APICs for non-ISA interrupts use IRQ values starting at
+ * IRQ 17. This layout matches the GSI numbering used by ACPI so that
+ * IRQ values returned by ACPI methods such as _CRS can be used
+ * directly by the ACPI bus driver.
+ *
+ * MSI interrupts allocate a block of interrupts starting at either
+ * the end of the I/O APIC range or 256, whichever is higher. When
+ * running under the Xen Hypervisor, an additional range of IRQ values
+ * are available for binding to event channel events. We use 256 as
+ * the minimum IRQ value for MSI interrupts to attempt to leave 255
+ * unused since 255 is used in PCI to indicate an invalid INTx IRQ.
+ */
+#define MINIMUM_MSI_INT 256
+
+extern u_int first_msi_irq;
+extern u_int num_io_irqs;
+extern u_int num_msi_irqs;
+
+/*
+ * Default base address for MSI messages on x86 platforms.
+ */
+#define MSI_INTEL_ADDR_BASE 0xfee00000
+
+#ifndef LOCORE
+
+typedef void inthand_t(void);
+
+#define IDTVEC(name) __CONCAT(X,name)
+
+struct intsrc;
+
+/*
+ * Methods that a PIC provides to mask/unmask a given interrupt source,
+ * "turn on" the interrupt on the CPU side by setting up an IDT entry, and
+ * return the vector associated with this source.
+ */
+struct pic {
+ void (*pic_register_sources)(struct pic *);
+ void (*pic_enable_source)(struct intsrc *);
+ void (*pic_disable_source)(struct intsrc *, int);
+ void (*pic_eoi_source)(struct intsrc *);
+ void (*pic_enable_intr)(struct intsrc *);
+ void (*pic_disable_intr)(struct intsrc *);
+ int (*pic_vector)(struct intsrc *);
+ int (*pic_source_pending)(struct intsrc *);
+ void (*pic_suspend)(struct pic *);
+ void (*pic_resume)(struct pic *, bool suspend_cancelled);
+ int (*pic_config_intr)(struct intsrc *, enum intr_trigger,
+ enum intr_polarity);
+ int (*pic_assign_cpu)(struct intsrc *, u_int apic_id);
+ void (*pic_reprogram_pin)(struct intsrc *);
+ TAILQ_ENTRY(pic) pics;
+};
+
+/* Flags for pic_disable_source() */
+enum {
+ PIC_EOI,
+ PIC_NO_EOI,
+};
+
+/*
+ * An interrupt source. The upper-layer code uses the PIC methods to
+ * control a given source. The lower-layer PIC drivers can store additional
+ * private data in a given interrupt source such as an interrupt pin number
+ * or an I/O APIC pointer.
+ */
+struct intsrc {
+ struct pic *is_pic;
+ struct intr_event *is_event;
+ u_long *is_count;
+ u_long *is_straycount;
+ u_int is_index;
+ u_int is_handlers;
+};
+
+struct trapframe;
+
+#ifdef SMP
+extern cpuset_t intr_cpus;
+#endif
+extern struct mtx icu_lock;
+extern int elcr_found;
+#ifdef SMP
+extern int msix_disable_migration;
+#endif
+
+#ifndef DEV_ATPIC
+void atpic_reset(void);
+#endif
+/* XXX: The elcr_* prototypes probably belong somewhere else. */
+int elcr_probe(void);
+enum intr_trigger elcr_read_trigger(u_int irq);
+void elcr_resume(void);
+void elcr_write_trigger(u_int irq, enum intr_trigger trigger);
+#ifdef SMP
+void intr_add_cpu(u_int cpu);
+#endif
+int intr_add_handler(const char *name, int vector, driver_filter_t filter,
+ driver_intr_t handler, void *arg, enum intr_type flags,
+ void **cookiep);
+#ifdef SMP
+int intr_bind(u_int vector, u_char cpu);
+#endif
+int intr_config_intr(int vector, enum intr_trigger trig,
+ enum intr_polarity pol);
+int intr_describe(u_int vector, void *ih, const char *descr);
+void intr_execute_handlers(struct intsrc *isrc, struct trapframe *frame);
+u_int intr_next_cpu(void);
+struct intsrc *intr_lookup_source(int vector);
+int intr_register_pic(struct pic *pic);
+int intr_register_source(struct intsrc *isrc);
+int intr_remove_handler(void *cookie);
+void intr_resume(bool suspend_cancelled);
+void intr_suspend(void);
+void intr_reprogram(void);
+void intrcnt_add(const char *name, u_long **countp);
+void nexus_add_irq(u_long irq);
+int msi_alloc(device_t dev, int count, int maxcount, int *irqs);
+void msi_init(void);
+int msi_map(int irq, uint64_t *addr, uint32_t *data);
+int msi_release(int *irqs, int count);
+int msix_alloc(device_t dev, int *irq);
+int msix_release(int irq);
+#ifdef XENHVM
+void xen_intr_alloc_irqs(void);
+#endif
+
+#endif /* !LOCORE */
+#endif /* _KERNEL */
+#endif /* !__X86_INTR_MACHDEP_H__ */
Property changes on: trunk/sys/x86/include/intr_machdep.h
___________________________________________________________________
Added: svn:eol-style
## -0,0 +1 ##
+native
\ No newline at end of property
Added: svn:keywords
## -0,0 +1 ##
+MidnightBSD=%H
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+text/plain
\ No newline at end of property
Modified: trunk/sys/x86/include/legacyvar.h
===================================================================
--- trunk/sys/x86/include/legacyvar.h 2020-02-08 19:32:41 UTC (rev 12310)
+++ trunk/sys/x86/include/legacyvar.h 2020-02-08 19:33:27 UTC (rev 12311)
@@ -24,7 +24,7 @@
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*
- * $FreeBSD: stable/10/sys/x86/include/legacyvar.h 280970 2015-04-01 21:48:54Z jhb $
+ * $FreeBSD: stable/11/sys/x86/include/legacyvar.h 294883 2016-01-27 02:23:54Z jhibbits $
*/
#ifndef _X86_LEGACYVAR_H_
@@ -57,9 +57,10 @@
int legacy_pcib_write_ivar(device_t dev, device_t child, int which,
uintptr_t value);
struct resource *legacy_pcib_alloc_resource(device_t dev, device_t child,
- int type, int *rid, u_long start, u_long end, u_long count, u_int flags);
+ int type, int *rid, rman_res_t start, rman_res_t end, rman_res_t count,
+ u_int flags);
int legacy_pcib_adjust_resource(device_t dev, device_t child, int type,
- struct resource *r, u_long start, u_long end);
+ struct resource *r, rman_res_t start, rman_res_t end);
int legacy_pcib_release_resource(device_t dev, device_t child, int type,
int rid, struct resource *r);
int legacy_pcib_alloc_msi(device_t pcib, device_t dev, int count,
Modified: trunk/sys/x86/include/mca.h
===================================================================
--- trunk/sys/x86/include/mca.h 2020-02-08 19:32:41 UTC (rev 12310)
+++ trunk/sys/x86/include/mca.h 2020-02-08 19:33:27 UTC (rev 12311)
@@ -25,7 +25,7 @@
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*
- * $FreeBSD: stable/10/sys/x86/include/mca.h 283927 2015-06-02 19:20:39Z jhb $
+ * $FreeBSD: stable/11/sys/x86/include/mca.h 281887 2015-04-23 14:22:20Z jhb $
*/
#ifndef __X86_MCA_H__
Modified: trunk/sys/x86/include/metadata.h
===================================================================
--- trunk/sys/x86/include/metadata.h 2020-02-08 19:32:41 UTC (rev 12310)
+++ trunk/sys/x86/include/metadata.h 2020-02-08 19:33:27 UTC (rev 12311)
@@ -24,7 +24,7 @@
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*
- * $FreeBSD: stable/10/sys/x86/include/metadata.h 294274 2016-01-18 15:52:07Z emaste $
+ * $FreeBSD: stable/11/sys/x86/include/metadata.h 293343 2016-01-07 19:47:26Z emaste $
*/
#ifndef _MACHINE_METADATA_H_
Modified: trunk/sys/x86/include/mptable.h
===================================================================
--- trunk/sys/x86/include/mptable.h 2020-02-08 19:32:41 UTC (rev 12310)
+++ trunk/sys/x86/include/mptable.h 2020-02-08 19:33:27 UTC (rev 12311)
@@ -23,7 +23,7 @@
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*
- * $FreeBSD: stable/10/sys/x86/include/mptable.h 259837 2013-12-24 19:10:56Z jhb $
+ * $FreeBSD: stable/11/sys/x86/include/mptable.h 259228 2013-12-11 21:19:04Z jhb $
*/
#ifndef __MACHINE_MPTABLE_H__
@@ -31,10 +31,13 @@
enum busTypes {
NOBUS = 0,
+ CBUS = 1,
+ CBUSII = 2,
EISA = 3,
ISA = 6,
MCA = 9,
PCI = 13,
+ XPRESS = 18,
MAX_BUSTYPE = 18,
UNKNOWN_BUSTYPE = 0xff
};
@@ -41,17 +44,17 @@
/* MP Floating Pointer Structure */
typedef struct MPFPS {
- char signature[4];
- u_int32_t pap;
- u_char length;
- u_char spec_rev;
- u_char checksum;
- u_char config_type;
- u_char mpfb2;
- u_char mpfb3;
- u_char mpfb4;
- u_char mpfb5;
-} *mpfps_t;
+ uint8_t signature[4];
+ uint32_t pap;
+ uint8_t length;
+ uint8_t spec_rev;
+ uint8_t checksum;
+ uint8_t config_type;
+ uint8_t mpfb2;
+ uint8_t mpfb3;
+ uint8_t mpfb4;
+ uint8_t mpfb5;
+} __packed *mpfps_t;
#define MPFB2_IMCR_PRESENT 0x80
#define MPFB2_MUL_CLK_SRCS 0x40
@@ -58,20 +61,20 @@
/* MP Configuration Table Header */
typedef struct MPCTH {
- char signature[4];
- u_short base_table_length;
- u_char spec_rev;
- u_char checksum;
- u_char oem_id[8];
- u_char product_id[12];
- u_int32_t oem_table_pointer;
- u_short oem_table_size;
- u_short entry_count;
- u_int32_t apic_address;
- u_short extended_table_length;
- u_char extended_table_checksum;
- u_char reserved;
-} *mpcth_t;
+ uint8_t signature[4];
+ uint16_t base_table_length;
+ uint8_t spec_rev;
+ uint8_t checksum;
+ uint8_t oem_id[8];
+ uint8_t product_id[12];
+ uint32_t oem_table_pointer;
+ uint16_t oem_table_size;
+ uint16_t entry_count;
+ uint32_t apic_address;
+ uint16_t extended_table_length;
+ uint8_t extended_table_checksum;
+ uint8_t reserved;
+} __packed *mpcth_t;
/* Base table entries */
@@ -82,44 +85,44 @@
#define MPCT_ENTRY_LOCAL_INT 4
typedef struct PROCENTRY {
- u_char type;
- u_char apic_id;
- u_char apic_version;
- u_char cpu_flags;
- u_int32_t cpu_signature;
- u_int32_t feature_flags;
- u_int32_t reserved1;
- u_int32_t reserved2;
-} *proc_entry_ptr;
+ uint8_t type;
+ uint8_t apic_id;
+ uint8_t apic_version;
+ uint8_t cpu_flags;
+ uint32_t cpu_signature;
+ uint32_t feature_flags;
+ uint32_t reserved1;
+ uint32_t reserved2;
+} __packed *proc_entry_ptr;
#define PROCENTRY_FLAG_EN 0x01
#define PROCENTRY_FLAG_BP 0x02
typedef struct BUSENTRY {
- u_char type;
- u_char bus_id;
- char bus_type[6];
-} *bus_entry_ptr;
+ uint8_t type;
+ uint8_t bus_id;
+ uint8_t bus_type[6];
+} __packed *bus_entry_ptr;
typedef struct IOAPICENTRY {
- u_char type;
- u_char apic_id;
- u_char apic_version;
- u_char apic_flags;
- u_int32_t apic_address;
-} *io_apic_entry_ptr;
+ uint8_t type;
+ uint8_t apic_id;
+ uint8_t apic_version;
+ uint8_t apic_flags;
+ uint32_t apic_address;
+} __packed *io_apic_entry_ptr;
#define IOAPICENTRY_FLAG_EN 0x01
typedef struct INTENTRY {
- u_char type;
- u_char int_type;
- u_short int_flags;
- u_char src_bus_id;
- u_char src_bus_irq;
- u_char dst_apic_id;
- u_char dst_apic_int;
-} *int_entry_ptr;
+ uint8_t type;
+ uint8_t int_type;
+ uint16_t int_flags;
+ uint8_t src_bus_id;
+ uint8_t src_bus_irq;
+ uint8_t dst_apic_id;
+ uint8_t dst_apic_int;
+} __packed *int_entry_ptr;
#define INTENTRY_TYPE_INT 0
#define INTENTRY_TYPE_NMI 1
@@ -138,9 +141,9 @@
/* Extended table entries */
typedef struct EXTENTRY {
- u_char type;
- u_char length;
-} *ext_entry_ptr;
+ uint8_t type;
+ uint8_t length;
+} __packed *ext_entry_ptr;
#define MPCT_EXTENTRY_SAS 0x80
#define MPCT_EXTENTRY_BHD 0x81
@@ -147,13 +150,13 @@
#define MPCT_EXTENTRY_CBASM 0x82
typedef struct SASENTRY {
- u_char type;
- u_char length;
- u_char bus_id;
- u_char address_type;
+ uint8_t type;
+ uint8_t length;
+ uint8_t bus_id;
+ uint8_t address_type;
uint64_t address_base;
uint64_t address_length;
-} __attribute__((__packed__)) *sas_entry_ptr;
+} __packed *sas_entry_ptr;
#define SASENTRY_TYPE_IO 0
#define SASENTRY_TYPE_MEMORY 1
@@ -160,23 +163,23 @@
#define SASENTRY_TYPE_PREFETCH 2
typedef struct BHDENTRY {
- u_char type;
- u_char length;
- u_char bus_id;
- u_char bus_info;
- u_char parent_bus;
- u_char reserved[3];
-} *bhd_entry_ptr;
+ uint8_t type;
+ uint8_t length;
+ uint8_t bus_id;
+ uint8_t bus_info;
+ uint8_t parent_bus;
+ uint8_t reserved[3];
+} __packed *bhd_entry_ptr;
#define BHDENTRY_INFO_SUBTRACTIVE_DECODE 0x1
typedef struct CBASMENTRY {
- u_char type;
- u_char length;
- u_char bus_id;
- u_char address_mod;
- u_int predefined_range;
-} *cbasm_entry_ptr;
+ uint8_t type;
+ uint8_t length;
+ uint8_t bus_id;
+ uint8_t address_mod;
+ uint32_t predefined_range;
+} __packed *cbasm_entry_ptr;
#define CBASMENTRY_ADDRESS_MOD_ADD 0x0
#define CBASMENTRY_ADDRESS_MOD_SUBTRACT 0x1
@@ -184,13 +187,6 @@
#define CBASMENTRY_RANGE_ISA_IO 0
#define CBASMENTRY_RANGE_VGA_IO 1
-/* descriptions of MP table entries */
-typedef struct BASETABLE_ENTRY {
- u_char type;
- u_char length;
- char name[16];
-} basetable_entry;
-
#ifdef _KERNEL
struct mptable_hostb_softc {
#ifdef NEW_PCIB
Modified: trunk/sys/x86/include/ofw_machdep.h
===================================================================
--- trunk/sys/x86/include/ofw_machdep.h 2020-02-08 19:32:41 UTC (rev 12310)
+++ trunk/sys/x86/include/ofw_machdep.h 2020-02-08 19:33:27 UTC (rev 12311)
@@ -24,13 +24,13 @@
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*
- * $FreeBSD: stable/10/sys/x86/include/ofw_machdep.h 266084 2014-05-14 19:18:58Z ian $
+ * $FreeBSD: stable/11/sys/x86/include/ofw_machdep.h 287260 2015-08-28 15:41:09Z imp $
*/
#ifndef _MACHINE_OFW_MACHDEP_H_
#define _MACHINE_OFW_MACHDEP_H_
-#include <x86/bus.h>
+#include <machine/bus.h>
#include <vm/vm.h>
typedef uint32_t cell_t;
Modified: trunk/sys/x86/include/pci_cfgreg.h
===================================================================
--- trunk/sys/x86/include/pci_cfgreg.h 2020-02-08 19:32:41 UTC (rev 12310)
+++ trunk/sys/x86/include/pci_cfgreg.h 2020-02-08 19:33:27 UTC (rev 12311)
@@ -24,7 +24,7 @@
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
- * $FreeBSD: stable/10/sys/x86/include/pci_cfgreg.h 223440 2011-06-22 21:04:13Z jhb $
+ * $FreeBSD: stable/11/sys/x86/include/pci_cfgreg.h 294883 2016-01-27 02:23:54Z jhibbits $
*
*/
@@ -47,7 +47,7 @@
#define CONF2_ENABLE_CHK 0x0e
#define CONF2_ENABLE_RES 0x0e
-u_long hostb_alloc_start(int type, u_long start, u_long end, u_long count);
+rman_res_t hostb_alloc_start(int type, rman_res_t start, rman_res_t end, rman_res_t count);
int pcie_cfgregopen(uint64_t base, uint8_t minbus, uint8_t maxbus);
int pci_cfgregopen(void);
u_int32_t pci_cfgregread(int bus, int slot, int func, int reg, int bytes);
Modified: trunk/sys/x86/include/psl.h
===================================================================
--- trunk/sys/x86/include/psl.h 2020-02-08 19:32:41 UTC (rev 12310)
+++ trunk/sys/x86/include/psl.h 2020-02-08 19:33:27 UTC (rev 12311)
@@ -31,7 +31,7 @@
* SUCH DAMAGE.
*
* from: @(#)psl.h 5.2 (Berkeley) 1/18/91
- * $FreeBSD: stable/10/sys/x86/include/psl.h 258559 2013-11-25 15:58:48Z emaste $
+ * $FreeBSD: stable/11/sys/x86/include/psl.h 331722 2018-03-29 02:50:57Z eadler $
*/
#ifndef _MACHINE_PSL_H_
Modified: trunk/sys/x86/include/ptrace.h
===================================================================
--- trunk/sys/x86/include/ptrace.h 2020-02-08 19:32:41 UTC (rev 12310)
+++ trunk/sys/x86/include/ptrace.h 2020-02-08 19:33:27 UTC (rev 12311)
@@ -28,7 +28,7 @@
* SUCH DAMAGE.
*
* @(#)ptrace.h 8.1 (Berkeley) 6/11/93
- * $FreeBSD: stable/10/sys/x86/include/ptrace.h 286311 2015-08-05 08:17:10Z kib $
+ * $FreeBSD: stable/11/sys/x86/include/ptrace.h 331722 2018-03-29 02:50:57Z eadler $
*/
#ifndef _MACHINE_PTRACE_H_
Added: trunk/sys/x86/include/pvclock.h
===================================================================
--- trunk/sys/x86/include/pvclock.h (rev 0)
+++ trunk/sys/x86/include/pvclock.h 2020-02-08 19:33:27 UTC (rev 12311)
@@ -0,0 +1,60 @@
+/* $MidnightBSD$ */
+/*-
+ * Copyright (c) 2014, Bryan Venteicher <bryanv at FreeBSD.org>
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ * $FreeBSD: stable/11/sys/x86/include/pvclock.h 278184 2015-02-04 08:33:04Z bryanv $
+ */
+
+#ifndef X86_PVCLOCK
+#define X86_PVCLOCK
+
+struct pvclock_vcpu_time_info {
+ uint32_t version;
+ uint32_t pad0;
+ uint64_t tsc_timestamp;
+ uint64_t system_time;
+ uint32_t tsc_to_system_mul;
+ int8_t tsc_shift;
+ uint8_t flags;
+ uint8_t pad[2];
+};
+
+#define PVCLOCK_FLAG_TSC_STABLE 0x01
+#define PVCLOCK_FLAG_GUEST_PASUED 0x02
+
+struct pvclock_wall_clock {
+ uint32_t version;
+ uint32_t sec;
+ uint32_t nsec;
+};
+
+void pvclock_resume(void);
+uint64_t pvclock_get_last_cycles(void);
+uint64_t pvclock_tsc_freq(struct pvclock_vcpu_time_info *ti);
+uint64_t pvclock_get_timecount(struct pvclock_vcpu_time_info *ti);
+void pvclock_get_wallclock(struct pvclock_wall_clock *wc,
+ struct timespec *ts);
+
+#endif
Property changes on: trunk/sys/x86/include/pvclock.h
___________________________________________________________________
Added: svn:eol-style
## -0,0 +1 ##
+native
\ No newline at end of property
Added: svn:keywords
## -0,0 +1 ##
+MidnightBSD=%H
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+text/plain
\ No newline at end of property
Modified: trunk/sys/x86/include/reg.h
===================================================================
--- trunk/sys/x86/include/reg.h 2020-02-08 19:32:41 UTC (rev 12310)
+++ trunk/sys/x86/include/reg.h 2020-02-08 19:33:27 UTC (rev 12311)
@@ -32,7 +32,7 @@
* SUCH DAMAGE.
*
* from: @(#)reg.h 5.5 (Berkeley) 1/18/91
- * $FreeBSD: stable/10/sys/x86/include/reg.h 283910 2015-06-02 14:54:53Z jhb $
+ * $FreeBSD: stable/11/sys/x86/include/reg.h 338691 2018-09-14 23:21:52Z jhb $
*/
#ifndef _MACHINE_REG_H_
@@ -205,6 +205,14 @@
/* Index 8-15: reserved */
};
+#define DBREG_DR6_RESERVED1 0xffff0ff0
+#define DBREG_DR6_BMASK 0x000f
+#define DBREG_DR6_B(i) (1 << (i))
+#define DBREG_DR6_BD 0x2000
+#define DBREG_DR6_BS 0x4000
+#define DBREG_DR6_BT 0x8000
+
+#define DBREG_DR7_RESERVED1 0x0400
#define DBREG_DR7_LOCAL_ENABLE 0x01
#define DBREG_DR7_GLOBAL_ENABLE 0x02
#define DBREG_DR7_LEN_1 0x00 /* 1 byte length */
@@ -235,6 +243,8 @@
#undef __dbreg64
#ifdef _KERNEL
+struct thread;
+
/*
* XXX these interfaces are MI, so they should be declared in a MI place.
*/
Modified: trunk/sys/x86/include/segments.h
===================================================================
--- trunk/sys/x86/include/segments.h 2020-02-08 19:32:41 UTC (rev 12310)
+++ trunk/sys/x86/include/segments.h 2020-02-08 19:33:27 UTC (rev 12311)
@@ -32,7 +32,7 @@
* SUCH DAMAGE.
*
* from: @(#)segments.h 7.1 (Berkeley) 5/9/91
- * $FreeBSD: stable/10/sys/x86/include/segments.h 255040 2013-08-29 19:52:18Z gibbs $
+ * $FreeBSD: stable/11/sys/x86/include/segments.h 331722 2018-03-29 02:50:57Z eadler $
*/
#ifndef _X86_SEGMENTS_H_
@@ -47,11 +47,7 @@
*/
#define SEL_RPL_MASK 3 /* requester priv level */
#define ISPL(s) ((s)&3) /* priority level of a selector */
-#ifdef XEN
-#define SEL_KPL 1 /* kernel priority level */
-#else
#define SEL_KPL 0 /* kernel priority level */
-#endif
#define SEL_UPL 3 /* user priority level */
#define ISLDT(s) ((s)&SEL_LDT) /* is it local or global */
#define SEL_LDT 4 /* local descriptor table */
@@ -220,7 +216,7 @@
#define IDT_DTRACE_RET 0x92 /* DTrace pid provider Interrupt Vector */
#define IDT_EVTCHN 0x93 /* Xen HVM Event Channel Interrupt Vector */
-#if defined(__i386__) || defined(__ia64__)
+#if defined(__i386__)
/*
* Entries in the Global Descriptor Table (GDT)
* Note that each 4 entries share a single 32 byte L1 cache line.
@@ -245,11 +241,7 @@
#define GBIOSUTIL_SEL 16 /* BIOS interface (Utility) */
#define GBIOSARGS_SEL 17 /* BIOS interface (Arguments) */
#define GNDIS_SEL 18 /* For the NDIS layer */
-#ifdef XEN
-#define NGDT 9
-#else
#define NGDT 19
-#endif
/*
* Entries in the Local Descriptor Table (LDT)
@@ -265,7 +257,7 @@
#define LBSDICALLS_SEL 16 /* BSDI system call gate */
#define NLDT (LBSDICALLS_SEL + 1)
-#else /* !__i386__ && !__ia64__ */
+#else /* !__i386__ */
/*
* Entries in the Global Descriptor Table (GDT)
*/
@@ -283,6 +275,6 @@
#define GUSERLDT_SEL 11 /* LDT */
/* slot 12 is second half of GUSERLDT_SEL */
#define NGDT 13
-#endif /* __i386__ || __ia64__ */
+#endif /* __i386__ */
#endif /* !_X86_SEGMENTS_H_ */
Modified: trunk/sys/x86/include/setjmp.h
===================================================================
--- trunk/sys/x86/include/setjmp.h 2020-02-08 19:32:41 UTC (rev 12310)
+++ trunk/sys/x86/include/setjmp.h 2020-02-08 19:33:27 UTC (rev 12311)
@@ -27,7 +27,7 @@
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*
- * $FreeBSD: stable/10/sys/x86/include/setjmp.h 232275 2012-02-28 22:17:52Z tijl $
+ * $FreeBSD: stable/11/sys/x86/include/setjmp.h 331722 2018-03-29 02:50:57Z eadler $
*/
#ifndef _MACHINE_SETJMP_H_
Modified: trunk/sys/x86/include/sigframe.h
===================================================================
--- trunk/sys/x86/include/sigframe.h 2020-02-08 19:32:41 UTC (rev 12310)
+++ trunk/sys/x86/include/sigframe.h 2020-02-08 19:33:27 UTC (rev 12311)
@@ -26,7 +26,7 @@
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
- * $FreeBSD: stable/10/sys/x86/include/sigframe.h 247047 2013-02-20 17:39:52Z kib $
+ * $FreeBSD: stable/11/sys/x86/include/sigframe.h 247047 2013-02-20 17:39:52Z kib $
*/
#ifndef _X86_SIGFRAME_H_
Modified: trunk/sys/x86/include/signal.h
===================================================================
--- trunk/sys/x86/include/signal.h 2020-02-08 19:32:41 UTC (rev 12310)
+++ trunk/sys/x86/include/signal.h 2020-02-08 19:33:27 UTC (rev 12311)
@@ -29,7 +29,7 @@
* SUCH DAMAGE.
*
* @(#)signal.h 8.1 (Berkeley) 6/11/93
- * $FreeBSD: stable/10/sys/x86/include/signal.h 247047 2013-02-20 17:39:52Z kib $
+ * $FreeBSD: stable/11/sys/x86/include/signal.h 331722 2018-03-29 02:50:57Z eadler $
*/
#ifndef _X86_SIGNAL_H
Modified: trunk/sys/x86/include/specialreg.h
===================================================================
--- trunk/sys/x86/include/specialreg.h 2020-02-08 19:32:41 UTC (rev 12310)
+++ trunk/sys/x86/include/specialreg.h 2020-02-08 19:33:27 UTC (rev 12311)
@@ -28,7 +28,7 @@
* SUCH DAMAGE.
*
* from: @(#)specialreg.h 7.1 (Berkeley) 5/9/91
- * $FreeBSD: stable/10/sys/x86/include/specialreg.h 315928 2017-03-25 05:09:03Z grehan $
+ * $FreeBSD: stable/11/sys/x86/include/specialreg.h 354658 2019-11-12 19:35:46Z scottl $
*/
#ifndef _MACHINE_SPECIALREG_H_
@@ -54,6 +54,7 @@
#define CR0_CD 0x40000000 /* Cache Disable */
#define CR3_PCID_SAVE 0x8000000000000000
+#define CR3_PCID_MASK 0xfff
/*
* Bits in PPro special registers
@@ -74,6 +75,7 @@
#define CR4_PCIDE 0x00020000 /* Enable Context ID */
#define CR4_XSAVE 0x00040000 /* XSETBV/XGETBV */
#define CR4_SMEP 0x00100000 /* Supervisor-Mode Execution Prevention */
+#define CR4_SMAP 0x00200000 /* Supervisor-Mode Access Prevention */
/*
* Bits in AMD64 special registers. EFER is 64 bits wide.
@@ -322,6 +324,13 @@
#define AMDPM_CPB 0x00000200
/*
+ * AMD extended function 8000_0008h ebx info (amd_extended_feature_extensions)
+ */
+#define AMDFEID_CLZERO 0x00000001
+#define AMDFEID_IRPERF 0x00000002
+#define AMDFEID_XSAVEERPTR 0x00000004
+
+/*
* AMD extended function 8000_0008h ecx info
*/
#define AMDID_CMP_CORES 0x000000ff
@@ -348,15 +357,21 @@
#define CPUID_STDEXT_MPX 0x00004000
#define CPUID_STDEXT_PQE 0x00008000
#define CPUID_STDEXT_AVX512F 0x00010000
+#define CPUID_STDEXT_AVX512DQ 0x00020000
#define CPUID_STDEXT_RDSEED 0x00040000
#define CPUID_STDEXT_ADX 0x00080000
#define CPUID_STDEXT_SMAP 0x00100000
+#define CPUID_STDEXT_AVX512IFMA 0x00200000
+#define CPUID_STDEXT_PCOMMIT 0x00400000
#define CPUID_STDEXT_CLFLUSHOPT 0x00800000
+#define CPUID_STDEXT_CLWB 0x01000000
#define CPUID_STDEXT_PROCTRACE 0x02000000
#define CPUID_STDEXT_AVX512PF 0x04000000
#define CPUID_STDEXT_AVX512ER 0x08000000
#define CPUID_STDEXT_AVX512CD 0x10000000
#define CPUID_STDEXT_SHA 0x20000000
+#define CPUID_STDEXT_AVX512BW 0x40000000
+#define CPUID_STDEXT_AVX512VL 0x80000000
/*
* CPUID instruction 7 Structured Extended Features, leaf 0 ecx info
@@ -365,10 +380,42 @@
#define CPUID_STDEXT2_UMIP 0x00000004
#define CPUID_STDEXT2_PKU 0x00000008
#define CPUID_STDEXT2_OSPKE 0x00000010
+#define CPUID_STDEXT2_WAITPKG 0x00000020
+#define CPUID_STDEXT2_GFNI 0x00000100
#define CPUID_STDEXT2_RDPID 0x00400000
+#define CPUID_STDEXT2_CLDEMOTE 0x02000000
+#define CPUID_STDEXT2_MOVDIRI 0x08000000
+#define CPUID_STDEXT2_MOVDIRI64B 0x10000000
#define CPUID_STDEXT2_SGXLC 0x40000000
/*
+ * CPUID instruction 7 Structured Extended Features, leaf 0 edx info
+ */
+#define CPUID_STDEXT3_MD_CLEAR 0x00000400
+#define CPUID_STDEXT3_TSXFA 0x00002000
+#define CPUID_STDEXT3_IBPB 0x04000000
+#define CPUID_STDEXT3_STIBP 0x08000000
+#define CPUID_STDEXT3_L1D_FLUSH 0x10000000
+#define CPUID_STDEXT3_ARCH_CAP 0x20000000
+#define CPUID_STDEXT3_CORE_CAP 0x40000000
+#define CPUID_STDEXT3_SSBD 0x80000000
+
+/* MSR IA32_ARCH_CAP(ABILITIES) bits */
+#define IA32_ARCH_CAP_RDCL_NO 0x00000001
+#define IA32_ARCH_CAP_IBRS_ALL 0x00000002
+#define IA32_ARCH_CAP_RSBA 0x00000004
+#define IA32_ARCH_CAP_SKIP_L1DFL_VMENTRY 0x00000008
+#define IA32_ARCH_CAP_SSB_NO 0x00000010
+#define IA32_ARCH_CAP_MDS_NO 0x00000020
+#define IA32_ARCH_CAP_IF_PSCHANGE_MC_NO 0x00000040
+#define IA32_ARCH_CAP_TSX_CTRL 0x00000080
+#define IA32_ARCH_CAP_TAA_NO 0x00000100
+
+/* MSR IA32_TSX_CTRL bits */
+#define IA32_TSX_CTRL_RTM_DISABLE 0x00000001
+#define IA32_TSX_CTRL_TSX_CPUID_CLEAR 0x00000002
+
+/*
* CPUID manufacturers identifiers
*/
#define AMD_VENDOR_ID "AuthenticAMD"
@@ -396,6 +443,8 @@
#define MSR_EBL_CR_POWERON 0x02a
#define MSR_TEST_CTL 0x033
#define MSR_IA32_FEATURE_CONTROL 0x03a
+#define MSR_IA32_SPEC_CTRL 0x048
+#define MSR_IA32_PRED_CMD 0x049
#define MSR_BIOS_UPDT_TRIG 0x079
#define MSR_BBL_CR_D0 0x088
#define MSR_BBL_CR_D1 0x089
@@ -408,6 +457,9 @@
#define MSR_APERF 0x0e8
#define MSR_IA32_EXT_CONFIG 0x0ee /* Undocumented. Core Solo/Duo only */
#define MSR_MTRRcap 0x0fe
+#define MSR_IA32_ARCH_CAP 0x10a
+#define MSR_IA32_FLUSH_CMD 0x10b
+#define MSR_TSX_FORCE_ABORT 0x10f
#define MSR_BBL_CR_ADDR 0x116
#define MSR_BBL_CR_DECC 0x118
#define MSR_BBL_CR_CTL 0x119
@@ -414,6 +466,7 @@
#define MSR_BBL_CR_TRIG 0x11a
#define MSR_BBL_CR_BUSY 0x11b
#define MSR_BBL_CR_CTL3 0x11e
+#define MSR_IA32_TSX_CTRL 0x122
#define MSR_SYSENTER_CS_MSR 0x174
#define MSR_SYSENTER_ESP_MSR 0x175
#define MSR_SYSENTER_EIP_MSR 0x176
@@ -467,6 +520,7 @@
#define MSR_DRAM_ENERGY_STATUS 0x619
#define MSR_PP0_ENERGY_STATUS 0x639
#define MSR_PP1_ENERGY_STATUS 0x641
+#define MSR_TSC_DEADLINE 0x6e0 /* Writes are not serializing */
/*
* VMX MSRs
@@ -488,8 +542,10 @@
#define MSR_VMX_TRUE_ENTRY_CTLS 0x490
/*
- * X2APIC MSRs
+ * X2APIC MSRs.
+ * Writes are not serializing.
*/
+#define MSR_APIC_000 0x800
#define MSR_APIC_ID 0x802
#define MSR_APIC_VERSION 0x803
#define MSR_APIC_TPR 0x808
@@ -548,6 +604,21 @@
#define IA32_MISC_EN_XDD 0x0000000400000000ULL
/*
+ * IA32_SPEC_CTRL and IA32_PRED_CMD MSRs are described in the Intel'
+ * document 336996-001 Speculative Execution Side Channel Mitigations.
+ */
+/* MSR IA32_SPEC_CTRL */
+#define IA32_SPEC_CTRL_IBRS 0x00000001
+#define IA32_SPEC_CTRL_STIBP 0x00000002
+#define IA32_SPEC_CTRL_SSBD 0x00000004
+
+/* MSR IA32_PRED_CMD */
+#define IA32_PRED_CMD_IBPB_BARRIER 0x0000000000000001ULL
+
+/* MSR IA32_FLUSH_CMD */
+#define IA32_FLUSH_CMD_L1D 0x00000001
+
+/*
* PAT modes.
*/
#define PAT_UNCACHEABLE 0x00
@@ -697,6 +768,22 @@
#define MC_MISC_ADDRESS_MODE 0x00000000000001c0 /* If MCG_CAP_SER_P */
#define MC_CTL2_THRESHOLD 0x0000000000007fff
#define MC_CTL2_CMCI_EN 0x0000000040000000
+#define MC_AMDNB_BANK 4
+#define MC_MISC_AMDNB_VAL 0x8000000000000000 /* Counter presence valid */
+#define MC_MISC_AMDNB_CNTP 0x4000000000000000 /* Counter present */
+#define MC_MISC_AMDNB_LOCK 0x2000000000000000 /* Register locked */
+#define MC_MISC_AMDNB_LVT_MASK 0x00f0000000000000 /* Extended LVT offset */
+#define MC_MISC_AMDNB_LVT_SHIFT 52
+#define MC_MISC_AMDNB_CNTEN 0x0008000000000000 /* Counter enabled */
+#define MC_MISC_AMDNB_INT_MASK 0x0006000000000000 /* Interrupt type */
+#define MC_MISC_AMDNB_INT_LVT 0x0002000000000000 /* Interrupt via Extended LVT */
+#define MC_MISC_AMDNB_INT_SMI 0x0004000000000000 /* SMI */
+#define MC_MISC_AMDNB_OVERFLOW 0x0001000000000000 /* Counter overflow */
+#define MC_MISC_AMDNB_CNT_MASK 0x00000fff00000000 /* Counter value */
+#define MC_MISC_AMDNB_CNT_SHIFT 32
+#define MC_MISC_AMDNB_CNT_MAX 0xfff
+#define MC_MISC_AMDNB_PTR_MASK 0x00000000ff000000 /* Pointer to additional registers */
+#define MC_MISC_AMDNB_PTR_SHIFT 24
/*
* The following four 3-byte registers control the non-cacheable regions.
@@ -800,6 +887,7 @@
#define MSR_FSBASE 0xc0000100 /* base address of the %fs "segment" */
#define MSR_GSBASE 0xc0000101 /* base address of the %gs "segment" */
#define MSR_KGSBASE 0xc0000102 /* base address of the kernel %gs */
+#define MSR_TSC_AUX 0xc0000103
#define MSR_PERFEVSEL0 0xc0010000
#define MSR_PERFEVSEL1 0xc0010001
#define MSR_PERFEVSEL2 0xc0010002
@@ -817,6 +905,8 @@
#define MSR_TOP_MEM 0xc001001a /* boundary for ram below 4G */
#define MSR_TOP_MEM2 0xc001001d /* boundary for ram above 4G */
#define MSR_NB_CFG1 0xc001001f /* NB configuration 1 */
+#define MSR_K8_UCODE_UPDATE 0xc0010020 /* update microcode */
+#define MSR_MC0_CTL_MASK 0xc0010044
#define MSR_P_STATE_LIMIT 0xc0010061 /* P-state Current Limit Register */
#define MSR_P_STATE_CONTROL 0xc0010062 /* P-state Control Register */
#define MSR_P_STATE_STATUS 0xc0010063 /* P-state Status Register */
@@ -823,12 +913,12 @@
#define MSR_P_STATE_CONFIG(n) (0xc0010064 + (n)) /* P-state Config */
#define MSR_SMM_ADDR 0xc0010112 /* SMM TSEG base address */
#define MSR_SMM_MASK 0xc0010113 /* SMM TSEG address mask */
+#define MSR_VM_CR 0xc0010114 /* SVM: feature control */
+#define MSR_VM_HSAVE_PA 0xc0010117 /* SVM: host save area address */
+#define MSR_AMD_CPUID07 0xc0011002 /* CPUID 07 %ebx override */
#define MSR_EXTFEATURES 0xc0011005 /* Extended CPUID Features override */
+#define MSR_LS_CFG 0xc0011020
#define MSR_IC_CFG 0xc0011021 /* Instruction Cache Configuration */
-#define MSR_K8_UCODE_UPDATE 0xc0010020 /* update microcode */
-#define MSR_MC0_CTL_MASK 0xc0010044
-#define MSR_VM_CR 0xc0010114 /* SVM: feature control */
-#define MSR_VM_HSAVE_PA 0xc0010117 /* SVM: host save area address */
/* MSR_VM_CR related */
#define VM_CR_SVMDIS 0x10 /* SVM: disabled by BIOS */
Added: trunk/sys/x86/include/stack.h
===================================================================
--- trunk/sys/x86/include/stack.h (rev 0)
+++ trunk/sys/x86/include/stack.h 2020-02-08 19:33:27 UTC (rev 12311)
@@ -0,0 +1,62 @@
+/* $MidnightBSD$ */
+/*-
+ * Mach Operating System
+ * Copyright (c) 1991,1990 Carnegie Mellon University
+ * All Rights Reserved.
+ *
+ * Permission to use, copy, modify and distribute this software and its
+ * documentation is hereby granted, provided that both the copyright
+ * notice and this permission notice appear in all copies of the
+ * software, derivative works or modified versions, and any portions
+ * thereof, and that both notices appear in supporting documentation.
+ *
+ * CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS
+ * CONDITION. CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND FOR
+ * ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE.
+ *
+ * Carnegie Mellon requests users of this software to return to
+ *
+ * Software Distribution Coordinator or Software.Distribution at CS.CMU.EDU
+ * School of Computer Science
+ * Carnegie Mellon University
+ * Pittsburgh PA 15213-3890
+ *
+ * any improvements or extensions that they make and grant Carnegie the
+ * rights to redistribute these changes.
+ *
+ * $FreeBSD: stable/11/sys/x86/include/stack.h 287645 2015-09-11 03:54:37Z markj $
+ */
+
+#ifndef _X86_STACK_H
+#define _X86_STACK_H
+
+/*
+ * Stack trace.
+ */
+
+#ifdef __i386__
+struct i386_frame {
+ struct i386_frame *f_frame;
+ u_int f_retaddr;
+ u_int f_arg0;
+};
+#endif
+
+#ifdef __amd64__
+struct amd64_frame {
+ struct amd64_frame *f_frame;
+ u_long f_retaddr;
+};
+
+struct i386_frame {
+ uint32_t f_frame;
+ uint32_t f_retaddr;
+ uint32_t f_arg0;
+};
+#endif /* __amd64__ */
+
+#ifdef _KERNEL
+int stack_nmi_handler(struct trapframe *);
+#endif
+
+#endif /* !_X86_STACK_H */
Property changes on: trunk/sys/x86/include/stack.h
___________________________________________________________________
Added: svn:eol-style
## -0,0 +1 ##
+native
\ No newline at end of property
Added: svn:keywords
## -0,0 +1 ##
+MidnightBSD=%H
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+text/plain
\ No newline at end of property
Modified: trunk/sys/x86/include/stdarg.h
===================================================================
--- trunk/sys/x86/include/stdarg.h 2020-02-08 19:32:41 UTC (rev 12310)
+++ trunk/sys/x86/include/stdarg.h 2020-02-08 19:33:27 UTC (rev 12311)
@@ -26,7 +26,7 @@
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*
- * $FreeBSD: stable/10/sys/x86/include/stdarg.h 256105 2013-10-07 10:01:23Z phk $
+ * $FreeBSD: stable/11/sys/x86/include/stdarg.h 331722 2018-03-29 02:50:57Z eadler $
*/
#ifndef _MACHINE_STDARG_H_
Modified: trunk/sys/x86/include/sysarch.h
===================================================================
--- trunk/sys/x86/include/sysarch.h 2020-02-08 19:32:41 UTC (rev 12310)
+++ trunk/sys/x86/include/sysarch.h 2020-02-08 19:33:27 UTC (rev 12311)
@@ -27,7 +27,7 @@
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*
- * $FreeBSD: stable/10/sys/x86/include/sysarch.h 233209 2012-03-19 21:57:31Z tijl $
+ * $FreeBSD: stable/11/sys/x86/include/sysarch.h 331722 2018-03-29 02:50:57Z eadler $
*/
/*
Modified: trunk/sys/x86/include/trap.h
===================================================================
--- trunk/sys/x86/include/trap.h 2020-02-08 19:32:41 UTC (rev 12310)
+++ trunk/sys/x86/include/trap.h 2020-02-08 19:33:27 UTC (rev 12311)
@@ -31,7 +31,7 @@
* SUCH DAMAGE.
*
* from: @(#)trap.h 5.4 (Berkeley) 5/9/91
- * $FreeBSD: stable/10/sys/x86/include/trap.h 262042 2014-02-17 12:57:13Z avg $
+ * $FreeBSD: stable/11/sys/x86/include/trap.h 331722 2018-03-29 02:50:57Z eadler $
*/
#ifndef _MACHINE_TRAP_H_
Added: trunk/sys/x86/include/ucode.h
===================================================================
--- trunk/sys/x86/include/ucode.h (rev 0)
+++ trunk/sys/x86/include/ucode.h 2020-02-08 19:33:27 UTC (rev 12311)
@@ -0,0 +1,69 @@
+/* $MidnightBSD$ */
+/*-
+ * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
+ *
+ * Copyright (c) 2018 The FreeBSD Foundation
+ *
+ * This software was developed by Mark Johnston under sponsorship from
+ * the FreeBSD Foundation.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ * $FreeBSD: stable/11/sys/x86/include/ucode.h 347700 2019-05-16 14:42:16Z markj $
+ */
+
+#ifndef _MACHINE_UCODE_H_
+#define _MACHINE_UCODE_H_
+
+struct ucode_intel_header {
+ uint32_t header_version;
+ int32_t update_revision;
+ uint32_t dat;
+ uint32_t processor_signature;
+ uint32_t checksum;
+ uint32_t loader_revision;
+ uint32_t processor_flags;
+#define UCODE_INTEL_DEFAULT_DATA_SIZE 2000
+ uint32_t data_size;
+ uint32_t total_size;
+ uint32_t reserved[3];
+};
+
+struct ucode_intel_extsig_table {
+ uint32_t signature_count;
+ uint32_t signature_table_checksum;
+ uint32_t reserved[3];
+ struct ucode_intel_extsig {
+ uint32_t processor_signature;
+ uint32_t processor_flags;
+ uint32_t checksum;
+ } entries[0];
+};
+
+int ucode_intel_load(void *data, bool unsafe,
+ uint64_t *nrevp, uint64_t *orevp);
+size_t ucode_load_bsp(uintptr_t free);
+void ucode_load_ap(int cpu);
+void ucode_reload(void);
+void * ucode_update(void *data);
+
+#endif /* _MACHINE_UCODE_H_ */
Property changes on: trunk/sys/x86/include/ucode.h
___________________________________________________________________
Added: svn:eol-style
## -0,0 +1 ##
+native
\ No newline at end of property
Added: svn:keywords
## -0,0 +1 ##
+MidnightBSD=%H
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+text/plain
\ No newline at end of property
Modified: trunk/sys/x86/include/ucontext.h
===================================================================
--- trunk/sys/x86/include/ucontext.h 2020-02-08 19:32:41 UTC (rev 12310)
+++ trunk/sys/x86/include/ucontext.h 2020-02-08 19:33:27 UTC (rev 12311)
@@ -27,7 +27,7 @@
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
- * $FreeBSD: stable/10/sys/x86/include/ucontext.h 247047 2013-02-20 17:39:52Z kib $
+ * $FreeBSD: stable/11/sys/x86/include/ucontext.h 295561 2016-02-12 07:38:19Z kib $
*/
#ifndef _X86_UCONTEXT_H_
@@ -163,4 +163,9 @@
} mcontext_t;
#endif /* __amd64__ */
+#ifdef __LINT__
+typedef struct __mcontext {
+} mcontext_t;
+#endif /* __LINT__ */
+
#endif /* !_X86_UCONTEXT_H_ */
Modified: trunk/sys/x86/include/vdso.h
===================================================================
--- trunk/sys/x86/include/vdso.h 2020-02-08 19:32:41 UTC (rev 12310)
+++ trunk/sys/x86/include/vdso.h 2020-02-08 19:33:27 UTC (rev 12311)
@@ -1,8 +1,12 @@
/* $MidnightBSD$ */
/*-
* Copyright 2012 Konstantin Belousov <kib at FreeBSD.ORG>.
+ * Copyright 2016 The FreeBSD Foundation.
* All rights reserved.
*
+ * Portions of this software were developed by Konstantin Belousov
+ * under sponsorship from the FreeBSD Foundation.
+ *
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
@@ -23,7 +27,7 @@
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
- * $FreeBSD: stable/10/sys/x86/include/vdso.h 237433 2012-06-22 07:06:40Z kib $
+ * $FreeBSD: stable/11/sys/x86/include/vdso.h 311376 2017-01-05 07:42:08Z sephe $
*/
#ifndef _X86_VDSO_H
@@ -31,8 +35,13 @@
#define VDSO_TIMEHANDS_MD \
uint32_t th_x86_shift; \
- uint32_t th_res[7];
+ uint32_t th_x86_hpet_idx; \
+ uint32_t th_res[6];
+#define VDSO_TH_ALGO_X86_TSC VDSO_TH_ALGO_1
+#define VDSO_TH_ALGO_X86_HPET VDSO_TH_ALGO_2
+#define VDSO_TH_ALGO_X86_HVTSC VDSO_TH_ALGO_3 /* Hyper-V ref. TSC */
+
#ifdef _KERNEL
#ifdef COMPAT_FREEBSD32
Modified: trunk/sys/x86/include/vmware.h
===================================================================
--- trunk/sys/x86/include/vmware.h 2020-02-08 19:32:41 UTC (rev 12310)
+++ trunk/sys/x86/include/vmware.h 2020-02-08 19:33:27 UTC (rev 12311)
@@ -24,7 +24,7 @@
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*
- * $FreeBSD: stable/10/sys/x86/include/vmware.h 278522 2015-02-10 16:34:42Z jhb $
+ * $FreeBSD: stable/11/sys/x86/include/vmware.h 278749 2015-02-14 09:00:12Z kib $
*/
#ifndef _X86_VMWARE_H_
@@ -32,9 +32,14 @@
#define VMW_HVMAGIC 0x564d5868
#define VMW_HVPORT 0x5658
+
#define VMW_HVCMD_GETVERSION 10
#define VMW_HVCMD_GETHZ 45
+#define VMW_HVCMD_GETVCPU_INFO 68
+#define VMW_VCPUINFO_LEGACY_X2APIC (1 << 3)
+#define VMW_VCPUINFO_VCPU_RESERVED (1 << 31)
+
static __inline void
vmware_hvcall(u_int cmd, u_int *p)
{
Added: trunk/sys/x86/include/x86_smp.h
===================================================================
--- trunk/sys/x86/include/x86_smp.h (rev 0)
+++ trunk/sys/x86/include/x86_smp.h 2020-02-08 19:33:27 UTC (rev 12311)
@@ -0,0 +1,108 @@
+/* $MidnightBSD$ */
+/*-
+ * ----------------------------------------------------------------------------
+ * "THE BEER-WARE LICENSE" (Revision 42):
+ * <phk at FreeBSD.org> wrote this file. As long as you retain this notice you
+ * can do whatever you want with this stuff. If we meet some day, and you think
+ * this stuff is worth it, you can buy me a beer in return. Poul-Henning Kamp
+ * ----------------------------------------------------------------------------
+ *
+ * $FreeBSD: stable/11/sys/x86/include/x86_smp.h 329462 2018-02-17 18:00:01Z kib $
+ *
+ */
+
+#ifndef _X86_X86_SMP_H_
+#define _X86_X86_SMP_H_
+
+#include <sys/bus.h>
+#include <machine/frame.h>
+#include <machine/intr_machdep.h>
+#include <x86/apicvar.h>
+#include <machine/pcb.h>
+
+struct pmap;
+
+/* global data in mp_x86.c */
+extern int mp_naps;
+extern int boot_cpu_id;
+extern struct pcb stoppcbs[];
+extern int cpu_apic_ids[];
+extern int bootAP;
+extern void *dpcpu;
+extern char *bootSTK;
+extern void *bootstacks[];
+extern volatile u_int cpu_ipi_pending[];
+extern volatile int aps_ready;
+extern struct mtx ap_boot_mtx;
+extern int cpu_logical;
+extern int cpu_cores;
+extern volatile uint32_t smp_tlb_generation;
+extern struct pmap *smp_tlb_pmap;
+extern vm_offset_t smp_tlb_addr1, smp_tlb_addr2;
+extern u_int xhits_gbl[];
+extern u_int xhits_pg[];
+extern u_int xhits_rng[];
+extern u_int ipi_global;
+extern u_int ipi_page;
+extern u_int ipi_range;
+extern u_int ipi_range_size;
+
+extern int nmi_kdb_lock;
+extern int nmi_is_broadcast;
+
+struct cpu_info {
+ int cpu_present:1;
+ int cpu_bsp:1;
+ int cpu_disabled:1;
+ int cpu_hyperthread:1;
+};
+extern struct cpu_info cpu_info[];
+
+#ifdef COUNT_IPIS
+extern u_long *ipi_invltlb_counts[MAXCPU];
+extern u_long *ipi_invlrng_counts[MAXCPU];
+extern u_long *ipi_invlpg_counts[MAXCPU];
+extern u_long *ipi_invlcache_counts[MAXCPU];
+extern u_long *ipi_rendezvous_counts[MAXCPU];
+#endif
+
+/* IPI handlers */
+inthand_t
+ IDTVEC(invltlb), /* TLB shootdowns - global */
+ IDTVEC(invlpg), /* TLB shootdowns - 1 page */
+ IDTVEC(invlrng), /* TLB shootdowns - page range */
+ IDTVEC(invlcache), /* Write back and invalidate cache */
+ IDTVEC(ipi_intr_bitmap_handler), /* Bitmap based IPIs */
+ IDTVEC(cpustop), /* CPU stops & waits to be restarted */
+ IDTVEC(cpususpend), /* CPU suspends & waits to be resumed */
+ IDTVEC(rendezvous); /* handle CPU rendezvous */
+
+/* functions in x86_mp.c */
+void assign_cpu_ids(void);
+void cpu_add(u_int apic_id, char boot_cpu);
+void cpustop_handler(void);
+void cpususpend_handler(void);
+void init_secondary_tail(void);
+void invltlb_handler(void);
+void invlpg_handler(void);
+void invlrng_handler(void);
+void invlcache_handler(void);
+void init_secondary(void);
+void ipi_startup(int apic_id, int vector);
+void ipi_all_but_self(u_int ipi);
+void ipi_bitmap_handler(struct trapframe frame);
+void ipi_cpu(int cpu, u_int ipi);
+int ipi_nmi_handler(void);
+void ipi_selected(cpuset_t cpus, u_int ipi);
+u_int mp_bootaddress(u_int);
+void set_interrupt_apic_ids(void);
+void smp_cache_flush(void);
+void smp_masked_invlpg(cpuset_t mask, vm_offset_t addr, struct pmap *pmap);
+void smp_masked_invlpg_range(cpuset_t mask, vm_offset_t startva,
+ vm_offset_t endva, struct pmap *pmap);
+void smp_masked_invltlb(cpuset_t mask, struct pmap *pmap);
+void mem_range_AP_init(void);
+void topo_probe(void);
+void ipi_send_cpu(int cpu, u_int ipi);
+
+#endif
Property changes on: trunk/sys/x86/include/x86_smp.h
___________________________________________________________________
Added: svn:eol-style
## -0,0 +1 ##
+native
\ No newline at end of property
Added: svn:keywords
## -0,0 +1 ##
+MidnightBSD=%H
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## -0,0 +1 ##
+text/plain
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Added: trunk/sys/x86/include/x86_var.h
===================================================================
--- trunk/sys/x86/include/x86_var.h (rev 0)
+++ trunk/sys/x86/include/x86_var.h 2020-02-08 19:33:27 UTC (rev 12311)
@@ -0,0 +1,161 @@
+/* $MidnightBSD$ */
+/*-
+ * Copyright (c) 1995 Bruce D. Evans.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * 3. Neither the name of the author nor the names of contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ * $FreeBSD: stable/11/sys/x86/include/x86_var.h 355094 2019-11-25 16:46:41Z kib $
+ */
+
+#ifndef _X86_X86_VAR_H_
+#define _X86_X86_VAR_H_
+
+/*
+ * Miscellaneous machine-dependent declarations.
+ */
+
+extern long Maxmem;
+extern u_int basemem;
+extern int busdma_swi_pending;
+extern u_int cpu_exthigh;
+extern u_int cpu_feature;
+extern u_int cpu_feature2;
+extern u_int amd_feature;
+extern u_int amd_feature2;
+extern u_int amd_pminfo;
+extern u_int amd_extended_feature_extensions;
+extern u_int via_feature_rng;
+extern u_int via_feature_xcrypt;
+extern u_int cpu_clflush_line_size;
+extern u_int cpu_stdext_feature;
+extern u_int cpu_stdext_feature2;
+extern u_int cpu_stdext_feature3;
+extern uint64_t cpu_ia32_arch_caps;
+extern u_int cpu_fxsr;
+extern u_int cpu_high;
+extern u_int cpu_id;
+extern u_int cpu_max_ext_state_size;
+extern u_int cpu_mxcsr_mask;
+extern u_int cpu_procinfo;
+extern u_int cpu_procinfo2;
+extern char cpu_vendor[];
+extern u_int cpu_vendor_id;
+extern u_int cpu_mon_mwait_flags;
+extern u_int cpu_mon_min_size;
+extern u_int cpu_mon_max_size;
+extern u_int cpu_maxphyaddr;
+extern char ctx_switch_xsave[];
+extern u_int hv_high;
+extern char hv_vendor[];
+extern char kstack[];
+extern char sigcode[];
+extern int szsigcode;
+extern int vm_page_dump_size;
+extern int workaround_erratum383;
+extern int _udatasel;
+extern int _ucodesel;
+extern int _ucode32sel;
+extern int _ufssel;
+extern int _ugssel;
+extern int use_xsave;
+extern uint64_t xsave_mask;
+extern int pti;
+extern int hw_ibrs_active;
+extern int hw_mds_disable;
+extern int hw_ssb_active;
+extern int x86_taa_enable;
+
+struct pcb;
+struct thread;
+struct reg;
+struct fpreg;
+struct dbreg;
+struct dumperinfo;
+struct trapframe;
+
+/*
+ * The interface type of the interrupt handler entry point cannot be
+ * expressed in C. Use simplest non-variadic function type as an
+ * approximation.
+ */
+typedef void alias_for_inthand_t(void);
+
+/*
+ * Returns the maximum physical address that can be used with the
+ * current system.
+ */
+static __inline vm_paddr_t
+cpu_getmaxphyaddr(void)
+{
+#if defined(__i386__) && !defined(PAE)
+ return (0xffffffff);
+#else
+ return ((1ULL << cpu_maxphyaddr) - 1);
+#endif
+}
+
+void *alloc_fpusave(int flags);
+void busdma_swi(void);
+bool cpu_mwait_usable(void);
+void cpu_probe_amdc1e(void);
+void cpu_setregs(void);
+void dump_add_page(vm_paddr_t);
+void dump_drop_page(vm_paddr_t);
+void finishidentcpu(void);
+void identify_cpu1(void);
+void identify_cpu2(void);
+void identify_hypervisor(void);
+void initializecpu(void);
+void initializecpucache(void);
+bool fix_cpuid(void);
+void fillw(int /*u_short*/ pat, void *base, size_t cnt);
+int is_physical_memory(vm_paddr_t addr);
+int isa_nmi(int cd);
+void handle_ibrs_entry(void);
+void handle_ibrs_exit(void);
+void hw_ibrs_recalculate(void);
+void hw_mds_recalculate(void);
+void hw_ssb_recalculate(bool all_cpus);
+void x86_taa_recalculate(void);
+void nmi_call_kdb(u_int cpu, u_int type, struct trapframe *frame);
+void nmi_call_kdb_smp(u_int type, struct trapframe *frame);
+void nmi_handle_intr(u_int type, struct trapframe *frame);
+void pagecopy(void *from, void *to);
+void printcpuinfo(void);
+int pti_get_default(void);
+int user_dbreg_trap(register_t dr6);
+int minidumpsys(struct dumperinfo *);
+struct pcb *get_pcb_td(struct thread *td);
+
+#define MSR_OP_ANDNOT 0x00000001
+#define MSR_OP_OR 0x00000002
+#define MSR_OP_WRITE 0x00000003
+#define MSR_OP_LOCAL 0x10000000
+#define MSR_OP_SCHED 0x20000000
+#define MSR_OP_RENDEZVOUS 0x30000000
+void x86_msr_op(u_int msr, u_int op, uint64_t arg1);
+
+#endif
Property changes on: trunk/sys/x86/include/x86_var.h
___________________________________________________________________
Added: svn:eol-style
## -0,0 +1 ##
+native
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## -0,0 +1 ##
+MidnightBSD=%H
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## -0,0 +1 ##
+text/plain
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Added: trunk/sys/x86/include/xen/xen-os.h
===================================================================
--- trunk/sys/x86/include/xen/xen-os.h (rev 0)
+++ trunk/sys/x86/include/xen/xen-os.h 2020-02-08 19:33:27 UTC (rev 12311)
@@ -0,0 +1,39 @@
+/* $MidnightBSD$ */
+/*****************************************************************************
+ * x86/xen/xen-os.h
+ *
+ * Random collection of macros and definition
+ *
+ * Copyright (c) 2003, 2004 Keir Fraser (on behalf of the Xen team)
+ * All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to
+ * deal in the Software without restriction, including without limitation the
+ * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ *
+ * $FreeBSD: stable/11/sys/x86/include/xen/xen-os.h 289686 2015-10-21 10:44:07Z royger $
+ */
+
+#ifndef _MACHINE_X86_XEN_XEN_OS_H_
+#define _MACHINE_X86_XEN_XEN_OS_H_
+
+/* Everything below this point is not included by assembler (.S) files. */
+#ifndef __ASSEMBLY__
+
+#endif /* !__ASSEMBLY__ */
+
+#endif /* _MACHINE_X86_XEN_XEN_OS_H_ */
Property changes on: trunk/sys/x86/include/xen/xen-os.h
___________________________________________________________________
Added: svn:eol-style
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Added: svn:mime-type
## -0,0 +1 ##
+text/plain
\ No newline at end of property
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