[Midnightbsd-cvs] src [12393] trunk/sys/sys/gpio.h: Sync with FreeBSD 11-stable
laffer1 at midnightbsd.org
laffer1 at midnightbsd.org
Sun Feb 16 17:48:42 EST 2020
Revision: 12393
http://svnweb.midnightbsd.org/src/?rev=12393
Author: laffer1
Date: 2020-02-16 17:48:41 -0500 (Sun, 16 Feb 2020)
Log Message:
-----------
Sync with FreeBSD 11-stable
Modified Paths:
--------------
trunk/sys/sys/gpio.h
Modified: trunk/sys/sys/gpio.h
===================================================================
--- trunk/sys/sys/gpio.h 2020-02-16 22:47:19 UTC (rev 12392)
+++ trunk/sys/sys/gpio.h 2020-02-16 22:48:41 UTC (rev 12393)
@@ -27,7 +27,7 @@
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*
- * $FreeBSD: stable/10/sys/sys/gpio.h 213237 2010-09-28 03:24:53Z gonzo $
+ * $FreeBSD: stable/11/sys/sys/gpio.h 331722 2018-03-29 02:50:57Z eadler $
*
*/
@@ -61,16 +61,28 @@
#define GPIOMAXNAME 64
/* GPIO pin configuration flags */
-#define GPIO_PIN_INPUT 0x0001 /* input direction */
-#define GPIO_PIN_OUTPUT 0x0002 /* output direction */
-#define GPIO_PIN_OPENDRAIN 0x0004 /* open-drain output */
-#define GPIO_PIN_PUSHPULL 0x0008 /* push-pull output */
-#define GPIO_PIN_TRISTATE 0x0010 /* output disabled */
-#define GPIO_PIN_PULLUP 0x0020 /* internal pull-up enabled */
-#define GPIO_PIN_PULLDOWN 0x0040 /* internal pull-down enabled */
-#define GPIO_PIN_INVIN 0x0080 /* invert input */
-#define GPIO_PIN_INVOUT 0x0100 /* invert output */
-#define GPIO_PIN_PULSATE 0x0200 /* pulsate in hardware */
+#define GPIO_PIN_INPUT 0x00000001 /* input direction */
+#define GPIO_PIN_OUTPUT 0x00000002 /* output direction */
+#define GPIO_PIN_OPENDRAIN 0x00000004 /* open-drain output */
+#define GPIO_PIN_PUSHPULL 0x00000008 /* push-pull output */
+#define GPIO_PIN_TRISTATE 0x00000010 /* output disabled */
+#define GPIO_PIN_PULLUP 0x00000020 /* internal pull-up enabled */
+#define GPIO_PIN_PULLDOWN 0x00000040 /* internal pull-down enabled */
+#define GPIO_PIN_INVIN 0x00000080 /* invert input */
+#define GPIO_PIN_INVOUT 0x00000100 /* invert output */
+#define GPIO_PIN_PULSATE 0x00000200 /* pulsate in hardware */
+#define GPIO_PIN_PRESET_LOW 0x00000400 /* preset pin to high or */
+#define GPIO_PIN_PRESET_HIGH 0x00000800 /* low before enabling output */
+/* GPIO interrupt capabilities */
+#define GPIO_INTR_NONE 0x00000000 /* no interrupt support */
+#define GPIO_INTR_LEVEL_LOW 0x00010000 /* level trigger, low */
+#define GPIO_INTR_LEVEL_HIGH 0x00020000 /* level trigger, high */
+#define GPIO_INTR_EDGE_RISING 0x00040000 /* edge trigger, rising */
+#define GPIO_INTR_EDGE_FALLING 0x00080000 /* edge trigger, falling */
+#define GPIO_INTR_EDGE_BOTH 0x00100000 /* edge trigger, both */
+#define GPIO_INTR_MASK (GPIO_INTR_LEVEL_LOW | GPIO_INTR_LEVEL_HIGH | \
+ GPIO_INTR_EDGE_RISING | \
+ GPIO_INTR_EDGE_FALLING | GPIO_INTR_EDGE_BOTH)
struct gpio_pin {
uint32_t gp_pin; /* pin number */
@@ -86,6 +98,71 @@
};
/*
+ * gpio_access_32 / GPIOACCESS32
+ *
+ * Simultaneously read and/or change up to 32 adjacent pins.
+ * If the device cannot change the pins simultaneously, returns EOPNOTSUPP.
+ *
+ * This accesses an adjacent set of up to 32 pins starting at first_pin within
+ * the device's collection of pins. How the hardware pins are mapped to the 32
+ * bits in the arguments is device-specific. It is expected that lower-numbered
+ * pins in the device's number space map linearly to lower-ordered bits within
+ * the 32-bit words (i.e., bit 0 is first_pin, bit 1 is first_pin+1, etc).
+ * Other mappings are possible; know your device.
+ *
+ * Some devices may limit the value of first_pin to 0, or to multiples of 16 or
+ * 32 or some other hardware-specific number; to access pin 2 would require
+ * first_pin to be zero and then manipulate bit (1 << 2) in the 32-bit word.
+ * Invalid values in first_pin result in an EINVAL error return.
+ *
+ * The starting state of the pins is captured and stored in orig_pins, then the
+ * pins are set to ((starting_state & ~clear_pins) ^ change_pins).
+ *
+ * Clear Change Hardware pin after call
+ * 0 0 No change
+ * 0 1 Opposite of current value
+ * 1 0 Cleared
+ * 1 1 Set
+ */
+struct gpio_access_32 {
+ uint32_t first_pin; /* First pin in group of 32 adjacent */
+ uint32_t clear_pins; /* Pins are changed using: */
+ uint32_t change_pins; /* ((hwstate & ~clear_pins) ^ change_pins) */
+ uint32_t orig_pins; /* Returned hwstate of pins before change. */
+};
+
+/*
+ * gpio_config_32 / GPIOCONFIG32
+ *
+ * Simultaneously configure up to 32 adjacent pins. This is intended to change
+ * the configuration of all the pins simultaneously, such that pins configured
+ * for output all begin to drive the configured values simultaneously, but not
+ * all hardware can do that, so the driver "does the best it can" in this
+ * regard. Notably unlike pin_access_32(), this does NOT fail if the pins
+ * cannot be atomically configured; it is expected that callers understand the
+ * hardware and have decided to live with any such limitations it may have.
+ *
+ * The pin_flags argument is an array of GPIO_PIN_xxxx flags. If the array
+ * contains any GPIO_PIN_OUTPUT flags, the driver will manipulate the hardware
+ * such that all output pins become driven with the proper initial values
+ * simultaneously if it can. The elements in the array map to pins in the same
+ * way that bits are mapped by pin_acces_32(), and the same restrictions may
+ * apply. For example, to configure pins 2 and 3 it may be necessary to set
+ * first_pin to zero and only populate pin_flags[2] and pin_flags[3]. If a
+ * given array entry doesn't contain GPIO_PIN_INPUT or GPIO_PIN_OUTPUT then no
+ * configuration is done for that pin.
+ *
+ * Some devices may limit the value of first_pin to 0, or to multiples of 16 or
+ * 32 or some other hardware-specific number. Invalid values in first_pin or
+ * num_pins result in an error return with errno set to EINVAL.
+ */
+struct gpio_config_32 {
+ uint32_t first_pin;
+ uint32_t num_pins;
+ uint32_t pin_flags[32];
+};
+
+/*
* ioctls
*/
#define GPIOMAXPIN _IOR('G', 0, int)
@@ -94,5 +171,8 @@
#define GPIOGET _IOWR('G', 3, struct gpio_req)
#define GPIOSET _IOW('G', 4, struct gpio_req)
#define GPIOTOGGLE _IOWR('G', 5, struct gpio_req)
+#define GPIOSETNAME _IOW('G', 6, struct gpio_pin)
+#define GPIOACCESS32 _IOWR('G', 7, struct gpio_access_32)
+#define GPIOCONFIG32 _IOW('G', 8, struct gpio_config_32)
#endif /* __GPIO_H__ */
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