[Midnightbsd-cvs] [MidnightBSD/src] 885684: sched: add SCHED_MIC, a hybrid-core-aware schedule...

[Lucas Holt]

  Branch: refs/heads/master
  Home:   https://github.com/MidnightBSD/src
  Commit: 8856847c9a27552141f003f6bf6cde119b893730
      https://github.com/MidnightBSD/src/commit/8856847c9a27552141f003f6bf6cde119b893730
  Author: Lucas Holt <luke at foolishgames.com>
  Date:   2026-06-11 (Thu, 11 Jun 2026)

  Changed paths:
    A scheduler.md
    A sys/amd64/conf/MIC
    M sys/conf/NOTES
    M sys/conf/files
    M sys/conf/options
    A sys/kern/sched_mic.c
    M sys/sys/smp.h
    M sys/x86/include/specialreg.h
    M sys/x86/x86/mp_x86.c

  Log Message:
  -----------
  sched: add SCHED_MIC, a hybrid-core-aware scheduler derived from ULE (#385)

SCHED_MIC is a copy of the ULE scheduler that weighs heterogeneous CPU
core classes when placing threads. On x86 CPUs with hybrid topologies it
prefers, in order: P-cores / AMD 3D V-Cache CCD cores, then E-cores / AMD
compute-CCD / AMD mobile "C" cores, then the second SMT thread of a busy
core, then Intel LP-E cores last. The preference is a soft, tunable bias
folded into the existing cpu_search_lowest() load comparison, applied only
on the placement path (sched_pickcpu); the long-term balancer and work
stealing stay class-blind. On homogeneous hardware, and on non-x86
architectures, SCHED_MIC behaves like ULE.

ULE remains the default; SCHED_MIC is opt-in (options SCHED_MIC, or the
sample sys/amd64/conf/MIC config).

Core class is detected per-CPU at AP startup via an smp_rendezvous in an
SI_SUB_SMP SYSINIT (#ifdef SCHED_MIC in mp_x86.c) and stored in a new
cpu_core_class[] array, defaulting to "performance" so unrecognized and
non-hybrid CPUs behave like ULE:

  - Intel P vs E: CPUID 0x1A core type (architectural).
  - Intel LP-E:   small core with no L3 (heuristic, kern.sched.detect_lpe).
  - AMD X3D / Cx: larger per-CCD L3 via CPUID 0x8000001D is preferred
                  (heuristic); symmetric/single-CCD parts stay all-perf.

Tunables under kern.sched.*: class_weight_eff, class_weight_lp,
smt_busy_penalty (0 = stock ULE SMT behavior), prefer_compute (swap AMD
cache/compute CCD preference), detect_lpe, and a read-only core_class dump.

The Intel detection path was validated against real Alder Lake silicon
(Core i7-1260P): 8 P-core threads classed perf, 8 E-cores classed eff,
no LP-E (E-cores retain L3, so the LP heuristic does not misfire).

Co-authored-by: Claude Fable 5 <noreply at anthropic.com>



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