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root/src/stable/0.9/sys/dev/e1000/e1000_ich8lan.c

Comparing stable/0.9/sys/dev/e1000/e1000_ich8lan.c (file contents):
Revision 9506 by laffer1, Sun Mar 26 15:15:03 2017 UTC vs.
Revision 9507 by laffer1, Tue Aug 15 10:42:25 2017 UTC

#	Line 1 | Line 1
1	–	/* $MidnightBSD$ */
1		/******************************************************************************
2
3	<	Copyright (c) 2001-2013, Intel Corporation
3	>	Copyright (c) 2001-2014, Intel Corporation
4		All rights reserved.
5
6		Redistribution and use in source and binary forms, with or without
#	Line 31 | Line 30
30		POSSIBILITY OF SUCH DAMAGE.
31
32		******************************************************************************/
33	<	/*$FreeBSD: release/9.2.0/sys/dev/e1000/e1000_ich8lan.c 248292 2013-03-14 22:55:59Z jfv $*/
33	>	/*$FreeBSD: stable/9/sys/dev/e1000/e1000_ich8lan.c 269647 2014-08-06 22:15:01Z jfv $*/
34
35		/* 82562G 10/100 Network Connection
36		* 82562G-2 10/100 Network Connection
#	Line 60 | Line 59
59		* 82578DC Gigabit Network Connection
60		* 82579LM Gigabit Network Connection
61		* 82579V Gigabit Network Connection
62	+	* Ethernet Connection I217-LM
63	+	* Ethernet Connection I217-V
64	+	* Ethernet Connection I218-V
65	+	* Ethernet Connection I218-LM
66	+	* Ethernet Connection (2) I218-LM
67	+	* Ethernet Connection (2) I218-V
68	+	* Ethernet Connection (3) I218-LM
69	+	* Ethernet Connection (3) I218-V
70		*/
71
72		#include "e1000_api.h"
#	Line 70 | Line 77 | static s32  e1000_acquire_nvm_ich8lan(struct e1000_hw
77		static void e1000_release_nvm_ich8lan(struct e1000_hw *hw);
78		static bool e1000_check_mng_mode_ich8lan(struct e1000_hw *hw);
79		static bool e1000_check_mng_mode_pchlan(struct e1000_hw *hw);
80	<	static void e1000_rar_set_pch2lan(struct e1000_hw *hw, u8 *addr, u32 index);
81	<	static void e1000_rar_set_pch_lpt(struct e1000_hw *hw, u8 *addr, u32 index);
80	>	static int  e1000_rar_set_pch2lan(struct e1000_hw *hw, u8 *addr, u32 index);
81	>	static int  e1000_rar_set_pch_lpt(struct e1000_hw *hw, u8 *addr, u32 index);
82	>	static s32 e1000_sw_lcd_config_ich8lan(struct e1000_hw *hw);
83		static void e1000_update_mc_addr_list_pch2lan(struct e1000_hw *hw,
84		u8 *mc_addr_list,
85		u32 mc_addr_count);
#	Line 182 | Line 190 | static bool e1000_phy_is_accessible_pchlan(struct e100
190		{
191		u16 phy_reg = 0;
192		u32 phy_id = 0;
193	<	s32 ret_val;
193	>	s32 ret_val = 0;
194		u16 retry_count;
195	+	u32 mac_reg = 0;
196
197		for (retry_count = 0; retry_count < 2; retry_count++) {
198		ret_val = hw->phy.ops.read_reg_locked(hw, PHY_ID1, &phy_reg);
#	Line 202 | Line 211 | static bool e1000_phy_is_accessible_pchlan(struct e100
211
212		if (hw->phy.id) {
213		if  (hw->phy.id == phy_id)
214	<	return TRUE;
214	>	goto out;
215		} else if (phy_id) {
216		hw->phy.id = phy_id;
217		hw->phy.revision = (u32)(phy_reg & ~PHY_REVISION_MASK);
218	<	return TRUE;
218	>	goto out;
219		}
220
221		/* In case the PHY needs to be in mdio slow mode,
222		* set slow mode and try to get the PHY id again.
223		*/
224	<	hw->phy.ops.release(hw);
225	<	ret_val = e1000_set_mdio_slow_mode_hv(hw);
226	<	if (!ret_val)
227	<	ret_val = e1000_get_phy_id(hw);
228	<	hw->phy.ops.acquire(hw);
224	>	if (hw->mac.type < e1000_pch_lpt) {
225	>	hw->phy.ops.release(hw);
226	>	ret_val = e1000_set_mdio_slow_mode_hv(hw);
227	>	if (!ret_val)
228	>	ret_val = e1000_get_phy_id(hw);
229	>	hw->phy.ops.acquire(hw);
230	>	}
231
232	<	return !ret_val;
232	>	if (ret_val)
233	>	return FALSE;
234	>	out:
235	>	if (hw->mac.type == e1000_pch_lpt) {
236	>	/* Unforce SMBus mode in PHY */
237	>	hw->phy.ops.read_reg_locked(hw, CV_SMB_CTRL, &phy_reg);
238	>	phy_reg &= ~CV_SMB_CTRL_FORCE_SMBUS;
239	>	hw->phy.ops.write_reg_locked(hw, CV_SMB_CTRL, phy_reg);
240	>
241	>	/* Unforce SMBus mode in MAC */
242	>	mac_reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
243	>	mac_reg &= ~E1000_CTRL_EXT_FORCE_SMBUS;
244	>	E1000_WRITE_REG(hw, E1000_CTRL_EXT, mac_reg);
245	>	}
246	>
247	>	return TRUE;
248		}
249
250		/**
251	+	*  e1000_toggle_lanphypc_pch_lpt - toggle the LANPHYPC pin value
252	+	*  @hw: pointer to the HW structure
253	+	*
254	+	*  Toggling the LANPHYPC pin value fully power-cycles the PHY and is
255	+	*  used to reset the PHY to a quiescent state when necessary.
256	+	**/
257	+	static void e1000_toggle_lanphypc_pch_lpt(struct e1000_hw *hw)
258	+	{
259	+	u32 mac_reg;
260	+
261	+	DEBUGFUNC("e1000_toggle_lanphypc_pch_lpt");
262	+
263	+	/* Set Phy Config Counter to 50msec */
264	+	mac_reg = E1000_READ_REG(hw, E1000_FEXTNVM3);
265	+	mac_reg &= ~E1000_FEXTNVM3_PHY_CFG_COUNTER_MASK;
266	+	mac_reg |= E1000_FEXTNVM3_PHY_CFG_COUNTER_50MSEC;
267	+	E1000_WRITE_REG(hw, E1000_FEXTNVM3, mac_reg);
268	+
269	+	/* Toggle LANPHYPC Value bit */
270	+	mac_reg = E1000_READ_REG(hw, E1000_CTRL);
271	+	mac_reg |= E1000_CTRL_LANPHYPC_OVERRIDE;
272	+	mac_reg &= ~E1000_CTRL_LANPHYPC_VALUE;
273	+	E1000_WRITE_REG(hw, E1000_CTRL, mac_reg);
274	+	E1000_WRITE_FLUSH(hw);
275	+	usec_delay(10);
276	+	mac_reg &= ~E1000_CTRL_LANPHYPC_OVERRIDE;
277	+	E1000_WRITE_REG(hw, E1000_CTRL, mac_reg);
278	+	E1000_WRITE_FLUSH(hw);
279	+
280	+	if (hw->mac.type < e1000_pch_lpt) {
281	+	msec_delay(50);
282	+	} else {
283	+	u16 count = 20;
284	+
285	+	do {
286	+	msec_delay(5);
287	+	} while (!(E1000_READ_REG(hw, E1000_CTRL_EXT) &
288	+	E1000_CTRL_EXT_LPCD) && count--);
289	+
290	+	msec_delay(30);
291	+	}
292	+	}
293	+
294	+	/**
295		*  e1000_init_phy_workarounds_pchlan - PHY initialization workarounds
296		*  @hw: pointer to the HW structure
297		*
#	Line 232 | Line 302 | static s32 e1000_init_phy_workarounds_pchlan(struct e1
302		{
303		u32 mac_reg, fwsm = E1000_READ_REG(hw, E1000_FWSM);
304		s32 ret_val;
235	–	u16 phy_reg;
305
306		DEBUGFUNC("e1000_init_phy_workarounds_pchlan");
307
#	Line 241 | Line 310 | static s32 e1000_init_phy_workarounds_pchlan(struct e1
310		*/
311		e1000_gate_hw_phy_config_ich8lan(hw, TRUE);
312
313	+	/* It is not possible to be certain of the current state of ULP
314	+	* so forcibly disable it.
315	+	*/
316	+	hw->dev_spec.ich8lan.ulp_state = e1000_ulp_state_unknown;
317	+	e1000_disable_ulp_lpt_lp(hw, TRUE);
318	+
319		ret_val = hw->phy.ops.acquire(hw);
320		if (ret_val) {
321		DEBUGOUT("Failed to initialize PHY flow\n");
#	Line 263 | Line 338 | static s32 e1000_init_phy_workarounds_pchlan(struct e1
338		mac_reg |= E1000_CTRL_EXT_FORCE_SMBUS;
339		E1000_WRITE_REG(hw, E1000_CTRL_EXT, mac_reg);
340
341	+	/* Wait 50 milliseconds for MAC to finish any retries
342	+	* that it might be trying to perform from previous
343	+	* attempts to acknowledge any phy read requests.
344	+	*/
345	+	msec_delay(50);
346	+
347		/* fall-through */
348		case e1000_pch2lan:
349	<	if (e1000_phy_is_accessible_pchlan(hw)) {
269	<	if (hw->mac.type == e1000_pch_lpt) {
270	<	/* Unforce SMBus mode in PHY */
271	<	hw->phy.ops.read_reg_locked(hw, CV_SMB_CTRL,
272	<	&phy_reg);
273	<	phy_reg &= ~CV_SMB_CTRL_FORCE_SMBUS;
274	<	hw->phy.ops.write_reg_locked(hw, CV_SMB_CTRL,
275	<	phy_reg);
276	<
277	<	/* Unforce SMBus mode in MAC */
278	<	mac_reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
279	<	mac_reg &= ~E1000_CTRL_EXT_FORCE_SMBUS;
280	<	E1000_WRITE_REG(hw, E1000_CTRL_EXT, mac_reg);
281	<	}
349	>	if (e1000_phy_is_accessible_pchlan(hw))
350		break;
283	–	}
351
352		/* fall-through */
353		case e1000_pchlan:
#	Line 290 | Line 357 | static s32 e1000_init_phy_workarounds_pchlan(struct e1
357
358		if (hw->phy.ops.check_reset_block(hw)) {
359		DEBUGOUT("Required LANPHYPC toggle blocked by ME\n");
360	+	ret_val = -E1000_ERR_PHY;
361		break;
362		}
363
364	<	DEBUGOUT("Toggling LANPHYPC\n");
364	>	/* Toggle LANPHYPC Value bit */
365	>	e1000_toggle_lanphypc_pch_lpt(hw);
366	>	if (hw->mac.type >= e1000_pch_lpt) {
367	>	if (e1000_phy_is_accessible_pchlan(hw))
368	>	break;
369
298	–	/* Set Phy Config Counter to 50msec */
299	–	mac_reg = E1000_READ_REG(hw, E1000_FEXTNVM3);
300	–	mac_reg &= ~E1000_FEXTNVM3_PHY_CFG_COUNTER_MASK;
301	–	mac_reg |= E1000_FEXTNVM3_PHY_CFG_COUNTER_50MSEC;
302	–	E1000_WRITE_REG(hw, E1000_FEXTNVM3, mac_reg);
303	–
304	–	if (hw->mac.type == e1000_pch_lpt) {
370		/* Toggling LANPHYPC brings the PHY out of SMBus mode
371	<	* So ensure that the MAC is also out of SMBus mode
371	>	* so ensure that the MAC is also out of SMBus mode
372		*/
373		mac_reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
374		mac_reg &= ~E1000_CTRL_EXT_FORCE_SMBUS;
375		E1000_WRITE_REG(hw, E1000_CTRL_EXT, mac_reg);
311	–	}
376
377	<	/* Toggle LANPHYPC Value bit */
378	<	mac_reg = E1000_READ_REG(hw, E1000_CTRL);
379	<	mac_reg |= E1000_CTRL_LANPHYPC_OVERRIDE;
380	<	mac_reg &= ~E1000_CTRL_LANPHYPC_VALUE;
317	<	E1000_WRITE_REG(hw, E1000_CTRL, mac_reg);
318	<	E1000_WRITE_FLUSH(hw);
319	<	usec_delay(10);
320	<	mac_reg &= ~E1000_CTRL_LANPHYPC_OVERRIDE;
321	<	E1000_WRITE_REG(hw, E1000_CTRL, mac_reg);
322	<	E1000_WRITE_FLUSH(hw);
323	<	if (hw->mac.type < e1000_pch_lpt) {
324	<	msec_delay(50);
325	<	} else {
326	<	u16 count = 20;
327	<	do {
328	<	msec_delay(5);
329	<	} while (!(E1000_READ_REG(hw, E1000_CTRL_EXT) &
330	<	E1000_CTRL_EXT_LPCD) && count--);
377	>	if (e1000_phy_is_accessible_pchlan(hw))
378	>	break;
379	>
380	>	ret_val = -E1000_ERR_PHY;
381		}
382		break;
383		default:
#	Line 335 | Line 385 | static s32 e1000_init_phy_workarounds_pchlan(struct e1
385		}
386
387		hw->phy.ops.release(hw);
388	+	if (!ret_val) {
389
390	<	/* Reset the PHY before any access to it.  Doing so, ensures
391	<	* that the PHY is in a known good state before we read/write
392	<	* PHY registers.  The generic reset is sufficient here,
393	<	* because we haven't determined the PHY type yet.
394	<	*/
344	<	ret_val = e1000_phy_hw_reset_generic(hw);
390	>	/* Check to see if able to reset PHY.  Print error if not */
391	>	if (hw->phy.ops.check_reset_block(hw)) {
392	>	ERROR_REPORT("Reset blocked by ME\n");
393	>	goto out;
394	>	}
395
396	+	/* Reset the PHY before any access to it.  Doing so, ensures
397	+	* that the PHY is in a known good state before we read/write
398	+	* PHY registers.  The generic reset is sufficient here,
399	+	* because we haven't determined the PHY type yet.
400	+	*/
401	+	ret_val = e1000_phy_hw_reset_generic(hw);
402	+	if (ret_val)
403	+	goto out;
404	+
405	+	/* On a successful reset, possibly need to wait for the PHY
406	+	* to quiesce to an accessible state before returning control
407	+	* to the calling function.  If the PHY does not quiesce, then
408	+	* return E1000E_BLK_PHY_RESET, as this is the condition that
409	+	*  the PHY is in.
410	+	*/
411	+	ret_val = hw->phy.ops.check_reset_block(hw);
412	+	if (ret_val)
413	+	ERROR_REPORT("ME blocked access to PHY after reset\n");
414	+	}
415	+
416		out:
417		/* Ungate automatic PHY configuration on non-managed 82579 */
418		if ((hw->mac.type == e1000_pch2lan) &&
#	Line 551 | Line 621 | static s32 e1000_init_nvm_params_ich8lan(struct e1000_
621		DEBUGFUNC("e1000_init_nvm_params_ich8lan");
622
623		/* Can't read flash registers if the register set isn't mapped. */
624	+	nvm->type = e1000_nvm_flash_sw;
625		if (!hw->flash_address) {
626		DEBUGOUT("ERROR: Flash registers not mapped\n");
627		return -E1000_ERR_CONFIG;
628		}
629
559	–	nvm->type = e1000_nvm_flash_sw;
560	–
630		gfpreg = E1000_READ_FLASH_REG(hw, ICH_FLASH_GFPREG);
631
632		/* sector_X_addr is a "sector"-aligned address (4096 bytes)
#	Line 573 | Line 642 | static s32 e1000_init_nvm_params_ich8lan(struct e1000_
642		/* find total size of the NVM, then cut in half since the total
643		* size represents two separate NVM banks.
644		*/
645	<	nvm->flash_bank_size = (sector_end_addr - sector_base_addr)
646	<	<< FLASH_SECTOR_ADDR_SHIFT;
645	>	nvm->flash_bank_size = ((sector_end_addr - sector_base_addr)
646	>	<< FLASH_SECTOR_ADDR_SHIFT);
647		nvm->flash_bank_size /= 2;
648		/* Adjust to word count */
649		nvm->flash_bank_size /= sizeof(u16);
#	Line 767 | Line 836 | s32 e1000_read_emi_reg_locked(struct e1000_hw *hw, u16
836		*
837		*  Assumes the SW/FW/HW Semaphore is already acquired.
838		**/
839	<	static s32 e1000_write_emi_reg_locked(struct e1000_hw *hw, u16 addr, u16 data)
839	>	s32 e1000_write_emi_reg_locked(struct e1000_hw *hw, u16 addr, u16 data)
840		{
841		DEBUGFUNC("e1000_read_emi_reg_locked");
842
#	Line 781 | Line 850 | static s32 e1000_write_emi_reg_locked(struct e1000_hw
850		*  Enable/disable EEE based on setting in dev_spec structure, the duplex of
851		*  the link and the EEE capabilities of the link partner.  The LPI Control
852		*  register bits will remain set only if/when link is up.
853	+	*
854	+	*  EEE LPI must not be asserted earlier than one second after link is up.
855	+	*  On 82579, EEE LPI should not be enabled until such time otherwise there
856	+	*  can be link issues with some switches.  Other devices can have EEE LPI
857	+	*  enabled immediately upon link up since they have a timer in hardware which
858	+	*  prevents LPI from being asserted too early.
859		**/
860	<	static s32 e1000_set_eee_pchlan(struct e1000_hw *hw)
860	>	s32 e1000_set_eee_pchlan(struct e1000_hw *hw)
861		{
862		struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
863		s32 ret_val;
864	<	u16 lpi_ctrl;
864	>	u16 lpa, pcs_status, adv, adv_addr, lpi_ctrl, data;
865
866		DEBUGFUNC("e1000_set_eee_pchlan");
867
868	<	if ((hw->phy.type != e1000_phy_82579) &&
869	<	(hw->phy.type != e1000_phy_i217))
868	>	switch (hw->phy.type) {
869	>	case e1000_phy_82579:
870	>	lpa = I82579_EEE_LP_ABILITY;
871	>	pcs_status = I82579_EEE_PCS_STATUS;
872	>	adv_addr = I82579_EEE_ADVERTISEMENT;
873	>	break;
874	>	case e1000_phy_i217:
875	>	lpa = I217_EEE_LP_ABILITY;
876	>	pcs_status = I217_EEE_PCS_STATUS;
877	>	adv_addr = I217_EEE_ADVERTISEMENT;
878	>	break;
879	>	default:
880		return E1000_SUCCESS;
881	+	}
882
883		ret_val = hw->phy.ops.acquire(hw);
884		if (ret_val)
#	Line 807 | Line 893 | static s32 e1000_set_eee_pchlan(struct e1000_hw *hw)
893
894		/* Enable EEE if not disabled by user */
895		if (!dev_spec->eee_disable) {
810	–	u16 lpa, pcs_status, data;
811	–
896		/* Save off link partner's EEE ability */
813	–	switch (hw->phy.type) {
814	–	case e1000_phy_82579:
815	–	lpa = I82579_EEE_LP_ABILITY;
816	–	pcs_status = I82579_EEE_PCS_STATUS;
817	–	break;
818	–	case e1000_phy_i217:
819	–	lpa = I217_EEE_LP_ABILITY;
820	–	pcs_status = I217_EEE_PCS_STATUS;
821	–	break;
822	–	default:
823	–	ret_val = -E1000_ERR_PHY;
824	–	goto release;
825	–	}
897		ret_val = e1000_read_emi_reg_locked(hw, lpa,
898		&dev_spec->eee_lp_ability);
899		if (ret_val)
900		goto release;
901
902	+	/* Read EEE advertisement */
903	+	ret_val = e1000_read_emi_reg_locked(hw, adv_addr, &adv);
904	+	if (ret_val)
905	+	goto release;
906	+
907		/* Enable EEE only for speeds in which the link partner is
908	<	* EEE capable.
908	>	* EEE capable and for which we advertise EEE.
909		*/
910	<	if (dev_spec->eee_lp_ability & I82579_EEE_1000_SUPPORTED)
910	>	if (adv & dev_spec->eee_lp_ability & I82579_EEE_1000_SUPPORTED)
911		lpi_ctrl |= I82579_LPI_CTRL_1000_ENABLE;
912
913	<	if (dev_spec->eee_lp_ability & I82579_EEE_100_SUPPORTED) {
913	>	if (adv & dev_spec->eee_lp_ability & I82579_EEE_100_SUPPORTED) {
914		hw->phy.ops.read_reg_locked(hw, PHY_LP_ABILITY, &data);
915		if (data & NWAY_LPAR_100TX_FD_CAPS)
916		lpi_ctrl |= I82579_LPI_CTRL_100_ENABLE;
#	Line 846 | Line 922 | static s32 e1000_set_eee_pchlan(struct e1000_hw *hw)
922		dev_spec->eee_lp_ability &=
923		~I82579_EEE_100_SUPPORTED;
924		}
925	+	}
926
927	<	/* R/Clr IEEE MMD 3.1 bits 11:10 - Tx/Rx LPI Received */
928	<	ret_val = e1000_read_emi_reg_locked(hw, pcs_status, &data);
927	>	if (hw->phy.type == e1000_phy_82579) {
928	>	ret_val = e1000_read_emi_reg_locked(hw, I82579_LPI_PLL_SHUT,
929	>	&data);
930		if (ret_val)
931		goto release;
932	+
933	+	data &= ~I82579_LPI_100_PLL_SHUT;
934	+	ret_val = e1000_write_emi_reg_locked(hw, I82579_LPI_PLL_SHUT,
935	+	data);
936		}
937
938	+	/* R/Clr IEEE MMD 3.1 bits 11:10 - Tx/Rx LPI Received */
939	+	ret_val = e1000_read_emi_reg_locked(hw, pcs_status, &data);
940	+	if (ret_val)
941	+	goto release;
942	+
943		ret_val = hw->phy.ops.write_reg_locked(hw, I82579_LPI_CTRL, lpi_ctrl);
944		release:
945		hw->phy.ops.release(hw);
#	Line 868 | Line 955 | release:
955		*  When K1 is enabled for 1Gbps, the MAC can miss 2 DMA completion indications
956		*  preventing further DMA write requests.  Workaround the issue by disabling
957		*  the de-assertion of the clock request when in 1Gpbs mode.
958	+	*  Also, set appropriate Tx re-transmission timeouts for 10 and 100Half link
959	+	*  speeds in order to avoid Tx hangs.
960		**/
961		static s32 e1000_k1_workaround_lpt_lp(struct e1000_hw *hw, bool link)
962		{
963		u32 fextnvm6 = E1000_READ_REG(hw, E1000_FEXTNVM6);
964	+	u32 status = E1000_READ_REG(hw, E1000_STATUS);
965		s32 ret_val = E1000_SUCCESS;
966	+	u16 reg;
967
968	<	if (link && (E1000_READ_REG(hw, E1000_STATUS) &
878	<	E1000_STATUS_SPEED_1000)) {
879	<	u16 kmrn_reg;
880	<
968	>	if (link && (status & E1000_STATUS_SPEED_1000)) {
969		ret_val = hw->phy.ops.acquire(hw);
970		if (ret_val)
971		return ret_val;
972
973		ret_val =
974		e1000_read_kmrn_reg_locked(hw, E1000_KMRNCTRLSTA_K1_CONFIG,
975	<	&kmrn_reg);
975	>	&reg);
976		if (ret_val)
977		goto release;
978
979		ret_val =
980		e1000_write_kmrn_reg_locked(hw,
981		E1000_KMRNCTRLSTA_K1_CONFIG,
982	<	kmrn_reg &
982	>	reg &
983		~E1000_KMRNCTRLSTA_K1_ENABLE);
984		if (ret_val)
985		goto release;
#	Line 904 | Line 992 | static s32 e1000_k1_workaround_lpt_lp(struct e1000_hw
992		ret_val =
993		e1000_write_kmrn_reg_locked(hw,
994		E1000_KMRNCTRLSTA_K1_CONFIG,
995	<	kmrn_reg);
995	>	reg);
996		release:
997		hw->phy.ops.release(hw);
998		} else {
999		/* clear FEXTNVM6 bit 8 on link down or 10/100 */
1000	<	E1000_WRITE_REG(hw, E1000_FEXTNVM6,
1001	<	fextnvm6 & ~E1000_FEXTNVM6_REQ_PLL_CLK);
1000	>	fextnvm6 &= ~E1000_FEXTNVM6_REQ_PLL_CLK;
1001	>
1002	>	if (!link || ((status & E1000_STATUS_SPEED_100) &&
1003	>	(status & E1000_STATUS_FD)))
1004	>	goto update_fextnvm6;
1005	>
1006	>	ret_val = hw->phy.ops.read_reg(hw, I217_INBAND_CTRL, &reg);
1007	>	if (ret_val)
1008	>	return ret_val;
1009	>
1010	>	/* Clear link status transmit timeout */
1011	>	reg &= ~I217_INBAND_CTRL_LINK_STAT_TX_TIMEOUT_MASK;
1012	>
1013	>	if (status & E1000_STATUS_SPEED_100) {
1014	>	/* Set inband Tx timeout to 5x10us for 100Half */
1015	>	reg |= 5 << I217_INBAND_CTRL_LINK_STAT_TX_TIMEOUT_SHIFT;
1016	>
1017	>	/* Do not extend the K1 entry latency for 100Half */
1018	>	fextnvm6 &= ~E1000_FEXTNVM6_ENABLE_K1_ENTRY_CONDITION;
1019	>	} else {
1020	>	/* Set inband Tx timeout to 50x10us for 10Full/Half */
1021	>	reg |= 50 <<
1022	>	I217_INBAND_CTRL_LINK_STAT_TX_TIMEOUT_SHIFT;
1023	>
1024	>	/* Extend the K1 entry latency for 10 Mbps */
1025	>	fextnvm6 |= E1000_FEXTNVM6_ENABLE_K1_ENTRY_CONDITION;
1026	>	}
1027	>
1028	>	ret_val = hw->phy.ops.write_reg(hw, I217_INBAND_CTRL, reg);
1029	>	if (ret_val)
1030	>	return ret_val;
1031	>
1032	>	update_fextnvm6:
1033	>	E1000_WRITE_REG(hw, E1000_FEXTNVM6, fextnvm6);
1034		}
1035
1036		return ret_val;
#	Line 1019 | Line 1139 | static s32 e1000_platform_pm_pch_lpt(struct e1000_hw *
1139		lat_ns /= 1000000000;
1140		obff_hwm = (s32)(rxa - lat_ns);
1141		}
1022	–
1142		if ((obff_hwm < 0) || (obff_hwm > E1000_SVT_OFF_HWM_MASK)) {
1143		DEBUGOUT1("Invalid high water mark %d\n", obff_hwm);
1144		return -E1000_ERR_CONFIG;
#	Line 1080 | Line 1199 | static s32 e1000_set_obff_timer_pch_lpt(struct e1000_h
1199		}
1200
1201		/**
1202	+	*  e1000_enable_ulp_lpt_lp - configure Ultra Low Power mode for LynxPoint-LP
1203	+	*  @hw: pointer to the HW structure
1204	+	*  @to_sx: boolean indicating a system power state transition to Sx
1205	+	*
1206	+	*  When link is down, configure ULP mode to significantly reduce the power
1207	+	*  to the PHY.  If on a Manageability Engine (ME) enabled system, tell the
1208	+	*  ME firmware to start the ULP configuration.  If not on an ME enabled
1209	+	*  system, configure the ULP mode by software.
1210	+	*/
1211	+	s32 e1000_enable_ulp_lpt_lp(struct e1000_hw *hw, bool to_sx)
1212	+	{
1213	+	u32 mac_reg;
1214	+	s32 ret_val = E1000_SUCCESS;
1215	+	u16 phy_reg;
1216	+
1217	+	if ((hw->mac.type < e1000_pch_lpt) ||
1218	+	(hw->device_id == E1000_DEV_ID_PCH_LPT_I217_LM) ||
1219	+	(hw->device_id == E1000_DEV_ID_PCH_LPT_I217_V) ||
1220	+	(hw->device_id == E1000_DEV_ID_PCH_I218_LM2) ||
1221	+	(hw->device_id == E1000_DEV_ID_PCH_I218_V2) ||
1222	+	(hw->dev_spec.ich8lan.ulp_state == e1000_ulp_state_on))
1223	+	return 0;
1224	+
1225	+	if (E1000_READ_REG(hw, E1000_FWSM) & E1000_ICH_FWSM_FW_VALID) {
1226	+	/* Request ME configure ULP mode in the PHY */
1227	+	mac_reg = E1000_READ_REG(hw, E1000_H2ME);
1228	+	mac_reg |= E1000_H2ME_ULP | E1000_H2ME_ENFORCE_SETTINGS;
1229	+	E1000_WRITE_REG(hw, E1000_H2ME, mac_reg);
1230	+
1231	+	goto out;
1232	+	}
1233	+
1234	+	if (!to_sx) {
1235	+	int i = 0;
1236	+
1237	+	/* Poll up to 5 seconds for Cable Disconnected indication */
1238	+	while (!(E1000_READ_REG(hw, E1000_FEXT) &
1239	+	E1000_FEXT_PHY_CABLE_DISCONNECTED)) {
1240	+	/* Bail if link is re-acquired */
1241	+	if (E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU)
1242	+	return -E1000_ERR_PHY;
1243	+
1244	+	if (i++ == 100)
1245	+	break;
1246	+
1247	+	msec_delay(50);
1248	+	}
1249	+	DEBUGOUT2("CABLE_DISCONNECTED %s set after %dmsec\n",
1250	+	(E1000_READ_REG(hw, E1000_FEXT) &
1251	+	E1000_FEXT_PHY_CABLE_DISCONNECTED) ? "" : "not",
1252	+	i * 50);
1253	+	}
1254	+
1255	+	ret_val = hw->phy.ops.acquire(hw);
1256	+	if (ret_val)
1257	+	goto out;
1258	+
1259	+	/* Force SMBus mode in PHY */
1260	+	ret_val = e1000_read_phy_reg_hv_locked(hw, CV_SMB_CTRL, &phy_reg);
1261	+	if (ret_val)
1262	+	goto release;
1263	+	phy_reg |= CV_SMB_CTRL_FORCE_SMBUS;
1264	+	e1000_write_phy_reg_hv_locked(hw, CV_SMB_CTRL, phy_reg);
1265	+
1266	+	/* Force SMBus mode in MAC */
1267	+	mac_reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
1268	+	mac_reg |= E1000_CTRL_EXT_FORCE_SMBUS;
1269	+	E1000_WRITE_REG(hw, E1000_CTRL_EXT, mac_reg);
1270	+
1271	+	/* Set Inband ULP Exit, Reset to SMBus mode and
1272	+	* Disable SMBus Release on PERST# in PHY
1273	+	*/
1274	+	ret_val = e1000_read_phy_reg_hv_locked(hw, I218_ULP_CONFIG1, &phy_reg);
1275	+	if (ret_val)
1276	+	goto release;
1277	+	phy_reg |= (I218_ULP_CONFIG1_RESET_TO_SMBUS |
1278	+	I218_ULP_CONFIG1_DISABLE_SMB_PERST);
1279	+	if (to_sx) {
1280	+	if (E1000_READ_REG(hw, E1000_WUFC) & E1000_WUFC_LNKC)
1281	+	phy_reg |= I218_ULP_CONFIG1_WOL_HOST;
1282	+
1283	+	phy_reg |= I218_ULP_CONFIG1_STICKY_ULP;
1284	+	} else {
1285	+	phy_reg |= I218_ULP_CONFIG1_INBAND_EXIT;
1286	+	}
1287	+	e1000_write_phy_reg_hv_locked(hw, I218_ULP_CONFIG1, phy_reg);
1288	+
1289	+	/* Set Disable SMBus Release on PERST# in MAC */
1290	+	mac_reg = E1000_READ_REG(hw, E1000_FEXTNVM7);
1291	+	mac_reg |= E1000_FEXTNVM7_DISABLE_SMB_PERST;
1292	+	E1000_WRITE_REG(hw, E1000_FEXTNVM7, mac_reg);
1293	+
1294	+	/* Commit ULP changes in PHY by starting auto ULP configuration */
1295	+	phy_reg |= I218_ULP_CONFIG1_START;
1296	+	e1000_write_phy_reg_hv_locked(hw, I218_ULP_CONFIG1, phy_reg);
1297	+	release:
1298	+	hw->phy.ops.release(hw);
1299	+	out:
1300	+	if (ret_val) {
1301	+	DEBUGOUT1("Error in ULP enable flow: %d\n", ret_val);
1302	+	} else
1303	+	hw->dev_spec.ich8lan.ulp_state = e1000_ulp_state_on;
1304	+
1305	+	return ret_val;
1306	+	}
1307	+
1308	+	/**
1309	+	*  e1000_disable_ulp_lpt_lp - unconfigure Ultra Low Power mode for LynxPoint-LP
1310	+	*  @hw: pointer to the HW structure
1311	+	*  @force: boolean indicating whether or not to force disabling ULP
1312	+	*
1313	+	*  Un-configure ULP mode when link is up, the system is transitioned from
1314	+	*  Sx or the driver is unloaded.  If on a Manageability Engine (ME) enabled
1315	+	*  system, poll for an indication from ME that ULP has been un-configured.
1316	+	*  If not on an ME enabled system, un-configure the ULP mode by software.
1317	+	*
1318	+	*  During nominal operation, this function is called when link is acquired
1319	+	*  to disable ULP mode (force=FALSE); otherwise, for example when unloading
1320	+	*  the driver or during Sx->S0 transitions, this is called with force=TRUE
1321	+	*  to forcibly disable ULP.
1322	+	*/
1323	+	s32 e1000_disable_ulp_lpt_lp(struct e1000_hw *hw, bool force)
1324	+	{
1325	+	s32 ret_val = E1000_SUCCESS;
1326	+	u32 mac_reg;
1327	+	u16 phy_reg;
1328	+	int i = 0;
1329	+
1330	+	if ((hw->mac.type < e1000_pch_lpt) ||
1331	+	(hw->device_id == E1000_DEV_ID_PCH_LPT_I217_LM) ||
1332	+	(hw->device_id == E1000_DEV_ID_PCH_LPT_I217_V) ||
1333	+	(hw->device_id == E1000_DEV_ID_PCH_I218_LM2) ||
1334	+	(hw->device_id == E1000_DEV_ID_PCH_I218_V2) ||
1335	+	(hw->dev_spec.ich8lan.ulp_state == e1000_ulp_state_off))
1336	+	return 0;
1337	+
1338	+	if (E1000_READ_REG(hw, E1000_FWSM) & E1000_ICH_FWSM_FW_VALID) {
1339	+	if (force) {
1340	+	/* Request ME un-configure ULP mode in the PHY */
1341	+	mac_reg = E1000_READ_REG(hw, E1000_H2ME);
1342	+	mac_reg &= ~E1000_H2ME_ULP;
1343	+	mac_reg |= E1000_H2ME_ENFORCE_SETTINGS;
1344	+	E1000_WRITE_REG(hw, E1000_H2ME, mac_reg);
1345	+	}
1346	+
1347	+	/* Poll up to 100msec for ME to clear ULP_CFG_DONE */
1348	+	while (E1000_READ_REG(hw, E1000_FWSM) &
1349	+	E1000_FWSM_ULP_CFG_DONE) {
1350	+	if (i++ == 10) {
1351	+	ret_val = -E1000_ERR_PHY;
1352	+	goto out;
1353	+	}
1354	+
1355	+	msec_delay(10);
1356	+	}
1357	+	DEBUGOUT1("ULP_CONFIG_DONE cleared after %dmsec\n", i * 10);
1358	+
1359	+	if (force) {
1360	+	mac_reg = E1000_READ_REG(hw, E1000_H2ME);
1361	+	mac_reg &= ~E1000_H2ME_ENFORCE_SETTINGS;
1362	+	E1000_WRITE_REG(hw, E1000_H2ME, mac_reg);
1363	+	} else {
1364	+	/* Clear H2ME.ULP after ME ULP configuration */
1365	+	mac_reg = E1000_READ_REG(hw, E1000_H2ME);
1366	+	mac_reg &= ~E1000_H2ME_ULP;
1367	+	E1000_WRITE_REG(hw, E1000_H2ME, mac_reg);
1368	+	}
1369	+
1370	+	goto out;
1371	+	}
1372	+
1373	+	ret_val = hw->phy.ops.acquire(hw);
1374	+	if (ret_val)
1375	+	goto out;
1376	+
1377	+	if (force)
1378	+	/* Toggle LANPHYPC Value bit */
1379	+	e1000_toggle_lanphypc_pch_lpt(hw);
1380	+
1381	+	/* Unforce SMBus mode in PHY */
1382	+	ret_val = e1000_read_phy_reg_hv_locked(hw, CV_SMB_CTRL, &phy_reg);
1383	+	if (ret_val) {
1384	+	/* The MAC might be in PCIe mode, so temporarily force to
1385	+	* SMBus mode in order to access the PHY.
1386	+	*/
1387	+	mac_reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
1388	+	mac_reg |= E1000_CTRL_EXT_FORCE_SMBUS;
1389	+	E1000_WRITE_REG(hw, E1000_CTRL_EXT, mac_reg);
1390	+
1391	+	msec_delay(50);
1392	+
1393	+	ret_val = e1000_read_phy_reg_hv_locked(hw, CV_SMB_CTRL,
1394	+	&phy_reg);
1395	+	if (ret_val)
1396	+	goto release;
1397	+	}
1398	+	phy_reg &= ~CV_SMB_CTRL_FORCE_SMBUS;
1399	+	e1000_write_phy_reg_hv_locked(hw, CV_SMB_CTRL, phy_reg);
1400	+
1401	+	/* Unforce SMBus mode in MAC */
1402	+	mac_reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
1403	+	mac_reg &= ~E1000_CTRL_EXT_FORCE_SMBUS;
1404	+	E1000_WRITE_REG(hw, E1000_CTRL_EXT, mac_reg);
1405	+
1406	+	/* When ULP mode was previously entered, K1 was disabled by the
1407	+	* hardware.  Re-Enable K1 in the PHY when exiting ULP.
1408	+	*/
1409	+	ret_val = e1000_read_phy_reg_hv_locked(hw, HV_PM_CTRL, &phy_reg);
1410	+	if (ret_val)
1411	+	goto release;
1412	+	phy_reg |= HV_PM_CTRL_K1_ENABLE;
1413	+	e1000_write_phy_reg_hv_locked(hw, HV_PM_CTRL, phy_reg);
1414	+
1415	+	/* Clear ULP enabled configuration */
1416	+	ret_val = e1000_read_phy_reg_hv_locked(hw, I218_ULP_CONFIG1, &phy_reg);
1417	+	if (ret_val)
1418	+	goto release;
1419	+	phy_reg &= ~(I218_ULP_CONFIG1_IND |
1420	+	I218_ULP_CONFIG1_STICKY_ULP |
1421	+	I218_ULP_CONFIG1_RESET_TO_SMBUS |
1422	+	I218_ULP_CONFIG1_WOL_HOST |
1423	+	I218_ULP_CONFIG1_INBAND_EXIT |
1424	+	I218_ULP_CONFIG1_DISABLE_SMB_PERST);
1425	+	e1000_write_phy_reg_hv_locked(hw, I218_ULP_CONFIG1, phy_reg);
1426	+
1427	+	/* Commit ULP changes by starting auto ULP configuration */
1428	+	phy_reg |= I218_ULP_CONFIG1_START;
1429	+	e1000_write_phy_reg_hv_locked(hw, I218_ULP_CONFIG1, phy_reg);
1430	+
1431	+	/* Clear Disable SMBus Release on PERST# in MAC */
1432	+	mac_reg = E1000_READ_REG(hw, E1000_FEXTNVM7);
1433	+	mac_reg &= ~E1000_FEXTNVM7_DISABLE_SMB_PERST;
1434	+	E1000_WRITE_REG(hw, E1000_FEXTNVM7, mac_reg);
1435	+
1436	+	release:
1437	+	hw->phy.ops.release(hw);
1438	+	if (force) {
1439	+	hw->phy.ops.reset(hw);
1440	+	msec_delay(50);
1441	+	}
1442	+	out:
1443	+	if (ret_val) {
1444	+	DEBUGOUT1("Error in ULP disable flow: %d\n", ret_val);
1445	+	} else
1446	+	hw->dev_spec.ich8lan.ulp_state = e1000_ulp_state_off;
1447	+
1448	+	return ret_val;
1449	+	}
1450	+
1451	+	/**
1452		*  e1000_check_for_copper_link_ich8lan - Check for link (Copper)
1453		*  @hw: pointer to the HW structure
1454		*
#	Line 1104 | Line 1473 | static s32 e1000_check_for_copper_link_ich8lan(struct
1473		if (!mac->get_link_status)
1474		return E1000_SUCCESS;
1475
1476	<	/* First we want to see if the MII Status Register reports
1477	<	* link.  If so, then we want to get the current speed/duplex
1478	<	* of the PHY.
1479	<	*/
1480	<	ret_val = e1000_phy_has_link_generic(hw, 1, 0, &link);
1481	<	if (ret_val)
1482	<	return ret_val;
1476	>	/* First we want to see if the MII Status Register reports
1477	>	* link.  If so, then we want to get the current speed/duplex
1478	>	* of the PHY.
1479	>	*/
1480	>	ret_val = e1000_phy_has_link_generic(hw, 1, 0, &link);
1481	>	if (ret_val)
1482	>	return ret_val;
1483
1484		if (hw->mac.type == e1000_pchlan) {
1485		ret_val = e1000_k1_gig_workaround_hv(hw, link);
#	Line 1118 | Line 1487 | static s32 e1000_check_for_copper_link_ich8lan(struct
1487		return ret_val;
1488		}
1489
1490	<	/* When connected at 10Mbps half-duplex, 82579 parts are excessively
1490	>	/* When connected at 10Mbps half-duplex, some parts are excessively
1491		* aggressive resulting in many collisions. To avoid this, increase
1492		* the IPG and reduce Rx latency in the PHY.
1493		*/
1494	<	if ((hw->mac.type == e1000_pch2lan) && link) {
1494	>	if (((hw->mac.type == e1000_pch2lan) ||
1495	>	(hw->mac.type == e1000_pch_lpt)) && link) {
1496		u32 reg;
1497		reg = E1000_READ_REG(hw, E1000_STATUS);
1498		if (!(reg & (E1000_STATUS_FD | E1000_STATUS_SPEED_MASK))) {
1499	+	u16 emi_addr;
1500	+
1501		reg = E1000_READ_REG(hw, E1000_TIPG);
1502		reg &= ~E1000_TIPG_IPGT_MASK;
1503		reg |= 0xFF;
#	Line 1136 | Line 1508 | static s32 e1000_check_for_copper_link_ich8lan(struct
1508		if (ret_val)
1509		return ret_val;
1510
1511	<	ret_val = e1000_write_emi_reg_locked(hw, I82579_RX_CONFIG, 0);
1511	>	if (hw->mac.type == e1000_pch2lan)
1512	>	emi_addr = I82579_RX_CONFIG;
1513	>	else
1514	>	emi_addr = I217_RX_CONFIG;
1515	>	ret_val = e1000_write_emi_reg_locked(hw, emi_addr, 0);
1516
1517		hw->phy.ops.release(hw);
1518
#	Line 1147 | Line 1523 | static s32 e1000_check_for_copper_link_ich8lan(struct
1523
1524		/* Work-around I218 hang issue */
1525		if ((hw->device_id == E1000_DEV_ID_PCH_LPTLP_I218_LM) ||
1526	<	(hw->device_id == E1000_DEV_ID_PCH_LPTLP_I218_V)) {
1526	>	(hw->device_id == E1000_DEV_ID_PCH_LPTLP_I218_V) ||
1527	>	(hw->device_id == E1000_DEV_ID_PCH_I218_LM3) ||
1528	>	(hw->device_id == E1000_DEV_ID_PCH_I218_V3)) {
1529		ret_val = e1000_k1_workaround_lpt_lp(hw, link);
1530		if (ret_val)
1531		return ret_val;
1532		}
1155	–
1533		if (hw->mac.type == e1000_pch_lpt) {
1534	<	/* Set platform power management values for Latency Tolerance
1535	<	* Reporting (LTR) and Optimized Buffer Flush/Fill (OBFF).
1534	>	/* Set platform power management values for
1535	>	* Latency Tolerance Reporting (LTR)
1536	>	* Optimized Buffer Flush/Fill (OBFF)
1537		*/
1538		ret_val = e1000_platform_pm_pch_lpt(hw, link);
1539		if (ret_val)
#	Line 1207 | Line 1585 | static s32 e1000_check_for_copper_link_ich8lan(struct
1585		e1000_check_downshift_generic(hw);
1586
1587		/* Enable/Disable EEE after link up */
1588	<	ret_val = e1000_set_eee_pchlan(hw);
1589	<	if (ret_val)
1590	<	return ret_val;
1588	>	if (hw->phy.type > e1000_phy_82579) {
1589	>	ret_val = e1000_set_eee_pchlan(hw);
1590	>	if (ret_val)
1591	>	return ret_val;
1592	>	}
1593
1594		/* If we are forcing speed/duplex, then we simply return since
1595		* we have already determined whether we have link or not.
#	Line 1433 | Line 1813 | static bool e1000_check_mng_mode_pchlan(struct e1000_h
1813		*  contain the MAC address but RAR[1-6] are reserved for manageability (ME).
1814		*  Use SHRA[0-3] in place of those reserved for ME.
1815		**/
1816	<	static void e1000_rar_set_pch2lan(struct e1000_hw *hw, u8 *addr, u32 index)
1816	>	static int e1000_rar_set_pch2lan(struct e1000_hw *hw, u8 *addr, u32 index)
1817		{
1818		u32 rar_low, rar_high;
1819
#	Line 1457 | Line 1837 | static void e1000_rar_set_pch2lan(struct e1000_hw *hw,
1837		E1000_WRITE_FLUSH(hw);
1838		E1000_WRITE_REG(hw, E1000_RAH(index), rar_high);
1839		E1000_WRITE_FLUSH(hw);
1840	<	return;
1840	>	return E1000_SUCCESS;
1841		}
1842
1843	<	if (index < hw->mac.rar_entry_count) {
1843	>	/* RAR[1-6] are owned by manageability.  Skip those and program the
1844	>	* next address into the SHRA register array.
1845	>	*/
1846	>	if (index < (u32) (hw->mac.rar_entry_count)) {
1847		s32 ret_val;
1848
1849		ret_val = e1000_acquire_swflag_ich8lan(hw);
#	Line 1477 | Line 1860 | static void e1000_rar_set_pch2lan(struct e1000_hw *hw,
1860		/* verify the register updates */
1861		if ((E1000_READ_REG(hw, E1000_SHRAL(index - 1)) == rar_low) &&
1862		(E1000_READ_REG(hw, E1000_SHRAH(index - 1)) == rar_high))
1863	<	return;
1863	>	return E1000_SUCCESS;
1864
1865		DEBUGOUT2("SHRA[%d] might be locked by ME - FWSM=0x%8.8x\n",
1866		(index - 1), E1000_READ_REG(hw, E1000_FWSM));
#	Line 1485 | Line 1868 | static void e1000_rar_set_pch2lan(struct e1000_hw *hw,
1868
1869		out:
1870		DEBUGOUT1("Failed to write receive address at index %d\n", index);
1871	+	return -E1000_ERR_CONFIG;
1872		}
1873
1874		/**
#	Line 1498 | Line 1882 | out:
1882		*  contain the MAC address. SHRA[0-10] are the shared receive address
1883		*  registers that are shared between the Host and manageability engine (ME).
1884		**/
1885	<	static void e1000_rar_set_pch_lpt(struct e1000_hw *hw, u8 *addr, u32 index)
1885	>	static int e1000_rar_set_pch_lpt(struct e1000_hw *hw, u8 *addr, u32 index)
1886		{
1887		u32 rar_low, rar_high;
1888		u32 wlock_mac;
#	Line 1522 | Line 1906 | static void e1000_rar_set_pch_lpt(struct e1000_hw *hw,
1906		E1000_WRITE_FLUSH(hw);
1907		E1000_WRITE_REG(hw, E1000_RAH(index), rar_high);
1908		E1000_WRITE_FLUSH(hw);
1909	<	return;
1909	>	return E1000_SUCCESS;
1910		}
1911
1912		/* The manageability engine (ME) can lock certain SHRAR registers that
#	Line 1557 | Line 1941 | static void e1000_rar_set_pch_lpt(struct e1000_hw *hw,
1941		/* verify the register updates */
1942		if ((E1000_READ_REG(hw, E1000_SHRAL_PCH_LPT(index - 1)) == rar_low) &&
1943		(E1000_READ_REG(hw, E1000_SHRAH_PCH_LPT(index - 1)) == rar_high))
1944	<	return;
1944	>	return E1000_SUCCESS;
1945		}
1946		}
1947
1948		out:
1949		DEBUGOUT1("Failed to write receive address at index %d\n", index);
1950	+	return -E1000_ERR_CONFIG;
1951		}
1952
1953		/**
#	Line 1620 | Line 2005 | release:
2005		static s32 e1000_check_reset_block_ich8lan(struct e1000_hw *hw)
2006		{
2007		u32 fwsm;
2008	+	bool blocked = FALSE;
2009	+	int i = 0;
2010
2011		DEBUGFUNC("e1000_check_reset_block_ich8lan");
2012
2013	<	fwsm = E1000_READ_REG(hw, E1000_FWSM);
2014	<
2015	<	return (fwsm & E1000_ICH_FWSM_RSPCIPHY) ? E1000_SUCCESS
2016	<	: E1000_BLK_PHY_RESET;
2013	>	do {
2014	>	fwsm = E1000_READ_REG(hw, E1000_FWSM);
2015	>	if (!(fwsm & E1000_ICH_FWSM_RSPCIPHY)) {
2016	>	blocked = TRUE;
2017	>	msec_delay(10);
2018	>	continue;
2019	>	}
2020	>	blocked = FALSE;
2021	>	} while (blocked && (i++ < 10));
2022	>	return blocked ? E1000_BLK_PHY_RESET : E1000_SUCCESS;
2023		}
2024
2025		/**
#	Line 1826 | Line 2219 | static s32 e1000_k1_gig_workaround_hv(struct e1000_hw
2219		if (ret_val)
2220		goto release;
2221
2222	<	status_reg &= BM_CS_STATUS_LINK_UP |
2223	<	BM_CS_STATUS_RESOLVED |
2224	<	BM_CS_STATUS_SPEED_MASK;
2222	>	status_reg &= (BM_CS_STATUS_LINK_UP |
2223	>	BM_CS_STATUS_RESOLVED |
2224	>	BM_CS_STATUS_SPEED_MASK);
2225
2226		if (status_reg == (BM_CS_STATUS_LINK_UP |
2227		BM_CS_STATUS_RESOLVED |
#	Line 1842 | Line 2235 | static s32 e1000_k1_gig_workaround_hv(struct e1000_hw
2235		if (ret_val)
2236		goto release;
2237
2238	<	status_reg &= HV_M_STATUS_LINK_UP |
2239	<	HV_M_STATUS_AUTONEG_COMPLETE |
2240	<	HV_M_STATUS_SPEED_MASK;
2238	>	status_reg &= (HV_M_STATUS_LINK_UP |
2239	>	HV_M_STATUS_AUTONEG_COMPLETE |
2240	>	HV_M_STATUS_SPEED_MASK);
2241
2242		if (status_reg == (HV_M_STATUS_LINK_UP |
2243		HV_M_STATUS_AUTONEG_COMPLETE |
#	Line 2126 | Line 2519 | void e1000_copy_rx_addrs_to_phy_ich8lan(struct e1000_h
2519		if (ret_val)
2520		goto release;
2521
2522	<	/* Copy both RAL/H (rar_entry_count) and SHRAL/H (+4) to PHY */
2523	<	for (i = 0; i < (hw->mac.rar_entry_count + 4); i++) {
2522	>	/* Copy both RAL/H (rar_entry_count) and SHRAL/H to PHY */
2523	>	for (i = 0; i < (hw->mac.rar_entry_count); i++) {
2524		mac_reg = E1000_READ_REG(hw, E1000_RAL(i));
2525		hw->phy.ops.write_reg_page(hw, BM_RAR_L(i),
2526		(u16)(mac_reg & 0xFFFF));
#	Line 2192 | Line 2585 | s32 e1000_lv_jumbo_workaround_ich8lan(struct e1000_hw
2585		return ret_val;
2586
2587		if (enable) {
2588	<	/* Write Rx addresses (rar_entry_count for RAL/H, +4 for
2588	>	/* Write Rx addresses (rar_entry_count for RAL/H, and
2589		* SHRAL/H) and initial CRC values to the MAC
2590		*/
2591	<	for (i = 0; i < (hw->mac.rar_entry_count + 4); i++) {
2591	>	for (i = 0; i < hw->mac.rar_entry_count; i++) {
2592		u8 mac_addr[ETH_ADDR_LEN] = {0};
2593		u32 addr_high, addr_low;
2594
#	Line 2264 | Line 2657 | s32 e1000_lv_jumbo_workaround_ich8lan(struct e1000_hw
2657		return ret_val;
2658		hw->phy.ops.read_reg(hw, PHY_REG(776, 20), &data);
2659		data &= ~(0x3FF << 2);
2660	<	data |= (0x1A << 2);
2660	>	data |= (E1000_TX_PTR_GAP << 2);
2661		ret_val = hw->phy.ops.write_reg(hw, PHY_REG(776, 20), data);
2662		if (ret_val)
2663		return ret_val;
#	Line 2378 | Line 2771 | release:
2771		*  e1000_k1_gig_workaround_lv - K1 Si workaround
2772		*  @hw:   pointer to the HW structure
2773		*
2774	<	*  Workaround to set the K1 beacon duration for 82579 parts
2774	>	*  Workaround to set the K1 beacon duration for 82579 parts in 10Mbps
2775	>	*  Disable K1 for 1000 and 100 speeds
2776		**/
2777		static s32 e1000_k1_workaround_lv(struct e1000_hw *hw)
2778		{
2779		s32 ret_val = E1000_SUCCESS;
2780		u16 status_reg = 0;
2387	–	u32 mac_reg;
2388	–	u16 phy_reg;
2781
2782		DEBUGFUNC("e1000_k1_workaround_lv");
2783
2784		if (hw->mac.type != e1000_pch2lan)
2785		return E1000_SUCCESS;
2786
2787	<	/* Set K1 beacon duration based on 1Gbps speed or otherwise */
2787	>	/* Set K1 beacon duration based on 10Mbs speed */
2788		ret_val = hw->phy.ops.read_reg(hw, HV_M_STATUS, &status_reg);
2789		if (ret_val)
2790		return ret_val;
2791
2792		if ((status_reg & (HV_M_STATUS_LINK_UP | HV_M_STATUS_AUTONEG_COMPLETE))
2793		== (HV_M_STATUS_LINK_UP | HV_M_STATUS_AUTONEG_COMPLETE)) {
2794	<	mac_reg = E1000_READ_REG(hw, E1000_FEXTNVM4);
2795	<	mac_reg &= ~E1000_FEXTNVM4_BEACON_DURATION_MASK;
2404	<
2405	<	ret_val = hw->phy.ops.read_reg(hw, I82579_LPI_CTRL, &phy_reg);
2406	<	if (ret_val)
2407	<	return ret_val;
2408	<
2409	<	if (status_reg & HV_M_STATUS_SPEED_1000) {
2794	>	if (status_reg &
2795	>	(HV_M_STATUS_SPEED_1000 | HV_M_STATUS_SPEED_100)) {
2796		u16 pm_phy_reg;
2797
2798	<	mac_reg |= E1000_FEXTNVM4_BEACON_DURATION_8USEC;
2413	<	phy_reg &= ~I82579_LPI_CTRL_FORCE_PLL_LOCK_COUNT;
2414	<	/* LV 1G Packet drop issue wa  */
2798	>	/* LV 1G/100 Packet drop issue wa  */
2799		ret_val = hw->phy.ops.read_reg(hw, HV_PM_CTRL,
2800		&pm_phy_reg);
2801		if (ret_val)
2802		return ret_val;
2803	<	pm_phy_reg &= ~HV_PM_CTRL_PLL_STOP_IN_K1_GIGA;
2803	>	pm_phy_reg &= ~HV_PM_CTRL_K1_ENABLE;
2804		ret_val = hw->phy.ops.write_reg(hw, HV_PM_CTRL,
2805		pm_phy_reg);
2806		if (ret_val)
2807		return ret_val;
2808		} else {
2809	+	u32 mac_reg;
2810	+	mac_reg = E1000_READ_REG(hw, E1000_FEXTNVM4);
2811	+	mac_reg &= ~E1000_FEXTNVM4_BEACON_DURATION_MASK;
2812		mac_reg |= E1000_FEXTNVM4_BEACON_DURATION_16USEC;
2813	<	phy_reg |= I82579_LPI_CTRL_FORCE_PLL_LOCK_COUNT;
2813	>	E1000_WRITE_REG(hw, E1000_FEXTNVM4, mac_reg);
2814		}
2428	–	E1000_WRITE_REG(hw, E1000_FEXTNVM4, mac_reg);
2429	–	ret_val = hw->phy.ops.write_reg(hw, I82579_LPI_CTRL, phy_reg);
2815		}
2816
2817		return ret_val;
#	Line 2963 | Line 3348 | static s32 e1000_flash_cycle_init_ich8lan(struct e1000
3348		/* Clear FCERR and DAEL in hw status by writing 1 */
3349		hsfsts.hsf_status.flcerr = 1;
3350		hsfsts.hsf_status.dael = 1;
2966	–
3351		E1000_WRITE_FLASH_REG16(hw, ICH_FLASH_HSFSTS, hsfsts.regval);
3352
3353		/* Either we should have a hardware SPI cycle in progress
#	Line 3030 | Line 3414 | static s32 e1000_flash_cycle_ich8lan(struct e1000_hw *
3414		/* Start a cycle by writing 1 in Flash Cycle Go in Hw Flash Control */
3415		hsflctl.regval = E1000_READ_FLASH_REG16(hw, ICH_FLASH_HSFCTL);
3416		hsflctl.hsf_ctrl.flcgo = 1;
3417	+
3418		E1000_WRITE_FLASH_REG16(hw, ICH_FLASH_HSFCTL, hsflctl.regval);
3419
3420		/* wait till FDONE bit is set to 1 */
#	Line 3084 | Line 3469 | static s32 e1000_read_flash_byte_ich8lan(struct e1000_
3469		u16 word = 0;
3470
3471		ret_val = e1000_read_flash_data_ich8lan(hw, offset, 1, &word);
3472	+
3473		if (ret_val)
3474		return ret_val;
3475
#	Line 3113 | Line 3499 | static s32 e1000_read_flash_data_ich8lan(struct e1000_
3499
3500		DEBUGFUNC("e1000_read_flash_data_ich8lan");
3501
3502	<	if (size < 1  || size > 2 || offset > ICH_FLASH_LINEAR_ADDR_MASK)
3502	>	if (size < 1 || size > 2 || offset > ICH_FLASH_LINEAR_ADDR_MASK)
3503		return -E1000_ERR_NVM;
3504	+	flash_linear_addr = ((ICH_FLASH_LINEAR_ADDR_MASK & offset) +
3505	+	hw->nvm.flash_base_addr);
3506
3119	–	flash_linear_addr = (ICH_FLASH_LINEAR_ADDR_MASK & offset) +
3120	–	hw->nvm.flash_base_addr;
3121	–
3507		do {
3508		usec_delay(1);
3509		/* Steps */
3510		ret_val = e1000_flash_cycle_init_ich8lan(hw);
3511		if (ret_val != E1000_SUCCESS)
3512		break;
3128	–
3513		hsflctl.regval = E1000_READ_FLASH_REG16(hw, ICH_FLASH_HSFCTL);
3514	+
3515		/* 0b/1b corresponds to 1 or 2 byte size, respectively. */
3516		hsflctl.hsf_ctrl.fldbcount = size - 1;
3517		hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_READ;
3518		E1000_WRITE_FLASH_REG16(hw, ICH_FLASH_HSFCTL, hsflctl.regval);
3134	–
3519		E1000_WRITE_FLASH_REG(hw, ICH_FLASH_FADDR, flash_linear_addr);
3520
3521		ret_val = e1000_flash_cycle_ich8lan(hw,
#	Line 3170 | Line 3554 | static s32 e1000_read_flash_data_ich8lan(struct e1000_
3554		return ret_val;
3555		}
3556
3557	+
3558		/**
3559		*  e1000_write_nvm_ich8lan - Write word(s) to the NVM
3560		*  @hw: pointer to the HW structure
#	Line 3223 | Line 3608 | static s32 e1000_update_nvm_checksum_ich8lan(struct e1
3608		struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
3609		u32 i, act_offset, new_bank_offset, old_bank_offset, bank;
3610		s32 ret_val;
3611	<	u16 data;
3611	>	u16 data = 0;
3612
3613		DEBUGFUNC("e1000_update_nvm_checksum_ich8lan");
3614
#	Line 3259 | Line 3644 | static s32 e1000_update_nvm_checksum_ich8lan(struct e1
3644		if (ret_val)
3645		goto release;
3646		}
3262	–
3647		for (i = 0; i < E1000_SHADOW_RAM_WORDS; i++) {
3264	–	/* Determine whether to write the value stored
3265	–	* in the other NVM bank or a modified value stored
3266	–	* in the shadow RAM
3267	–	*/
3648		if (dev_spec->shadow_ram[i].modified) {
3649		data = dev_spec->shadow_ram[i].value;
3650		} else {
#	Line 3274 | Line 3654 | static s32 e1000_update_nvm_checksum_ich8lan(struct e1
3654		if (ret_val)
3655		break;
3656		}
3277	–
3657		/* If the word is 0x13, then make sure the signature bits
3658		* (15:14) are 11b until the commit has completed.
3659		* This will allow us to write 10b which indicates the
#	Line 3289 | Line 3668 | static s32 e1000_update_nvm_checksum_ich8lan(struct e1
3668		act_offset = (i + new_bank_offset) << 1;
3669
3670		usec_delay(100);
3671	+
3672		/* Write the bytes to the new bank. */
3673		ret_val = e1000_retry_write_flash_byte_ich8lan(hw,
3674		act_offset,
#	Line 3302 | Line 3682 | static s32 e1000_update_nvm_checksum_ich8lan(struct e1
3682		(u8)(data >> 8));
3683		if (ret_val)
3684		break;
3685	<	}
3685	>	}
3686
3687		/* Don't bother writing the segment valid bits if sector
3688		* programming failed.
#	Line 3323 | Line 3703 | static s32 e1000_update_nvm_checksum_ich8lan(struct e1
3703		goto release;
3704
3705		data &= 0xBFFF;
3706	<	ret_val = e1000_retry_write_flash_byte_ich8lan(hw,
3327	<	act_offset * 2 + 1,
3706	>	ret_val = e1000_retry_write_flash_byte_ich8lan(hw, act_offset * 2 + 1,
3707		(u8)(data >> 8));
3708		if (ret_val)
3709		goto release;
#	Line 3335 | Line 3714 | static s32 e1000_update_nvm_checksum_ich8lan(struct e1
3714		* to 1's. We can write 1's to 0's without an erase
3715		*/
3716		act_offset = (old_bank_offset + E1000_ICH_NVM_SIG_WORD) * 2 + 1;
3717	+
3718		ret_val = e1000_retry_write_flash_byte_ich8lan(hw, act_offset, 0);
3719	+
3720		if (ret_val)
3721		goto release;
3722
#	Line 3434 | Line 3815 | static s32 e1000_write_flash_data_ich8lan(struct e1000
3815
3816		DEBUGFUNC("e1000_write_ich8_data");
3817
3818	<	if (size < 1 || size > 2 || data > size * 0xff ||
3438	<	offset > ICH_FLASH_LINEAR_ADDR_MASK)
3818	>	if (size < 1 || size > 2 || offset > ICH_FLASH_LINEAR_ADDR_MASK)
3819		return -E1000_ERR_NVM;
3820
3821	<	flash_linear_addr = (ICH_FLASH_LINEAR_ADDR_MASK & offset) +
3822	<	hw->nvm.flash_base_addr;
3821	>	flash_linear_addr = ((ICH_FLASH_LINEAR_ADDR_MASK & offset) +
3822	>	hw->nvm.flash_base_addr);
3823
3824		do {
3825		usec_delay(1);
#	Line 3447 | Line 3827 | static s32 e1000_write_flash_data_ich8lan(struct e1000
3827		ret_val = e1000_flash_cycle_init_ich8lan(hw);
3828		if (ret_val != E1000_SUCCESS)
3829		break;
3450	–
3830		hsflctl.regval = E1000_READ_FLASH_REG16(hw, ICH_FLASH_HSFCTL);
3831	+
3832		/* 0b/1b corresponds to 1 or 2 byte size, respectively. */
3833		hsflctl.hsf_ctrl.fldbcount = size - 1;
3834		hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_WRITE;
#	Line 3466 | Line 3846 | static s32 e1000_write_flash_data_ich8lan(struct e1000
3846		/* check if FCERR is set to 1 , if set to 1, clear it
3847		* and try the whole sequence a few more times else done
3848		*/
3849	<	ret_val = e1000_flash_cycle_ich8lan(hw,
3850	<	ICH_FLASH_WRITE_COMMAND_TIMEOUT);
3849	>	ret_val =
3850	>	e1000_flash_cycle_ich8lan(hw,
3851	>	ICH_FLASH_WRITE_COMMAND_TIMEOUT);
3852		if (ret_val == E1000_SUCCESS)
3853		break;
3854
#	Line 3489 | Line 3870 | static s32 e1000_write_flash_data_ich8lan(struct e1000
3870		return ret_val;
3871		}
3872
3873	+
3874		/**
3875		*  e1000_write_flash_byte_ich8lan - Write a single byte to NVM
3876		*  @hw: pointer to the HW structure
#	Line 3507 | Line 3889 | static s32 e1000_write_flash_byte_ich8lan(struct e1000
3889		return e1000_write_flash_data_ich8lan(hw, offset, 1, word);
3890		}
3891
3892	+
3893	+
3894		/**
3895		*  e1000_retry_write_flash_byte_ich8lan - Writes a single byte to NVM
3896		*  @hw: pointer to the HW structure
#	Line 3603 | Line 3987 | static s32 e1000_erase_flash_bank_ich8lan(struct e1000
3987		flash_linear_addr = hw->nvm.flash_base_addr;
3988		flash_linear_addr += (bank) ? flash_bank_size : 0;
3989
3990	<	for (j = 0; j < iteration ; j++) {
3990	>	for (j = 0; j < iteration; j++) {
3991		do {
3992	+	u32 timeout = ICH_FLASH_ERASE_COMMAND_TIMEOUT;
3993	+
3994		/* Steps */
3995		ret_val = e1000_flash_cycle_init_ich8lan(hw);
3996		if (ret_val)
#	Line 3613 | Line 3999 | static s32 e1000_erase_flash_bank_ich8lan(struct e1000
3999		/* Write a value 11 (block Erase) in Flash
4000		* Cycle field in hw flash control
4001		*/
4002	<	hsflctl.regval = E1000_READ_FLASH_REG16(hw,
4003	<	ICH_FLASH_HSFCTL);
4002	>	hsflctl.regval =
4003	>	E1000_READ_FLASH_REG16(hw, ICH_FLASH_HSFCTL);
4004	>
4005		hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_ERASE;
4006		E1000_WRITE_FLASH_REG16(hw, ICH_FLASH_HSFCTL,
4007		hsflctl.regval);
#	Line 3627 | Line 4014 | static s32 e1000_erase_flash_bank_ich8lan(struct e1000
4014		E1000_WRITE_FLASH_REG(hw, ICH_FLASH_FADDR,
4015		flash_linear_addr);
4016
4017	<	ret_val = e1000_flash_cycle_ich8lan(hw,
3631	<	ICH_FLASH_ERASE_COMMAND_TIMEOUT);
4017	>	ret_val = e1000_flash_cycle_ich8lan(hw, timeout);
4018		if (ret_val == E1000_SUCCESS)
4019		break;
4020
#	Line 3755 | Line 4141 | static s32 e1000_id_led_init_pchlan(struct e1000_hw *h
4141		*  @hw: pointer to the HW structure
4142		*
4143		*  ICH8 use the PCI Express bus, but does not contain a PCI Express Capability
4144	<	*  register, so the bus width is hard coded.
4144	>	*  register, so the the bus width is hard coded.
4145		**/
4146		static s32 e1000_get_bus_info_ich8lan(struct e1000_hw *hw)
4147		{
#	Line 3948 | Line 4334 | static s32 e1000_init_hw_ich8lan(struct e1000_hw *hw)
4334
4335		/* Set the transmit descriptor write-back policy for both queues */
4336		txdctl = E1000_READ_REG(hw, E1000_TXDCTL(0));
4337	<	txdctl = (txdctl & ~E1000_TXDCTL_WTHRESH) |
4338	<	E1000_TXDCTL_FULL_TX_DESC_WB;
4339	<	txdctl = (txdctl & ~E1000_TXDCTL_PTHRESH) |
4340	<	E1000_TXDCTL_MAX_TX_DESC_PREFETCH;
4337	>	txdctl = ((txdctl & ~E1000_TXDCTL_WTHRESH) |
4338	>	E1000_TXDCTL_FULL_TX_DESC_WB);
4339	>	txdctl = ((txdctl & ~E1000_TXDCTL_PTHRESH) |
4340	>	E1000_TXDCTL_MAX_TX_DESC_PREFETCH);
4341		E1000_WRITE_REG(hw, E1000_TXDCTL(0), txdctl);
4342		txdctl = E1000_READ_REG(hw, E1000_TXDCTL(1));
4343	<	txdctl = (txdctl & ~E1000_TXDCTL_WTHRESH) |
4344	<	E1000_TXDCTL_FULL_TX_DESC_WB;
4345	<	txdctl = (txdctl & ~E1000_TXDCTL_PTHRESH) |
4346	<	E1000_TXDCTL_MAX_TX_DESC_PREFETCH;
4343	>	txdctl = ((txdctl & ~E1000_TXDCTL_WTHRESH) |
4344	>	E1000_TXDCTL_FULL_TX_DESC_WB);
4345	>	txdctl = ((txdctl & ~E1000_TXDCTL_PTHRESH) |
4346	>	E1000_TXDCTL_MAX_TX_DESC_PREFETCH);
4347		E1000_WRITE_REG(hw, E1000_TXDCTL(1), txdctl);
4348
4349		/* ICH8 has opposite polarity of no_snoop bits.
#	Line 4042 | Line 4428 | static void e1000_initialize_hw_bits_ich8lan(struct e1
4428		*/
4429		reg = E1000_READ_REG(hw, E1000_RFCTL);
4430		reg |= (E1000_RFCTL_NFSW_DIS | E1000_RFCTL_NFSR_DIS);
4431	+
4432		/* Disable IPv6 extension header parsing because some malformed
4433		* IPv6 headers can hang the Rx.
4434		*/
#	Line 4480 | Line 4867 | void e1000_suspend_workarounds_ich8lan(struct e1000_hw
4867		u16 phy_reg, device_id = hw->device_id;
4868
4869		if ((device_id == E1000_DEV_ID_PCH_LPTLP_I218_LM) ||
4870	<	(device_id == E1000_DEV_ID_PCH_LPTLP_I218_V)) {
4870	>	(device_id == E1000_DEV_ID_PCH_LPTLP_I218_V) ||
4871	>	(device_id == E1000_DEV_ID_PCH_I218_LM3) ||
4872	>	(device_id == E1000_DEV_ID_PCH_I218_V3)) {
4873		u32 fextnvm6 = E1000_READ_REG(hw, E1000_FEXTNVM6);
4874
4875		E1000_WRITE_REG(hw, E1000_FEXTNVM6,
#	Line 4503 | Line 4892 | void e1000_suspend_workarounds_ich8lan(struct e1000_hw
4892
4893		/* Disable LPLU if both link partners support 100BaseT
4894		* EEE and 100Full is advertised on both ends of the
4895	<	* link.
4895	>	* link, and enable Auto Enable LPI since there will
4896	>	* be no driver to enable LPI while in Sx.
4897		*/
4898		if ((eee_advert & I82579_EEE_100_SUPPORTED) &&
4899		(dev_spec->eee_lp_ability &
4900		I82579_EEE_100_SUPPORTED) &&
4901	<	(hw->phy.autoneg_advertised & ADVERTISE_100_FULL))
4901	>	(hw->phy.autoneg_advertised & ADVERTISE_100_FULL)) {
4902		phy_ctrl &= ~(E1000_PHY_CTRL_D0A_LPLU |
4903		E1000_PHY_CTRL_NOND0A_LPLU);
4904	+
4905	+	/* Set Auto Enable LPI after link up */
4906	+	hw->phy.ops.read_reg_locked(hw,
4907	+	I217_LPI_GPIO_CTRL,
4908	+	&phy_reg);
4909	+	phy_reg |= I217_LPI_GPIO_CTRL_AUTO_EN_LPI;
4910	+	hw->phy.ops.write_reg_locked(hw,
4911	+	I217_LPI_GPIO_CTRL,
4912	+	phy_reg);
4913	+	}
4914		}
4915
4916		/* For i217 Intel Rapid Start Technology support,
#	Line 4521 | Line 4921 | void e1000_suspend_workarounds_ich8lan(struct e1000_hw
4921		* The SMBus release must also be disabled on LCD reset.
4922		*/
4923		if (!(E1000_READ_REG(hw, E1000_FWSM) &
4924	<	E1000_ICH_FWSM_FW_VALID)) {
4924	>	E1000_ICH_FWSM_FW_VALID)) {
4925		/* Enable proxy to reset only on power good. */
4926		hw->phy.ops.read_reg_locked(hw, I217_PROXY_CTRL,
4927		&phy_reg);
#	Line 4613 | Line 5013 | void e1000_resume_workarounds_pchlan(struct e1000_hw *
5013		DEBUGOUT("Failed to setup iRST\n");
5014		return;
5015		}
5016	+
5017	+	/* Clear Auto Enable LPI after link up */
5018	+	hw->phy.ops.read_reg_locked(hw, I217_LPI_GPIO_CTRL, &phy_reg);
5019	+	phy_reg &= ~I217_LPI_GPIO_CTRL_AUTO_EN_LPI;
5020	+	hw->phy.ops.write_reg_locked(hw, I217_LPI_GPIO_CTRL, phy_reg);
5021
5022		if (!(E1000_READ_REG(hw, E1000_FWSM) &
5023		E1000_ICH_FWSM_FW_VALID)) {

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