i386/include/apicreg.h

/* $MidnightBSD$ */
/*-
 * Copyright (c) 1996, by Peter Wemm and Steve Passe
 * All rights reserved.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
 * are met:
 * 1. Redistributions of source code must retain the above copyright
 *    notice, this list of conditions and the following disclaimer.
 * 2. The name of the developer may NOT be used to endorse or promote products
 *    derived from this software without specific prior written permission.
 *
 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
 * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
 * SUCH DAMAGE.
 *
 * $FreeBSD: src/sys/i386/include/apicreg.h,v 1.28 2005/01/06 22:18:15 imp Exp $
 */

#ifndef _MACHINE_APICREG_H_
#define _MACHINE_APICREG_H_

/*
 * Local && I/O APIC definitions.
 */

/*
 * Pentium P54C+ Built-in APIC
 * (Advanced programmable Interrupt Controller)
 * 
 * Base Address of Built-in APIC in memory location
 * is 0xfee00000.
 * 
 * Map of APIC Registers:
 * 
 * Offset (hex)    Description                     Read/Write state
 * 000             Reserved
 * 010             Reserved
 * 020 ID          Local APIC ID                   R/W
 * 030 VER         Local APIC Version              R
 * 040             Reserved
 * 050             Reserved
 * 060             Reserved
 * 070             Reserved
 * 080             Task Priority Register          R/W
 * 090             Arbitration Priority Register   R
 * 0A0             Processor Priority Register     R
 * 0B0             EOI Register                    W
 * 0C0 RRR         Remote read                     R
 * 0D0             Logical Destination             R/W
 * 0E0             Destination Format Register     0..27 R;  28..31 R/W
 * 0F0 SVR         Spurious Interrupt Vector Reg.  0..3  R;  4..9   R/W
 * 100             ISR  000-031                    R
 * 110             ISR  032-063                    R
 * 120             ISR  064-095                    R
 * 130             ISR  095-128                    R
 * 140             ISR  128-159                    R
 * 150             ISR  160-191                    R
 * 160             ISR  192-223                    R
 * 170             ISR  224-255                    R
 * 180             TMR  000-031                    R
 * 190             TMR  032-063                    R
 * 1A0             TMR  064-095                    R
 * 1B0             TMR  095-128                    R
 * 1C0             TMR  128-159                    R
 * 1D0             TMR  160-191                    R
 * 1E0             TMR  192-223                    R
 * 1F0             TMR  224-255                    R
 * 200             IRR  000-031                    R
 * 210             IRR  032-063                    R
 * 220             IRR  064-095                    R
 * 230             IRR  095-128                    R
 * 240             IRR  128-159                    R
 * 250             IRR  160-191                    R
 * 260             IRR  192-223                    R
 * 270             IRR  224-255                    R
 * 280             Error Status Register           R
 * 290             Reserved
 * 2A0             Reserved
 * 2B0             Reserved
 * 2C0             Reserved
 * 2D0             Reserved
 * 2E0             Reserved
 * 2F0             Reserved
 * 300 ICR_LOW     Interrupt Command Reg. (0-31)   R/W
 * 310 ICR_HI      Interrupt Command Reg. (32-63)  R/W
 * 320             Local Vector Table (Timer)      R/W
 * 330             Local Vector Table (Thermal)    R/W (PIV+)
 * 340             Local Vector Table (Performance) R/W (P6+)
 * 350 LVT1        Local Vector Table (LINT0)      R/W
 * 360 LVT2        Local Vector Table (LINT1)      R/W
 * 370 LVT3        Local Vector Table (ERROR)      R/W
 * 380             Initial Count Reg. for Timer    R/W
 * 390             Current Count of Timer          R
 * 3A0             Reserved
 * 3B0             Reserved
 * 3C0             Reserved
 * 3D0             Reserved
 * 3E0             Timer Divide Configuration Reg. R/W
 * 3F0             Reserved
 */


/******************************************************************************
 * global defines, etc.
 */


/******************************************************************************
 * LOCAL APIC structure
 */

#ifndef LOCORE
#include <sys/types.h>

#define PAD3    int : 32; int : 32; int : 32
#define PAD4    int : 32; int : 32; int : 32; int : 32

struct LAPIC {
        /* reserved */          PAD4;
        /* reserved */          PAD4;
        u_int32_t id;           PAD3;
        u_int32_t version;      PAD3;
        /* reserved */          PAD4;
        /* reserved */          PAD4;
        /* reserved */          PAD4;
        /* reserved */          PAD4;
        u_int32_t tpr;          PAD3;
        u_int32_t apr;          PAD3;
        u_int32_t ppr;          PAD3;
        u_int32_t eoi;          PAD3;
        /* reserved */          PAD4;
        u_int32_t ldr;          PAD3;
        u_int32_t dfr;          PAD3;
        u_int32_t svr;          PAD3;
        u_int32_t isr0;         PAD3;
        u_int32_t isr1;         PAD3;
        u_int32_t isr2;         PAD3;
        u_int32_t isr3;         PAD3;
        u_int32_t isr4;         PAD3;
        u_int32_t isr5;         PAD3;
        u_int32_t isr6;         PAD3;
        u_int32_t isr7;         PAD3;
        u_int32_t tmr0;         PAD3;
        u_int32_t tmr1;         PAD3;
        u_int32_t tmr2;         PAD3;
        u_int32_t tmr3;         PAD3;
        u_int32_t tmr4;         PAD3;
        u_int32_t tmr5;         PAD3;
        u_int32_t tmr6;         PAD3;
        u_int32_t tmr7;         PAD3;
        u_int32_t irr0;         PAD3;
        u_int32_t irr1;         PAD3;
        u_int32_t irr2;         PAD3;
        u_int32_t irr3;         PAD3;
        u_int32_t irr4;         PAD3;
        u_int32_t irr5;         PAD3;
        u_int32_t irr6;         PAD3;
        u_int32_t irr7;         PAD3;
        u_int32_t esr;          PAD3;
        /* reserved */          PAD4;
        /* reserved */          PAD4;
        /* reserved */          PAD4;
        /* reserved */          PAD4;
        /* reserved */          PAD4;
        /* reserved */          PAD4;
        /* reserved */          PAD4;
        u_int32_t icr_lo;       PAD3;
        u_int32_t icr_hi;       PAD3;
        u_int32_t lvt_timer;    PAD3;
        u_int32_t lvt_thermal;  PAD3;
        u_int32_t lvt_pcint;    PAD3;
        u_int32_t lvt_lint0;    PAD3;
        u_int32_t lvt_lint1;    PAD3;
        u_int32_t lvt_error;    PAD3;
        u_int32_t icr_timer;    PAD3;
        u_int32_t ccr_timer;    PAD3;
        /* reserved */          PAD4;
        /* reserved */          PAD4;
        /* reserved */          PAD4;
        /* reserved */          PAD4;
        u_int32_t dcr_timer;    PAD3;
        /* reserved */          PAD4;
};

typedef struct LAPIC lapic_t;

/******************************************************************************
 * I/O APIC structure
 */

struct IOAPIC {
        u_int32_t ioregsel;     PAD3;
        u_int32_t iowin;        PAD3;
};

typedef struct IOAPIC ioapic_t;

#undef PAD4
#undef PAD3

#endif  /* !LOCORE */


/******************************************************************************
 * various code 'logical' values
 */

/******************************************************************************
 * LOCAL APIC defines
 */

/* default physical locations of LOCAL (CPU) APICs */
#define DEFAULT_APIC_BASE       0xfee00000

/* constants relating to APIC ID registers */
#define APIC_ID_MASK            0xff000000
#define APIC_ID_SHIFT           24
#define APIC_ID_CLUSTER         0xf0
#define APIC_ID_CLUSTER_ID      0x0f
#define APIC_MAX_CLUSTER        0xe
#define APIC_MAX_INTRACLUSTER_ID 3
#define APIC_ID_CLUSTER_SHIFT   4

/* fields in VER */
#define APIC_VER_VERSION        0x000000ff
#define APIC_VER_MAXLVT         0x00ff0000
#define MAXLVTSHIFT             16

/* fields in LDR */
#define APIC_LDR_RESERVED       0x00ffffff

/* fields in DFR */
#define APIC_DFR_RESERVED       0x0fffffff
#define APIC_DFR_MODEL_MASK     0xf0000000
#define APIC_DFR_MODEL_FLAT     0xf0000000
#define APIC_DFR_MODEL_CLUSTER  0x00000000

/* fields in SVR */
#define APIC_SVR_VECTOR         0x000000ff
#define APIC_SVR_VEC_PROG       0x000000f0
#define APIC_SVR_VEC_FIX        0x0000000f
#define APIC_SVR_ENABLE         0x00000100
# define APIC_SVR_SWDIS         0x00000000
# define APIC_SVR_SWEN          0x00000100
#define APIC_SVR_FOCUS          0x00000200
# define APIC_SVR_FEN           0x00000000
# define APIC_SVR_FDIS          0x00000200

/* fields in TPR */
#define APIC_TPR_PRIO           0x000000ff
# define APIC_TPR_INT           0x000000f0
# define APIC_TPR_SUB           0x0000000f


/* fields in ICR_LOW */
#define APIC_VECTOR_MASK        0x000000ff

#define APIC_DELMODE_MASK       0x00000700
# define APIC_DELMODE_FIXED     0x00000000
# define APIC_DELMODE_LOWPRIO   0x00000100
# define APIC_DELMODE_SMI       0x00000200
# define APIC_DELMODE_RR        0x00000300
# define APIC_DELMODE_NMI       0x00000400
# define APIC_DELMODE_INIT      0x00000500
# define APIC_DELMODE_STARTUP   0x00000600
# define APIC_DELMODE_RESV      0x00000700

#define APIC_DESTMODE_MASK      0x00000800
# define APIC_DESTMODE_PHY      0x00000000
# define APIC_DESTMODE_LOG      0x00000800

#define APIC_DELSTAT_MASK       0x00001000
# define APIC_DELSTAT_IDLE      0x00000000
# define APIC_DELSTAT_PEND      0x00001000

#define APIC_RESV1_MASK         0x00002000

#define APIC_LEVEL_MASK         0x00004000
# define APIC_LEVEL_DEASSERT    0x00000000
# define APIC_LEVEL_ASSERT      0x00004000

#define APIC_TRIGMOD_MASK       0x00008000
# define APIC_TRIGMOD_EDGE      0x00000000
# define APIC_TRIGMOD_LEVEL     0x00008000

#define APIC_RRSTAT_MASK        0x00030000
# define APIC_RRSTAT_INVALID    0x00000000
# define APIC_RRSTAT_INPROG     0x00010000
# define APIC_RRSTAT_VALID      0x00020000
# define APIC_RRSTAT_RESV       0x00030000

#define APIC_DEST_MASK          0x000c0000
# define APIC_DEST_DESTFLD      0x00000000
# define APIC_DEST_SELF         0x00040000
# define APIC_DEST_ALLISELF     0x00080000
# define APIC_DEST_ALLESELF     0x000c0000

#define APIC_RESV2_MASK         0xfff00000

#define APIC_ICRLO_RESV_MASK    (APIC_RESV1_MASK | APIC_RESV2_MASK)

/* fields in LVT1/2 */
#define APIC_LVT_VECTOR         0x000000ff
#define APIC_LVT_DM             0x00000700
# define APIC_LVT_DM_FIXED      0x00000000
# define APIC_LVT_DM_SMI        0x00000200
# define APIC_LVT_DM_NMI        0x00000400
# define APIC_LVT_DM_INIT       0x00000500
# define APIC_LVT_DM_EXTINT     0x00000700
#define APIC_LVT_DS             0x00001000
#define APIC_LVT_IIPP           0x00002000
#define APIC_LVT_IIPP_INTALO    0x00002000
#define APIC_LVT_IIPP_INTAHI    0x00000000
#define APIC_LVT_RIRR           0x00004000
#define APIC_LVT_TM             0x00008000
#define APIC_LVT_M              0x00010000


/* fields in LVT Timer */
#define APIC_LVTT_VECTOR        0x000000ff
#define APIC_LVTT_DS            0x00001000
#define APIC_LVTT_M             0x00010000
#define APIC_LVTT_TM            0x00020000
# define APIC_LVTT_TM_ONE_SHOT  0x00000000
# define APIC_LVTT_TM_PERIODIC  0x00020000


/* APIC timer current count */
#define APIC_TIMER_MAX_COUNT    0xffffffff

/* fields in TDCR */
#define APIC_TDCR_2             0x00
#define APIC_TDCR_4             0x01
#define APIC_TDCR_8             0x02
#define APIC_TDCR_16            0x03
#define APIC_TDCR_32            0x08
#define APIC_TDCR_64            0x09
#define APIC_TDCR_128           0x0a
#define APIC_TDCR_1             0x0b

/******************************************************************************
 * I/O APIC defines
 */

/* default physical locations of an IO APIC */
#define DEFAULT_IO_APIC_BASE    0xfec00000

/* window register offset */
#define IOAPIC_WINDOW           0x10

/* indexes into IO APIC */
#define IOAPIC_ID               0x00
#define IOAPIC_VER              0x01
#define IOAPIC_ARB              0x02
#define IOAPIC_REDTBL           0x10
#define IOAPIC_REDTBL0          IOAPIC_REDTBL
#define IOAPIC_REDTBL1          (IOAPIC_REDTBL+0x02)
#define IOAPIC_REDTBL2          (IOAPIC_REDTBL+0x04)
#define IOAPIC_REDTBL3          (IOAPIC_REDTBL+0x06)
#define IOAPIC_REDTBL4          (IOAPIC_REDTBL+0x08)
#define IOAPIC_REDTBL5          (IOAPIC_REDTBL+0x0a)
#define IOAPIC_REDTBL6          (IOAPIC_REDTBL+0x0c)
#define IOAPIC_REDTBL7          (IOAPIC_REDTBL+0x0e)
#define IOAPIC_REDTBL8          (IOAPIC_REDTBL+0x10)
#define IOAPIC_REDTBL9          (IOAPIC_REDTBL+0x12)
#define IOAPIC_REDTBL10         (IOAPIC_REDTBL+0x14)
#define IOAPIC_REDTBL11         (IOAPIC_REDTBL+0x16)
#define IOAPIC_REDTBL12         (IOAPIC_REDTBL+0x18)
#define IOAPIC_REDTBL13         (IOAPIC_REDTBL+0x1a)
#define IOAPIC_REDTBL14         (IOAPIC_REDTBL+0x1c)
#define IOAPIC_REDTBL15         (IOAPIC_REDTBL+0x1e)
#define IOAPIC_REDTBL16         (IOAPIC_REDTBL+0x20)
#define IOAPIC_REDTBL17         (IOAPIC_REDTBL+0x22)
#define IOAPIC_REDTBL18         (IOAPIC_REDTBL+0x24)
#define IOAPIC_REDTBL19         (IOAPIC_REDTBL+0x26)
#define IOAPIC_REDTBL20         (IOAPIC_REDTBL+0x28)
#define IOAPIC_REDTBL21         (IOAPIC_REDTBL+0x2a)
#define IOAPIC_REDTBL22         (IOAPIC_REDTBL+0x2c)
#define IOAPIC_REDTBL23         (IOAPIC_REDTBL+0x2e)

/* fields in VER */
#define IOART_VER_VERSION       0x000000ff
#define IOART_VER_MAXREDIR      0x00ff0000
#define MAXREDIRSHIFT           16

/*
 * fields in the IO APIC's redirection table entries
 */
#define IOART_DEST      APIC_ID_MASK    /* broadcast addr: all APICs */

#define IOART_RESV      0x00fe0000      /* reserved */

#define IOART_INTMASK   0x00010000      /* R/W: INTerrupt mask */
# define IOART_INTMCLR  0x00000000      /*       clear, allow INTs */
# define IOART_INTMSET  0x00010000      /*       set, inhibit INTs */

#define IOART_TRGRMOD   0x00008000      /* R/W: trigger mode */
# define IOART_TRGREDG  0x00000000      /*       edge */
# define IOART_TRGRLVL  0x00008000      /*       level */

#define IOART_REM_IRR   0x00004000      /* RO: remote IRR */

#define IOART_INTPOL    0x00002000      /* R/W: INT input pin polarity */
# define IOART_INTAHI   0x00000000      /*      active high */
# define IOART_INTALO   0x00002000      /*      active low */

#define IOART_DELIVS    0x00001000      /* RO: delivery status */

#define IOART_DESTMOD   0x00000800      /* R/W: destination mode */
# define IOART_DESTPHY  0x00000000      /*      physical */
# define IOART_DESTLOG  0x00000800      /*      logical */

#define IOART_DELMOD    0x00000700      /* R/W: delivery mode */
# define IOART_DELFIXED 0x00000000      /*       fixed */
# define IOART_DELLOPRI 0x00000100      /*       lowest priority */
# define IOART_DELSMI   0x00000200      /*       System Management INT */
# define IOART_DELRSV1  0x00000300      /*       reserved */
# define IOART_DELNMI   0x00000400      /*       NMI signal */
# define IOART_DELINIT  0x00000500      /*       INIT signal */
# define IOART_DELRSV2  0x00000600      /*       reserved */
# define IOART_DELEXINT 0x00000700      /*       External INTerrupt */

#define IOART_INTVEC    0x000000ff      /* R/W: INTerrupt vector field */

#endif /* _MACHINE_APICREG_H_ */
Revision:	4776
Committed:	Sat Mar 31 17:05:11 2012 UTC (12 years, 1 month ago) by laffer1
Content type:	text/plain
File size:	14066 byte(s)
Log Message:	Bring in several improvements from OpenSolaris for dtrace, zfs, etc. Add kernel code for kernel lock manager for nfs, vfs and vm improvements and general compatibility with the recent network stack changes. Bring in several improvements and bugfixes from FreeBSD 7.1 Tag $MidnightBSD$
#	Content
1	/* $MidnightBSD$ */
2	/*-
3	* Copyright (c) 1996, by Peter Wemm and Steve Passe
4	* All rights reserved.
5	*
6	* Redistribution and use in source and binary forms, with or without
7	* modification, are permitted provided that the following conditions
8	* are met:
9	* 1. Redistributions of source code must retain the above copyright
10	* notice, this list of conditions and the following disclaimer.
11	* 2. The name of the developer may NOT be used to endorse or promote products
12	* derived from this software without specific prior written permission.
13	*
14	* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
15	* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17	* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
18	* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19	* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20	* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21	* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22	* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23	* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
24	* SUCH DAMAGE.
25	*
26	* $FreeBSD: src/sys/i386/include/apicreg.h,v 1.28 2005/01/06 22:18:15 imp Exp $
27	*/
28
29	#ifndef _MACHINE_APICREG_H_
30	#define _MACHINE_APICREG_H_
31
32	/*
33	* Local && I/O APIC definitions.
34	*/
35
36	/*
37	* Pentium P54C+ Built-in APIC
38	* (Advanced programmable Interrupt Controller)
39	*
40	* Base Address of Built-in APIC in memory location
41	* is 0xfee00000.
42	*
43	* Map of APIC Registers:
44	*
45	* Offset (hex) Description Read/Write state
46	* 000 Reserved
47	* 010 Reserved
48	* 020 ID Local APIC ID R/W
49	* 030 VER Local APIC Version R
50	* 040 Reserved
51	* 050 Reserved
52	* 060 Reserved
53	* 070 Reserved
54	* 080 Task Priority Register R/W
55	* 090 Arbitration Priority Register R
56	* 0A0 Processor Priority Register R
57	* 0B0 EOI Register W
58	* 0C0 RRR Remote read R
59	* 0D0 Logical Destination R/W
60	* 0E0 Destination Format Register 0..27 R; 28..31 R/W
61	* 0F0 SVR Spurious Interrupt Vector Reg. 0..3 R; 4..9 R/W
62	* 100 ISR 000-031 R
63	* 110 ISR 032-063 R
64	* 120 ISR 064-095 R
65	* 130 ISR 095-128 R
66	* 140 ISR 128-159 R
67	* 150 ISR 160-191 R
68	* 160 ISR 192-223 R
69	* 170 ISR 224-255 R
70	* 180 TMR 000-031 R
71	* 190 TMR 032-063 R
72	* 1A0 TMR 064-095 R
73	* 1B0 TMR 095-128 R
74	* 1C0 TMR 128-159 R
75	* 1D0 TMR 160-191 R
76	* 1E0 TMR 192-223 R
77	* 1F0 TMR 224-255 R
78	* 200 IRR 000-031 R
79	* 210 IRR 032-063 R
80	* 220 IRR 064-095 R
81	* 230 IRR 095-128 R
82	* 240 IRR 128-159 R
83	* 250 IRR 160-191 R
84	* 260 IRR 192-223 R
85	* 270 IRR 224-255 R
86	* 280 Error Status Register R
87	* 290 Reserved
88	* 2A0 Reserved
89	* 2B0 Reserved
90	* 2C0 Reserved
91	* 2D0 Reserved
92	* 2E0 Reserved
93	* 2F0 Reserved
94	* 300 ICR_LOW Interrupt Command Reg. (0-31) R/W
95	* 310 ICR_HI Interrupt Command Reg. (32-63) R/W
96	* 320 Local Vector Table (Timer) R/W
97	* 330 Local Vector Table (Thermal) R/W (PIV+)
98	* 340 Local Vector Table (Performance) R/W (P6+)
99	* 350 LVT1 Local Vector Table (LINT0) R/W
100	* 360 LVT2 Local Vector Table (LINT1) R/W
101	* 370 LVT3 Local Vector Table (ERROR) R/W
102	* 380 Initial Count Reg. for Timer R/W
103	* 390 Current Count of Timer R
104	* 3A0 Reserved
105	* 3B0 Reserved
106	* 3C0 Reserved
107	* 3D0 Reserved
108	* 3E0 Timer Divide Configuration Reg. R/W
109	* 3F0 Reserved
110	*/
111
112
113	/******************************************************************************
114	* global defines, etc.
115	*/
116
117
118	/******************************************************************************
119	* LOCAL APIC structure
120	*/
121
122	#ifndef LOCORE
123	#include <sys/types.h>
124
125	#define PAD3 int : 32; int : 32; int : 32
126	#define PAD4 int : 32; int : 32; int : 32; int : 32
127
128	struct LAPIC {
129	/* reserved */ PAD4;
130	/* reserved */ PAD4;
131	u_int32_t id; PAD3;
132	u_int32_t version; PAD3;
133	/* reserved */ PAD4;
134	/* reserved */ PAD4;
135	/* reserved */ PAD4;
136	/* reserved */ PAD4;
137	u_int32_t tpr; PAD3;
138	u_int32_t apr; PAD3;
139	u_int32_t ppr; PAD3;
140	u_int32_t eoi; PAD3;
141	/* reserved */ PAD4;
142	u_int32_t ldr; PAD3;
143	u_int32_t dfr; PAD3;
144	u_int32_t svr; PAD3;
145	u_int32_t isr0; PAD3;
146	u_int32_t isr1; PAD3;
147	u_int32_t isr2; PAD3;
148	u_int32_t isr3; PAD3;
149	u_int32_t isr4; PAD3;
150	u_int32_t isr5; PAD3;
151	u_int32_t isr6; PAD3;
152	u_int32_t isr7; PAD3;
153	u_int32_t tmr0; PAD3;
154	u_int32_t tmr1; PAD3;
155	u_int32_t tmr2; PAD3;
156	u_int32_t tmr3; PAD3;
157	u_int32_t tmr4; PAD3;
158	u_int32_t tmr5; PAD3;
159	u_int32_t tmr6; PAD3;
160	u_int32_t tmr7; PAD3;
161	u_int32_t irr0; PAD3;
162	u_int32_t irr1; PAD3;
163	u_int32_t irr2; PAD3;
164	u_int32_t irr3; PAD3;
165	u_int32_t irr4; PAD3;
166	u_int32_t irr5; PAD3;
167	u_int32_t irr6; PAD3;
168	u_int32_t irr7; PAD3;
169	u_int32_t esr; PAD3;
170	/* reserved */ PAD4;
171	/* reserved */ PAD4;
172	/* reserved */ PAD4;
173	/* reserved */ PAD4;
174	/* reserved */ PAD4;
175	/* reserved */ PAD4;
176	/* reserved */ PAD4;
177	u_int32_t icr_lo; PAD3;
178	u_int32_t icr_hi; PAD3;
179	u_int32_t lvt_timer; PAD3;
180	u_int32_t lvt_thermal; PAD3;
181	u_int32_t lvt_pcint; PAD3;
182	u_int32_t lvt_lint0; PAD3;
183	u_int32_t lvt_lint1; PAD3;
184	u_int32_t lvt_error; PAD3;
185	u_int32_t icr_timer; PAD3;
186	u_int32_t ccr_timer; PAD3;
187	/* reserved */ PAD4;
188	/* reserved */ PAD4;
189	/* reserved */ PAD4;
190	/* reserved */ PAD4;
191	u_int32_t dcr_timer; PAD3;
192	/* reserved */ PAD4;
193	};
194
195	typedef struct LAPIC lapic_t;
196
197	/******************************************************************************
198	* I/O APIC structure
199	*/
200
201	struct IOAPIC {
202	u_int32_t ioregsel; PAD3;
203	u_int32_t iowin; PAD3;
204	};
205
206	typedef struct IOAPIC ioapic_t;
207
208	#undef PAD4
209	#undef PAD3
210
211	#endif /* !LOCORE */
212
213
214	/******************************************************************************
215	* various code 'logical' values
216	*/
217
218	/******************************************************************************
219	* LOCAL APIC defines
220	*/
221
222	/* default physical locations of LOCAL (CPU) APICs */
223	#define DEFAULT_APIC_BASE 0xfee00000
224
225	/* constants relating to APIC ID registers */
226	#define APIC_ID_MASK 0xff000000
227	#define APIC_ID_SHIFT 24
228	#define APIC_ID_CLUSTER 0xf0
229	#define APIC_ID_CLUSTER_ID 0x0f
230	#define APIC_MAX_CLUSTER 0xe
231	#define APIC_MAX_INTRACLUSTER_ID 3
232	#define APIC_ID_CLUSTER_SHIFT 4
233
234	/* fields in VER */
235	#define APIC_VER_VERSION 0x000000ff
236	#define APIC_VER_MAXLVT 0x00ff0000
237	#define MAXLVTSHIFT 16
238
239	/* fields in LDR */
240	#define APIC_LDR_RESERVED 0x00ffffff
241
242	/* fields in DFR */
243	#define APIC_DFR_RESERVED 0x0fffffff
244	#define APIC_DFR_MODEL_MASK 0xf0000000
245	#define APIC_DFR_MODEL_FLAT 0xf0000000
246	#define APIC_DFR_MODEL_CLUSTER 0x00000000
247
248	/* fields in SVR */
249	#define APIC_SVR_VECTOR 0x000000ff
250	#define APIC_SVR_VEC_PROG 0x000000f0
251	#define APIC_SVR_VEC_FIX 0x0000000f
252	#define APIC_SVR_ENABLE 0x00000100
253	# define APIC_SVR_SWDIS 0x00000000
254	# define APIC_SVR_SWEN 0x00000100
255	#define APIC_SVR_FOCUS 0x00000200
256	# define APIC_SVR_FEN 0x00000000
257	# define APIC_SVR_FDIS 0x00000200
258
259	/* fields in TPR */
260	#define APIC_TPR_PRIO 0x000000ff
261	# define APIC_TPR_INT 0x000000f0
262	# define APIC_TPR_SUB 0x0000000f
263
264
265	/* fields in ICR_LOW */
266	#define APIC_VECTOR_MASK 0x000000ff
267
268	#define APIC_DELMODE_MASK 0x00000700
269	# define APIC_DELMODE_FIXED 0x00000000
270	# define APIC_DELMODE_LOWPRIO 0x00000100
271	# define APIC_DELMODE_SMI 0x00000200
272	# define APIC_DELMODE_RR 0x00000300
273	# define APIC_DELMODE_NMI 0x00000400
274	# define APIC_DELMODE_INIT 0x00000500
275	# define APIC_DELMODE_STARTUP 0x00000600
276	# define APIC_DELMODE_RESV 0x00000700
277
278	#define APIC_DESTMODE_MASK 0x00000800
279	# define APIC_DESTMODE_PHY 0x00000000
280	# define APIC_DESTMODE_LOG 0x00000800
281
282	#define APIC_DELSTAT_MASK 0x00001000
283	# define APIC_DELSTAT_IDLE 0x00000000
284	# define APIC_DELSTAT_PEND 0x00001000
285
286	#define APIC_RESV1_MASK 0x00002000
287
288	#define APIC_LEVEL_MASK 0x00004000
289	# define APIC_LEVEL_DEASSERT 0x00000000
290	# define APIC_LEVEL_ASSERT 0x00004000
291
292	#define APIC_TRIGMOD_MASK 0x00008000
293	# define APIC_TRIGMOD_EDGE 0x00000000
294	# define APIC_TRIGMOD_LEVEL 0x00008000
295
296	#define APIC_RRSTAT_MASK 0x00030000
297	# define APIC_RRSTAT_INVALID 0x00000000
298	# define APIC_RRSTAT_INPROG 0x00010000
299	# define APIC_RRSTAT_VALID 0x00020000
300	# define APIC_RRSTAT_RESV 0x00030000
301
302	#define APIC_DEST_MASK 0x000c0000
303	# define APIC_DEST_DESTFLD 0x00000000
304	# define APIC_DEST_SELF 0x00040000
305	# define APIC_DEST_ALLISELF 0x00080000
306	# define APIC_DEST_ALLESELF 0x000c0000
307
308	#define APIC_RESV2_MASK 0xfff00000
309
310	#define APIC_ICRLO_RESV_MASK (APIC_RESV1_MASK \| APIC_RESV2_MASK)
311
312	/* fields in LVT1/2 */
313	#define APIC_LVT_VECTOR 0x000000ff
314	#define APIC_LVT_DM 0x00000700
315	# define APIC_LVT_DM_FIXED 0x00000000
316	# define APIC_LVT_DM_SMI 0x00000200
317	# define APIC_LVT_DM_NMI 0x00000400
318	# define APIC_LVT_DM_INIT 0x00000500
319	# define APIC_LVT_DM_EXTINT 0x00000700
320	#define APIC_LVT_DS 0x00001000
321	#define APIC_LVT_IIPP 0x00002000
322	#define APIC_LVT_IIPP_INTALO 0x00002000
323	#define APIC_LVT_IIPP_INTAHI 0x00000000
324	#define APIC_LVT_RIRR 0x00004000
325	#define APIC_LVT_TM 0x00008000
326	#define APIC_LVT_M 0x00010000
327
328
329	/* fields in LVT Timer */
330	#define APIC_LVTT_VECTOR 0x000000ff
331	#define APIC_LVTT_DS 0x00001000
332	#define APIC_LVTT_M 0x00010000
333	#define APIC_LVTT_TM 0x00020000
334	# define APIC_LVTT_TM_ONE_SHOT 0x00000000
335	# define APIC_LVTT_TM_PERIODIC 0x00020000
336
337
338	/* APIC timer current count */
339	#define APIC_TIMER_MAX_COUNT 0xffffffff
340
341	/* fields in TDCR */
342	#define APIC_TDCR_2 0x00
343	#define APIC_TDCR_4 0x01
344	#define APIC_TDCR_8 0x02
345	#define APIC_TDCR_16 0x03
346	#define APIC_TDCR_32 0x08
347	#define APIC_TDCR_64 0x09
348	#define APIC_TDCR_128 0x0a
349	#define APIC_TDCR_1 0x0b
350
351	/******************************************************************************
352	* I/O APIC defines
353	*/
354
355	/* default physical locations of an IO APIC */
356	#define DEFAULT_IO_APIC_BASE 0xfec00000
357
358	/* window register offset */
359	#define IOAPIC_WINDOW 0x10
360
361	/* indexes into IO APIC */
362	#define IOAPIC_ID 0x00
363	#define IOAPIC_VER 0x01
364	#define IOAPIC_ARB 0x02
365	#define IOAPIC_REDTBL 0x10
366	#define IOAPIC_REDTBL0 IOAPIC_REDTBL
367	#define IOAPIC_REDTBL1 (IOAPIC_REDTBL+0x02)
368	#define IOAPIC_REDTBL2 (IOAPIC_REDTBL+0x04)
369	#define IOAPIC_REDTBL3 (IOAPIC_REDTBL+0x06)
370	#define IOAPIC_REDTBL4 (IOAPIC_REDTBL+0x08)
371	#define IOAPIC_REDTBL5 (IOAPIC_REDTBL+0x0a)
372	#define IOAPIC_REDTBL6 (IOAPIC_REDTBL+0x0c)
373	#define IOAPIC_REDTBL7 (IOAPIC_REDTBL+0x0e)
374	#define IOAPIC_REDTBL8 (IOAPIC_REDTBL+0x10)
375	#define IOAPIC_REDTBL9 (IOAPIC_REDTBL+0x12)
376	#define IOAPIC_REDTBL10 (IOAPIC_REDTBL+0x14)
377	#define IOAPIC_REDTBL11 (IOAPIC_REDTBL+0x16)
378	#define IOAPIC_REDTBL12 (IOAPIC_REDTBL+0x18)
379	#define IOAPIC_REDTBL13 (IOAPIC_REDTBL+0x1a)
380	#define IOAPIC_REDTBL14 (IOAPIC_REDTBL+0x1c)
381	#define IOAPIC_REDTBL15 (IOAPIC_REDTBL+0x1e)
382	#define IOAPIC_REDTBL16 (IOAPIC_REDTBL+0x20)
383	#define IOAPIC_REDTBL17 (IOAPIC_REDTBL+0x22)
384	#define IOAPIC_REDTBL18 (IOAPIC_REDTBL+0x24)
385	#define IOAPIC_REDTBL19 (IOAPIC_REDTBL+0x26)
386	#define IOAPIC_REDTBL20 (IOAPIC_REDTBL+0x28)
387	#define IOAPIC_REDTBL21 (IOAPIC_REDTBL+0x2a)
388	#define IOAPIC_REDTBL22 (IOAPIC_REDTBL+0x2c)
389	#define IOAPIC_REDTBL23 (IOAPIC_REDTBL+0x2e)
390
391	/* fields in VER */
392	#define IOART_VER_VERSION 0x000000ff
393	#define IOART_VER_MAXREDIR 0x00ff0000
394	#define MAXREDIRSHIFT 16
395
396	/*
397	* fields in the IO APIC's redirection table entries
398	*/
399	#define IOART_DEST APIC_ID_MASK /* broadcast addr: all APICs */
400
401	#define IOART_RESV 0x00fe0000 /* reserved */
402
403	#define IOART_INTMASK 0x00010000 /* R/W: INTerrupt mask */
404	# define IOART_INTMCLR 0x00000000 /* clear, allow INTs */
405	# define IOART_INTMSET 0x00010000 /* set, inhibit INTs */
406
407	#define IOART_TRGRMOD 0x00008000 /* R/W: trigger mode */
408	# define IOART_TRGREDG 0x00000000 /* edge */
409	# define IOART_TRGRLVL 0x00008000 /* level */
410
411	#define IOART_REM_IRR 0x00004000 /* RO: remote IRR */
412
413	#define IOART_INTPOL 0x00002000 /* R/W: INT input pin polarity */
414	# define IOART_INTAHI 0x00000000 /* active high */
415	# define IOART_INTALO 0x00002000 /* active low */
416
417	#define IOART_DELIVS 0x00001000 /* RO: delivery status */
418
419	#define IOART_DESTMOD 0x00000800 /* R/W: destination mode */
420	# define IOART_DESTPHY 0x00000000 /* physical */
421	# define IOART_DESTLOG 0x00000800 /* logical */
422
423	#define IOART_DELMOD 0x00000700 /* R/W: delivery mode */
424	# define IOART_DELFIXED 0x00000000 /* fixed */
425	# define IOART_DELLOPRI 0x00000100 /* lowest priority */
426	# define IOART_DELSMI 0x00000200 /* System Management INT */
427	# define IOART_DELRSV1 0x00000300 /* reserved */
428	# define IOART_DELNMI 0x00000400 /* NMI signal */
429	# define IOART_DELINIT 0x00000500 /* INIT signal */
430	# define IOART_DELRSV2 0x00000600 /* reserved */
431	# define IOART_DELEXINT 0x00000700 /* External INTerrupt */
432
433	#define IOART_INTVEC 0x000000ff /* R/W: INTerrupt vector field */
434
435	#endif /* _MACHINE_APICREG_H_ */