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Searched refs:ComplexPattern (Results 1 – 25 of 35) sorted by relevance

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/NextBSD/contrib/llvm/utils/TableGen/
HDCodeGenTarget.h198 class ComplexPattern {
205 ComplexPattern() : NumOperands(0) {} in ComplexPattern() function
206 ComplexPattern(Record *R);
HDDAGISelMatcherEmitter.cpp43 DenseMap<const ComplexPattern*, unsigned> ComplexPatternMap;
44 std::vector<const ComplexPattern*> ComplexPatterns;
81 unsigned getComplexPat(const ComplexPattern &P) { in getComplexPat()
401 const ComplexPattern &Pattern = CCPM->getPattern(); in EmitMatcher()
663 const ComplexPattern &P = *ComplexPatterns[i]; in EmitPredicateFunctions()
HDCodeGenDAGPatterns.h37 class ComplexPattern; variable
423 const ComplexPattern *
718 std::map<Record*, ComplexPattern, LessRecordByID> ComplexPatterns;
758 const ComplexPattern &getComplexPattern(Record *R) const { in getComplexPattern()
HDDAGISelMatcher.h25 class ComplexPattern; variable
719 const ComplexPattern &Pattern;
732 CheckComplexPatMatcher(const ComplexPattern &pattern, unsigned matchnumber, in CheckComplexPatMatcher()
737 const ComplexPattern &getPattern() const { return Pattern; } in getPattern()
HDCodeGenTarget.cpp385 ComplexPattern::ComplexPattern(Record *R) { in ComplexPattern() function in ComplexPattern
HDDAGISelMatcherGen.cpp507 if (const ComplexPattern *CP = in EmitMatcherCode()
547 const ComplexPattern &CP = *N->getComplexPatternInfo(CGP); in EmitMatcherCode()
HDCodeGenDAGPatterns.cpp800 const ComplexPattern *AM = P->getComplexPatternInfo(CGP); in getPatternSize()
1550 const ComplexPattern *
1568 if (const ComplexPattern *CP = getComplexPatternInfo(CGP)) in getNumMIResults()
1589 if (const ComplexPattern *CP = getComplexPatternInfo(CGP)) in NodeHasProperty()
2747 const ComplexPattern &CP = CDP.getComplexPattern(LeafRec); in AnalyzeNode()
3175 if (const ComplexPattern *CP = in AddPatternToMatch()
/NextBSD/contrib/llvm/lib/Target/Mips/
HDMicroMipsInstrInfo.td1 def addrimm12 : ComplexPattern<iPTR, 2, "selectIntAddrMM", [frameindex]>;
2 def addrimm4lsl2 : ComplexPattern<iPTR, 2, "selectIntAddrLSL2MM", [frameindex]>;
232 ComplexPattern Addr = addr> :
240 ComplexPattern Addr = addr> :
510 InstrItinClass Itin = NoItinerary, ComplexPattern Addr = addr> :
518 InstrItinClass Itin = NoItinerary, ComplexPattern Addr = addr> :
527 ComplexPattern Addr = addr> :
536 ComplexPattern Addr = addr> :
HDMipsInstrInfo.td583 ComplexPattern<iPTR, 2, "selectIntAddr", [frameindex]>;
586 ComplexPattern<iPTR, 2, "selectAddrRegImm", [frameindex]>;
589 ComplexPattern<iPTR, 2, "selectAddrRegReg", [frameindex]>;
592 ComplexPattern<iPTR, 2, "selectAddrDefault", [frameindex]>;
594 def addrimm10 : ComplexPattern<iPTR, 2, "selectIntAddrMSA", [frameindex]>;
670 InstrItinClass Itin = NoItinerary, ComplexPattern Addr = addr> :
679 InstrItinClass Itin = NoItinerary, ComplexPattern Addr = addr> :
1452 // add op with mem ComplexPattern is used and the stack address copy
HDMipsMSAInstrInfo.td280 ComplexPattern<ty, numops, fn, roots, props> {
350 def vsplat_uimm_pow2 : ComplexPattern<vAny, 1, "selectVSplatUimmPow2",
355 def vsplat_uimm_inv_pow2 : ComplexPattern<vAny, 1, "selectVSplatUimmInvPow2",
371 // FIXME: These should be a ComplexPattern but we can't use them because the
1155 ComplexPattern Imm, RegisterOperand ROWD,
1166 ComplexPattern Imm, RegisterOperand ROWD,
1177 ComplexPattern Imm, RegisterOperand ROWD,
1188 ComplexPattern Imm, RegisterOperand ROWD,
1243 ComplexPattern Mask, RegisterOperand ROWD,
2360 Operand MemOpnd = mem_msa, ComplexPattern Addr = addrimm10,
[all …]
/NextBSD/contrib/llvm/lib/Target/AMDGPU/
HDSIInstrInfo.td521 def DS1Addr1Offset : ComplexPattern<i32, 2, "SelectDS1Addr1Offset">;
522 def DS64Bit4ByteAligned : ComplexPattern<i32, 3, "SelectDS64Bit4ByteAligned">;
524 def MUBUFAddr32 : ComplexPattern<i64, 9, "SelectMUBUFAddr32">;
525 def MUBUFAddr64 : ComplexPattern<i64, 7, "SelectMUBUFAddr64">;
526 def MUBUFAddr64Atomic : ComplexPattern<i64, 5, "SelectMUBUFAddr64">;
527 def MUBUFScratch : ComplexPattern<i64, 4, "SelectMUBUFScratch">;
528 def MUBUFOffset : ComplexPattern<i64, 6, "SelectMUBUFOffset">;
529 def MUBUFOffsetAtomic : ComplexPattern<i64, 4, "SelectMUBUFOffset">;
531 def VOP3Mods0 : ComplexPattern<untyped, 4, "SelectVOP3Mods0">;
532 def VOP3NoMods0 : ComplexPattern<untyped, 4, "SelectVOP3NoMods0">;
[all …]
HDR600Instructions.td74 def ADDRParam : ComplexPattern<i32, 2, "SelectADDRParam", [], []>;
75 def ADDRDWord : ComplexPattern<i32, 1, "SelectADDRDWord", [], []>;
76 def ADDRVTX_READ : ComplexPattern<i32, 2, "SelectADDRVTX_READ", [], []>;
77 def ADDRGA_CONST_OFFSET : ComplexPattern<i32, 1, "SelectGlobalValueConstantOffset", [], []>;
78 def ADDRGA_VAR_OFFSET : ComplexPattern<i32, 2, "SelectGlobalValueVariableOffset", [], []>;
HDAMDGPUInstructions.td42 def ADDRIndirect : ComplexPattern<iPTR, 2, "SelectADDRIndirect", [], []>;
476 ComplexPattern addrPat> {
/NextBSD/contrib/llvm/lib/Target/Hexagon/
HDHexagonOperands.td508 def AddrFI : ComplexPattern<i32, 1, "SelectAddrFI", [frameindex], []>;
513 def AddrGA : ComplexPattern<i32, 1, "SelectAddrGA", [], []>;
514 def AddrGP : ComplexPattern<i32, 1, "SelectAddrGP", [], []>;
/NextBSD/contrib/llvm/lib/Target/ARM/
HDARMInstrThumb.td158 ComplexPattern<i32, 2, "SelectThumbAddrModeRR", []> {
174 ComplexPattern<i32, 2, "SelectThumbAddrModeRI5S1", []> {
182 ComplexPattern<i32, 2, "SelectThumbAddrModeRI5S2", []> {
190 ComplexPattern<i32, 2, "SelectThumbAddrModeRI5S4", []> {
202 ComplexPattern<i32, 2, "SelectThumbAddrModeImm5S4", []> {
214 ComplexPattern<i32, 2, "SelectThumbAddrModeImm5S2", []> {
226 ComplexPattern<i32, 2, "SelectThumbAddrModeImm5S1", []> {
240 ComplexPattern<i32, 2, "SelectThumbAddrModeSP", []> {
HDARMInstrInfo.td524 ComplexPattern<i32, 3, "SelectRegShifterOperand",
535 ComplexPattern<i32, 2, "SelectImmShifterOperand",
546 ComplexPattern<i32, 3, "SelectShiftRegShifterOperand",
557 ComplexPattern<i32, 2, "SelectShiftImmShifterOperand",
799 ComplexPattern<i32, 2, "SelectAddrModeImm12", []> {
822 ComplexPattern<i32, 3, "SelectLdStSOReg", []> {
878 ComplexPattern<i32, 3, "SelectAddrMode2", []> {
890 ComplexPattern<i32, 2, "SelectAddrMode2OffsetReg",
903 ComplexPattern<i32, 2, "SelectAddrMode2OffsetImm",
918 ComplexPattern<i32, 3, "SelectAddrMode3", []> {
[all …]
HDARMInstrThumb2.td46 ComplexPattern<i32, 2, "SelectT2ShifterOperandReg",
154 ComplexPattern<i32, 2, "SelectT2AddrModeImm12", []> {
194 ComplexPattern<i32, 2, "SelectT2AddrModeImm8", []> {
205 ComplexPattern<i32, 2, "SelectT2AddrModeImm8", []> {
221 ComplexPattern<i32, 1, "SelectT2AddrModeImm8Offset",
257 ComplexPattern<i32, 2, "SelectT2AddrModeExclusive"> {
268 ComplexPattern<i32, 3, "SelectT2AddrModeSoReg", []> {
/NextBSD/contrib/llvm/lib/Target/X86/
HDX86InstrFMA.td157 ComplexPattern mem_cpat> {
256 ComplexPattern mem_cpat, Intrinsic Int> {
HDX86InstrInfo.td701 def addr : ComplexPattern<iPTR, 5, "SelectAddr", [], [SDNPWantParent]>;
702 def lea32addr : ComplexPattern<i32, 5, "SelectLEAAddr",
706 def lea64_32addr : ComplexPattern<i32, 5, "SelectLEA64_32Addr",
711 def tls32addr : ComplexPattern<i32, 5, "SelectTLSADDRAddr",
714 def tls32baseaddr : ComplexPattern<i32, 5, "SelectTLSADDRAddr",
717 def lea64addr : ComplexPattern<i64, 5, "SelectLEAAddr",
721 def tls64addr : ComplexPattern<i64, 5, "SelectTLSADDRAddr",
724 def tls64baseaddr : ComplexPattern<i64, 5, "SelectTLSADDRAddr",
727 def vectoraddr : ComplexPattern<iPTR, 5, "SelectVectorAddr", [],[SDNPWantParent]>;
HDX86InstrFragmentsSIMD.td439 def sse_load_f32 : ComplexPattern<v4f32, 5, "SelectScalarSSELoad", [],
442 def sse_load_f64 : ComplexPattern<v2f64, 5, "SelectScalarSSELoad", [],
HDX86InstrXOP.td43 Operand memop, ComplexPattern mem_cpat> {
/NextBSD/contrib/llvm/lib/Target/AArch64/
HDAArch64InstrFormats.td335 ComplexPattern<FloatVT, 1, "SelectCVTFixedPosOperand<32>", [fpimm, ld]> {
343 ComplexPattern<FloatVT, 1, "SelectCVTFixedPosOperand<64>", [fpimm, ld]> {
561 ComplexPattern<Ty, 2, "SelectArithShiftedRegister", []> {
583 ComplexPattern<Ty, 2, "SelectLogicalShiftedRegister", []> {
632 : Operand<Ty>, ComplexPattern<Ty, 2, "SelectArithImmed", [imm]> {
652 : Operand<Ty>, ComplexPattern<Ty, 2, "SelectNegArithImmed", [imm]> {
681 ComplexPattern<Ty, 2, "SelectArithExtendedRegister", []> {
687 ComplexPattern<Ty, 2, "SelectArithExtendedRegister", []> {
2270 def am_indexed8 : ComplexPattern<i64, 2, "SelectAddrModeIndexed8", []>;
2271 def am_indexed16 : ComplexPattern<i64, 2, "SelectAddrModeIndexed16", []>;
[all …]
/NextBSD/contrib/llvm/lib/Target/BPF/
HDBPFInstrInfo.td57 def ADDRri : ComplexPattern<i64, 2, "SelectAddr", [], []>;
58 def FIri : ComplexPattern<i64, 2, "SelectFIAddr", [add, or], []>;
/NextBSD/contrib/llvm/lib/Target/SystemZ/
HDSystemZOperands.td63 : ComplexPattern<vt, 1, "selectPCRelAddress",
109 : ComplexPattern<!cast<ValueType>("i"##bitsize), numops,
/NextBSD/contrib/llvm/include/llvm/Target/
HDTargetSelectionDAG.td288 def SDNPWantRoot : SDNodeProperty; // ComplexPattern gets the root of match
289 def SDNPWantParent : SDNodeProperty; // ComplexPattern gets the parent
1086 // e.g. X86 addressing mode - def addr : ComplexPattern<4, "SelectAddr", [add]>;
1088 class ComplexPattern<ValueType ty, int numops, string fn,

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