1//===-- X86InstrInfo.td - Main X86 Instruction Definition --*- tablegen -*-===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file describes the X86 instruction set, defining the instructions, and 11// properties of the instructions which are needed for code generation, machine 12// code emission, and analysis. 13// 14//===----------------------------------------------------------------------===// 15 16//===----------------------------------------------------------------------===// 17// X86 specific DAG Nodes. 18// 19 20def SDTIntShiftDOp: SDTypeProfile<1, 3, 21 [SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>, 22 SDTCisInt<0>, SDTCisInt<3>]>; 23 24def SDTX86CmpTest : SDTypeProfile<1, 2, [SDTCisVT<0, i32>, SDTCisSameAs<1, 2>]>; 25 26def SDTX86Cmps : SDTypeProfile<1, 3, [SDTCisFP<0>, SDTCisSameAs<1, 2>, SDTCisVT<3, i8>]>; 27//def SDTX86Cmpss : SDTypeProfile<1, 3, [SDTCisVT<0, f32>, SDTCisSameAs<1, 2>, SDTCisVT<3, i8>]>; 28 29def SDTX86Cmov : SDTypeProfile<1, 4, 30 [SDTCisSameAs<0, 1>, SDTCisSameAs<1, 2>, 31 SDTCisVT<3, i8>, SDTCisVT<4, i32>]>; 32 33// Unary and binary operator instructions that set EFLAGS as a side-effect. 34def SDTUnaryArithWithFlags : SDTypeProfile<2, 1, 35 [SDTCisSameAs<0, 2>, 36 SDTCisInt<0>, SDTCisVT<1, i32>]>; 37 38def SDTBinaryArithWithFlags : SDTypeProfile<2, 2, 39 [SDTCisSameAs<0, 2>, 40 SDTCisSameAs<0, 3>, 41 SDTCisInt<0>, SDTCisVT<1, i32>]>; 42 43// SDTBinaryArithWithFlagsInOut - RES1, EFLAGS = op LHS, RHS, EFLAGS 44def SDTBinaryArithWithFlagsInOut : SDTypeProfile<2, 3, 45 [SDTCisSameAs<0, 2>, 46 SDTCisSameAs<0, 3>, 47 SDTCisInt<0>, 48 SDTCisVT<1, i32>, 49 SDTCisVT<4, i32>]>; 50// RES1, RES2, FLAGS = op LHS, RHS 51def SDT2ResultBinaryArithWithFlags : SDTypeProfile<3, 2, 52 [SDTCisSameAs<0, 1>, 53 SDTCisSameAs<0, 2>, 54 SDTCisSameAs<0, 3>, 55 SDTCisInt<0>, SDTCisVT<1, i32>]>; 56def SDTX86BrCond : SDTypeProfile<0, 3, 57 [SDTCisVT<0, OtherVT>, 58 SDTCisVT<1, i8>, SDTCisVT<2, i32>]>; 59 60def SDTX86SetCC : SDTypeProfile<1, 2, 61 [SDTCisVT<0, i8>, 62 SDTCisVT<1, i8>, SDTCisVT<2, i32>]>; 63def SDTX86SetCC_C : SDTypeProfile<1, 2, 64 [SDTCisInt<0>, 65 SDTCisVT<1, i8>, SDTCisVT<2, i32>]>; 66 67def SDTX86sahf : SDTypeProfile<1, 1, [SDTCisVT<0, i32>, SDTCisVT<1, i8>]>; 68 69def SDTX86rdrand : SDTypeProfile<2, 0, [SDTCisInt<0>, SDTCisVT<1, i32>]>; 70 71def SDTX86cas : SDTypeProfile<0, 3, [SDTCisPtrTy<0>, SDTCisInt<1>, 72 SDTCisVT<2, i8>]>; 73def SDTX86caspair : SDTypeProfile<0, 1, [SDTCisPtrTy<0>]>; 74 75def SDTX86atomicBinary : SDTypeProfile<2, 3, [SDTCisInt<0>, SDTCisInt<1>, 76 SDTCisPtrTy<2>, SDTCisInt<3>,SDTCisInt<4>]>; 77def SDTX86Ret : SDTypeProfile<0, -1, [SDTCisVT<0, i16>]>; 78 79def SDT_X86CallSeqStart : SDCallSeqStart<[SDTCisVT<0, i32>]>; 80def SDT_X86CallSeqEnd : SDCallSeqEnd<[SDTCisVT<0, i32>, 81 SDTCisVT<1, i32>]>; 82 83def SDT_X86Call : SDTypeProfile<0, -1, [SDTCisVT<0, iPTR>]>; 84 85def SDT_X86VASTART_SAVE_XMM_REGS : SDTypeProfile<0, -1, [SDTCisVT<0, i8>, 86 SDTCisVT<1, iPTR>, 87 SDTCisVT<2, iPTR>]>; 88 89def SDT_X86VAARG_64 : SDTypeProfile<1, -1, [SDTCisPtrTy<0>, 90 SDTCisPtrTy<1>, 91 SDTCisVT<2, i32>, 92 SDTCisVT<3, i8>, 93 SDTCisVT<4, i32>]>; 94 95def SDTX86RepStr : SDTypeProfile<0, 1, [SDTCisVT<0, OtherVT>]>; 96 97def SDTX86Void : SDTypeProfile<0, 0, []>; 98 99def SDTX86Wrapper : SDTypeProfile<1, 1, [SDTCisSameAs<0, 1>, SDTCisPtrTy<0>]>; 100 101def SDT_X86TLSADDR : SDTypeProfile<0, 1, [SDTCisInt<0>]>; 102 103def SDT_X86TLSBASEADDR : SDTypeProfile<0, 1, [SDTCisInt<0>]>; 104 105def SDT_X86TLSCALL : SDTypeProfile<0, 1, [SDTCisInt<0>]>; 106 107def SDT_X86SEG_ALLOCA : SDTypeProfile<1, 1, [SDTCisVT<0, iPTR>, SDTCisVT<1, iPTR>]>; 108 109def SDT_X86WIN_FTOL : SDTypeProfile<0, 1, [SDTCisFP<0>]>; 110 111def SDT_X86EHRET : SDTypeProfile<0, 1, [SDTCisInt<0>]>; 112 113def SDT_X86TCRET : SDTypeProfile<0, 2, [SDTCisPtrTy<0>, SDTCisVT<1, i32>]>; 114 115def SDT_X86MEMBARRIER : SDTypeProfile<0, 0, []>; 116 117def X86MemBarrier : SDNode<"X86ISD::MEMBARRIER", SDT_X86MEMBARRIER, 118 [SDNPHasChain,SDNPSideEffect]>; 119def X86MFence : SDNode<"X86ISD::MFENCE", SDT_X86MEMBARRIER, 120 [SDNPHasChain]>; 121def X86SFence : SDNode<"X86ISD::SFENCE", SDT_X86MEMBARRIER, 122 [SDNPHasChain]>; 123def X86LFence : SDNode<"X86ISD::LFENCE", SDT_X86MEMBARRIER, 124 [SDNPHasChain]>; 125 126 127def X86bsf : SDNode<"X86ISD::BSF", SDTUnaryArithWithFlags>; 128def X86bsr : SDNode<"X86ISD::BSR", SDTUnaryArithWithFlags>; 129def X86shld : SDNode<"X86ISD::SHLD", SDTIntShiftDOp>; 130def X86shrd : SDNode<"X86ISD::SHRD", SDTIntShiftDOp>; 131 132def X86cmp : SDNode<"X86ISD::CMP" , SDTX86CmpTest>; 133def X86bt : SDNode<"X86ISD::BT", SDTX86CmpTest>; 134 135def X86cmov : SDNode<"X86ISD::CMOV", SDTX86Cmov>; 136def X86brcond : SDNode<"X86ISD::BRCOND", SDTX86BrCond, 137 [SDNPHasChain]>; 138def X86setcc : SDNode<"X86ISD::SETCC", SDTX86SetCC>; 139def X86setcc_c : SDNode<"X86ISD::SETCC_CARRY", SDTX86SetCC_C>; 140 141def X86sahf : SDNode<"X86ISD::SAHF", SDTX86sahf>; 142 143def X86rdrand : SDNode<"X86ISD::RDRAND", SDTX86rdrand, 144 [SDNPHasChain, SDNPSideEffect]>; 145 146def X86rdseed : SDNode<"X86ISD::RDSEED", SDTX86rdrand, 147 [SDNPHasChain, SDNPSideEffect]>; 148 149def X86cas : SDNode<"X86ISD::LCMPXCHG_DAG", SDTX86cas, 150 [SDNPHasChain, SDNPInGlue, SDNPOutGlue, SDNPMayStore, 151 SDNPMayLoad, SDNPMemOperand]>; 152def X86cas8 : SDNode<"X86ISD::LCMPXCHG8_DAG", SDTX86caspair, 153 [SDNPHasChain, SDNPInGlue, SDNPOutGlue, SDNPMayStore, 154 SDNPMayLoad, SDNPMemOperand]>; 155def X86cas16 : SDNode<"X86ISD::LCMPXCHG16_DAG", SDTX86caspair, 156 [SDNPHasChain, SDNPInGlue, SDNPOutGlue, SDNPMayStore, 157 SDNPMayLoad, SDNPMemOperand]>; 158 159def X86retflag : SDNode<"X86ISD::RET_FLAG", SDTX86Ret, 160 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>; 161 162def X86vastart_save_xmm_regs : 163 SDNode<"X86ISD::VASTART_SAVE_XMM_REGS", 164 SDT_X86VASTART_SAVE_XMM_REGS, 165 [SDNPHasChain, SDNPVariadic]>; 166def X86vaarg64 : 167 SDNode<"X86ISD::VAARG_64", SDT_X86VAARG_64, 168 [SDNPHasChain, SDNPMayLoad, SDNPMayStore, 169 SDNPMemOperand]>; 170def X86callseq_start : 171 SDNode<"ISD::CALLSEQ_START", SDT_X86CallSeqStart, 172 [SDNPHasChain, SDNPOutGlue]>; 173def X86callseq_end : 174 SDNode<"ISD::CALLSEQ_END", SDT_X86CallSeqEnd, 175 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>; 176 177def X86call : SDNode<"X86ISD::CALL", SDT_X86Call, 178 [SDNPHasChain, SDNPOutGlue, SDNPOptInGlue, 179 SDNPVariadic]>; 180 181def X86rep_stos: SDNode<"X86ISD::REP_STOS", SDTX86RepStr, 182 [SDNPHasChain, SDNPInGlue, SDNPOutGlue, SDNPMayStore]>; 183def X86rep_movs: SDNode<"X86ISD::REP_MOVS", SDTX86RepStr, 184 [SDNPHasChain, SDNPInGlue, SDNPOutGlue, SDNPMayStore, 185 SDNPMayLoad]>; 186 187def X86rdtsc : SDNode<"X86ISD::RDTSC_DAG", SDTX86Void, 188 [SDNPHasChain, SDNPOutGlue, SDNPSideEffect]>; 189def X86rdtscp : SDNode<"X86ISD::RDTSCP_DAG", SDTX86Void, 190 [SDNPHasChain, SDNPOutGlue, SDNPSideEffect]>; 191def X86rdpmc : SDNode<"X86ISD::RDPMC_DAG", SDTX86Void, 192 [SDNPHasChain, SDNPOutGlue, SDNPSideEffect]>; 193 194def X86Wrapper : SDNode<"X86ISD::Wrapper", SDTX86Wrapper>; 195def X86WrapperRIP : SDNode<"X86ISD::WrapperRIP", SDTX86Wrapper>; 196 197def X86RecoverFrameAlloc : SDNode<"ISD::LOCAL_RECOVER", 198 SDTypeProfile<1, 1, [SDTCisSameAs<0, 1>, 199 SDTCisInt<1>]>>; 200 201def X86tlsaddr : SDNode<"X86ISD::TLSADDR", SDT_X86TLSADDR, 202 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>; 203 204def X86tlsbaseaddr : SDNode<"X86ISD::TLSBASEADDR", SDT_X86TLSBASEADDR, 205 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>; 206 207def X86ehret : SDNode<"X86ISD::EH_RETURN", SDT_X86EHRET, 208 [SDNPHasChain]>; 209 210def X86eh_sjlj_setjmp : SDNode<"X86ISD::EH_SJLJ_SETJMP", 211 SDTypeProfile<1, 1, [SDTCisInt<0>, 212 SDTCisPtrTy<1>]>, 213 [SDNPHasChain, SDNPSideEffect]>; 214def X86eh_sjlj_longjmp : SDNode<"X86ISD::EH_SJLJ_LONGJMP", 215 SDTypeProfile<0, 1, [SDTCisPtrTy<0>]>, 216 [SDNPHasChain, SDNPSideEffect]>; 217 218def X86tcret : SDNode<"X86ISD::TC_RETURN", SDT_X86TCRET, 219 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>; 220 221def X86add_flag : SDNode<"X86ISD::ADD", SDTBinaryArithWithFlags, 222 [SDNPCommutative]>; 223def X86sub_flag : SDNode<"X86ISD::SUB", SDTBinaryArithWithFlags>; 224def X86smul_flag : SDNode<"X86ISD::SMUL", SDTBinaryArithWithFlags, 225 [SDNPCommutative]>; 226def X86umul_flag : SDNode<"X86ISD::UMUL", SDT2ResultBinaryArithWithFlags, 227 [SDNPCommutative]>; 228def X86adc_flag : SDNode<"X86ISD::ADC", SDTBinaryArithWithFlagsInOut>; 229def X86sbb_flag : SDNode<"X86ISD::SBB", SDTBinaryArithWithFlagsInOut>; 230 231def X86inc_flag : SDNode<"X86ISD::INC", SDTUnaryArithWithFlags>; 232def X86dec_flag : SDNode<"X86ISD::DEC", SDTUnaryArithWithFlags>; 233def X86or_flag : SDNode<"X86ISD::OR", SDTBinaryArithWithFlags, 234 [SDNPCommutative]>; 235def X86xor_flag : SDNode<"X86ISD::XOR", SDTBinaryArithWithFlags, 236 [SDNPCommutative]>; 237def X86and_flag : SDNode<"X86ISD::AND", SDTBinaryArithWithFlags, 238 [SDNPCommutative]>; 239 240def X86bextr : SDNode<"X86ISD::BEXTR", SDTIntBinOp>; 241 242def X86mul_imm : SDNode<"X86ISD::MUL_IMM", SDTIntBinOp>; 243 244def X86WinAlloca : SDNode<"X86ISD::WIN_ALLOCA", SDTX86Void, 245 [SDNPHasChain, SDNPInGlue, SDNPOutGlue]>; 246 247def X86SegAlloca : SDNode<"X86ISD::SEG_ALLOCA", SDT_X86SEG_ALLOCA, 248 [SDNPHasChain]>; 249 250def X86TLSCall : SDNode<"X86ISD::TLSCALL", SDT_X86TLSCALL, 251 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>; 252 253def X86WinFTOL : SDNode<"X86ISD::WIN_FTOL", SDT_X86WIN_FTOL, 254 [SDNPHasChain, SDNPOutGlue]>; 255 256//===----------------------------------------------------------------------===// 257// X86 Operand Definitions. 258// 259 260// A version of ptr_rc which excludes SP, ESP, and RSP. This is used for 261// the index operand of an address, to conform to x86 encoding restrictions. 262def ptr_rc_nosp : PointerLikeRegClass<1>; 263 264// *mem - Operand definitions for the funky X86 addressing mode operands. 265// 266def X86MemAsmOperand : AsmOperandClass { 267 let Name = "Mem"; 268} 269let RenderMethod = "addMemOperands" in { 270 def X86Mem8AsmOperand : AsmOperandClass { let Name = "Mem8"; } 271 def X86Mem16AsmOperand : AsmOperandClass { let Name = "Mem16"; } 272 def X86Mem32AsmOperand : AsmOperandClass { let Name = "Mem32"; } 273 def X86Mem64AsmOperand : AsmOperandClass { let Name = "Mem64"; } 274 def X86Mem80AsmOperand : AsmOperandClass { let Name = "Mem80"; } 275 def X86Mem128AsmOperand : AsmOperandClass { let Name = "Mem128"; } 276 def X86Mem256AsmOperand : AsmOperandClass { let Name = "Mem256"; } 277 def X86Mem512AsmOperand : AsmOperandClass { let Name = "Mem512"; } 278 // Gather mem operands 279 def X86MemVX32Operand : AsmOperandClass { let Name = "MemVX32"; } 280 def X86MemVY32Operand : AsmOperandClass { let Name = "MemVY32"; } 281 def X86MemVZ32Operand : AsmOperandClass { let Name = "MemVZ32"; } 282 def X86MemVX64Operand : AsmOperandClass { let Name = "MemVX64"; } 283 def X86MemVY64Operand : AsmOperandClass { let Name = "MemVY64"; } 284 def X86MemVZ64Operand : AsmOperandClass { let Name = "MemVZ64"; } 285 def X86MemVX32XOperand : AsmOperandClass { let Name = "MemVX32X"; } 286 def X86MemVY32XOperand : AsmOperandClass { let Name = "MemVY32X"; } 287 def X86MemVX64XOperand : AsmOperandClass { let Name = "MemVX64X"; } 288 def X86MemVY64XOperand : AsmOperandClass { let Name = "MemVY64X"; } 289} 290 291def X86AbsMemAsmOperand : AsmOperandClass { 292 let Name = "AbsMem"; 293 let SuperClasses = [X86MemAsmOperand]; 294} 295 296class X86MemOperand<string printMethod, 297 AsmOperandClass parserMatchClass = X86MemAsmOperand> : Operand<iPTR> { 298 let PrintMethod = printMethod; 299 let MIOperandInfo = (ops ptr_rc, i8imm, ptr_rc_nosp, i32imm, i8imm); 300 let ParserMatchClass = parserMatchClass; 301 let OperandType = "OPERAND_MEMORY"; 302} 303 304// Gather mem operands 305class X86VMemOperand<RegisterClass RC, string printMethod, 306 AsmOperandClass parserMatchClass> 307 : X86MemOperand<printMethod, parserMatchClass> { 308 let MIOperandInfo = (ops ptr_rc, i8imm, RC, i32imm, i8imm); 309} 310 311def anymem : X86MemOperand<"printanymem">; 312 313def opaque32mem : X86MemOperand<"printopaquemem">; 314def opaque48mem : X86MemOperand<"printopaquemem">; 315def opaque80mem : X86MemOperand<"printopaquemem">; 316def opaque512mem : X86MemOperand<"printopaquemem">; 317 318def i8mem : X86MemOperand<"printi8mem", X86Mem8AsmOperand>; 319def i16mem : X86MemOperand<"printi16mem", X86Mem16AsmOperand>; 320def i32mem : X86MemOperand<"printi32mem", X86Mem32AsmOperand>; 321def i64mem : X86MemOperand<"printi64mem", X86Mem64AsmOperand>; 322def i128mem : X86MemOperand<"printi128mem", X86Mem128AsmOperand>; 323def i256mem : X86MemOperand<"printi256mem", X86Mem256AsmOperand>; 324def i512mem : X86MemOperand<"printi512mem", X86Mem512AsmOperand>; 325def f32mem : X86MemOperand<"printf32mem", X86Mem32AsmOperand>; 326def f64mem : X86MemOperand<"printf64mem", X86Mem64AsmOperand>; 327def f80mem : X86MemOperand<"printf80mem", X86Mem80AsmOperand>; 328def f128mem : X86MemOperand<"printf128mem", X86Mem128AsmOperand>; 329def f256mem : X86MemOperand<"printf256mem", X86Mem256AsmOperand>; 330def f512mem : X86MemOperand<"printf512mem", X86Mem512AsmOperand>; 331 332def v512mem : X86VMemOperand<VR512, "printf512mem", X86Mem512AsmOperand>; 333 334// Gather mem operands 335def vx32mem : X86VMemOperand<VR128, "printi32mem", X86MemVX32Operand>; 336def vy32mem : X86VMemOperand<VR256, "printi32mem", X86MemVY32Operand>; 337def vx64mem : X86VMemOperand<VR128, "printi64mem", X86MemVX64Operand>; 338def vy64mem : X86VMemOperand<VR256, "printi64mem", X86MemVY64Operand>; 339 340def vx32xmem : X86VMemOperand<VR128X, "printi32mem", X86MemVX32XOperand>; 341def vx64xmem : X86VMemOperand<VR128X, "printi32mem", X86MemVX64XOperand>; 342def vy32xmem : X86VMemOperand<VR256X, "printi32mem", X86MemVY32XOperand>; 343def vy64xmem : X86VMemOperand<VR256X, "printi64mem", X86MemVY64XOperand>; 344def vz32mem : X86VMemOperand<VR512, "printi32mem", X86MemVZ32Operand>; 345def vz64mem : X86VMemOperand<VR512, "printi64mem", X86MemVZ64Operand>; 346 347// A version of i8mem for use on x86-64 that uses GR64_NOREX instead of 348// plain GR64, so that it doesn't potentially require a REX prefix. 349def i8mem_NOREX : Operand<i64> { 350 let PrintMethod = "printi8mem"; 351 let MIOperandInfo = (ops GR64_NOREX, i8imm, GR64_NOREX_NOSP, i32imm, i8imm); 352 let ParserMatchClass = X86Mem8AsmOperand; 353 let OperandType = "OPERAND_MEMORY"; 354} 355 356// GPRs available for tailcall. 357// It represents GR32_TC, GR64_TC or GR64_TCW64. 358def ptr_rc_tailcall : PointerLikeRegClass<2>; 359 360// Special i32mem for addresses of load folding tail calls. These are not 361// allowed to use callee-saved registers since they must be scheduled 362// after callee-saved register are popped. 363def i32mem_TC : Operand<i32> { 364 let PrintMethod = "printi32mem"; 365 let MIOperandInfo = (ops ptr_rc_tailcall, i8imm, ptr_rc_tailcall, 366 i32imm, i8imm); 367 let ParserMatchClass = X86Mem32AsmOperand; 368 let OperandType = "OPERAND_MEMORY"; 369} 370 371// Special i64mem for addresses of load folding tail calls. These are not 372// allowed to use callee-saved registers since they must be scheduled 373// after callee-saved register are popped. 374def i64mem_TC : Operand<i64> { 375 let PrintMethod = "printi64mem"; 376 let MIOperandInfo = (ops ptr_rc_tailcall, i8imm, 377 ptr_rc_tailcall, i32imm, i8imm); 378 let ParserMatchClass = X86Mem64AsmOperand; 379 let OperandType = "OPERAND_MEMORY"; 380} 381 382let OperandType = "OPERAND_PCREL", 383 ParserMatchClass = X86AbsMemAsmOperand, 384 PrintMethod = "printPCRelImm" in { 385def i32imm_pcrel : Operand<i32>; 386def i16imm_pcrel : Operand<i16>; 387 388// Branch targets have OtherVT type and print as pc-relative values. 389def brtarget : Operand<OtherVT>; 390def brtarget8 : Operand<OtherVT>; 391 392} 393 394// Special parser to detect 16-bit mode to select 16-bit displacement. 395def X86AbsMem16AsmOperand : AsmOperandClass { 396 let Name = "AbsMem16"; 397 let RenderMethod = "addAbsMemOperands"; 398 let SuperClasses = [X86AbsMemAsmOperand]; 399} 400 401// Branch targets have OtherVT type and print as pc-relative values. 402let OperandType = "OPERAND_PCREL", 403 PrintMethod = "printPCRelImm" in { 404let ParserMatchClass = X86AbsMem16AsmOperand in 405 def brtarget16 : Operand<OtherVT>; 406let ParserMatchClass = X86AbsMemAsmOperand in 407 def brtarget32 : Operand<OtherVT>; 408} 409 410let RenderMethod = "addSrcIdxOperands" in { 411 def X86SrcIdx8Operand : AsmOperandClass { 412 let Name = "SrcIdx8"; 413 let SuperClasses = [X86Mem8AsmOperand]; 414 } 415 def X86SrcIdx16Operand : AsmOperandClass { 416 let Name = "SrcIdx16"; 417 let SuperClasses = [X86Mem16AsmOperand]; 418 } 419 def X86SrcIdx32Operand : AsmOperandClass { 420 let Name = "SrcIdx32"; 421 let SuperClasses = [X86Mem32AsmOperand]; 422 } 423 def X86SrcIdx64Operand : AsmOperandClass { 424 let Name = "SrcIdx64"; 425 let SuperClasses = [X86Mem64AsmOperand]; 426 } 427} // RenderMethod = "addSrcIdxOperands" 428 429let RenderMethod = "addDstIdxOperands" in { 430 def X86DstIdx8Operand : AsmOperandClass { 431 let Name = "DstIdx8"; 432 let SuperClasses = [X86Mem8AsmOperand]; 433 } 434 def X86DstIdx16Operand : AsmOperandClass { 435 let Name = "DstIdx16"; 436 let SuperClasses = [X86Mem16AsmOperand]; 437 } 438 def X86DstIdx32Operand : AsmOperandClass { 439 let Name = "DstIdx32"; 440 let SuperClasses = [X86Mem32AsmOperand]; 441 } 442 def X86DstIdx64Operand : AsmOperandClass { 443 let Name = "DstIdx64"; 444 let SuperClasses = [X86Mem64AsmOperand]; 445 } 446} // RenderMethod = "addDstIdxOperands" 447 448let RenderMethod = "addMemOffsOperands" in { 449 def X86MemOffs16_8AsmOperand : AsmOperandClass { 450 let Name = "MemOffs16_8"; 451 let SuperClasses = [X86Mem8AsmOperand]; 452 } 453 def X86MemOffs16_16AsmOperand : AsmOperandClass { 454 let Name = "MemOffs16_16"; 455 let SuperClasses = [X86Mem16AsmOperand]; 456 } 457 def X86MemOffs16_32AsmOperand : AsmOperandClass { 458 let Name = "MemOffs16_32"; 459 let SuperClasses = [X86Mem32AsmOperand]; 460 } 461 def X86MemOffs32_8AsmOperand : AsmOperandClass { 462 let Name = "MemOffs32_8"; 463 let SuperClasses = [X86Mem8AsmOperand]; 464 } 465 def X86MemOffs32_16AsmOperand : AsmOperandClass { 466 let Name = "MemOffs32_16"; 467 let SuperClasses = [X86Mem16AsmOperand]; 468 } 469 def X86MemOffs32_32AsmOperand : AsmOperandClass { 470 let Name = "MemOffs32_32"; 471 let SuperClasses = [X86Mem32AsmOperand]; 472 } 473 def X86MemOffs32_64AsmOperand : AsmOperandClass { 474 let Name = "MemOffs32_64"; 475 let SuperClasses = [X86Mem64AsmOperand]; 476 } 477 def X86MemOffs64_8AsmOperand : AsmOperandClass { 478 let Name = "MemOffs64_8"; 479 let SuperClasses = [X86Mem8AsmOperand]; 480 } 481 def X86MemOffs64_16AsmOperand : AsmOperandClass { 482 let Name = "MemOffs64_16"; 483 let SuperClasses = [X86Mem16AsmOperand]; 484 } 485 def X86MemOffs64_32AsmOperand : AsmOperandClass { 486 let Name = "MemOffs64_32"; 487 let SuperClasses = [X86Mem32AsmOperand]; 488 } 489 def X86MemOffs64_64AsmOperand : AsmOperandClass { 490 let Name = "MemOffs64_64"; 491 let SuperClasses = [X86Mem64AsmOperand]; 492 } 493} // RenderMethod = "addMemOffsOperands" 494 495class X86SrcIdxOperand<string printMethod, AsmOperandClass parserMatchClass> 496 : X86MemOperand<printMethod, parserMatchClass> { 497 let MIOperandInfo = (ops ptr_rc, i8imm); 498} 499 500class X86DstIdxOperand<string printMethod, AsmOperandClass parserMatchClass> 501 : X86MemOperand<printMethod, parserMatchClass> { 502 let MIOperandInfo = (ops ptr_rc); 503} 504 505def srcidx8 : X86SrcIdxOperand<"printSrcIdx8", X86SrcIdx8Operand>; 506def srcidx16 : X86SrcIdxOperand<"printSrcIdx16", X86SrcIdx16Operand>; 507def srcidx32 : X86SrcIdxOperand<"printSrcIdx32", X86SrcIdx32Operand>; 508def srcidx64 : X86SrcIdxOperand<"printSrcIdx64", X86SrcIdx64Operand>; 509def dstidx8 : X86DstIdxOperand<"printDstIdx8", X86DstIdx8Operand>; 510def dstidx16 : X86DstIdxOperand<"printDstIdx16", X86DstIdx16Operand>; 511def dstidx32 : X86DstIdxOperand<"printDstIdx32", X86DstIdx32Operand>; 512def dstidx64 : X86DstIdxOperand<"printDstIdx64", X86DstIdx64Operand>; 513 514class X86MemOffsOperand<Operand immOperand, string printMethod, 515 AsmOperandClass parserMatchClass> 516 : X86MemOperand<printMethod, parserMatchClass> { 517 let MIOperandInfo = (ops immOperand, i8imm); 518} 519 520def offset16_8 : X86MemOffsOperand<i16imm, "printMemOffs8", 521 X86MemOffs16_8AsmOperand>; 522def offset16_16 : X86MemOffsOperand<i16imm, "printMemOffs16", 523 X86MemOffs16_16AsmOperand>; 524def offset16_32 : X86MemOffsOperand<i16imm, "printMemOffs32", 525 X86MemOffs16_32AsmOperand>; 526def offset32_8 : X86MemOffsOperand<i32imm, "printMemOffs8", 527 X86MemOffs32_8AsmOperand>; 528def offset32_16 : X86MemOffsOperand<i32imm, "printMemOffs16", 529 X86MemOffs32_16AsmOperand>; 530def offset32_32 : X86MemOffsOperand<i32imm, "printMemOffs32", 531 X86MemOffs32_32AsmOperand>; 532def offset32_64 : X86MemOffsOperand<i32imm, "printMemOffs64", 533 X86MemOffs32_64AsmOperand>; 534def offset64_8 : X86MemOffsOperand<i64imm, "printMemOffs8", 535 X86MemOffs64_8AsmOperand>; 536def offset64_16 : X86MemOffsOperand<i64imm, "printMemOffs16", 537 X86MemOffs64_16AsmOperand>; 538def offset64_32 : X86MemOffsOperand<i64imm, "printMemOffs32", 539 X86MemOffs64_32AsmOperand>; 540def offset64_64 : X86MemOffsOperand<i64imm, "printMemOffs64", 541 X86MemOffs64_64AsmOperand>; 542 543def SSECC : Operand<i8> { 544 let PrintMethod = "printSSEAVXCC"; 545 let OperandType = "OPERAND_IMMEDIATE"; 546} 547 548def i8immZExt3 : ImmLeaf<i8, [{ 549 return Imm >= 0 && Imm < 8; 550}]>; 551 552def AVXCC : Operand<i8> { 553 let PrintMethod = "printSSEAVXCC"; 554 let OperandType = "OPERAND_IMMEDIATE"; 555} 556 557def i8immZExt5 : ImmLeaf<i8, [{ 558 return Imm >= 0 && Imm < 32; 559}]>; 560 561def AVX512ICC : Operand<i8> { 562 let PrintMethod = "printSSEAVXCC"; 563 let OperandType = "OPERAND_IMMEDIATE"; 564} 565 566def XOPCC : Operand<i8> { 567 let PrintMethod = "printXOPCC"; 568 let OperandType = "OPERAND_IMMEDIATE"; 569} 570 571class ImmSExtAsmOperandClass : AsmOperandClass { 572 let SuperClasses = [ImmAsmOperand]; 573 let RenderMethod = "addImmOperands"; 574} 575 576def X86GR32orGR64AsmOperand : AsmOperandClass { 577 let Name = "GR32orGR64"; 578} 579 580def GR32orGR64 : RegisterOperand<GR32> { 581 let ParserMatchClass = X86GR32orGR64AsmOperand; 582} 583def AVX512RCOperand : AsmOperandClass { 584 let Name = "AVX512RC"; 585} 586def AVX512RC : Operand<i32> { 587 let PrintMethod = "printRoundingControl"; 588 let OperandType = "OPERAND_IMMEDIATE"; 589 let ParserMatchClass = AVX512RCOperand; 590} 591 592// Sign-extended immediate classes. We don't need to define the full lattice 593// here because there is no instruction with an ambiguity between ImmSExti64i32 594// and ImmSExti32i8. 595// 596// The strange ranges come from the fact that the assembler always works with 597// 64-bit immediates, but for a 16-bit target value we want to accept both "-1" 598// (which will be a -1ULL), and "0xFF" (-1 in 16-bits). 599 600// [0, 0x7FFFFFFF] | 601// [0xFFFFFFFF80000000, 0xFFFFFFFFFFFFFFFF] 602def ImmSExti64i32AsmOperand : ImmSExtAsmOperandClass { 603 let Name = "ImmSExti64i32"; 604} 605 606// [0, 0x0000007F] | [0x000000000000FF80, 0x000000000000FFFF] | 607// [0xFFFFFFFFFFFFFF80, 0xFFFFFFFFFFFFFFFF] 608def ImmSExti16i8AsmOperand : ImmSExtAsmOperandClass { 609 let Name = "ImmSExti16i8"; 610 let SuperClasses = [ImmSExti64i32AsmOperand]; 611} 612 613// [0, 0x0000007F] | [0x00000000FFFFFF80, 0x00000000FFFFFFFF] | 614// [0xFFFFFFFFFFFFFF80, 0xFFFFFFFFFFFFFFFF] 615def ImmSExti32i8AsmOperand : ImmSExtAsmOperandClass { 616 let Name = "ImmSExti32i8"; 617} 618 619// [0, 0x0000007F] | 620// [0xFFFFFFFFFFFFFF80, 0xFFFFFFFFFFFFFFFF] 621def ImmSExti64i8AsmOperand : ImmSExtAsmOperandClass { 622 let Name = "ImmSExti64i8"; 623 let SuperClasses = [ImmSExti16i8AsmOperand, ImmSExti32i8AsmOperand, 624 ImmSExti64i32AsmOperand]; 625} 626 627// Unsigned immediate used by SSE/AVX instructions 628// [0, 0xFF] 629// [0xFFFFFFFFFFFFFF80, 0xFFFFFFFFFFFFFFFF] 630def ImmUnsignedi8AsmOperand : AsmOperandClass { 631 let Name = "ImmUnsignedi8"; 632 let RenderMethod = "addImmOperands"; 633} 634 635// A couple of more descriptive operand definitions. 636// 16-bits but only 8 bits are significant. 637def i16i8imm : Operand<i16> { 638 let ParserMatchClass = ImmSExti16i8AsmOperand; 639 let OperandType = "OPERAND_IMMEDIATE"; 640} 641// 32-bits but only 8 bits are significant. 642def i32i8imm : Operand<i32> { 643 let ParserMatchClass = ImmSExti32i8AsmOperand; 644 let OperandType = "OPERAND_IMMEDIATE"; 645} 646 647// 64-bits but only 32 bits are significant. 648def i64i32imm : Operand<i64> { 649 let ParserMatchClass = ImmSExti64i32AsmOperand; 650 let OperandType = "OPERAND_IMMEDIATE"; 651} 652 653// 64-bits but only 8 bits are significant. 654def i64i8imm : Operand<i64> { 655 let ParserMatchClass = ImmSExti64i8AsmOperand; 656 let OperandType = "OPERAND_IMMEDIATE"; 657} 658 659// Unsigned 8-bit immediate used by SSE/AVX instructions. 660def u8imm : Operand<i8> { 661 let PrintMethod = "printU8Imm"; 662 let ParserMatchClass = ImmUnsignedi8AsmOperand; 663 let OperandType = "OPERAND_IMMEDIATE"; 664} 665 666// 32-bit immediate but only 8-bits are significant and they are unsigned. 667// Used by some SSE/AVX instructions that use intrinsics. 668def i32u8imm : Operand<i32> { 669 let PrintMethod = "printU8Imm"; 670 let ParserMatchClass = ImmUnsignedi8AsmOperand; 671 let OperandType = "OPERAND_IMMEDIATE"; 672} 673 674// 64-bits but only 32 bits are significant, and those bits are treated as being 675// pc relative. 676def i64i32imm_pcrel : Operand<i64> { 677 let PrintMethod = "printPCRelImm"; 678 let ParserMatchClass = X86AbsMemAsmOperand; 679 let OperandType = "OPERAND_PCREL"; 680} 681 682def lea64_32mem : Operand<i32> { 683 let PrintMethod = "printanymem"; 684 let MIOperandInfo = (ops GR64, i8imm, GR64_NOSP, i32imm, i8imm); 685 let ParserMatchClass = X86MemAsmOperand; 686} 687 688// Memory operands that use 64-bit pointers in both ILP32 and LP64. 689def lea64mem : Operand<i64> { 690 let PrintMethod = "printanymem"; 691 let MIOperandInfo = (ops GR64, i8imm, GR64_NOSP, i32imm, i8imm); 692 let ParserMatchClass = X86MemAsmOperand; 693} 694 695 696//===----------------------------------------------------------------------===// 697// X86 Complex Pattern Definitions. 698// 699 700// Define X86 specific addressing mode. 701def addr : ComplexPattern<iPTR, 5, "SelectAddr", [], [SDNPWantParent]>; 702def lea32addr : ComplexPattern<i32, 5, "SelectLEAAddr", 703 [add, sub, mul, X86mul_imm, shl, or, frameindex], 704 []>; 705// In 64-bit mode 32-bit LEAs can use RIP-relative addressing. 706def lea64_32addr : ComplexPattern<i32, 5, "SelectLEA64_32Addr", 707 [add, sub, mul, X86mul_imm, shl, or, 708 frameindex, X86WrapperRIP], 709 []>; 710 711def tls32addr : ComplexPattern<i32, 5, "SelectTLSADDRAddr", 712 [tglobaltlsaddr], []>; 713 714def tls32baseaddr : ComplexPattern<i32, 5, "SelectTLSADDRAddr", 715 [tglobaltlsaddr], []>; 716 717def lea64addr : ComplexPattern<i64, 5, "SelectLEAAddr", 718 [add, sub, mul, X86mul_imm, shl, or, frameindex, 719 X86WrapperRIP], []>; 720 721def tls64addr : ComplexPattern<i64, 5, "SelectTLSADDRAddr", 722 [tglobaltlsaddr], []>; 723 724def tls64baseaddr : ComplexPattern<i64, 5, "SelectTLSADDRAddr", 725 [tglobaltlsaddr], []>; 726 727def vectoraddr : ComplexPattern<iPTR, 5, "SelectVectorAddr", [],[SDNPWantParent]>; 728 729//===----------------------------------------------------------------------===// 730// X86 Instruction Predicate Definitions. 731def HasCMov : Predicate<"Subtarget->hasCMov()">; 732def NoCMov : Predicate<"!Subtarget->hasCMov()">; 733 734def HasMMX : Predicate<"Subtarget->hasMMX()">; 735def Has3DNow : Predicate<"Subtarget->has3DNow()">; 736def Has3DNowA : Predicate<"Subtarget->has3DNowA()">; 737def HasSSE1 : Predicate<"Subtarget->hasSSE1()">; 738def UseSSE1 : Predicate<"Subtarget->hasSSE1() && !Subtarget->hasAVX()">; 739def HasSSE2 : Predicate<"Subtarget->hasSSE2()">; 740def UseSSE2 : Predicate<"Subtarget->hasSSE2() && !Subtarget->hasAVX()">; 741def HasSSE3 : Predicate<"Subtarget->hasSSE3()">; 742def UseSSE3 : Predicate<"Subtarget->hasSSE3() && !Subtarget->hasAVX()">; 743def HasSSSE3 : Predicate<"Subtarget->hasSSSE3()">; 744def UseSSSE3 : Predicate<"Subtarget->hasSSSE3() && !Subtarget->hasAVX()">; 745def HasSSE41 : Predicate<"Subtarget->hasSSE41()">; 746def NoSSE41 : Predicate<"!Subtarget->hasSSE41()">; 747def UseSSE41 : Predicate<"Subtarget->hasSSE41() && !Subtarget->hasAVX()">; 748def HasSSE42 : Predicate<"Subtarget->hasSSE42()">; 749def UseSSE42 : Predicate<"Subtarget->hasSSE42() && !Subtarget->hasAVX()">; 750def HasSSE4A : Predicate<"Subtarget->hasSSE4A()">; 751def HasAVX : Predicate<"Subtarget->hasAVX()">; 752def HasAVX2 : Predicate<"Subtarget->hasAVX2()">; 753def HasAVX1Only : Predicate<"Subtarget->hasAVX() && !Subtarget->hasAVX2()">; 754def HasAVX512 : Predicate<"Subtarget->hasAVX512()">, 755 AssemblerPredicate<"FeatureAVX512", "AVX-512 ISA">; 756def UseAVX : Predicate<"Subtarget->hasAVX() && !Subtarget->hasAVX512()">; 757def UseAVX2 : Predicate<"Subtarget->hasAVX2() && !Subtarget->hasAVX512()">; 758def NoAVX512 : Predicate<"!Subtarget->hasAVX512()">; 759def HasCDI : Predicate<"Subtarget->hasCDI()">, 760 AssemblerPredicate<"FeatureCDI", "AVX-512 CD ISA">; 761def HasPFI : Predicate<"Subtarget->hasPFI()">, 762 AssemblerPredicate<"FeaturePFI", "AVX-512 PF ISA">; 763def HasERI : Predicate<"Subtarget->hasERI()">, 764 AssemblerPredicate<"FeatureERI", "AVX-512 ER ISA">; 765def HasDQI : Predicate<"Subtarget->hasDQI()">, 766 AssemblerPredicate<"FeatureDQI", "AVX-512 DQ ISA">; 767def NoDQI : Predicate<"!Subtarget->hasDQI()">; 768def HasBWI : Predicate<"Subtarget->hasBWI()">, 769 AssemblerPredicate<"FeatureBWI", "AVX-512 BW ISA">; 770def HasVLX : Predicate<"Subtarget->hasVLX()">, 771 AssemblerPredicate<"FeatureVLX", "AVX-512 VL ISA">; 772def NoVLX : Predicate<"!Subtarget->hasVLX()">; 773 774def HasPOPCNT : Predicate<"Subtarget->hasPOPCNT()">; 775def HasAES : Predicate<"Subtarget->hasAES()">; 776def HasPCLMUL : Predicate<"Subtarget->hasPCLMUL()">; 777def HasFMA : Predicate<"Subtarget->hasFMA()">; 778def UseFMAOnAVX : Predicate<"Subtarget->hasFMA() && !Subtarget->hasAVX512()">; 779def HasFMA4 : Predicate<"Subtarget->hasFMA4()">; 780def HasXOP : Predicate<"Subtarget->hasXOP()">; 781def HasTBM : Predicate<"Subtarget->hasTBM()">; 782def HasMOVBE : Predicate<"Subtarget->hasMOVBE()">; 783def HasRDRAND : Predicate<"Subtarget->hasRDRAND()">; 784def HasF16C : Predicate<"Subtarget->hasF16C()">; 785def HasFSGSBase : Predicate<"Subtarget->hasFSGSBase()">; 786def HasLZCNT : Predicate<"Subtarget->hasLZCNT()">; 787def HasBMI : Predicate<"Subtarget->hasBMI()">; 788def HasBMI2 : Predicate<"Subtarget->hasBMI2()">; 789def HasRTM : Predicate<"Subtarget->hasRTM()">; 790def HasHLE : Predicate<"Subtarget->hasHLE()">; 791def HasTSX : Predicate<"Subtarget->hasRTM() || Subtarget->hasHLE()">; 792def HasADX : Predicate<"Subtarget->hasADX()">; 793def HasSHA : Predicate<"Subtarget->hasSHA()">; 794def HasPRFCHW : Predicate<"Subtarget->hasPRFCHW()">; 795def HasRDSEED : Predicate<"Subtarget->hasRDSEED()">; 796def HasPrefetchW : Predicate<"Subtarget->hasPRFCHW()">; 797def FPStackf32 : Predicate<"!Subtarget->hasSSE1()">; 798def FPStackf64 : Predicate<"!Subtarget->hasSSE2()">; 799def HasMPX : Predicate<"Subtarget->hasMPX()">; 800def HasCmpxchg16b: Predicate<"Subtarget->hasCmpxchg16b()">; 801def Not64BitMode : Predicate<"!Subtarget->is64Bit()">, 802 AssemblerPredicate<"!Mode64Bit", "Not 64-bit mode">; 803def In64BitMode : Predicate<"Subtarget->is64Bit()">, 804 AssemblerPredicate<"Mode64Bit", "64-bit mode">; 805def IsLP64 : Predicate<"Subtarget->isTarget64BitLP64()">; 806def NotLP64 : Predicate<"!Subtarget->isTarget64BitLP64()">; 807def In16BitMode : Predicate<"Subtarget->is16Bit()">, 808 AssemblerPredicate<"Mode16Bit", "16-bit mode">; 809def Not16BitMode : Predicate<"!Subtarget->is16Bit()">, 810 AssemblerPredicate<"!Mode16Bit", "Not 16-bit mode">; 811def In32BitMode : Predicate<"Subtarget->is32Bit()">, 812 AssemblerPredicate<"Mode32Bit", "32-bit mode">; 813def IsWin64 : Predicate<"Subtarget->isTargetWin64()">; 814def NotWin64 : Predicate<"!Subtarget->isTargetWin64()">; 815def IsPS4 : Predicate<"Subtarget->isTargetPS4()">; 816def NotPS4 : Predicate<"!Subtarget->isTargetPS4()">; 817def IsNaCl : Predicate<"Subtarget->isTargetNaCl()">; 818def NotNaCl : Predicate<"!Subtarget->isTargetNaCl()">; 819def SmallCode : Predicate<"TM.getCodeModel() == CodeModel::Small">; 820def KernelCode : Predicate<"TM.getCodeModel() == CodeModel::Kernel">; 821def FarData : Predicate<"TM.getCodeModel() != CodeModel::Small &&" 822 "TM.getCodeModel() != CodeModel::Kernel">; 823def NearData : Predicate<"TM.getCodeModel() == CodeModel::Small ||" 824 "TM.getCodeModel() == CodeModel::Kernel">; 825def IsStatic : Predicate<"TM.getRelocationModel() == Reloc::Static">; 826def IsNotPIC : Predicate<"TM.getRelocationModel() != Reloc::PIC_">; 827def OptForSize : Predicate<"OptForSize">; 828def OptForSpeed : Predicate<"!OptForSize">; 829def FastBTMem : Predicate<"!Subtarget->isBTMemSlow()">; 830def CallImmAddr : Predicate<"Subtarget->IsLegalToCallImmediateAddr(TM)">; 831def FavorMemIndirectCall : Predicate<"!Subtarget->callRegIndirect()">; 832def NotSlowIncDec : Predicate<"!Subtarget->slowIncDec()">; 833def HasFastMem32 : Predicate<"!Subtarget->isUnalignedMem32Slow()">; 834 835//===----------------------------------------------------------------------===// 836// X86 Instruction Format Definitions. 837// 838 839include "X86InstrFormats.td" 840 841//===----------------------------------------------------------------------===// 842// Pattern fragments. 843// 844 845// X86 specific condition code. These correspond to CondCode in 846// X86InstrInfo.h. They must be kept in synch. 847def X86_COND_A : PatLeaf<(i8 0)>; // alt. COND_NBE 848def X86_COND_AE : PatLeaf<(i8 1)>; // alt. COND_NC 849def X86_COND_B : PatLeaf<(i8 2)>; // alt. COND_C 850def X86_COND_BE : PatLeaf<(i8 3)>; // alt. COND_NA 851def X86_COND_E : PatLeaf<(i8 4)>; // alt. COND_Z 852def X86_COND_G : PatLeaf<(i8 5)>; // alt. COND_NLE 853def X86_COND_GE : PatLeaf<(i8 6)>; // alt. COND_NL 854def X86_COND_L : PatLeaf<(i8 7)>; // alt. COND_NGE 855def X86_COND_LE : PatLeaf<(i8 8)>; // alt. COND_NG 856def X86_COND_NE : PatLeaf<(i8 9)>; // alt. COND_NZ 857def X86_COND_NO : PatLeaf<(i8 10)>; 858def X86_COND_NP : PatLeaf<(i8 11)>; // alt. COND_PO 859def X86_COND_NS : PatLeaf<(i8 12)>; 860def X86_COND_O : PatLeaf<(i8 13)>; 861def X86_COND_P : PatLeaf<(i8 14)>; // alt. COND_PE 862def X86_COND_S : PatLeaf<(i8 15)>; 863 864// Predicate used to help when pattern matching LZCNT/TZCNT. 865def X86_COND_E_OR_NE : ImmLeaf<i8, [{ 866 return (Imm == X86::COND_E) || (Imm == X86::COND_NE); 867}]>; 868 869 870def i16immSExt8 : ImmLeaf<i16, [{ return Imm == (int8_t)Imm; }]>; 871def i32immSExt8 : ImmLeaf<i32, [{ return Imm == (int8_t)Imm; }]>; 872def i64immSExt8 : ImmLeaf<i64, [{ return Imm == (int8_t)Imm; }]>; 873 874 875def i64immSExt32 : ImmLeaf<i64, [{ return Imm == (int32_t)Imm; }]>; 876 877 878// i64immZExt32 predicate - True if the 64-bit immediate fits in a 32-bit 879// unsigned field. 880def i64immZExt32 : ImmLeaf<i64, [{ return (uint64_t)Imm == (uint32_t)Imm; }]>; 881 882def i64immZExt32SExt8 : ImmLeaf<i64, [{ 883 return (uint64_t)Imm == (uint32_t)Imm && (int32_t)Imm == (int8_t)Imm; 884}]>; 885 886// Helper fragments for loads. 887// It's always safe to treat a anyext i16 load as a i32 load if the i16 is 888// known to be 32-bit aligned or better. Ditto for i8 to i16. 889def loadi16 : PatFrag<(ops node:$ptr), (i16 (unindexedload node:$ptr)), [{ 890 LoadSDNode *LD = cast<LoadSDNode>(N); 891 ISD::LoadExtType ExtType = LD->getExtensionType(); 892 if (ExtType == ISD::NON_EXTLOAD) 893 return true; 894 if (ExtType == ISD::EXTLOAD) 895 return LD->getAlignment() >= 2 && !LD->isVolatile(); 896 return false; 897}]>; 898 899def loadi16_anyext : PatFrag<(ops node:$ptr), (i32 (unindexedload node:$ptr)),[{ 900 LoadSDNode *LD = cast<LoadSDNode>(N); 901 ISD::LoadExtType ExtType = LD->getExtensionType(); 902 if (ExtType == ISD::EXTLOAD) 903 return LD->getAlignment() >= 2 && !LD->isVolatile(); 904 return false; 905}]>; 906 907def loadi32 : PatFrag<(ops node:$ptr), (i32 (unindexedload node:$ptr)), [{ 908 LoadSDNode *LD = cast<LoadSDNode>(N); 909 ISD::LoadExtType ExtType = LD->getExtensionType(); 910 if (ExtType == ISD::NON_EXTLOAD) 911 return true; 912 if (ExtType == ISD::EXTLOAD) 913 return LD->getAlignment() >= 4 && !LD->isVolatile(); 914 return false; 915}]>; 916 917def loadi8 : PatFrag<(ops node:$ptr), (i8 (load node:$ptr))>; 918def loadi64 : PatFrag<(ops node:$ptr), (i64 (load node:$ptr))>; 919def loadf32 : PatFrag<(ops node:$ptr), (f32 (load node:$ptr))>; 920def loadf64 : PatFrag<(ops node:$ptr), (f64 (load node:$ptr))>; 921def loadf80 : PatFrag<(ops node:$ptr), (f80 (load node:$ptr))>; 922 923def sextloadi16i8 : PatFrag<(ops node:$ptr), (i16 (sextloadi8 node:$ptr))>; 924def sextloadi32i8 : PatFrag<(ops node:$ptr), (i32 (sextloadi8 node:$ptr))>; 925def sextloadi32i16 : PatFrag<(ops node:$ptr), (i32 (sextloadi16 node:$ptr))>; 926def sextloadi64i8 : PatFrag<(ops node:$ptr), (i64 (sextloadi8 node:$ptr))>; 927def sextloadi64i16 : PatFrag<(ops node:$ptr), (i64 (sextloadi16 node:$ptr))>; 928def sextloadi64i32 : PatFrag<(ops node:$ptr), (i64 (sextloadi32 node:$ptr))>; 929 930def zextloadi8i1 : PatFrag<(ops node:$ptr), (i8 (zextloadi1 node:$ptr))>; 931def zextloadi16i1 : PatFrag<(ops node:$ptr), (i16 (zextloadi1 node:$ptr))>; 932def zextloadi32i1 : PatFrag<(ops node:$ptr), (i32 (zextloadi1 node:$ptr))>; 933def zextloadi16i8 : PatFrag<(ops node:$ptr), (i16 (zextloadi8 node:$ptr))>; 934def zextloadi32i8 : PatFrag<(ops node:$ptr), (i32 (zextloadi8 node:$ptr))>; 935def zextloadi32i16 : PatFrag<(ops node:$ptr), (i32 (zextloadi16 node:$ptr))>; 936def zextloadi64i1 : PatFrag<(ops node:$ptr), (i64 (zextloadi1 node:$ptr))>; 937def zextloadi64i8 : PatFrag<(ops node:$ptr), (i64 (zextloadi8 node:$ptr))>; 938def zextloadi64i16 : PatFrag<(ops node:$ptr), (i64 (zextloadi16 node:$ptr))>; 939def zextloadi64i32 : PatFrag<(ops node:$ptr), (i64 (zextloadi32 node:$ptr))>; 940 941def extloadi8i1 : PatFrag<(ops node:$ptr), (i8 (extloadi1 node:$ptr))>; 942def extloadi16i1 : PatFrag<(ops node:$ptr), (i16 (extloadi1 node:$ptr))>; 943def extloadi32i1 : PatFrag<(ops node:$ptr), (i32 (extloadi1 node:$ptr))>; 944def extloadi16i8 : PatFrag<(ops node:$ptr), (i16 (extloadi8 node:$ptr))>; 945def extloadi32i8 : PatFrag<(ops node:$ptr), (i32 (extloadi8 node:$ptr))>; 946def extloadi32i16 : PatFrag<(ops node:$ptr), (i32 (extloadi16 node:$ptr))>; 947def extloadi64i1 : PatFrag<(ops node:$ptr), (i64 (extloadi1 node:$ptr))>; 948def extloadi64i8 : PatFrag<(ops node:$ptr), (i64 (extloadi8 node:$ptr))>; 949def extloadi64i16 : PatFrag<(ops node:$ptr), (i64 (extloadi16 node:$ptr))>; 950def extloadi64i32 : PatFrag<(ops node:$ptr), (i64 (extloadi32 node:$ptr))>; 951 952 953// An 'and' node with a single use. 954def and_su : PatFrag<(ops node:$lhs, node:$rhs), (and node:$lhs, node:$rhs), [{ 955 return N->hasOneUse(); 956}]>; 957// An 'srl' node with a single use. 958def srl_su : PatFrag<(ops node:$lhs, node:$rhs), (srl node:$lhs, node:$rhs), [{ 959 return N->hasOneUse(); 960}]>; 961// An 'trunc' node with a single use. 962def trunc_su : PatFrag<(ops node:$src), (trunc node:$src), [{ 963 return N->hasOneUse(); 964}]>; 965 966//===----------------------------------------------------------------------===// 967// Instruction list. 968// 969 970// Nop 971let hasSideEffects = 0, SchedRW = [WriteZero] in { 972 def NOOP : I<0x90, RawFrm, (outs), (ins), "nop", [], IIC_NOP>; 973 def NOOPW : I<0x1f, MRMXm, (outs), (ins i16mem:$zero), 974 "nop{w}\t$zero", [], IIC_NOP>, TB, OpSize16; 975 def NOOPL : I<0x1f, MRMXm, (outs), (ins i32mem:$zero), 976 "nop{l}\t$zero", [], IIC_NOP>, TB, OpSize32; 977} 978 979 980// Constructing a stack frame. 981def ENTER : Ii16<0xC8, RawFrmImm8, (outs), (ins i16imm:$len, i8imm:$lvl), 982 "enter\t$len, $lvl", [], IIC_ENTER>, Sched<[WriteMicrocoded]>; 983 984let SchedRW = [WriteALU] in { 985let Defs = [EBP, ESP], Uses = [EBP, ESP], mayLoad = 1, hasSideEffects=0 in 986def LEAVE : I<0xC9, RawFrm, 987 (outs), (ins), "leave", [], IIC_LEAVE>, 988 Requires<[Not64BitMode]>; 989 990let Defs = [RBP,RSP], Uses = [RBP,RSP], mayLoad = 1, hasSideEffects = 0 in 991def LEAVE64 : I<0xC9, RawFrm, 992 (outs), (ins), "leave", [], IIC_LEAVE>, 993 Requires<[In64BitMode]>; 994} // SchedRW 995 996//===----------------------------------------------------------------------===// 997// Miscellaneous Instructions. 998// 999 1000let Defs = [ESP], Uses = [ESP], hasSideEffects=0 in { 1001let mayLoad = 1, SchedRW = [WriteLoad] in { 1002def POP16r : I<0x58, AddRegFrm, (outs GR16:$reg), (ins), "pop{w}\t$reg", [], 1003 IIC_POP_REG16>, OpSize16; 1004def POP32r : I<0x58, AddRegFrm, (outs GR32:$reg), (ins), "pop{l}\t$reg", [], 1005 IIC_POP_REG>, OpSize32, Requires<[Not64BitMode]>; 1006def POP16rmr: I<0x8F, MRM0r, (outs GR16:$reg), (ins), "pop{w}\t$reg", [], 1007 IIC_POP_REG>, OpSize16; 1008def POP16rmm: I<0x8F, MRM0m, (outs), (ins i16mem:$dst), "pop{w}\t$dst", [], 1009 IIC_POP_MEM>, OpSize16; 1010def POP32rmr: I<0x8F, MRM0r, (outs GR32:$reg), (ins), "pop{l}\t$reg", [], 1011 IIC_POP_REG>, OpSize32, Requires<[Not64BitMode]>; 1012def POP32rmm: I<0x8F, MRM0m, (outs), (ins i32mem:$dst), "pop{l}\t$dst", [], 1013 IIC_POP_MEM>, OpSize32, Requires<[Not64BitMode]>; 1014} // mayLoad, SchedRW 1015 1016let mayStore = 1, SchedRW = [WriteStore] in { 1017def PUSH16r : I<0x50, AddRegFrm, (outs), (ins GR16:$reg), "push{w}\t$reg",[], 1018 IIC_PUSH_REG>, OpSize16; 1019def PUSH32r : I<0x50, AddRegFrm, (outs), (ins GR32:$reg), "push{l}\t$reg",[], 1020 IIC_PUSH_REG>, OpSize32, Requires<[Not64BitMode]>; 1021def PUSH16rmr: I<0xFF, MRM6r, (outs), (ins GR16:$reg), "push{w}\t$reg",[], 1022 IIC_PUSH_REG>, OpSize16; 1023def PUSH16rmm: I<0xFF, MRM6m, (outs), (ins i16mem:$src), "push{w}\t$src",[], 1024 IIC_PUSH_MEM>, OpSize16; 1025def PUSH32rmr: I<0xFF, MRM6r, (outs), (ins GR32:$reg), "push{l}\t$reg",[], 1026 IIC_PUSH_REG>, OpSize32, Requires<[Not64BitMode]>; 1027def PUSH32rmm: I<0xFF, MRM6m, (outs), (ins i32mem:$src), "push{l}\t$src",[], 1028 IIC_PUSH_MEM>, OpSize32, Requires<[Not64BitMode]>; 1029 1030def PUSH16i8 : Ii8<0x6a, RawFrm, (outs), (ins i16i8imm:$imm), 1031 "push{w}\t$imm", [], IIC_PUSH_IMM>, OpSize16; 1032def PUSHi16 : Ii16<0x68, RawFrm, (outs), (ins i16imm:$imm), 1033 "push{w}\t$imm", [], IIC_PUSH_IMM>, OpSize16; 1034 1035def PUSH32i8 : Ii8<0x6a, RawFrm, (outs), (ins i32i8imm:$imm), 1036 "push{l}\t$imm", [], IIC_PUSH_IMM>, OpSize32, 1037 Requires<[Not64BitMode]>; 1038def PUSHi32 : Ii32<0x68, RawFrm, (outs), (ins i32imm:$imm), 1039 "push{l}\t$imm", [], IIC_PUSH_IMM>, OpSize32, 1040 Requires<[Not64BitMode]>; 1041} // mayStore, SchedRW 1042} 1043 1044let Defs = [ESP, EFLAGS], Uses = [ESP], mayLoad = 1, hasSideEffects=0, 1045 SchedRW = [WriteLoad] in { 1046def POPF16 : I<0x9D, RawFrm, (outs), (ins), "popf{w}", [], IIC_POP_F>, 1047 OpSize16; 1048def POPF32 : I<0x9D, RawFrm, (outs), (ins), "popf{l|d}", [], IIC_POP_FD>, 1049 OpSize32, Requires<[Not64BitMode]>; 1050} 1051 1052let Defs = [ESP], Uses = [ESP, EFLAGS], mayStore = 1, hasSideEffects=0, 1053 SchedRW = [WriteStore] in { 1054def PUSHF16 : I<0x9C, RawFrm, (outs), (ins), "pushf{w}", [], IIC_PUSH_F>, 1055 OpSize16; 1056def PUSHF32 : I<0x9C, RawFrm, (outs), (ins), "pushf{l|d}", [], IIC_PUSH_F>, 1057 OpSize32, Requires<[Not64BitMode]>; 1058} 1059 1060let Defs = [RSP], Uses = [RSP], hasSideEffects=0 in { 1061let mayLoad = 1, SchedRW = [WriteLoad] in { 1062def POP64r : I<0x58, AddRegFrm, (outs GR64:$reg), (ins), "pop{q}\t$reg", [], 1063 IIC_POP_REG>, OpSize32, Requires<[In64BitMode]>; 1064def POP64rmr: I<0x8F, MRM0r, (outs GR64:$reg), (ins), "pop{q}\t$reg", [], 1065 IIC_POP_REG>, OpSize32, Requires<[In64BitMode]>; 1066def POP64rmm: I<0x8F, MRM0m, (outs), (ins i64mem:$dst), "pop{q}\t$dst", [], 1067 IIC_POP_MEM>, OpSize32, Requires<[In64BitMode]>; 1068} // mayLoad, SchedRW 1069let mayStore = 1, SchedRW = [WriteStore] in { 1070def PUSH64r : I<0x50, AddRegFrm, (outs), (ins GR64:$reg), "push{q}\t$reg", [], 1071 IIC_PUSH_REG>, OpSize32, Requires<[In64BitMode]>; 1072def PUSH64rmr: I<0xFF, MRM6r, (outs), (ins GR64:$reg), "push{q}\t$reg", [], 1073 IIC_PUSH_REG>, OpSize32, Requires<[In64BitMode]>; 1074def PUSH64rmm: I<0xFF, MRM6m, (outs), (ins i64mem:$src), "push{q}\t$src", [], 1075 IIC_PUSH_MEM>, OpSize32, Requires<[In64BitMode]>; 1076} // mayStore, SchedRW 1077} 1078 1079let Defs = [RSP], Uses = [RSP], hasSideEffects = 0, mayStore = 1, 1080 SchedRW = [WriteStore] in { 1081def PUSH64i8 : Ii8<0x6a, RawFrm, (outs), (ins i64i8imm:$imm), 1082 "push{q}\t$imm", [], IIC_PUSH_IMM>, Requires<[In64BitMode]>; 1083def PUSH64i32 : Ii32S<0x68, RawFrm, (outs), (ins i64i32imm:$imm), 1084 "push{q}\t$imm", [], IIC_PUSH_IMM>, OpSize32, 1085 Requires<[In64BitMode]>; 1086} 1087 1088let Defs = [RSP, EFLAGS], Uses = [RSP], mayLoad = 1, hasSideEffects=0 in 1089def POPF64 : I<0x9D, RawFrm, (outs), (ins), "popfq", [], IIC_POP_FD>, 1090 OpSize32, Requires<[In64BitMode]>, Sched<[WriteLoad]>; 1091let Defs = [RSP], Uses = [RSP, EFLAGS], mayStore = 1, hasSideEffects=0 in 1092def PUSHF64 : I<0x9C, RawFrm, (outs), (ins), "pushfq", [], IIC_PUSH_F>, 1093 OpSize32, Requires<[In64BitMode]>, Sched<[WriteStore]>; 1094 1095let Defs = [EDI, ESI, EBP, EBX, EDX, ECX, EAX, ESP], Uses = [ESP], 1096 mayLoad = 1, hasSideEffects = 0, SchedRW = [WriteLoad] in { 1097def POPA32 : I<0x61, RawFrm, (outs), (ins), "popal", [], IIC_POP_A>, 1098 OpSize32, Requires<[Not64BitMode]>; 1099def POPA16 : I<0x61, RawFrm, (outs), (ins), "popaw", [], IIC_POP_A>, 1100 OpSize16, Requires<[Not64BitMode]>; 1101} 1102let Defs = [ESP], Uses = [EDI, ESI, EBP, EBX, EDX, ECX, EAX, ESP], 1103 mayStore = 1, hasSideEffects = 0, SchedRW = [WriteStore] in { 1104def PUSHA32 : I<0x60, RawFrm, (outs), (ins), "pushal", [], IIC_PUSH_A>, 1105 OpSize32, Requires<[Not64BitMode]>; 1106def PUSHA16 : I<0x60, RawFrm, (outs), (ins), "pushaw", [], IIC_PUSH_A>, 1107 OpSize16, Requires<[Not64BitMode]>; 1108} 1109 1110let Constraints = "$src = $dst", SchedRW = [WriteALU] in { 1111// GR32 = bswap GR32 1112def BSWAP32r : I<0xC8, AddRegFrm, 1113 (outs GR32:$dst), (ins GR32:$src), 1114 "bswap{l}\t$dst", 1115 [(set GR32:$dst, (bswap GR32:$src))], IIC_BSWAP>, OpSize32, TB; 1116 1117def BSWAP64r : RI<0xC8, AddRegFrm, (outs GR64:$dst), (ins GR64:$src), 1118 "bswap{q}\t$dst", 1119 [(set GR64:$dst, (bswap GR64:$src))], IIC_BSWAP>, TB; 1120} // Constraints = "$src = $dst", SchedRW 1121 1122// Bit scan instructions. 1123let Defs = [EFLAGS] in { 1124def BSF16rr : I<0xBC, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src), 1125 "bsf{w}\t{$src, $dst|$dst, $src}", 1126 [(set GR16:$dst, EFLAGS, (X86bsf GR16:$src))], 1127 IIC_BIT_SCAN_REG>, PS, OpSize16, Sched<[WriteShift]>; 1128def BSF16rm : I<0xBC, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src), 1129 "bsf{w}\t{$src, $dst|$dst, $src}", 1130 [(set GR16:$dst, EFLAGS, (X86bsf (loadi16 addr:$src)))], 1131 IIC_BIT_SCAN_MEM>, PS, OpSize16, Sched<[WriteShiftLd]>; 1132def BSF32rr : I<0xBC, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src), 1133 "bsf{l}\t{$src, $dst|$dst, $src}", 1134 [(set GR32:$dst, EFLAGS, (X86bsf GR32:$src))], 1135 IIC_BIT_SCAN_REG>, PS, OpSize32, Sched<[WriteShift]>; 1136def BSF32rm : I<0xBC, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src), 1137 "bsf{l}\t{$src, $dst|$dst, $src}", 1138 [(set GR32:$dst, EFLAGS, (X86bsf (loadi32 addr:$src)))], 1139 IIC_BIT_SCAN_MEM>, PS, OpSize32, Sched<[WriteShiftLd]>; 1140def BSF64rr : RI<0xBC, MRMSrcReg, (outs GR64:$dst), (ins GR64:$src), 1141 "bsf{q}\t{$src, $dst|$dst, $src}", 1142 [(set GR64:$dst, EFLAGS, (X86bsf GR64:$src))], 1143 IIC_BIT_SCAN_REG>, PS, Sched<[WriteShift]>; 1144def BSF64rm : RI<0xBC, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src), 1145 "bsf{q}\t{$src, $dst|$dst, $src}", 1146 [(set GR64:$dst, EFLAGS, (X86bsf (loadi64 addr:$src)))], 1147 IIC_BIT_SCAN_MEM>, PS, Sched<[WriteShiftLd]>; 1148 1149def BSR16rr : I<0xBD, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src), 1150 "bsr{w}\t{$src, $dst|$dst, $src}", 1151 [(set GR16:$dst, EFLAGS, (X86bsr GR16:$src))], 1152 IIC_BIT_SCAN_REG>, PS, OpSize16, Sched<[WriteShift]>; 1153def BSR16rm : I<0xBD, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src), 1154 "bsr{w}\t{$src, $dst|$dst, $src}", 1155 [(set GR16:$dst, EFLAGS, (X86bsr (loadi16 addr:$src)))], 1156 IIC_BIT_SCAN_MEM>, PS, OpSize16, Sched<[WriteShiftLd]>; 1157def BSR32rr : I<0xBD, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src), 1158 "bsr{l}\t{$src, $dst|$dst, $src}", 1159 [(set GR32:$dst, EFLAGS, (X86bsr GR32:$src))], 1160 IIC_BIT_SCAN_REG>, PS, OpSize32, Sched<[WriteShift]>; 1161def BSR32rm : I<0xBD, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src), 1162 "bsr{l}\t{$src, $dst|$dst, $src}", 1163 [(set GR32:$dst, EFLAGS, (X86bsr (loadi32 addr:$src)))], 1164 IIC_BIT_SCAN_MEM>, PS, OpSize32, Sched<[WriteShiftLd]>; 1165def BSR64rr : RI<0xBD, MRMSrcReg, (outs GR64:$dst), (ins GR64:$src), 1166 "bsr{q}\t{$src, $dst|$dst, $src}", 1167 [(set GR64:$dst, EFLAGS, (X86bsr GR64:$src))], 1168 IIC_BIT_SCAN_REG>, PS, Sched<[WriteShift]>; 1169def BSR64rm : RI<0xBD, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src), 1170 "bsr{q}\t{$src, $dst|$dst, $src}", 1171 [(set GR64:$dst, EFLAGS, (X86bsr (loadi64 addr:$src)))], 1172 IIC_BIT_SCAN_MEM>, PS, Sched<[WriteShiftLd]>; 1173} // Defs = [EFLAGS] 1174 1175let SchedRW = [WriteMicrocoded] in { 1176// These uses the DF flag in the EFLAGS register to inc or dec EDI and ESI 1177let Defs = [EDI,ESI], Uses = [EDI,ESI,EFLAGS] in { 1178def MOVSB : I<0xA4, RawFrmDstSrc, (outs dstidx8:$dst), (ins srcidx8:$src), 1179 "movsb\t{$src, $dst|$dst, $src}", [], IIC_MOVS>; 1180def MOVSW : I<0xA5, RawFrmDstSrc, (outs dstidx16:$dst), (ins srcidx16:$src), 1181 "movsw\t{$src, $dst|$dst, $src}", [], IIC_MOVS>, OpSize16; 1182def MOVSL : I<0xA5, RawFrmDstSrc, (outs dstidx32:$dst), (ins srcidx32:$src), 1183 "movs{l|d}\t{$src, $dst|$dst, $src}", [], IIC_MOVS>, OpSize32; 1184def MOVSQ : RI<0xA5, RawFrmDstSrc, (outs dstidx64:$dst), (ins srcidx64:$src), 1185 "movsq\t{$src, $dst|$dst, $src}", [], IIC_MOVS>; 1186} 1187 1188// These uses the DF flag in the EFLAGS register to inc or dec EDI and ESI 1189let Defs = [EDI], Uses = [AL,EDI,EFLAGS] in 1190def STOSB : I<0xAA, RawFrmDst, (outs dstidx8:$dst), (ins), 1191 "stosb\t{%al, $dst|$dst, al}", [], IIC_STOS>; 1192let Defs = [EDI], Uses = [AX,EDI,EFLAGS] in 1193def STOSW : I<0xAB, RawFrmDst, (outs dstidx16:$dst), (ins), 1194 "stosw\t{%ax, $dst|$dst, ax}", [], IIC_STOS>, OpSize16; 1195let Defs = [EDI], Uses = [EAX,EDI,EFLAGS] in 1196def STOSL : I<0xAB, RawFrmDst, (outs dstidx32:$dst), (ins), 1197 "stos{l|d}\t{%eax, $dst|$dst, eax}", [], IIC_STOS>, OpSize32; 1198let Defs = [RCX,RDI], Uses = [RAX,RCX,RDI,EFLAGS] in 1199def STOSQ : RI<0xAB, RawFrmDst, (outs dstidx64:$dst), (ins), 1200 "stosq\t{%rax, $dst|$dst, rax}", [], IIC_STOS>; 1201 1202// These uses the DF flag in the EFLAGS register to inc or dec EDI and ESI 1203let Defs = [EDI,EFLAGS], Uses = [AL,EDI,EFLAGS] in 1204def SCASB : I<0xAE, RawFrmDst, (outs), (ins dstidx8:$dst), 1205 "scasb\t{$dst, %al|al, $dst}", [], IIC_SCAS>; 1206let Defs = [EDI,EFLAGS], Uses = [AX,EDI,EFLAGS] in 1207def SCASW : I<0xAF, RawFrmDst, (outs), (ins dstidx16:$dst), 1208 "scasw\t{$dst, %ax|ax, $dst}", [], IIC_SCAS>, OpSize16; 1209let Defs = [EDI,EFLAGS], Uses = [EAX,EDI,EFLAGS] in 1210def SCASL : I<0xAF, RawFrmDst, (outs), (ins dstidx32:$dst), 1211 "scas{l|d}\t{$dst, %eax|eax, $dst}", [], IIC_SCAS>, OpSize32; 1212let Defs = [EDI,EFLAGS], Uses = [RAX,EDI,EFLAGS] in 1213def SCASQ : RI<0xAF, RawFrmDst, (outs), (ins dstidx64:$dst), 1214 "scasq\t{$dst, %rax|rax, $dst}", [], IIC_SCAS>; 1215 1216// These uses the DF flag in the EFLAGS register to inc or dec EDI and ESI 1217let Defs = [EDI,ESI,EFLAGS], Uses = [EDI,ESI,EFLAGS] in { 1218def CMPSB : I<0xA6, RawFrmDstSrc, (outs), (ins dstidx8:$dst, srcidx8:$src), 1219 "cmpsb\t{$dst, $src|$src, $dst}", [], IIC_CMPS>; 1220def CMPSW : I<0xA7, RawFrmDstSrc, (outs), (ins dstidx16:$dst, srcidx16:$src), 1221 "cmpsw\t{$dst, $src|$src, $dst}", [], IIC_CMPS>, OpSize16; 1222def CMPSL : I<0xA7, RawFrmDstSrc, (outs), (ins dstidx32:$dst, srcidx32:$src), 1223 "cmps{l|d}\t{$dst, $src|$src, $dst}", [], IIC_CMPS>, OpSize32; 1224def CMPSQ : RI<0xA7, RawFrmDstSrc, (outs), (ins dstidx64:$dst, srcidx64:$src), 1225 "cmpsq\t{$dst, $src|$src, $dst}", [], IIC_CMPS>; 1226} 1227} // SchedRW 1228 1229//===----------------------------------------------------------------------===// 1230// Move Instructions. 1231// 1232let SchedRW = [WriteMove] in { 1233let hasSideEffects = 0 in { 1234def MOV8rr : I<0x88, MRMDestReg, (outs GR8 :$dst), (ins GR8 :$src), 1235 "mov{b}\t{$src, $dst|$dst, $src}", [], IIC_MOV>; 1236def MOV16rr : I<0x89, MRMDestReg, (outs GR16:$dst), (ins GR16:$src), 1237 "mov{w}\t{$src, $dst|$dst, $src}", [], IIC_MOV>, OpSize16; 1238def MOV32rr : I<0x89, MRMDestReg, (outs GR32:$dst), (ins GR32:$src), 1239 "mov{l}\t{$src, $dst|$dst, $src}", [], IIC_MOV>, OpSize32; 1240def MOV64rr : RI<0x89, MRMDestReg, (outs GR64:$dst), (ins GR64:$src), 1241 "mov{q}\t{$src, $dst|$dst, $src}", [], IIC_MOV>; 1242} 1243 1244let isReMaterializable = 1, isAsCheapAsAMove = 1 in { 1245def MOV8ri : Ii8 <0xB0, AddRegFrm, (outs GR8 :$dst), (ins i8imm :$src), 1246 "mov{b}\t{$src, $dst|$dst, $src}", 1247 [(set GR8:$dst, imm:$src)], IIC_MOV>; 1248def MOV16ri : Ii16<0xB8, AddRegFrm, (outs GR16:$dst), (ins i16imm:$src), 1249 "mov{w}\t{$src, $dst|$dst, $src}", 1250 [(set GR16:$dst, imm:$src)], IIC_MOV>, OpSize16; 1251def MOV32ri : Ii32<0xB8, AddRegFrm, (outs GR32:$dst), (ins i32imm:$src), 1252 "mov{l}\t{$src, $dst|$dst, $src}", 1253 [(set GR32:$dst, imm:$src)], IIC_MOV>, OpSize32; 1254def MOV64ri32 : RIi32S<0xC7, MRM0r, (outs GR64:$dst), (ins i64i32imm:$src), 1255 "mov{q}\t{$src, $dst|$dst, $src}", 1256 [(set GR64:$dst, i64immSExt32:$src)], IIC_MOV>; 1257} 1258let isReMaterializable = 1 in { 1259def MOV64ri : RIi64<0xB8, AddRegFrm, (outs GR64:$dst), (ins i64imm:$src), 1260 "movabs{q}\t{$src, $dst|$dst, $src}", 1261 [(set GR64:$dst, imm:$src)], IIC_MOV>; 1262} 1263 1264// Longer forms that use a ModR/M byte. Needed for disassembler 1265let isCodeGenOnly = 1, ForceDisassemble = 1, hasSideEffects = 0 in { 1266def MOV8ri_alt : Ii8 <0xC6, MRM0r, (outs GR8 :$dst), (ins i8imm :$src), 1267 "mov{b}\t{$src, $dst|$dst, $src}", [], IIC_MOV>; 1268def MOV16ri_alt : Ii16<0xC7, MRM0r, (outs GR16:$dst), (ins i16imm:$src), 1269 "mov{w}\t{$src, $dst|$dst, $src}", [], IIC_MOV>, OpSize16; 1270def MOV32ri_alt : Ii32<0xC7, MRM0r, (outs GR32:$dst), (ins i32imm:$src), 1271 "mov{l}\t{$src, $dst|$dst, $src}", [], IIC_MOV>, OpSize32; 1272} 1273} // SchedRW 1274 1275let SchedRW = [WriteStore] in { 1276def MOV8mi : Ii8 <0xC6, MRM0m, (outs), (ins i8mem :$dst, i8imm :$src), 1277 "mov{b}\t{$src, $dst|$dst, $src}", 1278 [(store (i8 imm:$src), addr:$dst)], IIC_MOV_MEM>; 1279def MOV16mi : Ii16<0xC7, MRM0m, (outs), (ins i16mem:$dst, i16imm:$src), 1280 "mov{w}\t{$src, $dst|$dst, $src}", 1281 [(store (i16 imm:$src), addr:$dst)], IIC_MOV_MEM>, OpSize16; 1282def MOV32mi : Ii32<0xC7, MRM0m, (outs), (ins i32mem:$dst, i32imm:$src), 1283 "mov{l}\t{$src, $dst|$dst, $src}", 1284 [(store (i32 imm:$src), addr:$dst)], IIC_MOV_MEM>, OpSize32; 1285def MOV64mi32 : RIi32S<0xC7, MRM0m, (outs), (ins i64mem:$dst, i64i32imm:$src), 1286 "mov{q}\t{$src, $dst|$dst, $src}", 1287 [(store i64immSExt32:$src, addr:$dst)], IIC_MOV_MEM>; 1288} // SchedRW 1289 1290let hasSideEffects = 0 in { 1291 1292/// Memory offset versions of moves. The immediate is an address mode sized 1293/// offset from the segment base. 1294let SchedRW = [WriteALU] in { 1295let mayLoad = 1 in { 1296let Defs = [AL] in 1297def MOV8ao32 : Ii32<0xA0, RawFrmMemOffs, (outs), (ins offset32_8:$src), 1298 "mov{b}\t{$src, %al|al, $src}", [], IIC_MOV_MEM>, 1299 AdSize32; 1300let Defs = [AX] in 1301def MOV16ao32 : Ii32<0xA1, RawFrmMemOffs, (outs), (ins offset32_16:$src), 1302 "mov{w}\t{$src, %ax|ax, $src}", [], IIC_MOV_MEM>, 1303 OpSize16, AdSize32; 1304let Defs = [EAX] in 1305def MOV32ao32 : Ii32<0xA1, RawFrmMemOffs, (outs), (ins offset32_32:$src), 1306 "mov{l}\t{$src, %eax|eax, $src}", [], IIC_MOV_MEM>, 1307 OpSize32, AdSize32; 1308let Defs = [RAX] in 1309def MOV64ao32 : RIi32<0xA1, RawFrmMemOffs, (outs), (ins offset32_64:$src), 1310 "mov{q}\t{$src, %rax|rax, $src}", [], IIC_MOV_MEM>, 1311 AdSize32; 1312 1313let Defs = [AL] in 1314def MOV8ao16 : Ii16<0xA0, RawFrmMemOffs, (outs), (ins offset16_8:$src), 1315 "mov{b}\t{$src, %al|al, $src}", [], IIC_MOV_MEM>, AdSize16; 1316let Defs = [AX] in 1317def MOV16ao16 : Ii16<0xA1, RawFrmMemOffs, (outs), (ins offset16_16:$src), 1318 "mov{w}\t{$src, %ax|ax, $src}", [], IIC_MOV_MEM>, 1319 OpSize16, AdSize16; 1320let Defs = [EAX] in 1321def MOV32ao16 : Ii16<0xA1, RawFrmMemOffs, (outs), (ins offset16_32:$src), 1322 "mov{l}\t{$src, %eax|eax, $src}", [], IIC_MOV_MEM>, 1323 AdSize16, OpSize32; 1324} 1325let mayStore = 1 in { 1326let Uses = [AL] in 1327def MOV8o32a : Ii32<0xA2, RawFrmMemOffs, (outs offset32_8:$dst), (ins), 1328 "mov{b}\t{%al, $dst|$dst, al}", [], IIC_MOV_MEM>, AdSize32; 1329let Uses = [AX] in 1330def MOV16o32a : Ii32<0xA3, RawFrmMemOffs, (outs offset32_16:$dst), (ins), 1331 "mov{w}\t{%ax, $dst|$dst, ax}", [], IIC_MOV_MEM>, 1332 OpSize16, AdSize32; 1333let Uses = [EAX] in 1334def MOV32o32a : Ii32<0xA3, RawFrmMemOffs, (outs offset32_32:$dst), (ins), 1335 "mov{l}\t{%eax, $dst|$dst, eax}", [], IIC_MOV_MEM>, 1336 OpSize32, AdSize32; 1337let Uses = [RAX] in 1338def MOV64o32a : RIi32<0xA3, RawFrmMemOffs, (outs offset32_64:$dst), (ins), 1339 "mov{q}\t{%rax, $dst|$dst, rax}", [], IIC_MOV_MEM>, 1340 AdSize32; 1341 1342let Uses = [AL] in 1343def MOV8o16a : Ii16<0xA2, RawFrmMemOffs, (outs offset16_8:$dst), (ins), 1344 "mov{b}\t{%al, $dst|$dst, al}", [], IIC_MOV_MEM>, AdSize16; 1345let Uses = [AX] in 1346def MOV16o16a : Ii16<0xA3, RawFrmMemOffs, (outs offset16_16:$dst), (ins), 1347 "mov{w}\t{%ax, $dst|$dst, ax}", [], IIC_MOV_MEM>, 1348 OpSize16, AdSize16; 1349let Uses = [EAX] in 1350def MOV32o16a : Ii16<0xA3, RawFrmMemOffs, (outs offset16_32:$dst), (ins), 1351 "mov{l}\t{%eax, $dst|$dst, eax}", [], IIC_MOV_MEM>, 1352 OpSize32, AdSize16; 1353} 1354} 1355 1356// These forms all have full 64-bit absolute addresses in their instructions 1357// and use the movabs mnemonic to indicate this specific form. 1358let mayLoad = 1 in { 1359let Defs = [AL] in 1360def MOV8ao64 : RIi64_NOREX<0xA0, RawFrmMemOffs, (outs), (ins offset64_8:$src), 1361 "movabs{b}\t{$src, %al|al, $src}", []>, AdSize64; 1362let Defs = [AX] in 1363def MOV16ao64 : RIi64_NOREX<0xA1, RawFrmMemOffs, (outs), (ins offset64_16:$src), 1364 "movabs{w}\t{$src, %ax|ax, $src}", []>, OpSize16, AdSize64; 1365let Defs = [EAX] in 1366def MOV32ao64 : RIi64_NOREX<0xA1, RawFrmMemOffs, (outs), (ins offset64_32:$src), 1367 "movabs{l}\t{$src, %eax|eax, $src}", []>, OpSize32, 1368 AdSize64; 1369let Defs = [RAX] in 1370def MOV64ao64 : RIi64<0xA1, RawFrmMemOffs, (outs), (ins offset64_64:$src), 1371 "movabs{q}\t{$src, %rax|rax, $src}", []>, AdSize64; 1372} 1373 1374let mayStore = 1 in { 1375let Uses = [AL] in 1376def MOV8o64a : RIi64_NOREX<0xA2, RawFrmMemOffs, (outs offset64_8:$dst), (ins), 1377 "movabs{b}\t{%al, $dst|$dst, al}", []>, AdSize64; 1378let Uses = [AX] in 1379def MOV16o64a : RIi64_NOREX<0xA3, RawFrmMemOffs, (outs offset64_16:$dst), (ins), 1380 "movabs{w}\t{%ax, $dst|$dst, ax}", []>, OpSize16, AdSize64; 1381let Uses = [EAX] in 1382def MOV32o64a : RIi64_NOREX<0xA3, RawFrmMemOffs, (outs offset64_32:$dst), (ins), 1383 "movabs{l}\t{%eax, $dst|$dst, eax}", []>, OpSize32, 1384 AdSize64; 1385let Uses = [RAX] in 1386def MOV64o64a : RIi64<0xA3, RawFrmMemOffs, (outs offset64_64:$dst), (ins), 1387 "movabs{q}\t{%rax, $dst|$dst, rax}", []>, AdSize64; 1388} 1389} // hasSideEffects = 0 1390 1391let isCodeGenOnly = 1, ForceDisassemble = 1, hasSideEffects = 0, 1392 SchedRW = [WriteMove] in { 1393def MOV8rr_REV : I<0x8A, MRMSrcReg, (outs GR8:$dst), (ins GR8:$src), 1394 "mov{b}\t{$src, $dst|$dst, $src}", [], IIC_MOV>; 1395def MOV16rr_REV : I<0x8B, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src), 1396 "mov{w}\t{$src, $dst|$dst, $src}", [], IIC_MOV>, OpSize16; 1397def MOV32rr_REV : I<0x8B, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src), 1398 "mov{l}\t{$src, $dst|$dst, $src}", [], IIC_MOV>, OpSize32; 1399def MOV64rr_REV : RI<0x8B, MRMSrcReg, (outs GR64:$dst), (ins GR64:$src), 1400 "mov{q}\t{$src, $dst|$dst, $src}", [], IIC_MOV>; 1401} 1402 1403let canFoldAsLoad = 1, isReMaterializable = 1, SchedRW = [WriteLoad] in { 1404def MOV8rm : I<0x8A, MRMSrcMem, (outs GR8 :$dst), (ins i8mem :$src), 1405 "mov{b}\t{$src, $dst|$dst, $src}", 1406 [(set GR8:$dst, (loadi8 addr:$src))], IIC_MOV_MEM>; 1407def MOV16rm : I<0x8B, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src), 1408 "mov{w}\t{$src, $dst|$dst, $src}", 1409 [(set GR16:$dst, (loadi16 addr:$src))], IIC_MOV_MEM>, OpSize16; 1410def MOV32rm : I<0x8B, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src), 1411 "mov{l}\t{$src, $dst|$dst, $src}", 1412 [(set GR32:$dst, (loadi32 addr:$src))], IIC_MOV_MEM>, OpSize32; 1413def MOV64rm : RI<0x8B, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src), 1414 "mov{q}\t{$src, $dst|$dst, $src}", 1415 [(set GR64:$dst, (load addr:$src))], IIC_MOV_MEM>; 1416} 1417 1418let SchedRW = [WriteStore] in { 1419def MOV8mr : I<0x88, MRMDestMem, (outs), (ins i8mem :$dst, GR8 :$src), 1420 "mov{b}\t{$src, $dst|$dst, $src}", 1421 [(store GR8:$src, addr:$dst)], IIC_MOV_MEM>; 1422def MOV16mr : I<0x89, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src), 1423 "mov{w}\t{$src, $dst|$dst, $src}", 1424 [(store GR16:$src, addr:$dst)], IIC_MOV_MEM>, OpSize16; 1425def MOV32mr : I<0x89, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src), 1426 "mov{l}\t{$src, $dst|$dst, $src}", 1427 [(store GR32:$src, addr:$dst)], IIC_MOV_MEM>, OpSize32; 1428def MOV64mr : RI<0x89, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src), 1429 "mov{q}\t{$src, $dst|$dst, $src}", 1430 [(store GR64:$src, addr:$dst)], IIC_MOV_MEM>; 1431} // SchedRW 1432 1433// Versions of MOV8rr, MOV8mr, and MOV8rm that use i8mem_NOREX and GR8_NOREX so 1434// that they can be used for copying and storing h registers, which can't be 1435// encoded when a REX prefix is present. 1436let isCodeGenOnly = 1 in { 1437let hasSideEffects = 0 in 1438def MOV8rr_NOREX : I<0x88, MRMDestReg, 1439 (outs GR8_NOREX:$dst), (ins GR8_NOREX:$src), 1440 "mov{b}\t{$src, $dst|$dst, $src} # NOREX", [], IIC_MOV>, 1441 Sched<[WriteMove]>; 1442let mayStore = 1, hasSideEffects = 0 in 1443def MOV8mr_NOREX : I<0x88, MRMDestMem, 1444 (outs), (ins i8mem_NOREX:$dst, GR8_NOREX:$src), 1445 "mov{b}\t{$src, $dst|$dst, $src} # NOREX", [], 1446 IIC_MOV_MEM>, Sched<[WriteStore]>; 1447let mayLoad = 1, hasSideEffects = 0, 1448 canFoldAsLoad = 1, isReMaterializable = 1 in 1449def MOV8rm_NOREX : I<0x8A, MRMSrcMem, 1450 (outs GR8_NOREX:$dst), (ins i8mem_NOREX:$src), 1451 "mov{b}\t{$src, $dst|$dst, $src} # NOREX", [], 1452 IIC_MOV_MEM>, Sched<[WriteLoad]>; 1453} 1454 1455 1456// Condition code ops, incl. set if equal/not equal/... 1457let SchedRW = [WriteALU] in { 1458let Defs = [EFLAGS], Uses = [AH] in 1459def SAHF : I<0x9E, RawFrm, (outs), (ins), "sahf", 1460 [(set EFLAGS, (X86sahf AH))], IIC_AHF>; 1461let Defs = [AH], Uses = [EFLAGS], hasSideEffects = 0 in 1462def LAHF : I<0x9F, RawFrm, (outs), (ins), "lahf", [], 1463 IIC_AHF>; // AH = flags 1464} // SchedRW 1465 1466//===----------------------------------------------------------------------===// 1467// Bit tests instructions: BT, BTS, BTR, BTC. 1468 1469let Defs = [EFLAGS] in { 1470let SchedRW = [WriteALU] in { 1471def BT16rr : I<0xA3, MRMDestReg, (outs), (ins GR16:$src1, GR16:$src2), 1472 "bt{w}\t{$src2, $src1|$src1, $src2}", 1473 [(set EFLAGS, (X86bt GR16:$src1, GR16:$src2))], IIC_BT_RR>, 1474 OpSize16, TB; 1475def BT32rr : I<0xA3, MRMDestReg, (outs), (ins GR32:$src1, GR32:$src2), 1476 "bt{l}\t{$src2, $src1|$src1, $src2}", 1477 [(set EFLAGS, (X86bt GR32:$src1, GR32:$src2))], IIC_BT_RR>, 1478 OpSize32, TB; 1479def BT64rr : RI<0xA3, MRMDestReg, (outs), (ins GR64:$src1, GR64:$src2), 1480 "bt{q}\t{$src2, $src1|$src1, $src2}", 1481 [(set EFLAGS, (X86bt GR64:$src1, GR64:$src2))], IIC_BT_RR>, TB; 1482} // SchedRW 1483 1484// Unlike with the register+register form, the memory+register form of the 1485// bt instruction does not ignore the high bits of the index. From ISel's 1486// perspective, this is pretty bizarre. Make these instructions disassembly 1487// only for now. 1488 1489let mayLoad = 1, hasSideEffects = 0, SchedRW = [WriteALULd] in { 1490 def BT16mr : I<0xA3, MRMDestMem, (outs), (ins i16mem:$src1, GR16:$src2), 1491 "bt{w}\t{$src2, $src1|$src1, $src2}", 1492 // [(X86bt (loadi16 addr:$src1), GR16:$src2), 1493 // (implicit EFLAGS)] 1494 [], IIC_BT_MR 1495 >, OpSize16, TB, Requires<[FastBTMem]>; 1496 def BT32mr : I<0xA3, MRMDestMem, (outs), (ins i32mem:$src1, GR32:$src2), 1497 "bt{l}\t{$src2, $src1|$src1, $src2}", 1498 // [(X86bt (loadi32 addr:$src1), GR32:$src2), 1499 // (implicit EFLAGS)] 1500 [], IIC_BT_MR 1501 >, OpSize32, TB, Requires<[FastBTMem]>; 1502 def BT64mr : RI<0xA3, MRMDestMem, (outs), (ins i64mem:$src1, GR64:$src2), 1503 "bt{q}\t{$src2, $src1|$src1, $src2}", 1504 // [(X86bt (loadi64 addr:$src1), GR64:$src2), 1505 // (implicit EFLAGS)] 1506 [], IIC_BT_MR 1507 >, TB; 1508} 1509 1510let SchedRW = [WriteALU] in { 1511def BT16ri8 : Ii8<0xBA, MRM4r, (outs), (ins GR16:$src1, i16i8imm:$src2), 1512 "bt{w}\t{$src2, $src1|$src1, $src2}", 1513 [(set EFLAGS, (X86bt GR16:$src1, i16immSExt8:$src2))], 1514 IIC_BT_RI>, OpSize16, TB; 1515def BT32ri8 : Ii8<0xBA, MRM4r, (outs), (ins GR32:$src1, i32i8imm:$src2), 1516 "bt{l}\t{$src2, $src1|$src1, $src2}", 1517 [(set EFLAGS, (X86bt GR32:$src1, i32immSExt8:$src2))], 1518 IIC_BT_RI>, OpSize32, TB; 1519def BT64ri8 : RIi8<0xBA, MRM4r, (outs), (ins GR64:$src1, i64i8imm:$src2), 1520 "bt{q}\t{$src2, $src1|$src1, $src2}", 1521 [(set EFLAGS, (X86bt GR64:$src1, i64immSExt8:$src2))], 1522 IIC_BT_RI>, TB; 1523} // SchedRW 1524 1525// Note that these instructions don't need FastBTMem because that 1526// only applies when the other operand is in a register. When it's 1527// an immediate, bt is still fast. 1528let SchedRW = [WriteALU] in { 1529def BT16mi8 : Ii8<0xBA, MRM4m, (outs), (ins i16mem:$src1, i16i8imm:$src2), 1530 "bt{w}\t{$src2, $src1|$src1, $src2}", 1531 [(set EFLAGS, (X86bt (loadi16 addr:$src1), i16immSExt8:$src2)) 1532 ], IIC_BT_MI>, OpSize16, TB; 1533def BT32mi8 : Ii8<0xBA, MRM4m, (outs), (ins i32mem:$src1, i32i8imm:$src2), 1534 "bt{l}\t{$src2, $src1|$src1, $src2}", 1535 [(set EFLAGS, (X86bt (loadi32 addr:$src1), i32immSExt8:$src2)) 1536 ], IIC_BT_MI>, OpSize32, TB; 1537def BT64mi8 : RIi8<0xBA, MRM4m, (outs), (ins i64mem:$src1, i64i8imm:$src2), 1538 "bt{q}\t{$src2, $src1|$src1, $src2}", 1539 [(set EFLAGS, (X86bt (loadi64 addr:$src1), 1540 i64immSExt8:$src2))], IIC_BT_MI>, TB; 1541} // SchedRW 1542 1543let hasSideEffects = 0 in { 1544let SchedRW = [WriteALU] in { 1545def BTC16rr : I<0xBB, MRMDestReg, (outs), (ins GR16:$src1, GR16:$src2), 1546 "btc{w}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RR>, 1547 OpSize16, TB; 1548def BTC32rr : I<0xBB, MRMDestReg, (outs), (ins GR32:$src1, GR32:$src2), 1549 "btc{l}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RR>, 1550 OpSize32, TB; 1551def BTC64rr : RI<0xBB, MRMDestReg, (outs), (ins GR64:$src1, GR64:$src2), 1552 "btc{q}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RR>, TB; 1553} // SchedRW 1554 1555let mayLoad = 1, mayStore = 1, SchedRW = [WriteALULd, WriteRMW] in { 1556def BTC16mr : I<0xBB, MRMDestMem, (outs), (ins i16mem:$src1, GR16:$src2), 1557 "btc{w}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MR>, 1558 OpSize16, TB; 1559def BTC32mr : I<0xBB, MRMDestMem, (outs), (ins i32mem:$src1, GR32:$src2), 1560 "btc{l}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MR>, 1561 OpSize32, TB; 1562def BTC64mr : RI<0xBB, MRMDestMem, (outs), (ins i64mem:$src1, GR64:$src2), 1563 "btc{q}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MR>, TB; 1564} 1565 1566let SchedRW = [WriteALU] in { 1567def BTC16ri8 : Ii8<0xBA, MRM7r, (outs), (ins GR16:$src1, i16i8imm:$src2), 1568 "btc{w}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RI>, 1569 OpSize16, TB; 1570def BTC32ri8 : Ii8<0xBA, MRM7r, (outs), (ins GR32:$src1, i32i8imm:$src2), 1571 "btc{l}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RI>, 1572 OpSize32, TB; 1573def BTC64ri8 : RIi8<0xBA, MRM7r, (outs), (ins GR64:$src1, i64i8imm:$src2), 1574 "btc{q}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RI>, TB; 1575} // SchedRW 1576 1577let mayLoad = 1, mayStore = 1, SchedRW = [WriteALULd, WriteRMW] in { 1578def BTC16mi8 : Ii8<0xBA, MRM7m, (outs), (ins i16mem:$src1, i16i8imm:$src2), 1579 "btc{w}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MI>, 1580 OpSize16, TB; 1581def BTC32mi8 : Ii8<0xBA, MRM7m, (outs), (ins i32mem:$src1, i32i8imm:$src2), 1582 "btc{l}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MI>, 1583 OpSize32, TB; 1584def BTC64mi8 : RIi8<0xBA, MRM7m, (outs), (ins i64mem:$src1, i64i8imm:$src2), 1585 "btc{q}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MI>, TB; 1586} 1587 1588let SchedRW = [WriteALU] in { 1589def BTR16rr : I<0xB3, MRMDestReg, (outs), (ins GR16:$src1, GR16:$src2), 1590 "btr{w}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RR>, 1591 OpSize16, TB; 1592def BTR32rr : I<0xB3, MRMDestReg, (outs), (ins GR32:$src1, GR32:$src2), 1593 "btr{l}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RR>, 1594 OpSize32, TB; 1595def BTR64rr : RI<0xB3, MRMDestReg, (outs), (ins GR64:$src1, GR64:$src2), 1596 "btr{q}\t{$src2, $src1|$src1, $src2}", []>, TB; 1597} // SchedRW 1598 1599let mayLoad = 1, mayStore = 1, SchedRW = [WriteALULd, WriteRMW] in { 1600def BTR16mr : I<0xB3, MRMDestMem, (outs), (ins i16mem:$src1, GR16:$src2), 1601 "btr{w}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MR>, 1602 OpSize16, TB; 1603def BTR32mr : I<0xB3, MRMDestMem, (outs), (ins i32mem:$src1, GR32:$src2), 1604 "btr{l}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MR>, 1605 OpSize32, TB; 1606def BTR64mr : RI<0xB3, MRMDestMem, (outs), (ins i64mem:$src1, GR64:$src2), 1607 "btr{q}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MR>, TB; 1608} 1609 1610let SchedRW = [WriteALU] in { 1611def BTR16ri8 : Ii8<0xBA, MRM6r, (outs), (ins GR16:$src1, i16i8imm:$src2), 1612 "btr{w}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RI>, 1613 OpSize16, TB; 1614def BTR32ri8 : Ii8<0xBA, MRM6r, (outs), (ins GR32:$src1, i32i8imm:$src2), 1615 "btr{l}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RI>, 1616 OpSize32, TB; 1617def BTR64ri8 : RIi8<0xBA, MRM6r, (outs), (ins GR64:$src1, i64i8imm:$src2), 1618 "btr{q}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RI>, TB; 1619} // SchedRW 1620 1621let mayLoad = 1, mayStore = 1, SchedRW = [WriteALULd, WriteRMW] in { 1622def BTR16mi8 : Ii8<0xBA, MRM6m, (outs), (ins i16mem:$src1, i16i8imm:$src2), 1623 "btr{w}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MI>, 1624 OpSize16, TB; 1625def BTR32mi8 : Ii8<0xBA, MRM6m, (outs), (ins i32mem:$src1, i32i8imm:$src2), 1626 "btr{l}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MI>, 1627 OpSize32, TB; 1628def BTR64mi8 : RIi8<0xBA, MRM6m, (outs), (ins i64mem:$src1, i64i8imm:$src2), 1629 "btr{q}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MI>, TB; 1630} 1631 1632let SchedRW = [WriteALU] in { 1633def BTS16rr : I<0xAB, MRMDestReg, (outs), (ins GR16:$src1, GR16:$src2), 1634 "bts{w}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RR>, 1635 OpSize16, TB; 1636def BTS32rr : I<0xAB, MRMDestReg, (outs), (ins GR32:$src1, GR32:$src2), 1637 "bts{l}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RR>, 1638 OpSize32, TB; 1639def BTS64rr : RI<0xAB, MRMDestReg, (outs), (ins GR64:$src1, GR64:$src2), 1640 "bts{q}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RR>, TB; 1641} // SchedRW 1642 1643let mayLoad = 1, mayStore = 1, SchedRW = [WriteALULd, WriteRMW] in { 1644def BTS16mr : I<0xAB, MRMDestMem, (outs), (ins i16mem:$src1, GR16:$src2), 1645 "bts{w}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MR>, 1646 OpSize16, TB; 1647def BTS32mr : I<0xAB, MRMDestMem, (outs), (ins i32mem:$src1, GR32:$src2), 1648 "bts{l}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MR>, 1649 OpSize32, TB; 1650def BTS64mr : RI<0xAB, MRMDestMem, (outs), (ins i64mem:$src1, GR64:$src2), 1651 "bts{q}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MR>, TB; 1652} 1653 1654let SchedRW = [WriteALU] in { 1655def BTS16ri8 : Ii8<0xBA, MRM5r, (outs), (ins GR16:$src1, i16i8imm:$src2), 1656 "bts{w}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RI>, 1657 OpSize16, TB; 1658def BTS32ri8 : Ii8<0xBA, MRM5r, (outs), (ins GR32:$src1, i32i8imm:$src2), 1659 "bts{l}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RI>, 1660 OpSize32, TB; 1661def BTS64ri8 : RIi8<0xBA, MRM5r, (outs), (ins GR64:$src1, i64i8imm:$src2), 1662 "bts{q}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RI>, TB; 1663} // SchedRW 1664 1665let mayLoad = 1, mayStore = 1, SchedRW = [WriteALULd, WriteRMW] in { 1666def BTS16mi8 : Ii8<0xBA, MRM5m, (outs), (ins i16mem:$src1, i16i8imm:$src2), 1667 "bts{w}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MI>, 1668 OpSize16, TB; 1669def BTS32mi8 : Ii8<0xBA, MRM5m, (outs), (ins i32mem:$src1, i32i8imm:$src2), 1670 "bts{l}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MI>, 1671 OpSize32, TB; 1672def BTS64mi8 : RIi8<0xBA, MRM5m, (outs), (ins i64mem:$src1, i64i8imm:$src2), 1673 "bts{q}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MI>, TB; 1674} 1675} // hasSideEffects = 0 1676} // Defs = [EFLAGS] 1677 1678 1679//===----------------------------------------------------------------------===// 1680// Atomic support 1681// 1682 1683// Atomic swap. These are just normal xchg instructions. But since a memory 1684// operand is referenced, the atomicity is ensured. 1685multiclass ATOMIC_SWAP<bits<8> opc8, bits<8> opc, string mnemonic, string frag, 1686 InstrItinClass itin> { 1687 let Constraints = "$val = $dst", SchedRW = [WriteALULd, WriteRMW] in { 1688 def NAME#8rm : I<opc8, MRMSrcMem, (outs GR8:$dst), 1689 (ins GR8:$val, i8mem:$ptr), 1690 !strconcat(mnemonic, "{b}\t{$val, $ptr|$ptr, $val}"), 1691 [(set 1692 GR8:$dst, 1693 (!cast<PatFrag>(frag # "_8") addr:$ptr, GR8:$val))], 1694 itin>; 1695 def NAME#16rm : I<opc, MRMSrcMem, (outs GR16:$dst), 1696 (ins GR16:$val, i16mem:$ptr), 1697 !strconcat(mnemonic, "{w}\t{$val, $ptr|$ptr, $val}"), 1698 [(set 1699 GR16:$dst, 1700 (!cast<PatFrag>(frag # "_16") addr:$ptr, GR16:$val))], 1701 itin>, OpSize16; 1702 def NAME#32rm : I<opc, MRMSrcMem, (outs GR32:$dst), 1703 (ins GR32:$val, i32mem:$ptr), 1704 !strconcat(mnemonic, "{l}\t{$val, $ptr|$ptr, $val}"), 1705 [(set 1706 GR32:$dst, 1707 (!cast<PatFrag>(frag # "_32") addr:$ptr, GR32:$val))], 1708 itin>, OpSize32; 1709 def NAME#64rm : RI<opc, MRMSrcMem, (outs GR64:$dst), 1710 (ins GR64:$val, i64mem:$ptr), 1711 !strconcat(mnemonic, "{q}\t{$val, $ptr|$ptr, $val}"), 1712 [(set 1713 GR64:$dst, 1714 (!cast<PatFrag>(frag # "_64") addr:$ptr, GR64:$val))], 1715 itin>; 1716 } 1717} 1718 1719defm XCHG : ATOMIC_SWAP<0x86, 0x87, "xchg", "atomic_swap", IIC_XCHG_MEM>; 1720 1721// Swap between registers. 1722let SchedRW = [WriteALU] in { 1723let Constraints = "$val = $dst" in { 1724def XCHG8rr : I<0x86, MRMSrcReg, (outs GR8:$dst), (ins GR8:$val, GR8:$src), 1725 "xchg{b}\t{$val, $src|$src, $val}", [], IIC_XCHG_REG>; 1726def XCHG16rr : I<0x87, MRMSrcReg, (outs GR16:$dst), (ins GR16:$val, GR16:$src), 1727 "xchg{w}\t{$val, $src|$src, $val}", [], IIC_XCHG_REG>, 1728 OpSize16; 1729def XCHG32rr : I<0x87, MRMSrcReg, (outs GR32:$dst), (ins GR32:$val, GR32:$src), 1730 "xchg{l}\t{$val, $src|$src, $val}", [], IIC_XCHG_REG>, 1731 OpSize32; 1732def XCHG64rr : RI<0x87, MRMSrcReg, (outs GR64:$dst), (ins GR64:$val,GR64:$src), 1733 "xchg{q}\t{$val, $src|$src, $val}", [], IIC_XCHG_REG>; 1734} 1735 1736// Swap between EAX and other registers. 1737let Uses = [AX], Defs = [AX] in 1738def XCHG16ar : I<0x90, AddRegFrm, (outs), (ins GR16:$src), 1739 "xchg{w}\t{$src, %ax|ax, $src}", [], IIC_XCHG_REG>, OpSize16; 1740let Uses = [EAX], Defs = [EAX] in 1741def XCHG32ar : I<0x90, AddRegFrm, (outs), (ins GR32:$src), 1742 "xchg{l}\t{$src, %eax|eax, $src}", [], IIC_XCHG_REG>, 1743 OpSize32, Requires<[Not64BitMode]>; 1744let Uses = [EAX], Defs = [EAX] in 1745// Uses GR32_NOAX in 64-bit mode to prevent encoding using the 0x90 NOP encoding. 1746// xchg %eax, %eax needs to clear upper 32-bits of RAX so is not a NOP. 1747def XCHG32ar64 : I<0x90, AddRegFrm, (outs), (ins GR32_NOAX:$src), 1748 "xchg{l}\t{$src, %eax|eax, $src}", [], IIC_XCHG_REG>, 1749 OpSize32, Requires<[In64BitMode]>; 1750let Uses = [RAX], Defs = [RAX] in 1751def XCHG64ar : RI<0x90, AddRegFrm, (outs), (ins GR64:$src), 1752 "xchg{q}\t{$src, %rax|rax, $src}", [], IIC_XCHG_REG>; 1753} // SchedRW 1754 1755let SchedRW = [WriteALU] in { 1756def XADD8rr : I<0xC0, MRMDestReg, (outs GR8:$dst), (ins GR8:$src), 1757 "xadd{b}\t{$src, $dst|$dst, $src}", [], IIC_XADD_REG>, TB; 1758def XADD16rr : I<0xC1, MRMDestReg, (outs GR16:$dst), (ins GR16:$src), 1759 "xadd{w}\t{$src, $dst|$dst, $src}", [], IIC_XADD_REG>, TB, 1760 OpSize16; 1761def XADD32rr : I<0xC1, MRMDestReg, (outs GR32:$dst), (ins GR32:$src), 1762 "xadd{l}\t{$src, $dst|$dst, $src}", [], IIC_XADD_REG>, TB, 1763 OpSize32; 1764def XADD64rr : RI<0xC1, MRMDestReg, (outs GR64:$dst), (ins GR64:$src), 1765 "xadd{q}\t{$src, $dst|$dst, $src}", [], IIC_XADD_REG>, TB; 1766} // SchedRW 1767 1768let mayLoad = 1, mayStore = 1, SchedRW = [WriteALULd, WriteRMW] in { 1769def XADD8rm : I<0xC0, MRMDestMem, (outs), (ins i8mem:$dst, GR8:$src), 1770 "xadd{b}\t{$src, $dst|$dst, $src}", [], IIC_XADD_MEM>, TB; 1771def XADD16rm : I<0xC1, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src), 1772 "xadd{w}\t{$src, $dst|$dst, $src}", [], IIC_XADD_MEM>, TB, 1773 OpSize16; 1774def XADD32rm : I<0xC1, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src), 1775 "xadd{l}\t{$src, $dst|$dst, $src}", [], IIC_XADD_MEM>, TB, 1776 OpSize32; 1777def XADD64rm : RI<0xC1, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src), 1778 "xadd{q}\t{$src, $dst|$dst, $src}", [], IIC_XADD_MEM>, TB; 1779 1780} 1781 1782let SchedRW = [WriteALU] in { 1783def CMPXCHG8rr : I<0xB0, MRMDestReg, (outs GR8:$dst), (ins GR8:$src), 1784 "cmpxchg{b}\t{$src, $dst|$dst, $src}", [], 1785 IIC_CMPXCHG_REG8>, TB; 1786def CMPXCHG16rr : I<0xB1, MRMDestReg, (outs GR16:$dst), (ins GR16:$src), 1787 "cmpxchg{w}\t{$src, $dst|$dst, $src}", [], 1788 IIC_CMPXCHG_REG>, TB, OpSize16; 1789def CMPXCHG32rr : I<0xB1, MRMDestReg, (outs GR32:$dst), (ins GR32:$src), 1790 "cmpxchg{l}\t{$src, $dst|$dst, $src}", [], 1791 IIC_CMPXCHG_REG>, TB, OpSize32; 1792def CMPXCHG64rr : RI<0xB1, MRMDestReg, (outs GR64:$dst), (ins GR64:$src), 1793 "cmpxchg{q}\t{$src, $dst|$dst, $src}", [], 1794 IIC_CMPXCHG_REG>, TB; 1795} // SchedRW 1796 1797let SchedRW = [WriteALULd, WriteRMW] in { 1798let mayLoad = 1, mayStore = 1 in { 1799def CMPXCHG8rm : I<0xB0, MRMDestMem, (outs), (ins i8mem:$dst, GR8:$src), 1800 "cmpxchg{b}\t{$src, $dst|$dst, $src}", [], 1801 IIC_CMPXCHG_MEM8>, TB; 1802def CMPXCHG16rm : I<0xB1, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src), 1803 "cmpxchg{w}\t{$src, $dst|$dst, $src}", [], 1804 IIC_CMPXCHG_MEM>, TB, OpSize16; 1805def CMPXCHG32rm : I<0xB1, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src), 1806 "cmpxchg{l}\t{$src, $dst|$dst, $src}", [], 1807 IIC_CMPXCHG_MEM>, TB, OpSize32; 1808def CMPXCHG64rm : RI<0xB1, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src), 1809 "cmpxchg{q}\t{$src, $dst|$dst, $src}", [], 1810 IIC_CMPXCHG_MEM>, TB; 1811} 1812 1813let Defs = [EAX, EDX, EFLAGS], Uses = [EAX, EBX, ECX, EDX] in 1814def CMPXCHG8B : I<0xC7, MRM1m, (outs), (ins i64mem:$dst), 1815 "cmpxchg8b\t$dst", [], IIC_CMPXCHG_8B>, TB; 1816 1817let Defs = [RAX, RDX, EFLAGS], Uses = [RAX, RBX, RCX, RDX] in 1818def CMPXCHG16B : RI<0xC7, MRM1m, (outs), (ins i128mem:$dst), 1819 "cmpxchg16b\t$dst", [], IIC_CMPXCHG_16B>, 1820 TB, Requires<[HasCmpxchg16b]>; 1821} // SchedRW 1822 1823 1824// Lock instruction prefix 1825def LOCK_PREFIX : I<0xF0, RawFrm, (outs), (ins), "lock", []>; 1826 1827// Rex64 instruction prefix 1828def REX64_PREFIX : I<0x48, RawFrm, (outs), (ins), "rex64", []>, 1829 Requires<[In64BitMode]>; 1830 1831// Data16 instruction prefix 1832def DATA16_PREFIX : I<0x66, RawFrm, (outs), (ins), "data16", []>; 1833 1834// Repeat string operation instruction prefixes 1835// These uses the DF flag in the EFLAGS register to inc or dec ECX 1836let Defs = [ECX], Uses = [ECX,EFLAGS] in { 1837// Repeat (used with INS, OUTS, MOVS, LODS and STOS) 1838def REP_PREFIX : I<0xF3, RawFrm, (outs), (ins), "rep", []>; 1839// Repeat while not equal (used with CMPS and SCAS) 1840def REPNE_PREFIX : I<0xF2, RawFrm, (outs), (ins), "repne", []>; 1841} 1842 1843 1844// String manipulation instructions 1845let SchedRW = [WriteMicrocoded] in { 1846// These uses the DF flag in the EFLAGS register to inc or dec EDI and ESI 1847let Defs = [AL,ESI], Uses = [ESI,EFLAGS] in 1848def LODSB : I<0xAC, RawFrmSrc, (outs), (ins srcidx8:$src), 1849 "lodsb\t{$src, %al|al, $src}", [], IIC_LODS>; 1850let Defs = [AX,ESI], Uses = [ESI,EFLAGS] in 1851def LODSW : I<0xAD, RawFrmSrc, (outs), (ins srcidx16:$src), 1852 "lodsw\t{$src, %ax|ax, $src}", [], IIC_LODS>, OpSize16; 1853let Defs = [EAX,ESI], Uses = [ESI,EFLAGS] in 1854def LODSL : I<0xAD, RawFrmSrc, (outs), (ins srcidx32:$src), 1855 "lods{l|d}\t{$src, %eax|eax, $src}", [], IIC_LODS>, OpSize32; 1856let Defs = [RAX,ESI], Uses = [ESI,EFLAGS] in 1857def LODSQ : RI<0xAD, RawFrmSrc, (outs), (ins srcidx64:$src), 1858 "lodsq\t{$src, %rax|rax, $src}", [], IIC_LODS>; 1859} 1860 1861let SchedRW = [WriteSystem] in { 1862// These uses the DF flag in the EFLAGS register to inc or dec EDI and ESI 1863let Defs = [ESI], Uses = [DX,ESI,EFLAGS] in { 1864def OUTSB : I<0x6E, RawFrmSrc, (outs), (ins srcidx8:$src), 1865 "outsb\t{$src, %dx|dx, $src}", [], IIC_OUTS>; 1866def OUTSW : I<0x6F, RawFrmSrc, (outs), (ins srcidx16:$src), 1867 "outsw\t{$src, %dx|dx, $src}", [], IIC_OUTS>, OpSize16; 1868def OUTSL : I<0x6F, RawFrmSrc, (outs), (ins srcidx32:$src), 1869 "outs{l|d}\t{$src, %dx|dx, $src}", [], IIC_OUTS>, OpSize32; 1870} 1871 1872// These uses the DF flag in the EFLAGS register to inc or dec EDI and ESI 1873let Defs = [EDI], Uses = [DX,EDI,EFLAGS] in { 1874def INSB : I<0x6C, RawFrmDst, (outs dstidx8:$dst), (ins), 1875 "insb\t{%dx, $dst|$dst, dx}", [], IIC_INS>; 1876def INSW : I<0x6D, RawFrmDst, (outs dstidx16:$dst), (ins), 1877 "insw\t{%dx, $dst|$dst, dx}", [], IIC_INS>, OpSize16; 1878def INSL : I<0x6D, RawFrmDst, (outs dstidx32:$dst), (ins), 1879 "ins{l|d}\t{%dx, $dst|$dst, dx}", [], IIC_INS>, OpSize32; 1880} 1881} 1882 1883// Flag instructions 1884let SchedRW = [WriteALU] in { 1885def CLC : I<0xF8, RawFrm, (outs), (ins), "clc", [], IIC_CLC>; 1886def STC : I<0xF9, RawFrm, (outs), (ins), "stc", [], IIC_STC>; 1887def CLI : I<0xFA, RawFrm, (outs), (ins), "cli", [], IIC_CLI>; 1888def STI : I<0xFB, RawFrm, (outs), (ins), "sti", [], IIC_STI>; 1889def CLD : I<0xFC, RawFrm, (outs), (ins), "cld", [], IIC_CLD>; 1890def STD : I<0xFD, RawFrm, (outs), (ins), "std", [], IIC_STD>; 1891def CMC : I<0xF5, RawFrm, (outs), (ins), "cmc", [], IIC_CMC>; 1892 1893def CLTS : I<0x06, RawFrm, (outs), (ins), "clts", [], IIC_CLTS>, TB; 1894} 1895 1896// Table lookup instructions 1897def XLAT : I<0xD7, RawFrm, (outs), (ins), "xlatb", [], IIC_XLAT>, 1898 Sched<[WriteLoad]>; 1899 1900let SchedRW = [WriteMicrocoded] in { 1901// ASCII Adjust After Addition 1902// sets AL, AH and CF and AF of EFLAGS and uses AL and AF of EFLAGS 1903def AAA : I<0x37, RawFrm, (outs), (ins), "aaa", [], IIC_AAA>, 1904 Requires<[Not64BitMode]>; 1905 1906// ASCII Adjust AX Before Division 1907// sets AL, AH and EFLAGS and uses AL and AH 1908def AAD8i8 : Ii8<0xD5, RawFrm, (outs), (ins i8imm:$src), 1909 "aad\t$src", [], IIC_AAD>, Requires<[Not64BitMode]>; 1910 1911// ASCII Adjust AX After Multiply 1912// sets AL, AH and EFLAGS and uses AL 1913def AAM8i8 : Ii8<0xD4, RawFrm, (outs), (ins i8imm:$src), 1914 "aam\t$src", [], IIC_AAM>, Requires<[Not64BitMode]>; 1915 1916// ASCII Adjust AL After Subtraction - sets 1917// sets AL, AH and CF and AF of EFLAGS and uses AL and AF of EFLAGS 1918def AAS : I<0x3F, RawFrm, (outs), (ins), "aas", [], IIC_AAS>, 1919 Requires<[Not64BitMode]>; 1920 1921// Decimal Adjust AL after Addition 1922// sets AL, CF and AF of EFLAGS and uses AL, CF and AF of EFLAGS 1923def DAA : I<0x27, RawFrm, (outs), (ins), "daa", [], IIC_DAA>, 1924 Requires<[Not64BitMode]>; 1925 1926// Decimal Adjust AL after Subtraction 1927// sets AL, CF and AF of EFLAGS and uses AL, CF and AF of EFLAGS 1928def DAS : I<0x2F, RawFrm, (outs), (ins), "das", [], IIC_DAS>, 1929 Requires<[Not64BitMode]>; 1930} // SchedRW 1931 1932let SchedRW = [WriteSystem] in { 1933// Check Array Index Against Bounds 1934def BOUNDS16rm : I<0x62, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src), 1935 "bound\t{$src, $dst|$dst, $src}", [], IIC_BOUND>, OpSize16, 1936 Requires<[Not64BitMode]>; 1937def BOUNDS32rm : I<0x62, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src), 1938 "bound\t{$src, $dst|$dst, $src}", [], IIC_BOUND>, OpSize32, 1939 Requires<[Not64BitMode]>; 1940 1941// Adjust RPL Field of Segment Selector 1942def ARPL16rr : I<0x63, MRMDestReg, (outs GR16:$dst), (ins GR16:$src), 1943 "arpl\t{$src, $dst|$dst, $src}", [], IIC_ARPL_REG>, 1944 Requires<[Not64BitMode]>; 1945def ARPL16mr : I<0x63, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src), 1946 "arpl\t{$src, $dst|$dst, $src}", [], IIC_ARPL_MEM>, 1947 Requires<[Not64BitMode]>; 1948} // SchedRW 1949 1950//===----------------------------------------------------------------------===// 1951// MOVBE Instructions 1952// 1953let Predicates = [HasMOVBE] in { 1954 let SchedRW = [WriteALULd] in { 1955 def MOVBE16rm : I<0xF0, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src), 1956 "movbe{w}\t{$src, $dst|$dst, $src}", 1957 [(set GR16:$dst, (bswap (loadi16 addr:$src)))], IIC_MOVBE>, 1958 OpSize16, T8PS; 1959 def MOVBE32rm : I<0xF0, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src), 1960 "movbe{l}\t{$src, $dst|$dst, $src}", 1961 [(set GR32:$dst, (bswap (loadi32 addr:$src)))], IIC_MOVBE>, 1962 OpSize32, T8PS; 1963 def MOVBE64rm : RI<0xF0, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src), 1964 "movbe{q}\t{$src, $dst|$dst, $src}", 1965 [(set GR64:$dst, (bswap (loadi64 addr:$src)))], IIC_MOVBE>, 1966 T8PS; 1967 } 1968 let SchedRW = [WriteStore] in { 1969 def MOVBE16mr : I<0xF1, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src), 1970 "movbe{w}\t{$src, $dst|$dst, $src}", 1971 [(store (bswap GR16:$src), addr:$dst)], IIC_MOVBE>, 1972 OpSize16, T8PS; 1973 def MOVBE32mr : I<0xF1, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src), 1974 "movbe{l}\t{$src, $dst|$dst, $src}", 1975 [(store (bswap GR32:$src), addr:$dst)], IIC_MOVBE>, 1976 OpSize32, T8PS; 1977 def MOVBE64mr : RI<0xF1, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src), 1978 "movbe{q}\t{$src, $dst|$dst, $src}", 1979 [(store (bswap GR64:$src), addr:$dst)], IIC_MOVBE>, 1980 T8PS; 1981 } 1982} 1983 1984//===----------------------------------------------------------------------===// 1985// RDRAND Instruction 1986// 1987let Predicates = [HasRDRAND], Defs = [EFLAGS] in { 1988 def RDRAND16r : I<0xC7, MRM6r, (outs GR16:$dst), (ins), 1989 "rdrand{w}\t$dst", 1990 [(set GR16:$dst, EFLAGS, (X86rdrand))]>, OpSize16, TB; 1991 def RDRAND32r : I<0xC7, MRM6r, (outs GR32:$dst), (ins), 1992 "rdrand{l}\t$dst", 1993 [(set GR32:$dst, EFLAGS, (X86rdrand))]>, OpSize32, TB; 1994 def RDRAND64r : RI<0xC7, MRM6r, (outs GR64:$dst), (ins), 1995 "rdrand{q}\t$dst", 1996 [(set GR64:$dst, EFLAGS, (X86rdrand))]>, TB; 1997} 1998 1999//===----------------------------------------------------------------------===// 2000// RDSEED Instruction 2001// 2002let Predicates = [HasRDSEED], Defs = [EFLAGS] in { 2003 def RDSEED16r : I<0xC7, MRM7r, (outs GR16:$dst), (ins), 2004 "rdseed{w}\t$dst", 2005 [(set GR16:$dst, EFLAGS, (X86rdseed))]>, OpSize16, TB; 2006 def RDSEED32r : I<0xC7, MRM7r, (outs GR32:$dst), (ins), 2007 "rdseed{l}\t$dst", 2008 [(set GR32:$dst, EFLAGS, (X86rdseed))]>, OpSize32, TB; 2009 def RDSEED64r : RI<0xC7, MRM7r, (outs GR64:$dst), (ins), 2010 "rdseed{q}\t$dst", 2011 [(set GR64:$dst, EFLAGS, (X86rdseed))]>, TB; 2012} 2013 2014//===----------------------------------------------------------------------===// 2015// LZCNT Instruction 2016// 2017let Predicates = [HasLZCNT], Defs = [EFLAGS] in { 2018 def LZCNT16rr : I<0xBD, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src), 2019 "lzcnt{w}\t{$src, $dst|$dst, $src}", 2020 [(set GR16:$dst, (ctlz GR16:$src)), (implicit EFLAGS)]>, XS, 2021 OpSize16; 2022 def LZCNT16rm : I<0xBD, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src), 2023 "lzcnt{w}\t{$src, $dst|$dst, $src}", 2024 [(set GR16:$dst, (ctlz (loadi16 addr:$src))), 2025 (implicit EFLAGS)]>, XS, OpSize16; 2026 2027 def LZCNT32rr : I<0xBD, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src), 2028 "lzcnt{l}\t{$src, $dst|$dst, $src}", 2029 [(set GR32:$dst, (ctlz GR32:$src)), (implicit EFLAGS)]>, XS, 2030 OpSize32; 2031 def LZCNT32rm : I<0xBD, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src), 2032 "lzcnt{l}\t{$src, $dst|$dst, $src}", 2033 [(set GR32:$dst, (ctlz (loadi32 addr:$src))), 2034 (implicit EFLAGS)]>, XS, OpSize32; 2035 2036 def LZCNT64rr : RI<0xBD, MRMSrcReg, (outs GR64:$dst), (ins GR64:$src), 2037 "lzcnt{q}\t{$src, $dst|$dst, $src}", 2038 [(set GR64:$dst, (ctlz GR64:$src)), (implicit EFLAGS)]>, 2039 XS; 2040 def LZCNT64rm : RI<0xBD, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src), 2041 "lzcnt{q}\t{$src, $dst|$dst, $src}", 2042 [(set GR64:$dst, (ctlz (loadi64 addr:$src))), 2043 (implicit EFLAGS)]>, XS; 2044} 2045 2046let Predicates = [HasLZCNT] in { 2047 def : Pat<(X86cmov (ctlz GR16:$src), (i16 16), (X86_COND_E_OR_NE), 2048 (X86cmp GR16:$src, (i16 0))), 2049 (LZCNT16rr GR16:$src)>; 2050 def : Pat<(X86cmov (ctlz GR32:$src), (i32 32), (X86_COND_E_OR_NE), 2051 (X86cmp GR32:$src, (i32 0))), 2052 (LZCNT32rr GR32:$src)>; 2053 def : Pat<(X86cmov (ctlz GR64:$src), (i64 64), (X86_COND_E_OR_NE), 2054 (X86cmp GR64:$src, (i64 0))), 2055 (LZCNT64rr GR64:$src)>; 2056 def : Pat<(X86cmov (i16 16), (ctlz GR16:$src), (X86_COND_E_OR_NE), 2057 (X86cmp GR16:$src, (i16 0))), 2058 (LZCNT16rr GR16:$src)>; 2059 def : Pat<(X86cmov (i32 32), (ctlz GR32:$src), (X86_COND_E_OR_NE), 2060 (X86cmp GR32:$src, (i32 0))), 2061 (LZCNT32rr GR32:$src)>; 2062 def : Pat<(X86cmov (i64 64), (ctlz GR64:$src), (X86_COND_E_OR_NE), 2063 (X86cmp GR64:$src, (i64 0))), 2064 (LZCNT64rr GR64:$src)>; 2065 2066 def : Pat<(X86cmov (ctlz (loadi16 addr:$src)), (i16 16), (X86_COND_E_OR_NE), 2067 (X86cmp (loadi16 addr:$src), (i16 0))), 2068 (LZCNT16rm addr:$src)>; 2069 def : Pat<(X86cmov (ctlz (loadi32 addr:$src)), (i32 32), (X86_COND_E_OR_NE), 2070 (X86cmp (loadi32 addr:$src), (i32 0))), 2071 (LZCNT32rm addr:$src)>; 2072 def : Pat<(X86cmov (ctlz (loadi64 addr:$src)), (i64 64), (X86_COND_E_OR_NE), 2073 (X86cmp (loadi64 addr:$src), (i64 0))), 2074 (LZCNT64rm addr:$src)>; 2075 def : Pat<(X86cmov (i16 16), (ctlz (loadi16 addr:$src)), (X86_COND_E_OR_NE), 2076 (X86cmp (loadi16 addr:$src), (i16 0))), 2077 (LZCNT16rm addr:$src)>; 2078 def : Pat<(X86cmov (i32 32), (ctlz (loadi32 addr:$src)), (X86_COND_E_OR_NE), 2079 (X86cmp (loadi32 addr:$src), (i32 0))), 2080 (LZCNT32rm addr:$src)>; 2081 def : Pat<(X86cmov (i64 64), (ctlz (loadi64 addr:$src)), (X86_COND_E_OR_NE), 2082 (X86cmp (loadi64 addr:$src), (i64 0))), 2083 (LZCNT64rm addr:$src)>; 2084} 2085 2086//===----------------------------------------------------------------------===// 2087// BMI Instructions 2088// 2089let Predicates = [HasBMI], Defs = [EFLAGS] in { 2090 def TZCNT16rr : I<0xBC, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src), 2091 "tzcnt{w}\t{$src, $dst|$dst, $src}", 2092 [(set GR16:$dst, (cttz GR16:$src)), (implicit EFLAGS)]>, XS, 2093 OpSize16; 2094 def TZCNT16rm : I<0xBC, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src), 2095 "tzcnt{w}\t{$src, $dst|$dst, $src}", 2096 [(set GR16:$dst, (cttz (loadi16 addr:$src))), 2097 (implicit EFLAGS)]>, XS, OpSize16; 2098 2099 def TZCNT32rr : I<0xBC, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src), 2100 "tzcnt{l}\t{$src, $dst|$dst, $src}", 2101 [(set GR32:$dst, (cttz GR32:$src)), (implicit EFLAGS)]>, XS, 2102 OpSize32; 2103 def TZCNT32rm : I<0xBC, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src), 2104 "tzcnt{l}\t{$src, $dst|$dst, $src}", 2105 [(set GR32:$dst, (cttz (loadi32 addr:$src))), 2106 (implicit EFLAGS)]>, XS, OpSize32; 2107 2108 def TZCNT64rr : RI<0xBC, MRMSrcReg, (outs GR64:$dst), (ins GR64:$src), 2109 "tzcnt{q}\t{$src, $dst|$dst, $src}", 2110 [(set GR64:$dst, (cttz GR64:$src)), (implicit EFLAGS)]>, 2111 XS; 2112 def TZCNT64rm : RI<0xBC, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src), 2113 "tzcnt{q}\t{$src, $dst|$dst, $src}", 2114 [(set GR64:$dst, (cttz (loadi64 addr:$src))), 2115 (implicit EFLAGS)]>, XS; 2116} 2117 2118multiclass bmi_bls<string mnemonic, Format RegMRM, Format MemMRM, 2119 RegisterClass RC, X86MemOperand x86memop> { 2120let hasSideEffects = 0 in { 2121 def rr : I<0xF3, RegMRM, (outs RC:$dst), (ins RC:$src), 2122 !strconcat(mnemonic, "\t{$src, $dst|$dst, $src}"), 2123 []>, T8PS, VEX_4V; 2124 let mayLoad = 1 in 2125 def rm : I<0xF3, MemMRM, (outs RC:$dst), (ins x86memop:$src), 2126 !strconcat(mnemonic, "\t{$src, $dst|$dst, $src}"), 2127 []>, T8PS, VEX_4V; 2128} 2129} 2130 2131let Predicates = [HasBMI], Defs = [EFLAGS] in { 2132 defm BLSR32 : bmi_bls<"blsr{l}", MRM1r, MRM1m, GR32, i32mem>; 2133 defm BLSR64 : bmi_bls<"blsr{q}", MRM1r, MRM1m, GR64, i64mem>, VEX_W; 2134 defm BLSMSK32 : bmi_bls<"blsmsk{l}", MRM2r, MRM2m, GR32, i32mem>; 2135 defm BLSMSK64 : bmi_bls<"blsmsk{q}", MRM2r, MRM2m, GR64, i64mem>, VEX_W; 2136 defm BLSI32 : bmi_bls<"blsi{l}", MRM3r, MRM3m, GR32, i32mem>; 2137 defm BLSI64 : bmi_bls<"blsi{q}", MRM3r, MRM3m, GR64, i64mem>, VEX_W; 2138} 2139 2140//===----------------------------------------------------------------------===// 2141// Pattern fragments to auto generate BMI instructions. 2142//===----------------------------------------------------------------------===// 2143 2144let Predicates = [HasBMI] in { 2145 // FIXME: patterns for the load versions are not implemented 2146 def : Pat<(and GR32:$src, (add GR32:$src, -1)), 2147 (BLSR32rr GR32:$src)>; 2148 def : Pat<(and GR64:$src, (add GR64:$src, -1)), 2149 (BLSR64rr GR64:$src)>; 2150 2151 def : Pat<(xor GR32:$src, (add GR32:$src, -1)), 2152 (BLSMSK32rr GR32:$src)>; 2153 def : Pat<(xor GR64:$src, (add GR64:$src, -1)), 2154 (BLSMSK64rr GR64:$src)>; 2155 2156 def : Pat<(and GR32:$src, (ineg GR32:$src)), 2157 (BLSI32rr GR32:$src)>; 2158 def : Pat<(and GR64:$src, (ineg GR64:$src)), 2159 (BLSI64rr GR64:$src)>; 2160} 2161 2162let Predicates = [HasBMI] in { 2163 def : Pat<(X86cmov (cttz GR16:$src), (i16 16), (X86_COND_E_OR_NE), 2164 (X86cmp GR16:$src, (i16 0))), 2165 (TZCNT16rr GR16:$src)>; 2166 def : Pat<(X86cmov (cttz GR32:$src), (i32 32), (X86_COND_E_OR_NE), 2167 (X86cmp GR32:$src, (i32 0))), 2168 (TZCNT32rr GR32:$src)>; 2169 def : Pat<(X86cmov (cttz GR64:$src), (i64 64), (X86_COND_E_OR_NE), 2170 (X86cmp GR64:$src, (i64 0))), 2171 (TZCNT64rr GR64:$src)>; 2172 def : Pat<(X86cmov (i16 16), (cttz GR16:$src), (X86_COND_E_OR_NE), 2173 (X86cmp GR16:$src, (i16 0))), 2174 (TZCNT16rr GR16:$src)>; 2175 def : Pat<(X86cmov (i32 32), (cttz GR32:$src), (X86_COND_E_OR_NE), 2176 (X86cmp GR32:$src, (i32 0))), 2177 (TZCNT32rr GR32:$src)>; 2178 def : Pat<(X86cmov (i64 64), (cttz GR64:$src), (X86_COND_E_OR_NE), 2179 (X86cmp GR64:$src, (i64 0))), 2180 (TZCNT64rr GR64:$src)>; 2181 2182 def : Pat<(X86cmov (cttz (loadi16 addr:$src)), (i16 16), (X86_COND_E_OR_NE), 2183 (X86cmp (loadi16 addr:$src), (i16 0))), 2184 (TZCNT16rm addr:$src)>; 2185 def : Pat<(X86cmov (cttz (loadi32 addr:$src)), (i32 32), (X86_COND_E_OR_NE), 2186 (X86cmp (loadi32 addr:$src), (i32 0))), 2187 (TZCNT32rm addr:$src)>; 2188 def : Pat<(X86cmov (cttz (loadi64 addr:$src)), (i64 64), (X86_COND_E_OR_NE), 2189 (X86cmp (loadi64 addr:$src), (i64 0))), 2190 (TZCNT64rm addr:$src)>; 2191 def : Pat<(X86cmov (i16 16), (cttz (loadi16 addr:$src)), (X86_COND_E_OR_NE), 2192 (X86cmp (loadi16 addr:$src), (i16 0))), 2193 (TZCNT16rm addr:$src)>; 2194 def : Pat<(X86cmov (i32 32), (cttz (loadi32 addr:$src)), (X86_COND_E_OR_NE), 2195 (X86cmp (loadi32 addr:$src), (i32 0))), 2196 (TZCNT32rm addr:$src)>; 2197 def : Pat<(X86cmov (i64 64), (cttz (loadi64 addr:$src)), (X86_COND_E_OR_NE), 2198 (X86cmp (loadi64 addr:$src), (i64 0))), 2199 (TZCNT64rm addr:$src)>; 2200} 2201 2202 2203multiclass bmi_bextr_bzhi<bits<8> opc, string mnemonic, RegisterClass RC, 2204 X86MemOperand x86memop, Intrinsic Int, 2205 PatFrag ld_frag> { 2206 def rr : I<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2), 2207 !strconcat(mnemonic, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"), 2208 [(set RC:$dst, (Int RC:$src1, RC:$src2)), (implicit EFLAGS)]>, 2209 T8PS, VEX_4VOp3; 2210 def rm : I<opc, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src1, RC:$src2), 2211 !strconcat(mnemonic, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"), 2212 [(set RC:$dst, (Int (ld_frag addr:$src1), RC:$src2)), 2213 (implicit EFLAGS)]>, T8PS, VEX_4VOp3; 2214} 2215 2216let Predicates = [HasBMI], Defs = [EFLAGS] in { 2217 defm BEXTR32 : bmi_bextr_bzhi<0xF7, "bextr{l}", GR32, i32mem, 2218 int_x86_bmi_bextr_32, loadi32>; 2219 defm BEXTR64 : bmi_bextr_bzhi<0xF7, "bextr{q}", GR64, i64mem, 2220 int_x86_bmi_bextr_64, loadi64>, VEX_W; 2221} 2222 2223let Predicates = [HasBMI2], Defs = [EFLAGS] in { 2224 defm BZHI32 : bmi_bextr_bzhi<0xF5, "bzhi{l}", GR32, i32mem, 2225 int_x86_bmi_bzhi_32, loadi32>; 2226 defm BZHI64 : bmi_bextr_bzhi<0xF5, "bzhi{q}", GR64, i64mem, 2227 int_x86_bmi_bzhi_64, loadi64>, VEX_W; 2228} 2229 2230 2231def CountTrailingOnes : SDNodeXForm<imm, [{ 2232 // Count the trailing ones in the immediate. 2233 return getI8Imm(countTrailingOnes(N->getZExtValue()), SDLoc(N)); 2234}]>; 2235 2236def BZHIMask : ImmLeaf<i64, [{ 2237 return isMask_64(Imm) && (countTrailingOnes<uint64_t>(Imm) > 32); 2238}]>; 2239 2240let Predicates = [HasBMI2] in { 2241 def : Pat<(and GR64:$src, BZHIMask:$mask), 2242 (BZHI64rr GR64:$src, 2243 (INSERT_SUBREG (i64 (IMPLICIT_DEF)), 2244 (MOV8ri (CountTrailingOnes imm:$mask)), sub_8bit))>; 2245 2246 def : Pat<(and GR32:$src, (add (shl 1, GR8:$lz), -1)), 2247 (BZHI32rr GR32:$src, 2248 (INSERT_SUBREG (i32 (IMPLICIT_DEF)), GR8:$lz, sub_8bit))>; 2249 2250 def : Pat<(and (loadi32 addr:$src), (add (shl 1, GR8:$lz), -1)), 2251 (BZHI32rm addr:$src, 2252 (INSERT_SUBREG (i32 (IMPLICIT_DEF)), GR8:$lz, sub_8bit))>; 2253 2254 def : Pat<(and GR64:$src, (add (shl 1, GR8:$lz), -1)), 2255 (BZHI64rr GR64:$src, 2256 (INSERT_SUBREG (i64 (IMPLICIT_DEF)), GR8:$lz, sub_8bit))>; 2257 2258 def : Pat<(and (loadi64 addr:$src), (add (shl 1, GR8:$lz), -1)), 2259 (BZHI64rm addr:$src, 2260 (INSERT_SUBREG (i64 (IMPLICIT_DEF)), GR8:$lz, sub_8bit))>; 2261} // HasBMI2 2262 2263let Predicates = [HasBMI] in { 2264 def : Pat<(X86bextr GR32:$src1, GR32:$src2), 2265 (BEXTR32rr GR32:$src1, GR32:$src2)>; 2266 def : Pat<(X86bextr (loadi32 addr:$src1), GR32:$src2), 2267 (BEXTR32rm addr:$src1, GR32:$src2)>; 2268 def : Pat<(X86bextr GR64:$src1, GR64:$src2), 2269 (BEXTR64rr GR64:$src1, GR64:$src2)>; 2270 def : Pat<(X86bextr (loadi64 addr:$src1), GR64:$src2), 2271 (BEXTR64rm addr:$src1, GR64:$src2)>; 2272} // HasBMI 2273 2274multiclass bmi_pdep_pext<string mnemonic, RegisterClass RC, 2275 X86MemOperand x86memop, Intrinsic Int, 2276 PatFrag ld_frag> { 2277 def rr : I<0xF5, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2), 2278 !strconcat(mnemonic, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"), 2279 [(set RC:$dst, (Int RC:$src1, RC:$src2))]>, 2280 VEX_4V; 2281 def rm : I<0xF5, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, x86memop:$src2), 2282 !strconcat(mnemonic, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"), 2283 [(set RC:$dst, (Int RC:$src1, (ld_frag addr:$src2)))]>, VEX_4V; 2284} 2285 2286let Predicates = [HasBMI2] in { 2287 defm PDEP32 : bmi_pdep_pext<"pdep{l}", GR32, i32mem, 2288 int_x86_bmi_pdep_32, loadi32>, T8XD; 2289 defm PDEP64 : bmi_pdep_pext<"pdep{q}", GR64, i64mem, 2290 int_x86_bmi_pdep_64, loadi64>, T8XD, VEX_W; 2291 defm PEXT32 : bmi_pdep_pext<"pext{l}", GR32, i32mem, 2292 int_x86_bmi_pext_32, loadi32>, T8XS; 2293 defm PEXT64 : bmi_pdep_pext<"pext{q}", GR64, i64mem, 2294 int_x86_bmi_pext_64, loadi64>, T8XS, VEX_W; 2295} 2296 2297//===----------------------------------------------------------------------===// 2298// TBM Instructions 2299// 2300let Predicates = [HasTBM], Defs = [EFLAGS] in { 2301 2302multiclass tbm_ternary_imm_intr<bits<8> opc, RegisterClass RC, string OpcodeStr, 2303 X86MemOperand x86memop, PatFrag ld_frag, 2304 Intrinsic Int, Operand immtype, 2305 SDPatternOperator immoperator> { 2306 def ri : Ii32<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, immtype:$cntl), 2307 !strconcat(OpcodeStr, 2308 "\t{$cntl, $src1, $dst|$dst, $src1, $cntl}"), 2309 [(set RC:$dst, (Int RC:$src1, immoperator:$cntl))]>, 2310 XOP, XOPA; 2311 def mi : Ii32<opc, MRMSrcMem, (outs RC:$dst), 2312 (ins x86memop:$src1, immtype:$cntl), 2313 !strconcat(OpcodeStr, 2314 "\t{$cntl, $src1, $dst|$dst, $src1, $cntl}"), 2315 [(set RC:$dst, (Int (ld_frag addr:$src1), immoperator:$cntl))]>, 2316 XOP, XOPA; 2317} 2318 2319defm BEXTRI32 : tbm_ternary_imm_intr<0x10, GR32, "bextr", i32mem, loadi32, 2320 int_x86_tbm_bextri_u32, i32imm, imm>; 2321let ImmT = Imm32S in 2322defm BEXTRI64 : tbm_ternary_imm_intr<0x10, GR64, "bextr", i64mem, loadi64, 2323 int_x86_tbm_bextri_u64, i64i32imm, 2324 i64immSExt32>, VEX_W; 2325 2326multiclass tbm_binary_rm<bits<8> opc, Format FormReg, Format FormMem, 2327 RegisterClass RC, string OpcodeStr, 2328 X86MemOperand x86memop, PatFrag ld_frag> { 2329let hasSideEffects = 0 in { 2330 def rr : I<opc, FormReg, (outs RC:$dst), (ins RC:$src), 2331 !strconcat(OpcodeStr,"\t{$src, $dst|$dst, $src}"), 2332 []>, XOP_4V, XOP9; 2333 let mayLoad = 1 in 2334 def rm : I<opc, FormMem, (outs RC:$dst), (ins x86memop:$src), 2335 !strconcat(OpcodeStr,"\t{$src, $dst|$dst, $src}"), 2336 []>, XOP_4V, XOP9; 2337} 2338} 2339 2340multiclass tbm_binary_intr<bits<8> opc, string OpcodeStr, 2341 Format FormReg, Format FormMem> { 2342 defm NAME#32 : tbm_binary_rm<opc, FormReg, FormMem, GR32, OpcodeStr, i32mem, 2343 loadi32>; 2344 defm NAME#64 : tbm_binary_rm<opc, FormReg, FormMem, GR64, OpcodeStr, i64mem, 2345 loadi64>, VEX_W; 2346} 2347 2348defm BLCFILL : tbm_binary_intr<0x01, "blcfill", MRM1r, MRM1m>; 2349defm BLCI : tbm_binary_intr<0x02, "blci", MRM6r, MRM6m>; 2350defm BLCIC : tbm_binary_intr<0x01, "blcic", MRM5r, MRM5m>; 2351defm BLCMSK : tbm_binary_intr<0x02, "blcmsk", MRM1r, MRM1m>; 2352defm BLCS : tbm_binary_intr<0x01, "blcs", MRM3r, MRM3m>; 2353defm BLSFILL : tbm_binary_intr<0x01, "blsfill", MRM2r, MRM2m>; 2354defm BLSIC : tbm_binary_intr<0x01, "blsic", MRM6r, MRM6m>; 2355defm T1MSKC : tbm_binary_intr<0x01, "t1mskc", MRM7r, MRM7m>; 2356defm TZMSK : tbm_binary_intr<0x01, "tzmsk", MRM4r, MRM4m>; 2357} // HasTBM, EFLAGS 2358 2359//===----------------------------------------------------------------------===// 2360// Pattern fragments to auto generate TBM instructions. 2361//===----------------------------------------------------------------------===// 2362 2363let Predicates = [HasTBM] in { 2364 def : Pat<(X86bextr GR32:$src1, (i32 imm:$src2)), 2365 (BEXTRI32ri GR32:$src1, imm:$src2)>; 2366 def : Pat<(X86bextr (loadi32 addr:$src1), (i32 imm:$src2)), 2367 (BEXTRI32mi addr:$src1, imm:$src2)>; 2368 def : Pat<(X86bextr GR64:$src1, i64immSExt32:$src2), 2369 (BEXTRI64ri GR64:$src1, i64immSExt32:$src2)>; 2370 def : Pat<(X86bextr (loadi64 addr:$src1), i64immSExt32:$src2), 2371 (BEXTRI64mi addr:$src1, i64immSExt32:$src2)>; 2372 2373 // FIXME: patterns for the load versions are not implemented 2374 def : Pat<(and GR32:$src, (add GR32:$src, 1)), 2375 (BLCFILL32rr GR32:$src)>; 2376 def : Pat<(and GR64:$src, (add GR64:$src, 1)), 2377 (BLCFILL64rr GR64:$src)>; 2378 2379 def : Pat<(or GR32:$src, (not (add GR32:$src, 1))), 2380 (BLCI32rr GR32:$src)>; 2381 def : Pat<(or GR64:$src, (not (add GR64:$src, 1))), 2382 (BLCI64rr GR64:$src)>; 2383 2384 // Extra patterns because opt can optimize the above patterns to this. 2385 def : Pat<(or GR32:$src, (sub -2, GR32:$src)), 2386 (BLCI32rr GR32:$src)>; 2387 def : Pat<(or GR64:$src, (sub -2, GR64:$src)), 2388 (BLCI64rr GR64:$src)>; 2389 2390 def : Pat<(and (not GR32:$src), (add GR32:$src, 1)), 2391 (BLCIC32rr GR32:$src)>; 2392 def : Pat<(and (not GR64:$src), (add GR64:$src, 1)), 2393 (BLCIC64rr GR64:$src)>; 2394 2395 def : Pat<(xor GR32:$src, (add GR32:$src, 1)), 2396 (BLCMSK32rr GR32:$src)>; 2397 def : Pat<(xor GR64:$src, (add GR64:$src, 1)), 2398 (BLCMSK64rr GR64:$src)>; 2399 2400 def : Pat<(or GR32:$src, (add GR32:$src, 1)), 2401 (BLCS32rr GR32:$src)>; 2402 def : Pat<(or GR64:$src, (add GR64:$src, 1)), 2403 (BLCS64rr GR64:$src)>; 2404 2405 def : Pat<(or GR32:$src, (add GR32:$src, -1)), 2406 (BLSFILL32rr GR32:$src)>; 2407 def : Pat<(or GR64:$src, (add GR64:$src, -1)), 2408 (BLSFILL64rr GR64:$src)>; 2409 2410 def : Pat<(or (not GR32:$src), (add GR32:$src, -1)), 2411 (BLSIC32rr GR32:$src)>; 2412 def : Pat<(or (not GR64:$src), (add GR64:$src, -1)), 2413 (BLSIC64rr GR64:$src)>; 2414 2415 def : Pat<(or (not GR32:$src), (add GR32:$src, 1)), 2416 (T1MSKC32rr GR32:$src)>; 2417 def : Pat<(or (not GR64:$src), (add GR64:$src, 1)), 2418 (T1MSKC64rr GR64:$src)>; 2419 2420 def : Pat<(and (not GR32:$src), (add GR32:$src, -1)), 2421 (TZMSK32rr GR32:$src)>; 2422 def : Pat<(and (not GR64:$src), (add GR64:$src, -1)), 2423 (TZMSK64rr GR64:$src)>; 2424} // HasTBM 2425 2426//===----------------------------------------------------------------------===// 2427// Memory Instructions 2428// 2429 2430def CLFLUSHOPT : I<0xAE, MRM7m, (outs), (ins i8mem:$src), 2431 "clflushopt\t$src", []>, PD; 2432def CLWB : I<0xAE, MRM6m, (outs), (ins i8mem:$src), "clwb\t$src", []>, PD; 2433def PCOMMIT : I<0xAE, MRM_F8, (outs), (ins), "pcommit", []>, PD; 2434 2435 2436//===----------------------------------------------------------------------===// 2437// Subsystems. 2438//===----------------------------------------------------------------------===// 2439 2440include "X86InstrArithmetic.td" 2441include "X86InstrCMovSetCC.td" 2442include "X86InstrExtension.td" 2443include "X86InstrControl.td" 2444include "X86InstrShiftRotate.td" 2445 2446// X87 Floating Point Stack. 2447include "X86InstrFPStack.td" 2448 2449// SIMD support (SSE, MMX and AVX) 2450include "X86InstrFragmentsSIMD.td" 2451 2452// FMA - Fused Multiply-Add support (requires FMA) 2453include "X86InstrFMA.td" 2454 2455// XOP 2456include "X86InstrXOP.td" 2457 2458// SSE, MMX and 3DNow! vector support. 2459include "X86InstrSSE.td" 2460include "X86InstrAVX512.td" 2461include "X86InstrMMX.td" 2462include "X86Instr3DNow.td" 2463 2464// MPX instructions 2465include "X86InstrMPX.td" 2466 2467include "X86InstrVMX.td" 2468include "X86InstrSVM.td" 2469 2470include "X86InstrTSX.td" 2471include "X86InstrSGX.td" 2472 2473// System instructions. 2474include "X86InstrSystem.td" 2475 2476// Compiler Pseudo Instructions and Pat Patterns 2477include "X86InstrCompiler.td" 2478 2479//===----------------------------------------------------------------------===// 2480// Assembler Mnemonic Aliases 2481//===----------------------------------------------------------------------===// 2482 2483def : MnemonicAlias<"call", "callw", "att">, Requires<[In16BitMode]>; 2484def : MnemonicAlias<"call", "calll", "att">, Requires<[In32BitMode]>; 2485def : MnemonicAlias<"call", "callq", "att">, Requires<[In64BitMode]>; 2486 2487def : MnemonicAlias<"cbw", "cbtw", "att">; 2488def : MnemonicAlias<"cwde", "cwtl", "att">; 2489def : MnemonicAlias<"cwd", "cwtd", "att">; 2490def : MnemonicAlias<"cdq", "cltd", "att">; 2491def : MnemonicAlias<"cdqe", "cltq", "att">; 2492def : MnemonicAlias<"cqo", "cqto", "att">; 2493 2494// In 64-bit mode lret maps to lretl; it is not ambiguous with lretq. 2495def : MnemonicAlias<"lret", "lretw", "att">, Requires<[In16BitMode]>; 2496def : MnemonicAlias<"lret", "lretl", "att">, Requires<[Not16BitMode]>; 2497 2498def : MnemonicAlias<"leavel", "leave", "att">, Requires<[Not64BitMode]>; 2499def : MnemonicAlias<"leaveq", "leave", "att">, Requires<[In64BitMode]>; 2500 2501def : MnemonicAlias<"loopz", "loope", "att">; 2502def : MnemonicAlias<"loopnz", "loopne", "att">; 2503 2504def : MnemonicAlias<"pop", "popw", "att">, Requires<[In16BitMode]>; 2505def : MnemonicAlias<"pop", "popl", "att">, Requires<[In32BitMode]>; 2506def : MnemonicAlias<"pop", "popq", "att">, Requires<[In64BitMode]>; 2507def : MnemonicAlias<"popf", "popfw", "att">, Requires<[In16BitMode]>; 2508def : MnemonicAlias<"popf", "popfl", "att">, Requires<[In32BitMode]>; 2509def : MnemonicAlias<"popf", "popfq", "att">, Requires<[In64BitMode]>; 2510def : MnemonicAlias<"popfd", "popfl", "att">; 2511 2512// FIXME: This is wrong for "push reg". "push %bx" should turn into pushw in 2513// all modes. However: "push (addr)" and "push $42" should default to 2514// pushl/pushq depending on the current mode. Similar for "pop %bx" 2515def : MnemonicAlias<"push", "pushw", "att">, Requires<[In16BitMode]>; 2516def : MnemonicAlias<"push", "pushl", "att">, Requires<[In32BitMode]>; 2517def : MnemonicAlias<"push", "pushq", "att">, Requires<[In64BitMode]>; 2518def : MnemonicAlias<"pushf", "pushfw", "att">, Requires<[In16BitMode]>; 2519def : MnemonicAlias<"pushf", "pushfl", "att">, Requires<[In32BitMode]>; 2520def : MnemonicAlias<"pushf", "pushfq", "att">, Requires<[In64BitMode]>; 2521def : MnemonicAlias<"pushfd", "pushfl", "att">; 2522 2523def : MnemonicAlias<"popad", "popal", "intel">, Requires<[Not64BitMode]>; 2524def : MnemonicAlias<"pushad", "pushal", "intel">, Requires<[Not64BitMode]>; 2525def : MnemonicAlias<"popa", "popaw", "intel">, Requires<[In16BitMode]>; 2526def : MnemonicAlias<"pusha", "pushaw", "intel">, Requires<[In16BitMode]>; 2527def : MnemonicAlias<"popa", "popal", "intel">, Requires<[In32BitMode]>; 2528def : MnemonicAlias<"pusha", "pushal", "intel">, Requires<[In32BitMode]>; 2529 2530def : MnemonicAlias<"popa", "popaw", "att">, Requires<[In16BitMode]>; 2531def : MnemonicAlias<"pusha", "pushaw", "att">, Requires<[In16BitMode]>; 2532def : MnemonicAlias<"popa", "popal", "att">, Requires<[In32BitMode]>; 2533def : MnemonicAlias<"pusha", "pushal", "att">, Requires<[In32BitMode]>; 2534 2535def : MnemonicAlias<"repe", "rep", "att">; 2536def : MnemonicAlias<"repz", "rep", "att">; 2537def : MnemonicAlias<"repnz", "repne", "att">; 2538 2539def : MnemonicAlias<"ret", "retw", "att">, Requires<[In16BitMode]>; 2540def : MnemonicAlias<"ret", "retl", "att">, Requires<[In32BitMode]>; 2541def : MnemonicAlias<"ret", "retq", "att">, Requires<[In64BitMode]>; 2542 2543def : MnemonicAlias<"salb", "shlb", "att">; 2544def : MnemonicAlias<"salw", "shlw", "att">; 2545def : MnemonicAlias<"sall", "shll", "att">; 2546def : MnemonicAlias<"salq", "shlq", "att">; 2547 2548def : MnemonicAlias<"smovb", "movsb", "att">; 2549def : MnemonicAlias<"smovw", "movsw", "att">; 2550def : MnemonicAlias<"smovl", "movsl", "att">; 2551def : MnemonicAlias<"smovq", "movsq", "att">; 2552 2553def : MnemonicAlias<"ud2a", "ud2", "att">; 2554def : MnemonicAlias<"verrw", "verr", "att">; 2555 2556// System instruction aliases. 2557def : MnemonicAlias<"iret", "iretw", "att">, Requires<[In16BitMode]>; 2558def : MnemonicAlias<"iret", "iretl", "att">, Requires<[Not16BitMode]>; 2559def : MnemonicAlias<"sysret", "sysretl", "att">; 2560def : MnemonicAlias<"sysexit", "sysexitl", "att">; 2561 2562def : MnemonicAlias<"lgdt", "lgdtw", "att">, Requires<[In16BitMode]>; 2563def : MnemonicAlias<"lgdt", "lgdtl", "att">, Requires<[In32BitMode]>; 2564def : MnemonicAlias<"lgdt", "lgdtq", "att">, Requires<[In64BitMode]>; 2565def : MnemonicAlias<"lidt", "lidtw", "att">, Requires<[In16BitMode]>; 2566def : MnemonicAlias<"lidt", "lidtl", "att">, Requires<[In32BitMode]>; 2567def : MnemonicAlias<"lidt", "lidtq", "att">, Requires<[In64BitMode]>; 2568def : MnemonicAlias<"sgdt", "sgdtw", "att">, Requires<[In16BitMode]>; 2569def : MnemonicAlias<"sgdt", "sgdtl", "att">, Requires<[In32BitMode]>; 2570def : MnemonicAlias<"sgdt", "sgdtq", "att">, Requires<[In64BitMode]>; 2571def : MnemonicAlias<"sidt", "sidtw", "att">, Requires<[In16BitMode]>; 2572def : MnemonicAlias<"sidt", "sidtl", "att">, Requires<[In32BitMode]>; 2573def : MnemonicAlias<"sidt", "sidtq", "att">, Requires<[In64BitMode]>; 2574 2575 2576// Floating point stack aliases. 2577def : MnemonicAlias<"fcmovz", "fcmove", "att">; 2578def : MnemonicAlias<"fcmova", "fcmovnbe", "att">; 2579def : MnemonicAlias<"fcmovnae", "fcmovb", "att">; 2580def : MnemonicAlias<"fcmovna", "fcmovbe", "att">; 2581def : MnemonicAlias<"fcmovae", "fcmovnb", "att">; 2582def : MnemonicAlias<"fcomip", "fcompi", "att">; 2583def : MnemonicAlias<"fildq", "fildll", "att">; 2584def : MnemonicAlias<"fistpq", "fistpll", "att">; 2585def : MnemonicAlias<"fisttpq", "fisttpll", "att">; 2586def : MnemonicAlias<"fldcww", "fldcw", "att">; 2587def : MnemonicAlias<"fnstcww", "fnstcw", "att">; 2588def : MnemonicAlias<"fnstsww", "fnstsw", "att">; 2589def : MnemonicAlias<"fucomip", "fucompi", "att">; 2590def : MnemonicAlias<"fwait", "wait">; 2591 2592def : MnemonicAlias<"fxsaveq", "fxsave64", "att">; 2593def : MnemonicAlias<"fxrstorq", "fxrstor64", "att">; 2594def : MnemonicAlias<"xsaveq", "xsave64", "att">; 2595def : MnemonicAlias<"xrstorq", "xrstor64", "att">; 2596def : MnemonicAlias<"xsaveoptq", "xsaveopt64", "att">; 2597 2598 2599class CondCodeAlias<string Prefix,string Suffix, string OldCond, string NewCond, 2600 string VariantName> 2601 : MnemonicAlias<!strconcat(Prefix, OldCond, Suffix), 2602 !strconcat(Prefix, NewCond, Suffix), VariantName>; 2603 2604/// IntegerCondCodeMnemonicAlias - This multiclass defines a bunch of 2605/// MnemonicAlias's that canonicalize the condition code in a mnemonic, for 2606/// example "setz" -> "sete". 2607multiclass IntegerCondCodeMnemonicAlias<string Prefix, string Suffix, 2608 string V = ""> { 2609 def C : CondCodeAlias<Prefix, Suffix, "c", "b", V>; // setc -> setb 2610 def Z : CondCodeAlias<Prefix, Suffix, "z" , "e", V>; // setz -> sete 2611 def NA : CondCodeAlias<Prefix, Suffix, "na", "be", V>; // setna -> setbe 2612 def NB : CondCodeAlias<Prefix, Suffix, "nb", "ae", V>; // setnb -> setae 2613 def NC : CondCodeAlias<Prefix, Suffix, "nc", "ae", V>; // setnc -> setae 2614 def NG : CondCodeAlias<Prefix, Suffix, "ng", "le", V>; // setng -> setle 2615 def NL : CondCodeAlias<Prefix, Suffix, "nl", "ge", V>; // setnl -> setge 2616 def NZ : CondCodeAlias<Prefix, Suffix, "nz", "ne", V>; // setnz -> setne 2617 def PE : CondCodeAlias<Prefix, Suffix, "pe", "p", V>; // setpe -> setp 2618 def PO : CondCodeAlias<Prefix, Suffix, "po", "np", V>; // setpo -> setnp 2619 2620 def NAE : CondCodeAlias<Prefix, Suffix, "nae", "b", V>; // setnae -> setb 2621 def NBE : CondCodeAlias<Prefix, Suffix, "nbe", "a", V>; // setnbe -> seta 2622 def NGE : CondCodeAlias<Prefix, Suffix, "nge", "l", V>; // setnge -> setl 2623 def NLE : CondCodeAlias<Prefix, Suffix, "nle", "g", V>; // setnle -> setg 2624} 2625 2626// Aliases for set<CC> 2627defm : IntegerCondCodeMnemonicAlias<"set", "">; 2628// Aliases for j<CC> 2629defm : IntegerCondCodeMnemonicAlias<"j", "">; 2630// Aliases for cmov<CC>{w,l,q} 2631defm : IntegerCondCodeMnemonicAlias<"cmov", "w", "att">; 2632defm : IntegerCondCodeMnemonicAlias<"cmov", "l", "att">; 2633defm : IntegerCondCodeMnemonicAlias<"cmov", "q", "att">; 2634// No size suffix for intel-style asm. 2635defm : IntegerCondCodeMnemonicAlias<"cmov", "", "intel">; 2636 2637 2638//===----------------------------------------------------------------------===// 2639// Assembler Instruction Aliases 2640//===----------------------------------------------------------------------===// 2641 2642// aad/aam default to base 10 if no operand is specified. 2643def : InstAlias<"aad", (AAD8i8 10)>; 2644def : InstAlias<"aam", (AAM8i8 10)>; 2645 2646// Disambiguate the mem/imm form of bt-without-a-suffix as btl. 2647// Likewise for btc/btr/bts. 2648def : InstAlias<"bt {$imm, $mem|$mem, $imm}", 2649 (BT32mi8 i32mem:$mem, i32i8imm:$imm), 0>; 2650def : InstAlias<"btc {$imm, $mem|$mem, $imm}", 2651 (BTC32mi8 i32mem:$mem, i32i8imm:$imm), 0>; 2652def : InstAlias<"btr {$imm, $mem|$mem, $imm}", 2653 (BTR32mi8 i32mem:$mem, i32i8imm:$imm), 0>; 2654def : InstAlias<"bts {$imm, $mem|$mem, $imm}", 2655 (BTS32mi8 i32mem:$mem, i32i8imm:$imm), 0>; 2656 2657// clr aliases. 2658def : InstAlias<"clrb $reg", (XOR8rr GR8 :$reg, GR8 :$reg), 0>; 2659def : InstAlias<"clrw $reg", (XOR16rr GR16:$reg, GR16:$reg), 0>; 2660def : InstAlias<"clrl $reg", (XOR32rr GR32:$reg, GR32:$reg), 0>; 2661def : InstAlias<"clrq $reg", (XOR64rr GR64:$reg, GR64:$reg), 0>; 2662 2663// lods aliases. Accept the destination being omitted because it's implicit 2664// in the mnemonic, or the mnemonic suffix being omitted because it's implicit 2665// in the destination. 2666def : InstAlias<"lodsb $src", (LODSB srcidx8:$src), 0>; 2667def : InstAlias<"lodsw $src", (LODSW srcidx16:$src), 0>; 2668def : InstAlias<"lods{l|d} $src", (LODSL srcidx32:$src), 0>; 2669def : InstAlias<"lodsq $src", (LODSQ srcidx64:$src), 0>, Requires<[In64BitMode]>; 2670def : InstAlias<"lods {$src, %al|al, $src}", (LODSB srcidx8:$src), 0>; 2671def : InstAlias<"lods {$src, %ax|ax, $src}", (LODSW srcidx16:$src), 0>; 2672def : InstAlias<"lods {$src, %eax|eax, $src}", (LODSL srcidx32:$src), 0>; 2673def : InstAlias<"lods {$src, %rax|rax, $src}", (LODSQ srcidx64:$src), 0>, Requires<[In64BitMode]>; 2674 2675// stos aliases. Accept the source being omitted because it's implicit in 2676// the mnemonic, or the mnemonic suffix being omitted because it's implicit 2677// in the source. 2678def : InstAlias<"stosb $dst", (STOSB dstidx8:$dst), 0>; 2679def : InstAlias<"stosw $dst", (STOSW dstidx16:$dst), 0>; 2680def : InstAlias<"stos{l|d} $dst", (STOSL dstidx32:$dst), 0>; 2681def : InstAlias<"stosq $dst", (STOSQ dstidx64:$dst), 0>, Requires<[In64BitMode]>; 2682def : InstAlias<"stos {%al, $dst|$dst, al}", (STOSB dstidx8:$dst), 0>; 2683def : InstAlias<"stos {%ax, $dst|$dst, ax}", (STOSW dstidx16:$dst), 0>; 2684def : InstAlias<"stos {%eax, $dst|$dst, eax}", (STOSL dstidx32:$dst), 0>; 2685def : InstAlias<"stos {%rax, $dst|$dst, rax}", (STOSQ dstidx64:$dst), 0>, Requires<[In64BitMode]>; 2686 2687// scas aliases. Accept the destination being omitted because it's implicit 2688// in the mnemonic, or the mnemonic suffix being omitted because it's implicit 2689// in the destination. 2690def : InstAlias<"scasb $dst", (SCASB dstidx8:$dst), 0>; 2691def : InstAlias<"scasw $dst", (SCASW dstidx16:$dst), 0>; 2692def : InstAlias<"scas{l|d} $dst", (SCASL dstidx32:$dst), 0>; 2693def : InstAlias<"scasq $dst", (SCASQ dstidx64:$dst), 0>, Requires<[In64BitMode]>; 2694def : InstAlias<"scas {$dst, %al|al, $dst}", (SCASB dstidx8:$dst), 0>; 2695def : InstAlias<"scas {$dst, %ax|ax, $dst}", (SCASW dstidx16:$dst), 0>; 2696def : InstAlias<"scas {$dst, %eax|eax, $dst}", (SCASL dstidx32:$dst), 0>; 2697def : InstAlias<"scas {$dst, %rax|rax, $dst}", (SCASQ dstidx64:$dst), 0>, Requires<[In64BitMode]>; 2698 2699// div and idiv aliases for explicit A register. 2700def : InstAlias<"div{b}\t{$src, %al|al, $src}", (DIV8r GR8 :$src)>; 2701def : InstAlias<"div{w}\t{$src, %ax|ax, $src}", (DIV16r GR16:$src)>; 2702def : InstAlias<"div{l}\t{$src, %eax|eax, $src}", (DIV32r GR32:$src)>; 2703def : InstAlias<"div{q}\t{$src, %rax|rax, $src}", (DIV64r GR64:$src)>; 2704def : InstAlias<"div{b}\t{$src, %al|al, $src}", (DIV8m i8mem :$src)>; 2705def : InstAlias<"div{w}\t{$src, %ax|ax, $src}", (DIV16m i16mem:$src)>; 2706def : InstAlias<"div{l}\t{$src, %eax|eax, $src}", (DIV32m i32mem:$src)>; 2707def : InstAlias<"div{q}\t{$src, %rax|rax, $src}", (DIV64m i64mem:$src)>; 2708def : InstAlias<"idiv{b}\t{$src, %al|al, $src}", (IDIV8r GR8 :$src)>; 2709def : InstAlias<"idiv{w}\t{$src, %ax|ax, $src}", (IDIV16r GR16:$src)>; 2710def : InstAlias<"idiv{l}\t{$src, %eax|eax, $src}", (IDIV32r GR32:$src)>; 2711def : InstAlias<"idiv{q}\t{$src, %rax|rax, $src}", (IDIV64r GR64:$src)>; 2712def : InstAlias<"idiv{b}\t{$src, %al|al, $src}", (IDIV8m i8mem :$src)>; 2713def : InstAlias<"idiv{w}\t{$src, %ax|ax, $src}", (IDIV16m i16mem:$src)>; 2714def : InstAlias<"idiv{l}\t{$src, %eax|eax, $src}", (IDIV32m i32mem:$src)>; 2715def : InstAlias<"idiv{q}\t{$src, %rax|rax, $src}", (IDIV64m i64mem:$src)>; 2716 2717 2718 2719// Various unary fpstack operations default to operating on on ST1. 2720// For example, "fxch" -> "fxch %st(1)" 2721def : InstAlias<"faddp", (ADD_FPrST0 ST1), 0>; 2722def : InstAlias<"fsub{|r}p", (SUBR_FPrST0 ST1), 0>; 2723def : InstAlias<"fsub{r|}p", (SUB_FPrST0 ST1), 0>; 2724def : InstAlias<"fmulp", (MUL_FPrST0 ST1), 0>; 2725def : InstAlias<"fdiv{|r}p", (DIVR_FPrST0 ST1), 0>; 2726def : InstAlias<"fdiv{r|}p", (DIV_FPrST0 ST1), 0>; 2727def : InstAlias<"fxch", (XCH_F ST1), 0>; 2728def : InstAlias<"fcom", (COM_FST0r ST1), 0>; 2729def : InstAlias<"fcomp", (COMP_FST0r ST1), 0>; 2730def : InstAlias<"fcomi", (COM_FIr ST1), 0>; 2731def : InstAlias<"fcompi", (COM_FIPr ST1), 0>; 2732def : InstAlias<"fucom", (UCOM_Fr ST1), 0>; 2733def : InstAlias<"fucomp", (UCOM_FPr ST1), 0>; 2734def : InstAlias<"fucomi", (UCOM_FIr ST1), 0>; 2735def : InstAlias<"fucompi", (UCOM_FIPr ST1), 0>; 2736 2737// Handle fmul/fadd/fsub/fdiv instructions with explicitly written st(0) op. 2738// For example, "fadd %st(4), %st(0)" -> "fadd %st(4)". We also disambiguate 2739// instructions like "fadd %st(0), %st(0)" as "fadd %st(0)" for consistency with 2740// gas. 2741multiclass FpUnaryAlias<string Mnemonic, Instruction Inst, bit EmitAlias = 1> { 2742 def : InstAlias<!strconcat(Mnemonic, "\t{$op, %st(0)|st(0), $op}"), 2743 (Inst RST:$op), EmitAlias>; 2744 def : InstAlias<!strconcat(Mnemonic, "\t{%st(0), %st(0)|st(0), st(0)}"), 2745 (Inst ST0), EmitAlias>; 2746} 2747 2748defm : FpUnaryAlias<"fadd", ADD_FST0r>; 2749defm : FpUnaryAlias<"faddp", ADD_FPrST0, 0>; 2750defm : FpUnaryAlias<"fsub", SUB_FST0r>; 2751defm : FpUnaryAlias<"fsub{|r}p", SUBR_FPrST0>; 2752defm : FpUnaryAlias<"fsubr", SUBR_FST0r>; 2753defm : FpUnaryAlias<"fsub{r|}p", SUB_FPrST0>; 2754defm : FpUnaryAlias<"fmul", MUL_FST0r>; 2755defm : FpUnaryAlias<"fmulp", MUL_FPrST0>; 2756defm : FpUnaryAlias<"fdiv", DIV_FST0r>; 2757defm : FpUnaryAlias<"fdiv{|r}p", DIVR_FPrST0>; 2758defm : FpUnaryAlias<"fdivr", DIVR_FST0r>; 2759defm : FpUnaryAlias<"fdiv{r|}p", DIV_FPrST0>; 2760defm : FpUnaryAlias<"fcomi", COM_FIr, 0>; 2761defm : FpUnaryAlias<"fucomi", UCOM_FIr, 0>; 2762defm : FpUnaryAlias<"fcompi", COM_FIPr>; 2763defm : FpUnaryAlias<"fucompi", UCOM_FIPr>; 2764 2765 2766// Handle "f{mulp,addp} st(0), $op" the same as "f{mulp,addp} $op", since they 2767// commute. We also allow fdiv[r]p/fsubrp even though they don't commute, 2768// solely because gas supports it. 2769def : InstAlias<"faddp\t{%st(0), $op|$op, st(0)}", (ADD_FPrST0 RST:$op), 0>; 2770def : InstAlias<"fmulp\t{%st(0), $op|$op, st(0)}", (MUL_FPrST0 RST:$op)>; 2771def : InstAlias<"fsub{|r}p\t{%st(0), $op|$op, st(0)}", (SUBR_FPrST0 RST:$op)>; 2772def : InstAlias<"fsub{r|}p\t{%st(0), $op|$op, st(0)}", (SUB_FPrST0 RST:$op)>; 2773def : InstAlias<"fdiv{|r}p\t{%st(0), $op|$op, st(0)}", (DIVR_FPrST0 RST:$op)>; 2774def : InstAlias<"fdiv{r|}p\t{%st(0), $op|$op, st(0)}", (DIV_FPrST0 RST:$op)>; 2775 2776// We accept "fnstsw %eax" even though it only writes %ax. 2777def : InstAlias<"fnstsw\t{%eax|eax}", (FNSTSW16r)>; 2778def : InstAlias<"fnstsw\t{%al|al}" , (FNSTSW16r)>; 2779def : InstAlias<"fnstsw" , (FNSTSW16r)>; 2780 2781// lcall and ljmp aliases. This seems to be an odd mapping in 64-bit mode, but 2782// this is compatible with what GAS does. 2783def : InstAlias<"lcall $seg, $off", (FARCALL32i i32imm:$off, i16imm:$seg), 0>, Requires<[Not16BitMode]>; 2784def : InstAlias<"ljmp $seg, $off", (FARJMP32i i32imm:$off, i16imm:$seg), 0>, Requires<[Not16BitMode]>; 2785def : InstAlias<"lcall {*}$dst", (FARCALL32m opaque48mem:$dst), 0>, Requires<[Not16BitMode]>; 2786def : InstAlias<"ljmp {*}$dst", (FARJMP32m opaque48mem:$dst), 0>, Requires<[Not16BitMode]>; 2787def : InstAlias<"lcall $seg, $off", (FARCALL16i i16imm:$off, i16imm:$seg), 0>, Requires<[In16BitMode]>; 2788def : InstAlias<"ljmp $seg, $off", (FARJMP16i i16imm:$off, i16imm:$seg), 0>, Requires<[In16BitMode]>; 2789def : InstAlias<"lcall {*}$dst", (FARCALL16m opaque32mem:$dst), 0>, Requires<[In16BitMode]>; 2790def : InstAlias<"ljmp {*}$dst", (FARJMP16m opaque32mem:$dst), 0>, Requires<[In16BitMode]>; 2791 2792def : InstAlias<"call {*}$dst", (CALL64m i64mem:$dst), 0>, Requires<[In64BitMode]>; 2793def : InstAlias<"jmp {*}$dst", (JMP64m i64mem:$dst), 0>, Requires<[In64BitMode]>; 2794def : InstAlias<"call {*}$dst", (CALL32m i32mem:$dst), 0>, Requires<[In32BitMode]>; 2795def : InstAlias<"jmp {*}$dst", (JMP32m i32mem:$dst), 0>, Requires<[In32BitMode]>; 2796def : InstAlias<"call {*}$dst", (CALL16m i16mem:$dst), 0>, Requires<[In16BitMode]>; 2797def : InstAlias<"jmp {*}$dst", (JMP16m i16mem:$dst), 0>, Requires<[In16BitMode]>; 2798 2799 2800// "imul <imm>, B" is an alias for "imul <imm>, B, B". 2801def : InstAlias<"imulw {$imm, $r|$r, $imm}", (IMUL16rri GR16:$r, GR16:$r, i16imm:$imm), 0>; 2802def : InstAlias<"imulw {$imm, $r|$r, $imm}", (IMUL16rri8 GR16:$r, GR16:$r, i16i8imm:$imm), 0>; 2803def : InstAlias<"imull {$imm, $r|$r, $imm}", (IMUL32rri GR32:$r, GR32:$r, i32imm:$imm), 0>; 2804def : InstAlias<"imull {$imm, $r|$r, $imm}", (IMUL32rri8 GR32:$r, GR32:$r, i32i8imm:$imm), 0>; 2805def : InstAlias<"imulq {$imm, $r|$r, $imm}", (IMUL64rri32 GR64:$r, GR64:$r, i64i32imm:$imm), 0>; 2806def : InstAlias<"imulq {$imm, $r|$r, $imm}", (IMUL64rri8 GR64:$r, GR64:$r, i64i8imm:$imm), 0>; 2807 2808// inb %dx -> inb %al, %dx 2809def : InstAlias<"inb\t{%dx|dx}", (IN8rr), 0>; 2810def : InstAlias<"inw\t{%dx|dx}", (IN16rr), 0>; 2811def : InstAlias<"inl\t{%dx|dx}", (IN32rr), 0>; 2812def : InstAlias<"inb\t$port", (IN8ri i8imm:$port), 0>; 2813def : InstAlias<"inw\t$port", (IN16ri i8imm:$port), 0>; 2814def : InstAlias<"inl\t$port", (IN32ri i8imm:$port), 0>; 2815 2816 2817// jmp and call aliases for lcall and ljmp. jmp $42,$5 -> ljmp 2818def : InstAlias<"call $seg, $off", (FARCALL16i i16imm:$off, i16imm:$seg)>, Requires<[In16BitMode]>; 2819def : InstAlias<"jmp $seg, $off", (FARJMP16i i16imm:$off, i16imm:$seg)>, Requires<[In16BitMode]>; 2820def : InstAlias<"call $seg, $off", (FARCALL32i i32imm:$off, i16imm:$seg)>, Requires<[Not16BitMode]>; 2821def : InstAlias<"jmp $seg, $off", (FARJMP32i i32imm:$off, i16imm:$seg)>, Requires<[Not16BitMode]>; 2822def : InstAlias<"callw $seg, $off", (FARCALL16i i16imm:$off, i16imm:$seg)>; 2823def : InstAlias<"jmpw $seg, $off", (FARJMP16i i16imm:$off, i16imm:$seg)>; 2824def : InstAlias<"calll $seg, $off", (FARCALL32i i32imm:$off, i16imm:$seg)>; 2825def : InstAlias<"jmpl $seg, $off", (FARJMP32i i32imm:$off, i16imm:$seg)>; 2826 2827// Force mov without a suffix with a segment and mem to prefer the 'l' form of 2828// the move. All segment/mem forms are equivalent, this has the shortest 2829// encoding. 2830def : InstAlias<"mov {$mem, $seg|$seg, $mem}", (MOV32sm SEGMENT_REG:$seg, i32mem:$mem), 0>; 2831def : InstAlias<"mov {$seg, $mem|$mem, $seg}", (MOV32ms i32mem:$mem, SEGMENT_REG:$seg), 0>; 2832 2833// Match 'movq <largeimm>, <reg>' as an alias for movabsq. 2834def : InstAlias<"movq {$imm, $reg|$reg, $imm}", (MOV64ri GR64:$reg, i64imm:$imm), 0>; 2835 2836// Match 'movq GR64, MMX' as an alias for movd. 2837def : InstAlias<"movq {$src, $dst|$dst, $src}", 2838 (MMX_MOVD64to64rr VR64:$dst, GR64:$src), 0>; 2839def : InstAlias<"movq {$src, $dst|$dst, $src}", 2840 (MMX_MOVD64from64rr GR64:$dst, VR64:$src), 0>; 2841 2842// movsx aliases 2843def : InstAlias<"movsx {$src, $dst|$dst, $src}", (MOVSX16rr8 GR16:$dst, GR8:$src), 0>; 2844def : InstAlias<"movsx {$src, $dst|$dst, $src}", (MOVSX16rm8 GR16:$dst, i8mem:$src), 0>; 2845def : InstAlias<"movsx {$src, $dst|$dst, $src}", (MOVSX32rr8 GR32:$dst, GR8:$src), 0>; 2846def : InstAlias<"movsx {$src, $dst|$dst, $src}", (MOVSX32rr16 GR32:$dst, GR16:$src), 0>; 2847def : InstAlias<"movsx {$src, $dst|$dst, $src}", (MOVSX64rr8 GR64:$dst, GR8:$src), 0>; 2848def : InstAlias<"movsx {$src, $dst|$dst, $src}", (MOVSX64rr16 GR64:$dst, GR16:$src), 0>; 2849def : InstAlias<"movsx {$src, $dst|$dst, $src}", (MOVSX64rr32 GR64:$dst, GR32:$src), 0>; 2850 2851// movzx aliases 2852def : InstAlias<"movzx {$src, $dst|$dst, $src}", (MOVZX16rr8 GR16:$dst, GR8:$src), 0>; 2853def : InstAlias<"movzx {$src, $dst|$dst, $src}", (MOVZX16rm8 GR16:$dst, i8mem:$src), 0>; 2854def : InstAlias<"movzx {$src, $dst|$dst, $src}", (MOVZX32rr8 GR32:$dst, GR8:$src), 0>; 2855def : InstAlias<"movzx {$src, $dst|$dst, $src}", (MOVZX32rr16 GR32:$dst, GR16:$src), 0>; 2856def : InstAlias<"movzx {$src, $dst|$dst, $src}", (MOVZX64rr8_Q GR64:$dst, GR8:$src), 0>; 2857def : InstAlias<"movzx {$src, $dst|$dst, $src}", (MOVZX64rr16_Q GR64:$dst, GR16:$src), 0>; 2858// Note: No GR32->GR64 movzx form. 2859 2860// outb %dx -> outb %al, %dx 2861def : InstAlias<"outb\t{%dx|dx}", (OUT8rr), 0>; 2862def : InstAlias<"outw\t{%dx|dx}", (OUT16rr), 0>; 2863def : InstAlias<"outl\t{%dx|dx}", (OUT32rr), 0>; 2864def : InstAlias<"outb\t$port", (OUT8ir i8imm:$port), 0>; 2865def : InstAlias<"outw\t$port", (OUT16ir i8imm:$port), 0>; 2866def : InstAlias<"outl\t$port", (OUT32ir i8imm:$port), 0>; 2867 2868// 'sldt <mem>' can be encoded with either sldtw or sldtq with the same 2869// effect (both store to a 16-bit mem). Force to sldtw to avoid ambiguity 2870// errors, since its encoding is the most compact. 2871def : InstAlias<"sldt $mem", (SLDT16m i16mem:$mem), 0>; 2872 2873// shld/shrd op,op -> shld op, op, CL 2874def : InstAlias<"shld{w}\t{$r2, $r1|$r1, $r2}", (SHLD16rrCL GR16:$r1, GR16:$r2), 0>; 2875def : InstAlias<"shld{l}\t{$r2, $r1|$r1, $r2}", (SHLD32rrCL GR32:$r1, GR32:$r2), 0>; 2876def : InstAlias<"shld{q}\t{$r2, $r1|$r1, $r2}", (SHLD64rrCL GR64:$r1, GR64:$r2), 0>; 2877def : InstAlias<"shrd{w}\t{$r2, $r1|$r1, $r2}", (SHRD16rrCL GR16:$r1, GR16:$r2), 0>; 2878def : InstAlias<"shrd{l}\t{$r2, $r1|$r1, $r2}", (SHRD32rrCL GR32:$r1, GR32:$r2), 0>; 2879def : InstAlias<"shrd{q}\t{$r2, $r1|$r1, $r2}", (SHRD64rrCL GR64:$r1, GR64:$r2), 0>; 2880 2881def : InstAlias<"shld{w}\t{$reg, $mem|$mem, $reg}", (SHLD16mrCL i16mem:$mem, GR16:$reg), 0>; 2882def : InstAlias<"shld{l}\t{$reg, $mem|$mem, $reg}", (SHLD32mrCL i32mem:$mem, GR32:$reg), 0>; 2883def : InstAlias<"shld{q}\t{$reg, $mem|$mem, $reg}", (SHLD64mrCL i64mem:$mem, GR64:$reg), 0>; 2884def : InstAlias<"shrd{w}\t{$reg, $mem|$mem, $reg}", (SHRD16mrCL i16mem:$mem, GR16:$reg), 0>; 2885def : InstAlias<"shrd{l}\t{$reg, $mem|$mem, $reg}", (SHRD32mrCL i32mem:$mem, GR32:$reg), 0>; 2886def : InstAlias<"shrd{q}\t{$reg, $mem|$mem, $reg}", (SHRD64mrCL i64mem:$mem, GR64:$reg), 0>; 2887 2888/* FIXME: This is disabled because the asm matcher is currently incapable of 2889 * matching a fixed immediate like $1. 2890// "shl X, $1" is an alias for "shl X". 2891multiclass ShiftRotateByOneAlias<string Mnemonic, string Opc> { 2892 def : InstAlias<!strconcat(Mnemonic, "b $op, $$1"), 2893 (!cast<Instruction>(!strconcat(Opc, "8r1")) GR8:$op)>; 2894 def : InstAlias<!strconcat(Mnemonic, "w $op, $$1"), 2895 (!cast<Instruction>(!strconcat(Opc, "16r1")) GR16:$op)>; 2896 def : InstAlias<!strconcat(Mnemonic, "l $op, $$1"), 2897 (!cast<Instruction>(!strconcat(Opc, "32r1")) GR32:$op)>; 2898 def : InstAlias<!strconcat(Mnemonic, "q $op, $$1"), 2899 (!cast<Instruction>(!strconcat(Opc, "64r1")) GR64:$op)>; 2900 def : InstAlias<!strconcat(Mnemonic, "b $op, $$1"), 2901 (!cast<Instruction>(!strconcat(Opc, "8m1")) i8mem:$op)>; 2902 def : InstAlias<!strconcat(Mnemonic, "w $op, $$1"), 2903 (!cast<Instruction>(!strconcat(Opc, "16m1")) i16mem:$op)>; 2904 def : InstAlias<!strconcat(Mnemonic, "l $op, $$1"), 2905 (!cast<Instruction>(!strconcat(Opc, "32m1")) i32mem:$op)>; 2906 def : InstAlias<!strconcat(Mnemonic, "q $op, $$1"), 2907 (!cast<Instruction>(!strconcat(Opc, "64m1")) i64mem:$op)>; 2908} 2909 2910defm : ShiftRotateByOneAlias<"rcl", "RCL">; 2911defm : ShiftRotateByOneAlias<"rcr", "RCR">; 2912defm : ShiftRotateByOneAlias<"rol", "ROL">; 2913defm : ShiftRotateByOneAlias<"ror", "ROR">; 2914FIXME */ 2915 2916// test: We accept "testX <reg>, <mem>" and "testX <mem>, <reg>" as synonyms. 2917def : InstAlias<"test{b}\t{$val, $mem|$mem, $val}", 2918 (TEST8rm GR8 :$val, i8mem :$mem), 0>; 2919def : InstAlias<"test{w}\t{$val, $mem|$mem, $val}", 2920 (TEST16rm GR16:$val, i16mem:$mem), 0>; 2921def : InstAlias<"test{l}\t{$val, $mem|$mem, $val}", 2922 (TEST32rm GR32:$val, i32mem:$mem), 0>; 2923def : InstAlias<"test{q}\t{$val, $mem|$mem, $val}", 2924 (TEST64rm GR64:$val, i64mem:$mem), 0>; 2925 2926// xchg: We accept "xchgX <reg>, <mem>" and "xchgX <mem>, <reg>" as synonyms. 2927def : InstAlias<"xchg{b}\t{$mem, $val|$val, $mem}", 2928 (XCHG8rm GR8 :$val, i8mem :$mem), 0>; 2929def : InstAlias<"xchg{w}\t{$mem, $val|$val, $mem}", 2930 (XCHG16rm GR16:$val, i16mem:$mem), 0>; 2931def : InstAlias<"xchg{l}\t{$mem, $val|$val, $mem}", 2932 (XCHG32rm GR32:$val, i32mem:$mem), 0>; 2933def : InstAlias<"xchg{q}\t{$mem, $val|$val, $mem}", 2934 (XCHG64rm GR64:$val, i64mem:$mem), 0>; 2935 2936// xchg: We accept "xchgX <reg>, %eax" and "xchgX %eax, <reg>" as synonyms. 2937def : InstAlias<"xchg{w}\t{%ax, $src|$src, ax}", (XCHG16ar GR16:$src), 0>; 2938def : InstAlias<"xchg{l}\t{%eax, $src|$src, eax}", 2939 (XCHG32ar GR32:$src), 0>, Requires<[Not64BitMode]>; 2940def : InstAlias<"xchg{l}\t{%eax, $src|$src, eax}", 2941 (XCHG32ar64 GR32_NOAX:$src), 0>, Requires<[In64BitMode]>; 2942def : InstAlias<"xchg{q}\t{%rax, $src|$src, rax}", (XCHG64ar GR64:$src), 0>; 2943