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Searched refs:RDX (Results 1 – 21 of 21) sorted by relevance

/NextBSD/contrib/llvm/lib/Target/X86/
HDX86InstrArithmetic.td78 // RAX,RDX = RAX*GR64
79 let Defs = [RAX,RDX,EFLAGS], Uses = [RAX], hasSideEffects = 0 in
82 [/*(set RAX, RDX, EFLAGS, (X86umul_flag RAX, GR64:$src))*/],
104 // RAX,RDX = RAX*[mem64]
105 let Defs = [RAX,RDX,EFLAGS], Uses = [RAX] in
123 // RAX,RDX = RAX*GR64
124 let Defs = [RAX,RDX,EFLAGS], Uses = [RAX] in
143 // RAX,RDX = RAX*[mem64]
144 let Defs = [RAX,RDX,EFLAGS], Uses = [RAX] in
306 // RDX:RAX/r64 = RAX,RDX
[all …]
HDX86CallingConv.td41 CCIfType<[i64], CCAssignToReg<[RAX, RDX, RCX]>>,
182 CCIfType<[i64], CCAssignToReg<[R15, RBP, RAX, RDX]>>
264 CCIfType<[i64], CCAssignToReg<[RDI, RSI, RDX, RCX, R8 , R9 ]>>,
353 CCIfSRet<CCIfType<[i64], CCAssignToRegWithShadow<[RDX , R8 , R9 ],
356 CCIfType<[i64], CCAssignToRegWithShadow<[RCX , RDX , R8 , R9 ],
362 [RCX , RDX , R8 , R9 ]>>,
411 CCIfType<[i64], CCAssignToReg<[R15, RBP, RSI, RDX, RCX, R8]>>,
684 CCIfType<[i64], CCIfSubtarget<"isTargetWin64()", CCAssignToReg<[RCX, RDX, R8, R9 ]>>>,
687 CCIfType<[i64], CCIfSubtarget<"is64Bit()", CCAssignToReg<[RDI, RSI, RDX, RCX]>>>,
762 def CSR_64EHRet : CalleeSavedRegs<(add RAX, RDX, CSR_64)>;
[all …]
HDX86RegisterInfo.cpp618 case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX: in getX86SubSuperRegisterOrZero()
630 case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX: in getX86SubSuperRegisterOrZero()
667 case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX: in getX86SubSuperRegisterOrZero()
703 case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX: in getX86SubSuperRegisterOrZero()
739 case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX: in getX86SubSuperRegisterOrZero()
740 return X86::RDX; in getX86SubSuperRegisterOrZero()
HDX86RegisterInfo.td130 def RDX : X86Reg<"rdx", 2, [EDX]>, DwarfRegNum<[1, -2, -2]>;
349 (add RAX, RCX, RDX, RSI, RDI, R8, R9, R10, R11,
373 def GR64_ABCD : RegisterClass<"X86", [i64], 64, (add RAX, RCX, RDX, RBX)>;
375 def GR64_TC : RegisterClass<"X86", [i64], 64, (add RAX, RCX, RDX, RSI, RDI,
377 def GR64_TCW64 : RegisterClass<"X86", [i64], 64, (add RAX, RCX, RDX,
396 (add RAX, RCX, RDX, RSI, RDI, RBX, RBP, RSP, RIP)>;
HDX86InstrSystem.td17 let Defs = [RAX, RDX] in
21 let Defs = [RAX, RCX, RDX] in
446 let Defs = [RAX, RDX], Uses = [ECX] in
487 let Uses = [RDX, RAX] in {
518 let Defs = [RAX, RDI], Uses = [RDX, RDI] in
523 let Defs = [RSI, RDI], Uses = [RBX, RDX, RSI, RDI] in {
535 let Defs = [RAX, RDX, RSI], Uses = [RAX, RSI] in
585 let Uses = [RAX, RBX, RCX, RDX], Defs = [RAX, RBX, RCX] in {
HDX86InstrExtension.td34 let Defs = [RAX,RDX], Uses = [RAX] in
36 "{cqto|cqo}", [], IIC_CBW>; // RDX:RAX = signext(RAX)
HDX86FastISel.cpp1644 { &X86::GR64RegClass, X86::RAX, X86::RDX, { in X86SelectDivRem()
1646 { X86::IDIV64r, X86::CQO, Copy, X86::RDX, S }, // SRem in X86SelectDivRem()
1648 { X86::DIV64r, X86::MOV32r0, Copy, X86::RDX, U }, // URem in X86SelectDivRem()
2766 X86::RDI, X86::RSI, X86::RDX, X86::RCX, X86::R8 , X86::R9 in fastLowerArguments()
HDX86ISelDAGToDAG.cpp2396 SrcReg = LoReg = X86::RAX; HiReg = X86::RDX; in Select()
2402 SrcReg = X86::RDX; LoReg = HiReg = 0; in Select()
2546 LoReg = X86::RAX; ClrReg = HiReg = X86::RDX; in Select()
HDX86InstrCompiler.td435 let Defs = [RAX, RCX, RDX, RSI, RDI, R8, R9, R10, R11,
703 let Defs = [RAX, RDX, EFLAGS], Uses = [RAX, RBX, RCX, RDX],
HDX86FrameLowering.cpp163 X86::RAX, X86::RDX, X86::RCX, X86::RSI, X86::RDI, in findDeadCallerSavedReg()
HDX86ISelLowering.cpp478 setExceptionSelectorRegister(X86::RDX); in X86TargetLowering()
2375 X86::RCX, X86::RDX, X86::R8, X86::R9 in get64BitArgumentGPRs()
2381 X86::RDI, X86::RSI, X86::RDX, X86::RCX, X86::R8, X86::R9 in get64BitArgumentGPRs()
2674 unsigned GPR = MF.addLiveIn(X86::RDX, &X86::GR64RegClass); in LowerFormalArguments()
3006 case X86::XMM1: ShadowReg = X86::RDX; break; in LowerCall()
15948 HI = DAG.getCopyFromReg(LO.getValue(1), DL, X86::RDX, MVT::i64, in getReadPerformanceCounter()
15989 HI = DAG.getCopyFromReg(LO.getValue(1), DL, X86::RDX, MVT::i64, in getReadTimeStampCounter()
18761 Regs64bit ? X86::RDX : X86::EDX, in ReplaceNodeResults()
18786 Regs64bit ? X86::RDX : X86::EDX, in ReplaceNodeResults()
HDX86InstrInfo.td1817 let Defs = [RAX, RDX, EFLAGS], Uses = [RAX, RBX, RCX, RDX] in
/NextBSD/contrib/llvm/lib/Target/X86/Disassembler/
HDX86DisassemblerDecoder.h173 ENTRY(RDX) \
191 ENTRY(RDX) \
/NextBSD/contrib/llvm/include/llvm/DebugInfo/PDB/
HDPDBTypes.h406 RDX = 331, enumerator
/NextBSD/sys/amd64/amd64/
HDbpf_jit_machdep.h42 #define RDX 2 macro
/NextBSD/contrib/llvm/lib/DebugInfo/PDB/
HDPDBExtras.cpp130 CASE_OUTPUT_ENUM_CLASS_NAME(PDB_RegisterId, RDX, OS) in operator <<()
/NextBSD/contrib/llvm/lib/Target/X86/AsmParser/
HDX86AsmInstrumentation.cpp168 X86::RCX, X86::RDX, X86::RDI, in ChooseFrameReg()
306 RegisterContext RegCtx(X86::RDX /* AddressReg */, X86::RAX /* ShadowReg */, in InstrumentMOVSBase()
HDX86Operand.h394 case X86::RDX: return X86::EDX; in getGR32FromGR64()
/NextBSD/contrib/llvm/tools/clang/include/clang/Basic/
HDAttrDocs.td886 passed in RCX, RDX, R8, and R9 as is done for the default Windows x64 calling
/NextBSD/contrib/gcc/config/i386/
HDsse.md3966 ;; RCX and RDX are used. Since 32bit register operands are implicitly
/NextBSD/share/misc/
HDpci_vendors17460 0001 RDX 11