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Searched refs:RS (Results 1 – 25 of 205) sorted by relevance

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/NextBSD/contrib/binutils/opcodes/
HDppc-opc.c393 #define RS RBS + 1 macro
394 #define RT RS
400 #define RSQ RS + 1
1806 { "efscfd", VX(4, 719), VX_MASK, PPCEFS, { RS, RB } },
1807 { "efdabs", VX(4, 740), VX_MASK, PPCEFS, { RS, RA } },
1808 { "efdnabs", VX(4, 741), VX_MASK, PPCEFS, { RS, RA } },
1809 { "efdneg", VX(4, 742), VX_MASK, PPCEFS, { RS, RA } },
1810 { "efdadd", VX(4, 736), VX_MASK, PPCEFS, { RS, RA, RB } },
1811 { "efdsub", VX(4, 737), VX_MASK, PPCEFS, { RS, RA, RB } },
1812 { "efdmul", VX(4, 744), VX_MASK, PPCEFS, { RS, RA, RB } },
[all …]
/NextBSD/contrib/llvm/lib/Target/XCore/
HDXCoreRegisterInfo.cpp96 int Offset, RegScavenger *RS ) { in InsertFPConstInst() argument
97 assert(RS && "requiresRegisterScavenging failed"); in InsertFPConstInst()
101 unsigned ScratchOffset = RS->scavengeRegister(&XCore::GRRegsRegClass, II, 0); in InsertFPConstInst()
102 RS->setRegUsed(ScratchOffset); in InsertFPConstInst()
164 unsigned Reg, int Offset, RegScavenger *RS ) { in InsertSPConstInst() argument
165 assert(RS && "requiresRegisterScavenging failed"); in InsertSPConstInst()
173 ScratchBase = RS->scavengeRegister(&XCore::GRRegsRegClass, II, 0); in InsertSPConstInst()
174 RS->setRegUsed(ScratchBase); in InsertSPConstInst()
178 unsigned ScratchOffset = RS->scavengeRegister(&XCore::GRRegsRegClass, II, 0); in InsertSPConstInst()
179 RS->setRegUsed(ScratchOffset); in InsertSPConstInst()
[all …]
HDXCoreFrameLowering.h51 RegScavenger *RS = nullptr) const override;
54 RegScavenger *RS = nullptr) const override;
/NextBSD/contrib/llvm/include/llvm/CodeGen/
HDRegAllocPBQP.h194 : RS(Unprocessed), NumOpts(0), DeniedOpts(0), OptUnsafeEdges(nullptr), in NodeMetadata()
204 : RS(Other.RS), NumOpts(Other.NumOpts), DeniedOpts(Other.DeniedOpts), in NodeMetadata()
220 : RS(Other.RS), NumOpts(Other.NumOpts), DeniedOpts(Other.DeniedOpts), in NodeMetadata()
231 RS = Other.RS;
248 RS = Other.RS;
273 ReductionState getReductionState() const { return RS; } in getReductionState()
274 void setReductionState(ReductionState RS) { in setReductionState() argument
275 assert(RS >= this->RS && "A node's reduction state can not be downgraded"); in setReductionState()
276 this->RS = RS; in setReductionState()
281 if (RS == ConservativelyAllocatable) in setReductionState()
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/NextBSD/contrib/llvm/lib/CodeGen/
HDPrologEpilogInserter.cpp68 RegScavenger *RS; member in __anon2321f5620111::PEI
179 RS = TRI->requiresRegisterScavenging(Fn) ? new RegScavenger() : nullptr; in runOnMachineFunction()
189 TFI->determineCalleeSaves(Fn, SavedRegs, RS); in runOnMachineFunction()
204 TFI->processFunctionBeforeFrameFinalized(Fn, RS); in runOnMachineFunction()
239 delete RS; in runOnMachineFunction()
622 if (RS && EarlyScavengingSlots) { in calculateFrameObjectOffsets()
624 RS->getScavengingFrameIndices(SFIs); in calculateFrameObjectOffsets()
674 if (RS && RS->isScavengingFrameIndex((int)i)) in calculateFrameObjectOffsets()
713 if (RS && RS->isScavengingFrameIndex((int)i)) in calculateFrameObjectOffsets()
727 if (RS && !EarlyScavengingSlots) { in calculateFrameObjectOffsets()
[all …]
/NextBSD/contrib/llvm/tools/clang/lib/StaticAnalyzer/Checkers/
HDMallocChecker.cpp93 static RefState getAllocatedOfSizeZero(const RefState *RS) { in getAllocatedOfSizeZero() argument
94 return RefState(AllocatedOfSizeZero, RS->getStmt(), in getAllocatedOfSizeZero()
95 RS->getAllocationFamily()); in getAllocatedOfSizeZero()
103 static RefState getEscaped(const RefState *RS) { in getEscaped() argument
104 return RefState(Escaped, RS->getStmt(), RS->getAllocationFamily()); in getEscaped()
370 const Expr *DeallocExpr, const RefState *RS,
894 const RefState *RS = State->get<RegionState>(Sym); in ProcessZeroAllocation() local
895 if (!RS) in ProcessZeroAllocation()
899 if (!RS->isAllocated()) in ProcessZeroAllocation()
903 RefState::getAllocatedOfSizeZero(RS)); in ProcessZeroAllocation()
[all …]
HDReturnPointerRangeChecker.cpp31 void checkPreStmt(const ReturnStmt *RS, CheckerContext &C) const;
35 void ReturnPointerRangeChecker::checkPreStmt(const ReturnStmt *RS, in checkPreStmt() argument
39 const Expr *RetE = RS->getRetValue(); in checkPreStmt()
HDReturnUndefChecker.cpp35 void checkPreStmt(const ReturnStmt *RS, CheckerContext &C) const;
39 void ReturnUndefChecker::checkPreStmt(const ReturnStmt *RS, in checkPreStmt() argument
41 const Expr *RetE = RS->getRetValue(); in checkPreStmt()
HDStackAddrEscapeChecker.cpp35 void checkPreStmt(const ReturnStmt *RS, CheckerContext &C) const;
119 void StackAddrEscapeChecker::checkPreStmt(const ReturnStmt *RS, in checkPreStmt() argument
122 const Expr *RetE = RS->getRetValue(); in checkPreStmt()
/NextBSD/contrib/llvm/lib/Target/AMDGPU/
HDSIPrepareScratchRegs.cpp111 RegScavenger RS; in runOnMachineFunction() local
113 RS.addScavengingFrameIndex(ScratchRsrcFI); in runOnMachineFunction()
124 RS.enterBasicBlock(&MBB); in runOnMachineFunction()
129 RS.forward(I); in runOnMachineFunction()
136 RS.scavengeRegister(&AMDGPU::SReg_128RegClass, 0); in runOnMachineFunction()
163 ScratchOffsetReg = RS.scavengeRegister(&AMDGPU::SGPR_32RegClass, 0); in runOnMachineFunction()
HDSIRegisterInfo.h41 RegScavenger *RS) const override;
129 int64_t Offset, RegScavenger *RS) const;
HDSIRegisterInfo.cpp142 RegScavenger *RS) const { in buildScratchLoadStore()
159 SOffset = RS->scavengeRegister(&AMDGPU::SGPR_32RegClass, MI, 0); in buildScratchLoadStore()
193 RegScavenger *RS) const { in eliminateFrameIndex()
293 FrameInfo->getObjectOffset(Index), RS); in eliminateFrameIndex()
306 FrameInfo->getObjectOffset(Index), RS); in eliminateFrameIndex()
315 unsigned TmpReg = RS->scavengeRegister(&AMDGPU::VGPR_32RegClass, MI, SPAdj); in eliminateFrameIndex()
/NextBSD/contrib/llvm/include/llvm/DebugInfo/DWARF/
HDDWARFUnit.h46 const DWARFDebugAbbrev *DA, StringRef RS, StringRef SS,
85 const DWARFDebugAbbrev *DA, StringRef RS, StringRef SS, in parseImpl() argument
92 auto U = llvm::make_unique<UnitType>(Context, Section, DA, RS, SS, SOS, in parseImpl()
144 const DWARFDebugAbbrev *DA, StringRef RS, StringRef SS,
158 void setRangesSection(StringRef RS, uint32_t Base) { in setRangesSection() argument
159 RangeSection = RS; in setRangesSection()
HDDWARFCompileUnit.h20 const DWARFDebugAbbrev *DA, StringRef RS, StringRef SS, in DWARFCompileUnit() argument
23 : DWARFUnit(Context, Section, DA, RS, SS, SOS, AOS, LE, UnitSection) {} in DWARFCompileUnit()
HDDWARFTypeUnit.h23 const DWARFDebugAbbrev *DA, StringRef RS, StringRef SS, in DWARFTypeUnit() argument
26 : DWARFUnit(Context, Section, DA, RS, SS, SOS, AOS, LE, UnitSection) {} in DWARFTypeUnit()
/NextBSD/contrib/llvm/lib/Target/PowerPC/
HDPPCFrameLowering.h49 RegScavenger *RS = nullptr) const override;
51 RegScavenger *RS = nullptr) const override;
52 void addScavengingSpillSlot(MachineFunction &MF, RegScavenger *RS) const;
/NextBSD/contrib/llvm/lib/Analysis/
HDCostModel.cpp181 ShuffleVectorInst *RS = dyn_cast<ShuffleVectorInst>(R); in matchPairwiseReductionAtLevel() local
182 if (!RS && Level) in matchPairwiseReductionAtLevel()
186 if (!Level && !RS && !LS) in matchPairwiseReductionAtLevel()
191 Value *NextLevelOpR = RS ? RS->getOperand(0) : nullptr; in matchPairwiseReductionAtLevel()
227 if (!matchPairwiseShuffleMask(RS, false, Level)) in matchPairwiseReductionAtLevel()
229 } else if (matchPairwiseShuffleMask(RS, true, Level)) { in matchPairwiseReductionAtLevel()
/NextBSD/contrib/llvm/lib/Target/BPF/
HDBPFFrameLowering.cpp34 RegScavenger *RS) const { in determineCalleeSaves()
35 TargetFrameLowering::determineCalleeSaves(MF, SavedRegs, RS); in determineCalleeSaves()
/NextBSD/contrib/llvm/lib/Target/Sparc/
HDSparcRegisterInfo.h40 RegScavenger *RS = nullptr) const override;
43 RegScavenger *RS = nullptr) const;
/NextBSD/sys/boot/efi/loader/
HDmain.c182 RS->ResetSystem(EfiResetCold, EFI_SUCCESS, 23, in command_reboot()
392 status = RS->GetNextVariableName(&varsz, NULL, NULL); in command_nvram()
395 status = RS->GetNextVariableName(&varsz, var, &varguid); in command_nvram()
402 status = RS->GetVariable(var, &varguid, NULL, &datasz, NULL); in command_nvram()
405 status = RS->GetVariable(var, &varguid, NULL, &datasz, data); in command_nvram()
/NextBSD/contrib/llvm/lib/Target/Mips/
HDMipsRegisterInfo.h58 RegScavenger *RS = nullptr) const override;
61 RegScavenger *RS = nullptr) const;
/NextBSD/contrib/llvm/lib/Target/SystemZ/
HDSystemZFrameLowering.h31 RegScavenger *RS) const override;
42 RegScavenger *RS) const override;
/NextBSD/sys/mips/conf/
HDROUTERSTATION.hints11 # Uncomment this hint for RS (not PRO)
16 # should be 100 for RS
/NextBSD/contrib/llvm/lib/Target/AArch64/
HDAArch64A57FPLoadBalancing.cpp494 RegScavenger RS; in scavengeRegister() local
495 RS.enterBasicBlock(&MBB); in scavengeRegister()
496 RS.forward(MachineBasicBlock::iterator(G->getStart())); in scavengeRegister()
501 BitVector AvailableRegs = RS.getRegsAvailable(TRI->getRegClass(RegClassID)); in scavengeRegister()
504 RS.forward(I); in scavengeRegister()
505 AvailableRegs &= RS.getRegsAvailable(TRI->getRegClass(RegClassID)); in scavengeRegister()
/NextBSD/contrib/llvm/lib/Target/Hexagon/
HDHexagonExpandCondsets.cpp654 RegisterRef RS = SO; in getCondTfrOpcode() local
655 if (TargetRegisterInfo::isVirtualRegister(RS.Reg)) { in getCondTfrOpcode()
656 const TargetRegisterClass *VC = MRI->getRegClass(RS.Reg); in getCondTfrOpcode()
660 assert(TargetRegisterInfo::isPhysicalRegister(RS.Reg)); in getCondTfrOpcode()
661 PhysR = RS.Reg; in getCondTfrOpcode()
663 unsigned PhysS = (RS.Sub == 0) ? PhysR : TRI->getSubReg(PhysR, RS.Sub); in getCondTfrOpcode()
1291 RegisterRef RS = S1; in coalesceSegments() local
1292 MachineInstr *RDef = getReachingDefForPred(RS, CI, RP.Reg, true); in coalesceSegments()
1297 RegisterRef RS = S2; in coalesceSegments() local
1298 MachineInstr *RDef = getReachingDefForPred(RS, CI, RP.Reg, false); in coalesceSegments()

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