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Searched refs:ResVT (Results 1 – 13 of 13) sorted by relevance

/NextBSD/contrib/llvm/lib/Target/NVPTX/
HDNVPTXISelLowering.cpp4257 EVT ResVT = N->getValueType(0); in ReplaceLoadVector() local
4260 assert(ResVT.isVector() && "Vector load must have vector type"); in ReplaceLoadVector()
4265 assert(ResVT.isSimple() && "Can only handle simple types"); in ReplaceLoadVector()
4266 switch (ResVT.getSimpleVT().SimpleTy) { in ReplaceLoadVector()
4288 TD.getPrefTypeAlignment(ResVT.getTypeForEVT(*DAG.getContext())); in ReplaceLoadVector()
4298 EVT EltVT = ResVT.getVectorElementType(); in ReplaceLoadVector()
4299 unsigned NumElts = ResVT.getVectorNumElements(); in ReplaceLoadVector()
4344 Res = DAG.getNode(ISD::TRUNCATE, DL, ResVT.getVectorElementType(), Res); in ReplaceLoadVector()
4350 SDValue BuildVec = DAG.getNode(ISD::BUILD_VECTOR, DL, ResVT, ScalarRes); in ReplaceLoadVector()
4373 EVT ResVT = N->getValueType(0); in ReplaceINTRINSIC_W_CHAIN() local
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/NextBSD/contrib/llvm/lib/CodeGen/SelectionDAG/
HDLegalizeVectorTypes.cpp1453 EVT ResVT = N->getValueType(0); in SplitVecOp_UnaryOp() local
1459 EVT OutVT = EVT::getVectorVT(*DAG.getContext(), ResVT.getVectorElementType(), in SplitVecOp_UnaryOp()
1465 return DAG.getNode(ISD::CONCAT_VECTORS, dl, ResVT, Lo, Hi); in SplitVecOp_UnaryOp()
1879 EVT ResVT = N->getValueType(0); in SplitVecOp_FP_ROUND() local
1885 EVT OutVT = EVT::getVectorVT(*DAG.getContext(), ResVT.getVectorElementType(), in SplitVecOp_FP_ROUND()
1891 return DAG.getNode(ISD::CONCAT_VECTORS, DL, ResVT, Lo, Hi); in SplitVecOp_FP_ROUND()
3090 EVT ResVT = EVT::getVectorVT(*DAG.getContext(), in WidenVecOp_SETCC() local
3094 ISD::EXTRACT_SUBVECTOR, dl, ResVT, WideSETCC, in WidenVecOp_SETCC()
HDLegalizeIntegerTypes.cpp177 EVT ResVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0)); in PromoteIntRes_Atomic0() local
179 N->getMemoryVT(), ResVT, in PromoteIntRes_Atomic0()
HDDAGCombiner.cpp9946 EVT ResVT = Use->getValueType(0); in canMergeExpensiveCrossRegisterBankCopy() local
9947 const TargetRegisterClass *ResRC = TLI.getRegClassFor(ResVT.getSimpleVT()); in canMergeExpensiveCrossRegisterBankCopy()
9950 if (ArgRC == ResRC || !TLI.isOperationLegal(ISD::LOAD, ResVT)) in canMergeExpensiveCrossRegisterBankCopy()
9964 ResVT.getTypeForEVT(*DAG->getContext())); in canMergeExpensiveCrossRegisterBankCopy()
9970 if (!TLI.isOperationLegal(ISD::LOAD, ResVT)) in canMergeExpensiveCrossRegisterBankCopy()
/NextBSD/contrib/llvm/lib/Target/SystemZ/
HDSystemZISelLowering.cpp2645 EVT ResVT = Op.getValueType(); in lowerBITCAST() local
2651 return DAG.getLoad(ResVT, DL, LoadN->getChain(), LoadN->getBasePtr(), in lowerBITCAST()
2654 if (InVT == MVT::i32 && ResVT == MVT::f32) { in lowerBITCAST()
2670 if (InVT == MVT::f32 && ResVT == MVT::i32) { in lowerBITCAST()
4505 SDValue SystemZTargetLowering::combineExtract(SDLoc DL, EVT ResVT, EVT VecVT, in combineExtract() argument
4531 return DAG.getUNDEF(ResVT); in combineExtract()
4561 EVT VT = MVT::getIntegerVT(ResVT.getSizeInBits()); in combineExtract()
4563 if (VT != ResVT) { in combineExtract()
4565 Op = DAG.getNode(ISD::BITCAST, DL, ResVT, Op); in combineExtract()
4601 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, ResVT, Op, in combineExtract()
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/NextBSD/contrib/llvm/lib/Target/AArch64/
HDAArch64ISelLowering.cpp8060 EVT ResVT = N->getValueType(0); in performExtendCombine() local
8061 if (!ResVT.isVector() || TLI.isTypeLegal(ResVT)) in performExtendCombine()
8068 if (!ResVT.isSimple() || !SrcVT.isSimple()) in performExtendCombine()
8086 unsigned NumElements = ResVT.getVectorNumElements(); in performExtendCombine()
8089 ResVT.getVectorElementType(), NumElements / 2); in performExtendCombine()
8102 return DAG.getNode(ISD::CONCAT_VECTORS, DL, ResVT, Lo, Hi); in performExtendCombine()
8790 EVT ResVT = N->getValueType(0); in performVSelectCombine() local
8794 if (ResVT.getSizeInBits() != CmpVT.getSizeInBits()) in performVSelectCombine()
8803 return DAG.getNode(ISD::VSELECT, SDLoc(N), ResVT, SetCC, in performVSelectCombine()
8815 EVT ResVT = N->getValueType(0); in performSelectCombine() local
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HDAArch64InstrInfo.td3694 multiclass DUPWithTruncPats<ValueType ResVT, ValueType Src64VT,
3697 def : Pat<(ResVT (AArch64dup (ScalVT (vector_extract (Src128VT V128:$Rn),
3701 def : Pat<(ResVT (AArch64dup (ScalVT (vector_extract (Src64VT V64:$Rn),
3714 multiclass DUPWithTrunci64Pats<ValueType ResVT, Instruction DUP,
3716 def : Pat<(ResVT (AArch64dup (i32 (trunc (vector_extract (v2i64 V128:$Rn),
3720 def : Pat<(ResVT (AArch64dup (i32 (trunc (vector_extract (v1i64 V64:$Rn),
/NextBSD/contrib/llvm/lib/Target/X86/
HDX86ISelLowering.h872 bool isExtractSubvectorCheap(EVT ResVT, unsigned Index) const override;
HDX86FastISel.cpp3186 EVT ResVT = VA.getValVT(); in fastLowerCall() local
3187 unsigned Opc = ResVT == MVT::f32 ? X86::ST_Fp80m32 : X86::ST_Fp80m64; in fastLowerCall()
3188 unsigned MemSize = ResVT.getSizeInBits()/8; in fastLowerCall()
3193 Opc = ResVT == MVT::f32 ? X86::MOVSSrm : X86::MOVSDrm; in fastLowerCall()
HDX86ISelLowering.cpp3955 bool X86TargetLowering::isExtractSubvectorCheap(EVT ResVT, in isExtractSubvectorCheap() argument
3957 if (!isOperationLegalOrCustom(ISD::EXTRACT_SUBVECTOR, ResVT)) in isExtractSubvectorCheap()
3960 return (Index == 0 || Index == ResVT.getVectorNumElements()); in isExtractSubvectorCheap()
6184 MVT ResVT = Op.getSimpleValueType(); in LowerAVXCONCAT_VECTORS() local
6186 assert((ResVT.is256BitVector() || in LowerAVXCONCAT_VECTORS()
6187 ResVT.is512BitVector()) && "Value type must be 256-/512-bit wide"); in LowerAVXCONCAT_VECTORS()
6191 unsigned NumElems = ResVT.getVectorNumElements(); in LowerAVXCONCAT_VECTORS()
6192 if (ResVT.is256BitVector()) in LowerAVXCONCAT_VECTORS()
6193 return Concat128BitVectors(V1, V2, ResVT, NumElems, DAG, dl); in LowerAVXCONCAT_VECTORS()
6196 MVT HalfVT = MVT::getVectorVT(ResVT.getScalarType(), in LowerAVXCONCAT_VECTORS()
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/NextBSD/contrib/llvm/lib/Target/PowerPC/
HDPPCISelDAGToDAG.cpp2308 EVT ResVT = VecVT.changeVectorElementTypeToInteger(); in SelectSETCC() local
2310 SDValue VCmp(CurDAG->getMachineNode(VCmpInst, dl, ResVT, LHS, RHS), 0); in SelectSETCC()
2313 ResVT, VCmp, VCmp); in SelectSETCC()
2316 return CurDAG->SelectNodeTo(N, VCmpInst, ResVT, LHS, RHS); in SelectSETCC()
HDPPCISelLowering.cpp5989 EVT ResVT = Op.getValueType(); in LowerSELECT_CC() local
6006 Sel1 = DAG.getNode(PPCISD::FSEL, dl, ResVT, LHS, TV, FV); in LowerSELECT_CC()
6009 return DAG.getNode(PPCISD::FSEL, dl, ResVT, in LowerSELECT_CC()
6018 return DAG.getNode(PPCISD::FSEL, dl, ResVT, LHS, TV, FV); in LowerSELECT_CC()
6026 return DAG.getNode(PPCISD::FSEL, dl, ResVT, in LowerSELECT_CC()
6039 Sel1 = DAG.getNode(PPCISD::FSEL, dl, ResVT, Cmp, TV, FV); in LowerSELECT_CC()
6042 return DAG.getNode(PPCISD::FSEL, dl, ResVT, in LowerSELECT_CC()
6049 return DAG.getNode(PPCISD::FSEL, dl, ResVT, Cmp, FV, TV); in LowerSELECT_CC()
6055 return DAG.getNode(PPCISD::FSEL, dl, ResVT, Cmp, TV, FV); in LowerSELECT_CC()
6061 return DAG.getNode(PPCISD::FSEL, dl, ResVT, Cmp, FV, TV); in LowerSELECT_CC()
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/NextBSD/contrib/llvm/include/llvm/Target/
HDTargetLowering.h1698 virtual bool isExtractSubvectorCheap(EVT ResVT, unsigned Index) const { in isExtractSubvectorCheap() argument