1 //===-- X86ISelLowering.h - X86 DAG Lowering Interface ----------*- C++ -*-===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file defines the interfaces that X86 uses to lower LLVM code into a 11 // selection DAG. 12 // 13 //===----------------------------------------------------------------------===// 14 15 #ifndef LLVM_LIB_TARGET_X86_X86ISELLOWERING_H 16 #define LLVM_LIB_TARGET_X86_X86ISELLOWERING_H 17 18 #include "llvm/CodeGen/CallingConvLower.h" 19 #include "llvm/CodeGen/SelectionDAG.h" 20 #include "llvm/Target/TargetLowering.h" 21 #include "llvm/Target/TargetOptions.h" 22 23 namespace llvm { 24 class X86Subtarget; 25 class X86TargetMachine; 26 27 namespace X86ISD { 28 // X86 Specific DAG Nodes 29 enum NodeType : unsigned { 30 // Start the numbering where the builtin ops leave off. 31 FIRST_NUMBER = ISD::BUILTIN_OP_END, 32 33 /// Bit scan forward. 34 BSF, 35 /// Bit scan reverse. 36 BSR, 37 38 /// Double shift instructions. These correspond to 39 /// X86::SHLDxx and X86::SHRDxx instructions. 40 SHLD, 41 SHRD, 42 43 /// Bitwise logical AND of floating point values. This corresponds 44 /// to X86::ANDPS or X86::ANDPD. 45 FAND, 46 47 /// Bitwise logical OR of floating point values. This corresponds 48 /// to X86::ORPS or X86::ORPD. 49 FOR, 50 51 /// Bitwise logical XOR of floating point values. This corresponds 52 /// to X86::XORPS or X86::XORPD. 53 FXOR, 54 55 /// Bitwise logical ANDNOT of floating point values. This 56 /// corresponds to X86::ANDNPS or X86::ANDNPD. 57 FANDN, 58 59 /// These operations represent an abstract X86 call 60 /// instruction, which includes a bunch of information. In particular the 61 /// operands of these node are: 62 /// 63 /// #0 - The incoming token chain 64 /// #1 - The callee 65 /// #2 - The number of arg bytes the caller pushes on the stack. 66 /// #3 - The number of arg bytes the callee pops off the stack. 67 /// #4 - The value to pass in AL/AX/EAX (optional) 68 /// #5 - The value to pass in DL/DX/EDX (optional) 69 /// 70 /// The result values of these nodes are: 71 /// 72 /// #0 - The outgoing token chain 73 /// #1 - The first register result value (optional) 74 /// #2 - The second register result value (optional) 75 /// 76 CALL, 77 78 /// This operation implements the lowering for readcyclecounter 79 RDTSC_DAG, 80 81 /// X86 Read Time-Stamp Counter and Processor ID. 82 RDTSCP_DAG, 83 84 /// X86 Read Performance Monitoring Counters. 85 RDPMC_DAG, 86 87 /// X86 compare and logical compare instructions. 88 CMP, COMI, UCOMI, 89 90 /// X86 bit-test instructions. 91 BT, 92 93 /// X86 SetCC. Operand 0 is condition code, and operand 1 is the EFLAGS 94 /// operand, usually produced by a CMP instruction. 95 SETCC, 96 97 /// X86 Select 98 SELECT, 99 100 // Same as SETCC except it's materialized with a sbb and the value is all 101 // one's or all zero's. 102 SETCC_CARRY, // R = carry_bit ? ~0 : 0 103 104 /// X86 FP SETCC, implemented with CMP{cc}SS/CMP{cc}SD. 105 /// Operands are two FP values to compare; result is a mask of 106 /// 0s or 1s. Generally DTRT for C/C++ with NaNs. 107 FSETCC, 108 109 /// X86 MOVMSK{pd|ps}, extracts sign bits of two or four FP values, 110 /// result in an integer GPR. Needs masking for scalar result. 111 FGETSIGNx86, 112 113 /// X86 conditional moves. Operand 0 and operand 1 are the two values 114 /// to select from. Operand 2 is the condition code, and operand 3 is the 115 /// flag operand produced by a CMP or TEST instruction. It also writes a 116 /// flag result. 117 CMOV, 118 119 /// X86 conditional branches. Operand 0 is the chain operand, operand 1 120 /// is the block to branch if condition is true, operand 2 is the 121 /// condition code, and operand 3 is the flag operand produced by a CMP 122 /// or TEST instruction. 123 BRCOND, 124 125 /// Return with a flag operand. Operand 0 is the chain operand, operand 126 /// 1 is the number of bytes of stack to pop. 127 RET_FLAG, 128 129 /// Repeat fill, corresponds to X86::REP_STOSx. 130 REP_STOS, 131 132 /// Repeat move, corresponds to X86::REP_MOVSx. 133 REP_MOVS, 134 135 /// On Darwin, this node represents the result of the popl 136 /// at function entry, used for PIC code. 137 GlobalBaseReg, 138 139 /// A wrapper node for TargetConstantPool, 140 /// TargetExternalSymbol, and TargetGlobalAddress. 141 Wrapper, 142 143 /// Special wrapper used under X86-64 PIC mode for RIP 144 /// relative displacements. 145 WrapperRIP, 146 147 /// Copies a 64-bit value from the low word of an XMM vector 148 /// to an MMX vector. If you think this is too close to the previous 149 /// mnemonic, so do I; blame Intel. 150 MOVDQ2Q, 151 152 /// Copies a 32-bit value from the low word of a MMX 153 /// vector to a GPR. 154 MMX_MOVD2W, 155 156 /// Copies a GPR into the low 32-bit word of a MMX vector 157 /// and zero out the high word. 158 MMX_MOVW2D, 159 160 /// Extract an 8-bit value from a vector and zero extend it to 161 /// i32, corresponds to X86::PEXTRB. 162 PEXTRB, 163 164 /// Extract a 16-bit value from a vector and zero extend it to 165 /// i32, corresponds to X86::PEXTRW. 166 PEXTRW, 167 168 /// Insert any element of a 4 x float vector into any element 169 /// of a destination 4 x floatvector. 170 INSERTPS, 171 172 /// Insert the lower 8-bits of a 32-bit value to a vector, 173 /// corresponds to X86::PINSRB. 174 PINSRB, 175 176 /// Insert the lower 16-bits of a 32-bit value to a vector, 177 /// corresponds to X86::PINSRW. 178 PINSRW, MMX_PINSRW, 179 180 /// Shuffle 16 8-bit values within a vector. 181 PSHUFB, 182 183 /// Compute Sum of Absolute Differences. 184 PSADBW, 185 186 /// Bitwise Logical AND NOT of Packed FP values. 187 ANDNP, 188 189 /// Copy integer sign. 190 PSIGN, 191 192 /// Blend where the selector is an immediate. 193 BLENDI, 194 195 /// Blend where the condition has been shrunk. 196 /// This is used to emphasize that the condition mask is 197 /// no more valid for generic VSELECT optimizations. 198 SHRUNKBLEND, 199 200 /// Combined add and sub on an FP vector. 201 ADDSUB, 202 203 // FP vector ops with rounding mode. 204 FADD_RND, 205 FSUB_RND, 206 FMUL_RND, 207 FDIV_RND, 208 FMAX_RND, 209 FMIN_RND, 210 FSQRT_RND, 211 212 // FP vector get exponent 213 FGETEXP_RND, 214 // FP Scale 215 SCALEF, 216 // Integer add/sub with unsigned saturation. 217 ADDUS, 218 SUBUS, 219 // Integer add/sub with signed saturation. 220 ADDS, 221 SUBS, 222 // Unsigned Integer average 223 AVG, 224 /// Integer horizontal add. 225 HADD, 226 227 /// Integer horizontal sub. 228 HSUB, 229 230 /// Floating point horizontal add. 231 FHADD, 232 233 /// Floating point horizontal sub. 234 FHSUB, 235 236 // Integer absolute value 237 ABS, 238 239 /// Floating point max and min. 240 FMAX, FMIN, 241 242 /// Commutative FMIN and FMAX. 243 FMAXC, FMINC, 244 245 /// Floating point reciprocal-sqrt and reciprocal approximation. 246 /// Note that these typically require refinement 247 /// in order to obtain suitable precision. 248 FRSQRT, FRCP, 249 250 // Thread Local Storage. 251 TLSADDR, 252 253 // Thread Local Storage. A call to get the start address 254 // of the TLS block for the current module. 255 TLSBASEADDR, 256 257 // Thread Local Storage. When calling to an OS provided 258 // thunk at the address from an earlier relocation. 259 TLSCALL, 260 261 // Exception Handling helpers. 262 EH_RETURN, 263 264 // SjLj exception handling setjmp. 265 EH_SJLJ_SETJMP, 266 267 // SjLj exception handling longjmp. 268 EH_SJLJ_LONGJMP, 269 270 /// Tail call return. See X86TargetLowering::LowerCall for 271 /// the list of operands. 272 TC_RETURN, 273 274 // Vector move to low scalar and zero higher vector elements. 275 VZEXT_MOVL, 276 277 // Vector integer zero-extend. 278 VZEXT, 279 280 // Vector integer signed-extend. 281 VSEXT, 282 283 // Vector integer truncate. 284 VTRUNC, 285 286 // Vector integer truncate with mask. 287 VTRUNCM, 288 289 // Vector FP extend. 290 VFPEXT, 291 292 // Vector FP round. 293 VFPROUND, 294 295 // Vector signed/unsigned integer to double. 296 CVTDQ2PD, CVTUDQ2PD, 297 298 // 128-bit vector logical left / right shift 299 VSHLDQ, VSRLDQ, 300 301 // Vector shift elements 302 VSHL, VSRL, VSRA, 303 304 // Vector shift elements by immediate 305 VSHLI, VSRLI, VSRAI, 306 307 // Vector packed double/float comparison. 308 CMPP, 309 310 // Vector integer comparisons. 311 PCMPEQ, PCMPGT, 312 // Vector integer comparisons, the result is in a mask vector. 313 PCMPEQM, PCMPGTM, 314 315 /// Vector comparison generating mask bits for fp and 316 /// integer signed and unsigned data types. 317 CMPM, 318 CMPMU, 319 // Vector comparison with rounding mode for FP values 320 CMPM_RND, 321 322 // Arithmetic operations with FLAGS results. 323 ADD, SUB, ADC, SBB, SMUL, 324 INC, DEC, OR, XOR, AND, 325 326 BEXTR, // Bit field extract 327 328 UMUL, // LOW, HI, FLAGS = umul LHS, RHS 329 330 // 8-bit SMUL/UMUL - AX, FLAGS = smul8/umul8 AL, RHS 331 SMUL8, UMUL8, 332 333 // 8-bit divrem that zero-extend the high result (AH). 334 UDIVREM8_ZEXT_HREG, 335 SDIVREM8_SEXT_HREG, 336 337 // X86-specific multiply by immediate. 338 MUL_IMM, 339 340 // Vector bitwise comparisons. 341 PTEST, 342 343 // Vector packed fp sign bitwise comparisons. 344 TESTP, 345 346 // Vector "test" in AVX-512, the result is in a mask vector. 347 TESTM, 348 TESTNM, 349 350 // OR/AND test for masks 351 KORTEST, 352 353 // Several flavors of instructions with vector shuffle behaviors. 354 PACKSS, 355 PACKUS, 356 // Intra-lane alignr 357 PALIGNR, 358 // AVX512 inter-lane alignr 359 VALIGN, 360 PSHUFD, 361 PSHUFHW, 362 PSHUFLW, 363 SHUFP, 364 //Shuffle Packed Values at 128-bit granularity 365 SHUF128, 366 MOVDDUP, 367 MOVSHDUP, 368 MOVSLDUP, 369 MOVLHPS, 370 MOVLHPD, 371 MOVHLPS, 372 MOVLPS, 373 MOVLPD, 374 MOVSD, 375 MOVSS, 376 UNPCKL, 377 UNPCKH, 378 VPERMILPV, 379 VPERMILPI, 380 VPERMV, 381 VPERMV3, 382 VPERMIV3, 383 VPERMI, 384 VPERM2X128, 385 //Fix Up Special Packed Float32/64 values 386 VFIXUPIMM, 387 //Range Restriction Calculation For Packed Pairs of Float32/64 values 388 VRANGE, 389 // Broadcast scalar to vector 390 VBROADCAST, 391 // Broadcast subvector to vector 392 SUBV_BROADCAST, 393 // Insert/Extract vector element 394 VINSERT, 395 VEXTRACT, 396 397 /// SSE4A Extraction and Insertion. 398 EXTRQI, INSERTQI, 399 400 // Vector multiply packed unsigned doubleword integers 401 PMULUDQ, 402 // Vector multiply packed signed doubleword integers 403 PMULDQ, 404 // Vector Multiply Packed UnsignedIntegers with Round and Scale 405 MULHRS, 406 407 // FMA nodes 408 FMADD, 409 FNMADD, 410 FMSUB, 411 FNMSUB, 412 FMADDSUB, 413 FMSUBADD, 414 // FMA with rounding mode 415 FMADD_RND, 416 FNMADD_RND, 417 FMSUB_RND, 418 FNMSUB_RND, 419 FMADDSUB_RND, 420 FMSUBADD_RND, 421 RNDSCALE, 422 423 // Compress and expand 424 COMPRESS, 425 EXPAND, 426 427 //Convert Unsigned/Integer to Scalar Floating-Point Value 428 //with rounding mode 429 SINT_TO_FP_RND, 430 UINT_TO_FP_RND, 431 432 // Vector float/double to signed/unsigned integer. 433 FP_TO_SINT_RND, FP_TO_UINT_RND, 434 // Save xmm argument registers to the stack, according to %al. An operator 435 // is needed so that this can be expanded with control flow. 436 VASTART_SAVE_XMM_REGS, 437 438 // Windows's _chkstk call to do stack probing. 439 WIN_ALLOCA, 440 441 // For allocating variable amounts of stack space when using 442 // segmented stacks. Check if the current stacklet has enough space, and 443 // falls back to heap allocation if not. 444 SEG_ALLOCA, 445 446 // Windows's _ftol2 runtime routine to do fptoui. 447 WIN_FTOL, 448 449 // Memory barrier 450 MEMBARRIER, 451 MFENCE, 452 SFENCE, 453 LFENCE, 454 455 // Store FP status word into i16 register. 456 FNSTSW16r, 457 458 // Store contents of %ah into %eflags. 459 SAHF, 460 461 // Get a random integer and indicate whether it is valid in CF. 462 RDRAND, 463 464 // Get a NIST SP800-90B & C compliant random integer and 465 // indicate whether it is valid in CF. 466 RDSEED, 467 468 PCMPISTRI, 469 PCMPESTRI, 470 471 // Test if in transactional execution. 472 XTEST, 473 474 // ERI instructions 475 RSQRT28, RCP28, EXP2, 476 477 // Compare and swap. 478 LCMPXCHG_DAG = ISD::FIRST_TARGET_MEMORY_OPCODE, 479 LCMPXCHG8_DAG, 480 LCMPXCHG16_DAG, 481 482 // Load, scalar_to_vector, and zero extend. 483 VZEXT_LOAD, 484 485 // Store FP control world into i16 memory. 486 FNSTCW16m, 487 488 /// This instruction implements FP_TO_SINT with the 489 /// integer destination in memory and a FP reg source. This corresponds 490 /// to the X86::FIST*m instructions and the rounding mode change stuff. It 491 /// has two inputs (token chain and address) and two outputs (int value 492 /// and token chain). 493 FP_TO_INT16_IN_MEM, 494 FP_TO_INT32_IN_MEM, 495 FP_TO_INT64_IN_MEM, 496 497 /// This instruction implements SINT_TO_FP with the 498 /// integer source in memory and FP reg result. This corresponds to the 499 /// X86::FILD*m instructions. It has three inputs (token chain, address, 500 /// and source type) and two outputs (FP value and token chain). FILD_FLAG 501 /// also produces a flag). 502 FILD, 503 FILD_FLAG, 504 505 /// This instruction implements an extending load to FP stack slots. 506 /// This corresponds to the X86::FLD32m / X86::FLD64m. It takes a chain 507 /// operand, ptr to load from, and a ValueType node indicating the type 508 /// to load to. 509 FLD, 510 511 /// This instruction implements a truncating store to FP stack 512 /// slots. This corresponds to the X86::FST32m / X86::FST64m. It takes a 513 /// chain operand, value to store, address, and a ValueType to store it 514 /// as. 515 FST, 516 517 /// This instruction grabs the address of the next argument 518 /// from a va_list. (reads and modifies the va_list in memory) 519 VAARG_64 520 521 // WARNING: Do not add anything in the end unless you want the node to 522 // have memop! In fact, starting from ATOMADD64_DAG all opcodes will be 523 // thought as target memory ops! 524 }; 525 } 526 527 /// Define some predicates that are used for node matching. 528 namespace X86 { 529 /// Return true if the specified 530 /// EXTRACT_SUBVECTOR operand specifies a vector extract that is 531 /// suitable for input to VEXTRACTF128, VEXTRACTI128 instructions. 532 bool isVEXTRACT128Index(SDNode *N); 533 534 /// Return true if the specified 535 /// INSERT_SUBVECTOR operand specifies a subvector insert that is 536 /// suitable for input to VINSERTF128, VINSERTI128 instructions. 537 bool isVINSERT128Index(SDNode *N); 538 539 /// Return true if the specified 540 /// EXTRACT_SUBVECTOR operand specifies a vector extract that is 541 /// suitable for input to VEXTRACTF64X4, VEXTRACTI64X4 instructions. 542 bool isVEXTRACT256Index(SDNode *N); 543 544 /// Return true if the specified 545 /// INSERT_SUBVECTOR operand specifies a subvector insert that is 546 /// suitable for input to VINSERTF64X4, VINSERTI64X4 instructions. 547 bool isVINSERT256Index(SDNode *N); 548 549 /// Return the appropriate 550 /// immediate to extract the specified EXTRACT_SUBVECTOR index 551 /// with VEXTRACTF128, VEXTRACTI128 instructions. 552 unsigned getExtractVEXTRACT128Immediate(SDNode *N); 553 554 /// Return the appropriate 555 /// immediate to insert at the specified INSERT_SUBVECTOR index 556 /// with VINSERTF128, VINSERT128 instructions. 557 unsigned getInsertVINSERT128Immediate(SDNode *N); 558 559 /// Return the appropriate 560 /// immediate to extract the specified EXTRACT_SUBVECTOR index 561 /// with VEXTRACTF64X4, VEXTRACTI64x4 instructions. 562 unsigned getExtractVEXTRACT256Immediate(SDNode *N); 563 564 /// Return the appropriate 565 /// immediate to insert at the specified INSERT_SUBVECTOR index 566 /// with VINSERTF64x4, VINSERTI64x4 instructions. 567 unsigned getInsertVINSERT256Immediate(SDNode *N); 568 569 /// Returns true if Elt is a constant zero or floating point constant +0.0. 570 bool isZeroNode(SDValue Elt); 571 572 /// Returns true of the given offset can be 573 /// fit into displacement field of the instruction. 574 bool isOffsetSuitableForCodeModel(int64_t Offset, CodeModel::Model M, 575 bool hasSymbolicDisplacement = true); 576 577 578 /// Determines whether the callee is required to pop its 579 /// own arguments. Callee pop is necessary to support tail calls. 580 bool isCalleePop(CallingConv::ID CallingConv, 581 bool is64Bit, bool IsVarArg, bool TailCallOpt); 582 583 /// AVX512 static rounding constants. These need to match the values in 584 /// avx512fintrin.h. 585 enum STATIC_ROUNDING { 586 TO_NEAREST_INT = 0, 587 TO_NEG_INF = 1, 588 TO_POS_INF = 2, 589 TO_ZERO = 3, 590 CUR_DIRECTION = 4 591 }; 592 } 593 594 //===--------------------------------------------------------------------===// 595 // X86 Implementation of the TargetLowering interface 596 class X86TargetLowering final : public TargetLowering { 597 public: 598 explicit X86TargetLowering(const X86TargetMachine &TM, 599 const X86Subtarget &STI); 600 601 unsigned getJumpTableEncoding() const override; 602 bool useSoftFloat() const override; 603 getScalarShiftAmountTy(const DataLayout &,EVT)604 MVT getScalarShiftAmountTy(const DataLayout &, EVT) const override { 605 return MVT::i8; 606 } 607 608 const MCExpr * 609 LowerCustomJumpTableEntry(const MachineJumpTableInfo *MJTI, 610 const MachineBasicBlock *MBB, unsigned uid, 611 MCContext &Ctx) const override; 612 613 /// Returns relocation base for the given PIC jumptable. 614 SDValue getPICJumpTableRelocBase(SDValue Table, 615 SelectionDAG &DAG) const override; 616 const MCExpr * 617 getPICJumpTableRelocBaseExpr(const MachineFunction *MF, 618 unsigned JTI, MCContext &Ctx) const override; 619 620 /// Return the desired alignment for ByVal aggregate 621 /// function arguments in the caller parameter area. For X86, aggregates 622 /// that contains are placed at 16-byte boundaries while the rest are at 623 /// 4-byte boundaries. 624 unsigned getByValTypeAlignment(Type *Ty, 625 const DataLayout &DL) const override; 626 627 /// Returns the target specific optimal type for load 628 /// and store operations as a result of memset, memcpy, and memmove 629 /// lowering. If DstAlign is zero that means it's safe to destination 630 /// alignment can satisfy any constraint. Similarly if SrcAlign is zero it 631 /// means there isn't a need to check it against alignment requirement, 632 /// probably because the source does not need to be loaded. If 'IsMemset' is 633 /// true, that means it's expanding a memset. If 'ZeroMemset' is true, that 634 /// means it's a memset of zero. 'MemcpyStrSrc' indicates whether the memcpy 635 /// source is constant so it does not need to be loaded. 636 /// It returns EVT::Other if the type should be determined using generic 637 /// target-independent logic. 638 EVT getOptimalMemOpType(uint64_t Size, unsigned DstAlign, unsigned SrcAlign, 639 bool IsMemset, bool ZeroMemset, bool MemcpyStrSrc, 640 MachineFunction &MF) const override; 641 642 /// Returns true if it's safe to use load / store of the 643 /// specified type to expand memcpy / memset inline. This is mostly true 644 /// for all types except for some special cases. For example, on X86 645 /// targets without SSE2 f64 load / store are done with fldl / fstpl which 646 /// also does type conversion. Note the specified type doesn't have to be 647 /// legal as the hook is used before type legalization. 648 bool isSafeMemOpType(MVT VT) const override; 649 650 /// Returns true if the target allows unaligned memory accesses of the 651 /// specified type. Returns whether it is "fast" in the last argument. 652 bool allowsMisalignedMemoryAccesses(EVT VT, unsigned AS, unsigned Align, 653 bool *Fast) const override; 654 655 /// Provide custom lowering hooks for some operations. 656 /// 657 SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override; 658 659 /// Replace the results of node with an illegal result 660 /// type with new values built out of custom code. 661 /// 662 void ReplaceNodeResults(SDNode *N, SmallVectorImpl<SDValue>&Results, 663 SelectionDAG &DAG) const override; 664 665 666 SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override; 667 668 /// Return true if the target has native support for 669 /// the specified value type and it is 'desirable' to use the type for the 670 /// given node type. e.g. On x86 i16 is legal, but undesirable since i16 671 /// instruction encodings are longer and some i16 instructions are slow. 672 bool isTypeDesirableForOp(unsigned Opc, EVT VT) const override; 673 674 /// Return true if the target has native support for the 675 /// specified value type and it is 'desirable' to use the type. e.g. On x86 676 /// i16 is legal, but undesirable since i16 instruction encodings are longer 677 /// and some i16 instructions are slow. 678 bool IsDesirableToPromoteOp(SDValue Op, EVT &PVT) const override; 679 680 MachineBasicBlock * 681 EmitInstrWithCustomInserter(MachineInstr *MI, 682 MachineBasicBlock *MBB) const override; 683 684 685 /// This method returns the name of a target specific DAG node. 686 const char *getTargetNodeName(unsigned Opcode) const override; 687 688 bool isCheapToSpeculateCttz() const override; 689 690 bool isCheapToSpeculateCtlz() const override; 691 692 /// Return the value type to use for ISD::SETCC. 693 EVT getSetCCResultType(const DataLayout &DL, LLVMContext &Context, 694 EVT VT) const override; 695 696 /// Determine which of the bits specified in Mask are known to be either 697 /// zero or one and return them in the KnownZero/KnownOne bitsets. 698 void computeKnownBitsForTargetNode(const SDValue Op, 699 APInt &KnownZero, 700 APInt &KnownOne, 701 const SelectionDAG &DAG, 702 unsigned Depth = 0) const override; 703 704 /// Determine the number of bits in the operation that are sign bits. 705 unsigned ComputeNumSignBitsForTargetNode(SDValue Op, 706 const SelectionDAG &DAG, 707 unsigned Depth) const override; 708 709 bool isGAPlusOffset(SDNode *N, const GlobalValue* &GA, 710 int64_t &Offset) const override; 711 712 SDValue getReturnAddressFrameIndex(SelectionDAG &DAG) const; 713 714 bool ExpandInlineAsm(CallInst *CI) const override; 715 716 ConstraintType getConstraintType(StringRef Constraint) const override; 717 718 /// Examine constraint string and operand type and determine a weight value. 719 /// The operand object must already have been set up with the operand type. 720 ConstraintWeight 721 getSingleConstraintMatchWeight(AsmOperandInfo &info, 722 const char *constraint) const override; 723 724 const char *LowerXConstraint(EVT ConstraintVT) const override; 725 726 /// Lower the specified operand into the Ops vector. If it is invalid, don't 727 /// add anything to Ops. If hasMemory is true it means one of the asm 728 /// constraint of the inline asm instruction being processed is 'm'. 729 void LowerAsmOperandForConstraint(SDValue Op, 730 std::string &Constraint, 731 std::vector<SDValue> &Ops, 732 SelectionDAG &DAG) const override; 733 734 unsigned getInlineAsmMemConstraint(StringRef ConstraintCode)735 getInlineAsmMemConstraint(StringRef ConstraintCode) const override { 736 if (ConstraintCode == "i") 737 return InlineAsm::Constraint_i; 738 else if (ConstraintCode == "o") 739 return InlineAsm::Constraint_o; 740 else if (ConstraintCode == "v") 741 return InlineAsm::Constraint_v; 742 else if (ConstraintCode == "X") 743 return InlineAsm::Constraint_X; 744 return TargetLowering::getInlineAsmMemConstraint(ConstraintCode); 745 } 746 747 /// Given a physical register constraint 748 /// (e.g. {edx}), return the register number and the register class for the 749 /// register. This should only be used for C_Register constraints. On 750 /// error, this returns a register number of 0. 751 std::pair<unsigned, const TargetRegisterClass *> 752 getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI, 753 StringRef Constraint, MVT VT) const override; 754 755 /// Return true if the addressing mode represented 756 /// by AM is legal for this target, for a load/store of the specified type. 757 bool isLegalAddressingMode(const DataLayout &DL, const AddrMode &AM, 758 Type *Ty, unsigned AS) const override; 759 760 /// Return true if the specified immediate is legal 761 /// icmp immediate, that is the target has icmp instructions which can 762 /// compare a register against the immediate without having to materialize 763 /// the immediate into a register. 764 bool isLegalICmpImmediate(int64_t Imm) const override; 765 766 /// Return true if the specified immediate is legal 767 /// add immediate, that is the target has add instructions which can 768 /// add a register and the immediate without having to materialize 769 /// the immediate into a register. 770 bool isLegalAddImmediate(int64_t Imm) const override; 771 772 /// \brief Return the cost of the scaling factor used in the addressing 773 /// mode represented by AM for this target, for a load/store 774 /// of the specified type. 775 /// If the AM is supported, the return value must be >= 0. 776 /// If the AM is not supported, it returns a negative value. 777 int getScalingFactorCost(const DataLayout &DL, const AddrMode &AM, Type *Ty, 778 unsigned AS) const override; 779 780 bool isVectorShiftByScalarCheap(Type *Ty) const override; 781 782 /// Return true if it's free to truncate a value of 783 /// type Ty1 to type Ty2. e.g. On x86 it's free to truncate a i32 value in 784 /// register EAX to i16 by referencing its sub-register AX. 785 bool isTruncateFree(Type *Ty1, Type *Ty2) const override; 786 bool isTruncateFree(EVT VT1, EVT VT2) const override; 787 788 bool allowTruncateForTailCall(Type *Ty1, Type *Ty2) const override; 789 790 /// Return true if any actual instruction that defines a 791 /// value of type Ty1 implicit zero-extends the value to Ty2 in the result 792 /// register. This does not necessarily include registers defined in 793 /// unknown ways, such as incoming arguments, or copies from unknown 794 /// virtual registers. Also, if isTruncateFree(Ty2, Ty1) is true, this 795 /// does not necessarily apply to truncate instructions. e.g. on x86-64, 796 /// all instructions that define 32-bit values implicit zero-extend the 797 /// result out to 64 bits. 798 bool isZExtFree(Type *Ty1, Type *Ty2) const override; 799 bool isZExtFree(EVT VT1, EVT VT2) const override; 800 bool isZExtFree(SDValue Val, EVT VT2) const override; 801 802 /// Return true if folding a vector load into ExtVal (a sign, zero, or any 803 /// extend node) is profitable. 804 bool isVectorLoadExtDesirable(SDValue) const override; 805 806 /// Return true if an FMA operation is faster than a pair of fmul and fadd 807 /// instructions. fmuladd intrinsics will be expanded to FMAs when this 808 /// method returns true, otherwise fmuladd is expanded to fmul + fadd. 809 bool isFMAFasterThanFMulAndFAdd(EVT VT) const override; 810 811 /// Return true if it's profitable to narrow 812 /// operations of type VT1 to VT2. e.g. on x86, it's profitable to narrow 813 /// from i32 to i8 but not from i32 to i16. 814 bool isNarrowingProfitable(EVT VT1, EVT VT2) const override; 815 816 /// Returns true if the target can instruction select the 817 /// specified FP immediate natively. If false, the legalizer will 818 /// materialize the FP immediate as a load from a constant pool. 819 bool isFPImmLegal(const APFloat &Imm, EVT VT) const override; 820 821 /// Targets can use this to indicate that they only support *some* 822 /// VECTOR_SHUFFLE operations, those with specific masks. By default, if a 823 /// target supports the VECTOR_SHUFFLE node, all mask values are assumed to 824 /// be legal. 825 bool isShuffleMaskLegal(const SmallVectorImpl<int> &Mask, 826 EVT VT) const override; 827 828 /// Similar to isShuffleMaskLegal. This is used by Targets can use this to 829 /// indicate if there is a suitable VECTOR_SHUFFLE that can be used to 830 /// replace a VAND with a constant pool entry. 831 bool isVectorClearMaskLegal(const SmallVectorImpl<int> &Mask, 832 EVT VT) const override; 833 834 /// If true, then instruction selection should 835 /// seek to shrink the FP constant of the specified type to a smaller type 836 /// in order to save space and / or reduce runtime. ShouldShrinkFPConstant(EVT VT)837 bool ShouldShrinkFPConstant(EVT VT) const override { 838 // Don't shrink FP constpool if SSE2 is available since cvtss2sd is more 839 // expensive than a straight movsd. On the other hand, it's important to 840 // shrink long double fp constant since fldt is very slow. 841 return !X86ScalarSSEf64 || VT == MVT::f80; 842 } 843 844 /// Return true if we believe it is correct and profitable to reduce the 845 /// load node to a smaller type. 846 bool shouldReduceLoadWidth(SDNode *Load, ISD::LoadExtType ExtTy, 847 EVT NewVT) const override; 848 849 /// Return true if the specified scalar FP type is computed in an SSE 850 /// register, not on the X87 floating point stack. isScalarFPTypeInSSEReg(EVT VT)851 bool isScalarFPTypeInSSEReg(EVT VT) const { 852 return (VT == MVT::f64 && X86ScalarSSEf64) || // f64 is when SSE2 853 (VT == MVT::f32 && X86ScalarSSEf32); // f32 is when SSE1 854 } 855 856 /// Return true if the target uses the MSVC _ftol2 routine for fptoui. 857 bool isTargetFTOL() const; 858 859 /// Return true if the MSVC _ftol2 routine should be used for fptoui to the 860 /// given type. isIntegerTypeFTOL(EVT VT)861 bool isIntegerTypeFTOL(EVT VT) const { 862 return isTargetFTOL() && VT == MVT::i64; 863 } 864 865 /// \brief Returns true if it is beneficial to convert a load of a constant 866 /// to just the constant itself. 867 bool shouldConvertConstantLoadToIntImm(const APInt &Imm, 868 Type *Ty) const override; 869 870 /// Return true if EXTRACT_SUBVECTOR is cheap for this result type 871 /// with this index. 872 bool isExtractSubvectorCheap(EVT ResVT, unsigned Index) const override; 873 874 /// Intel processors have a unified instruction and data cache getClearCacheBuiltinName()875 const char * getClearCacheBuiltinName() const override { 876 return nullptr; // nothing to do, move along. 877 } 878 879 unsigned getRegisterByName(const char* RegName, EVT VT, 880 SelectionDAG &DAG) const override; 881 882 /// This method returns a target specific FastISel object, 883 /// or null if the target does not support "fast" ISel. 884 FastISel *createFastISel(FunctionLoweringInfo &funcInfo, 885 const TargetLibraryInfo *libInfo) const override; 886 887 /// Return true if the target stores stack protector cookies at a fixed 888 /// offset in some non-standard address space, and populates the address 889 /// space and offset as appropriate. 890 bool getStackCookieLocation(unsigned &AddressSpace, 891 unsigned &Offset) const override; 892 893 SDValue BuildFILD(SDValue Op, EVT SrcVT, SDValue Chain, SDValue StackSlot, 894 SelectionDAG &DAG) const; 895 896 bool isNoopAddrSpaceCast(unsigned SrcAS, unsigned DestAS) const override; 897 898 bool useLoadStackGuardNode() const override; 899 /// \brief Customize the preferred legalization strategy for certain types. 900 LegalizeTypeAction getPreferredVectorAction(EVT VT) const override; 901 902 protected: 903 std::pair<const TargetRegisterClass *, uint8_t> 904 findRepresentativeClass(const TargetRegisterInfo *TRI, 905 MVT VT) const override; 906 907 private: 908 /// Keep a pointer to the X86Subtarget around so that we can 909 /// make the right decision when generating code for different targets. 910 const X86Subtarget *Subtarget; 911 const DataLayout *TD; 912 913 /// Select between SSE or x87 floating point ops. 914 /// When SSE is available, use it for f32 operations. 915 /// When SSE2 is available, use it for f64 operations. 916 bool X86ScalarSSEf32; 917 bool X86ScalarSSEf64; 918 919 /// A list of legal FP immediates. 920 std::vector<APFloat> LegalFPImmediates; 921 922 /// Indicate that this x86 target can instruction 923 /// select the specified FP immediate natively. addLegalFPImmediate(const APFloat & Imm)924 void addLegalFPImmediate(const APFloat& Imm) { 925 LegalFPImmediates.push_back(Imm); 926 } 927 928 SDValue LowerCallResult(SDValue Chain, SDValue InFlag, 929 CallingConv::ID CallConv, bool isVarArg, 930 const SmallVectorImpl<ISD::InputArg> &Ins, 931 SDLoc dl, SelectionDAG &DAG, 932 SmallVectorImpl<SDValue> &InVals) const; 933 SDValue LowerMemArgument(SDValue Chain, 934 CallingConv::ID CallConv, 935 const SmallVectorImpl<ISD::InputArg> &ArgInfo, 936 SDLoc dl, SelectionDAG &DAG, 937 const CCValAssign &VA, MachineFrameInfo *MFI, 938 unsigned i) const; 939 SDValue LowerMemOpCallTo(SDValue Chain, SDValue StackPtr, SDValue Arg, 940 SDLoc dl, SelectionDAG &DAG, 941 const CCValAssign &VA, 942 ISD::ArgFlagsTy Flags) const; 943 944 // Call lowering helpers. 945 946 /// Check whether the call is eligible for tail call optimization. Targets 947 /// that want to do tail call optimization should implement this function. 948 bool IsEligibleForTailCallOptimization(SDValue Callee, 949 CallingConv::ID CalleeCC, 950 bool isVarArg, 951 bool isCalleeStructRet, 952 bool isCallerStructRet, 953 Type *RetTy, 954 const SmallVectorImpl<ISD::OutputArg> &Outs, 955 const SmallVectorImpl<SDValue> &OutVals, 956 const SmallVectorImpl<ISD::InputArg> &Ins, 957 SelectionDAG& DAG) const; 958 bool IsCalleePop(bool isVarArg, CallingConv::ID CallConv) const; 959 SDValue EmitTailCallLoadRetAddr(SelectionDAG &DAG, SDValue &OutRetAddr, 960 SDValue Chain, bool IsTailCall, bool Is64Bit, 961 int FPDiff, SDLoc dl) const; 962 963 unsigned GetAlignedArgumentStackSize(unsigned StackSize, 964 SelectionDAG &DAG) const; 965 966 std::pair<SDValue,SDValue> FP_TO_INTHelper(SDValue Op, SelectionDAG &DAG, 967 bool isSigned, 968 bool isReplace) const; 969 970 SDValue LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) const; 971 SDValue LowerBUILD_VECTORvXi1(SDValue Op, SelectionDAG &DAG) const; 972 SDValue LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) const; 973 SDValue LowerVSELECT(SDValue Op, SelectionDAG &DAG) const; 974 SDValue LowerEXTRACT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const; 975 SDValue ExtractBitFromMaskVector(SDValue Op, SelectionDAG &DAG) const; 976 SDValue InsertBitToMaskVector(SDValue Op, SelectionDAG &DAG) const; 977 978 SDValue LowerINSERT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const; 979 SDValue LowerConstantPool(SDValue Op, SelectionDAG &DAG) const; 980 SDValue LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const; 981 SDValue LowerGlobalAddress(const GlobalValue *GV, SDLoc dl, 982 int64_t Offset, SelectionDAG &DAG) const; 983 SDValue LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const; 984 SDValue LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const; 985 SDValue LowerExternalSymbol(SDValue Op, SelectionDAG &DAG) const; 986 SDValue LowerSINT_TO_FP(SDValue Op, SelectionDAG &DAG) const; 987 SDValue LowerUINT_TO_FP(SDValue Op, SelectionDAG &DAG) const; 988 SDValue LowerUINT_TO_FP_i64(SDValue Op, SelectionDAG &DAG) const; 989 SDValue LowerUINT_TO_FP_i32(SDValue Op, SelectionDAG &DAG) const; 990 SDValue lowerUINT_TO_FP_vec(SDValue Op, SelectionDAG &DAG) const; 991 SDValue LowerTRUNCATE(SDValue Op, SelectionDAG &DAG) const; 992 SDValue LowerFP_TO_SINT(SDValue Op, SelectionDAG &DAG) const; 993 SDValue LowerFP_TO_UINT(SDValue Op, SelectionDAG &DAG) const; 994 SDValue LowerToBT(SDValue And, ISD::CondCode CC, 995 SDLoc dl, SelectionDAG &DAG) const; 996 SDValue LowerSETCC(SDValue Op, SelectionDAG &DAG) const; 997 SDValue LowerSELECT(SDValue Op, SelectionDAG &DAG) const; 998 SDValue LowerBRCOND(SDValue Op, SelectionDAG &DAG) const; 999 SDValue LowerMEMSET(SDValue Op, SelectionDAG &DAG) const; 1000 SDValue LowerJumpTable(SDValue Op, SelectionDAG &DAG) const; 1001 SDValue LowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG) const; 1002 SDValue LowerVASTART(SDValue Op, SelectionDAG &DAG) const; 1003 SDValue LowerVAARG(SDValue Op, SelectionDAG &DAG) const; 1004 SDValue LowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const; 1005 SDValue LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const; 1006 SDValue LowerFRAME_TO_ARGS_OFFSET(SDValue Op, SelectionDAG &DAG) const; 1007 SDValue LowerEH_RETURN(SDValue Op, SelectionDAG &DAG) const; 1008 SDValue lowerEH_SJLJ_SETJMP(SDValue Op, SelectionDAG &DAG) const; 1009 SDValue lowerEH_SJLJ_LONGJMP(SDValue Op, SelectionDAG &DAG) const; 1010 SDValue LowerINIT_TRAMPOLINE(SDValue Op, SelectionDAG &DAG) const; 1011 SDValue LowerFLT_ROUNDS_(SDValue Op, SelectionDAG &DAG) const; 1012 SDValue LowerWin64_i128OP(SDValue Op, SelectionDAG &DAG) const; 1013 SDValue LowerGC_TRANSITION_START(SDValue Op, SelectionDAG &DAG) const; 1014 SDValue LowerGC_TRANSITION_END(SDValue Op, SelectionDAG &DAG) const; 1015 1016 SDValue 1017 LowerFormalArguments(SDValue Chain, 1018 CallingConv::ID CallConv, bool isVarArg, 1019 const SmallVectorImpl<ISD::InputArg> &Ins, 1020 SDLoc dl, SelectionDAG &DAG, 1021 SmallVectorImpl<SDValue> &InVals) const override; 1022 SDValue LowerCall(CallLoweringInfo &CLI, 1023 SmallVectorImpl<SDValue> &InVals) const override; 1024 1025 SDValue LowerReturn(SDValue Chain, 1026 CallingConv::ID CallConv, bool isVarArg, 1027 const SmallVectorImpl<ISD::OutputArg> &Outs, 1028 const SmallVectorImpl<SDValue> &OutVals, 1029 SDLoc dl, SelectionDAG &DAG) const override; 1030 1031 bool isUsedByReturnOnly(SDNode *N, SDValue &Chain) const override; 1032 1033 bool mayBeEmittedAsTailCall(CallInst *CI) const override; 1034 1035 EVT getTypeForExtArgOrReturn(LLVMContext &Context, EVT VT, 1036 ISD::NodeType ExtendKind) const override; 1037 1038 bool CanLowerReturn(CallingConv::ID CallConv, MachineFunction &MF, 1039 bool isVarArg, 1040 const SmallVectorImpl<ISD::OutputArg> &Outs, 1041 LLVMContext &Context) const override; 1042 1043 const MCPhysReg *getScratchRegisters(CallingConv::ID CC) const override; 1044 1045 bool shouldExpandAtomicLoadInIR(LoadInst *SI) const override; 1046 bool shouldExpandAtomicStoreInIR(StoreInst *SI) const override; 1047 TargetLoweringBase::AtomicRMWExpansionKind 1048 shouldExpandAtomicRMWInIR(AtomicRMWInst *AI) const override; 1049 1050 LoadInst * 1051 lowerIdempotentRMWIntoFencedLoad(AtomicRMWInst *AI) const override; 1052 1053 bool needsCmpXchgNb(const Type *MemType) const; 1054 1055 /// Utility function to emit atomic-load-arith operations (and, or, xor, 1056 /// nand, max, min, umax, umin). It takes the corresponding instruction to 1057 /// expand, the associated machine basic block, and the associated X86 1058 /// opcodes for reg/reg. 1059 MachineBasicBlock *EmitAtomicLoadArith(MachineInstr *MI, 1060 MachineBasicBlock *MBB) const; 1061 1062 /// Utility function to emit atomic-load-arith operations (and, or, xor, 1063 /// nand, add, sub, swap) for 64-bit operands on 32-bit target. 1064 MachineBasicBlock *EmitAtomicLoadArith6432(MachineInstr *MI, 1065 MachineBasicBlock *MBB) const; 1066 1067 // Utility function to emit the low-level va_arg code for X86-64. 1068 MachineBasicBlock *EmitVAARG64WithCustomInserter( 1069 MachineInstr *MI, 1070 MachineBasicBlock *MBB) const; 1071 1072 /// Utility function to emit the xmm reg save portion of va_start. 1073 MachineBasicBlock *EmitVAStartSaveXMMRegsWithCustomInserter( 1074 MachineInstr *BInstr, 1075 MachineBasicBlock *BB) const; 1076 1077 MachineBasicBlock *EmitLoweredSelect(MachineInstr *I, 1078 MachineBasicBlock *BB) const; 1079 1080 MachineBasicBlock *EmitLoweredWinAlloca(MachineInstr *MI, 1081 MachineBasicBlock *BB) const; 1082 1083 MachineBasicBlock *EmitLoweredSegAlloca(MachineInstr *MI, 1084 MachineBasicBlock *BB) const; 1085 1086 MachineBasicBlock *EmitLoweredTLSCall(MachineInstr *MI, 1087 MachineBasicBlock *BB) const; 1088 1089 MachineBasicBlock *emitLoweredTLSAddr(MachineInstr *MI, 1090 MachineBasicBlock *BB) const; 1091 1092 MachineBasicBlock *emitEHSjLjSetJmp(MachineInstr *MI, 1093 MachineBasicBlock *MBB) const; 1094 1095 MachineBasicBlock *emitEHSjLjLongJmp(MachineInstr *MI, 1096 MachineBasicBlock *MBB) const; 1097 1098 MachineBasicBlock *emitFMA3Instr(MachineInstr *MI, 1099 MachineBasicBlock *MBB) const; 1100 1101 /// Emit nodes that will be selected as "test Op0,Op0", or something 1102 /// equivalent, for use with the given x86 condition code. 1103 SDValue EmitTest(SDValue Op0, unsigned X86CC, SDLoc dl, 1104 SelectionDAG &DAG) const; 1105 1106 /// Emit nodes that will be selected as "cmp Op0,Op1", or something 1107 /// equivalent, for use with the given x86 condition code. 1108 SDValue EmitCmp(SDValue Op0, SDValue Op1, unsigned X86CC, SDLoc dl, 1109 SelectionDAG &DAG) const; 1110 1111 /// Convert a comparison if required by the subtarget. 1112 SDValue ConvertCmpIfNecessary(SDValue Cmp, SelectionDAG &DAG) const; 1113 1114 /// Use rsqrt* to speed up sqrt calculations. 1115 SDValue getRsqrtEstimate(SDValue Operand, DAGCombinerInfo &DCI, 1116 unsigned &RefinementSteps, 1117 bool &UseOneConstNR) const override; 1118 1119 /// Use rcp* to speed up fdiv calculations. 1120 SDValue getRecipEstimate(SDValue Operand, DAGCombinerInfo &DCI, 1121 unsigned &RefinementSteps) const override; 1122 1123 /// Reassociate floating point divisions into multiply by reciprocal. 1124 bool combineRepeatedFPDivisors(unsigned NumUsers) const override; 1125 }; 1126 1127 namespace X86 { 1128 FastISel *createFastISel(FunctionLoweringInfo &funcInfo, 1129 const TargetLibraryInfo *libInfo); 1130 } 1131 } 1132 1133 #endif // X86ISELLOWERING_H 1134