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Searched refs:VT2 (Results 1 – 21 of 21) sorted by relevance

/NextBSD/contrib/llvm/include/llvm/CodeGen/
HDSelectionDAG.h421 SDVTList getVTList(EVT VT1, EVT VT2);
422 SDVTList getVTList(EVT VT1, EVT VT2, EVT VT3);
423 SDVTList getVTList(EVT VT1, EVT VT2, EVT VT3, EVT VT4);
932 SDNode *SelectNodeTo(SDNode *N, unsigned TargetOpc, EVT VT1, EVT VT2);
934 EVT VT2, ArrayRef<SDValue> Ops);
936 EVT VT2, EVT VT3, ArrayRef<SDValue> Ops);
938 EVT VT2, EVT VT3, EVT VT4, ArrayRef<SDValue> Ops);
940 EVT VT2, SDValue Op1);
942 EVT VT2, SDValue Op1, SDValue Op2);
944 EVT VT2, SDValue Op1, SDValue Op2, SDValue Op3);
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/NextBSD/contrib/llvm/lib/Target/MSP430/
HDMSP430ISelLowering.h110 bool isTruncateFree(EVT VT1, EVT VT2) const override;
121 bool isZExtFree(EVT VT1, EVT VT2) const override;
122 bool isZExtFree(SDValue Val, EVT VT2) const override;
HDMSP430ISelLowering.cpp1170 bool MSP430TargetLowering::isTruncateFree(EVT VT1, EVT VT2) const { in isTruncateFree()
1171 if (!VT1.isInteger() || !VT2.isInteger()) in isTruncateFree()
1174 return (VT1.getSizeInBits() > VT2.getSizeInBits()); in isTruncateFree()
1182 bool MSP430TargetLowering::isZExtFree(EVT VT1, EVT VT2) const { in isZExtFree()
1184 return 0 && VT1 == MVT::i8 && VT2 == MVT::i16; in isZExtFree()
1187 bool MSP430TargetLowering::isZExtFree(SDValue Val, EVT VT2) const { in isZExtFree()
1188 return isZExtFree(Val.getValueType(), VT2); in isZExtFree()
/NextBSD/contrib/llvm/include/llvm/IR/
HDLegacyPassNameParser.h91 const PassNameParser::OptionInfo *VT2) { in ValLessThan() argument
92 return std::strcmp(VT1->Name, VT2->Name); in ValLessThan()
/NextBSD/contrib/llvm/lib/CodeGen/SelectionDAG/
HDSelectionDAG.cpp1874 SDValue SelectionDAG::CreateStackTemporary(EVT VT1, EVT VT2) { in CreateStackTemporary() argument
1876 VT2.getStoreSizeInBits())/8; in CreateStackTemporary()
1878 Type *Ty2 = VT2.getTypeForEVT(*getContext()); in CreateStackTemporary()
5494 SDVTList SelectionDAG::getVTList(EVT VT1, EVT VT2) { in getVTList() argument
5498 ID.AddInteger(VT2.getRawBits()); in getVTList()
5505 Array[1] = VT2; in getVTList()
5512 SDVTList SelectionDAG::getVTList(EVT VT1, EVT VT2, EVT VT3) { in getVTList() argument
5516 ID.AddInteger(VT2.getRawBits()); in getVTList()
5524 Array[1] = VT2; in getVTList()
5532 SDVTList SelectionDAG::getVTList(EVT VT1, EVT VT2, EVT VT3, EVT VT4) { in getVTList() argument
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/NextBSD/contrib/llvm/lib/Target/X86/
HDX86ISelLowering.h786 bool isTruncateFree(EVT VT1, EVT VT2) const override;
799 bool isZExtFree(EVT VT1, EVT VT2) const override;
800 bool isZExtFree(SDValue Val, EVT VT2) const override;
814 bool isNarrowingProfitable(EVT VT1, EVT VT2) const override;
HDX86ISelLowering.cpp19175 bool X86TargetLowering::isTruncateFree(EVT VT1, EVT VT2) const { in isTruncateFree()
19176 if (!VT1.isInteger() || !VT2.isInteger()) in isTruncateFree()
19179 unsigned NumBits2 = VT2.getSizeInBits(); in isTruncateFree()
19188 bool X86TargetLowering::isZExtFree(EVT VT1, EVT VT2) const { in isZExtFree()
19190 return VT1 == MVT::i32 && VT2 == MVT::i64 && Subtarget->is64Bit(); in isZExtFree()
19193 bool X86TargetLowering::isZExtFree(SDValue Val, EVT VT2) const { in isZExtFree()
19195 if (isZExtFree(VT1, VT2)) in isZExtFree()
19202 !VT2.isSimple() || !VT2.isInteger()) in isZExtFree()
19240 bool X86TargetLowering::isNarrowingProfitable(EVT VT1, EVT VT2) const { in isNarrowingProfitable()
19242 return !(VT1 == MVT::i32 && VT2 == MVT::i16); in isNarrowingProfitable()
/NextBSD/contrib/llvm/lib/Target/AArch64/
HDAArch64ISelLowering.h297 bool isTruncateFree(EVT VT1, EVT VT2) const override;
302 bool isZExtFree(EVT VT1, EVT VT2) const override;
303 bool isZExtFree(SDValue Val, EVT VT2) const override;
HDAArch64ISelLowering.cpp6556 bool AArch64TargetLowering::isTruncateFree(EVT VT1, EVT VT2) const { in isTruncateFree()
6557 if (VT1.isVector() || VT2.isVector() || !VT1.isInteger() || !VT2.isInteger()) in isTruncateFree()
6560 unsigned NumBits2 = VT2.getSizeInBits(); in isTruncateFree()
6602 bool AArch64TargetLowering::isZExtFree(EVT VT1, EVT VT2) const { in isZExtFree()
6603 if (VT1.isVector() || VT2.isVector() || !VT1.isInteger() || !VT2.isInteger()) in isZExtFree()
6606 unsigned NumBits2 = VT2.getSizeInBits(); in isZExtFree()
6610 bool AArch64TargetLowering::isZExtFree(SDValue Val, EVT VT2) const { in isZExtFree()
6612 if (isZExtFree(VT1, VT2)) { in isZExtFree()
6621 VT2.isSimple() && !VT2.isVector() && VT2.isInteger() && in isZExtFree()
/NextBSD/contrib/llvm/lib/Target/AMDGPU/
HDAMDGPUISelLowering.h123 bool isZExtFree(SDValue Val, EVT VT2) const override;
125 bool isNarrowingProfitable(EVT VT1, EVT VT2) const override;
HDAMDGPUISelLowering.cpp563 bool AMDGPUTargetLowering::isZExtFree(SDValue Val, EVT VT2) const { in isZExtFree()
564 return isZExtFree(Val.getValueType(), VT2); in isZExtFree()
/NextBSD/contrib/llvm/lib/Target/XCore/
HDXCoreISelLowering.h100 bool isZExtFree(SDValue Val, EVT VT2) const override;
HDXCoreISelLowering.cpp190 bool XCoreTargetLowering::isZExtFree(SDValue Val, EVT VT2) const { in isZExtFree()
196 !VT2.isSimple() || !VT2.isInteger()) in isZExtFree()
/NextBSD/contrib/llvm/lib/Target/PowerPC/
HDPPCISelLowering.h586 bool isTruncateFree(EVT VT1, EVT VT2) const override;
588 bool isZExtFree(SDValue Val, EVT VT2) const override;
HDPPCISelLowering.cpp11374 bool PPCTargetLowering::isTruncateFree(EVT VT1, EVT VT2) const { in isTruncateFree()
11375 if (!VT1.isInteger() || !VT2.isInteger()) in isTruncateFree()
11378 unsigned NumBits2 = VT2.getSizeInBits(); in isTruncateFree()
11382 bool PPCTargetLowering::isZExtFree(SDValue Val, EVT VT2) const { in isZExtFree()
11399 return TargetLowering::isZExtFree(Val, VT2); in isZExtFree()
/NextBSD/contrib/llvm/lib/Target/Hexagon/
HDHexagonISelLowering.h116 bool isTruncateFree(EVT VT1, EVT VT2) const override;
HDHexagonISelLowering.cpp1780 bool HexagonTargetLowering::isTruncateFree(EVT VT1, EVT VT2) const { in isTruncateFree()
1781 if (!VT1.isSimple() || !VT2.isSimple()) in isTruncateFree()
1783 return (VT1.getSimpleVT() == MVT::i64) && (VT2.getSimpleVT() == MVT::i32); in isTruncateFree()
/NextBSD/contrib/llvm/include/llvm/Target/
HDTargetLowering.h794 MVT VT2; in getNumRegisters() local
796 return getVectorTypeBreakdown(Context, VT, VT1, NumIntermediates, VT2); in getNumRegisters()
1635 virtual bool isZExtFree(SDValue Val, EVT VT2) const { in isZExtFree() argument
1636 return isZExtFree(Val.getValueType(), VT2); in isZExtFree()
/NextBSD/contrib/llvm/lib/Target/ARM/
HDARMISelLowering.h281 bool isZExtFree(SDValue Val, EVT VT2) const override;
HDARMISelLowering.cpp10234 bool ARMTargetLowering::isZExtFree(SDValue Val, EVT VT2) const { in isZExtFree()
10240 !VT2.isSimple() || !VT2.isInteger()) in isZExtFree()
/NextBSD/contrib/llvm/lib/Transforms/Vectorize/
HDBBVectorize.cpp1035 *VT2 = getVecTypeForPair(IT2, JT2); in areInstsCompatible() local
1078 unsigned VCost = getInstrCost(I->getOpcode(), VT1, VT2, Op1VK, Op2VK); in areInstsCompatible()
1087 VParts2 = TTI->getNumberOfParts(VT2); in areInstsCompatible()