| /NextBSD/contrib/llvm/lib/Target/ARM/MCTargetDesc/ |
| HD | ARMUnwindOpAsm.cpp | 76 uint32_t Range = countTrailingOnes(Mask >> 5); // Exclude r4. in EmitRegSave()
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| /NextBSD/contrib/llvm/lib/Target/AArch64/MCTargetDesc/ |
| HD | AArch64AddressingModes.h | 240 CTO = countTrailingOnes(Imm >> I); in processLogicalImmediate()
248 CTO = CLO + countTrailingOnes(Imm) - (64 - Size); in processLogicalImmediate()
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| /NextBSD/contrib/llvm/lib/Target/Hexagon/ |
| HD | HexagonGenExtract.cpp | 168 uint32_t T = M.countTrailingOnes(); in INITIALIZE_PASS_DEPENDENCY()
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| /NextBSD/contrib/llvm/lib/Target/X86/ |
| HD | X86FloatingPoint.cpp | 946 unsigned N = countTrailingOnes(STReturns); in handleCall()
1423 unsigned NumSTUses = countTrailingOnes(STUses); in handleSpecialFP()
1430 unsigned NumSTDefs = countTrailingOnes(STDefs); in handleSpecialFP()
1440 unsigned NumSTPopped = countTrailingOnes(STPopped); in handleSpecialFP()
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| HD | X86InstrCompiler.td | 1513 return countTrailingOnes<uint64_t>(Imm) >= 5;
1516 return countTrailingOnes<uint64_t>(Imm) >= 6;
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| HD | X86ISelDAGToDAG.cpp | 941 if (countTrailingOnes(Mask >> MaskTZ) + MaskTZ + MaskLZ != 64) return true; in FoldMaskAndShiftToScale()
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| HD | X86InstrInfo.td | 2233 return getI8Imm(countTrailingOnes(N->getZExtValue()), SDLoc(N));
2237 return isMask_64(Imm) && (countTrailingOnes<uint64_t>(Imm) > 32);
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| /NextBSD/contrib/llvm/include/llvm/ADT/ |
| HD | APInt.h | 1403 unsigned countTrailingOnes() const { in countTrailingOnes() function
1405 return llvm::countTrailingOnes(VAL); in countTrailingOnes()
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| /NextBSD/contrib/llvm/lib/Transforms/Scalar/ |
| HD | AlignmentFromAssumptions.cpp | 253 MaskSCEV->getValue()->getValue().countTrailingOnes(); in extractAlignmentInfo()
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| /NextBSD/contrib/llvm/include/llvm/Support/ |
| HD | MathExtras.h | 407 std::size_t countTrailingOnes(T Value, ZeroBehavior ZB = ZB_Width) {
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| /NextBSD/contrib/llvm/lib/Analysis/ |
| HD | ValueTracking.cpp | 327 unsigned TrailZ = KnownZero.countTrailingOnes() + in computeKnownBitsMul()
328 KnownZero2.countTrailingOnes(); in computeKnownBitsMul()
1215 unsigned TrailZ = LocalKnownZero.countTrailingOnes(); in computeKnownBitsFromOperator()
1250 LocalKnownZero.countTrailingOnes())); in computeKnownBitsFromOperator()
1296 std::min(KnownZero2.countTrailingOnes(), in computeKnownBitsFromOperator()
1297 KnownZero3.countTrailingOnes())); in computeKnownBitsFromOperator()
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| HD | ScalarEvolution.cpp | 3839 return Zeros.countTrailingOnes(); in GetMinTrailingZeros()
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| /NextBSD/contrib/llvm/lib/CodeGen/SelectionDAG/ |
| HD | SelectionDAG.cpp | 125 if (CN->getAPIntValue().countTrailingOnes() < EltSize) in isBuildVectorAllOnes()
128 if (CFPN->getValueAPF().bitcastToAPInt().countTrailingOnes() < EltSize) in isBuildVectorAllOnes()
2075 unsigned TrailZ = KnownZero.countTrailingOnes() + in computeKnownBits()
2076 KnownZero2.countTrailingOnes(); in computeKnownBits()
2364 unsigned KnownZeroLow = KnownZero2.countTrailingOnes(); in computeKnownBits()
2370 KnownZero2.countTrailingOnes()); in computeKnownBits()
6911 unsigned AlignBits = KnownZero.countTrailingOnes(); in InferPtrAlignment()
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| HD | TargetLowering.cpp | 1340 MinBits = C->getAPIntValue().countTrailingOnes(); in SimplifySetCC()
1759 ShiftBits = C1.countTrailingOnes(); in SimplifySetCC()
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| HD | SelectionDAGBuilder.cpp | 1926 ShiftOp, DAG.getConstant(countTrailingOnes(B.Mask), dl, VT), in visitBitTestCase()
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| HD | DAGCombiner.cpp | 10269 if (countTrailingOnes(NotMask >> NotMaskTZ) + NotMaskTZ + NotMaskLZ != 64) in CheckForMaskedLoad()
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| /NextBSD/contrib/llvm/lib/Transforms/Utils/ |
| HD | Local.cpp | 943 unsigned TrailZ = KnownZero.countTrailingOnes(); in getOrEnforceKnownAlignment()
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| /NextBSD/contrib/llvm/lib/Target/AArch64/ |
| HD | AArch64ISelDAGToDAG.cpp | 1437 MSB = Srl_imm + (VT == MVT::i32 ? countTrailingOnes<uint32_t>(And_imm) in isBitfieldExtractOpFromAnd()
1438 : countTrailingOnes<uint64_t>(And_imm)) - in isBitfieldExtractOpFromAnd()
1886 MaskWidth = countTrailingOnes(NonZeroBits >> ShiftAmount); in isBitfieldPositioningOp()
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| /NextBSD/contrib/llvm/lib/Target/NVPTX/ |
| HD | NVPTXISelDAGToDAG.cpp | 4767 uint64_t NumBits = countTrailingOnes(MaskVal); in SelectBFE()
4831 NumBits = countTrailingOnes(MaskVal) - ShiftAmt; in SelectBFE()
4834 unsigned NumOnes = countTrailingOnes(MaskVal >> NumZeros); in SelectBFE()
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| /NextBSD/contrib/llvm/lib/Support/ |
| HD | APInt.cpp | 767 Count += llvm::countTrailingOnes(pVal[i]); in countTrailingOnesSlowCase()
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| /NextBSD/contrib/llvm/lib/Target/XCore/ |
| HD | XCoreISelLowering.cpp | 424 return KnownZero.countTrailingOnes() >= 2; in isWordAligned()
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| /NextBSD/contrib/llvm/lib/Target/PowerPC/ |
| HD | PPCISelDAGToDAG.cpp | 2549 MB = 64 - countTrailingOnes(Imm64); in Select()
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| /NextBSD/contrib/llvm/lib/Transforms/InstCombine/ |
| HD | InstCombineCompares.cpp | 2455 unsigned trailingOnes = RHS.countTrailingOnes(); in DemandedBitsLHSMask()
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| /NextBSD/contrib/llvm/lib/Target/ARM/ |
| HD | ARMISelDAGToDAG.cpp | 2343 unsigned Width = countTrailingOnes(And_imm) - 1; in SelectV6T2BitfieldExtractOp()
|