Home
last modified time | relevance | path

Searched refs:getSizeInBits (Results 1 – 25 of 80) sorted by relevance

1234

/NextBSD/contrib/llvm/include/llvm/CodeGen/
HDValueTypes.h84 unsigned BitWidth = EltTy.getSizeInBits(); in changeVectorElementTypeToInteger()
161 return (getSizeInBits() & 7) == 0; in isByteSized()
166 unsigned BitSize = getSizeInBits(); in isRound()
173 return getSizeInBits() == VT.getSizeInBits(); in bitsEq()
179 return getSizeInBits() > VT.getSizeInBits(); in bitsGT()
185 return getSizeInBits() >= VT.getSizeInBits(); in bitsGE()
191 return getSizeInBits() < VT.getSizeInBits(); in bitsLT()
197 return getSizeInBits() <= VT.getSizeInBits(); in bitsLE()
233 unsigned getSizeInBits() const { in getSizeInBits() function
235 return V.getSizeInBits(); in getSizeInBits()
[all …]
HDMachineValueType.h379 unsigned getSizeInBits() const { in getSizeInBits() function
454 return getScalarType().getSizeInBits(); in getScalarSizeInBits()
460 return (getSizeInBits() + 7) / 8; in getStoreSize()
471 return getSizeInBits() > VT.getSizeInBits(); in bitsGT()
476 return getSizeInBits() >= VT.getSizeInBits(); in bitsGE()
481 return getSizeInBits() < VT.getSizeInBits(); in bitsLT()
486 return getSizeInBits() <= VT.getSizeInBits(); in bitsLE()
HDBasicTTIImpl.h351 SrcLT.second.getSizeInBits() == DstLT.second.getSizeInBits()) { in getCastInstrCost()
392 SrcLT.second.getSizeInBits() == DstLT.second.getSizeInBits()) { in getCastInstrCost()
494 Src->getPrimitiveSizeInBits() < LT.second.getSizeInBits()) { in getMemoryOpCost()
/NextBSD/contrib/llvm/lib/Target/X86/Utils/
HDX86ShuffleDecode.cpp83 unsigned VectorSizeInBits = VT.getSizeInBits(); in DecodeMOVDDUPMask()
97 unsigned VectorSizeInBits = VT.getSizeInBits(); in DecodePSLLDQMask()
111 unsigned VectorSizeInBits = VT.getSizeInBits(); in DecodePSRLDQMask()
128 unsigned Offset = Imm * (VT.getVectorElementType().getSizeInBits() / 8); in DecodePALIGNRMask()
130 unsigned NumLanes = VT.getSizeInBits() / 128; in DecodePALIGNRMask()
149 unsigned NumLanes = VT.getSizeInBits() / 128; in DecodePSHUFMask()
200 unsigned NumLanes = VT.getSizeInBits() / 128; in DecodeSHUFPMask()
224 unsigned NumLanes = VT.getSizeInBits() / 128; in DecodeUNPCKHMask()
244 unsigned NumLanes = VT.getSizeInBits() / 128; in DecodeUNPCKLMask()
/NextBSD/contrib/llvm/lib/CodeGen/SelectionDAG/
HDLegalizeVectorOps.cpp555 unsigned SrcEltBits = SrcEltVT.getSizeInBits(); in ExpandLoad()
560 unsigned WideBits = WideVT.getSizeInBits(); in ExpandLoad()
608 unsigned Stride = SrcVT.getScalarType().getSizeInBits()/8; in ExpandLoad()
657 unsigned ScalarSize = MemSclVT.getSizeInBits(); in ExpandStore()
750 DAG.getConstant(APInt::getAllOnesValue(BitTy.getSizeInBits()), DL, in ExpandSELECT()
765 APInt::getAllOnesValue(BitTy.getSizeInBits()), DL, MaskTy); in ExpandSELECT()
785 unsigned BW = VT.getScalarType().getSizeInBits(); in ExpandSEXTINREG()
786 unsigned OrigBW = OrigTy.getScalarType().getSizeInBits(); in ExpandSEXTINREG()
832 unsigned EltWidth = VT.getVectorElementType().getSizeInBits(); in ExpandSIGN_EXTEND_VECTOR_INREG()
833 unsigned SrcEltWidth = SrcVT.getVectorElementType().getSizeInBits(); in ExpandSIGN_EXTEND_VECTOR_INREG()
[all …]
HDLegalizeTypes.cpp779 assert(Result.getValueType().getSizeInBits() >= in SetScalarizedVector()
780 Op.getValueType().getVectorElementType().getSizeInBits() && in SetScalarizedVector()
890 unsigned BitWidth = Op.getValueType().getSizeInBits(); in BitConvertToInteger()
899 unsigned EltWidth = Op.getValueType().getVectorElementType().getSizeInBits(); in BitConvertVectorToIntegerVector()
1012 unsigned EltSize = EltVT.getSizeInBits() / 8; // FIXME: should be ABI size. in GetVectorElementPointer()
1013 assert(EltSize * 8 == EltVT.getSizeInBits() && in GetVectorElementPointer()
1029 LVT.getSizeInBits() + HVT.getSizeInBits()); in JoinIntegers()
1034 DAG.getConstant(LVT.getSizeInBits(), dlHi, in JoinIntegers()
1117 assert(LoVT.getSizeInBits() + HiVT.getSizeInBits() == in SplitInteger()
1118 Op.getValueType().getSizeInBits() && "Invalid integer splitting!"); in SplitInteger()
[all …]
HDTargetLowering.cpp383 assert(Op.getValueType().getScalarType().getSizeInBits() == BitWidth && in SimplifyDemandedBits()
647 unsigned InnerBits = InnerVT.getSizeInBits(); in SimplifyDemandedBits()
651 if (!APInt(BitWidth, ShAmt).isIntN(ShTy.getSizeInBits())) in SimplifyDemandedBits()
698 unsigned VTSize = VT.getSizeInBits(); in SimplifyDemandedBits()
774 InDemandedMask |= APInt::getSignBit(VT.getScalarType().getSizeInBits()); in SimplifyDemandedBits()
817 unsigned ShAmt = ExVT.getScalarType().getSizeInBits(); in SimplifyDemandedBits()
819 unsigned VTBits = Op->getValueType(0).getScalarType().getSizeInBits(); in SimplifyDemandedBits()
843 BitWidth - ExVT.getScalarType().getSizeInBits()); in SimplifyDemandedBits()
850 APInt::getSignBit(ExVT.getScalarType().getSizeInBits()).zext(BitWidth); in SimplifyDemandedBits()
853 ExVT.getScalarType().getSizeInBits()) & in SimplifyDemandedBits()
[all …]
HDLegalizeVectorTypes.cpp765 EVT LoIntVT = EVT::getIntegerVT(*DAG.getContext(), LoVT.getSizeInBits()); in SplitVecRes_BITCAST()
766 EVT HiIntVT = EVT::getIntegerVT(*DAG.getContext(), HiVT.getSizeInBits()); in SplitVecRes_BITCAST()
855 unsigned IncrementSize = Lo.getValueType().getSizeInBits() / 8; in SplitVecRes_INSERT_SUBVECTOR()
935 unsigned IncrementSize = Lo.getValueType().getSizeInBits() / 8; in SplitVecRes_INSERT_VECTOR_ELT()
979 unsigned IncrementSize = LoMemVT.getSizeInBits()/8; in SplitVecRes_LOAD()
1012 (Alignment == MLD->getValueType(0).getSizeInBits()/8) ? in SplitVecRes_MLOAD()
1034 unsigned IncrementSize = LoMemVT.getSizeInBits()/8; in SplitVecRes_MLOAD()
1183 SrcVT.getSizeInBits() * 2 < DestVT.getSizeInBits()) { in SplitVecRes_ExtendOp()
1187 Ctx, SrcVT.getVectorElementType().getSizeInBits() * 2), in SplitVecRes_ExtendOp()
1534 if (EltVT.getSizeInBits() < 8) { in SplitVecOp_EXTRACT_VECTOR_ELT()
[all …]
HDLegalizeIntegerTypes.cpp290 NOutVT.getSizeInBits()), in PromoteIntRes_BITCAST()
751 DAG.getIntPtrConstant(SmallVT.getSizeInBits(), in PromoteIntRes_XMULO()
814 DAG.getConstant(i * RegVT.getSizeInBits(), dl, in PromoteIntRes_VAARG()
1008 DAG.getConstant(OVT.getSizeInBits(), dl, in PromoteIntOp_BUILD_PAIR()
1025 assert(N->getOperand(0).getValueType().getSizeInBits() >= in PromoteIntOp_BUILD_VECTOR()
1026 N->getValueType(0).getVectorElementType().getSizeInBits() && in PromoteIntOp_BUILD_VECTOR()
1055 assert(N->getOperand(1).getValueType().getSizeInBits() >= in PromoteIntOp_INSERT_VECTOR_ELT()
1056 N->getValueType(0).getVectorElementType().getSizeInBits() && in PromoteIntOp_INSERT_VECTOR_ELT()
1379 unsigned VTBits = N->getValueType(0).getSizeInBits(); in ExpandShiftByConstant()
1380 unsigned NVTBits = NVT.getSizeInBits(); in ExpandShiftByConstant()
[all …]
HDLegalizeDAG.cpp306 EVT intVT = EVT::getIntegerVT(*DAG.getContext(), VT.getSizeInBits()); in ExpandUnalignedStore()
323 StoredVT.getSizeInBits())); in ExpandUnalignedStore()
324 unsigned StoredBytes = StoredVT.getSizeInBits() / 8; in ExpandUnalignedStore()
325 unsigned RegBytes = RegVT.getSizeInBits() / 8; in ExpandUnalignedStore()
386 int NumBits = NewStoredVT.getSizeInBits(); in ExpandUnalignedStore()
430 EVT intVT = EVT::getIntegerVT(*DAG.getContext(), LoadedVT.getSizeInBits()); in ExpandUnalignedLoad()
449 unsigned LoadedBytes = LoadedVT.getSizeInBits() / 8; in ExpandUnalignedLoad()
450 unsigned RegBytes = RegVT.getSizeInBits() / 8; in ExpandUnalignedLoad()
516 unsigned NumBits = LoadedVT.getSizeInBits(); in ExpandUnalignedLoad()
605 unsigned EltSize = EltVT.getSizeInBits()/8; in PerformInsertVectorEltInMemory()
[all …]
HDDAGCombiner.cpp180 unsigned BitWidth = Op.getValueType().getScalarType().getSizeInBits(); in SimplifyDemandedBits()
728 EltVT.getSizeInBits() >= SplatBitSize); in isConstantSplatVector()
1758 unsigned DestBits = VT.getScalarType().getSizeInBits(); in visitADD()
2064 ConstValue1.getBitWidth() == VT.getScalarType().getSizeInBits(); in visitMUL()
2373 DAG.getConstant(APInt::getAllOnesValue(VT.getSizeInBits()), DL, in visitUREM()
2419 DAG.getConstant(N0.getValueType().getSizeInBits() - 1, in visitMULHS()
2431 unsigned SimpleSize = Simple.getSizeInBits(); in visitMULHS()
2467 unsigned SimpleSize = Simple.getSizeInBits(); in visitMULHU()
2545 unsigned SimpleSize = Simple.getSizeInBits(); in visitSMUL_LOHI()
2576 unsigned SimpleSize = Simple.getSizeInBits(); in visitUMUL_LOHI()
[all …]
HDSelectionDAG.cpp123 unsigned EltSize = N->getValueType(0).getVectorElementType().getSizeInBits(); in isBuildVectorAllOnes()
166 unsigned EltSize = N->getValueType(0).getVectorElementType().getSizeInBits(); in isBuildVectorAllZeros()
738 assert(VT.getSizeInBits() == 2 * N->getOperand(0).getValueSizeInBits() && in VerifySDNode()
1063 unsigned BitWidth = Op.getValueType().getScalarType().getSizeInBits(); in getZeroExtendInReg()
1065 VT.getSizeInBits()); in getZeroExtendInReg()
1072 assert(VT.getSizeInBits() == Op.getValueType().getSizeInBits() && in getAnyExtendVectorInReg()
1082 assert(VT.getSizeInBits() == Op.getValueType().getSizeInBits() && in getSignExtendVectorInReg()
1092 assert(VT.getSizeInBits() == Op.getValueType().getSizeInBits() && in getZeroExtendVectorInReg()
1105 getConstant(APInt::getAllOnesValue(EltVT.getSizeInBits()), DL, VT); in getNOT()
1118 TrueValue = getConstant(APInt::getAllOnesValue(EltVT.getSizeInBits()), DL, in getLogicalNOT()
[all …]
HDLegalizeTypesGeneric.cpp110 unsigned NewSizeInBits = ElemVT.getSizeInBits() / 2; in ExpandRes_BITCAST()
142 LHS.getValueType().getSizeInBits() << 1), in ExpandRes_BITCAST()
175 unsigned IncrementSize = NOutVT.getSizeInBits() / 8; in ExpandRes_BITCAST()
272 unsigned IncrementSize = NVT.getSizeInBits() / 8; in ExpandRes_NormalLoad()
480 unsigned IncrementSize = NVT.getSizeInBits() / 8; in ExpandOp_NormalStore()
HDLegalizeFloatTypes.cpp148 unsigned Size = NVT.getSizeInBits(); in SoftenFloatRes_FABS()
217 unsigned LSize = LVT.getSizeInBits(); in SoftenFloatRes_FCOPYSIGN()
218 unsigned RSize = RVT.getSizeInBits(); in SoftenFloatRes_FCOPYSIGN()
228 int SizeDiff = RVT.getSizeInBits() - LVT.getSizeInBits(); in SoftenFloatRes_FCOPYSIGN()
934 assert(NVT.getSizeInBits() == integerPartWidth && in ExpandFloatRes_ConstantFP()
1150 APInt(NVT.getSizeInBits(), 0)), dl, NVT); in ExpandFloatRes_FP_EXTEND()
1274 APInt(NVT.getSizeInBits(), 0)), dl, NVT); in ExpandFloatRes_LOAD()
1299 APInt(NVT.getSizeInBits(), 0)), dl, NVT); in ExpandFloatRes_XINT_TO_FP()
1639 EVT IVT = EVT::getIntegerVT(*DAG.getContext(), OpVT.getSizeInBits()); in PromoteFloatOp_BITCAST()
1712 EVT IVT = EVT::getIntegerVT(*DAG.getContext(), VT.getSizeInBits()); in PromoteFloatOp_STORE()
[all …]
/NextBSD/contrib/llvm/lib/Target/AArch64/
HDAArch64ISelLowering.cpp741 unsigned MemBits = VT.getScalarType().getSizeInBits(); in computeKnownBitsForTargetNode()
1585 if (VT.getSizeInBits() < InVT.getSizeInBits()) { in LowerVectorFP_TO_INT()
1593 if (VT.getSizeInBits() > InVT.getSizeInBits()) { in LowerVectorFP_TO_INT()
1644 if (VT.getSizeInBits() < InVT.getSizeInBits()) { in LowerVectorINT_TO_FP()
1652 if (VT.getSizeInBits() > InVT.getSizeInBits()) { in LowerVectorINT_TO_FP()
1743 if (OrigVT.getSizeInBits() >= 64) in getExtensionTo64Bits()
1767 if (OrigTy.getSizeInBits() >= 64) in addRequiredExtensionForVectorMULL()
1785 unsigned EltSize = VT.getVectorElementType().getSizeInBits(); in isExtendedBUILD_VECTOR()
1812 unsigned EltSize = VT.getVectorElementType().getSizeInBits() / 2; in skipExtensionForVectorMULL()
2183 unsigned ArgSize = VA.getValVT().getSizeInBits() / 8; in LowerFormalArguments()
[all …]
HDAArch64ISelDAGToDAG.cpp337 unsigned BitSize = N.getValueType().getSizeInBits(); in SelectShiftedRegister()
1133 bool Is128Bit = VT.getSizeInBits() == 128; in SelectStore()
1151 bool Is128Bit = VT.getSizeInBits() == 128; in SelectPostStore()
1203 bool Narrow = VT.getSizeInBits() == 64; in SelectLoadLane()
1243 bool Narrow = VT.getSizeInBits() == 64; in SelectPostLoadLane()
1299 bool Narrow = VT.getSizeInBits() == 64; in SelectStoreLane()
1329 bool Narrow = VT.getSizeInBits() == 64; in SelectPostStoreLane()
1430 if (!BiggerPattern && (Srl_imm <= 0 || Srl_imm >= VT.getSizeInBits())) { in isBitfieldExtractOpFromAnd()
1527 Trunc_bits = Opd0->getValueType(0).getSizeInBits() - VT.getSizeInBits(); in isBitfieldExtractOpFromShr()
1540 if (Shl_imm >= VT.getSizeInBits()) { in isBitfieldExtractOpFromShr()
[all …]
/NextBSD/contrib/llvm/lib/Target/SystemZ/
HDSystemZISelDAGToDAG.cpp119 : Opcode(Op), BitSize(N.getValueType().getSizeInBits()), in RxSBGOperands()
707 uint64_t Used = allOnes(Op.getValueType().getSizeInBits()); in detectOrAndInsertion()
813 unsigned InnerBitSize = N.getOperand(0).getValueType().getSizeInBits(); in expandRxSBG()
825 unsigned InnerBitSize = N.getOperand(0).getValueType().getSizeInBits(); in expandRxSBG()
839 unsigned BitSize = N.getValueType().getSizeInBits(); in expandRxSBG()
866 unsigned BitSize = N.getValueType().getSizeInBits(); in expandRxSBG()
909 if (!VT.isInteger() || VT.getSizeInBits() > 64) in tryRISBGZero()
968 if (!VT.isInteger() || VT.getSizeInBits() > 64) in tryRxSBG()
1045 if (Load->getMemoryVT().getSizeInBits() != in tryGather()
1046 Load->getValueType(0).getSizeInBits()) in tryGather()
[all …]
/NextBSD/contrib/llvm/lib/Target/Mips/
HDMipsSEISelDAGToDAG.cpp529 if (selectVSplat(N.getNode(), ImmValue, EltTy.getSizeInBits()) && in selectVSplatCommon()
530 ImmValue.getBitWidth() == EltTy.getSizeInBits()) { in selectVSplatCommon()
605 if (selectVSplat(N.getNode(), ImmValue, EltTy.getSizeInBits()) && in selectVSplatUimmPow2()
606 ImmValue.getBitWidth() == EltTy.getSizeInBits()) { in selectVSplatUimmPow2()
636 if (selectVSplat(N.getNode(), ImmValue, EltTy.getSizeInBits()) && in selectVSplatMaskL()
637 ImmValue.getBitWidth() == EltTy.getSizeInBits()) { in selectVSplatMaskL()
670 if (selectVSplat(N.getNode(), ImmValue, EltTy.getSizeInBits()) && in selectVSplatMaskR()
671 ImmValue.getBitWidth() == EltTy.getSizeInBits()) { in selectVSplatMaskR()
692 if (selectVSplat(N.getNode(), ImmValue, EltTy.getSizeInBits()) && in selectVSplatUimmInvPow2()
693 ImmValue.getBitWidth() == EltTy.getSizeInBits()) { in selectVSplatUimmInvPow2()
/NextBSD/contrib/llvm/lib/Target/NVPTX/
HDNVPTXISelLowering.cpp925 O << ".param .b" << PtrVT.getSizeInBits() << " _"; in getPrototype()
977 sz = PtrVT.getSizeInBits(); in getPrototype()
1118 if (elemtype.getSizeInBits() < 16) { in LowerCall()
1156 if (EltVT.getSizeInBits() < 16) { in LowerCall()
1206 if (EltVT.getSizeInBits() == 64) in LowerCall()
1276 unsigned sz = VT.getSizeInBits(); in LowerCall()
1351 if (elemtype.getSizeInBits() < 16) { in LowerCall()
1487 unsigned sz = EltVT.getSizeInBits(); in LowerCall()
1553 if (EltVT.getSizeInBits() == 64) { in LowerCall()
1604 unsigned sz = VTs[i].getSizeInBits(); in LowerCall()
[all …]
/NextBSD/contrib/llvm/lib/Target/X86/
HDX86ISelLowering.cpp1452 unsigned EltSize = VT.getVectorElementType().getSizeInBits(); in X86TargetLowering()
1458 if (EltSize >= 32 && VT.getSizeInBits() <= 512) { in X86TargetLowering()
1547 const unsigned EltSize = VT.getVectorElementType().getSizeInBits(); in X86TargetLowering()
2357 int FI = MFI->CreateFixedObject(ValVT.getSizeInBits()/8, in LowerMemArgument()
3110 uint32_t OpSize = (VA.getLocVT().getSizeInBits()+7)/8; in LowerCall()
3390 unsigned Bytes = Arg.getValueType().getSizeInBits() / 8; in MatchingStackOffset()
4018 unsigned ElSize = VT.getVectorElementType().getSizeInBits(); in isVEXTRACTIndex()
4036 unsigned ElSize = VT.getVectorElementType().getSizeInBits(); in isVINSERTIndex()
4069 unsigned NumElemsPerChunk = vecWidth / ElVT.getSizeInBits(); in getExtractVEXTRACTImmediate()
4084 unsigned NumElemsPerChunk = vecWidth / ElVT.getSizeInBits(); in getInsertVINSERTImmediate()
[all …]
/NextBSD/contrib/llvm/lib/Target/Hexagon/
HDHexagonISelLowering.cpp728 int ShiftAmount = VT.getSizeInBits() / 16; in getPostIndexedAddressParts()
1794 int EltBits = EltVT.getSizeInBits(); in shouldExpandBuildVectorWithShuffles()
1924 unsigned Size = VT.getSizeInBits(); in LowerBUILD_VECTOR()
2023 SDValue Width = DAG.getConstant(EltVT.getSizeInBits(), dl, MVT::i64); in LowerBUILD_VECTOR()
2036 if (VT.getSizeInBits() == 64 && in LowerBUILD_VECTOR()
2037 Operand.getValueType().getSizeInBits() == 32) { in LowerBUILD_VECTOR()
2047 if (VT.getSizeInBits() == 32) in LowerBUILD_VECTOR()
2065 SDValue Width = DAG.getConstant(VecVT.getSizeInBits(), dl, MVT::i64); in LowerCONCAT_VECTORS()
2095 if (VT.getSizeInBits() == 64 && in LowerCONCAT_VECTORS()
2096 Operand.getValueType().getSizeInBits() == 32) { in LowerCONCAT_VECTORS()
[all …]
/NextBSD/contrib/llvm/lib/Target/XCore/
HDXCoreSelectionDAGInfo.cpp26 unsigned SizeBitWidth = Size.getValueType().getSizeInBits(); in EmitTargetCodeForMemcpy()
/NextBSD/contrib/llvm/include/llvm/IR/
HDDataLayout.h483 uint64_t getSizeInBits() const { return 8 * StructSize; } in getSizeInBits() function
521 return getStructLayout(cast<StructType>(Ty))->getSizeInBits(); in getTypeSizeInBits()
/NextBSD/contrib/llvm/lib/CodeGen/
HDTargetLoweringBase.cpp942 unsigned BitSize = VT.getSizeInBits(); in getTypeConversion()
956 EVT::getIntegerVT(Context, VT.getSizeInBits() / 2)); in getTypeConversion()
996 EltVT = EVT::getIntegerVT(Context, 1 + EltVT.getSizeInBits()) in getTypeConversion()
1081 unsigned NewVTSize = NewVT.getSizeInBits(); in getVectorTypeBreakdownMVT()
1090 return NumVectorRegs*(NewVTSize/DestVT.getSizeInBits()); in getVectorTypeBreakdownMVT()
1312 if (SVT.getVectorElementType().getSizeInBits() > EltVT.getSizeInBits() in computeRegisterProperties()
1459 unsigned NewVTSize = NewVT.getSizeInBits(); in getVectorTypeBreakdown()
1466 return NumVectorRegs*(NewVTSize/DestVT.getSizeInBits()); in getVectorTypeBreakdown()
/NextBSD/contrib/llvm/lib/Target/PowerPC/
HDPPCTargetTransformInfo.cpp334 Src->getPrimitiveSizeInBits() >= LT.second.getSizeInBits() && in getMemoryOpCost()
335 LT.second.getSizeInBits() == 128 && in getMemoryOpCost()

1234