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Searched refs:iPTR (Results 1 – 25 of 36) sorted by relevance

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/NextBSD/contrib/llvm/lib/Target/X86/
HDX86InstrSSE.td333 def : Pat<(f32 (vector_extract (v4f32 VR128:$src), (iPTR 0))),
335 def : Pat<(f64 (vector_extract (v2f64 VR128:$src), (iPTR 0))),
340 def : Pat<(v4i32 (extract_subvector (v8i32 VR256:$src), (iPTR 0))),
342 def : Pat<(v4f32 (extract_subvector (v8f32 VR256:$src), (iPTR 0))),
345 def : Pat<(v2i64 (extract_subvector (v4i64 VR256:$src), (iPTR 0))),
347 def : Pat<(v2f64 (extract_subvector (v4f64 VR256:$src), (iPTR 0))),
350 def : Pat<(v8i16 (extract_subvector (v16i16 VR256:$src), (iPTR 0))),
352 def : Pat<(v16i8 (extract_subvector (v32i8 VR256:$src), (iPTR 0))),
358 def : Pat<(insert_subvector undef, (v2i64 VR128:$src), (iPTR 0)),
360 def : Pat<(insert_subvector undef, (v2f64 VR128:$src), (iPTR 0)),
[all …]
HDX86InstrAVX512.td487 (iPTR imm)))]>,
513 (AltTo.VT VR512:$src1), (AltFrom.VT From.RC:$src2), (iPTR imm)),
580 (iPTR imm)))]>,
592 def : Pat<(vextract_extract:$ext (AltFrom.VT VR512:$src1), (iPTR imm)),
599 def : Pat<(To.VT (extract_subvector (From.VT VR512:$src), (iPTR 0))),
604 def : Pat<(AltTo.VT (extract_subvector (AltFrom.VT VR512:$src), (iPTR 0))),
611 VR512:$src1, (iPTR imm:$idx), To.RC:$src0, GR8:$mask),
619 VR512:$src1, (iPTR imm:$idx), To.ImmAllZerosV, GR8:$mask),
627 VR512:$src1, (iPTR imm:$idx), To.ImmAllZerosV, (i8 -1)),
655 def : Pat<(insert_subvector undef, (v2i64 VR128X:$src), (iPTR 0)),
[all …]
HDX86InstrFragmentsSIMD.td493 (f32 (vector_extract (loadv4f32 node:$ptr), (iPTR 0)))>;
495 (f64 (vector_extract (loadv2f64 node:$ptr), (iPTR 0)))>;
593 (f32 (vector_extract (memopv4f32 node:$ptr), (iPTR 0)))>;
595 (f64 (vector_extract (memopv2f64 node:$ptr), (iPTR 0)))>;
HDX86InstrInfo.td83 def SDT_X86Call : SDTypeProfile<0, -1, [SDTCisVT<0, iPTR>]>;
86 SDTCisVT<1, iPTR>,
87 SDTCisVT<2, iPTR>]>;
107 def SDT_X86SEG_ALLOCA : SDTypeProfile<1, 1, [SDTCisVT<0, iPTR>, SDTCisVT<1, iPTR>]>;
297 AsmOperandClass parserMatchClass = X86MemAsmOperand> : Operand<iPTR> {
701 def addr : ComplexPattern<iPTR, 5, "SelectAddr", [], [SDNPWantParent]>;
727 def vectoraddr : ComplexPattern<iPTR, 5, "SelectVectorAddr", [],[SDNPWantParent]>;
/NextBSD/contrib/llvm/lib/Target/Sparc/
HDSparcInstr64Bit.td176 [(set iPTR:$dst, ADDRri:$addr)]>;
519 [(set i32:$rd, (op32 iPTR:$addr, i32:$rs2))]>;
524 [(set i64:$rd, (op64 iPTR:$addr, i64:$rs2))]>;
544 (atomic_swap_64 iPTR:$addr, i64:$rs2))]>;
570 def : Pat<(add iPTR:$r, (SPlo tglobaladdr:$in)), (ADDXri $r, tglobaladdr:$in)>;
571 def : Pat<(add iPTR:$r, (SPlo tconstpool:$in)), (ADDXri $r, tconstpool:$in)>;
572 def : Pat<(add iPTR:$r, (SPlo tblockaddress:$in)),
HDSparcInstrInfo.td82 def ADDRrr : ComplexPattern<iPTR, 2, "SelectADDRrr", [], []>;
83 def ADDRri : ComplexPattern<iPTR, 2, "SelectADDRri", [frameindex], []>;
96 def MEMrr : Operand<iPTR> {
101 def MEMri : Operand<iPTR> {
107 def TLSSym : Operand<iPTR>;
203 def getPCX : Operand<iPTR> {
517 [(set iPTR:$dst, ADDRri:$addr)]>;
1245 (atomic_cmp_swap iPTR:$rs1, i32:$rs2, i32:$swap))]>;
1290 def : Pat<(add iPTR:$r, (SPlo tglobaladdr:$in)), (ADDri $r, tglobaladdr:$in)>;
1291 def : Pat<(add iPTR:$r, (SPlo tconstpool:$in)), (ADDri $r, tconstpool:$in)>;
[all …]
/NextBSD/contrib/llvm/lib/Target/PowerPC/
HDPPCInstr64Bit.td39 def tocentry : Operand<iPTR> {
1078 def : Pat<(pre_truncsti8 i64:$rS, iPTR:$ptrreg, iaddroff:$ptroff),
1080 def : Pat<(pre_truncsti16 i64:$rS, iPTR:$ptrreg, iaddroff:$ptroff),
1082 def : Pat<(pre_truncsti32 i64:$rS, iPTR:$ptrreg, iaddroff:$ptroff),
1084 def : Pat<(aligned4pre_store i64:$rS, iPTR:$ptrreg, iaddroff:$ptroff),
1087 def : Pat<(pre_truncsti8 i64:$rS, iPTR:$ptrreg, iPTR:$ptroff),
1089 def : Pat<(pre_truncsti16 i64:$rS, iPTR:$ptrreg, iPTR:$ptroff),
1091 def : Pat<(pre_truncsti32 i64:$rS, iPTR:$ptrreg, iPTR:$ptroff),
1093 def : Pat<(pre_store i64:$rS, iPTR:$ptrreg, iPTR:$ptroff),
HDPPCInstrInfo.td53 def tocentry32 : Operand<iPTR> {
587 def calltarget : Operand<iPTR> {
592 def abscalltarget : Operand<iPTR> {
611 def ptr_rc_nor0 : Operand<iPTR>, PointerLikeRegClass<1> {
618 def ptr_rc_idx : Operand<iPTR>, PointerLikeRegClass<0> {
626 def dispRI : Operand<iPTR> {
633 def dispRIX : Operand<iPTR> {
640 def dispSPE8 : Operand<iPTR> {
647 def dispSPE4 : Operand<iPTR> {
654 def dispSPE2 : Operand<iPTR> {
[all …]
HDPPCInstrQPX.td980 def : Pat<(pre_store v4f64:$rS, iPTR:$ptrreg, iPTR:$ptroff),
982 def : Pat<(pre_store v4f32:$rS, iPTR:$ptrreg, iPTR:$ptroff),
984 def : Pat<(pre_truncstv4f32 v4f64:$rS, iPTR:$ptrreg, iPTR:$ptroff),
/NextBSD/contrib/llvm/utils/TableGen/
HDDAGISelMatcher.cpp370 if (T1 == MVT::iPTR) in TypesAreContradictory()
373 if (T2 == MVT::iPTR) in TypesAreContradictory()
HDCodeGenTarget.cpp45 case MVT::iPTR: return "TLI.getPointerTy()"; in getName()
116 case MVT::iPTR: return "MVT::iPTR"; in getEnumName()
HDCodeGenDAGPatterns.cpp55 assert((VT < MVT::LAST_VALUETYPE || VT == MVT::iPTR || in TypeSet()
179 case MVT::iPTR: in MergeInTypeInfo()
201 if ((InVT.TypeVec[0] == MVT::iPTR || InVT.TypeVec[0] == MVT::iPTRAny) && in MergeInTypeInfo()
207 if ((InVT.TypeVec[0] == MVT::iPTR || InVT.TypeVec[0] == MVT::iPTRAny) && in MergeInTypeInfo()
963 return NodeToApply->UpdateNodeType(ResNo, MVT::iPTR, TP); in ApplyTypeConstraint()
1066 return UpdateNodeType(ResNo, MVT::iPTR, TP); in UpdateNodeTypeFromInst()
1151 return MVT::iPTR; in getKnownType()
1518 return EEVT::TypeSet(MVT::iPTR, TP); in getImplicitType()
1679 if (VT == MVT::iPTR || VT == MVT::iPTRAny) in ApplyTypeConstraints()
1746 MadeChange |= getChild(0)->UpdateNodeType(0, MVT::iPTR, TP); in ApplyTypeConstraints()
HDCodeGenDAGPatterns.h69 assert(T < MVT::LAST_VALUETYPE || T == MVT::iPTR || T == MVT::iPTRAny); in isConcrete()
79 return getConcrete() == MVT::iPTR || getConcrete() == MVT::iPTRAny; in isDynamicallyResolved()
HDDAGISelMatcherOpt.cpp434 CTM->getType() == MVT::iPTR || in FactorNodes()
HDIntrinsicEmitter.cpp351 case MVT::iPTR: { in EncodeFixedType()
/NextBSD/contrib/llvm/lib/Target/BPF/
HDBPFInstrInfo.td19 def SDT_BPFCallSeqStart : SDCallSeqStart<[SDTCisVT<0, iPTR>]>;
20 def SDT_BPFCallSeqEnd : SDCallSeqEnd<[SDTCisVT<0, iPTR>, SDTCisVT<1, iPTR>]>;
21 def SDT_BPFCall : SDTypeProfile<0, -1, [SDTCisVT<0, iPTR>]>;
/NextBSD/contrib/llvm/include/llvm/CodeGen/
HDMachineValueType.h156 iPTR = 255, enumerator
385 case iPTR: in getSizeInBits()
HDValueTypes.td101 def iPTR : ValueType<0 , 255>;
/NextBSD/contrib/llvm/lib/Target/Mips/
HDMipsInstrInfo.td19 def SDT_MipsJmpLink : SDTypeProfile<0, 1, [SDTCisVT<0, iPTR>]>;
356 def calltarget : Operand<iPTR> {
468 class mem_generic : Operand<iPTR> {
502 def mem_ea : Operand<iPTR> {
509 def PtrRC : Operand<iPTR> {
583 ComplexPattern<iPTR, 2, "selectIntAddr", [frameindex]>;
586 ComplexPattern<iPTR, 2, "selectAddrRegImm", [frameindex]>;
589 ComplexPattern<iPTR, 2, "selectAddrRegReg", [frameindex]>;
592 ComplexPattern<iPTR, 2, "selectAddrDefault", [frameindex]>;
594 def addrimm10 : ComplexPattern<iPTR, 2, "selectIntAddrMSA", [frameindex]>;
[all …]
HDMipsInstrFPU.td198 [(set DRC:$fd, (OpNode (add iPTR:$base, iPTR:$index)))], Itin,
207 [(OpNode DRC:$fs, (add iPTR:$base, iPTR:$index))], Itin,
HDMicroMipsInstrInfo.td1 def addrimm12 : ComplexPattern<iPTR, 2, "selectIntAddrMM", [frameindex]>;
2 def addrimm4lsl2 : ComplexPattern<iPTR, 2, "selectIntAddrLSL2MM", [frameindex]>;
136 def calltarget_mm : Operand<iPTR> {
/NextBSD/contrib/llvm/lib/CodeGen/SelectionDAG/
HDSelectionDAGISel.cpp2341 return VT == MVT::iPTR && N.getValueType() == TLI->getPointerTy(DL); in CheckType()
2369 return VT == MVT::iPTR && cast<VTSDNode>(N)->getVT() == TLI->getPointerTy(DL); in CheckValueType()
2874 if (CaseVT == MVT::iPTR) in SelectCodeCommon()
3109 if (VT == MVT::iPTR) in SelectCodeCommon()
3294 NodeToMatch->getValueType(i) == MVT::iPTR || in SelectCodeCommon()
3295 Res.getValueType() == MVT::iPTR || in SelectCodeCommon()
/NextBSD/contrib/llvm/lib/IR/
HDValueTypes.cpp265 case Type::PointerTyID: return MVT(MVT::iPTR); in getVT()
/NextBSD/contrib/llvm/lib/Target/AMDGPU/
HDR600Instructions.td24 def MEMxi : Operand<iPTR> {
29 def MEMrr : Operand<iPTR> {
70 def FRAMEri : Operand<iPTR> {
HDAMDGPUInstructions.td42 def ADDRIndirect : ComplexPattern<iPTR, 2, "SelectADDRIndirect", [], []>;

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