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/NextBSD/contrib/llvm/lib/Target/Hexagon/
HDHexagonInstrInfoV5.td48 (sra (i64 (add (i64 (sra I64:$src1, u6ImmPred:$src2)), 1)),
57 : MInst<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1, u6Imm:$src2),
58 "$dst = asrrnd($src1, #$src2)">;
82 def CONST64_Float_Real : LDInst<(outs DoubleRegs:$dst), (ins f64imm:$src1),
83 "$dst = CONST64(#$src1)",
84 [(set F64:$dst, fpimm:$src1)]>,
88 def CONST32_Float_Real : LDInst<(outs IntRegs:$dst), (ins f32imm:$src1),
89 "$dst = CONST32(#$src1)",
90 [(set F32:$dst, fpimm:$src1)]>,
102 def TFRI_f : ALU32_ri<(outs IntRegs:$dst), (ins f32Ext:$src1),
[all …]
HDHexagonInstrInfo.td70 (ins IntRegs:$src1, ImmOp:$src2),
71 "$dst = "#!if(isNot, "!","")#mnemonic#"($src1, #$src2)",
74 bits<5> src1;
85 let Inst{20-16} = src1;
97 : Pat<(i1 (OpNode (i32 IntRegs:$src1), ImmPred:$src2)),
98 (MI IntRegs:$src1, ImmPred:$src2)>;
481 def: Pat<(not (i32 IntRegs:$src1)),
482 (A2_subri -1, IntRegs:$src1)>;
486 : ALU32Inst <(outs IntRegs:$Rx), (ins IntRegs:$src1, u16Imm:$u16),
488 [], "$src1 = $Rx" > {
[all …]
HDHexagonIntrinsicsDerived.td14 def : Pat <(mul DoubleRegs:$src1, DoubleRegs:$src2),
22 (M2_dpmpyuu_s0 (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src1),
27 (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src1), subreg_loreg)),
30 (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src1), subreg_hireg))),
35 (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src1), subreg_loreg)),
HDHexagonInstrInfoV3.td157 //def : Pat <(brcond (i1 (seteq (i32 IntRegs:$src1), 0)), bb:$offset),
158 // (JMP_RegEzt (i32 IntRegs:$src1), bb:$offset)>;
160 //def : Pat <(brcond (i1 (setne (i32 IntRegs:$src1), 0)), bb:$offset),
161 // (JMP_RegNzt (i32 IntRegs:$src1), bb:$offset)>;
163 //def : Pat <(brcond (i1 (setle (i32 IntRegs:$src1), 0)), bb:$offset),
164 // (JMP_RegLezt (i32 IntRegs:$src1), bb:$offset)>;
166 //def : Pat <(brcond (i1 (setge (i32 IntRegs:$src1), 0)), bb:$offset),
167 // (JMP_RegGezt (i32 IntRegs:$src1), bb:$offset)>;
169 //def : Pat <(brcond (i1 (setgt (i32 IntRegs:$src1), -1)), bb:$offset),
170 // (JMP_RegGezt (i32 IntRegs:$src1), bb:$offset)>;
[all …]
HDHexagonInstrInfoV4.td280 (i32 IntRegs:$src1))), 0)))),
281 (C2_muxii (S2_tstbit_r IntRegs:$src1, IntRegs:$src2), 1, 0)>;
389 def: Pat<(i64 (anyext (i32 IntRegs:$src1))), (Zext64 IntRegs:$src1)>;
450 : LDInst <(outs RC:$dst), (ins IntRegs:$src1, u2Imm:$src2, u6Ext:$src3),
451 "$dst = "#mnemonic#"($src1<<#$src2 + #$src3)",
454 bits<5> src1;
463 let Inst{20-16} = src1;
499 def : Pat <(VT (ldOp (add (shl IntRegs:$src1, u2ImmPred:$src2),
501 (MI IntRegs:$src1, u2ImmPred:$src2, tglobaladdr:$src3)>;
502 def : Pat <(VT (ldOp (add IntRegs:$src1,
[all …]
/NextBSD/contrib/llvm/lib/Target/X86/
HDX86InstrXOP.td88 (ins VR128:$src1, VR128:$src2),
89 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
90 [(set VR128:$dst, (Int VR128:$src1, VR128:$src2))]>, XOP_4VOp3;
92 (ins VR128:$src1, i128mem:$src2),
93 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
95 (Int VR128:$src1, (bitconvert (loadv2i64 addr:$src2))))]>,
98 (ins i128mem:$src1, VR128:$src2),
99 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
101 (Int (bitconvert (loadv2i64 addr:$src1)), VR128:$src2))]>,
122 (ins VR128:$src1, i8imm:$src2),
[all …]
HDX86InstrFMA.td18 let Constraints = "$src1 = $dst" in {
26 (ins VR128:$src1, VR128:$src2, VR128:$src3),
30 VR128:$src1, VR128:$src3)))]>;
34 (ins VR128:$src1, VR128:$src2, f128mem:$src3),
37 [(set VR128:$dst, (OpVT128 (Op VR128:$src2, VR128:$src1,
42 (ins VR256:$src1, VR256:$src2, VR256:$src3),
45 [(set VR256:$dst, (OpVT256 (Op VR256:$src2, VR256:$src1,
50 (ins VR256:$src1, VR256:$src2, f256mem:$src3),
54 (OpVT256 (Op VR256:$src2, VR256:$src1,
57 } // Constraints = "$src1 = $dst"
[all …]
HDX86InstrShiftRotate.td18 let Constraints = "$src1 = $dst", SchedRW = [WriteShift] in {
20 def SHL8rCL : I<0xD2, MRM4r, (outs GR8 :$dst), (ins GR8 :$src1),
22 [(set GR8:$dst, (shl GR8:$src1, CL))], IIC_SR>;
23 def SHL16rCL : I<0xD3, MRM4r, (outs GR16:$dst), (ins GR16:$src1),
25 [(set GR16:$dst, (shl GR16:$src1, CL))], IIC_SR>, OpSize16;
26 def SHL32rCL : I<0xD3, MRM4r, (outs GR32:$dst), (ins GR32:$src1),
28 [(set GR32:$dst, (shl GR32:$src1, CL))], IIC_SR>, OpSize32;
29 def SHL64rCL : RI<0xD3, MRM4r, (outs GR64:$dst), (ins GR64:$src1),
31 [(set GR64:$dst, (shl GR64:$src1, CL))], IIC_SR>;
34 def SHL8ri : Ii8<0xC0, MRM4r, (outs GR8 :$dst), (ins GR8 :$src1, i8imm:$src2),
[all …]
HDX86InstrSSE.td246 def rr : SI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
249 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
250 [(set RC:$dst, (OpNode RC:$src1, RC:$src2))], itins.rr, d>,
253 def rm : SI<opc, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
256 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
257 [(set RC:$dst, (OpNode RC:$src1, (load addr:$src2)))], itins.rm, d>,
267 def rr_Int : SI_Int<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
270 !strconcat(asm, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
273 RC:$src1, RC:$src2))], itins.rr, d>,
275 def rm_Int : SI_Int<opc, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, memopr:$src2),
[all …]
HDX86InstrCompiler.td875 def : Pat<(add GR32:$src1, (X86Wrapper tconstpool:$src2)),
876 (ADD32ri GR32:$src1, tconstpool:$src2)>;
877 def : Pat<(add GR32:$src1, (X86Wrapper tjumptable:$src2)),
878 (ADD32ri GR32:$src1, tjumptable:$src2)>;
879 def : Pat<(add GR32:$src1, (X86Wrapper tglobaladdr :$src2)),
880 (ADD32ri GR32:$src1, tglobaladdr:$src2)>;
881 def : Pat<(add GR32:$src1, (X86Wrapper texternalsym:$src2)),
882 (ADD32ri GR32:$src1, texternalsym:$src2)>;
883 def : Pat<(add GR32:$src1, (X86Wrapper mcsym:$src2)),
884 (ADD32ri GR32:$src1, mcsym:$src2)>;
[all …]
HDX86InstrAVX512.td263 // ($src1) is already tied to $dst so we just use that for the preserved
265 // $src1.
271 !con((ins _.RC:$src1), NonTiedIns),
272 !con((ins _.RC:$src1, _.KRCWM:$mask), NonTiedIns),
273 !con((ins _.RC:$src1, _.KRCWM:$mask), NonTiedIns),
275 (vselect _.KRCWM:$mask, RHS, _.RC:$src1)>;
282 !con((ins _.RC:$src1), NonTiedIns),
283 !con((ins _.RC:$src1, _.KRCWM:$mask), NonTiedIns),
284 !con((ins _.RC:$src1, _.KRCWM:$mask), NonTiedIns),
286 (X86select _.KRCWM:$mask, RHS, _.RC:$src1)>;
[all …]
HDX86InstrMMX.td93 let Constraints = "$src1 = $dst" in {
99 (ins VR64:$src1, VR64:$src2),
101 [(set VR64:$dst, (IntId VR64:$src1, VR64:$src2))], itins.rr>,
106 (ins VR64:$src1, i64mem:$src2),
108 [(set VR64:$dst, (IntId VR64:$src1,
117 (ins VR64:$src1, VR64:$src2),
119 [(set VR64:$dst, (IntId VR64:$src1, VR64:$src2))], itins.rr>,
122 (ins VR64:$src1, i64mem:$src2),
124 [(set VR64:$dst, (IntId VR64:$src1,
128 (ins VR64:$src1, i32u8imm:$src2),
[all …]
HDX86InstrArithmetic.td152 let Constraints = "$src1 = $dst" in {
157 def IMUL16rr : I<0xAF, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src1,GR16:$src2),
160 (X86smul_flag GR16:$src1, GR16:$src2))], IIC_IMUL16_RR>,
162 def IMUL32rr : I<0xAF, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src1,GR32:$src2),
165 (X86smul_flag GR32:$src1, GR32:$src2))], IIC_IMUL32_RR>,
168 (ins GR64:$src1, GR64:$src2),
171 (X86smul_flag GR64:$src1, GR64:$src2))], IIC_IMUL64_RR>,
178 (ins GR16:$src1, i16mem:$src2),
181 (X86smul_flag GR16:$src1, (load addr:$src2)))],
185 (ins GR32:$src1, i32mem:$src2),
[all …]
HDX86InstrMPX.td28 def 32rm: I<opc, MRMSrcMem, (outs), (ins BNDR:$src1, i32mem:$src2),
29 OpcodeStr#" \t{$src2, $src1|$src1, $src2}", []>,
31 def 64rm: RI<opc, MRMSrcMem, (outs), (ins BNDR:$src1, i64mem:$src2),
32 OpcodeStr#" \t{$src2, $src1|$src1, $src2}", []>,
34 def 32rr: I<opc, MRMSrcReg, (outs), (ins BNDR:$src1, GR32:$src2),
35 OpcodeStr#" \t{$src2, $src1|$src1, $src2}", []>,
37 def 64rr: RI<opc, MRMSrcReg, (outs), (ins BNDR:$src1, GR64:$src2),
38 OpcodeStr#" \t{$src2, $src1|$src1, $src2}", []>,
HDX86InstrVMX.td19 def INVEPT32 : I<0x80, MRMSrcMem, (outs), (ins GR32:$src1, i128mem:$src2),
20 "invept\t{$src2, $src1|$src1, $src2}", []>, T8PD,
22 def INVEPT64 : I<0x80, MRMSrcMem, (outs), (ins GR64:$src1, i128mem:$src2),
23 "invept\t{$src2, $src1|$src1, $src2}", []>, T8PD,
26 def INVVPID32 : I<0x81, MRMSrcMem, (outs), (ins GR32:$src1, i128mem:$src2),
27 "invvpid\t{$src2, $src1|$src1, $src2}", []>, T8PD,
29 def INVVPID64 : I<0x81, MRMSrcMem, (outs), (ins GR64:$src1, i128mem:$src2),
30 "invvpid\t{$src2, $src1|$src1, $src2}", []>, T8PD,
HDX86InstrCMovSetCC.td18 let Uses = [EFLAGS], Predicates = [HasCMov], Constraints = "$src1 = $dst",
21 : I<opc, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
24 (X86cmov GR16:$src1, GR16:$src2, CondNode, EFLAGS))],
27 : I<opc, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
30 (X86cmov GR32:$src1, GR32:$src2, CondNode, EFLAGS))],
33 :RI<opc, MRMSrcReg, (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
36 (X86cmov GR64:$src1, GR64:$src2, CondNode, EFLAGS))],
40 let Uses = [EFLAGS], Predicates = [HasCMov], Constraints = "$src1 = $dst",
43 : I<opc, MRMSrcMem, (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
45 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
[all …]
HDX86InstrInfo.td1471 def BT16rr : I<0xA3, MRMDestReg, (outs), (ins GR16:$src1, GR16:$src2),
1472 "bt{w}\t{$src2, $src1|$src1, $src2}",
1473 [(set EFLAGS, (X86bt GR16:$src1, GR16:$src2))], IIC_BT_RR>,
1475 def BT32rr : I<0xA3, MRMDestReg, (outs), (ins GR32:$src1, GR32:$src2),
1476 "bt{l}\t{$src2, $src1|$src1, $src2}",
1477 [(set EFLAGS, (X86bt GR32:$src1, GR32:$src2))], IIC_BT_RR>,
1479 def BT64rr : RI<0xA3, MRMDestReg, (outs), (ins GR64:$src1, GR64:$src2),
1480 "bt{q}\t{$src2, $src1|$src1, $src2}",
1481 [(set EFLAGS, (X86bt GR64:$src1, GR64:$src2))], IIC_BT_RR>, TB;
1490 def BT16mr : I<0xA3, MRMDestMem, (outs), (ins i16mem:$src1, GR16:$src2),
[all …]
HDX86Instr3DNow.td25 let Constraints = "$src1 = $dst";
37 def rr : I3DNow_binop<opc, MRMSrcReg, (ins VR64:$src1, VR64:$src2), Mn, []>;
38 def rm : I3DNow_binop<opc, MRMSrcMem, (ins VR64:$src1, i64mem:$src2), Mn, []>;
42 def rr : I3DNow_binop<opc, MRMSrcReg, (ins VR64:$src1, VR64:$src2), Mn,
44 !strconcat("int_x86_3dnow", Ver, "_", Mn)) VR64:$src1, VR64:$src2))]>;
45 def rm : I3DNow_binop<opc, MRMSrcMem, (ins VR64:$src1, i64mem:$src2), Mn,
47 !strconcat("int_x86_3dnow", Ver, "_", Mn)) VR64:$src1,
52 def rr : I3DNow_conv<opc, MRMSrcReg, (ins VR64:$src1), Mn, []>;
53 def rm : I3DNow_conv<opc, MRMSrcMem, (ins i64mem:$src1), Mn, []>;
HDX86InstrFragmentsSIMD.td633 def mgatherv4i32 : PatFrag<(ops node:$src1, node:$src2, node:$src3),
634 (masked_gather node:$src1, node:$src2, node:$src3) , [{
641 def mgatherv8i32 : PatFrag<(ops node:$src1, node:$src2, node:$src3),
642 (masked_gather node:$src1, node:$src2, node:$src3) , [{
649 def mgatherv2i64 : PatFrag<(ops node:$src1, node:$src2, node:$src3),
650 (masked_gather node:$src1, node:$src2, node:$src3) , [{
656 def mgatherv4i64 : PatFrag<(ops node:$src1, node:$src2, node:$src3),
657 (masked_gather node:$src1, node:$src2, node:$src3) , [{
663 def mgatherv8i64 : PatFrag<(ops node:$src1, node:$src2, node:$src3),
664 (masked_gather node:$src1, node:$src2, node:$src3) , [{
[all …]
/NextBSD/contrib/gcc/
HDreg-stack.c916 swap_to_top (rtx insn, stack regstack, rtx src1, rtx src2) in swap_to_top() argument
924 regno = get_hard_regnum (&temp_stack, src1); in swap_to_top()
1238 rtx *src1, *src2; in compare_for_stack_reg() local
1241 src1 = get_true_reg (&XEXP (pat_src, 0)); in compare_for_stack_reg()
1246 if ((! STACK_REG_P (*src1) in compare_for_stack_reg()
1256 src1 = get_true_reg (&XEXP (pat_src, 0)); in compare_for_stack_reg()
1264 src1_note = find_regno_note (insn, REG_DEAD, REGNO (*src1)); in compare_for_stack_reg()
1271 emit_swap_insn (insn, regstack, *src1); in compare_for_stack_reg()
1273 replace_reg (src1, FIRST_STACK_REG); in compare_for_stack_reg()
1289 && ! (STACK_REG_P (*src1) && STACK_REG_P (*src2) in compare_for_stack_reg()
[all …]
/NextBSD/contrib/llvm/lib/Target/AMDGPU/
HDEvergreenInstructions.td263 // [(set f64:$dst, (fma f64:$src0, f64:$src1, f64:$src2))]
281 [(set i32:$dst, (AMDGPUbfe_u32 i32:$src0, i32:$src1, i32:$src2))],
286 [(set i32:$dst, (AMDGPUbfe_i32 i32:$src0, i32:$src1, i32:$src2))],
293 [(set i32:$dst, (AMDGPUbfi i32:$src0, i32:$src1, i32:$src2))],
307 [(set i32:$dst, (AMDGPUbfm i32:$src0, i32:$src1))],
312 [(set i32:$dst, (AMDGPUmad_u24 i32:$src0, i32:$src1, i32:$src2))], VecALU
331 [(set i32:$dst, (AMDGPUmul_u24 i32:$src0, i32:$src1))], VecALU
374 let src1 = 0;
437 let src1 = 0;
452 R600_Reg32:$src1, REL:$src1_rel, SEL:$src1_sel,
[all …]
HDR600Instructions.td109 let src1 = 0;
140 R600_Reg32:$src1, NEG:$src1_neg, REL:$src1_rel, ABS:$src1_abs, SEL:$src1_sel,
146 "$src1_neg$src1_abs$src1$src1_abs$src1_rel, "
167 R600_Reg32:$src1))], itin
179 R600_Reg32:$src1, NEG:$src1_neg, REL:$src1_rel, SEL:$src1_sel,
185 "$src1_neg$src1$src1_rel, "
350 (ins i32imm:$src0, R600_TReg32_Y:$src1, R600_TReg32_X:$src2),
351 "INTERP_PAIR_XY $src0 $src1 $src2 : $dst0 dst1",
356 (ins i32imm:$src0, R600_TReg32_Y:$src1, R600_TReg32_X:$src2),
357 "INTERP_PAIR_ZW $src0 $src1 $src2 : $dst0 dst1",
[all …]
/NextBSD/contrib/llvm/lib/Target/NVPTX/
HDNVPTXVector.td390 def : Pat<(shl V2I16Regs:$src1, V2I16Regs:$src2),
391 (ShiftLV2I16 V2I16Regs:$src1, (CVTv2i16tov2i32 V2I16Regs:$src2))>;
392 def : Pat<(shl V2I8Regs:$src1, V2I8Regs:$src2),
393 (ShiftLV2I8 V2I8Regs:$src1, (CVTv2i8tov2i32 V2I8Regs:$src2))>;
394 def : Pat<(shl V2I64Regs:$src1, V2I64Regs:$src2),
395 (ShiftLV2I64 V2I64Regs:$src1, (CVTv2i64tov2i32 V2I64Regs:$src2))>;
397 def : Pat<(shl V4I16Regs:$src1, V4I16Regs:$src2),
398 (ShiftLV4I16 V4I16Regs:$src1, (CVTv4i16tov4i32 V4I16Regs:$src2))>;
399 def : Pat<(shl V4I8Regs:$src1, V4I8Regs:$src2),
400 (ShiftLV4I8 V4I8Regs:$src1, (CVTv4i8tov4i32 V4I8Regs:$src2))>;
[all …]
/NextBSD/contrib/llvm/lib/Target/SystemZ/
HDSystemZPatterns.td24 def : Pat<(operator cls:$src1, (sext GR32:$src2)),
25 (insn cls:$src1, GR32:$src2)>;
26 def : Pat<(operator cls:$src1, (sext_inreg GR64:$src2, i32)),
27 (insn cls:$src1, (EXTRACT_SUBREG GR64:$src2, subreg_l32))>;
33 def : Pat<(operator cls:$src1, (zext GR32:$src2)),
34 (insn cls:$src1, GR32:$src2)>;
35 def : Pat<(operator cls:$src1, (and GR64:$src2, 0xffffffff)),
36 (insn cls:$src1, (EXTRACT_SUBREG GR64:$src2, subreg_l32))>;
62 cls:$src1, (load mode:$src2)),
63 (insn cls:$src1, mode:$src2)>;
[all …]
HDSystemZOperators.td485 def inserti8 : PatFrag<(ops node:$src1, node:$src2),
486 (or (and node:$src1, -256), node:$src2)>;
487 def insertll : PatFrag<(ops node:$src1, node:$src2),
488 (or (and node:$src1, 0xffffffffffff0000), node:$src2)>;
489 def insertlh : PatFrag<(ops node:$src1, node:$src2),
490 (or (and node:$src1, 0xffffffff0000ffff), node:$src2)>;
491 def inserthl : PatFrag<(ops node:$src1, node:$src2),
492 (or (and node:$src1, 0xffff0000ffffffff), node:$src2)>;
493 def inserthh : PatFrag<(ops node:$src1, node:$src2),
494 (or (and node:$src1, 0x0000ffffffffffff), node:$src2)>;
[all …]

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