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Searched refs:v2f64 (Results 1 – 25 of 50) sorted by relevance

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/NextBSD/contrib/llvm/lib/Target/ARM/
HDARMCallingConv.td26 // Handle all vector types as either f64 or v2f64.
28 CCIfType<[v2i64, v4i32, v8i16, v16i8, v4f32], CCBitConvertToType<v2f64>>,
30 // f64 and v2f64 are passed in adjacent GPRs, possibly split onto the stack
31 CCIfType<[f64, v2f64], CCCustom<"CC_ARM_APCS_Custom_f64">>,
38 CCIfType<[v2f64], CCAssignToStack<16, 4>>
45 // Handle all vector types as either f64 or v2f64.
47 CCIfType<[v2i64, v4i32, v8i16, v16i8, v4f32], CCBitConvertToType<v2f64>>,
49 CCIfType<[f64, v2f64], CCCustom<"RetCC_ARM_APCS_Custom_f64">>,
59 // Handle all vector types as either f64 or v2f64.
61 CCIfType<[v2i64, v4i32, v8i16, v16i8, v4f32], CCBitConvertToType<v2f64>>,
[all …]
HDARMTargetTransformInfo.cpp57 { ISD::FP_ROUND, MVT::v2f64, 2 }, in getCastInstrCost()
137 { ISD::SINT_TO_FP, MVT::v2f64, MVT::v2i32, 2 }, in getCastInstrCost()
138 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v2i32, 2 }, in getCastInstrCost()
140 { ISD::SINT_TO_FP, MVT::v2f64, MVT::v2i8, 4 }, in getCastInstrCost()
141 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v2i8, 4 }, in getCastInstrCost()
142 { ISD::SINT_TO_FP, MVT::v2f64, MVT::v2i16, 3 }, in getCastInstrCost()
143 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v2i16, 3 }, in getCastInstrCost()
144 { ISD::SINT_TO_FP, MVT::v2f64, MVT::v2i32, 2 }, in getCastInstrCost()
145 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v2i32, 2 }, in getCastInstrCost()
147 { ISD::FP_TO_SINT, MVT::v2i32, MVT::v2f64, 2 }, in getCastInstrCost()
[all …]
HDARMCallingConv.h64 if (LocVT == MVT::v2f64 && in CC_ARM_APCS_Custom_f64()
118 if (LocVT == MVT::v2f64 && in CC_ARM_AAPCS_Custom_f64()
150 if (LocVT == MVT::v2f64 && !f64RetAssign(ValNo, ValVT, LocVT, LocInfo, State)) in RetCC_ARM_APCS_Custom_f64()
224 case MVT::v2f64: in CC_ARM_AAPCS_Custom_Aggregate()
HDARMISelLowering.cpp154 addTypeForNEON(VT, MVT::v2f64, MVT::v4i32); in addQRTypeForNEON()
435 addQRTypeForNEON(MVT::v2f64); in ARMTargetLowering()
445 setOperationAction(ISD::FADD, MVT::v2f64, Expand); in ARMTargetLowering()
446 setOperationAction(ISD::FSUB, MVT::v2f64, Expand); in ARMTargetLowering()
447 setOperationAction(ISD::FMUL, MVT::v2f64, Expand); in ARMTargetLowering()
450 setOperationAction(ISD::FDIV, MVT::v2f64, Expand); in ARMTargetLowering()
451 setOperationAction(ISD::FREM, MVT::v2f64, Expand); in ARMTargetLowering()
455 setOperationAction(ISD::FCOPYSIGN, MVT::v2f64, Expand); in ARMTargetLowering()
458 setOperationAction(ISD::SETCC, MVT::v2f64, Expand); in ARMTargetLowering()
460 setOperationAction(ISD::FNEG, MVT::v2f64, Expand); in ARMTargetLowering()
[all …]
HDARMRegisterInfo.td302 def QPR : RegisterClass<"ARM", [v16i8, v8i16, v4i32, v2i64, v4f32, v2f64], 128,
310 def QPR_VFP2 : RegisterClass<"ARM", [v16i8, v8i16, v4i32, v2i64, v4f32, v2f64],
314 def QPR_8 : RegisterClass<"ARM", [v16i8, v8i16, v4i32, v2i64, v4f32, v2f64],
327 def DPair : RegisterClass<"ARM", [v16i8, v8i16, v4i32, v2i64, v4f32, v2f64],
/NextBSD/contrib/llvm/lib/Target/PowerPC/
HDPPCInstrVSX.td52 SDTCisVT<0, v2f64>, SDTCisPtrTy<1>
55 SDTCisVT<0, v2f64>, SDTCisPtrTy<1>
103 [(set v2f64:$XT, (int_ppc_vsx_lxvd2x xoaddr:$src))]>;
125 [(store v2f64:$XT, xoaddr:$dst)]>;
148 [(set v2f64:$XT, (fadd v2f64:$XA, v2f64:$XB))]>;
158 [(set v2f64:$XT, (fmul v2f64:$XA, v2f64:$XB))]>;
175 [(set v2f64:$XT, (fsub v2f64:$XA, v2f64:$XB))]>;
251 [(set v2f64:$XT, (fma v2f64:$XA, v2f64:$XB, v2f64:$XTi))]>,
283 [(set v2f64:$XT, (fma v2f64:$XA, v2f64:$XB, (fneg v2f64:$XTi)))]>,
315 [(set v2f64:$XT, (fneg (fma v2f64:$XA, v2f64:$XB, v2f64:$XTi)))]>,
[all …]
HDPPCCallingConv.td68 CCIfType<[v2f64, v2i64], CCIfSubtarget<"hasVSX()",
121 CCIfType<[v2f64, v2i64], CCIfSubtarget<"hasVSX()",
162 CCIfType<[v16i8, v8i16, v4i32, v4f32, v2f64, v2i64], CCAssignToStack<16, 16>>
183 CCIfType<[v2f64, v2i64], CCIfSubtarget<"hasVSX()",
HDPPCISelLowering.cpp546 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v2f64, Legal); in PPCTargetLowering()
547 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2f64, Legal); in PPCTargetLowering()
549 setOperationAction(ISD::FFLOOR, MVT::v2f64, Legal); in PPCTargetLowering()
550 setOperationAction(ISD::FCEIL, MVT::v2f64, Legal); in PPCTargetLowering()
551 setOperationAction(ISD::FTRUNC, MVT::v2f64, Legal); in PPCTargetLowering()
552 setOperationAction(ISD::FNEARBYINT, MVT::v2f64, Legal); in PPCTargetLowering()
553 setOperationAction(ISD::FROUND, MVT::v2f64, Legal); in PPCTargetLowering()
557 setOperationAction(ISD::MUL, MVT::v2f64, Legal); in PPCTargetLowering()
558 setOperationAction(ISD::FMA, MVT::v2f64, Legal); in PPCTargetLowering()
560 setOperationAction(ISD::FDIV, MVT::v2f64, Legal); in PPCTargetLowering()
[all …]
/NextBSD/contrib/llvm/lib/Target/AArch64/
HDAArch64TargetTransformInfo.cpp194 { ISD::SINT_TO_FP, MVT::v2f64, MVT::v2i64, 1 }, in getCastInstrCost()
197 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v2i64, 1 }, in getCastInstrCost()
214 { ISD::SINT_TO_FP, MVT::v2f64, MVT::v2i8, 4 }, in getCastInstrCost()
215 { ISD::SINT_TO_FP, MVT::v2f64, MVT::v2i16, 4 }, in getCastInstrCost()
216 { ISD::SINT_TO_FP, MVT::v2f64, MVT::v2i32, 2 }, in getCastInstrCost()
217 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v2i8, 4 }, in getCastInstrCost()
218 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v2i16, 4 }, in getCastInstrCost()
219 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v2i32, 2 }, in getCastInstrCost()
225 { ISD::FP_TO_SINT, MVT::v2i64, MVT::v2f64, 1 }, in getCastInstrCost()
228 { ISD::FP_TO_UINT, MVT::v2i64, MVT::v2f64, 1 }, in getCastInstrCost()
[all …]
HDAArch64CallingConvention.td27 CCIfType<[v2f64, v4f32], CCBitConvertToType<v2i64>>,
33 CCIfBigEndian<CCIfType<[v2i64, v2f64, v4i32, v4f32, v8i16, v8f16, v16i8],
50 // Handle i1, i8, i16, i32, i64, f32, f64 and v2f64 by passing in registers,
73 CCIfType<[f128, v2i64, v4i32, v8i16, v16i8, v4f32, v2f64, v8f16],
81 CCIfType<[f128, v2i64, v4i32, v8i16, v16i8, v4f32, v2f64, v8f16],
87 CCIfType<[v2f64, v4f32], CCBitConvertToType<v2i64>>,
93 CCIfBigEndian<CCIfType<[v2i64, v2f64, v4i32, v4f32, v8i16, v8f16, v16i8],
109 CCIfType<[f128, v2i64, v4i32, v8i16, v16i8, v4f32, v2f64, v8f16],
120 CCIfType<[v2f64, v4f32, f128], CCBitConvertToType<v2i64>>,
131 // Handle i1, i8, i16, i32, i64, f32, f64 and v2f64 by passing in registers,
[all …]
HDAArch64ISelDAGToDAG.cpp2416 else if (VT == MVT::v2i64 || VT == MVT::v2f64) in Select()
2434 else if (VT == MVT::v2i64 || VT == MVT::v2f64) in Select()
2452 else if (VT == MVT::v2i64 || VT == MVT::v2f64) in Select()
2470 else if (VT == MVT::v2i64 || VT == MVT::v2f64) in Select()
2488 else if (VT == MVT::v2i64 || VT == MVT::v2f64) in Select()
2506 else if (VT == MVT::v2i64 || VT == MVT::v2f64) in Select()
2524 else if (VT == MVT::v2i64 || VT == MVT::v2f64) in Select()
2542 else if (VT == MVT::v2i64 || VT == MVT::v2f64) in Select()
2560 else if (VT == MVT::v2i64 || VT == MVT::v2f64) in Select()
2572 else if (VT == MVT::v2i64 || VT == MVT::v1i64 || VT == MVT::v2f64 || in Select()
[all …]
HDAArch64InstrInfo.td1310 defm : ScalToVecROLoadPat<ro64, load, f64, v2f64, LDRDroW, LDRDroX, dsub>;
1352 defm : VecROLoadPat<ro128, v2f64, LDRQroW, LDRQroX>;
1499 def : Pat<(v2f64 (load (am_indexed128 GPR64sp:$Rn, uimm12s16:$offset))),
1657 def : Pat<(v2f64 (load (am_unscaled128 GPR64sp:$Rn, simm9:$offset))),
1977 defm : VecROStorePat<ro128, v2f64, FPR128, STRQroW, STRQroX>;
2010 defm : VecROStoreLane0Pat<ro64, store , v2f64, f64, dsub, STRDroW, STRDroX>;
2077 def : Pat<(store (v2f64 FPR128:$Rt),
2172 def : Pat<(store (v2f64 FPR128:$Rt),
2187 def : Pat<(store (v2f64 FPR128:$Rt),
2282 def : Pat<(pre_store (v2f64 FPR128:$Rt), GPR64sp:$addr, simm9:$off),
[all …]
HDAArch64SchedA57.td415 // Q form - v4f32, v2f64
424 def : InstRW<[A57Write_5cyc_2V], (instregex "^(FABD|FADD|FSUB)(v4f32|v2f64|v2i64p)")>;
429 def : InstRW<[A57Write_9cyc_3V], (instregex "^FADDP(v4f32|v2f64|v2i64)")>;
434 …ite_5cyc_2V], (instregex "^(FACGE|FACGT|FCMEQ|FCMGE|FCMGT|FCMLE|FCMLT)(v4f32|v2f64|v4i32|v2i64)")>;
441 def : InstRW<[A57Write_5cyc_2V], (instregex "^[FVSU]CVT([AMNPZ][SU])?(_Int)?(v4f32|v2f64|v4i32|v2i6…
461 def : InstRW<[A57Write_5cyc_2V], (instregex "^(FMAX|FMIN)(NM)?(v4f32|v2f64)")>;
465 def : InstRW<[A57Write_9cyc_3V], (instregex "^(FMAX|FMIN)(NM)?P(v4f32|v2f64|v2i64)")>;
472 def : InstRW<[A57Write_5cyc_2V], (instregex "^FMULX?(v4f32|v2f64|v4i32|v2i64)")>;
480 def : InstRW<[A57WriteFPVMAQ, A57ReadFPVMA5], (instregex "^FML[AS](v4f32|v2f64|v4i32|v2i64)")>;
485 def : InstRW<[A57Write_5cyc_2V], (instregex "^FRINT[AIMNPXZ](v4f32|v2f64)")>;
[all …]
/NextBSD/contrib/llvm/lib/Target/X86/
HDX86InstrFMA.td103 loadv4f64, X86Fmadd, v2f64, v4f64>, VEX_W;
105 loadv4f64, X86Fmsub, v2f64, v4f64>, VEX_W;
108 v2f64, v4f64>, VEX_W;
111 v2f64, v4f64>, VEX_W;
123 loadv4f64, X86Fnmadd, v2f64, v4f64>, VEX_W;
125 loadv2f64, loadv4f64, X86Fnmsub, v2f64,
382 defm VFMADDPD4 : fma4p<0x69, "vfmaddpd", X86Fmadd, v2f64, v4f64,
384 defm VFMSUBPD4 : fma4p<0x6D, "vfmsubpd", X86Fmsub, v2f64, v4f64,
386 defm VFNMADDPD4 : fma4p<0x79, "vfnmaddpd", X86Fnmadd, v2f64, v4f64,
388 defm VFNMSUBPD4 : fma4p<0x7D, "vfnmsubpd", X86Fnmsub, v2f64, v4f64,
[all …]
HDX86InstrSSE.td335 def : Pat<(f64 (vector_extract (v2f64 VR128:$src), (iPTR 0))),
336 (COPY_TO_REGCLASS (v2f64 VR128:$src), FR64)>;
347 def : Pat<(v2f64 (extract_subvector (v4f64 VR256:$src), (iPTR 0))),
348 (v2f64 (EXTRACT_SUBREG (v4f64 VR256:$src), sub_xmm))>;
360 def : Pat<(insert_subvector undef, (v2f64 VR128:$src), (iPTR 0)),
378 def : Pat<(v2f64 (scalar_to_vector FR64:$src)),
389 def : Pat<(v2i64 (bitconvert (v2f64 VR128:$src))), (v2i64 VR128:$src)>;
394 def : Pat<(v4i32 (bitconvert (v2f64 VR128:$src))), (v4i32 VR128:$src)>;
399 def : Pat<(v8i16 (bitconvert (v2f64 VR128:$src))), (v8i16 VR128:$src)>;
404 def : Pat<(v16i8 (bitconvert (v2f64 VR128:$src))), (v16i8 VR128:$src)>;
[all …]
HDX86TargetTransformInfo.cpp402 {ISD::VECTOR_SHUFFLE, MVT::v2f64, 1}, in getShuffleCost()
425 {ISD::VECTOR_SHUFFLE, MVT::v2f64, 1}, // movsd in getShuffleCost()
444 {ISD::VECTOR_SHUFFLE, MVT::v2f64, 1}, // movsd in getShuffleCost()
478 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v2i64, 2*10 }, in getCastInstrCost()
479 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v4i32, 4*10 }, in getCastInstrCost()
480 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v8i16, 8*10 }, in getCastInstrCost()
481 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v16i8, 16*10 }, in getCastInstrCost()
482 { ISD::SINT_TO_FP, MVT::v2f64, MVT::v2i64, 2*10 }, in getCastInstrCost()
483 { ISD::SINT_TO_FP, MVT::v2f64, MVT::v4i32, 4*10 }, in getCastInstrCost()
484 { ISD::SINT_TO_FP, MVT::v2f64, MVT::v8i16, 8*10 }, in getCastInstrCost()
[all …]
HDX86CallingConv.td56 CCIfType<[v16i8, v8i16, v4i32, v2i64, v4f32, v2f64],
113 CCIfType<[f32, f64, v4i32, v2i64, v4f32, v2f64],
141 CCIfType<[f32, f64, v16i8, v8i16, v4i32, v2i64, v4f32, v2f64],
283 CCIfType<[f32, f64, v16i8, v8i16, v4i32, v2i64, v4f32, v2f64],
311 CCIfType<[v16i8, v8i16, v4i32, v2i64, v4f32, v2f64], CCAssignToStack<16, 16>>,
334 CCIfType<[v16i8, v8i16, v4i32, v2i64, v4f32, v2f64], CCPassIndirect<i64>>,
360 CCIfType<[f32, f64, v16i8, v8i16, v4i32, v2i64, v4f32, v2f64],
376 CCIfType<[f32, f64, v16i8, v8i16, v4i32, v2i64, v4f32, v2f64],
401 CCIfType<[f32, f64, v16i8, v8i16, v4i32, v2i64, v4f32, v2f64],
452 CCIfType<[v16i8, v8i16, v4i32, v2i64, v4f32, v2f64], CCAssignToStack<16, 16>>,
[all …]
HDX86InstrFragmentsSIMD.td71 SDTypeProfile<1, 1, [SDTCisVT<0, v2f64>,
74 SDTypeProfile<1, 1, [SDTCisVT<0, v2f64>,
442 def sse_load_f64 : ComplexPattern<v2f64, 5, "SelectScalarSSELoad", [],
452 def sdmem : Operand<v2f64> {
466 def loadv2f64 : PatFrag<(ops node:$ptr), (v2f64 (load node:$ptr))>;
484 def extloadv2f32 : PatFrag<(ops node:$ptr), (v2f64 (extloadvf32 node:$ptr))>;
545 (v2f64 (alignedload node:$ptr))>;
585 def memopv2f64 : PatFrag<(ops node:$ptr), (v2f64 (memop node:$ptr))>;
727 def bc_v2f64 : PatFrag<(ops node:$in), (v2f64 (bitconvert node:$in))>;
/NextBSD/contrib/llvm/lib/Target/SystemZ/
HDSystemZInstrVector.td128 def : Pat<(v2f64 (z_replicate_loadf64 bdxaddr12only:$addr)),
145 def : Pat<(v2f64 (z_vllezf64 bdxaddr12only:$addr)),
155 def : Pat<(z_vlef64 (v2f64 VR128:$val), bdxaddr12only:$addr, imm32zx1:$index),
180 defm : ReplicatePeephole<VLREPG, v2f64, load, f64>;
204 def : Pat<(z_vstef64 (v2f64 VR128:$val), bdxaddr12only:$addr,
231 def : BinaryRRWithType<VMRHG, VR128, z_merge_high, v2f64>;
239 def : BinaryRRWithType<VMRLG, VR128, z_merge_low, v2f64>;
254 def : Pat<(v2f64 (z_splat VR128:$vec, imm32zx16:$index)),
338 defm : GenericVectorOps<v2f64, v2i64>;
848 def : Pat<(v4f32 (z_vround (v2f64 VR128:$src))), (VLEDB VR128:$src, 0, 0)>;
[all …]
HDSystemZCallingConv.td54 CCIfType<[v16i8, v8i16, v4i32, v2i64, v4f32, v2f64],
84 CCIfType<[v16i8, v8i16, v4i32, v2i64, v4f32, v2f64],
91 CCIfType<[v16i8, v8i16, v4i32, v2i64, v4f32, v2f64],
96 CCIfType<[v16i8, v8i16, v4i32, v2i64, v4f32, v2f64],
HDSystemZRegisterInfo.td249 [v16i8, v8i16, v4i32, v2i64, v4f32, v2f64], 128,
254 [v16i8, v8i16, v4i32, v2i64, v4f32, v2f64], 128,
275 def v128db : TypedReg<v2f64, VR128>;
/NextBSD/contrib/llvm/include/llvm/CodeGen/
HDMachineValueType.h103 v2f64 = 52, // 2 x f64 enumerator
229 SimpleTy == MVT::v4f32 || SimpleTy == MVT::v2f64); in is128BitVector()
324 case v2f64: in getVectorElementType()
368 case v2f64: return 2; in getVectorNumElements()
436 case v2f64: return 128; in getSizeInBits()
586 if (NumElements == 2) return MVT::v2f64; in getVectorVT()
/NextBSD/contrib/llvm/lib/Target/Mips/
HDMipsMSAInstrInfo.td181 def vfsetoeq_v2f64 : vfsetcc_type<v2i64, v2f64, SETOEQ>;
183 def vfsetoge_v2f64 : vfsetcc_type<v2i64, v2f64, SETOGE>;
185 def vfsetogt_v2f64 : vfsetcc_type<v2i64, v2f64, SETOGT>;
187 def vfsetole_v2f64 : vfsetcc_type<v2i64, v2f64, SETOLE>;
189 def vfsetolt_v2f64 : vfsetcc_type<v2i64, v2f64, SETOLT>;
191 def vfsetone_v2f64 : vfsetcc_type<v2i64, v2f64, SETONE>;
193 def vfsetord_v2f64 : vfsetcc_type<v2i64, v2f64, SETO>;
195 def vfsetun_v2f64 : vfsetcc_type<v2i64, v2f64, SETUO>;
197 def vfsetueq_v2f64 : vfsetcc_type<v2i64, v2f64, SETUEQ>;
199 def vfsetuge_v2f64 : vfsetcc_type<v2i64, v2f64, SETUGE>;
[all …]
/NextBSD/contrib/llvm/lib/Target/X86/InstPrinter/
HDX86InstComments.cpp135 DecodeBLENDMask(MVT::v2f64, in EmitAnyX86InstComments()
307 DecodeMOVDDUPMask(MVT::v2f64, ShuffleMask); in EmitAnyX86InstComments()
626 DecodeSHUFPMask(MVT::v2f64, in EmitAnyX86InstComments()
675 DecodeUNPCKLMask(MVT::v2f64, ShuffleMask); in EmitAnyX86InstComments()
727 DecodeUNPCKHMask(MVT::v2f64, ShuffleMask); in EmitAnyX86InstComments()
798 DecodePSHUFMask(MVT::v2f64, in EmitAnyX86InstComments()
846 DecodeScalarMoveMask(MVT::v2f64, nullptr == Src2Name, ShuffleMask); in EmitAnyX86InstComments()
/NextBSD/contrib/llvm/lib/IR/
HDValueTypes.cpp170 case MVT::v2f64: return "v2f64"; in getEVTString()
239 case MVT::v2f64: return VectorType::get(Type::getDoubleTy(Context), 2); in getTypeForEVT()

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