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Searched refs:WREG32 (Results 1 – 25 of 102) sorted by relevance

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/dragonfly/sys/dev/drm/radeon/
HDrv515.c147 WREG32(R_000300_VGA_RENDER_CONTROL, in rv515_vga_render_disable()
212 WREG32(MC_IND_INDEX, 0x7f0000 | (reg & 0xffff)); in rv515_mc_rreg()
214 WREG32(MC_IND_INDEX, 0); in rv515_mc_rreg()
225 WREG32(MC_IND_INDEX, 0xff0000 | ((reg) & 0xffff)); in rv515_mc_wreg()
226 WREG32(MC_IND_DATA, (v)); in rv515_mc_wreg()
227 WREG32(MC_IND_INDEX, 0); in rv515_mc_wreg()
301 WREG32(R_000300_VGA_RENDER_CONTROL, 0); in rv515_mc_stop()
310 WREG32(AVIVO_D1CRTC_UPDATE_LOCK + crtc_offsets[i], 1); in rv515_mc_stop()
312 WREG32(AVIVO_D1CRTC_CONTROL + crtc_offsets[i], tmp); in rv515_mc_stop()
313 WREG32(AVIVO_D1CRTC_UPDATE_LOCK + crtc_offsets[i], 0); in rv515_mc_stop()
[all …]
HDradeon_bios.c294 WREG32(R600_BUS_CNTL, (bus_cntl & ~R600_BIOS_ROM_DIS));
297 WREG32(AVIVO_D1VGA_CONTROL,
300 WREG32(AVIVO_D2VGA_CONTROL,
303 WREG32(AVIVO_VGA_RENDER_CONTROL,
306 WREG32(R600_ROM_CNTL, rom_cntl | R600_SCK_OVERWRITE);
311 WREG32(R600_BUS_CNTL, bus_cntl);
313 WREG32(AVIVO_D1VGA_CONTROL, d1vga_control);
314 WREG32(AVIVO_D2VGA_CONTROL, d2vga_control);
315 WREG32(AVIVO_VGA_RENDER_CONTROL, vga_render_control);
317 WREG32(R600_ROM_CNTL, rom_cntl);
[all …]
HDrv770.c809 WREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset, tmp); in rv770_page_flip()
812 WREG32(AVIVO_D1GRPH_FLIP_CONTROL + radeon_crtc->crtc_offset, in rv770_page_flip()
815 WREG32(D2GRPH_SECONDARY_SURFACE_ADDRESS_HIGH, upper_32_bits(crtc_base)); in rv770_page_flip()
816 WREG32(D2GRPH_PRIMARY_SURFACE_ADDRESS_HIGH, upper_32_bits(crtc_base)); in rv770_page_flip()
818 WREG32(D1GRPH_SECONDARY_SURFACE_ADDRESS_HIGH, upper_32_bits(crtc_base)); in rv770_page_flip()
819 WREG32(D1GRPH_PRIMARY_SURFACE_ADDRESS_HIGH, upper_32_bits(crtc_base)); in rv770_page_flip()
821 WREG32(D1GRPH_SECONDARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset, in rv770_page_flip()
823 WREG32(D1GRPH_PRIMARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset, in rv770_page_flip()
836 WREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset, tmp); in rv770_page_flip()
903 WREG32(VM_L2_CNTL, ENABLE_L2_CACHE | ENABLE_L2_FRAGMENT_PROCESSING | in rv770_pcie_gart_enable()
[all …]
HDvce_v2_0.c45 WREG32(VCE_CLOCK_GATING_B, tmp); in vce_v2_0_set_sw_cg()
49 WREG32(VCE_UENC_CLOCK_GATING, tmp); in vce_v2_0_set_sw_cg()
53 WREG32(VCE_UENC_REG_CLOCK_GATING, tmp); in vce_v2_0_set_sw_cg()
55 WREG32(VCE_CGTT_CLK_OVERRIDE, 0); in vce_v2_0_set_sw_cg()
60 WREG32(VCE_CLOCK_GATING_B, tmp); in vce_v2_0_set_sw_cg()
65 WREG32(VCE_UENC_CLOCK_GATING, tmp); in vce_v2_0_set_sw_cg()
69 WREG32(VCE_UENC_REG_CLOCK_GATING, tmp); in vce_v2_0_set_sw_cg()
85 WREG32(VCE_CLOCK_GATING_B, tmp); in vce_v2_0_set_dyn_cg()
91 WREG32(VCE_UENC_CLOCK_GATING, tmp); in vce_v2_0_set_dyn_cg()
96 WREG32(VCE_UENC_REG_CLOCK_GATING, tmp); in vce_v2_0_set_dyn_cg()
[all …]
HDuvd_v1_0.c70 WREG32(UVD_RBC_RB_WPTR, ring->wptr); in uvd_v1_0_set_wptr()
123 WREG32(UVD_VCPU_CACHE_OFFSET0, addr); in uvd_v1_0_resume()
124 WREG32(UVD_VCPU_CACHE_SIZE0, size); in uvd_v1_0_resume()
128 WREG32(UVD_VCPU_CACHE_OFFSET1, addr); in uvd_v1_0_resume()
129 WREG32(UVD_VCPU_CACHE_SIZE1, size); in uvd_v1_0_resume()
134 WREG32(UVD_VCPU_CACHE_OFFSET2, addr); in uvd_v1_0_resume()
135 WREG32(UVD_VCPU_CACHE_SIZE2, size); in uvd_v1_0_resume()
139 WREG32(UVD_LMI_ADDR_EXT, (addr << 12) | (addr << 0)); in uvd_v1_0_resume()
143 WREG32(UVD_LMI_EXT40_ADDR, addr | (0x9 << 16) | (0x1 << 31)); in uvd_v1_0_resume()
145 WREG32(UVD_FW_START, *((uint32_t*)rdev->uvd.cpu_addr)); in uvd_v1_0_resume()
[all …]
HDr600.c116 WREG32(R600_RCU_INDEX, ((reg) & 0x1fff)); in r600_rcu_rreg()
127 WREG32(R600_RCU_INDEX, ((reg) & 0x1fff)); in r600_rcu_wreg()
128 WREG32(R600_RCU_DATA, (v)); in r600_rcu_wreg()
138 WREG32(R600_UVD_CTX_INDEX, ((reg) & 0x1ff)); in r600_uvd_ctx_rreg()
149 WREG32(R600_UVD_CTX_INDEX, ((reg) & 0x1ff)); in r600_uvd_ctx_wreg()
150 WREG32(R600_UVD_CTX_DATA, (v)); in r600_uvd_ctx_wreg()
336 WREG32(FMT_BIT_DEPTH_CONTROL + radeon_crtc->crtc_offset, tmp); in dce3_program_fmt()
863 WREG32(DC_HPD1_INT_CONTROL, tmp); in r600_hpd_set_polarity()
871 WREG32(DC_HPD2_INT_CONTROL, tmp); in r600_hpd_set_polarity()
879 WREG32(DC_HPD3_INT_CONTROL, tmp); in r600_hpd_set_polarity()
[all …]
HDvce_v1_0.c97 WREG32(VCE_RB_WPTR, ring->wptr); in vce_v1_0_set_wptr()
99 WREG32(VCE_RB_WPTR2, ring->wptr); in vce_v1_0_set_wptr()
110 WREG32(VCE_CLOCK_GATING_A, tmp); in vce_v1_0_enable_mgcg()
115 WREG32(VCE_UENC_CLOCK_GATING, tmp); in vce_v1_0_enable_mgcg()
119 WREG32(VCE_UENC_REG_CLOCK_GATING, tmp); in vce_v1_0_enable_mgcg()
123 WREG32(VCE_CLOCK_GATING_A, tmp); in vce_v1_0_enable_mgcg()
128 WREG32(VCE_UENC_CLOCK_GATING, tmp); in vce_v1_0_enable_mgcg()
132 WREG32(VCE_UENC_REG_CLOCK_GATING, tmp); in vce_v1_0_enable_mgcg()
142 WREG32(VCE_CLOCK_GATING_A, tmp); in vce_v1_0_init_cg()
147 WREG32(VCE_CLOCK_GATING_B, tmp); in vce_v1_0_init_cg()
[all …]
HDradeon_i2c.c117 WREG32(RADEON_DVI_I2C_CNTL_0, (RADEON_I2C_SOFT_RST | in pre_xfer()
120 WREG32(RADEON_DVI_I2C_CNTL_0, (RADEON_I2C_SOFT_RST | in pre_xfer()
131 WREG32(rec->mask_clk_reg, temp); in pre_xfer()
136 WREG32(rec->a_clk_reg, temp); in pre_xfer()
139 WREG32(rec->a_data_reg, temp); in pre_xfer()
143 WREG32(rec->en_clk_reg, temp); in pre_xfer()
146 WREG32(rec->en_data_reg, temp); in pre_xfer()
150 WREG32(rec->mask_clk_reg, temp); in pre_xfer()
154 WREG32(rec->mask_data_reg, temp); in pre_xfer()
169 WREG32(rec->mask_clk_reg, temp); in post_xfer()
[all …]
HDni.c46 WREG32(TN_SMC_IND_INDEX_0, (reg)); in tn_smc_rreg()
55 WREG32(TN_SMC_IND_INDEX_0, (reg)); in tn_smc_wreg()
56 WREG32(TN_SMC_IND_DATA_0, (v)); in tn_smc_wreg()
655 WREG32(MC_SHARED_BLACKOUT_CNTL, 1); in ni_mc_load_microcode()
659 WREG32(MC_SEQ_SUP_CNTL, 0x00000008); in ni_mc_load_microcode()
660 WREG32(MC_SEQ_SUP_CNTL, 0x00000010); in ni_mc_load_microcode()
664 WREG32(MC_SEQ_IO_DEBUG_INDEX, io_mc_regs[(i << 1)]); in ni_mc_load_microcode()
665 WREG32(MC_SEQ_IO_DEBUG_DATA, io_mc_regs[(i << 1) + 1]); in ni_mc_load_microcode()
670 WREG32(MC_SEQ_SUP_PGM, be32_to_cpup(fw_data++)); in ni_mc_load_microcode()
673 WREG32(MC_SEQ_SUP_CNTL, 0x00000008); in ni_mc_load_microcode()
[all …]
HDevergreen.c51 WREG32(EVERGREEN_CG_IND_ADDR, ((reg) & 0xffff)); in eg_cg_rreg()
62 WREG32(EVERGREEN_CG_IND_ADDR, ((reg) & 0xffff)); in eg_cg_wreg()
63 WREG32(EVERGREEN_CG_IND_DATA, (v)); in eg_cg_wreg()
73 WREG32(EVERGREEN_PIF_PHY0_INDEX, ((reg) & 0xffff)); in eg_pif_phy0_rreg()
84 WREG32(EVERGREEN_PIF_PHY0_INDEX, ((reg) & 0xffff)); in eg_pif_phy0_wreg()
85 WREG32(EVERGREEN_PIF_PHY0_DATA, (v)); in eg_pif_phy0_wreg()
95 WREG32(EVERGREEN_PIF_PHY1_INDEX, ((reg) & 0xffff)); in eg_pif_phy1_rreg()
106 WREG32(EVERGREEN_PIF_PHY1_INDEX, ((reg) & 0xffff)); in eg_pif_phy1_wreg()
107 WREG32(EVERGREEN_PIF_PHY1_DATA, (v)); in eg_pif_phy1_wreg()
1169 WREG32(CG_SCRATCH1, cg_scratch); in sumo_set_uvd_clocks()
[all …]
HDradeon_legacy_encoders.c85 WREG32(RADEON_DISP_PWR_MAN, disp_pwr_man); in radeon_legacy_lvds_update()
88 WREG32(RADEON_LVDS_PLL_CNTL, lvds_pll_cntl); in radeon_legacy_lvds_update()
93 WREG32(RADEON_LVDS_PLL_CNTL, lvds_pll_cntl); in radeon_legacy_lvds_update()
103 WREG32(RADEON_LVDS_GEN_CNTL, lvds_gen_cntl); in radeon_legacy_lvds_update()
113 WREG32(RADEON_LVDS_GEN_CNTL, lvds_gen_cntl); in radeon_legacy_lvds_update()
116 WREG32(RADEON_LVDS_GEN_CNTL, lvds_gen_cntl); in radeon_legacy_lvds_update()
120 WREG32(RADEON_LVDS_GEN_CNTL, lvds_gen_cntl); in radeon_legacy_lvds_update()
231 WREG32(RADEON_LVDS_GEN_CNTL, lvds_gen_cntl); in radeon_legacy_lvds_mode_set()
232 WREG32(RADEON_LVDS_PLL_CNTL, lvds_pll_cntl); in radeon_legacy_lvds_mode_set()
233 WREG32(RADEON_LVDS_SS_GEN_CNTL, lvds_ss_gen_cntl); in radeon_legacy_lvds_mode_set()
[all …]
HDcik.c176 WREG32(CIK_DIDT_IND_INDEX, (reg)); in cik_didt_rreg()
187 WREG32(CIK_DIDT_IND_INDEX, (reg)); in cik_didt_wreg()
188 WREG32(CIK_DIDT_IND_DATA, (v)); in cik_didt_wreg()
238 WREG32(PCIE_INDEX, reg); in cik_pciep_rreg()
250 WREG32(PCIE_INDEX, reg); in cik_pciep_wreg()
252 WREG32(PCIE_DATA, v); in cik_pciep_wreg()
1846 WREG32(SRBM_GFX_CNTL, srbm_gfx_cntl); in cik_srbm_select()
1904 WREG32(MC_SEQ_SUP_CNTL, 0x00000008); in ci_mc_load_microcode()
1905 WREG32(MC_SEQ_SUP_CNTL, 0x00000010); in ci_mc_load_microcode()
1910 … WREG32(MC_SEQ_IO_DEBUG_INDEX, le32_to_cpup(new_io_mc_regs++)); in ci_mc_load_microcode()
[all …]
HDevergreen_hdmi.c67 WREG32(AZ_HOT_PLUG_CONTROL, tmp); in dce4_audio_enable()
85 WREG32(HDMI_ACR_PACKET_CONTROL + offset, in evergreen_hdmi_update_acr()
88 WREG32(HDMI_ACR_PACKET_CONTROL + offset, in evergreen_hdmi_update_acr()
92 WREG32(HDMI_ACR_32_0 + offset, HDMI_ACR_CTS_32(acr->cts_32khz)); in evergreen_hdmi_update_acr()
93 WREG32(HDMI_ACR_32_1 + offset, acr->n_32khz); in evergreen_hdmi_update_acr()
95 WREG32(HDMI_ACR_44_0 + offset, HDMI_ACR_CTS_44(acr->cts_44_1khz)); in evergreen_hdmi_update_acr()
96 WREG32(HDMI_ACR_44_1 + offset, acr->n_44_1khz); in evergreen_hdmi_update_acr()
98 WREG32(HDMI_ACR_48_0 + offset, HDMI_ACR_CTS_48(acr->cts_48khz)); in evergreen_hdmi_update_acr()
99 WREG32(HDMI_ACR_48_1 + offset, acr->n_48khz); in evergreen_hdmi_update_acr()
228 WREG32(AFMT_AVI_INFO0 + offset, in evergreen_set_avi_packet()
[all …]
HDsi.c1618 WREG32(MC_SEQ_SUP_CNTL, 0x00000008); in si_mc_load_microcode()
1619 WREG32(MC_SEQ_SUP_CNTL, 0x00000010); in si_mc_load_microcode()
1624 … WREG32(MC_SEQ_IO_DEBUG_INDEX, le32_to_cpup(new_io_mc_regs++)); in si_mc_load_microcode()
1625 … WREG32(MC_SEQ_IO_DEBUG_DATA, le32_to_cpup(new_io_mc_regs++)); in si_mc_load_microcode()
1627 WREG32(MC_SEQ_IO_DEBUG_INDEX, io_mc_regs[(i << 1)]); in si_mc_load_microcode()
1628 WREG32(MC_SEQ_IO_DEBUG_DATA, io_mc_regs[(i << 1) + 1]); in si_mc_load_microcode()
1634 WREG32(MC_SEQ_SUP_PGM, le32_to_cpup(new_fw_data++)); in si_mc_load_microcode()
1636 WREG32(MC_SEQ_SUP_PGM, be32_to_cpup(fw_data++)); in si_mc_load_microcode()
1640 WREG32(MC_SEQ_SUP_CNTL, 0x00000008); in si_mc_load_microcode()
1641 WREG32(MC_SEQ_SUP_CNTL, 0x00000004); in si_mc_load_microcode()
[all …]
HDrs600.c120 WREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset, tmp); in rs600_page_flip()
123 WREG32(AVIVO_D1GRPH_FLIP_CONTROL + radeon_crtc->crtc_offset, in rs600_page_flip()
125 WREG32(AVIVO_D1GRPH_SECONDARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset, in rs600_page_flip()
127 WREG32(AVIVO_D1GRPH_PRIMARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset, in rs600_page_flip()
140 WREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset, tmp); in rs600_page_flip()
200 WREG32(AVIVO_TMDSA_BIT_DEPTH_CONTROL, tmp); in avivo_program_fmt()
203 WREG32(AVIVO_LVTMA_BIT_DEPTH_CONTROL, tmp); in avivo_program_fmt()
206 WREG32(AVIVO_DVOA_BIT_DEPTH_CONTROL, tmp); in avivo_program_fmt()
209 WREG32(AVIVO_DDIA_BIT_DEPTH_CONTROL, tmp); in avivo_program_fmt()
231 WREG32(voltage->gpio.reg, tmp); in rs600_pm_misc()
[all …]
HDradeon_cursor.c42 WREG32(EVERGREEN_CUR_UPDATE + radeon_crtc->crtc_offset, cur_lock); in radeon_lock_cursor()
49 WREG32(AVIVO_D1CUR_UPDATE + radeon_crtc->crtc_offset, cur_lock); in radeon_lock_cursor()
56 WREG32(RADEON_CUR_OFFSET + radeon_crtc->crtc_offset, cur_lock); in radeon_lock_cursor()
97 WREG32(EVERGREEN_CUR_SURFACE_ADDRESS_HIGH + radeon_crtc->crtc_offset, in radeon_show_cursor()
99 WREG32(EVERGREEN_CUR_SURFACE_ADDRESS + radeon_crtc->crtc_offset, in radeon_show_cursor()
101 WREG32(RADEON_MM_INDEX, EVERGREEN_CUR_CONTROL + radeon_crtc->crtc_offset); in radeon_show_cursor()
102 WREG32(RADEON_MM_DATA, EVERGREEN_CURSOR_EN | in radeon_show_cursor()
108 WREG32(R700_D2CUR_SURFACE_ADDRESS_HIGH, in radeon_show_cursor()
111 WREG32(R700_D1CUR_SURFACE_ADDRESS_HIGH, in radeon_show_cursor()
115 WREG32(AVIVO_D1CUR_SURFACE_ADDRESS + radeon_crtc->crtc_offset, in radeon_show_cursor()
[all …]
HDradeon_legacy_tv.c282 WREG32(RADEON_TEST_DEBUG_MUX, (RREG32(RADEON_TEST_DEBUG_MUX) & 0xffff60ff) | 0x100); in radeon_wait_pll_lock()
294 WREG32(RADEON_TEST_DEBUG_MUX, RREG32(RADEON_TEST_DEBUG_MUX) & 0xffffe0ff); in radeon_wait_pll_lock()
306 WREG32(RADEON_TV_HOST_WRITE_DATA, value); in radeon_legacy_tv_write_fifo()
308 WREG32(RADEON_TV_HOST_RD_WT_CNTL, addr); in radeon_legacy_tv_write_fifo()
309 WREG32(RADEON_TV_HOST_RD_WT_CNTL, addr | RADEON_HOST_FIFO_WT); in radeon_legacy_tv_write_fifo()
317 WREG32(RADEON_TV_HOST_RD_WT_CNTL, 0); in radeon_legacy_tv_write_fifo()
328 WREG32(RADEON_TV_HOST_RD_WT_CNTL, addr);
329 WREG32(RADEON_TV_HOST_RD_WT_CNTL, addr | RADEON_HOST_FIFO_RD);
337 WREG32(RADEON_TV_HOST_RD_WT_CNTL, 0);
393 WREG32(RADEON_TV_UV_ADR, tv_dac->tv.tv_uv_adr); in radeon_restore_tv_timing_tables()
[all …]
/dragonfly/sys/dev/drm/amd/amdgpu/
HDgmc_v8_0.c183 WREG32(mmBIF_FB_EN, 0); in gmc_v8_0_mc_stop()
187 WREG32(mmMC_SHARED_BLACKOUT_CNTL, blackout); in gmc_v8_0_mc_stop()
200 WREG32(mmMC_SHARED_BLACKOUT_CNTL, tmp); in gmc_v8_0_mc_resume()
204 WREG32(mmBIF_FB_EN, tmp); in gmc_v8_0_mc_resume()
328 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000008); in gmc_v8_0_tonga_mc_load_microcode()
329 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000010); in gmc_v8_0_tonga_mc_load_microcode()
333 WREG32(mmMC_SEQ_IO_DEBUG_INDEX, le32_to_cpup(io_mc_regs++)); in gmc_v8_0_tonga_mc_load_microcode()
334 WREG32(mmMC_SEQ_IO_DEBUG_DATA, le32_to_cpup(io_mc_regs++)); in gmc_v8_0_tonga_mc_load_microcode()
338 WREG32(mmMC_SEQ_SUP_PGM, le32_to_cpup(fw_data++)); in gmc_v8_0_tonga_mc_load_microcode()
341 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000008); in gmc_v8_0_tonga_mc_load_microcode()
[all …]
HDvce_v3_0.c86 WREG32(mmGRBM_GFX_INDEX, GET_VCE_INSTANCE(0)); in vce_v3_0_ring_get_rptr()
88 WREG32(mmGRBM_GFX_INDEX, GET_VCE_INSTANCE(1)); in vce_v3_0_ring_get_rptr()
97 WREG32(mmGRBM_GFX_INDEX, mmGRBM_GFX_INDEX_DEFAULT); in vce_v3_0_ring_get_rptr()
118 WREG32(mmGRBM_GFX_INDEX, GET_VCE_INSTANCE(0)); in vce_v3_0_ring_get_wptr()
120 WREG32(mmGRBM_GFX_INDEX, GET_VCE_INSTANCE(1)); in vce_v3_0_ring_get_wptr()
129 WREG32(mmGRBM_GFX_INDEX, mmGRBM_GFX_INDEX_DEFAULT); in vce_v3_0_ring_get_wptr()
149 WREG32(mmGRBM_GFX_INDEX, GET_VCE_INSTANCE(0)); in vce_v3_0_ring_set_wptr()
151 WREG32(mmGRBM_GFX_INDEX, GET_VCE_INSTANCE(1)); in vce_v3_0_ring_set_wptr()
154 WREG32(mmVCE_RB_WPTR, lower_32_bits(ring->wptr)); in vce_v3_0_ring_set_wptr()
156 WREG32(mmVCE_RB_WPTR2, lower_32_bits(ring->wptr)); in vce_v3_0_ring_set_wptr()
[all …]
HDgmc_v7_0.c95 WREG32(mmBIF_FB_EN, 0); in gmc_v7_0_mc_stop()
99 WREG32(mmMC_SHARED_BLACKOUT_CNTL, blackout | 1); in gmc_v7_0_mc_stop()
112 WREG32(mmMC_SHARED_BLACKOUT_CNTL, tmp); in gmc_v7_0_mc_resume()
116 WREG32(mmBIF_FB_EN, tmp); in gmc_v7_0_mc_resume()
203 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000008); in gmc_v7_0_mc_load_microcode()
204 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000010); in gmc_v7_0_mc_load_microcode()
208 WREG32(mmMC_SEQ_IO_DEBUG_INDEX, le32_to_cpup(io_mc_regs++)); in gmc_v7_0_mc_load_microcode()
209 WREG32(mmMC_SEQ_IO_DEBUG_DATA, le32_to_cpup(io_mc_regs++)); in gmc_v7_0_mc_load_microcode()
213 WREG32(mmMC_SEQ_SUP_PGM, le32_to_cpup(fw_data++)); in gmc_v7_0_mc_load_microcode()
216 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000008); in gmc_v7_0_mc_load_microcode()
[all …]
HDuvd_v5_0.c87 WREG32(mmUVD_RBC_RB_WPTR, lower_32_bits(ring->wptr)); in uvd_v5_0_ring_set_wptr()
261 WREG32(mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW, in uvd_v5_0_mc_resume()
263 WREG32(mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH, in uvd_v5_0_mc_resume()
268 WREG32(mmUVD_VCPU_CACHE_OFFSET0, offset >> 3); in uvd_v5_0_mc_resume()
269 WREG32(mmUVD_VCPU_CACHE_SIZE0, size); in uvd_v5_0_mc_resume()
273 WREG32(mmUVD_VCPU_CACHE_OFFSET1, offset >> 3); in uvd_v5_0_mc_resume()
274 WREG32(mmUVD_VCPU_CACHE_SIZE1, size); in uvd_v5_0_mc_resume()
279 WREG32(mmUVD_VCPU_CACHE_OFFSET2, offset >> 3); in uvd_v5_0_mc_resume()
280 WREG32(mmUVD_VCPU_CACHE_SIZE2, size); in uvd_v5_0_mc_resume()
282 WREG32(mmUVD_UDEC_ADDR_CONFIG, adev->gfx.config.gb_addr_config); in uvd_v5_0_mc_resume()
[all …]
HDamdgpu_amdkfd_gfx_v9.c282 WREG32(SOC15_REG_OFFSET(GC, 0, mmSH_MEM_CONFIG), sh_mem_config); in kgd_program_sh_mem_settings()
283 WREG32(SOC15_REG_OFFSET(GC, 0, mmSH_MEM_BASES), sh_mem_bases); in kgd_program_sh_mem_settings()
310 WREG32(SOC15_REG_OFFSET(ATHUB, 0, mmATC_VMID0_PASID_MAPPING) + vmid, in kgd_set_pasid_vmid_mapping()
319 WREG32(SOC15_REG_OFFSET(ATHUB, 0, in kgd_set_pasid_vmid_mapping()
324 WREG32(SOC15_REG_OFFSET(OSSSYS, 0, mmIH_VMID_0_LUT) + vmid, in kgd_set_pasid_vmid_mapping()
327 WREG32(SOC15_REG_OFFSET(ATHUB, 0, mmATC_VMID16_PASID_MAPPING) + vmid, in kgd_set_pasid_vmid_mapping()
336 WREG32(SOC15_REG_OFFSET(ATHUB, 0, in kgd_set_pasid_vmid_mapping()
341 WREG32(SOC15_REG_OFFSET(OSSSYS, 0, mmIH_VMID_0_LUT_MM) + vmid, in kgd_set_pasid_vmid_mapping()
361 WREG32(SOC15_REG_OFFSET(GC, 0, mmCPC_INT_CNTL), in kgd_init_interrupts()
426 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_CP_SCHEDULERS), value); in kgd_hqd_load()
[all …]
HDvce_v4_0.c114 WREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_RB_WPTR), in vce_v4_0_ring_set_wptr()
117 WREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_RB_WPTR2), in vce_v4_0_ring_set_wptr()
120 WREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_RB_WPTR3), in vce_v4_0_ring_set_wptr()
163 WREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_MMSCH_VF_CTX_ADDR_LO), lower_32_bits(addr)); in vce_v4_0_mmsch_start()
164 WREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_MMSCH_VF_CTX_ADDR_HI), upper_32_bits(addr)); in vce_v4_0_mmsch_start()
170 WREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_MMSCH_VF_VMID), data); in vce_v4_0_mmsch_start()
173 WREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_MMSCH_VF_CTX_SIZE), size); in vce_v4_0_mmsch_start()
176 WREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_MMSCH_VF_MAILBOX_RESP), 0); in vce_v4_0_mmsch_start()
184 WREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_MMSCH_VF_MAILBOX_HOST), 0x10000001); in vce_v4_0_mmsch_start()
337 WREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_RB_RPTR), lower_32_bits(ring->wptr)); in vce_v4_0_start()
[all …]
HDcik.c81 WREG32(mmPCIE_INDEX, reg); in cik_pcie_rreg()
93 WREG32(mmPCIE_INDEX, reg); in cik_pcie_wreg()
95 WREG32(mmPCIE_DATA, v); in cik_pcie_wreg()
106 WREG32(mmSMC_IND_INDEX_0, (reg)); in cik_smc_rreg()
117 WREG32(mmSMC_IND_INDEX_0, (reg)); in cik_smc_wreg()
118 WREG32(mmSMC_IND_DATA_0, (v)); in cik_smc_wreg()
128 WREG32(mmUVD_CTX_INDEX, ((reg) & 0x1ff)); in cik_uvd_ctx_rreg()
139 WREG32(mmUVD_CTX_INDEX, ((reg) & 0x1ff)); in cik_uvd_ctx_wreg()
140 WREG32(mmUVD_CTX_DATA, (v)); in cik_uvd_ctx_wreg()
150 WREG32(mmDIDT_IND_INDEX, (reg)); in cik_didt_rreg()
[all …]
HDamdgpu_amdkfd_gfx_v8.c201 WREG32(mmSRBM_GFX_CNTL, value); in lock_srbm()
208 WREG32(mmSRBM_GFX_CNTL, 0); in unlock_srbm()
238 WREG32(mmSH_MEM_CONFIG, sh_mem_config); in kgd_program_sh_mem_settings()
239 WREG32(mmSH_MEM_APE1_BASE, sh_mem_ape1_base); in kgd_program_sh_mem_settings()
240 WREG32(mmSH_MEM_APE1_LIMIT, sh_mem_ape1_limit); in kgd_program_sh_mem_settings()
241 WREG32(mmSH_MEM_BASES, sh_mem_bases); in kgd_program_sh_mem_settings()
261 WREG32(mmATC_VMID0_PASID_MAPPING + vmid, pasid_mapping); in kgd_set_pasid_vmid_mapping()
265 WREG32(mmATC_VMID_PASID_MAPPING_UPDATE_STATUS, 1U << vmid); in kgd_set_pasid_vmid_mapping()
268 WREG32(mmIH_VMID_0_LUT + vmid, pasid_mapping); in kgd_set_pasid_vmid_mapping()
284 WREG32(mmCPC_INT_CNTL, CP_INT_CNTL_RING0__TIME_STAMP_INT_ENABLE_MASK); in kgd_init_interrupts()
[all …]

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